LPC43xx_LPC43Sxx User Manual Lpc43xx

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UM10503
LPC43xx/LPC43Sxx ARM Cortex®-M4/M0 multi-core
microcontroller
Rev. 2.4 — 22 August 2018

User manual

Document information
Info

Content

Keywords

LPC43xx, LPC4300, LPC4370, LPC4350, LPC4330, LPC4320, LPC4310,
LPC4357, LPC4353, LPC4337, LPC4333, LPC4327, LPC4325, LPC4323,
LPC4322, LPC4317, LPC4315, LPC4313, LPC4312, LPC43S50, LPC43S30,
LPC43S20, LPC43S37, LPC43S57, LPC43S67, LPC4367, LPC43S70, ARM
Cortex-M4, ARM Cortex-M0, SPIFI, SCTimer/PWM, USB, Ethernet,
LPC4300 user manual, LPC43xx/LPC43Sxx user manual

Abstract

LPC4300/LPC43S00 user manual

UM10503

NXP Semiconductors

LPC43xx/LPC43Sxx User manual

Revision history
Rev

Date

Description

2.4

20180822

LPC43xx/LPC43Sxx User manual

Modifications:

•
•
•
•
•
•
•

2.3
Modifications:

2.2
Modifications:
2.1
Modifications:

2.0

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User manual

Updated Section 1.2 “Features”: Added unique ID for each device to digital peripherals.
Updated Table 33 “ISP command summary”: Changed ISP command: Read device unique ID.
Updated title of Table 47 “ISP Read device unique ID command”: Was serial number, changed to
device unique ID.
Added text to Section 6.7.13 “Read device unique ID”.
Updated title of Table 58 “IAP Read device unique ID command”: Was serial number, changed to
device unique ID.
Added text to Section 6.8.8 “Read device unique ID”.
Added Section 51.8.1 “Description” and Section 51.8.2 “Mitigation”

20170726

LPC43xx/LPC43Sxx User manual

•

Updated Section 13.2.1.1 “Changing the BASE_M4_CLK after power-up, reset, or deep power-down
mode”. Added list item 4.

•

Updated Section 13.2.1.2 “Changing the BASE_M4_CLK after waking up from deep-sleep or
power-down modes”. Added list item 3.

•

Updated Table 128 “PLL0USB control register (PLL0USB_CTRL, address 0x4005 0020) bit
description”. Added table note to AUTOBLOCK, bit 11.

•

Updated Table 132 “PLL0AUDIO control register (PLL0AUDIO_CTRL, address 0x4005 0030) bit
description”. Added table note to AUTOBLOCK, bit 11.

•

Updated Table 137 “PLL1_CTRL register (PLL1_CTRL, address 0x4005 0044) bit description”.
Added table note to AUTOBLOCK, bit 11.

20170525

•
•

LPC43xx/LPC43Sxx User manual

Updated Table 25 “QSPI devices supported by the boot code and the SPIFI API”:
Deleted Table: QSPI devices not supported by the boot code.

20151210

LPC43xx/LPC43Sxx User manual

•

Added CREG1 register. See Table 97 “CREG1 register (CREG1, address 0x4004 3008) bit
description”.

•

Updated text in Section 13.2.1 “Configuring the BASE_M4_CLK for high operating frequencies”: To
ramp up the clock frequency to an operating frequency above 110 MHz configure the core clock
BASE_M4_CLK as described in Section 13.2.1.1.

•

Updated description for USB0 (Event 9) and USB1(Event 10) peripheral in Table 82 “Event router
inputs”; USB0: Wake-up request signal. Not active in power-down and deep power-down mode. Use
for wake-up from sleep and deep-sleep mode; USB1: USB1 AHB_NEED_CLK signal. Not active in
power-down and deep power-down mode. Use for wake up from sleep and deep-sleep mode.

•

Replaced Figure 15 “Boot process flowchart for LPC43xx parts with flash” with a new one.

20151104

LPC43xx/LPC43Sxx User manual

All information provided in this document is subject to legal disclaimers.

Rev. 2.4 — 22 August 2018

© NXP B.V. 2018. All rights reserved.

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LPC43xx/LPC43Sxx User manual

Revision history …continued
Rev
Modifications:

Date

Description

•

Updated keywords in Document information to add LPC436x and LPC 43S6x. See Table “Document
information”.

•

Added text, the Cortex-M0 coprocessor hardware multiply is implemented as a 32-cycle iterative
multiplier in Section 1.1 “Introduction”.

•
•
•
•

Changed the title of each chapter to add LPC43Sxx.
Updated ordering information table to add S parts. See Table 1 “Ordering information”.
Updated ordering options table to add S-parts. See Table 2 “Ordering options”.
Updated on-chip memory (parts with on-chip flash) list item in Section 1.2 “Features”: Upto 154 kB
SRAM for code and data use.

•

Added block diagram of LPC436x/LPC43S6x. See Figure 5 “LPC436x/LPC43S6x block diagram
(parts with on-chip flash, dual-core)”

•
•
•

Updated Table 10 “LPC43xx/LPC43Sxx SRAM configuration” to add LPC436x and LPC43S6x parts.

•
•

Fixed CBC to read Cipher Block Chaining instead of Cipher Book Chaining in Section 8.2 “Features”.

Updated Figure 10 “Parts with on-chip flash: Memory mapping (overview)”.
Added device and hex coding information for S parts to Table 46 “LPC43xx part identification
numbers”.
Updated Section 30.6 “Register description” text. Was REGMODEn = 1: Registers operate as match
and reload registers. REGMODEn = 0: Registers operate as capture and capture control registers. 0
and 1 reversed to read, REGMODEn = 0: Registers operate as match and reload registers.
REGMODEn = 1: Registers operate as capture and capture control registers.

•

Updated Section 31.3 “Register description” text. Was REGMODEn = 1: Registers operate as match
and reload registers. REGMODEn = 0: Registers operate as capture and capture control registers. 0
and 1 reversed to read, REGMODEn = 0: Registers operate as match and reload registers.
REGMODEn = 1: Registers operate as capture and capture control registers.

•

Updated Table 54 “IAP Copy RAM to Flash command”
Param1(SRC): Source internal SRAM address from which data bytes are to be read. This address
should be a word boundary.

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Fixed broken link in Section 11.4.13 “Cortex-M0SUB TXEV event clear register” and Section 11.4.14
“Cortex-M0APP TXEV event clear register”.

•

Added a Remark to Section 25.9.1 “Endpoint queue head (dQH)”: In USB device control case if the
system error occurs, check if the endpoint transfer descriptor are programmed perfectly by software
application during set_configuration request. The system error will occur if the hardware accesses
inaccessible memory space for end point access.

•

Changed the IAP command array size to 5: See Section 6.8 “IAP commands”.
Define data structure or pointers to pass the IAP command table and result table to the IAP function:
unsigned long command[5]; unsigned long result[5];

All information provided in this document is subject to legal disclaimers.

Rev. 2.4 — 22 August 2018

© NXP B.V. 2018. All rights reserved.

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Revision history …continued
Rev

Date

Description

•
•
•

Updated Figure 24 “IAP parameter passing”.

•

Updated Table 1059 “CAN message interface message control registers (IF1_MCTRL, address
0x400E 2038 (C_CAN0) and 0x400A 4038 (C_CAN1)) bit description”: bit descriptions for bit 11 TXIE
is: 0 = The INTPND bit will be left unchanged after a successful transmission of a frame. 1 = INTPND
will be set after a successful transmission of a frame.

•

In Table 118 “Power-down modes register (PD0_SLEEP0_MODE - address 0x4004 201C) bit
description”, the value of Deep power down mode is changed to 0x0033 FF7F.

•

In Table 20 “OTP function allocation”, updated otp_ProgUSBID: otp_ProgUSBID will program prod_id
and vend_id in word 1 of bank 3: 3; word 1.

•

Added a table note to Table 986 “SPI clocking and power control”:

Updated Figure 27 “Boot flow for encrypted images (flashless parts)”.
Removed tge GPCLEAR_ENx bits from the register description. See Table 917 “Event
Monitor/Recorder Control Register (ERCONTRO, address 0x4004 6084) bit description”.

BASE_SPI_CLK  0.5 * BASE_M4_CLK (if interrupt goes to M4 or M0APP).
BASE_SPI_CLK  0.5 * BASE_PERIPH_CLK (if interrupt goes to M0SUB).

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•

In Table 42 “ISP Go command”, updated the address description and example: This address must be
on a word boundary and it is not allowed to add the Thumb bit (bit 0) of the address. The example is
G 436208208 T" branches to address 0x1A00 0250.

•
•

Updated Table 24 “Boot image header description”: Reserved bits: 15: 8 instead of 15:14.

•

Re-named Part ID register to CHIP ID register: Table 96 “Register overview: Configuration registers
(base address 0x4004 3000)” and Table 107 “Chip ID register (CHIPID, address 0x4004 3200) bit
description”. Added CHIP ID for Flash devices Rev A: CHIP ID is 0x7906 002B to Table 107 “Chip ID
register (CHIPID, address 0x4004 3200) bit description”.

•

Added SBUSCFG register. See Table 463 “System bus interface configuration register (SBUSCFG address 0x4000 6090) bit description”. Added a remark in Section 25.6.10 “Burst Size register
(BURSTSIZE)”.

•
•

Updated Figure 32 “AES endianness”.

•

Updated Section 6.4.5.8 “RAM used by IAP command handler”. Added text: 16 B of RAM from
0x10089FF0 to 0x10089FFF. Applications making use of IAP calls must reserve this RAM block.

•

Updated Section 6.4.5.7 “RAM used by ISP”; removed command handler from the title and updated
text.

Updated Table 74 “Boot image header description”: AES_CONTROL bits: 15:8. added a remark
before the table.

Added a bullet to Section 6.2 “Basic configuration”. If the application uses the IAP interface, it must
reserve the SRAM space used by IAP as outlined in Section 6.4.5.8 “RAM used by IAP command
handler”.

All information provided in this document is subject to legal disclaimers.

Rev. 2.4 — 22 August 2018

© NXP B.V. 2018. All rights reserved.

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LPC43xx/LPC43Sxx User manual

Revision history …continued
Rev

Date

Description

1.9

20150218

LPC43xx User manual

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User manual

•
•

Table 777 “SCT configuration example” updated and moved to Chapter 31.

•
•

Section 40.7.5.1 “USART clock in synchronous mode” added.

•

Bit description of bits TSEG1 and TSEG2 corrected in Table 1037 “CAN bit timing register (BT,
address 0x400E 200C (C_CAN0) and 0x400A 400C (C_CAN1)) bit description” and Figure 170 “Bit
timing” updated for clarity.

•

Parts MX1635E, W25Q16DV, W25Q32FV added to Table 25 “QSPI devices supported by the boot
code and the SPIFI API”.

•

Use of IAP calls clarified: IAP commands are not supported for flash-less parts. See Section 6.8 “IAP
commands”.

•

For flashless parts only: Unique part ID is stored in OTP bank 0 and readable at memory locations
0x4004 5000.to 0x4004 500C. See Section 4.1 and Table 14 “OTP memory description (OTP base
address 0x4004 5000)”.

•
•
•

For secure parts only: Chapter 7 “LPC43Sxx Boot ROM for secure parts” added.

•
•

Section 5.1.1 “Determine the boot code version” added.

•
•

IRC accuracy corrected in Section 1.2 “Features”.

Number of EMC_CS and EMC_DYCS pins corrected for the LQFP208 pin package in Table 409
“EMC pinout for different packages”.
Bit 12 changed to 1 for EMC address mapping 256 Mb, 512 Mb, 1 Gb. See Table 433 “Address
mapping”.

For secure parts only: AES DMA request lines added. See Table 100, Table 330, and Table 350.
Boot ROM chapter split into two chapters for secure and non-secure parts. See Chapter 5 “LPC43xx
Boot ROM” and Chapter 7 “LPC43Sxx Boot ROM for secure parts”.
Signal polarity of signals EMC_CKEOUT and EMC_DQMOUT corrected in Table 412 “EMC pin
description”. Both signals are active HIGH.
Added text: The secure boot from USART3 is not supported for LPC43Sxx parts: see Section 5.1,
Section 7.1, Table 21, and Table 22.

All information provided in this document is subject to legal disclaimers.

Rev. 2.4 — 22 August 2018

© NXP B.V. 2018. All rights reserved.

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Revision history …continued
Rev
Modifications:

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Date

•
•
•

Description

Section 1.7 “ARM core features” added.
ARM Cortex-M0 debug features added. See Section 51.3.
Corrected remark for bits MODE3, RFCLK, and FBCLK in Table 447 “SPIFI control register (CTRL,
address 0x4000 3000) bit description”: MODE3, RFCLK, and FBCLK should not all be 1, because in
this case there is no final falling edge on SCK on which to sample the last data bit of the frame.

•
•

RTCX2 TFBGA ball corrected: ball A7 changed to B7.

•

Bit 4 changed from Reserved to SEI in register USBSTS_D and USBSTS_H. See Table 470 and
Table 471.

•

Bit 4 changed from Reserved to SEE in register USBINTR_D and USBINTR_H. See Table 533 and
Table 534.

•

Bit 4 changed from Reserved to SEI register USBSTS_D and USBSTS_H. See Table 531 and
Table 532.

•
•
•

Added Section 25.11, System error.

•
•
•

Updated LPC43xx part identification number for LPC4370FET256 to0x0000 0030. See Table 46.

Bit 4 changed from Reserved to SEE (System Error Enable) register USBINTR_D and USBINTR_H.
See Table 472 and Table 473.

Removed BUS_RST from Table 168.
Updated Figure 8: the area specifying memory range 0x1008A000-0x10092000 is changed to 32 kB
local SRAM (LPC4370/50/30).
Added a remark on how to read the FLADJ register in Section 11.4.15 and Section 11.4.16.
Changed P1_13 from ball D6 to L8, P7_5 from ball C7 to A7, PF_4 from ball L8 to D6, RESET from
ball B7 to C7, RTCX2 moved from ball A7 to B7, and Ball G10 changed from VSS to VDDIO. See
Table 184.

All information provided in this document is subject to legal disclaimers.

Rev. 2.4 — 22 August 2018

© NXP B.V. 2018. All rights reserved.

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Revision history …continued
Rev

Date

Description

1.8

20140128

LPC43xx User manual

Modifications:

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User manual

•
•
•
•
•

Description of the C_CAN CLKDIV register corrected. See Table 1073.

•
•

Condition for the CAN PCLK added: PCLK < 50 MHz. See Section 44.2.

•

SRAM memory location retained in Power-down mode clarified in Section 3.3.5 “Memory retention in
the Power-down modes” and Figure 6 “Flashless parts: System memory map (see Figure 7 for
detailed addresses of all peripherals)”.

•
•
•
•

Section 36.7.1 “Register read procedure” updated for reading the RTC registers after wake-up.

•

Description of the WAKEUP bits expanded in the CCU branch clock configuration and status
registers. See Section 13.5.3 “CCU1/2 branch clock configuration registers” and Section 13.5.4
“CCU1/2 branch clock status registers”.

•

Bit RUN_N added to CCU branch clock status registers. See Section 13.5.3 “CCU1/2 branch clock
configuration registers”.

•

Statement added: Only write to the RTC registers when the 32 kHz oscillator is running. See
Section 36.2. Same for Alarm timer. See Section 35.2.

•

MII availability clarified: Ethernet MII not available on LQFP144 and TFBGA100 parts. See
Section 27.1 “How to read this chapter”.

•

Timer input and output connections clarified in Section 31.2 and Figure 39 “Connections between
GIMA and peripherals”.

•

Section 44.7.5.2 “Calculating the C_CAN bit rate” added.

Priorities of the EMC SDRAM ports added. See Section 22.4.
Table 20 “OTP function allocation” corrected.
Table 12 “OTP bank programming API functions available in ROM” added.
Bit field width of bits LEVEL in the FIFO_STS and bits FIFO_LEVEL in the FIFO_CFG register
changed to 4 bits. See Table 1120 and Table 1121. Description of the FIFO_STS register updated to
explain the use of the LEVEL bits. See Table 1120.
VBUS connection requirement for self-powered USB0 added to Section 24.5.1 “Requirements for
connecting the USB0_VBUS/USB1_VBUS signal”.

RTC_ALARM pin description corrected (Table 871 “RTC pin description”). This pin is not a 1.8 V pin.
Part LPC4350FBD208 removed.
Read-only status bits for EMC clock divider register configuration register added. See Table 161
“CCU1 branch clock configuration register (CLK_M4_EMCDIV_CFG, addresses 0x4005 1478) bit
description”.

All information provided in this document is subject to legal disclaimers.

Rev. 2.4 — 22 August 2018

© NXP B.V. 2018. All rights reserved.

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Revision history …continued
Rev

Date

Description

1.7

20131017

LPC43xx User manual

Modifications:

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User manual

•
•
•

12-bit ADC (ADCHS) for parts LPC4370 added. See Chapter 47.

•

Core M0SUB added for parts LPLC4370. See Chapter 2 “LPC43xx Multi-Core configuration and
Inter-Process Communication (IPC)”, Chapter 12 “LPC43xx Clock Generation Unit (CGU)”,
Chapter 13 “LPC43xx Clock Control Unit (CCU)”, Chapter 10 “LPC43xx Configuration Registers
(CREG)”, Chapter 14 “LPC43xx Reset Generation Unit (RGU)”, and Chapter 3 “LPC43xx Memory
mapping”.

•

Power-down mode with M0SUB SRAM maintained added for parts LPC4370. See Chapter 11
“LPC43xx Power Management Controller (PMC)” and Table 115.

•
•

AES speed corrected.

•
•
•
•
•

Description of the RESET pin updated in Section 15.2 “Pin description”.

•
•
•
•
•

Table 200 “SD/MMC delay register (SDDELAY, address 0x4008 6D80) bit description” added.

Table “LPC43xx part identification numbers” updated.
BASE_APLL_CLK renamed to BASE_AUDIO_CLK in Chapter 12 “LPC43xx Clock Generation Unit
(CGU)”, Chapter 13 “LPC43xx Clock Control Unit (CCU)”, Chapter 10 “LPC43xx Configuration
Registers (CREG)”, and Chapter 43 “LPC43xx I2S interface”.

Bit description of register CREG5 corrected. Bits 9:0 changed to reserved. Use bits 12:10 for
disabling JTAG. See Section 10.4.3 “CREG5 control register”.
Use of EMC_CLK pins clarified for SDRAM devices. See Section 22.2.
Pin description of the RESET pin updated.
Pin description of pins SD_VOLTD[2:0] updated.
Add bits 20 (BOD reset) and 21 (reset after wake-up from deep power-down) to the event router
registers.
USB driver code listing corrected. See Section 26.5 “USB API”.
Register RESET_EXT_STAT4 removed.
SDRAM address mappings added.
Device MX25L6435EM2I-10G added to Table 24 “QSPI devices supported by the boot code and the
SPIFI API”.

•
•

Table 4 “Ordering options” corrected. ULPI not available on 144-pin and 100-pin packages.

•

Editorial edits to Chapter 7 “LPC43xx Security API”. Section “CMAC using AES hardware
acceleration” removed.

•
•

VADC replaced by ADCHS throughout the document.

•

Figures and tables in Section 43.7.2 “I2S operating modes” corrected.

Editorial updates to Section 5.3.5 “Boot image creation” and Figure 16 “Image encryption flow”
added.

Section 12.2.1 “Configuring the BASE_M4_CLK for high operating frequencies” corrected to ensure
safe operation of the clock ramping procedure.

All information provided in this document is subject to legal disclaimers.

Rev. 2.4 — 22 August 2018

© NXP B.V. 2018. All rights reserved.

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Revision history …continued
Rev
Modifications:

1.6
Modifications:

UM10503

User manual

Date

Description

•

LPC4320 and LPC4310 part IDs corrected. See Table 45 “LPC43xx part identification numbers” and
the LPC4350/30/20/10 errata sheet.

•
•
•
•
•
•
•
•

Description of word1 of the part id corrected. See Table 45 “LPC43xx part identification numbers”.

•
•
•
•
•

Security features updates. FIPS compliancy added.

General description of the OTP updated.
General description of the AES updated.
Figure 14 “Boot process for parts without flash” updated.
Figure 115 “Repetitive Interrupt Timer (RIT) block diagram” corrected.
Details about encryption of the image header added in Section 5.3.4 “Boot image header format”.
Figure 14 “Boot process for parts without flash” corrected. SPI(SSP) boot requires image header.
Bit description of Table 378 “Debounce Count Register (DEBNCE, address 0x4000 4064) bit
description” updated. Host clock is the SD_CLK clock.
ISP mode added to Figure 14 “Boot process for parts without flash”.
Reset values of the EEPROM RWSTATE and WSTATE registers updated.
AES API function offsets corrected.
Part MX25L8006EM2L-12GMX25L8035E, MX25L1633E, MX25L3235E, MX25L6435E,
MX25L12835F, MX25L25635F added to list of devices supported for SPIFI boot.

20130125

LPC43xx user manual.

•
•
•
•

SGPIO-DMA connections clarified.

•
•

Section “Supported QSPI devices” moved to Chapter “LPC43xx Boot ROM”.

•

Bit description of Table “CAN error counter (EC, address 0x400E 2008 (C_CAN0) and 0x400A 4008
(C_CAN1)) bit description” corrected.

•

Bit clock calculation and bit description corrected in Section “CAN bit timing register”.

SGPIO location corrected.
SGPIO added to DMA master 0.
GPIO group interrupt wake-up from power-down modes corrected. Only wake-up from sleep mode
supported.
SPIFI register map and register descriptions added in Chapter “LPC43xx SPI Flash Interface
(SPIFI)”.

All information provided in this document is subject to legal disclaimers.

Rev. 2.4 — 22 August 2018

© NXP B.V. 2018. All rights reserved.

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Chapter :

Revision history …continued
Rev

Date

Description

1.5

20121203

LPC43xx user manual.

Modifications

•

Statement regarding the connection between sampling pin P2_7 and the watchdog timer overflow bit
is incorrect and was removed in Section “Sampling of pin P2_7” and Figure “Boot process flowchart
for LPC43xx parts with flash”.

•
•
•
•

SCT alias register locations corrected.

•
•
•
•
•
•
•
•
•
•
•

Section “MAC Frame filter register” updated to include hash filter option.

IRC accuracy corrected for flash-based parts.
SCT with dither engine added for flash-based parts.
SGPIO DMA connections added in Table “DMA mux control register (DMAMUX, address 0x4004
311C) bit description”.
Section “Hash filter” with examples added.
Description of the I2C MASK register clarified.
Description of the I2C slave address updated.
UART1 TER register location and bit description corrected.
Polarity of the DMACSYNC bit in the GPDMA SYNC register corrected.
SGPIO pattern match example corrected.
OTP API function table corrected. Location 0x1C is reserved.
SPIFI data rate and maximum clock corrected to SPIFI_CLK = 104 MHz and 52 MB/s.
Parts LPC433x, LPC432x, and LPC431x added.
The following changes were made on the TFBGA180 pinout:
– P1_13 moved from ball D6 to L8.
– P7_5 moved from ball C7 to A7.
– PF_4 moved from ball L8 to D6.
– RESET moved from ball B7 to C7.
– RTCX2 moved from ball A7 to B7.
– Ball G10 changed from VSS to VDDIO.

UM10503

User manual

•
•

Section “JTAG TAP Identification” updated.

•

Dual-core power-down modes added to Chapter “LPC43xx Power Management Controller (PMC)”.

EMC Configuration register, bit 8 changed to reserved. See Table “EMC Configuration register
(CONFIG - address 0x4000 5008) bit description”.

All information provided in this document is subject to legal disclaimers.

Rev. 2.4 — 22 August 2018

© NXP B.V. 2018. All rights reserved.

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Chapter :

Revision history …continued
Rev
Modifications:

1.4
Modifications:

UM10503

User manual

Date

Description

•
•

ETM time stamping feature not implemented.

•

Micron part N25Q256 removed from the list of devices supported by the SPIFI boot ROM driver and
API. (See Table “QSPI devices not supported by the boot code”.)

•
•
•
•

Part S25FL129P0XNFI01 added to the list of devices supported by the SPIFI boot ROM driver.

•

Description of the Alarm timer PRESETVAL bit updated in Table “Preset value register (PRESET 0x4004 0004) bit description”.

•

Description of ADC pins on digital/analog input pins changed. Each input to the ADC is connected to
ADC0 and ADC1.

•

Description of extra status bits added to Table “DMA Status register (DMA_STAT, address 0x4001
1014) bit description”.

•
•

Use of lower SPIFI memory clarified in Table “SPIFI flash memory map”.

•
•

Pseudo-code for PLL registers updated by code snippets from LPC43xx sample code.

Bit 0 in the RGU RESET_STATUS0 register changed to reserved. Section “Determine the cause of a
core reset” added.

SGPIO register descriptions for CTRL_ENABLED and CTRL_DISABLED registers updated.
Section “Dynamic Memory Refresh Timer register” register description updated.
Description of the Motor control PWM INVDC bit updated in Table “MCPWM Control read address
(CON - 0x400A 0000) bit description”.

Description of DAC DMA_ENA bit clarified in Table “D/A Control register (CTRL - address
0x400E 1004) bit description”.
Reset delay clock cycles explained in Section “RGU reset control register”.

20120903

LPC43xx user manual.

•

SSP0 boot pin functions corrected. Pin P3_3 = SSP0_SCK, pin P3_6 = SSP0_SSEL, pin P3_7 =
SSP0_MISO, pin P3_8 = SSP0_MOSI.

•

CLKMODE3 removed from the SCT. Bit value CLKMODE = 0x3 changed to reserved “SCT
configuration register (CONFIG - address 0x4000 0000) bit description”.

•
•
•
•
•
•
•
•
•
•
•
•
•

SWD mode removed for ARM Cortex-M0.
Details for GIMA clock synchronization added.
RESET_EXT_STATUS0 register removed.
Reset value of BASE_SAFE_CLK register changed to R (read-only).
Reset delay values corrected in Figure “RGU Reset structure”.
RGU reset values corrected in Table “Register overview: RGU (base address: 0x4005 3000)”.
Editorial updates in Chapter “LPC43xx Serial GPIO (SGPIO)”.
POR reset value of the event router STATUS register corrected.
USB boot mode updated: 12 MHz external crystal required.
IAP invoke call entry pointer clarified.
EMC memory data and control lines clarified for the LQFP208 package.
Figure updated to include boot process for AES capable parts.
Editorial updates.

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LPC43xx/LPC43Sxx User manual

Revision history …continued
Rev

Date

Description

1.3

20120706

LPC43xx user manual.

Modifications:

1.2
Modifications:

1.1
Modifications:

UM10503

User manual

•

Description of USB CDC device class updated in Section “USBD_API_INIT_PARAM” and
“USBD_CDC_API”.

•
•
•
•
•
•

Section “Susp_CTRL module” added for USB1.
Section “USB power optimization” updated.
Table “Boot image header use” added.
AES only available for LPC43Sxx parts.
Bank, Row, Column addressing for SDRAM devices added.
Parts LPC4337 and LPC4333 added.

20120608

•
•
•
•
•
•
•
•
•
•

Syncflash removed
Parameter tb updated.
Parameters for ISP/IAP command “Copy RAM to flash” updated.
Part IDs updated; also see Errata note ES_LPC43X0_A.
Description of CTRL_DISABLE register updated.
Table “SGPIO multiplexer” corrected.
Flash accelerator register waitstate values added.
Programming procedure for the SDRAM mode register added.
Clock ramp-up procedures for core clock added.
Description of the event router updated.

20120510

•
•
•
•
•
•
•
•
•
•
•
•
•
•
•

LPC43xx user manual.

LPC43xx user manual.

Reset value of the ETB bit in the ETBCFG register changed to one.
UART1 FIFOLVL register removed.
Chapter “LPC43xx flash programming/ISP and IAP” added.
OTP memory bank 0 changed to reserved.
Hardware IP checksum feature removed from ethernet block.
USB frame length adjust register added (for parts with on-chip flash only).
Flash accelerator control registers added (for parts with on-chip flash only).
Support for SAMPLE pin added to the CREG0 register.
Chapter “LPC43xx EEPROM memory” added (for parts with on-chip flash only).
SDRAM low-power mode removed in Chapter 21.
Motor control PWM hardware noise filtering removed.
Description of the QEI register VEL corrected.
Chapter “LPC43xx I2S interface” updated.
Remove condition RTC_ALARM = LOW on reset for entering debug mode.
Ethernet chapter updated: PPS and auxiliary timestamp features removed.

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Rev. 2.4 — 22 August 2018

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NXP Semiconductors

LPC43xx/LPC43Sxx User manual

Revision history …continued
Rev
Modifications:

1

Date

Description

•
•
•
•
•
•
•
•
•
•
•
•
•
•
•

Chapter 36 “LPC43xx Event monitor/recorder” added (for parts with on-chip flash only).

•

LQFP100 package removed.

Connection of USB0_VBUS/USB1_VBUS signals added.
Description of ADC GDR register updated.
Pin reset states updated.
SCT register map updated in Table 645.
Changed maximum clock frequency for SWD and ETB access to 120 MHz.
Reduced and normal power modes removed.
AES encryption option added (parts LPC43Sxx only).
SGPIO register names and descriptions updated.
Update description of bit 0 in the USBSTS_D and bit 5:0 in ENDPTCOMPLETE registers of USB0/1.
Update procedure “Setup packet handling using the trip wire mechanism”.
Polarity of bit OUTSEL in the SCT EVCTRL register swapped.
Bit 9 (JTAG enable for the M0 co-processor) added to the CREG5 register.
Description of CCU Auto mode updated.
Maximum power consumption in the USB Suspended state corrected according to USB 2.0 ECN
specification.

20111212

Preliminary LPC43xx user manual.

Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
UM10503

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UM10503
Chapter 1: Introductory information
Rev. 2.4 — 22 August 2018

User manual

1.1 Introduction
The LPC43xx/LPC43Sxx are ARM Cortex-M4 based microcontrollers for embedded
applications which include an ARM Cortex-M0 coprocessor, up to 1 MB of flash, up to 264
kB of SRAM, advanced configurable peripherals such as the State Configurable Timer
(SCTimer/PWM) and the Serial General Purpose I/O (SGPIO) interface, two High-speed
USB controllers, Ethernet, LCD, an external memory controller, and multiple digital and
analog peripherals. The LPC43xx/LPC43Sxx operate at CPU frequencies of up to 204
MHz.
The ARM Cortex-M4 is a next generation 32-bit core that offers system enhancements
such as low power consumption, enhanced debug features, and a high level of support
block integration. The ARM Cortex-M4 CPU incorporates a 3-stage pipeline, uses a
Harvard architecture with separate local instruction and data buses as well as a third bus
for peripherals, and includes an internal prefetch unit that supports speculative branching.
The ARM Cortex-M4 supports single-cycle digital signal processing and SIMD
instructions. A hardware floating-point processor is integrated in the core.
The LPC43xx/LPC43Sxx contain one or two ARM Cortex-M0 processors to share
computing tasks with the main ARM Cortex-M4 processor. All processors can serve
peripherals.
The ARM Cortex-M0 coprocessor is an energy-efficient and easy-to-use 32-bit core which
is code- and tool-compatible with the Cortex-M4 core. The Cortex-M0 coprocessor,
designed as a replacement for existing 8/16-bit microcontrollers, offers up to 204 MHz
performance with a simple instruction set and reduced code size. In LPC43xx/LPC43Sxx,
the Cortex-M0 coprocessor hardware multiply is implemented as a 32-cycle iterative
multiplier.
See Section 54.2 “References” for related documentation.

1.2 Features
• Cortex-M4 Processor core
– ARM Cortex-M4 processor (version r0p1), running at frequencies of up to
204 MHz.
– ARM Cortex-M4 built-in Memory Protection Unit (MPU) supporting eight regions.
– ARM Cortex-M4 built-in Nested Vectored Interrupt Controller (NVIC).
– Hardware floating-point unit.
– Non-maskable Interrupt (NMI) input.
– JTAG and Serial Wire Debug (SWD), serial trace, eight breakpoints, and four
watch points.
– Enhanced Trace Module (ETM) and Enhanced Trace Buffer (ETB) support.
– System tick timer.

• Cortex-M0 Processor core (all LPC43xx/LPC43Sxx parts)
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NXP Semiconductors

Chapter 1: Introductory information

– ARM Cortex-M0 processor (version r0p0) capable of off-loading the main ARM
Cortex-M4 processor.
– Running at frequencies of up to 204 MHz.
– JTAG and built-in NVIC.

• Cortex-M0 Processor subsystem core (LPC437x/LPC43S7x and
LPC436x/LPC43S6x parts only)
– ARM Cortex-M0 processor (version r0p0) controlling the SPI and SGPIO
peripherals residing on a separate AHB multilayer matrix with direct access to 2 kB
+ 16 kB of SRAM.
– Connected via a core-to-core bridge to the main AHB multilayer matrix and the
main ARM Cortex-M4 processor.
– Running at frequencies of up to 204 MHz.
– JTAG and built-in NVIC.

• On-chip memory (flashless parts)
– Up to 264 kB SRAM for code and data use.
– Additional 18 kB of SRAM for direct access by the M0 subsystem core
(LPC437x/LPC43S7x and LPC436x/LPC43S6x parts only).
– Multiple SRAM blocks with separate bus access. Two SRAM blocks can be
powered down individually.
– 64 kB ROM containing boot code and on-chip software drivers.
– General-purpose One-Time Programmable (OTP) memory.

• On-chip memory (parts with on-chip flash)
– Up to 1 MB on-chip dual bank flash memory with flash accelerator.
– 16 kB on-chip EEPROM data memory.
– Upto 154 kB SRAM for code and data use.
– Multiple SRAM blocks with separate bus access. Two SRAM blocks can be
powered down individually.
– 64 kB ROM containing boot code and on-chip software drivers.
– General-purpose One-Time Programmable (OTP) memory.

• Configurable digital peripherals
– Serial GPIO (SGPIO) interface.
– State Configurable Timer (SCTimer/PWM) subsystem on AHB.
– Global Input Multiplexer Array (GIMA) allows to cross-connect multiple inputs and
outputs to event driven peripherals like the timers, SCTimer/PWM, and ADC0/1.

• Serial interfaces
– Quad SPI Flash Interface (SPIFI) with 1-, 2-, or 4-bit data at rates of up to 52 MB
per second.
– 10/100T Ethernet MAC with RMII and MII interfaces and DMA support for high
throughput at low CPU load. Support for IEEE 1588 time stamping and advanced
time stamping (IEEE 1588-2008 v2).

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NXP Semiconductors

Chapter 1: Introductory information

– One High-speed USB 2.0 Host/Device/OTG interface with DMA support and
on-chip high-speed PHY.
– One High-speed USB 2.0 Host/Device interface with DMA support, on-chip
full-speed PHY and ULPI interface to external high-speed PHY.
– USB interface electrical test software included in ROM USB stack.
– One 550 UART with DMA support and full modem interface.
– Three 550 USARTs with DMA and synchronous mode support and a smart card
interface conforming to ISO7816 specification. One USART with IrDA interface.
– Two C_CAN 2.0B controllers with one channel each. Use of C_CAN controller
excludes operation of all other peripherals connected to the same bus bridge.
– Two SSP controllers with FIFO and multi-protocol support. Both SSPs with DMA
support.
– One SPI controller.
– One Fast-mode Plus I2C-bus interface with monitor mode and with open-drain I/O
pins conforming to the full I2C-bus specification. Supports data rates of up to
1 Mbit/s.
– One standard I2C-bus interface with monitor mode and with standard I/O pins.
– Two I2S interfaces, each with DMA support and with one input and one output.

• Digital peripherals
– External Memory Controller (EMC) supporting external SRAM, ROM, NOR flash,
and SDRAM devices.
– LCD controller with DMA support and a programmable display resolution of up to
1024H  768V. Supports monochrome and color STN panels and TFT color
panels; supports 1/2/4/8 bpp Color Look-Up Table (CLUT) and 16/24-bit direct pixel
mapping.
– Secure Digital Input Output (SD/MMC) card interface.
– Eight-channel General-Purpose DMA (GPDMA) controller can access all
memories on the AHB and all DMA-capable AHB slaves.
– Up to 164 General-Purpose Input/Output (GPIO) pins with configurable
pull-up/pull-down resistors.
– GPIO registers are located on the AHB for fast access. GPIO ports have DMA
support.
– Up to eight GPIO pins can be selected from all GPIO pins as edge and level
sensitive interrupt sources.
– Two GPIO group interrupt modules enable an interrupt based on a programmable
pattern of input states of a group of GPIO pins.
– Four general-purpose timer/counters with capture and match capabilities.
– One motor control Pulse Width Modulator (PWM) for three-phase motor control.
– One Quadrature Encoder Interface (QEI).
– Repetitive Interrupt timer (RI timer).
– Windowed watchdog timer (WWDT).
– Ultra-low power Real-Time Clock (RTC) on separate power domain with 256 bytes
of battery powered backup registers.
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NXP Semiconductors

Chapter 1: Introductory information

– (Parts with on-chip flash only): Event recorder with three inputs to record event
identification and event time; can be battery powered.
– Alarm timer; can be battery powered.
– Unique ID for each device.

• Analog peripherals
– One 10-bit DAC with DMA support and a data conversion rate of 400 kSamples/s.
– Two 10-bit ADCs with DMA support and a data conversion rate of 400 kSamples/s.
Up to eight input channels per ADC.
– One 6-channel, 12-bit high-speed ADC (ADCHS) with DMA support and a data
conversion rate of 80 MSamples/s (LPC4370 only).

• Security (LPC43Sxx only)
– AES decryption programmable through an on-chip API.
– Two 128-bit secure OTP memories for AES key storage and customer use.
– Random number generator (RNG) accessible through AES API.

• Clock generation unit
– Crystal oscillator with an operating range of 1 MHz to 25 MHz.
– 12 MHz Internal RC (IRC) oscillator trimmed to 1.5 % (flashless parts) or 3 %
(flash-based parts) accuracy over full temperature range and voltage.
– Ultra-low power Real-Time Clock (RTC) crystal oscillator.
– Three PLLs allow CPU operation up to the maximum CPU rate without the need for
a high-frequency crystal. The second PLL is dedicated to the High-speed USB, the
third PLL can be used as audio PLL.
– Clock output.

• Power
– Single 3.3 V (2.2 V to 3.6 V) power supply with on-chip DC-to-DC converter for the
core supply and the RTC power domain.
– RTC power domain can be powered separately by a 3 V battery supply.
– Four reduced power modes: Sleep, Deep-sleep, Power-down, and Deep
power-down.
– Processor wake-up from Sleep mode via wake-up interrupts from various
peripherals.
– Wake-up from Deep-sleep, Power-down, and Deep power-down modes via
external interrupts and interrupts generated by battery powered blocks in the RTC
power domain.
– Brownout detect with four separate thresholds for interrupt and forced reset.
– Power-On Reset (POR).
– Available as LBGA256, TFBGA180, and TFBGA100 packages and as LQFP208
and LQFP144 packages.

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UM10503

NXP Semiconductors

Chapter 1: Introductory information

1.3 Ordering information (flashless parts)
Table 1.

Ordering information

Type number

Package
Name

Description

Version

Plastic low profile ball grid array package; 256 balls; body 17  17  1 mm

SOT740-2

LPC4370FET256

LBGA256

LPC4370FET100

TFBGA100 Plastic thin fine-pitch ball grid array package; 100 balls; body 9  9  0.7 mm SOT926-1

LPC4350FET256

LBGA256

LPC4350FET180

TFBGA180 Thin fine-pitch ball grid array package; 180 balls

Plastic low profile ball grid array package; 256 balls; body 17  17  1 mm

SOT740-2
SOT570-3

Plastic low profile ball grid array package; 256 balls; body 17  17  1 mm

LPC4330FET256

LBGA256

LPC4330FET180

TFBGA180 Thin fine-pitch ball grid array package; 180 balls

SOT740-2

LPC4330FET100

TFBGA100 Plastic thin fine-pitch ball grid array package; 100 balls; body 9  9  0.7 mm SOT926-1

LPC4330FBD144

LQFP144

LPC4320FET100

TFBGA100 Plastic thin fine-pitch ball grid array package; 100 balls; body 9  9  0.7 mm SOT926-1

LPC4320FBD144

LQFP144

LPC4310FET100

TFBGA100 Plastic thin fine-pitch ball grid array package; 100 balls; body 9  9  0.7 mm SOT926-1

LPC4310FBD144

LQFP144

Plastic low profile quad flat package; 144 leads; body 20  20  1.4 mm

SOT486-1

LPC43S70FET256

LBGA256

Plastic low profile ball grid array package; 256 balls; body17  17  1 mm

SOT740-2

LPC43S70FET100

TFBGA100 Plastic thin fine-pitch ball grid array package; 100 balls; body 9  9  0.7 mm SOT926-1

LPC43S50FET256

LBGA256

LPC43S50FET180

TFBGA180 Thin fine-pitch ball grid array package; 180 balls

SOT570-3

Plastic low profile quad flat package; 144 leads; body 20  20  1.4 mm
Plastic low profile quad flat package; 144 leads; body 20  20  1.4 mm

Plastic low profile ball grid array package; 256 balls; body 17  17  1 mm

SOT486-1
SOT486-1

SOT740-2
SOT570-3

Plastic low profile ball grid array package; 256 balls; body 17  17  1 mm

LPC43S30FET256

LBGA256

LPC43S30FET100

TFBGA100 Plastic thin fine-pitch ball grid array package; 100 balls; body 9  9  0.7 mm SOT926-1

SOT740-2

LPC43S30FBD144 LQFP144

Plastic low profile quad flat package; 144 leads; body 20  20  1.4 mm

SOT486-1

LPC43S20FBD144 LQFP144

Plastic low profile quad flat package; 144 leads; body 20  20  1.4 mm

SOT486-1

LPC43S20FET180
Table 2.

TFBGA180 Thin fine-pitch ball grid array package; 180 balls

SOT570-3

Ordering options

Type number

Total
SRAM

Cores

LCD

Ethernet

USB0
(Host,
Device,
OTG)

USB1
(Host,
Device)/
ULPI
interface

10-bit
ADC
channels

12-bit
ADC
channels
(ADCHS)

GPIO

LPC4370FET256

282 kB

M4/M0/M0

yes

yes

yes

yes/yes

8 (ADC0)/
8 (ADC1)

6

164

LPC4370FET100

282 kB

M4/M0/M0

no

yes

yes

no

n/a

3

49

LPC4350FET256

264 kB

M4/M0

yes

yes

yes

yes/yes

8

n/a

164

LPC4350FET180

264 kB

M4/M0

yes

yes

yes

yes/yes

8

n/a

118

LPC4330FET256

264 kB

M4/M0

no

yes

yes

yes/yes

8

n/a

164

LPC4330FET180

264 kB

M4/M0

no

yes

yes

yes/yes

8

n/a

118

LPC4330FET100

264 kB

M4/M0

no

yes

yes

yes/no

4

n/a

49

LPC4330FBD144

264 kB

M4/M0

no

yes

yes

yes/no

8

n/a

83

LPC4320FET100

200 kB

M4/M0

no

no

yes

no

4

n/a

49

LPC4320FBD144

200 kB

M4/M0

no

no

yes

no

8

n/a

83

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UM10503

NXP Semiconductors

Chapter 1: Introductory information

Table 2.

Ordering options

Type number

Total
SRAM

Cores

LCD

Ethernet

USB0
(Host,
Device,
OTG)

USB1
(Host,
Device)/
ULPI
interface

10-bit
ADC
channels

12-bit
ADC
channels
(ADCHS)

GPIO

LPC4310FET100

168 kB

M4/M0

no

no

no

no

4

n/a

49

LPC4310FBD144

168 kB

M4/M0

no

no

no

no

8

n/a

83

LPC43S70FET256

282 kB

M4/M0/M0

yes

yes

yes

yes/yes

8 (ADC0)/
8 (ADC1)

6

164

LPC43S70FET100

282 kB

M4/M0/M0

no

yes

yes

no

n/a

3

49

LPC43S50FET256

264 kB

M4/M0

yes

yes

yes

yes/yes

8

n/a

164

LPC43S50FET180

264 kB

M4/M0

yes

yes

yes

yes/yes

8

n/a

118

LPC43S30FET256

264 kB

M4/M0

no

yes

yes

yes/yes

8

n/a

164

LPC43S30FET100

264 kB

M4/M0

no

yes

yes

yes/no

4

n/a

49

LPC43S30FBD144

264 kB

M4/M0

no

yes

yes

yes/no

8

n/a

83

LPC43S20FBD144

200 kB

M4/M0

no

no

yes

no

8

n/a

83

LPC43S20FET180

200 kB



no

no

yes

no

8



118

1.4 Ordering information (parts with on-chip flash)
Table 3.

Ordering information

Type number

Package
Name

Description

Version

LBGA256

Plastic low profile ball grid array package; 256 balls; body 17  17  1 mm

SOT740-2

LPC4367JBD208

LQFP208

Plastic low profile quad flat package; 208 leads; body 28  28  1.4 mm

SOT459-1

LPC4367JET100

TFBGA100 Plastic thin fine-pitch ball grid array package; 100 balls; body 9  9  0.7 mm SOT926-1

LPC4357FET256

LBGA256

Plastic low profile ball grid array package; 256 balls; body 17  17  1 mm

SOT740-2

LPC4357JET256

LBGA256

Plastic low profile ball grid array package; 256 balls; body 17  17  1 mm

SOT740-2

LPC4357JBD208

LQFP208

Plastic low profile quad flat package; 208 leads; body 28  28  1.4 mm

SOT459-1

LPC4353FET256

LBGA256

Plastic low profile ball grid array package; 256 balls; body 17  17  1 mm

SOT740-2

LPC4353JET256

LBGA256

Plastic low profile ball grid array package; 256 balls; body 17  17  1 mm

SOT740-2

LPC4353JBD208

LQFP208

Plastic low profile quad flat package; 208 leads; body 28  28  1.4 mm

SOT459-1

LPC4367JET256

LPC4337FET256

LBGA256

Plastic low profile ball grid array package; 256 balls; body 17  17  1 mm

SOT740-2

LPC4337JET256

LBGA256

Plastic low profile ball grid array package; 256 balls; body 17  17  1 mm

SOT740-2

LPC4337JBD144

LQFP144

Plastic low profile quad flat package; 144 leads; body 20  20  1.4 mm

SOT486-1

LPC4337JET100

TFBGA100 Plastic thin fine-pitch ball grid array package; 100 balls; body 9  9  0.7 mm SOT926-1

LPC4333FET256

LBGA256

Plastic low profile ball grid array package; 256 balls; body 17  17  1 mm

SOT740-2

LPC4333JET256

LBGA256

Plastic low profile ball grid array package; 256 balls; body 17  17  1 mm

SOT740-2

LPC4333JBD144

LQFP144

Plastic low profile quad flat package; 144 leads; body 20  20  1.4 mm

SOT486-1

LPC4333JET100

TFBGA100 Plastic thin fine-pitch ball grid array package; 100 balls; body 9  9  0.7 mm SOT926-1
Plastic low profile quad flat package; 144 leads; body 20  20  1.4 mm

LPC4327JBD144

LQFP144

LPC4327JET100

TFBGA100 Plastic thin fine-pitch ball grid array package; 100 balls; body 9  9  0.7 mm SOT926-1

LPC4325JBD144

LQFP144

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User manual

Plastic low profile quad flat package; 144 leads; body 20  20  1.4 mm
All information provided in this document is subject to legal disclaimers.

Rev. 2.4 — 22 August 2018

SOT486-1
SOT486-1

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UM10503

NXP Semiconductors

Chapter 1: Introductory information

Table 3.

Ordering information …continued

Type number

Package
Name

LPC4325JET100

Description

Version

TFBGA100 Plastic thin fine-pitch ball grid array package; 100 balls; body 9  9  0.7 mm SOT926-1
Plastic low profile quad flat package; 144 leads; body 20  20  1.4 mm

LPC4323JBD144

LQFP144

LPC4323JET100

TFBGA100 Plastic thin fine-pitch ball grid array package; 100 balls; body 9  9  0.7 mm SOT926-1

SOT486-1

LPC4322JBD144

LQFP144

LPC4322JET100

TFBGA100 Plastic thin fine-pitch ball grid array package; 100 balls; body 9  9  0.7 mm SOT926-1

Plastic low profile quad flat package; 144 leads; body 20  20  1.4 mm

SOT486-1

Plastic low profile quad flat package; 144 leads; body 20  20  1.4 mm

LPC4317JBD144

LQFP144

LPC4317JET100

TFBGA100 Plastic thin fine-pitch ball grid array package; 100 balls; body 9  9  0.7 mm SOT926-1

SOT486-1

LPC4315JBD144

LQFP144

LPC4315JET100

TFBGA100 Plastic thin fine-pitch ball grid array package; 100 balls; body 9  9  0.7 mm SOT926-1

Plastic low profile quad flat package; 144 leads; body 20  20  1.4 mm

SOT486-1

Plastic low profile quad flat package; 144 leads; body 20  20  1.4 mm

LPC4313JBD144

LQFP144

LPC4313JET100

TFBGA100 Plastic thin fine-pitch ball grid array package; 100 balls; body 9  9  0.7 mm SOT926-1

SOT486-1

LPC4312JBD144

LQFP144

LPC4312JET100

TFBGA100 Plastic thin fine-pitch ball grid array package; 100 balls; body 9  9  0.7 mm SOT926-1

Plastic low profile quad flat package; 144 leads; body 20  20  1.4 mm

SOT486-1

LPC43S67JET256 LBGA256

Plastic low profile ball grid array package; 256 balls; body 17  17  1 mm

SOT740-2

LPC43S67JBD208 LQFP208

Plastic low profile quad flat package; 208 leads; body 28  28  1.4 mm

SOT459-1

LPC43S67JET100 TFBGA100 Plastic thin fine-pitch ball grid array package; 100 balls; body 9  9  0.7 mm SOT926-1
LPC43S57JET256 LBGA256

Plastic low profile ball grid array package; 256 balls; body 17  17  1 mm

LPC43S57JBD208 LQFP208

Plastic low profile quad flat package; 208 leads; body 28  28  1.4 mm

SOT459-1

LPC43S37JBD144 LQFP144

Plastic low profile quad flat package; 144 leads; body 20  20  1.4 mm

SOT486-1

SOT740-2

LPC43S37JET100 TFBGA100 Plastic thin fine-pitch ball grid array package; 100 balls; body 9  9  0.7 mm SOT926-1

Flash bank A

Flash bank B

Total SRAM

LCD

Ethernet

USB0 (Host, Device, OTG)

USB1 (Host, Device)/
ULPI interface

QEI

ADC channels

Temperature range[1]

GPIO

LPC4367JET256

1 MB

512 kB

512 kB

154 kB

yes

yes

yes

yes/yes yes

yes

8

J

164

LPC4367JBD208

1 MB

512 kB

512 kB

154 kB

yes

yes

yes

yes/yes yes

yes

8

J

142

LPC4367JET100

1 MB

512 kB

512 kB

154 kB

yes

yes

yes

yes/yes yes

yes

8

J

49

LPC4357FET256

1 MB

512 kB

512 kB

136 kB

yes

yes

yes

yes/yes yes

yes

8

F

164

LPC4357JET256

1 MB

512 kB

512 kB

136 kB

yes

yes

yes

yes/yes yes

yes

8

J

164

LPC4357JBD208

1 MB

512 kB

512 kB

136 kB

yes

yes

yes

yes/yes yes

yes

8

J

142

LPC4353FET256

512 kB 256 kB

256 kB

136 kB

yes

yes

yes

yes/yes yes

yes

8

F

164

LPC4353JET256

512 kB 256 kB

256 kB

136 kB

yes

yes

yes

yes/yes yes

yes

8

J

164

LPC4353JBD208

512 kB 256 kB

256 kB

136 kB

yes

yes

yes

yes/yes yes

yes

8

J

142

LPC4337FET256

1 MB

512 kB

136 kB

no

yes

yes

yes/yes yes

yes

8

F

164

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PWM

Flash total

Ordering options

Type number

Table 4.

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UM10503

NXP Semiconductors

Chapter 1: Introductory information

Ordering options

ADC channels

Temperature range[1]

GPIO

yes

yes/yes yes

yes

8

J

164

yes

yes

yes/no

yes

no

8

J

83

LPC4337JET100

1 MB

512 kB

512 kB

136 kB

no

yes

yes

yes/no

no

no

4

J

49

LPC4333FET256

512 kB 256 kB

256 kB

136 kB

no

yes

yes

yes/yes yes

yes

8

F

164

Flash total

PWM

yes

no

USB1 (Host, Device)/
ULPI interface

no

136 kB

Ethernet

136 kB

512 kB

LCD

512 kB

512 kB

Total SRAM

512 kB

1 MB

Flash bank B

1 MB

LPC4337JBD144

Flash bank A

LPC4337JET256

Type number

QEI

USB0 (Host, Device, OTG)

Table 4.

LPC4333JET256

512 kB 256 kB

256 kB

136 kB

no

yes

yes

yes/yes yes

yes

8

J

164

LPC4333JBD144

512 kB 256 kB

256 kB

136 kB

no

yes

yes

yes/no

yes

no

8

J

83

LPC4333JET100

512 kB 256 kB

256 kB

136 kB

no

yes

yes

yes/no

no

no

4

J

49

LPC4327JBD144

1 MB

512 kB

512 kB

136 kB

no

no

yes

no/no

yes

no

8

J

83

LPC4327JET100

1 MB

512 kB

512 kB

136 kB

no

no

yes

no/no

no

no

4

J

49

LPC4325JBD144

768 kB 384 kB

384 kB

136 kB

no

no

yes

no/no

yes

no

8

J

83

LPC4325JET100

768 kB 384 kB

384 kB

136 kB

no

no

yes

no/no

no

no

4

J

49

LPC4323JBD144

512 kB 256 kB

256 kB

104 kB

no

no

yes

no/no

yes

no

8

J

83

LPC4323JET100

512 kB 256 kB

256 kB

104 kB

no

no

yes

no/no

no

no

4

J

49

LPC4322JBD144

512 kB 512 kB

0 kB

104 kB

no

no

yes

no/no

yes

no

8

J

83

LPC4322JET100

512 kB 512 kB

0 kB

104 kB

no

no

yes

no/no

no

no

4

J

49

LPC4317JBD144

1 MB

512 kB

512 kB

136 kB

no

no

no

no/no

yes

no

8

J

83

LPC4317JET100

1 MB

512 kB

512 kB

136 kB

no

no

no

no/no

no

no

4

J

49

LPC4315JBD144

768 kB 384 kB

384 kB

136 kB

no

no

no

no/no

yes

no

8

J

83

LPC4315JET100

768 kB 384 kB

384 kB

136 kB

no

no

no

no/no

no

no

4

J

49

LPC4313JBD144

512 kB 256 kB

256 kB

104 kB

no

no

no

no/no

yes

no

8

J

83

LPC4313JET100

512 kB 256 kB

256 kB

104 kB

no

no

no

no/no

no

no

4

J

49

LPC4312JBD144

512 kB 512 kB

0 kB

104 kB

no

no

no

no/no

yes

no

8

J

83

LPC4312JET100

512 kB 512 kB

0 kB

104 kB

no

no

no

no/no

no

no

4

J

49

LPC43S67JET256 1 MB

512 kB

512 kB

154 kB

yes

yes

yes

yes/yes yes

yes

8

J

164

LPC43S67JBD208 1 MB

512 kB

512 kB

154 kB

yes

yes

yes

yes/yes yes

yes

8

J

142

LPC43S67JET100 1 MB

512 kB

512 kB

154 kB

yes

yes

yes

yes/yes yes

yes

8

J

49

LPC43S57JET256 1 MB

512 kB

512 kB

136 kB

yes

yes

yes

yes/yes yes

yes

8

J

164

LPC43S57JBD208 1 MB

512 kB

512 kB

136 kB

yes

yes

yes

yes/yes yes

yes

8

J

142

LPC43S37JBD144 1 MB

512 kB

512 kB

136 kB

no

yes

yes

yes/no

yes

no

8

J

83

LPC43S37JET100 1 MB

512 kB

512 kB

136 kB

no

yes

yes

yes/no

no

no

4

J

49

[1]

J = -40 °C to +105 °C; F = -40 °C to +85 °C.

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UM10503

NXP Semiconductors

Chapter 1: Introductory information

1.5 Block diagram (flashless parts)

LPC4350/S50/30/S30/20/S20/10
TEST/DEBUG
INTERFACE

TEST/DEBUG
INTERFACE

ARM
CORTEX-M0

HIGH-SPEED PHY

ARM
CORTEX-M4
system bus

D-code bus

I-code bus

DMA

ETHERNET(1)
10/100
MAC
IEEE 1588

HIGH-SPEED
USB0(1)
HOST/
DEVICE/OTG

HIGH-SPEED
USB1(1)
HOST/DEVICE

LCD(1)

SD/
MMC

masters

slaves

BRIDGE
AHB MULTILAYER MATRIX

SPI
SGPIO

slaves
BRIDGE 0

BRIDGE 1

BRIDGE 2

BRIDGE 3

BRIDGE

BRIDGE

128 kB LOCAL SRAM
72 kB LOCAL SRAM
64 kB ROM

RI TIMER

I2C1

CGU

ALARM TIMER

USART0

MOTOR
CONTROL
PWM(1)

USART2

10-bit DAC

CCU1

BACKUP REGISTERS

UART1

I2C0

USART3

C_CAN0

CCU2

POWER MODE CONTROL

SSP0

I2S0

TIMER2

10-bit ADC0

RGU

EMC

TIMER0

I2S1

CONFIGURATION
REGISTERS

TIMER3

10-bit ADC1
EVENT ROUTER

HS GPIO

TIMER1

C_CAN1

SSP1
OTP MEMORY

SPIFI

WWDT

SCU
GPIO
INTERRUPTS

32 kB AHB SRAM
16 +16 kB AHB SRAM
SCTimer/PWM

QEI(1)
RTC

RTC OSC

GIMA

AES ENCRYPTION/
DECRYPTION(2)

12 MHz IRC

GPIO GROUP0
INTERRUPT

RTC POWER DOMAIN

GPIO GROUP1
INTERRUPT

= connected to GPDMA

002aaf772-x

AES is supported for LPC43Sxx parts only.

Fig 1.

LPC4350/30/20/10 Block diagram (flashless parts, dual-core)

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Chapter 1: Introductory information

slaves

LPC4370

SUBSYSTEM AHB MULTILAYER MATRIX
system
bus

masters

2 kB LOCAL SRAM
16 kB LOCAL SRAM

ARM
CORTEX-M0

SPI

SUBSYSTEM
SGPIO
TEST/DEBUG
INTERFACE
CORE-CORE
BRIDGE
TEST/DEBUG
INTERFACE
MPU

FPU
TEST/DEBUG
INTERFACE

HIGH-SPEED PHY

ARM
CORTEX-M4
system bus

D-code bus

I-code bus

ETHERNET
10/100
MAC
IEEE 1588

DMA

HIGH-SPEED
USB0
HOST/
DEVICE/OTG

HIGH-SPEED
USB1
HOST/DEVICE

LCD(1)

SD/
MMC

ARM
CORTEX-M0

masters
master
AHB MULTILAYER MATRIX
slaves

BRIDGE 0

BRIDGE 1

BRIDGE 2

BRIDGE 3

BRIDGE

BRIDGE

128 kB LOCAL SRAM
72 kB LOCAL SRAM

I2C1

RI TIMER

USART0

USART2

10-bit DAC

CCU1

BACKUP REGISTERS

UART1

I2C0

USART3

C_CAN0

CCU2

POWER MODE CONTROL

SSP0

I2S0

TIMER2

10-bit ADC0

RGU

SPIFI

TIMER0

I2S1

CONFIGURATION
REGISTERS

TIMER3

10-bit ADC1
EVENT ROUTER

EMC

TIMER1

C_CAN1

SSP1
OTP MEMORY

12-bit ADC (ADCHS)

SCU
GPIO
INTERRUPTS

CGU

64 kB ROM

MOTOR
CONTROL
PWM

WWDT

ALARM TIMER

32 kB AHB SRAM
16 +16 kB AHB SRAM
SCTimer/PWM

QEI
RTC

RTC OSC

GIMA

HS GPIO

12 MHz IRC

GPIO GROUP0
INTERRUPT

RTC POWER DOMAIN

GPIO GROUP1
INTERRUPT

= connected to GPDMA
002aag606-x

Fig 2.

LPC4370 Block diagram (flashless parts, triple-core, 12-bit ADCHS)

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NXP Semiconductors

Chapter 1: Introductory information

slaves

LPC43S70

SUBSYSTEM AHB MULTILAYER MATRIX
system
bus

masters

2 kB LOCAL SRAM
16 kB LOCAL SRAM

ARM
CORTEX-M0

SPI

SUBSYSTEM
SGPIO
TEST/DEBUG
INTERFACE
CORE-CORE
BRIDGE
TEST/DEBUG
INTERFACE
MPU

FPU
TEST/DEBUG
INTERFACE

HIGH-SPEED PHY

ARM
CORTEX-M4
system bus

D-code bus

I-code bus

DMA

ETHERNET
10/100
MAC
IEEE 1588

HIGH-SPEED
USB0
HOST/
DEVICE/OTG

HIGH-SPEED
USB1
HOST/DEVICE

LCD(1)

SD/
MMC

ARM
CORTEX-M0

masters
master
AHB MULTILAYER MATRIX
slaves

BRIDGE 0

BRIDGE 1

BRIDGE 2

BRIDGE 3

BRIDGE

BRIDGE

128 kB LOCAL SRAM
72 kB LOCAL SRAM

I2C1

RI TIMER

USART0

USART2

10-bit DAC

CCU1

BACKUP REGISTERS

UART1

I2C0

USART3

C_CAN0

CCU2

POWER MODE CONTROL

SSP0

I2S0

TIMER2

10-bit ADC0

RGU

SPIFI

TIMER0

I2S1

CONFIGURATION
REGISTERS

TIMER3

10-bit ADC1
EVENT ROUTER

EMC

TIMER1

C_CAN1

SSP1
OTP MEMORY

12-bit ADC (ADCHS)

SCU
GPIO
INTERRUPTS

CGU

64 kB ROM

MOTOR
CONTROL
PWM

WWDT

ALARM TIMER

32 kB AHB SRAM
16 +16 kB AHB SRAM
SCTimer/PWM

QEI
RTC

RTC OSC

GIMA
12 MHz IRC

GPIO GROUP0
INTERRUPT

HS GPIO
AES ENCRYPTION/
DECRYPTION

RTC POWER DOMAIN

GPIO GROUP1
INTERRUPT

= connected to GPDMA
aaa-016379-x

Fig 3.

LPC43S70 Block diagram (flashless parts, triple-core, 12-bit ADCHS)

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UM10503

NXP Semiconductors

Chapter 1: Introductory information

1.6 Block diagram (parts with on-chip flash)

LPC435x/3x/2/1x
TEST/DEBUG
INTERFACE

TEST/DEBUG
INTERFACE

ARM
CORTEX-M0

HIGH-SPEED PHY

ARM
CORTEX-M4
system bus

D-code bus

I-code bus

DMA

ETHERNET(1)
10/100
MAC
IEEE 1588

HIGH-SPEED
USB0(1)
HOST/
DEVICE/OTG

HIGH-SPEED
USB1(1)
HOST/DEVICE

LCD(1)

SD/
MMC

masters

slaves

BRIDGE

AHB MULTILAYER MATRIX

SPI
SGPIO

slaves
BRIDGE 0

BRIDGE 1

BRIDGE 2

BRIDGE 3

BRIDGE

BRIDGE

64 kB ROM
32 kB LOCAL SRAM
40 kB LOCAL SRAM

RI TIMER

I2C1

CGU

ALARM TIMER

USART0

MOTOR
CONTROL
PWM(1)

USART2

10-bit DAC

CCU1

BACKUP REGISTERS

UART1

I2C0

USART3

C_CAN0

CCU2

POWER MODE CONTROL

SSP0

I2S0

TIMER2

10-bit ADC0

RGU

CONFIGURATION
REGISTERS

TIMER0

I2S1

TIMER3

10-bit ADC1

16 kB EEPROM
512/256 kB FLASH A

EVENT ROUTER
C_CAN1

512/256 kB FLASH B

TIMER1

SSP1
OTP MEMORY

SCTimer/PWM

WWDT

SCU
GPIO
INTERRUPTS

QEI(1)
RTC

RTC OSC

32 kB AHB SRAM
16 kB +
16 kB AHB SRAM

EMC

GIMA
12 MHz IRC

GPIO GROUP0
INTERRUPT

RTC POWER DOMAIN

HS GPIO
SPIFI

GPIO GROUP1
INTERRUPT

= connected to DMA

002aah234-x

AES is supported for parts LPC43Sxx only. LCD on parts LPC4357/53 only.

Fig 4.

LPC43xx block diagram (parts with on-chip flash, dual-core)

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UM10503

NXP Semiconductors

Chapter 1: Introductory information

LPC436x/43S6x
slaves
AHB MULTILAYER MATRIX
system
bus

masters

2 kB LOCAL SRAM
16 kB LOCAL SRAM

ARM
CORTEX-M0
SUBSYSTEM

SPI
SGPIO

TEST/DEBUG
INTERFACE
CORE-CORE
BRIDGE

TEST/DEBUG
INTERFACE

TEST/DEBUG
INTERFACE

ARM
CORTEX-M0
APPLICATION

HIGH-SPEED PHY

ARM
CORTEX-M4

HIGH-SPEED
USB0
HOST/
DEVICE/OTG

HIGH-SPEED
USB1
HOST/DEVICE

SD/
MMC

LCD

system bus

system bus

D-code bus

I-code bus

ETHERNET
10/100
MAC
IEEE 1588

GPDMA

masters
slaves
MAIN AHB MULTILAYER MATRIX
slaves
BRIDGE 0

BRIDGE 1

BRIDGE 2

BRIDGE 3

BRIDGE

BRIDGE

64 kB ROM
32 kB LOCAL SRAM
40 kB LOCAL SRAM

RI TIMER

I2C1

CGU

ALARM TIMER

USART0

MOTOR
CONTROL
PWM

USART2

10-bit DAC

CCU1

BACKUP REGISTERS

UART1

I2C0

USART3

C_CAN0

CCU2

POWER MODE CONTROL

SSP0

I2S0

TIMER2

10-bit ADC0

RGU

TIMER0

I2S1

CONFIGURATION
REGISTERS

TIMER3

10-bit ADC1

TIMER1

C_CAN1

WWDT

SCU
GPIO
INTERRUPTS

EVENT ROUTER
SSP1
OTP MEMORY
QEI
RTC
GIMA
12 MHz IRC

GPIO GROUP0
INTERRUPT
GPIO GROUP1
INTERRUPT

RTC OSC

RTC POWER DOMAIN

32 kB AHB SRAM
16 kB +
16 kB AHB SRAM
16 kB EEPROM
512 kB FLASH A
512 kB FLASH B
SCTimer/PWM
EMC
HS GPIO
SPIFI
AES ENCRYPTION/
DECRYPTION

= connected to GPDMA

aaa-018919-um

AES is supported for parts LPC43S67 only.

Fig 5.

LPC436x/LPC43S6x block diagram (parts with on-chip flash, dual-core)

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NXP Semiconductors

Chapter 1: Introductory information

1.7 ARM core features
1.7.1 ARM Cortex-M4 processor
The ARM Cortex-M4 CPU incorporates a 3-stage pipeline, uses a Harvard architecture
with separate local instruction and data buses as well as a third bus for peripherals, and
includes an internal prefetch unit that supports speculative branching. The ARM
Cortex-M4 supports single-cycle digital signal processing and SIMD instructions. A
hardware floating-point processor is integrated in the core. The processor includes an
NVIC with up to 53 interrupts.
The ARM Cortex-M4 is implemented with a Memory Protection Unit supporting eight
regions, a hardware Floating Point Unit (FPU), debugging features, and a system tick
timer.

1.7.2 ARM Cortex-M0 co-processors
The ARM Cortex-M0 is a general purpose, 32-bit microprocessor, which offers high
performance and very low-power consumption. The ARM Cortex-M0 co-processor uses a
3-stage pipeline von-Neumann architecture and a small but powerful instruction set
providing high-end processing hardware. The co-processor incorporates an NVIC with up
to 32 interrupts.
Both ARM Cortex-M0 cores are implemented in the same way supporting a 32-cycle
multiplier and debug features. A system tick timer is not included.

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UM10503
Chapter 2: LPC43xx/LPC43Sxx Multi-Core configuration and
Inter-Process Communication (IPC)
Rev. 2.4 — 22 August 2018

User manual

2.1 How to read this chapter
The ARM Cortex-M0APP processor is available on all LPC43xx/LPC43Sxx parts.
The ARM Cortex-M0SUB subsystem core is only available on parts LPC437x/LPC43S7x
and LPC436x/LPC43S6x parts only.

2.2 Basic configuration
The ARM Cortex-M0 processor(M0APP) is configured as follows:

• See Table 5 for clocking and power control.
• The ARM Cortex-M0 is reset by the M0APP_RST (reset #56) or by a general Reset.
• After power-up, the ARM Cortex-M0 remains in reset until the reset is released by
clearing the corresponding RESET_CTRL1 bit (see Table 172).

• The ARM Cortex-M0 interrupt is connected to interrupt slot # 1 in the ARM Cortex-M4
NVIC and slot #31 in the ARM Cortex-M0SUB. See Table 78 for peripheral interrupts
connected to the ARM Cortex-M0APP.

• To clear the ARM-Cortex-M0 interrupt, use the M0APPTXEVENT register (Table 109).
See Section 2.4.2.
The ARM Cortex-M0 subsystem core (M0SUB) is configured as follows:

• See Table 5 for clocking and power control.
• The ARM Cortex-M0 subsystem core is reset by the M0SUB_RST (reset # 12) or by a
general Reset.

• After power-up, the ARM Cortex-M0 subsystem core remains in reset until the reset is
released by clearing the corresponding RESET_CTRL0 bit (bit 12, see Table 171).

• The ARM Cortex-M0 subsystem core interrupt is connected to interrupt slot # 50 in
the ARM Cortex-M4 NVIC and interrupt slot #31 in the ARM Cortex-M0APP NVIC.
See Table 79 for peripheral interrupts connected to the ARM Cortex-M0 subsystem
core.

• To clear the ARM-Cortex-M0 interrupt, use the M0SUBTXEVENT register (Table 108).
See Section 2.4.2.

Table 5.

ARM Cortex-M0 clocking and power control

ARM Cortex-M0 clock (to the
M0APP core)

Base clock

Branch clock

Operating
frequency

BASE_M4_CLK

CLK_M4_M0

up to 204 MHz

ARM Cortex-M0 subsystem clock BASE_PERIPH_CLK
(to the M0SUB core)

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CLK_CLK_PERIPH up to 204 MHz
_CORE

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NXP Semiconductors

Chapter 2: LPC43xx/LPC43Sxx Multi-Core configuration and

INT #31
INT #1

INT #1
Cortex-M0SUB

Cortex-M0APP

TXEV

TXEV

INT #1

INT #50

Cortex-M4

INT #31

TXEV

CREG
M4TXEVENT

CREG
M0SUBTXEVENT
CREG
M0APPTXEVENT

Fig 6.

Multi-core connections

2.3 Introduction
The LPC43xx/LPC43Sxx is a multi-core microcontroller implementing an ARM Cortex-M4
and one or two ARM Cortex-M0 cores. All cores have access to the complete memory
map. The ARM Cortex-M4 is used as them main processor. One ARM Cortex-M0core
(M0APP) can be used as co-processor to off-load the ARM Cortex-M4 and to perform
serial I/O tasks. The other ARM Cortex-M0 core (M0SUB) - if available - is typically used
to control the SGPIO and SPI peripherals. This core is connected through a bridge to the
main Cortex-M4 processor.

2.4 General description
The ARM Cortex-M4 processor is used after reset as the top-level system controller. After
power-up or wake-up from Deep power-down mode, the M0 core or cores remain in reset
until the reset is released by software running on the M4 core. Then, the M4 can
communicate with one or both M0 cores through shared memory space and interrupts.

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Interrupt

Write
Pointer

RAM
CMD_BUFFER

Cortex M4

Read
Pointer

Cortex M0

AHB

(Master)

(Slave)
Write
Pointer

RAM
MSG_BUFFER
Read
Pointer

Interrupt

= M0 subsystem
= M4 subsystem
= shared

Fig 7.

Dual-core block diagram

2.4.1 Hardware
Instead of dedicated hardware, the IPC uses existing hardware components. The buffers
in shared memory can use any of the available SRAM. The buffer pointers are maintained
in software. The interrupts are captured in the processor’s NVIC and cleared in the CREG
block (see Table 105 and Table 109).

2.4.2 Interrupt handling
A CPU cores raises an interrupt to the other CPU core or cores using the TXEV
instruction. If both CPU have been set to respond to the same interrupt then the software
architecture should include means to differentiate messages for different CPU's, for
example the command in the command buffer could contain information for which CPU
the command is intended.
The ARM Cortex-M4 and ARM Cortex-M0 trigger interrupts to each other via CREG
registers M4TXEVENT, M0SUBTXEVENT,and M0APPTXEVENT (see
Table 105,Table 108, and Table 109). The M4-to-M0 and M0-to-M4 interrupts use the
SendEvent instruction (SEV) to raise the signal TXEV. This signal is captured by CREG. It
should be cleared by the interrupt handler of the receiving core.

2.4.3 M0SUB access
M0SUB connects via a bridge to the main AHB matrix. This bridge introduces an access
latency when crossing from the M0sub domain to the main matrix domain. The bridge
uses a write buffer to minimize latency; write accesses should be used when possible.

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2.5 IPC Protocol implementation example
The IPC supports low-level interfaces, e.g. a register level interface, but can also be
implemented as a higher level API.
The ARM Cortex-M4 host CPU is the master in this example. It initiates commands to the
ARM Cortex-M0 that mimic a hardware register level interface. The commands can be
issued either synchronously (wait for the reply message) or asynchronously (not wait for
the reply message) depending on the host application.
The ARM Cortex-M0 responds to commands given by the ARM Cortex-M4 by issuing
messages.
Since the ARM Cortex-M4 and ARM Cortex-M0 cannot at the same time write to the same
location, there is no need for a synchronization object (e.g. a semaphore) in this IPC.
The basic IPC features are:

• The ARM Cortex-M4 initializes the ARM Cortex-M0 system.
• The ARM Cortex-M4 communicates with the ARM Cortex-M0 system via a command
queue.

• The message queues are located in the ARM Cortex-M4 address space because the
ARM Cortex-M4 can be blocked from access to the ARM Cortex-M0 hardware
subsystem. The M0 subsystem can be made more deterministic (and secure) if no
unknown operations take place. A customer application executing on the M4 in the
M0 address space might block M0 operations and thereby cause M0 performance
problems.

2.5.1 IPC queues
The ARM Cortex-M4 has an output command queue and an input message queue. A
queue is defined by four registers:
1. queue start address
2. queue end address
3. write pointer
4. read pointer
The ARM Cortex-M4 initializes these four registers. These registers reside in the same
shared SRAM as the queues to ensure that data and registers changes are synchronous.
Their location is static and known up front by the ARM Cortex-M0.
Messages are passed through queues using cyclic buffers. A queue is filled with
commands or messages from start to end address. When a buffer pointer points beyond
the end address it wraps around to the start address. When the read pointer is equal to
the write pointer, the queue can be either empty or completely full. To avoid this ambiguity
the queue shall never be filled completely. The minimum queue size is thus 3 words (the
longest command/message +1 word). An equal write and read pointer will indicate an
empty queue.

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The command queue is filled by the ARM Cortex-M4 and emptied by the ARM Cortex-M0;
the write pointer is advanced by the ARM Cortex-M4 every time it adds a new command
to the queue. The read pointer is advanced by the ARM Cortex-M0 every time it removes
a command from the queue.
The message queue is filled by the ARM Cortex-M0 and emptied by the ARM Cortex-M4;
the write pointer is advanced by the ARM Cortex-M0 every time it adds a new message to
the queue. The read pointer is advanced by the ARM Cortex-M4 every time it removes a
message from the queue.
When a new command or message has been added to the queue and the write pointer
had been updated, an interrupt is raised to the other processor. The commands are
acknowledged by a return message (accept or fail).
The ARM Cortex-M4 and ARM Cortex-M0 only have one IPC write and one IPC read task.
If multiple instances exist then a local arbiter shall ensure that all write and read
operations are atomic; after data has been written (read) the write (read) pointer is
updated before another write (read) operation can start.
It is the responsibility of the process writing to a queue making sure that the queue is not
filled completely; before loading a new item the process should confirm that the write
pointer will not be equal to, or overtake the read pointer and will leave at least one free
space. On the other hand the receiving side shall promptly process and remove items
from the queue.
No explicit error handling is performed. It is assumed that the ARM Cortex-M0 will always
respond to a ARM Cortex-M4 command.

2.5.2 Protocol
The ARM Cortex-M0 is used as a co-processor to off-load the ARM Cortex-M4 and to
perform serial IO tasks. The ARM Cortex-M4 initializes tasks executed on the ARM
Cortex-M0. The ARM Cortex-M0 is able to signal to the ARM Cortex-M4 when these tasks
have completed or failed by issuing commands from ARM Cortex-M4 to ARM Cortex-M0,
where the ARM Cortex-M0 responds with messages. This command and message
interface resembles a hardware register level interface with command and status
registers.
The ARM Cortex-M4 issues 32-bit commands to the ARM Cortex-M0. Each command
starts with the argument id (P), followed by the read/write bit, followed by a 16-bit ID that
defines which task is referred to. The least significant bit of the task ID indicates the
command type. A Write command is followed by a 32-bit operand. When a new command
is available, the ARM Cortex-M4 signals this to the ARM Cortex-M0 by raising an
interrupt.
The ARM Cortex-M0 return 32-bit messages to the ARM Cortex-M4. A messages starts
the argument id (P or S), followed by a 16-bit ID that indicates which tasks the message
refers to. The least significant byte indicates the message type. A Read response
message is followed by the 32-bit read operand. When a new message is available, the
ARM Cortex-M0 signals this to the ARM Cortex-M4 by raising an interrupt.

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Small data transfers can be performed by the single 32-bit data read, CMD_RD_ID, and
write, CMD_WR_ID, commands. These commands use a 3-Byte addressing scheme to
support an argument space of 212 = 4096 32-bit words. Large data transfers can be more
efficiently handled using pointers.
Also higher level interfaces using API calls will typically use indirect, pointer based, reads
and writes.
When multiple tasks are running concurrently the ID is used to distinguish commands and
messages belonging to a certain task. A global command parser should be used to the
kick off commands to the tasks running on the ARM Cortex-M0.
The same holds true for the ARM Cortex-M4 side, a global message parser channels
back messages to the task dispatchers running on the ARM Cortex-M4 side.
Table 6.

Command list

Command

Bit mask

Description

CMD_RD_ID

0xPPP0.TTTT

read 32-bit WORD with argument ID=0xPPP
from the task with ID = 0xTTTT

CMD_WR_ID

0xPPP1.TTTT, WORD

write 32-bit WORD with argument ID=0xPPP to
the task with ID = 0xTTTT

Table 7.

Message list

Message

Bit mask

Description

MSG_SRV_ID

0xSS00.TTTT

ARM Cortex-M0 request servicing for the task
with ID = 0xTTTT. The service type is coded in
bytes SS. The meaning of SS is proprietary per
task. SS=0x00 means the task has finished.

MSG_RD_ID

0xPPP1.TTTT, VALUE

ARM Cortex-M0 responds with VALUE to a read
of WORD with argument ID=0xPPP* from the
task with ID = 0xTTTT.

MSG_RD_STS_ID 0xPPPR.TTTT

ARM Cortex-M0 response to a read of WORD
with argument ID=0xPPP* from the task with ID
= 0xTTTT fails. Cause of the failure is coded in
R; R = 2...4
2 = invalid argument
3 = reserved
4 = reserved

MSG_WR_STS_ID 0xPPPW.TTTT.

ARM Cortex-M0 response to a write with
argument ID=0xPPP* from the task with ID =
0xTTTT. Response is coded in W; W = 5...7
5 = write was successful
6 = write failed
7 = reserved

Table 8.

Command responses

Command

Possible responses

Description

CMD_RD_ID

MSG_RD_ID, VALUE

read acknowledged

MSG_RD_STS_ID

read failed

MSG_WR_STS_ID

write is acknowledged as a success or failure

CMD_WR, WORD

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2.5.3 Example
Assume that a certain task with ID 0x1234 should be executed by the ARM Cortex-M0.
For example, read data from a register level interface controlled by the ARM Cortex-M0.
Text in <>brackets indicates a register.
The registers can either be located in the ARM Cortex-M0 SRAM, for more deterministic
access times, or in shared SRAM. If the ARM Cortex-M0 SRAM is used, then the register
data needs to be copied at initialization time. This copying takes time. The ARM
Cortex-M4 can poll a status register to determine when the transfer has finished.
The ARM Cortex-M4 initializes the command and message queues by loading the startand end addresses and write and read pointers.
Then the ARM Cortex-M4 loads the register values in a reserved area in common SRAM
memory. An alternative approach is that the ARM Cortex-M4 writes register per register.
However, this requires more communication overhead than loading all data in one go.
Once all data has been set up, the ARM Cortex-M0 task can be started.
Table 9.

IPC example
Command

1

Message

CMD_WR

Byte values

Description

0x11234, pointer

Command to initialize
the task, the pointer
informs the ARM
Cortex-M0 of the
location of the register
values.

The ARM Cortex-M0 processes the registers
2

MSG_WR_STS

0x21234

ARM Cortex-M0 signals
write data has been
processed

3

MSR_SRV

0x001234

ARM Cortex-M0
requests service, e.g.
because data has been
captured and is
available

0x11234

ARM Cortex-M4 read
status

0x11234, VALUE

ARM Cortex-M0
responds with status

4

CMD_RD

5

MSG_RD,VALUE

Depending on the status the ARM Cortex-M4 may decide to read more data
6

CMD_RD

7

:

:

n

CMD_WR

n+1

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0x1234,1

ARM Cortex-M4 reads
result

MSG_RD,VALUE

0x11234, pointer

ARM Cortex-M0
responds with pointer to
results.

:

:

:

0x11234, value

Command to stop the
task

0x21234

ARM Cortex-M0 signals
stop has been
processed

MSG_WR_STS

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3.1 How to read this chapter
The available peripherals and their memories vary for different parts.

• Ethernet: available only on LPC436x/5x/3x, LPC43S6x/S5x/S3x, and
LPC4370/LPC43S70.

• USB0: available only on LPC436x/5x/3x/2x/, LPC43S6x/S5x/S3x, and
LPC4370/LPC43S70.

• USB1: available only on LPC436x/5x/3x, LPC43S6x/S5x/S3x, and
LPC4370/LPC43S70.

• SRAM: see Table 10.
• Flash: see Table 11.
• ARM Cortex-M0SUB core: available on LPC4370/LPC43S70 and
LPC436x/LPC43S6x parts only.
The registers and memory regions corresponding to unavailable peripheral and memory
blocks are reserved.

3.2 Basic configuration
In the CREG block (see Table 103), select the interface to access the 16 kB block of RAM
located at address 0x2000 C000. This RAM memory block can be accessed either by the
Embedded Trace Buffer (ETB) or be used as normal SRAM on the AHB bus.
Remark: When the ETB is used, the 16 kB memory space at 0x2000 C000 must not be
used by any other process.

3.3 Memory configuration
3.3.1 On-chip static RAM
The LPC43xx/LPC43Sxx support up to 282 kB SRAM on flashless parts or up to 136 kB
on parts with on-chip flash with separate bus master access for higher throughput and
individual power control for low power operation (see Figure 12).
When the Embedded Trace Buffer is used (see ETBCFG register, Table 103), the 16 kB
memory space at 0x2000 C000 must not be used by any other process.

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Chapter 3: LPC43xx/LPC43Sxx Memory mapping

Table 10.

LPC43xx/LPC43Sxx SRAM configuration

Part

Local SRAM

Local SRAM

0x2000 8000

0x2000 C000

AHB SRAM/
ETB SRAM[2]

0x2000 0000

AHB SRAM

0x1800 0000

AHB SRAM

0x1008 0000

M0
subsystem
SRAM

0x1000 0000

[1]

LPC4370

128 kB

72 kB

16 + 2 kB

32 kB

16 kB

16 kB

Figure 8

LPC4350

128 kB

72 kB

-

32 kB

16 kB

16 kB

Figure 8

LPC4330

128 kB

72 kB

-

32 kB

16 kB

16 kB

Figure 8

LPC4320

96 kB

40 kB

-

32 kB

16 kB

16 kB

Figure 8

LPC4310

96 kB

40 kB

-

16 kB

-

16 kB

Figure 8

LPC43S70

128 kB

72 kB

16 + 2 kB

32 kB

16 kB

16 kB

Figure 8

LPC43S50

128 kB

72 kB

-

32 kB

16 kB

16 kB

Figure 8

LPC43S30

128 kB

72 kB

-

32 kB

16 kB

16 kB

Figure 8

LPC43S20

96 kB

40 kB

-

32 kB

16 kB

16 kB

Figure 8

LPC43S10

96 kB

40 kB

-

16 kB

-

16 kB

Figure 8

LPC4367

32

40

16 + 2 kB

32

16

16

Figure 10

LPC435x

32 kB

40 kB

-

32 kB

16 kB

16 kB

Figure 10

LPC433x

32 kB

40 kB

-

32 kB

16 kB

16 kB

Figure 10

LPC4327

32 kB

40 kB

-

32 kB

16 kB

16 kB

Figure 10

LPC4325

32 kB

40 kB

-

32 kB

16 kB

16 kB

Figure 10

LPC4323

32 kB

40 kB

-

16 kB

-

16 kB

Figure 10

LPC4322

32 kB

40 kB

-

16 kB

-

16 kB

Figure 10

LPC4317

32 kB

40 kB

-

32 kB

16 kB

16 kB

Figure 10

LPC4315

32 kB

40 kB

-

32 kB

16 kB

16 kB

Figure 10

LPC4313

32 kB

40 kB

-

16 kB

-

16 kB

Figure 10

LPC4312

32 kB

40 kB

-

16 kB

-

16 kB

Figure 10

LPC43S67

32

40

16 + 2 kB

32

16

16

Figure 10

LPC43S5x

32 kB

40 kB

-

32 kB

16 kB

16 kB

Figure 10

LPC43S3x

32 kB

40 kB

-

32 kB

16 kB

16 kB

Figure 10

[1]

Top 8 kB at of memory starting at location 0x1008 8000 remain powered on in Sleep, Deep-sleep, and Power-down modes (see
Table 114).

[2]

To configure SRAM memory use for AHB or ETB, see Table 103.

3.3.2 Bit banding
Bit-banding offers efficient bit accesses. Bits in the bit-band region (0x2000 0000 to
0x2010 0000 and 0x4000 0000 to 0x4010 0000) can be accessed in the so-called alias
region at 0x2200 0000 and 0x4200 0000. Reads return the respective bit from the
bit-band region. Writes perform an atomic read-modify-write on the respective bit of the
bit-band region. For details, see the ARM Cortex-M4 technical reference manual.
Remark: Bit banding can not be used with the MAC_RWAKE_FRFLT register (see
Section 28.6.10).
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Remark: Although the EEPROM is mapped in a bit-banding capable region, attempts to
write access the EEPROM in the bit-banding aliased memory space will not result in a bit
write

3.3.3 On-chip flash
The available flash configuration for the LPC435x/3x/2x/1x and LPC43S5x/S3x are shown
in Table 11. An integrated flash accelerator maximizes performance for use with the two
fast AHB buses.
The flash memory interface includes an intelligent buffering scheme. It can be beneficial
to locate code and static data over the two flash memories to enable parallel code and
data access or to avoid that interrupts corrupt buffer content. The buffers are aligned on
32-byte boundaries.

Table 11.

LPC435x/3x/2x/1x and LPC43S5x/S3x Flash configuration

Part

Flash bank A
256 kB

Flash bank A
128 kB

Flash bank A
128 kB

Flash bank B
256 kB

Flash bank B Flash bank B
128 kB
128 kB

Total flash

staring at address:
0x1A00 0000

0x1A04 000

0x1A06 0000

0x1B00 0000

0x1B04 0000

0x1B06 0000

LPC43x7

yes

yes

yes

yes

yes

yes

1 MB

LPC43x5

yes

yes

no

yes

yes

no

768 kB

LPC43x3

yes

no

no

yes

no

no

512 kB

LPC43x2

yes

yes

yes

no

no

no

512 kB

LPC43Sx7 yes

yes

yes

yes

yes

yes

1 MB

3.3.4 On-chip EEPROM
The LPC436x/5x/3x/2x/1x and LPC43S6x/5x/3x parts with flash also include a 16 kB
EEPROM. The EEPROM is divided into 128 pages. The last EEPROM page is protected.

3.3.5 Memory retention in the Power-down modes
In Deep-sleep mode, all SRAM content is retained. At wake-up the system can restart
immediately.
In Power-down mode, only the top 8 kB of the SRAM block starting at 0x1008 0000 is
retained - that is 8 kB of SRAM located at 0x1009 0000 for devices with 72 kB SRAM and
8 kB of SRAM located at 0x1008 8000 for devices with 40 kB of SRAM (see Table 114
“Memory retention”). All other SRAM content is lost. Common practice is to store the stack
and other variables that need to be retained in this 8 kB memory space as well as code to
restart the rest of the system.
In Deep power-down mode, no SRAM content is retained. Variables that need to be
retained in deep power down can be stored in the 256-byte register file located in the RTC
domain at 0x4004 1000.

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3.3.6 Memory Protection Unit (MPU)
The MPU is a integral part of the ARM Cortex-M4 for memory protection and supported by
all LPC43xx parts. The processor supports the standard ARMv7 Protected Memory
System Architecture model. The MPU provides full support for:

• protection regions
• overlapping protection regions, with ascending region priority (7 = highest priority, 0 =
lowest priority)

• access permissions
• exporting memory attributes to the system
MPU mismatches and permission violations invoke the programmable-priority
MemManage fault handler. See the ARMv7-M Architecture Reference Manual for more
information.
The access permission bits, TEX, C, B, AP, and XN, of the Region Access Control
Register control access to the corresponding memory region. If an access is made to an
area of memory without the required permissions, a permission fault is raised. For more
information, see the ARMv7-M Architecture Reference Manual.
The MPU is used to enforce privilege rules, to separate processes, and to enforce access
rules. For details on how to use the MPU and for the register description refer to the ARM
Cortex-M4 Technical Reference Manual.

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3.4 Memory map (flashless parts)
LPC4370/50/30/20/10
LPC43S70/S50/S30/S20
4 GB

0xFFFF FFFF
reserved
0xE010 0000
ARM private bus
reserved
SPIFI data
256 MB dynamic external memory DYCS3
256 MB dynamic external memory DYCS2
reserved
peripheral bit band alias region
reserved

0xE000 0000
0x8800 0000
0x8000 0000
0x7000 0000
0x6000 0000
0x4400 0000
0x4200 0000
0x4010 2000

SGPIO
SPI
reserved
high-speed GPIO
reserved
reserved
0x2000 0000
0x1F00 0000
0x1E00 0000
0x1D00 0000
0x1C00 0000

12-bit ADC (ADCHS)

16 MB static external memory CS3

APB peripherals #3

16 MB static external memory CS2

reserved

16 MB static external memory CS1

APB peripherals #2

16 MB static external memory CS0

reserved
APB peripherals #1
reserved

reserved
APB peripherals #0

0x1800 0000
0x1400 0000

clocking/reset peripherals

16 kB M0 SUBSYSTEM SRAM

RTC domain peripherals

SPIFI data

reserved

0x1008 A000
0x1008 0000
0x1002 0000
0x1001 8000

256 MB dynamic external memory DYCS1
64 kB ROM

128 MB dynamic external memory DYCS0

reserved

0x400F 2000
0x400F 1000
0x400F 0000
0x400E 0000
0x400D 0000
0x400C 0000
0x400B 0000
0x400A 0000
0x4009 0000
0x4008 0000

0x4005 0000
0x4004 0000

0x4000 0000
0x3000 0000
0x2800 0000

reserved

32 kB local SRAM
(LPC4370/50/30)

0x2400 0000
32 MB AHB SRAM bit banding
0x2200 0000

32 kB + 8 kB local SRAM
(LPC4320/10)

reserved

reserved

16 kB AHB SRAM

32 kB local SRAM

16 kB AHB SRAM

0x2001 0000

16 kB AHB SRAM
96 kB local SRAM

16 kB AHB SRAM

0x1000 0000

local SRAM/
external static memory banks
0 GB

Fig 8.

0x400F 4000

0x4001 2000
AHB peripherals

1 GB

reserved

0x1009 2000

0x400F 8000

0x4006 0000

2 kB M0 SUBSYSTEM SRAM

0x1041 0000
0x1040 0000

0x4010 0000

reserved

0x1800 4800
0x1800 4000

0x4010 1000

256 MB shadow area

0x2000 C000
0x2000 8000
0x2000 4000
0x2000 0000
0x1000 0000
0x0000 0000

Flashless parts: System memory map (see Figure 9 for detailed addresses of all peripherals)

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LPC4370/50/30/20/10/S70/S30/S20
0x400F 0000
0x400E 5000

reserved

0x400E 4000

ADC1

0x400E 3000

ADC0

0x400E 2000

C_CAN0

0x400E 1000

DAC

0x400E 0000
0x400C 8000

I2C1

0x400C 7000
0x400C 6000

external memories and
ARM private bus
0x6000 0000
reserved
peripheral bit band alias region
reserved

GIMA

SGPIO

QEI

SPI
APB2
peripherals

timer3

0x400C 3000

timer2

0x400C 2000

USART3

0x400C 1000

USART2

12-bit ADC (ADCHS)

0x400C 0000
0x400B 0000

RI timer

APB3 peripherals

reserved

reserved

C_CAN1

APB2 peripherals

0x400A 1000
0x400A 0000
0x4008 A000
0x4008 9000
0x4008 8000
0x4008 7000

I2S1
I2S0
I2C0

reserved
reserved

reserved
APB1 peripherals
reserved

motor control PWM

APB0 peripherals
GPIO GROUP1 interrupt

reserved

GPIO GROUP0 interrupt
GPIO interrupts

clocking/reset peripherals

SCU

0x4008 5000

timer1

0x4008 4000

timer0

0x4008 3000

SSP0

0x4008 2000

UART1 w/ modem

0x4008 1000

USART0

0x4008 0000

WWDT

RTC domain peripherals
APB0
peripherals

0x4010 1000

RGU

0x4005 3000

CCU2

0x4005 2000

CCU1

0x4005 1000

CGU

0x4005 0000

0x4010 0000
reserved

0x400F 4000

0x4004 7000

RTC

0x4004 6000

0x400F 2000

OTP controller

0x4004 5000

event router

0x4004 4000

CREG

0x4004 3000

power mode control

0x4004 2000

backup registers

0x4004 1000

0x400F 1000
0x400F 0000

RTC domain
peripherals

0x400E 0000
0x400D 0000
0x400C 0000

alarm timer

0x4004 0000

0x400A 0000

ethernet

0x4001 2000
0x4001 0000

0x4009 0000

reserved

0x4000 9000

0x4008 0000

LCD

0x4000 8000

USB1

0x4000 7000

USB0

0x4000 6000

EMC

0x4000 5000

SD/MMC

0x4000 4000

SPIFI

0x4000 3000

DMA

0x4000 2000

reserved

0x4000 1000

SCTimer/PWM

0x4000 0000

0x400B 0000

0x4006 0000
0x4005 0000
0x4004 0000

reserved

AHB
peripherals

0x4001 2000
AHB peripherals
0x4000 0000
SRAM memories
external memory banks
0x0000 0000

40 of 1444

© NXP B.V. 2018. All rights reserved.

Flashless parts: Memory map with peripherals (see Figure 8 for detailed addresses of memory blocks)

UM10503

0x4008 6000

0x4010 2000

clocking
reset control
peripherals

0x400F 8000
high-speed GPIO

APB1
peripherals

0x4200 0000

0x4006 0000
0x4005 4000

Chapter 3: LPC43xx/LPC43Sxx Memory mapping

Rev. 2.4 — 22 August 2018

All information provided in this document is subject to legal disclaimers.

SSP1

0x400C 4000

0x400A 4000
0x400A 3000
0x400A 2000

0x4400 0000

reserved

reserved

0x400C 5000

0x400A 5000

Fig 9.

0xFFFF FFFF
APB3
peripherals

UM10503

NXP Semiconductors

Chapter 3: LPC43xx/LPC43Sxx Memory mapping

3.5 Memory map (parts with on-chip flash)
The memory map shown in Figure 10 and Figure 11 is global to both the Cortex-M4 and
the Cortex-M0 processors and all SRAM, flash, and EEPROM memory is shared between
both processors. Each processor uses its own ARM private bus memory map for the
NVIC and other system functions.

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UM10503

NXP Semiconductors

Chapter 3: LPC43xx/LPC43Sxx Memory mapping

4 GB

0xFFFF FFFF
reserved
0xE010 0000
ARM private bus
reserved
128 MB SPIFI data
256 MB dynamic external memory DYCS3
256 MB dynamic external memory DYCS2
reserved
peripheral bit band alias region
reserved

0x2000 0000
0x1F00 0000
0x1E00 0000
0x1D00 0000
0x1C00 0000

SGPIO

16 MB static external memory CS2

SPI

16 MB static external memory CS1

reserved

16 MB static external memory CS0

high-speed GPIO
reserved

0x1B08 0000

0x1B00 0000

reserved
256 kB flash B

reserved

256 kB flash B

APB peripherals #3
reserved

reserved

APB peripherals #2

0x1A08 0000
0x1A04 0000
0x1A00 0000

reserved

256 kB flash A

APB peripherals #1
256 kB flash A

reserved
APB peripherals #0

reserved

clocking/reset peripherals
RTC domain peripherals

0x1400 0000
0x1041 0000
0x1040 0000
0x1008 A000

0x4400 0000
0x4200 0000

0x4010 1000
0x4010 0000
0x400F 8000
0x400F 4000
0x400F 2000
0x400F 1000
0x400F 0000
0x400E 0000
0x400D 0000
0x400C 0000
0x400B 0000
0x400A 0000
0x4009 0000
0x4008 0000

0x4005 0000
0x4004 0000
0x4001 2000

2 kB SRAM (M0 subsystem)
16 kB SRAM (M0 subsystem)

AHB peripherals

1 GB

256 MB dynamic external memory DYCS1

64 MB SPIFI data

128 MB dynamic external memory DYCS0

reserved

0x4000 0000
0x3000 0000
0x2800 0000

reserved
0x2400 0000

64 kB ROM

32 MB AHB SRAM bit banding

reserved

0x2200 0000
reserved

32 kB + 8 kB local SRAM
0x1008 0000

0x2004 4000
16 kB EEPROM
reserved

reserved
4 x 16 kB AHB SRAM

0x1000 8000
0x1000 0000

0x6000 0000

reserved

0x1800 4800

0x1800 0000

0x7000 0000

0x4006 0000

8 kB ROM (M0 SERIAL)
reserved

0x1800 4000

0x8000 0000

reserved

0x1840 2000
0x1840 0000

0x8800 0000

0x4010 2000

16 MB static external memory CS3

reserved

0x1B04 0000

0xE000 0000

local SRAM/
external static memory banks

32 kB local SRAM
0 GB

256 MB shadow area

0x2004 0000
0x2001 0000
0x2000 0000
0x1000 0000
0x0000 0000
aaa-018954-um

Fig 10. Parts with on-chip flash: Memory mapping (overview)

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xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx
xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx

0x400E 5000

reserved

0x400E 4000

ADC1

0x400E 3000

ADC0

0x400E 2000

C_CAN0

0x400E 1000

DAC

0x400E 0000
0x400C 8000

I2C1

0x400C 7000

0xFFFF FFFF
APB3
peripherals

external memories and
ARM private bus

peripheral bit band alias region
reserved
SGPIO

GIMA

0x400C 5000
0x400C 4000

timer3

0x400C 3000

timer2

0x400C 2000

USART3

0x400C 1000

USART2

0x400C 0000
0x400B 0000

RI timer

APB3 peripherals

reserved

reserved

0x400A 4000
0x400A 3000
0x400A 2000
0x400A 1000
0x400A 0000
0x4008 A000
0x4008 9000
0x4008 8000
0x4008 7000

C_CAN1
I2S1
I2S0
I2C0

APB2
peripherals

RGU

0x4005 3000
0x4005 2000

CCU1

0x4005 1000

CGU

0x4005 0000

reserved

0x4005 0000
0x4004 7000

RTC/event monitor

0x4004 6000

OTP controller

0x4004 5000

event router

0x4004 4000

CREG

0x4004 3000

0x400F 2000

power mode control

0x4004 2000

0x400F 1000

backup registers

0x4004 1000

reserved
reserved

APB2 peripherals
reserved
APB1 peripherals
reserved

motor control PWM

APB0 peripherals
reserved

GPIO GROUP1 interrupt
GPIO GROUP0 interrupt
GPIO interrupts

0x4400 0000
0x4200 0000
0x4010 2000
0x4010 1000
0x4010 0000
0x400F 8000

reserved

APB1
peripherals

clocking
reset control
peripherals

reserved
high-speed GPIO

clocking/reset peripherals
RTC domain peripherals

SCU

0x4008 5000

timer1

0x4008 4000

timer0

0x4008 3000

SSP0

0x4008 2000

UART1 w/ modem

SRAM, flash, EEPROM memories,
SPIFI data, ROM
external memory banks

0x4008 1000

USART0

256 MB memory shadow area

0x4008 0000

WWDT

APB0
peripherals

0x400F 4000

RTC domain
peripherals

0x400F 0000

alarm timer

0x400E 0000
0x400D 0000

reserved

0x400C 0000

ethernet

0x400B 0000

reserved

0x400A 0000

EEPROM controller
flash B controller

0x4009 0000

flash A controller

0x4008 0000
0x4006 0000

reserved

0x4004 0000
0x4002 0000
0x4001 2000
0x4001 0000
0x4000 F000
0x4000 E000
0x4000 D000
0x4000 C000
0x4000 9000

LCD

0x4000 8000

USB1

0x4004 0000

0x4000 7000

USB0

0x4000 6000

0x4002 0000

EMC

0x4000 5000

0x4000 0000

SD/MMC

0x4000 4000

SPIFI

0x4000 3000

DMA

0x4000 2000

reserved

0x4000 1000

SCTimer/PWM

0x4000 0000

0x4005 0000

reserved
AHB peripherals

0x1000 0000
0x0000 0000

AHB
peripherals

002aah183-um

Fig 11. Parts with on-chip flash: Memory mapping (peripherals)

UM10503

43 of 1444

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0x4008 6000

0x4006 0000
0x4005 4000

Chapter 3: LPC43xx/LPC43Sxx Memory mapping

Rev. 2.4 — 22 August 2018

All information provided in this document is subject to legal disclaimers.

SPI

QEI
SSP1

reserved

CCU2

0x6000 0000
reserved

0x400C 6000

0x400A 5000

NXP Semiconductors

UM10503

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LPC436x/5x/3x/2x/1x/S6x/S5x/S3x

0x400F 0000

UM10503

NXP Semiconductors

Chapter 3: LPC43xx/LPC43Sxx Memory mapping

3.6 AHB Multilayer matrix configuration
The multilayer AHB matrix enables all bus masters to access any embedded memory as
well as external SPI flash memory connected to the SPIFI interface. When two or more
bus masters try to access the same slave, a round robin arbitration scheme is used; each
master takes turns accessing the slave in circular order. The access length is determined
by the burst access length of the master. For the CPU, the burst size is 1, for GPDMA, the
burst size can be up to 8. To optimize CPU performance, low-latency code should be
stored in a memory that is not accessed by other bus masters, especially masters that use
a long burst size.
To optimize the CPU performance, the ARM Cortex-M4 has three buses for Instruction
(code) (I) access, Data (D) access, and System (S) access. The I- and D-bus access
memory space is located below 0x2000 0000, the S-bus accesses the memory space
staring from 0x2000 0000. When instructions and data are kept in separate memories,
then code and data accesses can be done in parallel in one cycle. When code and data
are kept in the same memory, then instructions that load or store data may take two
cycles.
The LPC43xx peripherals are divided into AHB and APB peripherals. AHB peripherals
such as the USB and ethernet controllers are directly connected to the AHB matrix. APB
peripherals are connected to the AHB matrix via bus bridges.
The ARM-CortexM0 core M0SUB connects via a bridge to the main AHB matrix. This
bridge introduces an access latency when crossing from the M0SUB domain to the main
matrix domain. The bridge uses a write buffer to minimize latency; write accesses should
be used when possible. For example, when the M0SUB cor needs to read a block of data
one may get better performance (throughput) using GPDMA to write this block of data to
one of the local M0SUB SRAM. In this case, the latency is incurred once per burst instead
of every word.

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UM10503

NXP Semiconductors

Chapter 3: LPC43xx/LPC43Sxx Memory mapping

TEST/DEBUG
INTERFACE

ARM
CORTEX-M0
SUBSYSTEM
master
BRIDGE
TEST/DEBUG
INTERFACE

TEST/DEBUG
INTERFACE

FPU

ARM
CORTEX-M0

MPU

ARM
CORTEX-M4

DMA

slaves
USB1

LCD

SD/
MMC

masters

2 kB SRAM

USB0

APPLICATION

System
IDbus code code
bus bus

ETHERNET

HIGH-SPEED
PHY

16 kB SRAM
0

1
SPI
SGPIO
BRIDGE
slaves
64 kB ROM
128 kB LOCAL SRAM
72 kB LOCAL SRAM
32 kB AHB SRAM
16 kB + 16 kB
AHB SRAM
EXTERNAL
MEMORY
CONTROLLER

SPIFI
AHB PERIPHERALS
REGISTER
INTERFACES
BRIDGE0

APB0 PERIPHERALS

APB0 PERIPHERALS

BRIDGE

RTC PERIPHERALS

AHB MULTILAYER MATRIX
RTC PERIPHERALS
= master-slave connection

002aaf873

SGPIO and APB peripherals are connected to the matrix via bridges. See also Section 20.4.1 “SGPIO-to-AHB connection”.

Fig 12. AHB multilayer matrix connections (flashless parts)

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NXP Semiconductors

Chapter 3: LPC43xx/LPC43Sxx Memory mapping

TEST/DEBUG
INTERFACE

ARM
CORTEX-M0
SUBSYSTEM
master
BRIDGE
TEST/DEBUG
INTERFACE
MPU

FPU

ARM
CORTEX-M4
System
bus

TEST/DEBUG
INTERFACE

ARM
CORTEX-M0

DMA

APPLICATION

IDcode code
bus bus

ETHERNET

HIGH-SPEED
PHY

slaves
USB1

LCD

SD/
MMC

2 kB SRAM

masters

16 kB SRAM

USB0
0

1

SPI
SGPIO
BRIDGE
slaves
256/512 kB FLASH A
256/512 kB FLASH B
16 kB EEPROM
64 kB ROM
32 kB LOCAL SRAM
40 kB LOCAL SRAM
32 kB AHB SRAM
16 kB + 16 kB
AHB SRAM
EXTERNAL
MEMORY
CONTROLLER

SPIFI
AHB PERIPHERALS
REGISTER
INTERFACES
BRIDGE0

APB0 PERIPHERALS

APB0 PERIPHERALS

BRIDGE

RTC PERIPHERALS

AHB MULTILAYER MATRIX
RTC PERIPHERALS
= master-slave connection
aaa-018974

SGPIO and APB peripherals are connected to the matrix via bridges. See also Section 20.4.1 “SGPIO-to-AHB connection”.

Fig 13. AHB multilayer matrix master and slave connections (parts with on-chip flash)

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UM10503
Chapter 4: LPC43xx/LPC43Sxx One-Time Programmable
(OTP) memory and API
Rev. 2.4 — 22 August 2018

User manual

4.1 How to read this chapter
This chapter applies to all LPC43xx/LPC43Sxx parts with the following exceptions:.

• AES keys and AES functions are supported for parts LPC43Sxx only.
• The following bit must only be set for secure, flashless parts: JTAG_DISABLE in the
OTP memory bank 3, word 0 (bit 31).

• For flashless parts only: The unique part ID can be read from OTP bank 0, words 0 to
3 at memory location 0x4004 5000. (For parts with on-chip flash, use the ISP/IAP calls
to read the unique part ID.)
Different OTP API functions for programming the OTP banks are available depending on
boot ROM revision. Software library functions are available on LPCWare.com to be used
for programming OTP banks one and two when the OTP API functions are not available in
the ROM.
Table 12.

OTP bank programming API functions available in ROM

OTP API name

Offset

Flashless
parts
LPC4350/
30/20/
10

Parts with
flash;
LPC43xx;
die revision
‘-’

Parts with
flash; die
revision ‘A’
and higher

Secure parts, flashless; LPC43S50/30/
20/10

otp_ProgGP0

0x14

no

no

yes

use AES API aes_ProgramKey1

otp_ProgGP1

0x18

no

no

yes

use AES API aes_ProgramKey2

otp_ProgGP2

0x1C

no

no

yes

no

otp_ProgGP2_0

0x20

yes

yes

yes

yes

otp_ProgGP2_1

0x24

yes

yes

yes

yes

otp_ProgGP2_2

0x28

yes

yes

yes

yes

4.2 Features
• The OTP memory stores the following information:
– User programmable are the boot source, the USB vendor and product ID, and the
AES keys.
– Unused fields can be used to store other data.

• API support for programming the OTP in Boot ROM provided.

4.3 General description
The OTP memory contains four memory banks of 128 bits each. The first memory bank
(OTP bank 0) is reserved. The other three OTP banks are programmable. In non-secure
parts, OTP banks 1 and 2 are available for general-purpose data. In secure parts, OTP
banks 1 and 2 are used for AES keys. OTP bank 3 contains up to two user programmable
configuration words and two more words for general-purpose use.
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NXP Semiconductors

Chapter 4: LPC43xx/LPC43Sxx One-Time Programmable (OTP)

The virgin OTP state is all zeros. A zero value can be overwritten by a one, but a one in
any of the OTP bits cannot be changed.
Programming the OTP requires a higher voltage than reading. The read voltage is
generated internally. The programming voltage is supplied via pin VPP. The OTP
controller automatically selects the correct voltage. If the VPP pin is not connected, then
the OTP cannot be programmed. An API is provided to program data into the OTP.
The AES keys in the OTP memory used by secure parts are not readable by software.
Table 13.

OTP content for secure and non-secure parts

Secure devices

Non-secure devices

OTP Content
bank

Encrypted Software API
access

Content

Encrypted Software API
access

0

Reserved

-

-

-

1

-

-

-

-

AES key 1 for yes
secure boot
image

no

aes_ProgramKey1 User-defined; no
general
purpose 0

yes

otp_ProgGP0

2

AES key 2 for no
data

no

aes_ProgramKey2 User-defined; no
general
purpose 1

yes

otp_ProgGP1

3

Word 0:
Customer
control data

no

yes

otp_ProgBootSrc,
otp_ProgJTAGDis

yes

otp_ProgBootSrc

3

Word 1;
no
general
purpose word
0 or USB ID

yes

Same as for secure devices
otp_ProgGP2 or
otp_ProgGP2_0 or
otp_ProgUSBID

3

Words 2 to 3: no
General
purpose data
in words 1/2.

yes

otp_ProgGP2 or
otp_ProgGP2_1,
otp_ProgGP2_2

Word 0:
Customer
control data

no

Same as for secure devices

4.4 Register description
Table 14.

OTP memory description (OTP base address 0x4004 5000)

OTP
bank

Word

Access

Address
offset

Size

Description

Reference

0

0

Pre-programmed; cannot
be changed by the user.

0x000

32 bit

First 32 bit word of the unique part ID for
flashless parts. Reserved for parts with
on-chip flash.

-

0

1

Pre-programmed; cannot
be changed by the user.

0x004

32 bit

Second 32 bit word of the unique part ID for
flashless parts. Reserved for parts with
on-chip flash.

-

0

2

Pre-programmed; cannot
be changed by the user.

0x008

32 bit

Third 32 bit word of the unique part ID for
flashless parts. Reserved for parts with
on-chip flash.

-

0

3

Pre-programmed; cannot
be changed by the user.

0x00C

32 bit

Fourth 32 bit word of the unique part ID for
flashless parts. Reserved for parts with
on-chip flash.

-

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NXP Semiconductors

Chapter 4: LPC43xx/LPC43Sxx One-Time Programmable (OTP)

Table 14.

OTP memory description (OTP base address 0x4004 5000)

OTP
bank

Word

Access

1

0

1

Address
offset

Size

Description

Reference

User programmable; initial 0x010
state = 0

32 bit

General purpose OTP memory 0, word 0, or
AES key 1, word 0

-

1

User programmable; initial 0x014
state = 0

32 bit

General purpose OTP memory 0, word 1, or
AES0 key 1, word 1

-

1

2

User programmable; initial 0x018
state = 0

32 bit

General purpose OTP memory 0, word 2, or
AES0 key 1, word 2

-

1

3

User programmable; initial 0x01C
state = 0

32 bit

General purpose OTP memory 0, word 3, or
AES0 key 1, word 3

-

2

0

User programmable; initial 0x020
state = 0

32 bit

General purpose OTP memory 1, word 0, or
AES key 2, word 0

-

2

1

User programmable; initial 0x024
state = 0

32 bit

General purpose OTP memory 1, word 1, or
AES key 2, word 1

-

2

2

User programmable; initial 0x028
state = 0

32 bit

General purpose OTP memory 1, word 2, or
AES key 2, word 2

-

2

3

User programmable; initial 0x02C
state = 0

32 bit

General purpose OTP memory 1, word 3, or
AES key 2, word 3

-

3

0

User programmable; initial 0x030
state = 0

32 bit

Customer control data

Table 15

3

1

User programmable; initial 0x034
state = 0

32 bit

General purpose OTP memory 2, word 0, or
USB ID

Table 16

3

2

User programmable; initial 0x038
state = 0

32 bit

General purpose OTP memory 2, word 1

Table 17

3

3

User programmable; initial 0x03C
state = 0

32 bit

General purpose OTP memory 2, word 2

Table 18

Table 15.
Bit

Symbol

Value

Description

22:0

-

-

Reserved

23

USB_ID_ENABLE

24

UM10503

User manual

OTP memory bank 3, word 0 - Customer control data (address offset 0x030)

-

Setting this bit allows to enable OTP defined USB
vendor and product IDs. When enabled, the USB
driver uses the USB_VENDOR_ID and
USB_PRODUCT_ID values. If disabled, the NXP
vendor ID (0x1FC9) and product ID (0x000C) is
used.
0

Disabled

1

Enabled

-

Reserved

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NXP Semiconductors

Chapter 4: LPC43xx/LPC43Sxx One-Time Programmable (OTP)

Table 15.

OTP memory bank 3, word 0 - Customer control data (address offset 0x030)

Bit

Symbol

28:25

BOOT_SRC

Value

Description
Boot source selection in OTP. For details, see
Table 21.

0000

External pins

0001

UART0

0010

SPIFI

0011

EMC 8-bit

0100

EMC 16-bit

0101

EMC 32-bit

0110

USB0

0111

USB1

1000

SPI (via SSP)

1001

UART3

29

-

Reserved. Do not write to this bit.

30

-

Reserved. Do not write to this bit.

31

JTAG_DISABLE

If this bit set, JTAG cannot be enabled by software
and remains disabled.

Table 16.

OTP memory bank 3, word 1 - General purpose OTP memory 2, word 0, or USB ID
(address offset 0x034)

Bit

Symbol

Description

15:0

USB_VENDOR_ID

31:16

USB_PRODUCT_ID

If USB_ID_ENABLE bit not set, it is used as general purpose
OTP memory 2, word 0, GP2_0.

Table 17.

OTP memory bank 3, word 2 - General purpose OTP memory 2, word 1 (address
offset 0x038)

Bit

Symbol

Description

31:0

GP2_1

General purpose OTP memory 2, word 1. GP2_1.

Table 18.

OTP memory bank 3, word 3 - General purpose OTP memory 2, word 2 (address
offset 0x03C)

Bit

Symbol

Description

31:0

GP2_2

General purpose OTP memory 2, word 2. GP2_2.

4.5 OTP API
The OTP memory is controlled through a set of simple API calls located in the LPC43xx
ROM.
The API calls to the ROM are performed by executing functions which are pointed to by
pointer within the ROM driver table.

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Chapter 4: LPC43xx/LPC43Sxx One-Time Programmable (OTP)

Ptr to ROM Driver table
0x1040 0100

Device 0
ROM Driver Table

Ptr to Function 0

Ptr to Device Table 0

Ptr to Function 1

Ptr to OTP driver table

Ptr to Function 2

+0x04
+0x08

…

Ptr to Device Table 2

Ptr to Function n

…
Ptr to Device Table n

OTP Driver
otp_Init
otp_ProgBootSrc
otp_ProgJTAGDis
otp_ProgUSBID
Reserved
otp_ProgGP0
otp_ProgGP1
otp_ProgGP2
otp_ProgGP2_0
otp_ProgGP2_1
otp_ProgGP2_2
Reserved
Reserved
otp_GenRand

Fig 14. OTP driver pointer structure
Table 19.

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ROM driver pointers (main API entry point 0x1040 0100)

API

Address

Description

OTP

+0x04

Pointer to the OTP driver base

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Chapter 4: LPC43xx/LPC43Sxx One-Time Programmable (OTP)

4.5.1 OTP function allocation
Remark: See Section 4.1 for availability of OTP functions for different boot ROM versions.
Table 20.

OTP function allocation

Function

Offset

Description

OTP bank
OTP memory
programmed name

otp_Init

0x00

Initializes OTP controller.

-

-

3; word 0

Customer
control data

3; word 0

Customer
control data

3; word 1

Customer
control data

-

-

Parameter - void
Return- unsigned: see the general error codes.
otp_ProgBootSrc

0x04

Programs boot source in OTP bank 3, word 0 (customer
control data).
Parameter - unsigned src
Return- unsigned: see the general error codes.

otp_ProgJTAGDis 0x08

Set JTAG_DISABLE bit in OTP bank 3, word 0 (customer
control data). Use only when the device is AES capable.
Setting the JTAG_DISABLE bit disables the JTAG
permanently.
Parameter - void
Return- unsigned: see the general error codes.

otp_ProgUSBID

0x0C

Programs USB_ID.
Parameter - unsigned prod_id, unsigned vend_id
Return- unsigned: see the general error codes.

-

0x10

Reserved.

otp_ProgGP0

0x14

Programs the general purpose OTP memory GP0. Use only 1 (entire
if the device is not AES capable. The data parameter consists bank)
of four 32-bit words, one for each word in the memory bank.
The mask parameter contains a mask for each of the words
written. Mask bits that are set to 1 allow a write to the
corresponding OTP bit.

General
purpose
memory 0;
words 0 to 3

Parameter - unsigned *data, unsigned *mask
Return- unsigned: see the general error codes.
otp_ProgGP1

0x18

Programs the general purpose OTP memory GP1. Use only 2 (entire
if the device is not AES capable. The data parameter consists bank)
of four 32-bit words, one for each word in the memory bank.
The mask parameter contains a mask for each of the words
written. Mask bits that are set to 1 allow a write to the
corresponding OTP bit.

General
purpose
memory 1;
words 0 to 3

Parameter - unsigned *data, unsigned *mask
Return- unsigned: see the general error codes.
otp_ProgGP2

0x1C

Programs the general purpose OTP memory GP2 (however,
writes to word 0, which contains customer control data are
ignored). Use for customer-specific data. The data parameter
consists of four 32-bit words, one for each word in the
memory bank. The mask parameter contains a mask for each
of the words written. Mask bits that are set to 1 allow a write
to the corresponding OTP bit.

3 (word 1,
word 2, word
3); writes to
word 0 are
ignored

General
purpose
memory 2;
words 1 to 3;

Parameter - unsigned *data, unsigned *mask
Return- unsigned: see the general error codes.

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Chapter 4: LPC43xx/LPC43Sxx One-Time Programmable (OTP)

Table 20.

OTP function allocation

Function

Offset

Description

OTP bank
OTP memory
programmed name

otp_ProgGP2_0

0x20

Programs the general purpose OTP memory GP2 word 0.
Use for customer-specific data. The data parameter is one
32-bit word. The mask parameter contains a mask for the
word written. Mask bits that are set to 1 allow a write to the
corresponding OTP bit.

3 (word 1)

General
purpose
memory 2,
word 0

3 (word 2)

General
purpose
memory 2,
word 1

3 (word 3)

General
purpose
memory 2,
word 2

Remark: This function can only be used if the USB ID is not
programmed. Otherwise, error code ERR_OTP_USB_ID_ENABLED
is returned.
Parameter - unsigned data, unsigned mask
Return- unsigned: see the general error codes.
otp_ProgGP2_1

0x24

Programs the general purpose OTP memory GP2 word 1.
Use for customer-specific data.The data parameter is one
32-bit word. The mask parameter contains a mask for the
word written. Mask bits that are set to 1 allow a write to the
corresponding OTP bit.
Parameter - unsigned data, unsigned mask
Return- unsigned: see the general error codes.

otp_ProgGP2_2

0x28

Programs the general purpose OTP memory GP2 word 2.
Use for customer-specific data.The data parameter is one
32-bit word. The mask parameter contains a mask for the
word written. Mask bits that are set to 1 allow a write to the
corresponding OTP bit.
Parameter - unsigned data, unsigned mask
Return- unsigned: see the general error codes.

-

0x2C

Reserved.

-

-

-

0x30

Reserved.

-

-

otp_GenRand

0x34

Generate new random number using the hardware Random
Number Generator (RNG).

-

-

Parameter - void
Return- unsigned: see the general error codes.

4.5.1.1 OTP API error codes
ERR_OTP_BASE = 0x00070000,
/*0x00070001*/ ERR_OTP_WR_ENABLE_INVALID = ERR_OTP_BASE+1
/*0x00070002*/ ERR_OTP_SOME_BITS_ALREADY_PROGRAMMED
/*0x00070003*/ ERR_OTP_ALL_DATA_OR_MASK_ZERO
/*0x00070004*/ ERR_OTP_WRITE_ACCESS_LOCKED
/*0x00070005*/ ERR_OTP_READ_DATA_MISMATCH
/*0x00070006*/ ERR_OTP_USB_ID_ENABLED
/*0x00070007*/ ERR_OTP_ETH_MAC_ENABLED
/*0x00070008*/ ERR_OTP_AES_KEYS_ENABLED
/*0x00070009*/ ERR_OTP_ILLEGAL_BANK
LPC_OK = 0
Also see Section 53.2 “Error codes”.

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5.1 How to read this chapter
This chapter applies to all parts. AES support is available on LPC43Sxx parts only. See
Chapter 7 “LPC43Sxx Boot ROM for secure parts”.
Flash-based parts boot from on-chip flash by default (see Chapter 6), but other boot
modes described in this chapter are also supported. The UART boot mode is only
supported for flashless parts. The secure boot from USART3 is not supported for
LPC43Sxx parts.

5.1.1 Determine the boot code version
For parts with on-chip flash, the boot code version can be determined using ISP or IAP
calls. See Table 46 “ISP Read Boot Code version number command” and Table 57 “IAP
Read Boot Code version number command”.
For flashless parts, use ISP to read the boot code version number (see Table 46) or read
memory location 0x1040 7FFC which encodes the boot code version as follows:
Value 0x000B 000n at location 0x1040 7FFC reads as boot code version 11.n.

5.2 Features
The boot ROM memory includes the following features:

• ROM memory size is 64 kB.
• Supports booting from UART interfaces, external static memory such as NOR flash,
SPI flash, quad SPI flash, high-speed USB (USB0), and USB1.

• Includes API for OTP programming.
• Includes USB drivers.
• ISP mode for loading data to on-chip SRAM and execute code from this location.

5.3 Functional description
The internal ROM memory is used to store the boot code. After a reset, the ARM
processor will start its code execution from this memory.
The ARM core is configured to start executing code, upon reset, with the program counter
being set to the value 0x0000 0000. The LPC43xx contains a shadow pointer that allows
areas of memory to be mapped to address 0x0000 0000. The default value of the shadow
pointer is 0x1040 0000, ensuring that the code contained in the boot ROM is executed at
reset.
For flash-based parts, the part boots from internal flash by default (boot pin P2_7 is
HIGH). If the boot pin is sampled LOW on reset, the boot source is determined by the
setting of the OTP or the states of pins P2_9, P2_8, P1_2, and P1_1. For details of the
boot process for flash-based parts, see Figure 15.
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For flash-based and flashless parts alike, several external sources are available for
booting depending on the values of the OTP bits BOOT_SRC (see Section 4.4). If the
OTP memory is not programmed or the BOOT_SRC bits are all zero, the boot mode is
determined by the states of the boot pins P2_9, P2_8, P1_2, and P1_1.
Table 21.

Boot mode when OTP BOOT_SRC bits are programmed

Boot mode

BOOT_SRC BOOT_SRC BOOT_SRC
bit 3
bit 2
bit 1

BOOT_SRC Description
bit 0

Boot pins

0

0

0

0

Boot source is defined by the reset state of P1_1,
P1_2, P2_9, and P2_8 pins. See Table 22.

USART0

0

0

0

1

Boot from device connected to USART0 using pins
P2_0 and P2_1. For flash parts, enter UART ISP
mode.

SPIFI

0

0

1

0

Boot from Quad SPI flash connected to the SPIFI
interface using pins P3_3 to P3_8.

EMC 8-bit

0

0

1

1

Boot from external static memory (such as NOR
flash) using CS0 and an 8-bit data bus.

EMC 16-bit

0

1

0

0

Boot from external static memory (such as NOR
flash) using CS0 and a 16-bit data bus.

EMC 32-bit

0

1

0

1

Boot from external static memory (such as NOR
flash) using CS0 and a 32-bit data bus.

USB0

0

1

1

0

Boot from USB0.

USB1

0

1

1

1

Boot from USB1.

SPI (SSP)

1

0

0

0

Boot from SPI flash connected to the SSP0
interface on P3_3 (function SSP0_SCK), P3_6
(function SSP0_SSEL), P3_7 (function
SSP0_MSIO), and P3_8 (function SSP0_MOSI)[1].

USART3

1

0

0

1

Boot from device connected to USART3 using pins
P2_3 and P2_4. For flash parts, enter UART ISP
mode. The secure boot from USART3 is not
supported for LPC43Sxx parts.

[1]

The boot loader programs the appropriate pin function at reset to boot using SSP0.
Remark: Pin functions for SPIFI and SSP0 boot are different.

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Chapter 5: LPC43xx Boot ROM

Table 22.

Boot mode when OTP BOOT_SRC bits are zero

Boot mode

P2_9

P2_8

P1_2

P1_1

Description

USART0

LOW

LOW

LOW

LOW

Boot from device connected to USART0 using pins P2_0 and
P2_1. For flash parts, enter UART ISP mode.

SPIFI

LOW

LOW

LOW

HIGH

Boot from Quad SPI flash connected to the SPIFI interface on
P3_3 to P3_8[1].

EMC 8-bit

LOW

LOW

HIGH

LOW

Boot from external static memory (such as NOR flash) using CS0
and an 8-bit data bus.

EMC 16-bit

LOW

LOW

HIGH

HIGH

Boot from external static memory (such as NOR flash) using CS0
and a 16-bit data bus.

EMC 32-bit

LOW

HIGH

LOW

LOW

Boot from external static memory (such as NOR flash) using CS0
and a 32-bit data bus.

USB0

LOW

HIGH

LOW

HIGH

Boot from USB0.

USB1

LOW

HIGH

HIGH

LOW

Boot from USB1.

SPI (SSP)

LOW

HIGH

HIGH

HIGH

Boot from SPI flash connected to the SSP0 interface on P3_3
(function SSP0_SCK), P3_6 (function SSP0_SSEL), P3_7
(function SSP0_MISO), and P3_8 (function SSP0_MOSI)[1].

USART3

HIGH

LOW

LOW

LOW

Boot from device connected to USART3 using pins P2_3 and
P2_4. For flash parts, enter UART ISP mode. The secure boot
from USART3 is not supported for LPC43Sxx parts.

[1]

The boot loader programs the appropriate pin function at reset to boot from SPIFI or SSP0.
Remark: Pin functions for SPIFI and SSP0 boot are different.

5.3.1 Boot process for parts with internal flash
Parts with flash boot from on-chip flash if PIO2_7 is sampled HIGH. See Figure 15.
If pin P2_7 is sampled LOW, the boot loader checks the OTP bits and/or the external boot
pins to determine the communication port. If the OTP bits and boot pins are set to
USART0 or USART3, the part enters UART ISP mode.
A boot image must have a valid signature to be a valid flash image (see Section 6.4.4.1
“Criterion for Valid User Code”), and on parts with dual flash banks, only one flash bank
should contain a valid image. You can use the ISP/IAP command Set active boot flash
bank to configure one flash bank with the valid image (see Section 6.8.12 and
Section 6.7.15). If both images are valid, the boot loader loads the image located in flash
bank A.
Remark: If the boot loader image is located in flash bank B and data is stored in flash
bank A, then ensure that the data in flash bank A does not appear to be a valid image. An
example of a data set that would be interpreted as a valid image is a set in which the first
eight words of flash bank A contain all zeros.
This implies that the data in the first 8 locations of sector 0 in flash bank A cannot be
chosen freely. For example, choose data in location 8 in such a way that a non-valid
image is created. See Section 6.4.4.1 “Criterion for Valid User Code”.

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Chapter 5: LPC43xx Boot ROM

RESET

INITIALIZE

CRP1/2/3 ENABLED?

no

ENABLE DEBUG

A
yes
USER CODE
VALID in FLASH
BANK A?

no

yes

CRP3 ENABLED?
no
yes

USER CODE VALID?
no
yes

Enter ISP
MODE?
(P2_7=LOW)

USER CODE
VALID in FLASH
BANK B?
no

yes

no

yes

EXECUTE INTERNAL
USER CODE
A

check OTP/boot pins

boot from external boot source
enter UART ISP if the boot source is USART0 or USART3

Fig 15. Boot process flowchart for LPC43xx parts with flash

5.3.2 Boot process for parts without flash
The top level boot process is illustrated in Figure 16. The boot starts after Reset is
released. The IRC is selected as CPU clock,the Cortex-M4 starts the boot loader, and
JTAG access is enabled.
As shown in Figure 16, the boot ROM determines the boot mode based on the OTP
BOOT_SRC value or reset state of the pins P1_1, P1_2, P2_8, and P2_9. The boot ROM
copies the image to internal SRAM at location 0x1000 0000 and jumps to that location (it
sets ARM's to 0x1000 0000) after image verification. Hence the images for LPC43xx
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should be compiled with entry point at 0x0000 0000. On AES capable parts with a
programmed AES key, the image and header are authenticated using the CMAC
algorithm prior to copying to the internal SRAM. If authentication fails the device is reset.
On non-secure parts, the image and header are not authenticated. If the image is not
preceded by a header then the image is not copied to SRAM but assumed to be
executable as-is. In that case the shadow pointer is set to the first address location of the
external boot memory. The header-less images should be compiled with entry point at
0x0000 0000, the same as for an image with header.
Remark: When the boot process fails, pin P1_1 toggles at a 1 Hz rate for 60 seconds.
After 60 seconds, the device is reset.

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CPU clock
= IRC
12MHz

RESET

AES
capable and
key1
programmed?

disable
IRQ &
MPU

no

yes
load AES
key

enable
JTAG

CPU clock
=
96MHz

ISP pin
P2_7
LOW ?

no

yes
check BOOT _SRC

=1
=0
check pins
P2_9,P2_8,P1_2,
P1_1

=0

=6... 9

enter ISP
mode (USART0)

=2..5

>10

=1..4
BOOT _SRC=2
or pins =1

>9

BOOT _SRC=3
or pins =2

BOOT_SRC=4
or pins =3

BOOT_SRC=5
or pins =4

BOOT_SRC=1
or pins =0
BOOT _SRC=9
or pins =8

UART0
boot

BOOT _SRC=6
or pins =5

UART3
boot

SPIFI
boot

BOOT _SRC=7 BOOT _SRC=8
or pins =6
or pins =7

USB0
boot

Header
present?

no

yes

AES key1
programmed?

no

no

valid
Header?
no

AES
capable?

AES
capable and
key1
programmed?

yes

no

no

yes

valid
encrypted
header
and image
hash
authentic

EMC 32b
boot

yes

yes

yes

EMC 16b
boot

SPI
(SSP)
boot

USB1
boot

valid
Header?

EMC 8b
boot

no

yes
decrypt image to SRAM
at 0x1000 0000

copy image to
SRAM at
0x1000 0000

60s timeout
toggle pin
P1_1

set program counter
= 0x1000 0000,
run

set program counter
= 0x1000 0000,
run

Reset

set program counter
= boot address,
run

For details on secure booting using the AES engine, see Chapter 7 “LPC43Sxx Boot ROM for secure parts”.

Fig 16. Boot process for parts without flash

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Chapter 5: LPC43xx Boot ROM

5.3.3 Boot image header format
Non-AES capable products may boot from an image with header or execute directly from
the boot source if the boot source is memory mapped (see Table 23). When no valid
header is found, then the CPU will try to execute code from the first location of the
memory mapped boot source. The user should take care that this location contains
executable code, otherwise a hard fault exception will occur. This exception jumps to a
while(1) loop.
Table 23.

Boot image header use

Boot source

Memory mapped

Header required

USART0

no

yes

SPIFI

yes

no

EMC 8-bit

yes

no

EMC 16-bit

yes

no

EMC 32-bit

yes

no

USB0

no

yes

USB1

no

yes

SPI (SSP)

no

yes

USART3

no

yes

The image must be preceded by a header that has the layout described in Table 24. For
encrypted images the header must be encrypted with the AES user key1 and initialization
vector iv = 0. The user key is stored in the OTP (see Table 13). Non-encrypted images
may omit the header.
Table 24.

Boot image header description

Address

Name

Description

size [bits]

5:0

AES_ACTIVE[1]

AES encryption active

6

0x25 (100101): AES encryption active
0x1A (011010): AES encryption not active
all other values: invalid image
HASH_ACTIVE[1]

7:6

2

Indicates whether a hash is used:
00: reserved for non-secure parts.
01: reserved
10: reserved
11: no hash is used

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15:8

RESERVED

11...11 (binary)

8

31:16

HASH_SIZE[2]

Size of image copied to internal SRAM at
boot time.

16

95:32

HASH_VALUE

Reserved for non-secure parts.

64

127:96

RESERVED

11...11 (binary)

32

[1]

Can only be active if device is AES capable (secure part). Otherwise the image is considered invalid.

[2]

The image size should be set to no more than the size of the SRAM located at 0x1000 0000.

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Chapter 5: LPC43xx Boot ROM

5.3.4 Boot modes
5.3.4.1 UART boot mode
Figure 17 details the boot-flow steps of the UART boot mode. The execution of this mode
occurs only if the boot mode is set accordingly (see boot modes Table 21 and Table 22).
As illustrated in Figure 17, configure the UART with the following settings:

•
•
•
•

Baudrate = 115200, 57600, 38400, 19200, or 9600
Data bits = 8
Parity = None
Stop bits = 1

Auto baud is active; boot waits until 0x3F is received and responds with “OK”. This should
be followed by the header and image. The boot ROM doesn't implement any flow control
or any handshake mechanisms during file transfer.
After the boot image is downloaded, it is checked (based on header information) to be a
valid or invalid image and OK respectively FAILED is sent to a host followed by CR and
LF. Finally, the full boot image is copied, processed to address 0x10000000 and executed
from there.

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Setup Pin
Configuration
UART0 P2_1, P2_0 or
UART3 P2_3,P2_4

Init UART assuming
PCLK =12MHz

receive
character

no
char
= 0x3F?
yes
transmit
“OK” CR
LF

receive
image

valid
image?

no

transmit
“FAILED”
CR LF

yes
transmit
“OK” CR
LF

see main boot flow

Fig 17. UART boot process

5.3.4.2 EMC boot modes
The EMC boot process follows the main flow shown in Figure 18. The CPU clock is set to
96 MHz, and a non-AES capable part will boot directly from EMC when the image does
not contain a header. EMC uses 0xE wait states providing approximately 156 ns delay
before capturing data.
Note that the number of address bits selected in pin configuration is initially EMC_A[13:0].
All higher address bit pins are configured as pull down but not actively driven. After
reading the header, the address bits are extended to be in line with the image size as
defined by HASH_SIZE, e.g. if HASH_SIZE is 100 kB then pins EMC_A[16:14] are
configured since 217 > 100 kB. When booting without header, then the image should
configure extra address pins if more are needed beyond the initially configured
EMC_A[13:0]. This configuration should happen in the initial 16 kB area of the image.
If no header is present it is assumed that the image is located at address 0x1C00 0000
and is executed from there.

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Setup Pin
Configuration
EMC _A[13:0]
EMC_CS0

Read Image
Header

Image size
> 16384-16

no

yes
Extend
address bus

see main boot flow

Fig 18. EMC boot process

5.3.4.3 SPI boot mode
The boot uses SSP0 in SPI mode. The SPI clock is 18 MHz.
Figure 19 details the boot-flow steps of the SPI flash boot mode. The execution of this
mode occurs only if the boot mode is set accordingly (see boot modes Table 21 and
Table 22).

Setup clock
SSP0_SCK=
18MHz

Setup Pin
Configuration
P3_3, P3_6..P3_8

see main boot flow

Fig 19. SPI boot process

5.3.4.4 SPIFI boot mode
Figure 20 details the boot-flow steps of the Quad SPI flash boot mode. The execution of
this mode occurs only if the boot mode is set accordingly (see boot modes in Table 21
andTable 22). The boot code sets the SPIFI clock to 18 MHz at the beginning of the boot
process and checks for the type of SPI flash device. For an SPI flash, the part boots with a
18 MHz clock. For a quad SPI flash device, the part boots with a 32 MHz clock. If the
detected device is unknown, the SPIFI clock is reduced to 18 MHz.
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If no header is present, it is assumed that the image is located on address 0x8000 0000
and is executed from there.

Setup clock
SPIFI_SCK=
32MHz

Setup Pin
Configuration
P3_3..P3_8

Detect device

no

known
device?

yes
no
SPIFI_SCK=
18MHz

yes
if SQI device
supported
then 4-bit I/O
will be used

device
error?

activate
Vendor_ID
specific driver

see main boot flow

Reset

Fig 20. SPIFI boot process

5.3.4.4.1

Supported QSPI devices
Multiple QSPI devices from various vendors can be used with the SPIFI interface and the
SPIFI API available on nxp.com.
LPC43xx devices support boot from flash. The boot code sets the SPIFI clock to
32 MHz at the beginning of the boot process and checks for the type of SPI flash device. If
the detected device is not recognized by LPC43xx, the SPIFI clock is reduced to 18 MHz.
The devices listed in Table 25 are tested to work as boot devices for the LPC43xx and
with the SPIFI API.
Remark: All QSPI devices have been tested at an operating voltage of 3.3 V.

Table 25.

QSPI devices supported by the boot code and the SPIFI API

Manufacturer

Device

Exit from no opcode
mode

Comment

Chingis

PM25LD040, PM25LD010C,
PM25LD020C, PM25LD512C,
PM25LD256C, PM25LQ032C

Yes

-

Giga Device

GD25Q80

Yes

-

Macronix

MX25L6435E, MX25L8006E,
MX25L1606E, MX25L8035E,
MX25L1633E, MX25L3235E,
MX25L6435E, MX25L12835E,
MX25L25635E, MX1635E

Yes

-

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Table 25.

QSPI devices supported by the boot code and the SPIFI API

Manufacturer

Micron

Spansion

Device

Exit from no opcode
mode

Comment

MX25L12835F, MX25L25635F

Yes

These devices take longer time to be ready
after power on. You may need to delay the
startup of LPC43xx. One way to achieve this
sequence is to delay RESETN signal of
LPC43xx.

M25PX80, M25PX16,
M25PX32, M25PX64, M25P10,
M25P16, M25P32, M25P64,
M25P80

Yes

-

N25Q032A, N25Q064A,
N25Q128A, N25Q256A

No

LPC43xx support cold boot with these devices.
May not boot when LPC43xx is reset and serial
flash is in no Opcode mode. In case of planned
reset, MCU can get serial flash out of No
Opcode mode before resetting itself.

S25FL032P, S25FL064P,
S25FL128S, S25FL256S,
S25FL256S, S25FL129P,
S25FL004K, S25FL008K,

Yes

-

Yes

-

W25Q80BV, W25Q16DV,
Yes
W25Q32FV, W25Q64FV,
W25Q128FV, W25Q256FV,
W25Q32JVSIQ, W25Q64JVSIQ

-

S25FL016K, S25FL032K,
S25FL064K, S25FL116K,
S25FL132K, S25FL164K,
S25FL127S
SST (Microchip) SST25VF064, SST25VF016
Winbond

Remark: In addition, you might enable a QSPI device to boot by adding external circuitry
to delay the LPC43xx reset signal and provide extra time for the QSPI device to come up.
To boot from serial flashes, it is recommended that customers fully characterize the timing
in their applications.
Devices that comply with the following guidelines are expected to support the boot code:

• Any device that can accept a 03 read serial opcode after receiving an FF opcode is
expected to boot successfully.

• A device that switches to quad opcodes and doesn't return after an 0xff reset to serial
mode might not boot after a reset.
Remark: After booting, include the SPIFI API driver in your firmware image and use it to
re-initialize the SPIFI device for best performance.

5.3.4.5 USB boot mode
For booting from USB, two USB interfaces are available. USB0 supports high-speed and
full-speed while USB1 supports only full-speed. This boot mode requires that a 12 MHz
external crystal is connected to the XTAL1/2 pins. The boot code configures the CGU
accordingly. The USB clock is respectively set to 480 MHz or 60 MHz. USB1 requires the
VBUS pin to be set correctly.
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Initially, the USB0 PHY is disabled to save power. After it is enabled, enumeration can
start. The DFU class is used to download a boot image. After receiving a boot image from
a host, the image is validated based on a set of rules mentioned earlier. If valid, the image
is processed accordingly to address 0x1000 0000 and executed from there.
USB product and vendor ID are defined by the OTP (see Table 15 and Table 16).

USB0

Boot
source?

USB1

Setup clock
USB_CLK=480MHz
Enable HS PHY

Setup clock
USB_CLK=60MHz
Setup VBUS pin P2_5

DFU
enumerate

receive image

see main boot flow

Fig 21. USB boot process

5.3.5 Boot process timing
The following parameters describe the timing of the boot process:
Table 26.

Typical boot process timing parameters

Parameter

Description

Value

t_a

Check boot selection pins

< 1.25 s

t_b

Initialize device

250 s[1]; 180 s[2]; 200 s[3]

t_c

Copy image to embedded SRAM

< 0.3 s

If part is executing from external
flash with no copy
If the image is encrypted or must
be copied
[1]

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< 1 s to 10000 s
depending on the size of the image and the
speed of the boot memory

For flashless parts LPC4350/30/20/10.

[2]

For parts with on-chip flash; booting from flash.

[3]

For parts with on-chip flash; booting from an external source.

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IRC12
stable

IRC12
starts

IRC12

RESET
VDDREG

valid
threshold

GND
22 μs
supply
ramp up

0.5μs; IRC stability count
boot time
user code
ta μs

processor status

check boot
selection
pins

tb μs
initialise
device

tc μs
copy image to
embedded
SRAM

Fig 22. Boot process timing

5.3.6 UART ISP
In-System programming (ISP) is programming or re-programming the on-chip SRAM
memory using the boot loader software and the USART0 serial port. For flash parts,
USART3 is available for ISP communication as well (see Table 21 and Table 22). ISP can
be performed when the part resides in the end user board.
A LOW level on pin P2_7 after reset indicates hardware request to enter ISP mode.
ISP commands include preparing the on-chip flash for erase and write operation, reading,
writing, and erasing flash, and executing code from flash. For flashless parts, a limited set
of ISP commands is supported which allows to load data into on-chip SRAM and execute
code from on-chip SRAM. For details, see Chapter 6.

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IAP
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6.1 How to read this chapter
The flash programming ISP is available for parts with on-chip flash. A reduced set of
In-System-Programming (ISP) commands is supported for flashless parts (see Table 33).
See Chapter 5 for details on the boot process.
IAP commands are only supported for parts with on-chip flash.

6.2 Basic configuration
• The flash banks are reset by the FLASHA_RST and FLASHB_RST (reset # 25/29).
• The flash accelerator and the flash access time are controlled by the FLASHCFGA
and FLASHCFGB registers in the CREG block (see Table 101 and Table 102).

• The flash bank interrupts are ORed with the interrupts from the EEPROM and are
connected to interrupt slot #4 in the NVIC.

• If the application uses the IAP interface, it must reserve the SRAM space used by IAP
as outlined in Section 6.4.5.8 “RAM used by IAP command handler”.
The ISP is configured as follows:

• The ISP mode is entered when pin P2_7 is pulled LOW for parts with and without
on-chip flash.
– On parts with on-chip flash, ISP communication uses USART0 or USART3
depending on the OTP bits and/or boot pins (see Section 5.3).
– On flashless parts, ISP communication always uses USART0.
Table 27.

ISP clocking and power control

ISP command clock CCLK

Base clock

Branch clock

Operating
frequency

Notes

BASE_M4_CLK

CLK_M4_BUS

up to
204 MHz

-

6.3 Features
• In-System Programming: In-System programming (ISP) is programming or
reprogramming the on-chip flash memory, using the boot loader software and
USART0or USART3 serial port. This can be done when the part resides in the
end-user board.

• For parts without on-chip flash, ISP allows to load data to on-chip SRAM and to
execute code from on-chip SRAM using USART0.

• In Application Programming: In-Application (IAP) programming is performing erase
and write operation on the on-chip flash memory, as directed by the end-user
application code.
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• Flash signature generation: built-in hardware can generate a signature for a range of
flash addresses or for the entire flash memory.

6.4 General description
The boot loader controls initial operation after reset and also provides the tools for
programming the flash memory. This could be initial programming of a blank device,
erasure and re-programming of a previously programmed device, or programming of the
flash memory by the application program in a running system.
Remark: The initial value of the flash memory and the memory value after an erase
operation is all 1s.
The boot loader code is executed every time the part is powered on or reset. The boot
loader can execute the ISP command handler or the user application code.
A HIGH level after reset on pin P2_7, starts the boot process either from on-chip flash if
available or from an external boot source for flashless parts depending on the
configuration of the OTP memory or the boot pins (see Chapter 5).
A LOW level after reset on pin P2_7 indicates an external hardware request to start the
ISP command handler:

• On parts with on-chip flash, the setting of the OTP bits and the boot pins determine
which USART (USART0 or USART3) is configured for ISP communication (see
Section 5.3).

• On flashless parts, ISP communication uses USART0 regardless of the settings of the
OTP bits or the boot pins.
When the ISP mode is entered after a power-on-reset, the IRC and PLL1 are used to
generate the core clock of 96 MHz. Pins P2_0 and P2_1 are used for communication with
the USART0 and pins P2_3 and P2_4 are used for USART3. The UART PCLK (from
BASE_UART0/3_CLK) is set to the IRC (12 MHz).
After determining the host’s baud rate, the test string “Synchronized” is sent to a host.
After a successful handshake, ISP enters the command interpret mode.
Table 28.

ISP pin P2_7

Flash image

Action

HIGH

Valid flash image

Boot from flash.

HIGH

Invalid flash
image

Check OTP for ISP source pins (USART0 or USART3) If
OTP BOOT_SRC = 0x0, check boot pins. See
Section 5.3.

LOW

-

Check OTP for ISP mode or external boot. If OTP
BOOT_SRC = 0x0 and boot pins are all LOW, enter ISP
mode via USART0.See Section 5.3.

Table 29.

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ISP functionality for flash parts

ISP functionality for flash-less parts

ISP pin P2_7

Action

HIGH

Boot from external source as indicated by OTP or boot pins. See Section 5.3.

LOW

Enter ISP mode using USART0, pins P2_0 and P2_1
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6.4.1 Sampling of pin P2_7
Assuming that power supply pins are on their nominal levels when the rising edge on
RESET pin is generated, it may take up to 3 ms before P2_7 is sampled and the decision
on whether to continue with user code or ISP handler is made.
If a valid user program is found, then the execution control is transferred to it. If a valid
user program is not found, the boot process defaults to the ISP mode using USART0 and
the auto-baud routine is invoked.
Pin P2_7 is used as a hardware request signal for ISP and requires special attention. It is
recommended to provide external hardware (a pull-up resistor or other device) to put the
pin in a defined state. Otherwise unintended entry into ISP mode may occur.

6.4.2 Boot process for flashless parts
See Figure 16 for the boot process flowchart for flashless parts. If P2_7 is HIGH, the boot
code samples the OTP and the boot pins to determine the boot source. If P2_7 is LOW,
the boot code configures USART0 for ISP communication.

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6.4.3 Boot process for parts with internal flash
See Section 5.3.1 “Boot process for parts with internal flash”.

6.4.4 Memory map after any reset
When a user program begins execution after reset, the interrupt vectors are set to point to
the beginning of flash memory (see Figure 10).

6.4.4.1 Criterion for Valid User Code
The reserved Cortex-M4 exception vector location 7 (offset 0x 001C in the vector table)
should contain the 2’s complement of the check-sum of table entries 0 through 6. This
causes the checksum of the first 8 table entries to be 0. The boot loader code checksums
the first 8 locations in sector 0 of the flash. If the result is 0, then execution control is
transferred to the user code.
If the signature is not valid, the auto-baud routine synchronizes with the host via serial port
0. The host should send a “?” (0x3F) as a synchronization character and wait for a
response. The host side serial port settings should be 8 data bits, 1 stop bit and no parity.
The auto-baud routine measures the bit time of the received synchronization character in
terms of its own frequency and programs the baud rate generator of the serial port. It also
sends an ASCII string ("Synchronized") to the host. In response to this the host
should send the same string ("Synchronized"). The auto-baud routine looks at
the received characters to verify synchronization. If synchronization is verified then
"OK" string is sent to the host. The host should respond by sending
“0" for backwards compatibility with existing tools. "OK" string is
sent to the host after receiving “0". If synchronization is not verified then the
auto-baud routine waits again for a synchronization character.
Once the UART has established synchronization, the boot loader invokes the ISP
command handler. For safety reasons an "Unlock" command is required before executing
the commands resulting in flash erase/write operations and the "Go" command. The rest
of the commands can be executed without the unlock command. The Unlock command is
required to be executed once per ISP session. The Unlock command is explained in
Section 6.7.

6.4.5 Communication protocol
All ISP commands should be sent as single ASCII strings. Strings should be terminated
with Carriage Return (CR) and/or Line Feed (LF) control characters. Extra  and
 characters are ignored. All ISP responses are sent as  terminated ASCII
strings. Data is sent and received in UU-encoded format.

6.4.5.1 ISP command format
"Command Parameter_0 Parameter_1 … Parameter_n" "Data" (Data only for
Write commands).

6.4.5.2 ISP response format
"Return_CodeResponse_0Response_1 …
Response_n" "Data" (Data only for Read commands).

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6.4.5.3 ISP data format
The data stream is in UU-encoded format. The UU-encode algorithm converts 3 B of
binary data in to 4 B of printable ASCII character set. It is more efficient than Hex format
which converts 1 byte of binary data in to 2 bytes of ASCII hex. The sender should send
the check-sum after transmitting 20 UU-encoded lines. The length of any UU-encoded line
should not exceed 61 characters (bytes) i.e. it can hold 45 data bytes. The receiver should
compare it with the check-sum of the received bytes. If the check-sum matches then the
receiver should respond with "OK" to continue further transmission. If the
check-sum does not match the receiver should respond with "RESEND". In
response the sender should retransmit the bytes.

6.4.5.4 ISP flow control
A software XON/XOFF flow control scheme is used to prevent data loss due to buffer
overrun. When the data arrives rapidly, the ASCII control character DC3 (0x13) is sent to
stop the flow of data. Data flow is resumed by sending the ASCII control character DC1
(0x11). The host should also support the same flow control scheme.

6.4.5.5 ISP command abort
Commands can be aborted by sending the ASCII control character "ESC" (0x1B). This
feature is not documented as a command under "ISP Commands" section. Once the
escape code is received the ISP command handler waits for a new command.

6.4.5.6 Interrupts during IAP
The on-chip flash memory is not accessible during erase/write operations. When the user
application code starts executing the interrupt vectors from the user flash area are active.
The user should either disable interrupts, or ensure that user interrupt vectors are active in
RAM and that the interrupt handlers reside in RAM, before making a flash erase/write IAP
call. The IAP code does not use or disable interrupts.

6.4.5.7 RAM used by ISP
The boot code uses the local SRAM block at address 0x10080000 as its working area. In
parts with on-chip flash the content of the whole 40 kB SRAM block may be lost upon
reset. In parts without on-chip flash the lower 32 kB of this SRAM block may be lost upon
reset.

6.4.5.8 RAM used by IAP command handler
Flash programming commands use 16 B of RAM from 0x10089FF0 to 0x10089FFF.
Applications making use of IAP calls must reserve this RAM block. The maximum stack
usage in the user allocated stack space is 256 B. The stack space is excluding usage of
IAP Set active partition command. The Set active partition command requires an
additional 2200 B in stack additionally for a maximum of 2456 B.

6.4.6 Flash signature generation
For parts with on-chip flash, a hardware flash signature generation capability is built into
the flash memory. This feature can be used to create a signature that can then be used to
verify flash contents. Details of flash signature generation are shown in Section 6.11.

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6.5 Sector numbers
Some IAP and ISP commands operate on sectors and specify sector numbers. The
following table indicates the correspondence between sector numbers and memory
addresses for LPC43xx device. IAP and ISP routines are located in the Boot ROM.
In addition, individual pages can be erased using the IAP erase page call (see Table 61).
The page size is 512 B. One page is the smallest amount of data that can be written into
the flash memory.
Table 30.

Flash configuration

Flash
bank

Sector
number

Sector size
[kB]

Start address

End address

LPC43x2

LPC43x3 LPC43x5

LPC43x7

A

0

8

0x1A00 0000

0x1A00 1FFF

yes

yes

yes

yes

A

1

8

0x1A00 2000

0x1A00 3FFF

yes

yes

yes

yes

A

2

8

0x1A00 4000

0x1A00 5FFF

yes

yes

yes

yes

A

3

8

0x1A00 6000

0x1A00 7FFF

yes

yes

yes

yes

A

4

8

0x1A00 8000

0x1A00 9FFF

yes

yes

yes

yes

A

5

8

0x1A00 A000

0x1A00 BFFF

yes

yes

yes

yes

A

6

8

0x1A00 C000

0x1A00 DFFF

yes

yes

yes

yes

A

7

8

0x1A00 E000

0x1A00 FFFF

yes

yes

yes

yes

A

8

64

0x1A01 0000

0x1A01 FFFF

yes

yes

yes

yes

A

9

64

0x1A02 0000

0x1A02 FFFF

yes

yes

yes

yes

A

10

64

0x1A03 0000

0x1A03 FFFF

yes

yes

yes

yes

A

11

64

0x1A04 0000

0x1A04 FFFF

yes

-

yes

yes

A

12

64

0x1A05 0000

0x1A05 FFFF

yes

-

yes

yes

A

13

64

0x1A06 0000

0x1A06 FFFF

yes

-

-

yes

A

14

64

0x1A07 0000

0x1A07 FFFF

yes

-

-

yes

B

0

8

0x1B00 0000

0x1B00 1FFF

-

yes

yes

yes

B

1

8

0x1B00 2000

0x1B00 3FFF

-

yes

yes

yes

B

2

8

0x1B00 4000

0x1B00 5FFF

-

yes

yes

yes

B

3

8

0x1B00 6000

0x1B00 7FFF

-

yes

yes

yes

B

4

8

0x1B00 8000

0x1B00 9FFF

-

yes

yes

yes

B

5

8

0x1B00 A000

0x1B00 BFFF

-

yes

yes

yes

B

6

8

0x1B00 C000

0x1B00 DFFF

-

yes

yes

yes

B

7

8

0x1B00 E000

0x1B00 FFFF

-

yes

yes

yes

B

8

64

0x1B01 0000

0x1B01 FFFF

-

yes

yes

yes

B

9

64

0x1B02 0000

0x1B02 FFFF

-

yes

yes

yes

B

10

64

0x1B03 0000

0x1B03 FFFF

-

yes

yes

yes

B

11

64

0x1B04 0000

0x1B04 FFFF

-

-

yes

yes

B

12

64

0x1B05 0000

0x1B05 FFFF

-

-

yes

yes

B

13

64

0x1B06 0000

0x1B06 FFFF

-

-

-

yes

B

14

64

0x1B07 0000

0x1B07 FFFF

-

-

-

yes

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Chapter 6: LPC43xx/LPC43Sxx flash programming/ISP and IAP

6.6 Code Read Protection (CRP)
Code Read Protection is a mechanism that allows user to enable different levels of
security in the system so that access to the on-chip flash and use of the ISP can be
restricted. When needed, CRP is invoked by programming a specific pattern in flash
location at offset 0x2FC. IAP commands are not affected by the code read protection.
Important: Any CRP change becomes effective only after the device has gone
through a power cycle.
Table 31.

Code Read Protection options

Name

Pattern
programmed at
offset 0x2FC[1]

Description

CRP1

0x1234 5678

Access to chip via the JTAG pins is disabled. This mode allows partial flash update using the
following ISP commands and restrictions:

CRP2

0x8765 4321

•
•
•
•

Read Memory command: disabled.

•

Compare command: disabled. This mode is useful when CRP is required and flash field
updates are needed but all sectors can not be erased. The compare command is
disabled, so in the case of partial flash updates the secondary loader should implement
a checksum mechanism to verify the integrity of the flash.

•

Activate flash bank not allowed.

0x4321 8765

Go command: disabled.
Erase sectors command: can erase any individual sector except sector 0 only, or can
erase all sectors at once.

This is similar to CRP1 with the following additions:

•
•
•
CRP3

Copy RAM to Flash command: cannot write to Sector 0.

Write to RAM command: disabled.
Copy RAM to Flash: disabled.
Erase command: only allows erase of all sectors.

This is similar to CRP2, but ISP entry by pulling P2_7 LOW is disabled if a valid user code is
present in flash sector 0.
This mode effectively disables ISP override using the P2_7 pin. It is up to the user’s
application to provide for flash updates by using IAP calls or by invoking ISP.
Caution: If CRP3 is selected, no future factory testing can be performed on the device.

NO_ISP
[1]

0x4E69 7370

Disables ISP request using the P2_7 pin.

Program the CRP pattern at address 0x1A00 02FC for flash bank A and at 0x1B00 02FC for flash bank B.

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Chapter 6: LPC43xx/LPC43Sxx flash programming/ISP and IAP

Table 32.

Code Read Protection hardware/software interaction

CRP option

User Code
Valid

P2_7 pin at
reset

JTAG enabled LPC43xx
enters ISP
mode

partial flash
update in ISP
mode

None

No

X

Yes

Yes

Yes

Yes

High

Yes

No

NA

Yes

Low

Yes

Yes

Yes

No

x

No

Yes

Yes

Yes

High

No

No

NA

Yes

Low

No

Yes

Yes

No

x

No

Yes

No

Yes

High

No

No

NA

Yes

Low

No

Yes

No

CRP3

No

x

No

Yes

No

Yes

x

No

No

NA

NO_ISP

No

x

Yes

Yes

Yes

Yes

x

Yes

No

Yes

CRP1

CRP2

If any CRP mode is enabled and access to the chip is allowed via the ISP, an unsupported
or restricted ISP command will be terminated with return code
CODE_READ_PROTECTION_ENABLED.

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6.7 ISP commands
The following commands are accepted by the ISP command handler. Detailed status
codes are supported for each command. The command handler sends the return code
INVALID_COMMAND when an undefined command is received. Commands and return
codes are in ASCII format.
CMD_SUCCESS is sent by ISP command handler only when received ISP command has
been completely executed and the new ISP command can be given by the host.
Exceptions from this rule are "Set Baud Rate", "Write to RAM", "Read Memory", and "Go"
commands.
Table 33.

ISP command summary

ISP Command

Usage

Flashless
parts

Parts with Reference
on-chip
flash

Unlock

U 

yes

yes

Table 34

Set Baud Rate

B  

yes

yes

Table 35

Echo

A 

yes

yes

Table 36

Write to RAM

W  

yes

yes

Table 37

Read Memory

R 
 

yes

yes

Table 38

no

yes

Table 39

Prepare sectors for write P   
Copy RAM to Flash

C   

no

yes

Table 40

Go

G 
 

yes

yes

Table 41

Erase sectors

E   

no

yes

Table 42

Blank check sectors

I   

no

yes

Table 43

Read Part ID

J

yes

yes

Table 44

Read Boot Code version K

yes

yes

Table 46

Read device unique ID

N

yes

yes

Table 47

Compare

M   

no

yes

Table 48

Set active boot flash
bank

S 

no

yes

Table 49

6.7.1 Unlock 
Table 34.

ISP Unlock command

Command

U

Input

Unlock code: 2313010

Return Code

CMD_SUCCESS |
INVALID_CODE |
PARAM_ERROR

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Description

This command is used to unlock Flash Write, Erase, and Go commands.

Example

"U 23130" unlocks the Flash Write/Erase & Go commands.

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6.7.2 Set Baud Rate  
The UART PCLK is derived from the IRC at 12 MHz.
Table 35.

ISP Set Baud Rate command

Command

B

Input

Baud Rate: 9600 | 19200 | 38400 | 57600 | 115200

Return Code

CMD_SUCCESS |

Stop bit: 1 | 2
INVALID_BAUD_RATE |
INVALID_STOP_BIT |
PARAM_ERROR
Description

This command is used to change the baud rate. The new baud rate is effective
after the command handler sends the CMD_SUCCESS return code.

Example

"B 57600 1" sets the serial port to baud rate 57600 bps and 1 stop bit.

6.7.3 Echo 
Table 36.

ISP Echo command

Command

A

Input

Setting: ON = 1 | OFF = 0

Return Code

CMD_SUCCESS |
PARAM_ERROR

Description

The default setting for echo command is ON. When ON the ISP command handler
sends the received serial data back to the host.

Example

"A 0" turns echo off.

6.7.4 Write to RAM  
The host should send the data only after receiving the CMD_SUCCESS return code. The
host should send the check-sum after transmitting 20 UU-encoded lines. The checksum is
generated by adding raw data (before UU-encoding) bytes and is reset after transmitting
20 UU-encoded lines. The length of any UU-encoded line should not exceed
61 characters (bytes) i.e. it can hold 45 data bytes. When the data fits in less than
20 UU-encoded lines then the check-sum should be of the actual number of bytes sent.
The ISP command handler compares it with the check-sum of the received bytes. If the
check-sum matches, the ISP command handler responds with "OK" to
continue further transmission. If the check-sum does not match, the ISP command
handler responds with "RESEND". In response the host should retransmit the
bytes.
The ISP write command can write to all internal SRAM blocks and to the external memory
bank 0 (CS0 at location 0x1C00 0000). Because the ISP code uses SRAM, the Write to RAM
command can not access SRAM between 0x1008 0000 and 0x1008 0200, see Section 6.4.5.7.

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Table 37.

ISP Write to RAM command

Command

W

Input

Start Address: RAM address where data bytes are to be written. This address
should be a word boundary.
Number of Bytes: Number of bytes to be written. Count should be a multiple of 4

Return Code

CMD_SUCCESS |
ADDR_ERROR (Address not on word boundary) |
ADDR_NOT_MAPPED |
COUNT_ERROR (Byte count is not multiple of 4) |
PARAM_ERROR |
CODE_READ_PROTECTION_ENABLED

Description

This command is used to download data to RAM. Data should be in UU-encoded
format. This command is blocked when code read protection levels CRP2 or
CRP3 are enabled.

Example

"W 268435968 4" writes 4 bytes of data to address 0x1000 0200.

6.7.5 Read Memory 
 
The data stream is followed by the command success return code. The check-sum is sent
after transmitting 20 UU-encoded lines. The checksum is generated by adding raw data
(before UU-encoding) bytes and is reset after transmitting 20 UU-encoded lines. The
length of any UU-encoded line should not exceed 61 characters (bytes) i.e. it can hold
45 data bytes. When the data fits in less than 20 UU-encoded lines then the check-sum is
of actual number of bytes sent. The host should compare it with the checksum of the
received bytes. If the check-sum matches then the host should respond with
"OK" to continue further transmission. If the check-sum does not match then
the host should respond with "RESEND". In response the ISP command
handler sends the data again.
The ISP read command can read from all internal SRAM blocks, from the external
memory bank 0 (CS0 at location 0x1C00 0000), and from the internal flash.
Table 38.

ISP Read Memory command

Command

R

Input

Start Address: Address from where data bytes are to be read. This address
should be a word boundary.

Return Code

CMD_SUCCESS followed by  |

Number of Bytes: Number of bytes to be read. Count should be a multiple of 4.
ADDR_ERROR (Address not on word boundary) |
ADDR_NOT_MAPPED |
COUNT_ERROR (Byte count is not a multiple of 4) |
PARAM_ERROR |
CODE_READ_PROTECTION_ENABLED

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Description

This command is used to read data from RAM or flash memory. This command is
blocked when any level of code read protection is enabled.

Example

"R 268435968 4" reads 4 bytes of data from address 0x1000 0200.

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6.7.6 Prepare sectors for write operation   
This command is the first step in the two-step flash write/erase operation.
Table 39.

ISP Prepare sectors for write operation command

Command

P

Input

Start Sector Number
End Sector Number: Should be greater than or equal to start sector number.
Flash bank: Selects flash bank if the part supports more than on bank. 0 = flash
bank A, 1 = flash bank B.

Return Code

CMD_SUCCESS |
BUSY |
INVALID_SECTOR |
PARAM_ERROR | INVALID_FLASH_UNIT

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Description

This command must be executed before executing "Copy RAM to Flash" or
"Erase Sectors" command. Successful execution of the "Copy RAM to Flash" or
"Erase Sectors" command causes relevant sectors to be protected again. To
prepare a single sector use the same "Start" and "End" sector numbers.

Example

"P 0 0 0 " prepares the flash sector 0 in flash bank A.

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6.7.7 Copy RAM to Flash   
Before executing this command, perform the “Prepare sectors for write operation”
command.
Table 40.

ISP Copy command

Command

C

Input

Flash Address(DST): Destination flash address where data bytes are to be
written. The destination address should be a 512 byte boundary.
RAM Address(SRC): Source RAM address from where data bytes are to be read.
Number of Bytes: Number of bytes to be written. Should be 512 | 1024 | 4096.

Return Code CMD_SUCCESS |
SRC_ADDR_ERROR (Address not on word boundary) |
DST_ADDR_ERROR (Address not on correct boundary) |
SRC_ADDR_NOT_MAPPED |
DST_ADDR_NOT_MAPPED |
COUNT_ERROR (Byte count is not 512 | 1024 | 4096) |
SECTOR_NOT_PREPARED_FOR WRITE_OPERATION |
BUSY |
CMD_LOCKED |
PARAM_ERROR |
CODE_READ_PROTECTION_ENABLED

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Description

This command is used to program the flash memory. The "Prepare Sectors for
Write Operation" command should precede this command. The affected sectors are
automatically protected again once the copy command is successfully executed.
This command is blocked when code read protection levels CRP2 or CRP3 are
enabled. When code read protection level CRP1 is enabled, individual sectors
other than sector 0 can be written.

Example

"C 436207616 268468224 512 " copies 512 bytes from the RAM
address 0x1000 8000 to the flash address 0x1A00 0000.

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6.7.8 Go 
 
Table 41.

ISP Go command

Command

G

Input

Address: Flash or RAM address from which the code execution is to be started.
This address must be on a word boundary and it is not allowed to add the Thumb
bit (bit 0) of the address.
Mode (retained for backward compatibility): T (Execute program in Thumb
Mode) | A (not allowed).

Return Code CMD_SUCCESS |
ADDR_ERROR |
ADDR_NOT_MAPPED |
CMD_LOCKED |
PARAM_ERROR |
CODE_READ_PROTECTION_ENABLED
Description

This command is used to execute a program residing in RAM or flash memory. It
may not be possible to return to the ISP command handler once this command is
successfully executed. This command is blocked when any level of code read
protection is enabled.

Example

"G 436208208 T" branches to address 0x1A00 0250.

When the GO command is used, execution begins at the specified address (assuming it is
an executable address) with the device left as it was configured for the ISP code. The
PLL1 is configured to generate a CPU clock with a frequency of 96 MHz.

6.7.9 Erase sectors   
Table 42.

ISP Erase sector command

Command

E

Input

Start Sector Number
End Sector Number: Should be greater than or equal to start sector number.
Flash bank: Selects flash bank if the part supports more than on bank. 0 = flash
bank A, 1 = flash bank B.

Return Code CMD_SUCCESS |
BUSY |
INVALID_SECTOR |
SECTOR_NOT_PREPARED_FOR_WRITE_OPERATION |
CMD_LOCKED |
PARAM_ERROR |
CODE_READ_PROTECTION_ENABLED | INVALID_FLASH_UNIT

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Description

This command is used to erase one or more sectors of on-chip flash memory. This
command is blocked when code read protection level CRP3 is enabled. When code
read protection level CRP1 is enabled, individual sectors other than sector 0 can be
erased. All sectors can be erased at once in CRP1 and CRP2.

Example

"E 2 3 0" erases the flash sectors 2 and 3 in flash bank A.

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6.7.10 Blank check sectors   
Table 43.

ISP Blank check sector command

Command

I

Input

Start Sector Number:
End Sector Number: Should be greater than or equal to start sector number.
Flash bank: Selects flash bank if the part supports more than on bank. 0 = flash
bank A, 1 = flash bank B.

Return Code CMD_SUCCESS |
SECTOR_NOT_BLANK (followed by 
) |
INVALID_SECTOR |
PARAM_ERROR | INVALID_FLASH_UNIT
Description

This command is used to blank check one or more sectors of on-chip flash memory.

Example

"I 2 3 0 " blank checks the flash sectors 2 and 3 in flash bank 0.

6.7.11 Read Part Identification number
Table 44.

ISP Read Part Identification command

Command

J

Input

None.

Return Code CMD_SUCCESS followed by part identification number in ASCII (see Table 45
“LPC43xx part identification numbers”).
The command returns two words: word0 followed by word1. Only the 8 LSBs on
word1 contain configuration information. The top 24 MSBs should be ignored or
masked as 0s. On parts with on-chip flash, word 0 corresponds to the part id and
word1 indicates the flash configuration. On flashless parts, word0 corresponds to
the part id and word1 contains 0x0.
Description

Table 45.

This command is used to read the part identification number. The part identification
number maps to a feature subset within a device family. This number will not
normally change as a result of technical revisions.
LPC43xx part identification numbers

Device

Hex coding
Word0

Word1

Flashless parts M4/M0, 10-bit ADC

UM10503

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LPC4350FET256

0xA000 0830

0xXXXX XX00

LPC4350FET180

0xA000 0830

0xXXXX XX00

LPC43S50FET256

0xA000 0860

0xXXXXXXX00

LPC43S50FET180

0xA000 0860

0xXXXXXXX00

LPC4330FET256

0xA000 0A30

0xXXXX XX00

LPC4330FET180

0xA000 0A30

0xXXXX XX00

LPC4330FET100

0xA000 0A30

0xXXXX XX00

LPC4330FBD144

0xA000 0A30

0xXXXX XX00

LPC43S30FET256

0xA000 0A60

0xXXXXXXX00

LPC43S30FET100

0xA000 0A60

0xXXXXXXX00

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Table 45.

LPC43xx part identification numbers

Device

Hex coding
Word0

Word1

LPC43S30FBD144

0xA000 0A60

0xXXXXXXX00

LPC4320FET100

0xA000 CB3C

0xXXXX XX00

LPC4320FBD144

0xA000 CB3C

0xXXXX XX00

LPC43S20FBD144

A000CB6C

0xXXXXXXX00

LPC43S20FET180

A000CB6C

0xXXXXXXX00

LPC4310FET100

0xA00A CB3F

0xXXXX XX00

LPC4310FBD144

0xA00A CB3F

0xXXXX XX00

Flashless parts M4/M0/M0, 12-bit ADCHS
LPC4370FET256

0x0000 0030

0xXXXX XX00

LPC4370FET100

0x0000 0230

0xXXXX XX00

LPC43S70FET100

00000060

00000000

LPC43S70FET256

00000060

00000000

LPC4367JET256

8001C030

00000000

LPC4367JBD208

8001C030

00000000

LPC4367JET100

8001C030

00000000

LPC43S67JET256

8001C060

00000000

LPC43S67JET100

8001C060

00000000

LPC43S67JBD208

8001C060

00000000

Parts with on-chip flash M4/M0, 10-bit ADC

UM10503

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LPC4357JET256

0xA001C830

0xXXXX XX00

LPC4357FET256

0xA001C830

0xXXXX XX00

LPC4357JBD208

0xA001C830

0xXXXX XX00

LPC43S57JET256

A001C860

0xXXXXXXX00

LPC43S57JBD208

A001CA60

0xXXXXXXX00

LPC4353FET256

0xA001C830

0xXXXX XX44

LPC4353JET256

0xA001C830

0xXXXX XX44

LPC4353JBD208

0xA001C830

0xXXXX XX44

LPC4337FET256

0xA001CA30

0xXXXX XX00

LPC4337JET256

0xA001CA30

0xXXXX XX00

LPC4337JBD144

0xA001CA30

0xXXXX XX00

LPC4337JET100

0xA001CA30

0xXXXX XX00

LPC43S37JBD144

A001CA60

0xXXXXXXX00

LPC43S37JET100

A001CA60

0xXXXXXXX00

LPC4333FET256

0xA001CA30

0xXXXX XX44

LPC4333JET256

0xA001CA30

0xXXXX XX44

LPC4333JBD144

0xA001CA30

0xXXXX XX44

LPC4333JET100

0xA001CA30

0xXXXX XX44

LPC4327JBD144

0xA001CB3C

0xXXXX XX00

LPC4327JET100

0xA001CB3C

0xXXXX XX00

LPC4325JBD144

0xA001CB3C

0xXXXX XX22

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Table 45.

LPC43xx part identification numbers

Device

Hex coding
Word0

Word1

LPC4325JET100

0xA001CB3C

0xXXXX XX22

LPC4323JBD144

0xA00BCB3C

0xXXXX XX44

LPC4323JET100

0xA00BCB3C

0xXXXX XX44

LPC4322JBD144

0xA00BCB3C

0xXXXX XX80

LPC4322JET100

0xA00BCB3C

0xXXXX XX80

LPC4317JBD144

0xA001CB3F

0xXXXX XX00

LPC4317JET100

0xA001CB3F

0xXXXX XX00

LPC4315JBD144

0xA001CB3F

0xXXXX XX22

LPC4315JET100

0xA001CB3F

0xXXXX XX22

LPC4313JBD144

0xA00BCB3F

0xXXXX XX44

LPC4313JET100

0xA00BCB3F

0xXXXX XX44

LPC4312JBD144

0xA00BCB3F

0xXXXX XX80

LPC4312JET100

0xA00BCB3F

0xXXXX XX80

6.7.12 Read Boot Code version number
Table 46.

ISP Read Boot Code version number command

Command

K

Input

None

Return Code CMD_SUCCESS followed by 2 bytes of boot code version number in ASCII format.
It is to be interpreted as ..
Description

This command is used to read the boot code version number.

6.7.13 Read device unique ID
Table 47.

ISP Read device unique ID command

Command

N

Input

None.

Return Code CMD_SUCCESS followed by the device unique ID in 4 decimal ASCII groups, each
representing a 32-bit value.
Description

This command is used to read the device unique ID. The unique ID may be used to
uniquely identify a single unit among all LPC43xx devices.

To mitigate attacks using Flash Patch and Breakpoint (FPB) by remapping the ROM API,
you can insert the following code snippet to read the unique ID directly.
Execute the following piece of code from internal SRAM.
volatile uint32_t mem[4] = {0};
*(volatile unsigned int *)0x4000C000 = *(volatile unsigned int *)0x4000C000 | (1 << 6);
while ((*(volatile unsigned int *)0x4000C000 >> 6) & 1 != 1){}
mem[0] = *((uint32_t *) 0x1A000200);
mem[1] = *(((uint32_t *) 0x1A000200) + 1);
mem[2] = *(((uint32_t *) 0x1A000200) + 2);
mem[3] = *(((uint32_t *) 0x1A000200) + 3);
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*(volatile unsigned int *)0x4000C000 = *(volatile unsigned int *)0x4000C000 & ~(1 << 6);
while ((*(volatile unsigned int *)0x4000C000 >> 6) & 1 == 1){}
*(volatile unsigned int *)0x4000C000 = *(volatile unsigned int *)0x4000C000 & ~(1 << 6);
while ((*(volatile unsigned int *)0x4000C000 >> 6) & 1 == 1){}
Remark: If the adversary can get hold of the code and has the skills to reverse engineer
it, the user code could be modified and the direct Read of the unique ID is not useful
anymore.

6.7.14 Compare   
Table 48.

ISP Compare command

Command

M

Input

Address1 (DST): Starting flash or RAM address of data bytes to be compared.
This address should be a word boundary.
Address2 (SRC): Starting flash or RAM address of data bytes to be compared.
This address should be a word boundary.
Number of Bytes: Number of bytes to be compared; should be a multiple of 4.

Return Code CMD_SUCCESS | (Source and destination data are equal)
COMPARE_ERROR | (Followed by the offset of first mismatch)
COUNT_ERROR (Byte count is not a multiple of 4) |
ADDR_ERROR |
ADDR_NOT_MAPPED |
PARAM_ERROR |
Description

This command is used to compare the memory contents at two locations. This
command is blocked when any level of code read protection is enabled.

Example

"M 436207616 268435968 4" compares 4 bytes from the RAM address
0x1000 0200 to the 4 bytes from the flash address 0x1A00 0000.

6.7.15 Set active boot flash bank 
This command is only valid if two flash banks exist on the part and selects one of the two
banks for booting from flash. The command inserts a valid signature (see Section 6.4.4.1)
in the selected flash bank and invalidates the signature in the other flash bank. After a
reset, the part will boot from the selected flash bank and apply any code read protection
(CRP) that is included in the flash image of the selected bank to the entire flash (bank A
and bank B).
The set active boot flash bank command is disabled with CRP levels 1, 2, and 3. This
means that the boot flash bank cannot be changed if CRP is enabled. If CRP is included
in the new flash image to be activated by this command, ensure that the flash image
content is executing as expected. Otherwise, the part may fail to boot after reset and, for
CRP level 3, external boot or ISP may not be accessible to update the flash.

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Table 49.

ISP Set active boot flash bank command

Command

S

Input

Flash bank: Selects flash bank A or B for booting if the part supports more than on
bank. (0 = flash bank A, 1 = flash bank B).

Return Code INVALID_FLASH_UNIT |
INVALID_SECTOR |
COMPARE_ERROR |
USER_CODE_CHECKSUM |
DST_ADDR_ERROR |

BUSY | ERROR_SETTING_ACTIVE_PARTITION
Description

This command is only valid if there are two flash banks. It is used to enable booting
from the indicated flash unit by inserting valid signature and invalidating the other
flash unit. This command will not work if zeros are found where a vector table is
expected.
Remark: An invalid image in the selected flash unit can cause boot failure and
even a system lockup when CRP3 is set.

Example

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“S 0 ” selects flash bank A

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6.8 IAP commands
Remark: IAP commands are not supported for flash-less parts.
For in-application programming, call the IAP routine with a word pointer in register r0
pointing to memory (RAM) containing command code and parameters.

Ptr to ROM Driver table
0x1040 0100

ROM Driver Table

flash IAP
IAP_entry

0x1040 0100
Ptr to flash IAP calls
0x1040 0104
Ptr to Device Table 1
0x1040 0108
Ptr to Device Table 2

Device 1
Ptr to Function 0

…
Ptr to Function 1
Ptr to Device Table n

Ptr to Function 2

…
Ptr to Function n

Fig 23. IAP pointer structure

The result of the IAP command is returned in the result table pointed to by register r1. You
can reuse the command table for result by passing the same pointer in registers r0 and r1.
The parameter table should be big enough to hold all the results in case the number of
results are more than number of parameters. Parameter passing is illustrated in
Figure 24. The number of parameters and results vary according to the IAP command.
The maximum number of parameters is 4, passed to the "Copy RAM to Flash" command.
The maximum number of results is 4, returned by the "Read device unique ID" command.
The command handler sends the status code INVALID_COMMAND when an undefined
command is received.

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Command Parameter Array
command_param[0]

Command code

command_param[1]

Param 0

command_param[2]

Param 1

command_param[n]

Param n

ARM REGISTER r0

ARM REGISTER r1

Status Result Array
status_result[0]

Status code

status_result[1]

Result 0

status_result[2]

Result 1

status_result[n]

Result n

Fig 24. IAP parameter passing

In C code, call the IAP function in the following way:
1. Extract the IAP invoke call (iap_entry) entry pointer. The IAP invoke call is located in
the IAP jump table which is pointed to by the ROM driver table at address 0x1040
0100 + 0x000. See Figure 23.
2. Define data structure or pointers to pass the IAP command table and result table to
the IAP function:
unsigned int command_param[5];
unsigned int status_result[5];
or
unsigned int * command_param;
unsigned int * status_result;
command_param = (unsigned int *) 0x...
status_result =(unsigned int *) 0x...
3. Define a pointer to function type, which takes two parameters and returns void. Note
the IAP returns the result with the base address of the table residing in R1:
#define IAP_LOCATION *(volatile unsigned int *)(0x10400100);
typedef void (*IAP)(unsigned int [],unsigned int[]);

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4. Set the function pointer:
IAP iap_entry=(IAP)IAP_LOCATION;
5. Use the following statement to call the IAP:
iap_entry (command_param,status_result);
The IAP call can be simplified further by using the symbol definition file feature supported
by ARM Linker in RVDS (Realview Development Suite). You can also call the IAP routine
using assembly code. According to the ARM architecture Procedure Calling Standard
(AAPCS), up to 4 parameters can be passed in the r0, r1, r2 and r3 registers respectively.
Additional parameters are passed on the stack. Up to 4 parameters can be returned in the
r0, r1, r2 and r3 registers respectively. Additional parameters are returned indirectly via
memory. Some of the IAP calls require more than 4 parameters. If the ARM suggested
scheme is used for the parameter passing/returning then it might create problems due to
difference in the C compiler implementation from different vendors. The suggested
parameter passing scheme reduces this risk.
The flash memory is not accessible during a write or an erase operation. IAP commands
which result in a flash write/erase operation use 32 bytes of space in the top portion of the
on-chip RAM for execution. The user program should not be using this space if IAP flash
programming is permitted in the application. Maximum stack usage is mentioned in the
description of a command.

Table 50.

IAP Command Summary

IAP Command

Command Code

Reference

Init

4910

Table 51

Prepare sectors for write operation

5010

Table 52

Copy RAM to Flash

5110

Table 53

Erase sectors

5210

Table 54

Blank check sectors

5310

Table 55

Read part ID

5410

Table 56

Read Boot Code version

5510

Table 57

Read device unique ID

5810

Table 58

Compare

5610

Table 59

Reinvoke ISP

5710

Table 60

Erase page

5910

Table 61

Set active boot flash bank

6010

Table 62

6.8.1 IAP Initialization
This command initializes and prepares the flash for erase and write operations.
Table 51.

IAP Initialization command

Command

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Init IAP

Input

Command code: 49 (decimal)

Status Code

CMD_SUCCESS

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Table 51.

IAP Initialization command

Command

Init IAP

Result

None

Description

Initializes and prepares the flash for erase and write operations.

Stack usage

88 B

6.8.2 Prepare sectors for write operation
This command is the first step in the two-step flash write/erase operation.
Table 52.

IAP Prepare sectors for write operation command

Command

Prepare sectors for write operation

Input

Command code: 50 (decimal)
Param0: Start Sector Number
Param1: End Sector Number (should be greater than or equal to start sector
number).
Param2: Flash bank (0 = flash bank A, 1 = flash bank B)

Return Code

CMD_SUCCESS |
BUSY |
INVALID_SECTOR

Result

None

Description

This command must be executed before executing "Copy RAM to Flash" or
"Erase Sectors" command. Successful execution of the "Copy RAM to Flash" or
"Erase Sectors" command causes relevant sectors to be protected again. To
prepare a single sector use the same "Start" and "End" sector numbers.

Stack usage

118 B

6.8.3 Copy RAM to Flash
Before executing this command, perform the “Prepare sectors for write” command.

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Table 53.

IAP Copy RAM to Flash command

Command

Copy RAM to Flash

Input

Command code: 51 (decimal)
Param0(DST): Destination flash address where data bytes are to be written. This
address should be a 512 byte boundary.
Param1(SRC): Source internal SRAM address from which data bytes are to be
read. This address should be a word boundary.
Param2: Number of bytes to be written. Should be 512 | 1024 | 4096.
Param3: CPU Clock Frequency (CCLK) in kHz.

Status Code

CMD_SUCCESS |
SRC_ADDR_ERROR (Address not a word boundary) |
DST_ADDR_ERROR (Address not on correct boundary) |
SRC_ADDR_NOT_MAPPED |
DST_ADDR_NOT_MAPPED |
COUNT_ERROR (Byte count is not 512 | 1024 | 4096) |
SECTOR_NOT_PREPARED_FOR_WRITE_OPERATION |
BUSY

Result

None

Description

This command is used to program the flash memory. The affected sectors should
be prepared first by calling "Prepare Sector for Write Operation" command. The
affected sectors are automatically protected again once the copy command is
successfully executed.

Stack usage

208 B

6.8.4 Erase Sectors
Table 54.

IAP Erase Sectors command

Command

Erase Sectors

Input

Command code: 52 (decimal)
Param0: Start Sector Number
Param1: End Sector Number (should be greater than or equal to start sector
number).
Param2: CPU Clock Frequency (CCLK) in kHz.
Param3: Flash bank (0 = flash bank A, 1 = flash bank B)

Status Code

CMD_SUCCESS |
BUSY |
SECTOR_NOT_PREPARED_FOR_WRITE_OPERATION |
INVALID_SECTOR | INVALID_FLASH_UNIT

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Result

None

Description

This command is used to erase a sector or multiple sectors of on-chip flash
memory. To erase a single sector use the same "Start" and "End" sector numbers.

Stack usage

136 B

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6.8.5 Blank check sectors
Table 55.

IAP Blank check sectors command

Command

Blank check sectors

Input

Command code: 53 (decimal)
Param0: Start Sector Number
Param1: End Sector Number (should be greater than or equal to start sector
number).
Param2: Flash bank (0 = flash bank A, 1 = flash bank B)

Status Code

CMD_SUCCESS |
BUSY |
SECTOR_NOT_BLANK |
INVALID_SECTOR | INVALID_FLASH_UNIT

Result

Result0: Offset of the first non blank word location if the Status Code is
SECTOR_NOT_BLANK.
Result1: Contents of non blank word location.

Description

This command is used to blank check a sector or multiple sectors of on-chip flash
memory. To blank check a single sector use the same "Start" and "End" sector
numbers.

Stack usage

120 B

6.8.6 Read part identification number
Table 56.

IAP Read part identification number command

Command

Read part identification number

Input

Command code: 54 (decimal)
Parameters: None

Status Code

CMD_SUCCESS |

Result

Result0: Part Identification Number.
Result1: Part Identification Number.

Description

This command is used to read the part identification number. See Table 45
“LPC43xx part identification numbers”.
The command returns two words: word0 followed by word1. Word 0 corresponds
to the part id and word1 indicates the flash configuration or contains 0x0 for
flashless parts.

Stack usage

8B

6.8.7 Read Boot Code version number
Table 57.

IAP Read Boot Code version number command

Command

Read boot code version number

Input

Command code: 55 (decimal)
Parameters: None

Status Code

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Table 57.

IAP Read Boot Code version number command

Command

Read boot code version number

Result

Result0: 2 bytes of boot code version number. It is to be interpreted as
.

Description

This command is used to read the boot code version number.

Stack usage

8B

6.8.8 Read device unique ID
Table 58.

IAP Read device unique ID command

Command

Read device unique ID

Input

Command code: 58 (decimal)
Parameters: None

Status Code

CMD_SUCCESS |

Result

Result0: First 32-bit word of Device Identification Number (at the lowest address)
Result1: Second 32-bit word of Device Identification Number
Result2: Third 32-bit word of Device Identification Number
Result3: Fourth 32-bit word of Device Identification Number

Description

This command is used to read the device identification number. The device
unique ID may be used to uniquely identify a single unit among all LPC43xx
devices.

Stack usage

8B

To mitigate attacks using Flash Patch and Breakpoint (FPB) by remapping the ROM API,
see Section 6.7.13 “Read device unique ID”. to read the unique ID directly.

6.8.9 Compare   
Table 59.

IAP Compare command

Command

Compare

Input

Command code: 56 (decimal)
Param0(DST): Starting flash or RAM address of data bytes to be compared. This
address should be a word boundary.
Param1(SRC): Starting flash or RAM address of data bytes to be compared. This
address should be a word boundary.
Param2: Number of bytes to be compared; should be a multiple of 4.

Status Code

CMD_SUCCESS |
COMPARE_ERROR |
COUNT_ERROR (Byte count is not a multiple of 4) |
ADDR_ERROR |
ADDR_NOT_MAPPED

Result

Result0: Offset of the first mismatch if the Status Code is COMPARE_ERROR.

Description

This command is used to compare the memory contents at two locations.
The result may not be correct when the source or destination includes any
of the first 64 bytes starting from address zero. The first 64 bytes can be
re-mapped to RAM.

Stack usage

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6.8.10 Re-invoke ISP
Table 60.

IAP Re-invoke ISP

Command

Compare

Input

Command code: 57 (decimal)

Status Code

None

Result

None.

Description

This command is used to invoke the boot loader in ISP mode. It configures
UART0 pins U0_RX and U0_TX. Use this command when a valid user program is
present in the internal flash memory and the P2_7 pin is not accessible to force
the ISP mode. The command does not change CCLK, It does sets the source
dependent clock accordingly assuming that PLL1 is running at 288 MHz.

Stack usage

192 B

6.8.11 Erase page
The erase page command allows to erase one page (512 B) in a given sector.
Table 61.

IAP Erase page

Command

Erase page

Input

Command code: 59 (decimal)
Param0: Start flash address.
Param1: End flash address.
Param2: CPU clock frequency in kHz.

Status Code

CMD_SUCCESS | BUSY |
SECTOR_NOT_PREPARED_FOR_WRITE_OPERATION | INVALID_SECTOR |
INVALID_FLASH_UNIT

Result

None.

Description

This command is used to erase a page or multiple pages of on-chip flash memory.
To erase a single page use the same "Start" and "End" flash address. Start and
End addresses must be in the same sector.

Stack usage

168 B

6.8.12 Set active boot flash bank
This command is only valid if two flash banks exist on the part and selects one of the two
banks for booting from flash. The command inserts a valid signature (see Section 6.4.4.1)
in the selected flash bank and invalidates the signature in the other flash bank. After a
reset, the part will boot from the selected flash bank and apply any code read protection
(CRP) that is included in the flash image of the selected bank to the entire flash (bank A
and bank B).
The set active boot flash bank command is disabled with CRP levels 1, 2, and 3. This
means that the boot flash bank cannot be changed if CRP is enabled. If CRP is included
in the new flash image to be activated by this command, ensure that the flash image
content is executing as expected. Otherwise, the part may fail to boot after reset and, for
CRP level 3, external boot or ISP may not be accessible to update the flash.
Remark: This command uses a large stack space. See Table 62.

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Table 62.

IAP Set active boot flash bank

Command

Set active boot flash bank

Input

Command code: 60 (decimal)
Param0: Flash bank (0 = flash bank A, 1 = flash bank B).
Param1: CPU clock frequency in kHz.

Status Code

CMD_SUCCESS | BUSY |
SECTOR_NOT_PREPARED_FOR_WRITE_OPERATION | INVALID_SECTOR |
INVALID_FLASH_UNIT | ERROR_USER_CODE_CHECKSUM |
ERROR_SETTING_ACTIVE_PARTITION

Result

None.

Description

This command is only valid if there are two flash banks. It is used to enable
booting from the indicated flash unit by inserting a valid signature and invalidating
the other flash unit. This command will not work if zeros are found where a vector
table is expected.
Remark: An invalid image in the selected flash unit can cause boot failure and
even a system lockup when CRP3 is set.

Stack usage

2208 B

6.9 ISP/IAP Status Codes
Table 63.

ISP Status Codes Summary

Status Code

Mnemonic

Description

0x0000 0000

CMD_SUCCESS

Command is executed successfully. Sent by ISP handler only
when command given by the host has been completely and
successfully executed.

0x0000 0001

INVALID_COMMAND

Invalid command.

0x0000 0002

SRC_ADDR_ERROR

Source address is not on word boundary.

0x0000 0003

DST_ADDR_ERROR

Destination address not on word or 256 byte boundary.

0x0000 0004

SRC_ADDR_NOT_MAPPED

Source address is not mapped in the memory map. Count
value is taken into consideration where applicable.

0x0000 0005

DST_ADDR_NOT_MAPPED

Destination address is not mapped in the memory map. Count
value is taken into consideration where applicable.

0x0000 0006

COUNT_ERROR

Byte count is not multiple of 4 or is not a permitted value.

0x0000 0007

INVALID_SECTOR

Sector number is invalid or end sector number is greater than
start sector number.

0x0000 0008

SECTOR_NOT_BLANK

Sector is not blank.

0x0000 0009

SECTOR_NOT_PREPARED_
FOR_WRITE_OPERATION

Command to prepare sector for write operation was not
executed.

0x0000 000A

COMPARE_ERROR

Source and destination data not equal.

0x0000 000B

BUSY

Flash programming hardware interface is busy.

0x0000 000C

PARAM_ERROR

Insufficient number of parameters or invalid parameter.

0x0000 000D

ADDR_ERROR

Address is not on word boundary.

0x0000 000E

ADDR_NOT_MAPPED

Address is not mapped in the memory map. Count value is
taken in to consideration where applicable.

0x0000 000F

CMD_LOCKED

Command is locked.

0x0000 0010

INVALID_CODE

Unlock code is invalid.

0x0000 0011

INVALID_BAUD_RATE

Invalid baud rate setting.

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Table 63.

ISP Status Codes Summary

Status Code

Mnemonic

Description

0x0000 0012

INVALID_STOP_BIT

Invalid stop bit setting.

0x0000 0013

CODE_READ_PROTECTION_
ENABLED

Code read protection enabled.

0x0000 0014

INVALID_FLASH_UNIT

Invalid flash unit.

0x0000 0015

USER_CODE_CHECKSUM

0x0000 0016

ERROR_SETTING_ACTIVE_PARTITION

6.10 JTAG flash programming interface
Debug tools can write parts of the flash image to the RAM and then execute the IAP call
"Copy RAM to Flash" repeatedly with proper offset.

6.11 Flash signature generation
The flash module contains a built-in signature generator. This generator can produce a
128-bit signature from a range of flash memory. A typical usage is to verify the flashed
contents against a calculated signature (e.g. during programming).
The address range for generating a signature must be aligned on flash-word boundaries,
i.e. 128-bit boundaries. Once started, signature generation completes independently.
While signature generation is in progress, the flash memory cannot be accessed for other
purposes, and an attempted read will cause a wait state to be asserted until signature
generation is complete. Code outside of the flash (e.g. internal RAM) can be executed
during signature generation. This can include interrupt services, if the interrupt vector
table is re-mapped to memory other than the flash memory. The code that initiates
signature generation should also be placed outside of the flash memory.

6.11.1 Register description for signature generation
Table 64.

Register overview: FMC controller for flash bank A/B (base address 0x4000 C000 (flash bank A) and
0x4000 D000 (flash bank B))

Name

Access

Address offset

Description

Reset
Value

Reference

FMSSTART

R/W

0x020

Signature start address register

0

Table 65

FMSSTOP

R/W

0x024

Signature stop-address register

0

Table 66

FMSW0

R

0x02C

128-bit signature Word 0

-

Table 67

FMSW1

R

0x030

128-bit signature Word 1

-

Table 68

FMSW2

R

0x034

128-bit signature Word 2

-

Table 69

FMSW3

R

0x038

128-bit signature Word 3

-

Table 70

FMSTAT

R

0xFE0

Signature generation status register

0

Table 71

FMSTATCLR

W

0xFE8

Signature generation status clear register

-

Table 72

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6.11.1.1 Signature generation address and control registers
These registers control automatic signature generation. A signature can be generated for
any part of the flash memory contents. The address range to be used for generation is
defined by writing the start address to the signature start address register (FMSSTART)
and the stop address to the signature stop address register (FMSSTOP. The start and
stop addresses must be aligned to 128-bit boundaries and can be derived by dividing the
byte address by 16.
Signature generation is started by setting the SIG_START bit in the FMSSTOP register.
Setting the SIG_START bit is typically combined with the signature stop address in a
single write.
Table 65 and Table 66 show the bit assignments in the FMSSTART and FMSSTOP
registers respectively.
Table 65.

Flash Module Signature Start register (FMSSTART, address 0x4000 C020 (flash A) and 0x4000 D020 (flash
B)) bit description

Bit

Symbol

Description

31:17

-

Reserved, user software should not write ones to reserved bits. The value read from a NA
reserved bit is not defined.

16:0

START

Signature generation start address (corresponds to AHB byte address bits[20:4]).

Table 66.

0

Flash Module Signature Stop register (FMSSTOP , address 0x4000 C024 (flash A) and 0x4000 D024 (flash
B)) bit description

Bit

Symbol

31:18

-

17

SIG_START

16:0

Reset Value

STOP

Value

Description

Reset Value

Reserved, user software should not write ones to reserved bits. The value
read from a reserved bit is not defined.

NA

Start control bit for signature generation.

0

0

Signature generation is stopped

1

Initiate signature generation
BIST stop address divided by 16 (corresponds to AHB byte address [20:4]).

0

6.11.1.2 Signature generation result registers
The signature generation result registers return the flash signature produced by the
embedded signature generator. The 128-bit signature is reflected by the four registers
FMSW0, FMSW1, FMSW2 and FMSW3.
The generated flash signature can be used to verify the flash memory contents. The
generated signature can be compared with an expected signature and thus makes saves
time and code space. The method for generating the signature is described in
Section 6.11.2.
Table 70 show bit assignment of the FMSW0 and FMSW1, FMSW2, FMSW3 registers
respectively.
Table 67.

FMSW0 register bit description (FMSW0, address 0x4000 C02C (flash A) and 0x4000 D02C (flash B))

Bit

Symbol

Description

Reset Value

31:0

SW0[31:0]

Word 0 of 128-bit signature (bits 31 to 0).

-

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Table 68.

FMSW1 register bit description (FMSW1, address: 0x4000 C030 (flash A) and 0x4000 D030 (flash B))

Bit

Symbol

Description

Reset Value

31:0

SW1[63:32]

Word 1 of 128-bit signature (bits 63 to 32).

-

Table 69.

FMSW2 register bit description (FMSW2, address 0x4000 C034 (flash A) and 0x4000 D034 (flash B))

Bit

Symbol

Description

Reset Value

31:0

SW2[95:64]

Word 2 of 128-bit signature (bits 95 to 64).

-

Table 70.

FMSW3 register bit description (FMSW3, address 0x4000 C038 (flash A) and 0x4000 D038 (flash B))

Bit

Symbol

Description

Reset Value

31:0

SW3[127:96]

Word 3 of 128-bit signature (bits 127 to 96).

-

6.11.1.3 Flash Module Status register
The read-only FMSTAT register provides a means of determining when signature
generation has completed. Completion of signature generation can be checked by polling
the SIG_DONE bit in FMSTAT. SIG_DONE should be cleared via the FMSTATCLR
register before starting a signature generation operation, otherwise the status might
indicate completion of a previous operation.
Table 71.

Flash module Status register (FMSTAT, address 0x4000 CFE0 (flash A) and 0x4000 DFE0 (flash B)) bit
description

Bit

Symbol

Description

31:2

-

Reserved, user software should not write ones to reserved bits. The value read NA
from a reserved bit is not defined.

Reset Value

2

SIG_DONE

When 1, a previously started signature generation has completed. See
FMSTATCLR register description for clearing this flag.

1:0

-

Reserved, user software should not write ones to reserved bits. The value read NA
from a reserved bit is not defined.

0

6.11.1.4 Flash Module Status Clear register
The FMSTATCLR register is used to clear the signature generation completion flag.
Table 72.

Flash Module Status Clear register (FMSTATCLR, address 0x4000 CFE8 (flash A) and 0x4000 DFE8 (flash
B)) bit description

Bit

Symbol

Description

31:2

-

Reserved, user software should not write ones to reserved bits. The value read NA
from a reserved bit is not defined.

2

SIG_DONE_CLR

Writing a 1 to this bits clears the signature generation completion flag
(SIG_DONE) in the FMSTAT register.

1:0

-

Reserved, user software should not write ones to reserved bits. The value read NA
from a reserved bit is not defined.

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6.11.2 Algorithm and procedure for signature generation
Signature generation
A signature can be generated for any part of the flash contents. The address range to be
used for signature generation is defined by writing the start address to the FMSSTART
register, and the stop address to the FMSSTOP register.
The signature generation is started by writing a ‘1’ to FMSSTOP.MISR_START. Starting
the signature generation is typically combined with defining the stop address, which is
done in another field FMSSTOP.FMSSTOP of the same register.
The time that the signature generation takes is proportional to the address range for which
the signature is generated. Reading of the flash memory for signature generation uses a
self-timed read mechanism and does not depend on any configurable timing settings for
the flash. A safe estimation for the duration of the signature generation is:
Duration = int((60 / tcy) + 3 ) x (FMSSTOP - FMSSTART + 1)
When signature generation is triggered via software, the duration is in AHB clock cycles,
and tcy is the time in ns for one AHB clock. The SIG_DONE bit in FMSTAT can be polled
by software to determine when signature generation is complete.
If signature generation is triggered via JTAG, the duration is in JTAG tck cycles, and tcy is
the time in ns for one JTAG clock. Polling the SIG_DONE bit in FMSTAT is not possible in
this case.
After signature generation, a 128-bit signature can be read from the FMSW0 to FMSW3
registers. The 128-bit signature reflects the corrected data read from the flash. The 128-bit
signature reflects flash parity bits and check bit values.
Content verification
The signature as it is read from the FMSW0 to FMSW3 registers must be equal to the
reference signature. The algorithms to derive the reference signature is given in
Figure 25.
sign = 0
FOR address = FMSTART.FMSTART TO FMSTOP.FMSTOP
{
FOR i = 0 TO 126
nextSign[i] = f_Q[address][i] XOR sign[i+1]
nextSign[127] = f_Q[address][127] XOR sign[0] XOR sign[2] XOR
sign[27] XOR sign[29]
sign = nextSign
}
signature128 = sign
Fig 25. Algorithm for generating a 128 bit signature

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7.1 How to read this chapter
This chapter applies to LPC43Sxx parts (secure parts) only.
Flash-based, secure parts boot from on-chip flash by default (see Chapter 6), but other
(secure) boot modes are also supported. The UART boot mode is only supported for
flashless parts. The secure boot from USART3 is not supported for LPC43Sxx parts.

7.1.1 Determine the boot code version
For parts with on-chip flash, the boot code version can be determined using ISP or IAP
calls. See Table 46 “ISP Read Boot Code version number command” and Table 57 “IAP
Read Boot Code version number command”.
For flashless parts, use ISP to read the boot code version number (see Table 46) or read
memory location 0x1040 7FFC which encodes the boot code version as follows:
Value 0x000B 000n at location 0x1040 7FFC reads as boot code version 11.n.

7.2 Features
• Secure booting from an encrypted image.
• Cypher-based Message Authentication Code (CMAC) authentication on the boot
image.

• Supports development mode for booting from a plain text image. Development mode
is terminated by programming the AES key.

7.3 Functional description
7.3.1 Boot sources
The boot source is defined by the OTP or, if the OTP is blank, by the state of the boot pins
in the same way as for non-secure parts. Secure parts with and without internal flash
support the same boot sources as non-secure parts. See Section 5.3.

7.3.2 Encryption and boot flow
All flashless secure parts can boot from a secure (encrypted) image with CMAC
authentication. For parts with on-chip flash, the ISP mode must be enabled to select an
external boot source with the encrypted image.
Remark: Any on-chip flash image containing valid user code can be protected by
selecting from several CRP levels. See Section 6.6 “Code Read Protection (CRP)”.
Secure booting generally involves the following steps:
1. On an external device, create a secure image from the plain-text image:
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a. Use a 128-bit key to encrypt the image using Cypher Block Chaining (CBC)
encryption and an initialization vector of 0101010... (binary). After the first block of
data, each following (plain-text) block is XORed with the previous encrypted block
of data. For details, see Section 7.3.4 “CMAC”.
b. Create a header using Table 73 “Boot image header description” with a dummy
hash size. The actual hash size is calculated after encryption of the image and this
header.
c. Encrypt the header using CBC and an initialization vector of 0.
d. Use CMAC to create a hash code and calculate the hash size of the combined
encrypted header and image. See Section 7.3.4 “CMAC”.
e. Update the header with the calculated hash size.
f. Encrypt header as before using CBC and an initialization vector of 0.
2. On the LPC43Sxx, program the encryption key into the OTP memory bank 1 using the
API function aes_ProgramKey1 (see Table 75).
Remark: The encryption key itself is scrambled in OTP memory bank 1 for added
security.
3. Select boot mode. See Section 5.3.
4. On parts with on-chip flash, JTAG access is not disabled. Therefore, set the
appropriate CRP level in the flash memory to disable JTAG access.
On flashless parts, JTAG access is disabled automatically once the key is
programmed in OTP memory bank 1.
5. Reset the LPC43xx, and the part boots securely from the specified boot source. See
Figure 27 “Boot flow for encrypted images (flashless parts)”.
Remark: To test the secure boot flow, you can create a secure image with a key of all
zeros using the steps above and omitting programming the key into the OTP memory. The
part then boots after reset using the zero-encrypted image.

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512B

ENCRYPTION
512B
1

2

512B

512B

P
A
D

partition data in
512 Byte frames
encrypt data with
CBC AES
AES key = User Key
IV = AES-1(User Key,1)

3

define temporary
header: use fixed
Hash value

4

encrypt header with AES
AES key = User Key
IV = 0

5

calculate CMAC
AES key = User Key
IV = 0

6

make final header;
insert calculated
HASH_VALUE

<512B

HASH
VALUE

0x3456
789A

16 + 512* HASH_SIZE

MAC

encrypt header with AES
AES key = User Key
IV = 0
7

precede data
with final header

Fig 26. Image encryption

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CPU clock
= IRC
12MHz

RESET

AES
key1
programmed?

disable
IRQ &
MPU

no

yes
load AES
key

enable
JTAG

CPU clock
=
96MHz

no

boot source =
UART, USB, SSP
check BOOT _SRC

valid
header ?

AES key1
programmed?

boot source
= EMC, SPIFI

yes
enter ISP
mode (USART0)

no

header
present?

no
no

no

valid
header ?
yes

yes

AES
key1
programmed?

yes
valid
encrypted
header
and image
hash
authentic

ISP pin
P2_7
LOW ?

no
AES key1
programmed?

no

no

yes
no

yes
decrypt image to SRAM
at 0x1000 0000
set program counter
= 0x1000 0000,
run

copy image to
SRAM at
0x1000 0000

no

valid
encrypted
header
and image
hash
authentic

set program counter
= 0x1000 0000,
run

yes

60s timeout
toggle pin
P1_1

decrypt image to SRAM
at 0x1000 0000

Reset

set program counter
= 0x1000 0000,
run

For parts with on-chip flash, the boot source is checked when the ISP pin is pulled LOW. All other flows are identical to flashless
parts. See Figure 15.

Fig 27. Boot flow for encrypted images (flashless parts)

7.3.2.1 Development mode
A special development mode allows booting from a plain text image. This development
mode is active until the AES key1 has been programmed.
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Once the AES key1 is programmed in the OTP, the development mode is terminated and
JTAG access is automatically disabled for flashless parts.

7.3.3 Boot image header format
AES capable products with a programmed AES key1 will always boot from a secure
image and use CMAC authentication. A secure image should always include a header.
The image must be preceded by a header that has the layout described in Table 73. For
encrypted images the header must be encrypted with the AES user key1 and initialization
vector iv = 0. The user key is stored in the OTP (see Table 13).
Remark: All values except 0x1A in the AES_ACTIVE field in the encrypted header are
considered valid. If the AES_ACTIVE field in the encrypted header has the value 0x1A
(AES encryption not active), then the header should be changed such that the
AES_ACTIVE field is not equal to 0x1A. A change in one of the AES_CONTROL bits will
produce an alternative value. The correct mechanism when creating an encrypted header
is to try every possible value in AES_CONTROL until the encrypted version does not
contain the value 0x1A in the AES_ACTIVE field.
Table 73.

Boot image header description

Address

Name

Description

size [bits]

5:0

AES_ACTIVE[1]

AES encryption active

6

0x25 (100101): AES encryption active
0x1A (011010): AES encryption not active
all other values: invalid image
7:6

HASH_ACTIVE[1]

2

Indicates whether a hash is used:
00: CMAC hash is used, value is HASH_VALUE
01: reserved
10: reserved
11: no hash is used

15:8

AES_CONTROL

When AES encryption is active, these bits can be set to a
8
value such that the AES_ACTIVE field after AES encryption is
not equal to the value 0x1A (AES encryption not active).

31:16

HASH_SIZE[3]

Size of the part of the image over which the hash value is
calculated in number of 512 Byte frames. Also size of the
image copied to internal SRAM.

16

Hash size = 16[2] + HASH_SIZE x 512 Byte.
95:32

HASH_VALUE

CMAC hash value calculated over the first bytes of the image
(starting right from the header) as indicated by HASH_SIZE.
The value is truncated to the 64 MSB.

64

127:96

RESERVED

11...11 (binary)

32

[1]

Can only be active if device is AES capable, else is considered an invalid image.

[2]

16 extra bytes are required for the header bytes.

[3]

The image size should be set to no more than the size of the SRAM located at 0x1000 0000.

7.3.4 CMAC
The CMAC algorithm is used to calculate a tag which is used for image authentication.
The tag is stored in the header field HASH_VALUE.
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The authentication process works as follows:
1. Use the CMAC algorithm to generate the 128-bit tag. Truncate the tag to 64 MSB and
insert this truncated tag in the header.
2. At boot time the tag is recalculated. Authentication passes when the calculated tag is
equal to the received tag in the image header.
To generate an l-bit CMAC tag T of message M using a 128-bit block cipher AES and
secret key K, the CMAC tag generation process works as follows:
1. Generate sub key K1:
– Calculate a temporary value K0 = AESK(0).
– If msb(K0) = 0 then K1 = (K0 << 1) else K1 = (K0 << 1)  0x87
2. Divide message into 128-bit blocks M = M1 || ... || Mn-1 || Mn*, where M1 ...Mn-1 are
complete blocks.
3. The last block, Mn*, should be padded to be a complete block and then Mn = K1 
Mn*.
4. Let c0 = 00...0.
5. For i = 1, ..., n, calculate ci = AESK(ci-1  Mi).
6. Output T = msbl(cn).
The first message block is the header. Since the CMAC tag is stored in the header field
HASH_VALUE, and this tag is not yet known until after CMAC calculation, a temporary
header with a dummy tag value of 0x3456789A is used during CMAC calculation. This
dummy value should be replaced by the calculated tag value in the final header field
HASH_VALUE.
For LPC43xx the chosen CMAC parameters are: encryption key K = User Key (AES key1,
same as used for decryption) and tag length l = 64. Data is processed in little endian
mode. This means that the first byte read from the image is integrated into the AES
codeword as least significant byte. The 16th byte read from the image is the most
significant byte of the first AES codeword.
CMAC is calculated over the header and encrypted image.

M1

AESK

M2

M*n

+

+

AESK

AESK

K1

MSB64

Tag

Fig 28. CMAC generation

7.3.5 Boot process timing
The following parameters describe the timing of the boot process:
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Table 74.
Parameter

Typical boot process timing parameters
Description

Value

t_a

Check boot selection pins

< 1.25 s

t_b

Initialize device

250 s[1]; 180 s[2]; 200 s[3]

t_c

Copy image to embedded SRAM

< 0.3 s

If part is executing from external
flash with no copy
If the image is encrypted or must
be copied
[1]

< 1 s to 10000 s
depending on the size of the image and the
speed of the boot memory

For flashless parts LPC43S50/S30/S20.

[2]

For parts with on-chip flash; booting from flash.

[3]

For parts with on-chip flash; booting from an external source.

IRC12
stable

IRC12
starts

IRC12

RESET
VDDREG

valid
threshold

GND
22 μs
supply
ramp up

0.5μs; IRC stability count
boot time
user code
ta μs

processor status

check boot
selection
pins

tb μs
initialise
device

tc μs
copy image to
embedded
SRAM

Fig 29. Boot process timing

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8.1 How to read this chapter
AES encryption and decryption and the AES API are supported for parts LPC43Sxx only.

8.2 Features
•
•
•
•

Decryption of external image data.
Encryption of data.
Secure storage of AES keys.
Support for Cypher-based Message Authentication Code (CMAC) hash calculation to
authenticate data.for the boot image only

• Support for two secret hardware keys that cannot be read.
• AES engine peak performance of 0.5 byte/clock cycle.
• AES engine supports:
– Electronic Code Book (ECB) decode mode with 128-bit key.
– Cypher Block Chaining (CBC) decode mode with 128-bit key.
– CMAC hash calculation (see Section 7.3.4) for the boot image only.

• The AES engine is compliant with the FIPS (Federal Information Processing
Standard) Publication 197, Advanced Encryption Standard (AES).

• Random Number Generator (RNG) is supported by the AES API and passes the
following tests:
– diehard
– FIPS_140-1
– NIST

• Data is processed in little endian mode. This means that the first byte read from flash
is integrated into the AES codeword as least significant byte. The 16th byte read from
flash is the most significant byte of the first AES codeword.

• DMA transfers supported through the GPDMA.
Details of the AES decryption pertaining to the boot process are described in Chapter 7.
Remark: For other decode modes (Cipher Feedback (CFB), Output Feedback (OFB), and
Counter (CTR)), please contact the NXP sales office.

8.3 General description
The secure parts provide an on-chip hardware AES decryption and encryption engine to
protect the external image content and to accelerate processing for data decryption, data
integrity, and proof of origin. AES decryption can be applied to an external boot image
using a key that is itself encrypted and is stored in the OTP. This key cannot be read by
software or by any other means, and its encryption is unique for each part. In addition,
data can be encrypted or decrypted by the AES engine using the encrypted key in the
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OTP, a second key stored in the OTP (this key is not encrypted), a software supplied key,
or a key generated by an on-chip random number generator. For encryption and
decryption of data, an API is provided.
The AES hardware consists of these components:

• One-time programmable (OTP) non-volatile memory to store the AES keys. Two
instances (OTP1/2) are offered to store the two keys using the AES API (Table 75).

• An AES decryption engine. The AES uses a 128-bit key and processes blocks of 128
bit. Using the AES API, the keys can be stored in a dedicated hardware interface that
is not visible to software.

• The AES encryption engine. Encryption is selected through the AES_SetMode
command. The command returns an error if the parts are not configured for
encryption.

• The AES encryption and decryption engine supports DMA for transferring data
between memory and the AES engine.

• The ROM-based AES API for encrypting and decrypting data, storing and retrieving
keys, and for interfacing with the GPDMA.
The AES engine can be loaded with four different keys:
1. Key1 - user-defined and stored in the OTP uniquely encrypted for each part; used by
the boot code to decrypt boot image; can also be used to encrypt or decrypt data. This
key is the most secure key, as the original, programmed key is encrypted in the OTP
memory on-chip and cannot be read by software.
2. Key2 - user-defined and stored in the OTP; used to encrypt or decrypt data.
3. A software defined key.
4. A key generated by the Random Number Generator (RNG).

plain-text
data

GPDMA
decrypt

AES
engine
ECB or CBC

encrypt
GPDMA

encypted
data

key

software vector

unique id vector

OTP bank 2
software key
random number key

OTP bank 1

CBC init
vector

Using the GPDMA to transfer data in or out of the AES engine is optional.

Fig 30. AES data encryption/decryption

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Remark: The randomly generated and software defined keys are not retained during
Deep power-down and reset and must be reloaded.
Remark: To update the Random Number Generator (RNG) and load a new random
number, first use the otp_GenRand() API call, and then the aes_LoadKeyRNG() call (see
Section 8.5.6).

8.4 AES API
The AES is controlled through a set of simple API calls located in the LPC43Sxx ROM.
The API calls to the ROM are performed by executing functions which are pointed to by
pointer within the ROM driver table.

Ptr to ROM Driver table
0x1040 0108

Device 0
ROM Driver Table
0x1040 0100

Ptr to Function 0

Ptr to Device Table 0

Ptr to Function 1

Ptr to Device Table 1

Ptr to Function 2

0x1040 0104
0x1040 0108

…
Ptr to AES driver table
Ptr to Function n

0x1040 010C

…
AES Driver
Ptr to Device Table n

aes_Init
aes_SetMode
aes_LoadKey1
aes_LoadKey2
aes_LoadKeyRNG
aes_LoadKeySW
aes_LoadIVSW
aes_LoadIVIC
aes_Operate
aes_ProgramKey1
aes_ProgramKey2
aes_Config_DMA
aes_Operate_DMA
aes_Get_Status_DMA

Fig 31. AES driver pointer structure

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8.4.1 AES functions
The ROM-based security AES API controls the AES block. AES API functions are
provided to encrypt or decrypt data from memory to memory using an ECB or CBC
algorithm. If the CBC algorithm is selected, a user-defined initialization vector can be
defined.
To transfer data between memory and the AES peripheral using the GPDMA, additional
API functions are provided that configure the GPDMA, DMA peripheral input mux, and the
AES appropriately.
The AES API can load one of four keys to encrypt or decrypt data:

• Key1 stored in OTP memory bank 1. This is a secure key used by the boot code for
decrypting the boot image.

• Key2 stored in OTP memory bank 2.
• A software-generated key.
• A key generated by the on-chip random number generator.
Two APIs are provided to store keys in the OTP memory banks 1 and 2.
Table 75.

AES API calls

Function

Offset relative to Description
the API entry
point

aes_Init

0x00

Initialize AES engine
Parameter - void
Return - void

aes_SetMode

0x04

Defines AES engine operation mode
Parameter: unsigned cmd with values:
0 - ECB encode AES_API_CMD_ENCODE_ECB (if the parts are not
configured for encryption, using aes_SetMode with this parameter returns an
error)
1 - ECB decode AES_API_CMD_DECODE_ECB
2 - CBC encode AES_API_CMD_ENCODE_CBC (if the parts are not
configured for encryption, using aes_SetMode with this parameter returns an
error)
3 - CBC decode AES_API_CMD_DECODE_CBC
Return - unsigned: see general error codes.

aes_LoadKey1

0x08

Loads 128-bit AES user key 1
Parameter - void
Return - unsigned: see general error codes.

aes_LoadKey2

0x0C

Loads 128-bit AES user key 2
Parameter - void
Return - unsigned: see general error codes.

aes_LoadKeyRNG

0x10

Loads randomly generated key in AES engine. To update the RNG and load
a new random number, use the API call otp_GenRand before
aes_LoadKeyRNG.
Parameter - void
Return - void

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Table 75.

AES API calls

Function

Offset relative to Description
the API entry
point

aes_LoadKeySW

0x14

Loads 128-bit AES software defined user key
Parameter - unsigned char *key(16 bytes)
Return - unsigned: see general error codes.

aes_LoadIV_SW

0x18

Loads 128-bit AES initialization vector
Parameter - unsigned char *iv(16 bytes)
Return - unsigned: see general error codes.

aes_LoadIV_IC

0x1C

Loads 128-bit AES IC specific initialization vector, which is used to decrypt a
boot image.
Parameter - void
Return - unsigned: see general error codes.

aes_Operate

0x20

Performs the AES encryption or decryption after the AES mode has been set
using aes_Set_Mode and the appropriate keys and init vectors have been
loaded.
Parameter1 - unsigned char *data_out
Parameter2 - unsigned char *data_in
Parameter3 - unsigned size (128-bit word - 16 byte)
Return - unsigned: see general error codes.

aes_ProgramKey1

0x24

Programs 128-bit AES key in OTP.
Parameter: unsigned char *key (16 byte)
Return - unsigned: see general error codes.
Remark: When calling the aes_ProgramKey1 function, ensure that VPP =
2.7 V to 3.6 V.

aes_ProgramKey2

0x28

Programs 128-bit AES key in OTP.
Parameter: unsigned char *key (16 byte)
Return - unsigned: see general error codes.
Remark: When calling the aes_ProgramKey2 function, ensure that VPP =
2.7 V to 3.6 V.

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Table 75.

AES API calls

Function

Offset relative to Description
the API entry
point

aes_Config_DMA

0x2C

Checks for valid AES configuration of the chip and setup DMA channel to
process an AES data block.
Parameter: unsigned channel_id
Return - unsigned:
AES_API_ERROR_NOT_SUPPORTED
AES_API_ERROR_DMA_CHANNEL_CFG
AES_API_ERROR_DMA_MUX_CFG
AES_API_NO_ERROR

aes_Operate_DMA

0x30

Checks for valid AES configuration of the chip and enables DMA channel to
process an AES data block.
Parameter1: unsigned channel_id.
Parameter2: unsigned char *dataOutAddr (16 x size of consecutive bytes)
Parameter3: unsigned char *dataInAddr (16 x size of consecutive bytes)
Parameter4: unsigned size (number of 128 bit AES blocks)
Return – unsigned:
AES_API_ERROR_NOT_SUPPORTED
AES_API_NO_ERROR

aes_Get_Status_DMA

0x34

Read status of DMA channels that process an AES data block.
Parameter: channel_id.
Return – unsigned:
AES_API_NO_ERROR
AES_API_DMA_BUSY

8.4.1.1 AES ROM driver variables
The parameter channel_id is a combination of channel selection and DMA mux
configuration and is defined as follows:
Bits[2:0]: Destination channel number (0 to 7).
Bits[11:8]: Destination peripheral control number (select 2 or 14. These are the AES out
request lines).
Bits[13:12]: Destination DMA mux selection (use 3 if destination peripheral control
number is 2, use 1 if destination peripheral control number is 14).
Bits[18:16]: Source channel number (0 to 7).
Bits[27:24]: Source peripheral control number (select 1 or 13, these are the AES in
request lines).
Bits[29:28]: Source DMA mux selection (use 3 if destination peripheral control number is
1, use 1 if destination peripheral control number is 13).
Remark: Selecting the AES input and output DMA request lines in the channel_id
structure configures the DMAMUX register (see Section 11.4.5) in the CREG block for
AES.

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8.4.1.2 AES Error codes
For general error codes, see Chapter 53 “LPC43xx/LPC43Sxx API General error codes”.
/* Security API related errors */
ERR_SEC_AES_BASE = 0x00030000,
/*0x00030001*/ ERR_SEC_AES_WRONG_CMD=ERR_SEC_AES_BASE+1,
/*0x00030002*/ ERR_SEC_AES_NOT_SUPPORTED,
/*0x00030003*/ ERR_SEC_AES_KEY_ALREADY_PROGRAMMED,
/*0x00030004*/ ERR_SEC_AES_DMA_CHANNEL_CFG,
/*0x00030005*/ ERR_SEC_AES_DMA_MUX_CFG,
/*0x00030006*/ SEC_AES_DMA_BUSY,

8.5 Functional description
8.5.1 Using the AES API without DMA
Use the AES API functions as follows for data encryption/decryption without DMA:
1. Initialize the AES by calling aes_Init.
If the part is not a secure part, this routine returns an error.
2. Load the key:
– aes_LoadKey1 loads the secure key from OTP memory bank1.
– aes_LoadKey2 loads the non-secure key from OTP memory bank2.
– aes_LoadKeyRNG loads a randomly generated key.
– aes_LoadKeySW loads a key generated by the user code.
3. If using CBC encode or decode, load an initialization vector:
– aes_LoadIV_SW loads a vector generated by the user code.
– aes_LoadIV_IC loads a vector generated from the unique part ID.
4. Define the AES mode by calling aes_SetMode.
Select encryption or decryption and the encoding algorithm (ECB or CBC).
5. Run the AES engine by calling aes_Operate.
The AES engine reads the data from a specified memory location and copies the
encrypted or decrypted data to another memory location in 128-bit blocks.

8.5.2 Using the AES API with DMA
Use the AES API functions as follows for data encryption/decryption with DMA:
1. Initialize the AES by calling aes_Init.
If the part is not a secure part, this routine returns an error.
2. Load the key:
– aes_LoadKey1 loads the secure key from OTP memory bank1.
– aes_LoadKey2 loads the non-secure key from OTP memory bank2.
– aes_LoadKeyRNG loads a randomly generated key.
– aes_LoadKeySW loads a key generated by the user code.
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3. If using CBC encode or decode, load an initialization vector:
– aes_LoadIV_SW loads a vector generated by the user code.
– aes_LoadIV_IC loads a vector generated from the unique part id.
4. Define the AES mode by calling aes_SetMode.
Select encryption or decryption and the encoding algorithm (ECB or CBC).
5. Set up the channel_id parameter with the DMA channel, the peripheral source and
destination numbers, and the DMA input mux settings.
6. Configure the GPDMA by calling aes_Config_DMA.
7. Run the AES engine by calling aes_Operate_DMA.
The AES engine reads the data from a specified memory location and copies the
encrypted or decrypted data to another memory location in 128-bit blocks.
8. Check whether the AES is done by calling aes_Get_Status_DMA.

8.5.3 AES Decryption
Secure boot authenticates and decrypts the boot image. See Section 7.3.2.
AES decryption can also be used on non-image data. It is possible to decrypt a frame of
Cipher Text independent of other Cipher Text frames. This is useful when a random frame
needs to be accessed.

8.5.4 Use of AES keys
The two hardware keys stored in OTP cannot be accessed by software and offer a high
security level. Key1 is stored encrypted in the OTP and offers the highest security level.
The software key is a software defined AES key. Since this key is visible to software, it is
less secure than the hardware defined keys in OTP. However, the OTP can only store two
keys whereas multiple keys can be stored in software.
The 128-bit AES initialization vector iv is used to randomize the encryption when the same
data is encrypted multiple times. The init vector does not have to be secret and is also
used to decrypt the data. For the CMAC calculation, an AES initialization vector of iv = 0 is
used.
For the LPC43Sxx image, a user specific iv is used:
iv = AES-1(User Key, 1)

8.5.5 Endianness
The AES engine is capable of processing 128-bit (16-byte) blocks per operation. To
load/store an AES block, the 32-bit infrastructure is fully used. For convenience, the API
interface uses byte order rather than word order. The API passes/obtains a pointer to an
array of bytes, and the AES low-level driver type-casts the pointer to an unsigned 32-bit
array. Figure 32 shows 16-byte data AES encryption with a 16-byte key. For simplicity,
data and key bytes are chosen in incrementing order starting from 00.

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Chapter 8: LPC43Sxx Security API

RAM Offset

0

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

IV and Key: Always little endian
IV: 000102030405060708090a0b0c0d0e0f

0F 0E 0D 0C 0B 0A 09 08 07 06 05 04 03 02 01 00

Key: 2b7e151628aed2a6abf7158809cf4f3c

3C 4F CF 09 88 15 F7 AB A6 D2 AE 28 16 15 7E 2B

Plain/Cipher: ROM API requires little endian
Plain: 6bc1bee22e409f96e93d7e117393172a

2A 17 93 73 11 7E 3D E9 96 9F 40 2E E2 BE C1 6B

Cipher: 7649abac8119b246cee98e9b12e9197d

7D 19 E9 12 9B 8E E9 CE 46 B2 19 81 AC AB 49 76
aaa-020544

Fig 32. AES endianness

8.5.6 Storing AES keys in Deep power-down mode
In Deep power-down mode, all AES information is lost. After wake-up, the AES keys need
to be reloaded. If you want to use the same RNG key as before entering Deep
power-down mode, then you can store the RNG key in the backup registers at
0x4004 0000. Process the AES keys in the following order:
1. Generate a random number by calling the otp_GenRand() API.
2. Read the 128-bit random number at the following addresses: the addresses are
located in the OTP controller memory space - not in the physical otp memory.
– Bits 31:0 at location 0x4004 5050
– Bits 63:32 at location 0x4004 5054
– Bits 95:64 at location 0x4004 5058
– Bits 127:96 at location 0x4004 505C
3. Store this number in the RTC REGFILE registers.
4. Load this number in the AES engine using aes_LoadKeySW.
After every wake-up, perform the following operations:
1. Load the stored random number from the backup register.
2. Load this number in the AES engine using aes_LoadKeySW.

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Chapter 9: LPC43xx/LPC43Sxx Nested Vectored Interrupt
Controller (NVIC)
Rev. 2.4 — 22 August 2018

User manual

9.1 How to read this chapter
The NVIC interrupt sources vary for different parts.

• Ethernet interrupt: available only on LPC436x/5x/3x, LPC43S6x/S5x/S3x, and
LPC4370/LPC43S70.

• USB0 interrupt: available only on LPC436x/5x/3x, LPC43S6x/S5x/S3x, and
LPC4370/LPC43S70.

• USB1 interrupt: available only on LPC436x/5x/3x, LPC43S6x/S5x/S3x, and
LPC4370/LPC43S70.

• Flash/EEPROM interrupts: available on parts with on-chip flash only.
The Cortex-M0SUB subsystem core NVIC is only available on parts LPC4370/LPC43S70
and LPC436x/LPC43S6x.

9.2 Basic configuration
On the LPC43xx/LPC43Sxx, each core is supports its own NVIC. Each core can only
access its own local NVIC registers.

9.3 Features
• Nested Vectored Interrupt Controllers are integral parts of the ARM Cortex-M4 and
M0 processors.

•
•
•
•

Tightly coupled interrupt controllers provides low interrupt latency.
NVICs control system exceptions and peripheral interrupts.
Software interrupt generation is supported.
Cortex-M4 core:
– Up to 53 interrupts
– Relocatable vector table
– Non-Maskable Interrupt
– Eight programmable interrupt priority levels with hardware priority level masking

• Cortex-M0APP application core:
– Up to 32 interrupts
– Four programmable interrupt priority levels with hardware priority level masking

• Cortex-M0SUB subsystem core:
– Up to 32 interrupts
– Four programmable interrupt priority levels with hardware priority level masking

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Chapter 9: LPC43xx/LPC43Sxx Nested Vectored Interrupt Controller

9.4 General description
The Nested Vectored Interrupt Controller (NVIC) is an integral part of the Cortex-M4 and
M0. The tight coupling to the CPU allows for low interrupt latency and efficient processing
of late arriving interrupts.
Refer to the Cortex-M4 User Guide for details of NVIC operation.

9.5 Pin description
Table 76.

NVIC pin description

Function

Direction

Description

NMI

I

External Non-Maskable Interrupt (NMI) input

9.6 Interrupt sources
Table 77 lists the interrupt sources for each peripheral function. Each peripheral device
may have one or more interrupt lines to the Vectored Interrupt Controller. Each line may
represent more than one interrupt source, as noted.
Exception numbers relate to where entries are stored in the exception vector table.
Interrupt numbers are used in some other contexts, such as software interrupts.
In addition to the signals listed in Table 77 and Table 78, the NVIC handles the
Non-Maskable Interrupt (NMI). In order for NMI to operate from an external signal, the
NMI function must be connected to the related device pin (P4_0 or PE_4). When
connected, a logic one on the pin will cause the NMI to be processed. For details, refer to
the Cortex-M4 or Cortex-M0 User Guide.

9.6.1 Interrupt sources for the Cortex-M4
Table 77.

Connection of interrupt sources to the Cortex-M4 NVIC

Interrupt Exception Vector
ID
Number
Offset

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Function

Flags

0

16

0x40

DAC

-

1

17

0x44

M0APP

Cortex-M0APP; Latched TXEV; for
M4-M0APP communication

2

18

0x48

DMA

-

3

19

0x4C

-

Reserved

4

20

0x50

FLASHEEPROM

ORed flash bank A, flash bank B,
EEPROM interrupts

5

21

0x54

ETHERNET

Ethernet interrupt

6

22

0x58

SDIO

SD/MMC interrupt

7

23

0x5C

LCD

-

8

24

0x60

USB0

OTG interrupt

9

25

0x64

USB1

-

10

26

0x68

SCTimer/PWM

SCTimer/PWM combined interrupt

11

27

0x6C

RITIMER

-

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Table 77.

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Connection of interrupt sources to the Cortex-M4 NVIC

Interrupt Exception Vector
ID
Number
Offset

Function

Flags

12

28

0x70

TIMER0

-

13

29

0x74

TIMER1

-

14

30

0x78

TIMER2

-

15

31

0x7C

TIMER3

-

16

32

0x80

MCPWM

Motor control PWM

17

33

0x84

ADC0

-

18

34

0x88

I2C0

-

19

35

0x8C

I2C1

-

20

36

0x90

SPI

-

21

37

0x94

ADC1

-

22

38

0x98

SSP0

-

23

39

0x9C

SSP1

-

24

40

0xA0

USART0

-

25

41

0xA4

UART1

Combined UART interrupt with
Modem interrupt

26

42

0xA8

USART2

-

27

43

0xAC

USART3

Combined USART interrupt with IrDA
interrupt

28

44

0xB0

I2S0

-

29

45

0xB4

I2S1

-

30

46

0xB8

SPIFI

-

31

47

0xBC

SGPIO

-

32

48

0xC0

PIN_INT0

GPIO pin interrupt 0

33

49

0xC4

PIN_INT1

GPIO pin interrupt 1

34

50

0xC8

PIN_INT2

GPIO pin interrupt 2

35

51

0xCC

PIN_INT3

GPIO pin interrupt 3

36

52

0xD0

PIN_INT4

GPIO pin interrupt 4

37

53

0xD4

PIN_INT5

GPIO pin interrupt 5

38

54

0xD8

PIN_INT6

GPIO pin interrupt 6

39

55

0xDC

PIN_INT7

GPIO pin interrupt 7

40

56

0xE0

GINT0

GPIO global interrupt 0

41

57

0xE4

GINT1

GPIO global interrupt 1

42

58

0xE8

EVENTROUTER

Event router interrupt

43

59

0xEC

C_CAN1

-

44

60

0xF0

Reserved

-

45

61

0xF4

ADCHS

ADCHS combined interrupt

46

62

0xF8

ATIMER

Alarm timer interrupt

47

63

0xFC

RTC

-

48

64

0x100

Reserved

-

49

65

0x104

WWDT

-

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Table 77.

Connection of interrupt sources to the Cortex-M4 NVIC

Interrupt Exception Vector
ID
Number
Offset

Function

Flags

50

66

0x108

M0SUB

TXEV instruction from the M0
subsystem core

51

67

0x10C

C_CAN0

-

52

68

0x110

QEI

-

9.6.2 Interrupt sources for the Cortex-M0APP
Table 78.

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Connection of interrupt sources to the Cortex-M0APP NVIC

Interrupt Exception Vector
ID
Number
Offset

Function

Flag(s)

0

16

0x40

M0_RTC

-

1

17

0x44

M0_M4CORE

Interrupt from the M4 core

2

18

0x48

M0_DMA

-

3

19

0x4C

-

Reserved

4

20

0x50

M0_FLASHEEPROMAT ORed flash bank A, flash bank B,
EEPROM, Atimer interrupts

5

21

0x54

M0_ETHERNET

Ethernet interrupt

6

22

0x58

M0_SDIO

SD/MMC interrupt

7

23

0x5C

M0_LCD

-

8

24

0x60

M0_USB0

OTG interrupt

9

25

0x64

M0_USB1

-

10

26

0x68

M0_SCT

SCTimer/PWM combined interrupt

11

27

0x6C

M0_RITIMER_OR_
WWDT

RI timer interrupt ORed with WWDT
interrupt

12

28

0x70

M0_TIMER0

-

13

29

0x74

M0_GINT1

GPIO global interrupt 1

14

30

0x78

PIN_INT4

GPIO pin interrupt 4

15

31

0x7C

M0_TIMER3

-

16

32

0x80

M0_MCPWM

Motor control PWM

17

33

0x84

M0_ADC0

-

18

34

0x88

M0_I2C0_OR_I2C1

-

19

35

0x8C

M0_SGPIO

-

20

36

0x90

M0_SPI_OR_DAC

SPI interrupt ORed with DAC interrupt

21

37

0x94

M0_ADC1

-

22

38

0x98

M0_SSP0_OR_SSP1

SSP0 interrupt ORed with SSP1
interrupt

23

39

0x9C

M0_EVENTROUTER

Event router

24

40

0xA0

M0_USART0

-

25

41

0xA4

M0_UART1

Modem/UART1 interrupt

26

42

0xA8

M0_USART2_OR_
C_CAN1

USART2 interrupt ORed with
C_CAN1 interrupt

27

43

0xAC

M0_USART3

-

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Table 78.

Connection of interrupt sources to the Cortex-M0APP NVIC

Interrupt Exception Vector
ID
Number
Offset

Function

Flag(s)

28

44

0xB0

M0_I2S0_OR_I2S1_QEI I2S0 OR I2S1 OR QEI interrupt

29

45

0xB4

M0_C_CAN0

-

30

46

0xB8

M0_SPIFI_OR_ADCHS

SPIFI OR ADCHS interrupt

31

47

0xBC

M0_M0SUB

M0SUB core

9.6.3 Interrupt sources for the Cortex-M0SUB subsystem
Table 79.

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Connection of interrupt sources to the Cortex-M0SUB subsystem NVIC

Interrupt Exception Vector
ID
Number
Offset

Function

Flag(s)

0

16

0x40

M0S_DAC

-

1

17

0x44

M0S_M4CORE

Interrupt from the M4 core

2

18

0x48

M0S_DMA

-

3

19

0x4C

-

Reserved

4

20

0x50

M0S_SGPIO_INPUT

SGPIO input bit match

5

21

0x54

M0S_SGPIO_MATCH

SGPIO pattern match

6

22

0x58

M0S_SGPIO_SHIFT

SGPIO shift clock

7

23

0x5C

M0S_SGPIO_POS

SGPIO capture clock

8

24

0x60

M0S_USB0

OTG interrupt

9

25

0x64

M0S_USB1

-

10

26

0x68

M0S_SCT

SCTimer/PWM combined interrupt

11

27

0x6C

M0S_RITIMER

RI timer interrupt

12

28

0x70

M0S_GINT1

GPIO global interrupt 1

13

29

0x74

M0S_TIMER1

-

14

30

0x78

M0S_TIMER2

-

15

31

0x7C

M0S_PIN_INT5

GPIO pin interrupt 5

16

32

0x80

M0S_MCPWM

Motor control PWM

17

33

0x84

M0S_ADC0

-

18

34

0x88

M0S_I2C0

-

19

35

0x8C

M0S_I2C1

-

20

36

0x90

M0S_SPI

SPI interrupt

21

37

0x94

M0S_ADC1

-

22

38

0x98

M0S_SSP0_OR_SSP1

SSP0 interrupt ORed with SSP1
interrupt

23

39

0x9C

M0S_EVENTROUTER

Event router

24

40

0xA0

M0S_USART0

-

25

41

0xA4

M0S_UART1

Modem/UART1 interrupt

26

42

0xA8

MS0_USART2_OR_
C_CAN1

USART2 interrupt ORed with
C_CAN1 interrupt

27

43

0xAC

M0S_USART3

-

28

44

0xB0

M0S_I2S0_OR_I2S1_
OR_QEI

I2S0 OR I2S1 OR QEI interrupt

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Chapter 9: LPC43xx/LPC43Sxx Nested Vectored Interrupt Controller

Table 79.

Connection of interrupt sources to the Cortex-M0SUB subsystem NVIC

Interrupt Exception Vector
ID
Number
Offset

Function

Flag(s)

29

45

0xB4

M0S_C_CAN0

-

30

46

0xB8

M0S_SPIFI_OR_ADCHS SPIFI OR ADCHS combined
interrupt

31

47

0xBC

M0S_M0APP

M0APP core

9.7 Register description
The following table summarizes the registers in the NVIC. The Cortex-M4/M0 User
Guides provide a functional description of the NVIC registers.
Table 80.

Register overview: NVIC (base address 0xE000 E000)

Name

Access Address
offset

Description

Reset
value

ISER0

RW

0x100

Interrupt Set-Enable Register 0. This register allows enabling interrupts and
reading back the interrupt enables for specific peripheral functions.

0

ISER1

RW

0x104

Interrupt Set-Enable Register 1. This register allows enabling interrupts and
reading back the interrupt enables for specific peripheral functions.

0

ICER0

RW

0x180

Interrupt Clear-Enable Register 0. This register allows disabling interrupts and
reading back the interrupt enables for specific peripheral functions.

0

ICER1

RW

0x184

Interrupt Clear-Enable Register 1. This register allows disabling interrupts and
reading back the interrupt enables for specific peripheral functions.

0

ISPR0

RW

0x200

Interrupt Set-Pending Register 0. This register allows changing the interrupt
state to pending and reading back the interrupt pending state for specific
peripheral functions.

0

ISPR1

RW

0x204

Interrupt Set-Pending Register 1. This register allows changing the interrupt
state to pending and reading back the interrupt pending state for specific
peripheral functions.

0

ICPR0

RW

0x280

Interrupt Clear-Pending Register 0. This register allows changing the interrupt
state to not pending and reading back the interrupt pending state for specific
peripheral functions.

0

ICPR1

RW

0x284

Interrupt Clear-Pending Register 1. This register allows changing the interrupt
state to not pending and reading back the interrupt pending state for specific
peripheral functions.

0

IABR0

RO

0x300

Interrupt Active Bit Register 0. This register allows reading the current interrupt
active state for specific peripheral functions.

0

IABR1

RO

0x304

Interrupt Active Bit Register 1. This register allows reading the current interrupt
active state for specific peripheral functions.

0

IPR0

RW

0x400

Interrupt Priority Registers 0. This register allows assigning a priority to each
interrupt. Each register contains the 3-bit priority fields for 4 interrupts.

0

IPR1

RW

0x404

Interrupt Priority Registers 1 This register allows assigning a priority to each
interrupt. Each register contains the 3-bit priority fields for 4 interrupts.

0

IPR2

RW

0x408

Interrupt Priority Registers 2. This register allows assigning a priority to each
interrupt. Each register contains the 3-bit priority fields for 4 interrupts.

0

IPR3

RW

0x40C

Interrupt Priority Registers 3. This register allows assigning a priority to each
interrupt. Each register contains the 3-bit priority fields for 4 interrupts.

0

IPR4

RW

0x410

Interrupt Priority Registers 4. This register allows assigning a priority to each
interrupt. Each register contains the 3-bit priority fields for 4 interrupts.

0

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Chapter 9: LPC43xx/LPC43Sxx Nested Vectored Interrupt Controller

Table 80.

Register overview: NVIC (base address 0xE000 E000) …continued

Name

Access Address
offset

Description

Reset
value

IPR5

RW

0x414

Interrupt Priority Registers 5. This register allows assigning a priority to each
interrupt. Each register contains the 3-bit priority fields for 4 interrupts.

0

IPR6

RW

0x418

Interrupt Priority Registers 6. This register allows assigning a priority to each
interrupt. Each register contains the 3-bit priority fields for 4 interrupts.

0

IPR7

RW

0x41C

Interrupt Priority Registers 7. This register allows assigning a priority to each
interrupt. Each register contains the 3-bit priority fields for 4 interrupts.

0

STIR

WO

0xF00

Software Trigger Interrupt Register. This register allows software to generate an 0
interrupt.

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Chapter 10: LPC43xx/LPC43Sxx Event router
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User manual

10.1 How to read this chapter
The event router sources vary for different parts.

• Ethernet: available only on LPC436x/5x/3x, LPC43S6x/S5x/S3x, and
LPC4370/LPC43S70.

• USB0: available only on LPC436x/5x/3x, LPC43S6x/S5x/S3x, and
LPC4370/LPC43S70.

• USB1: available only on LPC436x/5x/3x, LPC43S6x/S5x/S3x, and
LPC4370/LPC43S70.
Remark: The event monitor/recorder interrupt from the RTC block is implemented in parts
with on-chip flash only.

10.2 Basic configuration
• See Table 81 for clocking.
• The event router is connected to interrupt #42 in the NVIC (see Table 77).
• The CREG0 register configures the WAKEUP0/1 pins as inputs to the event router or
as outputs which monitor the output of the event router (see Table 96).

• In order to detect an event connected to any of the peripheral interrupts, set the
corresponding bit to HIGH in the HILO register (the default setting of this register is
LOW).

• When using events #4 and #5, activate the 32 kHz oscillator in the CREG0 register
(Table 96).
Table 81.

Event router clocking and power control

Clock to event router

Base clock

Branch clock

Operating
frequency

BASE_M4_CLK

CLK_M4_BUS up to 204 MHz

10.3 General description
The event router is used to process wake-up events such as certain interrupts and
external or internal inputs for wake-up from any of the Power-down modes (Sleep,
Deep-sleep, Power-down, and Deep power-down modes).
In Deep-sleep, Power-down, or Deep power-down mode, only events on one of the four
WAKEUP pins and the RTC and alarm timer events, if the 32 kHz oscillator is running, are
active (see Table 82).
All events can wake up the part from Sleep mode. However, the RTC and alarm timer
events require that the 32 kHz oscillator is running.

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Chapter 10: LPC43xx/LPC43Sxx Event router

The event router has multiple event inputs from various peripherals. When the proper
edge detection is set in the EDGE configuration register, the event router can wake up the
part or can raise an interrupt in the NVIC.
Each event input to the event router can be configured to trigger an output signal on rising
or falling edges or on HIGH or LOW levels. The event router combines all events to an
output signal which is used as follows:

• Create an interrupt if the event router interrupt is enabled in the NVIC.
• Send an interrupt to the NVIC to wake up from WFI induced Sleep mode or
Deep-sleep mode.

• Wake up from WFE induced Sleep or Deep-sleep mode.
• Send a wake-up signal to the power management unit to wake up from Deep-sleep,
Power-down, and Deep power-down modes.

• Send a wake-up signal to CCU1 and CCU2 for turning on wake-up enabled branch
clocks (see Section 14.5.3).

WAKEUP1:0

CREG
WAKEUP3:2

NVIC

Core

PMU

Power regulator

CCU

wake-up

Peripheral interrupts

EVENT ROUTER

Events
0 to 19

GIMA outputs 27:26
Reset

Fig 33. Event router block diagram

10.4 Event router inputs
Table 82.

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Event router inputs

Event #

Source

Description

0

WAKEUP0 pin

WAKEUP0 pin. Always active. Use for wake-up from Deep
power-down and all other Power-down modes.

1

WAKEUP1 pin

WAKEUP1 pin. Always active. Use for wake-up from Deep
power-down and all other Power-down modes.

2

WAKEUP2 pin

WAKEUP2 pin. Always active. Use for wake-up from Deep
power-down and all other Power-down modes.

3

WAKEUP3 pin

WAKEUP3 pin. Always active. Use for wake-up from Deep
power-down and all other Power-down modes.

4

Alarm timer peripheral

Alarm timer interrupt. Active whenever the 32 kHz oscillator
is running.

5

RTC peripheral

RTC interrupt and event recorder/monitor interrupt (see
Section 10.1). Active whenever the 32 kHz oscillator is
running.

6

BOD trip level 1

BOD interrupt. Not active in Deep-sleep, Power-down, and
Deep power-down mode. Use for wake-up from Sleep
mode.

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Chapter 10: LPC43xx/LPC43Sxx Event router

Table 82.

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Event router inputs

Event #

Source

Description

7

WWDT peripheral

WWDT interrupt. Not active in Deep-sleep, Power-down,
and Deep power-down mode. Use for wake-up from Sleep
mode.

8

Ethernet peripheral

Wake-up packet indicator. Not active in Deep-sleep,
Power-down, and Deep power-down mode. Use for
wake-up from Sleep mode.

9

USB0 peripheral

Wake-up request signal. Not active in power-down and
deep power-down mode. Use for wake-up from sleep and
deep-sleep mode. See Section 25.12.4.

10

USB1 peripheral

USB1 AHB_NEED_CLK signal. Not active in power-down
and deep power-down mode. Use for wake up from sleep
and deep-sleep mode.See Section 26.7.1.

11

SD/MMC peripheral

SD/MMC interrupt. Not active in Deep-sleep, Power-down,
and Deep power-down mode. Use for wake-up from Sleep
mode.

12

C_CAN0/1 peripherals

ORed C_CAN0 and C_CAN1 interrupt. Not active in
Deep-sleep, Power-down, and Deep power-down mode.
Use for wake-up from Sleep mode.

13

GIMA output 25

Output 2 of the combined timer (ORed output of
SCTimer/PWM output 2 and the match channel 2 of timer
0). See Table 209. Not active in Deep-sleep, Power-down,
and Deep power-down mode. Use for wake-up from Sleep
mode.

14

GIMA output 26

Output 6 of the combined timer (ORed output of
SCTimer/PWM output 6 and the match channel 2 of timer
1). See Table 209. Not active in Deep-sleep, Power-down,
and Deep power-down mode. Use for wake-up from Sleep
mode.

15

QEI peripheral

QEI interrupt. Not active in Deep-sleep, Power-down, and
Deep power-down mode. Use for wake-up from Sleep
mode.

16

GIMA output 27

Output 14 of the combined timer (ORed output of
SCTimer/PWM output 14 and the match channel 2 of timer
3). See Table 209. Not active in Deep-sleep, Power-down,
and Deep power-down mode. Use for wake-up from Sleep
mode.

17

-

Reserved

18

-

Reserved

19

Reset

Reset event on pin RESET. Always functional. Active LOW.

20

BOD reset

Voltage on VDD(REG)(3V3) falls below the BOD reset level.
Active HIGH.

21

DPD

Wake-up from Deep power-down mode. At this time the
part is reset. Active HIGH.

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10.5 Pin description
Table 83.

Event router pin description

Pin

Direction

Description

WAKEUP0/1

I/O

External wake-up input; can raise an event router interrupt
and can cause wake-up from any of the power-down
modes. These pins can be configured to monitor the event
router output through the CREG0 register (Table 96).

WAKEUP2/3

I

External wake-up input; can raise an event router interrupt
and can cause wake-up from any of the power-down
modes.

10.6 Register description
Table 84.
Name

Register overview: Event router (base address 0x4004 4000)
Access Address
offset

Description

Reset Value

Reference

HILO

R/W

0x000

Level configuration register 0x000

Table 85

EDGE

R/W

0x004

Edge configuration

0x000

Table 87

-

-

0x008 0xFD4

Reserved

-

-

CLR_EN

W

0xFD8

Clear event enable register 0x0

Table 88

SET_EN

W

0xFDC

Set event enable register

0x0

Table 89

STATUS

R

0xFE0

Event Status register

0x03FD FFFF

Table 90

ENABLE

R

0xFE4

Event Enable register

0x0

Table 91

CLR_STAT

W

0xFE8

Clear event status register

0x0

Table 92

SET_STAT

W

0xFEC

Set event status register

0x0

Table 93

10.6.1 Level configuration register
This register works in combination with the edge configuration register EDGE (see
Table 87) to configure the level and edge detection for each input to the event router.
Table 85.

UM10503

User manual

Level configuration register (HILO, address 0x4004 4000) bit description

Bit

Symbol

Value Description

0

WAKEUP0_L

Reset
value

Level detect mode for WAKEUP0 event.

0

0

Detect LOW level on the WAKEUP0 pin if bit 0 in the
EDGE register is 0. Detect falling edge if bit 0 in the EDGE
register is 1.

1

Detect HIGH level on the WAKEUP0 pin if bit 0 in the
EDGE register is 0. Detect rising edge if bit 0 in the EDGE
register is 1.

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Chapter 10: LPC43xx/LPC43Sxx Event router

Table 85.

Symbol

1

WAKEUP1_L

2

3

4

5

6

UM10503

User manual

Level configuration register (HILO, address 0x4004 4000) bit description

Bit

Value Description

Reset
value

Level detect mode for WAKEUP1 event. The
corresponding bit in the EDGE register must be 0.

0

0

Detect LOW level on the WAKEUP1 pin if bit 1 in the
EDGE register is 0.

1

Detect HIGH level on the WAKEUP1 pin if bit 1 in the
EDGE register is 0. Detect rising edge if bit 1 in the EDGE
register is 1.

WAKEUP2_L

Level detect mode for WAKEUP2 event.

0

0

Detect LOW level on the WAKEUP2 pin if bit 2 in the
EDGE register is 0. Detect falling edge if bit 2 in the EDGE
register is 1.

1

Detect HIGH level on the WAKEUP2 pin if bit 2 in the
EDGE register is 0. Detect rising edge if bit 2 in the EDGE
register is 1.

WAKEUP3_L

Level detect mode for WAKEUP3 event.

0

0

Detect LOW level on the WAKEUP3 pin if bit 3 in the
EDGE register is 0. Detect falling edge if bit 3 in the EDGE
register is 1.

1

Detect HIGH level on the WAKEUP3 pin if bit 3 in the
EDGE register is 0. Detect rising edge if bit 3 in the EDGE
register is 1.

0

Detect LOW level of the alarm timer interrupt if bit 4 in the
EDGE register is 0. Detect falling edge if bit 4 in the EDGE
register is 1.

1

Detect HIGH level of the alarm timer interrupt if bit 4 in the
EDGE register is 0. Detect rising edge if bit 4 in the EDGE
register is 1.

ATIMER_L

Level detect mode for alarm timer event.

RTC_L

0

Level detect mode for RTC event.

0

0

Detect LOW level of the RTC interrupt if bit 5 in the EDGE
register is 0. Detect falling edge if bit 5 in the EDGE
register is 1.

1

Detect HIGH level of the RTC interrupt if bit 5 in the EDGE
register is 0. Detect rising edge if bit 5 in the EDGE register
is 1.

BOD_L

Level detect mode for BOD event.

0

0

Detect LOW level of the BOD interrupt if bit 6 in the EDGE
register is 0. Detect falling edge if bit 6 in the EDGE
register is 1.

1

Detect HIGH level of the BOD interrupt if bit 6 in the EDGE
register is 0. Detect rising edge if bit 6 in the EDGE register
is 1.

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Chapter 10: LPC43xx/LPC43Sxx Event router

Table 85.

Symbol

7

WWDT_L

8

9

10

11

12

UM10503

User manual

Level configuration register (HILO, address 0x4004 4000) bit description

Bit

Value Description

Reset
value

Level detect mode for WWDT event.

0

0

Detect LOW level of the WWDT interrupt if bit 7 in the
EDGE register is 0. Detect falling edge if bit 7 in the EDGE
register is 1.

1

Detect HIGH level of the WWDT interrupt if bit 7 in the
EDGE register is 0. Detect rising edge if bit 7 in the EDGE
register is 1.

ETH_L

Level detect mode for Ethernet event

0

0

Detect LOW level of the Ethernet interrupt if bit 8 in the
EDGE register is 0. Detect falling edge if bit 8 in the EDGE
register is 1.

1

Detect HIGH level of the Ethernet interrupt if bit 8 in the
EDGE register is 0. Detect rising edge if bit 8 in the EDGE
register is 1.

USB0_L

Level detect mode for USB0 event

0

0

Detect LOW level of the USB0 interrupt if bit 9 in the EDGE
register is 0. Detect falling edge if bit 9 in the EDGE
register is 1.

1

Detect HIGH level of the USB0 interrupt if bit 9 in the
EDGE register is 0. Detect rising edge if bit 9 in the EDGE
register is 1.

0

Detect LOW level of the USB1 interrupt if bit 10 in the
EDGE register is 0. Detect falling edge if bit 10 in the
EDGE register is 1.

1

Detect HIGH level of the USB1 interrupt if bit 10 in the
EDGE register is 0. Detect rising edge if bit 10 in the
EDGE register is 1.

USB1_L

Level detect mode for USB1 event

SDMMC_L

0

Level detect mode for SD/MMC event

0

0

Detect LOW level of the SD/MMC interrupt if bit 11 in the
EDGE register is 0. Detect falling edge if bit 11 in the
EDGE register is 1.

1

Detect HIGH level of the SD/MMC interrupt if bit 11 in the
EDGE register is 0. Detect rising edge if bit 11 in the EDGE
register is 1.

CAN_L

Level detect mode for C_CAN event.

0

0

Detect LOW level of the combined C_CAN interrupt if bit
12 in the EDGE register is 0. Detect falling edge if bit 12 in
the EDGE register is 1.

1

Detect HIGH level of the combined C_CAN interrupt if bit
12 in the EDGE register is 0. Detect rising edge if bit 12 in
the EDGE register is 1.

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Chapter 10: LPC43xx/LPC43Sxx Event router

Table 85.

Level configuration register (HILO, address 0x4004 4000) bit description

Bit

Symbol

13

TIM2_L

14

15

16

Value Description
Level detect mode for combined timer output 2 event.

20

0

Detect LOW level GIMA output 25 if bit 13 in the EDGE
register is 0. Detect falling edge if bit 13 in the EDGE
register is 1.

1

Detect HIGH level GIMA output 25 if bit 13 in the EDGE
register is 0. Detect rising edge if bit 13 in the EDGE
register is 1.

TIM6_L

Detect LOW level of GIMA output 26 if bit 14 in the EDGE
register is 0. Detect falling edge if bit 14 in the EDGE
register is 1.

1

Detect HIGH level of GIMA output 26 if bit 14 in the EDGE
register is 0. Detect rising edge if bit 14 in the EDGE
register is 1.

QEI_L

Level detect mode for QEI event.

UM10503

User manual

0

0

Detect LOW level of the QEI interrupt if bit 15 in the EDGE
register is 0. Detect falling edge if bit 15 in the EDGE
register is 1.

1

Detect HIGH level of the QEI interrupt if bit 15 in the EDGE
register is 0. Detect rising edge if bit 15 in the EDGE
register is 1.

0

Detect LOW level of GIMA output 27 if bit 16 in the EDGE
register is 0. Detect falling edge if bit 16 in the EDGE
register is 1.

1

Detect HIGH level of GIMA output 27 if bit 16 in the EDGE
register is 0. Detect rising edge if bit 16 in the EDGE
register is 1.

-

Reserved.

TIM14_L

Level detect mode for combined timer output 14 event.

RESET_L

0

Level detect mode for Reset

0

0

Detect LOW level if bit 17 in the EDGE register is 0. Detect
falling edge if bit 17 in the EDGE register is 1.

1

Detect HIGH level if bit 17 in the EDGE register is 0.
Detect rising edge if bit 17 in the EDGE register is 1.

BODRESET_
L
0

DPDRESET_
L
0

31:22 -

0

0

1
21

0

Level detect mode for combined timer output 6 event.

18:17 19

Reset
value

Level detect mode for BOD Reset

0

Detect LOW level if bit 20 in the EDGE register is 0. Detect
falling edge if bit 20 in the EDGE register is 1.
Detect HIGH level if bit 20 in the EDGE register is 0.
Detect rising edge if bit 20 in the EDGE register is 1.
Level detect mode for Deep power-down Reset

0

Detect LOW level if bit 21 in the EDGE register is 0. Detect
falling edge if bit 21 in the EDGE register is 1.

1

Detect HIGH level if bit 21 in the EDGE register is 0.
Detect rising edge if bit 21 in the EDGE register is 1.

-

Reserved.

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Chapter 10: LPC43xx/LPC43Sxx Event router

10.6.2 Edge configuration register
This register works in combination with the level configuration register HILO (see
Table 85) to configure the level or edge detection for each input to the event router.
The EDGE configuration register determines whether the event router responds to a level
change (EDGEn=1), or a constant level (EDGEn=0). The HILOn bit determines a
response to a rising edge (HILOn=1) or a falling edge (HILOn=0).
Table 86.

EDGE and HILO combined register settings

HILO bit n

EDGE bit n

Description

0

0

Detect LOW level

0

1

Detect falling edge

1

0

Detect HIGH level

1

1

Detect rising edge

When a HIGH level detect is active, the event router status bits cannot be cleared until the
signal is LOW. When a rising edge detect is active, the event router status bit can be
cleared right after the event has occurred.
Table 87.

Symbol

0

WAKEUP0_E

1

2

3

UM10503

User manual

Edge configuration register (EDGE, address 0x4004 4004) bit description

Bit

Value Description

Reset
value

Edge detect mode for WAKEUP0 event. The
corresponding bit in the EDGE register must be 0.

0

0

Level detect.

1

Edge detect of WAKEUP0 pin. Detect falling edge if bit 0
in the HILO register is 0. Detect rising edge if bit 0 in the
HILO register is 1.

WAKEUP1_E

Edge/level detect mode for WAKEUP1 event. The
corresponding bit in the EDGE register must be 0.

0

0

Level detect.

1

Edge detect of WAKEUP1 pin. Detect falling edge if bit 1
in the HILO register is 0. Detect rising edge if bit 1 in the
HILO register is 1.

WAKEUP2_E

Edge/level detect mode for WAKEUP2 event. The
corresponding bit in the EDGE register must be 0.

0

0

Level detect.

1

Edge detect of WAKEUP2 pin. Detect falling edge if bit 2
in the HILO register is 0. Detect rising edge if bit 2 in the
HILO register is 1.

WAKEUP3_E

Edge/level detect mode for WAKEUP3 event. The
corresponding bit in the EDGE register must be 0.
0

Level detect.

1

Edge detect of WAKEUP3 pin. Detect falling edge if bit
30 in the HILO register is 0. Detect rising edge if bit 3 in
the HILO register is 1.

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0

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Chapter 10: LPC43xx/LPC43Sxx Event router

Table 87.

Symbol

4

ATIMER_E

5

6

7

8

9

10

UM10503

User manual

Edge configuration register (EDGE, address 0x4004 4004) bit description

Bit

Value Description

Reset
value

Edge/level detect mode for alarm timer event. The
corresponding bit in the EDGE register must be 0.

0

0

Level detect.

1

Edge detect of the alarm timer interrupt. Detect falling
edge if bit 4 in the HILO register is 0. Detect rising edge if
bit 4 in the HILO register is 1.

RTC_E

Edge/level detect mode for RTC event. The
corresponding bit in the EDGE register must be 0.

0

0

Level detect.

1

Edge detect of the RTC interrupt. Detect falling edge if bit
5 in the HILO register is 0. Detect rising edge if bit 5 in
the HILO register is 1.

BOD_E

Edge/level detect mode for BOD event. The
corresponding bit in the EDGE register must be 0.

0

0

Level detect.

1

Edge detect of the BOD interrupt. Detect falling edge if
bit 6 in the HILO register is 0. Detect rising edge if bit 6 in
the HILO register is 1.

WWDT_E

Edge/level detect mode for WWDTD event. The
corresponding bit in the EDGE register must be 0.

0

0

Level detect.

1

Edge detect of the WWDT interrupt. Detect falling edge if
bit 7 in the HILO register is 0. Detect rising edge if bit 7 in
the HILO register is 1.

ETH_E

Edge/level detect mode for ethernet event. The
corresponding bit in the EDGE register must be 0.

0

0

Level detect.

1

Edge detect of the Ethernet interrupt. Detect falling edge
if bit 8 in the HILO register is 0. Detect rising edge if bit 8
in the HILO register is 1.

USB0_E

Edge/level detect mode for USB0 event. The
corresponding bit in the EDGE register must be 0.

0

0

Level detect.

1

Edge detect of the USB0 event. Detect falling edge if bit
9 in the HILO register is 0. Detect rising edge if bit 9 in
the HILO register is 1.

USB1_E

Edge/level detect mode for USB1 event. The
corresponding bit in the EDGE register must be 0.

0

0

Level detect.

1

Edge detect of the USB1 interrupt. Detect falling edge if
bit 10 in the HILO register is 0. Detect rising edge if bit 10
in the HILO register is 1.

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Chapter 10: LPC43xx/LPC43Sxx Event router

Table 87.

Edge configuration register (EDGE, address 0x4004 4004) bit description

Bit

Symbol

11

SDMMC_E

12

13

14

15

16

Value Description

UM10503

User manual

Edge/level detect mode for SD/MMC event.The
corresponding bit in the EDGE register must be 0.
0

Level detect.

1

Edge detect of the SD/MMC interrupt. Detect falling edge
if bit 10 in the HILO register is 0. Detect rising edge if bit
10 in the HILO register is 1.

CAN_E

Edge/level detect mode for C_CAN event. The
corresponding bit in the EDGE register must be 0.
0

Level detect.

1

Edge detect of the combined C_CAN interrupt. Detect
falling edge if bit 12 in the HILO register is 0. Detect
rising edge if bit 12 in the HILO register is 1.

TIM2_E

0

Edge/level detect mode for combined timer output 2
event. The corresponding bit in the EDGE register must
be 0.

0

0

Level detect.

1

Edge detect of GIMA output 25. Detect falling edge if bit
13 in the HILO register is 0. Detect rising edge if bit 13 in
the HILO register is 1.

TIM6_E

0

Edge/level detect mode for combined timer output 6
event. The corresponding bit in the EDGE register must
be 0.
0

Level detect.

1

Edge detect of GIMA output 26. Detect falling edge if bit
14 in the HILO register is 0. Detect rising edge if bit 14 in
the HILO register is 1.

QEI_E

Edge/level detect mode for QEI interrupt signal. The
corresponding bit in the EDGE register must be 0.

0

0

Level detect.

1

Edge detect of QEI interrupt. Detect falling edge if bit 15
in the HILO register is 0. Detect rising edge if bit 15 in the
HILO register is 1.

TIM14_E

Edge/level detect mode for combined timer output 14
event. The corresponding bit in the EDGE register must
be 0.

18:17 19

Reset
value

0

0

Level detect.

1

Edge detect of GIMA output 27. Detect falling edge if bit
16 in the HILO register is 0. Detect rising edge if bit 16 in
the HILO register is 1.

-

Reserved.

RESET_E

Edge/level detect mode for Reset. The corresponding bit 0
in the EDGE register must be 0.
0

Level detect.

1

Edge detect of the reset signal. Detect falling edge if bit
19 in the HILO register is 0. Detect rising edge if bit 19 in
the HILO register is 1.

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Chapter 10: LPC43xx/LPC43Sxx Event router

Table 87.

Edge configuration register (EDGE, address 0x4004 4004) bit description

Bit

Symbol

20

BODRESET_E

21

Value Description

Reset
value

Edge detect of the BOD reset signal. The corresponding 0
bit in the EDGE register must be 0.
0

Level detect.

1

Edge detect of the reset signal. Detect falling edge if bit
20 in the HILO register is 0. Detect rising edge if bit 19 in
the HILO register is 1.

DPDRESET_E

Edge detect of the deep power-down reset signal. The
corresponding bit in the EDGE register must be 0.

31:22 -

0

0

Level detect.

1

Edge detect of the reset signal. Detect falling edge if bit
21 in the HILO register is 0. Detect rising edge if bit 21 in
the HILO register is 1.

-

Reserved.

10.6.3 Clear event enable register
The CLR_EN register clears the corresponding bits in the ENABLE register.
Table 88.

UM10503

User manual

Clear event enable register (CLR_EN, address 0x4004 4FD8) bit description

Bit

Symbol

Description

Reset
value

0

WAKEUP0_CLREN

Writing a 1 to this bit clears the event enable bit 0 in the
ENABLE register.

-

1

WAKEUP1_CLREN

Writing a 1 to this bit clears the event enable bit 1 in the
ENABLE register.

-

2

WAKEUP2_CLREN

Writing a 1 to this bit clears the event enable bit 2 in the
ENABLE register.

-

3

WAKEUP3_CLREN

Writing a 1 to this bit clears the event enable bit 3 in the
ENABLE register.

-

4

ATIMER_CLREN

Writing a 1 to this bit clears the event enable bit 4 in the
ENABLE register.

-

5

RTC_CLREN

Writing a 1 to this bit clears the event enable bit 5 in the
ENABLE register.

-

6

BOD_CLREN

Writing a 1 to this bit clears the event enable bit 6 in the
ENABLE register.

-

7

WWDT_CLREN

Writing a 1 to this bit clears the event enable bit 7 in the
ENABLE register.

-

8

ETH_CLREN

Writing a 1 to this bit clears the event enable bit 8 in the
ENABLE register.

-

9

USB0_CLREN

Writing a 1 to this bit clears the event enable bit 9 in the
ENABLE register.

-

10

USB1_CLREN

Writing a 1 to this bit clears the event enable bit 10 in the
ENABLE register.

-

11

SDMMC_CLREN

Writing a 1 to this bit clears the event enable bit 11 in the
ENABLE register.

-

12

CAN_CLREN

Writing a 1 to this bit clears the event enable bit 12 in the
ENABLE register.

-

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Chapter 10: LPC43xx/LPC43Sxx Event router

Table 88.

Clear event enable register (CLR_EN, address 0x4004 4FD8) bit description

Bit

Symbol

Description

Reset
value

13

TIM2_CLREN

Writing a 1 to this bit clears the event enable bit 13 in the
ENABLE register.

-

14

TIM6_CLREN

Writing a 1 to this bit clears the event enable bit 14 in the
ENABLE register.

-

15

QEI_CLREN

Writing a 1 to this bit clears the event enable bit 15 in the
ENABLE register.

-

16

TIM14_CLREN

Writing a 1 to this bit clears the event enable bit 16 in the
ENABLE register.

-

18:17 -

Reserved.

-

19

RESET_CLREN

Writing a 1 to this bit clears the event enable bit 19 in the
ENABLE register.

-

20

BODRESET_CLREN Writing a 1 to this bit clears the event enable bit 20 in the
ENABLE register.

-

21

DPDRESET_CLREN Writing a 1 to this bit clears the event enable bit 21 in the
ENABLE register.

-

31:22 -

Reserved.

-

10.6.4 Set event enable register
The SET_EN register sets the corresponding bits in the ENABLE register.
Table 89.

UM10503

User manual

Event set enable register (SET_EN, address 0x4004 4FDC) bit description

Bit

Symbol

Description

Reset
value

0

WAKEUP0_SETEN

Writing a 1 to this bit sets the event enable bit 0 in the
ENABLE register.

-

1

WAKEUP1_SETEN

Writing a 1 to this bit sets the event enable bit 1 in the
ENABLE register.

-

2

WAKEUP2_SETEN

Writing a 1 to this bit sets the event enable bit 2 in the
ENABLE register.

-

3

WAKEUP3_SETEN

Writing a 1 to this bit sets the event enable bit 3 in the
ENABLE register.

-

4

ATIMER_SETEN

Writing a 1 to this bit sets the event enable bit 4 in the
ENABLE register.

-

5

RTC_SETEN

Writing a 1 to this bit sets the event enable bit 5 in the
ENABLE register.

-

6

BOD_SETEN

Writing a 1 to this bit sets the event enable bit 6 in the
ENABLE register.

-

7

WWDT_SETEN

Writing a 1 to this bit sets the event enable bit 7 in the
ENABLE register.

-

8

ETH_SETEN

Writing a 1 to this bit sets the event enable bit 8 in the
ENABLE register.

-

9

USB0_SETEN

Writing a 1 to this bit sets the event enable bit 9 in the
ENABLE register.

-

10

USB1_SETEN

Writing a 1 to this bit sets the event enable bit 10 in the
ENABLE register.

-

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Chapter 10: LPC43xx/LPC43Sxx Event router

Table 89.

UM10503

User manual

Event set enable register (SET_EN, address 0x4004 4FDC) bit description

Bit

Symbol

Description

Reset
value

11

SDMMC_SETEN

Writing a 1 to this bit sets the event enable bit 11 in the
ENABLE register.

-

12

CAN_SETEN

Writing a 1 to this bit sets the event enable bit 12 in the
ENABLE register.

-

13

TIM2_SETEN

Writing a 1 to this bit sets the event enable bit 13 in the
ENABLE register.

-

14

TIM6_SETEN

Writing a 1 to this bit sets the event enable bit 14 in the
ENABLE register.

-

15

QEI_SETEN

Writing a 1 to this bit sets the event enable bit 15 in the
ENABLE register.

-

16

TIM14_SETEN

Writing a 1 to this bit sets the event enable bit 16 in the
ENABLE register.

-

18:17

-

Reserved.

-

19

RESET_SETEN

Writing a 1 to this bit sets the event enable bit 19 in the
ENABLE register.

-

20

BODRESET_SETEN Writing a 1 to this bit sets the event enable bit 20 in the
ENABLE register.

-

21

DPDRESET_SETEN Writing a 1 to this bit sets the event enable bit 21 in the
ENABLE register.

-

31:22

-

-

Reserved.

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Chapter 10: LPC43xx/LPC43Sxx Event router

10.6.5 Event status register
The STATUS register monitors the internally generated interrupt or event signal from the
peripherals. The contents of this register can be read at any time. To change the contents
of this register, use the CLR_STAT and SET_STAT registers.
Remark: The reset value for this register indicates the POR reset value.
Table 90.

Event status register (STATUS, address 0x4004 4FE0) bit description

Bit

Symbol

Description

Reset
value

0

WAKEUP0_ST

A 1 in this bit shows that the WAKEUP0 event has been
raised.

1

1

WAKEUP1_ST

A 1 in this bit shows that the WAKEUP1 event has been
raised.

1

2

WAKEUP2_ST

A 1 in this bit shows that the WAKEUP2 event has been
raised.

1

3

WAKEUP3_ST

A 1 in this bit shows that the WAKEUP3 event has been
raised.

1

4

ATIMER_ST

A 1 in this bit shows that the ATIMER event has been raised. 1

5

RTC_ST

A 1 in this bit shows that the RTC event has been raised.

1

6

BOD_ST

A 1 in this bit shows that the BOD event has been raised.

1

7

WWDT_ST

A 1 in this bit shows that the WWDT event has been raised.

1

8

ETH_ST

A 1 in this bit shows that the ETHERNET event has been
raised.

1

9

USB0_ST

A 1 in this bit shows that the USB0 event has been raised.

1

10

USB1_ST

A 1 in this bit shows that the USB1 event has been raised.

1

11

SDMMC_ST

A 1 in this bit indicates that the SDMMC event has been
raised.

1

12

CAN_ST

A 1 in this bit shows that the C_CAN event has been raised.

1

13

TIM2_ST

A 1 in this bit shows that the combined timer 2 output event
has been raised.

1

14

TIM6_ST

A 1 in this bit shows that the combined timer 6 output event
has been raised.

1

15

QEI_ST

A 1 in this bit shows that the QEI event has been raised.

1

16

TIM14_ST

A 1 in this bit shows that the combined timer 14 output event 1
has been raised.

18:17

-

Reserved.

-

19

RESET_ST

A 1 in this bit shows that the reset event has been raised.

1

20

BODRESET_ST

A 1 in this bit indicates that the reset event has been raised.

1

21

DPDRESET_ST

A 1 in this bit indicates that the reset event has been raised.

1

31:22

-

Reserved.

-

10.6.6 Event enable register
The ENABLE register enables or disables the propagation of the interrupt or events which
are recorded in the STATUS register to the event router interrupt. The ENABLE register
does not prevent an interrupt or event from being recorded in the STATUS register.

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Chapter 10: LPC43xx/LPC43Sxx Event router

The ENABLE register can be read at any time. To change the contents of this register, use
the CLR_EN and SET_EN registers.
Table 91.

UM10503

User manual

Event enable register (ENABLE, address 0x4004 4FE4) bit description

Bit

Symbol

Description

0

WAKEUP0_EN A 1 in this bit shows that the WAKEUP0 event has been
enabled. This event wakes up the chip and contributes to the
event router interrupt when bit 0 = 1 in the STATUS register.

0

1

WAKEUP1_EN A 1 in this bit shows that the WAKEUP1 event has been
enabled. This event wakes up the chip and contributes to the
event router interrupt when bit 0 = 1 in the STATUS register.

0

2

WAKEUP2_EN A 1 in this bit shows that the WAKEUP2 event has been
enabled. This event wakes up the chip and contributes to the
event router interrupt when bit 0 = 1 in the STATUS register.

0

3

WAKEUP3_EN A 1 in this bit shows that the WAKEUP3 event has been
enabled. This event wakes up the chip and contributes to the
event router interrupt when bit 0 = 1 in the STATUS register.

0

4

ATIMER_EN

A 1 in this bit shows that the ATIMER event has been enabled. 0
This event wakes up the chip and contributes to the event
router interrupt when bit 0 = 1 in the STATUS register.

5

RTC_EN

A 1 in this bit shows that the RTC event has been enabled.
This event wakes up the chip and contributes to the event
router interrupt when bit 0 = 1 in the STATUS register.

0

6

BOD_EN

A 1 in this bit shows that the BOD event has been enabled.
This event wakes up the chip and contributes to the event
router interrupt when bit 0 = 1 in the STATUS register.

0

7

WWDT_EN

A 1 in this bit shows that the WWDT event has been enabled.
This event wakes up the chip and contributes to the event
router interrupt when bit 0 = 1 in the STATUS register.

0

8

ETH_EN

A 1 in this bit shows that the ETHERNET event has been
enabled. This event wakes up the chip and contributes to the
event router interrupt when bit 0 = 1 in the STATUS register.

0

9

USB0_EN

A 1 in this bit shows that the USB0 event has been enabled.
This event wakes up the chip and contributes to the event
router interrupt when bit 0 = 1 in the STATUS register.

0

10

USB1_EN

A 1 in this bit shows that the USB1 event has been enabled.
This event wakes up the chip and contributes to the event
router interrupt when bit 0 = 1 in the STATUS register.

0

11

SDMMC_EN

A 1 in this bit indicates that the SDMMC event has been
enabled. This event wakes up the chip and contributes to the
event router interrupt when bit 0 = 1 in the STATUS register.

0

12

CAN_EN

A 1 in this bit shows that the CAN event has been enabled.
This event wakes up the chip and contributes to the event
router interrupt when bit 0 = 1 in the STATUS register.

0

13

TIM2_EN

A 1 in this bit shows that the TIM2 event has been enabled.
This event wakes up the chip and contributes to the event
router interrupt when bit 0 = 1 in the STATUS register.

0

14

TIM6_EN

A 1 in this bit shows that the TIM6 event has been enabled.
This event wakes up the chip and contributes to the event
router interrupt when bit 0 = 1 in the STATUS register.

0

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Reset
value

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Chapter 10: LPC43xx/LPC43Sxx Event router

Table 91.

Event enable register (ENABLE, address 0x4004 4FE4) bit description

Bit

Symbol

Description

Reset
value

15

QEI_EN

A 1 in this bit shows that the QEI event has been enabled. This 0
event wakes up the chip and contributes to the event router
interrupt when bit 0 = 1 in the STATUS register.

16

TIM14_EN

A 1 in this bit shows that the TIM14 event has been enabled.
This event wakes up the chip and contributes to the event
router interrupt when bit 0 = 1 in the STATUS register.

0

18:17

-

Reserved

-

19

RESET_EN

A 1 in this bit shows that the RESET event has been enabled. 0
This event wakes up the chip and contributes to the event
router interrupt when bit 0 = 1 in the STATUS register.

20

BODRESET_E A 1 in this bit indicates that the BOD RESET event has been
N
enabled. This event wakes up the chip and contributes to the
event router interrupt when bit 0 = 1 in the STATUS register.

0

21

DPDRESET_E A 1 in this bit indicates that the deep power-down RESET
N
event has been enabled. This event wakes up the chip and
contributes to the event router interrupt when bit 0 = 1 in the
STATUS register.

0

31:22

-

-

Reserved.

10.6.7 Clear event status register
The CLR_STAT register clears the corresponding bit in the STATUS register.
Table 92.

UM10503

User manual

Clear event status register (CLR_STAT, address 0x4004 4FE8) bit description

Bit

Symbol

Description

Reset
value

0

WAKEUP0_CLRST

Writing a 1 to this bit clears the STATUS event bit 0 in
the STATUS register.

-

1

WAKEUP1_CLRST

Writing a 1 to this bit clears the STATUS event bit 1 in
the STATUS register.

-

2

WAKEUP2_CLRST

Writing a 1 to this bit clears the STATUS event bit 2 in
the STATUS register.

-

3

WAKEUP3_CLRST

Writing a 1 to this bit clears the STATUS event bit 3 in
the STATUS register.

-

4

ATIMER_CLRST

Writing a 1 to this bit clears the STATUS event bit 4 in
the STATUS register.

-

5

RTC_CLRST

Writing a 1 to this bit clears the STATUS event bit 5 in
the STATUS register.

-

6

BOD_CLRST

Writing a 1 to this bit clears the STATUS event bit 6 in
the STATUS register.

-

7

WWDT_CLRST

Writing a 1 to this bit clears the STATUS event bit 7 in
the STATUS register.

-

8

ETH_CLRST

Writing a 1 to this bit clears the STATUS event bit 8 in
the STATUS register.

-

9

USB0_CLRST

Writing a 1 to this bit clears the STATUS event bit 9 in
the STATUS register.

-

10

USB1_CLRST

Writing a 1 to this bit clears the STATUS event bit 10 in
the STATUS register.

-

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Chapter 10: LPC43xx/LPC43Sxx Event router

Table 92.

Clear event status register (CLR_STAT, address 0x4004 4FE8) bit description

Bit

Symbol

Description

Reset
value

11

SDMMC_CLRST

Writing a 1 to this bit clears the STATUS event bit 11 in
the STATUS register.

-

12

CAN_CLRST

Writing a 1 to this bit clears the STATUS event bit 12 in
the STATUS register.

-

13

TIM2_CLRST

Writing a 1 to this bit clears the STATUS event bit 13 in
the STATUS register.

-

14

TIM6_CLRST

Writing a 1 to this bit clears the STATUS event bit 14 in
the STATUS register.

-

15

QEI_CLRST

Writing a 1 to this bit clears the STATUS event bit 15 in
the STATUS register.

-

16

TIM14_CLRST

Writing a 1 to this bit clears the STATUS event bit 16 in
the STATUS register.

-

18:17

-

Reserved.

-

19

RESET_CLRST

Writing a 1 to this bit clears the STATUS event bit 19 in
the STATUS register.

-

20

BODRESET_CLRST Writing a 1 to this bit clears the STATUS event bit 20 in
the STATUS register.

-

21

DPDRESET_CLRST Writing a 1 to this bit clears the STATUS event bit 21 in
the STATUS register.

-

31:22

-

-

Reserved.

10.6.8 Set event status register
The SET_STAT register sets the corresponding bit in the STATUS register.
Table 93.

UM10503

User manual

Set event status register (SET_STAT, address 0x4004 4FEC) bit description

Bit

Symbol

Description

Reset
value

0

WAKEUP0_SETST

Writing a 1 to this bit sets the STATUS event bit 0 in the
STATUS register.

-

1

WAKEUP1_SETST

Writing a 1 to this bit sets the STATUS event bit 1 in the
STATUS register.

-

2

WAKEUP2_SETST

Writing a 1 to this bit sets the STATUS event bit 2 in the
STATUS register.

-

3

WAKEUP3_SETST

Writing a 1 to this bit sets the STATUS event bit 3 in the
STATUS register.

-

4

ATIMER_SETST

Writing a 1 to this bit sets the STATUS event bit 4 in the
STATUS register.

-

5

RTC_SETST

Writing a 1 to this bit sets the STATUS event bit 5 in the
STATUS register.

-

6

BOD_SETST

Writing a 1 to this bit sets the STATUS event bit 6 in the
STATUS register.

-

7

WWDT_SETST

Writing a 1 to this bit sets the STATUS event bit 7 in the
STATUS register.

-

8

ETH_SETST

Writing a 1 to this bit sets the STATUS event bit 8 in the
STATUS register.

-

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Chapter 10: LPC43xx/LPC43Sxx Event router

Table 93.

UM10503

User manual

Set event status register (SET_STAT, address 0x4004 4FEC) bit description

Bit

Symbol

Description

Reset
value

9

USB0_SETST

Writing a 1 to this bit sets the STATUS event bit 9 in the
STATUS register.

-

10

USB1_SETST

Writing a 1 to this bit sets the STATUS event bit 10 in the STATUS register.

11

SDMMC_SETST

Writing a 1 to this bit sets the STATUS event bit 11 in the STATUS register.

12

CAN_SETST

Writing a 1 to this bit sets the STATUS event bit 12 in the STATUS register.

13

TIM2_SETST

Writing a 1 to this bit sets the STATUS event bit 13 in the STATUS register.

14

TIM6_SETST

Writing a 1 to this bit sets the STATUS event bit 14 in the STATUS register.

15

QEI_SETST

Writing a 1 to this bit sets the STATUS event bit 15 in the STATUS register.

16

TIM14_SETST

Writing a 1 to this bit sets the STATUS event bit 16 in the STATUS register.

18:17

-

Reserved.

19

RESET_SETST

Writing a 1 to this bit sets the STATUS event bit 19 in the STATUS register.

20

BODRESET_SETST Writing a 1 to this bit sets the STATUS event bit 20 in the STATUS register.

21

DPDRESET_SETST

Writing a 1 to this bit sets the STATUS event bit 21 in the STATUS register.

31:22

-

Reserved.

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-

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Chapter 11: LPC43xx/LPC43Sxx Configuration Registers
(CREG)
Rev. 2.4 — 22 August 2018

User manual

11.1 How to read this chapter
The available peripherals vary for different parts.

• Ethernet: available only on LPC436x/5x/3x, LPC43S6x/S5x/S3x, and
LPC4370/LPC43S70.

• USB0: available only on LPC436x/5x/3x, LPC43S6x/S5x/S3x, and
LPC4370/LPC43S70.

• USB1: available only on LPC436x/5x/3x, LPC43S6x/S5x/S3x, and
LPC4370/LPC43S70.

• AES: available only secure parts.
If a peripheral is not available, the corresponding bits in the CREG registers are reserved.
The following registers or register bits are implemented only on parts with on-chip flash:

•
•
•
•
•

USB0FLADJ register
USB1FLADJ register
FALSHCFGA register
FLASHCFGB register
SAMPLECTRL bit in the CREG0 register

The ARM Cortex-M0APP processor is available on all LPC43xx/LPC43Sxx parts.
The ARM Cortex-M0SUB subsystem core is only available on parts LPC4370/LPC43S70
and LPC436x/LPC43S6x.

11.2 Basic configuration
The CREG block is configured as follows:

• See Table 94 for clocking and power control.
• The CREG block cannot be reset by software.
Table 94.
CREG

UM10503

User manual

CREG clocking and power control
Base clock

Branch clock

Operating frequency

BASE_M4_CLK

CLK_M4_CREG

up to 204 MHz

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Chapter 11: LPC43xx/LPC43Sxx Configuration Registers (CREG)

11.3 Features
The following settings are controlled in the configuration register block:

•
•
•
•
•
•
•
•
•
•
•

ETB SRAM configuration
BOD trip settings
RTC Oscillator output
DMA-to-peripheral muxing
Ethernet mode
Memory mapping
Timer/UART inputs
USB PHY control
RTC_ALARM and WAKEUP0/1 pin functions
Event control for interrupts from the M0APP and M0SUB cores
On parts with on-chip flash:
– Flash wait states and power control for flash banks A and B
– USB frame length adjust registers

In addition, the CREG block contains the part id and the part configuration information.

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Chapter 11: LPC43xx/LPC43Sxx Configuration Registers (CREG)

11.4 Register description
Table 95.

Register overview: Configuration registers (base address 0x4004 3000)

Name

Access

Address Description
offset

Reset
value

Reset
value after
EMC,
UART0/3
boot

Reset
value
after
USB0/1
boot

Reference

-

-

0x000

Reserved

-

-

-

-

CREG0

R/W

0x004

Chip configuration register
32 kHz oscillator output and
BOD control register.

-

0xF3C

0xF1C

Table 96

CREG1

R/W

0x008

Chip Configuration register 1. Controls wake-up using USB in
deep-sleep mode.

0x3030DB

0x3030DB Table 97

-

-

0x00C 0x0FC

Reserved

-

-

-

-

M4MEMMAP

R/W

0x100

ARM Cortex-M4 memory
mapping

0x1040
0000

0x1000
0000

0x1000
0000

Table 98

-

-

0x104 0x114

Reserved

-

-

-

-

CREG5

R/W

0x118

Chip configuration register 5.
Controls JTAG access.

-

0x4000
0260

-

Table 99

DMAMUX

R/W

0x11C

DMA mux control

-

-

-

Table 100

FLASHCFGA

R/W

0x120

Flash accelerator configuration 0x8000
register for flash bank A
F03A

-

-

Table 101

FLASHCFGB

R/W

0x124

Flash accelerator configuration 0x8000
register for flash bank B
F03A

-

-

Table 102

ETBCFG

R/W

0x128

ETB RAM configuration

0x1

0x1

0x1

Table 103

CREG6

R/W

0x12C

Chip configuration register 6.
Controls multiple functions :
Ethernet interface,
SCTimer/PWM output, I2S0/1
inputs, EMC clock.

0

-

-

Table 104

M4TXEVENT

R/W

0x130

Cortex-M4 TXEV event clear

0

-

-

Table 105

-

-

0x134 0x1FC

Reserved

-

-

-

-

CHIPID

RO

0x200

Chip ID

-

-

-

Table 106

-

-

0x200 0x304

Reserved

-

-

-

-

M0SUBMEMMAP

R/W

0x308

ARM Cortex-M0SUB memory
mapping

0x184000 00

-

Table 107

-

-

0x310

Reserved

-

-

-

-

M0SUBTXEVENT R/W

0x314

Cortex-M0SUB TXEV event
clear

0

-

-

Table 108

-

-

0x318 0x3FC

Reserved

-

-

-

-

M0APPTXEVENT

R/W

0x400

Cortex-M0APP TXEV event
clear

0

-

-

Table 109

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Chapter 11: LPC43xx/LPC43Sxx Configuration Registers (CREG)

Table 95.

Register overview: Configuration registers (base address 0x4004 3000)

Name

Access

Address Description
offset

Reset
value

Reset
value after
EMC,
UART0/3
boot

Reset
value
after
USB0/1
boot

Reference

M0APPMEMMAP

R/W

0x404

ARM Cortex-M0APP memory
mapping

0x2000
0000

-

-

Table 110

USB0FLADJ

R/W

0x500

USB0 frame length adjust
register

0x20

-

-

Table 111

USB1FLADJ

R/W

0x600

USB1 frame length adjust
register

0x20

-

-

Table 112

11.4.1 CREG0 control register
Table 96.

CREG0 register (CREG0, address 0x4004 3004) bit description

Bit

Symbol

0

EN1KHZ

1

2

3

Value

Description

Reset
value

Access

Enable 1 kHz output.

0

R/W

0

R/W

1

R/W

1

R/W

0

1 kHz output disabled.

1

1 kHz output enabled.

0

32 kHz output disabled.

1

32 kHz output enabled.

EN32KHZ

Enable 32 kHz output

RESET32KHZ

32 kHz oscillator reset
0

Clear reset.

1

Reset active.

PD32KHZ

32 kHz power control.
0

Powered.

1

Powered-down.

4

-

Reserved

-

-

5

USB0PHY

USB0 PHY power control.

1

R/W

0

R/W

0x3

R/W

7:6

9:8

0

Enable USB0 PHY power.

1

Disable USB0 PHY. PHY powered down.

ALARMCTRL

RTC_ALARM pin output control
0x0

RTC alarm.

0x1

Event router event.

0x2

Reserved.

0x3

Inactive.

BODLVL1

UM10503

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BOD trip level to generate an interrupt. See the
LPC43xx data sheets for the trip values.
0x0

Level 0 interrupt

0x1

Level 1 interrupt

0x2

Level 2 interrupt

0x3

Level 3 interrupt

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Chapter 11: LPC43xx/LPC43Sxx Configuration Registers (CREG)

Table 96.

CREG0 register (CREG0, address 0x4004 3004) bit description …continued

Bit

Symbol

11:10

BODLVL2

Value

15:14

31:18

R/W

0

R/W

0

R/W

0

R/W

-

-

0x2

Level 2 reset
Level 3 reset
SAMPLE pin input/output control

0x0

Reserved

0x1

Sample output from the event monitor/recorder.

0x2

Output from the event router.

0x3

Reserved.
WAKEUP0 pin input/output control
Input to the event router.

0x1

Output from the event router.

0x2

Reserved.

0x3

Input to the event router.

WAKEUP1CTRL

User manual

0x3

Level 1 reset

WAKEUP0CTRL

UM10503

BOD trip level to generate a reset. See the
LPC43xx data sheets for the trip values.
0x1

SAMPLECTRL

-

Access

Level 0 reset

0x0

17:16

Reset
value

0x0

0x3
13:12

Description

WAKEUP1 pin input/output control
0x0

Input to event router.

0x1

Output from the event router.

0x2

Reserved

0x3

Input to event router.
Reserved

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Chapter 11: LPC43xx/LPC43Sxx Configuration Registers (CREG)

11.4.2 CREG1 control register
Table 97.

CREG1 register (CREG1, address 0x4004 3008) bit description

Bit

Symbol

Value

Description

Reset
value

Access

8:0

-

-

Reserved

-

-

9

USB0_PHY_PWREN_LP

USB0 PHY power control in low power mode. Set
this bit to enable the power to USB0 PHY in low
power mode. This enables wake-up using USB0
peripheral in deep-sleep mode.

0

R/W

0

R/W

-

-

10

0

USB0 PHY power disabled in low power mode.

1

USB0 PHY power enabled in low power mode.

USB1_PHY_PWREN_LP

USB1 PHY power control in low power mode. Set
this bit to enable the power to USB1 PHY in low
power mode. This enables wake-up using USB1
peripheral in deep-sleep mode.
0

31:11

-

USB1 PHY power disabled in low power mode.

1

USB1 PHY power enabled in low power mode.

-

Reserved

Remark: The wake-up from deep-sleep using USB0 and USB1 is supported only in flash
based devices and is not supported in flashless devices.

11.4.3 ARM Cortex-M4 memory mapping register
The reset value for this register depends on the execution of the boot loader. See
Table 95. All memory mapped addresses must be located on a 4 kB boundary.
Table 98.
Bit

Memory mapping register (M4MEMMAP, address 0x4004 3100) bit description

Symbol

Description

Reset
value

Access

Reserved

0x000

-

M4MAP

Shadow address when accessing memory at address 0x0000 0000

11:0
31:12

R/W

11.4.4 CREG5 control register
Use this register to disable the JTAG for the M4 main core and the M0 co-processors. By
default the JTAG access is enabled unless an AES key is programmed and the device is a
secure device.
Remark: Disabling the JTAG can only be reversed by resetting the part through any
available reset.

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Table 99.

CREG5 control register (CREG5, address 0x4004 3118) bit description

Bit

Symbol

9:0
10

11

12

31:13

Value

Description

Reset Access
value

-

Reserved.

-

-

M0SUBTAPSEL

JTAG debug disable for M0SUB
co-processor. If this bit is set to 1, it can
be changed to 0 only through a chip
reset.

0

R/W

0

R/W

JTAG debug disable for
0
M0APPco-processor. If this bit is set to 1,
it can be changed to 0 only through a chip
reset.

R/W

0

No effect.

1

Disable JTAG debug. Once JTAG is
disabled, JTAG access remains disabled
until the chip is reset by any source.

M4TAPSEL

JTAG debug disable for M4 main
processor. If this bit is set to 1, it can be
changed to 0 only through a chip reset.
0

No effect.

1

Disable JTAG debug. Once JTAG is
disabled, JTAG access remains disabled
until the chip is reset by any source.

M0APPTAPSEL

0

No effect.

1

Disable JTAG debug. Once JTAG is
disabled, JTAG access remains disabled
until the chip is reset by any source.

-

Reserved.

-

-

11.4.5 DMA mux control register
This register controls which set of peripherals is connected to the DMA controller (see
Table 330).
Remark: On secure parts, the AES DMA API configures the DMA connections in this
register. See Table 75 “AES API calls”.
Table 100. DMA mux control register (DMAMUX, address 0x4004 311C) bit description

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Bit

Symbol

Value

1:0

DMAMUXPER0

Description

Reset Access
value

Select DMA to peripheral connection for
DMA peripheral 0.

0

0x0

SPIFI

0x1

SCT CTOUT_2

0x2

SGPIO14

0x3

Timer3 match 1

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Table 100. DMA mux control register (DMAMUX, address 0x4004 311C) bit description
Bit

Symbol

Value

3:2

DMAMUXPER1

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R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

Reserved

DMAMUXPER2

AES in
Select DMA to peripheral connection for
DMA peripheral 2.
Timer0 match 1

0x1

USART0 receive

0x2

Reserved

0x3

AES out

DMAMUXPER3

Select DMA to peripheral connection for
DMA peripheral 3.
0x0

Timer1 match 0

0x1

UART1 transmit

0x2

I2S1 DMA request 1

DMAMUXPER4

SSP1 transmit
Select DMA to peripheral connection for
DMA peripheral 4.
Timer1 match 1

0x1

UART1 receive

0x2

I2S1 DMA request 2

0x3

SSP1 receive

DMAMUXPER5

Select DMA to peripheral connection for
DMA peripheral 5.
0x0

Timer2 match 0

0x1

USART2 transmit

0x2

SSP1 transmit

DMAMUXPER6

SGPIO15
Selects DMA to peripheral connection for
DMA peripheral 6.

0x0

15:14

0

0x2

0x3
13:12

R/W

USART0 transmit

0x0

11:10

0

0x1

0x3
9:8

Select DMA to peripheral connection for
DMA peripheral 1
Timer0 match 0

0x0

7:6

Reset Access
value

0x0

0x3
5:4

Description

Timer2 match 1

0x1

USART2 receive

0x2

SSP1 receive

0x3

SGPIO14

DMAMUXPER7

Selects DMA to peripheral connection for
DMA peripheral 7.
0x0

Timer3 match 0

0x1

USART3 transmit

0x2

SCTimer/PWM DMA request 0

0x3

ADCHS write

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Table 100. DMA mux control register (DMAMUX, address 0x4004 311C) bit description
Bit

Symbol

Value

17:16

DMAMUXPER8

21:20

25:24

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R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

USART3 receive

0x2

SCTimer/PWM DMA request 1

DMAMUXPER9

ADCHS read
Select DMA to peripheral connection for
DMA peripheral 9.

0x0

SSP0 receive

0x1

I2S0 DMA request 1

0x2

SCTimer/PWM DMA request 1

0x3

Reserved

DMAMUXPER10

Select DMA to peripheral connection for
DMA peripheral 10.
0x0

SSP0 transmit

0x1

I2S0 DMA request 2

0x2

SCTimer/PWM DMA request 0

DMAMUXPER11

Reserved
Selects DMA to peripheral connection for
DMA peripheral 11.

0x0

SSP1 receive

0x1

SGPIO14

0x2

USART0 transmit

0x3

Reserved

DMAMUXPER12

Select DMA to peripheral connection for
DMA peripheral 12.
0x0

SSP1 transmit

0x1

SGPIO15

0x2

USART0 receive

DMAMUXPER13

Reserved
Select DMA to peripheral connection for
DMA peripheral 13.

0x0

29:28

0

0x1

0x3
27:26

Select DMA to peripheral connection for
DMA peripheral 8.
Timer3 match 1

0x3
23:22

Reset Access
value

0x0

0x3
19:18

Description

ADC0

0x1

AES in

0x2

SSP1 receive

0x3

USART3 receive

DMAMUXPER14

Select DMA to peripheral connection for
DMA peripheral 14.
0x0

ADC1

0x1

AES out

0x2

SSP1 transmit

0x3

USART3 transmit

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Table 100. DMA mux control register (DMAMUX, address 0x4004 311C) bit description
Bit

Symbol

Value

31:30

DMAMUXPER15

Description

Reset Access
value

Select DMA to peripheral connection for
DMA peripheral 15.

0

0x0

DAC

0x1

SCT CTOUT_3

0x2

SGPIO15

0x3

Timer3 match 0

R/W

11.4.6 Flash Accelerator Configuration register for flash bank A
Remark: This register is implemented on parts with on-chip flash only. See Section 11.1.
Following reset, flash accelerator functions are enabled and flash access timing is set to a
default value of 16 clocks.
Changing the FLASHCFG register value causes the flash accelerator to invalidate all of
the holding latches, resulting in new reads of flash information as required. This
guarantees synchronization of the flash accelerator to CPU operation.
Remark: Bits 11 to 0 of the FLASHCFG register control internal flash accelerator
functions and should not be altered.

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Table 101. Flash Accelerator Configuration for flash bank A register (FLASHCFGA, address 0x4004 3120) bit
description
Bit

Symbol

11:0

-

Value Description
-

15:12 FLASHTIM

Reset
value

Reserved. Do not change these bits from the reset value.

0x3A

Flash access time. The value of this field plus 1 gives the number of BASE_M4_CLK 0xF
clocks used for a flash access.
Warning: Improper setting of this value may result in incorrect operation of the
device.
All other values are allowed but may not be optimal for the supported clock
frequencies.
0x0

1 BASE_M4_CLK clock. Use for BASE_M4_CLK up to 21 MHz.

0x1

2 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 43 MHz.

0x2

3 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 64 MHz.

0x3

4 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 86 MHz.

0x4

5 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 107 MHz.

0x5

6 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 129 MHz.

0x6

7 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 150 MHz.

0x7

8 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 172 MHz.

0x8

9 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 193 MHz.

0x9

10 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 204 MHz. Safe setting for
all allowed conditions.

30:16 -

Reserved. Write zeros only to these bits.

0

31

Flash bank A power control

1

POW
0

Power-down

1

Active (Default)

11.4.7 Flash Accelerator Configuration register for flash bank B
Remark: This register is implemented on parts with on-chip flash only. See Section 11.1.
Following reset, flash accelerator functions are enabled and flash access timing is set to a
default value of 16 clocks.
Changing the FLASHCFG register value causes the flash accelerator to invalidate all of
the holding latches, resulting in new reads of flash information as required. This
guarantees synchronization of the flash accelerator to CPU operation.
Remark: Bits 11 to 0 of the FLASHCFG register control internal flash accelerator
functions and should not be altered.

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Chapter 11: LPC43xx/LPC43Sxx Configuration Registers (CREG)

Table 102. Flash Accelerator Configuration for flash bank B register (FLASHCFGB, address 0x4004 3124) bit
description
Bit

Symbol

11:0

-

Value Description
-

15:12 FLASHTIM

Reset value

Reserved. Do not change these bits from the reset value.

0x3A

Flash access time. The value of this field plus 1 gives the number of
BASE_M4_CLK clocks used for a flash access.

0xF

Warning: Improper setting of this value may result in incorrect operation of the
device.
All other values are allowed but may not be optimal for the supported clock
frequencies.
0x0

1 BASE_M4_CLK clock. Use for BASE_M4_CLK up to 21 MHz.

0x1

2 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 43 MHz.

0x2

3 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 64 MHz.

0x3

4 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 86 MHz.

0x4

5 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 107 MHz.

0x5

6 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 129 MHz.

0x6

7 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 150 MHz.

0x7

8 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 172 MHz.

0x8

9 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 193 MHz.

0x9

10 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 204 MHz. Safe setting
for all allowed conditions.

30:16 -

Reserved. Write zeros only to these bits.

0

31

Flash bank A power control

1

POW
0

Power-down

1

Active (Default)

11.4.8 ETB SRAM configuration register
This register selects how the 16 kB block of RAM located at address 0x2000 C000 is
used. This RAM memory block can be accessed either by the ETB or be used as normal
SRAM on the AHB bus.
Table 103. ETB SRAM configuration register (ETBCFG, address 0x4004 3128) bit description
Bit

Symbol

0

ETB

31:1

-

Value Description
Select SRAM interface
0

ETB accesses SRAM at address 0x2000 C000.

1

AHB accesses SRAM at address 0x2000 C000.
Reserved.

Reset
value

Access

1

R/W

-

-

11.4.9 CREG6 control register
This register controls various aspects of the LPC43xx:

• Bits 2:0 control the Ethernet PHY interface. The ethernet block reads this register
during set-up. Therefore the ethernet must be reset after changing the PHY interface.
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• Bit 4 selects the functionality of the SCT outputs connected to the CTOUT_n pins and
selected GIMA inputs:
– SCTimer/PWM output Red with timer match output (default).
– SCTimer/PWM output only.

• Bits 15:12 control the I2S clock connections. See also Table 1012 and Table 1013.
• Bit 16 controls the external memory controller clocking. See Section 23.2.
Table 104. CREG6 control register (CREG6, address 0x4004 312C) bit description
Bit

Symbol

2:0

ETHMODE

Value Description

Reset Access
value

Selects the Ethernet mode. Reset the ethernet after changing
the PHY interface.

R/W

All other settings are reserved.
0x0

MII

0x4

RMII

3

-

Reserved.

4

CTOUTCTRL

Selects the functionality of the SCTimer/PWM outputs.

11:5

-

12

I2S0_TX_SCK_IN_SEL

13

14

15

16

31:17

Reserved.

-

-

I2S0_TX_SCK input select

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

-

-

1

SCTimer/PWM outputs only. SCTimer/PWM outputs are used
without timer match outputs.

0

I2S Register. I2S clock selected as defined by the I2S
transmit mode register.

1

BASE_AUDIO_CLK for I2S transmit clock MCLK input and
MCLK output. The I2S must be configured in slave mode.
I2S0_RX_SCK input select

0

I2S Register. I2S clock selected as defined by the I2S receive
mode register.

1

BASE_AUDIO_CLK for I2S receive clock MCLK input and
MCLK output. The I2S must be configured in slave mode.
I2S1_TX_SCK input select

0

I2S register. I2S clock selected as defined by the I2S transmit
mode register.

1

BASE_AUDIO_CLK for I2S transmit clock MCLK input and
MCLK output. The I2S must be configured in slave mode.

I2S1_RX_SCK_IN_SEL

I2S1_RX_SCK input select
0

I2S register. I2S clock selected as defined by the I2S receive
mode register.

1

BASE_AUDIO_CLK for I2S receive clock MCLK input and
MCLK output. The I2S must be configured in slave mode.

EMC_CLK_SEL

User manual

R/W

Combine SCT and timer match outputs. SCTimer/PWM
outputs are Red with timer outputs.

I2S1_TX_SCK_IN_SEL

UM10503

0

0

I2S0_RX_SCK_IN_SEL

-

R/W

EMC_CLK divided clock select.
0

Divide by 1. EMC_CLK_DIV not divided.

1

Divide by 2. EMC_CLK_DIV divided by 2.
Reserved.
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Chapter 11: LPC43xx/LPC43Sxx Configuration Registers (CREG)

11.4.10 Cortex-M4 TXEV event clear register
This register captures the signal TXEV from the ARM Cortex-M4 processor (see
Section 2.4.2).
Table 105. M4 TXEV clear register (M4TXEVENT, address 0x4004 3130) bit description
Bit

Symbol

0

TXEVCLR

31:1

Value Description
Cortex-M4 TXEV event.
0

Clear the TXEV event.

1

No effect.

-

Reserved.

Reset
value

Access

0

R/W

-

-

11.4.11 Chip ID register
Table 106. Chip ID register (CHIPID, address 0x4004 3200) bit description
Bit

Symbol

Description

Reset
value

Access

31:0

ID

Boundary scan ID code

-

R

0x5906 002B or 0x6906 002B = LPC4370/50/30/20/10
and LPC43S70/S50/S30/S20 (flashless parts)
0x4906 002B = LPC436x/5x/3x/2x/1x,
LPC43S6x/S5x/S3x (Rev ‘-’ parts with on-chip flash)
0x7906 002B = LPC436x/5x/3x/2x/1x,
LPC43S6x/S5x/S3x (Rev A parts with on-chip flash)

11.4.12 ARM Cortex-M0SUB memory mapping register
The reset value for this register depends on the execution of the boot loader. See
Table 95. All memory mapped addresses must be located on a 4 kB boundary.
Table 107. Memory mapping register (M0SUBMEMMAP, address 0x4004 3308) bit description
Bit

Symbol

Description

Reset
value

Access

Reserved

0

-

M0SUBMAP

Shadow address when accessing memory at
address 0x0000 0000

-

R/W

11:0
31:12

11.4.13 Cortex-M0SUB TXEV event clear register
This register captures the signal TXEV from the ARM Cortex-M0SUB processor (see
Section 2.4.2).
Table 108. Cortex-M0SUB TXEV clear register (M0SUBTXEVENT, address 0x4004 3314) bit
description
Bit

Symbol

0

TXEVCLR

31:1
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-

Value Description
Cortex-M0SUB TXEV event handling.
0

Clear the TXEV event.

1

No effect.
Reserved.

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Reset
value

Access

0

R/W

-

-

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Chapter 11: LPC43xx/LPC43Sxx Configuration Registers (CREG)

11.4.14 Cortex-M0APP TXEV event clear register
This register captures the signal TXEV from the ARM Cortex-M0APP processor (see
Section 2.4.2).
Table 109. Cortex-M0APP TXEV clear register (M0APPTXEVENT, address 0x4004 3400) bit
description
Bit

Symbol

0

TXEVCLR

31:1

Value Description

-

Cortex-M0APP TXEV event handling.
0

Clear the TXEV event.

1

No effect.
Reserved.

Reset
value

Access

0

R/W

-

-

11.4.15 ARM Cortex-M0APP memory mapping register
The reset value for this register depends on the execution of the boot loader. See
Table 95. All memory mapped addresses must be located on a 4 kB boundary.
Table 110. Memory mapping register (M0APPMEMMAP, address 0x4004 3404) bit description
Bit

Symbol

11:0
31:12

M0APPMAP

Description

Reset
value

Access

Reserved

0

-

Shadow address when accessing memory at
address 0x0000 0000

-

R/W

11.4.16 USB0 frame length adjust register
Remark: This register is only implemented for parts with on-chip flash. See Section 11.1.
The USB frame length adjust register is used to adjust any offset from the clock source
that generates the clock that drives the SOF counter. When a new value is written into
these six bits, the length of the frame is adjusted. Its initial programmed value is
system-dependent based on the accuracy of hardware USB clock. This register should
only be modified when the HCH bit in the USB STS register is one. Changing value of this
register while the host controller is operating yields undefined results.
This register should not be reprogrammed by USB system software unless the default
values are incorrect, or the system is restoring the register while returning from a
suspended state.
Remark: The FLADJ register must be read only after initializing the USB interface.
Reading this register before initialization of the USB causes the MCU to stall.
For details on using the SOF signal, see Section 25.7.7.1.

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Chapter 11: LPC43xx/LPC43Sxx Configuration Registers (CREG)

Table 111. USB0 frame length adjust register (USB0FLADJ, address 0x4004 3500) bit
description
Bit

Symbol

Description

Reset
value

Access

5:0

FLTV

Frame length timing value

0x20

R/W

-

-

The frame length is given in the number of high-speed bit
times in decimal format. Each decimal value change to this
register corresponds to 16 high-speed bit times. The SOF
cycle time (number of SOF counter clock periods to
generate a SOF micro-frame length) is equal to 59488 +
value in this field. The default value is decimal 32 (0x20),
which results in a SOF cycle time of 60000.
0x00 = 59488 (= 59488 + 0 x 16)
0x01 = 59504 (= 59488 + 1 x 16)
0x02 = 59520 (= 59488 + 2 x 16)
...
0x1F = 59984 (= 59488 + 31 x 16)
0x20 = 60000 (= 59488 + 32 x 16)
...
0x3E = 60480 (= 59488 + 62 x 16)
0x3F = 60496 (= 59488 + 63 x 16)
31:6

-

Reserved

11.4.17 USB1 frame length adjust register
Remark: This register is only implemented for parts with on-chip flash. See Section 11.1.
The USB frame length adjust register is used to adjust any offset from the clock source
that generates the clock that drives the SOF counter. When a new value is written into
these six bits, the length of the frame is adjusted. Its initial programmed value is
system-dependent based on the accuracy of hardware USB clock. This register should
only be modified when the HCH bit in the USB STS register is one. Changing value of this
register while the host controller is operating yields undefined results.
This register should not be reprogrammed by USB system software unless the default
values are incorrect, or the system is restoring the register while returning from a
suspended state.
Remark: The FLADJ register must be read only after initializing the USB interface.
Reading this register before initialization of the USB causes the MCU to stall.
For details on using the SOF signal, see Section 25.7.7.1.

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Chapter 11: LPC43xx/LPC43Sxx Configuration Registers (CREG)

Table 112. USB1 frame length adjust register (USB1FLADJ, address 0x4004 3600) bit
description
Bit

Symbol

Description

Reset
value

Access

5:0

FLTV

Frame length timing value

0x20

R/W

-

-

The frame length is given in the number of high-speed bit
times in decimal format. Each decimal value change to this
register corresponds to 16 high-speed bit times. The SOF
cycle time (number of SOF counter clock periods to
generate a SOF micro-frame length) is equal to 59488 +
value in this field. The default value is decimal 32 (0x20),
which results in a SOF cycle time of 60000.
0x00 = 59488 (= 59488 + 0 x 16)
0x01 = 59504 (= 59488 + 1 x 16)
0x02 = 59520 (= 59488 + 2 x 16)
...
0x1F = 59984 (= 59488 + 31 x 16)
0x20 = 60000 (= 59488 + 32 x 16)
...
0x3E = 60480 (= 59488 + 62 x 16)
0x3F = 60496 (= 59488 + 63 x 16)
31:6

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Reserved

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Chapter 12: LPC43xx/LPC43Sxx Power Management
Controller (PMC)
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User manual

12.1 How to read this chapter
The power management controller is identical on all LPC43xx/LPC43Sxx parts.
The ARM-Cortex M0 subsystem core (M0SUB) and the power-down mode with M0SUB
SRAM maintained are only available on parts LPC4370/LPC43S70 and
LPC436x/LPC43S6x.

12.2 General description
The PMC controls the power consumption of the part and configures the power state of
the cores, memories, and peripherals.
The LPC43xx/LPC43Sxx supports the following power modes in order from highest to
lowest power consumption:
1. Active mode (for each core independently)
2. Sleep mode (for each core independently)
3. System power-down modes (for all cores, peripherals, and memories):
a. Deep-sleep mode
b. Power-down mode
c. Deep power-down mode
Active and sleep modes only affect the core. Cores can be in active or sleep mode
independently of each other. Any core in active mode can enter sleep mode through a
simple WFI/WFE instruction independently of whether the other cores are in active mode
or in sleep mode.
System power-down modes are initiated by a core but affect the entire system of cores,
peripherals, and memories. Any core in active mode can put the chip into one of the three
system power-down modes, Deep-sleep, Power-down, and Deep power-down, provided
that the core is enabled to do so in the PD0_SLEEP0_HW_ENA register. By default, only
the M4 core is enabled to control the system power-down modes and can put the system
into deep-sleep, power-down, or deep power-down independently of the other cores. If all
cores are enabled, the system will only enter system power-down once each core has
received a WFI/WFE instruction (see Section 12.2.6).
Wake-up from sleep mode is caused by an interrupt or event in the core’s NVIC. Interrupts
are captured in the NVIC (Chapter 9) and events are captured in the Event router
(Chapter 10). Both cores can wake up from sleep mode independently of each other.
Wake-up from the system power-down modes, Deep-sleep, Power-down, and Deep
power-down, is caused by an event on the WAKEUP pins or an event from the RTC or
alarm timer.

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WAKEUP pins
RTC/Alarm timer alarm
M4 NVIC: event router IRQ

System
Deep-sleep
Power-down
M4: WFI/WFE, SLEEPDEEP = 1
PD0_SLEEP0_MODE = 0x0030 00AA or
0x0030 FCBA

M4 active (master)
PD0_SLEEP0_HW_ENA = 0x1

M4: WFI/WFE, SLEEPDEEP = 1
PD0_SLEEP0_MODE = 0x0030 FF7F

M0APP/M0SUB active
M0APP/M0SUB sleep
M0APP/M0SUB reset

M4 NVIC: IRQ

M0APP/M0SUB active
M0APP/M0SUB sleep
M0APP/M0SUB reset

System
Deep Power-down

WAKEUP pins
RTC/ALARM timer alarm

M4 sleep

M4:WFI/WFE,
SLEEPDEEP = 0

chip reset

M4 active (master)
PD0_SLEEP0_HW_ENA = 0x1
Default after boot
WAKEUP pins
RTC/alarm timer alarm

M0APP/M0SUB reset

chip reset
System
Deep Power-down

WAKEUP pins
RTC/alarm timer alarm

System
Deep-sleep
Power-down

M0 NVIC: event router IRQ

M0: WFI/WFE, SLEEPDEEP = 1
PD0_SLEEP0_MODE = 0x0030 00AA or
0x0030 FCBA

M0: WFI/WFE, SLEEPDEEP = 1
PD0_SLEEP0_MODE = 0x0030 FF7F
M0APP/M0SUB active (master)
PD0_SLEEP0_HW_ENA = 0x2

M0 NVIC: IRQ

M4 active
M4 sleep

M0: WFI/WFE,
SLEEPDEEP = 0

M0APP/M0SUB sleep
M4 active
M4 sleep

When the master core enters and wakes up from Sleep mode, the state of the other core remains unchanged.
When the master core enters and wakes up from deep-sleep or power-down mode, the other core returns to the state it was in
before deep-sleep or power-down mode.
To release the M0 reset, write a 0 to the M0APP_RST or the M0SUB_RST bit in the RESET_CTRL1/0 registers
(Table 172/Table 171).

Fig 34. Power mode transitions

Remark: Before selecting the Deep-sleep mode or Power-down mode, you must select
the IRC as the clock source for all output clocks through the CGU registers (see
Section 13.8.1) and power down all PLLs.

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12.2.1 Active mode
By default, the LPC43xx/LPC43Sxx is in Active mode, which means that every peripheral
can perform a functional operation at nominal operating conditions.

12.2.2 Sleep mode
In Sleep mode, the CPU clock is shut down to save power; the peripherals can still remain
active and fully functional. The Sleep mode is entered by a WFI or WFE instruction if the
SLEEPDEEP bit in the ARM Cortex-M4 system control register is set to 0. Independently
of the M4 core, each ARM Cortex-M0 core can enter its own sleep mode if the M0 core’s
SLEEPDEEP bit is set to 0 and software issues a WFI/WFE instruction to the M0 core.
The part can wake up from sleep mode through any enabled interrupt in the the core’s
NVIC or any enabled event in the event router if the event router interrupt is enabled in the
NVIC.

12.2.3 Deep-sleep mode
In Deep-sleep mode the CPU clock and peripheral clocks are shut down to save power;
logic states and SRAM memory are maintained. All analog blocks and the BOD control
circuit are powered down.
Remark: Before entering Deep-sleep mode, program the CGU as follows:

• Switch the clock source of all base clocks to the IRC.
• Put the PLLs in power-down mode.
Reprogramming the CGU avoids any undefined or unlocked PLL clocks at wake-up and
minimizes power consumption during Deep-sleep mode.
Any ARM Cortex core can put the part in Deep-sleep mode depending on which core is
enabled in the PD0_SLEEP0_HW_ENA register.
To enter Deep-sleep mode, follow these steps:
1. In the PD0_SLEEP0_HW_ENA register, enable Deep-sleep mode for the M4 core or the M0
cores.

2. In the PD0_SLEEP0_MODE register, write the Deep-sleep value 0x0030 00AA.
3. In the ARM Cortex core control register for the core or cores enabled in step 1, set the
SLEEPDEEP bit.
4. Issue a WFI or WFE instruction for the core or cores enabled in step 1.
The part can wake up from Deep-sleep mode only through a signal on any of the
WAKEUP pins or a signal from the alarm timer or RTC. Enable the wake-up signals in the
event router. See Section 10.4.
When the LPC43xx wakes up from Deep-sleep mode, the 12 MHz IRC is used as the
clock source for all base clocks.

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12.2.4 Power-down mode
In Power-down mode the CPU clock and peripheral clocks are shut down but logic states
are maintained. All SRAM memory except for the upper 8 kB of the local SRAM located at
0x1008 0000, all analog blocks, and the BOD control circuit are powered down.

• Switch the clock source of all base clocks to the IRC.
• Put the PLLs in power-down mode.
Remark: Before entering Power-down mode, program the CGU as follows:
Reprogramming the CGU avoids any undefined or unlocked PLL clocks at wake-up and
minimizes power consumption during Power-down mode.
To enter Power-down mode, follow these steps:
1. In the PD0_SLEEP0_HW_ENA register, enable Power-down mode for the M4 core or the M0
cores.

2. In the PD0_SLEEP0_MODE register, write the Power-down value 0x0030 FCBA.
3. In the ARM Cortex core control register for the core or cores enabled in step 1, set the
SLEEPDEEP bit.
4. Issue a WFI or WFE instruction for the core or cores enabled in step 1.
The part can wake up from Power-down mode through a signal on any of the WAKEUP
pins or a signal from the alarm timer or RTC. Enable the wake-up signals in the event
router. See Section 10.4.
When the LPC43xx wakes up from Power-down mode, the 12 MHz IRC is used as the
clock source for all base clocks.

12.2.5 Deep power-down
In Deep power-down mode the entire core logic is powered down and the logic state of the
entire system including the I/O pads is lost. Only the logic in the RTC power domain
remains active.
To enter Deep power-down mode, follow these steps:
1. In the PD0_SLEEP0_HW_ENA register, enable Power-down mode for the M4 core or the M0
cores or both.

2. In the PD0_SLEEP0_MODE register, write the Deep power-down value 0x0030 FF7F.
3. In the ARM Cortex core control register for the core or cores enabled in step 1, set the
SLEEPDEEP bit.
4. Issue a WFI or WFE instruction for the core or cores enabled in step 1.
When the LPC43xx wakes up from Deep power-down mode, the boot loader configures
the PLL1 as the clock source running at 96 MHz and attempts to boot in the same way as
after a reset or power-up.
The part can wake up from Deep power-down mode through a signal on any of the
WAKEUP pins or a signal from the alarm timer or RTC. See Section 10.4.

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12.2.6 Hardware control of Deep-sleep, Power-down, Deep power-down
modes
The hardware sleep event enable register (Table 116) enables the ARM Cortex-M0 cores
or the ARM Cortex-M4 core to trigger a system power-down (deep-sleep, power-down, or
deep power-down). All of the following conditions must be met for the core that triggers
the system power-down before the part to go into system power-down:

• The core’s enable bit is set in the PD0_SLEEP0_HW_ENA register. By default the M4
core is enabled.

• The core receives a WFI/WFE instruction.
• The core’s SLEEPDEEP bit is set to 1.
In a multi-core system, each core can force the part to enter system power-down
independently of the state (active or sleep) of the other cores. To reduce software
overhead, the hardware sleep event register also allows to delay entering deep-sleep,
power-down or deep power-down modes until software triggers a system power-down in
each core individually. See Table 113.
Table 113. PD0_SLEEP0_HW_ENA register settings
M4 core
enabled
for
sleep
events

M0APP
PD_SLEEP0_HW Description
and
_ENA register
M0SUB
value
cores
enabled for
sleep
events

Yes

No

0x1

M4 core controls power-down: System (all cores, peripherals, memories) enters
Deep-sleep, Power-down, or Deep power-down when M4 receives WFI/WFE
instruction and M4 SLEEPDEEP bit =1.
The M0 core can be in active mode, sleep mode, or reset.
This is the default setting.

No

Yes

0x2

M0 cores control power-down System (all cores, peripherals, memories) enters
Deep-sleep, Power-down, or Deep power-down when both M0 cores receive
WFI/WFE instruction and M0 SLEEPDEEP bit =1. If one M0 core is in reset or
disabled, the remaining active core alone controls power-down,
The M4 core can be in active mode or sleep mode.

Yes

Yes

0x3

System enters Deep-sleep, Power-down, or Deep power-down once each core
has received a WFI/WFE instruction and their SLEEPDEEP bits =1.
Only active cores can control power-down. Cores which are disabled or in reset
are ignored.

12.2.7 Memory retention in Power-down modes
Table 114 shows which parts of the SRAM memory are preserved in Sleep mode and the
various power-down modes.
In addition, all FIFO memory contained in the peripheral blocks (USB0/1, LCD, CAN,
Ethernet, USART0/2/3, UART) is retained in Sleep mode and Deep-sleep mode but not in
Power-down mode and Deep-power-down mode.

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Table 114. Memory retention
Mode

32/128 kB
local SRAM
starting at
0x1000 0000

64/32 kB Local
SRAM starting
at
0x1008 0000[1]

8 kB local SRAM
starting at
0x1009 0000/
0x1008 8000[2]

16 + 2 kB M0
subsystem
SRAM starting at
location
0x1800 0000[3]

64 kB AHB
SRAM
starting at
0x2000 0000

256 byte
backup
registers at
0x4004 1000
(RTC power
domain)

Sleep mode

yes

yes

yes

yes

yes

yes

Deep-sleep mode

yes

yes

yes

yes

yes

yes

Power-down mode no

no

yes

no

no

yes

Power-down mode no
with M0SUB
SRAM retained

no

yes

yes

no

yes

Deep power-down no
mode

no

no

no

no

yes

[1]

64 kB for LPC4370/50/30, LPC43S70/S50/S30; 32 kB for LPC4320/10, LPC43S20, and parts with on-chip flash.

[2]

For LPC4370/50/30 starting at 0x1009 0000; for LPC4320/10 and parts with on-chip flash starting at 0x1008 8000.

[3]

Parts LPC4370/LPC43S70 and LPC436x/LPC43S6x only.

12.3 Register description
Table 115. Register overview: Power Mode Controller (PMC) (base address 0x4004 2000)
Name

Access Address Description
offset

Reset
value

Reference

PD0_SLEEP0_HW_ENA R/W

0x000

Hardware sleep event
enable register

0x0000
0001

Table 116

-

-

0x004 0x018

Reserved

-

-

PD0_SLEEP0_MODE

R/W

0x01C

Power-down mode
control register

0x003F
FF7F

Table 117

12.3.1 Hardware sleep event enable register PD0_SLEEP0_HW_ENA
This register enables the M4 core, the M0 core together with the M0 subsystem core if
enabled on the part, or all cores for triggering the system power-down modes Deep-sleep,
Power-down, and Deep-power down. Only if at least one of the cores is enabled in this
register, can the system enter Deep-sleep, Power-down, or Deep power-down mode. The
system power down modes are entered once the core receives a WFI/WFE instruction
and the corresponding mode is set in the PD0_SLEEP0_MODE.
If all cores are enabled in this register, the system will only enter a system power-down
mode once each cores have received a WFI/WFE instruction. For details, see
Section 12.2.6.
Remark: Only cores in active or sleep mode can control entering the system power-down.
The sleep event enable setting is ignored for any core in reset.

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Table 116. Hardware sleep event enable register (PD0_SLEEP0_HW_ENA - address
0x4004 2000) bit description
Bit

Symbol

Description

Reset Access
value

0

ENA_EVENT0

Writing a 1 enables the Cortex-M4 core to put the part 1
into any of the Power-down modes Deep-sleep,
Power-down, or Deep power-down depending on the
value in the PD0_SLEEP0_MODE register.

R/W

1

ENA_EVENT1

Writing a 1 enables the Cortex-M0 core and the
Cortex-M0 subsystem core to put the part into any of
the Power-down modes Deep-sleep, Power-down, or
Deep power-down depending on the value in the
PD0_SLEEP0_MODE register.

R/W

31:2

-

Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit is not
defined.

0

-

12.3.2 Power-down modes register PD0_SLEEP0_MODE
The PD0_SLEEP0_MODE register controls which of the three power-down modes,
Deep-sleep, Power-down, or Deep power-down is entered when an ARM WFE/WFI
instruction is issued and the SLEEPDEEP bit is set to 1 (SLEEPDEEP state).
Table 117. Power-down modes register (PD0_SLEEP0_MODE - address 0x4004 201C) bit
description

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Bit

Symbol

Description

Reset
value

Access

31:0

PWR_STATE

Selects between Deep-sleep, Power-down, and
Deep power-down modes.
Only one of the following three values can be
programmed in this register:
0x0030 00AA = Deep-sleep mode
0x0030 FCBA = Power-down mode
0x0030 3CBA = Power-down mode with M0SUB
SRAM maintained
0x0030 FF7F = Deep power-down mode

0x0033
FF7F

R/W

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12.4 Functional description
12.4.1 Run-time programming
The PD0_SLEEP0_MODE register can be programmed at run-time to change the default
power state of the LPC43xx after the next transition to a reduced-power state.
Table 118. Typical settings for PMC power modes

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Power-down
mode

Description

PD0_SLEEP0_MODE
register bit settings

Deep-sleep

CPU, peripherals, analog, USB PHY in retention mode;
all SRAM supplies in active mode; BOD in power-down
mode.

0x0030 00AA

Power-down

CPU, peripherals, analog supplies in retention mode;
0x0030 FCBA
USB PHY in power-down mode; SRAM1 in active mode;
all other SRAMs in power-down mode; BOD in
power-down mode.

Power-down
with M0SUB
SRAM
maintained

CPU, peripherals, analog supplies in retention mode;
USB PHY in power-down mode; SRAM1 and M0SUB
SRAM in active mode; all other SRAMs in power-down
mode; BOD in power-down mode.

0x0030 3CBA

Deep
power-down

CPU, peripherals, analog, USB PHY in power-down
mode; all SRAMs in power-down mode; BOD in
power-down mode.

0x0030 FF7F

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13.1 How to read this chapter
Ethernet, USB0, USB1, and LCD related clocks are not available on all packages. See
Section 1.3. The corresponding clock control registers are reserved.
The ADCHS is available on LPC4370/LPC43S70 parts only.
The Cortex-M0SUB subsystem core is enabled on parts LPC4370/LPC43S70 and
LPC436x/LPC43S6x, but the SGPIO and SPI peripherals are available on all
LPC43xx/LPC43Sxx parts.

13.2 Basic configuration
The CGU is configured as follows:

• See Table 119 for clocking and power control.
• Do not reset the CGU during normal operation.
• For using core clock frequencies (BASE_M4_CLK) higher than 110 MHz with the
crystal oscillator, you must change the CGU configuration from the default setting in
several steps. See Section 13.2.1.
Table 119. CGU clocking and power control
CGU

Base clock

Branch clock

Operating frequency

BASE_M4_CLK

CLK_M4_BUS

up to 204 MHz

13.2.1 Configuring the BASE_M4_CLK for high operating frequencies
To ramp up the clock frequency to an operating frequency above 110 MHz, configure the
core clock BASE_M4_CLK as described in Section 13.2.1.1.
The recommended procedure to configure BASE_M4_CLK depends on the current clock
configuration of the part. There are two typical configurations:
1. After a power-up, reset, or when waking up from deep-power down mode. In these
situations, the boot code executes. After the boot process has completed, the clock
configuration of the part is as follows:
– The core clock BASE_M4_CLK is connected to the output of PLL1 and running at
96 MHz.
– The clock source for the PLL1 is the 12 MHz IRC.
2. After wake-up from Deep-sleep or power-down modes. In this case, BASE_M4_CLK
is connected to the IRC running at 12 MHz.
No special requirements exist for ramping down BASE_M4_CLK or changing any of the
peripheral base clocks either from low to high or from high to low frequencies.

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13.2.1.1 Changing the BASE_M4_CLK after power-up, reset, or deep power-down
mode
The following procedure shows how to change the default setting of the core clock
(BASE_M4_CLK = 96 MHz; IRC = PLL1 clock source) to an operating frequency above
110 MHz while also changing the clock source from IRC to crystal oscillator:
1. Select the IRC as BASE_M4_CLK source.
2. Enable the crystal oscillator (see Table 126).
3. Wait 250 s.
4. Set the AUTOBLOCK bit (bit 11). This bit re-synchronizes the clock output during
frequency changes that prevents glitches when switching clock frequencies.
5. Reconfigure PLL1 as follows (see Table 137):
– Select the M and N divider values to produce the final desired PLL1 output
frequency foutPLL.
– Select the crystal oscillator as clock source for PLL1.
6. Wait for the PLL1 to lock.
7. Set the PLL1 P-divider to divide by 2 (DIRECT = 0, PSEL=0).
8. Select PLL1 as BASE_M4_CLK source. The BASE_M4_CLK now operates in the
mid-frequency range.
9. Wait 50 s.
10. Set the PLL1 P-divider to direct output mode (DIRECT = 1).
The BASE_M4_CLK now operates in the high-frequency range.

13.2.1.2 Changing the BASE_M4_CLK after waking up from deep-sleep or
power-down modes
The following procedure shows how to ramp up the BASE_M4_CLK clock from low
frequencies to the high frequency range (see Figure 35). This procedure applies after
waking up from deep-sleep or power-down modes and any time the part runs at
frequencies < 90 MHz.
1. If the crystal oscillator is powered down, enable the crystal oscillator (see Table 126),
and wait 250 s.
2. Select the crystal oscillator as clock source for BASE_M4_CLK (seeTable 145).
3. Set the AUTOBLOCK bit (bit 11). This bit re-synchronizes the clock output during
frequency changes that prevents glitches when switching clock frequencies.
4. Reconfigure PLL1 as follows (see Table 137):
– Select the M and N divider values to produce the final desired PLL1 output
frequency foutPLL.
– Select the crystal oscillator as clock source for PLL1.
5. Wait for the PLL1 to lock.
6. Set the PLL1 P-divider to divide by 2 (DIRECT = 0, PSEL=0).
7. Select PLL1 as BASE_M4_CLK source. The BASE_M4_CLK now operates in the
mid-frequency range.
8. Wait 50 s.
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9. Set the PLL1 P-divider to direct output mode (DIRECT = 1).
The BASE_M4_CLK now operates in the high frequency range (110 MHz to 204 MHz).

BASE_M4_CLK
BASE_M4_CLK
clock source =

PLL1
(crystal osc)

IRC

204 MHz
foutPLL

50 μs
110 MHz
foutPLL/2
90 MHz
PLL1 lock
time
250 μs
12 MHz
wake-up from
deep-sleep mode
power-down mode

enable
crystal
oscillator

set PLL1 M, N dividers,
connect PLL1 to crystal
oscillator

PSEL = 0,
PSEL = 0,
DIRECT = 0,
DIRECT = 1
connect
PLL1 to
BASE_M4_CLK

Fig 35. BASE_M4_CLK ramp-up procedure

A similar two-step procedure applies when changing the BASE_M4_CLK from low to high
frequencies using the PLL0AUDIO as the clock source.

13.3 Features
• PLL control
• Supports three PLLs:
– the PLL0USB for creating the 480 MHz clock for the high-speed USB0
– the PLL0AUDIO with fractional divider for creating a wide variety of frequencies for
audio applications with high accuracy
– the PLL1 for creating the core and peripheral clocks.

• Oscillator control
• Clock generation and clock source multiplexing
• Integer dividers for clock output stages

13.4 General description
The CGU generates multiple independent clocks for the core and the peripheral blocks of
the LPC43x. Each independent clock is called a base clock and itself is one of the inputs
to the two Clock Control Units (CCUs) which control the branch clocks to the individual
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Chapter 13: LPC43xx/LPC43Sxx Clock Generation Unit (CGU)

peripherals (see Chapter 14).

CGU

PLL0
(USB0)

12 MHz IRC

RTCX1
RTCX2

PLL0
(AUDIO)

32 kHz OSC

IDIVB
/16
IDIVC
/16

XTAL1

PLL1

CRYSTAL OSC
XTAL2

WWDT

BASE_SAFE_CLK
IDIVA
/4
OUTCLK1- 6, 9 - 10
(BASE_xxx_CLK)

8

OUTCLK12 - 19
(BASE_xxx_CLK)

8

IDIVD
/16

OUTCLK7

IDIVE
/256

OUTCLK8

ENET_RX_CLK

CCU1

branch clocks to core
and peripherals

CCU2

branch clocks to
peripherals

ETHERNET

ENET_TX_CLK
GP_CLKIN

OUTCLK11

LCD_CLK

OUTCLK20

CLKOUT

OUTCLK25

I2S

OUTCLK26

CGU_OUT0

OUTCLK27

CGU_OUT1

Fig 36. CGU and CCU1/2 block diagram

The CGU selects the inputs to the clock generators from multiple clock sources, controls
the clock generation, and routes the outputs of the clock generators through the clock
source bus to the output stages. Each output stage provides an independent clock source
and corresponds to one of the base clocks for the LPC43xx. See Table 120 for a
description of each base clock and Table 122 for the possible clock sources for each base
clock.
The CGU contains four types of clock generators:
1. External clock inputs and internal clocks: The external clock inputs are the Ethernet
PHY clocks and the general purpose input clock GP_CLKIN. The clocks from the
internal oscillators are the IRC and the 32 kHz oscillator output clocks. These clock
generators have no selectable inputs from the clock source bus and provide one clock
output each to the clock source bus.
2. Crystal oscillator: The crystal oscillator is controlled by the CGU. The input to the
crystal oscillator are the XTAL pins. The crystal oscillator creates one output to the
clock source bus.
3. PLLs: PLL0USB, PLL0AUDIO, and PLL1 are controlled by the CGU. Each PLL can
select one input from the clock source bus and provides one output to the clock
source bus. The input to the PLLs can be selected from all external and internal
clocks and oscillators, from the other PLLs, and from the outputs of any of the integer
dividers (see Table 121). One PLL0 cannot select the other PLL0 as input.
4. Integer dividers: Each of the five integer dividers can select one input from the clock
source bus and creates one divided output clock to the clock source bus. The input to
all integer dividers can be selected from all external and internal clocks and
oscillators, and from all three PLLs. In addition, the output of the first integer divider
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Chapter 13: LPC43xx/LPC43Sxx Clock Generation Unit (CGU)

can be selected as an input to all other integer dividers (see Table 121).
– Integer divider A: maximum division factor = 4 (see Table 138).
– Integer dividers B, C, D: maximum division factor = 16 (see Table 139).
– Integer divider E: maximum division factor = 256 (see Table 140).
The output stages select a clock source from the clock source bus for each base clock
(see Table 122). Except for the base clocks to the WWDT (BASE_SAFE_CLK) and USB0
(BASE_USB0_CLK), the clock source for each output stage can be any of the external
and internal clocks and oscillators directly or one of the PLL outputs or any of the outputs
of the integer dividers.
Table 120. CGU0 base clocks
Number Name

Frequency

Description

[1]

0

BASE_SAFE_CLK

12 MHz

Base safe clock (always on) for WWDT

1

BASE_USB0_CLK

480 MHz

Base clock for USB0

2

BASE_PERIPH_CLK

204 MHz

Base clock for Cortex-M0SUB subsystem,
SPI, and SGPIO

3

BASE_USB1_CLK

204 MHz

Base clock for USB1

4

BASE_M4_CLK

204 MHz

System base clock for ARM Cortex-M4
core and APB peripheral blocks #0 and #2

5

BASE_SPIFI_CLK

204 MHz

Base clock for SPIFI

6

BASE_SPI_CLK

204 MHz

Base clock for SPI

7

BASE_PHY_RX_CLK

75 MHz

Base clock for Ethernet PHY Receive
clock

8

BASE_PHY_TX_CLK

75 MHz

Base clock for Ethernet PHY Transmit
clock

9

BASE_APB1_CLK

204 MHz

Base clock for APB peripheral block # 1

10

BASE_APB3_CLK

204 MHz

Base clock for APB peripheral block # 3

11

BASE_LCD_CLK

204 MHz

Base clock for LCD

12

BASE_ADCHS_CLK

80 MHz

Base clock for ADCHS

13

BASE_SDIO_CLK

204 MHz

Base clock for SD/MMC

14

BASE_SSP0_CLK

204 MHz

Base clock for SSP0

15

BASE_SSP1_CLK

204 MHz

Base clock for SSP1

16

BASE_UART0_CLK

204 MHz

Base clock for UART0

17

BASE_UART1_CLK

204 MHz

Base clock for UART1

18

BASE_UART2_CLK

204 MHz

Base clock for UART2

19

BASE_UART3_CLK

204 MHz

Base clock for UART3

20

BASE_OUT_CLK

204 MHz

Base clock for CLKOUT pin

24-21

-

-

Reserved

25

BASE_AUDIO_CLK

204 MHz

Base clock for audio system (I2S)

26

BASE_CGU_OUT0_CLK

204 MHz

Base clock for CGU_OUT0 clock output

27

BASE_CGU_OUT1_CLK

204 MHz

Base clock for CGU_OUT1 clock output

[1]

Maximum frequency that guarantees stable operation of the LPC43xx.

Table 121 shows all available input clock sources for each clock generator.
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Chapter 13: LPC43xx/LPC43Sxx Clock Generation Unit (CGU)

Table 121. Clock sources for clock generators with selectable inputs
Clock generators
Clock sources

PLL0
USB

PLL0
AUDIO

PLL1

IDIVA
/4

IDIVB
/16

IDIVC
/16

IDIVD
/16

IDIVE
/256

32 kHz oscillator

yes

yes

yes

yes

yes

yes

yes

yes

IRC 12 MHz

yes

yes

yes

yes

yes

yes

yes

yes

ENET_RX_CLK

yes

yes

yes

yes

yes

yes

yes

yes

ENET_TX_CLK

yes

yes

yes

yes

yes

yes

yes

yes

GP_CLKIN

yes

yes

yes

yes

yes

yes

yes

yes

Crystal oscillator

yes

yes

yes

yes

yes

yes

yes

yes

PLL0USB

no

no

yes

yes

no

no

no

no

PLL0AUDIO

no

no

yes

yes

yes

yes

yes

yes

PLL1

yes

yes

no

yes

yes

yes

yes

yes

IDIVA

yes

yes

yes

no

yes

yes

yes

yes

IDIVB

yes

yes

yes

no

no

no

no

no

IDIVC

yes

yes

yes

no

no

no

no

no

IDIVD

yes

yes

yes

no

no

no

no

no

IDIVE

yes

yes

yes

no

no

no

no

no

Table 122. Clock sources for output stages
Output stages (d = default clock source, y = yes (clock source available), n = no (clock
source not available))

BASE_PERIPH_CLK

BASE_USB1_CLK

BASE_M4_CLK

BASE_SPIFI_CLK

BASE_SPI_CLK

BASE_PHY_RX_CLK

BASE_PHY_TX_CLK

BASE_APB1_CLK

BASE_APB3_CLK

BASE_LCD_CLK

BASE_ADCHS_CLK

BASE_SDIO_CLK

BASE_SSP0_CLK

BASE_SSP1_CLK

BASE_UART0_CLK

BASE_UART1_CLK

BASE_UART2_CLK

BASE_UART3_CLK

BASE_OUT_CLK

BASE_AUDIO_CLK

BASE_CGU_OUT0_CLK

BASE_CGU_OUT1_CLK

32 kHz
n
oscillator

n

y

y

y

y

y

y

y

y

y

y

y

y

y

y

y

y

y

y

y

y

y

y

IRC
12 MHz

d

n

d

d

d

d

d

d

d

d

d

d

d

d

d

d

d

d

d

d

d

d

d

d

ENET_
n
RX_CLK

n

y

y

y

y

y

y

y

y

y

y

y

y

y

y

y

y

y

y

y

y

y

y

ENET_
n
TX_CLK

n

y

y

y

y

y

y

y

y

y

y

y

y

y

y

y

y

y

y

y

y

y

y

GP_
CLKIN

n

n

y

y

y

y

y

y

y

y

y

y

y

y

y

y

y

y

y

y

y

y

y

y

Crystal
n
oscillator

n

y

y

y

y

y

y

y

y

y

y

y

y

y

y

y

y

y

y

y

y

y

y

PLL0
USB

n

d

n

y

n

n

n

n

n

n

n

n

n

n

n

n

n

n

n

n

y

n

y

y

PLL0
AUDIO

n

n

y

y

y

y

y

y

y

y

y

y

y

y

y

y

y

y

y

y

y

y

y

y

BASE_SAFE_CLK

BASE_USB0_CLK

Clock
sources

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Chapter 13: LPC43xx/LPC43Sxx Clock Generation Unit (CGU)

Table 122. Clock sources for output stages
Output stages (d = default clock source, y = yes (clock source available), n = no (clock
source not available))

BASE_SAFE_CLK

BASE_USB0_CLK

BASE_PERIPH_CLK

BASE_USB1_CLK

BASE_M4_CLK

BASE_SPIFI_CLK

BASE_SPI_CLK

BASE_PHY_RX_CLK

BASE_PHY_TX_CLK

BASE_APB1_CLK

BASE_APB3_CLK

BASE_LCD_CLK

BASE_ADCHS_CLK

BASE_SDIO_CLK

BASE_SSP0_CLK

BASE_SSP1_CLK

BASE_UART0_CLK

BASE_UART1_CLK

BASE_UART2_CLK

BASE_UART3_CLK

BASE_OUT_CLK

BASE_AUDIO_CLK

BASE_CGU_OUT0_CLK

BASE_CGU_OUT1_CLK

Clock
sources

PLL1

n

n

y

y

y

y

y

y

y

y

y

y

y

y

y

y

y

y

y

y

y

y

y

y

IDIVA

n

n

y

y

y

y

y

y

y

y

y

y

y

y

y

y

y

y

y

y

y

y

y

y

IDIVB

n

n

y

y

y

y

y

y

y

y

y

y

y

y

y

y

y

y

y

y

y

y

y

y

IDIVC

n

n

y

y

y

y

y

y

y

y

y

y

y

y

y

y

y

y

y

y

y

y

y

y

IDIVD

n

n

y

y

y

y

y

y

y

y

y

y

y

y

y

y

y

y

y

y

y

y

y

y

IDIVE

n

n

y

y

y

y

y

y

y

y

y

y

y

y

y

y

y

y

y

y

y

y

y

y

CGU
Oscillators,
clock inputs

PLLs

Integer
dividers

Output
generators
BASE_SAFE_CLK

BASE_USB0_CLK

12 MHz IRC

RTCX1
RTCX2

32 kHz OSC
OUTCLK_20/26/27

XTAL1
CRYSTAL OSC
XTAL2
ENET_RX_CLK

IDIVA /4
PLL0
(USB0)

BASE_USB1_CLK
IDIVB /16

17
ENET_TX_CLK

PLL0
(AUDIO)

OUTCLK_2, 4 - 19
(BASE_xxx_CLK)

IDIVC /16
BASE_AUDIO_CLK

GP_CLKIN

IDIVD /16

PLL1

IDIVE /256

5

Fig 37. CGU block diagram

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Chapter 13: LPC43xx/LPC43Sxx Clock Generation Unit (CGU)

13.5 Pin description
Table 123. CGU pin description
Pin function

Direction

Description

XTAL1

I

Crystal oscillator input

XTAL2

O

Crystal oscillator output

RTCX1

I

RTC 32 kHz oscillator input

RTCX2

O

RTC 32 kHz oscillator output

GP_CLKIN

I

General purpose input clock

ENET_TX_CLK

I

Ethernet PHY transmit clock

ENET_RX_CLK

I

Ethernet PHY receive clock

CLKOUT

O

Clock output pin

CGU_OUT0

O

CGU spare output 0

CGU_OUT1

O

CGU spare output 1

13.6 Register description
The register addresses of the CGU are shown in Table 124.
Remark: The CGU is configured by the boot loader at reset and when waking up from
Deep power-down to produce a 96 MHz clock using PLL1.
Table 124. Register overview: CGU (base address 0x4005 0000)
Name

Access Address
offset

Description

Reset
value

Reset
value
after
EMC,
UART0/
3 boot

Reset
value
after
USB0/1
boot

Reference

-

R

0x000

Reserved

-

-

-

-

-

R

0x004

Reserved

-

-

-

-

-

R

0x008

Reserved

-

-

-

-

-

R

0x00C

Reserved

-

-

-

-

-

-

0x010

Reserved

-

FREQ_MON

R/W

0x014

Frequency monitor register

0

0

0

XTAL_OSC_CTRL

R/W

0x018

Crystal oscillator control
register

0x0000
0005

0x0100
0000

0 (USB0) Table 126

PLL0USB_STAT

R

0x01C

PLL0USB status register

0x0100
0000

0x0100
0000

0x1
(USB0)

Table 127

PLL0USB_CTRL

R/W

0x020

PLL0USB control register

0x0100
0003

0x0100
0000

0x0600
0818
(USB0)

Table 128

PLL0USB_MDIV

R/W

0x024

PLL0USB M-divider register

0x05F8
5B6A

0x0100
0000

0x0196
7FFA
(USB0)

Table 129

PLL0USB_NP_DIV

R/W

0x028

PLL0USB N/P-divider
register

0x000B
1002

0x0100
0000

0x0030
2062
(USB0)

Table 130

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Table 124. Register overview: CGU (base address 0x4005 0000)
Name

Access Address
offset

Description

Reset
value

Reset
value
after
EMC,
UART0/
3 boot

Reset
value
after
USB0/1
boot

Reference

PLL0AUDIO_STAT

R

0x02C

PLL0AUDIO status register

0x0100
0000

0x0100
0000

0x0100
0000

Table 131

PLL0AUDIO_CTRL

R/W

0x030

PLL0AUDIO control register

0x0100
4003

0x0100
0000

0x0100
0000

Table 132

PLL0AUDIO_MDIV

R/W

0x034

PLL0AUDIO M-divider
register

0x05F8
5B6A

0x0100
0000

0x0100
0000

Table 133

PLL0AUDIO_NP_DIV R/W

0x038

PLL0AUDIO N/P-divider
register

0x000B
1002

0x0100
0000

0x0100
0000

Table 134

PLL0AUDIO_FRAC

R/W

0x03C

PLL0AUDIO fractional
divider register

0x0020
0000

0x0100
0000

0x0100
0000

Table 135

PLL1_STAT

R

0x040

PLL1 status register

0x0100
0000

0x1

0x1
(USB1)

Table 136

PLL1_CTRL

R/W

0x044

PLL1 control register

0x0100
0003

0x0117
0880

0x0117
0880
(USB1)

Table 137

IDIVA_CTRL

R/W

0x048

Integer divider A control
register

0x0100
0000

0x0100
0000

0x0100
0000

Table 138

IDIVB_CTRL

R/W

0x04C

Integer divider B control
register

0x0100
0000

0x0100
0000

0x0100
0000

Table 139

IDIVC_CTRL

R/W

0x050

Integer divider C control
register

0x0100
0000

0x0900
0808

0x0900
0808

Table 139

IDIVD_CTRL

R/W

0x054

Integer divider D control
register

0x0100
0000

0x0100
0000

0x0100
0000

Table 139

IDIVE_CTRL

R/W

0x058

Integer divider E control
register

0x0100
0000

0x0100
0000

0x0100
0000

Table 140

BASE_SAFE_CLK

R

0x05C

Output stage 0 control
register for base clock
BASE_SAFE_CLK

0x0100
0000

0x0100
0000

0x0100
0000

Table 141

BASE_USB0_CLK

R/W

0x060

Output stage 1 control
register for base clock
BASE_USB0_CLK

0x0700
0000

0x0100
0000

0x0700
0800
(USB0)

Table 142

BASE_PERIPH_CLK

R/W

0x064

Output stage 2 control
register for base clock
BASE_PERIPH_CLK

0x0700
0000

-

-

Table 143

BASE_USB1_CLK

R/W

0x068

Output stage 3 control
register for base clock
BASE_USB1_CLK

0x0100
0000

0x0100
0000

0x0100
0000

Table 144

BASE_M4_CLK

R/W

0x06C

Output stage 4 control
register for base clock
BASE_M4_CLK

0x0100
0000

0x0100
0000

0x0100
0000

Table 145

BASE_SPIFI_CLK

R/W

0x070

Output stage 5 control
register for base clock
BASE_SPIFI_CLK

0x0100
0000

0x0100
0000

0x0100
0000

Table 145

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Chapter 13: LPC43xx/LPC43Sxx Clock Generation Unit (CGU)

Table 124. Register overview: CGU (base address 0x4005 0000)
Name

Access Address
offset

Description

Reset
value

Reset
value
after
EMC,
UART0/
3 boot

Reset
value
after
USB0/1
boot

Reference

BASE_SPI_CLK

R/W

0x074

Output stage 6 control
register for base clock
BASE_SPI_CLK

0x0100
0000

0x0100
0000

0x0100
0000

Table 145

BASE_PHY_RX_CLK R/W

0x078

Output stage 7 control
register for base clock
BASE_PHY_RX_CLK

0x0100
0000

0x0100
0000

0x0100
0000

Table 145

BASE_PHY_TX_CLK R/W

0x07C

Output stage 8 control
register for base clock
BASE_PHY_TX_CLK

0x0100
0000

0x0100
0000

0x0100
0000

Table 145

BASE_APB1_CLK

R/W

0x080

Output stage 9 control
register for base clock
BASE_APB1_CLK

0x0100
0000

0x0100
0000

0x0100
0000

Table 145

BASE_APB3_CLK

R/W

0x084

Output stage 10 control
register for base clock
BASE_APB3_CLK

0x0100
0000

0x0100
0000

0x0100
0000

Table 145

BASE_LCD_CLK

R/W

0x088

Output stage 11 control
register for base clock
BASE_LCD_CLK

0x0100
0000

0x0100
0000

0x0100
0000

Table 145

BASE_ADCHS_CLK

R/W

0x08C

Output stage 12 control
register for base clock
BASE_ADCHS_CLK

0x0100
0000

0x0100
0000

0x0100
0000

Table 145

BASE_SDIO_CLK

R/W

0x090

Output stage 13 control
register for base clock
BASE_SDIO_CLK

0x0100
0000

0x0100
0000

0x0100
0000

Table 145

BASE_SSP0_CLK

R/W

0x094

Output stage 14 control
register for base clock
BASE_SSP0_CLK

0x0100
0000

0x0100
0000

0x0100
0000

Table 145

BASE_SSP1_CLK

R/W

0x098

Output stage 15 control
register for base clock
BASE_SSP1_CLK

0x0100
0000

0x0100
0000

0x0100
0000

Table 145

BASE_UART0_CLK

R/W

0x09C

Output stage 16 control
register for base clock
BASE_UART0_CLK

0x0100
0000

0x0100
0000

0x0100
0000

Table 145

BASE_UART1_CLK

R/W

0x0A0

Output stage 17 control
register for base clock
BASE_UART1_CLK

0x0100
0000

0x0100
0000

0x0100
0000

Table 145

BASE_UART2_CLK

R/W

0x0A4

Output stage 18 control
register for base clock
BASE_UART2_CLK

0x0100
0000

0x0100
0000

0x0100
0000

Table 145

BASE_UART3_CLK

R/W

0x0A8

Output stage 19 control
register for base clock
BASE_UART3_CLK

0x0100
0000

0x0100
0000

0x0100
0000

Table 145

BASE_OUT_CLK

R/W

0x0AC

Output stage 20 control
register for base clock
BASE_OUT_CLK

0x0100
0000

0x0100
0000

0x0100
0000

Table 146

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Chapter 13: LPC43xx/LPC43Sxx Clock Generation Unit (CGU)

Table 124. Register overview: CGU (base address 0x4005 0000)
Name

Access Address
offset

Description

Reset
value

Reset
value
after
EMC,
UART0/
3 boot

Reset
value
after
USB0/1
boot

Reference

OUTCLK_21_CTRL
to
OUTCLK_24_CTRL

R/W

0x0B0 to
0x0BC

Reserved output stages

-

-

-

-

BASE_AUDIO_CLK

R/W

0x0C0

Output stage 25 control
register for base clock
BASE_AUDIO_CLK

0x0100
0000

0x0100
0000

0x0100
0000

Table 147

BASE_CGU_OUT0_
CLK

R/W

0x0C4

Output stage 26 control
register for base clock
BASE_CGU_OUT0_CLK

0x0100
0000

0x0100
0000

0x0100
0000

Table 148

BASE_CGU_OUT1_
CLK

R/W

0x0C8

Output stage 27 control
register for base clock
BASE_CGU_OUT1_CLK

0x0100
0000

0x0100
0000

0x0100
0000

Table 148

13.6.1 Frequency monitor register
The CGU can report the relative frequency of any operating clock. The clock to be
measured must be selected by software, while the fixed-frequency IRC clock fref is used
as the reference frequency. A 14-bit counter then counts the number of cycles of the
measured clock that occur during a user-defined number of reference-clock cycles. When
the MEAS bit is set, the measured-clock counter is reset to 0 and counts up, while the
9-bit reference-clock counter is loaded with the value in RCNT and then counts down
towards 0. When either counter reaches its terminal value both counters are disabled and
the MEAS bit is reset to 0. The current values of the counters can then be read out and
the selected frequency obtained by the following equation:
FCNT
fselected = ----------------  fref
RCNT

Note that the accuracy of this measurement can be affected by several factors:
1. Quantization error is noticeable if the ratio between the two clocks is large (e.g.
100 kHz vs. 1 kHz), because one counter saturates while the other still has only a
small count value.
2. Due to synchronization, the counters are not started and stopped at exactly the same
time.
3. The measured frequency can only be to the same level of precision as the reference
frequency.

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Chapter 13: LPC43xx/LPC43Sxx Clock Generation Unit (CGU)

Table 125. FREQ_MON register (FREQ_MON, address 0x4005 0014) bit description
Bit

Symbol

8:0

Description

Reset
value

Access

RCNT

9-bit reference clock-counter value

0

R/W

22:9

FCNT

14-bit selected clock-counter value

0

R

23

MEAS

Measure frequency

0

R/W

Clock-source selection for the clock to be 0
measured. All other values are reserved.

R/W

28:24

31:29

Value

0

RCNT and FCNT disabled

1

Frequency counters started

CLK_SEL

-

0x00

32 kHz oscillator (default)

0x01

IRC

0x02

ENET_RX_CLK

0x03

ENET_TX_CLK

0x04

GP_CLKIN

0x05

Reserved

0x06

Crystal oscillator

0x07

PLL0USB

0x08

PLL0AUDIO

0x09

PLL1

0x0A

Reserved

0x0B

Reserved

0x0C

IDIVA

0x0D

IDIVB

0x0E

IDIVC

0x0F

IDIVD

0x10

IDIVE
Reserved

-

-

13.6.2 Crystal oscillator control register
The register XTAL_OSC_CONTROL contains the control bits for the crystal oscillator.
Table 126. XTAL_OSC_CTRL register (XTAL_OSC_CTRL, address 0x4005 0018) bit
description

UM10503

User manual

Bit

Symbol

0

ENABLE

Value Description

Reset Access
value

Oscillator-pad enable. Do not change the BYPASS 1
and ENABLE bits in one write-action: this will result
in unstable device operation!
0

Enable

1

Power-down (default)

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Table 126. XTAL_OSC_CTRL register (XTAL_OSC_CTRL, address 0x4005 0018) bit
description
Bit

Symbol

1

BYPASS

2

31:3

Value Description

Reset Access
value

Configure crystal operation or external-clock input
pin XTAL1. Do not change the BYPASS and
ENABLE bits in one write-action: this will result in
unstable device operation!
0

Crystal. Operation with crystal connected (default).

1

Bypass mode. Use this mode when an external
clock source is used instead of a crystal.

HF

Select frequency range
0

Low. Oscillator low-frequency mode (crystal or
external clock source 1 to 20 MHz). Between 15
MHz and 20 MHz, the state of the HF bit is don’t
care.

1

High. Oscillator high-frequency mode; crystal or
external clock source 15 to 25 MHz. Between 15
MHz and 20 MHz, the state of the HF bit is don’t
care.

-

Reserved

0

R/W

1

R/W

-

-

13.6.3 PLL0USB registers
The PLL0USB provides a dedicated clock to the High-speed USB0 interface.
See Section 13.7.4.5 for instructions on how to set up the PLL0USB.

13.6.3.1 PLL0USB status register
Table 127. PLL0USB status register (PLL0USB_STAT, address 0x4005 001C) bit description
Bit

Symbol

Description

Reset
value

Access

0

LOCK

PLL0 lock indicator

0

R

1

FR

PLL0 free running indicator

0

R

31:2

-

Reserved

-

13.6.3.2 PLL0USB control register
Table 128. PLL0USB control register (PLL0USB_CTRL, address 0x4005 0020) bit description
Bit

Symbol

0

PD

1

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Value

Description

Reset
value

Access

PLL0 power down

1

R/W

1

R/W

0

PLL0 enabled

1

PLL0 powered down

0

CCO clock sent to post-dividers. Use this
in normal operation.

1

PLL0 input clock sent to post-dividers
(default).

BYPASS

Input clock bypass control

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Table 128. PLL0USB control register (PLL0USB_CTRL, address 0x4005 0020) bit description
…continued

Bit

Symbol

Value

Description

Reset
value

Access

2

DIRECTI

PLL0 direct input

0

R/W

3

DIRECTO

PLL0 direct output

0

R/W

4

CLKEN

PLL0 clock enable

0

R/W

5

-

Reserved

-

-

6

FRM

Free running mode

0

R/W

7

-

Reserved

0

R/W

8

-

Reserved. Reads as zero. Do not write
one to this register.

0

R/W

9

-

Reserved. Reads as zero. Do not write
one to this register.

0

R/W

10

-

Reserved. Reads as zero. Do not write
one to this register.

0

R/W

11

AUTOBLOCK

Block clock automatically during frequency 0
change[1].

R/W

0

Disabled. Autoblocking disabled

1

Enabled. Autoblocking enabled

23:12

-

Reserved

-

-

28:24

CLK_SEL

Clock source selection. All other values
are reserved..

0x01

R/W

-

-

31:29
[1]

-

0x00

32 kHz oscillator

0x01

IRC (default)

0x02

ENET_RX_CLK

0x03

ENET_TX_CLK

0x04

GP_CLKIN

0x06

Crystal oscillator

0x09

PLL1

0x0C

IDIVA

0x0D

IDIVB

0x0E

IDIVC

0x0F

IDIVD

0x10

IDIVE
Reserved

When the PLL0USB is enabled, set the AUTOBLOCK bit (bit 11). This bit re-synchronizes the clock output
during frequency changes that prevents glitches when switching clock frequencies.

13.6.3.3 PLL0USB M-divider register
Remark: The PLL M-divider register does not use the direct binary representations of M
directly. Instead, it uses an encoded version MDEC of M. The valid range for M is 1 to
2^15. This value is encoded into a 17-bit MDEC value.
The relationship between M = msel and MDEC is expressed via the following code
snippet. For specific examples see Section 13.8.3 and Section 13.8.4.
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#define PLL0_MSEL_MAX (1<<15)
/* multiplier: compute mdec from msel */
unsigned mdec_new (unsigned msel) {
unsigned x=0x4000, im;
switch (msel) {
case 0: return 0xFFFFFFFF;
case 1: return 0x18003;
case 2: return 0x10003;
default:
for (im = msel; im <= PLL0_MSEL_MAX; im++)
x = ((x ^ x>>1) & 1) << 14 | x>>1 & 0xFFFF;
return x;
}
}
The values for SELP and SELI depend on the value for M = msel as expressed by the
following code snippet (SELR = 0):
/* bandwidth: compute seli from msel */
unsigned anadeci_new (unsigned msel) {
unsigned tmp;
if (msel > 16384) return 1;
if (msel > 8192) return 2;
if (msel > 2048) return 4;
if (msel >= 501) return 8;
if (msel >= 60) {
tmp=1024/(msel+9);
return ( 1024 == ( tmp*(msel+9)) ) == 0 ? tmp*4 : (tmp+1)*4 ;
}
return (msel & 0x3c) + 4;
}
/* bandwidth: compute selp from msel */
unsigned anadecp_new (unsigned msel) {
if (msel < 60) return (msel>>1) + 1;
return 31;
}
Table 129. PLL0USB M-divider register (PLL0USB_MDIV, address 0x4005 0024) bit
description

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Bit

Symbol

Description

16:0

MDEC

Decoded M-divider coefficient value. Select values for 0x5B6A
the M-divider between 1 and 131071.

R/W

21:17

SELP

Bandwidth select P value

11100

R/W

27:22

SELI

Bandwidth select I value

010111

R/W

31:28

SELR

Bandwidth select R value; SELR = 0.

0000

R/W

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Reset
value

Access

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Chapter 13: LPC43xx/LPC43Sxx Clock Generation Unit (CGU)

13.6.3.4 PLL0USB NP-divider register
Remark: The PLL NP-divider register does not use the direct binary representations of N
= nsel and P = psel directly. Instead, it uses encoded versions NDEC and PDEC of N and
P respectively.

• The valid range for N = nsel is from 1 to 2^8. This value is encoded into a 10-bit NDEC
value. The relationship can be expressed through the following code snippet:
#define PLL0_NSEL_MAX (1<<8)
/* pre-divider: compute ndec from nsel */
unsigned ndec_new (unsigned nsel) {
unsigned x=0x80, in;
switch (nsel) {
case 0: return 0xFFFFFFFF;
case 1: return 0x302;
case 2: return 0x202;
default:for (in = nsel; in <= PLL0_NSEL_MAX; in++)
x = ((x ^ x>>2 ^ x>>3 ^ x>>4) & 1) << 7 | x>>1 & 0xFF;
return x;
}
}

• The valid range for P = psel is from 1 to 2^5. This value is encoded into a 7-bit PDEC
value. The relationship can be expressed through the following code snippet:
#define PLL0_PSEL_MAX (1<<5)
/* post-divider: compute pdec from psel */
unsigned pdec_new (unsigned psel) {
unsigned x=0x10, ip;
switch (psel) {
case 0: return 0xFFFFFFFF;
case 1: return 0x62;
case 2: return 0x42;
default:for (ip = psel; ip <= PLL0_PSEL_MAX; ip++)
x = ((x ^ x>>2) & 1) << 4 | x>>1 & 0x3F;
return x;
}
}
For specific examples see Section 13.8.3 and Section 13.8.4.
Table 130. PLL0USB NP-divider register (PLL0USB_NP_DIV, address 0x4005 0028) bit
description

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Bit

Symbol

Description

Reset
value

Access

6:0

PDEC

Decoded P-divider coefficient value

000 0010

R/W
-

11:7

-

Reserved

-

21:12

NDEC

Decoded N-divider coefficient value

1011 0001 R/W

31:22

-

Reserved

-

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13.6.4 PLL0AUDIO registers
The PLL0AUDIO provides a wide range of frequencies for audio applications and can be
connected to multiple base clocks. The PLL0AUDIO can be used with or without a
fractional divider.
See Section 13.7.4.5 for instructions on how to set up the PLL0.

13.6.4.1 PLL0AUDIO status register
Table 131. PLL0AUDIO status register (PLL0AUDIO_STAT, address 0x4005 002C) bit
description
Bit

Symbol

Description

Reset
value

Access

0

LOCK

PLL0 lock indicator

0

R

1

FR

PLL0 free running indicator

0

R

31:2

-

Reserved

-

13.6.4.2 PLL0AUDIO control register
Table 132. PLL0AUDIO control register (PLL0AUDIO_CTRL, address 0x4005 0030) bit
description
Bit

Symbol

0

PD

1

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Value

Description

Reset
value

Access

PLL0 power down

1

R/W

1

R/W

0

PLL0 enabled

1

PLL0 powered down

BYPASS

Input clock bypass control
0

CCO clock sent to post-dividers. Use this
in normal operation.

1

PLL0 input clock sent to post-dividers
(default).

2

DIRECTI

PLL0 direct input

0

R/W

3

DIRECTO

PLL0 direct output

0

R/W

4

CLKEN

PLL0 clock enable

0

R/W

5

-

Reserved

-

-

6

FRM

Free running mode

0

R/W

7

-

Reserved

0

R/W

8

-

Reserved. Reads as zero. Do not write
one to this register.

0

R/W

9

-

Reserved. Reads as zero. Do not write
one to this register.

0

R/W

10

-

Reserved. Reads as zero. Do not write
one to this register.

0

R/W

11

AUTOBLOCK

Block clock automatically during frequency 0
change [1].

R/W

0

Disabled. Autoblocking disabled

1

Enabled. Autoblocking enabled

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Chapter 13: LPC43xx/LPC43Sxx Clock Generation Unit (CGU)

Table 132. PLL0AUDIO control register (PLL0AUDIO_CTRL, address 0x4005 0030) bit
description
…continued

Bit

Symbol

12

PLLFRACT_
REQ

13

SEL_EXT

14

Value

Description

Access

Fractional PLL word write request. Set this 0
bit to 1 if the fractional divider is enabled in
the SEL_EXT bit.

R/W

Select fractional divider.

0

R/W

1

R/W

0

FRAC Enabled. Enable fractional divider.

1

MDEC enabled. Fractional divider not
used.

MOD_PD

Reset
value

Sigma-Delta modulator power-down
0

Enabled. Sigma-Delta modulator enabled

1

Disabled. Sigma-Delta modulator powered
down

23:15

-

Reserved

-

-

28:24

CLK_SEL

Clock source selection. All other values
are reserved.

0x01

R/W

-

-

31:29
[1]

-

0x00

32 kHz oscillator

0x01

IRC (default)

0x02

ENET_RX_CLK

0x03

ENET_TX_CLK

0x04

GP_CLKIN

0x06

Crystal oscillator

0x09

PLL1

0x0C

IDIVA

0x0D

IDIVB

0x0E

IDIVC

0x0F

IDIVD

0x10

IDIVE
Reserved

When the PLL0AUDIO is enabled, set the AUTOBLOCK bit in the PLL0AUDIO_CTRL. This bit
re-synchronizes the clock output during frequency changes that prevents glitches when switching clock
frequencies.

13.6.4.3 PLL0AUDIO M-divider register
The PLL0AUDIO M-divider register can be set directly if the PLL0AUDIO is not used in
fractional mode. If the fractional divider is enabled (see Table 135), then the fractional
divider sets the MDEC value.
Remark: The PLL M-divider register does not use the direct binary representations of M
directly. Instead, it uses an encoded version MDEC of M. The valid range for M is 1 to
2^15. This value is encoded into a 17-bit MDEC value.
The relationship between M = msel and MDEC is expressed via the following code
snippet. For specific examples see Section 13.8.3 and Section 13.8.4.
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Chapter 13: LPC43xx/LPC43Sxx Clock Generation Unit (CGU)

#define PLL0_MSEL_MAX (1<<15)
/* multiplier: compute mdec from msel */
unsigned mdec_new (unsigned msel) {
unsigned x=0x4000, im;
switch (msel) {
case 0: return 0xFFFFFFFF;
case 1: return 0x18003;
case 2: return 0x10003;
default:
for (im = msel; im <= PLL0_MSEL_MAX; im++)
x = ((x ^ x>>1) & 1) << 14 | x>>1 & 0xFFFF;
return x;
}
}
Remark: The values for SELP, SELI, and SELR are generated by the encoding block and
need not be programmed explicitly.
Table 133. PLL0AUDIO M-divider register (PLL0AUDIO_MDIV, address 0x4005 0034) bit
description
Bit

Symbol

Description

Reset
value

16:0

MDEC

Decoded M-divider coefficient value. Select values for 0x5B6A
the M-divider between 1 and 131071.

R/W

31:17

-

Reserved

-

-

Access

13.6.4.4 PLL0AUDIO NP-divider register
Remark: The PLL NP-divider register does not use the direct binary representations of N
and P directly. Instead, it uses encoded versions NDEC and PDEC of N = nsel and P =
psel respectively.

• The valid range for N = nsel is from 1 to 2^8. This value is encoded into a 10-bit NDEC
value. The relationship can be expressed through the following code snippet:
#define PLL0_NSEL_MAX (1<<8)
/* pre-divider: compute ndec from nsel */
unsigned ndec_new (unsigned nsel) {
unsigned x=0x80, in;
switch (nsel) {
case 0: return 0xFFFFFFFF;
case 1: return 0x302;
case 2: return 0x202;
default:for (in = nsel; in <= PLL0_NSEL_MAX; in++)
x = ((x ^ x>>2 ^ x>>3 ^ x>>4) & 1) << 7 | x>>1 & 0xFF;
return x;
}
}

• The valid range for P = psel is from 1 to 2^5. This value is encoded into a 7-bit PDEC
value. The relationship can be expressed through the following code snippet:
#define PLL0_PSEL_MAX (1<<5)
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Chapter 13: LPC43xx/LPC43Sxx Clock Generation Unit (CGU)

/* post-divider: compute pdec from psel */
unsigned pdec_new (unsigned psel) {
unsigned x=0x10, ip;
switch (psel) {
case 0: return 0xFFFFFFFF;
case 1: return 0x62;
case 2: return 0x42;
default:for (ip = psel; ip <= PLL0_PSEL_MAX; ip++)
x = ((x ^ x>>2) & 1) << 4 | x>>1 & 0x3F;
return x;
}
}
Table 134. PLL0 AUDIO NP-divider register (PLL0AUDIO_NP_DIV, address 0x4005 0038) bit
description
Bit

Symbol

Description

Reset
value

Access

6:0

PDEC

Decoded P-divider coefficient value

000 0010

R/W

11:7

-

Reserved

-

-

21:12

NDEC

Decoded N-divider coefficient value

1011 0001 R/W

31:22

-

Reserved

-

-

13.6.4.5 PLL0AUDIO fractional divider register
When the fractional divider is active, the sigma-delta modulator block generates divider
values M and M+1 in the correct proportion so that an average division ratio of M+K/L is
realized where 0<=K<=L and M, K, and L are integer values. M Is determined by the
integer part of the PLLFRACT_CTRL register (PLLFRACT[21:15]) and K is determined by
the fractional part of the PLLFRACT_CTRL register (PLLFRACT[14:0]). Consecutive M
and M+1 values are then further encoded into appropriate MDEC values before being
presented as input to the M-divider.
Table 135. PLL0AUDIO fractional divider register (PLL0AUDIO_FRAC, address 0x4005 003C)
bit description
Bit

Symbol

Description

Reset
value

Access

21:0

PLLFRACT_CTRL

PLL fractional divider control word

000 0000

R/W

31:22

-

Reserved

-

-

13.6.5 PLL1 registers
The PLL1 is used for the core and all peripheral blocks.

13.6.5.1 PLL1 status register
Table 136. PLL1 status register (PLL1_STAT, address 0x4005 0040) bit description

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Bit

Symbol

Description

Reset
value

Access

0

LOCK

PLL1 lock indicator

0

R

31:1

-

Reserved

-

-

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Chapter 13: LPC43xx/LPC43Sxx Clock Generation Unit (CGU)

13.6.5.2 PLL1 control register
Table 137. PLL1_CTRL register (PLL1_CTRL, address 0x4005 0044) bit description
Bit

Symbol

0

PD

Value Description
PLL1 power down
0
1

1

R/W

1

R/W

PLL1 enabled
PLL1 powered down
Input clock bypass control

0

Normal. CCO clock sent to post-dividers. Use
for normal operation.

1

Input clock. PLL1 input clock sent to
post-dividers (default).

-

Reserved. Do not write one to this bit.

0

R/W

5:3

-

Reserved. Do not write one to these bits.

-

-

6

FBSEL

PLL feedback select (see Figure 40 “PLL1
block diagram”).

0

R/W

0

R/W

01

R/W

9:8

0

CCO out. CCO output is used as feedback
divider input clock.

1

PLL out. PLL output clock (clkout) is used as
feedback divider input clock. Use for normal
operation.

DIRECT

PLL direct CCO output
0

Disabled

1

Enabled

PSEL

Post-divider division ratio P. The P-divider
applied by the PLL is 2xP.
0x0

P=1

0x1

P = 2 (default)

0x2

P=4

0x3

P=8

10

-

Reserved

-

-

11

AUTOBLOCK

Block clock automatically during frequency
change[1].

0

R/W

10

R/W

-

-

13:12

15:14

User manual

BYPASS

1

2

7

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value

0

Disabled. Autoblocking disabled

1

Enabled. Autoblocking enabled

NSEL

-

Pre-divider division ratio N
0x0

1

0x1

2

0x2

3 (default)

0x3

4
Reserved

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Chapter 13: LPC43xx/LPC43Sxx Clock Generation Unit (CGU)

Table 137. PLL1_CTRL register (PLL1_CTRL, address 0x4005 0044) bit description
…continued

Bit

Symbol

23:16

MSEL

Value Description

Reset Access
value
11000 R/W

Feedback-divider division ratio (M)
00000000 = 1
00000001 = 2
...
11111111 = 256

28:24

31:29
[1]

CLK_SEL

Clock-source selection.
0x00

32 kHz oscillator

0x01

IRC (default)

0x02

ENET_RX_CLK

0x03

ENET_TX_CLK

0x04

GP_CLKIN

0x05

Reserved

0x06

Crystal oscillator

0x07

PLL0USB

0x08

PLL0AUDIO

0x09

Reserved

0x0A

Reserved

0x0C

IDIVA

0x0D

IDIVB

0x0E

IDIVC

0x0F

IDIVD

0x10

IDIVE

-

Reserved

0x01

R/W

-

-

When the PLL1 is enabled, set the AUTOBLOCK bit in the PLL1_CTRL register to 1. This bit
re-synchronizes the clock output during frequency changes that prevents glitches when switching clock
frequencies.

13.6.6 Integer divider register A
Table 138. IDIVA control register (IDIVA_CTRL, address 0x4005 0048) bit description
Bit

Symbol

0

PD

1

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-

Value

Description

Reset
value

Access

Integer divider A power down

0

R/W

-

-

0

Enabled. IDIVA enabled (default)

1

Power-down
Reserved

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Chapter 13: LPC43xx/LPC43Sxx Clock Generation Unit (CGU)

Table 138. IDIVA control register (IDIVA_CTRL, address 0x4005 0048) bit description
…continued

Bit

Symbol

3:2

IDIV

Value

Description

Reset
value

Access

Integer divider A divider values
(1/(IDIV + 1))

00

R/W

-

-

0x0

1 (default)

0x1

2

0x2

3

0x3

4

10:4

-

Reserved

11

AUTOBLOCK

Block clock automatically during frequency 0
change
0

Disabled. Autoblocking disabled

1

Enabled. Autoblocking enabled

R/W

23:12

-

Reserved

-

-

28:24

CLK_SEL

Clock source selection. All other values
are reserved.

0x01

R/W

-

-

31:29

0x00

32 kHz oscillator

0x01

IRC (default)

0x02

ENET_RX_CLK

0x03

ENET_TX_CLK

0x04

GP_CLKIN

0x06

Crystal oscillator

0x07

PLL0USB

0x08

PLL0AUDIO

0x09

PLL1

-

Reserved

13.6.7 Integer divider register B, C, D
Table 139. IDIVB/C/D control registers (IDIVB_CTRL, address 0x4005 004C; IDIVC_CTRL,
address 0x4005 0050; IDIVC_CTRL, address 0x4005 0054) bit description
Bit

Symbol

0

PD

Value

Description

Reset
value

Access

Integer divider power down

0

R/W

0

Enabled. IDIV enabled (default)

1

Power-down

1

-

Reserved

-

-

5:2

IDIV

Integer divider B, C, D divider values
(1/(IDIV + 1))

0000

R/W

-

-

0000 = 1 (default)
0001 = 2
...
1111 = 16
10:6
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-

Reserved
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Chapter 13: LPC43xx/LPC43Sxx Clock Generation Unit (CGU)

Table 139. IDIVB/C/D control registers (IDIVB_CTRL, address 0x4005 004C; IDIVC_CTRL,
address 0x4005 0050; IDIVC_CTRL, address 0x4005 0054) bit description
Bit

Symbol

Value

11

AUTOBLOCK

Description

Reset
value

Block clock automatically during frequency 0
change
0

Disabled. Autoblocking disabled

1

Enabled. Autoblocking enabled

Access
R/W

23:12

-

Reserved

-

-

28:24

CLK_SEL

Clock-source selection. All other values
are reserved.

0x01

R/W

-

-

0x00

31:29

32 kHz oscillator

0x01

IRC (default)

0x02

ENET_RX_CLK

0x03

ENET_TX_CLK

0x04

GP_CLKIN

0x06

Crystal oscillator

0x08

PLL0AUDIO

0x09

PLL1

0x0C

IDIVA

-

Reserved

13.6.8 Integer divider register E
Table 140. IDIVE control register (IDIVE_CTRL, address 0x4005 0058) bit description
Bit

Symbol

0

PD

Value

Description

Reset
value

Access

Integer divider power down

0

R/W

0

Enabled. IDIV enabled (default)

1

Power-down

1

-

Reserved

-

-

9:2

IDIV

Integer divider E divider values
(1/(IDIV + 1))

000000
00

R/W

-

-

00000000 = 1 (default)
00000001 = 2
...
111111111 = 256
10

-

Reserved

11

AUTOBLOCK

Block clock automatically during frequency 0
change

23:12

UM10503

User manual

-

0

Disabled. Autoblocking disabled

1

Enabled. Autoblocking enabled
Reserved

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Chapter 13: LPC43xx/LPC43Sxx Clock Generation Unit (CGU)

Table 140. IDIVE control register (IDIVE_CTRL, address 0x4005 0058) bit description
Bit

Symbol

28:24

CLK_SEL

31:29

Value

Description

Reset
value

Clock-source selection. All other values are 0x01
reserved.
0x00

32 kHz oscillator

0x01

IRC (default)

0x02

ENET_RX_CLK

0x03

ENET_TX_CLK

0x04

GP_CLKIN

0x06

Crystal oscillator

0x08

PLL0AUDIO

0x09

PLL1

0x0C

IDIVA

-

Reserved

-

Access
R/W

-

13.6.9 BASE_SAFE_CLK control register
This register controls the BASE_SAFE_CLK to the watchdog oscillator. The only possible
clock source for this base clock is the IRC.
Table 141. BASE_SAFE_CLK control register (BASE_SAFE_CLK, address 0x4005 005C) bit
description
Bit

Symbol

0

PD

Value

Description

Reset
value

Access

Output stage power down

0

R

-

-

0

Enabled. Output stage enabled (default)

1

Power-down

10:1

-

Reserved

11

AUTOBLOCK

Block clock automatically during frequency 0
change
0

Disabled. Autoblocking disabled

1

Enabled. Autoblocking enabled

R

23:12

-

Reserved

-

-

28:24

CLK_SEL

Clock source selection. All other values
are reserved.

0x01

R

31:29

-

-

-

0x01

IRC (default)
Reserved

13.6.10 BASE_USB0_CLK control register
This register controls the BASE_USB0_CLK to the High-speed USB0. The only possible
clock source for this base clock is the PLL0USB output.

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Chapter 13: LPC43xx/LPC43Sxx Clock Generation Unit (CGU)

Table 142. BASE_USB0_CLK control register (BASE_USB0_CLK, address 0x4005 0060) bit
description
Bit

Symbol

0

PD

Value

Description

Reset
value

Access

Output stage power down

0

R/W

0

Enabled. Output stage enabled (default)

1

Power-down

10:1

-

Reserved

-

-

11

AUTOBLOCK

Block clock automatically during frequency
change

0

R/W

0

Disabled. Autoblocking disabled

1

Enabled. Autoblocking enabled

23:12

-

Reserved

-

-

28:24

CLK_SEL

Clock-source selection.

0x07

R/W

31:29

-

-

-

0x07

PLL0USB (default)
Reserved

13.6.11 BASE_PERIPH_CLK control register
This register controls base clock 2 to the SGPIO block.
Table 143. BASE_PERIPH_CLK control register (BASE_PERIPH_CLK, address 0x4005 0064)
bit description
Bit

Symbol

0

PD

User manual

Description

Reset
value

Access

Output stage power down

0

R/W

-

-

0

Enabled. Output stage enabled (default)

1

Power-down

10:1

-

Reserved

11

AUTOBLOCK

Block clock automatically during frequency 0
change

23:12

UM10503

Value

-

0

Disabled. Autoblocking disabled

1

Enabled. Autoblocking enabled
Reserved

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Chapter 13: LPC43xx/LPC43Sxx Clock Generation Unit (CGU)

Table 143. BASE_PERIPH_CLK control register (BASE_PERIPH_CLK, address 0x4005 0064)
bit description …continued
Bit

Symbol

28:24

CLK_SEL

31:29

Value

Description

Reset
value

Clock source selection. All other values are 0x01
reserved.
0x00

32 kHz oscillator

0x01

IRC (default)

0x02

ENET_RX_CLK

0x03

ENET_TX_CLK

0x04

GP_CLKIN

0x06

Crystal oscillator

0x08

PLL0AUDIO

0x09

PLL1

0x0C

IDIVA

0x0D

IDIVB

0x0E

IDIVC

0x0F

IDIVD

0x10

IDIVE

-

Reserved

-

Access
R/W

-

13.6.12 BASE_USB1_CLK control register
These registers control base clocks 3 (USB1).
Table 144. BASE_USB1_CLK control register (BASE_USB1_CLK, address 0x4005 0068) bit
description
Bit

Symbol

0

PD

User manual

Description

Reset
value

Access

Output stage power down

0

R/W

-

-

0

Enabled. Output stage enabled (default)

1

Power-down

10:1

-

Reserved

11

AUTOBLOCK

Block clock automatically during frequency 0
change

23:12

UM10503

Value

-

0

Disabled. Autoblocking disabled

1

Enabled. Autoblocking enabled
Reserved

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Chapter 13: LPC43xx/LPC43Sxx Clock Generation Unit (CGU)

Table 144. BASE_USB1_CLK control register (BASE_USB1_CLK, address 0x4005 0068) bit
description …continued
Bit

Symbol

28:24

CLK_SEL

31:29

Value

Description

Reset
value

Clock source selection. All other values are 0x01
reserved.
0x00

32 kHz oscillator

0x01

IRC (default)

0x02

ENET_RX_CLK

0x03

ENET_TX_CLK

0x04

GP_CLKIN

0x06

Crystal oscillator

0x07

PLL0USB

0x08

PLL0AUDIO

0x09

PLL1

0x0C

IDIVA

0x0D

IDIVB

0x0E

IDIVC

0x0F

IDIVD

0x10

IDIVE

-

Reserved

-

Access
R/W

-

13.6.13 BASE_M4_CLK to BASE_UART3_CLKcontrol registers
These registers control base clocks 4 to 19.
Table 145. BASE_M4_CLK to BASE_UART3_CLK control registers (BASE_M4_CLK to
BASE_UART3_CLK, address 0x4005 006C to 0x4005 00A8) bit description
Bit

Symbol

0

PD

User manual

Description

Reset
value

Access

Output stage power down

0

R/W

-

-

0

Enabled. Output stage enabled (default)

1

power-down

10:1

-

Reserved

11

AUTOBLOCK

Block clock automatically during frequency 0
change

23:12

UM10503

Value

-

0

Disabled. Autoblocking disabled

1

Enabled. Autoblocking enabled
Reserved

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Chapter 13: LPC43xx/LPC43Sxx Clock Generation Unit (CGU)

Table 145. BASE_M4_CLK to BASE_UART3_CLK control registers (BASE_M4_CLK to
BASE_UART3_CLK, address 0x4005 006C to 0x4005 00A8) bit description
Bit

Symbol

28:24

CLK_SEL

31:29

Value

Description

Reset
value

Clock source selection. All other values are 0x01
reserved.
0x00

32 kHz oscillator

0x01

IRC (default)

0x02

ENET_RX_CLK

0x03

ENET_TX_CLK

0x04

GP_CLKIN

0x06

Crystal oscillator

0x08

PLL0AUDIO

0x09

PLL1

0x0C

IDIVA

0x0D

IDIVB

0x0E

IDIVC

0x0F

IDIVD

0x10

IDIVE

-

Reserved

-

Access
R/W

-

13.6.14 BASE_OUT_CLK register
This register controls the clock output to the CLKOUT pin. All clock generator outputs can
be monitored through this pin.
Table 146. BASE_OUT_CLK control register BASE_OUT_CLK, addresses 0x4005 00AC) bit
description
Bit

Symbol

0

PD

User manual

Description

Reset
value

Access

Output stage power down

0

R/W

-

-

0

Enabled. Output stage enabled (default)

1

Power-down

10:1

-

Reserved

11

AUTOBLOCK

Block clock automatically during frequency 0
change

23:12

UM10503

Value

-

0

Disabled. Autoblocking disabled

1

Enabled. Autoblocking enabled
Reserved

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Chapter 13: LPC43xx/LPC43Sxx Clock Generation Unit (CGU)

Table 146. BASE_OUT_CLK control register BASE_OUT_CLK, addresses 0x4005 00AC) bit
description …continued
Bit

Symbol

28:24

CLK_SEL

31:29

Value

Description

Reset
value

Access

Clock-source selection.

0x01

R/W

0x00

32 kHz oscillator

0x01

IRC (default)

0x02

ENET_RX_CLK

0x03

ENET_TX_CLK

0x04

GP_CLKIN

0x05

Reserved

0x06

Crystal oscillator

-

-

0x07

PLL0USB

0x08

PLL0AUDIO

0x09

PLL1

0x0C

IDIVA

0x0D

IDIVB

0x0E

IDIVC

0x0F

IDIVD

0x10

IDIVE

-

Reserved

13.6.15 BASE_AUDIO_CLK register
Table 147. BASE_AUDIO_CLK control register (BASE_AUDIO_CLK, addresses 0x4005 00C0)
bit description
Bit

Symbol

0

PD

User manual

Description

Reset
value

Access

Output stage power down

0

R/W

-

-

0

Enabled. Output stage enabled (default)

1

Power-down

10:1

-

Reserved

11

AUTOBLOCK

Block clock automatically during frequency 0
change

23:12

UM10503

Value

-

0

Disabled. Autoblocking disabled

1

Enabled. Autoblocking enabled
Reserved

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Chapter 13: LPC43xx/LPC43Sxx Clock Generation Unit (CGU)

Table 147. BASE_AUDIO_CLK control register (BASE_AUDIO_CLK, addresses 0x4005 00C0)
bit description …continued
Bit

Symbol

28:24

CLK_SEL

31:29

Value

Description

Reset
value

Access

Clock-source selection.

0x01

R/W

0x00

32 kHz oscillator

0x01

IRC (default)

0x02

ENET_RX_CLK

0x03

ENET_TX_CLK

0x04

GP_CLKIN

0x05

Reserved

0x06

Crystal oscillator

0x07

Reserved

0x08

PLL0AUDIO

0x09

PLL1

0x0C

IDIVA

0x0D

IDIVB

0x0E

IDIVC

0x0F

IDIVD

0x10

IDIVE
-

-

-

Reserved

13.6.16 BASE_CGU_OUT0_CLK to BASE_CGU_OUT1_CLK register
This register controls the clock output to the spare CGU outputs pins CGU_OUT0 and
CGU_OUT1. All clock generator outputs can be monitored through this pin.
Table 148. BASE_CGU_OUT0_CLK to BASE_CGU_OUT1_CLK control register
(BASE_CGU_OUT0_CLK to BASE_CGU_OUT1_CLK, addresses 0x4005 00C4 to
0x4005 00C8) bit description
Bit

Symbol

0

PD

User manual

Description

Reset
value

Access

Output stage power down

0

R/W

-

-

0

Enabled. Output stage enabled (default)

1

Power-down

10:1

-

Reserved

11

AUTOBLOCK

Block clock automatically during frequency 0
change

23:12

UM10503

Value

-

0

Disabled. Autoblocking disabled

1

Enabled. Autoblocking enabled
Reserved

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Chapter 13: LPC43xx/LPC43Sxx Clock Generation Unit (CGU)

Table 148. BASE_CGU_OUT0_CLK to BASE_CGU_OUT1_CLK control register
(BASE_CGU_OUT0_CLK to BASE_CGU_OUT1_CLK, addresses 0x4005 00C4 to
0x4005 00C8) bit description …continued
Bit

Symbol

28:24

CLK_SEL

31:29

-

Value

Description

Reset
value

Access

Clock-source selection.

0x01

R/W

-

-

0x00

32 kHz oscillator

0x01

IRC (default)

0x02

ENET_RX_CLK

0x03

ENET_TX_CLK

0x04

GP_CLKIN

0x05

Reserved

0x06

Crystal oscillator

0x07

PLL0USB

0x08

PLL0AUDIO

0x09

PLL1

0x0C

IDIVA

0x0D

IDIVB

0x0E

IDIVC

0x0F

IDIVD

0x10

IDIVE
Reserved

13.7 Functional description
13.7.1 32 kHz oscillator
The 32 kHz oscillator output is controlled by the CREG block (see Table 96). The RTC
and the Alarm timer are connected directly to the 32 kHz oscillator.

13.7.2 IRC
The IRC is a trimmed 12 MHz internal oscillator. Although the IRC is part of the CGU, the
CGU has no control over this clock source. The IRC is put into power down depending on
the power saving mode.

13.7.3 Crystal oscillator
The crystal oscillator is controlled by the XTAL_OSC_CTRL register in the CGU (see
Table 126).

13.7.4 PLL0 (PLL0USB and PLL0AUDIO)
The PLL blocks of the PLL0USB and PLL0AUDIO are identical. The PLL0AUDIO
supports an additional fractional divider to obtain more PLL frequencies with higher
accuracy for audio applications.

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Chapter 13: LPC43xx/LPC43Sxx Clock Generation Unit (CGU)

13.7.4.1 Features

• Input frequency: 14 kHz to 150 MHz. The input from an external crystal is limited to
25 MHz.

• CCO frequency: 275 MHz to 550 MHz.
• Output clock range: 4.3 MHz to 550 MHz.
• Programmable dividers:
– Pre-divider N (N, 1 to 28)
– Feedback-divider 2 x M (M, 1 to 215)
– Post-divider P x 2 (P, 1 to 25).

• Programmable bandwidth (integrating action, proportional action, high frequency
pole).

•
•
•
•
•
•

On-the-fly adjustment of the clock possible (dividers with handshake control).
Positive edge clocking.
Frequency limiter to avoid hang-up of the PLL.
Lock detector.
Power-down mode.
Free running mode

Remark: Both PLL0 blocks are functionally identical. The PLL0 for audio applications
(PLL0 for audio) supports an additional fractional divider stage (see Section 13.7.5).

13.7.4.2 PLL0 description
The block diagram of the PLL0 is shown in Figure 38. The clock input has to be fed to pin
clkin. Pin clkout is the PLL0 clock output. The analog part of the PLL consists of a Phase
Frequency Detector (PFD), filter and a Current Controlled Oscillator (CCO). The PFD has
two inputs, a reference input from the (divided) external clock and one input from the
divided CCO output clock. The PFD compares the phase/frequency of these input signals
and generates a control signal if they don’t match. This control signal is fed to a filter
which drives the CCO.

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Chapter 13: LPC43xx/LPC43Sxx Clock Generation Unit (CGU)

Bypass
CTRL[1]

Direct Output
CTRL[3]

32kHz
IRC
ENET_RX_CLK
ENET_TX_CLK
GP_CLKIN
CRYSTAL
PLL1
IDIVA
IDIVB
IDIVC
IDIVD
IDIVE

CLKOUT
Q

N-DIVIDER

PFD

Filter

P-DIVIDER

CCO

D

/2

CLKIN
“1”

Bandwidth Select P,I,R
MDIV[31:17]

NP_DIV[21:12]
Direct Input
CTRL[2]

NP_DIV[6:0]

/2

M-DIVIDER

CLKEN
CTRL[4]

CTRL[27:24]
MDIV[16:0]

Fig 38. PLL0 block diagram

The PLL contains three programmable dividers: pre-divider (N), feedback-divider (M) and
post-divider (P). The PLL contains a lock detector which measures the phase difference
between the rising edges of the input and feedback clocks. Only when this difference is
smaller than the so called “lock criterion” for more than seven consecutive input clock
periods, the lock output switches from low to high. A single too large phase difference
immediately resets the counter and causes the lock signal to drop (if it was high).
Requiring seven phase measurements in a row to be below a certain figure ensures that
the lock detector will not indicate lock until both the phase and frequency of the input and
feedback clocks are very well aligned. This effectively prevents false lock indications, and
thus ensures a glitch free lock signal.
To avoid frequency hang-up the PLL contains a frequency limiter. This feature is built in to
prevent the CCO from running too fast, this can occur if e.g. a wrong feedback-divider (M)
ratio is applied to the PLL.
Remark: The PLL0 does not use the direct binary representations of M, N, and P directly.
Instead, encoded versions MDEC, NDEC, and PDEC of M, N, and P respectively.
See Section 13.6.3.3 and Section 13.6.3.4 for how to obtain the encoded values for M, N,
and P.

13.7.4.3 Use of PLL0 operating modes
Table 149. PLL0 operating modes
PLL0_Mode bit settings:

13.7.4.3.1

Mode

PD

CLKEN

BYPASS

DIRECTI

DIRECTO

FRM

1: Normal

0

1

0

1/0

1/0

0

3: Power Down

1

x

x

x

x

x

Normal Mode
Mode 1 is the normal operating mode.
The pre- and post-divider can be selected to give:

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Chapter 13: LPC43xx/LPC43Sxx Clock Generation Unit (CGU)

•
•
•
•

mode 1a: Normal operating mode without post-divider and without pre-divider
mode 1b: Normal operating mode with post-divider and without pre-divider
mode 1c: Normal operating mode without post-divider and with pre-divider
mode 1d: Normal operating mode with post-divider and with pre-divider

To get at the output of the PLL (clkout) the best phase-noise and jitter performance, the
highest possible reference clock (clkref) at the PFD has to be used. Therefore mode 1a
and 1b are recommended, when it is possible to make the right output frequency without
pre-divider.
By using the post-divider the clock at the output of the PLL (clkout) the divider ratio is
always even because the divide-by-2 divider after the post-divider.
Table 150. DIRECTL and DIRECTO bit settings in HP0/1_Mode register

13.7.4.3.2

Mode

DIRECTI

DIRECTO

1a

1

1

1b

1

0

1c

0

1

1d

0

0

Mode 1a: Normal operating mode without post-divider and without pre-divider
In normal operating mode 1a the post-divider and pre-divider are bypassed. The operating
frequencies are:
Fout = Fcco = 2 x M x Fin (275 MHz Fcco 550 MHz, 4 kHz  Fin 150 MHz)
The feedback divider ratio is programmable:

• Feedback-divider M (M, 1 to 215)
13.7.4.3.3

Mode 1b: Normal operating mode with post-divider and without pre-divider
In normal operating mode 1b the pre-divider is bypassed. The operating frequencies are:
Fout = Fcco /(2 x P) = (M / P) x Fin  (275 MHz Fcco 550 MHz, 4 kHz Fin  150 MHz)
The divider ratios are programmable:

• Feedback-divider M (M, 1 to 215)
• Post-divider P (P, 1 to 32)
13.7.4.3.4

Mode 1c: Normal operating mode without post-divider and with pre-divider
In normal operating mode 1c the post-divider with divide-by-2 divider is bypassed. The
operating frequencies are:
Fout = Fcco = 2 x M x Fin / N  (275 MHz Fcco 550 MHz, 4 kHz Fin/N 150 MHz)
The divider ratios are programmable:

• Pre-divider N (N, 1 to 256)
• Feedback-divider M (M, 1 to 215)

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Chapter 13: LPC43xx/LPC43Sxx Clock Generation Unit (CGU)

13.7.4.3.5

Mode 1d: Normal operating mode with post-divider and with pre-divider
In normal operating mode 1d none of the dividers are bypassed. The operating
frequencies are:
Fout = Fcco /(2 x P) = M x Fin /(N x P)  (275 MHz Fcco 550 MHz, 4 kHz Fin/N 150
MHz)
The divider ratios are programmable:

• Pre-divider N (N, 1 to 256)
• Feedback-divider M (M, 1 to 215)
• Post-divider P (P, 1 to 32)
13.7.4.3.6

Mode 3: Power down mode (pd)
In this mode (pd = '1'), the oscillator will be stopped, the lock output will be made low, and
the internal current reference will be turned off. During pd it is also possible to load new
divider ratios at the input buses (msel, psel, nsel). Power-down mode is ended by making
pd low, causing the PLL to start up. The lock signal will be made high once the PLL has
regained lock on the input clock.

13.7.4.4 Settings for USB0
Table 151 shows the divider settings used for configuring an output frequency Fout of
480 MHz for USB0.

13.7.4.5 Usage notes
In order to set up the PLL0, follow these steps:
1. Power down the PLL0 by setting bit 0 in the PLL0 control register (PLL0USB_CTRL or
PLL0AUDIO_CTRL) to 1. This step is only needed if the PLL0 is currently enabled.
2. Configure the PLL0 m, n, and p divider values in the PLL0_M and PLL0_NP registers.
3. Power up the PLL0 by setting bit 0 in the PLL0 control (PLL0USB_CTRL or
PLL0AUDIO_CTRL) register to 0.
4. Wait for the PLL0 to lock by monitoring the LOCK bit in the PLL0_STAT register.
5. Enable the PLL0 clock output in the PLL0_CTRL register.
Remark: You can change the PLL0 settings while the PLL0 is running when you need to
configure the PLL0 for high output frequencies (see Section 13.2.1).

13.7.5 Fractional divider for PLL0AUDIO
The PLL0 for audio applications (PLL0AUDIO) includes an additional fractional divider.
The SEL_EXT bit in the PLL0AUDIO control register determines whether the fractional
divider is used (SEL_EXT=0) or bypassed (SEL_EXT=1). In the latter case, PLL0AUDIO
operates exactly as PLL0USB and the MDEC value is used directly to control the
feedback divider.
When the fractional divider is active, the sigma-delta modulator block generates divider
values M and M+1 in the correct proportion so that an average division ratio of M+K/L is
realized where 0<=K<=L and M, K, and L are integer values. M Is determined by the
integer part of the PLLFRACT_CTRL register (PLLFRACT[21:15]) and K is determined by
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Chapter 13: LPC43xx/LPC43Sxx Clock Generation Unit (CGU)

the fractional part of the PLLFRACT_CTRL register (PLLFRACT[14:0]). Consecutive M
and M+1 values are then further encoded into appropriate MENC values before being
presented as input to the M-divider.

Direct Output
CTRL[3]

PLL0AUDIO

32kHz
IRC
ENET_RX_CLK
ENET_TX_CLK
GP_CLKIN
CRYSTAL
PLL1
IDIVA
IDIVB
IDIVC
IDIVD
IDIVE

Bypass
CTRL[1]

FOUT
Q

N-DIVIDER

PFD

Filter

P-DIVIDER

CCO

D

/2

CLKIN
“1”

Bandwidth Select P,I,R
MDIV[31:17]

NP_DIV[21:12]
Direct Input
CTRL[2]

M-DIVIDER

NP_DIV[6:0]

/2

CTRL[27:24]

PLL0AUDIO
FRACTIONAL DIVIDER

CLKEN
CTRL[4]

SEL_EXT

DECODER
ΣΔ MODULATOR

FRAC[21:0]
CTRL[12] (PLLFRACT_REQ)

MDIV[16:0]

Fig 39. PLL0 with fractional divider

13.7.6 PLL1
13.7.6.1 Features

• 1 MHz to 50 MHz input frequency. The input from an external crystal is limited to
25 MHz.

•
•
•
•

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9.75 MHz to 320 MHz selectable output frequency with 50% duty cycle.
156 MHz to 320 MHz Current Controlled Oscillator (CCO) frequency.
Power-down mode.
Lock detector.

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13.7.6.2 PLL1 description

FCLKIN

P-divider

CCO

/N

pd

FCCO
PSEL<1:0>

2
NSEL<1:0>

PFD

2
pd
LOCK
DETECT

0

LOCK

1
BYPASS

cd

÷2xP

0

FCLKOUT

1
DIRECT

analog section

FCLKIN
pd
cd

/M

0
1

8
MSEL<7:0>

FBSEL

Fig 40. PLL1 block diagram

The block diagram of this PLL is shown in Figure 40. The input frequency range is 10 MHz
to 25 MHz. The input clock is fed directly to the Phase-Frequency Detector (PFD). This
block compares the phase and frequency of its inputs, and generates a control signal
when phase and/ or frequency do not match. The loop filter filters these control signals
and drives the current controlled oscillator (CCO), which generates the main clock. The
CCO frequency range is 156 MHz to 320 MHz.These clocks are either divided by 2xP by
the programmable post divider to create the output clocks, or are sent directly to the
outputs. The main output clock is then divided by M by the programmable feedback
divider to generate the feedback clock. The output signal of the phase-frequency detector
is also monitored by the lock detector, to signal when the PLL has locked on to the input
clock.

13.7.6.3 Lock detector
The lock detector measures the phase difference between the rising edges of the input
and feedback clocks. Only when this difference is smaller than the so called “lock
criterion” for more than eight consecutive input clock periods, the lock output switches
from low to high. A single too large phase difference immediately resets the counter and
causes the lock signal to drop (if it was high). Requiring eight phase measurements in a
row to be below a certain figure ensures that the lock detector will not indicate lock until
both the phase and frequency of the input and feedback clocks are very well aligned. This
effectively prevents false lock indications, and thus ensures a glitch free lock signal.

13.7.6.4 Power-down control
To reduce the power consumption when the PLL clock is not needed, a Power-down
mode has been incorporated. In this mode, the internal current reference will be turned
off, the oscillator and the phase-frequency detector will be stopped and the dividers will
enter a reset state. While in Power-down mode, the lock output will be low to indicate that

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the PLL is not in lock. When the Power-down mode is terminated, the PLL will resume its
normal operation and will make the lock signal high once it has regained lock on the input
clock.

13.7.6.5 Selectable feedback divider clock
To allow a trade-off to be made between functionality and power consumption, the
feedback divider can be connected to either the CCO clock by setting FBSEL to 0 or to the
output clock by setting FBSEL to 1. If the post-divider is used to divide down the CCO
clock the current consumption of the feedback divider can be reduced by making it run on
the lower output clock instead of the CCO clock, but doing so will limit the relation
between output and phase detector clock frequencies to integer values.

13.7.6.6 Direct output mode
In normal operating mode (with DIRECT set to 0) the CCO clock is divided by 2, 4, 8 or 16
depending on the value of PSEL[1:0], automatically giving an output clock with a 50%
duty cycle. If a higher output frequency is needed, the CCO clock can be sent directly to
the output by setting DIRECT to 1. Since the CCO was designed to directly generate a
clock with a 50% duty cycle, the output clock duty cycle will also be 50% in direct mode.

13.7.6.7 Divider ratio programming
Pre-divider
The pre-divider’s division ratio is controlled by the NSEL[1:0] input. The division ratio
between PLL’s input clock and the phase detector clock is the decimal value on NSEL[1:0]
plus one.
Post-divider
The division ratio of the post divider is controlled by the PSEL bits. The division ratio is two
times the value of P selected by PSEL bits. This guarantees an output clock with a 50%
duty cycle.
Feedback divider
The feedback divider’s division ratio is controlled by the MSEL bits. The division ratio
between the PLL’s output clock and the input clock is the decimal value on MSEL bits plus
one.

13.7.6.8 Frequency selection
The PLL frequency equations use the following parameters (also see Figure 40):
Integer mode
In this mode the post divider is enabled and the feedback divider is set to run on the PLL
output clock, giving the following frequency relations:
(1)
FCLKIN
FCLKOUT = M  ---------------------N

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(2)
FCLKIN
FCCO = 2  P  FCLKOUT = 2  P  M  ---------------------N

Non-integer mode
In this mode the post-divider is enabled and the feedback divider is set to run directly on
the CCO clock, which gives the following frequency dividers:
(3)
FCCO
M
FCLKIN
FCLKOUT = ----------------- = ------------  ---------------------2P
2P
N

(4)
FCLKIN
FCCO = M  ---------------------N

Direct mode
In this mode, the post-divider is disabled and the CCO clock is sent directly to the output,
leading to the following frequency equation:
(5)
FCLKIN
FCLKOUT = FCCO = M  ---------------------N

Power-down mode
In this mode, the internal current reference will be turned off, the oscillator and the
phase-frequency detector will be stopped and the dividers will enter a reset state. While in
Power-down mode, the lock output will be low, to indicate that the PLL is not in lock. When
the Power-down mode is terminated, the PLL will resume its normal operation and will
make the lock signal high once it has regained lock on the input clock.

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Chapter 13: LPC43xx/LPC43Sxx Clock Generation Unit (CGU)

13.8 Example CGU configurations
13.8.1 Programming the CGU for Deep-sleep and Power-down modes
Before the LPC43xx enters Deep-sleep or Power-down mode, the IRC must be
programmed as the clock source in the control registers for all output stages (OUTCLK_0
to OUTCLK_27). In addition, the PLLs must be in Power-down mode.
When the LPC43xx wakes up from Deep-sleep or Power-down mode, the IRC is used as
the clock sources for all output stages. Also see Chapter 12.

13.8.2 Programming the CGU for using I2S at peripheral clock rate of
30 MHz
In this example the peripheral clock of the I2S interface is set to 30 MHz. The peripheral
I2S clock is a branch of the BASE_APB1_CLK. Using a crystal of 12 MHz as clock source,
a PLL1 multiplier of 10, and an integer divider of 4 provide the desired clock rate.

XTAL_OSC

12MHz

PLL1 x 10

120MHz

DIVA / 4

30MHz

BASE_APB1_CLK

For this example, program the CGU as follows:
1. Enable the crystal oscillator in the XTAL_OSC_CTRL register (Table 126).
2. Wait for the crystal to stabilize.
3. Select the crystal oscillator as input to the PLL1 and set up the divider in the
PLL1_CTRL register (see Table 137):
– Set bits CLK_SEL in the PLL1_CTRL register to 0x6.
– Set MSEL = 9.
– Set NSEL = 0.
– Set PSEL = 1.
– Set FBSEL = 1.
– Set BYPASS = 0, DIRECT = 0.
4. Wait for the PLL1 to lock.
5. Select the PLL1 as clock source of the integer divider A (IDIVA) in the IDIVA register
and set AUTOBLOCK = 1 (see Table 137).
6. Select IDIVA as clock source of the base clock BASE_APB1_CLK and set
AUTOBLOCK = 1 (see Table 138).
7. Ensure that the I2S branch clock CLK_APB1_I2S is enabled in the CCU (see
Table 157).

13.8.3 PLL0USB settings for USB applications
Table 151 shows examples of the M-divider and NP-divider register settings that produce
a 480 MHz output clock for the USB0.
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Table 151. PLL0 (for USB) settings for 480 MHz output clock
Fclkin [MHz]

PLL0USB_MDIV

PLL0USB_NP_DIV

Table 129

Table 130

1

0x073E 56C9

0x0030 2062

2

0x073E 2DAD

0x0030 2062

3

0x0B3E 34B1

0x0030 2062

4

0x0E3E 7777

0x0030 2062

5

0x0D32 6667

0x0030 2062

6

0x0B2A 2A66

0x0030 2062

8

0x0820 6AAA

0x0030 2062

10

0x071A 7FAA

0x0030 2062

12

0x0616 7FFA

0x0030 2062

15

0x0512 3FFF

0x0030 2062

16

0x0410 1FFF

0x0030 2062

20

0x040E 03FF

0x0030 2062

24

0x030C 00FF

0x0030 2062

13.8.4 PLL0AUDIO settings for audio applications
13.8.4.1 Using the fractional divider
Table 152 shows typical divider settings for the audio PLL0 with the fractional divider
active.
To use the fractional divider, follow these steps:
1. Set bit SEL_EXT = 0 and PLLFRACT_REQ = 1 in the PLL0AUDIO_CTRL register
(Table 132).
2. Calculate NDEC, PDEC, and PLLFRACT_CTRL for the output frequency Fout.
3. Write the calculated NDEC and PDEC values to the PLL0AUDIO_NP_DIV register.
4. Write the calculated PLLFRACT_CTRL value to the PLL0AUDIOFRAC register.
Table 152. PLL0AUDIO divider settings for 12 MHz input
Fs [kHz]

Fout [MHz] Fcco [MHz] Error [Hz]

NDEC

PDEC

PLL0AUDIO_NP_DIV

PLLF0RACT_CTRL

Table 134

Table 135

128Fs
192

24.576

540.672

1

514

29

0x0000201d

0x16872b

96

12.288

417.792

1

1

3

0x00001003

0x1a1cac

88.2

11.2896

338.688

1

0

24

0x00000018

0x070e56

64

8.192

344.064

1

0

30

0x0000001e

0x072b02

48

6.144

307.2

1

1

6

0x00001006

0x133333

44.1

5.6448

282.24

1

1

6

0x00001006

0x11a3d7

192

49.152

491.52

11

514

5

0x00002005

0x147ae1

96

24.576

540.672

1

514

29

0x0000201d

0x16872b

88.2

22.5792

451.584

1

1

14

0x0000100e

0x1c3958

256Fs

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Chapter 13: LPC43xx/LPC43Sxx Clock Generation Unit (CGU)

Table 152. PLL0AUDIO divider settings for 12 MHz input
Fs [kHz]
64

Fout [MHz] Fcco [MHz] Error [Hz]
16.384

360.448

1

NDEC
1

PDEC
29

PLL0AUDIO_NP_DIV

PLLF0RACT_CTRL

Table 134

Table 135

0x0000101d

0x16872b

48

12.288

417.792

1

1

3

0x00001003

0x1a1cac

44.1

11.2896

338.688

1

0

24

0x00000018

0x070e56

32

8.192

344.064

1

0

30

0x0000001e

0x072b02

24

6.144

307.2

1

1

6

0x00001006

0x133333

22.05

5.6448

282.24

1

1

6

0x00001006

0x11a3d7

192

73.728

442.368

4

2

0x00002001

0x24dd2f

96

36.864

442.368

2

2

0x0000200a

0x24dd2f

88.2

33.8688

338.688

2

0

0x00000005

0x070e56

64

24.576

540.672

1

514

0x0000201d

0x16872b

48

18.432

442.368

1

2

0x0000201b

0x24dd2f

44.1

16.9344

338.688

1

0

0x0000000e

0x070e56

32

12.288

417.792

1

1

0x00001003

0x1a1cac

24

9.216

276.48

1

1

0x00001018

0x1147ae

22.05

8.4672

338.688

1

0

0x0000001f

0x070e56

16

6.144

307.2

1

1

0x00001006

0x133333

12

4.608

276.48

1

1

0x00001012

0x1147ae

192

98.304

393.216

30

2

66

0x00002042

0x20c49b

96

49.152

491.52

11

514

5

0x00002005

0x147ae1

88.2

45.1584

451.584

2

1

5

0x00001005

0x1c3958

64

32.768

458.752

4

1

21

0x00001015

0x1cac08

48

24.576

540.672

1

514

29

0x0000201d

0x16872b

44.1

22.5792

451.584

1

1

14

0x0000100e

0x1c3958

384Fs

512Fs

32

16.384

360.448

1

1

29

0x0000101d

0x16872b

24

12.288

417.792

1

1

3

0x00001003

0x1a1cac

22.05

11.2896

338.688

1

0

24

0x00000018

0x070e56

16

8.192

344.064

1

0

30

0x0000001e

0x072b02

12

6.144

307.2

1

1

6

0x00001006

0x133333

11.025

5.6448

282.24

1

1

6

0x00001006

0x11a3d7

196.608

393.216

60

2

98

0x00002062

0x20c49b

1024Fs
192
96

98.304

393.216

30

2

66

0x00002042

0x20c49b

88.2

90.3168

541.9008

28

0

1

0x00000001

0x0b4a23

64

65.536

524.288

13

2

2

0x00002002

0x2bb0cf

48

49.152

491.52

11

514

5

0x00002005

0x147ae1

44.1

45.1584

451.584

2

1

5

0x00001005

0x1c3958

32

32.768

458.752

4

1

21

0x00001015

0x1cac08

24

24.576

540.672

1

514

29

0x0000201d

0x16872b

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Chapter 13: LPC43xx/LPC43Sxx Clock Generation Unit (CGU)

Table 152. PLL0AUDIO divider settings for 12 MHz input
Fs [kHz]

Fout [MHz] Fcco [MHz] Error [Hz]

22.05

22.5792

451.584

1

NDEC
1

PDEC
14

PLL0AUDIO_NP_DIV

PLLF0RACT_CTRL

Table 134

Table 135

0x0000100e

0x1c3958

16

16.384

360.448

1

1

29

0x0000101d

0x16872b

12

12.288

417.792

1

1

3

0x00001003

0x1a1cac

11.025

11.2896

338.688

1

0

24

0x00000018

0x070e56

8

8.192

344.064

1

0

30

0x0000001e

0x072b02

13.8.4.1.1

Bypassing the fractional divider
To bypass the fractional divider and use the MDEC value directly, follow these steps:
1. Set bit SEL_EXT = 1 in the PLL0AUDIO_CTRL register (Table 132).
2. Calculate NDEC, PDEC, and MDEC for the output frequency Fout.
3. Write the calculated NDEC and PDEC values to the PLL0AUDIO_NP_DIV register.
4. Write the calculated MDEC value to the PLL0AUDIO_MDIV register.
Table 153. PLL0AUDIO divider setting for 12 MHz with fractional divider bypassed
Fs
[KHz]

Fout
[MHz]

Fcco
[MHz]

Error
PLL0AUDIO_
[Hz]
NDEC MDEC PDEC MDIV

PLL0AUDIO_
NP_DIV

Table 133

Table 134

128 Fs
192

24.576

491.52

0

63

13523

14

0x000034d3

0x0003f00e

96

12.288

368.64

0

63

2665

24

0x00000a69

0x0003f018

88.2

11.2896

338.688 0

45

18810

24

0x0000497a

0x0002d018

64

8.192

409.6

0

61

18724

6

0x00004924

0x0003d006

48

6.144

307.2

0

5

30580

6

0x00007774

0x00005006

44.1

5.6448

282.24

0

63

31356

6

0x00007a7c

0x0003f006

192

49.152

491.52

0

63

13523

5

0x000034d3

0x0003f005

96

24.576

491.52

0

63

13523

14

0x000034d3

0x0003f00e

88.2

22.5792 451.584 0

45

29122

14

0x000071c2

0x0002d00e

64

16.384

491.52

0

63

13523

24

0x000034d3

0x0003f018

48

12.288

368.64

0

63

2665

24

0x00000a69

0x0003f018

44.1

11.2896

338.688 0

45

18810

24

0x0000497a

0x0002d018

32

8.192

409.6

0

61

18724

6

0x00004924

0x0003d006

24

6.144

307.2

0

5

30580

6

0x00007774

0x00005006

22.05

5.6448

282.24

0

63

31356

6

0x00007a7c

0x0003f006

192

73.728

294.912 0

45

4770

66

0x000012a2

0x0002d042

96

36.864

368.64

0

63

2665

5

0x00000a69

0x0003f005

88.2

33.8688 338.688 0

45

18810

5

0x0000497a

0x0002d005

64

24.576

491.52

0

63

13523

14

0x000034d3

0x0003f00e

48

18.432

368.64

0

63

2665

14

0x00000a69

0x0003f00e

256 Fs

384 Fs

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Chapter 13: LPC43xx/LPC43Sxx Clock Generation Unit (CGU)

Table 153. PLL0AUDIO divider setting for 12 MHz with fractional divider bypassed
Fs
[KHz]

Fout
[MHz]

Fcco
[MHz]

Error
PLL0AUDIO_
[Hz]
NDEC MDEC PDEC MDIV

PLL0AUDIO_
NP_DIV

Table 133

Table 134

44.1

16.9344 338.688 0

45

18810

14

0x0000497a

0x0002d00e

32

12.288

368.64

0

63

2665

24

0x00000a69

0x0003f018

24

9.216

460.8

0

5

12733

6

0x000031bd

0x00005006

22.05

8.4672

423.36

0

63

17692

6

0x0000451c

0x0003f006

16

6.144

307.2

0

5

30580

6

0x00007774

0x00005006

12

4.608

276.48

0

63

1513

18

0x000005e9

0x0003f012

192

98.304

393.216 0

45

10784

66

0x00002a20

0x0002d042

96

49.152

491.52

0

63

13523

5

0x000034d3

0x0003f005

88.2

45.1584 451.584 0

45

29122

5

0x000071c2

0x0002d005

64

32.768

327.68

0

102

7482

5

0x00001d3a

0x00066005

48

24.576

491.52

0

63

13523

14

0x000034d3

0x0003f00e

512 Fs

44.1

22.5792 451.584 0

45

29122

14

0x000071c2

0x0002d00e

32

16.384

491.52

0

63

13523

24

0x000034d3

0x0003f018

24

12.288

368.64

0

63

2665

24

0x00000a69

0x0003f018

22.05

11.2896

338.688 0

45

18810

24

0x0000497a

0x0002d018

16

8.192

409.6

0

61

18724

6

0x00004924

0x0003d006

12

6.144

307.2

0

5

30580

6

0x00007774

0x00005006

11.025

5.6448

282.24

0

63

31356

6

0x00007a7c

0x0003f006

1024 Fs

UM10503

User manual

192

196.608 393.216 0

45

10784

98

0x00002a20

0x0002d062

96

98.304

45

10784

66

0x00002a20

0x0002d042

88.2

90.3168 541.901 31

181

3535

1

0x00000dcf

0x000b5001

64

65.536

393.216 0

45

10784

1

0x00002a20

0x0002d001

48

49.152

491.52

0

63

13523

5

0x000034d3

0x0003f005

44.1

45.1584 451.584 0

45

29122

5

0x000071c2

0x0002d005

32

32.768

327.68

0

102

7482

5

0x00001d3a

0x00066005

24

24.576

491.52

0

63

13523

14

0x000034d3

0x0003f00e

393.216 0

22.05

22.5792 451.584 0

45

29122

14

0x000071c2

0x0002d00e

16

16.384

491.52

0

63

13523

24

0x000034d3

0x0003f018

12

12.288

368.64

0

63

2665

24

0x00000a69

0x0003f018

11.025

11.2896

338.688 0

45

18810

24

0x0000497a

0x0002d018

8

8.192

409.6

61

18724

6

0x00004924

0x0003d006

0

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User manual

14.1 How to read this chapter
The ADCHS is only available on parts LPC4370/LPC43S70.
The Cortex-M0 subsystem core and the subsystem AHB multilayer matrix are only
enabled on parts LPC4370/LPC43S70 and LPC436x/LPC43S6x.
Flash/EEPROM, Ethernet, USB0, USB1, and LCD-related clocks are not available on all
parts and packages. See Table 2.

14.2 Basic configuration
The CCU1/2 are configured as follows:

•
•
•
•

See Table 154 for clocking and power control.
All branch clocks are enabled by default.
Do not reset the CCUs during normal operation.
Configure the output clock for the EMC clock divider (Table 163) together with bit 16 in
the CREG6 register (Table 104).

Table 154. CCU clocking and power control
Base clock

Branch clock

Operating frequency

CCU1

BASE_M4_CLK

CLK_M4_BUS

up to 204 MHz

CCU2

BASE_M4_CLK

CLK_M4_BUS

up to 204 MHz

Remark: The CCU registers for a given branch clock are only read and write accessible
when the branch clock is enabled.

14.3 Features
The CCUs switch the clocks to individual peripherals on or off.

• Auto mode activates the AHB disable protocol before switching off the branch clock.
• In Wake-up mode, clocks can be selected to run automatically after a wake-up event.

14.4 General description
Each CGU base clock has several clock branches which can be turned on or off
independently by the Clock Control Units CCU1 or CCU2. The branch clocks are
distributed between CCU1 and CCU2.

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Chapter 14: LPC43xx/LPC43Sxx Clock Control Unit (CCU)

Table 155. CCU1 branch clocks
Base clock

Branch clock

BASE_APB3_CLK CLK_APB3_BUS

Description
APB3 bus clock.

CLK_APB3_I2C1

Clock to the I2C1 register interface and I2C1
peripheral clock.

CLK_APB3_DAC

Clock to the DAC register interface.

CLK_APB3_ADC0

Clock to the ADC0 register interface and ADC0
peripheral clock.

CLK_APB3_ADC1

Clock to the ADC1 register interface and ADC1
peripheral clock.

CLK_APB3_CAN0

Clock to the C_CAN0 register interface and
C_CAN0 peripheral clock.

BASE_APB1_CLK CLK_APB1_BUS

APB1 bus clock.

CLK_APB1_MOTOCONP Clock to the PWM Motor control block and PWM
WM
Motor control peripheral clock.

BASE_SPIFI_CLK
BASE_M4_CLK

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CLK_APB1_I2C0

Clock to the I2C0 register interface and I2C0
peripheral clock.

CLK_APB1_I2S

Clock to the I2S0 and I2S1 register interfaces
and I2S0 and I2S1 peripheral clock.

CLK_APB1_CAN1

Clock to the C_CAN1 register interface and
C_CAN1 peripheral clock.

CLK_SPIFI

Clock for the SPIFI SCKI clock input.

CLK_M4_BUS

M4 bus clock.

CLK_M4_SPIFI

Clock to the SPIFI register interface.

CLK_M4_GPIO

Clock to the GPIO register interface

CLK_M4_LCD

Clock to the LCD register interface.

CLK_M4_ETHERNET

Clock to the Ethernet register interface.

CLK_M4_USB0

Clock to the USB0 register interface.

CLK_M4_EMC

Clock to the External memory controller.

CLK_M4_SDIO

Clock to the SD/MMC register interface.

CLK_M4_DMA

Clock to the DMA register interface.

CLK_M4_M4CORE

Clock to the Cortex-M4 core

CLK_M4_SCT

Clock to the SCTimer/PWM register interface.

CLK_M4_USB1

Clock to the USB1 register interface.

CLK_M4_EMC_DIV

Clock to the EMC with clock divider.

CLK_M4_FLASHA

Clock to the flash bank A

CLK_M4_FLASHB

Clock to the flash bank B

CLK_M4_M0APP

Clock to the M0APP coprocessor.

CLK_M4_ADCHS

Clock to the ADCHS.

CLK_M4_EEPROM

Clock to the EEPROM

CLK_M4_WWDT

Clock to the WWDT register interface.

CLK_M4_UART0

Clock to the USART0 register interface.

CLK_M4_UART1

Clock to the UART1 register interface.

CLK_M4_SSP0

Clock to the SSP0 register interface.

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Chapter 14: LPC43xx/LPC43Sxx Clock Control Unit (CCU)

Table 155. CCU1 branch clocks
Base clock

Branch clock

Description

BASE_M4_CLK

CLK_M4_TIMER0

Clock to the timer0 register interface and timer0
peripheral clock.

CLK_M4_TIMER1

Clock to the timer1 register interface and timer1
peripheral clock.

CLK_M4_SCU

Clock to the System control unit register
interface.

CLK_M4_CREG

Clock to the CREG register interface.

CLK_M4_RITIMER

Clock to the RI timer register interface and RI
timer peripheral clock.

CLK_M4_UART2

Clock to the UART2 register interface.

BASE_M4_CLK

BASE_PERIPH_
CLK

CLK_M4_UART3

Clock to the UART3 register interface.

CLK_M4_TIMER2

Clock to the timer2 register interface and timer2
peripheral clock.

CLK_M4_TIMER3

Clock to the timer3 register interface and timer3
peripheral clock.

CLK_M4_SSP1

Clock to the SSP1 register interface.

CLK_M4_QEI

Clock to the QEI register interface and QEI
peripheral clock.

CLK_PERIPH_BUS

Clock to the peripheral bus and the Cortex-M0
subsystem AHB multilayer matrix.

CLK_PERIPH_CORE

Clock to the Cortex-M0 subsystem core.

CLK_PERIPH_SGPIO

Clock to the SGPIO interface.

BASE_USB0_CLK CLK_USB0

USB0 peripheral clock.

BASE_USB1_CLK CLK_USB1

USB1 peripheral clock.

BASE_SPI_CLK

Clock to the SPI interface.

CLK_SPI

BASE_ADCHS_CL CLK_ADCHS
K

ADCHS clock.

Table 156. CCU2 branch clocks

UM10503

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Base clock

Branch clock

Description

BASE_AUDIO_CLK

CLK_AUDIO

Audio system (I2S) clock.

BASE_UART3_CLK

CLK_APB2_UART3

USART3 peripheral clock.

BASE_UART2_CLK

CLK_APB2_UART2

USART2 peripheral clock.

BASE_UART1_CLK

CLK_APB0_UART1

UART1 peripheral clock.

BASE_UART0_CLK

CLK_APB0_UART0

USART0 peripheral clock.

BASE_SSP1_CLK

CLK_APB2_SSP1

SSP1 peripheral clock.

BASE_SSP0_CLK

CLK_APB0_SSP0

SSP0 peripheral clock.

BASE_SDIO_CLK

CLK_SDIO

SD/MMC peripheral clock.

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14.5 Register description
Table 157. Register overview: CCU1 (base address 0x4005 1000)
Name

Access Address Description
offset

Reset value

Reference

PM

R/W

0x000

CCU1 power mode register

0x0000 0000

Table 159

BASE_STAT

R

0x004

CCU1 base clock status register

0x0000 0FFF Table 160

-

-

0x008 to Reserved
0x0FC

-

CLK_APB3_BUS_CFG

R/W

0x100

CLK_APB3_BUS clock configuration
register

0x0000 0001

Table 162

CLK_APB3_BUS_STAT

R

0x104

CLK_APB3_BUS clock status register

0x0000 0001

Table 165

CLK_APB3_I2C1_CFG

R/W

0x108

CLK_APB3_I2C1 configuration register

0x0000 0001

Table 162

CLK_APB3_I2C1_STAT

R

0x10C

CLK_APB3_I2C1 status register

0x0000 0001

Table 165

CLK_APB3_DAC_CFG

R/W

0x110

CLK_APB3_DAC configuration register

0x0000 0001

Table 162

CLK_APB3_DAC_STAT

R

0x114

CLK_APB3_DAC status register

0x0000 0001

Table 165

CLK_APB3_ADC0_CFG

R/W

0x118

CLK_APB3_ADC0 configuration register

0x0000 0001

Table 162

CLK_APB3_ADC0_STAT

R

0x11C

CLK_APB3_ADC0 status register

0x0000 0001

Table 165

CLK_APB3_ADC1_CFG

R/W

0x120

CLK_APB3_ADC1 configuration register

0x0000 0001

Table 162

CLK_APB3_ADC1_STAT

R

0x124

CLK_APB3_ADC1 status register

0x0000 0001

Table 165

CLK_APB3_CAN0_CFG

R/W

0x128

CLK_APB3_CAN0 configuration register

0x0000 0001

Table 162

CLK_APB3_CAN0_STAT

R

0x12C

CLK_APB3_CAN0 status register

0x0000 0001

Table 165

-

-

0x130 to Reserved
0x1FC

-

-

CLK_APB1_BUS_CFG

R/W

0x200

0x0000 0001

Table 162

CLK_APB1_BUS configuration register

CLK_APB1_BUS_STAT

R

0x204

CLK_APB1_BUS status register

0x0000 0001

Table 165

CLK_APB1_MOTOCON
PWM_CFG

R/W

0x208

CLK_APB1_MOTOCON configuration
register

0x0000 0001

Table 162

CLK_APB1_MOTOCON
PWM_STAT

R

0x20C

CLK_APB1_MOTOCON status register

0x0000 0001

Table 165

CLK_APB1_I2C0_CFG

R/W

0x210

CLK_APB1_I2C0 configuration register

0x0000 0001

Table 162

CLK_APB1_I2C0_STAT

R

0x214

CLK_APB1_I2C0 status register

0x0000 0001

Table 165

CLK_APB1_I2S_CFG

R/W

0x218

CLK_APB1_I2S configuration register

0x0000 0001

Table 162

CLK_APB1_I2S_STAT

R

0x21C

CLK_APB1_I2S status register

0x0000 0001

Table 165

CLK_APB1_CAN1_CFG

R/W

0x220

CLK_APB3_CAN1 configuration register

0x0000 0001

Table 162

CLK_APB1_CAN1_STAT

R

0x224

CLK_APB3_CAN1 status register

0x0000 0001

Table 165

-

-

0x220 to Reserved
0x2FC

-

-

CLK_SPIFI_CFG

R/W

0x300

CLK_SPIFI configuration register

0x0000 0001

Table 162

CLK_SPIFI_STAT

R

0x304

CLK_SPIFI status register

0x0000 0001

Table 165

-

-

0x308 to Reserved
0x3FC

-

-

CLK_M4_BUS_CFG

R/W

0x400

CLK_M4_BUS configuration register

0x0000 0001

Table 162

CLK_M4_BUS_STAT

R

0x404

CLK_M4_BUS status register

0x0000 0001

Table 165

CLK_M4_SPIFI_CFG

R/W

0x408

CLK_M4_SPIFI configuration register

0x0000 0001

Table 162

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Chapter 14: LPC43xx/LPC43Sxx Clock Control Unit (CCU)

Table 157. Register overview: CCU1 (base address 0x4005 1000)
Name

Access Address Description
offset

Reset value

Reference

CLK_M4_SPIFI_STAT

R

0x40C

CLK_M4_SPIFI status register

0x0000 0001

Table 165

CLK_M4_GPIO_CFG

R/W

0x410

CLK_M4_GPIO configuration register

0x0000 0001

Table 162

CLK_M4_GPIO_STAT

R

0x414

CLK_M4_GPIO status register

0x0000 0001

Table 165

CLK_M4_LCD_CFG

R/W

0x418

CLK_M4_LCD configuration register

0x0000 0001

Table 162

CLK_M4_LCD_STAT

R

0x41C

CLK_M4_LCD status register

0x0000 0001

Table 165

CLK_M4_ETHERNET_CFG

R/W

0x420

CLK_M4_ETHERNET configuration
register

0x0000 0001

Table 162

CLK_M4_ETHERNET_STAT

R

0x424

CLK_M4_ETHERNET status register

0x0000 0001

Table 165

CLK_M4_USB0_CFG

R/W

0x428

CLK_M4_USB0 configuration register

0x0000 0001

Table 162

CLK_M4_USB0_STAT

R

0x42C

CLK_M4_USB0 status register

0x0000 0001

Table 165

CLK_M4_EMC_CFG

R/W

0x430

CLK_M4_EMC configuration register

0x0000 0001

Table 162

CLK_M4_EMC_STAT

R

0x434

CLK_M4_EMC status register

0x0000 0001

Table 165

CLK_M4_SDIO_CFG

R/W

0x438

CLK_M4_SDIO configuration register

0x0000 0001

Table 162

CLK_M4_SDIO_STAT

R

0x43C

CLK_M4_SDIO status register

0x0000 0001

Table 165

CLK_M4_DMA_CFG

R/W

0x440

CLK_M4_DMA configuration register

0x0000 0001

Table 162

CLK_M4_DMA_STAT

R

0x444

CLK_M4_DMA status register

0x0000 0001

Table 165

CLK_M4_M4CORE_CFG

R/W

0x448

CLK_M4_M4CORE configuration register 0x0000 0001

Table 162

CLK_M4_M4CORE_STAT

R

0x44C

CLK_M4_M4CORE status register

0x0000 0001

Table 165

-

-

0x450 to Reserved
0x45C

-

-

-

-

0x460 to Reserved
0x464

-

-

CLK_M4_SCT_CFG

R/W

0x468

CLK_M4_SCT configuration register

0x0000 0001

Table 162

CLK_M4_SCT_STAT

R

0x46C

CLK_M4_SCT status register

0x0000 0001

Table 165

CLK_M4_USB1_CFG

R/W

0x470

CLK_M4_USB1 configuration register

0x0000 0001

Table 162

CLK_M4_USB1_STAT

R

0x474

CLK_M4_USB1 status register

0x0000 0001

Table 165

CLK_M4_EMCDIV_CFG

R/W

0x478

CLK_M4_EMCDIV configuration register

0x0000 0001

Table 163

CLK_M4_EMCDIV_STAT

R

0x47C

CLK_M4_EMCDIV status register

0x0000 0001

Table 165

CLK_M4_FLASHA_CFG

R/W

0x480

CLK_M4_FLASHA configuration register

0x0000 0001

Table 163

CLK_M4_FLASHA_STAT

R

0x484

CLK_M4_FLASHA status register

0x0000 0001

Table 165

CLK_M4_FLASHB_CFG

R/W

0x488

CLK_M4_FLASHB configuration register

0x0000 0001

Table 163

CLK_M4_FLASHB_STAT

R

0x48C

CLK_M4_FLASHB status register

0x0000 0001

Table 165

CLK_M4_M0APP_CFG

-

0x490

CLK_M4_M0APP_CFG configuration
register

0x0000 0001

Table 163

CLK_M4_M0APP_STAT

-

0x494

CLK_M4_M0APP_STAT status register

0x0000 0001

Table 165

CLK_M4_ADCHS_CFG

-

0x498

CLK_M4_ADCHS_CFG configuration
register

0x0000 0001

Table 163

CLK_M4_ADCHS_STAT

0x49C

CLK_M4_ADCHS_STAT configuration
register

0x0000 0001

Table 165

CLK_M4_EEPROM_CFG

0x4A0

CLK_M4_EEPROM configuration register 0x0000 0001

Table 163

CLK_M4_EEPROM_STAT

0x4A4

CLK_M4_EEPROM status register

Table 165

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Chapter 14: LPC43xx/LPC43Sxx Clock Control Unit (CCU)

Table 157. Register overview: CCU1 (base address 0x4005 1000)
Name

Access Address Description
offset

Reset value

Reference

-

-

0x4A8 to Reserved
0x4FC

-

CLK_M4_WWDT_CFG

R/W

0x500

CLK_M4_WWDT configuration register

0x0000 0001

Table 162

CLK_M4_WWDT_STAT

R

0x504

CLK_M4_WWDT status register

0x0000 0001

Table 165

CLK_M4_USART0_CFG

R/W

0x508

CLK_M4_UART0 configuration register

0x0000 0001

Table 162

CLK_M4_USART0_STAT

R

0x50C

CLK_M4_UART0 status register

0x0000 0001

Table 165

CLK_M4_UART1_CFG

R/W

0x510

CLK_M4_UART1 configuration register

0x0000 0001

Table 162

CLK_M4_UART1_STAT

R

0x514

CLK_M4_UART1 status register

0x0000 0001

Table 165

CLK_M4_SSP0_CFG

R/W

0x518

CLK_M4_SSP0 configuration register

0x0000 0001

Table 162

CLK_M4_SSP0_STAT

R

0x51C

CLK_M4_SSP0 status register

0x0000 0001

Table 165

CLK_M4_TIMER0_CFG

R/W

0x520

CLK_M4_TIMER0 configuration register

0x0000 0001

Table 162

CLK_M4_TIMER0_STAT

R

0x524

CLK_M4_TIMER0 status register

0x0000 0001

Table 165

CLK_M4_TIMER1_CFG

R/W

0x528

CLK_M4_TIMER1 configuration register

0x0000 0001

Table 162

CLK_M4_TIMER1_STAT

R

0x52C

CLK_M4_TIMER1 status register

0x0000 0001

Table 165

CLK_M4_SCU_CFG

R/W

0x530

CLK_M4_SCU configuration register

0x0000 0001

Table 162

CLK_M4_SCU_STAT

R

0x534

CLK_M4_SCU status register

0x0000 0001

Table 165

CLK_M4_CREG_CFG

R/W

0x538

CLK_M4_CREG configuration register

0x0000 0001

Table 162

CLK_M4_CREG status register

CLK_M4_CREG_STAT

R

0x53C

0x0000 0001

Table 165

-

-

0x540 to Reserved
0x5FC

-

-

CLK_M4_RITIMER_CFG

R/W

0x600

0x0000 0001

Table 162

CLK_M4_RITIMER_STAT

R

0x604

CLK_M4_RITIMER status register

0x0000 0001

Table 165

CLK_M4_USART2_CFG

R/W

0x608

CLK_M4_UART2 configuration register

0x0000 0001

Table 162

CLK_M4_USART2_STAT

R

0x60C

CLK_M4_UART2 status register

0x0000 0001

Table 165

CLK_M4_USART3_CFG

R/W

0x610

CLK_M4_UART3 configuration register

0x0000 0001

Table 162

CLK_M4_RITIMER configuration register

CLK_M4_USART3_STAT

R

0x614

CLK_M4_UART3 status register

0x0000 0001

Table 165

CLK_M4_TIMER2_CFG

R/W

0x618

CLK_M4_TIMER2 configuration register

0x0000 0001

Table 162

CLK_M4_TIMER2_STAT

R

0x61C

CLK_M4_TIMER2 status register

0x0000 0001

Table 165

CLK_M4_TIMER3_CFG

R/W

0x620

CLK_M4_TIMER3 configuration register

0x0000 0001

Table 162

CLK_M4_TIMER3_STAT

R

0x624

CLK_M4_TIMER3 status register

0x0000 0001

Table 165

CLK_M4_SSP1_CFG

R/W

0x628

CLK_M4_SSP1 configuration register

0x0000 0001

Table 162

CLK_M4_SSP1_STAT

R

0x62C

CLK_M4_SSP1 status register

0x0000 0001

Table 165

CLK_M4_QEI_CFG

R/W

0x630

CLK_M4_QEI configuration register

0x0000 0001

Table 162

CLK_M4_QEI_STAT

R

0x634

CLK_M4_QEI status register

0x0000 0001

Table 165

-

R/W

0x638 to Reserved
0x6FC

-

-

CLK_PERIPH_BUS_CFG

R/W

0x700

CLK_PERIPH_BUS configuration register 0x0000 0001

CLK_PERIPH_BUS_STAT

R

0x704

CLK_PERIPH_BUS status register

-

R/W

0x708 to Reserved
0x70C

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Table 162

0x0000 0001

Table 165

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-

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Chapter 14: LPC43xx/LPC43Sxx Clock Control Unit (CCU)

Table 157. Register overview: CCU1 (base address 0x4005 1000)
Name

Access Address Description
offset

Reset value

Reference

CLK_PERIPH_CORE_CFG

R/W

0x710

CLK_PERIPH_CORE configuration
register

0x0000 0001

Table 162

CLK_PERIPH_CORE_STAT

R

0x714

CLK_PERIPH_CORE status register

0x0000 0001

Table 165

CLK_PERIPH_SGPIO_CFG

R/W

0x718

CLK_PERIPH_SGPIO configuration
register

0x0000 0001

Table 162

CLK_PERIPH_SGPIO_STAT

R

0x71C

CLK_PERIPH_SGPIO status register

0x0000 0001

Table 165

-

R/W

0x720 to Reserved
0x7FC

-

-

CLK_USB0_CFG

R/W

0x800

CLK_USB0 configuration register

0x0000 0001

Table 162

CLK_USB0_STAT

R

0x804

CLK_USB0 status register

0x0000 0001

Table 165

-

-

0x808 to Reserved
0x8FC

-

-

CLK_USB1_CFG

R/W

0x900

CLK_USB1 configuration register

0x0000 0001

Table 162

CLK_USB1_STAT

R

0x904

CLK_USB1 status register

0x0000 0001

Table 165

-

-

0x908 to Reserved
0x9FC

-

-

CLK_SPI_CFG

R/W

0xA00

0x0000 0001

Table 162

CLK_SPI_STAT

R

0xA04

CLK_SPI status register

0x0000 0001

Table 165

CLK_ADCHS_CFG

R/W

0xB00

CLK_ADCHS configuration register

0x0000 0001

Table 162

CLK_ADCHS_STAT

R

0xB04

CLK_ADCHS status register

0x0000 0001

Table 165

Reference

CLK_SPI configuration register

Table 158. Register overview: CCU2 (base address 0x4005 2000)
Name

Access Address Description
offset

Reset value

PM

R/W

0x000

CCU2 power mode register

0x0000 0000 Table 159

BASE_STAT

R

0x004

CCU2 base clocks status register

0x0000 0FFF Table 161

-

-

0x008 to
0x0FC

Reserved

-

CLK_AUDIO_CFG

R/W

0x100

CLK_AUDIO configuration register

0x0000 0001 Table 164

CLK_AUDIO_STAT

R

0x104

CLK_AUDIO status register

0x0000 0001 Table 166

-

-

0x108 to
0x1FC

Reserved

-

CLK_APB2_USART3_CFG

R/W

0x200

CLK_APB2_UART3 configuration register

0x0000 0001 Table 164

CLK_APB2_USART3_STAT R

0x204

CLK_APB2_UART3 status register

0x0000 0001 Table 166

-

-

0x208 to
0x2FC

Reserved

-

CLK_APB2_USART2_CFG

R/W

0x300

CLK_APB2_UART2 configuration register

0x0000 0001 Table 164

CLK_APB2_USART2_STAT R

0x304

CLK_APB2_UART2 status register

0x0000 0001 Table 166

-

-

0x308 to
0x3FC

Reserved

-

CLK_APB0_UART1_CFG

R/W

0x400

CLK_APB0_UART1 configuration register

0x0000 0001 Table 164

CLK_APB0_UART1_STAT

R

0x404

CLK_APB0_UART1 status register

0x0000 0001 Table 166

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Chapter 14: LPC43xx/LPC43Sxx Clock Control Unit (CCU)

Table 158. Register overview: CCU2 (base address 0x4005 2000)
Name

Access Address Description
offset

Reset value

Reference

-

-

0x408 to
0x4FC

Reserved

-

CLK_APB0_USART0_CFG

R/W

0x500

CLK_APB0_UART0 configuration register

0x0000 0001 Table 164

CLK_APB0_USART0_STAT R

0x504

CLK_APB0_UART0 status register

0x0000 0001 Table 166

-

-

0x508 to
0x5FC

Reserved

-

CLK_APB2_SSP1_CFG

R/W

0x600

CLK_APB2_SSP1 configuration register

0x0000 0001 Table 164

CLK_APB2_SSP1_STAT

R

0x604

CLK_APB2_SSP1 status register

0x0000 0001 Table 166

-

-

0x608 to
0x6FC

Reserved

-

CLK_APB0_SSP0_CFG

R/W

0x700

CLK_APB0_SSP0 configuration register

0x0000 0001 Table 164

CLK_APB0_SSP0_STAT

R

0x704

CLK_APB0_SSP0 status register

0x0000 0001 Table 166

-

-

0x708 to
0x7FC

Reserved

-

CLK_SDIO_CFG

R/W

0x800

CLK_SDIO configuration register (for
SD/MMC)

0x0000 0001 Table 164

CLK_SDIO_STAT

R

0x804

CLK_SDIO status register (for SD/MMC)

0x0000 0001 Table 166

14.5.1 Power mode register
This register contains a single bit, PD, that disables all output clocks with Wake-up
enabled. (W = 1 in the CCU branch clock configuration registers, Section 14.5.3). Clocks
disabled by writing to this register are reactivated when a wake-up interrupt is detected or
when a 0 is written into the PD bit.
Table 159. CCU1/2 power mode register (CCU1_PM, address 0x4005 1000 and CCU2_PM,
address 0x4005 2000) bit description
Bit

Symbol

0

PD

31:1

-

Value

Description

Reset
value

Access

Initiate power-down mode

0

R/W

-

-

0

Normal operation.

1

Clocks with wake-up mode enabled (W = 1) are
disabled.
Reserved.

14.5.2 Base clock status register
Each bit in this register indicates whether the specified base clock can be safely switched
off. A logic zero indicates that all branch clocks generated from this base clock are
disabled. Hence, the base clock can also be switched off. A logic one value indicates that
there is still at least one branch clock running.
Remark: Reactivate the base clock before writing to the configuration register of the
branch clock.

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Table 160. CCU1 base clock status register (CCU1_BASE_STAT, address 0x4005 1004) bit
description
Bit

Symbol

Description

Reset
value

Access

0

BASE_APB3_
CLK_IND

Base clock indicator for BASE_APB3_CLK

1

R

1

R

1

R

1

R

-

-

0 = All branch clocks switched off.
1 = At least one branch clock running.

1

BASE_APB1_
CLK_IND

Base clock indicator for BASE_APB1_CLK
0 = All branch clocks switched off.
1 = At least one branch clock running.

2

BASE_SPIFI_
CLK_IND

Base clock indicator for BASE_SPIFI_CLK

BASE_M4_
CLK_IND

Base clock indicator for BASE_M4_CLK

0 = All branch clocks switched off.
1 = At least one branch clock running.

3

0 = All branch clocks switched off.
1 = At least one branch clock running.

5:4

-

Reserved

6

BASE_PERIPH_
CLK_IND

Base clock indicator for BASE_PERIPH_CLK 1

R

0 = All branch clocks switched off.
1 = At least one branch clock running.

7

BASE_USB0_
CLK_IND

Base clock indicator for BASE_USB0_CLK

BASE_USB1_
CLK_IND

Base clock indicator for BASE_USB1_CLK

1

R

1

R

1

R

-

-

0 = All branch clocks switched off.
1 = At least one branch clock running.

8

0 = All branch clocks switched off.
1 = at least one branch clock running.

9

BASE_SPI_
CLK_IND

Base clock indicator for BASE_SPI_CLK
0 = All branch clocks switched off.
1 = At least one branch clock running.

31:10 -

Reserved

Table 161. CCU2 base clock status register (CCU2_BASE_STAT, address 0x4005 2004) bit
description
Bit

Symbol

Description

Reset
value

Access

0

-

Reserved.

-

-

1

BASE_UART3_
CLK

Base clock indicator for BASE_UART3_CLK

1

R

1

R

1

R

0 = All branch clocks switched off.
1 = At least one branch clock running.

2

BASE_UART2_
CLK

Base clock indicator for BASE_UART2_CLK
0 = All branch clocks switched off.
1 = At least one branch clock running.

3

BASE_UART1_
CLK

Base clock indicator for BASE_UART1_CLK
0 = All branch clocks switched off.
1 = At least one branch clock running.

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Chapter 14: LPC43xx/LPC43Sxx Clock Control Unit (CCU)

Table 161. CCU2 base clock status register (CCU2_BASE_STAT, address 0x4005 2004) bit
description …continued
Bit

Symbol

Description

Reset
value

Access

4

BASE_UART0_
CLK

Base clock indicator for BASE_UART0_CLK

1

R

1

R

1

R

0 = All branch clocks switched off.
1 = At least one branch clock running.

5

BASE_SSP1_
CLK

Base clock indicator for BASE_SSP1_CLK
0 = All branch clocks switched off.
1 = At least one branch clock running.

6

BASE_SSP0_
CLK

Base clock indicator for BASE_SSP0_CLK
0 = All branch clocks switched off.
1 = At least one branch clock running.

7

-

Reserved.

-

-

31:8

-

Reserved.

-

-

14.5.3 CCU1/2 branch clock configuration registers
Each generated output clock from the CCU has a configuration register. They all follow the
format as described in Table 162 and Table 164.
On the LPC43xx, all branch clocks are in Run mode after reset. Auto and wake-up
features are disabled.
The clock can be configured to run in the following modes described by the bits RUN,
AUTO, and WAKEUP in the CLK_XXX_CFG registers:
RUN — The WAKEUP, PD, and AUTO control bits determine the activation of the branch
clock. If register bit AUTO is set, the AHB disable protocol must complete before the clock
is switched off. The PD bit is shown in Table 159.
AUTO — Enable auto (AHB disable mechanism). The PMU initiates the AHB disable
protocol before switching the clock off. This protocol ensures that all AHB transactions
have been completed before turning the clock off. However, if a bus master initiates a
transfer and the bus is still active, ensure that all transfers have completed before turning
off the master clock in auto mode. Otherwise, data may be lost when the master clock is
turned off and the master can’t process a response from the bus.
WAKEUP — The branch clock is wake-up enabled under the following conditions:

• The PD bit in the Power Mode register (seeTable 159) is set.
• Wake-up enabled clocks are switched off.
Wake-up enabled clocks are switched on when a wake-up event is detected or when the
PD bit is cleared. If register bit AUTO is set, the AHB disable protocol must complete
before the clock is switched off.
Remark: To disable any of the branch clocks safely, use two separate writes to the
CLK_XXX_CFG register: first set the AUTO bit, and then on the next write, disable the
clock by setting the RUN bit to zero.

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Chapter 14: LPC43xx/LPC43Sxx Clock Control Unit (CCU)

Table 162. CCU1 branch clock configuration register (CLK_XXX_CFG, addresses 0x4005
1100, 0x4005 1104,..., 0x4005 1A00) bit description
Bit

Symbol

0

RUN

1

2

31:3

Value

Description

Reset
value

Access

Run enable

1

R/W

0

R/W

0

R/W

-

-

0

Clock is disabled.

1

Clock is enabled.

AUTO

Auto (AHB disable mechanism) enable
0

Auto is disabled.

1

Auto is enabled.

WAKEUP

Wake-up configure
0

Wake-up is disabled.

1

Wake-up is enabled.

-

Reserved

Remark: Configure the output clock for the EMC clock divider (Table 163) together with
bit 16 in the CREG6 register (Table 104).
Table 163. CCU1 branch clock configuration register (CLK_M4_EMCDIV_CFG, addresses
0x4005 1478) bit description
Bit

Symbol

0

RUN

1

2

3

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Value

Description

Reset
value

Access

Run enable

1

R/W

0

R/W

0

R/W

Reserved

-

-

0

Clock is disabled.

1

Clock is enabled.

AUTO

Auto (AHB disable mechanism) enable
0

Auto is disabled.

1

Auto is enabled.

0

Wake-up is disabled.

1

Wake-up is enabled.

WAKEUP

Wake-up mechanism enable

-

4

-

Reserved

-

-

7:5

DIV

Clock divider value

0

W

0x0

No division (divide by 1).

0x1

Divide by 2.

0x2

Reserved

0x3

Reserved

0x4

Reserved

26:8

-

Reserved

-

-

29:27

DIVSTAT

Clock divider status. When this bit field is
read, the value of the DIV bit field in this
register is returned.

0

R

31:30

-

Reserved

-

-

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Chapter 14: LPC43xx/LPC43Sxx Clock Control Unit (CCU)

Table 164. CCU2 branch clock configuration register (CLK_XXX_CFG, addresses 0x4005
2100, 0x4005 2200,..., 0x4005 2800) bit description
Bit

Symbol

0

RUN

1

2

31:3

Value

Description

Reset
value

Access

Run enable

1

R/W

0

R/W

0

R/W

-

-

0

Clock is disabled.

1

Clock is enabled.

AUTO

Auto (AHB disable mechanism) enable
0

Auto is disabled.

1

Auto is enabled.

0

Wake-up is disabled.

1

Wake-up is enabled.

WAKEUP

-

Wake-up configure

Reserved

14.5.4 CCU1/2 branch clock status registers
Each output clock generated from the CCU has a status register. When writing to the
configuration register of an output clock, the Auto or Wake-up mechanism can delay the
update of the actual hardware signals. The Status Register shows the current value of
these signals. All output clock Status Registers follow the format as described in
Table 165 and Table 166.
Remark: The divider value for the CLK_M4_EMCDIV_CFG register is not reflected in the
status register. Read the DIVSTAT bits in the CLK_M4_EMCDIV_CFG register for the
divider status.
Table 165. CCU1 branch clock status register (CLK_XXX_STAT, addresses 0x4005 1104,
0x4005 110C,..., 0x4005 1A04) bit description
Bit

Symbol

Description

Reset
value

Access

0

RUN

Run enable status

1

R

0

R

Wake-up mechanism enable status. This bit reads 0
as 1 when the power down bit has been set in the
PM register (PD = 1) and the clock has been
configured to run after wake-up.

R

0 = clock is disabled.
1 = clock is enabled.
1

AUTO

Auto (AHB disable mechanism) enable status
0 = Auto is disabled.
1 = Auto is enabled.

2

WAKEUP

0 = Wake-up is disabled.
1 = Wake-up is enabled.

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Chapter 14: LPC43xx/LPC43Sxx Clock Control Unit (CCU)

Table 165. CCU1 branch clock status register (CLK_XXX_STAT, addresses 0x4005 1104,
0x4005 110C,..., 0x4005 1A04) bit description …continued
Bit

Symbol

Description

Reset
value

Access

4:3

-

Reserved.

-

-

5

RUN_N

Clock disable status. This bit has same
functionality as the RUN bit except with the
opposite polarity.

0

R

-

-

0 = clock is enabled.
1 = clock is disabled.
31:6

-

Reserved

Table 166. CCU2 branch clock status register (CLK_XXX_STAT, addresses 0x4005 2104,
0x4005 2204,..., 0x4005 2804) bit description
Bit

Symbol

Description

Reset
value

Access

0

RUN

Run enable status

1

R

0

R

0

R

0 = clock is disabled
1 = clock is enabled
1

AUTO

Auto (AHB disable mechanism) enable status
0 = Auto is disabled
1 = Auto is enabled

2

WAKEUP

Wake-up mechanism enable status. This bit
reads as 1 when the power down bit has been
set in the PM register (PD = 1) and the clock
has been configured to run after wake-up.
0 = Wake-up is disabled
1 = Wake-up is enabled

4:3

-

Reserved.

-

-

5

RUN_N

Clock disable status. This bit has same
functionality as the RUN bit except with the
opposite polarity.

0

R

-

-

0 = clock is enabled.
1 = clock is disabled.
31:6

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15.1 How to read this chapter
Flash/EEPROM, Ethernet, USB0, USB1, ADCHS, and LCD related resets are not
available on all packages or parts. See Section 1.3. The corresponding reset registers are
reserved.
The M0 subsystem core is only enabled on parts LPC4370/LPC43S70 and
LPC436x/LPC43S6x.

15.2 Basic configuration
Table 167. RGU clocking and power control
Base clock

Branch clock

Operating
frequency

RGU

BASE_M4_CLK

CLK_M4_BUS

up to 204 MHz

RGU delay clocks

BASE_SAFE_CLK

-

12 MHz

15.3 General description
The RGU allows generation of independent reset signals for various blocks and
peripherals on the LPC43xx. Each reset signal is asserted by a reset generator with one
output (the reset signal) and one or more inputs, which link the reset generators together
and create a reset hierarchy.
Remark: The ARM Cortex-M4 SYSRESETREQ triggers a peripheral reset PERIPH_RST.

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Chapter 15: LPC43xx/LPC43Sxx Reset Generation Unit (RGU)

RTC POWER DOMAIN

POR

alarm timer, RTC, CREG (partial), PMC

RGU
RESET

WWDT
CREG (partial), PMC

CORE_RST
GENERATOR

BOD reset
WWDT reset

PERIPH_RST
GENERATOR

Bus bridges,
memory controllers

24

APB peripherals, GPIO

Cortex-M4 core
MASTER_RST
GENERATOR

6

AHB peripherals (USB0/1, LCD
Ethernet, GPDMA, SDIO)

Fig 41. RGU Block diagram
Table 168. Reset output configuration
Reset output
generator

Reset
output
#

Reset source

Parts of the device reset when
activated

CORE_RST

0

external reset pin
RESET, BOD
reset, WWDT
time-out reset,
internal power
failure, exiting
from Deep
power-down

Entire chip except:

•

peripherals in the battery-powered
domain.

•

parts of creg.

PERIPH_RST

1

CORE_RST

All peripherals with reset source
PERIPH_RST and MASTER_RST

MASTER_RST

2

PERIPH_RST

All peripherals with reset source
MASTER_RST

Reserved

3

-

-

WWDT_RST

4

CORE_RST

WWDT. No software reset.

CREG_RST

5

CORE_RST

Configuration register block, Event router,
backup registers, RTC, alarm timer. No
software reset.

Reserved

6-7

-

-

SCU_RST

9

PERIPH_RST

System control unit

Reserved

10 - 11

-

-

M0SUB_RST

12

MASTER_RST

ARM Cortex-M0 subsystem core reset.
Remark: Software must clear this reset
by writing to the RESET_CTRL0 register.

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13

MASTER_RST

Cortex-M4 system reset.

Reserved

14

-

-

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Chapter 15: LPC43xx/LPC43Sxx Reset Generation Unit (RGU)

Table 168. Reset output configuration …continued

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Reset output
generator

Reset
output
#

Reset source

Parts of the device reset when
activated

Reserved

15

-

-

LCD_RST

16

MASTER_RST

LCD controller reset

USB0_RST

17

MASTER_RST

USB0 reset

USB1_RST

18

MASTER_RST

USB1 reset

DMA_RST

19

MASTER_RST

DMA reset

SDIO_RST

20

MASTER_RST

SDIO reset

EMC_RST

21

MASTER_RST

External memory controller reset

ETHERNET_RST

22

MASTER_RST

Ethernet reset

Reserved

23 - 24

-

-

FLASHA_RST

25

PERIPH_RST

Flash bank A reset

Reserved

26

-

-

EEPROM_RST

27

PERIPH_RST

EEPROM reset

GPIO_RST

28

PERIPH_RST

GPIO reset

FLASHB_RST

29

PERIPH_RST

Flash bank B reset

Reserved

30 - 31

-

-

TIMER0_RST

32

PERIPH_RST

Timer0 reset

TIMER1_RST

33

PERIPH_RST

Timer1 reset

TIMER2_RST

34

PERIPH_RST

Timer2 reset

TIMER3_RST

35

PERIPH_RST

Timer3 reset

RITIMER_RST

36

PERIPH_RST

Repetitive Interrupt timer reset

SCT_RST

37

PERIPH_RST

State Configurable Timer reset

MOTOCONPWM_RST 38

PERIPH_RST

Motor control PWM reset

QEI_RST

39

PERIPH_RST

QEI reset

ADC0_RST

40

PERIPH_RST

ADC0 reset (ADC register interface and
analog block)

ADC1_RST

41

PERIPH_RST

ADC1 reset (ADC register interface and
analog block)

DAC_RST

42

PERIPH_RST

DAC reset (DAC register interface and
analog block)

Reserved

43

-

-

UART0_RST

44

PERIPH_RST

USART0 reset

UART1_RST

45

PERIPH_RST

UART1 reset

UART2_RST

46

PERIPH_RST

USART2 reset

UART3_RST

47

PERIPH_RST

USART3 reset

I2C0_RST

48

PERIPH_RST

I2C0 reset

I2C1_RST

49

PERIPH_RST

I2C1 reset

SSP0_RST

50

PERIPH_RST

SSP0 reset

SSP1_RST

51

PERIPH_RST

SSP1 reset

I2S_RST

52

PERIPH_RST

I2S0 and I2S1 reset

SPIFI_RST

53

PERIPH_RST

SPIFI reset

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Chapter 15: LPC43xx/LPC43Sxx Reset Generation Unit (RGU)

Table 168. Reset output configuration …continued
Reset output
generator

Reset
output
#

Reset source

Parts of the device reset when
activated

CAN1_RST

54

PERIPH_RST

C_CAN1 reset

CAN0_RST

55

PERIPH_RST

C_CAN0 reset

M0APP_RST

56

MASTER_RST

ARM Cortex-M0 co-processor reset.
Remark: Software must clear the M0
processor reset by writing to the
RESET_CTRL1 register.

SGPIO_RST

57

PERIPH_RST

SGPIO reset

SPI_RST

58

PERIPH_RST

SPI reset

Reserved

59

-

-

ADCHS_RST

60

PERIPH_RST

ADCHS (12-bit ADC) reset

Reserved

63-61

-

-

The RGU monitors the reset cause for each reset output using the RESET_STATUS0 to
RESET_STATUS3 registers. The following reset causes are monitored in these registers:

• No reset has taken place.
• Reset generated by software (using the registers RESET_CTRL0 and
RESET_CTRL1).

• Reset generated by any of the reset sources.
15.3.1 Reset hierarchy
The POR resets the entire chip. The reset hierarchy for the other reset sources is shown
in Table 169.

Table 169. Reset priority
Priority Reset input

RTC
CREG WWDT RGU ABP
GPIO EMC AHB masters: Cortex
peripherals
peripherals
M4, Cortex M0, USB,
[1]/
GPDMA, SDIO,
Event router/
Ethernet
PMC

0

POR

yes

1

External reset pin, no
BOD and WWDT
resets, internal
power failure,
exiting the Deep
power-down
mode

2

CORE_RST

no

yes

yes

yes

yes

yes

yes

yes

partial yes

yes

yes

yes

yes

yes

yes

yes

yes

yes

yes

[2]

partial yes
[2]

3

PERIPH_RST

no

no

no

no

yes

yes

yes

yes

4

MASTER_RST

no

no

no

no

no

no

yes

yes

[1]

Includes alarm timer and RTC. The POR does not reset the backup registers.

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Chapter 15: LPC43xx/LPC43Sxx Reset Generation Unit (RGU)

[2]

The CREG0 register maintains its value during reset for partial resets.

TRSTn
TRSTn_loc

RESET
POR

CORE_RST

BOD reset
delay=3

WWDT reset
PMC reset
CORE_RST

delay=3
no sw
delay=3
no sw

WWDT_RST
CREG_RST
PERIPH_RST

delay=5

PERIPH_RST

spi,etc ....

delay=2

MASTER_RST
delay=5

MASTER_RST

m4,usb,lcd,etc...

delay=2

Fig 42. RGU Reset structure

15.4 Register overview
Table 170. Register overview: RGU (base address: 0x4005 3000)
Name

Access

Address Description
offset

Reset value

Reference

RESET_CTRL0

W

0x100

Reset control register 0

-

see Table 171

RESET_CTRL1

W

0x104

Reset control register 1

-

see Table 172

RESET_STATUS0

R/W

0x110

Reset status register 0

0x5555 0050 see Table 173

RESET_STATUS1

R/W

0x114

Reset status register 1

0x5555 5555 see Table 174

RESET_STATUS2

R/W

0x118

Reset status register 2

0x5555 5555 see Table 175

RESET_STATUS3

R/W

0x11C

Reset status register 3

0x5555 5555 see Table 176

RESET_ACTIVE_STATUS0 R

0x150

Reset active status register 0

0xFFFF
EFFF

see Table 177

RESET_ACTIVE_STATUS1 R

0x154

Reset active status register 1

0xFEFF
FFFF

see Table 178

-

R/W

0x400

Reserved

-

-

RESET_EXT_STAT1

R/W

0x404

Reset external status register 1 for
PERIPH_RST

0x0

see Table 179

RESET_EXT_STAT2

R/W

0x408

Reset external status register 2 for
MASTER_RST

0x4

see Table 180

-

-

0x40C

Reserved

-

-

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Chapter 15: LPC43xx/LPC43Sxx Reset Generation Unit (RGU)

Table 170. Register overview: RGU (base address: 0x4005 3000) …continued
Name

Access

Address Description
offset

Reset value

Reference

-

-

0x410

-

-

-

RESET_EXT_STAT5

R/W

0x414

Reset external status register 5 for
CREG_RST

0x0

see Table 181

RESET_EXT_STAT6

-

0x418

Reserved

-

-

RESET_EXT_STAT7

-

0x41C

Reserved

-

-

RESET_EXT_STAT8

R/W

0x420

Reset external status register 8 for
BUS_RST

0x4

see Table 182

RESET_EXT_STAT9

R/W

0x424

Reset external status register 9 for
SCU_RST

0x4

see Table 182

RESET_EXT_STAT10

-

0x428

Reserved

-

-

RESET_EXT_STAT11

-

0x42C

Reserved

-

-

RESET_EXT_STAT12

-

0x430

Reset external status register 12 for
M0SUB_RST

0x8

see Table 183

RESET_EXT_STAT13

R/W

0x434

Reset external status register 13 for
M4_RST

0x8

see Table 183

RESET_EXT_STAT14

-

0x438

Reserved

-

-

RESET_EXT_STAT15

-

0x43C

Reserved

-

-

RESET_EXT_STAT16

R/W

0x440

Reset external status register 16 for
LCD_RST

0x8

see Table 183

RESET_EXT_STAT17

R/W

0x444

Reset external status register 17 for
USB0_RST

0x8

see Table 183

RESET_EXT_STAT18

R/W

0x448

Reset external status register 18 for
USB1_RST

0x8

see Table 183

RESET_EXT_STAT19

R/W

0x44C

Reset external status register 19 for
DMA_RST

0x8

see Table 183

RESET_EXT_STAT20

R/W

0x450

Reset external status register 20 for
SDIO_RST

0x8

see Table 183

RESET_EXT_STAT21

R/W

0x454

Reset external status register 21 for
EMC_RST

0x8

see Table 183

RESET_EXT_STAT22

R/W

0x458

Reset external status register 22 for
ETHERNET_RST

0x8

see Table 183

RESET_EXT_STAT23

-

0x45C

Reserved

-

-

RESET_EXT_STAT24

-

0x460

Reserved

-

-

RESET_EXT_STAT25

R/W

0x464

Reset external status register 25 for
FLASHA_RST

0x4

see Table 182

RESET_EXT_STAT26

-

0x468

Reserved

-

-

RESET_EXT_STAT27

R/W

0x46C

Reset external status register 27 for
EEPROM_RST

0x4

see Table 182

RESET_EXT_STAT28

R/W

0x470

Reset external status register 28 for
GPIO_RST

0x4

see Table 182

RESET_EXT_STAT29

R/W

0x474

Reset external status register 29 for
FLASHB_RST

0x4

see Table 182

RESET_EXT_STAT30

-

0x478

Reserved

-

-

RESET_EXT_STAT31

-

0x47C

Reserved

-

-

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Chapter 15: LPC43xx/LPC43Sxx Reset Generation Unit (RGU)

Table 170. Register overview: RGU (base address: 0x4005 3000) …continued
Name

Access

Address Description
offset

Reset value

Reference

RESET_EXT_STAT32

R/W

0x480

Reset external status register 32 for
TIMER0_RST

0x4

see Table 182

RESET_EXT_STAT33

R/W

0x484

Reset external status register 33 for
TIMER1_RST

0x4

see Table 182

RESET_EXT_STAT34

R/W

0x488

Reset external status register 34 for
TIMER2_RST

0x4

see Table 182

RESET_EXT_STAT35

R/W

0x48C

Reset external status register 35 for
TIMER3_RST

0x4

see Table 182

RESET_EXT_STAT36

R/W

0x490

Reset external status register 36 for
RITIMER_RST

0x4

see Table 182

RESET_EXT_STAT37

R/W

0x494

Reset external status register 37 for
SCT_RST

0x4

see Table 182

RESET_EXT_STAT38

R/W

0x498

Reset external status register 38 for
MOTOCONPWM_RST

0x4

see Table 182

RESET_EXT_STAT39

R/W

0x49C

Reset external status register 39 for
QEI_RST

0x4

see Table 182

RESET_EXT_STAT40

R/W

0x4A0

Reset external status register 40 for
ADC0_RST

0x4

see Table 182

RESET_EXT_STAT41

R/W

0x4A4

Reset external status register 41 for
ADC1_RST

0x4

see Table 182

RESET_EXT_STAT42

R/W

0x4A8

Reset external status register 42 for
DAC_RST

0x4

see Table 182

RESET_EXT_STAT43

-

0x4AC

Reserved

-

-

RESET_EXT_STAT44

R/W

0x4B0

Reset external status register 44 for
UART0_RST

0x4

see Table 182

RESET_EXT_STAT45

R/W

0x4B4

Reset external status register 45 for
UART1_RST

0x4

see Table 182

RESET_EXT_STAT46

R/W

0x4B8

Reset external status register 46 for
UART2_RST

0x4

see Table 182

RESET_EXT_STAT47

R/W

0x4BC

Reset external status register 47 for
UART3_RST

0x4

see Table 182

RESET_EXT_STAT48

R/W

0x4C0

Reset external status register 48 for
I2C0_RST

0x4

see Table 182

RESET_EXT_STAT49

R/W

0x4C4

Reset external status register 49 for
I2C1_RST

0x4

see Table 182

RESET_EXT_STAT50

R/W

0x4C8

Reset external status register 50 for
SSP0_RST

0x4

see Table 182

RESET_EXT_STAT51

R/W

0x4CC

Reset external status register 51 for
SSP1_RST

0x4

see Table 182

RESET_EXT_STAT52

R/W

0x4D0

Reset external status register 52 for
I2S_RST

0x4

see Table 182

RESET_EXT_STAT53

R/W

0x4D4

Reset external status register 53 for
SPIFI_RST

0x4

see Table 182

RESET_EXT_STAT54

R/W

0x4D8

Reset external status register 54 for
CAN1_RST

0x4

see Table 182

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Chapter 15: LPC43xx/LPC43Sxx Reset Generation Unit (RGU)

Table 170. Register overview: RGU (base address: 0x4005 3000) …continued
Name

Access

Address Description
offset

Reset value

Reference

RESET_EXT_STAT55

R/W

0x4DC

Reset external status register 55 for
CAN0_RST

0x4

see Table 182

RESET_EXT_STAT56

R/W

0x4E0

Reset external status register 56 for
M0APP_RST

0x8

see Table 183

RESET_EXT_STAT57

R/W

0x4E4

Reset external status register 57 for
SGPIO_RST

0x4

see Table 182

RESET_EXT_STAT58

R/W

0x4E8

Reset external status register 58 for
SPI_RST

0x4

see Table 182

RESET_EXT_STAT59

-

0x4EC

Reserved

-

-

RESET_EXT_STAT60

R/W

0x4F0

Reset external status register 60 for
ADCHS_RST

0x4

see Table 182

RESET_EXT_STAT61

-

0x4F4

Reserved

-

-

RESET_EXT_STAT62

-

0x4F8

Reserved

-

-

RESET_EXT_STAT63

-

0x4FC

Reserved

-

-

15.4.1 RGU reset control register
The RGU reset control register allows software to activate and clear individual reset
outputs. Each bit corresponds to an individual reset output, and writing a one activates
that output. The reset output is automatically de-activated after a fixed reset delay period
with the exception of the M0APP_RST. If the reset output has a manual release, it stays
activated once pulled low until a 0 is written to the appropriate bit in this register. This
applies whether the reset activation came from the Reset Control Register or any other
source.
Remark: The reset delay is counted in IRC clock cycles. If the core frequency CCLK is
much higher than the IRC frequency, add a software delay of fCCLK/fIRC clock cycles
between resetting and accessing any of the peripheral blocks.
Table 171. Reset control register 0 (RESET_CTRL0, address 0x4005 3100) bit description
Bit

Symbol

Description

Reset
value

Access

0

CORE_RST

Writing a one activates the reset. This bit is automatically cleared to 0
after one clock cycle.

0

W

1

PERIPH_RST

Writing a one activates the reset. This bit is automatically cleared to 0
after three clock cycles.

0

W

2

MASTER_RST

Writing a one activates the reset. This bit is automatically cleared to 0
after three clock cycles.

0

W

3

-

Reserved

0

-

4

WWDT_RST

Writing a one to this bit has no effect.

0

-

5

CREG_RST

Writing a one to this bit has no effect.

0

-

6

-

Reserved

0

-

7

-

Reserved

0

-

8

BUS_RST

Writing a one activates the reset. This bit is automatically cleared to 0
after one clock cycle. Do not use during normal operation

0

W

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Chapter 15: LPC43xx/LPC43Sxx Reset Generation Unit (RGU)

Table 171. Reset control register 0 (RESET_CTRL0, address 0x4005 3100) bit description …continued
Bit

Symbol

Description

Reset
value

Access

9

SCU_RST

Writing a one activates the reset. This bit is automatically cleared to 0
after one clock cycle.

0

W

10

-

Reserved

0

-

11

-

Reserved

0

-

12

M0_SUB_RST

Writing a one activates the reset. Writing a 0 clears the reset. This bit
must be cleared by software.

1

W

13

M4_RST

Writing a one activates the reset. This bit is automatically cleared to 0
after one clock cycle.

0

W

14

-

Reserved

0

-

15

-

Reserved

0

-

16

LCD_RST

Writing a one activates the reset. This bit is automatically cleared to 0
after one clock cycle.

0

W

17

USB0_RST

Writing a one activates the reset. This bit is automatically cleared to 0
after one clock cycle.

0

W

18

USB1_RST

Writing a one activates the reset. This bit is automatically cleared to 0
after one clock cycle.

0

W

19

DMA_RST

Writing a one activates the reset. This bit is automatically cleared to 0
after one clock cycle.

0

W

20

SDIO_RST

Writing a one activates the reset. This bit is automatically cleared to 0
after one clock cycle.

0

W

21

EMC_RST

Writing a one activates the reset. This bit is automatically cleared to 0
after one clock cycle.

0

W

22

ETHERNET_RST

Writing a one activates the reset. This bit is automatically cleared to 0
after one clock cycle.

0

W

23

-

Reserved

-

-

24

-

Reserved

-

-

25

FLASHA_RST

Writing a one activates the reset. This bit is automatically cleared to 0
after one clock cycle.

0

W

26

-

Reserved

-

-

27

EEPROM_RST

Writing a one activates the reset. This bit is automatically cleared to 0
after one clock cycle.

0

W

28

GPIO_RST

Writing a one activates the reset. This bit is automatically cleared to 0
after one clock cycle.

0

W

29

FLASHB_RST

Writing a one activates the reset. This bit is automatically cleared to 0
after one clock cycle.

0

W

30

-

Reserved

-

-

31

-

Reserved

-

-

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Table 172. Reset control register 1 (RESET_CTRL1, address 0x4005 3104) bit description
Bit

Symbol

Description

Reset
value

Access

0

TIMER0_RST

Writing a one activates the reset. This bit is automatically
cleared to 0 after one clock cycle.

0

W

1

TIMER1_RST

Writing a one activates the reset. This bit is automatically
cleared to 0 after one clock cycle.

0

W

2

TIMER2_RST

Writing a one activates the reset. This bit is automatically
cleared to 0 after one clock cycle.

0

W

3

TIMER3_RST

Writing a one activates the reset. This bit is automatically
cleared to 0 after one clock cycle.

0

W

4

RITIMER_RST

Writing a one activates the reset. This bit is automatically
cleared to 0 after one clock cycle.

0

W

5

SCT_RST

Writing a one activates the reset. This bit is automatically
cleared to 0 after one clock cycle.

0

W

6

MOTOCONPWM_RST

Writing a one activates the reset. This bit is automatically
cleared to 0 after one clock cycle.

0

W

7

QEI_RST

Writing a one activates the reset. This bit is automatically
cleared to 0 after one clock cycle.

0

W

8

ADC0_RST

Writing a one activates the reset. This bit is automatically
cleared to 0 after one clock cycle.

0

W

9

ADC1_RST

Writing a one activates the reset. This bit is automatically
cleared to 0 after one clock cycle.

0

W

10

DAC_RST

Writing a one activates the reset. This bit is automatically
cleared to 0 after one clock cycle.

0

W

11

-

Reserved

-

-

12

UART0_RST

Writing a one activates the reset. This bit is automatically
cleared to 0 after one clock cycle.

0

W

13

UART1_RST

Writing a one activates the reset. This bit is automatically
cleared to 0 after one clock cycle.

0

W

14

UART2_RST

Writing a one activates the reset. This bit is automatically
cleared to 0 after one clock cycle.

0

W

15

UART3_RST

Writing a one activates the reset. This bit is automatically
cleared to 0 after one clock cycle.

0

W

16

I2C0_RST

Writing a one activates the reset. This bit is automatically
cleared to 0 after one clock cycle.

0

W

17

I2C1_RST

Writing a one activates the reset. This bit is automatically
cleared to 0 after one clock cycle.

0

W

18

SSP0_RST

Writing a one activates the reset. This bit is automatically
cleared to 0 after one clock cycle.

0

W

19

SSP1_RST

Writing a one activates the reset. This bit is automatically
cleared to 0 after one clock cycle.

0

W

20

I2S_RST

Writing a one activates the reset. This bit is automatically
cleared to 0 after one clock cycle.

0

W

21

SPIFI_RST

Writing a one activates the reset. This bit is automatically
cleared to 0 after one clock cycle.

0

W

22

CAN1_RST

Writing a one activates the reset. This bit is automatically
cleared to 0 after one clock cycle.

0

W

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Chapter 15: LPC43xx/LPC43Sxx Reset Generation Unit (RGU)

Table 172. Reset control register 1 (RESET_CTRL1, address 0x4005 3104) bit description
…continued

Bit

Symbol

Description

Reset
value

Access

23

CAN0_RST

Writing a one activates the reset. This bit is automatically
cleared to 0 after one clock cycle.

0

W

24

M0APP_RST

Writing a one activates the reset. Writing a 0 clears the reset.
This bit must be cleared by software.

1

W

25

SGPIO_RST

Writing a one activates the reset. This bit is automatically
cleared to 0 after one clock cycle.

0

W

26

SPI_RST

Writing a one activates the reset. This bit is automatically
cleared to 0 after one clock cycle.

0

W

27

-

Reserved

-

-

28

ADCHS_RST

Writing a one activates the reset. This bit is automatically
cleared to 0 after one clock cycle.

0

W

29

-

Reserved

-

-

30

-

Reserved

-

-

31

-

Reserved

-

-

15.4.2 RGU reset status register
The reset status register shows which source (if any) caused the last reset activation per
individual reset output of the RGU. When one (or more) inputs of the RGU caused the
Reset Output to go active (indicated by value 01), the corresponding
RESET_EXT_STATUS register can be read, see Section 15.4.4.
The RESET_STATUS registers are cleared by writing 0 to each of the status bits.
Table 173. Reset status register 0 (RESET_STATUS0, address 0x4005 3110) bit description
Bit

Symbol

Description

Reset
value

Access

1:0

-

Reserved

-

-

3:2

PERIPH_RST

Status of the PERIPH_RST reset generator output

00

R/W

01

R/W

00 = No reset activated
01 = Reset output activated by input to the reset generator - this reset is
self-clearing
10 = Reserved
11 = Reset output activated by software write to RESET_CTRL register
5:4

MASTER_RST

Status of the MASTER_RST reset generator output
00 = No reset activated
01 = Reset output activated by input to the reset generator - this reset is
self-clearing
10 = Reserved
11 = Reset output activated by software write to RESET_CTRL register

7:6

-

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Table 173. Reset status register 0 (RESET_STATUS0, address 0x4005 3110) bit description
Bit

Symbol

Description

Reset
value

Access

9:8

WWDT_RST

Status of the WWDT_RST reset generator output

00

R/W

00

R/W

00 = No reset activated
01 = Reset output activated by input to the reset generator
10 = Reserved
11 = Reserved
11:10

CREG_RST

Status of the CREG_RST reset generator output
00 = No reset activated
01 = Reset output activated by input to the reset generator
10 = Reserved
11 = Reserved

13:12

-

Reserved

01

-

15:14

-

Reserved

01

-

17:16

BUS_RST

Status of the BUS_RST reset generator output

01

R/W

01

R/W

00 = No reset activated
01 = Reset output activated by input to the reset generator
10 = Reserved
11 = Reset output activated by software write to RESET_CTRL register
19:18

SCU_RST

Status of the SCU_RST reset generator output
00 = No reset activated
01 = Reset output activated by input to the reset generator
10 = Reserved
11 = Reset output activated by software write to RESET_CTRL register

21:20

-

Reserved

01

-

23:22

-

Reserved

01

-

25:24

M0SUB_RST

Status of the M0SUB_RST reset generator output

01

R/W

01

R/W

00 = No reset activated
01 = Reset output activated by input to the reset generator
10 = Reserved
11 = Reset output activated by software write to RESET_CTRL register
27:26

M4_RST

Status of the M4_RST reset generator output
00 = No reset activated
01 = Reset output activated by input to the reset generator
10 = Reserved
11 = Reset output activated by software write to RESET_CTRL register

29:28

-

Reserved

01

-

31:30

-

Reserved

01

-

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Chapter 15: LPC43xx/LPC43Sxx Reset Generation Unit (RGU)

Table 174. Reset status register 1 (RESET_STATUS1, address 0x4005 3114) bit description
Bit

Symbol

Description

Reset
value

Access

1:0

LCD_RST

Status of the LCD_RST reset generator output

01

R/W

01

R/W

01

R/W

01

R/W

01

R/W

01

R/W

01

R/W

00 = No reset activated
01 = Reset output activated by input to the reset generator
10 = Reserved
11 = Reset output activated by software write to RESET_CTRL register
3:2

USB0_RST

Status of the USB0_RST reset generator output
00 = No reset activated
01 = Reset output activated by input to the reset generator
10 = Reserved
11 = Reset output activated by software write to RESET_CTRL register

5:4

USB1_RST

Status of the USB1_RST reset generator output
00 = No reset activated
01 = Reset output activated by input to the reset generator
10 = Reserved
11 = Reset output activated by software write to RESET_CTRL register

7:6

DMA_RST

Status of the DMA_RST reset generator output
00 = No reset activated
01 = Reset output activated by input to the reset generator
10 = Reserved
11 = Reset output activated by software write to RESET_CTRL register

9:8

SDIO_RST

Status of the SDIO_RST reset generator output
00 = No reset activated
01 = Reset output activated by input to the reset generator
10 = Reserved
11 = Reset output activated by software write to RESET_CTRL register

11:10

EMC_RST

Status of the EMC_RST reset generator output
00 = No reset activated
01 = Reset output activated by input to the reset generator
10 = Reserved
11 = Reset output activated by software write to RESET_CTRL register

13:12

ETHERNET_RST

Status of the ETHERNET_RST reset generator output
00 = No reset activated
01 = Reset output activated by input to the reset generator
10 = Reserved
11 = Reset output activated by software write to RESET_CTRL register

15:14

-

Reserved

01

-

17:16

-

Reserved

01

-

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Chapter 15: LPC43xx/LPC43Sxx Reset Generation Unit (RGU)

Table 174. Reset status register 1 (RESET_STATUS1, address 0x4005 3114) bit description
…continued

Bit

Symbol

Description

Reset
value

Access

19:18

FLASHA_RST

Status of the FLASHA_RST reset generator output

01

-

00 = No reset activated
01 = Reset output activated by input to the reset generator
10 = Reserved
11 = Reset output activated by software write to RESET_CTRL register
21:20

-

Reserved

01

-

23:22

EEPROM_RST

Status of the EEPROM_RST reset generator output

01

-

01

R/W

01

-

00 = No reset activated
01 = Reset output activated by input to the reset generator
10 = Reserved
11 = Reset output activated by software write to RESET_CTRL register
25:24

GPIO_RST

Status of the GPIO_RST reset generator output
00 = No reset activated
01 = Reset output activated by input to the reset generator
10 = Reserved
11 = Reset output activated by software write to RESET_CTRL register

27:26

FLASHB_RST

Status of the FLASHB_RST reset generator output
00 = No reset activated
01 = Reset output activated by input to the reset generator
10 = Reserved
11 = Reset output activated by software write to RESET_CTRL register

29:28

-

Reserved

01

-

31:30

-

Reserved

01

-

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Chapter 15: LPC43xx/LPC43Sxx Reset Generation Unit (RGU)

Table 175. Reset status register 2 (RESET_STATUS2, address 0x4005 3118) bit description
Bit

Symbol

Description

Reset
value

Access

1:0

TIMER0_RST

Status of the TIMER0_RST reset generator output

01

R/W

01

R/W

01

R/W

01

R/W

01

R/W

01

R/W

01

R/W

01

R/W

00 = No reset activated
01 = Reset output activated by input to the reset generator
10 = Reserved
11 = Reset output activated by software write to RESET_CTRL register
3:2

TIMER1_RST

Status of the TIMER1_RST reset generator output
00 = No reset activated
01 = Reset output activated by input to the reset generator
10 = Reserved
11 = Reset output activated by software write to RESET_CTRL register

5:4

TIMER2_RST

Status of the TIMER2_RST reset generator output
00 = No reset activated
01 = Reset output activated by input to the reset generator
10 = Reserved
11 = Reset output activated by software write to RESET_CTRL register

7:6

TIMER3_RST

Status of the TIMER3_RST reset generator output
00 = No reset activated
01 = Reset output activated by input to the reset generator
10 = Reserved
11 = Reset output activated by software write to RESET_CTRL register

9:8

RITIMER_RST

Status of the RITIMER_RST reset generator output
00 = No reset activated
01 = Reset output activated by input to the reset generator
10 = Reserved
11 = Reset output activated by software write to RESET_CTRL register

11:10 SCT_RST

Status of the SCT_RST reset generator output
00 = No reset activated
01 = Reset output activated by input to the reset generator
10 = Reserved
11 = Reset output activated by software write to RESET_CTRL register

13:12 MOTOCONPWM_
RST

Status of the MOTOCONPWM_RST reset generator output
00 = No reset activated
01 = Reset output activated by input to the reset generator
10 = Reserved
11 = Reset output activated by software write to RESET_CTRL register

15:14 QEI_RST

Status of the QEI_RST reset generator output
00 = No reset activated
01 = Reset output activated by input to the reset generator
10 = Reserved
11 = Reset output activated by software write to RESET_CTRL register

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Chapter 15: LPC43xx/LPC43Sxx Reset Generation Unit (RGU)

Table 175. Reset status register 2 (RESET_STATUS2, address 0x4005 3118) bit description …continued
…continued

Bit

Symbol

17:16 ADC0_RST

Description

Reset
value

Access

Status of the ADC0_RST reset generator output

01

R/W

01

R/W

01

R/W

00 = No reset activated
01 = Reset output activated by input to the reset generator
10 = Reserved
11 = Reset output activated by software write to RESET_CTRL register
19:18 ADC1_RST

Status of the ADC1_RST reset generator output
00 = No reset activated
01 = Reset output activated by input to the reset generator
10 = Reserved
11 = Reset output activated by software write to RESET_CTRL register

21:20 DAC_RST

Status of the DAC_RST reset generator output
00 = No reset activated
01 = Reset output activated by input to the reset generator
10 = Reserved
11 = Reset output activated by software write to RESET_CTRL register

23:22 -

Reserved

01

R/W

25:24 UART0_RST

Status of the UART0_RST reset generator output

01

R/W

01

R/W

01

R/W

01

R/W

00 = No reset activated
01 = Reset output activated by input to the reset generator
10 = Reserved
11 = Reset output activated by software write to RESET_CTRL register
27:26 UART1_RST

Status of the UART1_RST reset generator output
00 = No reset activated
01 = Reset output activated by input to the reset generator
10 = Reserved
11 = Reset output activated by software write to RESET_CTRL register

29:28 UART2_RST

Status of the UART2_RST reset generator output
00 = No reset activated
01 = Reset output activated by input to the reset generator
10 = Reserved
11 = Reset output activated by software write to RESET_CTRL register

31:30 UART3_RST

Status of the UART3_RST reset generator output
00 = No reset activated
01 = Reset output activated by input to the reset generator
10 = Reserved
11 = Reset output activated by software write to RESET_CTRL register

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Chapter 15: LPC43xx/LPC43Sxx Reset Generation Unit (RGU)

Table 176. Reset status register 3 (RESET_STATUS3, address 0x4005 311C) bit description
Bit

Symbol

Description

Reset
value

Access

1:0

I2C0_RST

Status of the I2C0_RST reset generator output

01

R/W

01

R/W

01

R/W

01

R/W

01

R/W

01

R/W

01

R/W

01

R/W

00 = No reset activated
01 = Reset output activated by input to the reset generator
10 = Reserved
11 = Reset output activated by software write to RESET_CTRL register
3:2

I2C1_RST

Status of the I2C1_RST reset generator output
00 = No reset activated
01 = Reset output activated by input to the reset generator
10 = Reserved
11 = Reset output activated by software write to RESET_CTRL register

5:4

SSP0_RST

Status of the SSP0_RST reset generator output
00 = No reset activated
01 = Reset output activated by input to the reset generator
10 = Reserved
11 = Reset output activated by software write to RESET_CTRL register

7:6

SSP1_RST

Status of the SSP1_RST reset generator output
00 = No reset activated
01 = Reset output activated by input to the reset generator
10 = Reserved
11 = Reset output activated by software write to RESET_CTRL register

9:8

I2S_RST

Status of the I2S_RST reset generator output
00 = No reset activated
01 = Reset output activated by input to the reset generator
10 = Reserved
11 = Reset output activated by software write to RESET_CTRL register

11:10

SPIFI_RST

Status of the SPIFI_RST reset generator output
00 = No reset activated
01 = Reset output activated by input to the reset generator
10 = Reserved
11 = Reset output activated by software write to RESET_CTRL register

13:12

CAN1_RST

Status of the CAN1_RST reset generator output
00 = No reset activated
01 = Reset output activated by input to the reset generator
10 = Reserved
11 = Reset output activated by software write to RESET_CTRL register

15:14

CAN0_RST

Status of the CAN0_RST reset generator output
00 = No reset activated
01 = Reset output activated by input to the reset generator
10 = Reserved
11 = Reset output activated by software write to RESET_CTRL register

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Chapter 15: LPC43xx/LPC43Sxx Reset Generation Unit (RGU)

Table 176. Reset status register 3 (RESET_STATUS3, address 0x4005 311C) bit description
…continued

Bit

Symbol

Description

Reset
value

Access

17:16

M0APP_RST

Status of the M0APP_RST reset generator output

11

R/W

01

R/W

01

R/W

00 = No reset activated
01 = Reset output activated by input to the reset generator
10 = Reserved
11 = Reset output activated by software write to RESET_CTRL register
19:18

SGPIO_RST

Status of the SGPIO_RST reset generator output
00 = No reset activated
01 = Reset output activated by input to the reset generator
10 = Reserved
11 = Reset output activated by software write to RESET_CTRL register

21:20

SPI_RST

Status of the SPI_RST reset generator output
00 = No reset activated
01 = Reset output activated by input to the reset generator
10 = Reserved
11 = Reset output activated by software write to RESET_CTRL register

23:22

-

Reserved

01

-

25:24

ADCHS_RST

Status of the ADCHS_RST reset generator output

01

R/W

00 = No reset activated
01 = Reset output activated by input to the reset generator
10 = Reserved
11 = Reset output activated by software write to RESET_CTRL register
27:26

-

Reserved

01

-

29:28

-

Reserved

01

-

31:30

-

Reserved

01

-

15.4.3 RGU reset active status register
The reset active status register shows the current value of the reset outputs of the RGU.
Note that the resets are active LOW.
Table 177. Reset active status register 0 (RESET_ACTIVE_STATUS0, address 0x4005 3150)
bit description
Bit

Symbol

0

CORE_RST

Description

Reset
value

Access

Current status of the CORE_RST

1

R

1

R

1

R

0 = Reset asserted
1 = No reset
1

PERIPH_RST

Current status of the PERIPH_RST
0 = Reset asserted
1 = No reset

2

MASTER_RST

Current status of the MASTER_RST
0 = Reset asserted
1 = No reset

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Chapter 15: LPC43xx/LPC43Sxx Reset Generation Unit (RGU)

Table 177. Reset active status register 0 (RESET_ACTIVE_STATUS0, address 0x4005 3150)
bit description …continued
Bit

Symbol

Description

Reset
value

Access

3

-

Reserved

1

4

WWDT_RST

Current status of the WWDT_RS

1

R

1

R

0 = Reset asserted
1 = No reset
5

CREG_RST

Current status of the CREG_RST
0 = Reset asserted
1 = No reset

6

-

Reserved

1

7

-

Reserved

1

8

BUS_RST

Current status of the BUS_RST

1

R

1

R

0 = Reset asserted
1 = No reset
9

SCU_RST

Current status of the SCU_RST
0 = Reset asserted
1 = No reset

10

-

Reserved

1

-

11

-

Reserved

1

-

12

M0SUB_RST

Current status of the M0SUB_RST

0

R

1

R

0 = Reset asserted
1 = No reset
13

M4_RST

Current status of the M4_RST
0 = Reset asserted
1 = No reset

14

-

Reserved

1

15

-

Reserved

1

16

LCD_RST

Current status of the LCD_RST

1

R

1

R

1

R

1

R

1

R

0 = Reset asserted
1 = No reset
17

USB0_RST

Current status of the USB0_RST
0 = Reset asserted
1 = No reset

18

USB1_RST

Current status of the USB1_RST
0 = Reset asserted
1 = No reset

19

DMA_RST

Current status of the DMA_RST
0 = Reset asserted
1 = No reset

20

SDIO_RST

Current status of the SDIO_RST
0 = Reset asserted
1 = No reset

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Chapter 15: LPC43xx/LPC43Sxx Reset Generation Unit (RGU)

Table 177. Reset active status register 0 (RESET_ACTIVE_STATUS0, address 0x4005 3150)
bit description …continued
Bit

Symbol

21

EMC_RST

Description

Reset
value

Access

Current status of the EMC_RST

1

R

1

R

0 = Reset asserted
1 = No reset
22

ETHERNET_RST

Current status of the
ETHERNET_RST
0 = Reset asserted
1 = No reset

23

-

Reserved

1

-

24

-

Reserved

1

-

25

FLASHA_RST

Current status of the FLASHA_RST

1

R

Reserved

1

-

Current status of the EEPROM_RST

1

R

1

R

1

R

0 = Reset asserted
1 = No reset
26

-

27

EEPROM_RST

0 = Reset asserted
1 = No reset
28

GPIO_RST

Current status of the GPIO_RST
0 = Reset asserted
1 = No reset

29

FLASHB_RST

Current status of the FLASHB_RST
0 = Reset asserted
1 = No reset

30

-

Reserved

1

-

31

-

Reserved

1

-

Table 178. Reset active status register 1 (RESET_ACTIVE_STATUS1, address 0x4005 3154)
bit description
Bit

Symbol

Description

Reset
value

Access

0

TIMER0_RST

Current status of the TIMER0_RST

1

R

1

R

1

R

1

R

0 = Reset asserted
1 = No reset
1

TIMER1_RST

Current status of the TIMER1_RST
0 = Reset asserted
1 = No reset

2

TIMER2_RST

Current status of the TIMER2_RST
0 = Reset asserted
1 = No reset

3

TIMER3_RST

Current status of the TIMER3_RST
0 = Reset asserted
1 = No reset

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Chapter 15: LPC43xx/LPC43Sxx Reset Generation Unit (RGU)

Table 178. Reset active status register 1 (RESET_ACTIVE_STATUS1, address 0x4005 3154)
bit description …continued
Bit

Symbol

4

RITIMER_RST

Description

Reset
value

Access

Current status of the RITIMER_RST

1

R

1

R

1

R

1

R

1

R

1

R

1

R

-

-

1

R

1

R

1

R

1

R

1

R

1

R

0 = Reset asserted
1 = No reset
5

SCT_RST

Current status of the SCT_RST
0 = Reset asserted
1 = No reset

6

MOTOCONPWM_RST

Current status of the
MOTOCONPWM_RST
0 = Reset asserted
1 = No reset

7

QEI_RST

Current status of the QEI_RST
0 = Reset asserted
1 = No reset

8

ADC0_RST

Current status of the ADC0_RST
0 = Reset asserted
1 = No reset

9

ADC1_RST

Current status of the ADC1_RST
0 = Reset asserted
1 = No reset

10

DAC_RST

Current status of the DAC_RST
0 = Reset asserted
1 = No reset

11

-

12

UART0_RST

Current status of the UART0_RST
0 = Reset asserted
1 = No reset

13

UART1_RST

Current status of the UART1_RST
0 = Reset asserted
1 = No reset

14

UART2_RST

Current status of the UART2_RST
0 = Reset asserted
1 = No reset

15

UART3_RST

Current status of the UART3_RST
0 = Reset asserted
1 = No reset

16

I2C0_RST

Current status of the I2C0_RST
0 = Reset asserted
1 = No reset

17

I2C1_RST

Current status of the I2C1_RST
0 = Reset asserted
1 = No reset

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Chapter 15: LPC43xx/LPC43Sxx Reset Generation Unit (RGU)

Table 178. Reset active status register 1 (RESET_ACTIVE_STATUS1, address 0x4005 3154)
bit description …continued
Bit

Symbol

Description

Reset
value

Access

18

SSP0_RST

Current status of the SSP0_RST

1

R

1

R

1

R

1

R

1

R

1

R

0

R

1

R

1

R

0 = Reset asserted
1 = No reset
19

SSP1_RST

Current status of the SSP1_RST
0 = Reset asserted
1 = No reset

20

I2S_RST

Current status of the I2S_RST
0 = Reset asserted
1 = No reset

21

SPIFI_RST

Current status of the SPIFI_RST
0 = Reset asserted
1 = No reset

22

CAN1_RST

Current status of the CAN1_RST
0 = Reset asserted
1 = No reset

23

CAN0_RST

Current status of the CAN0_RST
0 = Reset asserted
1 = No reset

24

M0APP_RST

Current status of the M0APP_RST
0 = Reset asserted
1 = No reset

25

SGPIO_RST

Current status of the SGPIO_RST
0 = Reset asserted
1 = No reset

26

SPI_RST

Current status of the SPI_RST
0 = Reset asserted
1 = No reset

27

-

Reserved.

-

-

28

ADCHS_RST

Current status of the ADCHS_RST

1

R

0 = Reset asserted
1 = No reset
29

-

Reserved.

-

-

30

-

Reserved.

-

-

31

-

Reserved.

-

-

15.4.4 Reset external status registers
The external status registers indicate which input to the reset generator caused the reset
output to go active. Any bit set to 1 in the Reset external status register should be cleared
to 0 after a read operation to allow the detection of the next reset.

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Chapter 15: LPC43xx/LPC43Sxx Reset Generation Unit (RGU)

All reset generators except the WWDT time-out reset, the BOD reset, the reset signal
from the PMU, and the software reset, which have no inputs, have an associated external
status register. All reset generators have only one input which, depending on the
hierarchy, can be either the CORE_RST, the PERIPHERAL_RST, or the MASTER_RST.
Note that the external status register does not show whether or not the reset was
activated by a software reset. The software reset is indicated in the reset status registers 0
to 3 (see Table 173 to Table 176).

15.4.4.1 Reset external status register 1 for PERIPH_RST
This register shows whether or not the CORE_RST output has activated the
PERIPH_RST. A reset generated from the CORE_RST is the only possible reset source
for the PERIPH_RST aside from a software reset by writing to the RESET_CTRL register.
Table 179. Reset external status register 1 (RESET_EXT_STAT1, address 0x4005 3404) bit
description
Bit

Symbol

Description

Reset
value

0

-

Reserved. Do not modify; read as logic 0.

0

1

CORE_RESET Reset activated by CORE_RST output. Write 0 to 0
clear.

Access
R/W

0 = Reset not activated
1 = Reset activated
31:2

-

Reserved. Do not modify; read as logic 0.

0

-

15.4.4.2 Reset external status register 2 for MASTER_RST
Table 180. Reset external status register 2 (RESET_EXT_STAT2, address 0x4005 3408) bit
description
Bit

Symbol

Description

Reset
value

Access

1:0

-

Reserved. Do not modify; read as logic 0.

0

-

2

PERIPHERAL_RESET Reset activated by PERIPHERAL_RST
output. Write 0 to clear.

1

R/W

0

-

0 = Reset not activated
1 = Reset activated
31:3

-

Reserved. Do not modify; read as logic 0.

15.4.4.3 Reset external status register 5 for CREG_RST
Table 181. Reset external status register 5 (RESET_EXT_STAT5, address 0x4005 3414) bit
description
Bit

Symbol

Description

Reset
value

Access

0

-

Reserved. Do not modify; read as logic 0.

0

-

1

CORE_RESET

Reset activated by CORE_RST output. Write
0 to clear.

0

R/W

0

-

0 = Reset not activated
1 = Reset activated
31:2
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Reserved. Do not modify; read as logic 0.
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Chapter 15: LPC43xx/LPC43Sxx Reset Generation Unit (RGU)

15.4.4.4 Reset external status registers for PERIPHERAL_RESET
Refer to Table 170 for reset generators which have the PERIPH_RST output as reset
source.
Table 182. Reset external status registers x (RESET_EXT_STATx, address 0x4005 34xx) bit
description
Bit

Symbol

Description

1:0

-

Reserved. Do not modify; read as logic 0.

2

PERIPHERAL_RESET Reset activated by PERIPHERAL_RST
output. Write 0 to clear.

Reset
value

Access

0

-

1

R/W

0

-

0 = Reset not activated
1 = Reset activated
31:3

-

Reserved. Do not modify; read as logic 0.

15.4.4.5 Reset external status registers for MASTER_RESET
Refer to Table 170 for reset generators which have the MASTER_RST output as reset
source. These are the ARM Cortex-M4 core, the ARM Cortex-M0 cores, the LCD
controller, the USB0, the GPDMA, the SD/MMC controller, the external memory controller,
and the Ethernet controller.
The reset value is dependent on the peripheral, see Table 170.
Table 183. Reset external status registers y (RESET_EXT_STATy, address 0x4005 34yy) bit
description
Bit

Symbol

Description

Reset
value

Access

2:0

-

Reserved. Do not modify; read as logic 0.

0

-

3

MASTER_RESET

Reset activated by MASTER_RST output.
Write 0 to clear.

1

R/W

0

-

0 = Reset not activated
1 = Reset activated
31:4

-

Reserved. Do not modify; read as logic 0.

15.5 Functional description
15.5.1 Determine the cause of a core reset
1. Use a flag in internal RAM to determine the cause of a core reset.
a. Check the value of a flag at the start of execution. Possible flag values are:
i. !=0xAA55 FF01 && !=0xAA55 FF02  power on reset (POR)
ii.0xAA55 FF01  external reset signal (RESET)
iii.0xAA55 FF02  RGU generated core reset
b. After checking the flag, write a value of 0xAA55 FF01 to this flag.
c. Before performing an RGU generated core reset write a value of 0xAA55 FF02 to
this flag.
2. Use bits in the event router registers to determine the cause of a core reset.
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Chapter 15: LPC43xx/LPC43Sxx Reset Generation Unit (RGU)

a. Check the state of the HILO, EDGE registers, and the RESET_E and RESET_ST
bits in the EDGE and STATUS registers
i. HILO==0 & EDGE==0  power on reset
ii. RESET_E==1 && RESET_ST==1  external reset input (RESET)
b. Setup the event router to detect RESET:
i. RESET_L = 0 // detect a low level (this is the bit's reset value)
ii. RESET_E = 1 // detect a falling edge
iii. RESET_CLRST = 1 // clear the previous event

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Chapter 16: LPC43xx/LPC43Sxx Pin configuration
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User manual

16.1 How to read this chapter
This chapter applies to all parts.

16.2 Pin description
On the LPC43xx/LPC43Sxx, digital pins are grouped into 16 pin groups, named P0 to P9
and PA to PF, with up to 20 pins used per group. Each digital pin may support up to eight
different digital pin functions, including General Purpose I/O (GPIO), selectable through
the SCU pin configuration registers. Some digital pins support an additional analog
function selectable through the ENAIO registers in the SCU.
Remark: Note that the pin name is not indicative of the GPIO port assigned to it.

16.2.1 LPC4350/30/20/10/LPC43S50/S30/S20 Pin description
Remark: These parts contain two 10-bit ADCs (ADC0 and ADC1). The input channels of
ADC0 and ADC1 are combined in such a way that channel 0 inputs (named ADC0_0 and
ADC1_0) are tied together and connected to both, channel 0 on ADC0 and channel 0 on
ADC1, channel 1 inputs (named ADC0_1 and ADC1_1) are tied together and connected
to channel 1 on ADC0 and ADC1, and so forth. There are eight ADC channels total for the
two ADCs.

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Chapter 16: LPC43xx/LPC43Sxx Pin configuration

Type

32

Description

[1]

LQFP144

G2

Reset state

TFBGA100

TFBGA180

Symbol

LBGA256

Table 184. LPC4350/30/20/10 and LPC43S50/S30/S20 pin descriptions
LCD, Ethernet, USB0, and USB1 functions are not available on all parts.

Multiplexed digital pins
P0_0

P0_1

L3

M2

K3

K2

G1

34

[2]

[2]

N;
PU

N;
PU

I/O

GPIO0[0] — General purpose digital input/output pin.

I/O

SSP1_MISO — Master In Slave Out for SSP1.

I

ENET_RXD1 — Ethernet receive data 1 (RMII/MII interface).

I/O

SGPIO0 — General purpose digital input/output pin.

-

R — Function reserved.

-

R — Function reserved.

I/O

I2S0_TX_WS — Transmit Word Select. It is driven by the
master and received by the slave. Corresponds to the signal
WS in the I2S-bus specification.

I/O

I2S1_TX_WS — Transmit Word Select. It is driven by the
master and received by the slave. Corresponds to the signal
WS in the I2S-bus specification.

I/O

GPIO0[1] — General purpose digital input/output pin.

I/O

SSP1_MOSI — Master Out Slave in for SSP1.

I

ENET_COL — Ethernet Collision detect (MII interface).

I/O

SGPIO1 — General purpose digital input/output pin.

-

R — Function reserved.

-

R — Function reserved.
ENET_TX_EN — Ethernet transmit enable (RMII/MII
interface).

P1_0

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P2

L1

H1

38

[2]

N;
PU

I/O

I2S1_TX_SDA — I2S1 transmit data. It is driven by the
transmitter and read by the receiver. Corresponds to the signal
SD in the I2S-bus specification.

I/O

GPIO0[4] — General purpose digital input/output pin.

I

CTIN_3 — SCT input 3. Capture input 1 of timer 1.

I/O

EMC_A5 — External memory address line 5.

-

R — Function reserved.

-

R — Function reserved.

I/O

SSP0_SSEL — Slave Select for SSP0.

I/O

SGPIO7 — General purpose digital input/output pin.

-

R — Function reserved.

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Chapter 16: LPC43xx/LPC43Sxx Pin configuration

P1_2

P1_3

P1_4

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K2

42

R3

P5

T3

N2

M2

P2

K1

J1

J2

43

44

47

[2]

[2]

[2]

[2]

N;
PU

N;
PU

N;
PU

N;
PU

Type

N1

Description

[1]

LQFP144

R2

Reset state

TFBGA100

P1_1

TFBGA180

Symbol

LBGA256

Table 184. LPC4350/30/20/10 and LPC43S50/S30/S20 pin descriptions …continued
LCD, Ethernet, USB0, and USB1 functions are not available on all parts.

I/O

GPIO0[8] — General purpose digital input/output pin. Boot pin
(see Table 22).

O

CTOUT_7 — SCT output 7. Match output 3 of timer 1.

I/O

EMC_A6 — External memory address line 6.

I/O

SGPIO8 — General purpose digital input/output pin.

-

R — Function reserved.

I/O

SSP0_MISO — Master In Slave Out for SSP0.

-

R — Function reserved.

-

R — Function reserved.

I/O

GPIO0[9] — General purpose digital input/output pin. Boot pin
(see Table 22).

O

CTOUT_6 — SCT output 6. Match output 2 of timer 1.

I/O

EMC_A7 — External memory address line 7.

I/O

SGPIO9 — General purpose digital input/output pin.

-

R — Function reserved.

I/O

SSP0_MOSI — Master Out Slave in for SSP0.

-

R — Function reserved.

-

R — Function reserved.

I/O

GPIO0[10] — General purpose digital input/output pin.

O

CTOUT_8 — SCT output 8. Match output 0 of timer 2.

I/O

SGPIO10 — General purpose digital input/output pin.

O

EMC_OE — LOW active Output Enable signal.

O

USB0_IND1 — USB0 port indicator LED control
output 1.

I/O

SSP1_MISO — Master In Slave Out for SSP1.

-

R — Function reserved.

O

SD_RST — SD/MMC reset signal for MMC4.4 card.

I/O

GPIO0[11] — General purpose digital input/output pin.

O

CTOUT_9 — SCT output 9. Match output 3 of timer 3.

I/O

SGPIO11 — General purpose digital input/output pin.

O

EMC_BLS0 — LOW active Byte Lane select signal 0.

O

USB0_IND0 — USB0 port indicator LED control output 0.

I/O

SSP1_MOSI — Master Out Slave in for SSP1.

-

R — Function reserved.

O

SD_VOLT1 — SD/MMC bus voltage select output 1.

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NXP Semiconductors

Chapter 16: LPC43xx/LPC43Sxx Pin configuration

P1_6

P1_7

J4

48

T4

T5

P3

N4

K4

G4

49

50

[2]

[2]

[2]

N;
PU

N;
PU

N;
PU

Type

N3

Description

[1]

LQFP144

R5

Reset state

TFBGA100

P1_5

TFBGA180

Symbol

LBGA256

Table 184. LPC4350/30/20/10 and LPC43S50/S30/S20 pin descriptions …continued
LCD, Ethernet, USB0, and USB1 functions are not available on all parts.

I/O

GPIO1[8] — General purpose digital input/output pin.

O

CTOUT_10 — SCT output 10. Match output 2 of timer 2.

-

R — Function reserved.

O

EMC_CS0 — LOW active Chip Select 0 signal.

I

USB0_PWR_FAULT — Port power fault signal indicating
overcurrent condition; this signal monitors over-current on the
USB bus (external circuitry required to detect over-current
condition).

I/O

SSP1_SSEL — Slave Select for SSP1.

I/O

SGPIO15 — General purpose digital input/output pin.

O

SD_POW — SD/MMC power monitor output.

I/O

GPIO1[9] — General purpose digital input/output pin.

I

CTIN_5 — SCT input 5. Capture input 2 of timer 2.

-

R — Function reserved.

O

EMC_WE — LOW active Write Enable signal.

-

R — Function reserved.

-

R — Function reserved.

I/O

SGPIO14 — General purpose digital input/output pin.

I/O

SD_CMD — SD/MMC command signal.

I/O

GPIO1[0] — General purpose digital input/output pin.

I

U1_DSR — Data Set Ready input for UART1.

O

CTOUT_13 — SCT output 13. Match output 3 of timer 3.

I/O

EMC_D0 — External memory data line 0.

O

USB0_PPWR — VBUS drive signal (towards external charge
pump or power management unit); indicates that VBUS must
be driven (active HIGH).
Add a pull-down resistor to disable the power switch at reset.
This signal has opposite polarity compared to the USB_PPWR
used on other NXP LPC parts.

UM10503

User manual

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

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NXP Semiconductors

Chapter 16: LPC43xx/LPC43Sxx Pin configuration

P1_9

P1_10

P1_11

UM10503

User manual

H5

51

T7

R8

T9

N5

N6

P8

J5

H6

J7

52

53

55

[2]

[2]

[2]

[2]

N;
PU

N;
PU

N;
PU

N;
PU

Type

M5

Description

[1]

LQFP144

R7

Reset state

TFBGA100

P1_8

TFBGA180

Symbol

LBGA256

Table 184. LPC4350/30/20/10 and LPC43S50/S30/S20 pin descriptions …continued
LCD, Ethernet, USB0, and USB1 functions are not available on all parts.

I/O

GPIO1[1] — General purpose digital input/output pin.

O

U1_DTR — Data Terminal Ready output for UART1.

O

CTOUT_12 — SCT output 12. Match output 3 of
timer 3.

I/O

EMC_D1 — External memory data line 1.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

O

SD_VOLT0 — SD/MMC bus voltage select output 0.

I/O

GPIO1[2] — General purpose digital input/output pin.

O

U1_RTS — Request to Send output for UART1.

O

CTOUT_11 — SCT output 11. Match output 3 of timer 2.

I/O

EMC_D2 — External memory data line 2.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

I/O

SD_DAT0 — SD/MMC data bus line 0.

I/O

GPIO1[3] — General purpose digital input/output pin.

I

U1_RI — Ring Indicator input for UART1.

O

CTOUT_14 — SCT output 14. Match output 2 of timer 3.

I/O

EMC_D3 — External memory data line 3.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

I/O

SD_DAT1 — SD/MMC data bus line 1.

I/O

GPIO1[4] — General purpose digital input/output pin.

I

U1_CTS — Clear to Send input for UART1.

O

CTOUT_15 — SCT output 15. Match output 3 of timer 3.

I/O

EMC_D4 — External memory data line 4.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

I/O

SD_DAT2 — SD/MMC data bus line 2.

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253 of 1444

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NXP Semiconductors

Chapter 16: LPC43xx/LPC43Sxx Pin configuration

P1_13

P1_14

P1_15

UM10503

User manual

K7

56

R10

R11

T12

L8

K7

P11

H8

J8

K8

60

61

62

[2]

[2]

[2]

[2]

N;
PU

N;
PU

N;
PU

N;
PU

Type

P7

Description

[1]

LQFP144

R9

Reset state

TFBGA100

P1_12

TFBGA180

Symbol

LBGA256

Table 184. LPC4350/30/20/10 and LPC43S50/S30/S20 pin descriptions …continued
LCD, Ethernet, USB0, and USB1 functions are not available on all parts.

I/O

GPIO1[5] — General purpose digital input/output pin.

I

U1_DCD — Data Carrier Detect input for UART1.

-

R — Function reserved.

I/O

EMC_D5 — External memory data line 5.

I

T0_CAP1 — Capture input 1 of timer 0.

-

R — Function reserved.

I/O

SGPIO8 — General purpose digital input/output pin.

I/O

SD_DAT3 — SD/MMC data bus line 3.

I/O

GPIO1[6] — General purpose digital input/output pin.

O

U1_TXD — Transmitter output for UART1.

-

R — Function reserved.

I/O

EMC_D6 — External memory data line 6.

I

T0_CAP0 — Capture input 0 of timer 0.

-

R — Function reserved.

I/O

SGPIO9 — General purpose digital input/output pin.

I

SD_CD — SD/MMC card detect input.

I/O

GPIO1[7] — General purpose digital input/output pin.

I

U1_RXD — Receiver input for UART1.

-

R — Function reserved.

I/O

EMC_D7 — External memory data line 7.

O

T0_MAT2 — Match output 2 of timer 0.

-

R — Function reserved.

I/O

SGPIO10 — General purpose digital input/output pin.

-

R — Function reserved.

I/O

GPIO0[2] — General purpose digital input/output pin.

O

U2_TXD — Transmitter output for USART2.

I/O

SGPIO2 — General purpose digital input/output pin.

I

ENET_RXD0 — Ethernet receive data 0 (RMII/MII interface).

O

T0_MAT1 — Match output 1 of timer 0.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

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254 of 1444

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NXP Semiconductors

Chapter 16: LPC43xx/LPC43Sxx Pin configuration

P1_17

P1_18

P1_19

UM10503

User manual

H9

64

M8

N12

M11

L6

N10

N9

H10 66

J10

K9

67

68

[2]

[3]

[2]

[2]

N;
PU

N;
PU

N;
PU

N;
PU

Type

L5

Description

[1]

LQFP144

M7

Reset state

TFBGA100

P1_16

TFBGA180

Symbol

LBGA256

Table 184. LPC4350/30/20/10 and LPC43S50/S30/S20 pin descriptions …continued
LCD, Ethernet, USB0, and USB1 functions are not available on all parts.

I/O

GPIO0[3] — General purpose digital input/output pin.

I

U2_RXD — Receiver input for USART2.

I/O

SGPIO3 — General purpose digital input/output pin.

I

ENET_CRS — Ethernet Carrier Sense (MII interface).

O

T0_MAT0 — Match output 0 of timer 0.

-

R — Function reserved.

-

R — Function reserved.

I

ENET_RX_DV — Ethernet Receive Data Valid (RMII/MII
interface).

I/O

GPIO0[12] — General purpose digital input/output pin.

I/O

U2_UCLK — Serial clock input/output for USART2 in
synchronous mode.

-

R — Function reserved.

I/O

ENET_MDIO — Ethernet MIIM data input and output.

I

T0_CAP3 — Capture input 3 of timer 0.

O

CAN1_TD — CAN1 transmitter output.

I/O

SGPIO11 — General purpose digital input/output pin.

-

R — Function reserved.

I/O

GPIO0[13] — General purpose digital input/output pin.

I/O

U2_DIR — RS-485/EIA-485 output enable/direction control for
USART2.

-

R — Function reserved.

O

ENET_TXD0 — Ethernet transmit data 0 (RMII/MII interface).

O

T0_MAT3 — Match output 3 of timer 0.

I

CAN1_RD — CAN1 receiver input.

I/O

SGPIO12 — General purpose digital input/output pin.

-

R — Function reserved.

I

ENET_TX_CLK (ENET_REF_CLK) — Ethernet Transmit
Clock (MII interface) or Ethernet Reference Clock (RMII
interface).

I/O

SSP1_SCK — Serial clock for SSP1.

-

R — Function reserved.

-

R — Function reserved.

O

CLKOUT — Clock output pin.

-

R — Function reserved.

O

I2S0_RX_MCLK — I2S receive master clock.

I/O

I2S1_TX_SCK — Transmit Clock. It is driven by the master
and received by the slave. Corresponds to the signal SCK in
the I2S-bus specification.

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255 of 1444

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NXP Semiconductors

Chapter 16: LPC43xx/LPC43Sxx Pin configuration

P2_0

T16

N14

G10 75

[2]

[2]

N;
PU

N;
PU

Type

K10 70

Description

[1]

J10

Reset state

M10

LQFP144

TFBGA100

P1_20

TFBGA180

Symbol

LBGA256

Table 184. LPC4350/30/20/10 and LPC43S50/S30/S20 pin descriptions …continued
LCD, Ethernet, USB0, and USB1 functions are not available on all parts.

I/O

GPIO0[15] — General purpose digital input/output pin.

I/O

SSP1_SSEL — Slave Select for SSP1.

-

R — Function reserved.

O

ENET_TXD1 — Ethernet transmit data 1 (RMII/MII interface).

I

T0_CAP2 — Capture input 2 of timer 0.

-

R — Function reserved.

I/O

SGPIO13 — General purpose digital input/output pin.

-

R — Function reserved.

I/O

SGPIO4 — General purpose digital input/output pin.

O

U0_TXD — Transmitter output for USART0.

I/O

EMC_A13 — External memory address line 13.

O

USB0_PPWR — VBUS drive signal (towards external charge
pump or power management unit); indicates that VBUS must
be driven (active HIGH).
Add a pull-down resistor to disable the power switch at reset.
This signal has opposite polarity compared to the USB_PPWR
used on other NXP LPC parts.

P2_1

UM10503

User manual

N15

M13 G7

81

[2]

N;
PU

I/O

GPIO5[0] — General purpose digital input/output pin.

-

R — Function reserved.

I

T3_CAP0 — Capture input 0 of timer 3.

O

ENET_MDC — Ethernet MIIM clock.

I/O

SGPIO5 — General purpose digital input/output pin.

I

U0_RXD — Receiver input for USART0.

I/O

EMC_A12 — External memory address line 12.

I

USB0_PWR_FAULT — Port power fault signal indicating
overcurrent condition; this signal monitors over-current on the
USB bus (external circuitry required to detect over-current
condition).

I/O

GPIO5[1] — General purpose digital input/output pin.

-

R — Function reserved.

I

T3_CAP1 — Capture input 1 of timer 3.

-

R — Function reserved.

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256 of 1444

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NXP Semiconductors

Chapter 16: LPC43xx/LPC43Sxx Pin configuration

P2_3

F5

84

J12

G11

D8

87

[2]

[3]

N;
PU

N;
PU

Type

L13

Description

[1]

LQFP144

M15

Reset state

TFBGA100

P2_2

TFBGA180

Symbol

LBGA256

Table 184. LPC4350/30/20/10 and LPC43S50/S30/S20 pin descriptions …continued
LCD, Ethernet, USB0, and USB1 functions are not available on all parts.

I/O

SGPIO6 — General purpose digital input/output pin.

I/O

U0_UCLK — Serial clock input/output for USART0 in
synchronous mode.

I/O

EMC_A11 — External memory address line 11.

O

USB0_IND1 — USB0 port indicator LED control output 1.

I/O

GPIO5[2] — General purpose digital input/output pin.

I

CTIN_6 — SCT input 6. Capture input 1 of timer 3.

I

T3_CAP2 — Capture input 2 of timer 3.

-

R — Function reserved.

I/O

SGPIO12 — General purpose digital input/output pin.

I/O

I2C1_SDA — I2C1 data input/output (this pin does not use a
specialized I2C pad).

O

U3_TXD — Transmitter output for USART3.

I

CTIN_1 — SCT input 1. Capture input 1 of timer 0. Capture
input 1 of timer 2.

I/O

GPIO5[3] — General purpose digital input/output pin.

-

R — Function reserved.

O

T3_MAT0 — Match output 0 of timer 3.

O

USB0_PPWR — VBUS drive signal (towards external charge
pump or power management unit); indicates that VBUS must
be driven (active HIGH).
Add a pull-down resistor to disable the power switch at reset.
This signal has opposite polarity compared to the USB_PPWR
used on other NXP LPC parts.

P2_4

UM10503

User manual

K11

L9

D9

88

[3]

N;
PU

I/O

SGPIO13 — General purpose digital input/output pin.

I/O

I2C1_SCL — I2C1 clock input/output (this pin does not use a
specialized I2C pad).

I

U3_RXD — Receiver input for USART3.

I

CTIN_0 — SCT input 0. Capture input 0 of timer 0, 1, 2, 3.

I/O

GPIO5[4] — General purpose digital input/output pin.

-

R — Function reserved.

O

T3_MAT1 — Match output 1 of timer 3.

I

USB0_PWR_FAULT — Port power fault signal indicating
overcurrent condition; this signal monitors over-current on the
USB bus (external circuitry required to detect over-current
condition).

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257 of 1444

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NXP Semiconductors

Chapter 16: LPC43xx/LPC43Sxx Pin configuration

[3]

N;
PU

Type

D10 91

Description

[1]

J12

Reset state

K14

LQFP144

TFBGA100

P2_5

TFBGA180

Symbol

LBGA256

Table 184. LPC4350/30/20/10 and LPC43S50/S30/S20 pin descriptions …continued
LCD, Ethernet, USB0, and USB1 functions are not available on all parts.

I/O

SGPIO14 — General purpose digital input/output pin.

I

CTIN_2 — SCT input 2. Capture input 2 of timer 0.

I

USB1_VBUS — Monitors the presence of USB1 bus power.
Note: This signal must be HIGH for USB reset to occur.

P2_6

P2_7

UM10503

User manual

K16

H14

J14

G9

95

G12 C10 96

[2]

[2]

N;
PU

N;
PU

I

ADCTRIG1 — ADC trigger input 1.

I/O

GPIO5[5] — General purpose digital input/output pin.

-

R — Function reserved.

O

T3_MAT2 — Match output 2 of timer 3.

O

USB0_IND0 — USB0 port indicator LED control output 0.

I/O

SGPIO7 — General purpose digital input/output pin.

I/O

U0_DIR — RS-485/EIA-485 output enable/direction control for
USART0.

I/O

EMC_A10 — External memory address line 10.

O

USB0_IND0 — USB0 port indicator LED control
output 0.

I/O

GPIO5[6] — General purpose digital input/output pin.

I

CTIN_7 — SCT input 7.

I

T3_CAP3 — Capture input 3 of timer 3.

-

R — Function reserved.

I/O

GPIO0[7] — General purpose digital input/output pin. If this pin
is pulled LOW at reset, the part enters ISP mode using
USART0.

O

CTOUT_1 — SCT output 1. Match output 3 of timer 3.

I/O

U3_UCLK — Serial clock input/output for USART3 in
synchronous mode.

I/O

EMC_A9 — External memory address line 9.

-

R — Function reserved.

-

R — Function reserved.

O

T3_MAT3 — Match output 3 of timer 3.

-

R — Function reserved.

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258 of 1444

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NXP Semiconductors

Chapter 16: LPC43xx/LPC43Sxx Pin configuration

P2_9

P2_10

P2_11

UM10503

User manual

C6

98

H16

G16

F16

G14 B10 102

F14

E13

E8

A9

104

105

[2]

[2]

[2]

[2]

N;
PU

N;
PU

N;
PU

N;
PU

Type

H14

Description

[1]

LQFP144

J16

Reset state

TFBGA100

P2_8

TFBGA180

Symbol

LBGA256

Table 184. LPC4350/30/20/10 and LPC43S50/S30/S20 pin descriptions …continued
LCD, Ethernet, USB0, and USB1 functions are not available on all parts.

I/O

SGPIO15 — General purpose digital input/output pin. Boot pin
(see Table 22).

O

CTOUT_0 — SCT output 0. Match output 0 of timer 0.

I/O

U3_DIR — RS-485/EIA-485 output enable/direction control for
USART3.

I/O

EMC_A8 — External memory address line 8.

I/O

GPIO5[7] — General purpose digital input/output pin.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

I/O

GPIO1[10] — General purpose digital input/output pin. Boot
pin (see Table 22).

O

CTOUT_3 — SCT output 3. Match output 3 of timer 0.

I/O

U3_BAUD — Baud pin for USART3.

I/O

EMC_A0 — External memory address line 0.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

I/O

GPIO0[14] — General purpose digital input/output pin.

O

CTOUT_2 — SCT output 2. Match output 2 of timer 0.

O

U2_TXD — Transmitter output for USART2.

I/O

EMC_A1 — External memory address line 1.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

I/O

GPIO1[11] — General purpose digital input/output pin.

O

CTOUT_5 — SCT output 5. Match output 3 of timer 3.

I

U2_RXD — Receiver input for USART2.

I/O

EMC_A2 — External memory address line 2.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

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Rev. 2.4 — 22 August 2018

© NXP B.V. 2018. All rights reserved.

259 of 1444

UM10503

NXP Semiconductors

Chapter 16: LPC43xx/LPC43Sxx Pin configuration

P2_13

P3_0

UM10503

User manual

B9

106

C16

F13

E14

D12

A10 108

A8

112

[2]

[2]

[2]

N;
PU

N;
PU

N;
PU

Type

D13

Description

[1]

LQFP144

E15

Reset state

TFBGA100

P2_12

TFBGA180

Symbol

LBGA256

Table 184. LPC4350/30/20/10 and LPC43S50/S30/S20 pin descriptions …continued
LCD, Ethernet, USB0, and USB1 functions are not available on all parts.

I/O

GPIO1[12] — General purpose digital input/output pin.

O

CTOUT_4 — SCT output 4. Match output 3 of timer 3.

-

R — Function reserved.

I/O

EMC_A3 — External memory address line 3.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

I/O

U2_UCLK — Serial clock input/output for USART2 in
synchronous mode.

I/O

GPIO1[13] — General purpose digital input/output pin.

I

CTIN_4 — SCT input 4. Capture input 2 of timer 1.

-

R — Function reserved.

I/O

EMC_A4 — External memory address line 4.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

I/O

U2_DIR — RS-485/EIA-485 output enable/direction control for
USART2.

I/O

I2S0_RX_SCK — I2S receive clock. It is driven by the master
and received by the slave. Corresponds to the signal SCK in
the I2S-bus specification.

O

I2S0_RX_MCLK — I2S receive master clock.

I/O

I2S0_TX_SCK — Transmit Clock. It is driven by the master
and received by the slave. Corresponds to the signal SCK in
the I2S-bus specification.

O

I2S0_TX_MCLK — I2S transmit master clock.

I/O

SSP0_SCK — Serial clock for SSP0.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

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Rev. 2.4 — 22 August 2018

© NXP B.V. 2018. All rights reserved.

260 of 1444

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NXP Semiconductors

Chapter 16: LPC43xx/LPC43Sxx Pin configuration

P3_2

P3_3

UM10503

User manual

F7

114

F11

B14

D9

B13

G6

A7

116

118

[2]

[2]

[4]

N;
PU

OL;
PU

N;
PU

Type

D10

Description

[1]

LQFP144

G11

Reset state

TFBGA100

P3_1

TFBGA180

Symbol

LBGA256

Table 184. LPC4350/30/20/10 and LPC43S50/S30/S20 pin descriptions …continued
LCD, Ethernet, USB0, and USB1 functions are not available on all parts.

I/O

I2S0_TX_WS — Transmit Word Select. It is driven by the
master and received by the slave. Corresponds to the signal
WS in the I2S-bus specification.

I/O

I2S0_RX_WS — Receive Word Select. It is driven by the
master and received by the slave. Corresponds to the signal
WS in the I2S-bus specification.

I

CAN0_RD — CAN receiver input.

O

USB1_IND1 — USB1 Port indicator LED control output 1.

I/O

GPIO5[8] — General purpose digital input/output pin.

-

R — Function reserved.

O

LCD_VD15 — LCD data.

-

R — Function reserved.

I/O

I2S0_TX_SDA — I2S transmit data. It is driven by the
transmitter and read by the receiver. Corresponds to the signal
SD in the I2S-bus specification.

I/O

I2S0_RX_SDA — I2S Receive data. It is driven by the
transmitter and read by the receiver. Corresponds to the signal
SD in the I2S-bus specification.

O

CAN0_TD — CAN transmitter output.

O

USB1_IND0 — USB1 Port indicator LED control output 0.

I/O

GPIO5[9] — General purpose digital input/output pin.

-

R — Function reserved.

O

LCD_VD14 — LCD data.

-

R — Function reserved.

-

R — Function reserved.

I/O

SPI_SCK — Serial clock for SPI.

I/O

SSP0_SCK — Serial clock for SSP0.

O

SPIFI_SCK — Serial clock for SPIFI.

O

CGU_OUT1 — CGU spare clock output 1.

-

R — Function reserved.

O

I2S0_TX_MCLK — I2S transmit master clock.

I/O

I2S1_TX_SCK — Transmit Clock. It is driven by the master
and received by the slave. Corresponds to the signal SCK in
the I2S-bus specification.

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Chapter 16: LPC43xx/LPC43Sxx Pin configuration

P3_5

P3_6

P3_7

UM10503

User manual

B8

119

C12

B13

C11

C11

B12

C10

B7

C7

D7

121

122

123

[2]

[2]

[2]

[2]

N;
PU

N;
PU

N;
PU

N;
PU

Type

C14

Description

[1]

LQFP144

A15

Reset state

TFBGA100

P3_4

TFBGA180

Symbol

LBGA256

Table 184. LPC4350/30/20/10 and LPC43S50/S30/S20 pin descriptions …continued
LCD, Ethernet, USB0, and USB1 functions are not available on all parts.

I/O

GPIO1[14] — General purpose digital input/output pin.

-

R — Function reserved.

-

R — Function reserved.

I/O

SPIFI_SIO3 — I/O lane 3 for SPIFI.

O

U1_TXD — Transmitter output for UART 1.

I/O

I2S0_TX_WS — Transmit Word Select. It is driven by the
master and received by the slave. Corresponds to the signal
WS in the I2S-bus specification.

I/O

I2S1_RX_SDA — I2S1 Receive data. It is driven by the
transmitter and read by the receiver. Corresponds to the signal
SD in the I2S-bus specification.

O

LCD_VD13 — LCD data.

I/O

GPIO1[15] — General purpose digital input/output pin.

-

R — Function reserved.

-

R — Function reserved.

I/O

SPIFI_SIO2 — I/O lane 2 for SPIFI.

I

U1_RXD — Receiver input for UART 1.

I/O

I2S0_TX_SDA — I2S transmit data. It is driven by the
transmitter and read by the receiver. Corresponds to the signal
SD in the I2S-bus specification.

I/O

I2S1_RX_WS — Receive Word Select. It is driven by the
master and received by the slave. Corresponds to the signal
WS in the I2S-bus specification.

O

LCD_VD12 — LCD data.

I/O

GPIO0[6] — General purpose digital input/output pin.

I/O

SPI_MISO — Master In Slave Out for SPI.

I/O

SSP0_SSEL — Slave Select for SSP0.

I/O

SPIFI_MISO — Input 1 in SPIFI quad mode; SPIFI output IO1.

-

R — Function reserved.

I/O

SSP0_MISO — Master In Slave Out for SSP0.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

I/O

SPI_MOSI — Master Out Slave In for SPI.

I/O

SSP0_MISO — Master In Slave Out for SSP0.

I/O

SPIFI_MOSI — Input I0 in SPIFI quad mode; SPIFI output IO0.

I/O

GPIO5[10] — General purpose digital input/output pin.

I/O

SSP0_MOSI — Master Out Slave in for SSP0.

-

R — Function reserved.

-

R — Function reserved.

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262 of 1444

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Chapter 16: LPC43xx/LPC43Sxx Pin configuration

P4_0

P4_1

P4_2

UM10503

User manual

E7

124

D5

A1

D3

D4

D3

A2

-

-

-

1

3

8

[2]

[2]

[5]

[2]

N;
PU

N;
PU

N;
PU

N;
PU

Type

C9

Description

[1]

LQFP144

C10

Reset state

TFBGA100

P3_8

TFBGA180

Symbol

LBGA256

Table 184. LPC4350/30/20/10 and LPC43S50/S30/S20 pin descriptions …continued
LCD, Ethernet, USB0, and USB1 functions are not available on all parts.

-

R — Function reserved.

I

SPI_SSEL — Slave Select for SPI. Note that this pin in an
input pin only. The SPI in master mode cannot drive the CS
input on the slave. Any GPIO pin can be used for SPI chip
select in master mode.

I/O

SSP0_MOSI — Master Out Slave in for SSP0.

I/O

SPIFI_CS — SPIFI serial flash chip select.

I/O

GPIO5[11] — General purpose digital input/output pin.

I/O

SSP0_SSEL — Slave Select for SSP0.

-

R — Function reserved.

-

R — Function reserved.

I/O

GPIO2[0] — General purpose digital input/output pin.

O

MCOA0 — Motor control PWM channel 0, output A.

I

NMI — External interrupt input to NMI.

-

R — Function reserved.

-

R — Function reserved.

O

LCD_VD13 — LCD data.

I/O

U3_UCLK — Serial clock input/output for USART3 in
synchronous mode.

-

R — Function reserved.

I/O

GPIO2[1] — General purpose digital input/output pin.

O

CTOUT_1 — SCT output 1. Match output 3 of timer 3.

O

LCD_VD0 — LCD data.

-

R — Function reserved.

-

R — Function reserved.

O

LCD_VD19 — LCD data.

O

U3_TXD — Transmitter output for USART3.

I

ENET_COL — Ethernet Collision detect (MII interface).

AI

ADC0_1 — ADC0 and ADC1, input channel 1. Configure the
pin as GPIO input and use the ADC function select register in
the SCU to select the ADC.

I/O

GPIO2[2] — General purpose digital input/output pin.

O

CTOUT_0 — SCT output 0. Match output 0 of timer 0.

O

LCD_VD3 — LCD data.

-

R — Function reserved.

-

R — Function reserved.

O

LCD_VD12 — LCD data.

I

U3_RXD — Receiver input for USART3.

I/O

SGPIO8 — General purpose digital input/output pin.

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Rev. 2.4 — 22 August 2018

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263 of 1444

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Chapter 16: LPC43xx/LPC43Sxx Pin configuration

P4_4

P4_5

UM10503

User manual

-

7

B1

D2

A1

C2

-

-

9

10

[5]

[5]

[2]

N;
PU

N;
PU

N;
PU

Type

B2

Description

[1]

LQFP144

C2

Reset state

TFBGA100

P4_3

TFBGA180

Symbol

LBGA256

Table 184. LPC4350/30/20/10 and LPC43S50/S30/S20 pin descriptions …continued
LCD, Ethernet, USB0, and USB1 functions are not available on all parts.

I/O

GPIO2[3] — General purpose digital input/output pin.

O

CTOUT_3 — SCT output 3. Match output 3 of timer 0.

O

LCD_VD2 — LCD data.

-

R — Function reserved.

-

R — Function reserved.

O

LCD_VD21 — LCD data.

I/O

U3_BAUD — Baud pin for USART3.

I/O

SGPIO9 — General purpose digital input/output pin.

AI

ADC0_0 — DAC, ADC0 and ADC1, input channel 0. Configure
the pin as GPIO input and use the ADC function select register
in the SCU to select the ADC.

I/O

GPIO2[4] — General purpose digital input/output pin.

O

CTOUT_2 — SCT output 2. Match output 2 of timer 0.

O

LCD_VD1 — LCD data.

-

R — Function reserved.

-

R — Function reserved.

O

LCD_VD20 — LCD data.

I/O

U3_DIR — RS-485/EIA-485 output enable/direction control for
USART3.

I/O

SGPIO10 — General purpose digital input/output pin.

O

DAC — DAC output. Configure the pin as GPIO input and use
the analog function select register in the SCU to select the
DAC.

I/O

GPIO2[5] — General purpose digital input/output pin.

O

CTOUT_5 — SCT output 5. Match output 3 of timer 3.

O

LCD_FP — Frame pulse (STN). Vertical synchronization pulse
(TFT).

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

I/O

SGPIO11 — General purpose digital input/output pin.

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Rev. 2.4 — 22 August 2018

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264 of 1444

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NXP Semiconductors

Chapter 16: LPC43xx/LPC43Sxx Pin configuration

P4_7

P4_8

P4_9

UM10503

User manual

-

11

H4

E2

L2

F4

D2

J2

-

-

-

14

15

33

[2]

[2]

[2]

[2]

N;
PU

O;
PU

N;
PU

N;
PU

Type

B1

Description

[1]

LQFP144

C1

Reset state

TFBGA100

P4_6

TFBGA180

Symbol

LBGA256

Table 184. LPC4350/30/20/10 and LPC43S50/S30/S20 pin descriptions …continued
LCD, Ethernet, USB0, and USB1 functions are not available on all parts.

I/O

GPIO2[6] — General purpose digital input/output pin.

O

CTOUT_4 — SCT output 4. Match output 3 of timer 3.

O

LCD_ENAB/LCDM — STN AC bias drive or TFT data enable
input.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

I/O

SGPIO12 — General purpose digital input/output pin.

O

LCD_DCLK — LCD panel clock.

I

GP_CLKIN — General purpose clock input to the CGU.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

I/O

I2S1_TX_SCK — Transmit Clock. It is driven by the master
and received by the slave. Corresponds to the signal SCK in
the I2S-bus specification.

I/O

I2S0_TX_SCK — Transmit Clock. It is driven by the master
and received by the slave. Corresponds to the signal SCK in
the I2S-bus specification.

-

R — Function reserved.

I

CTIN_5 — SCT input 5. Capture input 2 of timer 2.

O

LCD_VD9 — LCD data.

-

R — Function reserved.

I/O

GPIO5[12] — General purpose digital input/output pin.

O

LCD_VD22 — LCD data.

O

CAN1_TD — CAN1 transmitter output.

I/O

SGPIO13 — General purpose digital input/output pin.

-

R — Function reserved.

I

CTIN_6 — SCT input 6. Capture input 1 of timer 3.

O

LCD_VD11 — LCD data.

-

R — Function reserved.

I/O

GPIO5[13] — General purpose digital input/output pin.

O

LCD_VD15 — LCD data.

I

CAN1_RD — CAN1 receiver input.

I/O

SGPIO14 — General purpose digital input/output pin.

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Rev. 2.4 — 22 August 2018

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265 of 1444

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NXP Semiconductors

Chapter 16: LPC43xx/LPC43Sxx Pin configuration

P5_0

P5_1

P5_2

UM10503

User manual

-

35

N3

P3

R4

L2

M1

M3

-

-

-

37

39

46

[2]

[2]

[2]

[2]

N;
PU

N;
PU

N;
PU

N;
PU

Type

L3

Description

[1]

LQFP144

M3

Reset state

TFBGA100

P4_10

TFBGA180

Symbol

LBGA256

Table 184. LPC4350/30/20/10 and LPC43S50/S30/S20 pin descriptions …continued
LCD, Ethernet, USB0, and USB1 functions are not available on all parts.

-

R — Function reserved.

I

CTIN_2 — SCT input 2. Capture input 2 of timer 0.

O

LCD_VD10 — LCD data.

-

R — Function reserved.

I/O

GPIO5[14] — General purpose digital input/output pin.

O

LCD_VD14 — LCD data.

-

R — Function reserved.

I/O

SGPIO15 — General purpose digital input/output pin.

I/O

GPIO2[9] — General purpose digital input/output pin.

O

MCOB2 — Motor control PWM channel 2, output B.

I/O

EMC_D12 — External memory data line 12.

-

R — Function reserved.

I

U1_DSR — Data Set Ready input for UART 1.

I

T1_CAP0 — Capture input 0 of timer 1.

-

R — Function reserved.

-

R — Function reserved.

I/O

GPIO2[10] — General purpose digital input/output pin.

I

MCI2 — Motor control PWM channel 2, input.

I/O

EMC_D13 — External memory data line 13.

-

R — Function reserved.

O

U1_DTR — Data Terminal Ready output for UART 1. Can also
be configured to be an RS-485/EIA-485 output enable signal
for UART 1.

I

T1_CAP1 — Capture input 1 of timer 1.

-

R — Function reserved.

-

R — Function reserved.

I/O

GPIO2[11] — General purpose digital input/output pin.

I

MCI1 — Motor control PWM channel 1, input.

I/O

EMC_D14 — External memory data line 14.

-

R — Function reserved.

O

U1_RTS — Request to Send output for UART 1. Can also be
configured to be an RS-485/EIA-485 output enable signal for
UART 1.

I

T1_CAP2 — Capture input 2 of timer 1.

-

R — Function reserved.

-

R — Function reserved.

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Rev. 2.4 — 22 August 2018

© NXP B.V. 2018. All rights reserved.

266 of 1444

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NXP Semiconductors

Chapter 16: LPC43xx/LPC43Sxx Pin configuration

P5_4

P5_5

P5_6

UM10503

User manual

-

54

P9

P10

T13

N7

N8

M11

-

-

-

57

58

63

[2]

[2]

[2]

[2]

N;
PU

N;
PU

N;
PU

N;
PU

Type

P6

Description

[1]

LQFP144

T8

Reset state

TFBGA100

P5_3

TFBGA180

Symbol

LBGA256

Table 184. LPC4350/30/20/10 and LPC43S50/S30/S20 pin descriptions …continued
LCD, Ethernet, USB0, and USB1 functions are not available on all parts.

I/O

GPIO2[12] — General purpose digital input/output pin.

I

MCI0 — Motor control PWM channel 0, input.

I/O

EMC_D15 — External memory data line 15.

-

R — Function reserved.

I

U1_RI — Ring Indicator input for UART 1.

I

T1_CAP3 — Capture input 3 of timer 1.

-

R — Function reserved.

-

R — Function reserved.

I/O

GPIO2[13] — General purpose digital input/output pin.

O

MCOB0 — Motor control PWM channel 0, output B.

I/O

EMC_D8 — External memory data line 8.

-

R — Function reserved.

I

U1_CTS — Clear to Send input for UART 1.

O

T1_MAT0 — Match output 0 of timer 1.

-

R — Function reserved.

-

R — Function reserved.

I/O

GPIO2[14] — General purpose digital input/output pin.

O

MCOA1 — Motor control PWM channel 1, output A.

I/O

EMC_D9 — External memory data line 9.

-

R — Function reserved.

I

U1_DCD — Data Carrier Detect input for UART 1.

O

T1_MAT1 — Match output 1 of timer 1.

-

R — Function reserved.

-

R — Function reserved.

I/O

GPIO2[15] — General purpose digital input/output pin.

O

MCOB1 — Motor control PWM channel 1, output B.

I/O

EMC_D10 — External memory data line 10.

-

R — Function reserved.

O

U1_TXD — Transmitter output for UART 1.

O

T1_MAT2 — Match output 2 of timer 1.

-

R — Function reserved.

-

R — Function reserved.

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Rev. 2.4 — 22 August 2018

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267 of 1444

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NXP Semiconductors

Chapter 16: LPC43xx/LPC43Sxx Pin configuration

P6_0

P6_1

P6_2

UM10503

User manual

-

65

M12

R15

L13

M10 H7

P14

K11

G5

J9

73

74

78

[2]

[2]

[2]

[2]

N;
PU

N;
PU

N;
PU

N;
PU

Type

N11

Description

[1]

LQFP144

R12

Reset state

TFBGA100

P5_7

TFBGA180

Symbol

LBGA256

Table 184. LPC4350/30/20/10 and LPC43S50/S30/S20 pin descriptions …continued
LCD, Ethernet, USB0, and USB1 functions are not available on all parts.

I/O

GPIO2[7] — General purpose digital input/output pin.

O

MCOA2 — Motor control PWM channel 2, output A.

I/O

EMC_D11 — External memory data line 11.

-

R — Function reserved.

I

U1_RXD — Receiver input for UART 1.

O

T1_MAT3 — Match output 3 of timer 1.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

O

I2S0_RX_MCLK — I2S receive master clock.

-

R — Function reserved.

-

R — Function reserved.

I/O

I2S0_RX_SCK — Receive Clock. It is driven by the master and
received by the slave. Corresponds to the signal SCK in the
I2S-bus specification.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

I/O

GPIO3[0] — General purpose digital input/output pin.

O

EMC_DYCS1 — SDRAM chip select 1.

I/O

U0_UCLK — Serial clock input/output for USART0 in
synchronous mode.

I/O

I2S0_RX_WS — Receive Word Select. It is driven by the
master and received by the slave. Corresponds to the signal
WS in the I2S-bus specification.

-

R — Function reserved.

I

T2_CAP0 — Capture input 0 of timer 2.

-

R — Function reserved.

-

R — Function reserved.

I/O

GPIO3[1] — General purpose digital input/output pin.

O

EMC_CKEOUT1 — SDRAM clock enable 1.

I/O

U0_DIR — RS-485/EIA-485 output enable/direction control for
USART0.

I/O

I2S0_RX_SDA — I2S Receive data. It is driven by the
transmitter and read by the receiver. Corresponds to the signal
SD in the I2S-bus specification.

-

R — Function reserved.

I

T2_CAP1 — Capture input 1 of timer 2.

-

R — Function reserved.

-

R — Function reserved.

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Rev. 2.4 — 22 August 2018

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268 of 1444

UM10503

NXP Semiconductors

Chapter 16: LPC43xx/LPC43Sxx Pin configuration

-

79

[2]

N;
PU

Type

N13

Description

[1]

LQFP144

P15

Reset state

TFBGA100

P6_3

TFBGA180

Symbol

LBGA256

Table 184. LPC4350/30/20/10 and LPC43S50/S30/S20 pin descriptions …continued
LCD, Ethernet, USB0, and USB1 functions are not available on all parts.

I/O

GPIO3[2] — General purpose digital input/output pin.

O

USB0_PPWR — VBUS drive signal (towards external charge
pump or power management unit); indicates that the VBUS
signal must be driven (active HIGH).
Add a pull-down resistor to disable the power switch at reset.
This signal has opposite polarity compared to the USB_PPWR
used on other NXP LPC parts.

P6_4

P6_5

UM10503

User manual

R16

P16

M14 F6

L14

F9

80

82

[2]

[2]

N;
PU

N;
PU

I/O

SGPIO4 — General purpose digital input/output pin.

O

EMC_CS1 — LOW active Chip Select 1 signal.

-

R — Function reserved.

I

T2_CAP2 — Capture input 2 of timer 2.

-

R — Function reserved.

-

R — Function reserved.

I/O

GPIO3[3] — General purpose digital input/output pin.

I

CTIN_6 — SCT input 6. Capture input 1 of timer 3.

O

U0_TXD — Transmitter output for USART0.

O

EMC_CAS — LOW active SDRAM Column Address Strobe.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

I/O

GPIO3[4] — General purpose digital input/output pin.

O

CTOUT_6 — SCT output 6. Match output 2 of timer 1.

I

U0_RXD — Receiver input for USART0.

O

EMC_RAS — LOW active SDRAM Row Address Strobe.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

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Rev. 2.4 — 22 August 2018

© NXP B.V. 2018. All rights reserved.

269 of 1444

UM10503

NXP Semiconductors

Chapter 16: LPC43xx/LPC43Sxx Pin configuration

P6_7

P6_8

P6_9

UM10503

User manual

-

83

J13

H13

J15

H11

F12

H13

-

-

F8

85

86

97

[2]

[2]

[2]

[2]

N;
PU

N;
PU

N;
PU

N;
PU

Type

K12

Description

[1]

LQFP144

L14

Reset state

TFBGA100

P6_6

TFBGA180

Symbol

LBGA256

Table 184. LPC4350/30/20/10 and LPC43S50/S30/S20 pin descriptions …continued
LCD, Ethernet, USB0, and USB1 functions are not available on all parts.

I/O

GPIO0[5] — General purpose digital input/output pin.

O

EMC_BLS1 — LOW active Byte Lane select signal 1.

I/O

SGPIO5 — General purpose digital input/output pin.

I

USB0_PWR_FAULT — Port power fault signal indicating
overcurrent condition; this signal monitors over-current on the
USB bus (external circuitry required to detect over-current
condition).

-

R — Function reserved.

I

T2_CAP3 — Capture input 3 of timer 2.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

I/O

EMC_A15 — External memory address line 15.

I/O

SGPIO6 — General purpose digital input/output pin.

O

USB0_IND1 — USB0 port indicator LED control output 1.

I/O

GPIO5[15] — General purpose digital input/output pin.

O

T2_MAT0 — Match output 0 of timer 2.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

I/O

EMC_A14 — External memory address line 14.

I/O

SGPIO7 — General purpose digital input/output pin.

O

USB0_IND0 — USB0 port indicator LED control output 0.

I/O

GPIO5[16] — General purpose digital input/output pin.

O

T2_MAT1 — Match output 1 of timer 2.

-

R — Function reserved.

-

R — Function reserved.

I/O

GPIO3[5] — General purpose digital input/output pin.

-

R — Function reserved.

-

R — Function reserved.

O

EMC_DYCS0 — SDRAM chip select 0.

-

R — Function reserved.

O

T2_MAT2 — Match output 2 of timer 2.

-

R — Function reserved.

-

R — Function reserved.

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Chapter 16: LPC43xx/LPC43Sxx Pin configuration

P6_10

P6_11

P6_12

P7_0

UM10503

User manual

G15

B16

F11

F13

B14

C9

-

-

100

101

103

110

[2]

[2]

[2]

[2]

N;
PU

N;
PU

N;
PU

N;
PU

Type

Description

[1]

Reset state

G13 -

LQFP144

H15

H12

TFBGA100

TFBGA180

Symbol

LBGA256

Table 184. LPC4350/30/20/10 and LPC43S50/S30/S20 pin descriptions …continued
LCD, Ethernet, USB0, and USB1 functions are not available on all parts.

I/O

GPIO3[6] — General purpose digital input/output pin.

O

MCABORT — Motor control PWM, LOW-active fast abort.

-

R — Function reserved.

O

EMC_DQMOUT1 — Data mask 1 used with SDRAM and static
devices.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

I/O

GPIO3[7] — General purpose digital input/output pin.

-

R — Function reserved.

-

R — Function reserved.

O

EMC_CKEOUT0 — SDRAM clock enable 0.

-

R — Function reserved.

O

T2_MAT3 — Match output 3 of timer 2.

-

R — Function reserved.

-

R — Function reserved.

I/O

GPIO2[8] — General purpose digital input/output pin.

O

CTOUT_7 — SCT output 7. Match output 3 of timer 1.

-

R — Function reserved.

O

EMC_DQMOUT0 — Data mask 0 used with SDRAM and static
devices.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

I/O

GPIO3[8] — General purpose digital input/output pin.

O

CTOUT_14 — SCT output 14. Match output 2 of timer 3.

-

R — Function reserved.

O

LCD_LE — Line end signal.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

I/O

SGPIO4 — General purpose digital input/output pin.

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Chapter 16: LPC43xx/LPC43Sxx Pin configuration

P7_2

P7_3

P7_4

UM10503

User manual

-

113

A16

C13

C8

A14

C12

C6

-

-

-

115

117

132

[2]

[2]

[2]

[5]

N;
PU

N;
PU

N;
PU

N;
PU

Type

C13

Description

[1]

LQFP144

C14

Reset state

TFBGA100

P7_1

TFBGA180

Symbol

LBGA256

Table 184. LPC4350/30/20/10 and LPC43S50/S30/S20 pin descriptions …continued
LCD, Ethernet, USB0, and USB1 functions are not available on all parts.

I/O

GPIO3[9] — General purpose digital input/output pin.

O

CTOUT_15 — SCT output 15. Match output 3 of timer 3.

I/O

I2S0_TX_WS — Transmit Word Select. It is driven by the
master and received by the slave. Corresponds to the signal
WS in the I2S-bus specification.

O

LCD_VD19 — LCD data.

O

LCD_VD7 — LCD data.

-

R — Function reserved.

O

U2_TXD — Transmitter output for USART2.

I/O

SGPIO5 — General purpose digital input/output pin.

I/O

GPIO3[10] — General purpose digital input/output pin.

I

CTIN_4 — SCT input 4. Capture input 2 of timer 1.

I/O

I2S0_TX_SDA — I2S transmit data. It is driven by the
transmitter and read by the receiver. Corresponds to the signal
SD in the I2S-bus specification.

O

LCD_VD18 — LCD data.

O

LCD_VD6 — LCD data.

-

R — Function reserved.

I

U2_RXD — Receiver input for USART2.

I/O

SGPIO6 — General purpose digital input/output pin.

I/O

GPIO3[11] — General purpose digital input/output pin.

I

CTIN_3 — SCT input 3. Capture input 1 of timer 1.

-

R — Function reserved.

O

LCD_VD17 — LCD data.

O

LCD_VD5 — LCD data.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

I/O

GPIO3[12] — General purpose digital input/output pin.

O

CTOUT_13 — SCT output 13. Match output 3 of timer 3.

-

R — Function reserved.

O

LCD_VD16 — LCD data.

O

LCD_VD4 — LCD data.

O

TRACEDATA[0] — Trace data, bit 0.

-

R — Function reserved.

-

R — Function reserved.

AI

ADC0_4 — ADC0 and ADC1, input channel 4. Configure the
pin as GPIO input and use the ADC function select register in
the SCU to select the ADC.

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Chapter 16: LPC43xx/LPC43Sxx Pin configuration

P7_6

P7_7

UM10503

User manual

-

133

C7

B6

F5

D5

-

-

134

140

[5]

[2]

[5]

N;
PU

N;
PU

N;
PU

Type

A7

Description

[1]

LQFP144

A7

Reset state

TFBGA100

P7_5

TFBGA180

Symbol

LBGA256

Table 184. LPC4350/30/20/10 and LPC43S50/S30/S20 pin descriptions …continued
LCD, Ethernet, USB0, and USB1 functions are not available on all parts.

I/O

GPIO3[13] — General purpose digital input/output pin.

O

CTOUT_12 — SCT output 12. Match output 3 of timer 3.

-

R — Function reserved.

O

LCD_VD8 — LCD data.

O

LCD_VD23 — LCD data.

O

TRACEDATA[1] — Trace data, bit 1.

-

R — Function reserved.

-

R — Function reserved.

AI

ADC0_3 — ADC0 and ADC1, input channel 3. Configure the
pin as GPIO input and use the ADC function select register in
the SCU to select the ADC.

I/O

GPIO3[14] — General purpose digital input/output pin.

O

CTOUT_11 — SCT output 1. Match output 3 of timer 2.

-

R — Function reserved.

O

LCD_LP — Line synchronization pulse (STN). Horizontal
synchronization pulse (TFT).

-

R — Function reserved.

O

TRACEDATA[2] — Trace data, bit 2.

-

R — Function reserved.

-

R — Function reserved.

I/O

GPIO3[15] — General purpose digital input/output pin.

O

CTOUT_8 — SCT output 8. Match output 0 of timer 2.

-

R — Function reserved.

O

LCD_PWR — LCD panel power enable.

-

R — Function reserved.

O

TRACEDATA[3] — Trace data, bit 3.

O

ENET_MDC — Ethernet MIIM clock.

I/O

SGPIO7 — General purpose digital input/output pin.

AI

ADC1_6 — ADC1 and ADC0, input channel 6. Configure the
pin as GPIO input and use the ADC function select register in
the SCU to select the ADC.

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NXP Semiconductors

Chapter 16: LPC43xx/LPC43Sxx Pin configuration

P8_1

P8_2

P8_3

UM10503

User manual

-

-

H5

K4

J3

G4

J4

H3

-

-

-

-

-

-

[3]

[3]

[3]

[2]

N;
PU

N;
PU

N;
PU

N;
PU

Type

E4

Description

[1]

LQFP144

E5

Reset state

TFBGA100

P8_0

TFBGA180

Symbol

LBGA256

Table 184. LPC4350/30/20/10 and LPC43S50/S30/S20 pin descriptions …continued
LCD, Ethernet, USB0, and USB1 functions are not available on all parts.

I/O

GPIO4[0] — General purpose digital input/output pin.

I

USB0_PWR_FAULT — Port power fault signal indicating
overcurrent condition; this signal monitors over-current on the
USB bus (external circuitry required to detect over-current
condition).

-

R — Function reserved.

I

MCI2 — Motor control PWM channel 2, input.

I/O

SGPIO8 — General purpose digital input/output pin.

-

R — Function reserved.

-

R — Function reserved.

O

T0_MAT0 — Match output 0 of timer 0.

I/O

GPIO4[1] — General purpose digital input/output pin.

O

USB0_IND1 — USB0 port indicator LED control output 1.

-

R — Function reserved.

I

MCI1 — Motor control PWM channel 1, input.

I/O

SGPIO9 — General purpose digital input/output pin.

-

R — Function reserved.

-

R — Function reserved.

O

T0_MAT1 — Match output 1 of timer 0.

I/O

GPIO4[2] — General purpose digital input/output pin.

O

USB0_IND0 — USB0 port indicator LED control output 0.

-

R — Function reserved.

I

MCI0 — Motor control PWM channel 0, input.

I/O

SGPIO10 — General purpose digital input/output pin.

-

R — Function reserved.

-

R — Function reserved.

O

T0_MAT2 — Match output 2 of timer 0.

I/O

GPIO4[3] — General purpose digital input/output pin.

I/O

USB1_ULPI_D2 — ULPI link bidirectional data line 2.

-

R — Function reserved.

O

LCD_VD12 — LCD data.

O

LCD_VD19 — LCD data.

-

R — Function reserved.

-

R — Function reserved.

O

T0_MAT3 — Match output 3 of timer 0.

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Rev. 2.4 — 22 August 2018

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274 of 1444

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NXP Semiconductors

Chapter 16: LPC43xx/LPC43Sxx Pin configuration

P8_5

P8_6

P8_7

UM10503

User manual

-

-

J1

K3

K1

H1

J3

J1

-

-

-

-

-

-

[2]

[2]

[2]

[2]

N;
PU

N;
PU

N;
PU

N;
PU

Type

H2

Description

[1]

LQFP144

J2

Reset state

TFBGA100

P8_4

TFBGA180

Symbol

LBGA256

Table 184. LPC4350/30/20/10 and LPC43S50/S30/S20 pin descriptions …continued
LCD, Ethernet, USB0, and USB1 functions are not available on all parts.

I/O

GPIO4[4] — General purpose digital input/output pin.

I/O

USB1_ULPI_D1 — ULPI link bidirectional data line 1.

-

R — Function reserved.

O

LCD_VD7 — LCD data.

O

LCD_VD16 — LCD data.

-

R — Function reserved.

-

R — Function reserved.

I

T0_CAP0 — Capture input 0 of timer 0.

I/O

GPIO4[5] — General purpose digital input/output pin.

I/O

USB1_ULPI_D0 — ULPI link bidirectional data line 0.

-

R — Function reserved.

O

LCD_VD6 — LCD data.

O

LCD_VD8 — LCD data.

-

R — Function reserved.

-

R — Function reserved.

I

T0_CAP1 — Capture input 1 of timer 0.

I/O

GPIO4[6] — General purpose digital input/output pin.

I

USB1_ULPI_NXT — ULPI link NXT signal. Data flow control
signal from the PHY.

-

R — Function reserved.

O

LCD_VD5 — LCD data.

O

LCD_LP — Line synchronization pulse (STN). Horizontal
synchronization pulse (TFT).

-

R — Function reserved.

-

R — Function reserved.

I

T0_CAP2 — Capture input 2 of timer 0.

I/O

GPIO4[7] — General purpose digital input/output pin.

O

USB1_ULPI_STP — ULPI link STP signal. Asserted to end or
interrupt transfers to the PHY.

-

R — Function reserved.

O

LCD_VD4 — LCD data.

O

LCD_PWR — LCD panel power enable.

-

R — Function reserved.

-

R — Function reserved.

I

T0_CAP3 — Capture input 3 of timer 0.

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275 of 1444

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NXP Semiconductors

Chapter 16: LPC43xx/LPC43Sxx Pin configuration

P9_0

P9_1

P9_2

UM10503

User manual

-

-

T1

N6

N8

P1

P4

M6

-

-

-

-

-

-

[2]

[2]

[2]

[2]

N;
PU

N;
PU

N;
PU

N;
PU

Type

K1

Description

[1]

LQFP144

L1

Reset state

TFBGA100

P8_8

TFBGA180

Symbol

LBGA256

Table 184. LPC4350/30/20/10 and LPC43S50/S30/S20 pin descriptions …continued
LCD, Ethernet, USB0, and USB1 functions are not available on all parts.

-

R — Function reserved.

I

USB1_ULPI_CLK — ULPI link CLK signal. 60 MHz clock
generated by the PHY.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

O

CGU_OUT0 — CGU spare clock output 0.

O

I2S1_TX_MCLK — I2S1 transmit master clock.

I/O

GPIO4[12] — General purpose digital input/output pin.

O

MCABORT — Motor control PWM, LOW-active fast abort.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

I

ENET_CRS — Ethernet Carrier Sense (MII interface).

I/O

SGPIO0 — General purpose digital input/output pin.

I/O

SSP0_SSEL — Slave Select for SSP0.

I/O

GPIO4[13] — General purpose digital input/output pin.

O

MCOA2 — Motor control PWM channel 2, output A.

-

R — Function reserved.

-

R — Function reserved.

I/O

I2S0_TX_WS — Transmit Word Select. It is driven by the
master and received by the slave. Corresponds to the signal
WS in the I2S-bus specification.

I

ENET_RX_ER — Ethernet receive error (MII interface).

I/O

SGPIO1 — General purpose digital input/output pin.

I/O

SSP0_MISO — Master In Slave Out for SSP0.

I/O

GPIO4[14] — General purpose digital input/output pin.

O

MCOB2 — Motor control PWM channel 2, output B.

-

R — Function reserved.

-

R — Function reserved.

I/O

I2S0_TX_SDA — I2S transmit data. It is driven by the
transmitter and read by the receiver. Corresponds to the signal
SD in the I2S-bus specification.

I

ENET_RXD3 — Ethernet receive data 3 (MII interface).

I/O

SGPIO2 — General purpose digital input/output pin.

I/O

SSP0_MOSI — Master Out Slave in for SSP0.

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NXP Semiconductors

Chapter 16: LPC43xx/LPC43Sxx Pin configuration

P9_4

P9_5

-

-

N10

M9

M8

L7

-

-

-

69

[2]

[2]

[2]

N;
PU

N;
PU

N;
PU

Type

P5

Description

[1]

LQFP144

M6

Reset state

TFBGA100

P9_3

TFBGA180

Symbol

LBGA256

Table 184. LPC4350/30/20/10 and LPC43S50/S30/S20 pin descriptions …continued
LCD, Ethernet, USB0, and USB1 functions are not available on all parts.

I/O

GPIO4[15] — General purpose digital input/output pin.

O

MCOA0 — Motor control PWM channel 0, output A.

O

USB1_IND1 — USB1 Port indicator LED control output 1.

-

R — Function reserved.

-

R — Function reserved.

I

ENET_RXD2 — Ethernet receive data 2 (MII interface).

I/O

SGPIO9 — General purpose digital input/output pin.

O

U3_TXD — Transmitter output for USART3.

-

R — Function reserved.

O

MCOB0 — Motor control PWM channel 0, output B.

O

USB1_IND0 — USB1 Port indicator LED control output 0.

-

R — Function reserved.

I/O

GPIO5[17] — General purpose digital input/output pin.

O

ENET_TXD2 — Ethernet transmit data 2 (MII interface).

I/O

SGPIO4 — General purpose digital input/output pin.

I

U3_RXD — Receiver input for USART3.

-

R — Function reserved.

O

MCOA1 — Motor control PWM channel 1, output A.

O

USB1_PPWR — VBUS drive signal (towards external charge
pump or power management unit); indicates that VBUS must
be driven (active high).
Add a pull-down resistor to disable the power switch at reset.
This signal has opposite polarity compared to the USB_PPWR
used on other NXP LPC parts.

UM10503

User manual

-

R — Function reserved.

I/O

GPIO5[18] — General purpose digital input/output pin.

O

ENET_TXD3 — Ethernet transmit data 3 (MII interface).

I/O

SGPIO3 — General purpose digital input/output pin.

O

U0_TXD — Transmitter output for USART0.

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277 of 1444

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Chapter 16: LPC43xx/LPC43Sxx Pin configuration

PA_0

PA_1

PA_2

UM10503

User manual

-

72

L12

J14

K15

L10

H12

J13

-

-

-

-

-

-

[2]

[2]

[3]

[3]

N;
PU

N;
PU

N;
PU

N;
PU

Type

M9

Description

[1]

LQFP144

L11

Reset state

TFBGA100

P9_6

TFBGA180

Symbol

LBGA256

Table 184. LPC4350/30/20/10 and LPC43S50/S30/S20 pin descriptions …continued
LCD, Ethernet, USB0, and USB1 functions are not available on all parts.

I/O

GPIO4[11] — General purpose digital input/output pin.

O

MCOB1 — Motor control PWM channel 1, output B.

I

USB1_PWR_FAULT — USB1 Port power fault signal
indicating over-current condition; this signal monitors
over-current on the USB1 bus (external circuitry required to
detect over-current condition).

-

R — Function reserved.

-

R — Function reserved.

I

ENET_COL — Ethernet Collision detect (MII interface).

I/O

SGPIO8 — General purpose digital input/output pin.

I

U0_RXD — Receiver input for USART0.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

O

I2S1_RX_MCLK — I2S1 receive master clock.

O

CGU_OUT1 — CGU spare clock output 1.

-

R — Function reserved.

I/O

GPIO4[8] — General purpose digital input/output pin.

I

QEI_IDX — Quadrature Encoder Interface INDEX input.

-

R — Function reserved.

O

U2_TXD — Transmitter output for USART2.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

I/O

GPIO4[9] — General purpose digital input/output pin.

I

QEI_PHB — Quadrature Encoder Interface PHB input.

-

R — Function reserved.

I

U2_RXD — Receiver input for USART2.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

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Rev. 2.4 — 22 August 2018

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278 of 1444

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NXP Semiconductors

Chapter 16: LPC43xx/LPC43Sxx Pin configuration

PA_4

PB_0

PB_1

UM10503

User manual

-

-

G13

B15

A14

E12

D14

A13

-

-

-

-

-

-

[3]

[2]

[2]

[2]

N;
PU

N;
PU

N;
PU

N;
PU

Type

E10

Description

[1]

LQFP144

H11

Reset state

TFBGA100

PA_3

TFBGA180

Symbol

LBGA256

Table 184. LPC4350/30/20/10 and LPC43S50/S30/S20 pin descriptions …continued
LCD, Ethernet, USB0, and USB1 functions are not available on all parts.

I/O

GPIO4[10] — General purpose digital input/output pin.

I

QEI_PHA — Quadrature Encoder Interface PHA input.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

O

CTOUT_9 — SCT output 9. Match output 3 of timer 3.

-

R — Function reserved.

I/O

EMC_A23 — External memory address line 23.

I/O

GPIO5[19] — General purpose digital input/output pin.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

O

CTOUT_10 — SCT output 10. Match output 3 of timer 3.

O

LCD_VD23 — LCD data.

-

R — Function reserved.

I/O

GPIO5[20] — General purpose digital input/output pin.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

I

USB1_ULPI_DIR — ULPI link DIR signal. Controls the ULP
data line direction.

O

LCD_VD22 — LCD data.

-

R — Function reserved.

I/O

GPIO5[21] — General purpose digital input/output pin.

O

CTOUT_6 — SCT output 6. Match output 2 of timer 1.

-

R — Function reserved.

-

R — Function reserved.

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Rev. 2.4 — 22 August 2018

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279 of 1444

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NXP Semiconductors

Chapter 16: LPC43xx/LPC43Sxx Pin configuration

PB_3

PB_4

PB_5

UM10503

User manual

-

-

A13

B11

A12

A12

B10

A11

-

-

-

-

-

-

[2]

[2]

[2]

[2]

N;
PU

N;
PU

N;
PU

N;
PU

Type

B11

Description

[1]

LQFP144

B12

Reset state

TFBGA100

PB_2

TFBGA180

Symbol

LBGA256

Table 184. LPC4350/30/20/10 and LPC43S50/S30/S20 pin descriptions …continued
LCD, Ethernet, USB0, and USB1 functions are not available on all parts.

-

R — Function reserved.

I/O

USB1_ULPI_D7 — ULPI link bidirectional data line 7.

O

LCD_VD21 — LCD data.

-

R — Function reserved.

I/O

GPIO5[22] — General purpose digital input/output pin.

O

CTOUT_7 — SCT output 7. Match output 3 of timer 1.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

I/O

USB1_ULPI_D6 — ULPI link bidirectional data line 6.

O

LCD_VD20 — LCD data.

-

R — Function reserved.

I/O

GPIO5[23] — General purpose digital input/output pin.

O

CTOUT_8 — SCT output 8. Match output 0 of timer 2.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

I/O

USB1_ULPI_D5 — ULPI link bidirectional data line 5.

O

LCD_VD15 — LCD data.

-

R — Function reserved.

I/O

GPIO5[24] — General purpose digital input/output pin.

I

CTIN_5 — SCT input 5. Capture input 2 of timer 2.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

I/O

USB1_ULPI_D4 — ULPI link bidirectional data line 4.

O

LCD_VD14 — LCD data.

-

R — Function reserved.

I/O

GPIO5[25] — General purpose digital input/output pin.

I

CTIN_7 — SCT input 7.

O

LCD_PWR — LCD panel power enable.

-

R — Function reserved.

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Chapter 16: LPC43xx/LPC43Sxx Pin configuration

PC_0

PC_1

PC_2

UM10503

User manual

-

-

D4

E4

F6

-

-

-

-

-

-

-

-

-

[5]

[5]

[2]

[2]

N;
PU

N;
PU

N;
PU

N;
PU

Type

C5

Description

[1]

LQFP144

A6

Reset state

TFBGA100

PB_6

TFBGA180

Symbol

LBGA256

Table 184. LPC4350/30/20/10 and LPC43S50/S30/S20 pin descriptions …continued
LCD, Ethernet, USB0, and USB1 functions are not available on all parts.

-

R — Function reserved.

I/O

USB1_ULPI_D3 — ULPI link bidirectional data line 3.

O

LCD_VD13 — LCD data.

-

R — Function reserved.

I/O

GPIO5[26] — General purpose digital input/output pin.

I

CTIN_6 — SCT input 6. Capture input 1 of timer 3.

O

LCD_VD19 — LCD data.

-

R — Function reserved.

AI

ADC0_6 — ADC0 and ADC1, input channel 6. Configure the
pin as GPIO input and use the ADC function select register in
the SCU to select the ADC.

-

R — Function reserved.

I

USB1_ULPI_CLK — ULPI link CLK signal. 60 MHz clock
generated by the PHY.

-

R — Function reserved.

I/O

ENET_RX_CLK — Ethernet Receive Clock (MII interface).

O

LCD_DCLK — LCD panel clock.

-

R — Function reserved.

-

R — Function reserved.

I/O

SD_CLK — SD/MMC card clock.

AI

ADC1_1 — ADC1 and ADC0, input channel 1. Configure the
pin as USB1_ULPI_CLK input and use the ADC function select
register in the SCU to select the ADC.

I/O

USB1_ULPI_D7 — ULPI link bidirectional data line 7.

-

R — Function reserved.

I

U1_RI — Ring Indicator input for UART 1.

O

ENET_MDC — Ethernet MIIM clock.

I/O

GPIO6[0] — General purpose digital input/output pin.

-

R — Function reserved.

I

T3_CAP0 — Capture input 0 of timer 3.

O

SD_VOLT0 — SD/MMC bus voltage select output 0.

I/O

USB1_ULPI_D6 — ULPI link bidirectional data line 6.

-

R — Function reserved.

I

U1_CTS — Clear to Send input for UART 1.

O

ENET_TXD2 — Ethernet transmit data 2 (MII interface).

I/O

GPIO6[1] — General purpose digital input/output pin.

-

R — Function reserved.

-

R — Function reserved.

O

SD_RST — SD/MMC reset signal for MMC4.4 card.

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NXP Semiconductors

Chapter 16: LPC43xx/LPC43Sxx Pin configuration

PC_4

-

-

F4

-

-

-

[5]

[2]

N;
PU

N;
PU

Type

-

Description

[1]

LQFP144

F5

Reset state

TFBGA100

PC_3

TFBGA180

Symbol

LBGA256

Table 184. LPC4350/30/20/10 and LPC43S50/S30/S20 pin descriptions …continued
LCD, Ethernet, USB0, and USB1 functions are not available on all parts.

I/O

USB1_ULPI_D5 — ULPI link bidirectional data line 5.

-

R — Function reserved.

O

U1_RTS — Request to Send output for UART 1. Can also be
configured to be an RS-485/EIA-485 output enable signal for
UART 1.

O

ENET_TXD3 — Ethernet transmit data 3 (MII interface).

I/O

GPIO6[2] — General purpose digital input/output pin.

-

R — Function reserved.

-

R — Function reserved.

O

SD_VOLT1 — SD/MMC bus voltage select output 1.

AI

ADC1_0 — DAC, ADC0 and ADC1, input channel 0. Configure
the pin as GPIO input and use the ADC function select register
in the SCU to select the ADC.

-

R — Function reserved.

I/O

USB1_ULPI_D4 — ULPI link bidirectional data line 4.

-

R — Function reserved.
ENET_TX_EN — Ethernet transmit enable (RMII/MII
interface).

PC_5

PC_6

UM10503

User manual

G4

H6

-

-

-

-

-

-

[2]

[2]

N;
PU

N;
PU

I/O

GPIO6[3] — General purpose digital input/output pin.

-

R — Function reserved.

I

T3_CAP1 — Capture input 1 of timer 3.

I/O

SD_DAT0 — SD/MMC data bus line 0.

-

R — Function reserved.

I/O

USB1_ULPI_D3 — ULPI link bidirectional data line 3.

-

R — Function reserved.

O

ENET_TX_ER — Ethernet Transmit Error (MII interface).

I/O

GPIO6[4] — General purpose digital input/output pin.

-

R — Function reserved.

I

T3_CAP2 — Capture input 2 of timer 3.

I/O

SD_DAT1 — SD/MMC data bus line 1.

-

R — Function reserved.

I/O

USB1_ULPI_D2 — ULPI link bidirectional data line 2.

-

R — Function reserved.

I

ENET_RXD2 — Ethernet receive data 2 (MII interface).

I/O

GPIO6[5] — General purpose digital input/output pin.

-

R — Function reserved.

I

T3_CAP3 — Capture input 3 of timer 3.

I/O

SD_DAT2 — SD/MMC data bus line 2.

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Chapter 16: LPC43xx/LPC43Sxx Pin configuration

PC_8

PC_9

PC_10

UM10503

User manual

-

-

N4

K2

M5

-

-

-

-

-

-

-

-

-

[2]

[2]

[2]

[2]

N;
PU

N;
PU

N;
PU

N;
PU

Type

-

Description

[1]

LQFP144

G5

Reset state

TFBGA100

PC_7

TFBGA180

Symbol

LBGA256

Table 184. LPC4350/30/20/10 and LPC43S50/S30/S20 pin descriptions …continued
LCD, Ethernet, USB0, and USB1 functions are not available on all parts.

-

R — Function reserved.

I/O

USB1_ULPI_D1 — ULPI link bidirectional data line 1.

-

R — Function reserved.

I

ENET_RXD3 — Ethernet receive data 3 (MII interface).

I/O

GPIO6[6] — General purpose digital input/output pin.

-

R — Function reserved.

O

T3_MAT0 — Match output 0 of timer 3.

I/O

SD_DAT3 — SD/MMC data bus line 3.

-

R — Function reserved.

I/O

USB1_ULPI_D0 — ULPI link bidirectional data line 0.

-

R — Function reserved.

I

ENET_RX_DV — Ethernet Receive Data Valid (RMII/MII
interface).

I/O

GPIO6[7] — General purpose digital input/output pin.

-

R — Function reserved.

O

T3_MAT1 — Match output 1 of timer 3.

I

SD_CD — SD/MMC card detect input.

-

R — Function reserved.

I

USB1_ULPI_NXT — ULPI link NXT signal. Data flow control
signal from the PHY.

-

R — Function reserved.

I

ENET_RX_ER — Ethernet receive error (MII interface).

I/O

GPIO6[8] — General purpose digital input/output pin.

-

R — Function reserved.

O

T3_MAT2 — Match output 2 of timer 3.

O

SD_POW — SD/MMC power monitor output.

-

R — Function reserved.

O

USB1_ULPI_STP — ULPI link STP signal. Asserted to end or
interrupt transfers to the PHY.

I

U1_DSR — Data Set Ready input for UART 1.

-

R — Function reserved.

I/O

GPIO6[9] — General purpose digital input/output pin.

-

R — Function reserved.

O

T3_MAT3 — Match output 3 of timer 3.

I/O

SD_CMD — SD/MMC command signal.

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Rev. 2.4 — 22 August 2018

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Chapter 16: LPC43xx/LPC43Sxx Pin configuration

PC_12

PC_13

PC_14

UM10503

User manual

-

-

L6

M1

N1

-

-

-

-

-

-

-

-

-

[2]

[2]

[2]

[2]

N;
PU

N;
PU

N;
PU

N;
PU

Type

-

Description

[1]

LQFP144

L5

Reset state

TFBGA100

PC_11

TFBGA180

Symbol

LBGA256

Table 184. LPC4350/30/20/10 and LPC43S50/S30/S20 pin descriptions …continued
LCD, Ethernet, USB0, and USB1 functions are not available on all parts.

-

R — Function reserved.

I

USB1_ULPI_DIR — ULPI link DIR signal. Controls the ULPI
data line direction.

I

U1_DCD — Data Carrier Detect input for UART 1.

-

R — Function reserved.

I/O

GPIO6[10] — General purpose digital input/output pin.

-

R — Function reserved.

-

R — Function reserved.

I/O

SD_DAT4 — SD/MMC data bus line 4.

-

R — Function reserved.

-

R — Function reserved.

O

U1_DTR — Data Terminal Ready output for UART 1. Can also
be configured to be an RS-485/EIA-485 output enable signal
for UART 1.

-

R — Function reserved.

I/O

GPIO6[11] — General purpose digital input/output pin.

I/O

SGPIO11 — General purpose digital input/output pin.

I/O

I2S0_TX_SDA — I2S transmit data. It is driven by the
transmitter and read by the receiver. Corresponds to the signal
SD in the I2S-bus specification.

I/O

SD_DAT5 — SD/MMC data bus line 5.

-

R — Function reserved.

-

R — Function reserved.

O

U1_TXD — Transmitter output for UART 1.

-

R — Function reserved.

I/O

GPIO6[12] — General purpose digital input/output pin.

I/O

SGPIO12 — General purpose digital input/output pin.

I/O

I2S0_TX_WS — Transmit Word Select. It is driven by the
master and received by the slave. Corresponds to the signal
WS in the I2S-bus specification.

I/O

SD_DAT6 — SD/MMC data bus line 6.

-

R — Function reserved.

-

R — Function reserved.

I

U1_RXD — Receiver input for UART 1.

-

R — Function reserved.

I/O

GPIO6[13] — General purpose digital input/output pin.

I/O

SGPIO13 — General purpose digital input/output pin.

O

ENET_TX_ER — Ethernet Transmit Error (MII interface).

I/O

SD_DAT7 — SD/MMC data bus line 7.

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Rev. 2.4 — 22 August 2018

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284 of 1444

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NXP Semiconductors

Chapter 16: LPC43xx/LPC43Sxx Pin configuration

PD_1

PD_2

PD_3

UM10503

User manual

-

-

P1

R1

P4

-

-

-

-

-

-

-

-

-

[2]

[2]

[2]

[2]

N;
PU

N;
PU

N;
PU

N;
PU

Type

-

Description

[1]

LQFP144

N2

Reset state

TFBGA100

PD_0

TFBGA180

Symbol

LBGA256

Table 184. LPC4350/30/20/10 and LPC43S50/S30/S20 pin descriptions …continued
LCD, Ethernet, USB0, and USB1 functions are not available on all parts.

-

R — Function reserved.

O

CTOUT_15 — SCT output 15. Match output 3 of timer 3.

O

EMC_DQMOUT2 — Data mask 2 used with SDRAM and static
devices.

-

R — Function reserved.

I/O

GPIO6[14] — General purpose digital input/output pin.

-

R — Function reserved.

-

R — Function reserved.

I/O

SGPIO4 — General purpose digital input/output pin.

-

R — Function reserved.

-

R — Function reserved.

O

EMC_CKEOUT2 — SDRAM clock enable 2.

-

R — Function reserved.

I/O

GPIO6[15] — General purpose digital input/output pin.

O

SD_POW — SD/MMC power monitor output.

-

R — Function reserved.

I/O

SGPIO5 — General purpose digital input/output pin.

-

R — Function reserved.

O

CTOUT_7 — SCT output 7. Match output 3 of timer 1.

I/O

EMC_D16 — External memory data line 16.

-

R — Function reserved.

I/O

GPIO6[16] — General purpose digital input/output pin.

-

R — Function reserved.

-

R — Function reserved.

I/O

SGPIO6 — General purpose digital input/output pin.

-

R — Function reserved.

O

CTOUT_6 — SCT output 7. Match output 2 of timer 1.

I/O

EMC_D17 — External memory data line 17.

-

R — Function reserved.

I/O

GPIO6[17] — General purpose digital input/output pin.

-

R — Function reserved.

-

R — Function reserved.

I/O

SGPIO7 — General purpose digital input/output pin.

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Rev. 2.4 — 22 August 2018

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285 of 1444

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NXP Semiconductors

Chapter 16: LPC43xx/LPC43Sxx Pin configuration

PD_5

PD_6

PD_7

UM10503

User manual

-

-

P6

R6

T6

-

-

-

-

-

-

-

-

-

[2]

[2]

[2]

[2]

N;
PU

N;
PU

N;
PU

N;
PU

Type

-

Description

[1]

LQFP144

T2

Reset state

TFBGA100

PD_4

TFBGA180

Symbol

LBGA256

Table 184. LPC4350/30/20/10 and LPC43S50/S30/S20 pin descriptions …continued
LCD, Ethernet, USB0, and USB1 functions are not available on all parts.

-

R — Function reserved.

O

CTOUT_8 — SCT output 8. Match output 0 of timer 2.

I/O

EMC_D18 — External memory data line 18.

-

R — Function reserved.

I/O

GPIO6[18] — General purpose digital input/output pin.

-

R — Function reserved.

-

R — Function reserved.

I/O

SGPIO8 — General purpose digital input/output pin.

-

R — Function reserved.

O

CTOUT_9 — SCT output 9. Match output 3 of timer 3.

I/O

EMC_D19 — External memory data line 19.

-

R — Function reserved.

I/O

GPIO6[19] — General purpose digital input/output pin.

-

R — Function reserved.

-

R — Function reserved.

I/O

SGPIO9 — General purpose digital input/output pin.

-

R — Function reserved.

O

CTOUT_10 — SCT output 10. Match output 3 of timer 3.

I/O

EMC_D20 — External memory data line 20.

-

R — Function reserved.

I/O

GPIO6[20] — General purpose digital input/output pin.

-

R — Function reserved.

-

R — Function reserved.

I/O

SGPIO10 — General purpose digital input/output pin.

-

R — Function reserved.

I

CTIN_5 — SCT input 5. Capture input 2 of timer 2.

I/O

EMC_D21 — External memory data line 21.

-

R — Function reserved.

I/O

GPIO6[21] — General purpose digital input/output pin.

-

R — Function reserved.

-

R — Function reserved.

I/O

SGPIO11 — General purpose digital input/output pin.

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Rev. 2.4 — 22 August 2018

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286 of 1444

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NXP Semiconductors

Chapter 16: LPC43xx/LPC43Sxx Pin configuration

PD_9

PD_10

PD_11

UM10503

User manual

-

-

T11

P11

N9

-

-

M7

-

-

-

-

-

-

[2]

[2]

[2]

[2]

N;
PU

N;
PU

N;
PU

N;
PU

Type

-

Description

[1]

LQFP144

P8

Reset state

TFBGA100

PD_8

TFBGA180

Symbol

LBGA256

Table 184. LPC4350/30/20/10 and LPC43S50/S30/S20 pin descriptions …continued
LCD, Ethernet, USB0, and USB1 functions are not available on all parts.

-

R — Function reserved.

I

CTIN_6 — SCT input 6. Capture input 1 of timer 3.

I/O

EMC_D22 — External memory data line 22.

-

R — Function reserved.

I/O

GPIO6[22] — General purpose digital input/output pin.

-

R — Function reserved.

-

R — Function reserved.

I/O

SGPIO12 — General purpose digital input/output pin.

-

R — Function reserved.

O

CTOUT_13 — SCT output 13. Match output 3 of timer 3.

I/O

EMC_D23 — External memory data line 23.

-

R — Function reserved.

I/O

GPIO6[23] — General purpose digital input/output pin.

-

R — Function reserved.

-

R — Function reserved.

I/O

SGPIO13 — General purpose digital input/output pin.

-

R — Function reserved.

I

CTIN_1 — SCT input 1. Capture input 1 of timer 0. Capture
input 1 of timer 2.

O

EMC_BLS3 — LOW active Byte Lane select signal 3.

-

R — Function reserved.

I/O

GPIO6[24] — General purpose digital input/output pin.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

O

EMC_CS3 — LOW active Chip Select 3 signal.

-

R — Function reserved.

I/O

GPIO6[25] — General purpose digital input/output pin.

I/O

USB1_ULPI_D0 — ULPI link bidirectional data line 0.

O

CTOUT_14 — SCT output 14. Match output 2 of timer 3.

-

R — Function reserved.

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Rev. 2.4 — 22 August 2018

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287 of 1444

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NXP Semiconductors

Chapter 16: LPC43xx/LPC43Sxx Pin configuration

PD_13

PD_14

PD_15

UM10503

User manual

-

-

T14

R13

T15

-

L11

P13

-

-

-

-

-

-

[2]

[2]

[2]

[2]

N;
PU

N;
PU

N;
PU

N;
PU

Type

P9

Description

[1]

LQFP144

N11

Reset state

TFBGA100

PD_12

TFBGA180

Symbol

LBGA256

Table 184. LPC4350/30/20/10 and LPC43S50/S30/S20 pin descriptions …continued
LCD, Ethernet, USB0, and USB1 functions are not available on all parts.

-

R — Function reserved.

-

R — Function reserved.

O

EMC_CS2 — LOW active Chip Select 2 signal.

-

R — Function reserved.

I/O

GPIO6[26] — General purpose digital input/output pin.

-

R — Function reserved.

O

CTOUT_10 — SCT output 10. Match output 3 of timer 3.

-

R — Function reserved.

-

R — Function reserved.

I

CTIN_0 — SCT input 0. Capture input 0 of timer 0, 1, 2, 3.

O

EMC_BLS2 — LOW active Byte Lane select signal 2.

-

R — Function reserved.

I/O

GPIO6[27] — General purpose digital input/output pin.

-

R — Function reserved.

O

CTOUT_13 — SCT output 13. Match output 3 of timer 3.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

O

EMC_DYCS2 — SDRAM chip select 2.

-

R — Function reserved.

I/O

GPIO6[28] — General purpose digital input/output pin.

-

R — Function reserved.

O

CTOUT_11 — SCT output 11. Match output 3 of timer 2.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

I/O

EMC_A17 — External memory address line 17.

-

R — Function reserved.

I/O

GPIO6[29] — General purpose digital input/output pin.

I

SD_WP — SD/MMC card write protect input.

O

CTOUT_8 — SCT output 8. Match output 0 of timer 2.

-

R — Function reserved.

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288 of 1444

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NXP Semiconductors

Chapter 16: LPC43xx/LPC43Sxx Pin configuration

PE_0

PE_1

PE_2

UM10503

User manual

-

-

P14

N14

M14

N12

-

M12 -

L12

-

-

-

-

[2]

[2]

[2]

[2]

N;
PU

N;
PU

N;
PU

N;
PU

Type

P12

Description

[1]

LQFP144

R14

Reset state

TFBGA100

PD_16

TFBGA180

Symbol

LBGA256

Table 184. LPC4350/30/20/10 and LPC43S50/S30/S20 pin descriptions …continued
LCD, Ethernet, USB0, and USB1 functions are not available on all parts.

-

R — Function reserved.

-

R — Function reserved.

I/O

EMC_A16 — External memory address line 16.

-

R — Function reserved.

I/O

GPIO6[30] — General purpose digital input/output pin.

O

SD_VOLT2 — SD/MMC bus voltage select output 2.

O

CTOUT_12 — SCT output 12. Match output 3 of timer 3.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

I/O

EMC_A18 — External memory address line 18.

I/O

GPIO7[0] — General purpose digital input/output pin.

O

CAN1_TD — CAN1 transmitter output.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

I/O

EMC_A19 — External memory address line 19.

I/O

GPIO7[1] — General purpose digital input/output pin.

I

CAN1_RD — CAN1 receiver input.

-

R — Function reserved.

-

R — Function reserved.

I

ADCTRIG0 — ADC trigger input 0.

I

CAN0_RD — CAN receiver input.

-

R — Function reserved.

I/O

EMC_A20 — External memory address line 20.

I/O

GPIO7[2] — General purpose digital input/output pin.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

All information provided in this document is subject to legal disclaimers.

Rev. 2.4 — 22 August 2018

© NXP B.V. 2018. All rights reserved.

289 of 1444

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NXP Semiconductors

Chapter 16: LPC43xx/LPC43Sxx Pin configuration

PE_4

PE_5

PE_6

UM10503

User manual

-

-

K13

N16

M16

J11

-

-

-

-

-

-

-

-

[2]

[2]

[2]

[2]

N;
PU

N;
PU

N;
PU

N;
PU

Type

K10

Description

[1]

LQFP144

K12

Reset state

TFBGA100

PE_3

TFBGA180

Symbol

LBGA256

Table 184. LPC4350/30/20/10 and LPC43S50/S30/S20 pin descriptions …continued
LCD, Ethernet, USB0, and USB1 functions are not available on all parts.

-

R — Function reserved.

O

CAN0_TD — CAN transmitter output.

I

ADCTRIG1 — ADC trigger input 1.

I/O

EMC_A21 — External memory address line 21.

I/O

GPIO7[3] — General purpose digital input/output pin.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

I

NMI — External interrupt input to NMI.

-

R — Function reserved.

I/O

EMC_A22 — External memory address line 22.

I/O

GPIO7[4] — General purpose digital input/output pin.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

O

CTOUT_3 — SCT output 3. Match output 3 of timer 0.

O

U1_RTS — Request to Send output for UART 1. Can also be
configured to be an RS-485/EIA-485 output enable signal for
UART 1.

I/O

EMC_D24 — External memory data line 24.

I/O

GPIO7[5] — General purpose digital input/output pin.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

O

CTOUT_2 — SCT output 2. Match output 2 of timer 0.

I

U1_RI — Ring Indicator input for UART 1.

I/O

EMC_D25 — External memory data line 25.

I/O

GPIO7[6] — General purpose digital input/output pin.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

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Chapter 16: LPC43xx/LPC43Sxx Pin configuration

PE_8

PE_9

PE_10

UM10503

User manual

-

-

F14

E16

E14

-

-

-

-

-

-

-

-

-

[2]

[2]

[2]

[2]

N;
PU

N;
PU

N;
PU

N;
PU

Type

-

Description

[1]

LQFP144

F15

Reset state

TFBGA100

PE_7

TFBGA180

Symbol

LBGA256

Table 184. LPC4350/30/20/10 and LPC43S50/S30/S20 pin descriptions …continued
LCD, Ethernet, USB0, and USB1 functions are not available on all parts.

-

R — Function reserved.

O

CTOUT_5 — SCT output 5. Match output 3 of timer 3.

I

U1_CTS — Clear to Send input for UART1.

I/O

EMC_D26 — External memory data line 26.

I/O

GPIO7[7] — General purpose digital input/output pin.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

O

CTOUT_4 — SCT output 4. Match output 3 of timer 3.

I

U1_DSR — Data Set Ready input for UART 1.

I/O

EMC_D27 — External memory data line 27.

I/O

GPIO7[8] — General purpose digital input/output pin.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

I

CTIN_4 — SCT input 4. Capture input 2 of timer 1.

I

U1_DCD — Data Carrier Detect input for UART 1.

I/O

EMC_D28 — External memory data line 28.

I/O

GPIO7[9] — General purpose digital input/output pin.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

I

CTIN_3 — SCT input 3. Capture input 1 of timer 1.

O

U1_DTR — Data Terminal Ready output for UART 1. Can also
be configured to be an RS-485/EIA-485 output enable signal
for UART 1.

I/O

EMC_D29 — External memory data line 29.

I/O

GPIO7[10] — General purpose digital input/output pin.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

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Chapter 16: LPC43xx/LPC43Sxx Pin configuration

PE_12

PE_13

PE_14

UM10503

User manual

-

-

D15

G14

C15

-

-

-

-

-

-

-

-

-

[2]

[2]

[2]

[2]

N;
PU

N;
PU

N;
PU

N;
PU

Type

-

Description

[1]

LQFP144

D16

Reset state

TFBGA100

PE_11

TFBGA180

Symbol

LBGA256

Table 184. LPC4350/30/20/10 and LPC43S50/S30/S20 pin descriptions …continued
LCD, Ethernet, USB0, and USB1 functions are not available on all parts.

-

R — Function reserved.

O

CTOUT_12 — SCT output 12. Match output 3 of timer 3.

O

U1_TXD — Transmitter output for UART 1.

I/O

EMC_D30 — External memory data line 30.

I/O

GPIO7[11] — General purpose digital input/output pin.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

O

CTOUT_11 — SCT output 11. Match output 3 of
timer 2.

I

U1_RXD — Receiver input for UART 1.

I/O

EMC_D31 — External memory data line 31.

I/O

GPIO7[12] — General purpose digital input/output pin.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

O

CTOUT_14 — SCT output 14. Match output 2 of timer 3.

I/O

I2C1_SDA — I2C1 data input/output (this pin does not use a
specialized I2C pad).

O

EMC_DQMOUT3 — Data mask 3 used with SDRAM and static
devices.

I/O

GPIO7[13] — General purpose digital input/output pin.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

O

EMC_DYCS3 — SDRAM chip select 3.

I/O

GPIO7[14] — General purpose digital input/output pin.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

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Chapter 16: LPC43xx/LPC43Sxx Pin configuration

PF_0

PF_1

PF_2

UM10503

User manual

-

-

D12

E11

D11

-

-

-

-

-

-

-

-

-

[2]

[2]

[2]

[2]

N;
PU

O;
PU

N;
PU

N;
PU

Type

-

Description

[1]

LQFP144

E13

Reset state

TFBGA100

PE_15

TFBGA180

Symbol

LBGA256

Table 184. LPC4350/30/20/10 and LPC43S50/S30/S20 pin descriptions …continued
LCD, Ethernet, USB0, and USB1 functions are not available on all parts.

-

R — Function reserved.

O

CTOUT_0 — SCT output 0. Match output 0 of timer 0.

I/O

I2C1_SCL — I2C1 clock input/output (this pin does not use a
specialized I2C pad).

O

EMC_CKEOUT3 — SDRAM clock enable 3.

I/O

GPIO7[15] — General purpose digital input/output pin.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

I/O

SSP0_SCK — Serial clock for SSP0.

I

GP_CLKIN — General purpose clock input to the CGU.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

O

I2S1_TX_MCLK — I2S1 transmit master clock.

-

R — Function reserved.

-

R — Function reserved.

I/O

SSP0_SSEL — Slave Select for SSP0.

-

R — Function reserved.

I/O

GPIO7[16] — General purpose digital input/output pin.

-

R — Function reserved.

I/O

SGPIO0 — General purpose digital input/output pin.

-

R — Function reserved.

-

R — Function reserved.

O

U3_TXD — Transmitter output for USART3.

I/O

SSP0_MISO — Master In Slave Out for SSP0.

-

R — Function reserved.

I/O

GPIO7[17] — General purpose digital input/output pin.

-

R — Function reserved.

I/O

SGPIO1 — General purpose digital input/output pin.

-

R — Function reserved.

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Chapter 16: LPC43xx/LPC43Sxx Pin configuration

PF_4

PF_5

UM10503

User manual

-

-

D10

E9

D6

-

H4

-

120

-

[2]

[2]

[5]

N;
PU

O;
PU

N;
PU

Type

-

Description

[1]

LQFP144

E10

Reset state

TFBGA100

PF_3

TFBGA180

Symbol

LBGA256

Table 184. LPC4350/30/20/10 and LPC43S50/S30/S20 pin descriptions …continued
LCD, Ethernet, USB0, and USB1 functions are not available on all parts.

-

R — Function reserved.

I

U3_RXD — Receiver input for USART3.

I/O

SSP0_MOSI — Master Out Slave in for SSP0.

-

R — Function reserved.

I/O

GPIO7[18] — General purpose digital input/output pin.

-

R — Function reserved.

I/O

SGPIO2 — General purpose digital input/output pin.

-

R — Function reserved.

I/O

SSP1_SCK — Serial clock for SSP1.

I

GP_CLKIN — General purpose clock input to the CGU.

O

TRACECLK — Trace clock.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

O

I2S0_TX_MCLK — I2S transmit master clock.

I/O

I2S0_RX_SCK — I2S receive clock. It is driven by the master
and received by the slave. Corresponds to the signal SCK in
the I2S-bus specification.

-

R — Function reserved.

I/O

U3_UCLK — Serial clock input/output for USART3 in
synchronous mode.

I/O

SSP1_SSEL — Slave Select for SSP1.

O

TRACEDATA[0] — Trace data, bit 0.

I/O

GPIO7[19] — General purpose digital input/output pin.

-

R — Function reserved.

I/O

SGPIO4 — General purpose digital input/output pin.

-

R — Function reserved.

AI

ADC1_4 — ADC1 and ADC0, input channel 4. Configure the
pin as GPIO input and use the ADC function select register in
the SCU to select the ADC.

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Chapter 16: LPC43xx/LPC43Sxx Pin configuration

PF_7

PF_8

UM10503

User manual

-

-

B7

E6

-

-

-

-

-

-

[5]

[5]

[5]

N;
PU

N;
PU

N;
PU

Type

-

Description

[1]

LQFP144

E7

Reset state

TFBGA100

PF_6

TFBGA180

Symbol

LBGA256

Table 184. LPC4350/30/20/10 and LPC43S50/S30/S20 pin descriptions …continued
LCD, Ethernet, USB0, and USB1 functions are not available on all parts.

-

R — Function reserved.

I/O

U3_DIR — RS-485/EIA-485 output enable/direction control for
USART3.

I/O

SSP1_MISO — Master In Slave Out for SSP1.

O

TRACEDATA[1] — Trace data, bit 1.

I/O

GPIO7[20] — General purpose digital input/output pin.

-

R — Function reserved.

I/O

SGPIO5 — General purpose digital input/output pin.

I/O

I2S1_TX_SDA — I2S1 transmit data. It is driven by the
transmitter and read by the receiver. Corresponds to the signal
SD in the I2S-bus specification.

AI

ADC1_3 — ADC1 and ADC0, input channel 3. Configure the
pin as GPIO input and use the ADC function select register in
the SCU to select the ADC.

-

R — Function reserved.

I/O

U3_BAUD — Baud pin for USART3.

I/O

SSP1_MOSI — Master Out Slave in for SSP1.

O

TRACEDATA[2] — Trace data, bit 2.

I/O

GPIO7[21] — General purpose digital input/output pin.

-

R — Function reserved.

I/O

SGPIO6 — General purpose digital input/output pin.

I/O

I2S1_TX_WS — Transmit Word Select. It is driven by the
master and received by the slave. Corresponds to the signal
WS in the I2S-bus specification.

AI/
O

ADC1_7 — ADC1 and ADC0, input channel 7 or band gap
output. Configure the pin as GPIO input and use the ADC
function select register in the SCU to select the ADC.

-

R — Function reserved.

I/O

U0_UCLK — Serial clock input/output for USART0 in
synchronous mode.

I

CTIN_2 — SCT input 2. Capture input 2 of timer 0.

O

TRACEDATA[3] — Trace data, bit 3.

I/O

GPIO7[22] — General purpose digital input/output pin.

-

R — Function reserved.

I/O

SGPIO7 — General purpose digital input/output pin.

-

R — Function reserved.

AI

ADC0_2 — ADC0 and ADC1, input channel 2. Configure the
pin as GPIO input and use the ADC function select register in
the SCU to select the ADC.

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295 of 1444

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NXP Semiconductors

Chapter 16: LPC43xx/LPC43Sxx Pin configuration

PF_10

PF_11

-

-

A3

A2

-

-

-

-

-

-

[5]

[5]

[5]

N;
PU

N;
PU

N;
PU

Type

-

Description

[1]

LQFP144

D6

Reset state

TFBGA100

PF_9

TFBGA180

Symbol

LBGA256

Table 184. LPC4350/30/20/10 and LPC43S50/S30/S20 pin descriptions …continued
LCD, Ethernet, USB0, and USB1 functions are not available on all parts.

-

R — Function reserved.

I/O

U0_DIR — RS-485/EIA-485 output enable/direction control for
USART0.

O

CTOUT_1 — SCT output 1. Match output 3 of timer 3.

-

R — Function reserved.

I/O

GPIO7[23] — General purpose digital input/output pin.

-

R — Function reserved.

I/O

SGPIO3 — General purpose digital input/output pin.

-

R — Function reserved.

AI

ADC1_2 — ADC1 and ADC0, input channel 2. Configure the
pin as GPIO input and use the ADC function select register in
the SCU to select the ADC.

-

R — Function reserved.

O

U0_TXD — Transmitter output for USART0.

-

R — Function reserved.

-

R — Function reserved.

I/O

GPIO7[24] — General purpose digital input/output pin.

-

R — Function reserved.

I

SD_WP — SD/MMC card write protect input.

-

R — Function reserved.

AI

ADC0_5 — ADC0 and ADC1, input channel 5. Configure the
pin as GPIO input and use the ADC function select register in
the SCU to select the ADC.

-

R — Function reserved.

I

U0_RXD — Receiver input for USART0.

-

R — Function reserved.

-

R — Function reserved.

I/O

GPIO7[25] — General purpose digital input/output pin.

-

R — Function reserved.

O

SD_VOLT2 — SD/MMC bus voltage select output 2.

-

R — Function reserved.

AI

ADC1_5 — ADC1 and ADC0, input channel 5. Configure the
pin as GPIO input and use the ADC function select register in
the SCU to select the ADC.

Clock pins

UM10503

User manual

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Chapter 16: LPC43xx/LPC43Sxx Pin configuration

CLK1

CLK2

CLK3

K3

45

T10

D14

P12

-

P10

-

-

K6

-

-

99

-

[4]

[4]

[4]

[4]

O;
PU

O;
PU

O;
PU

O;
PU

Type

M4

Description

[1]

LQFP144

N5

Reset state

TFBGA100

CLK0

TFBGA180

Symbol

LBGA256

Table 184. LPC4350/30/20/10 and LPC43S50/S30/S20 pin descriptions …continued
LCD, Ethernet, USB0, and USB1 functions are not available on all parts.

O

EMC_CLK0 — SDRAM clock 0.

O

CLKOUT — Clock output pin.

-

R — Function reserved.

-

R — Function reserved.

I/O

SD_CLK — SD/MMC card clock.

O

EMC_CLK01 — SDRAM clock 0 and clock 1 combined.

I/O

SSP1_SCK — Serial clock for SSP1.

I

ENET_TX_CLK (ENET_REF_CLK) — Ethernet Transmit
Clock (MII interface) or Ethernet Reference Clock (RMII
interface).

O

EMC_CLK1 — SDRAM clock 1.

O

CLKOUT — Clock output pin.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

O

CGU_OUT0 — CGU spare clock output 0.

-

R — Function reserved.

O

I2S1_TX_MCLK — I2S1 transmit master clock.

O

EMC_CLK3 — SDRAM clock 3.

O

CLKOUT — Clock output pin.

-

R — Function reserved.

-

R — Function reserved.

I/O

SD_CLK — SD/MMC card clock.

O

EMC_CLK23 — SDRAM clock 2 and clock 3 combined.

O

I2S0_TX_MCLK — I2S transmit master clock.

I/O

I2S1_RX_SCK — Receive Clock. It is driven by the master and
received by the slave. Corresponds to the signal SCK in the
I2S-bus specification.

O

EMC_CLK2 — SDRAM clock 2.

O

CLKOUT — Clock output pin.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

O

CGU_OUT1 — CGU spare clock output 1.

-

R — Function reserved.

I/O

I2S1_RX_SCK — Receive Clock. It is driven by the master and
received by the slave. Corresponds to the signal SCK in the
I2S-bus specification.

Debug pins
UM10503

User manual

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NXP Semiconductors

Chapter 16: LPC43xx/LPC43Sxx Pin configuration

LQFP144

L4

K4

A6

28

[2]

I

I

JTAG interface control signal. Also used for boundary scan.

TCK/SWDCLK

J5

G5

H2

27

[2]

I; F

I

Test Clock for JTAG interface (default) or Serial Wire (SW)
clock.

TRST

M4

L4

B4

29

[2]

I; PU I

Test Reset for JTAG interface.

I; PU I

Test Mode Select for JTAG interface (default) or SW debug
data input/output.
Test Data Out for JTAG interface (default) or SW trace output.

Type

TFBGA100

DBGEN

[1]

TFBGA180

Description

LBGA256

Symbol

Reset state

Table 184. LPC4350/30/20/10 and LPC43S50/S30/S20 pin descriptions …continued
LCD, Ethernet, USB0, and USB1 functions are not available on all parts.

TMS/SWDIO

K6

K5

C4

30

[2]

TDO/SWO

K5

J5

H3

31

[2]

O

I; PU I

Test Data In for JTAG interface.

O

J4

H4

G3

26

[2]

USB0_DP

F2

E2

E1

18

[6]

-

I/O

USB0 bidirectional D+ line. Do not add an external series
resistor.

USB0_DM

G2

F2

E2

20

[6]

-

I/O

USB0 bidirectional D line. Do not add an external series
resistor.

USB0_VBUS

F1

E1

E3

21

[6]

-

I/O

VBUS pin (power on USB cable). This pin includes an internal
pull-down resistor of 64 k (typical)  16 k.

I

Indicates to the transceiver whether connected as an A-device
(USB0_ID LOW) or B-device (USB0_ID HIGH). For OTG this
pin has an internal pull-up resistor.

TDI
USB0 pins

[7]

USB0_ID

H2

G2

F1

22

[8]

-

USB0_RREF

H1

G1

F3

24

[8]

-

USB1_DP

F12

D11

E9

89

[9]

-

I/O

USB1 bidirectional D+ line. Add an external series resistor of
33  +/- 2 %.

USB1_DM

G12

E11

E10 90

[9]

-

I/O

USB1 bidirectional D line. Add an external series resistor of
33  +/- 2 %.

I2C0_SCL

L15

K13

D6

92

[10]

I; F

I/O

I2C clock input/output. Open-drain output (for I2C-bus
compliance).

I2C0_SDA

L16

K14

E6

93

[10]

I; F

I/O

I2C data input/output. Open-drain output (for I2C-bus
compliance).

12.0 k (accuracy 1 %) on-board resistor to ground for current
reference.

USB1 pins

I2C-bus pins

Reset and wake-up pins
RESET

D9

C7

B6

128

[11]

I; IA

I

External reset input: A LOW-going pulse as short as 50 ns on
this pin resets the device, causing I/O ports and peripherals to
take on their default states, and processor execution to begin
at address 0.

WAKEUP0

A9

A9

A4

130

[11]

I; IA

I

External wake-up input; can raise an interrupt and can cause
wake-up from any of the low power modes. A pulse with a
duration > 45 ns wakes up the part.

WAKEUP1

A10

C8

-

-

[11]

I; IA

I

External wake-up input; can raise an interrupt and can cause
wake-up from any of the low power modes. A pulse with a
duration > 45 ns wakes up the part.

UM10503

User manual

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298 of 1444

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NXP Semiconductors

Chapter 16: LPC43xx/LPC43Sxx Pin configuration

LQFP144

C9

E5

-

-

[11]

I; IA

I

External wake-up input; can raise an interrupt and can cause
wake-up from any of the low power modes. A pulse with a
duration > 45 ns wakes up the part.

WAKEUP3

D8

-

-

-

[11]

I; IA

I

External wake-up input; can raise an interrupt and can cause
wake-up from any of the low power modes. A pulse with a
duration > 45 ns wakes up the part.

ADC0_0/
ADC1_0/DAC

E3

B6

A2

6

[8]

I; IA

I

ADC input channel 0. Shared between 10-bit ADC0/1 and
DAC.

ADC0_1/
ADC1_1

C3

C4

A1

2

[8]

I; IA

I

ADC input channel 1. Shared between 10-bit ADC0/1.

ADC0_2/
ADC1_2

A4

B3

B3

143

[8]

I; IA

I

ADC input channel 2. Shared between 10-bit ADC0/1.

ADC0_3/
ADC1_3

B5

B4

A3

139

[8]

I; IA

I

ADC input channel 3. Shared between 10-bit ADC0/1.

ADC0_4/
ADC1_4

C6

A5

-

138

[8]

I; IA

I

ADC input channel 4. Shared between 10-bit ADC0/1.

ADC0_5/
ADC1_5

B3

C3

-

144

[8]

I; IA

I

ADC input channel 5. Shared between 10-bit ADC0/1.

ADC0_6/
ADC1_6

A5

A4

-

142

[8]

I; IA

I

ADC input channel 6. Shared between 10-bit ADC0/1.

ADC0_7/
ADC1_7

C5

B5

-

136

[8]

I; IA

I

ADC input channel 7. Shared between 10-bit ADC0/1.

RTC_ALARM

A11

A10

C3

129

[11]

-

O

RTC controlled output.

RTCX1

A8

A8

A5

125

[8]

-

I

Input to the RTC 32 kHz ultra-low power oscillator circuit.

-

O

Output from the RTC 32 kHz ultra-low power oscillator circuit.

Type

TFBGA100

WAKEUP2

[1]

TFBGA180

Description

LBGA256

Symbol

Reset state

Table 184. LPC4350/30/20/10 and LPC43S50/S30/S20 pin descriptions …continued
LCD, Ethernet, USB0, and USB1 functions are not available on all parts.

ADC pins

RTC

RTCX2

B8

B7

B5

126

[8]

Crystal oscillator pins
XTAL1

D1

C1

B1

12

[8]

-

I

Input to the oscillator circuit and internal clock generator
circuits.

XTAL2

E1

D1

C1

13

[8]

-

O

Output from the oscillator amplifier.

Power and ground pins
USB0_VDDA
3V3_DRIVER

F3

E3

D1

16

-

-

Separate analog 3.3 V power supply for driver.

USB0
_VDDA3V3

G3

F3

D2

17

-

-

USB 3.3 V separate power supply voltage.

USB0_VSSA
_TERM

H3

G3

D3

19

-

-

Dedicated analog ground for clean reference for termination
resistors.

USB0_VSSA
_REF

G1

F1

F2

23

-

-

Dedicated clean analog ground for generation of reference
currents and voltages.

VDDA

B4

A6

B2

137

-

-

Analog power supply and ADC reference voltage.

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Chapter 16: LPC43xx/LPC43Sxx Pin configuration

Table 184. LPC4350/30/20/10 and LPC43S50/S30/S20 pin descriptions …continued
LCD, Ethernet, USB0, and USB1 functions are not available on all parts.
TFBGA100

LQFP144

Reset state

B10

B9

C5

127

-

VDDREG

F10,
F9,
L8,
L7

D8,
E8

E4,
E5,
F4

94,
131,
59,
25

VPP

E8

-

-

-

VDDIO

D7,
E12,
F7,
F8,
G10,
H10,
J6,
J7,
K7,
L9,
L10,
N7,
N13

H5, F10, 5,
H10, K5
36,
K8,
41,
G10
71,
77,
107,
111,
141

VDD

-

-

-

-

VSS

G9,
H7,
J10,
J11,
K8

F10, D7,
E6,
E7,
E9,
K6,
K9

-

VSSIO

VSSA

Type

TFBGA180

VBAT

Description

[1]

LBGA256

Symbol

-

RTC power supply: 3.3 V on this pin supplies power to the
RTC.

-

Main regulator power supply. Tie the VDDREG and VDDIO
pins to a common power supply to ensure the same ramp-up
time for both supply voltages.

[12]

-

-

OTP programming voltage.

[12]

-

-

I/O power supply. Tie the VDDREG and VDDIO pins to a
common power supply to ensure the same ramp-up time for
both supply voltages.

[13]

-

-

Ground.

-

-

Ground.

Power supply for main regulator, I/O, and OTP.
[14]

[13]

C4,
D13,
G6,
G7,
G8,
H8,
H9,
J8,
J9,
K9,
K10,
M13,
P7,
P13

C8,
D4,
D5,
G8,
J3,
J6

4,
40,
76,
109

B2

A3

C2

135

-

-

Analog ground.

B9

B8

-

-

-

-

n.c.

[14]

Not connected
-

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Chapter 16: LPC43xx/LPC43Sxx Pin configuration

[1]

N = neutral, input buffer disabled; no extra VDDIO current consumption if the input is driven midway between supplies; I = input; OL =
output driving LOW; OH = output driving HIGH; AI/O = analog input/output; IA = inactive; PU = pull-up enabled (weak pull-up resistor
pulls up pin to VDDIO; F = floating. Reset state reflects the pin state at reset without boot code operation.

[2]

5 V tolerant pad with 15 ns glitch filter (5 V tolerant if VDDIO present; if VDDIO not present, do not exceed 3.6 V); provides digital I/O
functions with TTL levels and hysteresis; normal drive strength.

[3]

5 V tolerant pad with 15 ns glitch filter(5 V tolerant if VDDIO present; if VDDIO not present, do not exceed 3.6 V); provides digital I/O
functions with TTL levels, and hysteresis; high drive strength.

[4]

5 V tolerant pad with 15 ns glitch filter(5 V tolerant if VDDIO present; if VDDIO not present, do not exceed 3.6 V); provides high-speed
digital I/O functions with TTL levels and hysteresis.

[5]

5 V tolerant pad providing digital I/O functions (with TTL levels and hysteresis) and analog input or output (5 V tolerant if VDDIO present;
if VDDIO not present, do not exceed 3.6 V). When configured as a ADC input or DAC output, the pin is not 5 V tolerant and the digital
section of the pad must be disabled by setting the pin to an input function and disabling the pull-up resistor through the pin’s SFSP
register.

[6]

5 V tolerant transparent analog pad.

[7]

For maximum load CL = 6.5 F and maximum resistance Rpd = 80 k, the VBUS signal takes about 2 s to fall from VBUS = 5 V to VBUS
= 0.2 V when it is no longer driven.

[8]

Transparent analog pad. Not 5 V tolerant.

[9]

Pad provides USB functions 5 V tolerant if VDDIO present; if VDDIO not present, do not exceed 3.6 V. It is designed in accordance with
the USB specification, revision 2.0 (Full-speed and Low-speed mode only).

[10] Open-drain 5 V tolerant digital I/O pad, compatible with I2C-bus Fast Mode Plus specification. This pad requires an external pull-up to
provide output functionality. When power is switched off, this pin connected to the I2C-bus is floating and does not disturb the I2C lines.
[11] 5 V tolerant pad with 20 ns glitch filter; provides digital I/O functions with open-drain output with weak pull-up resistor and hysteresis.
[12] On the TFBGA100 packages, VPP is internally connected to VDDIO.
[13] On the LQFP144 package, VSSIO and VSS are connected to a common ground plane.
[14] On the TFBGA100 package, VSS is internally connected to VSSIO.

16.2.2 LPC4370/LPC43S70 Pin description
Remark: This part contains the 12-bit high-speed ADCHS and two 10-bit ADCs (ADC0
and ADC1). Except for ADC0 channel 7, all ADC0 and ADC1 analog conversions inputs
are available separately on mixed digital/analog pins for a total of 16 ADC channels for
two 10-bit ADCs. The pins for the 12-bit ADCHS are dedicated analog-only pins.

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Chapter 16: LPC43xx/LPC43Sxx Pin configuration

Type

Description

[1]

Reset state

TFBGA100

Symbol

LBGA256

Table 185. LPC4370/LPC43S70 Pin description
LCD is not available on all parts.

Multiplexed digital pins
P0_0

P0_1

L3

M2

G2

G1

[2]

[2]

I; PU I/O

GPIO0[0] — General purpose digital input/output pin.

I/O

SSP1_MISO — Master In Slave Out for SSP1.

I

ENET_RXD1 — Ethernet receive data 1 (RMII/MII interface).

I/O

SGPIO0 — General purpose digital input/output pin.

-

R — Function reserved.

-

R — Function reserved.

I/O

I2S0_TX_WS — Transmit Word Select. It is driven by the master and
received by the slave. Corresponds to the signal WS in the I2S-bus
specification.

I/O

I2S1_TX_WS — Transmit Word Select. It is driven by the master and
received by the slave. Corresponds to the signal WS in the I2S-bus
specification.

I; PU I/O

GPIO0[1] — General purpose digital input/output pin.

I/O

SSP1_MOSI — Master Out Slave in for SSP1.

I

ENET_COL — Ethernet Collision detect (MII interface).

I/O

SGPIO1 — General purpose digital input/output pin.

-

R — Function reserved.

-

R — Function reserved.
ENET_TX_EN — Ethernet transmit enable (RMII/MII interface).

I/O
P1_0

P1_1

UM10503

User manual

P2

R2

H1

K2

[2]

[2]

I; PU I/O

I2S1_TX_SDA — I2S1 transmit data. It is driven by the transmitter and read
by the receiver. Corresponds to the signal SD in the I2S-bus specification.
GPIO0[4] — General purpose digital input/output pin.

I

CTIN_3 — SCT input 3. Capture input 1 of timer 1.

I/O

EMC_A5 — External memory address line 5.

-

R — Function reserved.

-

R — Function reserved.

I/O

SSP0_SSEL — Slave Select for SSP0.

I/O

SGPIO7 — General purpose digital input/output pin.

-

R — Function reserved.

I; PU I/O

GPIO0[8] — General purpose digital input/output pin. Boot pin (see
Table 22).

O

CTOUT_7 — SCT output 7. Match output 3 of timer 1.

I/O

EMC_A6 — External memory address line 6.

I/O

SGPIO8 — General purpose digital input/output pin.

-

R — Function reserved.

I/O

SSP0_MISO — Master In Slave Out for SSP0.

-

R — Function reserved.

-

R — Function reserved.

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Chapter 16: LPC43xx/LPC43Sxx Pin configuration

P1_2

P1_3

P1_4

P1_5

UM10503

User manual

P5

T3

R5

J1

J2

J4

[2]

[2]

[2]

[2]

Type

K1

Description

[1]

R3

Reset state

TFBGA100

Symbol

LBGA256

Table 185. LPC4370/LPC43S70 Pin description …continued
LCD is not available on all parts.

I; PU I/O

GPIO0[9] — General purpose digital input/output pin. Boot pin (see
Table 22).

O

CTOUT_6 — SCT output 6. Match output 2 of timer 1.

I/O

EMC_A7 — External memory address line 7.

I/O

SGPIO9 — General purpose digital input/output pin.

-

R — Function reserved.

I/O

SSP0_MOSI — Master Out Slave in for SSP0.

-

R — Function reserved.

-

R — Function reserved.

I; PU I/O

GPIO0[10] — General purpose digital input/output pin.

O

CTOUT_8 — SCT output 8. Match output 0 of timer 2.

I/O

SGPIO10 — General purpose digital input/output pin.

O

EMC_OE — LOW active Output Enable signal.

O

USB0_IND1 — USB0 port indicator LED control
output 1.

I/O

SSP1_MISO — Master In Slave Out for SSP1.

-

R — Function reserved.

O

SD_RST — SD/MMC reset signal for MMC4.4 card.

I; PU I/O

GPIO0[11] — General purpose digital input/output pin.

O

CTOUT_9 — SCT output 9. Match output 1 of timer 2.

I/O

SGPIO11 — General purpose digital input/output pin.

O

EMC_BLS0 — LOW active Byte Lane select signal 0.

O

USB0_IND0 — USB0 port indicator LED control output 0.

I/O

SSP1_MOSI — Master Out Slave in for SSP1.

-

R — Function reserved.

O

SD_VOLT1 — SD/MMC bus voltage select output 1.

I; PU I/O

GPIO1[8] — General purpose digital input/output pin.

O

CTOUT_10 — SCT output 10. Match output 2 of timer 2.

-

R — Function reserved.

O

EMC_CS0 — LOW active Chip Select 0 signal.

I

USB0_PWR_FAULT — Port power fault signal indicating overcurrent
condition; this signal monitors over-current on the USB bus (external circuitry
required to detect over-current condition).

I/O

SSP1_SSEL — Slave Select for SSP1.

I/O

SGPIO15 — General purpose digital input/output pin.

O

SD_POW — SD/MMC power monitor output.

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Chapter 16: LPC43xx/LPC43Sxx Pin configuration

P1_6

P1_7

T5

G4

[2]

[2]

Type

K4

Description

[1]

T4

Reset state

TFBGA100

Symbol

LBGA256

Table 185. LPC4370/LPC43S70 Pin description …continued
LCD is not available on all parts.

I; PU I/O

GPIO1[9] — General purpose digital input/output pin.

I

CTIN_5 — SCT input 5. Capture input 2 of timer 2.

-

R — Function reserved.

O

EMC_WE — LOW active Write Enable signal.

-

R — Function reserved.

-

R — Function reserved.

I/O

SGPIO14 — General purpose digital input/output pin.

I/O

SD_CMD — SD/MMC command signal.

I; PU I/O

GPIO1[0] — General purpose digital input/output pin.

I

U1_DSR — Data Set Ready input for UART1.

O

CTOUT_13 — SCT output 13. Match output 1 of timer 3.

I/O

EMC_D0 — External memory data line 0.

O

USB0_PPWR — VBUS drive signal (towards external charge pump or
power management unit); indicates that VBUS must be driven (active HIGH).
Add a pull-down resistor to disable the power switch at reset. This signal has
opposite polarity compared to the USB_PPWR used on other NXP LPC
parts.

P1_8

P1_9

R7

T7

H5

J5

[2]

[2]

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

I; PU I/O
O

U1_DTR — Data Terminal Ready output for UART1.

O

CTOUT_12 — SCT output 12. Match output 0 of
timer 3.

I/O

EMC_D1 — External memory data line 1.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

O

SD_VOLT0 — SD/MMC bus voltage select output 0.

I; PU I/O
O

UM10503

User manual

GPIO1[1] — General purpose digital input/output pin.

GPIO1[2] — General purpose digital input/output pin.
U1_RTS — Request to Send output for UART1.

O

CTOUT_11 — SCT output 11. Match output 3 of timer 2.

I/O

EMC_D2 — External memory data line 2.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

I/O

SD_DAT0 — SD/MMC data bus line 0.

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Chapter 16: LPC43xx/LPC43Sxx Pin configuration

P1_10

P1_11

P1_12

P1_13

UM10503

User manual

T9

R9

R10

J7

K7

H8

[2]

[2]

[2]

[2]

Type

H6

Description

[1]

R8

Reset state

TFBGA100

Symbol

LBGA256

Table 185. LPC4370/LPC43S70 Pin description …continued
LCD is not available on all parts.

I; PU I/O

GPIO1[3] — General purpose digital input/output pin.

I

U1_RI — Ring Indicator input for UART1.

O

CTOUT_14 — SCT output 14. Match output 2 of timer 3.

I/O

EMC_D3 — External memory data line 3.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

I/O

SD_DAT1 — SD/MMC data bus line 1.

I; PU I/O

GPIO1[4] — General purpose digital input/output pin.

I

U1_CTS — Clear to Send input for UART1.

O

CTOUT_15 — SCT output 15. Match output 3 of timer 3.

I/O

EMC_D4 — External memory data line 4.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

I/O

SD_DAT2 — SD/MMC data bus line 2.

I; PU I/O

GPIO1[5] — General purpose digital input/output pin.

I

U1_DCD — Data Carrier Detect input for UART1.

-

R — Function reserved.

I/O

EMC_D5 — External memory data line 5.

I

T0_CAP1 — Capture input 1 of timer 0.

-

R — Function reserved.

I/O

SGPIO8 — General purpose digital input/output pin.

I/O

SD_DAT3 — SD/MMC data bus line 3.

I; PU I/O

GPIO1[6] — General purpose digital input/output pin.

O

U1_TXD — Transmitter output for UART1.

-

R — Function reserved.

I/O

EMC_D6 — External memory data line 6.

I

T0_CAP0 — Capture input 0 of timer 0.

-

R — Function reserved.

I/O

SGPIO9 — General purpose digital input/output pin.

I

SD_CD — SD/MMC card detect input.

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Chapter 16: LPC43xx/LPC43Sxx Pin configuration

P1_14

P1_15

P1_16

P1_17

UM10503

User manual

T12

M7

M8

K8

H9

H10

[2]

[2]

[2]

[3]

Type

J8

Description

[1]

R11

Reset state

TFBGA100

Symbol

LBGA256

Table 185. LPC4370/LPC43S70 Pin description …continued
LCD is not available on all parts.

I; PU I/O

GPIO1[7] — General purpose digital input/output pin.

I

U1_RXD — Receiver input for UART1.

-

R — Function reserved.

I/O

EMC_D7 — External memory data line 7.

O

T0_MAT2 — Match output 2 of timer 0.

-

R — Function reserved.

I/O

SGPIO10 — General purpose digital input/output pin.

-

R — Function reserved.

I; PU I/O

GPIO0[2] — General purpose digital input/output pin.

O

U2_TXD — Transmitter output for USART2.

I/O

SGPIO2 — General purpose digital input/output pin.

I

ENET_RXD0 — Ethernet receive data 0 (RMII/MII interface).

O

T0_MAT1 — Match output 1 of timer 0.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

I; PU I/O

GPIO0[3] — General purpose digital input/output pin.

I

U2_RXD — Receiver input for USART2.

I/O

SGPIO3 — General purpose digital input/output pin.

I

ENET_CRS — Ethernet Carrier Sense (MII interface).

O

T0_MAT0 — Match output 0 of timer 0.

-

R — Function reserved.

-

R — Function reserved.

I

ENET_RX_DV — Ethernet Receive Data Valid (RMII/MII interface).

I; PU I/O

GPIO0[12] — General purpose digital input/output pin.

I/O

U2_UCLK — Serial clock input/output for USART2 in synchronous mode.

-

R — Function reserved.

I/O

ENET_MDIO — Ethernet MIIM data input and output.

I

T0_CAP3 — Capture input 3 of timer 0.

O

CAN1_TD — CAN1 transmitter output.

I/O

SGPIO11 — General purpose digital input/output pin.

-

R — Function reserved.

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Chapter 16: LPC43xx/LPC43Sxx Pin configuration

P1_18

P1_19

P1_20

P2_0

M11

M10

T16

K9

K10

G10

[2]

[2]

[2]

[2]

Type

J10

Description

[1]

N12

Reset state

TFBGA100

Symbol

LBGA256

Table 185. LPC4370/LPC43S70 Pin description …continued
LCD is not available on all parts.

I; PU I/O

GPIO0[13] — General purpose digital input/output pin.

I/O

U2_DIR — RS-485/EIA-485 output enable/direction control for USART2.

-

R — Function reserved.

O

ENET_TXD0 — Ethernet transmit data 0 (RMII/MII interface).

O

T0_MAT3 — Match output 3 of timer 0.

I

CAN1_RD — CAN1 receiver input.

I/O

SGPIO12 — General purpose digital input/output pin.

-

R — Function reserved.

I; PU I

ENET_TX_CLK (ENET_REF_CLK) — Ethernet Transmit Clock (MII
interface) or Ethernet Reference Clock (RMII interface).

I/O

SSP1_SCK — Serial clock for SSP1.

-

R — Function reserved.

-

R — Function reserved.

O

CLKOUT — Clock output pin.

-

R — Function reserved.

O

I2S0_RX_MCLK — I2S receive master clock.

I/O

I2S1_TX_SCK — Transmit Clock. It is driven by the master and received by
the slave. Corresponds to the signal SCK in the I2S-bus specification.

I; PU I/O

GPIO0[15] — General purpose digital input/output pin.

I/O

SSP1_SSEL — Slave Select for SSP1.

-

R — Function reserved.

O

ENET_TXD1 — Ethernet transmit data 1 (RMII/MII interface).

I

T0_CAP2 — Capture input 2 of timer 0.

-

R — Function reserved.

I/O

SGPIO13 — General purpose digital input/output pin.

-

R — Function reserved.

I; PU I/O

SGPIO4 — General purpose digital input/output pin.

O

U0_TXD — Transmitter output for USART0.

I/O

EMC_A13 — External memory address line 13.

O

USB0_PPWR — VBUS drive signal (towards external charge pump or
power management unit); indicates that VBUS must be driven (active HIGH).
Add a pull-down resistor to disable the power switch at reset. This signal has
opposite polarity compared to the USB_PPWR used on other NXP LPC
parts.

UM10503

User manual

I/O

GPIO5[0] — General purpose digital input/output pin.

-

R — Function reserved.

I

T3_CAP0 — Capture input 0 of timer 3.

O

ENET_MDC — Ethernet MIIM clock.

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Chapter 16: LPC43xx/LPC43Sxx Pin configuration

P2_1

P2_2

P2_3

P2_4

UM10503

User manual

M15

J12

K11

F5

D8

D9

[2]

[2]

[3]

[3]

Type

G7

Description

[1]

N15

Reset state

TFBGA100

Symbol

LBGA256

Table 185. LPC4370/LPC43S70 Pin description …continued
LCD is not available on all parts.

I; PU I/O

SGPIO5 — General purpose digital input/output pin.

I

U0_RXD — Receiver input for USART0.

I/O

EMC_A12 — External memory address line 12.

I

USB0_PWR_FAULT — Port power fault signal indicating overcurrent
condition; this signal monitors over-current on the USB bus (external circuitry
required to detect over-current condition).

I/O

GPIO5[1] — General purpose digital input/output pin.

-

R — Function reserved.

I

T3_CAP1 — Capture input 1 of timer 3.

-

R — Function reserved.

I; PU I/O

SGPIO6 — General purpose digital input/output pin.

I/O

U0_UCLK — Serial clock input/output for USART0 in synchronous mode.

I/O

EMC_A11 — External memory address line 11.

O

USB0_IND1 — USB0 port indicator LED control output 1.

I/O

GPIO5[2] — General purpose digital input/output pin.

I

CTIN_6 — SCT input 6. Capture input 1 of timer 3.

I

T3_CAP2 — Capture input 2 of timer 3.

-

R — Function reserved.

I; PU I/O

SGPIO12 — General purpose digital input/output pin.

I/O

I2C1_SDA — I2C1 data input/output (this pin does not use a specialized I2C
pad).

O

U3_TXD — Transmitter output for USART3.

I

CTIN_1 — SCT input 1. Capture input 1 of timer 0. Capture input 1 of timer
2.

I/O

GPIO5[3] — General purpose digital input/output pin.

-

R — Function reserved.

O

T3_MAT0 — Match output 0 of timer 3.

I

USB0_PWR_EN — VBUS drive signal (towards external charge pump or
power management unit); indicates that Vbus must be driven (active HIGH).

I; PU I/O

SGPIO13 — General purpose digital input/output pin.

I/O

I2C1_SCL — I2C1 clock input/output (this pin does not use a specialized I2C
pad).

I

U3_RXD — Receiver input for USART3.

I

CTIN_0 — SCT input 0. Capture input 0 of timer 0, 1, 2, 3.

I/O

GPIO5[4] — General purpose digital input/output pin.

-

R — Function reserved.

O

T3_MAT1 — Match output 1 of timer 3.

I

USB0_PWR_FAULT — Port power fault signal indicating overcurrent
condition; this signal monitors over-current on the USB bus (external circuitry
required to detect over-current condition).

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Chapter 16: LPC43xx/LPC43Sxx Pin configuration

P2_5

[3]

Type

D10

Description

[1]

K14

Reset state

TFBGA100

Symbol

LBGA256

Table 185. LPC4370/LPC43S70 Pin description …continued
LCD is not available on all parts.

I; PU I/O

SGPIO14 — General purpose digital input/output pin.

I

CTIN_2 — SCT input 2. Capture input 2 of timer 0.

I

USB1_VBUS — Monitors the presence of USB1 bus power.
Note: This signal must be HIGH for USB reset to occur.

P2_6

P2_7

P2_8

UM10503

User manual

K16

H14

J16

G9

C10

C6

[2]

[2]

[2]

I

ADCTRIG1 — ADC trigger input 1.

I/O

GPIO5[5] — General purpose digital input/output pin.

-

R — Function reserved.

O

T3_MAT2 — Match output 2 of timer 3.

O

USB0_IND0 — USB0 port indicator LED control output 0.

I; PU I/O

SGPIO7 — General purpose digital input/output pin.

I/O

U0_DIR — RS-485/EIA-485 output enable/direction control for USART0.

I/O

EMC_A10 — External memory address line 10.

O

USB0_IND0 — USB0 port indicator LED control
output 0.

I/O

GPIO5[6] — General purpose digital input/output pin.

I

CTIN_7 — SCT input 7.

I

T3_CAP3 — Capture input 3 of timer 3.

-

R — Function reserved.

I; PU I/O

GPIO0[7] — General purpose digital input/output pin. If this pin is pulled
LOW at reset, the part enters ISP mode using USART0.

O

CTOUT_1 — SCT output 1. Match output 1 of timer 0.

I/O

U3_UCLK — Serial clock input/output for USART3 in synchronous mode.

I/O

EMC_A9 — External memory address line 9.

-

R — Function reserved.

-

R — Function reserved.

O

T3_MAT3 — Match output 3 of timer 3.

-

R — Function reserved.

I; PU I/O

SGPIO15 — General purpose digital input/output pin. Boot pin (see
Table 22).

O

CTOUT_0 — SCT output 0. Match output 0 of timer 0.

I/O

U3_DIR — RS-485/EIA-485 output enable/direction control for USART3.

I/O

EMC_A8 — External memory address line 8.

I/O

GPIO5[7] — General purpose digital input/output pin.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

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Chapter 16: LPC43xx/LPC43Sxx Pin configuration

P2_9

P2_10

G16

E8

[2]

[2]

Type

B10

Description

[1]

H16

Reset state

TFBGA100

Symbol

LBGA256

Table 185. LPC4370/LPC43S70 Pin description …continued
LCD is not available on all parts.

I; PU I/O
O

CTOUT_3 — SCT output 3. Match output 3 of timer 0.

I/O

U3_BAUD — Baud pin for USART3.

I/O

EMC_A0 — External memory address line 0.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

I; PU I/O

P2_12

UM10503

User manual

F16

E15

A9

B9

[2]

[2]

GPIO0[14] — General purpose digital input/output pin.

O

CTOUT_2 — SCT output 2. Match output 2 of timer 0.

O

U2_TXD — Transmitter output for USART2.

I/O

EMC_A1 — External memory address line 1.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

P2_11

GPIO1[10] — General purpose digital input/output pin. Boot pin (see
Table 22).

I; PU I/O

R — Function reserved.
GPIO1[11] — General purpose digital input/output pin.

O

CTOUT_5 — SCT output 5. Match output 1 of timer 1.

I

U2_RXD — Receiver input for USART2.

I/O

EMC_A2 — External memory address line 2.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

I; PU I/O

GPIO1[12] — General purpose digital input/output pin.

O

CTOUT_4 — SCT output 4. Match output 0 of timer 1.

-

R — Function reserved.

I/O

EMC_A3 — External memory address line 3.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

I/O

U2_UCLK — Serial clock input/output for USART2 in synchronous mode.

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NXP Semiconductors

Chapter 16: LPC43xx/LPC43Sxx Pin configuration

P2_13

P3_0

P3_1

P3_2

UM10503

User manual

F13

G11

F11

A8

F7

G6

[2]

[2]

[2]

[2]

Type

A10

Description

[1]

C16

Reset state

TFBGA100

Symbol

LBGA256

Table 185. LPC4370/LPC43S70 Pin description …continued
LCD is not available on all parts.

I; PU I/O

GPIO1[13] — General purpose digital input/output pin.

I

CTIN_4 — SCT input 4. Capture input 2 of timer 1.

-

R — Function reserved.

I/O

EMC_A4 — External memory address line 4.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

I/O

U2_DIR — RS-485/EIA-485 output enable/direction control for USART2.

I; PU I/O

I2S0_RX_SCK — I2S receive clock. It is driven by the master and received
by the slave. Corresponds to the signal SCK in the I2S-bus specification.

O

I2S0_RX_MCLK — I2S receive master clock.

I/O

I2S0_TX_SCK — Transmit Clock. It is driven by the master and received by
the slave. Corresponds to the signal SCK in the I2S-bus specification.

O

I2S0_TX_MCLK — I2S transmit master clock.

I/O

SSP0_SCK — Serial clock for SSP0.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

I; PU I/O

I2S0_TX_WS — Transmit Word Select. It is driven by the master and
received by the slave. Corresponds to the signal WS in the I2S-bus
specification.

I/O

I2S0_RX_WS — Receive Word Select. It is driven by the master and
received by the slave. Corresponds to the signal WS in the I2S-bus
specification.

I

CAN0_RD — CAN receiver input.

O

USB1_IND1 — USB1 Port indicator LED control output 1.

I/O

GPIO5[8] — General purpose digital input/output pin.

-

R — Function reserved.

O

LCD_VD15 — LCD data.

-

R — Function reserved.

I; PU I/O

I2S0_TX_SDA — I2S transmit data. It is driven by the transmitter and read
by the receiver. Corresponds to the signal SD in the I2S-bus specification.

I/O

I2S0_RX_SDA — I2S Receive data. It is driven by the transmitter and read
by the receiver. Corresponds to the signal SD in the I2S-bus specification.

O

CAN0_TD — CAN transmitter output.

O

USB1_IND0 — USB1 Port indicator LED control output 0.

I/O

GPIO5[9] — General purpose digital input/output pin.

-

R — Function reserved.

O

LCD_VD14 — LCD data.

-

R — Function reserved.

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Chapter 16: LPC43xx/LPC43Sxx Pin configuration

P3_3

P3_4

P3_5

P3_6

UM10503

User manual

A15

C12

B13

B8

B7

C7

[4]

[2]

[2]

[2]

Type

A7

Description

[1]

B14

Reset state

TFBGA100

Symbol

LBGA256

Table 185. LPC4370/LPC43S70 Pin description …continued
LCD is not available on all parts.

I; PU -

R — Function reserved.

I/O

SPI_SCK — Serial clock for SPI.

I/O

SSP0_SCK — Serial clock for SSP0.

O

SPIFI_SCK — Serial clock for SPIFI.

O

CGU_OUT1 — CGU spare clock output 1.

-

R — Function reserved.

O

I2S0_TX_MCLK — I2S transmit master clock.

I/O

I2S1_TX_SCK — Transmit Clock. It is driven by the master and received by
the slave. Corresponds to the signal SCK in the I2S-bus specification.

I; PU I/O

GPIO1[14] — General purpose digital input/output pin.

-

R — Function reserved.

-

R — Function reserved.

I/O

SPIFI_SIO3 — I/O lane 3 for SPIFI.

O

U1_TXD — Transmitter output for UART 1.

I/O

I2S0_TX_WS — Transmit Word Select. It is driven by the master and
received by the slave. Corresponds to the signal WS in the I2S-bus
specification.

I/O

I2S1_RX_SDA — I2S1 Receive data. It is driven by the transmitter and read
by the receiver. Corresponds to the signal SD in the I2S-bus specification.

O

LCD_VD13 — LCD data.

I; PU I/O

GPIO1[15] — General purpose digital input/output pin.

-

R — Function reserved.

-

R — Function reserved.

I/O

SPIFI_SIO2 — I/O lane 2 for SPIFI.

I

U1_RXD — Receiver input for UART 1.

I/O

I2S0_TX_SDA — I2S transmit data. It is driven by the transmitter and read
by the receiver. Corresponds to the signal SD in the I2S-bus specification.

I/O

I2S1_RX_WS — Receive Word Select. It is driven by the master and
received by the slave. Corresponds to the signal WS in the I2S-bus
specification.

O

LCD_VD12 — LCD data.

I; PU I/O

GPIO0[6] — General purpose digital input/output pin.

I/O

SPI_MISO — Master In Slave Out for SPI.

I/O

SSP0_SSEL — Slave Select for SSP0.

I/O

SPIFI_MISO — Input 1 in SPIFI quad mode; SPIFI output IO1.

-

R — Function reserved.

I/O

SSP0_MISO — Master In Slave Out for SSP0.

-

R — Function reserved.

-

R — Function reserved.

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Chapter 16: LPC43xx/LPC43Sxx Pin configuration

P3_7

P3_8

P4_0

P4_1

C10

D5

A1

E7

-

-

[2]

[2]

[2]

[5]
[13]

UM10503

User manual

Type

D7

Description

[1]

C11

Reset state

TFBGA100

Symbol

LBGA256

Table 185. LPC4370/LPC43S70 Pin description …continued
LCD is not available on all parts.

I; PU -

R — Function reserved.

I/O

SPI_MOSI — Master Out Slave In for SPI.

I/O

SSP0_MISO — Master In Slave Out for SSP0.

I/O

SPIFI_MOSI — Input I0 in SPIFI quad mode; SPIFI output IO0.

I/O

GPIO5[10] — General purpose digital input/output pin.

I/O

SSP0_MOSI — Master Out Slave in for SSP0.

-

R — Function reserved.

-

R — Function reserved.

I; PU -

R — Function reserved.

I

SPI_SSEL — Slave Select for SPI. Note that this pin in an input pin only.
The SPI in master mode cannot drive the CS input on the slave. Any GPIO
pin can be used for SPI chip select in master mode.

I/O

SSP0_MOSI — Master Out Slave in for SSP0.

I/O

SPIFI_CS — SPIFI serial flash chip select.

I/O

GPIO5[11] — General purpose digital input/output pin.

I/O

SSP0_SSEL — Slave Select for SSP0.

-

R — Function reserved.

-

R — Function reserved.

I; PU I/O

GPIO2[0] — General purpose digital input/output pin.

O

MCOA0 — Motor control PWM channel 0, output A.

I

NMI — External interrupt input to NMI.

-

R — Function reserved.

-

R — Function reserved.

O

LCD_VD13 — LCD data.

I/O

U3_UCLK — Serial clock input/output for USART3 in synchronous mode.

-

R — Function reserved.

I; PU I/O

GPIO2[1] — General purpose digital input/output pin.

O

CTOUT_1 — SCT output 1. Match output 1 of timer 0.

O

LCD_VD0 — LCD data.

-

R — Function reserved.

-

R — Function reserved.

O

LCD_VD19 — LCD data.

O

U3_TXD — Transmitter output for USART3.

I

ENET_COL — Ethernet Collision detect (MII interface).

AI

ADC0_1 — ADC0, input channel 1. Configure the pin as GPIO input and use
the ADC function select register in the SCU to select the ADC.

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Chapter 16: LPC43xx/LPC43Sxx Pin configuration

P4_2

P4_3

C2

-

[2]

[5]
[13]

P4_4

P4_5

UM10503

User manual

B1

D2

-

-

[5]

[2]

Type

-

Description

[1]

D3

Reset state

TFBGA100

Symbol

LBGA256

Table 185. LPC4370/LPC43S70 Pin description …continued
LCD is not available on all parts.

I; PU I/O

GPIO2[2] — General purpose digital input/output pin.

O

CTOUT_0 — SCT output 0. Match output 0 of timer 0.

O

LCD_VD3 — LCD data.

-

R — Function reserved.

-

R — Function reserved.

O

LCD_VD12 — LCD data.

I

U3_RXD — Receiver input for USART3.

I/O

SGPIO8 — General purpose digital input/output pin.

I; PU I/O

GPIO2[3] — General purpose digital input/output pin.

O

CTOUT_3 — SCT output 3. Match output 3 of timer 0.

O

LCD_VD2 — LCD data.

-

R — Function reserved.

-

R — Function reserved.

O

LCD_VD21 — LCD data.

I/O

U3_BAUD — Baud pin for USART3.

I/O

SGPIO9 — General purpose digital input/output pin.

AI

ADC0_0 — ADC0, input channel 0. Configure the pin as GPIO input and use
the ADC function select register in the SCU to select the ADC.

I; PU I/O

GPIO2[4] — General purpose digital input/output pin.

O

CTOUT_2 — SCT output 2. Match output 2 of timer 0.

O

LCD_VD1 — LCD data.

-

R — Function reserved.

-

R — Function reserved.

O

LCD_VD20 — LCD data.

I/O

U3_DIR — RS-485/EIA-485 output enable/direction control for USART3.

I/O

SGPIO10 — General purpose digital input/output pin.

O

DAC — DAC output. Configure the pin as GPIO input and use the analog
function select register in the SCU to select the DAC.

I; PU I/O

GPIO2[5] — General purpose digital input/output pin.

O

CTOUT_5 — SCT output 5. Match output 1 of timer 1.

O

LCD_FP — Frame pulse (STN). Vertical synchronization pulse (TFT).

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

I/O

SGPIO11 — General purpose digital input/output pin.

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NXP Semiconductors

Chapter 16: LPC43xx/LPC43Sxx Pin configuration

P4_6

P4_7

P4_8

P4_9

UM10503

User manual

H4

E2

L2

-

-

-

[2]

[2]

[2]

[2]

Type

-

Description

[1]

C1

Reset state

TFBGA100

Symbol

LBGA256

Table 185. LPC4370/LPC43S70 Pin description …continued
LCD is not available on all parts.

I; PU I/O

O;
PU

GPIO2[6] — General purpose digital input/output pin.

O

CTOUT_4 — SCT output 4. Match output 0 of timer 1.

O

LCD_ENAB/LCDM — STN AC bias drive or TFT data enable input.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

I/O

SGPIO12 — General purpose digital input/output pin.

O

LCD_DCLK — LCD panel clock.

I

GP_CLKIN — General purpose clock input to the CGU.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

I/O

I2S1_TX_SCK — Transmit Clock. It is driven by the master and received by
the slave. Corresponds to the signal SCK in the I2S-bus specification.

I/O

I2S0_TX_SCK — Transmit Clock. It is driven by the master and received by
the slave. Corresponds to the signal SCK in the I2S-bus specification.

I; PU -

R — Function reserved.

I

CTIN_5 — SCT input 5. Capture input 2 of timer 2.

O

LCD_VD9 — LCD data.

-

R — Function reserved.

I/O

GPIO5[12] — General purpose digital input/output pin.

O

LCD_VD22 — LCD data.

O

CAN1_TD — CAN1 transmitter output.

I/O

SGPIO13 — General purpose digital input/output pin.

I; PU -

R — Function reserved.

I

CTIN_6 — SCT input 6. Capture input 1 of timer 3.

O

LCD_VD11 — LCD data.

-

R — Function reserved.

I/O

GPIO5[13] — General purpose digital input/output pin.

O

LCD_VD15 — LCD data.

I

CAN1_RD — CAN1 receiver input.

I/O

SGPIO14 — General purpose digital input/output pin.

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Rev. 2.4 — 22 August 2018

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NXP Semiconductors

Chapter 16: LPC43xx/LPC43Sxx Pin configuration

P4_10

P5_0

P5_1

N3

P3

-

-

[2]

[2]

[2]

Type

-

Description

[1]

M3

Reset state

TFBGA100

Symbol

LBGA256

Table 185. LPC4370/LPC43S70 Pin description …continued
LCD is not available on all parts.

I; PU -

CTIN_2 — SCT input 2. Capture input 2 of timer 0.

O

LCD_VD10 — LCD data.

-

R — Function reserved.

I/O

GPIO5[14] — General purpose digital input/output pin.

O

LCD_VD14 — LCD data.

-

R — Function reserved.

I/O

SGPIO15 — General purpose digital input/output pin.

I; PU I/O

GPIO2[9] — General purpose digital input/output pin.

O

MCOB2 — Motor control PWM channel 2, output B.

I/O

EMC_D12 — External memory data line 12.

-

R — Function reserved.

I

U1_DSR — Data Set Ready input for UART 1.

I

T1_CAP0 — Capture input 0 of timer 1.

-

R — Function reserved.

-

R — Function reserved.

I; PU I/O

UM10503

User manual

R4

-

[2]

GPIO2[10] — General purpose digital input/output pin.

I

MCI2 — Motor control PWM channel 2, input.

I/O

EMC_D13 — External memory data line 13.

-

R — Function reserved.

O

U1_DTR — Data Terminal Ready output for UART 1. Can also be configured
to be an RS-485/EIA-485 output enable signal for UART 1.

I

T1_CAP1 — Capture input 1 of timer 1.

-

R — Function reserved.

P5_2

R — Function reserved.

I

I; PU I/O

R — Function reserved.
GPIO2[11] — General purpose digital input/output pin.

I

MCI1 — Motor control PWM channel 1, input.

I/O

EMC_D14 — External memory data line 14.

-

R — Function reserved.

O

U1_RTS — Request to Send output for UART 1. Can also be configured to
be an RS-485/EIA-485 output enable signal for UART 1.

I

T1_CAP2 — Capture input 2 of timer 1.

-

R — Function reserved.

-

R — Function reserved.

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Rev. 2.4 — 22 August 2018

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Chapter 16: LPC43xx/LPC43Sxx Pin configuration

P5_3

P5_4

P5_5

P5_6

UM10503

User manual

P9

P10

T13

-

-

-

[2]

[2]

[2]

[2]

Type

-

Description

[1]

T8

Reset state

TFBGA100

Symbol

LBGA256

Table 185. LPC4370/LPC43S70 Pin description …continued
LCD is not available on all parts.

I; PU I/O

GPIO2[12] — General purpose digital input/output pin.

I

MCI0 — Motor control PWM channel 0, input.

I/O

EMC_D15 — External memory data line 15.

-

R — Function reserved.

I

U1_RI — Ring Indicator input for UART 1.

I

T1_CAP3 — Capture input 3 of timer 1.

-

R — Function reserved.

-

R — Function reserved.

I; PU I/O

GPIO2[13] — General purpose digital input/output pin.

O

MCOB0 — Motor control PWM channel 0, output B.

I/O

EMC_D8 — External memory data line 8.

-

R — Function reserved.

I

U1_CTS — Clear to Send input for UART 1.

O

T1_MAT0 — Match output 0 of timer 1.

-

R — Function reserved.

-

R — Function reserved.

I; PU I/O

GPIO2[14] — General purpose digital input/output pin.

O

MCOA1 — Motor control PWM channel 1, output A.

I/O

EMC_D9 — External memory data line 9.

-

R — Function reserved.

I

U1_DCD — Data Carrier Detect input for UART 1.

O

T1_MAT1 — Match output 1 of timer 1.

-

R — Function reserved.

-

R — Function reserved.

I; PU I/O

GPIO2[15] — General purpose digital input/output pin.

O

MCOB1 — Motor control PWM channel 1, output B.

I/O

EMC_D10 — External memory data line 10.

-

R — Function reserved.

O

U1_TXD — Transmitter output for UART 1.

O

T1_MAT2 — Match output 2 of timer 1.

-

R — Function reserved.

-

R — Function reserved.

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Rev. 2.4 — 22 August 2018

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317 of 1444

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NXP Semiconductors

Chapter 16: LPC43xx/LPC43Sxx Pin configuration

P5_7

P6_0

P6_1

P6_2

UM10503

User manual

M12

R15

L13

H7

G5

J9

[2]

[2]

[2]

[2]

Type

-

Description

[1]

R12

Reset state

TFBGA100

Symbol

LBGA256

Table 185. LPC4370/LPC43S70 Pin description …continued
LCD is not available on all parts.

I; PU I/O

GPIO2[7] — General purpose digital input/output pin.

O

MCOA2 — Motor control PWM channel 2, output A.

I/O

EMC_D11 — External memory data line 11.

-

R — Function reserved.

I

U1_RXD — Receiver input for UART 1.

O

T1_MAT3 — Match output 3 of timer 1.

-

R — Function reserved.

-

R — Function reserved.

I; PU -

R — Function reserved.

O

I2S0_RX_MCLK — I2S receive master clock.

-

R — Function reserved.

-

R — Function reserved.

I/O

I2S0_RX_SCK — Receive Clock. It is driven by the master and received by
the slave. Corresponds to the signal SCK in the I2S-bus specification.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

I; PU I/O

GPIO3[0] — General purpose digital input/output pin.

O

EMC_DYCS1 — SDRAM chip select 1.

I/O

U0_UCLK — Serial clock input/output for USART0 in synchronous mode.

I/O

I2S0_RX_WS — Receive Word Select. It is driven by the master and
received by the slave. Corresponds to the signal WS in the I2S-bus
specification.

-

R — Function reserved.

I

T2_CAP0 — Capture input 0 of timer 2.

-

R — Function reserved.

-

R — Function reserved.

I; PU I/O

GPIO3[1] — General purpose digital input/output pin.

O

EMC_CKEOUT1 — SDRAM clock enable 1.

I/O

U0_DIR — RS-485/EIA-485 output enable/direction control for USART0.

I/O

I2S0_RX_SDA — I2S Receive data. It is driven by the transmitter and read
by the receiver. Corresponds to the signal SD in the I2S-bus specification.

-

R — Function reserved.

I

T2_CAP1 — Capture input 1 of timer 2.

-

R — Function reserved.

-

R — Function reserved.

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Chapter 16: LPC43xx/LPC43Sxx Pin configuration

P6_3

P6_4

P6_5

P6_6

UM10503

User manual

R16

P16

L14

F6

F9

-

[2]

[2]

[2]

[2]

Type

-

Description

[1]

P15

Reset state

TFBGA100

Symbol

LBGA256

Table 185. LPC4370/LPC43S70 Pin description …continued
LCD is not available on all parts.

I; PU I/O

GPIO3[2] — General purpose digital input/output pin.

I

USB0_PWR_EN — VBUS drive signal (towards external charge pump or
power management unit); indicates that the VBUS signal must be driven
(active HIGH).

I/O

SGPIO4 — General purpose digital input/output pin.

O

EMC_CS1 — LOW active Chip Select 1 signal.

-

R — Function reserved.

I

T2_CAP2 — Capture input 2 of timer 2.

-

R — Function reserved.

-

R — Function reserved.

I; PU I/O

GPIO3[3] — General purpose digital input/output pin.

I

CTIN_6 — SCT input 6. Capture input 1 of timer 3.

O

U0_TXD — Transmitter output for USART0.

O

EMC_CAS — LOW active SDRAM Column Address Strobe.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

I; PU I/O

GPIO3[4] — General purpose digital input/output pin.

O

CTOUT_6 — SCT output 6. Match output 2 of timer 1.

I

U0_RXD — Receiver input for USART0.

O

EMC_RAS — LOW active SDRAM Row Address Strobe.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

I; PU I/O

GPIO0[5] — General purpose digital input/output pin.

O

EMC_BLS1 — LOW active Byte Lane select signal 1.

I/O

SGPIO5 — General purpose digital input/output pin.

I

USB0_PWR_FAULT — Port power fault signal indicating overcurrent
condition; this signal monitors over-current on the USB bus (external circuitry
required to detect over-current condition).

-

R — Function reserved.

I

T2_CAP3 — Capture input 3 of timer 2.

-

R — Function reserved.

-

R — Function reserved.

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Chapter 16: LPC43xx/LPC43Sxx Pin configuration

P6_7

P6_8

P6_9

P6_10

UM10503

User manual

H13

J15

H15

-

F8

-

[2]

[2]

[2]

[2]

Type

-

Description

[1]

J13

Reset state

TFBGA100

Symbol

LBGA256

Table 185. LPC4370/LPC43S70 Pin description …continued
LCD is not available on all parts.

I; PU -

R — Function reserved.

I/O

EMC_A15 — External memory address line 15.

I/O

SGPIO6 — General purpose digital input/output pin.

O

USB0_IND1 — USB0 port indicator LED control output 1.

I/O

GPIO5[15] — General purpose digital input/output pin.

O

T2_MAT0 — Match output 0 of timer 2.

-

R — Function reserved.

-

R — Function reserved.

I; PU -

R — Function reserved.

I/O

EMC_A14 — External memory address line 14.

I/O

SGPIO7 — General purpose digital input/output pin.

O

USB0_IND0 — USB0 port indicator LED control output 0.

I/O

GPIO5[16] — General purpose digital input/output pin.

O

T2_MAT1 — Match output 1 of timer 2.

-

R — Function reserved.

-

R — Function reserved.

I; PU I/O

GPIO3[5] — General purpose digital input/output pin.

-

R — Function reserved.

-

R — Function reserved.

O

EMC_DYCS0 — SDRAM chip select 0.

-

R — Function reserved.

O

T2_MAT2 — Match output 2 of timer 2.

-

R — Function reserved.

-

R — Function reserved.

I; PU I/O

GPIO3[6] — General purpose digital input/output pin.

O

MCABORT — Motor control PWM, LOW-active fast abort.

-

R — Function reserved.

O

EMC_DQMOUT1 — Data mask 1 used with SDRAM and static devices.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

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NXP Semiconductors

Chapter 16: LPC43xx/LPC43Sxx Pin configuration

P6_11

P6_12

P7_0

P7_1

UM10503

User manual

G15

B16

C14

-

-

-

[2]

[2]

[2]

[2]

Type

C9

Description

[1]

H12

Reset state

TFBGA100

Symbol

LBGA256

Table 185. LPC4370/LPC43S70 Pin description …continued
LCD is not available on all parts.

I; PU I/O

GPIO3[7] — General purpose digital input/output pin.

-

R — Function reserved.

-

R — Function reserved.

O

EMC_CKEOUT0 — SDRAM clock enable 0.

-

R — Function reserved.

O

T2_MAT3 — Match output 3 of timer 2.

-

R — Function reserved.

-

R — Function reserved.

I; PU I/O

GPIO2[8] — General purpose digital input/output pin.

O

CTOUT_7 — SCT output 7. Match output 3 of timer 1.

-

R — Function reserved.

O

EMC_DQMOUT0 — Data mask 0 used with SDRAM and static devices.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

I; PU I/O

GPIO3[8] — General purpose digital input/output pin.

O

CTOUT_14 — SCT output 14. Match output 2 of timer 3.

-

R — Function reserved.

O

LCD_LE — Line end signal.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

I/O

SGPIO4 — General purpose digital input/output pin.

I; PU I/O

GPIO3[9] — General purpose digital input/output pin.

O

CTOUT_15 — SCT output 15. Match output 3 of timer 3.

I/O

I2S0_TX_WS — Transmit Word Select. It is driven by the master and
received by the slave. Corresponds to the signal WS in the I2S-bus
specification.

O

LCD_VD19 — LCD data.

O

LCD_VD7 — LCD data.

-

R — Function reserved.

O

U2_TXD — Transmitter output for USART2.

I/O

SGPIO5 — General purpose digital input/output pin.

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Chapter 16: LPC43xx/LPC43Sxx Pin configuration

P7_2

P7_3

P7_4

P7_5

UM10503

User manual

C13

C8

A7

-

-

-

[2]

[2]

[5]

[5]

Type

-

Description

[1]

A16

Reset state

TFBGA100

Symbol

LBGA256

Table 185. LPC4370/LPC43S70 Pin description …continued
LCD is not available on all parts.

I; PU I/O

GPIO3[10] — General purpose digital input/output pin.

I

CTIN_4 — SCT input 4. Capture input 2 of timer 1.

I/O

I2S0_TX_SDA — I2S transmit data. It is driven by the transmitter and read
by the receiver. Corresponds to the signal SD in the I2S-bus specification.

O

LCD_VD18 — LCD data.

O

LCD_VD6 — LCD data.

-

R — Function reserved.

I

U2_RXD — Receiver input for USART2.

I/O

SGPIO6 — General purpose digital input/output pin.

I; PU I/O

GPIO3[11] — General purpose digital input/output pin.

I

CTIN_3 — SCT input 3. Capture input 1 of timer 1.

-

R — Function reserved.

O

LCD_VD17 — LCD data.

O

LCD_VD5 — LCD data.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

I; PU I/O

GPIO3[12] — General purpose digital input/output pin.

O

CTOUT_13 — SCT output 13. Match output 1 of timer 3.

-

R — Function reserved.

O

LCD_VD16 — LCD data.

O

LCD_VD4 — LCD data.

O

TRACEDATA[0] — Trace data, bit 0.

-

R — Function reserved.

-

R — Function reserved.

AI

ADC0_4 — ADC0, input channel 4. Configure the pin as GPIO input and use
the ADC function select register in the SCU to select the ADC.

I; PU I/O

GPIO3[13] — General purpose digital input/output pin.

O

CTOUT_12 — SCT output 12. Match output 0 of timer 3.

-

R — Function reserved.

O

LCD_VD8 — LCD data.

O

LCD_VD23 — LCD data.

O

TRACEDATA[1] — Trace data, bit 1.

-

R — Function reserved.

-

R — Function reserved.

AI

ADC0_3 — ADC0, input channel 3. Configure the pin as GPIO input and use
the ADC function select register in the SCU to select the ADC.

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NXP Semiconductors

Chapter 16: LPC43xx/LPC43Sxx Pin configuration

P7_6

[2]

Type

-

Description

[1]

C7

Reset state

TFBGA100

Symbol

LBGA256

Table 185. LPC4370/LPC43S70 Pin description …continued
LCD is not available on all parts.

I; PU I/O

CTOUT_11 — SCT output 1. Match output 3 of timer 2.

-

R — Function reserved.

O

LCD_LP — Line synchronization pulse (STN). Horizontal synchronization
pulse (TFT).

-

R — Function reserved.

O

TRACEDATA[2] — Trace data, bit 2.

-

R — Function reserved.

P7_7

B6

-

[5]
[13]

P8_0

E5

-

[3]
[13]

P8_1

UM10503

User manual

H5

-

[3]

GPIO3[14] — General purpose digital input/output pin.

O

I; PU I/O

R — Function reserved.
GPIO3[15] — General purpose digital input/output pin.

O

CTOUT_8 — SCT output 8. Match output 0 of timer 2.

-

R — Function reserved.

O

LCD_PWR — LCD panel power enable.

-

R — Function reserved.

O

TRACEDATA[3] — Trace data, bit 3.

O

ENET_MDC — Ethernet MIIM clock.

I/O

SGPIO7 — General purpose digital input/output pin.

AI

ADC1_6 — ADC1, input channel 6. Configure the pin as GPIO input and use
the ADC function select register in the SCU to select the ADC.

I; PU I/O

GPIO4[0] — General purpose digital input/output pin.

I

USB0_PWR_FAULT — Port power fault signal indicating overcurrent
condition; this signal monitors over-current on the USB bus (external circuitry
required to detect over-current condition).

-

R — Function reserved.

I

MCI2 — Motor control PWM channel 2, input.

I/O

SGPIO8 — General purpose digital input/output pin.

-

R — Function reserved.

-

R — Function reserved.

O

T0_MAT0 — Match output 0 of timer 0.

I; PU I/O

GPIO4[1] — General purpose digital input/output pin.

O

USB0_IND1 — USB0 port indicator LED control output 1.

-

R — Function reserved.

I

MCI1 — Motor control PWM channel 1, input.

I/O

SGPIO9 — General purpose digital input/output pin.

-

R — Function reserved.

-

R — Function reserved.

O

T0_MAT1 — Match output 1 of timer 0.

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Rev. 2.4 — 22 August 2018

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323 of 1444

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NXP Semiconductors

Chapter 16: LPC43xx/LPC43Sxx Pin configuration

P8_2

P8_3

P8_4

P8_5

UM10503

User manual

J3

J2

J1

-

-

-

[3]

[2]

[2]

[2]

Type

-

Description

[1]

K4

Reset state

TFBGA100

Symbol

LBGA256

Table 185. LPC4370/LPC43S70 Pin description …continued
LCD is not available on all parts.

I; PU I/O

GPIO4[2] — General purpose digital input/output pin.

O

USB0_IND0 — USB0 port indicator LED control output 0.

-

R — Function reserved.

I

MCI0 — Motor control PWM channel 0, input.

I/O

SGPIO10 — General purpose digital input/output pin.

-

R — Function reserved.

-

R — Function reserved.

O

T0_MAT2 — Match output 2 of timer 0.

I; PU I/O

GPIO4[3] — General purpose digital input/output pin.

I/O

USB1_ULPI_D2 — ULPI link bidirectional data line 2.

-

R — Function reserved.

O

LCD_VD12 — LCD data.

O

LCD_VD19 — LCD data.

-

R — Function reserved.

-

R — Function reserved.

O

T0_MAT3 — Match output 3 of timer 0.

I; PU I/O

GPIO4[4] — General purpose digital input/output pin.

I/O

USB1_ULPI_D1 — ULPI link bidirectional data line 1.

-

R — Function reserved.

O

LCD_VD7 — LCD data.

O

LCD_VD16 — LCD data.

-

R — Function reserved.

-

R — Function reserved.

I

T0_CAP0 — Capture input 0 of timer 0.

I; PU I/O

GPIO4[5] — General purpose digital input/output pin.

I/O

USB1_ULPI_D0 — ULPI link bidirectional data line 0.

-

R — Function reserved.

O

LCD_VD6 — LCD data.

O

LCD_VD8 — LCD data.

-

R — Function reserved.

-

R — Function reserved.

I

T0_CAP1 — Capture input 1 of timer 0.

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324 of 1444

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NXP Semiconductors

Chapter 16: LPC43xx/LPC43Sxx Pin configuration

P8_6

P8_7

P8_8

P9_0

UM10503

User manual

K1

L1

T1

-

-

-

[2]

[2]

[2]

[2]

Type

-

Description

[1]

K3

Reset state

TFBGA100

Symbol

LBGA256

Table 185. LPC4370/LPC43S70 Pin description …continued
LCD is not available on all parts.

I; PU I/O

GPIO4[6] — General purpose digital input/output pin.

I

USB1_ULPI_NXT — ULPI link NXT signal. Data flow control signal from the
PHY.

-

R — Function reserved.

O

LCD_VD5 — LCD data.

O

LCD_LP — Line synchronization pulse (STN). Horizontal synchronization
pulse (TFT).

-

R — Function reserved.

-

R — Function reserved.

I

T0_CAP2 — Capture input 2 of timer 0.

I; PU I/O

GPIO4[7] — General purpose digital input/output pin.

O

USB1_ULPI_STP — ULPI link STP signal. Asserted to end or interrupt
transfers to the PHY.

-

R — Function reserved.

O

LCD_VD4 — LCD data.

O

LCD_PWR — LCD panel power enable.

-

R — Function reserved.

-

R — Function reserved.

I

T0_CAP3 — Capture input 3 of timer 0.

I; PU -

R — Function reserved.

I

USB1_ULPI_CLK — ULPI link CLK signal. 60 MHz clock generated by the
PHY.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

O

CGU_OUT0 — CGU spare clock output 0.

O

I2S1_TX_MCLK — I2S1 transmit master clock.

I; PU I/O

GPIO4[12] — General purpose digital input/output pin.

O

MCABORT — Motor control PWM, LOW-active fast abort.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

I

ENET_CRS — Ethernet Carrier Sense (MII interface).

I/O

SGPIO0 — General purpose digital input/output pin.

I/O

SSP0_SSEL — Slave Select for SSP0.

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NXP Semiconductors

Chapter 16: LPC43xx/LPC43Sxx Pin configuration

P9_1

P9_2

P9_3

P9_4

UM10503

User manual

N8

M6

N10

-

-

-

[2]

[2]

[2]

[2]

Type

-

Description

[1]

N6

Reset state

TFBGA100

Symbol

LBGA256

Table 185. LPC4370/LPC43S70 Pin description …continued
LCD is not available on all parts.

I; PU I/O

GPIO4[13] — General purpose digital input/output pin.

O

MCOA2 — Motor control PWM channel 2, output A.

-

R — Function reserved.

-

R — Function reserved.

I/O

I2S0_TX_WS — Transmit Word Select. It is driven by the master and
received by the slave. Corresponds to the signal WS in the I2S-bus
specification.

I

ENET_RX_ER — Ethernet receive error (MII interface).

I/O

SGPIO1 — General purpose digital input/output pin.

I/O

SSP0_MISO — Master In Slave Out for SSP0.

I; PU I/O

GPIO4[14] — General purpose digital input/output pin.

O

MCOB2 — Motor control PWM channel 2, output B.

-

R — Function reserved.

-

R — Function reserved.

I/O

I2S0_TX_SDA — I2S transmit data. It is driven by the transmitter and read
by the receiver. Corresponds to the signal SD in the I2S-bus specification.

I

ENET_RXD3 — Ethernet receive data 3 (MII interface).

I/O

SGPIO2 — General purpose digital input/output pin.

I/O

SSP0_MOSI — Master Out Slave in for SSP0.

I; PU I/O

GPIO4[15] — General purpose digital input/output pin.

O

MCOA0 — Motor control PWM channel 0, output A.

O

USB1_IND1 — USB1 Port indicator LED control output 1.

-

R — Function reserved.

-

R — Function reserved.

I

ENET_RXD2 — Ethernet receive data 2 (MII interface).

I/O

SGPIO9 — General purpose digital input/output pin.

O

U3_TXD — Transmitter output for USART3.

I; PU -

R — Function reserved.

O

MCOB0 — Motor control PWM channel 0, output B.

O

USB1_IND0 — USB1 Port indicator LED control output 0.

-

R — Function reserved.

I/O

GPIO5[17] — General purpose digital input/output pin.

O

ENET_TXD2 — Ethernet transmit data 2 (MII interface).

I/O

SGPIO4 — General purpose digital input/output pin.

I

U3_RXD — Receiver input for USART3.

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Rev. 2.4 — 22 August 2018

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326 of 1444

UM10503

NXP Semiconductors

Chapter 16: LPC43xx/LPC43Sxx Pin configuration

P9_5

P9_6

PA_0

PA_1

UM10503

User manual

L11

L12

J14

-

-

-

[2]

[2]

[2]

[3]

Type

-

Description

[1]

M9

Reset state

TFBGA100

Symbol

LBGA256

Table 185. LPC4370/LPC43S70 Pin description …continued
LCD is not available on all parts.

I; PU -

R — Function reserved.

O

MCOA1 — Motor control PWM channel 1, output A.

O

USB1_VBUS_EN — USB1 VBUS power enable.

-

R — Function reserved.

I/O

GPIO5[18] — General purpose digital input/output pin.

O

ENET_TXD3 — Ethernet transmit data 3 (MII interface).

I/O

SGPIO3 — General purpose digital input/output pin.

O

U0_TXD — Transmitter output for USART0.

I; PU I/O

GPIO4[11] — General purpose digital input/output pin.

O

MCOB1 — Motor control PWM channel 1, output B.

I

USB1_PWR_FAULT — USB1 Port power fault signal indicating over-current
condition; this signal monitors over-current on the USB1 bus (external
circuitry required to detect over-current condition).

-

R — Function reserved.

-

R — Function reserved.

I

ENET_COL — Ethernet Collision detect (MII interface).

I/O

SGPIO8 — General purpose digital input/output pin.

I

U0_RXD — Receiver input for USART0.

I; PU -

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

O

I2S1_RX_MCLK — I2S1 receive master clock.

O

CGU_OUT1 — CGU spare clock output 1.

-

R — Function reserved.

I; PU I/O

GPIO4[8] — General purpose digital input/output pin.

I

QEI_IDX — Quadrature Encoder Interface INDEX input.

-

R — Function reserved.

O

U2_TXD — Transmitter output for USART2.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

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327 of 1444

UM10503

NXP Semiconductors

Chapter 16: LPC43xx/LPC43Sxx Pin configuration

PA_2

PA_3

PA_4

PB_0

UM10503

User manual

H11

G13

B15

-

-

-

[3]

[3]

[2]

[2]

Type

-

Description

[1]

K15

Reset state

TFBGA100

Symbol

LBGA256

Table 185. LPC4370/LPC43S70 Pin description …continued
LCD is not available on all parts.

I; PU I/O

GPIO4[9] — General purpose digital input/output pin.

I

QEI_PHB — Quadrature Encoder Interface PHB input.

-

R — Function reserved.

I

U2_RXD — Receiver input for USART2.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

I; PU I/O

GPIO4[10] — General purpose digital input/output pin.

I

QEI_PHA — Quadrature Encoder Interface PHA input.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

I; PU -

R — Function reserved.

O

CTOUT_9 — SCT output 9. Match output 1 of timer 2.

-

R — Function reserved.

I/O

EMC_A23 — External memory address line 23.

I/O

GPIO5[19] — General purpose digital input/output pin.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

I; PU -

R — Function reserved.

O

CTOUT_10 — SCT output 10. Match output 2 of timer 2.

O

LCD_VD23 — LCD data.

-

R — Function reserved.

I/O

GPIO5[20] — General purpose digital input/output pin.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

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Rev. 2.4 — 22 August 2018

© NXP B.V. 2018. All rights reserved.

328 of 1444

UM10503

NXP Semiconductors

Chapter 16: LPC43xx/LPC43Sxx Pin configuration

PB_1

PB_2

PB_3

PB_4

UM10503

User manual

B12

A13

B11

-

-

-

[2]

[2]

[2]

[2]

Type

-

Description

[1]

A14

Reset state

TFBGA100

Symbol

LBGA256

Table 185. LPC4370/LPC43S70 Pin description …continued
LCD is not available on all parts.

I; PU -

R — Function reserved.

I

USB1_ULPI_DIR — ULPI link DIR signal. Controls the ULP data line
direction.

O

LCD_VD22 — LCD data.

-

R — Function reserved.

I/O

GPIO5[21] — General purpose digital input/output pin.

O

CTOUT_6 — SCT output 6. Match output 2 of timer 1.

-

R — Function reserved.

-

R — Function reserved.

I; PU -

R — Function reserved.

I/O

USB1_ULPI_D7 — ULPI link bidirectional data line 7.

O

LCD_VD21 — LCD data.

-

R — Function reserved.

I/O

GPIO5[22] — General purpose digital input/output pin.

O

CTOUT_7 — SCT output 7. Match output 3 of timer 1.

-

R — Function reserved.

-

R — Function reserved.

I; PU -

R — Function reserved.

I/O

USB1_ULPI_D6 — ULPI link bidirectional data line 6.

O

LCD_VD20 — LCD data.

-

R — Function reserved.

I/O

GPIO5[23] — General purpose digital input/output pin.

O

CTOUT_8 — SCT output 8. Match output 0 of timer 2.

-

R — Function reserved.

-

R — Function reserved.

I; PU -

R — Function reserved.

I/O

USB1_ULPI_D5 — ULPI link bidirectional data line 5.

O

LCD_VD15 — LCD data.

-

R — Function reserved.

I/O

GPIO5[24] — General purpose digital input/output pin.

I

CTIN_5 — SCT input 5. Capture input 2 of timer 2.

-

R — Function reserved.

-

R — Function reserved.

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Chapter 16: LPC43xx/LPC43Sxx Pin configuration

PB_5

PB_6

A6

-

[2]

[5]
[13]

PC_0

D4

-

[5]
[13]

PC_1

UM10503

User manual

E4

-

[2]

Type

-

Description

[1]

A12

Reset state

TFBGA100

Symbol

LBGA256

Table 185. LPC4370/LPC43S70 Pin description …continued
LCD is not available on all parts.

I; PU -

R — Function reserved.

I/O

USB1_ULPI_D4 — ULPI link bidirectional data line 4.

O

LCD_VD14 — LCD data.

-

R — Function reserved.

I/O

GPIO5[25] — General purpose digital input/output pin.

I

CTIN_7 — SCT input 7.

O

LCD_PWR — LCD panel power enable.

-

R — Function reserved.

I; PU -

R — Function reserved.

I/O

USB1_ULPI_D3 — ULPI link bidirectional data line 3.

O

LCD_VD13 — LCD data.

-

R — Function reserved.

I/O

GPIO5[26] — General purpose digital input/output pin.

I

CTIN_6 — SCT input 6. Capture input 1 of timer 3.

O

LCD_VD19 — LCD data.

-

R — Function reserved.

AI

ADC0_6 — ADC0, input channel 6. Configure the pin as GPIO input and use
the ADC function select register in the SCU to select the ADC.

I; PU -

R — Function reserved.

I

USB1_ULPI_CLK — ULPI link CLK signal. 60 MHz clock generated by the
PHY.

-

R — Function reserved.

I/O

ENET_RX_CLK — Ethernet Receive Clock (MII interface).

O

LCD_DCLK — LCD panel clock.

-

R — Function reserved.

-

R — Function reserved.

I/O

SD_CLK — SD/MMC card clock.

AI

ADC1_1 — ADC1, input channel 1. Configure the pin as USB1_ULPI_CLK
input and use the ADC function select register in the SCU to select the ADC.

I; PU I/O

USB1_ULPI_D7 — ULPI link bidirectional data line 7.

-

R — Function reserved.

I

U1_RI — Ring Indicator input for UART 1.

O

ENET_MDC — Ethernet MIIM clock.

I/O

GPIO6[0] — General purpose digital input/output pin.

-

R — Function reserved.

I

T3_CAP0 — Capture input 0 of timer 3.

O

SD_VOLT0 — SD/MMC bus voltage select output 0.

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Chapter 16: LPC43xx/LPC43Sxx Pin configuration

PC_2

PC_3

PC_4

F5

F4

-

-

[2]

[5]

[2]

Type

-

Description

[1]

F6

Reset state

TFBGA100

Symbol

LBGA256

Table 185. LPC4370/LPC43S70 Pin description …continued
LCD is not available on all parts.

I; PU I/O

USB1_ULPI_D6 — ULPI link bidirectional data line 6.

-

R — Function reserved.

I

U1_CTS — Clear to Send input for UART 1.

O

ENET_TXD2 — Ethernet transmit data 2 (MII interface).

I/O

GPIO6[1] — General purpose digital input/output pin.

-

R — Function reserved.

-

R — Function reserved.

O

SD_RST — SD/MMC reset signal for MMC4.4 card.

I; PU I/O

USB1_ULPI_D5 — ULPI link bidirectional data line 5.

-

R — Function reserved.

O

U1_RTS — Request to Send output for UART 1. Can also be configured to
be an RS-485/EIA-485 output enable signal for UART 1.

O

ENET_TXD3 — Ethernet transmit data 3 (MII interface).

I/O

GPIO6[2] — General purpose digital input/output pin.

-

R — Function reserved.

-

R — Function reserved.

O

SD_VOLT1 — SD/MMC bus voltage select output 1.

AI

ADC1_0 — ADC1, input channel 0. Configure the pin as GPIO input and use
the ADC function select register in the SCU to select the ADC.

I; PU -

R — Function reserved.

I/O

USB1_ULPI_D4 — ULPI link bidirectional data line 4.

-

R — Function reserved.
ENET_TX_EN — Ethernet transmit enable (RMII/MII interface).

PC_5

UM10503

User manual

G4

-

[2]

I/O

GPIO6[3] — General purpose digital input/output pin.

-

R — Function reserved.

I

T3_CAP1 — Capture input 1 of timer 3.

I/O

SD_DAT0 — SD/MMC data bus line 0.

I; PU -

R — Function reserved.

I/O

USB1_ULPI_D3 — ULPI link bidirectional data line 3.

-

R — Function reserved.

O

ENET_TX_ER — Ethernet Transmit Error (MII interface).

I/O

GPIO6[4] — General purpose digital input/output pin.

-

R — Function reserved.

I

T3_CAP2 — Capture input 2 of timer 3.

I/O

SD_DAT1 — SD/MMC data bus line 1.

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Chapter 16: LPC43xx/LPC43Sxx Pin configuration

PC_6

PC_7

PC_8

PC_9

UM10503

User manual

G5

N4

K2

-

-

-

[2]

[2]

[2]

[2]

Type

-

Description

[1]

H6

Reset state

TFBGA100

Symbol

LBGA256

Table 185. LPC4370/LPC43S70 Pin description …continued
LCD is not available on all parts.

I; PU -

R — Function reserved.

I/O

USB1_ULPI_D2 — ULPI link bidirectional data line 2.

-

R — Function reserved.

I

ENET_RXD2 — Ethernet receive data 2 (MII interface).

I/O

GPIO6[5] — General purpose digital input/output pin.

-

R — Function reserved.

I

T3_CAP3 — Capture input 3 of timer 3.

I/O

SD_DAT2 — SD/MMC data bus line 2.

I; PU -

R — Function reserved.

I/O

USB1_ULPI_D1 — ULPI link bidirectional data line 1.

-

R — Function reserved.

I

ENET_RXD3 — Ethernet receive data 3 (MII interface).

I/O

GPIO6[6] — General purpose digital input/output pin.

-

R — Function reserved.

O

T3_MAT0 — Match output 0 of timer 3.

I/O

SD_DAT3 — SD/MMC data bus line 3.

I; PU -

R — Function reserved.

I/O

USB1_ULPI_D0 — ULPI link bidirectional data line 0.

-

R — Function reserved.

I

ENET_RX_DV — Ethernet Receive Data Valid (RMII/MII interface).

I/O

GPIO6[7] — General purpose digital input/output pin.

-

R — Function reserved.

O

T3_MAT1 — Match output 1 of timer 3.

I

SD_CD — SD/MMC card detect input.

I; PU -

R — Function reserved.

I

USB1_ULPI_NXT — ULPI link NXT signal. Data flow control signal from the
PHY.

-

R — Function reserved.

I

ENET_RX_ER — Ethernet receive error (MII interface).

I/O

GPIO6[8] — General purpose digital input/output pin.

-

R — Function reserved.

O

T3_MAT2 — Match output 2 of timer 3.

O

SD_POW — SD/MMC power monitor output.

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Chapter 16: LPC43xx/LPC43Sxx Pin configuration

PC_10

[2]

Type

-

Description

[1]

M5

Reset state

TFBGA100

Symbol

LBGA256

Table 185. LPC4370/LPC43S70 Pin description …continued
LCD is not available on all parts.

I; PU -

USB1_ULPI_STP — ULPI link STP signal. Asserted to end or interrupt
transfers to the PHY.

I

U1_DSR — Data Set Ready input for UART 1.

-

R — Function reserved.

I/O

GPIO6[9] — General purpose digital input/output pin.

-

R — Function reserved.

O

T3_MAT3 — Match output 3 of timer 3.

I/O
PC_11

PC_12

PC_13

UM10503

User manual

L5

L6

M1

-

-

-

[2]

[2]

[2]

R — Function reserved.

O

I; PU -

SD_CMD — SD/MMC command signal.
R — Function reserved.

I

USB1_ULPI_DIR — ULPI link DIR signal. Controls the ULPI data line
direction.

I

U1_DCD — Data Carrier Detect input for UART 1.

-

R — Function reserved.

I/O

GPIO6[10] — General purpose digital input/output pin.

-

R — Function reserved.

-

R — Function reserved.

I/O

SD_DAT4 — SD/MMC data bus line 4.

I; PU -

R — Function reserved.

-

R — Function reserved.

O

U1_DTR — Data Terminal Ready output for UART 1. Can also be configured
to be an RS-485/EIA-485 output enable signal for UART 1.

-

R — Function reserved.

I/O

GPIO6[11] — General purpose digital input/output pin.

I/O

SGPIO11 — General purpose digital input/output pin.

I/O

I2S0_TX_SDA — I2S transmit data. It is driven by the transmitter and read
by the receiver. Corresponds to the signal SD in the I2S-bus specification.

I/O

SD_DAT5 — SD/MMC data bus line 5.

I; PU -

R — Function reserved.

-

R — Function reserved.

O

U1_TXD — Transmitter output for UART 1.

-

R — Function reserved.

I/O

GPIO6[12] — General purpose digital input/output pin.

I/O

SGPIO12 — General purpose digital input/output pin.

I/O

I2S0_TX_WS — Transmit Word Select. It is driven by the master and
received by the slave. Corresponds to the signal WS in the I2S-bus
specification.

I/O

SD_DAT6 — SD/MMC data bus line 6.

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NXP Semiconductors

Chapter 16: LPC43xx/LPC43Sxx Pin configuration

PC_14

PD_0

PD_1

PD_2

UM10503

User manual

N2

P1

R1

-

-

-

[2]

[2]

[2]

[2]

Type

-

Description

[1]

N1

Reset state

TFBGA100

Symbol

LBGA256

Table 185. LPC4370/LPC43S70 Pin description …continued
LCD is not available on all parts.

I; PU -

R — Function reserved.

-

R — Function reserved.

I

U1_RXD — Receiver input for UART 1.

-

R — Function reserved.

I/O

GPIO6[13] — General purpose digital input/output pin.

I/O

SGPIO13 — General purpose digital input/output pin.

O

ENET_TX_ER — Ethernet Transmit Error (MII interface).

I/O

SD_DAT7 — SD/MMC data bus line 7.

I; PU -

R — Function reserved.

O

CTOUT_15 — SCT output 15. Match output 3 of timer 3.

O

EMC_DQMOUT2 — Data mask 2 used with SDRAM and static devices.

-

R — Function reserved.

I/O

GPIO6[14] — General purpose digital input/output pin.

-

R — Function reserved.

-

R — Function reserved.

I/O

SGPIO4 — General purpose digital input/output pin.

I; PU -

R — Function reserved.

-

R — Function reserved.

O

EMC_CKEOUT2 — SDRAM clock enable 2.

-

R — Function reserved.

I/O

GPIO6[15] — General purpose digital input/output pin.

O

SD_POW — SD/MMC power monitor output.

-

R — Function reserved.

I/O

SGPIO5 — General purpose digital input/output pin.

I; PU -

R — Function reserved.

O

CTOUT_7 — SCT output 7. Match output 3 of timer 1.

I/O

EMC_D16 — External memory data line 16.

-

R — Function reserved.

I/O

GPIO6[16] — General purpose digital input/output pin.

-

R — Function reserved.

-

R — Function reserved.

I/O

SGPIO6 — General purpose digital input/output pin.

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Rev. 2.4 — 22 August 2018

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334 of 1444

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NXP Semiconductors

Chapter 16: LPC43xx/LPC43Sxx Pin configuration

PD_3

PD_4

PD_5

PD_6

UM10503

User manual

T2

P6

R6

-

-

-

[2]

[2]

[2]

[2]

Type

-

Description

[1]

P4

Reset state

TFBGA100

Symbol

LBGA256

Table 185. LPC4370/LPC43S70 Pin description …continued
LCD is not available on all parts.

I; PU -

R — Function reserved.

O

CTOUT_6 — SCT output 7. Match output 2 of timer 1.

I/O

EMC_D17 — External memory data line 17.

-

R — Function reserved.

I/O

GPIO6[17] — General purpose digital input/output pin.

-

R — Function reserved.

-

R — Function reserved.

I/O

SGPIO7 — General purpose digital input/output pin.

I; PU -

R — Function reserved.

O

CTOUT_8 — SCT output 8. Match output 0 of timer 2.

I/O

EMC_D18 — External memory data line 18.

-

R — Function reserved.

I/O

GPIO6[18] — General purpose digital input/output pin.

-

R — Function reserved.

-

R — Function reserved.

I/O

SGPIO8 — General purpose digital input/output pin.

I; PU -

R — Function reserved.

O

CTOUT_9 — SCT output 9. Match output 1 of timer 2.

I/O

EMC_D19 — External memory data line 19.

-

R — Function reserved.

I/O

GPIO6[19] — General purpose digital input/output pin.

-

R — Function reserved.

-

R — Function reserved.

I/O

SGPIO9 — General purpose digital input/output pin.

I; PU -

R — Function reserved.

O

CTOUT_10 — SCT output 10. Match output 2 of timer 2.

I/O

EMC_D20 — External memory data line 20.

-

R — Function reserved.

I/O

GPIO6[20] — General purpose digital input/output pin.

-

R — Function reserved.

-

R — Function reserved.

I/O

SGPIO10 — General purpose digital input/output pin.

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NXP Semiconductors

Chapter 16: LPC43xx/LPC43Sxx Pin configuration

PD_7

PD_8

PD_9

PD_10

UM10503

User manual

P8

T11

P11

-

-

-

[2]

[2]

[2]

[2]

Type

-

Description

[1]

T6

Reset state

TFBGA100

Symbol

LBGA256

Table 185. LPC4370/LPC43S70 Pin description …continued
LCD is not available on all parts.

I; PU -

R — Function reserved.

I

CTIN_5 — SCT input 5. Capture input 2 of timer 2.

I/O

EMC_D21 — External memory data line 21.

-

R — Function reserved.

I/O

GPIO6[21] — General purpose digital input/output pin.

-

R — Function reserved.

-

R — Function reserved.

I/O

SGPIO11 — General purpose digital input/output pin.

I; PU -

R — Function reserved.

I

CTIN_6 — SCT input 6. Capture input 1 of timer 3.

I/O

EMC_D22 — External memory data line 22.

-

R — Function reserved.

I/O

GPIO6[22] — General purpose digital input/output pin.

-

R — Function reserved.

-

R — Function reserved.

I/O

SGPIO12 — General purpose digital input/output pin.

I; PU -

R — Function reserved.

O

CTOUT_13 — SCT output 13. Match output 1 of timer 3.

I/O

EMC_D23 — External memory data line 23.

-

R — Function reserved.

I/O

GPIO6[23] — General purpose digital input/output pin.

-

R — Function reserved.

-

R — Function reserved.

I/O

SGPIO13 — General purpose digital input/output pin.

I; PU -

R — Function reserved.

I

CTIN_1 — SCT input 1. Capture input 1 of timer 0. Capture input 1 of timer
2.

O

EMC_BLS3 — LOW active Byte Lane select signal 3.

-

R — Function reserved.

I/O

GPIO6[24] — General purpose digital input/output pin.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

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© NXP B.V. 2018. All rights reserved.

336 of 1444

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NXP Semiconductors

Chapter 16: LPC43xx/LPC43Sxx Pin configuration

PD_11

PD_12

PD_13

PD_14

UM10503

User manual

N11

T14

R13

-

-

-

[2]

[2]

[2]

[2]

Type

-

Description

[1]

N9

Reset state

TFBGA100

Symbol

LBGA256

Table 185. LPC4370/LPC43S70 Pin description …continued
LCD is not available on all parts.

I; PU -

R — Function reserved.

-

R — Function reserved.

O

EMC_CS3 — LOW active Chip Select 3 signal.

-

R — Function reserved.

I/O

GPIO6[25] — General purpose digital input/output pin.

I/O

USB1_ULPI_D0 — ULPI link bidirectional data line 0.

O

CTOUT_14 — SCT output 14. Match output 2 of timer 3.

-

R — Function reserved.

I; PU -

R — Function reserved.

-

R — Function reserved.

O

EMC_CS2 — LOW active Chip Select 2 signal.

-

R — Function reserved.

I/O

GPIO6[26] — General purpose digital input/output pin.

-

R — Function reserved.

O

CTOUT_10 — SCT output 10. Match output 2 of timer 2.

-

R — Function reserved.

I; PU -

R — Function reserved.

I

CTIN_0 — SCT input 0. Capture input 0 of timer 0, 1, 2, 3.

O

EMC_BLS2 — LOW active Byte Lane select signal 2.

-

R — Function reserved.

I/O

GPIO6[27] — General purpose digital input/output pin.

-

R — Function reserved.

O

CTOUT_13 — SCT output 13. Match output 1 of timer 3.

-

R — Function reserved.

I; PU -

R — Function reserved.

-

R — Function reserved.

O

EMC_DYCS2 — SDRAM chip select 2.

-

R — Function reserved.

I/O

GPIO6[28] — General purpose digital input/output pin.

-

R — Function reserved.

O

CTOUT_11 — SCT output 11. Match output 3 of timer 2.

-

R — Function reserved.

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Rev. 2.4 — 22 August 2018

© NXP B.V. 2018. All rights reserved.

337 of 1444

UM10503

NXP Semiconductors

Chapter 16: LPC43xx/LPC43Sxx Pin configuration

PD_15

PD_16

PE_0

PE_1

UM10503

User manual

R14

P14

N14

-

-

-

[2]

[2]

[2]

[2]

Type

-

Description

[1]

T15

Reset state

TFBGA100

Symbol

LBGA256

Table 185. LPC4370/LPC43S70 Pin description …continued
LCD is not available on all parts.

I; PU -

R — Function reserved.

-

R — Function reserved.

I/O

EMC_A17 — External memory address line 17.

-

R — Function reserved.

I/O

GPIO6[29] — General purpose digital input/output pin.

I

SD_WP — SD/MMC card write protect input.

O

CTOUT_8 — SCT output 8. Match output 0 of timer 2.

-

R — Function reserved.

I; PU -

R — Function reserved.

-

R — Function reserved.

I/O

EMC_A16 — External memory address line 16.

-

R — Function reserved.

I/O

GPIO6[30] — General purpose digital input/output pin.

O

SD_VOLT2 — SD/MMC bus voltage select output 2.

O

CTOUT_12 — SCT output 12. Match output 0 of timer 3.

-

R — Function reserved.

I; PU -

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

I/O

EMC_A18 — External memory address line 18.

I/O

GPIO7[0] — General purpose digital input/output pin.

O

CAN1_TD — CAN1 transmitter output.

-

R — Function reserved.

-

R — Function reserved.

I; PU -

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

I/O

EMC_A19 — External memory address line 19.

I/O

GPIO7[1] — General purpose digital input/output pin.

I

CAN1_RD — CAN1 receiver input.

-

R — Function reserved.

-

R — Function reserved.

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NXP Semiconductors

Chapter 16: LPC43xx/LPC43Sxx Pin configuration

PE_2

PE_3

PE_4

PE_5

UM10503

User manual

K12

K13

N16

-

-

-

[2]

[2]

[2]

[2]

Type

-

Description

[1]

M14

Reset state

TFBGA100

Symbol

LBGA256

Table 185. LPC4370/LPC43S70 Pin description …continued
LCD is not available on all parts.

I; PU I

ADCTRIG0 — ADC trigger input 0.

I

CAN0_RD — CAN receiver input.

-

R — Function reserved.

I/O

EMC_A20 — External memory address line 20.

I/O

GPIO7[2] — General purpose digital input/output pin.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

I; PU -

R — Function reserved.

O

CAN0_TD — CAN transmitter output.

I

ADCTRIG1 — ADC trigger input 1.

I/O

EMC_A21 — External memory address line 21.

I/O

GPIO7[3] — General purpose digital input/output pin.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

I; PU -

R — Function reserved.

I

NMI — External interrupt input to NMI.

-

R — Function reserved.

I/O

EMC_A22 — External memory address line 22.

I/O

GPIO7[4] — General purpose digital input/output pin.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

I; PU -

R — Function reserved.

O

CTOUT_3 — SCT output 3. Match output 3 of timer 0.

O

U1_RTS — Request to Send output for UART 1. Can also be configured to
be an RS-485/EIA-485 output enable signal for UART 1.

I/O

EMC_D24 — External memory data line 24.

I/O

GPIO7[5] — General purpose digital input/output pin.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

All information provided in this document is subject to legal disclaimers.

Rev. 2.4 — 22 August 2018

© NXP B.V. 2018. All rights reserved.

339 of 1444

UM10503

NXP Semiconductors

Chapter 16: LPC43xx/LPC43Sxx Pin configuration

PE_6

PE_7

PE_8

PE_9

UM10503

User manual

F15

F14

E16

-

-

-

[2]

[2]

[2]

[2]

Type

-

Description

[1]

M16

Reset state

TFBGA100

Symbol

LBGA256

Table 185. LPC4370/LPC43S70 Pin description …continued
LCD is not available on all parts.

I; PU -

R — Function reserved.

O

CTOUT_2 — SCT output 2. Match output 2 of timer 0.

I

U1_RI — Ring Indicator input for UART 1.

I/O

EMC_D25 — External memory data line 25.

I/O

GPIO7[6] — General purpose digital input/output pin.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

I; PU -

R — Function reserved.

O

CTOUT_5 — SCT output 5. Match output 1 of timer 1.

I

U1_CTS — Clear to Send input for UART1.

I/O

EMC_D26 — External memory data line 26.

I/O

GPIO7[7] — General purpose digital input/output pin.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

I; PU -

R — Function reserved.

O

CTOUT_4 — SCT output 4. Match output 0 of timer 0.

I

U1_DSR — Data Set Ready input for UART 1.

I/O

EMC_D27 — External memory data line 27.

I/O

GPIO7[8] — General purpose digital input/output pin.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

I; PU -

R — Function reserved.

I

CTIN_4 — SCT input 4. Capture input 2 of timer 1.

I

U1_DCD — Data Carrier Detect input for UART 1.

I/O

EMC_D28 — External memory data line 28.

I/O

GPIO7[9] — General purpose digital input/output pin.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

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Chapter 16: LPC43xx/LPC43Sxx Pin configuration

PE_10

PE_11

PE_12

PE_13

UM10503

User manual

D16

D15

G14

-

-

-

[2]

[2]

[2]

[2]

Type

-

Description

[1]

E14

Reset state

TFBGA100

Symbol

LBGA256

Table 185. LPC4370/LPC43S70 Pin description …continued
LCD is not available on all parts.

I; PU -

R — Function reserved.

I

CTIN_3 — SCT input 3. Capture input 1 of timer 1.

O

U1_DTR — Data Terminal Ready output for UART 1. Can also be configured
to be an RS-485/EIA-485 output enable signal for UART 1.

I/O

EMC_D29 — External memory data line 29.

I/O

GPIO7[10] — General purpose digital input/output pin.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

I; PU -

R — Function reserved.

O

CTOUT_12 — SCT output 12. Match output 0 of timer 3.

O

U1_TXD — Transmitter output for UART 1.

I/O

EMC_D30 — External memory data line 30.

I/O

GPIO7[11] — General purpose digital input/output pin.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

I; PU -

R — Function reserved.

O

CTOUT_11 — SCT output 11. Match output 3 of
timer 2.

I

U1_RXD — Receiver input for UART 1.

I/O

EMC_D31 — External memory data line 31.

I/O

GPIO7[12] — General purpose digital input/output pin.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

I; PU -

R — Function reserved.

O

CTOUT_14 — SCT output 14. Match output 2 of timer 3.

I/O

I2C1_SDA — I2C1 data input/output (this pin does not use a specialized I2C
pad).

O

EMC_DQMOUT3 — Data mask 3 used with SDRAM and static devices.

I/O

GPIO7[13] — General purpose digital input/output pin.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

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Chapter 16: LPC43xx/LPC43Sxx Pin configuration

PE_14

PE_15

PF_0

E13

D12

-

-

[2]

[2]

[2]

Type

-

Description

[1]

C15

Reset state

TFBGA100

Symbol

LBGA256

Table 185. LPC4370/LPC43S70 Pin description …continued
LCD is not available on all parts.

I; PU -

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

O

EMC_DYCS3 — SDRAM chip select 3.

I/O

GPIO7[14] — General purpose digital input/output pin.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

I; PU -

R — Function reserved.

O;
PU

O

CTOUT_0 — SCT output 0. Match output 0 of timer 0.

I/O

I2C1_SCL — I2C1 clock input/output (this pin does not use a specialized I2C
pad).

O

EMC_CKEOUT3 — SDRAM clock enable 3.

I/O

GPIO7[15] — General purpose digital input/output pin.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

I/O

SSP0_SCK — Serial clock for SSP0.

I

GP_CLKIN — General purpose clock input to the CGU.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

O
PF_1

UM10503

User manual

E11

-

[2]

I2S1_TX_MCLK — I2S1 transmit master clock.

I; PU -

R — Function reserved.

-

R — Function reserved.

I/O

SSP0_SSEL — Slave Select for SSP0.

-

R — Function reserved.

I/O

GPIO7[16] — General purpose digital input/output pin.

-

R — Function reserved.

I/O

SGPIO0 — General purpose digital input/output pin.

-

R — Function reserved.

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Chapter 16: LPC43xx/LPC43Sxx Pin configuration

PF_2

PF_3

PF_4

PF_5

UM10503

User manual

E10

D10

E9

-

H4

-

[2]

[2]

[2]

[5]

Type

-

Description

[1]

D11

Reset state

TFBGA100

Symbol

LBGA256

Table 185. LPC4370/LPC43S70 Pin description …continued
LCD is not available on all parts.

I; PU -

R — Function reserved.

O

U3_TXD — Transmitter output for USART3.

I/O

SSP0_MISO — Master In Slave Out for SSP0.

-

R — Function reserved.

I/O

GPIO7[17] — General purpose digital input/output pin.

-

R — Function reserved.

I/O

SGPIO1 — General purpose digital input/output pin.

-

R — Function reserved.

I; PU -

R — Function reserved.

O;
PU

I

U3_RXD — Receiver input for USART3.

I/O

SSP0_MOSI — Master Out Slave in for SSP0.

-

R — Function reserved.

I/O

GPIO7[18] — General purpose digital input/output pin.

-

R — Function reserved.

I/O

SGPIO2 — General purpose digital input/output pin.

-

R — Function reserved.

I/O

SSP1_SCK — Serial clock for SSP1.

I

GP_CLKIN — General purpose clock input to the CGU.

O

TRACECLK — Trace clock.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

O

I2S0_TX_MCLK — I2S transmit master clock.

I/O

I2S0_RX_SCK — I2S receive clock. It is driven by the master and received
by the slave. Corresponds to the signal SCK in the I2S-bus specification.

I; PU -

R — Function reserved.

I/O

U3_UCLK — Serial clock input/output for USART3 in synchronous mode.

I/O

SSP1_SSEL — Slave Select for SSP1.

O

TRACEDATA[0] — Trace data, bit 0.

I/O

GPIO7[19] — General purpose digital input/output pin.

-

R — Function reserved.

I/O

SGPIO4 — General purpose digital input/output pin.

-

R — Function reserved.

AI

ADC1_4 — ADC1, input channel 4. Configure the pin as GPIO input and use
the ADC function select register in the SCU to select the ADC.

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NXP Semiconductors

Chapter 16: LPC43xx/LPC43Sxx Pin configuration

PF_6

PF_7

PF_8

B7

E6

-

-

[5]

[5]

[5]
[13]

UM10503

User manual

Type

-

Description

[1]

E7

Reset state

TFBGA100

Symbol

LBGA256

Table 185. LPC4370/LPC43S70 Pin description …continued
LCD is not available on all parts.

I; PU -

R — Function reserved.

I/O

U3_DIR — RS-485/EIA-485 output enable/direction control for USART3.

I/O

SSP1_MISO — Master In Slave Out for SSP1.

O

TRACEDATA[1] — Trace data, bit 1.

I/O

GPIO7[20] — General purpose digital input/output pin.

-

R — Function reserved.

I/O

SGPIO5 — General purpose digital input/output pin.

I/O

I2S1_TX_SDA — I2S1 transmit data. It is driven by the transmitter and read
by the receiver. Corresponds to the signal SD in the I2S-bus specification.

AI

ADC1_3 — ADC1, input channel 3. Configure the pin as GPIO input and use
the ADC function select register in the SCU to select the ADC.

I; PU -

R — Function reserved.

I/O

U3_BAUD — Baud pin for USART3.

I/O

SSP1_MOSI — Master Out Slave in for SSP1.

O

TRACEDATA[2] — Trace data, bit 2.

I/O

GPIO7[21] — General purpose digital input/output pin.

-

R — Function reserved.

I/O

SGPIO6 — General purpose digital input/output pin.

I/O

I2S1_TX_WS — Transmit Word Select. It is driven by the master and
received by the slave. Corresponds to the signal WS in the I2S-bus
specification.

AI/
O

ADC1_7 — ADC1, input channel 7 or band gap output. Configure the pin as
GPIO input and use the ADC function select register in the SCU to select the
ADC.

I; PU -

R — Function reserved.

I/O

U0_UCLK — Serial clock input/output for USART0 in synchronous mode.

I

CTIN_2 — SCT input 2. Capture input 2 of timer 0.

O

TRACEDATA[3] — Trace data, bit 3.

I/O

GPIO7[22] — General purpose digital input/output pin.

-

R — Function reserved.

I/O

SGPIO7 — General purpose digital input/output pin.

-

R — Function reserved.

AI

ADC0_2 — ADC0, input channel 2. Configure the pin as GPIO input and use
the ADC function select register in the SCU to select the ADC.

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NXP Semiconductors

Chapter 16: LPC43xx/LPC43Sxx Pin configuration

PF_9

[5]
[13]

PF_10

A3

-

[5]
[13]

PF_11

A2

-

[5]
[13]

UM10503

User manual

Type

-

Description

[1]

D6

Reset state

TFBGA100

Symbol

LBGA256

Table 185. LPC4370/LPC43S70 Pin description …continued
LCD is not available on all parts.

I; PU -

R — Function reserved.

I/O

U0_DIR — RS-485/EIA-485 output enable/direction control for USART0.

O

CTOUT_1 — SCT output 1. Match output 1 of timer 0.

-

R — Function reserved.

I/O

GPIO7[23] — General purpose digital input/output pin.

-

R — Function reserved.

I/O

SGPIO3 — General purpose digital input/output pin.

-

R — Function reserved.

AI

ADC1_2 — ADC1, input channel 2. Configure the pin as GPIO input and use
the ADC function select register in the SCU to select the ADC.

I; PU -

R — Function reserved.

O

U0_TXD — Transmitter output for USART0.

-

R — Function reserved.

-

R — Function reserved.

I/O

GPIO7[24] — General purpose digital input/output pin.

-

R — Function reserved.

I

SD_WP — SD/MMC card write protect input.

-

R — Function reserved.

AI

ADC0_5 — ADC0, input channel 5. Configure the pin as GPIO input and use
the ADC function select register in the SCU to select the ADC.

I; PU -

R — Function reserved.

I

U0_RXD — Receiver input for USART0.

-

R — Function reserved.

-

R — Function reserved.

I/O

GPIO7[25] — General purpose digital input/output pin.

-

R — Function reserved.

O

SD_VOLT2 — SD/MMC bus voltage select output 2.

-

R — Function reserved.

AI

ADC1_5 — ADC1, input channel 5. Configure the pin as GPIO input and use
the ADC function select register in the SCU to select the ADC.

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NXP Semiconductors

Chapter 16: LPC43xx/LPC43Sxx Pin configuration

Type

K3

Description

[1]

N5

Reset state

TFBGA100

Symbol

LBGA256

Table 185. LPC4370/LPC43S70 Pin description …continued
LCD is not available on all parts.

Clock pins
CLK0

CLK1

CLK2

CLK3

T10

D14

P12

-

K6

-

[4]

[4]

[4]

[4]

O;
PU

O;
PU

O;
PU

O;
PU

O

EMC_CLK0 — SDRAM clock 0.

O

CLKOUT — Clock output pin.

-

R — Function reserved.

-

R — Function reserved.

I/O

SD_CLK — SD/MMC card clock.

O

EMC_CLK01 — SDRAM clock 0 and clock 1 combined.

I/O

SSP1_SCK — Serial clock for SSP1.

I

ENET_TX_CLK (ENET_REF_CLK) — Ethernet Transmit Clock (MII
interface) or Ethernet Reference Clock (RMII interface).

O

EMC_CLK1 — SDRAM clock 1.

O

CLKOUT — Clock output pin.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

O

CGU_OUT0 — CGU spare clock output 0.

-

R — Function reserved.

O

I2S1_TX_MCLK — I2S1 transmit master clock.

O

EMC_CLK3 — SDRAM clock 3.

O

CLKOUT — Clock output pin.

-

R — Function reserved.

-

R — Function reserved.

I/O

SD_CLK — SD/MMC card clock.

O

EMC_CLK23 — SDRAM clock 2 and clock 3 combined.

O

I2S0_TX_MCLK — I2S transmit master clock.

I/O

I2S1_RX_SCK — Receive Clock. It is driven by the master and received by
the slave. Corresponds to the signal SCK in the I2S-bus specification.

O

EMC_CLK2 — SDRAM clock 2.

O

CLKOUT — Clock output pin.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

O

CGU_OUT1 — CGU spare clock output 1.

-

R — Function reserved.

I/O

I2S1_RX_SCK — Receive Clock. It is driven by the master and received by
the slave. Corresponds to the signal SCK in the I2S-bus specification.

I

JTAG interface control signal. Also used for boundary scan.

Debug pins
DBGEN
UM10503

User manual

L4

A6

[2]

I

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NXP Semiconductors

Chapter 16: LPC43xx/LPC43Sxx Pin configuration

J5

H2

[2]

I; F

TRST

M4

B4

[2]

I; PU I

Test Reset for JTAG interface.

TMS/SWDIO

K6

C4

[2]

I; PU I

Test Mode Select for JTAG interface (default) or SW debug data
input/output.

TDO/SWO

K5

H3

[2]

O

TDI

J4

G3

[2]

I; PU I

Test Data In for JTAG interface.

F2

E1

[6]

-

I/O

USB0 bidirectional D+ line.

-

I/O

USB0 bidirectional D line.

-

I/O

VBUS pin (power on USB cable). This pin includes an internal pull-down
resistor of 64 k (typical)  16 k.

I

Indicates to the transceiver whether connected as an A-device (USB0_ID
LOW) or B-device (USB0_ID HIGH). For OTG this pin has an internal pull-up
resistor.

Type

TCK/SWDCLK

[1]

TFBGA100

Description

LBGA256

Symbol

Reset state

Table 185. LPC4370/LPC43S70 Pin description …continued
LCD is not available on all parts.

I

O

Test Clock for JTAG interface (default) or Serial Wire (SW) clock.

Test Data Out for JTAG interface (default) or SW trace output.

USB0 pins
USB0_DP
USB0_DM

G2

E2

[6]

USB0_VBUS

F1

E3

[6]
[7]

USB0_ID

H2

F1

[8]

-

USB0_RREF

H1

F3

[8]

-

USB1_DP

F12

E9

[9]

-

I/O

USB1 bidirectional D+ line.

USB1_DM

G12

E10

[9]

-

I/O

USB1 bidirectional D line.

I2C0_SCL

L15

D6

[10]

I; F

I/O

I2C clock input/output. Open-drain output (for I2C-bus compliance).

I2C0_SDA

L16

E6

[10]

I; F

I/O

I2C data input/output. Open-drain output (for I2C-bus compliance).

12.0 k (accuracy 1 %) on-board resistor to ground for current reference.

USB1 pins

I2C-bus

pins

Reset and wake-up pins
RESET

D9

B6

[11]

I; IA

I

External reset input: A LOW-going pulse as short as 50 ns on this pin resets
the device, causing I/O ports and peripherals to take on their default states,
and processor execution to begin at address 0.

WAKEUP0

A9

A4

[11]

I; IA

I

External wake-up input; can raise an interrupt and can cause wake-up from
any of the low power modes.

WAKEUP1

A10

-

[11]

I; IA

I

External wake-up input; can raise an interrupt and can cause wake-up from
any of the low power modes.

WAKEUP2

C9

-

[11]

I; IA

I

External wake-up input; can raise an interrupt and can cause wake-up from
any of the low power modes.

WAKEUP3

D8

-

[11]

I; IA

I

External wake-up input; can raise an interrupt and can cause wake-up from
any of the low power modes.

UM10503

User manual

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NXP Semiconductors

Chapter 16: LPC43xx/LPC43Sxx Pin configuration

A2

[8]

I; IA

I

12-bit high-speed ADC input channel 0.

A1

[8]

I; IA

I

12-bit high-speed ADC input channel 1.

I; IA

I

12-bit high-speed ADC input channel 2.

Type

E3

[1]

TFBGA100

Description

LBGA256

Symbol

Reset state

Table 185. LPC4370/LPC43S70 Pin description …continued
LCD is not available on all parts.

ADC pins
ADCHS_0
ADCHS_1

C3

ADCHS_2

A4

B3

[8]

ADCHS_3

A5

-

[8]

I; IA

I

12-bit high-speed ADC input channel 3.

-

[8]

I; IA

I

12-bit high-speed ADC input channel 4.

-

[8]

I; IA

I

12-bit high-speed ADC input channel 5.

I; IA

I/O

12-bit high-speed ADC reference voltage output or negative differential
input.

I

10-bit ADC0 input channel 7.

ADCHS_4
ADCHS_5

C6
B3

ADCHS_NEG

B5

A3

[8]

ADC0_7

C5

-

[8]

I; IA

RTC_ALARM

A11

C3

[11]

-

O

RTC controlled output.

RTCX1

A8

A5

[8]

-

I

Input to the RTC 32 kHz ultra-low power oscillator circuit.

RTCX2

B8

B5

[8]

-

O

Output from the RTC 32 kHz ultra-low power oscillator circuit.

RTC

Crystal oscillator pins
XTAL1

D1

B1

[8]

-

I

Input to the oscillator circuit and internal clock generator circuits.

XTAL2

E1

C1

[8]

-

O

Output from the oscillator amplifier.

Power and ground pins
USB0_VDDA
3V3_DRIVER

F3

D1

-

-

Separate analog 3.3 V power supply for driver.

USB0
_VDDA3V3

G3

D2

-

-

USB 3.3 V separate power supply voltage.

USB0_VSSA
_TERM

H3

D3

-

-

Dedicated analog ground for clean reference for termination resistors.

USB0_VSSA
_REF

G1

F2

-

-

Dedicated clean analog ground for generation of reference currents and
voltages.

VDDA

B4

B2

-

-

Analog power supply and 10-bit ADC reference voltage.

VBAT

B10

C5

-

-

RTC power supply: 3.3 V on this pin supplies power to the RTC.

VDDREG

F10,
F9,
L8,
L7

E4,
E5,
F4

-

Main regulator power supply. Tie the VDDREG and VDDIO pins to a
common power supply to ensure the same ramp-up time for both supply
voltages.

VPP

E8

-

-

OTP programming voltage.

UM10503

User manual

-

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Rev. 2.4 — 22 August 2018

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348 of 1444

UM10503

NXP Semiconductors

Chapter 16: LPC43xx/LPC43Sxx Pin configuration

Type

Description

[1]

Reset state

TFBGA100

Symbol

LBGA256

Table 185. LPC4370/LPC43S70 Pin description …continued
LCD is not available on all parts.

VDDIO

D7,
F10,
E12, K5
F7,
F8,
G10,
H10,
J6,
J7,
K7,
L9,
L10,
N7,
N13

VDD

-

-

VSS

G9,
H7,
J10,
J11,
K8

-

-

-

Ground.

VSSIO

C4,
D13,
G6,
G7,
G8,
H8,
H9,
J8,
J9,
K9,
K10,
M13,
P7,
P13

C8,
D4,
D5,
G8,
J3,
J6

-

-

Ground.

VSSA

B2

C2

-

-

Analog ground.

B9

-

-

-

n.c.

-

-

I/O power supply. Tie the VDDREG and VDDIO pins to a common power
supply to ensure the same ramp-up time for both supply voltages.

Power supply for main regulator, I/O, and OTP.

Not connected
[1]

- = not pinned out.

[2]

I = input, O = output, AI/O analog input/output, IA = inactive; PU = pull-up enabled (weak pull-up resistor pulls up pin to VDD(IO)); F =
floating. Reset state reflects the pin state at reset without boot code operation.

[3]

5 V tolerant pad with 15 ns glitch filter (5 V tolerant if VDD(IO) present; if VDD(IO) not present, do not exceed 3.3 V); provides digital I/O
functions with TTL levels and hysteresis; normal drive strength.

[4]

5 V tolerant pad with 15 ns glitch filter (5 V tolerant if VDD(IO) present; if VDD(IO) not present, do not exceed 3.3 V) providing digital I/O
functions with TTL levels, and hysteresis; high drive strength.

[5]

5 V tolerant pad with 15 ns glitch filter (5 V tolerant if VDD(IO) present; if VDD(IO) not present, do not exceed 3.3 V) providing high-speed
digital I/O functions with TTL levels and hysteresis.

UM10503

User manual

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Chapter 16: LPC43xx/LPC43Sxx Pin configuration

[6]

5 V tolerant pad providing digital I/O functions (with TTL levels and hysteresis) and analog input or output (5 V tolerant if VDD(IO) present;
if VDD(IO) not present, do not exceed 3.3 V). When configured as a ADC input or DAC output, the pin is not 5 V tolerant and the digital
section of the pad must be disabled by setting the pin to an input function and disabling the pull-up resistor through the pin’s SFSP
register.

[7]

5 V tolerant transparent analog pad.

[8]

For maximum load CL = 6.5 F and maximum resistance Rpd = 80 k, the VBUS signal takes about 2 s to fall from VBUS = 5 V to VBUS
= 0.2 V when it is no longer driven.

[9]

Transparent analog pad. Not 5 V tolerant.

[10] Pad provides USB functions (5 V tolerant if VDD(IO) present; if VDD(IO) not present, do not exceed 3.3 V). It is designed in accordance
with the USB specification, revision 2.0 (Full-speed and Low-speed mode only).
[11] Open-drain 5 V tolerant digital I/O pad, compatible with I2C-bus Fast Mode Plus specification. This pad requires an external pull-up to
provide output functionality. When power is switched off, this pin connected to the I2C-bus is floating and does not disturb the I2C lines.
[12] 5 V tolerant pad with 20 ns glitch filter; provides digital I/O functions with open-drain output with weak pull-up resistor and hysteresis.
[13] To minimize interference on the 12-bit ADC signal lines, do not configure the digital signal as output when using the 12-bit ADC. See
Table 186.

To reduce interference from digital signals to the high-speed 12-bit ADC inputs, do not
configure digital pins that are pinned out close to the ADC signals as outputs when using
the 12-bit ADC. For the BGA256 package, the pins with interfering signals are shown in
Table 186.
Table 186. 12-bit ADC signal interferences for BGA256 package
12-bit ADC signal

LBGA256

Interfering pins

LBGA256

ADCHS0

E3

P4_3, PC_0

C2, D4

ADCHS1

C3

P4_1, P8_0, PC_0

A1, E5, D4

ADCHS2

A4

PF_10, PF_11

A3, A2

ADCHS3

A5

PF_9, PF_10

D6, A3

ADCHS4

C6

P7_7, PB_6

B6, A6

ADCHS5

B3

PF_11

A2

ADCHS_NEG

B5

P7_7, PF_8

B6, E6

16.2.3 LPC436x/5x/3x/2x/1x, LPC43S6x/S5x/S3x Pin description
Remark: These parts contain two 10-bit ADCs (ADC0 and ADC1). The input channels of
ADC0 and ADC1 are combined in such a way that channel 0 inputs (named ADC0_0 and
ADC1_0) are tied together and connected to both, channel 0 on ADC0 and channel 0 on
ADC1, channel 1 inputs (named ADC0_1 and ADC1_1) are tied together and connected
to channel 1 on ADC0 and ADC1, and so forth. There are eight ADC channels total for the
two ADCs.

UM10503

User manual

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NXP Semiconductors

Chapter 16: LPC43xx/LPC43Sxx Pin configuration

Type

32

Description

[1]

LQFP144

47

Reset state

LQFP208

TFBGA100

Pin name

LBGA256

Table 187. LPC436x/5x/3x/2x/1x, LPC43S6x/S5x/S3xpin description (flash parts)

Multiplexed digital pins
P0_0

P0_1

L3

M2

G2

G1

50

34

[2]

[2]

N;
PU

N;
PU

I/O

GPIO0[0] — General purpose digital input/output pin.

I/O

SSP1_MISO — Master In Slave Out for SSP1.

I

ENET_RXD1 — Ethernet receive data 1 (RMII/MII interface).

I/O

SGPIO0 — General purpose digital input/output pin.

-

R — Function reserved.

-

R — Function reserved.

I/O

I2S0_TX_WS — Transmit Word Select. It is driven by the
master and received by the slave. Corresponds to the signal
WS in the I2S-bus specification.

I/O

I2S1_TX_WS — Transmit Word Select. It is driven by the
master and received by the slave. Corresponds to the signal
WS in the I2S-bus specification.

I/O

GPIO0[1] — General purpose digital input/output pin.

I/O

SSP1_MOSI — Master Out Slave in for SSP1.

I

ENET_COL — Ethernet Collision detect (MII interface).

I/O

SGPIO1 — General purpose digital input/output pin.

-

R — Function reserved.

-

R — Function reserved.
ENET_TX_EN — Ethernet transmit enable (RMII/MII
interface).

P1_0

UM10503

User manual

P2

H1

54

38

[2]

N;
PU

I/O

I2S1_TX_SDA — I2S1 transmit data. It is driven by the
transmitter and read by the receiver. Corresponds to the signal
SD in the I2S-bus specification.

I/O

GPIO0[4] — General purpose digital input/output pin.

I

CTIN_3 — SCT input 3. Capture input 1 of timer 1.

I/O

EMC_A5 — External memory address line 5.

-

R — Function reserved.

-

R — Function reserved.

I/O

SSP0_SSEL — Slave Select for SSP0.

I/O

SGPIO7 — General purpose digital input/output pin.

I/O

EMC_D12 — External memory data line 12.

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Chapter 16: LPC43xx/LPC43Sxx Pin configuration

P1_2

P1_3

P1_4

UM10503

User manual

58

42

R3

P5

T3

K1

J1

J2

60

61

64

43

44

47

[2]

[2]

[2]

[2]

N;
PU

N;
PU

N;
PU

N;
PU

Type

K2

Description

[1]

LQFP144

R2

Reset state

LQFP208

P1_1

TFBGA100

Pin name

LBGA256

Table 187. LPC436x/5x/3x/2x/1x, LPC43S6x/S5x/S3xpin description (flash parts) …continued

I/O

GPIO0[8] — General purpose digital input/output pin. Boot pin
(see Table 22).

O

CTOUT_7 — SCT output 7. Match output 3 of timer 1.

I/O

EMC_A6 — External memory address line 6.

I/O

SGPIO8 — General purpose digital input/output pin.

-

R — Function reserved.

I/O

SSP0_MISO — Master In Slave Out for SSP0.

-

R — Function reserved.

I/O

EMC_D13 — External memory data line 13.

I/O

GPIO0[9] — General purpose digital input/output pin. Boot pin
(see Table 22).

O

CTOUT_6 — SCT output 6. Match output 2 of timer 1.

I/O

EMC_A7 — External memory address line 7.

I/O

SGPIO9 — General purpose digital input/output pin.

-

R — Function reserved.

I/O

SSP0_MOSI — Master Out Slave in for SSP0.

-

R — Function reserved.

I/O

EMC_D14 — External memory data line 14.

I/O

GPIO0[10] — General purpose digital input/output pin.

O

CTOUT_8 — SCT output 8. Match output 0 of timer 2.

I/O

SGPIO10 — General purpose digital input/output pin.

O

EMC_OE — LOW active Output Enable signal.

O

USB0_IND1 — USB0 port indicator LED control
output 1.

I/O

SSP1_MISO — Master In Slave Out for SSP1.

-

R — Function reserved.

O

SD_RST — SD/MMC reset signal for MMC4.4 card.

I/O

GPIO0[11] — General purpose digital input/output pin.

O

CTOUT_9 — SCT output 9. Match output 3 of timer 3.

I/O

SGPIO11 — General purpose digital input/output pin.

O

EMC_BLS0 — LOW active Byte Lane select signal 0.

O

USB0_IND0 — USB0 port indicator LED control output 0.

I/O

SSP1_MOSI — Master Out Slave in for SSP1.

I/O

EMC_D15 — External memory data line 15.

O

SD_VOLT1 — SD/MMC bus voltage select output 1.

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NXP Semiconductors

Chapter 16: LPC43xx/LPC43Sxx Pin configuration

P1_6

P1_7

65

48

T4

T5

K4

G4

67

69

49

50

[2]

[2]

[2]

N;
PU

N;
PU

N;
PU

Type

J4

Description

[1]

LQFP144

R5

Reset state

LQFP208

P1_5

TFBGA100

Pin name

LBGA256

Table 187. LPC436x/5x/3x/2x/1x, LPC43S6x/S5x/S3xpin description (flash parts) …continued

I/O

GPIO1[8] — General purpose digital input/output pin.

O

CTOUT_10 — SCT output 10. Match output 3 of timer 3.

-

R — Function reserved.

O

EMC_CS0 — LOW active Chip Select 0 signal.

I

USB0_PWR_FAULT — Port power fault signal indicating
overcurrent condition; this signal monitors over-current on the
USB bus (external circuitry required to detect over-current
condition).

I/O

SSP1_SSEL — Slave Select for SSP1.

I/O

SGPIO15 — General purpose digital input/output pin.

O

SD_POW — SD/MMC power monitor output.

I/O

GPIO1[9] — General purpose digital input/output pin.

I

CTIN_5 — SCT input 5. Capture input 2 of timer 2.

-

R — Function reserved.

O

EMC_WE — LOW active Write Enable signal.

-

R — Function reserved.

O

EMC_BLS0 — LOW active Byte Lane select signal 0.

I/O

SGPIO14 — General purpose digital input/output pin.

I/O

SD_CMD — SD/MMC command signal.

I/O

GPIO1[0] — General purpose digital input/output pin.

I

U1_DSR — Data Set Ready input for UART1.

O

CTOUT_13 — SCT output 13. Match output 3 of timer 3.

I/O

EMC_D0 — External memory data line 0.

O

USB0_PPWR — VBUS drive signal (towards external charge
pump or power management unit); indicates that VBUS must
be driven (active HIGH).
Add a pull-down resistor to disable the power switch at reset.
This signal has opposite polarity compared to the USB_PPWR
used on other NXP LPC parts.

UM10503

User manual

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

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Chapter 16: LPC43xx/LPC43Sxx Pin configuration

P1_9

P1_10

P1_11

UM10503

User manual

71

51

T7

R8

T9

J5

H6

J7

73

75

77

52

53

55

[2]

[2]

[2]

[2]

N;
PU

N;
PU

N;
PU

N;
PU

Type

H5

Description

[1]

LQFP144

R7

Reset state

LQFP208

P1_8

TFBGA100

Pin name

LBGA256

Table 187. LPC436x/5x/3x/2x/1x, LPC43S6x/S5x/S3xpin description (flash parts) …continued

I/O

GPIO1[1] — General purpose digital input/output pin.

O

U1_DTR — Data Terminal Ready output for UART1.

O

CTOUT_12 — SCT output 12. Match output 3 of
timer 3.

I/O

EMC_D1 — External memory data line 1.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

O

SD_VOLT0 — SD/MMC bus voltage select output 0.

I/O

GPIO1[2] — General purpose digital input/output pin.

O

U1_RTS — Request to Send output for UART1.

O

CTOUT_11 — SCT output 11. Match output 3 of timer 2.

I/O

EMC_D2 — External memory data line 2.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

I/O

SD_DAT0 — SD/MMC data bus line 0.

I/O

GPIO1[3] — General purpose digital input/output pin.

I

U1_RI — Ring Indicator input for UART1.

O

CTOUT_14 — SCT output 14. Match output 2 of timer 3.

I/O

EMC_D3 — External memory data line 3.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

I/O

SD_DAT1 — SD/MMC data bus line 1.

I/O

GPIO1[4] — General purpose digital input/output pin.

I

U1_CTS — Clear to Send input for UART1.

O

CTOUT_15 — SCT output 15. Match output 3 of timer 3.

I/O

EMC_D4 — External memory data line 4.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

I/O

SD_DAT2 — SD/MMC data bus line 2.

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Chapter 16: LPC43xx/LPC43Sxx Pin configuration

P1_13

P1_14

P1_15

UM10503

User manual

78

56

R10

R11

T12

H8

J8

K8

83

85

87

60

61

62

[2]

[2]

[2]

[2]

N;
PU

N;
PU

N;
PU

N;
PU

Type

K7

Description

[1]

LQFP144

R9

Reset state

LQFP208

P1_12

TFBGA100

Pin name

LBGA256

Table 187. LPC436x/5x/3x/2x/1x, LPC43S6x/S5x/S3xpin description (flash parts) …continued

I/O

GPIO1[5] — General purpose digital input/output pin.

I

U1_DCD — Data Carrier Detect input for UART1.

-

R — Function reserved.

I/O

EMC_D5 — External memory data line 5.

I

T0_CAP1 — Capture input 1 of timer 0.

-

R — Function reserved.

I/O

SGPIO8 — General purpose digital input/output pin.

I/O

SD_DAT3 — SD/MMC data bus line 3.

I/O

GPIO1[6] — General purpose digital input/output pin.

O

U1_TXD — Transmitter output for UART1.

-

R — Function reserved.

I/O

EMC_D6 — External memory data line 6.

I

T0_CAP0 — Capture input 0 of timer 0.

-

R — Function reserved.

I/O

SGPIO9 — General purpose digital input/output pin.

I

SD_CD — SD/MMC card detect input.

I/O

GPIO1[7] — General purpose digital input/output pin.

I

U1_RXD — Receiver input for UART1.

-

R — Function reserved.

I/O

EMC_D7 — External memory data line 7.

O

T0_MAT2 — Match output 2 of timer 0.

-

R — Function reserved.

I/O

SGPIO10 — General purpose digital input/output pin.

-

R — Function reserved.

I/O

GPIO0[2] — General purpose digital input/output pin.

O

U2_TXD — Transmitter output for USART2.

I/O

SGPIO2 — General purpose digital input/output pin.

I

ENET_RXD0 — Ethernet receive data 0 (RMII/MII interface).

O

T0_MAT1 — Match output 1 of timer 0.

-

R — Function reserved.

I/O

EMC_D8 — External memory data line 8.

-

R — Function reserved.

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Chapter 16: LPC43xx/LPC43Sxx Pin configuration

P1_17

P1_18

P1_19

UM10503

User manual

90

64

M8

N12

M11

H10

J10

K9

93

95

96

66

67

68

[2]

[3]

[2]

[2]

N;
PU

N;
PU

N;
PU

N;
PU

Type

H9

Description

[1]

LQFP144

M7

Reset state

LQFP208

P1_16

TFBGA100

Pin name

LBGA256

Table 187. LPC436x/5x/3x/2x/1x, LPC43S6x/S5x/S3xpin description (flash parts) …continued

I/O

GPIO0[3] — General purpose digital input/output pin.

I

U2_RXD — Receiver input for USART2.

I/O

SGPIO3 — General purpose digital input/output pin.

I

ENET_CRS — Ethernet Carrier Sense (MII interface).

O

T0_MAT0 — Match output 0 of timer 0.

-

R — Function reserved.

I/O

EMC_D9 — External memory data line 9.

I

ENET_RX_DV — Ethernet Receive Data Valid (RMII/MII
interface).

I/O

GPIO0[12] — General purpose digital input/output pin.

I/O

U2_UCLK — Serial clock input/output for USART2 in
synchronous mode.

-

R — Function reserved.

I/O

ENET_MDIO — Ethernet MIIM data input and output.

I

T0_CAP3 — Capture input 3 of timer 0.

O

CAN1_TD — CAN1 transmitter output.

I/O

SGPIO11 — General purpose digital input/output pin.

-

R — Function reserved.

I/O

GPIO0[13] — General purpose digital input/output pin.

I/O

U2_DIR — RS-485/EIA-485 output enable/direction control for
USART2.

-

R — Function reserved.

O

ENET_TXD0 — Ethernet transmit data 0 (RMII/MII interface).

O

T0_MAT3 — Match output 3 of timer 0.

I

CAN1_RD — CAN1 receiver input.

I/O

SGPIO12 — General purpose digital input/output pin.

I/O

EMC_D10 — External memory data line 10.

I

ENET_TX_CLK (ENET_REF_CLK) — Ethernet Transmit
Clock (MII interface) or Ethernet Reference Clock (RMII
interface).

I/O

SSP1_SCK — Serial clock for SSP1.

-

R — Function reserved.

-

R — Function reserved.

O

CLKOUT — Clock output pin.

-

R — Function reserved.

O

I2S0_RX_MCLK — I2S receive master clock.

I/O

I2S1_TX_SCK — Transmit Clock. It is driven by the master
and received by the slave. Corresponds to the signal SCK in
the I2S-bus specification.

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NXP Semiconductors

Chapter 16: LPC43xx/LPC43Sxx Pin configuration

P2_0

100

70

T16

G10

108

75

[2]

[2]

N;
PU

N;
PU

Type

K10

Description

[1]

LQFP144

M10

Reset state

LQFP208

P1_20

TFBGA100

Pin name

LBGA256

Table 187. LPC436x/5x/3x/2x/1x, LPC43S6x/S5x/S3xpin description (flash parts) …continued

I/O

GPIO0[15] — General purpose digital input/output pin.

I/O

SSP1_SSEL — Slave Select for SSP1.

-

R — Function reserved.

O

ENET_TXD1 — Ethernet transmit data 1 (RMII/MII interface).

I

T0_CAP2 — Capture input 2 of timer 0.

-

R — Function reserved.

I/O

SGPIO13 — General purpose digital input/output pin.

I/O

EMC_D11 — External memory data line 11.

I/O

SGPIO4 — General purpose digital input/output pin.

O

U0_TXD — Transmitter output for USART0. See Table 21 for
ISP mode.

I/O

EMC_A13 — External memory address line 13.

O

USB0_PPWR — VBUS drive signal (towards external charge
pump or power management unit); indicates that VBUS must
be driven (active HIGH).
Add a pull-down resistor to disable the power switch at reset.
This signal has opposite polarity compared to the USB_PPWR
used on other NXP LPC parts.

P2_1

UM10503

User manual

N15

G7

116

81

[2]

N;
PU

I/O

GPIO5[0] — General purpose digital input/output pin.

-

R — Function reserved.

I

T3_CAP0 — Capture input 0 of timer 3.

O

ENET_MDC — Ethernet MIIM clock.

I/O

SGPIO5 — General purpose digital input/output pin.

I

U0_RXD — Receiver input for USART0. See Table 21 for ISP
mode.

I/O

EMC_A12 — External memory address line 12.

I

USB0_PWR_FAULT — Port power fault signal indicating
overcurrent condition; this signal monitors over-current on the
USB bus (external circuitry required to detect over-current
condition).

I/O

GPIO5[1] — General purpose digital input/output pin.

-

R — Function reserved.

I

T3_CAP1 — Capture input 1 of timer 3.

-

R — Function reserved.

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NXP Semiconductors

Chapter 16: LPC43xx/LPC43Sxx Pin configuration

P2_3

121

84

J12

D8

127

87

[2]

[3]

N;
PU

N;
PU

Type

F5

Description

[1]

LQFP144

M15

Reset state

LQFP208

P2_2

TFBGA100

Pin name

LBGA256

Table 187. LPC436x/5x/3x/2x/1x, LPC43S6x/S5x/S3xpin description (flash parts) …continued

I/O

SGPIO6 — General purpose digital input/output pin.

I/O

U0_UCLK — Serial clock input/output for USART0 in
synchronous mode.

I/O

EMC_A11 — External memory address line 11.

O

USB0_IND1 — USB0 port indicator LED control output 1.

I/O

GPIO5[2] — General purpose digital input/output pin.

I

CTIN_6 — SCT input 6. Capture input 1 of timer 3.

I

T3_CAP2 — Capture input 2 of timer 3.

O

EMC_CS1 — LOW active Chip Select 1 signal.

I/O

SGPIO12 — General purpose digital input/output pin.

I/O

I2C1_SDA — I2C1 data input/output (this pin does not use a
specialized I2C pad).

O

U3_TXD — Transmitter output for USART3. See Table 21 for
ISP mode.

I

CTIN_1 — SCT input 1. Capture input 1 of timer 0. Capture
input 1 of timer 2.

I/O

GPIO5[3] — General purpose digital input/output pin.

-

R — Function reserved.

O

T3_MAT0 — Match output 0 of timer 3.

O

USB0_PPWR — VBUS drive signal (towards external charge
pump or power management unit); indicates that VBUS must
be driven (active HIGH).
Add a pull-down resistor to disable the power switch at reset.
This signal has opposite polarity compared to the USB_PPWR
used on other NXP LPC parts.

P2_4

UM10503

User manual

K11

D9

128

88

[3]

N;
PU

I/O

SGPIO13 — General purpose digital input/output pin.

I/O

I2C1_SCL — I2C1 clock input/output (this pin does not use a
specialized I2C pad).

I

U3_RXD — Receiver input for USART3. See Table 21 for ISP
mode.

I

CTIN_0 — SCT input 0. Capture input 0 of timer 0, 1, 2, 3.

I/O

GPIO5[4] — General purpose digital input/output pin.

-

R — Function reserved.

O

T3_MAT1 — Match output 1 of timer 3.

I

USB0_PWR_FAULT — Port power fault signal indicating
overcurrent condition; this signal monitors over-current on the
USB bus (external circuitry required to detect over-current
condition).

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358 of 1444

UM10503

NXP Semiconductors

Chapter 16: LPC43xx/LPC43Sxx Pin configuration

131

91

[3]

N;
PU

Type

D10

Description

[1]

LQFP144

K14

Reset state

LQFP208

P2_5

TFBGA100

Pin name

LBGA256

Table 187. LPC436x/5x/3x/2x/1x, LPC43S6x/S5x/S3xpin description (flash parts) …continued

I/O

SGPIO14 — General purpose digital input/output pin.

I

CTIN_2 — SCT input 2. Capture input 2 of timer 0.

I

USB1_VBUS — Monitors the presence of USB1 bus power.
Note: This signal must be HIGH for USB reset to occur.

P2_6

P2_7

P2_8

UM10503

User manual

K16

H14

J16

G9

C10

C6

137

138

140

95

96

98

[2]

[2]

[2]

N;
PU

N;
PU

N;
PU

I

ADCTRIG1 — ADC trigger input 1.

I/O

GPIO5[5] — General purpose digital input/output pin.

-

R — Function reserved.

O

T3_MAT2 — Match output 2 of timer 3.

O

USB0_IND0 — USB0 port indicator LED control output 0.

I/O

SGPIO7 — General purpose digital input/output pin.

I/O

U0_DIR — RS-485/EIA-485 output enable/direction control for
USART0.

I/O

EMC_A10 — External memory address line 10.

O

USB0_IND0 — USB0 port indicator LED control
output 0.

I/O

GPIO5[6] — General purpose digital input/output pin.

I

CTIN_7 — SCT input 7.

I

T3_CAP3 — Capture input 3 of timer 3.

O

EMC_BLS1 — LOW active Byte Lane select signal 1.

I/O

GPIO0[7] — General purpose digital input/output pin. If this
pin is pulled LOW at reset, the part enters ISP mode or boots
from an external source (see Table 21 and Table 22).

O

CTOUT_1 — SCT output 1. Match output 3 of timer 3.

I/O

U3_UCLK — Serial clock input/output for USART3 in
synchronous mode.

I/O

EMC_A9 — External memory address line 9.

-

R — Function reserved.

-

R — Function reserved.

O

T3_MAT3 — Match output 3 of timer 3.

-

R — Function reserved.

I/O

SGPIO15 — General purpose digital input/output pin. Boot pin
(see Table 22).

O

CTOUT_0 — SCT output 0. Match output 0 of timer 0.

I/O

U3_DIR — RS-485/EIA-485 output enable/direction control for
USART3.

I/O

EMC_A8 — External memory address line 8.

I/O

GPIO5[7] — General purpose digital input/output pin.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

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Rev. 2.4 — 22 August 2018

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NXP Semiconductors

Chapter 16: LPC43xx/LPC43Sxx Pin configuration

P2_10

P2_11

P2_12

UM10503

User manual

144

102

G16

F16

E15

E8

A9

B9

146

148

153

104

105

106

[2]

[2]

[2]

[2]

N;
PU

N;
PU

N;
PU

N;
PU

Type

B10

Description

[1]

LQFP144

H16

Reset state

LQFP208

P2_9

TFBGA100

Pin name

LBGA256

Table 187. LPC436x/5x/3x/2x/1x, LPC43S6x/S5x/S3xpin description (flash parts) …continued

I/O

GPIO1[10] — General purpose digital input/output pin. Boot
pin (see Table 22).

O

CTOUT_3 — SCT output 3. Match output 3 of timer 0.

I/O

U3_BAUD — Baud pin for USART3.

I/O

EMC_A0 — External memory address line 0.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

I/O

GPIO0[14] — General purpose digital input/output pin.

O

CTOUT_2 — SCT output 2. Match output 2 of timer 0.

O

U2_TXD — Transmitter output for USART2.

I/O

EMC_A1 — External memory address line 1.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

I/O

GPIO1[11] — General purpose digital input/output pin.

O

CTOUT_5 — SCT output 5. Match output 3 of timer 3.

I

U2_RXD — Receiver input for USART2.

I/O

EMC_A2 — External memory address line 2.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

I/O

GPIO1[12] — General purpose digital input/output pin.

O

CTOUT_4 — SCT output 4. Match output 3 of timer 3.

-

R — Function reserved.

I/O

EMC_A3 — External memory address line 3.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

I/O

U2_UCLK — Serial clock input/output for USART2 in
synchronous mode.

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Rev. 2.4 — 22 August 2018

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360 of 1444

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NXP Semiconductors

Chapter 16: LPC43xx/LPC43Sxx Pin configuration

P3_0

P3_1

UM10503

User manual

156

108

F13

G11

A8

F7

161

163

112

114

[2]

[2]

[2]

N;
PU

N;
PU

N;
PU

Type

A10

Description

[1]

LQFP144

C16

Reset state

LQFP208

P2_13

TFBGA100

Pin name

LBGA256

Table 187. LPC436x/5x/3x/2x/1x, LPC43S6x/S5x/S3xpin description (flash parts) …continued

I/O

GPIO1[13] — General purpose digital input/output pin.

I

CTIN_4 — SCT input 4. Capture input 2 of timer 1.

-

R — Function reserved.

I/O

EMC_A4 — External memory address line 4.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

I/O

U2_DIR — RS-485/EIA-485 output enable/direction control for
USART2.

I/O

I2S0_RX_SCK — I2S receive clock. It is driven by the master
and received by the slave. Corresponds to the signal SCK in
the I2S-bus specification.

O

I2S0_RX_MCLK — I2S receive master clock.

I/O

I2S0_TX_SCK — Transmit Clock. It is driven by the master
and received by the slave. Corresponds to the signal SCK in
the I2S-bus specification.

O

I2S0_TX_MCLK — I2S transmit master clock.

I/O

SSP0_SCK — Serial clock for SSP0.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

I/O

I2S0_TX_WS — Transmit Word Select. It is driven by the
master and received by the slave. Corresponds to the signal
WS in the I2S-bus specification.

I/O

I2S0_RX_WS — Receive Word Select. It is driven by the
master and received by the slave. Corresponds to the signal
WS in the I2S-bus specification.

I

CAN0_RD — CAN receiver input.

O

USB1_IND1 — USB1 Port indicator LED control output 1.

I/O

GPIO5[8] — General purpose digital input/output pin.

-

R — Function reserved.

O

LCD_VD15 — LCD data.

-

R — Function reserved.

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Rev. 2.4 — 22 August 2018

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361 of 1444

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NXP Semiconductors

Chapter 16: LPC43xx/LPC43Sxx Pin configuration

P3_3

P3_4

UM10503

User manual

166

116

B14

A15

A7

B8

169

171

118

119

[2]

[4]

[2]

OL;
PU

N;
PU

N;
PU

Type

G6

Description

[1]

LQFP144

F11

Reset state

LQFP208

P3_2

TFBGA100

Pin name

LBGA256

Table 187. LPC436x/5x/3x/2x/1x, LPC43S6x/S5x/S3xpin description (flash parts) …continued

I/O

I2S0_TX_SDA — I2S transmit data. It is driven by the
transmitter and read by the receiver. Corresponds to the signal
SD in the I2S-bus specification.

I/O

I2S0_RX_SDA — I2S Receive data. It is driven by the
transmitter and read by the receiver. Corresponds to the signal
SD in the I2S-bus specification.

O

CAN0_TD — CAN transmitter output.

O

USB1_IND0 — USB1 Port indicator LED control output 0.

I/O

GPIO5[9] — General purpose digital input/output pin.

-

R — Function reserved.

O

LCD_VD14 — LCD data.

-

R — Function reserved.

-

R — Function reserved.

I/O

SPI_SCK — Serial clock for SPI.

I/O

SSP0_SCK — Serial clock for SSP0.

O

SPIFI_SCK — Serial clock for SPIFI.

O

CGU_OUT1 — CGU spare clock output 1.

-

R — Function reserved.

O

I2S0_TX_MCLK — I2S transmit master clock.

I/O

I2S1_TX_SCK — Transmit Clock. It is driven by the master
and received by the slave. Corresponds to the signal SCK in
the I2S-bus specification.

I/O

GPIO1[14] — General purpose digital input/output pin.

-

R — Function reserved.

-

R — Function reserved.

I/O

SPIFI_SIO3 — I/O lane 3 for SPIFI.

O

U1_TXD — Transmitter output for UART 1.

I/O

I2S0_TX_WS — Transmit Word Select. It is driven by the
master and received by the slave. Corresponds to the signal
WS in the I2S-bus specification.

I/O

I2S1_RX_SDA — I2S1 Receive data. It is driven by the
transmitter and read by the receiver. Corresponds to the signal
SD in the I2S-bus specification.

O

LCD_VD13 — LCD data.

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Rev. 2.4 — 22 August 2018

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362 of 1444

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NXP Semiconductors

Chapter 16: LPC43xx/LPC43Sxx Pin configuration

P3_6

P3_7

P3_8

UM10503

User manual

173

121

B13

C11

C10

C7

D7

E7

174

176

179

122

123

124

[2]

[2]

[2]

[2]

N;
PU

N;
PU

N;
PU

N;
PU

Type

B7

Description

[1]

LQFP144

C12

Reset state

LQFP208

P3_5

TFBGA100

Pin name

LBGA256

Table 187. LPC436x/5x/3x/2x/1x, LPC43S6x/S5x/S3xpin description (flash parts) …continued

I/O

GPIO1[15] — General purpose digital input/output pin.

-

R — Function reserved.

-

R — Function reserved.

I/O

SPIFI_SIO2 — I/O lane 2 for SPIFI.

I

U1_RXD — Receiver input for UART 1.

I/O

I2S0_TX_SDA — I2S transmit data. It is driven by the
transmitter and read by the receiver. Corresponds to the signal
SD in the I2S-bus specification.

I/O

I2S1_RX_WS — Receive Word Select. It is driven by the
master and received by the slave. Corresponds to the signal
WS in the I2S-bus specification.

O

LCD_VD12 — LCD data.

I/O

GPIO0[6] — General purpose digital input/output pin.

I/O

SPI_MISO — Master In Slave Out for SPI.

I/O

SSP0_SSEL — Slave Select for SSP0.

I/O

SPIFI_MISO — Input 1 in SPIFI quad mode; SPIFI output IO1.

-

R — Function reserved.

I/O

SSP0_MISO — Master In Slave Out for SSP0.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

I/O

SPI_MOSI — Master Out Slave In for SPI.

I/O

SSP0_MISO — Master In Slave Out for SSP0.

I/O

SPIFI_MOSI — Input I0 in SPIFI quad mode; SPIFI output
IO0.

I/O

GPIO5[10] — General purpose digital input/output pin.

I/O

SSP0_MOSI — Master Out Slave in for SSP0.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

I

SPI_SSEL — Slave Select for SPI. Note that this pin in an
input pin only. The SPI in master mode cannot drive the CS
input on the slave. Any GPIO pin can be used for SPI chip
select in master mode.

I/O

SSP0_MOSI — Master Out Slave in for SSP0.

I/O

SPIFI_CS — SPIFI serial flash chip select.

I/O

GPIO5[11] — General purpose digital input/output pin.

I/O

SSP0_SSEL — Slave Select for SSP0.

-

R — Function reserved.

-

R — Function reserved.

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Rev. 2.4 — 22 August 2018

© NXP B.V. 2018. All rights reserved.

363 of 1444

UM10503

NXP Semiconductors

Chapter 16: LPC43xx/LPC43Sxx Pin configuration

P4_1

P4_2

P4_3

UM10503

User manual

1

1

A1

D3

C2

-

-

-

3

12

10

3

8

7

[2]

[5]

[2]

[5]

N;
PU

N;
PU

N;
PU

N;
PU

Type

-

Description

[1]

LQFP144

D5

Reset state

LQFP208

P4_0

TFBGA100

Pin name

LBGA256

Table 187. LPC436x/5x/3x/2x/1x, LPC43S6x/S5x/S3xpin description (flash parts) …continued

I/O

GPIO2[0] — General purpose digital input/output pin.

O

MCOA0 — Motor control PWM channel 0, output A.

I

NMI — External interrupt input to NMI.

-

R — Function reserved.

-

R — Function reserved.

O

LCD_VD13 — LCD data.

I/O

U3_UCLK — Serial clock input/output for USART3 in
synchronous mode.

-

R — Function reserved.

I/O

GPIO2[1] — General purpose digital input/output pin.

O

CTOUT_1 — SCT output 1. Match output 3 of timer 3.

O

LCD_VD0 — LCD data.

-

R — Function reserved.

-

R — Function reserved.

O

LCD_VD19 — LCD data.

O

U3_TXD — Transmitter output for USART3.

I

ENET_COL — Ethernet Collision detect (MII interface).

AI

ADC0_1 — ADC0 and ADC1, input channel 1. Configure the
pin as GPIO input and use the ADC function select register in
the SCU to select the ADC.

I/O

GPIO2[2] — General purpose digital input/output pin.

O

CTOUT_0 — SCT output 0. Match output 0 of timer 0.

O

LCD_VD3 — LCD data.

-

R — Function reserved.

-

R — Function reserved.

O

LCD_VD12 — LCD data.

I

U3_RXD — Receiver input for USART3.

I/O

SGPIO8 — General purpose digital input/output pin.

I/O

GPIO2[3] — General purpose digital input/output pin.

O

CTOUT_3 — SCT output 3. Match output 3 of timer 0.

O

LCD_VD2 — LCD data.

-

R — Function reserved.

-

R — Function reserved.

O

LCD_VD21 — LCD data.

I/O

U3_BAUD — Baud pin for USART3.

I/O

SGPIO9 — General purpose digital input/output pin.

AI

ADC0_0 — DAC, ADC0 and ADC1, input channel 0.
Configure the pin as GPIO input and use the ADC function
select register in the SCU to select the ADC.

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Rev. 2.4 — 22 August 2018

© NXP B.V. 2018. All rights reserved.

364 of 1444

UM10503

NXP Semiconductors

Chapter 16: LPC43xx/LPC43Sxx Pin configuration

P4_5

P4_6

UM10503

User manual

14

9

D2

C1

-

-

15

17

10

11

[5]

[2]

[2]

N;
PU

N;
PU

N;
PU

Type

-

Description

[1]

LQFP144

B1

Reset state

LQFP208

P4_4

TFBGA100

Pin name

LBGA256

Table 187. LPC436x/5x/3x/2x/1x, LPC43S6x/S5x/S3xpin description (flash parts) …continued

I/O

GPIO2[4] — General purpose digital input/output pin.

O

CTOUT_2 — SCT output 2. Match output 2 of timer 0.

O

LCD_VD1 — LCD data.

-

R — Function reserved.

-

R — Function reserved.

O

LCD_VD20 — LCD data.

I/O

U3_DIR — RS-485/EIA-485 output enable/direction control for
USART3.

I/O

SGPIO10 — General purpose digital input/output pin.

O

DAC — DAC output. Configure the pin as GPIO input and use
the analog function select register in the SCU to select the
DAC.

I/O

GPIO2[5] — General purpose digital input/output pin.

O

CTOUT_5 — SCT output 5. Match output 3 of timer 3.

O

LCD_FP — Frame pulse (STN). Vertical synchronization
pulse (TFT).

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

I/O

SGPIO11 — General purpose digital input/output pin.

I/O

GPIO2[6] — General purpose digital input/output pin.

O

CTOUT_4 — SCT output 4. Match output 3 of timer 3.

O

LCD_ENAB/LCDM — STN AC bias drive or TFT data enable
input.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

I/O

SGPIO12 — General purpose digital input/output pin.

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Rev. 2.4 — 22 August 2018

© NXP B.V. 2018. All rights reserved.

365 of 1444

UM10503

NXP Semiconductors

Chapter 16: LPC43xx/LPC43Sxx Pin configuration

P4_8

P4_9

P4_10

UM10503

User manual

21

14

E2

L2

M3

-

-

-

23

48

51

15

33

35

[2]

[2]

[2]

[2]

O;
PU

N;
PU

N;
PU

N;
PU

Type

-

Description

[1]

LQFP144

H4

Reset state

LQFP208

P4_7

TFBGA100

Pin name

LBGA256

Table 187. LPC436x/5x/3x/2x/1x, LPC43S6x/S5x/S3xpin description (flash parts) …continued

O

LCD_DCLK — LCD panel clock.

I

GP_CLKIN — General purpose clock input to the CGU.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

I/O

I2S1_TX_SCK — Transmit Clock. It is driven by the master
and received by the slave. Corresponds to the signal SCK in
the I2S-bus specification.

I/O

I2S0_TX_SCK — Transmit Clock. It is driven by the master
and received by the slave. Corresponds to the signal SCK in
the I2S-bus specification.

-

R — Function reserved.

I

CTIN_5 — SCT input 5. Capture input 2 of timer 2.

O

LCD_VD9 — LCD data.

-

R — Function reserved.

I/O

GPIO5[12] — General purpose digital input/output pin.

O

LCD_VD22 — LCD data.

O

CAN1_TD — CAN1 transmitter output.

I/O

SGPIO13 — General purpose digital input/output pin.

-

R — Function reserved.

I

CTIN_6 — SCT input 6. Capture input 1 of timer 3.

O

LCD_VD11 — LCD data.

-

R — Function reserved.

I/O

GPIO5[13] — General purpose digital input/output pin.

O

LCD_VD15 — LCD data.

I

CAN1_RD — CAN1 receiver input.

I/O

SGPIO14 — General purpose digital input/output pin.

-

R — Function reserved.

I

CTIN_2 — SCT input 2. Capture input 2 of timer 0.

O

LCD_VD10 — LCD data.

-

R — Function reserved.

I/O

GPIO5[14] — General purpose digital input/output pin.

O

LCD_VD14 — LCD data.

-

R — Function reserved.

I/O

SGPIO15 — General purpose digital input/output pin.

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Rev. 2.4 — 22 August 2018

© NXP B.V. 2018. All rights reserved.

366 of 1444

UM10503

NXP Semiconductors

Chapter 16: LPC43xx/LPC43Sxx Pin configuration

P5_1

P5_2

P5_3

UM10503

User manual

53

37

P3

R4

T8

-

-

-

55

63

76

39

46

54

[2]

[2]

[2]

[2]

N;
PU

N;
PU

N;
PU

N;
PU

Type

-

Description

[1]

LQFP144

N3

Reset state

LQFP208

P5_0

TFBGA100

Pin name

LBGA256

Table 187. LPC436x/5x/3x/2x/1x, LPC43S6x/S5x/S3xpin description (flash parts) …continued

I/O

GPIO2[9] — General purpose digital input/output pin.

O

MCOB2 — Motor control PWM channel 2, output B.

I/O

EMC_D12 — External memory data line 12.

-

R — Function reserved.

I

U1_DSR — Data Set Ready input for UART 1.

I

T1_CAP0 — Capture input 0 of timer 1.

-

R — Function reserved.

-

R — Function reserved.

I/O

GPIO2[10] — General purpose digital input/output pin.

I

MCI2 — Motor control PWM channel 2, input.

I/O

EMC_D13 — External memory data line 13.

-

R — Function reserved.

O

U1_DTR — Data Terminal Ready output for UART 1. Can also
be configured to be an RS-485/EIA-485 output enable signal
for UART 1.

I

T1_CAP1 — Capture input 1 of timer 1.

-

R — Function reserved.

-

R — Function reserved.

I/O

GPIO2[11] — General purpose digital input/output pin.

I

MCI1 — Motor control PWM channel 1, input.

I/O

EMC_D14 — External memory data line 14.

-

R — Function reserved.

O

U1_RTS — Request to Send output for UART 1. Can also be
configured to be an RS-485/EIA-485 output enable signal for
UART 1.

I

T1_CAP2 — Capture input 2 of timer 1.

-

R — Function reserved.

-

R — Function reserved.

I/O

GPIO2[12] — General purpose digital input/output pin.

I

MCI0 — Motor control PWM channel 0, input.

I/O

EMC_D15 — External memory data line 15.

-

R — Function reserved.

I

U1_RI — Ring Indicator input for UART 1.

I

T1_CAP3 — Capture input 3 of timer 1.

-

R — Function reserved.

-

R — Function reserved.

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Rev. 2.4 — 22 August 2018

© NXP B.V. 2018. All rights reserved.

367 of 1444

UM10503

NXP Semiconductors

Chapter 16: LPC43xx/LPC43Sxx Pin configuration

P5_5

P5_6

P5_7

UM10503

User manual

80

57

P10

T13

R12

-

-

-

81

89

91

58

63

65

[2]

[2]

[2]

[2]

N;
PU

N;
PU

N;
PU

N;
PU

Type

-

Description

[1]

LQFP144

P9

Reset state

LQFP208

P5_4

TFBGA100

Pin name

LBGA256

Table 187. LPC436x/5x/3x/2x/1x, LPC43S6x/S5x/S3xpin description (flash parts) …continued

I/O

GPIO2[13] — General purpose digital input/output pin.

O

MCOB0 — Motor control PWM channel 0, output B.

I/O

EMC_D8 — External memory data line 8.

-

R — Function reserved.

I

U1_CTS — Clear to Send input for UART 1.

O

T1_MAT0 — Match output 0 of timer 1.

-

R — Function reserved.

-

R — Function reserved.

I/O

GPIO2[14] — General purpose digital input/output pin.

O

MCOA1 — Motor control PWM channel 1, output A.

I/O

EMC_D9 — External memory data line 9.

-

R — Function reserved.

I

U1_DCD — Data Carrier Detect input for UART 1.

O

T1_MAT1 — Match output 1 of timer 1.

-

R — Function reserved.

-

R — Function reserved.

I/O

GPIO2[15] — General purpose digital input/output pin.

O

MCOB1 — Motor control PWM channel 1, output B.

I/O

EMC_D10 — External memory data line 10.

-

R — Function reserved.

O

U1_TXD — Transmitter output for UART 1.

O

T1_MAT2 — Match output 2 of timer 1.

-

R — Function reserved.

-

R — Function reserved.

I/O

GPIO2[7] — General purpose digital input/output pin.

O

MCOA2 — Motor control PWM channel 2, output A.

I/O

EMC_D11 — External memory data line 11.

-

R — Function reserved.

I

U1_RXD — Receiver input for UART 1.

O

T1_MAT3 — Match output 3 of timer 1.

-

R — Function reserved.

-

R — Function reserved.

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NXP Semiconductors

Chapter 16: LPC43xx/LPC43Sxx Pin configuration

P6_1

P6_2

UM10503

User manual

105

73

R15

L13

G5

J9

107

111

74

78

[2]

[2]

[2]

N;
PU

N;
PU

N;
PU

Type

H7

Description

[1]

LQFP144

M12

Reset state

LQFP208

P6_0

TFBGA100

Pin name

LBGA256

Table 187. LPC436x/5x/3x/2x/1x, LPC43S6x/S5x/S3xpin description (flash parts) …continued

-

R — Function reserved.

O

I2S0_RX_MCLK — I2S receive master clock.

-

R — Function reserved.

-

R — Function reserved.

I/O

I2S0_RX_SCK — Receive Clock. It is driven by the master
and received by the slave. Corresponds to the signal SCK in
the I2S-bus specification.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

I/O

GPIO3[0] — General purpose digital input/output pin.

O

EMC_DYCS1 — SDRAM chip select 1.

I/O

U0_UCLK — Serial clock input/output for USART0 in
synchronous mode.

I/O

I2S0_RX_WS — Receive Word Select. It is driven by the
master and received by the slave. Corresponds to the signal
WS in the I2S-bus specification.

-

R — Function reserved.

I

T2_CAP0 — Capture input 0 of timer 2.

-

R — Function reserved.

-

R — Function reserved.

I/O

GPIO3[1] — General purpose digital input/output pin.

O

EMC_CKEOUT1 — SDRAM clock enable 1.

I/O

U0_DIR — RS-485/EIA-485 output enable/direction control for
USART0.

I/O

I2S0_RX_SDA — I2S Receive data. It is driven by the
transmitter and read by the receiver. Corresponds to the signal
SD in the I2S-bus specification.

-

R — Function reserved.

I

T2_CAP1 — Capture input 1 of timer 2.

-

R — Function reserved.

-

R — Function reserved.

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369 of 1444

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NXP Semiconductors

Chapter 16: LPC43xx/LPC43Sxx Pin configuration

113

79

[2]

N;
PU

Type

-

Description

[1]

LQFP144

P15

Reset state

LQFP208

P6_3

TFBGA100

Pin name

LBGA256

Table 187. LPC436x/5x/3x/2x/1x, LPC43S6x/S5x/S3xpin description (flash parts) …continued

I/O

GPIO3[2] — General purpose digital input/output pin.

O

USB0_PPWR — VBUS drive signal (towards external charge
pump or power management unit); indicates that the VBUS
signal must be driven (active HIGH).
Add a pull-down resistor to disable the power switch at reset.
This signal has opposite polarity compared to the USB_PPWR
used on other NXP LPC parts.

P6_4

P6_5

P6_6

UM10503

User manual

R16

P16

L14

F6

F9

-

114

117

119

80

82

83

[2]

[2]

[2]

N;
PU

N;
PU

N;
PU

I/O

SGPIO4 — General purpose digital input/output pin.

O

EMC_CS1 — LOW active Chip Select 1 signal.

-

R — Function reserved.

I

T2_CAP2 — Capture input 2 of timer 2.

-

R — Function reserved.

-

R — Function reserved.

I/O

GPIO3[3] — General purpose digital input/output pin.

I

CTIN_6 — SCT input 6. Capture input 1 of timer 3.

O

U0_TXD — Transmitter output for USART0.

O

EMC_CAS — LOW active SDRAM Column Address Strobe.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

I/O

GPIO3[4] — General purpose digital input/output pin.

O

CTOUT_6 — SCT output 6. Match output 2 of timer 1.

I

U0_RXD — Receiver input for USART0.

O

EMC_RAS — LOW active SDRAM Row Address Strobe.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

I/O

GPIO0[5] — General purpose digital input/output pin.

O

EMC_BLS1 — LOW active Byte Lane select signal 1.

I/O

SGPIO5 — General purpose digital input/output pin.

I

USB0_PWR_FAULT — Port power fault signal indicating
overcurrent condition; this signal monitors over-current on the
USB bus (external circuitry required to detect over-current
condition).

-

R — Function reserved.

I

T2_CAP3 — Capture input 3 of timer 2.

-

R — Function reserved.

-

R — Function reserved.

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NXP Semiconductors

Chapter 16: LPC43xx/LPC43Sxx Pin configuration

P6_8

P6_9

P6_10

UM10503

User manual

123

85

H13

J15

H15

-

F8

-

125

139

142

86

97

100

[2]

[2]

[2]

[2]

N;
PU

N;
PU

N;
PU

N;
PU

Type

-

Description

[1]

LQFP144

J13

Reset state

LQFP208

P6_7

TFBGA100

Pin name

LBGA256

Table 187. LPC436x/5x/3x/2x/1x, LPC43S6x/S5x/S3xpin description (flash parts) …continued

-

R — Function reserved.

I/O

EMC_A15 — External memory address line 15.

I/O

SGPIO6 — General purpose digital input/output pin.

O

USB0_IND1 — USB0 port indicator LED control output 1.

I/O

GPIO5[15] — General purpose digital input/output pin.

O

T2_MAT0 — Match output 0 of timer 2.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

I/O

EMC_A14 — External memory address line 14.

I/O

SGPIO7 — General purpose digital input/output pin.

O

USB0_IND0 — USB0 port indicator LED control output 0.

I/O

GPIO5[16] — General purpose digital input/output pin.

O

T2_MAT1 — Match output 1 of timer 2.

-

R — Function reserved.

-

R — Function reserved.

I/O

GPIO3[5] — General purpose digital input/output pin.

-

R — Function reserved.

-

R — Function reserved.

O

EMC_DYCS0 — SDRAM chip select 0.

-

R — Function reserved.

O

T2_MAT2 — Match output 2 of timer 2.

-

R — Function reserved.

-

R — Function reserved.

I/O

GPIO3[6] — General purpose digital input/output pin.

O

MCABORT — Motor control PWM, LOW-active fast abort.

-

R — Function reserved.

O

EMC_DQMOUT1 — Data mask 1 used with SDRAM and
static devices.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

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Rev. 2.4 — 22 August 2018

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371 of 1444

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NXP Semiconductors

Chapter 16: LPC43xx/LPC43Sxx Pin configuration

P6_12

P7_0

P7_1

UM10503

User manual

143

101

G15

B16

C14

-

-

-

145

158

162

103

110

113

[2]

[2]

[2]

[2]

N;
PU

N;
PU

N;
PU

N;
PU

Type

C9

Description

[1]

LQFP144

H12

Reset state

LQFP208

P6_11

TFBGA100

Pin name

LBGA256

Table 187. LPC436x/5x/3x/2x/1x, LPC43S6x/S5x/S3xpin description (flash parts) …continued

I/O

GPIO3[7] — General purpose digital input/output pin.

-

R — Function reserved.

-

R — Function reserved.

O

EMC_CKEOUT0 — SDRAM clock enable 0.

-

R — Function reserved.

O

T2_MAT3 — Match output 3 of timer 2.

-

R — Function reserved.

-

R — Function reserved.

I/O

GPIO2[8] — General purpose digital input/output pin.

O

CTOUT_7 — SCT output 7. Match output 3 of timer 1.

-

R — Function reserved.

O

EMC_DQMOUT0 — Data mask 0 used with SDRAM and
static devices.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

I/O

GPIO3[8] — General purpose digital input/output pin.

O

CTOUT_14 — SCT output 14. Match output 2 of timer 3.

-

R — Function reserved.

O

LCD_LE — Line end signal.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

I/O

SGPIO4 — General purpose digital input/output pin.

I/O

GPIO3[9] — General purpose digital input/output pin.

O

CTOUT_15 — SCT output 15. Match output 3 of timer 3.

I/O

I2S0_TX_WS — Transmit Word Select. It is driven by the
master and received by the slave. Corresponds to the signal
WS in the I2S-bus specification.

O

LCD_VD19 — LCD data.

O

LCD_VD7 — LCD data.

-

R — Function reserved.

O

U2_TXD — Transmitter output for USART2.

I/O

SGPIO5 — General purpose digital input/output pin.

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Rev. 2.4 — 22 August 2018

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UM10503

NXP Semiconductors

Chapter 16: LPC43xx/LPC43Sxx Pin configuration

P7_3

P7_4

P7_5

UM10503

User manual

165

115

C13

C8

A7

-

-

-

167

189

191

117

132

133

[2]

[2]

[5]

[5]

N;
PU

N;
PU

N;
PU

N;
PU

Type

-

Description

[1]

LQFP144

A16

Reset state

LQFP208

P7_2

TFBGA100

Pin name

LBGA256

Table 187. LPC436x/5x/3x/2x/1x, LPC43S6x/S5x/S3xpin description (flash parts) …continued

I/O

GPIO3[10] — General purpose digital input/output pin.

I

CTIN_4 — SCT input 4. Capture input 2 of timer 1.

I/O

I2S0_TX_SDA — I2S transmit data. It is driven by the
transmitter and read by the receiver. Corresponds to the signal
SD in the I2S-bus specification.

O

LCD_VD18 — LCD data.

O

LCD_VD6 — LCD data.

-

R — Function reserved.

I

U2_RXD — Receiver input for USART2.

I/O

SGPIO6 — General purpose digital input/output pin.

I/O

GPIO3[11] — General purpose digital input/output pin.

I

CTIN_3 — SCT input 3. Capture input 1 of timer 1.

-

R — Function reserved.

O

LCD_VD17 — LCD data.

O

LCD_VD5 — LCD data.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

I/O

GPIO3[12] — General purpose digital input/output pin.

O

CTOUT_13 — SCT output 13. Match output 3 of timer 3.

-

R — Function reserved.

O

LCD_VD16 — LCD data.

O

LCD_VD4 — LCD data.

O

TRACEDATA[0] — Trace data, bit 0.

-

R — Function reserved.

-

R — Function reserved.

AI

ADC0_4 — ADC0 and ADC1, input channel 4. Configure the
pin as GPIO input and use the ADC function select register in
the SCU to select the ADC.

I/O

GPIO3[13] — General purpose digital input/output pin.

O

CTOUT_12 — SCT output 12. Match output 3 of timer 3.

-

R — Function reserved.

O

LCD_VD8 — LCD data.

O

LCD_VD23 — LCD data.

O

TRACEDATA[1] — Trace data, bit 1.

-

R — Function reserved.

-

R — Function reserved.

AI

ADC0_3 — ADC0 and ADC1, input channel 3. Configure the
pin as GPIO input and use the ADC function select register in
the SCU to select the ADC.

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Rev. 2.4 — 22 August 2018

© NXP B.V. 2018. All rights reserved.

373 of 1444

UM10503

NXP Semiconductors

Chapter 16: LPC43xx/LPC43Sxx Pin configuration

P7_7

P8_0

P8_1

UM10503

User manual

194

134

B6

E5

H5

-

-

-

201

2

34

140

-

-

[2]

[5]

[3]

[3]

N;
PU

N;
PU

N;
PU

N;
PU

Type

-

Description

[1]

LQFP144

C7

Reset state

LQFP208

P7_6

TFBGA100

Pin name

LBGA256

Table 187. LPC436x/5x/3x/2x/1x, LPC43S6x/S5x/S3xpin description (flash parts) …continued

I/O

GPIO3[14] — General purpose digital input/output pin.

O

CTOUT_11 — SCT output 1. Match output 3 of timer 2.

-

R — Function reserved.

O

LCD_LP — Line synchronization pulse (STN). Horizontal
synchronization pulse (TFT).

-

R — Function reserved.

O

TRACEDATA[2] — Trace data, bit 2.

-

R — Function reserved.

-

R — Function reserved.

I/O

GPIO3[15] — General purpose digital input/output pin.

O

CTOUT_8 — SCT output 8. Match output 0 of timer 2.

-

R — Function reserved.

O

LCD_PWR — LCD panel power enable.

-

R — Function reserved.

O

TRACEDATA[3] — Trace data, bit 3.

O

ENET_MDC — Ethernet MIIM clock.

I/O

SGPIO7 — General purpose digital input/output pin.

AI

ADC1_6 — ADC1 and ADC0, input channel 6. Configure the
pin as GPIO input and use the ADC function select register in
the SCU to select the ADC.

I/O

GPIO4[0] — General purpose digital input/output pin.

I

USB0_PWR_FAULT — Port power fault signal indicating
overcurrent condition; this signal monitors over-current on the
USB bus (external circuitry required to detect over-current
condition).

-

R — Function reserved.

I

MCI2 — Motor control PWM channel 2, input.

I/O

SGPIO8 — General purpose digital input/output pin.

-

R — Function reserved.

-

R — Function reserved.

O

T0_MAT0 — Match output 0 of timer 0.

I/O

GPIO4[1] — General purpose digital input/output pin.

O

USB0_IND1 — USB0 port indicator LED control output 1.

-

R — Function reserved.

I

MCI1 — Motor control PWM channel 1, input.

I/O

SGPIO9 — General purpose digital input/output pin.

-

R — Function reserved.

-

R — Function reserved.

O

T0_MAT1 — Match output 1 of timer 0.

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Rev. 2.4 — 22 August 2018

© NXP B.V. 2018. All rights reserved.

374 of 1444

UM10503

NXP Semiconductors

Chapter 16: LPC43xx/LPC43Sxx Pin configuration

P8_3

P8_4

P8_5

UM10503

User manual

36

-

J3

J2

J1

-

-

-

37

39

40

-

-

-

[3]

[2]

[2]

[2]

N;
PU

N;
PU

N;
PU

N;
PU

Type

-

Description

[1]

LQFP144

K4

Reset state

LQFP208

P8_2

TFBGA100

Pin name

LBGA256

Table 187. LPC436x/5x/3x/2x/1x, LPC43S6x/S5x/S3xpin description (flash parts) …continued

I/O

GPIO4[2] — General purpose digital input/output pin.

O

USB0_IND0 — USB0 port indicator LED control output 0.

-

R — Function reserved.

I

MCI0 — Motor control PWM channel 0, input.

I/O

SGPIO10 — General purpose digital input/output pin.

-

R — Function reserved.

-

R — Function reserved.

O

T0_MAT2 — Match output 2 of timer 0.

I/O

GPIO4[3] — General purpose digital input/output pin.

I/O

USB1_ULPI_D2 — ULPI link bidirectional data line 2.

-

R — Function reserved.

O

LCD_VD12 — LCD data.

O

LCD_VD19 — LCD data.

-

R — Function reserved.

-

R — Function reserved.

O

T0_MAT3 — Match output 3 of timer 0.

I/O

GPIO4[4] — General purpose digital input/output pin.

I/O

USB1_ULPI_D1 — ULPI link bidirectional data line 1.

-

R — Function reserved.

O

LCD_VD7 — LCD data.

O

LCD_VD16 — LCD data.

-

R — Function reserved.

-

R — Function reserved.

I

T0_CAP0 — Capture input 0 of timer 0.

I/O

GPIO4[5] — General purpose digital input/output pin.

I/O

USB1_ULPI_D0 — ULPI link bidirectional data line 0.

-

R — Function reserved.

O

LCD_VD6 — LCD data.

O

LCD_VD8 — LCD data.

-

R — Function reserved.

-

R — Function reserved.

I

T0_CAP1 — Capture input 1 of timer 0.

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Rev. 2.4 — 22 August 2018

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375 of 1444

UM10503

NXP Semiconductors

Chapter 16: LPC43xx/LPC43Sxx Pin configuration

P8_7

P8_8

P9_0

UM10503

User manual

43

-

K1

L1

T1

-

-

-

45

49

59

-

-

-

[2]

[2]

[2]

[2]

N;
PU

N;
PU

N;
PU

N;
PU

Type

-

Description

[1]

LQFP144

K3

Reset state

LQFP208

P8_6

TFBGA100

Pin name

LBGA256

Table 187. LPC436x/5x/3x/2x/1x, LPC43S6x/S5x/S3xpin description (flash parts) …continued

I/O

GPIO4[6] — General purpose digital input/output pin.

I

USB1_ULPI_NXT — ULPI link NXT signal. Data flow control
signal from the PHY.

-

R — Function reserved.

O

LCD_VD5 — LCD data.

O

LCD_LP — Line synchronization pulse (STN). Horizontal
synchronization pulse (TFT).

-

R — Function reserved.

-

R — Function reserved.

I

T0_CAP2 — Capture input 2 of timer 0.

I/O

GPIO4[7] — General purpose digital input/output pin.

O

USB1_ULPI_STP — ULPI link STP signal. Asserted to end or
interrupt transfers to the PHY.

-

R — Function reserved.

O

LCD_VD4 — LCD data.

O

LCD_PWR — LCD panel power enable.

-

R — Function reserved.

-

R — Function reserved.

I

T0_CAP3 — Capture input 3 of timer 0.

-

R — Function reserved.

I

USB1_ULPI_CLK — ULPI link CLK signal. 60 MHz clock
generated by the PHY.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

O

CGU_OUT0 — CGU spare clock output 0.

O

I2S1_TX_MCLK — I2S1 transmit master clock.

I/O

GPIO4[12] — General purpose digital input/output pin.

O

MCABORT — Motor control PWM, LOW-active fast abort.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

I

ENET_CRS — Ethernet Carrier Sense (MII interface).

I/O

SGPIO0 — General purpose digital input/output pin.

I/O

SSP0_SSEL — Slave Select for SSP0.

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Rev. 2.4 — 22 August 2018

© NXP B.V. 2018. All rights reserved.

376 of 1444

UM10503

NXP Semiconductors

Chapter 16: LPC43xx/LPC43Sxx Pin configuration

P9_2

P9_3

P9_4

UM10503

User manual

66

-

N8

M6

N10

-

-

-

70

79

92

-

-

-

[2]

[2]

[2]

[2]

N;
PU

N;
PU

N;
PU

N;
PU

Type

-

Description

[1]

LQFP144

N6

Reset state

LQFP208

P9_1

TFBGA100

Pin name

LBGA256

Table 187. LPC436x/5x/3x/2x/1x, LPC43S6x/S5x/S3xpin description (flash parts) …continued

I/O

GPIO4[13] — General purpose digital input/output pin.

O

MCOA2 — Motor control PWM channel 2, output A.

-

R — Function reserved.

-

R — Function reserved.

I/O

I2S0_TX_WS — Transmit Word Select. It is driven by the
master and received by the slave. Corresponds to the signal
WS in the I2S-bus specification.

I

ENET_RX_ER — Ethernet receive error (MII interface).

I/O

SGPIO1 — General purpose digital input/output pin.

I/O

SSP0_MISO — Master In Slave Out for SSP0.

I/O

GPIO4[14] — General purpose digital input/output pin.

O

MCOB2 — Motor control PWM channel 2, output B.

-

R — Function reserved.

-

R — Function reserved.

I/O

I2S0_TX_SDA — I2S transmit data. It is driven by the
transmitter and read by the receiver. Corresponds to the signal
SD in the I2S-bus specification.

I

ENET_RXD3 — Ethernet receive data 3 (MII interface).

I/O

SGPIO2 — General purpose digital input/output pin.

I/O

SSP0_MOSI — Master Out Slave in for SSP0.

I/O

GPIO4[15] — General purpose digital input/output pin.

O

MCOA0 — Motor control PWM channel 0, output A.

O

USB1_IND1 — USB1 Port indicator LED control output 1.

-

R — Function reserved.

-

R — Function reserved.

I

ENET_RXD2 — Ethernet receive data 2 (MII interface).

I/O

SGPIO9 — General purpose digital input/output pin.

O

U3_TXD — Transmitter output for USART3.

-

R — Function reserved.

O

MCOB0 — Motor control PWM channel 0, output B.

O

USB1_IND0 — USB1 Port indicator LED control output 0.

-

R — Function reserved.

I/O

GPIO5[17] — General purpose digital input/output pin.

O

ENET_TXD2 — Ethernet transmit data 2 (MII interface).

I/O

SGPIO4 — General purpose digital input/output pin.

I

U3_RXD — Receiver input for USART3.

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Rev. 2.4 — 22 August 2018

© NXP B.V. 2018. All rights reserved.

377 of 1444

UM10503

NXP Semiconductors

Chapter 16: LPC43xx/LPC43Sxx Pin configuration

98

69

[2]

N;
PU

Type

-

Description

[1]

LQFP144

M9

Reset state

LQFP208

P9_5

TFBGA100

Pin name

LBGA256

Table 187. LPC436x/5x/3x/2x/1x, LPC43S6x/S5x/S3xpin description (flash parts) …continued

-

R — Function reserved.

O

MCOA1 — Motor control PWM channel 1, output A.

O

USB1_PPWR — VBUS drive signal (towards external charge
pump or power management unit); indicates that VBUS must
be driven (active high).
Add a pull-down resistor to disable the power switch at reset.
This signal has opposite polarity compared to the USB_PPWR
used on other NXP LPC parts.

P9_6

PA_0

PA_1

UM10503

User manual

L11

L12

J14

-

-

-

103

126

134

72

-

-

[2]

[2]

[3]

N;
PU

N;
PU

N;
PU

-

R — Function reserved.

I/O

GPIO5[18] — General purpose digital input/output pin.

O

ENET_TXD3 — Ethernet transmit data 3 (MII interface).

I/O

SGPIO3 — General purpose digital input/output pin.

O

U0_TXD — Transmitter output for USART0.

I/O

GPIO4[11] — General purpose digital input/output pin.

O

MCOB1 — Motor control PWM channel 1, output B.

I

USB1_PWR_FAULT — USB1 Port power fault signal
indicating over-current condition; this signal monitors
over-current on the USB1 bus (external circuitry required to
detect over-current condition).

-

R — Function reserved.

-

R — Function reserved.

I

ENET_COL — Ethernet Collision detect (MII interface).

I/O

SGPIO8 — General purpose digital input/output pin.

I

U0_RXD — Receiver input for USART0.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

O

I2S1_RX_MCLK — I2S1 receive master clock.

O

CGU_OUT1 — CGU spare clock output 1.

-

R — Function reserved.

I/O

GPIO4[8] — General purpose digital input/output pin.

I

QEI_IDX — Quadrature Encoder Interface INDEX input.

-

R — Function reserved.

O

U2_TXD — Transmitter output for USART2.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

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Chapter 16: LPC43xx/LPC43Sxx Pin configuration

PA_3

PA_4

PB_0

UM10503

User manual

136

-

H11

G13

B15

-

-

-

147

151

164

-

-

-

[3]

[3]

[2]

[2]

N;
PU

N;
PU

N;
PU

N;
PU

Type

-

Description

[1]

LQFP144

K15

Reset state

LQFP208

PA_2

TFBGA100

Pin name

LBGA256

Table 187. LPC436x/5x/3x/2x/1x, LPC43S6x/S5x/S3xpin description (flash parts) …continued

I/O

GPIO4[9] — General purpose digital input/output pin.

I

QEI_PHB — Quadrature Encoder Interface PHB input.

-

R — Function reserved.

I

U2_RXD — Receiver input for USART2.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

I/O

GPIO4[10] — General purpose digital input/output pin.

I

QEI_PHA — Quadrature Encoder Interface PHA input.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

O

CTOUT_9 — SCT output 9. Match output 3 of timer 3.

-

R — Function reserved.

I/O

EMC_A23 — External memory address line 23.

I/O

GPIO5[19] — General purpose digital input/output pin.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

O

CTOUT_10 — SCT output 10. Match output 3 of timer 3.

O

LCD_VD23 — LCD data.

-

R — Function reserved.

I/O

GPIO5[20] — General purpose digital input/output pin.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

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NXP Semiconductors

Chapter 16: LPC43xx/LPC43Sxx Pin configuration

PB_2

PB_3

PB_4

UM10503

User manual

175

-

B12

A13

B11

-

-

-

177

178

180

-

-

-

[2]

[2]

[2]

[2]

N;
PU

N;
PU

N;
PU

N;
PU

Type

-

Description

[1]

LQFP144

A14

Reset state

LQFP208

PB_1

TFBGA100

Pin name

LBGA256

Table 187. LPC436x/5x/3x/2x/1x, LPC43S6x/S5x/S3xpin description (flash parts) …continued

-

R — Function reserved.

I

USB1_ULPI_DIR — ULPI link DIR signal. Controls the ULP
data line direction.

O

LCD_VD22 — LCD data.

-

R — Function reserved.

I/O

GPIO5[21] — General purpose digital input/output pin.

O

CTOUT_6 — SCT output 6. Match output 2 of timer 1.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

I/O

USB1_ULPI_D7 — ULPI link bidirectional data line 7.

O

LCD_VD21 — LCD data.

-

R — Function reserved.

I/O

GPIO5[22] — General purpose digital input/output pin.

O

CTOUT_7 — SCT output 7. Match output 3 of timer 1.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

I/O

USB1_ULPI_D6 — ULPI link bidirectional data line 6.

O

LCD_VD20 — LCD data.

-

R — Function reserved.

I/O

GPIO5[23] — General purpose digital input/output pin.

O

CTOUT_8 — SCT output 8. Match output 0 of timer 2.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

I/O

USB1_ULPI_D5 — ULPI link bidirectional data line 5.

O

LCD_VD15 — LCD data.

-

R — Function reserved.

I/O

GPIO5[24] — General purpose digital input/output pin.

I

CTIN_5 — SCT input 5. Capture input 2 of timer 2.

-

R — Function reserved.

-

R — Function reserved.

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NXP Semiconductors

Chapter 16: LPC43xx/LPC43Sxx Pin configuration

PB_6

PC_0

PC_1

UM10503

User manual

181

-

A6

D4

E4

-

-

-

-

7

9

-

-

-

[2]

[5]

[5]

[2]

N;
PU

N;
PU

N;
PU

N;
PU

Type

-

Description

[1]

LQFP144

A12

Reset state

LQFP208

PB_5

TFBGA100

Pin name

LBGA256

Table 187. LPC436x/5x/3x/2x/1x, LPC43S6x/S5x/S3xpin description (flash parts) …continued

-

R — Function reserved.

I/O

USB1_ULPI_D4 — ULPI link bidirectional data line 4.

O

LCD_VD14 — LCD data.

-

R — Function reserved.

I/O

GPIO5[25] — General purpose digital input/output pin.

I

CTIN_7 — SCT input 7.

O

LCD_PWR — LCD panel power enable.

-

R — Function reserved.

-

R — Function reserved.

I/O

USB1_ULPI_D3 — ULPI link bidirectional data line 3.

O

LCD_VD13 — LCD data.

-

R — Function reserved.

I/O

GPIO5[26] — General purpose digital input/output pin.

I

CTIN_6 — SCT input 6. Capture input 1 of timer 3.

O

LCD_VD19 — LCD data.

-

R — Function reserved.

AI

ADC0_6 — ADC0 and ADC1, input channel 6. Configure the
pin as GPIO input and use the ADC function select register in
the SCU to select the ADC.

-

R — Function reserved.

I

USB1_ULPI_CLK — ULPI link CLK signal. 60 MHz clock
generated by the PHY.

-

R — Function reserved.

I/O

ENET_RX_CLK — Ethernet Receive Clock (MII interface).

O

LCD_DCLK — LCD panel clock.

-

R — Function reserved.

-

R — Function reserved.

I/O

SD_CLK — SD/MMC card clock.

AI

ADC1_1 — ADC1 and ADC0, input channel 1. Configure the
pin as USB1_ULPI_CLK input and use the ADC function
select register in the SCU to select the ADC.

I/O

USB1_ULPI_D7 — ULPI link bidirectional data line 7.

-

R — Function reserved.

I

U1_RI — Ring Indicator input for UART 1.

O

ENET_MDC — Ethernet MIIM clock.

I/O

GPIO6[0] — General purpose digital input/output pin.

-

R — Function reserved.

I

T3_CAP0 — Capture input 0 of timer 3.

O

SD_VOLT0 — SD/MMC bus voltage select output 0.

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NXP Semiconductors

Chapter 16: LPC43xx/LPC43Sxx Pin configuration

PC_3

PC_4

13

-

F5

F4

-

-

11

16

-

-

[2]

[5]

[2]

N;
PU

N;
PU

N;
PU

Type

-

Description

[1]

LQFP144

F6

Reset state

LQFP208

PC_2

TFBGA100

Pin name

LBGA256

Table 187. LPC436x/5x/3x/2x/1x, LPC43S6x/S5x/S3xpin description (flash parts) …continued

I/O

USB1_ULPI_D6 — ULPI link bidirectional data line 6.

-

R — Function reserved.

I

U1_CTS — Clear to Send input for UART 1.

O

ENET_TXD2 — Ethernet transmit data 2 (MII interface).

I/O

GPIO6[1] — General purpose digital input/output pin.

-

R — Function reserved.

-

R — Function reserved.

O

SD_RST — SD/MMC reset signal for MMC4.4 card.

I/O

USB1_ULPI_D5 — ULPI link bidirectional data line 5.

-

R — Function reserved.

O

U1_RTS — Request to Send output for UART 1. Can also be
configured to be an RS-485/EIA-485 output enable signal for
UART 1.

O

ENET_TXD3 — Ethernet transmit data 3 (MII interface).

I/O

GPIO6[2] — General purpose digital input/output pin.

-

R — Function reserved.

-

R — Function reserved.

O

SD_VOLT1 — SD/MMC bus voltage select output 1.

AI

ADC1_0 — DAC, ADC1 and ADC0, input channel 0.
Configure the pin as GPIO input and use the ADC function
select register in the SCU to select the ADC.

-

R — Function reserved.

I/O

USB1_ULPI_D4 — ULPI link bidirectional data line 4.

-

R — Function reserved.
ENET_TX_EN — Ethernet transmit enable (RMII/MII
interface).

PC_5

UM10503

User manual

G4

-

20

-

[2]

N;
PU

I/O

GPIO6[3] — General purpose digital input/output pin.

-

R — Function reserved.

I

T3_CAP1 — Capture input 1 of timer 3.

I/O

SD_DAT0 — SD/MMC data bus line 0.

-

R — Function reserved.

I/O

USB1_ULPI_D3 — ULPI link bidirectional data line 3.

-

R — Function reserved.

O

ENET_TX_ER — Ethernet Transmit Error (MII interface).

I/O

GPIO6[4] — General purpose digital input/output pin.

-

R — Function reserved.

I

T3_CAP2 — Capture input 2 of timer 3.

I/O

SD_DAT1 — SD/MMC data bus line 1.

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NXP Semiconductors

Chapter 16: LPC43xx/LPC43Sxx Pin configuration

PC_7

PC_8

PC_9

UM10503

User manual

22

-

G5

N4

K2

-

-

-

-

-

-

-

-

-

[2]

[2]

[2]

[2]

N;
PU

N;
PU

N;
PU

N;
PU

Type

-

Description

[1]

LQFP144

H6

Reset state

LQFP208

PC_6

TFBGA100

Pin name

LBGA256

Table 187. LPC436x/5x/3x/2x/1x, LPC43S6x/S5x/S3xpin description (flash parts) …continued

-

R — Function reserved.

I/O

USB1_ULPI_D2 — ULPI link bidirectional data line 2.

-

R — Function reserved.

I

ENET_RXD2 — Ethernet receive data 2 (MII interface).

I/O

GPIO6[5] — General purpose digital input/output pin.

-

R — Function reserved.

I

T3_CAP3 — Capture input 3 of timer 3.

I/O

SD_DAT2 — SD/MMC data bus line 2.

-

R — Function reserved.

I/O

USB1_ULPI_D1 — ULPI link bidirectional data line 1.

-

R — Function reserved.

I

ENET_RXD3 — Ethernet receive data 3 (MII interface).

I/O

GPIO6[6] — General purpose digital input/output pin.

-

R — Function reserved.

O

T3_MAT0 — Match output 0 of timer 3.

I/O

SD_DAT3 — SD/MMC data bus line 3.

-

R — Function reserved.

I/O

USB1_ULPI_D0 — ULPI link bidirectional data line 0.

-

R — Function reserved.

I

ENET_RX_DV — Ethernet Receive Data Valid (RMII/MII
interface).

I/O

GPIO6[7] — General purpose digital input/output pin.

-

R — Function reserved.

O

T3_MAT1 — Match output 1 of timer 3.

I

SD_CD — SD/MMC card detect input.

-

R — Function reserved.

I

USB1_ULPI_NXT — ULPI link NXT signal. Data flow control
signal from the PHY.

-

R — Function reserved.

I

ENET_RX_ER — Ethernet receive error (MII interface).

I/O

GPIO6[8] — General purpose digital input/output pin.

-

R — Function reserved.

O

T3_MAT2 — Match output 2 of timer 3.

O

SD_POW — SD/MMC power monitor output.

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NXP Semiconductors

Chapter 16: LPC43xx/LPC43Sxx Pin configuration

PC_11

PC_12

PC_13

UM10503

User manual

-

-

L5

L6

M1

-

-

-

-

-

-

-

-

-

[2]

[2]

[2]

[2]

N;
PU

N;
PU

N;
PU

N;
PU

Type

-

Description

[1]

LQFP144

M5

Reset state

LQFP208

PC_10

TFBGA100

Pin name

LBGA256

Table 187. LPC436x/5x/3x/2x/1x, LPC43S6x/S5x/S3xpin description (flash parts) …continued

-

R — Function reserved.

O

USB1_ULPI_STP — ULPI link STP signal. Asserted to end or
interrupt transfers to the PHY.

I

U1_DSR — Data Set Ready input for UART 1.

-

R — Function reserved.

I/O

GPIO6[9] — General purpose digital input/output pin.

-

R — Function reserved.

O

T3_MAT3 — Match output 3 of timer 3.

I/O

SD_CMD — SD/MMC command signal.

-

R — Function reserved.

I

USB1_ULPI_DIR — ULPI link DIR signal. Controls the ULPI
data line direction.

I

U1_DCD — Data Carrier Detect input for UART 1.

-

R — Function reserved.

I/O

GPIO6[10] — General purpose digital input/output pin.

-

R — Function reserved.

-

R — Function reserved.

I/O

SD_DAT4 — SD/MMC data bus line 4.

-

R — Function reserved.

-

R — Function reserved.

O

U1_DTR — Data Terminal Ready output for UART 1. Can also
be configured to be an RS-485/EIA-485 output enable signal
for UART 1.

-

R — Function reserved.

I/O

GPIO6[11] — General purpose digital input/output pin.

I/O

SGPIO11 — General purpose digital input/output pin.

I/O

I2S0_TX_SDA — I2S transmit data. It is driven by the
transmitter and read by the receiver. Corresponds to the signal
SD in the I2S-bus specification.

I/O

SD_DAT5 — SD/MMC data bus line 5.

-

R — Function reserved.

-

R — Function reserved.

O

U1_TXD — Transmitter output for UART 1.

-

R — Function reserved.

I/O

GPIO6[12] — General purpose digital input/output pin.

I/O

SGPIO12 — General purpose digital input/output pin.

I/O

I2S0_TX_WS — Transmit Word Select. It is driven by the
master and received by the slave. Corresponds to the signal
WS in the I2S-bus specification.

I/O

SD_DAT6 — SD/MMC data bus line 6.

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Rev. 2.4 — 22 August 2018

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Chapter 16: LPC43xx/LPC43Sxx Pin configuration

PD_0

PD_1

PD_2

UM10503

User manual

-

-

N2

P1

R1

-

-

-

-

-

-

-

-

-

[2]

[2]

[2]

[2]

N;
PU

N;
PU

N;
PU

N;
PU

Type

-

Description

[1]

LQFP144

N1

Reset state

LQFP208

PC_14

TFBGA100

Pin name

LBGA256

Table 187. LPC436x/5x/3x/2x/1x, LPC43S6x/S5x/S3xpin description (flash parts) …continued

-

R — Function reserved.

-

R — Function reserved.

I

U1_RXD — Receiver input for UART 1.

-

R — Function reserved.

I/O

GPIO6[13] — General purpose digital input/output pin.

I/O

SGPIO13 — General purpose digital input/output pin.

O

ENET_TX_ER — Ethernet Transmit Error (MII interface).

I/O

SD_DAT7 — SD/MMC data bus line 7.

-

R — Function reserved.

O

CTOUT_15 — SCT output 15. Match output 3 of timer 3.

O

EMC_DQMOUT2 — Data mask 2 used with SDRAM and
static devices.

-

R — Function reserved.

I/O

GPIO6[14] — General purpose digital input/output pin.

-

R — Function reserved.

-

R — Function reserved.

I/O

SGPIO4 — General purpose digital input/output pin.

-

R — Function reserved.

-

R — Function reserved.

O

EMC_CKEOUT2 — SDRAM clock enable 2.

-

R — Function reserved.

I/O

GPIO6[15] — General purpose digital input/output pin.

O

SD_POW — SD/MMC power monitor output.

-

R — Function reserved.

I/O

SGPIO5 — General purpose digital input/output pin.

-

R — Function reserved.

O

CTOUT_7 — SCT output 7. Match output 3 of timer 1.

I/O

EMC_D16 — External memory data line 16.

-

R — Function reserved.

I/O

GPIO6[16] — General purpose digital input/output pin.

-

R — Function reserved.

-

R — Function reserved.

I/O

SGPIO6 — General purpose digital input/output pin.

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Rev. 2.4 — 22 August 2018

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NXP Semiconductors

Chapter 16: LPC43xx/LPC43Sxx Pin configuration

PD_4

PD_5

PD_6

UM10503

User manual

-

-

T2

P6

R6

-

-

-

-

-

68

-

-

-

[2]

[2]

[2]

[2]

N;
PU

N;
PU

N;
PU

N;
PU

Type

-

Description

[1]

LQFP144

P4

Reset state

LQFP208

PD_3

TFBGA100

Pin name

LBGA256

Table 187. LPC436x/5x/3x/2x/1x, LPC43S6x/S5x/S3xpin description (flash parts) …continued

-

R — Function reserved.

O

CTOUT_6 — SCT output 7. Match output 2 of timer 1.

I/O

EMC_D17 — External memory data line 17.

-

R — Function reserved.

I/O

GPIO6[17] — General purpose digital input/output pin.

-

R — Function reserved.

-

R — Function reserved.

I/O

SGPIO7 — General purpose digital input/output pin.

-

R — Function reserved.

O

CTOUT_8 — SCT output 8. Match output 0 of timer 2.

I/O

EMC_D18 — External memory data line 18.

-

R — Function reserved.

I/O

GPIO6[18] — General purpose digital input/output pin.

-

R — Function reserved.

-

R — Function reserved.

I/O

SGPIO8 — General purpose digital input/output pin.

-

R — Function reserved.

O

CTOUT_9 — SCT output 9. Match output 3 of timer 3.

I/O

EMC_D19 — External memory data line 19.

-

R — Function reserved.

I/O

GPIO6[19] — General purpose digital input/output pin.

-

R — Function reserved.

-

R — Function reserved.

I/O

SGPIO9 — General purpose digital input/output pin.

-

R — Function reserved.

O

CTOUT_10 — SCT output 10. Match output 3 of timer 3.

I/O

EMC_D20 — External memory data line 20.

-

R — Function reserved.

I/O

GPIO6[20] — General purpose digital input/output pin.

-

R — Function reserved.

-

R — Function reserved.

I/O

SGPIO10 — General purpose digital input/output pin.

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Rev. 2.4 — 22 August 2018

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386 of 1444

UM10503

NXP Semiconductors

Chapter 16: LPC43xx/LPC43Sxx Pin configuration

PD_8

PD_9

PD_10

UM10503

User manual

72

-

P8

T11

P11

-

-

-

74

84

86

-

-

-

[2]

[2]

[2]

[2]

N;
PU

N;
PU

N;
PU

N;
PU

Type

-

Description

[1]

LQFP144

T6

Reset state

LQFP208

PD_7

TFBGA100

Pin name

LBGA256

Table 187. LPC436x/5x/3x/2x/1x, LPC43S6x/S5x/S3xpin description (flash parts) …continued

-

R — Function reserved.

I

CTIN_5 — SCT input 5. Capture input 2 of timer 2.

I/O

EMC_D21 — External memory data line 21.

-

R — Function reserved.

I/O

GPIO6[21] — General purpose digital input/output pin.

-

R — Function reserved.

-

R — Function reserved.

I/O

SGPIO11 — General purpose digital input/output pin.

-

R — Function reserved.

I

CTIN_6 — SCT input 6. Capture input 1 of timer 3.

I/O

EMC_D22 — External memory data line 22.

-

R — Function reserved.

I/O

GPIO6[22] — General purpose digital input/output pin.

-

R — Function reserved.

-

R — Function reserved.

I/O

SGPIO12 — General purpose digital input/output pin.

-

R — Function reserved.

O

CTOUT_13 — SCT output 13. Match output 3 of timer 3.

I/O

EMC_D23 — External memory data line 23.

-

R — Function reserved.

I/O

GPIO6[23] — General purpose digital input/output pin.

-

R — Function reserved.

-

R — Function reserved.

I/O

SGPIO13 — General purpose digital input/output pin.

-

R — Function reserved.

I

CTIN_1 — SCT input 1. Capture input 1 of timer 0. Capture
input 1 of timer 2.

O

EMC_BLS3 — LOW active Byte Lane select signal 3.

-

R — Function reserved.

I/O

GPIO6[24] — General purpose digital input/output pin.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

All information provided in this document is subject to legal disclaimers.

Rev. 2.4 — 22 August 2018

© NXP B.V. 2018. All rights reserved.

387 of 1444

UM10503

NXP Semiconductors

Chapter 16: LPC43xx/LPC43Sxx Pin configuration

PD_12

PD_13

PD_14

UM10503

User manual

88

-

N11

T14

R13

-

-

-

94

97

99

-

-

-

[2]

[2]

[2]

[2]

N;
PU

N;
PU

N;
PU

N;
PU

Type

-

Description

[1]

LQFP144

N9

Reset state

LQFP208

PD_11

TFBGA100

Pin name

LBGA256

Table 187. LPC436x/5x/3x/2x/1x, LPC43S6x/S5x/S3xpin description (flash parts) …continued

-

R — Function reserved.

-

R — Function reserved.

O

EMC_CS3 — LOW active Chip Select 3 signal.

-

R — Function reserved.

I/O

GPIO6[25] — General purpose digital input/output pin.

I/O

USB1_ULPI_D0 — ULPI link bidirectional data line 0.

O

CTOUT_14 — SCT output 14. Match output 2 of timer 3.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

O

EMC_CS2 — LOW active Chip Select 2 signal.

-

R — Function reserved.

I/O

GPIO6[26] — General purpose digital input/output pin.

-

R — Function reserved.

O

CTOUT_10 — SCT output 10. Match output 3 of timer 3.

-

R — Function reserved.

-

R — Function reserved.

I

CTIN_0 — SCT input 0. Capture input 0 of timer 0, 1, 2, 3.

O

EMC_BLS2 — LOW active Byte Lane select signal 2.

-

R — Function reserved.

I/O

GPIO6[27] — General purpose digital input/output pin.

-

R — Function reserved.

O

CTOUT_13 — SCT output 13. Match output 3 of timer 3.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

O

EMC_DYCS2 — SDRAM chip select 2.

-

R — Function reserved.

I/O

GPIO6[28] — General purpose digital input/output pin.

-

R — Function reserved.

O

CTOUT_11 — SCT output 11. Match output 3 of timer 2.

-

R — Function reserved.

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Chapter 16: LPC43xx/LPC43Sxx Pin configuration

PD_16

PE_0

PE_1

UM10503

User manual

101

-

R14

P14

N14

-

-

-

104

106

112

-

-

-

[2]

[2]

[2]

[2]

N;
PU

N;
PU

N;
PU

N;
PU

Type

-

Description

[1]

LQFP144

T15

Reset state

LQFP208

PD_15

TFBGA100

Pin name

LBGA256

Table 187. LPC436x/5x/3x/2x/1x, LPC43S6x/S5x/S3xpin description (flash parts) …continued

-

R — Function reserved.

-

R — Function reserved.

I/O

EMC_A17 — External memory address line 17.

-

R — Function reserved.

I/O

GPIO6[29] — General purpose digital input/output pin.

I

SD_WP — SD/MMC card write protect input.

O

CTOUT_8 — SCT output 8. Match output 0 of timer 2.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

I/O

EMC_A16 — External memory address line 16.

-

R — Function reserved.

I/O

GPIO6[30] — General purpose digital input/output pin.

O

SD_VOLT2 — SD/MMC bus voltage select output 2.

O

CTOUT_12 — SCT output 12. Match output 3 of timer 3.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

I/O

EMC_A18 — External memory address line 18.

I/O

GPIO7[0] — General purpose digital input/output pin.

O

CAN1_TD — CAN1 transmitter output.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

I/O

EMC_A19 — External memory address line 19.

I/O

GPIO7[1] — General purpose digital input/output pin.

I

CAN1_RD — CAN1 receiver input.

-

R — Function reserved.

-

R — Function reserved.

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Chapter 16: LPC43xx/LPC43Sxx Pin configuration

PE_3

PE_4

PE_5

UM10503

User manual

115

-

K12

K13

N16

-

-

-

118

120

122

-

-

-

[2]

[2]

[2]

[2]

N;
PU

N;
PU

N;
PU

N;
PU

Type

-

Description

[1]

LQFP144

M14

Reset state

LQFP208

PE_2

TFBGA100

Pin name

LBGA256

Table 187. LPC436x/5x/3x/2x/1x, LPC43S6x/S5x/S3xpin description (flash parts) …continued

I

ADCTRIG0 — ADC trigger input 0.

I

CAN0_RD — CAN receiver input.

-

R — Function reserved.

I/O

EMC_A20 — External memory address line 20.

I/O

GPIO7[2] — General purpose digital input/output pin.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

O

CAN0_TD — CAN transmitter output.

I

ADCTRIG1 — ADC trigger input 1.

I/O

EMC_A21 — External memory address line 21.

I/O

GPIO7[3] — General purpose digital input/output pin.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

I

NMI — External interrupt input to NMI.

-

R — Function reserved.

I/O

EMC_A22 — External memory address line 22.

I/O

GPIO7[4] — General purpose digital input/output pin.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

O

CTOUT_3 — SCT output 3. Match output 3 of timer 0.

O

U1_RTS — Request to Send output for UART 1. Can also be
configured to be an RS-485/EIA-485 output enable signal for
UART 1.

I/O

EMC_D24 — External memory data line 24.

I/O

GPIO7[5] — General purpose digital input/output pin.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

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Chapter 16: LPC43xx/LPC43Sxx Pin configuration

PE_7

PE_8

PE_9

UM10503

User manual

124

-

F15

F14

E16

-

-

-

149

150

152

-

-

-

[2]

[2]

[2]

[2]

N;
PU

N;
PU

N;
PU

N;
PU

Type

-

Description

[1]

LQFP144

M16

Reset state

LQFP208

PE_6

TFBGA100

Pin name

LBGA256

Table 187. LPC436x/5x/3x/2x/1x, LPC43S6x/S5x/S3xpin description (flash parts) …continued

-

R — Function reserved.

O

CTOUT_2 — SCT output 2. Match output 2 of timer 0.

I

U1_RI — Ring Indicator input for UART 1.

I/O

EMC_D25 — External memory data line 25.

I/O

GPIO7[6] — General purpose digital input/output pin.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

O

CTOUT_5 — SCT output 5. Match output 3 of timer 3.

I

U1_CTS — Clear to Send input for UART1.

I/O

EMC_D26 — External memory data line 26.

I/O

GPIO7[7] — General purpose digital input/output pin.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

O

CTOUT_4 — SCT output 4. Match output 3 of timer 3.

I

U1_DSR — Data Set Ready input for UART 1.

I/O

EMC_D27 — External memory data line 27.

I/O

GPIO7[8] — General purpose digital input/output pin.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

I

CTIN_4 — SCT input 4. Capture input 2 of timer 1.

I

U1_DCD — Data Carrier Detect input for UART 1.

I/O

EMC_D28 — External memory data line 28.

I/O

GPIO7[9] — General purpose digital input/output pin.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

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Chapter 16: LPC43xx/LPC43Sxx Pin configuration

PE_11

PE_12

PE_13

UM10503

User manual

154

-

D16

D15

G14

-

-

-

-

-

-

-

-

-

[2]

[2]

[2]

[2]

N;
PU

N;
PU

N;
PU

N;
PU

Type

-

Description

[1]

LQFP144

E14

Reset state

LQFP208

PE_10

TFBGA100

Pin name

LBGA256

Table 187. LPC436x/5x/3x/2x/1x, LPC43S6x/S5x/S3xpin description (flash parts) …continued

-

R — Function reserved.

I

CTIN_3 — SCT input 3. Capture input 1 of timer 1.

O

U1_DTR — Data Terminal Ready output for UART 1. Can also
be configured to be an RS-485/EIA-485 output enable signal
for UART 1.

I/O

EMC_D29 — External memory data line 29.

I/O

GPIO7[10] — General purpose digital input/output pin.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

O

CTOUT_12 — SCT output 12. Match output 3 of timer 3.

O

U1_TXD — Transmitter output for UART 1.

I/O

EMC_D30 — External memory data line 30.

I/O

GPIO7[11] — General purpose digital input/output pin.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

O

CTOUT_11 — SCT output 11. Match output 3 of
timer 2.

I

U1_RXD — Receiver input for UART 1.

I/O

EMC_D31 — External memory data line 31.

I/O

GPIO7[12] — General purpose digital input/output pin.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

O

CTOUT_14 — SCT output 14. Match output 2 of timer 3.

I/O

I2C1_SDA — I2C1 data input/output (this pin does not use a
specialized I2C pad).

O

EMC_DQMOUT3 — Data mask 3 used with SDRAM and
static devices.

I/O

GPIO7[13] — General purpose digital input/output pin.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

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NXP Semiconductors

Chapter 16: LPC43xx/LPC43Sxx Pin configuration

PE_15

PF_0

PF_1

UM10503

User manual

-

-

E13

D12

E11

-

-

-

-

159

-

-

-

-

[2]

[2]

[2]

[2]

N;
PU

N;
PU

O;
PU

N;
PU

Type

-

Description

[1]

LQFP144

C15

Reset state

LQFP208

PE_14

TFBGA100

Pin name

LBGA256

Table 187. LPC436x/5x/3x/2x/1x, LPC43S6x/S5x/S3xpin description (flash parts) …continued

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

O

EMC_DYCS3 — SDRAM chip select 3.

I/O

GPIO7[14] — General purpose digital input/output pin.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

O

CTOUT_0 — SCT output 0. Match output 0 of timer 0.

I/O

I2C1_SCL — I2C1 clock input/output (this pin does not use a
specialized I2C pad).

O

EMC_CKEOUT3 — SDRAM clock enable 3.

I/O

GPIO7[15] — General purpose digital input/output pin.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

I/O

SSP0_SCK — Serial clock for SSP0.

I

GP_CLKIN — General purpose clock input to the CGU.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

O

I2S1_TX_MCLK — I2S1 transmit master clock.

-

R — Function reserved.

-

R — Function reserved.

I/O

SSP0_SSEL — Slave Select for SSP0.

-

R — Function reserved.

I/O

GPIO7[16] — General purpose digital input/output pin.

-

R — Function reserved.

I/O

SGPIO0 — General purpose digital input/output pin.

-

R — Function reserved.

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Rev. 2.4 — 22 August 2018

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393 of 1444

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NXP Semiconductors

Chapter 16: LPC43xx/LPC43Sxx Pin configuration

PF_3

PF_4

PF_5

UM10503

User manual

168

-

E10

D10

E9

-

H4

-

170

172

190

-

120

-

[2]

[2]

[2]

[5]

N;
PU

N;
PU

O;
PU

N;
PU

Type

-

Description

[1]

LQFP144

D11

Reset state

LQFP208

PF_2

TFBGA100

Pin name

LBGA256

Table 187. LPC436x/5x/3x/2x/1x, LPC43S6x/S5x/S3xpin description (flash parts) …continued

-

R — Function reserved.

O

U3_TXD — Transmitter output for USART3.

I/O

SSP0_MISO — Master In Slave Out for SSP0.

-

R — Function reserved.

I/O

GPIO7[17] — General purpose digital input/output pin.

-

R — Function reserved.

I/O

SGPIO1 — General purpose digital input/output pin.

-

R — Function reserved.

-

R — Function reserved.

I

U3_RXD — Receiver input for USART3.

I/O

SSP0_MOSI — Master Out Slave in for SSP0.

-

R — Function reserved.

I/O

GPIO7[18] — General purpose digital input/output pin.

-

R — Function reserved.

I/O

SGPIO2 — General purpose digital input/output pin.

-

R — Function reserved.

I/O

SSP1_SCK — Serial clock for SSP1.

I

GP_CLKIN — General purpose clock input to the CGU.

O

TRACECLK — Trace clock.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

O

I2S0_TX_MCLK — I2S transmit master clock.

I/O

I2S0_RX_SCK — I2S receive clock. It is driven by the master
and received by the slave. Corresponds to the signal SCK in
the I2S-bus specification.

-

R — Function reserved.

I/O

U3_UCLK — Serial clock input/output for USART3 in
synchronous mode.

I/O

SSP1_SSEL — Slave Select for SSP1.

O

TRACEDATA[0] — Trace data, bit 0.

I/O

GPIO7[19] — General purpose digital input/output pin.

-

R — Function reserved.

I/O

SGPIO4 — General purpose digital input/output pin.

-

R — Function reserved.

AI

ADC1_4 — ADC1 and ADC0, input channel 4. Configure the
pin as GPIO input and use the ADC function select register in
the SCU to select the ADC.

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Rev. 2.4 — 22 August 2018

© NXP B.V. 2018. All rights reserved.

394 of 1444

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NXP Semiconductors

Chapter 16: LPC43xx/LPC43Sxx Pin configuration

PF_7

PF_8

UM10503

User manual

192

-

B7

E6

-

-

193

-

-

-

[5]

[5]

[5]

N;
PU

N;
PU

N;
PU

Type

-

Description

[1]

LQFP144

E7

Reset state

LQFP208

PF_6

TFBGA100

Pin name

LBGA256

Table 187. LPC436x/5x/3x/2x/1x, LPC43S6x/S5x/S3xpin description (flash parts) …continued

-

R — Function reserved.

I/O

U3_DIR — RS-485/EIA-485 output enable/direction control for
USART3.

I/O

SSP1_MISO — Master In Slave Out for SSP1.

O

TRACEDATA[1] — Trace data, bit 1.

I/O

GPIO7[20] — General purpose digital input/output pin.

-

R — Function reserved.

I/O

SGPIO5 — General purpose digital input/output pin.

I/O

I2S1_TX_SDA — I2S1 transmit data. It is driven by the
transmitter and read by the receiver. Corresponds to the signal
SD in the I2S-bus specification.

AI

ADC1_3 — ADC1 and ADC0, input channel 3. Configure the
pin as GPIO input and use the ADC function select register in
the SCU to select the ADC.

-

R — Function reserved.

I/O

U3_BAUD — Baud pin for USART3.

I/O

SSP1_MOSI — Master Out Slave in for SSP1.

O

TRACEDATA[2] — Trace data, bit 2.

I/O

GPIO7[21] — General purpose digital input/output pin.

-

R — Function reserved.

I/O

SGPIO6 — General purpose digital input/output pin.

I/O

I2S1_TX_WS — Transmit Word Select. It is driven by the
master and received by the slave. Corresponds to the signal
WS in the I2S-bus specification.

AI/
O

ADC1_7 — ADC1 and ADC0, input channel 7 or band gap
output. Configure the pin as GPIO input and use the ADC
function select register in the SCU to select the ADC.

-

R — Function reserved.

I/O

U0_UCLK — Serial clock input/output for USART0 in
synchronous mode.

I

CTIN_2 — SCT input 2. Capture input 2 of timer 0.

O

TRACEDATA[3] — Trace data, bit 3.

I/O

GPIO7[22] — General purpose digital input/output pin.

-

R — Function reserved.

I/O

SGPIO7 — General purpose digital input/output pin.

-

R — Function reserved.

AI

ADC0_2 — ADC0 and ADC1, input channel 2. Configure the
pin as GPIO input and use the ADC function select register in
the SCU to select the ADC.

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Rev. 2.4 — 22 August 2018

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395 of 1444

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NXP Semiconductors

Chapter 16: LPC43xx/LPC43Sxx Pin configuration

PF_10

PF_11

UM10503

User manual

203

-

A3

A2

-

-

205

207

-

-

[5]

[5]

[5]

N;
PU

N;
PU

N;
PU

Type

-

Description

[1]

LQFP144

D6

Reset state

LQFP208

PF_9

TFBGA100

Pin name

LBGA256

Table 187. LPC436x/5x/3x/2x/1x, LPC43S6x/S5x/S3xpin description (flash parts) …continued

-

R — Function reserved.

I/O

U0_DIR — RS-485/EIA-485 output enable/direction control for
USART0.

O

CTOUT_1 — SCT output 1. Match output 3 of timer 3.

-

R — Function reserved.

I/O

GPIO7[23] — General purpose digital input/output pin.

-

R — Function reserved.

I/O

SGPIO3 — General purpose digital input/output pin.

-

R — Function reserved.

AI

ADC1_2 — ADC1 and ADC0, input channel 2. Configure the
pin as GPIO input and use the ADC function select register in
the SCU to select the ADC.

-

R — Function reserved.

O

U0_TXD — Transmitter output for USART0.

-

R — Function reserved.

-

R — Function reserved.

I/O

GPIO7[24] — General purpose digital input/output pin.

-

R — Function reserved.

I

SD_WP — SD/MMC card write protect input.

-

R — Function reserved.

AI

ADC0_5 — ADC0 and ADC1, input channel 5. Configure the
pin as GPIO input and use the ADC function select register in
the SCU to select the ADC.

-

R — Function reserved.

I

U0_RXD — Receiver input for USART0.

-

R — Function reserved.

-

R — Function reserved.

I/O

GPIO7[25] — General purpose digital input/output pin.

-

R — Function reserved.

O

SD_VOLT2 — SD/MMC bus voltage select output 2.

-

R — Function reserved.

AI

ADC1_5 — ADC1 and ADC0, input channel 5. Configure the
pin as GPIO input and use the ADC function select register in
the SCU to select the ADC.

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Rev. 2.4 — 22 August 2018

© NXP B.V. 2018. All rights reserved.

396 of 1444

UM10503

NXP Semiconductors

Chapter 16: LPC43xx/LPC43Sxx Pin configuration

62

45

Type

LQFP144

K3

Description

[1]

LQFP208

N5

Reset state

TFBGA100

Pin name

LBGA256

Table 187. LPC436x/5x/3x/2x/1x, LPC43S6x/S5x/S3xpin description (flash parts) …continued

Clock pins
CLK0

CLK1

CLK2

CLK3

UM10503

User manual

T10

D14

P12

-

K6

-

-

141

-

-

99

-

[4]

[4]

[4]

[4]

O;
PU

O;
PU

O;
PU

O;
PU

O

EMC_CLK0 — SDRAM clock 0.

O

CLKOUT — Clock output pin.

-

R — Function reserved.

-

R — Function reserved.

I/O

SD_CLK — SD/MMC card clock.

O

EMC_CLK01 — SDRAM clock 0 and clock 1 combined.

I/O

SSP1_SCK — Serial clock for SSP1.

I

ENET_TX_CLK (ENET_REF_CLK) — Ethernet Transmit
Clock (MII interface) or Ethernet Reference Clock (RMII
interface).

O

EMC_CLK1 — SDRAM clock 1.

O

CLKOUT — Clock output pin.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

O

CGU_OUT0 — CGU spare clock output 0.

-

R — Function reserved.

O

I2S1_TX_MCLK — I2S1 transmit master clock.

O

EMC_CLK3 — SDRAM clock 3.

O

CLKOUT — Clock output pin.

-

R — Function reserved.

-

R — Function reserved.

I/O

SD_CLK — SD/MMC card clock.

O

EMC_CLK23 — SDRAM clock 2 and clock 3 combined.

O

I2S0_TX_MCLK — I2S transmit master clock.

I/O

I2S1_RX_SCK — Receive Clock. It is driven by the master
and received by the slave. Corresponds to the signal SCK in
the I2S-bus specification.

O

EMC_CLK2 — SDRAM clock 2.

O

CLKOUT — Clock output pin.

-

R — Function reserved.

-

R — Function reserved.

-

R — Function reserved.

O

CGU_OUT1 — CGU spare clock output 1.

-

R — Function reserved.

I/O

I2S1_RX_SCK — Receive Clock. It is driven by the master
and received by the slave. Corresponds to the signal SCK in
the I2S-bus specification.

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Rev. 2.4 — 22 August 2018

© NXP B.V. 2018. All rights reserved.

397 of 1444

UM10503

NXP Semiconductors

Chapter 16: LPC43xx/LPC43Sxx Pin configuration

LQFP144

L4

A6

41

28

[2]

I

I

JTAG interface control signal. Also used for boundary scan.

TCK/SWDCLK

J5

H2

38

27

[2]

I; F

I

Test Clock for JTAG interface (default) or Serial Wire (SW)
clock.

TRST

M4

B4

42

29

[2]

I; PU I

Test Reset for JTAG interface.

I; PU I

Test Mode Select for JTAG interface (default) or SW debug
data input/output.
Test Data Out for JTAG interface (default) or SW trace output.

Type

LQFP208

DBGEN

[1]

TFBGA100

Description

LBGA256

Pin name

Reset state

Table 187. LPC436x/5x/3x/2x/1x, LPC43S6x/S5x/S3xpin description (flash parts) …continued

Debug pins

TMS/SWDIO

K6

C4

44

30

[2]

TDO/SWO

K5

H3

46

31

[2]

O

I; PU I

Test Data In for JTAG interface.

O

J4

G3

35

26

[2]

USB0_DP

F2

E1

26

18

[6]

-

I/O

USB0 bidirectional D+ line. Do not add an external series
resistor.

USB0_DM

G2

E2

28

20

[6]

-

I/O

USB0 bidirectional D line. Do not add an external series
resistor.

USB0_VBUS

F1

E3

29

21

[6]

-

I/O

VBUS pin (power on USB cable). This pin includes an internal
pull-down resistor of 64 k (typical)  16 k.

I

Indicates to the transceiver whether connected as an A-device
(USB0_ID LOW) or B-device (USB0_ID HIGH). For OTG this
pin has an internal pull-up resistor.

TDI
USB0 pins

[7]

USB0_ID

H2

F1

30

22

[8]

-

USB0_RREF

H1

F3

32

24

[8]

-

USB1_DP

F12

E9

129

89

[9]

-

I/O

USB1 bidirectional D+ line. Add an external series resistor of
33  +/- 2 %.

USB1_DM

G12

E10

130

90

[9]

-

I/O

USB1 bidirectional D line. Add an external series resistor of
33  +/- 2 %.

I2C0_SCL

L15

D6

132

92

[10]

I; F

I/O

I2C clock input/output. Open-drain output (for I2C-bus
compliance).

I2C0_SDA

L16

E6

133

93

[10]

I; F

I/O

I2C data input/output. Open-drain output (for I2C-bus
compliance).

12.0 k (accuracy 1 %) on-board resistor to ground for current
reference.

USB1 pins

I2C-bus pins

Reset and wake-up pins
RESET

D9

B6

185

128

[11]

I; IA

I

External reset input: A LOW-going pulse as short as 50 ns on
this pin resets the device, causing I/O ports and peripherals to
take on their default states, and processor execution to begin
at address 0.

WAKEUP0

A9

A4

187

130

[11]

I; IA

I

External wake-up input; can raise an interrupt and can cause
wake-up from any of the low power modes. A pulse with a
duration of at least 45 ns wakes up the part.
Input 0 of the event monitor.

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Chapter 16: LPC43xx/LPC43Sxx Pin configuration

-

-

Type

-

Description

[1]

LQFP144

A10

Reset state

LQFP208

WAKEUP1

TFBGA100

Pin name

LBGA256

Table 187. LPC436x/5x/3x/2x/1x, LPC43S6x/S5x/S3xpin description (flash parts) …continued

[11]

I; IA

I

External wake-up input; can raise an interrupt and can cause
wake-up from any of the low power modes. A pulse with a
duration of at least 45 ns wakes up the part.

I; IA

I

External wake-up input; can raise an interrupt and can cause
wake-up from any of the low power modes. A pulse with a
duration of at least 45 ns wakes up the part.
Input 1 of the event monitor.

WAKEUP2

C9

-

-

-

[11]

WAKEUP3

D8

-

-

-

[11]

I; IA

I

External wake-up input; can raise an interrupt and can cause
wake-up from any of the low power modes. A pulse with a
duration of at least 45 ns wakes up the part.

ADC0_0/
ADC1_0/DAC

E3

A2

8

6

[8]

I; IA

I

ADC input channel 0. Shared between 10-bit ADC0/1 and
DAC.

ADC0_1/
ADC1_1

C3

A1

4

2

[8]

I; IA

I

ADC input channel 1. Shared between 10-bit ADC0/1.

ADC0_2/
ADC1_2

A4

B3

206

143

[8]

I; IA

I

ADC input channel 2. Shared between 10-bit ADC0/1.

ADC0_3/
ADC1_3

B5

A3

200

139

[8]

I; IA

I

ADC input channel 3. Shared between 10-bit ADC0/1.

ADC0_4/
ADC1_4

C6

-

199

138

[8]

I; IA

I

ADC input channel 4. Shared between 10-bit ADC0/1.

ADC0_5/
ADC1_5

B3

-

208

144

[8]

I; IA

I

ADC input channel 5. Shared between 10-bit ADC0/1.

ADC0_6/
ADC1_6

A5

-

204

142

[8]

I; IA

I

ADC input channel 6. Shared between 10-bit ADC0/1.

ADC0_7/
ADC1_7

C5

-

197

136

[8]

I; IA

I

ADC input channel 7. Shared between 10-bit ADC0/1.

A11

C3

186

129

[11]

-

O

RTC controlled output.

125

[8]

-

I

Input to the RTC 32 kHz ultra-low power oscillator circuit.

Input 2 of the event monitor.

ADC pins

RTC
RTC_ALARM
RTCX1

A8

A5

182

RTCX2

B8

B5

183

126

[8]

-

O

Output from the RTC 32 kHz ultra-low power oscillator circuit.

SAMPLE

B9

-

-

-

[11]

O

O

Event monitor sample output.

Crystal oscillator pins
XTAL1

D1

B1

18

12

[8]

-

I

Input to the oscillator circuit and internal clock generator
circuits.

XTAL2

E1

C1

19

13

[8]

-

O

Output from the oscillator amplifier.

Power and ground pins
USB0_VDDA
3V3_DRIVER

F3

D1

24

16

-

-

Separate analog 3.3 V power supply for driver.

USB0
_VDDA3V3

G3

D2

25

17

-

-

USB 3.3 V separate power supply voltage.

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NXP Semiconductors

Chapter 16: LPC43xx/LPC43Sxx Pin configuration

Table 187. LPC436x/5x/3x/2x/1x, LPC43S6x/S5x/S3xpin description (flash parts) …continued
LQFP144

Reset state

H3

D3

27

19

-

-

Dedicated analog ground for clean reference for termination
resistors.

USB0_VSSA
_REF

G1

F2

31

23

-

-

Dedicated clean analog ground for generation of reference
currents and voltages.

VDDA

B4

B2

198

137

-

-

Analog power supply and ADC reference voltage.

VBAT

B10

C5

184

127

-

-

RTC power supply: 3.3 V on this pin supplies power to the
RTC.

VDDREG

F10,
F9,
L8,
L7

E4,
E5,
F4

135,
188,
195,
82,
33

94,
131,
59,
25

-

Main regulator power supply. Tie the VDDREG and VDDIO
pins to a common power supply to ensure the same ramp-up
time for both supply voltages.

VPP

E8

-

-

-

[12]

-

-

OTP programming voltage.

-

-

I/O power supply. Tie the VDDREG and VDDIO pins to a
common power supply to ensure the same ramp-up time for
both supply voltages.

Type

LQFP208

USB0_VSSA
_TERM

[1]

TFBGA100

Description

LBGA256

Pin name

VDDIO

D7,
F10,
E12, K5
F7,
F8,
G10,
H10,
J6,
J7,
K7,
L9,
L10,
N7,
N13

6,
52,
57,
102,
110,
155,
160,
202

5,
36,
41,
71,
77,
107,
111,
141

[12]

VSS

G9,
H7,
J10,
J11,
K8

-

-

[13]

-

-

Ground.

VSSIO

C4,
D13,
G6,
G7,
G8,
H8,
H9,
J8,
J9,
K9,
K10,
M13,
P7,
P13

5,
56,
109,
157

4,
40,
76,
109

[13]

-

-

Ground.

VSSA

B2

196

135

-

-

Analog ground.

UM10503

User manual

C8,
D4,
D5,
G8,
J3,
J6

C2

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Chapter 16: LPC43xx/LPC43Sxx Pin configuration

[1]

N = neutral, input buffer disabled; no extra VDDIO current consumption if the input is driven midway between supplies; set the EZI bit in
the SFS register to enable the input buffer; I = input, OL = output driving LOW; OH = output driving HIGH; AI/O = analog input/output; IA
= inactive; PU = pull-up enabled (weak pull-up resistor pulls up pin to VDDIO; F = floating. Reset state reflects the pin state at reset
without boot code operation.

[2]

5 V tolerant pad with 15 ns glitch filter (5 V tolerant if VDDIO present; if VDDIO not present, do not exceed 3.6 V); provides digital I/O
functions with TTL levels and hysteresis; normal drive strength.

[3]

5 V tolerant pad with 15 ns glitch filter (5 V tolerant if VDDIO present; if VDDIO not present, do not exceed 3.6 V); provides digital I/O
functions with TTL levels, and hysteresis; high drive strength.

[4]

5 V tolerant pad with 15 ns glitch filter (5 V tolerant if VDDIO present; if VDDIO not present, do not exceed 3.6 V); provides high-speed
digital I/O functions with TTL levels and hysteresis.

[5]

5 V tolerant pad providing digital I/O functions (with TTL levels and hysteresis) and analog input or output (5 V tolerant if VDDIO present;
if VDDIO not present, do not exceed 3.6 V). When configured as a ADC input or DAC output, the pin is not 5 V tolerant and the digital
section of the pad must be disabled by setting the pin to an input function and disabling the pull-up resistor through the pin’s SFSP
register.

[6]

5 V tolerant transparent analog pad.

[7]

For maximum load CL = 6.5 F and maximum resistance Rpd = 80 k, the VBUS signal takes about 2 s to fall from VBUS = 5 V to VBUS
= 0.2 V when it is no longer driven.

[8]

Transparent analog pad. Not 5 V tolerant.

[9]

Pad provides USB functions; 5 V tolerant if VDDIO present; if VDDIO not present, do not exceed 3.6 V. It is designed in accordance with
the USB specification, revision 2.0 (Full-speed and Low-speed mode only).

[10] Open-drain 5 V tolerant digital I/O pad, compatible with I2C-bus Fast Mode Plus specification. This pad requires an external pull-up to
provide output functionality. When power is switched off, this pin connected to the I2C-bus is floating and does not disturb the I2C lines.
[11] 5 V tolerant pad with 20 ns glitch filter; provides digital I/O functions with open-drain output with weak pull-up resistor and hysteresis.
[12] On the LQFP208, VPP is internally connected to VDDIO.
[13] On the LQFP208 package, VSSIO and VSS are connected to a common ground plane.

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Chapter 17: LPC43xx/LPC43Sxx System Control Unit (SCU)/
IO configuration
Rev. 2.4 — 22 August 2018

User manual

17.1 How to read this chapter
The following peripherals are not available on all parts, and the corresponding bit values
that select those functions in the SFSP registers are reserved:

• Ethernet: available on LPC436x/5x/3x, LPC43S6x/S5x/S3x, and
LPC4370/LPC43S70.

• USB0: available on LPC436x/5x/3x, LPC43S6x/S5x/S3x, and LPC4370/LPC43S70.
• USB1: available on LPC436x/5x/3x, LPC43S6x/S5x/S3x, and LPC4370/LPC43S70.
• LCD: available on LPC436x/5x, LPC43S6x/S5x, and LPC4370/LPC43S70.
Remark: The input channels to the two 10-bit ADCs are tied together for a total of eight
input channels on the following parts:

•
•
•
•
•

LPC436x/LPC43S6x
LPC435x/LPC43S5x
LPC433x/LPC43S3x
LPC432x/LPC43S2x
LPC431x

This means that for the parts with shared input channels, input ADC0_n is connected to
channel n on ADC0 and ADC1 and input ADC1_n is connected to channel n on ADC0 and
ADC1, See Table 197 and Table 199. In addition, the DAC output is shared with both,
ADC0 channel 0 (ADC0_0) and ADC1 channel 0 (ADC1_0). For details on the 10-bit ADC
pinning, see Section 47.1.
Each 10-bit ADC has eight independent input channels for a total of 16 input channels on
the following parts:

• LPC4370

17.2 Basic configuration
The SCU is configured as follows:

• See Table 188 for clocking and power control.
• The SCU is reset by the SCU_RST (reset # 9).
Remark: Before using any of the multiplexed pins or the I2C0 pins as inputs, set the
corresponding pin configuration registers as follows:

• Enable the input buffer by setting bit EZI to 1.
• For high-frequency signals, disable the input glitch filter by setting bit ZIF to 1.

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Chapter 17: LPC43xx/LPC43Sxx System Control Unit (SCU)/ IO

Table 188. SCU clocking and power control
Clock to SCU register interface

Base clock

Branch clock

Operating frequency

BASE_M4_CLK

CLK_M4_SCU

up to 204 MHz

17.3 General description
The system control unit determines the function and electrical mode of most digital pins.
By default, the digital function 0 with pull-up enabled is selected for all pins .
Remark: Some pins support pin muxing of digital and analog functions. All analog I/Os for
the ADC and DAC are also pinned out on analog-only pads without pin muxing.

VDDIO

enable output driver
ESD
PIN

data output from core
slew rate bit EHS
input buffer enable bit EZI

data input to core

glitch
filter

filter select bit ZIF
pull-up enable bit EPUN

ESD

pull-down enable bit EPD

analog I/O

VSSIO

Fig 43. Block diagram of the I/O pad

17.3.1 Digital pin function
The FUNC bits in the SFS registers control the function of each pin. Each pin can support
up to eight digital functions. Some pins support an additional analog function. If the
function is GPIO, the DIR registers determine whether the pin is configured as an input or
output (see Table 261). For any peripheral function, the pin direction is controlled
automatically depending on the pin’s functionality. The GPIO DIR registers do not affect
peripheral functions.

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Chapter 17: LPC43xx/LPC43Sxx System Control Unit (SCU)/ IO

17.3.2 Digital pin mode
The EPUN and EPD bits (see Figure 43) in the SFS registers allow the selection of weak
on-chip pull-up or pull-down resistors with a typical value of 50 k for each pin or the
selection of the repeater mode.
The possible on-chip resistor configurations are pull-up enabled, pull-down enabled, or no
pull-up/pull-down. The default value is pull-up enabled.
The repeater mode enables the pull-up resistor if the pin is at a logic HIGH and enables
the pull-down resistor if the pin is at a logic LOW. This causes the pin to retain its last
known state if it is configured as an input and is not driven externally. Repeater mode may
typically be used to prevent a pin from floating (and potentially using significant power if it
floats to an indeterminate state) if it is temporarily not driven.
To select the repeater mode, enable both the pull-up and the pull-down resistor in the SFS
registers.

17.3.3 Input buffer
To be able to receive a digital signal, the input buffer must be enabled through bit EZI in
the pin configuration registers (see Figure 43). By default, the input buffer is disabled.
For pads that support both a digital and an analog function, the input buffer must be
disabled before enabling the analog function (see Section 17.4.6 to Section 17.4.8).

17.3.4 Programmable glitch filter
All digital pins support a programmable glitch filter (bit ZIF), which can be switched on or
off (see Figure 43). By default, the glitch filter is on. The glitch filter should be disabled for
clocking signals with frequencies higher than 30 MHz.

17.3.5 Programmable slew rate
Normal-drive and high-speed pins support a programmable slew rate (bit EHS) to select
between lower noise and speed or higher noise and speed (see Figure 43). The typical
frequencies supported are 50 MHz/80 MHz for normal-drive pins and 75 MHz/204 MHz for
high-speed pins.

17.3.6 High-speed pins
The clock pins CLK0 to CLK3 and P3_3 support a programmable high-speed output with
typical frequencies of 75 MHz or 204 MHz depending on the slew rate setting (see
Section 17.3.5).

17.3.7 High-drive pins
Selected pins (see Section 17.4.2) support a high-drive output with four programmable
levels.
High-drive pins support the programmable glitch filter but not the programmable slew rate.

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Chapter 17: LPC43xx/LPC43Sxx System Control Unit (SCU)/ IO

17.3.8 I2C0-bus pins
The SFSI2C0 register (Table 195) allows to configure different modes for I2C0-bus
interface:

• Standard mode/Fast-mode I2C with an open-drain output according to the I2C-bus
specification. This is the default mode.

• Fast-mode Plus mode with an open-drain output according to the I2C-bus
specification.
The I2C0 pins use a programmable glitch filter (bit ZIF).
Remark: The input buffer must be enabled for the I2C0 pins SDA and SCL for proper
operation.

17.3.9 USB1 USB1_DP/USB1_DM pins
The input signal to the USB1 is controlled by the SFSUSB register (Table 194). The
USB_ESEA bit in this register must be set to one to enable the USB1 block.

17.3.10 EMC signal delay control
The SCU contains a programmable delay control for all EMC SDRAM clocks
(seeTable 202).

17.3.11 Pin multiplexing
Multiplexed digital pins are grouped into 16 pin groups, named P0 to P9 and PA to PF,
with up to 20 pins used per group. Each digital pin can support up to eight different digital
functions, including General Purpose I/O (GPIO), selectable through the SCU registers. In
addition, some pins support an analog function (ADC inputs and DAC output) selectable
through the ENAIO registers. Note that the pin name is not indicative of the GPIO port
assigned to it.

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xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx
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xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
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NXP Semiconductors

UM10503

User manual

Table 189. Pin multiplexing
FUNC1

FUNC2

FUNC3

FUNC4

FUNC5

FUNC6

FUNC7

P0_0

GPIO0[0]

SSP1_MISO

ENET_RXD1

SGPIO0

R

R

I2S0_TX_WS

I2S1_TX_WS

P0_1

GPIO0[1]

SSP1_MOSI

ENET_COL

SGPIO1

R

R

ENET_TX_EN

I2S1_TX_SD
A

P1_0

GPIO0[4]

CTIN_3

EMC_A5

R

R

SSP0_SSEL

SGPIO7

R

P1_1

GPIO0[8]

CTOUT_7

EMC_A6

SGPIO8

R

SSP0_MISO

R

R

P1_2

GPIO0[9]

CTOUT_6

EMC_A7

SGPIO9

R

SSP0_MOSI

R

R

P1_3

GPIO0[10]

CTOUT_8

SGPIO10

EMC_OE

USB0_IND1

SSP1_MISO

R

SD_RST

P1_4

GPIO0[11]

CTOUT_9

SGPIO11

EMC_BLS0

USB0_IND0

SSP1_MOSI

R

SD_VOLT1

P1_5

GPIO1[8]

CTOUT_10

R

EMC_CS0

USB0_PWR SSP1_SSEL
_FAULT

SGPIO15

SD_POW

P1_6

GPIO1[9]

CTIN_5

R

EMC_WE

R

R

SGPIO14

SD_CMD

P1_7

GPIO1[0]

U1_DSR

CTOUT_13

EMC_D0

USB0_PPW
R

R

R

R

P1_8

GPIO1[1]

U1_DTR

CTOUT_12

EMC_D1

R

R

R

SD_VOLT0

P1_9

GPIO1[2]

U1_RTS

CTOUT_11

EMC_D2

R

R

R

SD_DAT0

P1_10

GPIO1[3]

U1_RI

CTOUT_14

EMC_D3

R

R

R

SD_DAT1

P1_11

GPIO1[4]

U1_CTS

CTOUT_15

EMC_D4

R

R

R

SD_DAT2

P1_12

GPIO1[5]

U1_DCD

R

EMC_D5

T0_CAP1

R

SGPIO8

SD_DAT3

P1_13

GPIO1[6]

U1_TXD

R

EMC_D6

T0_CAP0

R

SGPIO9

SD_CD

P1_14

GPIO1[7]

U1_RXD

R

EMC_D7

T0_MAT2

R

SGPIO10

R

P1_15

GPIO0[2]

U2_TXD

SGPIO2

ENET_RXD0

T0_MAT1

R

R

R

P1_16

GPIO0[3]

U2_RXD

SGPIO3

ENET_CRS

T0_MAT0

R

R

ENET_RX_D
V

P1_17

GPIO0[12]

U2_UCLK

R

ENET_MDIO

T0_CAP3

CAN1_TD

SGPIO11

R

P1_18

GPIO0[13]

U2_DIR

R

ENET_TXD0

T0_MAT3

CAN1_RD

SGPIO12

R

P1_19

ENET_TX_CLK
(ENET_REF_
CLK)

SSP1_SCK

R

R

CLKOUT

R

I2S0_RX_MCL I2S1_TX_SC
K
K

P1_20

GPIO0[15]

SSP1_SSEL

R

ENET_TXD1

T0_CAP2

R

SGPIO13

R

P2_0

SGPIO4

U0_TXD

EMC_A13

USB0_PPWR

GPIO5[0]

R

T3_CAP0

ENET_MDC

ANALOG
SEL

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FUNC0

Chapter 17: LPC43xx/LPC43Sxx System Control Unit (SCU)/ IO

Rev. 2.4 — 22 August 2018

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Pin

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx
xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
FUNC1

FUNC2

FUNC3

FUNC4

FUNC5

FUNC6

FUNC7

ANALOG
SEL

P2_1

SGPIO5

U0_RXD

EMC_A12

USB0_PWR_F
AULT

GPIO5[1]

R

T3_CAP1

R

P2_2

SGPIO6

U0_UCLK

EMC_A11

USB0_IND1

GPIO5[2]

CTIN_6

T3_CAP2

R

P2_3

SGPIO12

I2C1_SDA

U3_TXD

CTIN_1

GPIO5[3]

R

T3_MAT0

USB0_PPWR

P2_4

SGPIO13

I2C1_SCL

U3_RXD

CTIN_0

GPIO5[4]

R

T3_MAT1

USB0_PWR_
FAULT

P2_5

SGPIO14

CTIN_2

USB1_VBUS

ADCTRIG1

GPIO5[5]

R

T3_MAT2

USB0_IND0

P2_6

SGPIO7

U0_DIR

EMC_A10

USB0_IND0

GPIO5[6]

CTIN_7

T3_CAP3

R

P2_7

GPIO0[7]

CTOUT_1

U3_UCLK

EMC_A9

R

R

T3_MAT3

R

P2_8

SGPIO15

CTOUT_0

U3_DIR

EMC_A8

GPIO5[7]

R

R

R

P2_9

GPIO1[10]

CTOUT_3

U3_BAUD

EMC_A0

R

R

R

R

P2_10

GPIO0[14]

CTOUT_2

U2_TXD

EMC_A1

R

R

R

R

P2_11

GPIO1[11]

CTOUT_5

U2_RXD

EMC_A2

R

R

R

R

P2_12

GPIO1[12]

CTOUT_4

R

EMC_A3

R

R

R

U2_UCLK

P2_13

GPIO1[13]

CTIN_4

R

EMC_A4

R

R

R

U2_DIR

P3_0

I2S0_RX_SCK

I2S0_RX_MCLK

I2S0_TX_SCK

I2S0_TX_MCL
K

SSP0_SCK

R

R

R

P3_1

I2S0_TX_WS

I2S0_RX_WS

CAN0_RD

USB1_IND1

GPIO5[8]

R

LCD_VD15

R

P3_2

I2S0_TX_SDA

I2S0_RX_SDA

CAN0_TD

USB1_IND0

GPIO5[9]

R

LCD_VD14

R

P3_3

R

SPI_SCK

SSP0_SCK

SPIFI_SCK

CGU_OUT1

R

I2S0_TX_MCL
K

I2S1_TX_SC
K

P3_4

GPIO1[14]

R

R

SPIFI_SIO3

U1_TXD

I2S0_TX_WS

I2S1_RX_SDA

LCD_VD13

P3_5

GPIO1[15]

R

R

SPIFI_SIO2

U1_RXD

I2S0_TX_SDA

I2S1_RX_WS

LCD_VD12

P3_6

GPIO0[6]

SPI_MISO

SSP0_SSEL

SPIFI_MISO

R

SSP0_MISO

R

R

P3_7

R

SPI_MOSI

SSP0_MISO

SPIFI_MOSI

GPIO5[10]

SSP0_MOSI

R

R

P3_8

R

SPI_SSEL

SSP0_MOSI

SPIFI_CS

GPIO5[11]

SSP0_SSEL

R

R

P4_0

GPIO2[0]

MCOA0

NMI

R

R

LCD_VD13

U3_UCLK

R

P4_1

GPIO2[1]

CTOUT_1

LCD_VD0

R

R

LCD_VD19

U3_TXD

ENET_COL

P4_2

GPIO2[2]

CTOUT_0

LCD_VD3

R

R

LCD_VD12

U3_RXD

SGPIO8

P4_3

GPIO2[3]

CTOUT_3

LCD_VD2

R

R

LCD_VD21

U3_BAUD

SGPIO9

ADC0_0

P4_4

GPIO2[4]

CTOUT_2

LCD_VD1

R

R

LCD_VD20

U3_DIR

SGPIO10

DAC

ADC0_1

UM10503

407 of 1444

© NXP B.V. 2018. All rights reserved.

FUNC0

Chapter 17: LPC43xx/LPC43Sxx System Control Unit (SCU)/ IO

Rev. 2.4 — 22 August 2018

All information provided in this document is subject to legal disclaimers.

Pin

NXP Semiconductors

UM10503

User manual

Table 189. Pin multiplexing

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx
xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
Pin

FUNC0

FUNC1

FUNC2

FUNC3

FUNC4

FUNC5

FUNC6

FUNC7

P4_5

GPIO2[5]

CTOUT_5

LCD_FP

R

R

R

R

SGPIO11

P4_6

GPIO2[6]

CTOUT_4

LCD_ENAB/LCD R
M

R

R

R

SGPIO12

P4_7

LCD_DCLK

GP_CLKIN

R

R

R

R

I2S1_TX_SCK

I2S0_TX_SC
K

P4_8

R

CTIN_5

LCD_VD9

R

GPIO5[12]

LCD_VD22

CAN1_TD

SGPIO13

P4_9

R

CTIN_6

LCD_VD11

R

GPIO5[13]

LCD_VD15

CAN1_RD

SGPIO14

P4_10

R

CTIN_2

LCD_VD10

R

GPIO5[14]

LCD_VD14

R

SGPIO15

P5_0

GPIO2[9]

MCOB2

EMC_D12

R

U1_DSR

T1_CAP0

R

R

MCI2

EMC_D13

R

U1_DTR

T1_CAP1

R

R

GPIO2[11]

MCI1

EMC_D14

R

U1_RTS

T1_CAP2

R

R

P5_3

GPIO2[12]

MCI0

EMC_D15

R

U1_RI

T1_CAP3

R

R

P5_4

GPIO2[13]

MCOB0

EMC_D8

R

U1_CTS

T1_MAT0

R

R

P5_5

GPIO2[14]

MCOA1

EMC_D9

R

U1_DCD

T1_MAT1

R

R

P5_6

GPIO2[15]

MCOB1

EMC_D10

R

U1_TXD

T1_MAT2

R

R

P5_7

GPIO2[7]

MCOA2

EMC_D11

R

U1_RXD

T1_MAT3

R

R

P6_0

R

I2S0_RX_MCLK

R

R

I2S0_RX_S
CK

R

R

R

P6_1

GPIO3[0]

EMC_DYCS1

U0_UCLK

I2S0_RX_WS

R

T2_CAP0

R

R

P6_2

GPIO3[1]

EMC_CKEOUT1

U0_DIR

I2S0_RX_SDA

R

T2_CAP1

R

R

P6_3

GPIO3[2]

USB0_PPWR

SGPIO4

EMC_CS1

R

T2_CAP2

R

R

P6_4

GPIO3[3]

CTIN_6

U0_TXD

EMC_CAS

R

R

R

R

P6_5

GPIO3[4]

CTOUT_6

U0_RXD

EMC_RAS

R

R

R

R

P6_6

GPIO0[5]

EMC_BLS1

SGPIO5

USB0_PWR_F
AULT

R

T2_CAP3

R

R

P6_7

R

EMC_A15

SGPIO6

USB0_IND1

GPIO5[15]

T2_MAT0

R

R

P6_8

R

EMC_A14

SGPIO7

USB0_IND0

GPIO5[16]

T2_MAT1

R

R

P6_9

GPIO3[5]

R

R

EMC_DYCS0

R

T2_MAT2

R

R

P6_10

GPIO3[6]

MCABORT

R

EMC_DQMOU
T1

R

R

R

R

P6_11

GPIO3[7]

R

R

EMC_CKEOUT R
0

T2_MAT3

R

R

UM10503

408 of 1444

© NXP B.V. 2018. All rights reserved.

GPIO2[10]

P5_2

ANALOG
SEL

Chapter 17: LPC43xx/LPC43Sxx System Control Unit (SCU)/ IO

Rev. 2.4 — 22 August 2018

All information provided in this document is subject to legal disclaimers.

P5_1

NXP Semiconductors

UM10503

User manual

Table 189. Pin multiplexing

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx
xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
Pin

FUNC0

FUNC1

FUNC2

FUNC3

FUNC4

FUNC5

FUNC6

FUNC7

P6_12

GPIO2[8]

CTOUT_7

R

EMC_DQMOU
T0

R

R

R

R

P7_0

GPIO3[8]

CTOUT_14

R

LCD_LE

R

R

R

SGPIO4

P7_1

GPIO3[9]

CTOUT_15

I2S0_TX_WS

LCD_VD19

LCD_VD7

R

U2_TXD

SGPIO5

P7_2

GPIO3[10]

CTIN_4

I2S0_TX_SDA

LCD_VD18

LCD_VD6

R

U2_RXD

SGPIO6

ANALOG
SEL

GPIO3[11]

CTIN_3

R

LCD_VD17

LCD_VD5

R

R

R

P7_4

GPIO3[12]

CTOUT_13

R

LCD_VD16

LCD_VD4

TRACEDATA[0]

R

R

ADC0_4

P7_5

GPIO3[13]

CTOUT_12

R

LCD_VD8

LCD_VD23

TRACEDATA[1]

R

R

ADC0_3

P7_6

GPIO3[14]

CTOUT_11

R

LCD_LP

R

TRACEDATA[2]

R

R

P7_7

GPIO3[15]

CTOUT_8

R

LCD_PWR

R

TRACEDATA[3]

ENET_MDC

SGPIO7

P8_0

GPIO4[0]

USB0_PWR_FAU R
LT

MCI2

SGPIO8

R

R

T0_MAT0

P8_1

GPIO4[1]

USB0_IND1

MCI1

SGPIO9

R

R

T0_MAT1

P8_2

GPIO4[2]

USB0_IND0

R

MCI0

SGPIO10

R

R

T0_MAT2

P8_3

GPIO4[3]

USB1_ULPI_D2

R

LCD_VD12

LCD_VD19

R

R

T0_MAT3

P8_4

GPIO4[4]

USB1_ULPI_D1

R

LCD_VD7

LCD_VD16

R

R

T0_CAP0

P8_5

GPIO4[5]

USB1_ULPI_D0

R

LCD_VD6

LCD_VD8

R

R

T0_CAP1

GPIO4[6]

USB1_ULPI_NXT R

LCD_VD5

LCD_LP

R

R

T0_CAP2

P8_7

GPIO4[7]

USB1_ULPI_STP R

LCD_VD4

LCD_PWR

R

R

T0_CAP3

P8_8

R

USB1_ULPI_CLK R

R

R

R

CGU_OUT0

I2S1_TX_MC
LK

P9_0

GPIO4[12]

MCABORT

R

R

R

ENET_CRS

SGPIO0

SSP0_SSEL

P9_1

GPIO4[13]

MCOA2

R

R

I2S0_TX_W
S

ENET_RX_ER

SGPIO1

SSP0_MISO

P9_2

GPIO4[14]

MCOB2

R

R

I2S0_TX_S
DA

ENET_RXD3

SGPIO2

SSP0_MOSI

P9_3

GPIO4[15]

MCOA0

USB1_IND1

R

R

ENET_RXD2

SGPIO9

U3_TXD

P9_4

R

MCOB0

USB1_IND0

R

GPIO5[17]

ENET_TXD2

SGPIO4

U3_RXD

P9_5

R

MCOA1

USB1_PPWR

R

GPIO5[18]

ENET_TXD3

SGPIO3

U0_TXD

P9_6

GPIO4[11]

MCOB1

USB1_PWR_FA
ULT

R

R

ENET_COL

SGPIO8

U0_RXD

PA_0

R

R

R

R

R

I2S1_RX_MCLK CGU_OUT1

R

UM10503

409 of 1444

© NXP B.V. 2018. All rights reserved.

P8_6

ADC1_6

Chapter 17: LPC43xx/LPC43Sxx System Control Unit (SCU)/ IO

Rev. 2.4 — 22 August 2018

All information provided in this document is subject to legal disclaimers.

P7_3

R

NXP Semiconductors

UM10503

User manual

Table 189. Pin multiplexing

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx
xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
FUNC1

FUNC2

FUNC3

FUNC4

FUNC5

FUNC6

FUNC7

PA_1

GPIO4[8]

QEI_IDX

R

U2_TXD

R

R

R

R

PA_2

GPIO4[9]

QEI_PHB

R

U2_RXD

R

R

R

R

PA_3

GPIO4[10]

QEI_PHA

R

R

R

R

R

R

PA_4

R

CTOUT_9

R

EMC_A23

GPIO5[19]

R

R

R

PB_0

R

CTOUT_10

LCD_VD23

R

GPIO5[20]

R

R

R

PB_1

R

USB1_ULPI_DIR

LCD_VD22

R

GPIO5[21]

CTOUT_6

R

R

PB_2

R

USB1_ULPI_D7

LCD_VD21

R

GPIO5[22]

CTOUT_7

R

R

PB_3

R

USB1_ULPI_D6

LCD_VD20

R

GPIO5[23]

CTOUT_8

R

R

PB_4

R

USB1_ULPI_D5

LCD_VD15

R

GPIO5[24]

CTIN_5

R

R

PB_5

R

USB1_ULPI_D4

LCD_VD14

R

GPIO5[25]

CTIN_7

LCD_PWR

R

PB_6

R

USB1_ULPI_D3

LCD_VD13

R

GPIO5[26]

CTIN_6

LCD_VD19

R

ADC0_6

PC_0

R

USB1_ULPI_CLK R

ENET_RX_CL
K

LCD_DCLK

R

R

SD_CLK

ADC1_1

PC_1

USB1_ULPI_D7 R

U1_RI

ENET_MDC

GPIO6[0]

R

T3_CAP0

SD_VOLT0

PC_2

USB1_ULPI_D6 R

U1_CTS

ENET_TXD2

GPIO6[1]

R

R

SD_RST

PC_3

USB1_ULPI_D5 R

U1_RTS

ENET_TXD3

GPIO6[2]

R

R

SD_VOLT1

PC_4

R

USB1_ULPI_D4

R

ENET_TX_EN

GPIO6[3]

R

T3_CAP1

SD_DAT0

PC_5

R

USB1_ULPI_D3

R

ENET_TX_ER

GPIO6[4]

R

T3_CAP2

SD_DAT1

PC_6

R

USB1_ULPI_D2

R

ENET_RXD2

GPIO6[5]

R

T3_CAP3

SD_DAT2

PC_7

R

USB1_ULPI_D1

R

ENET_RXD3

GPIO6[6]

R

T3_MAT0

SD_DAT3

PC_8

R

USB1_ULPI_D0

R

ENET_RX_DV

GPIO6[7]

R

T3_MAT1

SD_CD

PC_9

R

USB1_ULPI_NXT R

ENET_RX_ER

GPIO6[8]

R

T3_MAT2

SD_POW

PC_10

R

USB1_ULPI_STP U1_DSR

R

GPIO6[9]

R

T3_MAT3

SD_CMD

PC_11

R

USB1_ULPI_DIR

U1_DCD

R

GPIO6[10]

R

R

SD_DAT4

PC_12

R

R

U1_DTR

R

GPIO6[11]

SGPIO11

I2S0_TX_SDA

SD_DAT5

PC_13

R

R

U1_TXD

R

GPIO6[12]

SGPIO12

I2S0_TX_WS

SD_DAT6

PC_14

R

R

U1_RXD

R

GPIO6[13]

SGPIO13

ENET_TX_ER

SD_DAT7

PD_0

R

CTOUT_15

EMC_DQMOUT2 R

GPIO6[14]

R

R

SGPIO4

PD_1

R

R

EMC_CKEOUT2 R

GPIO6[15]

SD_POW

R

SGPIO5

PD_2

R

CTOUT_7

EMC_D16

GPIO6[16]

R

R

SGPIO6

R

ANALOG
SEL

ADC1_0

UM10503

410 of 1444

© NXP B.V. 2018. All rights reserved.

FUNC0

Chapter 17: LPC43xx/LPC43Sxx System Control Unit (SCU)/ IO

Rev. 2.4 — 22 August 2018

All information provided in this document is subject to legal disclaimers.

Pin

NXP Semiconductors

UM10503

User manual

Table 189. Pin multiplexing

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx
xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
Pin

FUNC0

FUNC1

FUNC2

FUNC3

FUNC4

FUNC5

FUNC6

FUNC7

PD_3

R

CTOUT_6

EMC_D17

R

GPIO6[17]

R

R

SGPIO7

PD_4

R

CTOUT_8

EMC_D18

R

GPIO6[18]

R

R

SGPIO8

PD_5

R

CTOUT_9

EMC_D19

R

GPIO6[19]

R

R

SGPIO9

PD_6

R

CTOUT_10

EMC_D20

R

GPIO6[20]

R

R

SGPIO10

PD_7

R

CTIN_5

EMC_D21

R

GPIO6[21]

R

R

SGPIO11

R

CTIN_6

EMC_D22

R

GPIO6[22]

R

R

SGPIO12

PD_9

R

CTOUT_13

EMC_D23

R

GPIO6[23]

R

R

SGPIO13

PD_10

R

CTIN_1

EMC_BLS3

R

GPIO6[24]

R

R

R

PD_11

R

R

EMC_CS3

R

GPIO6[25]

USB1_ULPI_D0 CTOUT_14

PD_12

R

R

EMC_CS2

R

GPIO6[26]

R

CTOUT_10

R

PD_13

R

CTIN_0

EMC_BLS2

R

GPIO6[27]

R

CTOUT_13

R

PD_14

R

R

EMC_DYCS2

R

GPIO6[28]

R

CTOUT_11

R

PD_15

R

R

EMC_A17

R

GPIO6[29]

SD_WP

CTOUT_8

R

ANALOG
SEL

R

PD_16

R

R

EMC_A16

R

GPIO6[30]

SD_VOLT2

CTOUT_12

R

PE_0

R

R

R

EMC_A18

GPIO7[0]

CAN1_TD

R

R

PE_1

R

R

R

EMC_A19

GPIO7[1]

CAN1_RD

R

R

PE_2

ADCTRIG0

CAN0_RD

R

EMC_A20

GPIO7[2]

R

R

R

R

CAN0_TD

ADCTRIG1

EMC_A21

GPIO7[3]

R

R

R

PE_4

R

NMI

R

EMC_A22

GPIO7[4]

R

R

R

PE_5

R

CTOUT_3

U1_RTS

EMC_D24

GPIO7[5]

R

R

R

PE_6

R

CTOUT_2

U1_RI

EMC_D25

GPIO7[6]

R

R

R

PE_7

R

CTOUT_5

U1_CTS

EMC_D26

GPIO7[7]

R

R

R

PE_8

R

CTOUT_4

U1_DSR

EMC_D27

GPIO7[8]

R

R

R

PE_9

R

CTIN_4

U1_DCD

EMC_D28

GPIO7[9]

R

R

R

PE_10

R

CTIN_3

U1_DTR

EMC_D29

GPIO7[10]

R

R

R

411 of 1444

© NXP B.V. 2018. All rights reserved.

PE_11

R

CTOUT_12

U1_TXD

EMC_D30

GPIO7[11]

R

R

R

PE_12

R

CTOUT_11

U1_RXD

EMC_D31

GPIO7[12]

R

R

R

PE_13

R

CTOUT_14

I2C1_SDA

EMC_DQMOU
T3

GPIO7[13]

R

R

R

PE_14

R

R

R

EMC_DYCS3

GPIO7[14]

R

R

R

UM10503

PE_3

Chapter 17: LPC43xx/LPC43Sxx System Control Unit (SCU)/ IO

Rev. 2.4 — 22 August 2018

All information provided in this document is subject to legal disclaimers.

PD_8

NXP Semiconductors

UM10503

User manual

Table 189. Pin multiplexing

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx
xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
Pin

FUNC0

FUNC1

FUNC2

FUNC3

PE_15

R

CTOUT_0

I2C1_SCL

PF_0

SSP0_SCK

GP_CLKIN

PF_1

R

R

FUNC4

FUNC5

FUNC6

FUNC7

EMC_CKEOUT GPIO7[15]
3

R

R

R

R

R

R

R

R

I2S1_TX_MC
LK

SSP0_SSEL

R

GPIO7[16]

R

SGPIO0

R

PF_2

R

U3_TXD

SSP0_MISO

R

GPIO7[17]

R

SGPIO1

R

PF_3

R

U3_RXD

SSP0_MOSI

R

GPIO7[18]

R

SGPIO2

R

PF_4

SSP1_SCK

GP_CLKIN

TRACECLK

R

R

R

I2S0_TX_MCL
K

I2S0_RX_SC
K

NXP Semiconductors

UM10503

User manual

Table 189. Pin multiplexing
ANALOG
SEL

R

U3_UCLK

SSP1_SSEL

TRACEDATA[0] GPIO7[19]

R

SGPIO4

R

ADC1_4

PF_6

R

U3_DIR

SSP1_MISO

TRACEDATA[1] GPIO7[20]

R

SGPIO5

I2S1_TX_SD
A

ADC1_3

PF_7

R

U3_BAUD

SSP1_MOSI

TRACEDATA[2] GPIO7[21]

R

SGPIO6

I2S1_TX_WS

ADC1_7

PF_8

R

U0_UCLK

CTIN_2

TRACEDATA[3] GPIO7[22]

R

SGPIO7

R

ADC0_2

PF_9

R

U0_DIR

CTOUT_1

R

GPIO7[23]

R

SGPIO3

R

ADC1_2

PF_10

R

U0_TXD

R

R

GPIO7[24]

R

SD_WP

R

ADC0_5

PF_11

R

U0_RXD

R

R

GPIO7[25]

R

SD_VOLT2

R

ADC1_5

CLK0

EMC_CLK0

CLKOUT

R

R

SD_CLK

EMC_CLK01

SSP1_SCK

ENET_TX_CL
K
(ENET_REF_
CLK)

CLK1

EMC_CLK1

CLKOUT

R

R

R

CGU_OUT0

R

I2S1_TX_MC
LK

CLK2

EMC_CLK3

CLKOUT

R

R

SD_CLK

EMC_CLK23

I2S0_TX_MCL
K

I2S1_RX_SC
K

CLK3

EMC_CLK2

CLKOUT

R

R

R

CGU_OUT1

R

I2S1_RX_SC
K

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UM10503

NXP Semiconductors

Chapter 17: LPC43xx/LPC43Sxx System Control Unit (SCU)/ IO

17.4 Register description
The system control unit contains the registers to configure the pin function of multiplexed
digital pins, the EMC clock delays, and the GPIO pin interrupts.
Remark: The boot loader configures the pins involved in the boot process (see
Section 5.3.2) when the part starts up. The reset values given in Table 190 for the pin
configuration registers and EMC delay registers do not take into account the changes
performed by the boot loader.
Table 190. Register overview: System Control Unit (SCU) (base address 0x4008 6000)
Name

Access Address Description
offset

Reset
value

Reset
value
after
EMC
boot

Reset
value
after
UART
boot

Reference

SFSP0_0

R/W

0x000

Pin configuration register for pin P0_0

0x00

0x00

0x00

Table 191

SFSP0_1

R/W

0x004

Pin configuration register for pin P0_1

0x00

0x00

0x00

Table 191

-

-

0x008 0x07C

Reserved

-

-

-

SFSP1_0

R/W

0x080

Pin configuration register for pin P1_0

0x00

0xD2

0x00

Table 191

SFSP1_1

R/W

0x084

Pin configuration register for pin P1_1

0x00

0xD2

0x00

Table 191

SFSP1_2

R/W

0x088

Pin configuration register for pin P1_2

0x00

0xD2

0x00

Table 191

SFSP1_3

R/W

0x08C

Pin configuration register for pin P1_3

0x00

0xD3

0x00

Table 191

SFSP1_4

R/W

0x090

Pin configuration register for pin P1_4

0x00

0xD3

0x00

Table 191

SFSP1_5

R/W

0x094

Pin configuration register for pin P1_5

0x00

0xD3

0x00

Table 191

SFSP1_6

R/W

0x098

Pin configuration register for pin P1_6

0x00

0xD3

0x00

Table 191

SFSP1_7

R/W

0x09C

Pin configuration register for pin P1_7

0x00

0xD3

0x00

Table 191

SFSP1_8

R/W

0x0A0

Pin configuration register for pin P1_8

0x00

0xD3

0x00

Table 191

SFSP1_9

R/W

0x0A4

Pin configuration register for pin P1_9

0x00

0xD3

0x00

Table 191

SFSP1_10

R/W

0x0A8

Pin configuration register for pin P1_10 0x00

0xD3

0x00

Table 191

SFSP1_11

R/W

0x0AC

Pin configuration register for pin P1_11

0x00

0xD3

0x00

Table 191

SFSP1_12

R/W

0x0B0

Pin configuration register for pin P1_12 0x00

0xD3

0x00

Table 191

SFSP1_13

R/W

0x0B4

Pin configuration register for pin P1_13 0x00

0xD3

0x00

Table 191

SFSP1_14

R/W

0x0B8

Pin configuration register for pin P1_14 0x00

0xD3

0x00

Table 191

SFSP1_15

R/W

0x0BC

Pin configuration register for pin P1_15 0x00

0x00

0x00

Table 191

SFSP1_16

R/W

0x0C0

Pin configuration register for pin P1_16 0x00

0x00

0x00

Table 191

SFSP1_17

R/W

0x0C4

Pin configuration register for pin P1_17 0x00

0x00

0x00

Table 192

SFSP1_18

R/W

0x0C8

Pin configuration register for pin P1_18 0x00

0x00

0x00

Table 191

SFSP1_19

R/W

0x0CC

Pin configuration register for pin P1_19 0x00

0x00

0x00

Table 191

SFSP1_20

R/W

0x0D0

Pin configuration register for pin P1_20 0x00

0x00

0x00

Table 191

-

-

0x0D4 0x0FC

Reserved

-

-

Pins P0_n

Pins P1_n

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Chapter 17: LPC43xx/LPC43Sxx System Control Unit (SCU)/ IO

Table 190. Register overview: System Control Unit (SCU) (base address 0x4008 6000)
…continued

Name

Access Address Description
offset

Reset
value

Reset
value
after
EMC
boot

Reset
value
after
UART
boot

Reference

SFSP2_0

R/W

0x100

Pin configuration register for pin P2_0

0x00

0xD8

0xD1
(UART
0)

Table 191

SFSP2_1

R/W

0x104

Pin configuration register for pin P2_1

0x00

0xD2

0xD1
(UART
0)

Table 191

SFSP2_2

R/W

0x108

Pin configuration register for pin P2_2

0x00

0xD2

SFSP2_3

R/W

0x10C

Pin configuration register for pin P2_3

0x00

0x00

0xD2
(UART
3)

Table 192

SFSP2_4

R/W

0x110

Pin configuration register for pin P2_4

0x00

0x00

0xD2
(UART
3)

Table 192

SFSP2_5

R/W

0x114

Pin configuration register for pin P2_5

0x00

0x00

0x00

Table 192

SFSP2_6

R/W

0x118

Pin configuration register for pin P2_6

0x00

0xD2

0x00

Table 191

SFSP2_7

R/W

0x11C

Pin configuration register for pin P2_7

0x00

0xD3

0x00

Table 191

SFSP2_8

R/W

0x120

Pin configuration register for pin P2_8

0x00

0xD3

0x00

Table 191

SFSP2_9

R/W

0x124

Pin configuration register for pin P2_9

0x00

0xD3

0x00

Table 191

SFSP2_10

R/W

0x128

Pin configuration register for pin P2_10 0x00

0xD3

0x00

Table 191

SFSP2_11

R/W

0x12C

Pin configuration register for pin P2_11

0x00

0xD3

0x00

Table 191

SFSP2_12

R/W

0x130

Pin configuration register for pin P2_12 0x00

0xD3

0x00

Table 191

SFSP2_13

R/W

0x134

Pin configuration register for pin P2_13 0x00

0xD3

0x00

Table 191

-

-

0x138 0x17C

Reserved

-

-

-

-

SFSP3_0

R/W

0x180

Pin configuration register for pin P3_0

0x00

0x00

0x00

Table 191

SFSP3_1

R/W

0x184

Pin configuration register for pin P3_1

0x00

0x00

0x00

Table 191

SFSP3_2

R/W

0x188

Pin configuration register for pin P3_2

0x00

0x00

0x00

Table 191

SFSP3_3

R/W

0x18C

Pin configuration register for pin P3_3

0x00

0x00

0x00

Table 193

SFSP3_4

R/W

0x190

Pin configuration register for pin P3_4

0x00

0x00

0x00

Table 191

SFSP3_5

R/W

0x194

Pin configuration register for pin P3_5

0x00

0x00

0x00

Table 191

SFSP3_6

R/W

0x198

Pin configuration register for pin P3_6

0x00

0x00

0x00

Table 191

SFSP3_7

R/W

0x19C

Pin configuration register for pin P3_7

0x00

0x00

0x00

Table 191

SFSP3_8

R/W

0x1A0

Pin configuration register for pin P3_8

0x00

0x00

0x00

Table 191

-

-

0x1A4 0x1FC

Reserved

-

-

-

R/W

0x200

Pin configuration register for pin P4_0

0x00

0x00

0x00

Pins P2_n

Table 191

Pins P3_n

Pins P4_n
SFSP4_0

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Chapter 17: LPC43xx/LPC43Sxx System Control Unit (SCU)/ IO

Table 190. Register overview: System Control Unit (SCU) (base address 0x4008 6000)
…continued

Name

Access Address Description
offset

Reset
value

Reset
value
after
EMC
boot

Reset
value
after
UART
boot

Reference

SFSP4_1

R/W

0x204

Pin configuration register for pin P4_1

0x00

0x00

0x00

Table 191/
Table 197

SFSP4_2

R/W

0x208

Pin configuration register for pin P4_2

0x00

0x00

0x00

Table 191

SFSP4_3

R/W

0x20C

Pin configuration register for pin P4_3

0x00

0x00

0x00

Table 191/
Table 197

SFSP4_4

R/W

0x210

Pin configuration register for pin P4_4

0x00

0x00

0x00

Table 191/
Table 201

SFSP4_5

R/W

0x214

Pin configuration register for pin P4_5

0x00

0x00

0x00

Table 191

SFSP4_6

R/W

0x218

Pin configuration register for pin P4_6

0x00

0x00

0x00

Table 191

SFSP4_7

R/W

0x21C

Pin configuration register for pin P4_7

0x00

0x00

0x00

Table 191

SFSP4_8

R/W

0x220

Pin configuration register for pin P4_8

0x00

0x00

0x00

Table 191

SFSP4_9

R/W

0x224

Pin configuration register for pin P4_9

0x00

0x00

0x00

Table 191

SFSP4_10

R/W

0x228

Pin configuration register for pin P4_10 0x00

0x00

0x00

Table 191

-

-

0x22C 0x27C

Reserved

-

-

-

SFSP5_0

R/W

0x280

Pin configuration register for pin P5_0

0x00

0xD2

0x00

Table 191

SFSP5_1

R/W

0x284

Pin configuration register for pin P5_1

0x00

0xD2

0x00

Table 191

SFSP5_2

R/W

0x288

Pin configuration register for pin P5_2

0x00

0xD2

0x00

Table 191

SFSP5_3

R/W

0x28C

Pin configuration register for pin P5_3

0x00

0xD2

0x00

Table 191

SFSP5_4

R/W

0x290

Pin configuration register for pin P5_4

0x00

0xD2

0x00

Table 191

SFSP5_5

R/W

0x294

Pin configuration register for pin P5_5

0x00

0xD2

0x00

Table 191

SFSP5_6

R/W

0x298

Pin configuration register for pin P5_6

0x00

0xD2

0x00

Table 191

SFSP5_7

R/W

0x29C

Pin configuration register for pin P5_7

0x00

0xD2

0x00

Table 191

-

-

0x2A0 0x2FC

Reserved

-

-

-

-

SFSP6_0

R/W

0x300

Pin configuration register for pin P6_0

0x00

0x00

0x00

Table 191

SFSP6_1

R/W

0x304

Pin configuration register for pin P6_1

0x00

0x00

0x00

Table 191

SFSP6_2

R/W

0x308

Pin configuration register for pin P6_2

0x00

0x00

0x00

Table 191

SFSP6_3

R/W

0x30C

Pin configuration register for pin P6_3

0x00

0x00

0x00

Table 191

SFSP6_4

R/W

0x310

Pin configuration register for pin P6_4

0x00

0x00

0x00

Table 191

SFSP6_5

R/W

0x314

Pin configuration register for pin P6_5

0x00

0x00

0x00

Table 191

SFSP6_6

R/W

0x318

Pin configuration register for pin P6_6

0x00

0xD1

0x00

Table 191

SFSP6_7

R/W

0x31C

Pin configuration register for pin P6_7

0x00

0xD8

0x00

Table 191

SFSP6_8

R/W

0x320

Pin configuration register for pin P6_8

0x00

0xD8

0x00

Table 191

SFSP6_9

R/W

0x324

Pin configuration register for pin P6_9

0x00

0x00

0x00

Table 191

SFSP6_10

R/W

0x328

Pin configuration register for pin P6_10 0x00

0x00

0x00

Table 191

Pins P5_n

Pins P6_n

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Chapter 17: LPC43xx/LPC43Sxx System Control Unit (SCU)/ IO

Table 190. Register overview: System Control Unit (SCU) (base address 0x4008 6000)
…continued

Name

Access Address Description
offset

Reset
value

Reset
value
after
EMC
boot

Reset
value
after
UART
boot

Reference

SFSP6_11

R/W

0x00

0x00

0x00

Table 191

SFSP6_12

R/W

0x330

Pin configuration register for pin P6_12 0x00

0x00

0x00

Table 191

-

-

0x334 0x37C

Reserved

-

-

-

-

SFSP7_0

R/W

0x380

Pin configuration register for pin P7_0

0x00

0x00

0x00

Table 191

SFSP7_1

R/W

0x384

Pin configuration register for pin P7_1

0x00

0x00

0x00

Table 191

SFSP7_2

R/W

0x388

Pin configuration register for pin P7_2

0x00

0x00

0x00

Table 191

SFSP7_3

R/W

0x38C

Pin configuration register for pin P7_3

0x00

0x00

0x00

Table 191

SFSP7_4

R/W

0x390

Pin configuration register for pin P7_4

0x00

0x00

0x00

Table 191/
Table 197

SFSP7_5

R/W

0x394

Pin configuration register for pin P7_5

0x00

0x00

0x00

Table 191/
Table 197

SFSP7_6

R/W

0x398

Pin configuration register for pin P7_6

0x00

0x00

0x00

Table 191

SFSP7_7

R/W

0x39C

Pin configuration register for pin P7_7

0x00

0x00

0x00

Table 191/
Table 199

-

-

0x3A0 0x3FC

Reserved

-

-

-

-

SFSP8_0

R/W

0x400

Pin configuration register for pin P8_0

0x00

0x00

0x00

Table 192

SFSP8_1

R/W

0x404

Pin configuration register for pin P8_1

0x00

0x00

0x00

Table 192

SFSP8_2

R/W

0x408

Pin configuration register for pin P8_2

0x00

0x00

0x00

Table 192

SFSP8_3

R/W

0x40C

Pin configuration register for pin P8_3

0x00

0x00

0x00

Table 191

SFSP8_4

R/W

0x410

Pin configuration register for pin P8_4

0x00

0x00

0x00

Table 191

SFSP8_5

R/W

0x414

Pin configuration register for pin P8_5

0x00

0x00

0x00

Table 191

SFSP8_6

R/W

0x418

Pin configuration register for pin P8_6

0x00

0x00

0x00

Table 191

SFSP8_7

R/W

0x41C

Pin configuration register for pin P8_7

0x00

0x00

0x00

Table 191

SFSP8_8

R/W

0x420

Pin configuration register for pin P8_8

0x00

0x00

0x00

Table 191

-

-

0x424 0x47C

Reserved

-

-

-

-

SFSP9_0

R/W

0x480

Pin configuration register for pin P9_0

0x00

0x00

0x00

Table 191

SFSP9_1

R/W

0x484

Pin configuration register for pin P9_1

0x00

0x00

0x00

Table 191

SFSP9_2

R/W

0x488

Pin configuration register for pin P9_2

0x00

0x00

0x00

Table 191

SFSP9_3

R/W

0x49C

Pin configuration register for pin P9_3

0x00

0x00

0x00

Table 191

SFSP9_4

R/W

0x490

Pin configuration register for pin P9_4

0x00

0x00

0x00

Table 191

SFSP9_5

R/W

0x494

Pin configuration register for pin P9_5

0x00

0x00

0x00

Table 191

SFSP9_6

R/W

0x498

Pin configuration register for pin P9_6

0x00

0x00

0x00

Table 191

0x32C

Pin configuration register for pin P6_11

Pins P7_n

Pins P8_n

Pins P9_n

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Chapter 17: LPC43xx/LPC43Sxx System Control Unit (SCU)/ IO

Table 190. Register overview: System Control Unit (SCU) (base address 0x4008 6000)
…continued

Name

Access Address Description
offset

Reset
value

Reset
value
after
EMC
boot

Reset
value
after
UART
boot

Reference

-

-

0x49C 0x4FC

Reserved

-

-

-

-

SFSPA_0

R/W

0x500

Pin configuration register for pin PA_0

0x00

0x00

0x00

Table 191

SFSPA_1

R/W

0x504

Pin configuration register for pin PA_1

0x00

0x00

0x00

Table 192

SFSPA_2

R/W

0x508

Pin configuration register for pin PA_2

0x00

0x00

0x00

Table 192

SFSPA_3

R/W

0x50C

Pin configuration register for pin PA_3

0x00

0x00

0x00

Table 192

SFSPA_4

R/W

0x510

Pin configuration register for pin PA_4

0x00

0xD8

0x00

Table 191

-

-

0x514 0x57C

Reserved

-

-

-

-

SFSPB_0

R/W

0x580

Pin configuration register for pin PB_0

0x00

0x00

0x00

Table 191

SFSPB_1

R/W

0x584

Pin configuration register for pin PB_1

0x00

0x00

0x00

Table 191

SFSPB_2

R/W

0x588

Pin configuration register for pin PB_2

0x00

0x00

0x00

Table 191

SFSPB_3

R/W

0x58C

Pin configuration register for pin PB_3

0x00

0x00

0x00

Table 191

SFSPB_4

R/W

0x590

Pin configuration register for pin PB_4

0x00

0x00

0x00

Table 191

SFSPB_5

R/W

0x594

Pin configuration register for pin PB_5

0x00

0x00

0x00

Table 191

SFSPB_6

R/W

0x598

Pin configuration register for pin PB_6

0x00

0x00

0x00

Table 191/
Table 197

-

-

0x59C 0x5FC

Reserved

-

-

-

-

SFSPC_0

R/W

0x600

Pin configuration register for pin PC_0

0x00

0x00

0x00

Table 191/
Table 199

SFSPC_1

R/W

0x604

Pin configuration register for pin PC_1

0x00

0x00

0x00

Table 191

SFSPC_2

R/W

0x608

Pin configuration register for pin PC_2

0x00

0x00

0x00

Table 191

SFSPC_3

R/W

0x60C

Pin configuration register for pin PC_3

0x00

0x00

0x00

Table 191/
Table 199

SFSPC_4

R/W

0x610

Pin configuration register for pin PC_4

0x00

0x00

0x00

Table 191

SFSPC_5

R/W

0x614

Pin configuration register for pin PC_5

0x00

0x00

0x00

Table 191

SFSPC_6

R/W

0x618

Pin configuration register for pin PC_6

0x00

0x00

0x00

Table 191

SFSPC_7

R/W

0x61C

Pin configuration register for pin PC_7

0x00

0x00

0x00

Table 191

SFSPC_8

R/W

0x620

Pin configuration register for pin PC_8

0x00

0x00

0x00

Table 191

SFSPC_9

R/W

0x624

Pin configuration register for pin PC_9

0x00

0x00

0x00

Table 191

SFSPC_10

R/W

0x628

Pin configuration register for pin PC_10 0x00

0x00

0x00

Table 191

SFSPC_11

R/W

0x62C

Pin configuration register for pin PC_11 0x00

0x00

0x00

Table 191

SFSPC_12

R/W

0x630

Pin configuration register for pin PC_12 0x00

0x00

0x00

Table 191

SFSPC_13

R/W

0x634

Pin configuration register for pin PC_13 0x00

0x00

0x00

Table 191

SFSPC_14

R/W

0x638

Pin configuration register for pin PC_14 0x00

0x00

0x00

Table 191

Pins PA_n

Pins PB_n

Pins PC_n

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Chapter 17: LPC43xx/LPC43Sxx System Control Unit (SCU)/ IO

Table 190. Register overview: System Control Unit (SCU) (base address 0x4008 6000)
…continued

Name

Access Address Description
offset

Reset
value

Reset
value
after
EMC
boot

Reset
value
after
UART
boot

Reference

-

-

0x63C 0x67C

Reserved

-

-

-

-

SFSPD_0

R/W

0x680

Pin configuration register for pin PD_0

0x00

0x00

0x00

Table 191

SFSPD_1

R/W

0x684

Pin configuration register for pin PD_1

0x00

0x00

0x00

Table 191

SFSPD_2

R/W

0x688

Pin configuration register for pin PD_2

0x00

0x00

0x00

Table 191

SFSPD_3

R/W

0x68C

Pin configuration register for pin PD_3

0x00

0x00

0x00

Table 191

SFSPD_4

R/W

0x690

Pin configuration register for pin PD_4

0x00

0x00

0x00

Table 191

SFSPD_5

R/W

0x694

Pin configuration register for pin PD_5

0x00

0x00

0x00

Table 191

SFSPD_6

R/W

0x698

Pin configuration register for pin PD_6

0x00

0x00

0x00

Table 191

SFSPD_7

R/W

0x69C

Pin configuration register for pin PD_7

0x00

0x00

0x00

Table 191

SFSPD_8

R/W

0x6A0

Pin configuration register for pin PD_8

0x00

0x00

0x00

Table 191

SFSPD_9

R/W

0x6A4

Pin configuration register for pin PD_9

0x00

0x00

0x00

Table 191

Pins PD_n

SFSPD_10

R/W

0x6A8

Pin configuration register for pin PD_10 0x00

0xD2

0x00

Table 191

SFSPD_11

R/W

0x6AC

Pin configuration register for pin PD_11 0x00

0x00

0x00

Table 191

SFSPD_12

R/W

0x6B0

Pin configuration register for pin PD_12 0x00

0x00

0x00

Table 191

SFSPD_13

R/W

0x6B4

Pin configuration register for pin PD_13 0x00

0xD2

0x00

Table 191

SFSPD_14

R/W

0x6B8

Pin configuration register for pin PD_14 0x00

0x00

0x00

Table 191

SFSPD_15

R/W

0x6BC

Pin configuration register for pin PD_15 0x00

0xD8

0x00

Table 191

SFSPD_16

R/W

0x6C0

Pin configuration register for pin PD_16 0x00

0xD8

0x00

Table 191

-

-

0x6C4 0x6FC

Reserved

-

SFSPE_0

R/W

0x700

Pin configuration register for pin PE_0

0x00

0xD8

0x00

Table 191

SFSPE_1

R/W

0x704

Pin configuration register for pin PE_1

0x00

0xD8

0x00

Table 191

SFSPE_2

R/W

0x708

Pin configuration register for pin PE_2

0x00

0xD8

0x00

Table 191

SFSPE_3

R/W

0x70C

Pin configuration register for pin PE_3

0x00

0xD8

0x00

Table 191

SFSPE_4

R/W

0x710

Pin configuration register for pin PE_4

0x00

0xD8

0x00

Table 191

SFSPE_5

R/W

0x714

Pin configuration register for pin PE_5

0x00

0x00

0x00

Table 191

SFSPE_6

R/W

0x718

Pin configuration register for pin PE_6

0x00

0x00

0x00

Table 191

SFSPE_7

R/W

0x71C

Pin configuration register for pin PE_7

0x00

0x00

0x00

Table 191

SFSPE_8

R/W

0x720

Pin configuration register for pin PE_8

0x00

0x00

0x00

Table 191

SFSPE_9

R/W

0x724

Pin configuration register for pin PE_9

0x00

0x00

0x00

Table 191

SFSPE_10

R/W

0x728

Pin configuration register for pin PE_10 0x00

0x00

0x00

Table 191

SFSPE_11

R/W

0x72C

Pin configuration register for pin PE_11 0x00

0x00

0x00

Table 191

SFSPE_12

R/W

0x730

Pin configuration register for pin PE_12 0x00

0x00

0x00

Table 191

SFSPE_13

R/W

0x734

Pin configuration register for pin PE_13 0x00

0x00

0x00

Table 191

SFSPE_14

R/W

0x738

Pin configuration register for pin PE_14 0x00

0x00

0x00

Table 191

Pins PE_n

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Chapter 17: LPC43xx/LPC43Sxx System Control Unit (SCU)/ IO

Table 190. Register overview: System Control Unit (SCU) (base address 0x4008 6000)
…continued

Name

Access Address Description
offset

Reset
value

Reset
value
after
EMC
boot

Reset
value
after
UART
boot

Reference

SFSPE_15

R/W

0x73C

Pin configuration register for pin PE_15 0x00

0x00

0x00

Table 191

-

-

0x740 0x77C

Reserved

-

SFSPF_0

R/W

0x780

Pin configuration register for pin PF_0

0x00

0x00

0x00

Table 191

SFSPF_1

R/W

0x784

SFSPF_2

R/W

0x788

Pin configuration register for pin PF_1

0x00

0x00

0x00

Table 191

Pin configuration register for pin PF_2

0x00

0x00

0x00

Table 191

SFSPF_3

R/W

0x78C

Pin configuration register for pin PF_3

0x00

0x00

0x00

Table 191

SFSPF_4

R/W

0x790

Pin configuration register for pin PF_4

0x00

0x00

0x00

Table 191

SFSPF_5

R/W

0x794

Pin configuration register for pin PF_5

0x00

0x00

0x00

Table 191/
Table 199

SFSPF_6

R/W

0x798

Pin configuration register for pin PF_6

0x00

0x00

0x00

Table 191/
Table 199

SFSPF_7

R/W

0x79C

Pin configuration register for pin PF_7

0x00

0x00

0x00

Table 191/
Table 199

SFSPF_8

R/W

0x7A0

Pin configuration register for pin PF_8

0x00

0x00

0x00

Table 191/
Table 197

SFSPF_9

R/W

0x7A4

Pin configuration register for pin PF_9

0x00

0x00

0x00

Table 191/
Table 199

SFSPF_10

R/W

0x7A8

Pin configuration register for pin PF_10 0x00

0x00

0x00

Table 191/
Table 197

SFSPF_11

R/W

0x7AC

Pin configuration register for pin PF_11

0x00

0x00

0x00

Table 191/
Table 199

-

-

0x7B0 0xBFC

Reserved

-

-

-

-

SFSCLK0

R/W

0xC00

Pin configuration register for pin CLK0

0x00

0x00

0x00

Table 193

SFSCLK1

R/W

0xC04

Pin configuration register for pin CLK1

0x00

0x00

0x00

Table 193

SFSCLK2

R/W

0xC08

Pin configuration register for pin CLK2

0x00

0x00

0x00

Table 193

SFSCLK3

R/W

0xC0C

Pin configuration register for pin CLK3

0x00

0x00

0x00

Table 193

-

-

0xC10 0xC7C

Reserved

-

-

-

-

Pins PF_n

CLKn pins

USB1 USB1_DP/USB1_DM pins and I2C-bus open-drain pins
SFSUSB

R/W

0xC80

Pin configuration register for pins
USB1_DM and USB1_DP

0x02

0x00

0x00

Table 194

SFSI2C0

R/W

0xC84

Pin configuration register for I2C0-bus
pins

0x00

0x00

0x00

Table 195

ADC pin select registers
ENAIO0

R/W

0xC88

ADC0 function select register

0x00

0x00

0x00

Table 197

ENAIO1

R/W

0xC8C

ADC1 function select register

0x00

0x00

0x00

Table 199

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Chapter 17: LPC43xx/LPC43Sxx System Control Unit (SCU)/ IO

Table 190. Register overview: System Control Unit (SCU) (base address 0x4008 6000)
…continued

Name

Access Address Description
offset

Reset
value

Reset
value
after
EMC
boot

Reset
value
after
UART
boot

Reference

ENAIO2

R/W

0xC90

Analog function select register

0x00

0x00

0x00

Table 201

R/W

0xD00

EMC clock delay register

0x00

0x00

0x00

Table 202

0xD80

SD/MMC sample and drive delay
register

0x00

0x00

0x00

Table 203

EMC delay register
EMCDELAYCLK

SD/MMC delay register
SDDELAY

R/W

Pin interrupt select registers
PINTSEL0

R/W

0xE00

Pin interrupt select register for pin
interrupts 0 to 3.

0x00

0x00

0x00

Table 204

PINTSEL1

R/W

0xE04

Pin interrupt select register for pin
interrupts 4 to 7.

0x00

0x00

0x00

Table 205

17.4.1 Pin configuration registers for normal-drive pins
Each digital pin and each clock pin on the LPC43xx/LPC43Sxx have an associated pin
configuration register which determines the pin’s function and electrical characteristics.
The pin configuration registers for normal-drive pins control the following pins:

•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•

UM10503

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P0_0 and P0_1
P1_0 to P1_16 and P1_18 to P1_20
P2_0 to P2_2 and P2_6 to P2_13
P3_0 to P3_2 and P3_4 to P3_8
P4_0 to P4_10
P5_0 to P5_7
P6_0 to P6_12
P7_0 to P7_7
P8_3 to P8_8
P9_0 to P9_6
PA_0 and PA_4
PB_0 to PB_6
PC_0 to PC_14
PD_0 to PD_16
PE_0 to PE_15
PF_0 to PF_11

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Chapter 17: LPC43xx/LPC43Sxx System Control Unit (SCU)/ IO

Table 191. Pin configuration registers for normal-drive pins (SFS, address 0x4008 6000
(SPSP0_0) to 0x4008 67AC (SFSPF_11)) bit description
Bit

Symbol

2:0

MODE

3

4

5

6

7

31:8

Value

Description

Reset Access
value

Select pin function.

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

Input glitch filter. Disable the input glitch filter 0
for clocking signals higher than 30 MHz.

R/W

0x0

Function 0 (default)

0x1

Function 1

0x2

Function 2

0x3

Function 3

0x4

Function 4

0x5

Function 5

0x6

Function 6

0x7

Function 7

EPD

Enable pull-down resistor at pad.
0

Disable pull-down.

1

Enable pull-down.Enable both pull-down
resistor and pull-up resistor for repeater
mode.

EPUN

Disable pull-up resistor at pad. By default,
the pull-up resistor is enabled at reset.
0

Enable pull-up. Enable both pull-down
resistor and pull-up resistor for repeater
mode.

1

Disable pull-up.

EHS

Select Slew rate.
0

Slow (low noise with medium speed)

1

Fast (medium noise with fast speed)

EZI

Input buffer enable. The input buffer is
disabled by default at reset and must be
enabled for receiving.
0

Disable input buffer

1

Enable input buffer

ZIF

-

0

Enable input glitch filter

1

Disable input glitch filter
Reserved

-

-

17.4.2 Pin configuration registers for high-drive pins
Each digital pin and each clock pin on the LPC43xx/LPC43Sxx have an associated pin
configuration register which determines the pin’s function and electrical characteristics.
The assigned functions for each pin are listed in Table 189.
The pin configuration registers for high-drive pins control the following pins:

• P1_17
• P2_3 to P2_5
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Chapter 17: LPC43xx/LPC43Sxx System Control Unit (SCU)/ IO

• P8_0 to P8_2
• PA_1 to PA_3
Table 192. Pin configuration registers for high-drive pins (SFS, address 0x4008 60C4
(SFSP1_17) to 0x4008 650C (SFSPA_3) bit description
Bit

Symbol

2:0

MODE

3

4

Value

Select pin function.

0

R/W

0

R/W

0

R/W

-

-

Function 0 (default)

0x1

Function 1

0x2

Function 2

0x3

Function 3

0x4

Function 4

0x5

Function 5

0x6

Function 6

0x7

Function 7

EPD

Enable pull-down resistor at pad.
0

Disable pull-down.

1

Enable pull-down. Enable both pull-down
resistor and pull-up resistor for repeater
mode.

EPUN

Disable pull-up resistor at pad. By default,
the pull-up resistor is enabled at reset.
0

Enable pull-up. Enable both pull-down
resistor and pull-up resistor for repeater
mode.

1

Disable pull-up

5

-

Reserved

6

EZI

Input buffer enable. The input buffer is
0
disabled by default at reset but must be
enabled to transfer data from the I/O buffer to
the pad.
1

7

ZIF

1
9:8

31:10

EHD

-

R/W

Disable input buffer
Enable input buffer
Input glitch filter. Disable the input glitch filter 0
for clocking signals higher than 30 MHz.

0

User manual

Reset Access
value

0x0

0

UM10503

Description

R/W

Enable input glitch filter
Disable input glitch filter
Select drive strength.

0x0

Normal-drive: 4 mA drive strength

0x1

Medium-drive: 8 mA drive strength

0x2

High-drive: 14 mA drive strength

0x3

Ultra high-drive: 20 mA drive strength
Reserved

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0

R/W

-

-

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Chapter 17: LPC43xx/LPC43Sxx System Control Unit (SCU)/ IO

17.4.3 Pin configuration registers for high-speed pins
Each digital pin and each clock pin on the LPC43xx/LPC43Sxx have an associated pin
configuration register which determines the pin’s function and electrical characteristics.
The assigned functions for each pin are listed in Table 189.
This register controls the following pins: P3_3 and pins CLK0 to CLK3.
Table 193. Pin configuration registers for high-speed pins (SFS, address 0x4008 618C
(SPSP3_3); 0x4008 6C00 (SFSCLK0) to 0x4008 6C0C (SFSCLK3)) bit description
Bit

Symbol

2:0

MODE

3

4

5

6

Value

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

Input glitch filter. Disable the input glitch filter 0
for clocking signals higher than 30 MHz.

R/W

0x1

Function 1

0x2

Function 2

0x3

Function 3

0x4

Function 4

0x5

Function 5

0x6

Function 6

0x7

Function 7

EPD

Enable pull-down resistor at pad.
0

Disable pull-down.

1

Enable pull-down. Enable both pull-down
resistor and pull-up resistor for repeater
mode.

EPUN

Disable pull-up resistor at pad. By default,
the pull-up resistor is enabled at reset.
0

Enable pull-up. Enable both pull-down
resistor and pull-up resistor for repeater
mode.

1

Disable pull-up.

EHS

Slew rate
0

Fast (low noise with fast speed)

1

High-speed (medium noise with high speed)

EZI

Input buffer enable. The input buffer is
disabled by default at reset and must be
enabled for receiving.

ZIF

-

Select pin function.
Function 0 (default)

1

31:8

Reset Access
value

0x0

0
7

Description

Disable input buffer
Enable input buffer

0

Enable input filter

1

Disable input filter
Reserved

-

-

17.4.4 Pin configuration register for USB1 pins USB1_DP/USB1_DM
Remark: The USB_ESEA bit must be set to one to use USB1.
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Chapter 17: LPC43xx/LPC43Sxx System Control Unit (SCU)/ IO

Table 194. Pin configuration for pins USB1_DP/USB1_DM register (SFSUSB, address 0x4008
6C80) bit description
Bit

Symbol

0

USB_AIM

Value Description
Differential data input AIP/AIM.
0

2

0

R/W

1

R/W

0

R/W

Going LOW with full speed edge rate

1
1

Reset Access
value

Going HIGH with full speed edge rate

USB_ESEA

Control signal for differential input or single input.
0

Reserved. Do not use.

1

Single input. Enables USB1. Use with the on-chip
full-speed PHY.

USB_EPD

Enable pull-down connect.
0

Pull-down disconnected

1

Pull-down connected

3

-

Reserved

-

-

4

USB_EPWR

Power mode.

0

R/W

Enable the vbus_valid signal. This signal is
0
monitored by the USB1 block. Use this bit for
software de-bouncing of the VBUS sense signal or
to indicate the VBUS state to the USB1 controller
when the VBUS signal is present but the
USB1_VBUS function is not connected in the
SFSP2_5 register.

R/W

5

0

Power saving mode (Suspend mode)

1

Normal mode

USB_VBUS

Remark: The setting of this bit has no effect if the
USB1_VBUS function of pin P2_5 is enabled
through the SFSP2_5 register.

31:6

0

VBUS signal LOW or inactive

1

VBUS signal HIGH or active

-

Reserved

-

-

17.4.5 Pin configuration register for open-drain I2C-bus pins
Table 195. Pin configuration for open-drain I2C-bus pins register (SFSI2C0, address 0x4008
6C84) bit description

UM10503

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Bit

Symbol

Value

0

SCL_EFP

Description

Reset Access
value

Select input glitch filter time constant for the
SCL pin.

0

R/W

0

50 ns glitch filter

1

3 ns glitch filter

1

-

Reserved. Always write a 0 to this bit.

0

R/W

2

SCL_EHD

Select I2C mode for the SCL pin.

0

R/W

0

Standard/Fast mode transmit

1

Fast-mode Plus transmit

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Chapter 17: LPC43xx/LPC43Sxx System Control Unit (SCU)/ IO

Table 195. Pin configuration for open-drain I2C-bus pins register (SFSI2C0, address 0x4008
6C84) bit description …continued
Bit

Symbol

Value

3

SCL_EZI

0
1

Description

Reset Access
value

Enable the input receiver for the SCL pin.
Always write a 1 to this bit when using the
I2C0.

0

R/W

Disabled
Enabled

6:4

-

Reserved

-

-

7

SCL_ZIF

Enable or disable input glitch filter for the
SCL pin. The filter time constant is
determined by bit SCL_EFP.

0

R/W

0

R/W

Reserved. Always write a 0 to this bit.

0

R/W

Select I2C mode for the SDA pin.

0

R/W

0

R/W

8

Enable input filter

1

Disable input filter

SDA_EFP

9

-

10

SDA_EHD

11

0

Select input glitch filter time constant for the
SDA pin.
0

50 ns glitch filter

1

3 ns glitch filter

0

Standard/Fast mode transmit

1

Fast-mode Plus transmit

SDA_EZI

Enable the input receiver for the SDA pin.
Always write a 1 to this bit when using the
I2C0.
0

Disabled

1

Enabled

14:12

-

Reserved

-

-

15

SDA_ZIF

Enable or disable input glitch filter for the
SDA pin. The filter time constant is
determined by bit SDA_EFP.

0

R/W

-

-

31:16

-

0

Enable input filter

1

Disable input filter
Reserved

17.4.6 ADC0 function select register
Remark: See Section 17.1 for parts for which the ADC inputs are shared between the
ADC0 and ADC1.
For pins with digital and analog functions, this register selects the input channel of the
ADC0 over any of the possible digital functions. This option is not available for channel
ADC0_7.
In addition, each analog function is pinned out on a dedicated analog pin which is not
affected by this register.
The following pins are controlled by the ENAIO0 register:
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Chapter 17: LPC43xx/LPC43Sxx System Control Unit (SCU)/ IO

Table 196. Pins controlled by the ENAIO0 register
Pin

ADC function

ENAIO0 register bit

P4_3

ADC0_0

0

P4_1

ADC0_1

1

PF_8

ADC0_2

2

P7_5

ADC0_3

3

P7_4

ADC0_4

4

PF_10

ADC0_5

5

PB_6

ADC0_6

6

By default, all pins are connected to their digital function 0 and only the digital pad is
available.
To select the analog function, the pad must be set as follows using the corresponding
SFSP register:
1. Tri-state the output driver by selecting an input at the pinmux e.g. GPIO function in
input mode.
2. Disable the receiver by setting the EZI bit to zero (see Table 191 or Table 192). This is
the default setting.
3. Disable the pull-up resistor by setting the EPUN bit to one, and disable the pull-down
resistor by setting the EPD bit to zero.
4. Set the bit corresponding to the analog function to 1 in the ENAIO0 register.
Table 197. ADC0 function select register (ENAIO0, address 0x4008 6C88) bit description
Bit

Symbol

0

ADC0_0

1

2

3

4

5

UM10503

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Value Description
Select ADC0_0
0

Digital function selected on pin P4_3.

1

Analog function ADC0_0 selected on pin P4_3

ADC0_1

Select ADC0_1
0

Digital function selected on pin P4_1.

1

Analog function ADC0_1 selected on pin P4_1.

ADC0_2

Select ADC0_2
0

Digital function selected on pin PF_8.

1

Analog function ADC0_2 selected on pin PF_8.

ADC0_3

Select ADC0_3
0

Digital function selected on pin P7_5.

1

Analog function ADC0_3 selected on pin P7_5.

ADC0_4

Select ADC0_4
0

Digital function selected on pin P7_4.

1

Analog function ADC0_4 selected on pin P7_4.

0

Digital function selected on pin PF_10.

1

Analog function ADC0_5 selected on pin PF_10.

ADC0_5

Select ADC0_5

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Reset Access
value
0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

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Chapter 17: LPC43xx/LPC43Sxx System Control Unit (SCU)/ IO

Table 197. ADC0 function select register (ENAIO0, address 0x4008 6C88) bit description
Bit

Symbol

6

ADC0_6

31:7

Value Description

Reset Access
value

Select ADC0_6
0

Digital function selected on pin PB_6.

1

Analog function ADC0_6 selected on pin PB_6.
Reserved

0

R/W

-

-

17.4.7 ADC1 function select register
Remark: See Section 17.1 for parts for which the ADC inputs are shared between the
ADC0 and ADC1.
For pins with digital and analog functions, this register selects the ADC1 function over any
of the possible digital functions.
In addition, each analog function is pinned out on a dedicated analog pin which is not
affected by this register.
The following pins are controlled by the ENAIO1 register:
Table 198. Pins controlled by the ENAIO1 register
Pin

ADC function

ENAIO1 register bit

PC_3

ADC1_0

0

PC_0

ADC1_1

1

PF_9

ADC1_2

2

PF_6

ADC1_3

3

PF_5

ADC1_4

4

PF_11

ADC1_5

5

P7_7

ADC1_6

6

PF_7

ADC1_7

7

By default, all pins are connected to their digital function 0 and only the digital pad is
available.
To select the analog function, the pad must be set as follows using the corresponding
SFSP register:
1. Tri-state the output driver by selecting an input at the pinmux e.g. GPIO function in
input mode.
2. Disable the receiver by setting the EZI bit to zero (see Table 191 or Table 192). This is
the default setting.
3. Disable the pull-up resistor by setting the EPUN bit to one, and disable the pull-down
resistor by setting the EPD bit to zero.
4. Set the bit corresponding to the analog function to 1 in the ENAIO1 register.

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Chapter 17: LPC43xx/LPC43Sxx System Control Unit (SCU)/ IO

Table 199. ADC1 function select register (ENAIO1, address 0x4008 6C8C) bit description
Bit

Symbol

0

ADC1_0

1

2

3

4

5

6

7

31:8

Value Description

Reset Access
value

Select ADC1_0
0

Digital function selected on pin PC_3.

1

Analog function ADC1_0 selected on pin PC_3.

0

Digital function selected on pin PC_0.

1

Analog function ADC1_1 selected on pin PC_0.

ADC1_1

Select ADC1_1

ADC1_2

Select ADC1_2
0

Digital function selected on pin PF_9.

1

Analog function ADC1_2 selected on pin PF_9.

ADC1_3

Select ADC1_3
0

Digital function selected on pin PF_6.

1

Analog function ADC1_3 selected on pin PF_6.

ADC1_4

Select ADC1_4
0

Digital function selected on pin PF_5.

1

Analog function ADC1_4 selected on pin PF_5.

0

Digital function selected on pin PF_11.

1

Analog function ADC1_5 selected on pin PF_11.

ADC1_5

Select ADC1_5

ADC1_6

Select ADC1_6
0

Digital function selected on pin P7_7.

1

Analog function ADC1_6 selected on pin P7_7.

ADC1_7

Select ADC1_7.
0

Digital function selected on pin PF_7.

1

Analog function ADC1_7 selected on pin PF_7.
Reserved

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

-

-

17.4.8 Analog function select register
For pins which have digital and analog functions, this register selects the analog DAC and
band gap function over any of the possible digital functions.
In addition, the DAC function is pinned out on a dedicated analog pin which is not affected
by this register.
The following pins are controlled by the ENAIO2 register:
Table 200. Pins controlled by the ENAIO2 register
Pin

ADC function

ENAIO2 register bit

P4_4

DAC

0

PF_7

BG (band gap output)

4

By default, all pins are connected to their digital function 0 and only the digital pad is
available.

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To select the analog function, the pad must be set as follows using the corresponding
SFSP register:
1. Tri-state the output driver by selecting an input at the pinmux e.g. GPIO function in
input mode.
2. Disable the receiver by setting the EZI bit to zero (see Table 191 or Table 192). This is
the default setting.
3. Disable the pull-up resistor by setting the EPUN bit to one, and disable the pull-down
resistor by setting the EPD bit to zero.
4. Set the bit corresponding to the analog function to 1in the ENAIO2 register.
Table 201. Analog function select register (ENAIO2, address 0x4008 6C90) bit description
Bit

Symbol

0

DAC

Value Description
Select DAC
0

Digital function selected on pin P4_4.

1

Analog function DAC selected on pin P4_4.

3:1
4

31:5

Reserved

Reset Access
value
0

R/W

-

-

Select band gap output. To measure the band gap, 0
disable the pull-up on pin PF_7 and connect PF_7
to the digital pad. Do not use the digital pad nor the
ADC1_7 on the board when measuring the band
gap (see Section 17.4.8.1).

BG

0

Digital function selected on pin PF_7.

1

Band gap output selected for pin PF_7.
Reserved

-

R/W

-

17.4.8.1 Measuring the band gap
To measure the band gap, set up the pin configuration and ADC function select registers
for pin PF_7 as follows:
1. Disable the pull-up and the input buffer: Set register SFSPF_7 at 0x4008 679C to
0x10.
2. Connect the ADC1_7 input to the digital pad: Set register ENAIO1at 0x4008 6C8C to
0x80.
3. Connect the band gap to the digital pad: Set register ENAIO2 at 0x4008 6C90 to
0x10.
4. Do not connect pin PF_7 on the board.

17.4.9 EMC clock delay register
This register provides a programmable delay for the EMC clock outputs. The delay for all
EMC_CLKn clock outputs is the same and increases in approximately 0.5 ns steps from 0
(CLK_DELAY = 0 to 3.5 ns (CLK_DELAY = 0x7777). The exact values of the delays vary
over temperature and processing.

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Chapter 17: LPC43xx/LPC43Sxx System Control Unit (SCU)/ IO

Table 202. EMC clock delay register (EMCDELAYCLK, address 0x4008 6D00) bit description
Bit

Symbol

Description

Reset Access
value

15:0

CLK_DELAY

EMC_CLKn SDRAM clock output delay.

0

R/W

-

-

0x0 = no delay
0x1111  0.5 ns delay
0x2222  1.0 ns delay
0x3333  1.5 ns delay
0x4444  2.0 ns delay
0x5555  2.5 ns delay
0x6666  3.0 ns delay
0x7777  3.5 ns delay
31:16

-

Reserved. Do not write ones to reserved register bits.

17.4.10 SD/MMC delay register
This register provides a programmable delay for the SD/MMC sample and drive inputs
and outputs. See the LPC43xx/LPC43Sxx data sheets for recommended settings.
Typical setting for SD cards are SAMPLE_DELAY = 0x8 and DRV_DELAY = 0xF.
Remark: The values DRV_DELAY = 0 and DRV_DELAY = 1 are not allowed.
Table 203. SD/MMC delay register (SDDELAY, address 0x4008 6D80) bit description
Bit

Symbol

Description

Reset
value

Access

3:0

SAMPLE_DELAY

SD/MMC sample delay. The delay value is
SAMPLE_DELAY x 0.5 ns.

0

R/W

7:4

-

Reserved. Do not write ones to reserved register
bits.

-

-

11:8

DRV_DELAY

SD/MMC drive delay. The delay value is
DRV_DELAY x 0.5 ns. The values
DRV_DELAY = 0 and DRV_DELAY = 1 are not
allowed.

0

R/W

Reserved. Do not write ones to reserved register
bits.

-

-

31: 12 -

17.4.11 Pin interrupt select register 0
This register selects one GPIO pin from all GPIO pins on all ports as the source for pin
interrupts 0 to 3.
Example: For pin interrupt 1, INTPIN1 = 0xA and PORTSEL1 = 1 select GPIO pin
GPIO1[10] located on pin P2_9 to generate an interrupt. Each pin interrupt must be
enabled in the NVIC.
To enable each pin interrupt and configure its edge or level sensitivity, use the GPIO pin
interrupt registers (see Section 19.4.1).

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Chapter 17: LPC43xx/LPC43Sxx System Control Unit (SCU)/ IO

Table 204. Pin interrupt select register 0 (PINTSEL0, address 0x4008 6E00) bit description
Bit

Symbol

4:0

INTPIN0

Pint interrupt 0: Select the pin number within the GPIO port 0
selected by the PORTSEL0 bit in this register.

7:5

PORTSEL0

Pin interrupt 0: Select the port for the pin number to be
selected in the INTPIN0 bits of this register.

User manual

Description

0x0

GPIO Port 0

0x1

GPIO Port 1

0x2

GPIO Port 2

0x3

GPIO Port 3

0x4

GPIO Port 4

0x5

GPIO Port 5

0x6

GPIO Port 6

0x7

GPIO Port 7

Reset
value

0

12:8

INTPIN1

Pint interrupt 1: Select the pin number within the GPIO port 0
selected by the PORTSEL1 bit in this register.

15:13

PORTSEL1

Pin interrupt 1: Select the port for the pin number to be
selected in the INTPIN1 bits of this register.
0x0

GPIO Port 0

0x1

GPIO Port 1

0x2

GPIO Port 2

0x3

GPIO Port 3

0x4

GPIO Port 4

0x5

GPIO Port 5

0x6

GPIO Port 6

0x7

GPIO Port 7

0

20:16

INTPIN2

Pint interrupt 2: Select the pin number within the GPIO port 0
selected by the PORTSEL2 bit in this register.

23:21

PORTSEL2

Pin interrupt 2: Select the port for the pin number to be
selected in the INTPIN2 bits of this register.

28:24

UM10503

Value

INTPIN3

0x0

GPIO Port 0

0x1

GPIO Port 1

0x2

GPIO Port 2

0x3

GPIO Port 3

0x4

GPIO Port 4

0x5

GPIO Port 5

0x6

GPIO Port 6

0x7

GPIO Port 7

0

Pint interrupt 3: Select the pin number within the GPIO port 0
selected by the PORTSEL3 bit in this register.

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Chapter 17: LPC43xx/LPC43Sxx System Control Unit (SCU)/ IO

Table 204. Pin interrupt select register 0 (PINTSEL0, address 0x4008 6E00) bit description
Bit

Symbol

Value

31:29

PORTSEL3

Description

Reset
value

Pin interrupt 3: Select the port for the pin number to be
selected in the INTPIN3 bits of this register.

0

0x0

GPIO Port 0

0x1

GPIO Port 1

0x2

GPIO Port 2

0x3

GPIO Port 3

0x4

GPIO Port 4

0x5

GPIO Port 5

0x6

GPIO Port 6

0x7

GPIO Port 7

17.4.12 Pin interrupt select register 1
This register selects one GPIO pin from all GPIO pins on all ports as the source for pin
interrupts 4 to 7.
Example: For pin interrupt 4, INTPIN4 = 0xA and PORTSEL4 = 1 select GPIO pin
GPIO1[10] located on pin P2_9 to generate an interrupt. Each pin interrupt must be
enabled in the NVIC using interrupt slots 32 to 39.
To enable each pin interrupt and configure its edge or level sensitivity, use the GPIO pin
interrupt registers (see Section 19.4.1).
Table 205. Pin interrupt select register 1 (PINTSEL1, address 0x4008 6E04) bit description
Bit

Symbol

4:0

INTPIN4

Pint interrupt 4: Select the pin number within the GPIO port 0
selected by the PORTSEL4 bit in this register.

7:5

PORTSEL4

Pin interrupt 4: Select the port for the pin number to be
selected in the INTPIN4 bits of this register.

12:8

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Value

INTPIN5

Description

0x0

GPIO Port 0

0x1

GPIO Port 1

0x2

GPIO Port 2

0x3

GPIO Port 3

0x4

GPIO Port 4

0x5

GPIO Port 5

0x6

GPIO Port 6

0x7

GPIO Port 7

Reset
value

0

Pint interrupt 5: Select the pin number within the GPIO port 0
selected by the PORTSEL5 bit in this register.

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Table 205. Pin interrupt select register 1 (PINTSEL1, address 0x4008 6E04) bit description

UM10503

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Bit

Symbol

Value

15:13

PORTSEL5

Description

Reset
value

Pin interrupt 5: Select the port for the pin number to be
selected in the INTPIN5 bits of this register.

0

0x0

GPIO Port 0

0x1

GPIO Port 1

0x2

GPIO Port 2

0x3

GPIO Port 3

0x4

GPIO Port 4

0x5

GPIO Port 5

0x6

GPIO Port 6

0x7

GPIO Port 7

20:16

INTPIN6

Pint interrupt 6: Select the pin number within the GPIO port 0
selected by the PORTSEL6 bit in this register.

23:21

PORTSEL6

Pin interrupt 6: Select the port for the pin number to be
selected in the INTPIN6 bits of this register.
0x0

GPIO Port 0

0x1

GPIO Port 1

0x2

GPIO Port 2

0x3

GPIO Port 3

0x4

GPIO Port 4

0x5

GPIO Port 5

0x6

GPIO Port 6

0x7

GPIO Port 7

0

28:24

INTPIN7

Pint interrupt 7: Select the pin number within the GPIO port 0
selected by the PORTSEL7 bit in this register.

31:29

PORTSEL7

Pin interrupt 7: Select the port for the pin number to be
selected in the INTPIN7 bits of this register.
0x0

GPIO Port 0

0x1

GPIO Port 1

0x2

GPIO Port 2

0x3

GPIO Port 3

0x4

GPIO Port 4

0x5

GPIO Port 5

0x6

GPIO Port 6

0x7

GPIO Port 7

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Chapter 18: LPC43xx/LPC43Sxx Global Input Multiplexer
Array (GIMA)
Rev. 2.4 — 22 August 2018

User manual

18.1 How to read this chapter
Remark: The ADCHS block is only available on the LPC4370.

18.2 Basic configuration
The GIMA is configured as follows:

• See Table 206 for clocking and power control.
• The GIMA is reset by the BUS_RST (reset #8 ). Do not reset the GIMA during normal
operation

• The GIMA outputs are connected to the timer, SCT, ADC, and event router
peripherals (see Figure 44).

• To configure the GIMA inputs for the timers and SCT, set the CTOUTCTRL bit in
CREG6 (Table 104). This bit controls whether the SCT outputs are ORed with the
timer match outputs or whether the SCT outputs only are used.
Table 206. GIMA clocking and power control

Clock to GIMA register interface

Base clock

Branch clock

Maximum
frequency

BASE_M4_CLK

CLK_M4_BUS

204 MHz

18.3 General description
The Global Input Multiplexer Array (GIMA) connects events to various event triggered
peripherals such as the ADCs, the SCT, or the timers.
Each output of the GIMA is connected to a peripheral function (for example, a timer
capture input or an ADC conversion trigger input) and configured through one register,
which selects the event triggers and configures the clock synchronization.
For example, an ADC conversion can be triggered on either an SCT output or a timer
match output. To select the trigger event, use GIMA output 28 which is connected to the
ADC0 and ADC1 start0 conversion inputs. The corresponding GIMA output register
ADCSTART0_IN selects SCT output 15 or the match output 0 of timer 0 as conversion
triggers (see Table 207).

18.3.1 GIMA event input selection
Events that can trigger a peripheral function (e.g. an ADC conversion or a timer capture)
can be selected from the following sources:

• Timer capture pins
• SCT input pins
• Timer0/1/2/3 match outputs
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Chapter 18: LPC43xx/LPC43Sxx Global Input Multiplexer Array (GIMA)

•
•
•
•

SCT outputs
I2S0/1 MWS signal
USART0/2/3 RX/TX active signal
USB0/1 SOF signal

The following peripheral functions are connected to GIMA outputs:

•
•
•
•

Timer0/1/2/3 capture inputs
SCT inputs
ADC0/1 start of conversion
Event router events

Figure 44 shows the peripherals which are connected through the GIMA. For details, see
Table 207.

SYSCON/ external pins
CTIN_[7:0]
T0/1/2/3_CAP[3:0]
USART0/2/3
RX
TX

I2S0/1
I2S0/1_RX_MWS
I2S0/1_TX_MWS
SGPIO
SGPIO3/12
SGPIO3/12_DIV
USB0/1
SOF0/1

24
16

TIMER0/1/2/3
capture channels 3:0

8

SCT
inputs 7:0

3

Event router
inputs 16, 14, 13

2

ADCHS
adc start0/1 triggers

6

4

GIMA

4

2

timer match
output channels OR
SCT outputs

Fig 44. Connections between GIMA and peripherals

Table 207 shows the GIMA output number, the peripheral function the GIMA output is
connected to, and the events that can be selected for this GIMA output. For signals that
originate from an external pin, select a pin from the pinout (more than one pins may be
possible) and program the corresponding pin function in the pin configuration register.
Inputs from external pins include any of the timer capture pins (T0/1/2/3_CAPx and SCT
input pins CTIN_x).
Each GIMA output uses one register (see Table 209) to control the synchronization stage
and to select an event from a subset of all available event trigger signals as shown in
Table 207.

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Chapter 18: LPC43xx/LPC43Sxx Global Input Multiplexer Array (GIMA)

Table 207. GIMA outputs
GIMA
output

GIMA output
connected to

GIMA inputs

0

T0 capture channel 0

pin CTIN_0

SGPIO3

pin T0_CAP0

-

Table 210

1

T0 capture channel 1

pin CTIN_1

USART2 TX
active

pin T0_CAP1

-

Table 211

2

T0 capture channel 2

pin CTIN_2

SGPIO3_DIV

pin T0_CAP2

-

Table 212

3

T0 capture channel 3

SCT output 15 or T3
match channel 3

pin T0_cap3

T3 match
channel 3

-

Table 213

4

T1 capture channel 0

pin CTIN_0

SGPIO12

pin T1_CAP0

-

Table 214

5

T1 capture channel 1

pin CTIN_3

USART0 TX
active

pin T1_CAP1

-

Table 215

6

T1 capture channel 2

pin CTIN_4

USART0 RX
active

pin T1_CAP2

-

Table 216

7

T1 capture channel 3

SCT output 3 or T0
match channel 3

pin T1_CAP3

T0 match
channel 3

-

Table 217

8

T2 capture channel 0

pin CTIN_0

SGPIO12_DIV

pin T2_CAP0

-

Table 218

9

T2 capture channel 1

pin CTIN_1

USART2 TX
active

I2S1_RX_MWS pin T2_CAP1

Table 219

10

T2 capture channel 2

pin CTIN_5

USART2 RX
active

I2S1_TX_MWS pin T2_CAP2

Table 220

11

T2 capture channel 3

SCT output 7 or T1
match channel 3

pin T2_CAP3

-

Table 221

12

T3 capture channel 0

pin CTIN_0

I2S0_RX_MWS pin T3_CAP0

-

Table 222

13

T3 capture channel 1

pin CTIN_6

USART3 TX
active

I2S0_TX_MWS pin T3_CAP1

Table 223

14

T3 capture channel 2

pin CTIN_7

USART3 RX
active

SOF0

pin T3_CAP2

Table 224

15

T3 capture channel 3

SCT output 11 or T2
match channel 3

SOF1

pin T3_CAP3

-

Table 225

16

SCT input 0

pin CTIN_0

SGPIO3

SGPIO3_DIV

-

Table 226

17

SCT input 1

pin CTIN_1

USART2 TX
active

SGPIO12

-

Table 227

18

SCT input 2

pin CTIN_2

SGPIO12

SGPIO12_DIV

-

Table 228

19

SCT input 3

pin CTIN_3

USART0 TX
active

I2S1_RX_MWS I2S1_TX_MWS Table 229

20

SCT input 4

pin CTIN_4

USART0 RX
active

I2S1_RX_MWS I2S1_TX_MWS Table 230

21

SCT input 5

pin CTIN_5

USART2 TX
active

SGPIO12_DIV

22

SCT input 6

pin CTIN_6

USART3 TX
active

I2S0_RX_MSW I2S0_TX_MWS Table 232

23

SCT input 7

pin CTIN_7

USART3 RX
active

SOF0

24

ADCHS trigger

see Table 234

25

Event router input 13

SCT output 2 or T0
match channel 2

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Reference

-

SOF1

Table 231

Table 233
Table 234

SGPIO3

T0 match
channel 2

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Chapter 18: LPC43xx/LPC43Sxx Global Input Multiplexer Array (GIMA)

Table 207. GIMA outputs
GIMA
output

GIMA output
connected to

GIMA inputs

26

Event router input 14

SCT output 6 or T1
match channel 2

SGPIO12

T1 match
channel 2

-

Table 236

27

Event router input 16

SCT output 14 or T3
match channel 2

T3 match
channel 2

-

-

Table 237

28

ADC0 and ADC1 start0
input (ADC CR register
START bits = 0x2)

SCT output 15 or T3
match channel 3

T0 match
channel 0

-

-

Table 238

29

ADC0 and ADC1 start1
input (ADC CR register
bit START = 0x3)

SCT output 8 or T2
match channel 0

T2 match
channel 0

-

-

Table 239

[1]

Reference

To configure the GIMA inputs for the timers and SCT, set the CTOUTCTRL bit in CREG6 (Section 11.4.9). This bit controls whether the
SCT outputs are ORed with the timer match output or whether the SCT outputs only are considered.

18.3.2 GIMA clock synchronization
The clock synchronization control for each GIMA output consists of five stages
(Figure 45):
1. Input selection
2. Input inversion: inverts the path between source and destination.
3. Asynchronous capture
4. Synchronization to peripheral clock
5. Pulse generation
INV

EDGE

input

SET

D

CLR

Q

Q

SYNCH

D

SET

CLR

Q

Q

D

SET

CLR

Q

Q

input

PULSE

D

SET

CLR

Q

output

Q

(peripheral)

SELECT

output_clk
(peripheral clock)

Fig 45. GIMA input stages

Once the input is selected for a GIMA output, the GIMA can synchronize the input signal
(the source) to the branch clock of the peripheral to which the GIMA output connects (the
target). For example, a signal from a pin can be synchronized to the timer branch clock if
the pin is connected to the timer capture inputs through the GIMA. Even though the timers
and the SCT have their own input synchronizer, the GIMA synchronizer can ensure that a
high-frequency input signal is correctly captured by the timer peripheral and no pulses are
missed.
The synchronization clocks are as follows:

• GIMA outputs 0 to 15: BASE_M4_CLK using the four timer branch clocks.
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Chapter 18: LPC43xx/LPC43Sxx Global Input Multiplexer Array (GIMA)

• GIMA outputs 16 to 23: BASE_M4_CLK using SCT branch clock.
• GIMA outputs 24: BASE_ADCHS_CLK
• GIMA outputs 25 to 27: no synchronization clock required because the event router
can capture a signal with edge or level sensitivity.

• GIMA outputs 28 to 29: BASE_APB3_CLK using the CLK_APB3_ADC0 branch clock
for both outputs.
Enable synchronization through the GIMA in the following situations:

• Always enable synchronization for GIMA outputs ADC start0 input and start1 input.
Both signals are synchronized to the ADC0 branch clock.

• When capturing a high-frequency input signal from a pin with the timer or SCT capture
inputs.
When connecting timer and SCT signals internally through the GIMA, no synchronization
is necessary because all timers use the BASE_M4_CLK as peripheral clock.

Table 208. Configuration options for the GIMA clock synchronization stages
GIMA output register
setting

Description

EDGE
(bit 1)

SYNCH PULSE
(bit 2)
(bit 3)

0

0

0

Asynchronous propagation of the signal from GIMA input to
peripheral. Use this option when the peripheral can synchronize the
input signal.

0

1

0

Synchronize GIMA input signal to peripheral branch clock.
Frequency of the input signal (source) must be lower than frequency
of the branch clock for the GIMA output (target).

0

1

1

Synchronize GIMA input signal to peripheral branch clock and
create a single-cycle pulse of the branch clock for the GIMA output
(target). Frequency of the input signal (source) must be lower than
frequency of the branch clock for the GIMA output (target).

1

1

1

Convert clock pulses from a higher-frequency input (source) to clock
pulses of the GIMA output branch (source) clock. In this mode, the
GIMA output can capture a short pulse from the input. Note that the
synchronization and clearing steps take a total of three clock cycles
of the output branch clock.

18.4 Register description
Table 209. Register overview: GIMA (base address: 0x400C 7000)
Name

Access Address
offset

Description

Reset Reference
value

CAP0_0_IN

R/W

0x000

Timer 0 CAP0_0 capture input multiplexer (GIMA
output 0)

0

Table 210

CAP0_1_IN

R/W

0x004

Timer 0 CAP0_1 capture input multiplexer (GIMA
output 1)

0

Table 211

CAP0_2_IN

R/W

0x008

Timer 0 CAP0_2 capture input multiplexer (GIMA
output 2)

0

Table 212

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Chapter 18: LPC43xx/LPC43Sxx Global Input Multiplexer Array (GIMA)

Table 209. Register overview: GIMA (base address: 0x400C 7000)
Name

Access Address
offset

Description

Reset Reference
value

CAP0_3_IN

R/W

0x00C

Timer 0 CAP0_3 capture input multiplexer (GIMA
output 3)

0

Table 213

CAP1_0_IN

R/W

0x010

Timer 1 CAP1_0 capture input multiplexer (GIMA
output 4)

0

Table 214

CAP1_1_IN

R/W

0x014

Timer 1 CAP1_1 capture input multiplexer (GIMA
output 5)

0

Table 215

CAP1_2_IN

R/W

0x018

Timer 1 CAP1_2 capture input multiplexer (GIMA
output 6)

0

Table 216

CAP1_3_IN

R/W

0x01C

Timer 1 CAP1_3 capture input multiplexer (GIMA
output 7)

0

Table 217

CAP2_0_IN

R/W

0x020

Timer 2 CAP2_0 capture input multiplexer (GIMA
output 8)

0

Table 218

CAP2_1_IN

R/W

0x024

Timer 2 CAP2_1 capture input multiplexer (GIMA
output 9)

0

Table 219

CAP2_2_IN

R/W

0x028

Timer 2 CAP2_2 capture input multiplexer (GIMA
output 10)

0

Table 220

CAP2_3_IN

R/W

0x02C

Timer 2 CAP2_3 capture input multiplexer (GIMA
output 11)

0

Table 221

CAP3_0_IN

R/W

0x030

Timer 3 CAP3_0 capture input multiplexer (GIMA
output 12)

0

Table 222

CAP3_1_IN

R/W

0x034

Timer 3 CAP3_1 capture input multiplexer (GIMA
output 13)

0

Table 223

CAP3_2_IN

R/W

0x038

Timer 3 CAP3_2 capture input multiplexer (GIMA
output 14)

0

Table 224

CAP3_3_IN

R/W

0x03C

Timer 3 CAP3_3 capture input multiplexer (GIMA
output 15)

0

Table 225

CTIN_0_IN

R/W

0x040

SCT CTIN_0 capture input multiplexer (GIMA output 0
16)

Table 226

CTIN_1_IN

R/W

0x044

SCT CTIN_1 capture input multiplexer (GIMA output 0
17)

Table 227

CTIN_2_IN

R/W

0x048

SCT CTIN_2 capture input multiplexer (GIMA output 0
18)

Table 228

CTIN_3_IN

R/W

0x04C

SCT CTIN_3 capture input multiplexer (GIMA output 0
19)

Table 229

CTIN_4_IN

R/W

0x050

SCT CTIN_4 capture input multiplexer (GIMA output 0
20)

Table 230

CTIN_5_IN

R/W

0x054

SCT CTIN_5 capture input multiplexer (GIMA output 0
21)

Table 231

CTIN_6_IN

R/W

0x058

SCT CTIN_6 capture input multiplexer (GIMA output 0
22)

Table 232

CTIN_7_IN

R/W

0x05C

SCT CTIN_7 capture input multiplexer (GIMA output 0
23)

Table 233

ADCHS_TRIGGER_IN

R/W

0x060

ADCHS trigger input multiplexer (GIMA output 24)

0

Table 234

EVENTROUTER_13_IN

R/W

0x064

Event router input 13 multiplexer (GIMA output 25)

0

Table 235

EVENTROUTER_14_IN

R/W

0x068

Event router input 14 multiplexer (GIMA output 26)

0

Table 236

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Chapter 18: LPC43xx/LPC43Sxx Global Input Multiplexer Array (GIMA)

Table 209. Register overview: GIMA (base address: 0x400C 7000)
Name

Access Address
offset

Description

Reset Reference
value

EVENTROUTER_16_IN

R/W

0x06C

Event router input 16 multiplexer (GIMA output 27)

0

Table 237

ADCSTART0_IN

R/W

0x070

ADC start0 input multiplexer (GIMA output 28)

0

Table 238

ADCSTART1_IN

R/W

0x074

ADC start1 input multiplexer (GIMA output 29)

0

Table 239

18.4.1 Timer 0 CAP0_0 capture input multiplexer (CAP0_0_IN)
Table 210. Timer 0 CAP0_0 capture input multiplexer (CAP0_0_IN, address 0x400C 7000) bit
description
Bit

Symbol

0

INV

1

2

3

7:4

31:8

Value

Description

Reset
value

Invert input

0

0

Not inverted.

1

Input inverted.

EDGE

Enable rising edge detection
0

No edge detection.

1

Rising edge detection enabled.

SYNCH

0

Enable synchronization
0

Disable synchronization.

1

Enable synchronization.

PULSE

0

Enable single pulse generation.
0

Disable single pulse generation.

1

Enable single pulse generation.

SELECT

0

Select input. Values 0x3 to 0xF are reserved.
0x0

CTIN_0

0x1

SGPIO3

0x2

T0_CAP0

-

0

Reserved

-

18.4.2 Timer 0 CAP0_1 capture input multiplexer (CAP0_1_IN)
Table 211. Timer 0 CAP0_1 capture input multiplexer (CAP0_1_IN, address 0x400C 7004) bit
description
Bit

Symbol

0

INV

1

UM10503

User manual

Value

Description

Reset
value

Invert input

0

0

Not inverted.

1

Input inverted.

EDGE

Enable rising edge detection
0

No edge detection.

1

Rising edge detection enabled.

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Chapter 18: LPC43xx/LPC43Sxx Global Input Multiplexer Array (GIMA)

Table 211. Timer 0 CAP0_1 capture input multiplexer (CAP0_1_IN, address 0x400C 7004) bit
description
Bit

Symbol

2

SYNCH

3

7:4

31:8

Value

Description

Reset
value

Enable synchronization

0

0

Disable synchronization.

1

Enable synchronization.

PULSE

Enable single pulse generation.
0

Disable single pulse generation.

1

Enable single pulse generation.

SELECT

0

Select input. Values 0x3 to 0xF are reserved.
0x0

CTIN_1

0x1

USART2 TX active

0x2

T0_CAP1

-

Reserved

0

-

18.4.3 Timer 0 CAP0_2 capture input multiplexer (CAP0_2_IN)
Table 212. Timer 0 CAP0_2 capture input multiplexer (CAP0_2_IN, address 0x400C 7008) bit
description
Bit

Symbol

0

INV

1

Value

7:4

31:8

UM10503

User manual

0

Not inverted.
Input inverted.

EDGE

Enable rising edge detection

0

No edge detection.
Rising edge detection enabled.

SYNCH

Enable synchronization
0

Disable synchronization.

1

Enable synchronization.

PULSE

0

Enable single pulse generation.
0

Disable single pulse generation.

1

Enable single pulse generation.

SELECT

-

Invert input
1

1

3

Reset
value

0

0
2

Description

0

Select input. Values 0x3 to 0xF are reserved.
0x0

CTIN_2

0x1

SGPIO3_DIV

0x2

T0_CAP2
Reserved

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Chapter 18: LPC43xx/LPC43Sxx Global Input Multiplexer Array (GIMA)

18.4.4 Timer 0 CAP0_3 capture input multiplexer (CAP0_3_IN)
Table 213. Timer 0 CAP0_3 capture input multiplexer (CAP0_3_IN, address 0x400C 700C) bit
description
Bit

Symbol

0

INV

1

2

3

Value

Invert input

0

Not inverted.

1

Input inverted.

0

No edge detection.

1

Rising edge detection enabled.

EDGE

Enable rising edge detection

SYNCH

0

Enable synchronization
0

Disable synchronization.

1

Enable synchronization.

PULSE

0

Enable single pulse generation.

0

Disable single pulse generation.

1

31:8

Reset
value

0

0
7:4

Description

Enable single pulse generation.

SELECT

Select input. Values 0x3 to 0xF are reserved.
0x0

CTOUT_15 or T3_MAT3

0x1

T0_CAP3

0x2

T3_MAT3

-

0

Reserved

-

18.4.5 Timer 1 CAP1_0 capture input multiplexer (CAP1_0_IN)
Table 214. Timer 1 CAP1_0 capture input multiplexer (CAP1_0_IN, address 0x400C 7010) bit
description
Bit

Symbol

0

INV

1

2

3

UM10503

User manual

Value

Description

Reset
value

Invert input

0

0

Not inverted.

1

Input inverted.

EDGE

Enable rising edge detection
0

No edge detection.

1

Rising edge detection enabled.

SYNCH

Enable synchronization
0

Disable synchronization.

1

Enable synchronization.

PULSE

Enable single pulse generation.
0

Disable single pulse generation.

1

Enable single pulse generation.

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0

0

0

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Chapter 18: LPC43xx/LPC43Sxx Global Input Multiplexer Array (GIMA)

Table 214. Timer 1 CAP1_0 capture input multiplexer (CAP1_0_IN, address 0x400C 7010) bit
description
Bit

Symbol

7:4

SELECT

31:8

Value

Description

Reset
value

Select input. Values 0x3 to 0xF are reserved.

0

0x0

CTIN_0

0x1

SGPIO12

0x2

T1_CAP0

-

Reserved

-

18.4.6 Timer 1 CAP1_1 capture input multiplexer (CAP1_1_IN)
Table 215. Timer 1 CAP1_1 capture input multiplexer (CAP1_1_IN, address 0x400C 7014) bit
description
Bit

Symbol

0

INV

1

2

3

7:4

31:8

Value

Description

Reset
value

Invert input

0

0

Not inverted.

1

Input inverted.

EDGE

Enable rising edge detection
0

No edge detection.

1

Rising edge detection enabled.

SYNCH

0

Enable synchronization
0

Disable synchronization.

1

Enable synchronization.

PULSE

0

Enable single pulse generation.
0

Disable single pulse generation.

1

Enable single pulse generation.

SELECT

0

Select input. Values 0x3 to 0xF are reserved.
0x0

CTIN_3

0x1

USART0 TX active

0x2

T1_CAP1

-

0

Reserved

-

18.4.7 Timer 1 CAP1_2 capture input multiplexer (CAP1_2_IN)
Table 216. Timer 1 CAP1_2 capture input multiplexer (CAP1_2_IN, address 0x400C 7018) bit
description
Bit

Symbol

0

INV

Value

0
1
1

UM10503

User manual

EDGE

Description

Reset
value

Invert input

0

Not inverted.
Input inverted.
Enable rising edge detection

0

No edge detection.

1

Rising edge detection enabled.

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Chapter 18: LPC43xx/LPC43Sxx Global Input Multiplexer Array (GIMA)

Table 216. Timer 1 CAP1_2 capture input multiplexer (CAP1_2_IN, address 0x400C 7018) bit
description
Bit

Symbol

2

SYNCH

3

7:4

Value

Description

Reset
value

Enable synchronization

0

0

Disable synchronization.

1

Enable synchronization.

PULSE

Enable single pulse generation.
0

Disable single pulse generation.

1

Enable single pulse generation.

SELECT

Select input. Values 0x3 to 0xF are reserved.
0x0

31:8

0

CTIN_4

0x1

USART0 RX active

0x2

T1_CAP2

-

0

Reserved

-

18.4.8 Timer 1 CAP1_3 capture input multiplexer (CAP1_3_IN)
Table 217. Timer 1 CAP1_3 capture input multiplexer (CAP1_3_IN, address 0x400C 701C) bit
description
Bit

Symbol

0

INV

1

2

3

7:4

31:8

UM10503

User manual

Value

Reset
value

Invert input

0

0

Not inverted.

1

Input inverted.

EDGE

Enable rising edge detection
0

No edge detection.

1

Rising edge detection enabled.

SYNCH

0

Enable synchronization
0

Disable synchronization.

1

Enable synchronization.

PULSE

0

Enable single pulse generation.
0

Disable single pulse generation.

1

Enable single pulse generation.

SELECT

-

Description

0

Select input. Values 0x3 to 0xF are reserved.
0x0

CTOUT_3 or T0_MAT3

0x1

T1_CAP3

0x2

T0_MAT3
Reserved

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Chapter 18: LPC43xx/LPC43Sxx Global Input Multiplexer Array (GIMA)

18.4.9 Timer 2 CAP2_0 capture input multiplexer (CAP2_0_IN)
Table 218. Timer 2 CAP2_0 capture input multiplexer (CAP2_0_IN, address 0x400C 7020) bit
description
Bit

Symbol

0

INV

1

2

3

Value

Invert input

0

Not inverted.

1

Input inverted.

EDGE

Enable rising edge detection
0

No edge detection.

1

Rising edge detection enabled.

SYNCH

0

Enable synchronization
0

Disable synchronization.

1

Enable synchronization.

PULSE

0

Enable single pulse generation.

0

Disable single pulse generation.

1

31:8

Reset
value

0

0
7:4

Description

Enable single pulse generation.

SELECT

Select input. Values 0x4 to 0xF are reserved.
0x0

CTIN_0

0x1

SGPIO12_DIV

0x2

T2_CAP0

-

Reserved

0

-

18.4.10 Timer 2 CAP2_1 capture input multiplexer (CAP2_1_IN)
Table 219. Timer 2 CAP2_1 capture input multiplexer (CAP2_1_IN, address 0x400C 7024) bit
description
Bit

Symbol

0

INV

1

2

3

UM10503

User manual

Value

Description

Reset
value

Invert input

0

0

Not inverted.

1

Input inverted.

EDGE

Enable rising edge detection
0

No edge detection.

1

Rising edge detection enabled.

SYNCH

Enable synchronization
0

Disable synchronization.

1

Enable synchronization.

PULSE

Enable single pulse generation.
0

Disable single pulse generation.

1

Enable single pulse generation.

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Rev. 2.4 — 22 August 2018

0

0

0

© NXP B.V. 2018. All rights reserved.

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NXP Semiconductors

Chapter 18: LPC43xx/LPC43Sxx Global Input Multiplexer Array (GIMA)

Table 219. Timer 2 CAP2_1 capture input multiplexer (CAP2_1_IN, address 0x400C 7024) bit
description
Bit

Symbol

7:4

SELECT

31:8

Value

Description

Reset
value

Select input. Values 0x4 to 0xF are reserved.

0

0x0

CTIN_1

0x1

USART2 TX active

0x2

I2S1_RX_MWS

0x3

T2_CAP1

-

Reserved

-

18.4.11 Timer 2 CAP2_2 capture input multiplexer (CAP2_2_IN)
Table 220. Timer 2 CAP2_2 capture input multiplexer (CAP2_2_IN, address 0x400C 7028) bit
description
Bit

Symbol

0

INV

Value

0

2

3

7:4

Invert input

0

Input inverted.

EDGE

Enable rising edge detection
0

No edge detection.

1

Rising edge detection enabled.

SYNCH

0

Enable synchronization
0

Disable synchronization.

1

Enable synchronization.

PULSE

0

Enable single pulse generation.
0

Disable single pulse generation.

1

Enable single pulse generation.

SELECT

0

Select input. Values 0x4 to 0xF are reserved.
0x0

31:8

Reset
value

Not inverted.

1
1

Description

0

CTIN_5

0x1

USART2 RX active

0x2

I2S1_TX_MWS

0x3

T2_CAP2

-

Reserved

-

18.4.12 Timer 2 CAP2_3 capture input multiplexer (CAP2_3_IN)
Table 221. Timer 2 CAP2_3 capture input multiplexer (CAP2_3_IN, address 0x400C 702C) bit
description

UM10503

User manual

Bit

Symbol

0

INV

Value

Description

Reset
value

Invert input

0

0

Not inverted.

1

Input inverted.

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Chapter 18: LPC43xx/LPC43Sxx Global Input Multiplexer Array (GIMA)

Table 221. Timer 2 CAP2_3 capture input multiplexer (CAP2_3_IN, address 0x400C 702C) bit
description
Bit

Symbol

1

EDGE

2

Value

0

1

Rising edge detection enabled.
Enable synchronization

0

Disable synchronization.

1

Enable synchronization.

0

Enable single pulse generation.
0
1

SELECT

0

Disable single pulse generation.
Enable single pulse generation.
Select input. Values 0x3 to 0xF are
reserved.

0x0

31:8

Enable rising edge detection
No edge detection.

PULSE

7:4

Reset
value

0
SYNCH

3

Description

-

0

CTOUT_7 or T1_MAT3

0x1

T2_CAP3

0x2

T1_MAT3
Reserved

-

18.4.13 Timer 3 CAP3_0 capture input multiplexer (CAP3_0_IN)
Table 222. Timer 3 CAP3_0 capture input multiplexer (CAP3_0_IN, address 0x400C 7030) bit
description
Bit

Symbol

0

INV

1

Value

7:4

31:8

UM10503

User manual

0

Not inverted.
Input inverted.

EDGE

Enable rising edge detection

0

No edge detection.
Rising edge detection enabled.

SYNCH

Enable synchronization
0

Disable synchronization.

1

Enable synchronization.

PULSE

Enable single pulse generation.
0

Disable single pulse generation.

1

Enable single pulse generation.

SELECT

-

Invert input
1

1

3

Reset
value

0

0
2

Description

0

0

Select input. Values 0x3 to 0xF are reserved. 0
0x0

CTIN_0

0x1

I2S0_RX_MWS

0x2

T3_CAP0
Reserved

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-

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Chapter 18: LPC43xx/LPC43Sxx Global Input Multiplexer Array (GIMA)

18.4.14 Timer 3 CAP3_1 capture input multiplexer (CAP3_1_IN)
Table 223. Timer 3 CAP3_1 capture input multiplexer (CAP3_1_IN, address 0x400C 7034) bit
description
Bit

Symbol

0

INV

1

2

3

7:4

31:8

Value

Description

Reset
value

Invert input

0

0

Not inverted.

1

Input inverted.

0

No edge detection.

1

Rising edge detection enabled.

EDGE

Enable rising edge detection

SYNCH

0

Enable synchronization
0

Disable synchronization.

1

Enable synchronization.

PULSE

0

Enable single pulse generation.
0

Disable single pulse generation.

1

Enable single pulse generation.

SELECT

0

Select input. Values 0x4 to 0xF are reserved.
0x0

CTIN_6

0x1

USART3 TX active

0x2

I2S0_TX_MWS

0x3

T3_CAP1

-

0

Reserved

-

18.4.15 Timer 3 CAP3_2 capture input multiplexer (CAP3_2_IN)
Table 224. Timer 3 CAP3_2 capture input multiplexer (CAP3_2_IN, address 0x400C 7038) bit
description
Bit

Symbol

0

INV

Value
0
1

1

2

3

UM10503

User manual

EDGE

Description

Reset value

Invert input

0

Not inverted.
Input inverted.
Enable rising edge detection

0

No edge detection.

1

Rising edge detection enabled.

SYNCH

Enable synchronization
0

Disable synchronization.

1

Enable synchronization.

PULSE

Enable single pulse generation.
0

Disable single pulse generation.

1

Enable single pulse generation.

All information provided in this document is subject to legal disclaimers.

Rev. 2.4 — 22 August 2018

0

0

0

© NXP B.V. 2018. All rights reserved.

448 of 1444

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NXP Semiconductors

Chapter 18: LPC43xx/LPC43Sxx Global Input Multiplexer Array (GIMA)

Table 224. Timer 3 CAP3_2 capture input multiplexer (CAP3_2_IN, address 0x400C 7038) bit
description
Bit

Symbol

7:4

SELECT

31:8

Value

Description

Reset value

Select input. Values 0x4 to 0xF are reserved. 0
0x0

CTIN_7

0x1

USART3 RX active

0x2

SOF0 (Start-Of-Frame USB0)

0x3

T3_CAP2

-

Reserved

-

18.4.16 Timer 3 CAP3_3 capture input multiplexer (CAP3_3_IN)
Table 225. Timer 3 CAP3_3 capture input multiplexer (CAP3_3_IN, address 0x400C 703C) bit
description
Bit

Symbol

0

INV

1

2

3

Value

Invert input

0

Not inverted.

1

Input inverted.

0

No edge detection.

1

Rising edge detection enabled.

EDGE

Enable rising edge detection

SYNCH

0

Enable synchronization
0

Disable synchronization.

1

Enable synchronization.

PULSE

0

Enable single pulse generation.

0

Disable single pulse generation.

1

31:8

Reset
value

0

0
7:4

Description

Enable single pulse generation.

SELECT

Select input. Values 0x4 to 0xF are reserved.
0x0

CTOUT11 or T2_MAT3

0x1

SOF1 (Start-Of-Frame USB1)

0x2

T3_CAP3

0x3

T2_MAT3

-

0

Reserved

-

18.4.17 SCT CTIN_0 capture input multiplexer (CTIN_0_IN)
Table 226. SCT CTIN_0 capture input multiplexer (CTIN_0_IN, address 0x400C 7040) bit
description

UM10503

User manual

Bit

Symbol

0

INV

Value

Description

Reset value

Invert input

0

0

Not inverted.

1

Input inverted.

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Chapter 18: LPC43xx/LPC43Sxx Global Input Multiplexer Array (GIMA)

Table 226. SCT CTIN_0 capture input multiplexer (CTIN_0_IN, address 0x400C 7040) bit
description
Bit

Symbol

1

EDGE

2

Value

31:8

Enable rising edge detection

0

No edge detection.

1

Rising edge detection enabled.

SYNCH

Enable synchronization

0

Disable synchronization.

1

7:4

Reset value

0

0
3

Description

Enable synchronization.

PULSE

Enable single pulse generation.
0

Disable single pulse generation.

1

Enable single pulse generation.

SELECT

Select input. Values 0x3 to 0xF are reserved.
0x0

CTIN_0

0x1

SGPIO3

0x2

SGPIO3_DIV

-

Reserved

0

0

-

18.4.18 SCT CTIN_1 capture input multiplexer (CTIN_1_IN)
Table 227. SCT CTIN_1 capture input multiplexer (CTIN_1_IN, address 0x400C 7044) bit
description
Bit

Symbol

0

INV

1

2

Value Description
Invert input
0

Not inverted.

1

Input inverted.

EDGE

Enable rising edge detection
0

No edge detection.

1

Rising edge detection enabled.

SYNCH

Enable synchronization
0
1

3

7:4

31:8

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PULSE

-

0

0

0

Disable synchronization.
Enable synchronization.
Enable single pulse generation.

0

Disable single pulse generation.

1

Enable single pulse generation.

SELECT

Reset value

Select input. Values 0x3 to 0xF are reserved.
0x0

CTIN_1

0x1

USART2 TX active

0x2

SGPIO12
Reserved

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18.4.19 SCT CTIN_2 capture input multiplexer (CTIN_2_IN)
Table 228. SCT CTIN_2 capture input multiplexer (CTIN_2_IN, address 0x400C 7048) bit
description
Bit

Symbol

0

INV

1

2

Value Description
Invert input
0

Not inverted.

1

Input inverted.

EDGE

Enable rising edge detection
0

No edge detection.

1

Rising edge detection enabled.

SYNCH

Enable synchronization
0

7:4

31:8

0

0

0

Disable synchronization.

1
3

Reset value

Enable synchronization.

PULSE

Enable single pulse generation.
0

Disable single pulse generation.

1

Enable single pulse generation.

SELECT

Select input. Values 0x3 to 0xF are reserved.
0x0

CTIN_2

0x1

SGPIO12

0x2

SGPIO12_DIV

-

Reserved

0

0

-

18.4.20 SCT CTIN_3 capture input multiplexer (CTIN_3_IN)
Table 229. SCT CTIN_3 capture input multiplexer (CTIN_3_IN, address 0x400C 704C) bit
description
Bit

Symbol

0

INV

1

2

Value

Description

Reset value

Invert input

0

0

Not inverted.

1

Input inverted.

EDGE

Enable rising edge detection
0

No edge detection.

1

Rising edge detection enabled.

SYNCH

Enable synchronization
0
1

3

UM10503

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PULSE

0

0

Disable synchronization.
Enable synchronization.
Enable single pulse generation.

0

Disable single pulse generation.

1

Enable single pulse generation.

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Table 229. SCT CTIN_3 capture input multiplexer (CTIN_3_IN, address 0x400C 704C) bit
description
Bit

Symbol

7:4

SELECT

31:8

Value

Description

Reset value

Select input. Values 0x4 to 0xF are reserved.

0

0x0

CTIN_3

0x1

USART0 TX active

0x2

I2S1_RX_MWS

0x3

I2S1_TX_MWS

-

Reserved

-

18.4.21 SCT CTIN_4 capture input multiplexer (CTIN_4_IN)
Table 230. SCT CTIN_4 capture input multiplexer (CTIN_4_IN, address 0x400C 7050) bit
description
Bit

Symbol

0

INV

1

2

Value

31:8

Invert input

0

Not inverted.

1

Input inverted.

EDGE

Enable rising edge detection
0

No edge detection.

1

Rising edge detection enabled.

SYNCH

Enable synchronization

0

0

Disable synchronization.

1

7:4

Reset value

0

0
3

Description

Enable synchronization.

PULSE

Enable single pulse generation.
0

Disable single pulse generation.

1

Enable single pulse generation.

0x0

CTIN_4

0x1

USART0 RX active

0x2

I2S1_RX_MWS

0x3

I2S1_TX_MWS

SELECT

Select input. Values 0x4 to 0xF are reserved.

-

Reserved

0

0

-

18.4.22 SCT CTIN_5 capture input multiplexer (CTIN_5_IN)
Table 231. SCT CTIN_5 capture input multiplexer (CTIN_5_IN, address 0x400C 7054) bit
description
Bit

Symbol

0

INV

1

UM10503

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Value

Description

Reset value

Invert input

0

0

Not inverted.

1

Input inverted.

0

No edge detection.

1

Rising edge detection enabled.

EDGE

Enable rising edge detection

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Table 231. SCT CTIN_5 capture input multiplexer (CTIN_5_IN, address 0x400C 7054) bit
description
Bit

Symbol

2

SYNCH

3

Value

Enable synchronization

0

Disable synchronization.

1

Enable synchronization.

PULSE

Enable single pulse generation.

0

Disable single pulse generation.

1

31:8

Reset value

0

0
7:4

Description

Enable single pulse generation.

SELECT

Select input. Values 0x3 to 0xF are reserved. 0
0x0

CTIN_5

0x1

USART2 RX active

0x2

SGPIO12_DIV

-

Reserved

-

18.4.23 SCT CTIN_6 capture input multiplexer (CTIN_6_IN)
Table 232. SCT CTIN_6 capture input multiplexer (CTIN_6_IN, address 0x400C 7058) bit
description
Bit

Symbol

0

INV

1

2

3

Value

1

Input inverted.

EDGE

Enable rising edge detection
0

No edge detection.

1

Rising edge detection enabled.

SYNCH

Enable synchronization
0

Disable synchronization.

1

Enable synchronization.

PULSE

Enable single pulse generation.

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SELECT

-

0

Not inverted.

1

31:8

Reset value

Invert input
0

0
7:4

Description

0

0

0

Disable single pulse generation.
Enable single pulse generation.
Select input. Values 0x4 to 0xF are
reserved.

0x0

CTIN_6

0x1

USART3 TX active

0x2

I2S0_RX_MWS

0x3

I2S0_TX_MWS
Reserved

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18.4.24 SCT CTIN_7 capture input multiplexer (CTIN_7_IN)
Table 233. SCT CTIN_7 capture input multiplexer (CTIN_7_IN, address 0x400C 705C) bit
description
Bit

Symbol

0

INV

1

2

Value

31:8

Invert input

0

Not inverted.

1

Input inverted.

EDGE

Enable rising edge detection
0

No edge detection.

1

Rising edge detection enabled.

SYNCH

Enable synchronization

0

0

Disable synchronization.

1

7:4

Reset value

0

0
3

Description

Enable synchronization.

PULSE

Enable single pulse generation.
0

Disable single pulse generation.

1

Enable single pulse generation.

0x0

CTIN_7

0x1

USART3 RX active

0x2

SOF0 (Start-Of-Frame USB0)

0x3

SOF1 (Start-Of-Frame USB1)

SELECT

Select input. Values 0x4 to 0xF are reserved.

-

Reserved

0

0

-

18.4.25 ADCHS trigger input multiplexer (ADCHS_TRIGGER_IN)
For details on the ADCHS triggers, see also Section 48.7.6.
Table 234. ADCHS trigger input multiplexer (ADCHS_TRIGGER_IN, address 0x400C 7060) bit
description
Bit

Symbol

0

INV

1

Value Description
Invert input
0

Not inverted.

1

Input inverted.

EDGE

Enable rising edge detection
0
1

2

3

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SYNCH

0

0

No edge detection.
Rising edge detection enabled.
Enable synchronization

0

Disable synchronization.

1

Enable synchronization.

PULSE

Reset value

Enable single pulse generation.
0

Disable single pulse generation.

1

Enable single pulse generation.

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Table 234. ADCHS trigger input multiplexer (ADCHS_TRIGGER_IN, address 0x400C 7060) bit
description …continued
Bit

Symbol

7:4

SELECT

31:8

Value Description
Select input. Values 0xA to 0xF are reserved.
0x0

GPIO6[28]

0x1

GPIO5[3]

0x2

SGPIO10

0x3

SGPIO12

0x4

Reserved

0x5

MCOB2

0x6

CTOUT_0 or T0_MAT0

0x7

CTOUT_8 or T2_MAT0

0x8

T0_MAT0

0x9

T2_MAT0

-

Reserved

Reset value
0

-

18.4.26 Event router input 13 multiplexer (EVENTROUTER_13_IN)
Table 235. Event router input 13 multiplexer (EVENTROUTER_13_IN, address 0x400C 7064)
bit description
Bit

Symbol

0

INV

Value Description
Invert input
0

2

3

7:4

Input inverted.

EDGE

Enable rising edge detection
0

No edge detection.

1

Rising edge detection enabled.

SYNCH

Enable synchronization
0

Disable synchronization.

1

Enable synchronization.

PULSE

Enable single pulse generation.
0

Disable single pulse generation.

1

Enable single pulse generation.

SELECT

Select input. Values 0x3 to 0xF are reserved.
0x0

31:8

UM10503

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-

0

Not inverted.

1
1

Reset value

0

0

0

0

CTOUT_2 or T0_MAT2

0x1

SGPIO3

0x2

T0_MAT2
Reserved

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Chapter 18: LPC43xx/LPC43Sxx Global Input Multiplexer Array (GIMA)

18.4.27 Event router input 14 multiplexer (EVENTROUTER_14_IN)
Table 236. Event router input 14 multiplexer (EVENTROUTER_14_IN, address 0x400C 7068)
bit description
Bit

Symbol

0

INV

1

Value

Description

Reset value

Invert input

0

0

Not inverted.

1

Input inverted.

EDGE

2

Enable rising edge detection
0

No edge detection.

1

Rising edge detection enabled.

SYNCH

Enable synchronization
0

Enable synchronization.

PULSE

7:4

Enable single pulse generation.
0

Disable single pulse generation.

1

Enable single pulse generation.

SELECT

31:8

0

Disable synchronization.

1
3

0

0

Select input. Values 0x3 to 0xF are reserved. 0
0x0

CTOUT_6 or T1_MAT2

0x1

SGPIO12

0x2

T1_MAT2

-

Reserved

-

18.4.28 Event router input 16 multiplexer (EVENTROUTER_16_IN)
Table 237. Event router input 16multiplexer (EVENTROUTER_16_IN, address 0x400C 706C)
bit description
Bit

Symbol

0

INV

1

2

Value

Description

Reset value

Invert input

0

0

Not inverted.

1

Input inverted.

EDGE

Enable rising edge detection
0

No edge detection.

1

Rising edge detection enabled.

SYNCH

Enable synchronization
0

7:4

31:8
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Enable synchronization.

PULSE

Enable single pulse generation.
0

Disable single pulse generation.

1

Enable single pulse generation.

SELECT

-

0

Disable synchronization.

1
3

0

Select input. Values 0x2 to 0xF are reserved.
0x0

CTOUT_14 or T3_MAT2

0x1

T3_MAT2
Reserved

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18.4.29 ADC start0 input multiplexer (ADCSTART0_IN)
Table 238. ADC start0 input multiplexer (ADCSTART0_IN, address 0x400C 7070) bit
description
Bit

Symbol

0

INV

1

Value

Description

Reset value

Invert input

0

0

Not inverted.

1

Input inverted.

EDGE

2

Enable rising edge detection
0

No edge detection.

1

Rising edge detection enabled.

SYNCH

3

Enable synchronization
0

Disable synchronization.

1

Enable synchronization.

PULSE

7:4

Enable single pulse generation.
0

Disable single pulse generation.

1

Enable single pulse generation.

0x0

CTOUT_15 or T3_MAT3

0x1

T0_MAT0

SELECT

31:8

Select input. Values 0x2 to 0xF are reserved.

-

Reserved

0

0

0

0

-

18.4.30 ADC start1 input multiplexer (ADCSTART1_IN)
Table 239. ADC start1 input multiplexer (ADCSTART1_IN, address 0x400C 7074) bit
description
Bit

Symbol

0

INV

1

2

3

7:4

31:8

UM10503

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Value

Reset value

Invert input

0

0

Not inverted.

1

Input inverted.

EDGE

Enable rising edge detection
0

No edge detection.

1

Rising edge detection enabled.

SYNCH

Enable synchronization
0

Disable synchronization.

1

Enable synchronization.

0

Disable single pulse generation.

1

Enable single pulse generation.

PULSE

Enable single pulse generation.

SELECT

-

Description

Select input. Values 0x2 to 0xF are reserved.
0x0

CTOUT_8 or T2_MAT0

0x1

T2_MAT0
Reserved

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Rev. 2.4 — 22 August 2018

User manual

19.1 How to read this chapter
All GPIO register bit descriptions refer to up to 31 pins on each GPIO port. Depending on
the package type, not all pins are available, and the corresponding bits in the GPIO
registers are reserved (see Table 240).
Table 240. GPIO pins for different pin packages
LBGA256

TFBGA180

TFBGA100

LQFP208

LQFP144

LQFP100

GPIO Port 0

GPIO0[15:0]

GPIO0[15:0]

GPIO0[4:0];
GPIO0[15:6]

GPIO0[15:0]

GPIO0[15:0]

-

GPIO Port 1

GPIO1[15:0]

GPIO1[15:0]

GPIO1[15:0]

GPIO1[15:0]

GPIO1[15:0]

-

GPIO Port 2

GPIO2[15:0]

GPIO2[15:0]

-

GPIO2[15:0]

GPIO2[15:0]

-

GPIO Port 3

GPIO3[15:0]

GPIO3[15:0]

GPIO3[1:0];
GPIO3[5:3];
GPIO3[7]

GPIO3[15:0]

GPIO3[15:0]

-

GPIO Port 4

GPIO4[15:0]

GPIO4[15:0]

-

GPIO4[15:0]

GPIO4[11]

-

GPIO Port 5

GPIO5[26:0]

GPIO5[26:0]

GPIO5[11:0]

GPIO5[25:0]

GPIO5[16:0];
GPIO5[18]

-

GPIO Port 6

GPIO6[30:0]

GPIO6[26:25];
GPIO[30:28]

-

GPIO6[5:0];
GPIO6[30:20]

-

-

GPIO Port 7

GPIO7[25:0]

GPIO7[4:0]

-

GPIO7[10:0];
GPIO7[21:17];
GPIO7[25:23]

-

-

19.2 Basic configuration
The GPIO blocks share a common clock and reset connection and are configured as
follows:

• See Table 241 for clocking and power control.
• The GPIO is reset by a GPIO_RST (reset #28).
• All GPIO pins are set to input by default. To read the signal on the GPIO input, enable
the input buffer in the SCU block for the corresponding pin (see Table 191 to
Table 193).

• For the pin interrupts, select up to 8 external interrupt pins from all GPIO port pins in
the SCU (see Table 204 and Table 205). The pin interrupts must be enabled in the
NVIC (see Table 77).

• The GPIO group interrupts must be enabled in the NVIC (see Table 77).
• GPIO port registers can be accessed by the GPDMA as memory-to-memory transfer.
Table 241. GPIO clocking and power control

GPIO, GPIO pin interrupt, GPIO group0
interrupt, GPIO group1 interrupt
UM10503

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Base clock

Branch clock

Operating
frequency

BASE_M4_CLK

CLK_M4_GPIO

up to 204 MHz

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Chapter 19: LPC43xx/LPC43Sxx GPIO

19.3 Features
19.3.1 GPIO pin interrupt features
• Up to 8 pins can be selected from all GPIO pins as edge- or level-sensitive interrupt
requests. Each request creates a separate interrupt in the NVIC.

• Edge-sensitive interrupt pins can interrupt on rising or falling edges or both.
• Level-sensitive interrupt pins can be HIGH- or LOW-active.
19.3.2 GPIO group interrupt features
• The inputs from any number of GPIO pins can be enabled to contribute to a combined
group interrupt.

• The polarity of each input enabled for the group interrupt can be configured HIGH or
LOW.

• Enabled interrupts can be logically combined through an OR or AND operation.
• Two group interrupts are supported to reflect two distinct interrupt patterns.
• The GPIO group interrupts can wake up the part from sleep mode.
19.3.3 GPIO port features
• GPIO pins can be configured as input or output by software.
• All GPIO pins default to inputs with interrupt disabled at reset.
• Pin registers allow pins to be sensed and set individually.

19.4 General description
The GPIO pins can be used in several ways to set pins as inputs or outputs and use the
inputs as combinations of level and edge sensitive interrupts.

19.4.1 GPIO pin interrupts
From all available GPIO pins, up to eight pins can be selected in the system control block
to serve as external interrupt pins. The external interrupt pins are connected to eight
individual interrupts in the NVIC and are created based on rising or falling edges or on the
input level on the pin.

19.4.2 GPIO group interrupt
For each port/pin connected to one of the two the GPIO Grouped Interrupt blocks
(GROUP0 and GROUP1), the GPIO grouped interrupt registers determine which pins are
enabled to generate interrupts and what the active polarities of each of those inputs are.
The GPIO grouped interrupt registers also select whether the interrupt output will be level
or edge triggered and whether it will be based on the OR or the AND of all of the enabled
inputs.
When the designated pattern is detected on the selected input pins, the GPIO grouped
interrupt block will generate an interrupt.
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Chapter 19: LPC43xx/LPC43Sxx GPIO

19.4.3 GPIO port
The GPIO port registers can be used to configure each GPIO pin as input or output and
read the state of each pin if the pin is configured as input or set the state of each pin if the
pin is configured as output.

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Chapter 19: LPC43xx/LPC43Sxx GPIO

19.5 Register description
The GPIO consists of the following blocks:

• The GPIO pin interrupts block at address 0x4008 7000. Registers in this block enable
the up to 8 pin interrupts selected in the PINTSELn registers (see Table 204 or
Table 205) and configure the level and edge sensitivity for each selected pin interrupt.
The GPIO interrupt registers are listed in Table 246 to Table 255.

• The GPIO GROUP0 interrupt block at address 0x4008 8000. Registers in this block
allow to configure any pin on port 0 and 1 to contribute to a combined interrupt. The
GPIO GROUP0 registers are listed in Table 243 and Section 19.5.2.

• The GPIO GROUP1 interrupt block at address 0x4008 9000. Registers in this block
allow to configure any pin on port 0 and 1 to contribute to a combined interrupt. The
GPIO GROUP1 registers are listed in Table 244 and Section 19.5.2.

• The GPIO port block at address 0x400F 4000. Registers in this block allow to read
and write to port pins and configure port pins as inputs or outputs.The GPIO port
registers are listed in Table 245 and Section 19.5.3.
Note: In all GPIO registers, bits that are not shown are reserved.
Table 242. Register overview: GPIO pin interrupts (base address: 0x4008 7000)
Name

Access Address
offset

Description

Reset Reference
value

ISEL

R/W

0x000

Pin Interrupt Mode register

0

Table 246

IENR

R/W

0x004

Pin interrupt level (rising edge) interrupt
enable register

0

Table 247

SIENR WO

0x008

Pin interrupt level (rising edge) interrupt set
register

NA

Table 248

CIENR WO

0x00C

Pin interrupt level (rising edge interrupt) clear NA
register

Table 249

IENF

R/W

0x010

Pin interrupt active level (falling edge)
interrupt enable register

0

Table 250

SIENF WO

0x014

Pin interrupt active level (falling edge)
interrupt set register

NA

Table 251

CIENF WO

0x018

Pin interrupt active level (falling edge)
interrupt clear register

NA

Table 252

RISE

R/W

0x01C

Pin interrupt rising edge register

0

Table 253

FALL

R/W

0x020

Pin interrupt falling edge register

0

Table 254

IST

R/W

0x024

Pin interrupt status register

0

Table 255

Table 243. Register overview: GPIO GROUP0 interrupt (base address 0x4008 8000)
Name

Access Address Description
offset

Reset value

Reference

CTRL

R/W

0x000

GPIO grouped interrupt control register

0

Table 256

PORT_POL0 R/W

0x020

GPIO grouped interrupt port 0 polarity register

0xFFFF FFFF

Table 257

PORT_POL1 R/W

0x024

GPIO grouped interrupt port 1 polarity register

0xFFFF FFFF

Table 257

PORT_POL2 R/W

0x028

GPIO grouped interrupt port 2 polarity register

0xFFFF FFFF

Table 257

PORT_POL3 R/W

0x02C

GPIO grouped interrupt port 3 polarity register

0xFFFF FFFF

Table 257

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Table 243. Register overview: GPIO GROUP0 interrupt (base address 0x4008 8000)
Name

Access Address Description
offset

Reset value

Reference

PORT_POL4 R/W

0x030

GPIO grouped interrupt port 4 polarity register

0xFFFF FFFF

Table 257

PORT_POL5 R/W

0x034

GPIO grouped interrupt port 5 polarity register

0xFFFF FFFF

Table 257

PORT_POL6 R/W

0x038

GPIO grouped interrupt port 6 polarity register

0xFFFF FFFF

Table 257

PORT_POL7 R/W

0x03C

GPIO grouped interrupt port 7 polarity register

0xFFFF FFFF

Table 257

PORT_ENA0 R/W

0x040

GPIO grouped interrupt port 0 enable register

0

Table 258

PORT_ENA1 R/W

0x044

GPIO grouped interrupt port 1 enable register

0

Table 258

PORT_ENA2 R/W

0x048

GPIO grouped interrupt port 2 enable register

0

Table 258

PORT_ENA3 R/W

0x04C

GPIO grouped interrupt port 3 enable register

0

Table 258

PORT_ENA4 R/W

0x050

GPIO grouped interrupt port 4 enable register

0

Table 258

PORT_ENA5 R/W

0x054

GPIO grouped interrupt port 5 enable register

0

Table 258

PORT_ENA6 R/W

0x058

GPIO grouped interrupt port 5 enable register

0

Table 258

PORT_ENA7 R/W

0x05C

GPIO grouped interrupt port 5 enable register

0

Table 258

Table 244. Register overview: GPIO GROUP1 interrupt (base address 0x4008 9000)
Name

Access Address Description
offset

Reset value

Reference

CTRL

R/W

0x000

GPIO grouped interrupt control register

0

Table 256

PORT_POL0

R/W

0x020

GPIO grouped interrupt port 0 polarity register

0xFFFF FFFF

Table 257

PORT_POL1

R/W

0x024

GPIO grouped interrupt port 1 polarity register

0xFFFF FFFF

Table 257

PORT_POL2

R/W

0x028

GPIO grouped interrupt port 2 polarity register

0xFFFF FFFF

Table 257

PORT_POL3

R/W

0x02C

GPIO grouped interrupt port 3 polarity register

0xFFFF FFFF

Table 257

PORT_POL4

R/W

0x030

GPIO grouped interrupt port 4 polarity register

0xFFFF FFFF

Table 257

PORT_POL5

R/W

0x034

GPIO grouped interrupt port 5 polarity register

0xFFFF FFFF

Table 257

PORT_POL6

R/W

0x038

GPIO grouped interrupt port 6 polarity register

0xFFFF FFFF

Table 257

PORT_POL7

R/W

0x03C

GPIO grouped interrupt port 7 polarity register

0xFFFF FFFF

Table 257

PORT_ENA0

R/W

0x040

GPIO grouped interrupt port 0 enable register

0

Table 258

PORT_ENA1

R/W

0x044

GPIO grouped interrupt port 1 enable register

0

Table 258

PORT_ENA2

R/W

0x048

GPIO grouped interrupt port 2 enable register

0

Table 258

PORT_ENA3

R/W

0x04C

GPIO grouped interrupt port 3 enable register

0

Table 258

PORT_ENA4

R/W

0x050

GPIO grouped interrupt port 4 enable register

0

Table 258

PORT_ENA5

R/W

0x054

GPIO grouped interrupt port 5 enable register

0

Table 258

PORT_ENA6

R/W

0x058

GPIO grouped interrupt port 5 enable register

0

Table 258

PORT_ENA7

R/W

0x05C

GPIO grouped interrupt port 5 enable register

0

Table 258

GPIO port addresses can be read and written as bytes, halfwords, or words.

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Table 245. Register overview: GPIO port (base address 0x400F 4000)
The highest pin number on each port depends on package size (see Table 240).
Name

Access

Address
offset

Description

B0 to B31

R/W

0x0000 to x001F

B32 to B63

R/W

0x0020 to 0x003F

B64 to B95

R/W

B96 to B127

R/W

Width

Reference

Byte pin registers port 0; pins PIO0_0 ext[1]
to PIO0_31

byte (8 bit)

Table 259

Byte pin registers port 1

ext[1]

byte (8 bit)

Table 259

0x0040 to 0x005F

Byte pin registers port 2

ext[1]

byte (8 bit)

0x0060 to 0x007F

Byte pin registers port 3

ext[1]

byte (8 bit)

Table 259

Byte pin registers port 4

ext[1]

byte (8 bit)

Table 259

B160 to B191 R/W

0x00A0 to 0x00BF Byte pin registers port 5

ext[1]

byte (8 bit)

Table 259

B192 to B223 R/W

0x00C0 to0x00DF Byte pin registers port 6

ext[1]

byte (8 bit)

Table 259

0x00E0 to 0x00FC Byte pin registers port 7

ext[1]

byte (8 bit)

Table 259

0x1000 to 0x107C Word pin registers port 0

ext[1]

word (32 bit)

Table 260

B128 to B159 R/W

B224 to B255 R/W
W0 to W31

R/W

0x0080 to 0x009F

Reset
value

W32 to W63

R/W

0x1080 to 0x10FC Word pin registers port 1

ext[1]

word (32 bit)

Table 260

W64 to W95

R/W

0x1100 to 0x11FC Word pin registers port 2

ext[1]

word (32 bit)

Table 260

0x1180 to 0x11FC Word pin registers port 3

ext[1]

word (32 bit)

Table 260

word (32 bit)

Table 260

W96 to W127 R/W
W128 to
W159

R/W

0x1200 to 0x12FC Word pin registers port 4

ext[1]

W160 to
W191

R/W

0x1280 to 0x12FC Word pin registers port 5

ext[1]

word (32 bit)

Table 260

W192 to
W223

R/W

0x1300 to 0x137C Word pin registers port 6

ext[1]

word (32 bit)

Table 260

W224 to
W255

R/W

0x1380 to 0x13FC Word pin registers port 7

ext[1]

word (32 bit)

Table 260

DIR0

R/W

0x2000

Direction registers port 0

0

word (32 bit)

Table 261

DIR1

R/W

0x2004

Direction registers port 1

0

word (32 bit)

Table 261

DIR2

R/W

0x2008

Direction registers port 2

0

word (32 bit)

Table 261

DIR3

R/W

0x200C

Direction registers port 3

0

word (32 bit)

Table 261

DIR4

R/W

0x2010

Direction registers port 4

0

word (32 bit)

Table 261

DIR5

R/W

0x2014

Direction registers port 5

0

word (32 bit)

Table 261

DIR6

R/W

0x2018

Direction registers port 6

0

word (32 bit)

Table 261

DIR7

R/W

0x201C

Direction registers port 7

0

word (32 bit)

Table 261

MASK0

R/W

0x2080

Mask register port 0

0

word (32 bit)

Table 262

MASK1

R/W

0x2084

Mask register port 1

0

word (32 bit)

Table 262

MASK2

R/W

0x2088

Mask register port 2

0

word (32 bit)

Table 262

MASK3

R/W

0x208C

Mask register port 3

0

word (32 bit)

Table 262

MASK4

R/W

0x2090

Mask register port 4

0

word (32 bit)

Table 262

MASK5

R/W

0x2094

Mask register port 5

0

word (32 bit)

Table 262

MASK6

R/W

0x2098

Mask register port 6

0

word (32 bit)

Table 262

MASK7

R/W

0x209C

Mask register port 7

0

word (32 bit)

Table 262

Port pin register port 0

ext[1]

word (32 bit)

Table 263

PIN0

R/W

0x2100

PIN1

R/W

0x2104

Port pin register port 1

ext[1]

word (32 bit)

Table 263

PIN2

R/W

0x2108

Port pin register port 2

ext[1]

word (32 bit)

Table 263

Port pin register port 3

ext[1]

word (32 bit)

Table 263

PIN3
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Table 245. Register overview: GPIO port (base address 0x400F 4000)
The highest pin number on each port depends on package size (see Table 240).
Name

Access

Address
offset

Description

Reset
value

Width

Reference

PIN4

R/W

0x2110

Port pin register port 4

ext[1]

word (32 bit)

Table 263

PIN5

R/W

0x2114

Port pin register port 5

ext[1]

word (32 bit)

Table 263

Port pin register port 6

ext[1]

word (32 bit)

Table 263

Port pin register port 7

ext[1]

word (32 bit)

Table 263

PIN6
PIN7

R/W
R/W

0x2118
0x211C

MPIN0

R/W

0x2180

Masked port register port 0

ext[1]

word (32 bit)

Table 264

MPIN1

R/W

0x2184

Masked port register port 1

ext[1]

word (32 bit)

Table 264

Masked port register port 2

ext[1]

word (32 bit)

Table 264

Masked port register port 3

ext[1]

word (32 bit)

Table 264

MPIN2
MPIN3

R/W
R/W

0x2188
0x218C

MPIN4

R/W

0x2190

Masked port register port 4

ext[1]

word (32 bit)

Table 264

MPIN5

R/W

0x2194

Masked port register port 5

ext[1]

word (32 bit)

Table 264

Masked port register port 6

ext[1]

word (32 bit)

Table 264

word (32 bit)

Table 264

MPIN6

R/W

0x2198

MPIN7

R/W

0x219C

Masked port register port 7

ext[1]

SET0

R/W

0x2200

Write: Set register for port 0
Read: output bits for port 0

0

word (32 bit)

Table 265

SET1

R/W

0x2204

Write: Set register for port 1
Read: output bits for port 1

0

word (32 bit)

Table 265

SET2

R/W

0x2208

Write: Set register for port 2
Read: output bits for port 2

0

word (32 bit)

Table 265

SET3

R/W

0x220C

Write: Set register for port 3
Read: output bits for port 3

0

word (32 bit)

Table 265

SET4

R/W

0x2210

Write: Set register for port 4
Read: output bits for port 4

0

word (32 bit)

Table 265

SET5

R/W

0x2214

Write: Set register for port 5
Read: output bits for port 5

0

word (32 bit)

Table 265

SET6

R/W

0x2218

Write: Set register for port 6
Read: output bits for port 6

0

word (32 bit)

Table 265

SET7

R/W

0x221C

Write: Set register for port 7
Read: output bits for port 7

0

word (32 bit)

Table 265

CLR0

WO

0x2280

Clear port 0

NA

word (32 bit)

Table 266

CLR1

WO

0x2284

Clear port 1

NA

word (32 bit)

Table 266

CLR2

WO

0x2288

Clear port 2

NA

word (32 bit)

Table 266

CLR3

WO

0x228C

Clear port 3

NA

word (32 bit)

Table 266

CLR4

WO

0x2290

Clear port 4

NA

word (32 bit)

Table 266

CLR5

WO

0x2294

Clear port 5

NA

word (32 bit)

Table 266

CLR6

WO

0x2298

Clear port 6

NA

word (32 bit)

Table 266

CLR7

WO

0x229C

Clear port 7

NA

word (32 bit)

Table 266

NOT0

WO

0x2300

Toggle port 0

NA

word (32 bit)

Table 267

NOT1

WO

0x2304

Toggle port 1

NA

word (32 bit)

Table 267

NOT2

WO

0x2308

Toggle port 2

NA

word (32 bit)

Table 267

NOT3

WO

0x230C

Toggle port 3

NA

word (32 bit)

Table 267

NOT4

WO

0x2310

Toggle port 4

NA

word (32 bit)

Table 267

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Table 245. Register overview: GPIO port (base address 0x400F 4000)
The highest pin number on each port depends on package size (see Table 240).
Name

Access

Address
offset

Description

Reset
value

Width

Reference

NOT5

WO

0x2314

Toggle port 5

NA

word (32 bit)

Table 267

NOT6

WO

0x2318

Toggle port 6

NA

word (32 bit)

Table 267

NOT7

WO

0x231C

Toggle port 7

NA

word (32 bit)

Table 267

[1]

“ext” in this table and subsequent tables indicates that the data read after reset depends on the state of the pin, which in turn may
depend on an external source.

19.5.1 GPIO pin interrupts register description
19.5.1.1 Pin interrupt mode register
For each of the 8 pin interrupts selected in the PINTSELn registers (see Table 204 and
Table 205), one bit in the ISEL register determines whether the interrupt is edge or level
sensitive.
Table 246. Pin interrupt mode register (ISEL, address 0x4008 7000) bit description
Bit

Symbol Description

Reset Access
value

7:0

PMODE Selects the interrupt mode for each pin interrupt. Bit n
configures the pin interrupt selected in PINTSELn.
0 = Edge sensitive
1 = Level sensitive

0

R/W

31:8

-

-

-

Reserved.

19.5.1.2 Pin interrupt level (rising edge) interrupt enable register
For each of the 8 pin interrupts selected in the PINTSELn registers (see Table 204 and
Table 205), one bit in the IENR register enables the interrupt depending on the pin
interrupt mode configured in the ISEL register:

• If the pin interrupt mode is edge sensitive (PMODE = 0), the rising edge interrupt is
enabled.

• If the pin interrupt mode is level sensitive (PMODE = 1), the level interrupt is enabled.
The IENF register configures the active level (HIGH or LOW) for this interrupt.
Table 247. Pin interrupt level (rising edge) interrupt enable register (IENR, address 0x4008
7004) bit description

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Bit

Symbol

Description

Reset Access
value

7:0

ENRL

Enables the rising edge or level interrupt for each pin
interrupt. Bit n configures the pin interrupt selected in
PINTSELn.
0 = Disable rising edge or level interrupt.
1 = Enable rising edge or level interrupt.

0

R/W

31:8

-

Reserved.

-

-

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19.5.1.3 Pin interrupt level (rising edge) interrupt set register
For each of the 8 pin interrupts selected in the PINTSELn registers (see Table 204 and
Table 205), one bit in the SIENR register sets the corresponding bit in the IENR register
depending on the pin interrupt mode configured in the ISEL register:

• If the pin interrupt mode is edge sensitive (PMODE = 0), the rising edge interrupt is
set.

• If the pin interrupt mode is level sensitive (PMODE = 1), the level interrupt is set.
Table 248. Pin interrupt level (rising edge) interrupt set register (SIENR, address 0x4008
7008) bit description
Bit

Symbol

Description

Reset Access
value

7:0

SETENRL

Ones written to this address set bits in the IENR, thus
enabling interrupts. Bit n sets bit n in the IENR register.
0 = No operation.
1 = Enable rising edge or level interrupt.

NA

WO

31:8

-

Reserved.

-

-

19.5.1.4 Pin interrupt level (rising edge interrupt) clear register
For each of the 8 pin interrupts selected in the PINTSELn registers (see Table 204 and
Table 205), one bit in the CIENR register clears the corresponding bit in the IENR register
depending on the pin interrupt mode configured in the ISEL register:

• If the pin interrupt mode is edge sensitive (PMODE = 0), the rising edge interrupt is
cleared.

• If the pin interrupt mode is level sensitive (PMODE = 1), the level interrupt is cleared.
Table 249. Pin interrupt level (rising edge interrupt) clear register (CIENR, address 0x4008
700C) bit description
Bit

Symbol

Description

Reset Access
value

7:0

CENRL

Ones written to this address clear bits in the IENR, thus
disabling the interrupts. Bit n clears bit n in the IENR
register.
0 = No operation.
1 = Disable rising edge or level interrupt.

NA

WO

31:8

-

Reserved.

-

-

19.5.1.5 Pin interrupt active level (falling edge) interrupt enable register
For each of the 8 pin interrupts selected in the PINTSELn registers (see Table 204 and
Table 205), one bit in the IENF register enables the falling edge interrupt or the configures
the level sensitivity depending on the pin interrupt mode configured in the ISEL register:

• If the pin interrupt mode is edge sensitive (PMODE = 0), the falling edge interrupt is
enabled.

• If the pin interrupt mode is level sensitive (PMODE = 1), the active level of the level
interrupt (HIGH or LOW) is configured.

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Table 250. Pin interrupt active level (falling edge) interrupt enable register (IENF, address
0x4008 7010) bit description
Bit

Symbol Description

Reset Access
value

7:0

ENAF

Enables the falling edge or configures the active level interrupt
for each pin interrupt. Bit n configures the pin interrupt selected
in PINTSELn.
0 = Disable falling edge interrupt or set active interrupt level
LOW.
1 = Enable falling edge interrupt enabled or set active interrupt
level HIGH.

0

R/W

Reserved.

-

-

31:8 -

19.5.1.6 Pin interrupt active level (falling edge) interrupt set register
For each of the 8 pin interrupts selected in the PINTSELn registers (see Table 204 and
Table 205), one bit in the SIENF register sets the corresponding bit in the IENF register
depending on the pin interrupt mode configured in the ISEL register:

• If the pin interrupt mode is edge sensitive (PMODE = 0), the falling edge interrupt is
set.

• If the pin interrupt mode is level sensitive (PMODE = 1), the HIGH-active interrupt is
selected.
Table 251. Pin interrupt active level (falling edge interrupt) set register (SIENF, address
0x4008 7014) bit description
Bit

Symbol

Description

Reset Access
value

7:0

SETENAF Ones written to this address set bits in the IENF, thus
enabling interrupts. Bit n sets bit n in the IENF register.
0 = No operation.
1 = Select HIGH-active interrupt or enable falling edge
interrupt.

NA

WO

31:8

-

-

-

Reserved.

19.5.1.7 Pin interrupt active level (falling edge interrupt) clear register
For each of the 8 pin interrupts selected in the PINTSELn registers (see Table 204 and
Table 205), one bit in the CIENF register sets the corresponding bit in the IENF register
depending on the pin interrupt mode configured in the ISEL register:

• If the pin interrupt mode is edge sensitive (PMODE = 0), the falling edge interrupt is
cleared.

• If the pin interrupt mode is level sensitive (PMODE = 1), the LOW-active interrupt is
selected.

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Table 252. Pin interrupt active level (falling edge) interrupt clear register (CIENF, address
0x4008 7018) bit description
Bit

Symbol Description

Reset Access
value

7:0

CENAF

Ones written to this address clears bits in the IENF, thus
disabling interrupts. Bit n clears bit n in the IENF register.
0 = No operation.
1 = LOW-active interrupt selected or falling edge interrupt
disabled.

NA

WO

31:8

-

Reserved.

-

-

19.5.1.8 Pin interrupt rising edge register
This register contains ones for pin interrupts selected in the PINTSELn registers (see
Table 204 and Table 205) on which a rising edge has been detected. Writing ones to this
register clears rising edge detection. Ones in this register assert an interrupt request for
pins that are enabled for rising-edge interrupts. All edges are detected for all pins selected
by the PINTSELn registers, regardless of whether they are interrupt-enabled.
Table 253. Pin interrupt rising edge register (RISE, address 0x4008 701C) bit description
Bit

Symbol

Description

Reset Access
value

7:0

RDET

Rising edge detect. Bit n detects the rising edge of the pin
selected in PINTSELn.
Read 0: No rising edge has been detected on this pin since
Reset or the last time a one was written to this bit.
Write 0: no operation.
Read 1: a rising edge has been detected since Reset or the
last time a one was written to this bit.
Write 1: clear rising edge detection for this pin.

0

R/W

Reserved.

-

-

31:8 -

19.5.1.9 Pin interrupt falling edge register
This register contains ones for pin interrupts selected in the PINTSELn registers (see
Table 204 and Table 205) on which a falling edge has been detected. Writing ones to this
register clears falling edge detection. Ones in this register assert an interrupt request for
pins that are enabled for falling-edge interrupts. All edges are detected for all pins
selected by the PINTSELn registers, regardless of whether they are interrupt-enabled.
Table 254. Pin interrupt falling edge register (FALL, address 0x4008 7020) bit description

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Bit

Symbol Description

7:0

FDET

Falling edge detect. Bit n detects the falling edge of the pin
0
selected in PINTSELn.
Read 0: No falling edge has been detected on this pin since
Reset or the last time a one was written to this bit.
Write 0: no operation.
Read 1: a falling edge has been detected since Reset or the
last time a one was written to this bit.
Write 1: clear falling edge detection for this pin.

R/W

31:8

-

Reserved.

-

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-

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19.5.1.10 Pin interrupt status register
Reading this register returns ones for pin interrupts that are currently requesting an
interrupt. For pins identified as edge-sensitive in the Interrupt Select register, writing ones
to this register clears both rising- and falling-edge detection for the pin. For level-sensitive
pins, writing ones inverts the corresponding bit in the Active level register, thus switching
the active level on the pin.
Table 255. Pin interrupt status register (IST address 0x4008 7024) bit description
Bit

Symbol Description

Reset Access
value

7:0

PSTAT

Pin interrupt status. Bit n returns the status, clears the edge 0
interrupt, or inverts the active level of the pin selected in
PINTSELn.
Read 0: interrupt is not being requested for this interrupt pin.
Write 0: no operation.
Read 1: interrupt is being requested for this interrupt pin.
Write 1 (edge-sensitive): clear rising- and falling-edge
detection for this pin.
Write 1 (level-sensitive): switch the active level for this pin (in
the IENF register).

R/W

31:8

-

Reserved.

-

-

19.5.2 GPIO GROUP0/GROUP1 interrupt register description
19.5.2.1 Grouped interrupt control register
Table 256. GPIO grouped interrupt control register (CTRL, addresses 0x4008 8000 (GROUP0
INT) and 0x4008 9000 (GROUP1 INT)) bit description
Bit

Symbol

0

INT

1

2

31:3

Value

Reset value

Group interrupt status. This bit is cleared by writing a 0
one to it. Writing zero has no effect.
0

No interrupt request is pending.

1

Interrupt request is active.

COMB

Combine enabled inputs for group interrupt

0

0

OR functionality: A grouped interrupt is generated
when any one of the enabled inputs is active (based
on its programmed polarity).

1

AND functionality: An interrupt is generated when all
enabled bits are active (based on their programmed
polarity).

TRIG

-

Description

Group interrupt trigger
0

Edge-triggered

1

Level-triggered

-

Reserved

0

0

19.5.2.2 GPIO grouped interrupt port polarity registers
The grouped interrupt port polarity registers determine how the polarity of each enabled
pin contributes to the grouped interrupt. Each port n (n = 0 to 7) is associated with its own
port polarity register, and the values of all registers together determine the grouped
interrupt.
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Table 257. GPIO grouped interrupt port polarity registers (PORT_POL, addresses 0x4008
8020 (PORT_POL0) to 0x4008 803C (PORT_POL7) (GROUP0 INT) and 0x4008 9020
(PORT_POL0) to 0x4008 903C (PORT_POL7) (GROUP1 INT)) bit description
Bit

Symbol Description

31:0

POL

Reset Access
value

Configure pin polarity of port n pins for group interrupt. Bit m 1
corresponds to pin GPIOn[m] of port n.
0 = the pin is active LOW. If the level on this pin is LOW, the
pin contributes to the group interrupt.
1 = the pin is active HIGH. If the level on this pin is HIGH, the
pin contributes to the group interrupt.

-

19.5.2.3 GPIO grouped interrupt port enable registers
The grouped interrupt port enable registers enable the pins which contribute to the
grouped interrupt. Each port n (n = 0 to 7) is associated with its own port enable register,
and the values of all registers together determine which pins contribute to the grouped
interrupt.
Table 258. GPIO grouped interrupt port n enable registers (PORT_ENA, addresses 0x4008
8040 (PORT_ENA0) to 0x4008 805C (PORT_ENA7) (GROUP0 INT) and 0x4008 9040
(PORT_ENA0) to 0x4008 905C (PORT_ENA7) (GROUP1 INT)) bit description
Bit

Symbol Description

31:0

ENA

Reset Access
value

Enable port n pin for group interrupt. Bit m corresponds to pin 0
GPIOPn[m] of port n.
0 = the port n pin is disabled and does not contribute to the
grouped interrupt.
1 = the port n pin is enabled and contributes to the grouped
interrupt.

-

19.5.3 GPIO port register description
19.5.3.1 GPIO port byte pin registers
Each GPIO pin GPIOn[m] has a byte register in this address range. The byte pin registers
of GPIO port 0 correspond to registers B0 to B31, the byte pin registers of GPIO port 1
correspond to registers B32 to B63, etc. Byte addresses are reserved for unused GPIO
port pins (see Table 240).
Software typically reads and writes bytes to access individual pins but also can read or
write halfwords to sense or set the state of two pins, and read or write words to sense or
set the state of four pins.
Remark: To read the signal on the GPIO input, enable the input buffer in the syscon block
for the corresponding pin (see Table 191 to Table 193).

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Table 259. GPIO port byte pin registers (B, addresses 0x400F 4000 (B0) to 0x400F 00FC
(B255)) bit description
Bit

Symbol Description

0

PBYTE

7:1

Reset Access
value

Read: state of the pin GPIOn[m], regardless of direction,
ext
masking, or alternate function. Pins configured as analog I/O
always read as 0.
Write: loads the pin’s output bit.

R/W

Reserved (0 on read, ignored on write)

-

0

19.5.3.2 GPIO port word pin registers
Each GPIO pin GPIOn[m] has a word register in this address range. The word pin
registers of GPIO port 0 correspond to registers W0 to W31, the word pin registers of
GPIO port 1 correspond to registers W32 to W63, etc. Word addresses are reserved for
unused GPIO port pins (see Table 240).
Any byte, halfword, or word read in this range will be all zeros if the pin is low or all ones if
the pin is high, regardless of direction, masking, or alternate function, except that pins
configured as analog I/O always read as zeros. Any write will clear the pin’s output bit if
the value written is all zeros, else it will set the pin’s output bit.
Remark: To read the signal on the GPIO input, enable the input buffer in the syscon block
for the corresponding pin (see Table 191 to Table 193).
Table 260. GPIO port word pin registers (W, addresses 0x400F 5000 (W0) to 0x400F 13FC
(W255)) bit description
Bit

Symbol

Description

Reset Access
value

31:0

PWORD

Read 0: pin GPIOn[m] is LOW.
Write 0: clear output bit.
Read 0xFFFF FFFF: pin is HIGH.
Write any value 0x0000 0001 to 0xFFFF FFFF: set output
bit.

ext

R/W

Remark: Only 0 or 0xFFFF FFFF can be read. Writing any
value other than 0 will set the output bit.

19.5.3.3 GPIO port direction registers
Each GPIO port n (n = 0 to 7) has one direction register for configuring the port pins as
inputs or outputs.
Table 261. GPIO port direction register (DIR, addresses 0x400F 6000 (DIR0) to 0x400F 601C
(DIR7)) bit description

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Bit

Symbol

Description

Reset Access
value

31:0

DIR

Selects pin direction for pin GPIOn[m] (bit 0 = GPIOn[0], bit
1 = GPIOn[1], ..., bit 31 = GPIOn[31]).
0 = input.
1 = output.

0

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19.5.3.4 GPIO port mask registers
Each GPIO port has one mask register. The mask registers affect writing and reading the
MPORT registers. Zeroes in these registers enable reading and writing; ones disable
writing and result in zeros in corresponding positions when reading.
Table 262. GPIO port mask register (MASK, addresses 0x400F 6080 (MASK0) to 0x400F 609C
(MASK7)) bit description
Bit

Symbol

Description

Reset Access
value

31:0

MASK

Controls which bits corresponding to GPIOn[m] are active in
0
the MPORT register (bit 0 = GPIOn[0], bit 1 = GPIOn[1], ..., bit
31 = GPIOn[31]).
0 = Read MPORT: pin state; write MPORT: load output bit.
1 = Read MPORT: 0; write MPORT: output bit not affected.

R/W

19.5.3.5 GPIO port pin registers
Each GPIO port has one port pin register. Reading these registers returns the current
state of the pins read, regardless of direction, masking, or alternate functions, except that
pins configured as analog I/O always read as 0s. Writing these registers loads the output
bits of the pins written to, regardless of the Mask register.
Remark: To read the signal on the GPIO input, enable the input buffer in the syscon block
for the corresponding pin (see Table 191 to Table 193).
Table 263. GPIO port pin register (PIN, addresses 0x400F 6100 (PIN0) to 0x400F 611C (PIN7))
bit description
Bit

Symbol Description

31:0

PORT

Reset Access
value

Reads pin states or loads output bits (bit 0 = GPIOn[0], bit 1 = ext
GPIOn[1], ..., bit 31 = GPIOn[31]).
0 = Read: pin is LOW; write: clear output bit.
1 = Read: pin is HIGH; write: set output bit.

R/W

19.5.3.6 GPIO masked port pin registers
Each GPIO port has one masked port pin register. These registers are similar to the
PORT registers, except that the value read is masked by ANDing with the inverted
contents of the corresponding MASK register, and writing to one of these registers only
affects output register bits that are enabled by zeros in the corresponding MASK register.
Table 264. GPIO masked port pin register (MPIN, addresses 0x400F 6180 (MPIN0) to 0x400F
619C (MPIN7)) bit description

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Bit

Symbol

Description

Reset Access
value

31:0

MPORT

Masked port register (bit 0 = GPIOn[0], bit 1 = GPIOn[1],
..., bit 31 = GPIOn[31]).
0 = Read: pin is LOW and/or the corresponding bit in the
MASK register is 1; write: clear output bit if the
corresponding bit in the MASK register is 0.
1 = Read: pin is HIGH and the corresponding bit in the
MASK register is 0; write: set output bit if the
corresponding bit in the MASK register is 0.

ext

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19.5.3.7 GPIO port set registers
Each GPIO port has one port set register. Output bits can be set by writing ones to these
registers, regardless of MASK registers. Reading from these register returns the port’s
output bits, regardless of pin directions.
Table 265. GPIO port set register (SET, addresses 0x400F 6200 (SET0) to 0x400F 621C
(SET7)) bit description
Bit

Symbol

Description

Reset
value

Access

31:0

SET

Read or set output bits (bit 0 = GPIOn[0], bit 1 =
GPIOn[1], ..., bit 31 = GPIOn[31]).
0 = Read: output bit: write: no operation.
1 = Read: output bit; write: set output bit.

0

R/W

19.5.3.8 GPIO port clear registers
Each GPIO port has one output clear register. Output bits can be cleared by writing ones
to these write-only registers, regardless of MASK registers.
Table 266. GPIO port clear register (CLR, addresses 0x400F 6280 (CLR0) to 0x400F 629C
(CLR7)) bit description
Bit

Symbol

Description

Reset Access
value

31:0

CLR

Clear output bits (bit 0 = GPIOn[0], bit 1 = GPIOn[1],
..., bit 31 = GPIOn[31]):
0 = No operation.
1 = Clear output bit.

NA

WO

19.5.3.9 GPIO port toggle registers
Each GPIO port has one output toggle register. Output bits can be
toggled/inverted/complemented by writing ones to these write-only registers, regardless of
MASK registers.
Table 267. GPIO port toggle register (NOT, addresses 0x400F 6300 (NOT0) to 0x400F 632C
(NOT7)) bit description
Bit

Symbol Description

31:0

NOTP0

Reset Access
value

Toggle output bits (bit 0 = GPIOn[0], bit 1 = GPIOn[1], ..., bit NA
31 = GPIOn[31]):
0 = no operation.
1 = Toggle output bit.

WO

19.6 Functional description
19.6.1 Reading pin state
Software can read the state of all GPIO pins except those selected for analog input or
output in the “I/O Configuration” logic. A pin does not have to be selected for GPIO in “I/O
Configuration” in order to read its state. There are four ways to read pin state:

• The state of a single pin can be read with 7 high-order zeros from a Byte Pin register.
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• The state of a single pin can be read in all bits of a byte, halfword, or word from a
Word Pin register.

• The state of multiple pins in a port can be read as a byte, halfword, or word from a
PORT register.

• The state of a selected subset of the pins in a port can be read from a Masked Port
(MPORT) register. Pins having a 1 in the port’s Mask register will read as 0 from its
MPORT register.

19.6.2 GPIO output
Each GPIO pin has an output bit in the GPIO block. These output bits are the targets of
write operations “to the pins”. Two conditions must be met in order for a pin’s output bit to
be driven onto the pin:
1. The pin must be selected for GPIO operation in the “I/O Configuration” block, and
2. the pin must be selected for output by a 1 in its port’s DIR register.
If either or both of these conditions is (are) not met, “writing to the pin” has no effect.
There are seven ways to change GPIO output bits:

• Writing to a Byte Pin register loads the output bit from the least significant bit.
• Writing to a Word Pin register loads the output bit with the OR of all of the bits written.
(This feature follows the definition of “truth” of a multi-bit value in programming
languages.)

• Writing to a port’s PORT register loads the output bits of all the pins written to.
• Writing to a port’s MPORT register loads the output bits of pins identified by zeros in
corresponding positions of the port’s MASK register.

• Writing ones to a port’s SET register sets output bits.
• Writing ones to a port’s CLR register clears output bits.
• Writing ones to a port’s NOT register toggles/complements/inverts output bits.
The state of a port’s output bits can be read from its SET register. Reading any of the
registers described in Section 19.6.1 returns the state of pins, regardless of their direction
or alternate functions.

19.6.3 Masked I/O
A port’s MASK register defines which of its pins should be accessible in its MPORT
register. Zeroes in MASK enable the corresponding pins to be read from and written to
MPORT. Ones in MASK force a pin to read as 0 and its output bit to be unaffected by
writes to MPORT. When a port’s MASK register contains all zeros, its PORT and MPORT
registers operate identically for reading and writing.
Users of previous NXP devices with similar GPIO blocks should be aware of an
incompatibility: on the LPC43xx, writing to the SET, CLR, and NOT registers is not
affected by the MASK register. On previous devices these registers were masked.

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Applications in which interrupts can result in Masked GPIO operation, or in task switching
among tasks that do Masked GPIO operation, must treat code that uses the Mask register
as a protected/restricted region. This can be done by interrupt disabling or by using a
semaphore.
The simpler way to protect a block of code that uses a MASK register is to disable
interrupts before setting the MASK register, and re-enable them after the last operation
that uses the MPORT or MASK register.
More efficiently, software can dedicate a semaphore to the MASK registers, and
set/capture the semaphore controlling exclusive use of the MASK registers before setting
the MASK registers, and release the semaphore after the last operation that uses the
MPORT or MASK registers.

19.6.4 GPIO Interrupts
Two separate GPIO interrupt facilities are provided. With pin interrupts, up to eight GPIO
pins can each have separately-vectored, edge- or level-sensitive interrupts.
With group interrupts, any subset of the pins in each port can be selected to contribute to
a common interrupt. Any of the pin and port interrupts can be enabled in the NVIC to wake
the part from Sleep mode.

19.6.4.1 Pin interrupts
In this interrupt facility, up to 8 pins are identified as interrupt sources by the Pin Interrupt
Select registers (PINTSEL0-7). All registers in the pin interrupt block contain 8 bits,
corresponding to the pins called out by the PINTSEL0-7 registers. The ISEL register
defines whether each interrupt pin is edge- or level-sensitive. The RISE and FALL
registers detect edges on each interrupt pin, and can be written to clear (and set) edge
detection. The IST register indicates whether each interrupt pin is currently requesting an
interrupt, and this register can also be written to clear interrupts.
The other pin interrupt registers play different roles for edge-sensitive and level-sensitive
pins, as described in Table 268.
Table 268. Pin interrupt registers for edge- and level-sensitive pins
Name

Edge-sensitive function

Level-sensitive function

IENR

Enables rising-edge interrupts.

Enables level interrupts.

SIENR

Write to enable rising-edge interrupts.

Write to enable level interrupts.

CIENR

Write to disable rising-edge interrupts.

Write to disable level interrupts.

IENF

Enables falling-edge interrupts.

Selects active level.

SIENF

Write to enable falling-edge interrupts.

Write to select high-active.

CIENF

Write to disable falling-edge interrupts.

Write to select low-active.

19.6.4.2 Group interrupts
In this interrupt facility, an interrupt can be requested for each port, based on any selected
subset of pins within each port. The pins that contribute to each port interrupt are selected
by 1s in the port’s Enable register, and an interrupt polarity can be selected for each pin in
the port’s Polarity register. The level on each pin is exclusive-ORed with its polarity bit and
the result is ANDed with its enable bit, and these results are then inclusive-ORed among
all the pins in the port, to create the port’s raw interrupt request.
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The raw interrupt request from each of the two group interrupts is sent to the NVIC, which
can be programmed to treat it as level- or edge-sensitive (see Table 77).

19.6.5 Recommended practices
The following lists some recommended uses for using the GPIO port registers:

•
•
•
•

For initial setup after Reset or re-initialization, write the PORT registers.
To change the state of one pin, write a Byte Pin or Word Pin register.
To change the state of multiple pins at a time, write the SET and/or CLR registers.
To change the state of multiple pins in a tightly controlled environment like a software
state machine, consider using the NOT register. This can require less write operations
than SET and CLR.

• To read the state of one pin, read a Byte Pin or Word Pin register.
• To make a decision based on multiple pins, read and mask a PORT register.

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20.1 How to read this chapter
The SGPIO is available on all LPC43xx/LPC43Sxx parts.

20.2 Basic configuration
The SGPIO is configured as follows:

•
•
•
•

See Table 269 for clocking and power control.
The SGPIO is reset by the SGPIO_RST (reset #57).
The SGPIO interrupt is connected to interrupt slot #31 in the ARM Cortex-M4 NVIC.
SGPIO output pins SGPIO3 and SGPIO12 are connected through the GIMA to the
event recorder, the timers, and the SCT (see Table 207). SGPIO output pins SGPIO3
and SGPIO12 also support a divided-by-128 signal to the GIMA (SGPIO3_DIV and
SGPIO12_DIV).

• SGPIO output pins SGPIO10 and SGPIO12 can trigger the 12-bit ADC.
• SGPIO output pins SGPIO14 and SGPIO15 can trigger a GPDMA request (see
Section 20.7.6).
Table 269. SGPIO clocking and power control

SGPIO peripheral
clock
(SGPIO_CLOCK)

Base clock

Branch clock

Operating
frequency

BASE_PERIPH_
CLK

CLK_PERIPH_ up to
SGPIO
204 MHz

Notes
This clock is
asynchronous to the
main clock and can be
freely chosen to create
a desired SGPIO data
rate.

20.3 Features
• Each SGPIO input/output slice can be used to perform a serial to parallel or parallel to
serial data conversion.

• 16 SGPIO input/output slices each with a 32-bit FIFO can shift the input value from a
pin or an output value to a pin with every cycle of a shift clock.

•
•
•
•

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Each slice is double-buffered.
Interrupt is generated on a full FIFO, shift clock, or pattern match.
Slices can be concatenated to increase buffer size.
Each slice has a 32-bit pattern match filter.

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Chapter 20: LPC43xx/LPC43Sxx Serial GPIO (SGPIO)

20.4 General description
Serial GPIO (SGPIO) offer standard GPIO functionality enhanced with features to
accelerate serial stream processing. A data stream on a single SGPIO input or output or
on a dual, quad, and byte lane data input/output is processed by using so called slices. Up
to 16 slices are supported, and all 16 slices have the same basic feature set with some
slices offering additional features.

• Slices:
– Each slice supports a 32-bit FIFO, shifted in from a pin or out to a pin at every shift
clock.
– Some slices control the pin output enable.
– Slices are double buffered; slices are swapped with the shadow register when the
POS counter reaches 0x0.
– Slices can be concatenated to increase the buffer size. Software should ensure
that if slice n is concatenated with slice m, POS[n] and POS[m] are equal and run
in phase.
– Interrupt is raised when the POS counter reaches 0x0.
– Support for parallel to multi-stream serial conversion and vice versa. Conversion
supports interleaving; Up to 8 bits can be shifted at a time (n= 1, 2, 4 or 8 for serial,
dual-serial, quad-serial and byte parallel IO).

• Clock:
– 12-bit counter running at SGPIO_CLOCK creates a shift clock to capture input or
create output values. Note that the input frequency should be less than half of the
SGPIO_CLOCK frequency.
– External input can be used as shift clock. Active edge can be rising or falling (not
both).
– External input can be used as shift clock qualifier. Can be active LOW or HIGH.
– Internal signals can be used as shift clock qualifier.
– POS counter running at shift clock to enable double buffering.

• Input:
– Inputs are captured using the shift clock.
– Inputs can raise interrupt on input level (LOW or HIGH) or transitions (rising, falling
rising or falling). Interrupts can be masked.
– Interrupts can be raised on a matching pattern. A pattern can be up to 32 bit long
and can be masked (match value = don’t care). Four slices (A, I, H and P) support
mask functionality.
– Four inputs can be used as shift clock for other slices to capture other inputs.

• Outputs:
– Create output: active level (LOW or HIGH) or tri-state. Note if a slice is used to
create an output clock at rate fout the slice clock should at least be 2x fout. This
limits the data rate per slice to half the SGPIO_CLOCK rate.
– Output enable can be controlled by other slices. For multi-lane output, the LSB
lane output enable can be controlled independently from the MSB lines.
– Create output clock from shift clock counter.
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Chapter 20: LPC43xx/LPC43Sxx Serial GPIO (SGPIO)

– Output clock polarity can be inverted.

• Interface
– The register memory map supports use of ARM Store Multiple and Load Multiple
instructions. Slice functions that control the same features are mapped in
consecutive registers.
– The bit order is optimized for MSB first. Interfaces that require LSB first should use
a software instruction (RBIT) to reverse the bit order (not supported by the ARM
Cortex-M0).

20.4.1 SGPIO-to-AHB connection
The SGPIO is connected to the multilayer matrix via an asynchronous bridge. This allows
the SGPIO to run at a clock (CLK_PERIPH_SGPIO) independent from the matrix clock
MCLK = BASE_M4_CLK. Also see Figure 4 and Figure 13.
The bridge introduces the following access latencies:
Read latency: 4 x MCLK + 4 x CLK_PERIPH_SGPIO
Write latency: 4 x MCLK + 2 x CLK_PERIPH_SGPIO

20.4.2 Interrupts
The combined SGPIO interrupt is connected to the Cortex-M4 interrupt #31 (see Table 77)
and the Cortex-M0 NVIC #19. On parts with enabled Cortex-M0 subsystem, each SGPIO
interrupt has a separate connection to the Cortex-M0 subsystem core NVIC (see
Table 79).
Interrupts are raised on the following events:

• The input bit match interrupt is raised when the input bit is equal to the conditions set
in DATA_CAPTURE_MODE (Table 310 to Table 314).

• The pattern match interrupt is raised when the input data is equal to the masked
pattern (see Table 304 to Table 309).

• The shift clock interrupt is raised at the occurrence of a shift clock when COUNTx
equals zero (see Table 292 to Table 297). This interrupt is generated at each shift bit.

• The capture clock interrupt is raised when a slice swap occurs, that is at the
occurrence of a capture clock when POSx equals zero (see Table 298 to Table 303).
Each of the interrupts can be controlled through a set of registers in one of the following
ways:

•
•
•
•
•

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Disable or enable interrupts using registers CLR_EN/SET_EN.
Read interrupts via the register STATUS.
Read the interrupt mask via the register ENABLE.
Set interrupts via the register SET_STAT.
Clear interrupts via the register CLR_STATUS.

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20.5 Pin description
Table 270. SGPIO pin description

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Pin function

Direction

Description

SGPIO[15:0]

I/O

Serial GPIO input/output

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20.6 Register description
Table 271. Register overview: SGPIO (base address 0x4010 1000)
Name

Access

Address offset

Description

Reset
value

Reference

OUT_MUX_CFG0 to
OUT_MUX_CFG15

R/W

0x0000 to 0x003C Pin multiplexer configuration registers.

0

Table 272

SGPIO_MUX_CFG0 to R/W
SGPIO_MUX_CFG15

0x0040 to 0x007C SGPIO multiplexer configuration registers. 0

Table 275

SLICE_MUX_CFG0 to
SLICE_MUX_CFG15

R/W

0x0080 to
0x00BC

Slice multiplexer configuration registers.

0

Table 277

REG0 to REG15

R/W

0x00C0 to
0x00FC

Slice data registers. Each time COUNT0
reaches 0x0 the register shifts loading bit
31 with data captured from DIN(n).
DOUT(n) is set to REG(0)

0

Table 278

REG_SS0 to
REG_SS15

R/W

0x0100 to 0x013C Slice data shadow registers. Each time
0
POS reaches 0x0 the contents of REG_SS
is exchanged with the content of REG

Table 279

PRESET0 to
PRESET15

R/W

0x0140 to 0x17C

Reload value of COUNT0, loaded when
COUNT0 reaches 0x0

0

Table 280

COUNT0 to COUNT15 R/W

0x0180 to 0x1BC

Down counter, counts down each clock
cycle.

0

Table 281

POS0 to POS15

R/W

0x01C0 to
0x01FC

Each time COUNT0 reaches 0x0 POS
counts down.

0

Table 282

MASK_A

R/W

0x0200

Mask for pattern match function of slice A

0

Table 283

MASK_H

R/W

0x0204

Mask for pattern match function of slice H

0

Table 284

MASK_I

R/W

0x0208

Mask for pattern match function of slice I

0

Table 285

MASK_P

R/W

0x020C

Mask for pattern match function of slice P

0

Table 286

GPIO_INREG

R

0x0210

GPIO input status register

0

Table 287

GPIO_OUTREG

R/W

0x0214

GPIO output control register

0

Table 288

GPIO_OENREG

R/W

0x0218

GPIO OE control register

0

Table 289

CTRL_ENABLE

R/W

0x021C

Enables the slice COUNT counter

0

Table 290

CTRL_DISABLE

R/W

0x0220

Disables the slice POS counter

0

Table 291

CLR_EN_0

W

0x0F00

Shift clock interrupt clear mask

0

Table 292

SET_EN_0

W

0x0F04

Shift clock interrupt set mask

0

Table 293

ENABLE_0

R

0x0F08

Shift clock interrupt enable

0

Table 294

STATUS_0

R

0x0F0C

Shift clock interrupt status

0

Table 295

CLR_STATUS_0

W

0x0F10

Shift clock interrupt clear status

0

Table 296

SET_STATUS_0

W

0x0F14

Shift clock interrupt set status

0

Table 297

CLR_EN_1

W

0x0F20

Exchange clock interrupt clear mask

0

Table 298

SET_EN_1

W

0x0F24

Exchange clock interrupt set mask

0

Table 299

ENABLE_1

R

0x0F28

Exchange clock interrupt enable

0

Table 300

STATUS_1

R

0x0F2C

Exchange clock interrupt status

0

Table 301

CLR_STATUS_1

W

0x0F30

Exchange clock interrupt clear status

0

Table 302

SET_STATUS_1

W

0x0F34

Exchange clock interrupt set status

0

Table 303

CLR_EN_2

W

0x0F40

Pattern match interrupt clear mask

0

Table 304

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Chapter 20: LPC43xx/LPC43Sxx Serial GPIO (SGPIO)

Table 271. Register overview: SGPIO (base address 0x4010 1000)
Name

Access

Address offset

Description

Reset
value

Reference

SET_EN_2

W

0x0F44

Pattern match interrupt set mask

0

Table 305

ENABLE_2

R

0x0F48

Pattern match interrupt enable

0

Table 306

STATUS_2

R

0x0F4C

Pattern match interrupt status

0

Table 307

CLR_STATUS_2

W

0x0F50

Pattern match interrupt clear status

0

Table 308

SET_STATUS_2

W

0x0F54

Pattern match interrupt set status

0

Table 309

CLR_EN_3

W

0x0F60

Input interrupt clear mask

0

Table 310

SET_EN_3

W

0x0F64

Input bit match interrupt set mask

0

Table 311

ENABLE_3

R

0x0F68

Input bit match interrupt enable

0

Table 312

STATUS_3

R

0x0F6C

Input bit match interrupt status

0

Table 313

CLR_STATUS_3

W

0x0F70

Input bit match interrupt clear status

0

Table 314

SET_STATUS_3

W

0x0F74

Input bit match interrupt set status

0

Table 315

20.6.1 Pin multiplexer configuration registers
Each register controls one local output pin multiplexer: OUT_MUX_CFG0 to
OUT_MUX_CFG15 control pins SGPIO0 to SGPIO15.
Remark: Pin n in Table 273 refers to a pin on the LPC43xx configured as SGPIOn pin
through the pin configuration registers.
The P_OUT_CFG bits control the width of the data stream when data is generated by a
slice or whether the output is used as GPIO or clock. Not all modes are supported by all
slices. Table 273 shows how the SGPIOn pins are connected to slices. For example, the
8-bit wide mode is only supported by slices A/B, J/M, or L/N. When using wider than 1-bit
modes, the number of bits shifted per clock should be set equal to the width for parallel
mode (see bits PARALLEL_MODE in Table 277).
The P_OE_CFG bits control the output enable source.This can be done statically with
register GPIO_OEREG or dynamically by another slice. Table 274 indicates which slices
control the output enable of which pins. Note that for modes wider than 1 bit, the output
enable is defined by 2 bits: one bit for the LSB and one bit for the MSBs. When using
wider than 1-bit modes (P_OE_CFG = dout_oem2, dout_oem4, or dout_oem8), the
number of bits shifted per clock should be set to 2 bits per clock.
Remark: When you change the output mode (bit P_OUT_CFG), the physical pin for the
output changes as well.
Example: Slice A in 1-bit mode is routed to pin 0 (SGPIO0). Slice A in clock output mode
is routed to pin 8 (SGPIO8). See Table 273 for the output configuration for different
modes.

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Chapter 20: LPC43xx/LPC43Sxx Serial GPIO (SGPIO)

Table 272. Pin multiplexer configuration registers (OUT_MUX_CFG[0:15], addresses 0x4010
1000 (OUT_MUX_CFG0) to 0x4010 103C (OUT_MUX_CFG15)) bit description
Bit

Symbol

Value

3:0

P_OUT_CFG

31:7

Reset
value

Access

Output control of output SGPIOn. All
other values are reserved.

0

R/W

0

R/W

-

-

0x0

dout_doutm1 (1-bit mode)

0x1

dout_doutm2a (2-bit mode 2a)

0x2

dout_doutm2b (2-bit mode 2b)

0x3

dout_doutm2c (2-bit mode 2c)

0x4

gpio_out (level set by GPIO_OUTREG)

0x5

dout_doutm4a (4-bit mode 4a)

0x6

dout_doutm4b (4-bit mode 4b)

0x7

dout_doutm4c (4-bit mode 4c)

0x8

clk_out

0x9

dout_doutm8a (8-bit mode 8a)

0xA

dout_doutm8b (8-bit mode 8b)

0xB
6:4

Description

P_OE_CFG

dout_doutm8c (8-bit mode 8c)
Output enable source. All other values
are reserved.

0x0

gpio_oe (state set by GPIO_OEREG)

0x4

dout_oem1 (1-bit mode)

0x5

dout_oem2 (2-bit mode)

0x6

dout_oem4 (4-bit mode)

0x7

dout_oem8 (8-bit mode)

-

Reserved.

Table 273. Output pin multiplexing
SGPIO pin
Output mode - register OUT_MUX_CFG, bits P_OUT_CFG (see Table 272)
1011

1010

1001

0111

0110

0101

0011

0010

0001

0000

8-bit 8c 8-bit 8b 8-bit 8a 4-bit 4c 4-bit 4b 4-bit 4a 2-bit 2c 2-bit 2b 2-bit 2a 1-bit

1000

0100

clk

gpio

SGPIO0

L0

J0

A0

J0

I0

A0

J0

I0

A0

A0

Bck

A

SGPIO1

L1

J1

A1

J1

I1

A1

J1

I1

A1

I0

Dck

B

SGPIO2

L2

J2

A2

J2

I2

A2

I0

J0

E0

E0

Eck

C

SGPIO3

L3

J3

A3

J3

I3

A3

I1

J1

E1

J0

Hck

D

SGPIO4

L4

J4

A4

L0

K0

C0

L0

K0

C0

C0

Cck

E

SGPIO5

L5

J5

A5

L1

K1

C1

L1

K1

C1

K0

Fck

F

SGPIO6

L6

J6

A6

L2

K2

C2

K0

L0

F0

F0

Ock

G

SGPIO7

L7

J7

A7

L3

K3

C3

K1

L1

F1

L0

Pck

H

SGPIO8

N0

M0

B0

N0

M0

B0

N0

M0

B0

B0

Ack

I

SGPIO9

N1

M1

B1

N1

M1

B1

N1

M1

B1

M0

Mck

J

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Chapter 20: LPC43xx/LPC43Sxx Serial GPIO (SGPIO)

Table 273. Output pin multiplexing
SGPIO pin
Output mode - register OUT_MUX_CFG, bits P_OUT_CFG (see Table 272)
1011

1010

1001

0111

0110

0101

0011

0010

0001

0000

1000

0100

8-bit 8c 8-bit 8b 8-bit 8a 4-bit 4c 4-bit 4b 4-bit 4a 2-bit 2c 2-bit 2b 2-bit 2a 1-bit

clk

gpio

SGPIO10

N2

M2

B2

N2

M2

B2

M0

N0

G0

G0

Gck

K

SGPIO11

N3

M3

B3

N3

M3

B3

M1

N1

G1

N0

Nck

L

SGPIO12

N4

M4

B4

P0

O0

D0

P0

O0

D0

D0

Ick

M

SGPIO13

N5

M5

B5

P1

O1

D1

P1

O1

D1

O0

Jck

N

SGPIO14

N6

M6

B6

P2

O2

D2

O0

P0

H0

H0

Kck

O

SGPIO15

N7

M7

B7

P3

O3

D3

O1

P1

H1

P0

Lck

P

Table 274. Output enable control
SGPIO pin
OE control - register OUT_MUX_CFG, bits P_OE_CFG

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111

110

101

100

000

8-bit

4-bit

2-bit

1-bit

gpio

SGPIO0

H0

H0

H0

B0

A

SGPIO1

H1

H1

H1

M0

B

SGPIO2

H1

H1

D0

G0

C

SGPIO3

H1

H1

D1

N0

D

SGPIO4

H1

O0

G0

D0

E

SGPIO5

H1

O1

G1

O0

F

SGPIO6

H1

O1

O0

H0

G

SGPIO7

H1

O1

O1

P0

H

SGPIO8

P0

P0

P0

A0

I

SGPIO9

P1

P1

P1

I0

J

SGPIO10

P1

P1

B0

E0

K

SGPIO11

P1

P1

B1

J0

L

SGPIO12

P1

N0

N0

C0

M

SGPIO13

P1

N1

N1

K0

N

SGPIO14

P1

N1

M0

F0

O

SGPIO15

P1

N1

M1

L0

P

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Chapter 20: LPC43xx/LPC43Sxx Serial GPIO (SGPIO)

dout _doutm1
dout _doutm2

0000
00xx

GP IO_RE G

0100
01xx

dout _doutm4
clk_out

dout

1000

dout _doutm8
reserved

10xx
11xx
p_out_cfg
3:0

OUT_MUX _CFGx

5:4

6

p_oe_cfg
dout_oem1
dout_oem2

00
01

dout_oem4
dout_oem8

10
11
GP IO _OE RE G

p_oe_cfg

1
doe
0

Fig 46. SGPIO local output pin multiplexer configuration

20.6.2 SGPIO multiplexer configuration registers
Each register controls one SGPIO multiplexer to select the following sources:

• External clock source (when COUNT is not used)
• External clock qualifier (static or controlled by a slice or external pin)
• Input concatenation structure
SGPIO_MUX_CFG0 to SGPIO_MUX_CFG15 control slices A (register 0) to P (register
15).
To avoid oscillation, slices that can be a clock source for other slices cannot support
external slice clocks themselves (CLK_SOURCE_SLICE_MODE). These slices should
not feed a clock higher than SGPIO_CLOCK/2 to the other slices.

Table 275. SGPIO multiplexer configuration registers (SGPIO_MUX_CFG[0:15], addresses
0x4010 0040 (SGPIO_MUX_CFG0) to 0x4010 007C (SGPIO_MUX_CFG15)) bit
description

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Bit

Symbol

Value Description

0

EXT_CLK_ENABLE

Select clock signal.
0x0

Internal clock signal (slice)

0x1

External clock signal (pin)

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Reset
value

Access

0

R/W

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Chapter 20: LPC43xx/LPC43Sxx Serial GPIO (SGPIO)

Table 275. SGPIO multiplexer configuration registers (SGPIO_MUX_CFG[0:15], addresses
0x4010 0040 (SGPIO_MUX_CFG0) to 0x4010 007C (SGPIO_MUX_CFG15)) bit
description
…continued

Bit

Symbol

2:1

CLK_SOURCE_PIN
_MODE

4:3

6:5

8:7

10:9

11

Value Description
Select source clock pin.
0x0

QUALIFIER_
MODE

SGPIO9

0x2

SGPIO10

0x3

SGPIO11
Select clock source slice.
Note that slices D, H, O and P do not
support this mode.

0x0

Slice D

0x1

Slice H

0x2

Slice O

0x3

Slice P
Select qualifier mode.

QUALIFIER_PIN_M
ODE

QUALIFIER_
SLICE_MODE

0x0

Enable

0x1

Disable

0x2

Slice (see bits
QUALIFIER_SLICE_MODE in this
register)

0x3

External SGPIO pin (SGPIO8, SGPIO9,
SGPIO10, or SGPIO11)
Select qualifier pin.

0x0

SGPIO9

0x2

SGPIO10

0x3

SGPIO11
Select qualifier slice.

0x0

Slice A, but for slice A slice D is used.

0x1

Slice H, but for slice H slice O is used.

0x2

Slice I, but for slice I slice D is used.

0x3

Slice P, but for slice P slice O is used.
Enable concatenation.

0x0

External data pin

0x1

Concatenate data

13:12 CONCAT_ORDER

31:14 UM10503

User manual

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

-

-

SGPIO8

0x1

CONCAT_ENABLE

Access

SGPIO8

0x1

CLK_SOURCE_
SLICE_MODE

Reset
value

Select concatenation order
0x0

Self-loop

0x1

2 slices

0x2

4 slices

0x3

8 slices
Reserved

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Chapter 20: LPC43xx/LPC43Sxx Serial GPIO (SGPIO)

Table 276 defines the input slice configuration for slices A through P. The concatenation
order and the concatenation rules determine which slice becomes the input slice to slices
A through P. See Section 20.7.2 for details.
Table 276. SGPIO multiplexer
slice

Slice Din

slice

Clock
Slice Din

CONCAT_ENABLE
0

CLK_SOURCE_ SLICE_MODE
1
CONCAT_ORDER
00

01

10

11

00

01

10

11

A

Pin SGPIO0

A

I

J

L

A

D

H

O

P

I

Pin SGPIO1

I

A

A

A

I

D

H

O

P

E

Pin SGPIO2

E

J

I

I

E

D

H

O

P

J

Pin SGPIO3

J

E

E

E

J

D

H

O

P

C

Pin SGPIO4

C

K

L

J

C

D

H

O

P

K

Pin SGPIO5

K

C

C

C

K

D

H

O

P

F

Pin SGPIO6

F

L

K

K

F

D

H

O

P

L

Pin SGPIO7

L

F

F

F

L

D

H

O

P

B

Pin SGPIO8

B

M

N

P

B

D

H

O

P

M

Pin SGPIO9

M

B

B

B

M

D

H

O

P

G

Pin SGPIO10

G

N

M

M

G

D

H

O

P

N

Pin SGPIO11

N

G

G

G

N

D

H

O

P

D

Pin SGPIO12

D

O

P

N

D

-

-

-

-

O

Pin SGPIO13

O

D

D

D

O

-

-

-

-

H

Pin SGPIO14

H

P

O

O

H

-

-

-

-

P

Pin SGPIO15

P

H

H

H

P

-

-

-

-

20.6.3 Slice multiplexer configuration registers
Each register controls a slice multiplexer shift clock and how many bits of the slice FIFO
are shifted per clock.
Registers SLICE_MUX_CFG0 to SLICE_MUX_CFG15 control slices A (register 0) to P
(register 15).
Bit MATCH_MODE selects whether the match filter is active or whether data is captured.
Only slice A, H, I, and P support matching with a mask (register MASK_x). For other slices
the pattern is not masked.
Bit CLKGEN_MODE selects as shift clock the clock generated by the slice counter or by
an external pin or other slice.
Bit INV_OUT_CLK can invert the shift clock. This should only be used for external clocks
coming from a pin.
Data_capture_mode is used to define which input data condition can generate an
interrupt.

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Chapter 20: LPC43xx/LPC43Sxx Serial GPIO (SGPIO)

See Table 277 for connecting slice data to pins for the various setting of bits
PARALLEL_MODE.
Table 277. Slice multiplexer configuration registers (SLICE_MUX_CFG[0:15], addresses
0x4010 1080 (SLICE_MUX_CFG0) to 0x4010 10BC (SLICE_MUX_CFG15)) bit
description
Bit

Symbol

Value Description

0

MATCH_MODE

Reset Access
value

Match mode. Selects whether the

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

-

-

match filter is active or whether data
is captured.

1

2

CLK_CAPTURE_
MODE

0x0

Do not match data.

0x1

Match data.
Capture clock mode

0x0

Use rising clock edge.

0x1

Use falling clock edge.
Clock generation mode. Selects the

CLKGEN_MODE

clock generated by the slice counter
or by an external pin or other slice as
shift clock.

3

5:4

7:6

0x0

Use clock internally generated by
COUNTER.

0x1

Use external clock from a pin or other
slice.

0x0

Normal clock.

0x1

Inverted clock.

INV_OUT_CLK

Invert output clock

DATA_CAPTURE_
MODE

Condition for input bit match interrupt
0x0

Detect rising edge.

0x1

Detect falling edge.

0x2

Detect LOW level.

0x3

Detect HIGH level.

PARALLEL_MODE

Parallel mode
0x0

Shift 1 bit per clock.

0x1

Shift 2 bits per clock.

0x2

Shift 4 bits per clock.

0x3
8

31:9

INV_QUALIFIER

Shift 1 byte per clock.
Inversion qualifier

-

0x0

Use normal qualifier.

0x1

Use inverted qualifier.

-

Reserved.

20.6.4 Slice data registers
Each register contains the data for one slice: REG0 to REG15 contain data for slice A
(register 0) to slice P (register 15).
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Chapter 20: LPC43xx/LPC43Sxx Serial GPIO (SGPIO)

At an active shift clock data is right shifted; captured data is shifted in at bit 31, and
register data is shifted out from bit 0.
Table 278. Slice data registers (REG[0:15], addresses 0x4010 10C0 (REG0) to 0x4010 10FC
(REG15)) bit description
Bit

Symbol

Description

Reset
value

Access

31:0

REG

At each active shift clock the register shifts right;
loading REG(31) with data captured from DIN(n) and
DOUT(n) is set to REG(0).

0

R/W

20.6.5 Slice data shadow registers
Each slice data shadow register contains the data for one slice: REG_SS0 to REG_SS15
contain data for slice A (register 0) to slice P (register 15).
This register controls when the shadow register REG_SS content is exchanged with the
main register REG. The exchange occurs when the POS counter reaches 0x0.
Table 279. Slice data shadow registers (REG_SS[0:15], addresses 0x4010 1100 (REG_SS0) to
0x4010 113C (REG_SS15)) bit description
Bit

Symbol

Description

31:0

REG_SS Each time POS reaches 0x0 the contents of REG_SS
is exchanged with the content of REG.

Reset
value

Access

0

R/W

20.6.6 Reload registers
Each register contains the reload value for one slice: PRESET0 to PRESET15 contain the
reload value for slice A (register 0) to slice P (register 15).
This register controls the internally generated slice shift clock frequency:
frequency(shift_clock) = frequency(SGPIO_CLK) / (PRESET+1).
Table 280. Reload registers (PRESET[0:15], addresses 0x4010 1140 (PRESET0) to 0x4010
117C (PRESET15)) bit description
Bit

Symbol

11:0
31:12

Description

Reset
value

Access

PRESET Counter reload value; loaded when COUNT reaches
0x0.

0

R/W

-

-

-

Reserved.

20.6.7 Down counter registers
This status register reflect the slice shift clock counter value. If the counter has to start
with a defined phase then COUNT should be set to the desired value before the counter is
enabled using CTRL_ENABLE.

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Chapter 20: LPC43xx/LPC43Sxx Serial GPIO (SGPIO)

Table 281. Down counter registers (COUNT[0:15], addresses 0x4010 1180 (COUNT0) to
0x4010 11BC (COUNT15)) bit description
Bit

Symbol

Description

Reset
value

11:0

COUNT

Down counter, counts down each shift clock cycle. Next 0
count after 0x0 is PRESET.

R/W

31:12

-

Reserved.

-

-

Access

20.6.8 Position registers
Each position register contains the position counter for one slice: POS0 to POS15 contain
the counter for slice A (register 0) to slice P (register 15).
This register controls when the shadow register REG_SS content is exchanged with main
register REG.
To exchange content every k x 32 bit, POS_PRESET should be 0x20 x k -1. This setting
should be used when k slices are concatenated (CONCAT_ENABLE is set).
Remark: Before a slice is started (using CTRL_ENABLE), POS should be set to the
POS_PRESET value.
Table 282. Position registers (POS[0:15], addresses 0x4010 11C0 (POS0) to 0x4010 11FC
(POS15)) bit description
Bit

Symbol

Description

Reset
value

Access

7:0

POS

Each time COUNT reaches 0x0 POS counts
down.

0

R/W

15:8

POS_RESET

Reload value for POS after POS reaches 0x0.

0

R/W

31:16

-

Reserved.

-

-

20.6.9 Slice A mask register
Table 283. Slice A mask register (MASK_A, address 0x4010 1200) bit description
Bit

Symbol

Description

Reset
value

Access

31:0

MASK_A

Mask for pattern match function of slice A

0

R/W

0 = No effect.
1 = Mask this bit.

20.6.10 Slice H mask register
Table 284. Slice H mask register (MASK_H, address 0x4010 1204) bit description
Bit

Symbol

Description

Reset
value

Access

31:0

MASK_H

Mask for pattern match function of slice H

0

R/W

0 = No effect.
1 = Mask this bit.

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Chapter 20: LPC43xx/LPC43Sxx Serial GPIO (SGPIO)

20.6.11 Slice I mask register
Table 285. Slice I mask register (MASK_I, address 0x4010 1208) bit description
Bit

Symbol

Description

Reset
value

Access

31:0

MASK_I

Mask for pattern match function of slice I

0

R/W

0 = No effect.
1 = Mask this bit.

20.6.12 Slice P mask register
Table 286. Slice P mask register (MASK_P, address 0x4010 120C) bit description
Bit

Symbol

Description

Reset
value

Access

31:0

MASK_P

Mask for pattern match function of slice P

0

R/W

0 = No effect.
1 = Mask this bit.

20.6.13 GPIO input status register
Table 287. GPIO input status register (GPIO_INREG, address 0x4010 1210) bit description
Bit

Symbol

Description

Reset
value

Access

15:0

GPIO_INi

Bit i reflects the input state of SGPIO pin i.
0 = LOW
1 = HIGH

0

R

31:16

-

Reserved.

-

-

20.6.14 GPIO output control register
Table 288. GPIO output control register (GPIO_OUTREG, address 0x4010 1214) bit
description

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Bit

Symbol

Description

Reset
value

Access

15:0

GPIO_OUT

GPIO output register. Bit i sets the output of
SGPIO pin i.
0 = LOW
1 = HIGH

0

R/W

31:16

-

Reserved.

-

-

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Chapter 20: LPC43xx/LPC43Sxx Serial GPIO (SGPIO)

20.6.15 GPIO output enable register
Table 289. GPIO output enable register (GPIO_OENREG, address 0x4010 1218) bit
description
Bit

Symbol

Description

Reset
value

15:0

GPIO_OE

Bit i selects the output enable state of SGPIO pin 0
i.
0 = GPIO output i is tri-stated.

Access
R/W

1 = GPIO output i is active.
31:16

-

Reserved.

-

-

20.6.16 Slice count enable register
Table 290. Slice count enable register (CTRL_ENABLE, address 0x4010 121C) bit
description
Bit

Symbol

Description

15:0

CTRL_EN

Slice count enable. Bit n controls slice n (0 = slice 0
A, ..., 15 = slice P).
0 = Disables slice shift clock.
1 = Starts COUNTn or external shift clock.

R/W

Reserved.

-

31:16 -

Reset
value

-

Access

20.6.17 Slice count disable register
When this register is set, it synchronously disables the POSi counter when the POSi
counter reaches a zero count. The CTRL_DISABLED register is not cleared at that time: it
remains set.
When starting COUNTi (by setting CTRL_ENi), this register should always be cleared. If
only on POSi countdown is needed (when only one slice should be processed), then this
register should be set after COUNTi is started with register CTRL_ENi.
Table 291. Slice count disable register (CTRL_DISABLE, address 0x4010 1220) bit
description
Bit

Symbol

Description

15:0

CTRL_DIS

Slice count disable. Bit n controls slice n, (0 = 0
slice A, ..., 15 = slice P).
0 = Enables COUNT and POS counters. The
counters start counting when the CTRL_EN bit
or bits are set in the CTRL_ENABLED register.
1 = Disables POS counter of slice n.

R/W

Reserved.

-

31:16 -

Reset
value

-

Access

20.6.18 Shift clock interrupt clear mask register
This register clears the shift clock interrupt mask of a slice.

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Table 292. Shift clock interrupt clear mask register (CLR_EN_0, address 0x4010 1F00) bit
description
Bit

Symbol

Description

Reset
value

Access

15:0

CLR_SCI

1 = Shift clock interrupt clear mask of slice n.

0

W

Reserved.

-

-

31:16 -

20.6.19 Shift clock interrupt set mask register
This register masks the shift clock interrupt of a slice.
Table 293. Shift clock interrupt set mask register (SET_EN_0, address 0x4010 1F04) bit
description
Bit

Symbol

Description

Reset
value

Access

15:0

SET_SCI

1 = Shift clock interrupt set mask of slice n.

0

W

Reserved.

-

-

31:16 -

20.6.20 Shift clock interrupt enable register
This register indicates whether the shift clock interrupt of a slice is enabled.
Table 294. Shift clock interrupt enable register (ENABLE_0, address 0x4010 1F08) bit
description
Bit

Symbol

Description

Reset
value

Access

15:0

ENABLE_SCI

1 = Shift clock interrupt enable of slice n.

0

R

Reserved.

-

-

31:16 -

20.6.21 Shift clock interrupt status register
This register indicates the shift clock interrupt status of a slice.
Table 295. Shift clock interrupt status register (STATUS_0, address 0x4010 1F0C) bit
description
Bit

Symbol

Description

Reset
value

Access

15:0

STATUS_SCI

Shift clock interrupt status of slice n.

0

R

Reserved.

-

-

31:16 -

20.6.22 Shift clock interrupt clear status register
This register clears the shift clock interrupt of a slice.
Table 296. Shift clock interrupt clear status register (CLR_STATUS_0, address 0x4010 1F10)
bit description
Bit

Symbol

15:0

CLR_STATUS_SCI

31:16 -

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Description

Reset
value

Access

Shift clock interrupt clear status of slice n.

0

W

Reserved.

-

-

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20.6.23 Shift clock interrupt set status register
This register sets the shift clock interrupt of a slice.
Table 297. Shift clock interrupt set status register (SET_STATUS_0, address 0x4010 1F14) bit
description
Bit

Symbol

Description

Reset
value

Access

15:0

SET_STATUS_SCI

Shift clock interrupt set status of slice n.

0

W

Reserved.

-

-

31:16 -

20.6.24 Exchange clock interrupt clear mask register
Set the CLR_EN_1 register bit to clear the corresponding bit in the ENABLE_1 register.
Table 298. Exchange clock interrupt clear mask register (CLR_EN_1, address 0x4010 1F20)
bit description
Bit

Symbol

Description

15:0

CLR_EN_CCI

31:16 -

Reset
value

Access

1 = Exchange clock interrupt clear mask of slice n. 0

W

Reserved.

-

-

20.6.25 Exchange clock interrupt set mask register
Set the SET_EN_1 register bit to set the corresponding bit in the ENABLE1 register.
Table 299. Exchange clock interrupt set mask register (SET_EN_1, address 0x4010 1F24) bit
description
Bit

Symbol

Description

Reset
value

Access

15:0

SET_EN_CCI

1 = Exchange clock interrupt set mask of slice n.

0

W

Reserved.

-

-

31:16 -

20.6.26 Exchange clock interrupt enable
When the ENABLE_1 register bits are set to one, the interrupt monitored in corresponding
bit in the STATUS_1 register can propagate to the SGPIO interrupt. The bits in this
register can be read at any time but can only be changed by writing to the corresponding
bits in the SET_EN_1 or CLR_EN_1 registers.
Table 300. Exchange clock interrupt enable register (ENABLE_1, address 0x4010 1F28) bit
description
Bit

Symbol

Description

Reset
value

Access

15:0

ENABLE_CCI

Exchange clock interrupt enable of slice n.

0

R

Reserved.

-

-

31:16 -

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Chapter 20: LPC43xx/LPC43Sxx Serial GPIO (SGPIO)

20.6.27 Exchange clock interrupt status register
The STATUS_1 register bits are set when the shadow and data registers are exchanged.
The bits in this registers are set independently of the value of the corresponding
ENABLE_1 bits. The bits in this register can be read at any time but can only be changed
by writing to the corresponding bits in the SET_STATUS_1 or CLR_STATUS_1 registers.
Table 301. Exchange clock interrupt status register (STATUS_1, address 0x4010 1F2C) bit
description
Bit

Symbol

Description

Reset
value

Access

15:0

STATUS_CCI

Exchange clock interrupt status of slice n.

0

R

Reserved.

-

-

31:16 -

20.6.28 Exchange clock interrupt clear status register
Table 302. Exchange clock interrupt clear status register (CLR_STATUS_1, address 0x4010
1F30) bit description
Bit

Symbol

Description

15:0

CLR_STATUS_CCI

31:16 -

Reset
value

Access

Exchange clock interrupt clear status of slice n. 0

W

Reserved.

-

-

20.6.29 Exchange clock interrupt set status register
Table 303. Exchange clock interrupt set status register (SET_STATUS_1, address 0x4010
1F34) bit description
Bit

Symbol

Description

Reset
value

Access

15:0

SET_STATUS_CCI

Exchange clock interrupt set status of slice n.

0

W

Reserved.

-

-

31:16 -

20.6.30 Pattern match interrupt clear mask register
Table 304. Pattern match interrupt clear mask register (CLR_EN_2, address 0x4010 1F40) bit
description
Bit

Symbol

Description

15:0

CLR_EN2_PMI

31:16 -

Reset
value

Access

1 = Match interrupt clear mask of slice n.

0

W

Reserved.

-

-

20.6.31 Pattern match interrupt set mask register
Table 305. Pattern match interrupt set mask register (SET_EN_2, address 0x4010 1F44) bit
description
Bit

Symbol

Description

Reset
value

Access

15:0

SET_EN_PMI

1 = Match interrupt set mask of slice n.

0

W

Reserved.

-

-

31:16 -

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Chapter 20: LPC43xx/LPC43Sxx Serial GPIO (SGPIO)

20.6.32 Pattern match interrupt enable
Table 306. Pattern match interrupt enable register (ENABLE_2, address 0x4010 1F48) bit
description
Bit

Symbol

Description

Reset
value

Access

15:0

ENABLE_PMI

Match interrupt enable of slice n.

0

R

Reserved.

-

-

31:16 -

20.6.33 Pattern match interrupt status register
Table 307. Pattern match interrupt status register (STATUS_2, address 0x4010 1F4C) bit
description
Bit

Symbol

Description

Reset
value

Access

15:0

STATUS_PMI

Match interrupt status of slice n.

0

R

Reserved.

-

-

31:16 -

20.6.34 Pattern match interrupt clear status register
Table 308. Pattern match interrupt clear status register (CLR_STATUS_2, address 0x4010
1F50) bit description
Bit

Symbol

Description

15:0

CLR_STATUS_PMI Match interrupt clear status of slice n.

31:16 -

Reserved.

Reset
value

Access

0

W

-

-

20.6.35 Pattern match interrupt set status register
Table 309. Pattern match interrupt set status register (SET_STATUS_2, address 0x4010
1F54) bit description
Bit

Symbol

Description

Reset
value

Access

15:0

SET_STATUS_PMI

Match interrupt set status of slice n.

0

W

Reserved.

-

-

31:16 -

20.6.36 Input interrupt clear mask register
Table 310. Input interrupt clear mask register (CLR_EN_3, address 0x4010 1F60 bit
description
Bit

Symbol

Description

Reset
value

Access

15:0

CLR_EN_INPI

1 = Input interrupt clear mask of slice n.

0

W

Reserved.

-

-

31:16 -

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20.6.37 Input bit match interrupt set mask register
Table 311. Input interrupt set mask register (SET_EN_3, address 0x4010 1F64) bit
description
Bit

Symbol

Description

Reset
value

Access

15:0

SET_EN_INPI

1 = Input interrupt set mask of slice n.

0

W

Reserved.

-

-

31:16 -

20.6.38 Input bit match interrupt enable
Table 312. Input interrupt enable register (ENABLE_3, address 0x4010 1F68) bit description
Bit

Symbol

Description

Reset
value

Access

15:0

ENABLE3_INPI

Input interrupt enable of slice n.

0

R

Reserved.

-

-

31:16 -

20.6.39 Input bit match interrupt status register
Table 313. Input interrupt status register (STATUS_3, address 0x4010 1F6C) bit description
Bit

Symbol

Description

Reset
value

Access

15:0

STATUS_INPI

Input interrupt status of slice n.

0

R

Reserved.

-

-

31:16 -

20.6.40 Input bit match interrupt clear status register
Table 314. Input interrupt clear status register (CLR_STATUS_3, address 0x4010 1F70) bit
description
Bit

Symbol

Description

Reset
value

Access

15:0

CLR_STATUS_INPI

Input interrupt clear status of slice n.

0

W

Reserved.

-

-

31:16 -

20.6.41 Input bit match interrupt set status register
Table 315. Shift clock interrupt set status register (SET_STATUS_3, address 0x4010 1F74) bit
description
Bit

Symbol

Description

Reset
value

Access

15:0

SET_STATUS_INPI

Shift interrupt set status of slice n.

0

W

Reserved.

-

-

31:16 -

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Chapter 20: LPC43xx/LPC43Sxx Serial GPIO (SGPIO)

20.7 Functional description
Serial GPIO (SGPIO) offer standard GPIO functionality enhanced with features to
accelerate serial stream processing. The enhanced features are made using so called
slices. All 16 slices have the same basic feature set. Some slices offer additional features
for pattern matching and processing 2-, 4- or 8-bit wide streams.

Interrupt
logic
dout

din _pin
din
din _slice
qualifier _ pin
qualifier _ slice
clk_pin

S lice
m ux
16x

Do

S lice
Ev
16x

clk_
qualifier

gpio_ in
D Q

D Q

int_ input
int_ match

Q

cl

P in
m ux
DIN

int_shift
int _capt

clk_out
clk_in

clk_slice

Di

int 0_event (i)
int 1_event (i)
int 2_event (i)
int 3_event (i)

int

DOUT0
OE 0

gpio _oe

D Q

D Q

gpio_ out
D Q

P in
m ux

DOUT15
OE15

Fig 47. SGPIO block diagram

A slice performs parallel to serial data conversion (and vice versa). One slice contains 32
1-bit registers (REG) connected in a chain. Data is right shifted through the chain. Input
data is shifted in at the MSB and shifted out from the LSB.
All input data, whether used as slice-, qualifier- or clock-input, is synchronized; this
introduces a delay of one SGPIO_CLOCK cycle. This latency should be taken into
account when changing a pin direction i.e. especially when emulating a high-speed
bi-directional bus.

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Chapter 20: LPC43xx/LPC43Sxx Serial GPIO (SGPIO)

SGPIO_
CLOCK

POS_PRESET

qualifier

PRESET

external clock

TCPOS

TC

a

8b POS counter

12b COUNTer

0
-1

-1
dout

shift_clk

din

in multi-lane modes
output multiple MSBs

in multi- lane modes
input multiple LSBs

REG
31

dout from
other slices
self loop

30

.

.

1

0

TCPOS
a
concat_
order

concat_
enable

REG_SS
31

30

.

.

1

0

Fig 48. Basic operation of one slice

The shift clock controls the rate at which data is shifted through the chain. The bit shift
increment is set by register parallel_mode to be 1, 2, 4 or 8 bits. Shifts of more than 1 are
used in multi-lane modes.
The shift clock can originate from an external source (see Table 275) or be generated
locally.The shift clock can be qualified by an external pin or other slice. The local clock is
made from a 12-bit down counter COUNT running at the SGPIO_CLOCK. The count
duration can be preset with register PRESET. When COUNT reaches zero, it is loaded
with PRESET.
The shift clock frequency is therefore equal to:
frequency(shift_clock) = frequency(SGPIO_CLK) / (PRESET+1).
Each time COUNT reaches zero the register shifts right; loading bit REG[31] with data
captured from DIN and loading DOUT with bit REG[0]. Thus COUNT controls the serial
data rate. When several slices are used to create an interface port the phase between the
different slices can be controlled by using different initial COUNT value.
A second down counter (POS) controls when parallel data is loaded to and stored from
the chain. The POS counter consists of an 8-bit counter that is decremented when
COUNT equals zero. When POS reaches zero it is loaded with the PRESET_POS value.
Slice data is exchanged using a double buffering scheme. When POS reaches zero the
slice register REG content is swapped with the slice buffer REG_SS content. This gives
the CPU more time to process the REG_SS buffer content. PRESET_POS can be used to
indicate word boundaries for words that are not a multiple of 32 bit. A PRESET_POS
value of zero will cause a REG swap with REG_SS after every shift clock.

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20.7.1 Example: input for slice A
In Figure 48, the input for slice A can be selected from the following choices:

• Pin - if CONCAT_ENABLE bit = 0 in the SGPIO_MUX_CFG register (Table 275). In
1-bit mode, this is pin SGPIO0 for slice A. For multi-bit modes, use Table 316 to
determine the pin.

• Output from a slice - if CONCAT_ENABLE bit = 1 in the SGPIO_MUX_CFG register
(Table 275). The slice is set by the CONCAT_ORDER bit in Table 275 and depends
on how many slices are concatenated. Possible concatenations are shown in
Figure 49.

20.7.2 Concatenation
Slices can be concatenated to increase the buffer size beyond REG_SS. This feature also
enables creating PWM streams by implementing reverse catenation.
Concatenation is set by register SGPIO_MUX_CFG (Table 275 and Table 276). The field
CONCAT_ENABLE enables this feature. When multiple slices are concatenated, this field
should be set the same for all involved slices. Field CONCAT_ORDER sets the
concatenation size. For a size of zero, the self- loop mode, the slice output is routed back
to the slice input. This mode can be used to create a repeating data stream.
Figure 49 shows which slices can be concatenated. Slices are ordered in four groups,
starting with slice A, B, C and D. Each group consists of four concatenated slices. For
example, the slice A input can be extended with three extra slices using slice I, E and J.
Or for output mode, slice I can be extended by slice A, J, and E. Slices are furthermore
ordered in four sub-groups starting with E, F, G and H. These sub-groups support
concatenation of two slices. Slices A and B support concatenation of up to seven slices.
If multiple slices are concatenated then the concat_order for those slices should be
consistent. For the above example, input slice A should be set as input
(concat_enable=0). When concat_enable is not set, the concat_order value is a don't
care. For slices I, E and J set concat_enable=1 and use concat_order =10 (4 slices).
Concatenated slices should have consistent shift clock and bit shift settings (in
SLICE_MUX_CFG). When k slices are concatenated, PRESET_POS should be set to
0x20 x k - 1.

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Chapter 20: LPC43xx/LPC43Sxx Serial GPIO (SGPIO)

E
8
4
2
0

E
8
4
2
0

E
8
4
2
0

E
8
4
2
0

E
8
4
2
0

E
8
4
2
0

E
8
4
2
0

E
8
4
2
0

E
8
4
2
0

A
(0)

E
8
4
2
0

I
(8)

E
8
4
2
0

E
(4)

E
8
4
2
0

J
(9)

E
8
4
2
0

C
(2)

E
8
4
2
0

K
(10)

E
8
4
2
0

F
(5)

E
8
4
2
0

L
(11)

Examples:

B
(1)

M
(12)

G
(6)

N
(13)

D
(3)

O
(14)

H
(7)

P
(15)

4 input slices concatenated
2 output slices selfloop

E = external data input mode
8 = 8 slices concatenated mode
4 = 4 slices concatenated mode
2 = 2 slices concatenated mode
0 = 0 slices concatenated (self loop) mode

Fig 49. Concatenation interconnections

20.7.3 Pattern match
All slices feature pattern match functionality. This can be used for example to detect a
start code. To use this functionality, REG_SS must be programmed with the pattern to be
matched (Note that REG_SS will not be swapped with REG when POS reaches zero!).
The MATCH_MODE bit must be set to 1. The input data is now compared to the
programmed pattern. When a match is found the pattern match interrupt is raised.

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Four slices (A, H, I and P) also support masking the pattern; MASK_x must be set for the
pattern bits to be compared (1 is compare). E.g. when looking for pattern 0x1234 XXXX,
then REG should be set to 0x1234 XXXX and MASK to 0xFFFF 0000.

20.7.4 Pin multiplexing
The slice input and output are connected via a local pin multiplexer to the global pin
multiplexer (Chapter 17).
Each pin can also be controlled for normal GPIO functions (input, output, output enable)
using registers GPIO_INREG, GPIO_OUTREG and GPIO_OEREG.
Table 273 shows the output multiplexing scheme. The settings are controlled by register
OUT_MUX_CFG. Table 314 shows the input multiplexing scheme. The settings are
controlled by register SGPIO_MUX_CFG.
The 16 slices are denoted as A to P. A suffix indicates which slice bit connects to a pin,
e.g. in 8-bit parallel input mode pins SGPIO0 to 7 connect to slice A bits 24 - 31.
Not all features are available for all pins. For example only pins SGPIO8 to 11 can be
used as clock source input or as qualifier input or qualifier output. See Section 20.6.2.

20.7.5 Slice multiplexer
The slice multiplexer selects the external slice clock and slice clock qualifier. It is
configured by register SGPIO_MUX_CFG.
The clock source can be from pins SGPIO8 to SGPIO11 or from slice D, H, O or P. Note
that the slices that can be used as clock source cannot be sourced from themselves or
other slices. The external clock is synchronized with the internal SGPIO clock. To prevent
aliasing the source clock frequency should be less than half the SGPIO frequency.
The qualifier signals come from pins SGPIO8, SGPIO9, SGPIO10, or SGPIO11 or from
slice A, H, I or P. Since a slice cannot feedback a qualifier to itself some other slices are
used as well. Slice D can be qualifier for slice A and I and slice O for slice H and P.

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Chapter 20: LPC43xx/LPC43Sxx Serial GPIO (SGPIO)

c lk _s lic e D
c lk _s lic e H

00
01

c lk _s lic e O

10
11

c lk_s lic e P

00
c lk _in

4:3

qualifier _s lic e A(D)

00

qualifier_s lic e H(O)
qualifier _s lic e I(D)

01
10

qualifier_s lic e P (O)

11

c lk_pin SGPIO8
c lk_pin SGPIO9
c lk _pin SGPIO10
c lk _pin SGPIO11

0
8:7

6:5

qua lif ie r_
p in _mod e

qua lif ie r_
slice_m ode

10 :9

13 :12

11

co ncat_e nable

2:1

qua lif ie r_
mo de

s gpio_mux _c fg

concat _ord er

10
11

ext_clk_e nable

c lk_pin SGPIO10
c lk_pin SGPIO11

11

clk_ source _
slice_m ode

00
01

clk_sour ce_
pin_m ode

c lk _pin SGPIO8
c lk _pin SGPIO9

10

00

'0'
'1'

01
10

01
00

c lk_qualifier

11

11
din_s lic e_m0
din_s lic e_m1

00
01

din_s lic e_m2

10

din_s lic e_m3

11
din_pin

1
din
0

Fig 50. SGPIO_MUX_CFG slice multiplexer settings
Table 316. Slice I/O multiplexing
x = external; cl = clock; q = qualifier
SGPIO Pin
Input mode
Parallel mode

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8-bit

4-bit

2-bit

1-bit

SGPIO0

A24

A28

A30

A31

SGPIO1

A25

A29

A31

I31

SGPIO2

A26

A30

E30

E31

SGPIO3

A27

A31

E31

J31

SGPIO4

A28

C28

C30

C31

SGPIO5

A29

C29

C31

K31

SGPIO6

A30

C30

F30

F31

SGPIO7

A31

C31

F31

L31

SGPIO8

B31

B28

B30

B31

xcl

xq

SGPIO9

B30

B29

B31

M31

xcl

xq

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Chapter 20: LPC43xx/LPC43Sxx Serial GPIO (SGPIO)

Table 316. Slice I/O multiplexing
x = external; cl = clock; q = qualifier
SGPIO Pin
Input mode
Parallel mode
8-bit

4-bit

2-bit

1-bit

Clock

Q

SGPIO10

B29

B30

G30

G31

xcl

xq

SGPIO11

B28

B31

G31

N31

xcl

xq

SGPIO12

B27

D28

D30

D31

SGPIO13

B26

D29

D31

O31

SGPIO14

B25

D30

H30

H31

SGPIO15

B24

D31

H31

P31

20.7.6 Internal connections
SGPIO pins SGPIO10 and SGPIO12 can trigger the 12-bit ADC.
SGPIO pins SGPIO14 and SGPIO15 can trigger a GPDMA request. To generate the
request, program a pulse in the bit stream of slice 14 or 15. For example, use a pattern
like 0x4000 0000.
SGPIO pins SGPIO3 and SGPIO12 connect to SCT and timer capture inputs. For I2S
applications, the SGPIO3 and SGPIO12 pins also support a signal which is divided by 128
(SGPIO3_DIV and SGPIO12_DIV).
A trigger signal can be created by the associated slice (for example pin SGPIO15 is
controlled by slice P in 1-bit output mode) or by using these pins in GPIO mode.

20.8 Examples
Table 317. SGPIO applications on the LPC43xx

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Example

Description

Logic analyzer

Capture up to 16 lines as fast as possible

Pattern generator

Shift out up to 16 lines as fast as possible, data input looped back (if wanted)

PWM

Similar to pattern generator, now looped. Slices can be concatenated to
support longer patterns.
Fixed frequency changing duty cycle is also possible by setting more bits high.

SPIFI

Uses 4-bit shift mode for data. Use oe to turn around data bus direction. GPIO
for CS and one slice for clock.

I2C

Use oe path as data, tie the output data to 0.

I2S

Uses one slice per stereo channel. Use local or external clock for master or
slave mode. Bit clock and master clock run at an integer multiple of the data
clock.

SPDIF

Uses one slice per SPDIF audio interface.

TDM

Uses one slice per TDM audio interface.

UART

Use match feature to detect start bit, use qualifier if needed to capture first
data.

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Chapter 20: LPC43xx/LPC43Sxx Serial GPIO (SGPIO)

20.8.1 Multi-channel I2S
20.8.1.1 I2S slice selection
A 5.1 channel I2S output interface in master mode requires 3 data outputs (SD[2:0]), 1
word select output (WS) and 1 clock output (SCK). In slave mode SCK becomes an input.
This means that output SCK should also support clock input. This is supported by pins
SGPIO8-SGPIO10 which are mapped in serial output mode to slices B, M, G or N, let's
use slice B. These slices should therefore not be used for SD or WS signals.
If an oversampled slave clock (MCK) is needed, use a slice that is capable to create
clocks for other slices (D, H, O or P), e.g. use slice D. In slave mode MCK is an input.
MCK is divided down to create the shift clock for Data, WS and SCK. In master mode
MCK is an output.
The output audio data rate is 6 x Fs. For Fs = 192 kHz this becomes 1.152 MWps and
thus relative low for a CPU frequency of 100+ MHz. Single slices can be used (without
concatenation), for example slices A, I and E. The WS is made by slice J. This results in
the following mapping:
Table 318. SGPIO Slice mapping for I2S 5.1
Slice: function

A,I,E : SD[2:0]

J : WS

B : SCK

D : MCK

counter A

slice A

sd2

pin SGPIO0

counter I

slice I

sd1

pin SGPIO1

counter E

slice E

sd0

pin SGPIO2

counter J

slice J

ws

pin SGPIO3

slave to sck
counter B

slice B

sckin
sck

pin SGPIO8

MCK/4

slice D

slave to mck

counter D

mckin

mck

pin SGPIO12

sgpio _clk

Fig 51. 5.1 channel I2S output mapped to SGPIO slices

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Chapter 20: LPC43xx/LPC43Sxx Serial GPIO (SGPIO)

SCK

WS

MSB

SD

LSB

word n-1
right channel

word n
left channel

MSB
word n+1
right channel

Fig 52. I2S configuration

20.8.1.2 I2S slice configuration
Using FS = 192 kHz and 32-bit audio samples provides the following parameters:

• WS=FS=192 kHz
• SCK = 2 x sample_width x FS = 2 x 32 x 192 kHz = 12.288 MHz, The slice shift clock
should be twice this rate.

• MCK = oversampling_rate x SCK= 4 x SCK = 49.152 MHz.
Set the SGPIO IP clock (SGPIO_CLOCK) to 2 x MCK = 98.304 MHz.
The output width, 1-bit serial, and the output enable, statically controlled by GPIO are set
as shown in Table 319.
Table 319. SGPIO setting for I2S 5.1, OUT_MUX_CFG register
OUT_MUX_CFGi

A,I,E (i=0,8,4)

J (i=9)

B (i=1)

D (i=3)

P_out_cfg

0000:
dout_doutm1

dout_doutm1

dout_doutm1

dout_doutm1

P_oe_cfg

000: gpio_oe

gpio_oe

gpio_oe

gpio_oe

GPIO_OUTREG

1

1

1

1

In Master mode the shift clocks are generated by the local slice COUNTERs. The WS and
CK slices contain repeating patterns and are concatenated in self-loop mode.
Table 320. SGPIO setting for I2S 5.1, SGPIO_MUX_CFG register
SGPIO_MUX_CF A,I,E (i=0,8,4)
Gi

J (i=9)

B (i=1)

D (i=3)

ext_clk_enable

x

x

x

x

qualifier_mode

00: enable

00: enable

00: enable

00: enable

concat_enable

0; no

1; yes

1; yes

1; yes

concat_order

x

00; self loop

00; self loop

00; self loop

The data width is 1 bit and all slices are shifted 1 bit per clock.

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Chapter 20: LPC43xx/LPC43Sxx Serial GPIO (SGPIO)

Table 321. SGPIO setting for I2S 5.1, SLICE_MUX_CFG register
SLICE_MUX_CF
Gi

A,I,E (i=0,8,4)

J (i=9)

B (i=1)

D (i=3)

match_mode

0: no

0: no

0: no

0: no

clk_gen_mode

0: use COUNTER 0: use COUNTER 0: use COUNTER 0: use COUNTER
clk
clk
clk
clk

parallel_mode

00: 1bit per clock

00: 1bit per clock

00: 1bit per clock

00: 1bit per clock

All slice counters start at the same phase at value 0.
All data slices use for POS, the slice register length, and the audio sample width. For 32,
16, or 8-bit samples, POS is set to width-1: 0x1F, 0x0F or 0x07. For 16 (8)-bit samples
POS can also be set to 0x1F and process 2 (4) samples. Slices that self-loop should
always use the complete 32-bit size.
Table 322. SGPIO setting for I2S 5.1, slice
SLICE

A,I,E (i=0,8,4)

J (i=9)

B (i=1)

D (i=3)

PRESETi

7: f=clk/8

7: f=clk/8

3: f=clk/4

0: f=clk
0
0x1F

COUNTi

0

0

0*[1]

POS_PRESETi

0x1F/0x0F/0x07

0x1F

0x1F

[1]

A value of 1 or 2 can be used to change the SCK phase relative to Data and WS.

In I2S slave mode, an external clock input is used. There are two cases:
1. SCK master mode: SCK is supplied at pin 8, this clock falling edge is used as shift
clock for all slices. No MCK is used.
2. MCK master mode: MCK is supplied at pin 12 to slice D, where this clock is divided by
the oversampling rate (=4). The output of slice D is used as shift clock for the other
slices.
In SCK master mode, the SCK input is shift clock for the SD and WS signals. MCK is not
used. The slice settings that are different for slave mode (1) with SCK supplied at pin 8
are shown in Table 323:
Table 323. SGPIO setting for I2S 5.1 (master mode, pin 8)
OUT_MUX_CFGi

A,I,E (i=0,8,4)

J (i=9)

B (i=1)

D (i=3)

P_out_cfg

0000:
dout_doutm1

dout_doutm1

slice not used

slice not used

P_oe_cfg

000: gpio_oe

gpio_oe

slice not used

slice not used

GPIO_OUTREG

1

1

0

0

ext_clk_enable

1: pin

1: pin

slice not used

slice not used

clk_source_pin

00: pin8

00: pin8

slice not used

slice not used

qualifier_mode

00: enable

00: enable

slice not used

slice not used

clk_gen_mode

1: use external
clock

1: use external
clock

slice not used

slice not used

inv_out_clk

1: inverted clock

1: inverted clock

slice not used

slice not used

SGPIO_MUX_CFGi

SLICE_MUX_CFGi

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Chapter 20: LPC43xx/LPC43Sxx Serial GPIO (SGPIO)

Table 323. SGPIO setting for I2S 5.1 (master mode, pin 8)
PRESETi

counter not used

counter not used

counter not used

counter not
used

COUNTi

counter not used

counter not used

counter not used

counter not
used

POS_PRESETi

0x1F/0x0F/0x07

0x1F

slice not used

slice not used

In MCK master mode, the MCK input is divided down to generate the SCK and shift the
SD and WS signals. The slice setting that are different for slave mode (1) with 4x
oversampled clock MCK supplied at pin 9 are shown in :
Table 324. SGPIO setting for I2S 5.1 (master mode, pin 9)
OUT_MUX_CFGi

A,I,E (i=0,8,4)

J (i=9)

B (i=1)

D (i=3)

P_out_cfg

0000: dout_doutm1

0000: dout_doutm1

1000: clk

x

P_oe_cfg

000: gpio_oe

000: gpio_oe

000: gpio_oe

x

GPIO_OUTREG

1

1

1

0

ext_clk_enable

0: internal clock

0: internal clock

0: internal clock

1: pin

clk_source_pin

x

x

x

01: pin9

clk_source_slice

00: slice D

slice D

slice D

x

qualifier_mode

00: enable

00: enable

00: enable

00: enable

SGPIO_MUX_CFGi

SLICE_MUX_CFGi
clk_gen_mode

1: use external clock 1: use external clock 1: use external clock 1: use external clock

clk_capture_mode

1: use falling clock

1: use falling clock

not used

x

PRESETi

not used

not used

not used

3: f=MCK/4

COUNTi

not used

not used

not used

0

POS_PRESETi

0x1F/0x0F/0x07

0x1F

not used

0x1F

20.8.1.3 I2S slice programming
After configuration the data patterns are loaded in REGi and REG_SSi.
For SD the audio samples are loaded in REGi and RE_SSi. Data is shifted out starting
from the LSB. After one sample is processed POS reaches countdown and REG_SSi is
swapped with REGi to load the next sample. The CPU should update REG_SSi with a
new sample before the next POS countdown when the current sample finishes.
The WS pattern repeats every 64-bit and is stored in REG9 and REG_SS9. To create a
WS pattern as shown in Figure 51 for a 32-bit data width set REG9 = 0x0000.0001 and
REG_SS9=0xFFFF.FFFE.
The SCK pattern is static and stored in REG3 and REG_SS3. To create a SCK pattern as
shown in Figure 51 set REG1 = 0x5555.5555 and REG_SS1 = 0x5555.5555. To invert the
clock phase use patterns 0xAAAA.AAAA instead.
MCK is not phase aligned to the other I2S signals. To toggle the output set
REG3 = 0x5555.5555 and REG_SS3 = 0x5555.5555. In slave mode MCK should be
divided by 4 to create SCK and the D and WS shift clock, this requires the pattern
11001100… hence REG3 = REG_SS3=0xCCCC.CCCC
All slices are started by enabling the COUNTERs by writing CTRL_ENABLE = 0x031B.
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Chapter 20: LPC43xx/LPC43Sxx Serial GPIO (SGPIO)

20.8.2 Camera interface example
The camera interface uses the following input signals:

•
•
•
•

DIN[0:7] Data inputs
HSYNC Horizontal synchronization input
VSYNC Vertical synchronization input
PIXCLX Pixel clock input

PIXCLK
HSYNC
VSYNC
DIN

0

1

2

3

n

Fig 53. SGPIO camera interface configuration

The DIN input is captured on an 8-bit input. Wider inputs (10-bit or 12-bit) require an
additional 2- or 4-bit input. Combining the 8- and 2- (or 4-) bit data to single 10- or 12-bit
words must be done in software.
From slice A and B supporting the 8-bit input mode, select slice A. To minimize the CPU
real time load, 8 slices are concatenated: A, I, E, J, C, K, F and L.
Inputs are captured on the PIXCLK falling edge. From pins SGPIO8-SGPIO11 which can
be used as clock input, choose pin SGPIO8. HSCYNC is used as qualifier for input data.
Pins SGPIO8-SGPIO11 can be used as qualifier; pin SGPIO8 is already used, therefore
use pin SGPIO9. Pin SGPIO9 is also input for slice M. VSYNC uses one of the remaining
free slices; for example G.
Output SGPIO15 (slice P) is used, as internal signal, to request a DMA transfer after a
block of data has been transferred to local SRAM.
Table 325. SGPIO Slice mapping for camera interface
Slice: function

A,I,E,J,C,K,F,L:
DIN[7:0]

pin SGPIO9/M:
SGPIO8: HSCYNC

Pin

G: VSYNC

P:
DMA_REQ

PIXCLK

20.8.2.1 Camera interface slice configuration
All interface signals are input only. The output configuration is don’t care.
Table 326. SGPIO setting for camera interface (OUT_MUX_CFG registers)
OUT_MUX_CFGi

A...L

Pin 8

M (i=12)

G (i=6)

P_out_cfg

x

x

x

x

P_oe_cfg

x

x

x

x

GPIO_OUTREG

0

0

0

0

Data is shifted in at PIXCLK (pin 8) using HSYNC (pin 9) as qualifier.
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Chapter 20: LPC43xx/LPC43Sxx Serial GPIO (SGPIO)

Table 327. SGPIO setting for camera interface (SGPIO_MUX_CFG registers)
SGPIO_MUX_CFGi

A...L

M (i=12)

G (i=6)

ext_clk_enable

1=pin

1=pin

1=pin

clk_source_pin_mode

00=Pin 8

00=Pin 8

00=Pin 8

qualifier_mode

11: external pin

00: enable

00: enable

qualifier_pin_mode

01: Pin 9

x

x

concat_enable

1: yes

0: no

0:; no

concat_order

11: 8 slices concat

x

x

The data width is 8 bit and all data slices are shifted 8 bit per clock.
Because an external clock is used as shift clock PRESET and COUNT are not used.
HSYNC and VSYNC are falling edge detected to raise an interrupt and indicate a start of
line or frame. DIN is captured when HSYNC is low. Software should discard not needed
data lines.
Alternatively the embedded codes 0xFF.00.00.YY (line start/end, frame start/end) are
detected with slice A set to match_mode, YY contains the actual code. Note that in
match_mode the shadow buffer is not used. To use the shadow buffer match_mode
should be disabled once an embedded code has been detected.
Eight slices are concatenated giving 8 x 32/8 = 32 shifts until REG need to be shadowed,
hence POS = 0x1F.
Table 328. SGPIO setting for camera interface (SLICE_MUX_CFG registers)
SLICE_MUX_CFGi

A...L

M (i=12)

G (i=6)

match_mode

0: no

0: no

0: no

clk_capture_mode

1: falling edge

1: falling edge

1: falling edge

clkgen_mode

1: use pin clock

1: use pin clock

1: use pin clock

data_capture_mode

x

01: detect falling edge

01: detect falling edge

parallel_mode

11: 1 byte/clk

x

x

inv_qualifier

1: inverted qualifier

x

x

PRESETi

x

x

x

COUNTi

x

x

x

POS_PRESETi

0x1F

x

x

The interface is started by starting slices A, I, E, J, C, K, F, L and M by writing
CTRL_ENABLE=0x1F3F.
Data is captured at a falling PIXCLK when HSYNC is low. At a POS interrupt 32 data
words are read from REG_SS and written to the data SRAM. Then SGPIO15 is toggled to
request a GP-DMA transfer of 32 words from the data SRAM to the final destination.
When DIN per line (or frame) is not a multiple of 32 data words then software should read
at the end of a line (or frame) the POS counter to determine whether all data has been
captured in REG.

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Chapter 21: LPC43xx/LPC43Sxx General Purpose DMA
(GPDMA) controller
Rev. 2.4 — 22 August 2018

User manual

21.1 How to read this chapter
The GPDMA is available on all LPC43xx/LPC43Sxxx parts.
Remark: The ADCHS is available on parts LPC4370.
Remark: The AES DMA request lines are only available on secure parts.

21.2 Basic configuration
The GPDMA is configured as follows:

• See Table 329 for clocking and power control.
• The GPDMA is reset by the DMA_RST (reset # 19).
• The DMAMUX register in the CREG block (see Table 100) selects between up to
three peripherals for each GPDMA-to-peripheral line.

• The GPIO block, the WWDT, and the timers can be accessed by the GPDMA as
memory-to-memory transfers.
Table 329. GPDMA clocking and power control
GPDMA

Base clock

Branch clock

Operating frequency

BASE_M4_CLK

CLK_M4_DMA

204 MHz

21.3 Features
• Eight DMA channels. Each channel can support an unidirectional transfer.
• 16 DMA request lines.
• Single DMA and burst DMA request signals. Each peripheral connected to the DMA
Controller can assert either a burst DMA request or a single DMA request. The DMA
burst size is set by programming the DMA Controller.

• Memory-to-memory, memory-to-peripheral, peripheral-to-memory, and
peripheral-to-peripheral transfers are supported.

• The GPIO block, the WWDT, and the timers can be accessed by the GPDMA as
memory-to-memory transfers.

• Scatter or gather DMA is supported through the use of linked lists. This means that
the source and destination areas do not have to occupy contiguous areas of memory.

• Hardware DMA channel priority.
• AHB slave DMA programming interface. The DMA Controller is programmed by
writing to the DMA control registers over the AHB slave interface.

• Two AHB bus masters for transferring data. These interfaces transfer data when a
DMA request goes active. Master 1 can access memories and peripherals, master 0
can access memories and the SGPIO only.
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Chapter 21: LPC43xx/LPC43Sxx General Purpose DMA (GPDMA)

• 32-bit AHB master bus width.
• Incrementing or non-incrementing addressing for source and destination.
• Programmable DMA burst size. The DMA burst size can be programmed to more
efficiently transfer data.

• Internal four-word FIFO per channel.
• Supports 8, 16, and 32-bit wide transactions.
• Big-endian and little-endian support. The DMA Controller defaults to little-endian
mode on reset.

• An interrupt to the processor can be generated on a DMA completion or when a DMA
error has occurred.

• Raw interrupt status. The DMA error and DMA count raw interrupt status can be read
prior to masking.

21.4 General description
The DMA controller allows peripheral-to memory, memory-to-peripheral,
peripheral-to-peripheral, and memory-to-memory transactions. Each DMA stream
provides unidirectional serial DMA transfers for a single source and destination. For
example, a bi-directional port requires one stream for transmit and one for receives. The
source and destination areas can each be either a memory region or a peripheral for
master 1. Master 0 can only access memory (see Section 3.6) and the SGPIO.

GPDMA

AHB MATRIX

DMA
requests
DMA
responses

DMA
Interrupts

AHB SLAVE
INTERFACE

CONTROL
LOGIC AND
REGISTERS

DMA
REQUEST
AND
RESPONSE
INTERFACE

CHANNEL
LOGIC AND
REGISTERS

AHB
MASTER
INTERFACE 0

AHB MATRIX

AHB
MASTER
INTERFACE 1

AHB MATRIX

INTERRUPT
REQUEST

Fig 54. DMA controller block diagram

21.5 DMA system connections
The connection of the DMA Controller to supported peripheral devices is shown in
Table 330. The LPC43xx supports multiple muxing options for each channel to connect
peripherals to the DMA. The DMAMUX register in the CREG block controls which option
is used (see Table 100).

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Chapter 21: LPC43xx/LPC43Sxx General Purpose DMA (GPDMA)

Table 330. Peripheral connections to the DMA controller and matching flow control signals
Peripheral DMA
SREQ
Number
muxing
option
(see
Table 100)
0

1

2

3

4

5

6

7

8

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BREQ

0x0

SPIFI

SPIFI

0x1

-

SCT CTOUT_2

0x2

-

SGPIO14

0x3

-

Timer3 match 1

0x0

-

Timer0 match 0

0x1

-

USART0 transmit

0x2

Reserved

Reserved

0x3

Reserved

AES in

0x0

-

Timer0 match 1

0x1

-

USART0 receive

0x2

Reserved

Reserved

0x3

Reserved

AES out

0x0

-

Timer1 match 0

0x1

-

UART1 transmit

0x2

-

I2S1 DMA request 1

0x3

SSP1 transmit

SSP1 transmit

0x0

-

Timer1 match 1

0x1

-

UART1 receive

0x2

-

I2S1 DMA request 2

0x3

SSP1 receive

SSP1 receive

0x0

-

Timer2 match 0

0x1

-

USART2 transmit

0x2

SSP1 transmit

SSP1 transmit

0x3

-

SGPIO15

0x0

-

Timer2 match 1

0x1

-

USART2 receive

0x2

SSP1 receive

SSP1 receive

0x3

-

SGPIO14

0x0

-

Timer3 match 0

0x1

-

USART3 transmit

0x2

-

SCT DMA request 0

0x3

Reserved

ADCHS write

0x0

-

Timer3 match 1

0x1

-

USART3 receive

0x2

-

SCT DMA request 1

0x3

Reserved

ADCHS read

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Chapter 21: LPC43xx/LPC43Sxx General Purpose DMA (GPDMA)

Table 330. Peripheral connections to the DMA controller and matching flow control signals
Peripheral DMA
SREQ
Number
muxing
option
(see
Table 100)

BREQ

9

10

11

12

13

14

15

0x0

SSP0 receive

SSP0 receive

0x1

-

I2S0 DMA request 1

0x2

-

SCT DMA request 1

0x3

Reserved

Reserved

0x0

SSP0 transmit

SSP0 transmit

0x1

-

I2S0 DMA request 2

0x2

-

SCT DMA request 0

0x3

Reserved

Reserved

0x0

SSP1 receive

SSP1 receive

0x1

-

SGPIO14

0x2

-

USART0 transmit

0x3

Reserved

Reserved

0x0

SSP1 transmit

SSP1 transmit

0x1

-

SGPIO15

0x2

-

USART0 receive

0x3

Reserved

Reserved

0x0

-

ADC0

0x1

Reserved

AES in

0x2

SSP1 receive

SSP1 receive

0x3

-

USART3 receive

0x0

-

ADC1

0x1

Reserved

AES out

0x2

SSP1 transmit

SSP1 transmit

0x3

-

USART3 transmit

0x0

-

DAC

0x1

-

SCT CTOUT_3

0x2

-

SGPIO15

0x3

-

Timer3 match 0

In addition to the peripherals listed in Table 330, the GPIOs, the WWDT, and the timers
can be accessed by the GPDMA as a memory-to-memory transaction with no flow control.

21.5.1 DMA request signals
The DMA request signals are used by peripherals to request a data transfer. The DMA
request signals indicate whether a single or burst transfer of data is required and whether
the transfer is the last in the data packet. The DMA available request signals are:
BREQ[15:0] — Burst request signals. These cause a programmed burst number of data
to be transferred.
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Chapter 21: LPC43xx/LPC43Sxx General Purpose DMA (GPDMA)

SREQ[15:0] — Single transfer request signals. These cause a single data to be
transferred. The DMA controller transfers a single transfer to or from the peripheral.
LBREQ[15:0] — Last burst request signals.
LSREQ[15:0] — Last single transfer request signals.
Note that most peripherals do not support all request types.

21.5.2 DMA response signals
The DMA response signals indicate whether the transfer initiated by the DMA request
signal has completed. The response signals can also be used to indicate whether a
complete packet has been transferred. The DMA response signals from the DMA
controller are:
CLR[15:0] — DMA clear or acknowledge signals. The CLR signal is used by the DMA
controller to acknowledge a DMA request from the peripheral.
TC[15:0] — DMA terminal count signals. The TC signal can be used by the DMA
controller to indicate to the peripheral that the DMA transfer is complete.

21.6 Register description
The DMA Controller supports 8 channels. Each channel has registers specific to the
operation of that channel. Other registers controls aspects of how source peripherals
relate to the DMA Controller. There are also global DMA control and status registers.
Table 331. Register overview: GPDMA (base address 0x4000 2000)
Name

Access Address
offset

Description

Reset value

Reference

INTSTAT

RO

0x000

DMA Interrupt Status Register

0x0000 0000

Table 332

INTTCSTAT

RO

0x004

DMA Interrupt Terminal Count Request Status
Register

0x0000 0000

Table 333

INTTCCLEAR

WO

0x008

DMA Interrupt Terminal Count Request Clear
Register

-

Table 334

General registers

INTERRSTAT

RO

0x00C

DMA Interrupt Error Status Register

0x0000 0000

Table 335

INTERRCLR

WO

0x010

DMA Interrupt Error Clear Register

-

Table 336

RAWINTTCSTAT RO

0x014

DMA Raw Interrupt Terminal Count Status
Register

0x0000 0000

Table 337

RAWINTERR
STAT

RO

0x018

DMA Raw Error Interrupt Status Register

0x0000 0000

Table 338

ENBLDCHNS

RO

0x01C

DMA Enabled Channel Register

0x0000 0000

Table 339

SOFTBREQ

R/W

0x020

DMA Software Burst Request Register

0x0000 0000

Table 340

SOFTSREQ

R/W

0x024

DMA Software Single Request Register

0x0000 0000

Table 341

SOFTLBREQ

R/W

0x028

DMA Software Last Burst Request Register

0x0000 0000

Table 342

SOFTLSREQ

R/W

0x02C

DMA Software Last Single Request Register

0x0000 0000

Table 343

CONFIG

R/W

0x030

DMA Configuration Register

0x0000 0000

Table 344

SYNC

R/W

0x034

DMA Synchronization Register

0x0000 0000

Table 345

Channel 0 registers
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Chapter 21: LPC43xx/LPC43Sxx General Purpose DMA (GPDMA)

Table 331. Register overview: GPDMA (base address 0x4000 2000) …continued
Name

Access Address
offset

Description

Reset value

Reference

SRCADDR0

R/W

DMA Channel 0 Source Address Register

0x0000 0000

Table 346

0x100

DESTADDR0

R/W

0x104

DMA Channel 0 Destination Address Register

0x0000 0000

Table 347

LLI0

R/W

0x108

DMA Channel 0 Linked List Item Register

0x0000 0000

Table 348

CONTROL0

R/W

0x10C

DMA Channel 0 Control Register

0x0000 0000

Table 349

0x0000 0000

Table 350

CONFIG0

R/W

0x110

DMA Channel 0 Configuration

Register[1]

Channel 1 registers
SRCADDR1

R/W

0x120

DMA Channel 1 Source Address Register

0x0000 0000

Table 346

DESTADDR1

R/W

0x124

DMA Channel 1 Destination Address Register

0x0000 0000

Table 347

LLI1

R/W

0x128

DMA Channel 1 Linked List Item Register

0x0000 0000

Table 348

CONTROL1

R/W

0x12C

DMA Channel 1 Control Register

0x0000 0000

Table 349

CONFIG1

R/W

0x130

DMA Channel 1 Configuration Register[1]

0x0000 0000

Table 350

0x140

DMA Channel 2 Source Address Register

0x0000 0000

Table 346

Channel 2 registers
SRCADDR2

R/W

DESTADDR2

R/W

0x144

DMA Channel 2 Destination Address Register

0x0000 0000

Table 347

LLI2

R/W

0x148

DMA Channel 2 Linked List Item Register

0x0000 0000

Table 348

CONTROL2

R/W

0x14C

DMA Channel 2 Control Register

0x0000 0000

Table 349

0x0000 0000

Table 350

CONFIG2

R/W

0x150

DMA Channel 2 Configuration

Register[1]

Channel 3 registers
SRCADDR3

R/W

0x160

DMA Channel 3 Source Address Register

0x0000 0000

Table 346

DESTADDR3

R/W

0x164

DMA Channel 3 Destination Address Register

0x0000 0000

Table 347

LLI3

R/W

0x168

DMA Channel 3 Linked List Item Register

0x0000 0000

Table 348

CONTROL3

R/W

0x16C

DMA Channel 3 Control Register

0x0000 0000

Table 349

CONFIG3

R/W

0x170

DMA Channel 3 Configuration Register[1]

0x0000 0000

Table 350

0x180

DMA Channel 4 Source Address Register

0x0000 0000

Table 346

Channel 4 registers
SRCADDR4

R/W

DESTADDR4

R/W

0x184

DMA Channel 4 Destination Address Register

0x0000 0000

Table 347

LLI4

R/W

0x188

DMA Channel 4 Linked List Item Register

0x0000 0000

Table 348

CONTROL4

R/W

0x18C

DMA Channel 4 Control Register

0x0000 0000

Table 349

0x0000 0000

Table 350

CONFIG4

R/W

0x190

DMA Channel 4 Configuration

Register[1]

Channel 5 registers
SRCADDR5

R/W

0x1A0

DMA Channel 5 Source Address Register

0x0000 0000

Table 346

DESTADDR5

R/W

0x1A4

DMA Channel 5 Destination Address Register

0x0000 0000

Table 347

LLI5

R/W

0x1A8

DMA Channel 5 Linked List Item Register

0x0000 0000

Table 348

CONTROL5

R/W

0x1AC

DMA Channel 5 Control Register

0x0000 0000

Table 349

CONFIG5

R/W

0x1B0

DMA Channel 5 Configuration Register[1]

0x0000 0000

Table 350

0x1C0

DMA Channel 6 Source Address Register

0x0000 0000

Table 346

Channel 6 registers
SRCADDR6

R/W

DESTADDR6

R/W

0x1C4

DMA Channel 6 Destination Address Register

0x0000 0000

Table 347

LLI6

R/W

0x1C8

DMA Channel 6 Linked List Item Register

0x0000 0000

Table 348

CONTROL6

R/W

01CC

DMA Channel 6 Control Register

0x0000 0000

Table 349

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Chapter 21: LPC43xx/LPC43Sxx General Purpose DMA (GPDMA)

Table 331. Register overview: GPDMA (base address 0x4000 2000) …continued
Name

Access Address
offset

Description

Reset value

Reference

CONFIG6

R/W

0x1D0

DMA Channel 6 Configuration Register[1]

0x0000 0000

Table 350

Channel 7 registers
SRCADDR7

R/W

0x1E0

DMA Channel 7 Source Address Register

0x0000 0000

Table 346

DESTADDR7

R/W

0x1E4

DMA Channel 7 Destination Address Register

0x0000 0000

Table 347

LLI7

R/W

0x1E8

DMA Channel 7 Linked List Item Register

0x0000 0000

Table 348

CONTROL7

R/W

0x1EC

DMA Channel 7 Control Register

0x0000 0000

Table 349

CONFIG7

R/W

0x1F0

DMA Channel 7 Configuration Register[1]

0x0000 0000

Table 350

[1]

Bit 17 of this register is a read-only status flag.

21.6.1 DMA Interrupt Status Register
The IntStat Register is read-only and shows the status of the interrupts after masking. A
HIGH bit indicates that a specific DMA channel interrupt request is active. The request
can be generated from either the error or terminal count interrupt requests.
Table 332. DMA Interrupt Status register (INTSTAT, address 0x4000 2000) bit description
Bit

Symbol

Description

Reset
value

Access

7:0

INTSTAT

Status of DMA channel interrupts after masking. Each bit
represents one channel:

0x00

RO

-

-

0 - the corresponding channel has no active interrupt
request.
1 - the corresponding channel does have an active interrupt
request.
31:8 -

Reserved. Read undefined.

21.6.2 DMA Interrupt Terminal Count Request Status Register
The INTTCSTAT Register is read-only and indicates the status of the terminal count after
masking.
Table 333. DMA Interrupt Terminal Count Request Status Register (INTTCSTAT, address
0x4000 2004) bit description
Bit

Symbol

Description

Reset
value

Access

7:0

INTTCSTAT

Terminal count interrupt request status for DMA
channels. Each bit represents one channel:

0x00

RO

-

-

0 - the corresponding channel has no active terminal
count interrupt request.
1 - the corresponding channel does have an active
terminal count interrupt request.
31:8 -

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Reserved. Read undefined.

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Chapter 21: LPC43xx/LPC43Sxx General Purpose DMA (GPDMA)

21.6.3 DMA Interrupt Terminal Count Request Clear Register
The INTTCCLEAR Register is write-only and clears one or more terminal count interrupt
requests. When writing to this register, each data bit that is set HIGH causes the
corresponding bit in the status register (IntTCStat) to be cleared. Data bits that are LOW
have no effect.
Table 334. DMA Interrupt Terminal Count Request Clear Register (INTTCCLEAR, address
0x4000 2008) bit description
Bit

Symbol

Description

Reset
value

7:0

INTTCCLEAR Allows clearing the Terminal count interrupt request
0x00
(IntTCStat) for DMA channels. Each bit represents one
channel:

Access
WO

0 - writing 0 has no effect.
1 - clears the corresponding channel terminal count
interrupt.
31:8

-

Reserved. Read undefined. Write reserved bits as
zero.

-

-

21.6.4 DMA Interrupt Error Status Register
The INTERRSTAT Register is read-only and indicates the status of the error request after
masking.
Table 335. DMA Interrupt Error Status Register (INTERRSTAT, address 0x4000 200C) bit
description
Bit

Symbol

Description

7:0

INTERRSTAT Interrupt error status for DMA channels. Each bit
represents one channel:

Reset
value

Access

0x00

RO

-

-

0 - the corresponding channel has no active error
interrupt request.
1 - the corresponding channel does have an active
error interrupt request.
31:8

-

Reserved. Read undefined.

21.6.5 DMA Interrupt Error Clear Register
The INTERRCLR Register is write-only and clears the error interrupt requests. When
writing to this register, each data bit that is HIGH causes the corresponding bit in the
status register to be cleared. Data bits that are LOW have no effect on the corresponding
bit in the register.

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Chapter 21: LPC43xx/LPC43Sxx General Purpose DMA (GPDMA)

Table 336. DMA Interrupt Error Clear Register (INTERRCLR, address 0x4000 2010) bit
description
Bit

Symbol

Description

Reset
value

7:0

INTERRCLR

Writing a 1 clears the error interrupt request (IntErrStat) 0x00
for DMA channels. Each bit represents one channel:

Access
WO

0 - writing 0 has no effect.
1 - clears the corresponding channel error interrupt.
31:8

-

Reserved. Read undefined. Write reserved bits as zero. -

-

21.6.6 DMA Raw Interrupt Terminal Count Status Register
The RAWINTTCSTAT Register is read-only and indicates which DMA channel is
requesting a transfer complete (terminal count interrupt) prior to masking. (Note: the
IntTCStat Register contains the same information after masking.) A HIGH bit indicates
that the terminal count interrupt request is active prior to masking.
Table 337. DMA Raw Interrupt Terminal Count Status Register (RAWINTTCSTAT, address
0x4000 2014) bit description
Bit

Symbol

Description

Reset
value

7:0

RAWINTTCSTAT Status of the terminal count interrupt for DMA
0x00
channels prior to masking. Each bit represents one
channel:

Access
RO

0 - the corresponding channel has no active
terminal count interrupt request.
1 - the corresponding channel does have an active
terminal count interrupt request.
31:8

-

Reserved. Read undefined.

-

-

21.6.7 DMA Raw Error Interrupt Status Register
The RAWINTERRSTAT Register is read-only and indicates which DMA channel is
requesting an error interrupt prior to masking. (Note: the IntErrStat Register contains the
same information after masking.) A HIGH bit indicates that the error interrupt request is
active prior to masking.
Table 338. DMA Raw Error Interrupt Status Register (RAWINTERRSTAT, address 0x4000
2018) bit description
Bit

Symbol

Description

Reset
value

7:0

RAWINTERRSTAT Status of the error interrupt for DMA channels prior 0x00
to masking. Each bit represents one channel:

Access
RO

0 - the corresponding channel has no active error
interrupt request.
1 - the corresponding channel does have an active
error interrupt request.
31:8

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-

Reserved. Read undefined.

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Chapter 21: LPC43xx/LPC43Sxx General Purpose DMA (GPDMA)

21.6.8 DMA Enabled Channel Register
The ENBLDCHNS Register is read-only and indicates which DMA channels are enabled,
as indicated by the Enable bit in the CCONFIG Register. A HIGH bit indicates that a DMA
channel is enabled. A bit is cleared on completion of the DMA transfer.
Table 339. DMA Enabled Channel Register (ENBLDCHNS, address 0x4000 201C) bit
description
Bit

Symbol

Description

7:0

ENABLEDCHANNELS Enable status for DMA channels. Each bit
represents one channel:

Reset
value

Access

0x00

RO

-

-

0 - DMA channel is disabled.
1 - DMA channel is enabled.
31:8

-

Reserved. Read undefined.

21.6.9 DMA Software Burst Request Register
The SOFTBREQ Register is read/write and enables DMA burst requests to be generated
by software. A DMA request can be generated for each source by writing a 1 to the
corresponding register bit. A register bit is cleared when the transaction has completed.
Reading the register indicates which sources are requesting DMA burst transfers. A
request can be generated from either a peripheral or the software request register. Each
bit is cleared when the related transaction has completed.
Table 340. DMA Software Burst Request Register (SOFTBREQ, address 0x4000 2020) bit
description
Bit

Symbol

Description

15:0

SOFTBREQ Software burst request flags for each of 16 possible
sources. Each bit represents one DMA request line or
peripheral function (refer to Table 330 for peripheral
hardware connections to the DMA controller):

Reset Access
value
0x00

R/W

-

-

0 - writing 0 has no effect.
1 - writing 1 generates a DMA burst request for the
corresponding request line.
31:16

-

Reserved. Read undefined. Write reserved bits as zero.

Note: It is recommended that software and hardware peripheral requests are not used at
the same time.

21.6.10 DMA Software Single Request Register
The SOFTSREQ Register is read/write and enables DMA single transfer requests to be
generated by software. A DMA request can be generated for each source by writing a 1 to
the corresponding register bit. A register bit is cleared when the transaction has
completed. Reading the register indicates which sources are requesting single DMA
transfers. A request can be generated from either a peripheral or the software request
register.

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Chapter 21: LPC43xx/LPC43Sxx General Purpose DMA (GPDMA)

Table 341. DMA Software Single Request Register (SOFTSREQ, address 0x4000 2024) bit
description
Bit

Symbol

Description

15:0

SOFTSREQ Software single transfer request flags for each of 16
possible sources. Each bit represents one DMA request
line or peripheral function:

Reset Access
value
0x00

R/W

-

-

0 - writing 0 has no effect.
1 - writing 1 generates a DMA single transfer request for
the corresponding request line.
31:16

-

Reserved. Read undefined. Write reserved bits as zero.

21.6.11 DMA Software Last Burst Request Register
The SOFTLBREQ Register is read/write and enables DMA last burst requests to be
generated by software. A DMA request can be generated for each source by writing a 1 to
the corresponding register bit. A register bit is cleared when the transaction has
completed. Reading the register indicates which sources are requesting last burst DMA
transfers. A request can be generated from either a peripheral or the software request
register.
Table 342. DMA Software Last Burst Request Register (SOFTLBREQ, address 0x4000 2028)
bit description
Bit

Symbol

Description

Reset Access
value

15:0

SOFTLBREQ

Software last burst request flags for each of 16
possible sources. Each bit represents one DMA
request line or peripheral function:

0x00

R/W

-

-

0 - writing 0 has no effect.
1 - writing 1 generates a DMA last burst request for the
corresponding request line.
31:16

-

Reserved. Read undefined. Write reserved bits as
zero.

21.6.12 DMA Software Last Single Request Register
The SOFTLSREQ Register is read/write and enables DMA last single requests to be
generated by software. A DMA request can be generated for each source by writing a 1 to
the corresponding register bit. A register bit is cleared when the transaction has
completed. Reading the register indicates which sources are requesting last single DMA
transfers. A request can be generated from either a peripheral or the software request
register.

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Chapter 21: LPC43xx/LPC43Sxx General Purpose DMA (GPDMA)

Table 343. DMA Software Last Single Request Register (SOFTLSREQ, address 0x4000 202C)
bit description
Bit

Symbol

Description

Reset Access
value

15:0

SOFTLSREQ

Software last single transfer request flags for each of
16 possible sources. Each bit represents one DMA
request line or peripheral function:

0x00

R/W

-

-

0 - writing 0 has no effect.
1 - writing 1 generates a DMA last single transfer
request for the corresponding request line.
31:16

-

Reserved. Read undefined. Write reserved bits as
zero.

21.6.13 DMA Configuration Register
The CONFIG Register is read/write and configures the operation of the DMA Controller.
The endianness of the AHB master interface can be altered by writing to the M bit of this
register. The AHB master interface is set to little-endian mode on reset.
Table 344. DMA Configuration Register (CONFIG, address 0x4000 2030) bit description
Bit

Symbol Value

Description

Reset Access
value

0

E

DMA Controller enable:

0x00

R/W

0x00

R/W

0x00

R/W

1

2

0

Disabled (default). Disabling the DMA Controller
reduces power consumption.

1

Enabled

M0

AHB Master 0 endianness configuration:
0

Little-endian mode (default).

1

Big-endian mode.

M1

31:3 -

AHB Master 1 endianness configuration:
0

Little-endian mode (default).

1

Big-endian mode.
Reserved. Read undefined. Write reserved bits as
zero.

21.6.14 DMA Synchronization Register
The Sync Register is read/write and enables or disables synchronization logic for the
DMA request signals. The DMA request signals consist of the BREQ[15:0], SREQ[15:0],
LBREQ[15:0], and LSREQ[15:0]. A bit set to 0 enables the synchronization logic for a
particular group of DMA requests. A bit set to 1 disables the synchronization logic for a
particular group of DMA requests. This register is reset to 0 enabling the synchronization
logic by default.

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Chapter 21: LPC43xx/LPC43Sxx General Purpose DMA (GPDMA)

Table 345. DMA Synchronization Register (SYNC, address 0x4000 2034) bit description
Bit

Symbol

Description

Reset Access
value

15:0

DMACSYNC Controls the synchronization logic for DMA request
signals. Each bit represents one set of DMA request
lines as described in the preceding text:

0x00

R/W

-

-

0 - synchronization logic for the corresponding DMA
request signals are enabled.
1 - synchronization logic for the corresponding
request line signals are disabled.
31:16

-

Reserved. Read undefined. Write reserved bits as
zero.

21.6.15 DMA Channel registers
The channel registers are used to program the eight DMA channels. These registers
consist of:

•
•
•
•
•

Eight SRCADDR Registers.
Eight DESTADDR Registers.
Eight LLI Registers.
Eight CONTROL Registers.
Eight CONFIG Registers.

When performing scatter/gather DMA, the first four of these are automatically updated.

21.6.16 DMA Channel Source Address Registers
The eight read/write SRCADDR Registers contain the current source address
(byte-aligned) of the data to be transferred. Each register is programmed directly by
software before the appropriate channel is enabled. When the DMA channel is enabled
this register is updated:

• As the source address is incremented.
• By following the linked list when a complete packet of data has been transferred.
Reading the register when the channel is active does not provide useful information. This
is because by the time software has processed the value read, the address may have
progressed. It is intended to be read only when the channel has stopped, in which case it
shows the source address of the last item read.
Note: The source and destination addresses must be aligned to the source and
destination widths.
Table 346. DMA Channel Source Address Registers (SRCADDR[0:7], 0x4000 2100
(SRCADDR0) to 0x4000 21E0 (SRCADDR7)) bit description

UM10503

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Bit

Symbol

Description

Reset value

31:0

SRCADDR

DMA source address. Reading this register will
return the current source address.

0x0000 0000 R/W

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Chapter 21: LPC43xx/LPC43Sxx General Purpose DMA (GPDMA)

21.6.17 DMA Channel Destination Address registers
The eight read/write DESTADDR Registers contain the current destination address
(byte-aligned) of the data to be transferred. Each register is programmed directly by
software before the channel is enabled. When the DMA channel is enabled the register is
updated as the destination address is incremented and by following the linked list when a
complete packet of data has been transferred. Reading the register when the channel is
active does not provide useful information. This is because by the time that software has
processed the value read, the address may have progressed. It is intended to be read
only when a channel has stopped, in which case it shows the destination address of the
last item read.
Table 347. DMA Channel Destination Address registers (DESTADDR[0:7], 0x4000 2104
(DESTADDR0) to 0x4000 21E4 (DESTADDR7)) bit description
Bit

Symbol

Description

Reset value

Access

31:0

DESTADDR

DMA Destination address. Reading this
register will return the current destination
address.

0x0000 0000 R/W

21.6.18 DMA Channel Linked List Item registers
The eight read/write LLI Registers contain a word-aligned address of the next Linked List
Item (LLI). If the LLI is 0, then the current LLI is the last in the chain, and the DMA channel
is disabled when all DMA transfers associated with it are completed. Programming this
register when the DMA channel is enabled may have unpredictable side effects.
Table 348. DMA Channel Linked List Item registers (LLI[0:7], 0x4000 2108 (LLI0) to 0x4000
21E8 (LLI7)) bit description
Bit

Symbol

0

LM

Value

0
1

Description

Reset
value

Access

AHB master select for loading the next LLI:

0

R/W

R/W

AHB Master 0.
AHB Master 1.

1

R

Reserved, and must be written as 0, masked on
read.

0

31:2

LLI

Linked list item. Bits [31:2] of the address for the
next LLI. Address bits [1:0] are 0.

0x0000 R/W
0000

21.6.19 DMA channel control registers
The eight read/write CONTROL Registers contain DMA channel control information such
as the transfer size, burst size, and transfer width. Each register is programmed directly
by software before the DMA channel is enabled. When the channel is enabled the register
is updated by following the linked list when a complete packet of data has been
transferred. Reading the register while the channel is active does not give useful
information. This is because by the time software has processed the value read, the
channel may have advanced. It is intended to be read only when a channel has stopped.

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Chapter 21: LPC43xx/LPC43Sxx General Purpose DMA (GPDMA)

Table 349. DMA Channel Control registers (CONTROL[0:7], 0x4000 210C (CONTROL0) to 0x4000 21EC (CONTROL7))
bit description
Bit

Symbol

11:0

TRANSFERSIZE

Value Description

Reset
value

Transfer size in number of transfers. A write to this field sets the 0x0
size of the transfer when the DMA Controller is the flow
controller. The transfer size value must be set before the
channel is enabled. Transfer size is updated as data transfers
are completed.

Access
R/W

A read from this field indicates the number of transfers
completed on the destination bus. Reading the register when
the channel is active does not give useful information because
by the time that the software has processed the value read, the
channel might have progressed. It is intended to be used only
when a channel is enabled and then disabled.
The transfer size value is not used if the DMA Controller is not
the flow controller.
14:12

17:15

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SBSIZE

Source burst size. Indicates the number of transfers that make 0x0
up a source burst. This value must be set to the burst size of the
source peripheral, or if the source is memory, to the memory
boundary size (see Figure 8). The burst size is the amount of
data that is transferred when the BREQ signal goes active in the
source peripheral.
0x0

Source burst size = 1

0x1

Source burst size = 4

0x2

Source burst size = 8

0x3

Source burst size = 16

0x4

Source burst size = 32

0x5

Source burst size = 64

0x6

Source burst size = 128

0x7

Source burst size = 256

DBSIZE

Destination burst size. Indicates the number of transfers that
0x0
make up a destination burst transfer request. This value must
be set to the burst size of the destination peripheral or, if the
destination is memory, to the memory boundary size. The burst
size is the amount of data that is transferred when the BREQ
signal goes active in the destination peripheral.
0x0

Destination burst size = 1

0x1

Destination burst size = 4

0x2

Destination burst size = 8

0x3

Destination burst size = 16

0x4

Destination burst size = 32

0x5

Destination burst size = 64

0x6

Destination burst size = 128

0x7

Destination burst size = 256

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Chapter 21: LPC43xx/LPC43Sxx General Purpose DMA (GPDMA)

Table 349. DMA Channel Control registers (CONTROL[0:7], 0x4000 210C (CONTROL0) to 0x4000 21EC (CONTROL7))
bit description …continued
Bit

Symbol

20:18

SWIDTH

23:21

24

Value Description

Source transfer width. Transfers wider than the AHB master bus 0x0
width are illegal. The source and destination widths can be
different from each other. The hardware automatically packs
and unpacks the data as required. 0x3 to 0x7 - Reserved.
0x0

Byte (8-bit)

0x1

Halfword (16-bit)

0x2

Word (32-bit)

DWIDTH

Destination transfer width. Transfers wider than the AHB master 0x0
bus width are not supported. The source and destination widths
can be different from each other. The hardware automatically
packs and unpacks the data as required. 0x3 to 0x7 - Reserved.
0x0

Byte (8-bit)

0x1

Halfword (16-bit)

0x2

Word (32-bit)

S

Source AHB master select:
0
1

25

Reset
value

D

Access
R/W

R/W

0

R/W

0

R/W

0

R/W

0

R/W

This information is provided to the peripheral during a DMA bus 0
access and indicates that the access is in user mode or
privileged mode.

R/W

AHB Master 0 selected for source transfer.
AHB Master 1 selected for source transfer.
Destination AHB master select:
Remark: Only Master1 can access a peripheral. Master0 can
only access memory.

26

27

28

29

30

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0

AHB Master 0 selected for destination transfer.

1

AHB Master 1 selected for destination transfer.

SI

Source increment:
0

The source address is not incremented after each transfer.

1

The source address is incremented after each transfer.

DI

Destination increment:
0

The destination address is not incremented after each transfer.

1

The destination address is incremented after each transfer.

PROT1

0

User mode

1

Privileged mode

PROT2

This information is provided to the peripheral during a DMA bus 0
access and indicates to the peripheral that the access is
bufferable or not bufferable.
0

Not bufferable

1

Bufferable

PROT3

This information is provided to the peripheral during a DMA bus 0
access and indicates to the peripheral that the access is
cacheable or not cacheable.
0

Not cacheable

1

Cacheable
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Chapter 21: LPC43xx/LPC43Sxx General Purpose DMA (GPDMA)

Table 349. DMA Channel Control registers (CONTROL[0:7], 0x4000 210C (CONTROL0) to 0x4000 21EC (CONTROL7))
bit description …continued
Bit

Symbol

31

I

Value Description
Terminal count interrupt enable bit.
0

The terminal count interrupt is disabled.

1

The terminal count interrupt is enabled.

Reset
value

Access

0

R/W

21.6.19.1 Protection and access information
AHB access information is provided to the source and/or destination peripherals when a
transfer occurs. The transfer information is provided by programming the DMA channel
(the PROT bits of the CONTROL Register, and the LOCK bit of the CONFIG Register).
These bits are programmed by software and can be used by peripherals.

21.6.20 Channel Configuration registers
The eight CONFIG Registers are read/write with the exception of bit[17] which is
read-only. Used these to configure the DMA channel. The registers are not updated when
a new LLI is requested.
Table 350. DMA Channel Configuration registers (CONFIG[0:7], 0x4000 2110 (CONFIG0) to 0x4000 21F0 (CONFIG7))
bit description
Bit

Symbol

0

E

Value

Description

Reset
value

Channel enable. Reading this bit indicates whether a channel is 0
currently enabled or disabled:

Access
R/W

The Channel Enable bit status can also be found by reading the
ENBLDCHNS Register.
A channel can be disabled by clearing the Enable bit. This
causes the current AHB transfer (if one is in progress) to
complete and the channel is then disabled. Any data in the FIFO
of the relevant channel is lost. Restarting the channel by setting
the Channel Enable bit has unpredictable effects, the channel
must be fully re-initialized.
The channel is also disabled, and Channel Enable bit cleared,
when the last LLI is reached, the DMA transfer is completed, or
if a channel error is encountered.
If a channel must be disabled without losing data in the FIFO,
the Halt bit must be set so that further DMA requests are
ignored. The Active bit must then be polled until it reaches 0,
indicating that there is no data left in the FIFO. Finally, the
Channel Enable bit can be cleared.
Remark: The GPDMA pre-loads the data from the source
memory as soon as the channel is enabled. The data
pre-loading occurs independently of receiving a DMA transfer
request.

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0

Channel disabled.

1

Channel enabled.

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Chapter 21: LPC43xx/LPC43Sxx General Purpose DMA (GPDMA)

Table 350. DMA Channel Configuration registers (CONFIG[0:7], 0x4000 2110 (CONFIG0) to 0x4000 21F0 (CONFIG7))
bit description …continued
Bit

Symbol

5:1

SRCPERIPHERAL

Value

Source peripheral. This value selects the DMA source request
peripheral. This field is ignored if the source of the transfer is
from memory. See Table 330 for details.
0x0

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Description

Reset
value

Access
R/W

SPIFI/SCT match 2/SGPIO14/Timer3 match 1

0x1

Timer0 match 0/USART0 transmit/AES in

0x2

Timer0 match 1/USART0 receive/AES out

0x3

Timer1 match 0/UART1 transmit/I2S1 DMA request 1/SSP1
transmit

0x4

Timer1 match 1/UART1 receive/I2S1 DMA request 2/SSP1
receive

0x5

Timer2 match 0/USART2 transmit/SSP1 transmit/SGPIO15

0x6

Timer2 match 1/USART2 receive/SSP1 receive/SGPIO14

0x7

Timer3 match 0/UART3 transmit/SCT DMA request 0/ADCHS
write

0x8

Timer3 match 1/UART3 receive/SCT DMA request 1/ADCHS
read

0x9

SSP0 receive/I2S0 DMA request 1/SCT DMA request 1

0xA

SSP0 transmit/I2S0 DMA request 2/SCT DMA request 0

0xB

SSP1 receive/SGPIO14/USART0 transmit

0xC

SSP1 transmit/SGPIO15/USART0 receive

0xD

ADC0/AES in/SSP1 receive/USART3 receive

0xE

ADC1/AES out/SSP1 transmit/USART3 transmit

0xF

DAC/SCT match 3/SGPIO15/Timer3 match 0

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Chapter 21: LPC43xx/LPC43Sxx General Purpose DMA (GPDMA)

Table 350. DMA Channel Configuration registers (CONFIG[0:7], 0x4000 2110 (CONFIG0) to 0x4000 21F0 (CONFIG7))
bit description …continued
Bit

Symbol

10:6

DESTPERIPHERAL

Value

Description
Destination peripheral. This value selects the DMA destination
request peripheral. This field is ignored if the destination of the
transfer is to memory. See Table 330 for details.

0x0

Access
R/W

SPIFI/SCT match 2/SGPIO14/Timer3 match 1

0x1

Timer0 match 0/USART0 transmit/AES in

0x2

Timer0 match 1/USART0 receive/AES out

0x3

Timer1 match 0/UART1 transmit/I2S1 DMA request 1/SSP1
transmit

0x4

Timer1 match 1/UART1 receive/I2S1 DMA request 2/SSP1
receive

0x5

Timer2 match 0/USART2 transmit/SSP1 transmit/SGPIO15

0x6

Timer2 match 1/USART2 receive/SSP1 receive/SGPIO14

0x7

Timer3 match 0/UART3 transmit/SCT DMA request 0/ADCHS
write

0x8

Timer3 match 1/UART3 receive/SCT DMA request 1/ADCHS
read

0x9

SSP0 receive/I2S0 DMA request 1/SCT DMA request 1

0xA

SSP0 transmit/I2S0 DMA request 2/SCT DMA request 0

0xB

SSP1 receive/SGPIO14/USART0 transmit

0xC

SSP1 transmit/SGPIO15/USART0 receive

0xD

ADC0/AES in/SSP1 receive/USART3 receive

0xE

ADC1/AES out/SSP1 transmit/USART3 transmit

0xF

DAC/SCT match 3/SGPIO15/Timer3 match 0

13:11 FLOWCNTRL

Reset
value

Flow control and transfer type. This value indicates the flow
controller and transfer type. The flow controller can be the DMA
Controller, the source peripheral, or the destination peripheral.

R/W

The transfer type can be memory-to-memory,
memory-to-peripheral, peripheral-to-memory, or
peripheral-to-peripheral.
Refer to Table 351 for the encoding of this field.
0x0

Memory to memory (DMA control)

0x1

Memory to peripheral (DMA control)

0x2

Peripheral to memory (DMA control)

0x3

Source peripheral to destination peripheral (DMA control)

0x4

Source peripheral to destination peripheral (destination control)

0x5

Memory to peripheral (peripheral control)

0x6

Peripheral to memory (peripheral control)

0x7

Source peripheral to destination peripheral (source control)

14

IE

Interrupt error mask. When cleared, this bit masks out the error
interrupt of the relevant channel.

R/W

15

ITC

Terminal count interrupt mask. When cleared, this bit masks out
the terminal count interrupt of the relevant channel.

R/W

16

L

Lock. When set, this bit enables locked transfers.

R/W

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Chapter 21: LPC43xx/LPC43Sxx General Purpose DMA (GPDMA)

Table 350. DMA Channel Configuration registers (CONFIG[0:7], 0x4000 2110 (CONFIG0) to 0x4000 21F0 (CONFIG7))
bit description …continued
Bit

Symbol

17

A

Value

Description

Reset
value

Access
RO

Active:
0 = there is no data in the FIFO of the channel.
1 = the channel FIFO has data.
This value can be used with the Halt and Channel Enable bits to
cleanly disable a DMA channel. This is a read-only bit.

18

H

R/W

Halt:
0 = enable DMA requests.
1 = ignore further source DMA requests.
The contents of the channel FIFO are drained.
This value can be used with the Active and Channel Enable bits
to cleanly disable a DMA channel.
0

Enable DMA requests.

1

Ignore further source DMA requests.

31:19 -

Reserved, do not modify, masked on read.

-

21.6.20.1 Lock control
The lock control may set the lock bit by writing a 1 to bit 16 of the CONFIG Register. When
a burst occurs, the AHB arbiter will not de-grant the master during the burst until the lock
is deasserted. The DMA Controller can be locked for a a single burst such as a long
source fetch burst or a long destination drain burst. The DMA Controller does not usually
assert the lock continuously for a source fetch burst followed by a destination drain burst.
There are situations when the DMA Controller asserts the lock for source transfers
followed by destination transfers. This is possible when internal conditions in the DMA
Controller permit it to perform a source fetch followed by a destination drain back-to-back.

21.6.20.2 Flow control and transfer type
Table 351 lists the bit values of the three flow control and transfer type bits identified in
Table Table 350.
Table 351. Flow control and transfer type bits

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Bit value

Transfer type

Controller

000

Memory to memory

DMA

001

Memory to peripheral

DMA

010

Peripheral to memory

DMA

011

Source peripheral to destination peripheral

DMA

100

Source peripheral to destination peripheral

Destination peripheral

101

Memory to peripheral

Peripheral

110

Peripheral to memory

Peripheral

111

Source peripheral to destination peripheral

Source peripheral

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Chapter 21: LPC43xx/LPC43Sxx General Purpose DMA (GPDMA)

21.7 Functional description
21.7.1 DMA controller functional description
The DMA Controller enables peripheral-to-memory, memory-to-peripheral,
peripheral-to-peripheral, and memory-to-memory transactions. Each DMA stream
provides unidirectional serial DMA transfers for a single source and destination. For
example, a bidirectional port requires one stream for transmit and one for receive. The
source and destination areas can each be either a memory region or a peripheral, and
can be accessed through the AHB master. Figure 54 shows a block diagram of the DMA
Controller.
The functions of the DMA Controller are described in the following sections.

21.7.1.1 AHB slave interface
All transactions to DMA Controller registers on the AHB slave interface are 32 bits wide.
Eight bit and 16-bit accesses are not supported and will result in an exception.

21.7.1.2 Control logic and register bank
The register block stores data written or to be read across the AHB interface.

21.7.1.3 DMA request and response interface
See DMA Interface description for information on the DMA request and response
interface.

21.7.1.4 Channel logic and channel register bank
The channel logic and channel register bank contains registers and logic required for each
DMA channel.

21.7.1.5 Interrupt request
The interrupt request generates the interrupt to the ARM processor.

21.7.1.6 AHB master interface
The DMA Controller contains two AHB master interfaces. Each AHB master is capable of
dealing with all types of AHB transactions, including:

• Split, retry, and error responses from slaves. If a peripheral performs a split or retry,
the DMA Controller stalls and waits until the transaction can complete.

• Locked transfers for source and destination of each stream.
• Setting of protection bits for transfers on each stream.
21.7.1.6.1

Bus and transfer widths
The physical width of the AHB bus is 32 bits. Source and destination transfers can be of
differing widths and can be the same width or narrower than the physical bus width. The
DMA Controller packs or unpacks data as appropriate.

21.7.1.6.2

Endian behavior
The DMA Controller can cope with both little-endian and big-endian addressing. Software
can set the endianness of each AHB master individually.

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Chapter 21: LPC43xx/LPC43Sxx General Purpose DMA (GPDMA)

Internally the DMA Controller treats all data as a stream of bytes instead of 16-bit or 32-bit
quantities. This means that when performing mixed-endian activity, where the endianness
of the source and destination are different, byte swapping of the data within the 32-bit data
bus is observed.
Note: If byte swapping is not required, then use of different endianness between the
source and destination addresses must be avoided. Table 352 shows endian behavior for
different source and destination combinations.
Table 352. Endian behavior
Source
endian

Destination
endian

Source
width

Destination
width

Little

Little

8

8

Little

Little

Little

Little

Little

Little

Little

UM10503

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Little

Little

Little

Little

Little

Little

Little

8

8

16

16

16

32

32

16

32

8

16

32

8

16

Source
Source data Destination Destination data
transfer
transfer
no/byte lane
no/byte lane
1/[7:0]

21

1/[7:0]

21212121

2/[15:8]

43

2/[15:8]

43434343

3/[23:16]

65

3/[23:16]

65656565

4/[31:24]

87

4/[31:24]

87878787

1/[7:0]

21

1/[15:0]

43214321

2/[15:8]

43

2/[31:16]

87658765

3/[23:16]

65

4/[31:24]

87

1/[7:0]

21

1/[31:0]

87654321

2/[15:8]

43

3/[23:16]

65

4/[31:24]

87

1/[7:0]

21

1/[7:0]

21212121

1/[15:8]

43

2/[15:8]

43434343

2/[23:16]

65

3/[23:16]

65656565

2/[31:24]

87

4/[31:24]

87878787

1/[7:0]

21

1/[15:0]

43214321

1/[15:8]

43

2/[31:16]

87658765

2/[23:16]

65

2/[31:24]

87

1/[7:0]

21

1/[31:0]

87654321

1/[15:8]

43

2/[23:16]

65

2/[31:24]

87

1/[7:0]

21

1/[7:0]

21212121

1/[15:8]

43

2/[15:8]

43434343

1/[23:16]

65

3/[23:16]

65656565

1/[31:24]

87

4/[31:24]

87878787

1/[7:0]

21

1/[15:0]

43214321

1/[15:8]

43

2/[31:16]

87658765

1/[23:16]

65

1/[31:24]

87

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Chapter 21: LPC43xx/LPC43Sxx General Purpose DMA (GPDMA)

Table 352. Endian behavior …continued
Source
endian

Destination
endian

Source
width

Destination
width

Source
Source data Destination Destination data
transfer
transfer
no/byte lane
no/byte lane

Little

Little

32

32

1/[7:0]

21

1/[15:8]

43

1/[23:16]

65

1/[31:24]

87

1/[31:24]
2/[23:16]

Big

Big

Big

Big

Big

Big

Big

Big

Big

UM10503

User manual

Big

Big

Big

Big

Big

Big

Big

Big

Big

8

8

8

16

16

16

32

32

32

8

16

32

8

16

32

8

16

32

1/[31:0]

87654321

12

1/[31:24]

12121212

34

2/[23:16]

34343434

3/[15:8]

56

3/[15:8]

56565656

4/[7:0]

78

4/[7:0]

78787878

1/[31:24]

12

1/[15:0]

12341234

2/[23:16]

34

2/[31:16]

56785678

3/[15:8]

56
1/[31:0]

12345678

4/[7:0]

78

1/[31:24]

12

2/[23:16]

34

3/[15:8]

56

4/[7:0]

78

1/[31:24]

12

1/[31:24]

12121212

1/[23:16]

34

2/[23:16]

34343434

2/[15:8]

56

3/[15:8]

56565656

2/[7:0]

78

4/[7:0]

78787878

1/[31:24]

12

1/[15:0]

12341234

1/[23:16]

34

2/[31:16]

56785678

2/[15:8]

56

2/[7:0]

78

1/[31:24]

12

1/[31:0]

12345678

1/[23:16]

34

2/[15:8]

56

2/[7:0]

78

1/[31:24]

12

1/[31:24]

12121212

1/[23:16]

34

2/[23:16]

34343434

1/[15:8]

56

3/[15:8]

56565656

1/[7:0]

78

4/[7:0]

78787878

1/[31:24]

12

1/[15:0]

12341234

1/[23:16]

34

2/[31:16]

56785678

1/[15:8]

56

1/[7:0]

78
1/[31:0]

12345678

1/[31:24]

12

1/[23:16]

34

1/[15:8]

56

1/[7:0]

78

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Chapter 21: LPC43xx/LPC43Sxx General Purpose DMA (GPDMA)

21.7.1.6.3

Error conditions
An error during a DMA transfer is flagged directly by the peripheral by asserting an Error
response on the AHB bus during the transfer. The DMA Controller automatically disables
the DMA stream after the current transfer has completed, and can optionally generate an
error interrupt to the CPU. This error interrupt can be masked.

21.7.1.7 Channel hardware
Each stream is supported by a dedicated hardware channel, including source and
destination controllers, as well as a FIFO. This enables better latency than a DMA
controller with only a single hardware channel shared between several DMA streams and
simplifies the control logic.

21.7.1.8 DMA request priority
DMA channel priority is fixed. DMA channel 0 has the highest priority and DMA channel 7
has the lowest priority.
If the DMA Controller is transferring data for the lower priority channel and then the higher
priority channel goes active, it completes the number of transfers delegated to the master
interface by the lower priority channel before switching over to transfer data for the higher
priority channel. In the worst case this is as large as a one quadword.
It is recommended that memory-to-memory transactions use the lowest priority channel.
Otherwise other AHB bus masters are prevented from accessing the bus during DMA
Controller memory-to-memory transfer.

21.7.1.9 Interrupt generation
A combined interrupt output is generated as an OR function of the individual interrupt
requests of the DMA Controller and is connected to the interrupt controller.

21.8 Using the DMA controller
21.8.1 Programming the DMA controller
All accesses to the DMA Controller internal register must be word (32-bit) reads and
writes.

21.8.1.1 Enabling the DMA controller
To enable the DMA controller set the Enable bit in the CONFIG register.

21.8.1.2 Disabling the DMA controller
To disable the DMA controller:

• Read the ENBLDCHNS register and ensure that all the DMA channels have been
disabled. If any channels are active, see Disabling a DMA channel.

• Disable the DMA controller by writing 0 to the DMA Enable bit in the CONFIG register.
21.8.1.3 Enabling a DMA channel
To enable the DMA channel set the channel enable bit in the relevant DMA channel
configuration register. Note that the channel must be fully initialized before it is enabled.
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Chapter 21: LPC43xx/LPC43Sxx General Purpose DMA (GPDMA)

21.8.1.4 Disabling a DMA channel
A DMA channel can be disabled in three ways:

• By writing directly to the channel enable bit. Any outstanding data in the FIFO’s is lost
if this method is used.

• By using the active and halt bits in conjunction with the channel enable bit.
• By waiting until the transfer completes. This automatically clears the channel.
Disabling a DMA channel and losing data in the FIFO
Clear the relevant channel enable bit in the relevant channel configuration register. The
current AHB transfer (if one is in progress) completes and the channel is disabled. Any
data in the FIFO is lost.
Disabling the DMA channel without losing data in the FIFO

• Set the halt bit in the relevant channel configuration register. This causes any future
DMA request to be ignored.

• Poll the active bit in the relevant channel configuration register until it reaches 0. This
bit indicates whether there is any data in the channel that has to be transferred.

• Clear the channel enable bit in the relevant channel configuration register
21.8.1.5 Setting up a new DMA transfer
To set up a new DMA transfer:
If the channel is not set aside for the DMA transaction:
1. Read the ENBLDCHNS controller register and find out which channels are inactive.
2. Choose an inactive channel that has the required priority.
3. Program the DMA controller

21.8.1.6 Halting a DMA channel
Set the halt bit in the relevant DMA channel configuration register. The current source
request is serviced. Any further source DMA request is ignored until the halt bit is cleared.

21.8.1.7 Programming a DMA channel
1. Choose a free DMA channel with the priority needed. DMA channel 0 has the highest
priority and DMA channel 7 the lowest priority.
2. Clear any pending interrupts on the channel to be used by writing to the IntTCClear
and INTERRCLEAR register. The previous channel operation might have left interrupt
active.
3. Write the source address into the CSRCADDR register.
4. Write the destination address into the CDESTADDR register.
5. Write the address of the next LLI into the CLLI register. If the transfer comprises of a
single packet of data then 0 must be written into this register.
6. Write the control information into the CCONTROL register.
7. Write the channel configuration information into the CCONFIG register. If the enable
bit is set then the DMA channel is automatically enabled.
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Chapter 21: LPC43xx/LPC43Sxx General Purpose DMA (GPDMA)

21.8.2 Flow control
The peripheral that controls the length of the packet is known as the flow controller. The
flow controller is usually the DMA Controller where the packet length is programmed by
software before the DMA channel is enabled. If the packet length is unknown when the
DMA channel is enabled, either the source or destination peripherals can be used as the
flow controller.
For simple or low-performance peripherals that know the packet length (that is, when the
peripheral is the flow controller), a simple way to indicate that a transaction has completed
is for the peripheral to generate an interrupt and enable the processor to reprogram the
DMA channel.
The transfer size value (in the CCONTROL register) is ignored if a peripheral is configured
as the flow controller.
When the DMA transfer is completed:
1. The DMA Controller issues an acknowledge to the peripheral in order to indicate that
the transfer has finished.
2. A TC interrupt is generated, if enabled.
3. The DMA Controller moves on to the next LLI.
The following sections describe the DMA Controller data flow sequences for the four
allowed transfer types:

•
•
•
•

Memory-to-peripheral (master 1 only).
Peripheral-to-memory (master 1 only).
Memory-to-memory.
Peripheral-to-peripheral (master 1 only).

Each transfer type can have either the peripheral or the DMA Controller as the flow
controller so there are eight possible control scenarios.
Table 353 indicates the request signals used for each type of transfer.
Table 353. DMA request signal usage
Transfer direction

Request generator

Flow controller

Memory-to-peripheral

Peripheral

DMA Controller

Memory-to-peripheral

Peripheral

Peripheral

Peripheral-to-memory

Peripheral

DMA Controller

Peripheral-to-memory

Peripheral

Peripheral

Memory-to-memory

DMA Controller

DMA Controller

Source peripheral to destination peripheral

Source peripheral and destination peripheral

Source peripheral

Source peripheral to destination peripheral

Source peripheral and destination peripheral

Destination peripheral

Source peripheral to destination peripheral

Source peripheral and destination peripheral

DMA Controller

21.8.2.1 Peripheral-to-memory or memory-to-peripheral DMA flow
For a peripheral-to-memory or memory-to-peripheral DMA flow, the following sequence
occurs:
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Chapter 21: LPC43xx/LPC43Sxx General Purpose DMA (GPDMA)

1. Program and enable the DMA channel.
2. Wait for a DMA request.
3. The DMA Controller starts transferring data when:
– The DMA request goes active.
– The DMA stream has the highest pending priority.
– The DMA Controller is the bus master of the AHB bus.
4. If an error occurs while transferring the data, an error interrupt is generated and
disables the DMA stream, and the flow sequence ends.
5. Decrement the transfer count if the DMA Controller is performing the flow control.
6. If the transfer has completed (indicated by the transfer count reaching 0, if the DMA
Controller is performing flow control, or by the peripheral sending a DMA request, if
the peripheral is performing flow control):
– The DMA Controller responds with a DMA acknowledge.
– The terminal count interrupt is generated (this interrupt can be masked).
– If the CLLI Register is not 0, then reload the CSRCADDR, CDESTADDR, CLLI,
and CCONTROL registers and go to back to step 2. However, if CLLI is 0, the DMA
stream is disabled and the flow sequence ends.

21.8.2.2 Peripheral-to-peripheral DMA flow
For a peripheral-to-peripheral DMA flow, the following sequence occurs:
1. Program and enable the DMA channel.
2. Wait for a source DMA request.
3. The DMA Controller starts transferring data when:
– The DMA request goes active.
– The DMA stream has the highest pending priority.
– The DMA Controller is the bus master of the AHB bus.
4. If an error occurs while transferring the data an error interrupt is generated, the DMA
stream is disabled, and the flow sequence ends.
5. Decrement the transfer count if the DMA Controller is performing the flow control.
6. If the transfer has completed (indicated by the transfer count reaching 0 if the DMA
Controller is performing flow control, or by the peripheral sending a DMA request if the
peripheral is performing flow control):
– The DMA Controller responds with a DMA acknowledge to the source peripheral.
– Further source DMA requests are ignored.
7. When the destination DMA request goes active and there is data in the DMA
Controller FIFO, transfer data into the destination peripheral.
8. If an error occurs while transferring the data, an error interrupt is generated, the DMA
stream is disabled, and the flow sequence ends.
9. If the transfer has completed it is indicated by the transfer count reaching 0 if the DMA
Controller is performing flow control, or by the sending a DMA request if the peripheral
is performing flow control. The following happens:

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Chapter 21: LPC43xx/LPC43Sxx General Purpose DMA (GPDMA)

– The DMA Controller responds with a DMA acknowledge to the destination
peripheral.
– The terminal count interrupt is generated (this interrupt can be masked).
– If the CLLI Register is not 0, then reload the CSRCADDR, CDESTADDR, CLLI,
and CCONTROL Registers and go to back to step 2. However, if CLLI is 0, the
DMA stream is disabled and the flow sequence ends.

21.8.2.3 Memory-to-memory DMA flow
For a memory-to-memory DMA flow the following sequence occurs:
1. Program and enable the DMA channel.
2. Transfer data whenever the DMA channel has the highest pending priority and the
DMA Controller gains mastership of the AHB bus.
3. If an error occurs while transferring the data, generate an error interrupt and disable
the DMA stream.
4. Decrement the transfer count.
5. If the count has reached zero:
– Generate a terminal count interrupt (the interrupt can be masked).
– If the CLLI Register is not 0, then reload the CSRCADDR, CDESTADDR, CLLI,
and CCONTROL Registers and go to back to step 2. However, if CLLI is 0, the
DMA stream is disabled and the flow sequence ends.
Note: Memory-to-memory transfers should be programmed with a low channel priority,
otherwise other DMA channels cannot access the bus until the memory-to-memory
transfer has finished, or other AHB masters cannot perform any transaction.

21.8.3 Interrupt requests
Interrupt requests can be generated when an AHB error is encountered or at the end of a
transfer (terminal count), after all the data corresponding to the current LLI has been
transferred to the destination. The interrupts can be masked by programming bits in the
relevant CCONTROL and CCONFIG Channel Registers. Interrupt status registers are
provided which group the interrupt requests from all the DMA channels prior to interrupt
masking (RAWINTTCSTAT and RAWINTERRSTAT), and after interrupt masking
(INTTCSTAT and INTERRSTAT). The INTSTAT Register combines both the INTTCSTAT
and INTERRSTAT requests into a single register to enable the source of an interrupt to be
quickly found. Writing to the INTTCCLEAR or the INTERRCLR Registers with a bit set
HIGH enables selective clearing of interrupts.

21.8.3.1 Hardware interrupt sequence flow
When a DMA interrupt request occurs, the Interrupt Service Routine needs to:
1. Read the INTTCSTAT Register to determine whether the interrupt was generated due
to the end of the transfer (terminal count). A HIGH bit indicates that the transfer
completed. If more than one request is active, it is recommended that the highest
priority channels be checked first.
2. Read the INTERRSTAT Register to determine whether the interrupt was generated
due to an error occurring. A HIGH bit indicates that an error occurred.
3. Service the interrupt request.
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Chapter 21: LPC43xx/LPC43Sxx General Purpose DMA (GPDMA)

4. For a terminal count interrupt, write a 1 to the relevant bit of the INTTCCLR Register.
For an error interrupt write a 1 to the relevant bit of the INTERRCLR Register to clear
the interrupt request.

21.8.4 Address generation
Address generation can be either incrementing or non-incrementing (address wrapping is
not supported).
Some devices, especially memories, disallow burst accesses across certain address
boundaries. The DMA controller assumes that this is the case with any source or
destination area, which is configured for incrementing addressing. This boundary is
assumed to be aligned with the specified burst size. For example, if the channel is set for
16-transfer burst to a 32-bit wide device then the boundary is 64-bytes aligned (that is
address bits [5:0] equal 0). If a DMA burst is to cross one of these boundaries, then,
instead of a burst, that transfer is split into separate AHB transactions.
Note: When transferring data to or from the SDRAM, the SDRAM access must always be
programmed to 32 bit accesses. The SDRAM memory controller does not support
AHB-INCR4 or INCR8 bursts using halfword or byte transfer-size. Start address in
SDRAM should always be aligned to a burst boundary address.

21.8.4.1 Word-aligned transfers across a boundary
The channel is configured for 16-transfer bursts, each transfer 32-bits wide, to a
destination for which address incrementing is enabled. The start address for the current
burst is 0x0C000024, the next boundary (calculated from the burst size and transfer
width) is 0x0C000040.
The transfer will be split into two AHB transactions:

• a 7-transfer burst starting at address 0x0C000024
• a 9-transfer burst starting at address 0x0C000040.
21.8.5 Scatter/gather
Scatter/gather is supported through the use of linked lists. This means that the source and
destination areas do not have to occupy contiguous areas in memory. Where
scatter/gather is not required, the CLLI Register must be set to 0.
The source and destination data areas are defined by a series of linked lists. Each Linked
List Item (LLI) controls the transfer of one block of data, and then optionally loads another
LLI to continue the DMA operation, or stops the DMA stream. The first LLI is programmed
into the DMA Controller.
The data to be transferred described by a LLI (referred to as the packet of data) usually
requires one or more DMA bursts (to each of the source and destination).

21.8.5.1 Linked list items
A Linked List Item (LLI) consists of four words. These words are organized in the following
order:
1. CSRCADDR
2. CDESTADDR
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Chapter 21: LPC43xx/LPC43Sxx General Purpose DMA (GPDMA)

3. CLLI
4. CCONTROL
Note: The CCONFIG DMA channel Configuration Register is not part of the linked list
item.
21.8.5.1.1

Programming the DMA controller for scatter/gather DMA
To program the DMA Controller for scatter/gather DMA:
1. Write the LLIs for the complete DMA transfer to memory. Each linked list item contains
four words:
– Source address.
– Destination address.
– Pointer to next LLI.
– Control word.
The last LLI has its linked list word pointer set to 0.
2. Choose a free DMA channel with the priority required. DMA channel 0 has the highest
priority and DMA channel 7 the lowest priority.
3. Write the first linked list item, previously written to memory, to the relevant channel in
the DMA Controller.
4. Write the channel configuration information to the channel Configuration Register and
set the Channel Enable bit. The DMA Controller then transfers the first and then
subsequent packets of data as each linked list item is loaded.
5. An interrupt can be generated at the end of each LLI depending on the Terminal
Count bit in the CCONTROL Register. If this bit is set an interrupt is generated at the
end of the relevant LLI. The interrupt request must then be serviced and the relevant
bit in the INTTCCLEAR Register must be set to clear the interrupt.

21.8.5.1.2

Example of scatter/gather DMA
See Figure 55 for an example of an LLI. A section of memory is to be transferred to a
peripheral. The addresses of each LLI entry are given, in hexadecimal, at the left-hand
side of the figure. The right side of the figure shows the memory containing the data to be
transferred.

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Chapter 21: LPC43xx/LPC43Sxx General Purpose DMA (GPDMA)

Linked List Array
LLI 1
0x2000 0000

LLI 2
0x2000 0010

LLI 3
0x2000 0020

Source address

= 0x2000 A200

Destination address

= peripheral

Next LLI address

= 0x2000 0010

Control information

= length

Source address

= 0x2000 B200

Destination address

= peripheral

Next LLI address

= 0x2000 0020

Control information

= length

Source address

= 0x2000 0200

Destination address

= peripheral

Next LLI address

= 0x2000 0030

Control information

= length

0x2000 A200

3072

3072 bytes of data

0x2000 AE00
0x2000 B200

3072

3072

3072 bytes of data

0x2000 BE00
0x2000 0200

3072 bytes of data

0x2000 0E00
LLI 8
0x2000 0070

Source address

= 0x2000 1200

Destination address

= peripheral

Next LLI address

= 0 ( end of list )

Control information

= length

0x2000 1200

3072
3072 bytes of data

0x2000 1E00

Fig 55. LLI example

The first LLI, stored at 0x2000 0000, defines the first block of data to be transferred, which
is the data stored from address 0x2000 A200 to 0x2000 AE00:

•
•
•
•
•
•

Source start address 0x2000 A200.
Destination address set to the destination peripheral address.
Transfer width, word (32-bit).
Transfer size, 3072 bytes (0xC00).
Source and destination burst sizes, 16 transfers.
Next LLI address, 0x2000 0010.

The second LLI, stored at 0x2000 0010, describes the next block of data to be transferred:

•
•
•
•
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Source start address 0x2000 B200.
Destination address set to the destination peripheral address.
Transfer width, word (32-bit).
Transfer size, 3072 bytes (0xC00).
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• Source and destination burst sizes, 16 transfers.
• Next LLI address, 0x2000 0020.
A chain of descriptors is built up, each one pointing to the next in the series. To initialize
the DMA stream, the first LLI, 0x2000 0000, is programmed into the DMA Controller.
When the first packet of data has been transferred the next LLI is automatically loaded.
The final LLI is stored at 0x2000 0070 and contains:

•
•
•
•
•
•

Source start address 0x2000 1200.
Destination address set to the destination peripheral address.
Transfer width, word (32-bit).
Transfer size, 3072 bytes (0xC00).
Source and destination burst sizes, 16 transfers.
Next LLI address, 0x0.

Because the next LLI address is set to zero, this is the last descriptor, and the DMA
channel is disabled after transferring the last item of data. The channel is probably set to
generate an interrupt at this point to indicate to the ARM processor that the channel can
be reprogrammed.

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Chapter 22: LPC43xx/LPC43Sxx SD/MMC interface
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User manual

22.1 How to read this chapter
The SD/MMC card interface is available on all LPC43xx/LPC43Sxx parts.

22.2 Basic configuration
The SD/MMC interface is configured as follows:

• The SD/MMC is reset by the SDIO_RST (reset # 20).
• The delay values on the sample and drive inputs and outputs can be adjusted using
the SDDELAY register in the SYSCON block. See Table 203.
Table 354. SDIO clocking and power control
Base clock

Branch clock

Operating frequency

SDIO register
interface

BASE_M4_CLK

CLK_M4_SDIO

up to 204 MHz

SDIO bit rate clock

BASE_SDIO_CLK

CLK_SDIO

Up to 52 MHz

22.3 Features
The SD/MMC card interface supports the following features:

•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
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Secure Digital memory protocol commands.
Secure Digital I/O protocol commands.
Multimedia Card protocol commands.
CE-ATA digital protocol commands.
Command Completion signal and interrupt to processor.
Completion Signal disable feature.
One SD or MMC (4.4) or CE-ATA (1.1) device.
CRC generation and error detection.
Provides individual clock control to selectively turn ON or OFF clock to the card.
SDIO interrupts in 1-bit and 4-bit modes.
SDIO suspend and resume operation.
SDIO read wait.
Block size of 1 to 65,535 bytes
FIFO over-run and under-run prevention by stopping card clock.
Little-endian mode of AHB operation.
Internal (bus mastering) DMA.
Two FIFOs, TX and RX FIFO (FIFO depth = 32 and FIFO data width = 32 bits).

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Chapter 22: LPC43xx/LPC43Sxx SD/MMC interface

22.4 General description
The SD/MMC controller interface consists of the following main functional blocks:

• Bus Interface Unit (BIU) - Provides AHB and DMA interfaces for register and data
read/writes.

• Card Interface Unit (CIU) - Handles the card protocols and provides clock
management.

• Internal MCI DMA controller: AHB bus mastering DMA controller

SDIO
Interrupt
Control

Power,
Pullup,
Card Detect,
& Debounce
Control

Host
Interface
Unit

MUX/
De-Mux
Unit

Registers
Command
Control
Path

DMA
Interface
Control
AHB
Master
Interface

Power
Switches

Socket

Output Hold Register

APB/AHB
Slave
Interface

Interrupt
Control

Regulators

CIU

Synchronizer

Interrupts ,
status

BIU

Input Sample Register

CLK_M4_SDIO

FIFO
Control

Internal
DMA
Controller

Data
Path
Control

Write
Protect
Card
Detect

Card

cclk
ccmd
cdata

cclk_in_drv
cclk_in_sample
cclk_in

FIFO
RAM

Clock
Control

Note: The card_detect and write-protect signals are from the
SD/MMC card socket and not from the SD/MMC card.

Fig 56. SD/MMC block diagram

22.5 Pin description
Table 355. SD/MMC pin description

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User manual

Pin function

Direction Description

SD_CLK

O

SD/SDIO/MMC clock

SD_CD

I

SDIO card detect for single slot

SD_WP

I

SDIO card write protect

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Chapter 22: LPC43xx/LPC43Sxx SD/MMC interface

Table 355. SD/MMC pin description
Pin function

Direction Description

SD_LED

O

LED On signal. This signal cautions the user not to remove
the SD card while it is accessed.

SD_CMD

I/O

Command input/output

SD_D[7:0]

I/O

Data input/output for data lines DAT[7:0]

SD_VOLT[2:0]

O

SD/MMC bus voltage select output 2:0. SD/MMC General
Purpose Output pins on pins SD_VOLT0, SD_VOLT1, and
SD_VOLT2. These pins can be used to control an optional
external regulator for the SD/MMC slot. If an external
regulator is used to control the SD/MMC slot, voltage level
translation will be needed between the IO pads and the
SD/MMC slot.

SD_RST

O

SD/MMC reset signal for MMC4.4 card.

SD_POW

O

SD/SDIO/MMC slot power enable

22.6 Register description
Table 356. Register overview: SDMMC (base address: 0x4000 4000)
Name

Access

Address
offset

Description

Reset value

Reference

CTRL

R/W

0x000

Control Register

0

Table 357

PWREN

R/W

0x004

Power Enable Register

0

Table 358

CLKDIV

R/W

0x008

Clock Divider Register

0

Table 359

CLKSRC

R/W

0x00C

SD Clock Source Register

0

Table 360

CLKENA

R/W

0x010

Clock Enable Register

0

Table 361

TMOUT

R/W

0x014

Time-out Register

CTYPE

R/W

0x018

Card Type Register

BLKSIZ

R/W

0x01C

BYTCNT

R/W

0x020

INTMASK

R/W

0x024

Interrupt Mask Register

CMDARG

R/W

0x028

Command Argument Register

CMD

R/W

0x02C

RESP0

R

0x030

RESP1

R

RESP2

R

Table 362
0

Table 363

Block Size Register

0x200

Table 364

Byte Count Register

0x200

Table 365
Table 366

0x00000000

Table 367

Command Register

0x00000000

Table 368

Response Register 0

0x00000000

Table 369

0x034

Response Register 1

0x00000000

Table 370

0x038

Response Register 2

0

Table 371

RESP3

R

0x03C

Response Register 3

0

Table 372

MINTSTS

R

0x040

Masked Interrupt Status Register

0

Table 373

RINTSTS

R/W

0x044

Raw Interrupt Status Register

0

Table 374

STATUS

R

0x048

Status Register

Table 375

FIFOTH

R/W

0x04C

FIFO Threshold Watermark Register

CDETECT

R

0x050

Card Detect Register

Table 377

WRTPRT

R

0x054

Write Protect Register

Table 378

-

-

0x058

Reserved

-

-

TCBCNT

R

0x05C

Transferred CIU Card Byte Count Register

0x00000000

Table 379

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0x0F80 0000

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Chapter 22: LPC43xx/LPC43Sxx SD/MMC interface

Table 356. Register overview: SDMMC (base address: 0x4000 4000)
Name

Access

Address
offset

Description

Reset value

Reference

TBBCNT

R

0x060

Transferred Host to BIU-FIFO Byte Count
Register

0

Table 380

DEBNCE

R/W

0x064

Debounce Count Register

-

-

0x068

Reserved

-

-

-

-

0x06C

Reserved

-

-

-

-

0x070

Reserved

-

-

-

-

0x074

Reserved

-

-

RST_N

R/W

0x078

Hardware Reset

-

-

0x07C

Reserved

BMOD

R/W

0x080

PLDMND

W

0x084

DBADDR

R/W

0x088

IDSTS

R/W

IDINTEN
DSCADDR

Table 381

Table 382
-

-

Bus Mode Register

0x00000000

Table 383

Poll Demand Register

0x00000000

Table 384

Descriptor List Base Address Register

0x00000000

Table 385

0x08C

Internal DMAC Status Register

0x00000000

Table 386

R/W

0x090

Internal DMAC Interrupt Enable Register

0x00000000

Table 387

R

0x094

Current Host Descriptor Address Register

0x00000000

Table 388

BUFADDR

R

0x098

Current Buffer Descriptor Address Register

0x00000000

Table 389

DATA

R/W

 0x100

Data FIFO read/write; if address is equal or
greater than 0x100, then FIFO is selected as long
as device is selected. Address 0x100 and above
are mapped to the data FIFO. More than one
address is mapped to the data FIFO so that the
FIFO can be accessed using bursts.

-

22.6.1 Control Register
Table 357. Control Register (CTRL, address 0x4000 4000) bit description
Bit

Symbol

0

CONTROLLER_RESET

1

Value

User manual

Reset
value

Controller reset. To reset controller, software should set bit to 1. This
bit is auto-cleared after two AHB and two cclk_in clock cycles. This
resets:
- BIU/CIU interface
- CIU and state machines
- abort_read_data, send_irq_response, and read_wait bits of Control
register
- start_cmd bit of Command register
Does not affect any registers or DMA interface, or FIFO. or host
interrupts.

0

0

No change.

1

Reset. Reset SD/MMC controller

FIFO_RESET

UM10503

Description

Fifo reset. To reset FIFO, software should set bit to 1. This bit is
auto-cleared after completion of reset operation. auto-cleared after
two AHB clocks.
0

No change.

1

Reset. Reset to data FIFO To reset FIFO pointers

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Chapter 22: LPC43xx/LPC43Sxx SD/MMC interface

Table 357. Control Register (CTRL, address 0x4000 4000) bit description
Bit

Symbol

2

DMA_RESET

Value

Description

Reset
value

Dma reset. To reset DMA interface, software should set bit to 1. This
bit is auto-cleared after two AHB clocks.

0

0

No change.

1

Reset. Reset internal DMA interface control logic

3

-

Reserved

-

4

INT_ENABLE

Global interrupt enable/disable bit. The int port is 1 only when this bit
is 1 and one or more unmasked interrupts are set.

0

0

Disable interrupts

1

Enable interrupts

5

-

Reserved. Always write this bit as 0.

0

6

READ_WAIT

Read/wait. For sending read-wait to SDIO cards.

0

7

8

9

0

Clear read wait

1

Assert read wait

SEND_IRQ_RESPONSE

Send irq response. This bit automatically clears once response is
0
sent. To wait for MMC card interrupts, the host issues CMD40, and
the SD/MMC controller waits for an interrupt response from the MMC
card. In the meantime, if the host wants the SD/MMC interface to exit
waiting for interrupt state, it can set this bit, at which time the
SD/MMC interface command state-machine sends a CMD40
response on the bus and returns to idle state.
0

No change

1

Send auto IRQ response

ABORT_READ_DATA

Abort read data. Used in SDIO card suspend sequence.
0

No change

1

Abort. After suspend command is issued during read-transfer,
software polls card to find when suspend happened. Once suspend
occurs, software sets bit to reset data state-machine, which is waiting
for next block of data. This bit automatically clears once data state
machine resets to idle.
Used in SDIO card suspend sequence.

SEND_CCSD

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0

Send ccsd. When set, the SD/MMC controller sends CCSD to the
0
CE-ATA device. Software sets this bit only if current command is
expecting CCS (that is, RW_BLK) and interrupts are enabled in
CE-ATA device. Once the CCSD pattern is sent to device, the
SD/MMC interface automatically clears send_ccsd bit. It also sets
Command Done (CD) bit in RINTSTS register and generates interrupt
to host if Command Done interrupt is not masked.
NOTE: Once send_ccsd bit is set, it takes two card clock cycles to
drive the CCSD on the CMD line. Due to this, during the boundary
conditions it may happen that CCSD is sent to the CE-ATA device,
even if the device signalled CCS.
0

Clear bit if the SD/MMC controller does not reset the bit.

1

Send Command Completion Signal Disable (CCSD) to CE-ATA
device

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Chapter 22: LPC43xx/LPC43Sxx SD/MMC interface

Table 357. Control Register (CTRL, address 0x4000 4000) bit description
Bit

Symbol

10

SEND_AUTO_STOP_
CCSD

11

Value

Description

Reset
value

Send auto stop ccsd. NOTE: Always set send_auto_stop_ccsd and
0
send_ccsd bits together; send_auto_stop_ccsd should not be set
independent of send_ccsd. When set, the SD/MMC interface
automatically sends internallygenerated STOP command (CMD12) to
CE-ATA device. After sending internally-generated STOP command,
Auto Command Done (ACD) bit in RINTSTS is set and generates
interrupt to host if Auto Command Done interrupt is not masked. After
sending the CCSD, the SD/MMC interface automatically clears
send_auto_stop_ccsd bit.
0

Clear this bit if the SD/MMC controller does not reset the bit.

1

Send internally generated STOP after sending CCSD to CE-ATA
device.

CEATA_DEVICE_
INTERRUPT _STATUS

CEATA device interrupt status. Software should appropriately write to 0
this bit after power-on reset or any other reset to CE-ATA device. After
reset, usually CE-ATA device interrupt is disabled (nIEN = 1). If the
host enables CE-ATA device interrupt, then software should set this
bit.
0

Disabled. Interrupts not enabled in CE-ATA device (nIEN = 1 in ATA
control register)

1

Enabled. Interrupts are enabled in CE-ATA device (nIEN = 0 in ATA
control register)

15:12

-

Reserved

-

16

CARD_VOLTAGE_A0

Controls the state of the SD_VOLT0 pin. SD/MMC card voltage
control is not implemented.

0

17

CARD_VOLTAGE_A1

Controls the state of the SD_VOLT1 pin. SD/MMC card voltage
control is not implemented.

0

18

CARD_VOLTAGE_A2

Controls the state of the SD_VOLT2 pin. SD/MMC card voltage
control is not implemented.

0

23:19

-

Reserved.

0

24

-

Reserved. Always write this bit as 0.

0

25

USE_INTERNAL_DMAC

SD/MMC DMA use.

0

31:26

-

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0

Host. The host performs data transfers through the slave interface

1

DMA. Internal DMA used for data transfer
Reserved

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Chapter 22: LPC43xx/LPC43Sxx SD/MMC interface

22.6.2 Power Enable Register
Table 358. Power Enable Register (PWREN, address 0x4000 4004) bit description
Bit

Symbol

Description

Reset
value

0

POWER_ENABLE

Power on/off switch for card; once power is turned on,
software should wait for regulator/switch ramp-up time
before trying to initialize card.
0 - power off
1 - power on
Optional feature: port can be used as general-purpose
output on the SD_POW pin.

0

31:1

-

Reserved

-

22.6.3 Clock Divider Register
Table 359. Clock Divider Register (CLKDIV, address 0x4000 4008) bit description

UM10503

User manual

Bit

Symbol

Description

Reset
value

7:0

CLK_DIVIDER0

Clock divider-0 value. Clock division is 2*n. For example,
value of 0 means divide by 2*0 = 0 (no division, bypass),
value of 1 means divide by 2*1 = 2, value of ff means
divide by 2*255 = 510, and so on.

0

15:8

CLK_DIVIDER1

Clock divider-1 value. Clock division is 2*n. For example,
0
value of 0 means divide by 2*0 = 0 (no division, bypass),
value of 1 means divide by 2*1 = 2, value of ff means
divide by 2*255 = 510, and so on. In MMC-Ver3.3-only
mode, bits not implemented because only one clock divider
is supported.

23:16

CLK_DIVIDER2

0
Clock divider-2 value. Clock division is 2*n. For example,
value of 0 means divide by 2*0 = 0 (no division, bypass),
value of 1 means divide by 2*1 = 2, value of ff means
divide by 2*255 = 510, and so on. In MMC-Ver3.3-only
mode, bits not implemented because only one clock divider
is supported.

31:24

CLK_DIVIDER3

Clock divider-3 value. Clock division is 2*n. For example,
0
value of 0 means divide by 2*0 = 0 (no division, bypass), a
value of 1 means divide by 2*1 = 2, a value of ff means
divide by 2*255 = 510, and so on.
In MMC-Ver3.3-only mode, bits not implemented because
only one clock divider is supported. divide by 2*0 = 0 (no
division, bypass), value of 1 means divide by 2*1 = 2, value
of ff means divide by 2*255 = 510, and so on. In
MMC-Ver3.3-only mode, bits not implemented because
only one clock divider is supported.

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Chapter 22: LPC43xx/LPC43Sxx SD/MMC interface

22.6.4 SD Clock Source Register
Table 360. SD Clock Source Register (CLKSRC, address 0x4000 400C) bit description
Bit

Symbol

Description

Reset
value

1:0

CLK_SOURCE Clock divider source for SD card.
0
00 - Clock divider 0
01 - Clock divider 1
10 - Clock divider 2
11 - Clock divider 3
In MMC-Ver3.3-only controller, only one clock divider supported.
The cclk_out is always from clock divider 0, and this register is
not implemented.

31:1

-

Reserved

-

22.6.5 Clock Enable Register
Table 361. Clock Enable Register (CLKENA, address 0x4000 4010) bit description
Bit

Symbol

Description

Reset
value

0

CCLK_ENABLE

Clock-enable control for SD card clock. One MMC card clock supported.
0 - Clock disabled
1 - Clock enabled

0

15:1

-

Reserved

-

16

CCLK_LOW_POWER

Low-power control for SD card clock. One MMC card clock supported.
0 - Non-low-power mode
1 - Low-power mode;
stop clock when card in IDLE (should be normally set to only MMC and SD
memory cards; for SDIO cards, if interrupts must be detected, clock should
not be stopped).

0

31:17

-

Reserved

-

22.6.6 Time-out Register
Table 362. Time-out Register (TMOUT, address 0x4000 4014) bit description
Bit

Symbol

Description

Reset
value

7:0

RESPONSE_TIMEOUT

Response time-out value. Value is in number of card output clocks cclk_out.

0x40

31:8

DATA_TIMEOUT

Value for card Data Read time-out; same value also used for Data
Starvation by Host time-out. Value is in number of card output clocks cclk_out of selected card. Starvation by Host time-out. Value is in number
of card output clocks - cclk_out of selected card.

0xFFFFFF

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Chapter 22: LPC43xx/LPC43Sxx SD/MMC interface

22.6.7 Card Type Register
Table 363. Card Type Register (CTYPE, address 0x4000 4018) bit description
Bit

Symbol

Description

Reset
value

0

CARD_WIDTH0

Indicates if card is 1-bit or 4-bit:
0 - 1-bit mode
1 - 4-bit mode

0

1 and 4-bit modes only work when 8-bit mode in
CARD_WIDTH1 is not enabled (bit 16 in this register is
set to 0).
15:1

-

Reserved

-

16

CARD_WIDTH1

Indicates if card is 8-bit:
0 - Non 8-bit mode
1 - 8-bit mode.

0

Reserved

-

31:17 -

22.6.8 Block Size Register
Table 364. Block Size Register (BLKSIZ, address 0x4000 401C) bit description
Bit

Symbol

Description

Reset value

15:0

BLOCK_SIZE

Block size

0x200

31:16

-

Reserved

-

22.6.9 Byte Count Register
Table 365. Byte Count Register (BYTCNT, address 0x4000 4020) bit description
Bit

Symbol

Description

Reset
value

31:0

BYTE_COUNT

Number of bytes to be transferred; should be integer multiple 0x200
of Block Size for block transfers. For undefined number of byte
transfers, byte count should be set to 0. When byte count is set
to 0, it is responsibility of host to explicitly send stop/abort
command to terminate data transfer.

22.6.10 Interrupt Mask Register
Table 366. Interrupt Mask Register (INTMASK, address 0x4000 4024) bit description

UM10503

User manual

Bit

Symbol

Description

0

CDET

Card detect. Bits used to mask unwanted interrupts. Value 0
of 0 masks interrupt; value of 1 enables interrupt.

1

RE

Response error. Bits used to mask unwanted interrupts.
Value of 0 masks interrupt; value of 1 enables interrupt.

0

2

CDONE

Command done. Bits used to mask unwanted interrupts.
Value of 0 masks interrupt; value of 1 enables interrupt.

0

3

DTO

Data transfer over. Bits used to mask unwanted interrupts. 0
Value of 0 masks interrupt; value of 1 enables interrupt.

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Table 366. Interrupt Mask Register (INTMASK, address 0x4000 4024) bit description
Bit

Symbol

Description

Reset
value

4

TXDR

Transmit FIFO data request. Bits used to mask unwanted
interrupts. Value of 0 masks interrupt; value of 1 enables
interrupt.

0

5

RXDR

Receive FIFO data request. Bits used to mask unwanted
interrupts. Value of 0 masks interrupt; value of 1 enables
interrupt.

0

6

RCRC

Response CRC error. Bits used to mask unwanted
interrupts. Value of 0 masks interrupt; value of 1 enables
interrupt.

0

7

DCRC

Data CRC error. Bits used to mask unwanted interrupts.
Value of 0 masks interrupt; value of 1 enables interrupt.

0

8

RTO

Response time-out. Bits used to mask unwanted
interrupts. Value of 0 masks interrupt; value of 1 enables
interrupt.

0

9

DRTO

Data read time-out. Bits used to mask unwanted interrupts. 0
Value of 0 masks interrupt; value of 1 enables interrupt.

10

HTO

Data starvation-by-host time-out (HTO) /Volt_switch_int.
Bits used to mask unwanted interrupts. Value of 0 masks
interrupt; value of 1 enables interrupt.

11

FRUN

FIFO underrun/overrun error. Bits used to mask unwanted 0
interrupts. Value of 0 masks interrupt; value of 1 enables
interrupt.

12

HLE

Hardware locked write error. Bits used to mask unwanted
interrupts. Value of 0 masks interrupt; value of 1 enables
interrupt.

0

13

SBE

Start-bit error. Bits used to mask unwanted interrupts.
Value of 0 masks interrupt; value of 1 enables interrupt.

0

14

ACD

Auto command done. Bits used to mask unwanted
interrupts. Value of 0 masks interrupt; value of 1 enables
interrupt.

0

15

EBE

End-bit error (read)/Write no CRC. Bits used to mask
0
unwanted interrupts. Value of 0 masks interrupt; value of 1
enables interrupt.

16

SDIO_INT_MASK Mask SDIO interrupt. When masked, SDIO interrupt
detection for card is disabled. A 0 masks an interrupt, and
1 enables an interrupt. In MMC-Ver3.3-only mode, this bit
is always 0.

0

31:17

-

-

0

Reserved

22.6.11 Command Argument Register
Table 367. Command Argument Register (CMDARG, address 0x4000 4028) bit description

UM10503

User manual

Bit

Symbol

Description

31:0

CMD_ARG

Value indicates command argument to be passed to card. 0

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22.6.12 Command Register
Table 368. Command Register (CMD, address 0x4000 402C) bit description
Bit

Symbol

5:0
6

7

8

9

10

11

12

13

Value

Description

Reset
value

CMD_INDEX

Command index

0

RESPONSE_EXPECT

Response expect

0

0

None. No response expected from card

1

Expected. Response expected from card

RESPONSE_ LENGTH

Response length
0

Short. Short response expected from card

1

Long. Long response expected from card

CHECK_RESPONSE_
CRC

Check response crc. Some of command responses do not return valid 0
CRC bits. Software should disable CRC checks for those commands
in order to disable CRC checking by controller.
0

Do not check response CRC

1

Check response CRC

DATA_EXPECTED

Data expected
0

None. No data transfer expected (read/write)

1

Data. Data transfer expected (read/write)

READ_WRITE
0

Read from card

1

Write to card

0

Transfer mode. Don't care if no data expected.
0

Block data transfer command

1

Stream data transfer command

0

0
Send auto stop. When set, the SD/MMC interface sends stop
command to SD_MMC_CEATA cards at end of data transfer. Refer to
Table 390 to determine:
- when send_auto_stop bit should be set, since some data transfers
do not need explicit stop commands
- open-ended transfers that software should explicitly send to stop
command
Additionally, when resume is sent to resume - suspended memory
access of SD-Combo card - bit should be set correctly if suspended
data transfer needs send_auto_stop. Don't care if no data expected
from card.

SEND_AUTO_STOP

0

No stop command sent at end of data transfer

1

Send stop command at end of data transfer

WAIT_PRVDATA_
COMPLETE

User manual

0

read/write. Don't care if no data expected from card.

TRANSFER_MODE

UM10503

0

Wait prvdata complete. The wait_prvdata_complete = 0 option
typically used to query status of card during data transfer or to stop
current data transfer; card_number should be same as in previous
command.

0

0

Send. Send command at once, even if previous data transfer has not
completed.

1

Wait. Wait for previous data transfer completion before sending
command.

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Table 368. Command Register (CMD, address 0x4000 402C) bit description
Bit

Symbol

14

STOP_ABORT_CMD

15

Value

Description

Reset
value

Stop abort command. When open-ended or predefined data transfer
is in progress, and host issues stop or abort command to stop data
transfer, bit should be set so that command/data state-machines of
CIU can return correctly to idle state. This is also applicable for Boot
mode transfers. To Abort boot mode, this bit should be set along with
CMD[26] = disable_boot.

0

0

Disabled. Neither stop nor abort command to stop current data
transfer in progress. If abort is sent to function-number currently
selected or not in data-transfer mode, then bit should be set to 0.

1

Enabled. Stop or abort command intended to stop current data
transfer in progress.

SEND_INITIALIZATION

Send initialization. After power on, 80 clocks must be sent to card for 0
initialization before sending any commands to card. Bit should be set
while sending first command to card so that controller will initialize
clocks before sending command to card. This bit should not be set for
either of the boot modes (alternate or mandatory).
0

No. Do not send initialization sequence (80 clocks of 1) before
sending this command.

1

Send. Send initialization sequence before sending this command.

20:16

-

Reserved. Always write as 0.

21

UPDATE_CLOCK_
REGISTERS_ONLY

Update clock registers only. Following register values transferred into 0
card clock domain: CLKDIV, CLRSRC, CLKENA. Changes card
clocks (change frequency, truncate off or on, and set low-frequency
mode); provided in order to change clock frequency or stop clock
without having to send command to cards. During normal command
sequence, when update_clock_registers_only = 0, following control
registers are transferred from BIU to CIU: CMD, CMDARG, TMOUT,
CTYPE, BLKSIZ, BYTCNT. CIU uses new register values for new
command sequence to card(s). When bit is set, there are no
Command Done interrupts because no command is sent to
SD_MMC_CEATA cards.

22

0

Normal. Normal command sequence

1

No. Do not send commands, just update clock register value into card
clock domain

READ_CEATA_DEVICE

UM10503

User manual

0

Read ceata device. Software should set this bit to indicate that
0
CE-ATA device is being accessed for read transfer. This bit is used to
disable read data time-out indication while performing CE-ATA read
transfers. Maximum value of I/O transmission delay can be no less
than 10 seconds.The SD/MMC interface should not indicate read data
time-out while waiting for data from CE-ATA device.
0

No read. Host is not performing read access (RW_REG or RW_BLK)
towards CE-ATA device.

1

Read. Host is performing read access (RW_REG or RW_BLK)
towards CE-ATA device.

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Table 368. Command Register (CMD, address 0x4000 402C) bit description
Bit

Symbol

Value

23

CCS_EXPECTED

Description

Reset
value

CCS expected. If the command expects Command Completion Signal 0
(CCS) from the CE-ATA device, the software should set this control
bit. The SD/MMC controller sets the Data Transfer Over (DTO) bit in
the RINTSTS register and generates an interrupt to the host if the
Data Transfer Over interrupt is not masked.
0

Disabled. Interrupts are not enabled in CE-ATA device (nIEN = 1 in
ATA control register), or command does not expect CCS from device.

1

Enabled. Interrupts are enabled in CE-ATA device (nIEN = 0), and
RW_BLK command expects command completion signal from
CE-ATA device.

24

ENABLE_BOOT

Enable Boot - this bit should be set only for mandatory boot mode.
When Software sets this bit along with start_cmd, CIU starts the boot
sequence for the corresponding card by asserting the CMD line low.
Do NOT set disable_boot and enable_boot together.

0

25

EXPECT_BOOT_ACK

Expect Boot Acknowledge. When Software sets this bit along with
enable_boot, CIU expects a boot acknowledge start pattern of 0-1-0
from the selected card.

0

26

DISABLE_BOOT

Disable Boot. When software sets this bit along with start_cmd, CIU
terminates the boot operation. Do NOT set disable_boot and
enable_boot together.

0

27

BOOT_MODE

Boot Mode

0

28

0

Mandatory Boot operation

1

Alternate Boot operation

VOLT_SWITCH

Voltage switch bit
0

0

Disabled. No voltage switching

1

Enabled. Voltage switching enabled; must be set for CMD11 only

30:29

-

Reserved

31

START_CMD

Start command. Once command is taken by CIU, this bit is cleared.
When bit is set, host should not attempt to write to any command
registers. If write is attempted, hardware lock error is set in raw
interrupt register. Once command is sent and response is received
from SD_MMC_CEATA cards, Command Done bit is set in the raw
interrupt register.

22.6.13 Response Register 0
Table 369. Response Register 0 (RESP0, address 0x4000 4030) bit description

UM10503

User manual

Bit

Symbol

Description

Reset
value

31:0

RESPONSE0

Bit[31:0] of response

0

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Chapter 22: LPC43xx/LPC43Sxx SD/MMC interface

22.6.14 Response Register 1
Table 370. Response Register 1 (RESP1, address 0x4000 4034) bit description
Bit

Symbol

Description

Reset
value

31:0

RESPONSE1

Register represents bit[63:32] of long response. When CIU 0
sends auto-stop command, then response is saved in
register. Response for previous command sent by host is
still preserved in Response 0 register. Additional auto-stop
issued only for data transfer commands, and response type
is always short for them. For information on when CIU
sends auto-stop commands, refer to Auto-Stop.

22.6.15 Response Register 2
Table 371. Response Register 2 (RESP2, address 0x4000 4038) bit description
Bit

Symbol

Description

Reset
value

31:0

RESPONSE2

Bit[95:64] of long response

0

22.6.16 Response Register 3
Table 372. Response Register 3 (RESP3, address 0x4000 403C) bit description
Bit

Symbol

Description

Reset
value

31:0

RESPONSE3

Bit[127:96] of long response

0

22.6.17 Masked Interrupt Status Register
Table 373. Masked Interrupt Status Register (MINTSTS, address 0x4000 4040) bit description

UM10503

User manual

Bit

Symbol

Description

Reset
value

0

CDET

Card detect. Interrupt enabled only if corresponding bit in
interrupt mask register is set.

0

1

RE

Response error. Interrupt enabled only if corresponding bit 0
in interrupt mask register is set.

2

CDONE

Command done. Interrupt enabled only if corresponding bit 0
in interrupt mask register is set.

3

DTO

Data transfer over. Interrupt enabled only if corresponding
bit in interrupt mask register is set.

0

4

TXDR

Transmit FIFO data request. Interrupt enabled only if
corresponding bit in interrupt mask register is set.

0

5

RXDR

Receive FIFO data request. Interrupt enabled only if
corresponding bit in interrupt mask register is set.

0

6

RCRC

Response CRC error. Interrupt enabled only if
corresponding bit in interrupt mask register is set.

0

7

DCRC

Data CRC error. Interrupt enabled only if corresponding bit 0
in interrupt mask register is set.

8

RTO

Response time-out. Interrupt enabled only if corresponding 0
bit in interrupt mask register is set.
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Chapter 22: LPC43xx/LPC43Sxx SD/MMC interface

Table 373. Masked Interrupt Status Register (MINTSTS, address 0x4000 4040) bit description
Bit

Symbol

Description

Reset
value

9

DRTO

Data read time-out. Interrupt enabled only if corresponding 0
bit in interrupt mask register is set.

10

HTO

Data starvation-by-host time-out (HTO). Interrupt enabled
only if corresponding bit in interrupt mask register is set.

0

11

FRUN

FIFO underrun/overrun error. Interrupt enabled only if
corresponding bit in interrupt mask register is set.

0

12

HLE

Hardware locked write error. Interrupt enabled only if
corresponding bit in interrupt mask register is set.

0

13

SBE

Start-bit error. Interrupt enabled only if corresponding bit in 0
interrupt mask register is set.

14

ACD

Auto command done. Interrupt enabled only if
corresponding bit in interrupt mask register is set.

15

EBE

End-bit error (read)/write no CRC. Interrupt enabled only if 0
corresponding bit in interrupt mask register is set.

16

SDIO_
INTERRUPT

Interrupt from SDIO card. SDIO interrupt for card enabled
only if corresponding sdio_int_mask bit is set in Interrupt
mask register (mask bit 1 enables interrupt; 0 masks
interrupt).
0 - No SDIO interrupt from card
1 - SDIO interrupt from card
In MMC-Ver3.3-only mode, this bit is always 0.

-

31:17

-

Reserved

-

0

22.6.18 Raw Interrupt Status Register
Table 374. Raw Interrupt Status Register (RINTSTS, address 0x4000 4044) bit description

UM10503

User manual

Bit

Symbol

Description

0

CDET

Card detect. Writes to bits clear status bit. Value of 1 clears 0
status bit, and value of 0 leaves bit intact. Bits are logged
regardless of interrupt mask status.

1

RE

Response error. Writes to bits clear status bit. Value of 1
clears status bit, and value of 0 leaves bit intact. Bits are
logged regardless of interrupt mask status.

0

2

CDONE

Command done. Writes to bits clear status bit. Value of 1
clears status bit, and value of 0 leaves bit intact. Bits are
logged regardless of interrupt mask status.

0

3

DTO

Data transfer over. Writes to bits clear status bit. Value of 1 0
clears status bit, and value of 0 leaves bit intact. Bits are
logged regardless of interrupt mask status.

4

TXDR

Transmit FIFO data request. Writes to bits clear status bit. 0
Value of 1 clears status bit, and value of 0 leaves bit intact.
Bits are logged regardless of interrupt mask status.

5

RXDR

Receive FIFO data request. Writes to bits clear status bit. 0
Value of 1 clears status bit, and value of 0 leaves bit intact.
Bits are logged regardless of interrupt mask status.

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Table 374. Raw Interrupt Status Register (RINTSTS, address 0x4000 4044) bit description
Bit

Symbol

Description

Reset
value

6

RCRC

Response CRC error. Writes to bits clear status bit. Value
of 1 clears status bit, and value of 0 leaves bit intact. Bits
are logged regardless of interrupt mask status.

0

7

DCRC

Data CRC error. Writes to bits clear status bit. Value of 1
clears status bit, and value of 0 leaves bit intact. Bits are
logged regardless of interrupt mask status.

0

8

RTO_BAR

Response time-out (RTO)/Boot Ack Received (BAR).
Writes to bits clear status bit. Value of 1 clears status bit,
and value of 0 leaves bit intact. Bits are logged regardless
of interrupt mask status.

0

9

DRTO_BDS

Data read time-out (DRTO)/Boot Data Start (BDS). Writes
to bits clear status bit. Value of 1 clears status bit, and
value of 0 leaves bit intact. Bits are logged regardless of
interrupt mask status.

0

10

HTO

Data starvation-by-host time-out (HTO). Writes to bits clear 0
status bit. Value of 1 clears status bit, and value of 0 leaves
bit intact. Bits are logged regardless of interrupt mask
status./Volt_switch_int

11

FRUN

FIFO underrun/overrun error. Writes to bits clear status bit. 0
Value of 1 clears status bit, and value of 0 leaves bit intact.
Bits are logged regardless of interrupt mask status.

12

HLE

Hardware locked write error. Writes to bits clear status bit. 0
Value of 1 clears status bit, and value of 0 leaves bit intact.
Bits are logged regardless of interrupt mask status.

13

SBE

Start-bit error. Writes to bits clear status bit. Value of 1
clears status bit, and value of 0 leaves bit intact. Bits are
logged regardless of interrupt mask status.

0

14

ACD

Auto command done. Writes to bits clear status bit. Value
of 1 clears status bit, and value of 0 leaves bit intact. Bits
are logged regardless of interrupt mask status.

0

15

EBE

End-bit error (read)/write no CRC. Writes to bits clear
0
status bit. Value of 1 clears status bit, and value of 0 leaves
bit intact. Bits are logged regardless of interrupt mask
status.

16

SDIO_INTERRUPT

Interrupt from SDIO card. Writes to these bits clear them.
Value of 1 clears bit and 0 leaves bit intact.
0 - No SDIO interrupt from card
1 - SDIO interrupt from card
In MMC-Ver3.3-only mode, bits always 0. Bits are logged
regardless of interrupt-mask status.

0

Reserved.

-

31:17 -

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Chapter 22: LPC43xx/LPC43Sxx SD/MMC interface

22.6.19 Status Register
Table 375. Status Register (STATUS, address 0x4000 4048) bit description
Bit

Symbol

Description

Reset
value

0

FIFO_RX_
WATERMARK

FIFO reached Receive watermark level; not qualified with data transfer.

0

1

FIFO_TX_
WATERMARK

FIFO reached Transmit watermark level; not qualified with data transfer.

1

2

FIFO_EMPTY

FIFO is empty status

1

3

FIFO_FULL

FIFO is full status

0

7:4

CMDFSMSTATES

Command FSM states:
0 - Idle
1 - Send init sequence
2 - Tx cmd start bit
3 - Tx cmd tx bit
4 - Tx cmd index + arg
5 - Tx cmd crc7
6 - Tx cmd end bit
7 - Rx resp start bit
8 - Rx resp IRQ response
9 - Rx resp tx bit
10 - Rx resp cmd idx
11 - Rx resp data
12 - Rx resp crc7
13 - Rx resp end bit
14 - Cmd path wait NCC
15 - Wait; CMD-to-response turnaround
NOTE: The command FSM state is represented using 19 bits. The STATUS
Register(7:4) has 4 bits to represent the command FSM states. Using these 4
bits, only 16 states can be represented. Thus three states cannot be
represented in the STATUS(7:4) register. The three states that are not
represented in the STATUS Register(7:4) are:
- Bit 16 - Wait for CCS
- Bit 17 - Send CCSD
- Bit 18 - Boot Mode
Due to this, while command FSM is in Wait for CCS state or Send CCSD or
Boot Mode?, the Status register indicates status as 0 for the bit field 7:4.

0

8

DATA_3_STATUS

Raw selected card_data[3]; checks whether card is present
0 - card not present
1 - card present

9

DATA_BUSY

Inverted version of raw selected card_data[0]
0 - card data not busy
1 - card data busy

10

DATA_STATE_
MC_BUSY

Data transmit or receive state-machine is busy

16:11

RESPONSE_INDEX Index of previous response, including any auto-stop sent by core.

0

29:17

FIFO_COUNT

FIFO count - Number of filled locations in FIFO

0

30

DMA_ACK

DMA acknowledge signal state

0

31

DMA_REQ

DMA request signal state

0

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22.6.20 FIFO Threshold Watermark Register
Table 376. FIFO Threshold Watermark Register (FIFOTH, address 0x4000 404C) bit description
Bit

Symbol

11:0

TX_WMARK

FIFO threshold watermark level when transmitting data to card. When 0
FIFO data count is less than or equal to this number, DMA/FIFO
request is raised. If Interrupt is enabled, then interrupt occurs. During
end of packet, request or interrupt is generated, regardless of
threshold programming. In non-DMA mode, when transmit FIFO
threshold (TXDR) interrupt is enabled, then interrupt is generated
instead of DMA request. During end of packet, on last interrupt, host is
responsible for filling FIFO with only required remaining bytes (not
before FIFO is full or after CIU completes data transfers, because
FIFO may not be empty). In DMA mode, at end of packet, if last
transfer is less than burst size, DMA controller does single cycles until
required bytes are transferred. 12 bits - 1 bit less than FIFO-count of
status register, which is 13 bits. Limitation: TX_WMark >= 1;
Recommended value: TX_WMARK = 16; (means less than or equal to
FIFO_DEPTH/2).

15:12

-

Reserved.

27:16

RX_WMARK

FIFO threshold watermark level when receiving data to card. When
0x1F
FIFO data count reaches greater than this number, DMA/FIFO
request is raised. During end of packet, request is generated
regardless of threshold programming in order to complete any
remaining data. In non-DMA mode, when receiver FIFO threshold
(RXDR) interrupt is enabled, then interrupt is generated instead of
DMA request. During end of packet, interrupt is not generated if
threshold programming is larger than any remaining data. It is
responsibility of host to read remaining bytes on seeing Data Transfer
Done interrupt. In DMA mode, at end of packet, even if remaining
bytes are less than threshold, DMA request does single transfers to
flush out any remaining bytes before Data Transfer Done interrupt is
set. 12 bits - 1 bit less than FIFO-count of status register, which is 13
bits. Limitation: RX_WMark less than FIFO_DEPTH-2
Recommended: RX_WMARK = 15; (means greater than
(FIFO_DEPTH/2) - 1)
NOTE: In DMA mode during CCS time-out, the DMA does not
generate the request at the end of packet, even if remaining bytes are
less than threshold. In this case, there will be some data left in the
FIFO. It is the responsibility of the application to reset the FIFO after
the CCS time-out.

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Table 376. FIFO Threshold Watermark Register (FIFOTH, address 0x4000 404C) bit description
Bit

Symbol

30:28

DMA_MTS

31

Value

Description

Reset
value

Burst size of multiple transaction; should be programmed same as
0
DW-DMA controller multiple-transaction-size SRC/DEST_MSIZE.The
units for transfers is the H_DATA_WIDTH parameter. A single transfer
(dw_dma_single assertion in case of Non DW DMA interface) would
be signalled based on this value. Value should be sub-multiple of
(RX_WMark + 1) and (32 - TX_WMark).
For example, if FIFO_DEPTH = 16, FDATA_WIDTH =
H_DATA_WIDTH
Allowed combinations for MSize and TX_WMark are:
MSize = 1, TX_WMARK = 1-15
MSize = 4, TX_WMark = 8
MSize = 4, TX_WMark = 4
MSize = 4, TX_WMark = 12
MSize = 8, TX_WMark = 8
MSize = 8, TX_WMark = 4.
Allowed combinations for MSize and RX_WMark are:
MSize = 1, RX_WMARK = 0-14
MSize = 4, RX_WMark = 3
MSize = 4, RX_WMark = 7
MSize = 4, RX_WMark = 11
MSize = 8, RX_WMark = 7
MSize = 8, RX_WMark = 11
Recommended: MSize = 8, TX_WMark = 8, RX_WMark = 7
0x0

1 transfer

0x1

4 transfers

0x2

8 transfers

0x3

16 transfers

0x4

32 transfers

0x5

64 transfers

0x6

128 transfers

0x7

256 transfers

-

Reserved

0

22.6.21 Card Detect Register
Table 377. Card Detect Register (CDETECT, address 0x4000 4050) bit description
Bit

Symbol

Description

Reset
value

0

CARD_DETECT

Card detect. 0 represents presence of card.

0

31:1

-

Reserved

-

22.6.22 Write Protect Register
Table 378. Write Protect Register (WRTPRT, address 0x4000 4054) bit description

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Bit

Symbol

Description

Reset
value

0

WRITE_PROTECT

Write protect. 1 represents write protection.

0

31:1

-

Reserved

-

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22.6.23 Transferred CIU Card Byte Count Register
Table 379. Transferred CIU Card Byte Count Register (TCBCNT, address 0x4000 405C) bit description
Bit

Symbol

Description

Reset
value

31:0

TRANS_CARD_BYTE_ Number of bytes transferred by CIU unit to card.
COUNT
Register should be read only after data transfer completes; during data transfer,
register returns 0.

0

22.6.24 Transferred Host to BIU-FIFO Byte Count Register
Table 380. Transferred Host to BIU-FIFO Byte Count Register (TBBCNT, address 0x4000 4060) bit description
Bit

Symbol

Description

Reset
value

31:0

TRANS_FIFO_BYTE_ Number of bytes transferred between Host/DMA memory and BIU FIFO.
COUNT

0

22.6.25 Debounce Count Register
Table 381. Debounce Count Register (DEBNCE, address 0x4000 4064) bit description
Bit

Symbol

Description

Reset
value

23:0

DEBOUNCE_
COUNT

Number of host clocks (SD_CLK) used by debounce
filter logic for card detect; typical debounce time is
5-25 ms.

0xFFFFFF

31:24

-

Reserved

22.6.26 Hardware Reset
Table 382. Hardware Reset (RST_N, address 0x4000 4078) bit description
Bit

Symbol

Description

Reset
value

0

CARD_RESET

Hardware reset.
1 - Active mode
0 - Reset

1

Toggles state on SD_RST pin. This bit causes the
card to enter pre-idle state, which requires it to be
re-initialized.

31:1

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22.6.27 Bus Mode Register
Table 383. Bus Mode Register (BMOD, address 0x4000 4080) bit description
Bit

Symbol

Value

0

SWR

Software Reset. When set, the DMA Controller resets all its internal registers. SWR 0
is read/write. It is automatically cleared after 1 clock cycle.

1

FB

Fixed Burst. Controls whether the AHB Master interface performs fixed burst
transfers or not. When set, the AHB will use only SINGLE, INCR4, INCR8 or
INCR16 during start of normal burst transfers. When reset, the AHB will use
SINGLE and INCR burst transfer operations. FB is read/write.

0

6:2

DSL

Descriptor Skip Length. Specifies the number of HWord/Word/Dword to skip
between two unchained descriptors. This is applicable only for dual buffer
structure. DSL is read/write.

0

7

DE

SD/MMC DMA Enable. When set, the SD/MMC DMA is enabled. DE is read/write.

10:8

PBL

Programmable Burst Length. These bits indicate the maximum number of beats to 0
be performed in one SD/MMC DMA transaction. The SD/MMC DMA will always
attempt to burst as specified in PBL each time it starts a Burst transfer on the host
bus. The permissible values are 1, 4, 8, 16, 32, 64, 128 and 256. This value is the
mirror of MSIZE of FIFOTH register. In order to change this value, write the
required value to FIFOTH register. This is an encode value as follows.Transfer unit
is 32 bit. PBL is a read-only value.
0x0

1 transfer

0x1

4 transfers

0x2

8 transfers

0x3

16 transfers

0x4

32 transfers

0x5

64 transfers

0x6

128 transfers

0x7
31:11

Description

Reset
value

256 transfers

-

Reserved

22.6.28 Poll Demand Register
Table 384. Poll Demand Register (PLDMND, address 0x4000 4084) bit description

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Bit

Symbol

Description

31:0

PD

Poll Demand. If the OWN bit of a descriptor is not set, the FSM
goes to the Suspend state. The host needs to write any value
into this register for the SD/MMC DMA state machine to resume
normal descriptor fetch operation. This is a write only register.
PD bit is write-only.

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22.6.29 Descriptor List Base Address Register
Table 385. Descriptor List Base Address Register (DBADDR, address 0x4000 4088) bit
description
Bit

Symbol

Description

Reset
value

31:0

SDL

Start of Descriptor List. Contains the base address of the First
Descriptor. The LSB bits [1:0] are ignored and taken as all-zero
by the SD/MMC DMA internally. Hence these LSB bits are
read-only.

0

22.6.30 Internal DMAC Status Register
Table 386. Internal DMAC Status Register (IDSTS, address 0x4000 408C) bit description

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Bit

Symbol Description

Reset
value

0

TI

Transmit Interrupt. Indicates that data transmission is finished for a
descriptor. Writing a 1 clears this bit.

0

1

RI

Receive Interrupt. Indicates the completion of data reception for a
descriptor. Writing a 1 clears this bit.

0

2

FBE

Fatal Bus Error Interrupt. Indicates that a Bus Error occurred
(IDSTS[12:10]). When this bit is set, the DMA disables all its bus
accesses. Writing a 1 clears this bit.

0

3

-

Reserved

4

DU

Descriptor Unavailable Interrupt. This bit is set when the descriptor 0
is unavailable due to OWN bit = 0 (DES0[31] =0). Writing a 1 clears
this bit.

5

CES

Card Error Summary. Indicates the status of the transaction to/from
the card; also present in RINTSTS. Indicates the logical OR of the
following bits:
EBE - End Bit Error
RTO - Response Time-out/Boot Ack Time-out
RCRC - Response CRC
SBE - Start Bit Error
DRTO - Data Read Time-out/BDS time-out
DCRC - Data CRC for Receive
RE - Response Error
Writing a 1 clears this bit.

7:6

-

Reserved

8

NIS

Normal Interrupt Summary. Logical OR of the following: IDSTS[0] - 0
Transmit Interrupt IDSTS[1] - Receive Interrupt Only unmasked bits
affect this bit. This is a sticky bit and must be cleared each time a
corresponding bit that causes NIS to be set is cleared. Writing a 1
clears this bit.

9

AIS

Abnormal Interrupt Summary. Logical OR of the following: IDSTS[2] 0
- Fatal Bus Interrupt IDSTS[4] - DU bit Interrupt IDSTS[5] - Card
Error Summary Interrupt Only unmasked bits affect this bit. This is a
sticky bit and must be cleared each time a corresponding bit that
causes AIS to be set is cleared. Writing a 1 clears this bit.

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Table 386. Internal DMAC Status Register (IDSTS, address 0x4000 408C) bit description
Bit

Symbol Description

Reset
value

12:10 EB

Error Bits. Indicates the type of error that caused a Bus Error. Valid
only with Fatal Bus Error bit (IDSTS[2]) set. This field does not
generate an interrupt.
001 - Host Abort received during transmission
010 - Host Abort received during reception
Others: Reserved EB is read-only.

0

16:13 FSM

DMAC state machine present state.
0 - DMA_IDLE
1 - DMA_SUSPEND
2 - DESC_RD
3 - DESC_CHK
4 - DMA_RD_REQ_WAIT
5 - DMA_WR_REQ_WAIT
6 - DMA_RD
7 - DMA_WR
8 - DESC_CLOSE
This bit is read-only.

0

31:17 -

Reserved

22.6.31 Internal DMAC Interrupt Enable Register
Table 387. Internal DMAC Interrupt Enable Register (IDINTEN, address 0x4000 4090) bit
description

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Bit

Symbol

Description

Reset
value

0

TI

Transmit Interrupt Enable. When set with Normal Interrupt
Summary Enable, Transmit Interrupt is enabled. When
reset, Transmit Interrupt is disabled.

0

1

RI

Receive Interrupt Enable. When set with Normal Interrupt
Summary Enable, Receive Interrupt is enabled. When
reset, Receive Interrupt is disabled.

0

2

FBE

Fatal Bus Error Enable. When set with Abnormal Interrupt
Summary Enable, the Fatal Bus Error Interrupt is enabled.
When reset, Fatal Bus Error Enable Interrupt is disabled.

0

3

-

Reserved

4

DU

Descriptor Unavailable Interrupt. When set along with
Abnormal Interrupt Summary Enable, the DU interrupt is
enabled.

5

CES

Card Error summary Interrupt Enable. When set, it enables 0
the Card Interrupt summary.

7:6

-

Reserved

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Table 387. Internal DMAC Interrupt Enable Register (IDINTEN, address 0x4000 4090) bit
description
Bit

Symbol

Description

Reset
value

8

NIS

Normal Interrupt Summary Enable. When set, a normal
interrupt is enabled. When reset, a normal interrupt is
disabled. This bit enables the following bits: IDINTEN[0] Transmit Interrupt IDINTEN[1] - Receive Interrupt

0

9

AIS

Abnormal Interrupt Summary Enable. When set, an
abnormal interrupt is enabled. This bit enables the
following bits: IDINTEN[2] - Fatal Bus Error Interrupt
IDINTEN[4] - DU Interrupt IDINTEN[5] - Card Error
Summary Interrupt

0

31:10

-

Reserved

22.6.32 Current Host Descriptor Address Register
Table 388. Current Host Descriptor Address Register (DSCADDR, address 0x4000 4094) bit
description
Bit

Symbol

Description

Reset
value

31:0

HDA

Host Descriptor Address Pointer. Cleared on reset. Pointer
updated by IDMAC during operation. This register points to
the start address of the current descriptor read by the
SD/MMC DMA.

0

22.6.33 Current Buffer Descriptor Address Register
Table 389. Current Buffer Descriptor Address Register (BUFADDR, address 0x4000 4098) bit
description
Bit

Symbol

Description

Reset
value

31:0

HBA

Host Buffer Address Pointer. Cleared on Reset. Pointer updated 0
by IDMAC during operation. This register points to the current
Data Buffer Address being accessed by the SD/MMC DMA.

22.7 Functional description
22.7.1 Power/pull-up control and card detection unit
Signal pull-up resistors can be enabled for the SD pins via the SCU by enabling the
pull-up for the pads. The approximate pull-up value for a pin is about 50 kOhm. For
designs that need to support legacy MMC cards in open-drain mode, an external pull-up
controlled
with a general purpose output and FET will be needed for the CMD line.
Slot power can be controlled with the SD_POW pin and the SD_VOLT[2:0] pins. It is
recommended that the slot power regulator is enabled and disabled via the SD_POW pin,
which can be directly controlled with bit 0 of the Power enable register (PWREN).
Use of the SD_VOLT[2:0] pins is optional and not needed in a design with a single power
supply sourcing the card slot.
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The card detection signal is debounced based on the number of blocks specified in the
Debounce Count Register (DEBNCE). When this signal is connected to the card detect
pin of the card slot, then CDETECT register's bit 0 state will be filtered by the number of
debounce cycles specified in DEBNCE. This guarantees that interrupt related to the card
detect signal are debounced before occurring.

22.7.2 Auto-Stop
The auto-stop command helps to send an exact number of data bytes using a stream read
or write for the MMC, and a multiple-block read or write for SD memory transfer for SD
cards. The module internally generates a stop command and is loaded in the command
path when the SEND_AUTO_STOP bit is set in the Command register.
The software should set the SEND_AUTO_STOP bit according to details listed in table
below:
Table 390. SEND_AUTO_STOP bit

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Card
Type

Transfer Type

Byte
SEND_AUTO_
Count STOP bit set

Comments

MMC

Stream read

0

No

Open-ended stream

MMC

Stream read

>0

Yes

Auto-stop after all bytes transfer

MMC

Stream read

0

No

Open-ended stream

MMC

Stream read

>0

Yes

Auto-stop after all bytes transfer

MMC

Single-block read

>0

No

Byte count = 0 is illegal

MMC

Single-block write

>0

No

Byte count = 0 is illegal

MMC

Multiple-block read

0

No

Open-ended multiple block
Pre-defined multiple block

MMC

Multiple-block read

>0

Yes[1]

MMC

Multiple-block write

0

No

Open-ended multiple block

MMC

Multiple-block write

>0

Yes[1]

Pre-defined multiple block

SDMEM

Single-block read

>0

No

Byte count = 0 is illegal

SDMEM

Single-block write

>0

No

Byte count = 0 is illegal

SDMEM

Multiple-block read

0

No

Open-ended multiple block

SDMEM

Multiple-block read

>0

Yes

Auto-stop after all bytes transfer

SDMEM

Multiple-block write

0

No

Open-ended multiple block

SDMEM

Multiple-block write

>0

Yes

Auto-stop after all bytes transfer

SDIO

Single-block read

>0

No

Byte count = 0 is illegal

SDIO

Single-block write

>0

No

Byte count = 0 is illegal

SDIO

Multiple-block read

0

No

Open-ended multiple block

SDIO

Multiple-block read

>0

No

Pre-defined multiple block

SDIO

Multiple-block write

0

No

Open-ended multiple block

SDIO

Multiple-block write

>0

No

Pre-defined multiple block

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[1]

The condition under which the transfer mode is set to block transfer and byte_count is equal to block size is
treated as a single-block data transfer command for both MMC and SD cards. If byte_count = n
block_size (n = 2, 3, …), the condition is treated as a predefined multiple-block data transfer command. In
the case of an MMC card, the cpu software can perform a predefined data transfer in two ways: 1) Issue the
CMD23 command before issuing CMD18/CMD25 commands to the card – in this case, issue
CMD18/CMD25 commands without setting the send_auto_stop bit. 2) Issue CMD18/CMD25 commands
without issuing CMD23 command to the card, with the send_auto_stop bit set. In this case, the
multiple-block data transfer is terminated by an internally-generated auto-stop command after the
programmed byte count.

The following list conditions for the auto-stop command.

• Stream read for MMC card with byte count greater than 0 - The Module generates an
internal stop command and loads it into the command path so that the end bit of the
stop command is sent out when the last byte of data is read from the card and no
extra data byte is received. If the byte count is less than 6 (48 bits), a few extra data
bytes are received from the card before the end bit of the stop command is sent.

• Stream write for MMC card with byte count greater than 0 - The Module generates an
internal stop command and loads it into the command path so that the end bit of the
stop command is sent when the last byte of data is transmitted on the card bus and no
extra data byte is transmitted. If the byte count is less than 6 (48 bits), the data path
transmits the data last in order to meet the above condition.

• Multiple-block read memory for SD card with byte count greater than 0 - If the block
size is less than 4 (single-bit data bus), 16 (4-bit data bus), or 32 (8-bit data bus), the
auto-stop command is loaded in the command path after all the bytes are read.
Otherwise, the top command is loaded in the command path so that the end bit of the
stop command is sent after the last data block is received.

• Multiple-block write memory for SD card with byte count greater than 0 - If the block
size is less than 3 (single-bit data bus), 12 (4-bit data bus), or 24 (8-bit data bus), the
auto-stop command is loaded in the command path after all data blocks are
transmitted. Otherwise, the stop command is loaded in the command path so that the
end bit of the stop command is sent after the end bit of the CRC status is received.

• Precaution for cpu software during auto-stop - Whenever an auto-stop command is
issued, the cpu software should not issue a new command to the Module until the
auto-stop is sent by the Module and the data transfer is complete. If the cpu issues a
new command during a data transfer with the auto-stop in progress, an auto-stop
command may be sent after the new command is sent and its response is received;
this can delay sending the stop command, which transfers extra data bytes. For a
stream write, extra data bytes are erroneous data that can corrupt the card data. If the
cpu wants to terminate the data transfer before the data transfer is complete, it can
issue a stop or abort command, in which case the Module does not generate an
auto-stop command.

22.7.3 Software/hardware restrictions
Only one data transfer command should be issued at one time. For CE-ATA devices, if
CE-ATA device interrupts are enabled (nIEN=0), only one RW_MULTIPLE_BLOCK
command (RW_BLK) should be issued; no other commands (including a new RW_BLK)
should be issued before the Data Transfer. Over status is set for the outstanding
RW_BLK.

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Before issuing a new data transfer command, the software should ensure that the card is
not busy due to any previous data transfer command. Before changing the card clock
frequency, the software must ensure that there are no data or command transfers in
progress.
To avoid glitches in the card clock outputs (cclk_out), the software should use the
following steps when changing the card clock frequency:
1. Update the Clock Enable register to disable all clocks. To ensure completion of any
previous command before this update, send a command to the CIU to update the
clock registers by setting:
– start_cmd bit
– "update clock registers only" bits
– "wait_previous data complete" bit
Wait for the CIU to take the command by polling for 0 on the start_cmd bit.
2. Set the start_cmd bit to update the Clock Divider and/or Clock Source registers, and
send a command to the CIU in order to update the clock registers; wait for the CIU to
take the command.
3. Set start_cmd to update the Clock Enable register in order to enable the required
clocks and send a command to the CIU to update the clock registers; wait for the CIU
to take the command.
In non-DMA mode, while reading from a card, the Data Transfer Over (RINTSTS[3])
interrupt occurs as soon as the data transfer from the card is over. There still could be
some data left in the FIFO, and the RX_WMark interrupt may or may not occur, depending
on the remaining bytes in the FIFO. Software should read any remaining bytes upon
seeing the Data Transfer Over (DTO) interrupt. In DMA mode while reading from a card,
the DTO interrupt occurs only after all the FIFO data is flushed to memory by the DMA
Interface unit.
While writing to a card in DMA mode, if an undefined-length transfer is selected by setting
the Byte Count register to 0, the DMA logic will likely request more data than it will send to
the card, since it has no way of knowing at which point the software will stop the transfer.
The DMA request stops as soon as the DTO is set by the CIU.
If the software issues a controller_reset command by setting control register bit[0] to 1, all
the CIU state machines are reset; the FIFO is not cleared. The DMA sends all remaining
bytes to the cpu. In addition to a card-reset, if a FIFO reset is also issued, then:

• Any pending DMA transfer on the bus completes correctly
• DMA data read is ignored
• Write data is unknown (x)
Additionally, if dma_reset is also issued, any pending DMA transfer is abruptly terminated.
The DMA controller channel should also be reset and reprogrammed.
If any of the previous data commands do not properly terminate, then the software should
issue the FIFO reset in order to remove any residual data, if any, in the FIFO. After
asserting the FIFO reset, you should wait until this bit is cleared.

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One data-transfer requirement between the FIFO and cpu is that the number of transfers
should be a multiple of the FIFO data width (F_DATA_WIDTH), which is 32. So if you want
to write only 15 bytes to an SD/MMC/CE-ATA card (BYTCNT), the cpu should write 16
bytes to the FIFO or program the DMA to do 16-byte transfers, if DMA mode is enabled.
The software can still program the Byte Count register to only 15, at which point only 15
bytes will be transferred to the card. Similarly, when 15 bytes are read from a card, the
cpu should still read all 16 bytes from the FIFO.
It is recommended that you do not change the FIFO threshold register in the middle of
data transfers.

22.7.4 Programming sequence
22.7.4.1 Initialization
Once the power and clocks are stable, reset_n should be asserted (active-low) for at least
two clocks of clk or cclk_in, whichever is slower. The reset initializes the registers, ports,
FIFO-pointers, DMA interface controls, and state-machines in the design. After power-on
reset, the software should do the following:
1. After power on reset, configure the SD/MMC pins using the SFSP registers in the
syscon block (Table 190).
2. Set masks for interrupts by clearing appropriate bits in the Interrupt Mask register
@0x024. Set the global int_enable bit of the Control register @0x00. It is
recommended that you write 0xffff_ffff to the Raw Interrupt register @0x044 in order
to clear any pending interrupts before setting the int_enable bit.
3. Enumerate card stack - Each card is enumerated according to card type; for details,
refer to "Enumerated Card Stack". For enumeration, you should restrict the clock
frequency to 400 KHz in accordance with SD_MMC/CE-ATA standards.
4. Changing clock. The cards operate at a maximum of 26 MHz (at maximum of 52 MHz
in high-speed mode).
5. Set other IP parameters, which normally do not need to be changed with every
command, with a typical value such as time-out values in cclk_out according to
SD_MMC/CE-ATA specifications.
ResponseTimeOut = 0x40
DataTimeOut = highest of one of the following:
– (10  ((TAAC Fop) + (100 NSAC))
– Cpu FIFO read/write latency from FIFO empty/full
FIFO threshold value in bytes in the FIFOTH register @0x04C. Typically, the
threshold value can be set to half the FIFO depth (=32); that is:
– RX_WMark = (FIFO_DEPTH/2) - 1;
– TX_WMark = FIFO_DEPTH/2
6. If the software decides to handle the interrupts provided by the IP core, you should
create another thread to handle interrupts.

22.7.4.2 Enumerated Card Stack
The card stack does the following:

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•
•
•
•

Enumerates all connected cards
Sets the RCA for the connected cards
Reads card-specific information
Stores card-specific information locally

Enumerate_Card_Stack - Enumerates the card connected on the module. The card can
be of the type MMC, CE-ATA, SD, or SDIO. All types of SDIO cards are supported; that is,
SDIO_IO_ONLY, SDIO_MEM_ONLY, and SDIO_COMBO cards. The enumeration
sequence includes the following steps:
1. Check if the card is connected.
2. Clear the bits in the card_type register. Clear the register bit for a 1-bit, 4-bit, or 8-bit
bus width.
3. Identify the card type; that is, SD, MMC, or SDIO.
– Send CMD5 first. If a response is received, then the card is SDIO
– If not, send ACMD41; if a response is received, then the card is SD.
– Otherwise, the card is an MMC or CE-ATA
4. Enumerate the card according to the card type.
Use a clock source with a frequency = Fod (that is, 400 KHz) and use the following
enumeration command sequence:
– SD card - Send CMD0, ACMD41, CMD2, CMD3.
– SDHC card - send CMD0, SDCMD8, ACMD41, CMD2, CMD3
– SDIO - Send CMD5; if the function count is valid, CMD3. For the SDIO memory
section, follow the same commands as for the SD card.
– MMC - Send CMD0, CMD1, CMD2, CMD3
5. Identify the MMC/CE-ATA device.
– Selecting ATA mode for a CE-ATA device.
– Cpu should query the byte 504 (S_CMD_SET) of EXT_CSD register by sending
CMD8. If bit 4 is set to 1, then the device supports ATA mode.
– If ATA mode is supported, the cpu should select the ATA mode by setting the ATA
bit (bit 4) of the EXT_CSD register slice 191(CMD_SET) to activate the ATA
command set for use. The cpu selects the command set using the SWITCH
(CMD6) command.
– The current mode selected is shown in byte 191 of the EXT_CSD register.
If the device does not support ATA mode, then the device can be an MMC device
or a CE-ATA v1.0 device.
– Send RW_REG; if a response is received and the response data contains CE-ATA
signature, the device is a CE-ATA device.
– Otherwise the device is an MMC card.
6. You can change the card clock frequency after enumeration.

22.7.4.3 Clock Programming
The clock programming has to be done in the CGU. The cclk_in has to be equal to the
cclk_out. Therefore the registers that support this have to be:
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• CLKDIV @0x08 = 0x0 (bypass of clock divider).
• CLKSRC @0x0C = 0x0
• CLKENA @0x10 =0x0 or 0x1. This register enables or disables clock for the card and
enables low-power mode, which automatically stops the clock to a card when the card
is idle for more than 8 clocks.
The Module loads each of these registers only when the start_cmd bit and the
Update_clk_regs_only bit in the CMD register are set. When a command is successfully
loaded, the Module clears this bit, unless the Module already has another command in the
queue, at which point it gives an HLE (Hardware Locked Error); for details on HLEs, refer
to "Error Handling".
Software should look for the start_cmd and the Update_clk_regs_only bits, and should
also set the wait_prvdata_complete bit to ensure that clock parameters do not change
during data transfer. Note that even though start_cmd is set for updating clock registers,
the Module does not raise a command_done signal upon command completion.

22.7.4.4 No-Data Command With or Without Response Sequence
To send any non-data command, the software needs to program the CMD register @0x2C
and the CMDARG register @0x28 with appropriate parameters. Using these two
registers, the Module forms the command and sends it to the command bus. The Module
reflects the errors in the command response through the error bits of the RINTSTS
register.
When a response is received - either erroneous or valid - the Module sets the
command_done bit in the RINTSTS register. A short response is copied in Response
Register0, while a long response is copied to all four response registers @0x30, 0x34,
0x38, and 0x3C. The Response3 register bit 31 represents the MSB, and the Response0
register bit 0 represents the LSB of a long response.
For basic commands or non-data commands, follow these steps:
1. Program the Command register @0x28 with the appropriate command argument
parameter.
2. Program the Command register @0x2C with the settings in Table 391.
3. Wait for command acceptance by cpu. The following happens when the command is
loaded into the Module:
– Module accepts the command for execution and clears the start_cmd bit in the
CMD register, unless one command is in process, at which point the Module can
load and keep the second command in the buffer.
– If the Module is unable to load the command - that is, a command is already in
progress, a second command is in the buffer, and a third command is attempted then it generates an HLE (hardware-locked error).
– Check if there is an HLE.
– Wait for command execution to complete. After receiving either a response from a
card or response time-out, the Module sets the command_done bit in the RINTSTS
register. Software can either poll for this bit or respond to a generated interrupt.

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– Check if response_timeout error, response_CRC error, or response error is set.
This can be done either by responding to an interrupt raised by these errors or by
polling bits 1, 6, and 8 from the RINTSTS register @0x44. If no response error is
received, then the response is valid. If required, the software can copy the
response from the response registers @0x30-0x3C.
Software should not modify clock parameters while a command is being executed.
Table 391. CMD register settings for No-Data Command
Name

Value

start_cmd

1

Comment

update_clock_ registers_only

0

No clock parameters update command

card_number

0

Card number in use. Only zero is possible
because one card is support.

Data_expected

0

No data command.

Send_initialization

0

Can be 1, but only for card reset commands,
such as CMD0

stop_abort_cmd

0

Can be 1 for commands to stop data transfer,
such as CMD12

Cmd_index

Command index

Response_length

0

Can be 1 for R2 (long) response

Response_expect

1

Can be 0 for commands with no response; for
example, CMD0, CMD4,
CMD15, and so on

User-selectable
Wait_prvdata_complete

1

Before sending command on command line,
cpu should wait for
completion of any data command in process,
if any (recommended to
always set this bit, unless the current
command is to query status or stop
data transfer when transfer is in progress)

Check_response_crc

1

0 – Do not check response CRC
1 – Check response CRC
Some of command responses do not return
valid CRC bits. Software should disable CRC
checks for those commands in order to
disable CRC checking by controller.

22.7.4.5 Data Transfer Commands
Data transfer commands transfer data between the memory card and the Module. To send
a data command, the Module needs a command argument, total data size, and block size.
Software can receive or send data through the FIFO.
Before a data transfer command, software should confirm that the card is not busy and is
in a transfer state, which can be done using the CMD13 and CMD7 commands,
respectively.

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For the data transfer commands, it is important that the same bus width that is
programmed in the card should be set in the card type register @0x18. Therefore, in order
to change the bus width, you should always use the following supplied APIs as
appropriate for the type of card:

• Set_SD_Mode() - SD/SDIO card
• Set_HSmodeSettings() - HSMMC card
The Module generates an interrupt for different conditions during data transfer, which are
reflected in the RINTSTS register @0x44 as:
1. Data_Transfer_Over (bit 3) - When data transfer is over or terminated. If there is a
response time-out error, then the Module does not attempt any data transfer and the
"Data Transfer Over" bit is never set.
2. Transmit_FIFO_Data_request (bit 4) - FIFO threshold for transmitting data was
reached; software is expected to write data, if available, in FIFO.
3. Receive_FIFO_Data_request (bit 5) - FIFO threshold for receiving data was reached;
software is expected to read data from FIFO.
4. Data starvation by Cpu time-out (bit 10) - FIFO is empty during transmission or is full
during reception. Unless software writes data for empty condition or reads data for full
condition, the Module cannot continue with data transfer. The clock to the card has
been stopped.
5. Data read time-out error (bit 9) - Card has not sent data within the time-out period.
6. Data CRC error (bit 7) - CRC error occurred during data reception.
7. Start bit error (bit 13) - Start bit was not received during data reception.
8. End bit error (bit 15) - End bit was not received during data reception or for a write
operation; a CRC error is indicated by the card.
Conditions 6, 7, and 8 indicate that the received data may have errors. If there was a
response time-out, then no data transfer occurred.

22.7.4.6 Single-Block or Multiple-Block Read
Steps involved in a single-block or multiple-block read are:
1. Write the data size in bytes in the BYTCNT register @0x20.
2. Write the block size in bytes in the BLKSIZ register @0x1C. The Module expects data
from the card in blocks of size BLKSIZ each.
3. Program the CMDARG register @0x28 with the data address of the beginning of a
data read. Program the Command register with the parameters listed in Table 392.
For SD and MMC cards, use CMD17 for a single-block read and CMD18 for a
multiple-block read. For SDIO cards, use CMD53 for both single-block and
multiple-block transfers.
After writing to the CMD register, the Module starts executing the command; when the
command is sent to the bus, the command_done interrupt is generated.
4. Software should look for data error interrupts; that is, bits 7, 9, 13, and 15 of the
RINTSTS register. If required, software can terminate the data transfer by sending a
STOP command.

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5. Software should look for Receive_FIFO_Data_request and/or data starvation by cpu
time-out conditions. In both cases, the software should read data from the FIFO and
make space in the FIFO for receiving more data.
6. When a Data_Transfer_Over interrupt is received, the software should read the
remaining data from the FIFO.
Table 392. CMD register settings for Single-block or Multiple-block Read
Name

Value

Comment

start_cmd

1

update_clock_ registers_only

0

No clock parameters update command

card_number

0

Card number in use. Only zero is
possible because one card is support.

Data_expected

1

Send_initialization

0

Can be 1, but only for card reset
commands, such as CMD0

stop_abort_cmd

0

Can be 1 for commands to stop data
transfer, such as CMD12

Send_auto_stop

0/1

-

Transfer_mode

0

Block transfer

Read_write

0

Read from card

Cmd_index

Command index

Response_length

0

Can be 1 for R2 (long) response

Response_expect

1

Can be 0 for commands with no
response; for example, CMD0, CMD4,
CMD15, and so on

User-selectable
Wait_prvdata_complete

1

Before sending command on
command line, cpu should wait for
completion of any data command in
process, if any (recommended to
always set this bit, unless the current
command is to query status or stop
data transfer when transfer is in
progress)

Check_response_crc

1

0 – Do not check response CRC
1 – Check response CRC
Some of command responses do not
return valid CRC bits. Software should
disable CRC checks for those
commands in order to disable CRC
checking by controller.

22.7.4.7 Single-Block or Multiple-Block Write
Steps involved in a single-block or multiple-block write are:
1. Write the data size in bytes in the BYTCNT register @0x20.
2. Write the block size in bytes in the BLKSIZ register @0x1C; the Module sends data in
blocks of size BLKSIZ each.
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3. Program CMDARG register @0x28 with the data address to which data should be
written.
4. Write data in the FIFO; it is usually best to start filling data the full depth of the FIFO.
5. Program the Command register with the parameters listed in Table 393. For SD and
MMC cards, use CMD24 for a single-block write and CMD25 for a multiple-block
write. For SDIO cards, use CMD53 for both single-block and multiple-block transfers.
After writing to the CMD register, Module starts executing a command; when the
command is sent to the bus, a command_done interrupt is generated.
6. Software should look for data error interrupts; that is, for bits 7, 9, and 15 of the
RINTSTS register. If required, software can terminate the data transfer by sending the
STOP command.
7. Software should look for Transmit_FIFO_Data_request and/or time-out conditions
from data starvation by the cpu. In both cases, the software should write data into the
FIFO.
8. When a Data_Transfer_Over interrupt is received, the data command is over. For an
open-ended block transfer, if the byte count is 0, the software must send the STOP
command. If the byte count is not 0, then upon completion of a transfer of a given
number of bytes, the Module should send the STOP command, if necessary.
Completion of the AUTO-STOP command is reflected by the Auto_command_done
interrupt - bit 14 of the RINTSTS register. A response to AUTO_STOP is stored in
RESP1 @0x34.
Table 393. CMD register settings for Single-block or Multiple-block write
Name

Value

Comments

start_cmd

1

update_clock_ registers_only

0

No clock parameters update command

card_number

0

Card number in use. Only zero is
possible because one card is support.

Data_expected

1

Send_initialization

0

Can be 1, but only for card reset
commands, such as CMD0

stop_abort_cmd

0

Can be 1 for commands to stop data
transfer, such as CMD12

Send_auto_stop

0/1

-

Transfer_mode

0

Block transfer

Read_write

1

Write to card

Cmd_index

Command
index

Response_length

0

Can be 1 for R2 (long) response

Response_expect

1

Can be 0 for commands with no
response; for example, CMD0, CMD4,
CMD15, and so on

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Table 393. CMD register settings for Single-block or Multiple-block write
Name

Value

Comments

1

Before sending command on
command line, cpu should wait for

User-selectable
Wait_prvdata_complete

completion of any data command in
process, if any (recommended to
always set this bit, unless the current
command is to query status or stop
data transfer when transfer is in
progress)
Check_response_crc

1

0 – Do not check response CRC
1 – Check response CRC
Some of command responses do not
return valid CRC bits. Software should
disable CRC checks for those
commands in order to disable CRC
checking by controller.

22.7.4.8 Stream Read
A stream read is like the block read mentioned in "Single-Block or Multiple-Block Read",
except for the following bits in the Command register:
transfer_mode = 1; //Stream transfer
cmd_index = CMD20;
A stream transfer is allowed for only a single-bit bus width.

22.7.4.9 Stream Write
A stream write is exactly like the block write mentioned in "Single-Block or Multiple-Block
Write", except for the following bits in the Command register:

• transfer_mode = 1;//Stream transfer
• cmd_index = CMD11;
In a stream transfer, if the byte count is 0, then the software must send the STOP
command. If the byte count is not 0, then when a given number of bytes completes a
transfer, the Module sends the STOP command. Completion of this AUTO_STOP
command is reflected by the Auto_command_done interrupt. A response to an
AUTO_STOP is stored in the RESP1 register @0x34.
A stream transfer is allowed for only a single-bit bus width.

22.7.4.10 Sending Stop or Abort in Middle of Transfer
The STOP command can terminate a data transfer between a memory card and the
Module, while the ABORT command can terminate an I/O data transfer for only the
SDIO_IOONLY and SDIO_COMBO cards.

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• Send STOP command - Can be sent on the command line while a data transfer is in
progress; this command can be sent at any time during a data transfer. For
information on sending this command, refer to "No-Data Command With or Without
Response Sequence".
You can also use an additional setting for this command in order to set the Command
register bits (5-0) to CMD12 and set bit 14 (stop_abort_cmd) to 1. If stop
stop_abort_cmd is not set to 1, the user stopped a data transfer. Reset bit 13 of the
Command register (wait_prvdata_complete) to 0 in order to make the Module send
the command at once, even though there is a data transfer in progress.
– Send ABORT command - Can be used with only an SDIO_IOONLY or
SDIO_COMBO card. To abort the function that is transferring data, program the
function number in ASx bits (CCCR register of card, address 0x06, bits (0-2) using
CMD52.
This is a non-data command. For information on sending this command, refer to
"No-Data Command With or Without Response Sequence".
Program the CMDARG register @0x28 with the appropriate command argument
parameters listed in Table 394.
– Program the Command register using the command index as CMD52. Similar to
the STOPcommand, set bit 14 of the Command register (stop_abort_cmd) to 1,
which must be done in order to inform the Module that the user aborted the data
transfer. Reset bit 13 (wait_prvdata_complete) of the Command register to 0 in
order to make the Module send the command at once, even though a data transfer
is in progress.
– Wait for command_transfer_over.
– Check response (R5) for errors.

• During an open-ended card write operation, if the card clock is stopped because the
FIFO is empty, the software must first fill the data into the FIFO and start the card
clock before issuing a stop/abort command to the card.
Table 394. Parameters for CMDARG register
Bits

Contents

Value

31

R/W flag

1

30-28

Function number

0, for CCCR access

27

RAW flag

1, if needed to read after write

26

Don’t care

-

25-9

Register address

0x06

8

Don’t care

-

7-0

Write data

Function number to be aborted

22.7.5 Suspend or Resume Sequence
In an SDIO card, the data transfer between an I/O function and the Module can be
temporarily halted using the SUSPEND command; this may be required in order to
perform a high-priority data transfer with another function. When desired, the data transfer
can be resumed using the RESUME command.

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The following functions can be implemented by programming the appropriate bits in the
CCCR register (Function 0) of the SDIO card. To read from or write to the CCCR register,
use the CMD52 command.
1. SUSPEND data transfer - Non-data command.
– Check if the SDIO card supports the SUSPEND/RESUME protocol; this can be
done through the SBS bit in the CCCR register @0x08 of the card.
Check if the data transfer for the required function number is in process; the
function number that is currently active is reflected in bits 0-3 of the CCCR register
@0x0D. Note that if the BS bit (address 0xc::bit 0) is 1, then only the function
number given by the FSx bits is valid.
To suspend the transfer, set BR (bit 2) of the CCCR register @0x0C.
Poll for clear status of bits BR (bit 1) and BS (bit 0) of the CCCR @0x0C. The BS
(Bus Status) bit is 1 when the currently-selected function is using the data bus; the
BR (Bus Release) bit remains 1 until the bus release is complete. When the BR
and BS bits are 0, the data transfer from the selected function has been
suspended.
During a read-data transfer, the Module can be waiting for the data from the card. If
the data transfer is a read from a card, then the Module must be informed after the
successful completion of the SUSPEND command. The Module then resets the
data state machine and comes out of the wait state. To accomplish this, set
abort_read_data (bit 8) in the Control register.
Wait for data completion. Get pending bytes to transfer by reading the TCBCNT
register @0x5C.
2. RESUME data transfer - This is a data command.
– Check that the card is not in a transfer state, which confirms that the bus is free for
data transfer.
If the card is in a disconnect state, select it using CMD7. The card status can be
retrieved in response to CMD52/CMD53 commands.
Check that a function to be resumed is ready for data transfer; this can be
confirmed by reading the RFx flag in CCCR @0x0F. If RF = 1, then the function is
ready for data transfer.
To resume transfer, use CMD52 to write the function number at FSx bits (0-3) in the
CCCR register @0x0D. Form the command argument for CMD52 and write it in
CMDARG @0x28; bit values are listed in Table 395.
– Write the block size in the BLKSIZ register @0x1C; data will be transferred in units
of this block size.
Write the byte count in the BYTCNT register @0x20. This is the total size of the
data; that is, the remaining bytes to be transferred. It is the responsibility of the
software to handle the data.
Program Command register; similar to a block transfer. For details, refer to
"Single-Block or Multiple-Block Read" and "Single-Block or Multiple-Block Write".
When the Command register is programmed, the command is sent and the
function resumes data transfer. Read the DF flag (Resume Data Flag). If it is 1,
then the function has data for the transfer and will begin a data transfer as soon as
the function or memory is resumed. If it is 0, then the function has no data for the
transfer.
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If the DF flag is 0, then in case of a read, the Module waits for data. After the data
time-out period, it gives a data time-out error.
Table 395. Parameters for CMDARG register
Bits

Contents

Value

31

R/W flag

1

30-28

Function number

0, for CCCR access

27

RAW flag

1, read after write

26

Don’t care

-

25-9

Register address

0x0D

8

Don’t care

-

7-0

Write data

Function number to be aborted

22.7.5.1 Read_Wait Sequence
Read_wait is used with only the SDIO card and can temporarily stall the data
transfer-either from function or memory-and allow the cpu to send commands to any
function within the SDIO device. The cpu can stall this transfer for as long as required.
The Module provides the facility to signal this stall transfer to the card. The steps for doing
this are:
1. Check if the card supports the read_wait facility; read SRW (bit 2) of the CCCR
register @0x08. If this bit is 1, then all functions in the card support the read_wait
facility. Use CMD52 to read this bit.
2. If the card supports the read_wait signal, then assert it by setting the read_wait (bit 6)
in the CTRL register @0x00.
3. Clear the read_wait bit in the CTRL register.

22.7.5.2 CE-ATA Data Transfer Commands
This section describes the CE-ATA data transfer commands. For information on the basic
settings and interrupts generated for different conditions, refer to "Data Transfer
Commands".
22.7.5.2.1

Reset and Device Recovery
Before starting CE-ATA operations, the cpu should perform an MMC reset and
initialization procedure. The cpu and device should negotiate the MMC TRAN state
(defined by the MultiMedia Card System Specification) before the device enters the MMC
TRAN state. The cpu should follow the existing MMC Card enumeration procedure in
order to negotiate the MMC
TRAN state. After completing normal MMC reset and initialization procedures, the cpu
should query the initial ATA Task File values using RW_REG/CMD39.
By default, the MMC block size is 512 bytes-indicated by bits 1:0 of the srcControl register
inside the CE-ATA device. The cpu can negotiate the use of a 1KB or 4KB MMC block
size. The device indicates MMC block sizes that it can support through the srcCapabilities
register; the cpu reads this register in order to negotiate the MMC block size. Negotiation
is complete when the cpu controller writes the MMC block size into the srcControl register
bits 1:0 of the device.

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22.7.5.2.2

ATA Task File Transfer
ATA task file registers are mapped to addresses 0x00h-0x10h in the MMC register space.
RW_REG is used to issue the ATA command, and the ATA task file is transmitted in a
single RW_REG MMC command sequence.
The cpu software stack should write the task file image to the FIFO before setting the
CMDARG and CMD registers. The cpu processor then sets the address and byte count in
the CMDARG-offset 0x28 in the BIU register space-before setting the CMD (offset 0x2C)
register bits.
For RW_REG, there is no command completion signal from the CE-ATA device
ATA Task File Transfer Using RW_MULTIPLE_REGISTER (RW_REG)
This command involves data transfer between the CE-ATA device and the Module. To
send a data command, the Module needs a command argument, total data size, and
block size. Software can receive or send data through the FIFO.
Steps involved in an ATA Task file transfer (read or write) are:
1. Write the data size in bytes in the BYTCNT register @0x20.
2. Write the block size in bytes in the BLKSIZ register @0x1C; the Module expects a
single block transfer.
3. Program the CMDARG register @0x28 with the beginning register address.
You should program the CMDARG, CMD, BLKSIZ, and BYTCNT registers according to
the following tables.

• Program the Command Argument (CMDARG) register as shown below.
Table 396. Parameters for CMDARG register
Bits

Contents

Value

31

R/W flag

1 (write) or 0 (read)

30-24

Reserved

0

23:18

Starting register
0
address for
read/write; Dword
aligned

17:16

Register address; 0
Dword aligned

15-8

Reserved; bits
cleared to 0 by
CPU

7:2

Number of bytes 16
to read/write;
integral number of
Dwords

1:0

Byte count in
0
integral number of
Dwords

0

• Program the Command (CMD) register as shown below.
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Table 397. CMD register settings
Name

Value

Comment

start_cmd

1

Css_expect

0

Command Completion Signal is not
expected

Read_ceata_device

0/1

1 – If RW_BLK or RW_REG read

update_clock_ registers_only

0

No clock parameters update command

card_number

0

Card number in use. Only zero is
possible because one card is support.

Data_expected

1

Send_initialization

0

stop_abort_cmd

0

Send_auto_stop

0

Transfer_mode

0

Block transfer

Read_write

0/1

0 read from card,

Can be 1, but only for card reset
commands, such as CMD0

1 - Write to card
Cmd_index

Command index

Response_length

0

Response_expect

1

User-selectable
Wait_prvdata_complete

1

0 – Sends command immediately
1 – Sends command after previous data
transfer over

Check_response_crc

1

0 – Do not check response CRC
1 – Check response CRC

• Program the block size (BLKSIZ) register as shown below.
Table 398. BLKSIZ register
Bits

Value

Comment

31:16

0

Reserved bits as zeroes (0)

15:0

16

For accessing entire task file (16, 8-bit
registers); block size of 16 bytes

• Program the Byte Count (BYTCNT) register as shown below.
Table 399. BYTCNT register

22.7.5.2.3

Bits

Value

Comment

31:0

16

For accessing entire task file(16, 8 bit
registers); byte count value of 16 is
used with the block size set to 16

ATA Payload Transfer Using RW_MULTIPLE_BLOCK (RW_BLK)
This command involves data transfer between the CE-ATA device and the Module. To
send a data command, the Module needs a command argument, total data size, and
block size. Software can receive or send data through the FIFO.
Steps involved in an ATA payload transfer (read or write) are:

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1. Write the data size in bytes in the BYTCNT register @0x20.
2. Write the block size in bytes in the BLKSIZ register @0x1C. The Module expects a
single/multiple block transfer.
3. Program the CMDARG register @0x28 to indicate the Data Unit Count.
You should program the CMDARG, CMD, BLKSIZ, and BYTCNT registers according
to the following tables.
– Program the Command Argument (CMDARG) register as shown below.
Table 400. Parameters for CMDARG register
Bits

Contents

Value

31

R/W flag

1 (write) or 0 (read)

30-24

Reserved

0

23:16

Reserved

0

15:8

Data Count Unit
[15:8]

Data count

1:0

Data Count Unit
[7:0]

Data count

• Program the Command (CMD) register as shown below.
Table 401. CMD register settings
Name

Value

Comment

start_cmd

1

-

Css_expect

1

Command Completion Signal is expected;
set for RW_BLK if interrupts are enabled in
CE-ATA device, nIEN = 0

Read_ceata_device

0/1

1 – If RW_BLK or RW_REG read

update_clock_ registers_only

0

No clock parameters update command

card_number

0

Card number in use. Only zero is possible
because one card is support.

Data_expected

1

Send_initialization

0

stop_abort_cmd

0

Send_auto_stop

0

Transfer_mode

0

Block transfer

Read_write

0/1

0 read from card,

Can be 1, but only for card reset commands,
such as CMD0

1 - Write to card
Cmd_index

Command index

Response_length

0

Response_expect

1

User-selectable
Wait_prvdata_complete

1

0 – Sends command immediately
1 – Sends command after previous data
transfer over

Check_response_crc

1

0 – Do not check response CRC
1 – Check response CRC

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• Program the block size (BLKSIZ) register as shown below.
Table 402. BLKSIZ register
Bits

Value

Comment

31:16

0

Reserved bits as zeroes (0)

15:0

512, 1024, 4096

MMC block size can be 512, 1024, or 4096
bytes as negotiated by CPU

• Program the Byte Count (BYTCNT) register as shown below.
Table 403. BYTCNT register

22.7.5.2.4

Bits

Value

Comment

31:0

N  block_size

byte_count should be integral multiple of
block size; for ATA media access commands,
byte count should be multiple of 4KB. (N 
block_size = X  4KB, where N and X are
integers)

Sending Command Completion Signal Disable
While waiting for the Command Completion Signal (CCS) for an outstanding RW_BLK,
the cpu can send a Command Completion Signal Disable (CCSD).

• Send CCSD - Module sends CCSD to the CE-ATA device if the send_ccsd bit is set in
the CTRL register; this bit is set only after a response is received for the RW_BLK.

• Send internal Stop command - Send internally generated STOP (CMD12) command
after sending the CCSD pattern. If send_auto_stop_ccsd bit is also set when the
controller is programmed to send the CCSD pattern, the Module sends the internally
generated STOP command on the CMD line. After sending the STOP command, the
Module sets the Auto Command Done bit in the RINTSTS register.
22.7.5.2.5

Recovery after Command Completion Signal Time-out
If time-out happened while waiting for Command Completion Signal (CCS), the cpu needs
to send Command Completion Signal Disable (CCSD) followed by a STOP command to
abort the pending ATA command. The cpu can program the Module to send internally
generated STOP command after sending the CCSD pattern

• Send CCSD - Set the send_ccsd bit in the CTRL register.
• Reset bit 13 of the Command register (wait_prvdata_complete) to 0 in order to make
the Module send the command at once, even though there is a data transfer in
progress.

• Send internal STOP command - Set send_auto_stop_ccsd bit in the CTRL register,
which programs the cpu controller to send the internally generated STOP command.
After sending the STOP command, the Module sets the Auto Command Done bit in
the RINTSTS register.
22.7.5.2.6

Reduced ATA Command Set
It is necessary for the CE-ATA device to support the reduced ATA command subset. The
following details discuss this reduced command set.

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• IDENTIFY DEVICE - Returns 512-byte data structure to the cpu that describes
device-specific information and capabilities. The cpu issues the IDENTIFY DEVICE
command only if the MMC block size is set to 512 bytes; any other MMC block size
has indeterminate results.
The cpu issues RW_REG for the ATA command, and the data is retrieved through
RW_BLK.
The cpu controller uses the following settings while sending RW_REG for the IDENTIFY
DEVICE ATA command. The following lists the primary bit

• CMD register setting - data_expected field set to 0
• CMDARG register settings:
– Bit [31] set to 0
– Bits [7:2] set to 128.

• Task file settings:
– Command field of the ATA task file set to ECh
– Reserved fields of the task file cleared to 0

• BLKSIZ register bits [15:0] and BYTCNT register - Set to 16
The cpu controller uses the following settings for data retrieval (RW_BLK):\

• CMD register settings:
– ccs_expect set to 1
– data_expected set to 1

• CMDARG register settings:
– Bit [31] set to 0 (Read operation)
Data Count set to 1 (16'h0001)

• BLKSIZ register bits [15:0] and BYTCNT register - Set to 512 IDENTIFY DEVICE can
be aborted as a result of the CPU issued CMD12.
– READ DMA EXT - Reads a number of logical blocks of data from the device using
the Data-In data transfer protocol. The cpu uses RW_REG to issue the ATA
command and RW_BLK for the data transfer.
– WRITE DMA EXT - Writes a number of logical blocks of data to the device using
the Data-Out data transfer protocol. The cpu uses RW_REG to issue the ATA
command and RW_BLK for the data transfer.
– STANDBY IMMEDIATE - No data transfer (RW_BLK) is expected for this ATA
command, which causes the device to immediately enter the most aggressive
power management mode that still retains internal device context.

• CMD Register setting - data_expected field set to 0
CMDARG register settings:
– Bit [31] set to 1
– Bits [7:2] set to 4

• Task file settings:
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– Command field of the ATA task file set to E0h
– Reserved fields of the task file cleared to 0

• BLKSIZ register bits [15:0] and BYTCNT register - Set to 16
– FLUSH CACHE EXT - No data transfer (RW_BLK) is expected for this ATA
command. For devices that buffer/cache written data, the FLUSH CACHE EXT
command ensures that buffered data is written to the device media. For devices
that do not buffer written data, FLUSH CACHE EXT returns a success status. The
cpu issues RW_REG for the ATA command, and the status is retrieved through
CMD39/RW_REG; there can be error status for this ATA command, in which case
fields other than the status field of the ATA task file are valid.

• The CPU uses the following settings while sending the RW_REG for STANDBY
IMMEDIATE ATA command:

•
•
•
•
•
•
•
•

CMD register setting - data_expected field set to 0
CMDARG register settings:
Bit [31] set to 1
Bits [7:2] set to 4
Task file settings:
Command field of the ATA task file set to EAh
Reserved fields of the task file cleared to 0
BLKSIZ register bits [15:0] and BYTCNT register - Set to 16

22.7.5.3 Controller/DMA/FIFO Reset Usage
Communication with the card involves the following:

• Controller - Controls all functions of the Module.
• FIFO - Holds data to be sent or received.
• DMA - If DMA transfer mode is enabled, then transfers data between system memory
and the FIFO.

• Controller reset - Resets the controller by setting the controller_reset bit (bit 0) in the
CTRL register; this resets the CIU and state machines, and also resets the
BIU-to-CIU interface. Since this reset bit is self-clearing, after issuing the reset, wait
until this bit is cleared.

• FIFO reset - Resets the FIFO by setting the fifo_reset bit (bit 1) in the CTRL register;
this resets the FIFO pointers and counters of the FIFO. Since this reset bit is
self-clearing, after issuing the reset, wait until this bit is cleared.
DMA reset - Resets the internal DMA controller logic by setting the dma_reset bit (bit
2) in the CTRL register, which abruptly terminates any DMA transfer in process. Since
this reset bit is self-clearing, after issuing the reset, wait until this bit is cleared.
The following are recommended methods for issuing reset commands:

• Non-DMA transfer mode - Simultaneously sets controller_reset and fifo_reset; clears
the RAWINTS register @0x44 using another write in order to clear any resultant
interrupt.

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• Generic DMA mode - Simultaneously sets controller_reset, fifo_reset, and dma_reset;
clears the RAWINTS register @0x44 by using another write in order to clear any
resultant interrupt. If a "graceful" completion of the DMA is required, then it is
recommended to poll the status register to see whether the dma request is 0 before
resetting the DMA interface control and issuing an additional FIFO reset.

• In DMA transfer mode, even when the FIFO pointers are reset, if there is a DMA
transfer in progress, it could push or pop data to or from the FIFO; the DMA itself
completes correctly. In order to clear the FIFO, the software should issue an
additional FIFO reset and clear any FIFO underrun or overrun errors in the RAWINTS
register caused by the DMA transfers after the FIFO was reset.

22.7.5.4 Error Handling
The Module implements error checking; errors are reflected in the RAWINTS register
@0x44 and can be communicated to the software through an interrupt, or the software
can poll for these bits. Upon power-on, interrupts are disabled (int_enable in the CTRL
register is 0), and all the interrupts are masked (bits 0-31 of the INTMASK register; default
is 0). Error handling:

• Response and data time-out errors - For response time-out, software can retry the
command. For data time-out, the Module has not received the data start bit - either for
the first block or the intermediate block - within the time-out period, so software can
either retry the whole data transfer again or retry from a specified block onwards. By
reading the contents of the TCBCNT later, the software can decide how many bytes
remain to be copied.

• Response errors - Set when an error is received during response reception. In this
case, the response that copied in the response registers is invalid. Software can retry
the command.

• Data errors - Set when error in data reception are observed; for example, data CRC,
start bit not found, end bit not found, and so on. These errors could be set for any
block-first block, intermediate block, or last block. On receipt of an error, the software
can issue a STOP or ABORT command and retry the command for either whole data
or partial data.

• Hardware locked error - Set when the Module cannot load a command issued by
software. When software sets the start_cmd bit in the CMD register, the Module tries
to load the command. If the command buffer is already filled with a command, this
error is raised. The software then has to reload the command.

• FIFO underrun/overrun error - If the FIFO is full and software tries to write data in the
FIFO, then an overrun error is set. Conversely, if the FIFO is empty and the software
tries to read data from the FIFO, an underrun error is set. Before reading or writing
data in the FIFO, the software should read

• the fifo_empty or fifo_full bits in the Status register.
• Data starvation by cpu time-out - Raised when the Module is waiting for software
intervention to transfer the data to or from the FIFO, but the software does not transfer
within the stipulated time-out period. Under this condition and when a read transfer is
in process, the software

• Should read data from the FIFO and create space for further data reception. When a
transmit operation is in process, the software should fill data in the FIFO in order to
start transferring data to the card.
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• CRC Error on Command - If a CRC error is detected for a command, the CE-ATA
device does not send a response, and a response time-out is expected from the
Module. The ATA layer is notified that an MMC transport layer error occurred.

• Write operation - Any MMC Transport layer error known to the device causes an
outstanding ATA command to be terminated. The ERR bits are set in the ATA status
registers and the appropriate error code is sent to the ATA Error register.

• If nIEN=0, then the Command Completion Signal (CCS) is sent to the cpu.
If device interrupts are not enabled (nIEN=1), then the device completes the entire Data
Unit Count if the cpu controller does not abort the ongoing transfer.
During a multiple-block data transfer, if a negative CRC status is received from the device,
the data path signals a data CRC error to the BIU by setting the data CRC error bit in the
RINTSTS register. It then continues further data transmission until all the bytes are
transmitted.

• Read operation - If MMC transport layer errors are detected by the cpu controller, the
cpu completes the ATA command with an error status.
The cpu controller can issue a Command Completion Signal Disable (CCSD) followed by
a STOP TRANSMISSION (CMD12) to abort the read transfer. The cpu can also transfer
the entire Data Unit Count bytes without aborting the data transfer.

22.7.6 DMA descriptors
The SD/MMC DMA controller uses the following descriptor structures:

• Dual-Buffer Structure – The distance between two descriptors is determined by the
Skip Length value programmed in the Descriptor Skip Length (DSL) field of the Bus
Mode Register (BMOD).

• Chain Structure – Each descriptor points to a unique buffer and the next descriptor.

Data Buffer 1

Descriptor A
Data Buffer 2

Data Buffer 1

Descriptor B
Data Buffer 2

Data Buffer 1

Descriptor C
Data Buffer 2

Fig 57. Dual-buffer descriptor structure

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Data Buffer

Descriptor A

Data Buffer

Descriptor B

Data Buffer

Descriptor C

Fig 58. Chain descriptor structure

22.7.6.1 SD/MMC DMA descriptors
22.7.6.1.1

SD/MMC DMA descriptor DESC0
The DES0 descriptor contains control and status information.
Table 404. SD/MMC DMA DESC0 descriptor
Bit

Symbol Description

0

-

Reserved

1

DIC

Disable Interrupt on Completion
When set, this bit will prevent the setting of the TI/RI bit of the IDMAC Status
Register (IDSTS) for the data that ends in the buffer pointed to by this descriptor.

2

LD

Last Descriptor
When set, this bit indicates that the buffers pointed to by this descriptor are the
last buffers of the data.

3

FS

First Descriptor
When set, this bit indicates that this descriptor contains the first buffer of the
data. If the size of the first buffer is 0, next Descriptor contains the beginning of
the data.

4

CH

Second Address Chained
When set, this bit indicates that the second address in the descriptor is the Next
Descriptor address rather than the second buffer address. When this bit is set,
BS2 (DES1[25:13]) should be all zeros.

5

ER

End of Ring
When set, this bit indicates that the descriptor list reached its final descriptor.
The IDMAC returns to the base address of the list, creating a Descriptor Ring.
This is meaningful for only a dual-buffer descriptor structure.

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Table 404. SD/MMC DMA DESC0 descriptor
Bit

Symbol Description

29:6

-

Reserved

30

CES

Card Error Summary
These error bits indicate the status of the transaction to or from the card. These
bits are also present in RINTSTS Indicates the logical OR of the following bits:

•
•
•
•
•
•
•
31

22.7.6.1.2

OWN

EBE: End Bit Error
RTO: Response Time-out
RCRC: Response CRC
SBE: Start Bit Error
DRTO: Data Read Time-out
DCRC: Data CRC for Receive
RE: Response Error

When set, this bit indicates that the descriptor is owned by the SD/MMC DMA.
When this bit is reset, it indicates that the descriptor is owned by the Host. The
SD/MMC DMA clears this bit when it completes the data transfer.

SD/MMC DMA descriptor DESC1
The DES1 descriptor contains the buffer size.
Table 405. SD/MMC DMA DESC1 descriptor
Bit

Symbol Description

12:0

BS1

Buffer 1 Size
Indicates the data buffer byte size, which must be a multiple of 4 bytes. In the
case where the buffer size is not a multiple of 4, the resulting behavior is
undefined. If this field is 0, the DMA ignores this buffer and proceeds to the next
descriptor in case of a chain structure, or to the next buffer in case of a
dual-buffer structure.
Remark: If there is only one descriptor and only one buffer to be programmed,
use only the Buffer 1 and not Buffer 2.

25:13 BS2

Buffer 2 Size
These bits indicate the second data buffer byte size. The buffer size must be a
multiple of 4. Otherwise, the resulting behavior is undefined. This field is not
valid if DES0[4] is set.

31:26 -

22.7.6.1.3

Reserved

SD/MMC DMA descriptor DESC2
The DES2 descriptor contains the address pointer to the data buffer;
Table 406. SD/MMC DMA DESC2 descriptor
Bit

Symbol Description

31:0

BAP1

Buffer Address Pointer 1
These bits indicate the physical address of the first data buffer. The SD/MMC
DMA ignores DES2 [1:0], corresponding to the bus width of 64/32/16, internally.

22.7.6.1.4

SD/MMC DMA descriptor DESC3
The DES3 descriptor contains the address pointer to the next descriptor if the present
descriptor is not the last descriptor in a chained descriptor structure or the second buffer
address for a dual-buffer structure.

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Table 407. SD/MMC DMA DESC3 descriptor
Bit

Symbol Description

31:0

BAP2

Buffer Address Pointer 2/ Next Descriptor Address
These bits indicate the physical address of the second buffer when the
dual-buffer structure is used. If the Second Address Chained (DES0[4]) bit is
set, then this address contains the pointer to the physical memory where the
Next Descriptor is present.
If this is not the last descriptor, then the Next Descriptor address pointer must be
bus-width aligned (DES3[1:0] = 0 , internally the LSBs are ignored).

22.7.6.2 Initialization
For the SD/MMC DMA initialization, follow these steps:
1. Write to the Bus Mode Register (BMOD) to set the Host bus access parameters.
2. Write to the Interrupt Enable Register (IDINTEN) to mask unnecessary interrupt
causes.
3. The software driver creates either the Transmit or the Receive descriptor list. Then it
writes to Descriptor List Base Address Register (DBADDR), providing the IDMAC with
the starting address of the list.
4. The SD/MMC DMA engine attempts to acquire descriptors from the descriptor lists.

22.7.6.3 Host bus burst access
The SD/MMC DMA attempts to execute fixed-length burst transfers on the AHB Master
interface if configured using the FB bit of the IDMAC Bus Mode register. The maximum
burst length is indicated and limited by the PBL field. The descriptors are always accessed
in the maximum possible burst-size for the 16-bytes to be read: 16*8/bus-width.
The SD/MMC DMA initiates a data transfer only when sufficient space to accommodate
the configured burst is available in the FIFO or the number of bytes to the end of data,
when less than the configured burst-length. The SD/MMC DMA indicates the start
address and the number of transfers required to the AHB Master Interface. When the AHB
Interface is configured for fixed-length bursts, then it transfers data using the best
combination of INCR4/8/16 and SINGLE transactions. Otherwise, in no fixed-length
bursts, it transfers data using INCR (undefined length) and SINGLE transactions.

22.7.6.4 Host data buffer alignment
The transmit and receive data buffers in host memory must be 32-bit aligned.

22.7.6.5 Buffer size calculations
The driver knows the amount of data to transmit or receive. For transmitting to the card,
the IDMAC transfers the exact number of bytes to the FIFO, indicated by the buffer size
field of DES1.
If a descriptor is not marked as last - LS bit of DES0 - then the corresponding buffers of
the descriptor are full, and the amount of valid data in a buffer is accurately indicated by its
buffer size field. If a descriptor is marked as last, then the buffer cannot be full, as
indicated by the buffer size in DES1. The driver is aware of the number of locations that
are valid in this case.

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22.7.6.6 Transmission
The SD/MMC transmission occurs as follows:
1. The Host sets up the Descriptor (DES0-DES3) for transmission and sets the OWN bit
(DES0[31]). The Host also prepares the data buffer.
2. The Host programs the write data command in the CMD register in BIU.
3. The Host will also program the required transmit threshold level (TX_WMark field in
FIFOTH register).
4. The SD/MMC DMA determines that a write data transfer needs to be done as a
consequence of step 2.
5. The SD/MMC DMA engine fetches the descriptor and checks the OWN bit. If the
OWN bit is not set, it means that the host owns the descriptor. In this case the
SD/MMC DMA enters suspend state and asserts the Descriptor Unable interrupt in
the SD/MMC DMA status register (IDSTS). In such a case, the host needs to release
the SD/MMC DMA by writing any value to the poll demand register.
6. It will then wait for Command Done (CD) bit and no errors from BIU which indicates
that a transfer can be done.
7. The SD/MMC DMA engine will now wait for a DMA interface request from BIU. This
request will be generated based on the programmed transmit threshold value. For the
last bytes of data which can’t be accessed using a burst, SINGLE transfers are
performed on AHB Master Interface.
8. The SD/MMC DMA fetches the Transmit data from the data buffer in the Host memory
and transfers to the FIFO for transmission to card.
9. When data spans across multiple descriptors, the SD/MMC DMA will fetch the next
descriptor and continue with its operation with the next descriptor. The Last Descriptor
bit in the descriptor indicates whether the data spans multiple descriptors or not.
10. When data transmission is complete, status information is updated in SD/MMC DMA
status register (IDSTS) by setting Transmit Interrupt, if enabled. Also, the OWN bit is
cleared by the SD/MMC DMA by performing a write transaction to DES0.

22.7.6.7 Reception
The SD/MMC reception occurs as follows:
1. The Host sets up the Descriptor (DES0-DES3) for reception, sets the OWN
(DES0[31]).
2. The Host programs the read data command in the CMD register in BIU.
3. The Host will program the required receive threshold level (RX_WMark field in
FIFOTH register).
4. The SD/MMC DMA determines that a read data transfer needs to be done as a
consequence of step 2.
5. The SD/MMC DMA engine fetches the descriptor and checks the OWN bit. If the
OWN bit is not set, it means that the host owns the descriptor. In this case the DMA
enters suspend state and asserts the Descriptor Unable interrupt in the SD/MMC
DMA status register (IDSTS). In such a case, the host needs to release the SD/MMC
DMA by writing any value to the poll demand register.
6. It will then wait for Command Done (CD) bit and no errors from BIU which indicates
that a transfer can be done.
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Chapter 22: LPC43xx/LPC43Sxx SD/MMC interface

7. The SD/MMC DMA engine will now wait for a DMA interface request (dw_dma_req)
from BIU. This request will be generated based on the programmed receive threshold
value. For the last bytes of data which can’t be accessed using a burst, SINGLE
transfers are performed on AHB.
8. The SD/MMC DMA fetches the data from the FIFO and transfer to Host memory.
9. When data spans across multiple descriptors, the SD/MMC DMA will fetch the next
descriptor and continue with its operation with the next descriptor. The Last Descriptor
bit in the descriptor indicates whether the data spans multiple descriptors or not.
10. When data reception is complete, status information is updated in SD/MMC DMA
status register (IDSTS) by setting Receive Interrupt, if enabled. Also, the OWN bit is
cleared by the SD/MMC DMA by performing a write transaction to DES0.

22.7.6.8 Interrupts
Interrupts can be generated as a result of various events. The SD/MMC DMA Status
Register (IDSTS) contains all the bits that might cause an interrupt. The SD/MMC DMA
Interrupt Enable Register (IDINTEN) contains an Enable bit for each of the events that can
cause an interrupt.
There are two groups of summary interrupts - Normal and Abnormal - as outlined in Status
Register (IDSTS). Interrupts are cleared by writing a 1 to the corresponding bit position.
When all the enabled interrupts within a group are cleared, the corresponding summary
bit is cleared. When both the summary bits are cleared, the interrupt signal is de-asserted.
Interrupts are not queued and if the interrupt event occurs before the driver has
responded to it, no additional interrupts are generated. For example, Receive Interrupt
(IDSTS[1]) indicates that one or more data was transferred to the Host buffer.
An interrupt is generated only once for simultaneous, multiple events. The driver must
scan the SD/MMC DMA Status Register for the interrupt cause.
Remark: The final interrupt (int) signal from created is a logical OR of the interrupt from
BIU and SD/MMC DMA.

22.7.6.9 Abort
When the host issues CMD12 when a data transfer on the card data lines is in progress,
the FSM closes the present descriptor after completing the transfer of data until a DTO
interrupt is asserted. Once an abort command is issued, the DMA performs single burst
transfers:
1. When the host issues CMD12 when a data transfer on the card data lines is in
progress, the FSM closes the present descriptor after completing the transfer of data
until a DTO interrupt is asserted. Once an abort command is issued, the DMAC
performs single burst transfers.
2. For a card read, the SD/MMC DMA keeps popping data from FIFO and writes to the
host memory until a DTO interrupt is generated. This is required since DTO interrupt
is not generated until and unless all the FIFO data is emptied.
Remark: The following scenarios apply for closing the descriptors:

• In case of an FBE, the current descriptor and the remaining unread descriptors are
not closed by the SD/MMC DMA.
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• In case of a write abort, only the current descriptor during which an abort occurred is
closed by the SD/MMC DMA . The remaining unread descriptors are not closed by the
IDMAC.

• In case of a read abort, the SD/MMC DMA pops the data out of the FIFO and writes
them to the corresponding descriptor data buffers. The remaining unread descriptors
are not closed.

22.7.6.10 FBE scenarios
An FBE occurs due to an AHB error response on the AHB bus. This is a system error, so
the software driver should not perform any further programming to the SD/MMC The only
recovery mechanism from such scenarios is to do one of the following:

• Issue a hard reset by asserting the reset_n signal .
• Do a program controller reset by writing to the CTRL[0] register .
22.7.6.11 FIFO overflow and underflow
During normal data transfer conditions, FIFO overflow and underflow will not occur.
However if there is a programming error, then FIFO overflow/underflow can result. For
example, consider the following scenarios.
For transmit: PBL=4, Tx watermark = 1. For these programming values, if the FIFO has
only one location empty, it issues a dw_dma_req to DMA state machine. Due to PBL
value=4, the DMA performs 4 pushes into the FIFO. This will result in a FIFO overflow
interrupt.
For receive: PBL=4, Rx watermark = 1. For these programming values, if the FIFO has
only one location filled, it issues a dw_dma_req to the DMA state machine. Due to PBL
value=4, the DMA performs 4 pops to the FIFO. This will result in a FIFO underflow
interrupt.
The driver should ensure that the number of bytes to be transferred as indicated in the
descriptor should be a multiple of 4 bytes. For example, if the BYTCNT = 13, the number
of bytes indicated in the descriptor should be 16.

22.7.6.12 Programming of PBL and watermark levels
The SD/MMC DMA performs data transfers depending on the programmed PBL and
threshold values. Table 408 lists the allowed programming values.
Table 408. PBL and watermark levels

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PBL (number of transfers)

Transmit/receive watermark value

1

greater than or equal to 1

4

greater than or equal to 4

8

greater than or equal to 8

16

greater than or equal to 16

32

greater than or equal to 32

64

greater than or equal to 64

128

greater than or equal to 128

256

greater than or equal to 256

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Chapter 23: LPC43xx/LPC43Sxx External Memory Controller
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User manual

23.1 How to read this chapter
The EMC is available on all LPC43xx/LPC43Sxx parts.
The memory and address bus widths depend on package size (see Table 409).
Table 409. EMC pinout for different packages
Function

LBGA256

TFBGA180

TFBGA100

LQFP208

LQFP144

LQFP100

A

EMC_A[23:0]

EMC_A[23:0]

EMC_A[13:0]

EMC_A[23:0]

EMC_A[15:0]

-

D

EMC_D[31:0]

EMC_D[15:0]

EMC_D[7:0]

EMC_D[15:0]

EMC_D[15:0]

-

BLS

EMC_BLS[3:0]

EMC_BLS[3:0]

EMC_BLS0

EMC_BLS[1:0]

EMC_BLS[1:0]

-

CS

EMC_CS[3:0]

EMC_CS[3:0]

EMC_CS0

EMC_CS[3:0]

EMC_CS[1:0]

-

OE

EMC_OE

EMC_OE

EMC_OE

EMC_OE

EMC_OE

-

WE

EMC_WE

EMC_WE

EMC_WE

EMC_WE

EMC_WE

-

CKEOUT

EMC_
CKEOUT[3:0]

EMC_
CKEOUT[1:0]

EMC_
CKEOUT[1:0]

EMC_
CKEOUT[1:0]

EMC_
CKEOUT[1:0]

-

CLK

EMC_CLK[3:0]; EMC_CLK0,
EMC_CLK01,
EMC_CLK3;
EMC_CLK23
EMC_CLK01,
EMC_CLK23

EMC_CLK0,
EMC_CLK3;
EMC_CLK01,
EMC_CLK23

EMC_CLK0,
EMC_CLK3;
EMC_CLK01,
EMC_CLK23

EMC_CLK0,
EMC_CLK3;
EMC_CLK01,
EMC_CLK23

-

DQMOUT

EMC_
DQMOUT[3:0]

EMC_
DQMOUT[1:0]

-

EMC_
DQMOUT[1:0]

EMC_
DQMOUT[1:0]

-

DYCS

EMC_
DYCS[3:0]

EMC_DYCS[1:0] EMC_DYCS[1:0] EMC_DYCS[2:0] EMC_DYCS[1:0] -

CAS

EMC_CAS

EMC_CAS

EMC_CAS

EMC_CAS

EMC_CAS

-

RAS

EMC_RAS

EMC_RAS

EMC_RAS

EMC_RAS

EMC_RAS

-

23.2 Basic configuration
The External Memory Controller is configured as follows:

• See Table 410 for clocking and power control. Two clocks are supported:
– BASE_M4_CLK
– 1/2  BASE_M4_CLK
If the EMC clock EMC_CCLK is configured for 1/2  BASE_M4_CLK, the
CLK_M4_EMC_DIV branch clock must be configured for half-frequency clock
operation in both the CREG6 register (Table 104) and the CCU1
CLK_EMCDIV_CFG register (Table 163).

• All four EMC_CLK clock signals must be configured for all SDRAM devices
independently of their size by selecting the EMC_CLK function and enabling the input
buffer (EZI = 1) in all four SFSCLKn registers in the SCU.

• The EMC is reset by the EMC_RST (reset # 21).
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Chapter 23: LPC43xx/LPC43Sxx External Memory Controller (EMC)

• Program the SDRAM Delay value for the EMC_CLKn lines in the EMCDELAYCLK
register in the SCU block. (See Section 17.4.9.). Add the SDRAM delay for most
SDRAM devices running at frequencies above 96 MHz under typical conditions. Add
the SDRAM delay at any frequency to compensate for variations over temperature.
For details, see the LPC435x data sheets.
Table 410. EMC clocking and power control
Base clock

Branch clock

Operating
frequency

Notes

EMC
BASE_M4_CLK
registers
and EMC
clock
EMC_CCLK

CLK_M4_EMC

up to
204 MHz

The maximum operating
frequency depends on
temperature and voltage
settings and is typically
120 MHz for SDRAM
devices. For details, see
the LPC4350_30_20_10
data sheet.

EMC clock
BASE_M4_CLK
EMC_CCLK
(divided
clock)

CLK_M4_EMC_DIV

up to
204 MHz

This is an alternative
clock option for
EMC_CCLK. This clock
can run at the same
frequency as
BASE_M4_CLK or half
the frequency of
BASE_M4_CLK.

23.3 Features
• 8-bit, 16-bit, and 32-bit wide static memory support with up to four chip selects.
• Asynchronous static memory device support including RAM, ROM, and NOR Flash,
with or without asynchronous page mode.

• Static memory features include:
– Asynchronous page mode read
– Programmable wait states
– Bus turnaround delay
– Output enable and write enable delays
– Extended wait

• 16-bit and 32-bit wide chip select SDRAM memory support with up to four chip selects
and up to 256 MB of data.

• Controller supports 2 kbit, 4 kbit, and 8 kbit row address synchronous memory parts.
That is typical 512 MB, 256 MB, and 128 MB parts, with 4, 8, 16, or 32 data bits per
device.

• Dynamic memory interface support including Single Data Rate SDRAM.
• Dynamic memory self-refresh mode controlled by software.
• Power-saving modes dynamically control EMC_CKEOUT and EMC_CLK to
SDRAMs.

• Low transaction latency.
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Chapter 23: LPC43xx/LPC43Sxx External Memory Controller (EMC)

• Read and write buffers to reduce latency and to improve performance.
• Separate reset domains allow the for auto-refresh through a chip reset if desired.
• Programmable delay elements allow to fine-tune the EMC timing.
Remark: Synchronous static memory devices (synchronous burst mode) are not
supported.

23.4 General description
The LPC43xx External Memory Controller (EMC) is an ARM PrimeCell MultiPort Memory
Controller peripheral offering support for asynchronous static memory devices such as
RAM, ROM and Flash, as well as dynamic memories such as Single Data Rate SDRAM.

EMC

SDRAM interface

EMC_A[23:0]

EMC_WE
AHB SLAVE
REGISTER
INTERFACE

MEMORY
CONTROLLER
STATE
MACHINE

EMC_DYCS[3:0]
EMC_CAS
EMC_RAS

AHB SLAVE
MEMORY
INTERFACE

EMC_DQMOUT[3:0]
EMC_D[31:0] (write)
EMC_CKEOUT[3:0]

CLK_M4_EMC
CLK_M4_EMC_DIV
CLKOUT
CREG6

programmable
delay

EMC_CLK[3:0]

EMCDELAYCLK
DATAIN
FIFO

EMC_D[31:0] (read)

Program the EMC_CLKn delays in the EMCDELAYCLK register in the SYSCON block (Table 202), to adjust the delays for
different SDRAM frequencies and operating conditions.

Fig 59. EMC block diagram (SDRAM)

The EMC has four ports that connect to the bus masters as follows (in order of priority,
1 = top):
1. LCD controller
2. M4 S-bus
3. M4 I/D-bus, M0APP bus
4. Other bus masters including M0SUB bus

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Chapter 23: LPC43xx/LPC43Sxx External Memory Controller (EMC)

Lower priority requests are only serviced when no higher priority requests are active.
Same priority requests are serviced in turn (round-robin arbitration).
Static memories are mapped below 0x2000 0000. This memory area is addressed by the
M4 I/D-bus.
Dynamic memories are mapped above 0x1FFF FFFF. This memory area is addressed by
the M4 S-bus. When the M4 core is executing from SDRAM not much bandwidth is
remaining for lower priority bus masters (M0 and other bus masters except for the LCD
controller). Also see Section 3.6 “AHB Multilayer matrix configuration”.

EMC

SRAM interface

EMC_A[23:0]

EMC_WE

AHB MATRIX

CLK_M4_EMC/
CLK_M4_EMC_DIV

AHB SLAVE
REGISTER
INTERFACE

CLK_M4_EMC/
CLK_M4_EMC_DIV

MEMORY
CONTROLLER
STATE
MACHINE

EMC_OE

EMC_D[31:0] (write)

AHB SLAVE
MEMORY
INTERFACE

EMC_CS[3:0]
EMC_BLS[3:0]

DATAIN
FIFO

EMC_D[31:0] (read)

Fig 60. EMC block diagram (SRAM)

23.5 Memory bank select
Eight independently-configurable memory chip selects are supported:

• Pins EMC_CS3 to EMC_CS0 are used to select static memory devices.
• Pins EMC_DYCS3 to EMC_DYCS0 are used to select dynamic memory devices.
Static memory chip select ranges are each 16 MB in size, while dynamic memory chip
selects cover a range of 256 MB each. Table 411 shows the address ranges of the chip
selects.
Table 411. Memory bank selection

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Chip select pin

Address range

Memory type

Size of range

EMC_CS0

0x1C00 0000 - 0x1CFF FFFF

Static

16 MB

EMC_CS1

0x1D00 0000 - 01DFF FFFF

Static

16 MB

EMC_CS2

0x1E00 0000 - 0x1EFF FFFF

Static

16 MB

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Chapter 23: LPC43xx/LPC43Sxx External Memory Controller (EMC)

Table 411. Memory bank selection
Chip select pin

Address range

Memory type

Size of range

EMC_CS3

0x1F00 0000 - 0x1FFF FFFF

Static

16 MB

EMC_DYCS0

0x2800 0000 - 0x2FFF FFFF

Dynamic

128 MB

EMC_DYCS1

0x3000 0000 - 0x3FFF FFFF

Dynamic

256 MB

EMC_DYCS2

0x6000 0000 - 0x6FFF FFFF

Dynamic

256 MB

EMC_DYCS3

0x7000 0000 - 0x7FFF FFFF

Dynamic

256 MB

23.6 Pin description
Table 412. EMC pin description
Pin function

Direction

Description

EMC_A[23:0]

O

Address bus

EMC_D[31:0]

I/O

Data bus

EMC_BLS[3:0]

O

Byte lane select

EMC_CS[3:0]

O

Static RAM memory bank select

EMC_OE

O

Output enable

EMC_WE

O

Write enable

EMC_CKEOUT[3:0]

O

SDRAM clock enable signals

EMC_CLK[3:0];
EMC_CLK01;
EMC_CLK23

O

SDRAM clock signals

EMC_DQMOUT[3:0]

O

Data mask output to SDRAM memory banks

EMC_DYCS[3:0]

O

SDRAM memory bank select

EMC_CAS

O

Column address strobe

EMC_RAS

O

Row address strobe

23.7 Register description
This chapter describes the EMC registers and provides details required when
programming the microcontroller. The EMC registers are shown in Table 413.
Reset value reflects the data stored in used bits only. It does not include the content of
reserved bits.
Table 413. Register overview: External memory controller (base address 0x4000 5000)
Name

Access Address Description
offset

Reset
value

Reset
value
after
EMC
boot

Reference

CONTROL

R/W

0x000

Controls operation of the memory
controller.

0x3

[1]0x1

Table 414

STATUS

RO

0x004

Provides EMC status information.

0x5

0x5

Table 415

CONFIG

R/W

0x008

Configures operation of the memory
controller.

0

0

Table 416

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Chapter 23: LPC43xx/LPC43Sxx External Memory Controller (EMC)

Table 413. Register overview: External memory controller (base address 0x4000 5000) …continued
Name

Access Address Description
offset

Reset
value

Reset
value
after
EMC
boot

Reference

-

-

-

-

-

0x00C 0x01C

Reserved.

DYNAMICCONTROL

R/W

0x020

Controls dynamic memory operation.

0x6

0x6

Table 417

DYNAMICREFRESH

R/W

0x024

Configures dynamic memory refresh
operation.

0

0

Table 418

DYNAMICREADCONFIG

R/W

0x028

Configures the dynamic memory read
strategy.

0

0

Table 419

-

-

0x02C

Reserved.

-

-

-

DYNAMICRP

R/W

0x030

Selects the precharge command period. 0xF

0xF

Table 420

DYNAMICRAS

R/W

0x034

Selects the active to precharge
command period.

0xF

0xF

Table 421

DYNAMICSREX

R/W

0x038

Selects the self-refresh exit time.

0xF

0xF

Table 422

DYNAMICAPR

R/W

0x03C

Selects the last-data-out to active
command time.

0xF

0xF

Table 423

DYNAMICDAL

R/W

0x040

Selects the data-in to active command
time.

0xF

0xF

Table 424

DYNAMICWR

R/W

0x044

Selects the write recovery time.

0xF

0xF

Table 425

DYNAMICRC

R/W

0x048

Selects the active to active command
period.

0x1F

0x1F

Table 426

DYNAMICRFC

R/W

0x04C

Selects the auto-refresh period.

0x1F

0x1F

Table 427

DYNAMICXSR

R/W

0x050

Selects the exit self-refresh to active
command time.

0x1F

0x1F

Table 428

DYNAMICRRD

R/W

0x054

Selects the active bank A to active bank 0xF
B latency.

0xF

Table 429

DYNAMICMRD

R/W

0x058

Selects the load mode register to active
command time.

0xF

0xF

Table 430

-

R/W

0x05C 0x07C

Reserved.

-

-

-

STATICEXTENDEDWAIT

R/W

0x080

Selects time for long static memory read 0
and write transfers.

0

Table 431

-

R/W

-

Reserved.

-

-

-

DYNAMICCONFIG0

R/W

0x100

Selects the configuration information for 0
dynamic memory chip select 0.

0

Table 432

DYNAMICRASCAS0

R/W

0x104

Selects the RAS and CAS latencies for
dynamic memory chip select 0.

0x303

0x303

Table 434

0x108 0x11C

Reserved.

-

-

-

DYNAMICCONFIG1

R/W

0x120

Selects the configuration information for 0
dynamic memory chip select 1.

0

Table 432

DYNAMICRASCAS1

R/W

0x124

Selects the RAS and CAS latencies for
dynamic memory chip select 1.

0x303

0x303

Table 434

-

-

0x128 0x13C

Reserved.

-

-

-

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Chapter 23: LPC43xx/LPC43Sxx External Memory Controller (EMC)

Table 413. Register overview: External memory controller (base address 0x4000 5000) …continued
Name

Access Address Description
offset

DYNAMICCONFIG2

R/W

0x140

DYNAMICRASCAS2

R/W

-

Reset
value
after
EMC
boot

Reference

Selects the configuration information for 0
dynamic memory chip select 2.

0

Table 432

0x144

Selects the RAS and CAS latencies for
dynamic memory chip select 2.

0x303

0x303

Table 434

-

0x148 0x15C

Reserved.

-

-

-

DYNAMICCONFIG3

R/W

0x160

Selects the configuration information for 0
dynamic memory chip select 3.

0

Table 432

DYNAMICRASCAS3

R/W

0x164

Selects the RAS and CAS latencies for
dynamic memory chip select 3.

0x303

0x303

Table 434

-

-

0x168 0x1FC

Reserved.

-

-

-

STATICCONFIG0

R/W

0x200

Selects the memory configuration for
static chip select 0.

0

0x81

Table 435

STATICWAITWEN0

R/W

0x204

Selects the delay from chip select 0 to
write enable.

0

0

Table 436

STATICWAITOEN0

R/W

0x208

Selects the delay from chip select 0 or
address change, whichever is later, to
output enable.

0

0

Table 437

STATICWAITRD0

R/W

0x20C

Selects the delay from chip select 0 to a 0x1F
read access.

[2]

STATICWAITPAGE0

R/W

0x210

Selects the delay for asynchronous page 0x1F
mode sequential accesses for chip
select 0.

0x1F

Table 439

STATICWAITWR0

R/W

0x214

Selects the delay from chip select 0 to a 0x1F
write access.

0x1F

Table 440

STATICWAITTURN0

R/W

0x218

Selects the number of bus turnaround
cycles for chip select 0.

0xF

0xF

Table 441

-

-

0x21C

Reserved.

-

-

-

STATICCONFIG1

R/W

0x220

Selects the memory configuration for
static chip select 1.

0

0

Table 435

STATICWAITWEN1

R/W

0x224

Selects the delay from chip select 1 to
write enable.

0

0

Table 436

STATICWAITOEN1

R/W

0x228

Selects the delay from chip select 1 or
address change, whichever is later, to
output enable.

0

0

Table 437

STATICWAITRD1

R/W

0x22C

Selects the delay from chip select 1 to a 0x1F
read access.

0x1F

Table 438

STATICWAITPAGE1

R/W

0x230

Selects the delay for asynchronous page 0x1F
mode sequential accesses for chip
select 1.

0x1F

Table 439

STATICWAITWR1

R/W

0x234

Selects the delay from chip select 1 to a 0x1F
write access.

0x1F

Table 440

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0xE Table 438

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Chapter 23: LPC43xx/LPC43Sxx External Memory Controller (EMC)

Table 413. Register overview: External memory controller (base address 0x4000 5000) …continued
Name

Access Address Description
offset

Reset
value

Reset
value
after
EMC
boot

Reference

STATICWAITTURN1

R/W

Selects the number of bus turnaround
cycles for chip select 1.

0xF

0xF

Table 441

0x238

-

-

0x23C

Reserved.

-

-

-

STATICCONFIG2

R/W

0x240

Selects the memory configuration for
static chip select 2.

0

0

Table 435

STATICWAITWEN2

R/W

0x244

Selects the delay from chip select 2 to
write enable.

0

0

Table 436

STATICWAITOEN2

R/W

0x248

Selects the delay from chip select 2 or
address change, whichever is later, to
output enable.

0

0

Table 437

STATICWAITRD2

R/W

0x24C

Selects the delay from chip select 2 to a 0x1F
read access.

0x1F

Table 438

STATICWAITPAGE2

R/W

0x250

Selects the delay for asynchronous page 0x1F
mode sequential accesses for chip
select 2.

0x1F

Table 439

STATICWAITWR2

R/W

0x254

Selects the delay from chip select 2 to a 0x1F
write access.

0x1F

Table 440

STATICWAITTURN2

R/W

0x258

Selects the number of bus turnaround
cycles for chip select 2.

0xF

0xF

Table 441

-

-

0x25C

Reserved.

-

-

-

STATICCONFIG3

R/W

0x260

Selects the memory configuration for
static chip select 3.

0

0

Table 435

STATICWAITWEN3

R/W

0x264

Selects the delay from chip select 3 to
write enable.

0

0

Table 436

STATICWAITOEN3

R/W

0x268

Selects the delay from chip select 3 or
address change, whichever is later, to
output enable.

0

0

Table 437

STATICWAITRD3

R/W

0x26C

Selects the delay from chip select 3 to a 0x1F
read access.

0x1F

Table 438

STATICWAITPAGE3

R/W

0x270

Selects the delay for asynchronous page 0x1F
mode sequential accesses for chip
select 3.

0x1F

Table 439

STATICWAITWR3

R/W

0x274

Selects the delay from chip select 3 to a 0x1F
write access.

0x1F

Table 440

STATICWAITTURN3

R/W

0x278

Selects the number of bus turnaround
cycles for chip select 3.

0xF

Table 441

[1]

The reset value after warm reset for the CONTROL register is 0x0000 0001.

[2]

If booting from EMC, see Section 5.3.4.2 “EMC boot modes”.

0xF

23.7.1 EMC Control register
The Control register is a read/write register that controls operation of the memory
controller. The control bits can be altered during normal operation.

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Table 414. EMC Control register (CONTROL, address 0x4000 5000) bit description
Bit

Symbol

0

E

1

Value Description

1
EMC Enable. Indicates if the EMC is enabled or
disabled.Disabling the EMC reduces power consumption. When
the memory controller is disabled the memory is not refreshed.
The memory controller is enabled by setting the enable bit, or by
reset. This bit must only be modified when the EMC is in idle
state.[1]
0

Disabled

1

Enabled. (POR and warm reset value).

M

2

Reset
value

Address mirror. Indicates normal or reset memory map. On POR, 1
CS1 is mirrored to both CS0 and DYCS0 memory areas.
Clearing the M bit enables CS0 and DYCS0 memory to be
accessed.
0

Normal. Normal memory map.

1

Reset. Reset memory map. Static memory CS1 is mirrored onto
CS0 and DYCS0 (POR reset value).
0
Low-power mode. Indicates normal, or low-power mode.
Entering low-power mode reduces memory controller power
consumption. Dynamic memory is refreshed as necessary. The
memory controller returns to normal functional mode by clearing
the low-power mode bit (L), or by POR.

L

This bit must only be modified when the EMC is in idle state.[1]

31:3
[1]

-

0

Normal. Normal mode (warm reset value).

1

Low-power mode.

-

Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.

-

The external memory cannot be accessed in low-power or disabled state. If a memory access is performed
an AHB error response is generated. The EMC registers can be programmed in low-power and/or disabled
state.

23.7.2 EMC Status register
The read-only Status register provides EMC status information.
Table 415. EMC Status register (STATUS, address 0x4000 5004) bit description
Bit

Symbol

0

B

1

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Value

Description

Reset
value

Busy indicator.
1
This bit is used to ensure that the memory controller enters
the low-power or disabled mode cleanly by determining if
the memory controller is busy or not:
0

Idle. EMC is idle (warm reset value).

1

Busy. EMC is busy performing memory transactions,
commands, auto-refresh cycles, or is in self-refresh mode
(POR reset value).

S

Write buffer status. This bit enables the EMC to enter
low-power mode or disabled mode cleanly:
0

Empty. Write buffers empty (POR reset value)

1

Data. Write buffers contain data.

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Table 415. EMC Status register (STATUS, address 0x4000 5004) bit description
Bit

Symbol

2

SA

31:3 -

Value

Description

Reset
value

Self-refresh acknowledge. This bit indicates the operating
mode of the EMC:

1

0

Normal mode.

1

Self-refresh mode. (POR reset value.)

-

Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.

-

23.7.3 EMC Configuration register
The Config register configures the operation of the memory controller. It is recommended
that this register is modified during system initialization, or when there are no current or
outstanding transactions. This can be ensured by waiting until the EMC is idle, and then
entering low-power, or disabled mode. This register is accessed with one wait state.
Table 416. EMC Configuration register (CONFIG, address 0x4000 5008) bit description
Bit

Symbol

0

EM

Value Description

Reset
value

Endian mode.
0

Little-endian mode. (POR reset value.)

1

Big-endian mode.

0

On power-on reset, the value of the endian bit is 0. All data must
be flushed in the EMC before switching between little-endian and
big-endian modes.
7:1

-

8

-

-

31:9 -

-

Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.

-

Reserved. Always write a 0 to this bit.

0

Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.

-

23.7.4 Dynamic Memory Control register
The DynamicControl register controls dynamic memory operation. The control bits can be
altered during normal operation.
Table 417. Dynamic Control register (DYNAMICCONTROL, address 0x4000 5020) bit
description

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Bit

Symbol

0

CE

Value Description

Reset
value

Dynamic memory clock enable.

0

0

Disabled. Clock enable of idle devices are deasserted to save
power (POR reset value).

1

Enabled. All clock enables are driven HIGH continuously.[1]

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Table 417. Dynamic Control register (DYNAMICCONTROL, address 0x4000 5020) bit
description
Bit

Symbol

1

CS

2

Value Description

Reset
value

Dynamic memory clock control. When clock control is LOW the 1
output clock CLKOUT is stopped when there are no SDRAM
transactions. The clock is also stopped during self-refresh mode.
0

Stop. CLKOUT stops when all SDRAMs are idle and during
self-refresh mode.

1

Run. CLKOUT runs continuously (POR reset value).

SR

Self-refresh request, EMC SREFREQ. By writing 1 to this bit
self-refresh can be entered under software control. Writing 0 to
this bit returns the EMC to normal mode.

1

The self-refresh acknowledge bit in the Status register must be
polled to discover the current operating mode of the EMC.[2]

4:3

-

5

MMC

6

-

8:7

I

0

Normal mode.

1

Self-refresh. Enter self-refresh mode (POR reset value).

-

Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.

-

Memory clock control.

0

0

Enabled. CLKOUT enabled (POR reset value).

1

Disabled. CLKOUT disabled.[3]

-

Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.

-

SDRAM initialization.

00

0x0

Normal. Issue SDRAM NORMAL operation command (POR
reset value).

0x1

Mode. Issue SDRAM MODE command.

0x2

PALL. Issue SDRAM PALL (precharge all) command.

0x3

NOP. Issue SDRAM NOP (no operation) command)

-

-

Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.

-

31:14 -

-

Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.

-

13:9

[1]

Clock enable must be HIGH during SDRAM initialization.

[2]

The memory controller exits from power-on reset with the self-refresh bit HIGH. To enter normal functional
mode set this bit LOW.

[3]

Disabling CLKOUT can be performed if there are no SDRAM memory transactions. When enabled this bit
can be used in conjunction with the dynamic memory clock control (CS) field.

23.7.5 Dynamic Memory Refresh Timer register
This register configures dynamic memory operation. Set up the length of each refresh
cycle according to the EMC_CCLK frequency and the SDRAM specification during
system initialization, or when there are no current or outstanding transactions. This can be
ensured by waiting until the EMC is idle, and then entering low-power, or disabled mode.

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While the EMC is running, the refresh cycle time can be adjusted to compensate for a
changing EMC_CCLK frequency. The EMC controller might skip one refresh cycle in this
case.
Always adjust the refresh cycle time so that the appropriate number of refresh cycles fit in
the refresh time. Both the number of refresh cycles and the refresh time tREF are given in
the SDRAM data sheet.
This register is used for all four dynamic memory chip selects. Therefore the worst case
value for all of the chip selects must be programmed.
Table 418. Dynamic Memory Refresh Timer register (DYNAMICREFRESH, address
0x4000 5024) bit description
Bit

Symbol

Description

Reset
value

10:0

REFRESH

Refresh timer.
Indicates the multiple of 16 EMC_CCLKs between SDRAM refresh
cycles.
0x0 = Refresh disabled (POR reset value).
0x1 - 0x7FF = n x16 = 16n EMC_CCLKs between SDRAM refresh
cycles.
For example:

0

0x1 = 1 x 16 = 16 EMC_CCLKs between SDRAM refresh cycles.
0x8 = 8 x 16 = 128 EMC_CCLKs between SDRAM refresh cycles
31:11 -

Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.

-

For example, for the refresh period of 16 µs, and a EMC_CCLK frequency of 50 MHz, the
following value must be programmed into this register:
(16 x 10-6 x 50 x 106) / 16 = 50 or 0x32
If auto-refresh through warm reset is requested (by setting the EMC_Reset_Disable bit),
the timing of auto-refresh must be adjusted to allow a sufficient refresh rate when the
clock rate is reduced during the wake-up period of a reset cycle. During this period, the
EMC (and all other portions of the chip that are being clocked) run from the IRC oscillator
at 12 MHz. The IRC oscillator frequency must be used as the EMC_CCLK rate for refresh
calculations if auto-refresh through warm reset is requested.
Note: The refresh cycles are evenly distributed. However, there might be slight variations
when the auto-refresh command is issued depending on the status of the memory
controller.

23.7.6 Dynamic Memory Read Configuration register
This register configures the dynamic memory read strategy. This register must be
modified during system initialization with a bit value RD  1. This register is accessed with
one wait state.
Note: This register is used for all four dynamic memory chip selects. Therefore the worst
case value for all of the chip selects must be programmed.
Remark: Choose command delay strategy (RD = 0x1) for SDRAM operation.
See Section 17.4.9 for programming the delay value for the EMC_CLKn delay.
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Table 419. Dynamic Memory Read Configuration register (DYNAMICREADCONFIG, address
0x4000 5028) bit description
Bit

Symbol

1:0

RD

31:2

-

Value Description

Reset
value

Read data strategy.

0x0

0x0

Do not use. POR reset value.

0x1

Command delayed by 1/2 EMC_CCLK.

0x2

Command delayed by 1/2 EMC_CCLK plus one clock cycle.

0x3

Command delayed by1/2 EMC_CCLK plus two clock cycles,

-

Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.

23.7.7 Dynamic Memory Precharge Command Period register
This register enables you to program the precharge command period, tRP. This register
must only be modified during system initialization. This value is normally found in SDRAM
data sheets as tRP. This register is accessed with one wait state.
Note: This register is used for all four dynamic memory chip selects. Therefore the worst
case value for all of the chip selects must be programmed.
Table 420. Dynamic Memory Precharge Command Period register (DYNAMICRP, address
0x4000 5030) bit description
Bit

Symbol

Description

Reset
value

3:0

TRP

Precharge command period.
0x0 - 0xE = n + 1 clock cycles. The delay is in EMC_CCLK cycles.
0xF = 16 clock cycles (POR reset value).

0xF

31:4

-

Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.

-

23.7.8 Dynamic Memory Active to Precharge Command Period register
This register enables you to program the active to precharge command period, tRAS. It is
recommended that this register is modified during system initialization, or when there are
no current or outstanding transactions. This can be ensured by waiting until the EMC is
idle, and then entering low-power, or disabled mode. This value is normally found in
SDRAM data sheets as tRAS. This register is accessed with one wait state.
Note: This register is used for all four dynamic memory chip selects. Therefore the worst
case value for all of the chip selects must be programmed.
Table 421. Dynamic Memory Active to Precharge Command Period register (DYNAMICRAS,
address 0x4000 5034) bit description

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Bit

Symbol Description

Reset
value

3:0

TRAS

Active to precharge command period.
0x0 - 0xE = n + 1 clock cycles. The delay is in EMC_CCLK cycles.
0xF = 16 clock cycles (POR reset value).

0xF

31:4

-

Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.

-

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23.7.9 Dynamic Memory Self Refresh Exit Time register
This register enables you to program the self-refresh exit time, tSREX. It is recommended
that this register is modified during system initialization, or when there are no current or
outstanding transactions. This can be ensured by waiting until the EMC is idle, and then
entering low-power, or disabled mode. This value is normally found in SDRAM data
sheets as tSREX, for devices without this parameter you use the same value as tXSR.
This register is accessed with one wait state.
Note: This register is used for all four dynamic memory chip selects. Therefore the worst
case value for all of the chip selects must be programmed.
Table 422. Dynamic Memory Self Refresh Exit Time register (DYNAMICSREX, address
0x4000 5038) bit description
Bit

Symbol

Description

Reset
value

3:0

TSREX

Self-refresh exit time.
0x0 - 0xE = n + 1 clock cycles. The delay is in EMC_CCLK cycles.
0xF = 16 clock cycles (POR reset value).

0xF

31:4

-

Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.

-

23.7.10 Dynamic Memory Last Data Out to Active Time register
This register enables you to program the last-data-out to active command time, tAPR. It is
recommended that this register is modified during system initialization, or when there are
no current or outstanding transactions. This can be ensured by waiting until the EMC is
idle, and then entering low-power, or disabled mode. This value is normally found in
SDRAM data sheets as tAPR. This register is accessed with one wait state.
Note: This register is used for all four dynamic memory chip selects. Therefore the worst
case value for all of the chip selects must be programmed.
Table 423. Dynamic Memory Last Data Out to Active Time register (DYNAMICAPR, address
0x4000 503C) bit description
Bit

Symbol

Description

Reset
value

3:0

TAPR

Last-data-out to active command time.
0x0 - 0xE = n + 1 clock cycles. The delay is in EMC_CCLK cycles.
0xF = 16 clock cycles (POR reset value).

0xF

31:4

-

Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.

-

23.7.11 Dynamic Memory Data In to Active Command Time register
This register enables you to program the data-in to active command time, tDAL. It is
recommended that this register is modified during system initialization, or when there are
no current or outstanding transactions. This can be ensured by waiting until the EMC is
idle, and then entering low-power, or disabled mode. This value is normally found in
SDRAM data sheets as tDAL, or tAPW. This register is accessed with one wait state.
Note: This register is used for all four dynamic memory chip selects. Therefore the worst
case value for all of the chip selects must be programmed.
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Table 424. Dynamic Memory Data In to Active Command Time register (DYNAMICDAL,
address 0x4000 5040) bit description
Bit

Symbol Description

Reset
value

3:0

TDAL

Data-in to active command.
0x0 - 0xE = n clock cycles. The delay is in EMC_CCLK cycles.
0xF = 15 clock cycles (POR reset value).

0xF

31:4

-

Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.

-

23.7.12 Dynamic Memory Write Recovery Time register
This register enables you to program the write recovery time, tWR. It is recommended that
this register is modified during system initialization, or when there are no current or
outstanding transactions. This can be ensured by waiting until the EMC is idle, and then
entering low-power, or disabled mode. This value is normally found in SDRAM data
sheets as tWR, tDPL, tRWL, or tRDL. This register is accessed with one wait state.
Note: This register is used for all four dynamic memory chip selects. Therefore the worst
case value for all of the chip selects must be programmed.
Table 425. Dynamic Memory Write Recovery Time register (DYNAMICWR, address
0x4000 5044) bit description
Bit

Symbol Description

Reset
value

3:0

TWR

Write recovery time.
0x0 - 0xE = n + 1 clock cycles. The delay is in EMC_CCLK cycles.
0xF = 16 clock cycles (POR reset value).

0xF

31:4

-

Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.

-

23.7.13 Dynamic Memory Active to Active Command Period register
This register enables you to program the active to active command period, tRC. It is
recommended that this register is modified during system initialization, or when there are
no current or outstanding transactions. This can be ensured by waiting until the EMC is
idle, and then entering low-power, or disabled mode. This value is normally found in
SDRAM data sheets as tRC. This register is accessed with one wait state.
Note: This register is used for all four dynamic memory chip selects. Therefore the worst
case value for all of the chip selects must be programmed.
Table 426. Dynamic Memory Active to Active Command Period register (DYNAMICRC,
address 0x4000 5048) bit description

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Bit

Symbol

Description

Reset
value

4:0

TRC

Active to active command period.
0x0 - 0x1E = n + 1 clock cycles. The delay is in EMC_CCLK cycles.
0x1F = 32 clock cycles (POR reset value).

0x1F

31:5

-

Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.

-

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23.7.14 Dynamic Memory Auto-refresh Period register
This register enables you to program the auto-refresh period, and auto-refresh to active
command period, tRFC. It is recommended that this register is modified during system
initialization, or when there are no current or outstanding transactions. This can be
ensured by waiting until the EMC is idle, and then entering low-power, or disabled mode.
This value is normally found in SDRAM data sheets as tRFC, or sometimes as tRC. This
register is accessed with one wait state.
Note: This register is used for all four dynamic memory chip selects. Therefore the worst
case value for all of the chip selects must be programmed.
Table 427. Dynamic Memory Auto Refresh Period register (DYNAMICRFC, address
0x4000 504C) bit description
Bit

Symbol

Description

Reset
value

4:0

TRFC

Auto-refresh period and auto-refresh to active command period.
0x0 - 0x1E = n + 1 clock cycles. The delay is in EMC_CCLK cycles.
0x1F = 32 clock cycles (POR reset value).

0x1F

31:5

-

Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.

-

23.7.15 Dynamic Memory Exit Self Refresh register
This register enables you to program the exit self-refresh to active command time, tXSR. It
is recommended that this register is modified during system initialization, or when there
are no current or outstanding transactions. This can be ensured by waiting until the EMC
is idle, and then entering low-power, or disabled mode. This value is normally found in
SDRAM data sheets as tXSR. This register is accessed with one wait state.
Note: This register is used for all four dynamic memory chip selects. Therefore the worst
case value for all of the chip selects must be programmed.
Table 428. Dynamic Memory Exit Self Refresh register (DYNAMICXSR, address 0x4000 5050)
bit description
Bit

Symbol

Description

Reset
value

4:0

TXSR

Exit self-refresh to active command time.
0x0 - 0x1E = n + 1 clock cycles. The delay is in EMC_CCLK cycles.
0x1F = 32 clock cycles (POR reset value).

0x1F

31:5

-

Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.

-

23.7.16 Dynamic Memory Active Bank A to Active Bank B Time register
This register enables you to program the active bank A to active bank B latency, tRRD. It
is recommended that this register is modified during system initialization, or when there
are no current or outstanding transactions. This can be ensured by waiting until the EMC
is idle, and then entering low-power, or disabled mode. This value is normally found in
SDRAM data sheets as tRRD. This register is accessed with one wait state.
Note: This register is used for all four dynamic memory chip selects. Therefore the worst
case value for all of the chip selects must be programmed.
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Table 429. Dynamic Memory Active Bank A to Active Bank B Time register (DYNAMICRRD,
address 0x4000 5054) bit description
Bit

Symbol

Description

Reset
value

3:0

TRRD

Active bank A to active bank B latency
0x0 - 0xE = n + 1 clock cycles. The delay is in EMC_CCLK cycles.
0xF = 16 clock cycles (POR reset value).

0xF

31:4

-

Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.

-

23.7.17 Dynamic Memory Load Mode register to Active Command Time
This register enables you to program the load mode register to active command time,
tMRD. It is recommended that this register is modified during system initialization, or when
there are no current or outstanding transactions. This can be ensured by waiting until the
EMC is idle, and then entering low-power, or disabled mode. This value is normally found
in SDRAM data sheets as tMRD, or tRSA. This register is accessed with one wait state.
Note: This register is used for all four dynamic memory chip selects. Therefore the worst
case value for all of the chip selects must be programmed.
Table 430. Dynamic Memory Load Mode register to Active Command Time (DYNAMICMRD,
address 0x4000 5058) bit description
Bit

Symbol

Description

Reset
value

3:0

TMRD

Load mode register to active command time.
0x0 - 0xE = n + 1 clock cycles. The delay is in EMC_CCLK cycles.
0xF = 16 clock cycles (POR reset value).

0xF

31:4

-

Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.

-

23.7.18 Static Memory Extended Wait register
This register is used to time long static memory read and write transfers when the
ExtendedWait (EW) bit in the StaticConfig register is set. It is recommended that this
register is modified during system initialization, or when there are no current or
outstanding transactions. However, if necessary, these control bits can be altered during
normal operation. This register is accessed with one wait state.
Table 431. Static Memory Extended Wait register (STATICEXTENDEDWAIT, address
0x4000 5080) bit description
Bit

Symbol

9:0

EXTENDEDWAIT Extended wait time out.
0x0
16 clock cycles (POR reset value). The delay is in EMC_CCLK
cycles.
0x0 = 16 clock cycles.
0x1 - 0x3FF = (n+1) x16 clock cycles.

31:10 -

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Description

Reset
value

Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.

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For example, for a static memory read/write transfer time of 16 µs, and a EMC_CCLK
frequency of 50 MHz, the following value must be programmed into this register:
(16 x 10-6 x 50 x 106) / 16 - 1 = 49

23.7.19 Dynamic Memory Configuration registers
These registers enable you to program the configuration information for the relevant
dynamic memory chip select. These registers are normally only modified during system
initialization. These registers are accessed with one wait state.
Table 432. Dynamic Memory Configuration registers (DYNAMICCONFIG[0:3], address
0x4000 5100 (DYNAMICCONFIG0) to 0x4000 5160 (DYNAMICCONFIG3)) bit
description
Bit

Symbol

Value Description

2:0

-

-

4:3

MD

6:5

-

12:7

AM0

13

-

14

AM1

18:15 19

20

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Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
Memory device.

0

0x0

SDRAM (POR reset value).

0x1

Reserved.

0x2

Reserved.

0x3

Reserved.

-

Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
0

Address mapping.
See Table 433. 000000 = reset value.[1]
-

Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
Address mapping
See Table 433. 0 = reset value.

0

-

Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.

0

Disabled. Buffer disabled for accesses to this chip select (POR
reset value).

1

Enabled. Buffer enabled for accesses to this chip select. After
configuration of the dynamic memory, the buffer must be
enabled for normal operation. [2]

B

Buffer enable.

P

31:21 -

Reset
value

Write protect.

0

0

None. Writes not protected (POR reset value).

1

Protected. Writes protected.

-

Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.

[1]

The SDRAM column and row width and number of banks are computed automatically from the address
mapping.

[2]

The buffers must be disabled during SDRAM initialization. The buffers must be enabled during normal
operation.

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Address mappings that are not shown in Table 433 are reserved.
Table 433. Address mapping
14

12

11:9 8:7

Description

16 bit external bus high-performance address mapping (Row, Bank, Column)
0

0

000

00

16 Mb (2Mx8), 2 banks, row length = 11, column length = 9

0

0

000

01

16 Mb (1Mx16), 2 banks, row length = 11, column length = 8

0

0

001

00

64 Mb (8Mx8), 4 banks, row length = 12, column length = 9

0

0

001

01

64 Mb (4Mx16), 4 banks, row length = 12, column length = 8

0

0

010

00

128 Mb (16Mx8), 4 banks, row length = 12, column length = 10

0

0

010

01

128 Mb (8Mx16), 4 banks, row length = 12, column length = 9

0

0

011

00

256 Mb (32Mx8), 4 banks, row length = 13, column length = 10

0

0

011

01

256 Mb (16Mx16), 4 banks, row length = 13, column length = 9

0

0

100

00

512 Mb (64Mx8), 4 banks, row length = 13, column length = 11

0

0

100

01

512 Mb (32Mx16), 4 banks, row length = 13, column length = 10

16 bit external bus address mapping (Bank, Row, Column)
0

1

000

00

16 Mb (2Mx8), 2 banks, row length = 11, column length = 9

0

1

000

01

16 Mb (1Mx16), 2 banks, row length = 11, column length = 8

0

1

001

00

64 Mb (8Mx8), 4 banks, row length = 12, column length = 9

0

1

001

01

64 Mb (4Mx16), 4 banks, row length = 12, column length = 8

0

1

010

00

128 Mb (16Mx8), 4 banks, row length = 12, column length = 10

0

1

010

01

128 Mb (8Mx16), 4 banks, row length = 12, column length = 9

0

1

011

00

256 Mb (32Mx8), 4 banks, row length = 13, column length = 10

0

1

011

01

256 Mb (16Mx16), 4 banks, row length = 13, column length = 9

0

1

100

00

512 Mb (64Mx8), 4 banks, row length = 13, column length = 11

0

1

100

01

512 Mb (32Mx16), 4 banks, row length = 13, column length = 10

32 bit external bus high-performance address mapping (Row, Bank, Column)

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1

0

000

00

16 Mb (2Mx8), 2 banks, row length = 11, column length = 9

1

0

000

01

16 Mb (1Mx16), 2 banks, row length = 11, column length = 8

1

0

001

00

64 Mb (8Mx8), 4 banks, row length = 12, column length = 9

1

0

001

01

64 Mb (4Mx16), 4 banks, row length = 12, column length = 8

1

0

001

10

64 Mb (2Mx32), 4 banks, row length = 11, column length = 8

1

0

010

00

128 Mb (16Mx8), 4 banks, row length = 12, column length = 10

1

0

010

01

128 Mb (8Mx16), 4 banks, row length = 12, column length = 9

1

0

010

10

128 Mb (4Mx32), 4 banks, row length = 12, column length = 8

1

0

011

00

256 Mb (32Mx8), 4 banks, row length = 13, column length = 10

1

0

011

01

256 Mb (16Mx16), 4 banks, row length = 13, column length = 9

1

0

011

10

256 Mb (8Mx32), 4 banks, row length = 13, column length = 8

1

0

100

00

512 Mb (64Mx8), 4 banks, row length = 13, column length = 11

1

0

100

01

512 Mb (32Mx16), 4 banks, row length = 13, column length = 10

1

0

010

01

256 Mb (8Mx32), 4 banks, row length = 12, column length = 9

1

0

011

01

512 Mb, (16Mx32), 4 banks, row length = 13, column length = 9

1

0

100

01

1 Gb (32Mx32), 4 banks, row length = 13, column length = 10

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Table 433. Address mapping …continued
14

12

11:9 8:7

Description

32 bit external bus address mapping (Bank, Row, Column)
1

1

000

00

16 Mb (2Mx8), 2 banks, row length = 11, column length = 9

1

1

000

01

16 Mb (1Mx16), 2 banks, row length = 11, column length = 8

1

1

001

00

64 Mb (8Mx8), 4 banks, row length = 12, column length = 9

1

1

001

01

64 Mb (4Mx16), 4 banks, row length = 12, column length = 8

1

1

001

10

64 Mb (2Mx32), 4 banks, row length = 11, column length = 8

1

1

010

00

128 Mb (16Mx8), 4 banks, row length = 12, column length = 10

1

1

010

01

128 Mb (8Mx16), 4 banks, row length = 12, column length = 9

1

1

010

10

128 Mb (4Mx32), 4 banks, row length = 12, column length = 8

1

1

011

00

256 Mb (32Mx8), 4 banks, row length = 13, column length = 10

1

1

011

01

256 Mb (16Mx16), 4 banks, row length = 13, column length = 9

1

1

011

10

256 Mb (8Mx32), 4 banks, row length = 13, column length = 8

1

1

100

00

512 Mb (64Mx8), 4 banks, row length = 13, column length = 11

1

1

100

01

512 Mb (32Mx16), 4 banks, row length = 13, column length = 10

1

1

010

01

256 Mb (8Mx32), 4 banks, row length = 12, column length = 9

1

1

011

01

512 Mb, (16Mx32), 4 banks, row length = 13, column length = 9

1

1

100

01

1 Gb (32Mx32), 4 banks, row length = 13, column length = 10

A chip select can be connected to a single memory device, in this case the chip select
data bus width is the same as the device width. Alternatively the chip select can be
connected to a number of external devices. In this case the chip select data bus width is
the sum of the memory device data bus widths.
For example, for a chip select connected to:

•
•
•
•

a 32-bit wide memory device, choose a 32-bit wide address mapping.
a 16-bit wide memory device, choose a 16-bit wide address mapping.
four x 8-bit wide memory devices, choose a 32-bit wide address mapping.
two x 8-bit wide memory devices, choose a 16-bit wide address mapping.

The SDRAM bank select pins BA1 and BA0 are connected to address lines A14 and A13,
respectively.

23.7.20 Dynamic Memory RAS & CAS Delay registers
These registers enable you to program the RAS and CAS latencies for the relevant
dynamic memory. It is recommended that these registers are modified during system
initialization, or when there are no current or outstanding transactions. This can be
ensured by waiting until the EMC is idle, and then entering low-power, or disabled mode.
These registers are accessed with one wait state.
Note: The values programmed into these registers must be consistent with the values
used to initialize the SDRAM memory device.

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Table 434. Dynamic Memory RASCAS Delay registers (DYNAMICRASCAS[0:3], address
0x4000 5104 (DYNAMICRASCAS0) to 0x4000 5164 (DYNAMICRASCAS3)) bit
description
Bit

Symbol

1:0

RAS

7:2

-

9:8

CAS

31:10 -

Value Description

Reset
value

RAS latency (active to read/write delay).

11

0x0

Reserved.

0x1

One EMC_CCLK cycle.

0x2

Two EMC_CCLK cycles.

0x3

Three EMC_CCLK cycles (POR reset value).

-

Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
CAS latency.

11

0x0

Reserved.

0x1

One EMC_CCLK cycle.

0x2

Two EMC_CCLK cycles.

0x3

Three EMC_CCLK cycles (POR reset value).

-

Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.

23.7.21 Static Memory Configuration registers
These registers configure the static memory configuration. It is recommended that these
registers are modified during system initialization, or when there are no current or
outstanding transactions. This can be ensured by waiting until the EMC is idle, and then
entering low-power, or disabled mode. These registers are accessed with one wait state.
Table 435. Static Memory Configuration registers (STATICCONFIG[0:3], address 0x4000 5200
(STATICCONFIG0) to 0x4000 5260 (STATICCONFIG3)) bit description

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Bit

Symbol

1:0

MW

2

-

3

PM

Value Description

Reset
value

Memory width.

0

0x0

8 bit (POR reset value).

0x1

16 bit.

0x2

32 bit.

0x3

Reserved.

-

Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.

-

Page mode.
In page mode the EMC can burst up to four external accesses.
Therefore devices with asynchronous page mode burst four or
higher devices are supported. Asynchronous page mode burst
two devices are not supported and must be accessed normally.

0

0

Disabled. (POR reset value.)

1

Enabled. Async page mode enabled (page length four).

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Table 435. Static Memory Configuration registers (STATICCONFIG[0:3], address 0x4000 5200
(STATICCONFIG0) to 0x4000 5260 (STATICCONFIG3)) bit description
Bit

Symbol

Value Description

Reset
value

5:4

-

-

Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.

-

6

PC

Chip select polarity.
The value of the chip select polarity on power-on reset is 0.

0

7

0

Active LOW chip select.

1

Active HIGH chip select.
0
Byte lane state.
The byte lane state bit, PB, enables different types of memory to
be connected. For byte-wide static memories the BLSn[3:0]
signal from the EMC is usually connected to WE (write enable).
In this case for reads all the BLSn[3:0] bits must be HIGH. This
means that the byte lane state (PB) bit must be LOW.

PB

16 bit wide static memory devices usually have the BLSn[3:0]
signals connected to the UBn and LBn (upper byte and lower
byte) signals in the static memory. In this case a write to a
particular byte must assert the appropriate UBn or LBn signal
LOW. For reads, all the UB and LB signals must be asserted
LOW so that the bus is driven. In this case the byte lane state
(PB) bit must be HIGH.
Remark: When PB is set to 0, the WE signal is undefined or 0.
You must set PB to 1, to use the WE signal.

8

-

19

B

User manual

1

Low. For reads the respective active bits in BLSn[3:0] are LOW.
For writes the respective active bits in BLSn[3:0] are LOW.
0

Extended wait.
Extended wait (EW) uses the StaticExtendedWait register to
time both the read and write transfers rather than the
StaticWaitRd and StaticWaitWr registers. This enables much
longer transactions.[1]
0

Disabled. Extended wait disabled (POR reset value).

1

Enabled. Extended wait enabled.

-

Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.

-

Buffer enable[2].

0

0

Disabled. Buffer disabled (POR reset value).

1

Enabled. Buffer enabled.

P

31:21 -

UM10503

High. For reads all the bits in BLSn[3:0] are HIGH. For writes the
respective active bits in BLSn[3:0] are LOW (POR reset value).

EW

18:9

20

0

Write protect.

0

0

None. Writes not protected (POR reset value).

1

Protect. Write protected.

-

Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.

[1]

Extended wait and page mode cannot be selected simultaneously.

[2]

EMC may perform burst read access even when the buffer enable bit is cleared.

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23.7.22 Static Memory Write Enable Delay registers
These registers enable you to program the delay from the chip select to the write enable.
It is recommended that these registers are modified during system initialization, or when
there are no current or outstanding transactions. This can be ensured by waiting until the
EMC is idle, and then entering low-power, or disabled mode. These registers are
accessed with one wait state.

Table 436. Static Memory Write Enable Delay registers (STATICWAITWEN[0:3], address
0x4000 5204 (STATICWAITWEN0) to 0x4000 5264 (STATICWAITWEN3)) bit
description
Bit

Symbol

Description

Reset
value

3:0

WAITWEN

Wait write enable.
0x0
Delay from chip select assertion to write enable.
0x0 = One EMC_CCLK cycle delay between assertion of chip select
and write enable (POR reset value).
0x1 - 0xF = (n + 1) EMC_CCLK cycle delay. The delay is (WAITWEN
+1) x tEMC_CCLK.

31:4

-

Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.

-

23.7.23 Static Memory Output Enable Delay registers
These registers enable you to program the delay from the chip select or address change,
whichever is later, to the output enable. It is recommended that these registers are
modified during system initialization, or when there are no current or outstanding
transactions. This can be ensured by waiting until the EMC is idle, and then entering
low-power, or disabled mode. These registers are accessed with one wait state.
Table 437. Static Memory Output Enable delay registers (STATICWAITOEN[0:3], address
0x4000 5208 (STATICWAITOEN0) to 0x4000 5268 (STATICWAITOEN3)) bit
description
Bit

Symbol

Description

Reset
value

3:0

WAITOEN

Wait output enable.
Delay from chip select assertion to output enable.
0x0 = No delay (POR reset value).
0x1 - 0xF = n cycle delay. The delay is WAITOEN x tEMC_CCLK.

0x0

31:4

-

Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.

-

23.7.24 Static Memory Read Delay registers
These registers enable you to program the delay from the chip select to the read access.
It is recommended that these registers are modified during system initialization, or when
there are no current or outstanding transactions. This can be ensured by waiting until the
EMC is idle, and then entering low-power, or disabled mode. It is not used if the extended
wait bit is enabled in the StaticConfig registers. These registers are accessed with one
wait state.

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Table 438. Static Memory Read Delay registers (STATICWAITRD[0:3], address 0x4000 520C
(STATICWAITRD0) to 0x4000 526C (STATICWAITRD3)) bit description
Bit

Symbol

Description

4:0

WAITRD

Non-page mode read wait states or asynchronous page mode read first 0x1F
[1]
access wait state.
Non-page mode read or asynchronous page mode read, first read only:
0x0 - 0x1E = (n + 1) EMC_CCLK cycles for read accesses. For
non-sequential reads, the wait state time is (WAITRD + 1) x
tEMC_CCLK.
0x1F = 32 EMC_CCLK cycles for read accesses (POR reset value).

31:5

-

Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.

[1]

Reset
value

-

The reset value depends on the boot mode. See Section 5.3.4.2 “EMC boot modes”.

23.7.25 Static Memory Page Mode Read Delay registers
These registers enable you to program the delay for asynchronous page mode sequential
accesses. It is recommended that these registers are modified during system initialization,
or when there are no current or outstanding transactions. This can be ensured by waiting
until the EMC is idle, and then entering low-power, or disabled mode. This register is
accessed with one wait state.
Table 439. Static Memory Page Mode Read Delay registers (STATICWAITPAGE[0:3], address
0x4000 5210 (STATICWAITPAGE0) to 0x4000 5270 (STATICWAITPAGE3)) bit
description
Bit

Symbol

Description

Reset
value

4:0

WAITPAGE Asynchronous page mode read after the first read wait states.
0x1F
Number of wait states for asynchronous page mode read accesses
after the first read:
0x0 - 0x1E = (n+ 1) EMC_CCLK cycle read access time. For
asynchronous page mode read for sequential reads, the wait state
time for page mode accesses after the first read is (WAITPAGE + 1)
x tEMC_CCLK.
0x1F = 32 EMC_CCLK cycle read access time (POR reset value).

31:5

-

Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.

23.7.26 Static Memory Write Delay registers
These registers enable you to program the delay from the chip select to the write access.
It is recommended that these registers are modified during system initialization, or when
there are no current or outstanding transactions. This can be ensured by waiting until the
EMC is idle, and then entering low-power, or disabled mode.These registers are not used
if the extended wait (EW) bit is enabled in the StaticConfig register. These registers are
accessed with one wait state.

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Table 440. Static Memory Write Delay registers (STATICWAITWR[0:3], address 0x4000 5214
(STATICWAITWR0) to 0x4000 5274 (STATICWAITWR3)) bit description
Bit

Symbol

Description

Reset
value

4:0

WAITWR

Write wait states.
SRAM wait state time for write accesses after the first read:
0x0 - 0x1E = (n + 2) EMC_CCLK cycle write access time. The wait
state time for write accesses after the first read is WAITWR (n + 2) x
tEMC_CCLK.
0x1F = 33 EMC_CCLK cycle write access time (POR reset value).

0x1F

31:5

-

Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.

-

23.7.27 Static Memory Turn Round Delay registers
These registers enable you to program the number of bus turnaround cycles. It is
recommended that these registers are modified during system initialization, or when there
are no current or outstanding transactions. This can be ensured by waiting until the EMC
is idle, and then entering low-power, or disabled mode. These registers are accessed with
one wait state.
Table 441. Static Memory Turn Round Delay registers (STATICWAITTURN[0:3], address
0x4000 5218 (STATICWAITTURN0) to 0x4000 5278 (STATICWAITTURN3)) bit
description
Bit

Symbol

Description

Reset
value

3:0

WAITTURN Bus turnaround cycles.
0x0 - 0xE = (n + 1) EMC_CCLK turnaround cycles. Bus turnaround
time is (WAITTURN + 1) x tEMC_CCLK.
0xF = 16 EMC_CCLK turnaround cycles (POR reset value).

0xF

31:4

-

-

Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.

Bus turn-around cycles are generated between external bus transfers in the following
situations when at least one of the memory banks is static memory:

• between read and read to different memory banks
• between read and write to the same memory bank
• between read and write to different memory banks
Bus turn-around cycles prevent bus contention on the external memory data bus.

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23.8 Functional description
Figure 59 shows a block diagram of the EMC.
The functions of the EMC blocks are described in the following sections:

•
•
•
•
•

AHB slave register interface.
AHB slave memory interfaces.
Data buffers.
Memory controller state machine.
Pad interface.

Note: For 32 bit wide chip selects data is transferred to and from dynamic memory in
SDRAM bursts of four. For 16 bit wide chip selects SDRAM bursts of eight are used.

23.8.1 AHB slave register interface
The AHB slave register interface block enables the registers of the EMC to be
programmed. This module also contains most of the registers and performs the majority of
the register address decoding.
To eliminate the possibility of endianness problems, all data transfers to and from the
registers of the EMC must be 32 bits wide.
Note: If an access is attempted with a size other than a word (32 bits), it causes an
ERROR response to the AHB bus and the transfer is terminated.

23.8.2 AHB slave memory interface
The AHB slave memory interface allows access to external memories.

23.8.2.1 Memory transaction endianness
The endianness of the data transfers to and from the external memories is determined by
the Endian mode (N) bit in the Config register.
Note: The memory controller must be idle (see the busy field of the Status Register)
before endianness is changed, so that the data is transferred correctly.

23.8.2.2 Memory transaction size
Memory transactions can be 8, 16, or 32 bits wide. Any access attempted with a size
greater than a word (32 bits) causes an ERROR response to the AHB bus and the transfer
is terminated.

23.8.2.3 Write protected memory areas
Write transactions to write-protected memory areas generate an ERROR response to the
AHB bus and the transfer is terminated.

23.8.3 Pad interface
The pad interface block provides the interface to the pads.

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The EMC dynamic memory interface requires that all EMC_CLK signals are selected on
the CLKn pins for 16-bit memory and for 32-bit memory.
For static memory larger delays are defined by in steps of one EMC clock cycle by the
STATICWAIT registers (see Section 23.7.22 to Section 23.7.27).

23.8.4 Data buffers
The AHB interface reads and writes via buffers to improve memory bandwidth and reduce
transaction latency. The EMC contains four 16-word buffers. The buffers can be used as
read buffers, write buffers, or a combination of both. The buffers are allocated
automatically.
The buffers must be disabled during SDRAM initialization. The buffers must be enabled
during normal operation.
The buffers can be enabled or disabled for static memory using the StaticConfig
Registers.

23.8.4.1 Write buffers
Write buffers are used to:

• Merge write transactions so that the number of external transactions are minimized.
Buffer data until the EMC can complete the write transaction, improving AHB write
latency.
Convert all dynamic memory write transactions into quadword bursts on the external
memory interface. This enhances transfer efficiency for dynamic memory.

• Reduce external memory traffic. This improves memory bandwidth and reduces
power consumption.
Write buffer operation:

• If the buffers are enabled, an AHB write operation writes into the Least Recently Used
(LRU) buffer, if empty.
If the LRU buffer is not empty, the contents of the buffer are flushed to memory to
make space for the AHB write data.

• If a buffer contains write data it is marked as dirty, and its contents are written to
memory before the buffer can be reallocated.
The write buffers are flushed whenever:

• The memory controller state machine is not busy performing accesses to external
memory.
The memory controller state machine is not busy performing accesses to external
memory, and an AHB interface is writing to a different buffer.
Note: For dynamic memory, the smallest buffer flush is a quadword of data. For static
memory, the smallest buffer flush is a byte of data.

23.8.4.2 Read buffers
Read buffers are used to:
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• Buffer read requests from memory. Future read requests that hit the buffer read the
data from the buffer rather than memory, reducing transaction latency.
Convert all read transactions into quadword bursts on the external memory interface.
This enhances transfer efficiency for dynamic memory.

• Reduce external memory traffic. This improves memory bandwidth and reduces
power consumption.
Read buffer operation:

• If the buffers are enabled and the read data is contained in one of the buffers, the read
data is provided directly from the buffer.

• If the read data is not contained in a buffer, the LRU buffer is selected. If the buffer is
dirty (contains write data), the write data is flushed to memory. When an empty buffer
is available the read command is posted to the memory.
A buffer filled by performing a read from memory is marked as not-dirty (not containing
write data) and its contents are not flushed back to the memory controller unless a
subsequent AHB transfer performs a write that hits the buffer.

23.8.5 Using the EMC with SDRAM
23.8.5.1 SDRAM burst length
For 32-bit wide chip selects data is transferred to and from dynamic memory in SDRAM
bursts of four. For 16-bit wide chip selects SDRAM bursts of eight are used.

23.8.5.2 SDRAM mode register burst length set-up
To be used with the EMC, the SDRAM must be configured for a 128-bit sequential burst.
The burst length is configured through the mode register in the SDRAM memory. The
layout for a JEDEC standard SDRAM mode register is shown in Table 442. The EMC
address bits are mapped to the SDRAM mode register bits as indicated in Table 442.

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Table 442. SDRAM mode register description
Address line

SDRAM mode
register bit

A2:A0

2:0

A3

Value

Burst length
000

1 (M3 = 0)
1 (M3 =1)

001

2 (M3 = 0)
2 (M3 =1)

010

4 (M3 = 0)
4 (M3 =1)

011

8 (M3 = 0)
8 (M3 =1)

100

Reserved (M3 = 0)
Reserved (M3 = 1)

101

Reserved (M3 = 0)
Reserved (M3 = 1)

110

Reserved (M3 = 0)
Reserved (M3 = 1)

111

Full page (M3 = 0)
Reserved (M3 = 1)

3

Burst type
0
1

A6:A4

6:4

A8:A7

8:7

A9

9

Sequential
Interleaved
Latency mode

000

Reserved

001

Reserved

010

2

011

3

100

Reserved

101

Reserved

110

Reserved

111

Reserved
Operating mode. All other values are
reserved.

00

A11:A10

Description

Standard operation
Write burst mode

0

Programmed burst length

1

Single location access

11:10

Reserved

The SDRAM mode register is loaded in two steps:
1. Use the DYNAMICCONTROL register to issue a set mode command.
2. When the SDRAM is in the set mode state, issue an SDRAM read from an address
specific to the selected mode and the SDRAM memory organization.
This loads the mode register with the correct settings.
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The read address is calculated as follows:

• Determine the mode register content MODE:
– For a single 16-bit external SDRAM chip set the burst length to 8. For a single
32-bit SDRAM chip set the burst length to 4.
– Select the sequential mode.
– Select latency mode = 2 or 3.
– Select Write burst mode = 0.

• Determine the shift value OFFSET to shift the mode register content by. This shift
value depends on the SDRAM device organization and it is calculated as:
OFFSET = number of columns + total bus width + bank select bits (RBC mode)
OFFSET = number of columns + total bus width (BRC mode)
– The number of columns is listed in Table 433 for a specific SDRAM device.
– The total bus with is 1 for a 16-bit bus and 2 for a 32-bit bus. If you combine two
16-bit devices to form a 32-bit memory bank, the total bus width is 2.
– This is the number of bits needed to indicate the number of banks. Most SDRAM
devices use 2 bank select bits for four banks.

• Select the SDRAM memory mapped address DYCSX.
• The SDRAM read address is ADDRESS = DYCSX + (MODE << OFFSET).
23.8.5.2.1

Example for setting the SDRAM mode register
For a 16-bit external SDRAM chip, select latency mode = 2 and burst size = 8. The mode
register value is MODE = 0x23.
Using a 128 Mb (8Mx16) SDRAM chip with address mapping of 4 banks, row length = 12,
column length = 9 (see Table 433), OFFSET = 9 + 1 + 2.
Using DYCS0, the SDRAM address is 0x2800 0000.
The SDRAM read command address becomes 0x2802 3000.

23.8.5.3 Self-refresh mode
The EMC provides a mechanism to place the dynamic memories into self-refresh mode.
Self-refresh mode can be entered by software by setting the SR bit in the DynamicControl
Register and polling the SA bit in the Status Register.
Any transactions to memory that are generated while the memory controller is in
self-refresh mode are rejected and an error response is generated to the AHB bus.
Clearing the SR bit in the DynamicControl Register returns the memory to normal
operation. See the memory data sheet for refresh requirements.
Note: The static memory can be accessed as normal when the SDRAM memory is in
self-refresh mode.

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Chapter 23: LPC43xx/LPC43Sxx External Memory Controller (EMC)

23.8.6 External static memory interface
External memory interfacing depends on the bank width (32, 16 or 8 bit selected via MW
bits in corresponding StaticConfig register).
If a memory bank is configured to be 32 bits wide, address lines A0 and A1 can be used
as non-address lines. If a memory bank is configured to 16 bits wide, A0 is not required.
However, 8 bit wide memory banks do require all address lines down to A0. Configuring
A1 and/or A0 lines to provide address or non-address function is accomplished using the
SYSCON registers.
Symbol a_b in the following figures refers to the highest order address line in the data bus.
Symbol a_m refers to the highest order address line of the memory chip used in the
external memory interface.
If the external memory is used as external boot memory for flashless devices, refer to
Section 5.2 on how to connect the EMC. The memory bank width for memory banks one
and two is determined by the setting of the BOOT pins.

23.8.6.1 32-bit wide memory bank connection

CS
OE

BLS[3]
D[31:24]

CE
OE
WE

CE
OE
WE

BLS[2]

IO[7:0]
A[a_m:0]

IO[7:0]
A[a_m:0]

D[23:16]

BLS[1]
D[15:8]

CE
OE
WE
IO[7:0]
A[a_m:0]

BLS[0]
D[7:0]

CE
OE
WE
IO[7:0]
A[a_m:0]

A[a_b:2]

a. 32 bit wide memory bank interfaced to four 8 bit memory chips
CS
OE
WE

BLS[3]
BLS[2]
D[31:16]

CE
OE
WE
UB
LB
IO[15:0]
A[a_m:0]

BLS[1]
BLS[0]
D[15:0]

CE
OE
WE
UB
LB
IO[15:0]
A[a_m:0]

A[a_b:2]

b. 32 bit wide memory bank interfaced to two 16 bit memory chips

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CS
OE
WE

BLS[3]
BLS[2]
BLS[1]
BLS[0]
D[31:0]

CE
OE
WE
B3
B2
B1
B0
IO[31:0]
A[a_m:0]

A[a_b:2]

c. 32 bit wide memory bank interfaced to one 8 bit memory chip
Fig 61. 32 bit bank external memory interfaces ( bits MW = 10)

23.8.6.2 16-bit wide memory bank connection

CS
OE
CE
OE
WE

BLS[1]

BLS[0]

IO[7:0]
A[a_m:0]

D[15:8]

D[7:0]

CE
OE
WE
IO[7:0]
A[a_m:0]

A[a_b:1]

a. 16 bit wide memory bank interfaced to two 8 bit memory chips
CS
OE
WE

BLS[1]
BLS[0]
D[15:0]

CE
OE
WE
UB
LB
IO[15:0]
A[a_m:0]

A[a_b:1]

b. 16 bit wide memory bank interfaced to a 16 bit memory chip
Fig 62. 16 bit bank external memory interfaces (bits MW = 01)

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23.8.6.3 8-bit wide memory bank connection
CS
OE
CE
OE
WE
D[7:0]

WE
IO[7:0]
A[a_m:0]

A[a_b:0]

Fig 63. 8 bit bank external memory interface (bits MW = 00)

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Chapter 24: LPC43xx/LPC43Sxx SPI Flash Interface (SPIFI)
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24.1 How to read this chapter
The SPIFI is available on all LPC43xx/LPC43Sxx parts. A software driver library is
available on LPCware.com.
See Section 5.3.4.4 “SPIFI boot mode” for details on the SPIFI boot process.

24.2 Basic configuration
The SPIFI is configured as follows:

• See Table 443 for clocking and power control.
• The SPIFI is reset by the SPIFI_RST (reset # 53).
Table 443. SPIFI clocking and power control
Base clock

Branch clock

Operating
frequency

SPIFI AHB register clock

BASE_M4_CLK

CLK_M4_SPIFI

up to
204 MHz

SPIFI serial clock input

BASE_SPIFI_CLK

SPIFI_CLK

104 MHz

Remark: All parts can use the SPIFI for booting. See Section 5.3.4.4.

24.3 Features
•
•
•
•
•
•
•
•

Quad SPI Flash Interface (SPIFI) interface to external flash.
Transfer rates of up to SPIFI_CLK/2 bytes per second.
External flash is directly memory mapped for fast access.
Supports 1-, 2-, and 4-bit bi-directional serial protocols.
Transfer protocol compatible with various vendors and devices.
The SPIFI memory is accessible by the DMA.
Software driver library available on the LPCware.com website.
Supports execute-in-place (direct code execution from the SPI Flash memory) and
general read/write/erase operations.

• Built-in cache to give high-performance code execution.

24.4 General description
The SPI Flash Interface (SPIFI) allows low pin-count serial flash memories to be
connected to an ARM processor with very little performance penalty compared to higher
pin-count parallel flash devices. After a few commands configure the interface at startup,
the entire flash content is accessible as normal memory using byte, halfword, and word

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Chapter 24: LPC43xx/LPC43Sxx SPI Flash Interface (SPIFI)

accesses by the processor and/or DMA channels. Erasure and programming are handled
by simple sequences of commands. A software API available on LPCware.com provides
set-up, programming, and erase functions.
Many SPI flash devices use serial commands for device setup/initialization, and then
move to dual or quad commands for normal operation. Different serial Flash vendors and
devices accept or require different commands and command formats. SPIFI includes
sufficient flexibility to be compatible with many market-leading devices plus extensions to
help insure compatibility with future devices.
SPI Flash devices respond to commands sent by software, or automatically sent by the
SPIFI when software reads the serial flash region of the memory map. Commands are
divided into fields called opcode, address, intermediate data, and data. The address,
intermediate data, and data fields are optional depending on the opcode. Some devices
include a mode in which the opcode can be implied in Read commands for higher
performance. Data fields are further divided into input and output data fields depending on
the opcode.

Table 444. SPIFI flash memory map
Memory

Address

SPIFI data

0x1400 0000 to 0x17FF FFFF (Use this memory area for debugging code and for
slightly improved performance).
0x8000 0000 to 0x87FF FFFF (Debug will not work if the program counter is in this
memory area).
Remark: These are the spaces allocated to the SPIFI in the LPC43xx. The same
data appears in the first area and the first half of the second area. These areas
allow up to 64 MB and up to 128 MB of SPI flash to be mapped into the Cortex-M4
memory space. In practice, the usable space is limited to the size of the connected
device.

24.5 Pin description
Table 445. SPIFI pin description
Pin function

Direction

Description

SPIFI_SCK

O

Serial clock for the flash memory, switched only during active bits on the MOSI/IO0,
MISO/IO1, and IO3:2 lines.

SPIFI_CS

O

Chip select for the flash memory, driven LOW while a command is in progress, and
high between commands.

SPIFI_MOSI or IO0

I/O

This is an output except in quad/dual input data fields. After a quad/dual input data field,
it becomes an output again one serial clock period after CS goes high.

SPIFI_MISO or IO1

I/O

This is an output in quad/dual opcode, address, intermediate, and output data fields,
and an input in SPI mode and in quad/dual input data fields. After an input data field in
quad/dual mode, it becomes an output again one serial clock period after CS goes
high.

SPIFI_SIO[3:2]

I/O

These are outputs in quad opcode, address, intermediate, and output data fields, and
inputs in quad input data fields. These pins (or any other GPIO pins) may be used,
when not in quad mode, as software controlled Hold and/or WPn controls for flash
memories that support those functions.

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Chapter 24: LPC43xx/LPC43Sxx SPI Flash Interface (SPIFI)

24.6 Register description
The SPIFI register interface supports word accesses.
Table 446. Register overview: SPIFI (base address 0x4000 3000)
Name

Access Address Description
offset

Reset value

Reference

CTRL

R/W

0x000

SPIFI control register

0x400F FFFF Table 447

CMD

R/W

0x004

SPIFI command register

0x0000 0000

Table 448

ADDR

R/W

0x008

SPIFI address register

0x0000 0000

Table 449

IDATA

R/W

0x00C

SPIFI intermediate data register

0x0000 0000

Table 450

CLIMIT

R/W

0x010

SPIFI cache limit register

0x0800 0000

Table 451

DATA

R/W

0x014

SPIFI data register

0x0000 0000

Table 452

MCMD

R/W

0x018

SPIFI memory command register

0x0000 0000

Table 453

STAT

R/W

0x01C

SPIFI status register

0x0200 0000

Table 454

24.6.1 SPIFI control register
The SPIFI control register controls the overall operation of the SPIFI and should be written
before any commands are initiated.
Table 447. SPIFI control register (CTRL, address 0x4000 3000) bit description
Bit

Symbol

15:0

TIMEOUT

Value Description

Reset
value

This field contains the number of serial clock periods without the processor
reading data in memory mode, which will cause the SPIFI hardware to
terminate the command by driving the CS pin high and negating the CMD bit
in the Status register. (This allows the flash memory to enter a lower-power
state.)

0xFFFF

If the processor reads data from the flash region after a time-out, the
command in the Memory Command Register is issued again.
19:16 CSHIGH

This field controls the minimum CS high time, expressed as a number of serial 1111
clock periods minus one.

20

-

Reserved.

-

21

D_PRFTCH_DIS

This bit allows conditioning of memory mode prefetches based on the AHB
HPROT (instruction/data) access information. A 1 in this register means that
the SPIFI will not attempt a speculative prefetch when it encounters data
accesses.

0

22

INTEN

If this bit is 1 when a command ends, the SPIFI will assert its interrupt request 0
output. See INTRQ in the status register for further details.

23

MODE3

SPI Mode 3 select.

0

0

SCK LOW. The SPIFI drives SCK low after the rising edge at which the last bit
of each command is captured, and keeps it low while CS is HIGH.

1

SCK HIGH. the SPIFI keeps SCK high after the rising edge for the last bit of
each command and while CS is HIGH, and drives it low after it drives CS
LOW. (Known serial flash devices can handle either mode, but some devices
may require a particular mode for proper operation.)
Remark: MODE3, RFCLK, and FBCLK should not all be 1, because in this
case there is no final falling edge on SCK on which to sample the last data bit
of the frame.

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Chapter 24: LPC43xx/LPC43Sxx SPI Flash Interface (SPIFI)

Table 447. SPIFI control register (CTRL, address 0x4000 3000) bit description
Bit

Symbol

Value Description

Reset
value

26:24 -

Reserved.

27

Cache prefetching enable. The SPIFI includes an internal cache. A 1 in this bit 0
disables prefetching of cache lines.

28

29

PRFTCH_DIS

-

0

Enable. Cache prefetching enabled.

1

Disable. Disables prefetching of cache lines.

DUAL

Select dual protocol.
0

Quad protocol. This protocol uses IO3:0.

1

Dual protocol. This protocol uses IO1:0.

RFCLK

0

Select active clock edge for input data.

0

0

Rising edge. Read data is sampled on rising edges on the clock, as in classic
SPI operation.

1

Falling edge. Read data is sampled on falling edges of the clock, allowing a
full serial clock of of time in order to maximize the serial clock frequency.
Remark: MODE3, RFCLK, and FBCLK should not all be 1, because in this
case there is no final falling edge on SCK on which to sample the last data bit
of the frame.

30

FBCLK

Feedback clock select.

1

0

Internal clock. The SPIFI samples read data using an internal clock.

1

Feedback clock. Read data is sampled using a feedback clock from the SCK
pin. This allows slightly more time for each received bit.
Remark: MODE3, RFCLK, and FBCLK should not all be 1, because in this
case there is no final falling edge on SCK on which to sample the last data bit
of the frame.

31

DMAEN

A 1 in this bit enables the DMA Request output from the SPIFI. Set this bit
0
only when a DMA channel is used to transfer data in peripheral mode. Do not
set this bit when a DMA channel is used for memory-to-memory transfers
from the SPIFI memory area. DRQEN should only be used in Command
mode.

24.6.2 SPIFI command register
The Command Register may only be written as a word, but bytes, halfwords, and words
may be read from it. It may be written to when the CMD and MCINIT bits in the Status
register are 0, and under these circumstances writing initiates the transmission of a new
command. For a command that contains an address and/or intermediate data, software
should write to the Address and/or Intermediate Data registers, before writing to this
register. If the command contains output data, software should write it to the Data Register
after writing to this register. If the command contains input data, software can read it from
the Data Register after writing to this register.

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Chapter 24: LPC43xx/LPC43Sxx SPI Flash Interface (SPIFI)

Table 448. SPIFI command register (CMD, address 0x4000 3004) bit description
Bit

Symbol

Value Description

13:0

DATALEN

Except when the POLL bit in this register is 1, this field
controls how many data bytes are in the command. 0
indicates that the command does not contain a data field.

14

POLL

This bit should be written as 1 only with an opcode that a) 0
contains an input data field, and b) causes the serial flash
device to return byte status repetitively (e.g., a Read Status
command). When this bit is 1, the SPIFI hardware
continues to read bytes until the test specified by the
dataLen field is met. The hardware tests the bit in each
status byte selected by DATALEN bits 2:0, until a bit is
found that is equal to DATALEN bit 3. When the test
succeeds, the SPIFI captures the byte that meets this test
so that it can be read from the Data Register, and
terminates the command by raising CS. The
end-of-command interrupt can be enabled to inform
software when this occurs

15

DOUT

If the DATALEN field is not zero, this bit controls the
direction of the data:
0

Input from serial flash.

1

Output to serial flash.

18:16 INTLEN

20:19 FIELDFORM

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Reset
value
0

0

This field controls how many intermediate bytes precede
the data. (Each such byte may require 8 or 2 SCK cycles,
depending on whether the intermediate field is in serial,
2-bit, or 4-bit format.) Intermediate bytes are output by the
SPIFI, and include post-address control information,
dummy and delay bytes. See the description of the
Intermediate Data register for the contents of such bytes.

0

This field controls how the fields of the command are sent.

0

0x0

All serial. All fields of the command are serial.

0x1

Quad/dual data. Data field is quad/dual, other fields are
serial.

0x2

Serial opcode. Opcode field is serial. Other fields are
quad/dual.

0x3

All quad/dual. All fields of the command are in quad/dual
format.

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Chapter 24: LPC43xx/LPC43Sxx SPI Flash Interface (SPIFI)

Table 448. SPIFI command register (CMD, address 0x4000 3004) bit description
Bit

Symbol

Value Description

23:21 FRAMEFORM

Reset
value

This field controls the opcode and address fields.

0

0x0

Reserved.

0x1

Opcode. Opcode only, no address.

0x2

Opcode one byte. Opcode, least significant byte of
address.

0x3

Opcode two bytes. Opcode, two least significant bytes of
address.

0x4

Opcode three bytes. Opcode, three least significant bytes
of address.

0x5

Opcode four bytes. Opcode, 4 bytes of address.

0x6

No opcode three bytes. No opcode, 3 least significant bytes
of address.

0x7

No opcode four bytes. No opcode, 4 bytes of address.

31:24 OPCODE

The opcode of the command (not used for some
FRAMEFORM values).

0

24.6.3 SPIFI address register
Before writing a command that includes an address field to the Command register,
software should write the address to this register. The most significant byte of the address
is sent first.
Table 449. SPIFI address register (ADDR, address 0x4000 3008) bit description
Bit

Symbol

Description

31:0

ADDRESS Address.

Reset
value
0

24.6.4 SPIFI intermediate data register
Before writing a command to the Command register that requires specific intermediate
byte values, software should write the value of the bytes to this register. The least
significant byte of this register is sent first. If more than four intermediate bytes are
specified in the Command register, zeroes are sent after the 4th byte.
The main use of this register with current serial flash devices is to select the no-opcode
mode (continuous read, code execution) using the byte value 0xA5, and cancelling this
mode using 0xFF.
Many devices that require dummy (delay) bytes don't care about their contents, in which
case this register need not be written.
Table 450. SPIFI intermediate data register (IDATA, address 0x4000 300C) bit description

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Bit

Symbol

Description

Reset
value

31:0

IDATA

Value of intermediate bytes.

0

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Chapter 24: LPC43xx/LPC43Sxx SPI Flash Interface (SPIFI)

24.6.5 SPIFI cache limit register
The SPIFI hardware includes caching of previously-accessed data to improve
performance. Software can write an address within the device to this register, to prevent
such caching at and above that address. After Reset this register contains the allocated
size of the SPIFI memory area, so that all possible accesses are below that value and are
thus cacheable.
Table 451. SPIFI cache limit register (CLIMIT, address 0x4000 3010) bit description
Bit

Symbol

Description

Reset value

31:0

CLIMIT

Zero-based upper limit of cacheable memory

0x0800 0000

24.6.6 SPIFI data register
After initiating a command that includes a data output field by writing to the Command
Register, software should write output data to this register. Store Byte instructions provide
one data byte, Store Halfword instructions provide two bytes, and Store Word instructions
provide 4 bytes of output data. Store commands are waited if the FIFO is too full to accept
the number of bytes being stored. For Store Halfword and Store Word, the least significant
byte is sent first.
After initiating a command that includes a data input field by writing to the Command
Register, software should read input data from this register. Load Byte instructions deliver
one data byte to software, Load Halfword instructions deliver two bytes, and Load Word
instructions deliver 4 bytes of input data. Load commands are waited if a command is in
progress and the FIFO does not contain the number of bytes being loaded. For Load
Halfword and Load Word commands, the least significant byte is received first.
DATALEN bytes should be read from or written to this register. If such a (read or write)
command needs to be terminated before that time, software should write a 1 to the
RESET bit in the Status register to accomplish this. If software attempts to read or write
more data than was specified in DATALEN, a Data Abort exception will occur.
In polling mode (see the POLL bit in the SPIFI command register), one byte must be read
from this register because the poll mechanism writes the matching byte.
This register is not used for commands initiated by reading the flash address range in the
memory map. In DMA transfers in peripheral to-or-from-memory mode, the address of this
register should be used as the peripheral address.
Table 452. SPIFI Data register (DATA, address 0x4000 3014) bit description
Bit

Symbol

Description

Reset
value

31:0

DATA

Input or output data

0

24.6.7 SPIFI memory command register
Before accessing the flash area of the memory map, software should set up the device.
After optionally writing to the Intermediate Data register, software should write a word to
this register to define the command that is used to read data. Thereafter data can be read
from the flash memory area, either directly or by means of a DMA channel.

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Chapter 24: LPC43xx/LPC43Sxx SPI Flash Interface (SPIFI)

Writing to this register will be ignored when a command is in progress or while data has
yet to be written or read from the FIFO for a command issued. Use the MCINIT bit of the
Status register to verify that the hardware is in Memory mode. A successful write to this
register sets the SPIFI into Memory mode. The content of this register is identical to that of
the Command Register, except for the DATALEN (not used), POLL, DOUT, and
FRAMEFORM bits.
Table 453. SPIFI memory command register (MCMD, address 0x4000 3018) bit description
Bit

Symbol

Value Description

13:0

-

Reserved.

0

14

POLL

This bit should be written as 0.

0

15

DOUT

This bit should be written as 0.

0

18:16 INTLEN

This field controls how many intermediate bytes precede 0
the data. (Each such byte may require 8 or 2 SCK
cycles, depending on whether the intermediate field is in
serial, 2-bit, or 4-bit format.) Intermediate bytes are
output by the SPIFI, and include post-address control
information, dummy and delay bytes. See the
description of the Intermediate Data register for the
contents of such bytes.

20:19 FIELDFORM

This field controls how the fields of the command are
sent.
0x0

All serial. All fields of the command are serial.

0x1

Quad/dual data. Data field is quad/dual, other fields are
serial.

0x2

Serial opcode. Opcode field is serial. Other fields are
quad/dual.

0x3

All quad/dual. All fields of the command are in quad/dual
format.

23:21 FRAMEFORM

31:24 OPCODE

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Reset
value

This field controls the opcode and address fields.
0x0

Reserved.

0x1

Reserved.

0x2

Opcode one byte. Opcode, least-significant byte of
address.

0x3

Opcode two bytes. Opcode, 2 least-significant bytes of
address.

0x4

Opcode three bytes. Opcode, 3 least-significant bytes of
address.

0x5

Opcode four bytes. Opcode, 4 bytes of address.

0x6

No opcode three bytes. No opcode, 3 least-significant
bytes of address.

0x7

No opcode, 4 bytes of address.
The opcode of the command (not used for some
FRAMEFORM values).

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Chapter 24: LPC43xx/LPC43Sxx SPI Flash Interface (SPIFI)

24.6.8 SPIFI status register
This register indicates the state of the SPIFI.
Table 454. SPIFI status register (STAT, address 0x4000 301C) bit description
Bit

Symbol

Description

0

MCINIT

This bit is set when software successfully writes the Memory
0
Command register, and is cleared by Reset or by writing a 1 to the
RESET bit in this register.

1

CMD

This bit is 1 when the Command register is written. It is cleared by 0
a hardware reset, a write to the RESET bit in this register, or the
deassertion of CS which indicates that the command has
completed communication with the SPI Flash.

3:2

Reset
value

Reserved

0

4

RESET

Write a 1 to this bit to abort a current command or memory mode.
This bit is cleared when the hardware is ready for a new
command to be written to the Command register.

5

INTRQ

This bit reflects the SPIFI interrupt request. Write a 1 to this bit to 5
clear it. This bit is set when a CMD was previously 1 and has been
cleared due to the deassertion of CS.

23:6

-

Reserved

0

31:24

VERSION

The SPIFI hardware described in this chapter returns

0x02

24.7 Functional description
24.7.1 Data transfer
Serial SPI uses the signals SPIFI_SCK, SPIFI_CS,SPIFI_MISO, and SPIFI_MISO, while
quad mode adds the two IO signals SPIFI_SIO[3:2].
The SPIFI implements basic, dual, and quad SPI in half-duplex mode, in which the SPIFI
always sends a command to a serial flash memory at the start of each frame. (A frame is
the sequence of bytes transmitted during one period with CS LOW.) In general,
commands start with an opcode byte although some serial flashes allow a no-opcode
mode in which commands start with the address to be read. In write commands, the SPIFI
sends all of the data in the frame, while in read commands, the SPIFI sends the
command, and then the serial flash sends data to the SPIFI.
Classic SPI includes four modes (mode 0 to mode 3), of which the SPIFI and most serial
flashes implement modes 0 and 3. In mode 0, the SCK line is LOW between frames while
in mode 3 it is HIGH. In mode 0, the SPIFI drives the first data bits from the time that it
drives CS LOW, and drives the rest of the data on falling edges of SCK. In mode 3, the
SPIFI drives SCK LOW one-half clock period after it drives CS LOW, and drives data on
the falling edge of SCK. In either mode the serial flash samples the data on the rising
edges of SCK.
The same scheme (transmitter changes data on falling edges of SCK, receiver samples
data on rising edges) is maintained for the entire frame, including read data sent by the
serial flash to the SPIFI.

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Chapter 24: LPC43xx/LPC43Sxx SPI Flash Interface (SPIFI)

The SPI protocol avoids all issues of set-up and hold times between the clock and data
lines by using half of the SCK period to transmit the data. For high clock speeds, it is
necessary to sample read data using a feedback clock. The FBCLK bit enables the
feedback clock from the SCK pad sampling method. This provides the best possible
timing margin for both read and write data under the opposite-edge scheme.
But maximizing clock frequency is of such importance that further improvement is
sometimes needed, by means of using the whole serial clock period to transmit data. This
choice is enabled for read data by setting the RFCLK bit. When this bit is 1, the SPIFI
samples data on the falling edge of the serial clock that follows the rising edge which is
normally used. RFCLK and FBCLK and MODE3 should not all be 1 because in this case
there would be no falling edge of the feedback clock to capture the last bit of a frame.
Consult the datasheet of the serial flash device to be used for the formats of the
commands that it supports. Figure 64 shows commands consisting of an opcode field
only, sent in SPI and quad modes. All fields are multiples of 8 bits long. Bytes are sent
with the most significant bit first in SPI mode, and the most significant 4 bits first in quad
mode.

SPIFI_CS
SPIFI_SCK
SPIFI_MOSI

Opcode-only command in SPI mode

SPIFI_CS
SPIFI_SCK
IO0 (SPIFI_IO0)
IO1 (SPIFI_IO1)
IO2 (SPIFI_SIO2)
IO3 (SPIFI_SIO3)

Opcode-only command in quad mode

Fig 64. Opcode only commands

Figure 65 shows a command that reads 1 byte from the slave in SPI mode and a
command that reads 3 bytes from the slave with the opcode and input data fields both in
quad mode.

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Chapter 24: LPC43xx/LPC43Sxx SPI Flash Interface (SPIFI)

SPIFI_CS
SPIFI_SCK
SPIFI_MOSI
SPIFI_MISO

Opcode 05, input data 02, SPI mode
SPIFI_CS
SPIFI_SCK

IO3:0

A

F

B

IO3:0 driven
by Master

F

2

6

0

2

IO3:0 driven
by Slave

Opcode AF, input data BF 26 02, both fields quad mode

Fig 65. Read commands

In quad mode, the IO3:0 lines are driven by the SPIFI in opcode, address, intermediate
and output data fields, and driven by the flash memory in input data fields. In address
fields the more significant bytes are sent first.

24.7.2 Software requirements and capabilities
During device set-up, software should initialize the external serial flash device using those
commands that place it in its highest-performance mode. When this sequence is
complete, software should write the command that will be issued in response to a read
from the serial flash region of the memory map, to the Memory Command Register. If
software attempts to read the flash region after Reset, power-up, or writing the Command
Register without writing the Memory Command Register thereafter, the SPIFI responds
with an Abort error.
After writing the Memory Command Register, the contents of the flash would appear to the
system as memory mapped. This enables data access or execution from the serial flash
over AHB.
SPIFI has two operational modes:
1. Memory Mode - whereby the contents of the FLASH are memory mapped in the chip.
2. Command Mode - whereby the user can manually construct command sequences for
the flash.
SPIFI cannot switch over from Memory Mode to Command mode and vice versa without
writing 1 to the RESET bit in the SPIFI Status Register and polling until it is cleared by
hardware to ensure that the current mode has been aborted.
The SPIFI includes a cache to maximize performance for accesses to the serial flash
region of the memory map. The cache is only used in Memory mode and can be disabled.

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Chapter 24: LPC43xx/LPC43Sxx SPI Flash Interface (SPIFI)

Because the SPIFI is an AHB device, software or a DMA channel can read bytes,
halfwords, or words from the flash region.
Reads from the flash region are delayed by deasserting HREADY when necessary, until
the requested bytes are available to be read.
In Memory mode, SPIFI prefetches sequential addresses in order to improve
performance.
If no AHB accesses have taken place for a period specified by the time-out (TO) field in
the Control register, the SPIFI will deassert CS. Once a new access occurs that requires a
new fetch of data, the SPIFI will reassert CS and send a new command to fetch the
required data. This is done in order to save power in the SPI flash device.
If software reads or writes more data from the Data Register than was configured in the
DataLen field of the Command register or reads or writes when no command was issued,
the SPIFI hardware issues an abort exception.
When the serial flash needs to be programmed or erased, software should not write to the
flash region of the address map. Instead, it should write the appropriate sequence of
commands to the Command, Address, and Data registers. When an actual erase or
program operation is under way in the serial flash device, software should write a Read
Status command (with the POLL bit set) to the Command register. Thereafter:

• If INTEN in the Control register is 1, the SPIFI will interrupt the processor when the
erase or write operation (and thus the Read Status command) completes.

• If not, software can continually or periodically read the Status register until it indicates
that the Read Status command is complete.
When erasing or programming completes, software can do further programming or
erasing, or return to normal (memory mode) operation.

24.7.3 Peripheral mode DMA operation
The SPIFI inserts wait states when necessary during read and write operations by the
core to maintain synchronization between core accesses and serial data transfer with the
serial flash. This mechanism is all that is needed for load and store accesses and for
memory-to-memory transfers by a DMA channel.
The peripheral mode is a mode that supports DMA transfers in which the SPIFI acts as a
peripheral and drives a request signal to the DMA channel to control data transfer. This
mode does not necessarily move data faster than memory-to-memory operation, but it
may be advantageous in systems in which software controls dynamic transfer of code
and/or data between the serial flash and RAM on an as-needed basis. The advantage is
that clock cycles are not lost to wait states, and thus the overall operation of the AHB is
more efficient.
The DMA controller should be programmed to present word operations at the fixed
address of the Data Register to have a burst size of one transfer. The SPIFI drives the
DMA request to the DMA controller.
To use this mode, software should write the Command register to start the command and
program a DMA channel as described above to transfer data between the Data register
and RAM. The SPIFI asserts the DMA request when:
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Chapter 24: LPC43xx/LPC43Sxx SPI Flash Interface (SPIFI)

• DRQEN in the Control register is 1.
• MCINIT is 0.
• There are at least 4 bytes in the FIFO for a read operation, or at least 4 empty byte
locations in the FIFO for a write/program operation.
.

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Chapter 25: LPC43xx/LPC43Sxx USB0 Host/Device/OTG
controller
Rev. 2.4 — 22 August 2018

User manual

25.1 How to read this chapter
The USB0 Host/Device/OTG controller is available on parts LPC436x/LPC43S6x,
LPC435x/LPC43S5x, LPC433x/LPC43S3x, and LPC432x.
USB frame length adjustment is available for parts with on-chip flash only.

25.2 Basic configuration
The USB0 Host/Device/OTG controller is configured as follows:

• See Table 455 for clocking and power control.
• The USB0 is reset by the USB0_RST (reset # 17).
• The USB0 OTG interrupt is connected to interrupt slot # 8 in the NVIC, and the
wake-up request indicator is connected to slot # 9 in the Event router (see
Section 25.12.4).

• Power to the USB0 on-chip PHY is controlled through the CREG block (see Table 96).
The on-chip PHY is powered down by default unless the USB0 boot mode is selected.
To use the USB0 controller, enable the PHY in the CREG0 register, bit 5.

• The SOF/VF indicator can be connected to Timer3 or the to SCT through the GIMA
(see Section 25.7.7 and Table 207).

• The registers for frame length adjustment in USB host mode are located in the CREG
block (see Table 111; parts with on-chip flash only).
Table 455. USB0 clocking and power control
Base clock

Branch clock

USB0 clock

BASE_USB0_CLK CLK_USB0

USB0 register
interface clock

BASE_M4_CLK

Operating
frequency

Notes

480 MHz

Uses PLL0USB dedicated to
USB0. CLK_USB0 must be
set to the 480 MHz clock in
all USB modes (low-speed,
full-speed, and high-speed
modes).

CLK_M4_USB0 up to
204 MHz

-

25.3 Features
•
•
•
•
•
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Contains on-chip high-speed UTMI+ compliant transceiver (PHY).
Supports all high-speed, full-speed, and low-speed USB-compliant peripherals.
Complies with Universal Serial Bus specification 2.0.
Complies with USB On-The-Go supplement.
Complies with Enhanced Host Controller Interface (EHCI) Specification.
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Chapter 25: LPC43xx/LPC43Sxx USB0 Host/Device/OTG controller

•
•
•
•

Supports auto USB 2.0 mode discovery.
Supports software HNP and SRP for OTG peripherals.
Supports power management
Supports six logical endpoints including one control endpoint for a total of 12 physical
endpoints.

• This module has its own, integrated DMA engine.
• Can be used together with the audio PLL for USB streaming applications.
• Support for frame length adjustment to correlate the SOF signal with an external clock
(see Section 25.7.7.1).

25.4 Introduction
Universal Serial Bus (USB) is a standard protocol developed to connect several types of
devices to each other in order to exchange data or for other purposes. Many portable
devices can benefit from the ability to communicate to each other over the USB interface
without intervention of a host PC. The addition of the On-The-Go functionality to USB
makes this possible without losing the benefits of the standard USB protocol. Examples of
USB devices are: PC, mouse, keyboard, MP3 player, digital camera, USB storage device
(USB stick).

25.4.1 Block diagram

LPC43xx
SYSTEM
MEMORY

ARM Cortex-M4

AHB

master

slave

TX-BUFFER
(DUAL-PORT RAM)
USB 2.0 HIGH-SPEED
OTG
RX-BUFFER
(DUAL-PORT RAM)

INTERNAL
HIGH-SPEED
PHY

USB0_VBUS
USB0_DP
USB0_DM
USB0_ID

to
PC/
Mobile/
CE

GROUND

Fig 66. High-speed USB OTG block diagram

25.4.2 About USB On-The-Go
The USB On-The-Go block enables usage in both device mode and in host mode. This
means that you can connect to a PC to exchange data, but also to another USB device
such as a digital camera or MP3 player.

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Chapter 25: LPC43xx/LPC43Sxx USB0 Host/Device/OTG controller

25.4.3 USB acronyms and abbreviations
Table 456. USB related acronyms
Acronym

Description

ATX

Analog Transceiver

DCD

Device Controller Driver

dQH

device Endpoint Queue Head

dTD

device Transfer Descriptor

EOP

End Of Packet

EP

End Point

FS

Full Speed

HCD

Host Controller Driver

HS

High Speed

LS

Low Speed

MPS

Maximum Packet Size

NAK

Negative Acknowledge

OTG

On-The-Go

PID

Packet Identifier

QH

Queue Head

SE0

Single Ended 0

SOF

Start Of Frame

TT

Transaction Translator

USB

Universal Serial Bus

25.4.4 Transmit and receive buffers
The USB OTG controller contains a Transmit buffer to store data to be transmitted on the
USB and a Receive buffer to store data received from the USB. The Receive buffer
contains 256 words. The Transmit buffer contains 128 words for each endpoint in device
mode and 512 words in host mode.

25.4.5 Fixed endpoint configuration
Table 457 shows the supported endpoint configurations. The Maximum Packet Size (see
Table 458) is dependent on the type of endpoint and the device configuration (low-speed,
full-speed, or high-speed).
Table 457. Fixed endpoint configuration

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Logical
endpoint

Physical
endpoint

Endpoint type

Direction

0

0

Control

Out

0

1

Control

In

1

2

Interrupt/Bulk/Isochronous

Out

1

3

Interrupt/Bulk/Isochronous

In

2

4

Interrupt/Bulk/Isochronous

Out

2

5

Interrupt/Bulk/Isochronous

In

3

6

Interrupt/Bulk/Isochronous

Out

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Chapter 25: LPC43xx/LPC43Sxx USB0 Host/Device/OTG controller

Table 457. Fixed endpoint configuration
Logical
endpoint

Physical
endpoint

Endpoint type

Direction

3

7

Interrupt/Bulk/Isochronous

In

4

8

Interrupt/Bulk/Isochronous

Out

4

9

Interrupt/Bulk/Isochronous

In

5

10

Interrupt/Bulk/Isochronous

Out

5

11

Interrupt/Bulk/Isochronous

In

Table 458. USB Packet size
Endpoint type

Speed

Packet size (byte)

Control

Low-speed

8

Full-speed

8, 16, 32, or 64

High-speed

64

Low-speed

n/a

Full-speed

up to 1023

High-speed

up to 1024

Low-speed

up to 8

Full-speed

up to 64

Isochronous

Interrupt

Bulk

High-speed

up to 1024

Low-speed

n/a

Full-speed

8, 16, 32, or 64

High-speed

8, 16, 32, 64, or 512

25.5 Pin description

Table 459. USB0 pin description
Pin function

Direction

Description

USB0_IND0

O

Port indicator LED control output.

USB0_IND1

O

Port indicator LED control output.

USB0_PWR_FAULT

I

Port power fault signal indicating overcurrent condition; this signal monitors
over-current on the USB bus (external circuitry required to detect over-current
condition).

USB0_PPWR

O

VBUS drive signal (towards external charge pump or power management unit);
indicates that VBUS must be driven (active HIGH).
Add a pull-down resistor to disable the power switch at reset. This signal has
opposite polarity compared to the USB_PPWR used on other NXP LPC parts.

USB0_DP

I/O

USB0 bidirectional D+ line. The D+ line has an internal 1.5 k pull-up. This pull-up is
enabled when software sets the RS bit (Bit 0) in the USBCMD register and the USB0
controller sees a valid VBUS voltage level (above ~1.8V) on the VBUS pin. Do not
add an external series resistor.

USB0_DM

I/O

USB0 bidirectional D line. The D- line has an internal 1.5 k pull-up. This pull-up is
enabled when software sets RS bit (BIT_0) in the USBCMD register and the USB0
controller sees a valid VBUS voltage level (above ~1.8V) on the VBUS pin. Do not
add an external series resistor.

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Chapter 25: LPC43xx/LPC43Sxx USB0 Host/Device/OTG controller

Table 459. USB0 pin description
Pin function

Direction

Description

USB0_VBUS

I

VBUS pin (power on USB cable). This pin includes an internal pull-down resistor of
64 kOhm (typical) ± 16 kOhm. For maximum load CL = 6.5 uF and maximum
pull-down resistor Rpd = 80 kOhm, the VBUS signal takes about 2 s to fall from
VBUS = 5 V to VBUS = 0.2 V when it is no longer driven.
Remark: This input is only 5 V tolerant when VDDIO is present.

USB0_ID

I

Indicates to the transceiver whether connected as an A-device (USB0_ID LOW) or
B-device (USB0_ID HIGH). For OTG this pin has an internal pull-up resistor.

USB0_RREF

-

12.0 k (accuracy 1%) on-board resistor to ground for current reference;

USB0_VDDA3V3_
DRIVER

-

Separate analog 3.3 V power supply for driver.

USB0_VDDA3V3

-

USB 3.3 V separate power supply voltage

USB0_VSSA_TERM

-

Dedicated analog ground for clean reference for termination resistors.

USB0_VSSA_REF

-

Dedicated clean analog ground for generation of reference currents and voltages.

25.5.1 Requirements for connecting the USB0_VBUS/USB1_VBUS signal
The USB0_VBUS and USB1_VBUS pins are only 5 V tolerant when VDDIO is present.
Therefore, special precautions are necessary when the USB0 controller is implemented
as a USB-powered USB device or an OTG product.
For a USB OTG product, it is important to be able to detect the VBUS level and to charge
and discharge VBUS. This requires adding active devices that disconnect the link when
VDDIO is not present.
For self-powered USB products that only use USB0 and that do not run in OTG mode,
USB0_VBUS can be left disconnected as long as the VC bit in the OTGSC register is set.
When this bit is set a voltage is applied to the USB0_VBUS pin internally which is the
equivalent of connecting the pin to a 5 V VBUS supply. Keeping the USB0_VBUS
disconnected, ensures that OTG VBUS line pulsing does not go towards the cable.

25.6 Register description
Table 460. Register access abbreviations

UM10503

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Abbreviation

Description

R/W

Read/Write

R/WC

Read/Write one to Clear

R/WO

Read/Write Once

RO

Read Only

WO

Write Only

R/WS

Read/Write one to Set

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Chapter 25: LPC43xx/LPC43Sxx USB0 Host/Device/OTG controller

Table 461. Register overview: USB0 OTG controller (register base address 0x4000 6000)
Name

Access Address
offset

Description

Reset
value

Reset value Reference
after USB0
boot

-

-

0x000 0x08F

Reserved

-

-

Device/host capability registers
SBUSCFG

R/W

0x90

System bus interface configuration

0

Table 462

CAPLENGTH

RO

0x100

Capability register length

0x0100
0040

0x0100
0040

Table 463

HCSPARAMS

RO

0x104

Host controller structural parameters 0x0001
0011

0x0001
0011

Table 464

HCCPARAMS

RO

0x108

Host controller capability parameters 0x0000
0006

0x0000
0006

Table 465

DCIVERSION

RO

0x120

Device interface version number

0x0000
0001

0x0000
0001

Table 466

DCCPARAMS

RO

0x124

Device controller capability
parameters

0x0000
0186

0x0000
0186

Table 467

-

-

0x128 0x13C

Reserved

-

Device/host operational registers
USBCMD_D

R/W

0x140

USB command (device mode)

0x0008
0000

0

Table 468

USBCMD_H

R/W

0x140

USB command (host mode)

0x0008
0000

-

Table 469

USBSTS_D

R/W

0x144

USB status (device mode)

0

0x0000
0080

Table 471

USBSTS_H

R/W

0x144

USB status (host mode)

0

-

Table 472

USBINTR_D

R/W

0x148

USB interrupt enable (device mode)

0

0x0001
0147

Table 473

USBINTR_H

R/W

0x148

USB interrupt enable (host mode)

0

-

Table 474

FRINDEX_D

R/W

0x14C

USB frame index (device mode)

0

0x0000
1F20

Table 475

FRINDEX_H

R/W

0x14C

USB frame index (host mode)

0

-

Table 476

-

-

0x150

Reserved

DEVICEADDR

R/W

0x154

USB device address (device mode)

0

0x0400
0000

Table 478

PERIODICLISTBASE

R/W

0x154

Frame list base address (host mode) 0

-

Table 479

ENDPOINTLISTADDR R/W

0x158

Address of endpoint list in memory

0

0x2000
0000

Table 480

ASYNCLISTADDR

R/W

0x158

Asynchronous list address

0

0

Table 481

TTCTRL

R/W

0x15C

Asynchronous buffer status for
embedded TT (host mode)

0

0

Table 482

BURSTSIZE

R/W

0x160

Programmable burst size

0

0

Table 483

TXFILLTUNING

R/W

0x164

Host transmit pre-buffer packet
tuning (host mode)

0

0

Table 484

-

-

0x168 0x170

Reserved

-

-

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Chapter 25: LPC43xx/LPC43Sxx USB0 Host/Device/OTG controller

Table 461. Register overview: USB0 OTG controller (register base address 0x4000 6000) …continued
Name

Access Address
offset

Description

Reset
value

Reset value Reference
after USB0
boot

BINTERVAL

R/W

0x174

Length of virtual frame

0

0

Table 485

ENDPTNAK

R/W

0x178

Endpoint NAK (device mode)

0

0

Table 486

ENDPTNAKEN

R/W

0x17C

Endpoint NAK Enable (device mode) 0

0

Table 487

-

-

0x180

Reserved

-

-

PORTSC1_D

R/W

0x184

Port 1 status/control (device mode)

0

0x3C00
0004

Table 488

PORTSC1_H

R/W

0x184

Port 1 status/control (host mode)

0

-

Table 489

-

-

0x188 0x1A0

-

-

-

OTGSC

R/W

0x1A4

OTG status and control

0

0x0020
0D09

Table 491

USBMODE_D

R/W

0x1A8

USB device mode (device mode)

0

0xA

Table 492

USBMODE_H

R/W

0x1A8

USB device mode (host mode)

0

-

Table 493

Device endpoint registers
ENDPTSETUPSTAT

R/W

0x1AC

Endpoint setup status

0

0

Table 494

ENDPTPRIME

R/W

0x1B0

Endpoint initialization

0

0

Table 495

ENDPTFLUSH

R/W

0x1B4

Endpoint de-initialization

0

0

Table 496

ENDPTSTAT

RO

0x1B8

Endpoint status

0

0

Table 497

ENDPTCOMPLETE

R/W

0x1BC

Endpoint complete

0

0

Table 498

ENDPTCTRL0

R/W

0x1C0

Endpoint control 0

0

0

Table 499

ENDPTCTRL1

R/W

0x1C4

Endpoint control 1

0

0

Table 500

ENDPTCTRL2

R/W

0x1C8

Endpoint control 2

0

0

Table 500

ENDPTCTRL3

R/W

0x1CC

Endpoint control 3

0

0

Table 500

ENDPTCTRL4

R/W

0x1D0

Endpoint control 4

0

0

Table 500

ENDPTCTRL5

R/W

0x1D4

Endpoint control 5

0

0

Table 500

25.6.1 Use of registers
The register interface has bit functions described for device mode and bit functions
described for host mode. However, during OTG operations it is necessary to perform
tasks independent of the controller mode.
The only way to transition the controller mode out of host or device mode is by setting the
controller reset bit. Therefore, it is also necessary for the OTG tasks to be performed
independently of a controller reset as well as independently of the controller mode.

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Chapter 25: LPC43xx/LPC43Sxx USB0 Host/Device/OTG controller

Hardware reset or
USBCMD RST bit = 1

IDLE
MODE = 00

write 10 to USBMODE

DEVICE
MODE = 10

write 11 to USBMODE

HOST
MODE = 11

Fig 67. USB controller modes

The following registers and register bits are used for OTG operations. The values of these
register bits are independent of the controller mode and are not affected by a write to the
RESET bit in the USBCMD register.

•
•
•
•

All identification registers
All device/host capabilities registers
All bits of the OTGSC register (Section 25.6.16)
The following bits of the PORTSC register (Section 25.6.15):
– PTS (parallel interface select)
– STS (serial transceiver select)
– PTW (parallel transceiver width)
– PHCD (PHY low power suspend)
– WKOC, WKDC, WKCN (wake signals)
– PIC[1:0] (port indicators)
– PP (port power)

25.6.2 Device/host capability registers
The SBUSCFG register controls the burst length used by the USB0 controller.
Remark: The recommended value for AHBBRST is 0x7. Changing the AHBBRST field
while an AMBA AHB transaction is in progress will yield undefined results! One possible
way of ensuring that no undefined results occur is to set the Run/Stop (RS) bit to zero in
the USBCMD register, after the HCHALTED is detected in USBSTS.

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Chapter 25: LPC43xx/LPC43Sxx USB0 Host/Device/OTG controller

Table 462. System bus interface configuration register (SBUSCFG - address 0x4000 6090) bit description
Bit

Symbol

2:0

AHB_BRST

31:3

-

Value

Description

Access

Reset
value

The burst length used by the USB controller can be selected using R/W
these bits. This field controls the RX and TX burst length in
BURSTSIZE register.
0x0

INCR burst of unspecified length

0x1

INCR4, non-multiple transfers of INCR4 will be decomposed into
singles

0x2

INCR8, non-multiple transfers of INCR8, will be decomposed into
INCR4 or singles

0x3

INCR16, non-multiple transfers of INCR16, will be decomposed
into INCR8, INCR4, or singles

0x4

This value is reserved and should not be used

0x5

INCR4, non-multiple transfers of INCR4 will be decomposed into
smaller unspecified length bursts

0x6

INCR8, non-multiple transfers of INCR8 will be decomposed into
smaller unspecified length bursts

0x7

INCR16, non-multiple transfers of INCR16 will be decomposed into
smaller unspecified length bursts.

Reserved

Not used in device mode. Writing a one to this bit when the device
mode is selected, will have undefined results.

0

-

-

Table 463. CAPLENGTH register (CAPLENGTH - address 0x4000 6100) bit description
Bit

Symbol

Description

Reset
value

Access

7:0

CAPLENGTH

Indicates offset to add to the register base
address at the beginning of the Operational
Register

0x40

RO

23:8

HCIVERSION

BCD encoding of the EHCI revision number
supported by this host controller.

0x100

RO

31:24

-

These bits are reserved and should be set to
zero.

-

-

Table 464. HCSPARAMS register (HCSPARAMS - address 0x4000 6104) bit description

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Bit

Symbol

Description

Reset
value

Access

3:0

N_PORTS

Number of downstream ports. This field specifies
the number of physical downstream ports
implemented on this host controller.

0x1

RO

4

PPC

Port Power Control. This field indicates whether
the host controller implementation includes port
power control.

0x1

RO

7:5

-

These bits are reserved and should be set to zero. -

-

11:8

N_PCC

Number of Ports per Companion Controller. This
field indicates the number of ports supported per
internal Companion Controller.

RO

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Chapter 25: LPC43xx/LPC43Sxx USB0 Host/Device/OTG controller

Table 464. HCSPARAMS register (HCSPARAMS - address 0x4000 6104) …continuedbit
Bit

Symbol

Description

Reset
value

Access

15:12

N_CC

Number of Companion Controller. This field
indicates the number of companion controllers
associated with this USB2.0 host controller.

0x0

RO

16

PI

Port indicators. This bit indicates whether the
ports support port indicator control.

0x1

RO

19:17

-

These bits are reserved and should be set to zero. -

-

23:20

N_PTT

Number of Ports per Transaction Translator. This 0x0
field indicates the number of ports assigned to
each transaction translator within the USB2.0 host
controller.

RO

27:24

N_TT

Number of Transaction Translators. This field
indicates the number of embedded transaction
translators associated with the USB2.0 host
controller.

RO

31:28

-

These bits are reserved and should be set to zero. -

0x0

-

Table 465. HCCPARAMS register (HCCPARAMS - address 0x4000 6108) bit description
Bit

Symbol

Description

Reset
value

Access

0

ADC

64-bit Addressing Capability. If zero, no 64-bit addressing
capability is supported.

0

RO

1

PFL

Programmable Frame List Flag. If set to one, then the
1
system software can specify and use a smaller frame list
and configure the host controller via the USBCMD register
Frame List Size field. The frame list must always be
aligned on a 4K-boundary. This requirement ensures that
the frame list is always physically contiguous.

RO

2

ASP

Asynchronous Schedule Park Capability. If this bit is set to 1
a one, then the host controller supports the park feature
for high-speed queue heads in the Asynchronous
Schedule.The feature can be disabled or enabled and set
to a specific level by using the Asynchronous Schedule
Park Mode Enable and Asynchronous Schedule Park
Mode Count fields in the USBCMD register.

RO

7:4

IST

Isochronous Scheduling Threshold. This field indicates,
relative to the current position of the executing host
controller, where software can reliably update the
isochronous schedule.

0

RO

15:8

EECP

EHCI Extended Capabilities Pointer. This optional field
indicates the existence of a capabilities list.

0

RO

31:16

-

These bits are reserved and should be set to zero.

-

-

Table 466. DCIVERSION register (DCIVERSION - address 0x4000 6120) bit description

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Bit

Symbol

Description

15:0

DCIVERSION The device controller interface conforms to the
two-byte BCD encoding of the interface version
number contained in this register.
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Reset
value

Access

0x1

RO

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Chapter 25: LPC43xx/LPC43Sxx USB0 Host/Device/OTG controller

Table 467. DCCPARAMS (address 0x4000 6124)
Bit

Symbol

Description

Reset value Access

4:0

DEN

Device Endpoint Number.

0x4

RO

6:5

-

These bits are reserved and should be set to zero.

-

-

7

DC

Device Capable.

0x1

RO

8

HC

Host Capable.

0x1

RO

31:9

-

These bits are reserved and should be set to zero.

-

-

25.6.3 USB Command register (USBCMD)
The host/device controller executes the command indicated in this register.

25.6.3.1 Device mode
Table 468. USB Command register in device mode (USBCMD_D - address 0x4000 6140) bit description
Bit

Symbol

0

RS

1

Value

Description

Access

Reset
value

Run/Stop

R/W

0

R/W

0

0

Writing a 0 to this bit will cause a detach event.

1

Writing a one to this bit will cause the device controller to enable a pull-up
on USB_DP and initiate an attach event. This control bit is not directly
connected to the pull-up enable, as the pull-up will become disabled upon
transitioning into high-speed mode. Software should use this bit to prevent
an attach event before the device controller has been properly initialized.

RST

Controller reset.
Software uses this bit to reset the controller. This bit is set to zero by the
host/device Controller when the reset process is complete. Software
cannot terminate the reset process early by writing a zero to this register.
0

Set to 0 by hardware when the reset process is complete.

1

When software writes a one to this bit, the device controller resets its
internal pipelines, timers, counters, state machines etc. to their initial
values. Writing a one to this bit when the device is in the attached state is
not recommended, since the effect on an attached host is undefined. In
order to ensure that the device is not in an attached state before initiating a
device controller reset, all primed endpoints should be flushed and the
USBCMD Run/Stop bit should be set to 0.

3:2

-

-

Not used in device mode.

-

0

4

-

-

Not used in device mode.

-

0

5

-

-

Not used in device mode.

-

0

6

-

-

Not used in device mode. Writing a one to this bit when the device mode is selected, will have undefined results.

-

7

-

-

Reserved. These bits should be set to 0.

-

-

9:8

-

-

10

-

11

-

12

-

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Not used in Device mode.

-

-

Reserved.These bits should be set to 0.

-

0

Not used in Device mode.

-

Reserved.These bits should be set to 0.

-

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Chapter 25: LPC43xx/LPC43Sxx USB0 Host/Device/OTG controller

Table 468. USB Command register in device mode (USBCMD_D - address 0x4000 6140) bit description …continued
Bit

Symbol

13

SUTW

Value

Description

Access

Reset
value

Setup trip wire

R/W

0

R/W

0

During handling a setup packet, this bit is used as a semaphore to ensure
that the setup data payload of 8 bytes is extracted from a QH by the DCD
without being corrupted. If the setup lockout mode is off (see USBMODE
register) then there exists a hazard when new setup data arrives while the
DCD is copying the setup data payload from the QH for a previous setup
packet. This bit is set and cleared by software and will be cleared by
hardware when a hazard exists. (See Section 25.10).
14

ATDTW

Add dTD trip wire
This bit is used as a semaphore to ensure the to proper addition of a new
dTD to an active (primed) endpoint’s linked list. This bit is set and cleared
by software during the process of adding a new dTD. See also
Section 25.10.
This bit shall also be cleared by hardware when its state machine is hazard
region for which adding a dTD to a primed endpoint may go unrecognized.

15

-

Not used in device mode.

-

-

23:16

ITC

Interrupt threshold control.

R/W

0x8

The system software uses this field to set the maximum rate at which the
host/device controller will issue interrupts. ITC contains the maximum
interrupt interval measured in micro-frames. Valid values are shown below.
All other values are reserved.
0x0 = Immediate (no threshold)
0x1 = 1 micro frame.
0x2 = 2 micro frames.
0x8 = 8 micro frames.
0x10 = 16 micro frames.
0x20 = 32 micro frames.
0x40 = 64 micro frames.
31:24

-

Reserved

0

25.6.3.2 Host mode
Table 469. USB Command register in host mode (USBCMD_H - address 0x4000 6140) bit description - host mode
Bit

Symbol

0

RS

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Value

Description

Access Reset
value

Run/Stop

R/W

0

When this bit is set to 0, the Host Controller completes the current
transaction on the USB and then halts. The HC Halted bit in the
status register indicates when the Host Controller has finished the
transaction and has entered the stopped state. Software should not
write a one to this field unless the host controller is in the Halted state
(i.e. HCHalted in the USBSTS register is a one).

1

When set to a 1, the Host Controller proceeds with the execution of
the schedule. The Host Controller continues execution as long as this
bit is set to a one.

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Chapter 25: LPC43xx/LPC43Sxx USB0 Host/Device/OTG controller

Table 469. USB Command register in host mode (USBCMD_H - address 0x4000 6140) bit description - host mode
Bit

Symbol

1

RST

2

Value

Description

Access Reset
value

Controller reset.
R/W
Software uses this bit to reset the controller. This bit is set to zero by
the host/device controller when the reset process is complete.
Software cannot terminate the reset process early by writing a zero to
this register.
0

This bit is set to zero by hardware when the reset process is
complete.

1

When software writes a one to this bit, the Host Controller resets its
internal pipelines, timers, counters, state machines etc. to their initial
value. Any transaction currently in progress on USB is immediately
terminated. A USB reset is not driven on downstream ports. Software
should not set this bit to a one when the HCHalted bit in the USBSTS
register is a zero. Attempting to reset an actively running host
controller will result in undefined behavior.

FS0

0

0

Bit 0 of the Frame List Size bits. See Table 470.
This field specifies the size of the frame list that controls which bits in
the Frame Index Register should be used for the Frame List Current
index. Note that this field is made up from USBCMD bits 15, 3, and 2.

3

FS1

Bit 1 of the Frame List Size bits. See Table 470.

4

PSE

This bit controls whether the host controller skips processing the
periodic schedule.

5

6

0

Do not process the periodic schedule.

1

Use the PERIODICLISTBASE register to access the periodic
schedule.

ASE

0

This bit controls whether the host controller skips processing the
asynchronous schedule.
0

Do not process the asynchronous schedule.

1

Use the ASYNCLISTADDR to access the asynchronous schedule.

IAA

This bit is used as a doorbell by software to tell the host controller to
issue an interrupt the next time it advances asynchronous schedule.
0

The host controller sets this bit to zero after it has set the Interrupt on
Sync Advance status bit in the USBSTS register to one.

1

Software must write a 1 to this bit to ring the doorbell.

R/W

0

R/W

0

R/W

0

When the host controller has evicted all appropriate cached schedule
states, it sets the Interrupt on Async Advance status bit in the
USBSTS register. If the Interrupt on Sync Advance Enable bit in the
USBINTR register is one, then the host controller will assert an
interrupt at the next interrupt threshold.
Software should not write a one to this bit when the asynchronous
schedule is inactive. Doing so will yield undefined results.
7

-

9:8

ASP1_0

-

Reserved

0

Asynchronous schedule park mode
R/W
Contains a count of the number of successive transactions the host
controller is allowed to execute from a high-speed queue head on the
Asynchronous schedule before continuing traversal of the
Asynchronous schedule. Valid values are 0x1 to 0x3.

11

Remark: Software must not write 00 to this bit when Park Mode
Enable is one as this will result in undefined behavior.
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Chapter 25: LPC43xx/LPC43Sxx USB0 Host/Device/OTG controller

Table 469. USB Command register in host mode (USBCMD_H - address 0x4000 6140) bit description - host mode
Bit

Symbol

Value

Description

Access Reset
value

10

-

-

Reserved.

-

0

11

ASPE

Asynchronous Schedule Park Mode Enable

R/W

1

-

0

0

Park mode is disabled.

1

Park mode is enabled.

12

-

-

Reserved.

13

-

-

Not used in Host mode.

-

14

-

-

Reserved.

-

0

15

FS2

Bit 2 of the Frame List Size bits. See Table 470.

-

0

23:16

ITC

Interrupt threshold control.

R/W

0x8

The system software uses this field to set the maximum rate at which
the host/device controller will issue interrupts. ITC contains the
maximum interrupt interval measured in micro-frames. Valid values
are shown below. All other values are reserved.
0x0 = Immediate (no threshold)
0x1 = 1 micro frame.
0x2 = 2 micro frames.
0x8 = 8 micro frames.
0x10 = 16 micro frames.
0x20 = 32 micro frames.
0x40 = 64 micro frames.
31:24

-

Reserved

0

Table 470. Frame list size values
USBCMD bit 15

USBCMD bit 3

USBCMD bit 2

Frame list size

0

0

0

1024 elements (4096 bytes) - default
value

0

0

1

512 elements (2048 bytes)

0

1

0

256 elements (1024 bytes)

0

1

1

128 elements (512 bytes)

1

0

0

64 elements (256 bytes)

1

0

1

32 elements (128 bytes)

1

1

0

16 elements (64 bytes)

1

1

1

8 elements (32 bytes)

25.6.4 USB Status register (USBSTS)
This register indicates various states of the Host/Device controller and any pending
interrupts. Software sets a bit to zero in this register by writing a one to it.
Remark: This register does not indicate status resulting from a transaction on the serial
bus.

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25.6.4.1 Device mode
Table 471. USB Status register in device mode (USBSTS_D - address 0x4000 6144) register bit description
Bit

Symbol

0

UI

1

2

Value

Description

Reset
value

Access

USB interrupt

0

R/WC

0

R/WC

0

R/WC

0

This bit is cleared by software writing a one to it.

1

This bit is set by the device controller under the
following conditions:

UEI

•

when the cause of an interrupt is a
completion of a USB transaction where the
Transfer Descriptor (TD) has an interrupt on
complete (IOC) bit set.

•

when a short packet is detected. A short
packet is when the actual number of bytes
received was less than the expected number
of bytes.

•

when a SETUP packet is received,

USB error interrupt
0

This bit is cleared by software writing a one to it.

1

When completion of a USB transaction results in
an error condition, this bit is set by the host/device
controller. This bit is set along with the USBINT
bit, if the TD on which the error interrupt occurred
also had its interrupt on complete (IOC) bit set.
The device controller detects resume signaling
only (see Section 25.10.11.6).

PCI

Port change detect.
0

This bit is cleared by software writing a one to it.

1

The device controller sets this bit to a one when
the port controller enters the full or high-speed
operational state. When the port controller exits
the full or high-speed operation states due to
Reset or Suspend events, the notification
mechanisms are the USB Reset Received bit
(URI) and the DCSuspend bits (SLI) respectively.

3

-

Not used in Device mode.

4

SEI

System Error

0

-

0

-

The USB Controller sets this bit to 1 when a
serious error occurs during a system access
involving the USB Controller module. Conditions
that set this bit to 1 include AHB Parity error, AHB
Master Abort, and AHB Target Abort. When this
error occurs, the USB Controller clears the
Run/Stop bit in the Command register to prevent
further execution of the scheduled TDs.
5

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AAI

Not used in Device mode.

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Chapter 25: LPC43xx/LPC43Sxx USB0 Host/Device/OTG controller

Table 471. USB Status register in device mode (USBSTS_D - address 0x4000 6144) register bit description
Bit

Symbol

6

URI

7

8

Value

Description

Reset
value

Access

USB reset received

0

R/WC

0

R/WC

0

R/WC

0

This bit is cleared by software writing a one to it.

1

When the device controller detects a USB Reset
and enters the default state, this bit will be set to a
one.

0

This bit is cleared by software writing a one to it.

1

When the device controller detects a Start Of
(micro) Frame, this bit will be set to a one. When
a SOF is extremely late, the device controller will
automatically set this bit to indicate that an SOF
was expected. Therefore, this bit will be set
roughly every 1 ms in device FS mode and every
125 s in HS mode and will be synchronized to
the actual SOF that is received. Since the device
controller is initialized to FS before connect, this
bit will be set at an interval of 1ms during the
prelude to connect and chirp.

SRI

SOF received

SLI

DCSuspend
0

The device controller clears the bit upon exiting
from a Suspended state. This bit is cleared by
software writing a one to it.

1

When a device controller enters a Suspended
state from an active state, this bit will be set to a
one.

11:9

-

-

Reserved. Software should only write 0 to
reserved bits.

12

-

-

Not used in Device mode.

0

13

-

-

Not used in Device mode.

0

14

-

-

Not used in Device mode.

0

15

-

-

Not used in Device mode.

0

16

NAKI

NAK interrupt bit

0

RO

0

This bit is automatically cleared by hardware
when the all the enabled TX/RX Endpoint NAK
bits are cleared.

1

It is set by hardware when for a particular
endpoint both the TX/RX Endpoint NAK bit and
the corresponding TX/RX Endpoint NAK Enable
bit are set.

-

Reserved. Software should only write 0 to
reserved bits.

0

-

17

-

18

-

Not used in Device mode.

0

-

19

-

Not used in Device mode.

0

-

31:20

-

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-

Reserved. Software should only write 0 to
reserved bits.

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Chapter 25: LPC43xx/LPC43Sxx USB0 Host/Device/OTG controller

25.6.4.2 Host mode
Table 472. USB Status register in host mode (USBSTS_H - address 0x4000 6144) register bit description
Bit

Symbol Value

Description

Reset Access
value

0

UI

USB interrupt (USBINT)

0

R/WC

0

R/WC

0

R/WC

0

R/WC

0

R/WC

0

This bit is cleared by software writing a one to it.

1

This bit is set by the host/device controller when the cause of an interrupt is
a completion of a USB transaction where the Transfer Descriptor (TD) has
an interrupt on complete (IOC) bit set.
This bit is also set by the host/device controller when a short packet is
detected. A short packet is when the actual number of bytes received was
less than the expected number of bytes.

1

2

3

4

UEI

USB error interrupt (USBERRINT)
0

This bit is cleared by software writing a one to it.

1

When completion of a USB transaction results in an error condition, this bit
is set by the host/device controller. This bit is set along with the USBINT bit,
if the TD on which the error interrupt occurred also had its interrupt on
complete (IOC) bit set.

0

This bit is cleared by software writing a one to it.

1

The Host Controller sets this bit to a one when on any port a Connect
Status occurs, a Port Enable/Disable Change occurs, or the Force Port
Resume bit is set as the result of a J-K transition on the suspended port.

PCI

Port change detect.

FRI

Frame list roll-over
0

This bit is cleared by software writing a one to it.

1

The Host Controller sets this bit to a one when the Frame List Index rolls
over from its maximum value to zero. The exact value at which the rollover
occurs depends on the frame list size. For example, if the frame list size (as
programmed in the Frame List Size field of the USBCMD register) is 1024,
the Frame Index Register rolls over every time FRINDEX bit 13 toggles.
Similarly, if the size is 512, the Host Controller sets this bit to a one every
time FRINDEX bit 12 toggles (see Section 25.6.6).

SEI

System Error
The USB Controller sets this bit to 1 when a serious error occurs during a
system access involving the USB Controller module. Conditions that set
this bit to 1 include AHB Parity error, AHB Master Abort, and AHB Target
Abort. When this error occurs, the USB Controller clears the Run/Stop bit in
the Command register to prevent further execution of the scheduled TDs.

5

AAI

6

-

7

SRI

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Interrupt on async advance
0

This bit is cleared by software writing a one to it.

1

System software can force the host controller to issue an interrupt the next
time the host controller advances the asynchronous schedule by writing a
one to the Interrupt on Async Advance Doorbell bit in the USBCMD
register. This status bit indicates the assertion of that interrupt source.

-

Not used by the Host controller.

0

R/WC

SOF received

0

R/WC

0

This bit is cleared by software writing a one to it.

1

In host mode, this bit will be set every 125 s and can be used by host
controller driver as a time base.
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Chapter 25: LPC43xx/LPC43Sxx USB0 Host/Device/OTG controller

Table 472. USB Status register in host mode (USBSTS_H - address 0x4000 6144) register bit description …continued
Bit

Symbol Value

Description

Reset Access
value

8

-

-

Not used by the Host controller.

-

-

11:9

-

-

Reserved.

12

HCH

1

RO

0

RO

0

RO

13

HCHalted
0

The RS bit in USBCMD is set to zero. Set by the host controller.

1

The Host Controller sets this bit to one after it has stopped executing
because of the Run/Stop bit being set to 0, either by software or by the
Host Controller hardware (e.g. because of an internal error).

RCL

Reclamation
0
1

14

PS

No empty asynchronous schedule detected.
An empty asynchronous schedule is detected. Set by the host controller.
Periodic schedule status
This bit reports the current real status of the Periodic Schedule. The Host
Controller is not required to immediately disable or enable the Periodic
Schedule when software transitions the Periodic Schedule Enable bit in the
USBCMD register. When this bit and the Periodic Schedule Enable bit are
the same value, the Periodic Schedule is either enabled (if both are 1) or
disabled (if both are 0).

15

0

The periodic schedule status is disabled.

1

The periodic schedule status is enabled.

AS

Asynchronous schedule status

0

This bit reports the current real status of the Asynchronous Schedule. The
Host Controller is not required to immediately disable or enable the
Asynchronous Schedule when software transitions the Asynchronous
Schedule Enable bit in the USBCMD register. When this bit and the
Asynchronous Schedule Enable bit are the same value, the Asynchronous
Schedule is either enabled (if both are 1) or disabled (if both are 0).
0
1

Asynchronous schedule status is disabled.
Asynchronous schedule status is enabled.

16

-

Not used on Host mode.

17

-

Reserved.

18

UAI

USB host asynchronous interrupt (USBHSTASYNCINT)

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0

This bit is cleared by software writing a one to it.

1

This bit is set by the Host Controller when the cause of an interrupt is a
completion of a USB transaction where the Transfer Descriptor (TD) has an
interrupt on complete (IOC) bit set and the TD was from the asynchronous
schedule. This bit is also set by the Host when a short packet is detected
and the packet is on the asynchronous schedule. A short packet is when
the actual number of bytes received was less than the expected number of
bytes.

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0

-

0

R/WC

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Chapter 25: LPC43xx/LPC43Sxx USB0 Host/Device/OTG controller

Table 472. USB Status register in host mode (USBSTS_H - address 0x4000 6144) register bit description …continued
Bit

Symbol Value

Description

Reset Access
value

19

UPI

USB host periodic interrupt (USBHSTPERINT)

0

31:20

0

This bit is cleared by software writing a one to it.

1

This bit is set by the Host Controller when the cause of an interrupt is a
completion of a USB transaction where the Transfer Descriptor (TD) has an
interrupt on complete (IOC) bit set and the TD was from the periodic
schedule. This bit is also set by the Host Controller when a short packet is
detected and the packet is on the periodic schedule. A short packet is
when the actual number of bytes received was less than the expected
number of bytes.

R/WC

-

25.6.5 USB Interrupt register (USBINTR)
The software interrupts are enabled with this register. An interrupt is generated when a bit
is set and the corresponding interrupt is active. The USB Status register (USBSTS) still
shows interrupt sources even if they are disabled by the USBINTR register, allowing
polling of interrupt events by the software. All interrupts must be acknowledged by
software by clearing (that is writing a 1 to) the corresponding bit in the USBSTS register.

25.6.5.1 Device mode
Table 473. USB Interrupt register in device mode (USBINTR_D - address 0x4000 6148) bit description
Bit

Symbol Description

Reset
value

Access

0

UE

0

R/W

0

R/W

0

R/W

0

-

0

R/W

USB interrupt enable
When this bit is one, and the USBINT bit in the USBSTS register is one, the
host/device controller will issue an interrupt at the next interrupt threshold. The
interrupt is acknowledged by software clearing the USBINT bit in USBSTS.

1

UEE

USB error interrupt enable
When this bit is a one, and the USBERRINT bit in the USBSTS register is a one, the
host/device controller will issue an interrupt at the next interrupt threshold. The
interrupt is acknowledged by software clearing the USBERRINT bit in the USBSTS
register.

2

PCE

Port change detect enable
When this bit is a one, and the Port Change Detect bit in the USBSTS register is a
one, the host/device controller will issue an interrupt. The interrupt is acknowledged by
software clearing the Port Change Detect bit in USBSTS.

3

-

Not used by the Device controller.

4

SEE

System Error Enable
When this bit is a one, and the System Error bit in the USBSTS register is a one, the
host/device controller will issue an interrupt. The interrupt is acknowledged by
software clearing the System Error bit in USBSTS register.

5

-

Not used by the Device controller.

6

URE

USB reset enable
When this bit is a one, and the USB Reset Received bit in the USBSTS register is a
one, the device controller will issue an interrupt. The interrupt is acknowledged by
software clearing the USB Reset Received bit.

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Chapter 25: LPC43xx/LPC43Sxx USB0 Host/Device/OTG controller

Table 473. USB Interrupt register in device mode (USBINTR_D - address 0x4000 6148) bit description …continued
Bit

Symbol Description

Reset
value

Access

7

SRE

0

R/W

0

R/W

SOF received enable
When this bit is a one, and the SOF Received bit in the USBSTS register is a one, the
device controller will issue an interrupt. The interrupt is acknowledged by software
clearing the SOF Received bit.

8

SLE

Sleep enable
When this bit is a one, and the DCSuspend bit in the USBSTS
register transitions, the device controller will issue an interrupt. The interrupt is
acknowledged by software writing a one to the DCSuspend bit.

15:9

-

Reserved

-

-

16

NAKE

NAK interrupt enable

0

R/W

This bit is set by software if it wants to enable the hardware interrupt for the NAK
Interrupt bit. If both this bit and the corresponding NAK Interrupt bit are set, a
hardware interrupt is generated.
17

-

Reserved

18

-

Not used by the Device controller.

19

-

Not used by the Device controller.

31:20 -

Reserved

25.6.5.2 Host mode
Table 474. USB Interrupt register in host mode (USBINTR_H - address 0x4000 6148) bit description
Bit

Symbol Description

Access Reset
value

0

UE

R/W

0

R/W

0

R/W

0

0

-

USB interrupt enable
When this bit is one, and the USBINT bit in the USBSTS register is one, the
host/device controller will issue an interrupt at the next interrupt threshold. The
interrupt is acknowledged by software clearing the USBINT bit in USBSTS.

1

UEE

USB error interrupt enable
When this bit is a one, and the USBERRINT bit in the USBSTS register is a one, the
host/device controller will issue an interrupt at the next interrupt threshold. The
interrupt is acknowledged by software clearing the USBERRINT bit in the USBSTS
register.

2

PCE

Port change detect enable
When this bit is a one, and the Port Change Detect bit in the USBSTS register is a
one, the host/device controller will issue an interrupt. The interrupt is acknowledged
by software clearing the Port Change Detect bit in USBSTS.

3

FRE

Frame list rollover enable
When this bit is a one, and the Frame List Rollover bit in the USBSTS register is a
one, the host controller will issue an interrupt. The interrupt is acknowledged by
software clearing the Frame List Rollover bit.

4

SEE

System Error Enable
When this bit is a one, and the System Error bit in the USBSTS register is a one, the
host/device controller will issue an interrupt. The interrupt is acknowledged by
software clearing the System Error bit in USBSTS register.

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Chapter 25: LPC43xx/LPC43Sxx USB0 Host/Device/OTG controller

Table 474. USB Interrupt register in host mode (USBINTR_H - address 0x4000 6148) bit description …continued
Bit

Symbol Description

Access Reset
value

5

AAE

R/W

Interrupt on asynchronous advance enable

0

When this bit is a one, and the Interrupt on Async Advance bit in the USBSTS register
is a one, the host controller will issue an interrupt at the next interrupt threshold. The
interrupt is acknowledged by software clearing the Interrupt on Async Advance bit.
6

-

Not used by the Host controller.

-

0

7

SRE

If this bit is one and the SRI bit in the USBSTS register is one, the host controller will issue an interrupt. In host mode, the SRI bit will be set every 125 s and can be used
by the host controller as a time base. The interrupt is acknowledged by software
clearing the SRI bit in the USBSTS register.

0

8

-

Not used by the Host controller.

-

0

15:9

-

Reserved

16

-

Not used by the host controller.

R/W

0

17

-

Reserved

18

UAIE

USB host asynchronous interrupt enable

R/W

0

R/W

0

When this bit is a one, and the USBHSTASYNCINT bit in the USBSTS register is a
one, the host controller will issue an interrupt at the next interrupt threshold. The
interrupt is acknowledged by software clearing the USBHSTASYNCINT bit.
19

UPIA

USB host periodic interrupt enable
When this bit is a one, and the USBHSTPERINT bit in the USBSTS register is a one,
the host controller will issue an interrupt at the next interrupt threshold. The interrupt is
acknowledged by software clearing the USBHSTPERINT bit.

31:20 -

Reserved

25.6.6 Frame index register (FRINDEX)
25.6.6.1 Device mode
In Device mode this register is read only, and the device controller updates the
FRINDEX[13:3] register from the frame number indicated by the SOF marker. Whenever a
SOF is received by the USB bus, FRINDEX[13:3] will be checked against the SOF
marker. If FRINDEX[13:3] is different from the SOF marker, FRINDEX[13:3] will be set to
the SOF value and FRINDEX[2:0] will be set to zero (i.e. SOF for 1 ms frame). If
FRINDEX [13:3] is equal to the SOF value, FRINDEX[2:0] will be incremented (i.e. SOF
for 125 s micro-frame) by hardware.
Table 475. USB frame index register in device mode (FRINDEX_D - address 0x4000 614C) bit
description

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Bit

Symbol

Description

Reset value

Access

2:0

FRINDEX2_0

13:3

FRINDEX13_3

Current micro frame number

N/A

RO

Current frame number of the last frame
transmitted

N/A

RO

31:14

-

Reserved

N/A

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Chapter 25: LPC43xx/LPC43Sxx USB0 Host/Device/OTG controller

25.6.6.2 Host mode
This register is used by the host controller to index the periodic frame list. The register
updates every 125 s (once each micro-frame). Bits[N: 3] are used to select a particular
entry in the Periodic Frame List during periodic schedule execution. The number of bits
used for the index depends on the size of the frame list as set by system software in the
Frame List Size field in the USBCMD register.
This register must be written as a DWord. Byte writes produce undefined results. This
register cannot be written unless the Host Controller is in the 'Halted' state as indicated by
the HCHalted bit in the USBSTS register (host mode). A write to this register while the
Run/Stop bit is set to a one produces undefined results. Writes to this register also affect
the SOF value.
Table 476. USB frame index register in host (FRINDEX_H - address 0x4000 614C) bit
description
Bit

Symbol

Description

Reset value

Access

2:0

FRINDEX2_0

Current micro frame number

N/A

R/W

12:3

FRINDEX12_3

Frame list current index.

N/A

R/W

31:13

-

Reserved

N/A

Table 477. Number of bits used for the frame list index
USBCMD USBCMD USBCMD Frame list size
bit 15
bit 3
bit 2

N

0

0

0

1024 elements (4096 bytes). Default value.

12

0

0

1

512 elements (2048 bytes)

11

0

1

0

256 elements (1024 bytes)

10

0

1

1

128 elements (512 bytes)

9

1

0

0

64 elements (256 bytes)

8

1

0

1

32 elements (128 bytes)

7

1

1

0

16 elements (64 bytes)

6

1

1

1

8 elements (32 bytes)

5

25.6.7 Device address (DEVICEADDR - device) and Periodic List Base
(PERIODICLISTBASE- host) registers
25.6.7.1 Device mode
The upper seven bits of this register represent the device address. After any controller
reset or a USB reset, the device address is set to the default address (0). The default
address will match all incoming addresses. Software shall reprogram the address after
receiving a SET_ADDRESS descriptor.
The USBADRA bit is used to accelerate the SET_ADDRESS sequence by allowing the
DCD to preset the USBADR register bits before the status phase of the SET_ADDRESS
descriptor.

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Chapter 25: LPC43xx/LPC43Sxx USB0 Host/Device/OTG controller

Table 478. USB Device Address register in device mode (DEVICEADDR - address 0x4000 6154) bit description
Bit

Symbol

Value Description

23:0

-

Reserved

24

USBADRA

Device address advance
0

Any write to USBADR are instantaneous.

1

When the user writes a one to this bit at the same time or before USBADR
is written, the write to USBADR fields is staged and held in a hidden
register. After an IN occurs on endpoint 0 and is acknowledged, USBADR
will be loaded from the holding register.

Reset
value

Access

0

-

0

R/W

Hardware will automatically clear this bit on the following conditions:

•

IN is ACKed to endpoint 0. USBADR is updated from the staging
register.

•
•

OUT/SETUP occurs on endpoint 0. USBADR is not updated.
Device reset occurs. USBADR is set to 0.

Remark: After the status phase of the SET_ADDRESS descriptor, the
DCD has 2 ms to program the USBADR field. This mechanism will ensure
this specification is met when the DCD can not write the device address
within 2 ms from the SET_ADDRESS status phase. If the DCD writes the
USBADR with USBADRA=1 after the SET_ADDRESS data phase (before
the prime of the status phase), the USBADR will be programmed instantly
at the correct time and meet the 2 ms USB requirement.
31:25

USBADR

USB device address

25.6.7.2 Host mode
This 32-bit register contains the beginning address of the Periodic Frame List in the
system memory. The host controller driver (HCD) loads this register prior to starting the
schedule execution by the Host Controller. The memory structure referenced by this
physical memory pointer is assumed to be 4 kB aligned. The contents of this register are
combined with the Frame Index Register (FRINDEX) to enable the Host Controller to step
through the Periodic Frame List in sequence.
Table 479. USB Periodic List Base register in host mode (PERIODICLISTBASE - address 0x4000 6154) bit
description
Bit

Symbol

Description

Reset
value

Access

11:0

-

Reserved

-

-

31:12

PERBASE31_12

Base Address (Low)

-

R/W

These bits correspond to the memory address signals 31:12.

25.6.8 Endpoint List Address register (ENDPOINTLISTADDR - device) and
Asynchronous List Address (ASYNCLISTADDR - host) registers
25.6.8.1 Device mode
In device mode, this register contains the address of the top of the endpoint list in system
memory. Bits[10:0] of this register cannot be modified by the system software and will
always return a zero when read. The memory structure referenced by this physical
memory pointer is assumed 64 byte aligned. The entire device endpoint list must be
aligned on a 2 kB boundary.
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Chapter 25: LPC43xx/LPC43Sxx USB0 Host/Device/OTG controller

Table 480. USB Endpoint List Address register in device mode (ENDPOINTLISTADDR - address 0x4000 6158) bit
description
Bit

Symbol

Description

Reset
value

Access

10:0

-

Reserved

0

-

31:11

EPBASE31_11

Endpoint list pointer (low)

-

R/W

These bits correspond to memory address signals 31:11, respectively. This
field will reference a list of up to 12 Queue Heads (QH). (i.e. one queue head
per endpoint and direction.)

25.6.8.2 Host mode
This 32-bit register contains the address of the next asynchronous queue head to be
executed by the host. Bits [4:0] of this register cannot be modified by the system software
and will always return a zero when read.
Table 481. USB Asynchronous List Address register in host mode (ASYNCLISTADDR- address 0x4000 6158) bit
description
Bit

Symbol

Description

Reset
value

Access

4:0

-

Reserved

0

-

31:5

ASYBASE31_5

Link pointer (Low) LPL

-

R/W

These bits correspond to memory address signals 31:5, respectively. This
field may only reference a Queue Head (OH).

25.6.9 TT Control register (TTCTRL)
25.6.9.1 Device mode
This register is not used in device mode.

25.6.9.2 Host mode
This register contains parameters needed for internal TT operations. This register is used
by the host controller only. Writes must be in Dwords.
Table 482. USB TT Control register in host mode (TTCTRL - address 0x4000 615C) bit description
Bit

Symbol

Description

Reset
value

Access

23:0

-

Reserved.

0

-

30:24

TTHA

Hub address when FS or LS device are connected directly.

N/A

R/W

31

-

Reserved.

0

25.6.10 Burst Size register (BURSTSIZE)
This register is used to control and dynamically change the burst size used during data
movement on the master interface of the USB DMA controller. Writes must be in Dwords.
The default for the length of a burst of 32-bit words for RX and TX DMA data transfers is
16 words each.
Remark: The value of the fields TXPBURST/RXPBURST in register BURSTSIZE
depends on the setting of the SBUSCFG register.
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Chapter 25: LPC43xx/LPC43Sxx USB0 Host/Device/OTG controller

Table 483. USB burst size register (BURSTSIZE - address 0x4000 6160) bit description - device/host mode
Bit

Symbol

Description

Reset
value

Access

7:0

RXPBURST

Programmable RX burst length

0x10

R/W

0x10

R/W

-

-

This register represents the maximum length of a burst in 32-bit words while
moving data from the USB bus to system memory.
15:8

TXPBURST

Programmable TX burst length
This register represents the maximum length of a burst in 32-bit words while
moving data from system memory to the USB bus.

31:16

-

Reserved.

25.6.11 Transfer buffer Fill Tuning register (TXFILLTUNING)
25.6.11.1 Device controller
This register is not used in device mode.

25.6.11.2 Host controller
The fields in this register control performance tuning associated with how the host
controller posts data to the TX latency FIFO before moving the data onto the USB bus.
The specific areas of performance include the how much data to post into the FIFO and
an estimate for how long that operation should take in the target system.
Definitions:
T0 = Standard packet overhead
T1 = Time to send data payload
Tff = Time to fetch packet into TX FIFO up to specified level
Ts = Total packet flight time (send-only) packet; Ts = T0 + T1
Tp = Total packet time (fetch and send) packet; Tp = Tff + T0 + T1
Upon discovery of a transmit (OUT/SETUP) packet in the data structures, host controller
checks to ensure Tp remains before the end of the (micro) frame. If so it proceeds to
pre-fill the TX FIFO. If at anytime during the pre-fill operation the time remaining the
[micro]frame is < Ts then the packet attempt ceases and the packet is tried at a later time.
Although this is not an error condition and the host controller will eventually recover, a
mark will be made the scheduler health counter to note the occurrence of a “backoff”
event. When a back-off event is detected, the partial packet fetched may need to be
discarded from the latency buffer to make room for periodic traffic that will begin after the
next SOF. Too many back-off events can waste bandwidth and power on the system bus
and thus should be minimized (not necessarily eliminated). Backoffs can be minimized
with use of the TSCHHEALTH (Tff) described below.

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Chapter 25: LPC43xx/LPC43Sxx USB0 Host/Device/OTG controller

Table 484. USB Transfer buffer Fill Tuning register in host mode (TXFILLTUNING - address 0x4000 6164) bit
description
Bit

Symbol

Description

Reset
value

Access

7:0

TXSCHOH

FIFO burst threshold

0x2

R/W

0x0

R/W

This register controls the number of data bursts that are posted to the TX
latency FIFO in host mode before the packet begins on to the bus. The
minimum value is 2 and this value should be a low as possible to maximize
USB performance. A higher value can be used in systems with unpredictable
latency and/or insufficient bandwidth where the FIFO may underrun because
the data transferred from the latency FIFO to USB occurs before it can be
replenished from system memory. This value is ignored if the Stream Disable
bit in USBMODE register is set.
12:8

TXSCHEATLTH Scheduler health counter
This register increments when the host controller fails to fill the TX latency
FIFO to the level programmed by TXFIFOTHRES before running out of time
to send the packet before the next Start-Of-Frame .
This health counter measures the number of times this occurs to provide
feedback to selecting a proper TXSCHOH. Writing to this register will clear the
counter. The maximum value is 31.

15:13

-

Reserved

-

-

21:16

TXFIFOTHRES

Scheduler overhead

0x0

R/W

This register adds an additional fixed offset to the schedule time estimator
described above as Tff. As an approximation, the value chosen for this register
should limit the number of back-off events captured in the TXSCHHEALTH to
less than 10 per second in a highly utilized bus. Choosing a value that is too
high for this register is not desired as it can needlessly reduce USB utilization.
The time unit represented in this register is 1.267 s when a device is
connected in High-Speed Mode for OTG and SPH.
The time unit represented in this register is 6.333 s when a device is
connected in Low/Full Speed Mode for OTG and SPH.
31:22

-

Reserved

25.6.12 BINTERVAL register
This register defines the bInterval value which determines the length of the virtual frame
(see Section 25.7.7). The BINTERVAL register divides the SOF signal by the value BINT.
Remark: The BINTERVAL register is not related to the bInterval endpoint descriptor field
in the USB specification.
Table 485. USB BINTERVAL register (BINTERVAL - address 0x4000 6174) bit description
Bit

Symbol

Description

Reset
value

Access

3:0

BINT

bInterval value (see Section 25.7.7)

0x00

R/W

31:4

-

Reserved

-

-

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Chapter 25: LPC43xx/LPC43Sxx USB0 Host/Device/OTG controller

25.6.13 USB Endpoint NAK register (ENDPTNAK)
25.6.13.1 Device mode
This register indicates when the device sends a NAK handshake on an endpoint. Each Tx
and Rx endpoint has a bit in the EPTN and EPRN field respectively.
A bit in this register is cleared by writing a 1 to it.
Table 486. USB endpoint NAK register (ENDPTNAK - address 0x4000 6178) bit description
Bit

Symbol

Description

Reset
value

Access

5:0

EPRN

Rx endpoint NAK

0x00

R/WC

Each RX endpoint has one bit in this field. The bit is set when the device
sends a NAK handshake on a received OUT or PING token for the
corresponding endpoint.
Bit 5 corresponds to endpoint 5.
...
Bit 1 corresponds to endpoint 1.
Bit 0 corresponds to endpoint 0.
15:6

-

Reserved

-

-

21:16

EPTN

Tx endpoint NAK

0x00

R/WC

-

-

Each TX endpoint has one bit in this field. The bit is set when the device
sends a NAK handshake on a received IN token for the corresponding
endpoint.
Bit 5 corresponds to endpoint 5.
...
Bit 1 corresponds to endpoint 1.
Bit 0 corresponds to endpoint 0.
31:22

-

Reserved

25.6.13.2 Host mode
This register is not used in host mode.

25.6.14 USB Endpoint NAK Enable register (ENDPTNAKEN)
25.6.14.1 Device mode
Each bit in this register enables the corresponding bit in the ENDPTNAK register. Each Tx
and Rx endpoint has a bit in the EPTNE and EPRNE field respectively.

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Chapter 25: LPC43xx/LPC43Sxx USB0 Host/Device/OTG controller

Table 487. USB Endpoint NAK Enable register (ENDPTNAKEN - address 0x4000 617C) bit description
Bit

Symbol

Description

Reset
value

Access

5:0

EPRNE

Rx endpoint NAK enable

0x00

R/W

Each bit enables the corresponding RX NAK bit. If this bit is set and the
corresponding RX endpoint NAK bit is set, the NAK interrupt bit is set.
Bit 5 corresponds to endpoint 5.
...
Bit 1 corresponds to endpoint 1.
Bit 0 corresponds to endpoint 0.
15:6

-

Reserved

-

-

21:16

EPTNE

Tx endpoint NAK

0x00

R/W

-

-

Each bit enables the corresponding TX NAK bit. If this bit is set and the
corresponding TX endpoint NAK bit is set, the NAK interrupt bit is set.
Bit 5 corresponds to endpoint 5.
...
Bit 1 corresponds to endpoint 1.
Bit 0 corresponds to endpoint 0.
31:22

-

Reserved

25.6.14.2 Host mode
This register is not used in host mode.

25.6.15 Port Status and Control register (PORTSC1)
25.6.15.1 Device mode
The device controller implements one port register, and it does not support power control.
Port control in device mode is used for status port reset, suspend, and current connect
status. It is also used to initiate test mode or force signaling. This register allows software
to put the PHY into low-power Suspend mode and disable the PHY clock.
Table 488. Port Status and Control register in device mode (PORTSC1_D - address 0x4000 6184) bit description
Bit

Symbol

0

CCS

Value Description

Reset
value

Access

0

RO

Not used in device mode

0

-

Current connect status
0

Device not attached
A zero indicates that the device did not attach successfully or was forcibly
disconnected by the software writing a zero to the Run bit in the USBCMD
register. It does not state the device being disconnected or suspended.

1

Device attached.
A one indicates that the device successfully attached and is operating in
either high-speed mode or full-speed mode as indicated by the High Speed
Port bit in this register.

1

-

-

2

PE

Port enable.
This bit is always 1. The device port is always enabled.

1

RO

3

PEC

Port enable/disable change

0

RO

This bit is always 0. The device port is always enabled.
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Chapter 25: LPC43xx/LPC43Sxx USB0 Host/Device/OTG controller

Table 488. Port Status and Control register in device mode (PORTSC1_D - address 0x4000 6184) bit description
Bit

Symbol

Value Description

Reset
value

Access

5:4

-

-

0

RO

6

FPR

7

8

9

Reserved

Force port resume
0
After the device has been in Suspended state for 5 ms or more, software
must set this bit to one to drive resume signaling before clearing. The
device controller will set this bit to one if a J-to-K transition is detected while
the port is in the Suspended state. The bit will be cleared when the device
returns to normal operation. When this bit transitions to a one because a
J-to-K transition detected, the Port Change Detect bit in the USBSTS
register is set to one as well.
0

No resume (K-state) detected/driven on port.

1

Resume detected/driven on port.

SUSP

Suspend
In device mode, this is a read-only status bit .
0

Port not in Suspended state

1

Port in Suspended state

PR

Port reset
In device mode, this is a read-only status bit. A device reset from the USB
bus is also indicated in the USBSTS register.
0

Port is not in the reset state.

1

Port is in the reset state.

HSP

High-speed status

R/W

0

RO

0

RO

0

RO

Remark: This bit is redundant with bits 27:26 (PSPD) in this register. It is
implemented for compatibility reasons.
0

Host/device connected to the port is not in High-speed mode.

1

Host/device connected to the port is in High-speed mode.

11:10 -

-

Not used in device mode.

12

-

-

Not used in device mode.

13

-

-

Reserved

-

-

Port indicator control
Writing to this field effects the value of the USB0_IND[1:0] pins.

00

R/W

15:14 PIC1_0

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0x0

Port indicators are off.

0x1

amber

0x2

green

0x3

undefined

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Chapter 25: LPC43xx/LPC43Sxx USB0 Host/Device/OTG controller

Table 488. Port Status and Control register in device mode (PORTSC1_D - address 0x4000 6184) bit description
Bit

Symbol

Value Description

19:16 PTC3_0

Reset
value

Port test control
0000
Any value other than 0000 indicates that the port is operating in test mode.

Access
R/W

The FORCE_ENABLE_FS and FORCE ENABLE_LS are extensions to the
test mode support specified in the EHCI specification. Writing the PTC field
to any of the FORCE_ENABLE_HS/FS/LS values will force the port into
the connected and enabled state at the selected speed. Writing the PTC
field back to TEST_MODE_DISABLE will allow the port state machines to
progress normally from that point. Values 0111 to 1111 are not valid.
0x0

TEST_MODE_DISABLE

0x1

J_STATE

0x2

K_STATE

0x3

SE0 (host)/NAK (device)

0x4

Packet

0x5

FORCE_ENABLE_HS

0x6

FORCE_ENABLE_FS

-

-

Not used in device mode. This bit is always 0 in device mode.

21

-

-

Not used in device mode. This bit is always 0 in device mode.

0

-

22

-

Not used in device mode. This bit is always 0 in device mode.

0

-

23

PHCD

PHY low power suspend - clock disable (PLPSCD)

0

R/W

0

R/W

0

RO

-

-

20

0

-

In device mode, The PHY can be put into Low Power Suspend – Clock
Disable when the device is not running (USBCMD Run/Stop = 0) or the
host has signaled suspend (PORTSC SUSPEND = 1). Low power suspend
will be cleared automatically when the host has signaled resume. Before
forcing a resume from the device, the device controller driver must clear
this bit.

24

25

0

Writing a 0 enables the PHY clock. Reading a 0 indicates the status of the
PHY clock (enabled).

1

Writing a 1 disables the PHY clock. Reading a 1 indicates the status of the
PHY clock (disabled).

PFSC

-

Port force full speed connect
0

Port connects at any speed.

1

Writing this bit to a 1 will force the port to only connect at full speed. It
disables the chirp sequence that allows the port to identify itself as
High-speed. This is useful for testing FS configurations with a HS host, hub
or device.

-

Reserved

27:26 PSPD

Port speed
This register field indicates the speed at which the port is operating.

31:28 -

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0x0

Full-speed

0x1

invalid in device mode

0x2

High-speed

-

Reserved

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Chapter 25: LPC43xx/LPC43Sxx USB0 Host/Device/OTG controller

25.6.15.2 Host mode
The host controller uses one port. The register is only reset when power is initially applied
or in response to a controller reset. The initial conditions of the port are:

• No device connected
• Port disabled
If the port has power control, this state remains until software applies power to the port by
setting port power to one in the PORTSC register.
Table 489. Port Status and Control register in host mode (PORTSC1_H - address 0x4000 6184) bit description
Bit

Symbol

0

CCS

Value Description
Current connect status

Reset
value

Access

0

R/WC

0

R/WC

0

R/W

This value reflects the current state of the port and may not correspond
directly to the event that caused the CSC bit to be set.
This bit is 0 if PP (Port Power bit) is 0.
Software clears this bit by writing a 1 to it.
0
1
1

CSC

No device is present.
Device is present on the port.
Connect status change
Indicates a change has occurred in the port’s Current Connect Status. The
host/device controller sets this bit for all changes to the port device connect
status, even if system software has not cleared an existing connect status
change. For example, the insertion status changes twice before system
software has cleared the changed condition, hub hardware will be setting
an already-set bit (i.e., the bit will remain set). Software clears this bit by
writing a one to it.
This bit is 0 if PP (Port Power bit) is 0

2

0

No change in current status.

1

Change in current status.

PE

Port enable.
Ports can only be enabled by the host controller as a part of the reset and
enable. Software cannot enable a port by writing a one to this field. Ports
can be disabled by either a fault condition (disconnect event or other fault
condition) or by the host software. Note that the bit status does not change
until the port state actually changes. There may be a delay in disabling or
enabling a port due to other host controller and bus events.
When the port is disabled. downstream propagation of data is blocked
except for reset.
This bit is 0 if PP (Port Power bit) is 0.

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0

Port disabled.

1

Port enabled.

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Chapter 25: LPC43xx/LPC43Sxx USB0 Host/Device/OTG controller

Table 489. Port Status and Control register in host mode (PORTSC1_H - address 0x4000 6184) bit description
Bit

Symbol

3

PEC

Value Description
Port disable/enable change

Reset
value

Access

0

R/WC

0

RO

0

R/WC

0

R/W

For the root hub, this bit gets set to a one only when a port is disabled due
to disconnect on the port or due to the appropriate conditions existing at
the EOF2 point (See Chapter 11 of the USB Specification). Software clears
this by writing a one to it.
This bit is 0 if PP (Port Power bit) is 0,

4

5

0

No change.

1

Port enabled/disabled status has changed.

OCA

Over-current active
This bit will automatically transition from 1 to 0 when the over-current
condition is removed.
0

The port does not have an over-current condition.

1

The port has currently an over-current condition.

OCC

Over-current change
This bit gets set to one when there is a change to Over-current Active.
Software clears this bit by writing a one to this bit position.

6

FPR

Force port resume
Software sets this bit to one to drive resume signaling. The Host Controller
sets this bit to one if a J-to-K transition is detected while the port is in the
Suspended state. When this bit transitions to a one because a J-to-K
transition is detected, the Port Change Detect bit in the USBSTS register is
also set to one. This bit will automatically change to zero after the resume
sequence is complete. This behavior is different from EHCI where the host
controller driver is required to set this bit to a zero after the resume duration
is timed in the driver.
Note that when the Host controller owns the port, the resume sequence
follows the defined sequence documented in the USB Specification
Revision 2.0. The resume signaling (Full-speed K) is driven on the port as
long as this bit remains a one. This bit will remain a one until the port has
switched to the high-speed idle. Writing a zero has no affect because the
port controller will time the resume operation clear the bit the port control
state switches to HS or FS idle.
This bit is 0 if PP (Port Power bit) is 0.

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0

No resume (K-state) detected/driven on port.

1

Resume detected/driven on port.

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Chapter 25: LPC43xx/LPC43Sxx USB0 Host/Device/OTG controller

Table 489. Port Status and Control register in host mode (PORTSC1_H - address 0x4000 6184) bit description
Bit

Symbol

7

SUSP

Value Description
Suspend
Together with the PE (Port enabled bit), this bit describes the port states,
see Table 490.

Reset
value

Access

0

R/W

0

R/W

0

RO

0x3

RO

The host controller will unconditionally set this bit to zero when software
sets the Force Port Resume bit to zero. The host controller ignores a write
of zero to this bit.
If host software sets this bit to a one when the port is not enabled (i.e. Port
enabled bit is a zero) the results are undefined.
This bit is 0 if PP (Port Power bit) is 0.
0

Port not in Suspended state

1

Port in Suspended state
When in Suspended state, downstream propagation of data is blocked on
this port, except for port reset. The blocking occurs at the end of the current
transaction if a transaction was in progress when this bit was written to 1.
In the Suspended state, the port is sensitive to resume detection. Note that
the bit status does not change until the port is suspended and that there
may be a delay in suspending a port if there is a transaction currently in
progress on the USB.

8

PR

Port reset
When software writes a one to this bit the bus-reset sequence as defined in
the USB Specification Revision 2.0 is started. This bit will automatically
change to zero after the reset sequence is complete. This behavior is
different from EHCI where the host controller driver is required to set this
bit to a zero after the reset duration is timed in the driver.
This bit is 0 if PP (Port Power bit) is 0.

9

0

Port is not in the reset state.

1

Port is in the reset state.

HSP

High-speed status
0

Host/device connected to the port is not in High-speed mode.

1

Host/device connected to the port is in High-speed mode.

11:10 LS

Line status
These bits reflect the current logical levels of the USB_DP and USB_DM
signal lines. USB_DP corresponds to bit 11 and USB_DM to bit 10.
In host mode, the use of linestate by the host controller driver is not
necessary for this controller (unlike EHCI) because the controller hardware
manages the connection of LS and FS.

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0x0

SE0 (USB_DP and USB_DM LOW)

0x1

J-state (USB_DP HIGH and USB_DM LOW)

0x2

K-state (USB_DP LOW and USB_DM HIGH)

0x3

Undefined

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Chapter 25: LPC43xx/LPC43Sxx USB0 Host/Device/OTG controller

Table 489. Port Status and Control register in host mode (PORTSC1_H - address 0x4000 6184) bit description
Bit

Symbol

Value Description

Reset
value

Access

12

PP

-

0

R/W

Port power control
Host/OTG controller requires port power control switches. This bit
represents the current setting of the switch (0=off, 1=on). When power is
not available on a port (i.e. PP equals a 0), the port is non-functional and
will not report attaches, detaches, etc.
When an over-current condition is detected on a powered port and PPC is
a one, the PP bit in each affected port may be transitioned by the host
controller driver from a one to a zero (removing power from the port).

13

-

0

Port power off.

1

Port power on.

-

Reserved

0

-

Port indicator control
Writing to this field effects the value of the pins USB0_IND1 and
USB0_IND0.

00

R/W

15:14 PIC1_0

0x0

Port indicators are off.

0x1

Amber

0x2

Green

0x3

Undefined

19:16 PTC3_0

Port test control
0000
Any value other than 0000 indicates that the port is operating in test mode.

R/W

The FORCE_ENABLE_FS and FORCE ENABLE_LS are extensions to the
test mode support specified in the EHCI specification. Writing the PTC field
to any of the FORCE_ENABLE_{HS/FS/LS} values will force the port into
the connected and enabled state at the selected speed. Writing the PTC
field back to TEST_MODE_DISABLE will allow the port state machines to
progress normally from that point. Values 0x8 to 0xF are reserved.
0x0

TEST_MODE_DISABLE

0x1

J_STATE

0x2

K_STATE

0x3

SE0 (host)/NAK (device)

0x4

Packet

0x5

FORCE_ENABLE_HS

0x6

FORCE_ENABLE_FS

0x7
20

WKCN

FORCE_ENABLE_LS
Wake on connect enable (WKCNNT_E)

0

R/W

0

R/W

This bit is 0 if PP (Port Power bit) is 0

21

0

Disables the port to wake up on device connects.

1

Writing this bit to a one enables the port to be sensitive to device connects
as wake-up events.

WKDC

Wake on disconnect enable (WKDSCNNT_E)
This bit is 0 if PP (Port Power bit) is 0.

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0

Disables the port to wake up on device disconnects.

1

Writing this bit to a one enables the port to be sensitive to device
disconnects as wake-up events.
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Chapter 25: LPC43xx/LPC43Sxx USB0 Host/Device/OTG controller

Table 489. Port Status and Control register in host mode (PORTSC1_H - address 0x4000 6184) bit description
Bit

Symbol

22

WKOC

23

Value Description
Wake on over-current enable (WKOC_E)
0

Disables the port to wake up on over-current events.

1

Writing a one to this bit enabled the port to be sensitive to over-current
conditions as wake-up events.

PHCD

PHY low power suspend - clock disable (PLPSCD)

Reset
value

Access

0

R/W

0

R/W

0

R/W

0

RO

-

-

In host mode, the PHY can be put into Low Power Suspend – Clock
Disable when the downstream device has been put into suspend mode or
when no downstream device is connected. Low power suspend is
completely under the control of software.

24

25

0

Writing a 0 enables the PHY clock. Reading a 0 indicates the status of the
PHY clock (enabled).

1

Writing a 1 disables the PHY clock. Reading a 1 indicates the status of the
PHY clock (disabled).

PFSC

-

Port force full speed connect
0

Port connects at any speed.

1

Writing this bit to a 1 will force the port to only connect at Full Speed. It
disables the chirp sequence that allows the port to identify itself as High
Speed. This is useful for testing FS configurations with a HS host, hub or
device.

-

Reserved

27:26 PSPD

Port speed
This register field indicates the speed at which the port is operating. For HS
mode operation in the host controller and HS/FS operation in the device
controller the port routing steers data to the Protocol engine. For FS and
LS mode operation in the host controller, the port routing steers data to the
Protocol Engine w/ Embedded Transaction Translator.
0x0

Full-speed

0x1

Low-speed

0x2

High-speed

31:28 -

Reserved

Table 490. Port states as described by the PE and SUSP bits in the PORTSC1 register
PE bit

SUSP bit

Port state

0

0 or 1

disabled

1

0

enabled

1

1

suspend

25.6.16 OTG Status and Control register (OTGSC)
The OTG register has four sections:

•
•
•
•
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OTG interrupt enables (R/W)
OTG Interrupt status (R/WC)
OTG status inputs (RO)
OTG controls (R/W)
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Chapter 25: LPC43xx/LPC43Sxx USB0 Host/Device/OTG controller

The status inputs are debounced using a 1 msec time constant. Values on the status
inputs that do not persist for more than 1 msec will not cause an update of the status input
register or cause an OTG interrupt.
Table 491. OTG Status and Control register (OTGSC - address 0x4000 61A4) bit description
Bit

Symbol

0

VD

Value

Description

Reset
value

Access

VBUS_Discharge

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

1

R/W

0

R/W

0

R/W

0

RO

0

RO

0

RO

0

RO

0

RO

0

RO

0

RO

Setting this bit to 1 causes VBUS to discharge through a resistor.
1

VC

VBUS_Charge
Setting this bit to 1 causes the VBUS line to be charged. This is used for
VBUS pulsing during SRP.

2

3

HAAR

Hardware assist auto_reset
0

Disabled

1

Enable automatic reset after connect on host port.

OT

OTG termination
This bit must be set to 1 when the OTG controller is in device mode. This
controls the pull-down on USB_DM.

4

DP

Data pulsing
Setting this bit to 1 causes the pull-up on USB_DP to be asserted for data
pulsing during SRP.

5

IDPU

ID pull-up.
This bit provides control over the pull-up resistor.

6

0

Pull-up off. The ID bit will not be sampled.

1

Pull-up on.

HADP

Hardware assist data pulse
Write a 1 to start data pulse sequence.

7

8

HABA

Hardware assist B-disconnect to A-connect
0

Disabled.

1

Enable automatic B-disconnect to A-connect sequence.

ID

USB ID
0
1

9

AVV

A-device
B-device
A-VBUS valid
Reading 1 indicates that VBUS is above the A-VBUS valid threshold.

10

ASV

A-session valid
Reading 1 indicates that VBUS is above the A-session valid threshold.

11

BSV

B-session valid
Reading 1 indicates that VBUS is above the B-session valid threshold.

12

BSE

B-session end
Reading 1 indicates that VBUS is below the B-session end threshold.

13

MS1T

1 millisecond timer toggle
This bit toggles once per millisecond.

14

DPS

Data bus pulsing status
Reading a 1 indicates that data bus pulsing is detected on the port.

15

-

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-

Reserved

0
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Chapter 25: LPC43xx/LPC43Sxx USB0 Host/Device/OTG controller

Table 491. OTG Status and Control register (OTGSC - address 0x4000 61A4) bit description …continued
Bit

Symbol

16

IDIS

Value

Description

Reset
value

Access

USB ID interrupt status

0

R/WC

0

R/WC

0

R/WC

0

R/WC

0

R/WC

0

R/WC

0

R/WC

This bit is set when a change on the ID input has been detected.
Software must write a 1 to this bit to clear it.
17

AVVIS

A-VBUS valid interrupt status
This bit is set then VBUS has either risen above or fallen below the
A-VBUS valid threshold (4.4 V on an A-device).
Software must write a 1 to this bit to clear it.

18

ASVIS

A-Session valid interrupt status
This bit is set then VBUS has either risen above or fallen below the
A-session valid threshold (0.8 V).
Software must write a 1 to this bit to clear it.

19

BSVIS

B-Session valid interrupt status
This bit is set then VBUS has either risen above or fallen below the
B-session valid threshold (0.8 V).
Software must write a 1 to this bit to clear it.

20

BSEIS

B-Session end interrupt status
This bit is set then VBUS has fallen below the B-session end threshold.
Software must write a 1 to this bit to clear it.

21

ms1S

1 millisecond timer interrupt status
This bit is set once every millisecond.
Software must write a 1 to this bit to clear it.

22

DPIS

Data pulse interrupt status
This bit is set when data bus pulsing occurs on DP or DM. Data bus pulsing
is only detected when the CM bit in USBMODE = Host (11) and the
PortPower bit in PORTSC = Off (0).
Software must write a 1 to this bit to clear it.

23

-

24

IDIE

-

Reserved

0

USB ID interrupt enable

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

Setting this bit enables the interrupt. Writing a 0 disables the interrupt.
25

AVVIE

A-VBUS valid interrupt enable
Setting this bit enables the A-VBUS valid interrupt. Writing a 0 disables the
interrupt.

26

ASVIE

A-session valid interrupt enable
Setting this bit enables the A-session valid interrupt. Writing a 0 disables
the interrupt

27

BSVIE

B-session valid interrupt enable
Setting this bit enables the B-session valid interrupt. Writing a 0 disables
the interrupt.

28

BSEIE

B-session end interrupt enable
Setting this bit enables the B-session end interrupt. Writing a 0 disables the
interrupt.

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Chapter 25: LPC43xx/LPC43Sxx USB0 Host/Device/OTG controller

Table 491. OTG Status and Control register (OTGSC - address 0x4000 61A4) bit description …continued
Bit

Symbol

29

MS1E

Value

Description

Reset
value

Access

1 millisecond timer interrupt enable

0

R/W

0

R/W

0

-

Setting this bit enables the 1 millisecond timer interrupt. Writing a 0
disables the interrupt.
30

DPIE

Data pulse interrupt enable
Setting this bit enables the data pulse interrupt. Writing a 0 disables the
interrupt

31

-

-

Reserved

25.6.17 USB Mode register (USBMODE)
The USBMODE register sets the USB mode for the OTG controller. The possible modes
are Device, Host, and Idle mode for OTG operations.

25.6.17.1 Device mode
Table 492. USB Mode register in device mode (USBMODE_D - address 0x4000 61A8) bit description
Bit

Symbol Value

Description

Reset
value

Access

1:0

CM1_0

Controller mode

00

R/ WO

0

R/W

0

R/W

The controller defaults to an idle state and needs to be initialized to the
desired operating mode after reset. This register can only be written once
after reset. If it is necessary to switch modes, software must reset the
controller by writing to the RESET bit in the USBCMD register before
reprogramming this register.

2

0x0

Idle

0x1

Reserved

0x2

Device controller

0x3

Host controller

ES

Endian select
This bit can change the byte ordering of the transfer buffers to match the
host microprocessor bus architecture. The bit fields in the microprocessor
interface and the DMA data structures (including the setup buffer within the
device QH) are unaffected by the value of this bit, because they are based
upon 32-bit words.

3

0

Little endian: first byte referenced in least significant byte of 32-bit word.

1

Big endian: first byte referenced in most significant byte of 32-bit word.

SLOM

Setup Lockout mode
In device mode, this bit controls behavior of the setup lock mechanism. See
Section 25.10.8.

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Setup Lockouts on

1

Setup Lockouts Off (DCD requires the use of Setup Buffer Tripwire in
USBCMD)

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Chapter 25: LPC43xx/LPC43Sxx USB0 Host/Device/OTG controller

Table 492. USB Mode register in device mode (USBMODE_D - address 0x4000 61A8) bit description …continued
Bit

Symbol Value

4

SDIS

Description

Reset
value

Access

Stream disable mode

0

R/W

0

-

Remark: The use of this feature substantially limits the overall USB
performance that can be achieved.
0

Not disabled

1

Disabled.
Setting this bit to one disables double priming on both RX and TX for low
bandwidth systems. This mode ensures that when the RX and TX buffers
are sufficient to contain an entire packet that the standard double buffering
scheme is disabled to prevent overruns/underruns in bandwidth limited
systems. Note: In High Speed Mode, all packets received will be responded
to with a NYET handshake when stream disable is active.

5

-

31:6

-

Not used in device mode.
-

Reserved

25.6.17.2 Host mode
Table 493. USB Mode register in host mode (USBMODE_H - address 0x4000 61A8) bit description
Bit

Symbol Value

Description

Reset
value

Access

1:0

CM

Controller mode

00

R/ WO

0

R/W

0

-

The controller defaults to an idle state and needs to be initialized to the
desired operating mode after reset. This register can only be written once
after reset. If it is necessary to switch modes, software must reset the
controller by writing to the RESET bit in the USBCMD register before
reprogramming this register.

2

0x0

Idle

0x1

Reserved

0x2

Device controller

0x3

Host controller

ES

Endian select
This bit can change the byte ordering of the transfer buffers. The bit fields in
the microprocessor interface and the DMA data structures (including the
setup buffer within the device QH) are unaffected by the value of this bit,
because they are based upon 32-bit words.

3

-

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Little endian: first byte referenced in least significant byte of 32-bit word.

1

Big endian: first byte referenced in most significant byte of 32-bit word.
Not used in host mode

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Chapter 25: LPC43xx/LPC43Sxx USB0 Host/Device/OTG controller

Table 493. USB Mode register in host mode (USBMODE_H - address 0x4000 61A8) bit description …continued
Bit

Symbol Value

4

SDIS

Description

Reset
value

Access

Stream disable mode

0

R/W

0

R/WO

-

-

Remark: The use of this feature substantially limits the overall USB
performance that can be achieved.
0

Not disabled

1

Disabled.
Setting to a ‘1’ ensures that overruns/underruns of the latency FIFO are
eliminated for low bandwidth systems where the RX and TX buffers are
sufficient to contain the entire packet. Enabling stream disable also has the
effect of ensuring the the TX latency is filled to capacity before the packet is
launched onto the USB.
Note: Time duration to pre-fill the FIFO becomes significant when stream
disable is active. See TXFILLTUNING to characterize the adjustments
needed for the scheduler when using this feature.

5

31:6

VBPS

-

VBUS power select
0

vbus_pwr_select is set LOW.

1

vbus_pwr_select is set HIGH

-

Reserved

25.6.18 USB Endpoint Setup Status register (ENDPSETUPSTAT)
Table 494. USB Endpoint Setup Status register (ENDPTSETUPSTAT - address 0x4000 61AC) bit description
Bit

Symbol

Description

Reset
value

5:0

ENDPTSET Setup endpoint status for logical endpoints 0 to 5.
0
UPSTAT
For every setup transaction that is received, a corresponding bit in this register
is set to one. Software must clear or acknowledge the setup transfer by writing
a one to a respective bit after it has read the setup data from Queue head. The
response to a setup packet as in the order of operations and total response
time is crucial to limit bus time outs while the setup lockout mechanism is
engaged.

R/WC

31:6

-

-

Reserved

-

Access

25.6.19 USB Endpoint Prime register (ENDPTPRIME)
For each endpoint, software should write a one to the corresponding bit whenever posting
a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin
parsing for a new transfer descriptor from the queue head and prepare a receive buffer.
Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed.
Remark: These bits will be momentarily set by hardware during hardware endpoint
re-priming operations when a dTD is retired and the dQH is updated.

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Chapter 25: LPC43xx/LPC43Sxx USB0 Host/Device/OTG controller

Table 495. USB Endpoint Prime register (ENDPTPRIME - address 0x4000 61B0) bit description
Bit

Symbol

Description

Reset
value

5:0

PERB

Prime endpoint receive buffer for physical OUT endpoints 5 to 0.
0
For each OUT endpoint, a corresponding bit is set to 1 by software to request a
buffer be prepared for a receive operation for when a USB host initiates a USB
OUT transaction. Software should write a one to the corresponding bit
whenever posting a new transfer descriptor to an endpoint. Hardware will
automatically use this bit to begin parsing for a new transfer descriptor from the
queue head and prepare a receive buffer. Hardware will clear this bit when the
associated endpoint(s) is (are) successfully primed.

Access
R/WS

PERB0 = endpoint 0
...
PERB5 = endpoint 5
15:6

-

21:16 PETB

Reserved

-

-

Prime endpoint transmit buffer for physical IN endpoints 5 to 0.

0

R/WS

-

-

For each IN endpoint a corresponding bit is set to one by software to request a
buffer be prepared for a transmit operation in order to respond to a USB
IN/INTERRUPT transaction. Software should write a one to the corresponding
bit when posting a new transfer descriptor to an endpoint. Hardware will
automatically use this bit to begin parsing for a new transfer descriptor from the
queue head and prepare a transmit buffer. Hardware will clear this bit when the
associated endpoint(s) is (are) successfully primed.
PETB0 = endpoint 0
...
PETB5 = endpoint 5
31:22 -

Reserved

25.6.20 USB Endpoint Flush register (ENDPTFLUSH)
Writing a one to a bit(s) in this register will cause the associated endpoint(s) to clear any
primed buffers. If a packet is in progress for one of the associated endpoints, then that
transfer will continue until completion. Hardware will clear this register after the endpoint
flush operation is successful.
Table 496. USB Endpoint Flush register (ENDPTFLUSH - address 0x4000 61B4) bit description
Bit

Symbol

Description

Reset
value

Access

5:0

FERB

Flush endpoint receive buffer for physical OUT endpoints 5 to 0.

0

R/WC

Writing a one to a bit(s) will clear any primed buffers.
FERB0 = endpoint 0
...
FERB5 = endpoint 5

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Chapter 25: LPC43xx/LPC43Sxx USB0 Host/Device/OTG controller

Table 496. USB Endpoint Flush register (ENDPTFLUSH - address 0x4000 61B4) bit description
Bit

Symbol

Description

Reset
value

Access

15:6

-

Reserved

-

-

Flush endpoint transmit buffer for physical IN endpoints 5 to 0.

0

R/WC

-

-

21:16 FETB

Writing a one to a bit(s) will clear any primed buffers.
FETB0 = endpoint 0
...
FETB5 = endpoint 5
31:22 -

Reserved

25.6.21 USB Endpoint Status register (ENDPTSTAT)
One bit for each endpoint indicates status of the respective endpoint buffer. This bit is set
by hardware as a response to receiving a command from a corresponding bit in the
ENDPTPRIME register. There will always be a delay between setting a bit in the
ENDPTPRIME register and endpoint indicating ready. This delay time varies based upon
the current USB traffic and the number of bits set in the ENDPTPRIME register. Buffer
ready is cleared by USB reset, by the USB DMA system, or through the ENDPTFLUSH
register.
Remark: These bits will be momentarily cleared by hardware during hardware endpoint
re-priming operations when a dTD is retired and the dQH is updated.
Table 497. USB Endpoint Status register (ENDPTSTAT - address 0x4000 61B8) bit description
Bit

Symbol

Description

Reset
value

Access

5:0

ERBR

Endpoint receive buffer ready for physical OUT endpoints 5 to 0.

0

RO

This bit is set to 1 by hardware as a response to receiving a command from a
corresponding bit in the ENDPTPRIME register.
ERBR0 = endpoint 0
...
ERBR5 = endpoint 5
15:6

-

21:16 ETBR

Reserved

-

-

Endpoint transmit buffer ready for physical IN endpoints 3 to 0.

0

RO

-

-

This bit is set to 1 by hardware as a response to receiving a command from a
corresponding bit in the ENDPTPRIME register.
ETBR0 = endpoint 0
...
ETBR5 = endpoint 5
31:22 -

Reserved

25.6.22 USB Endpoint Complete register (ENDPTCOMPLETE)
Each bit in this register indicates that a received/transmit event occurred and software
should read the corresponding endpoint queue to determine the transfer status. If the
corresponding IOC bit is set in the Transfer Descriptor, then this bit will be set
simultaneously with the USBINT.

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Chapter 25: LPC43xx/LPC43Sxx USB0 Host/Device/OTG controller

Writing a one will clear the corresponding bit in this register.
Table 498. USB Endpoint Complete register (ENDPTCOMPLETE - address 0x4000 61BC) bit description
Bit

Symbol

Description

Reset
value

Access

5:0

ERCE

Endpoint receive complete event for physical OUT endpoints 5 to 0.

0

R/WC

Reserved

-

-

Endpoint transmit complete event for physical IN endpoints 5 to 0.

0

R/WC

-

-

This bit is set to 1 by hardware when receive event (OUT) occurred.
ERCE0 = endpoint 0
...
ERCE5 = endpoint 5
15:6

-

21:16 ETCE

This bit is set to 1 by hardware when a transmit event (IN/INTERRUPT)
occurred.
ETCE0 = endpoint 0
...
ETCE5 = endpoint 5
31:22 -

Reserved

25.6.23 USB Endpoint 0 Control register (ENDPTCTRL0)
This register initializes endpoint 0 for control transfer. Endpoint 0 is always a control
endpoint.
Table 499. USB Endpoint 0 Control register (ENDPTCTRL0 - address 0x4000 61C0) bit description
Bit

Symbol

0

RXS

Value

Description

Reset
value

Access

Rx endpoint stall

0

R/W

00

R/W

Reserved

-

-

Rx endpoint enable

1

RO

-

-

0

Endpoint ok.

1

Endpoint stalled
Software can write a one to this bit to force the endpoint to return a
STALL handshake to the Host. It will continue returning STALL until
the bit is cleared by software, or it will automatically be cleared upon
receipt of a new SETUP request.
After receiving a SETUP request, this bit will continue to be cleared
by hardware until the associated ENDSETUPSTAT bit is cleared.[1]

1

-

3:2

RXT1_0

-

Reserved
Endpoint type
Endpoint 0 is always a control endpoint.

6:4

-

7

RXE

-

Endpoint enabled. Control endpoint 0 is always enabled. This bit is
always 1.
15:8

-

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Chapter 25: LPC43xx/LPC43Sxx USB0 Host/Device/OTG controller

Table 499. USB Endpoint 0 Control register (ENDPTCTRL0 - address 0x4000 61C0) bit description …continued
Bit

Symbol

16

TXS

Value

Description

Reset
value

Tx endpoint stall
0

Endpoint ok.

1

Endpoint stalled

Access
R/W

Software can write a one to this bit to force the endpoint to return a
STALL handshake to the Host. It will continue returning STALL until
the bit is cleared by software, or it will automatically be cleared upon
receipt of a new SETUP request.
After receiving a SETUP request, this bit will continue to be cleared
by hardware until the associated ENDSETUPSTAT bit is cleared.[1]
17

-

-

Reserved

19:18 TXT1_0

Endpoint type

00

RO

1

RO

Endpoint 0 is always a control endpoint.
22:20 23

-

Reserved

TXE

Tx endpoint enable
Endpoint enabled. Control endpoint 0 is always enabled. This bit is
always 1.

31:24 [1]

-

Reserved

There is a slight delay (50 clocks max) between the ENPTSETUPSTAT being cleared and hardware continuing to clear this bit. In most
systems it is unlikely that the DCD software will observe this delay. However, should the DCD notice that the stall bit is not set after
writing a one to it, software should continually write this stall bit until it is set or until a new setup has been received by checking the
associated ENDPTSETUPSTAT bit.

25.6.24 Endpoint 1 to 5 control registers
Each endpoint that is not a control endpoint has its own register to set the endpoint type
and enable or disable the endpoint.
Remark: The reset value for all endpoint types is the control endpoint. If one endpoint
direction is enabled and the paired endpoint of opposite direction is disabled, then the
endpoint type of the unused direction must be changed from the control type to any other
type (e.g. bulk). Leaving an unconfigured endpoint control will cause undefined behavior
for the data PID tracking on the active endpoint.
Table 500. USB Endpoint 1 to 5 control registers (ENDPTCTRL - address 0x4000 61C4 (ENDPTCTRL1) to
0x4000 61D4 (ENDPTCTRL5)) bit description
Bit

Symbol

0

RXS

Value

0

Description

Reset
value

Access

Rx endpoint stall

0

R/W

Endpoint ok.
This bit will be cleared automatically upon receipt of a SETUP
request if this Endpoint is configured as a Control Endpoint and this
bit will continue to be cleared by hardware until the associated
ENDPTSETUPSTAT bit is cleared.

1

Endpoint stalled
Software can write a one to this bit to force the endpoint to return a
STALL handshake to the Host. It will continue returning STALL until
the bit is cleared by software, or it will automatically be cleared upon
receipt of a new SETUP request.

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Table 500. USB Endpoint 1 to 5 control registers (ENDPTCTRL - address 0x4000 61C4 (ENDPTCTRL1) to
0x4000 61D4 (ENDPTCTRL5)) bit description …continued
Bit

Symbol

Value

Description

Reset
value

Access

1

-

Reserved

0

R/W

3:2

RXT

Endpoint type

00

R/W

0

R/W

0

WS

0

R/W

0

R/W

Reserved

0

-

Tx endpoint type

00

R/W

4

-

5

RXI

0x0

Control

0x1

Isochronous

0x2

Bulk

0x3

Interrupt

-

Reserved
Rx data toggle inhibit
This bit is only used for test and should always be written as zero.
Writing a one to this bit will cause this endpoint to ignore the data
toggle sequence and always accept data packets regardless of their
data PID.

6

0

Disabled

1

Enabled

RXR

Rx data toggle reset
Write 1 to reset the PID sequence.
Whenever a configuration event is received for this Endpoint,
software must write a one to this bit in order to synchronize the data
PIDs between the host and device.

7

RXE

Rx endpoint enable
Remark: An endpoint should be enabled only after it has been
configured.

15:8

-

16

TXS

0

Endpoint disabled.

1

Endpoint enabled.

-

Reserved
Tx endpoint stall

0

Endpoint ok.
This bit will be cleared automatically upon receipt of a SETUP
request if this Endpoint is configured as a Control Endpoint, and this
bit will continue to be cleared by hardware until the associated
ENDPTSETUPSTAT bit is cleared.

1

Endpoint stalled
Software can write a one to this bit to force the endpoint to return a
STALL handshake to the Host. It will continue returning STALL until
the bit is cleared by software, or it will automatically be cleared upon
receipt of a new SETUP request.

17

-

-

19:18 TXT1_0

20

-

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Control

0x1

Isochronous

0x2

Bulk

0x3

Interrupt

-

Reserved
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Table 500. USB Endpoint 1 to 5 control registers (ENDPTCTRL - address 0x4000 61C4 (ENDPTCTRL1) to
0x4000 61D4 (ENDPTCTRL5)) bit description …continued
Bit

Symbol

21

TXI

Value

Description

Reset
value

Access

Tx data toggle inhibit

0

R/W

1

WS

0

R/W

This bit is only used for test and should always be written as zero.
Writing a one to this bit will cause this endpoint to ignore the data
toggle sequence and always accept data packets regardless of their
data PID.

22

0

Enabled

1

Disabled

TXR

Tx data toggle reset
Write 1 to reset the PID sequence.
Whenever a configuration event is received for this Endpoint,
software must write a one to this bit in order to synchronize the data
PID’s between the host and device.

23

TXE

Tx endpoint enable
Remark: An endpoint should be enabled only after it has been
configured
0

31:24 -

Endpoint disabled.

1

Endpoint enabled.

-

Reserved

0

25.7 Functional description
25.7.1 OTG core
The OTG core forms the main digital part of the USB-OTG. See the USB EHCI
specification for details about this core.

25.7.2 Host data structures
See Chapter 4 of the USB EHCI Specification for Universal Serial Bus 1.0.

25.7.3 Host operational model
See Chapter 3 of the USB EHCI Specification for Universal Serial Bus 1.0.

25.7.4 ATX_RGEN module
The requirements for the reset signal towards the ATX transceiver are as follows:

• The clocks must be running for a reset to occur correctly.
• The ATX must see a rising edge of reset to correctly reset the clock generation
module.

• The reset must be a minimum of 133 ns (4  30 MHz clock cycles) in duration to reset
all logic correctly.
The ATX_RGEN module generates a reset signal towards the ATX fulfilling above 3
requirements, no matter how the AHB reset looks like.
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25.7.5 ATX transceiver
The USB-OTG has a USB transceiver with UTMI+ interface. It contains the required
transceiver OTG functionality; this includes:

• VBUS sensing for producing the session-valid and VBUS-valid signals.
• sampling of the USB_ID input for detection of A-device or B-device connection.
• charging and discharging of VBUS for starting and ending a session as B-device.
25.7.6 Modes of operation
In general, the USB-OTG can operate either in host mode or in device mode. Software
must put the core in the appropriate mode by setting the USBMODE.CM field (‘11’ for host
mode, ‘10’ for device mode).
The USBMODE.CM field can also be equal to ‘00’, which means that the core is in idle
mode (neither host nor device mode). This will happen after the following:

• a hardware reset.
• a software reset via the USBCMD.RST bit. When switching from host mode to device
mode as part of the HNP protocol (or vice versa), software must issue a software
reset which sets the USB core to the idle state in a time frame dependent on the
software.

25.7.7 SOF/VF indicator
See Section 25.1 for connecting the SOF signal to other peripherals on the LPC43xx.
The USB-OTG generates a SOF/VF indicator signal, which can be used by user specific
external logic.
In FS mode, the SOF/VF indicator signal has a frequency equal to the frame frequency,
which is about 1 kHz. The signal is high for half of the frame period and low for the other
half of the frame period. The positive edge is aligned with the start of a frame (= SOF).
In HS mode, the SOF/VF indicator signal has a frequency equal to the virtual frame
frequency. The positive edge indicates the start of the Virtual Frame and is aligned with
the occurrence of an SOF token on the USB
The length of the virtual frame is defined as: VF = microframe  2bInterval
bInterval is specified in the 4-bit programmable BINTERVAL.BINT register field. The
minimum value of bInterval is 0, the maximum value is 15.
In suspend mode the SOF/VF indicator signal is turned off (= remains low).

25.7.7.1 SOF frame length adjust
Remark: The SOF frame length adjust is implemented on parts with on-chip flash only.
If the USB is in host mode, the SOF length can be changed dynamically based on the
data flow. The frame length adjustment feature is useful when combining the USB with I2S
in an audio application where the audio clock is derived from a highly accurate source. In
this case, I2S is consuming the buffer at the audio clock rate while the USB is filling the
buffer. If software detects that the USB is filling the buffer slowly relative to the I2S
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Chapter 25: LPC43xx/LPC43Sxx USB0 Host/Device/OTG controller

consumption rate, then software can reduce the SOF length using the USB0FLADJ
register. The USB bit clock is still running at the normal rate so no bus errors occur. The
host only changes when it introduces the next SOF token - earlier or later on a bit-time
resolution boundary. Adding the SOF token early allows to obtain more data over the
course of the transmission.
The registers to control the frame length are located in the CREG block (see Table 111).

25.7.8 Hardware assist
The hardware assist provides automated response and sequencing that may not be
possible in software if there are significant interrupt latency response times. The use of
this additional circuitry is optional and can be used to assist the following three state
transitions by setting the appropriate bits in the OTGSC register:

• Auto reset (set bit HAAR).
• Data pulse (set bit HADP).
• B-disconnect to A-connect (set bit HABA).
25.7.8.1 Auto reset
When the HAAR in the OTGSC register is set to one, the host will automatically start a
reset after a connect event. This shortcuts the normal process where software is notified
of the connect event and starts the reset. Software will still receive notification of the
connect event (CCS bit in the PORTSC register) but should not write the reset bit in the
USBCMD register when the HAAR is set. Software will be notified again after the reset is
complete via the enable change bit in the PORTSC register which causes a port change
interrupt.
This assist will ensure the OTG parameter TB_ACON_BSE0_MAX = 1 ms is met (see
OTG specification for an explanation of the OTG timing requirements).

25.7.8.2 Data pulse
Writing a one to HADP in the OTGSC register will start a data pulse of approximately 7 ms
in duration and then automatically cease the data pulsing. During the data pulse, the DP
bit will be set and then cleared. This automation relieves software from accurately
controlling the data-pulse duration. During the data pulse, the HCD can poll to see that the
HADP and DP bit have returned low to recognize the completion, or the HCD can simply
launch the data pulse and wait to see if a VBUS Valid interrupt occurs when the A-side
supplies bus power.
This assist will ensure data pulsing meets the OTG requirement of > 5 ms and < 10 ms.

25.7.8.3 B-disconnect to A-connect (Transition to the A-peripheral state)
During HNP, the B-disconnect occurs from the OTG A_suspend state, and within 3 ms,
the A-device must enable the pull-up on the DP leg in the A-peripheral state. For the
hardware assist to begin the following conditions must be met:

• HABA is set.
• Host controller is in suspend mode.
• Device is disconnecting.
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The hardware assist consists of the following steps:
1. Hardware resets the OTG controller (writes 1 to the RST bit in USBCMD).
2. Hardware selects the device mode (writes 10 to bits CM[1:0] in USBMODE).
3. Hardware sets the RS bit in USBCMD and enables the necessary interrupts:
– USB reset enable (URE) - enables interrupt on USB bus reset to device.
– Sleep enable (SLE) - enables interrupt on device suspend.
– Port change detect enable (PCE) - enables interrupt on device connect.
When software has enabled this hardware assist, it must not interfere during the transition
and should not write any register in the OTG core until it gets an interrupt from the device
controller signifying that a reset interrupt has occurred or until it has verified that the core
has entered device mode. HCD/DCD must not activate the core soft reset at any time
since this action is performed by hardware. During the transition, the software may see an
interrupt from the disconnect and/or other spurious interrupts (i.e. SOF/etc.) that may or
may not cascade and my be cleared by the soft reset depending on the software response
time.
After the core has entered device mode with help of the hardware assist, the DCD must
ensure that the ENDPTLISTADDR is programmed properly before the host sends a setup
packet. Since the end of the reset duration, which may be initiated quickly (a few
microseconds) after connect, will require at a minimum 50 ms, this is the time for which
the DCD must be ready to accept setup packets after having received notification that the
reset has been detected or simply that the OTG is in device mode which ever occurs first.
If the A-peripheral fails to see a reset after the controller enters device mode and engages
the D+-pull-up, the device controller interrupts the DCD signifying that a suspend has
occurred. This assist will ensure the parameter TA_BDIS_ACON_MAX = 3ms is met.

25.8 Deviations from EHCI standard
For the purposes of a dual-role Host/Device controller with support for On-The-Go
applications, it is necessary to deviate from the EHCI specification. Device operation and
On-The-Go operation is not specified in the EHCI and thus the implementation supported
in this core is specific to the LPC43xx. The host mode operation of the core is near EHCI
compatible with few minor differences documented in this section.
The particulars of the deviations occur in the areas summarized here:

• Embedded Transaction Translator – Allows direct attachment of FS and LS devices in
host mode without the need for a companion controller.

• Device operation - In host mode the device operational registers are generally
disabled and thus device mode is mostly transparent when in host mode. However,
there are a couple exceptions documented in the following sections.

• On-The-Go Operation - This design includes an On-The-Go controller.
25.8.1 Embedded Transaction Translator function
The USB-HS OTG controller supports directly connected full and low speed devices
without requiring a companion controller by including the capabilities of a USB 2.0 high
speed hub transaction translator. Although there is no separate Transaction Translator
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block in the system, the transaction translator function normally associated with a high
speed hub has been implemented within the DMA and Protocol engine blocks. The
embedded transaction translator function is an extension to EHCI interface but
makes use of the standard data structures and operational models that exist in the EHCI
specification to support full and low speed devices.

25.8.1.1 Capability registers
The following items have been added to the capability registers to support the embedded
Transaction Translator Function:

• N_TT bits added to HCSPARAMS – Host Control Structural Parameters (see
Table 464).

• N_PTT added to HCSPARAMS – Host Control Structural Parameters (see Table 464).
25.8.1.2 Operational registers
The following items have been added to the operational registers to support the
embedded TT:

• New register TTCTRL (see Section 25.6.9).
• Two-bit Port Speed (PSPD) bits added to the PORTSC1 register (see
Section 25.6.15).

25.8.1.3 Discovery
In a standard EHCI controller design, the EHCI host controller driver detects a Full speed
(FS) or Low speed (LS) device by noting if the port enable bit is set after the port reset
operation. The port enable will only be set in a standard EHCI controller implementation
after the port reset operation and when the host and device negotiate a High-Speed
connection (i.e. Chirp completes successfully). Since this controller has an embedded
Transaction Translator, the port enable will always be set after the port reset operation
regardless of the result of the host device chirp result and the resulting port speed will be
indicated by the PSPD field in PORTSC1 (see Section 25.6.15).
Table 501. Handling of directly connected full-speed and low-speed devices

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EHCI with embedded Transaction Translator

After the port enable bit is set following a
connection and reset sequence, the device/hub
is assumed to be HS.

After the port enable bit is set following a
connection and reset sequence, the device/hub
speed is noted from PORTSC1.

FS and LS devices are assumed to be
downstream from a HS hub thus, all port-level
control is performed through the Hub Class to
the nearest Hub.

FS and LS device can be either downstream
from a HS hub or directly attached. When the
FS/LS device is downstream from a HS hub,
then port-level control is done using the Hub
Class through the nearest Hub. When a FS/LS
device is directly attached, then port-level
control is accomplished using PORTSC1.

FS and LS devices are assumed to be
downstream from a HS hub with HubAddr=X,
where HubAddr > 0 and HubAddr is the address
of the Hub where the bus transitions from HS to
FS/LS (i.e. Split target hub).

FS and LS device can be either downstream
from a HS hub with HubAddr = X [HubAddr > 0]
or directly attached, where HubAddr = TTHA
(TTHA is programmable and defaults to 0) and
HubAddr is the address of the Root Hub where
the bus transitions from HS to FS/LS (i.e. Split
target hub is the root hub).

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25.8.1.4 Data structures
The same data structures used for FS/LS transactions though a HS hub are also used for
transactions through the Root Hub with an embedded Transaction Translator. Here it is
demonstrated how the Hub Address and Endpoint Speed fields should be set for directly
attached FS/LS devices and hubs:
1. QH (for directly attached FS/LS device) – Async. (Bulk/Control Endpoints) Periodic
(Interrupt)
– Hub Address = TTHA (default TTHA = 0)
– Transactions to directly attached device/hub: QH.EPS = Port Speed
– Transactions to a device downstream from directly attached FS hub: QH.EPS =
Downstream Device Speed
Remark: When QH.EPS = 01 (LS) and PORTSC1.PSPD = 00 (FS), a LS-pre-pid
will be sent before transmitting the LS traffic.
Maximum Packet Size must be less than or equal to 64 or undefined behavior may
result.
2. siTD (for directly attached FS device) – Periodic (ISO Endpoint)
all FS ISO transactions:
Hub Address = (default TTHA = 0)
siTD.EPS = 00 (full speed)
Maximum Packet Size must be less than or equal to 1023 or undefined behavior may
result.

25.8.1.5 Operational model
The operational models are well defined for the behavior of the Transaction Translator
(see USB 2.0 specification) and for the EHCI controller moving packets between system
memory and a USB-HS hub. Since the embedded Transaction Translator exists within the
host controller there is no physical bus between the EHCI host controller driver and the
USB FS/LS bus. These sections will briefly discuss the operational model for how the
EHCI and Transaction Translator operational models are combined without the physical
bus between them. The following sections assume the reader is familiar with both the
EHCI and USB 2.0 Transaction Translator operational models.
25.8.1.5.1

Micro-frame pipeline
The EHCI operational model uses the concept of H-frames and B-frames to describe the
pipeline between the Host (H) and the Bus (B). The embedded Transaction Translator
shall use the same pipeline algorithms specified in the USB 2.0 specification for a
Hub-based Transaction Translator.
It is important to note that when programming the S-mask and C-masks in the EHCI data
structures to schedule periodic transfers for the embedded Transaction Translator, the
EHCI host controller driver must follow the same rules specified in EHCI for programming
the S-mask and C-mask for downstream Hub-based Transaction Translators. Once
periodic transfers are exhausted, any stored asynchronous transfer will be moved.
Asynchronous transfers are opportunistic in that they shall execute whenever possible
and their operation is not tied to H-frame and B-frame boundaries with the exception that
an asynchronous transfer can not babble through the SOF (start of B-frame 0.)

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25.8.1.6 Split state machines
The start and complete split operational model differs from EHCI slightly because there is
no bus medium between the EHCI controller and the embedded Transaction Translator.
Where a start or complete-split operation would occur by requesting the split to the HS
hub, the start/complete split operation is simply an internal operation to the embedded
Transaction Translator. The following table summarizes the conditions where handshakes
are emulated from internal state instead of actual handshakes to HS split bus traffic.
Table 502. Split state machine properties
Condition
Start-split

Complete-split

Emulate TT response

All asynchronous buffers full.

NAK

All periodic buffers full.

ERR

Success for start of Async. Transaction.

ACK

Start Periodic Transaction.

No Handshake (Ok)

Failed to find transaction in queue.

Bus Time Out

Transaction in Queue is Busy.

NYET

Transaction in Queue is Complete.

[Actual Handshake from
LS/FS device]

25.8.1.7 Asynchronous Transaction scheduling and buffer management
The following USB 2.0 specification items are implemented in the embedded Transaction
Translator:
1. USB 2.0 specification, section 11.17.3: Sequencing is provided & a packet length
estimator ensures no full-speed/low-speed packet babbles into SOF time.
2. USB 2.0 specification, section 11.17.4: Transaction tracking for 2 data pipes.
3. USB 2.0 specification, section 11.17.5: Clear_TT_Buffer capability provided though
the use of the TTCTRL register.

25.8.1.8 Periodic Transaction scheduling and buffer management
The following USB 2.0 specification items are implemented in the embedded Transaction
Translator:
1. USB 2.0 specs, section 11.18.6.[1-2]:
– Abort of pending start-splits:
EOF (and not started in micro-frames 6)
Idle for more than 4 micro-frames
– Abort of pending complete-splits:
EOF
Idle for more than 4 micro-frames
2. USB 2.0 specs, section 11.18.6.[7-8]:
– Transaction tracking for up to 16 data pipes:
– Complete-split transaction searching:

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There is no data schedule mechanism for these transactions other than
micro-frame pipeline. The embedded TT assumes the number of packets
scheduled in a frame does not exceed the frame duration (1 ms) or else undefined
behavior may result.

25.8.1.9 Multiple Transaction Translators
The maximum number of embedded Transaction Translators that is currently supported is
one as indicated by the N_TT field in the HCSPARAMS – Host Control Structural
Parameters register.

25.8.2 Device operation
The co-existence of a device operational controller within the host controller has little
effect on EHCI compatibility for host operation except as noted in this section.

25.8.2.1 USBMODE register
Given that the dual-role controller is initialized in neither host nor device mode, the
USBMODE register must be programmed for host operation before the EHCI host
controller driver can begin EHCI host operations.

25.8.2.2 Non-Zero register fields
Some of the reserved fields and reserved addresses in the capability registers and
operational register are used in device mode.For read and write operations to these
register, note the following:

• Always write zero to all EHCI reserved fields (some of which are device fields). This
is an EHCI requirement of the device controller driver.

• Read operations by the host controller must properly mask EHCI reserved fields
(some of which are device fields) because fields that are used exclusively in device
mode are undefined in host mode.

25.8.2.3 SOF interrupt
This SOF Interrupt used for device mode is also used in host mode. In host mode, this
interrupt is raised every 125 s (high-speed mode). EHCI does not specify this interrupt
but it has been added for convenience and as a potential software time base. See
USBSTS (Section 25.6.4) and USBINTR (Section 25.6.5) registers.

25.8.3 Deviations from EHCI
25.8.3.1 Discovery
25.8.3.1.1

Port reset
The port connect methods specified by EHCI require setting the port reset bit in the
PORTSC1 register for a duration of 10 ms. Due to the complexity required to support the
attachment of devices that are not high speed, there are counters already present in the
design that can count the 10 ms reset pulse to alleviate the burden on the software to
measure this duration. The basic connection is summarized as follows:

• [Port Change Interrupt] Port connect change occurs to notify the host controller driver
that a device has attached.
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• Software writes a ‘1’ to the port reset bit in the PORTSC1 register to reset the device.
• Software writes a ‘0’ to the port reset bit in the PORTSC1 register after 10 ms.
This step, which is necessary in a standard EHCI design, may be omitted with this
implementation. Should the EHCI host controller driver attempt to write a ‘0’ to the
port reset bit while a reset is in progress, the write will simply be ignored, and the reset
will continue until completion.

• [Port Change Interrupt] Port enable change occurs to notify the host controller that
the device is now operational, and at this point the port speed has been determined.
25.8.3.1.2

Port speed detection
After the port change interrupt indicates that a port is enabled, the EHCI stack should
determine the port speed. Unlike the EHCI implementation which will re-assign the port
owner for any device that does not connect at High-Speed, this host controller supports
direct-attach of non High-Speed devices. Therefore, the following differences are
important regarding port speed detection:

• Port Owner is read-only and always reads 0.
• A 2-bit Port Speed indicator has been added to the PORTSC1register to provide the
current operating speed of the port to the host controller driver.

• A 1-bit High Speed indicator has been added to the PORTSC1register to indicate that
the port is in High-Speed vs. Full/Low Speed – This information is redundant with the
2-bit Port Speed indicator above.

25.9 Device data structures
This section defines the interface data structures used to communicate control, status,
and data between Device Controller Driver (DCD) Software and the device controller. The
data structure definitions in this chapter support a 32-bit memory buffer address space.
Remark: The software must ensure that no interface data structure reachable by the
Device controller crosses a 4kB-page boundary.
The data structures defined in the chapter are (from the device controller’s perspective) a
mix of read-only and read/ writable fields. The DCD must preserve the read-only fields on
all data structure writes.

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Endpoint Queue Heads
dQH

Endpoint Transfer
Descriptors dTD

Endpoint dQH5 - IN
Endpoint dQH5 - OUT

dTD

dTD
Endpoint dQH1 - OUT

dTD

Control Endpoint dQH0 - IN

dTD

Control Endpoint dQH0 - OUT

dTD

TRANSFER
BUFFER

TRANSFER
BUFFER

TRANSFER
BUFFER

transfer buffer
pointer
transfer buffer
pointer

ENDPOINTLISTADDR

transfer buffer
pointer

transfer buffer
pointer

TRANSFER
BUFFER

Fig 68. Endpoint queue head organization

Device queue heads are arranged in an array in a continuous area of memory pointed to
by the ENDPOINTLISTADDR pointer. The even device queue heads in the list are used
for receive endpoints (OUT) and the odd-numbered queue heads in the list are used for
transmit endpoints (IN). The device controller will index into this array based upon the
endpoint number in the USB request. All information necessary to respond to transactions
for all primed transfers is contained in this list so the device controller can readily respond
to incoming requests without having to traverse a linked list.
Remark: The Endpoint Queue Head List must be aligned to a 2 kB boundary.

25.9.1 Endpoint queue head (dQH)
The device Endpoint Queue Head (dQH) is where all transfers are managed. The dQH is
a 48-byte data structure but must be aligned on 64-byte boundaries. During priming of an
endpoint, the dTD (device transfer descriptor) is copied into the overlay area of the dQH
(see Figure 69), which starts at the nextTD pointer DWord and continues through the end
of the buffer pointers DWords. After a transfer is complete, the dTD status DWord is
updated in the dTD pointed to by the currentTD pointer. While a packet is in progress, the
overlay area of the dQH is used as a staging area for the dTD so that the device controller
can access needed information with minimal latency.
Remark: In USB device control case, if the system error occurs, check if the endpoint
transfer descriptor are programmed perfectly by software application during
set_configuration request. The system error will occur if the hardware accesses
inaccessible memory space for end point access.

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device Queue Head (dQH)
offset
0x00

bit

31

0

ENDPOINT CAPABILITIES/CHARACTERISTICS

0x04

CURRENT dTD POINTER

0x08

NEXT dTD POINTER

0x0C

transfer overlay

Total_bytes

IOC

0x10

BUFFER POINTER PAGE 0

0x14

endpoint transfer descriptor (dTD)
NEXT dTD POINTER

T

MulO

STATUS
CURR_OFFS

Total_bytes

IOC

MulO

T
STATUS

BUFFER POINTER PAGE 0

CURR_OFFS

BUFFER POINTER PAGE 1

BUFFER POINTER PAGE 1

FRAME_N

0x18

BUFFER POINTER PAGE 2

BUFFER POINTER PAGE 2

0x1C

BUFFER POINTER PAGE 3

BUFFER POINTER PAGE 3

0x20

BUFFER POINTER PAGE 4

BUFFER POINTER PAGE 4

0x24

RESERVED

0x28

SET-UP BUFFER: BYTES 3:0

0x2C

SET-UP BUFFER: BYTES 7:4

Fig 69. Endpoint queue head data structure

25.9.1.1 Endpoint capabilities and characteristics descriptor fields
This DWord specifies static information about the endpoint, in other words, this
information does not change over the lifetime of the endpoint. The device controller
software should not attempt to modify this information while the corresponding endpoint is
enabled.

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Table 503. Endpoint capabilities and characteristics
Access Bit
RO

Name

Description

31:30 MULT

Number of packets executed per transaction descriptor
00 - Execute N transactions as demonstrated by the USB variable
length protocol where N is computed using Max_packet_length
and the Total_bytes field in the dTD.
01 - Execute one transaction
10 - Execute two transactions
11 - Execute three transactions
Remark: Non-isochronous endpoints must set MULT = 00.
Remark: Isochronous endpoints must set MULT = 01, 10, or 11
as needed.

RO

29

ZLT

Zero length termination select
This bit is used for non-isochronous endpoints to indicate when a
zero-length packet is received to terminate transfers in case the
total transfer length is “multiple”.
0 - Enable zero-length packet to terminate transfers equal to a
multiple of Max_packet_length (default).
1 - Disable zero-length packet on transfers that are equal in
length to a multiple Max_packet_length.

RO

28:27 -

reserved

RO

26:16 Max_packet
_length

Maximum packet size of the associated endpoint (<= 1024)

RO

15

Interrupt on setup

IOS

This bit is used on control type endpoints to indicate if USBINT is
set in response to a setup being received.
RO

14:0

-

reserved

25.9.1.2 Current dTD pointer descriptor fields
The current dTD pointer is used by the device controller to locate the transfer in progress.
This word is for device controller (hardware) use only and should not be modified by DCD
software.
Table 504. Current dTD pointer
Access

Bit

Name

Description

R/W
31:5
(hardware
only)

Current_TD_pointer Current dTD pointer

-

-

4:0

This field is a pointer to the dTD that is represented in
the transfer overlay area. This field will be modified by
the device controller to the next dTD pointer during
endpoint priming or queue advance.
reserved

25.9.1.3 Transfer overlay descriptor fields
The seven DWords in the overlay area represent a transaction working space for the
device controller. The general operational model is that the device controller can detect
whether the overlay area contains a description of an active transfer. If it does not contain
an active transfer, then it will not read the associated endpoint.
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After an endpoint is readied, the dTD will be copied into this queue head overlay area by
the device controller. Until a transfer is expired, software must not write the queue head
overlay area or the associated transfer descriptor. When the transfer is complete, the
device controller will write the results back to the original transfer descriptor and advance
the queue. See dTD for a description of the overlay fields.

25.9.1.4 Set-up buffer descriptor fields
The set-up buffer is dedicated storage for the 8-byte data that follows a set-up PID.
Remark: Each endpoint has a TX and an RX dQH associated with it, and only the RX
queue head is used for receiving setup data packets.
Table 505. Set-up buffer
Dword

Access

Bit

Name

1

R/W

31:0

BUF0

Description
Setup buffer 0
This buffer contains bytes 3 to 0 of an incoming setup
buffer packet and is written by the device controller to
be read by software.

2

R/W

31:0

BUF1

Setup buffer 1
This buffer contains bytes 7 to 4 of an incoming setup
buffer packet and is written by the device controller to
be read by software.

25.9.2 Endpoint transfer descriptor (dTD)
The dTD describes to the device controller the location and quantity of data to be
sent/received for a given transfer. The DCD should not attempt to modify any field in an
active dTD except the Next Link Pointer, which should only be modified as described in
Section 25.10.11.
Table 506. Next dTD pointer
Access Bit
RO

Name

Description

31:5 Next_link_pointer

Next link pointer
This field contains the physical memory address of the next
dTD to be processed. The field corresponds to memory
address signals [31:5], respectively.

4:1

-

reserved

0

T

Terminate
This bit indicates to the device controller when there are no
more valid entries in the queue.
1 - pointer is invalid
0 - Pointer is valid, i.e. pointer points to a valid transfer
element descriptor.

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Table 507. dTD token
Access

Bit

Name

Description

-

31

-

reserved

R/W

30:16

Total_bytes

Total bytes
This field specifies the total number of bytes to be moved with
this transfer descriptor. This field is decremented by the
number of bytes actually moved during the transaction and it
is decremented only when the transaction has been
completed successfully.
The maximum value software can write into this field is
0x5000 (5 x 4 kB) for the maximum number of bytes five page
pointers can access. Although it is possible to create a
transfer up to 20 kB this assumes that the first offset into the
first page is zero. When the offset cannot be predetermined,
crossing past the fifth page can be guaranteed by limiting the
total bytes to 16 kB. Therefore, the maximum recommended
Total-Bytes = 16 kB (0x4000).
If Total_bytes = 0 when the host controller fetches this
transfer descriptor and the active bit is set in the Status field
of this dTD, the device controller executes a zero-length
transaction and retires the dTD.
Remark: For IN transfers, it is not a requirement that
Total_bytes is an even multiple of Max_packet_length. If
software builds such a dTD, the last transaction will always be
less than Max_packet_length.

RO

15

IOC

Interrupt on complete
This bit is used to indicate if USBINT will be set when the
device controller is finished with this dTD.
1 - USBINT set.
0 - USBINT not set.

-

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-

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Table 507. dTD token …continued
Access

Bit

Name

Description

RO

11:10

MultO

Multiplier Override (see Section 25.9.2.1 for an example)
This field can be used for transmit ISOs to override the MULT
field in the dQH. This field must be zero for all packet types
that are not transmit-ISO.
00 - Execute N transactions as demonstrated by the USB
variable length protocol where N is computed using
Max_packet_length and the Total_bytes field in the dTD.
01 - Execute one transaction
10 - Execute two transactions
11 - Execute three transactions
Remark: Non-ISO and Non-TX endpoints must set
MultO=”00”.

R/W

9:8

-

reserved

7:0

Status

Status
This field is used by the device controller to communicate
individual execution states back to the software. This field
contains the status of the last transaction performed on this
dTD.
Bit 7 = 1 - status: Active
Bit 6 = 1 - status: Halted
Bit 5 = 1 - status: Buffer Error
Bit 4 - reserved
Bit 3 = 1 - status: Transaction Error
Bit 2 - reserved
Bit 1 - reserved
Bit 0 - reserved

Table 508. dTD buffer page pointer list
Access

Bit

Name

Description

RO

31:12

BUFF_P

Selects the page offset in memory for the packet buffer.
Non-virtual memory systems will typically set the buffer
pointers to a series of incrementing integers.

page 0:
11:0

CURR_OFFS

Offset into the 4 kB buffer where the packet is to begin.

page 1:
10:0

FRAME_N

Written by the device controller to indicate the frame
number in which a packet finishes. This is typically
used to correlate relative completion times of packets
on an isochronous endpoint.

25.9.2.1 Determining the number of packets for Isochronous IN endpoints
The following examples show how the MULT field in the dQH and the MultO in the dTD
are used to control the number of packets sent in an In-transaction for an isochronous
endpoint:
Example 1
MULT = 3; Max_packet_size = 8; Total_bytes = 15; MultO = 0 (default)
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In this case three packets are sent: Data2 (8 bytes), Data1 (7 bytes), Data0 (0 bytes).
Example 2
MULT = 3; Max_packet_size = 8; Total_bytes = 15; MultO = 2
In this case two packets are sent: Data1 (8 bytes), Data0 (7 bytes).
To optimize efficiency for IN transfers, software should compute MultO = greatest integer
of (Total_bytes/Max_packet_size). If Total_bytes = 0, then MultO should be 1.

25.10 Device operational model
The function of the device operation is to transfer a request in the memory image to and
from the Universal Serial Bus. Using a set of linked list transfer descriptors, pointed to by
a queue head, the device controller will perform the data transfers. The following sections
explain the use of the device controller from the device controller driver (DCD)
point-of-view and further describe how specific USB bus events relate to status changes
in the device controller programmer's interface.

25.10.1 Device controller initialization
After hardware reset, the device is disabled until the Run/Stop bit is set to a ‘1’. In the
Disabled state, the pull-up on the USB_DM is not active which prevents an attach event
from occurring. At a minimum, it is necessary to have the queue heads setup for endpoint
zero before the device attach occurs. Shortly after the device is enabled, a USB reset will
occur followed by a setup packet arriving at endpoint 0. A Queue head must be prepared
so that the device controller can store the incoming setup packet.
In order to initialize a device, the software should perform the following steps:
1. Set Controller Mode in the USBMODE register to device mode.
Remark: Transitioning from host mode to device mode requires a device controller
reset before modifying USBMODE.
2. Allocate and Initialize device queue heads in system memory (see Section 25.9).
Minimum: Initialize device queue heads 0 Tx & 0 Rx.
Remark: All device queue heads associated with control endpoints must be initialized
before the control endpoint is enabled. Non-Control device queue heads must be
initialized before the endpoint is used and not necessarily before the endpoint is
enabled.
3. Configure ENDPOINTLISTADDR Pointer (see Section 25.6.8).
4. Enable the microprocessor interrupt associated with the USB-HS core.
Recommended: enable all device interrupts including: USBINT, USBERRINT, Port
Change Detect, USB Reset Received, DCSuspend (see Table 473).
5. Set Run/Stop bit to Run Mode.
After the Run bit is set, a device reset will occur. The DCD must monitor the reset
event and adjust the software state as described in the Bus Reset section of the Port
State and Control section (see Section 25.10.2).
Remark: Endpoint 0 is designed as a control endpoint only and does not need to be
configured using ENDPTCTRL0 register.
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It is also not necessary to initially prime Endpoint 0 because the first packet received will
always be a setup packet. The contents of the first setup packet will require a response in
accordance with USB device framework command set (see USB Specification Rev. 2.0,
chapter 9).

25.10.2 Port state and control
From a chip or system reset, the device controller enters the Powered state. A transition
from the Powered state to the Attached state occurs when the Run/Stop bit is set to a ‘1’.
After receiving a reset on the bus, the port will enter the defaultFS or defaultHS state in
accordance with the reset protocol described in Appendix C.2 of the USB Specification
Rev. 2.0. The following state diagram depicts the state of a USB 2.0 device.

active state

Powered
set Run/Stop bit
to Run mode

inactive state

power
interruption
Attached

reset
bus inactive
Su

Default
FS/HS

Suspended
FS/HS
bus activity

when the host
resets, the device
returns to default
state

address
asigned
bus inactive
Address
FS/HSS

Suspended
FS/HS
bus activity

device
deconfigured

device
configured
bus inactive

Configured
FS/HS

Suspended
FS/HS

software only state
bus activity

Fig 70. Device state diagram
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The states powered, attach, default FS/HS, suspend FS/HS are implemented in the
device controller and are communicated to the DCD using the following status bits:

•
•
•
•

DCSuspend - see Table 471.
USB reset received - see Table 471.
Port change detect - see Table 471.
High-speed port - see Table 488.

It is the responsibility of the DCD to maintain a state variable to differentiate between the
DefaultFS/HS state and the Address/Configured states. Change of state from Default to
Address and the configured states is part of the enumeration process described in the
Device Framework section of the USB 2.0 Specification.
As a result of entering the Address state, the device address register (DEVICEADDR)
must be programmed by the DCD.
Entry into the Configured state indicates that all endpoints to be used in the operation of
the device have been properly initialized by programming the ENDPTCTRLx registers and
initializing the associated queue heads.

25.10.3 Bus reset
A bus reset is used by the host to initialize downstream devices. When a bus reset is
detected, the device controller will renegotiate its attachment speed, reset the device
address to 0, and notify the DCD by interrupt (assuming the USB Reset Interrupt Enable
is set). After a reset is received, all endpoints (except endpoint 0) are disabled and any
primed transactions will be cancelled by the device controller. The concept of priming will
be clarified below, but the DCD must perform the following tasks when a reset is received:

• Clear all setup token semaphores by reading the ENDPTSETUPSTAT register and
writing the same value back to the ENDPTSETUPSTAT register.

• Clear all the endpoint complete status bits by reading the ENDPTCOMPLETE register
and writing the same value back to the ENDPTCOMPLETE register.

• Cancel all primed status by waiting until all bits in the ENDPTPRIME register are 0
and then writing 0xFFFFFFFF to the ENDPTFLUSH register.

• Read the reset bit in the PORTSC1 register and make sure that it is still active. A USB
reset will occur for a minimum of 3 ms and the DCD must reach this point in the reset
cleanup before end of the reset occurs, otherwise a hardware reset of the device
controller is recommended (rare).
Remark: A hardware reset can be performed by writing a one to the device controller
reset bit in the USBCMD register. A hardware reset will cause the device to detach
from the bus by clearing the Run/Stop bit. Thus, the DCD must completely re-initialize
the device controller after a hardware reset.

• Free all allocated dTDs because they will no longer be executed by the device
controller. If this is the first time the DCD is processing a USB reset event, then it is
likely that no dTDs have been allocated. At this time, the DCD may release control
back to the OS because no further changes to the device controller are permitted until
a Port Change Detect is indicated.

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• After a Port Change Detect, the device has reached the default state and the DCD
can read the PORTSC1 to determine if the device is operating in FS or HS mode. At
this time, the device controller has reached normal operating mode and DCD can
begin enumeration according to the USB2.0 specification Chapter 9 - Device
Framework.
Remark: The device DCD may use the FS/HS mode information to determine the
bandwidth mode of the device.
In some applications, it may not be possible to enable one or more pipes while in FS
mode. Beyond the data rate issue, there is no difference in DCD operation between FS
and HS modes.

25.10.4 Suspend/resume
25.10.4.1 Suspend
In order to conserve power, USB devices automatically enter the Suspended state when
the device has observed no bus traffic for a specified period. When suspended, the USB
device maintains any internal status, including its address and configuration. Attached
devices must be prepared to suspend any time they are in the Default, Address, or
Configured state. Bus activity may cease due to the host entering a suspend mode of its
own. In addition, a USB device shall also enter the suspended state when the hub port it is
attached to is disabled.
A USB device exits suspend mode when there is bus activity. A USB device may also
request the host to exit suspend mode or selective suspend by using electrical signaling to
indicate remote wake-up. The ability of a device to signal remote wake-up is optional. If
the USB device is capable of remote wake-up signaling, the device must support the
ability of the host to enable and disable this capability. When the device is reset, remote
wake-up signaling must be disabled.
25.10.4.1.1

Operational model
The device controller moves into the Suspended state when suspend signaling is
detected or activity is missing on the upstream port for more than a specific period. After
the device controller enters the Suspended state, the DCD is notified by an interrupt
(assuming DC Suspend Interrupt is enabled). When the DCSuspend bit in the PORTSC1
is set to a ‘1’, the device controller is suspended.
DCD response when the device controller is suspended is application specific and may
involve switching to low power operation. Information on the bus power limits in the
Suspended state can be found in USB 2.0 specification.

25.10.4.2 Resume
If the device controller is suspended, its operation is resumed when any non-idle signaling
is received on its upstream facing port. In addition, the device can signal the system to
resume operation by forcing resume signaling to the upstream port. Resume signaling is
sent upstream by writing a ‘1’ to the Resume bit in the in the PORTSC1 while the device is
in the Suspended state. Sending resume signal to an upstream port should cause the host
to issue resume signaling and bring the suspended bus segment (one or more devices)
back to the active condition.

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Remark: Before resume signaling can be used, the host must enable it by using the Set
Feature command defined in USB Device Framework (chapter 9) of the USB 2.0
Specification.

25.10.5 Managing endpoints
The USB 2.0 specification defines an endpoint, also called a device endpoint or an
address endpoint as a uniquely addressable portion of a USB device that can source or
sink data in a communications channel between the host and the device. The endpoint
address is specified by the combination of the endpoint number and the endpoint
direction.
The channel between the host and an endpoint at a specific device represents a data
pipe. Endpoint 0 for a device is always a control type data channel used for device
discovery and enumeration. Other types of endpoints supported by USB include bulk,
interrupt, and isochronous. Each endpoint type has specific behavior related to packet
response and error handling. More detail on endpoint operation can be found in the USB
2.0 specification.
The LPC43xx USB0 controller supports up to six endpoints.
Each endpoint direction is essentially independent and can be configured with differing
behavior in each direction. For example, the DCD can configure endpoint 1-IN to be a bulk
endpoint and endpoint 1- OUT to be an isochronous endpoint. This helps to conserve the
total number of endpoints required for device operation. The only exception is that control
endpoints must use both directions on a single endpoint number to function as a control
endpoint. Endpoint 0 , for example, is always a control endpoint and uses both directions.
Each endpoint direction requires a queue head allocated in memory. For is 6 endpoint
numbers, one queue head for each endpoint direction is used by the device controller for
a total of 12 queue heads. The operation of an endpoint and the use of queue heads are
described later in this document.

25.10.5.1 Endpoint initialization
After hardware reset, all endpoints except endpoint zero are un-initialized and disabled.
The DCD must configure and enable each endpoint by writing to the RXE or TXE bit in the
ENDPTCTRLx register (see Table 500). Each 32-bit ENDPTCTRLx is split into an upper
and lower half. The lower half of ENDPTCTRLx is used to configure the receive or OUT
endpoint and the upper half is likewise used to configure the corresponding transmit or IN
endpoint. Control endpoints must be configured the same in both the upper and lower half
of the ENDPTCTRLx register otherwise the behavior is undefined. The following table
shows how to construct a configuration word for endpoint initialization.
Table 509. Device controller endpoint initialization
Field

Value

Data Toggle Reset

1

Data Toggle Inhibit

0

Endpoint Type

00 - control
01 - isochronous

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Table 509. Device controller endpoint initialization
Field

Value
10 - bulk
11 - interrupt

Endpoint Stall

0

25.10.5.2 Stalling
There are two occasions where the device controller may need to return to the host a
STALL:
1. The first occasion is the functional stall, which is a condition set by the DCD as
described in the USB 2.0 device framework (chapter 9). A functional stall is only used
on non-control endpoints and can be enabled in the device controller by setting the
endpoint stall bit in the ENDPTCTRLx register associated with the given endpoint and
the given direction. In a functional stall condition, the device controller will continue to
return STALL responses to all transactions occurring on the respective endpoint and
direction until the endpoint stall bit is cleared by the DCD.
2. A protocol stall, unlike a function stall, is only used on control endpoints and is
automatically cleared by the device controller at the start of a new control transaction
(setup phase). When enabling a protocol stall, the DCD should enable the stall bits
(both directions) as a pair. A single write to the ENDPTCTRLx register can ensure that
both stall bits are set at the same instant.
Remark: Any write to the ENDPTCTRLx register during operational mode must preserve
the endpoint type field (i.e. perform a read-modify-write).
Table 510. Device controller stall response matrix
USB packet

Endpoint
STALL bit

Effect on
STALL bit

USB response

SETUP packet received by a non-control
endpoint.

N/A

None

STALL

IN/OUT/PING packet received by a
non-control endpoint.

1

None

STALL

IN/OUT/PING packet received by a
non-control endpoint.

0

None

ACK/NAK/NYET

SETUP packet received by a control endpoint. N/A

Cleared

ACK

IN/OUT/PING packet received by a control
endpoint.

1

None

STALL

IN/OUT/PING packet received by a control
endpoint.

0

None

ACK/NAK/NYET

25.10.5.3 Data toggle
Data toggle is a mechanism to maintain data coherency between host and device for any
given data pipe. For more information on data toggle, refer to the USB 2.0 specification.

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25.10.5.3.1

Data toggle reset
The DCD may reset the data toggle state bit and cause the data toggle sequence to reset
in the device controller by writing a ‘1’ to the data toggle reset bit in the ENDPTCTRLx
register. This should only be necessary when configuring/initializing an endpoint or
returning from a STALL condition.

25.10.5.3.2

Data toggle inhibit
Remark: This feature is for test purposes only and should never be used during normal
device controller operation.
Setting the data toggle Inhibit bit active (‘1’) causes the device controller to ignore the data
toggle pattern that is normally sent and accept all incoming data packets regardless of the
data toggle state. In normal operation, the device controller checks the DATA0/DATA1 bit
against the data toggle to determine if the packet is valid. If Data PID does not match the
data toggle state bit maintained by the device controller for that endpoint, the data toggle
is considered not valid. If the data toggle is not valid, the device controller assumes the
packet was already received and discards the packet (not reporting it to the DCD). To
prevent the host controller from re-sending the same packet, the device controller will
respond to the error packet by acknowledging it with either an ACK or NYET response.

25.10.6 Operational model for packet transfers
All transactions on the USB bus are initiated by the host and in turn, the device must
respond to any request from the host within the turnaround time stated in the USB 2.0
Specification. At USB 1.1 Full or Low Speed rates, this turnaround time was significant
and the USB 1.1 device controllers were designed so that the device controller could
access main memory or interrupt a host protocol processor in order to respond to the USB
1.1 transaction. The architecture of the USB 2.0 device controller is different because the
same methods will not meet USB 2.0 High-speed turnaround time requirements by simply
increasing the clock rate.
A USB host will send requests to the device controller in an order that can not be precisely
predicted as a single pipeline, so it is not possible to prepare a single packet for the device
controller to execute. However, the order of packet requests is predictable when the
endpoint number and direction is considered. For example, if endpoint 3 (transmit
direction) is configured as a bulk pipe, then we can expect the host will send IN requests
to that endpoint. This device controller is designed in such a way that it can prepare
packets for each endpoint/direction in anticipation of the host request. The process of
preparing the device controller to send or receive data in response to host initiated
transaction on the bus is referred to as “priming” the endpoint. This term will be used
throughout the following documentation to describe the device controller operation so the
DCD can be designed properly to use priming. Further, note that the term “flushing” is
used to describe the action of clearing a packet that was queued for execution.

25.10.6.1 Priming transmit endpoints
Priming a transmit endpoint will cause the device controller to fetch the device transfer
descriptor (dTD) for the transaction pointed to by the device queue head (dQH). After the
dTD is fetched, it will be stored in the dQH until the device controller completes the
transfer described by the dTD. Storing the dTD in the dQH allows the device controller to

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fetch the operating context needed to handle a request from the host without the need to
follow the linked list, starting at the dQH when the host request is received. After the
device has loaded the dTD, the leading data in the packet is stored in a FIFO in the device
controller. This FIFO is split into virtual channels so that the leading data can be stored for
any endpoint up to six endpoints for the LPC43xx USB0.
After a priming request is complete, an endpoint state of primed is indicated in the
ENDPTSTATUS register. For a primed transmit endpoint, the device controller can
respond to an IN request from the host and meet the stringent bus turnaround time of High
Speed USB. Since only the leading data is stored in the device controller FIFO, it is
necessary for the device controller to begin filling in behind leading data after the
transaction starts. The FIFO must be sized to account for the maximum latency that can
be incurred by the system memory bus. On the LPC43xx, 128 x 36 bit dual port memory
FIFOs are used for each IN endpoint.

25.10.6.2 Priming receive endpoints
Priming receive endpoints is identical to priming of transmit endpoints from the point of
view of the DCD. At the device controller the major difference in the operational model is
that there is no data movement of the leading packet data simply because the data is to
be received from the host. Note as part of the architecture, the FIFO for the receive
endpoints is not partitioned into multiple channels like the transmit FIFO. Thus, the size of
the RX FIFO does not scale with the number of endpoints.

25.10.7 Interrupt/bulk endpoint operational model
The behaviors of the device controller for interrupt and bulk endpoints are identical. All
valid IN and OUT transactions to bulk pipes will handshake with a NAK unless the
endpoint had been primed. Once the endpoint has been primed, data delivery will
commence.
A dTD will be retired by the device controller when the packets described in the transfer
descriptor have been completed. Each dTD describes N packets to be transferred
according to the USB Variable Length transfer protocol. The formula and table below
describe how the device controller computes the number and length of the packets to be
sent/received by the USB.The results vary according to the total number of bytes and
maximum packet length (wMaxPacketSize).
With Zero Length Termination (ZLT) = 0
N = INT(Number Of Bytes/wMaxPacketSize) + 1
With Zero Length Termination (ZLT) = 1
N = CEILING(Number Of Bytes/wMaxPacketSize)
Table 511. Variable length transfer protocol example (ZLT = 0)

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Bytes (dTD)

Max Packet Length
(dQH)

N

P1

P2

P3

511

256

2

256

255

-

512

256

3

256

256

0

512

512

2

512

0

-

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Table 512. Variable length transfer protocol example (ZLT = 1)
Bytes (dTD)

Max Packet
N
Length (dQH)

P1

P2

P3

511

256

2

256

255

-

512

256

2

256

256

-

512

512

1

512

-

-

Remark: The MULT field in the dQH must be set to “00” for bulk, interrupt, and control
endpoints.
TX-dTD is complete when all packets described by the dTD were successfully
transmitted.Total bytes in dTD will equal zero when this occurs.
RX-dTD is complete when:

• All packets described in the dTD were successfully received. The Total_bytes field in
the dTD will equal zero when this occurs.

• A short packet (number of bytes < maximum packet length) was received. This is a
successful transfer completion; DCD must check the Total_bytes field in the dTD to
determine the number of bytes that are remaining. From the total bytes remaining in
the dTD, the DCD can compute the actual bytes received.

• A long packet was received (number of bytes > maximum packet size) OR (total bytes
received > total bytes specified). This is an error condition. The device controller will
discard the remaining packet, and set the Buffer Error bit in the dTD. In addition, the
endpoint will be flushed and the USBERR interrupt will become active.
On the successful completion of the packets described by the dTD, the active bit in the
dTD will be cleared and the next pointer will be followed when the Terminate bit is clear.
When the Terminate bit is set, the device controller will flush the endpoint/direction and
cease operations for that endpoint/direction. On the unsuccessful completion of a packet
(see long packet above), the dQH will be left pointing to the dTD that was in error. In order
to recover from this error condition, the DCD must properly reinitialize the dQH by clearing
the active bit and update the nextTD pointer before attempting to re-prime the endpoint.
Remark: All packet level errors such as a missing handshake or CRC error will be retried
automatically by the device controller.
There is no required interaction with the DCD for handling such errors.

25.10.7.1 Interrupt/bulk endpoint bus response matrix
Table 513. Interrupt/bulk endpoint bus response matrix

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Token
type

STALL

Not primed

Primed

Underflow

Overflow

Setup

Ignore

Ignore

Ignore

n/a

n/a

In

STALL

NAK

Transmit

BS error

n/a

Out

STALL

NAK

Receive and NYET/ACK

n/a

NAK

Ping

STALL

NAK

ACK

n/a

n/a

Invalid

Ignore

Ignore

Ignore

Ignore

Ignore

[1]

BS error = Force Bit Stuff Error

[2]

NYET/ACK – NYET unless the Transfer Descriptor has packets remaining according to the USB variable
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length protocol then ACK.
[3]

SYSERR – System error should never occur when the latency FIFOs are correctly sized and the DCD is
responsive.

25.10.8 Control endpoint operational model
25.10.8.1 Setup phase
All requests to a control endpoint begin with a setup phase followed by an optional data
phase and a required status phase. The device controller will always accept the setup
phase unless the setup lockout is engaged.
The setup lockout will engage so that future setup packets are ignored. Lockout of setup
packets ensures that while software is reading the setup packet stored in the queue head,
that data is not written as it is being read potentially causing an invalid setup packet.
In hardware the setup lockout mechanism can be disabled and a new tripwire type
semaphore will ensure that the setup packet payload is extracted from the queue head
without being corrupted by an incoming setup packet. This is the preferred behavior
because ignoring repeated setup packets due to long software interrupt latency would be
a compliance issue.
25.10.8.1.1

Setup packet handling using setup lockout mechanism
After receiving an interrupt and inspecting USBMODE to determine that a setup packet
was received on a particular pipe:
1. Duplicate contents of dQH.SetupBuffer into local software byte array.
2. Write '1' to clear corresponding ENDPTSETUPSTAT bit and thereby disabling Setup
Lockout (i.e. the Setup Lockout activates as soon as a setup packet arrives. By writing
to the ENDPTSETUPSTAT, the device controller will accept new setup packets.).
3. Process setup packet using local software byte array copy and execute
status/handshake phases.
Remark: After receiving a new setup packet the status and/or handshake phases
may still be pending from a previous control sequence. These should be flushed &
deallocated before linking a new status and/or handshake dTD for the most recent
setup packet.
4. Before priming for status/handshake phases ensure that ENDPTSETUPSTAT is ‘0’.
The time from writing a ‘1’ to ENDPTSETUPSTAT and reading back a ‘0’ may vary
according to the type of traffic on the bus up to nearly a 1 ms. However, it is absolutely
necessary to ensure ENDPTSETUPSTAT has transitioned to ‘0’ after step 1 and
before priming for the status/handshake phases.
Remark: To limit the exposure of setup packets to the setup lockout mechanism (if used),
the DCD should designate the priority of responding to setup packets above responding to
other packet completions.

25.10.8.1.2

Setup packet handling using the trip wire mechanism

• Disable Setup Lockout by writing ‘1’ to Setup Lockout Mode (SLOM) in the
USBMODE register (once at initialization). Setup lockout is not necessary when using
the tripwire as described below.

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Remark: Leaving the Setup Lockout Mode As ‘0’ will result in pre-2.3 hardware
behavior.

• After receiving an interrupt and inspecting ENDPTSETUPSTAT to determine that a
setup packet was received on a particular pipe:
a. Write '1' to clear corresponding bit ENDPTSETUPSTAT.
b. Write ‘1’ to Setup Tripwire (SUTW) in USBCMD register.
c. Duplicate contents of dQH.SetupBuffer into local software byte array.
d. Read Setup TripWire (SUTW) in USBCMD register. (if set - continue; if cleared - go
to b).
e. Write '0' to clear Setup Tripwire (SUTW) in USBCMD register.
f. Process setup packet using local software byte array copy and execute
status/handshake phases.
g. Before priming for status/handshake phases ensure that ENDPTSETUPSTAT is
‘0’.

• A poll loop should be used to wait until ENDPTSETUPSTAT transitions to ‘0’ after step
a) above and before priming for the status/handshake phases.

• The time from writing a ‘1’ to ENDPTSETUPSTAT and reading back a ‘0’ is very short
(~1-2 us) so a poll loop in the DCD will not be harmful.
Remark: After receiving a new setup packet the status and/or handshake phases may still
be pending from a previous control sequence. These should be flushed & deallocated
before linking a new status and/or handshake dTD for the most recent setup packet.

25.10.8.2 Data phase
Following the setup phase, the DCD must create a device transfer descriptor for the data
phase (if present) and prime the transfer.
After priming the packet, the DCD must verify that a new setup packet has not been
received by reading the ENDPTSETUPSTAT register immediately.This step verifies that
the prime has completed. A prime completes when the associated bit in the
ENDPTPRIME register is zero and the associated bit in the ENDPTSTATUS register is
one. If a prime fails, i.e. the ENDPTPRIME bit goes to zero and the ENDPTSTATUS bit is
not set, then the prime has failed. This can only be due to improper setup of the dQH, dTD
or a setup arriving during the prime operation. If a new setup packet is indicated after the
ENDPTPRIME bit is cleared, then the transfer descriptor can be freed and the DCD must
reinterpret the setup packet.
Should a setup arrive after the data stage is primed, the device controller will
automatically clear the prime status (ENDPTSTATUS) to enforce data coherency with the
setup packet.
Remark: The MULT field in the dQH must be set to “00” for bulk, interrupt, and control
endpoints.
Remark: Error handling of data phase packets is the same as bulk packets described
previously.

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25.10.8.3 Status phase
Similar to the data phase, the DCD must create a transfer descriptor (with byte length
equal zero) and prime the endpoint for the status phase. The DCD must also perform the
same checks of the ENDPTSETUPSTAT as described above in the data phase.
Remark: The MULT field in the dQH must be set to “00” for bulk, interrupt, and control
endpoints.
Remark: Error handling of status phase packets is the same as bulk packets described
previously.

25.10.8.4 Control endpoint bus response matrix
Shown in the following table is the device controller response to packets on a control
endpoint according to the device controller state.
Table 514. Control endpoint bus response matrix
Token
type

Endpoint state

Setup
lockout

STALL

Not primed Primed

Underflow

Overflow

Setup

ACK

ACK

ACK

n/a

SYSERR

-

In

STALL

NAK

Transmit

BS error

n/a

n/a

Out

STALL

NAK

Receive and
NYET/ACK

n/a

NAK

n/a

Ping

STALL

NAK

ACK

n/a

n/a

n/a

Invalid

Ignore

Ignore

Ignore

Ignore

Ignore

ignore

[1]

BS error = Force Bit Stuff Error

[2]

NYET/ACK – NYET unless the Transfer Descriptor has packets remaining according to the USB variable
length protocol then ACK.

[3]

SYSERR – System error should never occur when the latency FIFOs are correctly sized and the DCD is
responsive.

25.10.9 Isochronous endpoint operational model
Isochronous endpoints are used for real-time scheduled delivery of data, and their
operational model is significantly different from the host throttled Bulk, Interrupt, and
Control data pipes. Real time delivery by the device controller is accomplished by the
following:

• Exactly MULT Packets per (micro) Frame are transmitted/received. Note: MULT is a
two-bit field in the device Queue Head. The variable length packet protocol is not
used on isochronous endpoints.

• NAK responses are not used. Instead, zero length packets are sent in response to an
IN request to an unprimed endpoint. For unprimed RX endpoints, the response to an
OUT transaction is to ignore the packet within the device controller.

• Prime requests always schedule the transfer described in the dTD for the next (micro)
frame. If the ISO-dTD is still active after that frame, then the ISO-dTD will be held
ready until executed or canceled by the DCD.

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An EHCI compatible host controller uses the periodic frame list to schedule data
exchanges to Isochronous endpoints. The operational model for device mode does not
use such a data structure. Instead, the same dTD used for Control/Bulk/Interrupt
endpoints is also used for isochronous endpoints. The difference is in the handling of the
dTD.
The first difference between bulk and ISO-endpoints is that priming an ISO-endpoint is a
delayed operation such that an endpoint will become primed only after a SOF is received.
After the DCD writes the prime bit, the prime bit will be cleared as usual to indicate to
software that the device controller completed priming the dTD for transfer. Internal to the
design, the device controller hardware masks that prime start until the next frame
boundary. This behavior is hidden from the DCD but occurs so that the device controller
can match the dTD to a specific (micro) frame.
Another difference with isochronous endpoints is that the transaction must wholly
complete in a (micro) frame. Once an ISO transaction is started in a (micro) frame it will
retire the corresponding dTD when MULT transactions occur or the device controller finds
a fulfillment condition. The transaction error bit set in the status field indicates a fulfillment
error condition. When a fulfillment error occurs the device controller will force-retire the
ISO-dTD and move to the next ISO-dTD.
It is important to note that fulfillment errors are only caused due to partially completed
packets. If no activity occurs to a primed ISO-dTD, the transaction will stay primed
indefinitely. This means it is up to software discard transmit ISO-dTDs that pile up from a
failure of the host to move the data. Finally, the last difference with ISO packets is in the
data level error handling. When a CRC error occurs on a received packet, the packet is
not retried similar to bulk and control endpoints. Instead, the CRC is noted by setting the
Transaction Error bit and the data is stored as usual for the application software to sort
out.
TX packet retired

• MULT counter reaches zero.
• Fulfillment Error [Transaction Error bit is set].
• # Packets Occurred > 0 AND # Packets Occurred < MULT.
Remark: For TX-ISO, MULT Counter can be loaded with a lesser value in the dTD
Multiplier Override field. If the Multiplier Override is zero, the MULT Counter is initialized to
the Multiplier in the QH.
RX packet retired

• MULT counter reaches zero.
• Non-MDATA Data PID is received.
Remark: Exit criteria only valid in hardware version 2.3 or later. Previous to hardware
version 2.3, any PID sequence that did not match the MULT field exactly would be
flagged as a transaction error due to PID mismatch or fulfillment error.

• Overflow Error:
– Packet received is > maximum packet length. [Buffer Error bit is set].
– Packet received exceeds total bytes allocated in dTD. [Buffer Error bit is set].

• Fulfillment error [Transaction Error bit is set]:
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# Packets Occurred > 0 AND # Packets Occurred < MULT.

• CRC Error [Transaction Error bit is set]
Remark: For ISO, when a dTD is retired, the next dTD is primed for the next frame. For
continuous (micro) frame to (micro) frame operation the DCD should ensure that the dTD
linked-list is out ahead of the device controller by at least two (micro) frames.

25.10.9.1 Isochronous pipe synchronization
When it is necessary to synchronize an isochronous data pipe to the host, the (micro)
frame number (FRINDEX register) can be used as a marker. To cause a packet transfer to
occur at a specific (micro) frame number [N], the DCD should interrupt on SOF during
frame N-1. When the FRINDEX = N -1, the DCD must write the prime bit. The device
controller will prime the isochronous endpoint in (micro) frame N–1 so that the device
controller will execute delivery during (micro) frame N.
Remark: Priming an endpoint towards the end of (micro) frame N-1 will not guarantee
delivery in (micro) frame N. The delivery may actually occur in (micro) frame N+1 if the
device controller does not have enough time to complete the prime before the SOF for
packet N is received.

25.10.9.2 Isochronous endpoint bus response matrix
Table 515. Isochronous endpoint bus response matrix
Token
type

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STALL

Not primed

Primed

Underflow

Setup

STALL

STALL

STALL

n/a

n/a

In

NULL
packet

NULL packet

Transmit

BS error

n/a

Out

Ignore

Ignore

Receive

n/a

Drop packet

Ping

Ignore

Ignore

Ignore

Ignore

Ignore

Invalid

Ignore

Ignore

Ignore

Ignore

Ignore

[1]

BS error = Force Bit Stuff Error

[2]

NULL packet = Zero length packet.

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25.10.10 Managing queue heads

Endpoint Queue Heads
dQH

Endpoint Transfer
Descriptors dTD
transfer buffer
pointer

Endpoint dQH0 - Out

dTD

Endpoint dQH0 - In

dTD

Endpoint dQH1 - Out

dTD

transfer buffer
pointer

TRANSFER
BUFFER

TRANSFER
BUFFER

dTD

transfer buffer
pointer

transfer buffer
pointer

TRANSFER
BUFFER

TRANSFER
BUFFER

ENDPOINTLISTADDR

Fig 71. Endpoint queue head diagram

The device queue head (dQH) points to the linked list of transfer tasks, each depicted by
the device Transfer Descriptor (dTD). An area of memory pointed to by
ENDPOINTLISTADDR contains a group of all dQH’s in a sequential list as shown in
Figure 71. The even elements in the list of dQH’s are used for receive endpoints (OUT)
and the odd elements are used for transmit endpoints (IN). Device transfer descriptors are
linked head to tail starting at the queue head and ending at a terminate bit. Once the dTD
has been retired, it will no longer be part of the linked list from the queue head. Therefore,
software is required to track all transfer descriptors since pointers will no longer exist
within the queue head once the dTD is retired (see Section 25.10.11.1).
In addition to the current and next pointers and the dTD overlay examined in section
Section 25.10.6, the dQH also contains the following parameters for the associated
endpoint: Multiplier, Maximum Packet Length, Interrupt On Setup. The complete
initialization of the dQH including these fields is demonstrated in the next section.

25.10.10.1 Queue head initialization
Initialize one pair of device queue heads for the control endpoint. For each non-control
endpoint direction used, initialize one queue head.To initialize a device queue head, follow
these steps:

• Write the wMaxPacketSize field as required by the USB Chapter 9 or application
specific protocol.

• Write the multiplier field to 0 for control, bulk, and interrupt endpoints. For ISO
endpoints, set the multiplier to 1,2, or 3 as required by the bandwidth and in
accordance with the USB Chapter 9 protocol. Note: In FS mode, the multiplier field
can only be 1 for ISO endpoints.

• Write the next dTD Terminate bit field to “1”.
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• Write the Active bit in the status field to “0”.
• Write the Halt bit in the status field to “0”.
Remark: The DCD must only modify dQH if the associated endpoint is not primed and
there are no outstanding dTD’s.

25.10.10.2 Operational model for setup transfers
As discussed in section Control Endpoint Operational Model (Section 25.10.8), a setup
transfer requires special treatment by the DCD. A setup transfer does not use a dTD but
instead stores the incoming data from a setup packet in an 8-byte buffer within the dQH.
Upon receiving notification of the setup packet, the DCD should handle the setup transfer
as demonstrated here:
1. Copy the setup buffer contents from dQH - RX to software buffer.
2. Acknowledge setup backup by writing a “1” to the corresponding bit in
ENDPTSETUPSTAT.
Remark: The acknowledge must occur before continuing to process the setup packet.
Remark: After the acknowledge has occurred, the DCD must not attempt to access
the setup buffer in the dQH – RX. Only the local software copy should be examined.
3. Check for pending data or status dTD’s from previous control transfers and flush if any
exist as discussed in section Flushing/De-priming an Endpoint.
Remark: It is possible for the device controller to receive setup packets before
previous control transfers complete. Existing control packets in progress must be
flushed and the new control packet completed.
4. Decode setup packet and prepare data phase [optional] and status phase transfer as
require by the USB Specification Chapter 9 or application specific protocol.

25.10.11 Managing transfers with transfer descriptors
25.10.11.1 Software link pointers
It is necessary for the DCD software to maintain head and tail pointers to the linked list of
dTDs for each respective queue head. This is necessary because the dQH only maintains
pointers to the current working dTD and the next dTD to be executed. The operations
described in following sections for managing dTD will assume the DCD can reference the
head and tail of the dTD linked list.
Remark: To conserve memory, the reserved fields at the end of the dQH can be used to
store the Head & Tail pointers but it still remains the responsibility of the DCD to maintain
the pointers.

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Head Pointer

Tail Pointer

current
Endpoint
QH

next

completed dTDs

queued dTDs

Fig 72. Software link pointers

25.10.11.2 Building a transfer descriptor
Before a transfer can be executed from the linked list, a dTD must be built to describe the
transfer. Use the following procedure for building dTDs:
Allocate 8-DWord dTD block of memory aligned to 8-DWord boundaries. Example: bit
address 4:0 would be equal to “00000”.
Write the following fields:
1. Initialize first 7 DWords to 0.
2. Set the terminate bit to “1”.
3. Fill in total bytes with transfer size.
4. Set the interrupt on complete if desired.
5. Initialize the status field with the active bit set to “1” and all remaining status bits set to
“0”.
6. Fill in buffer pointer page 0 and the current offset to point to the start of the data buffer.
7. Initialize buffer pointer page 1 through page 4 to be one greater than each of the
previous buffer pointers.

25.10.11.3 Executing a transfer descriptor
To safely add a dTD, the DCD must follow this procedure which will handle the event
where the device controller reaches the end of the dTD list at the same time a new dTD is
being added to the end of the list.
Determine whether the linked list is empty: Check DCD driver to see if pipe is empty
(internal representation of linked list should indicate if any packets are outstanding).
Linked list is empty
1. Write dQH next pointer AND dQH terminate bit to 0 as a single DWord operation.
2. Clear active and halt bits in dQH (in case set from a previous error).
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3. Prime endpoint by writing ‘1’ to correct bit position in ENDPTPRIME.
Linked list is not empty
1. Add dTD to end of the linked list.
2. Read correct prime bit in ENDPTPRIME – if ‘1’ DONE.
3. Set ATDTW bit in USBCMD register to ‘1’.
4. Read correct status bit in ENDPTSTAT. (Store in temp variable for later).
5. Read ATDTW bit in USBCMD register.
– If ‘0’ go to step 3.
– If ‘1’ continue to step 6.
6. Write ATDTW bit in USBCMD register to ‘0’.
7. If status bit read in step 4 (ENDPSTAT reg) indicates endpoint priming is DONE
(corresponding ERBRx or ETBRx is one): DONE.
8. If status bit read in step 4 is 0 then go to Linked list is empty: Step 1.

25.10.11.4 Transfer completion
After a dTD has been initialized and the associated endpoint primed the device controller
will execute the transfer upon the host-initiated request. The DCD will be notified with a
USB interrupt if the Interrupt On Complete bit was set or alternately, the DCD can poll the
endpoint complete register to find when the dTD had been executed. After a dTD has
been executed, DCD can check the status bits to determine success or failure.
Remark: Multiple dTD can be completed in a single endpoint complete notification. After
clearing the notification, DCD must search the dTD linked list and retire all dTDs that have
finished (Active bit cleared).
By reading the status fields of the completed dTDs, the DCD can determine if the
transfers completed successfully. Success is determined with the following combination of
status bits:
Active = 0
Halted = 0
Transaction Error = 0
Data Buffer Error = 0
Should any combination other than the one shown above exist, the DCD must take proper
action. Transfer failure mechanisms are indicated in the Device Error Matrix (see
Table 516).
In addition to checking the status bit, the DCD must read the Total_bytes field to determine
the actual bytes transferred. When a transfer is complete, the Total_bytes field is
decremented by the actual bytes transferred. For Transmit packets, a packet is only
complete after the Total_bytes field reaches zero, but for receive packets, the host may
send fewer bytes in the transfer according the USB variable length packet protocol.

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25.10.11.5 Flushing an endpoint
It is necessary for the DCD to flush one or more endpoints on a USB device reset or
during a broken control transfer. There may also be application specific requirements to
stop transfers in progress. The following procedure can be used by the DCD to stop a
transfer in progress:
1. Write a ‘1’ to the corresponding bit(s) in ENDPTFLUSH.
2. Wait until all bits in ENDPTFLUSH are ‘0’.
Remark: Software note: This operation may take a large amount of time depending
on the USB bus activity. It is not desirable to have this wait loop within an interrupt
service routine.
3. Read the ENDPTSTAT register to ensure that for all endpoints commanded to be
flushed the corresponding bits are now ‘0’. If the corresponding bits are ‘1’ after step
#2 has finished, then the flush failed as described in the following:
In very rare cases, a packet is in progress to the particular endpoint when
commanded flush using ENDPTFLUSH. A safeguard is in place to refuse the flush to
ensure that the packet in progress completes successfully. The DCD may need to
repeatedly flush any endpoints that fail to flush by repeating steps 1-3 until each
endpoint is successfully flushed.

25.10.11.6 Device error matrix
Table 516 summarizes packet errors that are not automatically handled by the device
controller.
The following errors can occur:
Overflow: Number of bytes received exceeded max. packet size or total buffer length.
This error will also set the Halt bit in the dQH, and if there are dTDs remaining in the
linked list for the endpoint, then those will not be executed.
ISO packet error: CRC Error on received ISO packet. Contents not guaranteed to be
correct.
ISO fulfillment error: Host failed to complete the number of packets defined in the dQH
MULT field within the given (micro) frame. For scheduled data delivery the DCD may
need to readjust the data queue because a fulfillment error will cause the device
controller to cease data transfers on the pipe for one (micro) frame. During the “dead”
(micro) frame, the device controller reports error on the pipe and primes for the following
(micro) frame
Table 516. Device error matrix

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Error

Direction

Packet type

Data buffer error Transaction
bit
error bit

Overflow

Rx

Any

1

0

ISO packet error

Rx

ISO

0

1

ISO fulfillment
error

Both

ISO

0

1

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25.10.12 Servicing interrupts
The interrupt service routine must consider different types of interrupts for high-frequency
and low-frequency, and error operations and specify the priorities accordingly.

25.10.12.1 High-frequency interrupts
High frequency interrupts in particular should be handled in the order below. The most
important of these is listed first because the DCD must acknowledge a setup buffer in the
timeliest manner possible.
Table 517. High-frequency interrupt events
Execution order

Interrupt

1a

Copy contents of setup buffer and acknowledge
USB interrupt:
ENDPTSETUPSTATUS setup packet (as indicated in Section 25.10.10).
[1]
Process setup packet according to USB 2.0 Chapter
9 or application specific protocol.

1b

USB interrupt:
ENDPTCOMPLETE[1]

Handle completion of dTD as indicated in
Section 25.10.10.

2

SOF interrupt

Action as deemed necessary by application. This
interrupt may not have a use in all applications.

[1]

Action

It is likely that multiple interrupts stack up on any call to the Interrupt Service Routine AND during
the Interrupt Service Routine.

25.10.12.2 Low-frequency interrupts
The low frequency events include the following interrupts. These interrupt can be handled
in any order since they don’t occur often in comparison to the high-frequency interrupts.
Table 518. Low-frequency interrupt events
Interrupt

Action

Port change

Change software state information.

Sleep enable (Suspend)

Change software state information. Low power
handling as necessary.

Reset Received

Change software state information. Abort
pending transfers.

25.10.12.3 Error interrupts
Error interrupts will be least frequent and should be placed last in the interrupt service
routine.
Table 519. Error interrupt events

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Interrupt

Action

USB error interrupt

This error is redundant because it combines USB Interrupt and an error
status in the dTD. The DCD will more aptly handle packet-level errors by
checking dTD status field upon receipt of USB Interrupt (w/
ENDPTCOMPLETE).

System error

Unrecoverable error. Immediate Reset of core; free transfers buffers in
progress and restart the DCD.

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25.11 System error
The USB controller is an AHB bus master and any interaction between the USB controller
and the system may experience errors. The type of error may be catastrophic to the USB
controller (such as a Master Abort), making it impossible for the USB controller to continue
in a coherent manner. In the presence of non-catastrophic errors, such as parity errors,
the USB controller could potentially continue operation. The recommended behavior for
these types of errors is to escalate it to a catastrophic error and halt the USB controller. A
system error will result in the following actions:

• The Run/Stop bit in the USBCMD register is set to zero.
• The following bits in the USBSTS register are set:
– System Error bit is set to a one.
– HChalted bit is set to a one.

• If the System Error Enable bit in the USBINTR register is a one, then the USB
controller will issue a hard interrupt.
Remark: After a system error, the software must reset the USB controller via HCReset in
the UBCMD register before re-initializing and re-starting the USB controller.
The most likely cause of system error in device mode is that the pointer fields (next dTD
pointer, buffer pointer) in endpoint transfer descriptors or in endpoint queue head got
corrupted (pointing to inaccessible memory location). The DCD should always provide
pointers to the USB controller accessible memory area. See Figure 12.To avoid corruption
of endpoint transfer descriptors due to race conditions between the DCD and the USB
controller, the DCD must follow the safety procedure described in Section 25.10.11.3
“Executing a transfer descriptor” to add new dTD to the queue. When creating new queue
heads, the DCD must ensure that the EP is disabled or the queue is empty. If the queue is
not empty, the DCD should flush the endpoint first before altering the queue head
structure.

25.12 USB power optimization
The USB-HS core is a fully synchronous static design. Applications that transfer more
data or use a greater number of packets to be sent will consume a greater amount of
power.
The USB power consumption can be controlled by disabling the USB clocks and disabling
the High-speed PHY (see Section 25.2).
A device may go into the Suspended state either autonomously by disconnecting from the
USB, or in response to USB suspend signaling.

25.12.1 USB power states
The USB provides a mechanism to place segments of the USB or the entire USB into a
low-power Suspended state. USB devices are required to respond to a 3ms lack of activity
on the USB bus by going into a Suspended state. In the USB-HS core software is notified
of the suspend condition via the transition of the SUSP bit in the PORTSC1 register.
Optionally an interrupt can be generated which is controlled by the port change Detect
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Enable bit in the USBINTR control register. Software then has 7 ms to transition a bus
powered device into the Suspended state. In the Suspended state, a USB device has a
maximum USB bus power budget of 2.5 mA. In general, to achieve that level of power
conservation, most of the device circuits will need to be switched off, or clock at an
extremely low frequency. This can be accomplished by suspending the clock.
The implementation of low power states in the USB-HS core is dependent on the use of
the device role (host or peripheral), whether the device is bus powered, and the selected
clock architecture of the core.
Bus powered peripheral devices are required by the USB specification to support a low
power Suspended state. Self powered peripheral devices and hosts set their own power
management strategies based on their system level requirements.
Before the system clock is suspended or set to a frequency that is below the operational
frequency of the USB-HS core, the core must be moved from the operational state to a
low power state.

25.12.2 Device power states
A bus powered peripheral device must move through the power states as directed by the
host. Optionally autonomously directed low power states may be implemented.

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Host directed

3 ms
idle

Autonomous
operational
Low-power
request
resume
interrupt
received

prepare
for
Suspend

disconnect

SW sets
Suspend bit

SW sets
Suspend bit

user-defined
wakeup

disconnect
Suspend

Suspend

Resume

Lock power states
(clock may be suspended)

user-defined
wakeup

start
Resume

Fig 73. Device power state diagram

In the operational state both the transceiver clock and system clocks are running.
Software can initiate a low power mode autonomously by disconnecting from the host to
go into the disconnect state. Once in this state, the software can set the Suspend bit to
turn off the transceiver clock putting the system into the disconnect-Suspended state.
Since software cannot depend on the presence of a clock to clear the Suspend bit, a
wake-up event must be defined which would clear the suspend bit and allow the
transceiver clock to resume.
The device can also go into suspend mode as a result of a suspend command from the
host. Suspend is signaled on the bus by 3 ms of idle time on the bus. This will generate a
suspend interrupt to the software at which point the software must prepare to go into
suspend then set the suspend bit. Once the Suspend bit is set the transceiver clock may
turn off and the device will be in the suspended state. The device has two ways of getting
out of suspend.
1. If remote wake-up is enabled, a wake-up event could be defined which would clear
the Suspend bit. The software would then initiate the resume by setting the Resume
bit in the port controller then waiting for a port change interrupt indicating that the port
is in an operational state.
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Chapter 25: LPC43xx/LPC43Sxx USB0 Host/Device/OTG controller

2. If the host puts resume signaling on the bus, it will clear the Suspend bit and generate
a port change interrupt when the resume is finished.
Remark: The Suspend interrupt is generated by the USB block whenever it detects that
the bus is idle for more than 3 ms. However, during the enumeration process some hosts
wait longer than 3 ms after issuing reset and before transmitting any tokens on bus.
Hence software should implement a debounce logic for suspend interrupt handling to
detect a true suspend command issued by host.

25.12.3 Host power states

operational
all devices
disconnected

Low-power
request

signal
Suspend

disconnect

wait for
3 ms

SW sets
Suspend bit

user-defined
wakeup

disconnect
Suspend

Suspend

user-defined
wakeup

connect
interrupt
Resume or
Reset

K-state
on bus

Lock power states
(clock may be suspended)

Wait
Resume

Fig 74. Host/OTG power state diagram

From an operational state when a host gets a low power request, it must set the suspend
bit in the port controller. This will put an idle on the bus, block all traffic through the port,
and turn off the transceiver clock. There are two ways for a host controller to get out of the
Suspended state. If it has enabled remote wake-up, a K-state on the bus will turn on the
transceiver clock and generate an interrupt. The software will then have to wait 20 ms for
the resume to complete and the port to go back to an active state. Alternatively an

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Chapter 25: LPC43xx/LPC43Sxx USB0 Host/Device/OTG controller

external event could clear the suspend bit and start the transceiver clock running again.
The software can then initiate a resume by setting the resume bit in the port controller, or
force a reconnect by setting the reset bit in the port controller.
If all devices have disconnected from the host, the host can go into a low power mode by
the software setting the suspend bit. From the disconnect-Suspended state a connect
event can start the transceiver clock and interrupt the software. The software then needs
to set the reset bit to start the connect process.

25.12.4 Susp_CTRL module
The SUSP_CTRL module implements the power management logic of the USB block. It
controls the suspend input of the transceiver. Asserting this suspend signal
(PORTSC1.PHCD bit) will put the transceiver in suspend mode and the 480 MHz clock or
the 60 MHz clock will be switched off.
In suspend mode, the transceiver will raise an output signal indicating that the PLL
generating the 480 MHz clock can be switched off.
For USB0 this signal is connected to event #9 (USB0_L) in the event router (see
Table 82). Software should check for this signal to be HIGH before stopping the USB PLL
and putting the chip in low power mode. Note that the event router block doesn't support a
raw pin status register hence HIGH level detection should be configured for this pin to
detect when to turn the PLL off. Similarly, to detect resume signaling to leave the low
power state, software should configure this pin to detect a LOW-level in the event router.
The SUSP_CTRL module also generates an output signal indicating whether the AHB
clock is needed or not. If not, the AHB clock is allowed to be switched off or reduced in
frequency in order to save power.
For USB0, this signal is used to turn off the AHB clock to USB block.
The core will enter the low power state if:

• Software sets the PORTSC1.PHCD bit.
When operating in host mode, the core will leave the low power state on one of the
following conditions:

•
•
•
•
•
•
•

software clears the PORTSC1.PHCD bit
a device is connected and the PORTSC1.WKCN bit is set
a device is disconnected an the PORTSC1.WKDC bit is set
an over-current condition occurs and the PORTSC1.WKOC bit is set
a remote wake-up from the attached device occurs (when USB bus was in suspend)
a change on vbusvalid occurs (= VBUS threshold at 4.4 V is crossed)
a change on bvalid occurs (=VBUS threshold at 4.0 V is crossed).

When operating in device mode, the core will leave the low power state on one of the
following conditions:

• software clears the PORTSC1.PHCD bit.
• a change on the USB data lines (dp/dm) occurs.
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Chapter 25: LPC43xx/LPC43Sxx USB0 Host/Device/OTG controller

• a change on vbusvalid occurs (= VBUS threshold at 4.4 V is crossed).
• a change on bvalid occurs (= VBUS threshold at 4.0 V is crossed).
The vbusvalid and bvalid signals coming from the transceiver are not filtered in the
SUSP_CTRL module. Any change on those signals will cause a wake-up event. Hence
for USB0, it is recommended that the OTG_DISCHARGE resistor be enabled, by setting
OTGSC.VD bit, before entering low power mode.

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Chapter 26: LPC43xx/LPC43Sxx USB1 Host/Device controller
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26.1 How to read this chapter
The USB1 Host/Device controller is available on parts LPC436x/LPC43S6x,
LPC435x/LPC43S5x, and LPC433x/LPC43S3x.
USB frame length adjustment is available for parts with on-chip flash only.

26.2 Basic configuration
The USB1 controller is configured as follows:

• See Table 520 for clocking and power control.
• The USB1 is reset by a USB1_RST (reset # 18).
• The USB1 interrupt is connected to interrupt slot # 9 in the NVIC. The USB
AHB_NEED_CLK signal is connected to slot # 10 in the event router. (See
Section 26.7.1).

• In the SFSUSB register, the USB_ESEA bit must be set to 1 for the USB1 to operate
(see Table 194).

• The registers for frame length adjustment in USB host mode are located in the CREG
block (see Table 112; parts with on-chip flash only).
Table 520. USB1 clocking and power control
Base clock

Branch clock

USB1 clock

BASE_USB1_CLK CLK_USB1

USB1 register
interface clock

BASE_M4_CLK

Operating Notes
frequency
60 MHz

Uses PLL1. CLK_USB1 must
be 60 MHz when the USB1 is
operated in low-speed and
full-speed modes. In
high-speed mode, the clock
is provided by the ULPI PHY.

CLK_M4_USB1 up to
204 MHz

26.2.1 Full-speed mode without external PHY
In Full-speed mode, use CLK_USB1 to generate a clock for the USB1 interface.

26.2.2 High-speed mode with ULPI interface
In High-speed mode, the external PHY generates the clock for the USB1 interface, and
the USB1_ULPI_CLK must be enabled on pins PC_0 or P8_8 through their respective pin
configuration registers in the system configuration block. The USB1 branch clock
CLK_USB1 must be disabled.

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Chapter 26: LPC43xx/LPC43Sxx USB1 Host/Device controller

26.3 Features
• Supports all high-speed USB-compliant peripherals if connected to external ULPI
PHY.

•
•
•
•
•

Supports all full-speed USB-compliant peripherals.
Complies with Universal Serial Bus specification 2.0.
Complies with Enhanced Host Controller Interface Specification.
Supports auto USB 2.0 mode discovery.
Supports three logical endpoints plus one control endpoint for a total of 8 physical
endpoints.

• This module has its own, integrated DMA engine.
• Support for frame length adjustment to correlate the SOF signal with an external clock
(see Section 25.7.7.1).

26.4 General description
The USB1 controller provides plug-and-play connection of peripheral devices to a host
with three different data speeds: High-Speed with a data rate of 480 Mbps (with external
PHY only), Full-Speed with a data rate of 12 Mbps, Low-Speed with a data rate of 1.5
Mbps. Many portable devices can benefit from the ability to communicate to each other
over the USB interface without intervention of a host PC.
Support of the High-Speed data rate requires an external USB HS OTG PHY that
connects to the USB controller via the ULPI interface. Full-Speed or Low-Speed is
supported through the on-chip Full-speed PHY.

LPC43xx
SYSTEM
MEMORY

ARM Cortex-M4

AHB

master

slave
ULPI_D[7:0]

TX-BUFFER
(DUAL-PORT RAM)

ULPI_STP
USB 2.0

RX-BUFFER
(DUAL-PORT RAM)

ULPI

ULPI_CLK
ULPI_DIR
ULPI_NXT

EXTERNAL
HIGH-SPEED
ULPI
PHY

USB1_VBUS
USB1_DP
USB1_DM
GROUND

to
PC/
Mobile/
CE

Fig 75. USB1 block diagram with ULPI

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Chapter 26: LPC43xx/LPC43Sxx USB1 Host/Device controller

LPC43xx
SYSTEM
MEMORY

ARM Cortex-M4

AHB

master

slave

TX-BUFFER
(DUAL-PORT RAM)
USB 2.0

INTERNAL
FULL-SPEED
PHY

RX-BUFFER
(DUAL-PORT RAM)

USB1_VBUS
USB1_DP
USB1_DM
GROUND

to
PC/
Mobile/
CE

Fig 76. USB1 block diagram with internal full-speed PHY

26.5 Pin description
Table 521. USB1 pin description
Pin function

Direction

Description

USB1_DP

I/O

USB1 bidirectional D+ line. The D+ line has an internal 1.5 k pull-up. This pull-up is
enabled when software sets the RS bit (Bit 0) in the USBCMD register. The USB1
controller checks whether the USB1_VBUS pin is pulled HIGH (there is no voltage
monitoring). For applications which use the USB1_VBUS pin as GPIO, software can
monitor VBUS through bit 5 in SFSUSB register (0x4008 6C80).
Add an external series resistor of 33  +/- 2 %.

USB1_DM

I/O

USB1_VBUS

I

USB1 bidirectional D line. The D- line has an internal 1.5 k pull-up. This pull-up is
enabled when software sets the RS bit (Bit 0) in the USBCMD register. The USB1
controller checks whether the USB1_VBUS pin is pulled HIGH (there is no voltage
monitoring). For applications which use the USB1_VBUS pin as GPIO, software can
monitor VBUS through bit 5 in SFSUSB register (0x4008 6C80).
Add an external series resistor of 33  +/- 2 %.
VBUS pin (power on USB cable). If the USB1_VBUS function is not connected on
pin P2_5, use the USB_VBUS bit in the SFSUSB register Table 194 to indicate the
VBUS state to the USB1 controller.
Remark: This input is only 5 V tolerant when VDDIO is present.

USB1_PPWR

O

VBUS drive signal (towards external charge pump or power management unit);
indicates that VBUS must be driven (active HIGH).
Add a pull-down resistor to disable the power switch at reset. This signal has
opposite polarity compared to the USB_PPWR used on other NXP LPC parts.

USB1_IND0

O

Port indicator LED control output 0.

USB1_IND1

O

Port indicator LED control output 1.

USB1_PWR_FAULT

I

Port power fault signal indicating over-current condition; this signal monitors
over-current on the USB bus (external circuitry required to detect over-current
condition).

I/O

ULPI link 8-bit bidirectional data bus timed on the rising clock edge.

ULPI pins
ULPI_DATA[7:0]
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Chapter 26: LPC43xx/LPC43Sxx USB1 Host/Device controller

Table 521. USB1 pin description
Pin function

Direction

Description

ULPI_STP

O

ULPI link STP signal. Asserted to end or interrupt transfers to the PHY.

ULPI_NXT

I

ULPI link NXT signal. Data flow control signal from the PHY.

ULPI_DIR

I

ULPI link DIR signal. Controls the DATA bus direction.

ULPI_CLK

I

ULPI link CLK signal. 60 MHz clock generated by the PHY.

Remark: For requirements when connecting the USB1_VBUS signal to a USB powered
device-only product or an OTG product, see Section 25.5.1

26.6 Register description
Remark: For Full-speed operation with on-chip Full-speed PHY, the pads of the PHY
need to be configured. For configuration of these pads see Table 194.
Remark: For operations with an external PHY connected through the ULPI interface the
interface needs to be selected in the PTS bits of the PORTSC1 register (Section 26.6.15).
Table 522. Register access abbreviations
Abbreviation

Description

R/W

Read/Write

R/WC

Read/Write one to Clear

R/WO

Read/Write Once

RO

Read Only

WO

Write Only

R/WS

Read/Write one to Set

Table 523. Register overview: USB1 host/device controller (register base address 0x4000 7000)
Name

Access Address
offset

Description

-

-

0x000 0x0FF

Reserved

Reset value

Reference

0x0001 0040

Table 524

Device/host capability registers
CAPLENGTH

RO

0x100

Capability register length

HCSPARAMS

RO

0x104

Host controller structural parameters

0x0001 0011

Table 525

HCCPARAMS

RO

0x108

Host controller capability parameters

0x0000 0005

Table 526

DCIVERSION

RO

0x120

Device interface version number

0x0000 0001

Table 527

DCCPARAMS

RO

0x124

Device controller capability parameters 0x0000 0184

Table 528

-

-

0x128 0x13C

Reserved

-

-

0x140

USB command (device mode)

0x0004 0000

Table 529

Device/host operational registers
USBCMD_D

R/W

USBCMD_H

R/W

0x140

USB command (host mode)

0x0004 00B0

Table 530

USBSTS_D

R/W

0x144

USB status (device mode)

0x0000 0000

Table 532

USBSTS_H

R/W

0x144

USB status (host mode)

0x0000 1000

Table 533

USBINTR_D

R/W

0x148

USB interrupt enable (device mode)

0x0000 0000

Table 534

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Chapter 26: LPC43xx/LPC43Sxx USB1 Host/Device controller

Table 523. Register overview: USB1 host/device controller (register base address 0x4000 7000) …continued
Name

Access Address
offset

Description

Reset value

Reference

USBINTR_H

R/W

USB interrupt enable (host mode)

0x0000 0000

Table 535

0x148

FRINDEX_D

RO

0x14C

USB frame index (device mode)

0x0000 0000

Table 536

FRINDEX_H

R/W

0x14C

USB frame index (host mode)

0x0000 0000

Table 537

-

-

0x150

Reserved

DEVICEADDR

R/W

0x154

USB device address

PERIODICLISTBASE

R/W

0x154

ENDPOINTLISTADDR

R/W

0x158

ASYNCLISTADDR

R/W

TTCTRL

0x0000 0000

Table 539

Frame list base address

0x0000 0000

Table 540

Address of endpoint list in memory

0x0000 0000

Table 541

0x158

Asynchronous list address

0x0000 0000

Table 542

R/W

0x15C

Asynchronous buffer status for
embedded TT (host mode)

0x0000 0000

Table 543

BURSTSIZE

R/W

0x160

Programmable burst size

0x0000 0000

Table 544

TXFILLTUNING

R/W

0x164

Host transmit pre-buffer packet tuning
(host mode)

0x0000 0000

Table 545

-

-

0x168 0x16C

Reserved

-

-

ULPIVIEWPORT

R/W

0x170

ULPI viewport

0x0000 0000

Table 546

BINTERVAL

R/W

0x174

Length of virtual frame

0x0000 0000

Table 547

ENDPTNAK

R/W

0x178

Endpoint NAK (device mode)

0x0000 0000

Table 548

ENDPTNAKEN

R/W

0x17C

Endpoint NAK Enable (device mode)

0x0000 0000

Table 549

-

-

0x180

-

-

-

PORTSC1_D

R/W

0x184

Port 1 status/control (device mode)

0x0000 0000

Table 550

PORTSC1_H

R/W

0x184

Port 1 status/control (host mode)

0x0000 0000

Table 551

-

-

0x188 0x1A0

-

-

-

-

-

0x1A4

-

-

-

USBMODE_D

R/W

0x1A8

USB mode (device mode)

0x0000 0000

Table 553

USBMODE_H

R/W

0x1A8

USB mode (host mode)

0x0000 0000

Table 554

ENDPTSETUPSTAT

R/W

0x1AC

Endpoint setup status

0x0000 0000

Table 555

ENDPTPRIME

R/W

0x1B0

Endpoint initialization

0x0000 0000

Table 556

ENDPTFLUSH

R/W

0x1B4

Endpoint de-initialization

0x0000 0000

Table 557

ENDPTSTAT

RO

0x1B8

Endpoint status

0x0000 0000

Table 558

ENDPTCOMPLETE

R/W

0x1BC

Endpoint complete

0x0000 0000

Table 559

ENDPTCTRL0

R/W

0x1C0

Endpoint control 0

0x0000 0000

Table 560

ENDPTCTRL1

R/W

0x1C4

Endpoint control 1

0x0000 0000

Table 561

ENDPTCTRL2

R/W

0x1C8

Endpoint control 2

0x0000 0000

Table 561

ENDPTCTRL3

R/W

0x1CC

Endpoint control 3

0x0000 0000

Table 561

Device endpoint registers

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Chapter 26: LPC43xx/LPC43Sxx USB1 Host/Device controller

26.6.1 Device/host capability registers
Table 524. CAPLENGTH register (CAPLENGTH - address 0x4000 7100) bit description
Bit

Symbol

Description

Reset value Access

7:0

CAPLENGTH

Indicates offset to add to the register base
address at the beginning of the Operational
Register

0x40

RO

23:8

HCIVERSION

BCD encoding of the EHCI revision number
supported by this host controller.

0x100

RO

31:24

-

These bits are reserved and should be set to zero.

-

Table 525. HCSPARAMS register (HCSPARAMS - address 0x4000 7104) bit description

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Bit

Symbol

Description

3:0

N_PORTS

Number of downstream ports. This field
0x1
specifies the number of physical
downstream ports implemented on this host
controller.

RO

4

PPC

Port Power Control. This field indicates
whether the host controller implementation
includes port power control.

0x1

RO

7:5

-

These bits are reserved and should be set
to zero.

-

-

11:8

N_PCC

Number of Ports per Companion Controller. 0x0
This field indicates the number of ports
supported per internal Companion
Controller.

RO

15:12

N_CC

Number of Companion Controller. This field 0x0
indicates the number of companion
controllers associated with this USB2.0 host
controller.

RO

16

PI

Port indicators. This bit indicates whether
the ports support port indicator control.

0x1

RO

19:17

-

These bits are reserved and should be set
to zero.

-

-

23:20

N_PTT

Number of Ports per Transaction Translator. 0x0
This field indicates the number of ports
assigned to each transaction translator
within the USB2.0 host controller.

RO

27:24

N_TT

Number of Transaction Translators. This
field indicates the number of embedded
transaction translators associated with the
USB2.0 host controller.

0x0

RO

31:28

-

These bits are reserved and should be set
to zero.

-

-

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Chapter 26: LPC43xx/LPC43Sxx USB1 Host/Device controller

Table 526. HCCPARAMS register (HCCPARAMS - address 0x4000 7108) bit description
Bit

Symbol

Description

Reset value Access

0

ADC

64-bit Addressing Capability. If zero, no 64-bit
addressing capability is supported.

0

RO

1

PFL

Programmable Frame List Flag. If set to one, then
the system software can specify and use a smaller
frame list and configure the host controller via the
USBCMD register Frame List Size field. The frame
list must always be aligned on a 4K-boundary. This
requirement ensures that the frame list is always
physically contiguous.

1

RO

2

ASP

Asynchronous Schedule Park Capability. If this bit is 1
set to a one, then the host controller supports the
park feature for high-speed queue heads in the
Asynchronous Schedule.The feature can be
disabled or enabled and set to a specific level by
using the Asynchronous Schedule Park Mode
Enable and Asynchronous Schedule Park Mode
Count fields in the USBCMD register.

RO

7:4

IST

Isochronous Scheduling Threshold. This field
indicates, relative to the current position of the
executing host controller, where software can
reliably update the isochronous schedule.

0

RO

15:8

EECP

EHCI Extended Capabilities Pointer. This optional
field indicates the existence of a capabilities list.

0

RO

31:16

-

These bits are reserved and should be set to zero.

-

-

Table 527. DCIVERSION register (DCIVERSION - address 0x4000 7120) bit description
Bit

Symbol

Description

15:0

DCIVERSION The device controller interface conforms to the 0x1
two-byte BCD encoding of the interface version
number contained in this register.

RO

31:16

-

-

These bits are reserved and should be set to
zero.

Reset value Access

-

Table 528. DCCPARAMS (address 0x4000 7124)
Bit

Symbol

Description

Reset value Access

4:0

DEN

Device Endpoint Number.

0x4

RO

6:5

-

These bits are reserved and should be set to zero.

-

-

7

DC

Device Capable.

0x1

RO

8

HC

Host Capable.

0x1

RO

31:9

-

These bits are reserved and should be set to zero.

-

-

26.6.2 USB Command register (USBCMD)
The host/device controller executes the command indicated in this register.

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Chapter 26: LPC43xx/LPC43Sxx USB1 Host/Device controller

26.6.2.1 Device mode
Table 529. USB Command register in device mode (USBCMD_D - address 0x4000 7140) bit description
Bit

Symbol

0

RS

1

Value

Description

Reset Access
value

Run/Stop

0

R/W

0

R/W

0

Writing a 0 to this bit will cause a detach event.

1

Writing a one to this bit will cause the device controller to enable a pull-up
on USB_DP and initiate an attach event. This control bit is not directly
connected to the pull-up enable, as the pull-up will become disabled upon
transitioning into high-speed mode. Software should use this bit to prevent
an attach event before the device controller has been properly initialized.

RST

Controller reset.
Software uses this bit to reset the controller. This bit is set to zero by the
Host/Device Controller when the reset process is complete. Software
cannot terminate the reset process early by writing a zero to this register.
0

Set to 0 by hardware when the reset process is complete.

1

When software writes a one to this bit, the Device Controller resets its
internal pipelines, timers, counters, state machines etc. to their initial
values. Writing a one to this bit when the device is in the attached state is
not recommended, since the effect on an attached host is undefined. In
order to ensure that the device is not in an attached state before initiating a
device controller reset, all primed endpoints should be flushed and the
USBCMD Run/Stop bit should be set to 0.

3:2

-

Not used in device mode.

0

-

4

-

Not used in device mode.

0

-

5

-

Not used in device mode.

0

-

6

-

Not used in device mode. Writing a one to this bit when the device mode is selected, will have undefined results.

-

7

-

-

Reserved. These bits should be set to 0.

-

-

9:8

-

-

Not used in Device mode.

-

-

10

-

Reserved.These bits should be set to 0.

0

11

-

12

-

Reserved.These bits should be set to 0.

0

-

13

SUTW

Setup trip wire

0

R/W

0

R/W

-

Not used in Device mode.

-

During handling a setup packet, this bit is used as a semaphore to ensure
that the setup data payload of 8 bytes is extracted from a QH by the DCD
without being corrupted. If the setup lockout mode is off (see USBMODE
register) then there exists a hazard when new setup data arrives while the
DCD is copying the setup data payload from the QH for a previous setup
packet. This bit is set and cleared by software and will be cleared by
hardware when a hazard exists. (See Section 25.10).
14

ATDTW

Add dTD trip wire
This bit is used as a semaphore to ensure the to proper addition of a new
dTD to an active (primed) endpoint’s linked list. This bit is set and cleared
by software during the process of adding a new dTD. See also
Section 25.10.
This bit shall also be cleared by hardware when its state machine is hazard
region for which adding a dTD to a primed endpoint may go unrecognized.

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Chapter 26: LPC43xx/LPC43Sxx USB1 Host/Device controller

Table 529. USB Command register in device mode (USBCMD_D - address 0x4000 7140) bit description …continued
Bit

Symbol

15
23:16

Value

Description

Reset Access
value

FS2

Not used in device mode.

-

-

ITC

Interrupt threshold control.

0x8

R/W

The system software uses this field to set the maximum rate at which the
host/device controller will issue interrupts. ITC contains the maximum
interrupt interval measured in micro-frames. Valid values are shown below.
All other values are reserved.
0x0 = Immediate (no threshold)
0x1 = 1 micro frame.
0x2 = 2 micro frames.
0x8 = 8 micro frames.
0x10 = 16 micro frames.
0x20 = 32 micro frames.
0x40 = 64 micro frames.
31:24

-

Reserved

0

26.6.2.2 Host mode
Table 530. USB Command register in host mode (USBCMD_H - address 0x4000 7140) bit description
Bit

Symbol

0

RS

1

2

Value

Reset Access
value

Run/Stop

0

R/W

0
Controller reset.
Software uses this bit to reset the controller. This bit is set to zero by
the Host/Device Controller when the reset process is complete.
Software cannot terminate the reset process early by writing a zero to
this register.

R/W

0

When this bit is set to 0, the Host Controller completes the current
transaction on the USB and then halts. The HC Halted bit in the
status register indicates when the Host Controller has finished the
transaction and has entered the stopped state. Software should not
write a one to this field unless the host controller is in the Halted state
(i.e. HCHalted in the USBSTS register is a one).

1

When set to a 1, the Host Controller proceeds with the execution of
the schedule. The Host Controller continues execution as long as this
bit is set to a one.

RST

FS0

Description

0

This bit is set to zero by hardware when the reset process is
complete.

1

When software writes a one to this bit, the Host Controller resets its
internal pipelines, timers, counters, state machines etc. to their initial
value. Any transaction currently in progress on USB is immediately
terminated. A USB reset is not driven on downstream ports. Software
should not set this bit to a one when the HCHalted bit in the USBSTS
register is a zero. Attempting to reset an actively running host
controller will result in undefined behavior.
0

Bit 0 of the Frame List Size bits. See Table 531.
This field specifies the size of the frame list that controls which bits in
the Frame Index Register should be used for the Frame List Current
index. Note that this field is made up from USBCMD bits 15, 3, and 2.

3

FS1

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Chapter 26: LPC43xx/LPC43Sxx USB1 Host/Device controller

Table 530. USB Command register in host mode (USBCMD_H - address 0x4000 7140) bit description …continued
Bit

Symbol

4

PSE

5

6

Value

Description

Reset Access
value

This bit controls whether the host controller skips processing the
periodic schedule.

0

R/W

0

R/W

0

R/W

0

Do not process the periodic schedule.

1

Use the PERIODICLISTBASE register to access the periodic
schedule.

ASE

This bit controls whether the host controller skips processing the
asynchronous schedule.
0

Do not process the asynchronous schedule.

1

Use the ASYNCLISTADDR to access the asynchronous schedule.

IAA

This bit is used as a doorbell by software to tell the host controller to
issue an interrupt the next time it advances asynchronous schedule.
0

The host controller sets this bit to zero after it has set the Interrupt on
Sync Advance status bit in the USBSTS register to one.

1

Software must write a 1 to this bit to ring the doorbell.
When the host controller has evicted all appropriate cached schedule
states, it sets the Interrupt on Async Advance status bit in the
USBSTS register. If the Interrupt on Sync Advance Enable bit in the
USBINTR register is one, then the host controller will assert an
interrupt at the next interrupt threshold.
Software should not write a one to this bit when the asynchronous
schedule is inactive. Doing so will yield undefined results.

7

-

9:8

ASP1_0

-

Reserved

0

Asynchronous schedule park mode.
11
Contains a count of the number of successive transactions the host
controller is allowed to execute from a high-speed queue head on the
Asynchronous schedule before continuing traversal of the
Asynchronous schedule. Valid values are 0x1 to 0x3.

R/W

Remark: Software must not write 00 to this bit when Park Mode
Enable is one as this will result in undefined behavior.
10

-

11

ASPE

-

Reserved.

0

-

Asynchronous Schedule Park Mode Enable

1

R/W

0

-

0

-

0

Park mode is disabled.

1

Park mode is enabled.

12

-

-

Reserved.

13

-

-

Not used in Host mode.

14

-

-

Reserved.

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Chapter 26: LPC43xx/LPC43Sxx USB1 Host/Device controller

Table 530. USB Command register in host mode (USBCMD_H - address 0x4000 7140) bit description …continued
Bit

Symbol

15

FS2

23:16

ITC

Value

Description

Reset Access
value

Bit 2 of the Frame List Size bits. See Table 531.

0

-

Interrupt threshold control.

0x8

R/W

The system software uses this field to set the maximum rate at which
the host/device controller will issue interrupts. ITC contains the
maximum interrupt interval measured in micro-frames. Valid values
are shown below. All other values are reserved.
0x0 = Immediate (no threshold)
0x1 = 1 micro frame.
0x2 = 2 micro frames.
0x8 = 8 micro frames.
0x10 = 16 micro frames.
0x20 = 32 micro frames.
0x40 = 64 micro frames.
31:24

-

Reserved

0

Table 531. Frame list size values
USBCMD bit 15

USBCMD bit 3

USBCMD bit 2

Frame list size

0

0

0

1024 elements (4096 bytes) - default
value

0

0

1

512 elements (2048 bytes)

0

1

0

256 elements (1024 bytes)

0

1

1

128 elements (512 bytes)

1

0

0

64 elements (256 bytes)

1

0

1

32 elements (128 bytes)

1

1

0

16 elements (64 bytes)

1

1

1

8 elements (32 bytes)

26.6.3 USB Status register (USBSTS)
This register indicates various states of the Host/Device controller and any pending
interrupts. Software sets a bit to zero in this register by writing a one to it.
Remark: This register does not indicate status resulting from a transaction on the serial
bus.

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Chapter 26: LPC43xx/LPC43Sxx USB1 Host/Device controller

26.6.3.1 Device mode
Table 532. USB Status register in device mode (USBSTS_D - address 0x4000 7144) register bit description
Bit

Symbol

0

UI

1

2

Value

SEI

Access

USB interrupt

0

R/WC

0

R/WC

0

R/WC

0

-

This bit is cleared by software writing a one to it.

1

This bit is set by the device controller under the
following conditions:

•

when the cause of an interrupt is a
completion of a USB transaction where the
Transfer Descriptor (TD) has an interrupt on
complete (IOC) bit set.

•

when a short packet is detected. A short
packet is when the actual number of bytes
received was less than the expected number
of bytes.

•

when a SETUP packet is received,

USB error interrupt
0

This bit is cleared by software writing a one to it.

1

When completion of a USB transaction results in
an error condition, this bit is set by the
Host/Device Controller. This bit is set along with
the USBINT bit, if the TD on which the error
interrupt occurred also had its interrupt on
complete (IOC) bit set. The device controller
detects resume signaling only (see
Section 25.10.11.6).

PCI

4

Reset
value

0

UEI

3

Description

Port change detect.
0

This bit is cleared by software writing a one to it.

1

The Device Controller sets this bit to a one when
the port controller enters the full or high-speed
operational state. When the port controller exits
the full or high-speed operation states due to
Reset or Suspend events, the notification
mechanisms are the USB Reset Received bit
(URI) and the DCSuspend bits (SLI) respectively.

0

System Error

Not used in Device mode.
The USB Controller sets this bit to 1 when a
serious error occurs during a system access
involving the USB Controller module. Conditions
that set this bit to 1 include AHB Parity error, AHB
Master Abort, and AHB Target Abort. When this
error occurs, the USB Controller clears the
Run/Stop bit in the Command register to prevent
further execution of the scheduled TDs.

5

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Not used in Device mode.

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Chapter 26: LPC43xx/LPC43Sxx USB1 Host/Device controller

Table 532. USB Status register in device mode (USBSTS_D - address 0x4000 7144) register bit description
Bit

Symbol

6

URI

7

8

Value

Description

Reset
value

Access

USB reset received

0

R/WC

0

R/WC

0

R/WC

0

This bit is cleared by software writing a one to it.

1

When the device controller detects a USB Reset
and enters the default state, this bit will be set to a
one.

0

This bit is cleared by software writing a one to it.

1

When the device controller detects a Start Of
(micro) Frame, this bit will be set to a one. When
a SOF is extremely late, the device controller will
automatically set this bit to indicate that an SOF
was expected. Therefore, this bit will be set
roughly every 1 ms in device FS mode and every
125 s in HS mode and will be synchronized to
the actual SOF that is received. Since the device
controller is initialized to FS before connect, this
bit will be set at an interval of 1ms during the
prelude to connect and chirp.

SRI

SOF received

SLI

DCSuspend
0

The device controller clears the bit upon exiting
from a Suspended state. This bit is cleared by
software writing a one to it.

1

When a device controller enters a Suspended
state from an active state, this bit will be set to a
one.

11:9

-

-

Reserved. Software should only write 0 to
reserved bits.

0

12

-

-

Not used in Device mode.

0

13

-

-

Not used in Device mode.

0

14

-

-

Not used in Device mode.

0

15

-

-

Not used in Device mode.

0

16

NAKI

NAK interrupt bit

0

RO

0

This bit is automatically cleared by hardware
when the all the enabled TX/RX Endpoint NAK
bits are cleared.

1

It is set by hardware when for a particular
endpoint both the TX/RX Endpoint NAK bit and
the corresponding TX/RX Endpoint NAK Enable
bit are set.

-

Reserved. Software should only write 0 to
reserved bits.

0

-

17

-

18

-

Not used in Device mode.

0

-

19

-

Not used in Device mode.

0

-

31:20

-

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Reserved. Software should only write 0 to
reserved bits.

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Chapter 26: LPC43xx/LPC43Sxx USB1 Host/Device controller

26.6.3.2 Host mode
Table 533. USB Status register in host mode (USBSTS_H - address 0x4000 7144) register bit description
Bit

Symbol Value

Description

Reset Access
value

0

UI

USB interrupt (USBINT)

0

R/WC

0

R/WC

0

R/WC

0

R/WC

0

R/WC

0

This bit is cleared by software writing a one to it.

1

This bit is set by the Host/Device Controller when the cause of an interrupt
is a completion of a USB transaction where the Transfer Descriptor (TD)
has an interrupt on complete (IOC) bit set.
This bit is also set by the Host/Device Controller when a short packet is
detected. A short packet is when the actual number of bytes received was
less than the expected number of bytes.

1

2

3

4

UEI

USB error interrupt (USBERRINT)
0

This bit is cleared by software writing a one to it.

1

When completion of a USB transaction results in an error condition, this bit
is set by the Host/Device Controller. This bit is set along with the USBINT
bit, if the TD on which the error interrupt occurred also had its interrupt on
complete (IOC) bit set.

0

This bit is cleared by software writing a one to it.

1

The Host Controller sets this bit to a one when on any port a Connect
Status occurs, a Port Enable/Disable Change occurs, or the Force Port
Resume bit is set as the result of a J-K transition on the suspended port.

PCI

Port change detect.

FRI

SEI

Frame list roll-over
0

This bit is cleared by software writing a one to it.

1

The Host Controller sets this bit to a one when the Frame List Index rolls
over from its maximum value to zero. The exact value at which the rollover
occurs depends on the frame list size. For example, if the frame list size (as
programmed in the Frame List Size field of the USBCMD register) is 1024,
the Frame Index Register rolls over every time FRINDEX [13] toggles.
Similarly, if the size is 512, the Host Controller sets this bit to a one every
time FRINDEX bit 12 toggles (see Section 26.6.5).

0

System Error
The USB Controller sets this bit to 1 when a serious error occurs during a
system access involving the USB Controller module. Conditions that set
this bit to 1 include AHB Parity error, AHB Master Abort, and AHB Target
Abort. When this error occurs, the USB Controller clears the Run/Stop bit in
the Command register to prevent further execution of the scheduled TDs.

5

AAI

6

-

7

SRI

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0

This bit is cleared by software writing a one to it.

1

System software can force the host controller to issue an interrupt the next
time the host controller advances the asynchronous schedule by writing a
one to the Interrupt on Async Advance Doorbell bit in the USBCMD
register. This status bit indicates the assertion of that interrupt source.

-

Not used by the Host controller.

0

R/WC

SOF received

0

R/WC

0

This bit is cleared by software writing a one to it.

1

In host mode, this bit will be set every 125 s and can be used by host
controller driver as a time base.
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Chapter 26: LPC43xx/LPC43Sxx USB1 Host/Device controller

Table 533. USB Status register in host mode (USBSTS_H - address 0x4000 7144) register bit description …continued
Bit

Symbol Value

Description

Reset Access
value

8

SLI

-

Not used by the Host controller.

-

-

11:9

-

-

Reserved.

12

HCH

1

RO

0

RO

0

RO

13

HCHalted
0

The RS bit in USBCMD is set to zero. Set by the host controller.

1

The Host Controller sets this bit to one after it has stopped executing
because of the Run/Stop bit being set to 0, either by software or by the
Host Controller hardware (e.g. because of an internal error).

RCL

Reclamation
0
1

14

PS

No empty asynchronous schedule detected.
An empty asynchronous schedule is detected. Set by the host controller.
Periodic schedule status
This bit reports the current real status of the Periodic Schedule. The Host
Controller is not required to immediately disable or enable the Periodic
Schedule when software transitions the Periodic Schedule Enable bit in the
USBCMD register. When this bit and the Periodic Schedule Enable bit are
the same value, the Periodic Schedule is either enabled (if both are 1) or
disabled (if both are 0).

15

0

The periodic schedule status is disabled.

1

The periodic schedule status is enabled.

AS

Asynchronous schedule status

0

This bit reports the current real status of the Asynchronous Schedule. The
Host Controller is not required to immediately disable or enable the
Asynchronous Schedule when software transitions the Asynchronous
Schedule Enable bit in the USBCMD register. When this bit and the
Asynchronous Schedule Enable bit are the same value, the Asynchronous
Schedule is either enabled (if both are 1) or disabled (if both are 0).
0
1

Asynchronous schedule status is disabled.
Asynchronous schedule status is enabled.

16

-

Not used on Host mode.

17

-

Reserved.

18

UAI

USB host asynchronous interrupt (USBHSTASYNCINT)

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0

This bit is cleared by software writing a one to it.

1

This bit is set by the Host Controller when the cause of an interrupt is a
completion of a USB transaction where the Transfer Descriptor (TD) has an
interrupt on complete (IOC) bit set and the TD was from the asynchronous
schedule. This bit is also set by the Host when a short packet is detected
and the packet is on the asynchronous schedule. A short packet is when
the actual number of bytes received was less than the expected number of
bytes.

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-

0

R/WC

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Chapter 26: LPC43xx/LPC43Sxx USB1 Host/Device controller

Table 533. USB Status register in host mode (USBSTS_H - address 0x4000 7144) register bit description …continued
Bit

Symbol Value

Description

Reset Access
value

19

UPI

USB host periodic interrupt (USBHSTPERINT)

0

R/WC

-

-

31:20

-

0

This bit is cleared by software writing a one to it.

1

This bit is set by the Host Controller when the cause of an interrupt is a
completion of a USB transaction where the Transfer Descriptor (TD) has an
interrupt on complete (IOC) bit set and the TD was from the periodic
schedule. This bit is also set by the Host Controller when a short packet is
detected and the packet is on the periodic schedule. A short packet is
when the actual number of bytes received was less than the expected
number of bytes.
Reserved.

26.6.4 USB Interrupt register (USBINTR)
The software interrupts are enabled with this register. An interrupt is generated when a bit
is set and the corresponding interrupt is active. The USB Status register (USBSTS) still
shows interrupt sources even if they are disabled by the USBINTR register, allowing
polling of interrupt events by the software. All interrupts must be acknowledged by
software by clearing (that is writing a 1 to) the corresponding bit in the USBSTS register.

26.6.4.1 Device mode
Table 534. USB Interrupt register in device mode (USBINTR_D - address 0x4000 7148) bit description
Bit

Symbol Description

Reset
value

Access

0

UE

0

R/W

0

R/W

0

R/W

0

-

0

R/W

USB interrupt enable
When this bit is one, and the USBINT bit in the USBSTS register is one, the
host/device controller will issue an interrupt at the next interrupt threshold. The
interrupt is acknowledged by software clearing the USBINT bit in USBSTS.

1

UEE

USB error interrupt enable
When this bit is a one, and the USBERRINT bit in the USBSTS register is a one, the
host/device controller will issue an interrupt at the next interrupt threshold. The
interrupt is acknowledged by software clearing the USBERRINT bit in the USBSTS
register.

2

PCE

Port change detect enable
When this bit is a one, and the Port Change Detect bit in the USBSTS register is a
one, the host/device controller will issue an interrupt. The interrupt is acknowledged by
software clearing the Port Change Detect bit in USBSTS.

3

-

Not used by the Device controller.

4

SEE

System Error Enable
When this bit is a one, and the System Error bit in the USBSTS register is a one, the
host/device controller will issue an interrupt. The interrupt is acknowledged by
software clearing the System Error bit in USBSTS register.

5

-

Not used by the Device controller.

6

URE

USB reset enable
When this bit is a one, and the USB Reset Received bit in the USBSTS register is a
one, the device controller will issue an interrupt. The interrupt is acknowledged by
software clearing the USB Reset Received bit.

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Chapter 26: LPC43xx/LPC43Sxx USB1 Host/Device controller

Table 534. USB Interrupt register in device mode (USBINTR_D - address 0x4000 7148) bit description …continued
Bit

Symbol Description

Reset
value

Access

7

SRE

0

R/W

0

R/W

SOF received enable
When this bit is a one, and the SOF Received bit in the USBSTS register is a one, the
device controller will issue an interrupt. The interrupt is acknowledged by software
clearing the SOF Received bit.

8

SLE

Sleep enable
When this bit is a one, and the DCSuspend bit in the USBSTS
register transitions, the device controller will issue an interrupt. The interrupt is
acknowledged by software writing a one to the DCSuspend bit.

15:9

-

Reserved

-

-

16

NAKE

NAK interrupt enable

0

R/W

This bit is set by software if it wants to enable the hardware interrupt for the NAK
Interrupt bit. If both this bit and the corresponding NAK Interrupt bit are set, a
hardware interrupt is generated.
17

-

Reserved

18

UAIE

Not used by the Device controller.

19

UPIA

Not used by the Device controller.

31:20 -

Reserved

26.6.4.2 Host mode
Table 535. USB Interrupt register in host mode (USBINTR_H - address 0x4000 7148) bit description
Bit

Symbol Description

Access Reset
value

0

UE

R/W

0

R/W

0

R/W

0

-

0

USB interrupt enable
When this bit is one, and the USBINT bit in the USBSTS register is one, the
host/device controller will issue an interrupt at the next interrupt threshold. The
interrupt is acknowledged by software clearing the USBINT bit in USBSTS.

1

UEE

USB error interrupt enable
When this bit is a one, and the USBERRINT bit in the USBSTS register is a one, the
host/device controller will issue an interrupt at the next interrupt threshold. The
interrupt is acknowledged by software clearing the USBERRINT bit in the USBSTS
register.

2

PCE

Port change detect enable
When this bit is a one, and the Port Change Detect bit in the USBSTS register is a
one, the host/device controller will issue an interrupt. The interrupt is acknowledged
by software clearing the Port Change Detect bit in USBSTS.

3

FRE

Frame list rollover enable
When this bit is a one, and the Frame List Rollover bit in the USBSTS register is a
one, the host controller will issue an interrupt. The interrupt is acknowledged by
software clearing the Frame List Rollover bit.

4

SEE

System Error Enable
When this bit is a one, and the System Error bit in the USBSTS register is a one, the
host/device controller will issue an interrupt. The interrupt is acknowledged by
software clearing the System Error bit in USBSTS register.

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Chapter 26: LPC43xx/LPC43Sxx USB1 Host/Device controller

Table 535. USB Interrupt register in host mode (USBINTR_H - address 0x4000 7148) bit description …continued
Bit

Symbol Description

Access Reset
value

5

AAE

R/W

Interrupt on asynchronous advance enable

0

When this bit is a one, and the Interrupt on Async Advance bit in the USBSTS register
is a one, the host controller will issue an interrupt at the next interrupt threshold. The
interrupt is acknowledged by software clearing the Interrupt on Async Advance bit.
6

-

Not used by the Host controller.

-

0

7

SRE

If this bit is one and the SRI bit in the USBSTS register is one, the host controller will issue an interrupt. In host mode, the SRI bit will be set every 125 s and can be used
by the host controller as a time base. The interrupt is acknowledged by software
clearing the SRI bit in the USBSTS register.

0

8

-

Not used by the Host controller.

-

0

15:9

-

Reserved

16

-

Not used by the host controller.

R/W

0

17

-

Reserved

18

UAIE

USB host asynchronous interrupt enable

R/W

0

R/W

0

When this bit is a one, and the USBHSTASYNCINT bit in the USBSTS register is a
one, the host controller will issue an interrupt at the next interrupt threshold. The
interrupt is acknowledged by software clearing the USBHSTASYNCINT bit.
19

UPIA

USB host periodic interrupt enable
When this bit is a one, and the USBHSTPERINT bit in the USBSTS register is a one,
the host controller will issue an interrupt at the next interrupt threshold. The interrupt is
acknowledged by software clearing the USBHSTPERINT bit.

31:20 -

Reserved

26.6.5 Frame index register (FRINDEX)
26.6.5.1 Device mode
In Device mode this register is read only, and the device controller updates the
FRINDEX[13:3] register from the frame number indicated by the SOF marker. Whenever a
SOF is received by the USB bus, FRINDEX[13:3] will be checked against the SOF
marker. If FRINDEX[13:3] is different from the SOF marker, FRINDEX[13:3] will be set to
the SOF value and FRINDEX[2:0] will be set to zero (i.e. SOF for 1 ms frame). If
FRINDEX [13:3] is equal to the SOF value, FRINDEX[2:0] will be incremented (i.e. SOF
for 125 s micro-frame) by hardware.
Table 536. USB frame index register in device mode (FRINDEX_D - address 0x4000 714C) bit
description

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Bit

Symbol

Description

Reset value

Access

2:0

FRINDEX2_0

Current micro frame number

-

RO

13:3

FRINDEX13_3

Current frame number of the last frame
transmitted

-

RO

31:14

-

Reserved

-

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Chapter 26: LPC43xx/LPC43Sxx USB1 Host/Device controller

26.6.5.2 Host mode
This register is used by the host controller to index the periodic frame list. The register
updates every 125 s (once each micro-frame). Bits[N: 3] are used to select a particular
entry in the Periodic Frame List during periodic schedule execution. The number of bits
used for the index depends on the size of the frame list as set by system software in the
Frame List Size field in the USBCMD register.
This register must be written as a DWord. Byte writes produce undefined results. This
register cannot be written unless the Host Controller is in the 'Halted' state as indicated by
the HCHalted bit in the USBSTS register (host mode). A write to this register while the
Run/Stop bit is set to a one produces undefined results. Writes to this register also affect
the SOF value.
Table 537. USB frame index register in host mode (FRINDEX_H - address 0x4000 714C) bit
description
Bit

Symbol

Description

Reset value

Access

2:0

FRINDEX2_0

Current micro frame number

-

R/W

12:3

FRINDEX12_3

Frame list current index for
1024 elements.

-

R/W

31:13

-

Reserved

-

Table 538. Number of bits used for the frame list index
USBCMD USBCMD USBCMD Frame list size
bit 15
bit 3
bit 2

Size of
FRINDEX12_3
bit field

0

0

0

1024 elements (4096 bytes). Default value.

12

0

0

1

512 elements (2048 bytes)

11

0

1

0

256 elements (1024 bytes)

10

0

1

1

128 elements (512 bytes)

9

1

0

0

64 elements (256 bytes)

8

1

0

1

32 elements (128 bytes)

7

1

1

0

16 elements (64 bytes)

6

1

1

1

8 elements (32 bytes)

5

26.6.6 Device address (DEVICEADDR) and Periodic List Base
(PERIODICLISTBASE) registers
26.6.6.1 Device mode
The upper seven bits of this register represent the device address. After any controller
reset or a USB reset, the device address is set to the default address (0). The default
address will match all incoming addresses. Software shall reprogram the address after
receiving a SET_ADDRESS descriptor.
The USBADRA bit is used to accelerate the SET_ADDRESS sequence by allowing the
DCD to preset the USBADR register bits before the status phase of the SET_ADDRESS
descriptor.

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Table 539. USB Device Address register in device mode (DEVICEADDR - address 0x4000 7154) bit description
Bit

Symbol

Value Description

23:0

-

reserved

24

USBADRA

Device address advance
0

Any write to USBADR are instantaneous.

1

When the user writes a one to this bit at the same time or before USBADR
is written, the write to USBADR fields is staged and held in a hidden
register. After an IN occurs on endpoint 0 and is acknowledged, USBADR
will be loaded from the holding register.

Reset
value

Access

0

-

0

R/W

Hardware will automatically clear this bit on the following conditions:

•

IN is ACKed to endpoint 0. USBADR is updated from the staging
register.

•
•

OUT/SETUP occurs on endpoint 0. USBADR is not updated.
Device reset occurs. USBADR is set to 0.

Remark: After the status phase of the SET_ADDRESS descriptor, the
DCD has 2 ms to program the USBADR field. This mechanism will ensure
this specification is met when the DCD can not write the device address
within 2 ms from the SET_ADDRESS status phase. If the DCD writes the
USBADR with USBADRA=1 after the SET_ADDRESS data phase (before
the prime of the status phase), the USBADR will be programmed instantly
at the correct time and meet the 2 ms USB requirement.
31:25

USBADR

USB device address

26.6.6.2 Host mode
This 32-bit register contains the beginning address of the Periodic Frame List in the
system memory. The host controller driver (HCD) loads this register prior to starting the
schedule execution by the Host Controller. The memory structure referenced by this
physical memory pointer is assumed to be 4 kB aligned. The contents of this register are
combined with the Frame Index Register (FRINDEX) to enable the Host Controller to step
through the Periodic Frame List in sequence.
Table 540. USB Periodic List Base register in host mode (PERIODICLISTBASE - address 0x4000 7154) bit
description
Bit

Symbol

Description

Reset
value

Access

11:0

-

Reserved

N/A

-

31:12

PERBASE31_12

Base Address (Low)

N/A

R/W

These bits correspond to the memory address signals[31:12].

26.6.7 Endpoint List Address register (ENDPOINTLISTADDR) and
Asynchronous List Address (ASYNCLISTADDR) registers
26.6.7.1 Device mode
In device mode, this register contains the address of the top of the endpoint list in system
memory. Bits[10:0] of this register cannot be modified by the system software and will
always return a zero when read.The memory structure referenced by this physical
memory pointer is assumed 64 byte aligned.

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Table 541. USB Endpoint List Address register in device mode (ENDPOINTLISTADDR - address 0x4000 7158) bit
description
Bit

Symbol

Description

Reset
value

Access

10:0

-

reserved

0

-

31:11

EPBASE31_11

Endpoint list pointer (low)

N/A

R/W

These bits correspond to memory address signals 31:11, respectively. This
field will reference a list of up to 8 Queue Heads (QH). (i.e. one queue head
per endpoint and direction.)

26.6.7.2 Host mode
This 32-bit register contains the address of the next asynchronous queue head to be
executed by the host. Bits [4:0] of this register cannot be modified by the system software
and will always return a zero when read.
Table 542. USB Asynchronous List Address register in host mode (ASYNCLISTADDR- address 0x4000 7158) bit
description
Bit

Symbol

Description

Reset
value

Access

4:0

-

Reserved

0

-

31:5

ASYBASE31_5

Link pointer (Low) LPL

-

R/W

These bits correspond to memory address signals 31:5, respectively. This
field may only reference a Queue Head (OH).

26.6.8 TT Control register (TTCTRL)
26.6.8.1 Device mode
This register is not used in device mode.

26.6.8.2 Host mode
This register contains parameters needed for internal TT operations. This register is used
by the host controller only. Writes must be in Dwords.
Table 543. USB TT Control register in host mode (TTCTRL - address 0x4000 715C) bit description
Bit

Symbol

Description

Reset
value

Access

23:0

-

Reserved.

0

-

30:24

TTHA

Hub address when FS or LS device are connected directly.

N/A

R/W

31

-

Reserved.

0

26.6.9 Burst Size register (BURSTSIZE)
This register is used to control and dynamically change the burst size used during data
movement on the master interface of the USB DMA controller. Writes must be in Dwords.
The default for the length of a burst of 32-bit words for RX and TX DMA data transfers is
16 words each.

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Table 544. USB burst size register in device/host mode (BURSTSIZE - address 0x4000 7160) bit description
Bit

Symbol

Description

Reset
value

Access

7:0

RXPBURST

Programmable RX burst length

0x10

R/W

0x10

R/W

-

-

This register represents the maximum length of a burst in 32-bit words while
moving data from the USB bus to system memory.
15:8

TXPBURST

Programmable TX burst length
This register represents the maximum length of a burst in 32-bit words while
moving data from system memory to the USB bus.

31:16

-

reserved

26.6.10 Transfer buffer Fill Tuning register (TXFILLTUNING)
26.6.10.1 Device controller
This register is not used in device mode.

26.6.10.2 Host controller
The fields in this register control performance tuning associated with how the host
controller posts data to the TX latency FIFO before moving the data onto the USB bus.
The specific areas of performance include the how much data to post into the FIFO and
an estimate for how long that operation should take in the target system.
Definitions:
T0 = Standard packet overhead
T1 = Time to send data payload
Tff = Time to fetch packet into TX FIFO up to specified level
Ts = Total packet flight time (send-only) packet; Ts = T0 + T1
Tp = Total packet time (fetch and send) packet; Tp = Tff + T0 + T1
Upon discovery of a transmit (OUT/SETUP) packet in the data structures, host controller
checks to ensure Tp remains before the end of the (micro) frame. If so it proceeds to
pre-fill the TX FIFO. If at anytime during the pre-fill operation the time remaining the
[micro]frame is < Ts then the packet attempt ceases and the packet is tried at a later time.
Although this is not an error condition and the host controller will eventually recover, a
mark will be made the scheduler health counter to note the occurrence of a “backoff”
event. When a back-off event is detected, the partial packet fetched may need to be
discarded from the latency buffer to make room for periodic traffic that will begin after the
next SOF. Too many back-off events can waste bandwidth and power on the system bus
and thus should be minimized (not necessarily eliminated). Backoffs can be minimized
with use of the TSCHHEALTH (Tff) described below.

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Table 545. USB Transfer buffer Fill Tuning register in host mode (TXFILLTUNING - address 0x4000 7164) bit
description
Bit

Symbol

Description

Reset
value

Access

7:0

TXSCHOH

FIFO burst threshold

0x2

R/W

0x0

R/W

This register controls the number of data bursts that are posted to the TX
latency FIFO in host mode before the packet begins on to the bus. The
minimum value is 2 and this value should be a low as possible to maximize
USB performance. A higher value can be used in systems with unpredictable
latency and/or insufficient bandwidth where the FIFO may underrun because
the data transferred from the latency FIFO to USB occurs before it can be
replenished from system memory. This value is ignored if the Stream Disable
bit in USBMODE register is set.
12:8

TXSCHEATLTH Scheduler health counter
This register increments when the host controller fails to fill the TX latency
FIFO to the level programmed by TXFIFOTHRES before running out of time
to send the packet before the next Start-Of-Frame .
This health counter measures the number of times this occurs to provide
feedback to selecting a proper TXSCHOH. Writing to this register will clear the
counter. The maximum value is 31.

15:13

-

Reserved

-

-

21:16

TXFIFOTHRES

Scheduler overhead

0x0

R/W

This register adds an additional fixed offset to the schedule time estimator
described above as Tff. As an approximation, the value chosen for this register
should limit the number of back-off events captured in the TXSCHHEALTH to
less than 10 per second in a highly utilized bus. Choosing a value that is too
high for this register is not desired as it can needlessly reduce USB utilization.
The time unit represented in this register is 1.267 s when a device is
connected in High-Speed Mode.
The time unit represented in this register is 6.333 s when a device is
connected in Low/Full Speed Mode.
31:22

-

Reserved

26.6.11 USB ULPI viewport register (ULPIVIEWPORT)
The register provides indirect access to the ULPI PHY register set. Although the core
performs access to the ULPI PHY register set, there may be extraordinary circumstances
where software may need direct access.
Remark: Writes to the ULPI through the viewport can substantially harm standard USB
operations. Currently no usage model has been defined where software should need to
execute writes directly to the ULPI – see exception regarding optional features below.
Remark: Executing read operations though the ULPI viewport should have no harmful
side effects to standard USB operations.
There are two operations that can be performed with the ULPI Viewport, wake-up and
read /write operations. The wakeup operation is used to put the ULPI interface into normal
operation mode and reenable the clock if necessary. A wakeup operation is required
before accessing the registers when the ULPI interface is operating in low power mode,
serial mode, or carkit mode. The ULPI state can be determined by reading the sync. state
bit (ULPISS). If this bit is a one, then ULPI interface is running in normal operation mode
and can accept read/write operations. If the ULPISS indicates a 0 then read/write
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operations will not be able execute. Undefined behavior will result if ULPISS = 0 and a
read or write operation is performed. To execute a wakeup operation, write all 32 bits of
the ULPI Viewport where ULPIPORT is constructed appropriately and the ULPIWU bit is a
1 and ULPIRUN bit is a 0. Poll the ULPI Viewport until ULPIWU is zero for the operation to
complete.
To execute a read or write operation, write all 32-bits of the ULPI Viewport where
ULPIDATWR, ULPIADDR, ULPIPORT, ULPIRW are constructed appropriately and the
ULPIRUN bit is a 1. Poll the ULPI Viewport until ULPIRUN is zero for the operation to
complete. Once ULPIRUN is zero, the ULPIDATRD will be valid if the operation was a
read.
The polling method above could also be replaced and interrupt driven using the ULPI
interrupt defined in the USBSTS and USBINTR registers. When a wakeup or read/write
operation complete, the ULPI interrupt will be set.

Table 546. USB ULPI viewport register (ULPIVIEWPORT - address 0x4000 7170) bit description
Bit

Symbol

7:0

Description

Access

Reset
value

ULPIDATWR

When a write operation is commanded, the data to be sent is written
to this field.

R/W

0

15:8

ULPIDATRD

After a read operation completes, the result is placed in this field.

R

0

23:16

ULPIADDR

When a read or write operation is commanded, the address of the
operation is written to this field.

R/W

0

26:24

ULPIPORT

For the wakeup or read/write operation to be executed, this value
must be written as 0.

R/W

000

27

ULPISS

ULPI sync state. This bit represents the state of the ULPI interface.

R

0

28

-

29

ULPIRW

30

ULPIRUN

Value

0

In another state (ie. carkit, serial, low power)

1

Normal Sync. State.

-

Reserved

-

-

ULPI Read/Write control. This bit selects between running a read or
write operation.

R/W

0

R/W

-

R/W

0

0

Read

1

Write
ULPI Read/Write Run.
Writing the 1 to this bit will begin the read/write operation. The bit will
automatically transition to 0 after the read/write is complete. Once
this bit is set, the driver can not set it back to 0.
Remark: The driver must never execute a wake-up and a read/write
operation at the same time.

31

ULPIWU

ULPI Wake-up.
Writing the 1 to this bit will begin the wake-up operation. The bit will
automatically transition to 0 after the wake-up is complete. Once this
bit is set, the driver can not set it back to 0.
Remark: The driver must never execute a wake-up and a read/write
operation at the same time.

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26.6.12 BINTERVAL register
This register defines the bInterval value which determines the length of the virtual frame
(see Section 25.7.7).
Remark: The BINTERVAL register is not related to the bInterval endpoint descriptor field
in the USB specification.
Table 547. USB BINTERVAL register (BINTERVAL - address 0x4000 7174) bit description in device/host mode
Bit

Symbol

Description

Reset
value

Access

3:0

BINT

bInterval value

0x00

R/W

31:4

-

Reserved

-

-

26.6.13 USB Endpoint NAK register (ENDPTNAK)
26.6.13.1 Device mode
This register indicates when the device sends a NAK handshake on an endpoint. Each Tx
and Rx endpoint has a bit in the EPTN and EPRN field respectively.
A bit in this register is cleared by writing a 1 to it.
Table 548. USB endpoint NAK register in device mode (ENDPTNAK - address 0x4000 7178) bit description
Bit

Symbol

Description

Reset
value

Access

3:0

EPRN

Rx endpoint NAK

0x00

R/WC

Each RX endpoint has one bit in this field. The bit is set when the device
sends a NAK handshake on a received OUT or PING token for the
corresponding endpoint.
Bit 3 corresponds to endpoint 3.
...
Bit 1 corresponds to endpoint 1.
Bit 0 corresponds to endpoint 0.
15:6

-

Reserved

-

-

19:16

EPTN

Tx endpoint NAK

0x00

R/WC

-

-

Each TX endpoint has one bit in this field. The bit is set when the device
sends a NAK handshake on a received IN token for the corresponding
endpoint.
Bit 3 corresponds to endpoint 3.
...
Bit 1 corresponds to endpoint 1.
Bit 0 corresponds to endpoint 0.
31:20

-

Reserved

26.6.13.2 Host mode
This register is not used in host mode.

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26.6.14 USB Endpoint NAK Enable register (ENDPTNAKEN)
26.6.14.1 Device mode
Each bit in this register enables the corresponding bit in the ENDPTNAK register. Each Tx
and Rx endpoint has a bit in the EPTNE and EPRNE field respectively.
Table 549. USB Endpoint NAK Enable register in device mode (ENDPTNAKEN - address 0x4000 717C) bit
description
Bit

Symbol

3:0

EPRNE

Description

Reset
value

Access

Rx endpoint NAK enable

0x00

R/W

Reserved

-

-

Tx endpoint NAK

0x00

R/W

-

-

Each bit enables the corresponding RX NAK bit. If this bit is set and the
corresponding RX endpoint NAK bit is set, the NAK interrupt bit is set.
Bit 3 corresponds to endpoint 3.
...
Bit 1 corresponds to endpoint 1.
Bit 0 corresponds to endpoint 0.
15:4

-

19:16

EPTNE

Each bit enables the corresponding TX NAK bit. If this bit is set and the
corresponding TX endpoint NAK bit is set, the NAK interrupt bit is set.
Bit 3 corresponds to endpoint 3.
...
Bit 1 corresponds to endpoint 1.
Bit 0 corresponds to endpoint 0.
31:20

-

Reserved

26.6.14.2 Host mode
This register is not used in host mode.

26.6.15 Port Status and Control register (PORTSC1)
26.6.15.1 Device mode
The device controller implements one port register, and it does not support power control.
Port control in device mode is used for status port reset, suspend, and current connect
status. It is also used to initiate test mode or force signaling. This register allows software
to put the PHY into low-power Suspend mode and disable the PHY clock.

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Table 550. Port Status and Control register in device mode (PORTSC1_D - address 0x4000 7184) bit description
Bit

Symbol

0

CCS

Value Description
Current connect status
0

Reset
value

Access

0

RO

Device not attached
A zero indicates that the device did not attach successfully or was forcibly
disconnected by the software writing a zero to the Run bit in the USBCMD
register. It does not state the device being disconnected or suspended.

1

Device attached.
A one indicates that the device successfully attached and is operating in
either high-speed mode or full-speed mode as indicated by the High Speed
Port bit in this register.

1

CSC

-

Not used in device mode

0

-

2

PE

1

Port enable.
This bit is always 1. The device port is always enabled.

1

RO

3

PEC

0

Port enable/disable change

0

RO

Reserved

0

RO

Force port resume
After the device has been in Suspended state for 5 ms or more, software
must set this bit to one to drive resume signaling before clearing. The
Device Controller will set this bit to one if a J-to-K transition is detected
while the port is in the Suspended state. The bit will be cleared when the
device returns to normal operation. When this bit transitions to a one
because a J-to-K transition detected, the Port Change Detect bit in the
USBSTS register is set to one as well.

0

R/W

0

RO

0

RO

0

RO

-

-

This bit is always 0. The device port is always enabled.
5:4

-

6

FPR

-

0
1
7

SUSP

1

9

Resume detected/driven on port.
Suspend
In device mode, this is a read-only status bit .

0
8

No resume (K-state) detected/driven on port.

PR

Port not in Suspended state
Port in Suspended state
Port reset
In device mode, this is a read-only status bit. A device reset from the USB
bus is also indicated in the USBSTS register.

0

Port is not in the reset state.

1

Port is in the reset state.

HSP

High-speed status
Remark: This bit is redundant with bits 27:26 (PSPD) in this register. It is
implemented for compatibility reasons.
0

Host/device connected to the port is not in High-speed mode.

1

Host/device connected to the port is in High-speed mode.

11:10 LS

-

Not used in device mode.

12

PP

-

Not used in device mode.

13

-

-

Reserved

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Table 550. Port Status and Control register in device mode (PORTSC1_D - address 0x4000 7184) bit description
Bit

Symbol

Value Description

15:14 PIC1_0

Port indicator control
Writing to this field effects the value of the USB1_IND1:0 pins.
0x0

Port indicators are off.

0x1

amber

0x2

green

0x3
19:16 PTC3_0

Reset
value

Access

00

R/W

undefined
Port test control
0000
Any value other than 0000 indicates that the port is operating in test mode.

R/W

The FORCE_ENABLE_FS and FORCE ENABLE_LS are extensions to the
test mode support specified in the EHCI specification. Writing the PTC field
to any of the FORCE_ENABLE_HS/FS/LS values will force the port into
the connected and enabled state at the selected speed. Writing the PTC
field back to TEST_MODE_DISABLE will allow the port state machines to
progress normally from that point. Values 0x7 to 0xF are reserved.
0x0

TEST_MODE_DISABLE

0x1

J_STATE

0x2

K_STATE

0x3

SE0 (host)/NAK (device)

0x4

Packet

0x5

FORCE_ENABLE_HS

0x6

FORCE_ENABLE_FS

20

-

-

Not used in device mode. This bit is always 0 in device mode.

0

-

21

-

-

Not used in device mode. This bit is always 0 in device mode.

0

-

22

-

Not used in device mode. This bit is always 0 in device mode.

0

-

23

PHCD

PHY low power suspend - clock disable (PLPSCD)

0

R/W

0

R/W

In device mode, The PHY can be put into Low Power Suspend – Clock
Disable when the device is not running (USBCMD Run/Stop = 0) or the
host has signaled suspend (PORTSC SUSPEND = 1). Low power suspend
will be cleared automatically when the host has signaled resume. Before
forcing a resume from the device, the device controller driver must clear
this bit.

24

25

0

Writing a 0 enables the PHY clock. Reading a 0 indicates the status of the
PHY clock (enabled).

1

Writing a 1 disables the PHY clock. Reading a 1 indicates the status of the
PHY clock (disabled).

PFSC

-

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0

Port connects at any speed.

1

Writing this bit to a 1 will force the port to only connect at full speed. It
disables the chirp sequence that allows the port to identify itself as
High-speed. This is useful for testing FS configurations with a HS host, hub
or device.

-

Reserved

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Table 550. Port Status and Control register in device mode (PORTSC1_D - address 0x4000 7184) bit description
Bit

Symbol

Value Description

27:26 PSPD

Port speed

Reset
value

Access

0

RO

This register field indicates the speed at which the port is operating.

29:28 -

0x1

Full-speed

0x2

invalid in device mode

0x3

High-speed

-

Reserved

-

-

Parallel transceiver select. All other values are reserved.

-

R/W

31:30 PTS
0x2

ULPI

0x3

Serial/ 1.1 PHY (Full-speed only)

26.6.15.2 Host mode
The host controller uses one port. The register is only reset when power is initially applied
or in response to a controller reset. The initial conditions of the port are:

• No device connected
• Port disabled
If the port has power control, this state remains until software applies power to the port by
setting port power to one in the PORTSC register.
Table 551. Port Status and Control register in host mode (PORTSC1_H - address 0x4000 7184) bit description
Bit

Symbol

0

CCS

Value Description
Current connect status

Reset
value

Access

0

R/WC

0

R/WC

This value reflects the current state of the port and may not correspond
directly to the event that caused the CSC bit to be set.
This bit is 0 if PP (Port Power bit) is 0.
Software clears this bit by writing a 1 to it.

1

0

No device is present.

1

Device is present on the port.

CSC

Connect status change
Indicates a change has occurred in the port’s Current Connect Status. The
host/device controller sets this bit for all changes to the port device connect
status, even if system software has not cleared an existing connect status
change. For example, the insertion status changes twice before system
software has cleared the changed condition, hub hardware will be ‘setting’
an already-set bit (i.e., the bit will remain set). Software clears this bit by
writing a one to it.
This bit is 0 if PP (Port Power bit) is 0

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No change in current status.

1

Change in current status.

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Chapter 26: LPC43xx/LPC43Sxx USB1 Host/Device controller

Table 551. Port Status and Control register in host mode (PORTSC1_H - address 0x4000 7184) bit description
…continued

Bit

Symbol

2

PE

Value Description
Port enable.

Reset
value

Access

0

R/W

0

R/WC

0

RO

0

R/WC

0

R/W

Ports can only be enabled by the host controller as a part of the reset and
enable. Software cannot enable a port by writing a one to this field. Ports
can be disabled by either a fault condition (disconnect event or other fault
condition) or by the host software. Note that the bit status does not change
until the port state actually changes. There may be a delay in disabling or
enabling a port due to other host controller and bus events.
When the port is disabled. downstream propagation of data is blocked
except for reset.
This bit is 0 if PP (Port Power bit) is 0.

3

PEC

0

Port disabled.

1

Port enabled.

0

Port disable/enable change
For the root hub, this bit gets set to a one only when a port is disabled due
to disconnect on the port or due to the appropriate conditions existing at
the EOF2 point (See Chapter 11 of the USB Specification). Software clears
this by writing a one to it.
This bit is 0 if PP (Port Power bit) is 0,

4

5

0

No change.

1

Port enabled/disabled status has changed.

OCA

Over-current active
This bit will automatically transition from 1 to 0 when the over-current
condition is removed.
0

The port does not have an over-current condition.

1

The port has currently an over-current condition.

OCC

Over-current change
This bit gets set to one when there is a change to Over-current Active.
Software clears this bit by writing a one to this bit position.

6

FPR

Force port resume
Software sets this bit to one to drive resume signaling. The Host Controller
sets this bit to one if a J-to-K transition is detected while the port is in the
Suspended state. When this bit transitions to a one because a J-to-K
transition is detected, the Port Change Detect bit in the USBSTS register is
also set to one. This bit will automatically change to zero after the resume
sequence is complete. This behavior is different from EHCI where the host
controller driver is required to set this bit to a zero after the resume duration
is timed in the driver.
Note that when the Host controller owns the port, the resume sequence
follows the defined sequence documented in the USB Specification
Revision 2.0. The resume signaling (Full-speed ‘K’) is driven on the port as
long as this bit remains a one. This bit will remain a one until the port has
switched to the high-speed idle. Writing a zero has no affect because the
port controller will time the resume operation clear the bit the port control
state switches to HS or FS idle.
This bit is 0 if PP (Port Power bit) is 0.

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0

No resume (K-state) detected/driven on port.

1

Resume detected/driven on port.
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Chapter 26: LPC43xx/LPC43Sxx USB1 Host/Device controller

Table 551. Port Status and Control register in host mode (PORTSC1_H - address 0x4000 7184) bit description
…continued

Bit

Symbol

7

SUSP

Value Description
Suspend
Together with the PE (Port enabled bit), this bit describes the port states,
see Table 552 “Port states as described by the PE and SUSP bits in the
PORTSC1 register”.

Reset
value

Access

0

R/W

0

R/W

0

RO

0x3

RO

The host controller will unconditionally set this bit to zero when software
sets the Force Port Resume bit to zero. The host controller ignores a write
of zero to this bit.
If host software sets this bit to a one when the port is not enabled (i.e. Port
enabled bit is a zero) the results are undefined.
This bit is 0 if PP (Port Power bit) is 0.
0

Port not in Suspended state

1

Port in Suspended state
When in Suspended state, downstream propagation of data is blocked on
this port, except for port reset. The blocking occurs at the end of the current
transaction if a transaction was in progress when this bit was written to 1.
In the Suspended state, the port is sensitive to resume detection. Note that
the bit status does not change until the port is suspended and that there
may be a delay in suspending a port if there is a transaction currently in
progress on the USB.

8

PR

Port reset
When software writes a one to this bit the bus-reset sequence as defined in
the USB Specification Revision 2.0 is started. This bit will automatically
change to zero after the reset sequence is complete. This behavior is
different from EHCI where the host controller driver is required to set this
bit to a zero after the reset duration is timed in the driver.
This bit is 0 if PP (Port Power bit) is 0.

9

0

Port is not in the reset state.

1

Port is in the reset state.

HSP

High-speed status
0
1

11:10 LS

Host/device connected to the port is not in High-speed mode.
Host/device connected to the port is in High-speed mode.
Line status
These bits reflect the current logical levels of the USB_DP and USB_DM
signal lines. USB_DP corresponds to bit 11 and USB_DM to bit 10.
In host mode, the use of linestate by the host controller driver is not
necessary for this controller (unlike EHCI) because the controller hardware
manages the connection of LS and FS.

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0x0

SE0 (USB_DP and USB_DM LOW)

0x1

J-state (USB_DP HIGH and USB_DM LOW)

0x2

K-state (USB_DP LOW and USB_DM HIGH)

0x3

Undefined

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Chapter 26: LPC43xx/LPC43Sxx USB1 Host/Device controller

Table 551. Port Status and Control register in host mode (PORTSC1_H - address 0x4000 7184) bit description
…continued

Bit

Symbol

Value Description

Reset
value

Access

12

PP

-

0

R/W

Port power control
Host controller requires port power control switches. This bit represents the
current setting of the switch (0=off, 1=on). When power is not available on
a port (i.e. PP equals a 0), the port is non-functional and will not report
attaches, detaches, etc.
When an over-current condition is detected on a powered port and PPC is
a one, the PP bit in each affected port may be transitioned by the host
controller driver from a one to a zero (removing power from the port).

13

-

0

Port power off.

1

Port power on.

-

15:14 PIC1_0

Reserved

0

-

Port indicator control
Writing to this field controls the value of the pins USB1_IND1 and
USB1_IND0.

00

R/W

0x0

Port indicators are off.

0x1

Amber

0x2

Green

0x3

Undefined
0000
Port test control
Any value other than 0000 indicates that the port is operating in test mode.

19:16 PTC3_0

R/W

The FORCE_ENABLE_FS and FORCE ENABLE_LS are extensions to the
test mode support specified in the EHCI specification. Writing the PTC field
to any of the FORCE_ENABLE_{HS/FS/LS} values will force the port into
the connected and enabled state at the selected speed. Writing the PTC
field back to TEST_MODE_DISABLE will allow the port state machines to
progress normally from that point. Values 0x8 to 0xF are reserved.

20

0x0

TEST_MODE_DISABLE

0x1

J_STATE

0x2

K_STATE

0x3

SE0 (host)/NAK (device)

0x4

Packet

0x5

FORCE_ENABLE_HS

0x6

FORCE_ENABLE_FS

0x7

FORCE_ENABLE_LS

WKCN

Wake on connect enable (WKCNNT_E)

0

R/W

This bit is 0 if PP (Port Power bit) is 0

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0

Disables the port to wake up on device connects.

1

Writing this bit to a one enables the port to be sensitive to device connects
as wake-up events.

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Chapter 26: LPC43xx/LPC43Sxx USB1 Host/Device controller

Table 551. Port Status and Control register in host mode (PORTSC1_H - address 0x4000 7184) bit description
…continued

Bit

Symbol

21

WKDC

Value Description
Wake on disconnect enable (WKDSCNNT_E)

Reset
value

Access

0

R/W

0

R/W

0

R/W

0

R/W

0

RO

This bit is 0 if PP (Port Power bit) is 0.

22

23

0

Disables the port to wake up on device disconnects.

1

Writing this bit to a one enables the port to be sensitive to device
disconnects as wake-up events.

WKOC

Wake on over-current enable (WKOC_E)
0

Disables the port to wake up on over-current events.

1

Writing a one to this bit enabled the port to be sensitive to over-current
conditions as wake-up events.

PHCD

PHY low power suspend - clock disable (PLPSCD)
In host mode, the PHY can be put into Low Power Suspend – Clock
Disable when the downstream device has been put into suspend mode or
when no downstream device is connected. Low power suspend is
completely under the control of software.

24

25

0

Writing a 0 enables the PHY clock. Reading a 0 indicates the status of the
PHY clock (enabled).

1

Writing a 1 disables the PHY clock. Reading a 1 indicates the status of the
PHY clock (disabled).

PFSC

-

Port force full speed connect
0

Port connects at any speed.

1

Writing this bit to a 1 will force the port to only connect at Full Speed. It
disables the chirp sequence that allows the port to identify itself as High
Speed. This is useful for testing FS configurations with a HS host, hub or
device.

-

Reserved

27:26 PSPD

Port speed
This register field indicates the speed at which the port is operating. For HS
mode operation in the host controller and HS/FS operation in the device
controller the port routing steers data to the Protocol engine. For FS and
LS mode operation in the host controller, the port routing steers data to the
Protocol Engine w/ Embedded Transaction Translator.

29:28 -

0x0

Full-speed

0x1

Low-speed

0x2

High-speed

-

Reserved

-

-

Parallel transceiver select. All other values are reserved.

-

R/W

31:30 PTS

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0x2

ULPI

0x3

Serial/ 1.1 PHY (Full-speed only)

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Chapter 26: LPC43xx/LPC43Sxx USB1 Host/Device controller

Table 552. Port states as described by the PE and SUSP bits in the PORTSC1 register
PE bit

SUSP bit

Port state

0

0 or 1

disabled

1

0

enabled

1

1

suspend

26.6.16 USB Mode register (USBMODE)
The USBMODE register sets the USB mode for the USB controller. The possible modes
are Device, Host, and Idle mode.

26.6.16.1 Device mode
Table 553. USB Mode register in device mode (USBMODE_D - address 0x4000 71A8) bit description
Bit

Symbol Value

Description

Reset
value

Access

1:0

CM1_0

Controller mode

00

R/ WO

0

R/W

0

R/W

The controller defaults to an idle state and needs to be initialized to the
desired operating mode after reset. This register can only be written once
after reset. If it is necessary to switch modes, software must reset the
controller by writing to the RESET bit in the USBCMD register before
reprogramming this register.

2

0x0

Idle

0x1

Reserved

0x2

Device controller

0x3

Host controller

ES

Endian select
This bit can change the byte ordering of the transfer buffers to match the
host microprocessor bus architecture. The bit fields in the microprocessor
interface and the DMA data structures (including the setup buffer within the
device QH) are unaffected by the value of this bit, because they are based
upon 32-bit words.

3

0

Little endian: first byte referenced in least significant byte of 32-bit word.

1

Big endian: first byte referenced in most significant byte of 32-bit word.

SLOM

Setup Lockout mode
In device mode, this bit controls behavior of the setup lock mechanism. See
Section 25.10.8.

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0

Setup Lockouts on

1

Setup Lockouts Off (DCD requires the use of Setup Buffer Tripwire in
USBCMD)

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Chapter 26: LPC43xx/LPC43Sxx USB1 Host/Device controller

Table 553. USB Mode register in device mode (USBMODE_D - address 0x4000 71A8) bit description …continued
Bit

Symbol Value

4

SDIS

Description

Reset
value

Access

Stream disable mode

0

R/W

0

-

Remark: The use of this feature substantially limits the overall USB
performance that can be achieved.
0

Not disabled

1

Disabled.
Setting this bit to one disables double priming on both RX and TX for low
bandwidth systems. This mode ensures that when the RX and TX buffers
are sufficient to contain an entire packet that the standard double buffering
scheme is disabled to prevent overruns/underruns in bandwidth limited
systems. Note: In High Speed Mode, all packets received will be responded
to with a NYET handshake when stream disable is active.

5

-

31:6

-

Not used in device mode.
-

Reserved

26.6.16.2 Host mode
Table 554. USB Mode register in host mode (USBMODE_H - address 0x4000 71A8) bit description
Bit

Symbol Value

Description

Reset
value

Access

1:0

CM1_0

Controller mode

00

R/ WO

0

R/W

0

-

The controller defaults to an idle state and needs to be initialized to the
desired operating mode after reset. This register can only be written once
after reset. If it is necessary to switch modes, software must reset the
controller by writing to the RESET bit in the USBCMD register before
reprogramming this register.

2

0x0

Idle

0x1

Reserved

0x2

Device controller

0x3

Host controller

ES

Endian select
This bit can change the byte ordering of the transfer buffers. The bit fields in
the microprocessor interface and the DMA data structures (including the
setup buffer within the device QH) are unaffected by the value of this bit,
because they are based upon 32-bit words.

3

-

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0

Little endian: first byte referenced in least significant byte of 32-bit word.

1

Big endian: first byte referenced in most significant byte of 32-bit word.
Not used in host mode

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Chapter 26: LPC43xx/LPC43Sxx USB1 Host/Device controller

Table 554. USB Mode register in host mode (USBMODE_H - address 0x4000 71A8) bit description …continued
Bit

Symbol Value

4

SDIS

Description

Reset
value

Access

Stream disable mode

0

R/W

0

R/WO

-

-

Remark: The use of this feature substantially limits the overall USB
performance that can be achieved.
0

Not disabled

1

Disabled.
Setting to a 1 ensures that overruns/underruns of the latency FIFO are
eliminated for low bandwidth systems where the RX and TX buffers are
sufficient to contain the entire packet. Enabling stream disable also has the
effect of ensuring the TX latency is filled to capacity before the packet is
launched onto the USB.
Note: Time duration to pre-fill the FIFO becomes significant when stream
disable is active. See TXFILLTUNING to characterize the adjustments
needed for the scheduler when using this feature.

5

31:6

VBPS

-

VBUS power select
0

vbus_pwr_select is set LOW.

1

vbus_pwr_select is set HIGH

-

Reserved

26.6.17 USB Endpoint Setup Status register (ENDPSETUPSTAT)
Table 555. USB Endpoint Setup Status register (ENDPTSETUPSTAT - address 0x4000 71AC) bit description
Bit

Symbol

Description

Reset
value

Access

3:0

ENDPT
SETUP
STAT

Setup endpoint status for logical endpoints.

0

R/WC

-

Reserved

-

-

31:4

For every setup transaction that is received, a corresponding bit in this register
is set to one. Software must clear or acknowledge the setup transfer by writing
a one to a respective bit after it has read the setup data from Queue head. The
response to a setup packet as in the order of operations and total response
time is crucial to limit bus time outs while the setup lockout mechanism is
engaged.

26.6.18 USB Endpoint Prime register (ENDPTPRIME)
For each endpoint, software should write a one to the corresponding bit whenever posting
a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin
parsing for a new transfer descriptor from the queue head and prepare a receive buffer.
Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed.
Remark: These bits will be momentarily set by hardware during hardware endpoint
re-priming operations when a dTD is retired and the dQH is updated.

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Chapter 26: LPC43xx/LPC43Sxx USB1 Host/Device controller

Table 556. USB Endpoint Prime register (ENDPTPRIME - address 0x4000 71B0) bit description
Bit

Symbol

Description

Reset
value

3:0

PERB

Prime endpoint receive buffer for physical OUT endpoints.
0
For each OUT endpoint, a corresponding bit is set to 1 by software to request a
buffer be prepared for a receive operation for when a USB host initiates a USB
OUT transaction. Software should write a one to the corresponding bit
whenever posting a new transfer descriptor to an endpoint. Hardware will
automatically use this bit to begin parsing for a new transfer descriptor from the
queue head and prepare a receive buffer. Hardware will clear this bit when the
associated endpoint(s) is (are) successfully primed.

Access
R/WS

PERB0 = endpoint 0
...
PERB3 = endpoint 3
15:4

-

19:16 PETB

Reserved

-

-

Prime endpoint transmit buffer for physical IN endpoints.

0

R/WS

-

-

For each IN endpoint a corresponding bit is set to one by software to request a
buffer be prepared for a transmit operation in order to respond to a USB
IN/INTERRUPT transaction. Software should write a one to the corresponding
bit when posting a new transfer descriptor to an endpoint. Hardware will
automatically use this bit to begin parsing for a new transfer descriptor from the
queue head and prepare a transmit buffer. Hardware will clear this bit when the
associated endpoint(s) is (are) successfully primed.
PETB0 = endpoint 0
...
PETB3 = endpoint 3
31:20 -

Reserved

26.6.19 USB Endpoint Flush register (ENDPTFLUSH)
Writing a one to a bit(s) in this register will cause the associated endpoint(s) to clear any
primed buffers. If a packet is in progress for one of the associated endpoints, then that
transfer will continue until completion. Hardware will clear this register after the endpoint
flush operation is successful.
Table 557. USB Endpoint Flush register (ENDPTFLUSH - address 0x4000 71B4) bit description
Bit

Symbol

Description

Reset
value

Access

3:0

FERB

Flush endpoint receive buffer for physical OUT endpoints.

0

R/WC

Writing a one to a bit(s) will clear any primed buffers.
FERB0 = endpoint 0
...
FERB3 = endpoint 3

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Chapter 26: LPC43xx/LPC43Sxx USB1 Host/Device controller

Table 557. USB Endpoint Flush register (ENDPTFLUSH - address 0x4000 71B4) bit description
Bit

Symbol

Description

Reset
value

Access

15:4

-

Reserved

-

-

Flush endpoint transmit buffer for physical IN endpoints.

0

R/WC

-

-

19:16 FETB

Writing a one to a bit(s) will clear any primed buffers.
FETB0 = endpoint 0
...
FETB3 = endpoint 3
31:20 -

Reserved

26.6.20 USB Endpoint Status register (ENDPTSTAT)
One bit for each endpoint indicates status of the respective endpoint buffer. This bit is set
by hardware as a response to receiving a command from a corresponding bit in the
ENDPTPRIME register. There will always be a delay between setting a bit in the
ENDPTPRIME register and endpoint indicating ready. This delay time varies based upon
the current USB traffic and the number of bits set in the ENDPTPRIME register. Buffer
ready is cleared by USB reset, by the USB DMA system, or through the ENDPTFLUSH
register.
Remark: These bits will be momentarily cleared by hardware during hardware endpoint
re-priming operations when a dTD is retired and the dQH is updated.
Table 558. USB Endpoint Status register (ENDPTSTAT - address 0x4000 71B8) bit description
Bit

Symbol

Description

Reset
value

Access

3:0

ERBR

Endpoint receive buffer ready for physical OUT endpoints.

0

RO

This bit is set to 1 by hardware as a response to receiving a command from a
corresponding bit in the ENDPTPRIME register.
ERBR0 = endpoint 0
...
ERBR3 = endpoint 3
15:4

-

19:16 ETBR

Reserved

-

-

Endpoint transmit buffer ready for physical IN endpoints 3 to 0.

0

RO

-

-

This bit is set to 1 by hardware as a response to receiving a command from a
corresponding bit in the ENDPTPRIME register.
ETBR0 = endpoint 0
...
ETBR3 = endpoint 3
31:20 -

Reserved

26.6.21 USB Endpoint Complete register (ENDPTCOMPLETE)
Each bit in this register indicates that a received/transmit event occurred and software
should read the corresponding endpoint queue to determine the transfer status. If the
corresponding IOC bit is set in the Transfer Descriptor, then this bit will be set
simultaneously with the USBINT.

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Chapter 26: LPC43xx/LPC43Sxx USB1 Host/Device controller

Writing a one will clear the corresponding bit in this register.
Table 559. USB Endpoint Complete register (ENDPTCOMPLETE - address 0x4000 71BC) bit description
Bit

Symbol

Description

Reset
value

Access

3:0

ERCE

Endpoint receive complete event for physical OUT endpoints.

0

R/WC

Reserved

-

-

Endpoint transmit complete event for physical IN endpoints.

0

R/WC

-

-

This bit is set to 1 by hardware when receive event (OUT) occurred.
ERCE0 = endpoint 0
...
ERCE3 = endpoint 3
15:4

-

19:16 ETCE

This bit is set to 1 by hardware when a transmit event (IN/INTERRUPT)
occurred.
ETCE0 = endpoint 0
...
ETCE3 = endpoint 3
31:20 -

Reserved

26.6.22 USB Endpoint 0 Control register (ENDPTCTRL0)
This register initializes endpoint 0 for control transfer. Endpoint 0 is always a control
endpoint.
Table 560. USB Endpoint 0 Control register (ENDPTCTRL0 - address 0x4000 71C0) bit description
Bit

Symbol

0

RXS

Value

Description

Reset
value

Access

Rx endpoint stall

0

R/W

0

R/W

0

Endpoint ok.

1

Endpoint stalled
Software can write a one to this bit to force the endpoint to return a
STALL handshake to the Host. It will continue returning STALL until
the bit is cleared by software, or it will automatically be cleared upon
receipt of a new SETUP request.
After receiving a SETUP request, this bit will continue to be cleared
by hardware until the associated ENDSETUPSTAT bit is cleared.[1]

1

-

-

Reserved

3:2

RXT

0x0

Endpoint type
Endpoint 0 is always a control endpoint.

6:4

-

-

Reserved

-

-

7

RXE

1

Rx endpoint enable

1

RO

-

-

Endpoint enabled. Control endpoint 0 is always enabled. This bit is
always 1.
15:8

-

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-

Reserved

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Chapter 26: LPC43xx/LPC43Sxx USB1 Host/Device controller

Table 560. USB Endpoint 0 Control register (ENDPTCTRL0 - address 0x4000 71C0) bit description …continued
Bit

Symbol

16

TXS

Value

Description

Reset
value

Tx endpoint stall
0

Endpoint ok.

1

Endpoint stalled

Access
R/W

Software can write a one to this bit to force the endpoint to return a
STALL handshake to the Host. It will continue returning STALL until
the bit is cleared by software, or it will automatically be cleared upon
receipt of a new SETUP request.
After receiving a SETUP request, this bit will continue to be cleared
by hardware until the associated ENDSETUPSTAT bit is cleared.[1]
17

-

-

19:18 TXT

Reserved

0x0

Endpoint type

0

RO

1

RO

Endpoint 0 is always a control endpoint.
22:20 -

-

Reserved

23

1

Tx endpoint enable

TXE

Endpoint enabled. Control endpoint 0 is always enabled. This bit is
always 1.
31:24 [1]

-

Reserved

There is a slight delay (50 clocks max) between the ENPTSETUPSTAT being cleared and hardware continuing to clear this bit. In most
systems it is unlikely that the DCD software will observe this delay. However, should the DCD notice that the stall bit is not set after
writing a one to it, software should continually write this stall bit until it is set or until a new setup has been received by checking the
associated ENDPTSETUPSTAT bit.

26.6.23 Endpoint 1 to 3 control registers
Each endpoint that is not a control endpoint has its own register to set the endpoint type
and enable or disable the endpoint.
Remark: The reset value for all endpoint types is the control endpoint. If one endpoint
direction is enabled and the paired endpoint of opposite direction is disabled, then the
endpoint type of the unused direction must be changed from the control type to any other
type (e.g. bulk). Leaving an unconfigured endpoint control will cause undefined behavior
for the data PID tracking on the active endpoint.
Table 561. USB Endpoint 1 to 3 control registers (ENDPTCTRL - address 0x4000 71C4 (ENDPTCTRL1) to
0x4000 71CC (ENDPTCTRL3)) bit description
Bit

Symbol

0

RXS

Value

0

Description

Reset
value

Access

Rx endpoint stall

0

R/W

Endpoint ok.
This bit will be cleared automatically upon receipt of a SETUP
request if this Endpoint is configured as a Control Endpoint and this
bit will continue to be cleared by hardware until the associated
ENDPTSETUPSTAT bit is cleared.

1

Endpoint stalled
Software can write a one to this bit to force the endpoint to return a
STALL handshake to the Host. It will continue returning STALL until
the bit is cleared by software, or it will automatically be cleared upon
receipt of a new SETUP request.[1]

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Chapter 26: LPC43xx/LPC43Sxx USB1 Host/Device controller

Table 561. USB Endpoint 1 to 3 control registers (ENDPTCTRL - address 0x4000 71C4 (ENDPTCTRL1) to
0x4000 71CC (ENDPTCTRL3)) bit description …continued
Bit

Symbol

Value

Description

Reset
value

Access

1

-

Reserved

0

R/W

3:2

RXT

Endpoint type

00

R/W

0

R/W

0

WS

0

R/W

0

R/W

Reserved

0

-

Tx endpoint type

00

R/W

4

-

5

RXI

0x0

Control

0x1

Isochronous

0x2

Bulk

0x3

Interrupt

-

Reserved
Rx data toggle inhibit
This bit is only used for test and should always be written as zero.
Writing a one to this bit will cause this endpoint to ignore the data
toggle sequence and always accept data packets regardless of their
data PID.

6

0

Disabled

1

Enabled

RXR

Rx data toggle reset
Write 1 to reset the PID sequence.
Whenever a configuration event is received for this Endpoint,
software must write a one to this bit in order to synchronize the data
PIDs between the host and device.

7

RXE

Rx endpoint enable
Remark: An endpoint should be enabled only after it has been
configured.

15:8

-

16

TXS

0

Endpoint disabled.

1

Endpoint enabled.

-

Reserved
Tx endpoint stall

0

Endpoint ok.
This bit will be cleared automatically upon receipt of a SETUP
request if this Endpoint is configured as a Control Endpoint, and this
bit will continue to be cleared by hardware until the associated
ENDPTSETUPSTAT bit is cleared.

1

Endpoint stalled
Software can write a one to this bit to force the endpoint to return a
STALL handshake to the Host. It will continue returning STALL until
the bit is cleared by software, or it will automatically be cleared upon
receipt of a new SETUP request.[1]

17

-

-

19:18 TXT

20

-

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0x0

Control

0x1

Isochronous

0x2

Bulk

0x3

Interrupt

-

Reserved
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Chapter 26: LPC43xx/LPC43Sxx USB1 Host/Device controller

Table 561. USB Endpoint 1 to 3 control registers (ENDPTCTRL - address 0x4000 71C4 (ENDPTCTRL1) to
0x4000 71CC (ENDPTCTRL3)) bit description …continued
Bit

Symbol

21

TXI

Value

Description

Reset
value

Access

Tx data toggle inhibit

0

R/W

1

WS

0

R/W

This bit is only used for test and should always be written as zero.
Writing a one to this bit will cause this endpoint to ignore the data
toggle sequence and always accept data packets regardless of their
data PID.

22

0

Enabled

1

Disabled

TXR

Tx data toggle reset
Write 1 to reset the PID sequence.
Whenever a configuration event is received for this Endpoint,
software must write a one to this bit in order to synchronize the data
PID’s between the host and device.

23

TXE

Tx endpoint enable
Remark: An endpoint should be enabled only after it has been
configured
0

31:24 [1]

Endpoint disabled.

1

Endpoint enabled.

-

Reserved

0

For control endpoints only: There is a slight delay (50 clocks max) between the ENPTSETUPSTAT being cleared and hardware
continuing to clear this bit. In most systems it is unlikely that the DCD software will observe this delay. However, should the DCD notice
that the stall bit is not set after writing a one to it, software should continually write this stall bit until it is set or until a new setup has been
received by checking the associated ENDPTSETUPSTAT bit.

26.7 Functional description
For details on the device data structures, see Section 25.9. For the device operational
model, see Section 25.10.

26.7.1 Susp_CTRL module
The SUSP_CTRL module implements the power management logic of USB block. It
controls the suspend input of the transceiver. Asserting this suspend signal
(PORTSC1.PHCD bit) will put the transceiver in suspend mode and the 60 MHz clock will
be switched off.
In suspend mode, the transceiver will raise an output signal. For USB1, this signal is not
connected to any register.
The SUSP_CTRL module also generates an output signal indicating whether the AHB
clock is needed or not. If not, the AHB clock is allowed to be switched off or reduced in
frequency in order to save power.
For USB1, this signal is connected to event #10 (USB1_L) in the event router (see
Table 82). Software should check for this signal to be low before stopping the USB PLL
and putting the chip in low power mode. Note that the event router block doesn't have a

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raw pin status register hence LOW level detection should be configured for this pin to
detect when to turn the PLL off. Similarly, to detect resume signaling to leave low power
state, software should configure this pin to detect a HIGH level in the event router.
The core will enter the low power state if:

• Software sets the PORTSC1.PHCD bit.
When operating in host mode, the core will leave the low power state on one of the
following conditions:

•
•
•
•
•
•
•

software clears the PORTSC1.PHCD bit
a device is connected and the PORTSC1.WKCN bit is set
a device is disconnected an the PORTSC1.WKDC bit is set
an over-current condition occurs and the PORTSC1.WKOC bit is set
a remote wake-up from the attached device occurs (when USB bus was in suspend)
a change on vbusvalid occurs (= VBUS threshold at 4.4 V is crossed)
a change on bvalid occurs (=VBUS threshold at 4.0 V is crossed).

When operating in device mode, the core will leave the low power state on one of the
following conditions:

•
•
•
•

software clears the PORTSC1.PHCD bit.
a change on the USB data lines (dp/dm) occurs.
a change on vbusvalid occurs (= VBUS threshold at 4.4 V is crossed).
a change on bvalid occurs (= VBUS threshold at 4.0 V is crossed).

The vbusvalid and bvalid signals coming from the transceiver are not filtered in the
SUSP_CTRL module. Any change on those signals will cause a wake-up event.

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27.1 How to read this chapter
The USB ROM API is available on parts LPC4350/30/20 and LPC43S50/S30/S20.

27.2 Introduction
The boot ROM contains a USB driver to simplify the USB application development. The
USB driver implements the Communication Device Class (CDC), the Human Interface
Device (HID), and the Mass Storage Device (MSC) device class. The USB on-chip drivers
support composite device.

27.3 USB driver functions
The USB device driver ROM API consists of the following modules:

• Communication Device Class (CDC) function driver. This module contains an internal
implementation of the USB CDC Class. User applications can use this class driver
instead of implementing the CDC-ACM class manually via the low-level USBD_HW
and USBD_Core APIs. This module is designed to simplify the user code by exposing
only the required interface needed to interface with Devices using the USB CDC-ACM
Class.
– Communication Device Class function driver initialization parameter data structure
(Table 588 “USBD_CDC_API class structure”).
– CDC class API functions structure. This module exposes functions which interact
directly with USB device controller hardware (Table 588 “USBD_CDC_API class
structure”).

• USB core layer
– struct (Table 585 “_WB_T class structure”)
– union (Table 562 “__WORD_BYTE class structure”)
– struct (Table 563 “_BM_T class structure”)
– struct (Table 576 “_REQUEST_TYPE class structure”)
– struct (Table 583 “_USB_SETUP_PACKET class structure”)
– struct (Table 579 “_USB_DEVICE_QUALIFIER_DESCRIPTOR class structure”)
– struct USB device descriptor
– struct (Table 579 “_USB_DEVICE_QUALIFIER_DESCRIPTOR class structure”)
– struct USB configuration descriptor
– struct (Table 581 “_USB_INTERFACE_DESCRIPTOR class structure”)
– struct USB endpoint descriptor
– struct (Table 584 “_USB_STRING_DESCRIPTOR class structure”)
– struct (Table 577 “_USB_COMMON_DESCRIPTOR class structure”)
– struct (Table 582 “_USB_OTHER_SPEED_CONFIGURATION class structure”)
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– USB descriptors data structure (Table 578 “_USB_CORE_DESCS_T class
structure”)
– USB device stack initialization parameter data structure (Table 587
“USBD_API_INIT_PARAM class structure”).
– USB device stack core API functions structure (Table 590 “USBD_CORE_API
class structure”).

• Device Firmware Upgrade (DFU) class function driver
– DFU descriptors data structure (Table 592 “USBD_DFU_INIT_PARAM class
structure”).
– DFU class API functions structure. This module exposes functions which interact
directly with the USB device controller hardware (Table 591 “USBD_DFU_API
class structure”).

• HID class function driver
– struct (Table 571 “_HID_DESCRIPTOR class structure”).
– struct (Table 573 “_HID_REPORT_T class structure”).
– USB descriptors data structure (Table 594 “USBD_HID_INIT_PARAM class
structure”).
– HID class API functions structure. This structure contains pointers to all the
functions exposed by the HID function driver module (Table 595 “USBD_HW_API
class structure”).

• USB device controller driver
– Hardware API functions structure. This module exposes functions which interact
directly with the USB device controller hardware (Table 595 “USBD_HW_API class
structure”).

• Mass Storage Class (MSC) function driver
– Mass Storage Class function driver initialization parameter data structure
(Table 597).
– MSC class API functions structure. This module exposes functions which interact
directly with the USB device controller hardware (Table 596).

27.4 Calling the USB device driver
A fixed location in ROM contains a pointer to the ROM driver table i.e. 0x1FFF 1FF8. The
ROM driver table contains a pointer to the USB driver table. Pointers to the various USB
driver functions are stored in this table. USB driver functions can be called by using a C
structure. Figure 77 illustrates the pointer mechanism used to access the on-chip USB
driver.
typedef struct USBD_API
{
const USBD_HW_API_T* hw;
const USBD_CORE_API_T* core;
const USBD_MSC_API_T* msc;
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const USBD_DFU_API_T* dfu;
const USBD_HID_API_T* hid;
const USBD_CDC_API_T* cdc;
const uint32_t* reserved6;
const uint32_t version;
} USBD_API_T;

Ptr to USB ROM Driver table
0x1040 011C

Device 1
Ptr to Function 0
Ptr to Function 1
Ptr to Function 2

…
Ptr to Function n
ROM Driver Table
0x1040 0100
Reserved
0x1040 0104
Ptr to Device Table 1

USB API

0x1040 0108

USB hardware function table
hw

Ptr to Device Table 2
0x1040 010C

core

…

0x1040 011C

msc
Ptr to USB ROM Driver table
dfu
hid
cdc

USB core function table
USB MSC function table
USB DFU function table
USB HID function table
USB CDC function table

Fig 77. USB device driver pointer structure

27.5 USB API
27.5.1 __WORD_BYTE
Table 562. __WORD_BYTE class structure
Member

Description

W

uint16_t __WORD_BYTE::W
data member to do 16 bit access

WB

WB_TWB_T __WORD_BYTE::WB
data member to do 8 bit access

27.5.2 _BM_T

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Table 563. _BM_T class structure
Member

Description

Recipient

uint8_t _BM_T::Recipient
Recipient type.

Type

uint8_t _BM_T::Type
Request type.

Dir

uint8_t _BM_T::Dir
Direction type.

27.5.3 _CDC_ABSTRACT_CONTROL_MANAGEMENT_DESCRIPTOR
Table 564. _CDC_ABSTRACT_CONTROL_MANAGEMENT_DESCRIPTOR class structure
Member

Description

bFunctionLength

uint8_t _CDC_ABSTRACT_CONTROL_MANAGEMENT_DESCRIPTOR::bFunctionLength

bDescriptorType

uint8_t _CDC_ABSTRACT_CONTROL_MANAGEMENT_DESCRIPTOR::bDescriptorType

bDescriptorSubtype

uint8_t _CDC_ABSTRACT_CONTROL_MANAGEMENT_DESCRIPTOR::bDescriptorSubtype

bmCapabilities

uint8_t _CDC_ABSTRACT_CONTROL_MANAGEMENT_DESCRIPTOR::bmCapabilities

27.5.4 _CDC_CALL_MANAGEMENT_DESCRIPTOR
Table 565. _CDC_CALL_MANAGEMENT_DESCRIPTOR class structure
Member

Description

bFunctionLength

uint8_t _CDC_CALL_MANAGEMENT_DESCRIPTOR::bFunctionLength

bDescriptorType

uint8_t _CDC_CALL_MANAGEMENT_DESCRIPTOR::bDescriptorType

bDescriptorSubtype

uint8_t _CDC_CALL_MANAGEMENT_DESCRIPTOR::bDescriptorSubtype

bmCapabilities

uint8_t _CDC_CALL_MANAGEMENT_DESCRIPTOR::bmCapabilities

bDataInterface

uint8_t _CDC_CALL_MANAGEMENT_DESCRIPTOR::bDataInterface

27.5.5 _CDC_HEADER_DESCRIPTOR
Table 566. _CDC_HEADER_DESCRIPTOR class structure
Member

Description

bFunctionLength

uint8_t _CDC_HEADER_DESCRIPTOR::bFunctionLength

bDescriptorType

uint8_t _CDC_HEADER_DESCRIPTOR::bDescriptorType

bDescriptorSubtype

uint8_t _CDC_HEADER_DESCRIPTOR::bDescriptorSubtype

bcdCDC

uint16_t _CDC_HEADER_DESCRIPTOR::bcdCDC

27.5.6 _CDC_LINE_CODING

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Table 567. _CDC_LINE_CODING class structure
Member

Description

dwDTERate

uint32_t _CDC_LINE_CODING::dwDTERate

bCharFormat

uint8_t _CDC_LINE_CODING::bCharFormat

bParityType

uint8_t _CDC_LINE_CODING::bParityType

bDataBits

uint8_t _CDC_LINE_CODING::bDataBits

27.5.7 _CDC_UNION_1SLAVE_DESCRIPTOR
Table 568. _CDC_UNION_1SLAVE_DESCRIPTOR class structure
Member

Description

sUnion

CDC_UNION_DESCRIPTORCDC_UNION_DESCRIPTOR _CDC_UNION_1SLAVE_DESCRIPTOR::sUnion

bSlaveInterfaces

uint8_t _CDC_UNION_1SLAVE_DESCRIPTOR::bSlaveInterfaces[1][1]

27.5.8 _CDC_UNION_DESCRIPTOR
Table 569. _CDC_UNION_DESCRIPTOR class structure
Member

Description

bFunctionLength

uint8_t _CDC_UNION_DESCRIPTOR::bFunctionLength

bDescriptorType

uint8_t _CDC_UNION_DESCRIPTOR::bDescriptorType

bDescriptorSubtype

uint8_t _CDC_UNION_DESCRIPTOR::bDescriptorSubtype

bMasterInterface

uint8_t _CDC_UNION_DESCRIPTOR::bMasterInterface

27.5.9 _DFU_STATUS
Table 570. _DFU_STATUS class structure
Member

Description

bStatus

uint8_t _DFU_STATUS::bStatus

bwPollTimeout

uint8_t _DFU_STATUS::bwPollTimeout[3][3]

bState

uint8_t _DFU_STATUS::bState

iString

uint8_t _DFU_STATUS::iString

27.5.10 _HID_DESCRIPTOR
HID class-specific HID Descriptor.

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Table 571. _HID_DESCRIPTOR class structure
Member

Description

bLength

uint8_t _HID_DESCRIPTOR::bLength
Size of the descriptor, in bytes.

bDescriptorType

uint8_t _HID_DESCRIPTOR::bDescriptorType
Type of HID descriptor.

bcdHID

uint16_t _HID_DESCRIPTOR::bcdHID
BCD encoded version that the HID descriptor and device complies to.

bCountryCode

uint8_t _HID_DESCRIPTOR::bCountryCode
Country code of the localized device, or zero if universal.

bNumDescriptors

uint8_t _HID_DESCRIPTOR::bNumDescriptors
Total number of HID report descriptors for the interface.

DescriptorList

PRE_PACK struct POST_PACK _HID_DESCRIPTOR::_HID_DESCRIPTOR_LISTPRE_PACK struct POST_PACK
_HID_DESCRIPTOR::_HID_DESCRIPTOR_LIST _HID_DESCRIPTOR::DescriptorList[1][1]
Array of one or more descriptors

27.5.11 _HID_DESCRIPTOR::_HID_DESCRIPTOR_LIST
Table 572. _HID_DESCRIPTOR::_HID_DESCRIPTOR_LIST class structure
Member

Description

bDescriptorType

uint8_t _HID_DESCRIPTOR::_HID_DESCRIPTOR_LIST::bDescriptorType
Type of HID report.

wDescriptorLength

uint16_t _HID_DESCRIPTOR::_HID_DESCRIPTOR_LIST::wDescriptorLength
Length of the associated HID report descriptor, in bytes.

27.5.12 _HID_REPORT_T
HID report descriptor data structure.
Table 573. _HID_REPORT_T class structure
Member

Description

len

uint16_t _HID_REPORT_T::len
Size of the report descriptor in bytes.

idle_time

uint8_t _HID_REPORT_T::idle_time
This value is used by stack to respond to Set_Idle & GET_Idle requests for the specified
report ID. The value of this field specified the rate at which duplicate reports are generated for
the specified Report ID. For example, a device with two input reports could specify an idle
rate of 20 milliseconds for report ID 1 and 500 milliseconds for report ID 2.

__pad

uint8_t _HID_REPORT_T::__pad
Padding space.

desc

uint8_t * _HID_REPORT_T::desc
Report descriptor.

27.5.13 _MSC_CBW
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Table 574. _MSC_CBW class structure
Member

Description

dSignature

uint32_t _MSC_CBW::dSignature

dTag

uint32_t _MSC_CBW::dTag

dDataLength

uint32_t _MSC_CBW::dDataLength

bmFlags

uint8_t _MSC_CBW::bmFlags

bLUN

uint8_t _MSC_CBW::bLUN

bCBLength

uint8_t _MSC_CBW::bCBLength

CB

uint8_t _MSC_CBW::CB[16][16]

27.5.14 _MSC_CSW
Table 575. _MSC_CSW class structure
Member

Description

dSignature

uint32_t _MSC_CSW::dSignature

dTag

uint32_t _MSC_CSW::dTag

dDataResidue

uint32_t _MSC_CSW::dDataResidue

bStatus

uint8_t _MSC_CSW::bStatus

27.5.15 _REQUEST_TYPE
Table 576. _REQUEST_TYPE class structure
Member

Description

B

uint8_t _REQUEST_TYPE::B
byte wide access member

BM

BM_TBM_T _REQUEST_TYPE::BM
bitfield structure access member

27.5.16 _USB_COMMON_DESCRIPTOR
Table 577. _USB_COMMON_DESCRIPTOR class structure
Member

Description

bLength

uint8_t _USB_COMMON_DESCRIPTOR::bLength
Size of this descriptor in bytes

bDescriptorType

uint8_t _USB_COMMON_DESCRIPTOR::bDescriptorType
Descriptor Type

27.5.17 _USB_CORE_DESCS_T
USB descriptors data structure.

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Table 578. _USB_CORE_DESCS_T class structure
Member

Description

device_desc

uint8_t * _USB_CORE_DESCS_T::device_desc
Pointer to USB device descriptor

string_desc

uint8_t * _USB_CORE_DESCS_T::string_desc
Pointer to array of USB string descriptors

full_speed_desc

uint8_t * _USB_CORE_DESCS_T::full_speed_desc
Pointer to USB device configuration descriptor when device is operating in full speed mode.

high_speed_desc

uint8_t * _USB_CORE_DESCS_T::high_speed_desc
Pointer to USB device configuration descriptor when device is operating in high speed mode.
For full-speed only implementation this pointer should be same as full_speed_desc.

device_qualifier

uint8_t * _USB_CORE_DESCS_T::device_qualifier
Pointer to USB device qualifier descriptor. For full-speed only implementation this pointer
should be set to null (0).

27.5.18 _USB_DEVICE_QUALIFIER_DESCRIPTOR
Table 579. _USB_DEVICE_QUALIFIER_DESCRIPTOR class structure
Member

Description

bLength

uint8_t _USB_DEVICE_QUALIFIER_DESCRIPTOR::bLength
Size of descriptor

bDescriptorType

uint8_t _USB_DEVICE_QUALIFIER_DESCRIPTOR::bDescriptorType
Device Qualifier Type

bcdUSB

uint16_t _USB_DEVICE_QUALIFIER_DESCRIPTOR::bcdUSB
USB specification version number (e.g., 0200H for V2.00)

bDeviceClass

uint8_t _USB_DEVICE_QUALIFIER_DESCRIPTOR::bDeviceClass
Class Code

bDeviceSubClass

uint8_t _USB_DEVICE_QUALIFIER_DESCRIPTOR::bDeviceSubClass
SubClass Code

bDeviceProtocol

uint8_t _USB_DEVICE_QUALIFIER_DESCRIPTOR::bDeviceProtocol
Protocol Code

bMaxPacketSize0

uint8_t _USB_DEVICE_QUALIFIER_DESCRIPTOR::bMaxPacketSize0
Maximum packet size for other speed

bNumConfigurations

uint8_t _USB_DEVICE_QUALIFIER_DESCRIPTOR::bNumConfigurations
Number of Other-speed Configurations

bReserved

uint8_t _USB_DEVICE_QUALIFIER_DESCRIPTOR::bReserved
Reserved for future use, must be zero

27.5.19 _USB_DFU_FUNC_DESCRIPTOR

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Table 580. _USB_DFU_FUNC_DESCRIPTOR class structure
Member

Description

bLength

uint8_t _USB_DFU_FUNC_DESCRIPTOR::bLength

bDescriptorType

uint8_t _USB_DFU_FUNC_DESCRIPTOR::bDescriptorType

bmAttributes

uint8_t _USB_DFU_FUNC_DESCRIPTOR::bmAttributes

wDetachTimeOut

uint16_t _USB_DFU_FUNC_DESCRIPTOR::wDetachTimeOut

wTransferSize

uint16_t _USB_DFU_FUNC_DESCRIPTOR::wTransferSize

bcdDFUVersion

uint16_t _USB_DFU_FUNC_DESCRIPTOR::bcdDFUVersion

27.5.20 _USB_INTERFACE_DESCRIPTOR
Table 581. _USB_INTERFACE_DESCRIPTOR class structure
Member

Description

bLength

uint8_t _USB_INTERFACE_DESCRIPTOR::bLength
Size of this descriptor in bytes

bDescriptorType

uint8_t _USB_INTERFACE_DESCRIPTOR::bDescriptorType
INTERFACE Descriptor Type

bInterfaceNumber

uint8_t _USB_INTERFACE_DESCRIPTOR::bInterfaceNumber
Number of this interface. Zero-based value identifying the index in the array of concurrent
interfaces supported by this configuration.

bAlternateSetting

uint8_t _USB_INTERFACE_DESCRIPTOR::bAlternateSetting
Value used to select this alternate setting for the interface identified in the prior field

bNumEndpoints

uint8_t _USB_INTERFACE_DESCRIPTOR::bNumEndpoints
Number of endpoints used by this interface (excluding endpoint zero). If this value is zero, this
interface only uses the Default Control Pipe.

bInterfaceClass

uint8_t _USB_INTERFACE_DESCRIPTOR::bInterfaceClass
Class code (assigned by the USB-IF).

bInterfaceSubClass

uint8_t _USB_INTERFACE_DESCRIPTOR::bInterfaceSubClass
Subclass code (assigned by the USB-IF).

bInterfaceProtocol

uint8_t _USB_INTERFACE_DESCRIPTOR::bInterfaceProtocol
Protocol code (assigned by the USB).

iInterface

uint8_t _USB_INTERFACE_DESCRIPTOR::iInterface
Index of string descriptor describing this interface

27.5.21 _USB_OTHER_SPEED_CONFIGURATION

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Table 582. _USB_OTHER_SPEED_CONFIGURATION class structure
Member

Description

bLength

uint8_t _USB_OTHER_SPEED_CONFIGURATION::bLength
Size of descriptor

bDescriptorType

uint8_t _USB_OTHER_SPEED_CONFIGURATION::bDescriptorType
Other_speed_Configuration Type

wTotalLength

uint16_t _USB_OTHER_SPEED_CONFIGURATION::wTotalLength
Total length of data returned

bNumInterfaces

uint8_t _USB_OTHER_SPEED_CONFIGURATION::bNumInterfaces
Number of interfaces supported by this speed configuration

bConfigurationValue

uint8_t _USB_OTHER_SPEED_CONFIGURATION::bConfigurationValue
Value to use to select configuration

IConfiguration

uint8_t _USB_OTHER_SPEED_CONFIGURATION::IConfiguration
Index of string descriptor

bmAttributes

uint8_t _USB_OTHER_SPEED_CONFIGURATION::bmAttributes
Same as Configuration descriptor

bMaxPower

uint8_t _USB_OTHER_SPEED_CONFIGURATION::bMaxPower
Same as Configuration descriptor

27.5.22 _USB_SETUP_PACKET
Table 583. _USB_SETUP_PACKET class structure
Member

Description

bmRequestType

REQUEST_TYPE _USB_SETUP_PACKET::bmRequestType
This bit-mapped field identifies the characteristics of the specific request.
_BM_T.

bRequest

uint8_t _USB_SETUP_PACKET::bRequest
This field specifies the particular request. The Type bits in the bmRequestType field modify
the meaning of this field.
USBD_REQUEST.

wValue

WORD_BYTE _USB_SETUP_PACKET::wValue
Used to pass a parameter to the device, specific to the request.

wIndex

WORD_BYTE _USB_SETUP_PACKET::wIndex
Used to pass a parameter to the device, specific to the request. The wIndex field is often used
in requests to specify an endpoint or an interface.

wLength

uint16_t _USB_SETUP_PACKET::wLength
This field specifies the length of the data transferred during the second phase of the control
transfer.

27.5.23 _USB_STRING_DESCRIPTOR

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Chapter 27: LPC43xx/LPC43Sxx USB API

Table 584. _USB_STRING_DESCRIPTOR class structure
Member

Description

bLength

uint8_t _USB_STRING_DESCRIPTOR::bLength
Size of this descriptor in bytes

bDescriptorType

uint8_t _USB_STRING_DESCRIPTOR::bDescriptorType
STRING Descriptor Type

bString

uint16_t _USB_STRING_DESCRIPTOR::bString
UNICODE encoded string

27.5.24 _WB_T
Table 585. _WB_T class structure
Member

Description

L

uint8_t _WB_T::L
lower byte

H

uint8_t _WB_T::H
upper byte

27.5.25 USBD_API
Main USBD API functions structure.This structure contains pointer to various USB Device
stack's sub-module function tables. This structure is used as main entry point to access
various methods (grouped in sub-modules) exposed by ROM based USB device stack.
Table 586. USBD_API class structure
Member

Description

hw

const USBD_HW_API_T* USBD_API::hw
Pointer to function table which exposes functions which interact directly with USB device stack's core
layer.

core

const USBD_CORE_API_T* USBD_API::core
Pointer to function table which exposes functions which interact directly with USB device controller
hardware.

msc

const USBD_MSC_API_T* USBD_API::msc
Pointer to function table which exposes functions provided by MSC function driver module.

dfu

const USBD_DFU_API_T* USBD_API::dfu
Pointer to function table which exposes functions provided by DFU function driver module.

hid

const USBD_HID_API_T* USBD_API::hid
Pointer to function table which exposes functions provided by HID function driver module.

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Table 586. USBD_API class structure
Member

Description

cdc

const USBD_CDC_API_T* USBD_API::cdc
Pointer to function table which exposes functions provided by CDC-ACM function driver module.

reserved6

const uint32_t* USBD_API::reserved6
Reserved for future function driver module.

version

const uint32_t USBD_API::version
Version identifier of USB ROM stack. The version is defined as 0x0CHDMhCC where each nibble
represents version number of the corresponding component. CC - 7:0 - 8bit core version number h - 11:8
- 4bit hardware interface version number M - 15:12 - 4bit MSC class module version number D - 19:16 4bit DFU class module version number H - 23:20 - 4bit HID class module version number C - 27:24 - 4bit
CDC class module version number H - 31:28 - 4bit reserved

27.5.26 USBD_API_INIT_PARAM
USB device stack initialization parameter data structure.
Table 587. USBD_API_INIT_PARAM class structure
Member

Description

usb_reg_base

uint32_t USBD_API_INIT_PARAM::usb_reg_base
USB device controller's base register address.

mem_base

uint32_t USBD_API_INIT_PARAM::mem_base
Base memory location from where the stack can allocate data and buffers.
Remark: The memory address set in this field should be accessible by USB DMA controller. Also
this value should be aligned on 2048 byte boundary.

mem_size

uint32_t USBD_API_INIT_PARAM::mem_size
The size of memory buffer which stack can use.
Remark: The mem_size should be greater than the size returned by
USBD_HW_API::GetMemSize() routine.

max_num_ep

uint8_t USBD_API_INIT_PARAM::max_num_ep
max number of endpoints supported by the USB device controller instance (specified by

pad0

uint8_t USBD_API_INIT_PARAM::pad0[3][3]

USB_Reset_Event

USB_CB_T USBD_API_INIT_PARAM::USB_Reset_Event
Event for USB interface reset. This event fires when the USB host requests that the device reset
its interface. This event fires after the control endpoint has been automatically configured by the
library.
Remark: This event is called from USB_ISR context and hence is time-critical. Having delays in
this callback will prevent the device from enumerating correctly or operate properly.

USB_Suspend_Event

USB_CB_T USBD_API_INIT_PARAM::USB_Suspend_Event
Event for USB suspend. This event fires when the USB host suspends the device by halting its
transmission of Start Of Frame pulses to the device. This is generally hooked in order to move the
device over to a low power state until the host wakes up the device.
Remark: This event is called from USB_ISR context and hence is time-critical. Having delays in
this callback will cause other system issues.

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Table 587. USBD_API_INIT_PARAM class structure
Member

Description

USB_Resume_Event

USB_CB_T USBD_API_INIT_PARAM::USB_Resume_Event
Event for USB wake up or resume. This event fires when a the USB device interface is suspended
and the host wakes up the device by supplying Start Of Frame pulses. This is generally hooked to
pull the user application out of a low power state and back into normal operating mode.
Remark: This event is called from USB_ISR context and hence is time-critical. Having delays in
this callback will cause other system issues.

reserved_sbz

USB_CB_T USBD_API_INIT_PARAM::reserved_sbz
Reserved parameter should be set to zero.

USB_SOF_Event

USB_CB_T USBD_API_INIT_PARAM::USB_SOF_Event
Event for USB Start Of Frame detection, when enabled. This event fires at the start of each USB
frame, once per millisecond in full-speed mode or once per 125 microseconds in high-speed
mode, and is synchronized to the USB bus.
This event is time-critical; it is run once per millisecond (full-speed mode) and thus long handlers
will significantly degrade device performance. This event should only be enabled when needed to
reduce device wake-ups.
This event is not normally active - it must be manually enabled and disabled via the USB interrupt
register.
Remark: This event is not normally active - it must be manually enabled and disabled via the USB
interrupt register.

USB_WakeUpCfg

USB_PARAM_CB_T USBD_API_INIT_PARAM::USB_WakeUpCfg
Event for remote wake-up configuration, when enabled. This event fires when the USB host
request the device to configure itself for remote wake-up capability. The USB host sends this
request to device which report remote wake-up capable in their device descriptors, before going to
low-power state. The application layer should implement this callback if they have any special on
board circuit to triger remote wake up event. Also application can use this callback to differentiate
the following SUSPEND event is caused by cable plug-out or host SUSPEND request. The device
can wake-up host only after receiving this callback and remote wake-up feature is enabled by
host. To signal remote wake-up the device has to generate resume signaling on bus by calling
usapi.hw->WakeUp() routine.
Parameters:
1. hUsb = Handle to the USB device stack.
2. param1 = When 0 - Clear the wake-up configuration, 1 - Enable the wake-up configuration.
Returns:
The call back should return ErrorCode_t type to indicate success or error condition.

USB_Power_Event

USB_PARAM_CB_T USBD_API_INIT_PARAM::USB_Power_Event
Reserved parameter should be set to zero.

USB_Error_Event

USB_PARAM_CB_T USBD_API_INIT_PARAM:USB_Error_Event
Event for error condition. This event fires when USB device controller detect an error condition in
the system.
Parameters:
1. hUsb = Handle to the USB device stack.
2. param1 = USB device interrupt status register.
Returns:
The call back should return ErrorCode_t type to indicate success or error condition.

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Table 587. USBD_API_INIT_PARAM class structure
Member

Description

USB_Configure_Event

USB_CB_T USBD_API_INIT_PARAM::USB_Configure_Event
Event for USB configuration number changed. This event fires when a the USB host changes the
selected configuration number. On receiving configuration change request from host, the stack
enables/configures the endpoints needed by the new configuration before calling this callback
function.
Remark: This event is called from USB_ISR context and hence is time-critical. Having delays in
this callback will prevent the device from enumerating correctly or operate properly.

USB_Interface_Event

USB_CB_T USBD_API_INIT_PARAM::USB_Interface_Event
Event for USB interface setting changed. This event fires when a the USB host changes the
interface setting to one of alternate interface settings. On receiving interface change request from
host, the stack enables/configures the endpoints needed by the new alternate interface setting
before calling this callback function.
Remark: This event is called from USB_ISR context and hence is time-critical. Having delays in
this callback will prevent the device from enumerating correctly or operate properly.

USB_Feature_Event

USB_CB_T USBD_API_INIT_PARAM::USB_Feature_Event
Event for USB feature changed. This event fires when a the USB host send set/clear feature
request. The stack handles this request for USB_FEATURE_REMOTE_WAKEUP,
USB_FEATURE_TEST_MODE and USB_FEATURE_ENDPOINT_STALL features only. On
receiving feature request from host, the stack handle the request appropriately and then calls this
callback function.
Remark: This event is called from USB_ISR context and hence is time-critical. Having delays in
this callback will prevent the device from enumerating correctly or operate properly.

virt_to_phys

uint32_t(* USBD_API_INIT_PARAM::virt_to_phys)(void *vaddr)
Reserved parameter for future use. should be set to zero.

cache_flush

void(* USBD_API_INIT_PARAM::cache_flush)(uint32_t *start_adr, uint32_t *end_adr)
Reserved parameter for future use. should be set to zero.

27.5.27 USBD_CDC_API
CDC class API functions structure.This module exposes functions which interact directly
with USB device controller hardware.
Table 588. USBD_CDC_API class structure
Member

Description

GetMemSize

uint32_t(*uint32_t USBD_CDC_API::GetMemSize)(USBD_CDC_INIT_PARAM_T *param)
Function to determine the memory required by the CDC function driver module.
This function is called by application layer before calling pUsbApi->CDC->Init(), to allocate memory
used by CDC function driver module. The application should allocate the memory which is accessible
by USB controller/DMA controller.
Remark: Some memory areas are not accessible by all bus masters.
Parameters:
1. param = Structure containing CDC function driver module initialization parameters.
Returns:
Returns the required memory size in bytes.

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Table 588. USBD_CDC_API class structure
Member

Description

init

ErrorCode_t(*ErrorCode_t USBD_CDC_API::init)(USBD_HANDLE_T hUsb, USBD_CDC_INIT_PARAM_T *param,
USBD_HANDLE_T *phCDC)
Function to initialize CDC function driver module.
This function is called by application layer to initialize CDC function driver module.
hUsbHandle to the USB device stack. paramStructure containing CDC function driver module
initialization parameters.
Parameters:
1. hUsb = Handle to the USB device stack.
2. param = Structure containing CDC function driver module initialization parameters.
Returns:
Returns ErrorCode_t type to indicate success or error condition.
Return values:
1. LPC_OK = On success
2. ERR_USBD_BAD_MEM_BUF = Memory buffer passed is not 4-byte aligned or smaller than
required.
3. ERR_API_INVALID_PARAM2 = Either CDC_Write() or CDC_Read() or CDC_Verify() callbacks
are not defined.
4. ERR_USBD_BAD_INTF_DESC = Wrong interface descriptor is passed.
5. ERR_USBD_BAD_EP_DESC = Wrong endpoint descriptor is passed.

SendNotification

ErrorCode_t(*ErrorCode_t USBD_CDC_API::SendNotification)(USBD_HANDLE_T hCdc, uint8_t bNotification, uint16_t
data)
Function to send CDC class notifications to host.
This function is called by application layer to send CDC class notifications to host. See usbcdc11.pdf,
section 6.3, Table 67 for various notification types the CDC device can send.
Remark: The current version of the driver only supports following notifications allowed by ACM
subclass: CDC_NOTIFICATION_NETWORK_CONNECTION, CDC_RESPONSE_AVAILABLE,
CDC_NOTIFICATION_SERIAL_STATE. For all other notifications application should construct the
notification buffer appropriately and call hw->USB_WriteEP() for interrupt endpoint associated with the
interface.
Parameters:
1. hCdc = Handle to CDC function driver.
2. bNotification = Notification type allowed by ACM subclass. Should be
CDC_NOTIFICATION_NETWORK_CONNECTION, CDC_RESPONSE_AVAILABLE or
CDC_NOTIFICATION_SERIAL_STATE. For all other types ERR_API_INVALID_PARAM2 is
returned. See usbcdc11.pdf, section 3.6.2.1, table 5.
3. data = Data associated with notification. For CDC_NOTIFICATION_NETWORK_CONNECTION
a non-zero data value is interpreted as connected state. For CDC_RESPONSE_AVAILABLE
this parameter is ignored. For CDC_NOTIFICATION_SERIAL_STATE the data should use
bitmap values defined in usbcdc11.pdf, section 6.3.5, Table 69.
Returns:
Returns ErrorCode_t type to indicate success or error condition.
Return values:
1. LPC_OK = On success
2. ERR_API_INVALID_PARAM2 = If unsupported notification type is passed.

27.5.28 USBD_CDC_INIT_PARAM
Communication Device Class function driver initialization parameter data structure.
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Table 589. USBD_CDC_INIT_PARAM class structure
Member

Description

mem_base

uint32_t USBD_CDC_INIT_PARAM::mem_base
Base memory location from where the stack can allocate data and buffers.
Remark: The memory address set in this field should be accessible by USB DMA controller.
Also this value should be aligned on 4 byte boundary.

mem_size

uint32_t USBD_CDC_INIT_PARAM::mem_size
The size of memory buffer which stack can use.
Remark: The mem_size should be greater than the size returned by
USBD_CDC_API::GetMemSize() routine.

cif_intf_desc

uint8_t * USBD_CDC_INIT_PARAM::cif_intf_desc
Pointer to the control interface descriptor within the descriptor array

dif_intf_desc

uint8_t * USBD_CDC_INIT_PARAM::dif_intf_desc
Pointer to the data interface descriptor within the descriptor array

CIC_GetRequest

ErrorCode_t(* USBD_CDC_INIT_PARAM::CIC_GetRequest)(USBD_HANDLE_T hHid, USB_SETUP_PACKET
*pSetup, uint8_t **pBuffer, uint16_t *length)
Communication Interface Class specific get request call-back function.
This function is provided by the application software. This function gets called when host
sends CIC management element get requests.
Remark: Applications implementing Abstract Control Model subclass can set this param to
NULL. As the default driver parses ACM requests and calls the individual ACM call-back
routines defined in this structure. For all other subclasses this routine should be provided by
the application. The setup packet data (pSetup) is passed to the call-back so that application
can extract the CIC request type and other associated data. By default the stack will assign
pBuffer pointer to EP0Buff allocated at init. The application code can directly write data into
this buffer as long as data is less than 64 byte. If more data has to be sent then application
code should update pBuffer pointer and length accordingly.
Parameters:
1. hCdc = Handle to CDC function driver.
2. pSetup = Pointer to setup packet received from host.
3. pBuffer = Pointer to a pointer of data buffer containing request data. Pointer-to-pointer is
used to implement zero-copy buffers. See USBD_ZeroCopy for more details on
zero-copy concept.
4. length = Amount of data to be sent back to host.
Returns:
The call back should returns ErrorCode_t type to indicate success or error condition.
Return values:
1. LPC_OK = On success.
2. ERR_USBD_UNHANDLED = Event is not handled hence pass the event to next in line.
3. ERR_USBD_xxx = For other error conditions.

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Table 589. USBD_CDC_INIT_PARAM class structure
Member

Description

CIC_SetRequest

ErrorCode_t(* USBD_CDC_INIT_PARAM::CIC_SetRequest)(USBD_HANDLE_T hCdc, USB_SETUP_PACKET
*pSetup, uint8_t **pBuffer, uint16_t length)
Communication Interface Class specific set request call-back function.
This function is provided by the application software. This function gets called when host
sends a CIC management element requests.
Remark: Applications implementing Abstract Control Model subclass can set this param to
NULL. As the default driver parses ACM requests and calls the individual ACM call-back
routines defined in this structure. For all other subclasses this routine should be provided by
the application. The setup packet data (pSetup) is passed to the call-back so that application
can extract the CIC request type and other associated data. If a set request has data
associated, then this call-back is called twice. (1) First when setup request is received, at this
time application code could update pBuffer pointer to point to the intended destination. The
length param is set to 0 so that application code knows this is first time. By default the stack
will assign pBuffer pointer to EP0Buff allocated at init. Note, if data length is greater than 64
bytes and application code doesn't update pBuffer pointer the stack will send STALL condition
to host. (2) Second when the data is received from the host. This time the length param is set
with number of data bytes received.
Parameters:
1. hCdc = Handle to CDC function driver.
2. pSetup = Pointer to setup packet received from host.
3. pBuffer = Pointer to a pointer of data buffer containing request data. Pointer-to-pointer is
used to implement zero-copy buffers. See USBD_ZeroCopy for more details on
zero-copy concept.
4. length = Amount of data copied to destination buffer.
Returns:
The call back should returns ErrorCode_t type to indicate success or error condition.
Return values:
1. LPC_OK = On success.
2. ERR_USBD_UNHANDLED = Event is not handled hence pass the event to next in line.
3. ERR_USBD_xxx = For other error conditions.

CDC_BulkIN_Hdlr

ErrorCode_t(* USBD_CDC_INIT_PARAM::CDC_BulkIN_Hdlr)(USBD_HANDLE_T hUsb, void *data, uint32_t
event)
Communication Device Class specific BULK IN endpoint handler.
The application software should provide the BULK IN endpoint handler. Applications should
transfer data depending on the communication protocol type set in descriptors.
Remark:
Parameters:
1. hUsb = Handle to the USB device stack.
2. data = Pointer to the data which will be passed when callback function is called by the
stack.
3. event = Type of endpoint event. See USBD_EVENT_T for more details.
Returns:
The call back should returns ErrorCode_t type to indicate success or error condition.
Return values:
1. LPC_OK = On success.
2. ERR_USBD_UNHANDLED = Event is not handled hence pass the event to next in line.
3. ERR_USBD_xxx = For other error conditions.

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Table 589. USBD_CDC_INIT_PARAM class structure
Member

Description

CDC_BulkOUT_Hdlr

ErrorCode_t(* USBD_CDC_INIT_PARAM::CDC_BulkOUT_Hdlr)(USBD_HANDLE_T hUsb, void *data,
uint32_t event))(USBD_HANDLE_T hUsb, void *data, uint32_t event)
Communication Device Class specific BULK OUT endpoint handler.
The application software should provide the BULK OUT endpoint handler. Applications
should transfer data depending on the communication protocol type set in descriptors.
Remark:
Parameters:
1. hUsb = Handle to the USB device stack.
2. data = Pointer to the data which will be passed when callback function is called by the
stack.
3. event = Type of endpoint event. See USBD_EVENT_T for more details.
Returns:
The call back should returns ErrorCode_t type to indicate success or error condition.
Return values:
1. LPC_OK = On success.
2. ERR_USBD_UNHANDLED = Event is not handled hence pass the event to next in line.
3. ERR_USBD_xxx = For other error conditions.

SendEncpsCmd

ErrorCode_t(* USBD_CDC_INIT_PARAM::SendEncpsCmd)(USBD_HANDLE_T hCDC, uint8_t *buffer, uint16_t
len)
Abstract control model(ACM) subclass specific SEND_ENCAPSULATED_COMMAND
request call-back function.
This function is provided by the application software. This function gets called when host
sends a SEND_ENCAPSULATED_COMMAND set request.
Parameters:
1. hCdc = Handle to CDC function driver.
2. buffer = Pointer to the command buffer.
3. len = Length of the command buffer.
Returns:
The call back should returns ErrorCode_t type to indicate success or error condition.
Return values:
1. LPC_OK = On success.
2. ERR_USBD_UNHANDLED = Event is not handled hence pass the event to next in line.
3. ERR_USBD_xxx = For other error conditions.

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Table 589. USBD_CDC_INIT_PARAM class structure
Member

Description

GetEncpsResp

ErrorCode_t(* USBD_CDC_INIT_PARAM::GetEncpsResp)(USBD_HANDLE_T hCDC, uint8_t **buffer,
uint16_t *len)
Abstract control model(ACM) subclass specific GET_ENCAPSULATED_RESPONSE request
call-back function.
This function is provided by the application software. This function gets called when host
sends a GET_ENCAPSULATED_RESPONSE request.
Parameters:
1. hCdc = Handle to CDC function driver.
2. buffer = Pointer to a pointer of data buffer containing response data. Pointer-to-pointer is
used to implement zero-copy buffers. See USBD_ZeroCopy for more details on
zero-copy concept.
3. len = Amount of data to be sent back to host.
Returns:
The call back should returns ErrorCode_t type to indicate success or error condition.
Return values:
1. LPC_OK = On success.
2. ERR_USBD_UNHANDLED = Event is not handled hence pass the event to next in line.
3. ERR_USBD_xxx = For other error conditions.

SetCommFeature

ErrorCode_t(* USBD_CDC_INIT_PARAM::SetCommFeature)(USBD_HANDLE_T hCDC, uint16_t feature,
uint8_t *buffer, uint16_t len)
Abstract control model(ACM) subclass specific SET_COMM_FEATURE request call-back
function.
This function is provided by the application software. This function gets called when host
sends a SET_COMM_FEATURE set request.
Parameters:
1. hCdc = Handle to CDC function driver.
2. feature = Communication feature type.
3. buffer = Pointer to the settings buffer for the specified communication feature.
4. len = Length of the request buffer.
Returns:
The call back should returns ErrorCode_t type to indicate success or error condition.
Return values:
1. LPC_OK = On success.
2. ERR_USBD_UNHANDLED = Event is not handled hence pass the event to next in line.
3. ERR_USBD_xxx = For other error conditions.

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Table 589. USBD_CDC_INIT_PARAM class structure
Member

Description

GetCommFeature

ErrorCode_t(* USBD_CDC_INIT_PARAM::GetCommFeature)(USBD_HANDLE_T hCDC, uint16_t feature,
uint8_t **pBuffer, uint16_t *len)
Abstract control model(ACM) subclass specific GET_COMM_FEATURE request call-back
function.
This function is provided by the application software. This function gets called when host
sends a GET_ENCAPSULATED_RESPONSE request.
Parameters:
1. hCdc = Handle to CDC function driver.
2. feature = Communication feature type.
3. buffer = Pointer to a pointer of data buffer containing current settings for the
communication feature. Pointer-to-pointer is used to implement zero-copy buffers.
4. len = Amount of data to be sent back to host.
Returns:
The call back should returns ErrorCode_t type to indicate success or error condition.
Return values:
1. LPC_OK = On success.
2. ERR_USBD_UNHANDLED = Event is not handled hence pass the event to next in line.
3. ERR_USBD_xxx = For other error conditions.

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Table 589. USBD_CDC_INIT_PARAM class structure
Member

Description

ClrCommFeature

ErrorCode_t(* USBD_CDC_INIT_PARAM::ClrCommFeature)(USBD_HANDLE_T hCDC, uint16_t feature)
Abstract control model(ACM) subclass specific CLEAR_COMM_FEATURE request call-back
function.
This function is provided by the application software. This function gets called when host
sends a CLEAR_COMM_FEATURE request. In the call-back the application should Clears
the settings for a particular communication feature.
Parameters:
1. hCdc = Handle to CDC function driver.
2. feature = Communication feature type. See usbcdc11.pdf, section 6.2.4, Table 47.
Returns:
The call back should returns ErrorCode_t type to indicate success or error condition.
Return values:
1. LPC_OK = On success.
2. ERR_USBD_UNHANDLED = Event is not handled hence pass the event to next in line.
3. ERR_USBD_xxx = For other error conditions.

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Table 589. USBD_CDC_INIT_PARAM class structure
Member

Description

SetCtrlLineState

ErrorCode_t(* USBD_CDC_INIT_PARAM::SetCtrlLineState)(USBD_HANDLE_T hCDC, uint16_t state)
Abstract control model(ACM) subclass specific SET_CONTROL_LINE_STATE request
call-back function.
This function is provided by the application software. This function gets called when host
sends a SET_CONTROL_LINE_STATE request. RS-232 signal used to tell the DCE device
the DTE device is now present
Parameters:
1. hCdc = Handle to CDC function driver.
2. state = The state value uses bitmap values defined the USB CDC class specification
document published by usb.org.
Returns:
The call back should returns ErrorCode_t type to indicate success or error condition.
Return values:
1. LPC_OK = On success.
2. ERR_USBD_UNHANDLED = Event is not handled hence pass the event to next in line.
3. ERR_USBD_xxx = For other error conditions.

SendBreak

ErrorCode_t(* USBD_CDC_INIT_PARAM::SendBreak)(USBD_HANDLE_T hCDC, uint16_t mstime)
Abstract control model(ACM) subclass specific SEND_BREAK request call-back function.
This function is provided by the application software. This function gets called when host
sends a SEND_BREAK request.
Parameters:
1. hCdc = Handle to CDC function driver.
2. mstime = Duration of Break signal in milliseconds. If mstime is FFFFh, then the
application should send break until another SendBreak request is received with the
wValue of 0000h.
Returns:
The call back should returns ErrorCode_t type to indicate success or error condition.
Return values:
1. LPC_OK = On success.
2. ERR_USBD_UNHANDLED = Event is not handled hence pass the event to next in line.
3. ERR_USBD_xxx = For other error conditions.

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Table 589. USBD_CDC_INIT_PARAM class structure
Member

Description

SetLineCode

ErrorCode_t(* USBD_CDC_INIT_PARAM::SetLineCode)(USBD_HANDLE_T hCDC, CDC_LINE_CODING
*line_coding)
Abstract control model(ACM) subclass specific SET_LINE_CODING request call-back
function.
This function is provided by the application software. This function gets called when host
sends a SET_LINE_CODING request. The application should configure the device per DTE
rate, stop-bits, parity, and number-of-character bits settings provided in command buffer.
Parameters:
1. hCdc = Handle to CDC function driver.
2. line_coding = Pointer to the CDC_LINE_CODING command buffer.
Returns:
The call back should returns ErrorCode_t type to indicate success or error condition.
Return values:
1. LPC_OK = On success.
2. ERR_USBD_UNHANDLED = Event is not handled hence pass the event to next in line.
3. ERR_USBD_xxx = For other error conditions.

CDC_InterruptEP_Hdlr

ErrorCode_t(* USBD_CDC_INIT_PARAM::CDC_InterruptEP_Hdlr)(USBD_HANDLE_T hUsb, void *data,
uint32_t event)
Optional Communication Device Class specific INTERRUPT IN endpoint handler.
The application software should provide the INT IN endpoint handler. Applications should
transfer data depending on the communication protocol type set in descriptors.
Parameters:
1. hUsb = Handle to the USB device stack.
2. data = Pointer to the data which will be passed when callback function is called by the
stack.
3. event = Type of endpoint event. See USBD_EVENT_T for more details.
Returns:
The call back should returns ErrorCode_t type to indicate success or error condition.
Return values:
1. LPC_OK = On success.
2. ERR_USBD_UNHANDLED = Event is not handled hence pass the event to next in line.
3. ERR_USBD_xxx = For other error conditions.

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Table 589. USBD_CDC_INIT_PARAM class structure
Member

Description

CDC_Ep0_Hdlr

ErrorCode_t(* USBD_CDC_INIT_PARAM::CDC_Ep0_Hdlr)(USBD_HANDLE_T hUsb, void *data, uint32_t
event)
Optional user override-able function to replace the default CDC class handler.
The application software could override the default EP0 class handler with their own by
providing the handler function address as this data member of the parameter structure.
Application which like the default handler should set this data member to zero before calling
the USBD_CDC_API::Init().
Parameters:
1. hUsb = Handle to the USB device stack.
2. data = Pointer to the data which will be passed when callback function is called by the
stack.
3. event = Type of endpoint event. See USBD_EVENT_T for more details.
Returns:
The call back should returns ErrorCode_t type to indicate success or error condition.
Return values:
1. LPC_OK = On success.
2. ERR_USBD_UNHANDLED = Event is not handled hence pass the event to next in line.
3. ERR_USBD_xxx = For other error conditions.

27.5.29 USBD_CORE_API
USBD stack Core API functions structure.
Table 590. USBD_CORE_API class structure
Member

Description

RegisterClassHandler

ErrorCode_t(*ErrorCode_t USBD_CORE_API::RegisterClassHandler)(USBD_HANDLE_T hUsb,
USB_EP_HANDLER_T pfn, void *data)
Function to register class specific EP0 event handler with USB device stack.
The application layer uses this function when it has to register the custom class's EP0 handler. The
stack calls all the registered class handlers on any EP0 event before going through default
handling of the event. This gives the class handlers to implement class specific request handlers
and also to override the default stack handling for a particular event targeted to the interface.
Check USB_EP_HANDLER_T for more details on how the callback function should be
implemented. Also application layer could use this function to register EP0 handler which responds
to vendor specific requests.
Parameters:
1. hUsb = Handle to the USB device stack.
2. pfn = Class specific EP0 handler function.
3. data = Pointer to the data which will be passed when callback function is called by the stack.
Returns:
Returns ErrorCode_t type to indicate success or error condition.
Return values:
1. LPC_OK = On success
2. ERR_USBD_TOO_MANY_CLASS_HDLR(0x0004000c) = The number of class handlers
registered is greater than the number of handlers allowed by the stack.

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Table 590. USBD_CORE_API class structure
Member

Description

RegisterEpHandler

ErrorCode_t(*ErrorCode_t USBD_CORE_API::RegisterEpHandler)(USBD_HANDLE_T hUsb, uint32_t ep_index,
USB_EP_HANDLER_T pfn, void *data)
Function to register interrupt/event handler for the requested endpoint with USB device stack.
The application layer uses this function to register the custom class's EP0 handler. The stack calls
all the registered class handlers on any EP0 event before going through default handling of the
event. This gives the class handlers to implement class specific request handlers and also to
override the default stack handling for a particular event targeted to the interface. Check
USB_EP_HANDLER_T for more details on how the callback function should be implemented.
Parameters:
1. hUsb = Handle to the USB device stack.
2. ep_index = Class specific EP0 handler function.
3. pfn = Class specific EP0 handler function.
4. data = Pointer to the data which will be passed when callback function is called by the stack.
Returns:
Returns ErrorCode_t type to indicate success or error condition.
Return values:
1. LPC_OK = On success
2. ERR_USBD_TOO_MANY_CLASS_HDLR(0x0004000c) = Too many endpoint handlers.

SetupStage

void(*void USBD_CORE_API::SetupStage)(USBD_HANDLE_T hUsb)
Function to set EP0 state machine in setup state.
This function is called by USB stack and the application layer to set the EP0 state machine in setup
state. This function will read the setup packet received from USB host into stack's buffer.
Remark: This interface is provided to users to invoke this function in other scenarios which are not
handle by current stack. In most user applications this function is not called directly.Also this
function can be used by users who are selectively modifying the USB device stack's standard
handlers through callback interface exposed by the stack.
Parameters:
1. hUsb = Handle to the USB device stack.
Returns:
Nothing.

DataInStage

void(*void USBD_CORE_API::DataInStage)(USBD_HANDLE_T hUsb)
Function to set EP0 state machine in data_in state.
This function is called by USB stack and the application layer to set the EP0 state machine in
data_in state. This function will write the data present in EP0Data buffer to EP0 FIFO for
transmission to host.
Remark: This interface is provided to users to invoke this function in other scenarios which are not
handle by current stack. In most user applications this function is not called directly.Also this
function can be used by users who are selectively modifying the USB device stack's standard
handlers through callback interface exposed by the stack.
Parameters:
1. hUsb = Handle to the USB device stack.
Returns:
Nothing.

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Table 590. USBD_CORE_API class structure
Member

Description

DataOutStage

void(*void USBD_CORE_API::DataOutStage)(USBD_HANDLE_T hUsb)
Function to set EP0 state machine in data_out state.
This function is called by USB stack and the application layer to set the EP0 state machine in
data_out state. This function will read the control data (EP0 out packets) received from USB host
into EP0Data buffer.
Remark: This interface is provided to users to invoke this function in other scenarios which are not
handle by current stack. In most user applications this function is not called directly.Also this
function can be used by users who are selectively modifying the USB device stack's standard
handlers through callback interface exposed by the stack.
Parameters:
1. hUsb = Handle to the USB device stack.
Returns:
Nothing.

StatusInStage

void(*void USBD_CORE_API::StatusInStage)(USBD_HANDLE_T hUsb)
Function to set EP0 state machine in status_in state.
This function is called by USB stack and the application layer to set the EP0 state machine in
status_in state. This function will send zero length IN packet on EP0 to host, indicating positive
status.
Remark: This interface is provided to users to invoke this function in other scenarios which are not
handle by current stack. In most user applications this function is not called directly.Also this
function can be used by users who are selectively modifying the USB device stack's standard
handlers through callback interface exposed by the stack.
Parameters:
1. hUsb = Handle to the USB device stack.
Returns:
Nothing.

StatusOutStage

void(*void USBD_CORE_API::StatusOutStage)(USBD_HANDLE_T hUsb)
Function to set EP0 state machine in status_out state.
This function is called by USB stack and the application layer to set the EP0 state machine in
status_out state. This function will read the zero length OUT packet received from USB host on
EP0.
Remark: This interface is provided to users to invoke this function in other scenarios which are not
handle by current stack. In most user applications this function is not called directly.Also this
function can be used by users who are selectively modifying the USB device stack's standard
handlers through callback interface exposed by the stack.
Parameters:
1. hUsb = Handle to the USB device stack.
Returns:
Nothing.

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Table 590. USBD_CORE_API class structure
Member

Description

StallEp0

void(*void USBD_CORE_API::StallEp0)(USBD_HANDLE_T hUsb)
Function to set EP0 state machine in stall state.
This function is called by USB stack and the application layer to generate STALL signalling on EP0
endpoint. This function will also reset the EP0Data buffer.
Remark: This interface is provided to users to invoke this function in other scenarios which are not
handle by current stack. In most user applications this function is not called directly.Also this
function can be used by users who are selectively modifying the USB device stack's standard
handlers through callback interface exposed by the stack.
Parameters:
1. hUsb = Handle to the USB device stack.
Returns:
Nothing.

27.5.30 USBD_DFU_API
DFU class API functions structure.This module exposes functions which interact directly
with USB device controller hardware.

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Table 591. USBD_DFU_API class structure
Member

Description

GetMemSize

uint32_t(*uint32_t USBD_DFU_API::GetMemSize)(USBD_DFU_INIT_PARAM_T *param)
Function to determine the memory required by the DFU function driver module.
This function is called by application layer before calling pUsbApi->dfu->Init(), to allocate memory used by
DFU function driver module. The application should allocate the memory which is accessible by USB
controller/DMA controller.
Remark: Some memory areas are not accessible by all bus masters.
Parameters:
1. param = Structure containing DFU function driver module initialization parameters.
Returns:
Returns the required memory size in bytes.

init

ErrorCode_t(*ErrorCode_t USBD_DFU_API::init)(USBD_HANDLE_T hUsb, USBD_DFU_INIT_PARAM_T *param, uint32_t
init_state)
Function to initialize DFU function driver module.
This function is called by application layer to initialize DFU function driver module.
Parameters:
1. hUsb = Handle to the USB device stack.
2. param = Structure containing DFU function driver module initialization parameters.
Returns:
Returns ErrorCode_t type to indicate success or error condition.
Return values:
1. LPC_OK = On success
2. ERR_USBD_BAD_MEM_BUF = Memory buffer passed is not 4-byte aligned or smaller than
required.
3. ERR_API_INVALID_PARAM2 = Either DFU_Write() or DFU_Done() or DFU_Read() callbacks are
not defined.
4. ERR_USBD_BAD_DESC = USB_DFU_DESCRIPTOR_TYPE is not defined immediately after
interface descriptor.wTransferSize in descriptor doesn't match the value passed in
param->wTransferSize.DFU_Detach() is not defined while USB_DFU_WILL_DETACH is set in DFU
descriptor.
5. ERR_USBD_BAD_INTF_DESC = Wrong interface descriptor is passed.

27.5.31 USBD_DFU_INIT_PARAM
USB descriptors data structure.
Table 592. USBD_DFU_INIT_PARAM class structure
Member

Description

mem_base

uint32_t USBD_DFU_INIT_PARAM::mem_base
Base memory location from where the stack can allocate data and buffers.
Remark: The memory address set in this field should be accessible by USB DMA controller. Also this
value should be aligned on 4 byte boundary.

mem_size

uint32_t USBD_DFU_INIT_PARAM::mem_size
The size of memory buffer which stack can use.
Remark: The mem_size should be greater than the size returned by USBD_DFU_API::GetMemSize()
routine.

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Table 592. USBD_DFU_INIT_PARAM class structure
Member

Description

wTransferSize

uint16_t USBD_DFU_INIT_PARAM::wTransferSize
DFU transfer block size in number of bytes. This value should match the value set in DFU descriptor
provided as part of the descriptor array (

pad

uint16_t USBD_DFU_INIT_PARAM::pad

intf_desc

uint8_t * USBD_DFU_INIT_PARAM::intf_desc
Pointer to the DFU interface descriptor within the descriptor array (

DFU_Write

uint8_t(*uint8_t(* USBD_DFU_INIT_PARAM::DFU_Write)(uint32_t block_num, uint8_t **src, uint32_t length, uint8_t
*bwPollTimeout))(uint32_t block_num, uint8_t **src, uint32_t length, uint8_t *bwPollTimeout)
DFU Write callback function.
This function is provided by the application software. This function gets called when host sends a write
command. For application using zero-copy buffer scheme this function is called for the first time with
Parameters:
1. block_num = Destination start address.
2. src = Pointer to a pointer to the source of data. Pointer-to-pointer is used to implement zero-copy
buffers. See Zero-Copy Data Transfer model for more details on zero-copy concept.
3. bwPollTimeout = Pointer to a 3 byte buffer which the callback implementer should fill with the
amount of minimum time, in milliseconds, that the host should wait before sending a subsequent
DFU_GETSTATUS request.
4. length = Number of bytes to be written.
Returns:
Returns DFU_STATUS_ values defined in mw_usbd_dfu.h.

DFU_Read

uint32_t(*uint32_t(* USBD_DFU_INIT_PARAM::DFU_Read)(uint32_t block_num, uint8_t **dst, uint32_t length))(uint32_t
block_num, uint8_t **dst, uint32_t length)
DFU Read callback function.
This function is provided by the application software. This function gets called when host sends a read
command.
Parameters:
1. block_num = Destination start address.
2. dst = Pointer to a pointer to the source of data. Pointer-to-pointer is used to implement zero-copy
buffers. See Zero-Copy Data Transfer model for more details on zero-copy concept.
3. length = Amount of data copied to destination buffer.
Returns:
Returns DFU_STATUS_ values defined in mw_usbd_dfu.h.

DFU_Done

void(*USBD_DFU_INIT_PARAM::DFU_Done)(void)
DFU done callback function.
This function is provided by the application software. This function gets called after download is
finished.
Nothing.
Returns:
Nothing.

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Table 592. USBD_DFU_INIT_PARAM class structure
Member

Description

DFU_Detach

void(* USBD_DFU_INIT_PARAM::DFU_Detach)(USBD_HANDLE_T hUsb)
DFU detach callback function.
This function is provided by the application software. This function gets called after
USB_REQ_DFU_DETACH is received. Applications which set USB_DFU_WILL_DETACH bit in DFU
descriptor should define this function. As part of this function application can call Connect() routine to
disconnect and then connect back with host. For application which rely on WinUSB based host
application should use this feature since USB reset can be invoked only by kernel drivers on Windows
host. By implementing this feature host doesn't have to issue reset instead the device has to do it
automatically by disconnect and connect procedure.
hUsbHandle DFU control structure.
Parameters:
1. hUsb = Handle DFU control structure.
Returns:
Nothing.

DFU_Ep0_Hdlr

ErrorCode_t(* USBD_DFU_INIT_PARAM::DFU_Ep0_Hdlr)(USBD_HANDLE_T hUsb, void *data, uint32_t event)
Optional user overridable function to replace the default DFU class handler.
The application software could override the default EP0 class handler with their own by providing the
handler function address as this data member of the parameter structure. Application which like the
default handler should set this data member to zero before calling the USBD_DFU_API::Init().
Remark:
Parameters:
1. hUsb = Handle to the USB device stack.
2. data = Pointer to the data which will be passed when callback function is called by the stack.
3. event = Type of endpoint event. See USBD_EVENT_T for more details.
Returns:
The call back should returns ErrorCode_t type to indicate success or error condition.
Return values:
1. LPC_OK = On success.
2. ERR_USBD_UNHANDLED = Event is not handled hence pass the event to next in line.
3. ERR_USBD_xxx = For other error conditions.

27.5.32 USBD_HID_API
HID class API functions structure.This structure contains pointers to all the function
exposed by HID function driver module.

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Table 593. USBD_HID_API class structure
Member

Description

GetMemSize

uint32_t(*uint32_t USBD_HID_API::GetMemSize)(USBD_HID_INIT_PARAM_T *param)
Function to determine the memory required by the HID function driver module.
This function is called by application layer before calling pUsbApi->hid->Init(), to allocate memory used by
HID function driver module. The application should allocate the memory which is accessible by USB
controller/DMA controller.
Remark: Some memory areas are not accessible by all bus masters.
Parameters:
1. param = Structure containing HID function driver module initialization parameters.
Returns:
Returns the required memory size in bytes.

init

ErrorCode_t(*ErrorCode_t USBD_HID_API::init)(USBD_HANDLE_T hUsb, USBD_HID_INIT_PARAM_T *param)
Function to initialize HID function driver module.
This function is called by application layer to initialize HID function driver module. On successful
initialization the function returns a handle to HID function driver module in passed param structure.
Parameters:
1. hUsb = Handle to the USB device stack.
2. param = Structure containing HID function driver module initialization parameters.
Returns:
Returns ErrorCode_t type to indicate success or error condition.
Return values:
1. LPC_OK = On success
2. ERR_USBD_BAD_MEM_BUF = Memory buffer passed is not 4-byte aligned or smaller than
required.
3. ERR_API_INVALID_PARAM2 = Either HID_GetReport() or HID_SetReport() callback are not
defined.
4. ERR_USBD_BAD_DESC = HID_HID_DESCRIPTOR_TYPE is not defined immediately after
interface descriptor.
5. ERR_USBD_BAD_INTF_DESC = Wrong interface descriptor is passed.
6. ERR_USBD_BAD_EP_DESC = Wrong endpoint descriptor is passed.

27.5.33 USBD_HID_INIT_PARAM
USB descriptors data structure.

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Table 594. USBD_HID_INIT_PARAM class structure
Member

Description

mem_base

uint32_t USBD_HID_INIT_PARAM::mem_base
Base memory location from where the stack can allocate data and buffers.
Remark: The memory address set in this field should be accessible by USB DMA controller. Also
this value should be aligned on 4 byte boundary.

mem_size

uint32_t USBD_HID_INIT_PARAM::mem_size
The size of memory buffer which stack can use.
Remark: The mem_size should be greater than the size returned by
USBD_HID_API::GetMemSize() routine.

max_reports

uint8_t USBD_HID_INIT_PARAM::max_reports
Number of HID reports supported by this instance of HID class driver.

pad

uint8_t USBD_HID_INIT_PARAM::pad[3][3]

intf_desc

uint8_t * USBD_HID_INIT_PARAM::intf_desc
Pointer to the HID interface descriptor within the descriptor array (

report_data

USB_HID_REPORT_T *USB_HID_REPORT_T* USBD_HID_INIT_PARAM::report_data
Pointer to an array of HID report descriptor data structure (
Remark: This array should be of global scope.

HID_GetReport

ErrorCode_t(* USBD_HID_INIT_PARAM::HID_GetReport)(USBD_HANDLE_T hHid, USB_SETUP_PACKET *pSetup,
uint8_t **pBuffer, uint16_t *length)
HID get report callback function.
This function is provided by the application software. This function gets called when host sends a
HID_REQUEST_GET_REPORT request. The setup packet data (
Remark: HID reports are sent via interrupt IN endpoint also. This function is called only when report
request is received on control endpoint. Application should implement HID_EpIn_Hdlr to send
reports to host via interrupt IN endpoint.
Parameters:
1. hHid = Handle to HID function driver.
2. pSetup = Pointer to setup packet received from host.
3. pBuffer = Pointer to a pointer of data buffer containing report data. Pointer-to-pointer is used to
implement zero-copy buffers. See Zero-Copy Data Transfer model for more details on
zero-copy concept.
4. length = Amount of data copied to destination buffer.
Returns:
The call back should returns ErrorCode_t type to indicate success or error condition.
Return values:
1. LPC_OK = On success.
2. ERR_USBD_UNHANDLED = Event is not handled hence pass the event to next in line.
3. ERR_USBD_xxx = For other error conditions.

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Table 594. USBD_HID_INIT_PARAM class structure
Member

Description

HID_SetReport

ErrorCode_t(* USBD_HID_INIT_PARAM::HID_SetReport)(USBD_HANDLE_T hHid, USB_SETUP_PACKET *pSetup,
uint8_t **pBuffer, uint16_t length)
HID set report callback function.
This function is provided by the application software. This function gets called when host sends a
HID_REQUEST_SET_REPORT request. The setup packet data (
Parameters:
1. hHid = Handle to HID function driver.
2. pSetup = Pointer to setup packet received from host.
3. pBuffer = Pointer to a pointer of data buffer containing report data. Pointer-to-pointer is used to
implement zero-copy buffers. See Zero-Copy Data Transfer model for more details on
zero-copy concept.
4. length = Amount of data copied to destination buffer.
Returns:
The call back should returns ErrorCode_t type to indicate success or error condition.
Return values:
1. LPC_OK = On success.
2. ERR_USBD_UNHANDLED = Event is not handled hence pass the event to next in line.
3. ERR_USBD_xxx = For other error conditions.

HID_GetPhysDesc

ErrorCode_t(* USBD_HID_INIT_PARAM::HID_GetPhysDesc)(USBD_HANDLE_T hHid, USB_SETUP_PACKET
*pSetup, uint8_t **pBuf, uint16_t *length)
Optional callback function to handle HID_GetPhysDesc request.
The application software could provide this callback HID_GetPhysDesc handler to handle get
physical descriptor requests sent by the host. When host requests Physical Descriptor set 0,
application should return a special descriptor identifying the number of descriptor sets and their
sizes. A Get_Descriptor request with the Physical Index equal to 1 should return the first Physical
Descriptor set. A device could possibly have alternate uses for its items. These can be enumerated
by issuing subsequent Get_Descriptor requests while incrementing the Descriptor Index. A device
should return the last descriptor set to requests with an index greater than the last number defined in
the HID descriptor.
Remark: Applications which don't have physical descriptor should set this data member to zero
before calling the USBD_HID_API::Init().
Parameters:
1. hHid = Handle to HID function driver.
2. pSetup = Pointer to setup packet received from host.
3. pBuf = Pointer to a pointer of data buffer containing physical descriptor data. If the physical
descriptor is in USB accessible memory area application could just update the pointer or else it
should copy the descriptor to the address pointed by this pointer.
4. length = Amount of data copied to destination buffer or descriptor length.
Returns:
The call back should returns ErrorCode_t type to indicate success or error condition.
Return values:
1. LPC_OK = On success.
2. ERR_USBD_UNHANDLED = Event is not handled hence pass the event to next in line.
3. ERR_USBD_xxx = For other error conditions.

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Table 594. USBD_HID_INIT_PARAM class structure
Member

Description

HID_SetIdle

ErrorCode_t(* USBD_HID_INIT_PARAM::HID_SetIdle)(USBD_HANDLE_T hHid, USB_SETUP_PACKET *pSetup,
uint8_t idleTime)
Optional callback function to handle HID_REQUEST_SET_IDLE request.
The application software could provide this callback to handle HID_REQUEST_SET_IDLE requests
sent by the host. This callback is provided to applications to adjust timers associated with various
reports, which are sent to host over interrupt endpoint. The setup packet data (
Remark: Applications which don't send reports on Interrupt endpoint or don't have idle time between
reports should set this data member to zero before calling the USBD_HID_API::Init().
Parameters:
1. hHid = Handle to HID function driver.
2. pSetup = Pointer to setup packet recived from host.
3. idleTime = Idle time to be set for the specified report.
Returns:
The call back should returns ErrorCode_t type to indicate success or error condition.
Return values:
1. LPC_OK = On success.
2. ERR_USBD_UNHANDLED = Event is not handled hence pass the event to next in line.
3. ERR_USBD_xxx = For other error conditions.

HID_SetProtocol

ErrorCode_t(* USBD_HID_INIT_PARAM::HID_SetProtocol)(USBD_HANDLE_T hHid, USB_SETUP_PACKET *pSetup,
uint8_t protocol)
Optional callback function to handle HID_REQUEST_SET_PROTOCOL request.
The application software could provide this callback to handle HID_REQUEST_SET_PROTOCOL
requests sent by the host. This callback is provided to applications to adjust modes of their code
between boot mode and report mode.
Remark: Applications which don't support protocol modes should set this data member to zero
before calling the USBD_HID_API::Init().
Parameters:
1. hHid = Handle to HID function driver.
2. pSetup = Pointer to setup packet recived from host.
3. protocol = Protocol mode. 0 = Boot Protocol 1 = Report Protocol
Returns:
The call back should returns ErrorCode_t type to indicate success or error condition.
Return values:
1. LPC_OK = On success.
2. ERR_USBD_UNHANDLED = Event is not handled hence pass the event to next in line.
3. ERR_USBD_xxx = For other error conditions.

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Table 594. USBD_HID_INIT_PARAM class structure
Member

Description

HID_EpIn_Hdlr

ErrorCode_t(* USBD_HID_INIT_PARAM::HID_EpIn_Hdlr)(USBD_HANDLE_T hUsb, void *data, uint32_t event)
Optional Interrupt IN endpoint event handler.
The application software could provide Interrupt IN endpoint event handler. Application which send
reports to host on interrupt endpoint should provide an endpoint event handler through this data
member. This data member is ignored if the interface descriptor
Parameters:
1. hUsb = Handle to the USB device stack.
2. data = Handle to HID function driver.
3. event = Type of endpoint event. See USBD_EVENT_T for more details.
Returns:
The call back should return ErrorCode_t type to indicate success or error condition.
Return values:
1. LPC_OK = On success.
2. ERR_USBD_UNHANDLED = Event is not handled hence pass the event to next in line.
3. ERR_USBD_xxx = For other error conditions.

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Table 594. USBD_HID_INIT_PARAM class structure
Member

Description

HID_EpOut_Hdlr

ErrorCode_t(* USBD_HID_INIT_PARAM::HID_EpOut_Hdlr)(USBD_HANDLE_T hUsb, void *data, uint32_t event)
Optional Interrupt OUT endpoint event handler.
The application software could provide Interrupt OUT endpoint event handler. Application which
receives reports from host on interrupt endpoint should provide an endpoint event handler through
this data member. This data member is ignored if the interface descriptor
Parameters:
1. hUsb = Handle to the USB device stack.
2. data = Handle to HID function driver.
3. event = Type of endpoint event. See USBD_EVENT_T for more details.
Returns:
The call back should return ErrorCode_t type to indicate success or error condition.
Return values:
1. LPC_OK = On success.
2. ERR_USBD_UNHANDLED = Event is not handled hence pass the event to next in line.
3. ERR_USBD_xxx = For other error conditions.

HID_GetReportDesc

ErrorCode_t(* USBD_HID_INIT_PARAM::HID_GetReportDesc)(USBD_HANDLE_T hHid, USB_SETUP_PACKET
*pSetup, uint8_t **pBuf, uint16_t *length)
Optional user overridable function to replace the default HID_GetReportDesc handler.
The application software could override the default HID_GetReportDesc handler with their own by
providing the handler function address as this data member of the parameter structure. Application
which like the default handler should set this data member to zero before calling the
USBD_HID_API::Init() and also provide report data array
Remark:
Parameters:
1. hUsb = Handle to the USB device stack.
2. data = Pointer to the data which will be passed when callback function is called by the stack.
3. event = Type of endpoint event. See USBD_EVENT_T for more details.
Returns:
The call back should returns ErrorCode_t type to indicate success or error condition.
Return values:
1. LPC_OK = On success.
2. ERR_USBD_UNHANDLED = Event is not handled hence pass the event to next in line.
3. ERR_USBD_xxx = For other error conditions.

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Table 594. USBD_HID_INIT_PARAM class structure
Member

Description

HID_Ep0_Hdlr

ErrorCode_t(* USBD_HID_INIT_PARAM::HID_Ep0_Hdlr)(USBD_HANDLE_T hUsb, void *data, uint32_t event)
Optional user overridable function to replace the default HID class handler.
The application software could override the default EP0 class handler with their own by providing the
handler function address as this data member of the parameter structure. Application which like the
default handler should set this data member to zero before calling the USBD_HID_API::Init().
Remark:
Parameters:
1. hUsb = Handle to the USB device stack.
2. data = Pointer to the data which will be passed when callback function is called by the stack.
3. event = Type of endpoint event. See USBD_EVENT_T for more details.
Returns:
The call back should returns ErrorCode_t type to indicate success or error condition.
Return values:
1. LPC_OK = On success.
2. ERR_USBD_UNHANDLED = Event is not handled hence pass the event to next in line.
3. ERR_USBD_xxx = For other error conditions.

27.5.34 USBD_HW_API
Hardware API functions structure.This module exposes functions which interact directly
with USB device controller hardware.

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Table 595. USBD_HW_API class structure
Member

Description

GetMemSize

uint32_t(*uint32_t USBD_HW_API::GetMemSize)(USBD_API_INIT_PARAM_T *param)
Function to determine the memory required by the USB device stack's DCD and core layers.
This function is called by application layer before calling pUsbApi->hw->
Remark: Some memory areas are not accessible by all bus masters.
Parameters:
1. param = Structure containing USB device stack initialization parameters.
Returns:
Returns the required memory size in bytes.

Init

ErrorCode_t(*ErrorCode_t USBD_HW_API::Init)(USBD_HANDLE_T *phUsb, USB_CORE_DESCS_T *pDesc,
USBD_API_INIT_PARAM_T *param)
Function to initialize USB device stack's DCD and core layers.
This function is called by application layer to initialize USB hardware and core layers. On successful
initialization the function returns a handle to USB device stack which should be passed to the rest of
the functions.
Parameters:
1. phUsb = Pointer to the USB device stack handle of type USBD_HANDLE_T.
2. param = Structure containing USB device stack initialization parameters.
Returns:
Returns ErrorCode_t type to indicate success or error condition.
Return values:
1. LPC_OK(0) = On success
2. ERR_USBD_BAD_MEM_BUF(0x0004000b) = When insufficient memory buffer is passed or
memory is not aligned on 2048 boundary.

Connect

void(*void USBD_HW_API::Connect)(USBD_HANDLE_T hUsb, uint32_t con)
Function to make USB device visible/invisible on the USB bus.
This function is called after the USB initialization. This function uses the soft connect feature to make
the device visible on the USB bus. This function is called only after the application is ready to handle
the USB data. The enumeration process is started by the host after the device detection. The driver
handles the enumeration process according to the USB descriptors passed in the USB initialization
function.
Parameters:
1. hUsb = Handle to the USB device stack.
2. con = States whether to connect (1) or to disconnect (0).
Returns:
Nothing.

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Table 595. USBD_HW_API class structure
Member

Description

ISR

void(*void USBD_HW_API::ISR)(USBD_HANDLE_T hUsb)
Function to USB device controller interrupt events.
When the user application is active the interrupt handlers are mapped in the user flash space. The user
application must provide an interrupt handler for the USB interrupt and call this function in the interrupt
handler routine. The driver interrupt handler takes appropriate action according to the data received on
the USB bus.
Parameters:
1. hUsb = Handle to the USB device stack.
Returns:
Nothing.

Reset

void(*void USBD_HW_API::Reset)(USBD_HANDLE_T hUsb)
Function to Reset USB device stack and hardware controller.
Reset USB device stack and hardware controller. Disables all endpoints except EP0. Clears all
pending interrupts and resets endpoint transfer queues. This function is called internally by
pUsbApi->hw->init() and from reset event.
Parameters:
1. hUsb = Handle to the USB device stack.
Returns:
Nothing.

ForceFullSpeed

void(*void USBD_HW_API::ForceFullSpeed)(USBD_HANDLE_T hUsb, uint32_t cfg)
Function to force high speed USB device to operate in full speed mode.
This function is useful for testing the behavior of current device when connected to a full speed only
hosts.
Parameters:
1. hUsb = Handle to the USB device stack.
2. cfg = When 1 - set force full-speed or 0 - clear force full-speed.
Returns:
Nothing.

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Table 595. USBD_HW_API class structure
Member

Description

WakeUpCfg

void(*void USBD_HW_API::WakeUpCfg)(USBD_HANDLE_T hUsb, uint32_t cfg)
Function to configure USB device controller to walk-up host on remote events.
This function is called by application layer to configure the USB device controller to wake up on remote
events. It is recommended to call this function from users's USB_WakeUpCfg() callback routine
registered with stack.
Remark: User's USB_WakeUpCfg() is registered with stack by setting the USB_WakeUpCfg member
of USBD_API_INIT_PARAM_T structure before calling pUsbApi->hw->Init() routine. Certain USB
device controllers needed to keep some clocks always on to generate resume signaling through
pUsbApi->hw->WakeUp(). This hook is provided to support such controllers. In most controllers cases
this is an empty routine.
Parameters:
1. hUsb = Handle to the USB device stack.
2. cfg = When 1 - Configure controller to wake on remote events or 0 - Configure controller not to
wake on remote events.
Returns:
Nothing.

SetAddress

void(*void USBD_HW_API::SetAddress)(USBD_HANDLE_T hUsb, uint32_t adr)
Function to set USB address assigned by host in device controller hardware.
This function is called automatically when USB_REQUEST_SET_ADDRESS request is received by
the stack from USB host. This interface is provided to users to invoke this function in other scenarios
which are not handle by current stack. In most user applications this function is not called directly. Also
this function can be used by users who are selectively modifying the USB device stack's standard
handlers through callback interface exposed by the stack.
Parameters:
1. hUsb = Handle to the USB device stack.
2. adr = USB bus Address to which the device controller should respond. Usually assigned by the
USB host.
Returns:
Nothing.

Configure

void(*void USBD_HW_API::Configure)(USBD_HANDLE_T hUsb, uint32_t cfg)
Function to configure device controller hardware with selected configuration.
This function is called automatically when USB_REQUEST_SET_CONFIGURATION request is
received by the stack from USB host. This interface is provided to users to invoke this function in other
scenarios which are not handle by current stack. In most user applications this function is not called
directly. Also this function can be used by users who are selectively modifying the USB device stack's
standard handlers through callback interface exposed by the stack.
Parameters:
1. hUsb = Handle to the USB device stack.
2. cfg = Configuration index.
Returns:
Nothing.

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Table 595. USBD_HW_API class structure
Member

Description

ConfigEP

void(*void USBD_HW_API::ConfigEP)(USBD_HANDLE_T hUsb, USB_ENDPOINT_DESCRIPTOR *pEPD)
Function to configure USB Endpoint according to descriptor.
This function is called automatically when USB_REQUEST_SET_CONFIGURATION request is
received by the stack from USB host. All the endpoints associated with the selected configuration are
configured. This interface is provided to users to invoke this function in other scenarios which are not
handle by current stack. In most user applications this function is not called directly. Also this function
can be used by users who are selectively modifying the USB device stack's standard handlers through
callback interface exposed by the stack.
Parameters:
1. hUsb = Handle to the USB device stack.
2. pEPD = Endpoint descriptor structure defined in USB 2.0 specification.
Returns:
Nothing.

DirCtrlEP

void(*void USBD_HW_API::DirCtrlEP)(USBD_HANDLE_T hUsb, uint32_t dir)
Function to set direction for USB control endpoint EP0.
This function is called automatically by the stack on need basis. This interface is provided to users to
invoke this function in other scenarios which are not handle by current stack. In most user applications
this function is not called directly. Also this function can be used by users who are selectively modifying
the USB device stack's standard handlers through callback interface exposed by the stack.
Parameters:
1. hUsb = Handle to the USB device stack.
2. cfg = When 1 - Set EP0 in IN transfer mode 0 - Set EP0 in OUT transfer mode
Returns:
Nothing.

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Table 595. USBD_HW_API class structure
Member

Description

EnableEP

void(*void USBD_HW_API::EnableEP)(USBD_HANDLE_T hUsb, uint32_t EPNum)
Function to enable selected USB endpoint.
This function enables interrupts on selected endpoint.
Parameters:
1. hUsb = Handle to the USB device stack.
2. EPNum = Endpoint number as per USB specification. ie. An EP1_IN is represented by 0x81
number.
Returns:
Nothing.
This function enables interrupts on selected endpoint.
Parameters:
1. hUsb = Handle to the USB device stack.
2. EPNum = Endpoint number corresponding to the event as per USB specification. ie. An EP1_IN is
represented by 0x81 number. For device events set this param to 0x0.
3. event = Type of endpoint event. See USBD_EVENT_T for more details.
4. enable = 1 - enable event, 0 - disable event.
Returns:
Returns ErrorCode_t type to indicate success or error condition.
Return values:
1. LPC_OK(0) = - On success
2. ERR_USBD_INVALID_REQ(0x00040001) = - Invalid event type.

DisableEP

void(*void USBD_HW_API::DisableEP)(USBD_HANDLE_T hUsb, uint32_t EPNum)
Function to disable selected USB endpoint.
This function disables interrupts on selected endpoint.
Parameters:
1. hUsb = Handle to the USB device stack.
2. EPNum = Endpoint number as per USB specification. ie. An EP1_IN is represented by 0x81
number.
Returns:
Nothing.

ResetEP

void(*void USBD_HW_API::ResetEP)(USBD_HANDLE_T hUsb, uint32_t EPNum)
Function to reset selected USB endpoint.
This function flushes the endpoint buffers and resets data toggle logic.
Parameters:
1. hUsb = Handle to the USB device stack.
2. EPNum = Endpoint number as per USB specification. ie. An EP1_IN is represented by 0x81
number.
Returns:
Nothing.

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Table 595. USBD_HW_API class structure
Member

Description

SetStallEP

void(*void USBD_HW_API::SetStallEP)(USBD_HANDLE_T hUsb, uint32_t EPNum)
Function to STALL selected USB endpoint.
Generates STALL signalling for requested endpoint.
Parameters:
1. hUsb = Handle to the USB device stack.
2. EPNum = Endpoint number as per USB specification. ie. An EP1_IN is represented by 0x81
number.
Returns:
Nothing.

ClrStallEP

void(*void USBD_HW_API::ClrStallEP)(USBD_HANDLE_T hUsb, uint32_t EPNum)
Function to clear STALL state for the requested endpoint.
This function clears STALL state for the requested endpoint.
Parameters:
1. hUsb = Handle to the USB device stack.
2. EPNum = Endpoint number as per USB specification. ie. An EP1_IN is represented by 0x81
number.
Returns:
Nothing.

SetTestMode

ErrorCode_t(*ErrorCode_t USBD_HW_API::SetTestMode)(USBD_HANDLE_T hUsb, uint8_t mode)
Function to set high speed USB device controller in requested test mode.
USB-IF requires the high speed device to be put in various test modes for electrical testing. This USB
device stack calls this function whenever it receives USB_REQUEST_CLEAR_FEATURE request for
USB_FEATURE_TEST_MODE. Users can put the device in test mode by directly calling this function.
Returns ERR_USBD_INVALID_REQ when device controller is full-speed only.
Parameters:
1. hUsb = Handle to the USB device stack.
2. mode = Test mode defined in USB 2.0 electrical testing specification.
Returns:
Returns ErrorCode_t type to indicate success or error condition.
Return values:
1. LPC_OK(0) = - On success
2. ERR_USBD_INVALID_REQ(0x00040001) = - Invalid test mode or Device controller is full-speed
only.

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Table 595. USBD_HW_API class structure
Member

Description

ReadEP

uint32_t(*uint32_t USBD_HW_API::ReadEP)(USBD_HANDLE_T hUsb, uint32_t EPNum, uint8_t *pData)
Function to read data received on the requested endpoint.
This function is called by USB stack and the application layer to read the data received on the
requested endpoint.
Parameters:
1. hUsb = Handle to the USB device stack.
2. EPNum = Endpoint number as per USB specification. ie. An EP1_IN is represented by 0x81
number.
3. pData = Pointer to the data buffer where data is to be copied.
Returns:
Returns the number of bytes copied to the buffer.

ReadReqEP

uint32_t(*uint32_t USBD_HW_API::ReadReqEP)(USBD_HANDLE_T hUsb, uint32_t EPNum, uint8_t *pData, uint32_t len)
Function to queue read request on the specified endpoint.
This function is called by USB stack and the application layer to queue a read request on the specified
endpoint.
Parameters:
1. hUsb = Handle to the USB device stack.
2. EPNum = Endpoint number as per USB specification. ie. An EP1_IN is represented by 0x81
number.
3. pData = Pointer to the data buffer where data is to be copied. This buffer address should be
accessible by USB DMA master.
4. len = Length of the buffer passed.
Returns:
Returns the length of the requested buffer.

ReadSetupPkt

uint32_t(*uint32_t USBD_HW_API::ReadSetupPkt)(USBD_HANDLE_T hUsb, uint32_t EPNum, uint32_t *pData)
Function to read setup packet data received on the requested endpoint.
This function is called by USB stack and the application layer to read setup packet data received on the
requested endpoint.
Parameters:
1. hUsb = Handle to the USB device stack.
2. EPNum = Endpoint number as per USB specification. ie. An EP0_IN is represented by 0x80
number.
3. pData = Pointer to the data buffer where data is to be copied.
Returns:
Returns the number of bytes copied to the buffer.

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Table 595. USBD_HW_API class structure
Member

Description

WriteEP

uint32_t(*uint32_t USBD_HW_API::WriteEP)(USBD_HANDLE_T hUsb, uint32_t EPNum, uint8_t *pData, uint32_t cnt)
Function to write data to be sent on the requested endpoint.
This function is called by USB stack and the application layer to send data on the requested endpoint.
Parameters:
1. hUsb = Handle to the USB device stack.
2. EPNum = Endpoint number as per USB specification. ie. An EP1_IN is represented by 0x81
number.
3. pData = Pointer to the data buffer from where data is to be copied.
4. cnt = Number of bytes to write.
Returns:
Returns the number of bytes written.

WakeUp

void(*void USBD_HW_API::WakeUp)(USBD_HANDLE_T hUsb)
Function to generate resume signaling on bus for remote host wake-up.
This function is called by application layer to remotely wake up host controller when system is in
suspend state. Application should indicate this remote wake up capability by setting
USB_CONFIG_REMOTE_WAKEUP in bmAttributes of Configuration Descriptor. Also this routine will
generate resume signalling only if host enables USB_FEATURE_REMOTE_WAKEUP by sending
SET_FEATURE request before suspending the bus.
Parameters:
1. hUsb = Handle to the USB device stack.
Returns:
Nothing.

EnableEvent

ErrorCode_t(* USBD_HW_API::EnableEvent)(USBD_HANDLE_T hUsb, uint32_t EPNum, uint32_t event_type, uint32_t
enable)

27.5.35 USBD_MSC_API
MSC class API functions structure.This module exposes functions which interact directly
with USB device controller hardware.

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Table 596. USBD_MSC_API class structure
Member

Description

GetMemSize

uint32_t(*uint32_t USBD_MSC_API::GetMemSize)(USBD_MSC_INIT_PARAM_T *param)
Function to determine the memory required by the MSC function driver module.
This function is called by application layer before calling pUsbApi->msc->Init(), to allocate
memory used by MSC function driver module. The application should allocate the memory
which is accessible by USB controller/DMA controller.
Remark: Some memory areas are not accessible by all bus masters.
Parameters:
1. param = Structure containing MSC function driver module initialization parameters.
Returns:
Returns the required memory size in bytes.

init

ErrorCode_t(*ErrorCode_t USBD_MSC_API::init)(USBD_HANDLE_T hUsb, USBD_MSC_INIT_PARAM_T
*param)
Function to initialize MSC function driver module.
This function is called by application layer to initialize MSC function driver module.
Parameters:
1. hUsb = Handle to the USB device stack.
2. param = Structure containing MSC function driver module initialization parameters.
Returns:
Returns ErrorCode_t type to indicate success or error condition.
Return values:
1. LPC_OK = On success
2. ERR_USBD_BAD_MEM_BUF = Memory buffer passed is not 4-byte aligned or smaller
than required.
3. ERR_API_INVALID_PARAM2 = Either MSC_Write() or MSC_Read() or MSC_Verify()
callbacks are not defined.
4. ERR_USBD_BAD_INTF_DESC = Wrong interface descriptor is passed.
5. ERR_USBD_BAD_EP_DESC = Wrong endpoint descriptor is passed.

27.5.36 USBD_MSC_INIT_PARAM
Mass Storage class function driver initialization parameter data structure.

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Table 597. USBD_MSC_INIT_PARAM class structure
Member

Description

mem_base

uint32_t USBD_MSC_INIT_PARAM::mem_base
Base memory location from where the stack can allocate data and buffers.
Remark: The memory address set in this field should be accessible by USB DMA controller.
Also this value should be aligned on 4 byte boundary.

mem_size

uint32_t USBD_MSC_INIT_PARAM::mem_size
The size of memory buffer which stack can use.
Remark: The mem_size should be greater than the size returned by
USBD_MSC_API::GetMemSize() routine.

InquiryStr

uint8_t * USBD_MSC_INIT_PARAM::InquiryStr
Pointer to the 28 character string. This string is sent in response to the SCSI Inquiry
command.
Remark: The data pointed by the pointer should be of global scope.

BlockCount

uint32_t USBD_MSC_INIT_PARAM::BlockCount
Number of blocks present in the mass storage device

BlockSize

uint32_t USBD_MSC_INIT_PARAM::BlockSize
Block size in number of bytes

MemorySize

uint32_t USBD_MSC_INIT_PARAM::MemorySize
Memory size in number of bytes

intf_desc

uint8_t * USBD_MSC_INIT_PARAM::intf_desc
Pointer to the interface descriptor within the descriptor array (

MSC_Write

void(*void(* USBD_MSC_INIT_PARAM::MSC_Write)(uint32_t offset, uint8_t **src, uint32_t length))(uint32_t
offset, uint8_t **src, uint32_t length)
MSC Write callback function.
This function is provided by the application software. This function gets called when host
sends a write command.
Parameters:
1. offset = Destination start address.
2. src = Pointer to a pointer to the source of data. Pointer-to-pointer is used to implement
zero-copy buffers. See Zero-Copy Data Transfer model for more details on zero-copy
concept.
3. length = Number of bytes to be written.
Returns:
Nothing.

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Table 597. USBD_MSC_INIT_PARAM class structure
Member

Description

MSC_Read

void(*void(* USBD_MSC_INIT_PARAM::MSC_Read)(uint32_t offset, uint8_t **dst, uint32_t length))(uint32_t
offset, uint8_t **dst, uint32_t length)
MSC Read callback function.
This function is provided by the application software. This function gets called when host
sends a read command.
Parameters:
1. offset = Source start address.
2. dst = Pointer to a pointer to the source of data. The MSC function drivers implemented in
stack are written with zero-copy model. Meaning the stack doesn't make an extra copy of
buffer before writing/reading data from USB hardware FIFO. Hence the parameter is
pointer to a pointer containing address buffer (uint8_t** dst). So that the user application
can update the buffer pointer instead of copying data to address pointed by the
parameter. /note The updated buffer address should be access able by USB DMA
master. If user doesn't want to use zero-copy model, then the user should copy data to
the address pointed by the passed buffer pointer parameter and shouldn't change the
address value. See Zero-Copy Data Transfer model for more details on zero-copy
concept.
3. length = Number of bytes to be read.
Returns:
Nothing.

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Chapter 27: LPC43xx/LPC43Sxx USB API

Table 597. USBD_MSC_INIT_PARAM class structure
Member

Description

MSC_Verify

ErrorCode_t(* USBD_MSC_INIT_PARAM::MSC_Verify)(uint32_t offset, uint8_t buf[], uint32_t length)
MSC Verify callback function.
This function is provided by the application software. This function gets called when host
sends a verify command. The callback function should compare the buffer with the
destination memory at the requested offset and
Parameters:
1. offset = Destination start address.
2. buf = Buffer containing the data sent by the host.
3. length = Number of bytes to verify.
Returns:
Returns ErrorCode_t type to indicate success or error condition.
Return values:
1. LPC_OK = If data in the buffer matches the data at destination
2. ERR_FAILED = At least one byte is different.

MSC_GetWriteBuf

void(*void(* USBD_MSC_INIT_PARAM::MSC_GetWriteBuf)(uint32_t offset, uint8_t **buff_adr, uint32_t
length))(uint32_t offset, uint8_t **buff_adr, uint32_t length)
Optional callback function to optimize MSC_Write buffer transfer.
This function is provided by the application software. This function gets called when host
sends SCSI_WRITE10/SCSI_WRITE12 command. The callback function should update the
Parameters:
1. offset = Destination start address.
2. buf = Buffer containing the data sent by the host.
3. length = Number of bytes to write.
Returns:
Nothing.

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Chapter 27: LPC43xx/LPC43Sxx USB API

Table 597. USBD_MSC_INIT_PARAM class structure
Member

Description

MSC_Ep0_Hdlr

ErrorCode_t(* USBD_MSC_INIT_PARAM::MSC_Ep0_Hdlr)(USBD_HANDLE_T hUsb, void *data, uint32_t
event)
Optional user overridable function to replace the default MSC class handler.
The application software could override the default EP0 class handler with their own by
providing the handler function address as this data member of the parameter structure.
Application which like the default handler should set this data member to zero before calling
the USBD_MSC_API::Init().
Remark:
Parameters:
1. hUsb = Handle to the USB device stack.
2. data = Pointer to the data which will be passed when callback function is called by the
stack.
3. event = Type of endpoint event. See USBD_EVENT_T for more details.
Returns:
The call back should returns ErrorCode_t type to indicate success or error condition.
Return values:
1. LPC_OK = On success.
2. ERR_USBD_UNHANDLED = Event is not handled hence pass the event to next in line.
3. ERR_USBD_xxx = For other error conditions.

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User manual

28.1 How to read this chapter
The Ethernet controller is available on parts LPC437x/LPC43S7x, LPC436x/LPC43S6x,
LPC435x/LPC43S5x, and LPC433x/LPC43S3x.
The MII is not available on the LQFP144 and TFBGA100 packages.

28.2 Basic configuration
The Ethernet controller is configured as follows:

•
•
•
•
•

See Table 598 for clocking and power control.
The Ethernet is reset by the ETHERNET_RST (reset # 22).
The Ethernet interrupt is connected to interrupt slot # 5 in the NVIC.
The Ethernet wake-up packet indicator is connected to slot # 8 in the event router.
Set the Ethernet mode to RMII or MII in the CREG6 register in the CREG block (see
Table 104).

Table 598. Ethernet clocking and power control

Ethernet
register
interface clock

Base clock

Branch
clock

Operating
frequency

BASE_M4_CLK

CLK_M4_
up to
ETHERNET 204 MHz

Notes
-

28.3 Features
•
•
•
•
•
•

10/100 Mbit/s
DMA support
IEEE 1588 Time stamping block
IEEE 1588 advanced Time stamp support (IEEE 1588-2008 v2)
Power management remote wake-up frame and magic packet detection
Supports both full-duplex and half-duplex operation
– Supports CSMA/CD Protocol for half-duplex operation.
– Supports IEEE 802.3x flow control for full-duplex operation.
– Optional forwarding of received pause control frames to the user application in
full-duplex operation.
– Back-pressure support for half-duplex operation.
– Automatic transmission of zero-quanta pause frame on deassertion of flow control
input in full-duplex operation.

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Chapter 28: LPC43xx/LPC43Sxx Ethernet

28.4 General description
The Ethernet block enables a host to transmit and receive data over Ethernet in
compliance with the IEEE 802.3-2005 standard. The Ethernet interface contains a full
featured 10 Mbps or 100 Mbps Ethernet MAC (Media Access Controller) designed to
provide optimized performance through the use of DMA hardware acceleration.
Features include a generous suite of control registers, half or full duplex operation, flow
control, control frames, hardware acceleration for transmit retry, receive packet filtering
and wake-up on LAN activity, supporting both Wake-Up and Magic Packet frames.
Automatic frame transmission and reception with Scatter-Gather DMA off-loads many
operations from the CPU.
Additional features such as IEEE 1588 Time Stamping (IEEE 1588-2002) and IEEE
Advanced Time Stamp support (IEEE 1588-2008 v2) enrich the list of supported features.
The Ethernet block is an AHB master connected to the AHB Multilayer Matrix and has
access to internal SRAM and memory connected to the External Memory Controller for
Ethernet data, control, and status information. Other AHB traffic in the LPC43xx can take
place using other masters, effectively separating Ethernet activity from the rest of the
system.
The Ethernet block interfaces with an off-chip Ethernet PHY using the MII (Media
Independent Interface) or RMII (reduced MII) protocol and with the on-chip MIIM (Media
Independent Interface Management) serial bus.

LPC43xx

AHB
Master
Interface

TxFIFO RxFIFO
(256 B) (256 B)

DMA

TxFC

RxFC
PHY
Interface
EMAC

DMA
CSR

AHB
Slave
Interface

OMR
Register

(RMII/MII)

RMII/MII

PHY

MAC
CSR

Ethernet core
Ethernet MAC Transaction Layer (MTL)
Ethernet DMA

Fig 78. Ethernet block diagram
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Chapter 28: LPC43xx/LPC43Sxx Ethernet

28.5 Pin description
Table 599. Ethernet pin description
Pin function

Direction

Description

ENET_MDIO

I/O

Ethernet MIIM Data Input and Output.

ENET_MDC

O

Ethernet MIIM Clock.

I

Ethernet Receive Data.

MIIM interface

RMII interface
ENET_RXD[1:0]
ENET_TXD[1:0]

O

Ethernet Transmit Data.

ENET_RX_DV

I

Ethernet Receive Data Valid.

ENET_REF_CLK

I

Ethernet Reference Clock.

ENET_TX_EN

O

Ethernet Transmit Data Enable.

ENET_RXD[3:0]

I

Ethernet Receive Data.

ENET_TXD[3:0]

O

Ethernet Transmit Data.

ENET_COL

I

Ethernet Collision detect.

MII interface

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ENET_CRS

I

Ethernet Carrier Sense.

ENET_TX_ER

O

Ethernet Transmit Error.

ENET_TX_CLK

I

Ethernet Transmit Clock.

ENET_RX_CLK

I

Ethernet Receive Clock.

ENET_RX_ER

I

Ethernet Receive Error.

ENET_TX_EN

O

Ethernet Transmit Enable.

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28.6 Register description
Table 600. Register overview: Ethernet MAC and DMA (base address 0x4001 0000)
Name

Access

Address
offset

Description

Reset value

Reference

MAC_CONFIG

R/W

0x0000

MAC_FRAME_FILTER

R/W

0x0004

MAC configuration register

0x0000 8000

Table 601

MAC frame filter

0x0000 0000

Table 602

MAC_HASHTABLE_HIGH

R/W

0x0008

Hash table high register

0x0000 0000

Table 603

MAC_HASHTABLE_LOW

R/W

0x000C

Hash table low register

0x0000 0000

Table 604

MAC_MII_ADDR

R/W

0x0010

MII address register

0x0000 0000

Table 605

MAC_MII_DATA

R/W

0x0014

MII data register

0x0000 0000

Table 607

MAC_FLOW_CTRL

R/W

0x0018

Flow control register

0x0000 0000

Table 608

MAC_VLAN_TAG

R/W

0x001C

VLAN tag register

0x0000 0000

Table 609

-

-

0x0020

Reserved

-

-

MAC_DEBUG

RO

0x0024

Debug register

0x0000 0000

Table 610

MAC_RWAKE_FRFLT

R/W

0x0028

Remote wake-up frame filter 0x0000 0000

Table 611

MAC_PMT_CTRL_STAT

R/W

0x002C

PMT control and status

0x0000 0000

Table 612

-

-

0x0030 0x0034

Reserved

-

-

MAC_INTR

RO

0x0038

Interrupt status register

0x0000 0000

Table 613

MAC_INTR_MASK

R/W

0x003C

Interrupt mask register

0x0000 0000

Table 614

MAC_ADDR0_HIGH

R/W

0x0040

MAC address 0 high register 0x8000 FFFF

Table 615

MAC_ADDR0_LOW

R/W

0x0044

MAC address 0 low register 0xFFFF FFFF

Table 616

-

-

0x0048 0x06FC

Reserved

-

-

MAC_TIMESTP_CTRL

R/W

0x0700

Time stamp control register

0x0000 2000

Table 617

SUBSECOND_INCR

R/W

0x0704

Sub-second increment
register

0x0000 0000

Table 619

SECONDS

RO

0x0708

System time seconds
register

0x0000 0000

Table 620

NANOSECONDS

RO

0x070C

System time nanoseconds
register

0x0000 0000

Table 621

SECONDSUPDATE

R/W

0x0710

System time seconds
update register

0x0000 0000

Table 622

NANOSECONDSUPDATE

R/W

0x0714

System time nanoseconds
update register

0x0000 0000

Table 623

ADDEND

R/W

0x0718

Time stamp addend register 0x0000 0000

Table 624

TARGETSECONDS

R/W

0x071C

Target time seconds register 0x0000 0000

Table 625

TARGETNANOSECONDS

R/W

0x0720

Target time nanoseconds
register

0x0000 0000

Table 626

HIGHWORD

R/W

0x0724

System time higher word
seconds register

0x0000 0000

Table 627

TIMESTAMPSTAT

RO

0x0728

Time stamp status register

0x0000 0000

Table 628

0x072C 0x0FFC

Reserved

0x1000

Bus Mode Register

DMA_BUS_MODE
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Chapter 28: LPC43xx/LPC43Sxx Ethernet

Table 600. Register overview: Ethernet MAC and DMA (base address 0x4001 0000)
Name

Access

Address
offset

Description

Reset value

Reference

DMA_TRANS_POLL_DEMAND

R/W

0x1004

Transmit poll demand
register

0x0000 0000

Table 631

DMA_REC_POLL_DEMAND

R/W

0x1008

Receive poll demand
register

0x0000 0000

Table 632

DMA_REC_DES_ADDR

R/W

0x100C

Receive descriptor list
address register

0x0000 0000

Table 633

DMA_TRANS_DES_ADDR

R/W

0x1010

Transmit descriptor list
address register

0x0000 0000

Table 634

DMA_STAT

R/W

0x1014

Status register

0x0000 0000

Table 635

DMA_OP_MODE

R/W

0x1018

Operation mode register

0x0000 0000

Table 636

DMA_INT_EN

R/W

0x101C

Interrupt enable register

0x0000 0000

Table 637

DMA_MFRM_BUFOF

RO

0x1020

Missed frame and buffer
overflow register

0x0000 0000

Table 638

DMA_REC_INT_WDT

R/W

0x1024

Receive interrupt watchdog
timer register

0x0000 0000

Table 639

-

-

0x1028 0x1044

Reserved

-

-

DMA_CURHOST_TRANS_DES

RO

0x1048

Current host transmit
descriptor register

0x0000 0000

Table 640

DMA_CURHOST_REC_DES

RO

0x104C

Current host receive
descriptor register

0x0000 0000

Table 641

DMA_CURHOST_TRANS_BUF

RO

0x1050

Current host transmit buffer
address register

0x0000 0000

Table 642

DMA_CURHOST_REC_BUF

RO

0x1054

Current host receive buffer
address register

0x0000 0000

Table 643

0x1058

-

-

-

-

28.6.1 MAC Configuration register
The MAC Configuration register establishes receive and transmit operating modes.
Table 601. MAC Configuration register (MAC_CONFIG, address 0x4001 0000) bit description
Bit

Symbol

Description

Reset Access
value

1:0

-

Reserved

00

RO

2

RE

Receiver enable

0

R/W

0

R/W

When this bit is set, the receiver state machine of the MAC is enabled for receiving
frames from the MII. When this bit is reset, the MAC receive state machine is disabled
after the completion of the reception of the current frame, and will not receive any
further frames from the MII.
3

TE

Transmitter Enable
When this bit is set, the transmit state machine of the MAC is enabled for
transmission on the MII. When this bit is reset, the MAC transmit state machine is
disabled after the completion of the transmission of the current frame, and will not
transmit any further frames.

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Chapter 28: LPC43xx/LPC43Sxx Ethernet

Table 601. MAC Configuration register (MAC_CONFIG, address 0x4001 0000) bit description …continued
Bit

Symbol

Description

Reset Access
value

4

DF

Deferral Check

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

RO

When this bit is set, the deferral check function is enabled in the MAC. The MAC will
issue a Frame Abort status, along with the excessive deferral error bit set in the
transmit frame status when the transmit state machine is deferred for more than
24,288 bit times in 10/100-Mbps mode. If the Core is configured for 1000 Mbps
operation, or if the Jumbo frame mode is enabled in 10/100-Mbps mode, the
threshold for deferral is 155,680 bits times. Deferral begins when the transmitter is
ready to transmit, but is prevented because of an active CRS (carrier sense) signal on
the MII. Defer time is not cumulative. If the transmitter defers for 10,000 bit times,
then transmits, collides, backs off, and then has to defer again after completion of
back-off, the deferral timer resets to 0 and restarts.
When this bit is reset, the deferral check function is disabled and the MAC defers until
the CRS signal goes inactive. This bit is applicable only in Half-Duplex mode and is
reserved (RO) in Full-Duplex-only configuration.
6:5

BL

Back-Off Limit
The Back-Off limit determines the random integer number (r) of slot time delays
(4,096 bit times for 1000 Mbps and 512 bit times for 10/100 Mbps) the MAC waits
before rescheduling a transmission attempt during retries after a collision. This bit is
applicable only to Half-Duplex mode and is reserved (RO) in Full-Duplex-only
configuration.

•
•
•
•

00: k = min (n, 10)
01: k = min (n, 8)
10: k = min (n, 4)
11: k = min (n, 1)

where n = retransmission attempt. The random integer r takes the value in the range
0  r  2k.
7

ACS

Automatic Pad/CRC Stripping
When this bit is set, the MAC strips the Pad/FCS field on incoming frames only if the
length’s field value is less than or equal to 1,500 bytes. All received frames with
length field greater than or equal to 1,501 bytes are passed to the application without
stripping the Pad/FCS field.
When this bit is reset, the MAC will pass all incoming frames to the Host unmodified.

8

-

Link Up/Down
Indicates whether the link is up or down during the transmission of configuration in
SMII interface:
0 = Link down
1 = Link up

9

DR

Disable Retry
When this bit is set, the MAC will attempt only 1 transmission. When a collision occurs
on the MII, the MAC will ignore the current frame transmission and report a Frame
Abort with excessive collision error in the transmit frame status.
When this bit is reset, the MAC will attempt retries based on the settings of BL. This
bit is applicable only to Half-Duplex mode and is reserved (RO with default value) in
Full- Duplex-only configuration.

10

-

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Table 601. MAC Configuration register (MAC_CONFIG, address 0x4001 0000) bit description …continued
Bit

Symbol

Description

Reset Access
value

11

DM

Duplex Mode

0

R/W

0

R/W

0

R/W

When this bit is set, the MAC operates in a Full-Duplex mode where it can transmit
and receive simultaneously.
12

LM

Loopback Mode
When this bit is set, the MAC operates in loopback mode at MII. The MII Receive
clock input is required for the loopback to work properly, as the Transmit clock is not
looped-back internally.

13

DO

Disable Receive Own
When this bit is set, the MAC disables the reception of frames in Half-Duplex mode.
When this bit is reset, the MAC receives all packets that are given by the PHY while
transmitting.
This bit is not applicable if the MAC is operating in Full-Duplex mode.

14

FES

0

Speed
Indicates the speed in Fast Ethernet (MII) mode:
0 = 10 Mbps
1 = 100 Mbps

15

PS

Port select

1

RO

0

R/W

000

R//W

0

R/W

0

RO

1 = MII (100 Mbp) - this is the only allowed value.
16

DCRS

Disable carrier sense during transmission
When set high, this bit makes the MAC transmitter ignore the MII CRS signal during
frame transmission in Half-Duplex mode. This request results in no errors generated
due to Loss of Carrier or No Carrier during such transmission. When this bit is low, the
MAC transmitter generates such errors due to Carrier Sense and will even abort the
transmissions.

19:17

IFG

Inter-frame gap
These bits control the minimum IFG between frames during transmission.
000 = 96 bit times
001 = 88 bit times
010 = 80 bit times
...
000 = 40 bit times
Note that in Half-Duplex mode, the minimum IFG can be configured for 64 bit times
(IFG = 100) only. Lower values are not considered

20

JE

Jumbo Frame Enable
When this bit is set, MAC allows Jumbo frames of 9,018 bytes (9,022 bytes for VLAN
tagged frames) without reporting a giant frame error in the receive frame status.

21

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Table 601. MAC Configuration register (MAC_CONFIG, address 0x4001 0000) bit description …continued
Bit

Symbol

Description

Reset Access
value

22

JD

Jabber Disable

0

R/W

0

R/W

0x00

RO

When this bit is set, the MAC disables the jabber timer on the transmitter, and can
transfer frames of up to 16,384 bytes.
When this bit is reset, the MAC cuts off the transmitter if the application sends out
more than 2,048 bytes of data (10,240 if JE is set high) during transmission.
23

WD

Watchdog Disable
When this bit is set, the MAC disables the watchdog timer on the receiver, and can
receive frames of up to 16,384 bytes.
When this bit is reset, the MAC allows no more than 2,048 bytes (10,240 if JE is set
high) of the frame being received and cuts off any bytes received after that.

31:24

-

Reserved.

28.6.2 MAC Frame filter register
The MAC Frame Filter register contains the filter controls for receiving frames. Some of
the controls from this register go to the address check block of the MAC, which performs
the first level of address filtering. The second level of filtering is performed on the
incoming frame, based on other controls such as Pass Bad Frames and Pass Control
Frames.
If the hash table filter is enabled for unicast or multicast, then the perfect filter is disabled
unless bit 10 is set in this register.
See Section 28.7.1 for examples of how to configure the hash filter.
Table 602. MAC Frame filter register (MAC_FRAME_FILTER, address 0x4001 0004) bit description
Bit

Symbol

Description

Reset Access
value

0

PR

Promiscuous Mode

0

R/W

0

R/W

0

R/W

0

R/W

When this bit is set, the Address Filter module passes all incoming frames regardless
of its destination or source address. The SA/DA Filter Fails status bits of the Receive
Status Word will always be cleared when PR is set.
1

HUC

Hash Unicast
When set, MAC performs destination address filtering of unicast frames according to
the hash table. When reset, the MAC performs a perfect destination address filtering
for unicast frames, that is, it compares the DA field with the values programmed in DA
registers.

2

HMC

Hash Multicast
When set, MAC performs destination address filtering of received multicast frames
according to the hash table. When reset, the MAC performs a perfect destination
address filtering for multicast frames, that is, it compares the DA field with the values
programmed in DA registers.

3

DAIF

DA Inverse Filtering
When this bit is set, the Address Check block operates in inverse filtering mode for
the DA address comparison for both unicast and multicast frames.
When reset, normal filtering of frames is performed.

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Chapter 28: LPC43xx/LPC43Sxx Ethernet

Table 602. MAC Frame filter register (MAC_FRAME_FILTER, address 0x4001 0004) bit description …continued
Bit

Symbol

Description

Reset Access
value

4

PM

Pass All Multicast

0

R/W

0

R/W

00

R/W

When set, this bit indicates that all received frames with a multicast destination
address (first bit in the destination address field is '1') are passed.
When reset, filtering of multicast frame depends on HMC bit.
5

DBF

Disable Broadcast Frames
When this bit is set, the AFM module filters all incoming broadcast frames.
When this bit is reset, the AFM module passes all received broadcast frames.

7:6

PCF

Pass Control Frames
These bits control the forwarding of all control frames (including unicast and multicast
PAUSE frames). Note that the processing of PAUSE control frames depends only on
RFE of the Flow Control Register.
00 = MAC filters all control frames from reaching the application.
01 = MAC forwards all control frames except PAUSE control frames to application
even if they fail the Address filter.
10 = MAC forwards all control frames to application even if they fail the Address Filter.
11 = MAC forwards control frames that pass the Address Filter.

8

-

Reserved.

-

-

9

-

Reserved.

-

-

10

HPF

Hash or perfect filter

0

R/W

When set, this bit configures the address filter to pass a frame if it matches either the
perfect filtering or the hash filtering as set by HMC or HUC bits. When low and if the
HUC/HMC bit is set, the frame is passed only if it matches the Hash filter.
30:11

-

Reserved

0

RO

31

RA

Receive all

0

R/W

When this bit is set, the MAC Receiver module passes to the Application all frames
received irrespective of whether they pass the address filter. The result of the SA/DA
filtering is updated (pass or fail) in the corresponding bits in the Receive Status Word.
When this bit is reset, the Receiver module passes to the Application only those
frames that pass the SA/DA address filter.

28.6.3 MAC Hash table high register
The 64-bit Hash table is used for group address filtering. For hash filtering, the contents of
the destination address in the incoming frame is passed through the CRC logic, and the
upper 6 bits of the CRC register are used to index the contents of the Hash table. The
most significant bit determines the register to be used (Hash Table High/Hash Table Low),
and the other 5 bits determine which bit within the register. A hash value of 00000 selects
Bit 0 of the selected register, and a value of 11111 selects Bit 31 of the selected register.
For example, if the DA of the incoming frame is received as 0x1F52419CB6AF (0x1F is
the first byte received on MII interface), then the internally calculated 6-bit Hash value is
0x2C and the HTH register bit[12] is checked for filtering. If the DA of the incoming frame
is received as 0xA00A98000045, then the calculated 6- bit Hash value is 0x07 and the
HTL register bit[7] is checked for filtering.

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If the corresponding bit value of the register is 1, the frame is accepted. Otherwise, it is
rejected. If the PM (Pass All Multicast) bit is set in the MAC_CONFIG register, then all
multicast frames are accepted regardless of the multicast hash values.
If the Hash Table register is configured to be double-synchronized to the MII clock domain,
the synchronization is triggered only when Bits[31:24] (in Little-Endian mode) or Bits[7:0]
(in Big-Endian mode) of the Hash Table High/Low registers are written to. Please note that
consecutive writes to these register should be performed only after at least 4 clock cycles
in the destination clock domain when double synchronization is enabled.
The Hash Table High register contains the higher 32 bits of the Hash table.
See Section 28.7.1 for examples of how to configure the hash filter.
Table 603. MAC Hash table high register (MAC_HASHTABLE_HIGH, address 0x4001 0008) bit
description
Bit

Symbol

31:0

HTH

Description

Reset Access
value

Hash table high

0

R/W

This field contains the upper 32 bits of Hash table.

28.6.4 MAC Hash table low register
The Hash Table Low register contains the lower 32 bits of the Hash table.
See Section 28.7.1 for examples of how to configure the hash filter.
Table 604. MAC Hash table low register (MAC_HASHTABLE_LOW, address 0x4001 0008) bit
description
Bit

Symbol

31:0

HTL

Description

Reset Access
value

Hash table low

0

R/W

This field contains the upper 32 bits of Hash table.

28.6.5 MAC MII Address register
The MII Address register controls the management cycles to the external PHY through the
management interface.

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Table 605. MAC MII Address register (MAC_MII_ADDR, address 0x4001 0010) bit description
Bit

Symbol

Description

Reset Access
value

0

GB

MII busy
This register field can be read by the application (Read), can be set to 1 by the
application with a register write of 1 (Write Set), and is cleared to 0 by the core (Self
Clear). The application cannot clear this type of field, and a register write of 0 to this
bit has no effect on this field.

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

RO

This bit should read a logic 0 before writing to this register and the MAC_MII_DATA
register. This bit must also be set to 0 during a Write to this register. During a PHY
register access, this bit will be set to 1 by the Application to indicate that a Read or
Write access is in progress. The MAC_MII_DATA register should be kept valid until
this bit is cleared by the MAC during a PHY Write operation. The MAC_MII_DATA
register is invalid until this bit is cleared by the MAC during a PHY Read operation.
This register should not be written to until this bit is cleared.
1

W

MII write
When set, this bit tells the PHY that this will be a Write operation using the MII Data
register. If this bit is not set, this will be a Read operation, placing the data in the MII
Data register.

5:2

CR

CSR clock range
The CSR Clock Range selection determines the frequency of the MDC clock. The
suggested range of CLK_M4_ETHERNET frequency applicable for each value below
(when Bit[5] = 0) ensures that the MDC clock is approximately between the frequency
range 1.0 MHz - 2.5 MHz.
When bit 5 is set, you can achieve MDC clock of frequency higher than the IEEE
802.3 specified frequency limit of 2.5 MHz and program a clock divider of lower value.
For example, when CLK_M4_ETHERNET is of frequency 100 MHz and you program
these bits as 1010, then the resultant MDC clock will be of 12.5 MHz which is outside
the limit of IEEE 802.3 specified range. Program the values given below only if the
interfacing chips supports faster MDC clocks.
See Table 606 for bit values.

10:6

GR

MII register
These bits select the desired MII register in the selected PHY device.

15:11

PA

Physical layer address
This field tells which of the 32 possible PHY devices are being accessed.

31:16

-

Reserved
Table 606. CSR clock range values

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Bits 5:2

CLK_M4_ETHERNET

MDC clock

0000

60 - 100 MHz

CLK_M4_ETHERNET/42

0001

100 - 150 MHz

CLK_M4_ETHERNET/62

0010

20 - 35 MHz

CLK_M4_ETHERNET/16

0011

35 - 60 MHz

CLK_M4_ETHERNET/26

0100

150 - 250 MHz

CLK_M4_ETHERNET/102

0101

250 - 300 MHz

CLK_M4_ETHERNET/124

0110, 0111

Reserved

-

1000

-

CLK_M4_ETHERNET/42

1001

-

CLK_M4_ETHERNET/62

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Table 606. CSR clock range values
Bits 5:2

CLK_M4_ETHERNET

MDC clock

1010

-

CLK_M4_ETHERNET/16

1011

-

CLK_M4_ETHERNET/26

1100

-

CLK_M4_ETHERNET/102

1101

-

CLK_M4_ETHERNET/124

1110

-

CLK_M4_ETHERNET/42

1111

-

CLK_M4_ETHERNET/62

28.6.6 MAC MII Data register
The MII Data register stores Write data to be written to the PHY register located at the
address specified in the MAC_MII_ADDR register. This register also stores Read data
from the PHY register located at the address specified by the MAC_MII_ADDR register.
Table 607. MII Data register (MAC_MII_DATA, address 0x4001 0014) bit description
Bit

Symbol

15:0

GD

Description

Reset Access
value

MII data

0

R/W

0

RO

This contains the 16-bit data value read from the PHY after a
Management Read operation or the 16-bit data value to be
written to the PHY before a Management Write operation.
31:16

-

Reserved

28.6.7 MAC Flow control register
The Flow Control register controls the generation and reception of the Control (Pause
Command) frames by the MAC’s Flow control module. A Write to a register with the Busy
bit set to 1 triggers the Flow Control block to generate a Pause Control frame. The fields
of the control frame are selected as specified in the 802.3x specification, and the Pause
Time value from this register is used in the Pause Time field of the control frame. The
Busy bit remains set until the control frame is transferred onto the cable. The Host must
make sure that the Busy bit is cleared before writing to the register.

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Table 608. MAC Flow control register (MAC_FLOW_CTRL, address 0x4001 0018) bit description
Bit

Symbol

Description

Reset Access
value

0

FCB

Flow Control Busy/Backpressure Activate
This register field can be read by the application (Read), can be set to 1 by the
application with a register write of 1 (Write Set), and is cleared to 0 by the core (Self
Clear). The application cannot clear this type of field, and a register write of 0 to this
bit has no effect on this field.

0

R/W

0

R/W

0

R/W

0

R/W

00

R/W

This bit initiates a Pause Control frame in Full-Duplex mode.
In Full-Duplex mode, this bit should be read as 0 before writing to the Flow Control
register. To initiate a Pause control frame, the Application must set this bit to 1. During
a transfer of the Control Frame, this bit will continue to be set to signify that a frame
transmission is in progress. After the completion of Pause control frame transmission,
the MAC will reset this bit to 0. The Flow Control register should not be written to until
this bit is cleared.
In Half-Duplex mode, when this bit is set (and TFE is set), then backpressure is
asserted by the MAC Core. During backpressure, when the MAC receives a new
frame, the transmitter starts sending a JAM pattern resulting in a collision. This control
register bit is logically ORed with the flow controller input signal for the backpressure
function. When the MAC is configured to Full- Duplex mode, the BPA is automatically
disabled.
1

TFE

Transmit Flow Control Enable
In Full-Duplex mode, when this bit is set, the MAC enables the flow control operation
to transmit Pause frames. When this bit is reset, the flow control operation in the MAC
is disabled, and the MAC will not transmit any Pause frames.
In Half-Duplex mode, when this bit is set, the MAC enables the back-pressure
operation. When this bit is reset, the backpressure feature is disabled.

2

RFE

Receive Flow Control Enable
When this bit is set, the MAC will decode the received Pause frame and disable its
transmitter for a specified (Pause Time) time. When this bit is reset, the decode
function of the Pause frame is disabled.

3

UP

Unicast Pause Frame Detect
When this bit is set, the MAC will detect the Pause frames with the station’s unicast
address specified in MAC Address0 High Register and MAC Address0 Low Register,
in addition to the detecting Pause frames with the unique multicast address. When
this bit is reset, the MAC will detect only a Pause frame with the unique multicast
address specified in the 802.3x standard.

5:4

PLT

Pause Low Threshold
This field configures the threshold of the PAUSE timer at which the input flow control
is checked for automatic retransmission of PAUSE Frame. The threshold values
should be always less than the Pause Time configured in Bits[31:16]. For example, if
PT = 0x100 (256 slot-times), and PLT = 01, then a second PAUSE frame is
automatically transmitted if the flow control signal is asserted at 228 (256 – 28)
slot-times after the first PAUSE frame is transmitted.

6

-

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Reserved

0x000 RO

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Table 608. MAC Flow control register (MAC_FLOW_CTRL, address 0x4001 0018) bit description …continued
Bit

Symbol

Description

Reset Access
value

7

DZPQ

Disable Zero-Quanta Pause

0

R/W

RO

When set, this bit disables the automatic generation of Zero-Quanta Pause Control
frames on the deassertion of the flow-control signal from the FIFO layer. When this bit
is reset, normal operation with automatic Zero-Quanta Pause Control frame
generation is enabled.
15:8

-

Reserved

0

31:16

PT

Pause time

0x000 R/W
0

This field holds the value to be used in the Pause Time field in the transmit control
frame. If the Pause Time bits is configured to be double-synchronized to the MII clock
domain, then consecutive writes to this register should be performed only after at
least 4 clock cycles in the destination clock domain.

28.6.8 MAC VLAN tag register
The VLAN Tag register contains the IEEE 802.1Q VLAN Tag to identify the VLAN frames.
The MAC compares the 13th and 14th bytes of the receiving frame (Length/Type) with
0x8100, and the following 2 bytes are compared with the VLAN tag; if a match occurs, it
sets the received VLAN bit in the receive frame status. The legal length of the frame is
increased from 1518 bytes to 1522 bytes.
If the VLAN Tag register is configured to be double-synchronized to the MII clock domain,
then consecutive writes to these register should be performed only after at least 4 clock
cycles in the destination clock domain.
Table 609. MAC VLAN tag register (MAC_VLAN_TAG, address 0x4001 001C) bit description
Bit

Symbol

Description

Reset Access
value

15:0

VL

VLAN Tag Identifier for Receive Frames

0x000 R/W
This contains the 802.1Q VLAN tag to identify VLAN frames, and is compared to the 0
fifteenth and sixteenth bytes of the frames being received for VLAN frames.
Bits[15:13] are the User Priority, Bit[12] is the Canonical Format Indicator (CFI) and
bits[11:0] are the VLAN tag’s VLAN Identifier (VID) field. When the ETV bit is set, only
the VID (Bits[11:0]) is used for comparison.
If VL (VL[11:0] if ETV is set) is all zeros, the MAC does not check the fifteenth and
sixteenth bytes for VLAN tag comparison, and declares all frames with a Type field
value of 0x8100 to be VLAN frames.

16

ETV

Enable 12-Bit VLAN Tag Comparison

0

R/W

When this bit is set, a 12-bit VLAN identifier, rather than the complete 16-bit VLAN
tag, is used for comparison and filtering. Bits[11:0] of the VLAN tag are compared with
the corresponding field in the received VLAN-tagged frame.
When this bit is reset, all 16 bits of the received VLAN frame’s fifteenth and sixteenth
bytes are used for comparison.
31:17

-

Reserved

0x000 RO
0

28.6.9 MAC Debug register
This debug register gives the status of all the main modules of the transmit and receive
data-paths and the FIFOs. An all-zero status indicates that the MAC core is in idle state
(and FIFOs are empty) and no activity is going on in the data-paths.
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Remark: Reset values in this register are valid only if the clocks to the Ethernet block are
present during the reset operation.
Table 610. MAC Debug register (MAC_DEBUG, address 0x4001 0024) bit description
Bit

Symbol

Description

Reset Access
value

0

RXIDLESTAT

When high, it indicates that the MAC MII receive protocol engine is actively
receiving data and not in IDLE state.

0

RO

2:1

FIFOSTAT0

When high, it indicates the active state of the small FIFO Read and Write
controllers respectively of the MAC receive Frame Controller module.

0

RO

3

-

Reserved

-

RO

4

RXFIFOSTAT1

When high, it indicates that the MTL RxFIFO Write Controller is active and
transferring a received frame to the FIFO.

0

RO

6:5

RXFIFOSTAT

State of the RxFIFO read Controller:

0

RO

00 = idle state
01 = reading frame data
10 = reading frame status (or Time stamp)
11 = flushing the frame data and status
7

-

Reserved

-

RO

9:8

RXFIFOLVL

Status of the RxFIFO Fill-level

0

RO

00 = RxFIFO Empty
01 = RxFIFO fill-level below flow-control de-activate threshold
10 = RxFIFO fill-level above flow-control activate threshold
11 = RxFIFO Full
15:10

-

Reserved

-

RO

16

TXIDLESTAT

When high, it indicates that the MAC MII transmit protocol engine is actively
transmitting data and not in IDLE state.

0

RO

18:17

TXSTAT

State of the MAC Transmit Frame Controller module:

0

RO

00 = idle
01 = Waiting for Status of previous frame or IFG/backoff period to be over
10 = Generating and transmitting a PAUSE control frame (in full duplex mode)
11 = Transferring input frame for transmission
19

PAUSE

When high, it indicates that the MAC transmitter is in PAUSE condition (in
full-duplex only) and hence will not schedule any frame for transmission.

0

RO

21:20

TXFIFOSTAT

State of the TxFIFO read Controller

0

RO

When high, it indicates that the TxFIFO Write Controller is active and
transferring data to the TxFIFO.

0

RO

00 = idle state
01 = READ state (transferring data to MAC transmitter)
10 = Waiting for TxStatus from MAC transmitter
11 = Writing the received TxStatus or flushing the TxFIFO
22

TXFIFOSTAT1

23

-

Reserved

0

RO

24

TXFIFOLVL

When high, it indicates that the TxFIFO is not empty and has some data left for 0
transmission.

RO

25

TXFIFOFULL

When high, it indicates that the TxStatus FIFO is full and hence the controller
will not be accepting any more frames for transmission.

0

RO

31:26

-

Reserved

-

RO

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28.6.10 MAC Remote wake-up frame filter register
This is the address through which the remote Wake-up Frame Filter registers
(WKUPFMFILTER) are written/read by the Application. WKUPFMFILTER is actually a
pointer to eight (not transparent) such WKUPFMFILTER registers. Eight sequential Writes
to this address (0x028) will write all WKUPFMFILTER registers. Eight sequential Reads
from this address (0x028) will read all WKUPFMFILTER registers. See Section 28.7.2.1
for details.
Remark: Do not use bit-banding for this register.
Table 611. MAC Remote wake-up frame filter register (MAC_RWAKE_FRFLT, address 0x4001
0028) bit description
Bit

Symbol

Description

Reset Access
value

31:0

ADDR

WKUPFMFILTER address

-

R/W

28.6.11 MAC PMT control and status register
The PMT control and status registers programs the request wake-up events and monitors
the wake-up events. See Section 28.7.2 for details.
Table 612. MAC PMT control and status register (MAC_PMT_CTRL_STAT, address 0x4001 002C) bit description
Bit

Symbol

Description

Reset Access
value

0

PD

Power-down
This register field can be read by the application (Read), can be set to 1 by the
application with a register write of 1 (Write Set), and is cleared to 0 by the core (Self
Clear). The application cannot clear this type of field, and a register write of 0 to this
bit has no effect on this field.

0

R/W

0

R/W

0

R/W

When set, all received frames will be dropped. This bit is cleared automatically when
a magic packet or Wake-Up frame is received, and Power-Down mode is disabled.
Frames received after this bit is cleared are forwarded to the application.This bit must
only be set when either the Magic Packet Enable or Wake- Up Frame Enable bit is set
high.
1

MPE

Magic packet enable
When set, enables generation of a power management event due to Magic Packet
reception.

2

WFE

Wake-up frame enable
When set, enables generation of a power management event due to wake-up frame
reception.

4:3

-

Reserved

00

RO

5

MPR

Magic Packet Received
This register field can be read by the application (Read), can be set to 1 by the
Ethernet core on a certain internal event (Self Set), and is automatically cleared to 0
on a register read. A register write of 0 has no effect on this field.

0

RO

When set, this bit indicates the power management event was generated by the
reception of a Magic Packet. This bit is cleared by a Read into this register.

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Table 612. MAC PMT control and status register (MAC_PMT_CTRL_STAT, address 0x4001 002C) bit description
Bit

Symbol

Description

Reset Access
value

6

WFR

Wake-up Frame Received
This register field can be read by the application (Read), can be set to 1 by the
Ethernet core on a certain internal event (Self Set), and is automatically cleared to 0
on a register read. A register write of 0 has no effect on this field.

0

RO

When set, this bit indicates the power management event was generated due to
reception of a wake-up frame. This bit is cleared by a Read into this register.
8:7

-

Reserved

0

RO

9

GU

Global Unicast

0

R/W

0x00
0000

RO

0

R/W

When set, enables any unicast packet filtered by the MAC (DAF) address recognition
to be a wake-up frame.
30:10

-

Reserved

31

WFFRPR Wake-up Frame Filter Register Pointer Reset
This register field can be read by the application (Read), can be set to 1 by the
application with a register write of 1 (Write Set), and is cleared to 0 by the core (Self
Clear). The application cannot clear this type of field, and a register write of 0 to this
bit has no effect on this field.
When set, resets the Remote Wake-up Frame Filter register pointer to 000. It is
automatically cleared after 1 clock cycle.

28.6.12 MAC Interrupt status register
The Interrupt Status register contents identify the events in the MAC-CORE that can
generate interrupt.
Table 613. MAC Interrupt status register (MAC_INTR, address 0x4001 0038) bit description
Bit

Symbol

Description

Reset Access
value

2:0

-

Reserved.

0

RO

3

PMT

PMT Interrupt Status

0

RO

0

RO

This bit is set whenever a Magic packet or Wake-on-LAN
frame is received in Power- Down mode (See bits 5 and 6 in
Table 612). This bit is cleared when both bits[6:5] are
cleared because of a read operation to the PMT Control and
Status register.
8:4

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Table 613. MAC Interrupt status register (MAC_INTR, address 0x4001 0038) bit description
Bit

Symbol

Description

Reset Access
value

9

TS

Timestamp interrupt status

0

RO

When Advanced Timestamp feature is enabled, this bit is
set when any of the following conditions is true:
• The system time value equals or exceeds the value
specified in the Target Time High and Low registers
• There is an overflow in the seconds register
This bit is cleared on reading the byte 0 of the Timestamp
Status register (Table 628).
Otherwise, when default Time stamping is enabled, this bit
when set indicates that the system time value equals or
exceeds the value specified in the Target Time registers. In
this mode, this bit is cleared after the completion of the read
of this Interrupt Status Register[9]. In all other modes, this
bit is reserved.
10

-

Reserved.

0

RO

31:11

-

Reserved

0

RO

28.6.13 MAC Interrupt mask register
The Interrupt Mask Register bits enables the user to mask the interrupt signal due to the
corresponding event in the Interrupt Status Register.
Table 614. MAC Interrupt mask register (MAC_INTR_MASK, address 0x4001 003C) bit
description
Bit

Symbol

Description

Reset Access
value

2:0

-

Reserved

0

RO

3

PMTIM

PMT Interrupt Mask

0

R/W

0

R/W

0

R/W

This bit when set, will disable the assertion of the interrupt
signal due to the setting of PMT Interrupt Status bit in
Table 613.
8:4

-

Reserved.

9

TSIM

Timestamp interrupt mask
When set, this bit disables the assertion of the interrupt
signal because of the setting of Timestamp Interrupt Status
bit in Table 613

10
31:11

-

Reserved.
Reserved

28.6.14 MAC Address 0 high register
The MAC Address 0 High register holds the upper 16 bits of the 6-byte first MAC address
of the station. Note that the first DA byte that is received on the MII interface corresponds
to the LS Byte (Bits [7:0]) of the MAC Address Low register. For example, if
0x112233445566 is received (0x11 is the first byte) on the MII as the destination address,
then the MacAddress0 Register [47:0] is compared with 0x665544332211.

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If the MAC address registers are configured to be double-synchronized to the MII clock
domains, then the synchronization is triggered only when Bits[31:24] (in Little-Endian
mode) or Bits[7:0] (in Big-Endian mode) of the MAC Address Low Register are written to.
Please note that consecutive writes to this Address Low Register should be performed
only after at least 4 clock cycles in the destination clock domain for proper synchronization
updates.
Table 615. MAC Address 0 high register (MAC_ADDR0_HIGH, address 0x4001 0040) bit
description
Bit

Symbol

15:0

A47_32

Description

Reset
value

Access

MAC Address0 [47:32]

0xFFFF R/W

This field contains the upper 16 bits (47:32) of the 6-byte
first MAC address. This is used by the MAC for filtering for
received frames and for inserting the MAC address in the
Transmit Flow Control (PAUSE) Frames.
30:16

-

Reserved

0x0000 RO

31

MO

Always 1

1

RO

28.6.15 MAC Address 0 low register
The MAC Address 0 Low register holds the lower 32 bits of the 6-byte first MAC address
of the station.
Table 616. MAC Address 0 low register (MAC_ADDR0_LOW, address 0x4001 0044) bit
description
Bit

Symbol

Description

Reset
value

Access

31:0

A31_0

MAC Address0 [31:0]

0xFFFF
FFFF

R/W

This field contains the lower 32 bits of the 6-byte first
MAC address. This is used by the MAC for filtering for
received frames and for inserting the MAC address in
the Transmit Flow Control (PAUSE) Frames.

28.6.16 MAC IEEE1588 time stamp control register
This register controls the operation of the System Time generator and the snooping of
PTP packets for time-stamping in the Receiver.

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Table 617. MAC IEEE1588 time stamp control register (MAC_TIMESTP_CTRL, address 0x4001 0700) bit description
Bit

Symbol

Description

Reset
value

Access

0

TSENA

Time stamp Enable

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

When this bit, is set the timestamping is enabled for transmit and receive
frames. When disabled timestamp is not added for transmit and receive
frames and the TimeStamp Generator is also suspended. User has to always
initialize the TimeStamp (system time) after enabling this mode.
1

TSCFUPDT

Time stamp Fine or Coarse Update
When set, indicates that the system times update to be done using fine
update method. When reset it indicates the system time stamp update to be
done using Coarse method. This bit is reserved if the fine correction option is
not enabled.

2

TSINIT

Time stamp Initialize
This register field can be read and written by the application (Read and
Write), and is cleared to 0 by the Ethernet core (Self Clear).
When set, the system time is initialized (over-written) with the value specified
in the Time stamp High Update and Time stamp Low Update registers. This
register bit should be read zero before updating it. This bit is reset once the
initialize is complete.

3

TSUPDT

Time stamp Update
This register field can be read and written by the application (Read and
Write), and is cleared to 0 by the Ethernet core (Self Clear).
When set, the system time is updated (added/subtracted) with the value
specified in the Time stamp High Update and Time stamp Low Update
registers. This register bit should be read zero before updating it. This bit is
reset once the update is completed in hardware.

4

TSTRIG

Time stamp Interrupt Trigger Enable
This register field can be read and written by the application (Read and
Write), and is cleared to 0 by the Ethernet core (Self Clear).
When set, the Time stamp interrupt is generated when the System Time
becomes greater than the value written in Target Time register. This bit is
reset after the generation of Time stamp Trigger Interrupt.

5

TSADDREG

Addend Reg Update
When set, the contents of the Time stamp Addend register is updated in the
PTP block for fine correction. This is cleared when the update is completed.
This register bit should be zero before setting it. This is a reserved bit when
only coarse correction option is selected.

7:6

-

Reserved

8

TSENALL

Enable Time stamp for All Frames
When set, the Time stamp snapshot is enabled for all frames received by the
core.

9

TSCTRLSSR

Time stamp Digital or Binary rollover control
When set, the Time stamp Low register rolls over after 0x3B9A_C9FF value
(i.e., 1 nanosecond accuracy) and increments the Time stamp (High)
seconds. When reset, the rollover value of sub-second register is
0x7FFF_FFFF. The sub-second increment has to be programmed correctly
depending on the PTP reference clock frequency and this bit value.

10

TSVER2ENA

Enable PTP packet snooping for version 2 format
When set, the PTP packets are snooped using the 1588 version 2 format
else snooped using the version 1 format.

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Table 617. MAC IEEE1588 time stamp control register (MAC_TIMESTP_CTRL, address 0x4001 0700) bit description
Bit

Symbol

Description

Reset
value

Access

11

TSIPENA

Enable Time stamp Snapshot for PTP over Ethernet frames

0

R/W

0

R/W

1

R/W

0

R/W

0

R/W

00

R/W

0

R/W

When set, the Time stamp snapshot is taken for frames which have PTP
messages in Ethernet frames (PTP over Ethernet) also. By default snapshots
are taken for UDP-IP-Ethernet PTP packets.
12

TSIPV6ENA

Enable Time stamp Snapshot for IPv6 frames
When set, the Time stamp snapshot is taken for IPv6 frames.

13

TSIPV4ENA

Enable Time stamp Snapshot for IPv4 frames
When set, the Time stamp snapshot is taken for IPv4 frames.

14

TSEVNTENA

Enable Time stamp Snapshot for Event Messages
When set, the Time stamp snapshot is taken for event messages only. When
reset snapshot is taken for all other messages except Announce,
Management and Signaling.

15

TSMSTRENA

Enable Snapshot for Messages Relevant to Master
When set, the snapshot is taken for messages relevant to master node only
else snapshot is taken for messages relevant to slave node. This is valid only
for ordinary clock and boundary clock node.

17:16

TSCLKTYPE

Select the type of clock node
The following are the options to select the type of clock node:
00 = ordinary clock
01 = boundary clock
10 = end-to-end transparent clock
11 = peer-to-peer transparent clock

18

TSENMACADDR Enable MAC address for PTP frame filtering
When set, uses the DA MAC address (that matches any MAC Address
register except the default MAC address 0) to filter the PTP frames when
PTP is sent directly over Ethernet.

31:19

Table 618 indicates the messages, for which a snapshot is taken depending on the clock,
enable master and enable snapshot for event message register settings.
Table 618. Time stamp snapshot dependency on register bits
TSCLKTYPE TSMSTRENA

TSEVNTENA

Messages for which snapshot is taken

00 or 01

x

0

SYNC, Follow_Up, Delay_Req, Delay_Resp

00 or 01

1

1

Delay_req

00 or 01

0

1

SYNC

10

N/A

0

SYNC, Follow_Up, Delay_Req, Delay_Resp

10

N/A

1

SYNC, Follow_Up

11

N/A

0

SYNC, Follow_Up, Delay_Req, Delay_Resp,
Pdelay_Req, Pdelay_Resp

11

N/A

1

SYNC, Pdelay_Req, Pdelay_Resp

28.6.17 Sub-second increment register
This register contains the 8-bit value by which the Sub-Second register is incremented.
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In Coarse Update mode (TSCFUPDT bit in Table 617), the value in this register is added
to the system time every clock cycle. In Fine Update mode, the value in this register is
added to the system time whenever the Accumulator gets an overflow.
Table 619. Sub-second increment register (SUBSECOND_INCR, address 0x4001 0704) bit
description
Bit

Symbol

Description

Reset
value

Access

7:0

SSINC

Sub-second increment value.

0

R/W

0

RO

The value programmed in this register is accumulated
with the contents of the sub-second register. For
example, to achieve an accuracy of 20 ns, the value to
be programmed is 20. (Program 0x14 with a 50 MHz
reference clock if 1 ns accuracy is selected.)
31:8

-

Reserved.

28.6.18 System time seconds register
This register contains the lower 32 bits of the seconds field of the system time.
The System Time - Seconds register, along with System Time - Nanoseconds register,
indicates the current value of the system time maintained by the core. Though it is
updated on a continuous basis, there is some delay from the actual time due to clock
domain transfer latencies.
Table 620. System time seconds register (SECONDS, address 0x4001 0708) bit description
Bit

Symbol

31:0

TSS

Description

Reset
value

Access

Time stamp second

0

R/W

The value in this field indicates the current value in
seconds of the System Time maintained by the core.

28.6.19 System time nanoseconds register
This register contains 32 bits of the nano-seconds field of the system time.

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Table 621. System time nanoseconds register (NANOSECONDS, address 0x4001 070C) bit
description
Bit

Symbol

Description

Reset
value

Access

30:0

TSSS

Time stamp sub seconds

0

RO

0

RO

The value in this field has the sub second representation
of time, with an accuracy of 0.46 nano-second. (When
TSCTRLSSR in the MAC_TIMESTAMP_CTRL register
is set, each bit represents 1 ns and the maximum value
will be 0x3B9A_C9FF, after which it rolls-over to zero).
31

PSNT

Positive or negative time
This bit indicates positive or negative time value. If the
bit is reset, it indicates that the time representation is
positive, and if it is set, it indicates negative time value.
(This bit represents the 32nd bit of the nanoseconds
value when the Advance Time stamp feature is
enabled).

28.6.20 System time seconds update register
This register contains the lower 32 bits of the seconds field to be written to, added to, or
subtracted from the System Time value.
The System Time - Seconds Update register, along with the System Time - Nanoseconds
Update register, initialize or update the system time maintained by the core. You must
write both of these registers before setting the TSINIT or TSUPDT bits in the Time stamp
Control register.
Table 622. System time seconds update register (SECONDSUPDATE, address 0x4001 0710)
bit description
Bit

Symbol

31:0

TSS

Description

Reset
value

Access

Time stamp second

0

R/W

The value in this field indicates the time, in seconds, to
be initialized or added to the system time.

28.6.21 System time nanoseconds update register
This register contains 32 bits of the nano-seconds field to be written to, added to, or
subtracted from the System Time value.

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Table 623. System time nanoseconds update register (NANOSECONDSUPDATE, address
0x4001 0714) bit description
Bit

Symbol

Description

Reset
value

Access

30:0

TSSS

Time stamp sub seconds

0

R/W

0

R/W

The value in this field has the sub second representation
of time, with an accuracy of 0.46 nano-second. (When
TSCTRLSSR is set in the Time stamp control register,
each bit represents 1 ns and the programmed value
should not exceed 0x3B9A_C9FF.)
31

ADDSUB Add or subtract time
When this bit is set, the time value is subtracted with the
contents of the update register. When this bit is reset,
the time value is added with the contents of the update
register.

28.6.22 Time stamp addend register
This register is used by the software to readjust the clock frequency linearly to match the
master clock frequency.
This register value is used only when the system time is configured for Fine Update mode
(TSCFUPDT bit in Table 617). This register content is added to a 32-bit accumulator in
every clock cycle and the system time is updated whenever the accumulator overflows.
Table 624. Time stamp addend register (ADDEND, address 0x4001 0718) bit description
Bit

Symbol

Description

Reset
value

Access

31:0

TSAR

Time stamp addend

0

R/W

This register indicates the 32-bit time value to be added
to the Accumulator register to achieve time
synchronization.

28.6.23 Target time seconds register
This register contains the higher 32 bits of time to be compared with the system time for
interrupt event generation.
The Target Time Seconds register, along with Target Time Nanoseconds register, are
used to schedule an interrupt event (TSTARGT bit in Table 628 when Advanced
Timestamping is enabled, or otherwise, TS interrupt bit in Table 613) when the system
time exceeds the value programmed in these registers.
Table 625. Target time seconds register (TARGETSECONDS, address 0x4001 071C) bit
description
Bit

Symbol

Description

Reset
value

Access

31:0

TSTR

Target time seconds register

0

R/W

This register stores the time in seconds. When the Time
stamp value matches or exceeds both Target Time
stamp registers, the MAC, if enabled, generates an
interrupt.

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28.6.24 Target time nanoseconds register
This register contains the higher 32 bits of time to be compared with the system time for
interrupt event generation.
Table 626. Target time nanoseconds register (TARGETNANOSECONDS, address 0x4001
0720) bit description
Bit

Symbol

30:0

TSTR

Description

Reset
value

Access

Target Time stamp low

0

RO

-

-

This register stores the time in (signed) nanoseconds.
When the value of the Time stamp matches the Target
Time stamp registers (both), the MAC will generate an
interrupt if enabled. (This value should not exceed
0x3B9A_C9FF when TSCTRLSSR is set in the Time
stamp control register.)
31

-

Reserved.

28.6.25 System time higher words seconds register
This register contains the most significant 16-bits of the Time stamp seconds value.
Table 627. System time higher words seconds register (HIGHWORD, address 0x4001 0724)
bit description
Bit

Symbol

Description

Reset
value

Access

15:0

TSHWR

Time stamp higher word

0

R/W

-

-

Contains the most significant 16-bits of the Time stamp
seconds value. The register is directly written to initialize
the value. This register is incremented when there is an
overflow from the 32-bits of the System Time - Seconds
register.
31:16

-

Reserved.

28.6.26 Time stamp status register
This register contains the PTP status. All bits except Bits[27:25] gets cleared after this
register is read by the host.
The register field can be read by the application (Read), can be set to 1 by the core on a
certain internal event (Self Set), and is automatically cleared to 0 on a register read. A
register write of 0 has no effect on this field.

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Table 628. Time stamp status register (TIMESTAMPSTAT, address 0x4001 0728) bit
description
Bit

Symbol

Description

Reset
value

Access

0

TSSOVF

Time stamp seconds overflow

0

R/W

0

R/W

-

-

When set, indicates that the seconds value of the Time
stamp (when supporting version 2 format) has
overflowed beyond 0xFFFF_FFFF.
1

TSTARGT Time stamp target reached
When set, indicates the value of system time is greater
or equal to the value specified in the Target Time High
and Low registers

31:2

-

Reserved.

28.6.27 DMA Bus mode register
The Bus Mode register establishes the bus operating modes for the DMA.
Table 629. DMA Bus mode register (DMA_BUS_MODE, address 0x4001 1000) bit description
Bit

Symbol

Description

Reset Access
value

0

SWR

Software reset
0
This register field can be read by the application (Read), can be set to 1 by the
application with a register write of 1 (Write Set), and is cleared to 0 by the Ethernet
core (Self Clear). The application cannot clear this type of field, and a register write of
0 to this bit has no effect on this field.

R/W

When this bit is set, the MAC DMA Controller resets all MAC Subsystem internal
registers and logic. It is cleared automatically after the reset operation has completed
in all of the core clock domains. Read a 0 value in this bit before re-programming any
register of the core.
Remark: The reset operation is completed only when all the resets in all the active
clock domains are de-asserted. Hence it is essential that all the PHY inputs clocks
(applicable for the selected PHY interface) are present for software reset completion.
1

DA

DMA arbitration scheme

0

R/W

0

R/W

0

R/W

0 = Round-robin with Rx:Tx priority given in bits [15:14]
1 = Rx has priority over Tx
6:2

DSL

Descriptor skip length
This bit specifies the number of Word to skip between two unchained descriptors. The
address skipping starts from the end of current descriptor to the start of next
descriptor. When DSL value equals zero, then the descriptor table is taken as
contiguous by the DMA, in Ring mode.

7

ATDS

Alternate descriptor size
When set, the alternate descriptor (see Section 28.7.6.3) size is increased to 32 bytes
(8 DWORDS). This is required when the Advanced Time-Stamp feature or Full IPC
Offload Engine is enabled in the receiver.
When reset, the descriptor size reverts back to 4 DWORDs (16 bytes).

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Table 629. DMA Bus mode register (DMA_BUS_MODE, address 0x4001 1000) bit description …continued
Bit

Symbol

13:8

PBL

Description

Reset Access
value

Programmable burst length

1

R/W

00

R/W

0

R/W

1

R/W

0

R/W

0

R/W

These bits indicate the maximum number of beats to be transferred in one DMA
transaction. This will be the maximum value that is used in a single block Read/Write.
The DMA will always attempt to burst as specified in PBL each time it starts a Burst
transfer on the host bus. PBL can be programmed with permissible values of 1, 2, 4,
8, 16, and 32. Any other value will result in undefined behavior. When USP is set
high, this PBL value is applicable for TxDMA transactions only.
The PBL values have the following limitations.
The maximum number of beats (PBL) possible is limited by the size of the Tx FIFO
and Rx FIFO in the MTL layer and the data bus width on the DMA. The FIFO has a
constraint that the maximum beat supported is half the depth of the FIFO, except
when specified (as given below). For different data bus widths and FIFO sizes, the
valid PBL range (including x8 mode) is provided in the following table. If the PBL is
common for both transmit and receive DMA, the minimum Rx FIFO and Tx FIFO
depths must be considered. Do not program out-of-range PBL values, because the
system may not behave properly.
15:14

PR

Rx-to-Tx priority ratio
RxDMA requests given priority over TxDMA requests in the following ratio. This is
valid only when the DA bit is reset.
00 = 1-to-1
01 = 2-to-1
10 = 3-to-1
11 = 4-to-1

16

FB

Fixed burst
This bit controls whether the AHB Master interface performs fixed burst transfers or
not. When set, the AHB will use only SINGLE, INCR4, INCR8 or INCR16 during start
of normal burst transfers. When reset, the AHB will use SINGLE and INCR burst
transfer operations.

22:17

RPBL

RxDMA PBL
These bits indicate the maximum number of beats to be transferred in one RxDMA
transaction. This will be the maximum value that is used in a single block Read/Write.
The RxDMA will always attempt to burst as specified in RPBL each time it starts a
Burst transfer on the host bus. RPBL can be programmed with permissible values of
1, 2, 4, 8, 16, and 32. Any other value will result in undefined behavior. These bits are
valid and applicable only when USP is set high.

23

USP

Use separate PBL
When set high, it configures the RxDMA to use the value configured in bits [22:17] as
PBL while the PBL value in bits [13:8] is applicable to TxDMA operations only. When
reset to low, the PBL value in bits [13:8] is applicable for both DMA engines.

24

PBL8X

8 x PBL mode
When set high, this bit multiplies the PBL value programmed (bits [22:17] and bits
[13:8]) eight times. Thus the DMA will transfer data in to a maximum of 8, 16, 32, 64,
128, and 256 beats depending on the PBL value.
Remark: This bit function is not backward compatible. Before version 3.50a, this bit
was 4xPBL.

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Table 629. DMA Bus mode register (DMA_BUS_MODE, address 0x4001 1000) bit description …continued
Bit

Symbol

Description

Reset Access
value

25

AAL

Address-aligned beats

0

R/W

0

R/W

When this bit is set high and the FB bit equals 1, the AHB interface generates all
bursts aligned to the start address LS bits. If the FB bit equals 0, the first burst
(accessing the data buffer’s start address) is not aligned, but subsequent bursts are
aligned to the address.
26

MB

Mixed burst
When this bit is set high and FB bit is low, the AHB master interface will start all bursts
of length more than 16 with INCR (undefined burst) whereas it will revert to fixed burst
transfers (INCRx and SINGLE) for burst-length of 16 and below.

27

TXPR

When set, this bit indicates that the transmit DMA has higher priority than the 0
receive DMA during arbitration for the system-side bus.

R/W

31:28

-

Reserved

RO

0

Table 630. Programmable burst length settings
Data bus width

FIFO depth

Valid PBL range in full duplex
mode

32 bit

128 bytes

8 or less

256 bytes

32 or less

512 bytes

64 or less

1 kB

128 or less

2 kB and above

all

28.6.28 DMA Transmit poll demand register
The Transmit Poll Demand register enables the Transmit DMA to check whether or not the
current descriptor is owned by DMA. The Transmit Poll Demand command is given to
wake up the TxDMA if it is in Suspend mode. The TxDMA can go into Suspend mode due
to an Underflow error in a transmitted frame or due to the unavailability of descriptors
owned by Transmit DMA. You can give this command anytime and the TxDMA will reset
this command once it starts re-fetching the current descriptor from host memory.
Table 631. DMA Transmit poll demand register (DMA_TRANS_POLL_DEMAND, address
0x4001 1004) bit description
Bit

Symbol

Description

Reset Access
value

31:0

TPD

0
Transmit poll demand
This register field can be read by the application, and when
a write operation is performed with any data value, an event
is triggered.

R/W

When these bits are written with any value, the DMA reads
the current descriptor pointed to by the Current Host
Transmit Descriptor register (Section 28.6.37). If that
descriptor is not available (owned by Host), transmission
returns to the Suspend state and bit 2 in the DMA_STAT
Register is asserted. If the descriptor is available,
transmission resumes.

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28.6.29 DMA Receive poll demand register
The Receive Poll Demand register enables the receive DMA to check for new descriptors.
This command is given to wake up the RxDMA from SUSPEND state. The RxDMA can go
into SUSPEND state only due to the unavailability of descriptors owned by it.
Table 632. DMA Receive poll demand register (DMA_REC_POLL_DEMAND, address 0x4001
1008) bit description
Bit

Symbol

Description

Reset Access
value

31:0

RPD

Receive poll demand
0
This register field can be read by the application, and when
a write operation is performed with any data value, an event
is triggered.

R/W

When these bits are written with any value, the DMA reads
the current descriptor pointed to by the Current Host
Receive Descriptor register (Section 28.6.38). If that
descriptor is not available (owned by Host), reception
returns to the Suspended state and bit 7 in the DMA_STAT
Register is not asserted. If the descriptor is available, the
Receive DMA returns to active state.

28.6.30 DMA Receive descriptor list address register
The Receive Descriptor List Address register points to the start of the Receive Descriptor
List. The descriptor lists reside in the host’s physical memory space and must be
Word-aligned . The DMA internally converts it to bus width aligned address by making the
corresponding LS bits low. Writing to this register is permitted only when reception is
stopped. When stopped, this register must be written to before the receive Start command
is given.
Table 633. DMA Receive descriptor list address register (DMA_REC_DES_ADDR, address
0x4001 100C) bit description
Bit

Symbol

31:0

SRL

Description

Reset Access
value

Start of receive list

0

R/W

This field contains the base address of the First Descriptor
in the Receive Descriptor list. The LSB bit 1 will be ignored
and taken as all-zero by the DMA internally. Hence these
LSB bits are Read Only.

28.6.31 DMA Transmit descriptor list address register
The Transmit Descriptor List Address register points to the start of the Transmit Descriptor
List. The descriptor lists reside in the host’s physical memory space and must be
Word-aligned . The DMA internally converts it to bus width aligned address by making the
corresponding LSB to low. Writing to this register is permitted only when transmission has
stopped. When stopped, this register can be written before the transmission Start
command is given.

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Table 634. DMA Transmit descriptor list address register (DMA_TRANS_DES_ADDR,
address 0x4001 1010) bit description
Bit

Symbol

Description

Reset Access
value

31:0

SRL

Start of transmit list

0

R/W

This field contains the base address of the First Descriptor
in the Transmit Descriptor list. The LSB bit 1 will be ignored
and taken as all-zero by the DMA internally. Hence these
LSB bits are Read Only.

28.6.32 DMA Status register
The Status register contains all the status bits that the DMA reports to the host. This
register is usually read by the Software driver during an interrupt service routine or polling.
Most of the fields in this register cause the host to be interrupted. The bits in this register
are not cleared when read. Writing 1 to (unreserved) bits in this register (bits [16:0]) clears
them and writing 0 has no effect. Each field (bits[16:0]) can be masked by masking the
appropriate bit in the DMA_INT_EN register.
This fields in this register can be read by the application (Read), can be set to 1 by the
Ethernet core on a certain internal event (Self Set), and can be cleared to 0 by the
application with a register write of 1 (Write Clear). A register write of 0 has no effect on the
field.
Table 635. DMA Status register (DMA_STAT, address 0x4001 1014) bit description
Bit

Symbol

0

TI

Description

Reset Access
value

Transmit interrupt

0

R/W

0

RW

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

This bit indicates that frame transmission is finished and TDES1[31] is set in the First
Descriptor.
1

TPS

Transmit process stopped
This bit is set when the transmission is stopped.

2

TU

Transmit buffer unavailable
This bit indicates that the Next Descriptor in the Transmit List is owned by the host
and cannot be acquired by the DMA. Transmission is suspended. Bits[22:20] explain
the Transmit Process state transitions. To resume processing transmit descriptors,
the host should change the ownership of the bit of the descriptor and then issue a
Transmit Poll Demand command.

3

TJT

Transmit jabber timeout
This bit indicates that the Transmit Jabber Timer expired, meaning that the transmitter
had been excessively active. The transmission process is aborted and placed in the
Stopped state. This causes the Transmit Jabber Timeout TDES0[14] flag to assert.

4

OVF

Receive overflow
This bit indicates that the Receive Buffer had an Overflow during frame reception. If
the partial frame is transferred to application, the overflow status is set in RDES0[11].

5

UNF

Transmit underflow
This bit indicates that the Transmit Buffer had an Underflow during frame
transmission. Transmission is suspended and an Underflow Error TDES0[1] is set.

6

RI

Receive interrupt
This bit indicates the completion of frame reception. Specific frame status information
has been posted in the descriptor. Reception remains in the Running state.

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Table 635. DMA Status register (DMA_STAT, address 0x4001 1014) bit description …continued
Bit

Symbol

Description

Reset Access
value

7

RU

Receive buffer unavailable

0

R/W

0

R/W

0

R/W

0

R/W

This bit indicates that the Next Descriptor in the Receive List is owned by the host and
cannot be acquired by the DMA. Receive Process is suspended. To resume
processing Receive descriptors, the host should change the ownership of the
descriptor and issue a Receive Poll Demand command. If no Receive Poll Demand is
issued, Receive Process resumes when the next recognized incoming frame is
received. This bit is set only when the previous Receive Descriptor was owned by the
DMA.
8

RPS

Received process stopped
This bit is asserted when the Receive Process enters the Stopped state.

9

RWT

Receive watchdog timeout
This bit is asserted when a frame with a length greater than 2,048 bytes is received
(10,240 when Jumbo Frame mode is enabled).

10

ETI

Early transmit interrupt
This bit indicates that the frame to be transmitted was fully transferred to the MTL
Transmit FIFO.

12:11

-

Reserved

0

RO

13

FBI

Fatal bus error interrupt

0

R/W

0

R/W

0

R/W

This bit indicates that a bus error occurred, as detailed in bits [25:23]. When this bit is
set, the corresponding DMA engine disables all its bus accesses.
14

ERI

Early receive interrupt
This bit indicates that the DMA had filled the first data buffer of the packet. Receive
Interrupt bit 6 in this register automatically clears this bit.

15

AIE

Abnormal interrupt summary
Abnormal Interrupt Summary bit value is the logical OR of the following when the
corresponding interrupt bits are enabled in the DMA_INT_EN register:
DMA_STAT register, bit 1: Transmit process stopped
DMA_STAT register, bit 3: Transmit jabber timeout
DMA_STAT register, bit 4: Receive overflow
DMA_STAT register, bit 5: Transmit underflow
DMA_STAT register, bit 7: Receiver buffer unavailable
DMA_STAT register, bit 8: Receive process stopped
DMA_STAT register, bit 9: Receive watchdog timeout
DMA_STAT register, bit 10: Early transmit interrupt
DMA_STAT register, bit 13: Fatal bus error
Only unmasked bits affect the Abnormal Interrupt Summary bit.
This is a sticky bit and must be cleared each time a corresponding bit that causes AIS
to be set is cleared.

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Table 635. DMA Status register (DMA_STAT, address 0x4001 1014) bit description …continued
Bit

Symbol

Description

Reset Access
value

16

NIS

Normal interrupt summary

0

R/W

0

RO

000

RO

0

RO

Normal Interrupt Summary bit value is the logical OR of the following when the
corresponding interrupt bits are enabled in the DMA_INT_EN register:
DMA_STAT register, bit 0: Transmit interrupt
DMA_STAT register, bit 2: Transmit buffer unavailable
DMA_STAT register, bit 6: Receive interrupt
DMA_STAT register, bit 14: Early receive interrupt
Only unmasked bits affect the Normal Interrupt Summary bit.
This is a sticky bit and must be cleared (by writing a 1 to this bit) each time a
corresponding bit that causes NIS to be set is cleared.
19:17

RS

Receive Process State
These bits indicate the receive DMA state machine state. This field does not generate
an interrupt.
000 = Stopped: Reset or Stop Receive Command issued.
001 = Running: Fetching Receive Transfer Descriptor.
010 = Reserved.
011 = Running: Waiting for receive packet.
100 = Suspended: Receive Descriptor Unavailable.
101 = Running: Closing Receive Descriptor.
110 = TIME_STAMP write state.
111 = Running: Transferring the receive packet data from receive buffer to host
memory.

22:20

TS

Transmit Process State
These bits indicate the transmit DMA state machine state. This field does not
generate an interrupt.
000 = Stopped; Reset or Stop Transmit Command issued.
001 = Running; Fetching Transmit Transfer Descriptor.
010 = Running; Waiting for status.
011 = Running; Reading Data from host memory buffer and queuing it to transmit
buffer (Tx FIFO).
100 = TIME_STAMP write state.
101 = Reserved.
110 = Suspended; Transmit Descriptor Unavailable or Transmit Buffer Underflow.
111 = Running; Closing Transmit Descriptor.

23

EB1

Error bit 1
This bit indicates the type of error that caused a Bus Error (e.g., error response on the
AHB interface). This bits is valid only when bit 13 in this register is set. This field does
not generate an interrupt.
1 = Error during data transfer by TxDMA.
0 = Error during data transfer by RxDMA.

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Table 635. DMA Status register (DMA_STAT, address 0x4001 1014) bit description …continued
Bit

Symbol

Description

Reset Access
value

24

EB2

Error bit 2

0

RO

0

RO

0

RO

This bit indicates the type of error that caused a Bus Error (e.g., error response on the
AHB interface). This bits is valid only when bit 13 in this register is set. This field does
not generate an interrupt.
1 = Error during read transfer.
0 = Error during write transfer.
25

EB3

Error bit 3
This bit indicates the type of error that caused a Bus Error (e.g., error response on the
AHB interface). This bits is valid only when bit 13 in this register is set. This field does
not generate an interrupt.
1 = Error during descriptor access.
0 = Error during data buffer access.

31:26

-

Reserved

28.6.33 DMA Operation mode register
The Operation Mode register establishes the Transmit and Receive operating modes and
commands. This register should be the last CSR to be written as part of DMA initialization.
Table 636. DMA operation mode register (DMA_OP_MODE, address 0x4001 1018) bit description
Bit

Symbol

Description

Reset Access
value

0

-

Reserved

0

RO

1

SR

Start/stop receive

0

R/W

0

R/W

0

R/W

0

RO

When this bit is set, the Receive process is placed in the Running state. The DMA
attempts to acquire the descriptor from the Receive list and processes incoming
frames. Descriptor acquisition is attempted from the current position in the list, which
is the address set by the DMA_REC_DES_ADDR register or the position retained
when the Receive process was previously stopped. If no descriptor is owned by the
DMA, reception is suspended and Receive Buffer Unavailable bit (bit 7 in DMA_STAT
register) is set. The Start Receive command is effective only when reception has
stopped. If the command was issued before setting the DMA_REC_DES_ADDR,
DMA behavior is unpredictable.
2

OSF

Operate on second frame
When this bit is set, this bit instructs the DMA to process a second frame of Transmit
data even before status for first frame is obtained.

4:3

RTC

Receive threshold control
These two bits control the threshold level of the MTL Receive FIFO. Transfer
(request) to DMA starts when the frame size within the MTL Receive FIFO is larger
than the threshold. In addition, full frames with a length less than the threshold are
transferred automatically. These bits are valid only when the RSF bit is zero, and are
ignored when the RSF bit is set to 1.
00 = 64
01 = 32
10 = 96
11 = 128

5

-

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Table 636. DMA operation mode register (DMA_OP_MODE, address 0x4001 1018) bit description …continued
Bit

Symbol

Description

Reset Access
value

6

FUF

Forward undersized good frames

0

R/W

0

R/W

When set, the Rx FIFO will forward Undersized frames (frames with no Error and
length less than 64 bytes) including pad-bytes and CRC).
When reset, the Rx FIFO will drop all frames of less than 64 bytes, unless it is already
transferred due to lower value of Receive Threshold (e.g., RTC = 01).
7

FEF

Forward error frames
When this bit is reset, the Rx FIFO drops frames with error status (CRC error, collision
error, , watchdog timeout, overflow). However, if the frame’s start byte (write) pointer
is already transferred to the read controller side (in Threshold mode), then the frames
are not dropped. When FEF is set, all frames except runt error frames are forwarded
to the DMA. But when RxFIFO overflows when a partial frame is written, then such
frames are dropped even when FEF is set.

12:8

-

Reserved

0

RO

13

ST

Start/Stop Transmission Command

0

R/W

0

R/W

0

RO

When this bit is set, transmission is placed in the Running state, and the DMA checks
the Transmit List at the current position for a frame to be transmitted. Descriptor
acquisition is attempted either from the current position in the list, which is the
Transmit List Base Address set by the DMA_TRANS_DES_ADDR register or from
the position retained when transmission was stopped previously. If the current
descriptor is not owned by the DMA, transmission enters the Suspended state and
Transmit Buffer Unavailable (DMA_STAT register, bit 2) is set. The Start Transmission
command is effective only when transmission is stopped. If the command is issued
before setting the DMA_TRANS_DES_ADDR register, then the DMA behavior is
unpredictable.
When this bit is reset, the transmission process is placed in the Stopped state after
completing the transmission of the current frame. The Next Descriptor position in the
Transmit List is saved, and becomes the current position when transmission is
restarted. The stop transmission command is effective only the transmission of the
current frame is complete or when the transmission is in the Suspended state.
16:14

TTC

Transmit threshold control
These three bits control the threshold level of the MTL Transmit FIFO. Transmission
starts when the frame size within the MTL Transmit FIFO is larger than the threshold.
In addition, full frames with a length less than the threshold are also transmitted.
These bits are used only when the TSF bit (Bit 21) is reset.
000 = 64
001 = 128
010 = 192
011 = 256
100 = 40
101 = 32
110 = 24
111 = 16

19:17

-

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Table 636. DMA operation mode register (DMA_OP_MODE, address 0x4001 1018) bit description …continued
Bit

Symbol

Description

Reset Access
value

20

FTF

Flush transmit FIFO
0
This register field can be read by the application (Read), can be set to 1 by the
application with a register write of 1 (Write Set), and is cleared to 0 by the Ethernet
core (Self Clear). The application cannot clear this type of field, and a register write of
0 to this bit has no effect on this field.

R/W

When this bit is set, the transmit FIFO controller logic is reset to its default values and
thus all data in the Tx FIFO is lost/flushed. This bit is cleared internally when the
flushing operation is completed fully. The Operation Mode register should not be
written to until this bit is cleared. The data which is already accepted by the MAC
transmitter will not be flushed. It will be scheduled for transmission and will result in
underflow and runt frame transmission.
Remark: The flush operation completes only after emptying the TxFIFO of its
contents and all the pending Transmit Status of the transmitted frames are accepted
by the host. In order to complete this flush operation, the PHY transmit clock is
required to be active.
21

-

Reserved

0

RO

23:22

-

Reserved

0

RO

24

DFF

Disable flushing of received frames

0

R/W

When this bit is set, the RxDMA does not flush any frames due to the unavailability of
receive descriptors/buffers as it does normally when this bit is reset. (See).
25

-

Reserved

0

RO

26

-

Reserved

0

RO

31:27

-

Reserved

0

RO

28.6.34 DMA Interrupt enable register
The Interrupt Enable register enables the interrupts reported by the DMA_STAT register.
Setting a bit to 1 enables a corresponding interrupt. After a hardware or software reset, all
interrupts are disabled.
Table 637. DMA Interrupt enable register (DMA_INT_EN, address 0x4001 101C) bit description
Bit

Symbol

0

TIE

Description

Reset Access
value

Transmit interrupt enable

0

R/W

0

R/W

0

R/W

When this bit is set with Normal Interrupt Summary Enable (bit 16 in this register),
Transmit Interrupt is enabled. When this bit is reset, Transmit Interrupt is disabled.
1

TSE

Transmit stopped enable
When this bit is set with Abnormal Interrupt Summary Enable (bit 15 in this register),
Transmission Stopped Interrupt is enabled. When this bit is reset, Transmission
Stopped Interrupt is disabled.

2

TUE

Transmit buffer unavailable enable
When this bit is set with Normal Interrupt Summary Enable (bit 16 in this register),
Transmit Buffer Unavailable Interrupt is enabled. When this bit is reset, Transmit
Buffer Unavailable Interrupt is disabled.

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Table 637. DMA Interrupt enable register (DMA_INT_EN, address 0x4001 101C) bit description …continued
Bit

Symbol

Description

Reset Access
value

3

TJE

Transmit jabber timeout enable

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

When this bit is set with Abnormal Interrupt Summary Enable (bit 15 in this register),
Transmit Jabber Timeout Interrupt is enabled. When this bit is reset, Transmit Jabber
Timeout Interrupt is disabled.
4

OVE

Overflow interrupt enable
When this bit is set with Abnormal Interrupt Summary Enable (bit 15 in this register),
Receive Overflow Interrupt is enabled. When this bit is reset, Overflow Interrupt is
disabled.

5

UNE

Underflow interrupt enable
When this bit is set with Abnormal Interrupt Summary Enable (bit 15 in this register),
Transmit Underflow Interrupt is enabled. When this bit is reset, Underflow Interrupt is
disabled.

6

RIE

Receive interrupt enable
When this bit is set with Normal Interrupt Summary Enable (bit 16 in this register),
Receive Interrupt is enabled. When this bit is reset, Receive Interrupt is disabled.

7

RUE

Receive buffer unavailable enable
When this bit is set with Abnormal Interrupt Summary Enable (bit 15 in this register),
Receive Buffer Unavailable Interrupt is enabled. When this bit is reset, the Receive
Buffer Unavailable Interrupt is disabled.

8

RSE

Received stopped enable
When this bit is set with Abnormal Interrupt Summary Enable (bit 15 in this register),
Receive Stopped Interrupt is enabled. When this bit is reset, Receive Stopped
Interrupt is disabled.

9

RWE

Receive watchdog timeout enable
When this bit is set with Abnormal Interrupt Summary Enable (bit 15 in this register),
the Receive Watchdog Timeout Interrupt is enabled. When this bit is reset, Receive
Watchdog Timeout Interrupt is disabled.

10

ETE

Early transmit interrupt enable
When this bit is set with an Abnormal Interrupt Summary Enable (bit 15 in this
register), Early Transmit Interrupt is enabled. When this bit is reset, Early Transmit
Interrupt is disabled.

12:11

-

Reserved

0

RO

13

FBE

Fatal bus error enable

0

R/W

0

R/W

When this bit is set with Abnormal Interrupt Summary Enable (bit 15 in this register),
the Fatal Bus Error Interrupt is enabled. When this bit is reset, Fatal Bus Error Enable
Interrupt is disabled.
14

ERE

Early receive interrupt enable
When this bit is set with Normal Interrupt Summary Enable (bit 16 in this register),
Early Receive Interrupt is enabled. When this bit is reset, Early Receive Interrupt is
disabled.

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Table 637. DMA Interrupt enable register (DMA_INT_EN, address 0x4001 101C) bit description …continued
Bit

Symbol

Description

Reset Access
value

15

AIE

Abnormal interrupt summary enable

0

R/W

0

R/W

0

RO

When this bit is set, an Abnormal Interrupt is enabled. When this bit is reset, an
Abnormal Interrupt is disabled. This bit enables the following bits
DMA_STAT register, bit 1: Transmit process stopped
DMA_STAT register, bit 3: Transmit jabber timeout
DMA_STAT register, bit 4: Receive overflow
DMA_STAT register, bit 5: Transmit underflow
DMA_STAT register, bit 7: Receiver buffer unavailable
DMA_STAT register, bit 8: Receive process stopped
DMA_STAT register, bit 9: Receive watchdog timeout
DMA_STAT register, bit 10: Early transmit interrupt
DMA_STAT register, bit 13: Fatal bus error
16

NIE

Normal interrupt summary enable
When this bit is set, a normal interrupt is enabled. When this bit is reset, a normal
interrupt is disabled. This bit enables the following bits:
DMA_STAT register, bit 0: Transmit interrupt
DMA_STAT register, bit 2: Transmit buffer unavailable
DMA_STAT register, bit 6: Receive interrupt
DMA_STAT register, bit 14: Early receive interrupt

31:17

-

Reserved

The interrupt (sbd_intr_o_interrupt) is generated as shown in Figure 79. It is asserted
when the NIS/AIS Status bit is asserted and the corresponding Interrupt Enable bits
(NIE/AIE) are enabled.

TI

AND
TIE
ERI

OR

NIS

AND

AN D

ERE
NIE

OR

sbd _intr_o

TPS

AND

OR

AIS

TSE

AN D

FBI

AIE

AND
FBE

Fig 79. Interrupt generation
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28.6.35 DMA Missed frame and buffer overflow counter register
The DMA maintains two counters to track the number of missed frames during reception.
This register reports the current value of the counter. The counter is used for diagnostic
purposes. Bits[15:0] indicate missed frames due to the host buffer being unavailable.
Bits[27:17] indicate missed frames due to buffer overflow conditions and runt frames
(good frames of less than 64 bytes) dropped by the MTL.
Table 638. DMA Missed frame and buffer overflow counter register (DMA_MFRM_BUFOF,
address 0x4001 1020) bit description
Bit

Symbol

Description

Reset Access
value

15:0

FMC

Number of frames missed
This register field can be read by the application (Read),
can be set to 1 by the Ethernet core on a certain internal
event (Self Set), and is automatically cleared to 0 on a
register read. A register write of 0 has no effect on this
field.

0

RO

Indicates the number of frames missed by the controller
due to the Host Receive Buffer being unavailable. This
counter is incremented each time the DMA discards an
incoming frame. The counter is cleared when this register
is read with.
16

OC

Overflow bit for missed frame counter
This register field can be read by the application (Read),
can be set to 1 by the Ethernet core on a certain internal
event (Self Set), and is automatically cleared to 0 on a
register read. A register write of 0 has no effect on this
field.

0

RO

27:17

FMA

Number of frames missed by the application
This register field can be read by the application (Read),
can be set to 1 by the Ethernet core on a certain internal
event (Self Set), and is automatically cleared to 0 on a
register read. A register write of 0 has no effect on this
field.

0

RO

Indicates the number of frames missed by the application.
This counter is incremented each time the MTL asserts
the sideband signal. The counter is cleared when this
register is read.
28

OF

Overflow bit for FIFO overflow counter
This register field can be read by the application (Read),
can be set to 1 by the Ethernet core on a certain internal
event (Self Set), and is automatically cleared to 0 on a
register read. A register write of 0 has no effect on this
field.

0

RO

31:29

-

Reserved

0

RO

28.6.36 DMA Receive interrupt watchdog timer register
This register, when written with non-zero value, will enable the watchdog timer for RI (bit 6
in the DMA_STAT register).

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Table 639. DMA Receive interrupt watchdog timer register (DMA_REC_INT_WDT, address
0x4001 1024) bit description
Bit

Symbol

Description

Reset Access
value

7:0

RIWT

RI watchdog timeout

0

R/W

0

RO

Indicates the number of system clock cycles multiplied by
256 for which the watchdog timer is set. The watchdog timer
gets triggered with the programmed value after the RxDMA
completes the transfer of a frame for which the RI status bit
is not set due to the setting in the corresponding descriptor
RDES1[31]. When the watch-dog timer runs out, the RI bit is
set and the timer is stopped. The watchdog timer is reset
when RI bit is set high due to automatic setting of RI as per
RDES1[31] of any received frame.
31:8

-

Reserved

28.6.37 DMA Current host transmit descriptor register
The Current Host Transmit Descriptor register points to the start address of the current
Transmit Descriptor read by the DMA.
Table 640. DMA Current host transmit descriptor register (DMA_CURHOST_TRANS_DES,
address 0x4001 1048) bit description
Bit

Symbol

31:0

HTD

Description

Reset Access
value

Host Transmit Descriptor Address Pointer

0

RO

Cleared on Reset. Pointer updated by DMA during
operation.

28.6.38 DMA Current host receive descriptor register
The Current Host Receive Descriptor register points to the start address of the current
Receive Descriptor read by the DMA.
Table 641. DMA Current host receive descriptor register (DMA_CURHOST_REC_DES,
address 0x4001 104C) bit description
Bit

Symbol

Description

Reset Access
value

31:0

HRD

Host Receive Descriptor Address Pointer

0

RO

Cleared on Reset. Pointer updated by DMA during
operation.

28.6.39 DMA Current host transmit buffer address register
The Current Host Transmit Buffer Address register points to the current Transmit Buffer
Address being read by the DMA.

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Table 642. DMA Current host transmit buffer address register
(DMA_CURHOST_TRANS_BUF, address 0x4001 1050) bit description
Bit

Symbol

Description

Reset Access
value

31:0

HTB

Host Transmit Buffer Address Pointer

0

RO

Cleared on Reset. Pointer updated by DMA during
operation.

28.6.40 DMA Current host receive buffer address register
The Current Host Receive Buffer Address register points to the current Receive Buffer
address being read by the DMA.
Table 643. DMA Current host receive buffer address register (DMA_CURHOST_REC_BUF,
address 0x4001 1054) bit description
Bit

Symbol

31:0

HRB

Description

Reset Access
value

Host Receive Buffer Address Pointer

0

RO

Cleared on Reset. Pointer updated by DMA during
operation.

28.7 Functional description
28.7.1 Hash filter
To use the hash filter, follow these steps:
1. Calculate CRC32 from the DA (Destination Address) MAC address.
2. Perform a bit-wise reversal of the last two bytes of the value obtained in step 1.
3. Use the first 6 bits of the value obtained in step 2 as follows:
– The most significant bit determines the hash table register to use.
– The other 5 bits determine the bit to set in the selected register.
4. In the MAC_FRAME_REGISTER, enable the HMC bit (bit 2) for multicast hash
filtering or the HUC bit (bit 1) for unicast hash filtering.

28.7.1.1 Example for a unicast MAC address
MAC: 5e-45-a2-6c-30-1e
CRC32: 0x94B3F747
Last 2 bytes in binary: 0100 0111
Bit-wise reversal: 1110 0010
First 6 bits: 111000

( 1=Hash Table High / 11000 => 0x18 => bit 24 )

In the MAC_HASH_TABLE_HIGH register write a 1 to bit 24.
In the MAC_FRAME_FILTER register, set the HUC bit (bit 1) to 1.

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28.7.1.2 Example for a multicast MAC address
MAC: 01-45-a2-6c-30-33
CRC32: 0x2CB41110
Last 2 bytes in binary:

0001 0000

Bit-wise reversal: 0000 1000
First 6 bits: 000010

( 0=Hash Table Low / 00010 => 0x2 => bit 2 )

In the MAC_HASH_TABLE_LOW register, write a 1 to bit 2.
In the MAC_FRAME_FILTER register, set the HMC bit (bit 2) to 1.

28.7.2 Power management block
This section describes the power management (PMT) mechanisms supported by the
MAC. PMT supports the reception of network (remote) wake-up frames and Magic Packet
frames. PMT does not perform the clock gate function, but generates interrupts for
wake-up frames and Magic Packets received by the MAC. The PMT block sits on the
receiver path of the MAC and is enabled with remote wake-up frame enable and Magic
Packet enable. These enables are in the PMT Control and Status register and are
programmed by the Application.
When the power-down mode is enabled in the PMT, then all received frames are dropped
by the ethernet core and they are not forwarded to the application. The ethernet comes
out of the power-down mode only when either a Magic Packet or a Remote Wake-up
frame is received and the corresponding detection is enabled.

28.7.2.1 Remote wake-up frame registers
The register WKUPFMFILTER_REG, address (0x028), loads the Wake-up Frame Filter
register. To load values in a Wake-up Frame Filter register, the entire register
(WKUPFMFILTER_REG) must be written. The WKUPFMFILTER_REG register is loaded
by sequentially loading the eight register values in address (0x028) for
WKUPFMFILTER_REG0, WKUPFMFILTER_REG1,... WKUPFMFILTER_REG7,
respectively. WKUPFMFILTER_REG is read in the same way.
Remark: The internal counter to access the appropriate WKUPFMFILTER_REG is
incremented when lane 3 (or lane 0 in big-endian) is accessed by the CPU. This should be
kept in mind if you are accessing these registers in byte or half-word mode.

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WKUPFMFILTER0

Filter 0 Byte Mask

WKUPFMFILTER1

Filter 1 Byte Mask

WKUPFMFILTER2

Filter 2 Byte Mask

WKUPFMFILTER3

Filter 3 Byte Mask

WKUPFMFILTER4

WKUPFMFILTER5

RSVD

Filter 3
Command

Filter 3 Offset

RSVD

Filter 2
Command

Filter 2 Offset

RSVD

Filter 1
Command

Filter 1 Offset

RSVD

Filter 0
Command

Filter 0 Offset

WKUPFMFILTER6

Filter 1 CRC - 16

Filter 0 CRC - 16

WKUPFMFILTER7

Filter 3 CRC - 16

Filter 2 CRC - 16

Fig 80. Wake-up frame filter register

Filter i byte mask
This register defines which bytes of the frame are examined by filter i (0, 1, 2, and 3) in
order to determine whether or not the frame is a wake-up frame. The MSB (thirty-first bit)
must be zero. Bit j [30:0] is the Byte Mask. If bit j (byte number) of the Byte Mask is set,
then Filter i Offset + j of the incoming frame is processed by the CRC block; otherwise
Filter i Offset + j is ignored.
Filter i command
This 4-bit command controls the filter i operation. Bit 3 specifies the address type, defining
the pattern’s destination address type. When the bit is set, the pattern applies to only
multicast frames; when the bit is reset, the pattern applies only to unicast frame. Bit 2 and
Bit 1 are reserved. Bit 0 is the enable for filter i; if Bit 0 is not set, filter i is disabled.
Filter i offset
This register defines the offset (within the frame) from which filter i examines the frames.
This 8-bit pattern offset is the offset for the filter i first byte to be examined. The minimum
allowed is 12, which refers to the 13th byte of the frame. The offset value 0 refers to the
first byte of the frame.
Filter i CRC-16
This register contains the CRC_16 value calculated from the pattern, as well as the byte
mask programmed to the wake-up filter register block.

28.7.2.2 Remote wake-up detection
When the MAC is in sleep mode and the remote wake-up bit is enabled in PMT Control
and Status register (0x002C), normal operation is resumed after receiving a remote
wake-up frame. The Application writes all eight wake-up filter registers by performing a
sequential Write to address (0x0028). The Application enables remote wake-up by writing
a 1 to Bit 2 of the PMT Control and Status register.
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PMT supports four programmable filters that allow support of different receive frame
patterns. If the incoming frame passes the address filtering of Filter Command, and if
Filter CRC-16 matches the incoming examined pattern, then the wake-up frame is
received.
Filter_offset (minimum value 12, which refers to the 13th byte of the frame) determines the
offset from which the frame is to be examined. Filter Byte Mask determines which bytes of
the frame must be examined. The thirty-first bit of Byte Mask must be set to zero.
The remote wake-up CRC block determines the CRC value that is compared with Filter
CRC-16. The wake-up frame is checked only for length error, FCS error, dribble bit error,
MII error, collision, and to ensure that it is not a runt frame. Even if the wake-up frame is
more than 512 bytes long, if the frame has a valid CRC value, it is considered valid.
Wake-up frame detection is updated in the PMT Control and Status register for every
remote Wake-up frame received. A PMT interrupt to the Application triggers a Read to the
PMT Control and Status register to determine reception of a wake-up frame.

28.7.2.3 Magic packet detection
The Magic Packet frame is based on a method that uses Advanced Micro Device’s Magic
Packet technology to power up the sleeping device on the network. The MAC receives a
specific packet of information, called a Magic Packet, addressed to the node on the
network.
Only Magic Packets that are addressed to the device or a broadcast address will be
checked to determine whether they meet the wake-up requirements. Magic Packets that
pass the address filtering (unicast or broadcast) will be checked to determine whether
they meet the remote Wake-on-LAN data format of 6 bytes of all ones followed by a MAC
Address appearing 16 times.
The application enables Magic Packet wake-up by writing a 1 to Bit 1 of the PMT Control
and Status register. The PMT block constantly monitors each frame addressed to the
node for a specific Magic Packet pattern. Each frame received is checked for a 0xFFFF
FFFF FFFF pattern following the destination and source address field. The PMT block
then checks the frame for 16 repetitions of the MAC address without any breaks or
interruptions. In case of a break in the 16 repetitions of the address, the 0xFFFF FFFF
FFFF pattern is scanned for again in the incoming frame. The 16 repetitions can be
anywhere in the frame, but must be preceded by the synchronization stream (0xFFFF
FFFF FFFF). The device will also accept a multicast frame, as long as the 16 duplications
of the MAC address are detected.
If the MAC address of a node is 0x0011 2233 4455, then the MAC scans for the data
sequence:
00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55
00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55
00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55
00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55
...CRC
Magic Packet detection is updated in the PMT Control and Status register for Magic
Packet received. A PMT interrupt to the Application triggers a read to the PMT CSR to
determine whether a Magic Packet frame has been received.
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28.7.2.4 System considerations during power-down
MAC neither gates nor stops clocks when Power-down mode is enabled. Power saving by
clock gating must be done outside the core by the application. The receive data path must
be clocked with ENET_RX_CLK during Power-down mode because it is involved in magic
packet/wake-on-LAN frame detection. However, the transmit path and the application path
clocks can be gated off during Power-down mode.
The PMT interrupt is asserted when a valid wake-up frame is received. This signal is
generated in the receive clock domain
The recommended power-down and wake-up sequence is as follows.
1. Disable the Transmit DMA and wait for any previous frame transmissions to complete.
These transmissions can be detected when Transmit Interrupt (see DMA_STAT
register bit NIS; Table 635) is received.
2. Disable the MAC transmitter and MAC receiver by clearing the appropriate bits in the
MAC Configuration register.
3. Wait until the Receive DMA empties all the frames from the Rx FIFO (a software timer
may be required).
4. Enable Power-Down mode by appropriately configuring the PMT registers.
5. Enable the MAC Receiver and enter Power-Down mode.
6. Gate the application and transmit clock inputs to the core (and other relevant clocks in
the system) to reduce power and enter Sleep mode.
7. On receiving a valid wake-up frame, the MAC PMT interrupt signal and exits
Power-Down mode.
8. On receiving the interrupt, the system must enable the application and transmit clock
inputs to the core.
9. Read the PMT Status register to clear the interrupt, then enable the other modules in
the system and resume normal operation.
Remark:

28.7.3 DMA arbiter functions
If you have enabled the transmit (Tx) DMA and receive (Rx) DMA of a channel, you can
specify which DMA gets the bus when the channel gets the control of the bus. You can set
the priority between the corresponding Tx DMA and Rx DMA by using the bit 27 (TXPR:
Transmit Priority) of the DMA Bus Mode Register). For round-robin arbitration, you can
use the bits [15:14] (PR: Priority Ratio) of the Bus Mode Register to specify the weighted
priority between the Tx DMA and Rx DMA. Table 644 provides information about the
priority scheme between Tx DMA and Rx DMA.
Table 644. Priority scheme for transmit and receive DMA

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Bit 27

Bit 15

0

x

0

0

0

0

0

1

Bit 14

Bit 1

Priority scheme

x

x

Rx always has priority over Tx

0

0

Tx and Rx have equal priority. Rx gets the access first on
simultaneous requests.

1

0

Rx has priority over Tx in the ratio 2:1.

0

0

Rx has priority over Tx in the ratio 3:1.

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Table 644. Priority scheme for transmit and receive DMA
Bit 27

Bit 15

Bit 14

Bit 1

Priority scheme

0

1

1

0

Rx has priority over Tx in the ratio 4:1.

1

x

x

1

Tx always has priority over Rx.

1

0

0

0

Tx and Rx have equal priority. Tx gets the access first on
simultaneous requests.

1

0

1

0

Tx has priority over Rx in the ratio 2:1.

1

1

0

0

Tx has priority over Rx in the ratio 3:1.

1

1

1

0

Tx has priority over Rx in the ratio 4:1.

28.7.4 IEEE 1588-2002 timestamps
The IEEE 1588-2002 standard defines a protocol, Precision Time Protocol (PTP), that
enables precise synchronization of clocks in measurement and control systems
implemented with technologies such as network communication, local computing, and
distributed objects. The PTP applies to systems communicating by local area networks
supporting multicast messaging, including (but not limited to) Ethernet. This protocol
enables heterogeneous systems that include clocks of varying inherent precision,
resolution, and stability to synchronize. The protocol supports system-wide
synchronization accuracy in the sub-microsecond range with minimal network and local
clock computing resources.
The PTP is transported over UDP/IP. The system or network is classified into Master and
Slave nodes for distributing the timing/clock information. Figure 81 shows the process that
PTP uses for synchronizing a slave node to a master node by exchanging PTP
messages.

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Fig 81. Networked time synchronization

As shown in Figure 81, the PTP uses the following process:
1. The master broadcasts the PTP Sync messages to all its nodes. The Sync message
contains the master.s reference time information. The time at which this message
leaves the master.s system is t1. This time must be captured, for Ethernet ports, at
MII.
2. The slave receives the Sync message and also captures the exact time, t2, using its
timing reference.
3. The master sends a Follow_up message to the slave, which contains t1 information
for later use.
4. The slave sends a Delay_Req message to the master, noting the exact time, t3, at
which this frame leaves the MII.
5. The master receives the message, capturing the exact time, t4, at which it enters its
system.
6. The master sends the t4 information to the slave in the Delay_Resp message.
7. The slave uses the four values of t1, t2, t3, and t4 to synchronize its local timing
reference to the master’s timing reference.

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Most of the PTP implementation is done in the software above the UDP layer. However,
the hardware support is required to capture the exact time when specific PTP packets
enter or leave the Ethernet port at the MII. This timing information must be captured and
returned to the software for the proper implementation of PTP with high accuracy.

28.7.4.1 Reference timing source
To get a snapshot of the time, the MAC requires a reference time in 64-bit format as
defined in the IEEE 1588 specification. The Ethernet MAC uses internal timing to provide
a reference timing source by using the reference clock input to generate the Reference
time (also called the System Time) internally and capture timestamps. The generation,
update, and modification of the System Time are described in Section 28.7.4.2.

28.7.4.2 System time register module
The 64-bit time is maintained in this module and updated using the input reference clock.
This time is the source for taking snapshots (timestamps) of Ethernet frames being
transmitted or received at the MII.
The System Time counter can be initialized or corrected using the coarse correction
method. In this method, the initial value or the offset value is written to the Timestamp
Update register (Table 617). For initialization, the System Time counter is written with the
value in the
Timestamp Update registers, while for system time correction, the offset value is added to
or subtracted from the system time.In the fine correction method, a slave clock’s
frequency drift with respect to the master clock (as defined in IEEE 1588) is corrected
over a period of time instead of in one clock, as in coarse correction. This helps maintain
linear time and does not introduce drastic changes (or a large jitter) in the reference time
between PTP Sync message intervals. In this method, an accumulator sums up the
contents of the Addend register, as shown in Figure 4-2. The arithmetic carry that the
accumulator generates is used as a pulse to increment the system time counter. The
accumulator and the addend are 32-bit registers. Here, the accumulator acts as a
high-precision frequency multiplier or divider.
This algorithm is shown in Figure 82:

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addend_val[31:0]
addend_updt

Addend register

+

Accumulator register

Constant value
incr_sub_sec_reg

+

Sub-second register
incr_sec_reg

Second register

Fig 82. System update using fine method

The System Time Update logic requires a 50-MHz clock frequency to achieve 20-ns
accuracy. The frequency division is the ratio of the reference clock frequency to the
required clock frequency. Hence, if the reference clock is, for example, 66 MHz, this ratio
is calculated as 66 MHz / 50 MHz = 1.32. Hence, the default addend value to be set in the
register is 232 / 1.32, 0xC1F07C1F.
If the reference clock drifts lower, to 65 MHz for example, the ratio is 65 / 50, or 1.3 and
the value to set in the addend register is 232 / 1.30, or 0xC4EC4EC4. If the clock drifts
higher, to 67 MHz for example, the addend register must be set to 0xBF0B7672. When
the clock drift is nil, the default addend value of 0xC1F07C1F (232 / 1.32) must be
programmed.
In Figure 82, the constant value used to accumulate the sub-second register is decimal
43, which achieves an accuracy of 20 ns in the system time (in other words, it is
incremented in 20-ns steps).
The software must calculate the drift in frequency based on the Sync messages and
update the Addend register accordingly.
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Initially, the slave clock is set with FreqCompensationValue0 in the Addend register. This
value is as follows:
FreqCompensationValue0 = 232 / FreqDivisionRatio
If MasterToSlaveDelay is initially assumed to be the same for consecutive Sync
messages, the algorithm described below must be applied. After a few Sync cycles,
frequency lock occurs. The slave clock can then determine a precise MasterToSlaveDelay
value and re-synchronize with the master using the new value.
The algorithm is as follows:

• At time MasterSyncTimen the master sends the slave clock a Sync message. The
slave receives this message when its local clock is SlaveClockTimen and computes
MasterClockTimen as:
MasterClockTimen = MasterSyncTimen + MasterToSlaveDelayn

• The master clock count for current Sync cycle, MasterClockCountn is given by:
MasterClockCountn = MasterClockTimen . MasterClockTimen-1 (assuming that
MasterToSlaveDelay is the same for Sync cycles n and n - 1)

• The slave clock count for current Sync cycle, SlaveClockCountn is given by:
SlaveClockCountn = SlaveClockTimenn - SlaveClockTimen-1

• The difference between master and slave clock counts for current Sync cycle,
ClockDiffCountn is given by:
ClockDiffCountn = MasterClockCountn - SlaveClockCountn

• The frequency-scaling factor for slave clock, FreqScaleFactorn is given by:
FreqScaleFactorn = (MasterClockCountn + ClockDiffCountn) / SlaveClockCountn

• The frequency compensation value for Addend register, FreqCompensationValuen is
given by:
FreqCompensationValuen = FreqScaleFactorn * FreqCompensationValuen-1
In theory, this algorithm achieves lock in one Sync cycle; however, it may take several
cycles, because of changing network propagation delays and operating conditions.
This algorithm is self-correcting: if for any reason the slave clock is initially set to a value
from the master that is incorrect, the algorithm corrects it at the cost of more Sync cycles.

28.7.4.3 Transmit path functions
The MAC captures a timestamp when the Start Frame Delimiter (SFD) of a frame is sent
on MII. The frames for which you want to capture timestamps are controllable on a
per-frame basis. In other words, each transmit frame can be marked to indicate whether a
timestamp should be captured for that frame.
The MAC does not process the transmitted frames to identify the PTP frames. You need
to specify the frames for which you want to capture timestamps.
Use the control bits in the transmit descriptor (see Section 28.7.6.3.1). The MAC returns
the timestamp to the software inside the corresponding transmit descriptor, thus
connecting the timestamp automatically to the specific PTP frame. The 64-bit timestamp
information is written to the TDES6 and TDES7 fields. The TDES7 field holds the 32 least
significant bits of the timestamp.
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28.7.4.4 Receive path functions
The MAC captures the timestamp of all frames received on the MII. The MAC does not
process the received frames to identify the PTP frames in the default mode, that is, when
the Advanced Timestamp feature is not selected.
The MAC gives the timestamp and the corresponding status on the MAC Receive
Interface (MRI) along with the EOF data. The MAC transaction layer (MTL) provides the
timestamp on the data bus after the EOF data has been transferred. The MTL sends a
separate signal to validate the timestamp and to indicate the availability of the timestamp.
Once the timestamp is transferred, the Status Valid signal is asserted as soon as status
data is present on the data bus.
The DMA returns the timestamp to the software in the corresponding receive descriptor.
The 64-bit timestamp information is written back to the RDES6 and RDES7 fields. The
RDES2 holds the 32 least significant bits of the timestamp, except as mentioned in
Section 28.7.6.3.2. The timestamp is written only to that receive descriptor for which the
Last Descriptor status field has been set to 1 (the EOF marker). When the timestamp is
not available (for example, because of an RxFIFO overflow), an all-ones pattern is written
to the descriptors (RDES6 and RDES7), indicating that timestamp is not correct. If the
software uses a control register bit to disable Time stamping, the DMA does not alter
RDES6 or RDES7.

28.7.4.5 Timestamp error margin
According to the IEEE 1588 specifications, a timestamp must be captured at the SFD of
the transmitted and received frames at the MII interface. Because the reference timing
source (the PTP clock) is different from the MII clocks, a small error margin is introduced,
because of the transfer of information across asynchronous clock domains.
In the transmit path, the captured and reported timestamp has a maximum error margin of
2 PTP clocks. It means that the captured timestamp has the reference timing source value
that is given within 2 clocks after the SFD has been transmitted on the MII.
Similarly, in the receive path, the error margin is 3 MII clocks, plus up to 2 PTP clocks. You
can ignore the error margin because of the II clocks by assuming that this constant delay
is present in the system (or link) before the SFD data reaches the GMAC.s MII interface.

28.7.4.6 Frequency range of the reference timing clock
The timestamp information is transferred across asynchronous clock domains, that is,
from MAC clock domain to application clock domain. Therefore, a minimum delay is
required between two consecutive timestamp captures. This delay is 4 clock cycles of II
and 3 clock cycles of PTP clocks. If the delay between two timestamp captures is less
than this delay, the MAC does not take a timestamp snapshot for the second frame.
The maximum PTP clock frequency is limited by the maximum resolution of the reference
time (1 ns resulting in 1 GHz) and the timing constraints achievable for logic operating on
the PTP clock. In addition, the resolution, or granularity, of the reference time source
determines the accuracy of the synchronization. Therefore, a higher PTP clock frequency
gives better system performance.

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The minimum PTP clock frequency depends on the time required between two
consecutive SFD bytes. Because the MII clock frequency is fixed by IEEE specification,
the minimum PTP clock frequency required for proper operation depends upon the
operating mode and operating speed of the MAC as shown in Table 4-1.
Table 645. Minimum PTP clock frequency cycle
Mode

Minimum gap between two
SFDs

Minimum PTP frequency

100-Mbps
full-duplex
operation

168 MII clocks (128 clocks for a (3 * PTP) + (4 * MII) ≤ 168 * MII that is,
64-byte frame + 24 clocks of
~0.5 MHz ((168 – 4) * 40 ns ÷ 3 = 2,180 ns
min IFG + 16 clocks of
period)
preamble)

28.7.5 IEEE 1588-2008 advanced time stamps
In addition to the basic timestamp features (see Section 28.7.4) the ethernet controller
supports the following advanced timestamp features defined in the IEEE 1588-2008
standard:

•
•
•
•

Supports the IEEE 1588-2008 (version 2) time stamp format.
Provides an option to take snapshot of all frames or only PTP type frames.
Provides an option to take snapshot of only event messages.
Provides an option to take the snapshot based on the clock type: ordinary, boundary,
end-to-end, and peer-to-peer.

• Provides an option to select the node to be a Master or Slave for ordinary and
boundary clock.

• Identifies the PTP message type, version, and PTP payload in frames sent directly
over Ethernet and sends the status.

• Provides an option to measure sub-second time in digital or binary format.
28.7.5.1 Peer-to-Peer PTP Transparent Clock (P2P TC) Message Support
The IEEE 1588-2008 version supports Peer-to-Peer PTP (Pdelay) message in addition to
SYNC, Delay Request, Follow-up, and Delay Response messages. Figure 83 shows the
method to calculate the propagation delay in clocks supporting peer-to-peer path
correction.

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P2P TC A
Delay
Requester
Time

P2P TC B
Delay
Responder
Time
Timestamps
known by Delay
Requester

t1

t1
Pdelay_Req

tAB

t2

t3
tBA
t4

Pdelay_Resp
Pdelay_Resp_Follow_Up:
t2, t3

t1 ,t 4
t1, t2 , t3, t4

Fig 83. Propagation Delay Calculation in Clocks Supporting Peer-to-Peer Path Correction

As shown in Figure 83, the propagation delay is calculated in the following way:
1. Port-1 issues a Pdelay_Req message and generates a timestamp, t1, for the
Pdelay_Req message .
2. Port-2 receives the Pdelay_Req message and generates a timestamp, t2, for this
message.
3. Port-2 returns a Pdelay_Resp message and generates a timestamp, t3, for this
message.
To minimize errors because of any frequency offset between the two ports, Port-2
returns the Pdelay_Resp message as quickly as possible after the receipt of the
Pdelay_Req message. The Port-2 returns any one of the following:
– The difference between the timestamps t2 and t3 in the Pdelay_Resp message.
– The difference between the timestamps t2 and t3 in the Pdelay_Resp_Follow_Up
message.
– The timestamps t2 and t3 in the Pdelay_Resp and Pdelay_Resp_Follow_Up
messages respectively.
4. Port-1 generates a timestamp, t4, on receiving the Pdelay_Resp message.
5. Port-1 uses all four timestamps to compute the mean link delay.

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28.7.5.2 Clock types
The Ethernet controller supports the following clock types defined in the IEEE 1588-2008
standard:

•
•
•
•
28.7.5.2.1

Ordinary clock
Boundary clock
End-to-end transparent clock
Peer-to-peer transparent clock

Ordinary clock
The ordinary clock in a domain supports a single copy of the protocol. The ordinary clock
has a single PTP state and a single physical port. In typical industrial automation
applications, an ordinary clock is associated with an application device such as a sensor
or an actuator. In telecommunications applications, the ordinary clock can be associated
with a timing demarcation device.
The ordinary clock can be a grandmaster or a slave clock. The ordinary clock supports the
following features:

• Send and receives PTP messages. The timestamp snapshot can be controlled as
described in Table 617.

• Maintains the data sets such as timestamp values.
Table 646. Ordinary clock: PTP messages for snapshot
Master

Slave

Delay_Req

SYNC

For an ordinary clock, you can take the snapshot of either one of the following PTP
message types: version 1 or version 2. You cannot take the snapshots for both PTP
message types. You can take the snapshot by setting the control bit (TSVER2ENA) and
selecting the snapshot mode in Table 617.
28.7.5.2.2

Boundary clock
The boundary clock typically has several physical ports communicating with the network.
The messages related to synchronization, master-slave hierarchy, and signaling terminate
in the protocol engine of the boundary clock and are not forwarded. The PTP message
type status given by the core (see.Section 28.7.4.4) helps you to identify the type of
message and take appropriate action.
The boundary clock is similar to the ordinary clock except for the following features:

• The clock data sets are common to all ports of the boundary clock .
• The local clock is common to all ports of the boundary clock.
Therefore, the features of the ordinary clock are also applicable to the boundary clock.
28.7.5.2.3

End-to-end transparent clock
The end-to-end transparent clock supports the end-to-end delay measurement
mechanism between slave clocks and the master clock. The end-to-end transparent clock
forwards all messages like normal bridge, router, or repeater. The residence time of a PTP
packet is the time taken by the PTP packet from the Ingress port to the Egress port.

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The residence time of a SYNC packet inside the end-to-end transparent clock is updated
in the correction field of the associated Follow_Up PTP packet before it is transmitted.
Similarly, the residence time of a Delay_Req packet inside the end-to-end transparent
clock is updated in the correction field of the associated Delay_Resp PTP packet before it
is transmitted. Therefore, the snapshot needs to be taken at both Ingress and Egress
ports only for the messages mentioned in Table 647.
You can take the snapshot by setting the snapshot select bits (SNAPTYPSEL) to 10 in
Table 617.
Table 647. End-to-end transparent clock: PTP messages for which a snapshot is taken for
transparent clock implementation
SYNC
FOLLOW_UP

28.7.5.2.4

Peer-to-peer transparent clock support
In this type of clock the computation of the link delay is based on an exchange of
Pdelay_Req, Pdelay_Resp and Pdelay_Resp_Follow_Up messages with the link peer.
Hence support for taking snapshot for the event messages related to Pdelay is added.
Table 648. End-to-end transparent clock: PTP messages for which a snapshot is taken for
transparent clock implementation
SYNC
Pdelay_Req
Pdelay_Resp

The transparent clock corrects only the SYNC and Follow-up message. As discussed
earlier this can be achieved using the message status provided.
The type of clock to be implemented will be configurable through control register (see
Table 617). To ensure that the snapshot is taken only for the messages indicated in the
table for the corresponding clock type, the.TSEVNTENA: Enable Time stamp Snapshot for
Event Messages. bit has to be set.

28.7.5.3 PTP processing and control
Table 4-5 shows the common message header for the PTP messages. This format is
taken from IEEE standard 1588-2008 (Revision of IEEE Std. 1588-2002).
Table 649. Message format defined in IEEE 1588-2008
Bits
7

6

5

4

3

transportSpecific

User manual

1
messageType

Reserved

UM10503

2

versionPTP

0

OCTETS

OFFSET

1

0

1

1

messageLength

2

2

domainNumber

1

4

Reserved

1

5

flagField

2

6

correctionField

8

8

Reserved

4

16

sourcePortIdentity

10

20

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Table 649. Message format defined in IEEE 1588-2008
Bits
7

6

5

4

3

2

1

0

sequenceId
controlField

([1])

logMessageInterva
[1]

OCTETS

OFFSET

2

30

1

32

1

33

Field is used in version 1. In version 2, messageType field is used for detecting different message types.

There are some fields in the Ethernet payload that you can use to detect the PTP packet
type and control the snapshot to be taken. These fields are different for the following PTP
frames:

• PTP Frames Over IPv4
• PTP Frames Over IPv6
• PTP Frames Over Ethernet
28.7.5.3.1

PTP frames over IPv4
Table 4-6 provides information about the fields that are matched to control snapshot for
the PTP packets sent over UDP over IPv4 for IEEE 1588 version 1 and 2. The octet
positions for the tagged frames are offset by 4. This is based on Annex D of IEEE
1588-2008 standard and the message format defined in Table 647.
Table 650. IPv4-UDP PTP Frame Fields Required for Control and Status
Field Matched

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Matched Value

Description

MAC Frame Type 12, 13

Octet Position

0x0800

IPv4 datagram

IP version and
Header Length

14

0x45

IP version is IPv4

Layer 4 Protocol

23

0x11

UDP

IP Multicast
Address (IEEE
1588 version 1)

30, 31, 32, 33

0xE0, 0x00, 0x01, Multicast IPv4 addresses allowed.
0x81 (or 0x82 or
224.0.1.129 224.0.1.130 224.0.1.131
0x83 or 0x84)
224.0.1.132

IP Multicast
Address (IEEE
1588 version 2)

30, 31, 32, 33

0xE0, 0x00, 0x01,
0x81 (Hex) 0xE0,
0x00, 0x00, 0x6B
(Hex)

PTP-Primary multicast address:
224.0.1.129
PTP-Pdelay multicast address:
224.0.0.107

UDP Destination
Port

36, 37

0x013F, 0x0140

0x013F – PTP event message ([1])
0x0140 – PTP general messages

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Table 650. IPv4-UDP PTP Frame Fields Required for Control and Status
Field Matched

Matched Value

Description

PTP Control Field 74
(IEEE version 1)

0x00/0x01/0x02/
0x03/0x04

0x00 – SYNC,
0x01 – Delay_Req
0x02 – Follow_Up
0x03 – Delay_Resp
0x04 – Management

PTP Message
Type Field (IEEE
version 2)

42 (nibble)

0x0/0x1/0x2/0x3/
0x8/0x9/0xB
/0xC/0xD

0x0 – SYNC
0x1 – Delay_Req
0x2 – Pdelay_Req
0x3 – Pdelay_Resp
0x8 – Follow_Up
0x9 – Delay_Resp
0xA – Pdelay_Resp_Follow_Up
0xB – Announce
0xC – Signaling
0xD - Management

PTP Version

43 (nibble)

0x1 or 0x2

0x1 – Supports PTP version 1
0x2 – Supports PTP version 2

[1]

28.7.5.3.2

Octet Position

PTP event messages are SYNC, Delay_Req (IEEE 1588 version 1 and 2) or Pdelay_Req, Pdelay_Resp
(IEEE 1588 version 2 only).

PTP Frames Over IPv6
Table 651 provides information about the fields that are matched to control the snapshots
for the PTP packets sent over UDP over IPv6 for IEEE 1588 version 1 and 2. The octet
positions for the tagged frames are offset by 4. This is based on Annex D of IEEE
1588-2008 standard and the message format defined in Table 647.
Table 651. IPv6-UDP PTP Frame Fields Required for Control and Status
Field Matched

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Matched Value

Description

MAC Frame Type 12, 13

Octet Position

0x86DD

IP datagram

IP version

0x6

IP version is IPv6

0x11

UDP

14(bits [7:4])
([1])

Layer 4 Protocol

20

PTP Multicast
Address

38 – 53

FF0x:0:0:0:0:0:0:
181 (Hex)
FF02:0:0:0:0:0:0:
6B (Hex)

PTP – Primary multicast address:
FF0x:0:0:0:0:0:0:0:0:181 (Hex)
PTP – Pdelay multicast address:
FF02:0:0:0:0:0:0:0:0:6B (Hex)

UDP Destination
Port

56, 57 ([1])

0x013F, 0x140

0x013F – PTP event message
0x0140 – PTP general messages

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Table 651. IPv6-UDP PTP Frame Fields Required for Control and Status
Field Matched

Octet Position

PTP Control Field 93
(IEEE version 1)

Matched Value

Description

0x00/0x01/0x02/
0x03/0x04

0x00 – SYNC
0x01 – Delay_Req
0x02 – Follow_Up
0x03 – Delay_Resp
0x04 – Management (version1)

PTP Message
Type Field (IEEE
version 2)

74 ([1]) (nibble)

0x0/0x1/0x2/0x3/
0x8/0x9/0xB
/0xC/0xD

0x0 – SYNC
0x1 – Delay_Req
0x2 – Pdelay_Req
0x3 – Pdelay_Resp
0x8 – Follow_Up
0x9 – Delay_Resp
0xA – Pdelay_Resp_Follow_Up
0xB – Announce
0xC – Signaling
0xD - Management

PTP Version

75 (nibble)

0x1 or 0x2

0x1 – Supports PTP version 1
0x2 – Supports PTP version 2

[1]

28.7.5.3.3

([1])

The Extension Header is not defined for PTP packets.

PTP frames over ethernet
Table 4-8 provides information about the fields that are matched to control the snapshots
for the PTP packets sent over Ethernet for IEEE 1588 version 1 and 2. The octet positions
for the tagged frames are offset by 4. This is based on Annex D of the IEEE 1588-2008
standard and the message format defined in Table 649.
Table 652. Ethernet PTP Frame Fields Required for Control And Status

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Field Matched

Octet Position

Matched Value

Description

MAC Destination
Multicast
Address[1]

0-5

01-1B-19-00-00-00
01-80-C2-00-00-0E

All PTP messages can use any of the
following multicast addresses[2]:
01-1B-19-00-00-00
01-80-C2-00-00-0E[3]

MAC Frame Type 12, 13

0x88F7

PTP Ethernet frame

PTP Control Field 45
(IEEE version 1)

0x00/0x01/0x02/
0x03/0x04

0x00 – SYNC
0x01 – Delay_Req
0x02 – Follow_Up
0x03 – Delay_Resp
0x04 – Management

PTP Message
Type Field (IEEE
version 2)

14 (nibble)

0x0/0x1/0x2/0x3/
0x8/0x9/0xB
/0xC/0xD

0x0 – SYNC
0x1 – Delay_Req
0x2 – Pdelay_Req
0x3 – Pdelay_Resp
0x8 – Follow_Up
0x9 – Delay_Resp
0xA – Pdelay_Resp_Follow_Up
0xB – Announce
0xC – Signaling
0xD - Management

PTP Version

14 (nibble)

0x1 or 0x2

0x1 – Supports PTP version 1
0x2 – Supports PTP version 2

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[1]

The address match of destination addresses (DA) programmed in MAC address 1 to 31 is used if the
control bit 18 (TSENMACADDR: Enable MAC address for PTP frame filtering) of the Timestamp Control
register is set.

[2]

IEEE standard 1588-2008, Annex F

[3]

The Ethernet controller does not consider the PTP version 1 messages with Peer delay multicast address
(01-80-C2-00-00- 0E) as valid PTP messages.

28.7.5.4 Reference timing source
The ethernet controller supports the 48-bit seconds field reference timing sources
featured in the IEEE 1588-2008 standard.
28.7.5.4.1

48-bit seconds field
The ethernet controller supports 80-bit timestamping. The timestamp has the following
fields:

• UInteger48 secondsField
The seconds field is the integer portion of the timestamp in units of seconds and is
48-bits wide. For example, 2.000000001 seconds are represented as secondsField =
0x0000_0000_0002.

• UInteger32 nanosecondsField
The nanoseconds field is the fractional portion of the timestamp in units of
nanoseconds. For example, 2.000000001 nanoseconds are represented as
nanoSeconds = 0x0000_0001.
The nanoseconds field supports the following two modes:
– Digital rollover mode: In digital rollover mode, the maximum value in the
nanoseconds field is 0x3B9A_C9FF, that is, (10e9-1) nanoseconds.
– Binary rollover mode: In binary rollover mode, the nanoseconds field rolls over and
increments the seconds field after value 0x7FFF_FFFF. Accuracy is ~0.466 ns per
bit.
You can set these modes by using the bit 9 (TSCTRLSSR) of Table 617.
When you select the advanced timestamp feature, the timestamp maintained in the core is
still 64-bit wide. The overflow to the upper 16-bits of seconds register happens once in
130 years. You can read the values of the upper 16-bits of the seconds field from the CSR
register.

28.7.5.5 Transmit path functions
There is no change in the transmit path functions for the Advanced timestamp feature.
The structure of the descriptor changes when you enable the advanced timestamp
feature. The advanced timestamp feature is supported only through Alternate (Enhanced)
descriptors format. The descriptor is 32-bytes long (8 DWORDS) and the snapshot of the
timestamp is written in descriptor TDES6 and TDES7. For detailed information about
descriptors, see Section 28.7.6.3.

28.7.5.6 Receive path functions
When you select the advanced timestamp feature, the MAC processes the received
frames to identify valid PTP frames. You can control the snapshot of the time, to be sent to
the application, by using the following options of the timestamp control register
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(Section 28.6.16):

• When you select the advanced timestamp feature, the MAC processes the received
frames to identify valid PTP frames. You can control the snapshot of the time, to be
sent to the application, by using the following options of the Timestamp Control
Register.

• When you select the advanced timestamp feature, the MAC processes the received
frames to identify valid PTP frames. You can control the snapshot of the time, to be
sent to the application, by using the following options of Register 448 (Timestamp
Control Register).

• Enable snapshot for PTP frames transmitted directly over Ethernet or
UDP-IP-Ethernet.

• Enable timestamp snapshot for the received frame for IPv4 or IPv6.
• Enable timestamp snapshot for EVENT messages (SYNC, DELAY_REQ,
PDELAY_REQ or PDELAY_RESP) only.

• Enable the node to be a Master or Slave and select the snapshot type. This controls
the type of messages for which snapshots are taken.
Remark: The ethernet controller also supports PTP messages over VLAN frames.
The MAC provides the time stamp, along with EOF. An additional signal validates the
presence of timestamp for the receive frame.
The MTL provides the time stamp on the data bus after the EOF data has been
transferred. An additional signal validates the timestamp. This signal is asserted to
indicate the availability of timestamp. Once the timestamp is transferred, the MTL sends
the receive status to the application. In 32-bit datawidth mode, the MTL provides the
additional status related to the timestamp on the data bus after the normal status is read.
The additional status is provided only when the bit 0 of the normal status is set and is
validated.
The DMA returns the time stamp to the software inside the corresponding Transmit and
Receive Descriptor. The advanced timestamp feature is supported only with the 32-bytes
long Alternate (Enhanced) descriptor. The extended status, containing the timestamp
message status and the IPC status, is written in descriptor RDES4 and the snapshot of
the timestamp is written in descriptors RDES6 and RDES7. For detailed information about
descriptors, see Section 28.7.6.3.

28.7.6 DMA controller description
The DMA has independent Transmit and Receive engines and a CSR space. The
Transmit engine transfers data from system memory to the device port (MTL), while the
Receive engine transfers data from the device port to the system memory. The controller
uses descriptors to efficiently move data from source to destination with minimal Host
CPU intervention. The DMA is designed for packet-oriented data transfers such as frames
in Ethernet. The controller can be programmed to interrupt the Host CPU for situations
such as Frame Transmit and Receive transfer completion, and other normal/error
conditions.
The DMA and the Host driver communicate through two data structures:

• Control and Status registers (CSR). See Section 28.6.
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• Descriptor lists and data buffers. See Section 28.7.6.3.
The DMA transfers data frames received by the core to the Receive Buffer in the Host
memory, and Transmit data frames from the Transmit Buffer in the Host memory.
Descriptors that reside in the Host memory act as pointers to these buffers. There are two
descriptor lists; one for reception, and one for transmission. The base address of each list
is written into DMA Registers Table 633 and Table 634. A descriptor list is forward linked
(either implicitly or explicitly). The last descriptor may point back to the first entry to create
a ring structure. Explicit chaining of descriptors is accomplished by setting the second
address chained in both Receive and Transmit descriptors (RDES1[24] and TDES1[24]).
The descriptor lists resides in the Host physical memory address space. Each descriptor
can point to a maximum of two buffers. This enables two buffers to be used, physically
addressed, rather than contiguous buffers in memory.
A data buffer resides in the Host physical memory space, and consists of an entire frame
or part of a frame, but cannot exceed a single frame. Buffers contain only data, buffer
status is maintained in the descriptor. Data chaining refers to frames that span multiple
data buffers. However, a single descriptor cannot span multiple frames. The DMA skips to
the next frame buffer when end-of-frame is detected. Data chaining can be enabled or
disabled.

Ring Structure

Chain Structure

Buffer 1

Buffer 1

Descriptor 0

Descriptor 0
Buffer 2

Buffer 1
Descriptor 1

Buffer 2

Buffer 1
Descriptor 1

Buffer 1
Descriptor 2
Buffer 2

Buffer 1
Descriptor 2
Buffer 1
Descriptor n
Buffer 2

Next Descriptor

Fig 84. Descriptor ring and chain structure

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28.7.6.1 Initialization
Follow these steps to initialize the ethernet controller:
1. Write to DMA Register Table 629 to set Host bus access parameters.
2. Write to DMA Register Table 637 to mask unnecessary interrupt causes.
3. The software driver creates the Transmit and Receive descriptor lists. Then it writes to
both DMA Register Table 633 and DMA Register Table 634, providing the DMA with
the starting address of each list.
4. Write to MAC Registers Table 602, Table 604, and Table 603 for desired filtering
options.
5. Write to MAC Register Table 601 to configure the operating mode and enable the
transmit operation (bit 3: Transmitter Enable). The PS and DM bits are set based on
the auto-negotiation result (read from the PHY).
6. Write to DMA Register Table 636 to set bits 13 and 1 to start transmission and
reception.
7. Write to MAC Register Table 601 to enable the Receive operation (bit 2: Receiver
Enable).
The Transmit and Receive engines enter the Running state and attempt to acquire
descriptors from the respective descriptor lists. The Receive and Transmit engines then
begin processing Receive and Transmit operations. The Transmit and Receive processes
are independent of each other and can be started or stopped separately.
28.7.6.1.1

Host bus burst access
The DMA attempts to execute fixed-length Burst transfers on the AHB Master interface if
configured to do so (FB bit of DMA Register 0). The maximum Burst length is indicated
and limited by the PBL field (DMA Register 0[13:8]). The Receive and Transmit
descriptors are always accessed in the maximum possible (limited by PBL or 16 x 8/bus
width) burst-size for the 16-bytes to be read.
The Transmit DMA initiates a data transfer only when sufficient space to accommodate
the configured burst is available in MTL Transmit FIFO or the number of bytes till the end
of frame (when it is less than the configured burst-length). The DMA indicates the start
address and the number of transfers required to the AHB Master Interface. When the AHB
Interface is configured for fixed-length burst, then it transfers data using the best
combination of INCR4/8/16 and SINGLE transactions. Otherwise (no fixed-length burst), it
transfers data using INCR (undefined length) and SINGLE transactions.
The Receive DMA initiates a data transfer only when sufficient data to accommodate the
configured burst is available in MTL Receive FIFO or when the end of frame (when it is
less than the configured burst-length) is detected in the Receive FIFO. The DMA indicates
the start address and the number of transfers required to the AHB Master Interface. When
the AHB Interface is configured for fixed-length burst, then it transfers data using the best
combination of INCR4/8/16 and SINGLE transactions. If the end-of frame is reached
before the fixed-burst ends on the AHB interface, then dummy transfers are performed in
order to complete the fixed-burst. Otherwise (FB bit of DMA Register Table 629 is reset), it
transfers data using INCR (undefined length) and SINGLE transactions.

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When the AHB interface is configured for address-aligned beats, both DMA engines
ensure that the first burst transfer the AHB initiates is less than or equal to the size of the
configured PBL. Thus, all subsequent beats start at an address that is aligned to the
configured PBL. The DMA can only align the address for beats up to size 16 (for PBL >
16), because the AHB interface does not support more than INCR16.
28.7.6.1.2

Host data buffer alignment
The Transmit and Receive data buffers do not have any restrictions on start address
alignment. For example, in systems with 32-bit memory, the start address for the buffers
can be aligned to any of the four bytes. However, the DMA always initiates transfers with
address aligned to the bus width with dummy data for the byte lanes not required. This
typically happens during the transfer of the beginning or end of an Ethernet frame.
Example: Buffer read
If the Transmit buffer address is 0x00000FF2 (for 32-bit data bus), and 15 bytes need to
be transferred, then the DMA reads five full words from address 0x00000FF0, but when
transferring data to the MTL Transmit FIFO, the extra bytes (the first two bytes) are
dropped or ignored. Similarly, the last 3 bytes of the last transfer are also ignored. The
DMA always ensures it transfers a full 32-bit data to the MTL Transmit FIFO, unless it is
the end-of-frame.
Example: Buffer write
If the Receive buffer address is 0x0000FF2 (for 64-bit data bus) and 16 bytes of a
received frame need to be transferred, then the DMA writes 3 full words from address
0x00000FF0. But the first 2 bytes of first transfer and the last 6 bytes of the third transfer
have dummy data.

28.7.6.1.3

Buffer size calculations
The DMA does not update the size fields in the Transmit and Receive descriptors. The
DMA updates only the status fields (RDES and TDES) of the descriptors. The driver has
to perform the size calculations.
The transmit DMA transfers the exact number of bytes (indicated by buffer size field of
TDES1) towards the MAC core. If a descriptor is marked as first (FS bit of TDES1 is set),
then the DMA marks the first transfer from the buffer as the start of frame. If a descriptor is
marked as last (LS bit of TDES1), then the DMA marks the last transfer from that data
buffer as the end-of frame to the MTL.
The Receive DMA transfers data to a buffer until the buffer is full or the end-of frame is
received from the MTL. If a descriptor is not marked as last (LS bit of RDES0), then the
descriptor’s corresponding buffer(s) are full and the amount of valid data in a buffer is
accurately indicated by its buffer size field minus the data buffer pointer offset when the
FS bit of that descriptor is set. The offset is zero when the data buffer pointer is aligned to
the data bus width. If a descriptor is marked as last, then the buffer may not be full (as
indicated by the buffer size in RDES1). To compute the amount of valid data in this final
buffer, the driver must read the frame length (FL bits of RDES0[29:16]) and subtract the
sum of the buffer sizes of the preceding buffers in this frame. The Receive DMA always
transfers the start of next frame with a new descriptor.
Remark: Even when the start address of a receive buffer is not aligned to the system
bus’s data width, the system should allocate a receive buffer of a size aligned to the
system bus width. For example, if the system allocates a 1,024-byte (1 KB) receive buffer

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starting from address 0x1000, the software can program the buffer start address in the
Receive descriptor to have a 0x1002 offset. The Receive DMA writes the frame to this
buffer with dummy data in the first two locations (0x1000 and 0x1001). The actual frame is
written from location 0x1002. Thus, the actual useful space in this buffer is 1,022 bytes,
even though the buffer size is programmed as 1,024 bytes, because of the start address
offset.
28.7.6.1.4

DMA arbiter
The arbiter inside the DMA module performs the arbitration between the Transmit and
Receive channel accesses to the AHB Master interface. Two types of arbitrations are
possible: round-robin, and fixed-priority.
When round-robin arbitration is selected (DA bit of Register Table 629 (Bus Mode
Register) is reset), the arbiter allocates the data bus in the ratio set by the PR bits of DMA
Register Table 629, when both Transmit and Receive DMAs are requesting for access
simultaneously. When the DA bit is set, the Receive DMA always gets priority over the
Transmit DMA for data access by default. When the TXPR bit (bit 27 of DMA register
Table 629) is also set, then the Transmit DMA gets priority over the Receive DMA.

28.7.6.2 Transmission
28.7.6.2.1

TxDMA operation: Default (non-OSF) mode
The transmit DMA engine in default mode proceeds as follows:
1. The Host sets up the transmit descriptor (TDES0-TDES3) and sets the Own bit
(TDES0[31]) after setting up the corresponding data buffer(s) with Ethernet Frame
data.
2. Once the ST bit (DMA Register) is set, the DMA enters the Run state.
3. While in the Run state, the DMA polls the Transmit Descriptor list for frames requiring
transmission. After polling starts, it continues in either sequential descriptor ring order
or chained order. If the DMA detects a descriptor flagged as owned by the Host, or if
an error condition occurs, transmission is suspended and both the Transmit Buffer
Unavailable (DMA Register Table 635) and Normal Interrupt Summary (DMA Register
Table 635) bits are set. The Transmit Engine proceeds to Step 9.
4. If the acquired descriptor is flagged as owned by DMA (TDES0[31] = 1), the DMA
decodes the Transmit Data Buffer address from the acquired descriptor.
5. The DMA fetches the Transmit data from the Host memory and transfers the data to
the MTL for transmission.
6. If an Ethernet frame is stored over data buffers in multiple descriptors, the DMA
closes the intermediate descriptor and fetches the next descriptor. Steps 3, 4, and 5
are repeated until the end-of-Ethernet-frame data is transferred to the MTL.
7. When frame transmission is complete, if IEEE 1588 Time stamping was enabled for the
frame (as indicated in the transmit status) the timestamp value obtained from MTL is
written to the transmit descriptor (TDES2 and TDES3) that contains the end-of-frame
buffer. The status information is then written to this transmit descriptor (TDES0).
Because the Own bit is cleared during this step, the Host now owns this descriptor. If
Time stamping was not enabled for this frame, the DMA does not alter the contents of
TDES2 and TDES3.

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8. Transmit Interrupt (DMA Register Table 635) is set after completing transmission of a
frame that has Interrupt on Completion (TDES1[31]) set in its Last Descriptor. The
DMA engine then returns to Step 3.
9. In the Suspend state, the DMA tries to re-acquire the descriptor (and thereby return to
Step 3) when it receives a Transmit Poll demand and the Underflow Interrupt Status
bit is cleared.
The TxDMA transmission flow in default mode is shown in Figure 85.

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Start TxDMA

Start

Stop TxDMA

(Re-)fetch next
descriptor

(AHB)
error?

Poll demand

Yes

No

TxDMA suspended

No

Own
bit set?
Yes

Transfer data from
buffer(s)

(AHB)
error?

Yes

No

No

Frame xfer
complete?
Yes

Close intermediate
descriptor

Wait for Tx status

Time stamp
present?

Yes

Write time stamp to
TDES2 and TDES3

No

Write status word
to TDES0

No

(AHB)
error?

No

(AHB)
error?

Yes

Yes

Fig 85. TxDMA operation in default mode

28.7.6.2.2

TxDMA operation: OSF mode
While in the Run state, the transmit process can simultaneously acquire two frames
without closing the Status descriptor of the first (if the OSF bit is set in DMA Operation
mode register, bit 2). As the transmit process finishes transferring the first frame, it

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immediately polls the Transmit Descriptor list for the second frame. If the second frame is
valid, the transmit process transfers this frame before writing the first frame’s status
information.
In OSF mode, the Run state Transmit DMA operates in the following sequence:
1. The DMA operates as described in steps 1 to 6 of the TxDMA (default mode).
2. Without closing the previous frame’s last descriptor, the DMA fetches the next
descriptor.
3. If the DMA owns the acquired descriptor, the DMA decodes the transmit buffer
address in this descriptor. If the DMA does not own the descriptor, the DMA goes into
Suspend mode and skips to Step 7.
4. The DMA fetches the Transmit frame from the Host memory and transfers the frame
to the MTL until the End-of-Frame data is transferred, closing the intermediate
descriptors if this frame is split across multiple descriptors.
5. The DMA waits for the previous frame’s frame transmission status and Time stamp.
Once the status is available, the DMA writes the Time stamp to TDES2 and TDES3, if
such Time stamp was captured (as indicated by a status bit). The DMA then writes the
status, with a cleared Own bit, to the corresponding TDES0, thus closing the
descriptor. If Time stamping was not enabled for the previous frame, the DMA does not
alter the contents of TDES2 and TDES3.
6. If enabled, the Transmit interrupt is set, the DMA fetches the next descriptor, then
proceeds to Step 3 (when Status is normal). If the previous transmission status shows
an underflow error, the DMA goes into Suspend mode (Step 7).
7. In Suspend mode, if a pending status and Time stamp are received from the MTL, the
DMA writes the Time stamp (if enabled for the current frame) to TDES2 and TDES3,
then writes the status to the corresponding TDES0. It then sets relevant interrupts and
returns to Suspend mode.
8. The DMA can exit Suspend mode and enter the Run state (go to Step 1 or Step 2
depending on pending status) only after receiving a Transmit Poll demand (DMA
Transmit Poll Demand register).
Remark: As the DMA fetches the next descriptor in advance before closing the current
descriptor, the descriptor chain should have more than 2 different descriptors for correct
and proper operation.
The basic flow is described in Figure 86.

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Start TxDMA

Start

Stop TxDMA

(Re-)fetch next
descriptor

(AHB)
error?

Poll
demand

Yes

No

TxDMA suspended

No

Own
bit set?
Yes

Previous frame
status available

Transfer data from
buffer(s)

(AHB)
error?

Time stamp
present?

Yes

No

Yes
No

Frame xfer
complete?

Write time stamp to
TDES2 & TDES3
for previous frame

No

Yes

No

Yes

Wait for previous
frame’s Tx status

Close intermediate
descriptor

(AHB)
error?

Yes

Time stamp
present?

No

Yes

Write time stamp to
TDES2 & TDES3
for previous frame

No

Write status word to
prev. frame’s TDES0

Write status word to
prev. frame’s TDES0

No

Second
frame?

(AHB)
error?

No

No

(AHB)
error?

Yes

(AHB)
error?
Yes

Yes

Fig 86. TxDMA operation in OSF mode

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28.7.6.2.3

Transmit frame processing
The Transmit DMA expects that the data buffers contain complete Ethernet frames,
excluding preamble, pad bytes, and FCS fields. The DA, SA, and Type/Len fields contain
valid data. If the Transmit Descriptor indicates that the MAC core must disable CRC or
PAD insertion, the buffer must have complete Ethernet frames (excluding preamble),
including the CRC bytes.
Frames can be data-chained and can span several buffers. Frames must be delimited by
the First Descriptor (TDES1[29]) and the Last Descriptor (TDES1[30]), respectively.
As transmission starts, the First Descriptor must have (TDES1[29]) set. When this occurs,
frame data transfers from the Host buffer to the MTL Transmit FIFO. Concurrently, if the
current frame has the Last Descriptor (TDES1[30]) clear, the Transmit Process attempts
to acquire the Next Descriptor. The Transmit Process expects this descriptor to have
TDES1[29] clear. If TDES1[30] is clear, it indicates an intermediary buffer. If TDES1[30] is
set, it indicates the last buffer of the frame.
After the last buffer of the frame has been transmitted, the DMA writes back the final
status information to the Transmit Descriptor 0 (TDES0) word of the descriptor that has
the last segment set in Transmit Descriptor 1 (TDES1[30]). At this time, if Interrupt on
Completion (TDES1[31]) was set, Transmit Interrupt (DMA Status register, bit 0) is set, the
Next Descriptor is fetched, and the process repeats.
The actual frame transmission begins after the MTL Transmit FIFO has reached either a
programmable transmit threshold (DMA Operation Mode register, bits [16:14]), or a full
frame is contained in the FIFO. There is also an option for Store and Forward Mode (DMA
Operation Mode register, bit [21]). Descriptors are released (Own bit TDES0[31] clears)
when the DMA finishes transferring the frame.
Remark: To ensure proper transmission of a frame and the next frame, you must specify
a non-zero buffer size for the transmit descriptor that has the Last Descriptor (TDES1[30])
set.

28.7.6.2.4

Transmit polling suspended
Transmit polling can be suspended by either of the following conditions:

• The DMA detects a descriptor owned by the Host (TDES0[31]=0). To resume, the
driver must give descriptor ownership to the DMA and then issue a Poll Demand
command.

• A frame transmission is aborted when a transmit error because of underflow is
detected. The appropriate Transmit Descriptor 0 (TDES0) bit is set.
If the second condition occur, both Abnormal Interrupt Summary (DMA Status register
Table 635) and Transmit Underflow bits (DMA Status register Table 635) are set, and the
information is written to Transmit Descriptor 0, causing the suspension. If the DMA goes
into SUSPEND state because of the first condition, then both Normal Interrupt Summary
(DMA Status register Table 635) and Transmit Buffer Unavailable (DMA Status register
Table 635) are set.
In both cases, the position in the Transmit List is retained. The retained position is that of
the descriptor following the Last Descriptor closed by the DMA.

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The driver must explicitly issue a Transmit Poll Demand command after rectifying the
suspension cause.
28.7.6.2.5

Reception
The Receive DMA engine’s reception sequence is shown in Figure 87 and proceeds as
follows:
1. The host sets up Receive descriptors (RDES0-RDES3) and sets the Own bit
(RDES0[31]).
2. Once the SR (DMA Operation Mode register Table 636) bit is set, the DMA enters the
Run state. While in the Run state, the DMA polls the Receive Descriptor list,
attempting to acquire free descriptors. If the fetched descriptor is not free (is owned by
the host), the DMA enters the Suspend state and jumps to Step 9.
3. The DMA decodes the receive data buffer address from the acquired descriptors.
4. Incoming frames are processed and placed in the acquired descriptor’s data buffers.
5. When the buffer is full or the frame transfer is complete, the Receive engine fetches
the next descriptor.
6. If the current frame transfer is complete, the DMA proceeds to Step 7. If the DMA
does not own the next fetched descriptor and the frame transfer is not complete (EOF
is not yet transferred), the DMA sets the Descriptor Error bit in the RDES0 (unless
flushing is disabled). The DMA closes the current descriptor (clears the Own bit) and
marks it as intermediate by clearing the Last Segment (LS) bit in the RDES0 value
(marks it as Last Descriptor if flushing is not disabled), then proceeds to Step 8. If the
DMA does own the next descriptor but the current frame transfer is not complete, the
DMA closes the current descriptor as intermediate and reverts to Step 4.
7. If IEEE 1588 Time stamping is enabled, the DMA writes the timestamp (if available) to
the current descriptor’s RDES2 and RDES3. It then takes the receive frame’s status
from the MTL and writes the status word to the current descriptor’s RDES0, with the
Own bit cleared and the Last Segment bit set.
8. The Receive engine checks the latest descriptor’s Own bit. If the host owns the
descriptor (Own bit is 0) the Receive Buffer Unavailable bit (DMA Status register
Table 635) is set and the DMA Receive engine enters the Suspended state (Step 9). If
the DMA owns the descriptor, the engine returns to Step 4 and awaits the next frame.
9. Before the Receive engine enters the Suspend state, partial frames are flushed from
the Receive FIFO (You can control flushing using Bit 24 of DMA Operation MOde
register Table 636).
10. The Receive DMA exits the Suspend state when a Receive Poll demand is given or
the start of next frame is available from the MTL’s Receive FIFO. The engine
proceeds to Step 2 and refetches the next descriptor.

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Start RxDMA

Poll demand /
new frame available

Stop RxDMA

(Re-)Fetch next
descriptor

(AHB)
error?

RxDMA suspended

Yes

No

Yes
Frame transfer
complete?

Yes

Start

No

Own bit set?

No

Yes

Flush disabled ?

Frame data
available ?

No

Yes

Flush the
remaining frame

Write data to buffer(s)

No

Wait for frame data

(AHB)
error?

Yes

No
Fetch next descriptor

(AHB)
error?

Yes

No

Flush
disabled ?
No

Set descriptor error

No

Yes

Own bit set
for next desc?

Yes

No

Frame transfer
complete?

Yes

Close RDES0 as
intermediate descriptor

Time stamp
present?

Yes

Write time stamp to
RDES2 & RDES3

No
Close RDES0 as last
descriptor

No

(AHB)
error?

No

(AHB)
error?

Yes

Yes

Fig 87. Receive DMA operation

The DMA does not acknowledge accepting the status from the MTL until it has completed
the Time stamp write-back and is ready to perform status write-back to the descriptor.

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If software has enabled Time stamping through CSR, when a valid Time stamp value is not
available for the frame (for example, because the receive FIFO was full before the Time
stamp could be written to it), the DMA writes all-ones to RDES2 and RDES3. Otherwise
(that is, if Time stamping is not enabled), the RDES2 and RDES3 remain unchanged.
28.7.6.2.6

Receive descriptor acquisition
The Receive Engine always attempts to acquire an extra descriptor in anticipation of an
incoming frame. Descriptor acquisition is attempted if any of the following conditions is
satisfied:

• The receive Start/Stop bit (DMA Operation Mode register Table 636) has been set
immediately after being placed in the Run state.

• The data buffer of current descriptor is full before the frame ends for the current
transfer.

• The controller has completed frame reception, but the current Receive Descriptor is
not yet closed.

• The receive process has been suspended because of a host-owned buffer
(RDES0[31] = 0) and a new frame is received.

• A Receive poll demand has been issued.
28.7.6.2.7

Receive frame processing
The MAC transfers the received frames to the Host memory only when the frame passes
the address filter and frame size is greater than or equal to configurable threshold bytes
set for the Receive FIFO of MTL, or when the complete frame is written to the FIFO in
Store-and-Forward mode.
If the frame fails the address filtering, it is dropped in the MAC block itself (unless Receive
All bit 31 is set in the MAC Frame Filter register; Table 602). Frames that are shorter than
64 bytes, because of collision or premature termination, can be purged from the MTL
Receive FIFO.
After 64 (configurable threshold) bytes have been received, the MTL block requests the
DMA block to begin transferring the frame data to the Receive Buffer pointed to by the
current descriptor. The DMA sets First Descriptor (RDES0[9]) after the DMA Host
Interface (AHB or MDC) becomes ready to receive a data transfer (if DMA is not fetching
transmit data from the host), to delimit the frame. The descriptors are released when the
Own (RDES[31]) bit is reset to 0, either as the Data buffer fills up or as the last segment of
the frame is transferred to the Receive buffer. If the frame is contained in a single
descriptor, both Last Descriptor (RDES[8]) and First Descriptor (RDES[9]) are set.
The DMA fetches the next descriptor, sets the Last Descriptor (RDES[8]) bit, and releases
the RDES0 status bits in the previous frame descriptor. Then the DMA sets Receive
Interrupt (Register 5[6]). The same process repeats unless the DMA encounters a
descriptor flagged as being owned by the host. If this occurs, the Receive Process sets
Receive Buffer Unavailable (DMA Status register Table 635) and then enters the Suspend
state. The position in the receive list is retained.

28.7.6.2.8

Receive process suspended
If a new Receive frame arrives while the Receive Process is in Suspend state, the DMA
refetches the current descriptor in the Host memory. If the descriptor is now owned by the
DMA, the Receive Process re-enters the Run state and starts frame reception. If the

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descriptor is still owned by the host, by default, the DMA discards the current frame at the
top of the MTL Rx FIFO and increments the missed frame counter. If more than one frame
is stored in the MTL Rx FIFO, the process repeats.
The discarding or flushing of the frame at the top of the MTL Rx FIFO can be avoided by
setting Operation Mode register bit 24 (DFF) in Table 636. In such conditions, the receive
process sets the Receive Buffer Unavailable status and returns to the Suspend state.
28.7.6.2.9

Interrupts
Interrupts can be generated as a result of various events. The DMA Status register
(Table 635) contains all the bits that might cause an interrupt. Table 637 contains an
enable bit for each of the events that can cause an interrupt.
There are two groups of interrupts, Normal and Abnormal, as described in DMA Status
register (Table 635). Interrupts are cleared by writing a 1 to the corresponding bit position.
When all the enabled interrupts within a group are cleared, the corresponding summary
bit is cleared. When both the summary bits are cleared, the interrupt signal is de-asserted.
If the MAC core is the cause for assertion of the interrupt, then any of the GLI, GMI, or GPI
bits of DMA Status register (Table 635) are set HIGH.
Remark: The DMA Status register (Table 635) is the (interrupt) status register. The
interrupt pin is asserted because of any event in this status register only if the
corresponding interrupt enable bit is set in DMA Interrupt Enable Register (Table 637).
Interrupts are not queued and if the interrupt event occurs before the driver has
responded to it, no additional interrupts are generated. For example, the Receive Interrupt
(bit 6 of the DMA Status Register (Table 635) indicates that one or more frames were
transferred to the Host buffer. The driver must scan all descriptors, from the last recorded
position to the first one owned by the DMA.
An interrupt is generated only once for simultaneous, multiple events. The driver must
scan the DMA Status register (Table 635) for the cause of the interrupt. The interrupt is not
generated again unless a new interrupting event occurs, after the driver has cleared the
appropriate bit in DMA Status register. For example, the controller generates a DMA
Receive interrupt (bit 6 of the DMA Status register), and the driver begins reading DMA
Status register. Next, Receive Buffer Unavailable (bit 7 of DMA Status register (Status
Register)) occurs. The driver clears the Receive interrupt. Even then, the sbd_intr_o
signal is not de-asserted, because of the active or pending Receive Buffer Unavailable
interrupt.
An interrupt timer RIWT (bits 7:0 in Receive Interrupt Watchdog Timer Register
(Table 639)) is given for flexible control of Receive Interrupt. When this Interrupt timer is
programmed with a non-zero value, it gets activated as soon as the RxDMA completes a
transfer of a received frame to system memory without asserting the Receive Interrupt
because it is not enabled in the corresponding Receive Descriptor (RDES1[31]. When this
timer runs out as per the programmed value, RI bit is set and the interrupt is asserted if
the corresponding RI is enabled in DMA Interrupt Enable register (Table 637). This timer
gets disabled before it runs out, when a frame is transferred to memory and the RI is set
because it is enabled for that descriptor.

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28.7.6.2.10

Error response to DMA
For any data transfer initiated by a DMA channel, if the slave replies with an error
response, that DMA stops all operations and updates the error bits and the Fatal Bus
Error bit in the DMA Status register (Table 635). That DMA controller can resume
operation only after soft resetting or hard resetting the core and re-initializing the DMA.
This DMA behavior is true for non-AHB interfaced DMAs that receive an error response.

28.7.6.3 Ethernet descriptors
The descriptor structure supports up to 8 DWORDS (32 bytes) and the IEEE 1588-2008
Advanced Timestamp feature. The features of the descriptor structure are:

• Descriptor size can be 4 DWORDS (16 bytes) or 8 DWORDS (32 bytes) depending
on the setting of the ATDS bit in the DMA Bus Mode register (Table 629).

• Support buffers of up to 8 KB (useful for Jumbo frames).
• The transmit descriptor stores the timestamp in TDES6 and TDES7 when you select
the Advanced Timestamp.

• This receive descriptor structure is also used for storing the extended status (RDES4)
and timestamp (RDES6 and RDES7) when advanced timestamp feature or IPC full
offload is selected.

• When the descriptor mode is selected, and the Timestamp feature is enabled, the
software needs to allocate 32-bytes (8 DWORDS) of memory for every descriptor.
When Timestamping or Receive IPC FullOffload engine are not enabled, the
extended descriptors are not required and the SW can use alternate descriptors with
the default size of 16 bytes. The core also needs to be configured for this change
using the bit 7 (ATDS: Alternate Descriptor Size) of DMA Bus Mode register
(Table 629).

• When a descriptor is chosen without Timestamp or Full IPC Offload feature, the
descriptor size is always 4 DWORDs (DES0-DES3).
28.7.6.3.1

Transmit descriptor
The transmit descriptor structure is shown in Figure 88. The application software must
program the control bits TDES0[31:20] during descriptor initialization. When the DMA
updates the descriptor, it write backs all the control bits except the OWN bit (which it
clears) and updates the status bits[19:0]. The contents of the transmitter descriptor word 0
(TDES0) through word 3 (TDES3) are given in Table 653 through Table 656, respectively.
With the advance timestamp support, the snapshot of the timestamp to be taken can be
enabled for a given frame by setting bit TTSE: Transmit Timestamp Enable. (bit-25 of
TDES0). When the descriptor is closed (i.e. when the OWN bit is cleared), the time-stamp
is written into TDES6 and TDES7. This is indicated by the status bit TTSS: Transmit
Timestamp Status. (bit-17 of TDES0). This is shown in Figure 88. The contents of TDES6
and TDES7 are mentioned in Table 657 to Table 658.
When either Advanced Timestamp or IPC Offload (Type 2) features is enabled, the SW
should set the DMA Bus Mode register[7], so that the DMA operates with extended
descriptor size. When this control bit is reset, the TDES4-TDES7 descriptor space are not
valid.

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31

0

O
W
TDES0
N

TDES1

Ctrl
[30:26]
R
E
S

T
T
S
E

R
E
S

Ctrl
[23:20]

R
E
S

T
T
T
S

Buffer 2 Byte Count [28:16]

Status [16:0]

R
E
S

Buffer 1 Byte Count [12:0]

TDES2

Buffer 1 Address [31:0]

TDES3

Buffer 2 Address [31:0] or Next Descriptor Address [31:0]

TDES4

Reserved

TDES5

Reserved

TDES6

Transmit Time Stamp Low [31:0]

TDES7

Transmit Time Stamp High [31:0]

Fig 88. Transmitter descriptor fields

The DMA always reads or fetches four DWORDS of the descriptor from system memory
to obtain the buffer and control information as shown in Figure 89. When Advanced
timestamp feature support is enabled, TDES0 has additional control bits[6:3] for channel 1
and channel 2. For channel 0, the bits 6:3 are ignored. The bits 6:3 are described in
Table 653.

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31

0

O
W
TDES0
N

TDES1

Ctrl
[30:26]
R
E
S

T
T
S
E

R
E
S

Ctrl
[23:20]

R
E
S

SLOT
Number
[6:3]

Reserved for
Status [17:7]

Buffer 2 Byte Count [28:16]

R
E
S

Reserved for
Status [3:0]

Buffer 1 Byte Count [12:0]

TDES2

Buffer 1 Address [31:0]

TDES3

Buffer 2 Address [31:0] or Next Descriptor Address [31:0]

Fig 89. Transmit descriptor fetch (read)
Table 653. Transmit descriptor word 0 (TDES0)
Bit

Symbol

Description

0

DB

Deferred Bit
When set, this bit indicates that the MAC defers before transmission because of the presence of
carrier. This bit is valid only in Half-Duplex mode.

1

UF

Underflow Error
When set, this bit indicates that the MAC aborted the frame because data arrived late from the Host
memory. Underflow Error indicates that the DMA encountered an empty transmit buffer while
transmitting the frame. The transmission process enters the Suspended state and sets both
Transmit Underflow (Register 5[5]) and Transmit Interrupt (Register 5[0]).

2

ED

Excessive Deferral
When set, this bit indicates that the transmission has ended because of excessive deferral of over
24,288 bit times (155,680 bits times in 1,000-Mbps mode or if Jumbo Frame is enabled) if the
Deferral Check (DC) bit in the MAC Control register is set high.

6:3

CC/
CC: Collision Count (Status field)
SLOTNUM These status bits indicate the number of collisions that occurred before the frame was transmitted.
This count is not valid when the Excessive Collisions bit (TDES0[8]) is set. The core updates this
status field only in the half-duplex mode.
SLOTNUM: Slot Number Control Bits in AV Mode
These bits indicate the slot interval in which the data should be fetched from the corresponding
buffers addressed by TDES2 or TDES3. When the transmit descriptor is fetched, the DMA
compares the slot number value in this field with the slot interval maintained in the core . It fetches
the data from the buffers only if there is a match in values. These bits are valid only for the AV
channels (not channel 0).

7

VF

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Table 653. Transmit descriptor word 0 (TDES0)
Bit

Symbol

Description

8

EC

Excessive Collision
When set, this bit indicates that the transmission was aborted after 16 successive collisions while
attempting to transmit the current frame. If the DR (Disable Retry) bit in the MAC Configuration
register is set, this bit is set after the first collision, and the transmission of the frame is aborted.

9

LC

Late Collision
When set, this bit indicates that frame transmission was aborted due to a collision occurring after the
collision window (64 byte-times, including preamble, in MII mode and 512 byte-times, including
preamble and carrier extension, in MII mode). This bit is not valid if the Underflow Error bit is set.

10

NC

No Carrier
When set, this bit indicates that the Carrier Sense signal form the PHY was not asserted during
transmission.

11

LC

Loss of Carrier
When set, this bit indicates that a loss of carrier occurred during frame transmission. This is valid
only for the frames transmitted without collision when the MAC operates in Half-Duplex mode.

12

IPE

IP Payload Error
When set, this bit indicates that MAC transmitter detected an error in the TCP, UDP, or ICMP IP
datagram payload.
The transmitter checks the payload length received in the IPv4 or IPv6 header against the actual
number of TCP, UDP, or ICMP packet bytes received from the application and issues an error status
in case of a mismatch.

13

FF

Frame Flushed
When set, this bit indicates that the DMA/MTL flushed the frame due to a software Flush command
given by the CPU.

14

JT

Jabber Timeout
When set, this bit indicates the MAC transmitter has experienced a jabber time-out. This bit is only
set when the MAC configuration register’s JD bit is not set.

15

ES

Error Summary
Indicates the logical OR of the following bits:
• TDES0[14]: Jabber Timeout
• TDES0[13]: Frame Flush
• TDES0[11]: Loss of Carrier
• TDES0[10]: No Carrier
• TDES0[9]: Late Collision
• TDES0[8]: Excessive Collision
• TDES0[2]: Excessive Deferral
• TDES0[1]: Underflow Error
• TDES0[16]: IP Header Error
• TDES0[12]: IP Payload Error

16

IHE

IP Header Error
When set, this bit indicates that the MAC transmitter detected an error in the IP datagram header.
The transmitter checks the header length in the IPv4 packet against the number of header bytes
received from the application and indicates an error status if there is a mismatch. For IPv6 frames, a
header error is reported if the main header length is not 40 bytes. Furthermore, the Ethernet
Length/Type field value for an IPv4 or IPv6 frame must match the IP header version received with
the packet. For IPv4 frames, an error status is also indicated if the Header Length field has a value
less than 0x5.

17

TTSS

Transmit Timestamp Status
This field is used as a status bit to indicate that a timestamp was captured for the described transmit
frame. When this bit is set, TDES2 and TDES3 have a timestamp value captured for the transmit
frame. This field is only valid when the descriptor’s Last Segment control bit (TDES0[29]) is set.

19:18

-

Reserved

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Table 653. Transmit descriptor word 0 (TDES0)
Bit

Symbol

Description

20

TCH

Second Address Chained
When set, this bit indicates that the second address in the descriptor is the Next Descriptor address
rather than the second buffer address. When TDES0[20] is set, TBS2 (TDES1[28:16]) is a “don’t
care” value. TDES0[21] takes precedence over TDES0[20].

21

TER

Transmit End of Ring
When set, this bit indicates that the descriptor list reached its final descriptor. The DMA returns to
the base address of the list, creating a descriptor ring.

23:22

-

Reserved

24

-

Reserved

25

TTSE

Transmit Timestamp Enable
When set, this bit enables IEEE1588 hardware Time stamping for the transmit frame referenced by
the descriptor. This field is valid only when the First Segment control bit (TDES0[28]) is set.

26

DP

Disable Pad
When set, the MAC does not automatically add padding to a frame shorter than 64 bytes. When this
bit is reset, the DMA automatically adds padding and CRC to a frame shorter than 64 bytes, and the
CRC field is added despite the state of the DC (TDES0[27]) bit. This is valid only when the first
segment (TDES0[28]) is set.

27

DC

Disable CRC
When this bit is set, the MAC does not append a cyclic redundancy check (CRC) to the end of the
transmitted frame. This is valid only when the first segment (TDES0[28]) is set.

28

FS

First Segment
When set, this bit indicates that the buffer contains the first segment of a frame.

29

LS

Last Segment
When set, this bit indicates that the buffer contains the last segment of the frame. When this bit is
set, the TBS1: Transmit Buffer 1 Size or TBS2: Transmit Buffer 2 Size field in TDES1 should have a
non-zero value.

30

IC

Interrupt on Completion
When set, this bit sets the Transmit Interrupt (Register 5[0]) after the present frame has been
transmitted.

31

OWN

Own Bit
When set, this bit indicates that the descriptor is owned by the DMA. When this bit is reset, it
indicates that the descriptor is owned by the Host. The DMA clears this bit either when it completes
the frame transmission or when the buffers allocated in the descriptor are read completely. The
ownership bit of the frame’s first descriptor must be set after all subsequent descriptors belonging to
the same frame have been set. This avoids a possible race condition between fetching a descriptor
and the driver setting an ownership bit.
Table 654. Transmit descriptor word 1 (TDES1)

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Bit

Symbol Description

12:0

TBS1

Transmit buffer 1 size
These bits indicate the first data buffer byte size, in bytes. If this field is 0, the
DMA ignores this buffer and uses Buffer 2 or the next descriptor, depending
on the value of TCH (TDES0[20]).

15:13

-

Reserved

28:16

TBS2

These bits indicate the second data buffer size in bytes. This field is not valid
if TDES0[20] is set. See Section 28.7.6.1.3.

31:29

-

Reserved

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Table 655. Transmit descriptor word 2 (TDES2)
Bit

Symbol Description

31:0

B1ADD

Buffer 1 Address Pointer
These bits indicate the physical address of Buffer 1. There is no limitation on
the buffer address alignment. See Section 28.7.6.1.2 for further detail on
buffer address alignment.

Table 656. Transmit descriptor word 3 (TDES3)
Bit

Symbol Description

31:0

B2ADD

Buffer 2 Address Pointer (Next Descriptor Address)
Indicates the physical address of Buffer 2 when a descriptor ring structure is
used. If the Second Address Chained (TDES1[24]) bit is set, this address
contains the pointer to the physical memory where the Next Descriptor is
present. The buffer address pointer must be aligned to the bus width only
when TDES1[24] is set. (LSBs are ignored internally.)

Table 657. Transmit descriptor word 6 (TDES6)
Bit

Symbol Description

31:0

TTSL

Transmit Frame Timestamp Low
This field is updated by DMA with the least significant 32 bits of the
timestamp captured for the corresponding transmit frame. This field has the
timestamp only if the Last Segment bit (LS) in the descriptor is set and
Timestamp status (TTSS) bit is set.

Table 658. Transmit descriptor word 7 (TDES7)

28.7.6.3.2

Bit

Symbol Description

31:0

TTSH

Transmit Frame Timestamp High
This field is updated by DMA with the most significant 32 bits of the
timestamp captured for the corresponding receive frame. This field has the
timestamp only if the Last Segment bit (LS) in the descriptor is set and
Timestamp status (TTSS) bit is set.

Receive descriptor
The structure of the received descriptor is shown in Figure 90. This can have 32 bytes of
descriptor data (8 DWORDs) when Advanced Timestamp is selected.
Remark: The SW should set the DMA Bus Mode register[7] so that the DMA operates
with extended descriptor size. When this control bit is reset, RDES0[7] and RDES0[0] is
always cleared and the RDES4-RDES7 descriptor space are not valid.

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31

RDES0

RDES1

0

O
W
N

Status [30:0]

CTRL

RES Buffer 2 Byte Count
[30:29]
[28:16]

CTRL
[15:14]

RES

Buffer 1 Byte Count
[12:0]

RDES2

Buffer 1 Address [31:0]

RDES3

Buffer 2 Address [31:0] or Next Descriptor Address [31:0]

RDES4

Extended Status [31:0]

RDES5

Reserved

RDES6

Receive Time Stamp Low [31:0]

RDES7

Receive Time Stamp High [31:0]

Fig 90. Receive descriptor fields (alternate configuration)

The contents of RDES0 are identified in Table 659. The contents of RDES1 through
RDES3 are identified in Table 660 to Table 662.

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Table 659. Receive descriptor fields 0 (RDES0)

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Bit

Symbol

Description

0

ESA

Extended Status Available/Rx MAC Address
When Advanced Timestamp is present, this bit, when set, indicates that the
extended status is available in descriptor word 4 (RDES4). This is valid only
when the Last Descriptor bit (RDES0[8]) is set. When Advance Timestamp
Feature is not selected, this bit indicates Rx MAC Address status. When set,
this bit indicates that the Rx MAC Address registers value (1 to 31) matched
the frame’s DA field. When reset, this bit indicates that the Rx MAC Address
Register 0 value matched the DA field.

1

CE

CRC Error
When set, this bit indicates that a Cyclic Redundancy Check (CRC) Error
occurred on the received frame. This field is valid only when the Last
Descriptor (RDES0[8]) is set.

2

DE

Dribble Bit Error
When set, this bit indicates that the received frame has a non-integer multiple
of bytes (odd nibbles). This bit is valid only in MII Mode.

3

RE

Receive Error
When set, this bit indicates that the receive error signal is asserted while
receive data valid signal is asserted during frame reception. This error also
includes carrier extension error in MII and Half-duplex mode. Error can be of
less/no extension, or error (rxd  0f) during extension.

4

RWT

Receive Watchdog Timeout
When set, this bit indicates that the Receive Watchdog Timer has expired
while receiving the current frame and the current frame is truncated after the
Watchdog Timeout.

5

FT

Frame Type
When set, this bit indicates that the Receive Frame is an Ethernet-type frame
(the LT field is greater than or equal to 0x0600). When this bit is reset, it
indicates that the received frame is an IEEE802.3 frame. This bit is not valid
for Runt frames less than 14 bytes.

6

LC

Late Collision
When set, this bit indicates that a late collision has occurred while receiving
the frame in Half-Duplex mode.

7

TSA

Timestamp Available when Advanced Timestamp feature is present.
When set, this bit indicates that a snapshot of the Timestamp is written in
descriptor words 6 (RDES6) and 7 (RDES7). This is valid only when the Last
Descriptor bit (RDES0[8]) is set.

8

LS

Last Descriptor
When set, this bit indicates that the buffers pointed to by this descriptor are the
last buffers of the frame

9

FS

First Descriptor
When set, this bit indicates that this descriptor contains the first buffer of the
frame. If the size of the first buffer is 0, the second buffer contains the
beginning of the frame. If the size of the second buffer is also 0, the next
Descriptor contains the beginning of the frame.

10

VLAN

VLAN Tag
When set, this bit indicates that the frame pointed to by this descriptor is a
VLAN frame tagged by the MAC Core.

11

OE

Overflow Error
When set, this bit indicates that the received frame was damaged due to
buffer overflow in MTL.

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Table 659. Receive descriptor fields 0 (RDES0)

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Bit

Symbol

Description

12

LE

Length Error
When set, this bit indicates that the actual length of the frame received and
that the Length/ Type field does not match. This bit is valid only when the
Frame Type (RDES0[5]) bit is reset.

13

SAF

Source Address Filter Fail
When set, this bit indicates that the SA field of frame failed the SA Filter in the
MAC Core.

14

DE

Descriptor Error
When set, this bit indicates a frame truncation caused by a frame that does not
fit within the current descriptor buffers, and that the DMA does not own the
Next Descriptor. The frame is truncated. This field is valid only when the Last
Descriptor (RDES0[8]) is set.

15

ES

ES: Error Summary
Indicates the logical OR of the following bits:
• RDES0[1]: CRC Error
• RDES0[3]: Receive Error
• RDES0[4]: Watchdog Timeout
• RDES0[6]: Late Collision
• RDES0[7]: Giant Frame
• RDES4[4:3]: IP Header/Payload Error
• RDES0[11]: Overflow Error
• RDES0[14]: Descriptor Error
This field is valid only when the Last Descriptor (RDES0[8]) is set.

29:16

FL

Frame Length
These bits indicate the byte length of the received frame that was transferred
to host memory (including CRC). This field is valid when Last Descriptor
(RDES0[8]) is set and either the Descriptor Error (RDES0[14]) or Overflow
Error bits are reset. This field is valid when Last Descriptor (RDES0[8]) is set.
When the Last Descriptor and Error Summary bits are not set, this field
indicates the accumulated number of bytes that have been transferred for the
current frame.

30

AFM

Destination Address Filter Fail
When set, this bit indicates a frame that failed in the DA Filter in the MAC
Core.

31

OWN

Own Bit
When set, this bit indicates that the descriptor is owned by the DMA of the
MAC Subsystem. When this bit is reset, this bit indicates that the descriptor is
owned by the Host. The DMA clears this bit either when it completes the frame
reception or when the buffers that are associated with this descriptor are full.

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Table 660. Receive descriptor fields 1 (RDES1)
Bit

Symbol

Description

12:0

RBS1

Receive Buffer 1 Size
Indicates the first data buffer size in bytes. The buffer size must be a multiple
of 4, 8, or 16, depending upon the bus widths (32, 64, or 128), even if the
value of RDES2 (buffer1 address pointer) is not aligned. When the buffer
size is not a multiple of 4, 8, or 16, the resulting behavior is undefined. If this
field is 0, the DMA ignores this buffer and uses Buffer 2 or next descriptor
depending on the value of RCH (Bit 14). See Section 28.7.6.1.3 for further
details on calculating buffer sizes.

13

-

Reserved

14

RCH

Second Address Chained
When set, this bit indicates that the second address in the descriptor is the
Next Descriptor address rather than the second buffer address. When this
bit is set, RBS2 (RDES1[28:16]) is a “don’t care” value. RDES1[15] takes
precedence over RDES1[14].

15

RER

Receive End of Ring
When set, this bit indicates that the descriptor list reached its final descriptor.
The DMA returns to the base address of the list, creating a descriptor ring.

28:16

RBS2

Receive Buffer 2 Size
These bits indicate the second data buffer size, in bytes. The buffer size
must be a multiple of 4, even if the value of RDES3 (buffer2 address pointer)
is not aligned to bus width. If the buffer size is not an appropriate multiple of
4, the resulting behavior is undefined. This field is not valid if RDES1[14] is
set. See Section 28.7.6.1.3 for further details on calculating buffer sizes.

Table 661. Receive descriptor fields 2 (RDES2)
Bit

Symbol

Description

31:0

B1ADD

Address Pointer
These bits indicate the physical address of Buffer 1. There are no limitations
on the buffer address alignment except for the following condition: The DMA
uses the configured value for its address generation when the RDES2 value
is used to store the start of frame. Note that the DMA performs a write
operation with the RDES20 bits as 0 during the transfer of the start of frame
but the frame data is shifted as per the actual Buffer address pointer. The
DMA ignores RDES20 if the address pointer is to a buffer where the middle
or last part of the frame is stored. See Section 28.7.6.1.2for further details on
buffer address alignment.

Table 662. Receive descriptor fields 3 (RDES3)

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Bit

Symbol

Description

31:0

B2ADD

Buffer 2 Address Pointer (Next Descriptor Address)
These bits indicate the physical address of Buffer 2 when a descriptor ring
structure is used. If the Second Address Chained (RDES1[24]) bit is set, this
address contains the pointer to the physical memory where the Next
Descriptor is present. If RDES1[24] is set, the buffer (Next Descriptor)
address pointer must be bus width-aligned (RDES3[1:0] = 0. LSBs are
ignored internally.) However, when RDES1[24] is reset, there are no
limitations on the RDES3 value, except for the following condition: The DMA
uses the configured value for its buffer address generation when the RDES3
value is used to store the start of frame. The DMA ignores RDES3 [1:0] if the
address pointer is to a buffer where the middle or last part of the frame is
stored.

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The extended status written is as shown in Table 663. The extended status is written only
when there is status related to IPC or timestamp available. The availability of extended
status is indicated by bit-0 of RDES0. This status is available only when Advance
Timestamp or IPC Full Offload feature is selected.
Table 663. Receive descriptor fields 4 (RDES4)
Bit

Symbol

Description

2:0

-

Reserved

3

-

Reserved

4

-

Reserved

5

-

-

6

IPV4

IPv4 Packet Received
When set, this bit indicates that the received packet is an IPv4 packet.

7

IPV6

IPv6 Packet Received
When set, this bit indicates that the received packet is an IPv6 packet.

11:8

MT

Message Type These bits are encoded to give the type of the message received.
• 0000: No PTP message received
• 0001: SYNC (all clock types)
• 0010: Follow_Up (all clock types)
• 0011: Delay_Req (all clock types)
• 0100: Delay_Resp (all clock types)
• 0101: Pdelay_Req (in peer-to-peer transparent clock)
• 0110: Pdelay_Resp (in peer-to-peer transparent clock)
• 0111: Pdelay_Resp_Follow_Up (in peer-to-peer transparent clock)
• 1000: Announce
• 1001: Management
• 1010: Signaling
• 1011-1110: Reserved
• 1111: PTP packet with Reserved message type
These bits are used for the Advance Timestamp feature.

12

PTPTYPE

PTP Frame Type
When set, this bit that the PTP message is sent directly over Ethernet. When this bit is not set
and the message type is non-zero, it indicates that the PTP message is sent over UDP-IPv4 or
UDP-IPv6. The information on IPv4 or IPv6 can be obtained from bits 6 and 7.

13

PTPVERSION

PTP Version
When set, indicates that the received PTP message is having the IEEE 1588 version 2 format.
When reset, it has the version 1 format. This is valid only if the message type is non-zero.

31:14

-

Reserved.

RDES6 and RDES7 contain the snapshot of the time-stamp. The availability of the
snapshot of the time-stamp in RDES6 and RDES7 is indicated by bit-7 in the RDES0
descriptor. The contents of RDES6 and RDES7 are identified in Table 664 and Table 665.
Table 664. Receive descriptor fields 6 (RDES6)

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Bit

Symbol

Description

31:0

RTSL

Receive Frame Timestamp Low
This field is updated by DMA with the least significant 32 bits of the timestamp
captured for the corresponding receive frame. This field is updated by DMA
only for the last descriptor of the receive frame which is indicated by Last
Descriptor status bit (RDES0[8]).

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Table 665. Receive descriptor fields 7 (RDES7)

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Bit

Symbol

Description

31:0

RTSH

Receive Frame Timestamp High
This field is updated by DMA with the most significant 32 bits of the timestamp
captured for the corresponding receive frame. This field is updated by DMA
only for the last descriptor of the receive frame which is indicated by Last
Descriptor status bit (RDES0[8]).

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Rev. 2.4 — 22 August 2018

User manual

29.1 How to read this chapter
The LCD controller is available on parts LPC4370/LPC43S70, LPC4350/LPC43S50, and
LPC436x/LPC43S6x.

29.2 Basic configuration
The LCD controller is configured as follows:

• See Table 666 for clocking and power control.
• The LCD is reset by the LCD_RST (reset # 16).
• The LCD interrupt is connected to interrupt slot # 7 in the NVIC.
Table 666. LCD clocking and power control
LCD register interface clock

Base clock

Branch clock

Operating frequency

BASE_M4_CLK

CLK_M4_LCD

up to 204 MHz

29.3 Features
•
•
•
•

AHB bus master interface to access frame buffer.
Setup and control via a separate AHB slave interface.
Dual 16-deep programmable 64-bit wide FIFOs for buffering incoming display data.
Supports single and dual-panel monochrome Super Twisted Nematic (STN) displays
with 4 or 8-bit interfaces.

• Supports single and dual-panel color STN displays.
• Supports Thin Film Transistor (TFT) color displays.
• Programmable display resolution including, but not limited to: 320x200, 320x240,
640x200, 640x240, 640x480, 800x600, and 1024x768.

•
•
•
•
•
•
•
•
•
•
•
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Hardware cursor support for single-panel displays.
15 gray-level monochrome, 3375 color STN, and 32K color palettized TFT support.
1, 2, or 4 bits-per-pixel (bpp) palettized displays for monochrome STN.
1, 2, 4, or 8 bpp palettized color displays for color STN and TFT.
16 bpp true-color non-palettized, for color STN and TFT.
24 bpp true-color non-palettized, for color TFT.
Programmable timing for different display panels.
256 entry, 16-bit palette RAM, arranged as a 128x32-bit RAM.
Frame, line, and pixel clock signals.
AC bias signal for STN, data enable signal for TFT panels.
Supports little and big-endian, and Windows CE data formats.

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• LCD panel clock may be generated from the peripheral clock, or from a clock input
pin.

29.4 General description
The LCD controller performs translation of pixel-coded data into the required formats and
timings to drive a variety of single or dual panel monochrome and color LCDs.
Packets of pixel coded data are fed using the AHB interface, to two independent,
programmable, 32-bit wide, DMA FIFOs that act as input data flow buffers.
The buffered pixel coded data is then unpacked using a pixel serializer.
Depending on the LCD type and mode, the unpacked data can represent:

• An actual true display gray or color value.
• An address to a 256x16 bit wide palette RAM gray or color value.
In the case of STN displays, either a value obtained from the addressed palette location,
or the true value is passed to the gray scaling generators. The hardware-coded gray scale
algorithm logic sequences the activity of the addressed pixels over a programmed number
of frames to provide the effective display appearance.
For TFT displays, either an addressed palette value or true color value is passed directly
to the output display drivers, bypassing the gray scaling algorithmic logic.
In addition to data formatting, the LCD controller provides a set of programmable display
control signals, including:

•
•
•
•

LCD panel power enable
Pixel clock
Horizontal and vertical synchronization pulses
Display bias

The LCD controller generates individual interrupts for:

•
•
•
•

Upper or lower panel DMA FIFO underflow
Base address update signification
Vertical compare
Bus error

There is also a single combined interrupt that is asserted when any of the individual
interrupts become active.
Figure 91 shows a simplified block diagram of the LCD controller.

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AHB
slave
interface

Timing
controller
Panel clock
generator

AHB Bus

Upper
panel
DMA
FIFO

AHB
master
interface

LCD control
signals
LCD panel
clock
LCDCLKIN

Input
FIFO
control

Pixel
serializer

RAM
palette
(128x32)

Upper
panel
formatter

Upper
panel
output
FIFO

Upper
STN

Lower
panel
formatter

Lower
panel
output
FIFO

Lower
STN

Gray
scaler
Lower
panel
DMA
FIFO

Hardware
Cursor

FIFO underflow
AHB error

STN/TFT
data
select

Interrupt
generation

LCD panel
data

Interrupt

Fig 91. LCD controller block diagram

29.4.1 Programmable parameters
The following key display and controller parameters can be programmed:

•
•
•
•
•
•
•
•
•
•
•
•
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Horizontal front and back porch
Horizontal synchronization pulse width
Number of pixels per line
Vertical front and back porch
Vertical synchronization pulse width
Number of lines per panel
Number of pixel clocks per line
Hardware cursor control.
Signal polarity, active HIGH or LOW
AC panel bias
Panel clock frequency
Bits-per-pixel
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•
•
•
•
•

Display type: STN monochrome, STN color, or TFT
STN 4 or 8-bit interface mode
STN dual or single panel mode
Little-endian, big-endian, or Windows CE mode
Interrupt generation event

29.4.2 Hardware cursor support
The hardware cursor feature reduces software overhead associated with maintaining a
cursor image in the LCD frame buffer.
Without this feature, software needed to:

• Save an image of the area under the next cursor position.
• Update the area with the cursor image.
• Repair the last cursor position with a previously saved image.
In addition, the LCD driver had to check whether the graphics operation had overwritten
the cursor, and correct it. With a cursor size of 64x64 and 24-bit color, each cursor move
involved reading and writing approximately 75 kB of data.
The hardware cursor removes the requirement for this management by providing a
completely separate image buffer for the cursor, and superimposing the cursor image on
the LCD output stream at the current cursor (X,Y) coordinate.
To move the hardware cursor, the software driver supplies a new cursor coordinate. The
frame buffer requires no modification. This significantly reduces software overhead.
The cursor image is held in the LCD controller in an internal 256x32-bit buffer memory.

29.4.3 Types of LCD panels supported
The LCD controller supports the following types of LCD panel:

•
•
•
•
•

Active matrix TFT panels with up to 24-bit bus interface.
Single-panel monochrome STN panels (4-bit and 8-bit bus interface).
Dual-panel monochrome STN panels (4-bit and 8-bit bus interface per panel).
Single-panel color STN panels, 8-bit bus interface.
Dual-panel color STN panels, 8-bit bus interface per panel.

29.4.3.1 TFT panels
TFT panels support one or more of the following color modes:

•
•
•
•
•
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1 bpp, palettized, 2 colors selected from available colors.
2 bpp, palettized, 4 colors selected from available colors.
4 bpp, palettized, 16 colors selected from available colors.
8 bpp, palettized, 256 colors selected from available colors.
12 bpp, direct 4:4:4 RGB.

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• 16 bpp, direct 5:5:5 RGB, with 1 bpp not normally used. This pixel is still output, and
can be used as a brightness bit to connect to the Least Significant Bit (LSB) of RGB
components of a 6:6:6 TFT panel.

• 16 bpp, direct 5:6:5 RGB.
• 24 bpp, direct 8:8:8 RGB, providing over 16 million colors.
Each 16-bit palette entry is composed of 5 bpp (RGB), plus a common intensity bit. This
provides better memory utilization and performance compared with a full 6 bpp structure.
The total number of colors supported can be doubled from 32K to 64K if the intensity bit is
used and applied to all three color components simultaneously.
Alternatively, the 16 signals can be used to drive a 5:6:5 panel with the extra bit only
applied to the green channel.

29.4.3.2 Color STN panels
Color STN panels support one or more of the following color modes:

•
•
•
•
•

1 bpp, palettized, 2 colors selected from 3375.
2 bpp, palettized, 4 colors selected from 3375.
4 bpp, palettized, 16 colors selected from 3375.
8 bpp, palettized, 256 colors selected from 3375.
16 bpp, direct 4:4:4 RGB, with 4 bpp not being used.

29.4.3.3 Monochrome STN panels
Monochrome STN panels support one or more of the following modes:

• 1 bpp, palettized, 2 gray scales selected from 15.
• 2 bpp, palettized, 4 gray scales selected from 15.
• 4 bpp, palettized, 16 gray scales selected from 15.
More than 4 bpp for monochrome panels can be programmed, but using these modes has
no benefit because the maximum number of gray scales supported on the display is 15.

29.5 Pin description
The largest configuration for the LCD controller uses 31 pins. There are many variants
using as few as 10 pins for a monochrome STN panel. Pins are allocated in groups based
on the selected configuration. All LCD functions are shared with other chip functions. In
Table 667, only the LCD related portion of the pin name is shown.
Table 667. LCD controller pins
Pin function

Type

LCDPWR

Output LCD panel power enable.

Function

LCDCLK

Output LCD panel clock.

LCDENAB/LCDM Output STN AC bias drive or TFT data enable output.
(LCDAC)

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LCDFP

Output Frame pulse (STN). Vertical synchronization pulse (TFT)

LCDLE

Output Line end signal
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Table 667. LCD controller pins
Pin function

Type

Function

LCDLP

Output Line synchronization pulse (STN). Horizontal synchronization pulse
(TFT)

LCDVD[23:0]

Output LCD panel data. Bits used depend on the panel configuration.

GP_CLKIN

Input

General purpose CGU input clock. Can be used as the LCD external
clock LCDCLKIN.

29.5.1 Signal usage
The signals that are used for various display types are identified in the following sections.

29.5.1.1 Signals used for single panel STN displays
The signals used for single panel STN displays are shown in Table 668. UD refers to
upper panel data.
Table 668. Pins used for single panel STN displays
Pin name

4-bit Monochrome
(10 pins)

8-bit Monochrome
(14 pins)

(14 pins)

LCDPWR

Y

Y

Y

LCDDCLK

Y

Y

Y

LCDENAB/ LCDM

Y

Y

Y

LCDFP

Y

Y

Y

LCDLE

Y

Y

Y

LCDLP

Color

Y

Y

Y

LCDVD[3:0]

UD[3:0]

UD[3:0]

UD[3:0]

LCDVD[7:4]

-

UD[7:4]

UD[7:4]

LCDVD[23:8]

-

-

-

29.5.1.2 Signals used for dual panel STN displays
The signals used for dual panel STN displays are shown in Table 669. UD refers to upper
panel data, and LD refers to lower panel data.
Table 669. Pins used for dual panel STN displays
Pin name

4-bit Monochrome
(14 pins)

8-bit Monochrome
(22 pins)

(22 pins)

LCDPWR

Y

Y

Y

LCDDCLK

Y

Y

Y

LCDENAB/ LCDM

Y

Y

Y

LCDFP

Y

Y

Y

LCDLE

Y

Y

Y

LCDLP

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Y

Y

LCDVD[3:0]

UD[3:0]

UD[3:0]

UD[3:0]

LCDVD[7:4]

-

UD[7:4]

UD[7:4]

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Table 669. Pins used for dual panel STN displays
Pin name

4-bit Monochrome
(14 pins)

8-bit Monochrome
(22 pins)

LCDVD[11:8]

Color
(22 pins)

LD[3:0]

LD[3:0]

LD[3:0]

LCDVD[15:12]

-

LD[7:4]

LD[7:4]

LCDVD[23:16]

-

-

-

29.5.1.3 Signals used for TFT displays
The signals used for TFT displays are shown in Table 670.
Table 670. Pins used for TFT displays
Pin name

12-bit, 4:4:4
mode

16-bit, 5:6:5
mode

16-bit, 1:5:5:5
mode

(18 pins)

(22 pins)

(24 pins)

24-bit
(30 pins)

LCDPWR

Y

Y

Y

Y

LCDDCLK

Y

Y

Y

Y

LCDENAB/ LCDM

Y

Y

Y

Y

LCDFP

Y

Y

Y

Y

LCDLE

Y

Y

Y

Y

LCDLP

Y

Y

Y

Y

LCDVD[1:0]

-

-

-

RED[1:0]

LCDVD[2]

-

-

Intensity

RED[2]

LCDVD[3]

-

RED[0]

RED[0]

RED[3]

LCDVD[7:4]

RED[3:0]

RED[4:1]

RED[4:1]

RED[7:4]

LCDVD[9:8]

-

-

-

GREEN[1:0]

LCDVD[10]

-

GREEN[0]

Intensity

GREEN[2]

LCDVD[11]

-

GREEN[1]

GREEN[0]

GREEN[3]

LCDVD[15:12]

GREEN[3:0]

GREEN[5:2]

GREEN[4:1]

GREEN[7:4]

LCDVD[17:16]

-

-

-

BLUE[1:0]

LCDVD[18]

-

-

Intensity

BLUE[2]

LCDVD[19]
LCDVD[23:20]

-

BLUE[0]

BLUE[0]

BLUE[3]

BLUE[3:0]

BLUE[4:1]

BLUE[4:1]

BLUE[7:4]

29.6 Register description
Table 671 shows the registers associated with the LCD controller and a summary of their
functions. Following the table are details for each register.
Table 671. Register overview: LCD controller (base address: 0x4000 8000)
Name

Access Address offset

Description

Reset Reference
value
[1]

TIMH

R/W

0x000

Horizontal Timing Control register

0x0

Table 672

TIMV

R/W

0x004

Vertical Timing Control register

0x0

Table 673

POL

R/W

0x008

Clock and Signal Polarity Control register

0x0

Table 674

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Table 671. Register overview: LCD controller (base address: 0x4000 8000) …continued
Name

Access Address offset

Description

Reset Reference
value
[1]

LE

R/W

0x00C

Line End Control register

0x0

Table 675

UPBASE

R/W

0x010

Upper Panel Frame Base Address register

0x0

Table 676

LPBASE

R/W

0x014

Lower Panel Frame Base Address register

0x0

Table 677

CTRL

R/W

0x018

LCD Control register

0x0

Table 678

INTMSK

R/W

0x01C

Interrupt Mask register

0x0

Table 679

INTRAW

RO

0x020

Raw Interrupt Status register

0x0

Table 680

INTSTAT

RO

0x024

Masked Interrupt Status register

0x0

Table 681

INTCLR

WO

0x028

Interrupt Clear register

0x0

Table 682

UPCURR

RO

0x02C

Upper Panel Current Address Value register

0x0

Table 683

LPCURR

RO

0x030

Lower Panel Current Address Value register

0x0

Table 684

-

-

0x034 to 0x1FC

Reserved

-

-

PAL

R/W

0x200 to 0x3FC

256x16-bit Color Palette registers

0x0

Table 685

-

-

0x400 to 0x7FC

Reserved

-

-

CRSR_IMG

R/W

0x800 to 0xBFC

Cursor Image registers

0x0

Table 686

CRSR_CTRL

R/W

0xC00

Cursor Control register

0x0

Table 687

CRSR_CFG

R/W

0xC04

Cursor Configuration register

0x0

Table 688

CRSR_PAL0

R/W

0xC08

Cursor Palette register 0

0x0

Table 689

CRSR_PAL1

R/W

0xC0C

Cursor Palette register 1

0x0

Table 690

CRSR_XY

R/W

0xC10

Cursor XY Position register

0x0

Table 691

CRSR_CLIP

R/W

0xC14

Cursor Clip Position register

0x0

Table 692

CRSR_INTMSK

R/W

0xC20

Cursor Interrupt Mask register

0x0

Table 693

CRSR_INTCLR

WO

0xC24

Cursor Interrupt Clear register

0x0

Table 694

CRSR_INTRAW

RO

0xC28

Cursor Raw Interrupt Status register

0x0

Table 695

CRSR_INTSTAT

RO

0xC2C

Cursor Masked Interrupt Status register

0x0

Table 696

[1]

Reset Value reflects the data stored in used bits only. It does not include reserved bits content.

29.6.1 Horizontal Timing register
The TIMH register controls the Horizontal Synchronization pulse Width (HSW), the
Horizontal Front Porch (HFP) period, the Horizontal Back Porch (HBP) period, and the
Pixels-Per-Line (PPL).

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Table 672. Horizontal Timing register (TIMH, address 0x4000 8000) bit description
Bit

Symbol

Description

Reset
value

1:0

-

Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.

-

7:2

PPL

Pixels-per-line.

0x0

The PPL bit field specifies the number of pixels in each line or
row of the screen. PPL is a 6-bit value that represents between
16 and 1024 pixels per line. PPL counts the number of pixel
clocks that occur before the HFP is applied.
Program the value required divided by 16, minus 1. Actual
pixels-per-line = 16 * (PPL + 1). For example, to obtain 320
pixels per line, program PPL as (320/16) -1 = 19.
15:8

HSW

Horizontal synchronization pulse width.

0x0

The 8-bit HSW field specifies the pulse width of the line clock in
passive mode, or the horizontal synchronization pulse in active
mode. Program with desired value minus 1.
23:16

HFP

0x0

Horizontal front porch.
The 8-bit HFP field sets the number of pixel clock intervals at the
end of each line or row of pixels, before the LCD line clock is
pulsed. When a complete line of pixels is transmitted to the LCD
driver, the value in HFP counts the number of pixel clocks to wait
before asserting the line clock. HFP can generate a period of
1-256 pixel clock cycles. Program with desired value minus 1.

31:24

HBP

Horizontal back porch.

0x0

The 8-bit HBP field is used to specify the number of pixel clock
periods inserted at the beginning of each line or row of pixels.
After the line clock for the previous line has been deasserted, the
value in HBP counts the number of pixel clocks to wait before
starting the next display line. HBP can generate a delay of 1-256
pixel clock cycles. Program with desired value minus 1.

29.6.1.1 Horizontal timing restrictions
DMA requests new data at the start of a horizontal display line. Some time must be
allowed for the DMA transfer and for data to propagate down the FIFO path in the LCD
interface. The data path latency forces some restrictions on the usable minimum values
for horizontal porch width in STN mode. The minimum values are HSW = 2 and HBP = 2.
Single panel mode:

•
•
•
•

HSW = 3 pixel clock cycles
HBP = 5 pixel clock cycles
HFP = 5 pixel clock cycles
Panel Clock Divisor (PCD) = 1 (LCDCLK / 3)

Dual panel mode:

• HSW = 3 pixel clock cycles
• HBP = 5 pixel clock cycles
• HFP = 5 pixel clock cycles
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• PCD = 5 (LCDCLK / 7)
If enough time is given at the start of the line, for example, setting HSW = 6, HBP = 10,
data does not corrupt for PCD = 4, the minimum value.

29.6.2 Vertical Timing register
The TIMV register controls the Vertical Synchronization pulse Width (VSW), the Vertical
Front Porch (VFP) period, the Vertical Back Porch (VBP) period, and the Lines-Per-Panel
(LPP).
Table 673. Vertical Timing register (TIMV, address 0x4000 8004) bit description
Bit

Symbol

Description

Reset
value

9:0

LPP

Lines per panel.

0x0

This is the number of active lines per screen. The LPP field specifies
the total number of lines or rows on the LCD panel being controlled.
LPP is a 10-bit value allowing between 1 and 1024 lines. Program
the register with the number of lines per LCD panel, minus 1. For
dual panel displays, program the register with the number of lines on
each of the upper and lower panels.
15:10

VSW

Vertical synchronization pulse width.

0x0

This is the number of horizontal synchronization lines. The 6-bit VSW
field specifies the pulse width of the vertical synchronization pulse.
Program the register with the number of lines required, minus one.
The number of horizontal synchronization lines must be small (for
example, program to zero) for passive STN LCDs. The higher the
value the worse the contrast on STN LCDs.
23:16

VFP

Vertical front porch.

0x0

This is the number of inactive lines at the end of a frame, before the
vertical synchronization period. The 8-bit VFP field specifies the
number of line clocks to insert at the end of each frame. When a
complete frame of pixels is transmitted to the LCD display, the value
in VFP is used to count the number of line clock periods to wait.
After the count has elapsed, the vertical synchronization signal,
LCDFP, is asserted in active mode, or extra line clocks are inserted
as specified by the VSW bit-field in passive mode. VFP generates
0–255 line clock cycles. Program to zero on passive displays for
improved contrast.
31:24

VBP

Vertical back porch.

0x0

This is the number of inactive lines at the start of a frame, after the
vertical synchronization period. The 8-bit VBP field specifies the
number of line clocks inserted at the beginning of each frame. The
VBP count starts immediately after the vertical synchronization signal
for the previous frame has been negated for active mode, or the extra
line clocks have been inserted as specified by the VSW bit field in
passive mode. After this has occurred, the count value in VBP sets
the number of line clock periods inserted before the next frame. VBP
generates 0–255 extra line clock cycles. Program to zero on passive
displays for improved contrast.

29.6.3 Clock and Signal Polarity register
The POL register controls various details of clock timing and signal polarity.
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Table 674. Clock and Signal Polarity register (POL, address 0x4000 8008) bit description
Bit

Symbol

Description

Reset
value

4:0

PCD_LO

Lower five bits of panel clock divisor.

0x0

The ten-bit PCD field, comprising PCD_HI (bits 31:27 of this
register) and PCD_LO, is used to derive the LCD panel clock
frequency LCDDCLK from the input clock, LCDDCLK =
LCDCLK/(PCD+2).
For monochrome STN displays with a 4 or 8-bit interface, the
panel clock is a factor of four and eight down from the actual
individual pixel clock rate. For color STN displays, 22/3 pixels
are output per LCDDCLK cycle, so the panel clock is 0.375 times
the pixel rate.
For TFT displays, the pixel clock divider can be bypassed by
setting the BCD bit in this register.
Note: data path latency forces some restrictions on the usable
minimum values for the panel clock divider in STN modes:
Single panel color mode, PCD = 1 (LCDDCLK = LCDCLK/3).
Dual panel color mode, PCD = 4 (LCDDCLK = LCDCLK/6).
Single panel monochrome 4-bit interface mode, PCD =
2(LCDDCLK = LCDCLK/4).
Dual panel monochrome 4-bit interface mode and single panel
monochrome 8-bit interface mode, PCD = 6(LCDDCLK =
LCDCLK/8).
Dual panel monochrome 8-bit interface mode, PCD =
14(LCDDCLK = LCDCLK/16).
5

CLKSEL

0x0

Clock Select.
This bit controls the selection of the source for LCDCLK.
0 = the clock source for the LCD block is CCLK.
1 = the clock source for the LCD block is LCDCLKIN (external
clock input for the LVD).

10:6

ACB

AC bias pin frequency.

0x0

The AC bias pin frequency is only applicable to STN displays.
These require the pixel voltage polarity to periodically reverse to
prevent damage caused by DC charge accumulation. Program
this field with the required value minus one to apply the number
of line clocks between each toggle of the AC bias pin,
LCDENAB. This field has no effect if the LCD is operating in TFT
mode, when the LCDENAB pin is used as a data enable signal.
11

IVS

Invert vertical synchronization.

0x0

The IVS bit inverts the polarity of the LCDFP signal.
0 = LCDFP pin is active HIGH and inactive LOW.
1 = LCDFP pin is active LOW and inactive HIGH.
12

IHS

Invert horizontal synchronization.

0x0

The IHS bit inverts the polarity of the LCDLP signal.
0 = LCDLP pin is active HIGH and inactive LOW.
1 = LCDLP pin is active LOW and inactive HIGH.

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Table 674. Clock and Signal Polarity register (POL, address 0x4000 8008) bit description
Bit

Symbol

Description

Reset
value

13

IPC

Invert panel clock.

0x0

The IPC bit selects the edge of the panel clock on which pixel
data is driven out onto the LCD data lines.
0 = Data is driven on the LCD data lines on the rising edge of
LCDDCLK.
1 = Data is driven on the LCD data lines on the falling edge of
LCDDCLK.
14

IOE

Invert output enable.

0x0

This bit selects the active polarity of the output enable signal in
TFT mode. In this mode, the LCDENAB pin is used as an enable
that indicates to the LCD panel when valid display data is
available. In active display mode, data is driven onto the LCD
data lines at the programmed edge of LCDDCLK when
LCDENAB is in its active state.
0 = LCDENAB output pin is active HIGH in TFT mode.
1 = LCDENAB output pin is active LOW in TFT mode.
15

-

Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.

-

25:16

CPL

Clocks per line.

0x0

This field specifies the number of actual LCDDCLK clocks to the
LCD panel on each line. This is the number of PPL divided by
either 1 (for TFT), 4 or 8 (for monochrome passive), 2 2/3 (for
color passive), minus one. This must be correctly programmed in
addition to the PPL bit in the TIMH register for the LCD display to
work correctly.
26

BCD

Bypass pixel clock divider.

0x0

Setting this to 1 bypasses the pixel clock divider logic. This is
mainly used for TFT displays.
31:27

PCD_HI

Upper five bits of panel clock divisor.

0x0

See description for PCD_LO, in bits [4:0] of this register.

29.6.4 Line End Control register
The LE register controls the enabling of line-end signal LCDLE. When enabled, a positive
pulse, four LCDCLK periods wide, is output on LCDLE after a programmable delay, LED,
from the last pixel of each display line. If the line-end signal is disabled it is held
permanently LOW.

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Table 675. Line End Control register (LE, address 0x4000 800C) bit description
Bit

Symbol

Description

Reset
value

6:0

LED

Line-end delay.

0x0

Controls Line-end signal delay from the rising-edge of the last
panel clock, LCDDCLK. Program with number of LCDCLK clock
periods minus 1.
15:7

-

Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.

-

16

LEE

LCD Line end enable.

0x0

0 = LCDLE disabled (held LOW).
1 = LCDLE signal active.
31:17

-

Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.

-

29.6.5 Upper Panel Frame Base Address register
The UPBASE register is the color LCD upper panel DMA base address register, and is
used to program the base address of the frame buffer for the upper panel. LCDUPBase
(and LCDLPBase for dual panels) must be initialized before enabling the LCD controller.
The base address must be doubleword aligned.
Optionally, the value may be changed mid-frame to create double-buffered video displays.
These registers are copied to the corresponding current registers at each LCD vertical
synchronization. This event causes the LNBU bit and an optional interrupt to be
generated. The interrupt can be used to reprogram the base address when generating
double-buffered video.
Table 676. Upper Panel Frame Base register (UPBASE, address 0x4000 8010) bit
description
Bit

Symbol

Description

Reset
value

2:0

-

Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.

-

31:3

LCDUPBASE

LCD upper panel base address.

0x0

This is the start address of the upper panel frame data in
memory and is doubleword aligned.

29.6.6 Lower Panel Frame Base Address register
The LPBASE register is the color LCD lower panel DMA base address register, and is
used to program the base address of the frame buffer for the lower panel. LCDLPBase
must be initialized before enabling the LCD controller. The base address must be
doubleword aligned.
Optionally, the value may be changed mid-frame to create double-buffered video displays.
These registers are copied to the corresponding current registers at each LCD vertical
synchronization. This event causes the LNBU bit and an optional interrupt to be
generated. The interrupt can be used to reprogram the base address when generating
double-buffered video.

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Table 677. Lower Panel Frame Base register (LPBASE, address 0x4000 8014) bit
description
Bit

Symbol

Description

Reset
value

2:0

-

Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.

-

31:3

LCDLPBASE

LCD lower panel base address.

0x0

This is the start address of the lower panel frame data in memory
and is doubleword aligned.

29.6.7 LCD Control register
The CTRL register controls the LCD operating mode and the panel pixel parameters.
Table 678. LCD Control register (CTRL, address 0x4000 8018) bit description
Bit

Symbol

Description

Reset
value

0

LCDEN

LCD enable control bit.

0x0

0 = LCD disabled. Signals LCDLP, LCDDCLK, LCDFP,
LCDENAB, and LCDLE are low.
1 = LCD enabled. Signals LCDLP, LCDDCLK, LCDFP,
LCDENAB, and LCDLE are high.
See LCD power-up and power-down sequence for details on
LCD power sequencing.
3:1

LCDBPP

0x0

LCD bits per pixel:
Selects the number of bits per LCD pixel:
000 = 1 bpp.
001 = 2 bpp.
010 = 4 bpp.
011 = 8 bpp.
100 = 16 bpp.
101 = 24 bpp (TFT panel only).
110 = 16 bpp, 5:6:5 mode.
111 = 12 bpp, 4:4:4 mode.

4

LCDBW

0x0

STN LCD monochrome/color selection.
0 = STN LCD is color.
1 = STN LCD is monochrome.
This bit has no meaning in TFT mode.

5

LCDTFT

LCD panel TFT type selection.

0x0

0 = LCD is an STN display. Use gray scaler.
1 = LCD is a TFT display. Do not use gray scaler.
6

LCDMONO8

Monochrome LCD interface width.

0x0

This bit controls whether a monochrome STN LCD uses a 4 or
8-bit parallel interface. It has no meaning in other modes and
must be programmed to zero.
0 = monochrome LCD uses a 4-bit interface.
1 = monochrome LCD uses a 8-bit interface.

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Table 678. LCD Control register (CTRL, address 0x4000 8018) bit description …continued
Bit

Symbol

Description

Reset
value

7

LCDDUAL

Single or Dual LCD panel selection.

0x0

STN LCD interface is:
0 = single-panel.
1 = dual-panel.
8

BGR

Color format selection.

0x0

0 = RGB: normal output.
1 = BGR: red and blue swapped.
9

BEBO

0x0

Big-endian Byte Order.
Controls byte ordering in memory:
0 = little-endian byte order.
1 = big-endian byte order.

10

BEPO

0x0

Big-Endian Pixel Ordering.
Controls pixel ordering within a byte:
0 = little-endian ordering within a byte.
1 = big-endian pixel ordering within a byte.
The BEPO bit selects between little and big-endian pixel packing
for 1, 2, and 4 bpp display modes, it has no effect on 8 or 16 bpp
pixel formats.
See Pixel serializer for more information on the data format.

11

LCDPWR

0x0

LCD power enable.
0 = power not gated through to LCD panel and LCDV[23:0]
signals disabled, (held LOW).
1 = power gated through to LCD panel and LCDV[23:0] signals
enabled, (active).
See LCD power-up and power-down sequence for details on
LCD power sequencing.

13:12

LCDVCOMP

0x0

LCD Vertical Compare Interrupt.
Generate VComp interrupt at:
00 = start of vertical synchronization.
01 = start of back porch.
10 = start of active video.
11 = start of front porch.

15:14

-

Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.

16

WATERMARK LCD DMA FIFO watermark level.

0x0

Controls when DMA requests are generated:
0 = An LCD DMA request is generated when either of the DMA
FIFOs have four or more empty locations.
1 = An LCD DMA request is generated when either of the DMA
FIFOs have eight or more empty locations.
31:17

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Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.

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29.6.8 Interrupt Mask register
The INTMSK register controls whether various LCD interrupts occur.Setting bits in this
register enables the corresponding raw interrupt INTRAW status bit values to be passed
to the INTSTAT register for processing as interrupts.
Table 679. Interrupt Mask register (INTMSK, address 0x4000 801C) bit description
Bit

Symbol

Description

Reset
value

0

-

Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.

-

1

FUFIM

FIFO underflow interrupt enable.

0x0

0: The FIFO underflow interrupt is disabled.
1: Interrupt will be generated when the FIFO underflows.
2

LNBUIM

LCD next base address update interrupt enable.

0x0

0: The base address update interrupt is disabled.
1: Interrupt will be generated when the LCD base address
registers have been updated from the next address registers.
3

VCOMPIM

Vertical compare interrupt enable.

0x0

0: The vertical compare time interrupt is disabled.
1: Interrupt will be generated when the vertical compare time (as
defined by LcdVComp field in the CTRL register) is reached.
4

BERIM

AHB master error interrupt enable.

0x0

0: The AHB Master error interrupt is disabled.
1: Interrupt will be generated when an AHB Master error occurs.
31:5

-

Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.

-

29.6.9 Raw Interrupt Status register
The INTRAW register contains status flags for various LCD controller events. These flags
can generate an interrupts if enabled by mask bits in the INTMSK register.
Table 680. Raw Interrupt Status register (INTRAW, address 0x4000 8020) bit description
Bit

Symbol

Description

Reset
value

0

-

Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.

-

1

FUFRIS

FIFO underflow raw interrupt status.
Set when either the upper or lower DMA FIFOs have been read
accessed when empty causing an underflow condition to occur.
Generates an interrupt if the FUFIM bit in the INTMSK register is
set.

2

LNBURIS

LCD next address base update raw interrupt status.

0x0

Mode dependent. Set when the current base address registers
have been successfully updated by the next address registers.
Signifies that a new next address can be loaded if double
buffering is in use.
Generates an interrupt if the LNBUIM bit in the INTMSK register
is set.
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Table 680. Raw Interrupt Status register (INTRAW, address 0x4000 8020) bit description
Bit

Symbol

Description

Reset
value

3

VCOMPRIS

Vertical compare raw interrupt status.

0x0

Set when one of the four vertical regions is reached, as selected
by the LcdVComp bits in the CTRL register.
Generates an interrupt if the VCompIM bit in the INTMSK
register is set.
4

BERRAW

AHB master bus error raw interrupt status.

0x0

Set when the AHB master interface receives a bus error
response from a slave.
Generates an interrupt if the BERIM bit in the INTMSK register is
set.
31:5

-

Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.

-

29.6.10 Masked Interrupt Status register
The INTSTAT register is Read-Only, and contains a bit-by-bit logical AND of the INTRAW
register and the INTMASK register. A logical OR of all interrupts is provided to the system
interrupt controller.
Table 681. Masked Interrupt Status register (INTSTAT, address 0x4000 8024) bit description
Bit

Symbol

Description

Reset
value

0

-

Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.

-

1

FUFMIS

FIFO underflow masked interrupt status.

0x0

Set when the both the FUFRIS bit in the INTRAW register and
the FUFIM bit in the INTMSK register are set.
2

LNBUMIS

LCD next address base update masked interrupt status.

0x0

Set when the both the LNBURIS bit in the INTRAW register and
the LNBUIM bit in the INTMSK register are set.
3

VCOMPMIS

Vertical compare masked interrupt status.

0x0

Set when the both the VCompRIS bit in the INTRAW register
and the VCompIM bit in the INTMSK register are set.
4

BERMIS

0x0

AHB master bus error masked interrupt status.
Set when the both the BERRAW bit in the INTRAW register and
the BERIM bit in the INTMSK register are set.

31:5

-

Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.

-

29.6.11 Interrupt Clear register
The INTCLR register is Write-Only. Writing a logic 1 to the relevant bit clears the
corresponding interrupt.

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Table 682. Interrupt Clear register (INTCLR, address 0x4000 8028) bit description
Bit

Symbol

Description

Reset
value

0

-

Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.

-

1

FUFIC

FIFO underflow interrupt clear.

0x0

Writing a 1 to this bit clears the FIFO underflow interrupt.
2

LNBUIC

LCD next address base update interrupt clear.

0x0

Writing a 1 to this bit clears the LCD next address base update
interrupt.
3

VCOMPIC

Vertical compare interrupt clear.

4

BERIC

AHB master error interrupt clear.

0x0

Writing a 1 to this bit clears the vertical compare interrupt.
0x0

Writing a 1 to this bit clears the AHB master error interrupt.
31:5

-

Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.

-

29.6.12 Upper Panel Current Address register
The UPCURR register is Read-Only, and contains an approximate value of the upper
panel data DMA address when read.
Note: This register can change at any time and therefore can only be used as a rough
indication of display position.
Table 683. Upper Panel Current Address register (UPCURR, address 0x4000 802C) bit
description
Bit

Symbol

Description

31:0

LCDUPCURR LCD Upper Panel Current Address.

Reset
value
0x0

Contains the current LCD upper panel data DMA address.

29.6.13 Lower Panel Current Address register
The LPCURR register is Read-Only, and contains an approximate value of the lower
panel data DMA address when read.
Note: This register can change at any time and therefore can only be used as a rough
indication of display position.
Table 684. Lower Panel Current Address register (LPCURR, address 0x4000 8030) bit
description
Bit

Symbol

Description

Reset
value

31:0

LCDLPCURR

LCD Lower Panel Current Address.

0x0

Contains the current LCD lower panel data DMA address.

29.6.14 Color Palette registers
The PAL register contain 256 palette entries organized as 128 locations of two entries per
word.
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Each word location contains two palette entries. This means that 128 word locations are
used for the palette. When configured for little-endian byte ordering, bits [15:0] are the
lower numbered palette entry and [31:16] are the higher numbered palette entry. When
configured for big-endian byte ordering this is reversed, because bits [31:16] are the low
numbered palette entry and [15:0] are the high numbered entry.
Note: Only TFT displays use all of the palette entry bits.
Table 685. Color Palette registers (PAL, address 0x4000 8200 (PAL0) to 0x4000 83FC
(PAL255)) bit description
Bit

Symbol

Description

Reset
value

4:0

R04_0

Red palette data.

0x0

For STN displays, only the four MSBs, bits [4:1], are used. For
monochrome displays only the red palette data is used. All of the
palette registers have the same bit fields.
9:5

G04_0

Green palette data.

0x0

14:10

B04_0

Blue palette data.

0x0

15

I0

Intensity / unused bit.

0x0

Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT
display, doubling the number of colors to 64K, where each color
has two different intensities.
20:16

R14_0

Red palette data.

0x0

For STN displays, only the four MSBs, bits [4:1], are used. For
monochrome displays only the red palette data is used. All of the
palette registers have the same bit fields.
25:21

G14_0

Green palette data.

0x0

30:26

B14_0

Blue palette data.

0x0

31

I1

Intensity / unused bit.

0x0

Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT
display, doubling the number of colors to 64K, where each color
has two different intensities.

29.6.15 Cursor Image registers
The CRSR_IMG register area contains 256-word wide values which are used to define
the image or images overlaid on the display by the hardware cursor mechanism. The
image must always be stored in LBBP mode (little-endian byte, big-endian pixel) mode, as
described in Section 29.7.5.6. Two bits are used to encode color and transparency for
each pixel in the cursor.
Depending on the state of bit 0 in the CRSR_CFG register (see Cursor Configuration
register description), the cursor image RAM contains either four 32x32 cursor images, or
a single 64x64 cursor image.
The two colors defined for the cursor are mapped onto values from the CRSR_PAL0 and
CRSR_PAL0 registers (see Cursor Palette register descriptions).

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Table 686. Cursor Image registers (CRSR_IMG, address 0x4000 8800 (CRSR_IMG0) to
0x4000 8BFC (CRSR_IMG1)) bit description
Bit

Symbol

Description

Reset
value

31:0

CRSR_IMG

Cursor Image data.

0x0

The 256 words of the cursor image registers define the
appearance of either one 64x64 cursor or 4 32x32 cursors.

29.6.16 Cursor Control register
The CRSR_CTRL register provides access to frequently used cursor functions, such as
the display on/off control for the cursor, and the cursor number.
If a 32x32 cursor is selected, one of four 32x32 cursors can be enabled. The images each
occupy one quarter of the image memory, with Cursor0 from location 0, followed by
Cursor1 from address 0x100, Cursor2 from 0x200 and Cursor3 from 0x300. If a 64x64
cursor is selected only one cursor fits in the image buffer, and no selection is possible.
Similar frame synchronization rules apply to the cursor number as apply to the cursor
coordinates. If CrsrFramesync is 1, the displayed cursor image is only changed during the
vertical frame blanking period. If CrsrFrameSync is 0, the cursor image index is changed
immediately, even if the cursor is currently being scanned.
Table 687. Cursor Control register (CRSR_CTRL, address 0x4000 8C00) bit description
Bit

Symbol

Description

Reset
value

0

CrsrOn

Cursor enable.

0x0

0 = Cursor is not displayed.
1 = Cursor is displayed.
3:1

-

Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.

0x0

5:4

CRSRNUM1_0

Cursor image number.

0x0

If the selected cursor size is 6x64, this field has no effect. If
the selected cursor size is 32x32:
00 = Cursor0.
01 = Cursor1.
10 = Cursor2.
11 = Cursor3.
31:6

-

Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.

0x0

29.6.17 Cursor Configuration register
The CRSR_CFG register provides overall configuration information for the hardware
cursor.

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Table 688. Cursor Configuration register (CRSR_CFG, address 0x4000 8C04) bit description
Bit

Symbol

Description

Reset
value

0

CrsrSize

Cursor size selection.

0x0

0 = 32x32 pixel cursor. Allows for 4 defined cursors.
1 = 64x64 pixel cursor.
1

FRAMESYNC Cursor frame synchronization type.

0x0

0 = Cursor coordinates are asynchronous.
1 = Cursor coordinates are synchronized to the frame
synchronization pulse.
31:2

-

Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.

-

29.6.18 Cursor Palette register 0
The cursor palette registers provide color palette information for the visible colors of the
cursor. Color0 maps through CRSR_PAL0.
The register provides 24-bit RGB values that are displayed according to the abilities of the
LCD panel in the same way as the frame-buffers palette output is displayed.
In monochrome STN mode, only the upper 4 bits of the Red field are used. In STN color
mode, the upper 4 bits of the Red, Blue, and Green fields are used. In 24 bits per pixel
mode, all 24 bits of the palette registers are significant.
Table 689. Cursor Palette register 0 (CRSR_PAL0, address 0x4000 8C08) bit description
Bit

Symbol

Description

Reset
value

7:0

RED

Red color component

0x0

15:8

GREEN

Green color component

0x0

23:16

BLUE

Blue color component.

0x0

31:24

-

Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.

-

29.6.19 Cursor Palette register 1
The cursor palette registers provide color palette information for the visible colors of the
cursor. Color1 maps through CRSR_PAL1.
The register provides 24-bit RGB values that are displayed according to the abilities of the
LCD panel in the same way as the frame-buffers palette output is displayed.
In monochrome STN mode, only the upper 4 bits of the Red field are used. In STN color
mode, the upper 4 bits of the Red, Blue, and Green fields are used. In 24 bits per pixel
mode, all 24 bits of the palette registers are significant.

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Table 690. Cursor Palette register 1 (CRSR_PAL1, address 0x4000 8C0C) bit description
Bit

Symbol

Description

Reset
value

7:0

RED

Red color component

0x0

15:8

GREEN

Green color component

0x0

23:16

BLUE

Blue color component.

0x0

31:24

-

Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.

-

29.6.20 Cursor XY Position register
The CRSR_XY register defines the distance of the top-left edge of the cursor from the
top-left side of the cursor overlay. Refer to the section on Cursor Clipping for more details.
If the FrameSync bit in the CRSR_CFG register is 0, the cursor position changes
immediately, even if the cursor is currently being scanned. If Framesync is 1, the cursor
position is only changed during the next vertical frame blanking period.
Table 691. Cursor XY Position register (CRSR_XY, address 0x4000 8C10) bit description
Bit

Symbol

Description

Reset
value

9:0

CRSRX

X ordinate of the cursor origin measured in pixels.

0x0

When 0, the left edge of the cursor is at the left of the display.
15:10

-

Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.

-

25:16

CRSRY

Y ordinate of the cursor origin measured in pixels.

0x0

31:26

-

When 0, the top edge of the cursor is at the top of the display.
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.

-

29.6.21 Cursor Clip Position register
The CRSR_CLIP register defines the distance from the top-left edge of the cursor image,
to the first displayed pixel in the cursor image.
Different synchronization rules apply to the Cursor Clip registers than apply to the cursor
coordinates. If the FrameSync bit in the CRSR_CFG register is 0, the cursor clip point is
changed immediately, even if the cursor is currently being scanned.
If the Framesync bit in the CRSR_CFG register is 1, the displayed cursor image is only
changed during the vertical frame blanking period, providing that the cursor position has
been updated since the Clip register was programmed. When programming, the Clip
register must be written before the Position register (ClcdCrsrXY) to ensure that in a given
frame, the clip and position information is coherent.

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Table 692. Cursor Clip Position register (CRSR_CLIP, address 0x4000 8C14) bit description
Bit

Symbol

Description

Reset
value

5:0

CRSRCLIPX

Cursor clip position for X direction.

0x0

Distance from the left edge of the cursor image to the first
displayed pixel in the cursor.
When 0, the first pixel of the cursor line is displayed.
7:6

-

Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.

-

13:8

CRSRCLIPY

Cursor clip position for Y direction.

0x0

Distance from the top of the cursor image to the first displayed
pixel in the cursor.
When 0, the first displayed pixel is from the top line of the cursor
image.
31:14

-

Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.

-

29.6.22 Cursor Interrupt Mask register
The CRSR_INTMSK register is used to enable or disable the cursor from interrupting the
processor.
Table 693. Cursor Interrupt Mask register (CRSR_INTMSK, address 0x4000 8C20) bit
description
Bit

Symbol

0

CRSRIM

Description

Reset
value

Cursor interrupt mask.

0x0

When clear, the cursor never interrupts the processor.
When set, the cursor interrupts the processor immediately after
reading of the last word of cursor image.
31:1

-

Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.

-

29.6.23 Cursor Interrupt Clear register
The CRSR_INTCLR register is used by software to clear the cursor interrupt status and
the cursor interrupt signal to the processor.
Table 694. Cursor Interrupt Clear register (CRSR_INTCLR, address 0x4000 8C24) bit
description
Bit

Symbol

Description

Reset
value

0

CRSRIC

Cursor interrupt clear.

0x0

Writing a 0 to this bit has no effect.
Writing a 1 to this bit causes the cursor interrupt status to be
cleared.
31:1

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Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.

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29.6.24 Cursor Raw Interrupt Status register
The CRSR_INTRAW register is set to indicate a cursor interrupt. When enabled via the
CrsrIM bit in the CRSR_INTMSK register, provides the interrupt to the system interrupt
controller.
Table 695. Cursor Raw Interrupt Status register (CRSR_INTRAW, address 0x4000 8C28) bit
description
Bit

Symbol

Description

Reset
value

0

CRSRRIS

Cursor raw interrupt status.

0x0

The cursor interrupt status is set immediately after the last data
is read from the cursor image for the current frame.
This bit is cleared by writing to the CrsrIC bit in the
CRSR_INTCLR register.
31:1

-

Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.

-

29.6.25 Cursor Masked Interrupt Status register
The CRSR_INTSTAT register is set to indicate a cursor interrupt providing that the
interrupt is not masked in the CRSR_INTMSK register.
Table 696. Cursor Masked Interrupt Status register (CRSR_INTSTAT, address 0x4000 8C2C)
bit description
Bit

Symbol

Description

Reset
value

0

CRSRMIS

Cursor masked interrupt status.

0x0

The cursor interrupt status is set immediately after the last data
read from the cursor image for the current frame, providing that
the corresponding bit in the CRSR_INTMSK register is set.
The bit remains clear if the CRSR_INTMSK register is clear.
This bit is cleared by writing to the CRSR_INTCLR register.
31:1

-

Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.

-

29.7 Functional description
29.7.1 AHB interfaces
The LCD controller includes two separate AHB interfaces. The first, an AHB slave
interface, is used primarily by the CPU to access control and data registers within the LCD
controller. The second, an AHB master interface, is used by the LCD controller for DMA
access to display data stored in memory elsewhere in the system. The LCD DMA
controller can access any SRAM on AHB and the external memory.

29.7.1.1 AMBA AHB slave interface
The AHB slave interface connects the LCD controller to the AHB bus and provides CPU
accesses to the registers and palette RAM.

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29.7.1.2 AMBA AHB master interface
The AHB master interface transfers display data from a selected slave (memory) to the
LCD controller DMA FIFOs. It can be configured to obtain data from any on-chip SRAM on
AHB, various types of off-chip static memory, or off-chip SDRAM.
In dual panel mode, the DMA FIFOs are filled up in an alternating fashion via a single
DMA request. In single panel mode, the DMA FIFOs are filled up in a sequential fashion
from a single DMA request.
The inherent AHB master interface state machine performs the following functions:

• Loads the upper panel base address into the AHB address incrementer on
recognition of a new frame.

• Monitors both the upper and lower DMA FIFO levels and asserts a DMA request to
request display data from memory, filling them to above the programmed watermark.
the DMA request is reasserted when there are at least four locations available in
either FIFO (dual panel mode).

• Checks for 1 kB boundaries during fixed-length bursts, appropriately adjusting the
address in such occurrences.

• Generates the address sequences for fixed-length and undefined bursts.
• Controls the handshaking between the memory and DMA FIFOs. It inserts busy
cycles if the FIFOs have not completed their synchronization and updating sequence.

• Fills up the DMA FIFOs, in dual panel mode, in an alternating fashion from a single
DMA request.

• Asserts the a bus error interrupt if an error occurs during an active burst.
• Responds to retry commands by restarting the failed access. This introduces some
busy cycles while it re-synchronizes.

29.7.2 Dual DMA FIFOs and associated control logic
The pixel data accessed from memory is buffered by two DMA FIFOs that can be
independently controlled to cover single and dual-panel LCD types. Each FIFO is 16
words deep by 64 bits wide and can be cascaded to form an effective 32-Dword deep
FIFO in single panel mode.
Synchronization logic transfers the pixel data from the AHB clock domain to the LCD
controller clock domain. The water level marks in each FIFO are set such that each FIFO
requests data when at least four locations become available.
An interrupt signal is asserted if an attempt is made to read either of the two DMA FIFOs
when they are empty (an underflow condition has occurred).

29.7.3 Pixel serializer
This block reads the 32-bit wide LCD data from the output port of the DMA FIFO and
extracts 24, 16, 8, 4, 2, or 1 bpp data, depending on the current mode of operation. The
LCD controller supports big-endian, little-endian, and Windows CE data formats.
Depending on the mode of operation, the extracted data can be used to point to a color or
gray scale value in the palette RAM or can actually be a true color value that can be
directly applied to an LCD panel input.
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Table 697 through Table 699 show the structure of the data in each DMA FIFO word
corresponding to the endianness and bpp combinations. For each of the three supported
data formats, the required data for each panel display pixel must be extracted from the
data word.
Table 697. FIFO bits for Little-endian Byte, Little-endian Pixel order

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FIFO bit

1 bpp

31

p31

30

p30

29

p29

28

p28

27

p27

26

p26

25

p25

24

p24

23

p23

22

p22

21

p21

20

p20

19

p19

18

p18

17

p17

16

p16

15

p15

14

p14

13

p13

12

p12

11

p11

10

p10

9

p9

8

p8

7

p7

6

p6

5

p5

4

p4

3

p3

2

p2

1

p1

0

p0

2 bpp

4 bpp

8 bpp

16 bpp

24 bpp

p15
p7
p14
p3
p13
p6
p12
p1
p11
p5
p10
p2
p9
p4
p8
p7
p3
p6
p1

p0

p5
p2
p4
p0
p3
p1
p2
p0
p1
p0
p0

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Table 698. FIFO bits for Big-endian Byte, Big-endian Pixel order

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FIFO bit

1 bpp

31

p0

30

p1

29

p2

28

p3

27

p4

26

p5

25

p6

24

p7

23

p8

22

p9

21

p10

20

p11

19

p12

18

p13

17

p14

16

p15

15

p16

14

p17

13

p18

12

p19

11

p20

10

p21

9

p22

8

p23

7

p24

6

p25

5

p26

4

p27

3

p28

2

p29

1

p30

0

p31

2 bpp

4 bpp

8 bpp

16 bpp

24 bpp

p0
p0
p1
p0
p2
p1
p3
p0
p4
p2
p5
p1
p6
p3
p7
p8
p4
p9
p2

p0

p10
p5
p11
p1
p12
p6
p13
p3
p14
p7
p15

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Table 699. FIFO bits for Little-endian Byte, Big-endian Pixel order
FIFO bit

1 bpp

31

p24

30

p25

29

p26

28

p27

27

p28

26

p29

25

p30

24

p31

23

p16

22

p17

21

p18

20

p19

19

p20

18

p21

17

p22

16

p23

15

p8

14

p9

13

p10

12

p11

11

p12

10

p13

9

p14

8

p15

7

p0

6

p1

5

p2

4

p3

3

p4

2

p5

1

p6

0

p7

2 bpp

4 bpp

8 bpp

16 bpp

24 bpp

p12
p6
p13
p3
p14
p7
p15
p1
p8
p4
p9
p2
p10
p5
p11
p4
p2
p5
p1

p0

p6
p3
p7
p0
p0
p0
p1
p0
p2
p1
p3

Table 700 shows the structure of the data in each DMA FIFO word in RGB mode.

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Table 700. RGB mode data formats
FIFO data 24-bit RGB

16-bit (1:5:5:5 RGB) 16-bit (5:6:5 RGB)

16-bit (4:4:4 RGB)

31

-

p1 intensity bit

p1, Blue 4

-

30

-

p1, Blue 4

p1, Blue 3

-

29

-

p1, Blue 3

p1, Blue 2

-

28

-

p1, Blue 2

p1, Blue 1

-

27

-

p1, Blue 1

p1, Blue 0

p1, Blue 3

26

-

p1, Blue 0

p1, Green 5

p1, Blue 2

25

-

p1, Green 4

p1, Green 4

p1, Blue 1

24

-

p1, Green 3

p1, Green 3

p1, Blue 0

23

p0, Blue 7

p1, Green 2

p1, Green 2

p1, Green 3

22

p0, Blue 6

p1, Green 1

p1, Green 1

p1, Green 2

21

p0, Blue 5

p1, Green 0

p1, Green 0

p1, Green 1

20

p0, Blue 4

p1, Red 4

p1, Red 4

p1, Green 0

19

p0, Blue 3

p1, Red 3

p1, Red 3

p1, Red 3

18

p0, Blue 2

p1, Red 2

p1, Red 2

p1, Red 2

17

p0, Blue 1

p1, Red 1

p1, Red 1

p1, Red 1

16

p0, Blue 0

p1, Red 0

p1, Red 0

p1, Red 0

15

p0, Green 7

p0 intensity bit

p0, Blue 4

-

14

p0, Green 6

p0, Blue 4

p0, Blue 3

-

13

p0, Green 5

p0, Blue 3

p0, Blue 2

-

12

p0, Green 4

p0, Blue 2

p0, Blue 1

-

11

p0, Green 3

p0, Blue 1

p0, Blue 0

p0, Blue 3

10

p0, Green 2

p0, Blue 0

p0, Green 5

p0, Blue 2

9

p0, Green 1

p0, Green 4

p0, Green 4

p0, Blue 1

8

p0, Green 0

p0, Green 3

p0, Green 3

p0, Blue 0

7

p0, Red 7

p0, Green 2

p0, Green 2

p0, Green 3

6

p0, Red 6

p0, Green 1

p0, Green 1

p0, Green 2

5

p0, Red 5

p0, Green 0

p0, Green 0

p0, Green 1

4

p0, Red 4

p0, Red 4

p0, Red 4

p0, Green 0

3

p0, Red 3

p0, Red 3

p0, Red 3

p0, Red 3

2

p0, Red 2

p0, Red 2

p0, Red 2

p0, Red 2

1

p0, Red 1

p0, Red 1

p0, Red 1

p0, Red 1

0

p0, Red 0

p0, Red 0

p0, Red 0

p0, Red 0

29.7.4 RAM palette
The RAM-based palette is a 256 x 16 bit dual-port RAM physically structured as 128 x 32
bits. Two entries can be written into the palette from a single word write access. The Least
Significant Bit (LSB) of the serialized pixel data selects between upper and lower halves of
the palette RAM. The half that is selected depends on the byte ordering mode. In
little-endian mode, setting the LSB selects the upper half, but in big-endian mode, the
lower half of the palette is selected.

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Pixel data values can be written and verified through the AHB slave interface. For
information on the supported colors, refer to the section on the related panel type earlier in
this chapter.
The palette RAM is a dual port RAM with independent controls and addresses for each
port. Port1 is used as a read/write port and is connected to the AHB slave interface. The
palette entries can be written and verified through this port. Port2 is used as a read-only
port and is connected to the unpacker and gray scaler. For color modes of less than 16
bpp, the palette enables each pixel value to be mapped to a 16-bit color:

• For TFT displays, the 16-bit value is passed directly to the pixel serializer.
• For STN displays, the 16-bit value is first converted by the gray scaler.
Table 701 shows the bit representation of the palette data. The palette 16-bit output uses
the TFT 1:5:5:5 data format. In 16 and 24 bpp TFT mode, the palette is bypassed and the
output of the pixel serializer is used as the TFT panel data.
Table 701. Palette data storage for TFT modes.
Bit(s)

Name

Description

Name

Description

(RGB format)

(RGB format)

(BGR format)

(BGR format)

31

I

Intensity / unused

I

Intensity / unused

30:26

B[4:0]

Blue palette data

R[4:0]

Red palette data

25:21

G[4:0]

Green palette data

G[4:0]

Green palette data

20:16

R[4:0]

Red palette data

B[4:0]

Blue palette data

15

I

Intensity / unused

I

Intensity / unused

14:10

B[4:0]

Blue palette data

R[4:0]

Red palette data

9:5

G[4:0]

Green palette data

G[4:0]

Green palette data

4:0

R[4:0]

Red palette data

B[4:0]

Blue palette data

The red and blue pixel data can be swapped to support BGR data format using a control
register bit (bit 8 = BGR). See the CTRL register description for more information.
Table 702 shows the bit representation of the palette data for the STN color modes.
Table 702. Palette data storage for STN color modes.
Bit(s)

Name

Description

Name

Description

(RGB format)

(RGB format)

(BGR format)

(BGR format)

-

Unused

-

Unused

30:27

B[3:0]

Blue palette data

R[3:0]

Red palette data

26

-

Unused

-

Unused

25:22

G[3:0]

Green palette data

G[3:0]

Green palette data

21

-

Unused

-

Unused

31

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R[3:0]

Red palette data

B[3:0]

Blue palette data

16

-

Unused

-

Unused

15

I

Unused

I

Unused

14:11

B[4:1]

Blue palette data

R[4:1]

Red palette data

10

B[0]

Unused

R[0]

Unused

9:6

G[4:1]

Green palette data

G[4:1]

Green palette data

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Table 702. Palette data storage for STN color modes.
Bit(s)

Name

Description

Name

Description

(RGB format)

(RGB format)

(BGR format)

(BGR format)

5

G[0]

Unused

G[0]

Unused

4:1

R[4:1]

Red palette data

B[4:1]

Blue palette data

0

R[0]

Unused

B[0]

Unused

For monochrome STN mode, only the red palette field bits [4:1] are used. However, in
STN color mode the green and blue [4:1] are also used. Only 4 bits per color are used,
because the gray scaler only supports 16 different shades per color.
Table 703 shows the bit representation of the palette data for the STN monochrome
mode.
Table 703. Palette data storage for STN monochrome mode.
Bit(s)

Name

Description

31

-

Unused

30:27

-

Unused

26

-

Unused

25:22

-

Unused

21

-

Unused

20:17

Y[3:0]

Intensity data

16

-

Unused

15

-

Unused

14:11

-

Unused

10

-

Unused

9:6

-

Unused

5

-

Unused

4:1

Y[3:0]

Intensity data

0

-

Unused

29.7.5 Hardware cursor
The hardware cursor is an integral part of the LCD controller. It uses the LCD timing
module to provide an indication of the current scan position coordinate, and intercepts the
pixel stream between the palette logic and the gray scale/output multiplexer.
All cursor programming registers are accessed through the LCD slave interface. This also
provides a read/write port to the cursor image RAM.

29.7.5.1 Cursor operation
The hardware cursor is contained in a dual port RAM. It is programmed by software
through the AHB slave interface. The AHB slave interface also provides access to the
hardware cursor control registers. These registers enable you to modify the cursor
position and perform various other functions.
When enabled, the hardware cursor uses the horizontal and vertical synchronization
signals, along with a pixel clock enable and various display parameters to calculate the
current scan coordinate.
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When the display point is inside the bounds of the cursor image, the cursor replaces
frame buffer pixels with cursor pixels.
When the last cursor pixel is displayed, an interrupt is generated that software can use as
an indication that it is safe to modify the cursor image. This enables software controlled
animations to be performed without flickering for frame synchronized cursors.

29.7.5.2 Cursor sizes
Two cursor sizes are supported, as shown in Table 704.
Table 704. Palette data storage for STN monochrome mode.
X Pixels

Y Pixels

Bits per pixel

Words per line

Words in cursor image

32

32

2

2

64

64

64

2

4

256

29.7.5.3 Cursor movement
The following descriptions assume that both the screen and cursor origins are at the top
left of the visible screen (the first visible pixel scanned each frame). Figure 92 shows how
each pixel coordinate is assumed to be the top left corner of the pixel.

CRSR_XY(X)

CRSR_XY(Y)

(0,0)

Fig 92. Cursor movement

29.7.5.4 Cursor XY positioning
The CRSR_XY register controls the cursor position on the cursor overlay (see Cursor XY
Position register). This provides separate fields for X and Y ordinates.
The CRSR_CFG register (see Cursor Configuration register) provides a FrameSync bit
controlling the visible behavior of the cursor.

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With FrameSync inactive, the cursor responds immediately to any change in the
programmed CRSR_XY value. Some transient smearing effects may be visible if the
cursor is moved across the LCD scan line.
With FrameSync active, the cursor only updates its position after a vertical
synchronization has occurred. This provides clean cursor movement, but the cursor
position only updates once a frame.

29.7.5.5 Cursor clipping
The CRSR_XY register (see Cursor XY Position register) is programmed with positive
binary values that enable the cursor image to be located anywhere on the visible screen
image. The cursor image is clipped automatically at the screen limits when it extends
beyond the screen image to the right or bottom (see X1,Y1 in Figure 93). The checked
pattern shows the visible portion of the cursor.
Because the CRSR_XY register values are positive integers, to emulate cursor clipping
on the left and top of screen, a Clip Position register, CRSR_CLIP, is provided. This
controls which point of the cursor image is positioned at the CRSR_CLIP coordinate. For
clipping functions on the Y axis, CRSR_XY(X) is zero, and Clip(X) is programmed to
provide the offset into the cursor image (X2 and X3). The equivalent function is provided
to clip on the X axis at the top of the display (Y2).
For cursors that are not clipped at the X=0 or Y=0 lines, program the Clip Position register
X and Y fields with zero to display the cursor correctly. See Clip(X4,Y4) for the effect of
incorrect programming.

Cursor(X5)
Clip(X3)

Cursor(Y1)

Clip(Y4)

Cursor(Y5)

Clip(Y2)

Clip(X2)

Clip(X4)

Cursor(X1)

Fig 93. Cursor clipping
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29.7.5.6 Cursor image format
The LCD frame buffer supports three packing formats, but the hardware cursor image
requirement has been simplified to support only LBBP. This is little-endian byte,
big-endian pixel for Windows CE mode.
The Image RAM start address is offset by 0x800 from the LCD base address, as shown in
the register description in this chapter.
The displayed cursor coordinate system is expressed in terms of (X,Y). 64 x 64 is an
extension of the 32 x 32 format shown in Figure 94.

TOP
(0, 0)

(1, 0)

(2, 0)

(29, 0)

(30, 0)

(31, 0)

(0, 1)

(1, 1)

(2, 1)

(29, 1)

(30, 1)

(31, 1)

(0, 2)

(1, 2)

(2, 2)

(29, 2)

(30, 2)

(31, 2)

LEFT

RIGHT

(0, 29)

(1, 29)

(2, 29)

(29, 29)

(30, 29)

(31, 29)

(0, 30)

(1, 30)

(2, 30)

(29, 30)

(30, 30)

(31, 30)

(0, 31)

(1, 31)

(2, 31)

(29, 31)

(30, 31)

(31, 31)

BOTTOM

Fig 94. Cursor image format

32 by 32 pixel format
Four cursors are held in memory, each with the same pixel format. Table 705 lists the
base addresses for the four cursors.
Table 705. Addresses for 32 x 32 cursors

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Address

Description

0x4000 8800

Cursor 0 start address.

0x4000 8900

Cursor 1 start address.

0x4000 8A00

Cursor 2 start address.

0x4000 8B00

Cursor 3 start address.
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Table 706 shows the buffer to pixel mapping for Cursor 0.
Table 706. Buffer to pixel mapping for 32 x 32 pixel cursor format
Offset into cursor memory
Data bits

0

4

(8 * y)

(8 * y) +4

F8

FC

31:30

(12, 0)

(28, 0)

(12, y)

(28, y)

(12, 31)

(28,31)

29:28

(13, 0)

(29, 0)

(13, y)

(29, y)

(13, 31)

(29, 31)

27:26

(14, 0)

(30, 0)

(14, y)

(30, y)

(14, 31)

(30, 31)

25:24

(15, 0)

(31, 0)

(15, y)

(31, y)

(15, 31)

(31, 31)

23:22

(8, 0)

(24, 0)

(8, y)

(24, y)

(8, 31)

(24, 31)

21:20

(9, 0)

(25, 0)

(9, y)

(25, y)

(9, 31)

(25, 31)

19:18

(10, 0)

(26, 0)

(10, y)

(26, y)

(10, 31)

(26, 31)

17:16

(11, 0)

(27, 0)

(11, y)

(27, y)

(11, 31)

(27, 31)

15:14

(4, 0)

(20, 0)

(4, y)

(20, y)

(4, 31)

(20, 31)

13:12

(5, 0)

(21, 0)

(5, y)

(21, y)

(5, 31)

(21, 31)

11:10

(6, 0)

(22, 0)

(6, y)

(22, y)

(6, 31)

(22, 31)

9:8

(7, 0)

(23, 0)

(7, y)

(23, y)

(7, 31)

(23, 31)

7:6

(0, 0)

(16, 0)

(0, y)

(16, y)

(0, 31)

(16, 31)

5:4

(1, 0)

(17, 0)

(1, y)

(17, y)

(1, 31)

(17, 31)

3:2

(2, 0)

(18, 0)

(2, y)

(18, y)

(2, 31)

(18, 31)

1:0

(3, 0)

(19, 0)

(3, y)

(19, y)

(3, 31)

(19, 31)

64 by 64 pixel format
Only one cursor fits in the memory space in 64 x 64 mode. Table 707 shows the 64 x 64
cursor format.
Table 707. Buffer to pixel mapping for 64 x 64 pixel cursor format
Offset into cursor memory
Data bits

0

4

8

12

(16 * y)

(16 * y) +4

(16 * y) + 8

(16 * y) + 12

FC

31:30

(12, 0)

(28, 0)

(44, 0)

(60, 0)

(12, y)

(28, y)

(44, y)

(60, y)

(60, 63)

29:28

(13, 0)

(29, 0)

(45, 0)

(61, 0)

(13, y)

(29, y)

(45, y)

(61, y)

(61, 63)

27:26

(14, 0)

(30, 0)

(46, 0)

(62, 0)

(14, y)

(30, y)

(46, y)

(62, y)

(62, 63)

25:24

(15, 0)

(31, 0)

(47, 0)

(63, 0)

(15, y)

(31, y)

(47, y)

(63, y)

(63, 63)

23:22

(8, 0)

(24, 0)

(40, 0)

(56, 0)

(8, y)

(24, y)

(40, y)

(56, y)

(56, 63)

21:20

(9, 0)

(25, 0)

(41, 0)

(57, 0)

(9, y)

(25, y)

(41, y)

(57, y)

(57, 63)

19:18

(10, 0)

(26, 0)

(42, 0)

(58, 0)

(10, y)

(26, y)

(42, y)

(58, y)

(58, 63)

17:16

(11, 0)

(27, 0)

(43, 0)

(59, 0)

(11, y)

(27, y)

(43, y)

(59, y)

(59, 63)

15:14

(4, 0)

(20, 0)

(36, 0)

(52, 0)

(4, y)

(20, y)

(36, y)

(52, y)

(52, 63)

13:12

(5, 0)

(21, 0)

(37, 0)

(53, 0)

(5, y)

(21, y)

(37, y)

(53, y)

(53, 63)

11:10

(6, 0)

(22, 0)

(38, 0)

(54, 0)

(6, y)

(22, y)

(38, y)

(54, y)

(54, 63)

9:8

(7, 0)

(23, 0)

(39, 0)

(55, 0)

(7, y)

(23, y)

(39, y)

(55, y)

(55, 63)

7:6

(0, 0)

(16, 0)

(32, 0)

(48, 0)

(0, y)

(16, y)

(32, y)

(48, y)

(48, 63)

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Table 707. Buffer to pixel mapping for 64 x 64 pixel cursor format
Offset into cursor memory
Data bits

0

4

8

12

(16 * y)

(16 * y) +4

(16 * y) + 8

(16 * y) + 12

FC

5:4

(1, 0)

(17, 0)

(33, 0)

(49, 0)

(1, y)

(17, y)

(33, y)

(49, y)

(49, 63)

3:2

(2, 0)

(18, 0)

(34, 0)

(50, 0)

(2, y)

(18, y)

(34, y)

(50, y)

(50, 63)

1:0

(3, 0)

(19, 0)

(35, 0)

(51, 0)

(3, y)

(19, y)

(35, y)

(51, y)

(51, 63)

Cursor pixel encoding
Each pixel of the cursor requires two bits of information. These are interpreted as Color0,
Color1, Transparent, and Transparent inverted.
In the coding scheme, bit 1 selects between color and transparent (AND mask) and bit 0
selects variant (XOR mask).
Table 708 shows the pixel encoding bit assignments.
Table 708. Pixel encoding
Value
00

Description
Color0.
The cursor color is displayed according to the Red-Green-Blue (RGB) value
programmed into the CRSR_PAL0 register.

01

Color1.
The cursor color is displayed according to the RGB value programmed into the
CRSR_PAL1 register.

10

Transparent.
The cursor pixel is transparent, so is displayed unchanged. This enables the visible
cursor to assume shapes that are not square.

11

Transparent inverted.
The cursor pixel assumes the complementary color of the frame pixel that is displayed.
This can be used to ensure that the cursor is visible regardless of the color of the
frame buffer image.

29.7.6 Gray scaler
A patented gray scale algorithm drives monochrome and color STN panels. This provides
15 gray scales for monochrome displays. For STN color displays, the three color
components (RGB) are gray scaled simultaneously. This results in 3375 (15x15x15)
colors being available. The gray scaler transforms each 4-bit gray value into a sequence
of activity-per-pixel over several frames, relying to some degree on the display
characteristics, to give the representation of gray scales and color.

29.7.7 Upper and lower panel formatters
Formatters are used in STN mode to convert the gray scaler output to a parallel format as
required by the display. For monochrome displays, this is either 4 or 8 bits wide, and for
color displays, it is 8 bits wide. Table 709 shows a color display driven with 2 2/3 pixels
worth of data in a repeating sequence.
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Table 709. Color display driven with 2 2/3 pixel data
Byte

CLD[7]

CLD[6]

CLD[5]

CLD[4]

CLD[3]

CLD[2]

CLD[1]

CLD[0]

0

P2[Green]

P2[Red]

P1[Blue]

P1[Green]

P1[Red]

P0[Blue]

P0[Green]

P0[Red]

1

P5[Red]

P4q[Blue]

P4[Green]

P4[Red]

P3[Blue]

P3[Green]

P3[Red]

P2[Blue]

2

P7[Blue]

P7[Green]

P7[Red]

P6[Blue]

P6[Green]

P6[Red]

P5[Blue]

P5[Green]

Each formatter consists of three 3-bit (RGB) shift left registers. RGB pixel data bit values
from the gray scaler are concurrently shifted into the respective registers. When enough
data is available, a byte is constructed by multiplexing the registered data to the correct bit
position to satisfy the RGB data pattern of LCD panel. The byte is transferred to the 3-byte
FIFO, which has enough space to store eight color pixels.

29.7.8 Panel clock generator
The output of the panel clock generator block is the panel clock, pin LCDDCLK. The panel
clock can be based on either the peripheral clock for the LCD block or the external clock
input for the LCD, pin LCDCLKIN. Whichever source is selected can be divided down in
order to produce the internal LCD clock, LCDCLK.
The panel clock generator can be programmed to output the LCD panel clock in the range
of LCDCLK/2 to LCDCLK/1025 to match the bpp data rate of the LCD panel being used.
The CLKSEL bit in the POL register determines whether the base clock used is CCLK or
the LCDCLKIN pin.

29.7.9 Timing controller
The primary function of the timing controller block is to generate the horizontal and vertical
timing panel signals. It also provides the panel bias and enable signals. These timings are
all register-programmable.

29.7.10 STN and TFT data select
Support is provided for passive Super Twisted Nematic (STN) and active Thin Film
Transistor (TFT) LCD display types:

29.7.10.1 STN displays
STN display panels require algorithmic pixel pattern generation to provide pseudo gray
scaling on monochrome displays, or color creation on color displays.

29.7.10.2 TFT displays
TFT display panels require the digital color value of each pixel to be applied to the display
data inputs.

29.7.11 Interrupt generation
Four interrupts are generated by the LCD controller, and a single combined interrupt. The
four interrupts are:

• Master bus error interrupt.
• Vertical compare interrupt.
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• Next base address update interrupt.
• FIFO underflow interrupt.
Each of the four individual maskable interrupts is enabled or disabled by changing the
mask bits in the INT_MSK register. These interrupts are also combined into a single
overall interrupt, which is asserted if any of the individual interrupts are both asserted and
unmasked. Provision of individual outputs in addition to a combined interrupt output
enables use of either a global interrupt service routine, or modular device drivers to
handle interrupts.
The status of the individual interrupt sources can be read from the INTRAW register.

29.7.11.1 Master bus error interrupt
The master bus error interrupt is asserted when an ERROR response is received by the
master interface during a transaction with a slave. When such an error is encountered, the
master interface enters an error state and remains in this state until clearance of the error
has been signaled to it. When the respective interrupt service routine is complete, the
master bus error interrupt may be cleared by writing a 1 to the BERIC bit in the INTCLR
register. This action releases the master interface from its ERROR state to the start of
FRAME state, and enables fresh frame of data display to be initiated.

29.7.11.2 Vertical compare interrupt
The vertical compare interrupt asserts when one of four vertical display regions, selected
using the CTRL register, is reached. The interrupt can be made to occur at the start of:

•
•
•
•

Vertical synchronization.
Back porch.
Active video.
Front porch.

The interrupt may be cleared by writing a 1 to the VcompIC bit in the INTCLR register.
29.7.11.2.1

Next base address update interrupt
The LCD next base address update interrupt asserts when either the LCDUPBASE or
LCDLPBASE values have been transferred to the LCDUPCURR or LCDLPCURR
incrementers respectively. This signals to the system that it is safe to update the
LCDUPBASE or the LCDLPBASE registers with new frame base addresses if required.
The interrupt can be cleared by writing a 1 to the LNBUIC bit in the INTCLR register

29.7.11.2.2

FIFO underflow interrupt
The FIFO underflow interrupt asserts when internal data is requested from an empty DMA
FIFO. Internally, upper and lower panel DMA FIFO underflow interrupt signals are
generated.
The interrupt can be cleared by writing a 1 to the FUFIC bit in the INTCLR register.

29.7.12 LCD power-up and power-down sequence
The LCD controller requires the following power-up sequence to be performed:

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Chapter 29: LPC43xx/LPC43Sxx LCD

1. When power is applied, the following signals are held LOW:

•
•
•
•
•
•

LCDLP
LCDDCLK
LCDFP
LCDENAB/ LCDM
LCDVD[23:0]
LCDLE

2. When LCD power is stabilized, a 1 is written to the LcdEn bit in the CTRL register. This
enables the following signals into their active states:

•
•
•
•
•

LCDLP
LCDDCLK
LCDFP
LCDENAB/ LCDM
LCDLE

The LCDV[23:0] signals remain in an inactive state.
3. When the signals in step 2 have stabilized, the contrast voltage (not controlled or
supplied by the LCD controller) is applied to the LCD panel.
4. If required, a software or hardware timer can be used to provide the minimum display
specific delay time between application of the control signals and power to the panel
display. On completion of the time interval, power is applied to the panel by writing a 1 to
the LcdPwr bit within the CTRL register that, in turn, sets the LCDPWR signal high and
enables the LCDV[23:0] signals into their active states. The LCDPWR signal is intended
to be used to gate the power to the LCD panel.
The power-down sequence is the reverse of the above four steps and must be strictly
followed, this time, writing the respective register bits with 0.
Figure 95 shows the power-up and power-down sequences.

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Chapter 29: LPC43xx/LPC43Sxx LCD

LCD on sequence

LCD off sequence
Minimum 0 ms

Minimum 0 ms
LCD Power
Minimum 0 ms

Minimum 0 ms

LCDLP, LCDCP,
LCDFP, LCDAC,
LCDLE
Contrast Voltage
LCDPWR,
LCD[23:0]

Display specific delay

Display specific delay

Fig 95. Power-up and power-down sequences

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Chapter 29: LPC43xx/LPC43Sxx LCD

29.8 LCD timing diagrams
one horizontal line

pixel clock
(internal)
LCD_TIMH (HSW)
LCDLP
(line synch
pulse)

LCDDCLK
(panel clock)

suppressed
during LCDLP

LCD_TIMH (HBP)

16  LCD_TIMH(PPL)  1

horizontal back porch
(defined in pixel clocks)

LCD_TIMH (HFP)

horizontal front porch
(defined in pixel clocks)

LCDVD[15:0]
(panel data)
one horizontal line of LCD data

(1) The active data lines will vary with the type of STN panel (4-bit, 8-bit, color, mono) and with single or dual frames.
(2) The LCD panel clock is selected and scaled by the LCD controller and used to produce LCDCLK.
(3) The duration of the LCDLP signal is controlled by the HSW field in the TIMH register.
(4) The Polarity of the LCDLP signal is determined by the IHS bit in the POL register.

Fig 96. Horizontal timing for STN displays

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Chapter 29: LPC43xx/LPC43Sxx LCD

one frame

LCDDCLK
(panel clock)

panel data clock active

LCD_TIMV (VSW)
LCDFP
(vertical synch
pulse)
LCD_TIMV (VBP)

LCD_TIMV(LPP)

LCD_TIMV (VFP)

back porch
(defined in line clocks)

all horizontal lines for one frame

front porch
(defined in line clocks)

pixel data
and horizontal
controls for one
frame
see horizontal timing for STN displays

(1) Signal polarities may vary for some displays.

Fig 97. Vertical timing for STN displays

one horizontal line

pixel clock
(internal)
LCD_TIMH (HSW)
LCDLP
(lhorizontal
synch pulse)

LCDDCLK
(panel clock)

LCD_TIMH (HBP)

LCD_TIMH(PPL)

LCD_TIMH (HFP)

LCDENAB
horizontal back porch
(defined in pixel clocks)

horizontal front porch
(defined in pixel clocks)

LCDVD[23:0]
(panel data)
one horizontal line of LCD data

(1) The active data lines will vary with the type of TFT panel.
(2) The LCD panel clock is selected and scaled by the LCD controller and used to produce LCDCLK.
(3) The duration of the LCDLP is controlled by the HSW field in the TIMH register.
(4) The polarity of the LCDLP signal is determined by the IHS bit in the POL register.

Fig 98. Horizontal timing for TFT displays
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Chapter 29: LPC43xx/LPC43Sxx LCD

one frame

LCDDCLK
(panel clock)

panel data clock active

LCDENA
(data enable)

data enable

LCD_TIMV (VSW)
LCDFP
(vertical synch
pulse)
LCD_TIMV (VBP)

LCD_TIMV(LPP)

LCD_TIMV (VFP)

back porch
(defined in line clocks)

all horizontal lines for one frame

front porch
(defined in line clocks)

pixel data
and horizontal
control signals
for one frame
see horizontal timing for TFT displays

(1) Polarities may vary for some displays.

Fig 99. Vertical timing for TFT displays

29.9 LCD panel signal usage
Table 710. LCD panel connections for STN single panel mode
External pin

4-bit mono STN single panel

8-bit mono STN single panel

Color STN single panel

LPC43xx pin
used

LCD function

LPC43xx pin
used

LCD function

LPC43xx pin
used

LCD function

LCDVD23

-

-

-

-

-

-

LCDVD22

-

-

-

-

-

-

LCDVD21

-

-

-

-

-

-

LCDVD20

-

-

-

-

-

-

LCDVD19

-

-

-

-

-

-

LCDVD18

-

-

-

-

-

-

LCDVD17

-

-

-

-

-

-

LCDVD16

-

-

-

-

-

-

LCDVD15

-

-

-

-

-

-

LCDVD14

-

-

-

-

-

-

LCDVD13

-

-

-

-

-

-

LCDVD12

-

-

-

-

-

-

LCDVD11

-

-

-

-

-

-

LCDVD10

-

-

-

-

-

-

LCDVD9

-

-

-

-

-

-

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Chapter 29: LPC43xx/LPC43Sxx LCD

Table 710. LCD panel connections for STN single panel mode
External pin

4-bit mono STN single panel

8-bit mono STN single panel

Color STN single panel

LPC43xx pin
used

LPC43xx pin
used

LPC43xx pin
used

LCD function

LCD function

LCD function

LCDVD8

-

-

-

-

-

-

LCDVD7

-

-

P8_4

UD[7]

P8_4

UD[7]

LCDVD6

-

-

P8_5

UD[6]

P8_5

UD[6]

LCDVD5

-

-

P8_6

UD[5]

P8_6

UD[5]

LCDVD4

-

-

P8_7

UD[4]

P8_7

UD[4]

LCDVD3

P4_2

UD[3]

P4_2

UD[3]

P4_2

UD[3]

LCDVD2

P4_3

UD[2]

P4_3

UD[2]

P4_3

UD[2]

LCDVD1

P4_4

UD[1]

P4_4

UD[1]

P4_4

UD[1]

LCDVD0

P4_1

UD[0]

P4_1

UD[0]

P4_1

UD[0]

LCDLP

P7_6

LCDLP

P7_6

LCDLP

P7_6

LCDLP

LCDENAB/
LCDM

P4_6

LCDENAB/
LCDM

P4_6

LCDENAB/
LCDM

P4_6

LCDENAB/
LCDM

LCDFP

P4_5

LCDFP

P4_5

LCDFP

P4_5

LCDFP

LCDDCLK

P4_7

LCDDCLK

P4_7

LCDDCLK

P4_7

LCDDCLK

LCDLE

P7_0

LCDLE

P7_0

LCDLE

P7_0

LCDLE

LCDPWR

P7_7

CDPWR

P7_7

LCDPWR

P7_7

LCDPWR

GP_CLKIN

PF_4

LCDCLKIN

PF_4

LCDCLKIN

PF_4

LCDCLKIN

Table 711. LCD panel connections for STN dual panel mode
External pin

4-bit mono STN dual panel

8-bit mono STN dual panel

Color STN dual panel

LPC43xx pin
used

LCD function

LPC43xx pin
used

LCD function

LPC43xx pin
used

LCD function

LCDVD23

-

-

-

-

-

-

LCDVD22

-

-

-

-

-

-

LCDVD21

-

-

-

-

-

-

LCDVD20

-

-

-

-

-

-

LCDVD19

-

-

-

-

-

-

LCDVD18

-

-

-

-

-

-

LCDVD17

-

-

-

-

-

-

LCDVD16

-

-

-

-

-

-

LCDVD15

-

-

PB_4

LD[7]

PB_4

LD[7]

LCDVD14

-

-

PB_5

LD[6]

PB_5

LD[6]

LCDVD13

-

-

PB_6

LD[5]

PB_6

LD[5]

LCDVD12

-

-

P8_3

LD[4]

P8_3

LD[4]

LCDVD11

P4_9

LD[3]

P4_9

LD[3]

P4_9

LD[3]

LCDVD10

P4_10

LD[2]

P4_10

LD[2]

P4_10

LD[2]

LCDVD9

P4_8

LD[1]

P4_8

LD[1]

P4_8

LD[1]

LCDVD8

P7_5

LD[0]

P7_5

LD[0]

P7_5

LD[0]

LCDVD7

-

-

UD[7]

P8_4

UD[7]

LCDVD6

-

-

UD[6]

P8_5

UD[6]

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Chapter 29: LPC43xx/LPC43Sxx LCD

Table 711. LCD panel connections for STN dual panel mode
External pin

4-bit mono STN dual panel

8-bit mono STN dual panel

Color STN dual panel

LPC43xx pin
used

LCD function

LPC43xx pin
used

LCD function

LPC43xx pin
used

LCD function

LCDVD5

-

-

P8_6

UD[5]

P8_6

UD[5]

LCDVD4

-

-

P8_7

UD[4]

P8_7

UD[4]

LCDVD3

P4_2

UD[3]

P4_2

UD[3]

P4_2

UD[3]

LCDVD2

P4_3

UD[2]

P4_3

UD[2]

P4_3

UD[2]

LCDVD1

P4_4

UD[1]

P4_4

UD[1]

P4_4

UD[1]

LCDVD0

P4_1

UD[0]

P4_1

UD[0]

P4_1

UD[0]

LCDLP

P7_6

LCDLP

P7_6

LCDLP

P7_6

LCDLP

LCDENAB/
LCDM

P4_6

LCDENAB/
LCDM

P4_6

LCDENAB/
LCDM

P4_6

LCDENAB/
LCDM

LCDFP

P4_5

LCDFP

P4_5

LCDFP

P4_5

LCDFP

LCDDCLK

P4_7

LCDDCLK

P4_7

LCDDCLK

P4_7

LCDDCLK

LCDLE

P7_0

LCDLE

P7_0

LCDLE

P7_0

LCDLE

LCDPWR

P7_7

LCDPWR

P7_7

LCDPWR

P7_7

LCDPWR

GP_CLKIN

PF_4

LCDCLKIN

PF_4

LCDCLKIN

PF_4

LCDCLKIN

Table 712. LCD panel connections for TFT panels
External
pin

TFT 12 bit (4:4:4 mode) TFT 16 bit (5:6:5 mode)

TFT 16 bit (1:5:5:5 mode) TFT 24 bit

LPC43xx
pin used

LCD
function

LPC43xx
pin used

LCD
function

LPC43xx pin LCD
used
function

LPC43xx
pin used

LCD
function

LCDVD23

PB_0

BLUE3

PB_0

BLUE4

PB_0

BLUE4

PB_0

BLUE7

LCDVD22

PB_1

BLUE2

PB_1

BLUE3

PB_1

BLUE3

PB_1

BLUE6

LCDVD21

PB_2

BLUE1

PB_2

BLUE2

PB_2

BLUE2

PB_2

BLUE5

LCDVD20

PB_3

BLUE0

PB_3

BLUE1

PB_3

BLUE1

PB_3

BLUE4

LCDVD19

-

-

P7_1

BLUE0

P7_1

BLUE0

P7_1

BLUE3

LCDVD18

-

-

-

-

P7_2

intensity

P7_2

BLUE2

LCDVD17

-

-

-

-

-

-

P7_3

BLUE1

LCDVD16

-

-

-

-

-

-

P7_4

BLUE0

LCDVD15

PB_4

GREEN3

PB_4

GREEN5

PB_4

GREEN4

PB_4

GREEN7

LCDVD14

PB_5

GREEN2

PB_5

GREEN4

PB_5

GREEN3

PB_5

GREEN6

LCDVD13

PB_6

GREEN1

PB_6

GREEN3

PB_6

GREEN2

PB_6

GREEN5

LCDVD12

P8_3

GREEN0

P8_3

GREEN2

P8_3

GREEN1

P8_3

GREEN4

LCDVD11

-

-

P4_9

GREEN1

P4_9

GREEN0

P4_9

GREEN3

LCDVD10

-

-

P4_10

GREEN0

P4_10

intensity

P4_10

GREEN2

LCDVD9

-

-

-

-

-

-

P4_8

GREEN1

LCDVD8

-

-

-

-

-

-

P7_5

GREEN0

LCDVD7

P8_4

RED3

P8_4

RED4

P8_4

RED4

P8_4

RED7

LCDVD6

P8_5

RED2

P8_5

RED3

P8_5

RED3

P8_5

RED6

LCDVD5

P8_6

RED1

P8_6

RED2

P8_6

RED2

P8_6

RED5

LCDVD4

P8_7

RED0

P8_7

RED1

P8_7

RED1

P8_7

RED4

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Table 712. LCD panel connections for TFT panels
External
pin

TFT 12 bit (4:4:4 mode) TFT 16 bit (5:6:5 mode)

TFT 16 bit (1:5:5:5 mode) TFT 24 bit

LPC43xx
pin used

LCD
function

LPC43xx
pin used

LCD
function

LPC43xx pin LCD
used
function

LPC43xx
pin used

LCD
function

LCDVD3

-

-

P4_2

RED0

P4_2

RED0

P4_2

RED3

LCDVD2

-

-

-

-

P4_3

intensity

P4_3

RED2

LCDVD1

-

-

-

-

-

-

P4_4

RED1

LCDVD0

-

-

-

-

-

-

P4_1

RED0

LCDLP

P7_6

LCDLP

P7_6

LCDLP

P7_6

LCDLP

P7_6

LCDLP

LCDENAB/
LCDM

P4_6

LCDENAB/ P4_6
LCDM

LCDENAB/ P4_6
LCDM

LCDENAB/ P4_6
LCDM

LCDFP

P4_5

LCDFP

P4_5

LCDFP

P4_5

LCDFP

P4_5

LCDFP

LCDDCLK

P4_7

LCDDCLK

P4_7

LCDDCLK

P4_7

LCDDCLK

P4_7

LCDDCLK

LCDLE

P7_0

LCDLE

P7_0

LCDLE

P7_0

LCDLE

P7_0

LCDLE

LCDPWR

P7_7

LCDPWR

P7_7

LCDPWR

P7_7

LCDPWR

P7_7

LCDPWR

LCDCLKIN

PF_4

LCDCLKIN PF_4

GP_CLKIN PF_4

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Chapter 30: LPC43xx/LPC43Sxx State Configurable Timer
(SCT)
Rev. 2.4 — 22 August 2018

User manual

30.1 How to read this chapter
The SCT without the dither engine is available on all flashless LPC43xx/LPC43Sxx parts
(LPC4370/50/30/20/10).

30.2 Basic configuration
The SCT is configured as follows:

•
•
•
•

See Table 713 for clocking and power control.
The SCT is reset by the SCT_RST (reset #37).
Connect inputs and outputs of the SCT through the GIMA (see Chapter 18).
The SCT combined interrupt is connected to slot # 10 in the NVIC. SCT outputs 2, 6,
14 are ORed with timer match channels and connected to slots # 13, 14, 16 in the
Event router (see Table 82).

• To connect the SCT outputs 0 and 1 to the GPDMA, use the DMAMUX register in the
CREG block (see Table 100).

• The SCT outputs are ORed with various timer match outputs if bit CTOUTCTRL in
CREG6 is zero (see Table 104; this is the default). Set the CTOUTCTRL bit to one to
use the SCT outputs without interference from the timers.
Table 713. SCT clocking and power control

SCT

Base clock

Branch clock

Operating
frequency

BASE_M4_CLK

CLK_M4_SCT

up to 204 MHz

30.3 Features
•
•
•
•
•

Two 16-bit counters or one 32-bit counter.
Counters clocked by bus clock or selected input.
Up counters or up-down counters.
State variable allows sequencing across multiple counter cycles.
The following conditions define an event: a counter match condition, an input (or
output) condition, a combination of a match and/or and input/output condition in a
specified state.

• Events control outputs, interrupts, and DMA requests.
• Selected events can limit, halt, start, or stop a counter.
• Supports:
– 8 inputs
– 16 outputs
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Chapter 30: LPC43xx/LPC43Sxx State Configurable Timer (SCT)

– 16 match/capture registers
– 16 events
– 32 states

30.4 General description
The State Configurable Timer (SCT) allows a wide variety of timing, counting, output
modulation, and input capture operations.
The most basic user-programmable option is whether a SCT operates as two 16-bit
counters or a unified 32-bit counter. In the two-counter case, in addition to the counter
value the following operational elements are independent for each half:

• State variable
• Limit, halt, stop, and start conditions
• Values of Match/Capture registers, plus reload or capture control values
In the two-counter case, the following operational elements are global to the SCT:

•
•
•
•
•
•

Clock selection
Inputs
Events
Outputs
Interrupts
DMA requests

Events, outputs, interrupts, and DMA requests can use match conditions from either
counter.
Remark: This document uses the term “bus error” to indicate an SCT response that
makes the processor take an exception.

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Chapter 30: LPC43xx/LPC43Sxx State Configurable Timer (SCT)

CLK_M4_SCT

SCT clock

prescaler(s)

Fig 100. SCT block diagram

SCT clock

CLK_M4_SCT

prescaler
H counter
Unified
counter

prescaler
L counter

Fig 101. SCT counter and select logic

30.5 Pin description
The SCT inputs can originate from the external pins or from several internal sources.
Each SCT input is connected to one GIMA register which defines the input source.
Remark: SCT outputs are connected to the CTOUT_n pins and are ORed with timer
match outputs when the CTOUCTRL bit is set to 0 in CREG6 (see Table 104; this is the
default). Some SCT outputs are connected to multiple destinations at once, for example to
an external pin and the event router.
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Chapter 30: LPC43xx/LPC43Sxx State Configurable Timer (SCT)

Table 714. SCT inputs and outputs
Description

Pin function Internal signal

Default (see
GIMA,
Table 207)

CTOUTCTRL
bit (see
Table 104)

CTIN_0

-

yes

-

-

SGPIO3

no

-

-

SGPIO3_DIV

no

-

CTIN_1

-

yes

-

-

USART2 TX active

no

-

-

SGPIO12

no

-

CTIN_2

-

yes

-

-

SGPIO12

no

-

-

SGPIO12_DIV

no

-

CTIN_3

-

yes

-

-

USART0 TX active

no

-

-

I2S1_RX_MWS

no

-

-

I2S1_TX_MWS

no

-

CTIN4

-

yes

-

USART0 RX active

no

-

SCT inputs

SCT input 0

SCT input 1

SCT input 2

SCT input 3

SCT input 4

SCT input 5

SCT input 6

SCT input 7

I2S1_RX_MWS

no

-

I2S1_TX_MWS

no

-

CTIN_5

-

yes

-

-

USART2 TX active

no

-

-

SGPIO12_DIV

CTIN_6

-

yes

-

-

USART3 TX active

no

-

-

I2S0_RX_MWS

no

-

-

I2S0_TX_MWS

no

-

CTIN_7

-

yes

-

-

USART3 RX active

no

-

-

SOF0

no

-

-

SOF1

no

-

CTOUT_0

-

-

0

SCT outputs

SCT output 0 ORed with Timer0 match output 0
SCT output 0

CTOUT_0

-

-

1

SCT output 1 ORed with Timer3 match output 3

CTOUT_1

-

-

0

SCT output 1

CTOUT_1

-

-

1

SCT output 2 ORed with Timer0 match output 2

CTOUT_2

Event router input 13

-

0

SCT output 2

CTOUT_2

Event router input 13

-

1

SCT output 3 ORed with Timer0 match output 3

CTOUT_3

T1 capture channel 3

-

0

SCT output 3

CTOUT_3

T1 capture channel 3

-

1

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Chapter 30: LPC43xx/LPC43Sxx State Configurable Timer (SCT)

Table 714. SCT inputs and outputs …continued
Description

Pin function Internal signal

Default (see
GIMA,
Table 207)

CTOUTCTRL
bit (see
Table 104)

SCT output 4 ORed with Timer3 match output 3

CTOUT_4

-

-

0

SCT output 4

CTOUT_4

-

SCT output 5 ORed with Timer3 match output 3

CTOUT_5

-

SCT output 5

CTOUT_5

-

SCT output 6 ORed with Timer1 match output 2

CTOUT_6

Event router input 14

SCT output 6

CYOUT_6

Event router input 14

SCT output 7 ORed with Timer1 match output 3

CTOUT_7

T2 capture channel 3

SCT output 7

CTOUT_7

T2 capture channel 3

SCT output 8 ORed with Timer2 match output 0

CTOUT_8

ADC start1 input (ADC

1
-

0
1

-

0
1

-

0
1

-

0

CR register bit START =
0x3)
SCT output 8

CTOUT_8

ADC start1 input (ADC

1

CR register bit START =
0x3)
SCT output 9 ORed with Timer3 match output 3

CTOUT_9

-

-

0

SCT output 9

CTOUT_9

-

SCT output 10 ORed with Timer3 match output 3

CTOUT_10

-

SCT output 10

CTOUT_10

-

SCT output 11 ORed with Timer2 match output 3

CTOUT_11

T3 capture channel 3

-

0

SCT output 11

CTOUT_11

T3 capture channel 3

-

1

SCT output 12 ORed with Timer3 match output 3

CTOUT_12

-

-

0

SCT output 12

CTOUT_12

-

-

1

SCT output 13 ORed with Timer3 match output 3

CTOUT_13

-

-

0

SCT output 13

CTOUT_13

-

-

1

SCT output 14 ORed with Timer3 match output 2

CTOUT_14

Event router input 16

-

0

SCT output 14

CTOUT_14

Event router input 16

-

1

SCT output 15 ORed with Timer3 match output 3

CTOUT_15

T0 capture channel
3/ADC start0 input (ADC

0

1
-

0
1

CR register START bits
= 0x2)
SCT output 15

CTOUT_15

T0 capture channel
3/ADC start0 input (ADC

1

CR register START bits
= 0x2)

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Chapter 30: LPC43xx/LPC43Sxx State Configurable Timer (SCT)

30.6 Register description
The register addresses of the State Configurable Timer are shown in Table 715. For most
of the SCT registers, the register function depends on the setting of certain other register
bits:
1. The UNIFY bit in the CONFIG register determines whether the SCT is used as one
32-bit register (for operation as one 32-bit counter/timer) or as two 16-bit
counter/timers named L and H. The setting of the UNIFY bit is reflected in the register
map:
– UNIFY = 1: Only one register is used (for operation as one 32-bit counter/timer).
– UNIFY = 0: Access the L and H registers by a 32-bit read or write operation or can
be read or written to individually (for operation as two 16-bit counter/timers).
Typically, the UNIFY bit is configured by writing to the CONFIG register before any
other registers are accessed.
2. The REGMODEn bits in the REGMODE register determine whether each set of
Match/Capture registers uses the match or capture functionality:
– REGMODEn = 0: Registers operate as match and reload registers.
– REGMODEn = 1: Registers operate as capture and capture control registers.
Table 715. Register overview: State Configurable Timer (base address 0x4000 0000)
Name

Access Address Description
offset

Reset value Reference

CONFIG

R/W

0x000

SCT configuration register

0x0000 7E00 Table 716

CTRL

R/W

0x004

SCT control register

0x0004 0004 Table 717

CTRL_L

R/W

0x004

SCT control register low counter 16-bit

0x0004 0004 Table 717

CTRL_H

R/W

0x006

SCT control register high counter 16-bit

0x0004 0004 Table 717

LIMIT

R/W

0x008

SCT limit register

0x0000 0000 Table 718

LIMIT_L

R/W

0x008

SCT limit register low counter 16-bit

0x0000 0000 Table 718

LIMIT_H

R/W

0x00A

SCT limit register high counter 16-bit

0x0000 0000 Table 718

HALT

R/W

0x00C

SCT halt condition register

0x0000 0000 Table 719

HALT_L

R/W

0x00C

SCT halt condition register low counter 16-bit

0x0000 0000 Table 719

HALT_H

R/W

0x00E

SCT halt condition register high counter 16-bit

0x0000 0000 Table 719

STOP

R/W

0x010

SCT stop condition register

0x0000 0000 Table 720

STOP_L

R/W

0x010

SCT stop condition register low counter 16-bit

0x0000 0000 Table 720

STOP_H

R/W

0x012

SCT stop condition register high counter 16-bit

0x0000 0000 Table 720

START

R/W

0x014

SCT start condition register

0x0000 0000 Table 721

START_L

R/W

0x014

SCT start condition register low counter 16-bit

0x0000 0000 Table 721

START_H

R/W

0x016

SCT start condition register high counter 16-bit

0x0000 0000 Table 721

-

-

0x018 0x03C

Reserved

COUNT

R/W

0x040

SCT counter register

0x0000 0000 Table 722

COUNT_L

R/W

0x040

SCT counter register low counter 16-bit

0x0000 0000 Table 722

-

COUNT_H

R/W

0x042

SCT counter register high counter 16-bit

0x0000 0000 Table 722

STATE

R/W

0x044

SCT state register

0x0000 0000 Table 723

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Chapter 30: LPC43xx/LPC43Sxx State Configurable Timer (SCT)

Table 715. Register overview: State Configurable Timer (base address 0x4000 0000) …continued
Name

Access Address Description
offset

Reset value Reference

STATE_L

R/W

0x0000 0000 Table 723

STATE_H

R/W

0x046

SCT state register high counter 16-bit

0x0000 0000 Table 723

INPUT

RO

0x048

SCT input register

0x0000 0000 Table 724

REGMODE

R/W

0x04C

SCT match/capture registers mode register

0x0000 0000 Table 725

REGMODE_L

R/W

0x04C

SCT match/capture registers mode register low
counter 16-bit

0x0000 0000 Table 725

REGMODE_H

R/W

0x04E

SCT match/capture registers mode register high
counter 16-bit

0x0000 0000 Table 725

OUTPUT

R/W

0x050

SCT output register

0x0000 0000 Table 726

0x044

SCT state register low counter 16-bit

OUTPUTDIRCTRL

R/W

0x054

SCT output counter direction control register

0x0000 0000 Table 727

RES

R/W

0x058

SCT conflict resolution register

0x0000 0000 Table 728

DMAREQ0

R/W

0x05C

SCT DMA request 0 register

0x0000 0000 Table 729

DMAREQ1

R/W

0x060

SCT DMA request 1 register

0x0000 0000 Table 730

-

-

0x064 0x0EC

Reserved

-

EVEN

R/W

0x0F0

SCT event enable register

0x0000 0000 Table 731

EVFLAG

R/W

0x0F4

SCT event flag register

0x0000 0000 Table 732

CONEN

R/W

0x0F8

SCT conflict enable register

0x0000 0000 Table 733

CONFLAG

R/W

0x0FC

SCT conflict flag register

0x0000 0000 Table 734

MATCH0 to
MATCH15

R/W

0x100 to SCT match value register of match channels 0 to
0x13C
15; REGMOD0 to REGMODE15 = 0

0x0000 0000 Table 734

MATCH0_L to
MATCH15_L

R/W

0x100 to SCT match value register of match channels 0 to
0x13C
15; low counter 16-bit; REGMOD0_L to
REGMODE15_L = 0

0x0000 0000 Table 734

MATCH0_H to
MATCH15_H

R/W

0x102 to SCT match value register of match channels 0 to
0x13E
15; high counter 16-bit; REGMOD0_H to
REGMODE15_H = 0

0x0000 0000 Table 734

CAP0 to CAP15

0x100 to SCT capture register of capture channel 0 to 15;
0x13C
REGMOD0 to REGMODE15 = 1

0x0000 0000 Table 736

CAP0_L to CAP15_L

0x100 to SCT capture register of capture channel 0 to 15;
0x13C
low counter 16-bit; REGMOD0_L to
REGMODE15_L = 1

0x0000 0000 Table 736

CAP0_H to CAP15_H

0x102 to SCT capture register of capture channel 0 to 15;
0x13E
high counter 16-bit; REGMOD0_H to
REGMODE15_H = 1

0x0000 0000 Table 736

-

MATCH0_L to
MATCH15_L

R/W

0x180 to MATCH alias register (see Section 30.7.9). SCT
0x1A0
match value register of match channels 0 to 15;
low counter 16-bit; REGMOD0_L to
REGMODE15_L = 0

0x0000 0000 Table 734

MATCH0_H to
MATCH15_H

R/W

0x1C0 to MATCH alias register (see Section 30.7.9). SCT
0x1E0
match value register of match channels 0 to 15;
high counter 16-bit; REGMOD0_H to
REGMODE15_H = 0

0x0000 0000 Table 734

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Chapter 30: LPC43xx/LPC43Sxx State Configurable Timer (SCT)

Table 715. Register overview: State Configurable Timer (base address 0x4000 0000) …continued
Name

Access Address Description
offset

Reset value Reference

CAP0_L to CAP15_L

0x180 to CAP alias register (see Section 30.7.9). SCT
0x1A0
capture register of capture channel 0 to 15; low
counter 16-bit; REGMOD0_L to REGMODE15_L
=1

0x0000 0000 Table 736

CAP0_H to CAP15_H

0x0000 0000 Table 736
0x1C0 to CAP alias register (see Section 30.7.9). SCT
0x1E0
capture register of capture channel 0 to 15; high
counter 16-bit; REGMOD0_H to REGMODE15_H
=1

MATCHREL0 to
MATCHREL15

R/W

0x200 to SCT match reload value register 0 to 15;
0x23C
REGMOD0 = 0 to REGMODE15 = 0

0x0000 0000 Table 737

MATCHREL0_L to
MATCHREL15_L

R/W

0x200 to SCT match reload value register 0 to 15; low
0x23C
counter 16-bit; REGMOD0_L = 0 to
REGMODE15_L = 0

0x0000 0000 Table 737

MATCHREL0_H to
MATCHREL15_H

R/W

0x202 to SCT match reload value register 0 to 15; high
0x23E
counter 16-bit; REGMOD0_H = 0 to
REGMODE15_H = 0

0x0000 0000 Table 737

CAPCTRL0 to
CAPCTRL15

0x200 to SCT capture control register 0 to 15; REGMOD0
0x23C
= 1 to REGMODE15 = 1

0x0000 0000 Table 738

CAPCTRL0_L to
CAPCTRL15_L

0x200 to SCT capture control register 0 to 15; low counter
0x23C
16-bit; REGMOD0_L = 1 to REGMODE15_L = 1

0x0000 0000 Table 738

CAPCTRL0_H to
CAPCTRL15_H

0x202 to SCT capture control register 0 to 15; high counter 0x0000 0000 Table 738
0x23E
16-bit; REGMOD0 = 1 to REGMODE15 = 1

MATCHREL0_L to
MATCHREL15_L

R/W

0x280 to MATCHREL alias registers (see Section 30.7.9).
0x2A0
SCT match reload value register 0 to 15; low
counter 16-bit; REGMOD0_L = 0 to
REGMODE15_L = 0

0x0000 0000 Table 737

MATCHREL0_H to
MATCHREL15_H

R/W

0x2C0 to MATCHREL alias registers (see Section 30.7.9).
0x2E0
SCT match reload value register 0 to 15; high
counter 16-bit; REGMOD0_H = 0 to
REGMODE15_H = 0

0x0000 0000 Table 737

CAPCTRL0_L to
CAPCTRL15_L

0x280 to CAPCTRL alias registers (see Section 30.7.9).
0x2A0
SCT capture control register 0 to 15; low counter
16-bit; REGMOD0_L = 1 to REGMODE15_L = 1

0x0000 0000 Table 738

CAPCTRL0_H to
CAPCTRL15_H

0x2C0 to CAPCTRL alias registers (see Section 30.7.9).
0x0000 0000 Table 738
0x2E0
SCT capture control register 0 to 15; high counter
16-bit; REGMOD0 = 1 to REGMODE15 = 1

EVSTATEMSK0

R/W

0x300

SCT event state register 0

0x0000 0000 Table 739

EVCTRL0

R/W

0x304

SCT event control register 0

0x0000 0000 Table 740

EVSTATEMSK1

R/W

0x308

SCT event state register 1

0x0000 0000 Table 739

EVCTRL1

R/W

0x30C

SCT event control register 1

0x0000 0000 Table 740

EVSTATEMSK2

R/W

0x310

SCT event state register 2

0x0000 0000 Table 739

EVCTRL2

R/W

0x314

SCT event control register 2

0x0000 0000 Table 740

EVSTATEMSK3

R/W

0x318

SCT event state register 3

0x0000 0000 Table 739

EVCTRL3

R/W

0x31C

SCT event control register 3

0x0000 0000 Table 740

EVSTATEMSK4

R/W

0x320

SCT event state register 4

0x0000 0000 Table 739

EVCTRL4

R/W

0x324

SCT event control register4

0x0000 0000 Table 740

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Chapter 30: LPC43xx/LPC43Sxx State Configurable Timer (SCT)

Table 715. Register overview: State Configurable Timer (base address 0x4000 0000) …continued
Name

Access Address Description
offset

Reset value Reference

EVSTATEMSK5

R/W

SCT event state register 5

0x0000 0000 Table 739

0x328

EVCTRL5

R/W

0x32C

SCT event control register 5

0x0000 0000 Table 740

EVSTATEMSK6

R/W

0x330

SCT event state register 6

0x0000 0000 Table 739

EVCTRL6

R/W

0x334

SCT event control register 6

0x0000 0000 Table 740

EVSTATEMSK7

R/W

0x338

SCT event state register 7

0x0000 0000 Table 739

EVCTRL7

R/W

0x33C

SCT event control register 7

0x0000 0000 Table 740

EVSTATEMSK8

R/W

0x340

SCT event state register 8

0x0000 0000 Table 739

EVCTRL8

R/W

0x344

SCT event control register 8

0x0000 0000 Table 740

EVSTATEMSK9

R/W

0x348

SCT event state register 9

0x0000 0000 Table 739

EVCTRL9

R/W

0x34C

SCT event control register 9

0x0000 0000 Table 740

EVSTATEMSK10

R/W

0x350

SCT event state register 10

0x0000 0000 Table 739

EVCTRL10

R/W

0x354

SCT event control register 10

0x0000 0000 Table 740

EVSTATEMSK11

R/W

0x358

SCT event state register 11

0x0000 0000 Table 739

EVCTRL11

R/W

0x35C

SCT event control register 11

0x0000 0000 Table 740

EVSTATEMSK12

R/W

0x360

SCT event state register 12

0x0000 0000 Table 739

EVCTRL12

R/W

0x364

SCT event control register 12

0x0000 0000 Table 740

EVSTATEMSK13

R/W

0x368

SCT event state register 13

0x0000 0000 Table 739

EVCTRL13

R/W

0x36C

SCT event control register 13

0x0000 0000 Table 740

EVSTATEMSK14

R/W

0x370

SCT event state register 14

0x0000 0000 Table 739

EVCTRL14

R/W

0x374

SCT event control register 14

0x0000 0000 Table 740

EVSTATEMSK15

R/W

0x378

SCT event state register 15

0x0000 0000 Table 739

EVCTRL15

R/W

0x37C

SCT event control register 15

0x0000 0000 Table 740

OUTPUTSET0

R/W

0x500

SCT output 0 set register

0x0000 0000 Table 741

OUTPUTCL0

R/W

0x504

SCT output 0 clear register

0x0000 0000 Table 742

OUTPUTSET1

R/W

0x508

SCT output 1 set register

0x0000 0000 Table 741

OUTPUTCL1

R/W

0x50C

SCT output 1 clear register

0x0000 0000 Table 742

OUTPUTSET2

R/W

0x510

SCT output 2 set register

0x0000 0000 Table 741

OUTPUTCL2

R/W

0x514

SCT output 2 clear register

0x0000 0000 Table 742

OUTPUTSET3

R/W

0x518

SCT output 3 set register

0x0000 0000 Table 741

OUTPUTCL3

R/W

0x51C

SCT output 3 clear register

0x0000 0000 Table 742

OUTPUTSET4

R/W

0x520

SCT output 4 set register

0x0000 0000 Table 741

OUTPUTCL4

R/W

0x524

SCT output 4 clear register

0x0000 0000 Table 742

OUTPUTSET5

R/W

0x528

SCT output 5 set register

0x0000 0000 Table 741

OUTPUTCL5

R/W

0x52C

SCT output 5 clear register

0x0000 0000 Table 742

OUTPUTSET6

R/W

0x530

SCT output 6 set register

0x0000 0000 Table 741

OUTPUTCL6

R/W

0x534

SCT output 6 clear register

0x0000 0000 Table 742

OUTPUTSET7

R/W

0x538

SCT output 7 set register

0x0000 0000 Table 741

OUTPUTCL7

R/W

0x53C

SCT output 7 clear register

0x0000 0000 Table 742

OUTPUTSET8

R/W

0x540

SCT output 8 set register

0x0000 0000 Table 741

OUTPUTCL8

R/W

0x544

SCT output 8 clear register

0x0000 0000 Table 742

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Chapter 30: LPC43xx/LPC43Sxx State Configurable Timer (SCT)

Table 715. Register overview: State Configurable Timer (base address 0x4000 0000) …continued
Name

Access Address Description
offset

Reset value Reference

OUTPUTSET9

R/W

SCT output 9 set register

0x0000 0000 Table 741

0x548

OUTPUTCL9

R/W

0x54C

SCT output 9 clear register

0x0000 0000 Table 742

OUTPUTSET10

R/W

0x550

SCT output 10 set register

0x0000 0000 Table 741

OUTPUTCL10

R/W

0x554

SCT output 10 clear register

0x0000 0000 Table 742

OUTPUTSET11

R/W

0x558

SCT output 11 set register

0x0000 0000 Table 741

OUTPUTCL11

R/W

0x55C

SCT output 11 clear register

0x0000 0000 Table 742

OUTPUTSET12

R/W

0x560

SCT output 12 set register

0x0000 0000 Table 741

OUTPUTCL12

R/W

0x564

SCT output 12 clear register

0x0000 0000 Table 742

OUTPUTSET13

R/W

0x568

SCT output 13 set register

0x0000 0000 Table 741

OUTPUTCL13

R/W

0x56C

SCT output 13 clear register

0x0000 0000 Table 742

OUTPUTSET14

R/W

0x570

SCT output 14 set register

0x0000 0000 Table 741

OUTPUTCL14

R/W

0x574

SCT output 14 clear register

0x0000 0000 Table 742

OUTPUTSET15

R/W

0x578

SCT output 15 set register

0x0000 0000 Table 741

OUTPUTCL15

R/W

0x57C

SCT output 15 clear register

0x0000 0000 Table 742

30.6.1 SCT configuration register
This register configures the overall operation of the SCT. Write to this register before any
other registers.
Table 716. SCT configuration register (CONFIG - address 0x4000 0000) bit description
Bit

Symbol

0

UNIFY

2:1

Value

User manual

Reset
value

SCT operation

0

0

The SCT operates as two 16-bit counters named L and H.

1

The SCT operates as a unified 32-bit counter.

CLKMODE

UM10503

Description

SCT clock mode

00

0x0

The bus clock clocks the SCT and prescalers.

0x1

The SCT clock is the bus clock, but the prescalers are enabled to count only
when sampling of the input selected by the CKSEL field finds the selected
edge. The minimum pulse width on the clock input is 1 bus clock period. This
mode is the high-performance sampled-clock mode.

0x2

The input selected by CKSEL clocks the SCT and prescalers. The input is
synchronized to the bus clock and possibly inverted. The minimum pulse width
on the clock input is 1 bus clock period. This mode is the low-power
sampled-clock mode.

0x3

Reserved.

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Chapter 30: LPC43xx/LPC43Sxx State Configurable Timer (SCT)

Table 716. SCT configuration register (CONFIG - address 0x4000 0000) bit description …continued
Bit

Symbol

6:3

CLSEL

Value

Description

Reset
value

SCT clock select

0000

0x0

Rising edges on input 0.

0x1

Falling edges on input 0.

0x2

Rising edges on input 1.

0x3

Falling edges on input 1.

0x4

Rising edges on input 2.

0x5

Falling edges on input 2.

0x6

Rising edges on input 3.

0x7

Falling edges on input 3.

0x8

Rising edges on input 4.

0x9

Falling edges on input 4.

0xA

Rising edges on input 5.

0xB

Falling edges on input 5.

0xC

Rising edges on input 6.

0xD

Falling edges on input 6.

0xE

Rising edges on input 7.

0xF

Falling edges on input 7.

7

NORELAOD_L

-

A 1 in this bit prevents the lower match registers from being reloaded from their 0
respective reload registers. Software can write to set or clear this bit at any
time. This bit applies to both the higher and lower registers when the UNIFY bit
is set.

8

NORELOAD_H

-

A 1 in this bit prevents the higher match registers from being reloaded from their 0
respective reload registers. Software can write to set or clear this bit at any
time. This bit is not used when the UNIFY bit is set.

16:9

INSYNCn

-

Synchronization for input n (bit 9 = input 0, bit 10 = input 1,..., bit 16 = input 7). A 1
1 in one of these bits subjects the corresponding input to synchronization to the
SCT clock, before it is used to create an event. If an input is synchronous to the
SCT clock, keep its bit 0 for faster response.
When the CKMODE field is 1x, the bit in this field, corresponding to the input
selected by the CKSEL field, is not used.

31:17

-

Reserved

-

30.6.2 SCT control register
If UNIFY = 1 in the CONFIG register, only the _L bits are used.
If UNIFY = 0 in the CONFIG register, this register can be written to as two registers
CTRL_L and CTRL_H. Both the L and H registers can be read or written individually or in
a single 32-bit read or write operation.
All bits in this register can be written to when the counter is stopped or halted. When the
counter is running, the only bits that can be written are STOP or HALT.(Other bits can be
written in a subsequent write after HALT is set to 1.)

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Chapter 30: LPC43xx/LPC43Sxx State Configurable Timer (SCT)

Table 717. SCT control register (CTRL - address 0x4000 0004) bit description
Bit

Symbol

Value Description

Reset
value

0

DOWN_L

-

This bit is 1 when the L or unified counter is counting down. Hardware sets this bit
when the counter limit is reached and BIDIR is 1. Hardware clears this bit when the
counter reaches 0.

0

1

STOP_L

-

When this bit is 1 and HALT is 0, the L or unified counter does not run but I/O events 0
related to the counter can occur. If such an event matches the mask in the Start
register, this bit is cleared and counting resumes.

2

HALT_L

-

When this bit is 1, the L or unified counter does not run and no events can occur. A
reset sets this bit. When the HALT_L bit is one, the STOP_L bit is cleared. If you
want to remove the halt condition and keep the SCT in the stop condition (not
running), then you can change the halt and stop condition with one single write to
this register.

1

Remark: Once set, only software can clear this bit to restore counter operation.

3

CLRCTR_L -

Writing a 1 to this bit clears the L or unified counter. This bit always reads as 0.

0

4

BIDIR_L

L or unified counter direction select

0

12:5

PRE_L

0

The counter counts up to its limit condition, then is cleared to zero.

1

The counter counts up to its limit, then counts down to 0.

-

Specifies the factor by which the SCT clock is prescaled to produce the L or unified
counter clock. The counter clock is clocked at the rate of the SCT clock divided by
PRE_L+1.

0

Remark: Clear the counter (by writing a 1 to the CLRCTR bit) whenever changing
the PRE value.

15:13

-

16

DOWN_H

-

Reserved
This bit is 1 when the H counter is counting down. Hardware sets this bit when the
counter limit is reached and BIDIR is 1. Hardware clears this bit when the counter
reaches 0.

17

STOP_H

-

When this bit is 1 and HALT is 0, the H counter does not run but I/O events related to 0
the counter can occur. If such an event matches the mask in the Start register, this bit
is cleared and counting resumes.

18

HALT_H

-

When this bit is 1, the H counter does not run and no events can occur. A reset sets 1
this bit. When the HALT_H bit is one, the STOP_H bit is cleared. If you want to
remove the halt condition and keep the SCT in the stop condition (not running), then
you can change the halt and stop condition with one single write to this register.

0

Remark: Once set, this bit can only be cleared by software to restore counter
operation.

19

CLRCTR_H -

Writing a 1 to this bit clears the H counter. This bit always reads as 0.

0

20

BIDIR_H

Direction select

0

28:21

PRE_H

0

The H counter counts up to its limit condition, then is cleared to zero.

1

The H counter counts up to its limit, then counts down to 0.

-

Specifies the factor by which the SCT clock is prescaled to produce the H counter
0
clock. The counter clock is clocked at the rate of the SCT clock divided by PRELH+1.
Remark: Clear the counter (by writing a 1 to the CLRCTR bit) whenever changing
the PRE value.

31:29

-

Reserved

30.6.3 SCT limit register
If UNIFY = 1 in the CONFIG register, only the _L bits are used.
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Chapter 30: LPC43xx/LPC43Sxx State Configurable Timer (SCT)

If UNIFY = 0 in the CONFIG register, this register can be written to as two registers
LIMIT_L and LIMIT_H. Both the L and H registers can be read or written individually or in
a single 32-bit read or write operation.
The bits in this register set which events act as counter limits. When a limit event occurs,
the counter is cleared to zero in unidirectional mode or begins counting down in
bidirectional mode. When the counter reaches all ones, this state is always treated as a
limit event, and the counter is cleared in unidirectional mode or, in bidirectional mode,
begins counting down on the next clock edge - even if no limit event as defined by the
SCT limit register has occurred.
Table 718. SCT limit register (LIMIT - address 0x4000 0008) bit description
Bit

Symbol

Description

Reset
value

15:0

LIMMSK_L

If bit n is one, event n is used as a counter limit for the L or
unified counter (event 0 = bit 0, event 1 = bit 1, event 15 =
bit 15).

0

31:16

LIMMSK_H

If bit n is one, event n is used as a counter limit for the H
counter (event 0 = bit 16, event 1 = bit 17, event 15 = bit
31).

0

30.6.4 SCT halt condition register
If UNIFY = 1 in the CONFIG register, only the _L bits are used.
If UNIFY = 0 in the CONFIG register, this register can be written to as two registers
HALT_L and HALT_H. Both the L and H registers can be read or written individually or in a
single 32-bit read or write operation.
Remark: Any event halting the counter disables its operation until software clears the
HALT bit (or bits) in the CTRL register (Table 717).
Table 719. SCT halt condition register (HALT - address 0x4000 000C) bit description
Bit

Symbol

Description

Reset
value

15:0

HALTMSK_L

If bit n is one, event n sets the HALT_L bit in the CTRL register 0
(event 0 = bit 0, event 1 = bit 1, event 15 = bit 15).

31:16 HALTMSK_H

If bit n is one, event n sets the HALT_H bit in the CTRL register 0
(event 0 = bit 16, event 1 = bit 17, event 15 = bit 31).

30.6.5 SCT stop condition register
If UNIFY = 1 in the CONFIG register, only the _L bits are used.
If UNIFY = 0 in the CONFIG register, this register can be written to as two registers
STOPT_L and STOP_H. Both the L and H registers can be read or written individually or
in a single 32-bit read or write operation.

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Chapter 30: LPC43xx/LPC43Sxx State Configurable Timer (SCT)

Table 720. SCT stop condition register (STOP - address 0x4000 0010) bit description
Bit

Symbol

Description

Reset
value

15:0

STOPMSK_L

If bit n is one, event n sets the STOP_L bit in the CTRL register
(event 0 = bit 0, event 1 = bit 1, event 15 = bit 15).

0

31:16 STOPMSK_H

If bit n is one, event n sets the STOP_H bit in the CTRL register 0
(event 0 = bit 16, event 1 = bit 17, event 15 = bit 31).

30.6.6 SCT start condition register
If UNIFY = 1 in the CONFIG register, only the _L bits are used.
If UNIFY = 0 in the CONFIG register, this register can be written to as two registers
START_L and START_H. Both the L and H registers can be read or written individually or
in a single 32-bit read or write operation.
The bits in this register select which events, if any, clear the STOP bit in the Control
register. (Since no events can occur when HALT is 1, only software can clear the HALT bit
by writing the Control register.)
Table 721. SCT start condition register (START - address 0x4000 0014) bit description
Bit

Symbol

Description

Reset
value

15:0

STARTMSK_L

If bit n is one, event n clears the STOP_L bit in the CTRL
register (event 0 = bit 0, event 1 = bit 1, event 15 = bit 15).

0

If bit n is one, event n clears the STOP_H bit in the CTRL
register (event 0 = bit 16, event 1 = bit 17, event 15 = bit 31).

0

31:16 STARTMSK_H

30.6.7 SCT counter register
If UNIFY = 1 in the CONFIG register, the counter is a unified 32-bit register and both the
_L and _H bits are used.
If UNIFY = 0 in the CONFIG register, this register can be written to as two registers
COUNT_L and COUNT_H. Both the L and H registers can be read or written individually
or in a single 32-bit read or write operation. In this case, the L and H registers count
independently under the control of the other registers.
Attempting to write a counter while it is running does not affect the counter but produces a
bus error. Software can read the counter registers at any time.
Table 722. SCT counter register (COUNT - address 0x4000 0040) bit description
Bit

Symbol

Description

Reset
value

15:0

CTR_L

When UNIFY = 0, read or write the 16-bit L counter value. When
UNIFY = 1, read or write the lower 16 bits of the 32-bit unified
counter.

0

31:16

CTR_H

When UNIFY = 0, read or write the 16-bit H counter value. When
UNIFY = 1, read or write the upper 16 bits of the 32-bit unified
counter.

0

30.6.8 SCT state register
If UNIFY = 1 in the CONFIG register, only the _L bits are used.
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Chapter 30: LPC43xx/LPC43Sxx State Configurable Timer (SCT)

If UNIFY = 0 in the CONFIG register, this register can be written to as two registers
STATE_L and STATE_H. Both the L and H registers can be read or written individually or
in a single 32-bit read or write operation.
Software can read the state associated with a counter at any time. Writing the state is only
allowed when the counter HALT bit is 1; when HALT is 0, a write attempt does not change
the state and results in a bus error.
The state variable is the main feature that distinguishes the SCT from other counter/timer/
PWM blocks. Events can be made to occur only in certain states. Events, in turn, can
perform the following actions:

•
•
•
•

set and clear outputs
limit, stop, and start the counter
cause interrupts and DMA requests
modify the state variable

The value of a state variable is completely under the control of the application. If an
application does not use states, the value of the state variable remains zero, which is the
default value.
A state variable can be used to track and control multiple cycles of the associated counter
in any desired operational sequence. The state variable is logically associated with a state
machine diagram which represents the SCT configuration. See Section 30.6.23 and
30.6.24 for more about the relationship between states and events.
The STATELD/STADEV fields in the event control registers of all defined events set all
possible values for the state variable. The change of the state variable during multiple
counter cycles reflects how the associated state machine moves from one state to the
next.
Table 723. SCT state register (STATE - address 0x4000 0044) bit description
Bit

Symbol

Description

Reset
value

4:0

STATE_L

State variable.

0

15:5

-

Reserved.

-

20:16

STATE_H

State variable.

0

31:21

-

Reserved.

30.6.9 SCT input register
Software can read the state of the SCT inputs in this read-only register in two slightly
different forms. The only situation in which these values are different is if CLKMODE = 2 in
the CONFIG register.
Table 724. SCT input register (INPUT - address 0x4000 0048) bit description

UM10503

User manual

Bit

Symbol

Description

Reset
value

0

AIN0

Real-time status of input 0.

pin

1

AIN1

Real-time status of input 1.

pin

2

AIN2

Real-time status of input 2.

pin

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Chapter 30: LPC43xx/LPC43Sxx State Configurable Timer (SCT)

Table 724. SCT input register (INPUT - address 0x4000 0048) bit description
Bit

Symbol

Description

Reset
value

3

AIN3

Real-time status of input 3.

pin

4

AIN4

Real-time status of input 4.

pin

5

AIN5

Real-time status of input 5.

pin

6

AIN6

Real-time status of input 6.

pin

7

AIN7

Real-time status of input 7.

pin

15:8

-

Reserved.

-

16

SIN0

Input 0 state synchronized to the SCT clock.

-

17

SIN1

Input 1 state synchronized to the SCT clock.

-

18

SIN2

Input 2 state synchronized to the SCT clock.

-

19

SIN3

Input 3 state synchronized to the SCT clock.

-

20

SIN4

Input 4 state synchronized to the SCT clock.

-

21

SIN5

Input 5 state synchronized to the SCT clock.

-

22

SIN6

Input 6 state synchronized to the SCT clock.

-

23

SIN7

Input 7 state synchronized to the SCT clock.

-

31:24

-

Reserved

-

30.6.10 SCT match/capture registers mode register
If UNIFY = 1 in the CONFIG register, only the _L bits of this register are used. The L bits
control whether each set of match/capture registers operates as unified 32-bit
capture/match registers.
If UNIFY = 0 in the CONFIG register, this register can be written to as two registers
REGMODE_L and REGMODE_H. Both the L and H registers can be read or written
individually or in a single 32-bit read or write operation.The _L bits/registers control the L
match/capture registers, and the _H bits/registers control the H match/capture registers.
The SCT contains 16 Match/Capture register pairs. The Register Mode register selects
whether each register pair acts as a Match register (see Section 30.6.19) or as a Capture
register (see Section 30.6.20). Each Match/Capture register has an accompanying
register which serves as a Reload register when the register is used as a Match register
(Section 30.6.21) or as a Capture-Control register when the register is used as a capture
register (Section 30.6.22). REGMODE_H is used only when the UNIFY bit is 0.
An alternate addressing mode is available for all of the Match/Capture and
Reload/Capture-Control registers, for DMA access to halfword registers when UNIFY=0.
This mode is described in Section 30.7.9.

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Chapter 30: LPC43xx/LPC43Sxx State Configurable Timer (SCT)

Table 725. SCT match/capture registers mode register (REGMODE - address 0x4000 004C)
bit description
Bit

Symbol

Description

Reset
value

15:0

REGMOD_L

Each bit controls one pair of match/capture registers (register 0 =
bit 0, register 1 = bit 1,..., register 15 = bit 15).

0

0 = registers operate as match registers.
1 = registers operate as capture registers.
31:16 REGMOD_H

Each bit controls one pair of match/capture registers (register 0 =
bit 16, register 1 = bit 17,..., register 15 = bit 31).

0

0 = registers operate as match registers.
1 = registers operate as capture registers.

30.6.11 SCT output register
The SCT supports 16 outputs, each of which has a corresponding bit in this register.
Software can write to any of the output registers when both counters are halted to control
the outputs directly. Writing to this register when either counter is stopped or running does
not affect the outputs and results in an bus error.
Software can read this register at any time to sense the state of the outputs.
Table 726. SCT output register (OUTPUT - address 0x4000 0050) bit description
Bit

Symbol

Description

Reset
value

15:0

OUT

Writing a 1 to bit n makes the corresponding output HIGH. 0 makes 0
the corresponding output LOW (output 0 = bit 0, output 1 = bit 1,...,
output 15 = bit 15).

31:16

-

Reserved

30.6.12 SCT bidirectional output control register
This register specifies (for each output) the impact of the counting direction on the
meaning of set and clear operations on the output (see Section 30.6.25 and
Section 30.6.26).
Table 727. SCT bidirectional output control register (OUTPUTDIRCTRL - address 0x4000 0054) bit description
Bit

Symbol

1:0

SETCLR0

3:2

Value Description

Set/clear operation on output 0. Value 0x3 is reserved. Do not program this value.

User manual

0

0x0

Set and clear do not depend on any counter.

0x1

Set and clear are reversed when counter L or the unified counter is counting down.

0x2

Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.

SETCLR1

UM10503

Reset
value

Set/clear operation on output 1. Value 0x3 is reserved. Do not program this value.

0

0x0

Set and clear do not depend on any counter.

0x1

Set and clear are reversed when counter L or the unified counter is counting down.

0x2

Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.

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Chapter 30: LPC43xx/LPC43Sxx State Configurable Timer (SCT)

Table 727. SCT bidirectional output control register (OUTPUTDIRCTRL - address 0x4000 0054) bit description
Bit

Symbol

5:4

SETCLR2

7:6

9:8

11:
10

13:
12

15:
14

17:
16

19:
18

21:
20

23:
22

Value Description

Set/clear operation on output 2. Value 0x3 is reserved. Do not program this value.
Set and clear do not depend on any counter.

0x1

Set and clear are reversed when counter L or the unified counter is counting down.

0x2

Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
Set/clear operation on output 3. Value 0x3 is reserved. Do not program this value.

0

0x0

Set and clear do not depend on any counter.

0x1

Set and clear are reversed when counter L or the unified counter is counting down.

0x2

Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.

SETCLR4

Set/clear operation on output 4. Value 0x3 is reserved. Do not program this value.

0

0x0

Set and clear do not depend on any counter.

0x1

Set and clear are reversed when counter L or the unified counter is counting down.

0x2

Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.

SETCLR5

Set/clear operation on output 5. Value 0x3 is reserved. Do not program this value.

0

0x0

Set and clear do not depend on any counter.

0x1

Set and clear are reversed when counter L or the unified counter is counting down.

0x2

Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.

SETCLR6

Set/clear operation on output 6. Value 0x3 is reserved. Do not program this value.

0

0x0

Set and clear do not depend on any counter.

0x1

Set and clear are reversed when counter L or the unified counter is counting down.

0x2

Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.

SETCLR7

Set/clear operation on output 7. Value 0x3 is reserved. Do not program this value.

0

0x0

Set and clear do not depend on any counter.

0x1

Set and clear are reversed when counter L or the unified counter is counting down.

0x2

Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.

SETCLR8

Set/clear operation on output 8. Value 0x3 is reserved. Do not program this value.

0

0x0

Set and clear do not depend on any counter.

0x1

Set and clear are reversed when counter L or the unified counter is counting down.

0x2

Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.

SETCLR9

Set/clear operation on output 9. Value 0x3 is reserved. Do not program this value.

0

0x0

Set and clear do not depend on any counter.

0x1

Set and clear are reversed when counter L or the unified counter is counting down.

0x2

Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.

SETCLR10

Set/clear operation on output 5. Value 0x3 is reserved. Do not program this value.

0

0x0

Set and clear do not depend on any counter.

0x1

Set and clear are reversed when counter L or the unified counter is counting down.

0x2

Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.

SETCLR11

User manual

0

0x0

SETCLR3

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Reset
value

Set/clear operation on output 11. Value 0x3 is reserved. Do not program this value.

0

0x0

Set and clear do not depend on any counter.

0x1

Set and clear are reversed when counter L or the unified counter is counting down.

0x2

Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
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Chapter 30: LPC43xx/LPC43Sxx State Configurable Timer (SCT)

Table 727. SCT bidirectional output control register (OUTPUTDIRCTRL - address 0x4000 0054) bit description
Bit

Symbol

25:
24

SETCLR12

27:
26

29:
28

31:
30

Value Description

Reset
value

Set/clear operation on output 12. Value 0x3 is reserved. Do not program this value.

0

0x0

Set and clear do not depend on any counter.

0x1

Set and clear are reversed when counter L or the unified counter is counting down.

0x2

Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.

SETCLR13

Set/clear operation on output 13. Value 0x3 is reserved. Do not program this value.

0

0x0

Set and clear do not depend on any counter.

0x1

Set and clear are reversed when counter L or the unified counter is counting down.

0x2

Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.

SETCLR14

Set/clear operation on output 14. Value 0x3 is reserved. Do not program this value.

0

0x0

Set and clear do not depend on any counter.

0x1

Set and clear are reversed when counter L or the unified counter is counting down.

0x2

Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.

SETCLR15

Set/clear operation on output 15. Value 0x3 is reserved. Do not program this value.

0

0x0

Set and clear do not depend on any counter.

0x1

Set and clear are reversed when counter L or the unified counter is counting down.

0x2

Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.

30.6.13 SCT conflict resolution register
The registers OUTPUTSETn (Section 30.6.25) and OUTPUTCLn (Section 30.6.26) allow
both setting and clearing to be indicated for an output in the same clock cycle, even for the
same event. This SCT conflict resolution register resolves this conflict.
To enable an event to toggle an output, set the OnRES value to 0x3 in this register, and
set the event bits in both the Set and Clear registers.
Table 728. SCT conflict resolution register (RES - address 0x4000 0058) bit description
Bit

Symbol

1:0

O0RES

Value Description

Effect of simultaneous set and clear on output 0.
0x0

No change.

0x1

Set output (or clear based on the SETCLR0 field).

0x2

Clear output (or set based on the SETCLR0 field).

0x3
3:2

UM10503

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O1RES

Reset
value

0

Toggle output.
Effect of simultaneous set and clear on output 1.

0x0

No change.

0x1

Set output (or clear based on the SETCLR1 field).

0x2

Clear output (or set based on the SETCLR1 field).

0x3

Toggle output.

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Chapter 30: LPC43xx/LPC43Sxx State Configurable Timer (SCT)

Table 728. SCT conflict resolution register (RES - address 0x4000 0058) bit description
Bit

Symbol

5:4

O2RES

7:6

Value Description

Effect of simultaneous set and clear on output 2.

11:
10

13:
12

15:
14

No change.

0x1

Set output (or clear based on the SETCLR2 field).

0x2

Clear output n (or set based on the SETCLR2 field).

0x3

Toggle output.

0x0

No change.

0x1

Set output (or clear based on the SETCLR3 field).

0x2

Clear output (or set based on the SETCLR3 field).

O3RES

Effect of simultaneous set and clear on output 3.

O4RES
0x0

No change.

0x1

Set output (or clear based on the SETCLR4 field).

0x2

Clear output (or set based on the SETCLR4 field).

0x3

Toggle output.

O5RES

Effect of simultaneous set and clear on output 5.
0x0

No change.

0x1

Set output (or clear based on the SETCLR5 field).

0x2

Clear output (or set based on the SETCLR5 field).

0x3

Toggle output.

O6RES

Effect of simultaneous set and clear on output 6.
0x0

No change.

0x1

Set output (or clear based on the SETCLR6 field).

0x2

Clear output (or set based on the SETCLR6 field).

0x3

Toggle output.

O7RES

Effect of simultaneous set and clear on output 7.
0x0

No change.

0x1

Set output (or clear based on the SETCLR7 field).

0x2

Clear output (or set based on the SETCLR7 field).

19:
18

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O8RES

0

0

0

0

Toggle output.
Effect of simultaneous set and clear on output 8.

0x0

No change.

0x1

Set output (or clear based on the SETCLR8 field).

0x2

Clear output (or set based on the SETCLR8 field).

0x3

Toggle output.

O9RES

0

Toggle output.
Effect of simultaneous set and clear on output 4.

0x3
17:
16

0

0x0

0x3
9:8

Reset
value

Effect of simultaneous set and clear on output 9.
0x0

No change.

0x1

Set output (or clear based on the SETCLR9 field).

0x2

Clear output (or set based on the SETCLR9 field).

0x3

Toggle output.

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Chapter 30: LPC43xx/LPC43Sxx State Configurable Timer (SCT)

Table 728. SCT conflict resolution register (RES - address 0x4000 0058) bit description
Bit

Symbol

21:
20

O10RES

23:
22

Value Description

Effect of simultaneous set and clear on output 10.

27:
26

29:
28

31:
30

0

0x0

No change.

0x1

Set output (or clear based on the SETCLR10 field).

0x2

Clear output (or set based on the SETCLR10 field).

0x3

Toggle output.

O11RES

Effect of simultaneous set and clear on output 11.

0

0x0

No change.

0x1

Set output (or clear based on the SETCLR11 field).

0x2

Clear output (or set based on the SETCLR11 field).

0x3
25:
24

Reset
value

O12RES

Toggle output.
Effect of simultaneous set and clear on output 12.

0

0x0

No change.

0x1

Set output (or clear based on the SETCLR12 field).

0x2

Clear output (or set based on the SETCLR12 field).

0x3

Toggle output.

O13RES

Effect of simultaneous set and clear on output 13.
0x0

0

No change.

0x1

Set output (or clear based on the SETCLR13 field).

0x2

Clear output (or set based on the SETCLR13 field).

0x3

Toggle output.

O14RES

Effect of simultaneous set and clear on output 14.

0

0x0

No change.

0x1

Set output (or clear based on the SETCLR14 field).

0x2

Clear output (or set based on the SETCLR14 field).

0x3

Toggle output.

O15RES

Effect of simultaneous set and clear on output 15.

0

0x0

No change.

0x1

Set output (or clear based on the SETCLR15 field).

0x2

Clear output (or set based on the SETCLR15 field).

0x3

Toggle output.

30.6.14 SCT DMA request 0 and 1 registers
The SCT includes two DMA request outputs. These registers enable the DMA requests to
be triggered when a particular event occurs or when counter Match registers are loaded
from its Reload registers.

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Chapter 30: LPC43xx/LPC43Sxx State Configurable Timer (SCT)

Table 729. SCT DMA 0 request register (DMAREQ0 - address 0x4000 005C) bit description
Bit

Symbol

Description

Reset
value

15:0

DEV_0

If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 0
1 = bit 1,..., event 15 = bit 15).

29:16

-

Reserved

30

DRL0

A 1 in this bit makes the SCT set DMA request 0 when it loads
the Match_L/Unified registers from the Reload_L/Unified
registers.

31

DRQ0

This read-only bit indicates the state of DMA Request 0

-

Table 730. SCT DMA 1 request register (DMAREQ1 - address 0x4000 0060) bit description
Bit

Symbol

Description

Reset
value

15:0

DEV_1

If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 0
1 = bit 1,..., event 15 = bit 15).

29:16

-

Reserved

30

DRL1

A 1 in this bit makes the SCT set DMA request 1 when it loads
the Match L/Unified registers from the Reload L/Unified
registers.

31

DRQ1

This read-only bit indicates the state of DMA Request 1.

-

30.6.15 SCT flag enable register
This register enables flags to request an interrupt if the FLAGn bit in the SCT event flag
register (Section 30.6.16) is also set.
Table 731. SCT flag enable register (EVEN - address 0x4000 00F0) bit description
Bit

Symbol

Description

Reset
value

15:0

IEN

The SCT requests interrupt when bit n of this register and the event 0
flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event
15 = bit 15).

31:16

-

Reserved

30.6.16 SCT event flag register
This register records events. Writing ones to this register clears the corresponding flags
and negates the SCT interrupt request if all enabled Flag bits are zero.
Table 732. SCT event flag register (EVFLAG - address 0x4000 00F4) bit description
Bit

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Symbol

Description

Reset
value

15:0 FLAG

Bit n is one if event n has occurred since reset or a 1 was last written to
this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15).

0

31:
16

Reserved

-

-

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Chapter 30: LPC43xx/LPC43Sxx State Configurable Timer (SCT)

30.6.17 SCT conflict enable register
This register enables the “no change conflict” events specified in the SCT conflict
resolution register to request an IRQ.
Table 733. SCT conflict enable register (CONEN - address 0x4000 00F8) bit description
Bit

Symbol

Description

Reset
value

15:0

NCEN

The SCT requests interrupt when bit n of this register and the SCT 0
conflict flag register are both one (output 0 = bit 0, output 1 = bit
1,..., output 15 = bit 15).

31:16

-

Reserved

30.6.18 SCT conflict flag register
This register records interrupt-enabled no-change conflict events and provides details of a
bus error. Writing ones to the NCFLAG bits clears the corresponding read bits and
negates the SCT interrupt request if all enabled Flag bits are zero.
Table 734. SCT conflict flag register (CONFLAG - address 0x4000 00FC) bit description
Bit

Symbol

Description

Reset
value

15:0

NCFLAG

Bit n is one if a no-change conflict event occurred on output n
since reset or a 1 was last written to this bit (output 0 = bit 0,
output 1 = bit 1,..., output 15 = bit 15).

0

29:16

-

Reserved.

-

30

BUSERRL

The most recent bus error from this SCT involved writing CTR
L/Unified, STATE L/Unified, MATCH L/Unified, or the Output
register when the L/U counter was not halted. A word write to
certain L and H registers can be half successful and half
unsuccessful.

0

31

BUSERRH

The most recent bus error from this SCT involved writing CTR
H, STATE H, MATCH H, or the Output register when the H
counter was not halted.

0

30.6.19 SCT match registers 0 to 15 (REGMODEn bit = 0)
Match registers are compared to the counters to help create events. When the UNIFY bit
is 0, the L and H registers are independently compared to the L and H counters. When
UNIFY is 1, the L and H registers hold a 32-bit value that is compared to the unified
counter. A Match can only occur in a clock in which the counter is running (STOP and
HALT are both 0).
Match registers can be read at any time. Writing to a Match register while the associated
counter is running does not affect the Match register and results in a bus error. Match
events occur in the SCT clock in which the counter is (or would be) incremented to the
next value. When a Match event limits its counter as described in Section 30.6.3, the
value in the Match register is the last value of the counter before it is cleared to zero (or
decremented if BIDIR is 1).

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Chapter 30: LPC43xx/LPC43Sxx State Configurable Timer (SCT)

There is no “write-through” from Reload registers to Match registers. Before starting a
counter, software can write one value to the Match register used in the first cycle of the
counter and a different value to the corresponding Match Reload register used in the
second cycle.
Table 735. SCT match registers 0 to 15 (MATCH - address 0x4000 0100 (MATCH0) to 0x4000
4013C (MATCH15)) bit description (REGMODEn bit = 0)
Bit

Symbol

Description

Reset
value

15:0

MATCHn_L When UNIFY = 0, read or write the 16-bit value to be compared to
the L counter. When UNIFY = 1, read or write the lower 16 bits of
the 32-bit value to be compared to the unified counter.

0

31:16

MATCHn_H When UNIFY = 0, read or write the 16-bit value to be compared to
the H counter. When UNIFY = 1, read or write the upper 16 bits of
the 32-bit value to be compared to the unified counter.

0

30.6.20 SCT capture registers 0 to 15 (REGMODEn bit = 1)
These registers allow software to read the counter values at which the event selected by
the corresponding Capture Control registers occurred.
Table 736. SCT capture registers 0 to 15 (CAP - address 0x4000 0100 (CAP0) to 0x4000 013C
(CAP15)) bit description (REGMODEn bit = 1)
Bit

Symbol

Description

Reset
value

15:0

CAPn_L

When UNIFY = 0, read the 16-bit counter value at which this
0
register was last captured. When UNIFY = 1, read the lower 16 bits
of the 32-bit value at which this register was last captured.

31:16

CAPn_H

When UNIFY = 0, read the 16-bit counter value at which this
0
register was last captured. When UNIFY = 1, read the upper 16 bits
of the 32-bit value at which this register was last captured.

30.6.21 SCT match reload registers 0 to 15 (REGMODEn bit = 0)
A Match register (L, H, or unified 32-bit) is loaded from the corresponding Reload register
when BIDIR is 0 and the counter reaches its limit condition, or when BIDIR is 1 and the
counter reaches 0.
Table 737. SCT match reload registers 0 to 15 (MATCHREL- address 0x4000 0200
(MATCHRELOAD0) to 0x4000 023C (MATCHRELOAD15) bit description
(REGMODEn bit = 0)
Bit

Symbol

Description

Reset
value

15:0

RELOADn_L When UNIFY = 0, read or write the 16-bit value to be loaded into
the SCTMATCHn_L register. When UNIFY = 1, read or write the
lower 16 bits of the 32-bit value to be loaded into the MATCHn
register.

31:16 RELOADn_H When UNIFY = 0, read or write the 16-bit to be loaded into the
MATCHn_H register. When UNIFY = 1, read or write the upper 16
bits of the 32-bit value to be loaded into the MATCHn register.

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30.6.22 SCT capture control registers 0 to 15 (REGMODEn bit = 1)
If UNIFY = 1 in the CONFIG register, only the _L bits are used.
If UNIFY = 0 in the CONFIG register, this register can be written to as two registers
CAPCTRLn_L and CAPCTRLn_H. Both the L and H registers can be read or written
individually or in a single 32-bit read or write operation.
Each Capture Control register (L, H, or unified 32-bit) controls which events load the
corresponding Capture register from the counter.
Table 738. SCT capture control registers 0 to 15 (CAPCTRL- address 0x4000 0200
(CAPCTRL0) to 0x4000 023C (CAPCTRL15)) bit description (REGMODEn bit = 1)
Bit

Symbol

Description

Reset
value

15:0

CAPCONn_L

If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the 0
CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1
= bit 1,..., event 15 = bit 15).

31:16

CAPCONn_H

If bit m is one, event m causes the CAPn_H (UNIFY = 0)
0
register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event
15 = bit 31).

30.6.23 SCT event state mask registers 0 to 15
Each event has one associated SCT event state mask register that allow this event to
happen in one or more states of the counter selected by the HEVENT bit in the
corresponding EVCTRLn register.
An event n is disabled when its EVSTATEMSKn register contains all zeros, since it is
masked regardless of the current state.
In simple applications that do not use states, write 0x01 to this register to enable an event.
Since the state always remains at its reset value of 0, writing 0x01 effectively permanently
state-enables this event.
Table 739. SCT event state mask registers 0 to 15 (EVSTATEMSK - addresses 0x4000 0300
(EVSTATEMSK0) to 0x4000 0378 (EVSTATEMSK15)) bit description
Bit

Symbol

Description

Reset
value

31:0

STATEMSKn

If bit m is one, event n (n= 0 to 15) happens in state m of the
0
counter selected by the HEVENT bit (m = state number; state 0 =
bit 0, state 1= bit 1,..., state 31 = bit 31).

30.6.24 SCT event control registers 0 to 15
This register defines the conditions for event n to occur, other than the state variable
which is defined by the state mask register. Most events are associated with a particular
counter (high, low, or unified), in which case the event can depend on a match to that
register. The other possible ingredient of an event is a selected input or output signal.

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Chapter 30: LPC43xx/LPC43Sxx State Configurable Timer (SCT)

When the UNIFY bit is 0, each event is associated with a particular counter by the
HEVENT bit in its event control register. An event cannot occur when its related counter is
halted nor when the current state is not enabled to cause the event as specified in its
event mask register. An event is permanently disabled when its event state mask register
contains all 0s.
An enabled event can be programmed to occur based on a selected input or output edge
or level and/or based on its counter value matching a selected match register.
Each event can modify its counter STATE value. If more than one event associated with
the same counter occurs in a given clock cycle, only the state change specified for the
highest-numbered event among them takes place. Other actions dictated by any
simultaneously occurring events all take place.
Table 740. SCT event control register 0 to 15 (EVCTRL - address 0x4000 0304 (EVCTRL0) to 0x4000 037C
(EVCTRL15)) bit description
Bit

Symbol

Value Description

3:0

MATCHSEL

-

4

HEVENT

5

9:6

0

Selects the L state and the L match register selected by MATCHSEL.

1

Selects the H state and the H match register selected by MATCHSEL.
Input/output select

0

Selects the input selected by IOSEL.

1

Selects the output selected by IOSEL.

-

Selects the input or output signal associated with this event (if any). Do not select an
input in this register, if CKMODE is 1x. In this case the clock input is an implicit
ingredient of every event.

0

Selects the I/O condition for event n. (The detection of edges on outputs lag the
conditions that switch the outputs by one SCT clock). In order to guarantee proper
edge/state detection, an input must have a minimum pulse width of at least one SCT
clock period .

0

0x0

LOW

0x1

Rise

0x2

Fall

0x3

HIGH

13:12 COMBMODE

User manual

0

0

11:10 IOCOND

UM10503

Selects the Match register associated with this event (if any). A match can occur only 0
when the counter selected by the HEVENT bit is running.
Select L/H counter. Do not set this bit if UNIFY = 1.

OUTSEL

IOSEL

Reset
value

Selects how the specified match and I/O condition are used and combined.
0x0

OR. The event occurs when either the specified match or I/O condition occurs.

0x1

MATCH. Uses the specified match only.

0x2

IO. Uses the specified I/O condition only.

0x3

AND. The event occurs when the specified match and I/O condition occur
simultaneously.

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Chapter 30: LPC43xx/LPC43Sxx State Configurable Timer (SCT)

Table 740. SCT event control register 0 to 15 (EVCTRL - address 0x4000 0304 (EVCTRL0) to 0x4000 037C
(EVCTRL15)) bit description
Bit

Symbol

14

STATELD

Value Description

Reset
value

This bit controls how the STATEV value modifies the state selected by HEVENT when 0
this event is the highest-numbered event occurring for that state.
0

STATEV value is added into STATE (the carry-out is ignored).

1

STATEV value is loaded into STATE.

19:15 STATEV

This value is loaded into or added to the state selected by HEVENT, depending on
STATELD, when this event is the highest-numbered event occurring for that state. If
STATELD and STATEV are both zero, there is no change to the STATE value.

31:20 -

Reserved

0

30.6.25 SCT output set registers 0 to 15
Each output n has one set register that controls how events affect each output. Whether
outputs are set or cleared depends on the setting of the SETCLRn field in the
SCTOUTPUTDIRCTRL register.
Table 741. SCT output set register 0 to 15 (OUTPUTSET - address 0x4000 0500
(OUTPUTSET0) to 0x4000 0578 (OUTPUTSET15)) bit description
Bit

Symbol

Description

Reset
value

15:0

SET

A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0
0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.

31:16

-

Reserved

30.6.26 SCT output clear registers 0 to 15
Each output n has one clear register that controls how events affect each output. Whether
outputs are set or cleared depends on the setting of the SETCLRn field in the
OUTPUTDIRCTRL register.
Table 742. SCT output clear register 0 to 15 (OUTPUTCL - address 0x4000 0504
(OUTPUTCL0) to 0x4000 057C (OUTPUTCL15)) bit description

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Bit

Symbol

Description

15:0

CLR

A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0
0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.

31:16

-

Reserved

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Chapter 30: LPC43xx/LPC43Sxx State Configurable Timer (SCT)

30.7 Functional description
30.7.1 Match logic
Counter H

Match
Reload
iH

Match
Reg i H

=

Match i H
UNIFY

Match
Reload
iL

Match
Reg i L

=

Match i L

Counter L
Fig 102. Match logic

30.7.2 Capture logic

SCT clock

Fig 103. Capture logic

30.7.3 Event selection
State variables allow control of the SCT across more than one cycle of the counter.
Counter matches, input/output edges, and state values are combined into a set of
general-purpose events that can switch outputs, request interrupts, and change state
values.

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Chapter 30: LPC43xx/LPC43Sxx State Configurable Timer (SCT)

H matches

select

L matches
MATCHSELi
inputs
outputs

event i

select

IOSELi
OUTSELi
IOCONDi
COMBMODEi

select

STATEMASKi
H STATE
L STATE
HEVENTi

Fig 104. Event selection

30.7.4 Output generation
Figure 105 shows one output slice of the SCT.

Events
Set
register

NoChangeConflict
i

SETCLRi
OiRES

Clear
register i

Select

OUT
reg

Output

i
i

SCT clock

Fig 105. Output slice i

30.7.5 Interrupt generation
The SCT generates one interrupt to the NVIC.

Events
Enable
register

Conflict
Enable
register

Flags
register

No Change
Conflict events

UT interrupt
Conflict
Flags
register

Fig 106. SCT interrupt generation

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Chapter 30: LPC43xx/LPC43Sxx State Configurable Timer (SCT)

30.7.6 Clearing the prescaler
When enabled by a non-zero PRE field in the Control register, the prescaler acts as a
clock divider for the counter, like a fractional part of the counter value. The prescaler is
cleared whenever the counter is cleared or loaded for any of the following reasons:

•
•
•
•

Hardware reset
Software writing to the counter register
Software writing a 1 to the CLRCTR bit in the control register
an event selected by a 1 in the counter limit register when BIDIR = 0

When BIDIR is 0, a limit event caused by an I/O signal can clear a non-zero prescaler.
However, a limit event caused by a Match only clears a non-zero prescaler in one special
case as described Section 30.7.7.
A limit event when BIDIR is 1 does not clear the prescaler. Rather it clears the DOWN bit
in the Control register, and decrements the counter on the same clock if the counter is
enabled in that clock.

30.7.7 Match vs. I/O events
Counter operation is complicated by the prescaler and by clock mode 01 in which the SCT
clock is the bus clock. However, the prescaler and counter are enabled to count only when
a selected edge is detected on a clock input.

• The prescaler is enabled when the clock mode is not 01, or when the input edge
selected by the CLKSEL field is detected.

• The counter is enabled when the prescaler is enabled, and (PRELIM=0 or the
prescaler is equal to the value in PRELIM).
An I/O component of an event can occur in any SCT clock when its counter HALT bit is 0.
In general, a Match component of an event can only occur in a UT clock when its counter
HALT and STOP bits are both 0 and the counter is enabled.
Table 743 shows when the various kinds of events can occur.
Table 743. Event conditions
COMBMODE IOMODE

Event can occur on clock:

IO

Any

Event can occur whenever HALT = 0 (type A).

MATCH

Any

Event can occur when HALT = 0 and STOP = 0 and the counter is
enabled (type C).

OR

Any

From the IO component: Event can occur whenever HALT = 0 (A).
From the match component: Event can occur when HALT = 0 and
STOP = 0 and the counter is enabled (C).

AND

LOW or HIGH

Event can occur when HALT = 0 and STOP = 0 and the counter is
enabled (C).

AND

RISE or FALL

Event can occur whenever HALT = 0 (A).

30.7.8 DMA operation
A DMA controller can be used to write one or more Reload registers, or read one or more
Capture registers, typically at the start of a counter cycle.
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Chapter 30: LPC43xx/LPC43Sxx State Configurable Timer (SCT)

Remark: The SCT can also be used to launch timed or other event-determined transfers
among other peripherals or between other peripherals and memory. It is not necessary to
transfer data in and out of the SCT in response to a DMA request.
DMA access to more than one Reload or Capture register requires that they be
consecutive registers. (Nothing else in the SCT constrains how these registers are
assigned and used.)
An event can set a DMA request or set when a counter Match registers are loaded from its
Reload registers, as described in Section 30.6.14. The two requests of the SCT can be
used to do the same register access for both counters when UNIFY is 0. Alternatively, one
request can be used for writing Reload registers and the other for reading Capture
registers.
The SCT does not know how many transfers are done for each request, so it cannot
control its DMA requests accordingly.
The two DMA requests are connected to DMABREQ7 and DMABREQ8. Write the number
of registers to be transferred for each request to the TransferSize field in the Channel
Control Register of the DMA channel to which the request is connected. If the Linked List
feature is used, there is a TransferSize value in each Linked List entry. The GPDMA
asserts the DMACCLR signal when that number of transfers has been completed, which
makes the SCT clear the request.

30.7.9 Alternate addressing for match/capture registers
The Match, Reload, Capture, and Capture Control registers are arranged as consecutive
words, with the standard division of each word into two halfwords. When the UNIFY bit is
zero, these two halfwords are related to the L and H counters. Software has the option of
writing words initially to set up both halves of a SCT simultaneously, or writing halfwords to
set up each half separately.
Applications can use a DMA controller to write Reload registers or to read Capture
registers. However, when UNIFY is 0, the addressing of the halfword registers is not
compatible with the requirement of many DMA controllers to use consecutive addresses
for sequential address operation. Table 744 shows how the second half of the range
occupied by each type of register contains an alternate address map for halfword
accesses to the same registers, which is compatible with DMA that use sequential
address operation. When UNIFY is 1, perform DMA word accesses using standard
offsets.
Table 744. Alternate address map for DMA halfword access

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Match register

Capture register

Standard offset

DMA halfword offset

MATCH0_L

CAP0_L

0x100

0x180

MATCH0_H

CAP0_H

0x102

0x1C0

MATCH1_L

CAP1_L

0x104

0x182

MATCH1_H

CAP1_H

0x106

0x1C2

...

...

...

...

MATCHREL0_L

CAPCTRL0_L

0x200

0x280

MATCHREL0_H

CAPCTRL0_H

0x202

0x2C0

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Chapter 30: LPC43xx/LPC43Sxx State Configurable Timer (SCT)

Table 744. Alternate address map for DMA halfword access

UM10503

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Match register

Capture register

Standard offset

DMA halfword offset

MATCHREL1_L

CAPCTRL1_L

0x204

0x282

MATCHREL1_H

CAPCTRL1_H

0x206

0x2C2

...

...

...

...

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Chapter 30: LPC43xx/LPC43Sxx State Configurable Timer (SCT)

30.7.10 SCT operation
In its simplest, single-state configuration, the SCT operates as an event controlled one- or
bidirectional counter. Events can be configured to be counter match events, an input or
output level, transitions on an input or output pin, or a combination of match and
input/output behavior. In response to an event, the SCT output or outputs can transition,
or the SCT can perform other actions such as creating an interrupt or starting, stopping, or
resetting the counter. Multiple simultaneous actions are allowed for each event.
Furthermore, any number of events can trigger one specific action of the SCT.
An action or multiple actions of the SCT uniquely define an event. A state is defined by
which events are enabled to trigger an SCT action or actions in any stage of the counter.
Events not selected for this state are ignored.
In a multi-state configuration, states change in response to events. A state change is an
additional action that the SCT can perform when the event occurs. When an event is
configured to change the state, the new state defines a new set of events resulting in
different actions of the SCT. Through multiple cycles of the counter, events can change
the state multiple times and thus create a large variety of event controlled transitions on
the SCT outputs and/or interrupts.
Once configured, the SCT can run continuously without software intervention and can
generate multiple output patterns entirely under the control of events.

• To configure the SCT, see Section 30.7.10.1.
• To start, run, and stop the SCT, see Section 30.7.10.2.
• To configure the SCT as simple event controlled counter/timer, see Section 30.7.10.3.
30.7.10.1 Configure the SCT
To set up the SCT for multiple events and states, perform the following configuration
steps:
30.7.10.1.1

Configure the counter
1. Configure the L and H counters in the CONFIG register by selecting two independent
16-bit counters (L counter and H counter) or one combined 32-bit counter in the
UNIFY field.
2. Select the SCT clock source in the CONFIG register (fields CLKMODE and CLKSEL)
from any of the inputs or an internal clock.

30.7.10.1.2

Configure the match and capture registers
1. Select how many match and capture registers the application uses (total of up to 16):
– In the REGMODE register, select for each of the 16 match/capture register pairs
whether the register is used as a match register or capture register.
2. Define match conditions for each match register selected:
– Each match register MATCH sets one match value, if a 32-bit counter is used, or
two match values, if the L and H 16-bit counters are used.
– Each match reload register MATCHRELOAD sets a reload value that is loaded into
the match register when the counter reaches a limit condition or the value 0.

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Chapter 30: LPC43xx/LPC43Sxx State Configurable Timer (SCT)

30.7.10.1.3

Configure events and event responses
1. Define when each event can occur in the following way in the EVCTRL registers (up
to 16, one register per event):
– Select whether the event occurs on an input or output changing, on an input or
output level, a match condition of the counter, or a combination of match and
input/output conditions in field COMBMODE.
– For a match condition:
Select the match register that contains the match condition for the event to occur.
Enter the number of the selected match register in field MATCHSEL.
If using L and H counters, define whether the event occurs on matching the L or
the H counter in field HEVENT.
– For an SCT input or output level or transition:
Select the input number or the output number that is associated with this event in
fields IOSEL and OUTSEL.
Define how the selected input or output triggers the event (edge or level sensitive)
in field IOCOND.
2. Define what the effect of each event is on the SCT outputs in the OUTPUTSET or
OUTPUTCLR registers (up to 16 outputs, one register per output):
– For each SCT output, select which events set or clear this output. More than one
event can change the output, and each event can change multiple outputs.
3. Define how each event affects the counter:
– Set the corresponding event bit in the LIMIT register for the event to set an upper
limit for the counter.
When a limit event occurs in unidirectional mode, the counter is cleared to zero
and begins counting up on the next clock edge.
When a limit event occurs in bidirectional mode, the counter begins to count down
from the current value on the next clock edge.
– Set the corresponding event bit in the HALT register for the event to halt the
counter. If the counter is halted, it stops counting and no new events can occur.
The counter operation can only be restored by clearing the HALT_L and/or the
HALT_H bits in the CTRL register.
– Set the corresponding event bit in the STOP register for the event to stop the
counter. If the counter is stopped, it stops counting. However, an event that is
configured as a transition on an input/output can restart the counter.
– Set the corresponding event bit in the START register for the event to restart the
counting. Only events that are defined by an input changing can be used to restart
the counter.
4. Define which events contribute to the SCT interrupt:
– Set the corresponding event bit in the EVEN and the EVFLAG registers to enable
the event to contribute to the SCT interrupt.
5. Define whether an event triggers a DMA request.
– Set the corresponding event bit in the DMAREQ0/1 registers for the event to
trigger DMA requests 0 or 1.

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Chapter 30: LPC43xx/LPC43Sxx State Configurable Timer (SCT)

30.7.10.1.4

Configure multiple states
1. In the EVSTATEMASK register for each event (up to 16 events, one register per
event), select the state or states (up to 31) in which this event is allowed to occur.
Each state can be selected for more than one event.
2. Determine how the event affects the system state:
In the EVCTRL registers (up to 16 events, one register per event), set the new state
value in the STATEV field for this event. If the event is the highest numbered in the
current state, this value is either added to the existing state value or replaces the
existing state value, depending on the field STATELD.
Remark: If there are higher numbered events in the current state, this event cannot
change the state.
If the STATEV and STATELD values are set to zero, the state does not change.

30.7.10.1.5

Miscellaneous options

• There are a certain (selectable) number of capture registers. Each capture register
can be programmed to capture the counter contents when one or more events occur.

• If the counter is in bidirectional mode, the effect of set and clear of an output can be
made to depend on whether the counter is counting up or down by writing to the
OUTPUTDIRCTRL register.

•
30.7.10.2 Operate the SCT
1. Configure the SCT (see Section 30.7.10.1 “Configure the SCT”).
a. Configure the counter (see Section 30.7.10.1.1).
b. Configure the match and capture registers (see Section 30.7.10.1.2).
c. Configure the events and event responses (see Section 30.7.10.1.3).
d. Configure multiple states (Section 30.7.10.1.4).
2. Write to the STATE register to define the initial state. By default the initial state is state
0.
3. To start the SCT, write to the CTRL register:
– Clear the counters.
– Clear or set the STOP_L and/or STOP_H bits.
Remark: The counter starts counting once the STOP bit is cleared as well. If the
STOP bit is set, the SCT waits instead for an event to occur that is configured to
start the counter.
– For each counter, select unidirectional or bidirectional counting mode (field
BIDIR_L and/or BIDIR_H).
– Select the prescale factor for the counter clock (CTRL register).
– Clear the HALT_L and/or HALT_H bit. By default, the counters are halted and no
events can occur.
4. To stop the counters by software at any time, stop or halt the counter (write to
STOP_L and/or STOP_H bits or HALT_L and/or HALT_H bits in the CTRL register).

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Chapter 30: LPC43xx/LPC43Sxx State Configurable Timer (SCT)

– When the counters are stopped, both an event configured to clear the STOP bit or
software writing a zero to the STOP bit can start the counter again.
– When the counter are halted, only a software write to clear the HALT bit can start
the counter again. No events can occur.
– When the counters are halted, software can set any SCT output HIGH or LOW
directly by writing to the OUT register.
The current state can be read at any time by reading the STATE register.
To change the current state by software (that is independently of any event occurring), set
the HALT bit and write to the STATE register to change the state value. Writing to the
STATE register is only allowed when the counter is halted (the HALT_L and/or HALT_H
bits are set) and no events can occur.

30.7.10.3 Configure the SCT without using states
The SCT can be used as standard counter/timer with external capture inputs and match
outputs without using the state logic. To operate the SCT without states, configure the
SCT as follows:

• Write zero to the STATE register (zero is the default).
• Write zero to the STATELD and STATEV fields in the EVCTRL registers for each
event.

• Write 0x1 to the EVSTATEMASK register of each event. Writing 0x1 enables the
event.
In effect, the event is allowed to occur in a single state which never changes while the
counter is running.

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Chapter 31: LPC43xx/LPC43Sxx State Configurable Timer
(SCT) with dither engine
Rev. 2.4 — 22 August 2018

User manual

31.1 How to read this chapter
The SCT with dither engine is available on all flash-based LPC43xx/LPC43Sxx parts. The
SCT implemented here is identical to the SCT implemented for flashless parts except for
the following additions:

•
•
•
•

Dither engine and fractional match registers
Automatic limits
Holding of match events until a qualifying event occurs
Event enabling based on count direction

All SCT functions available in the flashless parts are also available in the SCT with dither
engine. See Chapter 30 “LPC43xx/LPC43Sxx State Configurable Timer (SCT)” for the
following sections which apply to both versions of the SCT with or without the dither
engine:
Section 30.2 “Basic configuration”
Section 30.4 “General description”
Section 30.5 “Pin description”
Section 30.7 “Functional description” for all common SCT features

31.2 Features
•
•
•
•
•

Two 16-bit counters or one 32-bit counter.
Counters clocked by bus clock or selected input.
Up counters or up-down counters.
State variable allows sequencing across multiple counter cycles.
The following conditions define an event: a counter match condition, an input (or
output) condition, a combination of a match and/or and input/output condition in a
specified state.

• Events control outputs, interrupts, and DMA requests.
– Match register 0 can be used as an automatic limit.
– In bi-directional mode, events can be enabled based on the count direction,
– Match events can be held until another qualifying event occurs.

• Selected events can limit, halt, start, or stop a counter.
• Supports:
– 8 inputs
– 16 outputs
– 16 match/capture registers
– 16 events
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Chapter 31: LPC43xx/LPC43Sxx State Configurable Timer (SCT) with

– 32 states
– Match register 0 to 5 support a fractional component for the dither engine

31.3 Register description
The register addresses of the State Configurable Timer are shown in Table 745. For most
of the SCT registers, the register function depends on the setting of certain other register
bits:
1. The UNIFY bit in the CONFIG register determines whether the SCT is used as one
32-bit register (for operation as one 32-bit counter/timer) or as two 16-bit
counter/timers named L and H. The setting of the UNIFY bit is reflected in the register
map:
– UNIFY = 1: Only one register is used (for operation as one 32-bit counter/timer).
– UNIFY = 0: Access the L and H registers by a 32-bit read or write operation or can
be read or written to individually (for operation as two 16-bit counter/timers).
Typically, the UNIFY bit is configured by writing to the CONFIG register before any
other registers are accessed.
2. The REGMODEn bits in the REGMODE register determine whether each set of
Match/Capture registers uses the match or capture functionality:
– REGMODEn = 0: Registers operate as match and reload registers.
– REGMODEn = 1: Registers operate as capture and capture control registers.
The register overview includes the alias registers for the Match, Reload, Fractional match,
Fractional match reload, Capture, and Capture Control L and H 16-bit registers. See
Section 31.4.2.
Table 745. Register overview: State Configurable Timer (base address 0x4000 0000)
Name

Access Address Description
offset

Reset value Reference

CONFIG

R/W

0x000

SCT configuration register

0x0000 7E00 Table 746

CTRL

R/W

0x004

SCT control register

0x0004 0004 Table 747

CTRL_L

R/W

0x004

SCT control register low counter 16-bit

0x0004 0004 Table 747

CTRL_H

R/W

0x006

SCT control register high counter 16-bit

0x0004 0004 Table 747

LIMIT

R/W

0x008

SCT limit register

0x0000 0000 Table 748

LIMIT_L

R/W

0x008

SCT limit register low counter 16-bit

0x0000 0000 Table 748

LIMIT_H

R/W

0x00A

SCT limit register high counter 16-bit

0x0000 0000 Table 748

HALT

R/W

0x00C

SCT halt condition register

0x0000 0000 Table 749

HALT_L

R/W

0x00C

SCT halt condition register low counter 16-bit

0x0000 0000 Table 749

HALT_H

R/W

0x00E

SCT halt condition register high counter 16-bit

0x0000 0000 Table 749

STOP

R/W

0x010

SCT stop condition register

0x0000 0000 Table 750

STOP_L

R/W

0x010

SCT stop condition register low counter 16-bit

0x0000 0000 Table 750

STOP_H

R/W

0x012

SCT stop condition register high counter 16-bit

0x0000 0000 Table 750

START

R/W

0x014

SCT start condition register

0x0000 0000 Table 751

START_L

R/W

0x014

SCT start condition register low counter 16-bit

0x0000 0000 Table 751

START_H

R/W

0x016

SCT start condition register high counter 16-bit

0x0000 0000 Table 751

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Chapter 31: LPC43xx/LPC43Sxx State Configurable Timer (SCT) with

Table 745. Register overview: State Configurable Timer (base address 0x4000 0000) …continued
Name

Access Address Description
offset

DITHER

R/W

DITHER_L

R/W

DITHER_H

R/W

-

-

0x01C 0x03C

COUNT

R/W

0x040

SCT counter register

0x0000 0000 Table 753

COUNT_L

R/W

0x040

SCT counter register low counter 16-bit

0x0000 0000 Table 753

COUNT_H

R/W

0x042

SCT counter register high counter 16-bit

0x0000 0000 Table 753

STATE

R/W

0x044

SCT state register

0x0000 0000 Table 754

STATE_L

R/W

0x044

SCT state register low counter 16-bit

0x0000 0000 Table 754

STATE_H

R/W

0x046

SCT state register high counter 16-bit

0x0000 0000 Table 754

INPUT

RO

0x048

SCT input register

0x0000 0000 Table 755

REGMODE

R/W

0x04C

SCT match/capture registers mode register

0x0000 0000 Table 756

REGMODE_L

R/W

0x04C

SCT match/capture registers mode register low
counter 16-bit

0x0000 0000 Table 756

REGMODE_H

R/W

0x04E

SCT match/capture registers mode register high
counter 16-bit

0x0000 0000 Table 756

OUTPUT

R/W

0x050

SCT output register

0x0000 0000 Table 757

OUTPUTDIRCTRL

R/W

0x054

SCT output counter direction control register

0x0000 0000 Table 758

RES

R/W

0x058

SCT conflict resolution register

0x0000 0000 Table 759

DMAREQ0

R/W

0x05C

SCT DMA request 0 register

0x0000 0000 Table 760

DMAREQ1

R/W

0x060

SCT DMA request 1 register

0x0000 0000 Table 761

-

-

0x064 0x0EC

Reserved

-

EVEN

R/W

0x0F0

SCT event enable register

0x0000 0000 Table 762

EVFLAG

R/W

0x0F4

SCT event flag register

0x0000 0000 Table 763

CONEN

R/W

0x0F8

SCT conflict enable register

0x0000 0000 Table 764

CONFLAG

R/W

0x0FC

SCT conflict flag register

0x0000 0000 Table 765

MATCH0 to
MATCH15

R/W

0x100 to SCT match value register of match channels 0 to
0x13C
15; REGMOD0 to REGMODE15 = 0

0x0000 0000 Table 765

MATCH0_L to
MATCH15_L

R/W

0x100 to SCT match value register of match channels 0 to
0x13C
15; low counter 16-bit; REGMOD0_L to
REGMODE15_L = 0

0x0000 0000 Table 765

MATCH0_H to
MATCH15_H

R/W

0x102 to SCT match value register of match channels 0 to
0x13E
15; high counter 16-bit; REGMOD0_H to
REGMODE15_H = 0

0x0000 0000 Table 765

CAP0 to CAP15

0x100 to SCT capture register of capture channel 0 to 15;
0x13C
REGMOD0 to REGMODE15 = 1

0x0000 0000 Table 768

CAP0_L to CAP15_L

0x100 to SCT capture register of capture channel 0 to 15;
0x13C
low counter 16-bit; REGMOD0_L to
REGMODE15_L = 1

0x0000 0000 Table 768

CAP0_H to CAP15_H

0x102 to SCT capture register of capture channel 0 to 15;
0x13E
high counter 16-bit; REGMOD0_H to
REGMODE15_H = 1

0x0000 0000 Table 768

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0x018

Reset value Reference

SCT dither condition register

Table 752

0x018

SCT dither condition register low counter 16-bit

Table 752

0x01A

SCT dither condition register high counter 16-bit

Table 752

Reserved

-

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Chapter 31: LPC43xx/LPC43Sxx State Configurable Timer (SCT) with

Table 745. Register overview: State Configurable Timer (base address 0x4000 0000) …continued
Name

Access Address Description
offset

Reset value Reference

FRACMAT0 to 5

R/W

0x140 to Fractional match registers 0 to 5 for SCT match
0x154
value registers 0 to 5.

0x0000 0000 Table 767

FRACMAT0_L to
FRACMAT5_L

R/W

0x140 to Fractional match registers 0 to 5 for SCT match
0x154
value registers 0 to 5; low counter 16-bit.

0x0000 0000 Table 767

FRACMAT0_H to
FRACMAT5_H

R/W

0x142 to Fractional match registers 0 to 5 for SCT match
0x156
value registers 0 to 5; high counter 16-bit.

0x0000 0000 Table 767

MATCH0_L to
MATCH15_L

R/W

0x180 to MATCH alias register. SCT match value register
0x1A0
of match channels 0 to 15; low counter 16-bit;
REGMOD0_L to REGMODE15_L = 0

0x0000 0000 Table 765

MATCH0_H to
MATCH15_H

R/W

0x1C0 to MATCH alias register. SCT match value register
0x1E0
of match channels 0 to 15; high counter 16-bit;
REGMOD0_H to REGMODE15_H = 0

0x0000 0000 Table 765

CAP0_L to CAP15_L

0x180 to CAP alias register. SCT capture register of
0x1A0
capture channel 0 to 15; low counter 16-bit;
REGMOD0_L to REGMODE15_L = 1

0x0000 0000 Table 768

CAP0_H to CAP15_H

0x1C0 to CAP alias register. SCT capture register of
0x1E0
capture channel 0 to 15; high counter 16-bit;
REGMOD0_H to REGMODE15_H = 1

0x0000 0000 Table 768

FRACMAT0_L to
FRACMAT5_L

R/W

0x1A0 to Fractional match alias registers 0 to 5 for SCT
0x1AA
match value registers 0 to 5; low counter 16-bit.

0x0000 0000 Table 767

FRACMAT0_H to
FRACMAT5_H

R/W

0x1E0 to Fractional match alias registers 0 to 5 for SCT
0x1EA
match value registers 0 to 5; high counter 16-bit.

0x0000 0000 Table 767

MATCHREL0 to
MATCHREL15

R/W

0x200 to SCT match reload value register 0 to 15;
0x23C
REGMOD0 = 0 to REGMODE15 = 0

0x0000 0000 Table 769

MATCHREL0_L to
MATCHREL15_L

R/W

0x200 to SCT match reload value register 0 to 15; low
0x23C
counter 16-bit; REGMOD0_L = 0 to
REGMODE15_L = 0

0x0000 0000 Table 769

MATCHREL0_H to
MATCHREL15_H

R/W

0x202 to SCT match reload value register 0 to 15; high
0x23E
counter 16-bit; REGMOD0_H = 0 to
REGMODE15_H = 0

0x0000 0000 Table 769

CAPCTRL0 to
CAPCTRL15

0x200 to SCT capture control register 0 to 15; REGMOD0
0x23C
= 1 to REGMODE15 = 1

0x0000 0000 Table 771

CAPCTRL0_L to
CAPCTRL15_L

0x200 to SCT capture control register 0 to 15; low counter
0x23C
16-bit; REGMOD0_L = 1 to REGMODE15_L = 1

0x0000 0000 Table 771

CAPCTRL0_H to
CAPCTRL15_H

0x202 to SCT capture control register 0 to 15; high counter 0x0000 0000 Table 771
0x23E
16-bit; REGMOD0 = 1 to REGMODE15 = 1

FRACMATREL0 to
FRACMATREL5

R/W

0x240 to Fractional match reload registers 0 to 5 for SCT
0x254
match value registers 0 to 5.

0x0000 0000 Table 770

FRACMATREL0_L to R/W
FRACMATREL5_L

0x240 to Fractional match reload registers 0 to 5 for SCT
0x254
match value registers 0 to 5; low counter 16-bit.

0x0000 0000 Table 770

FRACMATREL0_H to R/W
FRACMATREL5_H

0x242 to Fractional match reload registers 0 to 5 for SCT
0x256
match value registers 0 to 5; high counter 16-bit.

0x0000 0000 Table 770

MATCHREL0_L to
MATCHREL15_L

R/W

0x280 to MATCHREL alias registers. SCT match reload
0x2A0
value register 0 to 15; low counter 16-bit;
REGMOD0_L = 0 to REGMODE15_L = 0

0x0000 0000 Table 769

MATCHREL0_H to
MATCHREL15_H

R/W

0x2C0 to MATCHREL alias registers. SCT match reload
0x2E0
value register 0 to 15; high counter 16-bit;
REGMOD0_H = 0 to REGMODE15_H = 0

0x0000 0000 Table 769

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Chapter 31: LPC43xx/LPC43Sxx State Configurable Timer (SCT) with

Table 745. Register overview: State Configurable Timer (base address 0x4000 0000) …continued
Name

Access Address Description
offset

Reset value Reference

CAPCTRL0_L to
CAPCTRL15_L

0x280 to CAPCTRL alias registers. SCT capture control
0x0000 0000 Table 771
0x2E0
register 0 to 15; low counter 16-bit; REGMOD0_L
= 1 to REGMODE15_L = 1

CAPCTRL0_H to
CAPCTRL15_H

0x0000 0000 Table 771
0x2C0 to CAPCTRL alias registers. SCT capture control
0x2E0
register 0 to 15; high counter 16-bit; REGMOD0 =
1 to REGMODE15 = 1

FRACMATREL0_L to R/W
FRACMATREL5_L

0x2A0 to Fractional match reload alias registers 0 to 5 for
0x2AA
SCT match value registers 0 to 5; low counter
16-bit.

0x0000 0000 Table 770

FRACMATREL0_H to R/W
FRACMATREL5_H

0x2E0 to Fractional match reload alias registers 0 to 5 for
0x2EA
SCT match value registers 0 to 5; high counter
16-bit.

0x0000 0000 Table 770

EV0_STATE

0x300

0x0000 0000 Table 772

R/W

SCT event state register 0

EV0_CTRL

R/W

0x304

SCT event control register 0

0x0000 0000 Table 773

EV1_STATE

R/W

0x308

SCT event state register 1

0x0000 0000 Table 772

EV1_CTRL

R/W

0x30C

SCT event control register 1

0x0000 0000 Table 773

EV2_STATE

R/W

0x310

SCT event state register 2

0x0000 0000 Table 772

EV2_CTRL

R/W

0x314

SCT event control register 2

0x0000 0000 Table 773

EV3_STATE

R/W

0x318

SCT event state register 3

0x0000 0000 Table 772

EV3_CTRL

R/W

0x31C

SCT event control register 3

0x0000 0000 Table 773

EV4_STATE

R/W

0x320

SCT event state register 4

0x0000 0000 Table 772

EV4_CTRL

R/W

0x324

SCT event control register4

0x0000 0000 Table 773

EV5_STATE

R/W

0x328

SCT event state register 5

0x0000 0000 Table 772

EV5_CTRL

R/W

0x32C

SCT event control register 5

0x0000 0000 Table 773

EV6_STATE

R/W

0x330

SCT event state register 6

0x0000 0000 Table 772

EV6_CTRL

R/W

0x334

SCT event control register 6

0x0000 0000 Table 773

EV7_STATE

R/W

0x338

SCT event state register 7

0x0000 0000 Table 772

EV7_CTRL

R/W

0x33C

SCT event control register 7

0x0000 0000 Table 773

EV8_STATE

R/W

0x340

SCT event state register 8

0x0000 0000 Table 772

EV8_CTRL

R/W

0x344

SCT event control register 8

0x0000 0000 Table 773

EV9_STATE

R/W

0x348

SCT event state register 9

0x0000 0000 Table 772

EV9_CTRL

R/W

0x34C

SCT event control register 9

0x0000 0000 Table 773

EV10_STATE

R/W

0x350

SCT event state register 10

0x0000 0000 Table 772

EV10_CTRL

R/W

0x354

SCT event control register 10

0x0000 0000 Table 773

EV11_STATE

R/W

0x358

SCT event state register 11

0x0000 0000 Table 772

EV11_CTRL

R/W

0x35C

SCT event control register 11

0x0000 0000 Table 773

EV12_STATE

R/W

0x360

SCT event state register 12

0x0000 0000 Table 772

EV12_CTRL

R/W

0x364

SCT event control register 12

0x0000 0000 Table 773

EV13_STATE

R/W

0x368

SCT event state register 13

0x0000 0000 Table 772

EV13_CTRL

R/W

0x36C

SCT event control register 13

0x0000 0000 Table 773

EV14_STATE

R/W

0x370

SCT event state register 14

0x0000 0000 Table 772

EV14_CTRL

R/W

0x374

SCT event control register 14

0x0000 0000 Table 773

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Chapter 31: LPC43xx/LPC43Sxx State Configurable Timer (SCT) with

Table 745. Register overview: State Configurable Timer (base address 0x4000 0000) …continued
Name

Access Address Description
offset

Reset value Reference

EV15_STATE

R/W

0x0000 0000 Table 772

0x378

SCT event state register 15

EV15_CTRL

R/W

0x37C

SCT event control register 15

0x0000 0000 Table 773

OUT0_SET

R/W

0x500

SCT output 0 set register

0x0000 0000 Table 774

OUT0_CLR

R/W

0x504

SCT output 0 clear register

0x0000 0000 Table 775

OUT1_SET

R/W

0x508

SCT output 1 set register

0x0000 0000 Table 774

OUT1_CLR

R/W

0x50C

SCT output 1 clear register

0x0000 0000 Table 775

OUT2_SET

R/W

0x510

SCT output 2 set register

0x0000 0000 Table 774

OUT2_CLR

R/W

0x514

SCT output 2 clear register

0x0000 0000 Table 775

OUT3_SET

R/W

0x518

SCT output 3 set register

0x0000 0000 Table 774

OUT3_CLR

R/W

0x51C

SCT output 3 clear register

0x0000 0000 Table 775

OUT4_SET

R/W

0x520

SCT output 4 set register

0x0000 0000 Table 774

OUT4_CLR

R/W

0x524

SCT output 4 clear register

0x0000 0000 Table 775

OUT5_SET

R/W

0x528

SCT output 5 set register

0x0000 0000 Table 774

OUT5_CLR

R/W

0x52C

SCT output 5 clear register

0x0000 0000 Table 775

OUT6_SET

R/W

0x530

SCT output 6 set register

0x0000 0000 Table 774

OUT6_CLR

R/W

0x534

SCT output 6 clear register

0x0000 0000 Table 775

OUT7_SET

R/W

0x538

SCT output 7 set register

0x0000 0000 Table 774

OUT7_CLR

R/W

0x53C

SCT output 7 clear register

0x0000 0000 Table 775

OUT8_SET

R/W

0x540

SCT output 8 set register

0x0000 0000 Table 774

OUT8_CLR

R/W

0x544

SCT output 8 clear register

0x0000 0000 Table 775

OUT9_SET

R/W

0x548

SCT output 9 set register

0x0000 0000 Table 774

OUT9_CLR

R/W

0x54C

SCT output 9 clear register

0x0000 0000 Table 775

OUT10_SET

R/W

0x550

SCT output 10 set register

0x0000 0000 Table 774

OUT10_CLR

R/W

0x554

SCT output 10 clear register

0x0000 0000 Table 775

OUT11_SET

R/W

0x558

SCT output 11 set register

0x0000 0000 Table 774

OUT11_CLR

R/W

0x55C

SCT output 11 clear register

0x0000 0000 Table 775

OUT12_SET

R/W

0x560

SCT output 12 set register

0x0000 0000 Table 774

OUT12_CLR

R/W

0x564

SCT output 12 clear register

0x0000 0000 Table 775

OUT13_SET

R/W

0x568

SCT output 13 set register

0x0000 0000 Table 774

OUT13_CLR

R/W

0x56C

SCT output 13 clear register

0x0000 0000 Table 775

OUT14_SET

R/W

0x570

SCT output 14 set register

0x0000 0000 Table 774

OUT14_CLR

R/W

0x574

SCT output 14 clear register

0x0000 0000 Table 775

OUT15_SET

R/W

0x578

SCT output 15 set register

0x0000 0000 Table 774

OUT15_CLR

R/W

0x57C

SCT output 15 clear register

0x0000 0000 Table 775

31.3.1 SCT configuration register
This register configures the overall operation of the SCT. Write to this register before any
other registers.

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Chapter 31: LPC43xx/LPC43Sxx State Configurable Timer (SCT) with

Table 746. SCT configuration register (CONFIG, address 0x4000 0000) bit description
Bit

Symbol

0

UNIFY

2:1

Value

Reset
value

SCT operation

0

0

16-bit.The SCT operates as two 16-bit counters named L and H.

1

32-bit. The SCT operates as a unified 32-bit counter.

0x0

Bus clock. The bus clock clocks the SCT and prescalers.

0x1

Prescaled bus clock. The SCT clock is the bus clock, but the prescalers are
enabled to count only when sampling of the input selected by the CKSEL field
finds the selected edge. The minimum pulse width on the clock input is 1 bus
clock period. This mode is the high-performance sampled-clock mode.

0x2

SCT Input. The input selected by CKSEL clocks the SCT and prescalers. The
input is synchronized to the bus clock and possibly inverted. The minimum
pulse width on the clock input is 1 bus clock period. This mode is the low-power
sampled-clock mode.

CLKMODE

SCT clock mode

0x3
6:3

Description

CKSEL

00

Reserved.
SCT clock select

0x0

Rising edges on input 0.

0x1

Falling edges on input 0.

0x2

Rising edges on input 1.

0x3

Falling edges on input 1.

0x4

Rising edges on input 2.

0x5

Falling edges on input 2.

0x6

Rising edges on input 3.

0x7

Falling edges on input 3.

0x8

Rising edges on input 4.

0x9

Falling edges on input 4.

0xA

Rising edges on input 5.

0xB

Falling edges on input 5.

0xC

Rising edges on input 6.

0xD

Falling edges on input 6.

0xE

Rising edges on input 7.

0xF

Falling edges on input 7.

0000

7

NORELAOD_L

-

A 1 in this bit prevents the lower match and fractional match registers from
being reloaded from their respective reload registers. Software can write to set
or clear this bit at any time. This bit applies to both the higher and lower
registers when the UNIFY bit is set.

0

8

NORELOAD_H

-

A 1 in this bit prevents the higher match and fractional match registers from
being reloaded from their respective reload registers. Software can write to set
or clear this bit at any time. This bit is not used when the UNIFY bit is set.

0

16:9

INSYNC

-

Synchronization for input n (bit 9 = input 0, bit 10 = input 1,..., bit 16 = input 7). A 1
1 in one of these bits subjects the corresponding input to synchronization to the
SCT clock, before it is used to create an event. If an input is synchronous to the
SCT clock, keep its bit 0 for faster response.
When the CKMODE field is 1x, the bit in this field, corresponding to the input
selected by the CKSEL field, is not used.

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Chapter 31: LPC43xx/LPC43Sxx State Configurable Timer (SCT) with

Table 746. SCT configuration register (CONFIG, address 0x4000 0000) bit description …continued
Bit

Symbol

Value

Description

Reset
value

17

AUTOLIMIT_L

-

A one in this bit causes a match on match register 0 to be treated as a de-facto 0
LIMIT condition without the need to define an associated event.
As with any LIMIT event, this automatic limit causes the counter to be cleared to
zero in uni-directional mode or to change the direction of count in bi-directional
mode.
Software can write to set or clear this bit at any time. This bit applies to both the
higher and lower registers when the UNIFY bit is set.

18

AUTOLIMIT_H

-

A one in this bit will cause a match on match register 0 to be treated as a
de-facto LIMIT condition without the need to define an associated event.

0

As with any LIMIT event, this automatic limit causes the counter to be cleared to
zero in uni-directional mode or to change the direction of count in bi-directional
mode.
Software can write to set or clear this bit at any time. This bit is not used when
the UNIFY bit is set.
31:19

-

Reserved

-

31.3.2 SCT control register
If UNIFY = 1 in the CONFIG register, only the _L bits are used.
If UNIFY = 0 in the CONFIG register, this register can be written to as two registers
CTRL_L and CTRL_H. Both the L and H registers can be read or written individually or in
a single 32-bit read or write operation.
All bits in this register can be written to when the counter is stopped or halted. When the
counter is running, the only bits that can be written are STOP or HALT. (Other bits can be
written in a subsequent write after HALT is set to 1.)
Table 747. SCT control register (CTRL, address 0x4000 0004) bit description
Bit

Symbol

Value Description

Reset
value

0

DOWN_L

-

This bit is 1 when the L or unified counter is counting down. Hardware sets this bit
0
when the counter limit is reached and BIDIR is 1. Hardware clears this bit when the
counter reaches 0 or when the counter is counting down and a limit condition occurs.

1

STOP_L

-

When this bit is 1 and HALT is 0, the L or unified counter does not run but I/O events 0
related to the counter can occur. If such an event matches the mask in the Start
register, this bit is cleared and counting resumes.

2

HALT_L

-

When this bit is 1, the L or unified counter does not run and no events can occur. A
reset sets this bit. When the HALT_L bit is one, the STOP_L bit is cleared. If you
want to remove the halt condition and keep the SCT in the stop condition (not
running), then you can change the halt and stop condition with one single write to
this register.

3

CLRCTR_L -

Writing a 1 to this bit clears the L or unified counter. This bit always reads as 0.

0

4

BIDIR_L

L or unified counter direction select

0

1

Remark: Once set, only software can clear this bit to restore counter operation.

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0

Up. The counter counts up to its limit condition, then is cleared to zero.

1

Up-down. The counter counts up to its limit, then counts down to a limit condition or
to 0.

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Chapter 31: LPC43xx/LPC43Sxx State Configurable Timer (SCT) with

Table 747. SCT control register (CTRL, address 0x4000 0004) bit description
Bit

Symbol

Value Description

Reset
value

12:5

PRE_L

-

0

Specifies the factor by which the SCT clock is prescaled to produce the L or unified
counter clock. The counter clock is clocked at the rate of the SCT clock divided by
PRE_L+1.
Remark: Clear the counter (by writing a 1 to the CLRCTR bit) whenever changing
the PRE value.

15:13

-

Reserved

16

DOWN_H

-

This bit is 1 when the H counter is counting down. Hardware sets this bit when the
counter limit is reached and BIDIR is 1. Hardware clears this bit when the counter
reaches 0 or when the counter is counting down and a limit condition occurs.

17

STOP_H

-

When this bit is 1 and HALT is 0, the H counter does not run but I/O events related to 0
the counter can occur. If such an event matches the mask in the Start register, this bit
is cleared and counting resumes.

18

HALT_H

-

When this bit is 1, the H counter does not run and no events can occur. A reset sets 1
this bit. When the HALT_H bit is one, the STOP_H bit is cleared. If you want to
remove the halt condition and keep the SCT in the stop condition (not running), then
you can change the halt and stop condition with one single write to this register.

0

Remark: Once set, this bit can only be cleared by software to restore counter
operation.

19

CLRCTR_H -

Writing a 1 to this bit clears the H counter. This bit always reads as 0.

0

20

BIDIR_H

Direction select

0

28:21

PRE_H

0

Up. The H counter counts up to its limit condition, then is cleared to zero.

1

Up-down. The H counter counts up to its limit, then counts down to a limit condition
or to 0.

-

Specifies the factor by which the SCT clock is prescaled to produce the H counter
0
clock. The counter clock is clocked at the rate of the SCT clock divided by PRELH+1.
Remark: Clear the counter (by writing a 1 to the CLRCTR bit) whenever changing
the PRE value.

31:29

-

Reserved

31.3.3 SCT limit register
If UNIFY = 1 in the CONFIG register, only the _L bits are used.
If UNIFY = 0 in the CONFIG register, this register can be written to as two registers
LIMIT_L and LIMIT_H. Both the L and H registers can be read or written individually or in
a single 32-bit read or write operation.
The bits in this register set which events act as counter limits. After a counter has reached
its limit, the counter is cleared to zero in unidirectional mode or changes its direction of
count in bidirectional mode. When the counter reaches all ones, this state is always
treated as a limit event, and the counter is cleared in unidirectional mode or, in
bidirectional mode, begins counting down on the next clock edge - even if no limit event as
defined by the SCT limit register has occurred.
In addition to using this register to specify events that serve as limits, it is also possible to
automatically cause a limit condition whenever a match register 0 match occurs. This
eliminates the need to define an event for the sole purpose of creating a limit. The
AUTOLIMIT_L and AUTOLIMIT_H bits in the configuration register enable/disable this
feature (see Table 746).
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Chapter 31: LPC43xx/LPC43Sxx State Configurable Timer (SCT) with

Table 748. SCT limit register (LIMIT, address 0x4000 0008) bit description
Bit

Symbol

Description

Reset
value

15:0

LIMMSK_L

If bit n is one, event n is used as a counter limit event for the 0
L or unified counter (event 0 = bit 0, event 1 = bit 1, event
15 = bit 15).

31:16

LIMMSK_H

If bit n is one, event n is used as a counter limit event for the 0
H counter (event 0 = bit 16, event 1 = bit 17, event 15 = bit
31).

31.3.4 SCT halt condition register
If UNIFY = 1 in the CONFIG register, only the _L bits are used.
If UNIFY = 0 in the CONFIG register, this register can be written to as two registers
HALT_L and HALT_H. Both the L and H registers can be read or written individually or in a
single 32-bit read or write operation.
Remark: Any event halting the counter disables its operation until software clears the
HALT bit (or bits) in the CTRL register (Table 747).
Table 749. SCT halt condition register (HALT, address 0x4000 000C) bit description
Bit

Symbol

Description

Reset
value

15:0

HALTMSK_L

If bit n is one, event n sets the HALT_L bit in the CTRL register 0
(event 0 = bit 0, event 1 = bit 1, event 15 = bit 15).

31:16 HALTMSK_H

If bit n is one, event n sets the HALT_H bit in the CTRL register 0
(event 0 = bit 16, event 1 = bit 17, event 15 = bit 31).

31.3.5 SCT stop condition register
If UNIFY = 1 in the CONFIG register, only the _L bits are used.
If UNIFY = 0 in the CONFIG register, this register can be written to as two registers
STOP_L and STOP_H. Both the L and H registers can be read or written individually or in
a single 32-bit read or write operation.
Table 750. SCT stop condition register (STOP, address 0x4000 0010) bit description
Bit

Symbol

Description

Reset
value

15:0

STOPMSK_L

If bit n is one, event n sets the STOP_L bit in the CTRL register
(event 0 = bit 0, event 1 = bit 1, event 15 = bit 15).

0

31:16 STOPMSK_H

If bit n is one, event n sets the STOP_H bit in the CTRL register 0
(event 0 = bit 16, event 1 = bit 17, event 15 = bit 31).

31.3.6 SCT start condition register
If UNIFY = 1 in the CONFIG register, only the _L bits are used.
If UNIFY = 0 in the CONFIG register, this register can be written to as two registers
START_L and START_H. Both the L and H registers can be read or written individually or
in a single 32-bit read or write operation.
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Chapter 31: LPC43xx/LPC43Sxx State Configurable Timer (SCT) with

The bits in this register select which events, if any, clear the STOP bit in the Control
register. (Since no events can occur when HALT is 1, only software can clear the HALT bit
by writing the Control register.)
Table 751. SCT start condition register (START, address 0x4000 0014) bit description
Bit

Symbol

Description

Reset
value

15:0

STARTMSK_L

If bit n is one, event n clears the STOP_L bit in the CTRL
register (event 0 = bit 0, event 1 = bit 1, event 15 = bit 15).

0

If bit n is one, event n clears the STOP_H bit in the CTRL
register (event 0 = bit 16, event 1 = bit 17, event 15 = bit 31).

0

31:16 STARTMSK_H

31.3.7 SCT dither condition register
If UNIFY = 1 in the CONFIG register, only the L bits are used.
If UNIFY = 0 in the CONFIG register, this register can be written to as two registers
DITHER_L and DITHER_H. Both the L and H registers can be read or written individually
or in a single 32-bit read or write operation.
When the Dither Condition register contains all zeroes (the default value), the dither
engine advances to the next count in the dither pattern every time the SCT counter
reaches zero (i.e. at the start of every new SCT counter cycle).
It is possible, using this register, to alter that behavior by qualifying the advancement
through the dither pattern with designated events. As with the other condition/mask
registers (HALT, STOP, LIMIT, etc.) each bit in this register corresponds to an event.
Setting one or more of the bits in this register to ones will cause the dither engine to
advance to the next element in the dither pattern (i.e. increment the 16-state cycle
counter) only following SCT counter cycles during which one or more of the designated
dither events have occurred.
There is one, global Dither Condition register per 16-bit SCT. This register controls
advancement through the dither patterns for all of the match registers associated with that
half of the SCT.
For details on the dither engine and the dither pattern, see Section 31.4.1.1.

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Chapter 31: LPC43xx/LPC43Sxx State Configurable Timer (SCT) with

Table 752. SCT dither condition register (DITHER, address 0x4000 0018) bit description
Bit

Symbol

Description

Reset
value

15:0

DITHMSK_L

If bit n is one, the event n causes the dither engine to advance 0
to the next element in the dither pattern at the start of the next
counter cycle of the 16-bit low counter or the unified counter
(event 0 = bit 0, event 1 = bit 1, event 15 = bit 15). If all bits are
set to 0, the dither pattern automatically advances at the start
of every new counter cycle.

31:16 DITHMSK_H

If bit n is one, the event n causes the dither engine to advance 0
to the next element in the dither pattern at the start of the next
counter cycle of the 16-bit high counter (event 0 = bit 0, event 1
= bit 1, event 15 = bit 15). If all bits are set to 0, the dither
pattern automatically advances at the start of every new
counter cycle.

31.3.8 SCT counter register
If UNIFY = 1 in the CONFIG register, the counter is a unified 32-bit register and both the
_L and _H bits are used.
If UNIFY = 0 in the CONFIG register, this register can be written to as two registers
COUNT_L and COUNT_H. Both the L and H registers can be read or written individually
or in a single 32-bit read or write operation. In this case, the L and H registers count
independently under the control of the other registers.
Attempting to write a counter while it is running does not affect the counter but produces a
bus error. Software can read the counter registers at any time.
Table 753. SCT counter register (COUNT, address 0x4000 0040) bit description
Bit

Symbol

Description

Reset
value

15:0

CTR_L

When UNIFY = 0, read or write the 16-bit L counter value. When
UNIFY = 1, read or write the lower 16 bits of the 32-bit unified
counter.

0

31:16

CTR_H

When UNIFY = 0, read or write the 16-bit H counter value. When
UNIFY = 1, read or write the upper 16 bits of the 32-bit unified
counter.

0

31.3.9 SCT state register
If UNIFY = 1 in the CONFIG register, only the _L bits are used.
If UNIFY = 0 in the CONFIG register, this register can be written to as two registers
STATE_L and STATE_H. Both the L and H registers can be read or written individually or
in a single 32-bit read or write operation.
Software can read the state associated with a counter at any time. Writing the state is only
allowed when the counter HALT bit is 1; when HALT is 0, a write attempt does not change
the state and results in a bus error.
The state variable is the main feature that distinguishes the SCT from other counter/timer/
PWM blocks. Events can be made to occur only in certain states. Events, in turn, can
perform the following actions:
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Chapter 31: LPC43xx/LPC43Sxx State Configurable Timer (SCT) with

•
•
•
•

set and clear outputs
limit, stop, and start the counter
cause interrupts and DMA requests
modify the state variable

The value of a state variable is completely under the control of the application. If an
application does not use states, the value of the state variable remains zero, which is the
default value.
A state variable can be used to track and control multiple cycles of the associated counter
in any desired operational sequence. The state variable is logically associated with a state
machine diagram which represents the SCT configuration. See Section 31.3.26 and
31.3.27 for more about the relationship between states and events.
The STATELD/STADEV fields in the event control registers of all defined events set all
possible values for the state variable. The change of the state variable during multiple
counter cycles reflects how the associated state machine moves from one state to the
next.
Table 754. SCT state register (STATE, address 0x4000 0044) bit description
Bit

Symbol

Description

Reset
value

4:0

STATE_L

State variable.

0

15:5

-

Reserved.

-

20:16

STATE_H

State variable.

0

31:21

-

Reserved.

31.3.10 SCT input register
Software can read the state of the SCT inputs in this read-only register in two slightly
different forms. The only situation in which these values are different is if CLKMODE = 2 in
the CONFIG register.
Table 755. SCT input register (INPUT, address 0x4000 0048) bit description

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User manual

Bit

Symbol

Description

Reset
value

0

AIN0

Real-time status of input 0.

pin

1

AIN1

Real-time status of input 1.

pin

2

AIN2

Real-time status of input 2.

pin

3

AIN3

Real-time status of input 3.

pin

4

AIN4

Real-time status of input 4.

pin

5

AIN5

Real-time status of input 5.

pin

6

AIN6

Real-time status of input 6.

pin

7

AIN7

Real-time status of input 7.

pin

15:8

-

Reserved.

-

16

SIN0

Input 0 state synchronized to the SCT clock.

-

17

SIN1

Input 1 state synchronized to the SCT clock.

-

18

SIN2

Input 2 state synchronized to the SCT clock.

-

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Chapter 31: LPC43xx/LPC43Sxx State Configurable Timer (SCT) with

Table 755. SCT input register (INPUT, address 0x4000 0048) bit description
Bit

Symbol

Description

Reset
value

19

SIN3

Input 3 state synchronized to the SCT clock.

-

20

SIN4

Input 4 state synchronized to the SCT clock.

-

21

SIN5

Input 5 state synchronized to the SCT clock.

-

22

SIN6

Input 6 state synchronized to the SCT clock.

-

23

SIN7

Input 7 state synchronized to the SCT clock.

-

31:24

-

Reserved

-

31.3.11 SCT match/capture registers mode register
If UNIFY = 1 in the CONFIG register, only the _L bits of this register are used. The L bits
control whether each set of match/capture registers operates as unified 32-bit
capture/match registers.
If UNIFY = 0 in the CONFIG register, this register can be written to as two registers
REGMODE_L and REGMODE_H. Both the L and H registers can be read or written
individually or in a single 32-bit read or write operation. The _L bits/registers control the L
match/capture registers, and the _H bits/registers control the H match/capture registers.
The SCT contains 16 Match/Capture register pairs. The Register Mode register selects
whether each register pair acts as a Match register (see Section 31.3.20) or as a Capture
register (see Section 31.3.22). Each Match/Capture register has an accompanying
register which serves as a Reload register when the register is used as a Match register
(Section 31.3.23) or as a Capture-Control register when the register is used as a capture
register (Section 31.3.25). REGMODE_H is used only when the UNIFY bit is 0.
An alternate addressing mode is available for all of the Match/Capture and
Reload/Capture-Control registers, for DMA access to halfword registers when UNIFY=0.
This mode is described in Section 31.4.2.
Table 756. SCT match/capture registers mode register (REGMODE, address 0x4000 004C) bit
description
Bit

Symbol

Description

Reset
value

15:0

REGMOD_L

Each bit controls one pair of match/capture registers (register 0 =
bit 0, register 1 = bit 1,..., register 15 = bit 15).

0

0 = registers operate as match registers.
1 = registers operate as capture registers.
31:16 REGMOD_H

Each bit controls one pair of match/capture registers (register 0 =
bit 16, register 1 = bit 17,..., register 15 = bit 31).

0

0 = registers operate as match registers.
1 = registers operate as capture registers.

31.3.12 SCT output register
The SCT supports 16 outputs, each of which has a corresponding bit in this register.
Software can write to any of the output registers when both counters are halted to control
the outputs directly. Writing to this register when either counter is stopped or running does
not affect the outputs and results in a bus error.
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Chapter 31: LPC43xx/LPC43Sxx State Configurable Timer (SCT) with

Software can read this register at any time to sense the state of the outputs.
Table 757. SCT output register (OUTPUT, address 0x4000 0050) bit description
Bit

Symbol

Description

Reset
value

15:0

OUT

Writing a 1 to bit n makes the corresponding output HIGH. 0 makes 0
the corresponding output LOW (output 0 = bit 0, output 1 = bit 1,...,
output 15 = bit 15).

31:16

-

Reserved

31.3.13 SCT bidirectional output control register
This register specifies (for each output) the impact of the counting direction on the
meaning of set and clear operations on the output (see Section 31.3.28 and
Section 31.3.29).
Table 758. SCT bidirectional output control register (OUTPUTDIRCTRL, address 0x4000 0054) bit description
Bit

Symbol

1:0

SETCLR0

3:2

5:4

7:6

9:8

Value Description

Set/clear operation on output 0. Value 0x3 is reserved. Do not program this value.
Independent. Set and clear do not depend on any counter.

0x1

L counter. Set and clear are reversed when counter L or the unified counter is counting
down.

0x2

H counter. Set and clear are reversed when counter H is counting down. Do not use if
UNIFY = 1.
Set/clear operation on output 1. Value 0x3 is reserved. Do not program this value.

0

0x0

Independent. Set and clear do not depend on any counter.

0x1

L counter. Set and clear are reversed when counter L or the unified counter is counting
down.

0x2

H counter. Set and clear are reversed when counter H is counting down. Do not use if
UNIFY = 1.

SETCLR2

Set/clear operation on output 2. Value 0x3 is reserved. Do not program this value.

0

0x0

Independent. Set and clear do not depend on any counter.

0x1

L counter. Set and clear are reversed when counter L or the unified counter is counting
down.

0x2

H counter. Set and clear are reversed when counter H is counting down. Do not use if
UNIFY = 1.

SETCLR3

Set/clear operation on output 3. Value 0x3 is reserved. Do not program this value.

0

0x0

Independent. Set and clear do not depend on any counter.

0x1

L counter. Set and clear are reversed when counter L or the unified counter is counting
down.

0x2

H counter. Set and clear are reversed when counter H is counting down. Do not use if
UNIFY = 1.

SETCLR4

User manual

0

0x0

SETCLR1

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Reset
value

Set/clear operation on output 4. Value 0x3 is reserved. Do not program this value.

0

0x0

Independent. Set and clear do not depend on any counter.

0x1

L counter. Set and clear are reversed when counter L or the unified counter is counting
down.

0x2

H counter. Set and clear are reversed when counter H is counting down. Do not use if
UNIFY = 1.
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Chapter 31: LPC43xx/LPC43Sxx State Configurable Timer (SCT) with

Table 758. SCT bidirectional output control register (OUTPUTDIRCTRL, address 0x4000 0054) bit description
Bit

Symbol

11:
10

SETCLR5

13:
12

15:
14

17:
16

19:
18

21:
20

23:
22

Value Description

Set/clear operation on output 5. Value 0x3 is reserved. Do not program this value.
Independent. Set and clear do not depend on any counter.

0x1

L counter. Set and clear are reversed when counter L or the unified counter is counting
down.

0x2

H counter. Set and clear are reversed when counter H is counting down. Do not use if
UNIFY = 1.
Set/clear operation on output 6. Value 0x3 is reserved. Do not program this value.

0

0x0

Independent. Set and clear do not depend on any counter.

0x1

L counter. Set and clear are reversed when counter L or the unified counter is counting
down.

0x2

H counter. Set and clear are reversed when counter H is counting down. Do not use if
UNIFY = 1.

SETCLR7

Set/clear operation on output 7. Value 0x3 is reserved. Do not program this value.

0

0x0

Independent. Set and clear do not depend on any counter.

0x1

L counter. Set and clear are reversed when counter L or the unified counter is counting
down.

0x2

H counter. Set and clear are reversed when counter H is counting down. Do not use if
UNIFY = 1.

SETCLR8

Set/clear operation on output 8. Value 0x3 is reserved. Do not program this value.

0

0x0

Independent. Set and clear do not depend on any counter.

0x1

L counter. Set and clear are reversed when counter L or the unified counter is counting
down.

0x2

H counter. Set and clear are reversed when counter H is counting down. Do not use if
UNIFY = 1.

SETCLR9

Set/clear operation on output 9. Value 0x3 is reserved. Do not program this value.

0

0x0

Independent. Set and clear do not depend on any counter.

0x1

L counter. Set and clear are reversed when counter L or the unified counter is counting
down.

0x2

H counter. Set and clear are reversed when counter H is counting down. Do not use if
UNIFY = 1.

SETCLR10

Set/clear operation on output 5. Value 0x3 is reserved. Do not program this value.

0

0x0

Independent. Set and clear do not depend on any counter.

0x1

L counter. Set and clear are reversed when counter L or the unified counter is counting
down.

0x2

H counter. Set and clear are reversed when counter H is counting down. Do not use if
UNIFY = 1.

SETCLR11

User manual

0

0x0

SETCLR6

UM10503

Reset
value

Set/clear operation on output 11. Value 0x3 is reserved. Do not program this value.

0

0x0

Independent. Set and clear do not depend on any counter.

0x1

L counter. Set and clear are reversed when counter L or the unified counter is counting
down.

0x2

H counter. Set and clear are reversed when counter H is counting down. Do not use if
UNIFY = 1.

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Chapter 31: LPC43xx/LPC43Sxx State Configurable Timer (SCT) with

Table 758. SCT bidirectional output control register (OUTPUTDIRCTRL, address 0x4000 0054) bit description
Bit

Symbol

25:
24

SETCLR12

27:
26

29:
28

31:
30

Value Description

Reset
value

Set/clear operation on output 12. Value 0x3 is reserved. Do not program this value.

0

0x0

Independent. Set and clear do not depend on any counter.

0x1

L counter. Set and clear are reversed when counter L or the unified counter is counting
down.

0x2

H counter. Set and clear are reversed when counter H is counting down. Do not use if
UNIFY = 1.

SETCLR13

Set/clear operation on output 13. Value 0x3 is reserved. Do not program this value.

0

0x0

Independent. Set and clear do not depend on any counter.

0x1

L counter. Set and clear are reversed when counter L or the unified counter is counting
down.

0x2

H counter. Set and clear are reversed when counter H is counting down. Do not use if
UNIFY = 1.

SETCLR14

Set/clear operation on output 14. Value 0x3 is reserved. Do not program this value.

0

0x0

Independent. Set and clear do not depend on any counter.

0x1

L counter. Set and clear are reversed when counter L or the unified counter is counting
down.

0x2

H counter. Set and clear are reversed when counter H is counting down. Do not use if
UNIFY = 1.

SETCLR15

Set/clear operation on output 15. Value 0x3 is reserved. Do not program this value.

0

0x0

Independent. Set and clear do not depend on any counter.

0x1

L counter. Set and clear are reversed when counter L or the unified counter is counting
down.

0x2

H counter. Set and clear are reversed when counter H is counting down. Do not use if
UNIFY = 1.

31.3.14 SCT conflict resolution register
The registers OUTPUTSETn (Section 31.3.28) and OUTPUTCLn (Section 31.3.29) allow
both setting and clearing to be indicated for an output in the same clock cycle, even for the
same event. This SCT conflict resolution register resolves this conflict.
To enable an event to toggle an output, set the OnRES value to 0x3 in this register, and
set the event bits in both the Set and Clear registers.
Table 759. SCT conflict resolution register (RES, address 0x4000 0058) bit description

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Bit

Symbol

1:0

O0RES

Value Description

Effect of simultaneous set and clear on output 0.
0x0

No change.

0x1

Set output (or clear based on the SETCLR0 field).

0x2

Clear output (or set based on the SETCLR0 field).

0x3

Toggle output.

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value

0

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Chapter 31: LPC43xx/LPC43Sxx State Configurable Timer (SCT) with

Table 759. SCT conflict resolution register (RES, address 0x4000 0058) bit description
Bit

Symbol

3:2

O1RES

5:4

Value Description

Effect of simultaneous set and clear on output 1.

9:8

11:
10

13:
12

No change.

0x1

Set output (or clear based on the SETCLR1 field).

0x2

Clear output (or set based on the SETCLR1 field).

0x3

Toggle output.

0x0

No change.

0x1

Set output (or clear based on the SETCLR2 field).

0x2

Clear output n (or set based on the SETCLR2 field).

O2RES

Effect of simultaneous set and clear on output 2.

O3RES
0x0

No change.

0x1

Set output (or clear based on the SETCLR3 field).

0x2

Clear output (or set based on the SETCLR3 field).

0x3

Toggle output.

O4RES

Effect of simultaneous set and clear on output 4.
0x0

No change.

0x1

Set output (or clear based on the SETCLR4 field).

0x2

Clear output (or set based on the SETCLR4 field).

0x3

Toggle output.

O5RES

Effect of simultaneous set and clear on output 5.
0x0

No change.

0x1

Set output (or clear based on the SETCLR5 field).

0x2

Clear output (or set based on the SETCLR5 field).

0x3

Toggle output.

O6RES

Effect of simultaneous set and clear on output 6.
0x0

No change.

0x1

Set output (or clear based on the SETCLR6 field).

0x2

Clear output (or set based on the SETCLR6 field).

17:
16

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O7RES

0

0

0

0

Toggle output.
Effect of simultaneous set and clear on output 7.

0x0

No change.

0x1

Set output (or clear based on the SETCLR7 field).

0x2

Clear output (or set based on the SETCLR7 field).

0x3

Toggle output.

O8RES

0

Toggle output.
Effect of simultaneous set and clear on output 3.

0x3
15:
14

0

0x0

0x3
7:6

Reset
value

Effect of simultaneous set and clear on output 8.
0x0

No change.

0x1

Set output (or clear based on the SETCLR8 field).

0x2

Clear output (or set based on the SETCLR8 field).

0x3

Toggle output.

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Chapter 31: LPC43xx/LPC43Sxx State Configurable Timer (SCT) with

Table 759. SCT conflict resolution register (RES, address 0x4000 0058) bit description
Bit

Symbol

19:
18

O9RES

21:
20

Value Description

Effect of simultaneous set and clear on output 9.
0x0

No change.

0x1

Set output (or clear based on the SETCLR9 field).

0x2

Clear output (or set based on the SETCLR9 field).

0x3

Toggle output.

O10RES

25:
24

27:
26

29:
28

Effect of simultaneous set and clear on output 10.

0

No change.

0x1

Set output (or clear based on the SETCLR10 field).

0x2

Clear output (or set based on the SETCLR10 field).

O11RES

Toggle output.
Effect of simultaneous set and clear on output 11.

0

0x0

No change.

0x1

Set output (or clear based on the SETCLR11 field).

0x2

Clear output (or set based on the SETCLR11 field).

0x3

Toggle output.

O12RES

Effect of simultaneous set and clear on output 12.
0x0

0

No change.

0x1

Set output (or clear based on the SETCLR12 field).

0x2

Clear output (or set based on the SETCLR12 field).

0x3

Toggle output.

O13RES

Effect of simultaneous set and clear on output 13.

0

0x0

No change.

0x1

Set output (or clear based on the SETCLR13 field).

0x2

Clear output (or set based on the SETCLR13 field).

0x3

Toggle output.

O14RES

Effect of simultaneous set and clear on output 14.

0

0x0

No change.

0x1

Set output (or clear based on the SETCLR14 field).

0x2

Clear output (or set based on the SETCLR14 field).

0x3
31:
30

0

0x0

0x3
23:
22

Reset
value

O15RES

Toggle output.
Effect of simultaneous set and clear on output 15.

0

0x0

No change.

0x1

Set output (or clear based on the SETCLR15 field).

0x2

Clear output (or set based on the SETCLR15 field).

0x3

Toggle output.

31.3.15 SCT DMA request 0 and 1 registers
The SCT includes two DMA request outputs. These registers enable the DMA requests to
be triggered when a particular event occurs or when counter Match registers are loaded
from its Reload registers.
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Chapter 31: LPC43xx/LPC43Sxx State Configurable Timer (SCT) with

Table 760. SCT DMA 0 request register (DMAREQ0, address 0x4000 005C) bit description
Bit

Symbol

Description

Reset
value

15:0

DEV_0

If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 0
1 = bit 1,..., event 15 = bit 15).

29:16

-

Reserved

30

DRL0

A 1 in this bit makes the SCT set DMA request 0 when it loads
the Match_L/Unified registers from the Reload_L/Unified
registers.

31

DRQ0

This read-only bit indicates the state of DMA Request 0

-

Table 761. SCT DMA 1 request register (DMAREQ1, address 0x4000 0060) bit description
Bit

Symbol

Description

Reset
value

15:0

DEV_1

If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 0
1 = bit 1,..., event 15 = bit 15).

29:16

-

Reserved

30

DRL1

A 1 in this bit makes the SCT set DMA request 1 when it loads
the Match L/Unified registers from the Reload L/Unified
registers.

31

DRQ1

This read-only bit indicates the state of DMA Request 1.

-

31.3.16 SCT flag enable register
This register enables flags to request an interrupt if the FLAGn bit in the SCT event flag
register (Section 31.3.17) is also set.
Table 762. SCT flag enable register (EVEN, address 0x4000 00F0) bit description
Bit

Symbol

Description

Reset
value

15:0

IEN

The SCT requests interrupt when bit n of this register and the event 0
flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event
15 = bit 15).

31:16

-

Reserved

31.3.17 SCT event flag register
This register records events. Writing ones to this register clears the corresponding flags
and negates the SCT interrupt request if all enabled Flag bits are zero.
Table 763. SCT event flag register (EVFLAG, address 0x4000 00F4) bit description
Bit

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Symbol

Description

Reset
value

15:0 FLAG

Bit n is one if event n has occurred since reset or a 1 was last written to
this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15).

0

31:
16

Reserved

-

-

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Chapter 31: LPC43xx/LPC43Sxx State Configurable Timer (SCT) with

31.3.18 SCT conflict enable register
This register enables the “no change conflict” events specified in the SCT conflict
resolution register to request an interrupt.
Table 764. SCT conflict enable register (CONEN, address 0x4000 00F8) bit description
Bit

Symbol

Description

Reset
value

15:0

NCEN

The SCT requests interrupt when bit n of this register and the SCT 0
conflict flag register are both one (output 0 = bit 0, output 1 = bit
1,..., output 15 = bit 15).

31:16

-

Reserved

31.3.19 SCT conflict flag register
This register records interrupt-enabled no-change conflict events and provides details of a
bus error. Writing ones to the NCFLAG bits clears the corresponding read bits and
negates the SCT interrupt request if all enabled Flag bits are zero.
Table 765. SCT conflict flag register (CONFLAG, address 0x4000 00FC) bit description
Bit

Symbol

Description

Reset
value

15:0

NCFLAG

Bit n is one if a no-change conflict event occurred on output n
since reset or a 1 was last written to this bit (output 0 = bit 0,
output 1 = bit 1,..., output 15 = bit 15).

0

29:16

-

Reserved.

-

30

BUSERRL

The most recent bus error from this SCT involved writing CTR
L/Unified, STATE L/Unified, MATCH L/Unified, or the Output
register when the L/U counter was not halted. A word write to
certain L and H registers can be half successful and half
unsuccessful.

0

31

BUSERRH

The most recent bus error from this SCT involved writing CTR
H, STATE H, MATCH H, or the Output register when the H
counter was not halted.

0

31.3.20 SCT match registers 0 to 15 (REGMODEn bit = 0)
Match registers are compared to the counters to help create events. When the UNIFY bit
is 0, the L and H registers are independently compared to the L and H counters. When
UNIFY is 1, the L and H registers hold a 32-bit value that is compared to the unified
counter. A Match can only occur in a clock in which the counter is running (STOP and
HALT are both 0).
Match registers can be read at any time. Writing to a Match register while the associated
counter is running does not affect the Match register and results in a bus error. Match
events occur in the SCT clock in which the counter is (or would be) incremented to the
next value. When a Match event limits its counter as described in Section 31.3.3, the
value in the Match register is the last value of the counter before it is cleared to zero (or
decremented if BIDIR is 1).

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Chapter 31: LPC43xx/LPC43Sxx State Configurable Timer (SCT) with

There is no “write-through” from Reload registers to Match registers. Before starting a
counter, software can write one value to the Match register used in the first cycle of the
counter and a different value to the corresponding Match Reload register used in the
second cycle.
Table 766. SCT match registers 0 to 15 (MATCH[0:15], address 0x4000 0100 (MATCH0) to
0x4000 4013C (MATCH15)) bit description (REGMODEn bit = 0)
Bit

Symbol

Description

Reset
value

15:0

MATCHn_L When UNIFY = 0, read or write the 16-bit value to be compared to
the L counter. When UNIFY = 1, read or write the lower 16 bits of
the 32-bit value to be compared to the unified counter.

0

31:16

MATCHn_H When UNIFY = 0, read or write the 16-bit value to be compared to
the H counter. When UNIFY = 1, read or write the upper 16 bits of
the 32-bit value to be compared to the unified counter.

0

31.3.21 SCT fractional match registers 0 to 5
Fractional Match registers are provided for up to the first six of the match registers. The
values programmed in these registers provide higher average resolution over time by
applying a dither pattern as described in Section 31.4.1.1. This dither pattern results in
delaying recognition of a match for one counter clock for n (0 to 15) out of every 16
counter cycles. The value of n is programmed in these Fractional Match registers.
Fractional Match registers can be read at any time. Writing to a Fractional Match register
while the associated counter is running will not affect the register and will result in a bus
error.
Each Fractional Match register has a Fractional Match Reload register associated with it.
The contents of the reload registers are transferred into the Fractional Match registers at
the start of every new SCT counter cycle unless the NORELOAD bit for the appropriate
half-counter is set.
The reload registers may be written to at any time, regardless of whether or not the
counter is running.
There is no write-through from the Fractional Match Reload registers to the Fractional
Match registers. Before starting a counter, software can write one value to the Fractional
Match register that will be used in the first cycle or period of operation, and a different
value to the corresponding Fractional Match Reload register that will be used in the
second cycle or period.
An alternate addressing mode is available for all of the Fractional Match registers for DMA
access to halfword registers when UNIFY=0. See Section 31.4.2.

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Chapter 31: LPC43xx/LPC43Sxx State Configurable Timer (SCT) with

Table 767. SCT fractional match registers 0 to 5 (FRACMAT[0:5], address 0x4000 0140
(FRACMAT0) to 0x4000 40154 (FRACMAT5)) bit description
Bit

Symbol

Description

Reset
value

3:0

FRACMAT_L

When UNIFY = 0, read or write the 4-bit value specifying the
dither pattern to be applied to the corresponding MATCHn_L
register (n = 0 to 5). When UNIFY = 1, the value applies to the
unified, 32-bit fractional match register.

0

15:4

-

Reserved.

-

19:16

FRACMAT_H

When UNIFY = 0, read or write 4-bit value specifying the dither
pattern to be applied to the corresponding MATCHn_H register
(n = 0 to 5).

0

31:20

-

Reserved.

-

[1]

See Section 31.4.1.1 for selecting the dither pattern.

31.3.22 SCT capture registers 0 to 15 (REGMODEn bit = 1)
These registers allow software to read the counter values at which the event selected by
the corresponding Capture Control registers occurred.
Table 768. SCT capture registers 0 to 15 (CAP[0:15], address 0x4000 0100 (CAP0) to 0x4000
013C (CAP15)) bit description (REGMODEn bit = 1)
Bit

Symbol

Description

Reset
value

15:0

CAP_L

When UNIFY = 0, read the 16-bit counter value at which this
0
register was last captured. When UNIFY = 1, read the lower 16 bits
of the 32-bit value at which this register was last captured.

31:16

CAP_H

When UNIFY = 0, read the 16-bit counter value at which this
0
register was last captured. When UNIFY = 1, read the upper 16 bits
of the 32-bit value at which this register was last captured.

31.3.23 SCT match reload registers 0 to 15 (REGMODEn bit = 0)
A Match register (L, H, or unified 32-bit) is loaded from the corresponding Reload register
when BIDIR is 0 and the counter reaches its limit condition, or when BIDIR is 1 and the
counter reaches 0.
Table 769. SCT match reload registers 0 to 15 (MATCHREL[0:15], address 0x4000 0200
(MATCHREL0) to 0x4000 023C (MATCHREL15) bit description (REGMODEn bit =
0)

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Bit

Symbol

Description

Reset
value

15:0

RELOAD_L

When UNIFY = 0, read or write the 16-bit value to be loaded into
the MATCHn_L register. When UNIFY = 1, read or write the lower
16 bits of the 32-bit value to be loaded into the MATCHn register.

0

31:16 RELOAD_H

When UNIFY = 0, read or write the 16-bit to be loaded into the
MATCHn_H register. When UNIFY = 1, read or write the upper 16
bits of the 32-bit value to be loaded into the MATCHn register.

0

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Chapter 31: LPC43xx/LPC43Sxx State Configurable Timer (SCT) with

31.3.24 SCT fractional match reload registers 0 to 5
A Fractional Match register (L, H, or unified 32-bit) is loaded from the corresponding
Fractional Match Reload register when BIDIR is 0 and the counter reaches its limit
condition, or BIDIR is 1 and the counter reaches 0, unless the appropriate NORELOAD bit
is set.
An alternate addressing mode is available for all Fractional Match Reload registers for
DMA access to halfword registers when UNIFY=0. See Section 31.4.2.
Table 770. SCT fractional match reload registers 0 to 5 (FRACMATREL[0:5], address 0x4000
0240 (FRACMATREL0) to 0x4000 0254 (FRACMATREL5) bit description
Bit

Symbol

Description

Reset
value

3:0

RELFRAC_L When UNIFY = 0, read or write the 4-bit value to be loaded into the 0
FRACMATn_L register. When UNIFY = 1, read or write the lower 4
bits to be loaded into the FRACMATn register.

15:4

-

Reserved.

-

19:16 RELFRAC_H When UNIFY = 0, read or write the 4-bit value to be loaded into the 0
FRACMATn_H register. When UNIFY = 1, read or write the upper 4
bits with the 4-bit value to be loaded into the FRACMATn register.
31:20 -

Reserved.

-

31.3.25 SCT capture control registers 0 to 15 (REGMODEn bit = 1)
If UNIFY = 1 in the CONFIG register, only the _L bits are used.
If UNIFY = 0 in the CONFIG register, this register can be written to as two registers
CAPCTRLn_L and CAPCTRLn_H. Both the L and H registers can be read or written
individually or in a single 32-bit read or write operation.
Each Capture Control register (L, H, or unified 32-bit) controls which events load the
corresponding Capture register from the counter.
Table 771. SCT capture control registers 0 to 15 (CAPCTRL- address 0x4000 0200
(CAPCTRL0) to 0x4000 023C (CAPCTRL15)) bit description (REGMODEn bit = 1)
Bit

Symbol

Description

Reset
value

15:0

CAPCON_L

If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the 0
CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1
= bit 1,..., event 15 = bit 15).

31:16

CAPCON_H

If bit m is one, event m causes the CAPn_H (UNIFY = 0)
0
register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event
15 = bit 31).

31.3.26 SCT event state mask registers 0 to 15
Each event has one associated SCT event state mask register that allows this event to
happen in one or more states of the counter selected by the HEVENT bit in the
corresponding EVCTRLn register.
An event n is disabled when its EVSTATEMSKn register contains all zeros, since it is
masked regardless of the current state.
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Chapter 31: LPC43xx/LPC43Sxx State Configurable Timer (SCT) with

In simple applications that do not use states, write 0x01 to this register to enable an event.
Since the state always remains at its reset value of 0, writing 0x01 effectively permanently
state-enables this event.
Table 772. SCT event state mask registers 0 to 15 (EV[0:15]_STATE, addresses 0x4000 0300
(EV0_STATE) to 0x4000 0378 (EV15_STATE)) bit description
Bit

Symbol

Description

Reset
value

31:0

STATEMSK

If bit m is one, event n (n= 0 to 15) happens in state m of the
0
counter selected by the HEVENT bit (m = state number; state 0 =
bit 0, state 1= bit 1,..., state 31 = bit 31).

31.3.27 SCT event control registers 0 to 15
This register defines the conditions for event n to occur, other than the state variable
which is defined by the state mask register. Most events are associated with a particular
counter (high, low, or unified), in which case the event can depend on a match to that
register. The other possible ingredient of an event is a selected input or output signal.
When the UNIFY bit is 0, each event is associated with a particular counter by the
HEVENT bit in its event control register. An event cannot occur when its related counter is
halted nor when the current state is not enabled to cause the event as specified in its
event mask register. An event is permanently disabled when its event state mask register
contains all zeros.
An enabled event can be programmed to occur based on a selected input or output edge
or level and/or based on its counter value matching a selected match register. In BIDR
mode, events can also be enabled based on the count direction.
Each event can modify its counter STATE value. If more than one event associated with
the same counter occurs in a given clock cycle, only the state change specified for the
highest-numbered event among them takes place. Other actions dictated by any
simultaneously occurring events all take place.
Table 773. SCT event control register 0 to 15 (EV[0:15]_CTRL, address 0x4000 0304 (EV0_CTRL) to 0x4000 037C
(EV15_CTRL)) bit description
Bit

Symbol

Value Description

3:0

MATCHSEL

-

4

HEVENT

5

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0

0

L state. Selects the L state and the L match register selected by MATCHSEL.

1

H state. Selects the H state and the H match register selected by MATCHSEL.

OUTSEL

IOSEL

Selects the Match register associated with this event (if any). A match can occur only 0
when the counter selected by the HEVENT bit is running.
Select L/H counter. Do not set this bit if UNIFY = 1.

Input/output select
0

9:6

Reset
value

0

Input. Selects the input selected by IOSEL.

1

Output. Selects the output selected by IOSEL.

-

Selects the input or output signal associated with this event (if any). Do not select an
input in this register, if CKMODE is 1x. In this case the clock input is an implicit
ingredient of every event.

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Chapter 31: LPC43xx/LPC43Sxx State Configurable Timer (SCT) with

Table 773. SCT event control register 0 to 15 (EV[0:15]_CTRL, address 0x4000 0304 (EV0_CTRL) to 0x4000 037C
(EV15_CTRL)) bit description
Bit

Symbol

Value Description

11:10 IOCOND

Selects the I/O condition for event n. (The detection of edges on outputs lags the
conditions that switch the outputs by one SCT clock). In order to guarantee proper
edge/state detection, an input must have a minimum pulse width of at least one SCT
clock period.
0x0

LOW

0x1

Rise

0x2

Fall

0x3

HIGH

13:12 COMBMODE

14

Reset
value

Selects how the specified match and I/O condition are used and combined.
0x0

OR. The event occurs when either the specified match or I/O condition occurs.

0x1

MATCH. Uses the specified match only.

0x2

IO. Uses the specified I/O condition only.

0x3

AND. The event occurs when the specified match and I/O condition occur
simultaneously.

STATELD

0

0

This bit controls how the STATEV value modifies the state selected by HEVENT when 0
this event is the highest-numbered event occurring for that state.
0

STATEV value is added into STATE (the carry-out is ignored).

1

STATEV value is loaded into STATE.

19:15 STATEV

This value is loaded into or added to the state selected by HEVENT, depending on
STATELD, when this event is the highest-numbered event occurring for that state. If
STATELD and STATEV are both zero, there is no change to the STATE value.

20

If this bit is one and the COMBMODE field specifies a match component to the
triggering of this event, then a match is considered to be active whenever the counter
value is GREATER THAN OR EQUAL TO the value specified in the match register
when counting up, LESS THEN OR EQUAL TO the match value when counting down.

MATCHMEM

0

If this bit is zero, a match is only be active during the cycle when the counter is equal
to the match value.
22:21 DIRECTION

31:23 -

Direction qualifier for event generation. This field only applies when the counters are
operating in BIDIR mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is
reserved.
0x0

Direction independent. This event is triggered regardless of the count direction.

0x1

Counting up. This event is triggered only during up-counting when BIDIR = 1.

0x2

Counting down. This event is triggered only during down-counting when BIDIR = 1.
Reserved

31.3.28 SCT output set registers 0 to 15
Each output n has one set register that controls how events affect each output. Whether
outputs are set or cleared depends on the setting of the SETCLRn field in the
OUTPUTDIRCTRL register.

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Chapter 31: LPC43xx/LPC43Sxx State Configurable Timer (SCT) with

Table 774. SCT output set register 0 to 15 (OUT[0:15]_SET, address 0x4000 0500 (OUT0_SET)
to 0x4000 0578 (OUT15_SET)) bit description
Bit

Symbol

Description

Reset
value

15:0

SET

A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0
0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.

31:16

-

Reserved

31.3.29 SCT output clear registers 0 to 15
Each output n has one clear register that controls how events affect each output. Whether
outputs are set or cleared depends on the setting of the SETCLRn field in the
OUTPUTDIRCTRL register.
Table 775. SCT output clear register 0 to 15 (OUT[0:15]_CLR, address 0x4000 0504
(OUT0_CLR) to 0x4000 057C (OUT15_CLR)) bit description
Bit

Symbol

Description

Reset
value

15:0

CLR

A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0
0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.

31:16

-

Reserved

31.4 Functional description
31.4.1 Fractional matches
The first 6 match registers may be configured to have a fractional portion to their match
values. Higher average resolution is achievable on the match registers with associated
fractional match register by using a dithering mechanism. The dither engine delays the
assertion of a match by one counter clock every n (0 to 15) out of 16 counter cycles. The
value of n is specified in the 4-bit FRACMAT register associated with each of the first six
match registers.
Dithering can be disabled on any of the match registers by loading all zeroes (the default
value) into its FRACMAT register.

31.4.1.1 Dithering
At the start of each new SCT counter cycle (i.e. when the counter counts-down to zero in
bi-directional mode or is cleared to zero by a limit event), the dither engine determines
which matches are to be delayed by one clock during the coming counter cycle. Delaying
the match effectively adds 1 to the designated match value when up-counting or subtracts
1 when down-counting, during that particular counter cycle.
For each dither-enabled match register, the value programmed in its associated
FRACMAT register specifies how many out of every 16 counter cycles its match is to be
delayed. An algorithm applied to the FRACMAT value distributes this number as evenly as
possible across the 16 counter cycles. This results in a unique dither pattern for each
match register (SeeTable 776).

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Chapter 31: LPC43xx/LPC43Sxx State Configurable Timer (SCT) with

Additional control over the dithering process is provided to the user via a Dither Condition
(event-mask) register. Typically, the dither engine advances though the match dither
patterns at the start of every new SCT counter cycle. The Dither Condition register allows
the user to specify that advancement to the next element in the dither patterns will only
occur if one or more designated events occurred during the previous cycle of the counter.
The dither algorithm is designed to spread out the cycles in which the matches are
delayed as evenly as possible across the 16 counter cycles. The following table shows the
dither pattern that is applied for each value of FRACMAT. A ‘D’ indicates the counter
cycles where a match on the relevant match register is delayed.
Table 776. Dither pattern
Counter cycle
FRACMAT 0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

0x0

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

0x1

-

-

-

-

-

-

-

-

D

-

-

-

-

-

-

-

0x2

-

-

-

-

D

-

-

-

-

-

-

-

D

-

-

-

0x3

-

-

-

-

D

-

-

-

D

-

-

-

D

-

-

-

0x4

-

-

D

-

-

-

D

-

-

-

D

-

-

-

D

-

0x5

-

-

D

-

-

-

D

-

D

-

D

-

-

-

D

-

0x6

-

-

D

-

D

-

D

-

-

-

D

-

D

-

D

-

0x7

-

-

D

-

D

-

D

-

D

-

D

-

D

-

D

-

0x8

-

D

-

D

-

D

-

D

-

D

-

D

-

D

-

D

0x9

-

D

-

D

-

D

-

D

D

D

-

D

-

D

-

D

0xA

-

D

-

D

D

D

-

D

-

D

-

D

D

D

-

D

0xB

-

D

-

D

D

D

-

D

D

D

-

D

D

D

-

D

0xC

-

D

D

D

-

D

D

D

-

D

D

D

-

D

D

D

0xD

-

D

D

D

-

D

D

D

D

D

D

D

-

D

D

D

0xE

-

D

D

D

D

D

D

D

-

D

D

D

D

D

D

D

0xF

-

D

D

D

D

D

D

D

D

D

D

D

D

D

D

D

31.4.2 Alternate addressing for match/capture registers
The Match, Reload, Fractional match, Fractional match reload, Capture, and Capture
Control registers are arranged as consecutive words, with the standard division of each
word into two halfwords. When the UNIFY bit is zero, these two halfwords are related to
the L and H counters. Software has the option of writing words initially to set up both
halves of the SCT simultaneously, or writing halfwords to set up each half separately.
Applications can use a DMA controller to write Reload registers or to read Capture
registers. However, when UNIFY is 0, the addressing of the halfword registers is not
compatible with the requirement of many DMA controllers to use consecutive addresses
for sequential address operation. Table 777 shows how the second half of the range
occupied by each type of register contains an alternate address map for halfword
accesses to the same registers, which is compatible with DMA that use sequential
address operation. When UNIFY is 1, perform DMA word accesses using standard
offsets.

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Chapter 31: LPC43xx/LPC43Sxx State Configurable Timer (SCT) with

Table 777. Alternate address map for DMA halfword access
Match register

Capture register

Standard offset

DMA halfword offset

MATCH0_L

CAP0_L

0x100

0x180

MATCH0_H

CAP0_H

0x102

0x1C0

MATCH1_L

CAP1_L

0x104

0x182

MATCH1_H

CAP1_H

0x106

0x1C2

...

...

...

...

MATCHREL0_L

CAPCTRL0_L

0x200

0x280

MATCHREL0_H

CAPCTRL0_H

0x202

0x2C0

MATCHREL1_L

CAPCTRL1_L

0x204

0x282

MATCHREL1_H

CAPCTRL1_H

0x206

0x2C2

...

...

...

...

FRACMAT0_L

-

0x140

0x1A0

FRACMAT0_H

-

0x142

0x1E0

FRACMAT1_L

-

0x144

0x1A2

FRACMAT1_H

-

0x146

0x1E2

...

-

...

...

RELFRAC0_L

-

0x240

0x2A0

RELFRAC0_H

-

0x242

0x2E0

RELFRAC1_L

-

0x244

0x2A2

RELFRAC1_H

-

0x246

0x2E2

...

-

...

...

31.5 SCT Example
Figure 107 shows a simple application of the SCT using two sets of match events (EV0/1
and EV3/4) to set/clear SCT output 0. The timer is automatically reset whenever it
reaches the MAT0 match value.
In the initial state 0, match event EV0 sets output 0 to HIGH and match event EV1 clears
output 0. The SCT input 0 is monitored: If input0 is found LOW by the next time the timer
is reset(EV2), the state is changed to state 1, and EV3/4 are enabled, which create the
same output but triggered by different match values. If input 0 is found HIGH by the next
time the timer is reset, the associated event (EV5) causes the state to change back to
state 0where the events EV0 and EV1 are enabled.
The example uses the following SCT configuration:

•
•
•
•
•

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1 input
1 output
5 match registers
6 events and match 0 used with autolimit function
2 states

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Chapter 31: LPC43xx/LPC43Sxx State Configurable Timer (SCT) with

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Fig 107. SCT configuration example

This application of the SCT uses the following configuration (all register values not listed
in Table 745 are set to their default values):
Table 778. SCT configuration example
Configuration

Counter

Registers

Setting

CONFIG

Uses one counter (UNIFY = 1).

CONFIG

Enable the autolimit for MAT0. (AUTOLIMIT = 1.)

CTRL

Uses unidirectional counter (BIDIR_L = 0).

Clock base

CONFIG

Uses default values for clock configuration.

Match/Capture registers

REGMODE

Configure one match register for each match event by setting
REGMODE_L bits 0,1, 2, 3, 4 to 0. This is the default.

Define match values

MATCH0/1/2/3/4

Set a match value MATCH0/1/2/3/4_L in each register. The match 0
register serves as an automatic limit event that resets the counter.
without using an event. To enable the automatic limit, set the
AUTOLIMIT bit in the CONFIG register.

Define match reload
values

MATCHREL0/1/2/3/4

Set a match reload value RELOAD0/1/2/3/4_L in each register
(same as the match value in this example).

Define when event 0
occurs

EVCTRL0

Define when event 1
occurs

EVCTRL1

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•
•

Set COMBMODE = 0x1. Event 0 uses match condition only.

•
•

Set COMBMODE = 0x1. Event 1 uses match condition only.

Set MATCHSEL = 1. Select match value of match register 1.
The match value of MAT1 is associated with event 0.
Set MATCHSEL = 2 Select match value of match register 2. The
match value of MAT2 is associated with event 1.

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Chapter 31: LPC43xx/LPC43Sxx State Configurable Timer (SCT) with

Table 778. SCT configuration example
Configuration

Registers

Define when event 2
occurs

EVCTRL2

Define how event 2
changes the state

EVCTRL2

Define when event 3
occurs

EVCTRL3

Define when event 4
occurs

EVCTRL4

Define when event 5
occurs

EVCTRL5

Setting

•

Set COMBMODE = 0x3. Event 2 uses match condition and I/O
condition.

•
•
•

Set IOSEL = 0. Select input 0.
Set IOCOND = 0x0. Input 0 is LOW.
Set MATCHSEL = 0. Chooses match register 0 to qualify the
event.

Set STATEV bits to 1 and the STATED bit to 1. Event 2 changes the
state to state 1.

•
•

Set COMBMODE = 0x1. Event 3 uses match condition only.

•
•

Set COMBMODE = 0x1. Event 4 uses match condition only.

•

Set COMBMODE = 0x3. Event 5 uses match condition and I/O
condition.

•
•
•

Set IOSEL = 0. Select input 0.

Set MATCHSEL = 0x3. Select match value of match register 3.
The match value of MAT3 is associated with event 3..
Set MATCHSEL = 0x4. Select match value of match register
4.The match value of MAT4 is associated with event 4.

Set IOCOND = 0x3. Input 0 is HIGH.
Set MATCHSEL = 0. Chooses match register 0 to qualify the
event.

Define how event 5
changes the state

EVCTRL5

Set STATEV bits to 0 and the STATED bit to 1. Event 5 changes the
state to state 0.

Define by which events
output 0 is set

OUTPUTSET0

Set SET0 bits 0 (for event 0) and 3 (for event 3) to one to set the
output when these events 0 and 3 occur.

Define by which events
output 0 is cleared

OUTPUTCLR0

Set CLR0 bits 1 (for events 1) and 4 (for event 4) to one to clear the
output when events 1 and 4 occur.

Configure states in which EVSTATEMSK0
event 0 is enabled

Set STATEMSK0 bit 0 to 1. Set all other bits to 0. Event 0 is enabled
in state 0.

Configure states in which EVSTATEMSK1
event 1 is enabled

Set STATEMSK1 bit 0 to 1. Set all other bits to 0. Event 1 is enabled
in state 0.

Configure states in which EVSTATEMSK2
event 2 is enabled

Set STATEMSK2 bit 0 to 1. Set all other bits to 0. Event 2 is enabled
in state 0.

Configure states in which EVSTATEMSK3
event 3 is enabled

Set STATEMSK3 bit 1 to 1. Set all other bits to 0. Event 3 is enabled
in state 1.

Configure states in which EVSTATEMSK4
event 4 is enabled

Set STATEMSK4 bit 1 to 1. Set all other bits to 0. Event 4 is enabled
in state 1.

Configure states in which EVSTATEMSK5
event 5 is enabled

Set STATEMSK5 bit 1 to 1. Set all other bits to 0. Event 5 is enabled
in state 1.

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Chapter 32: LPC43xx/LPC43Sxx Timer0/1/2/3
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32.1 How to read this chapter
The timers are available on all LPC43xx/LPC43Sxx parts.

32.2 Basic configuration
The Timers are configured as follows:

• See Table 779 for clocking and power control.
• The Timer0/1/2/3 are reset by the TIMER0/1/2/3_RST (reset #32/33/34/35).
• The Timer0/1/2/3 interrupts are connected to slot # 12/13/14/15 in the NVIC. Match
channels 2 of Timer0/1/3 are connected to slots # 13, 14, 16 in the Event router.
(These outputs are ORed with SCT outputs 2, 6, 14.)

• For connecting the match channels 0 and 1 of Timer0/1/2/3 to the GPDMA, use the
DMAMUX register in the CREG block (see Table 100) and enable the GPDMA
channel in the DMA Channel Configuration registers (Section 21.6.20).

• The timer registers can be also accessed by the GPDMA as memory-to-memory
transfer.

• To connect a timer capture input to a pin, first select either the CTIN_m or Tn_CAPm
input in the SCU (Section 17.3.11), and then configure the capture input multiplexer
for the selected pin through the GIMA (see Section 18.3).

• The timer match outputs are connected to dedicated Tn_MATm pins and to the
CTOUT_m pins, where they may be ORed with the SCT outputs. See Table 104 and
Table 714.
Table 779. Timer0/1/2/3 clocking and power control
Base clock

Branch clock

Operating
frequency

Clock to the timer0 register interface and
timer0 peripheral clock PCLK.

BASE_M4_CLK

CLK_M4_TIMER0 up to
204 MHz

Clock to the timer1 register interface and
timer1 peripheral clock PCLK.

BASE_M4_CLK

CLK_M4_TIMER1 up to
204 MHz

Clock to the timer2 register interface and
timer2 peripheral clock PCLK.

BASE_M4_CLK

CLK_M4_TIMER2 up to
204 MHz

Clock to the timer3 register interface and
timer3 peripheral clock PCLK.

BASE_M4_CLK

CLK_M4_TIMER3 up to
204 MHz

32.3 Features
• A 32 bit Timer/Counter with a programmable 32 bit Prescaler.
• Counter or Timer operation
• Up to four 32-bit capture channels per timer, that can take a snapshot of the timer
value when an input signal transitions. A capture event may also optionally generate
an interrupt.
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• Four 32-bit match registers that allow:
– Continuous operation with optional interrupt generation on match.
– Stop timer on match with optional interrupt generation.
– Reset timer on match with optional interrupt generation.

• Up to four external outputs corresponding to match registers, with the following
capabilities:
– Set low on match.
– Set high on match.
– Toggle on match.
– Do nothing on match.

32.4 General description
The Timer/Counter is designed to count cycles of the peripheral clock (PCLK) or an
externally-supplied clock, and can optionally generate interrupts or perform other actions
at specified timer values, based on four match registers. It also includes four capture
inputs to trap the timer value when an input signal transitions, optionally generating an
interrupt.
Table 780 gives a brief summary of each of the Timer/Counter related functions.
Table 780. Timer/Counter function description
Pin

Type

Description

CAP0_[3:0]
CAP1_[3:0]
CAP2_[3:0]
CAP3_[3:0]

Input

Capture Signals- A transition on a capture input can be configured to
load one of the Capture Registers with the value in the Timer Counter
and optionally generate an interrupt. Capture functionality can be
selected from a number of pins.
Timer/Counter block can select a capture signal as a clock source
instead of the PCLK derived clock. For more details see Section 32.6.11.

MAT0_[3:0]
MAT1_[3:0]
MAT2_[3:0]
MAT3_[3:0]

Output

External Match Output - When a match register (MR3:0) equals the timer
counter (TC) this output can either toggle, go LOW, go HIGH, or do
nothing. The External Match Register (EMR) controls the functionality of
this output. Match Output functionality can be selected on a number of
pins in parallel.

32.4.1 Architecture
The block diagram for TIMER/COUNTER0 and TIMER/COUNTER1 is shown in
Figure 108.

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Chapter 32: LPC43xx/LPC43Sxx Timer0/1/2/3

MATCH REGISTER 0
MATCH REGISTER 1
MATCH REGISTER 2
MATCH REGISTER 3
MATCH CONTROL REGISTER
EXTERNAL MATCH REGISTER
INTERRUPT REGISTER

CONTROL
=

MAT[3:0]
INTERRUPT

=

CAP[3:0]
=

STOP ON MATCH
RESET ON MATCH
LOAD[3:0]

=

CAPTURE CONTROL REGISTER

CSN

CAPTURE REGISTER 0

TIMER COUNTER

CAPTURE REGISTER 1

CE

CAPTURE REGISTER 2
CAPTURE REGISTER 3

TCI
PCLK
PRESCALE COUNTER
reset

enable

TIMER CONTROL REGISTER

MAXVAL
PRESCALE REGISTER

Fig 108. Timer block diagram

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32.5 Pin description
Input signals to each timer capture channel can originate from the external pins or from
several other internal sources. The GIMA (see Table 207) and (for capture channel 3 of
each timer) the CTOUTCTRL bit of CREG6 determine which signal is captured by the
timer.
The match outputs are connected to the Tn_MATm pin functions. In addition, the match
outputs ORed with the SCT outputs can be monitored on the CTOUT pins provided that
the CTOUTCTRL bit is set to 0 (default) in the CREG6 register (see Table 104).
Table 781. Timer0 inputs and outputs
Input/output From/to
multiplexed pin
function

From/to internal signal

Default (see
GIMA,
Table 207)

CTOUTCTRL
bit (see
Table 104)

CTIN_0

-

yes

-

-

SGPIO3

no

-

T0_CAP0

-

no

-

CTIN_1

-

yes

-

-

USART2 TX active

no

-

Timer0 inputs

CAP0

CAP1

CAP2

CAP3

T0_CAP1

-

no

-

CTIN_2

-

yes

-

-

SGPIO3_DIV

no

-

T0_CAP2

-

no

-

-

SCT output 15 OR T3 match
channel 3

yes

0

-

SCT output 15

yes

1

T0_CAP3

-

no

-

-

T3 match channel 3

no

-

-

-

-

CTOUT_0; if
match ORed with
SCT output

-

0

-

no

-

no

-

Timer0 outputs

MAT0

T0_MAT0

ADC start0 input (ADC
CR register START bits
= 0x2)

MAT1

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-

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Table 781. Timer0 inputs and outputs …continued
Input/output From/to
multiplexed pin
function

From/to internal signal

Default (see
GIMA,
Table 207)

CTOUTCTRL
bit (see
Table 104)

MAT2

MAT3

-

-

-

CTOUT_2 if
match ORed with
SCT output

T0_MAT2

-

0

-

Event router input 13

no

-

T0_MAT3

-

-

-

CTOUT_3 if
match ORed with
SCT output

-

0

From/to internal signal

Default (see
GIMA,
Table 207)

CTOUTCTRL
bit (see
Table 104)

CTIN_0

-

yes

-

-

SGPIO12

no

-

T1_CAP0

-

no

-

CTIN_3

-

yes

-

T1_CAP1

-

no

-

-

USART0 TX active

no

-

CTIN_4

-

yes

-

T1_CAP2

-

no

-

Table 782. Timer1 inputs and outputs
Input/output From/to
multiplexed pin
function
Timer1 inputs

CAP0

CAP1

CAP2
CAP3

-

USART0 RX active

no

-

-

SCT output 3 OR T0 match
channel 3

yes

0

-

SCT output 3

yes

1

-

T0 match channel 3

no

-

T1_CAP3

-

no

-

Timer1 outputs

MAT0

T1_MAT0

-

-

-

MAT1

T1_MAT1

-

-

-

MAT2

T1_MAT2

-

-

-

CTOUT_6 if
match ORed with
SCT output
MAT3

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0

-

Event router input 14

no

-

T1_MAT3

-

-

-

CTOUT_7 if
match ORed with
SCT output

-

0

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Table 783. Timer2 inputs and outputs
Input/output From/to
multiplexed pin
function

From/to internal signal

Default (see
GIMA,
Table 207)

CTOUTCTRL
bit (see
Table 104)

CTIN_0

-

yes

-

-

SGPIO12_DIV

no

-

T2_CAP0

-

no

-

CTIN_1

-

yes

-

T2_CAP1

-

no

-

Timer2 inputs

CAP0

CAP1

CAP2
CAP3

-

USART2 TX active

no

-

-

I2S1_RX_MWS

no

-

CTIN_5

-

yes

-

T2_CAP2

-

no

-

-

USART2 RX active

no

-

-

I2S1_TX_MWS

no

-

-

SCT output 7 OR T1 match
channel 3

yes

0

-

SCT output 7

yes

1

-

T1 match channel 3

no

-

T2_CAP3

-

no

-

Timer2 outputs

MAT0

-

-

-

CTOUT_8 if
match ORed with
SCT output

T2_MAT0

-

0

-

no

-

ADC start1 input (ADC
CR register bit START =
0x3)

MAT1

T2_MAT1

-

-

-

MAT2

T2_MAT2

-

-

-

MAT3

T3_MAT3

-

-

-

CTOUT_11 if
match ORed with
SCT output

-

0

Default (see
GIMA,
Table 207)

CTOUTCTRL
bit (see
Table 104)

Table 784. Timer3 inputs and outputs
Input/output From/to
multiplexed pin
function

From/to internal signal

Timer3 inputs

CAP0

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yes

-

-

CTIN_0
I2S0_RX_MWS

no

-

T3_CAP0

-

no

-

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Table 784. Timer3 inputs and outputs …continued
Input/output From/to
multiplexed pin
function

From/to internal signal

Default (see
GIMA,
Table 207)

CTOUTCTRL
bit (see
Table 104)

CAP1

CTIN_6

-

yes

-

T3_CAP1

-

no

-

-

USART3 TX active

no

-

-

I2S0_TX_MWS

no

-

CTIN_7

-

yes

-

T3_CAP2

-

no

-

-

USART3 RX active

no

-

-

SOF0

no

-

CAP2

CAP3

T3_CAP3

no

-

-

SCT output 11 OR T2 match
channel 3

yes

0

-

SCT output 11

yes

1

-

T2 match channel 3

no

-

-

SOF1

no

-

Timer3 outputs

MAT0

T3_MAT0

-

-

-

MAT1

T3_MAT1

-

-

-

MAT2

T3_MAT2

-

-

-

CTOUT_14 if
match ORed with
SCT output

-

0

-

Event router input 16

no

-

T3_MAT3

-

-

-

CTOUT_1,
CTOUT_4,
CTOUT_5,
CTOUT_9,
CTOUT_10,
CTOUT_12,
CTOUT_13,
CTOUT_15 if
match ORed with
SCT output

-

0

MAT3

32.6 Register description
Each Timer/Counter contains the registers shown in Table 785.

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Table 785. Register overview: Timer0/1/2/3 (register base addresses 0x4008 4000 (TIMER0), 0x4008 5000 (TIMER1),
0x400C 3000 (TIMER2), 0x400C 4000 (TIMER3))
Name

Access Address
offset

Description

IR

R/W

0x000

Interrupt Register. The IR can be written to clear interrupts. 0
The IR can be read to identify which of eight possible
interrupt sources are pending.

Table 786

TCR

R/W

0x004

Timer Control Register. The TCR is used to control the
Timer Counter functions. The Timer Counter can be
disabled or reset through the TCR.

0

Table 787

TC

R/W

0x008

Timer Counter. The 32 bit TC is incremented every PR+1
cycles of PCLK. The TC is controlled through the TCR.

0

Table 788

PR

R/W

0x00C

Prescale Register. When the Prescale Counter (PC) is
equal to this value, the next clock increments the TC and
clears the PC.

0

Table 789

PC

R/W

0x010

Prescale Counter. The 32 bit PC is a counter which is
0
incremented to the value stored in PR. When the value in
PR is reached, the TC is incremented and the PC is
cleared. The PC is observable and controllable through the
bus interface.

Table 790

MCR

R/W

0x014

Match Control Register. The MCR is used to control if an
interrupt is generated and if the TC is reset when a Match
occurs.

0

Table 791

MR0

R/W

0x018

Match Register 0. MR0 can be enabled through the MCR 0
to reset the TC, stop both the TC and PC, and/or generate
an interrupt every time MR0 matches the TC.

Table 792

MR1

R/W

0x01C

Match Register 1. See MR0 description.

0

Table 792

MR2

R/W

0x020

Match Register 2. See MR0 description.

0

Table 792

MR3

R/W

0x024

Match Register 3. See MR0 description.

0

Table 792

CCR

R/W

0x028

Capture Control Register. The CCR controls which edges
of the capture inputs are used to load the Capture
Registers and whether or not an interrupt is generated
when a capture takes place.

0

Table 793

CR0

RO

0x02C

Capture Register 0. CR0 is loaded with the value of TC
when there is an event on the CAPn.0 input.

0

Table 794

CR1

RO

0x030

Capture Register 1. See CR0 description.

0

Table 794

CR2

RO

0x034

Capture Register 2. See CR0 description.

0

Table 794

CR3

RO

0x038

Capture Register 3. See CR0 description.

0

Table 794

EMR

R/W

0x03C

External Match Register. The EMR controls the external
match pins MATn.0-3 (MAT0.0-3 and MAT1.0-3
respectively).

0

Table 795

CTCR

R/W

0x070

Count Control Register. The CTCR selects between Timer 0
and Counter mode, and in Counter mode selects the signal
and edge(s) for counting.

Table 797

[1]

Reset
Reference
value[1]

Reset value reflects the data stored in used bits only. It does not include reserved bits content.

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32.6.1 Timer interrupt registers
The Interrupt Register consists of four bits for the match interrupts and four bits for the
capture interrupts. If an interrupt is generated then the corresponding bit in the IR will be
high. Otherwise, the bit will be low. Writing a logic one to the corresponding IR bit will reset
the interrupt. Writing a zero has no effect. The act of clearing an interrupt for a timer match
also clears any corresponding DMA request.
Table 786. Timer interrupt registers (IR, addresses 0x4008 4000 (TIMER0), 0x4008 5000
(TIMER1), 0x400C 3000 (TIMER2), 0x400C 4000 (TIMER3)) bit description
Bit

Symbol

Description

Reset
value

0

MR0INT

Interrupt flag for match channel 0.

0

1

MR1INT

Interrupt flag for match channel 1.

0

2

MR2INT

Interrupt flag for match channel 2.

0

3

MR3INT

Interrupt flag for match channel 3.

0

4

CR0INT

Interrupt flag for capture channel 0 event.

0

5

CR1INT

Interrupt flag for capture channel 1 event.

0

6

CR2INT

Interrupt flag for capture channel 2 event.

0

7

CR3INT

Interrupt flag for capture channel 3 event.

0

31:8

-

Reserved.

-

32.6.2 Timer control registers
The Timer Control Register (TCR) is used to control the operation of the Timer/Counter.
Table 787. Timer control register (TCR, addresses 0x4008 4004 (TIMER0), 0x4008 5004
(TIMER1), 0x400C 3004 (TIMER2), 0x400C 4004 (TIMER3)) bit description
Bit

Symbol

Description

Reset value

0

CEN

When one, the Timer Counter and Prescale Counter are 0
enabled for counting. When zero, the counters are
disabled.

1

CRST

When one, the Timer Counter and the Prescale Counter 0
are synchronously reset on the next positive edge of
PCLK. The counters remain reset until TCR[1] is
returned to zero.

31:2

-

Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit is not
defined.

NA

32.6.3 Timer counter registers
The 32-bit Timer Counter register is incremented when the prescale counter reaches its
terminal count. Unless it is reset before reaching its upper limit, the Timer Counter will
count up through the value 0xFFFF FFFF and then wrap back to the value 0x0000 0000.
This event does not cause an interrupt, but a match register can be used to detect an
overflow if needed.

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Table 788. Timer counter registers (TC, addresses 0x4008 4008 (TIMER0), 0x4008 5008
(TIMER1), 0x400C 3008 (TIMER2), 0x400C 4008 (TIMER3)) bit description
Bit

Symbol

Description

Reset
value

31:0

TC

Timer counter value.

0

32.6.4 Timer prescale registers
The 32-bit Timer prescale register specifies the maximum value for the Prescale Counter.
Table 789. Timer prescale registers (PR, addresses 0x4008 400C (TIMER0), 0x4008 500C
(TIMER1), 0x400C 300C (TIMER2), 0x400C 400C (TIMER3)) bit description
Bit

Symbol

Description

Reset
value

31:0

PM

Prescale counter maximum value.

0

32.6.5 Timer prescale counter registers
The 32-bit Prescale Counter controls division of PCLK by some constant value before it is
applied to the Timer Counter. This allows control of the relationship of the resolution of the
timer versus the maximum time before the timer overflows. The Prescale Counter is
incremented on every PCLK. When it reaches the value stored in the Prescale register,
the Timer Counter is incremented and the Prescale Counter is reset on the next PCLK.
This causes the Timer Counter to increment on every PCLK when PR = 0, every 2 PCLKs
when PR = 1, etc.
Table 790. Timer prescale counter registers (PC, addresses 0x4008 4010 (TIMER0),
0x4008 5010 (TIMER1), 0x400C 3010 (TIMER2), 0x400C 4010 (TIMER3)) bit
description
Bit

Symbol

Description

Reset
value

31:0

PC

Prescale counter value.

0

32.6.6 Timer match control registers
The Match Control Register is used to control what operations are performed when one of
the Match Registers matches the Timer Counter. The function of each of the bits is shown
in Table 791.
Table 791. Timer match control registers (MCR, addresses 0x4008 4014 (TIMER0),
0x4008 5014 (TIMER1), 0x400C 3014 (TIMER2), 0x400C 4014 (TIMER3)) bit
description
Bit

Symbol Value Description

Reset
value

0

MR0I

0

1

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Interrupt on MR0
0

Disabled. Interrupt is disabled

1

Enabled. Interrupt is generated when MR0 matches the value in
the TC.

MR0R

Reset on MR0
0

Disabled. Feature disabled.

1

Reset. TC will be reset if MR0 matches it.

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Table 791. Timer match control registers (MCR, addresses 0x4008 4014 (TIMER0),
0x4008 5014 (TIMER1), 0x400C 3014 (TIMER2), 0x400C 4014 (TIMER3)) bit
description …continued
Bit

Symbol Value Description

Reset
value

2

MR0S

0

3

4

5

6

7

8

9

10

11

User manual

Stop on MR0

0

Disabled. Feature disabled.

1

Match. TC and PC will be stopped and TCR[0] will be set to 0 if
MR0 matches the TC.

MR1I

Interrupt on MR1

0

0

Disabled. Interrupt is disabled.

1

Match. Interrupt is generated when MR1 matches the value in
the TC.

MR1R

Reset on MR1
0

Disabled. Feature disabled.

1

Reset. TC will be reset if MR1 matches it.

MR1S

0

Stop on MR1

0

0

Disabled. Feature disabled.

1

Stop. TC and PC will be stopped and TCR[0] will be set to 0 if
MR1 matches the TC.

MR2I

Interrupt on MR2

0

0

Disabled. Interrupt is disabled

1

Match. Interrupt is generated when MR2 matches the value in
the TC.

MR2R

Reset on MR2
0

Disabled. Feature disabled.

1

Match. TC will be reset if MR2 matches it.

MR2S

0

Stop on MR2.

0

0

Disabled. Feature disabled.

1

Stop. TC and PC will be stopped and TCR[0] will be set to 0 if
MR2 matches the TC.

MR3I

Interrupt on MR3

0

0

Disabled. This interrupt is disabled.

1

Interrupt. Interrupt is generated when MR3 matches the value in
the TC.

MR3R

Reset on MR3
0

Disabled. Feature disabled.

1

Match. TC will be reset if MR3 matches it.

MR3S

31:12 -

UM10503

1

0

Stop on MR3

0

0

Disabled. Feature disabled.

1

Stop. TC and PC will be stopped and TCR[0] will be set to 0 if
MR3 matches the TC.
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.

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Chapter 32: LPC43xx/LPC43Sxx Timer0/1/2/3

32.6.7 Timer match registers (MR0 - MR3)
The Match register values are continuously compared to the Timer Counter value. When
the two values are equal, actions can be triggered automatically. The action possibilities
are to generate an interrupt, reset the Timer Counter, or stop the timer. Actions are
controlled by the settings in the MCR register.
Table 792. Timer match registers (MR[0:3], addresses 0x4008 4018 (MR0) to 0x4008 4024
(M3) (TIMER0), 0x4008 5018 (MR0) to 0x4008 5024 (MR3)(TIMER1), 0x400C 3018
(MR0) to 0x400C 8024 (MR3) (TIMER2), 0x400C 4018 (MR0) to 0x400C 4024
(MR3)(TIMER3)) bit description
Bit

Symbol

Description

Reset
value

31:0

MATCH

Timer counter match value.

0

32.6.8 Timer capture control registers
The Capture Control Register is used to control whether one of the four Capture Registers
is loaded with the value in the Timer Counter when the capture event occurs, and whether
an interrupt is generated by the capture event. Setting both the rising and falling bits at the
same time is a valid configuration, resulting in a capture event for both edges. In the
description below, n represents the Timer number.
Remark: If Counter mode is selected for a particular CAP input in the CTCR, the 3 bits for
that input in this register should be programmed as 000, but capture and/or interrupt can
be selected for the other 3 CAP inputs.
Table 793. Timer capture control registers (CCR, addresses 0x4008 4028 (TIMER0),
0x4008 5020 (TIMER1), 0x400C 3028 (TIMER2), 0x400C 4028 (TIMER3)) bit
description
Bit

Symbol

0

CAP0RE

1

2

3

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Value

Description

Reset
value

Capture on CAPn.0 rising edge

0

0

Disabled. This feature is disabled.

1

Low to high. A sequence of 0 then 1 on CAPn.0 will cause CR0
to be loaded with the contents of TC.

0

Disabled. This feature is disabled.

1

High to low. A sequence of 1 then 0 on CAPn.0 will cause CR0
to be loaded with the contents of TC.

CAP0FE

Capture on CAPn.0 falling edge

CAP0I

0

Interrupt on CAPn.0 event

0

0

Disabled. This feature is disabled.

1

Load. A CR0 load due to a CAPn.0 event will generate an
interrupt.

0

Disabled. This feature is disabled.

1

Low to high. A sequence of 0 then 1 on CAPn.1 will cause CR1
to be loaded with the contents of TC.

CAP1RE

Capture on CAPn.1 rising edge

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Chapter 32: LPC43xx/LPC43Sxx Timer0/1/2/3

Table 793. Timer capture control registers (CCR, addresses 0x4008 4028 (TIMER0),
0x4008 5020 (TIMER1), 0x400C 3028 (TIMER2), 0x400C 4028 (TIMER3)) bit
description …continued
Bit

Symbol

4

CAP1FE

5

6

7

8

9

10

11

Value

Reset
value

Capture on CAPn.1 falling edge

0

0

Disabled. This feature is disabled.

1

High to low. A sequence of 1 then 0 on CAPn.1 will cause CR1
to be loaded with the contents of TC.

CAP1I

Interrupt on CAPn.1 event

0

0

Disabled. This feature is disabled.

1

Load. A CR1 load due to a CAPn.1 event will generate an
interrupt.

CAP2RE

Capture on CAPn.2 rising edge

0

0

Disabled. This feature is disabled.

1

Low to high. A sequence of 0 then 1 on CAPn.2 will cause CR2
to be loaded with the contents of TC.

CAP2FE

Capture on CAPn.2 falling edge:

0

0

Disabled. This feature is disabled.

1

High to low. A sequence of 1 then 0 on CAPn.2 will cause CR2
to be loaded with the contents of TC.

CAP2I

Interrupt on CAPn.2 event

0

0

Disabled. This feature is disabled.

1

Load. A CR2 load due to a CAPn.2 event will generate an
interrupt.

CAP3RE

Capture on CAPn.3 rising edge

0

0

Disabled. This feature is disabled.

1

Low to high. A sequence of 0 then 1 on CAPn.3 will cause CR3
to be loaded with the contents of TC.

CAP3FE

High to low. Capture on CAPn.3 falling edge

0

0

Disabled. This feature is disabled.

1

A sequence of 1 then 0 on CAPn.3 will cause CR3 to be loaded
with the contents of TC.

CAP3I

31:12 -

Description

Interrupt on CAPn.3 event:

0

0

Disabled. This feature is disabled.

1

Load. A CR3 load due to a CAPn.3 event will generate an
interrupt.
Reserved, user software should not write ones to reserved bits. NA
The value read from a reserved bit is not defined.

32.6.9 Timer capture registers
Each Capture register is associated with a device pin and may be loaded with the Timer
Counter value when a specified event occurs on that pin. The settings in the Capture
Control Register register determine whether the capture function is enabled, and whether
a capture event happens on the rising edge of the associated pin, the falling edge, or on
both edges.
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Chapter 32: LPC43xx/LPC43Sxx Timer0/1/2/3

Table 794. Timer capture registers (CR[0:3], address 0x4008 402C (CR0) to 0x4008 4038
(CR3) (TIMER0), 0x4008 502C (CR0) to 0x4008 5038 (CR3) (TIMER1), 0x400C 302C
(CR0) to 0x400C 3038 (CR3) (TIMER2), 0x400C 402C (CR0) to 0x400C 4038 (CR3)
(TIMER3)) bit description
Bit

Symbol

Description

Reset
value

31:0

CAP

Timer counter capture value.

0

32.6.10 Timer external match registers
The External Match Register provides both control and status of the external match pins.
In the descriptions below, “n” represents the Timer number, 0 or 1, and “m” represent a
Match number, 0 through 3.
Match events for Match 0 and Match 1 in each timer can cause a DMA request, see
Section 32.7.2.
Table 795. Timer external match registers (EMR, addresses 0x4008 403C (TIMER0),
0x4008 503C (TIMER1), 0x400C 303C (TIMER2), 0x400C 403C (TIMER3)) bit
description

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Bit

Symbol Value

Description

Reset
value

0

EM0

External Match 0. When a match occurs between the TC and
MR0, this bit can either toggle, go low, go high, or do nothing,
depending on bits 5:4 of this register. This bit can be driven
onto a MATn.0 pin, in a positive-logic manner (0 = low,
1 = high).

0

1

EM1

External Match 1. When a match occurs between the TC and
MR1, this bit can either toggle, go low, go high, or do nothing,
depending on bits 7:6 of this register. This bit can be driven
onto a MATn.1 pin, in a positive-logic manner (0 = low,
1 = high).

0

2

EM2

External Match 2. When a match occurs between the TC and
MR2, this bit can either toggle, go low, go high, or do nothing,
depending on bits 9:8 of this register. This bit can be driven
onto a MATn.0 pin, in a positive-logic manner (0 = low,
1 = high).

0

3

EM3

External Match 3. When a match occurs between the TC and
MR3, this bit can either toggle, go low, go high, or do nothing,
depending on bits 11:10 of this register. This bit can be driven
onto a MATn.0 pin, in a positive-logic manner (0 = low,
1 = high).

0

5:4

EMC0

External Match Control 0. Determines the functionality of
External Match 0.

00

0x0

Do Nothing.

0x1

Clear. Clear the corresponding External Match bit/output to 0
(MATn.m pin is LOW if pinned out).

0x2

Set. Set the corresponding External Match bit/output to 1
(MATn.m pin is HIGH if pinned out).

0x3

Toggle. Toggle the corresponding External Match bit/output.

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Chapter 32: LPC43xx/LPC43Sxx Timer0/1/2/3

Table 795. Timer external match registers (EMR, addresses 0x4008 403C (TIMER0),
0x4008 503C (TIMER1), 0x400C 303C (TIMER2), 0x400C 403C (TIMER3)) bit
description
Bit

Symbol Value

Description

Reset
value

7:6

EMC1

External Match Control 1. Determines the functionality of
External Match 1.

00

9:8

0x0

Do Nothing.

0x1

Clear. Clear the corresponding External Match bit/output to 0
(MATn.m pin is LOW if pinned out).

0x2

Set. Set the corresponding External Match bit/output to 1
(MATn.m pin is HIGH if pinned out).

0x3

Toggle. Toggle the corresponding External Match bit/output.

EMC2

External Match Control 2. Determines the functionality of
External Match 2.

00

0x0

Do Nothing.

0x1

Clear. Clear the corresponding External Match bit/output to 0
(MATn.m pin is LOW if pinned out).

0x2

Set. Set the corresponding External Match bit/output to 1
(MATn.m pin is HIGH if pinned out).

0x3

Toggle. Toggle the corresponding External Match bit/output.

11:10 EMC3

External Match Control 3. Determines the functionality of
External Match 3.

00

0x0

Do Nothing.

0x1

Clear. Clear the corresponding External Match bit/output to 0
(MATn.m pin is LOW if pinned out).

0x2

Set. Set the corresponding External Match bit/output to 1
(MATn.m pin is HIGH if pinned out).

0x3

Toggle. Toggle the corresponding External Match bit/output.

31:12 -

Reserved, user software should not write ones to reserved bits. NA
The value read from a reserved bit is not defined.

Table 796. External Match Control
EMR[11:10], EMR[9:8],
EMR[7:6], or EMR[5:4]

Function

00

Do Nothing.

01

Clear the corresponding External Match bit/output to 0 (MATn.m pin is
LOW if pinned out).

10

Set the corresponding External Match bit/output to 1 (MATn.m pin is
HIGH if pinned out).

11

Toggle the corresponding External Match bit/output.

32.6.11 Timer count control registers
The Count Control Register (CTCR) is used to select between Timer and Counter mode,
and in Counter mode to select the pin and edge(s) for counting.

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Chapter 32: LPC43xx/LPC43Sxx Timer0/1/2/3

When Counter Mode is chosen as a mode of operation, the CAP input (selected by the
CTCR bits 3:2) is sampled on every rising edge of the PCLK clock. After comparing two
consecutive samples of this CAP input, one of the following four events is recognized:
rising edge, falling edge, either of edges or no changes in the level of the selected CAP
input. Only if the identified event corresponds to the one selected by bits 1:0 in the CTCR
register, the Timer Counter register will be incremented.
Effective processing of the externally supplied clock to the counter has some limitations.
Since two successive rising edges of the PCLK clock are used to identify only one edge
on the CAP selected input, the frequency of the CAP input can not exceed one quarter of
the PCLK clock. Consequently, duration of the high/low levels on the same CAP input in
this case can not be shorter than 1/(2 PCLK).
Table 797. Timer count control register (CTCR, addresses 0x4008 4070 (TIMER0),
0x4008 5070 (TIMER1), 0x400C 3070 (TIMER2), 0x400C 4070 (TIMER3)) bit
description
Bit

Symbol

Value

1:0

CTMODE

Description

Reset
value

Counter/Timer Mode
This field selects which rising PCLK edges can increment
Timer’s Prescale Counter (PC), or clear PC and increment
Timer Counter (TC).

00

Timer Mode: the TC is incremented when the Prescale
Counter matches the Prescale Register.

3:2

0x0

Timer Mode. Counts every rising PCLK edge

0x1

Counter Mode rising edge. TC is incremented on rising
edges on the CAP input selected by bits 3:2.

0x2

Counter Mode falling edge. TC is incremented on falling
edges on the CAP input selected by bits 3:2.

0x3

Counter Mode edges. TC is incremented on both edges on
the CAP input selected by bits 3:2.

CINSEL

00

Count Input Select
When bits 1:0 in this register are not 00, these bits select
which CAP pin is sampled for clocking.
Note: If Counter mode is selected for a particular CAPn
input in the TnCTCR, the 3 bits for that input in the Capture
Control Register (TnCCR) must be programmed as 000.
However, capture and/or interrupt can be selected for the
other 3 CAPn inputs in the same timer.

31:4

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-

0x0

CAP0. CAPn.0 for TIMERn

0x1

CAP1. CAPn.1 for TIMERn

0x2

CAP2. CAPn.2 for TIMERn

0x3

CAP3. CAPn.3 for TIMERn

-

Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.

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Chapter 32: LPC43xx/LPC43Sxx Timer0/1/2/3

32.7 Functional description
32.7.1 Example timer operation
Figure 109 shows a timer configured to reset the count and generate an interrupt on
match. The prescaler is set to 2 and the match register set to 6. At the end of the timer
cycle where the match occurs, the timer count is reset. This gives a full length cycle to the
match value. The interrupt indicating that a match occurred is generated in the next clock
after the timer reached the match value.
Figure 110 shows a timer configured to stop and generate an interrupt on match. The
prescaler is again set to 2 and the match register set to 6. In the next clock after the timer
reaches the match value, the timer enable bit in TCR is cleared, and the interrupt
indicating that a match occurred is generated.

PCLK
prescale
counter

2

timer
counter

4

0

1

2

0

1

5

2

0

6

1
0

2

0

1
1

timer counter
reset
interrupt

Fig 109. A timer cycle in which PR=2, MRx=6, and both interrupt and reset on match are enabled.

PCLK
prescale counter
timer counter
TCR[0]
(counter enable)

2
4

0

1
5
1

2

0
6
0

interrupt

Fig 110. A timer Cycle in Which PR=2, MRx=6, and both interrupt and stop on match are enabled

32.7.2 DMA operation
DMA requests are generated by 0 to 1 transitions of the External Match 0 and 1 bits of
each timer. In order to have an effect, the GPDMA must be configured and the relevant
timer DMA request selected as a DMA source via the CREG block, see Table 100.
When a timer is initially set up to generate a DMA request, the request may already be
asserted before a match condition occurs. An initial DMA request may be avoided by
having software by write a one to the interrupt flag location, as if clearing a timer interrupt.
See Section 32.6.1. A DMA request will be cleared automatically when it is acted upon by
the GPDMA controller.

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Chapter 33: LPC43xx/LPC43Sxx Motor Control PWM
(MOTOCONPWM)
Rev. 2.4 — 22 August 2018

User manual

33.1 How to read this chapter
The Motor control PWM is available on all LPC43xx/LPC43Sxx parts.

33.2 Basic configuration
The PWM is configured as follows:

• See Table 798 for clocking and power control.
• The PWM is reset by the MOTOCONPWM_RST (reset #38).
• The PWM interrupt is connected to slot #16 in the NVIC.
Table 798. PWM clocking and power control
Base clock

Clock to the PWM Motor control block and BASE_APB1_
PWM Motocon peripheral clock.
CLK

Branch clock

Operating
frequency

CLK_APB1_
MOTOCON

up to
204 MHz

33.3 Introduction
The Motor Control PWM (MCPWM) is optimized for three-phase AC and DC motor control
applications, but can be used in many other applications that need timing, counting,
capture, and comparison.

33.4 Features
The MCPWM contains three independent channels, each including:

•
•
•
•
•
•
•

a 32-bit Timer/Counter (TC)
a 32-bit Limit register (LIM)
a 32-bit Match register (MAT)
a 10-bit dead-time register (DT) and an associated 10-bit dead-time counter
a 32-bit capture register (CAP)
two modulated outputs (MCOA and MCOB) with opposite polarities
a period interrupt, a pulse-width interrupt, and a capture interrupt

Input pins MCI0-2 can trigger TC capture or increment a channel’s TC. A global Abort
input can force all of the channels into “A passive” state and cause an interrupt.

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Chapter 33: LPC43xx/LPC43Sxx Motor Control PWM (MOTOCONPWM)

33.5 General description
Section 33.8 includes detailed descriptions of the various modes of MCPWM operation,
but a quick preview here will provide background for the register descriptions below.
The MCPWM includes 3 channels, each of which controls a pair of outputs that in turn can
control something off-chip, like one set of coils in a motor. Each channel includes a
Timer/Counter (TC) register that is incremented by a processor clock (timer mode) or by
an input pin (counter mode).
Each channel has a Limit register that is compared to the TC value, and when a match
occurs the TC is “recycled” in one of two ways. In “edge-aligned mode” the TC is reset to
0, while in “centered mode” a match switches the TC into a state in which it decrements on
each processor clock or input pin transition until it reaches 0, at which time it starts
counting up again.
Each channel also includes a Match register that holds a smaller value than the Limit
register. In edge-aligned mode the channel’s outputs are switched whenever the TC
matches either the Match or Limit register, while in center-aligned mode they are switched
only when it matches the Match register.
So the Limit register controls the period of the outputs, while the Match register controls
how much of each period the outputs spend in each state. Having a small value in the
Limit register minimizes “ripple” if the output is integrated into a voltage, and allows the
MCPWM to control devices that operate at high speed.
The “downside” of small values in the Limit register is that they reduce the resolution of
the duty cycle controlled by the Match register. If you have 8 in the Limit register, the
Match register can only select the duty cycle among 0%, 12.5%, 25%, …, 87.5%, or
100%. In general, the resolution of each step in the Match value is 1 divided by the Limit
value.
This trade-off between resolution and period/frequency is inherent in the design of pulse
width modulators.

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Chapter 33: LPC43xx/LPC43Sxx Motor Control PWM (MOTOCONPWM)

33.5.1 Block Diagram
PCLK
MCI0-2

Clock
selection

Event
selection

TC0

Clock
selection

Event
selection

TC1

Clock
selection

Event
selection

TC2

MCCNTCON
MCCAPCON
cntl

RT0

cntl

RT1

MAT0
(write)

MAT1
(write)

MAT0
(oper)

mux

MAT1
(oper)

=

LIM0
(write)

MAT2
(write)

ACMODE

ACMODE

=

LIM2
(write)

LIM1
(oper)

=

mux

MAT2
(oper)

=

LIM1
(write)

LIM0
(oper)

cntl

RT2

LIM2
(oper)

=

CAP0

=

CAP1

CAP2

interrupt
logic
MCABORT

mux

ACMODE
DT0
dead-time
counter

ACMODE

DT1
channel
output
control
A0

MCCON

B0

MCINTF

DT2

dead-time
counter

channel
output
control
A1

MCCON
MCCP
MCABORT

MCINTEN

mux

MCCON

dead-time
counter

B1

channel
output
control
A2

MCCON

B2

global output control

MCOA0

MCOB0

MCOA1

MCOB1

MCOA2

MCOB2

Fig 111. MCPWM Block Diagram

33.6 Pin description
Table 799 lists the MCPWM pins.
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Chapter 33: LPC43xx/LPC43Sxx Motor Control PWM (MOTOCONPWM)

Table 799. MOTOCON PWM pin description
Pin function

Type

Description

MCOA0/1/2

O

Output A for channels 0, 1, 2

MCOB0/1/2

O

Output B for channels 0, 1, 2

MCABORT

I

Low-active Fast Abort

MCI0/1/2

I

Input for channels 0, 1, 2

33.7 Register description
“Control” registers and “interrupt” registers have separate read, set, and clear addresses.
Reading such a register’s read address (e.g. MCCON) yields the state of the register bits.
Writing ones to the set address (e.g. MCCON_SET) sets register bit(s), and writing ones
to the clear address (e.g. MCCON_CLR) clears register bit(s).
The Capture registers (MCCAP) are read-only, and the write-only MCCAP_CLR address
can be used to clear one or more of them. All the other MCPWM registers (MCTIM,
MCPER, MCPW, MCDEADTIME, and MCCP) are normal read-write registers.
Table 800. Register overview: Motor Control Pulse Width Modulator (MCPWM) (base address 0x400A 0000)
Name

Access

Address Description
offset

Reset value

Reference

CON

RO

0x000

PWM Control read address

0

Table 801

CON_SET

WO

0x004

PWM Control set address

-

Table 802

CON_CLR

WO

0x008

PWM Control clear address

-

Table 803

CAPCON

RO

0x00C

Capture Control read address

0

Table 804

CAPCON_SET

WO

0x010

Capture Control set address

-

Table 805

CAPCON_CLR

WO

0x014

Event Control clear address

-

Table 806

TC0

R/W

0x018

Timer Counter register, channel 0

0

Table 807

TC1

R/W

0x01C

Timer Counter register, channel 1

0

Table 807

TC2

R/W

0x020

Timer Counter register, channel 2

0

Table 807

LIM0

R/W

0x024

Limit register, channel 0

0xFFFF FFFF Table 808

LIM1

R/W

0x028

Limit register, channel 1

0xFFFF FFFF Table 808

LIM2

R/W

0x02C

Limit register, channel 2

0xFFFF FFFF Table 808

MAT0

R/W

0x030

Match register, channel 0

0xFFFF FFFF Table 809

MAT1

R/W

0x034

Match register, channel 1

0xFFFF FFFF Table 809

MAT2

R/W

0x038

Match register, channel 2

0xFFFF FFFF Table 809

DT

R/W

0x03C

Dead time register

0x3FFF FFFF Table 810

MCCP

R/W

0x040

Communication Pattern register

0

Table 811

CAP0

RO

0x044

Capture register, channel 0

0

Table 812

CAP1

RO

0x048

Capture register, channel 1

0

Table 812

CAP2

RO

0x04C

Capture register, channel 2

0

Table 812

INTEN

RO

0x050

Interrupt Enable read address

0

Table 814

INTEN_SET

WO

0x054

Interrupt Enable set address

-

Table 815

INTEN_CLR

WO

0x058

Interrupt Enable clear address

-

Table 816

CNTCON

RO

0x05C

Count Control read address

0

Table 817

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Chapter 33: LPC43xx/LPC43Sxx Motor Control PWM (MOTOCONPWM)

Table 800. Register overview: Motor Control Pulse Width Modulator (MCPWM) (base address 0x400A 0000)
Name

Access

Address Description
offset

Reset value

Reference

CNTCON_SET

WO

0x060

Count Control set address

-

Table 818

CNTCON_CLR

WO

0x064

Count Control clear address

-

Table 819

INTF

RO

0x068

Interrupt flags read address

0

Table 820

INTF_SET

WO

0x06C

Interrupt flags set address

-

Table 821

INTF_CLR

WO

0x070

Interrupt flags clear address

-

Table 822

CAP_CLR

WO

0x074

Capture clear address

-

Table 823

33.7.1 MCPWM Control register
33.7.1.1 MCPWM Control read address
The CON register controls the operation of all channels of the PWM. This address is
read-only, but the underlying register can be modified by writing to addresses CON_SET
and CON_CLR.
Table 801. MCPWM Control read address (CON - 0x400A 0000) bit description
Bit

Symbol

0

RUN0

1

Value Description

Stops/starts timer channel 0.
0

Stop.

1

Run.

CENTER0
1

3

4

POLA0

RUN1

9

User manual

Center-aligned.
Passive state is LOW, active state is HIGH.

1

Passive state is HIGH, active state is LOW.

0

Controls the dead-time feature for channel 0.
0

Dead-time disabled.

1

Dead-time enabled.

0

Enable/disable updates of functional registers for channel 0 (see Section 33.8.2).
0

Functional registers are updated from the write registers at the end of each PWM
cycle.

1

Functional registers remain the same as long as the timer is running.

-

0

Reserved.
Stops/starts timer channel 1.

0

Stop.

1

Run.

CENTER1

UM10503

Edge-aligned.

0

DISUP0

8

0

Selects polarity of the MCOA0 and MCOB0 pins.

DTE0

7:5

0

Edge/center aligned operation for channel 0.
0

2

Reset
value

Edge/center aligned operation for channel 1.
0

Edge-aligned.

1

Center-aligned.

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Chapter 33: LPC43xx/LPC43Sxx Motor Control PWM (MOTOCONPWM)

Table 801. MCPWM Control read address (CON - 0x400A 0000) bit description
Bit

Symbol

10

POLA1

11

Value Description

Selects polarity of the MCOA1 and MCOB1 pins.
0

Passive state is LOW, active state is HIGH.

1

Passive state is HIGH, active state is LOW.

DTE1
1
DISUP1

-

16

RUN2

19

20

0

Stops/starts timer channel 2.

0

30

Edge-aligned.

1

Center-aligned.

User manual

0

Selects polarity of the MCOA2 and MCOB2 pins.
0

Passive state is LOW, active state is HIGH.

1

Passive state is HIGH, active state is LOW.

0

Controls the dead-time feature for channel 1.
0

Dead-time disabled.

1

Dead-time enabled.

0

Enable/disable updates of functional registers for channel 2 (see Section 33.8.2).
0

Functional registers are updated from the write registers at the end of each PWM
cycle.

1

Functional registers remain the same as long as the timer is running.

-

Reserved.

0

Controls the polarity of the MCOB outputs for all 3 channels in 3-phase DC mode
(typically set to 1). In other modes, the value of this bit has no effect.
0

The MCOB outputs have opposite polarity from the MCOA outputs (aside from
dead time).

1

The MCOB outputs have the same basic polarity as the MCOA outputs. (see
Section 33.8.6)

ACMODE

UM10503

Run.

0

DISUP2

INVBDC

Stop.
Edge/center aligned operation for channel 2.

DTE2

29

Functional registers are updated from the write registers at the end of each PWM
cycle.
Functional registers remain the same as long as the timer is running.

POLA2

-

0

Reserved.

CENTER2

28:21

Dead-time enabled.

1

1

18

Dead-time disabled.

0

17

0

Enable/disable updates of functional registers for channel 1 (see Section 33.8.2).
0

15:13

0

Controls the dead-time feature for channel 1.
0

12

Reset
value

3-phase AC mode select (see Section 33.8.7).

0

0

3-phase AC-mode off: Each PWM channel uses its own timer-counter and period
register.

1

3-phase AC-mode on: All PWM channels use the timer-counter and period register
of channel 0.

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Table 801. MCPWM Control read address (CON - 0x400A 0000) bit description
Bit

Symbol

31

DCMODE

Value Description

Reset
value

3-phase DC mode select (see Section 33.8.6).

0

0

3-phase DC mode off: PWM channels are independent (unless bit ACMODE = 1)

1

3-phase DC mode on: The internal MCOA0 output is routed through the CP register
(i.e. a mask) register to all six PWM outputs.

33.7.1.2 MCPWM Control set address
Writing ones to this write-only address sets the corresponding bits in MCCON.
Table 802. MCPWM Control set address (CON_SET - 0x400A 0004) bit description
Bit

Symbol

Description

0

RUN0_SET

Writing a one sets the corresponding bit in the CON register. -

1

CENTER0_SET

Writing a one sets the corresponding bit in the CON register. -

2

POLA0_SET

Writing a one sets the corresponding bit in the CON register. -

3

DTE0_SET

Writing a one sets the corresponding bit in the CON register. -

4

DISUP0_SET

Writing a one sets the corresponding bit in the CON register. -

7:5

-

Writing a one sets the corresponding bit in the CON register. -

8

RUN1_SET

Writing a one sets the corresponding bit in the CON register. -

9

CENTER1_SET

Writing a one sets the corresponding bit in the CON register. -

10

POLA1_SET

Writing a one sets the corresponding bit in the CON register. -

11

DTE1_SET

Writing a one sets the corresponding bit in the CON register. -

12

DISUP1_SET

Writing a one sets the corresponding bit in the CON register. -

15:13 -

Reset
value

Writing a one sets the corresponding bit in the CON register. -

16

RUN2_SET

Writing a one sets the corresponding bit in the CON register. -

17

CENTER2_SET

Writing a one sets the corresponding bit in the CON register. -

18

POLA2_SET

Writing a one sets the corresponding bit in the CON register. -

19

DTE2_SET

Writing a one sets the corresponding bit in the CON register. -

20

DISUP2_SET

Writing a one sets the corresponding bit in the CON register. -

28:21 -

Writing a one sets the corresponding bit in the CON register. -

29

INVBDC_SET

Writing a one sets the corresponding bit in the CON register. -

30

ACMODE_SET

Writing a one sets the corresponding bit in the CON register. -

31

DCMODE_SET

Writing a one sets the corresponding bit in the CON register. -

33.7.1.3 MCPWM Control clear address
Writing ones to this write-only address clears the corresponding bits in CON.
Table 803. MCPWM Control clear address (CON_CLR - 0x400A 0008) bit description

UM10503

User manual

Bit

Symbol

Description

0

RUN0_CLR

Writing a one clears the corresponding bit in the CON register. -

1

CENTER0_CLR

Writing a one clears the corresponding bit in the CON register. -

2

POLA0_CLR

Writing a one clears the corresponding bit in the CON register. -

3

DTE0_CLR

Writing a one clears the corresponding bit in the CON register. -

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Table 803. MCPWM Control clear address (CON_CLR - 0x400A 0008) bit description
Bit

Symbol

Description

4

DISUP0_CLR

Writing a one clears the corresponding bit in the CON register. -

7:5

-

Writing a one clears the corresponding bit in the CON register. -

8

RUN1_CLR

Writing a one clears the corresponding bit in the CON register. -

9

CENTER1_CLR

Writing a one clears the corresponding bit in the CON register. -

10

POLA1_CLR

Writing a one clears the corresponding bit in the CON register. -

11

DTE1_CLR

Writing a one clears the corresponding bit in the CON register. -

12

DISUP1_CLR

Writing a one clears the corresponding bit in the CON register. -

15:1 3

Reset
value

Writing a one clears the corresponding bit in the CON register. -

16

RUN2_CLR

Writing a one clears the corresponding bit in the CON register. -

17

CENTER2_CLR

Writing a one clears the corresponding bit in the CON register. -

18

POLA2_CLR

Writing a one clears the corresponding bit in the CON register. -

19

DTE2_CLR

Writing a one clears the corresponding bit in the CON register. -

20

DISUP2_CLR

Writing a one clears the corresponding bit in the CON register. -

28:2 1

Writing a one clears the corresponding bit in the CON register. -

29

INVBDC_CLR

Writing a one clears the corresponding bit in the CON register. -

30

ACMOD_CLR

Writing a one clears the corresponding bit in the CON register. -

31

DCMODE_CLR

Writing a one clears the corresponding bit in the CON register.

33.7.2 PWM Capture Control register
33.7.2.1 MCPWM Capture Control read address
The MCCAPCON register controls detection of events on the MCI0-2 inputs for all
MCPWM channels. Any of the three MCI inputs can be used to trigger a capture event on
any or all of the three channels. This address is read-only, but the underlying register can
be modified by writing to addresses CAPCON_SET and CAPCON_CLR.
Table 804. MCPWM Capture Control read address (CAPCON - 0x400A 000C) bit description
Bit

Symbol

Description

Reset
value

0

CAP0MCI0_RE

A 1 in this bit enables a channel 0 capture event on a rising edge on MCI0.

0

1

CAP0MCI0_FE

A 1 in this bit enables a channel 0 capture event on a falling edge on MCI0.

0

2

CAP0MCI1_RE

A 1 in this bit enables a channel 0 capture event on a rising edge on MCI1.

0

3

CAP0MCI1_FE

A 1 in this bit enables a channel 0 capture event on a falling edge on MCI1.

0

4

CAP0MCI2_RE

A 1 in this bit enables a channel 0 capture event on a rising edge on MCI2.

0

5

CAP0MCI2_FE

A 1 in this bit enables a channel 0 capture event on a falling edge on MCI2.

0

6

CAP1MCI0_RE

A 1 in this bit enables a channel 1 capture event on a rising edge on MCI0.

0

7

CAP1MCI0_FE

A 1 in this bit enables a channel 1 capture event on a falling edge on MCI0.

0

8

CAP1MCI1_RE

A 1 in this bit enables a channel 1 capture event on a rising edge on MCI1.

0

9

CAP1MCI1_FE

A 1 in this bit enables a channel 1 capture event on a falling edge on MCI1.

0

10

CAP1MCI2_RE

A 1 in this bit enables a channel 1 capture event on a rising edge on MCI2.

0

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Table 804. MCPWM Capture Control read address (CAPCON - 0x400A 000C) bit description
Bit

Symbol

Description

Reset
value

11

CAP1MCI2_FE

A 1 in this bit enables a channel 1 capture event on a falling edge on MCI2.

0

12

CAP2MCI0_RE

A 1 in this bit enables a channel 2 capture event on a rising edge on MCI0.

0

13

CAP2MCI0_FE

A 1 in this bit enables a channel 2 capture event on a falling edge on MCI0.

0

14

CAP2MCI1_RE

A 1 in this bit enables a channel 2 capture event on a rising edge on MCI1.

0

15

CAP2MCI1_FE

A 1 in this bit enables a channel 2 capture event on a falling edge on MCI1.

0

16

CAP2MCI2_RE

A 1 in this bit enables a channel 2 capture event on a rising edge on MCI2.

0

17

CAP2MCI2_FE

A 1 in this bit enables a channel 2 capture event on a falling edge on MCI2.

0

18

RT0

If this bit is 1, TC0 is reset by a channel 0 capture event.

0

19

RT1

If this bit is 1, TC1 is reset by a channel 1 capture event.

0

20

RT2

If this bit is 1, TC2 is reset by a channel 2 capture event.

0

Reserved.

-

31:21 -

33.7.2.2 MCPWM Capture Control set address
Writing ones to this write-only address sets the corresponding bits in CAPCON.
Table 805. MCPWM Capture Control set address (CAPCON_SET - 0x400A 0010) bit
description

UM10503

User manual

Bit

Symbol

Description

0

CAP0MCI0_RE_SET

Writing a one sets the corresponding bits in the CAPCON register.

1

CAP0MCI0_FE_SET

Writing a one sets the corresponding bits in the CAPCON register.

2

CAP0MCI1_RE_SET

Writing a one sets the corresponding bits in the CAPCON register.

3

CAP0MCI1_FE_SET

Writing a one sets the corresponding bits in the CAPCON register.

4

CAP0MCI2_RE_SET

Writing a one sets the corresponding bits in the CAPCON register.

5

CAP0MCI2_FE_SET

Writing a one sets the corresponding bits in the CAPCON register.

6

CAP1MCI0_RE_SET

Writing a one sets the corresponding bits in the CAPCON register.

7

CAP1MCI0_FE_SET

Writing a one sets the corresponding bits in the CAPCON register.

8

CAP1MCI1_RE_SET

Writing a one sets the corresponding bits in the CAPCON register.

9

CAP1MCI1_FE_SET

Writing a one sets the corresponding bits in the CAPCON register.

10

CAP1MCI2_RE_SET

Writing a one sets the corresponding bits in the CAPCON register.

11

CAP1MCI2_FE_SET

Writing a one sets the corresponding bits in the CAPCON register.

12

CAP2MCI0_RE_SET

Writing a one sets the corresponding bits in the CAPCON register.

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Table 805. MCPWM Capture Control set address (CAPCON_SET - 0x400A 0010) bit
description
Bit

Symbol

Description

13

CAP2MCI0_FE_SET

Writing a one sets the corresponding bits in the CAPCON register.

14

CAP2MCI1_RE_SET

Writing a one sets the corresponding bits in the CAPCON register.

15

CAP2MCI1_FE_SET

Writing a one sets the corresponding bits in the CAPCON register.

16

CAP2MCI2_RE_SET

Writing a one sets the corresponding bits in the CAPCON register.

17

CAP2MCI2_FE_SET

Writing a one sets the corresponding bits in the CAPCON register.

18

RT0_SET

Writing a one sets the corresponding bits in the CAPCON register.

19

RT1_SET

Writing a one sets the corresponding bits in the CAPCON register.

20

RT2_SET

Writing a one sets the corresponding bits in the CAPCON register.

31:21 -

Reset
value

Reserved.

-

33.7.2.3 MCPWM Capture control clear address
Writing ones to this write-only address clears the corresponding bits in MCCAPCON.
Table 806. MCPWM Capture control clear register (CAPCON_CLR - address 0x400A 0014) bit
description

UM10503

User manual

Bit

Symbol

Description

Reset
value

0

CAP0MCI0_RE_CLR

Writing a one clears the corresponding bits in the
CAPCON register.

-

1

CAP0MCI0_FE_CLR

Writing a one clears the corresponding bits in the
CAPCON register.

-

2

CAP0MCI1_RE_CLR

Writing a one clears the corresponding bits in the
CAPCON register.

-

3

CAP0MCI1_FE_CLR

Writing a one clears the corresponding bits in the
CAPCON register.

-

4

CAP0MCI2_RE_CLR

Writing a one clears the corresponding bits in the
CAPCON register.

-

5

CAP0MCI2_FE_CLR

Writing a one clears the corresponding bits in the
CAPCON register.

-

6

CAP1MCI0_RE_CLR

Writing a one clears the corresponding bits in the
CAPCON register.

-

7

CAP1MCI0_FE_CLR

Writing a one clears the corresponding bits in the
CAPCON register.

-

8

CAP1MCI1_RE_CLR

Writing a one clears the corresponding bits in the
CAPCON register.

-

9

CAP1MCI1_FE_CLR

Writing a one clears the corresponding bits in the
CAPCON register.

-

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Table 806. MCPWM Capture control clear register (CAPCON_CLR - address 0x400A 0014) bit
description
Bit

Symbol

Description

Reset
value

10

CAP1MCI2_RE_CLR

Writing a one clears the corresponding bits in the
CAPCON register.

-

11

CAP1MCI2_FE_CLR

Writing a one clears the corresponding bits in the
CAPCON register.

-

12

CAP2MCI0_RE_CLR

Writing a one clears the corresponding bits in the
CAPCON register.

-

13

CAP2MCI0_FE_CLR

Writing a one clears the corresponding bits in the
CAPCON register.

-

14

CAP2MCI1_RE_CLR

Writing a one clears the corresponding bits in the
CAPCON register.

-

15

CAP2MCI1_FE_CLR

Writing a one clears the corresponding bits in the
CAPCON register.

-

16

CAP2MCI2_RE_CLR

Writing a one clears the corresponding bits in the
CAPCON register.

-

17

CAP2MCI2_FE_CLR

Writing a one clears the corresponding bits in the
CAPCON register.

-

18

RT0_CLR

Writing a one clears the corresponding bits in the
CAPCON register.

-

19

RT1_CLR

Writing a one clears the corresponding bits in the
CAPCON register.

-

20

RT2_CLR

Writing a one clears the corresponding bits in the
CAPCON register.

-

Reserved.

-

31:21 -

33.7.3 MCPWM Timer/Counter 0-2 registers
These registers hold the current values of the 32-bit counter/timers for channels 0-2. Each
value is incremented on every PCLK, or by edges on the MCI0-2 pins, as selected by
CNTCON. The timer/counter counts up from 0 until it reaches the value in its
corresponding PER register (or is stopped by writing to CON_CLR).
A TC register can be read at any time. In order to write to the TC register, its channel must
be stopped. If not, the write will not take place, no exception is generated.
Table 807. MCPWM Timer/Counter 0 to 2 registers (TC - 0x400A 0018 (TC0), 0x400A 001C
(TC1), 0x400A 0020) (TC2)bit description
Bit

Symbol

Description

Reset
value

31:0

MCTC

Timer/Counter value.

0

33.7.4 MCPWM Limit 0-2 registers
These registers hold the limiting values for timer/counters 0-2. When a timer/counter
reaches its corresponding limiting value: 1) in edge-aligned mode, it is reset and starts
over at 0; 2) in center-aligned mode, it begins counting down until it reaches 0, at which
time it begins counting up again.

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Chapter 33: LPC43xx/LPC43Sxx Motor Control PWM (MOTOCONPWM)

If the channel’s CENTER bit in CON is 0 selecting edge-aligned mode, the match between
TC and LIM switches the channel’s A output from “active” to “passive” state. If the
channel’s CENTER and DTE bits in CON are both 0, the match simultaneously switches
the channel’s B output from “passive” to “active” state.
If the channel’s CENTER bit is 0 but the DTE bit is 1, the match triggers the channel’s
deadtime counter to begin counting -- when the deadtime counter expires, the channel’s B
output switches from “passive” to “active” state.
In center-aligned mode, matches between a channel’s TC and LIM registers have no
effect on its A and B outputs.
Writing to either a Limit or a Match (33.7.5) register loads a “write” register, and if the
channel is stopped it also loads an “operating” register that is compared to the TC. If the
channel is running and its “disable update” bit in CON is 0, the operating registers are
loaded from the write registers: 1) in edge-aligned mode, when the TC matches the
operating Limit register; 2) in center-aligned mode, when the TC counts back down to 0. If
the channel is running and the “disable update” bit is 1, the operating registers are not
loaded from the write registers until software stops the channel.
Reading an LIM address always returns the operating value.
Table 808. MCPWM Limit 0 to 2 registers (LIM - 0x400A 0024 (LIM0), 0x400A 0028 (LIM1),
0x400A 002C (LIM2)) bit description
Bit

Symbol

Description

Reset value

31:0

MCLIM

Limit value.

0xFFFF FFFF

Remark: In timer mode, the period of a channel’s modulated MCO outputs is determined
by its Limit register, and the pulse width at the start of the period is determined by its
Match register. If it suits your way of thinking, consider the Limit register to be the “Period
register” and the Match register to be the “Pulse Width register”.

33.7.5 MCPWM Match 0-2 registers
These registers also have “write” and “operating” versions as described above for the
Limit registers, and the operating registers are also compared to the channels’ TCs. See
33.7.4 above for details of reading and writing both Limit and Match registers.
The Match and Limit registers control the MCO0-2 outputs. If a Match register is to have
any effect on its channel’s operation, it must contain a smaller value than the
corresponding Limit register.
Table 809. MCPWM Match 0 to 2 registers (MAT - addresses 0x400A 0030 (MAT0),
0x400A 0034 (MAT1), 0x400A 0038 (MAT2)) bit description
Bit

Symbol

Description

Reset value

31:0

MCMAT

Match value.

0xFFFF FFFF

33.7.5.1 Match register in Edge-Aligned mode
If the channel’s CENTER bit in CON is 0 selecting edge-aligned mode, a match between
TC and MAT switches the channel’s B output from “active” to “passive” state. If the
channel’s CENTER and DTE bits in CON are both 0, the match simultaneously switches
the channel’s A output from “passive” to “active” state.

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If the channel’s CENTER bit is 0 but the DTE bit is 1, the match triggers the channel’s
deadtime counter to begin counting -- when the deadtime counter expires, the channel’s A
output switches from “passive” to “active” state.

33.7.5.2 Match register in Center-Aligned mode
If the channel’s CENTER bit in CON is 1 selecting center-aligned mode, a match between
TC and MAT while the TC is incrementing switches the channel’s B output from “active” to
“passive” state, and a match while the TC is decrementing switches the A output from
“active” to “passive”. If the channel’s CENTER bit in CON is 1 but the DTE bit is 0, a match
simultaneously switches the channel’s other output in the opposite direction.
If the channel’s CENTER and DTE bits are both 1, a match between TC and MAT triggers
the channel’s deadtime counter to begin counting -- when the deadtime counter expires,
the channel’s B output switches from “passive” to “active” if the TC was counting up at the
time of the match, and the channel’s A output switches from “passive” to “active” if the TC
was counting down at the time of the match.

33.7.5.3 0 and 100% duty cycle
To lock a channel’s MCO outputs at the state “B active, A passive”, write its Match register
with a higher value than you write to its Limit register. The match never occurs.
To lock a channel’s MCO outputs at the opposite state, “A active, B passive”, simply write
0 to its Match register.

33.7.6 MCPWM Dead-time register
This register holds the dead-time values for the three channels. If a channel’s DTE bit in
CON is 1 to enable its dead-time counter, the counter counts down from this value
whenever one its channel’s outputs changes from “active” to “passive” state. When the
dead-time counter reaches 0, the channel changes its other output from “passive” to
“active” state.
The motivation for the dead-time feature is that power transistors, like those driven by the
A and B outputs in a motor-control application, take longer to fully turn off than they take to
start to turn on. If the A and B transistors are ever turned on at the same time, a wasteful
and damaging current will flow between the power rails through the transistors. In such
applications, the dead-time register should be programmed with the number of PCLK
periods that is greater than or equal to the transistors’ maximum turn-off time minus their
minimum turn-on time.
Table 810. MCPWM Dead-time register (DT - address 0x400A 003C) bit description
Bit

UM10503

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Symbol

Description

Reset value

0.[1]

0x3FF

9:0

DT0

Dead time for channel

19:10

DT1

Dead time for channel 1.[2]

0x3FF

29:20

DT2

Dead time for channel 2.[2]

0x3FF

31:30

-

reserved

[1]

If ACMODE is 1 selecting AC-mode, this field controls the dead time for all three channels.

[2]

If ACMODE is 0.

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33.7.7 MCPWM Communication Pattern register
This register is used in DC mode only. The internal MCOA0 signal is routed to any or all of
the six output pins under the control of the bits in this register. Like the Match and Limit
registers, this register has “write” and “operational” versions. See 33.7.4 and 33.8.2 for
more about this subject.
Table 811. MCPWM Communication Pattern register (CP - address 0x400A 0040) bit
description
Bit

Symbol

0

CCPA0

Value Description

Communication pattern output A, channel 0.
0
1

1

2

3

4

CCPB0

MCOA0 passive.
internal MCOA0.

0

MCOB0 passive.

1

MCOB0 tracks internal MCOA0.

CCPA1

0

Communication pattern output A, channel 1.
0

MCOA1 passive.

1

MCOA1 tracks internal MCOA0.

CCPB1

0

Communication pattern output B, channel 1.
0

MCOB1 passive.

1

MCOB1 tracks internal MCOA0.

CCPA2

0

Communication pattern output A, channel 2.
1

31:6

0

Communication pattern output B, channel 0.

0
5

Reset
value

CCPB2

0

MCOA2 passive.
MCOA2 tracks internal MCOA0.
Communication pattern output B, channel 2.

-

0

MCOB2 passive.

1

MCOB2 tracks internal MCOA0.

0

Reserved.

33.7.8 MCPWM Capture read addresses
The CAPCON register (Table 804) allows software to select any edge(s) on any of the
MCI0-2 inputs as a capture event for each channel. When a channel’s capture event
occurs, the current TC value for that channel is stored in its read-only Capture register.
These addresses are read-only, but the underlying registers can be cleared by writing to
the CAP_CLR address
Table 812. MCPWM Capture read addresses (CAP - 0x400A 0044 (CAP0), 0x400A 0048
(CAP1), 0x400A 004C 9CAP2)) bit description
Bit

Symbol

Description

Reset
value

31:0

CAP

Current TC value at a capture event.

0x0000 00
00

33.7.9 MCPWM Interrupt registers
The Motor Control PWM module includes the following interrupt sources:
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Table 813. Motor Control PWM interrupts
Symbol

Description

ILIM0/1/2

Limit interrupts for channels 0, 1, 2.

IMAT0/1/2

Match interrupts for channels 0, 1, 2.

ICAP0/1/2

Capture interrupts for channels 0, 1, 2.

ABORT

Fast abort interrupt

7.9.1 MCPWM Interrupt Enable read address
The INTEN register controls which of the MCPWM interrupts are enabled. This address is
read-only, but the underlying register can be modified by writing to addresses INTEN_SET
and INTEN_CLR.
Table 814. MCPWM Interrupt Enable read address (INTEN - 0x400A 0050) bit description
Bit

Symbol

0

ILIM0

1

Value

0

Interrupt disabled.
Interrupt enabled.

IMAT0

Match interrupt for channel 0.

ICAP0

0

Interrupt disabled.
Interrupt enabled.
Capture interrupt for channel 0.

0

Interrupt disabled.

1

Interrupt enabled.

0

3

-

Reserved.

-

4

ILIM1

Limit interrupt for channel 1.

0

5

6

0

Interrupt disabled.

1

Interrupt enabled.

0

Interrupt disabled.

1

Interrupt enabled.

IMAT1

Match interrupt for channel 1.

ICAP1

Capture interrupt for channel 1.
0

Interrupt disabled.

1

Interrupt enabled.

0

0

7

-

Reserved.

-

8

ILIM2

Limit interrupt for channel 2.

0

9

User manual

Limit interrupt for channel 0.

1

1

UM10503

Reset
value

0

0
2

Description

0

Interrupt disabled.

1

Interrupt enabled.

IMAT2

Match interrupt for channel 2.
0

Interrupt disabled.

1

Interrupt enabled.

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Table 814. MCPWM Interrupt Enable read address (INTEN - 0x400A 0050) bit description
Bit

Symbol

10

ICAP2

Value

Description

Reset
value

Capture interrupt for channel 2.

0

0

Interrupt disabled.

1

Interrupt enabled.

14:11

-

Reserved.

-

15

ABORT

Fast abort interrupt.

0

31:16

-

0

Interrupt disabled.

1

Interrupt enabled.
Reserved.

-

33.7.9.2 MCPWM Interrupt Enable set address
Writing ones to this write-only address sets the corresponding bits in INTEN, thus
enabling interrupts.
Table 815. MCPWM interrupt enable set register (INTEN_SET - address 0x400A 0054) bit
description
Bit

Symbol

Description

Reset
value

0

ILIM0_SET

Writing a one sets the corresponding bit in INTEN, thus enabling
the interrupt.

-

1

IMAT0_SET

Writing a one sets the corresponding bit in INTEN, thus enabling
the interrupt.

-

2

ICAP0_SET

Writing a one sets the corresponding bit in INTEN, thus enabling
the interrupt.

-

3

-

Reserved.

-

4

ILIM1_SET

Writing a one sets the corresponding bit in INTEN, thus enabling
the interrupt.

-

5

IMAT1_SET

Writing a one sets the corresponding bit in INTEN, thus enabling
the interrupt.

-

6

ICAP1_SET

Writing a one sets the corresponding bit in INTEN, thus enabling
the interrupt.

-

7

-

Reserved.

-

9

ILIM2_SET

Writing a one sets the corresponding bit in INTEN, thus enabling
the interrupt.

-

10

IMAT2_SET

Writing a one sets the corresponding bit in INTEN, thus enabling
the interrupt.

-

11

ICAP2_SET

Writing a one sets the corresponding bit in INTEN, thus enabling
the interrupt.

-

14:12 -

Reserved.

-

15

Writing a one sets the corresponding bit in INTEN, thus enabling
the interrupt.

-

Reserved.

-

ABORT_SET

31:16 -

33.7.9.3 MCPWM Interrupt Enable clear address
Writing ones to this write-only address clears the corresponding bits in INTEN, thus
disabling interrupts.
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Table 816. PWM interrupt enable clear register (INTEN_CLR - address 0x400A 0058) bit
description
Bit

Symbol

Description

0

ILIM0_CLR

Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt.

1

IMAT0_CLR

Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt.

2

ICAP0_CLR

Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt.

3

-

Reserved.

4

ILIM1_CLR

Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt.

5

IMAT1_CLR

Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt.

6

ICAP1_CLR

Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt.

7

-

Reserved.

8

ILIM2_CLR

Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt.

9

IMAT2_CLR

Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt.

10

ICAP2_CLR

Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt.

14:11 15

Reset
value

-

-

Reserved.

-

ABORT_CLR Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt.

31:16 -

Reserved.

-

33.7.10 MCPWM Count Control register
33.7.10.1 MCPWM Count Control read address
The CNTCON register controls whether the MCPWM channels are in timer or counter
mode, and in counter mode whether the counter advances on rising and/or falling edges
on any or all of the three MCI inputs. If timer mode is selected, the counter advances
based on the PCLK clock.
This address is read-only. To set or clear the register bits, write ones to the
CNTCON_SET or CNTCON_CLR address.
Table 817. MCPWM Count Control read address (CNTCON - 0x400A 005C) bit description
Bit

Symbol

0

TC0MCI0_RE

UM10503

User manual

Value Description

Reset
value

Counter 0 rising edge mode, channel 0.
0

A rising edge on MCI0 does not affect counter 0.

1

If MODE0 is 1, counter 0 advances on a rising edge on MCI0.

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Table 817. MCPWM Count Control read address (CNTCON - 0x400A 005C) bit description
Bit

Symbol

1

TC0MCI0_FE

2

Value Description

Counter 0 falling edge mode, channel 0.
0

A falling edge on MCI0 does not affect counter 0.

1

If MODE0 is 1, counter 0 advances on a falling edge on MCI0.

TC0MCI1_RE

Counter 0 rising edge mode, channel 1.
0
1

3

4

5

6

TC0MCI1_FE

A falling edge on MCI1 does not affect counter 0.

1

If MODE0 is 1, counter 0 advances on a falling edge on MCI1.
Counter 0 rising edge mode, channel 2.

0

A rising edge on MCI0 does not affect counter 0.

1

If MODE0 is 1, counter 0 advances on a rising edge on MCI2.

TC0MCI2_FE

Counter 0 falling edge mode, channel 2.
0

A falling edge on MCI0 does not affect counter 0.

1

If MODE0 is 1, counter 0 advances on a falling edge on MCI2.

TC1MCI0_RE

Counter 1 rising edge mode, channel 0.
1

8

9

10

11

12

13

TC1MCI0_FE

A falling edge on MCI0 does not affect counter 1.

1

If MODE1 is 1, counter 1 advances on a falling edge on MCI0.
Counter 1 rising edge mode, channel 1.

0

A rising edge on MCI1 does not affect counter 1.

1

If MODE1 is 1, counter 1 advances on a rising edge on MCI1.
Counter 1 falling edge mode, channel 1.

0

A falling edge on MCI0 does not affect counter 1.

1

If MODE1 is 1, counter 1 advances on a falling edge on MCI1.

TC1MCI2_RE

Counter 1 rising edge mode, channel 2.
0

A rising edge on MCI2 does not affect counter 1.

1

If MODE1 is 1, counter 1 advances on a rising edge on MCI2.

TC1MCI2_FE

Counter 1 falling edge mode, channel 2.
0

A falling edge on MCI2 does not affect counter 1.

1

If MODE1 is 1, counter 1 advances on a falling edge on MCI2.

0

A rising edge on MCI0 does not affect counter 2.

1

If MODE2 is 1, counter 2 advances on a rising edge on MCI0.

TC2MCI0_RE

Counter 2 rising edge mode, channel 0.

TC2MCI0_FE

UM10503

User manual

0

0

0

If MODE1 is 1, counter 1 advances on a rising edge on MCI0.

0

TC1MCI1_FE

0

A rising edge on MCI0 does not affect counter 1.
Counter 1 falling edge mode, channel 0.

TC1MCI1_RE

0

If MODE0 is 1, counter 0 advances on a rising edge on MCI1.

0
TC0MCI2_RE

0

A rising edge on MCI1 does not affect counter 0.
Counter 0 falling edge mode, channel 1.

0
7

Reset
value

Counter 2 falling edge mode, channel 0.
0

A falling edge on MCI0 does not affect counter 2.

1

If MODE2 is 1, counter 2 advances on a falling edge on MCI0.

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0

0

0

0

0

0

0

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Table 817. MCPWM Count Control read address (CNTCON - 0x400A 005C) bit description
Bit

Symbol

14

TC2MCI1_RE

15

16

17

30

31

Reset
value

Counter 2 rising edge mode, channel 1.
0

A rising edge on MCI1 does not affect counter 2.

1

If MODE2 is 1, counter 2 advances on a rising edge on MCI1.

TC2MCI1_FE

0

Counter 2 falling edge mode, channel 1.
0

A falling edge on MCI1 does not affect counter 2.

1

If MODE2 is 1, counter 2 advances on a falling edge on MCI1.

TC2MCI2_RE

0

Counter 2 rising edge mode, channel 2.

0

0

A rising edge on MCI2 does not affect counter 2.

1

If MODE2 is 1, counter 2 advances on a rising edge on MCI2.

0

A falling edge on MCI2 does not affect counter 2.

1

If MODE2 is 1, counter 2 advances on a falling edge on MCI2.

-

Reserved.

-

Channel 0 counter/timer mode.

0

0

Channel 0 is in timer mode.

1

Channel 0 is in counter mode.

TC2MCI2_FE

28:18 29

Value Description

Counter 2 falling edge mode, channel 2.

CNTR0

CNTR1

0

Channel 1 counter/timer mode.
0

Channel 1 is in timer mode.

1

Channel 1 is in counter mode.

CNTR2

0

Channel 2 counter/timer mode.
0

Channel 2 is in timer mode.

1

Channel 2 is in counter mode.

0

33.7.10.2 MCPWM Count Control set address
Writing one(s) to this write-only address sets the corresponding bit(s) in CNTCON.
Table 818. MCPWM Count Control set address (CNTCON_SET - 0x400A 0060) bit description

UM10503

User manual

Bit

Symbol

Description

Reset
value

0

TC0MCI0_RE_SET

Writing a one sets the corresponding bit in the CNTCON
register.

-

1

TC0MCI0_FE_SET

Writing a one sets the corresponding bit in the CNTCON
register.

-

2

TC0MCI1_RE_SET

Writing a one sets the corresponding bit in the CNTCON
register.

-

3

TC0MCI1_FE_SET

Writing a one sets the corresponding bit in the CNTCON
register.

-

4

TC0MCI2_RE_SET

Writing a one sets the corresponding bit in the CNTCON
register.

-

5

TC0MCI2_FE_SET

Writing a one sets the corresponding bit in the CNTCON
register.

-

6

TC1MCI0_RE_SET

Writing a one sets the corresponding bit in the CNTCON
register.

-

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Table 818. MCPWM Count Control set address (CNTCON_SET - 0x400A 0060) bit description
Bit

Symbol

Description

Reset
value

7

TC1MCI0_FE_SET

Writing a one sets the corresponding bit in the CNTCON
register.

-

8

TC1MCI1_RE_SET

Writing a one sets the corresponding bit in the CNTCON
register.

-

9

TC1MCI1_FE_SET

Writing a one sets the corresponding bit in the CNTCON
register.

-

10

TC1MCI2_RE_SET

Writing a one sets the corresponding bit in the CNTCON
register.

-

11

TC1MCI2_FE_SET

Writing a one sets the corresponding bit in the CNTCON
register.

-

12

TC2MCI0_RE_SET

Writing a one sets the corresponding bit in the CNTCON
register.

-

13

TC2MCI0_FE_SET

Writing a one sets the corresponding bit in the CNTCON
register.

-

14

TC2MCI1_RE_SET

Writing a one sets the corresponding bit in the CNTCON
register.

-

15

TC2MCI1_FE_SET

Writing a one sets the corresponding bit in the CNTCON
register.

-

16

TC2MCI2_RE_SET

Writing a one sets the corresponding bit in the CNTCON
register.

-

17

TC2MCI2_FE_SET

Writing a one sets the corresponding bit in the CNTCON
register.

-

28:18 -

Reserved.

29

CNTR0_SET

Writing a one sets the corresponding bit in the CNTCON
register.

-

30

CNTR1_SET

Writing a one sets the corresponding bit in the CNTCON
register.

-

31

CNTR2_SET

Writing a one sets the corresponding bit in the CNTCON
register.

-

33.7.10.3 MCPWM Count Control clear address
Writing one(s) to this write-only address clears the corresponding bit(s) in CNTCON.
Table 819. MCPWM Count Control clear address (CNTCON_CLR - 0x400A 0064) bit
description

UM10503

User manual

Bit

Symbol

Description

Reset
value

0

TC0MCI0_RE_CLR Writing a one clears the corresponding bit in the CNTCON register.

1

TC0MCI0_FE_CLR

2

TC0MCI1_RE_CLR Writing a one clears the corresponding bit in the CNTCON register.

3

TC0MCI1_FE_CLR

Writing a one clears the corresponding bit in the CNTCON register.

Writing a one clears the corresponding bit in the CNTCON register.

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Table 819. MCPWM Count Control clear address (CNTCON_CLR - 0x400A 0064) bit
description
Bit

Symbol

Description

Reset
value

4

TC0MCI2_RE

Writing a one clears the corresponding bit in the CNTCON register.

5

TC0MCI2_FE_CLR

Writing a one clears the corresponding bit in the CNTCON register.

6

TC1MCI0_RE_CLR Writing a one clears the corresponding bit in the CNTCON register.

7

TC1MCI0_FE_CLR

8

TC1MCI1_RE_CLR Writing a one clears the corresponding bit in the CNTCON register.

9

TC1MCI1_FE_CLR

10

TC1MCI2_RE_CLR Writing a one clears the corresponding bit in the CNTCON register.

11

TC1MCI2_FE_CLR

12

TC2MCI0_RE_CLR Writing a one clears the corresponding bit in the CNTCON register.

13

TC2MCI0_FE_CLR

14

TC2MCI1_RE_CLR Writing a one clears the corresponding bit in the CNTCON register.

15

TC2MCI1_FE_CLR

16

TC2MCI2_RE_CLR Writing a one clears the corresponding bit in the CNTCON register.

17

TC2MCI2_FE_CLR

Writing a one clears the corresponding bit in the CNTCON register.

Writing a one clears the corresponding bit in the CNTCON register.

Writing a one clears the corresponding bit in the CNTCON register.

Writing a one clears the corresponding bit in the CNTCON register.

Writing a one clears the corresponding bit in the CNTCON register.

Writing a one clears the corresponding bit in the CNTCON register.

28:18 -

Reserved.

29

CNTR0_CLR

Writing a one clears the corresponding bit in the CNTCON register.

30

CNTR1_CLR

Writing a one clears the corresponding bit in the CNTCON register.

31

CNTR2_CLR

Writing a one clears the corresponding bit in the CNTCON register.

33.7.11 MCPWM Interrupt flag registers
33.7.11.1 MCPWM Interrupt Flags read address
The INTF register includes all MCPWM interrupt flags, which are set when the
corresponding hardware event occurs, or when ones are written to the INTF_SET
address. When corresponding bits in this register and INTEN are both 1, the MCPWM
asserts its interrupt request to the Interrupt Controller module. This address is read-only,
but the bits in the underlying register can be modified by writing ones to addresses
INTF_SET and INTF_CLR.
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Chapter 33: LPC43xx/LPC43Sxx Motor Control PWM (MOTOCONPWM)

Table 820. MCPWM Interrupt flags read address (INTF - 0x400A 0068) bit description
Bit

Symbol

0

ILIM0_F

1

2

Limit interrupt flag for channel 0.

0

0

This interrupt source is not contributing to the MCPWM
interrupt request.

1

If the corresponding bit in INTEN is 1, the MCPWM module is
asserting its interrupt request to the Interrupt Controller.

IMAT0_F

Match interrupt flag for channel 0.

0

0

This interrupt source is not contributing to the MCPWM
interrupt request.

1

If the corresponding bit in INTEN is 1, the MCPWM module is
asserting its interrupt request to the Interrupt Controller.

ICAP0_F

Capture interrupt flag for channel 0.

0

0

This interrupt source is not contributing to the MCPWM
interrupt request.

1

If the corresponding bit in INTEN is 1, the MCPWM module is
asserting its interrupt request to the Interrupt Controller.

-

Reserved.

-

4

ILIM1_F

Limit interrupt flag for channel 1.

0

6

0

This interrupt source is not contributing to the MCPWM
interrupt request.

1

If the corresponding bit in INTEN is 1, the MCPWM module is
asserting its interrupt request to the Interrupt Controller.

IMAT1_F

Match interrupt flag for channel 1.

0

0

This interrupt source is not contributing to the MCPWM
interrupt request.

1

If the corresponding bit in INTEN is 1, the MCPWM module is
asserting its interrupt request to the Interrupt Controller.

ICAP1_F

Capture interrupt flag for channel 1.

0

0

This interrupt source is not contributing to the MCPWM
interrupt request.

1

If the corresponding bit in INTEN is 1, the MCPWM module is
asserting its interrupt request to the Interrupt Controller.

7

-

Reserved.

-

8

ILIM2_F

Limit interrupt flag for channel 2.

0

9

User manual

Reset
value

3

5

UM10503

Value Description

0

This interrupt source is not contributing to the MCPWM
interrupt request.

1

If the corresponding bit in INTEN is 1, the MCPWM module is
asserting its interrupt request to the Interrupt Controller.

IMAT2_F

Match interrupt flag for channel 2.

0

0

This interrupt source is not contributing to the MCPWM
interrupt request.

1

If the corresponding bit in INTEN is 1, the MCPWM module is
asserting its interrupt request to the Interrupt Controller.

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Chapter 33: LPC43xx/LPC43Sxx Motor Control PWM (MOTOCONPWM)

Table 820. MCPWM Interrupt flags read address (INTF - 0x400A 0068) bit description
Bit

Symbol

10

ICAP2_F

Value Description

Reset
value

Capture interrupt flag for channel 2.

0

0

This interrupt source is not contributing to the MCPWM
interrupt request.

1

If the corresponding bit in INTEN is 1, the MCPWM module is
asserting its interrupt request to the Interrupt Controller.

14:11 -

Reserved.

-

15

Fast abort interrupt flag.

0

ABORT_F
0

This interrupt source is not contributing to the MCPWM
interrupt request.

1

If the corresponding bit in INTEN is 1, the MCPWM module is
asserting its interrupt request to the Interrupt Controller.

31:16 -

Reserved.

-

33.7.11.2 MCPWM Interrupt Flags set address
Writing one(s) to this write-only address sets the corresponding bit(s) in INTF, thus
possibly simulating hardware interrupt(s).
Table 821. MCPWM Interrupt Flags set address (INTF_SET - 0x400A 006C) bit description
Bit

Symbol

Description

Reset
value

0

ILIM0_F_SET

Writing a one sets the corresponding bit in the INTF register,
thus possibly simulating hardware interrupt.

-

1

IMAT0_F_SET

Writing a one sets the corresponding bit in the INTF register,
thus possibly simulating hardware interrupt.

-

2

ICAP0_F_SET

Writing a one sets the corresponding bit in the INTF register,
thus possibly simulating hardware interrupt.

-

3

-

Reserved.

-

4

ILIM1_F_SET

Writing a one sets the corresponding bit in the INTF register,
thus possibly simulating hardware interrupt.

-

5

IMAT1_F_SET

Writing a one sets the corresponding bit in the INTF register,
thus possibly simulating hardware interrupt.

-

6

ICAP1_F_SET

Writing a one sets the corresponding bit in the INTF register,
thus possibly simulating hardware interrupt.

-

7

-

Reserved.

-

8

ILIM2_F_SET

Writing a one sets the corresponding bit in the INTF register,
thus possibly simulating hardware interrupt.

-

9

IMAT2_F_SET

Writing a one sets the corresponding bit in the INTF register,
thus possibly simulating hardware interrupt.

-

10

ICAP2_F_SET

Writing a one sets the corresponding bit in the INTF register,
thus possibly simulating hardware interrupt.

-

Reserved.

-

14:11 15

ABORT_F_SET Writing a one sets the corresponding bit in the INTF register,
thus possibly simulating hardware interrupt.

31:16 -

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Reserved.

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33.7.11.3 MCPWM Interrupt Flags clear address
Writing one(s) to this write-only address sets the corresponding bit(s) in INTF, thus
clearing the corresponding interrupt request(s). This is typically done in interrupt service
routines.
Table 822. MCPWM Interrupt Flags clear address (INTF_CLR - 0x400A 0070) bit description
Bit

Symbol

Description

0

ILIM0_F_CLR

Writing a one clears the corresponding bit in the INTF register, thus clearing the corresponding interrupt request.

1

IMAT0_F_CLR

Writing a one clears the corresponding bit in INTEN, thus
disabling the interrupt.

-

2

ICAP0_F_CLR

Writing a one clears the corresponding bit in INTEN, thus
disabling the interrupt.

-

3

-

Reserved.

-

4

ILIM1_F_CLR

Writing a one clears the corresponding bit in INTEN, thus
disabling the interrupt.

-

5

IMAT1_F_CLR

Writing a one clears the corresponding bit in INTEN, thus
disabling the interrupt.

-

6

ICAP1_F_CLR

Writing a one clears the corresponding bit in INTEN, thus
disabling the interrupt.

-

7

-

Reserved.

-

8

ILIM2_F_CLR

Writing a one clears the corresponding bit in INTEN, thus
disabling the interrupt.

-

9

IMAT2_F_CLR

Writing a one clears the corresponding bit in INTEN, thus
disabling the interrupt.

-

10

ICAP2_F_CLR

Writing a one clears the corresponding bit in INTEN, thus
disabling the interrupt.

-

14:11

-

Writing a one clears the corresponding bit in INTEN, thus
disabling the interrupt.

-

15

ABORT_F_CLR

Writing a one clears the corresponding bit in INTEN, thus
disabling the interrupt.

-

Reserved.

-

31:16 -

Reset
value

33.7.12 MCPWM Capture clear address
Writing ones to this write-only address clears the selected CAP register(s).
Table 823. MCPWM Capture clear address (CAP_CLR - 0x400A 0074) bit description

UM10503

User manual

Bit

Symbol

Description

0

CAP_CLR0

Writing a 1 to this bit clears the CAP0 register.

1

CAP_CLR1

Writing a 1 to this bit clears the CAP1 register.

2

CAP_CLR2

Writing a 1 to this bit clears the CAP2 register.

31:3

-

Reserved

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33.8 Functional description
33.8.1 Pulse-width modulation
Each channel of the MCPWM has two outputs, A and B, that can drive a pair of transistors
to switch a controlled point between two power rails. Most of the time the two outputs have
opposite polarity, but a dead-time feature can be enabled (on a per-channel basis) to
delay both signals’ transitions from “passive” to “active” state so that the transistors are
never both turned on simultaneously. In a more general view, the states of each output
pair can be thought of “high”, “low”, and “floating” or “up”, “down”, and “center-off”.
Each channel’s mapping from “active” and “passive” to “high” and “low” is programmable.
After Reset, the three A outputs are passive/low, and the B outputs are active/high.
The MCPWM can perform edge-aligned and center-aligned pulse-width modulation.
Remark: In timer mode, the period of a channel’s modulated MCO outputs is determined
by its Limit register, and the pulse width at the start of the period is determined by its
Match register. If it suits your way of thinking, consider the Limit register to be the “Period
register” and the Match register to be the “Pulse Width register”.
Edge-aligned PWM without dead-time
In this mode the timer TC counts up from 0 to the value in the LIM register. As shown in
Figure 112, the MCO state is “A passive” until the TC matches the Match register, at which
point it changes to “A active”. When the TC matches the Limit register, the MCO state
changes back to “A passive”, and the TC is reset and starts counting up again.

active

passive

active

passive

passive

active

passive

active

MCOB

POLA = 0

MCOA

0

MAT

LIM
timer reset

MAT

LIM
timer reset

Fig 112. Edge-aligned PWM waveform without dead time, POLA = 0

Center-aligned PWM without dead-time
In this mode the timer TC counts up from 0 to the value in the LIM register, then counts
back down to 0 and repeats. As shown in Figure 113, while the timer counts up, the MCO
state is “A passive” until the TC matches the Match register, at which point it changes to “A
active”. When the TC matches the Limit register it starts counting down. When the TC
matches the Match register on the way down, the MCO state changes back to “A passive”.

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Chapter 33: LPC43xx/LPC43Sxx Motor Control PWM (MOTOCONPWM)

active

passive

active

passive

passive

active

passive

active

MCOB

POLA = 0

MCOA

MAT

0

LIM

0

MAT

LIM

Fig 113. Center-aligned PWM waveform without dead time, POLA = 0

Dead-time counter
When the a channel’s DTE bit is set in CON, the dead-time counter delays the
passive-to-active transitions of both MCO outputs. The dead-time counter starts counting
down, from the channel’s DT value (in the DT register) to 0, whenever the channel’s A or
B output changes from active to passive. The transition of the other output from passive to
active is delayed until the dead-time counter reaches 0. During the dead time, the MCOA
and MCOB output levels are both passive. Figure 114 shows operation in edge aligned
mode with dead time, and Figure 115 shows center-aligned operation with dead time.

active

active
passive

passive
MCOB

DT

DT

active
passive

active
passive

MCOA

POLA = 0
DT
0

MAT

LIM
timer reset

DT
MAT

LIM
timer reset

Fig 114. Edge-aligned PWM waveform with dead time, POLA = 0

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Chapter 33: LPC43xx/LPC43Sxx Motor Control PWM (MOTOCONPWM)

active

active

passive

passive

MCOB
DT

active

active
passive

passive
POLA = 0

MCOA
DT
0

MAT

LIM

DT
MAT

0

LIM

Fig 115. Center-aligned waveform with dead time, POLA = 0

33.8.2 Shadow registers and simultaneous updates
The Limit, Match, and Communication Pattern registers (LIM, MAT, and CP) are
implemented as register pairs, each consisting of a write register and an operational
register. Software writes into the write registers. The operational registers control the
actual operation of each channel and are loaded with the current value in the write
registers when the TC starts counting up from 0.
Updating of the functional registers can be disabled by setting a channel’s DISUP bit in
the CON register. If the DISUP bits are set, the functional registers are not updated until
software stops the channel.
If a channel is not running when software writes to its LIM or MAT register, the functional
register is updated immediately.
Software can write to a TC register only when its channel is stopped.

33.8.3 Fast Abort (ABORT)
The MCPWM has an external input MCABORT. When this input goes low, all six MCO
outputs assume their “A passive” states, and the Abort interrupt is generated if enabled.
The outputs remain locked in “A passive” state until the ABORT interrupt flag is cleared or
the Abort interrupt is disabled. The ABORT flag may not be cleared before the MCABORT
input goes high.
In order to clear an ABORT flag, a 1 must be written to bit 15 of the INTF_CLR register.
This will remove the interrupt request. The interrupt can also be disabled by writing a 1 to
bit 15 of the INTEN_CLR register.

33.8.4 Capture events
Each PWM channel can take a snapshot of its TC when an input signal transitions. Any
channel may use any combination of rising and/or falling edges on any or all of the MCI0-2
inputs as a capture event, under control of the CAPCON register. Rising or falling edges
on the inputs are detected synchronously with respect to PCLK.
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A capture event on a channel causes the following:

• The current value of the TC is stored in the Capture register (CAP).
• If the channel’s capture event interrupt is enabled (see Table 814), the capture event
interrupt flag is set.

• If the channel’s RT bit is set in the CAPCON register, enabling reset on a capture
event, the input event has the same effect as matching the channel’s TC to its LIM
register. This includes resetting the TC and switching the MCO pin(s) in edge-aligned
mode as described in 33.7.4 and 33.8.1.

33.8.5 External event counting (Counter mode)
If a channel’s MODE bit is 1 in CNTCON, its TC is incremented by rising and/or falling
edge(s) (synchronously detected) on the MCI0-2 input(s), rather than by PCLK. The PWM
functions and capture functions are unaffected.

33.8.6 Three-phase DC mode
The three-phase DC mode is selected by setting the DCMODE bit in the CON register.
In this mode, the internal MCOA0 signal can be routed to any or all of the MCO outputs.
Each MCO output is masked by a bit in the current commutation pattern register CP. If a
bit in the CP register is 0, its output pin has the logic level for the passive state of output
MCOA0. The polarity of the off state is determined by the POLA0 bit.
All MCO outputs that have 1 bits in the CP register are controlled by the internal MCOA0
signal.
The three MCOB output pins are inverted when the INVBDC bit is 1 in the CON register.
This feature accommodates bridge-drivers that have active-low inputs for the low-side
switches.
The CP register is implemented as a shadow register pair, so that changes to the active
communication pattern occur at the beginning of a new PWM cycle. See 33.7.4 and
33.8.2 for more about writing and reading such registers.
Figure 116 shows sample waveforms of the MCO outputs in three-phase DC mode. Bits 1
and 3 in the CP register (corresponding to outputs MCOB1 and MCOB0) are set to 0 so
that these outputs are masked and in the off state. Their logic level is determined by the
POLA0 bit (here, POLA0 = 0 so the passive state is logic LOW). The INVBDC bit is set to
0 (logic level not inverted) so that the B output have the same polarity as the A outputs.
Note that this mode differs from other modes in that the MCOB outputs are not the
opposite of the MCOA outputs.
In the situation shown in Figure 116, bits 0, 2, 4, and 5 in the CP register are set to 1. That
means that MCOA1 and both MCO outputs for channel 2 follow the MCOA0 signal.

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Chapter 33: LPC43xx/LPC43Sxx Motor Control PWM (MOTOCONPWM)

MCOB2

CCPB2 = 1, on-state

MCOA2

CCPA2 = 1, on-state

MCOB1

CCPB1 = 0, off-state

MCOA1

CCPA1 = 1, on-state

MCOB0

CCPB0 = 0, off-state

CCPA0 = 1, on-state
MCOA0

POLA0 = 0, INVBDC = 0

Fig 116. Three-phase DC mode sample waveforms

33.8.7 Three phase AC mode
The three-phase AC-mode is selected by setting the ACMODE bit in the CON register.
In this mode, the value of channel 0’s TC is routed to all channels for comparison with
their MAT registers. (The LIM1-2 registers are not used.)
Each channel controls its MCO output by comparing its MAT value to TC0.
Figure 117 shows sample waveforms for the six MCO outputs in three-phase AC mode.
The POLA bits are set to 0 for all three channels, so that for all MCO outputs the active
levels are high and the passive levels are low. Each channel has a different MAT value
which is compared to the TC0 value. In this mode the period value is identical for all three
channels and is determined by LIM0. The dead-time mode is disabled.

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Chapter 33: LPC43xx/LPC43Sxx Motor Control PWM (MOTOCONPWM)

MCOB2

POLA2 = 0
MCOA2
MAT2

MAT2

MCOB1

POLA1 = 0

MCOA1
MAT1

MAT1

MCOB0

POLA0 = 0

MCOA0

0

MAT0

LIM0
timer reset

LIM0
timer reset

Fig 117. Three-phase AC mode sample waveforms, edge aligned PWM mode

33.8.8 Interrupts
The MCPWM includes 10 possible interrupt sources:

• When any channel’s TC matches its Match register.
• When any channel’s TC matches its Limit register.
• When any channel captures the value of its TC into its Capture register, because a
selected edge occurs on any of MCI0-2.

• When all three channels’ outputs are forced to “A passive” state because the
MCABORT pin goes low.
Section 33.7.9 “MCPWM Interrupt registers” explains how to enable these interrupts, and
Section 33.7.2 “PWM Capture Control register” describes how to map edges on the
MCI0-2 inputs to “capture events” on the three channels.

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Chapter 34: LPC43xx/LPC43Sxx Quadrature Encoder
Interface (QEI)
Rev. 2.4 — 22 August 2018

User manual

34.1 How to read this chapter
The QEI is available on all LPC435x/3x parts.

34.2 Basic configuration
The QEI is configured as follows:

• See Table 824 for clocking and power control.
• The QEI is reset by the QEI_RST (reset #39).
• The QEI interrupt is connected to slot # 15 in the Event router.
Table 824. QEI clocking and power control
Base clock

Clock to the QEI register interface and QEI BASE_M4_CLK
peripheral clock.

Branch clock

Operating
frequency

CLK_M4_QEI

up to
204 MHz

34.3 Features
This Quadrature Encoder Interface (QEI) has the following features:

•
•
•
•
•
•
•
•
•
•

Tracks encoder position.
Increments/ decrements depending on direction.
Programmable for 2X or 4X position counting.
Velocity capture using built-in timer.
Velocity compare function with less than interrupt.
Uses 32-bit registers for position and velocity.
Three position compare registers with interrupts.
Index counter for revolution counting.
Index compare register with interrupts.
Can combine index and position interrupts to produce an interrupt for whole and
partial revolution displacement.

• Digital filter with programmable delays for encoder input signals.
• Can accept decoded signal inputs (clock and direction).

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Chapter 34: LPC43xx/LPC43Sxx Quadrature Encoder Interface (QEI)

34.4 Introduction
A quadrature encoder, also known as a 2-channel incremental encoder, converts angular
displacement into two pulse signals. By monitoring both the number of pulses and the
relative phase of the two signals, you can track the position, direction of rotation, and
velocity. In addition, a third channel, or index signal, can be used to reset the position
counter. This quadrature encoder interface module decodes the digital pulses from a
quadrature encoder wheel to integrate position over time and determine direction of
rotation. In addition, it can capture the velocity of the encoder wheel.

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Chapter 34: LPC43xx/LPC43Sxx Quadrature Encoder Interface (QEI)

PC LK

Phb

Pha

i dx

rst
Velocity Timer

tim _int

rst

Inx

Velocity Reload

gating

Velocity Compare

Digital Filter

velc _int

rst
Velocity Capture
Quad Decoder

err _int

Velocity Counter
inx _int
dir _int
enclk _int

Windowing

Inx_
pulse

dir

MaxPos Compare

clk _

max _pos _int

pulse

Position Counter

Position Compare

Index Counter

Index Compare

pos 0rev _int
pos 1rev _int
pos 2rev _int

pos 0rev _int
pos 1rev _int
pos 2rev _int

rev 0_ int
rev 1_ int
rev 2_ int

Fig 118.Encoder interface block diagram

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Chapter 34: LPC43xx/LPC43Sxx Quadrature Encoder Interface (QEI)

34.5 Pin description
Table 825. QEI pin description
Pin
function

I/O

Description

QEI_A

I

Used as the Phase A (PhA) input to the Quadrature Encoder Interface.

QEI_B

I

Used as the Phase B (PhB) input to the Quadrature Encoder Interface.

QEI_IDX

I

Used as the Index (IDX) input to the Quadrature Encoder Interface.

34.6 Register description
Table 826. Register overview: QEI (base address 0x400C 6000)
Name

Access

Address
offset

Description

Reset value

Reference

Control registers

CON

WO

0x000

Control register

0

Table 827

STAT

RO

0x004

Encoder status register

0

Table 828

CONF

R/W

0x008

Configuration register

0x000F 0000

Table 829

Position, index, and timer registers

POS

RO

0x00C

Position register

0

Table 830

MAXPOS

R/W

0x010

Maximum position register

0

Table 831

CMPOS0

R/W

0x014

position compare register 0

0xFFFF FFFF Table 832

CMPOS1

R/W

0x018

position compare register 1

0xFFFF FFFF Table 833

CMPOS2

R/W

0x01C

position compare register 2

0xFFFF FFFF Table 834

INXCNT

RO

0x020

Index count register

0

INXCMP0

R/W

0x024

Index compare register 0

0xFFFF FFFF Table 836

LOAD

R/W

0x028

Velocity timer reload register

0xFFFF FFFF Table 837

TIME

RO

0x02C

Velocity timer register

0xFFFF FFFF Table 838

VEL

RO

0x030

Velocity counter register

0

CAP

RO

0x034

Velocity capture register

0xFFFF FFFF Table 840

VELCOMP

R/W

0x038

Velocity compare register

0

Table 841

FILTERPHA R/W

0x03C

Digital filter register on input
phase A (QEI_A)

0

Table 842

FILTERPHB R/W

0x040

Digital filter register on input
phase B (QEI_B)

0

Table 843

FILTERINX

R/W

0x044

Digital filter register on input
index (QEI_IDX)

0

Table 844

WINDOW

R/W

0x048

Index acceptance window
register

0x0000 0000

Table 845

INXCMP1

R/W

0x04C

Index compare register 1

0xFFFF FFFF Table 846

INXCMP2

R/W

0x050

Index compare register 2

0xFFFF FFFF Table 847

Table 835

Table 839

Interrupt registers

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IEC

WO

0xFD8

Interrupt enable clear register

0

Table 848

IES

WO

0xFDC

Interrupt enable set register

0

Table 849

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Chapter 34: LPC43xx/LPC43Sxx Quadrature Encoder Interface (QEI)

Table 826. Register overview: QEI (base address 0x400C 6000)

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Name

Access

Address
offset

Description

Reset value

Reference

INTSTAT

RO

0xFE0

Interrupt status register

0

Table 850

IE

RO

0xFE4

Interrupt enable register

0

Table 851

CLR

WO

0xFE8

Interrupt status clear register

0

Table 852

SET

WO

0xFEC

Interrupt status set register

0

Table 853

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Chapter 34: LPC43xx/LPC43Sxx Quadrature Encoder Interface (QEI)

34.6.1 Control registers
34.6.1.1 QEI Control register
This register contains bits which control the operation of the position and velocity counters
of the QEI module.
Table 827: QEI Control register (CON - address 0x400C 6000) bit description
Bit

Symbol

Description

Reset
value

0

RESP

Reset position counter. When set = 1, resets the position counter to
all zeros. Autoclears when the position counter is cleared.

0

1

RESPI

Reset position counter on index. When set = 1, resets the position
counter to all zeros when an index pulse occurs. Autoclears when
the position counter is cleared.

0

2

RESV

Reset velocity. When set = 1, resets the velocity counter to all zeros 0
and reloads the velocity timer. Autoclears when the velocity counter
is cleared.

3

RESI

Reset index counter. When set = 1, resets the index counter to all
zeros. Autoclears when the index counter is cleared.

0

31:4

-

reserved

0

34.6.1.2 QEI Status register
This register provides the status of the encoder interface.
Table 828: QEI Interrupt Status register (STAT - address 0x400C 6004) bit description
Bit

Symbol

Description

Reset
value

0

DIR

Direction bit. In combination with DIRINV bit indicates forward or
reverse direction. See Table 856.

31:1

-

reserved

0

34.6.1.3 QEI Configuration register
This register contains the configuration of the QEI module.

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Chapter 34: LPC43xx/LPC43Sxx Quadrature Encoder Interface (QEI)

Table 829: QEI Configuration register (CONF - address 0x400C 6008) bit description

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Bit

Symbol

Description

Reset
value

0

DIRINV

Direction invert. When = 1, complements the DIR bit.

0

1

SIGMODE

Signal Mode. When = 0, PhA and PhB function as quadrature
encoder inputs. When = 1, PhA functions as the direction signal
and PhB functions as the clock signal.

0

2

CAPMODE Capture Mode. When = 0, only PhA edges are counted (2X).
When = 1, BOTH PhA and PhB edges are counted (4X),
increasing resolution but decreasing range.

0

3

INVINX

Invert Index. When set, inverts the sense of the index input.

0

4

CRESPI

Continuously reset position counter on index. When set = 1,
resets the position counter to all zeros when an index pulse
occurs at the next position increase (recalibration). Auto-clears
when the position counter is cleared.

0

15:5

-

Reserved

0

19:16

INXGATE

Index gating configuration:
when INXGATE(19)=1, pass the index when Pha=0 and Phb=0,
else block.
when INXGATE(18)=1, pass the index when Pha=0 and Phb=1,
else block.
when INXGATE(17)=1, pass the index when Pha=1 and Phb=1,
else block.
when INXGATE(16)=1, pass the index when Pha=1 and Phb=0,
else block.

1111

31:20

-

reserved

0

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Chapter 34: LPC43xx/LPC43Sxx Quadrature Encoder Interface (QEI)

34.6.2 Position, index and timer registers
34.6.2.1 QEI Position register
This register contains the current value of the encoder position. Increments or decrements
when encoder counts occur, depending on the direction of rotation.
Table 830. QEI Position register (POS - address 0x400C 600C) bit description
Bit

Symbol

Description

Reset value

31:0

POS

Current position value.

0

34.6.2.2 QEI Maximum Position register
This register contains the maximum value of the encoder position. In forward rotation the
position register resets to zero when the position register exceeds this value. In reverse
rotation the position register resets to this value when the position register decrements
from zero.
Table 831. QEI Maximum Position register (MAXPOS - address 0x400C 6010) bit description
Bit

Symbol

Description

Reset value

31:0

MAXPOS

Maximum position value.

0

34.6.2.3 QEI Position Compare register 0
This register contains a position compare value. This value is compared against the
current value of the position register. Interrupts can be enabled to interrupt when the
compare value is less than, equal to, or greater than the current value of the position
register.
Table 832. QEI Position Compare register 0 (CMPOS0 - address 0x400C 6014) bit description
Bit

Symbol

Description

Reset value

31:0

PCMP0

Position compare value 0.

0xFFFF FFFF

34.6.2.4 QEI Position Compare register 1
This register contains a position compare value. This value is compared against the
current value of the position register. Interrupts can be enabled to interrupt when the
compare value is less than, equal to, or greater than the current value of the position
register.
Table 833. QEI Position Compare register 1 (CMPOS1 - address 0x400C 6018) bit description
Bit

Symbol

Description

Reset value

31:0

PCMP1

Position compare value 1.

0xFFFF FFFF

34.6.2.5 QEI Position Compare register 2
This register contains a position compare value. This value is compared against the
current value of the position register. Interrupts can be enabled to interrupt when the
compare value is less than, equal to, or greater than the current value of the position
register.
Table 834. QEI Position Compare register 2 (CMPOS2 - address 0x400C 601C) bit description

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Bit

Symbol

Description

Reset value

31:0

PCMP2

Position compare value 2.

0xFFFF FFFF

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Chapter 34: LPC43xx/LPC43Sxx Quadrature Encoder Interface (QEI)

34.6.2.6 QEI Index Count register
This register contains the current value of the encoder position. Increments or decrements
when encoder counts occur, depending on the direction of rotation.
Table 835. QEI Index Count register (INXCNT- address 0x400C 6020) bit description
Bit

Symbol

Description

Reset value

31:0

ENCPOS

Current encoder position value.

0

34.6.2.7 QEI Index Compare register 0
This register contains an index compare value. This value is compared against the current
value of the index count register. Interrupts can be enabled to interrupt when the compare
value is less than, equal to, or greater than the current value of the index count register.
Table 836. QEI Index Compare register 0 (INXCMP0 - address 0x400C 6024) bit description
Bit

Symbol

Description

Reset value

31:0

ICMP0

Index compare value.

0xFFFF FFFF

34.6.2.8 QEI Timer Reload register
This register contains the reload value of the velocity timer. When the timer (TIME)
reaches zero or the RESV bit is asserted, this value is loaded into the timer (TIME).
Table 837. QEI Timer Load register (LOAD - address 0x400C 6028) bit description
Bit

Symbol

Description

Reset value

31:0

VELLOAD

Current velocity timer pre-load value.The velocity
timer counts down from this value.

0xFFFF FFFF

34.6.2.9 QEI Timer register
This register contains the current value of the velocity timer. When this timer reaches zero,
the value of velocity register (VEL) is stored in the velocity capture register (CAP), the
timer is reloaded with the value stored in the velocity reload register (LOAD), and the
velocity interrupt (TIM_Int) is asserted.
Table 838. QEI Timer register (TIME - address 0x400C 602C) bit description
Bit

Symbol

Description

Reset value

31:0

VELVAL

Current velocity timer value.

0xFFFF FFFF

34.6.2.10 QEI Velocity register
This register contains the running count of velocity pulses for the current time period.
When the velocity timer (TIME) reaches zero, the content of this register is captured in the
velocity capture register (CAP). After capture, this register is set to zero. This register is
also reset when the velocity reset bit (RESV) is asserted.
Table 839. QEI Velocity register (VEL - address 0x400C 6030) bit description

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Bit

Symbol

Description

Reset value

31:0

VELPC

Current velocity pulse count.

0x0

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Chapter 34: LPC43xx/LPC43Sxx Quadrature Encoder Interface (QEI)

34.6.2.11 QEI Velocity Capture register
This register contains the most recently measured velocity of the encoder. This
corresponds to the number of velocity pulses counted in the previous velocity timer
period.The current velocity count is latched into this register when the velocity timer
overflows.
Table 840. QEI Velocity Capture register (CAP - address 0x400C 6034) bit description
Bit

Symbol

Description

Reset value

31:0

VELCAP

Velocity capture value.

0xFFFF FFFF

34.6.2.12 QEI Velocity Compare register
This register contains a velocity compare value. This value is compared against the
captured velocity in the velocity capture register. If the capture velocity is less than the
value in this compare register, a velocity compare interrupt (VELC_Int) will be asserted, if
enabled.
Table 841. QEI Velocity Compare register (VELCOMP - address 0x400C 6038) bit description
Bit

Symbol

Description

Reset value

31:0

VELCMP

Velocity compare value.

0x0

34.6.2.13 QEI Digital filter on phase A input register
This register contains the sampling count for the digital filter. A sampling count of zero
bypasses the filter.
Table 842. QEI Digital filter on phase A input register (FILTERPHA - 0x400C 603C) bit
description
Bit

Symbol

Description

Reset
value

31:0

FILTA

Digital filter sampling delay

0x0

34.6.2.14 QEI Digital filter on phase B input register
This register contains the sampling count for the digital filter. A sampling count of zero
bypasses the filter.
Table 843. QEI Digital filter on phase B input register (FILTERPHB - 0x400C 6040) bit
description
Bit

Symbol

Description

Reset
value

31:0

FILTB

Digital filter sampling delay

0x0

34.6.2.15 QEI Digital filter on index input register
This register contains the sampling count for the digital filter. A sampling count of zero
bypasses the filter.
Table 844. QEI Digital filter on index input register (FILTERINX - 0x400C 6044) bit
description

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Bit

Symbol

Description

Reset
value

31:0

FITLINX

Digital filter sampling delay

0x0

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34.6.2.16 QEI Index acceptance window register
This register contains the width of the index acceptance window, when the index and the
phase / clock edges fall nearly together. If the activating phase / clock edge falls before
the Index, but within the window, the (re)calibration will be activated on that clock/phase
edge.
Table 845. QEI Index acceptance window register (WINDOW - 0x400C 6048) bit description
Bit

Symbol

Description

Reset
value

31:0

WINDOW

Index acceptance window width

0x0

34.6.2.17 QEI Index Compare register 1
This register contains an index compare value. This value is compared against the current
value of the index count register. Interrupts can be enabled to interrupt when the compare
value is less than, equal to, or greater than the current value of the index count register.
Table 846. QEI Index Compare register 1 (INXCMP1 - address 0x400C 604C) bit description
Bit

Symbol

Description

Reset value

31:0

ICMP1

Index compare value 1.

0xFFFF FFFF

34.6.2.18 QEI Index Compare register 2
This register contains an index compare value. This value is compared against the current
value of the index count register. Interrupts can be enabled to interrupt when the compare
value is less than, equal to, or greater than the current value of the index count register.
Table 847. QEI Index Compare register 2 (INXCMP2 - address 0x400C 6050) bit description

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Bit

Symbol

Description

Reset value

31:0

ICMP2

Index compare value 2.

0xFFFF FFFF

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34.6.3 Interrupt registers
34.6.3.1 QEI Interrupt Enable Clear register
Writing a 1 to a bit in this register clears the corresponding bit in the QEI Interrupt Enable
register (QEIIE).
Table 848: QEI Interrupt Enable Clear register (IEC - address 0x400C 6FD8) bit description
Bit

Symbol

Description

Reset
value

0

INX_EN

Indicates that an index pulse was detected.

0

1

TIM_EN

Indicates that a velocity timer overflow occurred

0

2

VELC_EN

Indicates that captured velocity is less than compare velocity.

0

3

DIR_EN

Indicates that a change of direction was detected.

0

4

ERR_EN

Indicates that an encoder phase error was detected.

0

5

ENCLK_EN

Indicates that and encoder clock pulse was detected.

0

6

POS0_INT

Indicates that the position 0 compare value is equal to the current position.

0

7

POS1_INT

Indicates that the position 1compare value is equal to the current position.

0

8

POS2_INT

Indicates that the position 2 compare value is equal to the current position.

0

9

REV0_INT

Indicates that the index 0 compare value is equal to the current index count.

0

10

POS0REV_INT Combined position 0 and revolution count interrupt. Set when both the POS0_INT bit is set 0
and the REV0_Int is set.

11

POS1REV_INT Combined position 1 and revolution count interrupt. Set when both the POS1_INT bit is set 0
and the REV1_INT is set.

12

POS2REV_INT Combined position 2 and revolution count interrupt. Set when both the POS2_INT bit is set 0
and the REV2_INT is set.

13

REV1_INT

Indicates that the index 1 compare value is equal to the current index count.

0

14

REV2_INT

Indicates that the index 2 compare value is equal to the current index count.

0

15

MAXPOS_INT

Indicates that the current position count goes through the MAXPOS value to zero in
forward direction, or through zero to MAXPOS in backward direction.

0

Reserved

0

31:16 -

34.6.3.2 QEI Interrupt Enable Set register
Writing a 1 to a bit in this register sets the corresponding bit in the QEI Interrupt Enable
register (QEIIE).
Table 849: QEI Interrupt Enable Set register (IES - address 0x400C 6FDC) bit description
Bit

Symbol

Description

Reset
value

0

INX_EN

Indicates that an index pulse was detected.

0

1

TIM_EN

Indicates that a velocity timer overflow occurred

0

2

VELC_EN

Indicates that captured velocity is less than compare velocity.

0

3

DIR_EN

Indicates that a change of direction was detected.

0

4

ERR_EN

Indicates that an encoder phase error was detected.

0

5

ENCLK_EN

Indicates that and encoder clock pulse was detected.

0

6

POS0_INT

Indicates that the position 0 compare value is equal to the current position.

0

7

POS1_INT

Indicates that the position 1 compare value is equal to the current position.

0

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Table 849: QEI Interrupt Enable Set register (IES - address 0x400C 6FDC) bit description
Bit

Symbol

Description

Reset
value

8

POS2_INT

Indicates that the position 2 compare value is equal to the current position.

0

9

REV0_INT

Indicates that the index compare value is equal to the current index count.

0

10

POS0REV_INT

Combined position 0 and revolution count interrupt. Set when both the POS0_INT bit is
set and the REV0_INT is set.

0

11

POS1REV_INT

Combined position 1 and revolution count interrupt. Set when both the POS1_INT bit is
set and the REV1_INT is set.

0

12

POS2REV_INT

Combined position 2 and revolution count interrupt. Set when both the POS2_INT bit is
set and the REV2_INT is set.

0

13

REV1_INT

Indicates that the index 1 compare value is equal to the current index count.

0

14

REV2_INT

Indicates that the index 2 compare value is equal to the current index count.

0

15

MAXPOS_INT

Indicates that the current position count goes through the MAXPOS value to zero in
forward direction, or through zero to MAXPOS in backward direction.

0

31:16

-

Reserved

0

34.6.3.3 QEI Interrupt Status register
This register provides the status of the encoder interface and the current set of interrupt
sources that are asserted to the controller. Bits set to 1 indicate the latched events that
have occurred; a zero bit indicates that the event in question has not occurred. Writing a 0
to a bit position clears the corresponding interrupt.
Table 850: QEI Interrupt Status register (INTSTAT - address 0x400C 6FE0) bit description
Bit

Symbol

Description

Reset
value

0

INX_INT

Indicates that an index pulse was detected.

0

1

TIM_INT

Indicates that a velocity timer overflow occurred

0

2

VELC_INT

Indicates that captured velocity is less than compare velocity.

0

3

DIR_INT

Indicates that a change of direction was detected.

0

4

ERR_INT

Indicates that an encoder phase error was detected.

0

5

ENCLK_INT

Indicates that and encoder clock pulse was detected.

0

6

POS0_INT

Indicates that the position 0 compare value is equal to the current position.

0

7

POS1_INT

Indicates that the position 1compare value is equal to the current position.

0

8

POS2_INT

Indicates that the position 2 compare value is equal to the current position.

0

9

REV0_INT

Indicates that the index compare value is equal to the current index count.

0

10

POS0REV_INT Combined position 0 and revolution count interrupt. Set when both the POS0_INT bit is
set and the REV0_INT is set.

0

11

POS1REV_INT Combined position 1 and revolution count interrupt. Set when both the POS1_INT bit is
set and the REV1_INT is set.

0

12

POS2REV_INT Combined position 2 and revolution count interrupt. Set when both the POS2_INT bit is
set and the REV2_INT is set.

0

13

REV1_INT

Indicates that the index 1 compare value is equal to the current index count.

0

14

REV2_INT

Indicates that the index 2 compare value is equal to the current index count.

0

15

MAXPOS_INT

Indicates that the current position count goes through the MAXPOS value to zero in
forward direction, or through zero to MAXPOS in backward direction.

0

31:16

-

Reserved

0

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34.6.3.4 QEI Interrupt Enable register
This register enables interrupt sources. Bits set to 1 enable the corresponding interrupt; a
0 bit disables the corresponding interrupt.
Table 851: QEI Interrupt Enable register (IE - address 0x400C 6FE4) bit description
Bit

Symbol

Description

Reset
value

0

INX_INT

Indicates that an index pulse was detected.

0

1

TIM_INT

Indicates that a velocity timer overflow occurred

0

2

VELC_INT

Indicates that captured velocity is less than compare velocity.

0

3

DIR_INT

Indicates that a change of direction was detected.

0

4

ERR_INT

Indicates that an encoder phase error was detected.

0

5

ENCLK_INT

Indicates that and encoder clock pulse was detected.

0

6

POS0_INT

Indicates that the position 0 compare value is equal to the current position.

0

7

POS1_INT

Indicates that the position 1compare value is equal to the current position.

0

8

POS2_INT

Indicates that the position 2 compare value is equal to the current position.

0

9

REV0_INT

Indicates that the index compare value is equal to the current index count.

0

10

POS0REV_INT

Combined position 0 and revolution count interrupt. Set when both the POS0_INT bit is
set and the REV0_INT is set.

0

11

POS1REV_INT

Combined position 1 and revolution count interrupt. Set when both the POS1_INT bit is
set and the REV1_INT is set.

0

12

POS2REV_INT

Combined position 2 and revolution count interrupt. Set when both the POS2_INT bit is
set and the REV2_INT is set.

0

13

REV1_INT

Indicates that the index 1 compare value is equal to the current index count.

0

14

REV2_INT

Indicates that the index 2 compare value is equal to the current index count.

0

15

MAXPOS_INT

Indicates that the current position count goes through the MAXPOS value to zero in
forward direction, or through zero to MAXPOS in backward direction.

0

31:16

-

Reserved

0

34.6.3.5 QEI Interrupt Status Clear register
Writing a 1 to a bit in this register clears the corresponding bit in the QEI Interrupt Status
register (QEISTAT).
Table 852: QEI Interrupt Status Clear register (CLR - 0x400C 6FE8) bit description
Bit

Symbol

Description

Reset
value

0
1

INX_INT

Indicates that an index pulse was detected.

0

TIM_INT

Indicates that a velocity timer overflow occurred

0

2

VELC_INT

Indicates that captured velocity is less than compare velocity.

0

3

DIR_INT

Indicates that a change of direction was detected.

0

4

ERR_INT

Indicates that an encoder phase error was detected.

0

5

ENCLK_INT

Indicates that and encoder clock pulse was detected.

0

6

POS0_INT

Indicates that the position 0 compare value is equal to the current position.

0

7

POS1_INT

Indicates that the position 1compare value is equal to the current position.

0

8

POS2_INT

Indicates that the position 2 compare value is equal to the current position.

0

9

REV0_INT

Indicates that the index compare value is equal to the current index count.

0

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Table 852: QEI Interrupt Status Clear register (CLR - 0x400C 6FE8) bit description
Bit

Symbol

Description

Reset
value

10

POS0REV_INT Combined position 0 and revolution count interrupt. Set when both the POS0_INT bit is
set and the REV0_INT is set.

0

11

POS1REV_INT Combined position 1 and revolution count interrupt. Set when both the POS1_INT bit is
set and the REV1_INT is set.

0

12

POS2REV_INT Combined position 2 and revolution count interrupt. Set when both the POS2_INT bit is
set and the REV2_INT is set.

0

13

REV1_INT

Indicates that the index 1 compare value is equal to the current index count.

0

14

REV2_INT

Indicates that the index 2 compare value is equal to the current index count.

0

15

MAXPOS_INT

Indicates that the current position count goes through the MAXPOS value to zero in
forward direction, or through zero to MAXPOS in backward direction.

31:16

-

Reserved

0

34.6.3.6 QEI Interrupt Status Set register
Writing a one to a bit in this register sets the corresponding bit in the QEI Interrupt Status
register (STAT).
Table 853: QEI Interrupt Status Set register (SET - address 0x400C 6FEC) bit description
Bit

Symbol

Description

Reset
value

0

INX_INT

Indicates that an index pulse was detected.

0

1

TIM_INT

Indicates that a velocity timer overflow occurred

0

2

VELC_INT

Indicates that captured velocity is less than compare velocity.

0

3

DIR_INT

Indicates that a change of direction was detected.

0

4

ERR_INT

Indicates that an encoder phase error was detected.

0

5

ENCLK_INT

Indicates that and encoder clock pulse was detected.

6

POS0_INT

Indicates that the position 0 compare value is equal to the current position.

0

7

POS1_INT

Indicates that the position 1compare value is equal to the current position.

0

8

POS2_INT

Indicates that the position 2 compare value is equal to the current position.

0

9

REV0_INT

Indicates that the index compare value is equal to the current index count.

0

10

POS0REV_INT Combined position 0 and revolution count interrupt. Set when both the POS0_INT bit is
set and the REV0_INT is set.

0

11

POS1REV_INT Combined position 1 and revolution count interrupt. Set when both the POS1_INT bit is
set and the REV1_INT is set.

0

12

POS2REV_INT Combined position 2 and revolution count interrupt. Set when both the POS2_INT bit is
set and the REV2_INT is set.

0

13

REV1_INT

Indicates that the index 1 compare value is equal to the current index count.

0

14

REV2_INT

Indicates that the index 2 compare value is equal to the current index count.

0

15

MAXPOS_INT

Indicates that the current position count goes through the MAXPOS value to zero in
forward direction, or through zero to MAXPOS in backward direction.

0

31:16

-

Reserved

0

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Chapter 34: LPC43xx/LPC43Sxx Quadrature Encoder Interface (QEI)

34.7 Functional description
The QEI module interprets the two-bit gray code produced by a quadrature encoder wheel
to integrate position over time and determine direction of rotation. In addition, it can
capture the velocity of the encoder wheel.

34.7.1 Input signals
The QEI module supports two modes of signal operation: quadrature phase mode and
clock/direction mode. In quadrature phase mode, the encoder produces two clocks that
are 90 degrees out of phase; the edge relationship is used to determine the direction of
rotation. In clock/direction mode, the encoder produces a clock signal to indicate steps
and a direction signal to indicate the direction of rotation.).
This mode is determined by the SigMode bit of the QEI Control (CON) register (See
Table 827). When the SigMode bit = 1, the quadrature decoder is bypassed and the PhA
pin functions as the direction signal and PhB pin functions as the clock signal for the
counters, etc. When the SigMode bit = 0, the PhA pin and PhB pins are decoded by the
quadrature decoder. In this mode the quadrature decoder produces the direction and
clock signals for the counters, etc. In both modes the direction signal is subject to the
effects of the direction invert (DIRINV) bit.

34.7.1.1 Quadrature input signals
When edges on PhA lead edges on PhB, the position counter is incremented. When
edges on PhB lead edges on PhA, the position counter is decremented. When a rising
and falling edge pair is seen on one of the phases without any edges on the other, the
direction of rotation has changed.
Table 854. Encoder states
Phase A

Phase B

state

1

0

1

1

1

2

0

1

3

0

0

4

Table 855. Encoder state transitions[1]
from state

to state

Direction

1

2

positive

2

3

3

4

4

1

4

3

3

2

2

1

1

4

[1]

negative

All other state transitions are illegal and should set the ERR bit.

Interchanging of the PhA and PhB input signals are compensated by complementing the
DIR bit. When set = 1, the direction inversion bit (DIRINV) complements the DIR bit.
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Chapter 34: LPC43xx/LPC43Sxx Quadrature Encoder Interface (QEI)

Table 856. Encoder direction
DIR bit

DIRINV bit

direction

0

0

forward

1

0

reverse

0

1

reverse

1

1

forward

Figure 119 shows how quadrature encoder signals equate to direction and count.

PhA
PhB
direction
position

-1 -1 -1 -1 -1 -1 -1 -1 -1

+1 +1 +1 +1 +1 +1 +1 +1

-1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1

Fig 119. Quadrature Encoder Basic Operation

34.7.1.2 Digital input filtering
All three encoder inputs (PhA, PhB, and index) require digital filtering. The number of
sample clocks is user programmable from 1 to 4,294,967,295 (0xFFFF FFFF). In order for
a transition to be accepted, the input signal must remain in new state for the programmed
number of sample clocks.

34.7.2 Position capture
The capture mode for the position integrator can be set to update the position counter on
every edge of the PhA signal or to update on every edge of both PhA and PhB. Updating
the position counter on every PhA and PhB provides more positional resolution at the cost
of less range in the positional counter.
The position integrator and velocity capture can be independently enabled. Alternatively,
the phase signals can be interpreted as a clock and direction signal as output by some
encoders.
The position counter is automatically reset on one of three conditions. Incrementing past
the maximum position value (MAXPOS) will reset the position counter to zero. If the reset
on index bit (RESPI) is set, sensing the index pulse for the first time will once reset the
position counter to zero after the next positional increase (calibrate). If the continuously
reset on index bit (CRESPI) is set, sensing the index pulse will continuously reset the
position counter to zero after the next positional increase (recalibrate).

34.7.3 Velocity capture
The velocity capture has a programmable timer and a capture register. It counts the
number of phase edges (using the same configuration as for the position integrator) in a
given time period. When the velocity timer (TIME) reaches zero, the contents of the
velocity counter (VEL) are transferred to the capture (CAP) register. The velocity counter
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Chapter 34: LPC43xx/LPC43Sxx Quadrature Encoder Interface (QEI)

is then cleared. The velocity timer is loaded with the contents of the velocity reload
register (LOAD). Finally, the velocity interrupt (TIM_Int) is asserted. The number of edges
counted in a given time period is directly proportional to the velocity of the encoder.
Setting the reset velocity bit (RESV) will clear the velocity counter, reset the velocity
capture register to 0xFFFF FFFF, and load the velocity timer with the contents of the
velocity reload register (LOAD).
The following equation converts the velocity counter value into an RPM value:
RPM = (PCLK  Speed  60) / Load  PPR  Edges)
where:

• PCLK is the QEI controller clock.
• PPR is the number of pulses per revolution of the physical encoder.
• Edges is 2 or 4, based on the capture mode set in the CON register (2 for CapMode
set to 0 and 4 for CapMode set to 1)
For example, consider a motor running at 600 rpm. A 2048 pulse per revolution
quadrature encoder is attached to the motor, producing 8192 phase edges per revolution.
With clocking on both PhA and PhB edges, this results in 81,920 pulses per second (the
motor turns 10 times per second). If the timer were clocked at 10,000 Hz, and the load
value was 2,500 (¼ of a second), it would count 20,480 pulses per update. Using the
above equation:
RPM = (10000  20480  60) / (2500  2048  4) = 600 RPM
Now, consider that the motor is sped up to 3000 RPM. This results in 409,600 pulses per
second, or 102,400 every ¼ of a second. Again, the above equation gives:
RPM = (10000  102400  60) / (2500  2048  4) = 3000 RPM

34.7.4 Velocity compare
In addition to velocity capture, the velocity measurement system includes a
programmable velocity compare register. After every velocity capture event the contents
of the velocity capture register (CAP) is compared with the contents of the velocity
compare register (VELCOMP). If the captured velocity is less than the compare value an
interrupt is asserted provided that the velocity compare interrupt enable bit is set. This can
be used to determine if a motor shaft is either stalled or moving too slow.

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Chapter 35: LPC43xx/LPC43Sxx Repetitive Interrupt Timer
(RIT)
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User manual

35.1 How to read this chapter
The RIT is available on all LPC43xx/LPC43Sxx parts.

35.2 Basic configuration
The RIT is configured as follows:

• See Table 857 for clocking and power control.
• The RIT is reset by the RITIMER_RST (reset #36).
• The RIT interrupt is connected to slot # 11 in the NVIC.
Table 857. RIT clocking and power control
Base clock

Clock to the RI timer register interface and BASE_M4_CLK
RI timer peripheral clock (PCLK).

Branch clock

Operating
frequency

CLK_M4_RITIMER

up to
204 MHz

35.3 Features
• 32-bit counter running from BASE_M4_CLK. Counter can be free-running, or be reset
by a generated interrupt.

• 32-bit compare value.
• 32-bit compare mask. An interrupt is generated when the counter value equals the
compare value after masking. This allows for combinations not possible with a simple
compare.

35.4 General description
The Repetitive Interrupt Timer (RIT) provides a versatile means of generating interrupts at
specified time intervals, without using a standard timer. It is intended for repeating
interrupts that aren’t related to Operating System interrupts. The RIT could also be used
as an alternative to the Cortex-M4 System Tick Timer if there are different system
requirements.

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Chapter 35: LPC43xx/LPC43Sxx Repetitive Interrupt Timer (RIT)

RESET
CNT_ENA

RESET

ENA
CLR
32-bit COUNTER

SET
ENABLE_TIMER
3
PBUS
ENABLE_BREAK

2

32

BREAK
ENABLE_CLK

PBUS

EQ
COMPARATOR
EQ

bit 32
compare

CLR
RESET

bit 0
compare

32 X

SET_INT

..
.

S
0
PBUS
write '1' to
clear

32

INTR

C
CLR

RESET
CTRL
register

32 X
bit 31
(MASK)

RESET
SET

PBUS

bit 0
(MASK)

CLR

MASK
register

COMPARE
register

PBUS

PBUS

Fig 120. Repetitive Interrupt Timer (RIT) block diagram

35.5 Register description
Table 858. Register overview: Repetitive Interrupt Timer (RIT) (base address 0x400C 0000)
Name

Access

Address

Description

Reset value[1] Reference

COMPVAL

R/W

0x000

Compare register

0xFFFF FFFF Table 859

MASK

R/W

0x004

Mask register. This register holds the 32-bit mask value.
A 1 written to any bit will force the compare to be true on
the corresponding bit of the counter and compare
register.

0

Table 860

CTRL

R/W

0x008

Control register.

0xC

Table 861

COUNTER R/W

0x00C

32-bit counter

0

Table 862

[1]

Reset Value reflects the data stored in used bits only. It does not include content of reserved bits.

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Chapter 35: LPC43xx/LPC43Sxx Repetitive Interrupt Timer (RIT)

35.5.1 RI Compare Value register
Table 859. RI Compare Value register (COMPVAL - address 0x400C 0000) bit description
Bit

Symbol

Description

Reset value

31:0

RICOMP

Compare register. Holds the compare value which is
compared to the counter.

0xFFFF FFFF

35.5.2 RI Mask register
Table 860. RI Mask register (MASK - address 0x400C 0004) bit description
Bit

Symbol

Description

Reset
value

31:0

RIMASK

Mask register. This register holds the 32-bit mask value. A one written 0
to any bit overrides the result of the comparison for the corresponding
bit of the counter and compare register (causes the comparison of the
register bits to be always true).

35.5.3 RI Control register
Table 861. RI Control register (CTRL - address 0x400C 0008) bit description
Bit

Symbol

0

RITINT

Value

1

Description

Reset
value

Interrupt flag

0

This bit is set to 1 by hardware whenever the counter value
equals the masked compare value specified by the contents
of COMPVAL and MASK registers.
Writing a 1 to this bit will clear it to 0. Writing a 0 has no
effect.

1

2

3

0

The counter value does not equal the masked compare
value.

1

The timer will be cleared to 0 whenever the counter value
0
equals the masked compare value specified by the contents
of COMPVAL and MASK registers. This will occur on the
same clock that sets the interrupt flag.

0

The timer will not be cleared to 0.

RITENCLR

Timer enable clear

RITENBR

Timer enable for debug

1

1

The timer is halted when the processor is halted for
debugging.

0

Debug has no effect on the timer operation.

RITEN

Timer enable.
1

1

Timer enabled.
Remark: This can be overruled by a debug halt if enabled in
bit 2.

31:4

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-

0

Timer disabled.

-

Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.

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Chapter 35: LPC43xx/LPC43Sxx Repetitive Interrupt Timer (RIT)

35.5.4 RI Counter register
Table 862. RI Counter register (COUNTER - address 0x400C 000C) bit description
Bit

Symbol

Description

Reset
value

31:0

RICOUNTER

32-bit up counter. Counts continuously unless RITEN bit in CTRL
register is cleared or debug mode is entered (if enabled by the
RITNEBR bit in CTRL). Can be loaded to any value in software.

0

35.6 RI timer operation
Following reset, the counter begins counting up from 0x0000 0000. Whenever the counter
value equals the value programmed into the COMPVAL register the interrupt flag will be
set. Any bit or combination of bits can be removed from this comparison (i.e. forced to
compare) by writing a ‘1’ to the corresponding bit(s) in the MASK register. If the enable_clr
bit is low (default state), a valid comparison ONLY causes the interrupt flag to be set. It
has no effect on the count sequence. Counting continues as usual. When the counter
reaches 0xFFFFFFFF it rolls-over to 0x000 00000 on the next clock and continues
counting. If the enable_clr bit is set to ‘1’ a valid comparison will also cause the counter to
be reset to zero. Counting will resume from there on the next clock edge.
Counting can be halted in software by writing a ‘0’ to the RITEN bit. Counting will also be
halted when the processor is halted for debugging provided the RITENBR bit is set. Both
the RITEN and RITENBR bits are set on reset.
The interrupt flag can be cleared in software by writing a ‘1’ to the RITINT bit.
Software can load the counter to any value at any time by writing to COUNTER.
The counter (COUNTER), COMPVAL register, MASK register and CTRL register can all
be read by software at any time.

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Chapter 36: LPC43xx/LPC43Sxx Alarm timer
Rev. 2.4 — 22 August 2018

User manual

36.1 How to read this chapter
The Alarm timer is available on all LPC43xx/LPC43Sxx parts.

36.2 Basic configuration
The Alarm timer is configured as follows:

• See Table 863 for clocking and power control. The 32 kHz output of the 32 kHz
oscillator must be enabled in the CREG0 register in the CREG block (see Table 96).

• The Alarm timer interrupt is connected to slot # 4 in the Event router.
Remark: Only write to the Alarm timer registers while the 32 kHz oscillator is running.
Repeated writes to the Alarm timer registers without the 32 kHz clock can stall the CPU.
To confirm that the 32 kHz clock is running, read the Alarm timer counter register
(DOWNCOUNTER, see Table 865), which counts down from a preset value using the
1024 Hz signal derived from the 32 kHz oscillator.
Table 863. Alarm timer clocking and power control
Base clock

Branch clock

Operating
frequency

Clock to alarm timer register interface

BASE_M4_CLK

CLK_M4_BUS up to 204 MHz

32 kHz crystal oscillator output for the
counter/timer clock

-

-

1024 Hz (fixed
frequency)

36.3 General description
The alarm timer is a 16-bit timer and counts down from a preset value. The counter
triggers a status bit when it reaches 0x00 and asserts an interrupt if enabled.
The alarm timer operates in the RTC power domain. It consists of a 16-bit counter
(DOWNCOUNTER) running at a 1024 Hz clock. The 1024 Hz clock is derived from the
32 kHz crystal clock. The alarm timer is inactive when this clock is not active.
The alarm timer counts down from an initial value PRESET. When it reaches 0x0 and the
interrupt is enabled (via SET_EN), bit STATUS is triggered. The counter continues
counting down starting from PRESET. The countdown period is PRESET + 1 input clock
cycles.
STATUS is propagated to the interrupt output. The interrupt is connected to the Event
router and can be used to wake up the device from a low power mode.

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Chapter 36: LPC43xx/LPC43Sxx Alarm timer

36.4 Register description
Table 864. Register overview: Alarm timer (base address 0x4004 0000)
Name

Access

Address
offset

Description

Reset
value

Reference

DOWNCOUNTER

R/W

0x000

Downcounter register

0x000

Table 865

PRESET

R/W

0x004

Preset value register

0x000

Table 866

-

-

0x008 0xFD4

Reserved

-

-

CLR_EN

W

0xFD8

Interrupt clear enable register

0x0

Table 867

SET_EN

W

0xFDC

Interrupt set enable register

0x0

Table 868

STATUS

R

0xFE0

Status register

0x0

Table 869

ENABLE

R

0xFE4

Enable register

0x0

Table 870

CLR_STAT

W

0xFE8

Clear register

0x0

Table 871

SET_STAT

W

0xFEC

Set register

0x0

Table 872

36.4.1 Downcounter register
Table 865. Downcounter register (DOWNCOUNTER - 0x4004 0000) bit description
Bit

Symbol

15:0

CVAL

Description

Reset value

When equal to zero an interrupt is raised.

0x0

When equal to zero PRESET is loaded and counting
continues.
31:16

-

Reserved.

-

36.4.2 Preset value register
Table 866. Preset value register (PRESET - 0x4004 0004) bit description
Bit

Symbol

Description

Reset value

15:0

PRESETVAL

Value loaded in DOWNCOUNTER when
0
DOWNCOUNTER equals zero. Example: PRESETVAL = 0
causes an interrupt every 1/1024 s, PRESETVAL = 1
causes an interrupt every 2/1024 s, etc.

31:16

-

Reserved.

-

36.4.3 Interrupt clear enable register
Table 867. Interrupt clear enable register (CLR_EN - 0x4004 0FD8) bit description

UM10503

User manual

Bit

Symbol

Description

Reset value

0

CLR_EN

Writing a 1 to this bit clears the interrupt enable bit in the
ENABLE register.

0

31:1

-

Reserved.

-

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Chapter 36: LPC43xx/LPC43Sxx Alarm timer

36.4.4 Interrupt set enable register
Table 868. Interrupt set enable register (SET_EN - 0x4004 0FDC) bit description
Bit

Symbol

Description

Reset value

0

SET_EN

Writing a 1 to this bit sets the interrupt enable bit in the
ENABLE register.

0

31:1

-

Reserved.

-

36.4.5 Interrupt status register
Table 869. Interrupt status register (STATUS - 0x4004 0FE0) bit description
Bit

Symbol

Description

Reset value

0

STAT

A 1 in this bit shows that the STATUS interrupt has been
raised.

0

31:1

-

Reserved.

-

36.4.6 Interrupt enable register
Table 870. Interrupt enable register (ENABLE - 0x4004 0FE4) bit description
Bit

Symbol

Description

Reset value

0

EN

A 1 in this bit shows that the STATUS interrupt has been
enabled and that the STATUS interrupt request signal is
asserted when STAT = 1 in the STATUS register.

0

31:1

-

Reserved.

-

36.4.7 Clear status register
Table 871. Interrupt clear status register (CLR_STAT - 0x4004 0FE8) bit description
Bit

Symbol

Description

Reset value

0

CSTAT

Writing a 1 to this bit clears the STATUS interrupt bit in the
STATUS register.

0

31:1

-

Reserved.

-

36.4.8 Set status register
Table 872. Interrupt set status register (SET_STAT - 0x4004 0FEC) bit description

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User manual

Bit

Symbol

Description

Reset value

0

SSTAT

Writing a 1 to this bit sets the STATUS interrupt bit in the
STATUS register.

0

31:1

-

Reserved.

-

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Chapter 37: LPC43xx/LPC43Sxx Real-Time Clock (RTC)
Rev. 2.4 — 22 August 2018

User manual

37.1 How to read this chapter
The RTC is available on all LPC43xx/LPC43Sxx parts.

37.2 Basic configuration
The RTC is configured as follows:

• See Table 873 for clocking and power control. The 1 kHz output of the 32 kHz
oscillator must be enabled in the CREG0 register in the CREG block (see Table 96).

• The RTC interrupt is connected to slot # 5 in the Event router slot #47 in the NVIC.
• The functionality of the RTC_ALARM pin is controlled by the CREG0 register (see
Table 96). By default, the RTC Alarm interrupt can be monitored on this pin.
Remark: After initializing the 32 kHz oscillator, wait for 2 sec before writing to the RTC
registers.
Remark: Only write to the RTC registers while the 32 kHz oscillator is running. Repeated
writes to the RTC registers without the 32 kHz clock can stall the CPU. To confirm that the
32 kHz clock is running, read the Alarm timer counter register (DOWNCOUNTER, see
Table 865), which counts down from a preset value using the 1024 Hz clock signal derived
from the 32 kHz oscillator.
Table 873. RTC clocking and power control
Base clock

Branch clock

Operating frequency

Clock to the RTC register
interface

BASE_M4_CLK

CLK_M4_BUS up to 204 MHz

32 kHz crystal oscillator output
for the RTC counter/timer clock

-

-

1024 Hz (fixed frequency);
the RTC receives an
internal 1 Hz clock.

37.3 Features
• Measures the passage of time to maintain a calendar and clock. Provides seconds,
minutes, hours, day of month, month, year, day of week, and day of year.

• Ultra-low power design to support battery powered systems. Uses power from the
CPU power supply when it is present.

•
•
•
•

Dedicated battery power supply pin.
RTC power supply is isolated from the rest of the chip.
Calibration counter allows adjustment to better than 1 sec/day with 1 sec resolution.
Periodic interrupts can be generated from increments of any field of the time registers
and selected fractional second values.

• An Alarm interrupt can be generated for a specific date/time.

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Chapter 37: LPC43xx/LPC43Sxx Real-Time Clock (RTC)

37.4 General description
The Real Time Clock (RTC) is a set of counters for measuring time when system power is
on, and optionally when it is off. It uses very little power when its registers are not being
accessed by the CPU, especially in reduced power modes. On the LPC43xx, the RTC is
clocked by a separate 32 kHz oscillator that produces a 1 Hz internal time reference. The
RTC is powered by its own power supply pin, VBAT.

Alarm Registers
minute
hour

second

day

month

year

month

year

alarm compare
1 Hz
Clock
second
LSB
out

minute

LSB
set

sign
bit

Time Registers

day
day of
week

Counter
Increment
Interrupts

day of
year
Calibration
calibration compare register

match
calibration
control
logic

hour

Alarm out
and Alarm
Interrupts

calibration compare
counter
reset
calibration counter

Fig 121. RTC functional block diagram

37.5 Pin description
Table 874. RTC pin description

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User manual

Pin function

Direction

Description

RTC_ALARM

O

RTC controlled output. The pin goes HIGH when an RTC alarm is
generated. CREG0 bits ALARMCTRL must be set to 0 (see
Table 96).

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Chapter 37: LPC43xx/LPC43Sxx Real-Time Clock (RTC)

37.6 Register description
Table 875. Register overview: RTC (base address 0x4004 6000)
Name

Access Address Description
offset

Reset
value

Reference

ILR

W

0x000

Interrupt Location Register

0x0

Table 877

-

-

0x004

Reserved

0x00

-

CCR

R/W

0x008

Clock Control Register

0x00

Table 878

CIIR

R/W

0x00C

Counter Increment Interrupt Register 0x00

Table 879

AMR

R/W

0x010

Alarm Mask Register

-[1]

CTIME0

R

0x014

Consolidated Time Register 0

-[1]

Table 881

Consolidated Time Register 1

-[1]

Table 882

Consolidated Time Register 2

-[1]

Table 883
Table 886

CTIME1
CTIME2

R

0x018

R

0x01C

Table 880

SEC

R/W

0x020

Seconds Register

-[1]

MIN

R/W

0x024

Minutes Register

-[1]

Table 887

Hours Register

-[1]

Table 888

Day of Month Register

-[1]

Table 889
Table 890

HRS
DOM

R/W

0x028

R/W

0x02C

DOW

R/W

0x030

Day of Week Register

-[1]

DOY

R/W

0x034

Day of Year Register

-[1]

Table 891

Months Register

-[1]

Table 892

Years Register

-[1]

Table 893

Calibration Value Register

-[1]

Table 894

-

-

Alarm Seconds Register

-[1]

Table 896
Table 897

MONTH
YEAR

R/W

0x038

R/W

0x03C

CALIBRATION

R/W

0x040

-

-

0x044 0x05C

ASEC

R/W

0x060

AMIN

R/W

0x064

Alarm Minutes Register

-[1]

AHRS

R/W

0x068

Alarm Hours Register

-[1]

Table 898

Alarm Day of Month Register

-[1]

Table 899

Alarm Day of Week Register

-[1]

Table 900
Table 901

ADOM
ADOW

R/W

0x6C

R/W

0x070

ADOY

R/W

0x074

Alarm Day of Year Register

-[1]

AMON

R/W

0x078

Alarm Month Register

-[1]

Table 902

Alarm Year Register

-[1]

Table 903

AYRS
[1]

R/W

0x07C

This register value is not changed by reset.

In addition to the RTC registers, 64 general purpose registers are available to store data
when the main power supply is switched off. The general purpose registers reside in the
RTC power domain and can be battery powered.
Table 876. Register overview: REGFILE (base address 0x4004 1000)
Name

Access

Address
offset

Description

Reset
Value

REGFILE0

R/W

0x000

General purpose storage register

0x0

R/W

0x0FC

General purpose storage register

0x0

to
REGFILE63

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Chapter 37: LPC43xx/LPC43Sxx Real-Time Clock (RTC)

37.6.1 Interrupt Location Register
The Interrupt Location Register is a 2-bit register that specifies which blocks are
generating an interrupt. Writing a one to the appropriate bit clears the corresponding
interrupt. Writing a zero has no effect. This allows the programmer to read this register
and write back the same value to clear only the interrupt that is detected by the read.
Table 877. Interrupt Location Register (ILR - address 0x4004 6000) bit description
Bit

Symbol

Description

Reset
value

0

RTCCIF

When one, the Counter Increment Interrupt block generated an
0
interrupt. Writing a one to this bit location clears the counter increment
interrupt.

1

RTCALF

When one, the alarm registers generated an interrupt. Writing a one to 0
this bit location clears the alarm interrupt.

31:2

-

Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.

NA

37.6.2 Clock Control Register
The clock register is a 4-bit register that controls the operation of the clock divide circuit.
Bits 0, 1, and 4 in this register should be initialized when the RTC is first turned on.
Table 878. Clock Control Register (CCR - address 0x4004 6008) bit description
Bit

Symbol

0

CLKEN

1

-[1]

0

The time counters are disabled so that they may be initialized.

1

The time counters are enabled.

0

No effect.

1

When one, the elements in the internal oscillator divider are
reset, and remain reset until this bit is changed to zero. This is
the divider that generates the 1 Hz clock from the 32.768 kHz
crystal. The state of the divider is not visible to software.

CTC Reset.

0

3:2

-

Internal test mode controls. These bits must be 0 for normal
RTC operation.

-[1]

4

CCALEN

Calibration counter enable.

-[1]

[1]

User manual

Reset
value

Clock Enable.

CTCRST

31:5

UM10503

Value Description

-

0

The calibration counter is enabled and counting, using the
1 Hz clock. When the calibration counter is equal to the value
of the CALIBRATION register, the counter resets and repeats
counting up to the value of the CALIBRATION register. See
Section 37.6.6.2 and Section 37.7.2.

1

The calibration counter is disabled and reset to zero.
Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.

NA

This register value is not changed by reset.

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Chapter 37: LPC43xx/LPC43Sxx Real-Time Clock (RTC)

37.6.3 Counter Increment Interrupt Register
The Counter Increment Interrupt Register (CIIR) gives the ability to generate an interrupt
every time a counter is incremented. This interrupt remains valid until cleared by writing a
1 to bit 0 of the Interrupt Location Register (ILR[0]).
Table 879. Counter Increment Interrupt Register (CIIR - address 0x4004 600C) bit description
Bit

Symbol

Description

Reset
value

0

IMSEC

When 1, an increment of the Second value generates an interrupt.

0

1

IMMIN

When 1, an increment of the Minute value generates an interrupt.

0

2

IMHOUR

When 1, an increment of the Hour value generates an interrupt.

0

3

IMDOM

When 1, an increment of the Day of Month value generates an
interrupt.

0

4

IMDOW

When 1, an increment of the Day of Week value generates an
interrupt.

0

5

IMDOY

When 1, an increment of the Day of Year value generates an interrupt. 0

6

IMMON

When 1, an increment of the Month value generates an interrupt.

0

7

IMYEAR

When 1, an increment of the Year value generates an interrupt.

0

31:8

-

Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.

NA

37.6.4 Alarm Mask Register
The Alarm Mask Register (AMR) allows the user to mask any of the alarm registers.
Table 880 shows the relationship between the bits in the AMR and the alarms. For the
alarm function, every non-masked alarm register must match the corresponding time
counter for an interrupt to be generated. The interrupt is generated only when the counter
comparison first changes from no match to match. The interrupt is removed when a one is
written to the appropriate bit of the Interrupt Location Register (ILR). If all mask bits are
set, then the alarm is disabled.
Table 880. Alarm Mask Register (AMR - address 0x4004 6010) bit description
Bit

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Symbol

Description

Reset
value

0

AMRSEC

When 1, the Second value is not compared for the alarm.

0

1

AMRMIN

When 1, the Minutes value is not compared for the alarm.

0

2

AMRHOUR When 1, the Hour value is not compared for the alarm.

0

3

AMRDOM

When 1, the Day of Month value is not compared for the alarm.

0

4

AMRDOW

When 1, the Day of Week value is not compared for the alarm.

0

5

AMRDOY

When 1, the Day of Year value is not compared for the alarm.

0

6

AMRMON

When 1, the Month value is not compared for the alarm.

0

7

AMRYEAR

When 1, the Year value is not compared for the alarm.

0

31:8

-

Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.

NA

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Chapter 37: LPC43xx/LPC43Sxx Real-Time Clock (RTC)

37.6.5 Consolidated time registers
The values of the Time Counters can optionally be read in a consolidated format which
allows the programmer to read all time counters with only three read operations. The
various registers are packed into 32-bit values as shown in Table 881, Table 882, and
Table 883. The least significant bit of each register is read back at bit 0, 8, 16, or 24.
The Consolidated Time Registers are read-only. To write new values to the Time
Counters, the Time Counter addresses should be used.

37.6.5.1 Consolidated Time Register 0
The Consolidated Time Register 0 contains the low order time values: Seconds, Minutes,
Hours, and Day of Week.
Table 881. Consolidated Time register 0 (CTIME0 - address 0x4004 6014) bit description
Bit

Symbol

Description

Reset
value

5:0

SECONDS

Seconds value in the range of 0 to 59

-[1]

7:6

-

Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.

-

13:8

MINUTES

Minutes value in the range of 0 to 59

-[1]

15:14

-

Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.

-

20:16

HOURS

Hours value in the range of 0 to 23

-[1]

23:21

-

Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.

-[1]

26:24

DOW

Day of week value in the range of 0 to 6

-[1]

31:27

-

Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.

-

[1]

This register value is not changed by reset.

37.6.5.2 Consolidated Time Register 1
The Consolidate Time Register 1 contains the Day of Month, Month, and Year values.
Table 882. Consolidated Time register 1 (CTIME1 - address 0x4004 6018) bit description
Bit

Symbol

Description

Reset
value

4:0

DOM

Day of month value in the range of 1 to 28, 29, 30, or 31
(depending on the month and whether it is a leap year).

-[1]

7:5

-

Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.

-

11:8

MONTH

Month value in the range of 1 to 12.

-[1]

15:12

-

Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.

-

27:16

YEAR

Year value in the range of 0 to 4095.

-[1]

31:28

-

Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.

-

[1]

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This register value is not changed by reset.

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Chapter 37: LPC43xx/LPC43Sxx Real-Time Clock (RTC)

37.6.5.3 Consolidated Time Register 2
The Consolidate Time Register 2 contains just the Day of Year value.
Table 883. Consolidated Time register 2 (CTIME2 - address 0x4004 601C) bit description
Bit

Symbol

Description

Reset
value

11:0

DOY

Day of year value in the range of 1 to 365 (366 for leap years).

-[1]

31:12

-

Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.

-

[1]

This register value is not changed by reset.

37.6.6 Time Counter Group
The time value consists of the eight counters shown in Table 884 and Table 885. These
counters can be read or written at the locations shown in Table 885.
Table 884. Time Counter relationships and values
Counter

Size

Enabled by

Minimum value

Maximum value

Second

6

1 Hz Clock

0

59

Minute

6

Second

0

59

Hour

5

Minute

0

23

Day of Month

5

Hour

1

28, 29, 30 or 31

Day of Week

3

Hour

0

6

Day of Year

9

Hour

1

365 or 366 (for leap year)

Month

4

Day of Month

1

12

Year

12

Month or day of Year

0

4095

Table 885. Time Counter registers
Name

User manual

Description

Access

Address

SEC

6

Seconds value in the range of 0 to 59

R/W

0x4004 6020

MIN

6

Minutes value in the range of 0 to 59

R/W

0x4004 6024

HRS

5

Hours value in the range of 0 to 23

R/W

0x4004 6028

DOM

5

Day of month value in the range of 1 to 28, 29, 30,
or 31 (depending on the month and whether it is a
leap year).[1]

R/W

0x4004 602C

DOW

3

Day of week value in the range of 0 to 6[1]

R/W

0x4004 6030

DOY

9

Day of year value in the range of 1 to 365 (366 for
leap years)[1]

R/W

0x4004 6034

MONTH

4

Month value in the range of 1 to 12

R/W

0x4004 6038

YEAR

12

Year value in the range of 0 to 4095

R/W

0x4004 603C

[1]

UM10503

Size

These values are simply incremented at the appropriate intervals and reset at the defined overflow point.
They are not calculated and must be correctly initialized in order to be meaningful.

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Chapter 37: LPC43xx/LPC43Sxx Real-Time Clock (RTC)

Table 886. Seconds register (SEC - address 0x4004 6020) bit description
Bit

Symbol

Description

Reset
value

5:0

SECONDS

Seconds value in the range of 0 to 59

-[1]

31:6

-

Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.

-

[1]

This register value is not changed by reset.

Table 887. Minutes register (MIN - address 0x4004 6024) bit description
Bit

Symbol

Description

Reset
value

5:0

MINUTES

Minutes value in the range of 0 to 59

-[1]

31:6

-

Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.

-

[1]

This register value is not changed by reset.

Table 888. Hours register (HRS - address 0x4004 6028) bit description
Bit

Symbol

Description

Reset
value

4:0

HOURS

Hours value in the range of 0 to 23

-[1]

31:5

-

Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.

-

[1]

This register value is not changed by reset.

Table 889. Day of month register (DOM - address 0x4004 602C) bit description
Bit

Symbol

Description

Reset
value

4:0

DOM

Day of month value in the range of 1 to 28, 29, 30, or 31
(depending on the month and whether it is a leap year).

-[1]

31:5

-

Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.

-

[1]

This register value is not changed by reset.

Table 890. Day of week register (DOW - address 0x4004 6030) bit description
Bit

Symbol

Description

Reset
value

2:0

DOW

Day of week value in the range of 0 to 6.

-[1]

31:3

-

Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.

-

[1]

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This register value is not changed by reset.

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Chapter 37: LPC43xx/LPC43Sxx Real-Time Clock (RTC)

Table 891. Day of year register (DOY - address 0x4004 6034) bit description
Bit

Symbol

Description

Reset
value

8:0

DOY

Day of year value in the range of 1 to 365 (366 for leap years).

-[1]

31:9

-

Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.

-

[1]

This register value is not changed by reset.

Table 892. Month register (MONTH - address 0x4004 6038) bit description
Bit

Symbol

Description

Reset
value

3:0

MONTH

Month value in the range of 1 to 12.

-[1]

31:4

-

Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.

-

[1]

This register value is not changed by reset.

Table 893. Year register (YEAR - address 0x4004 603C) bit description
Bit

Symbol

Description

Reset
value

11:0

YEAR

Year value in the range of 0 to 4095.

-[1]

31:12

-

Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.

-

[1]

This register value is not changed by reset.

37.6.6.1 Leap year calculation
The RTC does a simple bit comparison to see if the two lowest order bits of the year
counter are zero. If true, then the RTC considers that year a leap year. The RTC considers
all years evenly divisible by 4 as leap years. This algorithm is accurate from the year 1901
through the year 2099, but fails for the year 2100, which is not a leap year. The only effect
of leap year on the RTC is to alter the length of the month of February for the month, day
of month, and year counters.

37.6.6.2 Calibration register
The following register is used to calibrate the time counter. The bits in this register are not
changed by reset.
Table 894. Calibration register (CALIBRATION - address 0x4004 6040) bit description

UM10503

User manual

Bit

Symbol

Value

Description

16:0

CALVAL

-

If enabled, the calibration counter counts up to this value.
-[1]
The maximum value is 131072 corresponding to about 36.4
hours. Calibration is disabled if CALVAL = 0.

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Chapter 37: LPC43xx/LPC43Sxx Real-Time Clock (RTC)

Table 894. Calibration register (CALIBRATION - address 0x4004 6040) bit description
Bit

Symbol

17

CALDIR

31:18
[1]

Value

Description

Reset
value

Calibration direction

-[1]

0

Forward calibration. When CALVAL is equal to the
calibration counter, the RTC timers will jump by 2 seconds.

1

Backward calibration. When CALVAL is equal to the
calibration counter, the RTC timers will stop incrementing for
1 second.

-

Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.

-

This register value is not changed by reset.

37.6.7 Alarm register group
The alarm registers are shown in Table 895. The values in these registers are compared
with the time counters. If all the unmasked (See Section 37.6.4 “Alarm Mask Register” on
page 1093) alarm registers match their corresponding time counters then an interrupt is
generated. The interrupt is cleared when a 1 is written to bit 1 of the Interrupt Location
Register (ILR[1]).
Table 895. Alarm registers
Name

Size

Description

Access

Address

ALSEC

6

Alarm value for Seconds

R/W

0x4004 6060

ALMIN

6

Alarm value for Minutes

R/W

0x4004 6064

ALHRS

5

Alarm value for Hours

R/W

0x4004 6068

ALDOM

5

Alarm value for Day of Month

R/W

0x4004 606C

ALDOW

3

Alarm value for Day of Week

R/W

0x4004 6070

ALDOY

9

Alarm value for Day of Year

R/W

0x4004 6074

ALMON

4

Alarm value for Months

R/W

0x4004 6078

ALYEAR

12

Alarm value for Years

R/W

0x4004 607C

Table 896. Alarm Seconds register (ASEC - address 0x4004 6060) bit description
Bit

Symbol

Description

Reset
value

5:0

SECONDS

Seconds value in the range of 0 to 59

-[1]

31:6

-

Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.

-

[1]

This register value is not changed by reset.

Table 897. Alarm Minutes register (AMIN - address 0x4004 6064) bit description
Bit

Symbol

Description

Reset
value

5:0

MINUTES

Minutes value in the range of 0 to 59

-[1]

31:6

-

Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.

-

[1]
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Chapter 37: LPC43xx/LPC43Sxx Real-Time Clock (RTC)

Table 898. Alarm Hours register (AHRS - address 0x4004 6068) bit description
Bit

Symbol

Description

Reset
value

4:0

HOURS

Hours value in the range of 0 to 23

-[1]

31:5

-

Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.

-

[1]

This register value is not changed by reset.

Table 899. Alarm Day of month register (ADOM - address 0x4004 606C) bit description
Bit

Symbol

Description

Reset
value

4:0

DOM

Day of month value in the range of 1 to 28, 29, 30, or 31
(depending on the month and whether it is a leap year).

-[1]

31:5

-

Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.

-

[1]

This register value is not changed by reset.

Table 900. Alarm Day of week register (ADOW - address 0x4004 6070) bit description
Bit

Symbol

Description

Reset
value

2:0

DOW

Day of week value in the range of 0 to 6.

-[1]

31:3

-

Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.

-

[1]

This register value is not changed by reset.

Table 901. Alarm Day of year register (ADOY - address 0x4004 6074) bit description
Bit

Symbol

Description

Reset
value

8:0

DOY

Day of year value in the range of 1 to 365 (366 for leap years).

-[1]

31:9

-

Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.

-

[1]

This register value is not changed by reset.

Table 902. Alarm Month register (AMON - address 0x4004 6078) bit description
Bit

Symbol

Description

Reset
value

3:0

MONTH

Month value in the range of 1 to 12.

-[1]

31:4

-

Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.

-

[1]

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This register value is not changed by reset.

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Chapter 37: LPC43xx/LPC43Sxx Real-Time Clock (RTC)

Table 903. Alarm Year register (AYRS - address 0x4004 607C) bit description
Bit

Symbol

Description

Reset
value

11:0

YEAR

Year value in the range of 0 to 4095.

-[1]

31:12

-

Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.

-

[1]

This register value is not changed by reset.

37.7 Functional description
37.7.1 Register read procedure
The RTC uses two clocks, the bus interface clock (CLK_M4_BUS) for register access and the
1 Hz clock provided by the RTCOSC in the battery powered low-power domain.
Writing data potentially takes up to 1.5 clock cycles of the 1 Hz clock to be captured in the
low-power domain. When reading, the registers reflect the actual content with a 0.5 clock
cycle delay of the 1 Hz clock, so the previously written data can show up to 2 clock cycles
of the 1 Hz clock later.
To read the correct register content, poll the last written register until it shows the new
value to ensure that the correct value has been captured. All earlier writes are also
captured at this point in time.
Within one second after a wake-up from a low power mode, the read values may be
incorrect. This can be resolved by either re-reading the register more than 1 sec after
wake-up or by reading the value until it has changed.

37.7.2 Calibration procedure
The calibration logic can periodically adjust the time counter either by not incrementing
the counter, or by incrementing the counter by 2 instead of 1. This allows calibrating the
RTC oscillator under some typical voltage and temperature conditions without the need to
externally trim the RTC oscillator.
A recommended method for determining the calibration value is to use the CLKOUT
feature to unintrusively observe the RTC oscillator frequency under the conditions it is to
be trimmed for, and calculating the number of clocks that will be seen before the time is off
by one second. That value is used to determine CALVAL.
The exact method of calibration depends on whether CALVAL is even or odd. For even
values, the hardware performs a two calibrations sequentially multiple times (one
calibration at CALVAL+1 and one calibration at CALVAL - 1) and averages both calibration
values. For odd values of CALVAL, the calibration time is accurate.
If the RTC oscillator is trimmed externally, the same method of unintrusively observing the
RTC oscillator frequency may be helpful in that process.
Backward calibration
Enable the RTC timer and calibration in the CCR register (set bits CLKEN = 1 and
CCALEN = 0). In the CALIBRATION register, set the calibration value CALVAL  1 and
select CALDIR = 1.
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Chapter 37: LPC43xx/LPC43Sxx Real-Time Clock (RTC)

• The SEC timer and the calibration counter count up for every 1 Hz clock cycle.
• When the calibration counter reaches CALVAL, a calibration match occurs and all
RTC timers will be stopped for one clock cycle so that the timers will not increment in
the next cycle.

• If an alarm match event occurs in the same cycle as the calibration match, the alarm
interrupt will be delayed by one cycle to avoid a double alarm interrupt.
Forward calibration
Enable the RTC timer and calibration in the CCR register (set bits CLKEN = 1 and
CCALEN = 0). In the CALIBRATION register, set the calibration value CALVAL  1 and
select CALDIR = 0.

• The SEC timer and the calibration counter count up for every 1 Hz clock cycle.
• When the calibration counter reaches CALVAL, a calibration match occurs and the
RTC timers are incremented by 2.

• When the calibration event occurs, the LSB of the ALSEC register is forced to be one
so that the alarm interrupt will not be missed when skipping a second.

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Chapter 38: LPC43xx/LPC43Sxx Windowed Watchdog timer
(WWDT)
Rev. 2.4 — 22 August 2018

User manual

38.1 How to read this chapter
The WWDT is available on all LPC43xx/LPC43Sxx parts.

38.2 Basic configuration
The WWDT is configured as follows:

• See Table 904 for clocking and power control. The only clock source for the WWDT
clock (WDCLK) is the IRC.

• The WWDT cannot be reset by software.
• The WWDT interrupt is connected to slot # 7 in the Event router and slot #49 in the
M4 NVIC.

• The branch clock CLK_M4_WWDT must be enabled to trigger the WWDT interrupt.
• The WWDT registers can be accessed by the GPDMA as memory-to-memory
transfer.
Table 904. WWDT clocking and power control
Base clock

Branch clock

Operating
frequency

Clock to WWDT register interface
(PCLK)

BASE_M4_CLK

CLK_M4_WWDT up to 204 MHz

Enable this branch
clock when the WWDT
is running.

Watchdog clock (WDCLK)

BASE_SAFE_CLK

-

-

12 MHz (fixed
frequency)

Notes

38.3 Features
• Internally resets chip if not reloaded during the programmable time-out period.
• Optional windowed operation requires reload to occur between a minimum and
maximum time-out period, both programmable.

• Optional warning interrupt can be generated at a programmable time prior to
watchdog time-out.

• Programmable 24 bit timer with internal fixed pre-scaler.
• Selectable time period from 1,024 watchdog clocks (TWDCLK  256  4) to over 67
million watchdog clocks (TWDCLK  224  4) in increments of 4 watchdog clocks.

• Safe watchdog operation. Once enabled, requires a hardware reset or a Watchdog
reset to be disabled.

• Incorrect feed sequence causes immediate watchdog reset if enabled.
• The watchdog reload value can optionally be protected such that it can only be
changed after the “warning interrupt” time is reached.

• Flag to indicate Watchdog reset.
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Chapter 38: LPC43xx/LPC43Sxx Windowed Watchdog timer (WWDT)

• The WWDT uses the IRC as a fixed clock source.

38.4 Applications
The purpose of the Watchdog Timer is to reset the microcontroller within a reasonable
amount of time if it enters an erroneous state. When enabled, a watchdog event will be
generated if the user program fails to feed (or reload) the Watchdog within a
predetermined amount of time. The Watchdog event will cause a chip reset if configured
to do so.
When a watchdog window is programmed, an early watchdog feed is also treated as a
watchdog event. This allows preventing situations where a system failure may still feed
the watchdog. For example, application code could be stuck in an interrupt service that
contains a watchdog feed. Setting the window such that this would result in an early feed
will generate a watchdog event, allowing for system recovery.

38.5 Description
The Watchdog consists of a fixed divide-by-4 pre-scaler and a 24-bit counter which
decrements on every clock cycle. The minimum value from which the counter decrements
is 0xFF. Setting a value lower than 0xFF causes 0xFF to be loaded in the counter. Hence
the minimum Watchdog interval is (TWDCLK  256  4) and the maximum Watchdog
interval is (TWDCLK  224  4) in multiples of (TWDCLK  4). The Watchdog should be used
in the following manner:

• Set the Watchdog time-out value in TC register.
• Setup the Watchdog timer operating mode in MOD register.
• Set a value for the watchdog window time in WINDOW register if windowed operation
is required.

• Set a compare value for the watchdog warning interrupt in the WARNINT register if a
warning interrupt is required.

• Enable the Watchdog by writing 0xAA followed by 0x55 to the FEED register.
• The Watchdog must be fed again before the Watchdog counter reaches zero in order
to prevent a watchdog event. If a window value is programmed, the feed must also
occur after the watchdog counter passes that value.
When the Watchdog Timer is configured so that a watchdog event will cause a reset and
the counter reaches zero, the CPU will be reset, loading the stack pointer and program
counter from the vector table as in the case of external reset. The Watchdog time-out flag
(WDTOF) can be examined to determine if the Watchdog has caused the reset condition.
The WDTOF flag must be cleared by software.
When the Watchdog Timer is configured to generate a warning interrupt, the interrupt will
occur when the counter matches the compare value defined by the WARNINT register.

38.5.1 WWDT behavior in Debug mode
If code execution is halted in Debug mode, the WWDT stops counting until code execution
resumes.

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Chapter 38: LPC43xx/LPC43Sxx Windowed Watchdog timer (WWDT)

38.5.2 WWDT behavior in the power-down modes
The WWDT is running in Sleep mode. A watchdog triggered reset in Sleep mode resets
and wakes up the chip. Likewise, a watchdog triggered interrupt wakes up the chip from
Sleep mode if the interrupt is enabled in the NVIC.
The WWDT is not operating in Deep-sleep, Power-down, and Deep power-down modes.

38.6 Clocking
The watchdog timer block uses two clocks: PCLK and WDCLK. PCLK is used for the APB
accesses to the watchdog registers and is derived from the BASE_M4_CLK. The WDCLK
is used for the watchdog timer counting and is derived from the IRC. The clock source (the
IRC) is fixed to ensure that the WDT always has a valid clock.
There is some synchronization logic between these two clock domains. When the MOD
and TC registers are updated by APB operations, the new value will take effect in three
WDCLK cycles on the logic in the WDCLK clock domain. When the watchdog timer is
counting the WDCLK clock cycles, the synchronization logic will first lock the value of the
counter on WDCLK and then synchronize it with the PCLK for reading when the TV
register by the CPU.

38.7 Register description
The Watchdog registers are shown in Table 905.
Table 905. Register overview: Watchdog timer (base address 0x4008 0000)
Name

Access Address Description
offset

Reset
value[1]

Reference

MOD

R/W

0x000

Watchdog mode register. This register contains the basic
mode and status of the Watchdog Timer.

0

Table 906

TC

R/W

0x004

Watchdog timer constant register. This register determines
the time-out value.

0xFF

Table 908

FEED

WO

0x008

Watchdog feed sequence register. Writing 0xAA followed by NA
0x55 to this register reloads the Watchdog timer with the
value contained in WDTC.

Table 909

TV

RO

0x00C

Watchdog timer value register. This register reads out the
current value of the Watchdog timer.

0xFF

Table 910

-

-

0x010

Reserved

-

-

WARNINT

R/W

0x014

Watchdog warning interrupt register. This register contains
the Watchdog warning interrupt compare value.

0

Table 911

WINDOW

R/W

0x018

Watchdog timer window register. This register contains the
Watchdog window value.

0xFF FFFF

Table 912

[1]

Reset value reflects the data stored in used bits only. It does not include reserved bits content.

38.7.1 Watchdog mode register
The WDMOD register controls the operation of the Watchdog as per the combination of
WDEN and RESET bits. Note that a watchdog feed must be performed before any
changes to the WDMOD register take effect.
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Chapter 38: LPC43xx/LPC43Sxx Windowed Watchdog timer (WWDT)

Table 906. Watchdog Mode register (MOD - 0x4008 0000) bit description
Bit

Symbol

0

WDEN

1

Value

Description

Reset value

Watchdog enable bit. This bit is Set Only.

0

0

The watchdog timer is stopped.

1

The watchdog timer is running.

WDRESET

Watchdog reset enable bit. This bit is Set Only.

0

0

A watchdog time-out will not cause a chip reset.

1

A watchdog time-out will cause a chip reset.

2

WDTOF

Watchdog time-out flag. Set when the watchdog
timer times out, by a feed error, or by events
associated with WDPROTECT, cleared by
software. Causes a chip reset if WDRESET = 1.
This flag is cleared by software writing a 0 to this
bit.

0 (Only after
external reset)

3

WDINT

Watchdog interrupt flag. Set when the timer
reaches the value in the WARNINT register.
Cleared by software by writing a 1 to this bit.

0

4

WDPROTECT

Watchdog update mode. This bit is Set Only.

0

7:5

-

0

The watchdog time-out value (WDTC) can be
changed at any time.

1

The watchdog time-out value (WDTC) can be
changed only after the counter is below the value
of WDWARNINT and WDWINDOW.
Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit
is not defined.

NA

Once the WDEN, WDPROTECT, or WDRESET bits are set they can not be cleared by
software. Both flags are cleared by an external reset or a Watchdog timer reset.
WDTOF The Watchdog time-out flag is set when the Watchdog times out, when a feed
error occurs, or when WDPROTECT =1 and an attempt is made to write to the TC
register. This flag is cleared by software writing a 0 to this bit.
WDINT The Watchdog interrupt flag is set when the Watchdog counter reaches the value
specified by WDWARNINT. This flag is cleared when any reset occurs, and is cleared by
software by writing a 1 to this bit.
Watchdog reset or interrupt will occur any time the watchdog is running and has an
operating clock source. Any clock source works in Sleep mode, and the IRC works in
Deep-sleep mode. If a watchdog interrupt occurs in Sleep or Deep-sleep mode, it will
wake up the device.

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Chapter 38: LPC43xx/LPC43Sxx Windowed Watchdog timer (WWDT)

Table 907. Watchdog operating modes selection
WDEN

WDRESET

Mode of Operation

0

X (0 or 1)

Debug/Operate without the Watchdog running.

1

0

Watchdog interrupt mode: the watchdog warning interrupt will be
generated but watchdog reset will not.
When this mode is selected, the watchdog counter reaching the value
specified by WDWARNINT will set the WDINT flag and the Watchdog
interrupt request will be generated.

1

1

Watchdog reset mode: Both the watchdog interrupt and watchdog reset
are enabled.
When this mode is selected, the watchdog counter reaching the value
specified by WDWARNINT will set the WDINT flag and the Watchdog
interrupt request will be generated. The watchdog counter reaching zero
will reset the microcontroller.
Remark: Other causes for a watchdog reset are: A watchdog feed or
changing the WDTC value (if the WDPROTECT bit is set in the MOD
register) before reaching the value of WDWINDOW.

38.7.2 Watchdog timer constant register
The TC register determines the time-out value. Every time a feed sequence occurs, the
TC register content is reloaded into the Watchdog timer. This is pre-loaded with the value
0x00 00FF upon reset. Writing values below 0xFF will cause 0x00 00FF to be loaded into
the TC register. Thus the minimum time-out interval is TWDCLK  256  4.
If the WDPROTECT bit in MOD register is set to one, an attempt to change the value of
TC before the watchdog counter is below the values of WDWARNINT and WDWINDOW
will cause a watchdog reset and set the WDTOF flag.
Table 908. Watchdog Timer Constant register (TC - 0x4008 0004) bit description
Bit

Symbol

Description

Reset value

23:0

WDTC

Watchdog time-out value.

0x00 00FF

31:24

-

Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.

NA

38.7.3 Watchdog feed register
Writing 0xAA followed by 0x55 to this register will reload the Watchdog timer with the
time-out value in the TC register. This operation will also start the Watchdog if it is enabled
via the MOD register. Setting the WDEN bit in the WDMOD register is not sufficient to
enable the Watchdog. A valid feed sequence must be completed after setting WDEN
before the Watchdog is capable of generating a reset. Until then, the Watchdog will ignore
feed errors. After writing 0xAA to FEED register, access to any Watchdog register other
than writing 0x55 to FEED register causes an immediate reset/interrupt when the
Watchdog is enabled, and sets the WDTOF flag. The reset will be generated during the
second PCLK following an incorrect access to a Watchdog register during a feed
sequence.
Interrupts should be disabled during the feed sequence. An abort condition will occur if an
interrupt happens during the feed sequence.

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Chapter 38: LPC43xx/LPC43Sxx Windowed Watchdog timer (WWDT)

Table 909. Watchdog Feed register (FEED - 0x4008 0008) bit description
Bit

Symbol

Description

Reset value

7:0

Feed

Feed value should be 0xAA followed by 0x55.

NA

38.7.4 Watchdog timer value register
The WDTV register is used to read the current value of Watchdog timer counter.
When reading the value of the 24 bit counter, the lock and synchronization procedure
takes up to 6 WDCLK cycles plus 6 PCLK cycles, so the value of WDTV is older than the
actual value of the timer when it's being read by the CPU.
Table 910. Watchdog Timer Value register (TV - 0x4008 000C) bit description
Bit

Symbol

Description

Reset value

23:0

Count

Counter timer value.

0x00 00FF

31:24

-

Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.

NA

38.7.5 Watchdog timer warning interrupt register
The WDWARNINT register determines the watchdog timer counter value that will
generate a watchdog interrupt. When the watchdog timer counter matches the value
defined by WDWARNINT, an interrupt will be generated after the subsequent WDCLK.
A match of the watchdog timer counter to WDWARNINT occurs when the bottom 10 bits
of the counter have the same value as the 10 bits of WARNINT, and the remaining upper
bits of the counter are all 0. This gives a maximum time of 1,023 watchdog timer counts
(4,096 watchdog clocks) for the interrupt to occur prior to a watchdog event. If
WDWARNINT is set to 0, the interrupt will occur at the same time as the watchdog event.
Table 911. Watchdog Timer Warning Interrupt register (WARNINT - 0x4008 0014) bit
description
Bit

Symbol

Description

Reset value

9:0

WDWARNINT

Watchdog warning interrupt compare value.

0

31:10

-

Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit is not
defined.

NA

38.7.6 Watchdog timer window register
The WDWINDOW register determines the highest WDTV value allowed when a watchdog
feed is performed. If a feed valid sequence completes prior to WDTV reaching the value in
WDWINDOW, a watchdog event will occur.
WDWINDOW resets to the maximum possible WDTV value, so windowing is not in effect.
Values of WDWINDOW below 0x100 will make it impossible to ever feed the watchdog
successfully.

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Chapter 38: LPC43xx/LPC43Sxx Windowed Watchdog timer (WWDT)

Table 912. Watchdog Timer Window register (WINDOW - 0x4008 0018) bit description
Bit

Symbol

Description

Reset value

23:0

WDWINDOW Watchdog window value.

31:24

-

0xFF FFFF

Reserved, user software should not write ones to reserved NA
bits. The value read from a reserved bit is not defined.

38.8 Block diagram
The block diagram of the Watchdog is shown below in the Figure 122. The
synchronization logic (PCLK - WDCLK) is not shown in the block diagram.

WDTC
WDCLKSEL

feed ok
wd_clk

÷4

24-bit down counter

clock
select

enable count

WDTV

WDFEED
feed sequence
detect and
protection

in
range

WDTC write

feed ok

feed error

WDWIND
compare
0

WDINTVAL

compare

compare

underflow

interrupt
compare

shadow bit
feed ok
WDMOD
register

WDPROTECT

WDTOF

WDINT

WDRESET

WDEN

(WDMOD[4])

(WDMOD[2])

(WDMOD[3])

(WDMOD[1])

(WDMOD[0])

chip reset
watchdog
interrupt

Fig 122. Watchdog block diagram

38.9 Watchdog timing examples
The following figures illustrate several aspects of Watchdog Timer operation is shown
below in Figure 123.

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Chapter 38: LPC43xx/LPC43Sxx Windowed Watchdog timer (WWDT)

WDCLK / 4
Watchdog
Counter

125A 1259

1258

1257

Early Feed
Event
Watchdog
Reset
Conditions :
WINDOW
WARNINT
TC

= 0x1200
= 0x3FF
= 0x2000

Fig 123. Early Watchdog Feed with Windowed Mode Enabled

WDCLK / 4
Watchdog
Counter

1201

1200 11FF 11FE 11FD 11FC 2000 1FFF 1FFE 1FFD 1FFC

Correct Feed
Event
Watchdog
Reset
Conditions :
WDWINDOW = 0x1200
WDWARNINT = 0x3FF
WDTC
= 0x2000

Fig 124. Correct Watchdog Feed with Windowed Mode Enabled

WDCLK / 4
Watchdog
Counter

0403

0402

0401

0400 03FF 03FE 03FD 03FC 03FB 03FA 03F9

Watchdog
Interrupt
Conditions :
WINDOW
WARNINT
TC

= 0x1200
= 0x3FF
= 0x2000

Fig 125. Watchdog Warning Interrupt

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Chapter 39: LPC43xx/LPC43Sxx Event monitor/recorder
Rev. 2.4 — 22 August 2018

User manual

39.1 How to read this chapter
The event monitor/recorder is available on parts with on-chip flash only.

39.2 Basic configuration
The event monitor/recorder is configured together with the RTC:

• See Table 913 for clocking and power control. The 1 kHz output of the 32 kHz
oscillator must be enabled in the CREG0 register in the CREG block (see Table 96).

• The event monitor/recorder raises an RTC interrupt which is connected to slot # 5 in
the Event router and slot #47 in the NVIC.

• Enable the SAMPLE pin for monitoring the sample clock in the CREG0 register (see
Table 96).
Table 913. RTC and event monitor/recorder clocking and power control
Base clock

Branch clock

Operating frequency

Clock to the RTC and event
BASE_M4_CLK
monitor/router register interface

CLK_M4_BUS up to 204 MHz

32 kHz crystal oscillator output
for the RTC counter/timer clock

-

-

1024 Hz (fixed frequency);
the RTC receives an
internal 1 Hz clock.

39.3 Features
• Supports three digital event inputs in the RTC power domain.
• An event is a level change at the digital event inputs.
• For each event channel, two timestamps mark the first and the last occurrence of an
event. Each channel also has a dedicated counter tracking the total number of events.
Timestamp values are taken from the RTC.

•
•
•
•
•
•

Runs in RTC power domain, independent of system power supply.
Can run in Deep Power Down mode if VBAT is present.
Very low-power consumption.
Interrupt available if system is up.
A qualified event can be used as a wake-up trigger.
State of event inputs accessible by software through general purpose I/O.

39.4 Applications
The event monitor/recorder is used to record tampering events in sealed product
enclosures. Sensors report any attempt to open the enclosure, or to tamper with the
device in any other way. The primary purpose of the Event Monitor/Recorder is to store
records of such events when the device is powered only by the backup battery.
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Chapter 39: LPC43xx/LPC43Sxx Event monitor/recorder

39.5 General description
The Event Monitor/Recorder relies on VBAT to be present at all times. A loss or dip of
VBAT voltage causes the Real-Time Clock power fail detector to reset the event
recordings. It is therefore important to have a VBAT power source that can deliver power
for the longest expected mains power outage.
Once system power is restored, the CPU can check for recorded tamper events. If there
were tamper events, the timestamp registers for the first and the last event would indicate
the period over which they occurred.
An edge on an event input is sampled with either a 1 kHz clock, a 64 Hz clock, or a 16 Hz
clock. A transition in either direction must be captured by two successive edges of this
clock in order to be recognized as a valid transition. This provides a 1-2 ms rejection filter
in case of the 1 kHz sample clock, a 15.6-31.2 ms rejection filter in case of the 64 Hz
sample clock, and a 62.5-125ms rejection filter in case of the 16 Hz sample clock. Such
an event will set the EVx bit in the ERSTATUS register on the next rising edge of the 1 Hz
clock.
If an event occurs, a timestamp will be taken from the RTC and stored in the
ERLASTSTAMPx register. This timestamp will be updated with every new event. The
event will also update the ERFIRSTSTAMPx register if this is the first event to occur since
the last time the EVx bit in the status register was cleared.
In addition to taking the timestamp(s), a 3-bit counter (ERCOUNTERx) will be
incremented on the rising edge of the 1 Hz clock (i.e. coincident with the ERLASTSTAMPx
register being updated). The counter stops counting and holds when it reaches a count of
seven. It will be cleared automatically when the software clears the EVx bit in the status
register.
An event can be enabled to clear the backup registers in the RTC block asynchronously.
This works even when the 32 kHz oscillator is not running or when Event
Monitor/Recorder clocks are disabled.
The following figure shows a block diagram of the Event Monitor/Recorder.

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Chapter 39: LPC43xx/LPC43Sxx Event monitor/recorder

RTC

Timestamp value
doy:h:m:s

ERFIRSTSTAMP0

ERCONTROL

ERLASTSTAMP 0
WAKEUP0
WAKEUP1

ERFIRSTSTAMP1

Control
Block

ERLASTSTAMP 1

WAKEUP2

ERFIRSTSTAMP2
ERSTATUS

ERLASTSTAMP 2
To wakeup/interrupt

Fig 126. Event Monitor/Recorder block diagram

The CPU may at any time check the ERSTATUS register for events. If, for instance the
EV0 bit is set, the corresponding ERFIRSTSTAMP0 and ERLASTSTAMP0 registers
contain valid timestamps. The ERCOUNTER0 will also contain a valid count of the total
number of events on channel 0 (up to a maximum of seven).
Once the (private) timestamps have been read, the CPU can clear the ERSTATUS.EVx
bits by writing a 1 to it.
The CPU should ignore the timestamp registers if the ERSTATUS.EVx bit is cleared.
There is no mechanism to clear or invalidate the timestamps after the event flag in the
status register has been cleared. The timestamp registers will keep their old values until a
new qualified event updates them. Such a qualified event will set the ERSTATUS.EVx bit
and inform the CPU that the timestamp registers contain new values.
An event channel can be qualified as a wake-up trigger signal by setting the
INTWAKE_ENAx bit in the ERCONTROL register. An event in that channel will then wake
up the device from a power saving mode.

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Chapter 39: LPC43xx/LPC43Sxx Event monitor/recorder

39.6 Pin description
Table 914. Event Monitor/Recorder pin description
Name

Type

Description

WAKEUP0

Input

Event input for event monitor/recorder channel 0.

WAKEUP1

Input

Event input for event monitor/recorder channel 1.

WAKEUP2

Input

Event input for event monitor/recorder channel 2.

SAMPLE

Output

Sample clock output for the event monitor/recorder. Use the
CREG0 register to enable this pin for the sample output. (see
Table 96).

39.7 Register description
Reset values apply only to a power-up of the Event Monitor/Recorder block, other types of
reset have no effect on this block. Since the Event Monitor/Recorder is powered
whenever either of the VDD(REG)(3V3), or VBAT supplies are present, power-up reset occurs
only when both supplies were absent and then one is turned on. The Reset Value reflects
the data stored in used bits only. It does not include reserved bits content.
Table 915. Register overview: event monitor/recorder (base address 0x4004 6000)
Name

Access Address
offset

Description

ERCONTROL

R/W

0x084

Event Monitor/Recorder Control register. Contains bits that control
0
actions for the event channels as well as for Event Monitor/Recorder
setup.

ERSTATUS

R/W

0x080

Event Monitor/Recorder Status register. Contains status flags for
event channels and other Event Monitor/Recorder conditions.

0

ERCOUNTERS

RO

0x088

Event Monitor/Recorder Counters register. Allows reading the
counters associated with the event channels.

0

ERFIRSTSTAMP0 RO

0x090

Event Monitor/Recorder First Stamp register for channel 0. Retains
the time stamp for the first event on channel 0.

NA

ERFIRSTSTAMP1 RO

0x094

Event Monitor/Recorder First Stamp register for channel 1 (see
ERFIRSTSTAMP0 description).

NA

ERFIRSTSTAMP2 RO

0x098

Event Monitor/Recorder First Stamp register for channel 2 (see
ERFIRSTSTAMP0 description).

NA

ERLASTSTAMP0

RO

0x0A0

Event Monitor/Recorder Last Stamp register for channel 0. Retains
the time stamp for the last (i.e. most recent) event on channel 0.

NA

ERLASTSTAMP1

RO

0x0A4

Event Monitor/Recorder Last Stamp register for channel 1 (see
ERLASTSTAMP0 description).

NA

ERLASTSTAMP2

RO

0x0A8

Event Monitor/Recorder Last Stamp register for channel 2 (see
ERLASTSTAMP0 description).

NA

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Chapter 39: LPC43xx/LPC43Sxx Event monitor/recorder

39.7.1 Event Monitor/Recorder Control Register
The Event Monitor/Recorder Control Register allows setup of the Event Monitor/Recorder
and individual control over aspects of each channel’s operation.
Table 916. Event Monitor/Recorder Control Register (ERCONTRO, address 0x4004 6084) bit description
Bit

Symbol

0

INTWAKE_EN0

Value Description

Reset
value

Interrupt and wake-up enable for channel 0.

0

0

No interrupt or wake-up will be generated by event channel 0.

1

An event in channel 0 will trigger an (RTC) interrupt and a wake-up request.

1

-

Reserved. Read value is undefined, only zero should be written.

NA

2

POL0

Selects the polarity of an event on input pin WAKEUP0.

0

3

0

A channel 0 event is defined as a negative edge on WAKEUP0.

1

A channel 0 event is defined as a positive edge on WAKEUP0.

EV0_INPUT_EN

Event enable control for channel 0. Event Inputs should remain DISABLED when 0
not being used for event detection, particularly if the associated pin is being used
for some other function.
0

Event 0 input is disabled and forced high internally.

1

Event 0 input is enabled.

9:4

-

Reserved. Read value is undefined, only zero should be written.

NA

10

INTWAKE_EN1

Interrupt and wake-up enable for channel 1.

0

0

No interrupt or wake-up will be generated by event channel 1.

1

An event in channel 1 will trigger an (RTC) interrupt and a wake-up request.

11

-

Reserved. Read value is undefined, only zero should be written.

12

POL1

Selects the polarity of an event on input pin WAKEUP1.

13

0

A channel 1 event is defined as a negative edge on WAKEUP1.

1

A channel 1 event is defined as a positive edge on WAKEUP1.

EV1_INPUT_EN

Event enable control for channel 1. Event Inputs should remain DISABLED when 0
not being used for event detection, particularly if the associated pin is being used
for some other function.
0

Event 1 input is disabled and forced high internally.

1

Event 1 input is enabled.

19:14 20

-

22

POL2

23

Reserved. Read value is undefined, only zero should be written.

INTWAKE_EN2

21

User manual

NA

Interrupt and wake-up enable for channel 2.
0

No interrupt or wake-up will be generated by event channel 2.

1

An event in channel 2 will trigger an (RTC) interrupt and a wake-up request.
Reserved. Read value is undefined, only zero should be written.

NA

Selects the polarity of an event on input pin WAKEUP2.

0

0

A channel 2 event is defined as a negative edge on WAKEUP2.

1

A channel 2 event is defined as a positive edge on WAKEUP2.

EV2_INPUT_EN

UM10503

NA

Event enable control for channel 2. Event Inputs should remain DISABLED when 0
not being used for event detection, particularly if the associated pin is being used
for some other function.
0

Event 2 input is disabled and forced high internally.

1

Event 2 input is enabled.
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Chapter 39: LPC43xx/LPC43Sxx Event monitor/recorder

Table 916. Event Monitor/Recorder Control Register (ERCONTRO, address 0x4004 6084) bit description
Bit

Symbol

Value Description

Reset
value

29:24 -

Reserved. Read value is undefined, only zero should be written.

NA

31:30 ERMODE

Controls enabling the Event Monitor/Recorder and selecting its operating
frequency. Event Monitor/Recorder registers can always be written to regardless
of the state of these bits. Events occurring during the 1-sec interval immediately
following enabling of the clocks may not be recognized.

0

0x0

Disable Event Monitor/Recorder clocks.
Operation of the Event Monitor/Recorder is disabled except for asynchronous
clearing of GP registers if selected.

0x1

16 Hz sample clock. Enable Event Monitor/Recorder and select a 16 Hz sample
clock for event input edge detection and glitch suppression.
Pulses (in either direction) shorter than 62.5 ms to 125 ms will be filtered out.

0x2

64 Hz sample clock. Enable Event Monitor/Recorder and select a 64 Hz sample
clock for event input edge detection and glitch suppression.
Pulses (in either direction) shorter than 15.6 ms to 31.2 ms will be filtered out.

0x3

1 kHz sample clock. Enable Event Monitor/Recorder and select a 1 kHz sample
clock for event input edge detection and glitch suppression.
Pulses (in either direction) shorter than 1 ms to 2 ms will be filtered out.

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Chapter 39: LPC43xx/LPC43Sxx Event monitor/recorder

39.7.2 Event Monitor/Recorder Status Register
The Event Monitor/Recorder Status Register contains flags for the 3 event channels,
general purpose register clear flag, and the interrupt/wake-up flag.
Table 917. Event Monitor/Recorder Status Register (ERSTATUS, address 0x4004 6080) bit description
Bit

Symbol

0

EV0

1

2

3

Value Description

Reset
value

Channel0 event flag (WAKEUP0 pin). Set at the end of any second if there has
been an event during the preceding second. This bit is cleared by writing a 1 to it.
Writing 0 has no effect.
0

No event change on channel 0.

1

At least one event has occurred on channel 0.

EV1

Channel1 Event flag (WAKEUP1 pin). Set at the end of any second if there has
been an event during the preceding second. This bit is cleared by writing a 1 to it.
Writing 0 has no effect.
0

No event change on channel 1.

1

At least one event has occurred on channel 1.

EV2

Channel2 Event flag (WAKEUP2 pin). Set at the end of any second if there has
been an event during the preceding second. This bit is cleared by writing a 1 to it.
Writing 0 has no effect.
0

No event change on channel 2.

1

At least one event has occurred on channel 2.

GP_CLEARED

General purpose register asynchronous clear flag. This bit is cleared by writing a 1
to it. Writing 0 has no effect.
0
1

0

0

General purpose registers have been asynchronous cleared.

-

Reserved. Read value is undefined, only zero should be written.

31

WAKEUP

Interrupt/wake-up request flag (Read-only). This bit is cleared by writing a 1 to it.
Writing 0 has no effect.

User manual

0

General purpose registers have not been asynchronous cleared.

30:4

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0

No interrupt/wake-up request is pending

1

An interrupt/wake-up request is pending.

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0

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Chapter 39: LPC43xx/LPC43Sxx Event monitor/recorder

39.7.3 Event Monitor/Recorder Counters Register
The Event Monitor/Recorder Counters Register is a read-only register that allows reading
counters that record the number of events on each Event Monitor/Recorder channel.
Table 918. Event Monitor/Recorder Counters Register (ERCOUNTERS, address 0x4004 6088) bit description
Bit

Symbol

2:0

COUNTER0 Value of the counter for Event 0. If the counter reaches full count (the value 7), it remains there
if additional events occur. This counter is cleared when the corresponding EVx bit in the
ERSTATUS register is cleared by software.

7:3

-

10:8

COUNTER1 Value of the counter for event 1. See description for COUNTER0.

15:11 -

Description

Reset
value

0

Reserved. The value read from a reserved bit is not defined.

NA
0

Reserved. The value read from a reserved bit is not defined.

NA

18:16 COUNTER2 Value of the counter for event 2. See description for COUNTER0.
31:19 -

0

Reserved. The value read from a reserved bit is not defined.

NA

39.7.4 Event Monitor/Recorder First Stamp Registers
The read-only Event Monitor/Recorder First Stamp Registers record a timestamp (from
the RTC) of the first event that occurs on each Event Monitor/Recorder channel. This is
when the corresponding EVx bit in the ERSTATUS register becomes set. Once that has
happened, these registers will not change until software clears the corresponding EVx bit
in the ERSTATUS register.
Contents of these register are only valid if the corresponding EVx bit in the ERSTATUS
register = 1.
Table 919. Event Monitor/Recorder First Stamp Register (ERFIRSTSTAMP[0:2],
0x0x4004 6090 (ERFIRSTSTAMP0) to 0x4004 6098 (ERFIRSTSTAMP2)) bit
description
Bit

Symbol Description

Reset value

5:0

SEC

Seconds value in the range of 0 to 59.

NA

11:6

MIN

Minutes value in the range of 0 to 59.

NA

16:12 HOUR

Hours value in the range of 0 to 23.

NA

25:17 DOY

Day of Year value in the range of 1 to 366.

NA

31:26 -

Reserved. The value read from a reserved bit is not defined.

NA

39.7.5 Event Monitor/Recorder Last Stamp Registers
The read-only Event Monitor/Recorder Last Stamp Registers record a timestamp (from
the RTC) whenever an event occurs on each Event Monitor/Recorder channel.
Contents of these register are only valid if the corresponding EVx bit in the ERSTATUS
register = 1.

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Chapter 39: LPC43xx/LPC43Sxx Event monitor/recorder

Note that after a first event on any channel, the contents of the corresponding
ERFIRSTSTAMP and ERLASTSTAMP registers will be the same (the first event and the
most recent event being the same). The values will diverge if a second event occurs on
the same channel
Table 920. Event Monitor/Recorder Last Stamp Register (ERLASTSTAMP[0:2],
0x0x4004 60A0 (ERLASTSTAMP0) to 0x4004 60A8 (ERLASTSTAMP2)) bit
description

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Bit

Symbol Description

5:0

SEC

Seconds value in the range of 0 to 59.

NA

11:6

MIN

Minutes value in the range of 0 to 59.

NA

16:12 HOUR

Hours value in the range of 0 to 23.

NA

25:17 DOY

Day of Year value in the range of 1 to 366.

NA

31:26 -

Reserved. The value read from a reserved bit is not defined.

NA

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Chapter 40: LPC43xx/LPC43Sxx USART0_2_3
Rev. 2.4 — 22 August 2018

User manual

40.1 How to read this chapter
The USART0/2/3 controllers are available on all LPC43xx/LPC43Sxx parts.

40.2 Basic configuration
The USART0/2/3 are configured as follows:

•
•
•
•

See Table 921 for clocking and power control.
The USART0/2/3 are reset by the UART0/2/3_RST (reset #44/46/47).
The USART0/2/3 interrupts are connected to slots # 24/26/27 in the NVIC.
For connecting the USART0/2/3 receive and transmit lines to the GPDMA, use the
DMAMUX register in the CREG block (see Table 100) and enable the GPDMA
channel in the DMA Channel Configuration registers (Section 21.6.20).

• The internal USART transmit/receive active signals (USARTx TX/RX) are connected
to the GIMA (see Table 207). These signals are driven when data are transmitted or
received and can be used to trigger any of the timers or the SCT.

• In synchronous mode, set the clock frequency on pin U0/2/3_UCLK to
 6  BASE_UART0/2/3_CLK.
Table 921. USART0/2/3 clocking and power control
Base clock

Branch clock

Operating
frequency

USART0 clock to register interface

BASE_M4_CLK

CLK_M4_UART0

up to 204 MHz

USART0 peripheral clock (PCLK)

BASE_UART0_CLK

CLK_APB0_UART0 up to 204 MHz

USART2 clock to register interface

BASE_M4_CLK

CLK_M4_UART2

USART2 peripheral clock (PCLK)

BASE_UART2_CLK

CLK_APB2_UART2 up to 204 MHz

USART3 clock to register interface

BASE_M4_CLK

CLK_M4_UART3

USART3 peripheral clock (PCLK)

BASE_UART3_CLK

CLK_APB2_UART3 up to 204 MHz

up to 204 MHz
up to 204 MHz

40.3 Features
•
•
•
•
•
•
•
•
•
UM10503

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16-byte receive and transmit FIFOs.
Register locations conform to ‘550 industry standard.
Receiver FIFO trigger points at 1, 4, 8, and 14 bytes.
Built-in baud rate generator.
UART mode allows for implementation of either software or hardware flow control.
RS-485/EIA-485 9-bit mode support with output enable.
Support for synchronous mode UART (USART).
IrDA interface (USART3 only).
DMA support.
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Chapter 40: LPC43xx/LPC43Sxx USART0_2_3

• Smart Card interface.

40.4 General description
The architecture of the USART is shown below in the block diagram.
The APB interface provides a communications link between the CPU or host and the
USART.
The USART receiver block, RX, monitors the serial input line, RXD, for valid input. The
USART RX Shift Register (RSR) accepts valid characters via RXD. After a valid character
is assembled in the RSR, it is passed to the USART RX Buffer Register FIFO to await
access by the CPU or host via the generic host interface.
The USART transmitter block, TX, accepts data written by the CPU or host and buffers the
data in the USART TX Holding Register FIFO (THR). The USART TX Shift Register (TSR)
reads the data stored in the THR and assembles the data to transmit via the serial output
pin, TXD1.
The USART Baud Rate Generator block, BRG, generates the timing enables used by the
USART TX and RX blocks. The BRG clock input source is PCLK. The main clock is
divided down per the divisor specified in the DLL and DLM registers. This divided down
clock is a 16x oversample clock, NBAUDOUT.
The interrupt interface contains registers IER and IIR. The interrupt interface receives
several one clock wide enables from the TX and RX blocks.
Status information from the TX and RX is stored in the LSR. Control information for the TX
and RX is stored in the LCR.

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Chapter 40: LPC43xx/LPC43Sxx USART0_2_3

Transmitter
Transmitter
Holding
Register

Transmitter
FIFO

Transmitter
Shift
Register

TXD

Transmitter
DMA
Interface
TX_DMA_REQ
TX_DMA_CLR

CSRC
UCLK
UCLK
OUT

Baud Rate/Clock Generator
Fractional
Main
Rate
Divider
Divider
(DLM, DLL)

PCLK

interrupt

UCLK
IN

FIFO Control
& Status
Interrupt
Control &
Status

Line Control
& Status
BAUD

RS485, IrDA,
& Auto-baud
Receiver
Receiver
Buffer
Register

Receiver
FIFO

Receiver
Shift
Register

RXD

Receiver
DMA
Interface
RX_DMA_REQ
RX_DMA_CLR

Fig 127. USART block diagram

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Chapter 40: LPC43xx/LPC43Sxx USART0_2_3

40.5 Pin description
Table 922. USART0/2/3 pin description
Pin function

Direction

Description

USART0

U0_RXD

I

Serial Input. Serial receive data.

U0_TXD

O

Serial Output. Serial transmit data.

U0_DIR

I/O

RS-485/EIA-485 output enable/direction control.

U0_UCLK

I/O

Serial clock input/output for USART0 in synchronous mode.

U2_RXD

I

Serial Input. Serial receive data.

U2_TXD

O

Serial Output. Serial transmit data.

U2_DIR

I/O

RS-485/EIA-485 output enable/direction control.

U2_UCLK

I/O

Serial clock input/output for USART2 in synchronous mode.

U3_RXD

I

Serial Input. Serial receive data.

U3_TXD

O

Serial Output. Serial transmit data.

U3_DIR

I/O

RS-485/EIA-485 output enable/direction control.

U3_UCLK

I/O

Serial clock input/output for USART3 in synchronous mode.

U3_BAUD

O

USART3 baud output.

USART2

USART3

U3_BAUD is an active LOW signal of the single clock cycle and
is generated at each rising edge of a 16x clock signal for the
transmitter section of the UART. The clock rate is established by
the USART3 clock frequency divided by the fractional divider and
the divisor specified in the baud generator divisor latches.
U3_BAUD can be used as an input to an external IrDA module.

40.6 Register description
The USART contains registers organized as shown in Table 923. The Divisor Latch
Access Bit (DLAB) is contained in LCR[7] and enables access to the Divisor Latches.
Reset value reflects the data stored in used bits only. It does not include the content of
reserved bits.
Table 923. Register overview: USART0/2/3 (base address: 0x4008 1000 (UART0), 0x400C 1000 (UART2), 0x400C 2000
(UART3))
Name

Access Address Description
offset

Reset Reference
value

RBR

RO

0x000

Receiver Buffer Register. Contains the next received
character to be read (DLAB = 0).

NA

Table 924

THR

WO

0x000

Transmit Holding Register. The next character to be
transmitted is written here (DLAB = 0).

NA

Table 925

DLL

R/W

0x000

Divisor Latch LSB. Least significant byte of the baud rate
0x01
divisor value. The full divisor is used to generate a baud rate
from the fractional rate divider (DLAB = 1).

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Table 923. Register overview: USART0/2/3 (base address: 0x4008 1000 (UART0), 0x400C 1000 (UART2), 0x400C 2000
(UART3))
Name

Access Address Description
offset

DLM

R/W

0x004

Divisor Latch MSB. Most significant byte of the baud rate
0x00
divisor value. The full divisor is used to generate a baud rate
from the fractional rate divider (DLAB = 1).

Table 927

IER

R/W

0x004

Interrupt Enable Register. Contains individual interrupt
0x00
enable bits for the 7 potential USART interrupts (DLAB = 0).

Table 928

IIR

RO

0x008

Interrupt ID Register. Identifies which interrupt(s) are
pending.

0x01

Table 929

FCR

WO

0x008

FIFO Control Register. Controls USART FIFO usage and
modes.

0x00

Table 931

LCR

R/W

0x00C

Line Control Register. Contains controls for frame formatting 0x00
and break generation.

Table 932

-

-

0x010

Reserved

-

LSR

RO

0x014

Line Status Register. Contains flags for transmit and receive 0x60
status, including line errors.

Table 933

-

-

0x018

Reserved

-

-

SCR

R/W

0x01C

Scratch Pad Register. Eight-bit temporary storage for
software.

0x00

Table 934

ACR

R/W

0x020

Auto-baud Control Register. Contains controls for the
auto-baud feature.

0x00

Table 935

ICR

R/W

0x024

IrDA control register (USART3 only)

0x00

Table 936

FDR

R/W

0x028

Fractional Divider Register. Generates a clock input for the
baud rate divider.

0x10

Table 938

OSR

R/W

0x02C

Oversampling Register. Controls the degree of
oversampling during each bit time.

0xF0

Table 939

-

-

0x030 0x03C

Reserved

-

-

HDEN

R/W

0x040

Half-duplex enable Register

-

-

0x044

Reserved

-

SCICTRL

R/W

0x048

Smart card interface control register

0x00

Table 941

RS485CTRL

R/W

0x04C

RS-485/EIA-485 Control. Contains controls to configure
various aspects of RS-485/EIA-485 modes.

0x00

Table 942

RS485ADRMATCH R/W

0x050

RS-485/EIA-485 address match. Contains the address
match value for RS-485/EIA-485 mode.

0x00

Table 943

RS485DLY

R/W

0x054

RS-485/EIA-485 direction control delay.

0x00

Table 944

SYNCCTRL

R/W

0x058

Synchronous mode control register.

0x00

Table 945

TER

R/W

0x05C

Transmit Enable Register. Turns off USART transmitter for
use with software flow control.

0x01

Table 946

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Reset Reference
value

-

Table 940
-

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40.6.1 USART Receiver Buffer Register
The RBR is the top byte of the USART RX FIFO. The top byte of the RX FIFO contains the
oldest character received and can be read via the bus interface. The LSB (bit 0)
represents the “oldest” received data bit. If the character received is less than 8 bits, the
unused MSBs are padded with zeroes.
The Divisor Latch Access Bit (DLAB) in LCR must be zero in order to access the RBR.
The RBR is always Read Only.
Since PE, FE and BI bits (see Table 933) correspond to the byte sitting on the top of the
RBR FIFO (i.e. the one that will be read in the next read from the RBR), the right approach
for fetching the valid pair of received byte and its status bits is first to read the content of
the LSR register, and then to read a byte from the RBR.
Table 924. USART Receiver Buffer Registers when DLAB = 0, Read Only (RBR, addresses
0x4008 1000 (USART0), 0x400C 1000 (USART2), 0x400C 2000 (USART3)) bit
description
Bit

Symbol

Description

Reset value

7:0

RBR

Receiver buffer.
The USART Receiver Buffer Register contains the oldest
received byte in the USART RX FIFO.

undefined

Reserved

-

31:8 -

40.6.2 USART Transmitter Holding Register
The THR is the top byte of the USART TX FIFO. The top byte is the newest character in
the TX FIFO and can be written via the bus interface. The LSB represents the first bit to
transmit.
The Divisor Latch Access Bit (DLAB) in LCR must be zero in order to access the THR.
The THR is always Write Only.
Table 925. USART Transmitter Holding Register when DLAB = 0, Write Only (THR, addresses
0x4008 1000 (USART0), 0x400C 1000 (USART2), 0x400C 2000 (USART3)) bit
description
Bit

Symbol

Description

7:0

THR

Transmit Holding Register.
NA
Writing to the USART Transmit Holding Register causes the data
to be stored in the USART transmit FIFO. The byte will be sent
when it reaches the bottom of the FIFO and the transmitter is
available.

31:8 -

Reserved

Reset value

-

40.6.3 USART Divisor Latch LSB and MSB Registers
The USART Divisor Latch is part of the USART Baud Rate Generator and holds the value
used, along with the Fractional Divider, to divide the USART_PCLK clock in order to
produce the baud rate clock, which must be 16x the desired baud rate. The DLL and DLM
registers together form a 16-bit divisor where DLL contains the lower 8 bits of the divisor
and DLM contains the higher 8 bits of the divisor. A 0x0000 value is treated like a 0x0001
value as division by zero is not allowed.The Divisor Latch Access Bit (DLAB) in LCR must
be one in order to access the USART Divisor Latches. Details on how to select the right
value for DLL and DLM can be found in Section 40.6.12.
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Table 926. USART Divisor Latch LSB Register when DLAB = 1 (DLL, addresses 0x4008 1000
(USART0), 0x400C 1000 (USART2), 0x400C 2000 (USART3)) bit description
Bit

Symbol

Description

Reset value

7:0

DLLSB

Divisor latch LSB.
The USART Divisor Latch LSB Register, along with the DLM
register, determines the baud rate of the USART.

0x01

Reserved

-

31:8 -

Table 927. USART Divisor Latch MSB Register when DLAB = 1 (DLM, addresses 0x4008 1004
(USART0), 0x400C 1004 (USART2), 0x400C 2004 (USART3)) bit description
Bit

Symbol

Description

Reset value

7:0

DLMSB

Divisor latch MSB.
The USART Divisor Latch MSB Register, along with the DLL
register, determines the baud rate of the USART.

0x00

Reserved

-

31:8 -

40.6.4 USART Interrupt Enable Register
The IER is used to enable the four USART interrupt sources.
Table 928. USART Interrupt Enable Register when DLAB = 0 (IER, addresses 0x4008 1004
(USART0), 0x400C 1004 (USART2), 0x400C 2004 (USART3)) bit description
Bit

Symbol

0

RBRIE

1

2

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Value

0

Disable. Disable the RDA interrupt.

1

Enable. Enable the RDA interrupt.
THRE Interrupt Enable.
Enables the THRE interrupt for USART. The status of this
interrupt can be read from LSR[5].

0

Disable. Disable the THRE interrupt.

1

Enable. Enable the THRE interrupt.

RXIE

-

6:4

-

Reset
value

RBR Interrupt Enable.
0
Enables the Receive Data Available interrupt for USART. It
also controls the Character Receive Time-out interrupt.

THREIE

3

Description

0

RX Line Interrupt Enable.
0
Enables the USART RX line status interrupts. The status of
this interrupt can be read from LSR[4:1].
0

Disable. Disable the RX line status interrupts.

1

Enable. Enable the RX line status interrupts.

-

Reserved

-

Reserved, user software should not write ones to reserved NA
bits. The value read from a reserved bit is not defined.

7

-

8

ABEOINTEN

-

Reserved

0

Enables the end of auto-baud interrupt.

0

0

Disable. Disable end of auto-baud Interrupt.

1

Enable. Enable end of auto-baud Interrupt.

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Table 928. USART Interrupt Enable Register when DLAB = 0 (IER, addresses 0x4008 1004
(USART0), 0x400C 1004 (USART2), 0x400C 2004 (USART3)) bit description
Bit

Symbol

Value

9

ABTOINTEN

Description

Reset
value

Enables the auto-baud time-out interrupt.

0

0

Disable. Disable auto-baud time-out Interrupt.

1

Enable. Enable auto-baud time-out Interrupt.

31:10 -

Reserved, user software should not write ones to reserved NA
bits. The value read from a reserved bit is not defined.

40.6.5 USART Interrupt Identification Register
IIR provides a status code that denotes the priority and source of a pending interrupt. The
interrupts are frozen during a IIR access. If an interrupt occurs during a IIR access, the
interrupt is recorded for the next IIR access.
Table 929. USART Interrupt Identification Register, read only (IIR, addresses 0x4008 1008
(USART0), 0x400C 1008 (USART2), 0x400C 2008 (USART3)) bit description
Bit

Symbol

0

INTSTATUS

3:1

Value Description

Reset
value

Interrupt status.
1
Note that IIR[0] is active low. The pending interrupt can be
determined by evaluating IIR[3:1].
0

Interrupt pending. At least one interrupt is pending.

1

Not pending. No interrupt is pending.

INTID

Interrupt identification.
IER[3:1] identifies an interrupt corresponding to the
USART Rx FIFO. All other combinations of IER[3:1] not
listed below are reserved (100,101,111).
0x3

RLS. Priority 1 (highest). (Highest) Receive Line Status
(RLS).

0x2

RDA. Priority 2 - Receive Data Available (RDA).

0x6

CTI. Priority 2 - Character Time-out Indicator (CTI).

0x1

THRE. Priority 3 - THRE Interrupt.

0x0

0

Reserved. Priority 4 (lowest) - Reserved.

5:4

-

7:6

FIFOENABLE

Copies of FCR[0].

8

ABEOINT

End of auto-baud interrupt.
0
True if auto-baud has finished successfully and interrupt is
enabled.

9

ABTOINT

Auto-baud time-out interrupt.
True if auto-baud has timed out and interrupt is enabled.

31:10 -

Reserved, user software should not write ones to reserved NA
bits. The value read from a reserved bit is not defined.
0

0

Reserved, user software should not write ones to reserved NA
bits. The value read from a reserved bit is not defined.

Bits IIR[9:8] are set by the auto-baud function and signal a time-out or end of auto-baud
condition. The auto-baud interrupt conditions are cleared by setting the corresponding
Clear bits in the Auto-baud Control Register.

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If the IntStatus bit is one and no interrupt is pending and the IntId bits will be zero. If the
IntStatus is 0, a non auto-baud interrupt is pending in which case the IntId bits identify the
type of interrupt and handling as described in Table 930. Given the status of IIR[3:0], an
interrupt handler routine can determine the cause of the interrupt and how to clear the
active interrupt. The IIR must be read in order to clear the interrupt prior to exiting the
Interrupt Service Routine.
The USART RLS interrupt (IIR[3:1] = 011) is the highest priority interrupt and is set
whenever any one of four error conditions occur on the USART RX input: overrun error
(OE), parity error (PE), framing error (FE) and break interrupt (BI). The USART Rx error
condition that set the interrupt can be observed via LSR[4:1]. The interrupt is cleared upon
a LSR read.
The USART RDA interrupt (IIR[3:1] = 010) shares the second level priority with the CTI
interrupt (IIR[3:1] = 110). The RDA is activated when the USART Rx FIFO reaches the
trigger level defined in FCR7:6 and is reset when the USART Rx FIFO depth falls below
the trigger level. When the RDA interrupt goes active, the CPU can read a block of data
defined by the trigger level.
The CTI interrupt (IIR[3:1] = 110) is a second level interrupt and is set when the USART
Rx FIFO contains at least one character and no USART Rx FIFO activity has occurred in
3.5 to 4.5 character times. Any USART Rx FIFO activity (read or write of USART RSR) will
clear the interrupt. This interrupt is intended to flush the USART RBR after a message has
been received that is not a multiple of the trigger level size. For example, if a peripheral
wished to send a 105 character message and the trigger level was 10 characters, the
CPU would receive 10 RDA interrupts resulting in the transfer of 100 characters and 1 to 5
CTI interrupts (depending on the service routine) resulting in the transfer of the remaining
5 characters.
Table 930. USART Interrupt Handling
IIR[3:0]
value[1]

Priority Interrupt
type

Interrupt source

0001

-

None

0110

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Highest RX Line
Status /
Error

OE[2]

Interrupt
reset

or

PE[2]

or

FE[2]

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BI[2]

LSR Read[2]

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Table 930. USART Interrupt Handling
IIR[3:0]
value[1]

Priority Interrupt
type

Interrupt source

Interrupt
reset

0100

Second RX Data
Available

Rx data available or trigger level reached in
FIFO (FCR0=1)

RBR
Read[3] or
USART
FIFO drops
below
trigger level

1100

Second Character Minimum of one character in the RX FIFO and
RBR
Time-out no character input or removed during a time
Read[3]
indication period depending on how many characters are
in FIFO and what the trigger level is set at (3.5 to
4.5 character times).
The exact time will be:
[(word length)  7 - 2]  8 + [(trigger level number of characters)  8 + 1] RCLKs

0010

Third

THRE

THRE[2]

IIR Read[4]
(if source of
interrupt) or
THR write

[1]

Values 0000, 0011, 010, 0111, 1000, 1001, 1010, 1011,1101, 1110,1111 are reserved.

[2]

For details see Section 40.6.8 “USART Line Status Register”

[3]

For details see Section 40.6.1 “USART Receiver Buffer Register”

[4]

For details see Section 40.6.5 “USART Interrupt Identification Register” and Section 40.6.2 “USART
Transmitter Holding Register”

The USART THRE interrupt (IIR[3:1] = 001) is a third level interrupt and is activated when
the USART THR FIFO is empty provided certain initialization conditions have been met.
These initialization conditions are intended to give the USART THR FIFO a chance to fill
up with data to eliminate many THRE interrupts from occurring at system start-up. The
initialization conditions implement a one character delay minus the stop bit whenever
THRE = 1 and there have not been at least two characters in the THR at one time since
the last THRE = 1 event. This delay is provided to give the CPU time to write data to THR
without a THRE interrupt to decode and service. A THRE interrupt is set immediately if the
USART THR FIFO has held two or more characters at one time and currently, the THR is
empty. The THRE interrupt is reset when a THR write occurs or a read of the IIR occurs
and the THRE is the highest interrupt (IIR[3:1] = 001).

40.6.6 USART FIFO Control Register
The FCR controls the operation of the USART RX and TX FIFOs.
Table 931. USART FIFO Control Register Write Only (FCR, addresses 0x4008 1008 (USART0), 0x400C 1008
(USART2), 0x400C 2008 (USART3)) bit description
Bit

Symbol

0

FIFOEN

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Value

Description

Reset
value

FIFO Enable.

0

0

Disabled. USART FIFOs are disabled. Must not be used in the application.

1

Enabled. Active high enable for both USART Rx and TX FIFOs and FCR[7:1]
access. This bit must be set for proper USART operation. Any transition on this bit
will automatically clear the USART FIFOs.
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Table 931. USART FIFO Control Register Write Only (FCR, addresses 0x4008 1008 (USART0), 0x400C 1008
(USART2), 0x400C 2008 (USART3)) bit description
Bit

Symbol

1

RXFIFORES

2

Value

Description

Reset
value

RX FIFO Reset.

0

0

No effect. No impact on either of USART FIFOs.

1

Clear. Writing a logic 1 to FCR[1] will clear all bytes in USART Rx FIFO, reset the
pointer logic. This bit is self-clearing.

0

No effect. No impact on either of USART FIFOs.

1

Clear. Writing a logic 1 to FCR[2] will clear all bytes in USART TX FIFO, reset the
pointer logic. This bit is self-clearing.

TXFIFORES

TX FIFO Reset.

0

3

DMAMODE

DMA Mode Select. When the FIFO enable bit (bit 0 of this register) is set, this bit
selects the DMA mode.

5:4

-

Reserved, user software should not write ones to reserved bits. The value read from NA
a reserved bit is not defined.

7:6

RXTRIGLVL

RX Trigger Level.
These two bits determine how many receiver USART FIFO characters must be
written before an interrupt is activated.

31:8 -

-

0x0

Level 0. Trigger level 0 (1 character or 0x01).

0x1

Level 1. Trigger level 1 (4 characters or 0x04).

0x2

Level 2. Trigger level 2 (8 characters or 0x08).

0x3

Level 3. Trigger level 3 (14 characters or 0x0E).
Reserved

0

0

-

40.6.6.1 DMA Operation
The user can optionally operate the USART transmit and/or receive using DMA. The DMA
mode is determined by the DMA Mode Select bit in the FCR register. Note that for DMA
operation as for any operation of the USART, the FIFOs must be enabled via the FIFO
Enable bit in the FCR register.
USART receiver DMA
In DMA mode, the receiver DMA request is asserted when the receiver FIFO level
becomes equal to or greater than trigger level, or if a character time-out occurs. See the
description of the RX Trigger Level above. The receiver DMA request is cleared by the
DMA controller.
USART transmitter DMA
In DMA mode, the transmitter DMA request is asserted when the transmitter FIFO
transitions to not full. The transmitter DMA request is cleared by the DMA controller.

40.6.7 USART Line Control Register
The LCR determines the format of the data character that is to be transmitted or received.

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Table 932. USART Line Control Register (LCR, addresses 0x4008 100C (USART0), 0x400C
100C (USART2), 0x400C 200C (USART3)) bit description
Bit

Symbol Value Description

Reset
Value

1:0

WLS

0

2

3

Word Length Select.
0x0

5-bit character length.

0x1

6-bit character length.

0x2

7-bit character length.

0x3

8-bit character length.

SBS

Stop Bit Select.
0

1 stop bit.

1

2 stop bits (1.5 if LCR[1:0]=00).

PE

Parity Enable
0

6

7

31:
8

Enable parity generation and checking.

PS

Parity Select.

0

0x0

Odd parity. Number of 1s in the transmitted character and the
attached parity bit will be odd.

0x1

Even Parity. Number of 1s in the transmitted character and the
attached parity bit will be even.

0x2

Force HIGH. Forced 1 stick parity.

0x3

Force LOW. Forced 0 stick parity.

BC

Break Control.

0

0

Disabled. Disable break transmission.

1

Enabled. Enable break transmission. Output pin USART TXD is
forced to logic 0 when LCR[6] is active high.

0

Disabled. Disable access to Divisor Latches.

1

Enabled. Enable access to Divisor Latches.

-

Reserved

DLAB

-

0

Disable parity generation and checking.

1
5:4

0

Divisor Latch Access Bit.

0

-

40.6.8 USART Line Status Register
The LSR is a Read Only register that provides status information on the USART TX and
RX blocks.
Table 933. USART Line Status Register Read Only (LSR, addresses 0x4008 1014 (USART0),
0x400C 1014 (USART2), 0x400C 2014 (USART3)) bit description
Bit Symbol

0

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Value

RDR

Description

Reset
Value

Receiver Data Ready.
LSR[0] is set when the RBR holds an unread character and is
cleared when the USART RBR FIFO is empty.

0

0

Empty. RBR is empty.

1

Data. RBR contains valid data.

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Table 933. USART Line Status Register Read Only (LSR, addresses 0x4008 1014 (USART0),
0x400C 1014 (USART2), 0x400C 2014 (USART3)) bit description …continued
Bit Symbol

1

2

Value

OE

Description

Reset
Value

Overrun Error.
0
The overrun error condition is set as soon as it occurs. A LSR
read clears LSR[1]. LSR[1] is set when USART RSR has a new
character assembled and the USART RBR FIFO is full. In this
case, the USART RBR FIFO will not be overwritten and the
character in the USART RSR will be lost.
0

Inactive. Overrun error status is inactive.

1

Active. Overrun error status is active.

PE

Parity Error.
When the parity bit of a received character is in the wrong
state, a parity error occurs. A LSR read clears LSR[2]. Time of
parity error detection is dependent on FCR[0].

0

Note: A parity error is associated with the character at the top
of the USART RBR FIFO.

3

0

Inactive. Parity error status is inactive.

1

Active. Parity error status is active.

FE

Framing Error.
0
When the stop bit of a received character is a logic 0, a framing
error occurs. A LSR read clears LSR[3]. The time of the
framing error detection is dependent on FCR0. Upon detection
of a framing error, the RX will attempt to re-synchronize to the
data and assume that the bad stop bit is actually an early start
bit. However, it cannot be assumed that the next received byte
will be correct even if there is no Framing Error.
Note: A framing error is associated with the character at the
top of the USART RBR FIFO.

4

0

Inactive. Framing error status is inactive.

1

Active. Framing error status is active.

BI

Break Interrupt.
When RXD1 is held in the spacing state (all zeros) for one full
character transmission (start, data, parity, stop), a break
interrupt occurs. Once the break condition has been detected,
the receiver goes idle until RXD1 goes to marking state (all
ones). A LSR read clears this status bit. The time of break
detection is dependent on FCR[0].

0

Note: The break interrupt is associated with the character at
the top of the USART RBR FIFO.

5

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0

Inactive. Break interrupt status is inactive.

1

Active. Break interrupt status is active.

THRE

Transmitter Holding Register Empty.
THRE is set immediately upon detection of an empty USART
THR and is cleared on a THR write.
0

Not empty. THR contains valid data.

1

Empty. THR is empty.

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Chapter 40: LPC43xx/LPC43Sxx USART0_2_3

Table 933. USART Line Status Register Read Only (LSR, addresses 0x4008 1014 (USART0),
0x400C 1014 (USART2), 0x400C 2014 (USART3)) bit description …continued
Bit Symbol

6

7

8

Value

TEMT

Reset
Value

Transmitter Empty.
TEMT is set when both THR and TSR are empty; TEMT is
cleared when either the TSR or the THR contain valid data.

1

0

Not empty. THR and/or the TSR contains valid data.

1

Empty. THR and the TSR are empty.

RXFE

Error in RX FIFO.
0
LSR[7] is set when a character with a RX error such as framing
error, parity error or break interrupt, is loaded into the RBR.
This bit is cleared when the LSR register is read and there are
no subsequent errors in the USART FIFO.
0

No error. RBR contains no USART RX errors or FCR[0]=0.

1

Error. USART RBR contains at least one USART RX error.

TXERR

31: 9

Description

Error in transmitted character.
A NACK response is given by the receiver in Smart card T=0
mode. This bit is cleared when the LSR register is read.

-

0

No error. No error (normal default condition).

1

NACK. A NACK response is received during Smart card T=0
operation.
Reserved

0

-

40.6.9 USART Scratch Pad Register
The SCR has no effect on the USART operation. This register can be written and/or read
at user’s discretion. There is no provision in the interrupt interface that would indicate to
the host that a read or write of the SCR has occurred.
Table 934. USART Scratch Pad Register (SCR, addresses 0x4008 101C (USART0), 0x400C
101C (USART2), 0x400C 201C (USART3)) bit description
Bit

Symbol Description

Reset Value

7:0

PAD

Scratch pad. A readable, writable byte.

0x00

31:8

-

Reserved

-

40.6.10 USART Auto-baud Control Register
The USART Auto-baud Control Register (ACR) controls the process of measuring the
incoming clock/data rate for the baud rate generation and can be read and written at
user’s discretion.

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Table 935. Autobaud Control Register (ACR, addresses 0x4008 1020 (USART0), 0x400C 1020
(USART2), 0x400C 2020 (USART3)) bit description
Bit

Symbol

0

START

1

2

Value

Description

Reset
value

Start bit.
This bit is automatically cleared after auto-baud
completion.

0

0

Stop. Auto-baud stop (auto-baud is not running).

1

Start. Auto-baud start (auto-baud is running).
Auto-baud run bit. This bit is automatically cleared
after auto-baud completion.

MODE

Auto-baud mode select bit.

0

0

Mode 0.

1

Mode 1.

0

No restart.

1

Restart. Restart in case of time-out (counter restarts
at next USART Rx falling edge)

AUTORESTART

Restart bit.

0

7:3

-

Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit is
not defined.

0

8

ABEOINTCLR

End of auto-baud interrupt clear bit (write-only).

0

9

0

No effect. Writing a 0 has no impact.

1

Clear. Writing a 1 will clear the corresponding
interrupt in the IIR.

ABTOINTCLR

Auto-baud time-out interrupt clear bit (write-only).

31:10 -

0

No effect. Writing a 0 has no impact.

1

Clear. Writing a 1 will clear the corresponding
interrupt in the IIR.
Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit is
not defined.

0

0

40.6.11 IrDA Control Register (USART3)
The IrDA Control Register enables and configures the IrDA mode for USART3 only. The
value of U3ICR should not be changed while transmitting or receiving data, or data loss or
corruption may occur.
Remark: IrDA is available on USART3 only.
Table 936. IrDA Control Register (ICR, address 0x4000 8024) bit description

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Bit

Symbol

0

IRDAEN

Value Description

Reset
value

IrDA mode enable.

0

0

Disabled. IrDA mode on USART3 is disabled, USART3
acts as a standard USART.

1

Enabled. IrDA mode on USART3 is enabled.

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Table 936. IrDA Control Register (ICR, address 0x4000 8024) bit description
Bit

Symbol

1

IRDAINV

2

5:3

Value Description

Serial input direction.

0

0

Not inverted. The serial input is not inverted.

1

Inverted. The serial input is inverted. This has no effect
on the serial output.

FIXPULSEEN

IrDA fixed pulse width mode.

0

0

Disabled. IrDA fixed pulse width mode disabled.

1

Enabled. IrDA fixed pulse width mode enabled.

PULSEDIV

31:6 -

Reset
value

Configures the pulse when FixPulseEn = 1. See
Table 937 for details.
NA

0

Reserved, user software should not write ones to
0
reserved bits. The value read from a reserved bit is not
defined.

The PulseDiv bits in U3ICR are used to select the pulse width when the fixed pulse width
mode is used in IrDA mode (IrDAEn = 1 and FixPulseEn = 1). The value of these bits
should be set so that the resulting pulse width is at least 1.63 µs. Table 937 shows the
possible pulse widths.
Table 937. IrDA Pulse Width
FixPulseEn

PulseDiv

IrDA Transmitter Pulse width (µs)

0

x

3 / (16  baud rate)

1

0

2  TPCLK

1

1

4  TPCLK

1

2

8  TPCLK

1

3

16  TPCLK

1

4

32  TPCLK

1

5

64  TPCLK

1

6

128  TPCLK

1

7

256  TPCLK

40.6.12 USART Fractional Divider Register
The USART Fractional Divider Register (FDR) controls the clock pre-scaler for the baud
rate generation and can be read and written at the user’s discretion. This pre-scaler takes
the APB clock and generates an output clock according to the specified fractional
requirements.
Important: If the fractional divider is active (DIVADDVAL > 0) and DLM = 0, the value of
the DLL register must be 3 or greater.

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Table 938. USART Fractional Divider Register (FDR, addresses 0x4008 1028 (USART0),
0x400C 1028 (USART2), 0x400C 2028 (USART3)) bit description
Bit

Function

Description

Reset
value

3:0

DIVADDVAL

Baud rate generation pre-scaler divisor value.
0
If this field is 0, fractional baud rate generator will not impact the
USART baud rate.

7:4

MULVAL

Baud rate pre-scaler multiplier value.
This field must be greater or equal 1 for USART to operate
properly, regardless of whether the fractional baud rate
generator is used or not.

1

31:8

-

Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.

0

This register controls the clock pre-scaler for the baud rate generation. The reset value of
the register keeps the fractional capabilities of USART disabled making sure that USART
is fully software and hardware compatible with USARTs not equipped with this feature.
The USART baud rate can be calculated as:
(6)
PCLK
UART baudrate = -----------------------------------------------------------------------------------------------------------------DivAddVal
16   256  DLM + DLL    1 + -----------------------------

MulVal 
Where USART_PCLK is the peripheral clock, DLM and DLL are the standard USART
baud rate divider registers, and DIVADDVAL and MULVAL are USART fractional baud
rate generator specific parameters.
The value of MULVAL and DIVADDVAL should comply to the following conditions:
1. 1 MULVAL  15
2. 0  DIVADDVAL  14
3. DIVADDVAL< MULVAL
The value of the FDR should not be modified while transmitting/receiving data or data may
be lost or corrupted.
If the FDR register value does not comply to these two requests, then the fractional divider
output is undefined. If DIVADDVAL is zero then the fractional divider is disabled, and the
clock will not be divided.

40.6.13 USART Oversampling Register
In most applications, the USART samples received data 16 times in each nominal bit time
and sends bits that are 16 input clocks wide. This register allows software to control the
ratio between the input clock and bit clock. Oversampling is required for smart card mode
and provides an alternative to fractional division for other modes.

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Table 939. USART Oversampling Register (OSR, addresses 0x4008 102C (USART0), 0x400C
102C (USART2), 0x400C 20402C (USART3)) bit description
Bit

Symbol

Description

Reset
value

0

-

Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.

NA

3:1

OSFRAC

Fractional part of the oversampling ratio, in units of 1/8th of an
input clock period. (001 = 0.125, ..., 111 = 0.875)

0

7:4

OSINT

Integer part of the oversampling ratio, minus 1. The reset values
equate to the normal operating mode of 16 input clocks per bit
time.

0xF

14:8

FDINT

In Smart Card mode, these bits act as a more-significant extension 0
of the OSint field, allowing an oversampling ratio up to 2048 as
required by ISO7816-3. In Smart Card mode, bits 14:4 should
initially be set to 371, yielding an oversampling ratio of 372.

31:15 -

Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.

NA

Example: For a baud rate of 3.25 Mbps with a 24 MHz USART clock frequency, the ideal
oversampling ratio is 24/3.25 or 7.3846. Setting OSINT to 0110 (binary) for 7 clocks/bit
and OSFrac to 011 (binary) for 0.375 clocks/bit, results in an oversampling ratio of 7.375.
In Smart card mode, OSInt is extended by FDINT. This extends the possible oversampling
to 2048, as required to support ISO 7816-3. Note that this value can be exceeded when
D<0, but this is not supported by the USART. When Smart card mode is enabled, the
initial value of OSINT and FDINT should be programmed as 00101110011 (binary) (372
minus one).

40.6.14 USART Half-duplex enable register
Remark: The HDEN register should be disabled when in smart card mode (smart card by
default runs in half-duplex mode).
After reset the USART will be in full-duplex mode, meaning that both TX and RX work
independently. After setting the HDEN bit, the USART will be in half-duplex mode. In this
mode, the USART ensures that the receiver is locked when idle, or will enter a locked
state after having received a complete ongoing character reception. Line conflicts must be
handled in software. The behavior of the USART is unpredictable when data is presented
for reception while data is being transmitted.
For this reason, the value of the HDEN register should not be modified while sending or
receiving data, or data may be lost or corrupted.

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Table 940. USART Half duplex enable register (HDEN, addresses 0x4008 1040 (USART0),
0x400C 1040 (USART2), 0x400C 2040 (USART3)) bit description
Bit

Symbol

0

HDEN

31:1

Value Description

Reset
value

Half-duplex mode enable
0

Disabled. Disable half-duplex mode.

1

Enabled. Enable half-duplex mode.

-

0

Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit is not
defined.

-

40.6.15 USART Smart card interface control register
Table 941. USART Smart card interface control register (SCICTRL, addresses 0x4008 1048
(USART0), 0x400C 1048 (USART2), 0x400C 2048 (USART3)) bit description
Bit

Symbol

0

SCIEN

1

2

Value Description

Reset
value

Smart Card Interface Enable.

0

0

Disabled. Smart card interface disabled.

1

Enabled. synchronous half duplex smart card interface
is enabled.

NACKDIS

NACK response disable. Only applicable in T=0.
0

Enabled. A NACK response is enabled.

1

Disabled. A NACK response is inhibited.

PROTSEL

0

Protocol selection as defined in the ISO7816-3 standard. 0
0

T=0

1

T=1

4:3

-

Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit is not
defined.

0

7:5

TXRETRY

Maximum number of retransmissions in case of a
negative acknowledge (protocol T=0). When the retry
counter is exceeded, the USART will be locked until the
FIFO is cleared. A TX error interrupt is generated when
enabled.

-

15:8

GUARDTIME

Extra guard time. No extra guard time (0x0) results in a
standard guard time as defined in ISO 7816-3,
depending on the protocol type. A guard time of 0xFF
indicates a minimal guard time as defined for the
selected protocol.

31:16

-

-

Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit is not
defined.

NA

After reset the USART smart card interface will be disabled. After setting the SCIEN bit
the USART will be in ISO 7816-3 compliant asynchronous smart card mode T=0.

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The NACKDIS bit is used to inhibit a nack response during T=0 (the I/O line is not pulled
low during the guard time to indicate an erroneous reception). The received character will
be stored in the RX FIFO but a parity error will be generated. It is up to the software to
handle the incorrect received character.
The PROTSEL bit is used to selected between the two supported smart card protocols
T=0 and T=1. More information on these protocols can be found in the ISO 7816-3
standard.
The retry bit field indicates the number of retransmission when receiving a NACK
response, which can be up to 7 trails. When the number is exceeded, an interrupt is
generated and the USART is locked until the FIFO is empty. This can be done by flushing
the FIFO. When no FIFO is available, or the FIFO is already empty, the interrupt can be
used by the software to determine the next action.
The guard time bit file is used to program the extra number of guard time cycles to allow
the smart card to process the information before sending a response. The extra guard
time can be programmed from 0 to 255, where 255 indicates the minimum possible
character length. This value is depending on the selected protocol and can be either 11
etu for protocol T=1 or 12 etu for protocol T=0.
Waiting times as defined in the standard cannot be programmed directly, but are
implemented using the capture inputs of the timers.
Remark: The SCICTRL register should not be modified while sending or receiving data,
or data may be lost or corrupted.
Remark: The SCICTRL register should not be enabled in combination with the
SYNCCTRL register, as only asynchronous smart card is supported.

40.6.16 USART RS485 Control register
The RS485CTRL register controls the configuration of the USART in RS-485/EIA-485
mode.
Table 942. USART RS485 Control register (RS485CTRL, addresses 0x4008 104C (USART0),
0x400C 104C (USART2), 0x400C 204C (USART3)) bit description
Bit

Symbol

0

NMMEN

1

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Value

Description

Reset
value

NMM enable.

0

0

Disabled. RS-485/EIA-485 Normal Multidrop
Mode (NMM) is disabled.

1

Enabled. RS-485/EIA-485 Normal Multidrop
Mode (NMM) is enabled. In this mode, an address
is detected when a received byte causes the
USART to set the parity error and generate an
interrupt.

RXDIS

Receiver enable.
0

Enabled. The receiver is enabled.

1

Disabled.The receiver is disabled.

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Table 942. USART RS485 Control register (RS485CTRL, addresses 0x4008 104C (USART0),
0x400C 104C (USART2), 0x400C 204C (USART3)) bit description …continued
Bit

Symbol

2

AADEN

3

-

4

DCTRL

5

Value

Description

Reset
value

AAD enable

0

0

Disabled. Auto Address Detect (AAD) is disabled.

1

Enabled. Auto Address Detect (AAD) is enabled.

-

Reserved.

-

Direction control for DIR pin.

0

0

Disabled. Disable Auto Direction Control.

1

Enabled. Enable Auto Direction Control.

OINV

Direction control pin polarity.
This bit reverses the polarity of the direction
control signal on the DIR pin.

31:6 -

0

0

Low. The direction control pin will be driven to
logic 0 when the transmitter has data to be sent. It
will be driven to logic 1 after the last bit of data
has been transmitted.

1

High. The direction control pin will be driven to
logic 1 when the transmitter has data to be sent. It
will be driven to logic 0 after the last bit of data
has been transmitted.

-

Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit
is not defined.

NA

After reset RS485 mode will be disabled. The RS485 feature allows the USART to be
configured as one of multiple addressable slave receivers controlled by a single USART.
In RS485 mode the USART differentiates between an address character and a data
character by means of a ninth bit. The parity bit is used to implement this bit, and when set
to ‘1’ indicates an address and when set to ‘0’ indicates data. RS485 mode is enabled by
setting the NMMEN bit. The USART slave receiver can be assigned a unique address
and, manually or automatically, reject or accept data based on a received address. See
section Section 40.7.4 for details.

40.6.17 USART RS485 Address Match register
The RS485ADRMATCH register contains the address match value for RS-485/EIA-485
mode.
Table 943. USART RS485 Address Match register (RS485ADRMATCH, addresses
0x4008 1050 (USART0), 0x400C 1050 (USART2), 0x400C 2050 (USART3)) bit
description
Bit

Symbol

Description

Reset value

7:0

ADRMATCH

Contains the address match value.

0x00

31:8

-

Reserved

-

The ADRMATCH bit field contains the slave address match value that is used to compare a
received address value to. During automatic address detection, this value is used to
accept or reject serial input data.

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Chapter 40: LPC43xx/LPC43Sxx USART0_2_3

40.6.18 USART RS485 Delay value register
The user may program the 8-bit RS485DLY register with a delay between the last stop bit
leaving the TXFIFO and the de-assertion of the DIR pin. This delay time is in periods of
the baud clock. Any delay time from 0 to 255 bit times may be programmed.
Table 944. USART RS485 Delay value register (RS485DLY, addresses 0x4008 1054 (USART0),
0x400C 1054 (USART2), 0x400C 2054 (USART3)) bit description
Bit

Symbol

Description

Reset value

7:0

DLY

Contains the direction control delay value. This register works in
conjunction with an 8-bit counter.

0x00

31:8

-

Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.

NA

40.6.19 USART Synchronous mode control register
SYNCCTRL register is a Read/write register that controls the synchronous mode. The
synchronous mode control module generates or receives the synchronous clock with the
serial input/ output data and distributes the edge detect samples to the transmit and
receive shift registers.
Table 945. USART Synchronous mode control registers (SYNCCTRL, address addresses
0x4008 1058 (USART0), 0x400C 1058 (USART2), 0x400C 2058 (USART3)) bit
description
Bit

Symbol

0

SYNC

1

2

3

4

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Value

Description

Reset
value

Enables synchronous mode.

0

0

Disabled.

1

Enabled.

CSRC

Clock source select.

0

0

Slave mode. Synchronous slave mode (SCLK in)

1

Master mode. Synchronous master mode (SCLK out)

FES

Edge sampling.

0

0

Rising. RxD is sampled on the rising edge of SCLK.

1

Falling. RxD is sampled on the falling edge of SCLK.

TSBYPASS

Transmit synchronization bypass in synchronous slave
mode.
0

Synchronized. The input clock is synchronized prior to
being used in clock edge detection logic.

1

Not synchronized. The input clock is not synchronized
prior to being used in clock edge detection logic. This
allows for a high er input clock rate at the expense of
potential metastability.

CSCEN

Continuous master clock enable (used only when
CSRC is 1)

0

0

On character. SCLK cycles only when characters are
being sent on TxD.

1

Continuously. SCLK runs continuously (characters can
be received on RxD independently from transmission on
TxD).

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Chapter 40: LPC43xx/LPC43Sxx USART0_2_3

Table 945. USART Synchronous mode control registers (SYNCCTRL, address addresses
0x4008 1058 (USART0), 0x400C 1058 (USART2), 0x400C 2058 (USART3)) bit
description
Bit

Symbol

5

SSSDIS

6

31:7

Value

Reset
value

Start/stop bits

0

0

Send. Send start and stop bits as in other modes.

1

Do not send. Do not send start/stop bits.

0

Software. CSCEN is under software control.

1

Hardware. Hardware clears CSCEN after each
character is received.

CCCLR

-

Description

Continuous clock clear

0

Reserved. The value read from a reserved bit is not
defined.

NA

After reset, synchronous mode is disabled. Synchronous mode allows the user to send
(synchronous master mode) or receive (synchronous slave mode) a clock with the serial
input and output data. Synchronous mode is enabled by setting the SYNC bit. The CSRC
bit can be used to switch between synchronous slave mode (logic 0) and synchronous
master mode (logic 1). The serial data can either be sampled on the rising edge (default)
or the falling edge of the serial clock. When the STARTSTOPDISABLE bit is set, the FES
bit is hardware overwritten to sample on the falling edge.
A master clock is only required to generate a clock when transmitting data. In this case,
data can only be received when data is transmitted. When the CSCEN bit is set, the clock
will always be running (during synchronous master mode only), allowing data to be
received continuously.
Note that this option should not be used in combination with STARTSTOPDISABLE
(during full-duplex communication). The continuous clock can be automatically stopped by
hardware after having received a complete character. This can be done by asserting the
CCCLR bit. This is useful in half-duplex mode, where the clock cannot be generated by
sending a character. After the reception of one character, the CSCEN bit is automatically
cleared by hardware. When another character needs to be received, the CSCEN should
be enabled again.
By default data transmission and reception performs the same in asynchronous mode and
synchronous mode. When the STARTSTOPDISABLE bit is set, no start and stop bits are
transmitted (nor are they received). This means that all bits that are send or received (a
clock is running) are data bits.
Remark: The value of the SYNCCTRL register should not be modified while
transmitting/receiving, data or data might get lost or corrupted.
Remark: The SYNCCTRL register should not be enabled in combination with the
SCICTRL register, as only asynchronous smart card is supported.

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40.6.20 USART Transmit Enable Register
In addition to being equipped with full hardware flow control (auto-cts and auto-rts
mechanisms described above), TER enables implementation of software flow control.
When TXEN = 1, USART transmitter will keep sending data as long as they are available.
As soon as TXEN becomes 0, USART transmission will stop.
Table 946 describes how to use TXEN bit in order to achieve software flow control.
Table 946. USART Transmit Enable Register (TER, addresses 0x4008 105C (USART0),
0x400C 105C (USART2), 0x400C 205C (USART3)) bit description
Bit

Symbol

Description

Reset value

0

TXEN

Transmit enable.
After reset transmission is enabled. When the TXEN bit is
de-asserted, no data will be transmitted although data may be
pending in the TSR or THR.

1

31:1 -

Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.

40.7 Functional description
40.7.1 Auto-baud
The USART auto-baud function can be used to measure the incoming baud rate based on
the ”AT" protocol (Hayes command). If enabled the auto-baud feature will measure the bit
time of the receive data stream and set the divisor latch registers DLM and DLL
accordingly.
Auto-baud is started by setting the ACR Start bit. Auto-baud can be stopped by clearing
the ACR Start bit. The Start bit will clear once auto-baud has finished and reading the bit
will return the status of auto-baud (pending/finished).
Two auto-baud measuring modes are available which can be selected by the ACR Mode
bit. In Mode 0 the baud rate is measured on two subsequent falling edges of the USART
Rx pin (the falling edge of the start bit and the falling edge of the least significant bit). In
Mode 1 the baud rate is measured between the falling edge and the subsequent rising
edge of the USART Rx pin (the length of the start bit).
The ACR AutoRestart bit can be used to automatically restart baud rate measurement if a
time-out occurs (the rate measurement counter overflows). If this bit is set, the rate
measurement will restart at the next falling edge of the USART Rx pin.
The auto-baud function can generate two interrupts.

• The IIR ABTOInt interrupt will get set if the interrupt is enabled (IER ABToIntEn is set
and the auto-baud rate measurement counter overflows).

• The IIR ABEOInt interrupt will get set if the interrupt is enabled (IER ABEOIntEn is set
and the auto-baud has completed successfully).
The auto-baud interrupts have to be cleared by setting the corresponding ACR
ABTOIntClr and ABEOIntEn bits.

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The fractional baud rate generator must be disabled (DIVADDVAL = 0) during auto-baud.
Also, when auto-baud is used, any write to DLM and DLL registers should be done before
ACR register write. The minimum and the maximum baud rates supported by USART are
function of USART_PCLK, number of data bits, stop bits and parity bits.
(7)

2  P CLK
PCLK
ratemin = -------------------------  UART baudrate  ------------------------------------------------------------------------------------------------------------ = ratemax
16  2 15

16   2 + databits + paritybits + stopbits 

40.7.2 Auto-baud modes
When the software is expecting an ”AT" command, it configures the USART with the
expected character format and sets the ACR Start bit. The initial values in the divisor
latches DLM and DLM don‘t care. Because of the ”A" or ”a" ASCII coding (”A" = 0x41,
”a" = 0x61), the USART Rx pin sensed start bit and the LSB of the expected character are
delimited by two falling edges. When the ACR Start bit is set, the auto-baud protocol will
execute the following phases:
1. On ACR Start bit setting, the baud rate measurement counter is reset and the USART
RSR is reset. The RSR baud rate is switched to the highest rate.
2. A falling edge on USART Rx pin triggers the beginning of the start bit. The rate
measuring counter will start counting USART_PCLK cycles.
3. During the receipt of the start bit, 16 pulses are generated on the RSR baud input with
the frequency of the USART input clock, guaranteeing the start bit is stored in the
RSR.
4. During the receipt of the start bit (and the character LSB for Mode = 0), the rate
counter will continue incrementing with the pre-scaled USART input clock
(USART_PCLK).
5. If Mode = 0, the rate counter will stop on next falling edge of the USART Rx pin. If
Mode = 1, the rate counter will stop on the next rising edge of the USART Rx pin.
6. The rate counter is loaded into DLM/DLL and the baud rate will be switched to normal
operation. After setting the DLM/DLL, the end of auto-baud interrupt IIR ABEOInt will
be set, if enabled. The RSR will now continue receiving the remaining bits of the ”A/a"
character.

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'A' (0x41) or 'a' (0x61)
start

bit0

bit1

bit2

bit3

bit4

bit5

bit6

bit7

parity stop

UARTn RX
start bit

LSB of 'A' or 'a'

U0ACR start
rate counter
16xbaud_rate

16 cycles

16 cycles

a. Mode 0 (start bit and LSB are used for auto-baud)
'A' (0x41) or 'a' (0x61)
start

bit0

bit1

bit2

bit3

bit4

bit5

bit6

bit7

parity stop

UARTn RX
start bit

LSB of 'A' or 'a'

U1ACR start
rate counter
16xbaud_rate

16 cycles

b. Mode 1 (only start bit is used for auto-baud)
Fig 128. Auto-baud a) mode 0 and b) mode 1 waveform

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40.7.3 Baud rate calculation in asynchronous mode
USART can operate with or without using the Fractional Divider. In real-life applications it
is likely that the desired baud rate can be achieved using several different Fractional
Divider settings. The following algorithm illustrates one way of finding a set of DLM, DLL,
MULVAL, and DIVADDVAL values. Such set of parameters yields a baud rate with a
relative error of less than 1.1% from the desired one.
The USART baud rate can be calculated as:
(8)
PCLK
UART baudrate = -----------------------------------------------------------------------------------------------------------------DivAddVal
16   256  DLM + DLL    1 + -----------------------------

MulVal 
Where USART_PCLK is the peripheral clock, DLM and DLL are the standard USART
baud rate divider registers, and DIVADDVAL and MULVAL are USART fractional baud
rate generator specific parameters.
The value of MULVAL and DIVADDVAL should comply to the following conditions:
1. 1 MULVAL  15
2. 0  DIVADDVAL  14
3. DIVADDVAL< MULVAL
The value of the FDR should not be modified while transmitting/receiving data or data may
be lost or corrupted.
If the FDR register value does not comply to these two requests, then the fractional divider
output is undefined. If DIVADDVAL is zero then the fractional divider is disabled, and the
clock will not be divided.

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Calculating UART
baudrate (BR)

PCLK,
BR

DL est = PCLK/(16 x BR)

DL est is an
integer?

True

False

DIVADDVAL = 0
MULVAL = 1

FR est = 1.5

Pick another FR est from
the range [1.1, 1.9]

DL est = Int(PCLK/(16 x BR x FR est))

FR est = PCLK/(16 x BR x DL est)

False
1.1 < FR est < 1.9?

True

DIVADDVAL = table(FR est )
MULVAL = table(FR est )

DLM = DL est [15:8]
DLL = DLest [7:0]

End

Fig 129. Algorithm for setting USART dividers

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Table 947. Fractional Divider setting look-up table
FR

DivAddVal/
MulVal

FR

DivAddVal/
MulVal

FR

DivAddVal/
MulVal

FR

DivAddVal/
MulVal

1.000

0/1

1.250

1/4

1.500

1/2

1.750

3/4

1.067

1/15

1.267

4/15

1.533

8/15

1.769

10/13

1.071

1/14

1.273

3/11

1.538

7/13

1.778

7/9

1.077

1/13

1.286

2/7

1.545

6/11

1.786

11/14

1.083

1/12

1.300

3/10

1.556

5/9

1.800

4/5

1.091

1/11

1.308

4/13

1.571

4/7

1.818

9/11

1.100

1/10

1.333

1/3

1.583

7/12

1.833

5/6

1.111

1/9

1.357

5/14

1.600

3/5

1.846

11/13

1.125

1/8

1.364

4/11

1.615

8/13

1.857

6/7

1.133

2/15

1.375

3/8

1.625

5/8

1.867

13/15

1.143

1/7

1.385

5/13

1.636

7/11

1.875

7/8

1.154

2/13

1.400

2/5

1.643

9/14

1.889

8/9

1.167

1/6

1.417

5/12

1.667

2/3

1.900

9/10

1.182

2/11

1.429

3/7

1.692

9/13

1.909

10/11

1.200

1/5

1.444

4/9

1.700

7/10

1.917

11/12

1.214

3/14

1.455

5/11

1.714

5/7

1.923

12/13

1.222

2/9

1.462

6/13

1.727

8/11

1.929

13/14

1.231

3/13

1.467

7/15

1.733

11/15

1.933

14/15

40.7.3.1 Example 1: USART_PCLK = 14.7456 MHz, BR = 9600
According to the provided algorithm DLest = PCLK/(16 x BR) = 14.7456 MHz / (16 x 9600)
= 96. Since this DLest is an integer number, DIVADDVAL = 0, MULVAL = 1, DLM = 0, and
DLL = 96.

40.7.3.2 Example 2: USART_PCLK = 12 MHz, BR = 115200
According to the provided algorithm DLest = PCLK/(16 x BR) = 12 MHz / (16 x 115200) =
6.51. This DLest is not an integer number and the next step is to estimate the FR
parameter. Using an initial estimate of FRest = 1.5 a new DLest = 4 is calculated and FRest
is recalculated as FRest = 1.628. Since FRest = 1.628 is within the specified range of 1.1
and 1.9, DIVADDVAL and MULVAL values can be obtained from the attached look-up
table.
The closest value for FRest = 1.628 in the look-up Table 947 is FR = 1.625. It is
equivalent to DIVADDVAL = 5 and MULVAL = 8.
Based on these findings, the suggested USART setup would be: DLM = 0, DLL = 4,
DIVADDVAL = 5, and MULVAL = 8. According to Equation 6, the USART’s baud rate is
115384. This rate has a relative error of 0.16% from the originally specified 115200.

40.7.4 RS-485/EIA-485 modes of operation
The RS-485/EIA-485 feature allows the USART to be configured as an addressable slave.
The addressable slave is one of multiple slaves controlled by a single master.

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The USART master transmitter will identify an address character by setting the parity (9th)
bit to ‘1’. For data characters, the parity bit is set to ‘0’.
Each USART slave receiver can be assigned a unique address. The slave can be
programmed to either manually or automatically reject data following an address which is
not theirs.
RS-485/EIA-485 Normal Multidrop Mode (NMM)
Setting the RS485CTRL bit 0 enables this mode. In this mode, an address is detected
when a received byte causes the USART to set the parity error and generate an interrupt.
If the receiver is disabled (RS485CTRL bit 1 = ‘1’), any received data bytes will be ignored
and will not be stored in the RXFIFO. When an address byte is detected (parity bit = ‘1’) it
will be placed into the RXFIFO and an Rx Data Ready Interrupt will be generated. The
processor can then read the address byte and decide whether or not to enable the
receiver to accept the following data.
While the receiver is enabled (RS485CTRL bit 1 =’0’), all received bytes will be accepted
and stored in the RXFIFO regardless of whether they are data or address. When an
address character is received a parity error interrupt will be generated and the processor
can decide whether or not to disable the receiver.
RS-485/EIA-485 Auto Address Detection (AAD) mode
When both RS485CTRL register bits 0 (9-bit mode enable) and 2 (AAD mode enable) are
set, the USART is in auto address detect mode.
In this mode, the receiver will compare any address byte received (parity = ‘1’) to the 8-bit
value programmed into the RS485ADRMATCH register.
If the receiver is disabled (RS485CTRL bit 1 = ‘1’), any received byte will be discarded if it
is either a data byte OR an address byte which fails to match the RS485ADRMATCH
value.
When a matching address character is detected it will be pushed onto the RXFIFO along
with the parity bit, and the receiver will be automatically enabled (RS485CTRL bit 1 will be
cleared by hardware). The receiver will also generate an Rx Data Ready Interrupt.
While the receiver is enabled (RS485CTRL bit 1 = ‘0’), all bytes received will be accepted
and stored in the RXFIFO until an address byte which does not match the
RS485ADRMATCH value is received. When this occurs, the receiver will be automatically
disabled in hardware (RS485CTRL bit 1 will be set), The received non-matching address
character will not be stored in the RXFIFO.
RS-485/EIA-485 Auto Direction Control
RS485/EIA-485 mode includes the option of allowing the transmitter to automatically
control the state of the DIR pin as a direction control output signal.
Setting RS485CTRL bit 4 = ‘1’ enables this feature.
When Auto Direction Control is enabled, the selected pin will be asserted (driven LOW)
when the CPU writes data into the TXFIFO. The pin will be de-asserted (driven HIGH)
once the last bit of data has been transmitted. See bits 4 and 5 in the RS485CTRL
register.
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The RS485CTRL bit 4 takes precedence over all other mechanisms controlling the
direction control pin.
RS485/EIA-485 driver delay time
The driver delay time is the delay between the last stop bit leaving the TXFIFO and the
de-assertion of the DIR pin. This delay time can be programmed in the 8-bit RS485DLY
register. The delay time is in periods of the baud clock. Any delay time from 0 to 255 bit
times may be used.
RS485/EIA-485 output inversion
The polarity of the direction control signal on the DIR pin can be reversed by programming
bit 5 in the RS485CTRL register. When this bit is set, the direction control pin will be
driven to logic 1 when the transmitter has data waiting to be sent. The direction control pin
will be driven to logic 0 after the last bit of data has been transmitted.

40.7.5 Synchronous mode
When the synchronous receiver/ transmitter feature is configured (USART), the serial
interface is extended with a serial input and output clock and an output enable for
controlling the clock pad.
By default transmission and reception in synchronous mode operates uses the same
protocol as in asynchronous mode. Synchronous mode can be configured using the
Synchronous Mode Control Register. This register allows to control:

•
•
•
•

The direction of the serial clock, i.e. synchronous slave or master mode
The sampling edge of the serial clock
Two-stage or one stage synchronization of the input serial clock during transmission
During synchronous master mode, the clock can be continuous or disabled when in
idle or break mode

• The transmission of start and stop bits can be omitted. Valid data is identified by a
running clock. Sampling is always done on the falling edge of the serial clock
Data is shifted in the receive shift register at the sampling edge of the serial clock.

40.7.5.1 USART clock in synchronous mode
In synchronous master mode, the USART synchronous clock is determined as follows:
(9)
BASE_UARTn_CLK
Un_UCLK = ---------------------------------------------------------------------------------------------------------------------DIVADDVAL
2   256  DLM + DLL    1 + -----------------------------------

MULVAL 
DLM and DLL are the standard USART0 baud rate divider registers, and DIVADDVAL and
MULVAL are USART0 fractional baud rate generator specific parameters. Setting
DIVADDVAL = 0 disables the fractional baud rate generator.

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40.7.5.2 Synchronous slave mode
This mode is enabled by setting the CSRC bit of the control register to ‘0’. During
synchronous slave mode, an external clock is required that clocks the serial input and
output data. Note that internally, the serial clock is treated as a data signal. Edge detection
on the serial clock is performed to synchronize the serial clock with the USART clock
domain, hence no registers are clocked with the serial clock.
Reception
By default the received character is similar to the character in asynchronous mode. The
serial data stream is kept HIGH when no data is available. During this time it is not
required for the external serial clock to be running. The first bit that will be received is the
start bit. During this time, the external serial clock must be running. The beginning of the
start bit can either be aligned with the rising edge of the serial clock (sampling on the
falling edge) or the falling edge (sampling on the rising edge), see the FES bit in
Table 945. When sampling on the rising edge, it is not required that the beginning of the
start bit is aligned with a clock edge (the clock may not have been running before). In this
case, the edge on the serial input data due to the start bit (logic 1 to 0) is used to
determine the start of the character.
The NOSTARTSTOPBITS bit of the Synchronous Mode Control register allows the user to
disable the transmission/ reception of the start and stop bits, improving the efficiency of
the USART. As a character is no longer identified by the start and stop bits, the serial clock
is used to determine the data bits. When the serial clock is running, all data that is
sampled is regarded as valid data.
In order to be able to identify the start of a character, the beginning of the character must
be aligned with the rising edge of the serial clock. For this reason, the FES bit of the
Synchronous Mode Control register is forced in hardware to ‘1’.
Directly after sampling the last bit, the character is stored in the receive FIFO.
Transmission
During synchronous slave mode, data can only be transmitted when the external serial
clock is running. Hence, when no start and stop bits are sent, transmission can only take
place when data is received from the master. When the start and stop bits are transmitted,
the external clock may only be detected after the first half of the received start bit
(sampling at the rising edge of the external serial clock). By using the edge created by the
received start bit (logic 1 to 0), it is made sure that the start bit of the character that is to be
transmitted by the slave is stable before this rising edge the external slave clock. In this
way it is ensured, that the master receives as many bits as it has transmitted.
When the first sample edge of the incoming serial clock samples a ‘1’ on the serial input
data (and start-stop bits are transmitted, thus the master has not initiated a transaction
yet), it is assumed that the master is running a continuous clock (instead of only running
the clock when sending data characters). The USART will not wait for a start bit from the
master, but will immediately start transmitting data when available. Note that in this
situation, the number of bits transmitted by the master and the number of bits transmitted
by the slave (received by the master) may not be aligned. It is assumed that a higher level
protocol ensures that complete characters are received when the master stops the clock.

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Transmission of data during synchronous slave mode is most time-critical. First the
external serial input clock must be detected using edge detection logic. Then, data needs
to be shifted out and be stable before the sampling edge of the external serial clock.
Remark: In this mode the u_clk period is allowed to be 4x the serial clock period.

40.7.5.3 Synchronous master mode
Synchronous master mode is enabled by setting the CSRC register bit to ‘1’. In this mode,
the external clock is generated internally by the baud-rate generation logic and is used to
clock the input and output serial data. The functionality of the baud-rate generation is
described in Section 40.7.3. Auto-baud is not supported during synchronous mode. The
1x baud rate clock is used to shift out the serial output data and to sample the serial input
data.
Synchronous master mode behaves similar to the slave mode, except that the serial input
data is not registered at the interface but is clocked in the USART clock domain at the
sampling edge of the serial clock.
During synchronous master mode, when start and stop bits are transmitted, the user can
enable the external clock continuously using cscen bit of the Synchronous Mode Control
register. This allows the connected slave to transmit data even when no data is
transmitted by the master itself.

40.7.6 Smart card mode
Figure 130 shows a typical asynchronous smart card application.

selectable
power rail
pull-up
resistor

pull-up
resistor

GPIO

pull-up
resistor
VCC

UCLK

Optional
Logic Level
Translation

LPCxxxx
TXD

CLK
I/O

ISO 7816
Smart Card

GPIO

RST

GPIO

Insertion Switch

Fig 130. Typical smart card application

When the SCIEN bit in the SCICTRL register (Table 941) is set as described above, the
USART provides bidirectional serial data on the open-drain TXD pin. No RXD pin is used
when SCIEN is 1. The USART UCLK pin will output synchronously with the data at the
data bit rate. Software must use timers to implement character and block waiting times (no
hardware support via trigger signals is provided on this part). GPIO pins can be used to
control the smart card reset and power pins. Any power supplied to the card must be
externally switched as card power supply requirements often exceed source currents
possible on this part. As the specific application may accommodate any of the available
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ISO 7816 class A, B, or C power requirements, be aware of the logic level tolerances and
requirements when communicating or powering cards that use different power rails than
this part.

40.7.6.1 Smart card set-up procedure
A T = 0 protocol transfer consists of 8-bits of data, an even parity bit, and two guard bits
that allow for the receiver of the particular transfer to flag parity errors through the NACK
response (see Figure 131). Extra guard bits may be added according to card
requirements. If no NACK is sent (provided the interface accepts them in SCICTRL), the
next byte may be transmitted immediately after the last guard bit. If the NACK is sent, the
transmitter will retry sending the byte until successfully received or until the SCICTRL
retry limit has been met.

Clock
Next transfer or
First retry

Asynchronous transfer
TXD

start

bit0

bit1

bit2

bit3

bit4

bit5

bit6

bit7

parity

NACK
extra extra
guard1 guard2
guard1 guard2

start

bit0

extra
guardn

Fig 131. Smart card T = 0 waveform

The smart card must be set up with the following considerations:
1. If necessary, bring the USART out of reset and enable clocking to the peripheral.
2. Setup an available USART TXD pin for the bidirectional transfers.
3. Set up the UCLK pin as the clock source using pin configuration registers. The default
clock requirement for most asynchronous cards is 372 times the bit rate.
4. Configure DLL and DLM for baud rate. It may not be necessary to target a specific
standard baud rate but rather to maintain a fraction of the previously mentioned clock
rate. For example if the clock rate is set to 4 MHz the baud rate would be 10753. A
clock rate of 3.5712 MHz would need a baud rate of 9600. An ISO 7816 PPS
exchange may require the baud rate to be changed later.
5. Configure LCR for character size and parity (typically 8-bit and even parity).
6. Configure SCICTRL with the desired NACK response, extra guard bits, and protocol
type.
7. Place the GPIO output signals into an inactive state where card power is off, RST is
low, and CLK is low and unchanging.
Thereafter, software should monitor card insertion, handle activation, wait for answer to
reset as described in ISO7816-3.

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41.1 How to read this chapter
The UART1 controller is available on all LPC43xx/LPC43Sxx parts.

41.2 Basic configuration
The UART1 is configured as follows:

•
•
•
•

See Table 948 for clocking and power control.
The UART1 is reset by the UART1_RST (reset #45).
The UART1 interrupt is connected to slot # 25 in the NVIC.
For connecting the UART1 receive and transmit lines to the GPDMA, use the
DMAMUX register in the CREG block (see Table 100) and enable the GPDMA
channel in the DMA Channel Configuration registers (Section 21.6.20).

Table 948. UART1 clocking and power control
Base clock

Branch clock

Operating
frequency

UART1 clock to register interface

BASE_M4_CLK

CLK_M4_UART1

up to 204 MHz

UART1 peripheral clock (PCLK)

BASE_UART1_CLK

CLK_APB0_UART1 up to 204 MHz

41.3 Features
•
•
•
•
•
•
•
•
•
•
•

Full modem control handshaking available.
Data sizes of 5, 6, 7, and 8 bits.
Parity generation and checking: odd, even mark, space or none.
One or two stop bits.
16 byte Receive and Transmit FIFOs.
Built-in baud rate generator, including a fractional rate divider for great versatility.
Supports DMA for both transmit and receive.
Auto-baud capability.
Break generation and detection.
Multiprocessor addressing mode.
RS-485 support.

41.4 General description
The architecture of the UART1 is shown below in the block diagram.
The APB interface provides a communications link between the CPU or host and the
UART1.
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The UART1 receiver block, RX, monitors the serial input line, RXD, for valid input. The
UART1 RX Shift Register (RSR) accepts valid characters via RXD. After a valid character
is assembled in the RSR, it is passed to the UART1 RX Buffer Register FIFO to await
access by the CPU or host via the generic host interface.
The UART1 transmitter block, TX, accepts data written by the CPU or host and buffers the
data in the UART1 TX Holding Register FIFO (THR). The UART1 TX Shift Register (TSR)
reads the data stored in the THR and assembles the data to transmit via the serial output
pin, TXD1.
The UART1 Baud Rate Generator block, BRG, generates the timing enables used by the
UART1 TX and RX blocks. The BRG clock input source is the APB clock (PCLK). The
main clock is divided down per the divisor specified in the DLL and DLM registers. This
divided down clock is a 16x oversample clock, NBAUDOUT.
The modem interface contains registers MCR and MSR. This interface is responsible for
handshaking between a modem peripheral and the UART1.
The interrupt interface contains registers IER and IIR. The interrupt interface receives
several one clock wide enables from the TX and RX blocks.
Status information from the TX and RX is stored in the LSR. Control information for the TX
and RX is stored in the LCR.

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Chapter 41: LPC43xx/LPC43Sxx UART1

Transmitter
Transmitter
Holding
Register

Transmitter
FIFO

Transmitter
Shift
Register

U1_TXD

Transmitter
DMA
Interface
TX_DMA_REQ
TX_DMA_CLR
Baud Rate Generator
Fractional
Main
Rate
Divider
Divider
(DLM, DLL)

PCLK

UART1 interrupt

FIFO Control
& Status

U1_CTS
U1_RTS
U1_DSR
U1_DTR
U1_DCD

Modem
Control
&
Status

Interrupt
Control &
Status
U1_OE

Line Control
& Status
RS485 &
Auto-baud

U1_RI
Receiver
Receiver
Buffer
Register

Receiver
FIFO

Receiver
Shift
Register

U1_RXD

Receiver
DMA
Interface
RX_DMA_REQ
RX_DMA_CLR

Fig 132.UART1 block diagram

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Chapter 41: LPC43xx/LPC43Sxx UART1

41.5 Pin description
Table 949: UART1 Pin description
Pin
function

Direction Description

U1_RXD

Input

Serial Input. Serial receive data.

U1_TXD

Output

Serial Output. Serial transmit data.

U1_CTS

Input

Clear To Send. Active low signal indicates if the external modem is ready to accept transmitted
data via TXD from the UART1. In normal operation of the modem interface (MCR[4] = 0), the
complement value of this signal is stored in MSR[4]. State change information is stored in MSR[0]
and is a source for a priority level 4 interrupt, if enabled (IER[3] = 1).

Clear to send. CTS is an asynchronous, active low modem status signal. Its condition can be
checked by reading bit 4 (CTS) of the modem status register. Bit 0 (DCTS) of the Modem Status
Register (MSR) indicates that CTS has changed states since the last read from the MSR. If the
modem status interrupt is enabled when CTS changes levels and the auto-cts mode is not enabled,
an interrupt is generated. CTS is also used in the auto-cts mode to control the transmitter.
U1_DCD

Input

Data Carrier Detect. Active low signal indicates if the external modem has established a
communication link with the UART1 and data may be exchanged. In normal operation of the
modem interface (MCR[4]=0), the complement value of this signal is stored in MSR[7]. State
change information is stored in MSR3 and is a source for a priority level 4 interrupt, if enabled
(IER[3] = 1).

U1_DSR

Input

Data Set Ready. Active low signal indicates if the external modem is ready to establish a
communications link with the UART1. In normal operation of the modem interface (MCR[4] = 0), the
complement value of this signal is stored in MSR[5]. State change information is stored in MSR[1]
and is a source for a priority level 4 interrupt, if enabled (IER[3] = 1).

U1_DTR

Output

Data Terminal Ready. Active low signal indicates that the UART1 is ready to establish connection
with external modem. The complement value of this signal is stored in MCR[0].

U1_RI

Input

Ring Indicator. Active low signal indicates that a telephone ringing signal has been detected by the
modem. In normal operation of the modem interface (MCR[4] = 0), the complement value of this
signal is stored in MSR[6]. State change information is stored in MSR[2] and is a source for a
priority level 4 interrupt, if enabled (IER[3] = 1).

U1_RTS

Output

Request To Send. Active low signal indicates that the UART1 would like to transmit data to the
external modem. The complement value of this signal is stored in MCR[1].

The DTR pin can also be used as an RS-485/EIA-485 output enable signal.

In auto-rts mode, RTS is used to control the transmitter FIFO threshold logic.
Request to send. RTS is an active low signal informing the modem or data set that the UART is
ready to receive data. RTS is set to the active (low) level by setting the RTS modem control register
bit and is set to the inactive (high) level either as a result of a system reset or during loop-back
mode operations or by clearing bit 1 (RTS) of the MCR. In the auto-rts mode, RTS is controlled by
the transmitter FIFO threshold logic.
The RTS pin can also be used as an RS-485/EIA-485 output enable signal.

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Chapter 41: LPC43xx/LPC43Sxx UART1

41.6 Register description
UART1 contains registers organized as shown in Table 950. The Divisor Latch Access Bit
(DLAB) is contained in LCR[7] and enables access to the Divisor Latches.
Reset value reflects the data stored in used bits only. It does not include the content of
reserved bits.
Table 950: Register overview: UART1 (base address 0x4008 2000)
Name

Access Address Description
offset

Reset
value

Reference

RBR

RO

0x000

Receiver Buffer Register. Contains the next received
character to be read. (DLAB=0)

NA

Table 951

THR

WO

0x000

Transmit Holding Register. The next character to be
transmitted is written here. (DLAB=0)

NA

Table 952

DLL

R/W

0x000

Divisor Latch LSB. Least significant byte of the baud rate 0x01
divisor value. The full divisor is used to generate a baud
rate from the fractional rate divider. (DLAB=1)

Table 953

DLM

R/W

0x004

Divisor Latch MSB. Most significant byte of the baud rate 0x00
divisor value. The full divisor is used to generate a baud
rate from the fractional rate divider.(DLAB=1)

Table 954

IER

R/W

0x004

Interrupt Enable Register. Contains individual interrupt
enable bits for the 7 potential UART1 interrupts.
(DLAB=0)

0x00

Table 955

IIR

RO

0x008

Interrupt ID Register. Identifies which interrupt(s) are
pending.

0x01

Table 956

FCR

WO

0x008

FIFO Control Register. Controls UART1 FIFO usage and 0x00
modes.

Table 958

LCR

R/W

0x00C

Line Control Register. Contains controls for frame
formatting and break generation.

0x00

Table 959

MCR

R/W

0x010

Modem Control Register. Contains controls for flow
control handshaking and loopback mode.

0x00

Table 960

LSR

RO

0x014

Line Status Register. Contains flags for transmit and
receive status, including line errors.

0x60

Table 961

MSR

RO

0x018

Modem Status Register. Contains handshake signal
status flags.

0x00

Table 962

SCR

R/W

0x01C

Scratch Pad Register. 8-bit temporary storage for
software.

0x00

Table 963

ACR

R/W

0x020

Auto-baud Control Register. Contains controls for the
auto-baud feature.

0x00

Table 964

FDR

R/W

0x028

Fractional Divider Register. Generates a clock input for
the baud rate divider.

0x10

Table 965

RS485CTRL

R/W

0x04C

RS-485/EIA-485 Control. Contains controls to configure
various aspects of RS-485/EIA-485 modes.

0x00

Table 966

RS485ADRMATCH

R/W

0x050

RS-485/EIA-485 address match. Contains the address
match value for RS-485/EIA-485 mode.

0x00

Table 967

RS485DLY

R/W

0x054

RS-485/EIA-485 direction control delay.

0x00

Table 968

TER

R/W

0x05C

Transmit Enable Register. Turns off UART transmitter for 0x01
use with software flow control.

Table 969

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41.6.1 UART1 Receiver Buffer Register (when DLAB = 0)
The RBR is the top byte of the UART1 RX FIFO. The top byte of the RX FIFO contains the
oldest character received and can be read via the bus interface. The LSB (bit 0)
represents the “oldest” received data bit. If the character received is less than 8 bits, the
unused MSBs are padded with zeroes.
The Divisor Latch Access Bit (DLAB) in LCR must be zero in order to access the RBR.
The RBR is always read-only.
Since PE, FE and BI bits correspond to the byte sitting on the top of the RBR FIFO (i.e.
the one that will be read in the next read from the RBR), the right approach for fetching the
valid pair of received byte and its status bits is first to read the content of the LSR register,
and then to read a byte from the RBR.
Table 951: UART1 Receiver Buffer Register when DLAB = 0 (RBR, address 0x4008 2000) bit description
Bit

Symbol Description

Reset value

7:0

RBR

Receiver Buffer.
Contains the oldest received byte in the UART1 RX FIFO.

undefined

31:8

-

Reserved, the value read from a reserved bit is not defined.

NA

41.6.2 UART1 Transmitter Holding Register (when DLAB = 0)
The write-only THR is the top byte of the UART1 TX FIFO. The top byte is the newest
character in the TX FIFO and can be written via the bus interface. The LSB represents the
first bit to transmit.
The Divisor Latch Access Bit (DLAB) in LCR must be zero in order to access the THR.
The THR is write-only.
Table 952: UART1 Transmitter Holding Register when DLAB = 0 (THR, address 0x4008 2000) bit description
Bit

Symbol Description

7:0

THR

Transmit Holding Register.
NA
Writing to the UART1 Transmit Holding Register causes the data to be stored in the UART1
transmit FIFO. The byte will be sent when it reaches the bottom of the FIFO and the
transmitter is available.

Reset value

31:8

-

Reserved, user software should not write ones to reserved bits.

NA

41.6.3 UART1 Divisor Latch LSB and MSB Registers (when DLAB = 1)
The UART1 Divisor Latch is part of the UART1 Baud Rate Generator and holds the value
used, along with the Fractional Divider, to divide the APB clock (PCLK) in order to produce
the baud rate clock, which must be 16x the desired baud rate. The DLL and DLM registers
together form a 16-bit divisor where DLL contains the lower 8 bits of the divisor and DLM
contains the higher 8 bits of the divisor. A 0x0000 value is treated like a 0x0001 value as
division by zero is not allowed.The Divisor Latch Access Bit (DLAB) in LCR must be one in
order to access the UART1 Divisor Latches. Details on how to select the right value for
DLL and DLM can be found later in this chapter, see Section 41.6.13.

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Table 953: UART1 Divisor Latch LSB Register when DLAB = 1 (DLL, address 0x4008 2000) bit description
Bit

Symbol Description

Reset value

7:0

DLLSB

Divisor Latch LSB.
The UART1 Divisor Latch LSB Register, along with the DLM register, determines the baud
rate of the UART1.

0x01

31:8

-

Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.

NA

Table 954: UART1 Divisor Latch MSB Register when DLAB = 1 (DLM, address 0x4008 2004) bit description
Bit

Symbol Description

Reset value

7:0

DLMSB

Divisor Latch MSB.
The UART1 Divisor Latch MSB Register, along with the DLL register, determines the baud
rate of the UART1.

0x00

31:8

-

Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.

NA

41.6.4 UART1 Interrupt Enable Register (when DLAB = 0)
The IER is used to enable the four UART1 interrupt sources.
Table 955: UART1 Interrupt Enable Register when DLAB = 0 (IER, address 0x4008 2004) bit description
Bit

Symbol

0

RBRIE

1

2

3

6:4

Value Description

RBR Interrupt Enable. Enables the Receive Data Available interrupt for UART1. It also
controls the Character Receive Time-out interrupt.
0

Disable. Disable the RDA interrupts.

1

Enable. Enable the RDA interrupts.

THREIE

THRE Interrupt Enable. Enables the THRE interrupt for UART1. The status of this
interrupt can be read from LSR[5].
0

Disable. Disable the THRE interrupts.

1

Enable. Enable the THRE interrupts.

RXIE
0

Disable. Disable the RX line status interrupts.

1

Enable. Enable the RX line status interrupts.

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Modem Status Interrupt Enable. Enables the modem interrupt. The status of this
interrupt can be read from MSR[3:0].
0

Disable. Disable the modem interrupt.

1

Enable. Enable the modem interrupt.

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0

0

Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.

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0

0

RX Line Interrupt Enable. Enables the UART1 RX line status interrupts. The status of
this interrupt can be read from LSR[4:1].

MSIE

-

Reset
value

NA

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Chapter 41: LPC43xx/LPC43Sxx UART1

Table 955: UART1 Interrupt Enable Register when DLAB = 0 (IER, address 0x4008 2004) bit description
Bit

Symbol

7

CTSIE

Value Description

Reset
value

CTS Interrupt Enable. If auto-cts mode is enabled this bit enables/disables the modem
status interrupt generation on a CTS1 signal transition. If auto-cts mode is disabled a
CTS1 transition will generate an interrupt if Modem Status Interrupt Enable (IER[3]) is
set.

0

In normal operation a CTS1 signal transition will generate a Modem Status Interrupt
unless the interrupt has been disabled by clearing the IER[3] bit in the IER register. In
auto-cts mode a transition on the CTS1 bit will trigger an interrupt only if both the IER[3]
and IER[7] bits are set.

8

0

Disable. Disable the CTS interrupt.

1

Enable. Enable the CTS interrupt.

ABEOIE

Enables the end of auto-baud interrupt.
0

Disable. Disable end of auto-baud Interrupt.

1
9

0

Enable. Enable end of auto-baud Interrupt.

ABTOIE

Enables the auto-baud time-out interrupt.
0

Disable. Disable auto-baud time-out Interrupt.

1

Enable. Enable auto-baud time-out Interrupt.

31:10 -

0

Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.

NA

41.6.5 UART1 Interrupt Identification Register
The IIR provides a status code that denotes the priority and source of a pending interrupt.
The interrupts are frozen during an IIR access. If an interrupt occurs during an IIR access,
the interrupt is recorded for the next IIR access.
Table 956: UART1 Interrupt Identification Register (IIR, address 0x4008 2008) bit description
Bit

Symbol

0

INTSTATUS

Value Description

Interrupt status. Note that IIR[0] is active low. The pending interrupt can be
determined by evaluating IIR[3:1].
0

1

Interrupt pending. At least one interrupt is pending.
1

3:1

Reset
value

INTID

Not pending. No interrupt is pending.
Interrupt identification. IER[3:1] identifies an interrupt corresponding to the UART1
Rx or TX FIFO. All other combinations of IER[3:1] not listed below are reserved
(100,101,111).

0x3

0

RLS. Priority 1 (highest). (Highest) Receive Line Status (RLS).

0x2

RDA. Priority 2 - Receive Data Available (RDA).

0x6

CTI. Priority 2 - Character Time-out Indicator (CTI).

0x1

THRE. Priority 3 - THRE Interrupt.

0x0

Reserved. Priority 4 (lowest) - Reserved.

5:4

-

Reserved, user software should not write ones to reserved bits. The value read from NA
a reserved bit is not defined.

7:6

FIFOENABLE

Copies of FCR[0].

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Chapter 41: LPC43xx/LPC43Sxx UART1

Table 956: UART1 Interrupt Identification Register (IIR, address 0x4008 2008) bit description
Bit

Symbol

Value Description

8

ABEOINT

End of auto-baud interrupt. True if auto-baud has finished successfully and interrupt 0
is enabled.

9

ABTOINT

Auto-baud time-out interrupt. True if auto-baud has timed out and interrupt is
enabled.

0

Reserved, the value read from a reserved bit is not defined.

NA

31:10 -

Reset
value

Bit IIR[9:8] are set by the auto-baud function and signal a time-out or end of auto-baud
condition. The auto-baud interrupt conditions are cleared by setting the corresponding
Clear bits in the Auto-baud Control Register.
If the IntStatus bit is 1 no interrupt is pending and the IntId bits will be zero. If the IntStatus
is 0, a non auto-baud interrupt is pending in which case the IntId bits identify the type of
interrupt and handling as described in Table 957. Given the status of IIR[3:0], an interrupt
handler routine can determine the cause of the interrupt and how to clear the active
interrupt. The IIR must be read in order to clear the interrupt prior to exiting the Interrupt
Service Routine.
The UART1 RLS interrupt (IIR[3:1] = 011) is the highest priority interrupt and is set
whenever any one of four error conditions occur on the UART1RX input: overrun error
(OE), parity error (PE), framing error (FE) and break interrupt (BI). The UART1 Rx error
condition that set the interrupt can be observed via LSR[4:1]. The interrupt is cleared upon
an LSR read.
The UART1 RDA interrupt (IIR[3:1] = 010) shares the second level priority with the CTI
interrupt (IIR[3:1] = 110). The RDA is activated when the UART1 Rx FIFO reaches the
trigger level defined in FCR7:6 and is reset when the UART1 Rx FIFO depth falls below
the trigger level. When the RDA interrupt goes active, the CPU can read a block of data
defined by the trigger level.
The CTI interrupt (IIR[3:1] = 110) is a second level interrupt and is set when the UART1
Rx FIFO contains at least one character and no UART1 Rx FIFO activity has occurred in
3.5 to 4.5 character times. Any UART1 Rx FIFO activity (read or write of UART1 RSR) will
clear the interrupt. This interrupt is intended to flush the UART1 RBR after a message has
been received that is not a multiple of the trigger level size. For example, if a peripheral
wished to send a 105 character message and the trigger level was 10 characters, the
CPU would receive 10 RDA interrupts resulting in the transfer of 100 characters and 1 to 5
CTI interrupts (depending on the service routine) resulting in the transfer of the remaining
5 characters.
Table 957: UART1 Interrupt Handling
IIR[3:0]
value[1]

Priority Interrupt
Type

Interrupt Source

Interrupt Reset

0001

-

None

-

0110

Highest RX Line
Status /
Error

OE[2] or PE[2] or FE[2] or BI[2]

LSR Read[2]

0100

Second RX Data
Available

Rx data available or trigger level reached in FIFO
(FCR0=1)

RBR Read[3] or UART1 FIFO
drops below trigger level

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Chapter 41: LPC43xx/LPC43Sxx UART1

Table 957: UART1 Interrupt Handling
IIR[3:0]
value[1]

Priority Interrupt
Type

Interrupt Source

Interrupt Reset

1100

Second Character Minimum of one character in the RX FIFO and no
RBR Read[3]
Time-out character input or removed during a time period depending
indication on how many characters are in FIFO and what the trigger
level is set at (3.5 to 4.5 character times).
The exact time will be:
[(word length)  7 - 2]  8 + [(trigger level - number of
characters)  8 + 1] RCLKs

0010

Third

THRE

THRE[2]

IIR Read[4] (if source of
interrupt) or THR write

0000

Fourth

Modem
Status

CTS or DSR or RI or DCD

MSR Read

[1]

Values "0000", “0011”, “0101”, “0111”, “1000”, “1001”, “1010”, “1011”,”1101”,”1110”,”1111” are reserved.

[2]

For details see Section 41.6.9 “UART1 Line Status Register”

[3]

For details see Section 41.6.1 “UART1 Receiver Buffer Register (when DLAB = 0)”

[4]

For details see Section 41.6.5 “UART1 Interrupt Identification Register” and Section 41.6.2 “UART1
Transmitter Holding Register (when DLAB = 0)”

The UART1 THRE interrupt (IIR[3:1] = 001) is a third level interrupt and is activated when
the UART1 THR FIFO is empty provided certain initialization conditions have been met.
These initialization conditions are intended to give the UART1 THR FIFO a chance to fill
up with data to eliminate many THRE interrupts from occurring at system start-up. The
initialization conditions implement a one character delay minus the stop bit whenever
THRE = 1 and there have not been at least two characters in the THR at one time since
the last THRE = 1 event. This delay is provided to give the CPU time to write data to THR
without a THRE interrupt to decode and service. A THRE interrupt is set immediately if the
UART1 THR FIFO has held two or more characters at one time and currently, the THR is
empty. The THRE interrupt is reset when a THR write occurs or a read of the IIR occurs
and the THRE is the highest interrupt (IIR[3:1] = 001).
It is the lowest priority interrupt and is activated whenever there is any state change on
modem inputs pins, DCD, DSR or CTS. In addition, a low to high transition on modem
input RI will generate a modem interrupt. The source of the modem interrupt can be
determined by examining MSR[3:0]. A MSR read will clear the modem interrupt.

41.6.6 UART1 FIFO Control Register
The write-only FCR controls the operation of the UART1 RX and TX FIFOs.
Table 958: UART1 FIFO Control Register (FCR, address 0x4008 2008) bit description
Bit

Symbol

0

FIFOEN

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Value

Description

Reset
value

FIFO enable.

0

0

Disabled. Must not be used in the application.

1

Enabled. Active high enable for both UART1 Rx and TX FIFOs and FCR[7:1]
access. This bit must be set for proper UART1 operation. Any transition on this
bit will automatically clear the UART1 FIFOs.

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Table 958: UART1 FIFO Control Register (FCR, address 0x4008 2008) bit description
Bit

Symbol

1

RXFIFORES

2

Value

Description

Reset
value

RX FIFO Reset.

0

0

No effect. No impact on either of UART1 FIFOs.

1

Clear. Writing a logic 1 to FCR[1] will clear all bytes in UART1 Rx FIFO, reset
the pointer logic. This bit is self-clearing.

TXFIFORES

TX FIFO Reset.

0

0

No effect. No impact on either of UART1 FIFOs.

1

Clear. Writing a logic 1 to FCR[2] will clear all bytes in UART1 TX FIFO, reset
the pointer logic. This bit is self-clearing.
0

3

DMAMODE

DMA Mode Select. When the FIFO enable bit (bit 0 of this register) is set, this
bit selects the DMA mode. See Section 41.6.6.1.

5:4

-

Reserved, user software should not write ones to reserved bits. The value read NA
from a reserved bit is not defined.

7:6

RXTRIGLVL

RX Trigger Level. These two bits determine how many receiver UART1 FIFO
characters must be written before an interrupt is activated.
0x0

Level 0. Trigger level 0 (1 character or 0x01).

0x1

Level 1. Trigger level 1 (4 characters or 0x04).

0x2

Level 2. Trigger level 2 (8 characters or 0x08).

0x3
31:8

-

0

Level 3. Trigger level 3 (14 characters or 0x0E).
Reserved, user software should not write ones to reserved bits.

NA

41.6.6.1 DMA Operation
The user can optionally operate the UART transmit and/or receive using DMA. The DMA
mode is determined by the DMA Mode Select bit in the FCR register. Note that for DMA
operation as for any operation of the UART, the FIFOs must be enabled via the FIFO
Enable bit in the FCR register.
UART receiver DMA
In DMA mode, the receiver DMA request is asserted on the event of the receiver FIFO
level becoming equal to or greater than trigger level, or if a character time-out occurs. See
the description of the RX Trigger Level above. The receiver DMA request is cleared by the
DMA controller.
UART transmitter DMA
In DMA mode, the transmitter DMA request is asserted on the event of the transmitter
FIFO transitioning to not full. The transmitter DMA request is cleared by the DMA
controller.

41.6.7 UART1 Line Control Register
The LCR determines the format of the data character that is to be transmitted or received.

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Table 959: UART1 Line Control Register (LCR, address 0x4008 200C) bit description
Bit

Symbol

1:0

WLS

Value Description

Word Length Select.
0x0

5-bit character length.

0x1

6-bit character length.

0x2

7-bit character length.

0x3
2

3

5:4

6

7

SBS

0

8-bit character length.
Stop Bit Select.

0

1 stop bit.

1

2 stop bits. (1.5 if LCR[1:0]=00).

PE

0

Parity Enable.

0

0

Disable parity generation and checking.

1

Enable parity generation and checking.

PS

Parity Select.

0

0x0

Odd parity. Number of 1s in the transmitted character and the attached
parity bit will be odd.

0x1

Even Parity. Number of 1s in the transmitted character and the attached
parity bit will be even.

0x2

Force HIGH. Forced 1 stick parity.

0x3

Force LOW. Forced 0 stick parity.

BC

Break Control.
Disabled. Disable break transmission.

1

Enabled. Enable break transmission. Output pin UART1 TXD is forced to
logic 0 when LCR[6] is active high.

DLAB

Divisor Latch Access Bit (DLAB)
1

-

0

0

0
31:8

Reset value

0

Disabled. Disable access to Divisor Latches.
Enabled. Enable access to Divisor Latches.
Reserved, user software should not write ones to reserved bits. The value NA
read from a reserved bit is not defined.

41.6.8 UART1 Modem Control Register
The MCR enables the modem loopback mode and controls the modem output signals.
Table 960: UART1 Modem Control Register (MCR, address 0x4008 2010) bit description
Bit

Symbol

Value Description

0

DTRCTRL

-

DTR Control.
0
Source for modem output pin, DTR. This bit reads as 0 when modem loopback mode
is active.

1

RTSCTRL

-

RTS Control.
0
Source for modem output pin RTS. This bit reads as 0 when modem loopback mode is
active.

3:2

-

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Reset
value

Reserved, user software should not write ones to reserved bits. The value read from a 0
reserved bit is not defined.

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Table 960: UART1 Modem Control Register (MCR, address 0x4008 2010) bit description
Bit

Symbol

4

LMS

Value Description

Reset
value

Loopback Mode Select.
0
The modem loopback mode provides a mechanism to perform diagnostic loopback
testing. Serial data from the transmitter is connected internally to serial input of the
receiver. Input pin, RXD1, has no effect on loopback and output pin, TXD1 is held in
marking state. The 4 modem inputs (CTS, DSR, RI and DCD) are disconnected
externally. Externally, the modem outputs (RTS, DTR) are set inactive. Internally, the 4
modem outputs are connected to the 4 modem inputs. As a result of these
connections, the upper 4 bits of the MSR will be driven by the lower 4 bits of the MCR
rather than the 4 modem inputs in normal mode. This permits modem status interrupts
to be generated in loopback mode by writing the lower 4 bits of MCR.
0

Disabled. Disable modem loopback mode.

1

Enabled. Enable modem loopback mode.

5

-

Reserved, user software should not write ones to reserved bits. The value read from a 0
reserved bit is not defined.

6

RTSEN

RTS enable.

7

31:8

0

0

Disabled. Disable auto-rts flow control.

1

Enabled. Enable auto-rts flow control.

CTSEN

CTS enable.

0

0

Disabled. Disable auto-cts flow control.

1

Enabled. Enable auto-cts flow control.

-

Reserved, user software should not write ones to reserved bits. The value read from a NA
reserved bit is not defined.

41.6.9 UART1 Line Status Register
The LSR is a read-only register that provides status information on the UART1 TX and RX
blocks.
Table 961: UART1 Line Status Register (LSR, address 0x4008 2014) bit description
Bit

Symbol

0

RDR

1

Value

User manual

Reset
value

Receiver Data Ready.
0
LSR[0] is set when the RBR holds an unread character and is cleared when the UART1
RBR FIFO is empty.
0

Empty. The UART1 receiver FIFO is empty.

1

Data. The UART1 receiver FIFO is not empty.

OE

UM10503

Description

Overrun Error.
0
The overrun error condition is set as soon as it occurs. An LSR read clears LSR[1].
LSR[1] is set when UART1 RSR has a new character assembled and the UART1 RBR
FIFO is full. In this case, the UART1 RBR FIFO will not be overwritten and the
character in the UART1 RSR will be lost.
0

Inactive. Overrun error status is inactive.

1

Active. Overrun error status is active.

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Table 961: UART1 Line Status Register (LSR, address 0x4008 2014) bit description
Bit

Symbol

2

PE

Value

Description

Reset
value

Parity Error.
When the parity bit of a received character is in the wrong state, a parity error occurs.
An LSR read clears LSR[2]. Time of parity error detection is dependent on FCR[0].

0

Note: A parity error is associated with the character at the top of the UART1 RBR
FIFO.

3

0

Inactive. Parity error status is inactive.

1

Active. Parity error status is active.
0
Framing Error.
When the stop bit of a received character is a logic 0, a framing error occurs. An LSR
read clears LSR[3]. The time of the framing error detection is dependent on FCR0.
Upon detection of a framing error, the RX will attempt to resynchronize to the data and
assume that the bad stop bit is actually an early start bit. However, it cannot be
assumed that the next received byte will be correct even if there is no Framing Error.

FE

Note: A framing error is associated with the character at the top of the UART1 RBR
FIFO.

4

0

Inactive. Framing error status is inactive.

1

Active. Framing error status is active.
0
Break Interrupt.
When RXD1 is held in the spacing state (all zeroes) for one full character transmission
(start, data, parity, stop), a break interrupt occurs. Once the break condition has been
detected, the receiver goes idle until RXD1 goes to marking state (all ones). An LSR
read clears this status bit. The time of break detection is dependent on FCR[0].

BI

Note: The break interrupt is associated with the character at the top of the UART1 RBR
FIFO.

5

6

7

31:8

0

Break interrupt status is inactive.

1

Break interrupt status is active.

THRE

Transmitter Holding Register Empty.
THRE is set immediately upon detection of an empty UART1 THR and is cleared on a
THR write.
0

Not empty. THR contains valid data.

1

Empty. THR is empty.

TEMT

Transmitter Empty.
TEMT is set when both THR and TSR are empty; TEMT is cleared when either the
TSR or the THR contain valid data.
0

Not empty. THR and/or the TSR contains valid data.

1

Empty. THR and the TSR are empty.

RXFE

-

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Error in RX FIFO.
LSR[7] is set when a character with a RX error such as framing error, parity error or
break interrupt, is loaded into the RBR. This bit is cleared when the LSR register is
read and there are no subsequent errors in the UART1 FIFO.
0

No error. RBR contains no UART1 RX errors or FCR[0]=0.

1

Error. UART1 RBR contains at least one UART1 RX error.
Reserved, the value read from a reserved bit is not defined.

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1

1

0

NA

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Chapter 41: LPC43xx/LPC43Sxx UART1

41.6.10 UART1 Modem Status Register
The MSR is a read-only register that provides status information on the modem input
signals. MSR[3:0] is cleared on MSR read. Note that modem signals have no direct effect
on UART1 operation, they facilitate software implementation of modem signal operations.
Table 962: UART1 Modem Status Register (MSR, address 0x4008 2018) bit description
Bit

Symbol

0

DCTS

1

Value Description

Delta CTS.
Set upon state change of input CTS. Cleared on an MSR read.
0

No change. No change detected on modem input, CTS.

1

State change. State change detected on modem input, CTS.

DDSR

Delta DSR.
Set upon state change of input DSR. Cleared on an MSR read.
0
1

2

3

Reset value

TERI

0

No change. No change detected on modem input, DSR.
State change. State change detected on modem input, DSR.
Trailing Edge RI.
Set upon low to high transition of input RI. Cleared on an MSR read.

0

No change. No change detected on modem input, RI.

1

Rising. Low-to-high transition detected on RI.

DDCD

0

0

Delta DCD. Set upon state change of input DCD. Cleared on an MSR read. 0
0

No change. No change detected on modem input, DCD.

1

State change. State change detected on modem input, DCD.

4

CTS

-

Clear To Send State. Complement of input signal CTS. This bit is
connected to MCR[1] in modem loopback mode.

0

5

DSR

-

Data Set Ready State. Complement of input signal DSR. This bit is
connected to MCR[0] in modem loopback mode.

0

6

RI

-

Ring Indicator State. Complement of input RI. This bit is connected to
MCR[2] in modem loopback mode.

0

7

DCD

-

Data Carrier Detect State. Complement of input DCD. This bit is connected 0
to MCR[3] in modem loopback mode.

31:8

-

-

Reserved, the value read from a reserved bit is not defined.

NA

41.6.11 UART1 Scratch Pad Register
The SCR has no effect on the UART1 operation. This register can be written and/or read
at user’s discretion. There is no provision in the interrupt interface that would indicate to
the host that a read or write of the SCR has occurred.
Table 963: UART1 Scratch Pad Register (SCR, address 0x4008 2014) bit description
Bit

Symbol Description

Reset value

7:0

Pad

Scratch pad. A readable, writable byte.

0x00

31:8

-

Reserved, the value read from a reserved bit is not defined.

NA

41.6.12 UART1 Auto-baud Control Register
The UART1 Auto-baud Control Register (ACR) controls the process of measuring the
incoming clock/data rate for the baud rate generation and can be read and written at
user’s discretion.
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Table 964: Autobaud Control Register (ACR, address 0x4008 2020) bit description
Bit

Symbol

0

START

1

Value

Start. Auto-baud start (auto-baud is running). Auto-baud run bit. This bit is
automatically cleared after auto-baud completion.
Auto-baud mode select bit.

ABEOINTCLR

9

Mode 1.
Auto-baud restart bit.

0

0

No restart

1

Restart. Restart in case of time-out (counter restarts at next UART1 Rx
falling edge)

-

Reserved, user software should not write ones to reserved bits. The value 0
read from a reserved bit is not defined.
End of auto-baud interrupt clear bit (write-only).

0

0

No effect. Writing a 0 has no impact.

1

Clear. Writing a 1 will clear the corresponding interrupt in the IIR.

ABTOINTCLR

Auto-baud time-out interrupt clear bit (write-only).
0

31:10 -

0

Mode 0.

1

8

0

1

AUTORESTART

-

Auto-baud start bit.
This bit is automatically cleared after auto-baud completion.
Stop. Auto-baud stop (auto-baud is not running).

MODE

7:3

Reset
value

0

0
2

Description

0

No effect. Writing a 0 has no impact.

1

Clear. Writing a 1 will clear the corresponding interrupt in the IIR.

-

Reserved, user software should not write ones to reserved bits. The value 0
read from a reserved bit is not defined.

41.6.13 UART1 Fractional Divider Register
The UART1 Fractional Divider Register (FDR) controls the clock pre-scaler for the baud
rate generation and can be read and written at the user’s discretion. This pre-scaler takes
the APB clock and generates an output clock according to the specified fractional
requirements.
Important: If the fractional divider is active (DIVADDVAL > 0) and DLM = 0, the value of
the DLL register must be greater than 2.
Table 965: UART1 Fractional Divider Register (FDR, address 0x4008 2028) bit description
Bit

Function

Description

Reset value

3:0

DIVADDVAL

Baud-rate generation pre-scaler divisor value. If this field is 0, 0
fractional baud-rate generator will not impact the UARTn
baudrate.

7:4

MULVAL

Baud-rate pre-scaler multiplier value. This field must be
greater or equal 1 for UARTn to operate properly, regardless
of whether the fractional baud-rate generator is used or not.

1

31:8

-

Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.

0

This register controls the clock pre-scaler for the baud rate generation. The reset value of
the register keeps the fractional capabilities of UART1 disabled making sure that UART1
is fully software and hardware compatible with UARTs not equipped with this feature.
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UART1 baud rate can be calculated as (n = 1):
(10)
PCLK
UART1 baudrate = -----------------------------------------------------------------------------------------------------------------DivAddVal
16   256  DLM + DLL    1 + -----------------------------

MulVal 
Where PCLK is the peripheral clock, DLM and DLL are the standard UART1 baud rate
divider registers, and DIVADDVAL and MULVAL are UART1 fractional baud rate generator
specific parameters.
The value of MULVAL and DIVADDVAL should comply to the following conditions:
1. 1  MULVAL  15
2. 0  DIVADDVAL  14
3. DIVADDVAL < MULVAL
The value of the FDR should not be modified while transmitting/receiving data or data may
be lost or corrupted.
If the FDR register value does not comply to these two requests, then the fractional divider
output is undefined. If DIVADDVAL is zero then the fractional divider is disabled, and the
clock will not be divided.

41.6.14 UART1 RS485 Control register
The RS485CTRL register controls the configuration of the UART in RS-485/EIA-485
mode.
Table 966: UART1 RS485 Control register (RS485CTRL - address 0x4008 204C) bit description
Bit

Symbol

0

NMMEN

1

2

3

Value Description

Disabled. RS-485/EIA-485 Normal Multidrop Mode (NMM) is disabled.

1

Enabled. RS-485/EIA-485 Normal Multidrop Mode (NMM) is enabled. In this mode,
an address is detected when a received byte causes the USART to set the parity
error and generate an interrupt.
Receive enable.

0

0

Enabled. The receiver is enabled.

1

Disabled.The receiver is disabled.

AADEN

Auto Address Detect enable.
0

Disabled. Auto Address Detect (AAD) is disabled.

1

Enabled. Auto Address Detect (AAD) is enabled.

SEL

User manual

0

0

RXDIS

UM10503

Reset value

Multidrop mode select.

0

Direction control.

0

0

RTS. If direction control is enabled (bit DCTRL = 1), pin RTS is used for direction
control.

1

DTR. If direction control is enabled (bit DCTRL = 1), pin DTR is used for direction
control.

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Table 966: UART1 RS485 Control register (RS485CTRL - address 0x4008 204C) bit description
Bit

Symbol

4

DCTRL

5

31:6

Value Description

Direction control enable.
0

Disabled. Disable Auto Direction Control.

1

Enabled. Enable Auto Direction Control.

OINV

-

Reset value

0

Polarity.
0
This bit reverses the polarity of the direction control signal on the RTS (or DTR) pin.
0

Low. The direction control pin will be driven to logic 0 when the transmitter has data
to be sent. It will be driven to logic 1 after the last bit of data has been transmitted.

1

High. The direction control pin will be driven to logic 1 when the transmitter has data
to be sent. It will be driven to logic 0 after the last bit of data has been transmitted.

-

Reserved, user software should not write ones to reserved bits. The value read
from a reserved bit is not defined.

NA

41.6.15 UART1 RS-485 Address Match register
The RS485ADRMATCH register contains the address match value for RS-485/EIA-485
mode.
Table 967. UART1 RS485 Address Match register (RS485ADRMATCH - address 0x4008 2050) bit description
Bit

Symbol

Description

Reset value

7:0

ADRMATCH

Contains the address match value.

0x00

31:8

-

Reserved, user software should not write ones to reserved bits. The value read from a NA
reserved bit is not defined.

41.6.16 UART1 RS-485 Delay value register
The user may program the 8-bit RS485DLY register with a delay between the last stop bit
leaving the TXFIFO and the de-assertion of RTS (or DTR). This delay time is in periods of
the baud clock. Any delay time from 0 to 255 bit times may be programmed.
Table 968. UART1 RS485 Delay value register (RS485DLY - address 0x4008 2054) bit description
Bit

Symbol

Description

Reset value

7:0

DLY

Contains the direction control (RTS or DTR) delay value. This register works in
conjunction with an 8-bit counter.

0x00

31:8

-

Reserved, user software should not write ones to reserved bits. The value read from a NA
reserved bit is not defined.

41.6.17 UART1 Transmit Enable Register
In addition to being equipped with full hardware flow control (auto-cts and auto-rts
mechanisms described above), TER enables implementation of software flow control, too.
When TXEN=1, UART1 transmitter will keep sending data as long as they are available.
As soon as TXEN becomes 0, UART1 transmission will stop.

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Chapter 41: LPC43xx/LPC43Sxx UART1

Table 969: UART1 Transmit Enable Register (TER - address 0x4008 205C) bit description
Bit

Symbol Description

Reset
value

0

TXEN

Transmit enable.
1
After reset transmission is enabled. When the TXEN bit is de-asserted,
no data will be transmitted although data may be pending in the TSR
or THR.

31:1

-

Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.

-

41.7 Functional description
41.7.1 Auto-flow control
If auto-RTS mode is enabled the UART1‘s receiver FIFO hardware controls the RTS1
output of the UART1. If the auto-CTS mode is enabled the UART1‘s TSR hardware will
only start transmitting if the CTS1 input signal is asserted.
41.7.1.1

Auto-RTS
The auto-RTS function is enabled by setting the RTSen bit. Auto-RTS data flow control
originates in the RBR module and is linked to the programmed receiver FIFO trigger level.
If auto-RTS is enabled, the data-flow is controlled as follows:
When the receiver FIFO level reaches the programmed trigger level, RTS1 is de-asserted
(to a high value). It is possible that the sending UART sends an additional byte after the
trigger level is reached (assuming the sending UART has another byte to send) because it
might not recognize the de-assertion of RTS1 until after it has begun sending the
additional byte. RTS1 is automatically reasserted (to a low value) once the receiver FIFO
has reached the previous trigger level. The re-assertion of RTS1 signals to the sending
UART to continue transmitting data.
If Auto-RTS mode is disabled, the RTSen bit controls the RTS1 output of the UART1. If
Auto-RTS mode is enabled, hardware controls the RTS1 output, and the actual value of
RTS1 will be copied in the RTS Control bit of the UART1. As long as Auto-RTS is enabled,
the value of the RTS Control bit is read-only for software.
Example: Suppose the UART1 operating in ‘550 mode has trigger level in FCR set to 0x2
then if Auto-RTS is enabled the UART1 will de-assert the RTS1 output as soon as the
receive FIFO contains 8 bytes (Table 958 on page 1162). The RTS1 output will be
reasserted as soon as the receive FIFO hits the previous trigger level: 4 bytes.

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Chapter 41: LPC43xx/LPC43Sxx UART1

~
~

UART1 Rx
byte N

stop

start

bits0..7

stop

N-1

N-2

start

bits0..7

stop

~
~

start

RTS1 pin

~
~~
~

UART1 Rx
FIFO read
UART1 Rx
FIFO level

N

N-1

N-2

M+2

M+1

M

M-1

~
~

N-1

Fig 133.Auto-RTS Functional Timing

41.7.1.2

Auto-CTS
The Auto-CTS function is enabled by setting the CTSen bit. If Auto-CTS is enabled the
transmitter circuitry in the TSR module checks CTS1 input before sending the next data
byte. When CTS1 is active (low), the transmitter sends the next byte. To stop the
transmitter from sending the following byte, CTS1 must be released before the middle of
the last stop bit that is currently being sent. In Auto-CTS mode a change of the CTS1
signal does not trigger a modem status interrupt unless the CTS Interrupt Enable bit is set,
Delta CTS bit in the MSR will be set though. Table 970 lists the conditions for generating a
Modem Status interrupt.

Table 970: Modem status interrupt generation
Enable Modem Status
Interrupt (ER[3])

CTSen
(MCR[7])

CTS Interrupt
Enable (IER[7])

Delta CTS
(MSR[0])

Delta DCD or Trailing Edge RI Modem Status
or Delta DSR (MSR[3] or
Interrupt
MSR[2] or MSR[1])

0

x

x

x

x

No

1

0

x

0

0

No

1

0

x

1

x

Yes

1

0

x

x

1

Yes

1

1

0

x

0

No

1

1

0

x

1

Yes

1

1

1

0

0

No

1

1

1

1

x

Yes

1

1

1

x

1

Yes

The auto-CTS function reduces interrupts to the host system. When flow control is
enabled, a CTS1 state change does not trigger host interrupts because the device
automatically controls its own transmitter. Without Auto-CTS, the transmitter sends any
data present in the transmit FIFO and a receiver overrun error can result. Figure 134
illustrates the Auto-CTS functional timing.

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~
~

UART1 TX
bits0..7

stop

start

bits0..7

stop

start

bits0..7

stop

~
~

start

~
~

Chapter 41: LPC43xx/LPC43Sxx UART1

~
~

CTS1 pin

Fig 134.Auto-CTS Functional Timing

While starting transmission of the initial character the CTS1 signal is asserted.
Transmission will stall as soon as the pending transmission has completed. The UART will
continue transmitting a 1 bit as long as CTS1 is de-asserted (high). As soon as CTS1 gets
de-asserted transmission resumes and a start bit is sent followed by the data bits of the
next character.

41.7.2 Auto-baud
See Section 40.7.1.

41.7.3 Auto-baud modes
See Section 40.7.2.

41.7.4 Baud rate calculation
See Section 40.7.3.

41.7.5 RS-485/EIA-485 modes of operation
See Section 40.7.4.

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42.1 How to read this chapter
The SSP0/1 controllers are available on all LPC43xx/LPC43Sxx parts.

42.2 Basic configuration
The SSP0/1 are configured as follows:

•
•
•
•

See Table 971 for clocking and power control.
The SSP0/1 are reset by the SSP0/1_RST (reset #50/51).
The SSP0/1 interrupts are connected to slots # 22/23 in the NVIC.
For connecting the SSP0/1 receive and transmit lines to the GPDMA, use the
DMAMUX register in the CREG block (see Table 100) and enable the GPDMA
channel in the DMA Channel Configuration registers (Section 21.6.20).

Table 971. SSP0/1 clocking and power control
Base clock

Branch clock

Operating
frequency

Clock to SSP0 register interface

BASE_M4_CLK

CLK_M4_SSP0

up to 204 MHz

SSP0 peripheral clock (PCLK)

BASE_SSP0_CLK

CLK_APB0_SSP0

up to 204 MHz

Clock to SSP1 register interface

BASE_M4_CLK

CLK_M4_SSP1

up to 204 MHz

SSP1 peripheral clock (PCLK)

BASE_SSP1_CLK

CLK_APB2_SSP1

up to 204 MHz

42.3 Features
• Compatible with Motorola SPI, 4-wire TI SSI, and National Semiconductor Microwire
buses.

•
•
•
•

Synchronous Serial Communication.
Supports master or slave operation.
Eight-frame FIFOs for both transmit and receive.
4-bit to 16-bit frame.

42.4 General description
The SSP is a Synchronous Serial Port (SSP) controller capable of operation on a SPI,
4-wire SSI, or Microwire bus. It can interact with multiple masters and slaves on the bus.
Only a single master and a single slave can communicate on the bus during a given data
transfer. Data transfers are in principle full duplex, with frames of 4 to 16 bits of data
flowing from the master to the slave and from the slave to the master. In practice it is often
the case that only one of these data flows carries meaningful data.
The LPC43xx has two Synchronous Serial Port controllers -- SSP0 and SSP1.

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42.5 Pin description
Table 972. SSP pin description
Pin
Name

Direction

Interface pin
name/function

Pin description

SPI

SSI

Microwire

SSP0/1_ I/O
SCK

SCK

CLK

SK

Serial Clock. SCK/CLK/SK is a clock signal used to synchronize the
transfer of data. It is driven by the master and received by the slave.
When the SPI interface is used, the clock is programmable to be
active-high or active-low, otherwise it is always active-high. SCK1 only
switches during a data transfer. Any other time, the SSPn interface
either holds it in its inactive state, or does not drive it (leaves it in
high-impedance state).

SSP0/1_ I/O
SSEL

SSEL FS

CS

Frame Sync/Slave Select. When the SSPn interface is a bus master,
it drives this signal to an active state before the start of serial data, and
then releases it to an inactive state after the serial data has been sent.
The active state of this signal can be high or low depending upon the
selected bus and mode. When the SSPn is a bus slave, this signal
qualifies the presence of data from the Master, according to the
protocol in use.

When there is just one bus master and one bus slave, the Frame Sync
or Slave Select signal from the Master can be connected directly to the
slave's corresponding input. When there is more than one slave on the
bus, further qualification of their Frame Select/Slave Select inputs will
typically be necessary to prevent more than one slave from responding
to a transfer.
SSP0/1_ I/O
MISO

MISO DR(M) SI(M)
DX(S) SO(S)

Master In Slave Out. The MISO signal transfers serial data from the
slave to the master. When the SSPn is a slave, serial data is output on
this signal. When the SSPn is a master, it clocks in serial data from this
signal. When the SSPn is a slave and is not selected by FS/SSEL, it
does not drive this signal (leaves it in high-impedance state).

SSP0/1_ I/O
MOSI

MOSI DX(M) SO(M)
DR(S) SI(S)

Master Out Slave In. The MOSI signal transfers serial data from the
master to the slave. When the SSPn is a master, it outputs serial data
on this signal. When the SSPn is a slave, it clocks in serial data from
this signal.

42.6 Register description
The register addresses of the SSP controllers are shown in Table 973 and Table 974.
Table 973. Register overview: SSP0 (base address 0x4008 3000)
Name

Access Address
offset

Description

Reset
value[1]

Reference

CR0

R/W

0x000

Control Register 0. Selects the serial clock rate, bus type,
and data size.

0

Table 975

CR1

R/W

0x004

Control Register 1. Selects master/slave and other modes.

0

Table 976

DR

R/W

0x008

Data Register. Writes fill the transmit FIFO, and reads
empty the receive FIFO.

0

Table 977

SR

RO

0x00C

Status Register

0x0000
0003

Table 978

CPSR

R/W

0x010

Clock Prescale Register

0

Table 979

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Table 973. Register overview: SSP0 (base address 0x4008 3000)
Name

Access Address
offset

Description

Reset
value[1]

Reference

IMSC

R/W

0x014

Interrupt Mask Set and Clear Register

0

Table 980

RIS

RO

0x018

Raw Interrupt Status Register

0x0000
0008

Table 981

MIS

RO

0x01C

Masked Interrupt Status Register

0

Table 982

ICR

WO

0x020

SSPICR Interrupt Clear Register

-

Table 983

DMACR

R/W

0x024

SSP0 DMA control register

0

Table 984

[1]

Reset value reflects the data stored in used bits only. It does not include reserved bits content.

Table 974. Register overview: SSP1 (base address 0x400C 5000)
Name

Access Address
offset

Description

Reset
value[1]

Reference

CR0

R/W

Control Register 0. Selects the serial clock rate, bus type,
and data size.

0

Table 975

CR1

R/W

0x004

Control Register 1. Selects master/slave and other modes.

0

Table 976

DR

R/W

0x008

Data Register. Writes fill the transmit FIFO, and reads empty 0
the receive FIFO.

Table 977

SR

RO

0x00C

Status Register

0x0000
0003

Table 978

CPSR

R/W

0x010

Clock Prescale Register

0

Table 979

IMSC

R/W

0x014

Interrupt Mask Set and Clear Register

0

Table 980

RIS

RO

0x018

Raw Interrupt Status Register

0x0000
0008

Table 981

MIS

RO

0x01C

Masked Interrupt Status Register

0

Table 982

ICR

R/W

0x020

SSPICR Interrupt Clear Register

-

Table 983

DMACR

R/W

0x024

SSP1 DMA control register

0

Table 984

[1]

0x000

Reset value reflects the data stored in used bits only. It does not include reserved bits content.

42.6.1 SSP Control Register 0
This register controls the basic operation of the SSP controller.

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Table 975: SSP Control Register 0 (CR0 - address 0x4008 3000 (SSP0), 0x400C 5000 (SSP1))
bit description
Bit

Symbol Value Description

Reset
value

3:0

DSS

0000

5:4

6

7

15:8

Data Size Select. This field controls the number of bits
transferred in each frame. Values 0000-0010 are not supported
and should not be used.
0x3

4-bit transfer

0x4

5-bit transfer

0x5

6-bit transfer

0x6

7-bit transfer

0x7

8-bit transfer

0x8

9-bit transfer

0x9

10-bit transfer

0xA

11-bit transfer

0xB

12-bit transfer

0xC

13-bit transfer

0xD

14-bit transfer

0xE

15-bit transfer

0xF

16-bit transfer

FRF

Frame Format.
0x0

SPI

0x1

TI

0x2

Microwire

0x3

This combination is not supported and should not be used.

CPOL

Clock Out Polarity. This bit is only used in SPI mode.

31:16 -

0

0

SSP controller maintains the bus clock low between frames.

1

SSP controller maintains the bus clock high between frames.

CPHA

SCR

00

Clock Out Phase. This bit is only used in SPI mode.

0

0

SSP controller captures serial data on the first clock transition of
the frame, that is, the transition away from the inter-frame state
of the clock line.

1

SSP controller captures serial data on the second clock transition
of the frame, that is, the transition back to the inter-frame state of
the clock line.
Serial Clock Rate. The number of prescaler-output clocks per bit 0x00
on the bus, minus one. Given that CPSDVSR is the prescale
divider, and the APB clock PCLK clocks the prescaler, the bit
frequency is PCLK / (CPSDVSR  [SCR+1]).
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.

NA

42.6.2 SSP Control Register 1
This register controls certain aspects of the operation of the SSP controller.

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Table 976: SSP Control Register 1 (CR1 - address 0x4008 3004 (SSP0), 0x400C 5004 (SSP1))
bit description
Bit

Symbol Value Description

Reset
value

0

LBM

0

1

2

Loop Back Mode.
0

Normal operation.

1

Loop back mode. Serial input is taken from the serial output
(MOSI or MISO) rather than the serial input pin (MISO or MOSI
respectively).

SSE

SSP Enable.

0

0

The SSP controller is disabled.

1

The SSP controller will interact with other devices on the serial
bus. Software should write the appropriate control information to
the other SSP registers and interrupt controller registers, before
setting this bit.

MS

Master/Slave Mode.This bit can only be written when the SSE bit 0
is 0.
0

The SSP controller acts as a master on the bus, driving the
SCLK, MOSI, and SSEL lines and receiving the MISO line.

1

The SSP controller acts as a slave on the bus, driving MISO line
and receiving SCLK, MOSI, and SSEL lines.

3

SOD

Slave Output Disable. This bit is relevant only in slave mode
0
(MS = 1). If it is 1, this blocks this SSP controller from driving the
transmit data line (MISO).

31:4

-

Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.

NA

42.6.3 SSP Data Register
Software can write data to be transmitted to this register, and read data that has been
received.
Table 977: SSP Data Register (DR - address 0x4008 3008 (SSP0), 0x400C 5008 (SSP1)) bit
description
Bit

Symbol Description

15:0

DATA

Reset
value

0x0000
Write: software can write data to be sent in a future frame to this
register whenever the TNF bit in the Status register is 1, indicating that
the Tx FIFO is not full. If the Tx FIFO was previously empty and the
SSP controller is not busy on the bus, transmission of the data will
begin immediately. Otherwise the data written to this register will be
sent as soon as all previous data has been sent (and received). If the
data length is less than 16 bits, software must right-justify the data
written to this register.
Read: software can read data from this register whenever the RNE bit
in the Status register is 1, indicating that the Rx FIFO is not empty.
When software reads this register, the SSP controller returns data from
the least recent frame in the Rx FIFO. If the data length is less than 16
bits, the data is right-justified in this field with higher order bits filled with
0s.

31:16 -

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42.6.4 SSP Status Register
This read-only register reflects the current status of the SSP controller.
Table 978: SSP Status Register (SR - address 0x4008 300C (SSP0), 0x400C 500C (SSP1)) bit
description
Bit

Symbol Description

Reset
value

0

TFE

Transmit FIFO Empty. This bit is 1 is the Transmit FIFO is empty, 0 if not. 1

1

TNF

Transmit FIFO Not Full. This bit is 0 if the Tx FIFO is full, 1 if not.

1

2

RNE

Receive FIFO Not Empty. This bit is 0 if the Receive FIFO is empty, 1 if
not.

0

3

RFF

Receive FIFO Full. This bit is 1 if the Receive FIFO is full, 0 if not.

0

4

BSY

Busy. This bit is 0 if the SSPn controller is idle, or 1 if it is currently
sending/receiving a frame and/or the Tx FIFO is not empty.

0

31:5

-

Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.

NA

42.6.5 SSP Clock Prescale Register
This register controls the factor by which the Prescaler divides the SSP peripheral clock
PCLK to yield the prescaler clock that is, in turn, divided by the SCR factor in SSPnCR0,
to determine the bit clock.
Table 979: SSP Clock Prescale Register (CPSR - address 0x4008 3010 (SSP0), 0x400C 5010
(SSP1)) bit description
Bit

Symbol

Description

Reset
value

7:0

CPSDVSR

This even value between 2 and 254, by which PCLK is divided to yield 0
the prescaler output clock. Bit 0 always reads as 0.

31:8

-

Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.

NA

Important: the SSPnCPSR value must be properly initialized or the SSP controller will not
be able to transmit data correctly.
In Slave mode, the SSP clock rate provided by the master must not exceed 1/12 of the
SSP peripheral clock. The content of the SSPnCPSR register is not relevant.
In master mode, CPSDVSRmin = 2 or larger (even numbers only).

42.6.6 SSP Interrupt Mask Set/Clear Register
This register controls whether each of the four possible interrupt conditions in the SSP
controller are enabled. Note that ARM uses the word “masked” in the opposite sense from
classic computer terminology, in which “masked” meant “disabled”. ARM uses the word
“masked” to mean “enabled”. To avoid confusion we will not use the word “masked”.

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Table 980: SSP Interrupt Mask Set/Clear register (IMSC - address 0x4008 3014 (SSP0),
0x400C 5014 (SSP1)) bit description
Bit

Symbol Description

Reset
value

0

RORIM

Software should set this bit to enable interrupt when a Receive Overrun 0
occurs, that is, when the Rx FIFO is full and another frame is completely
received. The ARM spec implies that the preceding frame data is
overwritten by the new frame data when this occurs.

1

RTIM

Software should set this bit to enable interrupt when a Receive Time-out 0
condition occurs. A Receive Time-out occurs when the Rx FIFO is not
empty, and no has not been read for a time-out period. The time-out
period is the same for master and slave modes and is determined by the
SSP bit rate: 32 bits at PCLK / (CPSDVSR  [SCR+1]).

2

RXIM

Software should set this bit to enable interrupt when the Rx FIFO is at
least half full.

0

3

TXIM

Software should set this bit to enable interrupt when the Tx FIFO is at
least half empty.

0

31:4

-

Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.

NA

42.6.7 SSP Raw Interrupt Status Register
This read-only register contains a 1 for each interrupt condition that is asserted,
regardless of whether or not the interrupt is enabled in the SSPnIMSC.
Table 981: SSP Raw Interrupt Status register (RIS - address 0x4008 3018 (SSP0), RIS 0x400C 5018 (SSP1)) bit description
Bit

Symbol

Description

Reset
value

0

RORRIS

This bit is 1 if another frame was completely received while the RxFIFO 0
was full. The ARM spec implies that the preceding frame data is
overwritten by the new frame data when this occurs.

1

RTRIS

This bit is 1 if the Rx FIFO is not empty, and has not been read for a
time-out period. The time-out period is the same for master and slave
modes and is determined by the SSP bit rate: 32 bits at PCLK /
(CPSDVSR  [SCR+1]).

0

2

RXRIS

This bit is 1 if the Rx FIFO is at least half full.

0

3

TXRIS

This bit is 1 if the Tx FIFO is at least half empty.

1

31:4

-

Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.

NA

42.6.8 SSP Masked Interrupt Status Register
This read-only register contains a 1 for each interrupt condition that is asserted and
enabled in the SSPnIMSC. When an SSP interrupt occurs, the interrupt service routine
should read this register to determine the cause(s) of the interrupt.

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Table 982: SSP Masked Interrupt Status register (MIS -address 0x4008 301C (SSP0),
0x400C 501C (SSP1)) bit description
Bit

Symbol

Description

Reset
value

0

RORMIS

This bit is 1 if another frame was completely received while the RxFIFO 0
was full, and this interrupt is enabled.

1

RTMIS

This bit is 1 if the Rx FIFO is not empty, has not been read for a
0
time-out period, and this interrupt is enabled. The time-out period is the
same for master and slave modes and is determined by the SSP bit
rate: 32 bits at PCLK / (CPSDVSR  [SCR+1]).

2

RXMIS

This bit is 1 if the Rx FIFO is at least half full, and this interrupt is
enabled.

0

3

TXMIS

This bit is 1 if the Tx FIFO is at least half empty, and this interrupt is
enabled.

0

31:4

-

Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.

NA

42.6.9 SSP Interrupt Clear Register
Software can write one or more one(s) to this write-only register, to clear the
corresponding interrupt condition(s) in the SSP controller. Note that the other two interrupt
conditions can be cleared by writing or reading the appropriate FIFO, or disabled by
clearing the corresponding bit in SSPnIMSC.
Table 983: SSP interrupt Clear Register (ICR - address 0x4008 3020 (SSP0), ICR 0x400C 5020 (SSP1)) bit description
Bit

Symbol

Description

Reset
value

0

RORIC

Writing a 1 to this bit clears the “frame was received when RxFIFO was
full” interrupt.

NA

1

RTIC

NA
Writing a 1 to this bit clears the Rx FIFO was not empty and has not
been read for a time-out period interrupt. The time-out period is the same
for master and slave modes and is determined by the SSP bit rate: 32
bits at PCLK / (CPSDVSR  [SCR+1]).

31:2

-

Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.

NA

42.6.10 SSP DMA Control Register
The SSPnDMACR register is the DMA control register. It is a read/write register.

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Table 984: SSP DMA Control Register (DMACR - address 0x4008 3024 (SSP0), 0x400C 5024
(SSP1)) bit description
Bit

Symbol

Description

Reset
value

0

RXDMAE

Receive DMA Enable. When this bit is set to one 1, DMA 0
for the receive FIFO is enabled, otherwise receive DMA is
disabled.

1

TXDMAE

Transmit DMA Enable. When this bit is set to one 1, DMA
for the transmit FIFO is enabled, otherwise transmit DMA
is disabled

31:2

-

Reserved, user software should not write ones to reserved NA
bits. The value read from a reserved bit is not defined.

0

42.7 Functional description
42.7.1 Texas Instruments synchronous serial frame format
Figure 135 shows the 4-wire Texas Instruments synchronous serial frame format
supported by the SSP module.

CLK
FS
DX/DR

MSB

LSB
4 to 16 bits

a. Single frame transfer

CLK
FS
DX/DR

MSB

LSB

MSB

4 to 16 bits

LSB
4 to 16 bits

b. Continuous/back-to-back frames transfer
Fig 135. Texas Instruments Synchronous Serial Frame Format: a) Single and b) Continuous/back-to-back Two
Frames Transfer

For device configured as a master in this mode, CLK and FS are forced LOW, and the
transmit data line DX is tri-stated whenever the SSP is idle. Once the bottom entry of the
transmit FIFO contains data, FS is pulsed HIGH for one CLK period. The value to be
transmitted is also transferred from the transmit FIFO to the serial shift register of the
transmit logic. On the next rising edge of CLK, the MSB of the 4-bit to 16-bit data frame is
shifted out on the DX pin. Likewise, the MSB of the received data is shifted onto the DR
pin by the off-chip serial slave device.
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Both the SSP and the off-chip serial slave device then clock each data bit into their serial
shifter on the falling edge of each CLK. The received data is transferred from the serial
shifter to the receive FIFO on the first rising edge of CLK after the LSB has been latched.

42.7.2 SPI frame format
The SPI interface is a four-wire interface where the SSEL signal behaves as a slave
select. The main feature of the SPI format is that the inactive state and phase of the SCK
signal are programmable through the CPOL and CPHA bits within the SSPCR0 control
register.

42.7.2.1 Clock Polarity (CPOL) and Phase (CPHA) control
When the CPOL clock polarity control bit is 0, it produces a steady state low value on the
SCK pin. If the CPOL clock polarity control bit is 1, a steady state high value is placed on
the CLK pin when data is not being transferred.
The CPHA control bit selects the clock edge that captures data and allows it to change
state. It has the most impact on the first bit transmitted by either allowing or not allowing a
clock transition before the first data capture edge. When the CPHA phase control bit is 0,
data is captured on the first clock edge transition. If the CPHA clock phase control bit is 1,
data is captured on the second clock edge transition.

42.7.2.2 SPI format with CPOL=0,CPHA=0
Single and continuous transmission signal sequences for SPI format with CPOL = 0,
CPHA = 0 are shown in Figure 136.

SCK
SSEL

MSB

MOSI
MISO

LSB

MSB

LSB

Q

4 to 16 bits

a. Single transfer with CPOL=0 and CPHA=0

SCK
SSEL

MOSI
MISO

MSB

LSB

MSB

LSB

MSB
Q

LSB

MSB

LSB

Q

4 to 16 bits

4 to 16 bits

b. Continuous transfer with CPOL=0 and CPHA=0
Fig 136. SPI frame format with CPOL=0 and CPHA=0 (a) Single and b) Continuous Transfer)

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In this configuration, during idle periods:

• The CLK signal is forced LOW.
• SSEL is forced HIGH.
• The transmit MOSI/MISO pad is in high impedance.
If the SSP is enabled and there is valid data within the transmit FIFO, the start of
transmission is signified by the SSEL master signal being driven LOW. This causes slave
data to be enabled onto the MISO input line of the master. Master’s MOSI is enabled.
One half SCK period later, valid master data is transferred to the MOSI pin. Now that both
the master and slave data have been set, the SCK master clock pin goes HIGH after one
further half SCK period.
The data is now captured on the rising and propagated on the falling edges of the SCK
signal.
In the case of a single word transmission, after all bits of the data word have been
transferred, the SSEL line is returned to its idle HIGH state one SCK period after the last
bit has been captured.
However, in the case of continuous back-to-back transmissions, the SSEL signal must be
pulsed HIGH between each data word transfer. This is because the slave select pin
freezes the data in its serial peripheral register and does not allow it to be altered if the
CPHA bit is logic zero. Therefore the master device must raise the SSEL pin of the slave
device between each data transfer to enable the serial peripheral data write. On
completion of the continuous transfer, the SSEL pin is returned to its idle state one SCK
period after the last bit has been captured.

42.7.2.3 SPI format with CPOL=0,CPHA=1
The transfer signal sequence for SPI format with CPOL = 0, CPHA = 1 is shown in
Figure 137, which covers both single and continuous transfers.

SCK
SSEL

MOSI
MISO

Q

MSB

LSB

MSB

LSB

Q

4 to 16 bits

Fig 137. SPI frame format with CPOL=0 and CPHA=1

In this configuration, during idle periods:

• The CLK signal is forced LOW.
• SSEL is forced HIGH.
• The transmit MOSI/MISO pad is in high impedance.

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If the SSP is enabled and there is valid data within the transmit FIFO, the start of
transmission is signified by the SSEL master signal being driven LOW. Master’s MOSI pin
is enabled. After a further one half SCK period, both master and slave valid data is
enabled onto their respective transmission lines. At the same time, the SCK is enabled
with a rising edge transition.
Data is then captured on the falling edges and propagated on the rising edges of the SCK
signal.
In the case of a single word transfer, after all bits have been transferred, the SSEL line is
returned to its idle HIGH state one SCK period after the last bit has been captured.
For continuous back-to-back transfers, the SSEL pin is held LOW between successive
data words and termination is the same as that of the single word transfer.

42.7.2.4 SPI format with CPOL = 1,CPHA = 0
Single and continuous transmission signal sequences for SPI format with CPOL=1,
CPHA=0 are shown in Figure 138.

SCK
SSEL

MSB

MOSI
MISO

LSB

MSB

LSB

Q

4 to 16 bits

a. Single transfer with CPOL=1 and CPHA=0
SCK
SSEL

MOSI
MISO

MSB

LSB

MSB

LSB

MSB
Q

LSB

MSB

LSB

Q

4 to 16 bits

4 to 16 bits

b. Continuous transfer with CPOL=1 and CPHA=0
Fig 138. SPI frame format with CPOL = 1 and CPHA = 0 (a) Single and b) Continuous Transfer)

In this configuration, during idle periods:

• The CLK signal is forced HIGH.
• SSEL is forced HIGH.
• The transmit MOSI/MISO pad is in high impedance.

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If the SSP is enabled and there is valid data within the transmit FIFO, the start of
transmission is signified by the SSEL master signal being driven LOW, which causes
slave data to be immediately transferred onto the MISO line of the master. Master’s MOSI
pin is enabled.
One half period later, valid master data is transferred to the MOSI line. Now that both the
master and slave data have been set, the SCK master clock pin becomes LOW after one
further half SCK period. This means that data is captured on the falling edges and be
propagated on the rising edges of the SCK signal.
In the case of a single word transmission, after all bits of the data word are transferred, the
SSEL line is returned to its idle HIGH state one SCK period after the last bit has been
captured.
However, in the case of continuous back-to-back transmissions, the SSEL signal must be
pulsed HIGH between each data word transfer. This is because the slave select pin
freezes the data in its serial peripheral register and does not allow it to be altered if the
CPHA bit is logic zero. Therefore the master device must raise the SSEL pin of the slave
device between each data transfer to enable the serial peripheral data write. On
completion of the continuous transfer, the SSEL pin is returned to its idle state one SCK
period after the last bit has been captured.

42.7.2.5 SPI format with CPOL = 1,CPHA = 1
The transfer signal sequence for SPI format with CPOL = 1, CPHA = 1 is shown in
Figure 139, which covers both single and continuous transfers.

SCK
SSEL

MOSI
MISO

Q

MSB

LSB

MSB

LSB

Q

4 to 16 bits

Fig 139. SPI Frame Format with CPOL = 1 and CPHA = 1

In this configuration, during idle periods:

• The CLK signal is forced HIGH.
• SSEL is forced HIGH.
• The transmit MOSI/MISO pad is in high impedance.
If the SSP is enabled and there is valid data within the transmit FIFO, the start of
transmission is signified by the SSEL master signal being driven LOW. Master’s MOSI is
enabled. After a further one half SCK period, both master and slave data are enabled onto
their respective transmission lines. At the same time, the SCK is enabled with a falling
edge transition. Data is then captured on the rising edges and propagated on the falling
edges of the SCK signal.

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After all bits have been transferred, in the case of a single word transmission, the SSEL
line is returned to its idle HIGH state one SCK period after the last bit has been captured.
For continuous back-to-back transmissions, the SSEL pins remains in its active LOW
state, until the final bit of the last word has been captured, and then returns to its idle state
as described above. In general, for continuous back-to-back transfers the SSEL pin is
held LOW between successive data words and termination is the same as that of the
single word transfer.

42.7.3 National Semiconductor Microwire frame format
Figure 140 shows the Microwire frame format for a single frame. Figure 141 shows the
same format when back-to-back frames are transmitted.

SK
CS

SO
SI

MSB

LSB

8-bit control
0 MSB

LSB

4 to 16 bits
output data

Fig 140. Microwire frame format (single transfer)

Microwire format is very similar to SPI format, except that transmission is half-duplex
instead of full-duplex, using a master-slave message passing technique. Each serial
transmission begins with an 8-bit control word that is transmitted from the SSP to the
off-chip slave device. During this transmission, no incoming data is received by the SSP.
After the message has been sent, the off-chip slave decodes it and, after waiting one
serial clock after the last bit of the 8-bit control message has been sent, responds with the
required data. The returned data is 4 to 16 bits in length, making the total frame length
anywhere from 13 to 25 bits.
In this configuration, during idle periods:

• The SK signal is forced LOW.
• CS is forced HIGH.
• The transmit data line SO is arbitrarily forced LOW.
A transmission is triggered by writing a control byte to the transmit FIFO.The falling edge
of CS causes the value contained in the bottom entry of the transmit FIFO to be
transferred to the serial shift register of the transmit logic, and the MSB of the 8-bit control
frame to be shifted out onto the SO pin. CS remains LOW for the duration of the frame
transmission. The SI pin remains tristated during this transmission.
The off-chip serial slave device latches each control bit into its serial shifter on the rising
edge of each SK. After the last bit is latched by the slave device, the control byte is
decoded during a one clock wait-state, and the slave responds by transmitting data back
to the SSP. Each bit is driven onto SI line on the falling edge of SK. The SSP in turn

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latches each bit on the rising edge of SK. At the end of the frame, for single transfers, the
CS signal is pulled HIGH one clock period after the last bit has been latched in the receive
serial shifter, that causes the data to be transferred to the receive FIFO.
Note: The off-chip slave device can tristate the receive line either on the falling edge of
SK after the LSB has been latched by the receive shiftier, or when the CS pin goes HIGH.
For continuous transfers, data transmission begins and ends in the same manner as a
single transfer. However, the CS line is continuously asserted (held LOW) and
transmission of data occurs back to back. The control byte of the next frame follows
directly after the LSB of the received data from the current frame. Each of the received
values is transferred from the receive shifter on the falling edge SK, after the LSB of the
frame has been latched into the SSP.

SK
CS
SO

LSB

MSB

LSB

8-bit control
SI

0 MSB

LSB

MSB

4 to 16 bits
output data

LSB

4 to 16 bits
output data

Fig 141. Microwire frame format (continuous transfers)

42.7.3.1 Setup and hold time requirements on CS with respect to SK in Microwire
mode
In the Microwire mode, the SSP slave samples the first bit of receive data on the rising
edge of SK after CS has gone LOW. Masters that drive a free-running SK must ensure
that the CS signal has sufficient setup and hold margins with respect to the rising edge of
SK.
Figure 142 illustrates these setup and hold time requirements. With respect to the SK
rising edge on which the first bit of receive data is to be sampled by the SSP slave, CS
must have a setup of at least two times the period of SK on which the SSP operates. With
respect to the SK rising edge previous to this edge, CS must have a hold of at least one
SK period.

t HOLD= tSK

tSETUP=2*tSK

SK
CS

SI

Fig 142. Microwire frame format setup and hold details

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43.1 How to read this chapter
The SPI controller is available on all LPC43xx/LPC43Sxx parts.

43.2 Basic configuration
The SPI is configured as follows:

• See Table 985 for clocking and power control.
• The SPI is reset by the SPI_RST (reset # 58).
• The SPI interrupt is connected to NVIV slot # 20 in the Cortex-M0 NVIC.
Table 985. SPI clocking and power control
Base clock

Branch clock

Operating
frequency

Clock to SPI; peripheral SPI
clock

BASE_SPI_CLK[1]

CLK_SPI

up to 204 MHz

Clock to the peripheral bus
controller

BASE_PERIPH_CLK

CLK_PERIPH_BUS

up to 204 MHz

Clock to the peripheral core
controller

BASE_PERIPH_CLK

BASE_PERIPH_CORE

up to 204 MHz

[1]

BASE_SPI_CLK  0.5 * BASE_M4_CLK (if interrupt goes to M4 or M0APP).
BASE_SPI_CLK  0.5 * BASE_PERIPH_CLK (if interrupt goes to M0SUB).

43.3 Features
•
•
•
•
•

Compliant with Serial Peripheral Interface (SPI) specification.
Synchronous, Serial, Full Duplex Communication.
SPI master or slave.
Maximum data bit rate of one eighth of the peripheral clock rate.
8 to 16 bits per transfer.

43.4 General description
SPI is a full duplex serial interface. It can handle multiple masters and slaves being
connected to a given bus. Only a single master and a single slave can communicate on
the interface during a given data transfer. During a data transfer the master always sends
8 to 16 bits of data to the slave, and the slave always sends a byte of data to the master.
The block diagram of the SPI solution implemented in SPI interface is shown in the
Figure 143.

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MOSI_IN
MOSI_OUT
MISO_IN
MISO_OUT
SPI SHIFT REGISTER

SPI CLOCK

SCK_IN
SCK_OUT
SS_IN

GENERATOR &
DETECTOR

SPI Interrupt

APB Bus

SPI REGISTER
INTERFACE

SPI STATE CONTROL

OUTPUT
ENABLE
LOGIC

SCK_OUT_EN
MOSI_OUT_EN
MISO_OUT_EN

Fig 143. SPI block diagram

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43.5 Pin description
Table 986. SPI pin description
Pin
Name

Type

Pin Description

SCK

Input/
Output

Serial Clock. The SPI clock signal (SCK) is used to synchronize the transfer of
data across the SPI interface. The SPI is always driven by the master and
received by the slave. The clock is programmable to be active high or active
low. The SPI is only active during a data transfer. Any other time, it is either in its
inactive state, or tri-stated.

SSEL

Input

Slave Select. The SPI slave select signal (SSEL) is an active low signal that
indicates which slave is currently selected to participate in a data transfer. Each
slave has its own unique slave select signal input. The SSEL must be low before
data transactions begin and normally stays low for the duration of the
transaction. If the SSEL signal goes high any time during a data transfer, the
transfer is considered to be aborted. In this event, the slave returns to idle, and
any data that was received is thrown away. There are no other indications of this
exception. This signal is not directly driven by the master. It could be driven by a
simple general purpose I/O under software control.
Remark: Note that this pin in an input pin only. The SPI in master mode cannot
drive the CS input on the slave. Any GPIO pin can be used for SPI chip select in
master mode.

MISO

Input/
Output

Master In Slave Out. The SPI Master In Slave Out signal (MISO) is a
unidirectional signal used to transfer serial data from an SPI slave to an SPI
master. When a device is a slave, serial data is output on this pin. When a
device is a master, serial data is input on this pin. When a slave device is not
selected, the slave drives the signal high-impedance.

MOSI

Input/
Output

Master Out Slave In. The SPI Master Out Slave In signal (MOSI) is a
unidirectional signal used to transfer serial data from an SPI master to an SPI
slave. When a device is a master, serial data is output on this pin. When a
device is a slave, serial data is input on this pin.

43.6 Register description
The SPI contains registers as shown in Table 987. All registers are byte, half word and
word accessible.
Table 987. Register overview: SPI (base address 0x4010 0000)

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Name

Access

Address
offset

Description

Reset
value[1]

CR

R/W

0x000

SPI Control Register. This register controls the
operation of the SPI.

0x00

SR

RO

0x004

SPI Status Register. This register shows the
status of the SPI.

0x00

DR

R/W

0x008

SPI Data Register. This bi-directional register
0x00
provides the transmit and receive data for the
SPI. Transmit data is provided to the SPI0 by
writing to this register. Data received by the SPI0
can be read from this register.

CCR

R/W

0x00C

SPI Clock Counter Register. This register
controls the frequency of a master’s SCK0.

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Table 987. Register overview: SPI (base address 0x4010 0000)
Name

Access

Address
offset

Description

Reset
value[1]

TCR

R/W

0x010

SPI Test Control register. For functional testing
only.

0x00

TSR

R/W

0x014

SPI Test Status register. For functional testing
only.

0x00

-

R/W

0x018

Reserved.

-

INT

R/W

0x01C

SPI Interrupt Flag. This register contains the
interrupt flag for the SPI interface.

0x00

[1]

Reset value reflects the data stored in used bits only. It does not include reserved bits content.

43.6.1 SPI Control Register
The SPCR register controls the operation of SPI through the configuration bits setting
shown in Table 988.
Table 988: SPI Control Register (CR - address 0x4010 0000) bit description
Bit

Symbol

Value Description

1:0

-

Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.

-

2

BITENABLE 0

The SPI controller sends and receives 8 bits of data per
transfer.

0

1
3

4

5

6

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CPHA

Reset
value

The SPI controller sends and receives the number of bits
selected by bits 11:8.
Clock phase control determines the relationship between
the data and the clock on SPI transfers, and controls when
a slave transfer is defined as starting and ending.

0

Data is sampled on the first clock edge of SCK. A transfer
starts and ends with activation and deactivation of the
SSEL signal.

1

Data is sampled on the second clock edge of the SCK. A
transfer starts with the first clock edge, and ends with the
last sampling edge when the SSEL signal is active.

CPOL

Clock polarity control.
0

SCK is active high.

1

SCK is active low.

MSTR

Master mode select.
0

The SPI operates in Slave mode.

1

The SPI operates in Master mode.

LSBF

0

0

0

LSB First controls which direction each byte is shifted when 0
transferred.
0

SPI data is transferred MSB (bit 7) first.

1

SPI data is transferred LSB (bit 0) first.

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Table 988: SPI Control Register (CR - address 0x4010 0000) bit description …continued
Bit

Symbol

7

SPIE

11:8

Value Description

Reset
value

Serial peripheral interrupt enable.

0

0

SPI interrupts are inhibited.

1

A hardware interrupt is generated each time the SPIF or
MODF bits are activated.

BITS

When bit 2 of this register is 1, this field controls the number 0000
of bits per transfer:
0x8

8 bits per transfer

0x9

9 bits per transfer

0xA

10 bits per transfer

0xB

11 bits per transfer

0xC

12 bits per transfer

0xD

13 bits per transfer

0xE

14 bits per transfer

0xF

15 bits per transfer

0x0

16 bits per transfer

31:12 -

Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.

NA

43.6.2 SPI Status Register
The SPSR register controls the operation of SPI as per the configuration bits setting
shown in Table 989.
Table 989: SPI Status Register (SR - address 0x4010 0004) bit description

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Bit

Symbol

Description

Reset
value

2:0

-

Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.

NA

3

ABRT

Slave abort. When 1, this bit indicates that a slave abort has occurred.
This bit is cleared by reading this register.

0

4

MODF

Mode fault. when 1, this bit indicates that a Mode fault error has
occurred. This bit is cleared by reading this register, then writing the
SPI0 control register.

0

5

ROVR

Read overrun. When 1, this bit indicates that a read overrun has
occurred. This bit is cleared by reading this register.

0

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Table 989: SPI Status Register (SR - address 0x4010 0004) bit description
Bit

Symbol

Description

Reset
value

6

WCOL

Write collision. When 1, this bit indicates that a write collision has
occurred. This bit is cleared by reading this register, then accessing the
SPI Data Register.

0

7

SPIF

SPI transfer complete flag. When 1, this bit indicates when a SPI data
transfer is complete. When a master, this bit is set at the end of the last
cycle of the transfer. When a slave, this bit is set on the last data
sampling edge of the SCK. This bit is cleared by first reading this
register, then accessing the SPI Data Register.

0

Note: this is not the SPI interrupt flag. This flag is found in the SPINT
register.

31:8

-

Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.

NA

43.6.3 SPI Data Register
This bi-directional data register provides the transmit and receive data for the SPI.
Transmit data is provided to the SPI by writing to this register. Data received by the SPI
can be read from this register. When used as a master, a write to this register will start an
SPI data transfer. Writes to this register will be blocked when a data transfer starts, or
when the SPIF status bit is set, and the SPI Status Register has not been read.
Table 990: SPI Data Register (DR - address 0x4010 0008) bit description
Bit

Symbol

Description

Reset
value

7:0

DATALOW

SPI Bi-directional data port.

0x00

15:8

DATAHIGH

If bit 2 of the SPCR is 1 and bits 11:8 are other than 1000, some or 0x00
all of these bits contain the additional transmit and receive bits.
When less than 16 bits are selected, the more significant among
these bits read as zeroes.

31:16 -

Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.

NA

43.6.4 SPI Clock Counter Register
This register controls the frequency of a master’s SCK. The register indicates the number
of SPI peripheral clock cycles that make up an SPI clock.
In Master mode, this register must be an even number greater than or equal to 8.
Violations of this can result in unpredictable behavior. The SPI SCK rate may be
calculated as: PCLK_SPI / SPCCR value.
In Slave mode, the SPI clock rate provided by the master must not exceed 1/8 of the SPI
peripheral clock. The content of the SPCCR register is not relevant.

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Table 991: SPI Clock Counter Register (CCR - address 0x4010 000C) bit description
Bit

Symbol

Description

Reset
value

7:0

COUNTER

SPI0 Clock counter setting.

0x00

31:8

-

Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.

NA

43.6.5 SPI Test Control Register
Note that the bits in this register are intended for functional verification only. This register
should not be used for normal operation.
Table 992: SPI Test Control Register (TCR - address 0x4010 0010) bit description
Bit

Symbol

Description

Reset
value

0

-

Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.

NA

7:1

TEST

SPI test mode. When 0, the SPI operates normally. When 1, SCK will
always be on, independent of master mode select and data availability
setting.

0

31:8

-

Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.

NA

43.6.6 SPI Test Status Register
Note: The bits in this register are intended for functional verification only. This register
should not be used for normal operation.
This register is a replication of the SPI Status Register. The difference between the
registers is that a read of this register will not start the sequence of events required to
clear these status bits. A write to this register will set an interrupt if the write data for the
respective bit is a 1.
Table 993: SPI Test Status Register (TSR - address 0x4010 0014) bit description
Bit

Symbol

Description

Reset
value

2:0

-

Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.

NA

3

ABRT

Slave abort.

0

4

MODF

Mode fault.

0

5

ROVR

Read overrun.

0

6

WCOL

Write collision.

0

7

SPIF

SPI transfer complete flag.

0

31:8

-

Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.

NA

43.6.7 SPI Interrupt Register
This register contains the interrupt flag for the SPI0 interface.

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Table 994: SPI Interrupt Register (INT - address 0x4010 001C) bit description
Bit

Symbol

Description

Reset
value

0

SPIF

SPI interrupt flag. Set by the SPI interface to generate an interrupt.
Cleared by writing a 1 to this bit.

0

Note: this bit will be set once when SPIE = 1 and at least one of SPIF
and WCOL bits is 1. However, only when the SPI Interrupt bit is set and
SPI0 Interrupt is enabled in the NVIC, SPI based interrupt can be
processed by interrupt handling software.

7:1

-

Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.

NA

31:8

-

Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.

NA

43.7 Functional description
43.7.1 SPI data transfers
Figure 144 is a timing diagram that illustrates the four different data transfer formats that
are available with the SPI port. This timing diagram illustrates a single 8-bit data transfer.
The first thing you should notice in this timing diagram is that it is divided into three
horizontal parts. The first part describes the SCK and SSEL signals. The second part
describes the MOSI and MISO signals when the Clock Phase control bit (CPHA) in the
SPI Control Register is 0. The third part describes the MOSI and MISO signals when the
CPHA variable is 1.
In the first part of the timing diagram, note two points. First, the SPI is illustrated with the
Clock Polarity control bit (CPOL) in the SPI Control Register set to both 0 and 1. The
second point to note is the activation and de-activation of the SSEL signal. When
CPHA = 0, the SSEL signal will always go inactive between data transfers. This is not
guaranteed when CPHA = 1 (the signal can remain active).

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SCK (CPOL = 0)

SCK (CPOL = 1)

SSEL

CPHA = 0

Cycle # CPHA = 0

1

2

3

4

5

6

7

8

MOSI (CPHA = 0)

BIT 1

BIT 2

BIT 3

BIT 4

BIT 5

BIT 6

BIT 7

BIT 8

MISO (CPHA = 0)

BIT 1

BIT 2

BIT 3

BIT 4

BIT 5

BIT 6

BIT 7

BIT 8

CPHA = 1

Cycle # CPHA = 1

1

2

3

4

5

6

7

8

MOSI (CPHA = 1)

BIT 1

BIT 2

BIT 3

BIT 4

BIT 5

BIT 6

BIT 7

BIT 8

MISO (CPHA = 1)

BIT 1

BIT 2

BIT 3

BIT 4

BIT 5

BIT 6

BIT 7

BIT 8

Fig 144. SPI data transfer format (CPHA = 0 and CPHA = 1)

The data and clock phase relationships are summarized in Table 995.
Table 995. SPI Data To Clock Phase Relationship
CPOL and CPHA
settings

When the first data bit is
driven

When all other data
bits are driven

When data is
sampled

CPOL = 0, CPHA = 0

Prior to first SCK rising edge

SCK falling edge

SCK rising edge

CPOL = 0, CPHA = 1

First SCK rising edge

SCK rising edge

SCK falling edge

CPOL = 1, CPHA = 0

Prior to first SCK falling edge

SCK rising edge

SCK falling edge

CPOL = 1, CPHA = 1

First SCK falling edge

SCK falling edge

SCK rising edge

The definition of when a transfer starts and stops is dependent on whether a device is a
master or a slave, and the setting of the CPHA variable.
When a device is a master, the start of a transfer is indicated by the master having a byte
of data that is ready to be transmitted. At this point, the master can activate the clock, and
begin the transfer. The transfer ends when the last clock cycle of the transfer is complete.
When a device is a slave and CPHA is set to 0, the transfer starts when the SSEL signal
goes active, and ends when SSEL goes inactive. When a device is a slave, and CPHA is
set to 1, the transfer starts on the first clock edge when the slave is selected, and ends on
the last clock edge where data is sampled.

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43.7.2 General information
There are five control and status registers for the SPI port. They are described in detail in
Section 43.6 “Register description” on page 1191.
The SPI Control Register (S0SPCR) contains a number of programmable bits used to
control the function of the SPI block. The settings for this register must be set up prior to a
given data transfer taking place.
The SPI Status Register (S0SPSR) contains read-only bits that are used to monitor the
status of the SPI interface, including normal functions, and exception conditions. The
primary purpose of this register is to detect completion of a data transfer. This is indicated
by the SPI Interrupt Flag (SPIF) in the S0SPINT register. The remaining bits in the register
are exception condition indicators. These exceptions will be described later in this section.
The SPI Data Register (S0SPDR) is used to provide the transmit and receive data bytes.
An internal shift register in the SPI block logic is used for the actual transmission and
reception of the serial data. Data is written to the SPI Data Register for the transmit case.
There is no buffer between the data register and the internal shift register. A write to the
data register goes directly into the internal shift register. Therefore, data should only be
written to this register when a transmit is not currently in progress. Read data is buffered.
When a transfer is complete, the receive data is transferred to a single byte data buffer,
where it is later read. A read of the SPI Data Register returns the value of the read data
buffer.
The SPI Clock Counter Register (S0SPCCR) controls the clock rate when the SPI block is
in master mode. This needs to be set prior to a transfer taking place, when the SPI block
is a master. This register has no function when the SPI block is a slave.
Prior to use, SPI configurations such as the master/slave settings, clock polarity, clock
rate, etc. must be set up in the SPI Control Register and SPI Clock Counter Register.
The I/Os for this implementation of SPI are standard CMOS I/Os. The open drain SPI
option is not implemented in this design. When a device is set up to be a slave, its I/Os are
only active when it is selected by the SSEL signal being active.

43.7.3 Master operation
The following sequence can be followed to set up the SPI prior to its first use as a master.
This is typically done during program initialization.
1. Set the SPI Clock Counter Register to the desired clock rate.
2. Set the SPI Control Register to the desired settings for master mode.
The following sequence describes how one should process a data transfer with the SPI
block when it is set up to be the master. This process assumes that any prior data transfer
has already completed.
1. Optionally, verify the SPI setup before starting the transfer.
2. Write the data to transmitted to the SPI Data Register. This write starts the SPI data
transfer.
3. Wait for the SPIF bit in the SPI Status Register to be set to 1. The SPIF bit will be set
after the last cycle of the SPI data transfer.
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4. Read the SPI Status Register.
5. Read the received data from the SPI Data Register (optional).
6. Go to step 2 if more data is to be transmitted.
Note: A read or write of the SPI Data Register is required in order to clear the SPIF status
bit. Therefore, if the optional read of the SPI Data Register does not take place, a write to
this register is required in order to clear the SPIF status bit.

43.7.4 Slave operation
The following sequence can be followed to set up the SPI prior to its first use as a slave.
This is typically done during program initialization.
1. Set the SPI Control Register to the desired settings for slave mode.
The following sequence describes how one should process a data transfer with the SPI
block when it is set up to be a slave. This process assumes that any prior data transfer
has already completed. It is required that the system clock driving the SPI logic be at least
8X faster than the SPI.
1. Optionally, verify the SPI setup before starting the transfer.
2. Write the data to transmitted to the SPI Data Register (optional). Note that this can
only be done when a slave SPI transfer is not in progress.
3. Wait for the SPIF bit in the SPI Status Register to be set to 1. The SPIF bit will be set
after the last sampling clock edge of the SPI data transfer.
4. Read the SPI Status Register.
5. Read the received data from the SPI Data Register (optional).
6. Go to step 2 if more data is to be transferred.
Note: A read or write of the SPI Data Register is required in order to clear the SPIF status
bit. Therefore, at least one of the optional reads or writes of the SPI Data Register must
take place, in order to clear the SPIF status bit.

43.7.5 Exception conditions
Read Overrun
A read overrun occurs when the SPI block internal read buffer contains data that has not
been read by the processor, and a new transfer has completed. The read buffer
containing valid data is indicated by the SPIF bit in the SPI Interrupt Register being active.
When a transfer completes, the SPI block needs to move the received data to the read
buffer. If the SPIF bit is active (the read buffer is full), the new receive data will be lost, and
the read overrun (ROVR) bit in the SPI Status Register will be activated.
Write Collision
As stated previously, there is no write buffer between the SPI block bus interface, and the
internal shift register. As a result, data must not be written to the SPI Data Register when
a SPI data transfer is currently in progress. The time frame where data cannot be written
to the SPI Data Register is from when the transfer starts, until after the SPI Status

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Register has been read when the SPIF status is active. If the SPI Data Register is written
in this time frame, the write data will be lost, and the write collision (WCOL) bit in the SPI
Status Register will be activated.
Mode Fault
If the SSEL signal goes active when the SPI block is a master, this indicates another
master has selected the device to be a slave. This condition is known as a mode fault.
When a mode fault is detected, the mode fault (MODF) bit in the SPI Status Register will
be activated, the SPI signal drivers will be de-activated, and the SPI mode will be changed
to be a slave.
If the SSEL function is assigned to its related pin in the relevant Pin Function Select
Register, the SSEL signal must always be inactive when the SPI controller is a master.
Slave Abort
A slave transfer is considered to be aborted if the SSEL signal goes inactive before the
transfer is complete. In the event of a slave abort, the transmit and receive data for the
transfer that was in progress are lost, and the slave abort (ABRT) bit in the SPI Status
Register will be activated.

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44.1 How to read this chapter
The I2S0/1 interfaces are available on all LPC43xx/LPC43Sxx parts.

44.2 Basic configuration
The I2S interface is configured as follows:

•
•
•
•
•
•

See Table 996 for clocking and power control.
The I2S0 is reset by the I2S0_RST (reset # 52).
The I2S1 is reset by the I2S1_RST (reset # 53).
The I2S0 interrupt is connected to slot # 28 in the NVIC.
The I2S1 interrupt is connected to slot # 29 in the NVIC.
For connecting the I2S receive and transmit lines to the GPDMA, use the DMAMUX
register in the CREG block (see Table 100) and enable the GPDMA channel in the
DMA Channel Configuration registers (Section 21.6.20).

• The I2S clock can be sourced directly from the CGU using the BASE_AUDIO_CLK.
See Table 104 for configuring the I2S clock inputs for the BASE_AUDIO_CLK.

• The I2S0/1 MWS signals
(I2S0_RX_MWS/I2S0_TX_MWS/IS1_RX_MWS/I2S1_TX_MWS) can be connected
to timer3 or the SCT through the GIMA (see Table 207).
Table 996. I2S clocking and power control

Clock to the I2S0 and I2S1 register
interface and I2S0/1 peripheral clock.

Base clock

Branch clock

Operating
frequency

BASE_APB1_CLK

CLK_APB1_I2S

up to
204 MHz

44.3 Features
The I2S bus provides a standard communication interface for digital audio applications.
The I2S bus specification defines a 3-wire serial bus, having one data, one clock, and one
word select signal. The basic I2S connection has one master, which is always the master,
and one slave. The I2S interface provides a separate transmit and receive channel, each
of which can operate as either a master or a slave.

• The I2S input can operate in both master and slave mode, independently of the I2S
output.

• The I2S output can operate in both master and slave mode, independently of the I2S
input.

• Capable of handling 8-bit, 16-bit, and 32-bit word sizes.
• Mono and stereo audio data supported.
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• Versatile clocking includes independent transmit and receive fractional rate
generators, and an ability to use a single clock input or output for a 4-wire mode.

• The sampling frequency (fs) can range (in practice) from 16 to 192 kHz (16, 22.05, 32,
44.1, 48, 96, or 192 kHz) for audio applications.

• Separate Master Clock outputs for both transmit and receive channels support a clock
up to 512 times the I2S sampling frequency.

• Word Select period in master mode is configurable (separately for I2S input and I2S
output).

• Two 8 word (32 byte) FIFO data buffers are provided, one for transmit and one for
receive.

• Generates interrupt requests when buffer levels cross a programmable boundary.
• Two DMA requests, controlled by programmable buffer levels. These are connected
to the General Purpose DMA block.

• Controls include reset, stop and mute options separately for I2S input and I2S output.

44.4 General description
The I2S performs serial data out via the transmit channel and serial data in via the receive
channel. These support the Inter IC Audio format for 8-bit, 16-bit and 32-bit audio data,
both for stereo and mono modes. Configuration, data access and control is performed by
a APB register set. Data streams are buffered by FIFOs with a depth of 8 words.
The I2S receive and transmit stage can operate independently in either slave or master
mode. In master mode, the I2S module supplies the SCK and WS signals. In slave mode,
the SCK and WS signals are provided by the external master.

• In master mode, word select is generated internally with a 9-bit counter. The ratio of
the SCK and WS signals can be programmed in the control register.

• In slave mode, word select is input from the relevant bus pin.
• When an I2S bus is active, the word select, receive clock and transmit clock signals
are sent continuously by the bus master, while data is sent continuously by the
transmitter.

• Disabling the I2S can be done with the stop or mute control bits separately for the
transmit and receive.

• The stop bit will disable accesses by the transmit channel or the receive channel to
the FIFOs and will place the transmit channel in mute mode.

• The mute control bit will place the transmit channel in mute mode. In mute mode, the
transmit channel FIFO operates normally, but the output is discarded and replaced by
zeroes. This bit does not affect the receive channel, data reception can occur
normally.

44.4.1 I2S connection schemes
I2S1 is automatically a slave to I2S0 if no external pins are selected for the I2S1 clock and
data lines.

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MCLK can be provided by a master or used by the master to create the I2S SCK. MCLK
can also be generated internally by the audio PLL through the CREG block (see
Table 104).

44.4.2 I2S connections to the GIMA
The Word Select (MWS) signal is generated by the I2S blocks in slave and master mode
to capture or generate data. MWS either originates either from the pin mux (SCU) in slave
mode (the I2S_WS signal) or is generated by the I2S block in master mode. The MWS
signal is then routed to the SCU (in master mode only) and to the GIMA where it can be
selected as input to Timer3 or the SCT. The MWS signal which is connected to the GIMA,
is divided by 128.

I2S

RX_WS/TX_WS
(slave mode)

SCU (PINMUX)

ws_sel
RX_MWS/TX_MWS

ws gen

/128

GIMA

rx capture

Fig 145. WS signal connections

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Chapter 44: LPC43xx/LPC43Sxx I2S interface

44.5 Pin description
Table 997. Pin description
Pin function

Direction

Description

I2S0/1_RX_SCK

Input/
Output

Receive Clock. A clock signal used to synchronize the transfer of data on the receive
channel. It is driven by the master and received by the slave. Corresponds to the signal
SCK in the I2S bus specification.

I2S0/1_RX_WS

Input/
Output

Receive Word Select. Selects the channel from which data is to be received. It is driven
by the master and received by the slave. Corresponds to the signal WS in the I2S bus
specification.
WS = 0 indicates that data is being received by channel 1 (left channel).
WS = 1 indicates that data is being received by channel 2 (right channel).

I2S0/1_RX_SDA

Input/
Output

Receive Data. Serial data, received MSB first. It is driven by the transmitter and read by
the receiver. Corresponds to the signal SD in the I2S bus specification.

I2S0/1_RX_MCLK

Output

Optional master clock output for the I2S receive function.

I2S0/1_TX_SCK

Input/
Output

Transmit Clock. A clock signal used to synchronize the transfer of data on the transmit
channel. It is driven by the master and received by the slave. Corresponds to the signal
SCK in the I2S bus specification.

I2S0/1_TX_WS

Input/
Output

Transmit Word Select. Selects the channel to which data is being sent. It is driven by the
master and received by the slave. Corresponds to the signal WS in the I2S bus
specification.
WS = 0 indicates that data is being sent to channel 1 (left channel).
WS = 1 indicates that data is being sent to channel 2 (right channel).

I2S0/1_TX_SDA

Input/
Output

Transmit Data. Serial data, sent MSB first. It is driven by the transmitter and read by the
receiver. Corresponds to the signal SD in the I2S bus specification.

IS0/1_TX_MCLK

Output

Optional master clock output for the I2S transmit function.

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Chapter 44: LPC43xx/LPC43Sxx I2S interface

SCK: serial clock
TRANSMITTER
(MASTER)

WS: word select
SD: serial data

SCK: serial clock
RECEIVER
(SLAVE)

TRANSMITTER
(SLAVE)

WS: word select
SD: serial data

RECEIVER
(MASTER)

CONTROLLER
(MASTER)
SCK
TRANSMITTER
(SLAVE)

WS
SD

RECEIVER
(SLAVE)

SCK

WS

MSB

SD
word n-1
right channel

LSB
word n
left channel

MSB
word n+1
right channel

Fig 146. Simple I2S configurations and bus timing

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44.6 Register description
Table 998 shows the registers associated with the I2S interface and a summary of their
functions. Following the table are details for each register.
Reset value reflects the data stored in used bits only. It does not include reserved bits
content.
Table 998. Register overview: I2S0 (base address 0x400A 2000)
Name

Access Address
offset

Description

DAO

R/W

0x000

I2S Digital Audio Output Register. Contains control bits for 0x87E1 Table 1000
the I2S transmit channel.

DAI

R/W

0x004

I2S Digital Audio Input Register. Contains control bits for
the I2S receive channel.

0x07E1 Table 1001

TXFIFO

WO

0x008

I2S Transmit FIFO. Access register for the 8 x 32-bit
transmitter FIFO.

0

Table 1002

RXFIFO

RO

0x00C

I2S Receive FIFO. Access register for the 8 x 32-bit
receiver FIFO.

0

Table 1003

STATE

RO

0x010

I2S Status Feedback Register. Contains status information 0x7
about the I2S interface.

Table 1004

DMA1

R/W

0x014

I2S DMA Configuration Register 1. Contains control
information for DMA request 1.

0

Table 1005

DMA2

R/W

0x018

I2S DMA Configuration Register 2. Contains control
information for DMA request 2.

0

Table 1006

IRQ

R/W

0x01C

I2S Interrupt Request Control Register. Contains bits that
control how the I2S interrupt request is generated.

0

Table 1007

TXRATE

R/W

0x020

I2S Transmit MCLK divider. This register determines the
0
I2S TX MCLK rate by specifying the value to divide PCLK
by in order to produce MCLK.

Table 1008

RXRATE

R/W

0x024

I2S Receive MCLK divider. This register determines the
0
I2S RX MCLK rate by specifying the value to divide PCLK
by in order to produce MCLK.

Table 1009

TXBITRATE

R/W

0x028

I2S Transmit bit rate divider. This register determines the
I2S transmit bit rate by specifying the value to divide
TX_MCLK by in order to produce the transmit bit clock.

0

Table 1010

RXBITRATE

R/W

0x02C

I2S Receive bit rate divider. This register determines the
I2S receive bit rate by specifying the value to divide
RX_MCLK by in order to produce the receive bit clock.

0

Table 1011

TXMODE

R/W

0x030

I2S Transmit mode control.

0

Table 1012

RXMODE

R/W

0x034

I2S Receive mode control.

0

Table 1013

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Chapter 44: LPC43xx/LPC43Sxx I2S interface

Table 999. Register overview: I2S1 (base address 0x400A 3000)
Name

Access Address
offset

Description

Reset
value

Reference

DAO

R/W

0x000

I2S Digital Audio Output Register. Contains control bits for 0x87E1 Table 1000
the I2S transmit channel.

DAI

R/W

0x004

I2S Digital Audio Input Register. Contains control bits for
the I2S receive channel.

0x07E1 Table 1001

TXFIFO

WO

0x008

I2S Transmit FIFO. Access register for the 8 x 32-bit
transmitter FIFO.

0

Table 1002

RXFIFO

RO

0x00C

I2S Receive FIFO. Access register for the 8 x 32-bit
receiver FIFO.

0

Table 1003

STATE

RO

0x010

I2S Status Feedback Register. Contains status information 0x7
about the I2S interface.

Table 1004

DMA1

R/W

0x014

I2S DMA Configuration Register 1. Contains control
information for DMA request 1.

0

Table 1005

DMA2

R/W

0x018

I2S DMA Configuration Register 2. Contains control
information for DMA request 2.

0

Table 1006

IRQ

R/W

0x01C

I2S Interrupt Request Control Register. Contains bits that
control how the I2S interrupt request is generated.

0

Table 1007

TXRATE

R/W

0x020

I2S Transmit MCLK divider. This register determines the
I2S TX MCLK rate by specifying the value to divide PCLK
by in order to produce MCLK.

0

Table 1008

RXRATE

R/W

0x024

I2S Receive MCLK divider. This register determines the
0
I2S RX MCLK rate by specifying the value to divide PCLK
by in order to produce MCLK.

Table 1009

TXBITRATE

R/W

0x028

I2S Transmit bit rate divider. This register determines the
I2S transmit bit rate by specifying the value to divide
TX_MCLK by in order to produce the transmit bit clock.

0

Table 1010

RXBITRATE

R/W

0x02C

I2S Receive bit rate divider. This register determines the
I2S receive bit rate by specifying the value to divide
RX_MCLK by in order to produce the receive bit clock.

0

Table 1011

TXMODE

R/W

0x030

I2S Transmit mode control.

0

Table 1012

RXMODE

R/W

0x034

I2S Receive mode control.

0

Table 1013

44.6.1 I2S Digital Audio Output register
The DAO register controls the operation of the I2S transmit channel. The function of bits in
DAO are shown in Table 1000.
Table 1000.I2S Digital Audio Output register (DAO, address 0x400A 2000 (I2S0) and 0x400A
3000 (I2S1)) bit description
Bit

Symbol

1:0

WORDWIDTH

2

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MONO

Value Description

Reset
value

Selects the number of bytes in data as follows:
0x0

8-bit data

0x1

16-bit data

0x2

Reserved. Do not use this setting

0x3

32-bit data
When 1, data is of monaural format. When 0, the
data is in stereo format.

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Table 1000.I2S Digital Audio Output register (DAO, address 0x400A 2000 (I2S0) and 0x400A
3000 (I2S1)) bit description
Bit

Symbol

Value Description

3

STOP

When 1, disables accesses on FIFOs, places the
transmit channel in mute mode.

4

RESET

When 1, asynchronously resets the transmit channel 0
and FIFO.

5

WS_SEL

When 0, the interface is in master mode. When 1,
the interface is in slave mode.

14:6

WS_HALFPERIOD

Word select half period minus 1, i.e. WS 64clk period 0x1F
-> ws_halfperiod = 31.

15

MUTE

When 1, the transmit channel sends only zeroes.

1

Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit is
not defined.

-

31:16 -

Reset
value

0

1

44.6.2 I2S Digital Audio Input register
The DAI register controls the operation of the I2S receive channel. The function of bits in
DAI are shown in Table 1001.
Table 1001.I2S Digital Audio Input register (DAI, address 0x400A 2004 (I2S0) and 0x400A
3004 (I2S1)) bit description
Bit

Symbol

Value

1:0

WORDWIDTH

Description

Reset
value

Selects the number of bytes in data as follows:

01

0x0

8-bit data

0x1

16-bit data

0x2

Reserved. Do not use this setting

0x3

32-bit data

2

MONO

When 1, data is of monaural format. When 0, the
data is in stereo format.

0

3

STOP

When 1, disables accesses on FIFOs, places the
transmit channel in mute mode.

0

4

RESET

When 1, asynchronously reset the transmit
channel and FIFO.

0

5

WS_SEL

When 0, the interface is in master mode. When 1,
the interface is in slave mode.

1

14:6

WS_HALFPERIOD

Word select half period minus 1, i.e. WS 64clk
period -> ws_halfperiod = 31.

0x1F

31:15

-

Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is
not defined.

44.6.3 I2S Transmit FIFO register
The TXFIFO register provides access to the transmit FIFO.

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Chapter 44: LPC43xx/LPC43Sxx I2S interface

Table 1002.Transmit FIFO register (TXFIFO, address 0x400A 2008 (I2S0) and 0x400A 3008
(I2S1)) bit description
Bit

Symbol

Description

Reset value

31:0

I2STXFIFO

8 x 32-bit transmit FIFO.

0

44.6.4 Receive FIFO register
The I2SRXFIFO register provides access to the receive FIFO.
Table 1003.I2S Receive FIFO register (RXFIFO, address 0x400A 200C (I2S0) and 0x400A 300C
(I2S1)) bit description
Bit

Symbol

31:0 I2SRXFIFO

Description

Reset value

8 x 32-bit receive FIFO.

0

44.6.5 I2S Status Feedback register
The STATE register provides status information about the I2S interface.
Table 1004.I2S Status Feedback register (STATE, address 0x400A 2010 (I2S0) and 0x400A
3010 (I2S1)) bit description
Bit

Symbol

Description

Reset
value

0

IRQ

This bit reflects the presence of Receive Interrupt or Transmit
Interrupt. This is determined by comparing the current FIFO
levels to the rx_depth_irq and tx_depth_irq fields in the IRQ
register.

1

1

DMAREQ1

This bit reflects the presence of Receive or Transmit DMA
Request 1. This is determined by comparing the current FIFO
levels to the rx_depth_dma1 and tx_depth_dma1 fields in the
DMA1 register.

1

2

DMAREQ2

This bit reflects the presence of Receive or Transmit DMA
Request 2. This is determined by comparing the current FIFO
levels to the rx_depth_dma2 and tx_depth_dma2 fields in the
DMA2 register.

1

7:3

-

Reserved.

0

11:8

RX_LEVEL

Reflects the current level of the Receive FIFO.

0

15:12

-

Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.

-

19:16

TX_LEVEL

Reflects the current level of the Transmit FIFO.

0

31:20

-

Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.

-

44.6.6 I2S DMA Configuration Register 1
The DMA1 register controls the operation of DMA request 1. The function of bits in DMA1
are shown in Table 1005. Refer to Chapter 21 for details of DMA operation.
This register enables the DMA for the I2S receive and transmit channels and sets the
FIFO level.

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Chapter 44: LPC43xx/LPC43Sxx I2S interface

Remark: The FIFOs contain eight 32 bit Dwords. Therefore, if the I2S controller is
configured for 32-bit mode (see Table 1000 and Table 1001), the maximum allowed FIFO
level is 4.
Table 1005.I2S DMA Configuration register 1 (DMA1, address 0x400A 2014 (I2S0) and 0x400A
3014 (I2S1)) bit description
Bit

Symbol

Description

Reset
value

0

RX_DMA1_ENABLE

When 1, enables DMA1 for I2S receive.

0

1

TX_DMA1_ENABLE

When 1, enables DMA1 for I2S transmit.

0

7:2

-

Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit is not
defined.

0

11:8

RX_DEPTH_DMA1

Set the FIFO level that triggers a receive DMA request on 0
DMA1.

15:12

-

Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit is not
defined.

-

19:16

TX_DEPTH_DMA1

Set the FIFO level that triggers a transmit DMA request
on DMA1.

0

31:20

-

Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit is not
defined.

-

44.6.7 I2S DMA Configuration Register 2
The DMA2 register controls the operation of DMA request 2. The function of bits in DMA2
are shown in Table 1000.
This register enables the DMA for the I2S receive and transmit channels and sets the
FIFO level.
Remark: The FIFOs contain eight 32 bit Dwords. Therefore, if the I2S controller is
configured for 32-bit mode (see Table 1000 and Table 1001), the maximum allowed FIFO
level is 4.
Table 1006.I2S DMA Configuration register 2 (DMA2, address 0x400A 2018 (I2S0) and 0x400A
3018 (I2S1)) bit description

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Bit

Symbol

Description

Reset
value

0

RX_DMA2_ENABLE

When 1, enables DMA1 for I2S receive.

0

1

TX_DMA2_ENABLE

When 1, enables DMA1 for I2S transmit.

0

7:2

-

Reserved.

0

11:8

RX_DEPTH_DMA2

Set the FIFO level that triggers a receive DMA request
on DMA2.

0

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Chapter 44: LPC43xx/LPC43Sxx I2S interface

Table 1006.I2S DMA Configuration register 2 (DMA2, address 0x400A 2018 (I2S0) and 0x400A
3018 (I2S1)) bit description
Bit

Symbol

Description

Reset
value

15:12

-

Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit is not
defined.

-

19:16

TX_DEPTH_DMA2

Set the FIFO level that triggers a transmit DMA request
on DMA2.

0

31:20

-

Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit is not
defined.

-

44.6.8 I2S Interrupt Request Control register
The IRQ register controls the operation of the I2S interrupt request. The function of bits in
IRQ are shown in Table 1000.
Table 1007.I2S Interrupt Request Control register (IRQ, address 0x400A 201C (I2S0) and
0x400A 301C (I2S1)) bit description
Bit

Symbol

Description

Reset
value

0

RX_IRQ_ENABLE

When 1, enables I2S receive interrupt.

0

1

TX_IRQ_ENABLE

When 1, enables I2S transmit interrupt.

0

7:2

-

Reserved.

0

11:8

RX_DEPTH_IRQ

Set the FIFO level on which to create an irq request.

0

15:12

-

Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.

-

19:16

TX_DEPTH_IRQ

Set the FIFO level on which to create an irq request.

0

31:20

-

Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.

-

44.6.9 I2S Transmit Clock Rate register
The MCLK rate for the I2S transmitter is determined by the values in the TXRATE register.
The required TXRATE setting depends on the desired audio sample rate, the format
(stereo/mono) used, and the data size.
The transmitter MCLK rate is generated using a fractional rate generator, dividing down
the frequency of PCLK = CLK_APB1_I2S. Values of the numerator (X) and the
denominator (Y) must be chosen to produce a frequency twice that desired for the
transmitter MCLK, which must be an integer multiple of the transmitter bit clock rate.
Fractional rate generators have some aspects that the user should be aware of when
choosing settings. These are discussed in Section 44.6.9.1. The equation for the
fractional rate generator is:
I2S_TX_MCLK = PCLK * (X/Y) /2
Note: If the value of X or Y is 0, then no clock is generated. Also, the value of Y must be
greater than or equal to X.

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Chapter 44: LPC43xx/LPC43Sxx I2S interface

Table 1008.I2S Transmit Clock Rate register (TXRATE, address 0x400A 2020 (I2S0) and
0x400A 3020 (I2S1)) bit description
Bit

Symbol

Description

Reset
value

7:0

Y_DIVIDER

I2S transmit MCLK rate denominator. This value is used to divide 0
PCLK to produce the transmit MCLK. Eight bits of fractional divide
supports a wide range of possibilities. A value of 0 stops the clock.

15:8

X_DIVIDER

I2S transmit MCLK rate numerator. This value is used to multiply
PCLK by to produce the transmit MCLK. A value of 0 stops the
clock. Eight bits of fractional divide supports a wide range of
possibilities. Note: the resulting ratio X/Y is divided by 2.

0

31:16

-

Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.

-

44.6.9.1 Notes on fractional rate generators
A fractional rate generator can introduce output jitter with some divide settings. This is
because the fractional rate generator is a fully digital function, so the output clock
transitions are synchronous with the source clock, whereas a theoretical perfect fractional
rate may have edges that are not related to the source clock. Therefore the output jitter
will not be greater than plus or minus one source clock between consecutive clock edges.
For example, if X = 0x07 and Y = 0x11, the fractional rate generator will output 7 clocks for
every 17 (11 hex) input clocks, distributed as evenly as it can. In this example, there is no
way to distribute the output clocks in a perfectly even fashion, so some clocks will be
longer than others. The output is divided by 2 in order to square it up, which also helps
with the jitter. The frequency averages out to exactly (7/17) / 2, but some clocks will be a
slightly different length than their neighbors. It is possible to avoid jitter entirely by
choosing fractions such that X divides evenly into Y, such as 2/4, 2/6, 3/9, 1/N, etc.

44.6.10 I2S Receive Clock Rate register
The MCLK rate for the I2S receiver is determined by the values in the RXRATE register.
The required RXRATE setting depends on the peripheral clock rate (PCLK_I2S =
CLK_APB1_I2S) and the desired MCLK rate (such as 256 fs).
The receiver MCLK rate is generated using a fractional rate generator, dividing down the
frequency of PCLK_I2S. Values of the numerator (X) and the denominator (Y) must be
chosen to produce a frequency twice that desired for the receiver MCLK, which must be
an integer multiple of the receiver bit clock rate. Fractional rate generators have some
aspects that the user should be aware of when choosing settings. These are discussed in
Section 44.6.9.1. The equation for the fractional rate generator is:
I2S_RX_MCLK = PCLK_I2S * (X/Y) /2
Note: If the value of X or Y is 0, then no clock is generated. Also, the value of Y must be
greater than or equal to X.

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Chapter 44: LPC43xx/LPC43Sxx I2S interface

Table 1009.I2S Receive Clock Rate register (RXRATE, address 0x400A 2024 (I2S0) and
0x400A 3024 (I2S1)) bit description
Bit

Symbol

Description

Reset
value

7:0

Y_DIVIDER

I2S receive MCLK rate denominator. This value is used to divide
0
PCLK to produce the receive MCLK. Eight bits of fractional divide
supports a wide range of possibilities. A value of 0 stops the clock.

15:8

X_DIVIDER

I2S receive MCLK rate numerator. This value is used to multiply
PCLK by to produce the receive MCLK. A value of 0 stops the
clock. Eight bits of fractional divide supports a wide range of
possibilities. Note: the resulting ratio X/Y is divided by 2.

0

31:16

-

Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.

-

44.6.11 I2S Transmit Clock Bit Rate register
The bit rate for the I2S transmitter is determined by the value of the TXBITRATE register.
The value depends on the audio sample rate desired and the data size and format
(stereo/mono) used. For example, a 48 kHz sample rate for 16-bit stereo data requires a
bit rate of 48 000 x 16 x 2 = 1.536 MHz.
Table 1010.I2S Transmit Clock Rate register (TXBITRATE, address 0x400A 2028 (I2S0) and
0x400A 3028 (I2S1)) bit description
Bit

Symbol

Description

Reset
value

5:0

TX_BITRATE

I2S transmit bit rate. This value plus one is used to divide
TX_MCLK to produce the transmit bit clock.

0

31:6

-

Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.

-

44.6.12 I2S Receive Clock Bit Rate register
The bit rate for the I2S receiver is determined by the value of the RXBITRATE register.
The value depends on the audio sample rate, as well as the data size and format used.
The calculation is the same as for TXBITRATE.
Table 1011.I2S Receive Clock Rate register (RXBITRATE, address 0x400A 202C (I2S0) and
0x400A 302C (I2S1)) bit description
Bit

Symbol

Description

Reset
value

5:0

RX_BITRATE

I2S receive bit rate. This value plus one is used to divide
RX_MCLK to produce the receive bit clock.

0

31:6

-

Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.

-

44.6.13 I2S Transmit Mode Control register
The Transmit Mode Control register contains additional controls for the transmit clock
source, enabling the 4-pin mode (SCK and WS signals are shared between I2S transmit and
receive blocks), and how MCLK is used.

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Chapter 44: LPC43xx/LPC43Sxx I2S interface

Table 1012.I2S Transmit Mode Control register (TXMODE, address 0x400A 2030 (I2S0) and
0x400A 3030 (I2S1)) bit description
Bit

Symbol

Value Description

1:0

TXCLKSEL

Reset
value

Clock source selection for the transmit bit clock divider.

0

0x0

Tx fractional rate divider. Select the TX fractional rate divider
clock output as the source

0x1

Reserved

0x2

RX_MCLK. Select the RX_MCLK signal as the TX_MCLK
clock source

0x3

Reserved

2

TX4PIN

Transmit 4-pin mode selection (SCK and WS signals are
shared between I2S transmit and receive blocks). When 1,
enables 4-pin mode.

0

3

TXMCENA

Enable for the TX_MCLK output. When 0, output of
TX_MCLK is not enabled. When 1, output of TX_MCLK is
enabled.

0

31:4

-

Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.

NA

44.6.14 I2S Receive Mode Control register
The Receive Mode Control register contains additional controls for receive clock source,
enabling the 4-pin mode (SCK and WS signals are shared between I2S transmit and receive
blocks), and how MCLK is used.
Table 1013.I2S Receive Mode Control register (RXMODE, address 0x400A 2034 (I2S0) and
0x400A 3034 (I2S1)) bit description

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Bit

Symbol

Value Description

1:0

RXCLKSEL

Reset
value

Clock source selection for the receive bit clock divider.

0

0x0

RX fractional divider. Select the RX fractional rate divider
clock output as the source

0x1

BASE_AUDIO_CLK or I2S_RX_MCLK. Select
BASE_AUDIO_CLK or I2S_RX_MCLK as the clock source.

0x2

TX_MCLK. Select the TX_MCLK signal as the RX_MCLK
clock source

0x3

Reserved

2

RX4PIN

Receive 4-pin mode selection (SCK and WS signals are
shared between I2S transmit and receive blocks). When 1,
enables 4-pin mode.

0

3

RXMCENA

Enable for the RX_MCLK output. When 0, output of
RX_MCLK is not enabled. When 1, output of RX_MCLK is
enabled.

0

31:4

-

Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.

NA

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Chapter 44: LPC43xx/LPC43Sxx I2S interface

44.7 Functional description
44.7.1 I2S transmit and receive interfaces
The I2S interface can transmit and receive 8-bit, 16-bit or 32-bit stereo or mono audio
information. Some details of the I2S implementation are:

• When the transmit FIFO contains insufficient data the transmit channel will repeat
transmitting the last data until new data is available. This can occur when the
microcontroller or the DMA at some time are unable to provide new data fast enough.
Because of this delay in providing new data, there is a need to fill the gap, which is
accomplished by continuing to transmit the last sample. The data is not muted, as this
would produce a noticeable and undesirable sound effects.

• When mute is true, the data value 0 is transmitted.
• When mono is false, two successive data words are respectively left and right data.
• The transmit channel and the receive channel FIFOs only handle 32-bit aligned
segments. Data chunks must be truncated or extended to a multiple of 32 bits. The
data word length is determined by the WORDWIDTH value in the configuration
register (see Table 1000). There is a separate WORDWIDTH value for the receive
channel and the transmit channel.
– 0: word is considered to contain four 8-bit data words.
– 1: word is considered to contain two 16-bit data words.
– 3: word is considered to contain one 32-bit data word.
When switching between different word widths or different modes, the I2S interface must
be reset via the reset bit in the control register in order to ensure correct synchronization.
It is advisable to set the stop bit also until sufficient data has been written in the transmit
FIFO. Note that when stopped, the data output is muted.
Data is read from the transmit FIFO after the falling edge of WS and will be transferred to
the transmit clock domain after the rising edge of WS. On the next falling edge of WS, the
left data will be loaded in the shift register and transmitted. On the following rising edge of
WS, the right data is loaded and transmitted.
The receive channel will start receiving data after a change of WS. When WS becomes
low it expects this data to be left data, when WS is high received data is expected to be
right data. Reception will stop when the bit counter has reached the limit set by the
WORDWIDTH value. On the next change of WS the received data will be stored in the
appropriate hold register. When complete data is available, it will be written into the
receive FIFO.

44.7.2 I2S operating modes
The clocking and WS usage of the I2S interface is fully configurable. In addition to master
and slave modes, which are independently configurable for the transmitter and the
receiver, several different clock sources are possible, including variations that share the
clock and/or WS between the transmitter and receiver. This last option allows using the
I2S interface with fewer pins, typically four.
Figure 147 provides an overview of the complete I2S interface. Specific operating modes
are explained in Section 44.7.2.1 and Section 44.7.2.2.
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TXMODE[3]

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CREG6[12]

Pin OE

I2S_TX_MCLK
0
1

0

I2S_TX_SDA

1

BASE_AUDIO_CLK

I2S_TX_SCK
TXRATE[15:8]
TXRATE[7:0]

Y
8-bit
Fractional
Rate Divider

TXMODE[1:0]

1
0

TX_MCLK

01
00
10

TXMODE[2]
TX_SCK

(1 to 64)

DAO[5]

2

IS
peripheral
block

TXBITRATE[5:0]
RXBITRATE[5:0]

TXRATE[7:0]

0
1
DAI[5]

RX_MCLK

10
00
01

(1 to 64) RX_SCK

RXMODE[1:0]

RXMODE[2]

TX_WS

I2S_TX_WS

1

1

PCLK
8-bit
Fractional
Rate Divider
X
Y

0

0

Pin OEn

TXMODE[2]
RXMODE[2]

1

1

0

0

RX_WS

I2S_RX_WS
DAI[5]

Pin OEn

TXRATE[15:8]

I2S_RX_SCK

I2S_RX_SDA

1

BASE_AUDIO_CLK

1

0

0

I2S_RX_MCLK
RXMODE[3]

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CREG6 bits 12 and 13 select PLL0AUDIO for the I2S0 interface. CREG bits 14 and 15 select BASE_AUDIO_CLK for the I2S1 interface.

Fig 147. I2S clocking and pin connections

Pin OE

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X

DAO[5]

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Chapter 44: LPC43xx/LPC43Sxx I2S interface

44.7.2.1 I2S Transmitter modes
44.7.2.1.1

Typical transmitter master mode (PCLK - no MCLK output)

Table 1014.Typical transmitter master mode (PCLK - no MCLK output)
CREG bit 12

DAO bit 5

TXMODE
bits [3:0]

Description

x

0

0000

Typical transmitter master mode. See Figure 148.
The I2S transmit function operates as a master.
The transmit clock source (TX_MCLK) is derived from PCLK using the
fractional divider.
The WS used is the internally generated TX_WS.
The TX_MCLK pin is not enabled for output.

CREG6[12]=X

TXMODE[3]=0

0
1

Pin OE

I2S_TX_MCLK
0
1

BASE_AUDIO_CLK

I2S_TX_SDA

I2S_TX_SCK
TX_RATE[15:8]
TX_RATE[7:0]
X
Y
8-bit
Fractional
Rate Divider

DAO[5]=0

TXMODE[1:0]=00

1
0

TX_MCLK

01
00
10

TXMODE[2]=0
TX_SCK

(1 to 64)

0
1

TXBITRATE[5:0]

DAO[5]=0

I2 S
peripheral
block

0
1

Pin OEn

TX_WS

I2S_TX_WS

TXMODE[2]=0
RX_MCLK

PCLK

RX_SCK

RX_WS

Bold lines indicate the clock path for this configuration.

Fig 148. Typical transmitter master mode (PCLK - no MCLK output)

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Chapter 44: LPC43xx/LPC43Sxx I2S interface

44.7.2.1.2

Transmitter master mode (PCLK), with MCLK output

Table 1015.Transmitter master mode (PCLK), with MCLK output
CREG bit 12 DAO bit 5

TXMODE
bits [3:0]

Description

0

1000

Transmitter master mode.

0

The I2S transmit function operates as a master.
The transmit clock source (TX_MCLK) is derived from PCLK using the
fractional divider.
The WS used is the internally generated TX_WS.
The TX_MCLK pin is enabled for output.

CREG6[12]=0

TXMODE[3]=1

0
1

Pin OE

I2S_TX_MCLK
0
1

BASE_AUDIO_CLK

I2S_TX_SDA

I2S_TX_SCK
TX_RATE[15:8]
TX_RATE[7:0]
X
Y
8-bit
Fractional
Rate Divider

DAO[5]=0

TXMODE[1:0]=00

1
0

TX_MCLK

01
00
10

TXMODE[2]=0
TX_SCK

(1 to 64)

0
1

TXBITRATE[5:0]

DAO[5]=0

I2 S
peripheral
block

0
1

Pin OEn

TX_WS

I2S_TX_WS

TXMODE[2]=0
RX_MCLK

PCLK

RX_SCK

RX_WS

Bold lines indicate the clock path for this configuration. CREG6 bits 12 and 13 select BASE_AUDIO_CLK for the I2S0 interface.
CREG bits 14 and 15 select PLL0AUDIO for the I2S1 interface.

Fig 149. Transmitter master mode (PCLK), with MCLK output

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Chapter 44: LPC43xx/LPC43Sxx I2S interface

44.7.2.1.3

Transmitter master mode, sharing RX_MCLK

Table 1016.Transmitter master mode, sharing RX_MCLK
CREG bit 12 DAO bit 5

TXMODE
bits [3:0]

Description

x

0010

Transmitter master mode sharing the receiver reference clock (RX_MCLK).

0

The I2S transmit function operates as a master.
The transmit clock source is RX_MCLK.
The WS used is the internally generated TX_WS.
The TX_MCLK pin is not enabled for output.

CREG6[12]=X

TXMODE[3]=0

0
1

Pin OE

I2S_TX_MCLK
0
1

BASE_AUDIO_CLK

I2S_TX_SDA

I2S_TX_SCK
TXRATE[15:8]
TXRATE[7:0]
X
Y
8-bit
Fractional
Rate Divider

DAO[5]=0

TXMODE[1:0]=10

1
0

TX_MCLK

01
00
10

TXMODE[2]=0
TX_SCK

(1 to 64)

0
1

TXBITRATE[5:0]

DAO[5]=0

I2 S
peripheral
block

0
1

Pin OEn

TX_WS

I2S_TX_WS

TXMODE[2]=0
RX_MCLK

RX_SCK

RX_WS

PCLK
Bold lines indicate the clock path for this configuration.

Fig 150. Transmitter master mode, sharing RX_MCLK

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Chapter 44: LPC43xx/LPC43Sxx I2S interface

44.7.2.1.4

Typical Transmitter slave mode

Table 1017.Typical Transmitter slave mode
CREG bit 12

DAO bit 5 TXMODE
bits [3:0]

Description

x

1

Typical transmitter slave mode.

0000

The I2S transmit function operates as a slave.
The transmit clock source TX_SCK is provided by the external master on the
TX_SCK pin. The transmit bit rate divider must be set to 1
(TXBITRATE[5:0]=000000) for this mode to operate correctly.
The WS signal is provided by the external master on the TX_WS pin.

CREG6[12]=X

TXMODE[3]=0

0
1

Pin OE

I2S_TX_MCLK
0
1

BASE_AUDIO_CLK

I2S_TX_SDA

I2S_TX_SCK
TXRATE[15:8]
TXRATE[7:0]
X
Y
8-bit
Fractional
Rate Divider

DAO[5]=1

TXMODE[1:0]=00

1
0

TX_MCLK

01
00
10

TXMODE[2]=0
TX_SCK

(1 to 64)

0
1

TXBITRATE[5:0]
RX_SCK

RX_MCLK

DAO[5]=1

I2 S
peripheral
block

0
1

Pin OEn

TX_WS

I2S_TX_WS

TXMODE[2]=0
RX_WS

PCLK
Bold lines indicate the clock path for this configuration.

Fig 151. Typical Transmitter slave mode

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Chapter 44: LPC43xx/LPC43Sxx I2S interface

44.7.2.1.5

4-Wire Transmitter mode

Table 1018.4-Wire Transmitter mode
CREG bit 12

DAO bit 5 TXMODE
bits [3:0]

Description

x

1

4-wire transmitter mode sharing the receiver RX_SCK and RX_WS (4-pin mode).

01xx

The I2S transmit function operates as an internal slave to the receive function.
The receive function can operate in either master or slave mode, determining the
operating mode of the entire I2S interface.
The transmit clock source is RX_SCK.
The WS used is the internally generated RX_WS.
The TX_MCLK pin is not enabled for output.

CREG6[12]=X

TXMODE[3]=0

0
1

Pin OE

I2S_TX_MCLK
0
1

BASE_AUDIO_CLK

I2S_TX_SDA

I2S_TX_SCK
TXRATE[15:8]
TXRATE[7:0]
X
Y
8-bit
Fractional
Rate Divider

DAO[5]=1
1
0

TX_MCLK

TXMODE[1:0]=XX

TXMODE[2]=1

01
00
10

TX_SCK
(1 to 64)

0
1

TXBITRATE[5:0]
RX_MCLK

RX_SCK

DAO[5]=1

I2S
peripheral
block

0
1

Pin OEn

TX_WS

I2S_TX_WS

TXMODE[2]=1
RX_WS

PCLK
Bold lines indicate the clock path for this configuration.

Fig 152. 4-Wire Transmitter mode

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Chapter 44: LPC43xx/LPC43Sxx I2S interface

44.7.2.1.6

Transmitter master mode (BASE_AUDIO_CLK)

Table 1019.Transmitter master mode (BASE_AUDIO_CLK)
CREG bit 12

DAO bit 5 TXMODE
bits [3:0]

Description

1

0

Transmitter master mode.

1001

The I2S transmit function operates as a master.
The transmit clock source (TX_MCLK) is derived from the BASE_AUDIO_CLK.
The WS used is the internally generated TX_WS.
The TX_MCLK pin is enabled for output.

CREG6[12]=1

TXMODE[3]=1

0
1

Pin OE

I2S_TX_MCLK
0
1

BASE_AUDIO_CLK

I2S_TX_SDA

I2S_TX_SCK
TXRATE[15:8]
TXRATE[7:0]
X
Y
8-bit
Fractional
Rate Divider

DAO[5]=0

TXMODE[1:0]=01

1
0

TX_MCLK

01
00
10

TXMODE[2]=0
TX_SCK

(1 to 64)

0
1

TXBITRATE[5:0]
RX_MCLK

RX_SCK

DAO[5]=0

I2S
peripheral
block

0
1

Pin OEn

TX_WS

I2S_TX_WS

TXMODE[2]=0
RX_WS

PCLK
Bold lines indicate the clock path for this configuration. CREG6 bits 12 and 13 select BASE_AUDIO_CLK for the I2S0 interface.
CREG bits 14 and 15 select BASE_AUDIO_CLK for the I2S1 interface.

Fig 153. Transmitter master mode (BASE_AUDIO_CLK)

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Chapter 44: LPC43xx/LPC43Sxx I2S interface

44.7.2.1.7

Transmitter master mode (External MCLK)

Table 1020.Transmitter master mode (External MCLK)
CREG bit 12

DAO bit 5 TXMODE
bits [3:0]

Description

0

0

Transmitter master mode.

0001

The I2S transmit function operates as a master.
The transmit clock source (TX_MCLK) is provided by the external master on the
TX_MCLK pin.
The WS used is the internally generated TX_WS.
The TX_MCLK pin is enabled for input.

CREG6[12]=0

TXMODE[3]=0

0
1

Pin OE

I2S_TX_MCLK
0
1

BASE_AUDIO_CLK

I2S_TX_SDA

I2S_TX_SCK

TXRATE[15:8]
TXRATE[7:0]
X
Y
8-bit
Fractional
Rate Divider

DAO[5]=0

TXMODE[1:0]=01

1
0

TX_MCLK

01
00
10

TXMODE[2]=0
TX_SCK

(1 to 64)

0
1

TXBITRATE[5:0]
RX_MCLK

RX_SCK

DAO[5]=0

I2 S
peripheral
block

0
1

Pin OEn

TX_WS

I2S_TX_WS

TXMODE[2]=0
RX_WS

PCLK
Bold lines indicate the clock path for this configuration. CREG6 bits 12 and 13 select BASE_AUDIO_CLK for the I2S0 interface.
CREG bits 14 and 15 select BASE_AUDIO_CLK for the I2S1 interface.

Fig 154. Transmitter master mode (External MCLK)

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Chapter 44: LPC43xx/LPC43Sxx I2S interface

44.7.2.2 I2S Receiver modes
44.7.2.2.1

Typical Receiver master mode (PCLK - no MCLK output)

Table 1021.Typical Receiver master mode (PCLK - no MCLK output)
CREG bit 13

DAI bit 5

RXMODE
bits [3:0]

x

0

0000

Description

Typical receiver master mode.
The I2S receive function operates as a master.
The receive clock source (RX_MCLK) is derived from PCLK using the
fractional divider.
The WS used is the internally generated RX_WS.
The RX_MCLK pin is not enabled for output.

PCLK
TX_MCLK

TX_WS
RXMODE[2]=0

TX_SCK
RXBITRATE[5:0]

8-bit
Fractional
Rate Divider
X
Y
TXRATE[7:0]

1
0
1
DAI[5]=0

RX_MCLK

10
00
01

(1 to 64) RX_SCK

RXMODE[1:0]=00

0

RXMODE[2]=0

I2 S
peripheral
block

1
0

I2S_RX_WS
RX_WS
DAI[5]=0

Pin OEn

TXRATE[15:8]

I2S_RX_SCK

1

BASE_AUDIO_CLK

1

0

I2S_RX_SDA

0

CREG6[13]=X

RXMODE[3]=0

Pin OE

I2S_RX_MCLK
Bold lines indicate the clock path for this configuration.

Fig 155. Typical Receiver master mode (PCLK - no MCLK output)

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Chapter 44: LPC43xx/LPC43Sxx I2S interface

44.7.2.2.2

Receiver master mode (PCLK), with MCLK output

Table 1022.Receiver master mode (PCLK), with MCLK output
CREG bit 13 DAI bit 5

RXMODE
bits [3:0]

Description

0

1000

Receiver master mode.

0

The I2S receive function operates as a master.
The receive clock source (RX_MCLK) is derived from PCLK using the
fractional divider.
The WS used is the internally generated RX_WS.
The RX_MCLK pin is enabled for output.

PCLK
TX_MCLK

TX_WS

TX_SCK
RXMODE[2]=0
RXBITRATE[5:0]

8-bit
Fractional
Rate Divider
X
Y
TXRATE[7:0]

1
0
1
DAI[5]=0

RX_MCLK

10
00
01

(1 to 64) RX_SCK

RXMODE[1:0]=00

0

RXMODE[2]=0

I2 S
peripheral
block

1
0

I2S_RX_WS
RX_WS
DAI[5]=0

Pin OEn

TXRATE[15:8]

I2S_RX_SCK

1

BASE_AUDIO_CLK

1

0

I2S_RX_SDA

0

CREG6[13]=0

RXMODE[3]=1

Pin OE

I2S_RX_MCLK
Bold lines indicate the clock path for this configuration. CREG6 bits 12 and 13 select BASE_AUDIO_CLK for the I2S0 interface.
CREG bits 14 and 15 select BASE_AUDIO_CLK for the I2S1 interface.

Fig 156. Receiver master mode (PCLK), with MCLK output

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Chapter 44: LPC43xx/LPC43Sxx I2S interface

44.7.2.2.3

Receiver master mode, sharing TX_MCLK

Table 1023.Receiver master mode, sharing TX_MCLK
CREG bit 13 DAI bit 5

RXMODE
bits [3:0]

Description

x

0010

Receiver master mode sharing the transmitter reference clock (TX_MCLK).

0

The I2S receive function operates as a master.
The receive clock source is TX_MCLK.
The WS used is the internally generated RX_WS.
The RX_MCLK pin is not enabled for output.

TX_WS

TX_SCK

TX_MCLK

RXMODE[2]=0

RXBITRATE[5:0]
8-bit
Fractional
Rate Divider
X
Y
TXRATE[7:0]

1
0
1
DAI[5]=0

RX_MCLK

10
00
01

(1 to 64) RX_SCK

RXMODE[1:0]=10

0

RXMODE[2]=0

I2S
peripheral
block

1

I2S_RX_WS
0

RX_WS
DAI[5]=0

Pin OEn

TXRATE[15:8]

I2S_RX_SCK

1

BASE_AUDIO_CLK

1

0

I2S_RX_SDA

0

CREG6[13]=X

RXMODE[3]=0

Pin OE

I2S_RX_MCLK
Bold lines indicate the clock path for this configuration.

Fig 157. Receiver master mode, sharing TX_MCLK

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Chapter 44: LPC43xx/LPC43Sxx I2S interface

44.7.2.2.4

Typical Receiver slave mode

Table 1024.Typical Receiver slave mode
CREG bit 13

DAI bit 5

RXMODE
bits [3:0]

Description

x

1

0000

Typical receiver slave mode.
The I2S receive function operates as a slave.
The receive clock source RX_SCK is provided by the external master on the
RX_SCK pin. The receive bit rate divider must be set to 1
(RXBITRATE[5:0]=000000) for this mode to operate correctly.
The WS signal is provided by the external master on the RX_WS pin.

PCLK
TX_MCLK

TX_WS
RXMODE[2]=0

TX_SCK
RXBITRATE[5:0]

8-bit
Fractional
Rate Divider
X
Y
TXRATE[7:0]

1
0
1
DAI[5]=1

RX_MCLK

10
00
01

(1 to 64) RX_SCK

RXMODE[1:0]=00

0

RXMODE[2]=0

I2 S
peripheral
block

1

I2S_RX_WS
0

RX_WS
DAI[5]=1

Pin OEn

TXRATE[15:8]

I2S_RX_SCK

1

BASE_AUDIO_CLK

1

0

I2S_RX_SDA

0

CREG6[13]=X

RXMODE[3]=0

Pin OE

I2S_RX_MCLK
Bold lines indicate the clock path for this configuration.

Fig 158. Typical Receiver slave mode

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Chapter 44: LPC43xx/LPC43Sxx I2S interface

44.7.2.2.5

4-Wire Receiver mode

Table 1025.4-Wire Receiver mode
CREG bit 13

DAI bit 5

RXMODE
bits [3:0]

Description

x

1

01xx

4-wire receiver mode sharing the transmitter TX_SCK and TX_WS (4-pin mode).
The I2S receive function operates as an internal slave to the transmit function.
The transmit function can operate in either master or slave mode, determining
the operating mode of the entire I2S interface.
The receive clock source is TX_SCK.
The WS used is the internally generated TX_WS.
The RX_MCLK pin is not enabled for output.

PCLK
TX_MCLK

TX_WS
RXMODE[2]=1

TX_SCK
RXBITRATE[5:0]

8-bit
Fractional
Rate Divider
X
Y
TXRATE[7:0]

1
0

RX_MCLK

1
DAI[5]=1

10
00
01

(1 to 64) RX_SCK

RXMODE[1:0]=XX

0

I2 S
peripheral
block

RXMODE[2]=1

1
0

I2S_RX_WS
RX_WS
DAI[5]=1

Pin OEn

TXRATE[15:8]

I2S_RX_SCK

1

BASE_AUDIO_CLK

1

0

I2S_RX_SDA

0

CREG6[13]=X

RXMODE[3]=0

Pin OE

I2S_RX_MCLK
Bold lines indicate the clock path for this configuration.

Fig 159. 4-Wire Receiver mode

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Chapter 44: LPC43xx/LPC43Sxx I2S interface

44.7.2.2.6

Receiver master mode (BASE_AUDIO_CLK)

Table 1026.Receiver master mode (BASE_AUDIO_CLK)
CREG bit 13

DAI bit 5

RXMODE
bits [3:0]

Description

1

0

1001

Receiver master mode.
The I2S receive function operates as a master.
The receive clock source (RX_MCLK) is derived from the BASE_AUDIO_CLK.
The WS used is the internally generated RX_WS.
The RX_MCLK pin is enabled for output.

PCLK
TX_MCLK

TX_WS

TX_SCK

RXMODE[2]=0
RXBITRATE[5:0]
8-bit
Fractional
Rate Divider
X
Y
TXRATE[7:0]

1
0
1
DAI[5]=0

RX_MCLK

10
00
01

(1 to 64) RX_SCK

RXMODE[1:0]=01

0

I2 S
peripheral
block

RXMODE[2]=0

1
0

I2S_RX_WS
RX_WS
DAI[5]=0

Pin OEn

TXRATE[15:8]

I2S_RX_SCK

1

BASE_AUDIO_CLK

1

0

I2S_RX_SDA

0

CREG6[13]=1

RXMODE[3]=1

Pin OE

I2S_RX_MCLK
Bold lines indicate the clock path for this configuration. CREG6 bits 12 and 13 select BASE_AUDIO_CLK for the I2S0 interface.
CREG bits 14 and 15 select BASE_AUDIO_CLK for the I2S1 interface.

Fig 160. Receiver master mode (BASE_AUDIO_CLK)

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Chapter 44: LPC43xx/LPC43Sxx I2S interface

44.7.2.2.7

Receiver master mode (External MCLK)

Table 1027.Receiver master mode (External MCLK)
CREG bit 13

DAI bit 5

RXMODE
bits [3:0]

Description

0

0

0001

Receiver master mode.
The I2S receive function operates as a master.
The receive clock source (RX_MCLK) is provided by the external master on the
RX_MCLK pin.
The WS used is the internally generated RX_WS.
The RX_MCLK pin is enabled for input.

PCLK
TX_MCLK

TX_WS

TX_SCK

RXMODE[2]=0
RXBITRATE[5:0]
8-bit
Fractional
Rate Divider
X
Y
TXRATE[7:0]

1
0
1
DAI[5]=0

RX_MCLK

10
00
01

(1 to 64) RX_SCK

RXMODE[1:0]=01

0

I2 S
peripheral
block

RXMODE[2]=0

1
0

I2S_RX_WS
RX_WS
DAI[5]=0

Pin OEn

TXRATE[15:8]

I2S_RX_SCK

1

BASE_AUDIO_CLK

1

0

I2S_RX_SDA

0

CREG6[13]=0

RXMODE[3]=0

Pin OE

I2S_RX_MCLK
Bold lines indicate the clock path for this configuration. CREG6 bits 12 and 13 select BASE_AUDIO_CLK for the I2S0 interface.
CREG bits 14 and 15 select BASE_AUDIO_CLK for the I2S1 interface.

Fig 161. Receiver master mode (External MCLK)

44.7.3 FIFO controller
Handling of data for transmission and reception is performed via the FIFO controller which
can generate two DMA requests and an interrupt request. The controller consists of a set
of comparators which compare FIFO levels with depth settings contained in registers. The
current status of the level comparators can be seen in the APB status register.

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Chapter 44: LPC43xx/LPC43Sxx I2S interface

Table 1028.Conditions for FIFO level comparison
Level Comparison

Condition

dmareq_tx_1

tx_depth_dma1 >= tx_level

dmareq_rx_1

rx_depth_dma1 <= rx_level

dmareq_tx_2

tx_depth_dma2 >= tx_level

dmareq_rx_2

rx_depth_dma2 <= rx_level

irq_tx

tx_depth_irq >= tx_level

irq_rx

rx_depth_irq <= rx_level

System signaling occurs when a level detection is true and enabled.
Table 1029.DMA and interrupt request generation
System Signaling

Condition

irq

(irq_rx & rx_irq_enable) | (irq_tx & tx_irq_enable)

dmareq[0]

(dmareq_tx_1 & tx_dma1_enable ) | (dmareq_rx_1 &
rx_dma1_enable )

dmareq[1]

( dmareq_tx_2 & tx_dma2_enable ) | (dmareq_rx_2 &
rx_dma2_enable )

Table 1030.Status feedback in the STATE register

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Status Feedback

Status

irq

irq_rx | irq_tx

dmareq1

(dmareq_tx_1 | dmareq_rx_1)

dmareq2

(dmareq_rx_2 | dmareq_tx_2)

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Chapter 44: LPC43xx/LPC43Sxx I2S interface

Mono 8-bit data mode
7

N+3

0

7

0

7

N+2

0

7

0

7

0

15

0

15

N+1

0

7

0

7

N

0

Stereo 8-bit data mode
7

LEFT + 1

RIGHT + 1

LEFT

RIGHT

0

Mono 16-bit data mode
15

N+1

N

0

Stereo 16-bit data mode
15

LEFT

RIGHT

0

Mono 32-bit data mode
N

31

0

Stereo 32-bit data mode
LEFT

31

RIGHT

31

0

0

N

N+1

Fig 162. FIFO contents for various I2S modes

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Chapter 45: LPC43xx/LPC43Sxx C_CAN
Rev. 2.4 — 22 August 2018

User manual

45.1 How to read this chapter
The C_CAN0/1 controllers are available on all LPC43xx/LPC43Sxx parts.

45.2 Basic configuration
The C_CAN is configured as follows:

•
•
•
•

See Table 1031 for clocking and power control.
The C_CAN0 is reset by the CAN0_RST (reset # 55).
The C_CAN1 is reset by the CAN1_RST (reset # 56).
The ORed C_CAN0 and C_CAN1 interrupt is connected to slot # 12 in the Event
router.

• The C_CAN0 interrupt is connected to interrupt #51 in the NVIC.
• The C_CAN1 interrupt is connected to interrupt #43 in the NVIC.
• Set the CAN clock divider CLKDIV to divide the CLK_APB3_CAN0 and
CLK_APB1_CAN1 clocks to run at less than 50 MHz. See Table 1076.

• See Section 45.7.5.2 for calculating the CAN bit rate.
Table 1031.C_CAN clocking and power control
Base clock

Branch clock

Operating
frequency

Clock to the C_CAN0 register interface
and C_CAN0 peripheral clock (PCLK).
PCLK must be divided by the CAN0
clock divider CLKDIV to be less than
50 MHz.

BASE_APB3_CLK

CLK_APB3_CAN0

up to
204 MHz

Clock to the C_CAN1 register interface
and C_CAN1 peripheral clock (PCLK).
PCLK must be divided by the CAN1
clock divider CLKDIV to be less than
50 MHz.

BASE_APB1_CLK

CLK_APB1_CAN1

up to
204 MHz

Remark: The clocks to the C_CAN0 and C_CAN1 interfaces can be set independently of
each other.
Remark: Use of C_CAN controller excludes operation of all other peripherals connected
to the same bus bridge. See the LPC43xx errata.

45.3 Features
•
•
•
•
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Conforms to protocol version 2.0 parts A and B.
Supports bit rate of up to 1 Mbit/s.
Supports 32 Message Objects.
Each Message Object has its own identifier mask.
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Chapter 45: LPC43xx/LPC43Sxx C_CAN

• Provides programmable FIFO mode (concatenation of Message Objects).
• Provides maskable interrupts.
• Supports Disabled Automatic Retransmission (DAR) mode for time-triggered CAN
applications.

• Provides programmable loop-back mode for self-test operation.

45.4 General description
Controller Area Network (CAN) is the definition of a high performance communication
protocol for serial data communication. The C_CAN controller is designed to provide a full
implementation of the CAN protocol according to the CAN Specification Version 2.0B. The
C_CAN controller allows to build powerful local networks with low-cost multiplex wiring by
supporting distributed real-time control with a very high level of security.
The CAN controller consists of a CAN core, message RAM, a message handler, control
registers, and the APB interface.
For communication on a CAN network, individual Message Objects are configured. The
Message Objects and Identifier Masks for acceptance filtering of received messages are
stored in the Message RAM.
All functions concerning the handling of messages are implemented in the Message
Handler. Those functions are the acceptance filtering, the transfer of messages between
the CAN Core and the Message RAM, and the handling of transmission requests as well
as the generation of the module interrupt.
The register set of the CAN controller can be accessed directly by the CPU via the APB
bus. These registers are used to control/configure the CAN Core and the Message
Handler and to access the Message RAM.
CAN0/1_TD

CAN0/1_RD

C_CAN0/1
CAN CORE

APB
bus
MESSAGE RAM

MESSAGE
HANDLER

APB
INTERFACE

REGISTER
INTERFACE

Fig 163. C_CAN block diagram
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Chapter 45: LPC43xx/LPC43Sxx C_CAN

45.5 Pin description
Table 1032.C_CAN pin description

UM10503

User manual

Pin function

Direction

Description

CAN0/1_RD

I

C_CAN receive input

CAN0/1_TD

O

C_CAN transmit output

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Chapter 45: LPC43xx/LPC43Sxx C_CAN

45.6 Register description
Register values at reset
After a hardware reset, the registers hold the values described in Table 1033. Additionally,
the busoff state is reset and the output TD0,1 is set to recessive (HIGH). The value
0x0001 (INIT = ‘1’) in the CAN Control Register enables the software initialization. The
CAN controller does not communicate with the CAN bus until the CPU resets INIT to ‘0’.
The data stored in the message RAM is not affected by a hardware reset. After power-on,
the contents of the message RAM is undefined.
Table 1033.Register overview: C_CAN0 (base address 0x400E 2000)
Name

Access

Address
offset

Description

Reset
value

Reference

CNTL

R/W

0x000

CAN control register

0x0001

Table 1035

STAT

R/W

0x004

Status register

0x0000

Table 1036

EC

RO

0x008

Error counter register

0x0000

Table 1037

BT

R/W

0x00C

Bit timing register

0x2301

Table 1038

INT

RO

0x010

Interrupt register

0x0000

Table 1039

TEST

R/W

0x014

Test register

-

Table 1040

BRPE

R/W

0x018

Baud rate prescaler extension register

0x0000

Table 1041

-

-

0x01C

Reserved

-

IF1_CMDREQ

R/W

0x020

Message interface 1 command request

0x0001

Table 1044

IF1_CMDMSK_W

R/W

0x024

Message interface 1 command mask (write
direction)

0x0000

Table 1046

IF1_CMDMSK_R

R/W

0x024

Message interface 1 command mask (read
direction)

0x0000

Table 1048

IF1_MSK1

R/W

0x028

Message interface 1 mask 1

0xFFFF

Table 1050

IF1_MSK2

R/W

0x02C

Message interface 1 mask 2

0xFFFF

Table 1052

IF1_ARB1

R/W

0x030

Message interface 1 arbitration 1

0x0000

Table 1054

IF1_ARB2

R/W

0x034

Message interface 1 arbitration 2

0x0000

Table 1056

IF1_MCTRL

R/W

0x038

Message interface 1 message control

0x0000

Table 1058

IF1_DA1

R/W

0x03C

Message interface 1 data A1

0x0000

Table 1060

IF1_DA2

R/W

0x040

Message interface 1 data A2

0x0000

Table 1061

IF1_DB1

R/W

0x044

Message interface 1 data B1

0x0000

Table 1064

IF1_DB2

R/W

0x048

Message interface 1 data B2

0x0000

Table 1066

0x04C 0x07C

Reserved

-

IF2_CMDREQ

R/W

0x080

Message interface 2 command request

0x0001

Table 1045

IF2_CMDMSK_W

R/W

0x084

Message interface 2 command mask (write
direction)

0x0000

Table 1047

IF2_CMDMSK_R

R/W

0x084

Message interface 2 command mask (read
direction)

0x0000

Table 1049

IF2_MSK1

R/W

0x088

Message interface 2 mask 1

0xFFFF

Table 1051

IF2_MSK2

R/W

0x08C

Message interface 2 mask 2

0xFFFF

Table 1053

IF2_ARB1

R/W

0x090

Message interface 2 arbitration 1

0x0000

Table 1055

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Chapter 45: LPC43xx/LPC43Sxx C_CAN

Table 1033.Register overview: C_CAN0 (base address 0x400E 2000)
Name

Access

Address
offset

Description

Reset
value

Reference

IF2_ARB2

R/W

0x094

Message interface 2 arbitration 2

0x0000

Table 1057

IF2_MCTRL

R/W

0x098

Message interface 2 message control

0x0000

Table 1059

IF2_DA1

R/W

0x09C

Message interface 2 data A1

0x0000

Table 1061

IF2_DA2

R/W

0x0A0

Message interface 2 data A2

0x0000

Table 1062

IF2_DB1

R/W

0x0A4

Message interface 2 data B1

0x0000

Table 1065

IF2_DB2

R/W

0x0A8

Message interface 2 data B2

0x0000

Table 1067

-

-

0x0AC 0x0FC

TXREQ1

RO

0x100

Transmission request 1

0x0000

Table 1068

TXREQ2

RO

0x104

Transmission request 2

0x0000

Table 1069

-

-

0x108 0x11C

Reserved

-

ND1

RO

0x120

New data 1

0x0000

Table 1070

ND2

RO

0x124

New data 2

0x0000

Table 1071

-

-

0x128 0x13C

Reserved

-

IR1

RO

0x140

Interrupt pending 1

0x0000

Table 1072
Table 1073

IR2

RO

0x144

Interrupt pending 2

0x0000

-

-

0x148 0x15C

Reserved

-

MSGV1

RO

0x160

Message valid 1

0x0000

Table 1074

MSGV2

RO

0x164

Message valid 2

0x0000

Table 1075

-

-

0x168 0x17C

Reserved

-

CLKDIV

R/W

0x180

CAN clock divider register

0x0001

Table 1076

Table 1034.Register overview: C_CAN1 (base address 0x400A 4000)
Name

Access

Address
offset

Description

Reset
value

Reference

CNTL

R/W

0x000

CAN control

0x0001

Table 1035

STAT

R/W

0x004

Status register

0x0000

Table 1036

EC

RO

0x008

Error counter

0x0000

Table 1037

0x00C

Bit timing register

0x2301

Table 1038

0x0000

Table 1039

BT
INT

RO

0x010

Interrupt register

TEST

R/W

0x014

Test register

-

Table 1040

BRPE

R/W

0x018

Baud rate prescaler extension register

0x0000

Table 1041

-

-

0x01C

Reserved

-

IF1_CMDREQ

R/W

0x020

Message interface 1 command request

0x0001

Table 1044

IF1_CMDMSK_W

R/W

0x024

Message interface 1 command mask (write
direction)

0x0000

Table 1046

IF1_CMDMSK_R

R/W

0x024

Message interface 1 command mask (read
direction)

0x0000

Table 1048

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Chapter 45: LPC43xx/LPC43Sxx C_CAN

Table 1034.Register overview: C_CAN1 (base address 0x400A 4000)
Name

Access

Address
offset

Description

Reset
value

Reference

IF1_MSK1

R/W

0x028

Message interface 1 mask 1

0xFFFF

Table 1050

IF1_MSK2

R/W

0x02C

Message interface 1 mask 2

0xFFFF

Table 1052

IF1_ARB1

R/W

0x030

Message interface 1 arbitration 1

0x0000

Table 1054

IF1_ARB2

R/W

0x034

Message interface 1 arbitration 2

0x0000

Table 1056

IF1_MCTRL

R/W

0x038

Message interface 1 message control

0x0000

Table 1058

IF1_DA1

R/W

0x03C

Message interface 1 data A1

0x0000

Table 1060

IF1_DA2

R/W

0x040

Message interface 1 data A2

0x0000

Table 1061

IF1_DB1

R/W

0x044

Message interface 1 data B1

0x0000

Table 1064

IF1_DB2

R/W

0x048

Message interface 1 data B2

0x0000

Table 1066

0x04C 0x07C

Reserved

-

IF2_CMDREQ

R/W

0x080

Message interface 2 command request

0x0001

Table 1045

IF2_CMDMSK_W

R/W

0x084

Message interface 2 command mask (write
direction)

0x0000

Table 1047

IF2_CMDMSK_R

R/W

0x084

Message interface 2 command mask (read
direction)

0x0000

Table 1049

IF2_MSK1

R/W

0x088

Message interface 2 mask 1

0xFFFF

Table 1051

IF2_MSK2

R/W

0x08C

Message interface 2 mask 2

0xFFFF

Table 1053

IF2_ARB1

R/W

0x090

Message interface 2 arbitration 1

0x0000

Table 1055

IF2_ARB2

R/W

0x094

Message interface 2 arbitration 2

0x0000

Table 1057

IF2_MCTRL

R/W

0x098

Message interface 2 message control

0x0000

Table 1059

IF2_DA1

R/W

0x09C

Message interface 2 data A1

0x0000

Table 1061

IF2_DA2

R/W

0x0A0

Message interface 2 data A2

0x0000

Table 1062

IF2_DB1

R/W

0x0A4

Message interface 2 data B1

0x0000

Table 1065

IF2_DB2

R/W

0x0A8

Message interface 2 data B2

0x0000

Table 1067

-

-

0x0AC 0x0FC

TXREQ1

RO

0x100

Transmission request 1

0x0000

Table 1068

TXREQ2

RO

0x104

Transmission request 2

0x0000

Table 1069

-

-

0x108 0x11C

Reserved

-

ND1

RO

0x120

New data 1

0x0000

Table 1070

ND2

RO

0x124

New data 2

0x0000

Table 1071

-

-

0x128 0x13C

Reserved

-

IR1

RO

0x140

Interrupt pending 1

0x0000

Table 1072

IR2

RO

0x144

Interrupt pending 2

0x0000

Table 1073

-

-

0x148 0x15C

Reserved

-

MSGV1

RO

0x160

Message valid 1

0x0000

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Chapter 45: LPC43xx/LPC43Sxx C_CAN

Table 1034.Register overview: C_CAN1 (base address 0x400A 4000)
Name

Access

Address
offset

Description

Reset
value

Reference

MSGV2

RO

0x164

Message valid 2

0x0000

Table 1075

-

-

0x168 0x17C

Reserved

-

CLKDIV

R/W

0x180

CAN clock divider register

0x0001

Table 1076

45.6.1 CAN protocol registers
45.6.1.1 CAN control register
After a hardware reset, the registers of the C_CAN controller hold the values described in
Table 1033. Additionally, the busoff state is set, and the TD0/1 outputs are set to HIGH.
The reset value 0x0001 of the CANCTRL register enables initialization by software (INIT =
1). The C_CAN does not influence the CAN bus until the CPU resets the INIT bit to 0.
Table 1035.CAN control registers (CNTL, address 0x400E 2000 (C_CAN0) and 0x400A 4000
(C_CAN1)) bit description
Bit

Symbol Value

Description

Reset
value

Access

0

INIT

Initialization

1

R/W

0

R/W

0

R/W

0

R/W

1

2

3

UM10503

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0

Normal operation.

1

Initialization is started. On reset, software
needs to initialize the CAN controller.

IE

Module interrupt enable
0

Disable CAN interrupts. The interrupt line is
always HIGH.

1

Enable CAN interrupts. The interrupt line is set
to LOW and remains LOW until all pending
interrupts are cleared.

SIE

Status change interrupt enable
0

Disable status change interrupts. No status
change interrupt will be generated.

1

Enable status change interrupts. A status
change interrupt will be generated when a
message transfer is successfully completed or
a CAN bus error is detected.

0

Disable error interrupt. No error status interrupt
will be generated.

1

Enable error interrupt. A change in the bits
BOFF or EWARN in the CANSTAT registers
will generate an interrupt.

-

Reserved

0

-

Disable automatic retransmission

0

R/W

EIE

4

-

5

DAR

Error interrupt enable

0

Automatic retransmission of disturbed
messages enabled.

1

Automatic retransmission disabled.

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Chapter 45: LPC43xx/LPC43Sxx C_CAN

Table 1035.CAN control registers (CNTL, address 0x400E 2000 (C_CAN0) and 0x400A 4000
(C_CAN1)) bit description
…continued

Bit

Symbol Value

Description

Reset
value

Access

6

CCE

Configuration change enable

0

R/W

0

R/W

-

-

7

31:8

0

The CPU has no write access to the bit timing
register.

1

The CPU has write access to the CANBT
register while the INIT bit is one.

TEST

-

Test mode enable
0

Normal operation.

1

Test mode.
reserved

Remark: The busoff recovery sequence (see CAN Specification Rev. 2.0) cannot be
shortened by setting or resetting the INIT bit. If the device goes into busoff state, it will set
INIT, stopping all bus activities. Once INIT has been cleared by the CPU, the device will
then wait for 129 occurrences of Bus Idle (129  11 consecutive HIGH/recessive bits)
before resuming normal operations. At the end of the busoff recovery sequence, the Error
Management Counters will be reset.
During the waiting time after the resetting of INIT, each time a sequence of 11
HIGH/recessive bits has been monitored, a Bit0Error code is written to the Status Register
CANSTAT, enabling the CPU to monitor the proceeding of the busoff recovery sequence
and to determine whether the CAN bus is stuck at LOW/dominant or continuously
disturbed.

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Chapter 45: LPC43xx/LPC43Sxx C_CAN

45.6.1.2 CAN status register
Table 1036.CAN status register (STAT, address 0x400E 2004 (C_CAN0) and 0x400A 4004 (C_CAN1)) bit description
Bit

Symbol

2:0

LEC

Value

Description

Reset
value

Access

Last error code

000

R/W

0

R/W

0

R/W

Type of the last error to occur on the CAN bus.The LEC field holds a
code which indicates the type of the last error to occur on the CAN bus.
This field will be cleared to ‘0’ when a message has been transferred
(reception or transmission) without error. The unused code ‘111’ may be
written by the CPU to check for updates.
0x0

No error.

0x1

Stuff error: More than 5 equal bits in a sequence have occurred in a
part of a received message where this is not allowed.

0x2

Form error: A fixed format part of a received frame has the wrong
format.

0x3

AckError: The message this CAN core transmitted was not
acknowledged.

0x4

Bit1Error: During the transmission of a message (with the exception of
the arbitration field), the device wanted to send a HIGH/recessive level
(bit of logical value ‘1’), but the monitored bus value was
LOW/dominant.

0x5

Bit0Error: During the transmission of a message (or acknowledge bit,
or active error flag, or overload flag), the device wanted to send a
LOW/dominant level (data or identifier bit logical value ‘0’), but the
monitored Bus value was HIGH/recessive. During busoff recovery this
status is set each time a

sequence of 11 HIGH/recessive bits has been monitored. This enables
the CPU to monitor the proceeding of the busoff recovery sequence
(indicating the bus is not stuck at LOW/dominant or continuously
disturbed).

3

0x6

CRCError: The CRC checksum was incorrect in the message received.

0x7

Unused: No CAN bus event was detected (written by the CPU).

TXOK

Transmitted a message successfully
The CPU must reset this bit. It is never reset by the CAN controller.

4

0

Since this bit must be reset by the CPU, no message has been
successfully transmitted.

1

Since this bit was last reset by the CPU, a message has been
successfully transmitted (error free and acknowledged by at least one
other node).

RXOK

Received a message successfully
The CPU must reset this bit. It is never reset by the CAN controller.

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0

Since this bit was last reset by the CPU, no message has been
successfully received.

1

Since this bit was last set to zero by the CPU, a message has been
successfully received independent of the result of acceptance filtering.

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Chapter 45: LPC43xx/LPC43Sxx C_CAN

Table 1036.CAN status register (STAT, address 0x400E 2004 (C_CAN0) and 0x400A 4004 (C_CAN1)) bit description
…continued

Bit

Symbol

5

EPASS

6

Value

-

Access

Error passive

0

RO

0

RO

0

RO

The CAN controller is in the error active state.

1

The CAN controller is in the error passive state as defined in the CAN
2.0 specification.

0

Both error counters are below the error warning limit of 96.

1

At least one of the error counters in the EC has reached the error
warning limit of 96.

0

The CAN module is not in busoff state.

1

The CAN controller is in busoff state.

-

reserved

Warning status

BOFF

31:8

Reset
value

0

EWARN

7

Description

Busoff status

A status interrupt is generated by bits BOFF, EWARN, RXOK, TXOK, or LEC. BOFF and
EWARN generate an error interrupt, and RXOK, TXOK, and LEC generate a status
change interrupt if EIE and SIE respectively are set to enabled in the CANCTRL register.
A change of bit EPASS and a write to RXOK, TXOK, or LEC will never create a status
interrupt.
Reading the CANSTAT register will clear the Status Interrupt value in the CANIR register.

45.6.1.3 CAN error counter
Table 1037.CAN error counter (EC, address 0x400E 2008 (C_CAN0) and 0x400A 4008 (C_CAN1)) bit description
Bit

Symbol

7:0
14:8

Value

Description

Reset
value

Access

TEC_7_0

Transmit error counter

0

RO

REC_6_0

Receive error counter

0

RO

0

RO

-

-

Current value of the transmit error counter (maximum value 255)
Current value of the receive error counter (maximum value 127).
15

RP

31:16 -

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Receive error passive
0

The receive counter is below the error passive level.

1

The receive counter has reached the error passive level as defined in the
CAN2.0 specification.

-

Reserved

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Chapter 45: LPC43xx/LPC43Sxx C_CAN

45.6.1.4 CAN bit timing register
Table 1038.CAN bit timing register (BT, address 0x400E 200C (C_CAN0) and 0x400A 400C
(C_CAN1)) bit description
Bit

Symbol

Description

Reset
value

Access

5:0

BRP

Baud rate prescaler

1

R/W

0

R/w

0011

R/W

010

R/W

-

-

The value by which the oscillator frequency is divided
for generating the bit time quanta. The bit time is built up
from a multiple of this quanta. Valid values for the Baud
Rate Prescaler are 0 to 63[1].
Valid programmed values are 0x01 - 0x3F[1].
7:6

SJW

(Re)synchronization jump width
Valid programmed values are 0 to

11:8

TSEG1

3[1].

Time segment before the sample point including
propagation time segment.
Valid values are 1 to 15[1].

14:12

TSEG2

Time segment after the sample point
Valid values are 0 to 7[1].

31:15
[1]

-

Reserved

Hardware interprets the value programmed into these bits as the bit value  1.

Remark: With a module clock CAN_CLK of 8 MHz, the reset value of 0x2301 configures
the C_CAN for a bit rate of 500 kBit/s. The registers are only writable if a configuration
change is enabled in CANCTRL and the controller is initialized by software (bits CCE and
INIT in the CAN Control Register are set).

45.6.1.5 CAN interrupt register
Table 1039.CAN interrupt register (INT, address 0x400E 2010 (C_CAN0) and 0x400A 4010
(C_CAN1)) bit description
Bit

Symbol

Description

Reset
value

15:0

INTID15_0

0x0000 = No interrupt is pending
0
0x0001 to 0x0020 = Number of message object which
caused the interrupt.
0x0021 to 0x7FFF = Unused
0x8000 = Status interrupt
0x8001 to 0xFFFF = Unused

R

31:16

-

Reserved

-

-

Access

If several interrupts are pending, the CAN Interrupt Register will point to the pending
interrupt with the highest priority, disregarding their chronological order. An interrupt
remains pending until the CPU has cleared it. If INTID is different from 0x0000 and IE is
set, the interrupt line to the CPU is active. The interrupt line remains active until INTID is
back to value 0x0000 (the cause of the interrupt is reset) or until IE is reset.
The Status Interrupt has the highest priority. Among the message interrupts, the Message
Object’ s interrupt priority decreases with increasing message number.
A message interrupt is cleared by clearing the Message Object’s INTPND bit. The
StatusInterrupt is cleared by reading the Status Register.
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Chapter 45: LPC43xx/LPC43Sxx C_CAN

45.6.1.6 CAN test register
Write access to the Test Register is enabled by setting bit Test in the CAN Control
Register.
The different test functions may be combined, but when TX[1:0]  “00” is selected, the
message transfer is disturbed.
Table 1040.CAN test register (TEST, address 0x400E 2014 (C_CAN0) and 0x400A 4014
(C_CAN1)) bit description
Bit

Symbol

Value

1:0

-

-

2

BASIC

3

4

0

Basic mode disabled.

1

IF1 registers used as TX buffer, IF2 registers
used as RX buffer.

SILENT

Silent mode
0

Normal operation.

1

The module is in silent mode.

LBACK

Loop back mode
1

7

31:8

TX1_0

-

Access

0

R/W

0

R/W

0

R/W

00

R/W

0

R

Loop back mode is disabled.
Loop back mode is enabled.
Control of TD pins

0x0

Level at the TD pin is controlled by the CAN
controller. This is the value at reset.

0x1

The sample point can be monitored at the TD
pin.

0x2

TD pin is driven LOW/dominant.

0x3

TD pin is driven HIGH/recessive.

RX

Reset
value

Basic mode

0
6:5

Description

Monitors the actual value of the RD Pin
0

The CAN bus is dominant (RD = 0).

1

The CAN bus is recessive (RD = 1).
Reserved

-

45.6.1.7 CAN baud rate prescaler extension register
Table 1041.CAN baud rate prescaler extension register (BRPE, address 0x400E 2018
(C_CAN0) and 0x400A 4018 (C_CAN1)) bit description
Bit

Symbol

Description

Reset
value

Access

3:0

BRPE

Baud rate prescaler extension

0x0000 R/W

By programming BRPE the Baud Rate Prescaler
can be extended to values up to 1023. Hardware
interprets the value as the value of BRPE (MSBs)
and BRP (LSBs) plus one.
Allowed values are 0x00 to 0x0F
31:4

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-

Reserved

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Chapter 45: LPC43xx/LPC43Sxx C_CAN

45.6.2 Message interface registers
There are two sets of interface registers which are used to control the CPU access to the
Message RAM. The interface registers avoid conflicts between CPU access to the
Message RAM and CAN message reception and transmission by buffering the data to be
transferred. A complete Message Object (see Section 45.6.2.1) or parts of the Message
Object may be transferred between the Message RAM and the IFx Message Buffer
registers in one single transfer.
The function of the two interface register sets is identical (except for test mode Basic).
One set of registers may be used for data transfer to the Message RAM while the other
set of registers may be used for the data transfer from the Message RAM, allowing both
processes to be interrupted by each other.
Each set of interface registers consists of message buffer registers controlled by their own
command registers. The command mask register specifies the direction of the data
transfer and which parts of a message object will be transferred. The command request
register is used to select a message object in the message RAM as target or source for
the transfer and to start the action specified in the command mask register.

transfer a
message object

transfer a
CAN frame

INTERFACE
COMMAND REGISTERS
IF1 COMMAND REQUEST
IF1 COMMAND MASK
IF2 COMMAND REQUEST
IF2 COMMAND MASK
MESSAGE BUFFER
REGISTERS

MESSAGE RAM

read transfer
write transfer

IF1 MASK1, 2
IF1 ARBITRATION 1/2
IF1 MESSAGE CTRL
IF1 DATA A1/2
IF1 DATA B1/2

APB
bus

MESSAGE OBJECT 1
MESSAGE OBJECT 2
.
.
.
MESSAGE OBJECT 32

IF2 MASK1, 2
IF2 ARBITRATION 1/2
IF2 MESSAGE CTRL
IF2 DATA A1/2
IF2 DATA B1/2
MESSAGE HANDLER

receive
CAN CORE/
SHIFT REGISTERS

transmit

CAN
bus

TRANSMISSION REQUEST 1/2
NEW DATA 1/2
INTERRUPT PENDING1/2
MESSAGE VALID1/2

Fig 164. Block diagram of a message object transfer

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User manual

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Chapter 45: LPC43xx/LPC43Sxx C_CAN

Table 1042.Message interface registers
IF1 register names

IF1 register set

IF2 register names

IF2 register set

IF1_CMDREQ

IF1 command request

IF2_CMDREQ

IF2 command request

IF1_CMDMASK

IF1 command mask

IF2_CMDMASK

IF2 command mask

IF1_MASK1

IF1 mask 1

IF2_MSK1

IF2 mask 1

IF1_MASK2

IF1 mask 2

IF2_MSK2

IF2 mask 2

IF1_ARB1

IF1 arbitration 1

IF2_ARB1

IF2 arbitration 1

IF1_ARB2

IF1 arbitration 2

IF2_ARB2

IF2 arbitration 2

IF1_MCTRL

IF1 message control

IF2_MCTRL

IF2 message control

IF1_DA1

IF1 data A1

IF2_DA1

IF2 data A1

IF1_DA2

IF1 data A2

IF2_DA2

IF2 data A2

CIF1_DB1

IF1 data B1

IF2_DB1

IF2 data B1

IF1_DB2

IF1 data B2

IF2_DB2

IF2 data B2

There are 32 Message Objects in the Message RAM. To avoid conflicts between CPU
access to the Message RAM and CAN message reception and transmission, the CPU
cannot directly access the Message Objects. The message objects are accessed through
the IFx Interface Registers.

45.6.2.1 Message objects
A message object contains the information from the various bits in the message interface
registers. Table 1043 below shows a schematic representation of the structure of the
message object. The bits of a message object and the respective interface register where
this bit is set or cleared are shown. For bit functions see the corresponding interface
register.
Table 1043.Structure of a message object in the message RAM
UMASK

MSK[28:0]

IF1/2_MCTRL
RMTEN

TXRQST

MXTD

IF1/2_DA1

DATA1

EOB

NEWDAT

MSGLST

IF1/2_MSK1/2
MSGVAL

IF1/2_MCTRL
DATA0

MDIR

RXIE

INTPND

IF1/2_MCTRL

ID[28:0]

XTD

DIR

DLC3

DLC2

IF1/2_ARB1/2
DATA2

TXIE

DATA3

IF1/2_DA2

DATA4

DLC1

DLC0

IF1/2_MCTRL
DATA5

DATA6

IF1/2_DB1

DATA7

IF1/2_DB2

45.6.2.2 CAN message interface command request registers
A message transfer is started as soon as the CPU has written the message number to the
Command Request Register. With this write operation the BUSY bit is automatically set to
‘1’ and the signal CAN_WAIT_B is pulled LOW) to notify the CPU that a transfer is in
progress. After a wait time of 3 to 6 CAN_CLK periods, the transfer between the Interface
Register and the Message RAM has completed. The BUSY bit is set back to zero and the
signal CAN_WAIT_B is set back).

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Chapter 45: LPC43xx/LPC43Sxx C_CAN

Table 1044.CAN message interface command request registers (IF1_CMDREQ, address
0x400E 2020 (C_CAN0) and 0x400A 4020 (C_CAN1)) bit description
Bit

Symbol

Description

5:0

Message Number Message number
0x01 to 0x20 = Valid message numbers

Reset
value

Access

0x01

R/W

0

R

-

-

The message object in the message RAM is
selected for data transfer.
0x00 = Not a valid message number. This
value is interpreted as 0x20.[1]
0x21 to 0x3F = Not a valid message number.
This value is interpreted as 0x01 - 0x1F.[1]
14:6

-

Reserved

15

BUSY

BUSY flag
Set to one by hardware when writing to this
Command request register.
Set to zero by hardware when read/write
action to this Command request register has
finished.

31:16
[1]

-

Reserved

When a message number that is not valid is written into the Command request registers, the message
number will be transformed into a valid value and that message object will be transferred.

Table 1045.CAN message interface command request registers (IF2_CMDREQ, address
0x400E 2080 (C_CAN0) and 0x400A 4080 (C_CAN1)) bit description
Bit

Symbol

Description

5:0

Message Number Message number
0x01 to 0x20 = Valid message numbers

Reset
value

Access

0x01

R/W

0

R

-

-

The message object in the message RAM is
selected for data transfer.
0x00 = Not a valid message number. This
value is interpreted as 0x20.[1]
0x21 to 0x3F = Not a valid message number.
This value is interpreted as 0x01 - 0x1F.[1]
14:6

-

Reserved

15

BUSY

BUSY flag
Set to one by hardware when writing to this
Command request register.
Set to zero by hardware when read/write
action to this Command request register has
finished.

31:16
[1]

UM10503

User manual

-

Reserved

When a message number that is not valid is written into the Command request registers, the message
number will be transformed into a valid value and that message object will be transferred.

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Chapter 45: LPC43xx/LPC43Sxx C_CAN

45.6.2.3 CAN message interface command mask registers
The control bits of the IFx Command Mask Register specify the transfer direction and
select which of the IFx Message Buffer Registers are source or target of the data
transfer.The functions of the register bits depend on the transfer direction (read or write)
which is selected in the WR/RD bit (bit 7) of this Command mask register.
Select the WR/RD to
one for the Write transfer direction (write to message RAM)
zero for the Read transfer direction (read from message RAM)
Transfer direction Write
Table 1046.CAN message interface command mask registers write direction
(IF1_CMDMSK_W, address 0x400E 2024 (C_CAN0) and 0x400A 4024 (C_CAN1))
bit description
Bit

Symbol

0

DATA_B

1

2

Value Description

Access data bytes 4-7
0

Data bytes 4-7 unchanged.

1

Transfer data bytes 4-7 to message object.

DATA_A

Access data bytes 0-3
0

Data bytes 0-3 unchanged.

1

Transfer data bytes 0-3 to message object.

TXRQST

Access transmission request bit
0

Reset
value

Access

0

R/W

0

R/W

0

R/W

No transmission request. TXRQSRT bit
unchanged in IF1/2_MCTRL.
Remark: If a transmission is requested by
programming this bit, the TXRQST bit in the
CANIFn_MCTRL register is ignored.

3

CLRINTPND

4

CTRL

5

UM10503

User manual

1

Request a transmission. Set the TXRQST bit
IF1/2_MCTRL.

-

This bit is ignored in the write direction.

0

R/W

Access control bits

0

R/W

0

R/W

0

Control bits unchanged.

1

Transfer control bits to message object

ARB

Access arbitration bits
0

Arbitration bits unchanged.

1

Transfer Identifier, DIR, XTD, and MSGVAL
bits to message object.

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Chapter 45: LPC43xx/LPC43Sxx C_CAN

Table 1046.CAN message interface command mask registers write direction
(IF1_CMDMSK_W, address 0x400E 2024 (C_CAN0) and 0x400A 4024 (C_CAN1))
bit description …continued
Bit

Symbol

6

MASK

7

Value Description

Access mask bits

WR_RD

0

Mask bits unchanged.

1

Transfer Identifier MASK + MDIR + MXTD to
message object.

1

Write transfer

Reset
value

Access

0

R/W

0

R/W

0

-

Transfer data from the selected message
buffer registers to the message object
addressed by the command request register
CANIFn_CMDREQ.
31:8

-

-

reserved

Table 1047.CAN message interface command mask registers write direction
(IF2_CMDMSK_W, address 0x400E 2084 (C_CAN0) and 0x400A 4084 (C_CAN1))
bit description
Bit

Symbol

0

DATA_B

1

2

Value Description

Access data bytes 4-7
0

Data bytes 4-7 unchanged.

1

Transfer data bytes 4-7 to message object.

DATA_A

Access data bytes 0-3
0

Data bytes 0-3 unchanged.

1

Transfer data bytes 0-3 to message object.

TXRQST

Access transmission request bit
0

Reset
value

Access

0

R/W

0

R/W

0

R/W

No transmission request. TXRQSRT bit
unchanged in IF1/2_MCTRL.
Remark: If a transmission is requested by
programming this bit, the TXRQST bit in the
CANIFn_MCTRL register is ignored.

3

CLRINTPND

4

CTRL

5

UM10503

User manual

1

Request a transmission. Set the TXRQST bit
IF1/2_MCTRL.

-

This bit is ignored in the write direction.

0

R/W

Access control bits

0

R/W

0

R/W

0

Control bits unchanged.

1

Transfer control bits to message object

ARB

Access arbitration bits
0

Arbitration bits unchanged.

1

Transfer Identifier, DIR, XTD, and MSGVAL
bits to message object.

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Chapter 45: LPC43xx/LPC43Sxx C_CAN

Table 1047.CAN message interface command mask registers write direction
(IF2_CMDMSK_W, address 0x400E 2084 (C_CAN0) and 0x400A 4084 (C_CAN1))
bit description …continued
Bit

Symbol

6

MASK

7

Value Description

Access mask bits

WR_RD

0

Mask bits unchanged.

1

Transfer Identifier MASK + MDIR + MXTD to
message object.

1

Write transfer

Reset
value

Access

0

R/W

0

R/W

0

-

Transfer data from the selected message
buffer registers to the message object
addressed by the command request register
CANIFn_CMDREQ.
31:8

-

-

reserved

Transfer direction Read
Table 1048.CAN message interface command mask registers read direction
(IF1_CMDMSK_R, address 0x400E 2024 (C_CAN0) and 0x400A 4024 (C_CAN1)) bit
description
Bit

Symbol

0

DATA_B

1

2

Value Description

Access data bytes 4-7
0

data bytes 4-7 unchanged.

1

Transfer data bytes 4-7 to IFx message buffer
register.

DATA_A

Access data bytes 0-3
0

data bytes 0-3 unchanged.

1

Transfer data bytes 0-3 to IFx message
buffer.

NEWDAT

Access new data bit
0

Reset
value

Access

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

NEWDAT bit remains unchanged.
Remark: A read access to a message object
can be combined with the reset of the control
bits INTPND and NEWDAT in IF1/2_MCTRL.
The values of these bits transferred to the IFx
Message Control Register always reflect the
status before resetting these bits.

1
3

4

UM10503

User manual

CLRINTPND

Clear NEWDAT bit in the message object.
Clear interrupt pending bit.

0

INTPND bit remains unchanged.

1

Clear INTPND bit in the message object.

CTRL

Access control bits
0

Control bits unchanged.

1

Transfer control bits to IFx message buffer.

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Chapter 45: LPC43xx/LPC43Sxx C_CAN

Table 1048.CAN message interface command mask registers read direction
(IF1_CMDMSK_R, address 0x400E 2024 (C_CAN0) and 0x400A 4024 (C_CAN1)) bit
description …continued
Bit

Symbol

5

ARB

6

7

Value Description

Access arbitration bits
0

Arbitration bits unchanged.

1

Transfer Identifier, DIR, XTD, and MSGVAL
bits to IFx message buffer register.

MASK

Access mask bits

WR_RD

0

Mask bits unchanged.

1

Transfer Identifier MASK + MDIR + MXTD to
IFx message buffer register.

0

Read transfer

Reset
value

Access

0

R/W

0

R/W

0

R/W

0

-

Transfer data from the message object
addressed by the command request register
to the selected message buffer registers
CANIFn_CMDREQ.
31:8

-

-

reserved

Table 1049.CAN message interface command mask registers read direction
(IF2_CMDMSK_R, address 0x400E 2084 (C_CAN0) and 0x400A 4084 (C_CAN1)) bit
description
Bit

Symbol

0

DATA_B

1

2

Value Description

Access data bytes 4-7
0

data bytes 4-7 unchanged.

1

Transfer data bytes 4-7 to IFx message buffer
register.

DATA_A

Access data bytes 0-3
0

data bytes 0-3 unchanged.

1

Transfer data bytes 0-3 to IFx message
buffer.

NEWDAT

Access new data bit
0

Reset
value

Access

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

NEWDAT bit remains unchanged.
Remark: A read access to a message object
can be combined with the reset of the control
bits INTPND and NEWDAT in IF1/2_MCTRL.
The values of these bits transferred to the IFx
Message Control Register always reflect the
status before resetting these bits.

1
3

4

UM10503

User manual

CLRINTPND

Clear NEWDAT bit in the message object.
Clear interrupt pending bit.

0

INTPND bit remains unchanged.

1

Clear INTPND bit in the message object.

0

Control bits unchanged.

1

Transfer control bits to IFx message buffer.

CTRL

Access control bits

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Chapter 45: LPC43xx/LPC43Sxx C_CAN

Table 1049.CAN message interface command mask registers read direction
(IF2_CMDMSK_R, address 0x400E 2084 (C_CAN0) and 0x400A 4084 (C_CAN1)) bit
description …continued
Bit

Symbol

5

ARB

6

Value Description

Access arbitration bits
0

Arbitration bits unchanged.

1

Transfer Identifier, DIR, XTD, and MSGVAL
bits to IFx message buffer register.

MASK

7

Access mask bits

WR_RD

0

Mask bits unchanged.

1

Transfer Identifier MASK + MDIR + MXTD to
IFx message buffer register.

0

Read transfer

Reset
value

Access

0

R/W

0

R/W

0

R/W

0

-

Transfer data from the message object
addressed by the command request register
to the selected message buffer registers
CANIFn_CMDREQ.
31:8

-

-

reserved

45.6.2.4 IF1 and IF2 message buffer registers
The bits of the Message Buffer registers mirror the Message Objects in the Message
RAM.
45.6.2.4.1

CAN message interface command mask 1 registers
Table 1050.CAN message interface command mask 1 registers (IF1_MSK1, address
0x400E 2028 (C_CAN0) and 0x400A 4028 (C_CAN1)) bit description
Bit

Symbol

Description

Reset
value

Access

15:0

MSK15_0

Identifier mask
0xFFFF R/W
0 = The corresponding bit in the identifier of the message
can not inhibit the match in the acceptance filtering.
1 = The corresponding identifier bit is used for
acceptance filtering.

31:16

-

reserved

0

-

Table 1051.CAN message interface command mask 1 registers (IF2_MSK1, address
0x400E 2088 (C_CAN0) and 0x400A 4088 (C_CAN1)) bit description

UM10503

User manual

Bit

Symbol

Description

15:0

MSK15_0

Identifier mask
0xFFFF R/W
0 = The corresponding bit in the identifier of the message
can not inhibit the match in the acceptance filtering.
1 = The corresponding identifier bit is used for
acceptance filtering.

31:16

-

reserved

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Reset
value

0

Access

-

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Chapter 45: LPC43xx/LPC43Sxx C_CAN

45.6.2.4.2

CAN message interface command mask 2 registers
Table 1052.CAN message interface command mask 2 registers (IF1_MSK2, address
0x400E 202C (C_CAN0) and 0x400A 402C (C_CAN1)) bit description
Bit

Symbol

12:0

MSK28_16

13
14

15

31:16

Value Description

Reset
value

Access

Identifier mask
0 = The corresponding bit in the identifier of the
message can not inhibit the match in the
acceptance filtering.
1 = The corresponding identifier bit is used for
acceptance filtering.

0xFFF

R/W

-

Reserved

1

-

MDIR

Mask message direction

1

R/W

1

R/W

0

-

0

The message direction bit (DIR) has no effect on
acceptance filtering.

1

The message direction bit (DIR) is used for
acceptance filtering.

0

The extended identifier bit (IDE) has no effect on
acceptance filtering.

1

The extended identifier bit (IDE) is used for
acceptance filtering.

-

Reserved

MXTD

Mask extend identifier

-

Table 1053.CAN message interface command mask 2 registers (IF2_MSK2, 0x400E 208C
(C_CAN0) and 0x400A 408C (C_CAN1)) bit description
Bit

Symbol

12:0

MSK28_16

13
14

15

31:16

UM10503

User manual

Value Description

Reset
value

Access

Identifier mask
0 = The corresponding bit in the identifier of the
message can not inhibit the match in the
acceptance filtering.
1 = The corresponding identifier bit is used for
acceptance filtering.

0xFFF

R/W

-

Reserved

1

-

MDIR

Mask message direction

1

R/W

1

R/W

0

-

0

The message direction bit (DIR) has no effect on
acceptance filtering.

1

The message direction bit (DIR) is used for
acceptance filtering.

MXTD

-

Mask extend identifier
0

The extended identifier bit (IDE) has no effect on
acceptance filtering.

1

The extended identifier bit (IDE) is used for
acceptance filtering.

-

Reserved

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Chapter 45: LPC43xx/LPC43Sxx C_CAN

45.6.2.4.3

CAN message interface command arbitration 1 registers
Table 1054.CAN message interface command arbitration 1 registers (IF1_ARB1, address
0x400E 2030 (C_CAN0) and 0x400A 4030 (C_CAN1)) bit description
Bit

Symbol

15:0

ID15_0

Description

Reset
value

Access

Message identifier

0x00

R/W

0

-

29-bit identifier (“extended frame”)
11-bit identifier (“standard frame”)
31:16

-

Reserved

Table 1055.CAN message interface command arbitration 1 registers (IF2_ARB1, address
0x400E 2090 (C_CAN0) and 0x400A 4090 (C_CAN1)) bit description
Bit

Symbol

Description

Reset
value

Access

15:0

ID15_0

Message identifier

0x00

R/W

0

-

29-bit identifier (“extended frame”)
11-bit identifier (“standard frame”)
31:16

45.6.2.4.4

-

Reserved

CAN message interface command arbitration 2 registers
Table 1056.CAN message interface command arbitration 2 registers (IF1_ARB2, address
0x400E 2034 (C_CAN0) and 0x400A 4034 (C_CAN1)) bit description
Bit

Symbol

12:0

ID28_16

Value Description

Message identifier

Reset
value

Access

0x00

R/W

0x00

R/W

0x00

R/W

29-bit identifier (“extended frame”)
11-bit identifier (“standard frame”)
13

DIR

Message direction
0

Direction = receive.
On TXRQST, a Remote Frame with the identifier
of this Message Object is transmitted. On
reception of a Data Frame with matching
identifier, that message is stored in this Message
Object.

1

Direction = transmit.
On TXRQST, the respective Message Object is
transmitted as a Data Frame. On reception of a
Remote Frame with matching identifier, the
TXRQST bit of this Message Object is set (if
RMTEN = one).

14

UM10503

User manual

XTD

Extend identifier
0

The 11-bit standard identifier will be used for this
message object.

1

The 29-bit extended identifier will be used for this
message object.

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Chapter 45: LPC43xx/LPC43Sxx C_CAN

Table 1056.CAN message interface command arbitration 2 registers (IF1_ARB2, address
0x400E 2034 (C_CAN0) and 0x400A 4034 (C_CAN1)) bit description …continued
Bit

Symbol

15

MSGVAL

Value Description

Message valid

Reset
value

Access

0

R/W

0

-

Remark: The MSGVAL bit of all unused
Messages Objects is reset during the initialization
before bit INIT is reset in the CAN Control
Register. This bit must be set to zero before the
identifier ID28:0, the control bits XTD, DIR, or the
Data Length Code DLC3:0 are modified, or if the
Messages Object is no longer required.

31:16

-

0

The message object is ignored by the message
handler.

1

The message object is configured and should be
considered by the message handler.

-

Reserved

Table 1057.CAN message interface command arbitration 2 registers (IF2_ARB2, address
0x400E 2094 (C_CAN0) and 0x400A 4094 (C_CAN1)) bit description
Bit

Symbol

12:0

ID28_16

Value Description

Message identifier

Reset
value

Access

0x00

R/W

0x00

R/W

0x00

R/W

29-bit identifier (“extended frame”)
11-bit identifier (“standard frame”)
13

DIR

Message direction
0

Direction = receive.
On TXRQST, a Remote Frame with the identifier
of this Message Object is transmitted. On
reception of a Data Frame with matching
identifier, that message is stored in this Message
Object.

1

Direction = transmit.
On TXRQST, the respective Message Object is
transmitted as a Data Frame. On reception of a
Remote Frame with matching identifier, the
TXRQST bit of this Message Object is set (if
RMTEN = one).

14

UM10503

User manual

XTD

Extend identifier
0

The 11-bit standard identifier will be used for this
message object.

1

The 29-bit extended identifier will be used for this
message object.

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Chapter 45: LPC43xx/LPC43Sxx C_CAN

Table 1057.CAN message interface command arbitration 2 registers (IF2_ARB2, address
0x400E 2094 (C_CAN0) and 0x400A 4094 (C_CAN1)) bit description …continued
Bit

Symbol

15

MSGVAL

Value Description

Message valid

Reset
value

Access

0

R/W

0

-

Remark: The MSGVAL bit of all unused
Messages Objects is reset during the initialization
before bit INIT is reset in the CAN Control
Register. This bit must be set to zero before the
identifier ID28:0, the control bits XTD, DIR, or the
Data Length Code DLC3:0 are modified, or if the
Messages Object is no longer required.

31:16

45.6.2.4.5

-

0

The message object is ignored by the message
handler.

1

The message object is configured and should be
considered by the message handler.

-

Reserved

CAN message interface message control registers
Table 1058.CAN message interface message control registers (IF1_MCTRL, address
0x400E 2038 (C_CAN0) and 0x400A 4038 (C_CAN1)) bit description
Bit

Symbol

3:0

DLC3_0

Value

Description

Reset
value

Access

Data length code

0000

R/W

reserved

-

-

End of buffer

0

R/W

0

R/W

0

R/W

Remark: The Data Length Code of a Message
Object must be defined the same as in all the
corresponding objects with the same identifier at
other nodes. When the Message Handler stores
a data frame, it will write the DLC to the value
given by the received message.
0000 to 1000 = Data frame has 0 - 8 data bytes.
1001 to 1111 = Data frame has 8 data bytes.

6:4

-

7

EOB

8

9

UM10503

User manual

0

Message object belongs to a FIFO buffer and is
not the last message object of that FIFO buffer.

1

Single message object or last message object of
a FIFO buffer.

TXRQST

Transmit request
0

This message object is not waiting for
transmission.

1

The transmission of this message object is
requested and is not yet done

RMTEN

Remote enable
0

At the reception of a remote frame, TXRQST is
left unchanged.

1

At the reception of a remote frame, TXRQST is
set.

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Table 1058.CAN message interface message control registers (IF1_MCTRL, address
0x400E 2038 (C_CAN0) and 0x400A 4038 (C_CAN1)) bit description …continued
Bit

Symbol

10

RXIE

11

12

Value

Description

Reset
value

Access

Receive interrupt enable

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

-

0

INTPND will be left unchanged after successful
reception of a frame.

1

INTPND will be set after successful reception of
a frame.

TXIE

Transmit interrupt enable
0

The INTPND bit will be left unchanged after a
successful transmission of a frame.

1

INTPND will be set after a successful
transmission of a frame.

UMASK

Use acceptance mask
Remark: If UMASK is set to 1, the message
object’s mask bits have to be programmed
during initialization of the message object before
MAGVAL is set to 1.

13

14

15

User manual

Mask ignored.

1

Use mask (MSK[28:0], MXTD, and MDIR) for
acceptance filtering.

INTPND

Interrupt pending
0

This message object is not the source of an
interrupt.

1

This message object is the source of an
interrupt. The Interrupt Identifier in the Interrupt
Register will point to this message object if there
is no other interrupt source with higher priority.

MSGLST

Message lost (only valid for message objects in
the direction receive).
0

No message lost since this bit was reset last by
the CPU.

1

The Message Handler stored a new message
into this object when NEWDAT was still set, the
CPU has lost a message.

NEWDAT

31:16 -

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0

New data
0

No new data has been written into the data
portion of this message object by the message
handler since this flag was cleared last by the
CPU.

1

The message handler or the CPU has written
new data into the data portion of this message
object.

-

Reserved

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Table 1059.CAN message interface message control registers (IF2_MCTRL, address
0x400E 2098 (C_CAN0) and 0x400A 4098 (C_CAN1)) bit description
Bit

Symbol

3:0

DLC3_0

Value

Description

Reset
value

Access

Data length code

0000

R/W

Remark: The Data Length Code of a Message
Object must be defined the same as in all the
corresponding objects with the same identifier at
other nodes. When the Message Handler stores
a data frame, it will write the DLC to the value
given by the received message.
0000 to 1000 = Data frame has 0 - 8 data bytes.
1001 to 1111 = Data frame has 8 data bytes.

6:4

-

reserved

-

-

7

EOB

End of buffer

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

8

9

10

11

12

0

Message object belongs to a FIFO buffer and is
not the last message object of that FIFO buffer.

1

Single message object or last message object of
a FIFO buffer.

TXRQST

Transmit request
0

This message object is not waiting for
transmission.

1

The transmission of this message object is
requested and is not yet done

RMTEN

Remote enable
0

At the reception of a remote frame, TXRQST is
left unchanged.

1

At the reception of a remote frame, TXRQST is
set.

RXIE

Receive interrupt enable
0

INTPND will be left unchanged after successful
reception of a frame.

1

INTPND will be set after successful reception of
a frame.

TXIE

Transmit interrupt enable
0

The INTPND bit will be left unchanged after a
successful reception of a frame.

1

INTPND will be set after a successful reception
of a frame.

UMASK

Use acceptance mask
Remark: If UMASK is set to 1, the message
object’s mask bits have to be programmed
during initialization of the message object before
MAGVAL is set to 1.

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0

Mask ignored.

1

Use mask (MSK[28:0], MXTD, and MDIR) for
acceptance filtering.

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Table 1059.CAN message interface message control registers (IF2_MCTRL, address
0x400E 2098 (C_CAN0) and 0x400A 4098 (C_CAN1)) bit description …continued
Bit

Symbol

13

INTPND

14

15

Description

Reset
value

Access

Interrupt pending

0

R/W

0

R/W

0

R/W

0

-

0

This message object is not the source of an
interrupt.

1

This message object is the source of an
interrupt. The Interrupt Identifier in the Interrupt
Register will point to this message object if there
is no other interrupt source with higher priority.

MSGLST

Message lost (only valid for message objects in
the direction receive).
0

No message lost since this bit was reset last by
the CPU.

1

The Message Handler stored a new message
into this object when NEWDAT was still set, the
CPU has lost a message.

NEWDAT

31:16 -

45.6.2.4.6

Value

New data
0

No new data has been written into the data
portion of this message object by the message
handler since this flag was cleared last by the
CPU.

1

The message handler or the CPU has written
new data into the data portion of this message
object.

-

Reserved

CAN message interface data A1 registers
In a CAN Data Frame, DATA0 is the first, DATA7 (in CAN_IF1B2 AND CAN_IF2B2) is the
last byte to be transmitted or received. In CAN’s serial bit stream, the MSB of each byte
will be transmitted first.
Remark: Byte DATA0 is the first data byte shifted into the shift register of the CAN Core
during a reception, byte DATA7 is the last. When the Message Handler stores a Data
Frame, it will write all the eight data bytes into a Message Object. If the Data Length Code
is less than 8, the remaining bytes of the Message Object will be overwritten by non
specified values.
Table 1060.CAN message interface data A1 registers (IF1_DA1, address 0x400E 203C
(C_CAN0) and 0x400A 403C (C_CAN1)) bit description

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Bit

Symbol Description

Reset value Access

7:0

DATA0

Data byte 0

0x00

R/W

15:8

DATA1

Data byte 1

0x00

R/W

31:16

-

Reserved

-

-

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Table 1061.CAN message interface data A1 registers (IF2_DA1, address 0x400E 209C
(C_CAN0) and 0x400A 409C (C_CAN1)) bit description

45.6.2.4.7

Bit

Symbol Description

Reset value Access

7:0

DATA0

Data byte 0

0x00

R/W

15:8

DATA1

Data byte 1

0x00

R/W

31:16

-

Reserved

-

-

CAN message interface data A2 registers
Table 1062.CAN message interface data A2 registers (IF1_DA2, address 0x400E 2040
(C_CAN0) and 0x400A 4040 (C_CAN1)) bit description
Bit

Symbol Description

Reset value Access

7:0

DATA2

Data byte 2

0x00

R/W

15:8

DATA3

Data byte 3

0x00

R/W

31:16

-

Reserved

-

-

Table 1063.CAN message interface data A2 registers (IF2_DA2, address 0x400E 20A0
(C_CAN0) and 0x400A 40A0 (C_CAN1)) bit description

45.6.2.4.8

Bit

Symbol Description

Reset value Access

7:0

DATA2

Data byte 2

0x00

R/W

15:8

DATA3

Data byte 3

0x00

R/W

31:16

-

Reserved

-

-

CAN message interface data B1 registers
Table 1064.CAN message interface data B1 registers (IF1_DB1, address 0x400E 2044
(C_CAN0) and 0x400A 4044 (C_CAN1)) bit description
Bit

Symbol Description

Reset value Access

7:0

DATA4

Data byte 4

0x00

R/W

15:8

DATA5

Data byte 5

0x00

R/W

31:16

-

Reserved

-

-

Table 1065.CAN message interface data B1 registers (IF2_DB1, address 0x400E 20A4
(C_CAN0) and 0x400A 40A4 (C_CAN1)) bit description

45.6.2.4.9

Bit

Symbol Description

Reset value Access

7:0

DATA4

Data byte 4

0x00

R/W

15:8

DATA5

Data byte 5

0x00

R/W

31:16

-

Reserved

-

-

CAN message interface data B2 registers
Table 1066.CAN message interface data B2 registers (IF1_DB2, address 0x400E 2048
(C_CAN0) and 0x400A 4048 (C_CAN1)) bit description

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Bit

Symbol Description

7:0

DATA6

Data byte 6

0x00

R/W

15:8

DATA7

Data byte 7

0x00

R/W

31:16

-

Reserved

-

-

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Table 1067.CAN message interface data B2 registers (IF2_DB2, address 0x400E 20A8
(C_CAN0) and 0x400A 40A8 (C_CAN1)) bit description
Bit

Symbol Description

Reset value Access

7:0

DATA6

Data byte 6

0x00

R/W

15:8

DATA7

Data byte 7

0x00

R/W

31:16

-

Reserved

-

-

45.6.3 Message handler registers
All Message Handler registers are read-only. Their contents (TXRQST, NEWDAT,
INTPND, and MSGVAL bits of each Message Object and the Interrupt Identifier) is status
information provided by the Message Handler FSM.

45.6.3.1 CAN transmission request 1 register
This register contains the TXRQST bits of message objects 1 to 16. By reading out the
TXRQST bits, the CPU can check for which Message Object a Transmission Request is
pending. The TXRQST bit of a specific Message Object can be set/reset by the CPU via
the IFx Message Interface Registers or by the Message Handler after reception of a
Remote Frame or after a successful transmission.
Table 1068.CAN transmission request 1 register (TXREQ1, address 0x400E 2100 (C_CAN0)
and 0x400A 4100 (C_CAN1)) bit description
Bit

Symbol

Description

15:0

TXRQST16_1

Transmission request bit of message objects 16 to 1. 0x00
0 = This message object is not waiting for
transmission.
1 = The transmission of this message object is
requested and not yet done.

R

Reserved

-

31:16 -

Reset
value

-

Access

45.6.3.2 CAN transmission request 2 register
This register contains the TXRQST bits of message objects 32 to 17. By reading out the
TXRQST bits, the CPU can check for which Message Object a Transmission Request is
pending. The TXRQST bit of a specific Message Object can be set/reset by the CPU via
the IFx Message Interface Registers or by the Message Handler after reception of a
Remote Frame or after a successful transmission.
Table 1069.CAN transmission request 2 register (TXREQ2, address 0x400E 2104 (C_CAN0)
and 0x400A 4104 (C_CAN1)) bit description
Bit

Symbol

Description

15:0

TXRQST32_17

Transmission request bit of message objects 32 to 17. 0x00
0 = This message object is not waiting for
transmission.
1 = The transmission of this message object is
requested and not yet done.

R

Reserved

-

31:16 -

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-

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45.6.3.3 CAN new data 1 register
This register contains the NEWDAT bits of message objects 16 to 1. By reading out the
NEWDAT bits, the CPU can check for which Message Object the data portion was
updated. The NEWDAT bit of a specific Message Object can be set/reset by the CPU via
the IFx Message Interface Registers or by the Message Handler after reception of a Data
Frame or after a successful transmission.
Table 1070.CAN new data 1 register (ND1, address 0x400E 2120 (C_CAN0) and 0x400A 4120
(C_CAN1)) bit description
Bit

Symbol

Description

Reset Access
value

15:0

NEWDAT16_1

New data bits of message objects 16 to 1.
0x00
0 = No new data has been written into the data portion
of this Message Object by the Message Handler since
last time this flag was cleared by the CPU.
1 = The Message Handler or the CPU has written new
data into the data portion of this Message Object.

R

31:16

-

Reserved

-

-

45.6.3.4 CAN new data 2 register
This register contains the NEWDAT bits of message objects 32 to 17. By reading out the
NEWDAT bits, the CPU can check for which Message Object the data portion was
updated. The NEWDAT bit of a specific Message Object can be set/reset by the CPU via
the IFx Message Interface Registers or by the Message Handler after reception of a Data
Frame or after a successful transmission.
Table 1071.CAN new data 2 register (ND2, address 0x400E 2124 (C_CAN0) and 0x400A 4124
(C_CAN1)) bit description
Bit

Symbol

Description

Reset Access
value

15:0

NEWDAT32_17

New data bits of message objects 32 to 17.
0 = No new data has been written into the data
portion of this Message Object by the Message
Handler since last time this flag was cleared by the
CPU.
1 = The Message Handler or the CPU has written
new data into the data portion of this Message
Object.

0x00

R

31:16

-

Reserved

-

-

45.6.3.5 CAN interrupt pending 1 register
This register contains the INTPND bits of message objects 16 to 1. By reading out the
INTPND bits, the CPU can check for which Message Object an interrupt is pending. The
INTPND bit of a specific Message Object can be set/reset by the CPU via the IFx
Message Interface Registers or by the Message Handler after reception or after a
successful transmission of a frame. This will also affect the value of INTPND in the
Interrupt Register.

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Table 1072.CAN interrupt pending 1 register (IR1, address 0x400E 2140 (C_CAN0) and
0x400A 4140 (C_CAN1)) bit description
Bit

Symbol

Description

Reset
value

Access

15:0

INTPND16_1

Interrupt pending bits of message objects 16 to 1.
0 = This message object is ignored by the message
handler.
1 = This message object is the source of an interrupt.

0x00

R

Reserved

-

-

31:16 -

45.6.3.6 CAN interrupt pending 2 register
This register contains the INTPND bits of message objects 32 to 17. By reading out the
INTPND bits, the CPU can check for which Message Object an interrupt is pending. The
INTPND bit of a specific Message Object can be set/reset by the CPU via the IFx
Message Interface Registers or by the Message Handler after reception or after a
successful transmission of a frame. This will also affect the value of INTPND in the
Interrupt Register.
Table 1073.CAN interrupt pending 2 register (IR2, addresses 0x400E 2144 (C_CAN0) and
0x400A 4144 (C_CAN1)) bit description
Bit

Symbol

Description

15:0

INTPND32_17

Interrupt pending bits of message objects 32 to 17.
0x00
0 = This message object is ignored by the message
handler.
1 = This message object is the source of an interrupt.

R

Reserved

-

31:16 -

Reset
value

-

Access

45.6.3.7 CAN message valid 1 register
This register contains the MSGVAL bits of message objects 16 to 1. By reading out the
MSGVAL bits, the CPU can check which Message Object is valid. The MSGVAL bit of a
specific Message Object can be set/reset by the CPU via the IFx Message Interface
Registers.
Table 1074.CAN message valid 1 register (MSGV1, addresses 0x400E 2160 (C_CAN0) and
0x400A 4160 (C_CAN1)) bit description
Bit

Symbol

Description

15:0

MSGVAL16_1

Message valid bits of message objects 16 to 1.
0x00
0 = This message object is ignored by the message
handler.
1 = This message object is configured and should be
considered by the message handler.

R

Reserved

-

31:16 -

Reset
value

-

Access

45.6.3.8 CAN message valid 2 register
This register contains the MSGVAL bits of message objects 32 to 17. By reading out the
MSGVAL bits, the CPU can check which Message Object is valid. The MSGVAL bit of a
specific Message Object can be set/reset by the CPU via the IFx Message Interface
Registers.
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Table 1075.CAN message valid 2 register (MSGV2, address 0x400E 2164 (C_CAN0) and
0x400A 4164 (C_CAN1)) bit description
Bit

Symbol

Description

15:0

MSGVAL32_17 Message valid bits of message objects 32 to 17.
R
0 = This message object is ignored by the message
handler.
1 = This message object is configured and should
be considered by the message handler.

31:16 -

Reserved

Access

-

Reset
value

0x00

-

45.6.4 CAN timing register
45.6.4.1 CAN clock divider register
This register determines the CAN clock signal. The CAN_CLK is derived from the
peripheral clock PCLK divided by the values in this register.
Table 1076.CAN clock divider register (CLKDIV, address 0x400E 2180 (C_CAN0) and 0x400A
4180 (C_CAN1)) bit description
Bit

Symbol

Description

3:0

CLKDIVVAL Clock divider value
CAN_CLK = PCLK/(CLKDIVVAL +1)

Reset
value

Access

0001

R/W

-

-

0000: CAN_CLK = PCLK divided by 1.
0001: CAN_CLK = PCLK divided by 2.
0010: CAN_CLK = PCLK divided by 3.
0011: CAN_CLK = PCLK divided by 4.
0100: CAN_CLK = PCLK divided by 5.
...
1111: CAN_CLK = PCLK divided by 16.
31:4

-

reserved

45.7 Functional description
45.7.1 C_CAN controller state after reset
After a hardware reset, the registers hold the values described in Table 1033. Additionally,
the busoff state is reset and the output CAN_TX is set to recessive (HIGH). The value
0x0001 (INIT = ‘1’) in the CAN Control Register enables the software initialization. The
CAN controller does not communicate with the CAN bus until the CPU resets INIT to ‘0’.
The data stored in the message RAM is not affected by a hardware reset. After power-on,
the contents of the message RAM is undefined.

45.7.2 C_CAN operating modes
45.7.2.1 Software initialization
The software initialization is started by setting the bit INIT in the CAN Control Register,
either by software or by a hardware reset, or by entering the busoff state.
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During software initialization (INIT bit is set), the following conditions are present:

•
•
•
•
•

All message transfer from and to the CAN bus is stopped.
The status of the CAN output CAN_TX is recessive (HIGH).
The EC counters are unchanged.
The configuration registers are unchanged.
Access to the bit timing register and the BRP extension register is enabled if the CCE
bit in the CAN control register is also set.

To initialize the CAN controller, software has to set up the bit timing register and each
message object. If a message object is not needed, it is sufficient to set its MSGVAL bit to
not valid. Otherwise, the whole message object has to be initialized.
Resetting the INIT bit finishes the software initialization. Afterwards the Bit Stream
Processor BSP synchronizes itself to the data transfer on the CAN bus by waiting for the
occurrence of a sequence of 11 consecutive recessive bits (Bus Idle) before it can take
part in bus activities and starts the message transfer.
Remark: The initialization of the Message Objects is independent of INIT and also can be
done on the fly, but the Message Objects should all be configured to particular identifiers
or set to not valid during software initialization before the BSP starts the message transfer.
To change the configuration of a Message Object during normal operation, the CPU has to
start by setting the MSGVAL bit to not valid. When the configuration is completed,
MSAGVALis set to valid again.

45.7.2.2 CAN message transfer
Once the CAN controller is initialized and INIT is reset to zero, the CAN core synchronizes
itself to the CAN bus and starts the message transfer.
Received messages are stored into their appropriate Message Objects if they pass the
Message Handler’s acceptance filtering. The whole message including all arbitration bits,
DLC and eight data bytes is stored into the Message Object. If the Identifier Mask is used,
the arbitration bits which are masked to “don’t care” may be overwritten in the Message
Object.
The CPU may read or write each message any time via the Interface Registers. The
Message Handler guarantees data consistency in case of concurrent accesses.
Messages to be transmitted are updated by the CPU. If a permanent Message Object
(arbitration and control bits set up during configuration) exists for the message, only the
data bytes are updated and then TXRQUT bit with NEWDAT bit are set to start the
transmission. If several transmit messages are assigned to the same Message Object
(when the number of Message Objects is not sufficient), the whole Message Object has to
be configured before the transmission of this message is requested.
The transmission of any number of Message Objects may be requested at the same time,
and they are transmitted subsequently according to their internal priority. Messages may
be updated or set to not valid any time, even when their requested transmission is still
pending. The old data will be discarded when a message is updated before its pending
transmission has started.

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Depending on the configuration of the Message Object, the transmission of a message
may be requested autonomously by the reception of a remote frame with a matching
identifier.

45.7.2.3 Disabled Automatic Retransmission (DAR)
According to the CAN Specification (ISO11898, 6.3.3 Recovery Management), the CAN
controller provides means for automatic retransmission of frames that have lost arbitration
or that have been disturbed by errors during transmission. The frame transmission service
will not be confirmed to the user before the transmission is successfully completed. By
default, the automatic retransmission on lost arbitration or error is enabled. It can be
disabled to enable the CAN controller to work within a Time Triggered CAN (TTCAN, see
ISO11898-1) environment.
The Disable Automatic Retransmission mode is enabled by programming bit DAR in the
CAN Control Register to one. In this operation mode the programmer has to consider the
different behavior of bits TXRQST and NEWDAT in the Control Registers of the Message
Buffers:

• When a transmission starts, bit TXRQST of the respective Message Buffer is reset
while bit NEWDAT remains set.

• When the transmission completed successfully, bit NEWDAT is reset.
• When a transmission failed (lost arbitration or error), bit NEWDAT remains set. To
restart the transmission, the CPU has to set TXRQST back to one.

45.7.2.4 Test modes
The Test mode is entered by setting bit TEST in the CAN Control Register to one. In Test
mode the bits TX1, TX0, LBACK, SILENT, and BASIC in the Test Register are writable. Bit
RX monitors the state of pins RD0,1 and therefore is only readable. All Test register
functions are disabled when bit TEST is reset to zero.
45.7.2.4.1

Silent mode
The CAN core can be set in Silent mode by programming the Test register bit SILENT to
one.
In Silent Mode, the CAN controller is able to receive valid data frames and valid remote
frames, but it sends only recessive bits on the CAN bus, and it cannot start a
transmission. If the CAN Core is required to send a dominant bit (ACK bit, overload flag,
active error flag), the bit is rerouted internally so that the CAN Core monitors this dominant
bit, although the CAN bus may remain in recessive state. The Silent mode can be used to
analyze the traffic on a CAN bus without affecting it by the transmission of dominant bits
(Acknowledge Bits, Error Frames).

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TD

C_CAN

RD

=1

Rx

Tx

CAN CORE

Fig 165. CAN core in Silent mode

45.7.2.4.2

Loop-back mode
The CAN Core can be set in Loop-back mode by programming the Test Register bit
LBACK to one. In Loop-back Mode, the CAN Core treats its own transmitted messages as
received messages and stores them (if they pass acceptance filtering) into a Receive
Buffer.
This mode is provided for self-test functions. To be independent from external stimulation,
the CAN Core ignores acknowledge errors (recessive bit sampled in the acknowledge slot
of a data/remote frame) in Loop-back mode. In this mode the CAN core performs an
internal feedback from its CAN_TD output to its CAN_RD input. The actual value of the
CAN_RD input pin is disregarded by the CAN Core. The transmitted messages can be
monitored at the CAN_TD pin.
TD

RD

C_CAN

Rx

Tx

CAN CORE

Fig 166. CAN core in Loop-back mode

45.7.2.4.3

Loop-back mode combined with Silent mode
It is also possible to combine Loop-back mode and Silent mode by programming bits
LBACK and SILENT to one at the same time. This mode can be used for a “Hot Self test”,
meaning the C_CAN can be tested without affecting a running CAN system connected to
the pins CAN_TD and CAN_RD. In this mode the CAN_RD pin is disconnected from the
CAN Core and the CAN_TD pin is held recessive.

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TD

C_CAN

RD

=1

Rx
Tx
CAN CORE

Fig 167. CAN core in Loop-back mode combined with Silent mode

45.7.2.4.4

Basic mode
The CAN Core can be set in Basic mode by programming the Test Register bit BASIC to
one. In this mode the CAN controller runs without the Message RAM.
The IF1 Registers are used as Transmit Buffer. The transmission of the contents of the
IF1 Registers is requested by writing the BUSY bit of the IF1 Command Request Register
to ‘1’. The IF1 Registers are locked while the BUSY bit is set. The BUSY bit indicates that
the transmission is pending.
As soon the CAN bus is idle, the IF1 Registers are loaded into the shift register of the CAN
Core and the transmission is started. When the transmission has completed, the BUSY bit
is reset and the locked IF1 Registers are released.
A pending transmission can be aborted at any time by resetting the BUSY bit in the IF1
Command Request Register while the IF1 Registers are locked. If the CPU has reset the
BUSY bit, a possible retransmission in case of lost arbitration or in case of an error is
disabled.
The IF2 Registers are used as Receive Buffer. After the reception of a message the
contents of the shift register is stored into the IF2 Registers, without any acceptance
filtering.
Additionally, the actual contents of the shift register can be monitored during the message
transfer. Each time a read Message Object is initiated by writing the BUSY bit of the IF2
Command Request Register to ‘1’, the contents of the shift register is stored into the IF2
Registers.
In Basic mode the evaluation of all Message Object related control and status bits and of
the control bits of the IFx Command Mask Registers is turned off. The message number of
the Command request registers is not evaluated. The NEWDAT and MSGLST bits of the
IF2 Message Control Register retain their function, DLC3-0 will show the received DLC,
the other control bits will be read as ‘0’.
In Basic mode the ready output CAN_WAIT_B is disabled (always ‘1’)

45.7.2.4.5

Software control of pin CAN_TD
Four output functions are available for the CAN transmit pin CAN_TD:
1. serial data output (default).

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2. drives CAN sample point signal to monitor the CAN controller’s timing.
3. drives recessive constant value.
4. drives dominant constant value.
The last two functions, combined with the readable CAN receive pin CAN_RD, can be
used to check the CAN bus’ physical layer.
The output mode of pin CAN_TD is selected by programming the Test Register bits TX1
and TX0 as described Section 45.6.1.6.
Remark: The three test functions for pin CAN_TD interfere with all CAN protocol
functions. The CAN_TD pin must be left in its default function when CAN message
transfer or any of the test modes Loo-back mode, Silent mode, or Basic mode are
selected.

45.7.3 CAN message handler
The Message handler controls the data transfer between the Rx/Tx Shift Register of the
CAN Core, the Message RAM and the IFx Registers, see Figure 164.
The message handler controls the following functions:

•
•
•
•
•
•
•

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Data Transfer between IFx Registers and the Message RAM
Data Transfer from Shift Register to the Message RAM
Data Transfer from Message RAM to Shift Register
Data Transfer from Shift Register to the Acceptance Filtering unit
Scanning of Message RAM for a matching Message Object
Handling of TXRQST flags
Handling of interrupts

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transfer a
message object

transfer a
CAN frame

INTERFACE
COMMAND REGISTERS
IF1 COMMAND REQUEST
IF1 COMMAND MASK
IF2 COMMAND REQUEST
IF2 COMMAND MASK
MESSAGE BUFFER
REGISTERS

MESSAGE RAM

read transfer
write transfer

IF1 MASK1, 2
IF1 ARBITRATION 1/2
IF1 MESSAGE CTRL
IF1 DATA A1/2
IF1 DATA B1/2

APB
bus

MESSAGE OBJECT 1
MESSAGE OBJECT 2
.
.
.
MESSAGE OBJECT 32

IF2 MASK1, 2
IF2 ARBITRATION 1/2
IF2 MESSAGE CTRL
IF2 DATA A1/2
IF2 DATA B1/2
MESSAGE HANDLER

receive
CAN CORE/
SHIFT REGISTERS

transmit

CAN
bus

TRANSMISSION REQUEST 1/2
NEW DATA 1/2
INTERRUPT PENDING1/2
MESSAGE VALID1/2

Fig 168. Block diagram of a message object transfer

45.7.3.1 Management of message objects
The configuration of the Message Objects in the Message RAM will (with the exception of
the bits MSGVAL, NEWDAT, INTPND, and TXRQST) is not be affected by resetting the
chip. All the Message Objects must be initialized by the CPU or they must be set to not
valid (MSGVAL = ‘0’).The bit timing must be configured before the CPU clears the INIT bit
in the CAN Control Register.
The configuration of a Message Object is done by programming Mask, Arbitration, Control
and Data field of one of the two interface register sets to the desired values. By writing to
the corresponding IFx Command Request Register, the IFx Message Buffer Registers are
loaded into the addressed Message Object in the Message RAM.
When the INIT bit in the CAN Control Register is cleared, the CAN Protocol Controller
state machine of the CAN core and the Message Handler State Machine control the CAN
controller’s internal data flow. Received messages that pass the acceptance filtering are
stored into the Message RAM, and messages with pending transmission request are
loaded into the CAN core’s shift register and are transmitted via the CAN bus.
The CPU reads received messages and updates messages to be transmitted via the IFx
Interface Registers. Depending on the configuration, the CPU is interrupted on certain
CAN message and CAN error events.

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45.7.3.2 Data Transfer between IFx Registers and the Message RAM
When the CPU initiates a data transfer between the IFx Registers and Message RAM, the
Message Handler sets the BUSY bit in the respective Command Register to ‘1’. After the
transfer has completed, the BUSY bit is set back to ‘0’.
The Command Mask Register specifies whether a complete Message Object or only parts
of it will be transferred. Due to the structure of the Message RAM it is not possible to write
single bits/bytes of one Message Object. Software must always write a complete Message
Object into the Message RAM. Therefore the data transfer from the IFx Registers to the
Message RAM requires a read-modify-write cycle:
1. Read the parts of the message object that are not to be changed from the message
RAM using the command mask register.
– After the partial read of a Message Object, the Message Buffer Registers that are
not selected in the Command Mask Register will be left unchanged.
2. Write the complete contents of the message buffer registers into the message object.
– After the partial write of a Message Object, the Message Buffer Registers that are
not selected in the Command Mask Register will set to the actual contents of the
selected Message Object.

45.7.3.3 Transmission of messages between the shift registers in the CAN core and
the Message buffer
If the shift register of the CAN Core cell is ready for loading and if there is no data transfer
between the IFx Registers and Message RAM, the MSGVAL bits in the Message Valid
Register TXRQST bits in the Transmission Request Register are evaluated. The valid
Message Object with the highest priority pending transmission request is loaded into the
shift register by the Message Handler and the transmission is started. The Message
Object’s NEWDAT bit is reset.
After a successful transmission and if no new data was written to the Message Object
(NEWDAT = ‘0’) since the start of the transmission, the TXRQST bit will be reset. If TXIE
is set, INTPND will be set after a successful transmission. If the CAN controller has lost
the arbitration or if an error occurred during the transmission, the message will be
retransmitted as soon as the CAN bus is free again. If meanwhile the transmission of a
message with higher priority has been requested, the messages will be transmitted in the
order of their priority.

45.7.3.4 Acceptance filtering of received messages
When the arbitration and control field (Identifier + IDE + RTR + DLC) of an incoming
message is completely shifted into the Rx/Tx Shift Register of the CAN Core, the
Message Handler state machine starts the scanning of the Message RAM for a matching
valid Message Object.
To scan the Message RAM for a matching Message Object, the Acceptance Filtering unit
is loaded with the arbitration bits from the CAN Core shift register. Then the arbitration and
mask fields (including MSGVAL, UMASK, NEWDAT, and EOB) of Message Object 1 are
loaded into the Acceptance Filtering unit and compared with the arbitration field from the
shift register. This is repeated with each following Message Object until a matching
Message Object is found or until the end of the Message RAM is reached.

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If a match occurs, the scanning is stopped and the Message Handler state machine
proceeds depending on the type of frame (Data Frame or Remote Frame) received.
45.7.3.4.1

Reception of a data frame
The Message Handler state machine stores the message from the CAN Core shift register
into the respective Message Object in the Message RAM. The data bytes, all arbitration
bits, and the Data Length Code are stored into the corresponding Message Object. This is
implemented to keep the data bytes connected with the identifier even if arbitration mask
registers are used.
The NEWDAT bit is set to indicate that new data (not yet seen by the CPU) has been
received. The CPU/software should reset NEWDAT when it reads the Message Object. If
at the time of the reception the NEWDAT bit was already set, MSGLST is set to indicate
that the previous data (supposedly not seen by the CPU) is lost. If the RxIE bit is set, the
INTPND bit is also set, causing the Interrupt Register to point to this Message Object.
The TXRQST bit of this Message Object is reset to prevent the transmission of a Remote
Frame, while the requested Data Frame has just been received.

45.7.3.4.2

Reception of a remote frame
When a Remote Frame is received, three different configurations of the matching
Message Object have to be considered:
1. DIR = ‘1’ (direction = transmit), RMTEN = ‘1’, UMASK = ‘1’ or ’0’
On the reception of a matching Remote Frame, the TXRQST bit of this Message
Object is set. The rest of the Message Object remains unchanged.
2. DIR = ‘1’ (direction = transmit), RMTEN = ‘0’, UMASK = ’0’
On the reception of a matching Remote Frame, the TXRQST bit of this Message
Object remains unchanged; the Remote Frame is ignored.
3. DIR = ‘1’ (direction = transmit), RMTEN = ‘0’, UMASK = ’1’
On the reception of a matching Remote Frame, the TXRQST bit of this Message
Object is reset. The arbitration and control field (Identifier + IDE + RTR + DLC) from
the shift register is stored into the Message Object in the Message RAM, and the
NEWDAT bit of this Message Object is set. The data field of the Message Object
remains unchanged; the Remote Frame is treated similar to a received Data Frame.

45.7.3.5 Receive/transmit priority
The receive/transmit priority for the Message Objects is attached to the message number.
Message Object 1 has the highest priority, while Message Object 32 has the lowest
priority. If more than one transmission request is pending, they are serviced due to the
priority of the corresponding Message Object.

45.7.3.6 Configuration of a transmit object
Table 1077 shows how a transmit object should be initialized by software (see also
Table 1043):

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Table 1077.Initialization of a transmit object
MSGVAL

1
MSGLST

0

Arbitration
bits

Data bits

Mask bits

EOB

DIR

NEWDAT

application
dependent

application
dependent

application
dependent

1

1

0

RXIE

TXIE

INTPND

RMTEN

TXRQST

0

application
dependent

0

application
dependent

0

The Arbitration Registers (ID28:0 and XTD bit) are given by the application. They define
the identifier and the type of the outgoing message. If an 11-bit Identifier (“Standard
Frame”) is used, it is programmed to ID28. In this case ID18, ID17 to ID0 can be
disregarded.
If the TXIE bit is set, the INTPND bit will be set after a successful transmission of the
Message Object.
If the RMTEN bit is set, a matching received Remote Frame will cause the TXRQST bit to
be set, and the Remote Frame will autonomously be answered by a Data Frame.
The Data Registers (DLC3:0, Data0:7) are given by the application. TXRQST and RMTEN
may not be set before the data is valid.
The Mask Registers (Msk28-0, UMASK, MXTD, and MDIR bits) may be used
(UMASK=’1’) to allow groups of Remote Frames with similar identifiers to set the TXRQST
bit. For details see Section 45.7.3.4.2. The DIR bit should not be masked.

45.7.3.7 Updating a transmit object
The CPU may update the data bytes of a Transmit Object any time via the IFx Interface
registers. Neither MSGVAL nor TXRQST have to be reset before the update.
Even if only a part of the data bytes are to be updated, all four bytes of the corresponding
IFx Data A Register or IFx Data B Register have to be valid before the content of that
register is transferred to the Message Object. Either the CPU has to write all four bytes
into the IFx Data Register or the Message Object is transferred to the IFx Data Register
before the CPU writes the new data bytes.
When only the (eight) data bytes are updated, first 0x0087 is written to the Command
Mask Register. Then the number of the Message Object is written to the Command
Request Register, concurrently updating the data bytes and setting TXRQST.
To prevent the reset of TXRQST at the end of a transmission that may already be in
progress while the data is updated, NEWDAT has to be set together with TXRQST. For
details see Section 45.7.3.3.
When NEWDAT is set together with TXRQST, NEWDAT will be reset as soon as the new
transmission has started.

45.7.3.8 Configuration of a receive object
Table 1078 shows how a receive object should be initialized by software (see also
Table 1043)

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Table 1078.Initialization of a receive object
MSGVAL

1
MSGLST

0

Arbitration
bits

Data bits

Mask bits

EOB

DIR

NEWDAT

application
dependent

application
dependent

application
dependent

1

0

0

RXIE

TXIE

INTPND

RMTEN

TXRQST

application
dependent

0

0

0

0

The Arbitration Registers (ID28-0 and XTD bit) are given by the application. They define
the identifier and type of accepted received messages. If an 11-bit Identifier (“Standard
Frame”) is used, it is programmed to ID28 to ID18. ID17 to ID0 can then be disregarded.
When a Data Frame with an 11-bit Identifier is received, ID17 to ID0 will be set to ‘0’.
If the RxIE bit is set, the INTPND bit will be set when a received Data Frame is accepted
and stored in the Message Object.
The Data Length Code (DLC[3:0] is given by the application. When the Message Handler
stores a Data Frame in the Message Object, it will store the received Data Length Code
and eight data bytes. If the Data Length Code is less than 8, the remaining bytes of the
Message Object will be overwritten by non specified values.
The Mask Registers (Msk[28:0], UMASK, MXTD, and MDIR bits) may be used
(UMASK=’1’) to allow groups of Data Frames with similar identifiers to be accepted. For
details see section Section 45.7.3.4.1. The DIR bit should not be masked in typical
applications.

45.7.3.9 Handling of received messages
The CPU may read a received message any time via the IFx Interface registers. The data
consistency is guaranteed by the Message Handler state machine.
To transfer the entire received message from message RAM into the message buffer,
software must write first 0x007F to the Command Mask Register and then the number of
the Message Object to the Command Request Register. Additionally, the bits NEWDAT
and INTPND are cleared in the Message RAM (not in the Message Buffer).
If the Message Object uses masks for acceptance filtering, the arbitration bits show which
of the matching messages has been received.
The actual value of NEWDAT shows whether a new message has been received since
last time this Message Object was read. The actual value of MSGLST shows whether
more than one message has been received since last time this Message Object was read.
MSGLST will not be automatically reset.
Using a Remote Frame, the CPU may request another CAN node to provide new data for
a receive object. Setting the TXRQST bit of a receive object will cause the transmission of
a Remote Frame with the receive object’s identifier. This Remote Frame triggers the other
CAN node to start the transmission of the matching Data Frame. If the matching Data
Frame is received before the Remote Frame could be transmitted, the TXRQST bit is
automatically reset.

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45.7.3.10 Configuration of a FIFO buffer
With the exception of the EOB bit, the configuration of Receive Objects belonging to a
FIFO Buffer is the same as the configuration of a (single) Receive Object, see section
Section 45.7.3.8.
To concatenate two or more Message Objects into a FIFO Buffer, the identifiers and
masks (if used) of these Message Objects have to be programmed to matching values.
Due to the implicit priority of the Message Objects, the Message Object with the lowest
number will be the first Message Object of the FIFO Buffer. The EOB bit of all Message
Objects of a FIFO Buffer except the last have to be programmed to zero. The EOB bits of
the last Message Object of a FIFO Buffer is set to one, configuring it as the End of the
Block.
45.7.3.10.1

Reception of messages with FIFO buffers
Received messages with identifiers matching to a FIFO Buffer are stored into a Message
Object of this FIFO Buffer starting with the Message Object with the lowest message
number.
When a message is stored into a Message Object of a FIFO Buffer the NEWDAT bit of this
Message Object is set. By setting NEWDAT while EOB is zero the Message Object is
locked for further write accesses by the Message Handler until the CPU has written the
NEWDAT bit back to zero.
Messages are stored into a FIFO Buffer until the last Message Object of this FIFO Buffer
is reached. If none of the preceding Message Objects is released by writing NEWDAT to
zero, all further messages for this FIFO Buffer will be written into the last Message Object
of the FIFO Buffer and therefore overwrite previous messages.

45.7.3.10.2

Reading from a FIFO buffer
When the CPU transfers the contents of Message Object to the IFx Message Buffer
registers by writing its number to the IFx Command Request Register, bits NEWDAT and
INTPND in the corresponding Command Mask Register should be reset to zero
(TXRQST/NEWDAT = ‘1’ and ClrINTPND = ‘1’). The values of these bits in the Message
Control Register always reflect the status before resetting the bits.
To assure the correct function of a FIFO Buffer, the CPU should read out the Message
Objects starting at the FIFO Object with the lowest message number.

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START

read CANIR

INTID = 0x8000 ?

INTID = 0x0001
to 0x0020 ?

yes

INTID = 0x0000 ?

yes

yes
END

status change
interrupt handling
MessageNum = INTID

write MessageNum to CANIFx_CMDREQ

read message to message buffer
reset NEWDAT = 0
reset INTPND = 0

read CANIFx_MCTRL

no
NEWDAT = 1

yes
read data from CANIFx_DA/B

yes
EOB = 1

no
MessageNum = MessageNum +1

Fig 169. Reading a message from the FIFO buffer to the message buffer

45.7.4 Interrupt handling
If several interrupts are pending, the CAN Interrupt Register will point to the pending
interrupt with the highest priority, disregarding their chronological order. An interrupt
remains pending until the CPU has cleared it.

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The Status Interrupt has the highest priority. Among the message interrupts, the Message
Object’s interrupt priority decreases with increasing message number.
A message interrupt is cleared by clearing the Message Object’s INTPND bit. The Status
Interrupt is cleared by reading the Status Register.
The interrupt identifier INTID in the Interrupt Register indicates the cause of the interrupt.
When no interrupt is pending, the register will hold the value zero. If the value of the
Interrupt Register is different from zero, then there is an interrupt pending and, if IE is set,
the interrupt line to the CPU, IRQ_B, is active. The interrupt line remains active until the
Interrupt Register is back to value zero (the cause of the interrupt is reset) or until IE is
reset.
The value 0x8000 indicates that an interrupt is pending because the CAN Core has
updated (not necessarily changed) the Status Register (Error Interrupt or Status Interrupt).
This interrupt has the highest priority. The CPU can update (reset) the status bits RXOK,
TXOK and LEC, but a write access of the CPU to the Status Register can never generate
or reset an interrupt.
All other values indicate that the source of the interrupt is one of the Message Objects
where INTID points to the pending message interrupt with the highest interrupt priority.
The CPU controls whether a change of the Status Register may cause an interrupt (bits
EIE and SIE in the CAN Control Register) and whether the interrupt line becomes active
when the Interrupt Register is different from zero (bit IE in the CAN Control Register). The
Interrupt Register will be updated even when IE is reset.
The CPU has two possibilities to follow the source of a message interrupt:

• Software can follow the INTID in the Interrupt Register.
• Software can poll the interrupt pending register.
An interrupt service routine reading the message that is the source of the interrupt may
read the message and reset the Message Object’s INTPND at the same time (bit
ClrINTPND in the Command Mask Register). When INTPND is cleared, the Interrupt
Register will point to the next Message Object with a pending interrupt.

45.7.5 Bit timing
Even if minor errors in the configuration of the CAN bit timing do not result in immediate
failure, the performance of a CAN network can be reduced significantly. In many cases,
the CAN bit synchronization will amend a faulty configuration of the CAN bit timing to such
a degree that only occasionally an error frame is generated. In the case of arbitration
however, when two or more CAN nodes simultaneously try to transmit a frame, a
misplaced sample point may cause one of the transmitters to become error passive.
The analysis of such sporadic errors requires a detailed knowledge of the CAN bit
synchronization inside a CAN node and of the CAN nodes’ interaction on the CAN bus.

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45.7.5.1 Bit time and bit rate
CAN supports bit rates in the range of lower than 1 kBit/s up to 1000 kBit/s. Each member
of the CAN network has its own clock generator, usually a quartz oscillator. The timing
parameter of the bit time (i.e. the reciprocal of the bit rate) can be configured individually
for each CAN node, creating a common bit rate even though the CAN nodes’ oscillator
periods (fosc) may be different.
The frequencies of these oscillators are not absolutely stable, as small variations are
caused by changes in temperature or voltage and by deteriorating components. As long
as the variations remain inside a specific oscillator tolerance range (df), the CAN nodes
are able to compensate for the different bit rates by re-synchronizing to the bit stream.
According to the CAN specification, the bit time is divided into four segments (Figure 170).
The Synchronization Segment, the Propagation Time Segment, the Phase Buffer
Segment 1, and the Phase Buffer Segment 2. Each segment consists of a specific,
programmable number of time quanta (see Table 1079). The length of the time quantum
(tq), which is the basic time unit of the bit time, is defined by the CAN controller’s system
clock f and the Baud Rate Prescaler (BRP): tq = BRP / fsys. The C_CAN’s system clock fsys
is the frequency C_CAN peripheral clock.
The Synchronization Segment Sync_Seg is the part of the bit time where edges of the
CAN bus level are expected to occur; the distance between an edge that occurs outside of
Sync_Seg and the Sync_Seg is called the phase error of that edge. The Propagation
Time Segment Prop_Seg is intended to compensate for the physical delay times within
the CAN network. The Phase Buffer Segments Phase_Seg1 and Phase_Seg2 surround
the Sample Point. The (Re-)Synchronization Jump Width (SJW) defines how far a
re-synchronization may move the Sample Point inside the limits defined by the Phase
Buffer Segments to compensate for edge phase errors.
Table 1079 describes the minimum programmable ranges required by the CAN protocol.
Bit time parameters are programmed through the BT register, Table 1038. For details on
bit timing and examples, see the C_CAN user’s manual, revision 1.2.
Table 1079.Parameters of the C_CAN bit time

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Parameter

Range

Function

BRP

(1...32)

Defines the length of the time quantum tq.

SYNC_SEG

1tq

Synchronization segment. Fixed length. Synchronization
of bus input to system clock.

PROP_SEG

(1...8)  tq

Propagation time segment. Compensates for physical
delay times. This parameter is determined by the system
delay times in the C_CAN network.

PHASE_SEG1

(1...8)  tq

Phase buffer segment 1. May be lengthened temporarily
by synchronization.

PHASE_SEG2
(TSEG2)

(1...8)  tq

Phase buffer segment 2. May be shortened temporarily by
synchronization.

SJW

(1...4)  tq

(Re-) synchronization jump width. May not be longer than
either phase buffer segment.

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TSEG1

TSEG2

PHASE_SEG1

PHASE_SEG2

Fig 170. Bit timing

45.7.5.2 Calculating the C_CAN bit rate
The C_CAN clock is derived from the BASE_APB3_CLK (for CAN0) or from
BASE_APB1_CLK (CAN1). The C_CAN clock can be divided by the C_CAN clock divider
(Table 1076): CAN_CLK = BASE_APB3_CLK/(DIVVAL +1) or CAN_CLK =
BASE_APB1_CLK/(DIVVAL +1).
Using Figure 170 and Table 1079, the bit rate and sample point can be expressed as
follows using tq = BRP/CAN_CLK:
Bit rate = 1/(tq x total number of quantas) = 1/(tq x (1 + PROP_SEG+TSEG1+TSEG2)) =
CAN_CLK/(BRP x (1 + PROP_SEG+TSEG1+TSEG2))
Sample point = (1 + PROP_SEG+TSEG1)/(1 + PROP_SEG+TSEG1+TSEG2) x 100
The CAN BT register (see Table 1038) stores the bit timing information for parameters
BRP (bits 5:0), PROP_SEG +TSEG1 (bits 11:8, named TSEG1), and TSEG2. Note that
the register content are +1 encoded.
Using the contents of the BT register for BRP, TSEG1, and TSEG2, the bit rate can be
calculated as follows:
Bit rate = CAN_CLK/((BRP + 1) x (TSEG1+2+TSEG2+1))
Sample point = (TSEG1+2)/(TSEG1+2+TSEG2+1) x 100

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46.1 How to read this chapter
The I2C-bus interfaces I2C0 and I2C1 are available on all LPC43xx/LPC43Sxx parts.

46.2 Basic configuration
The I2C0/1 are configured as follows:

•
•
•
•

See Table 1080 for clocking and power control.
The I2C0/1 are reset by the I2C0/1_RST (reset # 48/49).
The I2C0/1 interrupts are connected to slots # 18/19 in the NVIC.
Configure the I2C0 pins for Fast-mode Plus, Fast mode, or Standard mode through
the SFSI2C0 register in the SYSCON block (see Table 195).

Table 1080.I2C0/1 clocking and power control
Base clock

Branch clock

Operating
frequency

Clock to the I2C0 register interface and
I2C0 peripheral clock.

BASE_APB1_CLK CLK_APB1_I2C0 up to 204 MHz

Clock to the I2C1 register interface and
I2C1 peripheral clock.

BASE_APB3_CLK CLK_APB3_I2C1 up to 204 MHz

46.3 Features
• The I2C0-bus interface uses true open-drain pins and supports Fast mode plus with
bit rates of up to 1Mbit/s, Fast mode, or Standard mode.

• The I2C1-bus interface uses standard port pins supporting bit rates of up to 400 kbit/s.
• Standard I2C-compliant bus interfaces may be configured as Master, Slave, or
Master/Slave.

• Arbitration is handled between simultaneously transmitting masters without corruption
of serial data on the bus.

• Programmable clock allows adjustment of I2C transfer rates.
• Data transfer is bidirectional between masters and slaves.
• Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus.

• Serial clock synchronization is used as a handshake mechanism to suspend and
resume serial transfer.

•
•
•
•
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Optional recognition of up to four distinct slave addresses.
Monitor mode allows observing all I2C-bus traffic, regardless of slave address.
I2C-bus can be used for test and diagnostic purposes.
The I2C-bus contains a standard I2C-compliant bus interface with two pins.

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Chapter 46: LPC43xx/LPC43Sxx I2C-bus interface

46.4 Applications
Interfaces to external I2C standard parts, such as serial RAMs, LCDs, tone generators,
other microcontrollers, etc.

46.5 General description
A typical I2C-bus configuration is shown in Figure 171. Depending on the state of the
direction bit (R/W), two types of data transfers are possible on the I2C-bus:

• Data transfer from a master transmitter to a slave receiver. The first byte transmitted
by the master is the slave address. Next follows a number of data bytes. The slave
returns an acknowledge bit after each received byte.

• Data transfer from a slave transmitter to a master receiver. The first byte (the slave
address) is transmitted by the master. The slave then returns an acknowledge bit.
Next follows the data bytes transmitted by the slave to the master. The master returns
an acknowledge bit after all received bytes other than the last byte. At the end of the
last received byte, a “not acknowledge” is returned. The master device generates all
of the serial clock pulses and the START and STOP conditions. A transfer is ended
with a STOP condition or with a Repeated START condition. Since a Repeated
START condition is also the beginning of the next serial transfer, the I2C bus will not
be released.
The I2C interface is byte oriented and has four operating modes: master transmitter mode,
master receiver mode, slave transmitter mode and slave receiver mode.
The I2C interface complies with the entire I2C specification, supporting the ability to turn
power off to the processor without interfering with other devices on the same I2C-bus.

pull-up
resistor

pull-up
resistor

SDA
I 2C bus
SCL

SDA

SCL

LPC43xx

OTHER DEVICE WITH
I 2C INTERFACE

OTHER DEVICE WITH
I 2C INTERFACE

Fig 171. I2C-bus configuration

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Chapter 46: LPC43xx/LPC43Sxx I2C-bus interface

46.5.1 I2C Fast-mode Plus
Fast-Mode Plus supports a 1 Mbit/sec transfer rate to communicate with the I2C-bus
products which NXP Semiconductors is now providing.
In order to use Fast-Mode Plus, the I2C pins must be properly configured in the SFSI2C0
register in the SYSCON block (see Table 195).

46.6 Pin description
Table 1081.I2C-bus pin description
Pin function

Type

Description

I2C0_SDA

Input/Output

I2C data input/output. Open-drain output (for I2C-bus
compliance).

I2C0_SCL

Input/Output

I2C clock input/output. Open-drain output (for I2C-bus
compliance).

I2C1_SDA

Input/Output

I2C Serial Data. Uses standard I/O pins (Fast-mode only).

I2C1_SCL

Input/Output

I2C Serial Clock. Uses standard I/O pins (Fast-mode only).

The I2C-bus pins must be configured through SYSCON registers for Standard/ Fast-mode
or Fast-mode Plus.

46.7 Register description
Table 1082.Register overview: I2C0 (base address 0x400A 1000)
Name

Access Address Description
offset

CONSET

R/W

0x000

I2C Control Set Register. When a one is written to a bit of
0x00
this register, the corresponding bit in the I2C control register is
set. Writing a zero has no effect on the corresponding bit in
the I2C control register.

Table 1084

STAT

RO

0x004

I2C Status Register. During I2C operation, this register
provides detailed status codes that allow software to
determine the next action needed.

0xF8

Table 1085

DAT

R/W

0x008

I2C Data Register. During master or slave transmit mode,
0x00
data to be transmitted is written to this register. During master
or slave receive mode, data that has been received may be
read from this register.

Table 1086

ADR0

R/W

0x00C

I2C Slave Address Register 0. Contains the 7-bit slave
address for operation of the I2C interface in slave mode, and
is not used in master mode. The least significant bit
determines whether a slave responds to the General Call
address.

0x00

Table 1087

SCLH

R/W

0x010

SCH Duty Cycle Register High Half Word. Determines the
high time of the I2C clock.

0x04

Table 1088

SCLL

R/W

0x014

SCL Duty Cycle Register Low Half Word. Determines the 0x04
low time of the I2C clock. SCLL and SCLH together determine
the clock frequency generated by an I2C master and certain
times used in slave mode.

Table 1089

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Chapter 46: LPC43xx/LPC43Sxx I2C-bus interface

Table 1082.Register overview: I2C0 (base address 0x400A 1000) …continued
Name

Access Address Description
offset

CONCLR

WO

0x018

I2C Control Clear Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is
cleared. Writing a zero has no effect on the corresponding bit
in the I2C control register.

MMCTRL

R/W

0x01C

Monitor mode control register.

0x00

Table 1091

ADR1

R/W

0x020

I2C Slave Address Register 1. Contains the 7-bit slave
address for operation of the I2C interface in slave mode, and
is not used in master mode. The least significant bit
determines whether a slave responds to the General Call
address.

0x00

Table 1092

ADR2

R/W

0x024

I2C Slave Address Register 2. Contains the 7-bit slave
address for operation of the I2C interface in slave mode, and
is not used in master mode. The least significant bit
determines whether a slave responds to the General Call
address.

0x00

Table 1092

ADR3

R/W

0x028

I2C Slave Address Register 3. Contains the 7-bit slave
address for operation of the I2C interface in slave mode, and
is not used in master mode. The least significant bit
determines whether a slave responds to the General Call
address.

0x00

Table 1092

DATA_BUFFER RO

0x02C

Data buffer register. The contents of the 8 MSBs of the DAT 0x00
shift register will be transferred to the DATA_BUFFER
automatically after every nine bits (8 bits of data plus ACK or
NACK) has been received on the bus.

Table 1094

MASK0

R/W

0x030

I2C Slave address mask register 0. This mask register is
associated with ADR0 to determine an address match. The
mask register has no effect when comparing to the General
Call address (‘0000000’).

0x00

Table 1095

MASK1

R/W

0x034

I2C Slave address mask register 1. This mask register is
associated with ADR1 to determine an address match. The
mask register has no effect when comparing to the General
Call address (‘0000000’).

0x00

Table 1095

MASK2

R/W

0x038

I2C Slave address mask register 2. This mask register is
associated with ADR2 to determine an address match. The
mask register has no effect when comparing to the General
Call address (‘0000000’).

0x00

Table 1095

MASK3

R/W

0x03C

I2C Slave address mask register 3. This mask register is
associated with ADR3 to determine an address match. The
mask register has no effect when comparing to the General
Call address (‘0000000’).

0x00

Table 1095

[1]

Reset
Reference
value[1]

Table 1090

Reset value reflects the data stored in used bits only. It does not include reserved bits content.

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Chapter 46: LPC43xx/LPC43Sxx I2C-bus interface

Table 1083.Register overview: I2C1 (base address 0x400E 0000)
Name

Access Address Description
offset

Reset
Reference
value[1]

CONSET

R/W

0x000

I2C Control Set Register. When a one is written to a bit of this
register, the corresponding bit in the I2C control register is set.
Writing a zero has no effect on the corresponding bit in the I2C
control register.

0x00

Table 1084

STAT

RO

0x004

I2C Status Register. During I2C operation, this register provides 0xF8
detailed status codes that allow software to determine the next
action needed.

Table 1085

IDAT

R/W

0x008

I2C Data Register. During master or slave transmit mode, data
to be transmitted is written to this register. During master or
slave receive mode, data that has been received may be read
from this register.

0x00

Table 1086

ADR0

R/W

0x00C

I2C Slave Address Register 0. Contains the 7-bit slave
address for operation of the I2C interface in slave mode, and is
not used in master mode. The least significant bit determines
whether a slave responds to the General Call address.

0x00

Table 1087

SCLH

R/W

0x010

SCH Duty Cycle Register High Half Word. Determines the
high time of the I2C clock.

0x04

Table 1088

SCLL

R/W

0x014

SCL Duty Cycle Register Low Half Word. Determines the low 0x04
time of the I2C clock. SCLL and SCLH together determine the
clock frequency generated by an I2C master and certain times
used in slave mode.

Table 1089

CONCLR

WO

0x018

I2C Control Clear Register. When a one is written to a bit of
this register, the corresponding bit in the I2C control register is
cleared. Writing a zero has no effect on the corresponding bit in
the I2C control register.

Table 1090

MMCTRL

R/W

0x01C

Monitor mode control register.

0x00

Table 1091

ADR1

R/W

0x020

I2C Slave Address Register 1. Contains the 7-bit slave
address for operation of the I2C interface in slave mode, and is
not used in master mode. The least significant bit determines
whether a slave responds to the General Call address.

0x00

Table 1092

ADR2

R/W

0x024

I2C Slave Address Register 2. Contains the 7-bit slave
address for operation of the I2C interface in slave mode, and is
not used in master mode. The least significant bit determines
whether a slave responds to the General Call address.

0x00

Table 1092

ADR3

R/W

0x028

I2C Slave Address Register 3. Contains the 7-bit slave
address for operation of the I2C interface in slave mode, and is
not used in master mode. The least significant bit determines
whether a slave responds to the General Call address.

0x00

Table 1092

DATA_
BUFFER

RO

0x02C

Data buffer register. The contents of the 8 MSBs of the DAT
shift register will be transferred to the DATA_BUFFER
automatically after every nine bits (8 bits of data plus ACK or
NACK) has been received on the bus.

0x00

Table 1094

MASK0

R/W

0x030

I2C Slave address mask register 0. This mask register is
0x00
associated with ADR0 to determine an address match. The
mask register has no effect when comparing to the General Call
address (‘0000000’).

Table 1095

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Chapter 46: LPC43xx/LPC43Sxx I2C-bus interface

Table 1083.Register overview: I2C1 (base address 0x400E 0000) …continued
Name

Access Address Description
offset

MASK1

R/W

0x034

I2C Slave address mask register 1. This mask register is
0x00
associated with ADR1 to determine an address match. The
mask register has no effect when comparing to the General Call
address (‘0000000’).

Table 1095

MASK2

R/W

0x038

I2C Slave address mask register 2. This mask register is
0x00
associated with ADR2 to determine an address match. The
mask register has no effect when comparing to the General Call
address (‘0000000’).

Table 1095

MASK3

R/W

0x03C

I2C Slave address mask register 3. This mask register is
0x00
associated with ADR3 to determine an address match. The
mask register has no effect when comparing to the General Call
address (‘0000000’).

Table 1095

[1]

Reset
Reference
value[1]

Reset value reflects the data stored in used bits only. It does not include reserved bits content.

46.7.1 I2C Control Set register
The CONSET registers control setting of bits in the CON register that controls operation of
the I2C interface. Writing a one to a bit of this register causes the corresponding bit in the
I2C control register to be set. Writing a zero has no effect.
Table 1084.I2C Control Set register (CONSET - address 0x400A 1000 (I2C0) and 0x400E 0000
(I2C1)) bit description
Bit

Symbol

Description

Reset
value

1:0

-

Reserved. User software should not write ones to reserved bits.
The value read from a reserved bit is not defined.

-

2

AA

Assert acknowledge flag.

3

SI

I2C interrupt flag.

0

4

STO

STOP flag.

0

5

STA

START flag.

0

I2EN

I2C

0

6

31:7 -

interface enable.

Reserved. The value read from a reserved bit is not defined.

-

I2EN I2C Interface Enable. When I2EN is 1, the I2C interface is enabled. I2EN can be
cleared by writing 1 to the I2ENC bit in the CONCLR register. When I2EN is 0, the I2C
interface is disabled.
When I2EN is “0”, the SDA and SCL input signals are ignored, the I2C block is in the “not
addressed” slave state, and the STO bit is forced to “0”.
I2EN should not be used to temporarily release the I2C-bus since, when I2EN is reset, the
I2C-bus status is lost. The AA flag should be used instead.
STA is the START flag. Setting this bit causes the I2C interface to enter master mode and
transmit a START condition or transmit a Repeated START condition if it is already in
master mode.

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Chapter 46: LPC43xx/LPC43Sxx I2C-bus interface

When STA is 1 and the I2C interface is not already in master mode, it enters master mode,
checks the bus and generates a START condition if the bus is free. If the bus is not free, it
waits for a STOP condition (which will free the bus) and generates a START condition
after a delay of a half clock period of the internal clock generator. If the I2C interface is
already in master mode and data has been transmitted or received, it transmits a
Repeated START condition. STA may be set at any time, including when the I2C interface
is in an addressed slave mode.
STA can be cleared by writing 1 to the STAC bit in the CONCLR register. When STA is 0,
no START condition or Repeated START condition will be generated.
If STA and STO are both set, then a STOP condition is transmitted on the I2C-bus if it the
interface is in master mode, and transmits a START condition thereafter. If the I2C
interface is in slave mode, an internal STOP condition is generated, but is not transmitted
on the bus.
STO is the STOP flag. Setting this bit causes the I2C interface to transmit a STOP
condition in master mode, or recover from an error condition in slave mode. When STO is
1 in master mode, a STOP condition is transmitted on the I2C-bus. When the bus detects
the STOP condition, STO is cleared automatically.
In slave mode, setting this bit can recover from an error condition. In this case, no STOP
condition is transmitted to the bus. The hardware behaves as if a STOP condition has
been received and it switches to “not addressed” slave receiver mode. The STO flag is
cleared by hardware automatically.
SI is the I2C Interrupt Flag. This bit is set when the I2C state changes. However, entering
state F8 does not set SI since there is nothing for an interrupt service routine to do in that
case.
While SI is set, the low period of the serial clock on the SCL line is stretched, and the
serial transfer is suspended. When SCL is HIGH, it is unaffected by the state of the SI flag.
SI must be reset by software, by writing a 1 to the SIC bit in CONCLR register.
AA is the Assert Acknowledge Flag. When set to 1, an acknowledge (low level to SDA)
will be returned during the acknowledge clock pulse on the SCL line on the following
situations:
1. The address in the Slave Address Register has been received.
2. The General Call address has been received while the General Call bit (GC) in ADR is
set.
3. A data byte has been received while the I2C is in the master receiver mode.
4. A data byte has been received while the I2C is in the addressed slave receiver mode
The AA bit can be cleared by writing 1 to the AAC bit in the CONCLR register. When AA is
0, a not acknowledge (HIGH level to SDA) will be returned during the acknowledge clock
pulse on the SCL line on the following situations:
1. A data byte has been received while the I2C is in the master receiver mode.
2. A data byte has been received while the I2C is in the addressed slave receiver mode.

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Chapter 46: LPC43xx/LPC43Sxx I2C-bus interface

46.7.2 I2C Status register
Each I2C Status register reflects the condition of the corresponding I2C interface. The I2C
Status register is Read-Only.
Table 1085.I2C Status register (STAT - address 0x400A 1004 (I2C0) and 0x400E 0004 (I2C1))
bit description
Bit

Symbol

Description

2:0

-

These bits are unused and are always 0.

Reset value

0
I2C

0x1F

7:3

Status

These bits give the actual status information about the
interface.

31:8

-

Reserved. The value read from a reserved bit is not defined.

-

The three least significant bits are always 0. Taken as a byte, the status register contents
represent a status code. There are 26 possible status codes. When the status code is
0xF8, there is no relevant information available and the SI bit is not set. All other 25 status
codes correspond to defined I2C states. When any of these states entered, the SI bit will
be set. For a complete list of status codes, refer to tables from Table 1100 to Table 1105.

46.7.3 I2C Data register
This register contains the data to be transmitted or the data just received. The CPU can
read and write to this register only while it is not in the process of shifting a byte, when the
SI bit is set. Data in DAT remains stable as long as the SI bit is set. Data in DAT is always
shifted from right to left: the first bit to be transmitted is the MSB (bit 7), and after a byte
has been received, the first bit of received data is located at the MSB of DAT.
Table 1086.I2C Data register (DAT - 0x400A 1008 (I2C0) and 0x400E 0008 (I2C1)) bit
description
Bit

Symbol

Description

Reset value

7:0

Data

This register holds data values that have been received or are
to be transmitted.

0

Reserved. The value read from a reserved bit is not defined.

-

31:8 -

46.7.4 I2C Slave Address register 0
This register is readable and writable and are only used when an I2C interface is set to
slave mode. In master mode, this register has no effect. The LSB of ADR is the General
Call bit. When this bit is set, the General Call address (0x00) is recognized.
If this register contains 0x00, the I2C will not acknowledge any address on the bus. This
register will be cleared to this disabled state on reset. Three additional slave address
registers corresponding to addresses 1 to 3 are described Table 1093.
Table 1087.I2C Slave Address register 0 (ADR0 - address 0x400A 100C (I2C0) and
0x400E 000C (I2C1)) bit description

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Bit

Symbol

Description

Reset value

0

GC

General Call enable bit.

0

I2C

device address for slave mode.

0x00

7:1

Address

The

31:8

-

Reserved. The value read from a reserved bit is not defined.

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Chapter 46: LPC43xx/LPC43Sxx I2C-bus interface

46.7.5 I2C SCL HIGH and LOW duty cycle registers
Table 1088.I2C SCL HIGH Duty Cycle register (SCLH - address 0x400A 1010 (I2C0) and
0x400E 0010 (I2C1)) bit description
Bit

Symbol

Description

Reset value

15:0

SCLH

Count for SCL HIGH time period selection.

0x0004

31:16

-

Reserved. The value read from a reserved bit is not defined.

-

Table 1089.I2C SCL Low duty cycle register (SCLL - address 0x400A 1014 (I2C0) and
0x400E 0014 (I2C1)) bit description
Bit

Symbol

Description

Reset value

15:0

SCLL

Count for SCL low time period selection.

0x0004

31:16

-

Reserved. The value read from a reserved bit is not defined.

-

46.7.5.1 Selecting the appropriate I2C data rate and duty cycle
Software must set values for the registers SCLH and SCLL to select the appropriate data
rate and duty cycle. SCLH defines the number of C_PCLK cycles for the SCL HIGH time,
SCLL defines the number of I2C_PCLK cycles for the SCL low time. The frequency is
determined by the following formula (I2C_PCLK is the frequency of the peripheral I2C
clock):
(11)
I2CPCLK
I 2 C bitfrequency = --------------------------------------------------------I2CSCLH + I2CSCLL

The values for SCLL and SCLH must ensure that the data rate is in the appropriate I2C
data rate range. Each register value must be greater than or equal to 4. Table 1090 gives
some examples of I2C-bus rates based on I2C_PCLK frequency and SCLL and SCLH
values.
Table 1090.SCLL + SCLH values for selected I2C clock values
I2C mode

I2C bit
frequency

I2C_PCLK (MHz)
6

8

10

12

16

20

30

40

50

SCLH + SCLL

Standard mode

100 kHz

60

80

100

120

160

200

300

400

500

Fast-mode

400 kHz

15

20

25

30

40

50

75

100

125

Fast-mode Plus

1 MHz

-

8

10

12

16

20

30

40

50

SCLL and SCLH values should not necessarily be the same. Software can set different
duty cycles on SCL by setting these two registers. For example, the I2C-bus specification
defines the SCL low time and high time at different values for a Fast-mode and Fast-mode
Plus I2C.

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Chapter 46: LPC43xx/LPC43Sxx I2C-bus interface

46.7.6 I2C Control Clear register
The CONCLR registers control clearing of bits in the CON register that controls operation
of the I2C interface. Writing a one to a bit of this register causes the corresponding bit in
the I2C control register to be cleared. Writing a zero has no effect.
Table 1091.I2C Control Clear register (CONCLR - address 0x400A 1018 (I2C0) and
0x400E 0018 (I2C1)) bit description
Bit

Symbol

Description

Reset
value

1:0

-

Reserved. User software should not write ones to reserved bits. The
value read from a reserved bit is not defined.

-

2

AAC

Assert acknowledge Clear bit.

3

SIC

I2C interrupt Clear bit.

0

4

-

Reserved. User software should not write ones to reserved bits. The
value read from a reserved bit is not defined.

-

5

STAC

START flag Clear bit.

0

6

I2ENC

I2C interface Disable bit.

0

7

-

Reserved. User software should not write ones to reserved bits. The
value read from a reserved bit is not defined.

-

31:8

-

Reserved. The value read from a reserved bit is not defined.

-

AAC is the Assert Acknowledge Clear bit. Writing a 1 to this bit clears the AA bit in the
CONSET register. Writing 0 has no effect.
SIC is the I2C Interrupt Clear bit. Writing a 1 to this bit clears the SI bit in the CONSET
register. Writing 0 has no effect.
STAC is the START flag Clear bit. Writing a 1 to this bit clears the STA bit in the CONSET
register. Writing 0 has no effect.
I2ENC is the I2C Interface Disable bit. Writing a 1 to this bit clears the I2EN bit in the
CONSET register. Writing 0 has no effect.

46.7.7 I2C Monitor mode control register
This register controls the Monitor mode which allows the I2C module to monitor traffic on
the I2C bus without actually participating in traffic or interfering with the I2C bus.

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Table 1092.I2C Monitor mode control register (MMCTRL - address 0x400A 101C (I2C0) and
0x400E 001C (I2C1)) bit description
Bit

Symbol

0

MM_ENA

Value Description

Reset
value

Monitor mode enable.

0

0

Monitor mode disabled.

1

The I2C module will enter monitor mode. In this mode the
SDA output will be forced high. This will prevent the I2C
module from outputting data of any kind (including ACK)
onto the I2C data bus.
Depending on the state of the ENA_SCL bit, the output may
be also forced high, preventing the module from having
control over the I2C clock line.

1

ENA_SCL

2

SCL output enable.

0

0

When this bit is cleared to ‘0’, the SCL output will be forced
high when the module is in monitor mode. As described
above, this will prevent the module from having any control
over the I2C clock line.

1

When this bit is set, the I2C module may exercise the same
control over the clock line that it would in normal operation.
This means that, acting as a slave peripheral, the I2C
module can “stretch” the clock line (hold it low) until it has
had time to respond to an I2C interrupt.[1]

0

When this bit is cleared, an interrupt will only be generated
when a match occurs to one of the (up-to) four address
registers described above. That is, the module will
respond as a normal slave as far as address-recognition is
concerned.

1

When this bit is set to ‘1’ and the I2C is in monitor mode, an

MATCH_ALL

Select interrupt register match.

0

interrupt will be generated on ANY address received. This
will enable the part to monitor all traffic on the bus.
31:3
[1]

-

-

Reserved. The value read from reserved bits is not defined. -

When the ENA_SCL bit is cleared and the I2C no longer has the ability to stall the bus, interrupt response
time becomes important. To give the part more time to respond to an I2C interrupt under these conditions, a
DATA _BUFFER register is used (Section 46.7.9) to hold received data for a full 9-bit word transmission
time.

Remark: The ENA_SCL and MATCH_ALL bits have no effect if the MM_ENA is ‘0’ (i.e. if
the module is NOT in monitor mode).

46.7.7.1 Interrupt in Monitor mode
All interrupts will occur as normal when the module is in monitor mode. This means that
the first interrupt will occur when an address-match is detected (any address received if
the MATCH_ALL bit is set, otherwise an address matching one of the four address
registers).

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Subsequent to an address-match detection, interrupts will be generated after each data
byte is received for a slave-write transfer, or after each byte that the module “thinks” it has
transmitted for a slave-read transfer. In this second case, the data register will actually
contain data transmitted by some other slave on the bus which was actually addressed by
the master.
Following all of these interrupts, the processor may read the data register to see what was
actually transmitted on the bus.

46.7.7.2 Loss of arbitration in Monitor mode
In monitor mode, the I2C module will not be able to respond to a request for information by
the bus master or issue an ACK). Some other slave on the bus will respond instead. This
will most probably result in a lost-arbitration state as far as our module is concerned.
Software should be aware of the fact that the module is in monitor mode and should not
respond to any loss of arbitration state that is detected.

46.7.8 I2C Slave Address registers 1 to 3
These registers are readable and writable and are only used when an I2C interface is set
to slave mode. In master mode, this register has no effect. The LSB of ADR is the General
Call bit. When this bit is set, the General Call address (0x00) is recognized.
All four registers (including ADR0, see Table 1087) will be cleared to this disabled state on
reset.
You should program the Address field of all four registers to a non-zero value if you
support slave operating mode. Otherwise a zero in any of the four registers will make the
I2C module respond to the General Call address (0x00) unconditionally, i.e. irrespective of
the state of the GC bit. In that case the I2C module state machine would enter state 0x60
(“own SLA+W received”), not state 0x70 (“General Call address received”) as expected
for a General Call.
Only with all four Address fields set to non-zero values, the GC bit takes effect, and (if set)
the state machine enters state 0x70 when receiving a General Call. Responding to a
General Call is enabled if the GC bit is set in at least one of the four registers.
All four slave address comparators are always active. In case you want to be addressed
by a single address only, program this address into ADR0, and duplicate the address into
the three remaining registers. Set the corresponding MASKn register of these duplicates
to 0x00.
For the description of ADR0, see Section 46.7.3. The functionality of all ADRn registers is
identical.
Table 1093.I2C Slave Address registers (ADR - address 0x400A 1020 (ADR1) to 0x400A 1028
(ADR3) (I2C0) and 0x400E 0020 (ADR1) to 0x400E 0028 (ADR3) (I2C1)) bit
description

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Bit

Symbol

Description

Reset value

0

GC

General Call enable bit.

0

7:1

Address

The I2C device address for slave mode.

0x00

31:8

-

Reserved. The value read from a reserved bit is not defined.

-

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46.7.9 I2C Data buffer register
In monitor mode, the I2C module may lose the ability to stretch the clock (stall the bus) if
the ENA_SCL bit is not set. This means that the processor will have a limited amount of
time to read the contents of the data received on the bus. If the processor reads the DAT
shift register, as it ordinarily would, it could have only one bit-time to respond to the
interrupt before the received data is overwritten by new data.
To give the processor more time to respond, a new 8-bit, read-only DATA_BUFFER
register will be added. The contents of the 8 MSBs of the DAT shift register will be
transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus
ACK or NACK) has been received on the bus. This means that the processor will have
nine bit transmission times to respond to the interrupt and read the data before it is
overwritten.
The processor will still have the ability to read DAT directly, as usual, and the behavior of
DAT will not be altered in any way.
Although the DATA_BUFFER register is primarily intended for use in monitor mode with
the ENA_SCL bit = ‘0’, it will be available for reading at any time under any mode of
operation.
Table 1094.I2C Data buffer register (DATA_BUFFER - address 0x400A 102C (I2C0) and
0x400E 002C (I2C1)) bit description
Bit

Symbol Description

Reset value

7:0

Data

This register holds contents of the 8 MSBs of the DAT shift
register.

0

31:8

-

Reserved. The value read from a reserved bit is not defined.

-

46.7.10 I2C Mask registers
The four mask registers each contain seven active bits (7:1). Any bit in these registers
which is set to 1 will cause an automatic match on the corresponding bit of the received
address when it is compared to the ADRn register associated with that mask register. In
other words, bits in an ADRn register which are masked (set to 1) are not taken into
account in determining an address match.
On reset, all mask register bits are cleared to 0.
The mask register has no effect on the comparison to the General Call address
(0000000).
Bits(31:8) and bit(0) of the mask registers are unused and should not be written to. These
bits will always read back as zeros.
When an address-match interrupt occurs, the processor will have to read the data register
(DAT) to determine what the received address was that actually caused the match.

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Table 1095.I2C Mask registers (MASK - address 0x400A 1030 (MASK0) to 0x400A 103C
(MASK3) (I2C0) and 0x400E 0030 (MASK0) to 0x400E 003C (MASK3) (I2C1)) bit
description
Bit

Symbol

Description

Reset value

0

-

Reserved. User software should not write ones to reserved bits.
This bit reads always back as 0.

0

7:1

MASK

Mask bits.

0x00

Reserved. The value read from a reserved bit is not defined.

-

31:8 -

46.8 I2C operating modes
In a given application, the I2C block may operate as a master, a slave, or both. In the slave
mode, the I2C hardware looks for any one of its four slave addresses and the General Call
address. If one of these addresses is detected, an interrupt is requested. If the processor
wishes to become the bus master, the hardware waits until the bus is free before the
master mode is entered so that a possible slave operation is not interrupted. If bus
arbitration is lost in the master mode, the I2C block switches to the slave mode
immediately and can detect its own slave address in the same serial transfer.

46.8.1 Master Transmitter mode
In this mode data is transmitted from master to slave. Before the master transmitter mode
can be entered, the CONSET register must be initialized as shown in Table 1096. I2EN
must be set to 1 to enable the I2C function. If the AA bit is 0, the I2C interface will not
acknowledge any address when another device is master of the bus, so it can not enter
slave mode. The STA, STO and SI bits must be 0. The SI Bit is cleared by writing 1 to the
SIC bit in the CONCLR register. The STA bit should be cleared after writing the slave
address.
Table 1096.CONSET used to configure Master mode
Bit

7

6

5

4

3

2

1

0

Symbol

-

I2EN

STA

STO

SI

AA

-

-

Value

-

1

0

0

0

0

-

-

The first byte transmitted contains the slave address of the receiving device (7 bits) and
the data direction bit. In this mode the data direction bit (R/W) should be 0 which means
Write. The first byte transmitted contains the slave address and Write bit. Data is
transmitted 8 bits at a time. After each byte is transmitted, an acknowledge bit is received.
START and STOP conditions are output to indicate the beginning and the end of a serial
transfer.
The I2C interface will enter master transmitter mode when software sets the STA bit. The
I2C logic will send the START condition as soon as the bus is free. After the START
condition is transmitted, the SI bit is set, and the status code in the STAT register is 0x08.
This status code is used to vector to a state service routine which will load the slave
address and Write bit to the DAT register, and then clear the SI bit. SI is cleared by writing
a 1 to the SIC bit in the CONCLR register.
When the slave address and R/W bit have been transmitted and an acknowledgment bit
has been received, the SI bit is set again, and the possible status codes now are 0x18,
0x20, or 0x38 for the master mode, or 0x68, 0x78, or 0xB0 if the slave mode was enabled
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(by setting AA to 1). The appropriate actions to be taken for each of these status codes
are shown in Table 1100 to Table 1105.

S

SLAVE ADDRESS

RW=0

A

DATA

A

A/A

DATA

P

n bytes data transmitted

A = Acknowledge (SDA low)
from Master to Slave

A = Not acknowledge (SDA high)

from Slave to Master

S = START condition
P = STOP condition

Fig 172. Format in the Master Transmitter mode

46.8.2 Master Receiver mode
In the master receiver mode, data is received from a slave transmitter. The transfer is
initiated in the same way as in the master transmitter mode. When the START condition
has been transmitted, the interrupt service routine must load the slave address and the
data direction bit to the I2C Data register (DAT), and then clear the SI bit. In this case, the
data direction bit (R/W) should be 1 to indicate a read.
When the slave address and data direction bit have been transmitted and an
acknowledge bit has been received, the SI bit is set, and the Status Register will show the
status code. For master mode, the possible status codes are 0x40, 0x48, or 0x38. For
slave mode, the possible status codes are 0x68, 0x78, or 0xB0. For details, refer to
Table 1101.

S

SLAVE ADDRESS

RW=1

A

DATA

A

A

DATA

P

n bytes data received

A = Acknowledge (SDA low)
from Master to Slave

A = Not acknowledge (SDA high)

from Slave to Master

S = START condition
P = STOP condition

Fig 173. Format of Master Receiver mode

After a Repeated START condition, I2C may switch to the master transmitter mode.

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S

SLA

R

A

DATA

A

DATA

A

Sr

SLA

W

A

DATA

A

P

n bytes data transmitted
A = Acknowledge (SDA low)
A = Not acknowledge (SDA high)
From master to slave

S = START condition

From slave to master

P = STOP condition
SLA = Slave Address
Sr = Repeated START condition

Fig 174. A Master Receiver switches to Master Transmitter after sending Repeated START

46.8.3 Slave Receiver mode
In the slave receiver mode, data bytes are received from a master transmitter. To initialize
the slave receiver mode, write any of the Slave Address registers (ADR0-3) and write the
I2C Control Set register (CONSET) as shown in Table 1097.
Table 1097.CONSET used to configure Slave mode
Bit

7

6

5

4

3

2

1

0

Symbol

-

I2EN

STA

STO

SI

AA

-

-

Value

-

1

0

0

0

1

-

-

I2EN must be set to 1 to enable the I2C function. AA bit must be set to 1 to acknowledge
its own slave address or the General Call address. The STA, STO and SI bits are set to 0.
After ADR and CONSET are initialized, the I2C interface waits until it is addressed by its
own address or general address followed by the data direction bit. If the direction bit is 0
(W), it enters slave receiver mode. If the direction bit is 1 (R), it enters slave transmitter
mode. After the address and direction bit have been received, the SI bit is set and a valid
status code can be read from the Status register (STAT). Refer to Table 1104 for the status
codes and actions.

S

SLAVE ADDRESS

RW=0

A

DATA

A

A/A

DATA

P/Sr

n bytes data received

A = Acknowledge (SDA low)
from Master to Slave
from Slave to Master

A = Not acknowledge (SDA high)
S = START condition
P = STOP condition
Sr = Repeated START condition

Fig 175. Format of Slave Receiver mode

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46.8.4 Slave Transmitter mode
The first byte is received and handled as in the slave receiver mode. However, in this
mode, the direction bit will be 1, indicating a read operation. Serial data is transmitted via
SDA while the serial clock is input through SCL. START and STOP conditions are
recognized as the beginning and end of a serial transfer. In a given application, I2C may
operate as a master and as a slave. In the slave mode, the I2C hardware looks for its own
slave address and the General Call address. If one of these addresses is detected, an
interrupt is requested. When the microcontrollers wishes to become the bus master, the
hardware waits until the bus is free before the master mode is entered so that a possible
slave action is not interrupted. If bus arbitration is lost in the master mode, the I2C
interface switches to the slave mode immediately and can detect its own slave address in
the same serial transfer.

S

SLAVE ADDRESS

RW=1

A

DATA

A

A

DATA

P

n bytes data transmitted

A = Acknowledge (SDA low)
from Master to Slave

A = Not acknowledge (SDA high)

from Slave to Master

S = START condition
P = STOP condition

Fig 176. Format of Slave Transmitter mode

46.9 I2C implementation and operation
Figure 177 shows how the on-chip I2C-bus interface is implemented, and the following
text describes the individual blocks.

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8

ADDRESS REGISTERS
I2CnADDR0 to I2CnADDR3
MATCHALL
I2CnMMCTRL[3]
MASK and COMPARE

MASK REGISTERS
I2CnMASK0 to I2CnMASK3

INPUT
FILTER

I2CnDATABUFFER

SDA
SHIFT REGISTER
I2CnDAT

OUTPUT
STAGE

ACK
8

APB BUS

MONITOR MODE
REGISTER
I2CnMMCTRL

BIT COUNTER/
ARBITRATION and
SYNC LOGIC

INPUT
FILTER

PCLK
TIMING and
CONTROL
LOGIC

SCL
OUTPUT
STAGE

SERIAL CLOCK
GENERATOR

interrupt

CONTROL REGISTER and
SCL DUTY CYLE REGISTERS
I2CnCONSET, I2CnCONCLR, I2CnSCLH, I2CnSCLL
16

status
bus

STATUS
DECODER

STATUS REGISTER
I2CnSTAT
8

Fig 177. I2C serial interface block diagram

46.9.1 Input filters and output stages
Input signals are synchronized with the internal clock, and spikes shorter than three
clocks are filtered out.
The output for I2C is a special pad designed to conform to the I2C specification.

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46.9.2 Address Registers, ADR0 to ADR3
These registers may be loaded with the 7-bit slave address (7 most significant bits) to
which the I2C block will respond when programmed as a slave transmitter or receiver. The
LSB (GC) is used to enable General Call address (0x00) recognition. When multiple slave
addresses are enabled, the actual address received may be read from the DAT register at
the state where the own slave address has been received.

46.9.3 Address mask registers, MASK0 to MASK3
The four mask registers each contain seven active bits (7:1). Any bit in these registers
which is set to 1 will cause an automatic match on the corresponding bit of the received
address when it is compared to the ADRn register associated with that mask register. In
other words, bits in an ADRn register which are masked (set to 1) are not taken into
account in determining an address match.
When an address-match interrupt occurs, the processor will have to read the data register
(DAT) to determine which received address actually caused the match.

46.9.4 Comparator
The comparator compares the received 7-bit slave address with its own slave address (7
most significant bits in ADR). It also compares the first received 8-bit byte with the General
Call address (0x00). If an equality is found, the appropriate status bits are set and an
interrupt is requested.

46.9.5 Shift register, DAT
This 8-bit register contains a byte of serial data to be transmitted or a byte which has just
been received. Data in DAT is always shifted from right to left; the first bit to be transmitted
is the MSB (bit 7) and, after a byte has been received, the first bit of received data is
located at the MSB of DAT. While data is being shifted out, data on the bus is
simultaneously being shifted in; DAT always contains the last byte present on the bus.
Thus, in the event of lost arbitration, the transition from master transmitter to slave
receiver is made with the correct data in DAT.

46.9.6 Arbitration and synchronization logic
In the master transmitter mode, the arbitration logic checks that every transmitted logic 1
actually appears as a logic 1 on the I2C-bus. If another device on the bus overrules a logic
1 and pulls the SDA line low, arbitration is lost, and the I2C block immediately changes
from master transmitter to slave receiver. The I2C block will continue to output clock
pulses (on SCL) until transmission of the current serial byte is complete.
Arbitration may also be lost in the master receiver mode. Loss of arbitration in this mode
can only occur while the I2C block is returning a “not acknowledge”: (logic 1) to the bus.
Arbitration is lost when another device on the bus pulls this signal low. Since this can
occur only at the end of a serial byte, the I2C block generates no further clock pulses.
Figure 178 shows the arbitration procedure.

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(1)

(1)

(2)

1

2

3

(3)

SDA line

SCL line

4

8

9
ACK

(1) Another device transmits serial data.
(2) Another device overrules a logic (dotted line) transmitted this I2C master by pulling the SDA line
low. Arbitration is lost, and this I2C enters Slave Receiver mode.
(3) This I2C is in Slave Receiver mode but still generates clock pulses until the current byte has been
transmitted. This I2C will not generate clock pulses for the next byte. Data on SDA originates from
the new master once it has won arbitration.

Fig 178. Arbitration procedure

The synchronization logic will synchronize the serial clock generator with the clock pulses
on the SCL line from another device. If two or more master devices generate clock pulses,
the “mark” duration is determined by the device that generates the shortest “marks”, and
the “space” duration is determined by the device that generates the longest “spaces”.
Figure 179 shows the synchronization procedure.

SDA line
(1)

(3)

(1)

SCL line
(2)
high
period

low
period

(1) Another device pulls the SCL line low before this I2C has timed a complete high time. The other
device effectively determines the (shorter) HIGH period.
(2) Another device continues to pull the SCL line low after this I2C has timed a complete low time and
released SCL. The I2C clock generator is forced to wait until SCL goes HIGH. The other device
effectively determines the (longer) LOW period.
(3) The SCL line is released , and the clock generator begins timing the HIGH time.

Fig 179. Serial clock synchronization

A slave may stretch the space duration to slow down the bus master. The space duration
may also be stretched for handshaking purposes. This can be done after each bit or after
a complete byte transfer. the I2C block will stretch the SCL space duration after a byte has
been transmitted or received and the acknowledge bit has been transferred. The serial
interrupt flag (SI) is set, and the stretching continues until the serial interrupt flag is
cleared.

46.9.7 Serial clock generator
This programmable clock pulse generator provides the SCL clock pulses when the I2C
block is in the master transmitter or master receiver mode. It is switched off when the I2C
block is in slave mode. The I2C output clock frequency and duty cycle is programmable

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via the I2C Clock Control Registers. See the description of the SCLL and SCLH registers
for details. The output clock pulses have a duty cycle as programmed unless the bus is
synchronizing with other SCL clock sources as described above.

46.9.8 Timing and control
The timing and control logic generates the timing and control signals for serial byte
handling. This logic block provides the shift pulses for DAT, enables the comparator,
generates and detects START and STOP conditions, receives and transmits acknowledge
bits, controls the master and slave modes, contains interrupt request logic, and monitors
the I2C-bus status.

46.9.9 Control register, CONSET and CONCLR
The I2C control register contains bits used to control the following I2C block functions: start
and restart of a serial transfer, termination of a serial transfer, bit rate, address recognition,
and acknowledgment.
The contents of the I2C control register may be read as CONSET. Writing to CONSET will
set bits in the I2C control register that correspond to ones in the value written. Conversely,
writing to CONCLR will clear bits in the I2C control register that correspond to ones in the
value written.

46.9.10 Status decoder and status register
The status decoder takes all of the internal status bits and compresses them into a 5-bit
code. This code is unique for each I2C-bus status. The 5-bit code may be used to
generate vector addresses for fast processing of the various service routines. Each
service routine processes a particular bus status. There are 26 possible bus states if all
four modes of the I2C block are used. The 5-bit status code is latched into the five most
significant bits of the status register when the serial interrupt flag is set (by hardware) and
remains stable until the interrupt flag is cleared by software. The three least significant bits
of the status register are always zero. If the status code is used as a vector to service
routines, then the routines are displaced by eight address locations. Eight bytes of code is
sufficient for most of the service routines (see the software example in this section).

46.10 Details of I2C operating modes
The four operating modes are:

•
•
•
•

Master Transmitter
Master Receiver
Slave Receiver
Slave Transmitter

Data transfers in each mode of operation are shown in Figure 180, Figure 181,
Figure 182, Figure 183, and Figure 184. Table 1098 lists abbreviations used in these
figures when describing the I2C operating modes.

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Table 1098.Abbreviations used to describe an I2C operation
Abbreviation

Explanation

S

START Condition

SLA

7-bit slave address

R

Read bit (HIGH level at SDA)

W

Write bit (LOW level at SDA)

A

Acknowledge bit (LOW level at SDA)

A

Not acknowledge bit (HIGH level at SDA)

Data

8-bit data byte

P

STOP condition

In Figure 180 to Figure 184, circles are used to indicate when the serial interrupt flag is
set. The numbers in the circles show the status code held in the STAT register. At these
points, a service routine must be executed to continue or complete the serial transfer.
These service routines are not critical since the serial transfer is suspended until the serial
interrupt flag is cleared by software.
When a serial interrupt routine is entered, the status code in STAT is used to branch to the
appropriate service routine. For each status code, the required software action and details
of the following serial transfer are given in tables from Table 1100 to Table 1106.

46.10.1 Master Transmitter mode
In the master transmitter mode, a number of data bytes are transmitted to a slave receiver
(see Figure 180). Before the master transmitter mode can be entered, CON must be
initialized as follows:
Table 1099.CONSET used to initialize Master Transmitter mode
Bit

7

6

5

4

3

2

1

0

Symbol

-

I2EN

STA

STO

SI

AA

-

-

Value

-

1

0

0

0

x

-

-

The I2C rate must also be configured in the SCLL and SCLH registers. I2EN must be set
to logic 1 to enable the I2C block. If the AA bit is reset, the I2C block will not acknowledge
its own slave address or the General Call address in the event of another device
becoming master of the bus. In other words, if AA is reset, the I2C interface cannot enter
slave mode. STA, STO, and SI must be reset.

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Chapter 46: LPC43xx/LPC43Sxx I2C-bus interface

The master transmitter mode may now be entered by setting the STA bit. The I2C logic will
now test the I2C-bus and generate a START condition as soon as the bus becomes free.
When a START condition is transmitted, the serial interrupt flag (SI) is set, and the status
code in the status register (STAT) will be 0x08. This status code is used by the interrupt
service routine to enter the appropriate state service routine that loads DAT with the slave
address and the data direction bit (SLA+W). The SI bit in CON must then be reset before
the serial transfer can continue.
When the slave address and the direction bit have been transmitted and an
acknowledgment bit has been received, the serial interrupt flag (SI) is set again, and a
number of status codes in STAT are possible. There are 0x18, 0x20, or 0x38 for the
master mode and also 0x68, 0x78, or 0xB0 if the slave mode was enabled (AA = logic 1).
The appropriate action to be taken for each of these status codes is detailed in
Table 1100. After a Repeated START condition (state 0x10). The I2C block may switch to
the master receiver mode by loading DAT with SLA+R).

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Chapter 46: LPC43xx/LPC43Sxx I2C-bus interface

Table 1100.Master Transmitter mode
Status
Code
(STAT)

Status of the I2C-bus Application software response
and hardware
To/From DAT
To CON

0x08

A START condition
Load SLA+W;
has been transmitted. clear STA

0x10

A Repeated START
condition has been
transmitted.

Load SLA+W or

X

0

0

X

As above.

Load SLA+R;
Clear STA

X

0

0

X

SLA+R will be transmitted; the I2C block
will be switched to MST/REC mode.

SLA+W has been
transmitted; ACK has
been received.

Load data byte or

0

0

0

X

Data byte will be transmitted; ACK bit will
be received.

No DAT action or

1

0

0

X

Repeated START will be transmitted.

No DAT action or

0

1

0

X

STOP condition will be transmitted; STO
flag will be reset.

No DAT action

1

1

0

X

STOP condition followed by a START
condition will be transmitted; STO flag will
be reset.

SLA+W has been
Load data byte or
transmitted; NOT ACK
has been received.
No DAT action or

0

0

0

X

Data byte will be transmitted; ACK bit will
be received.

1

0

0

X

Repeated START will be transmitted.

No DAT action or

0

1

0

X

STOP condition will be transmitted; STO
flag will be reset.

No DAT action

1

1

0

X

STOP condition followed by a START
condition will be transmitted; STO flag will
be reset.

Load data byte or

0

0

0

X

Data byte will be transmitted; ACK bit will
be received.

No DAT action or

1

0

0

X

Repeated START will be transmitted.

No DAT action or

0

1

0

X

STOP condition will be transmitted; STO
flag will be reset.

No DAT action

1

1

0

X

STOP condition followed by a START
condition will be transmitted; STO flag will
be reset.

Load data byte or

0

0

0

X

Data byte will be transmitted; ACK bit will
be received.

No DAT action or

1

0

0

X

Repeated START will be transmitted.

No DAT action or

0

1

0

X

STOP condition will be transmitted; STO
flag will be reset.

No DAT action

1

1

0

X

STOP condition followed by a START
condition will be transmitted; STO flag will
be reset.

No DAT action or

0

0

0

X

I2C-bus will be released; not addressed
slave will be entered.

No DAT action

1

0

0

X

A START condition will be transmitted
when the bus becomes free.

0x18

0x20

0x28

0x30

0x38

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Data byte in DAT has
been transmitted;
ACK has been
received.

Data byte in DAT has
been transmitted;
NOT ACK has been
received.

Arbitration lost in
SLA+R/W or Data
bytes.

Next action taken by I2C hardware

STA STO SI

AA

X

X

0

0

SLA+W will be transmitted; ACK bit will
be received.

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Chapter 46: LPC43xx/LPC43Sxx I2C-bus interface

MT
successful
transmission
to a Slave
Receiver

S

SLA

W

A

DATA

A

18H

08H

P

28H

next transfer
started with a
Repeated Start
condition

S

SLA

W

10H

Not
Acknowledge
received after
the Slave
address

A

P

R

20H

Not
Acknowledge
received after a
Data byte

A

P

to Master
receive
mode,
entry
= MR

30H

arbitration lost
in Slave
address or
Data byte

A OR A

other Master
continues

A OR A

38H

arbitration lost
and
addressed as
Slave

A

other Master
continues

38H

other Master
continues

68H 78H B0H

to corresponding
states in Slave mode

from Master to Slave

from Slave to Master

DATA

n

any number of data bytes and their associated Acknowledge bits

this number (contained in I2STA) corresponds to a defined state of the
I2C bus

Fig 180. Format and states in the Master Transmitter mode

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Chapter 46: LPC43xx/LPC43Sxx I2C-bus interface

46.10.2 Master Receiver mode
In the master receiver mode, a number of data bytes are received from a slave transmitter
(see Figure 181). The transfer is initialized as in the master transmitter mode. When the
START condition has been transmitted, the interrupt service routine must load DAT with
the 7-bit slave address and the data direction bit (SLA+R). The SI bit in CON must then be
cleared before the serial transfer can continue.
When the slave address and the data direction bit have been transmitted and an
acknowledgment bit has been received, the serial interrupt flag (SI) is set again, and a
number of status codes in STAT are possible. These are 0x40, 0x48, or 0x38 for the
master mode and also 0x68, 0x78, or 0xB0 if the slave mode was enabled (AA = 1). The
appropriate action to be taken for each of these status codes is detailed in Table 1101.
After a Repeated START condition (state 0x10), the I2C block may switch to the master
transmitter mode by loading DAT with SLA+W.

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Chapter 46: LPC43xx/LPC43Sxx I2C-bus interface

Table 1101.Master Receiver mode
Status
Code
(STAT)

Status of the I2C-bus Application software response
and hardware
To/From DAT
To CON

0x08
0x10

0x38

0x40

0x48

STA STO SI

AA

A START condition
Load SLA+R
has been transmitted.

X

0

0

X

SLA+R will be transmitted; ACK bit will be
received.

A Repeated START
condition has been
transmitted.

Load SLA+R or

X

0

0

X

As above.

Load SLA+W

X

0

0

X

SLA+W will be transmitted; the I2C block
will be switched to MST/TRX mode.

0

0

0

X

I2C-bus will be released; the I2C block will
enter slave mode.

No DAT action

1

0

0

X

A START condition will be transmitted
when the bus becomes free.

No DAT action or

0

0

0

0

Data byte will be received; NOT ACK bit
will be returned.

No DAT action

0

0

0

1

Data byte will be received; ACK bit will be
returned.

1

0

0

X

Repeated START condition will be
transmitted.

0

1

0

X

STOP condition will be transmitted; STO
flag will be reset.

1

1

0

X

STOP condition followed by a START
condition will be transmitted; STO flag will
be reset.

Data byte has been
received; ACK has
been returned.

Read data byte or 0

0

0

0

Data byte will be received; NOT ACK bit
will be returned.

Read data byte

0

0

0

1

Data byte will be received; ACK bit will be
returned.

Data byte has been
received; NOT ACK
has been returned.

Read data byte or 1

0

0

X

Repeated START condition will be
transmitted.

Read data byte or 0

1

0

X

STOP condition will be transmitted; STO
flag will be reset.

Read data byte

1

0

X

STOP condition followed by a START
condition will be transmitted; STO flag will
be reset.

Arbitration lost in NOT No DAT action or
ACK bit.

SLA+R has been
transmitted; ACK has
been received.

SLA+R has been
No DAT action or
transmitted; NOT ACK
has been received.
No DAT action or
No DAT action

0x50

0x58

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Next action taken by I2C hardware

1

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Chapter 46: LPC43xx/LPC43Sxx I2C-bus interface

MR

successful
transmission to
a Slave
transmitter

S

08H

SLA

R

A

DATA

40H

A

DATA

50H

A

P

58H

next transfer
started with a
Repeated Start
condition

S

SLA

R

10H
Not Acknowledge
received after the
Slave address

A

P

W

48H
to Master
transmit
mode, entry
= MT

arbitration lost in
Slave address or
Acknowledge bit

other Master
continues

A OR A

A

38H

arbitration lost
and addressed
as Slave

A

other Master
continues

38H

other Master
continues

68H 78H B0H

to corresponding
states in Slave
mode

from Master to Slave

from Slave to Master

DATA

n

A

any number of data bytes and their associated
Acknowledge bits
this number (contained in I2STA) corresponds to a defined state of
the I2C bus

Fig 181. Format and states in the Master Receiver mode

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Chapter 46: LPC43xx/LPC43Sxx I2C-bus interface

46.10.3 Slave Receiver mode
In the slave receiver mode, a number of data bytes are received from a master transmitter
(see Figure 182). To initiate the slave receiver mode, ADR and CON must be loaded as
follows:
Table 1102.ADR usage in Slave Receiver mode
Bit

7

6

5

Symbol

4

3

2

1

own slave 7-bit address

0

GC

The upper 7 bits are the address to which the I2C block will respond when addressed by a
master. If the LSB (GC) is set, the I2C block will respond to the General Call address
(0x00); otherwise it ignores the General Call address.
Table 1103.CONSET used to initialize Slave Receiver mode
Bit

7

6

5

4

3

2

1

0

Symbol

-

I2EN

STA

STO

SI

AA

-

-

Value

-

1

0

0

0

1

-

-

The I2C-bus rate settings do not affect the I2C block in the slave mode. I2EN must be set
to logic 1 to enable the I2C block. The AA bit must be set to enable the I2C block to
acknowledge its own slave address or the General Call address. STA, STO, and SI must
be reset.
When ADR and CON have been initialized, the I2C block waits until it is addressed by its
own slave address followed by the data direction bit which must be “0” (W) for the I2C
block to operate in the slave receiver mode. After its own slave address and the W bit
have been received, the serial interrupt flag (SI) is set and a valid status code can be read
from STAT. This status code is used to vector to a state service routine. The appropriate
action to be taken for each of these status codes is detailed in Table 1104. The slave
receiver mode may also be entered if arbitration is lost while the I2C block is in the master
mode (see status 0x68 and 0x78).
If the AA bit is reset during a transfer, the I2C block will return a not acknowledge (logic 1)
to SDA after the next received data byte. While AA is reset, the I2C block does not
respond to its own slave address or a General Call address. However, the I2C-bus is still
monitored and address recognition may be resumed at any time by setting AA. This
means that the AA bit may be used to temporarily isolate the I2C block from the I2C-bus.

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Chapter 46: LPC43xx/LPC43Sxx I2C-bus interface

Table 1104.Slave Receiver mode
Status
Code
(STAT)

Status of the I2C-bus Application software response
and hardware
To/From DAT
To CON

0x60

Own SLA+W has
been received; ACK
has been returned.

0x68

0x70

0x78

0x80

0x88

0x90

UM10503

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Next action taken by I2C hardware

STA STO SI

AA

No DAT action or

X

0

0

0

Data byte will be received and NOT ACK
will be returned.

No DAT action

X

0

0

1

Data byte will be received and ACK will
be returned.

Arbitration lost in
SLA+R/W as master;
Own SLA+W has
been received, ACK
returned.

No DAT action or

X

0

0

0

Data byte will be received and NOT ACK
will be returned.

No DAT action

X

0

0

1

Data byte will be received and ACK will
be returned.

General call address
(0x00) has been
received; ACK has
been returned.

No DAT action or

X

0

0

0

Data byte will be received and NOT ACK
will be returned.

No DAT action

X

0

0

1

Data byte will be received and ACK will
be returned.

Arbitration lost in
SLA+R/W as master;
General call address
has been received,
ACK has been
returned.

No DAT action or

X

0

0

0

Data byte will be received and NOT ACK
will be returned.

No DAT action

X

0

0

1

Data byte will be received and ACK will
be returned.

Previously addressed
with own SLV
address; DATA has
been received; ACK
has been returned.

Read data byte or X

0

0

0

Data byte will be received and NOT ACK
will be returned.

Read data byte

X

0

0

1

Data byte will be received and ACK will
be returned.

Previously addressed
with own SLA; DATA
byte has been
received; NOT ACK
has been returned.

Read data byte or 0

0

0

0

Switched to not addressed SLV mode; no
recognition of own SLA or General call
address.

Read data byte or 0

0

0

1

Switched to not addressed SLV mode;
Own SLA will be recognized; General call
address will be recognized if
ADR[0] = logic 1.

Read data byte or 1

0

0

0

Switched to not addressed SLV mode; no
recognition of own SLA or General call
address. A START condition will be
transmitted when the bus becomes free.

Read data byte

1

0

0

1

Switched to not addressed SLV mode;
Own SLA will be recognized; General call
address will be recognized if
ADR[0] = logic 1. A START condition will
be transmitted when the bus becomes
free.

Read data byte or X

0

0

0

Data byte will be received and NOT ACK
will be returned.

Read data byte

0

0

1

Data byte will be received and ACK will
be returned.

Previously addressed
with General Call;
DATA byte has been
received; ACK has
been returned.

X

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Chapter 46: LPC43xx/LPC43Sxx I2C-bus interface

Table 1104.Slave Receiver mode …continued
Status
Code
(STAT)

Status of the I2C-bus Application software response
and hardware
To/From DAT
To CON

0x98

Previously addressed
with General Call;
DATA byte has been
received; NOT ACK
has been returned.

0xA0

UM10503

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STA STO SI

A STOP condition or
Repeated START
condition has been
received while still
addressed as
SLV/REC or
SLV/TRX.

Next action taken by I2C hardware
AA

Read data byte or 0

0

0

0

Switched to not addressed SLV mode; no
recognition of own SLA or General call
address.

Read data byte or 0

0

0

1

Switched to not addressed SLV mode;
Own SLA will be recognized; General call
address will be recognized if
ADR[0] = logic 1.

Read data byte or 1

0

0

0

Switched to not addressed SLV mode; no
recognition of own SLA or General call
address. A START condition will be
transmitted when the bus becomes free.

Read data byte

1

0

0

1

Switched to not addressed SLV mode;
Own SLA will be recognized; General call
address will be recognized if
ADR[0] = logic 1. A START condition will
be transmitted when the bus becomes
free.

No STDAT action
or

0

0

0

0

Switched to not addressed SLV mode; no
recognition of own SLA or General call
address.

No STDAT action
or

0

0

0

1

Switched to not addressed SLV mode;
Own SLA will be recognized; General call
address will be recognized if
ADR[0] = logic 1.

No STDAT action
or

1

0

0

0

Switched to not addressed SLV mode; no
recognition of own SLA or General call
address. A START condition will be
transmitted when the bus becomes free.

No STDAT action

1

0

0

1

Switched to not addressed SLV mode;
Own SLA will be recognized; General call
address will be recognized if
ADR[0] = logic 1. A START condition will
be transmitted when the bus becomes
free.

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Chapter 46: LPC43xx/LPC43Sxx I2C-bus interface

reception of the own
Slave address and one
or more Data bytes all
are acknowledged

S

SLA

W

A

DATA

60H

A

DATA

80H

last data byte
received is Not
acknowledged

A

P OR S

80H

A0H

A

P OR S

88H
arbitration lost as
Master and addressed
as Slave

A

68H

reception of the
General Call address
and one or more Data
bytes

GENERAL CALL

A

DATA

70h

A

DATA

90h

last data byte is Not
acknowledged

A

P OR S

90h

A0H

A

P OR S

98h
arbitration lost as
Master and addressed
as Slave by General
Call

A

78h

from Master to Slave

from Slave to Master

DATA

n

A

any number of data bytes and their associated Acknowledge bits

this number (contained in I2STA) corresponds to a defined state of the 2I C
bus

Fig 182. Format and states in the Slave Receiver mode

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Chapter 46: LPC43xx/LPC43Sxx I2C-bus interface

46.10.4 Slave Transmitter mode
In the slave transmitter mode, a number of data bytes are transmitted to a master receiver
(see Figure 183). Data transfer is initialized as in the slave receiver mode. When ADR and
CON have been initialized, the I2C block waits until it is addressed by its own slave
address followed by the data direction bit which must be “1” (R) for the I2C block to
operate in the slave transmitter mode. After its own slave address and the R bit have been
received, the serial interrupt flag (SI) is set and a valid status code can be read from STAT.
This status code is used to vector to a state service routine, and the appropriate action to
be taken for each of these status codes is detailed in Table 1105. The slave transmitter
mode may also be entered if arbitration is lost while the I2C block is in the master mode
(see state 0xB0).
If the AA bit is reset during a transfer, the I2C block will transmit the last byte of the transfer
and enter state 0xC0 or 0xC8. The I2C block is switched to the not addressed slave mode
and will ignore the master receiver if it continues the transfer. Thus the master receiver
receives all 1s as serial data. While AA is reset, the I2C block does not respond to its own
slave address or a General Call address. However, the I2C-bus is still monitored, and
address recognition may be resumed at any time by setting AA. This means that the AA
bit may be used to temporarily isolate the I2C block from the I2C-bus.

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Chapter 46: LPC43xx/LPC43Sxx I2C-bus interface

Table 1105.Slave Transmitter mode
Status
Code
(STAT)

Status of the I2C-bus Application software response
and hardware
To/From DAT
To CON

0xA8

Own SLA+R has been Load data byte or
received; ACK has
been returned.
Load data byte

0xB0

0xB8

0xC0

0xC8

UM10503

User manual

Arbitration lost in
Load data byte or
SLA+R/W as master;
Own SLA+R has been Load data byte
received, ACK has
been returned.

Next action taken by I2C hardware

STA STO SI

AA

X

0

0

0

Last data byte will be transmitted and
ACK bit will be received.

X

0

0

1

Data byte will be transmitted; ACK will be
received.

X

0

0

0

Last data byte will be transmitted and
ACK bit will be received.

X

0

0

1

Data byte will be transmitted; ACK bit will
be received.

Data byte in DAT has
been transmitted;
ACK has been
received.

Load data byte or

X

0

0

0

Last data byte will be transmitted and
ACK bit will be received.

Load data byte

X

0

0

1

Data byte will be transmitted; ACK bit will
be received.

Data byte in DAT has
been transmitted;
NOT ACK has been
received.

No DAT action or

0

0

0

0

Switched to not addressed SLV mode; no
recognition of own SLA or General call
address.

No DAT action or

0

0

0

1

Switched to not addressed SLV mode;
Own SLA will be recognized; General call
address will be recognized if
ADR[0] = logic 1.

No DAT action or

1

0

0

0

Switched to not addressed SLV mode; no
recognition of own SLA or General call
address. A START condition will be
transmitted when the bus becomes free.

No DAT action

1

0

0

1

Switched to not addressed SLV mode;
Own SLA will be recognized; General call
address will be recognized if
ADR[0] = logic 1. A START condition will
be transmitted when the bus becomes
free.

No DAT action or

0

0

0

0

Switched to not addressed SLV mode; no
recognition of own SLA or General call
address.

No DAT action or

0

0

0

1

Switched to not addressed SLV mode;
Own SLA will be recognized; General call
address will be recognized if
ADR[0] = logic 1.

No DAT action or

1

0

0

0

Switched to not addressed SLV mode; no
recognition of own SLA or General call
address. A START condition will be
transmitted when the bus becomes free.

No DAT action

1

0

0

01

Switched to not addressed SLV mode;
Own SLA will be recognized; General call
address will be recognized if
ADR.0 = logic 1. A START condition will
be transmitted when the bus becomes
free.

Last data byte in DAT
has been transmitted
(AA = 0); ACK has
been received.

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reception of the own
Slave address and
one or more Data
bytes all are
acknowledged

S

SLA

R

A

DATA

A8H

arbitration lost as
Master and
addressed as Slave

A

DATA

B8H

A

P OR S

C0H

A

B0H

last data byte
transmitted. Switched
to Not Addressed
Slave (AA bit in
I2CON = “0”)

A

ALL ONES

P OR S

C8H

from Master to Slave

from Slave to Master

DATA

n

A

any number of data bytes and their associated
Acknowledge bits

this number (contained in I2STA) corresponds to a defined state of
the I2C bus

Fig 183. Format and states in the Slave Transmitter mode

46.10.5 Miscellaneous states
There are two STAT codes that do not correspond to a defined I2C hardware state (see
Table 1106). These are discussed below.

46.10.5.1 STAT = 0xF8
This status code indicates that no relevant information is available because the serial
interrupt flag, SI, is not yet set. This occurs between other states and when the I2C block
is not involved in a serial transfer.

46.10.5.2 STAT = 0x00
This status code indicates that a bus error has occurred during an I2C serial transfer. A
bus error is caused when a START or STOP condition occurs at an illegal position in the
format frame. Examples of such illegal positions are during the serial transfer of an
address byte, a data byte, or an acknowledge bit. A bus error may also be caused when
external interference disturbs the internal I2C block signals. When a bus error occurs, SI is
set. To recover from a bus error, the STO flag must be set and SI must be cleared. This

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Chapter 46: LPC43xx/LPC43Sxx I2C-bus interface

causes the I2C block to enter the “not addressed” slave mode (a defined state) and to
clear the STO flag (no other bits in CON are affected). The SDA and SCL lines are
released (a STOP condition is not transmitted).
Table 1106.Miscellaneous States
Status
Code
(STAT)

Status of the I2C-bus Application software response
and hardware
To/From DAT
To CON

0xF8

No relevant state
information available;
SI = 0.

0x00

Bus error during MST No DAT action
or selected slave
modes, due to an
illegal START or
STOP condition. State
0x00 can also occur
when interference
causes the I2C block
to enter an undefined
state.

STA STO SI

No DAT action

Next action taken by I2C hardware
AA

No CON action

0

1

0

X

Wait or proceed current transfer.

Only the internal hardware is affected in
the MST or addressed SLV modes. In all
cases, the bus is released and the I2C
block is switched to the not addressed
SLV mode. STO is reset.

46.10.6 Some special cases
The I2C hardware has facilities to handle the following special cases that may occur
during a serial transfer:

•
•
•
•
•

Simultaneous Repeated START conditions from two masters
Data transfer after loss of arbitration
Forced access to the I2C-bus
I2C-bus obstructed by a LOW level on SCL or SDA
Bus error

46.10.6.1 Simultaneous Repeated START conditions from two masters
A Repeated START condition may be generated in the master transmitter or master
receiver modes. A special case occurs if another master simultaneously generates a
Repeated START condition (see Figure 184). Until this occurs, arbitration is not lost by
either master since they were both transmitting the same data.
If the I2C hardware detects a Repeated START condition on the I2C-bus before generating
a Repeated START condition itself, it will release the bus, and no interrupt request is
generated. If another master frees the bus by generating a STOP condition, the I2C block
will transmit a normal START condition (state 0x08), and a retry of the total serial data
transfer can commence.

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Chapter 46: LPC43xx/LPC43Sxx I2C-bus interface

S

SLA

W

08H

A

DATA

A

18H

S

OTHER MASTER
CONTINUES

28H

other Master sends
repeated START earlier

P

S

SLA

08H

retry

Fig 184. Simultaneous Repeated START conditions from two masters

46.10.6.2 Data transfer after loss of arbitration
Arbitration may be lost in the master transmitter and master receiver modes (see
Figure 178). Loss of arbitration is indicated by the following states in STAT; 0x38, 0x68,
0x78, and 0xB0 (see Figure 180 and Figure 181).
If the STA flag in CON is set by the routines which service these states, then, if the bus is
free again, a START condition (state 0x08) is transmitted without intervention by the CPU,
and a retry of the total serial transfer can commence.

46.10.6.3 Forced access to the I2C-bus
In some applications, it may be possible for an uncontrolled source to cause a bus
hang-up. In such situations, the problem may be caused by interference, temporary
interruption of the bus or a temporary short-circuit between SDA and SCL.
If an uncontrolled source generates a superfluous START or masks a STOP condition,
then the I2C-bus stays busy indefinitely. If the STA flag is set and bus access is not
obtained within a reasonable amount of time, then a forced access to the I2C-bus is
possible. This is achieved by setting the STO flag while the STA flag is still set. No STOP
condition is transmitted. The I2C hardware behaves as if a STOP condition was received
and is able to transmit a START condition. The STO flag is cleared by hardware (see
Figure 185).

time limit
STA flag

STO flag
SDA line

SCL line
start
condition

Fig 185. Forced access to a busy I2C-bus

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Chapter 46: LPC43xx/LPC43Sxx I2C-bus interface

46.10.6.4 I2C-bus obstructed by a LOW level on SCL or SDA
An I2C-bus hang-up can occur if either the SDA or SCL line is held LOW by any device on
the bus. If the SCL line is obstructed (pulled LOW) by a device on the bus, no further serial
transfer is possible, and the problem must be resolved by the device that is pulling the
SCL bus line LOW.
Typically, the SDA line may be obstructed by another device on the bus that has become
out of synchronization with the current bus master by either missing a clock, or by sensing
a noise pulse as a clock. In this case, the problem can be solved by transmitting additional
clock pulses on the SCL line (see Figure 186). The I2C interface does not include a
dedicated time-out timer to detect an obstructed bus, but this can be implemented using
another timer in the system. When detected, software can force clocks (up to 9 may be
required) on SCL until SDA is released by the offending device. At that point, the slave
may still be out of synchronization, so a START should be generated to insure that all I2C
peripherals are synchronized.

STA flag
(2)
(1)

SDA line

(3)

(1)

SCL line
start
condition

(1) Unsuccessful attempt to send a START condition.
(2) SDA line is released.
(3) Successful attempt to send a START condition. State 08H is entered.

Fig 186. Recovering from a bus obstruction caused by a LOW level on SDA

46.10.6.5 Bus error
A bus error occurs when a START or STOP condition is detected at an illegal position in
the format frame. Examples of illegal positions are during the serial transfer of an address
byte, a data bit, or an acknowledge bit.
The I2C hardware only reacts to a bus error when it is involved in a serial transfer either as
a master or an addressed slave. When a bus error is detected, the I2C block immediately
switches to the not addressed slave mode, releases the SDA and SCL lines, sets the
interrupt flag, and loads the status register with 0x00. This status code may be used to
vector to a state service routine which either attempts the aborted serial transfer again or
simply recovers from the error condition as shown in Table 1106.

46.10.7 I2C state service routines
This section provides examples of operations that must be performed by various I2C state
service routines. This includes:

• Initialization of the I2C block after a Reset.
• I2C Interrupt Service
• The 26 state service routines providing support for all four I2C operating modes.
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Chapter 46: LPC43xx/LPC43Sxx I2C-bus interface

46.10.8 Initialization
In the initialization example, the I2C block is enabled for both master and slave modes.
For each mode, a buffer is used for transmission and reception. The initialization routine
performs the following functions:

• I2ADR is loaded with the part’s own slave address and the General Call bit (GC)
• The I2C interrupt enable and interrupt priority bits are set
• The slave mode is enabled by simultaneously setting the I2EN and AA bits in CON
and the serial clock frequency (for master modes) is defined by is defined by loading
the SCLH and SCLL registers. The master routines must be started in the main program.
The I2C hardware now begins checking the I2C-bus for its own slave address and General
Call. If the General Call or the own slave address is detected, an interrupt is requested
and STAT is loaded with the appropriate state information.

46.10.9 I2C interrupt service
When the I2C interrupt is entered, STAT contains a status code which identifies one of the
26 state services to be executed.

46.10.10 The state service routines
Each state routine is part of the I2C interrupt routine and handles one of the 26 states.

46.10.11 Adapting state services to an application
The state service examples show the typical actions that must be performed in response
to the 26 I2C state codes. If one or more of the four I2C operating modes are not used, the
associated state services can be omitted, as long as care is taken that the those states
can never occur.
In an application, it may be desirable to implement some kind of time-out during I2C
operations, in order to trap an inoperative bus or a lost service routine.

46.11 Software example
46.11.1 Initialization routine
Example to initialize I2C Interface as a Slave and/or Master.
1. Load ADR with own Slave Address, enable General Call recognition if needed.
2. Enable I2C interrupt.
3. Write 0x44 to CONSET to set the I2EN and AA bits, enabling Slave functions. For
Master only functions, write 0x40 to CONSET.

46.11.2 Start Master Transmit function
Begin a Master Transmit operation by setting up the buffer, pointer, and data count, then
initiating a START.
1. Initialize Master data counter.
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Chapter 46: LPC43xx/LPC43Sxx I2C-bus interface

2. Set up the Slave Address to which data will be transmitted, and add the Write bit.
3. Write 0x20 to CONSET to set the STA bit.
4. Set up data to be transmitted in Master Transmit buffer.
5. Initialize the Master data counter to match the length of the message being sent.
6. Exit

46.11.3 Start Master Receive function
Begin a Master Receive operation by setting up the buffer, pointer, and data count, then
initiating a START.
1. Initialize Master data counter.
2. Set up the Slave Address to which data will be transmitted, and add the Read bit.
3. Write 0x20 to CONSET to set the STA bit.
4. Set up the Master Receive buffer.
5. Initialize the Master data counter to match the length of the message to be received.
6. Exit

46.11.4 I2C interrupt routine
Determine the I2C state and which state routine will be used to handle it.
1. Read the I2C status from STA.
2. Use the status value to branch to one of 26 possible state routines.

46.11.5 Non mode specific states
46.11.5.1 State: 0x00
Bus Error. Enter not addressed Slave mode and release bus.
1. Write 0x14 to CONSET to set the STO and AA bits.
2. Write 0x08 to CONCLR to clear the SI flag.
3. Exit

46.11.5.2 Master States
State 08 and State 10 are for both Master Transmit and Master Receive modes. The R/W
bit decides whether the next state is within Master Transmit mode or Master Receive
mode.

46.11.5.3 State: 0x08
A START condition has been transmitted. The Slave Address + R/W bit will be
transmitted, an ACK bit will be received.
1. Write Slave Address with R/W bit to DAT.
2. Write 0x04 to CONSET to set the AA bit.
3. Write 0x08 to CONCLR to clear the SI flag.
4. Set up Master Transmit mode data buffer.
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Chapter 46: LPC43xx/LPC43Sxx I2C-bus interface

5. Set up Master Receive mode data buffer.
6. Initialize Master data counter.
7. Exit

46.11.5.4 State: 0x10
A Repeated START condition has been transmitted. The Slave Address + R/W bit will be
transmitted, an ACK bit will be received.
1. Write Slave Address with R/W bit to DAT.
2. Write 0x04 to CONSET to set the AA bit.
3. Write 0x08 to CONCLR to clear the SI flag.
4. Set up Master Transmit mode data buffer.
5. Set up Master Receive mode data buffer.
6. Initialize Master data counter.
7. Exit

46.11.6 Master Transmitter states
46.11.6.1 State: 0x18
Previous state was State 8 or State 10, Slave Address + Write has been transmitted, ACK
has been received. The first data byte will be transmitted, an ACK bit will be received.
1. Load DAT with first data byte from Master Transmit buffer.
2. Write 0x04 to CONSET to set the AA bit.
3. Write 0x08 to CONCLR to clear the SI flag.
4. Increment Master Transmit buffer pointer.
5. Exit

46.11.6.2 State: 0x20
Slave Address + Write has been transmitted, NOT ACK has been received. A STOP
condition will be transmitted.
1. Write 0x14 to CONSET to set the STO and AA bits.
2. Write 0x08 to CONCLR to clear the SI flag.
3. Exit

46.11.6.3 State: 0x28
Data has been transmitted, ACK has been received. If the transmitted data was the last
data byte then transmit a STOP condition, otherwise transmit the next data byte.
1. Decrement the Master data counter, skip to step 5 if not the last data byte.
2. Write 0x14 to CONSET to set the STO and AA bits.
3. Write 0x08 to CONCLR to clear the SI flag.
4. Exit
5. Load DAT with next data byte from Master Transmit buffer.
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Chapter 46: LPC43xx/LPC43Sxx I2C-bus interface

6. Write 0x04 to CONSET to set the AA bit.
7. Write 0x08 to CONCLR to clear the SI flag.
8. Increment Master Transmit buffer pointer
9. Exit

46.11.6.4 State: 0x30
Data has been transmitted, NOT ACK received. A STOP condition will be transmitted.
1. Write 0x14 to CONSET to set the STO and AA bits.
2. Write 0x08 to CONCLR to clear the SI flag.
3. Exit

46.11.6.5 State: 0x38
Arbitration has been lost during Slave Address + Write or data. The bus has been
released and not addressed Slave mode is entered. A new START condition will be
transmitted when the bus is free again.
1. Write 0x24 to CONSET to set the STA and AA bits.
2. Write 0x08 to CONCLR to clear the SI flag.
3. Exit

46.11.7 Master Receive states
46.11.7.1 State: 0x40
Previous state was State 08 or State 10. Slave Address + Read has been transmitted,
ACK has been received. Data will be received and ACK returned.
1. Write 0x04 to CONSET to set the AA bit.
2. Write 0x08 to CONCLR to clear the SI flag.
3. Exit

46.11.7.2 State: 0x48
Slave Address + Read has been transmitted, NOT ACK has been received. A STOP
condition will be transmitted.
1. Write 0x14 to CONSET to set the STO and AA bits.
2. Write 0x08 to CONCLR to clear the SI flag.
3. Exit

46.11.7.3 State: 0x50
Data has been received, ACK has been returned. Data will be read from DAT. Additional
data will be received. If this is the last data byte then NOT ACK will be returned, otherwise
ACK will be returned.
1. Read data byte from DAT into Master Receive buffer.
2. Decrement the Master data counter, skip to step 5 if not the last data byte.
3. Write 0x0C to CONCLR to clear the SI flag and the AA bit.
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4. Exit
5. Write 0x04 to CONSET to set the AA bit.
6. Write 0x08 to CONCLR to clear the SI flag.
7. Increment Master Receive buffer pointer
8. Exit

46.11.7.4 State: 0x58
Data has been received, NOT ACK has been returned. Data will be read from DAT. A
STOP condition will be transmitted.
1. Read data byte from DAT into Master Receive buffer.
2. Write 0x14 to CONSET to set the STO and AA bits.
3. Write 0x08 to CONCLR to clear the SI flag.
4. Exit

46.11.8 Slave Receiver states
46.11.8.1 State: 0x60
Own Slave Address + Write has been received, ACK has been returned. Data will be
received and ACK returned.
1. Write 0x04 to CONSET to set the AA bit.
2. Write 0x08 to CONCLR to clear the SI flag.
3. Set up Slave Receive mode data buffer.
4. Initialize Slave data counter.
5. Exit

46.11.8.2 State: 0x68
Arbitration has been lost in Slave Address and R/W bit as bus Master. Own Slave Address
+ Write has been received, ACK has been returned. Data will be received and ACK will be
returned. STA is set to restart Master mode after the bus is free again.
1. Write 0x24 to CONSET to set the STA and AA bits.
2. Write 0x08 to CONCLR to clear the SI flag.
3. Set up Slave Receive mode data buffer.
4. Initialize Slave data counter.
5. Exit.

46.11.8.3 State: 0x70
General call has been received, ACK has been returned. Data will be received and ACK
returned.
1. Write 0x04 to CONSET to set the AA bit.
2. Write 0x08 to CONCLR to clear the SI flag.
3. Set up Slave Receive mode data buffer.
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Chapter 46: LPC43xx/LPC43Sxx I2C-bus interface

4. Initialize Slave data counter.
5. Exit

46.11.8.4 State: 0x78
Arbitration has been lost in Slave Address + R/W bit as bus Master. General call has been
received and ACK has been returned. Data will be received and ACK returned. STA is set
to restart Master mode after the bus is free again.
1. Write 0x24 to CONSET to set the STA and AA bits.
2. Write 0x08 to CONCLR to clear the SI flag.
3. Set up Slave Receive mode data buffer.
4. Initialize Slave data counter.
5. Exit

46.11.8.5 State: 0x80
Previously addressed with own Slave Address. Data has been received and ACK has
been returned. Additional data will be read.
1. Read data byte from DAT into the Slave Receive buffer.
2. Decrement the Slave data counter, skip to step 5 if not the last data byte.
3. Write 0x0C to CONCLR to clear the SI flag and the AA bit.
4. Exit.
5. Write 0x04 to CONSET to set the AA bit.
6. Write 0x08 to CONCLR to clear the SI flag.
7. Increment Slave Receive buffer pointer.
8. Exit

46.11.8.6 State: 0x88
Previously addressed with own Slave Address. Data has been received and NOT ACK
has been returned. Received data will not be saved. Not addressed Slave mode is
entered.
1. Write 0x04 to CONSET to set the AA bit.
2. Write 0x08 to CONCLR to clear the SI flag.
3. Exit

46.11.8.7 State: 0x90
Previously addressed with General Call. Data has been received, ACK has been returned.
Received data will be saved. Only the first data byte will be received with ACK. Additional
data will be received with NOT ACK.
1. Read data byte from DAT into the Slave Receive buffer.
2. Write 0x0C to CONCLR to clear the SI flag and the AA bit.
3. Exit

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Chapter 46: LPC43xx/LPC43Sxx I2C-bus interface

46.11.8.8 State: 0x98
Previously addressed with General Call. Data has been received, NOT ACK has been
returned. Received data will not be saved. Not addressed Slave mode is entered.
1. Write 0x04 to CONSET to set the AA bit.
2. Write 0x08 to CONCLR to clear the SI flag.
3. Exit

46.11.8.9 State: 0xA0
A STOP condition or Repeated START has been received, while still addressed as a
Slave. Data will not be saved. Not addressed Slave mode is entered.
1. Write 0x04 to CONSET to set the AA bit.
2. Write 0x08 to CONCLR to clear the SI flag.
3. Exit

46.11.9 Slave Transmitter states
46.11.9.1 State: 0xA8
Own Slave Address + Read has been received, ACK has been returned. Data will be
transmitted, ACK bit will be received.
1. Load DAT from Slave Transmit buffer with first data byte.
2. Write 0x04 to CONSET to set the AA bit.
3. Write 0x08 to CONCLR to clear the SI flag.
4. Set up Slave Transmit mode data buffer.
5. Increment Slave Transmit buffer pointer.
6. Exit

46.11.9.2 State: 0xB0
Arbitration lost in Slave Address and R/W bit as bus Master. Own Slave Address + Read
has been received, ACK has been returned. Data will be transmitted, ACK bit will be
received. STA is set to restart Master mode after the bus is free again.
1. Load DAT from Slave Transmit buffer with first data byte.
2. Write 0x24 to CONSET to set the STA and AA bits.
3. Write 0x08 to CONCLR to clear the SI flag.
4. Set up Slave Transmit mode data buffer.
5. Increment Slave Transmit buffer pointer.
6. Exit

46.11.9.3 State: 0xB8
Data has been transmitted, ACK has been received. Data will be transmitted, ACK bit will
be received.
1. Load DAT from Slave Transmit buffer with data byte.
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Chapter 46: LPC43xx/LPC43Sxx I2C-bus interface

2. Write 0x04 to CONSET to set the AA bit.
3. Write 0x08 to CONCLR to clear the SI flag.
4. Increment Slave Transmit buffer pointer.
5. Exit

46.11.9.4 State: 0xC0
Data has been transmitted, NOT ACK has been received. Not addressed Slave mode is
entered.
1. Write 0x04 to CONSET to set the AA bit.
2. Write 0x08 to CONCLR to clear the SI flag.
3. Exit.

46.11.9.5 State: 0xC8
The last data byte has been transmitted, ACK has been received. Not addressed Slave
mode is entered.
1. Write 0x04 to CONSET to set the AA bit.
2. Write 0x08 to CONCLR to clear the SI flag.
3. Exit

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Chapter 47: LPC43xx/LPC43Sxx 10-bit ADC0/1
Rev. 2.4 — 22 August 2018

User manual

47.1 How to read this chapter
ADC0 and ADC1 are available on all LPC43xx/LPC43Sxx parts. The number of ADC
channels is limited on small packages.
The 10-bit ADCs are not available on the TFBGA100 package on part LPC4370. This part
has the 12-bit ADCHS only.
Remark: The pinning for the 10-bit ADC function depends on whether the 12-bit ADCHS
is also present or not. For parts with the 12-bit ADCHS (LPC4370), see Table 1107, and
for parts without the 12-bit ADCHS (LPC435x/3x/2x/1), see Table 1108.

LBGA256

TFBGA100

Table 1107.10-bit ADC0/1 channels for different packages on parts LPC4370 (with 12-bit
ADCHS)
Pin

Notes

P4_3

yes

-

Channel 0 ADC0.

P4_1

yes

-

Channel 1 ADC0.

PF_8

yes

-

Channel 2 ADC0.

P7_5

yes

-

Channel 3 ADC0.

P7_4

yes

-

Channel 4 ADC0.

PF_10

yes

-

Channel 5 ADC0.

PB_6

yes

-

Channel 6 ADC0.

ADC0_7/ ADC1_7

yes

-

Channel 7 ADC0.

PC_3

yes

-

Channel 0 ADC1.

PC_0

yes

-

Channel 1 ADC1.

PF_9

yes

-

Channel 2 ADC1.

PF_6

yes

-

Channel 3 ADC1.

PF_5

yes

-

Channel 4 ADC1.

PF_11

yes

-

Channel 5 ADC1.

P7_7

yes

-

Channel 6 ADC1.

PF_7

yes

-

Channel 7 ADC1.

Table 1108.10-bit ADC0/1 channels for different packages on parts LPC435x/3x/2x/1x (without 12-bit ADCHS))
TFBGA180

TFBGA100

LQFP208

LQFP144

LQFP100

Notes

LBGA256

Pin

P4_3

yes

yes

-

yes

yes

-

Channel 0 ADC0 and channel 0 ADC1 and DAC.

P4_1

yes

yes

-

yes

yes

-

Channel 1 ADC0 and channel 1 ADC1.

PF_8

yes

-

-

-

-

-

Channel 2 ADC0 and channel 2 ADC1.

P7_5

yes

yes

-

yes

yes

-

Channel 3 ADC0 and channel 3 ADC1.

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Table 1108.10-bit ADC0/1 channels for different packages on parts LPC435x/3x/2x/1x (without 12-bit ADCHS))
TFBGA180

TFBGA100

LQFP208

LQFP144

LQFP100

Notes

LBGA256

Pin

P7_4

yes

yes

-

yes

yes

-

Channel 4 ADC0 and channel 4 ADC1.

PF_10

yes

-

-

yes

-

-

Channel 5 ADC0 and channel 5 ADC1.

PB_6

yes

yes

-

-

-

-

Channel 6 ADC0 and channel 6 ADC1.

PC_3

yes

-

-

yes

-

-

Channel 0 ADC0 and channel 0 ADC1 and DAC.

PC_0

yes

yes

-

yes

-

-

Channel 1 ADC0 and channel 1 ADC1.

PF_9

yes

-

-

yes

-

-

Channel 2 ADC0 and channel 2 ADC1.

PF_6

yes

-

-

yes

-

-

Channel 3 ADC0 and channel 3 ADC1.

PF_5

yes

-

-

yes

-

-

Channel 4 ADC0 and channel 4 ADC1.

PF_11

yes

-

-

yes

-

-

Channel 5 ADC0 and channel 5 ADC1.

P7_7

yes

yes

-

yes

yes

-

Channel 6 ADC0 and channel 6 ADC1.

PF_7

yes

-

-

yes

-

-

Channel 7 ADC0 and channel 7 ADC1.

P4_4

yes

yes

-

yes

yes

-

Channel 0 ADC0 and channel 0 ADC1 and DAC.

ADC0_0/ ADC1_0/DAC

yes

yes

yes

yes

yes

-

Channel 0 ADC0 and channel 0 ADC1 and DAC.

ADC0_1/ ADC1_1

yes

yes

yes

yes

yes

-

Channel 1 ADC0 and channel 1 ADC1.

ADC0_2/ ADC1_2

yes

yes

yes

yes

yes

-

Channel 2 ADC0 and channel 2 ADC1.

ADC0_3/ ADC1_3

yes

yes

yes

yes

yes

-

Channel 3 ADC0 and channel 3 ADC1.

ADC0_4/ ADC1_4

yes

yes

-

yes

yes

-

Channel 4 ADC0 and channel 4 ADC1.

ADC0_5/ ADC1_5

yes

yes

-

yes

yes

-

Channel 5 ADC0 and channel 5 ADC1.

ADC0_6/ ADC1_6

yes

yes

-

yes

yes

-

Channel 6 ADC0 and channel 6 ADC1.

ADC0_7/ ADC1_7

yes

yes

-

yes

yes

-

Channel 7 ADC0 and channel 7 ADC1.

47.2 Basic configuration
The ADC0 and ADC1 are configured as follows:

•
•
•
•
•
•

See Table 1109 for clocking and power control.
The ADC0 is reset by the ADC0_RST (reset # 40).
The ADC1 is reset by the ADC1_RST (reset # 41).
The ADC0 interrupt is connected to interrupt slot # 17 in the NVIC.
The ADC1 interrupt is connected to interrupt slot # 21 in the NVIC.
For connecting to the GPDMA, use the DMAMUX register (Table 100) in the CREG
block and enable the GPDMA channel in the DMA Channel Configuration registers
Section 21.6.20.

• External pins (ADCTRIG0/1)and the MOTOCON PWM MCOA2 output can be
selected as conversion triggers for ADC0/1 (see Table 1113).

• The ADC conversion triggers are connected through the GIMA (see Table 207) to the
timers or SCT outputs.

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• For the ADC0 and ADC1 inputs that are multiplexed with digital functions, the pins
need to be configured using the ENAIO0/1 registers (see Section 17.4.6 and
Section 17.4.8.

• The ADC1 channel 7 is connected to the bandgap reference (see Section 17.4.8.1).
Table 1109.ADC0/1 clocking and power control
Base clock

Branch clock

Operating
frequency

Notes

ADC0 clock

BASE_APB3_CLK CLK_APB3_ADC0 up to 204 MHz For register interface and
ADC0 conversion rate.

ADC1 clock

BASE_APB3_CLK CLK_APB3_ADC1 up to 204 MHz For register interface and
ADC1 conversion rate.

47.3 Features
•
•
•
•
•
•
•
•
•

10 bit successive approximation analog to digital converter.
Input multiplexing among 8 pins.
Power-down mode.
Measurement range 0 to 3.3 V.
10-bit conversion time = 2.45 s.
Burst conversion mode for single or multiple inputs.
Optional conversion on transition on input pin or Timer Match signal.
Individual result registers for each A/D channel to reduce interrupt overhead.\
Connected to bandgap reference (see Section 17.4.8.1).

47.4 General description
Basic clocking for the A/D converters is provided by the APB clocks
(CLK_APB4_ADC0/1). A programmable divider is included in each converter to scale this
clock to the 4.5 MHz (max) clock needed by the successive approximation process. A fully
accurate conversion requires 11 of these clocks.

47.5 Pin description
Table 1110 gives a brief summary of each of ADC related pins.

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Chapter 47: LPC43xx/LPC43Sxx 10-bit ADC0/1

Table 1110. ADC pin description
Pin
function

Type

ADC0_[7:0]/ Input
ADC1_[7:0]

Description

Shared Analog Inputs. The A/D converter cell can measure the voltage
on any of these input signals. The inputs are shared between ADC0 and
ADC1 on analog-only pins
Remark: The ADC0 pin is shared with the DAC0 pin.

ADC0_[6:0]

Input

Analog inputs.Inputs from multiplexed analog/digital pins to ADC0. The
A/D converter cell can measure the voltage on any of these input signals.
These pins are shared with ADC1.

ADC1_[7:0]

Input

Analog inputs.Inputs from multiplexed analog/digital pins to ADC1. The
A/D converter cell can measure the voltage on any of these input signals.
These pins are shared with ADC0.

ADCTRIG0

Input

Trigger inputs to the ADC0/1.

ADCTRIG1

Input

Trigger inputs to the ADC0/1.

VDDA

Power

Analog Power. Also voltage reference VREF for both ADCs.

VSSA

Ground

Analog ground.

47.6 Register description
The register addresses for the ADC0 are shown in Table 1111
Table 1111. Register overview: ADC0 (base address 0x400E 3000)
Name

Access Address
offset

Description

CR

R/W

0x000

A/D Control Register. The AD0CR register must be written to 0x0000 0000 Table 1113
select the operating mode before A/D conversion can occur.

GDR

R0

0x004

A/D Global Data Register. Contains the result of the most
recent A/D conversion.

-

-

-

0x008

Reserved.

-

INTEN

R/W

0x00C

A/D Interrupt Enable Register. This register contains enable
bits that allow the DONE flag of each A/D channel to be
included or excluded from contributing to the generation of
an A/D interrupt.

0x0000 0100 Table 1115

DR0

RO

0x010

A/D Channel 0 Data Register. This register contains the
result of the most recent conversion completed on channel 0

Table 1116

DR1

RO

0x014

A/D Channel 1 Data Register. This register contains the
result of the most recent conversion completed on channel 1.

Table 1116

DR2

RO

0x018

A/D Channel 2 Data Register. This register contains the
result of the most recent conversion completed on channel 2.

Table 1116

DR3

RO

0x01C

A/D Channel 3 Data Register. This register contains the
result of the most recent conversion completed on channel 3.

Table 1116

DR4

RO

0x020

A/D Channel 4 Data Register. This register contains the
result of the most recent conversion completed on channel 4.

Table 1116

DR5

RO

0x024

A/D Channel 5 Data Register. This register contains the
result of the most recent conversion completed on channel 5.

Table 1116

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Chapter 47: LPC43xx/LPC43Sxx 10-bit ADC0/1

Table 1111. Register overview: ADC0 (base address 0x400E 3000)
Name

Access Address
offset

Description

DR6

RO

0x028

A/D Channel 6 Data Register. This register contains the
result of the most recent conversion completed on channel 6.

Table 1116

DR7

RO

0x02C

A/D Channel 7 Data Register. This register contains the
result of the most recent conversion completed on channel 7.

Table 1116

STAT

RO

0x030

A/D Status Register. This register contains DONE and
OVERRUN flags for all of the A/D channels, as well as the
A/D interrupt flag.

Table 1117

[1]

Reset
value[1]

0

Reference

Reset value reflects the data stored in used bits only. It does not include reserved bits content.

Table 1112. Register overview: ADC1 (base address 0x400E 4000)
Name

Access Address
offset

Description

CR

R/W

0x000

A/D Control Register. The AD1CR register must be written to 0x0000 0000 Table 1113
select the operating mode before A/D conversion can occur.

GDR

R0

0x004

A/D Global Data Register. Contains the result of the most
recent A/D conversion.

-

-

-

0x008

Reserved.

-

INTEN

R/W

0x00C

A/D Interrupt Enable Register. This register contains enable 0x0000 0100 Table 1115
bits that allow the DONE flag of each A/D channel to be
included or excluded from contributing to the generation of
an A/D interrupt.

DR0

RO

0x010

A/D Channel 0 Data Register. This register contains the
result of the most recent conversion completed on channel 0

Table 1116

DR1

RO

0x014

A/D Channel 1 Data Register. This register contains the
result of the most recent conversion completed on channel
1.

-

Table 1116

DR2

RO

0x018

A/D Channel 2 Data Register. This register contains the
result of the most recent conversion completed on channel
2.

-

Table 1116

DR3

RO

0x01C

A/D Channel 3 Data Register. This register contains the
result of the most recent conversion completed on channel
3.

-

Table 1116

DR4

RO

0x020

A/D Channel 4 Data Register. This register contains the
result of the most recent conversion completed on channel
4.

-

Table 1116

DR5

RO

0x024

A/D Channel 5 Data Register. This register contains the
result of the most recent conversion completed on channel
5.

-

Table 1116

DR6

RO

0x028

A/D Channel 6 Data Register. This register contains the
result of the most recent conversion completed on channel
6.

-

Table 1116

DR7

RO

0x02C

A/D Channel 7 Data Register. This register contains the
result of the most recent conversion completed on channel
7.

-

Table 1116

STAT

RO

0x030

A/D Status Register. This register contains DONE and
OVERRUN flags for all of the A/D channels, as well as the
A/D interrupt flag.

0

Table 1117

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Chapter 47: LPC43xx/LPC43Sxx 10-bit ADC0/1

[1]

Reset value reflects the data stored in used bits only. It does not include reserved bits content.

47.6.1 A/D Control register
The A/D Control Register provides bits to select A/D channels to be converted, A/D timing,
A/D modes, and the A/D start trigger.
Table 1113. A/D Control register (CR - address 0x400E 3000 (ADC0) and 0x400E 4000 (ADC1)) bit description
Bit

Symbol

Value

Description

Reset
value

7:0

SEL

Selects which of the ADCn_[7:0] inputs are to be sampled and converted. Bit 0 0
selects ADCn_0, bit 1 selects pin ADCn_1,..., and bit 7 selects pin ADCn_7. In
software-controlled mode, only one of these bits should be 1. In hardware scan
mode, any value containing 1 to 8 ones is allowed. All zeroes is equivalent to
SEL = 0x01.

15:8

CLKDIV

The ADC clock is divided by the CLKDIV value plus one to produce the clock 0
for the A/D converter, which should be less than or equal to 4.5 MHz. Typically,
software should program the smallest value in this field that yields a clock of
4.5 MHz or slightly less, but in certain cases (such as a high-impedance analog
source) a slower clock may be desirable.

16

BURST

Controls Burst mode

0

0

Conversions are software controlled and require 11 clocks.

1

The AD converter does repeated conversions at the rate selected by the CLKS
field, scanning (if necessary) through the pins selected by 1s in the SEL field.
The first conversion after the start corresponds to the least-significant 1 in the
SEL field, then higher numbered 1 bits (pins) if applicable. Repeated
conversions can be terminated by clearing this bit, but the conversion that’s in
progress when this bit is cleared will be completed. The conversion result is
stored in the DR0 to DR7 registers, The GDR does not contain valid
conversion results in burst mode.
Important: START bits must be 000 when BURST = 1 or conversions will not
start.

19:17 CLKS

This field selects the number of clocks used for each conversion in Burst mode 000
and the number of bits of accuracy of the result in the LS bits of ADDR,
between 11 clocks (10 bits) and 4 clocks (3 bits).
0x0

20

-

21

PDN

23:22 -

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11 clocks / 10 bits

0x1

10 clocks / 9 bits

0x2

9 clocks / 8 bits

0x3

8 clocks / 7 bits

0x4

7 clocks / 6 bits

0x5

6 clocks / 5 bits

0x6

5 clocks / 4 bits

0x7

4 clocks / 3 bits

-

Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
Power mode

0

0

The A/D converter is in Power-down mode.

1

The A/D converter is operational.

-

Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
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Chapter 47: LPC43xx/LPC43Sxx 10-bit ADC0/1

Table 1113. A/D Control register (CR - address 0x400E 3000 (ADC0) and 0x400E 4000 (ADC1)) bit description
Bit

Symbol

Value

26:24 START

Controls the start of an A/D conversion when the BURST bit is 0.

0

No start (this value should be used when clearing PDN to 0).

0x1

Start now.

0x2

Start conversion when the edge selected by bit 27 occurs on CTOUT_15
(combined timer output 15, ADC start0).

0x3

Start conversion when the edge selected by bit 27 occurs on CTOUT_8
(combined timer output 8, ADC start1).

0x4

Start conversion when the edge selected by bit 27 occurs on ADCTRIG0 input
(ADC start3).

0x5

Start conversion when the edge selected by bit 27 occurs on ADCTRIG1 input
(ADC start4).

0x6

Start conversion when the edge selected by bit 27 occurs on Motocon PWM
output MCOA2 (ADC start5).
Reserved.

EDGE

31:28 -

Reset
value

0x0

0x7
27

Description

Controls rising or falling edge on the selected signal for the start of a
conversion. This bit is significant only when the START field contains 0x2
-0x6).

0

0

Rising edge.

1

Falling edge.

-

Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.

47.6.2 A/D Global Data register
The A/D Global Data Register contains the result of the most recent A/D conversion when
the ADC operates in software-controlled, non-burst mode (BURST bit set to zero and
START bits set to 0x1 in the CR register). This includes the data, DONE, and Overrun
flags, and the number of the A/D channel to which the data relates.
Remark: Use only the individual channel data registers DR0 to DR7 with burst mode or
with hardware triggering to read the conversion results.
Table 1114. A/D Global Data register (GDR - address 0x400E 3004 (ADC0) and 0x400E 4004
(ADC1)) bit description

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Bit

Symbol

Description

Reset
value

5:0

-

Reserved. These bits always read as zeroes.

0

15:6

V_VREF

When DONE is 1, this field contains a binary fraction representing
the voltage on the ADCn pin selected by the SEL field, divided by
the reference voltage on the VDDA pin. Zero in the field indicates
that the voltage on the ADCn input pin was less than, equal to, or
close to that on VSSA, while 0x3FF indicates that the voltage on
ADCn input pin was close to, equal to, or greater than that on
VDDA.

-

23:16 -

Reserved. These bits always read as zeroes.

0

26:24 CHN

These bits contain the channel from which the LS bits were
converted.

-

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Table 1114. A/D Global Data register (GDR - address 0x400E 3004 (ADC0) and 0x400E 4004
(ADC1)) bit description
Bit

Symbol

Description

Reset
value

29:27 -

Reserved. These bits always read as zeroes.

0

30

OVERRUN

This bit is 1 in burst mode if the results of one or more conversions 0
was (were) lost and overwritten before the conversion that
produced the result in the V_VREF bits.

31

DONE

This bit is set to 1 when an analog-to-digital conversion completes. 0
It is cleared when this register is read and when the AD0/1CR
register is written. If the AD0/1CR is written while a conversion is
still in progress, this bit is set and a new conversion is started.

47.6.3 A/D Interrupt Enable register
This register allows control over which A/D channels generate an interrupt when a
conversion is complete. For example, it may be desirable to use some A/D channels to
monitor sensors by continuously performing conversions on them. The most recent
results are read by the application program whenever they are needed. In this case, an
interrupt is not desirable at the end of each conversion for some A/D channels.
Table 1115. A/D Interrupt Enable register (INTEN - address 0x400E 300C (ADC0) and
0x400E 400C (ADC1)) bit description
Bit

Symbol

Description

7:0

ADINTEN

These bits allow control over which A/D channels generate
0x00
interrupts for conversion completion. When bit 0 is one, completion
of a conversion on A/D channel 0 will generate an interrupt, when bit
1 is one, completion of a conversion on A/D channel 1 will generate
an interrupt, etc.

8

ADGINTEN

When 1, enables the global DONE flag in ADDR to generate an
interrupt. When 0, only the individual A/D channels enabled by
ADINTEN 7:0 will generate interrupts.

1

Reserved. Always 0.

0

31:9 -

Reset
value

47.6.4 A/D Data Registers
The A/D Data Register hold the result when an A/D conversion is complete, and also
include the flags that indicate when a conversion has been completed and when a
conversion overrun has occurred.
Table 1116. A/D Data registers (DR - addresses 0x400E 3010 (DR0) to 0x400E 302C (DR7)
(ADC0); 0x400E 4010 (DR0) to 0x400E 402C (DR7) (ADC1)) bit description

UM10503

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Bit

Symbol

Description

Reset
value

5:0

-

Reserved. Always 0.

0

15:6

V_VREF

When DONE is 1, this field contains a binary fraction representing the voltage on the ADCn input pin selected in Table 1113, divided by the
voltage on the VDDA pin. Zero in the field indicates that the voltage on
the ADCn input pin was less than, equal to, or close to that on VDDA,
while 0x3FF indicates that the voltage on ADCn input pin was close to,
equal to, or greater than that on VDDA.

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Chapter 47: LPC43xx/LPC43Sxx 10-bit ADC0/1

Table 1116. A/D Data registers (DR - addresses 0x400E 3010 (DR0) to 0x400E 302C (DR7)
(ADC0); 0x400E 4010 (DR0) to 0x400E 402C (DR7) (ADC1)) bit description
Bit

Symbol

29:16 -

Description

Reset
value

Reserved. Always 0.

0

30

OVERRUN This bit is 1 in burst mode if the results of one or more conversions
was (were) lost and overwritten before the conversion that produced
the result in the V_VREF bits in this register.This bit is cleared by
reading this register.

0

31

DONE

0

This bit is set to 1 when an A/D conversion completes. It is cleared
when this register is read.

47.6.5 A/D Status register
The A/D Status register allows checking the status of all A/D channels simultaneously.
The DONE and OVERRUN flags appearing in the AD0/1DRn register for each A/D
channel n are mirrored in ADSTAT. The interrupt flag (the logical OR of all DONE flags) is
also found in ADSTAT.
Table 1117. A/D Status register (STAT - address 0x400E 3030 (ADC0) and 0x400E 4030
(ADC1)) bit description
Bit

Symbol

Description

Reset
value

7:0

DONE

These bits mirror the DONE status flags that appear in the result
register for each A/D channel.

0

15:8

OVERUN

These bits mirror the OVERRRUN status flags that appear in the
result register for each A/D channel. Reading ADSTAT allows
checking the status of all A/D channels simultaneously.

0

16

ADINT

This bit is the A/D interrupt flag. It is one when any of the individual
A/D channel Done flags is asserted and enabled to contribute to the
A/D interrupt via the ADINTEN register.

0

Reserved. Always 0.

0

31:17 -

47.7 Operation
47.7.1 Hardware-triggered conversion
If the BURST bit in the ADCR is 0 and the START field contains any value between 0x2
and 0x6, the A/D converter will start a conversion when a transition occurs on a selected
pin or Timer signal. The choices include the two ADCTRIG external input pins, an output
from the motocon PWM, and two combined timer outputs (see Section 47.6.1).
The result of a hard-ware triggered conversion is stored in the individual channel data
registers DR0 to DR7. The global data register does not yield valid readings of a
hardware-triggered conversion.

47.7.2 Interrupts
An interrupt is requested to the NVIC when the ADINT bit in the ADSTAT register is 1. The
ADINT bit is one when any of the DONE bits of the A/D channels which are enabled for
interrupts (via the ADINTEN register) are one. Software can use the Interrupt Enable bit in
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Chapter 47: LPC43xx/LPC43Sxx 10-bit ADC0/1

the NVIC that corresponds to the ADC to control whether this results in an interrupt. The
result register of the A/D channel which is generating an interrupt must be read in order to
clear the corresponding DONE flag.

47.7.3 DMA control
A DMA transfer request is generated from the ADC interrupt request line. To generate a
DMA transfer the same conditions must be met as the conditions for generating an
interrupt. A pending DMA request is cleared after the DMA has read from the requesting
channel’s A/D data register (DR[7:0]). Reading from the global data register (GDR) does
not clear any pending DMA requests.
For DMA transfers, only burst requests are supported. The burst size can be set to one of
the predefined burst sizes in the DMA channel control register (see Table 349). If the
number of ADC channels is not equal to one of the predefined DMA-supported burst sizes
(applicable DMA burst sizes are 1, 4, 8), set the burst size to one.
The DMA transfer size determines when a DMA interrupt is generated. The transfer size
can be set to the number of ADC channels being converted (see Section 21.6.19).
Non-contiguous channels can be transferred by the DMA using the scatter/gather linked
lists (see Section 21.8.5).

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Chapter 48: 12-bit ADC (ADCHS)
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User manual

48.1 How to read this chapter
The 12-bit ADC is only available on parts LPC4370 and LPC43S70.

48.2 Features
•
•
•
•
•
•
•
•
•
•

12-bit high-speed analog to digital converter.
Input multiplexing among 6 pins.
Descriptor based conversion sequence for single or multiple inputs.
Integrated 14-bit timer
Optional automatic high/low threshold detection.
Power-down mode.
Measurement range 0 to 1.2 V.
12-bit conversion rate of 80 MSamples/s.
Optional conversion on transition on input pin or various internal signals.
16-word output FIFO with DMA support.

48.3 Basic configuration
The ADCHS is configured as follows:

• See Table 1118 for clocking and power control.
• The ADCHS is reset by the ADCHS_RST (reset # 60).
• The ADCHS interrupt is connected to interrupt slot # 45 in the Cortex-M4 NVIC and to
slots #30 in the Cortex-M0 subsystem core and in the Cortex-M0 core.

• For connecting to the GPDMA, use the DMAMUX register (Table 100) in the CREG
block and enable the GPDMA channel in the DMA Channel Configuration registers
Section 21.6.20.

• The ADCHS conversion triggers are connected through the GIMA (see Table 234) to
the timers or SCT outputs.
Table 1118. ADCHS clocking and power control

UM10503

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Base clock

Branch clock

Operating
frequency

Notes

AHB clock

BASE_M4_CLK

CLK_M4_ADCHS

up to
204 MHz.

For register interface.

ADCHS
clock

BASE_ADCHS_CLK CLK_ADCHS

up to 80 MHz

For conversion rate.

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Chapter 48: 12-bit ADC (ADCHS)

48.4 Pin description
Table 1119. ADCHS pin description
Pin

Type

Description

ADCHS_0

Analog input

12-bit high-speed ADC input channel 0.

ADCHS_1

Analog input

12-bit high-speed ADC input channel 1.

ADCHS_2

Analog input

12-bit high-speed ADC input channel 2.

ADCHS_3

Analog input

12-bit high-speed ADC input channel 3.

ADCHS_4

Analog input

12-bit high-speed ADC input channel 4.

ADCHS_5

Analog input

12-bit high-speed ADC input channel 5.

ADCHS_NEG

-

12-bit high-speed ADC reference voltage output or negative
differential input.

VSSA

-

Ground.

48.5 General description
Basic clocking for the A/D converter is provided by BASE_ADCHS_CLK. This clock
frequency (fADC) can be up to 80 MHz. The conversion takes one clock cycle. Data is
available, after the conversion latency, in the output FIFO and channel output registers.
The FIFO and registers are clocked by the AHB clock. The FIFO can be read by general
purpose DMA or software.
The conversion sequence is defined by two descriptor tables (see Table 1136 and
Table 1137). The tables can be loaded by general purpose DMA or software.
Remark: When sampling long sequences that do not fit in the FIFO, the AHB clock should
be chosen sufficient high to be able to transfer the output samples across the AHB before
the FIFO overflows.

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1.2V

12k

8k5
DCINNEG

ADCHS__NEG
ADCHS_0
ADCHS_1
ADCHS_2
ADCHS_3
ADCHS_4
ADCHS_5

vin_neg

6 :1
input
mux

12-bit
ADC

DCINPOS

reset

12

vin_pos

3

16word
FIFO

DMA
AHB

ADC controller

Interrupt
Trigger

descriptor
table1

descriptor
table2

shadow
descriptor tbl1

shadow
descriptor tbl2

14-bit
descriptor
timer

Trigger
select
ADC_clk

Fig 187. ADCHS block diagram

48.6 Register description
Table 1120.Register overview: 12-bit ADC (base address 0x400F 0000)
Name

Access Address
offset

Description

Reset value

Reference

FLUSH

WO

0x0000

DMA_REQ

R/W

0x0004

Flushes FIFO

0x00000000

Table 1121

Set or clear DMA write request

0x00000001

Table 1122

FIFO_STS

RO

0x0008

Indicates FIFO fill level status

0x00000000

Table 1123

FIFO_CFG

R/W

0x000C

Configures FIFO fill level that triggers
interrupt and packing 1 or 2 samples per
word.

0x00000010

Table 1124

TRIGGER

WO

0x0010

Enable software trigger to start descriptor 0x00000000
processing

Table 1125

DSCR_STS

R/W

0x0014

Indicates active descriptor table and
descriptor entry

0x00000000

Table 1126

POWER_DOWN

R/W

0x0018

Set or clear power down mode

0x00000001

Table 1127

CONFIG

R/W

0x001C

Configures external trigger mode, store
0x00002400
channel ID in FIFO and walk-up recovery
time from power down.

Table 1128

THR_A

R/W

0x0020

Configures window comparator A levels.

0x0FFF0000

Table 1129

THR _B

R/W

0x0024

Configures window comparator B levels.

0x0FFF0000

Table 1130

LAST_SAMPLE0 to
LAST_SAMPLE5

RO

0x0028 to
0x003C

Contains last converted sample of input
M [M=0..5) and result of window
comparator.

0x00000000

Table 1131

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Table 1120.Register overview: 12-bit ADC (base address 0x400F 0000)
Name

Access Address
offset

Description

Reset value

Reference

-

R/W

0x0100

Reserved

-

ADC_SPEED

R/W

0x0104

ADC speed control

0x00000000

Table 1132

POWER_CONTROL

R/W

0x0108

Configures ADC power vs. speed, DC-in
biasing, output format and power gating.

0x00000000

Table 1134

FIFO_OUTPUT0 to
FIFO_OUTPUT15

RO

0x0200 to
0x023C

FIFO output mapped to 16 consecutive
0x00008000
address locations. An output contains the
value and input channel ID of one or two
converted samples

Table 1135

DESCRIPTOR0_0 to
DESCRIPTOR0_7

R/W

0x0300 to
0x031C

Table 0 descriptor n, n= 0 to 7

0x000090E0

Table 1136

DESCRIPTOR1_0 to
DESCRIPTOR1_7

R/W

0x0320 to
0x033C

Table 1 descriptors n, n=0 to 7

0x000090E0

Table 1137

CLR_EN0

WO

0x0F00

Interrupt 0 clear mask

0x00000000

Table 1138

SET_EN0

WO

0x0F04

Interrupt 0 set mask

0x00000000

Table 1139

MASK0

RO

0x0F08

Interrupt 0 mask

0x00000000

Table 1140

STATUS0

RO

0x0F0C

Interrupt 0 status. Interrupt 0 contains
0x00000000
FIFO fill level, descriptor status and ADC
range under/overflow

Table 1141

CLR_STAT0

WO

0x0F10

Interrupt 0 clear status

0x00000000

Table 1142

SET_STAT0

WO

0x0F14

Interrupt 0 set status

0x00000000

Table 1143

CLR_EN1

WO

0x0F20

Interrupt 1 mask clear enable.

0x00000000

Table 1144

SET_EN1

WO

0x0F24

Interrupt 1 mask set enable

0x00000000

Table 1145

MASK1

RO

0x0F28

Interrupt 1 mask

0x00000000

Table 1146

STATUS1

RO

0x0F2C

Interrupt 1 status. Interrupt 1 contains
window comparator results and register
last LAST_SAMPLE[M] overrun.

0x00000000

Table 1147

CLR_STAT1

WO

0x0F30

Interrupt 1 clear status

0x00000000

Table 1148

SET_STAT1

WO

0x0F34

Interrupt 1 set status

0x00000000

Table 1149

48.6.1 FIFO flush register
This register flushes the FIFO.
Remark: After issuing a FIFO flush command it takes time to update the FIFO fill level
status register. To read the correct FIFO fill level at least one CPU cycle should be
inserted between a flush command and a FIFO fill level read.
Table 1121.FIFO flush register (FLUSH, address 0x400F 0000) bit description
Bit

Symbol

Description

Reset
value

0

FIFO_FLUSH

1= FIFO is cleared

0x0

31:1

-

Reserved.

-

48.6.2 DMA request register
This register requests a DMA write to load a descriptor table from memory.
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Table 1122.DMA request register (DMA_REQ, address 0x400F 0004) bit description
Bit

Symbol

Description

Reset
value

0

DMA_REQ_WR

1 = Dma_req_wr is set (initially used to fill second table),

0x1

0 = Dma_req_wr is cleared
31:1

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48.6.3 FIFO fill level register
This register reflects the FIFO fill level. If the LEVEL bit field returns 0, either the FIFO is
empty or the FIFO contains 16 words. To determine the true FIFO fill level in this case,
read the FIFO_EMPTY bit in the STATUS0 register (Table 1141):

• If FIFO_EMPTY = 1, then all data in the FIFO have been read out and the FIFO is
empty.

• If FIFO_EMPTY = 0, then the FIFO contains 16 words.
Remark: After issuing a FIFO flush command it takes time to update the FIFO fill level
status register. To read the correct FIFO fill level at least one CPU cycle should be
inserted between a flush command and a FIFO fill level read.
Table 1123.FIFO fill level register (FIFO_STS, address 0x400F 0008) bit description
Bit

Symbol

Description

Reset
value

3:0

LEVEL

0 = FIFO is empty or FIFO level of 16 words has been
reached.

0x00

31:4

-

1...15 = FIFO is partially full and contains 1 to 15 words.
Reserved.

-

48.6.4 FIFO configuration register
This register configures whether 1 or 2 samples are packed in one FIFO word. The
packed data format.

bit

b31

b30..b2 8

PACKED_READ = 0

“00 ..00 ”

1 sample/word
PACKED_READ = 1

“0”

“00 0” o r
chann el ID

sample 2n +1

b15

b 14..b12

b 11..b0

“0”

“000” or
cha nnel ID

samp le

“0”

“000” or
cha nnel ID

samp le 2n







2 sa mpl es/word

b27..b1 6

an empt y FIF O ret urns 0x8000

Fig 188. FIFO packed data format

This register also defines at what FIFO fill level the interrupt flag FIFO_FULL is asserted.
Remark: The channel ID is optional. This is configured in register CONFIG.
Table 1124.FIFO configuration register (FIFO_CFG, address 0x400F 000C) bit description
Bit

Symbol

Description

Reset
value

0

PACKED_READ

0 = one sample is packed in one 32-bit read cycle

0x0

1 = two samples are packed in one 32-bit read cycle

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FIFO_LEVEL

When the FIFO contains more or equal than
FIFO_LEVEL samples, the interrupt flag FIFO_FULL
interrupt will be set and DMA_Read_Req will be raised.
The maximum threshold that can be programmed is 15
words. Note that the FIFO can contain up to 16 words.

0x8

31:5

-

Reserved

-

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48.6.5 Trigger register
A write to this register starts the descriptor timer and descriptor table processing. The register is always read as 0x0.
Table 1125.Trigger register (TRIGGER, address 0x400F 0010) bit description
Bit

Symbol

Description

Reset value

0

SW_TRIGGER

Auto cleared

0x0

31:1

-

Reserved

-

48.6.6 Descriptor status register
This register contains the active descriptor table and active descriptor entry values.
This register can also be used to set active descriptor table and active descriptor entry
values. The new values will be updated immediately.
Remark: This register should only be updated when descriptors are not running (halted).
Table 1126.Descriptor status register (DSCR_STS, address 0x400F 0014) bit description
Bit

Symbol

0

ACT_TABLE

Description

Reset
value

0 = table 0 is active

0x0

1 = table 1 is active.
3:1

ACT_DESCRIPTOR ID of the descriptor that is active.

0x0

31:4

-

-

Reserved

48.6.7 Power-down register
This register enables ADC power down mode. This register will also be set, or cleared, by
the descriptor table processor.
Table 1127.Power-down register (POWER_DOWN, address 0x400F 0018) bit description
Bit

Symbol

Description

Reset
value

0

PD_CTRL

0 = disable power down mode. Register holds value until set by 0x1
writing 1 to this bit or by descriptor processor when descriptor
field POWER_DOWN is set.
1 = enable power down mode. Register holds value until
cleared by writing 0 to this bit or by descriptor processor when
waking up RECOVERY_TIME before a conversion.

31:1

-

Reserved

-

48.6.8 Configuration register
This register configures the trigger source. For an external trigger it selects the active
edge or level and whether the external signal should be synchronized. Synchronization is
needed for short duration trigger inputs. Synchronization introduces a latency of 2-3 ADC
clock cycles. When synchronization is set here then it is recommended not to set SYNC in
the trigger selection block (Section 48.7.6).
When CHANNEL_ID_EN is set the channel ID is pre-fixed to the FIFO output data.

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The ADC wake-up time from power down is configured by RECOVERY_TIME. This value
should be set to 0x90. This gives a recovery time of 0x90/fADC; for fADC=80 MHz this
gives 1.80 µs.
Table 1128.Configuration register (CONFIG, address 0x400F 001C) bit description
Bit

Symbol

Description

Reset
value

1:0

TRIGGER__MASK

00 = triggers off

0x0

01 = software trigger only
10 = external trigger only
11 = both triggers allowed
3:2

TRIGGER_MODE

00 = rising external trigger

0x0

01 = falling external trigger
10 = low external trigger
11 = high external trigger
4

TRIGGER_SYNC

0 = do not synchronize external trigger input

0x0

1 = synchronize external trigger input
5

CHANNEL_ID_EN

0 = do not add channel ID to FIFO output data

0x0

1 = add channel ID to FIFO output data
13:6

RECOVERY_TIME

ADC recovery time from power down

0x90

31:14

-

Reserved

-

48.6.9 Threshold A/B register
This register sets the lower and upper threshold levels for automatic threshold comparison
for input channels linked to threshold comparator A (or B). Linking a channel to a
threshold comparator is controlled by descriptor field TRESHOLD_SEL (see
Section 48.6.14).
A conversion result less than the THR_LOW_A (or THR_LOW_B) value on the linked
channel will cause the THCMP_RANGE status bits for that channel to be set to 0b01. This
result will also generate an interrupt 1 request if enabled to do so via the SET_EN1 bits
associated with the comparator THCMP_BRANGE bits in the SET_EN1 register.
A conversion result greater than the THR_HIGH_A (or THR_HIGH_B) value on the linked
channel will cause the THCMP_RANGE status bits for that channel to be set to 0b10. This
result will also generate an interrupt 1 request if enabled to do so via the SET_EN1 bits
associated with the comparator THCMP_ARANGE bits in the SET_EN1 register.
If, for two successive conversion results on a given channel, one result is below a
threshold and the other is equal-to or above this threshold, then a threshold crossing has
occurred. In this case the THCMP_CROSS (see Section 48.6.10) status bits will indicate
that a threshold crossing has occurred. A threshold crossing event will also generate an
interrupt 1 request if enabled to do so via the SET_EN1 bits associated with each channel
in the SET_EN1 register.
Remark: The levels assume offset binary coded data; TWOS is set to 0 (see
Section 48.6.12).

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Table 1129.Threshold A register (THR_A, address 0x400F 0020) bit description
Bit

Symbol

Description

Reset
value

11:0

THR_LOW_A

Low Compare Threshold Register A:

0x000

Contains the lower threshold level for automatic threshold
comparison for any channels linked to threshold pair A.
27:16

THR_HIGH_A

0xFFF

High Compare Threshold Register A:
Contains the upper threshold level for automatic threshold
comparison for any channels linked to threshold pair A.

31:28

-

Reserved.

-

Table 1130.Threshold B register (THR_B, address 0x400F 0024) bit description
Bit

Symbol

Description

Reset
value

11:0

THR_LOW_B

Low Compare Threshold Register B:

0x000

Contains the lower threshold level for automatic threshold
comparison for any channels linked to threshold pair A.
27:16

THR_HIGH_B

High Compare Threshold Register B:

0xFFF

Contains the upper threshold level for automatic threshold
comparison for any channels linked to threshold pair A.
31:28

-

Reserved.

-

48.6.10 Last sample registers
When DONE is set these registers contain the last converted sample of channel m
(m=0,1..5). They also contain various status signals.
The comparator status fields THCMP_RANGE and THCMP_CROSS are 0b00 if the
channel is not linked to a comparator (when TRESHOLD_SEL is 0b00 or 0b11).
Table 1131.Last sample registers (LAST_SAMPLE[0:5], address 0x400F 0028 (LAST_SAMPLE0) to 0x400F 003C
(LAST_SAMPLE(5)) bit description
Bit

Symbol

0

DONE

Description

Reset
value

This bit is set to 1 when an A/D conversion on this channel completes.

0x0

This bit is cleared whenever this register is read.
1

OVERRUN

This bit will be set to a 1 if a new conversion on this channel completes and
overwrites the previous contents of the RESULT field before it has been read - i.e.
while the DONE bit is set.

0x0

This bit is cleared, along with the DONE bit, whenever this register is read.
This bit (in any of the registers) will cause an overrun interrupt request to be asserted
if the overrun interrupt is enabled.
3:2

THCMP_RANGE

Threshold Range Comparison result

0x0

00: In Range
01: Below Range
10: Above Range
11: Reserved

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Table 1131.Last sample registers (LAST_SAMPLE[0:5], address 0x400F 0028 (LAST_SAMPLE0) to 0x400F 003C
(LAST_SAMPLE(5)) bit description
Bit

Symbol

Description

Reset
value

5:4

THCMP_CROSS

Threshold Crossing Comparison result

0x0

00: No Threshold Crossing detected
01: Downward Threshold Crossing detected
10: Upward Threshold Crossing detected
11: Reserved
17:6

SAMPLE

12-Bit value of last converted sample for this channel

0x0

20:17 -

Reserved

0x0

31:21 -

Reserved

0x0

48.6.11 Speed register
The Speed register settings depend on the current settings CRS. For CRS = 0x3, all
DGEC should be set to -1 (0xF), for CRS = 0x4 all DGEC should be set to -2 (0xE). For all
other cases DGEC can be kept equal to 0. See also Table 1133.
Table 1132.Speed register (ADC_SPEED, address 0x400F 0104) bit description
Bit

Symbol

Description

Reset value

3:0

DGEC0

Speed0

0x0

7:4

DGEC1

Speed1

0x0

11:8

DGEC2

Speed2

0x0

15:12

DGEC3

Speed3

0x0

19:16

DGEC4

Speed4

0x0

23:20

DGEC5

Speed5

0x0

31:24

-

Reserved

-

48.6.12 Power control register
Power consumption and maximum speed of the ADC can be programmed by means of
the current settings signal CRS[3:0] as shown in Table 1133. Speed settings DCEC should
follow the CRS settings.
Table 1133.Power and speed programming
CRS[3:0]

Power [mW]

fADC [MS/s]

DGECi

0x0

20

20

0x0

0x1

30

30

0x0

0x2

45

50

0x0

0x3

60

65

0xF

0x4

75

80

0xE

0x5-0xF

do not use these
settings

n.a.

0x0

The input signals of the ADC can be either AC-coupled by means of two capacitors or
connected directly to the inputs (DC-coupled). For AC coupling, the DC biasing is
generated internally by setting DCINNEG= 1 and DCINPOS= 1.

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The input channels are multiplexed to ADC input vin_pos. All six input channels share the
same vin_neg, which is generated internally when DCINNEG is set to 1 and output at pin
ADCHS_NEG. The nominal vin_neg level is 0.50 V. Hence vin_pos should be in the range
from 0.50 ± 0.4 V.
It is possible to deselect the internal vin_neg and supply vin_neg externally at pin
ADCHS_NEG by setting DCINNEG= 0.
The output format can be set to offset binary by setting TWOS to '0' (minimum code
0x000, maximum code 0xFFF) or to two's complement by setting TWOS to '1' (minimum
code 0x800, maximum code 0x7FF).
The ADC can be full switched off by setting both POWER_SWITCH and BGAP_SWITCH
to 0. In this case automatic wake up is not available (see Table 1136).
Table 1134.Power control register (POWER_CONTROL, address 0x400F 0108) bit description
Bit

Symbol

Description

Reset
value

3:0

CRS

current setting for power versus speed programming

0x0

9 :4

DCINNEG

AC-DC coupling selection

0x0

0 = No dc bias
1 = DC bias on vin_neg side
15 : 10

DCINPOS

AC-DC coupling selection

0x0

0 = No dc bias
1 = DC bias on vin_pos side
16

TWOS

Output data format selection

0x0

0 = offset binary
1 = two’s complement
17

POWER_SWITCH

0 = ADC is powered down

18

BGAP_SWITCH

0 = ADC band gap reference is powered down

0x0

1 = ADC is active
0x0

1 = ADC band gap reference is active
31:19

-

Reserved

-

48.6.13 FIFO output register
These registers access the output FIFO that contains the 12-bit ADC conversion results.
All registers remap to the FIFO output. It is remapped 16 times to allow for DMA access
reading at 16 consecutive address locations.
SAMPLE is the conversion result value. CHAN_ID is the value of the sampled input (n:
input_n). When CHANNEL_ID_EN (see Table 1128) is set then CHAN_ID is always zero.
When PACKED_READ is set then two samples are packed into one 32-bit word. See
Table 1124 for the packed data format.
When an empty FIFO is read the output will be 0x8000 (or 0x80008000 for
PACKED_READ data).

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Table 1135.FIFO output register (FIFO_OUTPUT[0:15], address 0x400F 0200
(FIFO_OUTPUT0) to 0x400F 0203C (FIFO_OUTPUT15)) bit description
Bit

Symbol

Description

Reset
value

11:0

SAMPLE

Value of first converted sample

0x0

14:12

CHAN_ID

Channel number of first converted sample:

0x0

000: channel _0 or CHANNEL_ID_EN =0
001: channel _1
010: channel _2
011: channel _3
100: channel _4
101: channel _5
110: reserved
111: recovery_ error
15

EMPTY

0: FIFO not empty

0x1

1: FIFO empty
27:16

SAMPLE2

Value of second converted sample.

0x0

This field is only valid if PACKED_READ is set else it is 0x0
30:28

CHAN_ID2

Channel number of second converted sample

0x0

This field is only valid if CHANNEL_ID_EN and
PACKED_READ are set else it is 0x0
31

EMPTY2

0: FIFO not empty

0x0

1: FIFO empty and PACKED_READ is set

48.6.14 Descriptor table 0 register
These registers contain the descriptor entries of table 0. Register 0x400F0300+4n
contains descriptor n (n=0,1...7). The analog to digital conversion time and sequence are
controlled by descriptor table entries and the 14-bit descriptor timer. The descriptor timer
operates at fADC, it wraps around to 0x0000 after reaching its maximum value 0x3FFF.
The timer can be reset by field RESET_TIMER. HALT halts the descriptor processing but
the timer continues running. Processing restarts at a new input trigger.
A sample at input channel CHANNEL_NR is converted when the descriptor timer equals
field MATCH_VALUE.
An input channel can be linked to window comparator A or B by field TRESHOLD_SEL.
When INTERRUPT is set interrupt 0 can be raised when the conversion results is
available in the output FIFO or LAST_SAMPLE register and the mask bit associated with
DSCR_DONE is set by register SET_EN0.
When POWER_DOWN is set the ADC is powered down after the conversion has finished.
The ADC is automatically woken up before the next conversion. Wake up time is set in
RECOVERY_TIME (see Table 1128), this is default 144 fADC cycles.
Remark: If the first descriptor is required earlier than RECOVERY_TIME, then automatic
wake up cannot be used. In that case the previous descriptor should not set
POWER_DOWN.

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Chapter 48: 12-bit ADC (ADCHS)

Remark: When the ADC is switched off (POWER_SWITCH and BGAP_SWITCH are 0)
then automatic wake up is not available

The table is processed as set by field BRANCH to process: descriptor by descriptor, or
branch by the first descriptor in the current table 0 or the new table 1 (see Table 1137).
Table processing is started by a software trigger or external trigger input (see Table 1125
and Table 1128). The active table and active table descriptor are indicated by
STATUS_REG1 (see Table 1126). By chaining table 0 and table 1 and updating the not
active table, infinite long conversion sequences can be created.
The ADC controller uses a shadow table that is mapped to DESCRIPTOR0/1 registers
and another table that is used to control the ADC. The complete shadow table is copied
when UPDATE_TABLE of any descriptor entry is set to 1. When writing new table entries
to DESCRIPTOR0 these registers read do not reflect the table used by the ADC
processing until UPDATE_TABLE has been set 1 again.

Table 1136.Descriptor table 0 registers (DESCRIPTOR0_[0:7], address 0x400F 0300
(DESCRIPTOR0_0) to 0x400F 031C (DESCRIPTOR0_7)) bit description
Bit

Symbol

Description

Reset
value

2:0

CHANNEL_NR

0: convert input 0

0x0

1: convert input 1
2: convert input 2
3: convert input 3
4: convert input 4
5: convert input 5
6,7: reserved
3

HALT

0: After this descriptor continue with the next descriptor.

0x0

1: halt after this descriptor is processed. Restart at a new
trigger.
4

INTERRUPT

1: Raise interrupt when ADC result is available

0x0

5

POWER_DOWN

1: Power down after this conversion.

0x1

7:6

BRANCH

00: Continue with next descriptor (wraps around after
top).

0x3

01: Branch to the first descriptor in this table.
10: Swap tables and branch to the first descriptor of the
new table.
11: reserved (do not store sample). Continue with next
descriptor (wraps around after top).
21:8

MATCH_VALUE

Evaluate this descriptor when descriptor timer value is
equal to match value.

0x90

23:22 THRESHOLD_SEL Indicates which threshold comparison level register set is 0x0
to be used:
00: no comparison,
01: THR_A.
10: THR_B.
11: Reserved

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Table 1136.Descriptor table 0 registers (DESCRIPTOR0_[0:7], address 0x400F 0300
(DESCRIPTOR0_0) to 0x400F 031C (DESCRIPTOR0_7)) bit description
Bit

Symbol

Description

24

RESET_TIMER

Reset
value

1: reset descriptor timer.

0x0

30:25 -

Reserved

0x0

31

1: Update table with all 8 descriptors of this table.
0x0
Descriptors of this table that are written without this bit set
are not updated until any descriptor of this table is written
with this bit set.

UPDATE_TABLE

This field is write only. A read returns 0x0.

48.6.15 Descriptor table 1 register
These registers contain the descriptor entries of table 1. Register 0x400F0320+4n
contains descriptor n (n=0,1..7).
See Table 1136 (Descriptor Table 0 Register) for details on descriptor tables.
Table 1137.Descriptor table 1 registers (DESCRIPTOR1_[0:7], address 0x400F 0320
(DESCRIPTOR1_0) to 0x400F 033C (DESCRIPTOR1_7)) bit description
Bit

Symbol

Description

Reset
value

2:0

CHANNEL_NR

0: convert input 0

0x0

1: convert input 1
2: convert input 2
3: convert input 3
4: convert input 4
5: convert input 5
6,7: reserved
3

HALT

0: After this descriptor continue with the next descriptor.

0x0

1: halt after this descriptor is processed. Restart at a new
trigger.
4

INTERRUPT

1: Raise interrupt when ADC result is available

0x0

5

POWER_DOWN

1: Power down after this conversion.

0x1

7:6

BRANCH

00: Continue with next descriptor (wraps around after
top).

0x3

01: Branch to the first descriptor in this table.
10: Swap tables and branch to the first descriptor of the
new table.
11: reserved (do not store sample). Continue with next
descriptor (wraps around after top).
21:8

MATCH_VALUE

Evaluate this descriptor when descriptor timer value is
equal to match value.

0x90

23:22 THRESHOLD_SEL Indicates which threshold comparison level register set is 0x0
to be used:
00: no comparison,
01: THR_A.
10: THR_B.
11: Reserved
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Table 1137.Descriptor table 1 registers (DESCRIPTOR1_[0:7], address 0x400F 0320
(DESCRIPTOR1_0) to 0x400F 033C (DESCRIPTOR1_7)) bit description
Bit

Symbol

Description

24

RESET_TIMER

Reset
value

1: reset descriptor timer.

0x0

30:25 -

Reserved

0x0

31

1: Update table with all 8 descriptors of this table.
0x0
Descriptors of this table that are written without this bit set
are not updated until any descriptor of this table is written
with this bit set.

UPDATE_TABLE

This field is write only. A read returns 0x0.

48.6.16 Interrupt 0 clear mask register
This register clears the interrupt 0 bit mask fields.
Table 1138.Interrupt 0 clear mask register (CLR_EN0, address 0x400F 0F00) bit description
Bit

Symbol

Description

Reset
value

6:0

CEN0

Interrupt clear enable

0x00

31:7

-

Reserved

-

48.6.17 Interrupt 0 set mask register
This register sets the interrupt 0 bit mask fields.
Table 1139.Interrupt 0 set mask register (SET_EN0, address 0x400F 0F04) bit description
Bit

Symbol

Description

Reset
value

6:0

SEN0

Interrupt set enable

0x00

31:7

-

Reserved

-

48.6.18 Interrupt 0 enable register
This register contains the interrupt 0 bit mask fields.
Table 1140.Interrupt 0 enable register (MASK0, address 0x400F 0F08) bit description
Bit

Symbol

Description

Reset value

6:0

M0

Interrupt enable

0x00

31:7

-

Reserved

-

48.6.19 Interrupt 0 status register
This register contains the interrupt 0 status bit fields.

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Chapter 48: 12-bit ADC (ADCHS)

Table 1141.Interrupt 0 status register (STATUS0, address 0x400F 0F0C) bit description
Bit

Symbol

Description

Reset
value

0

FIFO_LEVEL_TRIG

0: number of samples in FIFO less than or equal to
FIFO_LEVEL.

0x0

1: number of samples in FIFO is more than
FIFO_LEVEL.
1

FIFO_EMPTY

0: FIFO is not empty.

0x1

2

FIFO_OVERFLOW

FIFO was full; conversion sample is not stored and
lost.

3

DSCR_DONE

The descriptor INTERRUPT field was enabled and its 0x0
sample is converted.

4

DSCR_ERROR

The ADC was not fully woken up when a sample was
converted and the conversion results is unreliable

0x0

5

ADC_OVF

Converted sample value was over range of the 12 bit
output code.

0x0

6

ADC_UNF

Converted sample value was under range of the 12 bit 0x0
output code.

31:7

-

Reserved

1: FIFO is empty.
0x0

-

48.6.20 Interrupt 0 clear status register
This register clears the interrupt 0 status bit fields.
Table 1142.Interrupt 0 clear status register (CLR_STAT0, address 0x400F 0F10) bit
description
Bit

Symbol

Description

Reset value

6:0

CSTAT0

Interrupt clear status

0x00

31:7

-

Reserved

-

48.6.21 Interrupt 0 set status register
This register sets the interrupt 0 status bit fields.
Table 1143.Interrupt 0 set status register (SET_STAT0, address 0x400F 0F14) ) bit description
Bit

Symbol

Description

Reset value

6:0

SSTAT0

Interrupt set status

0x00

31:7

-

Reserved

-

48.6.22 Interrupt 1 clear mask register
This register clears the interrupt 1 bit mask fields
Table 1144.Interrupt 1 clear mask (CLR_EN1, address 0x400F 0F20) bit description
Bit

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Symbol

Description

Reset value

29:0

CEN1

Interrupt clear enable

0x00000000

31:30

-

Reserved

-

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48.6.23 Interrupt 1 set mask register
This register sets the interrupt 1 bit mask fields.
Table 1145.Interrupt 1 set mask register (SET_EN1, address 0x400F 0F24) bit description
Bit

Symbol

Description

Reset value

29:0

SEN1

Interrupt set enable

0x00000000

31:30

-

Reserved

-

48.6.24 Interrupt 1 mask register
This register contains the interrupt 1 bit mask fields.
Table 1146.Interrupt 1 mask register (MASK1, address 0x400F 0F28) bit description
Bit

Symbol

Description

Reset value

29:0

M1

Interrupt enable

0x00000000

31:30

-

Reserved

-

48.6.25 Interrupt 1 status register
This register contains the interrupt 1 status bit fields. The bit fields are grouped per input
channel; bits 5m, 5m+1..5m+4 contain interrupt status information for channel m
(m=0,1..5).
Table 1147.Interrupt 1 status register (STATUS1, address 0x400F 0F2C) bit description

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Bit

Symbol

Description

Reset
value

0

THCMP_BRANGE0

Input channel 0 result below range

-

1

THCMP_ARANGE0

Input channel 0 result above range

-

2

THCMP_DCROSS0

Input channel 0 result downward threshold
crossing detected

-

3

THCMP_UCROSS0

Input channel 0 result upward threshold crossing detected

4

OVERRUN_0

A new conversion on channel m completed and
has overwritten the previous contents of register
LAST_SAMPLE [0] before it has been read

5

THCMP_BRANGE1

Input channel 1 result below range

6

THCMP_ARANGE1

Input channel 1 result above range

7

THCMP_DCROSS1

Input channel 1 result downward threshold
crossing detected

8

THCMP_UCROSS1

Input channel 1 result upward threshold crossing
detected

9

OVERRUN_1

A new conversion on channel m completed and
has overwritten the previous contents of register
LAST_SAMPLE [1] before it has been read

10

THCMP_BRANGE2

Input channel 2 result below range

11

THCMP_ARANGE2

Input channel 2 result above range

12

THCMP_DCROSS2

Input channel 2 result downward threshold
crossing detected

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Table 1147.Interrupt 1 status register (STATUS1, address 0x400F 0F2C) bit description
Bit

Symbol

Description

13

THCMP_UCROSS2

Input channel 2 result upward threshold crossing
detected

14

OVERRUN_2

A new conversion on channel m completed and
has overwritten the previous contents of register
LAST_SAMPLE [2] before it has been read

15

THCMP_BRANGE3

Input channel 3 result below range

16

THCMP_ARANGE3

Input channel 3 result above range

17

THCMP_DCROSS3

Input channel 3 result downward threshold
crossing detected

18

THCMP_UCROSS3

Input channel 3 result upward threshold crossing
detected

19

OVERRUN_3

A new conversion on channel m completed and
has overwritten the previous contents of register
LAST_SAMPLE [3] before it has been read

20

THCMP_BRANGE4

Input channel 4 result below range

21

THCMP_ARANGE4

Input channel 4 result above range

22

THCMP_DCROSS4

Input channel 4 result downward threshold
crossing detected

23

THCMP_UCROSS4

Input channel 4 result upward threshold crossing
detected

24

OVERRUN_4

A new conversion on channel m completed and
has overwritten the previous contents of register
LAST_SAMPLE [4] before it has been read

25

THCMP_BRANGE5

Input channel 5 result below range

26

THCMP_ARANGE5

Input channel 5 result above range

27

THCMP_DCROSS5

Input channel 5 result downward threshold
crossing detected

28

THCMP_UCROSS5

Input channel 5 result upward threshold crossing
detected

29

OVERRUN_5

A new conversion on channel m completed and
has overwritten the previous contents of register
LAST_SAMPLE [5] before it has been read

31:30 -

Reset
value

Reserved.

-

48.6.26 Interrupt 1 clear status register
This register clears the interrupt 1 status bit fields.
Table 1148.Interrupt 1 clear status register (CLR_STAT1, address 0x400F 0F30) bit
description
Bit

Symbol

Description

Reset value

29:0

CSTAT1

Interrupt clear status

0x00000000

31:30

-

Reserved.

-

48.6.27 Interrupt 1 set status register
This register sets the interrupt 1 status bit fields.
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Chapter 48: 12-bit ADC (ADCHS)

Table 1149.Interrupt 1 set status register (SET_STAT1, address 0x400F 0f34) bit description
Bit

Symbol

Description

Reset value

29:0

SSTAT1

Interrupt set status

0x00000000

31:30

-

Reserved.

-

48.7 Functional description
48.7.1 Analog inputs
The A/D convertor architecture is a flash convertor type with differential inputs. The
nominal output code is:
d_out = 2048 x (vin_pos - vin_neg)/400 mV
The output format can be set by TWOS to either two's complement or offset binary.
The input signals of the ADC can be either AC-coupled by means of two capacitors or
connected directly to the inputs (DC-coupled). For AC coupling, the DC biasing is
generated internally by setting DCINNEG and DCINPOS to 1.
The input channels are multiplexed to ADC input vin_pos. All six input channels share the
same vin_neg, which is generated internally when DCINNEG is set to 1 and output at pin
ADCHS_NEG. The nominal vin_neg level is 0.50 V. Hence vin_pos should be in the range
from 0.50 ± 0.4 V.
It is possible to deselect the internal vin_neg and supply vin_neg externally at pin
ADCHS_NEG by setting DCINNEG to 0. When only one input is used then the ADC can
be used in true differential mode.
When sampling different channels in a high-speed interleaved fashion some crosstalk
may occur when one input is immediately sampled after another input. This crosstalk
effect increases with an increased ADC clock frequency and an increased source
impedance driving the input. It can be reduced by various means:

• Driving the affected input with a lower source impedance.
• Decreasing the ADC clock frequency.
• Increasing the ADC clock frequency by at least 2x and increasing the time between
two successive samples to more than 1 descriptor timer count (inserting one or more
dummy cycles).

48.7.2 Reduced power modes
The ADC power consumption is proportional the fADC. Besides reducing the fADC
frequency to reduce power the ADC has a power down mode and a power-down mode to
reduce power.
In power down mode (PD_CTRL = 1) power consumption is reduced, but not zero.
Recovery to normal mode is fast; RECOVERY_TIME/fADC.
In power-down mode (POWER_SWITCH=BGAP_SWITCH = 1) the ADC power
consumption is zero but recovery to normal mode takes more time;
RECOVERY_TIME/fADC plus additional 100 µs for BGAP and 10 µs for POWER.
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Chapter 48: 12-bit ADC (ADCHS)

When POWER_DOWN is set the ADC is powered down after the conversion has finished.
The ADC is automatically woken up before the next conversion. Wake up time is set in
RECOVERY_TIME (see Table 1128); this is default 144 fADC cycles.
Remark: If a descriptor MATCH_VALUE time is earlier than RECOVERY_TIME, then
automatic wake up cannot be guaranteed to be ready on time and should not be used; in
that case the previous descriptor should not set POWER_DOWN. If a descriptor
MATCH_VALUE time is earlier than RECOVERY_TIME, the conversion result CHAN_ID
will be set to 0x111 and the interrupt flag DSCR_ERROR will be raised.

Power gating is not removed automatically. Software should remove power gating prior to
starting conversion.

48.7.3 Descriptor driven conversion
The ADC has 6 input channels and a dedicated descriptor timer. Two descriptor tables
define which ADC input channel should be sampled at what time and in what sequence.
The descriptors also can raise an interrupt when done and halt and/or reset the descriptor
timer. The two tables allow double buffering usage; one table is active while the other
table can be preloaded and swapped with the active table to become the new active table.
The sampling time instance is defined by a 14-bit descriptor timer clocked by fADC. When
the descriptor timer value is equal to descriptor field MATCH_VALUE a sample is
converted and the next descriptor is processed. The timer will wrap around if not halted or
reset before it reaches the maximum count value 0x3FFF. The timer can be reset by
descriptor field RESET_TIMER or a reset of the complete ADC controller.
The active descriptor table can be started by:
1. A software trigger (CPU writes to a register TRIGGER, see Table 1125).
2. An external trigger.
External triggers are selected with the GIMA ADCHS_TRIGGER_IN register (see
Section 48.7.6) and can be one of:

•
•
•
•
•

SCT outputs CTOUT_0 and CTOUT_8
Timer 0 match output T0_MAT0 and timer 2 output T2_MAT0.
PWM Timer output MCOB2
GPIO inputs GPIO6[28] (at pin PD_14) and GPIO5[3] (at pin P2_3)
SGPIO outputs SGPIO10 and SGPIO12

Once the descriptor timer is started, the descriptor table is processed entry by entry. This
continues until descriptor field HALT is set. After a halt the descriptor timer and hence
descriptor processing should be restarted by a new trigger.
The descriptor processing order is controlled by field BRANCH to be:

• Linear, with wrap around to the table start after the last table entry
• Branch to the table start
• Swap the active table and branch to the table start of the new table

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Chapter 48: 12-bit ADC (ADCHS)

By branching to the other table with BRANCH set to 0b10, updating the old table and
branching back to the updated table, a sequence can be extended to unlimited size with
minimal real time software load. When swapping tables a DMA request can be raised to
enable the DMA to load a new table, see Section 48.7.4.

Table 0
Trigger

BR ANC H

Table 1

BRAN CH

BRANCH:

descriptor 0

00

descriptor 0

00

00 or 11: to next

descriptor 1

00

descriptor 1

00

01: to start

descriptor 2

00

descriptor 2

00

10: swap table

descriptor 3

00

descriptor 3

00

descriptor 4

10

descriptor 4

00

descriptor 5

x

descriptor 5

00

descriptor 6

x

descriptor 6

01

descriptor 7

x

descriptor 7

x

Fig 189. Using BRANCH to control the descriptor table processing order

Converted samples are stored per input channel M in register LAST_SAMPLE[M] and
also in the output FIFO. However, samples are not stored if BRANCH = 0b11. If the FIFO
is full no further data will be written in the FIFO and these samples will be lost. An interrupt
can be raised at a given FIFO fill level as defined by FIFO_LEVEL (see Section 48.6.3) or
when the FIFO is empty. To reduce the FIFO access rate two samples can be packed in
on 32-bit word when PACKED_READ is set. Reading an empty FIFO will result in a value
0x00008000 or 0x80008000.
Both descriptor tables are double buffered; one active table and one shadow table. The
shadow table can be accessed by software via registers DESCRIPTOR_0 (or
DESCRIPTOR_1) or loaded via DMA (see Section 48.7.4.2). The shadow table is copied
to the active table 0 (or 1) by setting bit UPDATE_TABLE in any of the descriptor 0
(descriptor 1) registers.
The active table and table entry are contained in register STATUS_REG1. It is possible to
load new values; these will be registered after the current entry has been processed. It is
not recommended to change this register while the table processing is running.

48.7.4 DMA access
48.7.4.1 DMA read
The FIFO can be read by DMA channel 8. A DMA transfer request is generated when the
FIFO fill level is equal to or more than set by FIFO_LEVEL. This is the same behavior that
will raise the interrupt flag FIFO_FULL. The burst size can be set to one in the DMA
channel control register (see Table 349). If the FIFO fill level is not equal to one of the
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Chapter 48: 12-bit ADC (ADCHS)

other DMA-supported burst sizes (applicable DMA burst sizes are 1, 4, 8 or 16), set the
burst size to 1. Reading an empty FIFO will result in a value 0x00008000 or 0x80008000.

48.7.4.2 DMA write
The descriptor tables can be loaded by DMA channel 7. Setting DMA_REQ_WR will
assert a DMA write request to the general purpose DMA. A complete table of 8 entries will
be copied from memory to the ADC. The DMA burst size should be set to equal or more
than the number of entries to be loaded. DMA-supported burst sizes are 1, 4, and 8. E.g.
for a table with 6 entries, burst size should be set to 8.
Non-contiguous channels can be transferred by the DMA using the scatter/gather linked
lists (Section 21.8.5).

48.7.5 Interrupts
The ADC can generate three types of interrupts.

48.7.5.1 Descriptor related interrupts
A descriptor related interrupt is raised under the following conditions (see also
:Section 48.6.19):

• when a descriptor entry with the descriptor INTERRUPT field set has been
processed.

• when a sample was converted before the ADC was fully woken up.
• when the input value caused under- or overflow of the ADC.
48.7.5.2 Comparator interrupts
Two window comparators are available to detect whether samples are within a range and
cross from one range to another. Window comparator A or B can be assigned to an input
channel. A comparator should only be assigned to one input. See also Table 1147.
48.7.5.2.1

Range interrupt

Each channel may be compared to the THR_A register values (or to the THR_B register
values) if comparator A (or B) is linked to a channel by the descriptor table
THRESHOLD_SEL field.
The comparator compares input samples against two levels THR_LOW and THR_HIGH
to detect whether input samples are within a range. The range status is stored per
channel in status bits THCMP_RANGE (see Table 1131). A below or above range
interrupts can be raised when the input channel sample is:

• sample < THR_LOW; TCHMP_RANGE set to 0b01, interrupt flag THCMP_BRANGE
is set.

• THR_LOW < sample < THR_HIGH; TCHMP_RANGE set to 0b00, no comparator
interrupt is raised.

• sample > THR_HIGH; TCHMP_RANGE set to 0b10, interrupt flag THCMP_ARANGE
is set.

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Chapter 48: 12-bit ADC (ADCHS)

48.7.5.2.2

Slope interrupt

If, for two successive conversion results on a given channel, one result is below this
threshold and the other is equal-to or above this threshold, then a threshold crossing has
occurred. In this case the THCMP_CROSS (see Table 1131) status bits will indicate that a
threshold crossing has occurred.
A threshold crossing event will also raise interrupt flag THCMP_DCROSS for downward
crossing or THCMP_UCROSS for upward crossings and may generate an interrupt 1
request if enabled to do so via the SET_EN1 bits associated with each channel in the
SET_EN1 register.

ADC out
downward crossing
upward crossing

Ab ove Range
THR_HIGH

In Range
THR_LOW

Bel ow Range

time

Fig 190. Threshold detection

48.7.5.3 FIFO status interrupts
An Interrupt can be raised at a defined FIFO level. See Section 48.6.19.

48.7.6 ADC external triggers
Conversions on the 12-bit ADC can be triggered by multiple external and internal sources.
The trigger source and trigger detection logic is defined by the GIMA (see
Section 18.4.25).
The ADCHS_TRIGGER_IN register (Section 18.4.25) selects one out of nine external
signals as hardware ADC trigger.
The trigger signal is inverted if INVERT is set, edge detected if EDGE is set and
synchronized if SYNC is set.
When SYNC is used no additional synchronization should be used (TRIGGER_SYNC
should be cleared). SYNC should be set when EDGE detection is set. Synchronization
includes two to three additional cycles latency.
Input pulses with duration less than 2 fADC cycles may not be always detected.

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Chapter 49: LPC43xx/LPC13Sxx DAC
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49.1 How to read this chapter
The DAC is available on all LPC43xx/LPC43Sxx parts.

49.2 Basic configuration
The DAC is configured as follows:

• The DMA_ENA bit in the DAC control register (Table 1154) must be enabled to obtain
a valid DAC output.

•
•
•
•

See Table 1150 for clocking and power control.
The DAC is reset by the DAC_RST (reset # 42).
The DAC interrupt is connected to interrupt slot # 0 in the NVIC.
For connecting to the GPDMA, use the DMAMUX register (Table 100) in the CREG
block and enable the GPDMA channel in the DMA Channel Configuration registers
Section 21.6.20.

Table 1150.DAC clocking and power control
Base clock

Clock to the DAC register
interface and rate clock for the
DMA counter.

Branch clock

BASE_APB3_CLK CLK_APB3_DAC

Operating
frequency

Notes

up to
204 MHz

-

49.3 Features
•
•
•
•
•
•
•

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10-bit resolution
Monotonic by design (resistor string architecture)
Controllable conversion speed
Can be optimized for speed and power
Low power consumption
Maximum update rate of 1 MHz
DMA support

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Chapter 49: LPC43xx/LPC13Sxx DAC

49.4 Pin description
Table 1151.DAC pin description
Pin

Type

Description

DAC

Output

Analog Output. The voltage on this pin (with respect to VSSA) is
VALUE/1024  VDDA as written to the DAC CR register
(Table 1153).The DAC pin is shared with the channel 0 input pin of
ADC0 and ADC1. The settling time of the DAC output can be
controlled by the BIAS bit in the DAC CR register.

VDDA

Power

Analog power and voltage reference. This pin provides a voltage
reference level VREF for the D/A converter.

VSSA

-

Ground.

49.5 Register description
Table 1152.Register overview: DAC (base address 0x400E 1000)
Name

Access

Address
offset

Description

Reset
value

Reference

CR

R/W

0x000

DAC register. Holds the conversion
data.

0

Table 1153

CTRL

R/W

0x004

DAC control register.

0

Table 1154

CNTVAL

R/W

0x008

DAC counter value register.

0

Table 1155

49.5.1 D/A converter register
This read/write register includes the digital value to be converted to an analog output
value and a bit that trades off performance vs. power.
Table 1153:D/A Converter register (CR - address 0x400E 1000) bit description
Bit

Symbol Value

Description

Reset
value

5:0

-

Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.

-

15:6

VALUE

Once this field is written with a new VALUE, the voltage on the 0
DAC pin (with respect to VSSA) is VALUE/1024 x VDDA. The
value of the DAC output pin is valid after the selected settling
time (see the BIAS bit in this register) has expired.

16

BIAS

31:17 -

Settling time

0

0

Shorter settling times and higher power consumption; allows
for a maximum update rate of 1 MHz.

1

Longer settling times and lower power consumption; allows for
a maximum update rate of 400 kHz.
Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.

-

49.5.2 D/A Converter Control register
This read/write register enables the DMA operation and controls the DMA timer.

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Chapter 49: LPC43xx/LPC13Sxx DAC

Table 1154.D/A Control register (CTRL - address 0x400E 1004) bit description
Bit

Symbol

0

INT_DMA_REQ

1

2

3

31:4

Value Description

Reset
value

DMA request

0

0

This bit is cleared on any write to the DAC CR register.

1

This bit is set by hardware when the timer times out.

0

Disable double-buffering.

1

Enable double-buffering. When this bit and the
CNT_ENA bit are both set, the double-buffering feature
in the DAC CR register will be enabled. Writes to the
DAC CR register are written to a pre-buffer and then
transferred to the DAC CR on the next time-out of the
counter.

DBLBUF_ENA

DMA double-buffering

CNT_ENA

0

DMA time-out
0

Time-out counter operation is disabled.

1

Time-out counter operation is enabled.

DMA_ENA

0

Combined DAC enable and DMA enable. When the
DMA_ENA bit is cleared (default state after reset), DAC
DMA requests are blocked and the DAC output is
disabled.
0

Disable DAC/DMA.

1

Enable DAC and enable DMA Burst Request Input 15
(see Table 330).

-

Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit is not
defined.

0

-

49.5.3 D/A Converter Counter Value register
This read/write register contains the reload value for the Interrupt/DMA counter.
Table 1155:D/A Converter counter value register (CNTVAL - address 0x400E 1008) bit
description
Bit

Symbol

Description

Reset value

15:0

VALUE

16-bit reload value for the DAC interrupt/DMA timer.

0

Reserved.

-

31:16 -

49.6 Functional description
49.6.1 DMA counter
When the counter enable bit CNT_ENA in DAC CTRL register is set, a 16-bit counter will
begin counting down, at the rate selected by CLK_APB3_DAC, from the value
programmed into the DAC CNTVAL register. The counter is decremented each time the
counter reaches zero, the counter will be reloaded by the value of the DAC CNTVAL
register and the DMA request bit INT_DMA_REQ will be set in hardware.

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Chapter 49: LPC43xx/LPC13Sxx DAC

Note that the contents of the DAC CTRL and DAC CNTVAL registers are read and write
accessible, but the timer itself is not accessible for either read or write.
If the DMA_ENA bit is set in the DAC CTRL register, the DAC DMA request will be routed
to the GPDMA. When the DMA_ENA bit is cleared, the default state after a reset, DAC
DMA requests are blocked.

49.6.2 Double buffering
Double-buffering is enabled only if both, the CNT_ENA and the DBLBUF_ENA bits are set
in DAC CTRL. In this case, any write to the DAC CR register will only load the pre-buffer,
which shares its register address with the DAC CR register. The DAC CR itself will be
loaded from the pre-buffer whenever the counter reaches zero and the DMA request is
set. At the same time the counter is reloaded with the CNTVAL register value.
Reading the DAC CR register will only return the contents of the DAC CR register itself,
not the contents of the pre-buffer register.
If either the CNT_ENA or the DBLBUF_ENA bits are 0, any writes to the DAC CR address
will go directly to the DAC CR register.
pbus

CNTVAL
pbus
pbus_wr_to_CR
pbus
16

LD

CTRL
3
2

pbus

1

set_intrpt
pbus_wr_to_CR

S
C

0

PRE-BUFFER

EN
LD
COUNTER

DMA_ena
cnt_ena
dblbuf_ena

16

zero

intrptDMA_req
set_intrpt
ena_cnt_and_dblbuf

1

0

MUX

pbus_wr_to_CR

LD
CR
pbus
DAC value

Fig 191. DAC control with DMA interrupt and timer

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Chapter 50: LPC43xx/LPC43Sxx EEPROM memory
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50.1 How to read this chapter
The EEPROM is available on parts LPC436x/LPC43S6x and
LPC435x/3x/2x/1x/LPC43S5x/S3x with on-chip flash.

50.2 Basic configuration
The EEPROM is configured using the following registers:

• See Table 1156 for clocking and power control.
• The EEPROM is reset by the EEPROM_RST (reset # 27).
• The EEPROM interrupt is ORed with the interrupts from flash banks A and B and
connected to interrupt slot #4 in the NVIC.
Table 1156.EEPROM clocking and power control

EEPROM

Base clock

Branch clock

Operating frequency

BASE_M4_CLK

CLK_M4_EEPROM

up to 204 MHz

50.3 Features
•
•
•
•

16384 Byte EEPROM
Access via memory on the AHB bus
Less than 3 ms erase / program time
Endurance of > 100 k erase / program cycles

50.4 General description
The EEPROM can be read and written/erased. A write operation involves two steps. The
first step is writing a minimum of 1 word (4 bytes) to a maximum of 32 words (128 bytes)
to the desired page in the 16 kB EEPROM address space at address 0x2004 0000. Step
two is an erase/program of that page into non-volatile memory. There are 128 pages
within the 16 kB EEPROM address space. The last page contains the EEPROM
initialization data and is not writable. Note that data written to a page cannot be read back
from the page address until the data have been programmed into non-volatile memory.

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Chapter 50: LPC43xx/LPC43Sxx EEPROM memory

50.5 Register description
Table 1157.Register overview: EEPROM (base address 0x4000 E000)
Name

Access

Address
offset

Description

Reset
value[1]

Reference

EEPROM registers

CMD

R/W

0x000

EEPROM command register

0

Table 1158

RWSTATE

R/W

0x008

EEPROM read wait state
register

0x0000
0E07

Table 1159

AUTOPROG

R/W

0x00C

EEPROM auto programming
register

0

Table 1160

WSTATE

R/W

0x010

EEPROM wait state register

0x0004
0802

Table 1161

CLKDIV

R/W

0x014

EEPROM clock divider register 0x0000
0063

Table 1162

PWRDWN

R/W

0x018

EEPROM power-down register

0

Table 1163

EEPROM interrupt registers:

INTENCLR

W

0xFD8

EEPROM interrupt enable clear 0

Table 1164

INTENSET

W

0xFDC

EEPROM interrupt enable set

0

Table 1165

INTSTAT

R

0xFE0

EEPROM interrupt status

0

Table 1166

INTEN

R

0xFE4

EEPROM interrupt enable

0

Table 1167

INTSTATCLR

W

0xFE8

EEPROM interrupt status clear

0

Table 1168

INTSTATSET

W

0xFEC

EEPROM interrupt status set

0

Table 1169

[1]

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Chapter 50: LPC43xx/LPC43Sxx EEPROM memory

50.5.1 EEPROM control registers
50.5.1.1 EEPROM command register
The EEPROM command register is used to trigger an erase/program operation on the
EEPROM device.
Table 1158.EEPROM command register (CMD, address 0x4000 E000) bit description
Bits

Symbol

Description

Reset
value

2:0

CMD

Command. Read data shows the last command executed on the
EEPROM.

0

110 = erase/program page
All other values are reserved.
31:3

-

Reserved. Read value is undefined, only zero should be written.

NA

50.5.1.2 EEPROM read wait state register
The EEPROM has no awareness of absolute time, while for EEPROM operations several
minimum absolute timing constraints have to be met. Therefore the EEPROM can only
derive time from its clock by frequency division.
The EEPROM read wait state register is used to define wait states for the AHB read
operation in functional mode only. In JTAG mode the PHASE1 and PHASE2 fields of the
EEPROM wait state register EEWSTATE are used.
Program the wait state fields to appropriate values in this wait state register for EEPROM
operation. The fields are -1 encoded, so programming zero will result in a one cycle wait
state.
The register contains two fields, each representing a minimum duration of a phase of the
EEPROM read. The appropriate values for each field are determined as follows:
(waitstates +1) x Tclk  duration
Table 1159.EEPROM read wait state register (RWSTATE, address 0x4000 E008) bit
description
Bits

Symbol

Description

7:0

RPHASE2

Reset
value

Wait states 2 (minus 1 encoded).

0x07

The number of system clock periods to meet the read operations
TRPHASE2 duration.
15:8

RPHASE1

Wait states 1 (minus 1 encoded).

0x0E

The number of system clock periods to meet a duration equal to
TRPHASE1.
31:16

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-

Reserved. Read value is undefined, only zero should be written.

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Chapter 50: LPC43xx/LPC43Sxx EEPROM memory

50.5.1.3 EEPROM auto programming register
The auto programming register allows the user to let the controller start an erase/program
cycle automatically after AHB writes without the need to program the CMD register after
the page register has been written.
Table 1160.EEPROM auto programming register (AUTOPROG, address 0x4000 E00C) bit
description
Bits

Symbol

Description

1:0

AUTOPROG

Auto programming mode:

Reset
value

0

00 = auto programming off
01 = erase/program cycle is triggered after 1 word is written
10 = erase/program cycle is triggered after a write to AHB
address ending with ......1111100 (last word of a page)
31:2

-

Reserved. Read value is undefined, only zero should be written. NA

50.5.1.4 EEPROM wait state register
The EEPROM has no awareness of absolute time, while for EEPROM operations several
minimum absolute timing constraints have to be met. Therefore the EEPROM can only
derive time from its clock by frequency division.
Program the wait state fields to appropriate values in this wait state register for EEPROM
operation. The fields are -1 encoded so programming zero will result in a one cycle wait
state.
The fields in the WAITSTATE register represent a minimum duration of a phase of the
EEPROM operation. The appropriate wait state values for each fields are determined as
follows:
(waitstates +1) x Tclk  duration
The delays for the write and erase/program operations are combined to simplify the
software interface. Timing for write and erase/program operations is almost identical.

Table 1161.EEPROM wait state register (WSTATE, address 0x4000 E010) bit description
Bits

Symbol

Description

Reset
value

7:0

PHASE3

Wait states for phase 3 (minus 1 encoded).

0x2

15:8

PHASE2

The number of system clock periods to meet a duration equal to TPHASE3.
Wait states for phase 2 (minus 1 encoded).

0x8

The number of system clock periods to meet a duration equal to TPHASE2.
23:16

PHASE1

Wait states for phase 1 (minus 1 encoded).

0x4

The number of system clock periods to meet a duration equal to TPHASE1.
30:24

-

31

LCK_PARWEP

Reserved. Read value is undefined, only zero should be written.

NA

Lock timing parameters for write, erase and program operation

0

0 = WSTATE and CLKDIV registers have R/W access
1 = WSTATE and CLKDIV registers have R only access
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Chapter 50: LPC43xx/LPC43Sxx EEPROM memory

50.5.1.5 EEPROM clock divider register
The EEPROM device requires a 1500 kHz clock. The nominal value of the frequency is
1500 kHz, the lower limit is 800 kHz, the maximum limit is 1600 kHz.
This clock is generated by dividing the system bus clock. The clock divider register
contains the division factor.
If the division factor is 0, the clock is be IDLE to save power.
cclk
--------------------------------  1500kHz
CLKDIV + 1

Table 1162.EEPROM clock divider register (CLKDIV, address 0x4000 E014) bit description
Bits

Symbol

Description

Reset value

15:0

CLKDIV

Division factor (minus 1 encoded).

31:16

-

Reserved. Read value is undefined, only zero should be
written.

NA

50.5.1.6 EEPROM power down register
Use the EEPROM power down register to put the EEPROM device in power down mode.
Do not put the EEPROM in power-down mode during a pending EEPROM operation.
After clearing this bit any EEPROM operation has to be suspended for 100 s while the
EEPROM wakes up.
Table 1163.EEPROM power down/DCM register (PWRDWN, address 0x4000 E018) bit
description
Bits

Symbol

Description

0

PWRDWN

Power down mode bit.

Reset
value

0

0 = not in power down mode.
1 = power down mode.
31:1

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-

Reserved. Read value is undefined, only zero should be written.

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Chapter 50: LPC43xx/LPC43Sxx EEPROM memory

50.5.2 Interrupt registers
These registers control interrupts from the EEPROM.

50.5.2.1 Interrupt enable clear register
Table 1164.Interrupt enable clear register (INTENCLR, address 0x4000 EFD8) bit description
Bits

Symbol

Description

1:0

-

Reserved. Read value is undefined, only zero should be written.

Reset value

2

PROG_CLR_EN

NA

Clear program operation finished interrupt enable bit for EEPROM.

0

0 = leave corresponding bit unchanged.
1 = clear corresponding bit.
31:3

-

Reserved. Read value is undefined, only zero should be written.

NA

50.5.2.2 Interrupt enable set register
Table 1165.Interrupt enable set register (INTENSET, address 0x4000 EFDC) bit description
Bits

Symbol

Description

1:0

-

Reserved. Read value is undefined, only zero should be written.

Reset value

2

PROG_SET_EN

Set program operation finished interrupt enable bit for EEPROM device 1.

NA
0

0 = leave corresponding bit unchanged.
1 = set corresponding bit.
31:3

-

Reserved. Read value is undefined, only zero should be written.

NA

50.5.2.3 Interrupt status register
Table 1166.Interrupt status register (INTSTAT, address 0x4000 EFE0) bit description
Bits

Symbol

Description

Reset
value

1:0

-

Reserved. The value read from a reserved bit is not defined.

2

END_OF_PROG

NA

EEPROM program operation finished interrupt status bit.

0

Bit is:
- set when this operation has finished OR when one is written to the corresponding bit
of the INTSTATSET register.
- cleared when one is written to the corresponding bit of the INTSTATCLR register.
31:3

-

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Reserved. The value read from a reserved bit is not defined.

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Chapter 50: LPC43xx/LPC43Sxx EEPROM memory

50.5.2.4 Interrupt enable register
Table 1167.Interrupt enable register (INTEN, address 0x4000 EFE4) bit description
Bits

Symbol

Description

Reset
value

1:0

-

Reserved. The value read from a reserved bit is not defined.

2

EE_PROG_DONE

EEPROM program operation finished interrupt enable bit.

NA
0

Bit is:
- set when one is written in the corresponding bit of the INTENSET register.
- cleared when one is written to the corresponding bit of the INTENCLR register.
31:3

-

Reserved. The value read from a reserved bit is not defined.

NA

50.5.2.5 Interrupt status clear register
Table 1168.Interrupt status clear register (INTSTATCLR, address 0x4000 EFE8) bit description
Bits

Symbol

Description

Reset value

1:0

-

Reserved. Read value is undefined, only zero should be written.

2

PROG_CLR_ST

Clear program operation finished interrupt status bit for EEPROM device.

NA
0

0 = leave corresponding bit unchanged.
1 = clear corresponding bit.
31:3

-

Reserved. Read value is undefined, only zero should be written.

NA

50.5.2.6 Interrupt status set
Table 1169.Interrupt status set register (INTSTATSET, address 0x4000 EFEC) bit description
Bits

Symbol

Description

Reset value

1:0

-

Reserved. Read value is undefined, only zero should be written.

2

PROG_SET_ST

Set program operation finished interrupt status bit for EEPROM device.

NA
0

0 = leave corresponding bit unchanged.
1 = set corresponding bit.
31:3

-

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Reserved. Read value is undefined, only zero should be written.

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Chapter 50: LPC43xx/LPC43Sxx EEPROM memory

50.6 Functional description
50.6.1 Initialization
At power-up, the reset should be applied for at least 100us. However a normal reset (not
at power-up) period is only 40 ns.
After the reset period the controller initializes the EEPROM by reading the first word
(containing trimming information) of the last (protected) page of the EEPROM. The
information that is read is used as input values of the EEPROM device and is ignored by
the controller and not visible on the APB bus.
During the EEPROM reset and initialization any started AHB/APB transfer will stall the
bus.

50.6.2 EEPROM operations
An EEPROM device cannot be programmed directly. Writing data to it and the actual
erase/program of the memory are two separate steps.
1. Write 1 word (4 bytes) to 32 words (128 bytes) to the desired page in the 16 kB
EEPROM address space. There are 128 pages in the 16 kB EEPROM address
space. Page 1 begins at the first address of the EEPROM address space
(EEPROM_START = 0x2004 0000). Page 2 begins at EEPROM_START + 128, page
3 begins at EEPROM_START + 256, etc. Writes to a page cannot cross a 128 page
boundary.
Remark: Before reading this data from the EEPROM or writing to another page,
program the contents of the page register into the EEPROM.

2. Program the data into the EEPROM with the erase/program command issued via the
EEPROM CMD register on the APB.

50.6.2.1 Writing and erase/programming
Writing an EEPROM page is achieved by AHB writes.
Partial page writes are allowed, and the EEPROM will only take locations where a word
has been written for the erase/program cycle. Any word in a page can be written in any
order, but every word in the page may only be written once.
The address of the AHB transfer prior to the erase/program cycle will determine the page
address for the erase/program cycle.
The following modes are supported for the write and erase/programming operation:

• AUTOPROG = 00: When the page has been written (fully or partially), the data has to
be programmed into non-volatile memory. The erase/program cycle is triggered by
writing 0x6 to the CMD register. The page that is programmed is determined by the
address of the last AHB transfer. Therefore it is advised to perform a page write with
the page address and to prevent AHB reads between page register writes and the
erase/program trigger.

• AUTOPROG = 01: Writing a single word to the page starts the erase/program cycle
automatically. This mode is useful store small data items (word) on random locations.
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Chapter 50: LPC43xx/LPC43Sxx EEPROM memory

• AUTOPROG = 10: Writing to the last word of the page register (AHB address ending
with 1111100) automatically starts the erase/program cycle. This mode is useful to
store multiple full pages of data.
During programming, the EEPROM is not available for other operations. To prevent
undesired loss in performance which would be caused by stalling the bus, the EEPROM
instead generates an error for AHB read/writes and APB writes when programming is
busy. In order to prevent the error response, the program operation finished interrupt can
be enabled or the interrupt status bit can be polled.

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Chapter 51: LPC43xx/LPC43Sxx JTAG, Serial Wire Debug
(SWD), and trace functions
Rev. 2.3 — 22 August 2018

User manual

51.1 How to read this chapter
The debug functions are identical on all LPC43xx/LPC43Sxx parts. The parallel trace port
is not available on the 100-pin packages.

51.2 Basic configuration
• Select between Debug modes:
– When the DBGEN pin is HIGH, the ARM debug mode is entered.
– When the DBGEN pin is LOW, JTAG BSDL is entered.

• The core frequency must be 120 MHz or lower to use the SWO function.
• The ETM trace capture speed is limited by the trace pin properties. The maximum
speed is 120 MHz when the EHS bit is set in the pin configuration register for the
multiplexed trace pins (Table 191).

• Enable ETB SRAM in the CREG block (see Section 11.4.8).
• To disable JTAG, see CRP3 for flash-based parts (see Section 6.6 “Code Read
Protection (CRP)”) or use the CREG5 register (Section 11.4.4 “CREG5 control
register”).

51.3 Features
• ARM Cortex-M4:
– Supports both standard JTAG and ARM Serial Wire Debug modes.
– Direct debug access to all memories, registers, and peripherals.
– No target resources are required for the debugging session.
– Trace port provides CPU instruction trace capability. Output can be via a 4-bit trace
data port, or Serial Wire Viewer.
– ETM time stamping is not implemented.
– Six instruction breakpoints that can also be used to remap instruction addresses
for code patches. Two data comparators that can be used to remap addresses for
patches to literal values.
– Four data Watchpoints that can also be used as trace triggers.
– Instrumentation Trace Macrocell allows additional software controlled trace.

• ARM Cortex-M0 (M0SUB and M0APP):
– JTAG debug mode supported.
– Two instruction breakpoints.
– Two data Watchpoints that can also be used as trace triggers.

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Chapter 51: LPC43xx/LPC43Sxx JTAG, Serial Wire Debug (SWD), and

51.4 General description
Debug and trace functions are integrated into the ARM Cortex-M4. Serial wire debug and
trace functions are supported in addition to a standard JTAG debug and parallel trace
functions. The ARM Cortex-M4 is configured to support up to eight breakpoints and four
watchpoints.
Debugging with the LPC43xx defaults to JTAG. Once in the JTAG debug mode, the debug
tool can switch to Serial Wire Debug mode.
Remark: The SWD mode is supported for the ARM Cortex-M4 only.

51.4.1 Embedded Trace Macrocell (ETM)
Trace can be performed using either a 4-bit parallel interface or the Serial Wire Output.
The ETM Trace port provides CPU instruction trace capability using the ETB memory. To
access the ETB memory, enable the ETB SRAM in the CREG block (see Section 11.4.8).
Remark: The ETM time stamping feature is not implemented.

51.5 Pin description
Table 1170 to Table 1172 indicate the various pin functions related to debug and trace.
Some of these functions share pins with other functions which therefore may not be used
at the same time. Use of the JTAG port excludes use of Serial Wire Debug and Serial
Wire Output. Use of the parallel trace requires five pins that may be part of the user
application, limiting debug possibilities for those features. Trace using the Serial Wire
Output does not have this limitation but the bandwidth is limited.
Table 1170.JTAG pin description

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Pin Name

Type

Description

TCK

Input

JTAG Test Clock. This pin is the clock for debug logic when in the
JTAG debug mode.

TMS

Input

JTAG Test Mode Select. The TMS pin selects the next state in the
TAP state machine.

TDI

Input

JTAG Test Data In. This is the serial data input for the shift register.

TDO

Output

JTAG Test Data Output. This is the serial data output from the shift
register. Data is shifted out of the device on the negative edge of the
TCK signal.

TRST

Input

JTAG Test Reset. The TRST pin can be used to reset the test logic
within the debug logic.

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Chapter 51: LPC43xx/LPC43Sxx JTAG, Serial Wire Debug (SWD), and

Table 1171.Serial Wire Debug pin description[1]
Pin Name

Type

Description

SWDCLK

Input

Serial Wire Clock. This pin is the clock for debug logic when in the
Serial Wire Debug mode.

SWDIO

Input /
Output

Serial wire debug data input/output. The SWDIO pin is used by an
external debug tool to communicate with and control the Cortex-M4
CPU.

SWO

Output

Serial Wire Output. The SWO pin optionally provides data from the
ITM and/or the ETM for an external debug tool to evaluate.
Remark: The core frequency must be 120 MHz or lower to use the
SWO.

[1]

Supported for ARM Cortex-M4 only.

Table 1172.Parallel Trace pin description
Pin Name

Type

Description

TRACECLK

Input

Trace Clock. This pin provides the sample clock for trace data on
the TRACEDATA pins when tracing is enabled by an external debug
tool.

TRACEDATA[3:0]

Output

Trace Data bits 3 to 0. These pins provide ETM trace data when
tracing is enabled by an external debug tool. The debug tool can
then interpret the compressed information and make it available to
the user.

51.6 Debug connections
The LPC43xx supplies dedicated pins for JTAG and Serial Wire Debug (SWD). When a
debug session is started, the part will be in JTAG debug mode. Once in debug mode, the
debugger can switch the device to SWD mode.
Connections from a target board to the debugger can vary. Selecting a debug connector
to add to a new board design depends on the debug tools that will be used.
Remark: The SWD mode is supported for the ARM Cortex-M4 only.

51.6.1 ARM Standard JTAG connector (20-pin)
Figure 192 shows a standard JTAG connector. The ARM Standard JTAG Connector
provides support for Serial Wire and JTAG interface modes in a 20-pin (0.1") connector. It
can be used to access all SWD, SWV, and JTAG signals.

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3.3 V

3.3 V
1

2

3

4

5

6

7
9

8
10

11

12

13

14

15

16

17

18

19

20

TRST
TDI
TMS
TCLK
TDO
RESET
n.c
n.c.

10 kΩ to 100 kΩ

3.3 V

Fig 192. ARM Standard JTAG Connector

51.6.2 Cortex debug connector (10-pin)
Figure 193 shows the Cortex debug connector (10-pin). This connector provides support
for Serial Wire and JTAG in a very small connector. The 10-pin Cortex debug connector
can access to all SWD, SWV, and JTAG signals.

3.3 V

10 kΩ to 100 kΩ

3.3 V
1

2

3

4

5

6

7 Key

8

9

10

TMS /SWDIO
TCK/ SWDCLK
TDO /SWO
TDI
RESET

Fig 193. Cortex Debug Connector

51.6.3 Cortex Debug + ETM connector (20-pin)
If the debug trace feature will be used, there is also a debug-with-trace connector
specification as shown in Figure 194. This small 20-pin (0.05") connector provides access
to SWD, SWV, JTAG, and ETM (4-bit) signals.
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3.3 V

10 kΩ to 100 kΩ

3.3 V
1

2

3

4

5

6

7 Key

8

9

10

11

12

13

14

15

16

17

18

19

20

TMS / SWDIO
TCK/ SWDCLK
TDO/ SWO
TDI
RESET
TRACECLK
TRACEDATA[0]
TRACEDATA[1]
TRACEDATA[2]
TRACEDATA[3]

Fig 194. Cortex Debug + ETM Connector

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Chapter 51: LPC43xx/LPC43Sxx JTAG, Serial Wire Debug (SWD), and

51.7 Debug Notes
The following limitations apply during debugging:

• Due to limitations of the Cortex-M4 integration, the LPC43xx cannot wake up in the
usual manner from Deep Sleep and Power-down modes. Do not use these modes
during debug.

• The debug mode changes the way in which reduced power modes are handled by the
Cortex-M4 CPU. This causes power modes at the device level to be different from
normal mode operation. These differences mean that power measurements should
not be made while debugging because the results will be higher than during normal
operation in an application.

• During a debugging session, the System Tick Timer and the Repetitive Interrupt
Timers are automatically stopped whenever the CPU is stopped. Other peripherals
are not affected. If the Repetitive Interrupt Timer is configured such that its clock rate
is lower than the CPU clock rate, the RIT may not increment predictably during some
debug operations, such as single stepping.

• Debugging is disabled if code read protection of the flash memory is enabled.

51.8 Debug memory re-mapping
Following chip reset, a portion of the Boot ROM is mapped to address 0 so that it will be
automatically executed. The Boot ROM switches the map to point to 0x1000 0000 or
0x1C00 0000 (when booting from EMC) or 0x8000 0000 (when booting from SPIFI). Code
execution can start from address 0x0000 0000 using the M4 memory mapping register
(Table 98).
The register mapping is normally not transparent to the user. However, when a debugger
halts CPU execution immediately following reset, the Boot ROM is still mapped to address
0 and the IRC calibration value has not been loaded, which may cause the IRC frequency
to be outside of the specified 12 MHz. Ideally, the debugger should correct the mapping
automatically in this case.

51.8.1 Description
In the Arm Cortex-M3 and M4 cores, the Flash Patch and Breakpoint (FPB) is a feature
used by debug tools to set breakpoints. The FPB has a breakpoint unit supporting two
literal comparators and six instruction comparators. During user firmware development,
the debugger can utilize the FPB feature, while the user code does not use this feature.
Further information on the feature is available from Arm Info Centre.
In the field, a potential attack can occur during system firmware or other Over the Air
(OTA) updates, where malicious code may be loaded into the system SRAM/Flash and
used to execute a ROM Application Programming Interface (API) re-map using the FPB
function in privileged mode. With the ROM API remapped into another memory space, the
corresponding ROM API calls, such as the device Unique ID (UID) may return different
values compared to what is stored in the device. This can result in potential cloning, when
the UID feature is used for product identification or product licensing.
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Chapter 51: LPC43xx/LPC43Sxx JTAG, Serial Wire Debug (SWD), and

51.8.2 Mitigation
This specific attack is only possible when the malicious code can get direct privileged
access to the device memory (SRAM/Flash), and enable the FPB feature to remap the
ROM API. The correct method to prevent such an attack is to prevent malicious code to
get access to the system memory. Such methods are discussed further in the next
section.
If preventing such malicious code from obtaining privileged access is not possible, a
mitigation strategy is proposed is to detect if the FPB feature is enabled, before calling
any ROM API’s.
The user code can choose to run the FPB check before the system firmware update
occurs, via a secondary bootloader, which downloads the FPB check routine into SRAM
and ensure the FPB feature is disabled before perform firmware update.
Remark: Section 51.8.2.1 and Section 51.8.2.2 presents possible methods a user can
employ in the application code so that the UID or ROM API cannot (easily) be interfered
by remapping. If the adversary gets hold of the code and is able to reverse engineer it, the
user code can be modified to avoid these checks.

NXP recommends to execute the two FPB checks in the application code before calling
the ROM API or before any system firmware update.

51.8.2.1 Detection Option One
The first option proposed is to detect if the FPB function is enabled, in this case, the
debugger cannot be running.
Code snippet:
#define FP_CTRL_ADDRESS 0xE0002000
#define FP_CTRL_ENABLE ((*((uint32_t *)(FP_CTRL_ADDRESS))) & (uint32_t)1 )
#define ASSERT_FP_CTRL_ENABLE() if(FP_CTRL_ENABLE) { error_handler(); };

Insert the following MACRO, the program in front of the ROM API call that might be critical
if remapped:
ASSERT_FP_CTRL_ENABLE();
ROM_API_call();

This adds four additional instructions per MACRO insertion to the code, assuming that
there is a global error_handler() routine that might be called.

51.8.2.2 Detection Option Two
The second option is to detect if the FPB feature is remapping the ROM Address of the
LPC Microcontroller, this will allow debug support but increases the number of checks
(and code).
#define FP_CTRL_ADDRESS 0xE0002000
#define FP_COMP0_ADDRESS 0xE0002008
#define FP_COMP1_ADDRESS 0xE000200C
#define FP_COMP2_ADDRESS 0xE0002010
#define FP_COMP3_ADDRESS 0xE0002014
#define FP_COMP4_ADDRESS 0xE0002018
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Chapter 51: LPC43xx/LPC43Sxx JTAG, Serial Wire Debug (SWD), and

#define FP_COMP5_ADDRESS 0xE000201C
#define FP_COMP6_ADDRESS 0xE0002020
#define FP_COMP7_ADDRESS 0xE0002024
#define FP_CTRL_ENABLE ((*((uint32_t *)(FP_CTRL_ADDRESS))) & (uint32_t)1 )
#define ASSERT_FP_CTRL_ENABLE() if(FP_CTRL_ENABLE) { error_handler(); };

Macro defined for each comparator check
#define FP_COMP# IN_RANGE(0xC0000000,0x1FFFFFFC);
{
((*((uint32_t *)( FP_COMP#_ADDRESS))) & (uint32_t)1) = 1
& ((*((uint32_t *)( FP_COMP#_ADDRESS))) & (uint32_t)0x1FFFFFFC)
& ((*((uint32_t *)( FP_COMP#_ADDRESS))) & (uint32_t)0xC0000000)
}

In the application code, users should not make a ROM API call if:
ASSERT_FP_CTRL_ENABLE();
ASSERT_FP_COMP0_IN_RANGE(0xC0000000,0x1FFFFFFC);
or
ASSERT_FP_COMP1_IN_RANGE(0xC0000000,0x1FFFFFFC);
or
ASSERT_FP_COMP2_IN_RANGE(0xC0000000,0x1FFFFFFC);
or
ASSERT_FP_COMP3_IN_RANGE(0xC0000000,0x1FFFFFFC);
or
ASSERT_FP_COMP4_IN_RANGE(0xC0000000,0x1FFFFFFC);
or
ASSERT_FP_COMP5_IN_RANGE(0xC0000000,0x1FFFFFFC);
or
ASSERT_FP_COMP6_IN_RANGE(0xC0000000,0x1FFFFFFC);
or
ASSERT_FP_COMP7_IN_RANGE(0xC0000000,0x1FFFFFFC);

51.9 JTAG TAP Identification
The JTAG TAP controller contains device ID that can be used by debugging software to
identify the general type of device.
Table 1173.JTAG TAP identification
Mode

ID code

JTAG mode

0x4BA0 0477

SWD mode

0x2BA0 1477

Cortex-M0 co-processor

0x0BA0 1477

Debug and trace functions are integrated into the ARM Cortex-M4. Serial wire debug and
trace functions are supported in addition to a standard JTAG debug and parallel trace
functions. The ARM Cortex-M4 is configured to support up to eight breakpoints and four
watch points.

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Chapter 51: LPC43xx/LPC43Sxx JTAG, Serial Wire Debug (SWD), and

The ARM Cortex-M0 coprocessor supports JTAG debug. A standard ARM
Cortex-compliant debugger can debug the ARM Cortex-M4 and the ARM Cortex-M0
cores separately or both cores simultaneously.
Remark: In order to debug the ARM Cortex-M0, release the M0 reset by software in the
RGU block.

LPC43xx

TCK
TMS
TRST
TDI

TDO
DBGEN
RESET

ARM

ARM

TCK
Cortex-M0APP
TMS
TRST
TDI
TDO

TCK
Cortex-M0SUB
TMS
TRST
TDI
TDO

JTAG ID = 0x0BA0 1477

JTAG ID = 0x0BA0 1477

TCK
TMS
TRST
TDI

ARM
Cortex-M4
TDO

JTAG ID = 0x4BA0 0477

DBGEN = HIGH
RESET = HIGH

Remark: Only enabled ARM Cortex-M0 cores are visible in the debug tool.

Fig 195. Multi-core debug configuration

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Chapter 52: LPC43xx/LPC43Sxx ARM Cortex M0/M4 reference
Rev. 2.4 — 22 August 2018

User manual

52.1 How to read this chapter
Details of the ARM Cortex-M0 and ARM Cortex-M4 specification can be found in the
following documents:

• Cortex-M4 Devices Generic User Guide
• Cortex-M0 Devices Generic User Guide

52.2 Cortex-M4 instruction set summary
Table 1174 shows the Cortex-M4 instruction set with the following abbreviations to
calculate the number of cycles:

• P = The number of cycles required for a pipeline refill. This ranges from 1 to 3
depending on the alignment and width of the target instruction, and whether the
processor manages to speculate the address early.

• B = The number of cycles required to perform the barrier operation. For DSB and
DMB, the minimum number of cycles is zero. For ISB, the minimum number of cycles
is equivalent to the number required for a pipeline refill.

• N = The number of registers in the register list to be loaded or stored, including PC or
LR.

• W = The number of cycles spent waiting for an appropriate event.
Table 1174.Cortex-M4 instruction set summary
Operation

Move

Add

Subtract

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Description

Assembler

Cycles

Register

MOV Rd, 

1

16-bit immediate

MOVW Rd, #

1

Immediate into top

MOVT Rd, #

1

To PC

MOV PC, Rm

1+P

Add

ADD Rd, Rn, 

1

Add to PC

ADD PC, PC, Rm

1+P

Add with carry

ADC Rd, Rn, 

1

Form address

ADR Rd,
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Author                          : NXP Semiconductors
Create Date                     : 2018:08:22 19:29:38Z
Keywords                        : LPC4300 user manual, LPC43xx/LPC43Sxx user manual, LPC43xx, LPC4300, LPC43S50, LPC43S30, LPC43S20, LPC43S37, LPC43S57, LPC43S67, LPC4367, LPC43S70, ARM Cortex-M4, ARM Cortex-M0
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Format                          : application/pdf
Title                           : LPC43xx_LPC43Sxx User manual
Creator                         : NXP Semiconductors
Description                     : The LPC43xx/LPC43Sxx are ARM Cortex-M4 based microcontrollers, which include an ARM Cortex-M0 coprocessor, up to 1 MB of flash, up to 264 kB of SRAM, and operate at CPU frequencies of up to 204 MHz.
Subject                         : LPC4300 user manual, LPC43xx/LPC43Sxx user manual, LPC43xx, LPC4300, LPC43S50, LPC43S30, LPC43S20, LPC43S37, LPC43S57, LPC43S67, LPC4367, LPC43S70, ARM Cortex-M4, ARM Cortex-M0
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