Manual

manual

User Manual:

Open the PDF directly: View PDF PDF.
Page Count: 9

Scroll down to view the document on your mobile browser.
Echo Cancellation Core (16-lag) Based on LSM AlgorithmAnkai Liu2018-09-06AbstractThis document is a user manual for echo cancellation core (16-lag)based on LSM algorithm.1 IntroductionThis document is a user manual for echo cancellation core (16-lag) basedon LSM algorithm. The core is designed on CYCLONE IV FPGAs. Itis serving for a SPECIFIC signal type (16 bit binary signal with thefirst digit represent the sign) and a specific echo type (echo caused bytransmission within the circuit).In the project, we have implemented 4-lag and 16-lag cores that takescontinuous sampling. The whole core only require gate-logic calculations.We will provide 3 test bench in order to cover all submodules for potentialfuture modifications.2 echo cancelation full lag16Top level module.
Figure 1: echo cancelation full lag16 hierarchyFigure 2: echo cancelation full lag162.1 Inputclk operation: Global operation clocks.sampling cycle counter: Global sampling clocks.rst: Global reset.enable: Local input. Needs to stay 1 when using the module.set max iteration: Local input. Set to be the numbers of iterations thatusers wants to achieve.sig16b: Original signal from sender in 16 bits binary formate.sig16b lag: Signal with lag fro receiver in 16 bits binary formate.2Echo Cancellation Core (16-lag) Based on LSM Algorithm

Navigation menu