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Echo Cancellation Core (16-lag) Based on LSM Algorithm

Ankai Liu
2018-09-06

Abstract

This document is a user manual for echo cancellation core (16-lag)
based on LSM algorithm.

1

Introduction

This document is a user manual for echo cancellation core (16-lag) based
on LSM algorithm. The core is designed on CYCLONE IV FPGAs. It
is serving for a SPECIFIC signal type (16 bit binary signal with the
first digit represent the sign) and a specific echo type (echo caused by
transmission within the circuit).

In the project, we have implemented 4-lag and 16-lag cores that takes
continuous sampling. The whole core only require gate-logic calculations.
We will provide 3 test bench in order to cover all submodules for potential
future modifications.

2

echo cancelation full lag16

Top level module.

Figure 1: echo cancelation full lag16 hierarchy

Figure 2: echo cancelation full lag16

2.1

Input
clk operation: Global operation clocks.
sampling cycle counter: Global sampling clocks.
rst: Global reset.
enable: Local input. Needs to stay 1 when using the module.
set max iteration: Local input. Set to be the numbers of iterations that
users wants to achieve.
sig16b: Original signal from sender in 16 bits binary formate.
sig16b lag: Signal with lag fro receiver in 16 bits binary formate.

2

Echo Cancellation Core (16-lag) Based on LSM Algorithm

2.2

Output
para approx: Approximate parameters.
iteration: Numbers of iterations that has been done.
sig16b without echo: Approximation of original signal/signal without
the echo in 16 bits binary formate.

2.3

Important
• The echo cancelation full core takes new sample when ”sampling cycle counter = 0”. The reset cycle of sampling cycle counter
must be more than 2500 of the operation clks/600 of operation cycles.
• The recommenced maximum iteration is 64 for lag 4. See LSM algorithm demo.pdf
for details.

3

sig16b to double
Transforming 16 bit binary signal to double.

Figure 3: sig16b to double

3.1

Input
clk operation: Global operation clocks.

Echo Cancellation Core (16-lag) Based on LSM Algorithm

3

rst: Global reset.
enable: Local input. Turn on for 2 operation cycles/4 operation clks and
then turn off.
sig16b: Input signal in 16 bit binary formate.

3.2

output
double: Output signal in double.
ready: 1 for ready.

4

double to sig16b
Transform data types from double to 16 bit binary signal

Figure 4: double to sig16b

4.1

Input
sampling cycle counter: Global sampling clocks.
clk operation: Global operation clocks.
rst: Global reset.
enable: Local input. Needs to stay 1 when using the module.
double: Input in double.

4

Echo Cancellation Core (16-lag) Based on LSM Algorithm

4.2

Output
sig16b: Output in 16 bit binary formate.

5

para approx lag16
Estimate parameters for given original signals and signals with lags.

Figure 5: para approx lag16

5.1

Input
rst: Global reset.
sampling cycle counter: Global sampling clocks.
clk operation: Global operation clocks.
enable sampling: Local input. In order to make sure the samplings are
aligned, needs to stay on even the module is not operating.
enable: Local input. Turn on for 2 operation cycles/4 operation clks and
then turn off.
signal: Input signal in double.
signal lag: Input lag signal in double
gamma: Default is
64’b0011111111010000000000000000000000000000000000000000000000000000(0.01)

Echo Cancellation Core (16-lag) Based on LSM Algorithm

5

mu: Default is
64’b0011111111110000000000000000000000000000000000000000000000000000(1)
5.2

Output
parameters: Estimate parameters in double.
e: Unbiased error of prediction
e exp: Exponential of unbiased error of prediction
normalize amp exp: Exponential of amplitude of normalization. For debug purpose.
ready: 1 for ready

6

echo cancelation lag16
Preform echo cancellation for given parameters, original signals and signal
with lags.

Figure 6: echo cancelation lag16

6.1

Input
rst: Global reset.
sampling cycle counter: Global sampling clocks.
clk operation: Global operation clocks.

6

Echo Cancellation Core (16-lag) Based on LSM Algorithm

enable sampling Local input. In order to make sure the samplings are
aligned, needs to stay on even the module is not operating.
enable: Local input. Turn on for 2 operation cycles/4 operation clks and
then turn off.
signal reveive: Signals with echo in double.
signal send: Original signals in double.
parameters: Estimate parameters
6.2

Output
signal without echo: Signal after echo cancellation in double
signal without echo exp: Exponential of output signal. For debug purpose.
ready: 1 for ready.

7

lag generator lag16
Generate lag signal for given original signal and parameters.

Figure 7: lag generator lag16

7.1

Input
rst: Global reset.

Echo Cancellation Core (16-lag) Based on LSM Algorithm

7

enable sampling Local input. In order to make sure the samplings are
aligned, needs to stay on even the module is not operating.
enable: Local input. Turn on for 2 operation cycles/4 operation clks and
then turn off.
sampling cycle counter: Global sampling clocks.
clk operation: Global operation clocks.
signal: Signals with echo in double.
parameters: Estimate parameters

7.2

Output
signal lag: Signal after echo cancellation in double
signal align: Exponential of output signal. For debug purpose.
ready: 1 for ready.

8

double 16b tb
Test bench for data conversion modules:
double to sig16b.v
sig16b to double.v

Figure 8: double 16b tb hierarchy

9

tb all
Test bench for all sub-level modules:
sig16b to double.v
lag generator lag16.v

8

Echo Cancellation Core (16-lag) Based on LSM Algorithm

para approx lag16.v
echo cancelation lag16.v
double to sig16b.v

Figure 9: tb all hierarchy

10

echo cancelation full tb lag16
Test bench for top-level module:
echo cancelation full lag16.v

Figure 10: echo cancelation full tb lag16 hierarchy

Echo Cancellation Core (16-lag) Based on LSM Algorithm

9



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