Ngspice User Manual
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Ngspice Users Manual
Version 22
Paolo Nenzi, Holger Vogt
September 26, 2010
2
Locations
The project and download pages of ngspice may be found at
Ngspice home page http://ngspice.sourceforge.net/
Project page at sourceforge http://sourceforge.net/projects/ngspice/
Download page at sourceforge http://sourceforge.net/projects/ngspice/ les/
CVS source download http://sourceforge.net/scm/?type=cvs&group_id=38962
Status
This manual is a work in progress. Some todos are listed in the following. More is surely needed. You
are invited to report bugs, missing items, wrongly described items, bad English style etc.
To Do
1. Review of chapt. 1.3
2. .func
3. hfet1,2, jfet2 model descriptions
4. tclspice compilation chapt. 20.5
5. adms chapt. 14
6. more examples
7. LINUX graphics interface chapt. 19.2
3
Copyrights
Spice documentation copyright
Copyright 1996 The Regents of the University of California.
Permission to use, copy, modify, and distribute this software and its documentation for educational,
research and non-pro t purposes, without fee, and without a written agreement is hereby granted, provided that the above copyright notice, this paragraph and the following three paragraphs appear in all
copies. This software program and documentation are copyrighted by The Regents of the University of
California. The software program and documentation are supplied "as is", without any accompanying
services from The Regents. The Regents does not warrant that the operation of the program will be uninterrupted or error-free. The end-user understands that the program was developed for research purposes
and is advised not to rely exclusively on the program for any reason.
IN NO EVENT SHALL THE UNIVERSITY OF CALIFORNIA BE LIABLE TO ANY PARTY FOR
DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING
LOST PROFITS, ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF THE UNIVERSITY OF CALIFORNIA HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. THE UNIVERSITY OF CALIFORNIA SPECIFICALLY DISCLAIMS
ANY WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE SOFTWARE PROVIDED HEREUNDER IS ON AN "AS IS" BASIS, AND THE UNIVERSITY OF CALIFORNIA HAS
NO OBLIGATIONS TO PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR
MODIFICATIONS.
XSPICE SOFTWARE USER'S MANUAL copyright
Copyright
©
1992 Georgia Tech Research Corporation All Rights Reserved.
This material may be reproduced by or for the U.S. Government pursuant to the copyright license under
the clause at DFARS 252.227-7013 (Oct. 1988)
CIDER RESEARCH SOFTWARE AGREEMENT
This chapter speci es the terms under which the CIDER software and documentation coming with the
original distribution are provided.
Software is distributed as is, completely without warranty or service support.
The University of
California and its employ- ees are not liable for the condition or performance of the software.
The University does not warrant that it owns the copyright or other proprietary rights to all software
and documentation provided under this agreement, notwithstanding any copyright notice, and shall not
be liable for any infringement of copyright or proprietary rights brought by third parties against the recipient of the software and documentation provided under this agreement.
THE UNIVERSITY OF CALIFORNIA HEREBY DISCLAIMS ALL IMPLIED WARRANTIES, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE UNIVERSITY IS NOT LIABLE FOR ANY DAMAGES INCURRED BY
THE RECIPIENT IN USE OF THE SOFTWARE AND DOCUMENTATION, INCLUDING DIRECT,
INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES.
The University of California grants the recipient the right to modify, copy, and redistribute the
software and documentation, both within the recipient's organization and externally, subject to the
following restrictions:
(a) The recipient agrees not to charge for the University of California code itself. The recipient may,
however, charge for additions, extensions, or support.
(b) In any product based on the software, the recipient agrees to acknowledge the research group that
developed the software. This acknowledgement shall appear in the product documentation.
(c) The recipient agrees to obey all U.S. Government restrictions governing redistribution or export
of the software and documentation.
4
Part I
Ngspice User Manual
5
Contents
I Ngspice User Manual
5
1 Introduction
1.1
1.2
21
Simulation Algorithms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
22
1.1.1
Analog Simulation
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
22
1.1.2
Digital Simulation
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
22
1.1.3
Mixed-Mode Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
22
1.1.4
Mixed-Level Simulation
23
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Supported Analyses
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
24
1.2.1
DC Analyses
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
24
1.2.2
AC Small-Signal Analysis
1.2.3
Transient Analysis
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
25
1.2.4
Pole-Zero Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
25
1.2.5
Small-Signal Distortion Analysis
1.2.6
Sensitivity Analysis
1.2.7
Noise Analysis
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
24
. . . . . . . . . . . . . . . . . . . . . . . . . . . .
25
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
25
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
26
1.3
Analysis at Dierent Temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
26
1.4
Convergence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
27
1.4.1
Voltage convergence criterion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
27
1.4.2
Current convergence criterion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
27
1.4.3
Convergence failure
28
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2 Circuit Description
29
2.1
General Structure and Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
29
2.2
Basic lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
30
2.2.1
Title Line, .TITLE line
30
2.2.2
.END Line
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
31
2.2.3
Comments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
31
2.2.4
End-of-line comments
2.3
2.4
Device Models
Subcircuits
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
31
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
31
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
32
2.4.1
.SUBCKT Line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
33
2.4.2
.ENDS Line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
33
2.4.3
Subcircuit Calls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
33
2.5
GLOBAL
2.6
INCLUDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
34
2.7
LIB
34
2.8
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
33
Parametric netlists . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
34
2.8.1
.param line
34
2.8.2
Brace expressions in circuit elements:
2.8.3
Subcircuit parameters
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
35
2.8.4
Symbol scope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
35
2.8.5
Syntax of expressions
36
2.8.6
Reserved words
2.8.7
Alternative syntax
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
34
37
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
37
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
37
2.10 Parameters, functions, expressions, and command scripts . . . . . . . . . . . . . . . . . . .
37
2.9
func
2.10.1 Parameters
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7
37
CONTENTS
8
2.10.2 Nonlinear sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
38
2.10.3 Control commands, Command scripts
38
. . . . . . . . . . . . . . . . . . . . . . . . .
3 Circuit Elements and Models
3.1
3.2
39
General options and information
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
39
3.1.1
Simulating more devices in parallel . . . . . . . . . . . . . . . . . . . . . . . . . . .
39
3.1.2
Technology scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
39
3.1.3
Model binning
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
39
3.1.4
Transistors and Diodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
39
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
40
3.2.1
Elementary Devices
Resistors
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
40
3.2.2
Semiconductor Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
41
3.2.3
Semiconductor Resistor Model (R) . . . . . . . . . . . . . . . . . . . . . . . . . . .
41
3.2.4
Resistors, dependent on expressions
42
3.2.5
Capacitors
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
43
3.2.6
Semiconductor Capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
43
3.2.7
Semiconductor Capacitor Model (C) . . . . . . . . . . . . . . . . . . . . . . . . . .
43
3.2.8
Capacitors, dependent on expressions
44
3.2.9
Inductors
. . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
45
3.2.10 Inductor model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
46
3.2.11 Coupled (Mutual) Inductors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
46
3.2.12 Inductors, dependent on expressions
47
. . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.13 Capacitor or inductor with initial conditions
. . . . . . . . . . . . . . . . . . . . .
47
3.2.14 Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
48
3.2.15 Switch Model (SW/CSW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
48
4 Voltage and Current Sources
51
4.1
Arbitrary Phase Sources
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
51
4.2
Independent Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
51
4.2.1
Pulse
52
4.2.2
Sinusoidal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
53
4.2.3
Exponential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
53
4.2.4
Piece-Wise Linear
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
53
4.2.5
Single-Frequency FM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
54
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5 Linear Dependent Sources
55
5.1
Linear Voltage-Controlled Current Sources (VCCS) . . . . . . . . . . . . . . . . . . . . . .
55
5.2
Linear Voltage-Controlled Voltage Sources (VCVS) . . . . . . . . . . . . . . . . . . . . . .
55
5.3
Linear Current-Controlled Current Sources (CCCS)
. . . . . . . . . . . . . . . . . . . . .
55
5.4
Linear Current-Controlled Voltage Sources (CCVS) . . . . . . . . . . . . . . . . . . . . . .
56
5.5
Polynomial Source Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
56
6 Non-linear Dependent Sources
57
6.1
B source (ASRC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
57
6.2
E source (non-linear voltage source)* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
60
6.3
G source (non-linear current source)* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
61
7 Transmission Lines
7.1
7.2
Lossy Transmission Lines
7.2.1
7.3
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
63
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
63
Lossy Transmission Line Model (LTRA) . . . . . . . . . . . . . . . . . . . . . . . .
64
Uniform Distributed RC Lines
7.3.1
7.4
63
Lossless Transmission Lines
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
65
Uniform Distributed RC Model (URC) . . . . . . . . . . . . . . . . . . . . . . . . .
65
KSPICE Lossy Transmission Lines
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
65
7.4.1
Single Lossy Transmission Line (TXL) . . . . . . . . . . . . . . . . . . . . . . . . .
66
7.4.2
Coupled Multiconductor Line (CPL) . . . . . . . . . . . . . . . . . . . . . . . . . .
66
CONTENTS
9
8 DIODEs
69
8.1
Junction Diodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
69
8.2
Diode Model (D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
69
8.3
Diode Equations
70
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9 BJTs
75
9.1
Bipolar Junction Transistors (BJTs)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.2
BJT Models (NPN/PNP)
75
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
75
10 JFETs
79
10.1 Junction Field-Eect Transistors (JFETs) . . . . . . . . . . . . . . . . . . . . . . . . . . .
79
10.2 JFET Models (NJF/PJF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
79
10.2.1 Model by Parker and Skellern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
79
10.2.2 Modi ed Parker Skellern model . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
80
11 MESFETs
81
11.1 MESFETs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
81
11.2 MESFET Models (NMF/PMF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
81
11.2.1 Model by Statz e.a. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
81
11.2.2 Model by Ytterdal e.a. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
82
11.2.3 hfet1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
82
11.2.4 hfet2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
82
12 MOSFETs
83
12.1 MOSFET devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
83
12.2 MOSFET models (NMOS/PMOS)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
84
12.2.1 MOS Level 1
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
84
12.2.2 MOS Level 2
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
84
12.2.3 MOS Level 3
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
84
12.2.4 MOS Level 6
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
84
12.2.5 Notes on Level 1-6 models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
84
12.2.6 BSIM Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
87
12.2.7 BSIM1 model (level 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
87
12.2.8 BSIM2 model (level 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
89
12.2.9 BSIM3 model (levels 8, 49)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
89
12.2.10 BSIM4 model (levels 14, 54) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
89
12.2.11 EKV model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
90
12.2.12 BSIMSOI models (levels 10, 58, 55, 56, 57)
. . . . . . . . . . . . . . . . . . . . . .
90
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
90
12.2.13 SOI3 model (level 62)
13 Behavioral Modeling
91
13.1 Code Model Element & .MODEL Cards . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.2 Analog Models
91
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
94
13.2.1 Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
94
13.2.2 Summer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
95
13.2.3 Multiplier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
96
13.2.4 Divider
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
97
13.2.5 Limiter
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
98
13.2.6 Controlled Limiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
99
13.2.7 PWL Controlled Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
101
13.2.8 Analog Switch
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
102
13.2.9 Zener Diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
103
13.2.10 Current Limiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
104
13.2.11 Hysteresis Block
106
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.2.12 Dierentiator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
108
13.2.13 Integrator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
109
13.2.14 S-Domain Transfer Function
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
110
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
112
13.2.16 Inductive Coupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
113
13.2.15 Slew Rate Block
CONTENTS
10
13.2.17 Magnetic Core
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.2.18 Controlled Sine Wave Oscillator
. . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.2.19 Controlled Triangle Wave Oscillator
. . . . . . . . . . . . . . . . . . . . . . . . . .
114
116
117
13.2.20 Controlled Square Wave Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . .
118
13.2.21 Controlled One-Shot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
119
13.2.22 Capacitance Meter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
121
13.2.23 Inductance Meter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
122
13.3 Hybrid Models
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.3.1 Digital-to-Analog Node Bridge
13.3.2 Analog-to-Digital Node Bridge
13.3.3 Controlled Digital Oscillator
13.4.4 Nand
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
124
125
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
126
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
126
13.4.2 Inverter
13.4.3 And
122
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.4 Digital Models
13.4.1 Buer
122
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
127
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
127
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
128
13.4.5 Or . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
129
13.4.6 Nor
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
130
13.4.7 Xor
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
130
13.4.8 Xnor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
131
13.4.9 Tristate
132
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.4.10 Pullup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
133
13.4.11 Pulldown
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
134
13.4.12 D Flip Flop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
134
13.4.13 JK Flip Flop
136
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.4.14 Toggle Flip Flop
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
138
13.4.15 Set-Reset Flip Flop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
139
13.4.16 D Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
141
13.4.17 Set-Reset Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
143
13.4.18 State Machine
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.4.19 Frequency Divider
13.4.20 RAM
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
145
147
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
148
13.4.21 Digital Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
150
13.5 Prede ned Node Types
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.5.1 Real Node Type
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
152
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
152
13.5.2 Int Node Type
14 Verilog A Device models
152
153
14.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
153
14.2 adms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
153
14.3 How to generate a *.va model for ngspice
153
14.4 How to integrate a *.va model into ngspice
. . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . .
14.4.1 Adding admsXml to your build environment
. . . . . . . . . . . . . . . . . . . . .
15 Mixed-Level Simulation (ngspice with TCAD)
153
153
155
15.1 Cider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
155
15.2 GSS, Genius . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
156
16 Analyses and Output Control
157
16.1 Simulator Variables (.options) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16.1.1 General Options
157
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
157
16.1.2 DC Solution Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
158
16.1.3 Transient Analysis Options
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
159
16.1.4 MOSFET Speci c options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
160
16.1.5 Transimission Lines Speci c Options . . . . . . . . . . . . . . . . . . . . . . . . . .
160
16.1.6 Precedence of option and .options commands
. . . . . . . . . . . . . . . . . . . . .
160
16.2 Initial Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
161
16.2.1 .NODESET: Specify Initial Node Voltage Guesses
. . . . . . . . . . . . . . . . . .
161
16.2.2 .IC: Set Initial Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
161
CONTENTS
11
16.3 Analyses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16.3.1 .AC: Small-Signal AC Analysis
16.3.2 .DC: DC Transfer Function
161
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
162
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
162
16.3.3 .DISTO: Distortion Analysis
16.3.4 .NOISE: Noise Analysis
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16.3.5 .OP: Operating Point Analysis
16.3.6 .PZ: Pole-Zero Analysis
161
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
163
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
163
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
164
16.3.7 .SENS: DC or Small-Signal AC Sensitivity Analysis
16.3.8 .TF: Transfer Function Analysis
16.3.9 .TRAN: Transient Analysis
. . . . . . . . . . . . . . . . .
164
. . . . . . . . . . . . . . . . . . . . . . . . . . . .
165
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
165
16.3.10 .MEAS: Measurements after Op, Ac and Transient Analysis . . . . . . . . . . . . .
165
16.4 Batch Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
170
16.4.1 .SAVE: Name vector(s) to be saved in raw le . . . . . . . . . . . . . . . . . . . . .
170
16.4.2 .PRINT Lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
170
16.4.3 .PLOT Lines
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
171
16.4.4 .FOUR: Fourier Analysis of Transient Analysis Output . . . . . . . . . . . . . . . .
171
16.4.5 .PROBE: Name vector(s) to be saved in raw le
. . . . . . . . . . . . . . . . . . .
171
16.4.6 par('expression'): Algebraic expressions for output . . . . . . . . . . . . . . . . . .
172
17 Starting ngspice
173
17.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
173
17.2 Where to obtain ngspice . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
173
17.3 Command line options for starting ngspice and ngnutmeg
. . . . . . . . . . . . . . . . . .
174
17.4 Starting options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
175
17.4.1 Batch mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
175
17.4.2 Interactive mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
175
17.4.3 Interactive mode with control le or control section . . . . . . . . . . . . . . . . . .
175
17.5 Standard con guration le spinit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
176
17.6 User de ned con guration le .spiceinit
. . . . . . . . . . . . . . . . . . . . . . . . . . . .
177
17.7 Environmental variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
177
17.7.1 Ngspice speci c variables
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
177
17.7.2 Common environment variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
177
17.8 Memory usage
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
177
17.9 Simulation time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
178
17.10Ngspice on multi-core processors using OpenMP
. . . . . . . . . . . . . . . . . . . . . . .
178
17.10.1 Introduction
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
178
17.10.2 Some results
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
179
17.10.3 Usage
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
179
17.10.4 Literature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
179
17.11Server mode option -s
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17.12Ngspice control via input, output fos
180
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
180
17.13REPORTING ERRORS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
181
18 Interactive Interpreter
183
18.1 Expressions, Functions, and Constants . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
183
18.2 Plots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
185
18.3 Command Interpretation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
185
18.4 Commands
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
186
18.4.1 Ac*: Perform an AC, small-signal frequency response analysis . . . . . . . . . . . .
186
18.4.2 Alias: Create an alias for a command
186
. . . . . . . . . . . . . . . . . . . . . . . . .
18.4.3 Alter*: Change a device or model parameter
18.4.4 Altermod*: Change a model parameter
. . . . . . . . . . . . . . . . . . . . .
186
. . . . . . . . . . . . . . . . . . . . . . . .
187
18.4.5 Asciiplot: Plot values using old-style character plots
. . . . . . . . . . . . . . . . .
187
18.4.6 Aspice*: Asynchronous ngspice run . . . . . . . . . . . . . . . . . . . . . . . . . . .
187
18.4.7 Bug: Mail a bug report
18.4.8 Cd: Change directory
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
187
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
187
18.4.9 Compose: Compose a vector
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
188
18.4.10 Destroy: Delete a data set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
188
18.4.11 Dc*: Perform a DC-sweep analysis . . . . . . . . . . . . . . . . . . . . . . . . . . .
188
CONTENTS
12
18.4.12 De ne: De ne a function
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
188
18.4.13 Deftype: De ne a new type for a vector or plot . . . . . . . . . . . . . . . . . . . .
188
18.4.14 Delete*: Remove a trace or breakpoint . . . . . . . . . . . . . . . . . . . . . . . . .
189
18.4.15 Di: Compare vectors
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
189
18.4.16 Display: List known vectors and types . . . . . . . . . . . . . . . . . . . . . . . . .
189
18.4.17 Echo: Print text
189
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18.4.18 Edit*: Edit the current circuit
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18.4.19 FFT: fast Fourier transform of the input vector(s)
. . . . . . . . . . . . . . . . . .
189
189
18.4.20 Fourier: Perform a fourier transform . . . . . . . . . . . . . . . . . . . . . . . . . .
191
18.4.21 Gnuplot: Graphics output via Gnuplot . . . . . . . . . . . . . . . . . . . . . . . . .
191
18.4.22 Hardcopy: Save a plot to a le for printing
191
. . . . . . . . . . . . . . . . . . . . . .
18.4.23 Help: Print summaries of Ngspice commands
. . . . . . . . . . . . . . . . . . . . .
191
18.4.24 History: Review previous commands . . . . . . . . . . . . . . . . . . . . . . . . . .
191
18.4.25 Iplot*: Incremental plot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
191
18.4.26 Jobs*: List active asynchronous ngspice runs
18.4.27 Let: Assign a value to a vector
. . . . . . . . . . . . . . . . . . . . .
192
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
192
18.4.28 Linearize: Interpolate to a linear scale . . . . . . . . . . . . . . . . . . . . . . . . .
192
18.4.29 Listing*: Print a listing of the current circuit
192
. . . . . . . . . . . . . . . . . . . . .
18.4.30 Load: Load raw le data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
193
18.4.31 Meas*: Mesurements on simulation data . . . . . . . . . . . . . . . . . . . . . . . .
193
18.4.32 Noise*: Noise analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
193
18.4.33 Op*: Perform an operating point analysis . . . . . . . . . . . . . . . . . . . . . . .
193
18.4.34 Option*: Set a ngspice option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
193
18.4.35 Plot: Plot values on the display . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
194
18.4.36 Print: Print values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
195
18.4.37 Quit: Leave Ngspice or Nutmeg . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
195
18.4.38 Rehash: Reset internal hash tables . . . . . . . . . . . . . . . . . . . . . . . . . . .
195
18.4.39 Reset*: Reset an analysis
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
195
18.4.40 Reshape: Alter the dimensionality or dimensions of a vector . . . . . . . . . . . . .
195
18.4.41 Resume*: Continue a simulation after a stop
. . . . . . . . . . . . . . . . . . . . .
196
18.4.42 Rspice*: Remote ngspice submission . . . . . . . . . . . . . . . . . . . . . . . . . .
196
18.4.43 Run*: Run analysis from the input le . . . . . . . . . . . . . . . . . . . . . . . . .
196
18.4.44 Rusage: Resource usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
196
18.4.45 Save*: Save a set of outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
197
18.4.46 Sens*: Run a sensitivity analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . .
198
18.4.47 Set: Set the value of a variable
198
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18.4.48 Setcirc*: Change the current circuit
. . . . . . . . . . . . . . . . . . . . . . . . . .
18.4.49 Setplot: Switch the current set of vectors
198
. . . . . . . . . . . . . . . . . . . . . . .
198
18.4.50 Setscale: Set the scale vector for the current plot . . . . . . . . . . . . . . . . . . .
198
18.4.51 Settype: Set the type of a vector
. . . . . . . . . . . . . . . . . . . . . . . . . . . .
18.4.52 Shell: Call the command interpreter
. . . . . . . . . . . . . . . . . . . . . . . . . .
198
199
18.4.53 Shift: Alter a list variable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
199
18.4.54 Show*: List device state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
199
18.4.55 Showmod*: List model parameter values . . . . . . . . . . . . . . . . . . . . . . . .
199
18.4.56 Source: Read a ngspice input le . . . . . . . . . . . . . . . . . . . . . . . . . . . .
200
18.4.57 Spec: Create a frequency domain plot
200
. . . . . . . . . . . . . . . . . . . . . . . . .
18.4.58 Status*: Display breakpoint information . . . . . . . . . . . . . . . . . . . . . . . .
200
18.4.59 Step*: Run a xed number of timepoints
200
. . . . . . . . . . . . . . . . . . . . . . .
18.4.60 Stop*: Set a breakpoint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
200
18.4.61 Strcmp: Compare two strings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
201
18.4.62 Sysinfo*: Print system information . . . . . . . . . . . . . . . . . . . . . . . . . . .
201
18.4.63 Tf*: Run a Transfer Function analysis . . . . . . . . . . . . . . . . . . . . . . . . .
201
18.4.64 Trace*: Trace nodes
202
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18.4.65 Tran*: Perform a transient analysis
. . . . . . . . . . . . . . . . . . . . . . . . . .
202
18.4.66 Transpose: Swap the elements in a multi-dimensional data set . . . . . . . . . . . .
202
18.4.67 Unalias: Retract an alias
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
203
18.4.68 Unde ne: Retract a de nition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
203
18.4.69 Unlet: Delete the speci ed vector(s)
203
. . . . . . . . . . . . . . . . . . . . . . . . . .
CONTENTS
13
18.4.70 Unset: Clear a variable
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
203
18.4.71 Version: Print the version of ngspice . . . . . . . . . . . . . . . . . . . . . . . . . .
203
18.4.72 Where*: Identify troublesome node or device
. . . . . . . . . . . . . . . . . . . . .
204
18.4.73 Wrdata: Write data to a le . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
204
18.4.74 Write: Write data to a le . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
205
18.4.75 Xgraph: use the xgraph(1) program for plotting.
. . . . . . . . . . . . . . . . . . .
205
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
205
18.5.1 While - End . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
205
18.5 Control Structures
18.5.2 Repeat - End . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
205
18.5.3 Dowhile - End
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
205
18.5.4 Foreach - End . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
206
18.5.5 If - Then - Else . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
206
18.5.6 Label
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
206
18.5.7 Goto . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
206
18.5.8 Continue
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
206
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
207
18.5.9 Break
18.6 Variables
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
207
18.7 Scripts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
210
18.7.1 Variables
18.7.2 Vectors
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
211
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
211
18.7.3 Commands
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
211
18.7.4 control structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
211
18.7.5 Example script 'spectrum' . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
214
18.7.6 Example script for random numbers
. . . . . . . . . . . . . . . . . . . . . . . . . .
216
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
216
18.8 Monte-Carlo Simulation
18.9 MISCELLANEOUS (old stu, has to be checked for relevance)
. . . . . . . . . . . . . . .
218
18.10Bugs (old stu, has to be checked for relevance) . . . . . . . . . . . . . . . . . . . . . . . .
218
19 Graphical User Interfaces
19.1 MS Windows
19.2 LINUX
219
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
219
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
221
19.3 Integration with CAD software and third party GUIs . . . . . . . . . . . . . . . . . . . .
19.3.1 KJWaves
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19.3.2 GNU Spice GUI
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
221
221
222
19.3.3 XCircuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
222
19.3.4 GEDA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
222
20 TCLspice
223
20.1 tclspice framework
20.2 spicetoblt
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
223
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
223
20.3 Running TCLspice . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
223
20.4 examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
224
20.4.1 Active capacitor measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
224
20.4.2 Optimisation of a linearization circuit for a Thermistor
. . . . . . . . . . . . . . .
226
20.4.3 testbench3.tcl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
226
20.4.4 Progressive display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
229
20.5 Compiling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
229
21 Example Circuits
231
21.1 AC coupled transistor ampli er . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
233
21.2 Dierential Pair . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
236
21.3 MOSFET Characterization
236
21.4 RTL Inverter
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
21.5 Four-Bit Binary Adder (Bipolar)
236
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
237
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
238
21.7 Transmission-Line Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
239
21.6 Four-Bit Binary Adder (MOS)
CONTENTS
14
22 Notes
241
22.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
241
22.2 Acronyms and Abbreviations
241
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
II XSPICE Software User's Manual
245
23 XSPICE Basics
247
23.1 The XSPICE Code Model Subsystem
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
247
23.2 XSPICE Top-Level Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
247
24 Execution Procedures
249
24.1 Simulation and Modeling Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
24.1.1 Describing the Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
24.2 Circuit Description Syntax
249
249
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
254
24.2.1 XSPICE Syntax Extensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
254
25 Code Model Data TypeDe nitions
255
26 Example circuits
257
26.1 Ampli er with XSPICE model gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
257
26.2 XSPICE advanced usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
258
26.2.1 Circuit example C3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
258
26.2.2 How to create code models
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
260
26.2.3 Running example C3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
262
27 Code Models and User-De ned Nodes
265
27.1 Creating Code Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
265
27.2 Creating User-De ned Nodes
266
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
27.3 Compiling and Linking the Simulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
267
27.4 Interface Speci cation File
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
267
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
268
27.4.1 The Name Table
27.4.2 The Port Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
269
27.4.3 The Parameter Table
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
270
27.4.4 Static Variable Table
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
271
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
272
27.5 Model De nition File
27.5.1 Macros
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
272
27.5.2 Function Library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
278
27.6 User-De ned Node De nition File
27.6.1 Macros
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
284
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
285
27.6.2 Function Library
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
27.6.3 Example UDN De nition File
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28 Error Messages
285
287
291
28.1 Preprocessor Error Messages
28.2 Simulator Error Messages
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28.3 Code Model Error Messages
28.3.1 Code Model aswitch
28.3.2 Code Model climit
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
291
294
295
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
295
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
295
28.3.3 Code Model core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
296
28.3.4 Code Model d_osc
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
296
28.3.5 Code Model d_source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
296
28.3.6 Code Model d_state
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
297
28.3.7 Code Model oneshot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
297
28.3.8 Code Model pwl
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28.3.9 Code Model s_xfer
28.3.10 Code Model sine
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28.3.11 Code Model square
297
298
298
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
298
28.3.12 Code Model triangle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
299
CONTENTS
15
III CIDER
301
29 CIDER User's Manual
303
29.1 SPECIFICATION
303
29.1.1 Examples
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
304
29.2 BOUNDARY, INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
304
29.2.1 DESCRIPTION
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
29.2.2 PARAMETERS
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
305
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
305
29.3 COMMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
305
29.2.3 EXAMPLES
29.3.1 DESCRIPTION
29.3.2 EXAMPLES
29.4 CONTACT
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
305
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
305
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
29.4.1 DESCRIPTION
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
29.4.2 PARAMETERS
29.4.3 EXAMPLES
29.4.4 SEE ALSO
304
306
306
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
306
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
306
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
306
29.5 DOMAIN, REGION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
306
29.5.1 DESCRIPTION
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
29.5.2 PARAMETERS
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
307
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
307
29.5.3 EXAMPLES
29.5.4 SEE ALSO
29.6 DOPING
306
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
307
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
307
29.6.1 DESCRIPTION
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
29.6.2 PARAMETERS
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
310
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
310
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
311
29.6.3 EXAMPLES
29.6.4 SEE ALSO
29.7 ELECTRODE
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
29.7.1 DESCRIPTION
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
29.7.2 PARAMETERS
29.7.3 EXAMPLES
29.7.4 SEE ALSO
29.8 END
311
311
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
311
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
311
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
312
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
29.8.1 DESCRIPTION
29.9 MATERIAL
307
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
312
312
312
29.9.1 DESCRIPTION
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
29.9.2 PARAMETERS
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
313
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
313
29.9.3 EXAMPLES
29.9.4 SEE ALSO
29.10METHOD
312
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
313
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
313
29.10.1 DESCRIPTION
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IV Appendices
315
30 Model and Device Parameters
30.1 Elementary Devices
313
317
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
318
30.1.1 Resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
318
30.1.2 Capacitor - Fixed capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
319
30.1.3 Inductor - Fixed inductor
320
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
30.1.4 Mutual - Mutual Inductor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
321
30.2 Voltage and current sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
322
30.2.1 ASRC - Arbitrary source
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
322
30.2.2 Isource - Independent current source . . . . . . . . . . . . . . . . . . . . . . . . . .
323
30.2.3 Vsource - Independent voltage source . . . . . . . . . . . . . . . . . . . . . . . . . .
324
30.2.4 CCCS - Current controlled current source . . . . . . . . . . . . . . . . . . . . . . .
325
30.2.5 CCVS - Current controlled voltage source . . . . . . . . . . . . . . . . . . . . . . .
325
30.2.6 VCCS - Voltage controlled current source
. . . . . . . . . . . . . . . . . . . . . . .
326
30.2.7 VCVS - Voltage controlled voltage source
. . . . . . . . . . . . . . . . . . . . . . .
326
CONTENTS
16
30.3 Transmission Lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
327
30.3.1 CplLines - Simple Coupled Multiconductor Lines . . . . . . . . . . . . . . . . . . .
327
30.3.2 LTRA - Lossy transmussion line
328
. . . . . . . . . . . . . . . . . . . . . . . . . . . .
30.3.3 Tranline - Lossless transmission line
. . . . . . . . . . . . . . . . . . . . . . . . . .
329
30.3.4 TransLine - Simple Lossy Transmission Line . . . . . . . . . . . . . . . . . . . . . .
330
30.3.5 URC - Uniform R. C. line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
331
30.4 BJTs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
30.4.1 BJT - Bipolar Junction Transistor
. . . . . . . . . . . . . . . . . . . . . . . . . . .
332
332
30.4.2 BJT - Bipolar Junction Transistor Level 2 . . . . . . . . . . . . . . . . . . . . . . .
335
30.4.3 VBIC - Vertical Bipolar Inter-Company Model
338
. . . . . . . . . . . . . . . . . . . .
30.5 MOSFETs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
342
30.5.1 MOS1 - Level 1 MOSfet model with Meyer capacitance model
. . . . . . . . . . .
342
30.5.2 MOS2 - Level 2 MOSfet model with Meyer capacitance model
. . . . . . . . . . .
345
30.5.3 MOS3 - Level 3 MOSfet model with Meyer capacitance model
. . . . . . . . . . .
348
30.5.4 MOS6 - Level 6 MOSfet model with Meyer capacitance model
. . . . . . . . . . .
351
. . . . . . . . . . . . . . . . . . . . . . .
354
30.5.5 MOS9 - Modi ed Level 3 MOSfet model
30.5.6 BSIM1 - Berkeley Short Channel IGFET Model
. . . . . . . . . . . . . . . . . . .
357
30.5.7 BSIM2 - Berkeley Short Channel IGFET Model
. . . . . . . . . . . . . . . . . . .
359
30.5.8 BSIM3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
362
30.5.9 BSIM4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
362
31 Compilation notes
363
31.1 Ngspice Installation under LINUX (and other 'UNIXes') . . . . . . . . . . . . . . . . . . .
31.1.1 Prerequisites
363
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
363
31.1.2 Install from CVS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
363
31.1.3 Basic Install . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
364
31.1.4 Advanced Install
364
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
31.1.5 Compilation using an user de ned directory tree for object les
31.1.6 Compilers and Options
. . . . . . . . . .
365
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
365
31.1.7 Compiling For Multiple Architectures
. . . . . . . . . . . . . . . . . . . . . . . . .
366
31.1.8 Installation Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
366
31.1.9 Optional Features
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
366
31.1.10 Specifying the System Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
366
31.1.11 Sharing Defaults
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
366
31.1.12 Operation Controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
366
31.2 NGSPICE COMPILATION UNDER WINDOWS OS
31.2.1 How to make ngspice with MINGW and MSYS
. . . . . . . . . . . . . . . . . . . .
367
. . . . . . . . . . . . . . . . . . .
367
. . . . . . . . . . . . . . . . . . . . . . . . .
367
31.2.3 make ngspice with MS Visual Studio 2008 . . . . . . . . . . . . . . . . . . . . . . .
368
31.2.2 64 Bit executables with MINGW-w64
31.2.4 make ngspice with pure CYGWIN
. . . . . . . . . . . . . . . . . . . . . . . . . . .
368
31.2.5 make ngspice with CYGWIN and external MINGW32 . . . . . . . . . . . . . . . .
370
.
370
31.3 REPORTING ERRORS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
31.2.6 make ngspice with CYGWIN and internal MINGW32 (use con g.h made above)
370
Prefaces
Preface to the rst edition
This manual has been assembled from dierent sources:
1. The spice3f5 manual,
2. the Xspice user's manual,
3. the CIDER user's manual
and some original material needed to describe the new features and the newly implemented models. This
cut and paste approach, while not being ortodox, allowed ngspice to have a full manual in a fraction of
the time that writing a completely new text would have required. The use of LaTex and Lyx instead
of TeXinfo, which was the original encoding for the manual, further helped to reduce the writing eort
and improved the quality of the result, at the expense of an online version of the manual but, due to the
complexity of the software I hardly think that users will ever want to read an online text version.
In writing this text I followed the cut of spice3f5 manual, both in the chapter sequence and presentation
of material, mostly because that was already the user manual of spice.
Ngspice is an open source software, users can download the source code, compile, and run it. This
manual has an entire chapter describing program compilation and available options to help users in
building ngspice (see chapt. 31). The source package already comes with all safe options enabled by
default, and activating the others can produce unpredictable results and thus is recommended to expert
users only. This is the rst ngspice manual and I have removed all the historical material that described
the dierences between ngspice and spice3, since it was of no use for the user and not so useful for the
developer who can look for it in the Changelogs of in the revision control system.
I want to acknowledge the work dome Emmanuel Rouat and Arno W. Peters for converting to TEXinfo
the original spice3f documentation, their eort gave ngspice users the only available documentation that
described the changes for many years.
A good source of ideas for this manual comes from the online
spice3f manual written by Charles D.H. Williams (Spice3f5 User Guide), constantly updated and useful
for some insight that he gives in it.
As always, errors, omissions and unreadable phrases are only my fault.
Paolo Nenzi
Roma, March 24th 2001
Indeed. At the end of the day, this is engineering, and one learns to live
within the limitations of the tools.
Kevin Aylward , Warden of the Kings Ale
Preface to the actual edition (as of 2010)
Due to the wealth of new material and options in ngspice the actual order of chapters has been revised.
Several new chapters have been added. Thy lyx text processors has allowed adding internal cross references. The pdf format has become the standard format for distribution of the manual. Within each
new ngspice distribution (starting with ngspice-21) a manual edition is provided re ecting the ngspice
status at the time of distribution. At the same time, located at ngspice manuals, the manual is constantly
updated. Every new ngspice feature should enter this manual as soon as it has been made available in
the CVS source code.
Holger Vogt
Mülheim, 2010
17
18
CONTENTS
Acknowledgments
ngspice
Spice was originally written at The University of California at Berkeley (USA).
Since then, there have been many people working on the software, most of them releasing patches to
the original code through the Internet.
The following people have contributed in some way:
Vera Albrecht,
Cecil Aswell,
Giles C. Billingsley,
Phil Barker,
Steven Borley,
Stuart Brorson,
Mansun Chan,
Wayne A. Christopher,
Al Davis,
Glao S. Dezai,
Jon Engelbert,
Daniele Foci,
Noah Friedman,
David A. Gates,
Alan Gillespie,
John Heidemann,
Jerey M. Hsu,
JianHui Huang,
S. Hwang,
Chris Inbody,
Gordon M. Jacobs,
Min-Chie Jeng,
Beorn Johnson,
Stefan Jones,
Kenneth H. Keller,
Robert Larice,
Mathew Lew,
Robert Lindsell,
Weidong Liu,
Kartikeya Mayaram,
Richard D. McRoberts,
Manfred Metzger,
Wolfgang Muees,
Paolo Nenzi,
Gary W. Ng,
Hong June Park,
Arno Peters,
Serban-Mihai Popescu,
Georg Post,
Thomas L. Quarles,
Emmanuel Rouat,
19
CONTENTS
20
Jean-Marc Routure,
Jaijeet S. Roychowdhury,
Lionel Sainte Cluque,
Takayasu Sakurai,
Amakawa Shuhei,
Kanwar Jit Singh,
Bill Swartz,
Hitoshi Tanaka,
Steve Tell,
Andrew Tuckey,
Andreas Unger,
Holger Vogt,
Dietmar Warning,
Michael Widlok,
Charles D.H. Williams,
Antony Wilson,
and many others...
If someone helped in the development and has not been inserted in this list then this omission was unintentional. If you feel you should be on this list then please write to .
Do not be shy, we would like to make a list as complete as possible.
XSPICE
The XSPICE simulator is based on the SPICE3 program developed by the Electronics Research Laboratory, Department of Electrical Engineering and Computer Sciences, University of California at Berkeley.
The authors of XSPICE gratefully acknowledge UC Berkeley's development and distribution of this software, and their licensing policies which promote further improvements to simulation technology.
We also gratefully acknowledge the participation and support of our U.S. Air Force sponsors, the Aeronautical Systems Center and the Warner Robins Air Logistics Command, without which the development
of XSPICE would not have been possible.
Chapter 1
Introduction
Ngspice is a general-purpose circuit simulation program for nonlinear and linear analyses. Circuits may
contain resistors, capacitors, inductors, mutual inductors, independent or dependent voltage and current
sources, lossless and lossy transmission lines, switches, uniform distributed RC lines, and the ve most
common semiconductor devices: diodes, BJTs, JFETs, MESFETs, and MOSFETs.
Ngspice is an update of Spice3f5, the last Berkeley's release of Spice3 simulator family. Ngspice is
being developed to include new features to existing Spice3f5 and to x its bugs. Improving a complex
software like a circuit simulator is a very hard task and, while some improvements have been made, most
of the work has been done on bug xing and code refactoring.
Ngspice has built-in models for the semiconductor devices, and the user need specify only the pertinent
model parameter values. There are three models for bipolar junction transistors, all based on the integralcharge model of Gummel and Poon; however, if the Gummel-Poon parameters are not speci ed, the basic
model (BJT) reduces to the simpler Ebers-Moll model.
In either case and in either models, charge
storage eects, ohmic resistances, and a current-dependent output conductance may be included. The
second bipolar model BJT2 adds dc current computation in the substrate diode. The third model (VBIC)
contains further enhancements for advanced bipolar devices.
The semiconductor diode model can be used for either junction diodes or Schottky barrier diodes.
There are two models for JFET: the rst (JFET) is based on the model of Shichman and Hodges,
the second (JFET2) is based on the Parker-Skellern model.
All the original six MOSFET models are
implemented: MOS1 is described by a square-law I-V characteristic, MOS2 [1] is an analytical model,
while MOS3 [1] is a semi-empirical model; MOS6 [2] is a simple analytic model accurate in the short
channel region; MOS9, a physics based analytical model for electrical circuit simulation and design for
analogue applications (NXP MOS model 9 web page); BSIM 1 [3, 4]; BSIM2 [5] are the old BSIM
(Berkeley Short-channel IGFET Model) models. MOS2, MOS3, and BSIM include second-order eects
such as channel-length modulation, subthreshold conduction, scattering-limited velocity saturation, smallsize eects, and charge controlled capacitances. The recent MOS models for submicron devices are the
BSIM3 (Berkeley BSIM3 web page) and BSIM4 (Berkeley BSIM4 web page) models. Silicon-on-insulator
MOS transistors are described by the SOI models from the BSIMSOI family (Berkeley BSIMSOI web
page) and the STAG [18] one. There is partial support for a couple of HFET models and one model for
MESA devices.
Ngspice supports mixed-level simulation and provides a direct link between technology parameters and
circuit performance. A mixed-level circuit and device simulator can provide greater simulation accuracy
than a stand-alone circuit or device simulator by numerically modeling the critical devices in a circuit.
Compact models can be used for noncritical devices. The mixed-level extensions to ngspice are two:
CIDER: a mixed-level circuit and device simulator integrated into ngspice code. CIDER was originally the name of the mixed-level extension made to spice3f5.
GSS: GSS (now called GENIUS) TCAD is a 2D simulator developed independently from ngspice.
The device simulator itself is free and not included into ngspice, but a socket interface is provided.
Ngspice supports mixed-signal simulation through the integration of XSPICE code into it. Xspice software, developed as an extension to Spice3C1 from GeorgiaTech, has been ported to ngspice to provide
board level and mixed-signal simulation.
New devices can be added to ngspice by two means: the xspice old code-model interface and the new
ADMS interface based on Verilog-A and XML.
21
CHAPTER 1. INTRODUCTION
22
Previously computed states can be loaded into the program to provide accurate initial guesses for
subsequent analysis. Finally, numerous small bugs have been discovered and xed, and the program has
been ported to a wider variety of computing platforms.
1.1
Simulation Algorithms
Computer-based circuit simulation is often used as a tool by designers, test engineers, and others who
want to analyze the operation of a design without examining the physical circuit. Simulation allows you
to change quickly the parameters of many of the circuit elements to determine how they aect the circuit
response. Often it is di cult or impossible to change these parameters in a physical circuit.
However, to be practical, a simulator must execute in a reasonable amount of time.
The key to
e cient execution is choosing the proper level of modeling abstraction for a given problem. To support
a given modeling abstraction, the simulator must provide appropriate algorithms.
Historically, circuit simulators have supported either an analog simulation algorithm or a digital
simulation algorithm.
Ngspice inherits the XSPICE framework and supports both analog and digital
algorithms and is a mixed-mode simulator.
1.1.1 Analog Simulation
Analog simulation focuses on the linear and non-linear behavior of a circuit over a continuous time
or frequency interval.
The circuit response is obtained by iteratively solving Kirchho 's Laws for the
circuit at time steps selected to ensure the solution has converged to a stable value and that numerical
approximations of integrations are su ciently accurate. Since Kirchho 's laws form a set of simultaneous
equations, the simulator operates by solving a matrix of equations at each time point.
This matrix
processing generally results in slower simulation times when compared to digital circuit simulators.
The response of a circuit is a function of the applied sources. Ngspice oers a variety of source types
including DC, sinewave, and pulse.
of simulation to be run.
In addition to specifying sources, the user must de ne the type
This is termed the mode of analysis.
AC analysis, and transient analysis.
Analysis modes include DC analysis,
For DC analysis, the time-varying behavior of reactive elements
is neglected and the simulator calculates the DC solution of the circuit.
Swept DC analysis may also
be accomplished with ngspice. This is simply the repeated application of DC analysis over a range of
DC levels for the input sources. For AC analysis, the simulator determines the response of the circuit,
including reactive elements to small-signal sinusoidal inputs over a range of frequencies. The simulator
output in this case includes amplitudes and phases as a function of frequency.
For transient analysis,
the circuit response, including reactive elements, is analyzed to calculate the behavior of the circuit as a
function of time.
1.1.2 Digital Simulation
Digital circuit simulation diers from analog circuit simulation in several respects. A primary dierence
is that a solution of Kirchho 's laws is not required. Instead, the simulator must only determine whether
a change in the logic state of a node has occurred and propagate this change to connected elements. Such
a change is called an event.
When an event occurs, the simulator examines only those circuit elements that are aected by the
event. As a result, matrix analysis is not required in digital simulators. By comparison, analog simulators
must iteratively solve for the behavior of the entire circuit because of the forward and reverse transmission
properties of analog components. This dierence results in a considerable computational advantage for
digital circuit simulators, which is re ected in the signi cantly greater speed of digital simulations.
1.1.3 Mixed-Mode Simulation
Modern circuits often contain a mix of analog and digital circuits. To simulate such circuits e ciently
and accurately a mix of analog and digital simulation techniques is required. When analog simulation
algorithms are combined with digital simulation algorithms, the result is termed mixed-mode simulation.
Two basic methods of implementing mixed-mode simulation used in practice are the native mode
and glued mode approaches. Native mode simulators implement both an analog algorithm and a digital
algorithm in the same executable. Glued mode simulators actually use two simulators, one of which is
analog and the other digital. This type of simulator must de ne an input/output protocol so that the
1.1. SIMULATION ALGORITHMS
23
two executables can communicate with each other eectively. The communication constraints tend to
reduce the speed, and sometimes the accuracy, of the complete simulator. On the other hand, the use of
a glued mode simulator allows the component models developed for the separate executables to be used
without modi cation.
Ngspice is a native mode simulator providing both analog and event-based simulation in the same
executable. The underlying algorithms of ngspice (coming from XSPICE and its Code Model Subsystem)
allow use of all the standard SPICE models, provide a pre-de ned collection of the most common analog
and digital functions, and provide an extensible base on which to build additional models.
User-De ned Nodes
Ngspice supports creation of User-De ned Node types. User-De ned Node types allow you to specify
nodes that propagate data other than voltages, currents, and digital states.
Like digital nodes, User-
De ned Nodes use event-driven simulation, but the state value may be an arbitrary data type. A simple
example application of User-De ned Nodes is the simulation of a digital signal processing lter algorithm.
In this application, each node could assume a real or integer value. More complex applications may de ne
types that involve complex data such as digital data vectors or even non-electronic data.
Ngspice digital simulation is actually implemented as a special case of this User-De ned Node capability where the digital state is de ned by a data structure that holds a Boolean logic state and a strength
value.
1.1.4 Mixed-Level Simulation
Ngspice can simulate numerical device models for diodes and transistors in two dierent ways, either
through the integrated DSIM simulator or interfacing to GSS TCAD system. DSIM is an internal Cbased device simulator which is part of the CIDER simulator, the mixed-level simulator based on spice3f5.
CIDER within ngspice provides circuit analyses, compact models for semiconductor devices, and one- or
two-dimesional numerical device models.
CIDER (DSIM)
DSIM provides accurate, one- and two-dimensional numerical device models based on the solution of
Poisson's equation, and the electron and hole current-continuity equations. DSIM incorporates many of
the same basic physical models found in the Stanford two-dimensional device simulator PISCES. Input
to CIDER consists of a SPICE-like description of the circuit and its compact models, and PISCES-like
descriptions of the structures of numerically modeled devices. As a result, CIDER should seem familiar
to designers already accustomed to these two tools. CIDER is based on the mixed-level circuit and device
simulator CODECS, and is a replacement for this program. The basic algorithms of the two programs
are the same. Some of the dierences between CIDER and CODECS are described below. The CIDER
input format has greater exibility and allows increased access to physical model parameters.
New
physical models have been added to allow simulation of state-of-the-art devices. These include transverse
eld mobility degradation important in scaled-down MOSFETs and a polysilicon model for poly-emitter
bipolar transistors. Temperature dependence has been included over the range from -50C to 150C. The
numerical models can be used to simulate all the basic types of semiconductor devices: resistors, MOS
capacitors, diodes, BJTs, JFETs and MOSFETs. BJTs and JFETs can be modeled with or without a
substrate contact. Support has been added for the management of device internal states. Post-processing
of device states can be performed using the ngnutmeg user interface.
GSS TCAD
GSS is a TCAD software which enables two-dimensional numerical simulation of semiconductor device
with well-known drift-diusion and hydrodynamic method. GSS has Basic DDM (drift-diusion method)
solver, Lattice Temperature Corrected DDM solver, EBM (energy balance method) solver and Quantum
corrected DDM solver which based on density-gradient theory. The GSS program is directed via input
statements by a user speci ed disk le. Supports triangle mesh generation and adaptive mesh re nement.
Employs PMI (physical model interface) to support various materials, including compound semiconductor
materials such as SiGe and AlGaAs. Supports DC sweep, transient and AC sweep calculations. The device
can be stimulated by voltage or current source(s).
GSS is no longer updated, but is still available as open source as a limited edition of the commercial
GENIUS TCAD tool.
CHAPTER 1. INTRODUCTION
24
1.2
Supported Analyses
The ngspice simulator supports the following dierent types of analysis:
1. DC Analysis (Operating Point and DC Sweep)
2. AC Small- Signal Analysis
3. Transient Analysis
4. Pole-Zero Analysis
5. Small-Signal Distortion Analysis
6. Sensitivity Analysis
7. Noise Analysis
Applications that are exclusively analog can make use of all analysis modes with the exception of Code
Model subsystem that do not implements Pole-Zero, Distortion, Sensitivity and Noise analyses. Eventdriven applications that include digital and User-De ned Node types may make use of DC (operating
point and DC sweep) and Transient only.
In order to understand the relationship between the dierent analyses and the two underlying simulation algorithms of ngspice, it is important to understand what is meant by each analysis type. This is
detailed below.
1.2.1 DC Analyses
The dc analysis portion of ngspice determines the dc operating point of the circuit with inductors shorted
and capacitors opened. The dc analysis options are speci ed on the
.DC, .TF,
and
.OP
control lines.
There is assumed to be no time dependence on any of the sources within the system description.
The simulator algorithm subdivides the circuit into those portions which require the analog simulator
algorithm and those which require the event-driven algorithm. Each subsystem block is then iterated to
solution, with the interfaces between analog nodes and event-driven nodes iterated for consistency across
the entire system.
Once stable values are obtained for all nodes in the system, the analysis halts and the results may be
displayed or printed out as you request them.
A dc analysis is automatically performed prior to a transient analysis to determine the transient initial
conditions, and prior to an ac small-signal analysis to determine the linearized, small-signal models for
nonlinear devices. If requested, the dc small-signal value of a transfer function (ratio of output variable
to input source), input resistance, and output resistance is also computed as a part of the dc solution.
The dc analysis can also be used to generate dc transfer curves: a speci ed independent voltage, current
source, resistor or temperature
1 is stepped over a user-speci ed range and the dc output variables are
stored for each sequential source value.
1.2.2 AC Small-Signal Analysis
AC analysis is limited to analog nodes and represents the small signal, sinusoidal solution of the analog
system described at a particular frequency or set of frequencies. This analysis is similar to the DC analysis
in that it represents the steady-state behavior of the described system with a single input node
set of stimulus frequencies.
at a given
The program rst computes the dc operating point of the circuit and determines linearized, smallsignal models for all of the nonlinear devices in the circuit. The resultant linear circuit is then analyzed
over a user-speci ed range of frequencies. The desired output of an ac small-signal analysis is usually a
transfer function (voltage gain, transimpedance, etc). If the circuit has only one ac input, it is convenient
to set that input to unity and zero phase, so that output variables have the same value as the transfer
function of the output variable with respect to the input.
1 Temperature (TEMP)
of Spice3f5.
and resistance sweeps have been introduced in Ngspice, they were not available in the original code
1.2. SUPPORTED ANALYSES
25
1.2.3 Transient Analysis
Transient analysis is an extension of DC analysis to the time domain.
A transient analysis begins by
obtaining a DC solution to provide a point of departure for simulating time-varying behavior. Once the
DC solution is obtained, the time-dependent aspects of the system are reintroduced, and the two simulator
algorithms incrementally solve for the time varying behavior of the entire system. Inconsistencies in node
values are resolved by the two simulation algorithms such that the time-dependent waveforms created by
the analysis are consistent across the entire simulated time interval. Resulting time-varying descriptions
of node behavior for the speci ed time interval are accessible to you.
All sources which are not time dependent (for example, power supplies) are set to their dc value. The
transient time interval is speci ed on a
.TRAN
control line.
1.2.4 Pole-Zero Analysis
The pole-zero analysis portion of Ngspice computes the poles and/or zeros in the small-signal ac transfer
function. The program rst computes the dc operating point and then determines the linearized, smallsignal models for all the nonlinear devices in the circuit. This circuit is then used to nd the poles and
zeros of the transfer function.
Two types of transfer functions are allowed:
one of the form (output
voltage)/(input voltage) and the other of the form (output voltage)/(input current). These two types
of transfer functions cover all the cases and one can nd the poles/zeros of functions like input/output
impedance and voltage gain. The input and output ports are speci ed as two pairs of nodes. The polezero analysis works with resistors, capacitors, inductors, linear-controlled sources, independent sources,
BJTs, MOSFETs, JFETs and diodes.
Transmission lines are not supported.
The method used in the
analysis is a sub-optimal numerical search. For large circuits it may take a considerable time or fail to
nd all poles and zeros. For some circuits, the method becomes "lost" and nds an excessive number of
poles or zeros.
1.2.5 Small-Signal Distortion Analysis
The distortion analysis portion of Ngspice computes steady-state harmonic and intermodulation products
for small input signal magnitudes. If signals of a single frequency are speci ed as the input to the circuit,
the complex values of the second and third harmonics are determined at every point in the circuit. If
there are signals of two frequencies input to the circuit, the analysis nds out the complex values of the
circuit variables at the sum and dierence of the input frequencies, and at the dierence of the smaller
frequency from the second harmonic of the larger frequency.
Distortion analysis is supported for the
following nonlinear devices:
Diodes (DIO),
BJT,
JFET,
MOSFETs (levels 1, 2, 3, 6, 9, BSIM1, BSIM2, BSIM3, BSIM4 and BSIMSOI),
MESFETS.
All linear devices are automatically supported by distortion analysis. If there are switches present in the
circuit, the analysis continues to be accurate provided the switches do not change state under the small
excitations used for distortion calculations.
1.2.6 Sensitivity Analysis
Ngspice will calculate either the DC operating-point sensitivity or the AC small-signal sensitivity of an
output variable with respect to all circuit variables, including model parameters.
Ngspice calculates
the dierence in an output variable (either a node voltage or a branch current) by perturbing each
parameter of each device independently. Since the method is a numerical approximation, the results may
demonstrate second order aects in highly sensitive parameters, or may fail to show very low but non-zero
sensitivity. Further, since each variable is perturb by a small fraction of its value, zero-valued parameters
are not analyzed (this has the bene t of reducing what is usually a very large amount of data).
CHAPTER 1. INTRODUCTION
26
Algorithm 1.1 Instance temperature computation
IF TEMP is speci ed THEN
instance_temperature = TEMP
ELSE IF
instance_temperature = circuit_temperature + DTEMP
END IF
1.2.7 Noise Analysis
The noise analysis portion of Ngspice does analysis device-generated noise for the given circuit. When
provided with an input source and an output port, the analysis calculates the noise contributions of each
device (and each noise generator within the device) to the output port voltage. It also calculates the input
noise to the circuit, equivalent to the output noise referred to the speci ed input source. This is done for
every frequency point in a speci ed range - the calculated value of the noise corresponds to the spectral
density of the circuit variable viewed as a stationary Gaussian stochastic process. After calculating the
spectral densities, noise analysis integrates these values over the speci ed frequency range to arrive at the
total noise voltage/current (over this frequency range). This calculated value corresponds to the variance
of the circuit variable viewed as a stationary Gaussian process.
1.3
Analysis at Dierent Temperatures
Temperature, in ngspice, is a property associated to the entire circuit, rather an analysis option. Circuit
temperature has a default (nominal) value of 27°C (300.15 K) that can be changed using the
in an
.option
TNOM option
control line. All analyses are, thus, performed at circuit temperature, and if you want to
simulate circuit behavior at dierent temperatures you should prepare a netlist for each temperature.
All input data for ngspice is assumed to have been measured at the circuit nominal temperature. This
TNOM
.model itself. Individual instances may further override the circuit temperature through
the speci cation of TEMP and DTEMP parameters on the instance. The two options are not independent
even if you can specify both on the instance line, the TEMP option overrides DTEMP. The algorithm to
value can further be overridden for any device which models temperature eects by specifying the
parameter on the
compute instance temperature is described below:
Temperature dependent support is provided for all devices except voltage and current sources (either independent and controlled) and BSIM models.
BSIM MOSFETs have an alternate temperature
dependency scheme which adjusts all of the model parameters before input to ngspice.
For details of the BSIM temperature adjustment, see [6] and [7]. Temperature appears explicitly in
the exponential terms of the BJT and diode model equations. In addition, saturation currents have a
built-in temperature dependence.
The temperature dependence of the saturation current in the BJT
models is determined by:
IS (T1 ) = IS (T0 )
where
k
is Boltzmann's constant,
parameter, and
XT I
q
T1
T0
XT I
exp
Eg q (T1 T0 )
k (T1 − T0 )
is the electronic charge,
Eg
(1.1)
is the energy gap which is a model
is the saturation current temperature exponent (also a model parameter, and usually
equal to 3).
The temperature dependence of forward and reverse beta is according to the formula:
B (T1 ) = B (T0 )
where
T0
and
T1
are in degrees Kelvin, and
XT B
T1
T0
XT B
(1.2)
is a user-supplied model parameter. Temperature
eects on beta are carried out by appropriate adjustment to the values of
BF , ISE , BR ,
and
ISC
(spice
model parameters BF, ISE, BR, and ISC, respectively).
Temperature dependence of the saturation current in the junction diode model is determined by:
IS (T1 ) = IS (T0 )
T1
T0
I
XT
N
exp
Eg q (T1 T0 )
N k (T1 − T0 )
(1.3)
1.4. CONVERGENCE
where
N
27
is the emission coe cient, which is a model parameter, and the other symbols have the same
meaning as above. Note that for Schottky barrier diodes, the value of the saturation current temperature
exponent,
XT I ,
is usually 2. Temperature appears explicitly in the value of junction potential, U (in
Ngspice PHI), for all the device models.
The temperature dependence is determined by:
kT
U (T ) =
ln
q
where
Nd
k
is Boltzmann's constant,
is the donor impurity density,
Ni
q
Na Nd
Ni (T )
!
(1.4)
2
is the electronic charge,
Na
is the acceptor impurity density,
Eg
is the intrinsic carrier concentration, and
Temperature appears explicitly in the value of surface mobility,
M0 (or U0 ),
is the energy gap.
for the MOSFET model.
The temperature dependence is determined by:
M0 (T0 )
M0 (T ) = 1.5
(1.5)
T
T0
The eects of temperature on resistors, capacitor and inductors is modeled by the formula:
h
i
2
R (T ) = R (T0 ) 1 + T C1 (T − T0 ) + T C2 (T − T0 )
where
T
is the circuit temperature,
T0
is the nominal temperature, and
(1.6)
T C1
and
T C2
are the rst
and second order temperature coe cients.
1.4
Convergence
Ngspice use the Newton-Raphson algorithm to solve nonlinear equations arising from circuit description.
The NR algorithm is interactive and terminates when both of the following conditions hold:
1. The nonlinear branch currents converge to within a tolerance of 0.1% or 1 picoamp (1.0e-12 Amp),
whichever is larger.
2. The node voltages converge to within a tolerance of 0.1% or 1 microvolt (1.0e-6 Volt), whichever is
larger.
1.4.1 Voltage convergence criterion
The algorithm has reached convergence if the dierence between the last iteration
(k
k
and the current one
+ 1):
vn(k+1) − vn(k) ≤ RELTOL ∗ vnmax + VNTOL
(1.7)
where
vnmax = max
The
RELTOL
vn(k+1) , vn(k)
(RELative TOLerance) parameter, which default value is
(1.8)
10−3 ,
speci es how small the
solution update must be, relative to the node voltage, to consider the solution to have converged. The
VNTOL
(absolute convergence) parameter, which has
1µV
as default becomes important when node volt-
ages have near zero values. The relative parameter alone, in such case, would need too strict tolerances,
perhaps lower than computer round-o error, and thus convergence would never be achieved.
VNTOL
forces the algorithm to consider as converged any node whose solution update is lower than its value.
1.4.2 Current convergence criterion
Ngspice checks the convergence on the non-linear functions that describe the non-linear branches in circuit
elements. In semiconductor devices the functions de nes currents through the device and thus the name
of the criterion.
Ngspice computes the dierence between the value of the nonlinear function computed for last voltage
and the linear approximation of the same current computed with the actual voltage:
CHAPTER 1. INTRODUCTION
28
\
(k+1)
(k)
ibranch − ibranch ≤ RELTOL ∗ ibrmax + ABSTOL
(1.9)
where
ibrmax
In the two expressions above, the
\
(k+1)
(k)
= max ibranch , ibranch
i\
branch
(1.10)
indicates the linear approximation of the current.
1.4.3 Convergence failure
Although the algorithm used in ngspice has been found to be very reliable, in some cases it fails to
converge to a solution. When this failure occurs, the program terminates the job. Failure to converge in
dc analysis is usually due to an error in specifying circuit connections, element values, or model parameter
values. Regenerative switching circuits or circuits with positive feedback probably will not converge in
the dc analysis unless the
OFF
option is used for some of the devices in the feedback path,
control line is used to force the circuit to converge to the desired state.
.nodeset
Chapter 2
Circuit Description
2.1
General Structure and Conventions
The circuit to be analyzed is described to ngspice by a set of element lines, which de ne the circuit
topology and element values, and a set of control lines, which de ne the model parameters and the run
controls. Two lines are essential:
The rst line in the input le must be the title, which is the only comment line that does not need
any special character in the rst place.
The last line must be
.end.
The order of the remaining lines is arbitrary (except, of course, that continuation lines must immediately
follow the line being continued). This feature in the ngspice input language dates back to the punched
card times where elements were written on separate cards (and cards frequently fell o ). Leading white
spaces in a line are ignored, as well as empty lines.
Each element in the circuit is speci ed by an element line that contains:
the element name,
the circuit nodes to which the element is connected,
and the values of the parameters that determine the electrical characteristics of the element.
The rst letter of the element name speci es the element type. The format for the ngspice element types
is given in what follows. In the rest of the manual, the strings
XXXXXXX, YYYYYYY,
and
ZZZZZZZ
denote
arbitrary alphanumeric strings.
R and can contain one or more characters.
R, R1, RSE, ROUT, and R3AC2ZY are valid resistor names. Details of each type of device are supplied
For example, a resistor name must begin with the letter
Hence,
in a following section 3.
Fields on a line are separated by one or more blanks, a comma, an equal (=) sign, or a left or right
parenthesis; extra spaces are ignored. A line may be continued by entering a + (plus) in column 1 of
the following line; ngspice continues reading beginning with column 2.
A name eld must begin with
a letter (A through Z) and cannot contain any delimiters. A number eld may be an integer eld (12,
-44), a oating point eld (3.14159), either an integer or oating point number followed by an integer
exponent (1e-14, 2.65e3), or either an integer or a oating point number followed by one of the following
scale factors:
29
CHAPTER 2. CIRCUIT DESCRIPTION
30
Su x
Name
Factor
T
Tera
1012
109
106
103
25.4 × 10−6
10−3
10−6
10−9
10−12
10−15
G
Giga
Meg
Mega
K
Kilo
mil
Mil
m
milli
u
micro
n
nano
p
pico
f
femto
Table 2.1: Ngspice scale factors
Letters immediately following a number that are not scale factors are ignored, and letters immediately
following a scale factor are ignored. Hence, 10, 10V, 10Volts, and 10Hz all represent the same number,
and M, MA, MSec, and MMhos all represent the same scale factor. Note that 1000, 1000.0, 1000Hz, 1e3,
1.0e3, 1kHz, and 1k all represent the same number.
Nodes names may be arbitrary character strings and are case insensitive.
The ground node must
be named 0 (zero). For compatibility reason gnd is accepted as ground node, and will internally be
treated as a global node and be converted to 0.
0)!
Each circuit has to have a ground node (gnd or
Note the dierence in ngspice where the nodes are treated as character strings and not evaluated as
numbers, thus 0 and 00 are distinct nodes in ngspice but not in SPICE2.
Ngspice requires that the following topological constraints are satis ed:
The circuit cannot contain a loop of voltage sources and/or inductors and cannot contain a cut-set
of current sources and/or capacitors.
Each node in the circuit must have a dc path to ground.
Every node must have at least two connections except for transmission line nodes (to permit unterminated transmission lines) and MOSFET substrate nodes (which have two internal connections
anyway).
2.2
Basic lines
2.2.1 Title Line, .TITLE line
Examples:
POWER AMPLIFIER CIRCUIT
* additional
*...
Test
lines
following
o f CAM c e l l
* additional
*...
lines
following
The title line must be the rst in the input le. Its contents are printed verbatim as the heading for
each section of output.
As an alternative you may place a
.TITLE
line anywhere in your input deck. The rst
line of your input deck will be overriden by the contents of this line following the .TITLE statement.
.TITLE line example:
******************************
* additional lines following
*...
. TITLE
Test
* additional
*...
o f CAM c e l l
lines
following
2.3. DEVICE MODELS
31
will internally be replaced by
Internal input deck:
Test
o f CAM c e l l
* additional lines
*...
* TITLE T e s t o f CAM
* additional lines
*...
following
cell
following
2.2.2 .END Line
Examples:
. end
The ".End" line must always be the last in the input le. Note that the period is an integral part of
the name.
2.2.3 Comments
General Form:
*
Examples:
*
*
RF=1K Gain
should
open − l o o p
Check
be
100
gain
and
phase
margin
The asterisk in the rst column indicates that this line is a comment line. Comment lines may be
placed anywhere in the circuit description.
2.2.4 End-of-line comments
General Form:
; < any
comment>
Examples:
RF2=1K
; Gain
C1=10p
$
should
Check
be
100
open − l o o p
gain
and
phase
margin
ngspice supports comments that begin with single characters ';' or double characters '$ ' or '//' or ''
2.3
Device Models
General form:
. model mname
t y p e ( pname1=p v a l 1
pname2=p v a l 2
...
)
Examples:
. model MOD1 npn
( b f =50
i s =1e −13
v b f =50)
Most simple circuit elements typically require only a few parameter values. However, some devices
(semiconductor devices in particular) that are included in ngspice require many parameter values. Often,
many devices in a circuit are de ned by the same set of device model parameters. For these reasons, a
set of device model parameters is de ned on a separate
.model
line and assigned a unique model name.
The device element lines in ngspice then refer to the model name.
For these more complex device types, each device element line contains the device name, the nodes
to which the device is connected, and the device model name. In addition, other optional parameters
may be speci ed for some devices: geometric factors and an initial condition (see the following section
on Transistors (9 to 12) and Diodes (8) for more details).
type is one of the following fteen types:
mname
in the above is the model name, and
CHAPTER 2. CIRCUIT DESCRIPTION
32
Code
Model Type
R
Semiconductor resistor model
C
Semiconductor capacitor model
L
Inductor model
SW
Voltage controlled switch
CSW
Current controlled switch
URC
Uniform distributed RC model
LTRA
Lossy transmission line model
D
Diode model
NPN
NPN BJT model
PNP
PNP BJT model
NJF
N-channel JFET model
PJF
P-channel JFET model
NMOS
N-channel MOSFET model
PMOS
P-channel MOSFET model
NMF
N-channel MESFET model
PMF
P-channel MESFET model
Table 2.2: Ngspice model types
Parameter values are de ned by appending the parameter name followed by an equal sign and the
parameter value. Model parameters that are not given a value are assigned the default values given below
for each model type. Models are listed in the section on each device along with the description of device
element lines. Model parameters and their default values are given in chapter 30.
2.4
Subcircuits
A subcircuit that consists of ngspice elements can be de ned and referenced in a fashion similar to
device models. Subcircuits are the way ngspice implements hierarchical modeling, but this is not entirely
true because each subcircuit instance is attened during parsing, and thus ngspice is not a hierarchical
simulator.
.subckt
.ends cards (or the keywords de ned by the substart and subend options (see 18.6)); the program
The subcircuit is de ned in the input deck by a grouping of element cards delimited by the
and the
then automatically inserts the de ned group of elements wherever the subcircuit is referenced. Instances
of subcircuits within a larger circuit are de ned through the use of an instance card which begins with
the letter X. A complete example of all three of these cards follows:
Example:
* The following is the instance card :
*
xdiv1 10 7 0 vdivide
* The following are the subcircuit definition cards :
*
. subckt vdivide 1 2 3
r1 1 2 10 K
r2 2 3 5 K
. ends
The above speci es a subcircuit with ports numbered 1, 2 and 3:
Resistor R1 is connected from port 1 to port 2, and has value 10 kOhms.
Resistor R2 is connected from port 2 to port 3, and has value 5 kOhms.
2.5. GLOBAL
33
The instance card, when placed in an ngspice deck, will cause subcircuit port 1 to be equated to circuit
node 10, while port 2 will be equated to node 7 and port 3 will equated to node 0.
There is no limit on the size or complexity of subcircuits, and subcircuits may contain other subcircuits.
An example of subcircuit usage is given in chapter 21.6.
2.4.1 .SUBCKT Line
General form:
. SUBCKT subnam N1
Examples:
. SUBCKT OPAMP 1
2
3
4
A circuit de nition is begun with a
.SUBCKT
line. SUBNAM is the subcircuit name, and N1, N2, ...
are the external nodes, which cannot be zero. The group of element lines which immediately follow the
.SUBCKT
line de ne the subcircuit. The last line in a subcircuit de nition is the
.ENDS
line (see below).
Control lines may not appear within a subcircuit de nition; however, subcircuit de nitions may contain
anything else, including other subcircuit de nitions, device models, and subcircuit calls (see below). Note
that any device models or subcircuit de nitions included as part of a subcircuit de nition are strictly
local (i.e., such models and de nitions are not known outside the subcircuit de nition). Also, any element
nodes not included on the
.SUBCKT line are strictly local, with the exception of 0 (ground) which is always
.SUBCKT line will be extended (see 2.8.3).
global. If you use parameters, the
2.4.2 .ENDS Line
General form:
. ENDS
Examples:
. ENDS OPAMP
The
.ENDS
line must be the last one for any subcircuit de nition. The subcircuit name, if included,
indicates which subcircuit de nition is being terminated; if omitted, all subcircuits being de ned are
terminated. The name is needed only when nested subcircuit de nitions are being made.
2.4.3 Subcircuit Calls
General form:
XYYYYYYY N1 SUBNAM
Examples:
X1 2
4
17
3
1 MULTI
Subcircuits are used in ngspice by specifying pseudo-elements beginning with the letter X, followed
by the circuit nodes to be used in expanding the subcircuit. If you use parameters, the subcircuit call
will be modi ed (see 2.8.3).
2.5
GLOBAL
General form:
.GLOBAL nodename
Examples:
.GLOBAL gnd
vcc
Nodes de ned in the .GLOBAL statement are available to all circuit and subcircuit blocks independently from any circuit hierarchy. After parsing the circuit, these nodes are accessible from top level.
CHAPTER 2. CIRCUIT DESCRIPTION
34
2.6
INCLUDE
General form:
. INCLUDE
filename
Examples:
. INCLUDE / u s e r s / s p i c e /common/ w a t t m e t e r . c i r
Frequently, portions of circuit descriptions will be reused in several input les, particularly with
.INCLUDE line may be used
.INCLUDE line in the original le.
common models and subcircuits. In any ngspice input le, the
other le as if that second le appeared in place of the
to copy some
There is no restriction on the le name imposed by ngspice beyond those imposed by the local
operating system.
2.7
LIB
General form:
. LIB
filename
libname
Examples:
. LIB
/ u s e r s / s p i c e /common/ m o s f e t s . l i b
The
library
.LIB
statement allows to include library descriptions into the input le. Inside the *.lib le a
libname may be selected.
libname <...> .ENDL
2.8
mos1
The statements of each library inside the *.lib le are enclosed in
.LIB
statements.
Parametric netlists
Ngspice allows for the de nition of parametric attributes in the netlists. This is an enhancement of the
ngspice front-end which adds arithmetic functionality to the circuit description language.
2.8.1 .param line
General form:
. param =
; =
....
Examples:
. param
p i p p o =5
. param pp=6
. param
p i p p p={ p i p p o + pp }
. param p={pp }
. param
pap = 'pp+p '
This line assigns numerical values to identi ers. More than one assignment per line is possible using the
';' separator. The
.param
lines inside subcircuits are copied per call, like any other line. All assignments
are executed sequentially through the expanded circuit. Before its rst use, a parameter name must have
been assigned a value. Expression de ning a parameter have to be put into braces
into single quotes
'p+p2'.
{p+p2},
alternatively
2.8.2 Brace expressions in circuit elements:
General form:
{ }
Examples:
These are allowed in
.model lines and in device lines.
A spice number is a oating point number with
an optional scaling su x, immediately glued to the numeric tokens (see chapt. 2.8.5). Brace expressions
2.8. PARAMETRIC NETLISTS
35
({..}) cannot be used to parametrize node names or parts of names. All identi ers used within an
must have known values at the time when the line is evaluated, else an error is agged.
2.8.3 Subcircuit parameters
General form:
. s u b c k t n o d e
node
...
= =
...
Examples:
. subckt
myfilter
in
out
r v a l =100k
c v a l =100nF
is the name of the subcircuit given by the user. node is an integer number or an identi er,
The rst = introduces an optional section of the line.
Each is a formal parameter, and each is either a spice number or a brace expression.
Inside the .subckt ... .ends context, each formal parameter may be used like any identi er that was
de ned on a .param control line. The parts are supposed to be default values of the parameters.
for one of the external nodes.
However, in the current version of , they are not used and each invocation of the subcircuit must supply
the _exact_ number of actual parameters.
The syntax of a subcircuit call (invocation) is:
General form:
X n o d e
node
...
= =
...
Examples:
X1
input
Here
output
myfilter
c v a l =1n
is the symbolic name given to that instance of the subcircuit,
of a subcircuit de ned beforehand.
connected.
r v a l =1k
node node ...
is the name
is the list of actual nodes where the subcircuit is
is either a spice number or a brace expression { } . The sequence of
X line must exactly match the number and the order of formal parameters of the subcircuit.
items on the
Subcircuit example with parameters:
*
Param−e x a m p l e
. param
a m p l i t u d e= 1V
*
. subckt
Ra
in
myfilter
in
r v a l =100k
c v a l =100nF
{2* r v a l }
Rb p1
out
C1 p1
0
{2* c v a l }
Ca
p2
{ cval }
Cb p2
out
{ cval }
R1 p2
0
{ rval }
. ends
myfilter
in
out
{2* r v a l }
p1
*
X1
input
output
V1
input
0 AC { a m p l i t u d e }
myfilter
r v a l =1k
c v a l =1n
. end
More text
2.8.4 Symbol scope
All subcircuit and model names are considered global and must be unique.
de ned outside of any .subckt ...
params:
symbols and any
names, until the
.ends
.param
.ends section are global.
The
.param
symbols that are
Inside such a section, the pertaining
assignments are considered local: they mask any global identical
line is encountered. You cannot reassign to a global number inside a
.subckt,
a
local copy is created instead. Scope nesting works up to a level of 10. For example, if the main circuit
calls A which has a formal parameter xx, A calls B which has a param. xx, and B calls C which also has
a formal param. xx, there will be three versions of 'xx' in the symbol table but only the most local one
- belonging to C - is visible.
CHAPTER 2. CIRCUIT DESCRIPTION
36
2.8.5 Syntax of expressions
( optional parts within [ ...] ):
An expression may be one of:
w h e r e
is
either
a
spice
number
or
an
identifier
(
[
,
...]
)
( )
As expected, atoms, built-in function calls and stu within parentheses are evaluated before the other
operators. The operators are evaluated following a list of precedence close to the one of the C language.
For equal precedence binary ops, evaluation goes left to right.
Operator
Alias
-
Precedence
Precedence
1
unary -
not
!
1
unary not
**
^
2
power
3
multiply
*
3
divide
mod
/
%
3
modulo
div
\
3
integer divide
+
4
add
-
4
subtract
==
5
equality
<>
5
un-equal
<=
!=
5
less or equal
>=
5
greater or equal
<
5
less than
>
5
greater than
and
&&
6
and
or
||
7
or
The result of logical operators is 1 or 0 , for True or False.
Builtin function
Notes
de ned
returns 1 if symbol is de ned, else 0
sqr
sqrt
sin
cos
exp
ln
arctan
abs
pwr
min
max
The scaling su xes (any decorative alphanumeric string may follow):
su x
value
g
1e9
meg
1e6
k
1e3
m
1e-3
u
1e-6
n
1e-9
p
1e-12
f
1e-15
Note: there are intentional redundancies in expression syntax, e.g. x^y , x**y and pwr(x,y) all have
2.9. FUNC
37
nearly the same result.
2.8.6 Reserved words
In addition to the above function names and to the verbose operators ( not and or div mod ), other words
are reserved and cannot be used as parameter names: and, or, not, div, mod, if, else, end, while, macro,
funct, de ned, include, for, to, downto, is, var, sqr, sqrt, sin, cos, exp, ln, arctan, abs, pwr.
2.8.7 Alternative syntax
The & sign is tolerated to provide some historical parameter notation: & as the rst character of a line
is equivalent to:
.param.
Inside a line, the notation
as
{identifier}
&(....)
is equivalent to
{....},
and
&identifier
means the same thing
.
Comments in the style of C++ line trailers (//) are detected and erased.
Warning: this is NOT possible in embedded .control parts of a source le, these lines are outside of
this scope.
Now, there is some possible confusion in Spice because of multiple numerical expression features. The
.param lines and the braces expressions (see next chapter 2.9) are evaluated in the front-end, that is, just
after the subcircuit expansion. (Technically, the X lines are kept as comments in the expanded circuit
so that the actual parameters can correctly be substituted ). So, after the netlist expansion and before
the internal data setup, all number attributes in the circuit are known constants.
However, there are
some circuit elements in Spice which accept arithmetic expressions that are NOT evaluated at this point,
but only later during circuit analysis. These are the arbitrary current and voltage sources (B-sources,
6), as well as E- and G-sources and R-, L-, or C-devices.
The syntactic dierence is that "compile-
time" expressions are within braces, but "run-time" expressions have no braces. To make things more
complicated, the backend language JDML also accepts arithmetic/logic expressions that operate on its
own scalar or vector data sets (18.1). Please see also chapt. 2.10.
It would be desirable to have the same expression syntax, operator and function set, and precedence
rules, for the three contexts mentioned above. In the current Numparam implementation, that goal is
not yet achieved...
2.9
func
With this line a function may be de ned. The syntax of its expression is equivalent to the expression
syntax from the .param line (2.8.5).
General form:
. f u n c { }
Examples:
. func
icos (x)
. func
f (x , y)
{ cos (x)
−
1}
{x*y}
Further explanation missing, e.g. sequence of functions, where to use.
2.10
Parameters, functions, expressions, and command scripts
In ngspice there are several ways to describe functional dependencies. In fact there are three independent
function parsers, being active before, during, and after the simulation. So it might be due to have a few
words on their interdepedencies.
2.10.1 Parameters
Parameters (chapt. 2.8.1) and functions, either de ned within the
statement (chapt. 2.9) are evaluated
input and the circuit.
before
.param
statement or with the
.func
any simulation is started, that is during the setup of the
Therefore these statements may not contain any simulation output (voltage or
current vectors), because it is simply not yet available. The syntax is described in chapt. 2.8.5. During
the circuit setup all functions are evaluated, all parameters are replaced by their resulting numerical
CHAPTER 2. CIRCUIT DESCRIPTION
38
values.
Thus it will not be possible to get feedback from a later stage (during or after simulation) to
change any of the parameters.
2.10.2 Nonlinear sources
During the simulation, the B source (chapt. 6) and their associated E and G sources, as well as some
devices (R, C, L) may contain expressions. These expressions may contain parameters from above (evaluated immediately upon ngspice start up), numerical data, predined functions, but also node voltages and
branch currents which are resulting from the simulation. The source or device values are continuously
updated
during the simulation.
Therefore the sources are powerful tools to de ne non-linear behaviour,
you may even create new 'devices' by yourself. Unfortunately the expression syntax (see chapt. 6.1) and
the pred ned functions may deviate from the ones for parameters listed in 2.8.1.
2.10.3 Control commands, Command scripts
Commands, as decribed in detail in chapt. 18.4, may be used interactively, but also as a command script
enclosed in
.control ...
.endc
lines.
The scripts may contain expressions (see chapt.
18.1).
The
expressions may work upon simulation output vectors (of node voltages, branch currents), as well as
upon prede ned or user de ned vectors and variables, and are invoked
after the simulation.
Parameters
from 2.8.1 are not allowed in these expressions. Again the expression syntax (see chapt. 18.1) will deviate
from the one for parameters or B sources listed in 2.8.1 and 6.1.
If you want to use parameters from 2.8.1 inside your control script, you may apply a trick by de ning a
voltage source with the parameter as its value, and then have it available as a vector (e.g. after a transient
simulation) with a then constant ouput (the parameter).
A feedback from here back into parameters
(2.10.1) is never possible. Also you cannot access non-linear sources of the preceeding simulation. However
you may start a rst simulation inside your control script, then evaluate its output using expressions,
change some of the element or model parameters with the
alter
and
altermod
statements (see chapt.
18.4.3) and then automatically start a new simulation.
Expressions and scripting are powerful tools within ngspice, and we will enhance the examples given
in chapt. 21 continuously to describe these features.
Chapter 3
Circuit Elements and Models
Data elds that are enclosed in less-than and greater-than signs ('< >') are optional. All indicated punctuation (parentheses, equal signs, etc.) is optional but indicate the presence of any delimiter. Further,
future implementations may require the punctuation as stated. A consistent style adhering to the punctuation shown here makes the input easier to understand. With respect to branch voltages and currents,
ngspice uniformly uses the associated reference convention (current ows in the direction of voltage drop).
3.1
General options and information
3.1.1 Simulating more devices in parallel
If you need to simulate more devices of the same kind in parallel, you can use the
m
(often called
parallel multiplier) option which is available for all instances except transmission lines and sources (both
independent and controlled). The parallel multiplier is implemented by multiplying the value of
m
the
element's matrix stamp, thus it cannot be used to accurately simulate larger devices in integrated circuits.
The netlist below show how to correctly use the parallel multiplier:
Multiple device example:
d1
2
0
mydiode m=10
d01
1
0
mydiode
d02
1
0
mydiode
d03
1
0
mydiode
d04
1
0
mydiode
d05
1
0
mydiode
d06
1
0
mydiode
d07
1
0
mydiode
d08
1
0
mydiode
d09
1
0
mydiode
d10
1
0
mydiode
...
The
d1 instance connected between nodes 2 and 0 is equivalent to the parallel d01-d10 connected between
1 and 0.
3.1.2 Technology scaling
Still to be implemented and written.
3.1.3 Model binning
Still to be implemented and written.
3.1.4 Transistors and Diodes
The area factor
m (often called parallel multiplier) used on the diode, BJT, JFET, and MESFET devices
determines the number of equivalent parallel devices of a speci ed model. The aected parameters are
39
CHAPTER 3. CIRCUIT ELEMENTS AND MODELS
40
marked with an asterisk under the heading area in the model descriptions (see the various chapters on
models below). Several geometric factors associated with the channel and the drain and source diusions
can be speci ed on the MOSFET device line.
Two dierent forms of initial conditions may be speci ed for some devices. The rst form is included
to improve the dc convergence for circuits that contain more than one stable state. If a device is speci ed
OFF,
the dc operating point is determined with the terminal voltages for that device set to zero. After
convergence is obtained, the program continues to iterate to obtain the exact value for the terminal
OFF option
OFF when in
voltages. If a circuit has more than one dc stable state, the
can be used to force the solution
to correspond to a desired state. If a device is speci ed
reality the device is conducting,
the program still obtains the correct solution (assuming the solutions converge) but more iterations are
required since the program must independently converge to two separate solutions.
The .NODESET control line (see chapt. 16.2.1) serves a similar purpose as the OFF option. The
.NODESET option is easier to apply and is the preferred means to aid convergence. The second form of
initial conditions are speci ed for use with the transient analysis. These are true initial conditions as
opposed to the convergence aids above. See the description of the
the
.TRAN
3.2
.IC
control line (chapt. 16.2.2) and
control line (chapt. 16.3.9) for a detailed explanation of initial conditions.
Elementary Devices
3.2.1 Resistors
General form:
RXXXXXXX n+ n− v a l u e < s c a l e =v a l >
+
Examples:
R1 1
2
100
RC1 12
17
R2 5
7
1K a c=2K
1K
RL 1
4
2K m=2
Ngspice has a fairly complex model for resistors.
It can simulate both discrete and semiconductor
resistors. Semiconductor resistors in ngspice means: resistors described by geometrical parameters. So,
do not expect detailed modeling of semiconductor eects.
n+
and
negative
n-
are the two element nodes,
1 but not zero.
value
is the resistance (in ohms) and may be positive or
Simulating small valued resistors: If you need to simulate very small resistors (0.001
Ohm or less), you should use CCVS (transresistance), it is less e cient but improves overall numerical accuracy.
Think about that a small resistance is a large
conductance.
Ngspice can assign a resistor instance a dierent value for AC analysis, speci ed using the
This value must not be zero as described above.
Pole-Zero nor noise). If you do not specify the
ac
ac keyword.
The AC resistance is used in AC analysis only (not
parameter, it is defaulted to
value.
If you want to
simulate temperature dependence of a resistor, you need to specify its temperature coe cients, using a
.model
line, like in the example below:
Example:
RE1 1
2
800
newres
dtemp=5
.MODEL n e w r e s R t c 1 = 0 . 0 0 1
Instance temperature is useful even if resistance does not varies with it, since the thermal noise
generated by a resistor depends on its absolute temperature. Resistors in ngspice generates two dierent
noises: thermal and icker. While thermal noise is always generated in the resistor, to add a icker noise
source you have to add a
.model
2
card de ning the icker noise parameters. It is possible to simulate
resistors that do not generate any kind of noise using the
noisy
keyword and assigning zero to it, as in
the following example:
1 A negative resistor modeling an active element can cause
2 Flicker noise can be used to model carbon resistors.
convergence problems, please avoid it.
3.2. ELEMENTARY DEVICES
41
Example:
Rmd 1 3 4
57
1.5k
n o i s y =0
Ngspice calculates the nominal resistance as described below:
VALUE∗scale
m
ac∗scale
m
Rnom =
Racnom =
(3.1)
If you are interested in temperature eects or noise equations, read the next section on semiconductor
resistors.
3.2.2 Semiconductor Resistors
General form:
RXXXXXXX n+ n− < l =l e n g t h >
+ m= < s c a l e =v a l >
Examples:
RLOAD 2
RMOD 3
10
1 0K
7 RMODEL L=10u W=1u
This is the more general form of the resistor presented before (3.2.1) and allows the modeling of
temperature eects and for the calculation of the actual resistance value from strictly geometric infor-
value is speci ed, it overrides the geometric information
mname is speci ed, then the resistance may be calculated from the process
information in the model mname and the given length and width. If value is not speci ed, then mname
and length must be speci ed. If width is not speci ed, then it is taken from the default width given in
mation and the speci cations of the process. If
and de nes the resistance. If
the model.
The (optional)
temp
value is the temperature at which this device is to operate, and overrides the
temperature speci cation on the
.option
control line and the value speci ed in
dtemp.
3.2.3 Semiconductor Resistor Model (R)
The resistor model consists of process-related device data that allow the resistance to be calculated from
geometric information and to be corrected for temperature. The parameters available are:
Name
Parameter
Units
Default
Example
TC1
rst order temperature coe.
Ω/°C
0.0
-
TC2
second order temperature coe.
Ω/°C 2
0.0
-
RSH
sheet resistance
Ω/
-
50
m
m
m
°C
1e-6
2e-6
0.0
1e-7
0.0
1e-7
DEFW
default width
NARROW
narrowing due to side etching
SHORT
shortening due to side etching
TNOM
parameter measurement temperature
KF
icker noise coe cient
AF
icker noise exponent
27
50
0.0
1e-25
0.0
The sheet resistance is used with the narrowing parameter and
l
and
w
1.0
from the resistor device to
determine the nominal resistance by the formula:
Rnom = rsh
or
DEFW is
l is not
used to supply a default value for
w
l − SHORT
w − NARROW
if one is not speci ed for the device.
speci ed, then the standard default resistance value of 1 kOhm is used.
override the circuit-wide value given on the
(3.2)
.options
If either
TNOM
rsh
is used to
control line where the parameters of this model
have been measured at a dierent temperature. After the nominal resistance is calculated, it is adjusted
for temperature by the formula:
R(T ) = R(TNOM) 1 + T C1 (T − TNOM) + T C2 (T − TNOM)2
where
(3.3)
R(TNOM) = Rnom |Racnom . In the above formula, T represents the instance temperature,
temp keyword or calculated using the circuit temperature and dtemp,
which can be explicitly set using the
CHAPTER 3. CIRCUIT ELEMENTS AND MODELS
42
if present. If both
temp
and
dtemp
are speci ed, the latter is ignored. Ngspice improves spice's resistors
noise model, adding icker noise (1/f ) to it and the
noisy
keyword to simulate noiseless resistors. The
thermal noise in resistors is modeled according to the equation:
4kT
i¯2R =
∆f
R
(3.4)
where "k " is the Boltzmann's constant, and "T " the instance temperature.
Flicker noise model is:
¯ =
i2Rf
n
AF
KFIR
∆f
f
(3.5)
A small list of sheet resistances (in Ω/) for conductors is shown below. The table represents typical
values for MOS processes in the 0.5 - 1 um
N. Weste, K. Eshraghian - Principles of CMOS VLSI Design 2nd
range. The table is taken from:
Edition, Addison Wesley.
Material
Min.
Typ.
Intermetal (metal1 - metal2)
0.005
0.007
Max.
0.1
Top-metal (metal3)
0.003
0.004
0.05
Polysilicon (poly)
15
20
30
Silicide
2
3
6
Diusion (n+, p+)
10
25
100
Silicided diusion
2
4
10
n-well
1000
2000
5000
3.2.4 Resistors, dependent on expressions
General form:
RXXXXXXX n+ n− R =
RXXXXXXX n+ n−
' expression '
' expression '
Examples:
R1
rr
0
r =
Expression
'V( r r ) < { Vt }
?
{R0}
:
{ 2 * R0 } '
may be an equation or an expression containing node voltages or branch currents (in
the form of i(vm)) and any other terms as given for the B source and described in chapter 6.1. It may
contain parameters (2.8.1). An example le is given below.
Example input le for non-linear resistor:
Non− l i n e a r
resistor
. param R0=1k
*
resistor
R1
*
rr
0
r =
control
V1
rr
Vi=1 Vt = 0 . 5
depending
set
0 PWL( 0
0
100u
noaskquit
100n
plot
i ( V1 )
. endc
. end
control
voltage
. control
tran
on
'V( r r ) < { Vt }
100u
uic
{ Vi } )
?
{R0}
v o l t a g e V( r r )
:
{ 2 * R0 } '
3.2. ELEMENTARY DEVICES
43
3.2.5 Capacitors
General form:
CXXXXXXX n+ n− < s c a l e =v a l >
+ < i c =i n i t _ c o n d i t i o n >
Examples:
CBYP 13
0
COSC 1 7
23
1UF
1 0U IC=3V
Ngspice provides a detailed model for capacitors. Capacitors in the netlist can be speci ed giving their
capacitance or their geometrical and physical characteristics. Following the original spice3 "convention",
capacitors speci ed by their geometrical or physical characteristics are called "semiconductor capacitors"
and are described in the next section.
In this rst form
n+
and
n-
are the positive and negative element nodes, respectively and
value
is
the capacitance in Farads.
Capacitance can be speci ed in the instance line as in the examples above or in a
.model
line, as in
the example below:
@C1 15
5
C2 2
cstd
7
. model
cstd
c s t d C c a p=3n
Both capacitors have a capacitance of 3nF.
If you want to simulate temperature dependence of a capacitor, you need to specify its temperature
coe cients, using a @command{.model} line, like in the example below:
CEB 1
2
1u
cap1
dtemp=5
.MODEL c a p 1 C t c 1 = 0 . 0 0 1
The (optional) initial condition is the initial (time zero) value of capacitor voltage (in Volts). Note
that the initial conditions (if any) apply 'only' if the
uic
option is speci ed on the
.tran
control line.
Ngspice calculates the nominal capacitance as described below:
Cnom = value ∗ scale ∗ m
(3.6)
3.2.6 Semiconductor Capacitors
General form:
CXXXXXXX n+ n− < l =l e n g t h >
+ < s c a l e =v a l > < i c =i n i t _ c o n d i t i o n >
Examples:
CLOAD 2
CMOD 3
10
1 0P
7 CMODEL L=10u W=1u
This is the more general form of the Capacitor presented in section (3.2.5), and allows for the calculation of the actual capacitance value from strictly geometric information and the speci cations of the
value is speci ed, it de nes the capacitance and both process and geometrical information
value is not speci ed, the capacitance is calculated from information contained model
mname and the given length and width (l, w keywords, respectively).
It is possible to specify mname only, without geometrical dimensions and set the capacitance in the
.model line (3.2.5).
process. If
are discarded. If
3.2.7 Semiconductor Capacitor Model (C)
The capacitor model contains process information that may be used to compute the capacitance from
strictly geometric information.
CHAPTER 3. CIRCUIT ELEMENTS AND MODELS
44
Name
Parameter
Units
Default
Example
1e-6
CAP
model capacitance
F
0.0
CJ
junction bottom capacitance
F/m2
-
5e-5
CJSW
junction sidewall capacitance
F/m
-
2e-11
DEFW
default device width
2e-6
default device length
m
m
m
m
F/°C
F/°C 2
°C
F/m
m
1e-6
DEFL
0.0
1e-6
0.0
1e-7
0.0
1e-7
0.0
0.001
0.0
0.0001
27
50
-
1
0.0
1e-9
NARROW
narrowing due to side etching
SHORT
shortening due to side etching
TC1
rst order temperature coe.
TC2
second order temperature coe.
TNOM
parameter measurement temperature
DI
relative dielectric constant
THICK
insulator thickness
The capacitor has a capacitance computed as:
value
If
is speci ed on the instance line then
Cnom = value ∗ scale ∗ m
(3.7)
If model capacitance is speci ed then
Cnom = CAP ∗ scale ∗ m
If neither
(3.8)
value nor CAP are speci ed, then geometrical and physical parameters are take into account:
C0 = CJ(l − SHORT)(w − NARROW) + 2CJSW(l − SHORT + w − NARROW)
CJ
.model
can be explicitly given on the
line or calculated by physical parameters. When
(3.9)
CJ
is not
given, is calculated as:
If
THICK
is not zero:
CJ =
CJ =
DI∗0
THICK
SiO2
THICK
if DI is specified,
otherwise.
(3.10)
If the relative dielectric constant is not speci ed the one for SiO2 is used. The values of the constants
F
0 = 8.854214871e − 12 m
are:
and
F
SiO2 = 3.4531479969e − 11 m
.
The nominal capacitance is then
computed as:
Cnom = C0 ∗ scale ∗ m
(3.11)
After the nominal capacitance is calculated, it is adjusted for temperature by the formula:
C(T ) = C(TNOM) 1 + T C1 (T − TNOM) + T C2 (T − TNOM)2
where
(3.12)
C(TNOM) = Cnom .
In the above formula, T represents the instance temperature, which can be explicitly set using the
temp
keyword or calculated using the circuit temperature and
dtemp,
if present.
3.2.8 Capacitors, dependent on expressions
General form:
CXXXXXXX n+ n− C =
CXXXXXXX n+ n−
' expression '
' expression '
Examples:
C1
cc
0
c =
Expression
'V( c c ) < { Vt }
?
{C1}
:
{Ch } '
may be an equation or an expression containing node voltages or branch currents (in
the form of i(vm)) and any other terms as given for the B source and described in chapter 6.1. It may
contain parameters (2.8.1).
3.2. ELEMENTARY DEVICES
45
Example input le:
Dependent
. param
. ic
*
Capacitor
C l=5n Ch=1n Vt=1m
v ( cc ) = 0
capacitor
C1
cc
* C1
I1
0
cc
0
0
1
depending
c =
?
v o l t a g e V( c c )
{ Cl }
:
{Ch } '
{Il}
n2
n2
Cxxx
n1−c o p y
n2
1
Bxxx
cc2
I =
I2
22
vn2
control
c ={Ch}
n1−c o p y
*
on
'V( c c ) < { Vt }
Exxx
n2
I l =100n
v ( cc2 ) = 0
n2
n2
cc2
1
' (V( c c 2 ) < { Vt }
?
{ Cl }
:
{Ch } ) '
*
i ( Exxx )
{Il}
0 DC 0
measure
charge
a i n t 1 %i d ( 1
cc )
a i n t 2 %i d ( 2 2
. model
by
2
integrating
current
time_count
cc2 )
3
time_count
time_count
i n t ( i n _ o f f s e t =0.0
+ o u t _ l o w e r _ l i m i t=−1e 1 2
+ l i m i t _ r a n g e =1e −9
g a i n =1.0
o u t _ u p p e r _ l i m i t=1e 1 2
out_ic =0.0)
. control
set
noaskquit
tran
100n
plot
v(2)
100u
plot
v ( cc )
v ( cc2 )
. endc
. end
3.2.9 Inductors
General form:
LYYYYYYY n+ n− < s c a l e =v a l >
+ < i c =i n i t _ c o n d i t i o n >
Examples:
LLINK 42
69
LSHUNT 23
51
1UH
1 0U IC = 1 5 . 7MA
The inductor device implemented into ngspice has many enhancements over the original one.n+ and
nvalue is the inductance in Henries. Inductance
examples above or in a .model line, as in the example
are the positive and negative element nodes, respectively.
can be speci ed in the instance line as in the
below:
L1
15
L2
2
5
7
indmod1
indmod1
. model
indmod1 L
i n d =3n
Both inductors have an inductance of 3nH.
The nt is used in conjunction with a .model line, and is used to specify the number of turns of
the inductor. If you want to simulate temperature dependence of an inductor, you need to specify its
temperature coe cients, using a
Lload
1
2
1u
.MODEL i n d 1
ind1
L
.model
line, like in the example below:
dtemp=5
t c 1 =0.001
The (optional) initial condition is the initial (time zero) value of inductor current (in Amps) that
ows from
n+, through the inductor, to n-. Note that the initial conditions (if any) apply only if the UIC
.tran analysis line.
option is speci ed on the
Ngspice calculates the nominal inductance as described below:
CHAPTER 3. CIRCUIT ELEMENTS AND MODELS
46
Lnom =
value ∗ scale
m
(3.13)
3.2.10 Inductor model
The inductor model contains physical and geometrical information that may be used to compute the
inductance of some common topologies like solenoids and toroids, wound in air or other material with
constant magnetic permeability.
Name
Parameter
Units
Default
Example
IND
model inductance
0.0
1e-3
CSECT
cross section
0.0
1e-3
LENGTH
length
0.0
1e-2
TC1
rst order temperature coe.
TC2
second order temperature coe.
TNOM
parameter measurement temperature
H
m2
m
H/°C
H/°C 2
°C
NT
number of turns
-
MU
relative magnetic permeability
H/m
0.0
-
0.0
0.001
0.0
0.0001
27
50
0.0
10
The inductor has an inductance computed as:
If
value
is speci ed on the instance line then
Lnom =
value ∗ scale
m
(3.14)
Lnom =
IND ∗ scale
m
(3.15)
If model inductance is speci ed then
If neither
value nor IND are speci ed, then geometrical and physical parameters are take into account.
In the following formulas
NT
If
refers to both instance and model parameter (instance parameter overrides model parameter):
LENGTH
is not zero:
(
Lnom =
Lnom =
with:µ0
MU∗µ0 ∗NT2 ∗CSECT
LENGTH
µ0 ∗NT2 ∗CSECT
LENGTH
H
= 1.25663706143592e − 6 m
.
if MU is specified,
(3.16)
otherwise.
After the nominal inductance is calculated, it is adjusted for
temperature by the formula:
L(T ) = L(TNOM) 1 + T C1 (T − TNOM) + T C2 (T − TNOM)2
where
L(TNOM) = Lnom . In the above formula, T
temp keyword or calculated using
be explicitly using the
(3.17)
represents the instance temperature, which can
the circuit temperature and
dtemp,
if present.
3.2.11 Coupled (Mutual) Inductors
General form:
KXXXXXXX LYYYYYYY LZZZZZZZ
value
Examples:
K43 LAA LBB 0 . 9 9 9
KXFRMR L1 L2
0.87
LYYYYYYY and LZZZZZZZ are the names of the two coupled inductors, and
value is the coe cient
of coupling, K, which must be greater than 0 and less than or equal to 1. Using the dot convention,
place a dot on the rst node of each inductor.
3.2. ELEMENTARY DEVICES
47
3.2.12 Inductors, dependent on expressions
General form:
LXXXXXXX n+ n− L =
LXXXXXXX n+ n−
' expression '
' expression '
Examples:
L1
l2
lll
L =
Expression
' i (Vm) < { I t }
?
{ Ll }
:
{Lh } '
may be an equation or an expression containing node voltages or branch currents (in
the form of i(vm)) and any other terms as given for the B source and described in chapter 6.1. It may
contain parameters (2.8.1).
Example input le:
Variable
. param
. ic
*
l2
*
*
lll
0
*
l2
0
current
dc
33
331
dc
current
i (Vm)
{Lh } '
inductor
linear
through
inductor
0
on
*
inductor
{ Vi }
inductor
int21
0
B21
L21
int21
0
1
B21
n1
n2 V =
measure
vm21 n2
V21 n1
:
inductor
current
0
0
*
control
{ Ll }
{ Ll }
voltage
non
on
inductor
331
V3 3 3
F21
through
?
0
on
measure
vm33
depending
' i (Vm) < { I t }
{ Vi }
fixed
L3
inductor
L =
voltage
V1
*
lll
measure
vm
Vi=2m
v( int21 ) = 0
variable
L1
*
inductor
L l = 0 . 5m Lh=5m I t =50u
' ( i ( Vm21 ) < { I t }
current
0
0
dc
( discrete
setup )
−1
through
?
{ Ll }
:
{Lh } ) '
*
v( int21 )
inductor
0
{ Vi }
. control
set
noaskquit
tran
1u
plot
i (Vm)
100u
uic
plot
i ( vm21 )
plot
i (vm)− i ( vm21 )
i ( vm33 )
i ( vm33 )
. endc
. end
3.2.13 Capacitor or inductor with initial conditions
The simulator supports the speci cation of voltage and current initial conditions on capacitor and inductor
These models are not the standard ones supplied with SPICE3, but are
in fact code models which can be substituted for the SPICE models when realistic initial
conditions are required. For details please refer to chapt. 13. A XSPICE deck example using these
models, respectively.
models is shown below:
*
* This circuit contains a capacitor and an inductor with
CHAPTER 3. CIRCUIT ELEMENTS AND MODELS
48
* initial conditions on them. Each of the components
* has a parallel resistor so that an exponential decay
* of the initial condition occurs with a time constant of
* 1 second.
*
a1 1 0 cap
.model cap capacitor (c=1000uf ic=1)
r1 1 0 1k
*
a2 2 0 ind
.model ind inductor (l=1H ic=1)
r2 2 0 1.0
*
.control
tran 0.01 3
plot v(1) v(2)
.endc
.end
3.2.14 Switches
General form:
SXXXXXXX N+ N− NC+ NC− MODEL
WYYYYYYY N+ N− VNAM MODEL
Examples:
s1
1
2
3
4
s w i t c h 1 ON
s2
5
6
3
0
sm2
Switch1
1
2
10
off
0
smodel1
w1 1
2
vclock
W2 3
0
vramp sm1 ON
wreset
5
6
switchmod1
vclck
lossyswitch
OFF
Nodes 1 and 2 are the nodes between which the switch terminals are connected. The model name is
mandatory while the initial conditions are optional. For the voltage controlled switch, nodes 3 and 4 are
the positive and negative controlling nodes respectively. For the current controlled switch, the controlling
current is that through the speci ed voltage source. The direction of positive controlling current ow is
from the positive node, through the source, to the negative node.
3.2.15 Switch Model (SW/CSW)
The switch model allows an almost ideal switch to be described in ngspice. The switch is not quite ideal,
in that the resistance can not change from 0 to in nity, but must always have a nite positive value. By
proper selection of the on and o resistances, they can be eectively zero and in nity in comparison to
other circuit elements. The parameters available are:
Name
Parameter
Units
Default
VT
threshold voltage
V
0.0
Switch model
S
IT
threshold current
A
0.0
W
VH
hysteresis voltage
V
0.0
S
IH
hysteresis current
A
0.0
W
RON
on resistance
o resistance
Ω
Ω
1.0
1/GM IN 3
S,W
ROFF
S,W
The use of an ideal element that is highly nonlinear such as a switch can cause large discontinuities to
occur in the circuit node voltages. A rapid change such as that associated with a switch changing state
can cause numerical round-o or tolerance problems leading to erroneous results or time step di culties.
The user of switches can improve the situation by taking the following steps:
First, it is wise to set ideal switch impedances just high or low enough to be negligible with respect
to other circuit elements. Using switch impedances that are close to "ideal" in all cases aggravates
3.2. ELEMENTARY DEVICES
49
the problem of discontinuities mentioned above.
Of course, when modeling real devices such as
MOSFETS, the on resistance should be adjusted to a realistic level depending on the size of the
device being modeled.
If a wide range of ON to OFF resistance must be used in the switches (ROFF/RON >1e+12), then
the tolerance on errors allowed during transient analysis should be decreased by using the
control line and specifying
TRTOL
.OPTIONS
to be less than the default value of 7.0.
When switches are placed around capacitors, then the option
CHGTOL
should also be reduced.
Suggested values for these two options are 1.0 and 1e-16 respectively. These changes inform ngspice
to be more careful around the switch points so that no errors are made due to the rapid change in
the circuit.
50
CHAPTER 3. CIRCUIT ELEMENTS AND MODELS
Chapter 4
Voltage and Current Sources
4.1
Arbitrary Phase Sources
The XSPICE simulator supports arbitrary phase independent sources that output at TIME=0.0 a value
corresponding to some speci ed phase shift. Other versions of SPICE use the TD (delay time) parameter
to set phase-shifted sources to their time-zero value until the delay time has elapsed. The XSPICE phase
parameter is speci ed in degrees and is included after the SPICE3 parameters normally used to specify
an independent source. Partial XSPICE deck examples of usage for pulse and sine waveforms are shown
below:
* Phase shift is specified after Berkeley defined parameters
* on the independent source cards. Phase shift for both of the
* following is specified as +45 degrees
*
v1 1 0 0.0 sin(0 1 1k 0 0 45.0)
r1 1 0 1k
*
v2 2 0 0.0 pulse(-1 1 0 1e-5 1e-5 5e-4 1e-3 45.0)
r2 2 0 1k
*
4.2
Independent Sources
General form:
VXXXXXXX N+ N− < DC/TRAN VALUE> >>
+ >> >>
IYYYYYYY N+ N− < DC/TRAN VALUE> >>
+ >> >>
Examples:
VCC 10
0 DC 6
VIN 13
2
ISRC
23
0 . 0 0 1 AC 1
2 1 AC 0 . 3 3 3
VMEAS 12
VCARRIER 1
n+
1
1
1MEG)
4 5 . 0 SFFM( 0
0 DISTOF1
0.1
0 DISTOF2
10K 5
1K)
− 90.0
0.01
5 AC 1 DISTOF1 DISTOF2
and
1
9
VMODULATOR 2
IIN1
SIN ( 0
n-
0.001
are the positive and negative nodes, respectively. Note that voltage sources need not be
grounded. Positive current is assumed to ow from the positive node, through the source, to the negative
node. A current source of positive value forces current to ow out of the
into the
n- node.
n+ node, through the source, and
Voltage sources, in addition to being used for circuit excitation, are the ammeters for
ngspice, that is, zero valued voltage sources may be inserted into the circuit for the purpose of measuring
current. They of course have no eect on circuit operation since they represent short-circuits.
51
CHAPTER 4. VOLTAGE AND CURRENT SOURCES
52
DC/TRAN
is the dc and transient analysis value of the source. If the source value is zero both for dc
and transient analyses, this value may be omitted. If the source value is time-invariant (e.g., a power
supply), then the value may optionally be preceded by the letters DC.
ACMAG
ACPHASE is the ac phase. The source is set to this value in the ac
ACMAG is omitted following the keyword AC, a value of unity is assumed. If ACPHASE is omitted,
a value of zero is assumed. If the source is not an ac small-signal input, the keyword AC and the ac values
is the ac magnitude and
analysis. If
are omitted.
DISTOF1 and DISTOF2 are the keywords that specify that the independent source has distortion inputs
F1 and F2 respectively (see the description of the .DISTO control line). The keywords
at the frequencies
may be followed by an optional magnitude and phase. The default values of the magnitude and phase
are 1.0 and 0.0 respectively.
Any independent source can be assigned a time-dependent value for transient analysis. If a source is
assigned a time-dependent value, the time-zero value is used for dc analysis. There are ve independent
source functions:
pulse,
exponential,
sinusoidal,
piece-wise linear,
and single-frequency FM.
If parameters other than source values are omitted or set to zero, the default values shown are assumed.
(TSTEP is the printing increment and
TSTOP is the nal time (see the .TRAN control line for explanation)).
4.2.1 Pulse
General form:
PULSE( V1 V2 TD TR TF PW PER)
Examples:
VIN 3
0 PULSE( − 1
1
2NS 2NS 2NS 50NS 1 0 0NS )
Name
Parameter
Default Value
Units
V1
Initial value
-
V2
Pulsed value
-
V, A
V, A
TD
Delay time
0.0
sec
TR
Rise time
TSTEP
sec
TF
Fall time
TSTEP
sec
PW
Pulse width
TSTOP
sec
PER
Period
TSTOP
sec
A single pulse so speci ed is described by the following table:
Time
Value
0
V1
TD
V1
TD+TR
V2
TD+TR+PW
V2
TD+TR+PW+TF
V1
TSTOP
V1
Intermediate points are determined by linear interpolation.
4.2. INDEPENDENT SOURCES
53
4.2.2 Sinusoidal
General form:
SIN (VO VA FREQ TD THETA)
Examples:
VIN 3
0
SIN ( 0
Name
1
1 0 0MEG 1NS 1 E10 )
Parameter
Default Value
Units
VO
Oset
-
VA
Amplitude
-
FREQ
Frequency
1/T ST OP
V, A
V, A
Hz
TD
Delay
0.0
THETA
Damping factor
0.0
sec
1/sec
The shape of the waveform is described by the following formula:
(
V (t) =
V0
V 0 + V Ae−(t−T D)T HET A sin (2πF REQ (t − T D))
if 0 ≤ t < T D
if T D ≤ t < T ST OP
(4.1)
4.2.3 Exponential
General Form:
EXP( V1 V2 TD1 TAU1 TD2 TAU2)
Examples:
VIN 3
0 EXP( − 4
Name
−1
2NS 3 0NS 60NS 40NS )
Parameter
Default Value
Units
V1
Initial value
-
V2
pulsed value
-
V, A
V, A
TD1
rise delay time
0.0
sec
TAU1
rise time constant
TSTEP
sec
TD2
fall delay time
TD1+TSTEP
sec
TAU2
fall time constant
TSTEP
sec
The shape of the waveform is described by the following formula:
Let
V 21 = V 2 − V 1 V 12 = V 1 − V 2:
V1
if 0 ≤ t < T D1,
(t−T D1)
− T AU 1
if T D1 ≤ t < T D2,
V (t) = V 1 + V 21 1 − e
(t−T D1)
(t−T D2)
V 1 + V 21 1 − e− T AU 1 + V 12 1 − e− T AU 2
if T D2 ≤ t < T ST OP.
(4.2)
4.2.4 Piece-Wise Linear
General Form:
PWL( T1 V1 )
Examples:
VCLOCK 7
5 PWL( 0
−7
Each pair of values (Ti ,
Ti .
1 0NS
Vi )
−7
1 1NS
−3
1 7NS
−3
1 8NS
−7
speci es that the value of the source is
5 0NS
Vi
−7)
r =0 t d =15NS
(in Volts or Amps) at time =
The value of the source at intermediate values of time is determined by using linear interpolation on
the input values. The parameter r determines a repaet time point. If r is not given, the whole sequence
of values (Ti ,
from
Vi )
time = 0
to
is issued once, then the output stays at its nal value. If
time = Tn
is repeated forever. If
r = 10ns,
r = 0,
the whole sequence
the sequence between 10ns and 50ns is
repeated forever. the r value has to be one of the time points T1 to Tn of the PWL sequence. If td is
given, the whole PWL sequence is delayed by a delay time
be patched, td and r are not yet available.
time = td.
The current source still needs to
CHAPTER 4. VOLTAGE AND CURRENT SOURCES
54
4.2.5 Single-Frequency FM
General Form:
SFFM(VO VA FC MDI FS )
Examples:
V1 1 2
0 SFFM( 0
Name
1M 2 0K 5
1K)
Parameter
Default value
Units
VO
Oset
-
VA
Amplitude
-
FC
Carrier frequency
1/T ST OP
V, A
V, A
Hz
MDI
Modulation index
FS
Signal frequency
1/T ST OP
Hz
The shape of the waveform is described by the following equation:
V (t) = VO + VA sin (2πF Ct + M DI sin (2πF St))
(4.3)
Chapter 5
Linear Dependent Sources
Ngspice allows circuits to contain linear dependent sources characterized by any of the four equations
i = gv v = ev i = f i v = hi
g , e, f , and h are constants
where
representing transconductance, voltage gain, current gain, and
transresistance, respectively. Non-linear dependent sources for voltages or currents (B, E, G) are described
in chapter 6.
5.1
Linear Voltage-Controlled Current Sources (VCCS)
General form:
GXXXXXXX N+ N− NC+ NC− VALUE
Examples:
G1 2
n+
0
5
and
0
n-
0 . 1MMHO
are the positive and negative nodes, respectively. Current ow is from the positive node,
through the source, to the negative
node.
nc+ and nc- are the positive and negative controlling nodes, respectively. value is the transcon-
ductance (in mhos).
5.2
Linear Voltage-Controlled Voltage Sources (VCVS)
General form:
EXXXXXXX N+ N− NC+ NC− VALUE
Examples:
E1 2
3
n+
14
1
2.0
n- is the negative
value is the
is the positive node, and
controlling nodes, respectively.
node.
nc+
and
nc-
are the positive and negative
voltage gain.
5.3
Linear Current-Controlled Current Sources (CCCS)
General form:
FXXXXXXX N+ N− VNAM VALUE
Examples:
F1
13
n+
5 VSENS 5
and
n-
are the positive and negative nodes, respectively. Current ow is from the positive node,
through the source, to the negative node.
vnam
is the name of a voltage source through which the
55
CHAPTER 5. LINEAR DEPENDENT SOURCES
56
Dependent Polynomial Sources
Source Type
Instance Card
POLYNOMIAL VCVS
EXXXXXXX N+ N- (POLY (ND)) NC1+ NC1- P0 (P1...)
POLYNOMIAL VCCS
GXXXXXXX N+ N- (POLY (ND)) NC1+ NC1- P0 (P1...)
POLYNOMIAL CCCS
FXXXXXXX N+ N- (POLY (ND)) VNAM1 !VNAM2...? P0 (P1...)
POLYNOMIAL CCVS
HXXXXXXX N+ N- (POLY (ND)) VNAM1 !VNAM2...? P0 (P1...)
Table 5.1: Dependent Polynomial Sources
controlling current ows.
The direction of positive controlling current ow is from the positive node,
through the source, to the negative node of
5.4
vnam. value
is the current gain.
Linear Current-Controlled Voltage Sources (CCVS)
General form:
HXXXXXXX n+ n− vnam
value
Examples:
HX 5
n+
1 7 VZ
and
n-
0 . 5K
are the positive and negative nodes, respectively.
vnam
is the name of a voltage source
through which the controlling current ows. The direction of positive controlling current ow is from the
positive node, through the source, to the negative node of
5.5
vnam. value
is the transresistance (in ohms).
Polynomial Source Compatibility
Dependent polynomial sources available in SPICE2G6 are fully supported in ngspice using the XSPICE
extension. Dependent polynomial sources are not supported in SPICE3 but were reinstated in XSPICE
to allow existing third party models to be incorporated readily into XSPICE. The form used to specify
these sources is shown in Table 5.1.
Chapter 6
Non-linear Dependent Sources
6.1
B source (ASRC)
General form:
BXXXXXXX n+ n− < i =e x p r >
Examples:
B1 0
1
B2 0
1 V=l n ( c o s ( l o g ( v ( 1 , 2 ) ^ 2 ) ) )
I=c o s ( v ( 1 ) ) + s i n ( v ( 2 ) )
B3 3
4
B4 3
4 V=e x p ( p i ^ i ( vdd ) )
B5 2
0 V = V( 1 ) < { Vlow }
− v (3)^4+ v ( 2 ) ^ v ( 1 )
I =17
n+ is the positive
node, and
?
{ Vlow }
:
V( 1 ) > { Vhigh }
n- is the negative node.
?
{ Vhigh }
The values of the
the voltages and currents across and through the device, respectively. If
current source, and if
V
:
V( 1 )
V and I parameters determine
I is given then the device is a
is given the device is a voltage source. One and only one of these parameters
must be given.
The small-signal AC behavior of the nonlinear source is a linear dependent source (or sources) with a
proportionality constant equal to the derivative (or derivatives) of the source at the DC operating point.
The expressions given for
V and I may be any function of voltages and currents through voltage sources in
'time' and 'temper' are available in a transient analysis, re ecting
'hertz' is available in an AC analysis.
'hertz' is zero during transient analysis. Using the variable 'hertz'
the system. In addition, the variables
the actual simulation time and circuit temperature. The variable
'time'
is zero in the AC analysis,
may cost some CPU time if you have a large circuit, because for each frequency the operating point has
to be determined before calculating the AC response.
The following functions of a single real variable are de ned:
Trigonometric functions:
Hyperbolic functions:
cos, sin, tan, acos, asin, atan
cosh, sinh, acosh, asinh, atanh
Exponential and logarithmic:
Other:
exp, ln, log
abs, sqrt, u, u2, uramp,
Functions
of two variables are: min, max, pow
Functions
of three variables are: a ? b:c
The function u is the unit step function, with a value of one for arguments greater than zero and a value
of zero for arguments less than zero. The function u2 returns a value of zero for arguments less than
zero, one for arguments greater than one and assumes the value of the argument between these limits.
The function "uramp" is the integral of the unit step: for an input x, the value is zero if x is less than
zero, or if x is greater than zero the value is x. These three functions are useful in synthesizing piece-wise
non-linear functions, though convergence may be adversely aected.
The following standard operators are de ned: +, -, *, /, ^, unary Logical operators are !=, >=, <=, ==,>,<, |, &&, ! .
57
CHAPTER 6. NON-LINEAR DEPENDENT SOURCES
58
A ternary function is de ned as
a ?
b : c
, which means
IF a, THEN b, ELSE c.
Be sure to
place a space in front of ' ?' to allow the parser distinguishing it from other tokens.
Example: Ternary function
*
*
B
source
C.
P.
. param
test
Basso
Clamped
voltage
" S w i t c h e d −mode
source
power
supplies " ,
New York ,
2008
?
V( 1 )
Vhigh = 4 . 6
. param Vlow = 0 . 4
Vin1
Bcl
1
2
0 DC 0 PWL( 0
0
1u
0 V = V( 1 ) < Vlow
5)
?
Vlow
:
V( 1 ) > Vhigh
Vhigh
:
. control
set
noaskquit
tran
5n
1u
p l o t V( 2 )
v s V( 1 )
. endc
. end
If the argument of log, ln, or sqrt becomes less than zero, the absolute value of the argument is used.
If a divisor becomes zero or the argument of log or ln becomes zero, an error will result. Other problems
may occur when the argument for a function in a partial derivative enters a region where that function
is unde ned.
Parameters may be used like {Vlow} shown in the example above. Parameters will be evaluated upon
set up of the circuit, vectors like V(1) will be evaluated during the simulation.
To get time into the expression you can integrate the current from a constant current source with a
capacitor and use the resulting voltage (don't forget to set the initial voltage across the capacitor).
Non-linear resistors, capacitors, and inductors may be synthesized with the nonlinear dependent
source. Nonlinear resistors, capacitors and inductors are implemented with their linear counterparts by
a change of variables implemented with the nonlinear dependent source. The following subcircuit will
implement a nonlinear capacitor:
Example: Non linear capacitor
. Subckt
*
Bx :
Bx 1
*
*
0
Cx :
Cx 2
*
Fx
pos
neg
f ( input
voltage )
v = f ( v ( pos , neg ) )
linear
0
Vx :
Vx 2
nlcap
calculate
capacitance
1
Ammeter
to
measure
current
into
the
capacitor
1 DC 0 V o l t s
Drive
pos
the
current
through
Cx b a c k
into
the
circuit
n e g Vx 1
. ends
Example for f(v(pos,neg)):
Bx 1
0 V = v ( pos , neg ) * v ( pos , neg )
Non-linear resistors or inductors may be described in a similar manner. An example for a nonlinear
resistor using this template is shown below.
6.1. B SOURCE (ASRC)
59
Example: Non linear resistor
* use o f ' hertz '
* . param r b a s e =1k
* some t e s t s
variable
1
0
B2
2
0 V = v(33)* hertz
b3
3
0 DC 0 AC 1
Translate
. Subckt
*
Bx :
*
2
*
***
source
−1
voltage )
/
{ rb }
/
s q r t (HERTZ)
*
v ( pos ,
neg )
1
to
1
measure
current
into
the
resistor
DC 0 V o l t s
the
pos
to B
r b=r b a s e
resistance
0
Drive
Fx
v =
Ammeter
2
0 R= '1 k / s q r t (HERTZ) '
neg
f ( input
0
linear
Vx :
Vx
pos
calculate
Rx :
*
R1 10
nlres
1
Rx
resistor
0 V = 6 . 2 8 3 e3 / ( h e r t z +6.283 e3 ) * v ( 3 3 )
V1 3 3
Bx
nonlinear
V = h e r t z *v ( 3 3 )
B1
***
in
current
neg
through
Rx b a c k
into
the
circuit
Vx 1
. ends
Xres
33
* Rres
Vres
10
33
10
nlres
10
r b=1k
1k
0 DC 0
. control
define
check ( a , b )
ac
10
*
lin
some
print
if
100
−
b))
checks
v(1)
v(2)
check ( v ( 1 ) ,
echo
vecmax ( a b s ( a
1k
"INFO :
v(3)
f r e q u e n c y ) < 1 e −12
ok "
end
plot
v r e s#b r a n c h
. endc
. end
par('expression'):
The B source syntax may also be used in output lines like
.plot
as algebraic ex-
pressions for output (see chapt.16.4.6 ).
Piecewise Linear Function:
pwl
Both B source types may contain a piece-wise linear dependency of one network variable:
Example: pwl_current
Bdio
1
0
I = pwl ( v (A) ,
0 ,0 ,
3 3 , 1 0m,
1 0 0 , 3 3m,
2 0 0 , 5 0m)
v(A) is the independent variable x. Each pair of values following describes the x,y functional relation:
In this example at node A voltage of 0V the current of 0A is generated - next pair gives 10mA owing
from ground to node 1 at 33V on node A and so forth.
The same is possible for voltage sources:
Example: pwl_voltage
Blimit
b
0 V = pwl ( v ( 1 ) ,
−4 ,0 , −2 ,2 ,
2 ,4 ,
4 ,5 ,
6 ,5)
Monotony of the independent variable in the pwl de niton is checked - nonmonotonic x entries will
stop the program execution.
v(1) may be replaced by a controlling current source.
replaced by an expression, e.g.
de ned before by a
below:
-2*i(Vin).
.param statement.
v(1) may also be
The value pairs may also be parameters, which have to be
An example for the pwl function using all of these options is shown
CHAPTER 6. NON-LINEAR DEPENDENT SOURCES
60
Example: pwl function in B source
Demonstrates
*
Also
usage
emulates
. param
x0=−4 y0=0
. param
x1=−2 y1=2
. param
x2=2 y2=−2
. param
x3=4 y3=1
. param
xx0=x0 −1
. param
xx3=x3+1
Vin
1
R 1
*
0
no
0
of
limits
outside
TABLE f u n c t i o n
like
Btest3
0
of
*
3
more
0
' x0 ' , ' y0 ' ,
4
0
and
an B
source
(ASRC)
limits
( continues
linearily )
' x2 ' , ' y2 ' ,
:
' x3 ' )
' x3 ' , ' y3 ' )
limits :
' x0 ' )
?
' y0 '
(v(1) <
' x2 ' , ' y2 ' ,
?
' x3 ' , ' y3 ' )
with
limits :
with
limits :
:
' y3 '
' x0 ' , ' y0 ' ,
' x1 ' , ' y1 ' ,
' x2 ' , ' y2 ' ,
+
' x3 ' , ' y3 ' ,
controlled
by
' xx3 ' , ' y3 ' )
current
efficient
5
values
' x1 ' , ' y1 ' ,
e l e g a n t TABLE f u n c t i o n
+
Btest5
x
I = pwl ( v ( 1 ) ,
' xx0 ' , ' y0 ' ,
more
' x0 ' , ' y0 ' ,
' x1 ' , ' y1 ' ,
+
+
in
with
tabulated
with
I = (v(1) <
efficient
Btest4
the
I = pwl ( v ( 1 ) ,
+ pwl ( v ( 1 ) ,
*
*
function
DC=0V
2
+
pwl
2
Btest2
*
the
t h e TABLE f u n c t i o n
and
e l e g a n t TABLE f u n c t i o n
I = pwl ( − 2 * i ( Vin ) ,
0
' xx0 ' , ' y0 ' ,
' x0 ' , ' y0 ' ,
+
' x1 ' , ' y1 ' ,
+
' x2 ' , ' y2 ' ,
+
' x3 ' , ' y3 ' ,
Rint2
2
0
1
Rint3
3
0
1
Rint4
4
0
1
Rint5
5
0
1
' xx3 ' , ' y3 ' )
. control
dc
Vin
plot
−6
v(2)
6
v(3)
0.2
v (4) −0.5
v (5)+0.5
. endc
. end
6.2
E source (non-linear voltage source)*
General form:
EXXXXXXX n+ n− v o l = ' e x p r '
Examples:
E41
4
0
vol =
Expression
'V( 3 ) * V(3) − O f f s '
may be an equation or an expression containing node voltages or branch currents (in
the form of i(vm)) and any other terms as given for the B source and described in chapter 6.1. It may
6.3. G SOURCE (NON-LINEAR CURRENT SOURCE)*
61
contain parameters (2.8.1).
6.3
G source (non-linear current source)*
General form:
GXXXXXXX n+ n− c u r = ' e x p r '
Examples:
G51
55
225
cur =
Expression
'V( 3 ) * V(3) − O f f s '
may be an equation or an expression containing node voltages or branch currents (in
the form of i(vm)) and any other terms as given for the B source and described in chapter 6.1. It may
contain parameters (2.8.1). An example le is given below.
Example input le:
VCCS,
non− l i n e a r
VCVS,
. param
Vi=1
. param
O f f s = ' 0 . 0 1 * Vi '
*
VCCS d e p e n d i n g
B21
*
22
R21
*
0
21
dc
0
55
55
current
0
0
cur =
dc
t h r o u g h VCCS
1
on V( 3 )
0 V = V( 3 ) * V( 3 )
int2
E1 1
0
int2
R1 1
0
1
0
1
new VCVS d e p e n d i n g
E41
4
R4 4
0
0
vol =
on V( 3 )
'V( 3 ) * V(3) − O f f s '
1
control
V1 3
on V( 3 )
'V( 3 ) * V(3) − O f f s '
0
VCVS d e p e n d i n g
B31
*
t h r o u g h VCCS
1
measure
R51
*
1
0
225
vm5 2 2 5
*
0
current
new VCCS d e p e n d i n g
G51
*
int1
measure
vm 2 2
on V( 3 )
0 V = V( 3 ) * V( 3 )
int1
G1 2 1
dependency
voltage
0 PWL( 0
0
100u
{ Vi } )
. control
set
noaskquit
tran
10 n
plot
i ( E1 )
100u
i ( E41 )
uic
plot
i (vm)
i ( vm5 )
. endc
. end
*) To get this functionality, the compatibility mode has to be set in
spinit by set ngbehavior=all.
62
CHAPTER 6. NON-LINEAR DEPENDENT SOURCES
Chapter 7
Transmission Lines
Ngspice implements both the original spice3f5 transmission lines models and the one introduced with
kspice.
The latter provide an improved transient analysis of lossy transmission lines.
Unlike spice
models, which uses the state-based approach to simulate lossy transmission lines, kspice simulates lossy
transmission lines and coupled multiconductor line systems using the recursive convolution method. The
impulse response of an arbitrary transfer function can be determined by deriving a recursive convolution
from the Pade approximations of the function. We use this approach for simulating each transmission
line's characteristics and each multiconductor line's modal functions. This method of lossy transmission
line simulation has been proved to give a speedup of one to two orders of magnitude over spice3f5.
7.1
Lossless Transmission Lines
General form:
TXXXXXXX N1 N2 N3 N4 Z0=VALUE >
+
Examples:
T1 1
n1
0
2
0
Z0=50 TD=10NS
and
n2
are the nodes at port 1;
n3
and
n4
are the nodes at port 2.
z0
is the characteristic
impedance. The length of the line may be expressed in either of two forms. The transmission delay,
may be speci ed directly (as td=10ns, for example). Alternatively, a frequency
with
nl,
f may be given,
td,
together
the normalized electrical length of the transmission line with respect to the wavelength in the
line at the frequency f .
If a frequency is speci ed but
nl
is omitted, 0.25 is assumed (that is, the
frequency is assumed to be the quarter-wave frequency). Note that although both forms for expressing
the line length are indicated as optional, one of the two must be speci ed.
Note that this element models only one propagating mode. If all four nodes are distinct in the actual
circuit, then two modes may be excited.
To simulate such a situation, two transmission-line elements
are required. (see the example in chapt. 21.7 for further clari cation.) The (optional) initial condition
speci cation consists of the voltage and current at each of the transmission line ports.
initial conditions (if any) apply only if the
UIC
option is speci ed on the
.TRAN
Note that the
control line.
Note that a lossy transmission line (see below) with zero loss may be more accurate than than the
lossless transmission line due to implementation details.
7.2
Lossy Transmission Lines
General form:
OXXXXXXX n1
n2
n3
n4 mname
Examples:
O23 1
0
2
0 LOSSYMOD
OCONNECT 10
5
20
5 INTERCONNECT
63
CHAPTER 7. TRANSMISSION LINES
64
This is a two-port convolution model for single conductor lossy transmission lines.
nodes at port 1;
n3
and
n4
n1
and
n2
are the
are the nodes at port 2. Note that a lossy transmission line with zero loss
may be more accurate than than the lossless transmission line due to implementation details.
7.2.1 Lossy Transmission Line Model (LTRA)
The uniform RLC/RC/LC/RG transmission line model (referred to as the LTRA model henceforth)
models a uniform constant-parameter distributed transmission line.
The RC and LC cases may also
be modelled using the URC and TRA models; however, the newer LTRA model is usually faster and
more accurate than the others. The operation of the LTRA model is based on the convolution of the
transmission line's impulse responses with its inputs (see [8]).
The LTRA model takes a number of
parameters, some of which must be given and some of which are optional.
Name
Parameter
Units/Type
Default
R
resistance/length
Ω/unit
0.0
0.2
L
inductance/length
H/unit
0.0
9.13e-9
G
conductance/length
mhos/unit
0.0
0.0
F/unit
C
capacitance/length
LEN
length of line
REL
breakpoint control
ABS
breakpoint control
NOSTEPLIMIT
don't limit timestep to less than
NOCONTROL
don't do complex timestep
Example
0.0
3.65e-12
no default
1.0
1
0.5
arbitrary unit
1
5
ag
not set
set
ag
not set
set
line delay
control
LININTERP
use linear interpolation
ag
not set
set
MIXEDINTERP
use linear when quadratic seems
ag
not set
set
RELTOL
1.0e-3
ABSTOL
1.0e-9
ag
not set
set
ag
not set
set
bad
COMPACTREL
special reltol for history
compaction
COMPACTABS
special abstol for history
compaction
TRUNCNR
use Newton-Raphson method
for timestep control
TRUNCDONTCUT
don't limit timestep to keep
impulse-response errors low
The following types of lines have been implemented so far:
RLC (uniform transmission line with series loss only),
RC (uniform RC line),
LC (lossless transmission line),
RG (distributed series resistance and parallel conductance only).
Any other combination will yield erroneous results and should not be tried. The length
must be speci ed.
NOSTEPLIMIT
LEN
of the line
is a ag that will remove the default restriction of limiting time-steps
to less than the line delay in the RLC case.
NOCONTROL
is a ag that prevents the default limiting of the
time-step based on convolution error criteria in the RLC and RC cases. This speeds up simulation but
may in some cases reduce the accuracy of results.
LININTERP is a ag that, when speci ed, will use linear
MIXEDINTERP
interpolation instead of the default quadratic interpolation for calculating delayed signals.
is a ag that, when speci ed, uses a metric for judging whether quadratic interpolation is not applicable
and if so uses linear interpolation; otherwise it uses the default quadratic interpolation.
TRUNCDONTCUT is a
ag that removes the default cutting of the time-step to limit errors in the actual calculation of impulseresponse related quantities.
COMPACTREL
and
COMPACTABS
are quantities that control the compaction
of the past history of values stored for convolution. Larger values of these lower accuracy but usually
TRYTOCOMPACT option, described in the .OPTIONS
TRUNCNR is a ag that turns on the use of Newton-Raphson iterations to determine an appropriate
increase simulation speed. These are to be used with the
section.
timestep in the timestep control routines. The default is a trial and error procedure by cutting the previous
timestep in half.
REL
and
ABS
are quantities that control the setting of breakpoints.
7.3. UNIFORM DISTRIBUTED RC LINES
65
The option most worth experimenting with for increasing the speed of simulation is
REL.
The default
value of 1 is usually safe from the point of view of accuracy but occasionally increases computation time.
A value greater than 2 eliminates all breakpoints and may be worth trying depending on the nature of
the rest of the circuit, keeping in mind that it might not be safe from the viewpoint of accuracy.
Breakpoints may usually be entirely eliminated if it is expected the circuit will not display sharp
discontinuities.
Values between 0 and 1 are usually not required but may be used for setting many
breakpoints.
COMPACTREL may also be experimented with when the option TRYTOCOMPACT is speci ed in a .OPTIONS
card. The legal range is between 0 and 1. Larger values usually decrease the accuracy of the simulation but
in some cases improve speed. If
TRYTOCOMPACT
is not speci ed on a
.OPTIONS
card, history compaction
is not attempted and accuracy is high.
NOCONTROL, TRUNCDONTCUT
7.3
and
NOSTEPLIMIT
also tend to increase speed at the expense of accuracy.
Uniform Distributed RC Lines
General form:
UXXXXXXX n1
n2
n3 mname
l =l e n
Examples:
U1 1
2
URC2 1
n1
0 URCMOD L=50U
12
and
2 UMODL l =1MIL N=6
n2
are the two element nodes the RC line connects, while
capacitances are connected.
lumps,
mname
is the model name,
len
n3
is the node to which the
is the length of the RC line in meters.
if speci ed, is the number of lumped segments to use in modelling the RC line (see the model
description for the action taken if this parameter is omitted).
7.3.1 Uniform Distributed RC Model (URC)
The URC model is derived from a model proposed by L. Gertzberrg in 1974. The model is accomplished
by a subcircuit type expansion of the URC line into a network of lumped RC segments with internally
generated nodes. The RC segments are in a geometric progression, increasing toward the middle of the
URC line, with
K
as a proportionality constant. The number of lumped segments used, if not speci ed
for the URC line device, is determined by the following formula:
C
2
log Fmax R
L L 2πL
N=
(K−1)
K
2
(7.1)
log K
The URC line is made up strictly of resistor and capacitor segments unless the
ISPERL parameter is given
a nonzero value, in which case the capacitors are replaced with reverse biased diodes with a zero-bias
junction capacitance equivalent to the capacitance replaced, and with a saturation current of
amps per meter of transmission line and an optional series resistance equivalent to
RSPERL
ISPERL
ohms per
meter.
7.4
Name
Parameter
Units
Default
Example
Area
K
Propagation Constant
-
2.0
1.2
-
FMAX
Maximum Frequency of interest
Hz
1.0 G
6.5 Meg
-
RPERL
Resistance per unit length
Ω/m
1000
10
-
CPERL
Capacitance per unit length
F/m
10e-15
1 pF
-
ISPERL
Saturation Current per unit length
A/m
0
-
-
RSPERL
Diode Resistance per unit length
Ω/m
0
-
-
KSPICE Lossy Transmission Lines
Unlike SPICE3, which uses the state-based approach to simulate lossy transmission lines, KSPICE simulates lossy transmission lines and coupled multiconductor line systems using the recursive convolution
method. The impulse response of an arbitrary transfer function can be determined by deriving a recursive
CHAPTER 7. TRANSMISSION LINES
66
convolution from the Pade approximations of the function. NGSPICE is using this approach for simulating each transmission line's characteristics and each multiconductor line's modal functions. This method
of lossy transmission line simulation has proven to give a speedup of one to two orders of magnitude over
SPICE3E.
Additional Documentation Available:
S. Lin and E. S. Kuh, "Pade Approximation Applied to Transient Simulation of Lossy Coupled
Transmission Lines," Proc. IEEE Multi-Chip Module Conference, 1992, pp. 52-55.
S. Lin, M. Marek-Sadowska, and E. S. Kuh, "SWEC: A StepWise Equivalent Conductance Timing
Simulator for CMOS VLSI Circuits," European Design Automation Conf., February 1991, pp. 142148.
S. Lin and E. S. Kuh, "Transient Simulation of Lossy Interconnect," Proc.
Design Automation
Conference, Anaheim, CA, June 1992, pp. 81-86.
7.4.1 Single Lossy Transmission Line (TXL)
General form:
YXXXXXXX N1 0 N2 0 mname
Example:
Y1 1
0
2
0 ymod LEN=2
.MODEL ymod
n1
and
n2
txl
R= 1 2 . 4 5 L= 8 . 9 7 2 e −9 G=0 C= 0 . 4 6 8 e −12
l e n g t h =16
are the nodes of the two ports; Optional instance parameter
len
is the length of the line
may be expressed in [m].
The TXL model takes a number of parameters:
Name
Parameter
Units/Type
Default
Example
R
resistance/length
Ω/unit
0.0
0.2
0.0
9.13e-9
L
inductance/length
H/unit
G
conductance/length
mhos/unit
0.0
0.0
C
capacitance/length
F/unit
0.0
3.65e-12
LENGTH
length of line
no default
1.0
Model parameter length must be speci ed.
7.4.2 Coupled Multiconductor Line (CPL)
The CPL multiconductor line model, which in theory should be similar to the RLGC model, but without
frequency dependent loss (neither skin eect and nor frequency dependent dielectric loss). Up to 8 coupled
lines are supported in NGSPICE.
General form:
PXXXXXXX NI1
NI2
...
NIX GND1 NO1 NO2
...
NOX GND2 mname
Example:
P1
in1
in2
0
b1
b2
. model PLINE CPL
+R=1 0
1
+L={L11 }
+G=0 0
{ L12 }
{ L22 }
{ C12 }
{ C22 }
0
+C={C11 }
. param
0 PLINE
l e n g t h ={Len }
Len=1 Rs=0
+ C11 = 9 . 1 4 3 5 7 9E−11 C12 = − 9.78265E−12 C22 = 9 . 1 4 3 5 7 8E−11
+ L11 = 3 . 8 3 5 7 2E−7 L12 = 8 . 2 6 2 5 3E−8 L22 = 3 . 8 3 5 7 2E−7
ni1 ... nix are the nodes at port 1 with gnd1; no1 ... nox are the nodes at port 2 with gnd2.
len is the length of the lines may be expressed in [m].
instance parameter
The CPL model takes a number of parameters:
Optional
7.4. KSPICE LOSSY TRANSMISSION LINES
Name
67
Parameter
Units/Type
Default
R
resistance/length
Ω/unit
Example
0.0
0.2
L
inductance/length
H/unit
0.0
9.13e-9
G
conductance/length
mhos/unit
0.0
0.0
C
capacitance/length
F/unit
0.0
3.65e-12
LENGTH
length of line
no default
1.0
All RLGC parameter are given in Maxwell matrix form. For R and G matrix the diagonal elements
must be speci ed, for L and C matrix the lower or upper-triangular elements must speci ed.
parameter LENGTH is a scalar and is mandatory.
Model
68
CHAPTER 7. TRANSMISSION LINES
Chapter 8
DIODEs
8.1
Junction Diodes
General form:
DXXXXXXX n+ n− mname < o f f > < i c =vd>
+
Examples:
DBRIDGE 2
DCLMP 3
10 DIODE1
7 DMOD 3 . 0
IC = 0 . 2
The pn junction (diode) implemented in ngspice expands the one in spice3f5. Perimetral eects and
high injection level have been introduced into the original model and temperature dependence of some
n+ and n- are the positive and negative nodes, respectively. mname is the
area is the area factor, pj is the perimeter factor, and off indicates an (optional) starting
parameters has been added.
model name,
condition on the device for dc analysis.
If the area factor is omitted, a value of 1.0 is assumed.
(optional) initial condition speci cation using
ic
is intended for use with the
uic
option on the
The
.tran
control line, when a transient analysis is desired starting from other than the quiescent operating point.
You should supply the inital voltage across the diode there. The (optional)
temp value is the temperature
.option control
at which this device is to operate, and overrides the temperature speci cation on the
line. The temperatire of each istance can be can be speci ed as an oset to the circuit temperature with
the
dtemp
8.2
option.
Diode Model (D)
is and n. An ohmic resistance,
tt, and a nonlinear depletion
layer capacitance which is determined by the parameters cjo, vj, and m. The temperature dependence
of the saturation current is de ned by the parameters eg, the energy and xti, the saturation current
temperature exponent. The nominal temperature at which these parameters were measured is tnom,
which defaults to the circuit-wide value speci ed on the .options control line. Reverse breakdown is
modelled by an exponential increase in the reverse diode current and is determined by the parameters bv
and ibv (both of which are positive numbers).
The dc characteristics of the diode are determined by the parameters
rs,
is included.
Charge storage eects are modeled by a transit time,
69
CHAPTER 8. DIODES
70
Junction DC parameters
Name
Parameter
BV
Reverse breakdown voltage
Units Default Example Scale factor
IBV
Current at breakdown voltage
IK (IKF)
Forward knee current
IKR
Reverse knee current
IS (JS)
Saturation current
JSW
Sidewall saturation current
N
Emission coe cient
RS
Ohmic resistance
V
A
A
A
A
A
∞
40
1.0e-3
1.0e-4
1.0e-3
1.0e-6
1.0e-3
1.0e-6
1.0e-14
1.0e-16
area
1.0e-14
1.0e-15
perimeter
-
1
1.5
Ω
0.0
100
Junction capacitance parameters
Name
Parameter
CJO (CJ0)
Zero-bias junction bottowall
1/area
Units Default Example Scale factor
F
0.0
2pF
area
F
0.0
.1pF
perimeter
-
0.5
-
-
0.5
-
capacitance
CJP (CJSW)
Zero-bias junction sidewall capacitance
FC
Coe cient for forward-bias depletion
bottomwall capacitance formula
FCS
Coe cient for forward-bias depletion
sidewall capacitance formula
M (MJ)
Area junction grading coe cient
-
0.5
0.5
MJSW
Periphery junction grading coe cient
-
0.33
0.5
VJ
Junction potential
1
0.6
PHP
Periphery junction potential
V
V
1
0.6
TT
Transit-time
sec
0
0.1ns
Units Default
Example
Temperature eects
Name Parameter
EG
Activation energy
TM1
1st order tempco for MJ
TM2
2nd order tempco for MJ
TNOM
Parameter measurement temperature
TRS
1st order tempco for RS
TRS2
2nd order tempco for RS
TTT1
1st order tempco for TT
TTT2
2nd order tempco for TT
XTI
1.11
1.11 Si
0.69 Sbd
0.67 Ge
1/°C
1/°C 2
0.0
-
0.0
-
°C
1/°C
1/°C 2
1/°C
1/°C 2
27
50
0.0
-
0.0
-
0.0
-
Saturation current temperature exponent
Noise modeling
Name Parameter
-
0.0
3.0
-
3.0
2.0
pn
Sbd
Units Default Example Scale factor
KF
Flicker noise coe cient
-
0
AF
Flicker noise exponent
-
1
8.3
eV
Scale factor
Diode Equations
The junction diode is the the basic semiconductor device and the simplest one modeled in ngspice, but
it's model is quite complex, even if not all the physical phenomena aecting a pn junction are modelled.
The diode is modeled in three dierent regions:
Forward bias :
the anode is more positive than the cathode, the diode is "on" and can conduct large
currents. To avoid convergence problems and unrealistic high current, it is better to specify a series
resistance to limit current with
rs
model parameter.
8.3. DIODE EQUATIONS
71
Algorithm 8.1 Diode breakdown current calculation
IBVef f < Ibdwn
IBVef f = Ibdwn
BVef f = BV
if
then
else
BVef f = BV − NVt ln(
Reverse bias :
IBVef f
Ibdwn
)
the cathode is more positive than the anode and the diode is "o". A reverse bias
diode conducts a small leakage current.
Breakdown :
the breakdown region is modelled only if the
bv
model parameter is given. When a
diode enters breakdown the current increase exponentially (remember to limit it);
bv
is a positive
value.
Parameters Scaling
Model parameters are scaled using the unitless parameters
area
and
pj
and the multiplier
m
as depicted
below:
AREAef f = AREA · M
P Jef f = PJ · M
ISef f = IS · AREAef f + JSW ∗ P Jef f
IBVef f = IBV · AREAef f
IKef f = IK · AREAef f
IKRef f = IKR · AREAef f
CJef f = CJ0 · AREAef f
CJPef f = CJP · P Jef f
Diode DC, Transient and AC model equations
ID
qVD
if VD ≥ −3 N qkT
ISef f (e N kT − 1) + VD ∗ GM IN,
kT 3
if − BVef f < VD < −3 N qkT
= −ISef f [1 + ( 3N
qVD e ) ] + VD ∗ GM IN,
−q(BVef f +VD )
−IS (e
N kT
) + VD ∗ GM IN, if VD ≤ −BVef f
ef f
(8.1)
The breakdown region must be described with more depth since the breakdown is not modelled in
physically. As written before, the breakdown modelling is based on two model parameters: the "nominal
breakdown voltage"
bv
and the current at the onset of breakdown
ibv.
For the diode model to be
consistent, the current value cannot be arbitrary chosen, since the reverse bias and breakdown regions
must match. When the diode enters breakdown region from reverse bias, the current is calculated using
1
the formula :
Ibdwn = −ISef f (e
−qBV
N kT
− 1)
(8.2)
The computed current is necessary to adjust the breakdown voltage making the two regions match.
The algorithm is a little bit convoluted and only a brief description is given here:
Most real diodes shows a current increase that, at high current levels, does not follow the exponential
relationship given above. This behaviour is due to high level of carriers injected into the junction. High
injection eects (as they are called) are modelled with
IDef f =
rID
I
1+ IKD
,
ik
and
ikr.
if VD ≥ −3 N qkT
ef f
r ID
ID
1+
, otherwise.
(8.3)
IKRef f
Diode capacitance is divided into two dierent terms:
1 if
Depletion capacitance
you look at the source code in le
order taylor series expansion.
diotemp.c
you will discoverthat the exponential relation is replaced with a rst
CHAPTER 8. DIODES
72
Diusion capacitance
Depletion capacitance is composed by two dierent contributes, one associated to the bottom of the
junction (bottowall depletion capacitance) and the other to the periphery (sidewall depletion capacitance).
The basic equations are:
CDiode = Cdif f usion + Cdepletion
Where the depletion capacitance i de ned as:
Cdepletion = Cdeplbw + Cdeplsw
The diusion capacitance, due to the injected minority carriers is modeled with the transit time
Cdif f usion = TT
tt:
∂IDef f
∂VD
The depletion capacitance is more complex to model, since the function used to approximate it diverges
when the diode voltage become greater than the junction built-in potential. To avoid function divergence,
the capacitance function is approximated with a linear extrapolation for applied voltage greater than a
fraction of the junction built-in potential.
Cdeplbw
Cdeplsw =
=
VD −MJ
,
VJ )
VD
1−FC·(1+MJI)+MJ· VJ
(1−FC)(1+MJ)
(
CJef f · (1 −
CJef f ·
if VD < FC · VJ
,
VD −MJSW
,
PHP )
VD
1−FCS·(1+MJSW)+MJSW· PHP
(1+MJSW)
(1−FCS)
otherwise.
(
CJPef f · (1 −
CJPef f ·
if VD < FCS · PHP
,
otherwise.
(8.4)
(8.5)
Temperature dependence
The temperature aects many of the parameters in the equations above, the following equations show
how. One of the most signi cant parameter that varies with the temperature for a semiconductor is the
band-gap energy:
EGnom = 1.16 − 7.02e−4 ·
TNOM2
TNOM + 1108.0
(8.6)
EG(T ) = 1.16 − 7.02e−4 ·
T2
TNOM + 1108.0
(8.7)
The leakeage currents temperature dependence is:
IS(T ) = IS · e
logf actor
N
JSW (T ) = JSW · e
logf actor
N
(8.8)
(8.9)
where "logfactor" is de ned:
logf actor =
EG
EG
T
−
+ XTI · ln(
)
Vt (TNOM) Vt (T )
TNOM
(8.10)
The contact potentials (bottowall an sidewall) temperature dependence is:
T
T
EGnom
EG(T)
V J(T ) = VJ · (
) − Vt (T ) · 3 · ln(
)+
−
TNOM
TNOM
Vt (TNOM)
Vt (T )
T
T
EGnom
EG(T)
P HP (T ) = PHP · (
) − Vt (T ) · 3 · ln(
)+
−
TNOM
TNOM
Vt (TNOM)
Vt (T )
(8.11)
(8.12)
The depletion capacitances temperature dependence is:
V J(T )
−4
CJ(T ) = CJ · 1 + MJ · (4.0e · (T − TNOM) −
+ 1)
VJ
(8.13)
8.3. DIODE EQUATIONS
73
P HP (T )
CJSW (T ) = CJSW · 1 + MJSW · (4.0e−4 · (T − TNOM) −
+ 1)
PHP
(8.14)
The transit time temperature dependence is:
T T (T ) = TT · (1 + TTT1 · (T − TNOM) + TTT2 · (T − TNOM)2 )
(8.15)
The junction grading coe cient temperature dependence is:
M J(T ) = MJ · (1 + TM1 · (T − TNOM) + TM2 · (T − TNOM)2 )
(8.16)
The series resistance temperature dependence is:
RS(T ) = RS · (1 + TRS · (T − TNOM) + TRS2 · (T − TNOM)2 )
(8.17)
Noise model
The diode has three noise contribution, one due to the presence of the parasitic resistance
rs
and the
other two (shot and icker) due to the pn junction.
The thermal noise due to the parasitic resistance is:
i2RS =
4kT ∆f
RS
(8.18)
The shot and icker noise contributions are:
i2d = 2qID ∆f +
AF
KF ∗ ID
∆f
f
(8.19)
74
CHAPTER 8. DIODES
Chapter 9
BJTs
9.1
Bipolar Junction Transistors (BJTs)
General form:
QXXXXXXX n c
nb
n e mname
+ < o f f > < i c =vbe , v c e>
Examples:
Q23
10
24
Q50A 1 1
nc, nb,
13 QMOD IC = 0 . 6 ,
26
and
4
5.0
20 MOD1
ne
ns is the (optional) substrate
area, areab, areac are the area factors
are the collector, base, and emitter nodes, respectively.
node. If unspeci ed, ground is used.
mname
is the model name,
(emitter, base and collector respectively), and
off
indicates an (optional) initial condition on the device
for the dc analysis. If the area factor is omitted, a value of 1.0 is assumed.
The (optional) initial condition speci cation using
on a
.tran
ic=vbe,vce is intended for use with the uic option
control line, when a transient analysis is desired starting from other than the quiescent
operating point. See the
The (optional)
temp
.ic
control line description for a better way to set transient initial conditions.
value is the temperature at which this device is to operate, and overrides the
temperature speci cation on the
.option
control line.
Using
dtemp
option you can specify instance's
temperature relative to the circuit temperature.
9.2
BJT Models (NPN/PNP)
Ngspice provides three BJT device models. The
keyword speci es the model to be used:
level=1 : This is the original spice BJT model, and it is the default model if the
not speci ed on the
level
.model
level
keyword is
line.
level=2 : This is a modi ed version of the original spice BJT that models both vertical and lateral
devices and includes temperature corrections of collector, emitter and base resistors.
level=4: Advanced VBIC model (see http://www.designers-guide.org/VBIC/ for details)
The bipolar junction transistor model in ngspice is an adaptation of the integral charge control model
of Gummel and Poon. This modi ed Gummel-Poon model extends the original model to include several
eects at high bias levels.
The model automatically simpli es to the simpler Ebers-Moll model when
certain parameters are not speci ed. The parameter names used in the modi ed Gummel-Poon model
have been chosen to be more easily understood by the program user, and to re ect better both physical
and circuit design thinking.
is, bf, nf, ise, ikf, amd ne which determine the forward
is, br, nr, isc, ikr, and nc which determine the reverse current gain
characteristics, and vaf and var which determine the output conductance for forward and reverse regions.
Level 2 model includes substrate saturation current iss. Three ohmic resistances rb, rc, and re
are included, where rb can be high current dependent. Base charge storage is modelled by forward
The dc model is de ned by the parameters
current gain characteristics,
75
CHAPTER 9. BJTS
76
and reverse transit times,
tf
and
tr,
the forward transit time
nonlinear depletion layer capacitances which are determined by
tf being bias dependent if desired, and
cje, vje, and nje for the B-E junction,
cjc, vjc, and njc for the B-C junction and cjs, vjs, and mjs for the C-S (Collector-Substrate) junction.
Level 2 model de nes a substrate capacitance that will be connected to device's base or collector, to
model lateral or vertical devices. The temperature dependence of the saturation currents,
level 2 model), is determined by the energy-gap,
xti.
eg,
is and iss (for
and the saturation current temperature exponent,
xtb
tnom,
.model line.
Additionally base current temperature dependence is modelled by the beta temperature exponent
in the new model. The values speci ed are assumed to have been measured at the temperature
which can be speci ed on the
.options
control line or overridden by a speci cation on the
Level 4 model (VBIC) has the following improvements beyond the GP models: Improved Early eect
modeling, Quasi-saturation modeling, Parasitic substrate transistor modeling, Parasitic xed (oxide)
capacitance modeling, Includes an avalanche multiplication model, Improved temperature modeling, Base
current is decoupled from collector current, Electrothermal modeling, Smooth, continuous mode.
The BJT parameters used in the modi ed Gummel-Poon model are listed below.
The parameter
names used in earlier versions of spice2 are still accepted.
Modi ed Gummel-Poon BJT Parameters
Name
Parameters
SUBS
Substrate connection: for vertical
Units
Default
Example
Scale factor
1
geometry, -1 for lateral geometry (level
2 only).
IS
ISS
Transport saturation current.
Reverse saturation current,
A
A
1.0e-16
1.0e-15
area
1.0e-16
1.0e-15
area
100
substrate-to-collector for vertical
device or substrate-to-base for lateral
(level 2 only).
BF
Ideal maximum forward beta.
-
100
NF
Forward current emission coe cient.
-
1.0
1
V
A
∞
∞
200
0.01
area
A
0.0
1e-13
area
VAF
Forward Early voltage.
IKF
Corner for forward beta current
roll-o.
ISE
B-E leakage saturation current.
NE
B-E leakage emission coe cient.
-
1.5
2
BR
Ideal maximum reverse beta.
-
1
0.1
NR
Reverse current emission coe cient.
VAR
Reverse Early voltage.
IKR
Corner for reverse beta high current
-
1
1
V
A
∞
∞
200
0.01
area
A
0.0
1e-13
area
roll-o.
ISC
B-C leakage saturation current (area is
"areab" for vertical devices and
"areac" for lateral).
NC
B-C leakage emission coe cient.
RB
Zero bias base resistance.
IRB
Current where base resistance falls
-
2
1.5
Ω
A
0
100
area
∞
0.1
area
Ω
RB
10
area
Ω
Ω
F
V
0
1
area
0
10
area
0
2pF
area
0.75
0.6
halfway to its min value.
RBM
Minimum base resistance at high
currents.
RE
Emitter resistance.
RC
Collector resistance.
CJE
B-E zero-bias depletion capacitance.
VJE
B-E built-in potential.
MJE
B-E junction exponential factor.
TF
XTF
Ideal forward transit time.
Coe cient for bias dependence of TF.
-
0.33
0.33
sec
0
0.1ns
-
0
9.2. BJT MODELS (NPN/PNP)
VTF
Voltage describing VBC dependence of
77
V
∞
A
0
deg
0
F
TF.
ITF
High-current parameter for eect on
-
area
0
2pF
area
TF.
PTF
Excess phase at freq=1.0/(TF*2PI)
Hz.
CJC
B-C zero-bias depletion capacitance
(area is "areab" for verticaldevices and
"areac" for lateral).
VJC
B-C built-in potential.
V
0.75
0.5
MJC
B-C junction exponential factor.
-
0.33
0.5
Fraction of B-C depletion capacitance
-
1
sec
0
10ns
F
0
2pF
XCJC
connected to internal base node.
TR
Ideal reverse transit time.
CJS
Zero-bias collector-substrate
capacitance (area is "areac" for
vertical devices and"areab" for
lateral).
VJS
Substrate junction built-in potential.
V
0.75
MJS
Substrate junction exponential factor.
-
0
XTB
Forward and reverse beta temperature
-
0
eV
1.11
0.5
exponent.
EG
Energy gap for temperature eect on
IS.
XTI
Temperature exponent for eect on IS.
-
3
KF
Flicker-noise coe cient.
-
0
AF
Flicker-noise exponent.
-
1
FC
Coe cient for forward-bias depletion
-
0.5
0
capacitance formula.
TNOM
TRE1
Parameter measurement temperature.
1st order temperature coe cient for
°C
27
50
1/°C
0.0
1e-3
1/°C 2
0.0
1e-5
1/°C
0.0
1e-3
1/°C 2
0.0
1e-5
1/°C
0.0
1e-3
1/°C 2
0.0
1e-5
1/°C
0.0
1e-3
1/°C 2
0.0
1e-5
RE (level 2 only).
TRE2
2nd order temperature coe cient for
RE (level 2 only).
TRC1
1st order temperature coe cient for
RC (level 2 only).
TRC2
2nd order temperature coe cient for
RC (level 2 only).
TRB1
1st order temperature coe cient for
RB (level 2 only).
TRB2
2nd order temperature coe cient for
RB (level 2 only).
TRBM1
1st order temperature coe cient for
RBM
TRBM2
2nd order temperature coe cient for
RBM
area
78
CHAPTER 9. BJTS
Chapter 10
JFETs
10.1
Junction Field-Eect Transistors (JFETs)
General form:
JXXXXXXX nd
ng
n s mname < o f f > < i c =vds , v g s>
Examples:
J1
7
2
3 JM1 OFF
nd, ng,
and
ns
are the drain, gate, and source nodes, respectively.
is the area factor, and
off
area factor is omitted, a value of 1.0 is assumed.
ic=VDS,VGS
mname
is intended for use with the
uic
area
The (optional) initial condition speci cation, using
option on the
.TRAN
control line, when a transient analysis
is desired starting from other than the quiescent operating point. See the
way to set initial conditions.
The (optional)
temp
.ic
control line for a better
value is the temperature at which this device is to
operate, and overrides the temperature speci cation on the
10.2
is the model name,
indicates an (optional) initial condition on the device for dc analysis. If the
.option
control line.
JFET Models (NJF/PJF)
10.2.1 Model by Parker and Skellern
The
level 1 JFET model is derived from the FET model of Shichman and Hodges.
are de ned by the parameters
voltage,
lambda,
vto
and
beta,
which determines the output conductance, and
gate junctions. Two ohmic resistances,
rd and rs, are included.
is,
cgs, cgd,
and
pb.
the saturation current of the two
Charge storage is modelled by nonlinear
depletion layer capacitances for both gate junctions which vary as the
are de ned by the parameters
The dc characteristics
which determine the variation of drain current with gate
−1/2 power of junction voltage and
Note that in Spice3f and later, a tting parameter b has been added. For details, see [9].
79
CHAPTER 10. JFETS
80
Name
Parameter
Units
Example
Scaling factor
V
-2.0
-2.0
BETA
Transconductance parameter (β )
A/V ”
1.0e-4
1.0e-3
LAMBDA
Channel-length modulation parameter
1/V
0
1.0e-4
RD
Drain ohmic resistance
100
area
Source ohmic resistance
Ω
Ω
F
F
0
RS
0
100
area
0
5pF
area
0
1pF
area
VTO
Threshold voltage
VT 0
Default
area
(λ)
CGS
CGD
Zero-bias G-S junction capacitance
Cgs
Zero-bias G-D junction capacitance
Cgd
PB
IS
Gate junction potential
Gate saturation current
IS
V
A
1
0.6
1.0e-14
1.0e-14
1.1
B
Doping tail parameter
-
1
KF
Flicker noise coe cient
-
0
AF
Flicker noise exponent
-
FC
Coe cient for forward-bias depletion
TNOM
Parameter measurement temperature
1
0.5
capacitance formula
10.2.2 Modi ed Parker Skellern model
level 2
to be written
°C
27
50
area
Chapter 11
MESFETs
11.1
MESFETs
General form:
ZXXXXXXX ND NG NS MNAME
Examples:
Z1
7
2
11.2
3 ZM1 OFF
MESFET Models (NMF/PMF)
11.2.1 Model by Statz e.a.
The MESFET model
level 1
is derived from the GaAs FET model of Statz et al. as described in [11].
The dc characteristics are de ned by the parameters VTO, B, and BETA, which determine the variation
of drain current with gate voltage, ALPHA, which determines saturation voltage, and LAMBDA, which
determines the output conductance. The formula are given by:
B(Vgs −VT )2 1 − 1 − A Vds
3
gs −VT )
Id = 1+b(V
2
B(Vgs −VT ) (1 + LVds )
3
(1 + LVds )
1+b(Vgs −VT )
Two ohmic resistances,
rd
and
rs,
for 0 < Vds <
for V >
(11.1)
3
A
are included. Charge storage is modeled by total gate charge as a
function of gate-drain and gate-source voltages and is de ned by the parameters
Name
3
A
Parameter
cgs, cgd,
Units
and
Default
pb.
Example
Area
VTO
Pinch-o voltage
V
-2.0
-2.0
BETA
Transconductance parameter
A/V 2
1.0e-4
1.0e-3
*
B
Doping tail extending parameter
1/V
0.3
0.3
*
ALPHA
Saturation voltage parameter
1/V
2
2
*
LAMBDA
Channel-length modulation parameter
1/V
0
1.0e-4
RD
Drain ohmic resistance
0
100
*
RS
Source ohmic resistance
0
100
*
0
5pF
*
0
1pF
*
1
0.6
0
CGS
Zero-bias G-S junction capacitance
CGD
Zero-bias G-D junction capacitance
PB
Gate junction potential
Ω
Ω
F
F
V
KF
Flicker noise coe cient
-
AF
Flicker noise exponent
-
1
FC
Coe cient for forward-bias depletion capacitance formula
-
0.5
81
CHAPTER 11. MESFETS
82
Device instance:
z1
2
3
0 mesmod
a r e a =1.4
Model:
. model
mesmod nmf
+ lambda = 0 . 0 3
l e v e l =1 r d =46
a l p h a =3
r s =46
v t 0 = − 1.3
b e t a = 1 . 4 e −3
11.2.2 Model by Ytterdal e.a.
level 2 (and levels 3,4) Copyright 1993:
T. Ytterdal, K. Lee, M. Shur and T. A. Fjeldly
to be written
M. Shur, T.A. Fjeldly, T. Ytterdal, K. Lee, "Uni ed GaAs MESFET Model for Circuit Simulation",
Int. Journal of High Speed Electronics, vol. 3, no. 2, pp. 201-233, 1992
11.2.3 hfet1
level 5
to be written
no documentation available
11.2.4 hfet2
level6
to be written
no documentation available
Chapter 12
MOSFETs
Ngspice supports all the original mosfet models present in spice3f5 and almost all the newer ones that have
been published and made open-source. Both bulk and SOI (Silicon on Insulator) models are available.
When compiled with the cider option, ngspice implements the four terminals numerical model that can be
used to simulate a MOSFET (please refer to numerical modeling documentation for additional information
and examples).
12.1
MOSFET devices
General form:
MXXXXXXX nd ng ns nb mname < l=v a l >
+
+
Examples:
M1 2 4
2
M31 2
17
M1 2
9
0
3
2 0 TYPE1
6
1 0 MODM L=5U W=2U
0 MOD1 L=10U W=5U AD=100P AS=100P PD=40U PS=40U
Note the su xes in the example: the su x u speci es microns (1e-6
m)
and p sq-microns (1e-12
m2 ).
nd, ng, ns, and nb are the drain, gate, source, and bulk (substrate) nodes,
mname is the model name and m is the multiplicity parameter, which simulates m paralleled
devices. All MOS models support the m parameter. Instance parameters l and w, channel length and
width respectively, are expressed in meters. The areas of drain and source diusions: ad and as, in
2
squared mters (m ).
In the instance card,
respectively.
If any of
l, w, ad,
or
as
are not speci ed, default values are used.
The use of defaults simpli es
input le preparation, as well as the editing required if device geometries are to be changed.
are the perimeters of the drain and source junctions, in meters.
nrd
and
nrs
pd
and
ps
designate the equivalent
rsh
.model control line for an accurate representation of the parasitic series drain and source
each transistor. pd and ps default to 0.0 while nrd and nrs to 1.0. off indicates an
number of squares of the drain and source diusions; these values multiply the sheet resistance
speci ed on the
resistance of
(optional) initial condition on the device for dc analysis. The (optional) initial condition speci cation
ic=vds,vgs,vbs is intended for use with the uic option on the .tran control line, when a transient
.ic control line for
better and more convenient way to specify transient initial conditions. The (optional) temp value is
using
analysis is desired starting from other than the quiescent operating point. See the
a
the temperature at which this device is to operate, and overrides the temperature speci cation on the
.option
control line.
The temperature speci cation is ONLY valid for level 1, 2, 3, and 6 MOSFETs, not for level 4 or 5
(BSIM) devices.
83
CHAPTER 12. MOSFETS
84
12.2
MOSFET models (NMOS/PMOS)
MOSFET models are the central part of ngspice, probably because they are the most widely used devices
in the electronics world.
Ngspice provides all the MOSFETs implemented in the original Spice3f and
adds several models developed by Berkeley's Device Group and other independent groups. The variable
level
speci es the model to be used and a short summary of available device is show in 12.1.
Note: not all models below are included in the standard ngspice distribution because of copyright
restrictions.
Ngspice provides four MOSFET device models, which dier in the formulation of the I-V characteristic.
12.2.1 MOS Level 1
This model is also known as the Schichman-Hodges model. This is the rst model written and the one
often described in the introductory textbooks of electronics. This model i applicable only to long channel
devices and, the use of Meyer's model for the C-V part makes it non charge conserving.
12.2.2 MOS Level 2
This model tries to overcome the limitations of the Level 1 model addressing several short-channel effect, like velocity saturation. The implementation of this model is complicated and this leads to many
convergence problems. C-V calculations can be done with the original Meyer model (non conserving).
12.2.3 MOS Level 3
This is a semiempirical model derived from the Level 2 one. This model is often used for digital design
and, in the years, has proven to be robust. A discontinuity in the model with respect to the KAPPA
parameter has been detected (see [10]). The supplied x has been implemented in Spice3f2 and later.
Since this x may aect parameter tting, the option badmos3 may be set to use the old implementation
(see the section on simulation variables and the .options line). Ngspice level 3 implementation takes
into account length and width mask adjustments (xl and
(wd).
xw) and device width narrowing due to diusion
12.2.4 MOS Level 6
This model is described in [2]. The model can express the current characteristics of short-channel MOSFETs at least down to 0. 25
µm
channel-length, GaAs FET, and resistance inserted MOSFETs. The
model evaluation time is about 1/3 of the evaluation time of the spice3 mos level 3 model. The model also
enables analytical treatments of circuits in short-channel region and makes up for a missing link between
a complicated MOSFET current characteristics and circuit behaviors in the deep submicron region.
12.2.5 Notes on Level 1-6 models
vto,
kp, lambda, phi and gamma. These parameters are computed by ngspice if process parameters (nsub,
tox, ...) are given, but users speci ed values always override. vto is positive (negative) for enhancement
The dc characteristics of the level 1 through level 3 MOSFETs are de ned by the device parameters
mode and negative (positive) for depletion mode N-channel (P-channel) devices.
Charge storage is modeled by three constant capacitors,
cgso, cgdo, and cgbo which represent overlap
capacitances, by the nonlinear thin-oxide capacitance which is distributed among the gate, source, drain,
and bulk regions, and by the nonlinear depletion-layer capacitances for both substrate junctions divided
mj and mjsw power of junction
cbd, cbs, cj, cjsw, mj, mjsw and pb.
into bottom and periphery, which vary as the
are determined by the parameters
voltage respectively, and
Charge storage eects are modelled by the piecewise linear voltages-dependent capacitance model
proposed by Meyer.
The thin-oxide charge-storage eects are treated slightly dierent for the level 1
model. These voltage-dependent capacitances are included only if
tox is speci ed in the input description
and they are represented using Meyer's formulation.
There is some overlap among the parameters describing the junctions, e.g. the reverse current can
is (in A) or as js (in A/m2 ). Whereas the rst is an absolute value the second
ad and as to give the reverse current of the drain and source junctions respectively.
be input either as
multiplied by
is
Name
MOS1
MOS2
MOS3
BSIM1
BSIM2
MOS6
BSIM3
MOS9
B4SOI
BSIM4
HISIM1
B3SOIPD
B3SOIFD
B3SOIDD
EKV
BSIM3V1S
BSIM3V1
BSIM3V1A
BSIM3V0
STAG
Level
1
2
3
4
5
6
8
9
10
14
17
29
30
31
44
49
50
51
52
62
Grove-Frhoman
Shichman-Hodges
Model
4.6.5
4.3.1
3.3.0
-
-
Version
Southampton
Berkeley
Alan Gillespie
Berkeley
Serban Popescu
EPFL
Berkeley
Berkeley
Berkeley
Berkeley
Berkeley
Alan Gillespie
Berkeley
Berkeley
Berkeley
Berkeley
Berkeley
Berkeley
Berkeley
Developer
References
not in the standard distribution
Described in [13]
Described in [2]
Described in [5]
Described in [3]
A semi-empirical model (see [1])
Described in [2]
This is the classical quadratic model.
Notes
12.2. MOSFET MODELS (NMOS/PMOS)
85
Table 12.1: MOSFET model summary
CHAPTER 12. MOSFETS
86
This methodology has been chosen since there is no sense in relating always junction characteristics
with
ad
and
as
entered on the device line; the areas can be defaulted. The same idea applies also to the
zero-bias junction capacitances
cbd
and
cbs
(in F) on one hand, and
cj
(in F/m2 ) on the other.
The parasitic drain and source series resistance can be expressed as either rd and rs (in ohms) or
rsh (in ohms/sq.), the latter being multiplied by the number of squares nrd and nrs input on the device
line.
NGSPICE level 1, 2, 3 and 6 parameters
Name
Parameter
Units
Default
LEVEL
Model index
-
1
Example
VTO
Zero-bias threshold voltage
V
0.0
1.0
(VT 0 )
KP
Transconductance parameter
A/V 2
2.0e-5
3.1e-5
GAMMA
Bulk treshold parameter
0.37
Sufrace potential (U)
0.6
0.65
LAMBDA
Channel length modulation
V
V
1/V
0.0
PHI
0.0
0.02
Ω
Ω
F
0.0
1.0
√
(MOS1 and MOS2 only) (λ)
RD
Drain ohmic resistance
RS
Source ohmic resistance
CBD
Zero-bias B-D junction
CBS
Zero-bias B-S junction
0.0
1.0
0.0
20fF
F
0.0
20fF
A
1.0e-14
1.0e-15
capacitance
capacitance
IS
Bulk junction saturation
current (IS )
PB
Bulk junction potential
V
0.8
0.87
CGSO
Gate-source overlap
F/m
0.0
4.0e-11
F/m
0.0
4.0e-11
F/m
0.0
2.0e-11
Ω/
0.0
10
F/m2
0.0
2.0e-4
-
0.5
0.5
F/m
0.0
1.0e-9
-
0.50 (level1)
0.33 (level2, 3)
capacitance per meter channel
width
CGDO
Gate-drain overlap capacitance
per meter channel width
CGBO
Gate-bulk overlap capacitance
per meter channel width
RSH
Drain and source diusion
sheet resistance
CJ
Zero-bias bulk junction bottom
cap. per sq-meter of junction
area
MJ
Bulk junction bottom grading
coe.
CJSW
Zero-bias bulk junction
sidewall cap. per meter of
junction perimeter
MJSW
Bulk junction sidewall grading
JS
Bulk junction saturation
TOX
Oxide thickness
coe.
current
NSUB
Substrate doping
NSS
Surface state density
NFS
Fast surface state density
m
cm−3
cm−2
cm−2
TPG
Type of gate material: +1 opp.
-
1.0
m
0.0
1.0e-7
1.0e-7
0.0
4.0e15
0.0
1.0e10
0.0
1.0e10
to substrate, -1 same as
substrate, 0 Al gate
XJ
Metallurgical junction depth
1M
12.2. MOSFET MODELS (NMOS/PMOS)
87
Name
Parameter
Units
Default
Example
LD
Lateral diusion
0.0
0.8M
UO
Surface mobility
600
700
UCRIT
Critical eld for mobility
m
cm2/V ·sec
V /cm
1.0e4
1.0e4
-
0.0
0.1
-
0.0
0.3
m/s
0.0
5.0e4
-
1.0
5.0
Flicker noise coe cient
-
0.0
1.0e-26
AF
Flicker noise exponent
-
1.0
1.2
FC
Coe cient for forward-bias
-
0.5
-
0.0
1.0
1/V
0.0
0.1
degradation (MOS2 only)
UEXP
Critical eld exponent in
mobility degradation (MOS2
only)
UTRA
Transverse eld coe.
(mobility) (deleted for MOS2)
VMAX
Maximum drift velocity of
carriers
NEFF
Total channel-charge ( xed
and mobile) coe cient (MOS2
only)
KF
depletion capacitance formula
DELTA
Width eect on threshold
voltage (MOS2 and MOS3)
THETA
Mobility modulation (MOS3
only)
ETA
Static feedback (MOS3 only)
-
0.0
1.0
KAPPA
Saturation eld factor (MOS3
-
0.2
0.5
°C
27
50
only)
TNOM
Parameter measurement
temperature
12.2.6 BSIM Models
Ngspice implments many of the BSIM models developer by Berkeley's device group. BSIM stands for
Berkeley Short-Channel IGFET Model and groups a class of models that are continuosly updated. In
general, all parameters of BSIM model are obtained from process characterization, in particulat level 4
and level 5 (BSIM1 and BSIM2) parameters are can be generated automatically. J. Pierret [4] describes
a means of generating a process le, and the program
ngproc2mod
provided with ngspice converts this
le into a sequence of BSIM1 .model lines suitable for inclusion in an ngspice input le.
Parameters marked below with an
*
wvfb
l/w column also have corresponding parameters with a
vfb is the basic parameter with units of Volts, and lvfb and
in the
length and width dependency. For example,
also exist and have units of Volt-meter.
The formula
P = P0 +
PL
Leffective
+
PW
Weffective
(12.1)
is used to evaluate the parameter for the actual device speci ed with
Leffective = Linput − DL
(12.2)
Weffective = Winput − DW
(12.3)
Note that unlike the other models in ngspice, the BSIM models are designed for use with a process
characterization system that provides all the parameters, thus there are no defaults for the parameters,
and leaving one out is considered an error. For an example set of parameters and the format of a process
le, see the SPICE2 implementation notes[3]. For more information on BSIM2, see reference [5].
12.2.7 BSIM1 model (level 4)
BSIM1 model (the rst is a long series) is an empirical model. Developers placed less emphasis on device
physics and based the model on parametrical polynomial equations to model the various physical eects.
CHAPTER 12. MOSFETS
88
This approach pays in terms of circuit simulation behaviour but the accuracy degrades in tghe submicron
region. A k nown problem of this model is the negative output conductance and the convergence problems,
both related to poor behavior of the polynomial equations.
Ngspice BSIM (level 4) parameters
Name
Parameter
Units
l/w
VFB
Flat-band voltage
*
PHI
Surface inversion potential
K1
Body eect coe cient
V
√V
V
K2
Drain/source depletion charge-sharing coe cient
-
*
ETA
Zero-bias drain-induced barrier-lowering coe cient
-
*
MUZ
Zero-bias mobility
cm2/V ·sec
µm
µm
1/V
DL
Shortening of channel
DW
Narrowing of channel
U0
Zero-bias transverse- eld mobility degradation
*
*
*
coe cient
U1
Zero-bias velocity saturation coe cient
Sens. of mobility to substrate bias at v=0
µ/V
cm2/V 2 ·sec
*
X2MZ
X2E
Sens. of drain-induced barrier lowering eect to
1/V
*
1/V
*
1/V 2
*
µm/V 2
cm2/V 2 sec
*
cm2/V 2 sec
*
cm2/V 2 sec
*
µm/V 2
*
*
substrate bias
X3E
Sens. of drain-induced barrier lowering eect to
drain bias at
X2U0
Vds = Vdd
Sens. of transverse eld mobility degradation eect
to substrate bias
X2U1
Sens. of velocity saturation eect to substrate bias
X3MS
Vds = Vdd
Sens. of mobility to substrate bias at Vds = Vdd
Sens. of mobility to drain bias at Vds = Vdd
X3U1
Sens. of velocity saturation eect on drain bias at
MUS
X2MS
Mobility at zero substrate bias and at
Vds=Vdd
TOX
Gate oxide thickness
TEMP
Temperature at which parameters were measured
VDD
Measurement bias range
CGDO
Gate-drain overlap capacitance per meter channel
CGSO
Gate-source overlap capacitance per meter channel
µm
°C
V
F/m
width
F/m
width
CGBO
Gate-bulk overlap capacitance per meter channel
F/m
length
XPART
Gate-oxide capacitance-charge model ag
-
N0
Zero-bias subthreshold slope coe cient
-
*
NB
Sens. of subthreshold slope to substrate bias
-
*
ND
Sens. of subthreshold slope to drain bias
-
*
RSH
Drain and source diusion sheet resistance
Ω/
JS
Source drain junction current density
A/m2
V
PB
Built in potential of source drain junction
MJ
Grading coe cient of source drain junction
-
PBSW
Built in potential of source, drain junction sidewall
V
MJSW
Grading coe cient of source drain junction sidewall
CJ
Source drain junction capacitance per unit area
F/m2
CJSW
source drain junction sidewall capacitance per unit
F/m
WDF
Source drain junction default width
DELL
Source drain junction length reduction
length
m
m
12.2. MOSFET MODELS (NMOS/PMOS)
xpart
89
= 0 selects a 40/60 drain/source charge partition in saturation, while
is the model name,
nd, ng,
and
ns
xpart=1
selects a 0/100
mname
area is the area factor, and off indicates an (optional) initial condition on the device
drain/source charge partition.
are the drain, gate, and source nodes, respectively.
for dc analysis. If the area factor is omitted, a value of 1.0 is assumed. The (optional) initial condition
speci cation, using
ic=vds,vgs is intended for use with the uic option on the .tran control line, when a
.ic control
transient analysis is desired starting from other than the quiescent operating point. See the
line for a better way to set initial conditions.
12.2.8 BSIM2 model (level 5)
This model contains many improvements over BSIM1 and is suitable for analog simulation. Nevertheless,
even BSIM2 breaks transistor operation into several distinct regions and this leads to discontinuties in
the rst derivative in C-V and I-V chracteristics that can cause numerical problems during simulation.
12.2.9 BSIM3 model (levels 8, 49)
BSIM3 solves the numerical problems of previous models with the introduction of smoothing functions.
It adopts a single equation to describe device characteristics in the operating regions.
eliminates the discontinuities in the I-V and C-V characteristics.
This approach
The original model, BSIM3 evolved
through three versions: BSIM3v1, BSIM3v2 and BSIM3v3. Both BSIM3v1 and BSIM3v2 had suered
from many mathematical problems and were replaced by BSIM3v3.
The latter is the only surviving
release and has itself a long revision history
The following table summarizes the story of this model:
Release
Date
Notes
BSIM3v3.0
10/30/1995
BSIM3v3.1
12/09/1996
BSIM3v3.2
06/16/1998
Two minor revisions available: BSIM3v3.2.1 and
BSIM3v3.3
07/29/2005
Parallel processing with OpenMP is available for
BSIM3v3.2.2
this model.
BSIM3v2 and 3v3 models has proven for accurate use in 0.18
µm
technologies. The model is publicy
available in source code form from University of California, Berkeley at
http://www-device.eecs.berkeley.edu/∼bsim3/get.html.
A detailed description is given in the user's manual available at
http://www-device.eecs.berkeley.edu/∼bsim3/ftpv330/Mod_doc/b3v33manu.tar.
12.2.10 BSIM4 model (levels 14, 54)
This is the newest class of the BSIM family and introduces noise modeling and extrinsic parasitics..
BSIM4, as the extension of BSIM3 model, addresses the MOSFET physical eects into sub-100nm regime.
It is a physics-based, accurate, scalable, robustic and predictive MOSFET SPICE model for circuit
simulation and CMOS technology development.
It is developed by the BSIM Research Group in the
Department of Electrical Engineering and Computer Sciences (EECS) at the University of California,
Berkeley (see http://www-device.eecs.berkeley.edu/∼bsim3/bsim4_get.html). BSIM4 has a long revision
history, which is summarized below.
Release
Date
Notes
BSIM4.0.0
03/24/2000
BSIM4.1.0
10/11/2000
BSIM4.2.0
04/06/2001
BSIM4.2.1
10/05/2001
*
BSIM4.3.0
05/09/2003
*
BSIM4.4.0
03/04/2004
*
BSIM4.5.0
07/29/2005
*
BSIM4.6.0
12/13/2006
...
BSIM4.6.5
09/09/2009
* **
*) supported in ngspice, using e.g. the
version=4.6
ag in the parameter le.
**) Parallel processing using OpenMP support is available for this model.
CHAPTER 12. MOSFETS
90
Details of any revision are to be found in the user's manual, a pdf download from
http://www-device.eecs.berkeley.edu/∼bsim3/BSIM4/BSIM464/BSIM464_Manual.pdf.
12.2.11 EKV model
Level 44 model (EKV) is not available in the standard distribution since it is not released in source form
by the EKV group. To obtain the code please refer to the (http://legwww.ep .ch/ekv/, EKV group home
page).
12.2.12 BSIMSOI models (levels 10, 58, 55, 56, 57)
BSIMSOI is a SPICE compact model for SOI (Silicon-On-Insulator) circuit design. This model is formulated on top of the BSIM3 framework. It shares the same basic equations with the bulk model so that the
physical nature and smoothness of BSIM3v3 are retained. Four models are supported in ngspice, those
based on BSIM3 and modelling fully depleted (FD, level 55), partially depleted (PD, level 57) and both
(DD, level 56), as well as the modern BSIMSOI version 4 model (levels 10, 58). Detailed descriptions
are beyond the scope of this manual, but see e.g. BSIMSOI_4.3.1_Users_manual for a very extensive
description of the recent model version. OpenMP support is available for levels 10, 58, version 4.3.1.
12.2.13 SOI3 model (level 62)
see literature citation [18] for a decription.
Chapter 13
Behavioral Modeling
Ngspice implements XSPICE extensions for behavioral modeling.
referred to as code level modeling.
In the XSPICE framework this is
This chapter describes the prede ned models available in ngspice,
stemming from the original XSPICE simulator. The instructions for writing new code models are given
in chapter 27.
To make use of the XSPICE extensions, you need to compile them in. LINX, CYGWIN, MINGW
and other users may add the ag
--enable-xspice to their ./configure command and then recompile.
The prebuild ngspice for Windows distribution has XSPICE already enabled.
For detailed compiling
instructions see chapter 31.1.
13.1
Code Model Element & .MODEL Cards
Ngspice includes a library of prede ned Code Models that can be placed within any circuit description
in a manner similar to that used to place standard device models. Code model instance cards always
begin with the letter A, and always make use of a .MODEL card to describe the code model desired.
Section of this document goes into greater detail as to how a code model similar to the prede ned models
may be developed, but once any model is created and linked into the simulator it may be placed using
one instance card and one .MODEL card (note here we conform to the SPICE custom of referring to a
single logical line of information as a card). As an example, the following uses the prede ned gain
code model which takes as an input some value on node 1, multiplies it by a gain of 5.0, and outputs the
new value to node 2. Note that, by convention, input ports are speci ed rst on code models. Output
ports follow the inputs.
Example:
a1 1 2 amp
. model amp gain ( gain =5.0)
In this example the numerical values picked up from single-ended (i.e. ground referenced) input node 1
and output to single-ended output node 2 will be voltages, since in the Interface Speci cation File for
this code model (i.e., gain), the default port type is speci ed as a voltage (more on this later). However,
if you didn't know this, the following modi cations to the instance card could be used to insure it:
Example:
a1 % v (1) % v (2) amp
. model amp gain ( gain =5.0)
The speci cation "%v" preceding the input and output node numbers of the instance card indicate to the
simulator that the inputs to the model should be single-ended voltage values. Other possibilities exist,
as described later.
91
CHAPTER 13. BEHAVIORAL MODELING
92
Some of the other features of the instance and .MODEL cards are worth noting. Of particular interest
is the portion of the .MODEL card which speci es
gain=5.0.
This portion of the card assigns a value to a
parameter of the "gain" model. There are other parameters which can be assigned values for this model,
and in general code models will have several. In addition to numeric values, code model parameters can
take non-numeric values (such as TRUE and FALSE), and even vector values. All of these topics will be
discussed at length in the following pages. In general, however, the instance and .MODEL cards which
de ne a code model will follow the abstract form described below. This form illustrates that the number
of inputs and outputs and the number of parameters which can be speci ed is relatively open-ended and
can be interpreted in a variety of ways (note that angle-brackets < and > enclose optional inputs):
Example:
AXXXXXXX <%v ,% i ,% vd ,% id ,% g ,% gd ,% h ,% hd , or %d >
+ <[ > <~ > <%v ,% i ,% vd ,% id ,% g ,% gd ,% h ,% hd , or %d >
+ < NIN1 or + NIN1 - NIN1 or " null " >
+ <~ >... < NIN2 .. <] > >
+ <%v ,% i ,% vd ,% id ,% g ,% gd ,% h ,% hd ,% d or % vname >
+ <[ > <~ > <%v ,% i ,% vd ,% id ,% g ,% gd ,% h ,% hd , or %d > < NOUT1 or + NOUT1 - NOUT1 >
+ <~ >... < NOUT2 .. <] > >
+ MODELNAME
. MODEL MODELNAME MODELTYPE
+ <( PARAMNAME1 = <[ > VAL1 < VAL2 ... <] > > PARAMNAME2 .. >) >
Square brackets ([ ]) are used to enclose vector input nodes.
In addition, these brackets are used to
delineate vectors of parameters.
The literal string null, when included in a node list, is interpreted as no connection at that input
to the model. "Null" is not allowed as the name of a model's input or output if the model only has one
input or one output. Also, null should only be used to indicate a missing connection for a code model;
use on other XSPICE component is not interpreted as a missing connection, but will be interpreted as
an actual node name.
The tilde, ~, when prepended to a digital node name, speci es that the logical value of that node be
inverted prior to being passed to the code model. This allows for simple inversion of input and output
polarities of a digital model in order to handle logically equivalent cases and others that frequently arise
in digital system design. The following example de nes a NAND gate, one input of which is inverted:
a1 [~1 2] 3 nand1
. model nand1 d_nand ( rise_delay =0.1 fall_delay =0.2)
The optional symbols %v, %i, %vd, etc.
specify the type of port the simulator is to expect for the
subsequent port or port vector. The meaning of each symbol is given in Table 13.1.
The symbols described in Table 13.1 may be omitted if the default port type for the model is desired.
Note that non-default port types for multi-input or multi-output (vector) ports must be speci ed by
placing one of the symbols in front of EACH vector port. On the other hand, if all ports of a vector port
are to be declared as having the same non-default type, then a symbol may be speci ed immediately
prior to the opening bracket of the vector. The following examples should make this clear:
Example 1: - Specifies two differential voltage connections, one
to nodes 1 & 2, and one to nodes 3 & 4.
%vd [1 2 3 4]
Example 2: - Specifies two single-ended connections to node 1 and
at node 2, and one differential connection to
nodes 3 & 4.
%v [1 2 %vd 3 4]
13.1. CODE MODEL ELEMENT & .MODEL CARDS
Port Type Modi ers
Modi er
%v
Interpretation
represents a single-ended voltage port - one node name or number
is expected for each port.
%i
represents a single-ended current port - one node name or number
is expected for each port.
%g
represents a single-ended voltage-input, current-output (VCCS)
port - one node name or number is expected for each port. This
type of port is automatically an input/output.
%h
represents a single-ended current-input, voltage-output (CCVS)
port - one node name or number is expected for each port. This
type of port is automatically an input/output.
%d
represents a digital port - one node name or number is expected
for each port.
This type of port may be either an input or an
output.
%vnam
epresents the name of a voltage source, the current through which
is taken as an input. This notation is provided primarily in order to allow models de ned using SPICE2G6 syntax to operate
properly in XSPICE.
%vd
represents a dierential voltage port - two node names or numbers
are expected for each port.
%id
represents a dierential current port - two node names or numbers
are expected for each port.
%gd
represents a dierential VCCS port - two node names or numbers
are expected for each port.
%hd
represents a dierential CCVS port - two node names or numbers
are expected for each port.
Table 13.1: Port Type Modi ers
93
CHAPTER 13. BEHAVIORAL MODELING
94
Example 3: - Identical to the previous example...parenthesis
are added for additional clarity.
%v [1 2 %vd(3 4)]
Example 4: - Specifies that the node numbers are to be treated in the
default fashion for the particular model.
If this model had %v as a default for this
port, then this notation would represent four single-ended
voltage connections.
[1 2 3 4]
The parameter names listed on the .MODEL card must be identical to those named in the code model
itself. The parameters for each prede ned code model are described in detail in Sections 13.2 (analog),
13.3 (Hybrid, A/D) and 13.4 (digital) . The steps required in order to specify parameters for user-de ned
models are described in Chapter 27.
The following is a list of instance card and associated .MODEL card examples showing use of prede ned models within an XSPICE deck:
a1 1 2 amp
.model amp gain(in_offset=0.1 gain=5.0 out_offset=-0.01)
a2 %i[1 2] 3 sum1
.model sum1 summer(in_offset=[0.1 -0.2] in_gain=[2.0 1.0]
+ out_gain=5.0 out_offset=-0.01)
a21 %i[1 %vd(2 5) 7 10] 3 sum2
.model sum2 summer(out_gain=10.0)
a5 1 2 limit5 .model limit5 limit(in_offset=0.1 gain=2.5 out_lower.limit=-5.0
+ out_upper_limit=5.0 limit_domain=0.10
+ fraction=FALSE)
a7 2 %id(4 7) xfer.cntl1
.model xfer_cntl1 pwl(x_array=[-2.0 -1.0 2.0 4.0 5.0]
+ y_array=[-0.2 -0.2 0.1 2.0 10.0]
+ input_domain=0.05 fraction=TRUE)
a8 3 %gd(6 7) switch3
.model switch3 aswitch(cntl_off=0.0 cntl_on=5.0 r_off=1e6
+ r_on=10.0 log=TRUE)
13.2
Analog Models
The following analog models are supplied with XSPICE. The descriptions included consist of the model
Interface Speci cation File and a description of the model's operation. This is followed by an example of a
simulator-deck placement of the model, including the .MODEL card and the speci cation of all available
parameters.
13.2.1 Gain
NAME_TABLE :
C_Function_Name :
Spice_Model_Name :
Description :
cm_gain
gain
" A simple gain block "
PORT_TABLE :
Port Name :
Description :
Direction :
Default_Type :
Allowed_Types :
Vector :
Vector . Bounds :
Null . Allowed :
in
" input "
in
v
[v , vd ,i , id ]
no
no
out
" output "
out
v
[v , vd ,i , id ]
no
no
13.2. ANALOG MODELS
PARAMETER_TABLE :
Parameter_Name :
Description :
Data_Type :
Default_Value :
Limits :
Vector :
Vector_Bounds :
Null_Allowed :
Description:
95
in_offset
" input offset "
real
0.0
no
yes
gain
" gain "
real
1.0
no
yes
out_offset
" output offset "
real
0.0
no
yes
This function is a simple gain block with optional osets on the input and the output.
The input oset is added to the input, the sum is then multiplied by the gain, and the result is
produced by adding the output oset. This model will operate in DC, AC, and Transient analysis
modes.
Example:
a1 1 2 amp
. model amp gain ( in_offset =0.1 gain =5.0
+ out_offset = -0.01)
13.2.2 Summer
NAME_TABLE :
C_Function_Name :
Spice_Model_Name :
Description :
cm_summer
summer
" A summer block "
PORT_TABLE :
Port Name :
Description :
Direction :
Default_Type :
Allowed_Types :
Vector :
Vector_Bounds :
Null_Allowed :
in
" input vector "
in
v
[v , vd ,i , id ]
yes
no
PARAMETER_TABLE :
Parameter_Name :
Description :
Data_Type :
Default_Value :
Limits :
Vector :
Vector_Bounds :
Null_Allowed :
in_offset
" input offset vector "
real
0.0
yes
in
yes
in_gain
" input gain vector "
real
1.0
yes
in
yes
PARAMETER_TABLE :
Parameter_Name :
Description :
Data_Type :
Default_Value :
Limits :
Vector :
out_gain
" output gain "
real
1.0
no
out_offset
" output offset "
real
0.0
no
out
" output "
out
v
[v , vd ,i , id ]
no
no
CHAPTER 13. BEHAVIORAL MODELING
96
Vector_Bounds :
Null_Allowed :
Description:
yes
yes
This function is a summer block with 2-to-N input ports. Individual gains and osets can
be applied to each input and to the output. Each input is added to its respective oset and then
multiplied by its gain. The results are then summed, multiplied by the output gain and added to
the output oset. This model will operate in DC, AC, and Transient analysis modes.
Example usage:
a2 [1 2] 3 sum1
. model sum1 summer ( in_offset =[0.1 -0.2] in_gain =[2.0 1.0]
+ out_gain =5.0 out_offset = -0.01)
13.2.3 Multiplier
NAME_TABLE:
C_Function_Name:
Spice_Model_Name:
Description:
PORT_TABLE:
Port_Name:
Description:
Direction:
Default_Type:
Allowed_Types:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
Description:
cm_mult
mult
"multiplier block"
in
"input vector"
in
v
[v,vd,i,id]
yes
[2 -]
no
out
"output"
out
v
[v,vd,i,id]
no
no
in_offset
"input offset vector"
real
0.0
yes
in
yes
in_gain
"input gain vector"
real
1.0
yes
in
yes
out_gain
"output gain"
real
1.0
no
yes
out_offset
"output offset"
real
0.0
no
yes
This function is a multiplier block with 2-to-N input ports. Individual gains and osets
can be applied to each input and to the output. Each input is added to its respective oset and
then multiplied by its gain. The results are multiplied along with the output gain and are added
to the output oset. This model will operate in DC, AC, and Transient analysis modes. However,
in ac analysis it is important to remember that results are invalid unless only ONE INPUT of the
multiplier is connected to a node which bears an AC signal (this is exempli ed by the use of a
multiplier to perform a potentiometer function: one input is DC, the other carries the AC signal).
13.2. ANALOG MODELS
97
Example SPICE Usage:
a3 [1 2 3] 4 sigmult
. model sigmult mult ( in_offset =[0.1 0.1 -0.1] in_gain =[10.0 10.0
+ 10.0] out_gain =5.0 out_offset =0.05)
13.2.4 Divider
NAME_TABLE:
C_Function_Name:
Spice_Model_Name:
Description:
PORT_TABLE:
Port_Name:
Description:
Direction:
Default_Type:
Allowed_Types:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
cm_divide
divide
"divider block"
num
"numerator"
in
v
[v,vd,i,id,vnam]
no
no
den
"denominator"
in
v
[v,vd,i,id,vnam]
no
no
num_offset
"numerator offset"
real
0.0
no
yes
num_gain
"numerator gain"
real
1.0
no
yes
den_offset
den_gain
"denominator offset" "denominator gain"
real
real
0.0
1.0
no
no
yes
yes
den_lower_limit
"denominator lower limit"
real
1.0e-10
no
yes
den_domain
"denominator smoothing domain"
real
1.0e-10
no
yes
out
"output"
out
v
[v,vd,i,id]
no
no
CHAPTER 13. BEHAVIORAL MODELING
98
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
Description:
fraction
"smoothing fraction/absolute value switch"
boolean
false
no
yes
out_gain
"output gain"
real
1.0
no
yes
out_offset
"output offset"
real
0.0
no
yes
This function is a two-quadrant divider. It takes two inputs; num (numerator) and den
(denominator).
Divide osets its inputs, multiplies them by their respective gains, divides the
results, multiplies the quotient by the output gain, and osets the result.
The denominator is
limited to a value above zero via a user speci ed lower limit. This limit is approached through a
quadratic smoothing function, the domain of which may be speci ed as a fraction of the lower limit
value (default), or as an absolute value. This model will operate in DC, AC and Transient analysis
modes.
However, in ac analysis it is important to remember that results are invalid unless only
ONE INPUT of the divider is connected to a node which bears an AC signal (this is exempli ed
by the use of the divider to perform a potentiometer function: one input is DC, the other carries
the AC signal).
Example SPICE Usage:
a4 1 2 4 divider
.model divider divide(num_offset=0.1 num_gain=2.5 den_offset=-0.1
+ den_gain=5.0 den_lower.limit=1e-5 den_domain=1e-6
+ fraction=FALSE out_gain=1.0 out_offset=0.0)
13.2.5 Limiter
NAME_TABLE:
C_Function_Name:
Spice_Model_Name:
Description:
PORT_TABLE:
Port Name:
Description:
Direction:
Default_Type:
Allowed_Types:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
cm_limit
limit
"limit block"
in
"input"
in
v
[v,vd,i,id]
no
no
out
"output"
out
v
[v,vd,i,id]
no
no
in_offset
"input offset"
real
0.0
no
-
gain
"gain"
real
1.0
no
-
13.2. ANALOG MODELS
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
Description:
99
yes
yes
out_lower_limit
out_upper_limit
"output lower limit" "output upper limit"
real
real
0.0
1.0
no
no
yes
yes
limit_range
"upper & lower smoothing range"
real
1.0e-6
no
yes
fraction
"smoothing fraction/absolute value switch"
boolean
FALSE
no
yes
The Limiter is a single input, single output function similar to the Gain Block. However,
the output of the Limiter function is restricted to the range speci ed by the output lower and
upper limits. This model will operate in DC, AC and Transient analysis modes. Note that the limit
range is the value BELOW THE UPPER LIMIT AND ABOVE THE LOWER LIMIT at which
smoothing of the output begins. For this model, then, the limit range represents the delta WITH
RESPECT TO THE OUTPUT LEVEL at which smoothing occurs. Thus, for an input gain of 2.0
and output limits of 1.0 and -1.0 volts, the output will begin to smooth out at
occurs when the input value is at
±0.9
±0.4.
Example SPICE Usage:
a5 1 2 limit5
.model limit5 limit(in_offset=0.1 gain=2.5 out_lower_limit=-5.0
+ out_upper_limit=5.0 limit_range=0.10 fraction=FALSE)
13.2.6 Controlled Limiter
NAME_TABLE:
C_Function_Name:
Spice_Model_Name:
Description:
PORT_TABLE:
Port_Name:
Description:
Direction:
Default_Type:
Allowed_Types:
Vector:
Vector_Bounds:
Null_Allowed:
PORT_TABLE:
cm_climit
climit
"controlled limiter block"
in
"input"
in
v
[v,vd,i,id,vnam]
no
no
cntl_upper
"upper lim. control input"
in
v
[v,vd,i,id,vnam]
no
no
volts, which
CHAPTER 13. BEHAVIORAL MODELING
100
Port_Name:
Description:
Direction:
Default_Type:
Allowed_Types:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
Description:
cntl_lower
"lower limit control input"
in
v
[v,vd,i,id,vnam]
no
no
in_offset
"input offset"
real
0.0
no
yes
out
"output"
out
v
[v,vd,i,id]
no
no
gain
"gain"
real
1.0
no
yes
upper_delta
lower_delta
"output upper delta" "output lower delta"
real
real
0.0
0.0
no
no
yes
yes
limit_range
"upper & lower sm. range"
real
1.0e-6
no
yes
fraction
"smoothing %/abs switch"
boolean
FALSE
no
yes
The Controlled Limiter is a single input, single output function similar to the Gain Block.
However, the output of the Limiter function is restricted to the range speci ed by the output lower
and upper limits. This model will operate in DC, AC, and Transient analysis modes. Note that the
limit range is the value BELOW THE CNTL_UPPER LIMIT AND ABOVE THE CNTL_LOWER
LIMIT at which smoothing of the output begins (minimum positive value of voltage must exist
between the CNTL_UPPER input and the CNTL_LOWER input at all times). For this model,
then, the limit range represents the delta WITH RESPECT TO THE OUTPUT LEVEL at which
smoothing occurs. Thus, for an input gain of 2.0 and output limits of 1.0 and -1.0 volts, the output
will begin to smooth out at
±0.9
volts, which occurs when the input value is at
±0.4.
Note also
that the Controlled Limiter code tests the input values of cntl_lower and cntl_upper to make sure
that they are spaced far enough apart to guarantee the existence of a linear range between them.
The range is calculated as the dierence between (cntl_upper - upper_delta - limit_range) and
(cntl_lower + lower_delta + limit_range) and must be greater than or equal to zero. Note that
when the limit range is speci ed as a fractional value, the limit range used in the above is taken
as the calculated fraction of the dierence between cntl upper and cntl lower. Still, the potential
exists for too great a limit range value to be speci ed for proper operation, in which case the model
will return an error message.
Example SPICE Usage:
a6 3 6 8 4 varlimit
.
.
.model varlimit climit(in_offset=0.1 gain=2.5 upper_delta=0.0
13.2. ANALOG MODELS
101
+ lower_delta=0.0 limit_range=0.10 fraction=FALSE)
13.2.7 PWL Controlled Source
NAME_TABLE:
C_Function_Name:
Spice_Model_Name:
Description:
PORT_TABLE:
Port_Name:
Description:
Direction:
Default_Type:
Allowed_Types:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
STATIC_VAR_TABLE:
Static_Var_Name:
Data_Type:
Description:
cm_pwl
pwl
"piecewise linear controlled source"
in
"input"
in
v
[v,vd,i,id,vnam]
no
no
out
"output"
out
v
[v,vd,i,id]
no
no
x_array
"x-element array"
real
yes
[2 -]
no
y_array
"y-element array"
real
yes
[2 -]
no
input_domain
"input sm. domain"
real
0.01
[1e-12 0.5]
no
yes
fraction
"smoothing %/abs switch"
boolean
TRUE
no
yes
last_x_value
pointer Description:
"iteration holding variable for limiting"
The Piece-Wise Linear Controlled Source is a single input, single output function similar
to the Gain Block. However, the output of the PWL Source is not necessarily linear for all values
of input.
Instead, it follows an I/O relationship speci ed by you via the x_array and y_array
coordinates. This is detailed below.
The x_array and y_array values represent vectors of coordinate points on the x and y axes, respectively. The x_array values are progressively increasing input coordinate points, and the associated
y_array values represent the outputs at those points. There may be as few as two (x_array[n],
y_array[n]) pairs speci ed, or as many as memory and simulation speed allow. This permits you to
very nely approximate a non-linear function by capturing multiple input-output coordinate points.
Two aspects of the PWL Controlled Source warrant special attention. These are the handling of
endpoints and the smoothing of the described transfer function near coordinate points.
In order to fully specify outputs for values of in outside of the bounds of the PWL function (i.e.,
less than x_array[0] or greater than x_array[n], where n is the largest userspeci ed coordinate index), the PWL Controlled Source model extends the slope found between the lowest two coordinate
pairs and the highest two coordinate pairs.
This has the eect of making the transfer function
completely linear for in less than x_array[0] and in greater than x_array[n].
It also has the
potentially subtle eect of unrealistically causing an output to reach a very large or small value for
large inputs. You should thus keep in mind that the PWL Source does not inherently provide a
limiting capability.
In order to diminish the potential for nonconvergence of simulations when using the PWL block, a
CHAPTER 13. BEHAVIORAL MODELING
102
form of smoothing around the x_array, y_array coordinate points is necessary. This is due to the
iterative nature of the simulator and its reliance on smooth rst derivatives of transfer functions in
order to arrive at a matrix solution. Consequently, the input_domain and fraction parameters
are included to allow you some control over the amount and nature of the smoothing performed.
Fraction is a switch that is either TRUE or FALSE. When TRUE (the default setting), the
simulator assumes that the speci ed input domain value is to be interpreted as a fractional gure.
Otherwise, it is interpreted as an absolute value. Thus, if fraction=TRUE and input_domain=0.10,
The simulator assumes that the smoothing radius about each coordinate point is to be set equal
to 10% of the length of either the x_array segment above each coordinate point, or the x_array
segment below each coordinate point. The speci c segment length chosen will be the smallest of
these two for each coordinate point.
On the other hand, if fraction=FALSE and input=0.10, then the simulator will begin smoothing
the transfer function at 0.10 volts (or amperes) below each x_array coordinate and will continue
the smoothing process for another 0.10 volts (or amperes) above each x_array coordinate point.
Since the overlap of smoothing domains is not allowed, checking is done by the model to ensure
that the speci ed input domain value is not excessive.
One subtle consequence of the use of the fraction=TRUE feature of the PWL Controlled Source is
that, in certain cases, you may inadvertently create extreme smoothing of functions by choosing inappropriate coordinate value points. This can be demonstrated by considering a function described
by three coordinate pairs, such as (-1,-1), (1,1), and (2,1). In this case, with a 10% input_domain
value speci ed (fraction=TRUE, input domain=0.10), you would expect to see rounding occur between in=0.9 and in=1.1, and nowhere else. On the other hand, if you were to specify the same
function using the coordinate pairs (-100,-100), (1,1) and (201,1), you would nd that rounding occurs between in=-19 and in=21. Clearly in the latter case the smoothing might cause an excessive
divergence from the intended linearity above and below in=1.
Example SPICE Usage:
a7 2 4 xfer_cntl1
.
.
.model xfer_cntl1 pwl(x_array=[-2.0 -1.0 2.0 4.0 5.0]
+
y_array=[-0.2 -0.2 0.1 2.0 10.0]
+
input_domain=0.05 fraction=TRUE)
13.2.8 Analog Switch
NAME_TABLE:
C_Function_Name:
Spice_Model_Name:
Description:
PORT_TABLE:
Port Name:
Description:
Direction:
Default_Type:
Allowed_Types:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
cm_aswitch
aswitch
"analog switch"
cntl_in
"input"
in
v
[v,vd,i,id]
no
no
out
"resistive output"
out
gd
[gd]
no
no
cntl_off
cntl_on
"control `off' value" "control `on' value"
real
real
0.0
1.0
no
no
yes
yes
13.2. ANALOG MODELS
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
Description:
103
r_off
"off resistance"
real
1.0e12
no
yes
log
"log/linear switch"
boolean
TRUE
no
yes
r_on
"on resistance"
real
1.0
no
yes
The Analog Switch is a resistor that varies either logarithmically or linearly between spec-
i ed values of a controlling input voltage or current. Note that the input is not internally limited.
Therefore, if the controlling signal exceeds the speci ed OFF state or ON state value, the resistance
may become excessively large or excessively small (in the case of logarithmic dependence), or may
become negative (in the case of linear dependence). For the experienced user, these excursions may
prove valuable for modeling certain devices, but in most cases you are advised to add limiting of
the controlling input if the possibility of excessive control value variation exists.
Example SPICE Usage:
a8 3 (6 7) switch3
.
.
.model switch3 aswitch(cntl_off=0.0 cntl_on=5.0 r_off=1e6
+
r_on=10.0 log=TRUE)
13.2.9 Zener Diode
NAME_TABLE:
C_Function_Name:
Spice_Model_Name:
Description:
PORT_TABLE:
Port Name:
Description:
Direction:
Default_Type:
Allowed_Types:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
cm_zener
zener
"zener diode"
z
"zener"
inout
gd
[gd]
no
no
v_breakdown
"breakdown voltage"
real
[1.0e-6 1.0e6]
no
no
i_breakdown
"breakdown current"
real
2.0e-2
[1.0e-9 -]
no
yes
i_sat
n_forward
CHAPTER 13. BEHAVIORAL MODELING
104
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
STATIC_VAR_TABLE:
Static_Var_Name:
Data_Type:
Description:
Description:
"saturation current" "forward emission coefficient"
real
real
1.0e-12
1.0
[1.0e-15 -]
[0.1 10]
no
no
yes
yes
limit_switch
"switch for on-board limiting (convergence aid)"
boolean
FALSE
no
yes
previous_voltage
pointer
"iteration holding variable for limiting"
The Zener Diode models the DC characteristics of most zeners. This model diers from
the Diode/Recti er by providing a user-de ned dynamic resistance in the reverse breakdown region.
The forward characteristic is de ned by only a single point, since most data sheets for zener diodes
do not give detailed characteristics in the forward region.
The rst three parameters de ne the DC characteristics of the zener in the breakdown region and
are usually explicitly given on the data sheet.
The saturation current refers to the relatively constant reverse current that is produced when the
voltage across the zener is negative, but breakdown has not been reached.
The reverse leakage
current determines the slight increase in reverse current as the voltage across the zener becomes
more negative. It is modeled as a resistance parallel to the zener with value v breakdown / i rev.
Note that the limit switch parameter engages an internal limiting function for the zener. This can,
in some cases, prevent the simulator from converging to an unrealistic solution if the voltage across
or current into the device is excessive. If use of this feature fails to yield acceptable results, the
convlimit option should be tried (add the following statement to the SPICE input deck: .options
convlimit)
Example SPICE Usage:
a9 3 4 vref10
.
.
.model vref10 zener(v_breakdown=10.0 i_breakdown=0.02
+
r_breakdown=1.0 i_rev=1e-6 i_sat=1e-12)
13.2.10 Current Limiter
NAME_TABLE:
C_Function_Name:
Spice_Model_Name:
Description:
PORT_TABLE:
Port Name:
Description:
Direction:
Default_Type:
Allowed_Types:
Vector:
Vector_Bounds:
Null_Allowed:
cm_ilimit
ilimit
"current limiter block"
in
"input"
in
v
[v,vd]
no
no
pos_pwr
"positive power supply"
inout
g
[g,gd]
no
yes
13.2. ANALOG MODELS
PORT_TABLE:
Port Name:
Description:
Direction:
Default_Type:
Allowed_Types:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
105
neg_pwr
"negative power supply"
inout
g
[g,gd]
no
yes
out
"output"
inout
g
[g,gd]
no
no
in_offset
"input offset"
real
0.0
no
yes
gain
"gain"
real
1.0
no
yes
r_out_source
"sourcing resistance"
real
1.0
[1.0e-9 1.0e9]
no
yes
r_out_sink
"sinking resistance"
real
1.0
[1.0e-9 1.0e9]
no
yes
i_limit_source
"current sourcing limit"
real
[1.0e-12 -]
no
yes
i_limit_sink
"current sinking limit"
real
[1.0e-12 -]
no
yes
v_pwr_range
"upper & lower power
supply smoothing range"
real
1.0e-6
[1.0e-15 -]
no
yes
i_source_range
"sourcing current
smoothing range"
real
1.0e-9
[1.0e-15 -]
no
yes
i_sink_range
"sinking current smoothing range"
CHAPTER 13. BEHAVIORAL MODELING
106
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
Description:
real
1.0e-9
[1.0e-15 -]
no
yes
r_out_domain
"internal/external voltage delta smoothing range"
real
1.0e-9
[1.0e-15 -]
no
yes
The Current Limiter models the behavior of an operational ampli er or comparator device
at a high level of abstraction. All of its pins act as inputs; three of the four also act as outputs.
The model takes as input a voltage value from the in connector. It then applies an oset and a
gain, and derives from it an equivalent internal voltage (veq), which it limits to fall between pos
pwr and neg pwr. If veq is greater than the output voltage seen on the out connector, a sourcing
current will ow from the output pin. Conversely, if the voltage is less than vout, a sinking current
will ow into the output pin.
Depending on the polarity of the current ow, either a sourcing or a sinking resistance value
(r_out_source, r_out_sink) is applied to govern the vout/i_out relationship. The chosen resistance will continue to control the output current until it reaches a maximum value speci ed by
either i_limit_source or i_limit_sink. The latter mimics the current limiting behavior of many
operational ampli er output stages.
During all operation, the output current is re ected either in the pos_pwr connector current or the
neg_pwr current, depending on the polarity of i_out. Thus, realistic power consumption as seen
in the supply rails is included in the model.
The user-speci ed smoothing parameters relate to model operation as follows: v_pwr_range controls the voltage below vpos_pwr and above vneg_pwr inputs beyond which veq [= gain * (vin +
voset)] is smoothed; i_source_range speci es the current below i_limit_source at which smoothing begins, as well as specifying the current increment above i_out=0.0 at which i_pos_pwr begins to transition to zero; i_sink_range serves the same purpose with respect to i_limit_sink and
i_neg_pwr that i_source_range serves for i_limit_source & i_pos_pwr; r_out_domain speci es
the incremental value above and below (veq-vout)=0.0 at which r_out will be set to r_out_source
and r_out_sink, respectively. For values of (veq- vout) less than r_out_domain and greater than
-r_out_domain, r_out is interpolated smoothly between r_out_source & r_out_sink.
Example SPICE Usage:
a10 3 10 20 4 amp3
.
.
.model amp3 ilimit(in_offset=0.0 gain=16.0 r_out_source=1.0
+
r_out_sink=1.0 i_limit_source=1e-3
+
i_limit_sink=10e-3 v_pwr_range=0.2
+
i_source_range=1e-6 i_sink_range=1e-6
+
r_out_domain=1e-6)
13.2.11 Hysteresis Block
NAME_TABLE:
C_Function_Name:
Spice_Model_Name:
Description:
PORT_TABLE:
Port Name:
cm_hyst
hyst
"hysteresis block"
in
out
13.2. ANALOG MODELS
Description:
Direction:
Default_Type:
Allowed_Types:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
Description:
107
"input"
in
v
[v,vd,i,id]
no
no
"output"
out
v
[v,vd,i,id]
no
no
in_low
"input low value"
real
0.0
no
yes
in_high
"input high value"
real
1.0
no
yes
hyst
"hysteresis"
real
0.1
[0.0 -]
no
yes
out_lower_limit
"output lower limit"
real
0.0
no
yes
out_upper_limit
input_domain
"output upper limit" "input smoothing domain"
real
real
1.0
0.01
no
no
yes
yes
fraction
"smoothing fraction/absolute value switch"
boolean
TRUE
no
yes
The Hysteresis block is a simple buer stage that provides hysteresis of the output with
respect to the input. The in low and in high parameter values specify the center voltage or current
inputs about which the hysteresis eect operates. The output values are limited to out lower limit
and out upper limit.
The value of hyst is added to the in low and in high points in order to
specify the points at which the slope of the hysteresis function would normally change abruptly as
the input transitions from a low to a high value. Likewise, the value of hyst is subtracted from
the in high and in low values in order to specify the points at which the slope of the hysteresis
function would normally change abruptly as the input transitions from a high to a low value. In
fact, the slope of the hysteresis function is never allowed to change abruptly but is smoothly varied
whenever the input domain smoothing parameter is set greater than zero.
Example SPICE Usage:
a11 1 2 schmitt1
.
.
CHAPTER 13. BEHAVIORAL MODELING
108
.model schmitt1 hyst(in_low=0.7 in_high=2.4 hyst=0.5
+
out_lower_limit=0.5 out_upper_limit=3.0
+
input_domain=0.01 fraction=TRUE)
13.2.12 Dierentiator
NAME_TABLE:
C_Function_Name:
Spice_Model_Name:
Description:
PORT_TABLE:
Port Name:
Description:
Direction:
Default_Type:
Allowed_Types:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
Description:
cm_d_dt
d_dt
"time-derivative block"
in
"input"
in
v
[v,vd,i,id]
no
no
out
"output"
out
v
[v,vd,i,id]
no
no
gain
"gain"
real
1.0
no
yes
out_offset
"output offset"
real
0.0
no
yes
out_lower_limit
out_upper_limit
"output lower limit" "output upper limit"
real
real
no
no
yes
yes
limit_range
"upper & lower limit smoothing range"
real
1.0e-6
no
yes
The Dierentiator block is a simple derivative stage that approximates the time derivative
of an input signal by calculating the incremental slope of that signal since the previous timepoint.
The block also includes gain and output oset parameters to allow for tailoring of the required
signal, and output upper and lower limits to prevent convergence errors resulting from excessively
large output values. The incremental value of output below the output upper limit and above the
output lower limit at which smoothing begins is speci ed via the limit range parameter.
In AC
analysis, the value returned is equal to the radian frequency of analysis multiplied by the gain.
Note that since truncation error checking is not included in the d_dt block, it is not recommended
that the model be used to provide an integration function through the use of a feedback loop. Such
an arrangement could produce erroneous results. Instead, you should make use of the "integrate"
model, which does include truncation error checking for enhanced accuracy.
Example SPICE Usage:
13.2. ANALOG MODELS
109
a12 7 12 slope_gen
.
.
.model slope_gen d_dt(out_offset=0.0 gain=1.0
+
out_lower_limit=1e-12 out_upper_limit=1e12
+
limit_range=1e-9)
13.2.13 Integrator
NAME_TABLE:
C_Function_Name:
Spice_Model_Name:
Description:
PORT_TABLE:
Port Name:
Description:
Direction:
Default_Type:
Allowed_Types:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
cm_int
int
"time-integration block"
in
"input"
in
v
[v,vd,i,id]
no
no
out
"output"
out
v
[v,vd,i,id]
no
no
in_offset
"input offset"
real
0.0
no
yes
gain
"gain"
real
1.0
no
yes
out_lower_limit
out_upper_limit
"output lower limit" "output upper limit"
real
real
no
no
yes
yes
limit_range
"upper & lower limit smoothing range"
real
1.0e-6
no
yes
out_ic
"output initial condition"
real
0.0
no
yes
CHAPTER 13. BEHAVIORAL MODELING
110
Description:
The Integrator block is a simple integration stage that approximates the integral with
respect to time of an input signal.
The block also includes gain and input oset parameters to
allow for tailoring of the required signal, and output upper and lower limits to prevent convergence
errors resulting from excessively large output values.
Note that these limits specify integrator
behavior similar to that found in an operational ampli er-based integration stage, in that once
a limit is reached, additional storage does not occur.
Thus, the input of a negative value to an
integrator which is currently driving at the out upper limit level will immediately cause a drop
in the output, regardless of how long the integrator was previously summing positive inputs. The
incremental value of output below the output upper limit and above the output lower limit at which
smoothing begins is speci ed via the limit range parameter. In AC analysis, the value returned is
equal to the gain divided by the radian frequency of analysis.
Note that truncation error checking is included in the int block. This should provide for a more
accurate simulation of the time integration function, since the model will inherently request smaller
time increments between simulation points if truncation errors would otherwise be excessive.
Example SPICE Usage:
a13 7 12 time_count
.
.
.model time_count int(in_offset=0.0 gain=1.0
+
out_lower_limit=-1e12 out_upper_limit=1e12
+
limit_range=1e-9 out_ic=0.0)
13.2.14 S-Domain Transfer Function
NAME_TABLE:
C_Function_Name:
Spice_Model_Name:
Description:
PORT_TABLE:
Port Name:
Description:
Direction:
Default_Type:
Allowed_Types:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
cm_s_xfer
s_xfer
"s-domain transfer function"
in
"input"
in
v
[v,vd,i,id]
no
no
out
"output"
out
v
[v,vd,i,id]
no
no
in_offset
"input offset"
real
0.0
no
yes
gain
"gain"
real
1.0
no
yes
num_coeff
"numerator polynomial coefficients"
real
yes
[1 -]
no
den_coeff
"denominator polynomial coefficients"
13.2. ANALOG MODELS
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
Description:
111
real
yes
[1 -]
no
int_ic
"integrator stage initial conditions"
real
0.0
yes
den_coeff
yes
denormalized_freq
"denorm. corner freq.(radians) for 1 rad/s coeffs"
real
1.0
no
yes
The s-domain transfer function is a single input, single output transfer function in the
Laplace transform variable s that allows for exible modulation of the frequencydomain characteristics of a signal. The code model may be con gured to produce an arbitrary s-domain transfer
function with the following restrictions:
1. The degree of the numerator polynomial cannot exceed that
of the denominator polynomial in the variable "s".
2. The coefficients for a polynomial must be stated
explicitly. That is, if a coefficient is zero, it must be
included as an input to the num coeff or den coeff vector.
The order of the coe cient parameters is from that associated with the highest-powered term decreasing
to that of the lowest. Thus, for the coe cient parameters speci ed below, the equation in s is shown:
.model filter s_xfer(gain=0.139713 num_coeff=[1.0 0.0 0.07464102]
+
den_coeff=[1.0 0.998942 0.01170077])
...specifies a transfer function of the form...
2
s +0.7464102
}
N (s) = 0.139713 · { s2 +0.998942s+0.00117077
The s-domain transfer function includes gain and input oset parameters to allow for tailoring of the
required signal. There are no limits on the internal signal values or on the output value of the s-domain
transfer function, so you are cautioned to specify gain and coe cient values that will not cause the model
to produce excessively large values. In AC analysis, the value returned is equal to the real and imaginary
components of the total s-domain transfer function at each frequency of interest.
The denormalized freq term allows you to specify coe cients for a normalized lter (i.e. one in which
the frequency of interest is 1 rad/s). Once these coe cients are included, specifying the denormalized
frequency value shifts the corner frequency to the actual one of interest. As an example, the following
transfer function describes a Chebyshev lowpass lter with a corner (passband) frequency of 1 rad/s:
1.0
}
N (s) = 0.139713 · { s2 +1.09773s+1.10251
In order to de ne an s_xfer model for the above, but with the corner frequency equal to 1500 rad/s
(9425 Hz), the following instance and model lines would be needed:
CHAPTER 13. BEHAVIORAL MODELING
112
a12 cheby1
.model cheby1 s_xfer(num_coeff=[1] den_coeff=[1 1.09773 1.10251]
+
denormalized_freq=1500)
In the above, you add the normalized coe cients and scales the lter through the use of the denormalized
freq parameter.
Similar results could have been achieved by performing the denormalization prior to
speci cation of the coe cients, and setting denormalized freq to the value 1.0 (or not specifying the
frequency, as the default is 1.0 rad/s) Note in the above that frequencies are ALWAYS SPECIFIED AS
RADIANS/SECOND.
Truncation error checking is included in the s-domain transfer block. This should provide for more
accurate simulations, since the model will inherently request smaller time increments between simulation
points if truncation errors would otherwise be excessive.
Example SPICE Usage:
a14 9 22 cheby_LP_3KHz
.
.
.model cheby_LP_3KHz s_xfer(in_offset=0.0 gain=1.0 num_coeff=[1.0]
+
den_coeff=[1.0 1.42562 1.51620])
13.2.15 Slew Rate Block
NAME_TABLE:
C_Function_Name:
Spice_Model_Name:
Description:
PORT_TABLE:
Port Name:
Description:
Direction:
Default_Type:
Allowed_Types:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
cm_slew
slew
"A simple slew rate follower block"
in
"input"
in
v
[v,vd,i,id]
no
no
out
"output"
out
v
[v,vd,i,id]
no
no
rise_slope
"maximum rising slope value"
real
1.0e9
no
yes
fall_slope
"maximum falling slope value"
real
1.0e9
no
yes
range
"smoothing range"
real
0.1
-
13.2. ANALOG MODELS
Vector:
Vector_Bounds:
Null_Allowed:
Description:
113
no
yes
This function is a simple slew rate block that limits the absolute slope of the output
with respect to time to some maximum or value. The actual slew rate eects of over-driving an
ampli er circuit can thus be accurately modeled by cascading the ampli er with this model. The
units used to describe the maximum rising and falling slope values are expressed in volts or amperes
per second. Thus a desired slew rate of 0.5 V/µs will be expressed as 0.5e+6, etc.
The slew rate block will continue to raise or lower its output until the dierence between the input
and the output values is zero. Thereafter, it will resume following the input signal, unless the slope
again exceeds its rise or fall slope limits. The range input speci es a smoothing region above or
below the input value. Whenever the model is slewing and the output comes to within the input
+ or - the range value, the partial derivative of the output with respect to the input will begin
to smoothly transition from 0.0 to 1.0.
When the model is no longer slewing (output = input),
dout/din will equal 1.0.
Example SPICE Usage:
a15 1 2 slew1
.model slew1 slew(rise_slope=0.5e6 fall_slope=0.5e6)
13.2.16 Inductive Coupling
NAME_TABLE:
C_Function_Name:
Spice_Model_Name:
Description:
PORT_TABLE:
Port_Name:
Description:
Direction:
Default_Type:
Allowed_Types:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
Description:
cm_lcouple
lcouple
"inductive coupling (for use with 'core' model)"
l
"inductor"
inout
hd
[h,hd]
no
no
mmf_out
"mmf output (in ampere-turns)"
inout
hd
[hd]
no
no
num_turns
"number of inductor turns"
real
1.0
no
yes
This function is a conceptual model which is used as a building block to create a wide
variety of inductive and magnetic circuit models. This function is normally used in conjunction with
the core model, but can also be used with resistors, hysteresis blocks, etc. to build up systems
which mock the behavior of linear and nonlinear components.
The lcouple takes as an input (on the l port) a current. This current value is multiplied by the
num_turns value, N, to produce an output value (a voltage value which appears on the mmf_out
port). The mmf_out acts similar to a magnetomotive force in a magnetic circuit; when the lcouple
is connected to the core model, or to some other resistive device, a current will ow. This current
value (which is modulated by whatever the lcouple is connected to) is then used by the lcouple to
calculate a voltage seen at the l port. The voltage is a function of the derivative with respect
to time of the current value seen at mmf_out.
The most common use for lcouples will be as a building block in the construction of transformer
models. To create a transformer with a single input and a single output, you would require two
CHAPTER 13. BEHAVIORAL MODELING
114
lcouple models plus one core model. The process of building up such a transformer is described
under the description of the core model, below.
Example SPICE Usage:
a150 (7 0) (9 10) lcouple1
.model lcouple1 lcouple(num_turns=10.0)
13.2.17 Magnetic Core
NAME_TABLE:
C_Function_Name:
Spice_Model_Name:
Description:
PORT_TABLE:
Port_Name:
Description:
Direction:
Default_Type:
Allowed_Types:
Vector: no
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
cm_core
core
"magnetic core"
mc
"magnetic core"
inout
gd
[g,gd]
no
H_array
"magnetic field array"
real
yes
[2 -]
no
B_array
"flux density array"
real
yes
[2 -]
no
area
"cross-sectional area"
real
no
no
length
"core length"
real
no
no
input_domain
"input sm. domain"
real
0.01
[1e-12 0.5]
no
yes
fraction
"smoothing fraction/abs switch"
boolean
TRUE
no
yes
13.2. ANALOG MODELS
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
Description:
115
mode
"mode switch (1 = pwl, 2 = hyst)"
int
1
[1 2]
no
yes
in_low
"input low value"
real
0.0
no
yes
in_high
"input high value"
real
1.0
no
yes
hyst
"hysteresis"
real
0.1
[0 -]
no
yes
out_lower_limit
"output lower limit"
real
0.0
no
yes
out_upper_limit
"output upper limit"
real
1.0
no
yes
This function is a conceptual model which is used as a building block to create a wide
variety of inductive and magnetic circuit models. This function is almost always expected to be
used in conjunction with the lcouple model to build up systems which mock the behavior of linear
and nonlinear magnetic components. There are two fundamental modes of operation for the core
model. These are the pwl mode (which is the default, and which is the most likely to be of use to
you) and the hysteresis mode. These are detailed below.
PWL Mode (mode = 1)
The core model in PWL mode takes as input a voltage which it treats as a magnetomotive force
(mmf ) value. This value is divided by the total eective length of the core to produce a value for the
Magnetic Field Intensity, H. This value of H is then used to nd the corresponding Flux Density, B, using
the piecewise linear relationship described by you in the H array / B array coordinate pairs. B is then
multiplied by the cross-sectional area of the core to nd the Flux value, which is output as a current.
The pertinent mathematical equations are listed below:
H = mmf =L, where L = Length
Here H, the Magnetic Field Intensity, is expressed in ampere-turns/meter.
B = f (H)
The B value is derived from a piecewise linear transfer function described to the model via the
(H_array[],B_array[]) parameter coordinate pairs.
This transfer function does not include hysteretic
eects; for that, you would need to substitute a HYST model for the core.
CHAPTER 13. BEHAVIORAL MODELING
116
φ
= BA, where A = Area
The nal current allowed to ow through the core is equal to
φ.
This value in turn is used by the
"lcouple" code model to obtain a value for the voltage re ected back across its terminals to the driving
electrical circuit.
The following example code shows the use of two lcouple models and one core model to produce a
simple primary/secondary transformer.
Example SPICE Usage:
a1 (2 0) (3 0) primary
.model primary lcouple (num_turns = 155)
a2 (3 4) iron_core
.model iron_core core (H_array = [-1000 -500 -375 -250 -188 -125 -63 0
+
63 125 188 250 375 500 1000]
+
B_array = [-3.13e-3 -2.63e-3 -2.33e-3 -1.93e-3
+
-1.5e-3 -6.25e-4 -2.5e-4 0 2.5e-4
+
6.25e-4 1.5e-3 1.93e-3 2.33e-3
+
2.63e-3 3.13e-3]
+
area = 0.01 length = 0.01)
a3 (5 0) (4 0) secondary
.model secondary lcouple (num_turns = 310)
HYSTERESIS Mode (mode = 2)
The core model in HYSTERESIS mode takes as input a voltage which it treats as a magnetomotive
force (mmf ) value. This value is used as input to the equivalent of a hysteresis code model block. The
parameters de ning the input low and high values, the output low and high values, and the amount of
hysteresis are as in that model. The output from this mode, as in PWL mode, is a current value which
is seen across the mc port. An example of the core model used in this fashion is shown below:
Example SPICE Usage:
a1 (2 0) (3 0) primary
.model primary lcouple (num_turns = 155)
a2 (3 4) iron_core
.model iron_core core (mode = 2 in_low=-7.0 in_high=7.0
+
out_lower_limit=-2.5e-4 out_upper_limit=2.5e-4
+
hyst = 2.3 )
a3 (5 0) (4 0) secondary
.model secondary lcouple (num_turns = 310)
One nal note to be made about the two core model nodes is that certain parameters are available in one
mode, but not in the other. In particular, the in_low, in_high, out_lower_limit, out_upper_limit, and
hysteresis parameters are not available in PWL mode. Likewise, the H_array, B_array, area, and length
values are unavailable in HYSTERESIS mode. The input domain and fraction parameters are common
to both modes (though their behavior is somewhat dierent; for explanation of the input domain and
fraction values for the HYSTERESIS mode, you should refer to the hysteresis code model discussion).
13.2.18 Controlled Sine Wave Oscillator
NAME_TABLE:
C_Function_Name:
Spice_Model_Name:
Description:
PORT_TABLE:
Port Name:
Description:
Direction:
Default_Type:
Allowed_Types:
Vector:
cm_sine
sine
"controlled sine wave oscillator"
cntl_in
"control input"
in
v
[v,vd,i,id]
no
out
"output"
out
v
[v,vd,i,id]
no
13.2. ANALOG MODELS
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
Description:
117
no
no
cntl_array
"control array"
real
0.0
yes
[2 -]
no
freq_array
"frequency array"
real
1.0e3
[0 -]
yes
cntl_array
no
out_low
out_high
"output peak low value" "output peak high value"
real
real
-1.0
1.0
no
no
yes
yes
This function is a controlled sine wave oscillator with parameterizable values of low and
high peak output. It takes an input voltage or current value. This value is used as the independent
variable in the piecewise linear curve described by the coordinate points of the cntl array and freq
array pairs. From the curve, a frequency value is determined, and the oscillator will output a sine
wave at that frequency. From the above, it is easy to see that array sizes of 2 for both the cntl array
and the freq array will yield a linear variation of the frequency with respect to the control input.
Any sizes greater than 2 will yield a piecewise linear transfer characteristic. For more detail, refer
to the description of the piecewise linear controlled source, which uses a similar method to derive
an output value given a control input.
Example SPICE Usage:
asine 1 2 in_sine
.model in_sine sine(cntl_array = [-1 0 5 6]
+
freq_array=[10 10 1000 1000] out_low = -5.0
+
out_high = 5.0)
13.2.19 Controlled Triangle Wave Oscillator
NAME_TABLE:
C_Function_Name:
Spice_Model_Name:
Description:
PORT_TABLE:
Port Name:
Description:
Direction:
Default_Type:
Allowed_Types:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
cm_triangle
triangle
"controlled triangle wave oscillator"
cntl_in
"control input"
in
v
[v,vd,i,id]
no
no
out
"output"
out
v
[v,vd,i,id]
no
no
cntl_array
"control array"
real
0.0
yes
freq_array
"frequency array"
real
1.0e3
[0 -]
yes
CHAPTER 13. BEHAVIORAL MODELING
118
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
Description:
[2 -]
no
cntl_array
no
out_low
out_high
"output peak low value" "output peak high value"
real
real
-1.0
1.0
no
no
yes
yes
rise_duty
"rise time duty cycle"
real
0.5
[1e-10 0.999999999]
no
yes
This function is a controlled triangle/ramp wave oscillator with parameterizable values of
low and high peak output and rise time duty cycle. It takes an input voltage or current value. This
value is used as the independent variable in the piecewise linear curve described by the coordinate
points of the cntl_array and freq_array pairs.
From the curve, a frequency value is determined, and the oscillator will output a triangle wave at
that frequency. From the above, it is easy to see that array sizes of 2 for both the cntl_array and
the freq_array will yield a linear variation of the frequency with respect to the control input. Any
sizes greater than 2 will yield a piecewise linear transfer characteristic. For more detail, refer to
the description of the piecewise linear controlled source, which uses a similar method to derive an
output value given a control input.
Example SPICE Usage:
ain 1 2 ramp1
.model ramp1 triangle(cntl_array = [-1 0 5 6]
+
freq_array=[10 10 1000 1000] out_low = -5.0
+
out_high = 5.0 duty_cycle = 0.9)
13.2.20 Controlled Square Wave Oscillator
NAME_TABLE:
C_Function_Name:
Spice_Model_Name:
Description:
PORT_TABLE:
Port Name:
Description:
Direction:
Default_Type:
Allowed_Types:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
cm_square
square
"controlled square wave oscillator"
cntl_in
"control input"
in
v
[v,vd,i,id]
no
no
out
"output"
out
v
[v,vd,i,id]
no
no
cntl_array
"control array"
real
0.0
-
freq_array
"frequency array"
real
1.0e3
[0 -]
13.2. ANALOG MODELS
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER.TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector: no
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
Description:
119
yes
[2 -]
no
yes
cntl_array
no
out_low
out_high
"output peak low value" "output peak high value"
real
real
-1.0
1.0
no
no
yes
yes
duty_cycle
"duty cycle"
real
0.5
[1e-6 0.999999]
rise_time
"output rise time"
real
1.0e-9
-
yes
yes
fall_time
"output fall time"
real
1.0e-9
no
yes
This function is a controlled square wave oscillator with parameterizable values of low
and high peak output, duty cycle, rise time, and fall time.
value.
It takes an input voltage or current
This value is used as the independent variable in the piecewise linear curve described by
the coordinate points of the cntl_array and freq_array pairs. From the curve, a frequency value is
determined, and the oscillator will output a square wave at that frequency.
From the above, it is easy to see that array sizes of 2 for both the cntl_array and the freq_array
will yield a linear variation of the frequency with respect to the control input. Any sizes greater
than 2 will yield a piecewise linear transfer characteristic. For more detail, refer to the description
of the piecewise linear controlled source, which uses a similar method to derive an output value
given a control input.
Example SPICE Usage:
ain 1 2 pulse1
.model pulse1 square(cntl_array = [-1 0 5 6]
+
freq_array=[10 10 1000 1000] out_low = 0.0
+
out_high = 4.5 duty_cycle = 0.2
+
rise_time = 1e-6 fall_time = 2e-6)
13.2.21 Controlled One-Shot
NAME_TABLE:
C_Function_Name:
Spice_Model_Name:
Description:
PORT_TABLE:
Port Name:
Description:
Direction:
cm_oneshot
oneshot
"controlled one-shot"
cntl_in
"control input"
in
clk
"clock input"
out
CHAPTER 13. BEHAVIORAL MODELING
120
Default_Type:
Allowed_Types:
Vector:
Vector_Bounds:
Null_Allowed:
PORT_TABLE:
Port Name:
Description:
Direction:
Default_Type:
Allowed_Types:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
v
[v,vd,i,id]
no
no
v
[v,vd,i,id]
no
no
out
"output"
out
v
[v,vd,i,id]
no
no
clk_trig
"clock trigger value"
real
0.5
no
no
pos_edge_trig
"positive/negative edge trigger switch"
boolean
TRUE
no
no
cntl_array
"control array"
real
0.0
yes
yes
pw_array
"pulse width array"
real
1.0e-6
[0.00 -]
yes
cntl_array
yes
out_low
"output low value"
real
0.0
no
yes
out_high
"output high value"
real
1.0
no
yes
delay
rise_time
"output delay from trig." "output rise time"
real
real
1.0e-9
1.0e-9
no
no
-
13.2. ANALOG MODELS
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
Description:
121
yes
yes
fall_time
"output fall time"
real
1.0e-9
yes
This function is a controlled oneshot with parameterizable values of low and high peak
output, input trigger value level, delay, and output rise and fall times. It takes an input voltage or
current value. This value is used as the independent variable in the piecewise linear curve described
by the coordinate points of the cntl_array and pw_array pairs.
From the curve, a pulse width
value is determined, and the oscillator will output a pulse of that width, delayed by the delay value,
and with speci ed rise and fall times.
From the above, it is easy to see that array sizes of 2 for both the cntl_array and the pw_array
will yield a linear variation of the pulse width with respect to the control input. Any sizes greater
than 2 will yield a piecewise linear transfer characteristic. For more detail, refer to the description
of the piecewise linear controlled source, which uses a similar method to derive an output value
given a control input.
Example SPICE Usage:
ain 1 2 3 4 pulse2
.model pulse1 oneshot(cntl_array = [-1 0 10 11]
+
pw_array=[1e-6 1e-6 1e-4 1e-4]
+
clk_trig = 0.9 pos_edge_trig = FALSE
+
out_low = 0.0 out_high = 4.5 duty_cycle = 0.9
+
rise_delay = 20.0-9 fall_delay = 35.0e-9)
13.2.22 Capacitance Meter
NAME_TABLE:
C_Function_Name:
Spice_Model_Name:
Description:
PORT_TABLE:
Port Name:
Description:
Direction:
Default_Type:
Allowed_Types:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
Description:
cm_cmeter
cmeter
"capacitance meter"
in
"input"
in
v
[v,vd,i,id]
no
no
out
"output"
out
v
[v,vd,i,id]
no
no
gain
"gain"
real
1.0
no
yes
The capacitance meter is a sensing device which is attached to a circuit node and produces
as an output a scaled value equal to the total capacitance seen on its input multiplied by the gain
parameter. This model is primarily intended as a building block for other models which must sense
a capacitance value and alter their behavior based upon it.
CHAPTER 13. BEHAVIORAL MODELING
122
Example SPICE Usage:
atest1 1 2 ctest
.model ctest cmeter(gain=1.0e12)
13.2.23 Inductance Meter
NAME_TABLE:
C_Function_Name:
Spice_Model_Name:
Description:
PORT_TABLE:
Port Name:
Description:
Direction:
Default_Type:
Allowed_Types:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
Description:
cm_lmeter
lmeter
"inductance meter"
in
"input"
in
v
[v,vd,i,id]
no
no
out
"output"
out
v
[v,vd,i,id]
no
no
gain
"gain"
real
1.0
no
yes
The inductance meter is a sensing device which is attached to a circuit node and produces
as an output a scaled value equal to the total inductance seen on its input multiplied by the gain
parameter. This model is primarily intended as a building block for other models which must sense
an inductance value and alter their behavior based upon it.
Example SPICE Usage:
atest2 1 2 ltest
.model ltest lmeter(gain=1.0e6)
13.3
Hybrid Models
The following hybrid models are supplied with XSPICE. The descriptions included below consist of the
model Interface Speci cation File and a description of the model's operation.
This is followed by an
example of a simulator-deck placement of the model, including the .MODEL card and the speci cation
of all available parameters.
A note should be made with respect to the use of hybrid models for other than simple digital-toanalog and analog-to-digital translations.
The hybrid models represented in this section address that
speci c need, but in the development of user-de ned nodes you may nd a need to translate not only
betweem digital and analog nodes, but also between real and digital, real and int, etc. In most cases such
translations will not need to be as involved or as detailed as shown in the following.
13.3.1 Digital-to-Analog Node Bridge
NAME_TABLE:
C_Function_Name:
Spice_Model_Name:
Description:
PORT_TABLE:
Port Name:
Description:
cm_dac_bridge
dac_bridge
"digital-to-analog node bridge"
in
"input"
out
"output"
13.3. HYBRID MODELS
Direction:
Default_Type:
Allowed_Types:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
Description:
123
in
d
[d]
yes
no
out
v
[v,vd,i,id,d]
yes
no
out_low
"0-valued analog output"
real
0.0
no
yes
out.high
"1-valued analog output"
real
1.0
no
yes
out_undef
"U-valued analog output"
real
0.5
no
yes
input_load
"input load (F)"
real
1.0e-12
no
yes
t_rise
"rise time 0->1"
real
1.0e-9
no
yes
t_fall
"fall time 1->0"
real
1.0e-9
no
yes
The dac_bridge is the rst of two node bridge devices designed to allow for the ready
transfer of digital information to analog values and back again. The second device is the adc_bridge
(which takes an analog value and maps it to a digital one).The dac_bridge takes as input a digital
value from a digital node. This value by de nition may take on only one of the values 0, 1 or U.
The dac_bridge then outputs the value out_low, out_high or out_undef , or ramps linearly
toward one of these nal values from its current analog output level.
The speed at which this
ramping occurs depends on the values of t_rise and t_fall. These parameters are interpreted by
Note that the dac_bridge
includes test code in its cfunc.mod le for determining the presence of the out_undef
parameter. If this parameter is not speci ed by you, and if out_high and out_low
values are speci ed, then out_undef is assigned the value of the arithmetic mean of
out_high and out_low. This simpli es coding of output buers, where typically a logic family
the model such that the rise or fall slope generated is always constant.
will include an out_low and out_high voltage, but not an out_undef value. This model also posts
an input load value (in farads) based on the parameter input load.
Example SPICE Usage:
CHAPTER 13. BEHAVIORAL MODELING
124
abridge1 7 2 dac1
.model dac1 dac_bridge(out_low = 0.7 out_high = 3.5 out_undef = 2.2
+
input_load = 5.0e-12 t_rise = 50e-9
+
t_fall = 20e-9)
13.3.2 Analog-to-Digital Node Bridge
NAME_TABLE:
C_Function_Name:
Spice_Model_Name:
Description:
PORT_TABLE:
Port Name:
Description:
Direction:
Default_Type:
Allowed_Types:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
Description:
cm_adc_bridge
adc_bridge
"analog-to-digital node bridge"
in
"input"
in
v
[v,vd,i,id,d]
yes
no
out
"output"
out
d
[d]
yes
no
in_low
"maximum 0-valued analog input"
real
1.0
no
yes
in_high
"minimum 1-valued analog input"
real
2.0
no
yes
rise_delay
"rise delay"
real
1.0e-9
[1.0e-12 -]
no
yes
fall_delay
"fall delay"
real
1.0e-9
[1.0e-12 -]
no
yes
The adc_bridge is one of two node bridge devices designed to allow for the ready transfer
of analog information to digital values and back again. The second device is the dac_bridge (which
takes a digital value and maps it to an analog one). The adc_bridge takes as input an analog value
from an analog node. This value by de nition may be in the form of a voltage, or a current. If
the input value is less than or equal to in_low, then a digital output value of 0 is generated. If
the input is greater than or equal to in_high, a digital output value of 1 is generated. If neither
of these is true, then a digital UNKNOWN value is output.
Note that unlike the case of the
dac_bridge, no ramping time or delay is associated with the adc_bridge. Rather, the continuous
ramping of the input value provides for any associated delays in the digitized signal.
Example SPICE Usage:
13.3. HYBRID MODELS
125
abridge2 1 8 adc_buff
.model adc_buff adc_bridge(in_low = 0.3 in_high = 3.5)
13.3.3 Controlled Digital Oscillator
NAME_TABLE:
C_Function_Name:
Spice_Model_Name:
Description:
PORT_TABLE:
Port Name:
Description:
Direction:
Default_Type:
Allowed_Types:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
Description:
cm_d_osc
d_osc
"controlled digital oscillator"
cntl_in
"control input"
in
v
[v,vd,i,id]
no
no
out
"output"
out
d
[d]
no
no
cntl_array
"control array"
real
0.0
yes
[2 -]
no
freq_array
"frequency array"
real
1.0e6
[0 -]
yes
cntl_array
no
duty_cycle
"duty cycle"
real
0.5
[1e-6 0.999999]
no
yes
init_phase
"initial phase of output"
real
0
[-180.0 +360.0]
no
yes
rise_delay
"rise delay"
real
1e-9
[0 -]
no
yes
fall_delay
"fall delay"
real
1e-9
[0 -]
no
yes
The digital oscillator is a hybrid model which accepts as input a voltage or current. This in-
put is compared to the voltage-to-frequency transfer characteristic speci ed by the cntl_array/freq_array
coordinate pairs, and a frequency is obtained which represents a linear interpolation or extrapolation based on those pairs. A digital time-varying signal is then produced with this fundamental
frequency.
The output waveform, which is the equivalent of a digital clock signal, has rise and fall delays which
can be speci ed independently. In addition, the duty cycle and the phase of the waveform are also
variable and can be set by you.
Example SPICE Usage:
a5 1 8 var_clock
.model var_clock d_osc(cntl_array = [-2 -1 1 2]
+
freq_array = [1e3 1e3 10e3 10e3]
CHAPTER 13. BEHAVIORAL MODELING
126
+
+
13.4
duty_cycle = 0.4 init_phase = 180.0
rise_delay = 10e-9 fall_delay=8e-9)
Digital Models
The following digital models are supplied with XSPICE. The descriptions included below consist of an
example model Interface Speci cation File and a description of the model's operation. This is followed by
an example of a simulator-deck placement of the model, including the .MODEL card and the speci cation
of all available parameters. Note that these models have not been nalized at this time.
Some information common to all digital models and/or digital nodes is included here. The following
are general rules which should make working with digital nodes and models more straightforward:
1. All digital nodes are initialized to ZERO at the start of a simulation (i.e., when INIT=TRUE).
This means that a model need not post an explicit value to an output node upon initialization if
its output would normally be a ZERO (although posting such would certainly cause no harm).
13.4.1 Buer
NAME_TABLE:
C_Function_Name:
Spice_Model_Name:
Description:
PORT_TABLE:
Port Name:
Description:
Direction:
Default_Type:
Allowed_Types:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
Description:
cm_d_buffer
d_buffer
"digital one-bit-wide buffer"
in
"input"
in
d
[d]
no
no
out
"output"
out
d
[d]
no
no
rise_delay
"rise delay"
real
1.0e-9
[1.0e-12 -]
no
yes
fall_delay
"fall delay"
real
1.0e-9
[1.0e-12 -]
no
yes
input_load
"input load value (F)"
real
1.0e-12
no
yes
The buer is a single-input, single-output digital buer which produces as output a time-
delayed copy of its input. The delays associated with an output rise and those associated with an
output fall may be dierent. The model also posts an input load value (in farads) based on the
parameter input load. The output of this model does NOT, however, respond to the total loading
it sees on its output; it will always drive the output strongly with the speci ed delays.
Example SPICE Usage:
a6 1 8 buff1
.model buff1 d_buffer(rise_delay = 0.5e-9 fall_delay = 0.3e-9
+
input_load = 0.5e-12)
13.4. DIGITAL MODELS
127
13.4.2 Inverter
NAME_TABLE:
C_Function_Name:
Spice_Model_Name:
Description:
PORT_TABLE:
Port Name:
Description:
Direction:
Default_Type:
Allowed_Types:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
Description:
cm_d_inverter
d_inverter
"digital one-bit-wide inverter"
in
"input"
in
d
[d]
no
no
out
"output"
out
d
[d]
no
no
rise_delay
"rise delay"
real
1.0e-9
[1.0e-12 -]
no
yes
fall_delay
"fall delay"
real
1.0e-9
[1.0e-12 -]
no
yes
input_load
"input load value (F)"
real
1.0e-12
no
yes
The inverter is a single-input, single-output digital inverter which produces as output an
inverted, time- delayed copy of its input.
The delays associated with an output rise and those
associated with an output fall may be speci ed independently. The model also posts an input load
value (in farads) based on the parameter input load. The output of this model does NOT, however,
respond to the total loading it sees on its output; it will always drive the output strongly with the
speci ed delays.
Example SPICE Usage:
a6 1 8 inv1
.model inv1 d_inverter(rise_delay = 0.5e-9 fall_delay = 0.3e-9
+
input_load = 0.5e-12)
13.4.3 And
NAME_TABLE:
C_Function_Name:
Spice_Model_Name:
Description:
PORT_TABLE:
Port Name:
Description:
Direction:
Default_Type:
Allowed_Types:
Vector:
Vector_Bounds:
cm_d_and
d_and
"digital `and' gate"
in
"input"
in
d
[d]
yes
[2 -]
out
"output"
out
d
[d]
no
-
CHAPTER 13. BEHAVIORAL MODELING
128
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
Description:
no
no
rise_delay
"rise delay"
real
1.0e-9
[1.0e-12 -]
no
yes
fall_delay
"fall delay"
real
1.0e-9
[1.0e-12 -]
no
yes
input_load
"input load value (F)"
real
1.0e-12
no
yes
The digital `and' gate is an n-input, single-output `and' gate which produces an active 1
value if, and only if, all of its inputs are also 1 values. If ANY of the inputs is a 0, the output will
also be a 0; if neither of these conditions holds, the output will be unknown. The delays associated
with an output rise and those associated with an output fall may be speci ed independently. The
model also posts an input load value (in farads) based on the parameter input load. The output
of this model does NOT, however, respond to the total loading it sees on its output; it will always
drive the output strongly with the speci ed delays.
Example SPICE Usage:
a6 [1 2] 8 and1
.model and1 d_and(rise_delay = 0.5e-9 fall_delay = 0.3e-9
+
input_load = 0.5e-12)
13.4.4 Nand
NAME_TABLE:
C_Function_Name:
Spice_Model_Name:
Description:
PORT_TABLE:
Port Name:
Description:
Direction:
Default_Type:
Allowed_Types:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
cm_d_nand
d_nand
"digital `nand' gate"
in
"input"
in
d
[d]
yes
[2 -]
no
out
"output"
out
d
[d]
no
no
rise_delay
"rise delay"
real
1.0e-9
[1.0e-12 -]
no
yes
fall_delay
"fall delay"
real
1.0e-9
[1.0e-12 -]
no
yes
input_load
13.4. DIGITAL MODELS
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
Description:
129
"input load value (F)"
real
1.0e-12
no
yes
The digital `nand' gate is an n-input, single-output `nand' gate which produces an active
0 value if and only if all of its inputs are 1 values. If ANY of the inputs is a 0, the output will
be a 1; if neither of these conditions holds, the output will be unknown. The delays associated
with an output rise and those associated with an output fall may be speci ed independently. The
model also posts an input load value (in farads) based on the parameter input load. The output
of this model does NOT, however, respond to the total loading it sees on its output; it will always
drive the output strongly with the speci ed delays.
Example SPICE Usage:
a6 [1 2 3] 8 nand1
.model nand1 d_nand(rise_delay = 0.5e-9 fall_delay = 0.3e-9
+
input_load = 0.5e-12)
13.4.5 Or
NAME_TABLE:
C_Function_Name:
Spice_Model_Name:
Description:
PORT_TABLE:
Port Name:
Description:
Direction:
Default_Type:
Allowed_Types:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
Description:
cm_d_or
d_or
"digital `or' gate"
in
"input"
in
d
[d]
yes
[2 -]
no
out
"output"
out
d
[d]
no
no
rise_delay
"rise delay"
real
1.0e-9
[1.0e-12 -]
no
yes
fall_delay
"fall delay"
real
1.0e-9
[1.0e-12 -]
no
yes
input_load
"input load value (F)"
real
1.0e-12
no
yes
The digital `or' gate is an n-input, single-output `or' gate which produces an active 1
value if at least one of its inputs is a 1 value. The gate produces a 0 value if all inputs are 0; if
neither of these two conditions holds, the output is unknown. The delays associated with an output
rise and those associated with an output fall may be speci ed independently. The model also posts
CHAPTER 13. BEHAVIORAL MODELING
130
an input load value (in farads) based on the parameter input load. The output of this model does
NOT, however, respond to the total loading it sees on its output; it will always drive the output
strongly with the speci ed delays.
Example SPICE Usage:
a6 [1 2 3] 8 or1
.model or1 d_or(rise_delay = 0.5e-9 fall_delay = 0.3e-9
+
input_load = 0.5e-12)
13.4.6 Nor
NAME_TABLE:
C_Function_Name:
Spice_Model_Name:
Description:
PORT_TABLE:
Port Name:
Description:
Direction:
Default_Type:
Allowed_Types:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
Description:
cm_d_nor
d_nor
"digital `nor' gate"
in
"input"
in
d
[d]
yes
[2 -]
no
out
"output"
out
d
[d]
no
no
rise_delay
"rise delay"
real
1.0e-9
[1.0e-12 -]
no
yes
fall_delay
"fall delay"
real
1.0e-9
[1.0e-12 -]
no
yes
input_load
"input load value (F)"
real
1.0e-12
no
yes
The digital `nor' gate is an n-input, single-output `nor' gate which produces an active 0
value if at least one of its inputs is a 1 value. The gate produces a 0 value if all inputs are 0; if
neither of these two conditions holds, the output is unknown. The delays associated with an output
rise and those associated with an output fall may be speci ed independently. The model also posts
an input load value (in farads) based on the parameter input load. The output of this model does
NOT, however, respond to the total loading it sees on its output; it will always drive the output
strongly with the speci ed delays.
Example SPICE Usage:
anor12 [1 2 3 4] 8 nor12
.model nor12 d_or(rise_delay = 0.5e-9 fall_delay = 0.3e-9
+
input_load = 0.5e-12)
13.4.7 Xor
NAME_TABLE:
13.4. DIGITAL MODELS
C_Function_Name:
Spice_Model_Name:
Description:
PORT_TABLE:
Port Name:
Description:
Direction:
Default_Type:
Allowed_Types:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
Description:
131
cm_d_xor
d_xor
"digital exclusive-or gate"
in
"input"
in
d
[d]
yes
[2 -]
no
out
"output"
out
d
[d]
no
no
rise_delay
"rise delay"
real
1.0e-9
[1.0e-12 -]
no
yes
fall_delay
"fall delay"
real
1.0e-9
[1.0e-12 -]
no
yes
input_load
"input load value (F)"
real
1.0e-12
no
yes
The digital `xor' gate is an n-input, single-output `xor' gate which produces an active 1
value if an odd number of its inputs are also 1 values. The delays associated with an output rise
and those associated with an output fall may be speci ed independently.
The model also posts an input load value (in farads) based on the parameter input load.
The
output of this model does NOT, however, respond to the total loading it sees on its output; it
will always drive the output strongly with the speci ed delays.
Note also that to maintain the
technology-independence of the model, any UNKNOWN input, or any oating input causes the
output to also go UNKNOWN.
Example SPICE Usage:
a9 [1 2] 8 xor3
.model xor3 d_xor(rise_delay = 0.5e-9 fall_delay = 0.3e-9
+
input_load = 0.5e-12)
13.4.8 Xnor
NAME_TABLE:
C_Function_Name:
Spice_Model_Name:
Description:
PORT_TABLE:
Port Name:
Description:
Direction:
Default_Type:
Allowed_Types:
Vector:
Vector_Bounds:
cm_d_xnor
d_xnor
"digital exclusive-nor gate"
in
"input"
in
d
[d]
yes
[2 -]
out
"output"
out
d
[d]
no
-
CHAPTER 13. BEHAVIORAL MODELING
132
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
Description:
no
no
rise_delay
"rise delay"
real
1.0e-9
[1.0e-12 -]
no
yes
fall_delay
"fall delay"
real
1.0e-9
[1.0e-12 -]
no
yes
input_load
"input load value (F)"
real
1.0e-12
no
yes
The digital `xnor' gate is an n-input, single-output `xnor' gate which produces an active
0 value if an odd number of its inputs are also 1 values. It produces a 1 output when an even
number of 1 values occurs on its inputs.
The delays associated with an output rise and those
associated with an output fall may be speci ed independently. The model also posts an input load
value (in farads) based on the parameter input load. The output of this model does NOT, however,
respond to the total loading it sees on its output; it will always drive the output strongly with
the speci ed delays.
Note also that to maintain the technology-independence of the model, any
UNKNOWN input, or any oating input causes the output to also go UNKNOWN.
Example SPICE Usage:
a9 [1 2] 8 xnor3
.model xnor3 d_xnor(rise_delay = 0.5e-9 fall_delay = 0.3e-9
+
input_load = 0.5e-12)
13.4.9 Tristate
NAME_TABLE:
C_Function_Name:
Spice_Model_Name:
Description:
PORT_TABLE:
Port Name:
Description:
Direction:
Default_Type:
Allowed_Types:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
cm_d_tristate
d_tristate
"digital tristate buffer"
in
"input"
in
d
[d]
no
no
enable
"enable"
in
d
[d]
no
no
delay
"delay"
real
1.0e-9
[1.0e-12 -]
no
yes
out
"output"
out
d
[d]
no
no
13.4. DIGITAL MODELS
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
Description:
133
input_load
"input load value (F)"
real
1.0e-12
no
yes
enable_load
"enable load value (F)"
real
1.0e-12
no
yes
The digital tristate is a simple tristate gate which can be con gured to allow for open-
collector behavior, as well as standard tristate behavior. The state seen on the input line is re ected
in the output. The state seen on the enable line determines the strength of the output. Thus, a
ONE forces the output to its state with a STRONG strength. A ZERO forces the output to go to a
HI_IMPEDANCE strength. The delays associated with an output state or strength change cannot
be speci ed independently, nor may they be speci ed independently for rise or fall conditions; other
gate models may be used to provide such delays if needed. The model posts input and enable load
values (in farads) based on the parameters input load and enable.The output of this model does
NOT, however, respond to the total loading it sees on its output; it will always drive the output
with the speci ed delay. Note also that to maintain the technology-independence of the model, any
UNKNOWN input, or any oating input causes the output to also go UNKNOWN. Likewise, any
UNKNOWN input on the enable line causes the output to go to an UNDETERMINED strength
value.
Example SPICE Usage:
a9 1 2 8 tri7
.model tri7 d_tristate(delay = 0.5e-9 input_load = 0.5e-12
+
enable_load = 0.5e-12)
13.4.10 Pullup
NAME_TABLE:
C_Function_Name:
Spice_Model_Name:
Description:
PORT_TABLE:
Port Name:
Description:
Direction:
Default_Type:
Allowed_Types:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
cm_d_pullup
d_pullup
"digital pullup resistor"
out
"output"
out
d
[d]
no
no
load
"load value (F)"
real
1.0e-12
no
CHAPTER 13. BEHAVIORAL MODELING
134
Vector_Bounds:
Null_Allowed:
Description:
yes
The digital pullup resistor is a device which emulates the behavior of an analog resistance
value tied to a high voltage level. The pullup may be used in conjunction with tristate buers to
provide open-collector wired or constructs, or any other logical constructs which rely on a resistive
pullup common to many tristated output devices. The model posts an input load value (in farads)
based on the parameters load.
Example SPICE Usage:
a2 9 pullup1
.model pullup1 d_pullup(load = 20.0e-12)
13.4.11 Pulldown
NAME_TABLE:
C_Function_Name:
Spice_Model_Name:
Description:
PORT_TABLE:
Port Name:
Description:
Direction:
Default_Type:
Allowed_Types:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
Description:
cm_d_pulldown
d_pulldown
"digital pulldown resistor"
out
"output"
out
d
[d]
no
no
load
"load value (F)"
real
1.0e-12
no
yes
The digital pulldown resistor is a device which emulates the behavior of an analog resis-
tance value tied to a low voltage level.
The pulldown may be used in conjunction with tristate
buers to provide open-collector wired or constructs, or any other logical constructs which rely
on a resistive pulldown common to many tristated output devices. The model posts an input load
value (in farads) based on the parameters load.
Example SPICE Usage:
a4 9 pulldown1
.model pulldown1 d_pulldown(load = 20.0e-12)
13.4.12 D Flip Flop
NAME_TABLE:
C_Function_Name:
Spice_Model_Name:
Description:
PORT_TABLE:
Port Name:
Description:
Direction:
Default_Type:
Allowed_Types:
cm_d_dff
d_dff
"digital d-type flip flop"
data
"input data"
in
d
[d]
clk
"clock"
in
d
[d]
13.4. DIGITAL MODELS
Vector:
Vector_Bounds:
Null_Allowed:
PORT_TABLE:
Port Name:
Description:
Direction:
Default_Type:
Allowed_Types:
Vector:
Vector_Bounds:
Null_Allowed:
PORT_TABLE:
Port Name:
Description:
Direction:
Default_Type:
Allowed_Types:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector.Bounds:
Null_Allowed:
PARAMETER_TABLE:
135
no
no
no
no
set
"asynch. set"
in
d
[d]
no
yes
reset
"asynch. reset"
in
d
[d]
no
yes
out
"data output"
out
d
[d]
no
yes
Nout
"inverted data output"
out
d
[d]
no
yes
clk_delay
"delay from clk"
real
1.0e-9
[1.0e-12 -]
no
yes
set_delay
"delay from set"
real
1.0e-9
[1.0e-12 -]
no
yes
reset_delay
"delay from reset"
real
1.0
[1.0e-12 -]
no
yes
ic
"output initial state"
int
0
[0 2]
no
yes
data_load
"data load value (F)"
real
1.0e-12
no
yes
clk_load
"clk load value (F)"
real
1.0e-12
no
yes
set_load
"set load value (F)"
real
1.0e-12
no
yes
reset_load
"reset load (F)"
real
1.0e-12
no
yes
CHAPTER 13. BEHAVIORAL MODELING
136
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
Description:
rise_delay
"rise delay"
real
1.0e-9
[1.0e-12 -]
no
yes
fall_delay
"fall delay"
real
1.0e-9
[1.0e-12 -]
no
yes
The digital d-type ip op is a one-bit, edge-triggered storage element which will store data
whenever the clk input line transitions from low to high (ZERO to ONE). In addition, asynchronous
set and reset signals exist, and each of the three methods of changing the stored output of the d_d
have separate load values and delays associated with them. Additionally, you may specify separate
rise and fall delay values that are added to those speci ed for the input lines; these allow for more
faithful reproduction of the output characteristics of dierent IC fabrication technologies.
Note that any UNKNOWN input on the set or reset lines immediately results in an UNKNOWN
output.
Example SPICE Usage:
a7 1 2 3 4 5 6 flop1
.model flop1 d_dff(clk_delay = 13.0e-9 set_delay = 25.0e-9
+
reset_delay = 27.0e-9 ic = 2 rise_delay = 10.0e-9
+
fall_delay = 3e-9)
13.4.13 JK Flip Flop
NAME_TABLE:
C_Function_Name:
Spice_Model_Name:
Description:
PORT_TABLE:
Port Name:
Description:
Direction:
Default_Type:
Allowed_Types:
Vector:
Vector_Bounds:
Null_Allowed:
PORT_TABLE:
Port Name:
Description:
Direction:
Default_Type:
Allowed_Types:
Vector:
Vector_Bounds:
Null_Allowed:
PORT_TABLE:
Port Name:
Description:
Direction:
Default_Type:
Allowed_Types:
Vector:
Vector_Bounds:
Null_Allowed:
PORT_TABLE:
Port Name:
cm_d_jkff
d_jkff
"digital jk-type flip flop"
j
"j input"
in
d
[d]
yes
[2 -]
no
k
"k input"
in
d
[d]
yes
j
no
clk
"clock"
in
d
[d]
no
no
set
"asynchronous set"
in
d
[d]
no
yes
reset
"asynchronous reset"
in
d
[d]
no
yes
out
Nout
13.4. DIGITAL MODELS
Description:
Direction:
Default_Type:
Allowed_Types:
Vector:
Vector_Bounds
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
Description:
137
"data output"
out
d
[d]
no
yes
"inverted data output"
out
d
[d]
no
yes
clk_delay
"delay from clk"
real
1.0e-9
[1.0e-12 -]
no
yes
set_delay
"delay from set"
real
1.0e-9
[1.0e-12 -]
no
yes
reset_delay
"delay from reset"
real
1.0
[1.0e-12 -]
no
yes
ic
"output initial state"
int
0
[0 2]
no
yes
jk_load
clk_load
"j,k load values (F)" "clk load value (F)"
real
real
1.0e-12
1.0e-12
no
no
yes
yes
set_load
"set load value (F)"
real
1.0e-12
no
yes
reset_load
"reset load (F)"
real
1.0e-12
no
yes
rise_delay
"rise delay"
real
1.0e-9
[1.0e-12 -]
no
yes
fall_delay
"fall delay"
real
1.0e-9
[1.0e-12 -]
no
yes
The digital jk-type ip op is a one-bit, edge-triggered storage element which will store
data whenever the clk input line transitions from low to high (ZERO to ONE). In addition, asynchronous set and reset signals exist, and each of the three methods of changing the stored output
of the d_jk have separate load values and delays associated with them. Additionally, you may
specify separate rise and fall delay values that are added to those speci ed for the input lines;
these allow for more faithful reproduction of the output characteristics of dierent IC fabrication
CHAPTER 13. BEHAVIORAL MODELING
138
technologies.
Note that any UNKNOWN inputs other than j or k cause the output to go UNKNOWN automatically.
Example SPICE Usage:
a8 1 2 3 4 5 6 7 flop2
.model flop2 d_jkff(clk_delay = 13.0e-9 set_delay = 25.0e-9
+
reset_delay = 27.0e-9 ic = 2 rise_delay = 10.0e-9
+
fall_delay = 3e-9)
13.4.14 Toggle Flip Flop
NAME_TABLE:
C_Function_Name:
Spice_Model_Name:
Description:
PORT_TABLE:
Port Name:
Description:
Direction:
Default_Type:
Allowed_Types:
Vector:
Vector_Bounds:
Null_Allowed:
PORT_TABLE:
Port Name:
Description:
Direction:
Default_Type:
Allowed_Types:
Vector:
Vector_Bounds:
Null_Allowed:
PORT.TABLE:
Port Name:
Description:
Direction:
Default_Type:
Allowed_Types:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
cm_d_tff
d_tff
"digital toggle flip flop"
t
"toggle input"
in
d
[d]
yes
[2 -]
no
clk
"clock"
in
d
[d]
no
no
set
"set"
in
d
[d]
no
yes
reset
"reset"
in
d
[d]
no
yes
out
"data output"
out
d
[d]
no
yes
Nout
"inverted data output"
out
d
[d]
no
yes
clk_delay
"delay from clk"
real
1.0e-9
[1.0e-12 -]
no
yes
set_delay
"delay from set"
real
1.0e-9
[1.0e-12 -]
no
yes
reset_delay
"delay from reset"
real
1.0
[1.0e-12 -]
no
ic
"output initial state"
int
0
[0 2]
no
13.4. DIGITAL MODELS
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default.Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
Description:
139
yes
yes
t_load
clk_load
"toggle load value (F)" "clk load value (F)"
real
real
1.0e-12
1.0e-12
no
no
yes
yes
set_load
"set load value (F)"
real
1.0e-12
no
yes
reset_load
"reset load (F)"
real
1.0e-12
no
yes
rise_delay
"rise delay"
real
1.0e-9
[1.0e-12 -]
no
yes
fall_delay
"fall delay"
real
1.0e-9
[1.0e-12 -]
no
yes
The digital toggle-type ip op is a one-bit, edge-triggered storage element which will
toggle its current state whenever the clk input line transitions from low to high (ZERO to ONE).
In addition, asynchronous set and reset signals exist, and each of the three methods of changing
the stored output of the d_t have separate load values and delays associated with them. Additionally, you may specify separate rise and fall delay values that are added to those speci ed for
the input lines; these allow for more faithful reproduction of the output characteristics of dierent
IC fabrication technologies.
Note that any UNKNOWN inputs other than t immediately cause the output to go UNKNOWN.
Example SPICE Usage:
a8 2 12 4 5 6 3 flop3
.model flop3 d_tff(clk_delay = 13.0e-9 set_delay = 25.0e-9
+
reset_delay = 27.0e-9 ic = 2 rise_delay = 10.0e-9
+
fall_delay = 3e-9 t_load = 0.2e-12)
13.4.15 Set-Reset Flip Flop
NAME_TABLE:
C_Function_Name:
Spice_Model_Name:
Description:
PORT_TABLE:
Port Name:
Description:
Direction:
Default_Type:
Allowed_Types:
Vector:
Vector_Bounds:
cm_d_srff
d_srff
"digital set-reset flip flop"
s
"set input"
in
d
[d]
no
-
r
"reset input"
in
d
[d]
no
-
CHAPTER 13. BEHAVIORAL MODELING
140
Null_Allowed:
PORT_TABLE:
Port Name:
Description:
Direction:
Default_Type:
Allowed_Types:
Vector:
Vector_Bounds:
Null_Allowed:
PORT_TABLE:
Port Name:
Description:
Direction:
Default_Type:
Allowed_Types:
Vector:
Vector_Bounds:
Null_Allowed:
PORT_TABLE:
Port Name:
Description:
Direction:
Default_Type:
Allowed_Types:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
no
no
clk
"clock"
in
d
[d]
no
no
set
"asynchronous set"
in
d
[d]
no
yes
reset
"asynchronous reset"
in
d
[d]
no
yes
out
"data output"
out
d
[d]
no
yes
Nout
"inverted data output"
out
d
[d]
no
yes
clk_delay
"delay from clk"
real
1.0e-9
[1.0e-12 -]
no
yes
set_delay
"delay from set"
real
1.0e-9
[1.0e-12 -]
no
yes
reset_delay
"delay from reset"
real
1.0e-9
[1.0e-12 -]
no
yes
ic
"output initial state"
int
0
[0 2]
no
yes
sr_load
clk_load
"set/reset loads (F)" "clk load value (F)"
real
real
1.0e-12
1.0e-12
no
no
yes
yes
set_load
"set load value (F)"
reset_load
"reset load (F)"
13.4. DIGITAL MODELS
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
Description:
141
real
1.0e-12
no
yes
real
1.0e-12
no
yes
rise_delay
"rise delay"
real
1.0e-9
[1.0e-12 -]
no
yes
fall_delay
"fall delay"
real
1.0e-9
[1.0e-12 -]
no
yes
The digital sr-type ip op is a one-bit, edge-triggered storage element which will store
data whenever the clk input line transitions from low to high (ZERO to ONE). The value stored
(i.e., the out value) will depend on the s and r input pin values, and will be:
out=ONE
if
out=ZERO
if
out=previous value if
out=UNKNOWN
if
s=ONE and r=ZERO;
s=ZERO and r=ONE;
s=ZERO and r=ZERO;
s=ONE and r=ONE;
In addition, asynchronous set and reset signals exist, and each of the three methods of changing the
stored output of the d_sr have separate load values and delays associated with them. You may also
specify separate rise and fall delay values that are added to those speci ed for the input lines; these allow
for more faithful reproduction of the output characteristics of dierent IC fabrication technologies.
Note that any UNKNOWN inputs other than s and r immediately cause the output to go UNKNOWN.
Example SPICE Usage:
a8 2 12 4 5 6 3 14 flop7
.model flop7 d_srff(clk_delay = 13.0e-9 set_delay = 25.0e-9
+
reset_delay = 27.0e-9 ic = 2 rise_delay = 10.0e-9
+
fall_delay = 3e-9)
13.4.16 D Latch
NAME_TABLE:
C_Function_Name:
Spice_Model_Name:
Description:
PORT_TABLE:
Port Name:
Description:
Direction:
Default_Type:
Allowed_Types:
Vector:
Vector_Bounds:
Null_Allowed:
PORT_TABLE:
Port Name:
Description:
Direction:
Default_Type:
Allowed_Types:
Vector:
Vector_Bounds:
cm_d_dlatch
d_dlatch
"digital d-type latch"
data
"input data"
in
d
[d]
no
no
enable
"enable input"
in
d
[d]
no
no
set
"set"
in
d
[d]
no
-
reset
"reset"
in
d
[d]
no
-
CHAPTER 13. BEHAVIORAL MODELING
142
Null_Allowed:
PORT_TABLE:
Port Name:
Description:
Direction:
Default_Type:
Allowed_Types:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
yes
yes
out
"data output"
out
d
[d]
no
no
Nout
"inverter data output"
out
d
[d]
no
no
data_delay
"delay from data"
real
1.0e-9
[1.0e-12 -]
no
yes
enable_delay
"delay from enable"
real
1.0e-9
[1.0e-12 -]
no
yes
set_delay
"delay from SET"
real
1.0e-9
[1.0e-12 -]
no
yes
reset_delay
"delay from RESET"
real
1.0e-9
[1.0e-12 -]
no
yes
ic
"output initial state"
boolean
0
no
yes
data_load
"data load (F)"
real
1.0e-12
no
yes
enable_load
"enable load value (F)"
real
1.0e-12
no
yes
set_load
"set load value (F)"
real
1.0e-12
no
yes
reset_load
"reset load (F)"
real
1.0e-12
no
yes
rise_delay
"rise delay"
fall_delay
"fall delay"
13.4. DIGITAL MODELS
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
Description:
143
real
1.0e-9
[1.0e-12 -]
no
yes
real
1.0e-9
[1.0e-12 -]
no
yes
The digital d-type latch is a one-bit, level-sensitive storage element which will output the
value on the data line whenever the enable input line is high (ONE). The value on the data line is
stored (i.e., held on the out line) whenever the enable line is low (ZERO).
In addition, asynchronous set and reset signals exist, and each of the four methods of changing the
stored output of the d_dlatch (i.e., data changing with enable=ONE, enable changing to ONE from
ZERO with a new value on data, raising set and raising reset) have separate delays associated with
them. You may also specify separate rise and fall delay values that are added to those speci ed for
the input lines; these allow for more faithful reproduction of the output characteristics of dierent
IC fabrication technologies.
Note that any UNKNOWN inputs other than on the data line when enable=ZERO immediately
cause the output to go UNKNOWN.
Example SPICE Usage:
a4 12 4 5 6 3 14 latch1
.model latch1 d_dlatch(data_delay = 13.0e-9 enable_delay = 22.0e-9
+
set_delay = 25.0e-9
+
reset_delay = 27.0e-9 ic = 2
+
rise_delay = 10.0e-9 fall_delay = 3e-9)
13.4.17 Set-Reset Latch
NAME_TABLE:
C_Function_Name:
Spice_Model_Name:
Description:
PORT_TABLE:
Port Name:
Description:
Direction:
Default_Type:
Allowed_Types:
Vector:
Vector_Bounds:
Null_Allowed:
PORT_TABLE:
Port Name:
Description:
Direction:
Default_Type:
Allowed_Types:
Vector:
Vector_Bounds:
Null_Allowed:
PORT_TABLE:
Port Name:
Description:
Direction:
Default_Type:
Allowed_Types:
Vector:
Vector_Bounds:
Null_Allowed:
cm_d_srlatch
d_srlatch
"digital sr-type latch"
s
"set"
in
d
[d]
yes
[2 -]
no
r
"reset"
in
d
[d]
yes
r
no
enable
"enable"
in
d
[d]
no
no
set
"set"
in
d
[d]
no
yes
reset
"reset"
in
d
[d]
no
yes
CHAPTER 13. BEHAVIORAL MODELING
144
PORT_TABLE:
Port Name:
Description:
Direction:
Default_Type:
Allowed_Types:
Vector: no no
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
out
"data output"
out
d
[d]
Nout
"inverted data output"
out
d
[d]
no
no
sr_delay
"delay from s or r input change"
real
1.0e-9
[1.0e-12 -]
no
yes
enable_delay
"delay from enable"
real
1.0e-9
[1.0e-12 -]
no
yes
set_delay
"delay from SET"
real
1.0e-9
[1.0e-12 -]
no
yes
reset_delay
"delay from RESET"
real
1.0e-9
[1.0e-12 -]
no
yes
ic
"output initial state"
boolean
0
no
yes
sr_load
enable_load
"s & r input loads (F)" "enable load value (F)"
real
real
1.0e-12
1.0e-12
no
no
yes
yes
set_load
"set load value (F)"
real
1.0e-12
no
yes
reset_load
"reset load (F)"
real
1.0e-12
no
yes
rise_delay
"rise delay"
real
fall_delay
"fall delay"
real
13.4. DIGITAL MODELS
145
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
Description:
1.0e-9
[1.0e-12 -]
no
yes
1.0e-9
[1.0e-12 -]
no
yes
The digital sr-type latch is a one-bit, level-sensitive storage element which will output the
value dictated by the state of the s and r pins whenever the enable input line is high (ONE). This
value is stored (i.e., held on the out line) whenever the enable line is low (ZERO). The particular
value chosen is as shown below:
s=ZERO,
s=ZERO,
s=ONE,
s=ONE,
r=ZERO
r=ONE
r=ZERO
r=ONE
=>
=>
=>
=>
out=current value (i.e., not change in output)
out=ZERO
out=ONE
out=UNKNOWN
Asynchronous set and reset signals exist, and each of the four methods of changing the stored output of
the d srlatch (i.e., s/r combination changing with enable=ONE, enable changing to ONE from ZERO with
an output-changing combination of s and r, raising set and raising reset) have separate delays associated
with them. You may also specify separate rise and fall delay values that are added to those speci ed for
the input lines; these allow for more faithful reproduction of the output characteristics of dierent IC
fabrication technologies.
Note that any UNKNOWN inputs other than on the s and r lines when enable=ZERO immediately
cause the output to go UNKNOWN.
Example SPICE Usage:
a4 12 4 5 6 3 14 16 latch2
.model latch2 d_srlatch(sr_delay = 13.0e-9 enable_delay = 22.0e-9
+
set_delay = 25.0e-9
+
reset_delay = 27.0e-9 ic = 2
+
rise_delay = 10.0e-9 fall_delay = 3e-9)
13.4.18 State Machine
NAME_TABLE:
C_Function_Name:
Spice_Model_Name:
Description:
PORT_TABLE:
Port Name:
Description:
Direction:
Default_Type:
Allowed_Types:
Vector:
Vector_Bounds:
Null_Allowed:
PORT_TABLE:
Port Name:
Description:
Direction:
Default_Type:
Allowed_Types:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
cm_d_state
d_state
"digital state machine"
in
"input"
in
d
[d]
yes
[1 -]
yes
clk
"clock"
in
d
[d]
no
no
reset
"reset"
in
d
[d]
no
yes
out
"output"
out
d
[d]
yes
[1 -]
no
clk_delay
"delay from CLK"
real
reset_delay
"delay from RESET"
real
CHAPTER 13. BEHAVIORAL MODELING
146
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
Description:
1.0e-9
1.0e-9
[1.0e-12 -]
[1.0e-12 -]
no
no
yes
yes
Parameter_Name:
state_file
"state transition specification file name"
string
"state.txt"
no
no
reset_state
"default state on RESET & at DC"
int
0
no
no
input_load
"input loading capacitance (F)"
real
1.0e-12
no
yes
clk_load
"clock loading capacitance (F)"
real
1.0e-12
no
yes
reset_load
"reset loading capacitance (F)"
real
1.0e-12
no
yes
The digital state machine provides for straightforward descriptions of clocked combina-
tional logic blocks with a variable number of inputs and outputs and with an unlimited number of
possible states. The model can be con gured to behave as virtually any type of counter or clocked
combinational logic block and can be used to replace very large digital circuit schematics with an
identically functional but faster representation.
The d state model is con gured through the use of a state de nition le (state.in) which resides in
a directory of your choosing. The le de nes all states to be understood by the model, plus input
bit combinations which trigger changes in state. An example state.in le is shown below:
13.4. DIGITAL MODELS
147
----------- begin file ------------* This is an example state.in file. This file
* defines a simple 2-bit counter with one input. The
* value of this input determines whether the counter counts
* up (in = 1) or down (in = 0).
0 0s 0s 0 -> 3
1 -> 1
1 0s 1z 0 -> 0
1 -> 2
2 1z 0s 0 -> 1
1 -> 3
3 1z 1z 0 -> 2
3 1z 1z 1 -> 0
------------------ end file --------------Several attributes of the above le structure should be noted. First, ALL LINES IN THE FILE MUST
BE ONE OF FOUR TYPES. These are:
1. A comment, beginning with a * in the rst column.
2. A header line, which is a complete description of the current state, the outputs corresponding to that
state, an input value, and the state that the model willassume should that input be encountered.
The rst line of a state de nition must ALWAYS be a header line.
3. A continuation line, which is a partial description of a state, consisting of an input value and the
state that the model will assume should that input be encountered. Note that continuation lines
may only be used after the initial header line de nition for a state.
4. A line containing nothing but whitespace (space, formfeed, newline, carriage return, tab, vertical
tab).
A line which is not one of the above will cause a le-loading error.
Note that in the example shown,
whitespace (any combination of blanks, tabs, commas) is used to separate values, and that the character
"->" is used to underline the state transition implied by the input preceding it. This particular character
is not critical in of itself, and can be replaced with any other character or non-broken combination of
characters that you prefer (e.g. ==>, >>, :, resolves_to, etc.)
The order of the output and input bits in the le is important; the rst column is always interpreted
to refer to the zeroth bit of input and output. Thus, in the le above, the output from state 1 sets
out[0] to 0s, and out[1] to 1z.
The state numbers need not be in any particular order, but a state de nition (which consists of
the sum total of all lines which de ne the state, its outputs, and all methods by which a state can be
exited) must be made on contiguous line numbers; a state de nition cannot be broken into sub-blocks
and distributed randomly throughout the le. On the other hand, the state de nition can be broken up
by as many comment lines as you desire.
Header les may be used throughout the state.in le, and continuation lines can be discarded completely if you so choose: continuation lines are primarily provided as a convenience.
Example SPICE Usage:
a4 [2 3 4 5] 1 12 [22 23 24 25 26 27 28 29] state1
.model state1 d_state(clk_delay = 13.0e-9 reset_delay = 27.0e-9
+
state_file = newstate.txt reset_state = 2)
13.4.19 Frequency Divider
NAME_TABLE:
C_Function_Name:
Spice_Model_Name:
Description:
PORT_TABLE:
Port Name:
Description:
cm_d_fdiv
d_fdiv
"digital frequency divider"
freq_in
"frequency input"
freq_out
"frequency output"
CHAPTER 13. BEHAVIORAL MODELING
148
Direction:
Default_Type:
Allowed_Types:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
Description:
in
d
[d]
no
no
out
d
[d]
no
no
div_factor
"divide factor"
int
2
[1 -]
no
yes
high_cycles
"# of cycles for high out"
int
1
[1 div_factor-1]
no
yes
i_count
"divider initial count value"
int
0
no
yes
rise_delay
"rise delay"
real
1.0e-9
[1.0e-12 -]
yes
in
yes
fall_delay
"fall delay"
real
1.0e-9
[1.0e-12 -]
yes
in
yes
freq_in_load
"freq_in load value (F)"
real
1.0e-12
no
yes
The digital frequency divider is a programmable step-down divider which accepts an ar-
bitrary divisor (div_factor), a duty-cycle term (high_cycles), and an initial count value (i_count).
The generated output is synchronized to the rising edges of the input signal. Rise delay and fall
delay on the outputs may also be speci ed independently.
Example SPICE Usage:
a4 3 7 divider
.model divider d_fdiv(div_factor = 5 high_cycles = 3
+
i_count = 4 rise_delay = 23e-9
+
fall_delay = 9e-9)
13.4.20 RAM
NAME_TABLE:
C_Function_Name:
Spice_Model_Name:
cm_d_ram
d_ram
13.4. DIGITAL MODELS
Description:
PORT_TABLE:
Port Name:
Description:
Direction:
Default_Type:
Allowed_Types:
Vector:
Vector_Bounds:
Null_Allowed:
PORT_TABLE:
Port Name:
Description:
Direction:
Default_Type:
Allowed_Types:
Vector:
Vector_Bounds:
Null_Allowed:
PORT_TABLE:
Port Name:
Description:
Direction:
Default_Type:
Allowed_Types:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
149
"digital random-access memory"
data_in
"data input line(s)"
in
d
[d]
yes
[1 -]
no
data_out
"data output line(s)"
out
d
[d]
yes
data_in
no
address
write_en
"address input line(s)" "write enable line"
in
in
d
d
[d]
[d]
yes
no
[1 -]
no
no
select
"chip select line(s)"
in
d
[d]
yes
[1 16]
no
select_value
"decimal active value for select line comparison"
int
1
[0 32767]
no
yes
ic
"initial bit state @ dc"
int
2
[0 2]
no
yes
read_delay
"read delay from address/select/write.en active"
real
100.0e-9
[1.0e-12 -]
no
yes
data_load
address_load
"data_in load value (F)" "addr. load value (F)"
CHAPTER 13. BEHAVIORAL MODELING
150
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
Description:
real
1.0e-12
no
yes
real
1.0e-12
no
yes
select_load
"select load value (F)"
real
1.0e-12
no
yes
enable_load
"enable line load value (F)"
real
1.0e-12
no
yes
The digital RAM is an M-wide, N-deep random access memory element with programmable
select lines, tristated data out lines, and a single write/~read line. The width of the RAM words
(M) is set through the use of the word width parameter. The depth of the RAM (N) is set by the
number of address lines input to the device. The value of N is related to the number of address
input lines (P) by the following equation:
2P = N
There is no reset line into the device.
However, an initial value for all bits may be speci ed by
setting the ic parameter to either 0 or 1. In reading a word from the ram, the read delay value
is invoked, and output will not appear until that delay has been satis ed. Separate rise and fall
delays are not supported for this device.
Note that UNKNOWN inputs on the address lines are not allowed during a write. In the event
that an address line does indeed go unknown during a write, THE ENTIRE CONTENTS OF THE
RAM WILL BE SET TO UNKNOWN. This is in contrast to the data in lines being set to unknown
during a write; in that case, only the selected word will be corrupted, and this is corrected once the
data lines settle back to a known value. Note that protection is added to the write en line such that
extended UNKNOWN values on that line are interpreted as ZERO values. This is the equivalent
of a read operation and will not corrupt the contents of the RAM. A similar mechanism exists for
the select lines. If they are unknown, then it is assumed that the chip is not selected.
Detailed timing-checking routines are not provided in this model, other than for the enable delay
and select delay restrictions on read operations. You are advised, therefore, to carefully check the
timing into and out of the RAM for correct read and write cycle times, setup and hold times, etc.
for the particular device they are attempting to model.
Example SPICE Usage:
a4 [3 4 5 6] [3 4 5 6] [12 13 14 15 16 17 18 19] 30 [22 23 24] ram2
.model ram2 d_ram(select_value = 2 ic = 2 read_delay = 80e-9)
13.4.21 Digital Source
NAME_TABLE:
C_Function_Name:
Spice_Model_Name:
Description:
cm_d_source
d_source
"digital signal source"
13.4. DIGITAL MODELS
PORT_TABLE:
Port Name:
Description:
Direction:
Default_Type:
Allowed_Types:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
PARAMETER_TABLE:
Parameter_Name:
Description:
Data_Type:
Default_Value:
Limits:
Vector:
Vector_Bounds:
Null_Allowed:
Description:
151
out
"output"
out
d
[d]
yes
no
input_file
"digital input vector filename"
string
"source.txt"
no
no
input_load
"input loading capacitance (F)"
real
1.0e-12
no
no
The digital source provides for straightforward descriptions of digital signal vectors in a
tabular format. The model reads input from the input le and, at the times speci ed in the le,
generates the inputs along with the strengths listed.
The
format of the input le is as shown below. Note that comment lines are delineated through the use
of a single * character in the rst column of a line. This is similar to the way the SPICE program
handles comments.
* T
* i
* m
* e
*
0.0000
1.234e-9
1.376e-9
2.5e-7
2.5006e-7
5.0e-7
c
l
o
c
k
Uu
0s
0s
1s
1s
0s
n
o
d
e
a
Uu
1s
0s
0s
1s
1s
n
o
d
e
b
Us
1s
1s
1s
1s
1s
n . . .
o . . .
d . . .
e . . .
c . . .
Uu . . .
0z . . .
0z . . .
0z . . .
0z . . .
0z . . .
Note that in the example shown, whitespace (any combination of blanks, tabs, commas) is used to separate
the time and strength/state tokens.
always interpreted to mean time.
out[N-2] output nodes.
The order of the input columns is important; the rst column is
The second through the N'th columns map to the out[0] through
A non-commented line which does not contain enough tokens to completely
de ne all outputs for the digital source will cause an error. Also, time values must increase monotonically
or an error will result in reading the source le.
Errors will also occur if a line exists in source.txt which is neither a comment nor vector line. The
only exception to this is in the case of a line that is completely blank; this is treated as a comment (note
that such lines often occur at the end of text within a le; ignoring these in particular prevents nuisance
errors on the part of the simulator).
Example SPICE Usage:
CHAPTER 13. BEHAVIORAL MODELING
152
a3 [2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17] input_vector
.model input_vector d_source(input_file = source_simple.text)
13.5
Prede ned Node Types
The following prewritten node types are included with the XSPICE simulator.
These, along with the
digital node type built into the simulator, should provide you not only with valuable event-driven modeling
capabilities, but also with examples to use for guidance in creating new UDN types.
13.5.1 Real Node Type
The real node type provides for event-driven simulation with double-precision oating point data. This
type is useful for evaluating sampled-data lters and systems. The type implements all optional functions
for User-De ned Nodes, including inversion and node resolution. For inversion, the sign of the value is
reversed. For node resolution, the resultant value at a node is the sum of all values output to that node.
13.5.2 Int Node Type
The int node type provides for event-driven simulation with integer data.
This type is useful for
evaluating roundo error eects in sampled-data systems. The type implements all optional functions
for User-De ned Nodes, including inversion and node resolution. For inversion, the sign of the integer
value is reversed. For node resolution, the resultant value at a node is the sum of all values output to
that node.
Chapter 14
Verilog A Device models
14.1
Introduction
To be written
14.2
adms
To compile Verilog-AMS compact models into ngspice-ready C models the the program admsXml is
required. Details of this software are described in adms home page.
14.3
How to generate a *.va model for ngspice
To be written
14.4
How to integrate a *.va model into ngspice
14.4.1 Adding admsXml to your build environment
To facilitate the installation of adms, a source code package has been assembled for use with ngspice,
available as a zip le for download.
It is based on adms source code from the subversion repository
downloaded on August 1st, 2010, and has been slightly modi ed (see ChangeLog).
Under OS LINUX (tested with SUSE 11.2, 64 bit) you may expand the zip le and run
followed by 'make' and 'make
install'.
./autogen_lin.sh,
Under OS CYGWIN (tested with actual CYGWIN on MS Windows 7, 64 bit), please use
followed by 'make' and 'make
install'.
./autogen_cyg.sh,
Under OS MINGW, a direct compilation would require the additional installation of perl module
XML-LibXML which is not as straighforward as it should be. However you may start with a CYGWIN
compile as decribed above.
If you then go to your MSYS window, cd to the adms top directory and
start
you will obtain admsXml.exe, copied to MSYS /bin, and you are ready to
./mingw-compile.sh,
go. To facilitate installation under MS Windows, a
admsXml.exe
zipped binary is available. Just copy it
to MSYS /bin directory and start working on your verilog models.
A short test of a successful installation is:
$ admsXml -v
$ [usage..] release name="admsXml" version="2.3.0" date="Aug 4 2010" time="10:24:18"
Compilation of admsXml with MS Visual Studio is not possible, because the source code has variable
declarations not only at the top of a block, but deliberately also in the following lines. This is o.k. by
the C99 standard, but not supported by MS Visual Studio.
153
154
CHAPTER 14. VERILOG A DEVICE MODELS
Chapter 15
Mixed-Level Simulation (ngspice with
TCAD)
15.1
Cider
Ngspice implements mixed-level simulation through the merging of its code with CIDER (details see
chapt. 29).
CIDER is a mixed-level circuit and device simulator that provides a direct link between technology
parameters and circuit performance.
A mixed-level circuit and device simulator can provide greater
simulation accuracy than a stand-alone circuit or device simulator by numerically modeling the critical
devices in a circuit. Compact models can be used for noncritical devices.
CIDER couples the latest version of SPICE3 (version 3F.2) [JOHN92] to a internal C-based device
simulator, DSIM. SPICE3 provides circuit analyses, compact models for semiconductor devices, and an
interactive user interface. DSIM provides accurate, one- and two-dimensional numerical device models
based on the solution of Poisson's equation, and the electron and hole current-continuity equations. DSIM
incorporates many of the same basic physical models found in the the Stanford two-dimensional device
imulator PISCES [PINT85].
Input to CIDER consists of a SPICE-like description of the c ircuit and
its compact models, and PISCES-like descriptions of the structures of numerically modeled devices. As
a result, CIDER should seem familiar to designers already accustome to these two tools. For example,
SPICE3F.2 input les should run without modi cation, producing identical results.
CIDER is based on the mixed-level circuit and device simulator CODECS [MAYA88] and is a replacement for this program. The basic algorithms of the two programs are the same. Some of the dierences
between CIDER and CODECS are described below. The CIDER input format has greater exibility and
allows increased access to physical model parameters. New physical models have been added to allow
simulation of state-of-the-art devices. These include transverse eld mobility degradation [GATE90] that
is important in scaled-down MOSFETs and a polysilicon model for poly-emitter bipolar transistors. Temperature dependence has been included for most physical models over the range from -50°C to 150°C. The
numerical models can be used to simulate all the basic types of semiconductor devices: resistors, MOS
capacitors, diodes, BJTs, JFETs and MOSFETs. BJTs and JFETs can be modeled with or without a
substrate contact. Support has been added for the management of device internal states. Post-processing
of device states can be performed using the NUTMEG user interface of SPICE3. Previously computed
states can be loaded into the program to provide accurate initial guesses for subssequent analyses. Finally, numerous small bugs have been discovered and xed, and the program has been ported to a wider
variety of computing platforms.
Berkeley tradition calls for the naming of new versions of programs by a xing a (number, letter,
number) triplet to the end of the program name. Under this scheme, CIDER should instead be named
CODECS2A.l.
However, tradition has been broken in this case because major incompatibilities exist
between the two programs and because it was observed that the acronym CODECS is already used in
the analog design community to refer to coder-decoder circuits.
Details of the basic semiconductor equations and the physical models used by CIDER are not provided
in this manual. Unfortunately, no other single source exists which describes all of the relevant background
material. Comprehensive reviews of device simulation can be found in [PINT90] and the book [SELB84].
CODECS and its inversion-layer mobility model are described in [MAYA88] and LGATE90], respectively.
PISCES and its models are described in [PINT85]. Temperature dependences for the PISCES models
155
156
CHAPTER 15. MIXED-LEVEL SIMULATION (NGSPICE WITH TCAD)
used by CIDER are available in [SOLL90].
15.2
GSS, Genius
For LINUX users the cooperation of the TCAD software GSS with ngspice might be of interest, see
http://ngspice.sourceforge.net/gss.html. This project is no longer maintained however, but has moved
into the Genius simulator, still available as open source http://www.cogenda.com/downloads/category/7genius-open-source-edition.html.
Chapter 16
Analyses and Output Control
The following command lines are for specifying analyses or plots within the circuit description le. Parallel
commands exist in the interactive command interpreter (detailed in the following section). Specifying
analyses and plots (or tables) in the input le is useful for batch runs.
-b
either the
Batch mode is entered when
option is given or when the default input source is redirected from a le. In batch mode,
the analyses speci ed by the control lines in the input le (e.g. .ac, .tran, etc.) are immediately
executed (unless .control lines exists; see the section on the interactive command interpreter). If the
-r raw le option is given then all data generated is written to a ngspice raw le. The raw le may be read
by either the interactive mode of ngspice or by ngnutmeg; see the previous section for details. In this
case, the
.save line (see 16.4) may be used to record the value of internal device variables (see Appendix,
chapter 30).
If a raw le is not speci ed, then output plots (in line-printer form) and tables can be printed
according to the
16.1
.print, .plot,
and
.four
control lines, described in chapter 16.4.
Simulator Variables (.options)
Various parameters of the simulations available in Ngspice can be altered to control the accuracy, speed, or
default values for some devices. These parameters may be changed via the
in chapt. 18.4.34) or via the .options line:
option
command (described
General form:
. options
opt1
opt2
...
( or
o p t=o p t v a l
...)
Examples:
. options
r e l t o l =.005
t r t o l =8
The options line allows the user to reset program control and user options for speci c simulation
purposes. Options speci ed to Ngspice via the option command (see chapt. ) are also passed on as if
speci ed on a
.options
line. Any combination of the following options may be included, in any order.
x (below) represents some positive number.
16.1.1 General Options
ACCT
causes accounting and run time statistics to be printed.
NOACCT
NOINIT
LIST
no printing of statistics, no printing of the Initial Transient Solution.
suppresses only printing of the Initial Transient Solution, maybe combined with ACCT.
causes the summary listing of the input data to be printed.
NOMOD
NOPAGE
suppresses the printout of the model parameters.
suppresses page ejects.
NODE
causes the printing of the node table.
OPTS
causes the option values to be printed.
157
CHAPTER 16. ANALYSES AND OUTPUT CONTROL
158
TEMP=x
Resets the operating temperature of the circuit. The default value is 27
°C
(300K). TEMP
can be overridden by a temperature speci cation on any temperature dependent instance
TNOM=x
is 27
resets the nominal temperature at which device parameters are measured. The default value
°C
(300 deg K). TNOM can be overridden by a speci cation on any temperature dependent
device model.
16.1.2 DC Solution Options
The following options controls properties pertaining to DC analysis and algorithms.
Since transient
analysis is based on DC many of the options aect the latter one.
ABSTOL=x
GMIN=x
resets the absolute current error tolerance of the program. The default value is 1 pA.
resets the value of GMIN, the minimum conductance allowed by the program. The default
value is 1.0e-12.
ITL1=x
resets the dc iteration limit. The default is 100.
ITL2=x
resets the dc transfer curve iteration limit. The default is 50.
KEEPOPINFO
Retain the operating point information when either an AC, Distortion, or Pole-Zero
analysis is run.
This is particularly useful if the circuit is large and you do not want to run a
(redundant) ".OP" analysis.
PIVREL=x
resets the relative ratio between the largest column entry and an acceptable pivot value.
The default value is 1.0e-3. In the numerical pivoting algorithm the allowed minimum pivot value
is determined by EPSREL=AMAX1(PIVREL*MAXVAL, PIVTOL) where MAXVAL is the maximum element in the column where a pivot is sought (partial pivoting).
PIVTOL=x
resets the absolute minimum value for a matrix entry to be accepted as a pivot.
The
default value is 1.0e-13.
RELTOL=x
resets the relative error tolerance of the program. The default value is 0.001 (0.1%).
RSHUNT=x
introduces a resistor from each analog node to ground. The value of the resistor should
be high enough to not interfere with circuit operations.
VNTOL=x
resets the absolute voltage error tolerance of the program. The default value is 1
µV .
Matrix Conditioning info
In most SPICE-based simulators, problems can arise with certain circuit topologies.
One of the most
common problems is the absense of a DC path to ground at some node. This may happen, for example,
when two capacitors are connected in series with no other connection at the common node or when certain
code models are cascaded. The result is an ill-conditioned or nearly singular matrix that prevents the
simulation from completing. XSPICE introduces a new rshunt option to help eliminate this problem.
When used, this option inserts resistors to ground at all the analog nodes in the circuit. In general, the
value of rshunt should be set to some very high resistance (e.g. 1000 Meg Ohms or greater) so that the
operation of the circuit is essentially unaected, but the matrix problems are corrected. If you should
encounter a no DC path to ground or a matrix is nearly singular error message with your circuit, you
should try adding the following .option card to your circuit description deck.
.option rshunt = 1.0e12
Usually a value of 1.0e12 is su cient to correct the matrix problems. However, if you still have problems,
you may wish to try lowering this value to 1.0e10 or 1.0e9.
16.1. SIMULATOR VARIABLES (.OPTIONS)
159
16.1.3 Transient Analysis Options
CHGTOL=x
resets the charge tolerance of the program. The default value is 1.0e-14.
CONVSTEP=x
relative step limit applied to code models.
CONVABSSTEP=x
GMINSTEPS=x
absolute step limit applied to code models.
[*] sets number of Gmin steps to be attempted. If the value is set to zero, the gmin
stepping algorithm is disabled. In such case the source stepping algorithm becomes the standard
when the standard proceeudre fails to converge to a solution.
ITL3=x
resets the lower transient analysis iteration limit. the default value is 4. (Note: not implemented
in Spice3).
ITL4=x
resets the transient analysis timepoint iteration limit. the default is 10.
ITL5=x
resets the transient analysis total iteration limit. the default is 5000. Set ITL5=0 to omit this
test. (Note: not implemented in Spice3).
ITL6=x
[*] synonym for SRCSTEPS.
MAXEVITER=x
sets the number of event iterations that are allowed at an analysis point
MAXOPALTER=x
speci es the maximum number of analog/event alternations that the simulator
can use in solving a hybrid circuit.
MAXORD=x
[*] speci es the maximum order for the numerical integration method used by SPICE.
Possible values for the Gear method are from 2 (the default) to 6.
Using the value 1 with the
trapezoidal method speci es Euler integration.
METHOD=name
sets the numerical integration method used by SPICE. Possible names are "Gear"
or "trapezoidal" (or just "trap"). The default is trapezoidal.
NOOPALTER=TRUE|FALSE
RAMPTIME=x
if set to false alternations between analog/event are enabled.
this options sets the rate of change of independent supplies and code model indcutors
and capacitors with initial conditions speci ed.
SRCSTEPS=x
[*] a non-zero value causes SPICE to use a source-stepping method to nd the DC
operating point. Its value speci es the number of steps.
TRTOL=x
resets the transient error tolerance. The default value is 7.0. This parameter is an estimate
of the factor by which ngspice overestimates the actual truncation error. If XSPICE is enabled, the
value is internally set to 1.0 for higher precision. This will cost a facor of two in cpu time during
transient analysis.
Supply Ramping example
A supply ramping function is provided by the simulator as an option to a transient analysis to simulate
the turn-on of power supplies to a board level circuit. The supply ramping function linearly ramps the
values of all independent sources and the capacitor and inductor code models (code model extension) with
initial conditions toward their nal value at a rate which you de ne. A complete ngspice deck example
of usage of the
ramptime
option is shown below.
CHAPTER 16. ANALYSES AND OUTPUT CONTROL
160
Example:
Supply ramping option
*
* This circuit demonstrates the use of the option
* " ramptime " which ramps independent sources and the
* capacitor and inductor initial conditions from
* zero to their final value during the time period
* specified .
*
*
. tran 0.1 5
. option ramptime =0.2
* a1 1 0 cap
. model cap capacitor ( c =1000 uf ic =1)
r1 1 0 1 k
*
a2 2 0 ind
. model ind inductor ( l =1 H ic =1)
r2 2 0 1.0
*
v1 3 0 1.0
r3 3 0 1 k
*
i1 4 0 1e -3
r4 4 0 1 k
*
v2 5 0 0.0 sin (0 1 0.3 0 0 45.0)
r5 5 0 1 k
*
. end
16.1.4 MOSFET Speci c options
BADMOS3
Use the older version of the MOS3 model with the kappa discontinuity.
DEFAD=x
resets the value for MOS drain diusion area; the default is 0.0.
DEFAS=x
resets the value for MOS source diusion area; the default is 0.0.
DEFL=x
DEFW=x
resets the value for MOS channel length; the default is 100.0
resets the value for MOS channel width; the default is 100.0
µm.
µm.
16.1.5 Transimission Lines Speci c Options
TRYTOCOMPACT
Applicable only to the LTRA model (see 7.2.1). When speci ed, the simulator
tries to condense LTRA transmission lines' past history of input voltages and currents.
16.1.6 Precedence of option and .options commands
There are various ways to set the above mentioned options in Ngspice. If no
option
or
.options
lines
are set by the user, internal default values are given for each of the simulator variables.
You may set options in the init les
spinit or .spiceinit via the option command (see chapt.
The values given here will supersede the default values. If you set options via the
.options
18.4.34).
line in your
input le, their values will supersede the default and init le data. Finally if you set options inside a
.control ... .endc section, these values will supersede any values of the respective simulator variables given
so far.
16.2. INITIAL CONDITIONS
16.2
161
Initial Conditions
16.2.1 .NODESET: Specify Initial Node Voltage Guesses
General form:
. NODESET V(NODNUM)=VAL V(NODNUM)=VAL
...
Examples:
. NODESET V( 1 2 ) = 4 . 5 V( 4 ) = 2 . 2 3
The
.nodeset line helps the program nd the dc or initial transient solution by making a preliminary
pass with the speci ed nodes held to the given voltages. The restriction is then released and the iteration
continues to the true solution. The
.nodeset line may be necessary for convergence on bistable or a-stable
circuits. In general, this line should not be necessary.
16.2.2 .IC: Set Initial Conditions
General form:
. ic
v ( nodnum)= v a l
v ( nodnum)= v a l
...
Examples:
. ic
v (4)= − 5
v (11)=5
The
.ic
v (2)=2.2
line is for setting transient initial conditions. It has two dierent interpretations, depending
uic parameter is speci ed on the .tran control line. Also, one should not confuse this
.nodeset line. The .nodeset line is only to help dc convergence, and does not aect nal
on whether the
line with the
bias solution (except for multi-stable circuits). The two interpretations of this line are as follows:
uic parameter is speci ed on the .tran line, then the node voltages speci ed on the .ic
1. When the
control line are used to compute the capacitor, diode, BJT, JFET, and MOSFET initial conditions.
This is equivalent to specifying the
convenient. The
ic=...
ic=...
parameter on each device line, but is much more
parameter can still be speci ed and takes precedence over the
.ic
values.
Since no dc bias (initial transient) solution is computed before the transient analysis, one should
take care to specify all dc source voltages on the
.ic
control line if they are to be used to compute
device initial conditions.
2. When the
uic
parameter is not speci ed on the
.tran
control line, the dc bias (initial transient)
solution is computed before the transient analysis. In this case, the node voltages speci ed on the
.ic
control line is forced to the desired initial values during the bias solution.
During transient
analysis, the constraint on these node voltages is removed. This is the preferred method since it
allows ngspice to compute a consistent dc solution.
16.3
Analyses
16.3.1 .AC: Small-Signal AC Analysis
General form:
. ac
dec
nd
fstart
. ac
oct
no
fstart
fstop
fstop
. ac
lin
np
fstart
fstop
Examples:
. ac
dec
10
1
. ac
dec
10
1K 1 0 0MEG
. ac
lin
100
dec
10K
1
1 0 0HZ
nd is the number of points per decade. oct stands for octave
no is the number of points per octave. lin stands for linear variation, and np is the number
fstart is the starting frequency, and fstop is the nal frequency. If this line is included in the
stands for decade variation, and
variation, and
of points.
input le, ngspice performs an AC analysis of the circuit over the speci ed frequency range. Note that in
CHAPTER 16. ANALYSES AND OUTPUT CONTROL
162
order for this analysis to be meaningful, at least one independent source must have been speci ed with
an ac value.
16.3.2 .DC: DC Transfer Function
General form:
. dc
srcnam
vstart
vstop
vincr
[ src2
start2
stop2
incr2 ]
Examples:
. dc VIN
0.25
5.0
. dc VDS 0
10
.5
. dc VCE 0
10
.25
. dc
0.25
VGS 0
IB
RLoad 1 k
2k
100
−15
75
5
. dc TEMP
The
.dc
0
5
1
1 0U 1U
line de nes the dc transfer curve source and sweep limits (again with capacitors open and
srcnam is the name of an independent voltage or current source, a resistor or the cirvstart, vstop, and vincr are the starting, nal, and incrementing values respectively.
inductors shorted).
cuit temperature.
The rst example causes the value of the voltage source VIN to be swept from 0.25 Volts to 5.0 Volts
in increments of 0.25 Volts. A second source (src2) may optionally be speci ed with associated sweep
parameters. In this case, the rst source is swept over its range for each value of the second source. This
option can be useful for obtaining semiconductor device output characteristics. See the example circuit
description on transistor characteristics (21.3).
16.3.3 .DISTO: Distortion Analysis
General form:
. disto
dec
nd
fstart
. disto
oct
no
fstart
f s t o p
f s t o p
. disto
lin
np
fstart
f s t o p
Examples:
. disto
dec
10
1 kHz
1 0 0Mhz
. disto
dec
10
1 kHz
1 0 0Mhz
The
.disto
0.9
line does a small-signal distortion analysis of the circuit. A multi-dimensional Volterra
series analysis is done using multi-dimensional Taylor series to represent the nonlinearities at the operating
point. Terms of up to third order are used in the series expansions.
f2overf1 is not speci ed, .disto does a harmonic analysis - i.e., it analyses
F1 , which is swept as speci ed by arguments
of the .disto command exactly as in the .ac command. Inputs at this frequency may be present at more
than one input source, and their magnitudes and phases are speci ed by the arguments of the distof1
If the optional parameter
distortion in the circuit using only a single input frequency
keyword in the input le lines for the input sources (see the description for independent sources). (The
arguments of the
distof2
keyword are not relevant in this case).
The analysis produces information about the AC values of all node voltages and branch currents at
2F1 and , vs. the input frequency F1 as it is swept. (A value of 1 (as a complex
cos(2π(2F1 )t) at 2F1 and cos(2π(3F1 )t) at 3F1 , using the convention that 1
fundamental frequency is equivalent to cos(2πF1 t).) The distortion component desired (2F1
the harmonic frequencies
distortion output) signi es
at the input
or
3F1 )
can be selected using commands in ngnutmeg, and then printed or plotted. (Normally, one is
interested primarily in the magnitude of the harmonic components, so the magnitude of the AC distortion
value is looked at). It should be noted that these are the AC values of the actual harmonic components,
and are not equal to HD2 and HD3. To obtain HD2 and HD3, one must divide by the corresponding AC
.ac line. This division can be done using ngnutmeg commands.
f2overf1 parameter is speci ed, it should be a real number between (and not equal to)
0.0 and 1.0; in this case, .disto does a spectral analysis. It considers the circuit with sinusoidal inputs at
two dierent frequencies F1 and F2 . F1 is swept according to the .disto control line options exactly as
in the .ac control line. F2 is kept xed at a single frequency as F1 sweeps - the value at which it is kept
xed is equal to f2overf1 times fstart. Each independent source in the circuit may potentially have two
values at
F1 ,
obtained from an
If the optional
16.3. ANALYSES
163
F1 and F2 . The magnitude and phase
distof1 keyword in the source's input line (see
and phase of the F2 component are speci ed by
(superimposed) sinusoidal inputs for distortion, at the frequencies
of the
F1
component are speci ed by the arguments of the
the description of independent sources); the magnitude
distof2 keyword.
the arguments of the
The analysis produces plots of all node voltages/branch currents
at the intermodulation product frequencies
F1 + F2 , F1 − F2 ,
The IM product of interest may be selected using the
and
(2F1 ) − F2 ,
vs the swept frequency
F1 .
setplot command, and displayed with the print and
plot commands. It is to be noted as in the harmonic analysis case, the results are the actual AC voltages
and currents at the intermodulation frequencies, and need to be normalized with respect to
.ac
values
to obtain the IM parameters.
If the
distof1
or
distof2
keywords are missing from the description of an independent source, then
that source is assumed to have no input at the corresponding frequency.
The default values of the
magnitude and phase are 1.0 and 0.0 respectively. The phase should be speci ed in degrees.
It should be carefully noted that the number
f2overf1
should ideally be an irrational number, and
that since this is not possible in practice, eorts should be made to keep the denominator in its fractional
representation as large as possible, certainly above 3, for accurate results (i.e., if f2overf1 is represented
as a fraction A/B , where A and B are integers with no common factors, B should be as large as possible;
A < B because f2overf1 is constrained to be < 1). To illustrate why, consider the cases
f2overf1 is 49/100 and 1/2. In a spectral analysis, the outputs produced are at F1 + F2 , F1 − F2
and 2F1 − F2 . In the latter case, F1 − F2 = F2 , so the result at the F1 − F2 component is erroneous
because there is the strong fundamental F2 component at the same frequency. Also, F1 + F2 = 2F1 − F2
note that
where
in the latter case, and each result is erroneous individually. This problem is not there in the case where
f2overf1
F1 − F2 = 51/100 F1 <> 49/100 F1 = F2 . In this case, there are two very
F2 and F1 − F2 . One of the advantages of the Volterra series
computes distortions at mix frequencies expressed symbolically (i.e. nF1 + mF2 ),
= 49/100, because
closely spaced frequency components at
technique is that it
therefore one is able to obtain the strengths of distortion components accurately even if the separation
between them is very small, as opposed to transient analysis for example. The disadvantage is of course
that if two of the mix frequencies coincide, the results are not merged together and presented (though
this could presumably be done as a postprocessing step). Currently, the interested user should keep track
of the mix frequencies himself or herself and add the distortions at coinciding mix frequencies together
should it be necessary.
16.3.4 .NOISE: Noise Analysis
General form:
. noise
v ( output
<, r e f >)
src
(
dec
|
lin
|
oct
)
pts
fstart
fstop
+
Examples:
. noise
v(5)
. noise
v(5 ,3)
VIN
V1
dec
oct
10
8
1kHZ 1 0 0Mhz
1.0
1 . 0 e6
1
.noise line does a noise analysis of the circuit. output is the node at which the total output noise
ref is speci ed, then the noise voltage v(output) - v(ref) is calculated. By default, ref
is assumed to be ground. src is the name of an independent source to which input noise is referred. pts,
fstart and fstop are .ac type parameters that specify the frequency range over which plots are desired.
pts_per_summary is an optional integer; if speci ed, the noise contributions of each noise generator is
produced every pts_per_summary frequency points. The .noise control line produces two plots:
The
is desired; if
1. one for the Noise Spectral Density curves and
2. one for the total Integrated Noise over the speci ed frequency range.
All noise voltages/currents are in squared units (V
2
integrated noise).
16.3.5 .OP: Operating Point Analysis
General form:
. op
/Hz
2
and A /Hz for spectral density,
V2
and
A2
for
CHAPTER 16. ANALYSES AND OUTPUT CONTROL
164
The inclusion of this line in an input le directs ngspice to determine the dc operating point of the
circuit with inductors shorted and capacitors opened.
Note: a DC analysis is automatically performed prior to a transient analysis to determine the transient initial conditions, and prior to an AC small-signal, Noise, and Pole-Zero analysis to determine the
linearized, small-signal models for nonlinear devices (see the KEEPOPINFO variable 16.1.2).
16.3.6 .PZ: Pole-Zero Analysis
General form:
. pz
node1
node2
node3
node4
cur
. pz
node1
node2
node3
node4
cur
zer
. pz
node1
node2
node3
node4
cur
pz
. pz
node1
node2
node3
node4
vol
pol
. pz
node1
n o d e 2 NODE3 n o d e 4
vol
zer
. pz
node1
node2
node3
vol
pz
pol
node4
pol
Examples:
. pz
1
0
3
0
cur
. pz
2
3
5
0
vol
zer
. pz
4
1
4
1
cur
pz
cur stands for a transfer function of the type (output voltage)/(input current) while vol stands for a
pol stands for pole analysis only, zer for
zero analysis only and pz for both. This feature is provided mainly because if there is a nonconvergence
in nding poles or zeros, then, at least the other can be found. Finally, node1 and node2 are the two
input nodes and node3 and node4 are the two output nodes. Thus, there is complete freedom regarding
transfer function of the type (output voltage)/(input voltage).
the output and input ports and the type of transfer function.
In interactive mode, the command syntax is the same except that the rst eld is
To print the results, one should use the command
print all.
pz instead of .pz.
16.3.7 .SENS: DC or Small-Signal AC Sensitivity Analysis
General form:
@example
. SENS OUTVAR
. SENS OUTVAR AC DEC ND FSTART FSTOP
. SENS OUTVAR AC OCT NO FSTART FSTOP
. SENS OUTVAR AC LIN NP FSTART FSTOP
@end example
Examples:
@example
. SENS V( 1 ,OUT)
. SENS V(OUT) AC DEC 1 0
. SENS
100
100 k
I (VTEST)
@end example
The sensitivity of OUTVAR to all non-zero device parameters is calculated when the SENS analysis is
speci ed. OUTVAR is a circuit variable (node voltage or voltage-source branch current). The rst form
calculates sensitivity of the DC operating-point value of OUTVAR. The second form calculates sensitivity
of the AC values of OUTVAR. The parameters listed for AC sensitivity are the same as in an AC analysis
(see ".AC" above). The output values are in dimensions of change in output per unit change of input (as
opposed to percent change in output or per percent change of input).
16.3. ANALYSES
165
16.3.8 .TF: Transfer Function Analysis
General form:
. tf
outvar
insrc
Examples:
. tf
v(5 ,
. tf
i (VLOAD)
The
.tf
3)
VIN
VIN
line de nes the small-signal output and input for the dc small-signal analysis.
smallsignal output variable and
insrc
outvar
is the
is the small-signal input source. If this line is included, ngspice
computes the dc small-signal value of the transfer function (output/input), input resistance, and output
resistance. For the rst example, ngspice would compute the ratio of V(5, 3) to VIN, the small-signal
input resistance at VIN, and the smallsignal output resistance measured across nodes 5 and 3.
16.3.9 .TRAN: Transient Analysis
General form:
. tran
tstep
t s t o p < t s t a r t >
Examples:
. tran
1 ns
100 ns
. tran
1 ns
1000 ns
. tran
10 ns
500 ns
1 us
tstep is the printing or plotting increment for lineprinter output. For use with the post-processor,
tstep is the suggested computing increment. tstop is the nal time, and tstart is the initial time. If
tstart is omitted, it is assumed to be zero. The transient analysis always begins at time zero. In the
interval , the circuit is analyzed (to reach a steady state), but no outputs are stored. In the
interval , the circuit is analyzed and outputs are stored. tmax is the maximum stepsize
that ngspice uses; for default, the program chooses either tstep or (tstop-tstart)/50.0, whichever is
smaller. tmax is useful when one wishes to guarantee a computing interval which is smaller than the
printer increment, tstep.
uic (use initial conditions) is an optional keyword which indicates that the user does not want ngspice
to solve for the quiescent operating point before beginning the transient analysis.
If this keyword is
speci ed, ngspice uses the values speci ed using IC=... on the various elements as the initial transient
.ic control line has been speci ed, then the node voltages
.ic line are used to compute the initial conditions for the devices. Look at the description on the
.ic control line for its interpretation when uic is not speci ed.
condition and proceeds with the analysis. If the
on the
16.3.10 .MEAS: Measurements after Op, Ac and Transient Analysis
The .meas or .measure statement is used to analyse the output data of a tran, ac, or dc simulation. The
command is executed immediately after the simulation has nished.
.meas analysis may not be used in batch mode (-b command line option), if an output le (raw le)
is given at the same time (-r
rawfile
command line option). In this batch mode ngspice will write its
simulation output data directly to the output le. The data is not kept in memory, thus is no longer
available for further analysis. This is made to allow a very large output stream with only a relatively
small memory usage. For .meas to be active you need to run the batch mode with a
.plot
or
.print
command. A better alternative may be to start ngspice in interactive mode.
If you need batch like operation, you may add a
.control ...
.endc
section to the input le:
CHAPTER 16. ANALYSES AND OUTPUT CONTROL
166
Example:
* input
file
...
. tran
1 ns
1000 ns
...
*********************************
. control
run
write
outputfile
data
. endc
*********************************
. end
and start ngspice in interactive mode, e.g. by running the command
ngspice inputfile
.
.meas then prints its user-de ned data analysis to the standard output. The analysis includes
propagation, delay, rise time, fall time, peak-to-peak voltage, minimum or maximum voltage, the integral
or derivative over a speci ed period and several other user de ned values.
The measure type
{DC|AC|TRAN|SP}
depends on the data which are to be evaluated, either
originating from a dc analysis, an ac analysis, a transient simulation or a spectrum from the
spec or fft
commands.
result will be a vector containing the result of the measurement. trig_variable, targ_variable,
out_variable are vectors stemming from the simulation, e.g. a voltage vector v(out).
VAL=val expects a real number val. It may be as well a parameter in or {} expanding to a real
and
number.
TD=td and AT=time expect a time value.
CROSS=# requires an integer number #. CROSS=LAST is possible as well. The same
expected by RISE and FALL.
*
************
Be careful because not all of the .measure commands have been implemented so far!
'out_variable=out_variable2' is missing for WHEN and FIND
'deriv' is missing
************
is
*
In the following lines you will get some explanation on the .measure commands. A simple simulation
le with two sines of dierent frequencies may serve as an example. The transient simulation delivers
time as the independent variable and two voltages as output (dependent variables).
Input le:
s i m p l e −meas− t r a n . s p
File :
*
*
Simple
. measurement
transient
vac1
1
vac2
2
. tran
examples
simulation
of
s i n (0
1
0 DC 0
s i n (0
1.2
0.9k
...
for
the
10 u
1k
two
0 DC 0
0
sine
signals
with
different
frequencies
0)
0
0)
5m
*
. measure
tran
$
different
inputs
see
below !
*
. control
run
plot
v(1)
v(2)
. endc
. end
After displaying the general syntax of the .measurement statement, some examples are posted, referring to the input le given above.
.measure according to general form 1 measures the dierence in dc voltage, frequency or time between two points selected from one or two output vectors. The current examples all are using transient
16.3. ANALYSES
167
simulation. Measurements start after a delay time td. If you run other examples with ac simulation or
spectrum analysis, time may be replaced by frequency, after a dc simulation the independent variable
may become a voltage or current.
General form 1:
.MEASURE {DC| AC |TRAN| SP}
|
result
CROSS=LAST>
CROSS=LAST>
Measure statement example (for use in the input le given above):
.measure tran tdiff TRIG v(1) VAL=0.5 RISE=1 TARG v(1) VAL=0.5 RISE=2
measures the time dierence between v(1) reaching 0.5 V for the rst time on its rst rising slope
(TRIG) versus reaching 0.5 V again on its second rising slope (TARG). I.e. it measures the signal period.
Output:
tdiff = 1.000000e-003 targ= 1.083343e-003 trig= 8.334295e-005
Measure statement example:
.measure tran tdiff TRIG v(1) VAL=0.5 RISE=1 TARG v(1) VAL=0.5 RISE=3
measures the time dierence between v(1) reaching 0.5 V for the rst time on its rising slope versus
reaching 0.5 V on its rising slope for the third time (i.e. two periods).
Measure statement:
.measure tran tdiff TRIG v(1) VAL=0.5 RISE=1 TARG v(1) VAL=0.5 FALL=1
measures the time dierence between v(1) reaching 0.5V for the rst time on its rising slope versus
reaching 0.5 V on its rst falling slope.
Measure statement:
.measure tran tdiff TRIG v(1) VAL=0 FALL=3 TARG v(2) VAL=0 FALL=3
measures the time dierence between v(1) reaching 0V its third falling slope versus v(2) reaching 0 V
on its third falling slope.
Measure statement:
.measure tran tdiff TRIG v(1) VAL=-0.6 CROSS=1 TARG v(2) VAL=-0.8 CROSS=1
measures the time dierence between v(1) crossing -0.6 V for the rst time (any slope) versus v(2)
crossing -0.8 V for the rst time (any slope).
Measure statement:
.measure tran tdiff TRIG AT=1m TARG v(2) VAL=-0.8 CROSS=3
measures the time dierence between the time point 1ms versus the time when v(2) crosses -0.8 V for
the third time (any slope).
The
FIND and WHEN functions allow to measure any dependent or independent time, frequency,
or dc parameter, when two signals cross each other or a signal crosses a given value. Measurements start
after a delay TD and may be restricted to a range between FROM and TO.
General form 2:
.MEASURE {DC| AC |TRAN| SP}
TO=v a l > <
CROSS=LAST>
Measure statement:
.measure tran teval WHEN v(2)=0.7 CROSS=LAST
measures the time point when v(2) crosses 0.7 V for the last time (any slope).
General form 3:
.MEASURE {DC| AC |TRAN| SP}
r e s u l t WHEN o u t _ v a r i a b l e=o u t _ v a r i a b l e 2
FROM=v a l > <
RISE=LAST>
Measure statement:
.measure tran teval WHEN v(2)=v(1) RISE=LAST
measures the time point when v(2) and v(1) are equal, v(2) rising for the last time.
Not yet implemented!
< FIXME:
CHAPTER 16. ANALYSES AND OUTPUT CONTROL
168
General form 4:
.MEASURE {DC| AC |TRAN| SP}
result
FIND
o u t _ v a r i a b l e WHEN o u t _ v a r i a b l e 2=v a l <
TD=td> <
FALL=LAST>
Measure statement:
.measure tran yeval FIND v(2) WHEN v(1)=-0.4 FALL=LAST
returns the dependent (y) variable drawn from v(2) at the time point when v(1) equals a value of
-0.4, v(2) falling for the last time.
< FIXME: Not yet implemented!
General form 5:
.MEASURE {DC| AC |TRAN| SP}
out_variable3
result
FIND
< FIXME: Not yet implemented!
General form 6:
.MEASURE {DC| AC |TRAN| SP}
result
FIND
o u t _ v a r i a b l e AT=v a l
Measure statement:
.measure tran yeval FIND v(2) AT=2m
returns the dependent (y) variable drawn from v(2) at the time point 2 ms (given by AT=time).
General form 7:
.MEASURE {DC| AC |TRAN| SP}
result
{AVG| MIN |MAX| PP |RMS|MIN_AT|MAX_AT}
o u t _ v a r i a b l e
Measure statements:
.measure tran ymax MAX v(2) from=2m to=3m
returns the maximum value of v(2) inside the time interval between 2 ms and 3 ms.
.measure tran tymax MAX_AT v(2) from=2m to=3m
returns the time point of the maximum value of v(2) inside the time interval between 2 ms and 3 ms.
.measure tran ypp PP v(1) from=2m to=4m
returns the peak to peak value of v(1) inside the time interval between 2 ms and 4 ms.
.measure tran yrms RMS v(1) from=2m to=4m
returns the root mean square value of v(1) inside the time interval between 2 ms and 4 ms.
.measure tran yavg AVG v(1) from=2m to=4m
returns the average value of v(1) inside the time interval between 2 ms and 4 ms.
General form 8:
.MEASURE {DC| AC |TRAN| SP}
result
INTEG o u t _ v a r i a b l e
Measure statement:
.measure tran yint INTEG v(2) from=2m to=3m
returns the area under v(2) inside the time interval between 2 ms and 3 ms.
General form 9:
.MEASURE {DC| AC |TRAN| SP}
result
param = ' e x p r e s s i o n '
Measure statement:
.param fval=5
.measure tran yadd param='fval + 7'
will evaluate the given expression fval + 7 and return the value 12.
.param vout_diff=50k
.meas tran bw_chk param='(vout_diff < 100k) ?
1 :
0'
will evaluate the given ternary function and return the value 1.
'Expression' is evaluated according to the rules given in chapt. 2.8.5 during start up of ngspice. Thus
it may not contain vectors like v(10), e.g. anything resulting from a simulation.
The
par('expression')
option (16.4.6) allows to use algebraic expressions in the
.measure
lines.
Every out_variable may be replaced by par('expression') within the general forms 1-9 described above.
16.3. ANALYSES
169
Internally par('expression') will be substituted by a vector according to the rules of the B source (chapt.
6.1). A typical example of the general form is shown below:
General form 10:
.MEASURE {DC| AC |TRAN| SP}
result
FIND p a r ( ' e x p r e s s i o n ' )
AT=v a l
Measure statement:
.measure tran vtest find par('(v(2)*v(1))') AT=2.3m
will return the product of the two voltages at timne point 2.3 ms.
General form:
.MEASURE {DC| AC |TRAN| SP}
.MEASURE {DC| AC |TRAN| SP}
o u t _ v a r i a b l e 2=v a l
+ o u t _ v a r i a b l e AT=v a l
result
DERIV o u t _ v a r i a b l e WHEN
+
CROSS=LAST>
.MEASURE {DC| AC |TRAN| SP}
result
DERIV o u t _ v a r i a b l e
+ WHEN o u t _ v a r i a b l e 2=o u t _ v a r i a b l e 3
+
+
.MEASURE {DC|AC|TRAN|SP} result DERIV ... is not yet available.
Some other examples, also showing the use of parameters, are given below. Corresponding demonstration input les are distributed with ngspice in folder /examples/measure.
Other examples:
. meas
tran
+v a l = ' vp / 2 '
inv_delay2
trig
v( in )
v a l = ' vp / 2 '
trig
AT = 1 n
t d=1n
f a l l =1
targ
v ( out )
r i s e =1
. meas
tran
test_data1
. meas
tran
out_slew
+v a l = ' 0 . 8 * vp '
trig
targ
v ( out )
v a l = ' 0 . 2 * vp '
v ( out )
v a l = ' vp / 2 '
r i s e =2
targ
r i s e =3
v ( out )
r i s e =2
. meas
tran
delay_chk
. meas
tran
skew
param = ' ( i n v _ d e l a y < 1 0 0 p s )
. meas
tran
skew2
when v ( o u t )=skew_meas
. meas
tran
skew3
when v ( o u t )=skew_meas
f a l l =2
. meas
tran
skew4
when v ( o u t )=skew_meas
f a l l =LAST
. meas
tran
s k e w 5 FIND v ( o u t ) AT=2n
. meas
tran
v0_min
. meas
tran
v0_avg
. meas
tran
v0_integ
. meas
tran
v0_rms
. meas
dc
is_at
. meas
dc
is_max max
. meas
dc
vds_at
. meas
ac
v o u t _ a t FIND v ( o u t ) AT=1MEG
. meas
ac
v o u t _ a t d FIND vdb ( o u t ) AT=1MEG
. meas
ac
vout_max max v ( o u t )
. meas
ac
freq_at
. meas
ac
vout_diff
. meas
ac
fixed_diff
. meas
ac
vout_avg
. meas
ac
vout_integ
. meas
ac
freq_at2
. meas
ac
bw_chk param = ' ( v o u t _ d i f f < 1 0 0 k )
. meas
ac
vout_rms
?
1
:
0'
when v ( o u t ) = 0 . 6
min
avg
i ( v0 )
i ( v0 )
integ
rms
FIND
from =' d f a l l '
from =' d f a l l '
i ( v0 )
i ( v0 )
t o = ' d f a l l +p e r i o d '
t o = ' d f a l l +p e r i o d '
from =' d f a l l '
from =' d f a l l '
t o = ' d f a l l +p e r i o d '
t o = ' d f a l l +p e r i o d '
i ( v s ) AT=1
i ( vs )
when
f r o m=0
t o =3.5
i ( vs ) =0.01
f r o m=1k
t o =10MEG
when v ( o u t ) = 0 . 1
trig
v ( out )
trig
avg
v a l =0.1
AT = 1 0 k
v ( out )
integ
v ( out )
when v ( o u t ) = 0 . 1
rms
v ( out )
targ
r i s e =1
targ
v ( out )
v a l =0.1
f r o m =10k
t o =1MEG
f r o m =20k
t o =500k
f a l l =LAST
f r o m =10
?
t o =1G
1
:
0'
v ( out )
v a l =0.1
r i s e =1
f a l l =1
CHAPTER 16. ANALYSES AND OUTPUT CONTROL
170
16.4
Batch Output
16.4.1 .SAVE: Name vector(s) to be saved in raw le
General form:
. save
vector
vector
vector
...
Examples:
. save
i ( vin )
input
output
. s a v e @m1 [ i d ]
The vectors listed on the .SAVE line are recorded in the raw le for use later with ngspice or ngnutmeg
(ngnutmeg is just the data-analysis half of ngspice, without the ability to simulate). The standard vector
names are accepted. If no .SAVE line is given, then the default set of vectors are saved (node voltages
and voltage source branch currents). If .SAVE lines are given, only those vectors speci ed are saved. For
more discussion on internal device data, see Appendix, chapt. 30. See also the section on the interactive
command interpreter for information on how to use the raw le.
16.4.2 .PRINT Lines
General form:
. print
prtype
o v 1
Examples:
. print
tran
. print
dc
. print
a c vm ( 4 ,
The
v(4)
v(2)
.print
i ( vin )
i ( vsrc )
2)
v (23 ,
vr ( 7 )
17)
vp ( 8 ,
3)
line de nes the contents of a tabular listing of one to eight output variables.
prtype
is
the type of the analysis (DC, AC, TRAN, NOISE, or DISTO) for which the speci ed outputs are desired.
The form for voltage or current output variables is the same as given in the previous section for the
print command; Spice2 restricts the output variable to the following forms (though this restriction is not
enforced by ngspice):
V(N1<,N2>)
speci es the voltage dierence between nodes N1 and N2. If N2
(and
the preceding comma) is omitted, ground (0) is assumed. See
the print
command in the previous section for more details. For
compatibility
with spice2, the following ve additional values can be accessed
for
the ac analysis by replacing the "V" in V(N1,N2) with:
I(VXXXXXXX)
VR
Real part
VI
Imaginary part
VM
Magnitude
VP
Phase
VDB
20log10(magnitude)
speci es the current owing in the independent voltage source
named
VXXXXXXX. Positive current ows from the positive node,
through the source, to the negative node. (Not yet implemented:
For the ac analysis, the corresponding replacements for the letter
I may be made in the same way as described for voltage
outputs.)
Output variables for the noise and distortion analyses have a dierent general form from that of
the other analyses.
par('expression')
There is no limit on the number of
.print
lines for each type of analysis.
option (16.4.6) allows to use algebraic expressions in the
.print
lines.
The
16.4. BATCH OUTPUT
171
16.4.3 .PLOT Lines
General form:
. plot
pltype
ov1
<( p l o 1 ,
p h i 1 )>
...
ov8>
Examples:
. plot
dc
. plot
tran
v(4)
. plot
a c vm ( 5 )
v(5)
v (17 ,
v(1)
5)
(2 ,
vm ( 3 1 ,
hd3 (R)
i ( vin )
vdb ( 5 )
v(17)
(1 ,
9)
vp ( 5 )
. plot
disto
. plot
tran
v(5 ,
.plot
line de nes the contents of one plot of from one to eight output variables.
The
hd2
5)
24)
3)
v(4)
sim2
(0 ,
5)
v(7)
(0 ,
10)
pltype
is the
type of analysis (DC, AC, TRAN, NOISE, or DISTO) for which the speci ed outputs are desired. The
syntax for the
ovi
is identical to that for the
.print
line and for the plot command in the interactive
mode.
The overlap of two or more traces on any plot is indicated by the letter X. When more than one
output variable appears on the same plot, the rst variable speci ed is printed as well as plotted. If a
.print line should be included. There is no limit
.plot lines speci ed for each type of analysis. The par('expression') option (16.4.6)
algebraic expressions in the .plot lines.
printout of all variables is desired, then a companion
on the number of
allows to use
16.4.4 .FOUR: Fourier Analysis of Transient Analysis Output
General form:
. four
freq
o v 1
Examples:
. four
The
1 0 0K v ( 5 )
.four
(or Fourier) line controls whether ngspice performs a Fourier analysis as a part of the
transient analysis.
freq
is the fundamental frequency, and
ov1
is the desired vector to be analysed. The
Fourier analysis is performed over the interval , where TSTOP is the nal
time speci ed for the transient analysis, and period is one period of the fundamental frequency. The dc
component and the rst nine harmonics are determined. For maximum accuracy, TMAX (see the
.tran
line) should be set to period/100.0 (or less for very high-Q circuits). The
option
(16.4.6) allows to use algebraic expressions in the
.four
lines.
16.4.5 .PROBE: Name vector(s) to be saved in raw le
General form:
. save
v e c t o r
Examples:
. probe
i ( vin )
input
output
. p r o b e @m1 [ i d ]
Same as .SAVE (see chapt. 16.4.1).
par('expression')
CHAPTER 16. ANALYSES AND OUTPUT CONTROL
172
16.4.6 par('expression'): Algebraic expressions for output
General form:
par ( ' e x p r e s s i o n ' )
o u t p u t=p a r ( ' e x p r e s s i o n ' )
$
not
in
. measure
Examples:
. four
1001
. measure
. print
. plot
tran
dc
s q 1=p a r ( ' v ( 1 ) * v ( 1 ) ' )
tran
vtest
find
par ( ' ( v ( 2 ) * v ( 1 ) ) ' )
o u t p u t=p a r ( ' v ( 1 ) / v ( 2 ) ' )
v(1)
v(1)
d i f f =p a r ( ' ( v (4) − v ( 2 ) ) / 0 . 0 1 ' )
In the output lines
AT= 2 . 3m
v(2)
.four, .plot, .print, .save
out222
and in the
ble to add algebraic expression for output, in addition to vectors.
.measure
evaluation it is possi-
All of these output lines accept
par('expression'), where expression is any expression as has already been de ned for the B source (see
expression may contain prede ned functions, numerical values, constants, simula-
chapter 6.1). Thus
tor output like v(n1) or i(vdb), parameters prede ned by a .param statement, and the variables hertz,
temper, and time.
Internally expression is replaced by an internally generated voltage node, which is the output of a B
source, one node and B source per par('...'). Several par('...') are allowed in each line, up to 99 per input
le. The internal nodes are named pa_00 to pa_99. If your input le already contains such node names,
an error will occur, unless you rename these nodes.
.four, .plot, .print, .save, but not in .measure, an alternative syntax output=par('expression')
par('expression') may be used as described above. output is the name of the new node
replace the expression. So output has to be unique and a valid node name.
The syntax of output=par('expression') is strict, no spaces between par and (', or between ( and
In
is possible.
to
', (' and ') both are required. Also there is not much error checking on your input, if there is an typo,
for example, an error may pop up at an unexpected place.
Chapter 17
Starting ngspice
17.1
Introduction
Ngspice consists of a simulator and a front-end for data analysis and plotting. The front-end may be run
as a separate "stand-alone" program under the name ngnutmeg. Ngnutmeg will read in the "raw" data
output le created by ngspice -r or with the write command in an interactive ngspice session. Ngnutmeg
or interactive ngspice can plot data from a simulation on a graphics terminal or a workstation display.
Most of the commands available in the interactive Ngspice front end are available in nutmeg; where this
is not the case, ngspice-only commands have been marked with an asterisk ("*").
Ngspice and ngnutmeg use the X Window System for plotting (see chapter 19.2) if they nd the
environment variable DISPLAY (OS LINUX, Cygwin, BCD ...).
(non-graphical) interface is used.
Otherwise, a terminal independent
If you are using X on a workstation, the DISPLAY variable should
already be set; if you want to display graphics on a system dierent from the one you are running ngspice
or ngutmeg on, DISPLAY should be of the form "machine:0.0". See the appropriate documentation on
the X Window System for more details.
The MS Windows vesrsions of ngspice and ngnutmeg will have a native gaphics interface (see chapter
19.1).
ngnutmeg is a subset of ngspice dedicated to data evaluation, still made available for historical reasons.
Typically ngspice will give you access to all commands required for simulation and analysis.
17.2
Where to obtain ngspice
The actual distribution of ngspice may be downloaded from the ngspice download web page.
stallation for LINUX or MS Windows is described in the le
INSTALL
The in-
to be found in the top level
directory.
If you want to check out the source code which is actually under development, you may have a look
at the ngspice source code repository, which is stored using the concurrent version system (CVS). The
CVS repository may be browsed on the CVS web page, also useful for downloading individual les. You
may however download (or check out) the complete source code tree from the console window (LINUX,
CYGWIN or MSYS/MINGW) by issuing the command (in a single line)
cvs -z3 -d:pserver:anonymous@ngspice.cvs.sourceforge.net:/cvsroot/ngspice -lf
co -P ngspice/ng-spice-rework
You need to have CVS installed, which is available for all three OSs. The whole source tree is then
available in /ngspice/ng-spice-rework.
described in
Compilation and local installation is again
INSTALL. If you later want to update your les and download the recent changes from the
repository, you just type
cvs -z3 -d:pserver:anonymous@ngspice.cvs.sourceforge.net:/cvsroot/ngspice -lf update
-d -P
173
CHAPTER 17. STARTING NGSPICE
174
17.3
Command line options for starting ngspice and ngnutmeg
Command Synopsis:
ngspice
ngnutmeg
[
[
−o
−
logfile
]
[
]
[
datafile
−r
rawfile ]
...
[
−b
]
[
−i
]
[
input
file
...
]
]
Options are:
Option
Long option
-
Meaning
Don't try to load the default data le ("rawspice.raw") if no
other les are given (ngnutmeg only).
-n
no-spiceinit
Don't try to source the le ".spiceinit" upon startup. Normally
ngspice and ngnutmeg try to nd the le in the current
directory, and if it is not found then in the user's home directory
(obsolete).
-t TERM
terminal=TERM
-b
batch
The program is being run on a terminal with mfb name term
(obsolete).
Run in batch mode. Ngspice reads the default input source (e.g.
keyboard) or reads the given input le and performs the analyses
speci ed; output is either Spice2-like line-printer plots ("ascii
plots") or a ngspice raw le. See the following section for details.
Note that if the input source is not a terminal (e.g. using the IO
redirection notation of "<") ngspice defaults to batch mode (-i
overrides). This option is valid for ngspice only.
-s
server
Run in server mode. This is like batch mode, except that a
temporary raw le is used and then written to the standard
output, preceded by a line with a single "@", after the
sicmulation is done. This mode is used by the ngspice daemon.
This option is valid for ngspice only.
Example from the console window:
cat adder.cir|ngspice -s|more
-i
interactive
Run in interactive mode. This is useful if the standard input is
not a terminal but interactive mode is desired. Command
completion is not available unless the standard input is a
terminal, however. This option is valid for ngspice only.
-r FILE
raw le=FILE
-p
pipe
Use raw le as the default le into which the results of the
simulation are saved. This option is valid for ngspice only.
Allow a program (e.g., xcircuit) to act as a GUI frontend for
ngspice through a pipe. Thus ngspice will assume that the pipe
is a tty and allows to run in interactive mode.
-o FILE
output=FILE
-h
help
All logs generated during a batch run (-b) will be saved in out le.
-v
version
Prints a version information.
-a
autorun
Start simulation immediately, as if a control section
A short help statement of the command line syntax.
.control
run
.endc
had been added to the input le.
Further arguments to ngspice are taken to be ngspice input les, which are read and saved (if running
in batch mode then they are run immediately). Ngspice accepts Spice3 (and also most Spice2) input les,
and outputs ascii plots, fourier analyses, and node printouts as speci ed in
cards. If an out parameter is given on a
.width
.plot, .four,
card, the eect is the same as
ngspice ascii plots do not use multiple ranges, however, if vectors together on a
and
.print
set width = ....
Since
.plot card have dierent
ranges they do not provide as much information as they do in a scalable graphics plot.
For ngnutmeg, further arguments are taken to be data les in binary or ascii format (see ngsconvert(1))
which are loaded into ngnutmeg. If the le is in binary format, it may be only partially completed (useful
for examining output before the simulation is nished). One le may contain any number of data sets
from dierent analyses.
17.4. STARTING OPTIONS
17.4
175
Starting options
17.4.1 Batch mode
Let's take as an example the Four-Bit binary adder MOS circuit shown in chapter 21.6, stored in a le
adder-mos.cir.
You may start the simulation immediately by calling
ngspice -b -r adder.raw -o adder.log adder-mos.cir
ngspice will start, simulate according to the .tran command and store the output data in a raw le
adder.raw. Comments, warnings and infos go to log le adder.log.
17.4.2 Interactive mode
If you call
ngspice adder-mos.cir
ngspice will start, load the circuit le, parse the circuit and then wait for your input. You may then
start the simulation by issuing the
run
command, and following completion you may analyse the data
by any of the commands given in chapter 18.4.
17.4.3 Interactive mode with control le or control section
If you add the following control section to your input le adder-mos.cir, you may call
ngspice adder-mos.cir
and see ngspice starting, simulating and then plotting immediately.
Control section:
*
ADDER
−
4 BIT ALL−NAND−GATE BINARY ADDER
. control
set
noaskquit
save
v c c#b r a n c h
run
plot
v c c#b r a n c h
rusage
all
. endc
Any suitable command listed in chapter 18.4 may be added to the control section, as well as control
structures described in chapter 18.5.
Batch-like behaviour may be obtained by changing the control
section to
Control section with batch-like behaviour:
*
ADDER
−
4 BIT ALL−NAND−GATE BINARY ADDER
. control
set
noaskquit
save
v c c#b r a n c h
run
write
a d d e r . raw
v c c#b r a n c h
quit
. endc
If you put this control section into a le, say adder-start.sp, you may just add the line
.include adder-start.sp
to your input le adder-mos.cir to obtain the batch-like behaviour. In the following example the line
.tran ...
from the input le is overridden by the
tran command given in the control section.
CHAPTER 17. STARTING NGSPICE
176
Control section overriding the .tran command:
*
ADDER
−
4 BIT ALL−NAND−GATE BINARY ADDER
. control
set
noaskquit
save
v c c#b r a n c h
tran
1n
plot
v c c#b r a n c h
rusage
500n
all
. endc
17.5
Standard con guration le spinit
Upon start up ngspice reads its con guration le
spinit. spinit may be found in C:\Spice\share\ngspice\scripts
(Windows) or /usr/local/share/ngspice/scripts (LINUX). The path may be overriden by setting the environmental variable SPICE_LIB_DIR to a path where /scripts will be added.
will also search for
spinit
in the directory where ngspice.exe resides. If
spinit
ngspice for Windows
is not found, a warning
message is issued, but ngspice will continue (but of course without code models etc.).
Standard spinit contents:
*
Standard
ngspice
alias
exit
quit
alias
acct
rusage
set
all
r n d s e e d =12
f i l e t y p e=a s c i i
ng d eb u g
* unset
brief
strcmp
__flag
*
*
file
x11lineararcs
* set
* set
* set
if
init
$program
" ngspice "
$__flag = 0
For
of
SPICE2 POLYs ,
your
edit
the
below
line
to
point
to
the
location
codemodel .
c o d e m o d e l C : / S p i c e / l i b / s p i c e / s p i c e 2 p o l y . cm
*
The
other
codemodels
c o d e m o d e l C : / S p i c e / l i b / s p i c e / a n a l o g . cm
c o d e m o d e l C : / S p i c e / l i b / s p i c e / d i g i t a l . cm
c o d e m o d e l C : / S p i c e / l i b / s p i c e / x t r a d e v . cm
c o d e m o d e l C : / S p i c e / l i b / s p i c e / x t r a e v t . cm
end
unset
__flag
spinit contains a script which is run upon startup of ngspice. You may nd details of scripting in the
next chapter. Aliases (name equivalences) are set.
set filetype=ascii
will yield ascii output in the
output data le (raw le), a more compact binary format is used otherwise. The asterisk '*' will comment
out this line. If used by ngspice, spinit will then load the XSPICE code models from their absolute paths.
You may also de ne relative paths here.
set ngdebug
will yield a lot of additional debug output. Any
other contents of the script. e.g. plotting preferences, may be included here and started automatically
set ngbehavior=all.
If the standard path for the libraries (see standard spinit above or /usr/local/lib/spice under
CYGWIN and LINUX) is not adeaquate, you may add for eaxample the ./con gure options --prefix=/usr
--libdir=/usr/lib64 to set the codemodel search path to /usr/lib64/spice. Besides the standard
lib only lib64 is aknowledged.
by ngspice. The compatibility mode of ngspice has to be set in spinit by
17.6. USER DEFINED CONFIGURATION FILE .SPICEINIT
17.6
177
User de ned con guration le .spiceinit
In addition to
spinit
you may de ne a le
.spiceinit
and put it into the current directory or in your
home directory. This le will be read in and executed after
spinit, but before any other input le is
spinit. If the command line option
read. It may contain any script and override the commands given in
-n
is used upon ngspice startup, this le will be ignored.
17.7
Environmental variables
17.7.1 Ngspice speci c variables
SPICE_LIB_DIR
default:
/usr/local/share/ngspice (LINUX, CYGWIN), C:\Spice\share\ngspice
(Windows)
SPICE_EXEC_DIR
default: /usr/local/bin (LINUX, CYGWIN), C:\Spice\bin (Windows)
SPICE_BUGADDR
default: http://ngspice.sourceforge.net/bugrep.html
Where to send bug reports on ngspice.
SPICE_EDITOR
default: vi (LINUX, CYGWIN), notepad.exe (MINGW, Visual Studio)
Set the editor called in the
SPICE_ASCIIRAWFILE
edit command.
Always overrides the EDITOR env. variable.
default: 0
Format of the raw le. 0 for binary, and 1 for ascii.
SPICE_NEWS
default: $SPICE_LIB_DIR/news
A le which is copied verbatim to stdout when ngspice starts in interactive mode.
SPICE_HELP_DIR
default: $SPICE_LIB_DIR/helpdir
Help directory, not used in Windows mode
SPICE_HOST
Used in the
default: empty string
rspice command (probably obsolete, to be documented)
SPICE_SCRIPTS
default: $SPICE_LIB_DIR/scripts
In this directory the spinit le will be searched.
SPICE_PATH
Used in the
default: $SPICE_EXEC_DIR/ngspice
aspice command (probably obsolete, to be documented)
NGSPICE_MEAS_PRECISION
default: 5
Sets the number of digits if output values are printed by the
SPICE_NO_DATASEG_CHECK
meas(ure) command.
default: unde ned
If de ned, will suppress memory resource info (probably obsolete, not used on Windows or where
the /proc information system is available.)
17.7.2 Common environment variables
TERM LINES COLS DISPLAY HOME PATH EDITOR SHELL POSIXLY_CORRECT
17.8
Memory usage
Ngspice started with batch option (-b) and raw le output (-r raw le) will store all simulation data
immediately into the raw le without keeping them in memory. Thus very large circuits may be simulated,
the memory requested upon ngspice startup will depend on the citcuit size, but will not increase during
simulation.
If you start ngspice in interactive mode or 'interactive' with control section, all data will be kept in
memory, to be available for later evaluation. A large circuit may outgrow even GBytes of memory. The
same may happen after a very long simulation run with many vectors and many time steps to be stored.
Issuing the
save
de ned by the command.
command will help to reduce memory requirements by saving only the data
CHAPTER 17. STARTING NGSPICE
178
17.9
Simulation time
Simulating large circuits may take an considerable amount of cpu time.
If this is of importance, you
should compile ngspice with the ags for optimum speed, set during con guring ngspice compilation.
Under LINUX, MINGW, and CYGWIN you should select the following option to disable the debug
mode, which slows down ngspice:
./configure --disable-debug
Adding --disable-debug will set
the -O2 optimisation ag for compiling and linking.
Under MS Visual Studio, you will have to select the
release version which includes optimization for
speed.
If you have selected XSPICE (see chapters 13 and II) as part of your compilation con guration (by
adding the option
--enable-xspice
to your
./configure
command), the value of
trtol
(see 16.1.3) is
set internally to 1 (insted of default 7) for higher precision. This may double or even triple the cpu time
needed for any transient simulation, because the amount of time steps and thus iteration steps is more
than doubled.
a... device nor the poly option for
not select --enable-xspice (even if you then will miss
So, for optimum speed, and if you do not use any
voltage sources in your input le, you may opt to
may nice features for mixed signal simulation!). For MS Visual Studio compilation there is currently no
simple way to exclude XSPICE during compilation.
Another way is to set the
option trtol=7 in your .spiceinit initialization le (via the option command
18.4.34) or in your circuit input le (via an .options line 16.1) to obtain standard spice3 tolerances and
a speed gain of two. Beware however of convergence or precision issues if you use XSPICE devices.
If your circuit comprises mostly of MOS transistors, and you have a multi-core processor at hand, you
may bene t from OpenMP parallel processing, as decribed next (17.10).
17.10
Ngspice on multi-core processors using OpenMP
17.10.1 Introduction
Todays computers typically come with CPUs having more than one core. It will thus be useful to enhance
ngspice to make use of such multi-core processors.
Using circuits comprising mostly of transistors and e.g. the BSIM3 model, around 2/3 of the cpu time
is spent in evaluating the model equations (e.g. in the BSIM3Load() function). The same happens with
other advanced transistor models. Thus this function should be parallized, if possible. Resulting from
that the parrallel processing has to be within a dedicated device model. Interstingly solving the matrix
takes only about 10% of the cpu time, so parallelizing the matrix solver is of secondary interest here!
A recent publication [1] has described a way to exactly do that using OpenMP, which is available on
many platforms and is easy to use, especially if you want to parallelize processing of a for-loop.
I have chosen the BSIM3 version 3.3.0 model, located in the BSIM3 directory, as the rst example. The
BSIM3load() function in b3ld.c contains two nested for-loops using linked lists (models and instances, e.g.
individual transistors). Unfortunately OpenMP requires a loop with an integer index. So in le B3set.c an
array is de ned, lled with pointers to all instances of BSIM3 and stored in model->BSIM3InstanceArray.
BSIM3load() is now a wrapper function, calling the for-loop, which runs through functions BSIM3LoadOMP(),
once per instance. Inside BSIM3LoadOMP() the model equations are caculated.
Typically you now need to synchronize the activities, in that storing the results into the matrix
has to be guarded.
The trick oered by the authors now is that the storage is moved out of the
BSIM3LoadOMP() function. Inside BSIM3LoadOMP() the updated data are stored in extra locations
locally per instance, de ned in bsim3def.h. Only after the complete for-loop is exercised, the update to
the matrix is done in an extra function BSIM3LoadRhsMat() in the main thread after the parallelized
loop. No extra synchronisation is required.
Then the thread programming needed is only a single line!!
#pragma omp parallel for num_threads(nthreads) private(here)
introducing the for-loop.
This of course is made possible only thanks to the OpenMP guys and the clever trick on no synchronisation introduced by the above cited authors.
The time-measuring function
usage (with the
rusage
getrusage()
used with LINUX or Cygwin to determine the cpu time
option enabled) counts tics from every core, adds them up, and thus reports a
CPU time value enlarged by a factor of 8 if 8 threads have been chosen. So now ngspice is forced to use
ftime
for time measuring if OpenMP is selected.
17.10. NGSPICE ON MULTI-CORE PROCESSORS USING OPENMP
179
Table 17.1: OpenMP performance
Threads
1 (standard)
1 (OpenMP)
2
3
4
6
8
CPU time [s]
Windows
167
174
110
95
83
94
93
CPU time [s]
LINUX
165
167
110
94-120
107
90
91
17.10.2 Some results
Some results on an inverter chain with 627 CMOS inverters, running for 200ns, compiled with Visual
Studio professional 2008 on Windows 7 (full optimization) or gcc 4.4, SUSE LINUX 11.2, -O2, on a i7
860 machine with four real cores (and 4 virtuals using hyperthreading):
So we see a ngspice speed up of nearly a factor of two! Even on an older notebook with dual core
processor, I have got more than 1.5x improvement using two threads. Similar results are to be expected
from BSIM4.
17.10.3 Usage
To say it clearly: OpenMP is installed inside the model equations of a particular model.
BSIM3 version 3.3.0, not in version
BSIM4 version 4.6.5, not an any other BSIM4 model, and
So for the
moment it is available only in
3.2.4 nor in any other BSIM3
model, in
in B4SOI, version 4.3.1, not in
any other SOI model. Older parameter les of version 4.6.x (x any number up to 5) are accepted, you
have to check for compatibility.
Under
LINUX you may run
./autogen.sh
./configure ... --enable-openmp
make install
The same has been tested under MS Windows with
CYGWIN
and
MINGW
as well and delivers
similar results.
MS Windows with Visual Studio Professional you have to place an additional preprocessor
USE_OMP, and then enable /openmp. Visual Studio Express is not su cient due to lack of
Under
ag
OpenMP support.
Even Visual Studio Professional lacks debugging support for OpenMP. There are
local preprocessor ags (USE_OMP3 in bsim3def.h, USE_OMP4 in bsim4def.h, and USE_OMP4SOI
in b4soidef.h) which you may modify individually if you want to switch o OpenMP in only one of the
models BSIM3, BSIM4, or B4SOI.
The number of threads has to be set manually by placing
set num_threads=4
into spinit or .spiceinit. If OpnenMP is enabled, but num_threads not set, a default value
num_threads=2
is set internally.
If you run a circuit, please keep in mind to select BSIM3 (levels 8, 49) version 3.3.0 (12.2.9), by placing
this version number into your parameter les), BSIM4 (levels 14, 54) version 4.6.5 (12.2.10), or B4SOI
(levels 10, 58) version 4.3.1 (12.2.12).
If you run ./con gure without
--enable-openmp (or without USE_OMP preprocessor ag under MS
Windows), you will get the standard, not parallelized BSIM3 and BSIM4 model, as has been available
from Berkeley. If OpenMP is selected and the number of threads set to 1, there will be only a very slight
cpu time disadvantage (typ. 3%) compared to the standard, non OpenMP build.
17.10.4 Literature
[1] R.K. Perng, T.-H. Weng, and K.-C. Li: "On Performance Enhancement of Circuit Simulation Using
Multithreaded Techniques", IEEE International Conference on Computational Science and Engineering,
2009, pp. 158-165
CHAPTER 17. STARTING NGSPICE
180
17.11
Server mode option -s
Aprogram may write the spice input to the console. This output is redirected to ngspice via '|'. ngspice
called with the -p option writes it output to the console, which again is redirected to a receiving program
by '|'. In the following simple example
cat
reads the input le and prints it content to the console, but
by a rst pipe redirected to ngspice, which transfers its output to
more via another pipe.
Example:
cat
input . c i r | ngspice
17.12
− s | more
Ngspice control via input, output fos
The following bash script (under LINUX)
- launches ngspice in another thread.
- writes some commands in ngspice input
- reads the output and prints them on the console.
Example:
#!/ u s r / b i n / e n v
bash
NGSPICE_COMMAND=" n g s p i c e "
rm
input . f i f o
rm
output . f i f o
mkfifo
input . f i f o
mkfifo
output . f i f o
−p − i
$NGSPICE_COMMAND
i n p u t . f i f o
echo
"I
echo
" Start
echo
""
echo
" source
echo
" set
n o a s k q u i t " >&3
echo
" set
n o b r e a k " >&3
echo
" tran
echo
" print
echo
" q u i t " >&3
can
write
to
processing . . . "
c i r c u i t . c i r " >&3
0 . 0 1 ms
0 . 1 ms">&3
n0 " >&3
echo
" Try
exec
4< o u t p u t . f i f o
echo
"I
echo
" Ready
while
to
can
open
read
to
output . f i f o
from
output
echo
$output
d o n e <&4
e x e c 3>&−
e x e c 4>&−
"End
processing "
The input le for
spice is:
..."
output . f i f o "
read . . . "
read
do
echo
input . f i f o "
>o u t p u t . f i f o
&
17.13. REPORTING ERRORS
181
Circuit.cir:
*
Circuit . cir
V1 n0
0
C1 n1
n0
R1 0
n1
SIN ( 0
10
1 kHz )
3 . 3 nF
1k
. end
17.13
REPORTING ERRORS
Ngspice is a complex piece of software. The source code contains over 1500 les. Various models and
simulation procedures are provided, some of them not used and tested intensively. Therefore errors may
be found, some still eveloving from the original spice3f5 code, others introduced during the ongoing code
enhancements.
If you happen to experience an error during the usage of ngspice, please send a report to the development team. Ngspice is hosted on sourceforge, the preferred place to post a bug report is the ngspice
bug tracker. We would prefer to have your bug tested against the actual source code available at CVS,
but of course a report using the most recent ngspice release is welcome!
information with your report:
Ngspice version
Operating system
Small input le to reproduce the bug
Actual output versus the expected output
Please provide the following
182
CHAPTER 17. STARTING NGSPICE
Chapter 18
Interactive Interpreter
18.1
Expressions, Functions, and Constants
Ngspice and ngnutmeg data is in the form of vectors: time, voltage, etc. Each vector has a type, and
vectors can be operated on and combined algebraically in ways consistent with their types. Vectors are
load command below), and when the initial data le
let command.
normally created when a data le is read in (see the
is loaded. They can also be created with the
An expression is an algebraic formula involving vectors and scalars (a scalar is a vector of length 1)
and the following operations:
+
− *
/ ^ %
,
% is the modulo operator, and the comma operator has two meanings: if it is present in the argument
list of a user de nable function, it serves to separate the arguments.
synonymous with
x + j(y).
Otherwise, the term
x , y
is
Also available are the logical operations & (and), | (or), ! (not), and the
relational operations <, >, >=, <=, =, and <> (not equal). If used in an algebraic expression they work
like they would in C, producing values of 0 or 1. The relational operators have the following synonyms:
Operator
Synonym
gt
>
lt
<
ge
>=
le
<=
ne
<>
and
&
or
|
not
!
eq
=
These are useful when < and > might be confused with IO redirection (which is almost always).
The following functions are available:
183
CHAPTER 18. INTERACTIVE INTERPRETER
184
Name
mag(vector)
ph(vector)
j(vector)
Function
Magnitude of vector (same as abs(vector)).
Phase of vector.
i(sqrt(-1)) times vector.
real(vector
The real component of vector.
imag(vector)
The imaginary part of vector.
db(vector)
20 log10(mag(vector)).
log(vector)
The logarithm (base 10) of vector.
ln(vector)
The natural logarithm (base e) of vector.
exp(vector)
e to the vector power.
abs(vector)
The absolute value of vector (same as mag).
sqrt(vector)
The square root of vector.
sin(vector)
The sine of vector.
cos(vector)
The cosine of vector.
tan(vector)
The tangent of vector.
atan(vector)
The inverse tangent of vector.
norm(vector)
The vector normalized to 1 (i.e, the largest magnitude of any
component is 1).
rnd(vector)
A vector with each component a random integer between 0 and
the absolute value of the vectors's corresponding component.
mean(vector)
The result is a scalar (a length 1 vector) that is the mean of the
elements of vector.
avg(vector)
group_delay(vector)
The average of a vector.
Calculates the group delay -dphase[rad]/dω[rad/s]. Input is the
complex vector of a system transfer function versus frequency,
resembling damping and phase per frequency value. Output is a
vector of group delay values (real values of delay times) versus
frequency.
vector(number)
The result is a vector of length number, with elements 0, 1, ...
number - 1. If number is a vector then just the rst element is
taken, and if it isn't an integer then the oor of the magnitude is
used.
unitvec(number)
The result is a vector of length number, all elements having a
value 1.
length(vector)
interpolate(plot.vector)
The length of vector.
The result of interpolating the named vector onto the scale of
the current plot. This function uses the variable polydegree to
determine the degree of interpolation.
deriv(vector)
Calculates the derivative of the given vector. This uses numeric
dierentiation by interpolating a polynomial and may not
produce satisfactory results (particularly with iterated
dierentiation). The implementation only calculates the
derivative with respect to the real component of that vector's
scale.
vecd(vector)
Compute the dierential of a vector.
vecmin(vector)
Returns the value of the vector element with maximum value.
vecmax(vector)
Returns the value of the vector element with minimum value.
sgauss(vector)
Returns a vector of random numbers drawn from a Gaussian
distribution (real value, mean = 0 , standard deviation = 1).
The length of the vector returned is determined by the input
vector. The contents of the input vector will not be used. A call
to sgauss(0) will return a single value of a random number as a
vector of length 1..
sunif(vector)
Returns a vector of random real numbers uniform distributed in
the interval [-1 .. 1[. The length of the vector returned is
determined by the input vector. The contents of the input vector
will not be used. A call to sunif(0) will return a single value of a
random number as a vector of length 1.
18.2. PLOTS
185
A vector may be either the name of a vector already de ned or a oating-point number (a scalar).
A number may be written in any format acceptable to ngspice, such as 14.6Meg or -1.231e-4. Note that
you can either use scienti c notation or one of the abbreviations like MEG or G, but not both. As with
ngspice, a number may have trailing alphabetic characters after it.
The notation
expr [num] denotes the num'th element of expr.
For multi-dimensional vectors, a vector
of one less dimension is returned. Also for multi-dimensional vectors, the notation
the nth element of the mth subvector. To get a subrange of a vector, use the form
expr[m][n] will return
expr[lower, upper]. To
reference vectors in a plot that is not the current plot (see the setplot command, below), the notation
plotname.vecname can be used. Either a plotname or a vector name may be the wildcard all. If the
plotname is all, matching vectors from all plots are speci ed, and if the vector name is all, all vectors in
the speci ed plots are referenced. Note that you may not use binary operations on expressions involving
wildcards - it is not obvious what
all + all should denote, for instance.
Thus some (contrived) examples
of expressions are:
Expressions example:
c o s (TIME) + db ( v ( 3 ) )
sin ( cos ( log ( [ 1
*
TIME
not
2
3
4
rnd ( v ( 9 ) )
−
15
( ( a c 3 . FREQ [ 3 2 ]
5
6
*
7
8
9
10])))
c o s ( v i n#b r a n c h )
& t r a n 1 . TIME [ 1 0 ] )
Vector names in ngspice may have a name such as
gt
^
[ 7 . 9 e5
8]
3)
@name[param],
where name is either the name of
a device instance or model. This denotes the value of the param parameter of the device or model. See
Appendix, chapt.
30 for details of what parameters are available.
The value is a vector of length 1.
This function is also available with the show command, and is available with variables for convenience
for command scripts. There are a number of pre-de ned constants in nutmeg. They are:
Constant
Name
Value
π
e
c
J
3.14159...
e (the base of natural logarithms)
2.71828...
c (the speed of light)
299,792,500 m/sec
i
i (the square root of -1)
kelvin
kelvin (Absolute zero in Centigrade)
-273.15°C
q
echarge (The charge of an electron)
1.6021918e-19 C
K
boltz (The Boltzman's constant)
1.3806226e-23J/K
h
planck (The Planck's constant)
6.626200e-34
These are all in MKS units. If you have another variable with a name that con icts with one of these
then it takes precedence.
18.2
Plots
The output vectors of any analysis are stored in plots, a traditional SPICE notion. A plot is a group
tran
linearize command will linearize all vectors and
store them in tran3, which then becomes the current plot. A fft will generate a plot spec1, again now the
current plot. The display command always will show all vectors in the current plot. Setplot followed
by Return will show all plots. Setplot name will change the current plot to 'name' (e.g. setplot tran2
will make tran2 the current plot). A sequence name.vector may be used to access the vector from a
of vectors. A rst
tran
command will generate several vectors within a plot tran1. A subsequent
command will store their vectors in tran2.
Then a
foreign plot.
You may generate plots by yourself: setplot new will generate a new plot named unknown1, set
curplottitle=a new plot will set a title, set curplotname=myplot will set its name as a short description, set curplotdate=Sat Aug 28 10:49:42 2010 will set its date. Note that strings with spaces
have to be given with double quotes.
Of course the notion 'plot' will be used by this manual also in its more common meaning, denoting a
graphics plot or being a
18.3
plot
command. Be careful to get the correct meaning.
Command Interpretation
If a word is typed as a command, and there is no built-in command with that name, the directories in
the
sourcepath
list are searched in order for the le. If it is found, it is read in as a command le (as
CHAPTER 18. INTERACTIVE INTERPRETER
186
if it were sourced).
Before it is read, however, the variables
argc
and
argv
are set to the number of
words following the lename on the command line, and a list of those words respectively. After the le is
nished, these variables are unset. Note that if a command le calls another, it must save its
argc since they are altered.
argv
and
Also, command les may not be re-entrant since there are no local variables.
(Of course, the procedures may explicitly manipulate a stack...) This way one can write scripts analogous
to shell scripts for ngnutmeg and ngspice.
Note that for the script to work with ngspice, it must begin with a blank line (or whatever else, since
it is thrown away) and then a line with
.control
on it.
This is an unfortunate result of the source
command being used for both circuit input and command le execution. Note also that this allows the
user to merely type the name of a circuit le as a command and it is automatically run. The commands
are executed immediately, without running any analyses that may be speci ed in the circuit (to execute
the analyses before the script executes, include a
run
command in the script).
/usr/local/lib/spice/scripts (or whatever the
sourcepath includes this directory, so you can use these
There are various command scripts installed in
path is on your machine), and the default
command les (almost) like builtin commands.
18.4
Commands
Commands marked with a * are only available in ngspice, not in ngnutmeg.
18.4.1 Ac*: Perform an AC, small-signal frequency response analysis
General Form:
ac
( DEC
| OCT |
LIN
) N Fstart
Fstop
Do an ac analysis. See chapter 16.3.1 of this manual for more details.
18.4.2 Alias: Create an alias for a command
General Form:
alias
[ word ]
[ text
...]
Causes word to be aliased to text. History substitutions may be used, as in C-shell aliases.
18.4.3 Alter*: Change a device or model parameter
Alter changes the value for a device or a speci ed parameter of a device or model.
General Form:
alter
dev =
alter
dev
alter
@dev [ param ]
param = < e x p r e s s i o n >
=
must be real (complex isn't handled right now, integer is ne though, but no strings.
For booleans, use 0/1.
Old style (pre 3f4):
alter
device
value
alter
device
parameter
value
[
parameter
value
]
Using the old style, its rst form is used by simple devices which have one principal value (resistors,
capacitors, etc.) where the second form is for more complex devices (bjt's, etc.). Model parameters can
be changed with the second form if the name contains a "#". For specifying vectors as values, start the
vector with "[", followed by the values in the vector, and end with "]". Be sure to place a space between
each of the values and before and after the "[" and "]".
Some examples are given below:
18.4. COMMANDS
187
Examples (Spice3f4 style):
alter
vd = 0 . 1
alter
vg
alter
@m1 [ w]=
alter
alter
dc = 0 . 6
1 5 e −06
@vg [ s i n ]
@Vi [ pwl ]
[
=
−1
1.5
2MEG ]
0
1.2
100p
[
0
]
18.4.4 Altermod*: Change a model parameter
General form:
altermod
mod = < e x p r e s s i o n >
altermod
mod param = < e x p r e s s i o n >
a l t e r m o d @mod [ param ]
=
Example:
a l t e r m o d m1 v t h 0 = 0 . 7
Altermod is a version of the alter (see 18.4.3) command which operates on models and is used in the
same manner.
18.4.5 Asciiplot: Plot values using old-style character plots
General Form:
asciiplot
plotargs
Produce a line printer plot of the vectors. The plot is sent to the standard output, so you can put it
into a le with
asciiplot args ... > le.
The set options width, height, and nobreak determine the width
and height of the plot, and whether there are page breaks, respectively. Note that you will have problems
if you try to asciiplot something with an X-scale that isn't monotonic (i.e, something like sin(TIME) ),
because asciiplot uses a simple-minded linear interpolation. The asciiplot command doesn't deal with log
scales or the delta keywords.
18.4.6 Aspice*: Asynchronous ngspice run
General Form:
aspice
input− f i l e
[ output− f i l e ]
Start an ngspice run, and when it is nished load the resulting data.
The raw data is kept in a
temporary le. If output- le is speci ed then the diagnostic output is directed into that le, otherwise it
is thrown away.
18.4.7 Bug: Mail a bug report
General Form:
bug
Send a bug report. Please include a short summary of the problem, the version number and name of
the operating system that you are running, the version of ngspice that you are running, and the relevant
ngspice input le. (If you have de ned
BUGADDR,
the mail is delivered to there.)
18.4.8 Cd: Change directory
General Form:
cd
[ directory ]
Change the current working directory to directory, or to the user's home directory if none is given.
CHAPTER 18. INTERACTIVE INTERPRETER
188
18.4.9 Compose: Compose a vector
General Form:
compose
name
compose
name parm = v a l
values
value1
[
[
value2
...
parm = v a l
]
...
]
The rst form takes the values and creates a new vector, the values may be arbitrary expressions.
The second form has the following possible parameters:
start
The value at which the vector should start.
stop
The value at which the vector should end.
step
The dierence between sucessive elements.
lin
The number of points, linearly spaced..
18.4.10 Destroy: Delete a data set
General Form:
destroy
[ plotnames
|
all ]
Release the memory holding the data for the speci ed runs.
18.4.11 Dc*: Perform a DC-sweep analysis
General Form:
dc
S o u r c e −Name
Vstart
Vstop
Vincr
[
Source2
Vstart2
Vstop2
Vincr2
]
Do a dc transfer curve analysis. See the previous sections (chapter 16.3.2) for more details.
18.4.12 De ne: De ne a function
General Form:
define
f u n c t i o n ( arg1 ,
arg2 ,
...)
expression
De ne the user-de nable function with the name function and arguments arg1, arg2, ...
to be ex-
pression, which may involve the arguments. When the function is later used, the arguments it is given
are substituted for the formal arguments when it is parsed. If expression is not present, any de nition
for function is printed, and if there are no arguments to de ne then all currently active de nitions are
printed. Note that you may have dierent functions de ned with the same name but dierent arities.
Some useful de nitions are:
Example:
define
max ( x , y )
(x > y)
define
min ( x , y )
(x < y)
*
*
x + ( x <= y )
x + ( x >= y )
*
*
y
y
18.4.13 Deftype: De ne a new type for a vector or plot
General Form:
deftype
[v
de nes
|
p]
typename
abbrev
types for vectors and plots. abbrev will be used to parse things like abbrev(name) and to label axes with
M, instead of numbers. It may be ommitted. Also, the command "deftype p plottype pattern
..." will assign plottype as the name to any plot with one of the patterns in its Name: eld.
Example:
deftype
v
settype
capacitance
plot
capacitance
moscap
vs
v ( cc )
F
moscap
18.4. COMMANDS
189
18.4.14 Delete*: Remove a trace or breakpoint
General Form:
delete
[
debug −number
...
]
Delete the speci ed breakpoints and traces.
The debug numbers are those shown by the status
command (unless you do status > le, in which case the debug numbers are not printed).
18.4.15 Di: Compare vectors
General Form:
diff
plot1
plot2
[ vec
...]
Compare all the vectors in the speci ed plots, or only the named vectors if any are given. There are
dierent vectors in the two plots, or any values in the vectors dier signi cantly the dierence is reported.
The variable
di_abstol, di_reltol, and di_vntol are used to determine a signi cant dierence.
18.4.16 Display: List known vectors and types
General Form:
display
[ varname
...]
Prints a summary of currently de ned vectors, or of the names speci ed. The vectors are sorted by
name unless the variable
nosort
is set. The information given is the name of the vector, the length, the
type of the vector, and whether it is real or complex data. Additionally, one vector is labelled [scale].
When a command such as plot is given without a
vs
argument, this scale is used for the X-axis. It is
always the rst vector in a raw le, or the rst vector de ned in a new plot. If you unde ne the scale (i.e,
let TIME = []),
one of the remaining vectors becomes the new scale (which is undetermined). You may
set the scale to another vector of the plot with the command
setscale (18.4.50).
18.4.17 Echo: Print text
General Form:
echo
[ text . . . ]
Echos the given text to the screen.
18.4.18 Edit*: Edit the current circuit
General Form:
edit
[
file
]
Print the current ngspice input le into a le, call up the editor on that le and allow the user to
modify it, and then read it back in, replacing the original le. If a lename is given, then edit that le
and load it, making the circuit the current one. The editor may be de ned in
like
spinit by a command line
set editor=C:/programs/notepad++.exe
18.4.19 FFT: fast Fourier transform of the input vector(s)
General Form:
fft
vector1
[ vector2 ]
...
This analysis provides a fast Fourier transform of the input vector(s). t is much faster than spec
(18.4.57) (about a factor of 50 to 100 for larger vectors) !
The t command will create a new plot consisting of the Fourier transforms of the vectors given on
the command line. Each vector given should be a transient analysis result, i.e. it should have `time' as a
scale. You will have got these vectors by the
tran Tstep Tstop Tstart
command.
The vector should have a linear equidistant time scale. Therefore linearization using the
linearize
command is recommended before running t. Be careful selecting a Tstep value small enough for good
CHAPTER 18. INTERACTIVE INTERPRETER
190
interpolation, e.g. much smaller than any signal period to be resolved by
fft (see linearize command).
The Fast Fourier Transform will be computed using a window function as given with the specwindow variable. Its code is based on the FFT function provided at http://local.wasp.uwa.edu.au/~pbourke/other/dft/,
downloaded April 5th, 2008. A new plot named specx will be generated with a new vector (having the
same name as the input vector, see command above) containing the transformed data.
How to compute the t from a transient simulation output:
−> s e t p l o t t r a n 1
−> l i n e a r i z e V( 2 )
9 −> s e t s p e c w i n d o w=b l a c k m a n
1 0 −> f f t V( 2 )
1 1 −> p l o t mag (V ( 2 ) )
ngspice
8
ngspice
9
ngspice
ngspice
ngspice
Linearize will create a new vector V(2) in a new plot tran2.
spec1 with vector V(2) holding the resulting data.
The command
new plot
The variables listed in the following table control operation of the
with the set command before calling
specwindow:
fft.
fft
fft V(2)
will create a
command. Each can be set
This variable is set to one of the following strings, which will determine the type of
windowing used for the Fourier transform in the spec command. If not set, the default is "hanning".
none
No windowing
rectangular
bartlet
Bartlett (also triangle) window
blackman
hanning
gaussian
Blackman window
Hanning (also hann or cosine) window
hamming
attop
Rectangular window
Hamming window
Gaussian window
Flat top window
Figure 18.1: Spec and FFT window functions (Gaussian order = 4)
specwindoworder:
This can be set to an integer in the range 2-8. This sets the order when the
Gaussian window is used in the spec command. If not set, order 2 is used.
18.4. COMMANDS
191
18.4.20 Fourier: Perform a fourier transform
General Form:
fourier
fundamental_frequency
[ value
...]
Does a fourier analysis of each of the given values, using the rst 10 multiples of the fundamental
frequency (or the rst nfreqs, if that variable is set - see below). The output is like that of the
.four
ngspice line (chapter 16.4.4). The values may be any valid expression. The values are interpolated onto
a xed-space grid with the number of points given by the fourgridsize variable, or 200 if it is not set. The
interpolation is of degree polydegree if that variable is set, or 1. If polydegree is 0, then no interpolation
is done. This is likely to give erroneous results if the time scale is not monotonic, though.
18.4.21 Gnuplot: Graphics output via Gnuplot
General Form:
gnuplot
file
plotargs
Like plot, but using gnuplot for graphics output and further data manipulation. ngspice creates a le
called
file.plt
containing the gnuplot command sequence, a le called
to be plotted, and a le called
file.eps
file.data
containing the data
containg a postscript hardcopy of the plot. On LINUX gnuplot
is called via xterm, which oers a gnuplot console to manipulate the data.
command console window is opened as well as the plot window.
On Windows a gnuplot
Of course you have to have gnuplot
installed properly on your system. This option will work with Gnuplot version 4.2.6, but unfortunately
not with version 4.4 (as of March 2010).
18.4.22 Hardcopy: Save a plot to a le for printing
General Form:
hardcopy
file
plotargs
Just like plot, except that it creates a le called
file
containing the plot. The le is a postscript
image. As an alternative the plot(5) format is available by setting the hcopydevtype variable to
plot5,
and can be printed by either the plot(1) program or lpr with the -g ag.
18.4.23 Help: Print summaries of Ngspice commands
Prints help. This help information, however, is spice3f5-like, stemming from 1991 and thus is outdated.
If the argument
all
is given, a short description of everything you could possibly type is printed.
If
commands are given, descriptions of those commands are printed. Otherwise help for only a few major
commands is printed. On Windows this
help command is no longer available.
Spice3f5 compatible help
may be found at http://newton.ex.ac.uk/teaching/CDHW/Electronics2/userguide/. For ngspice please
use this manual.
18.4.24 History: Review previous commands
General Form:
history
[ number ]
Print out the history, or the last
number
commands typed at the keyboard.
18.4.25 Iplot*: Incremental plot
General Form:
iplot
[
node
...]
Incrementally plot the values of the nodes while ngspice runs. The
the where command to nd trouble spots in a transient simulation.
iplot
command can be used with
CHAPTER 18. INTERACTIVE INTERPRETER
192
18.4.26 Jobs*: List active asynchronous ngspice runs
General Form:
jobs
Report on the asynchronous ngspice jobs currently running. Ngnutmeg checks to see if the jobs are
nished every time you execute a command. If it is done then the data is loaded and becomes available.
18.4.27 Let: Assign a value to a vector
General Form:
let
name = e x p r
Creates a new vector called name with the value speci ed by expr, an expression as described above.
If expr is [] (a zero-length vector) then the vector becomes unde ned. Individual elements of a vector
may be modi ed by appending a subscript to name (ex. name[0]). If there are no arguments, let is the
same as display.
let creates a vector in the current plot, use setplot (18.4.49) to create a new plot.
See also unlet (18.4.69), compose (18.4.9).
The command
18.4.28 Linearize: Interpolate to a linear scale
General Form:
linearize
vec
...
Create a new plot with all of the vectors in the current plot, or only those mentioned as arguments
to the command, all data linearized onto an equidistant time scale.
How compute the t from a transient simulation output:
−> s e t p l o t t r a n 1
−> l i n e a r i z e V( 2 )
9 −> s e t s p e c w i n d o w=b l a c k m a n
1 0 −> f f t V( 2 )
1 1 −> p l o t mag (V ( 2 ) ) t s t e p
ngspice
8
ngspice
9
ngspice
ngspice
ngspice
Linearize
will create new vectors
vec
or renew all vectors of the current plot if no arguments are
given. The new vectors are interpolated onto a linear time scale, which is determined by the values of
tstep, tstart, and tstop in the currently active transient analysis.
The currently loaded input le must
include a transient analysis (a tran command may be run interactively before the last reset, alternately),
and the current plot must be from this transient analysis.
tstart) / tstep + 1.5.
The length of the new vector is
(tstop -
This command is needed for example if you want to do a t analysis (18.4.19).
Please note that the parameter
tstep
of your transient analysis (see chapter 16.3.9) has to be small
enough to get adequate resolution, otherwise the command
linearize
will do sub-sampling of your
signal.
18.4.29 Listing*: Print a listing of the current circuit
General Form:
listing
[ logical ]
[ physical ]
[ deck ]
[ expand ]
[ param ]
logical argument is given, the listing is with all continuation lines collapsed into one line, and
physical argument is given the lines are printed out as they were found in the le. The default is
logical. A deck listing is just like the physical listing, except without the line numbers it recreates the
input le verbatim (except that it does not preserve case). If the word expand is present, the circuit is
printed with all subcircuits expanded. The option param allows to print all parameters and their actual
If the
if the
values.
18.4. COMMANDS
193
18.4.30 Load: Load raw le data
General Form:
load
[ filename ]
...
Loads either binary or ascii format raw le data from the les named.
The default lename is
rawspice.raw, or the argument to the -r ag if there was one.
18.4.31 Meas*: Mesurements on simulation data
General Form (example):
MEAS {DC| AC |TRAN}
CROSS=LAST>
TARG t a r g _ v a r i a b l e VAL=v a l
All of the input forms found in 16.3.10 may be used here with the command
.meas(ure).
Using meas inside the .control ...
the .meas use.
meas
instead of
.endc section oers additional features compared to
meas will print the results as usual, but in addition will store its measurement result
(typically the token
result given in the command line) in a vector.
This vector may be used in following
command lines of the script as an input value of another command.
For details of the command see
chapt. 16.3.10.
18.4.32 Noise*: Noise analysis
See the .NOISE analysis (16.3.4) for details.
The
noise command will generate two plots (typically named noise1 and noise2) with Noise Spectral
Density Curves and Integrated Noise data.
To write these data into output le(s), you may use the
following command sequence:
Command sequence for writing noise data to le(s):
. control
1 e −6 1 e −3
tran
write
t e s t _ t r a n . raw
n o i s e V( o u t )
print
*first
option
setplot
write
write
to
333
1
1 e8
16
onoise_total
get
all
of
the
output
( two
files )
noise1
all
noise2
t e s t _ n o i s e 2 . raw
second
write
dec
t e s t _ n o i s e 1 . raw
setplot
*
vinp
inoise_total
option
( all
t e s t a l l . raw
all
in
one
noise1 . a l l
raw− f i l e )
noise2 . a l l
. endc
18.4.33 Op*: Perform an operating point analysis
General Form:
op
Do an operating point analysis. See chapter 16.3.5 for more details.
18.4.34 Option*: Set a ngspice option
General Form:
option
[ o p t i o n=v a l ]
[ o p t i o n=v a l ]
...
Set any of the simulator variables as listed in chapt. 16.1. See this chapter also for more information
on the available options. The
option
command without any argument lists the actual options set in the
simulator (to be veri ed). Multiple options may be set in a single line.
CHAPTER 18. INTERACTIVE INTERPRETER
194
The following example demonstates a control section, which may be added to your circuit le to test
the in uence of variable trtol on the number of iterations and on the simulation time.
Command sequence for testing option trtol:
. control
set
noinit
option
t r t o l =1
echo
echo
t r t o l =1
run
rusage
traniter
trantime
reset
option
t r t o l =3
echo
echo
t r t o l =3
run
rusage
traniter
trantime
reset
option
t r t o l =5
echo
echo
t r t o l =5
run
rusage
traniter
trantime
reset
option
t r t o l =7
echo
echo
t r t o l =7
run
rusage
plot
traniter
trantime
tran1 . v ( out25 )
tran1 . v ( out50 )
v ( out25 )
v ( out50 )
. endc
18.4.35 Plot: Plot values on the display
General Form:
plot
exprs
[ ylimit
[ xcompress
comp ]
[ vs
[ xlabel
xname ]
ylo
yhi ]
[ xdelta
word ]
[ xlimit
xdel ]
xlo
[ ydelta
[ ylabel
word ]
xhi ]
ydel ]
[ title
[ xindices
[ xlog ]
word ]
xilo
[ ylog ]
xihi ]
[ loglog ]
[ samep ]
[ linear ]
Plot the given vectors or exprs on the screen (if you are on a graphics terminal).
The xlimit and
ylimit arguments determine the high and low x- and y-limits of the axes, respectively.
The xindices
arguments determine what range of points are to be plotted - everything between the xilo'th point and
the xihi'th point is plotted. The xcompress argument speci es that only one out of every comp points
should be plotted. If an xdelta or a ydelta parameter is present, it speci es the spacing between grid
lines on the X- and Y-axis. These parameter names may be abbreviated to xl, yl, xind, xcomp, xdel, and
ydel respectively.
The xname argument is an expression to use as the scale on the x-axis. If xlog or ylog are present
then the X or Y scale, respectively, is logarithmic (loglog is the same as specifying both). The xlabel and
ylabel arguments cause the speci ed labels to be used for the X and Y axes, respectively.
If samep is given, the values of the other parameters (other than xname) from the previous plot,
hardcopy, or asciiplot command is used unless re-de ned on the command line.
The title argument is used in the place of the plot name at the bottom of the graph.
The linear keyword is used to override a default logscale plot (as in the output for an AC analysis).
Finally, the keyword
polar
generates a polar plot. To produce a smith plot, use the keyword
smith.
Note that the data is transformed, so for smith plots you will see the data transformed by the function
(x-1)/(x+1). To produce a polar plot with a smith grid but without performing the smith transform, use
the keyword
smithgrid.
18.4. COMMANDS
If you specify
195
plot all,
all vectors (including the scale vector) are plotted versus the scale vector
(see commands display (18.4.16) or setscale (18.4.50) on viweing the vectors of the current plot). The
command
alli
plot ally
will not plot the scale vector, but all other 'real' y values.
will yield all current vectors, the command
plot allv
The command
plot
all voltage vectors.
18.4.36 Print: Print values
General Form:
print
[ col ]
[ line ]
expr
...
Prints the vector(s) described by the expression expr. If the col argument is present, print the vectors
named side by side. If line is given, the vectors are printed horizontally. col is the default, unless all the
vectors named have a length of one, in which case line is the default. The options width, length, and
nobreak are eective for this command (see asciiplot). If the expression is all, all of the vectors available
are printed. Thus print col all > le prints everything in the le in SPICE2 format. The scale vector
(time, frequency) is always in the rst column unless the variable noprintscale is true. You may use the
vectors alli, allv, ally with the print command, but then the scale vector will not be printed.
Examples:
set
w i d t h =300
print
set
all
l e n g t h =500
18.4.37 Quit: Leave Ngspice or Nutmeg
General Form:
quit
Quit ngnutmeg or ngspice. Ngspice will ask for an aknowledgement if parameters have not been saved.
If
'set noaskquit' is speci ed, ngspice will terminate immediately.
18.4.38 Rehash: Reset internal hash tables
General Form:
rehash
Recalculate the internal hash tables used when looking up UNIX commands, and make all UNIX
commands in the user's PATH available for command completion. This is useless unless you have set
unixcom rst (see above).
18.4.39 Reset*: Reset an analysis
General Form:
reset
Throw out any intermediate data in the circuit (e.g, after a breakpoint or after one or more analyses
have been done already), and re-parse the input le.
The circuit can then be re-run from it's initial
state, overriding the aect of any set or alter commands. In Spice-3e and earlier versions this was done
automatically by the run command.
18.4.40 Reshape: Alter the dimensionality or dimensions of a vector
General Form:
reshape
vector
vector
...
vector
vector
...
[
dimension ,
vector
vector
...
[
dimension
or
reshape
dimension ,
...
]
]
...
or
reshape
][
dimension
CHAPTER 18. INTERACTIVE INTERPRETER
196
This command changes the dimensions of a vector or a set of vectors. The nal dimension may be left
o and it will be lled in automatically. If no dimensions are speci ed, then the dimensions of the rst
vector are copied to the other vectors. An error message of the form 'dimensions of x were inconsistent'
can be ignored.
18.4.41 Resume*: Continue a simulation after a stop
General Form:
resume
Resume a simulation after a stop or interruption (control-C).
18.4.42 Rspice*: Remote ngspice submission
General Form:
rspice
input
file
Runs a ngspice remotely taking the input le as a ngspice input le, or the current circuit if no
argument is given.
Ngnutmeg or ngspice waits for the job to complete, and passes output from the
remote job to the user's standard output. When the job is nished the data is loaded in as with aspice.
If the variable
rhost
is set, ngnutmeg connects to this host instead of the default remote ngspice server
machine. This command uses the rsh command and thereby requires authentication via a .rhosts le
or other equivalent method. Note that
rsh
refers to the remote shell program, which may be
on your system; to override the default name of
rprogram
Note:
is set, then
rspice
rsh,
set the variable
remote_shell.
remsh
If the variable
rspice uses this as the pathname to the program to run on the remote system.
alter or altermod
will not acknowledge elements that have been changed via the
commands.
18.4.43 Run*: Run analysis from the input le
General Form:
run
[ rawfile ]
Run the simulation as speci ed in the input le. If there were any of the control lines .ac, .op, .tran,
or .dc, they are executed. The output is put in
raw le
if it was given, in addition to being available
interactively.
18.4.44 Rusage: Resource usage
General Form:
rusage
[ resource
...]
Print resource usage statistics. If any resources are given, just print the usage of that resource. Most
resources require that a circuit be loaded. Currently valid resources are:
elapsed
The amount of time elapsed since the last rusage elapsed call.
faults
Number of page faults and context switches (BSD only).
space
Data space used.
time
CPU time used so far.
temp
Operating temperature.
tnom
Temperature at which device parameters were measured.
equations
time
Circuit Equations
Total Analysis Time
totiter
Total iterations
18.4. COMMANDS
accept
Accepted timepoints
rejected
Rejected timepoints
loadtime
Time spent loading the circuit matrix and RHS.
reordertime
lutime
197
Matrix reordering time
L-U decomposition time
solvetime
trantime
Matrix solve time
Transient analysis time
tranpoints
traniter
Transient timepoints
Transient iterations
trancuriters
tranlutime
Transient iterations for the last time point*
Transient L-U decomposition time
transolvetime
everything
Transient matrix solve time
All of the above.
* listed incorrectly as "Transient iterations per point".
18.4.45 Save*: Save a set of outputs
General Form:
save
[ all
|
allv
|
alli
|
output
...]
Save a set of outputs, discarding the rest.
Maybe used to dramatically reduce memory (RAM)
requirements if only a few useful nodes or branches are saved. If a node has been mentioned in a save
command, it appears in the working plot after a run has completed, or in the raw le if ngspice is run in
batch mode. If a node is traced or plotted (see below) it is also saved. For backward compatibility, if
there are no save commands given, all outputs are saved.
When the keyword
all
or the keyword
allv, appears in the save command, all node voltages, voltage
source currents and inductor currents are saved in addition to any other values listed. If the keyword
alli
appears in the save command, all device currents are saved.
Note: the current implementation saves only the currents of devices which have internal nodes, i.e.
MOSFETs with non zero RD and RS; BJTs with non-zero RC, RB and RE; DIODEs with non-zero RS;
etc. Resistor and capacitor currents are not saved with this option. These de ciencies will be addressed
in a later revision.
Save voltage and current:
save
vd_node
.save). Nodes or branches have to be speci ed for
.control .... .endc section save should occur before the run or tran command
to become eective. Save allows to store and later access internal device parameters. e.g. in a command
Note: