UG086 Xilinx Memory Interface Generator (MIG), User Guide Mig
User Manual:
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- Memory Interface Solutions
- Section I: Introduction
- Using MIG
- MIG 3.6 Changes from MIG 3.5
- MIG 3.5 Changes from MIG 3.4
- MIG 3.4 Changes from MIG 3.3
- MIG 3.3 Changes from MIG 3.2
- MIG 3.2 Changes from MIG 3.1
- MIG 3.1 Changes from MIG 3.0
- MIG 3.0 Changes from MIG 2.3
- MIG 2.3 Changes from MIG 2.2
- MIG 2.2 Changes from MIG 2.1
- MIG 2.1 Changes from MIG 2.0
- MIG 2.0 Changes from MIG 1.73
- MIG 1.73 Changes from MIG 1.72
- MIG 1.72 Changes from MIG 1.7
- MIG 1.7 Changes from MIG 1.6
- MIG 1.6 Changes from MIG 1.5
- MIG 1.5 Changes from MIG 1.4
- Tool Features
- Design Tools
- Installation
- Getting Started
- MIG User Interface
- Implementing MIG Designs in ISE GUI Mode
- Using MIG
- Section II: Virtex-4 FPGA to Memory Interfaces
- Implementing DDR SDRAM Controllers
- Implementing DDR2 SDRAM Controllers
- Interface Model
- Direct-Clocking Interface
- Feature Summary
- Architecture
- MIG Tool Design Options for Direct-Clocking Interface
- DDR2 SDRAM Initialization and Calibration
- Direct-Clocking Interface Clocking Scheme
- Global Clock Architecture
- DDR2 SDRAM System and User Interface Signals
- Deep Memory Configurations
- Direct-Clocking DDR2 SDRAM Signal Allocations
- Simulating the DDR2 SDRAM Design
- Supported Devices
- Hardware Tested Configurations
- SerDes Clocking Interface
- Implementing QDRII SRAM Controllers
- Implementing DDRII SRAM Controllers
- Implementing RLDRAM II Controllers
- Section III: Spartan-3/3E/3A/3AN/3A DSP FPGA to Memory Interfaces
- Implementing DDR SDRAM Controllers
- Implementing DDR2 SDRAM Controllers
- Section IV: Virtex-5 FPGA to Memory Interfaces
- Implementing DDR2 SDRAM Controllers
- Implementing QDRII SRAM Controllers
- Implementing DDR SDRAM Controllers
- Implementing DDRII SRAM Controllers
- Feature Summary
- Architecture
- Interface Model
- Hierarchy
- MIG Design Options
- Implemented Features
- Generic Parameters
- DDRII SRAM Memory Controller Modules
- Clocking Scheme
- DDRII SRAM Initialization and Calibration
- DDRII SRAM Controller Interface Signals
- User Interface Accesses
- DDRII SRAM Signal Allocations
- Pinout Considerations
- Supported Devices
- Simulating the DDRII SRAM Design
- Section V: Simulation Guide
- Section VI: Debug Guide
- Section VII: Appendices
- Memory Implementation Guidelines
- Pinout-Related UCF Constraints for Virtex-5 FPGA DDR2 SDRAMs
- WASSO Limit Implementation Guidelines
- SSO for Spartan FPGA Designs
- Debug Port
- Analyzing MIG Designs in the ChipScope Analyzer with CDC
- Low Power Options
- Pin Mapping for x4 RDIMMs