MT3401 Datasheet. Www.s Manuals.com. Mos Tech

User Manual: Marking of electronic components, SMD Codes 03, 03**, 030N03LS, 030N03MS, 030N04NS, 035N04LS, 036N04L, 03C. Datasheets BSC030N03LS G, BSC030N03MS G, BSC030N04NS G, BSC035N04LS G, DTC143TCA, DTC143TEB, IPD036N04L G, MT3401, PDTA114EE, PSOT03, PSOT03C.

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茂钿半導體股份有限公司

MT3401

Mos-Tech Semiconductor Co.,LTD.

P-Channel Enhancement Mode Field Effect Transistor
FEATURES
●
●
●
●

PRODUCT SUMMARY

Super high dense cell design for low RDS(ON)
Rugged and reliable
Simple drive requirement
SOT-23 package

VDSS
-30V

ID

RDS(ON) (mΩ) Typ
45@ VGS=-10V

-5.6A

65 @ VGS=-4.5V

D

S

NOTE:The MT3401 is available
in a lead-free package
S

G

G

D

ABSOLUTE MAXIMUM RATINGS(TA=25℃ unless otherwise noted)
Parameter Sym

bol

Limit

Unit

Drain-Source Voltage

VDS

-30

V

Gate-Source Voltage

VGS

±20

V

ID

-5.6

A

IDM

-25

A

Drain-source Diode Forward Currentª

IS

-1.5

A

Maximum Power Dissipationª

PD

1.5

W

Operating Junction and Storage
Temperature Range

TJ,TSTG

Drain Current-Continuousª@Tj=125℃
- Pulse d

b

-55 to 150

°C

THERMAL CHARACTERISTICS
Thermal Resistance, Junction-to Ambientª

© 2 0 0 9 Mos-Tech Semiconductor

Rth

JA

1

90

℃/W

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茂钿半導體股份有限公司

MT3401

Mos-Tech Semiconductor Co.,LTD.

ELECTRICAL CHARACTERISTICS (TA=25℃ unless otherwise noted)
Parameter Sym

bol

Condition

Min

Typ

Max

Unit

OFF CHARACTERISTICS
Drain-Source Breakdown Voltage

BVDSS

VGS=0V,ID=-250µA

Zero Gate Voltage Drain Current

IDSS

VDS=-30V,V
=
GS 0V

1

µA

Gate-Body Leakage

IGSS

VGS=±10V,V
=
DS 0V

±100

nA

-2.0

V

-30

V

ON CHARACTERITICS

Gate Threshold Voltage

VGS(th) V

Drain-Source On-State Resistance

RDS(ON)

Forward Transconductance

ɡFS

DS=VGS,ID=-250µA

-1.2

VGS=-10V,I
=
D -4.6A

45

50

VGS=-4.5V,I
=
D -3.0A

65

70

=
D -1.7A
VGS=-10V,I

17

S

1226

pF

187

pF

91

pF

5.9

ns

6.9

ns

48

ns

16

ns

9.8

nC

1.8

nC

4.5

nC

mΩ

DAYNAMIC CHARACTERISTICS
Input Capacitance

CISS

Output Capacitance

COSS

Reverse Transfer Capacitance

CRSS

VDS=-15V,VGS=0V
f=1.0MHZ

SWITCHING CHARACTERISISTICS
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time

tD(ON)
tr
tD(OFF)
tf

Total Gate Charge

Qg

Gate-Source Charge

Qgs

Gate-Drain Charge

Qgd

© 2 0 0 9 Mos-Tech Semiconductor

VDD=-15V
ID=-1.0A,
VGEN=-10V
RL=15ohm
RGEN=6ohm

VDS=-15V,ID=-1.7A
VGS=-10V

2

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茂钿半導體股份有限公司

MT3401

Mos-Tech Semiconductor Co.,LTD.

ELECTRICAL CHARACTERICS (TA=25℃ unless otherwise noted)
Parameter Sym

bol

Condition

Min

Typ

Max

Unit

-0.8

-1.2

V

DRAIN-SOURCE DIODE CHARACTERISTICS
Diode Forward Voltage

VSD

VGS=
=0V,IS -1.25A

Notes

-ID, Drain Current (A)

-ID,Drain Current(A)

a. Surface Mounted on FR4 Board, t≦10sec
b. Pulse Test: Pulse Width≦300Us, Duty Cycle≦2%
c. Guaranteed by design, not subject to production testing.

- VDS, Drain-to-Source Voltage (V)

-VGS, Gate-to-source Voltage (V)
Figure 2.Transfer Characteristics

C,Capacitance(pF)

RDS(ON), On-Resistance(mΩ)

Figure 1.Output Characteristics

VGS=-10V
ID=-1.7A

- VGS, Drain-to Source Voltage
Figure3.Capacitance

Figure4. On-Resistance Variation with
Temperature

© 2 0 0 9 Mos-Tech Semiconductor

3

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茂钿半導體股份有限公司

MT3401

Mos-Tech Semiconductor Co.,LTD.

0.4

10

ID=-250uA

0.3
0.2
0.1
0.0
-0.1
-0.2
--50 -25 0

25 50 75 1

TJ=150℃

Is-Source Currenti(A)

Gate-Source Threshold Voltage

Vth, Normalized

0.5

00 12 5

TJ=25℃
1
0.2 0. 4 0. 6

0.8 1. 0 1. 2

1.4 1. 6

VSD-Soures-to-Drain Voltage(V)

Tj,. Junction Temperature(℃)

21

20

18

10

-Is,Source-drain current(A)

ɡFS,Transconductance(S)

Figure5.Gate Threshold Variation
With Temperature

15
12
9
6
3

VGS=-5V

0
0

5

10

15

20

25

1
0.6

30

1. 2

1. 4

1. 6

50

10

10

VDS=-15V

-ID,Drain Current(A)

-VGS,Gate to Source Voltage

1. 0

Figure8.Body Diode Forward Voltage
Variation with Source Current

Figure7.Transconductance Variation
With Drain Current

ID=-1.7A

6
4

2
0

0. 8

-VSD, Body Diode Forward Voltage

-IDS, Drain-Source Current (A)

8

Tj=25℃

0

1

0.1

0.03
0

1

2

3

4

5

6

0.1

7

10 20

50

-VDS, Drain-Source Voltage(V)

Qɡ, Total Gate Charge(nC)

Figure9. Gate Charge

© 2 0 0 9 Mos-Tech Semiconductor

1

Figure10.Maximum Safe Operating Area

4

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SOT-23 Std Tape and Reel Data
SOT23-3L Packaging
Configuration: F igure 1.0
Cus tomized Lab el

Packaging Description:
S OT 23-3L par ts ar e s hipped i n tape. T he carrier tape is
made from a d issipative (carbon filled) polycarbonate
resin. T he cover tape i s a m ultilay er film (Heat Activated
Adhes ive in nature) primarily c omposed o f polyester film,
adhes ive l ayer, seal ant, and anti-static s prayed ag ent.
T hes e reeled parts i n s tandard option ar e s hipped with
3, 000 units per 7 " or 177mm diameter reel. T he r eels ar e
dark blue in c olor and is made of polystyrene plas tic ( antistatic coated). O ther option c omes in 10,000 units per 13"
or 330c m diameter reel. T his and s ome other options ar e
des cribed in the P ackaging I nformation table.

Antis tatic Cover Tape

ACTR Label

T hes e f ull reel s are i ndividually labeled and plac ed inside
a s tandar d immediate bo x made o f recyclable corrugated
brown paper w ith a F airchild logo p rinting. One box
contains five reel s maximum. And thes e immediate boxes
are plac ed inside a labeled s hipping box which c omes i n
different s izes depending on the number of parts s hipped.

E mbosse d
Carri er Tape

038I

038I

038I

038I

SOT23-3L Packaging Information
Packaging Option
Packaging type
Qty per Reel/Tube/Bag

S tandar d
(no flow code)
TN R
3, 000

D87Z

7" Dia

13"

193x 183x80

355x 333x40

Max qty per Box

15, 000

30, 000

Weight per unit (gm)

0. 0082

0. 0082

Weight per Reel (kg)

0. 1175

0. 4006

Reel Size
Box Dimension (mm)

SOT23-3L Unit Orientation

TN R
10, 000

03 X X

MARKING DIAGRAM

Note/Comments

X:Month Code
X:Year Code

B arcode
Lab el

03:PartNO.
B arcode L abel s ample

B
L

XH1 MT3401AACTR

QT Y : 3000

XH2 C97I27K1-038I-K133 M13274

SPEC :

D
D
MOS-TECH SEMICONDUCTOR LTD

(ACTR)

193m m x 183m m x 80m m
P izza B ox for S tandard O ption

SOT23-3L Tape Leader and Trailer
Configuration: F igure 2.0

C arrier Tape
C over T ape

Tr ailer Ta pe
300mm minimum or
75 em pty pock ets

©2009 MOS-TECH Semiconductor Corporation

C omponents

Leade r T ape
500mm minimum or
125 em pty pockets

2009, Rev. D

SOT-23 Std Tape and Reel Data, continued
SOT23-3L Embossed Carrier Tape
Configuration: Figure 3.0
P0

P2

D0

D1

T
E1

W

F
E2
Wc

B0

Tc

A0

P1

K0

User Direction of Feed

Dimensions are in millimeter
Pkg type

A0

B0

SOT-23
(8mm)

3.15
+/-0.10

2.77
+/-0.10

W
8.0
+/-0.3

D0

D1

E1

E2

1.55
+/-0.05

1.125
+/-0.125

1.75
+/-0.10

F

6.25
min

3.50
+/-0.05

P1

P0

4.0
+/-0.1

4.0
+/-0.1

K0

T

1.30
+/-0.10

0.228
+/-0.013

Notes: A0, B0, and K0 dimensions are determined with respect to the EIA/Jedec RS-481
rotational and lateral movement requirements (see sketches A, B, and C).

Wc

0.06
+/-0.02

0.5mm
maximum

20 deg maximum
Typical
component
cavity
center line

B0

5.2
+/-0.3

Tc

0.5mm
maximum

20 deg maximum component rotation
Typical
component
center line

Sketch A (Side or Front Sectional View)
A0

Component Rotation

Sketch C (Top View)

Component lateral movement

Sketch B (Top View)

SOT23-3L Reel Configuration: Figure 4.0

Component Rotation

W1 Measured at Hub

Dim A
Max

Dim A
max

See detail AA

Dim N

7" Diameter Option
B Min
Dim C
See detail AA
W3

13" Diameter Option

Dim D
min

W2 max Measured at Hub
DETAIL AA

Dimensions are in inches and millimeters
Tape Size

Reel
Option

Dim A

Dim B
0.059
1.5

512 +0.020/-0.008
13 +0.5/-0.2

0.795
20.2

2.165
55

0.331 +0.059/-0.000
8.4 +1.5/0

0.567
14.4

0.311 - 0.429
7.9 - 10. 9

0.059
1.5

512 +0.020/-0.008
13 +0.5/-0.2

0.795
20.2

4.00
100

0.331 +0.059/-0.000
8.4 +1.5/0

0.567
14.4

0.311 - 0.429
7.9 - 10. 9

8mm

7" Dia

7.00
177.8

8mm

13" Dia

13.00
330

Dim C

Dim D

Dim N

Dim W1

Dim W2

Dim W3 (LSL-USL)

October 2005, Rev. D1

MOS-TECH Semiconductor Co.,LTD


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9. ೼Փ⫼ᴀ䌘᭭᠔䆄䕑ⱘѻકᯊˈᇍѢ᳔໻乱ᅮؐǃᎹ԰⬉⑤⬉य़ⱘ㣗ೈǃᬒ⛁⡍ᗻǃᅝ㺙ᴵӊঞ݊Ҫᴵӊ䇋
೼ᴀ݀ৌ㾘ᅮⱘֱ䆕㣗ೈ‫ݙ‬Փ⫼DŽབᵰ䍙ߎњᴀ݀ৌ㾘ᅮⱘֱ䆕㣗ೈՓ⫼ᯊˈᇍѢ⬅ℸ㗠䗴៤ⱘᬙ䱰੠ߎ⦄
ⱘџᬙˈᴀ݀ৌᇚϡᡓᢙӏԩ䋷ӏDŽ
10.ᴀ݀ৌϔⳈ㟈࡯Ѣᦤ催ѻકⱘ䋼䞣੠ৃ䴴ᗻˈԚϔ㠀ᴹ䇈ˈञᇐԧѻકᘏӮҹϔᅮⱘὖ⥛থ⫳ᬙ䱰ǃ៪㗙⬅
ѢՓ⫼ᴵӊϡৠ㗠ߎ⦄䫭䇃䖤㸠ㄝDŽЎњ䙓‫ܡ‬಴ᴀ݀ৌⱘѻકথ⫳ᬙ䱰៪㗙䫭䇃䖤㸠㗠ᇐ㟈Ҏ䑿џᬙ੠☿♒
៪䗴៤⼒Ӯᗻⱘᤳ༅ˈᏠᳯᅶ᠋㛑㞾㸠䋳䋷䖯㸠‫ݫ‬ԭ䆒䅵ǃ䞛পᓊ⚻ᇍㄪঞ䖯㸠䰆ℶ䫭䇃䖤㸠ㄝⱘᅝܼ䆒䅵
˄ࣙᣀ⹀ӊ੠䕃ӊϸᮍ䴶ⱘ䆒䅵˅ҹঞ㗕࣪໘⧚ㄝˈ䖭ᰃ԰Ўᴎ఼੠㋏㒳ⱘߎॖֱ䆕DŽ⡍߿ᰃऩ⠛ᴎⱘ䕃ӊˈ
⬅Ѣऩ⣀䖯㸠偠䆕ᕜೄ䲒ˈ᠔ҹ㽕∖೼乒ᅶࠊ䗴ⱘ᳔㒜ⱘᴎ఼ঞ㋏㒳Ϟ䖯㸠ᅝܼẔ偠Ꮉ԰DŽ
11. བᵰᡞᴀ䌘᭭᠔䆄䕑ⱘѻકҢ݊䕑ԧ䆒໛Ϟौϟˈ᳝ৃ㛑䗴៤၈‫ܓ‬䇃৲ⱘॅ䰽DŽ乒ᅶ೼ᇚᴀ݀ৌѻકᅝ㺙ࠄ
乒ᅶⱘ䆒໛Ϟᯊˈ䇋乒ᅶ㞾㸠䋳䋷ᇚᴀ݀ৌѻક䆒㕂Ўϡᆍᯧ࠹㨑ⱘᅝܼ䆒䅵DŽབᵰҢ乒ᅶⱘ䆒໛Ϟ࠹㨑㗠
䗴៤џᬙᯊˈᴀ݀ৌᇚϡᡓᢙӏԩ䋷ӏDŽ
12.೼᳾ᕫࠄᴀ݀ৌⱘџ‫ܜ‬к䴶䅸ৃᯊˈϡৃᇚᴀ䌘᭭ⱘϔ䚼ߚ៪㗙ܼ䚼䕀䕑៪㗙໡ࠊDŽ
13.བᵰ䳔㽕њ㾷݇Ѣᴀ䌘᭭ⱘ䆺㒚‫ݙ‬ᆍˈ៪㗙᳝݊Ҫ݇ᖗⱘ䯂乬ˈ䇋৥ᴀ݀ৌⱘ㧹Ϯにষ੼䆶DŽ

Keep safety first in your circuit designs!
1. MOS-TECH Semiconductor Corp. puts the maximum effort into making semiconductor products better
and more reliable, but there is always the possibility that trouble may occur with them. Trouble with
semiconductors may lead to personal injury, fire or property damage.
Remember to give due consideration to safety when making your circuit designs, with appropriate
measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or
(iii) prevention against any malfunction or mishap.

©2010 MOS-TECH Semiconductor Corporation

www.mtsemi.com

www.s-manuals.com



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