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MT6228 GSM/GPRS Baseband
Processor Data Sheet
Revision 1.02
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September 09, 2005
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MT6228 GSM/GPRS Baseband Processor Data Sheet Revision 1.0
Revision History
Revision
Date
1.00
Jun 28, 2005
Fixed ball count description from 313 to 314 balls.
Typo fixed.
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2.
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Sep 09, 2005
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1.02
First Release
1. Correct typo in “Flow Control” section of Post Resize
Aug 30, 2005
2. Change IRQ_STA and IRQ_STA2 registers to RO type in Interrupt-Controller
3. Additional core power ball, VDDK, is added in ball map diagram.
4. Updated package thickness to 1.2 in product description
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1.01
Comments
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MT6228 GSM/GPRS Baseband Processor Data Sheet Revision 1.0
TABLE OF CONTENTS
Revision History...................................................................................................................................... 2
Preface...................................................................................................................................................... 5
1. System Overview............................................................................................................................... 6
4
5
6
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Pin Outs.................................................................................................................................................................... 17
Top Marking Definition ........................................................................................................................................... 20
DC Characteristics ................................................................................................................................................... 21
Pin Description......................................................................................................................................................... 22
Power Description.................................................................................................................................................... 31
Micro-Controller Unit Subsystem ................................................................................................. 37
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
3.10
Processor Core ......................................................................................................................................................... 38
Memory Management .............................................................................................................................................. 38
Bus System............................................................................................................................................................... 41
Direct Memory Access............................................................................................................................................. 45
Interrupt Controller .................................................................................................................................................. 61
Code Cache Controller............................................................................................................................................. 74
MPU......................................................................................................................................................................... 82
Data Cache ............................................................................................................................................................... 91
Internal Memory Interface ..................................................................................................................................... 100
External Memory Interface .................................................................................................................................... 100
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3
Product Description........................................................................................................................ 17
2.1
2.2
2.3
2.4
2.5
Microcontroller Peripherals ........................................................................................................ 109
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
4.9
4.10
4.11
4.12
Pulse-Width Modulation Outputs........................................................................................................................... 109
Alerter .....................................................................................................................................................................112
SIM Interface ..........................................................................................................................................................114
Keypad Scanner ..................................................................................................................................................... 123
General Purpose Inputs/Outputs ............................................................................................................................ 125
General Purpose Timer........................................................................................................................................... 139
UART..................................................................................................................................................................... 142
IrDA Framer........................................................................................................................................................... 156
Real Time Clock .................................................................................................................................................... 164
Auxiliary ADC Unit ............................................................................................................................................... 170
SCCB ..................................................................................................................................................................... 173
Cipher Hash Engine ............................................................................................................................................... 176
Microcontroller Coprocessors ..................................................................................................... 185
5.1
5.2
5.3
5.4
Divider ................................................................................................................................................................... 185
CSD Accelerator .................................................................................................................................................... 187
FCS Codec ............................................................................................................................................................. 197
PPP Framer Coprocessor........................................................................................................................................ 199
Multi-Media Subsystem ............................................................................................................... 206
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Platform Features ....................................................................................................................................................... 9
MODEM Features.....................................................................................................................................................11
Multi-Media Features............................................................................................................................................... 12
General Description ................................................................................................................................................. 15
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1.1
1.2
1.3
1.4
6.1
6.2
6.3
6.4
LCD Interface ........................................................................................................................................................ 206
NAND FLASH interface ....................................................................................................................................... 226
USB OTG Controller ............................................................................................................................................. 242
Memory Stick and SD Memory Card Controller ................................................................................................... 259
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Audio Front-End........................................................................................................................... 512
7.1
7.2
7.3
General Description ............................................................................................................................................... 512
Register Definitions ............................................................................................................................................... 515
Programming Guide............................................................................................................................................... 519
Radio Interface Control ............................................................................................................... 521
8.1
8.2
8.3
8.4
Baseband Serial Interface....................................................................................................................................... 521
Baseband Parallel Interface.................................................................................................................................... 527
Automatic Power Control (APC) Unit ................................................................................................................... 530
Automatic Frequency Control (AFC) Unit ............................................................................................................ 536
Baseband Front End..................................................................................................................... 540
9.1
9.2
9.3
Baseband Serial Ports............................................................................................................................................. 541
Downlink Path (RX Path) ...................................................................................................................................... 543
Uplink Path (TX Path) ........................................................................................................................................... 549
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Graphic Memory Controller................................................................................................................................... 281
2D acceleration ...................................................................................................................................................... 284
Capture Resize ....................................................................................................................................................... 305
Drop Resize............................................................................................................................................................ 313
Post Resize ............................................................................................................................................................. 317
JPEG Decoder ........................................................................................................................................................ 330
JPEG Encoder ........................................................................................................................................................ 340
GIF Decoder........................................................................................................................................................... 346
PNG Decoder ......................................................................................................................................................... 356
Camera Interface .................................................................................................................................................... 368
Image DMA ........................................................................................................................................................... 410
Image Engine ......................................................................................................................................................... 441
MPEG-4/H.263 Video CODEC ............................................................................................................................. 458
TV Controller ......................................................................................................................................................... 498
TV encoder............................................................................................................................................................. 504
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6.5
6.6
6.7
6.8
6.9
6.10
6.11
6.12
6.13
6.14
6.15
6.16
6.17
6.18
6.19
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10 Timing Generator ......................................................................................................................... 552
10.1 TDMA timer........................................................................................................................................................... 552
10.2 Slow Clocking Unit................................................................................................................................................ 559
11 Power, Clocks and Reset .............................................................................................................. 563
11.1
11.2
11.3
11.4
B2PSI ..................................................................................................................................................................... 563
Clocks .................................................................................................................................................................... 565
Reset Generation Unit (RGU) ................................................................................................................................ 571
Software Power Down Control .............................................................................................................................. 574
12 Analog Front-end & Analog Blocks ............................................................................................ 579
12.1 General Description ............................................................................................................................................... 579
12.2 MCU Register Definitions ..................................................................................................................................... 590
12.3 Programming Guide............................................................................................................................................... 601
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13 Digital Pin Electrical Characteristics.......................................................................................... 603
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MT6228 GSM/GPRS Baseband Processor Data Sheet Revision 1.0
Preface
Acronym for Register Type
Capable of both read and write access
RO
Read only
RC
Read only. After reading the register bank, each bit which is HIGH(1) will be cleared to LOW(0 )
automatically.
WO
Write only
W1S
Write only. When writing data bits to register bank, each bit which is HIGH(1) will cause the
corresponding bit to be set to 1. Data bits which are LOW(0) has no effect on the corresponding bit.
W1C
Write only. When writing data bits to register bank, each bit which is HIGH(1) will cause the
corresponding bit to be cleared to 0. Data bits which are LOW(0) has no effect on the corresponding bit.
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MT6228 GSM/GPRS Baseband Processor Data Sheet Revision 1.0
1. System Overview
Typical application diagram is shown in Figure 1.
Platform
MT6228 is capable of running the ARM7EJ-STM RISC
processor at up to 104 MHz, thus providing fast data
processing capabilities. In addition to the high clock
frequency, separate CODE and DATA caches are also
added to further improve the overall system efficiency.
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Multi-media
The MT6228 multi-media subsystem provides a
connection to a CMOS image sensor and supports a
resolution up to 3Mpixels. With its advanced image
signal and data processing technology, MT6228 allows
efficient processing of image and video data. Built-in
JPEG CODEC and MPEG-4 CODEC enable real-time
recording and playback of high-quality images and video.
A hardware MPEG4 accelerator supports playback in VGA
mode at 15fps and encoding in CIF at 15fps. Videophone
functionality is also provided. Moreover, a high quality
de-blocking filter is removes blocking artifacts in video
playback. GIF and PNG decoders are implemented for
fast image decoding. MT6228 supports a TV-OUT
capability, allowing the mobile handset to connect to a TV
screen via an NTSC or PAL connection.
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For large amounts of data transfer, high performance DMA
(Direct Memory Access) with hardware flow control is
implemented, which greatly enhances the data movement
speed while reducing MCU processing load.
used to connect to legacy devices such as Color/Parallel
LCD, and multi-media companion chips are all supported
through this interface. To minimize power consumption
and ensure low noise, this interface is designed for flexible
I/O voltage and allows lowering of the supply voltage
down to 1.8V. The driving strength is configurable for
signal integrity adjustment. The data bus also employs
retention technology to prevent the bus from floating
during a turn over.
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MT6228 is a feature-rich and extremely powerful
single-chip solution for high-end GSM/GPRS mobile
phones. Based on the 32-bit ARM7EJ-STM RISC
processor, MT6228’s superb processing power, along with
high bandwidth architecture and dedicated hardware
support, provides an unprecedented platform for high
performance GPRS Class 12 MODEM and leading-edge
multimedia applications. Overall, MT6228 presents a
revolutionary platform for multimedia-centric mobile
devices.
Targeted as a media-rich platform for mobile applications,
MT6228 also provides hardware security digital rights
management for copyright protection. For further
safeguarding, and to protect the manufacturer’s
development investment, hardware flash content protection
is provided to prevent unauthorized porting of the software
load.
In addition to advanced image and video features, MT6228
utilizes high resolution DAC, digital audio, and audio
synthesis technology to provide superior audio features for
all future multi-media needs.
Memory
Connectivity and Storage
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To provide the greatest capacity for expansion and
maximum bandwidth for data intensive applications such
as multimedia features, MT6228 supports up to 4 external
state-of-the-art devices through its 8/16-bit host interface.
High performance devices such as Mobile RAM and
Cellular RAM are supported for maximum bandwidth.
Traditional devices such as burst/page mode flash, page
mode SRAM, and Pseudo SRAM are also supported. For
greatest compatibility, the memory interface can also be
To take advantage of its incredible multimedia strengths,
MT6228 incorporates myriads of advanced connectivity
and storage options for data storage and communication.
MT6228 supports UART, Fast IrDA, USB 1.1 Full Speed
OTG, SDIO, Bluetooth and WIFI Interface, and
MMC/SD/MS/MS Pro storage systems. These interfaces
provide MT6228 users with the highest degree of
flexibility in implementing solutions suitable for the
targeted application.
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Audio
Using a highly integrated mixed-signal Audio Front-End,
the MT6228 architecture allows for easy audio interfacing
with direct connection to the audio transducers. The
audio interface integrates D/A and A/D Converters for
Voice band, as well as high resolution Stereo D/A
Converters for Audio band. In addition, MT6228 also
provides Stereo Input and Analog MUX.
The MT6228 offers various low-power features to help
reduce system power consumption. These features
include a Pause Mode of 32 KHz clocking in Standby State,
Power Down Mode for individual peripherals, and
Processor Sleep Mode. MT6228 is also fabricated in an
advanced low leakage CMOS process, hence providing an
overall ultra low leakage solution.
Package
The MT6228 device is offered in a 13mm×13mm, 314-ball,
0.65 mm pitch, TFBGA package.
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MT6228 supports AMR codec to adaptively optimize
speech and audio quality. Moreover, HE-AAC codec is
implemented to deliver CD-quality audio at low bit rates.
Power Management
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Furthermore, to provide more better configurability and
bandwidth for multi-media products, an additional 18-bit
parallel interface is incorporated. This interface enables
connection to LCD panels as well as NAND flash devices
for additional multi-media data storage.
The JTAG interface enables in-circuit debugging of the
software program with the ARM7EJ-S core. With this
standardized debugging interface, MT6228 provides
developers with a wide set of options in choosing ARM
development kits from different third party vendors.
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To achieve a complete user interface, MT6228 also brings
together all the necessary peripheral blocks for a
multi-media GSM/GPRS phone. The peripheral blocks
include the Keypad Scanner with the capability to detect
multiple key presses, SIM Controller, Alerter, Real Time
Clock, PWM, Serial LCD Controller, and General Purpose
Programmable I/Os.
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MT6228 GSM/GPRS Baseband Processor Data Sheet Revision 1.0
On the whole, MT6228’s audio features provide a rich
solution for multi-media applications.
Radio
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MT6228 integrates a mixed-signal baseband front-end in
order to provide a well-organized radio interface with
flexibility for efficient customization. The front-end
contains gain and offset calibration mechanisms, and filters
with programmable coefficients for comprehensive
compatibility control on RF modules. This approach
allows the usage of a high resolution D/A Converter for
controlling VCXO or crystal, reducing the need for an
expensive TCVCXO. MT6228 achieves great MODEM
performance by utilizing a 14-bit high resolution A/D
Converter in the RF downlink path. Furthermore, to
reduce the need for extra external current-driving
component, the driving strength of some BPI outputs is
designed to be configurable.
Debug Function
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FLASH
SRAM
PSRAM
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MT6228 GSM/GPRS Baseband Processor Data Sheet Revision 1.0
SDRAM
CellularRAM
CMOS
SENSOR
NAND
FLASH
LCD
DEBUGGER
IMAGE INPUT
TV OUT
AFC
SPEECH/AUDIO
INPUT
SYSCLK
APC
SPEECH/AUDIO
OUTPUT
BPI
BSI
CHIP UID
B2PSI
AUXADC
POWER
MANAGEMENT
CIRCUITRY
SUPPLY
VOLTAGES
SERIAL
LCD
USB MMC/SD/MS
OTG MSPRO/SDIO
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AUDIO
DAC
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ALERTER
SIM
USIM
RF
MODULE
RX I/Q
HIFI STEREO
OUTPUT
I2S
TCVCXO
TX I/Q
FM STEREO
RADIO INPUT
PWM
18-BIT PARALLEL
INTERFACE
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JTAG
SERIAL
LCD
UART
KEYPAD
IRDA
1
2
3
4
5
6
7
8
9
*
0
#
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Figure 1 Typical application of MT6228
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MT6228 GSM/GPRS Baseband Processor Data Sheet Revision 1.0
Platform Features
General
Industry standard Parallel LCD interface
Supports multi-media companion chips with 8/16
bits data width
TFBGA 13mm×13mm, 314-ball, 0.65 mm pitch
package
Flexible I/O voltage of 1.8V ~ 2.8V for memory
interface
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Integrated voice-band, audio-band and base-band
analog front ends
MCU Subsystem
Configurable driving strength for memory
interface
ARM7EJ-S 32-bit RISC processor
Java hardware acceleration for fast Java-based
games and applets
Operating frequency: 26/52/104 MHz
Dedicated DMA bus
14 DMA channels
1M bits on-chip SRAM
1M bits MCU dedicated Tightly Coupled memory
User Interfaces
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High performance multi-layer AMBA bus
6-row × 7-column keypad controller with
hardware scanner
Supports multiple key presses for gaming
SIM/USIM controller with hardware T=0/T=1
protocol control
Real Time Clock (RTC) operating with a separate
power supply
General Purpose I/Os (GPIOs)
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256K bits CODE cache
2 sets of Pulse Width Modulation (PWM) output
64K bits DATA cache
Alerter output with Enhanced PWM or PDM
On-chip boot ROM for Factory Flash
Programming
8 external interrupt lines
Security
Watchdog timer for system crash recovery
3 sets of General Purpose Timer
Circuit Switch Data coprocessor
Division coprocessor
Cipher: supports AES, DES/3DES
Hash: supports MD5, SHA-1
Supports security key and 27 bit chip unique ID
Connectivity
PPP Framer coprocessor
External Memory Interface
Supports up to 4 external devices
Supports 8-bit or 16-bit memory components with
maximum size of up to 64M Bytes each
3 UARTs with hardware flow control and speeds
up to 921600 bps
IrDA modulator/demodulator with hardware
framer. Supports SIR/MIR/FIR operating speeds.
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Full-speed USB 1.1 OTG capability. Supports
device mode, limited host mode, and dual-role
OTG mode.
Supports Mobile RAM and Cellular RAM
Supports Flash and SRAM/PSRAM with page
mode or burst mode
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MT6228 GSM/GPRS Baseband Processor Data Sheet Revision 1.0
Multi Media Card, Secure Digital Memory Card,
Memory Stick, Memory Stick Pro host controller
with flexible I/O voltage power
Supports SDIO interface for SDIO peripherals as
well as WIFI connectivity
DAI/PCM and I2S interface for Audio application
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Power Management
Power Down Mode for analog and digital circuits
Processor Sleep Mode
7-channel Auxiliary 10-bit A/D Converter for
charger and battery monitoring and photo sensing
Test and Debug
Built-in digital and analog loop back modes for
both Audio and Baseband Front-End
DAI port complying with GSM Rec.11.10
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JTAG port for debugging embedded MCU
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Pause Mode of 32 KHz clocking in Standby State
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MT6228 GSM/GPRS Baseband Processor Data Sheet Revision 1.0
MODEM Features
Radio Interface and Baseband Front End
GSM/GPRS quad vocoders for adaptive multirate
(AMR), enhanced full rate (EFR), full rate (FR)
and half rate (HR)
GMSK modulator with analog I and Q channel
outputs
GSM channel coding, equalization and A5/1 and
A5/2 ciphering
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10-bit D/A Converter for uplink baseband I and Q
signals
GPRS GEA1 and GEA2 ciphering
14-bit high resolution A/D Converter for downlink
baseband I and Q signals
10-bit D/A Converter for Automatic Power
Control
13-bit high resolution D/A Converter for
Automatic Frequency Control
Programmable Radio RX filter
2 channels Baseband Serial Interface (BSI) with
3-wire control
Packet Switched Data with CS1/CS2/CS3/CS4
coding schemes
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Calibration mechanism of offset and gain
mismatch for baseband A/D Converter and D/A
Converter
Programmable GSM/GPRS modem
GSM Circuit Switch Data
GPRS Class 12
Voice Interface and Voice Front End
Two microphone inputs sharing one low noise
amplifier with programmable gain and automatic
gain control (AGC) mechanisms
Voice power amplifier with programmable gain
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Bi-directional BSI interface. RF chip register
read access with 3-wire or 4-wire interface.
10-Pin Baseband Parallel Interface (BPI) with
programmable driving strength
Multi-band support
2nd order Sigma-Delta A/D Converter for voice
uplink path
D/A Converter for voice downlink path
Supports half-duplex hands-free operation
Compliant with GSM 03.50
Voice and Modem CODEC
Dial tone generation
Voice memo
Noise reduction
Echo suppression
Advanced sidetone Oscillation Reduction
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Digital sidetone generator with programmable
gain
Two programmable acoustic compensation filters
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Multi-Media Features
LCD/NAND Flash Interface
Shading compensation
Dedicated Parallel Interface supports 3 external
devices with 8-/16-bit NAND flash interface,
8-/9-/16-/18-bit Parallel interface, and Serial
interface for LCM
Defect Pixel compensation
Graphic Compression
GIF Decoder
PNG Decoder
Built-in NAND Flash Controller with 1-bit ECC
for mass storage
JPEG Decoder
LCD Controller
Supports LCM format: RGB332, RGB444,
RGB565, RGB666, RGB888
Supports LCD module with maximum resolution
up to 800x600 at 24bpp
Per pixel alpha channel
True color engine
ISO/IEC 10918-1 JPEG Baseline and Progressive
modes
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Supports simultaneous connection to up to 3
parallel LCD and 2 serial LCD modules
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Supports all possible YUV formats, including
grayscale format
Supports all DC/AC Huffman table parsing
Supports all quantization table parsing
Supports a restart interval
Supports SOS, DHT, DQT and DRI marker
parsing
Supports hardware display rotation
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IEEE Std 1180-1990 IDCT standards compliance
Capable of combining display memories with up to
6 blending layers
Image Signal Processor
8/10 bit Bayer format image input
Supports progressive image processing to
minimize storage space requirement
Supports reload-able DMA for VLD stream
JPEG Encoder
Capable of processing image of size up to 3M
pixels
Color correction matrix
ISO/IEC 10918-1 JPEG baseline mode
ISO/IEC 10918-2 compliance
Supports YUV422 and YUV420 and grayscale
formats
Automatic exposure (AE) control
Supports JFIF
Automatic white balance (AWB) control
Standard DC and AC Huffman tables
Programmable AE/AWB windows
Provides 4 levels of encode quality
Edge enhancement support
Supports continuous shooting
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Gamma correction
Histogram equalization logic
Image Data Processing
Horizontal and vertical sync information on
separate pins
Supports Digital Zoom
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MT6228 GSM/GPRS Baseband Processor Data Sheet Revision 1.0
Supports RGB888/565, YUV444 image
processing
Error Resilience for decoder: Slice
Resynchronization, Data Partitioning, Reversible
VLC
High throughput hardware scaler. Capable of
tailoring an image to an arbitrary size.
Supported visual tools for encoder: I-VOP, P-VOP,
Half-Pel, DC Prediction, Unrestricted MV,
Reversible VLC, Short Header
Horizontal scaling in averaging method
Vertical scaling in bilinear method
Supports encoding motion vector of range up
to –64/+63.5 pixels
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Simultaneous scaling for MPEG-4 encode and
LCD display
HE-AAC decode support
YUV and RGB color space conversion
AAC/AMR/WB-AMR audio decode support
Pixel format transform
Pixel processing: hue/saturation/intensity/color
adjustment, Gamma correction and
grayscale/invert/sepia-tone effects
Programmable spatial filtering: linear filter,
non-linear filter and multi-pass artistic effects
Hardware accelerated image editing
Photo frame capability
AMR/WB-AMR audio encode support
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Boundary padding
TV-OUT
Supports NTSC/PAL formats (interlaced mode)
10 bit video DAC with 2x oversampling
Supports one composite video output
2D Accelerator
Supports 32-bpp ARGB8888, 24-bpp RGB888,
16-bpp RGB565, and 8-bpp index color modes
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RGB thumbnail data output
MPEG-4/H.263 CODEC
Supports SVG Tiny
Rectangle gradient fill
Hardware Video CODEC
BitBlt: multi-BitBlt with 7 rotation, 16 binary ROP
ISO/IEC 14496-2 simple profile:
Alpha blending with 7 rotation
decode @ level 0/1/2/3
Line drawing: normal line, dotted line,
anti-aliasing
encode @ level 0
ITU-T H.263 profile 0 @ level 10
Max decode speed is VGA @ 15fps
Max encode speed is CIF @ 15fps
Support VGA mode encoding
Horizontal and vertical de-blocking filter in video
playback
Circle drawing
Bezier curve drawing
Triangle flat fill
Font caching: normal font, italic font
Command queue with max depth of 2047
Audio CODEC
Supports HE-AAC codec decode
Supported visual tools for decoder: I-VOP, P-VOP,
AC/DC Prediction, 4-MV, Unrestricted MV, Error
Resilience, Short Header
Supports AAC codec decode
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Encoder resync marker and HEC
Wavetable synthesis with up to 64 tones
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Advanced wavetable synthesizer capable of
generating simulated stereo
Wavetable including GM full set of 128
instruments and 47 sets of percussions
PCM Playback and Record
Digital Audio Playback
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Audio Interface and Audio Front End
Supports I2S interface
Stereo analog input for stereo audio source
Analog multiplexer for stereo audio
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Stereo to mono conversion
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High resolution D/A Converters for Stereo Audio
playback
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1.4
General Description
Revision 1.0
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MT6228 GSM/GPRS Baseband Processor Data Sheet
Figure 2 depicts the block diagram of MT6228. Based on a dual-processor architecture, MT6228 integrates both an
ARM7EJ-S core and a digital signal processor core. ARM7EJ-S is the main processor responsible for running
high-level GSM/GPRS protocol software as well as multi-media applications. The digital signal processor manages
the low-level MODEM as well as advanced audio functions. Except for a few mixed-signal circuitries, the other
building blocks in MT6228 are connected to either the microcontroller or the digital signal processor.
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MT6228 consists of the following subsystems:
Microcontroller Unit (MCU) Subsystem: includes an ARM7EJ-S RISC processor and its accompanying
memory management and interrupt handling logics;
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Digital Signal Processor (DSP) Subsystem: includes a DSP and its accompanying memory, memory controller,
and interrupt controller;
MCU/DSP Interface: the junction at which the MCU and the DSP exchange hardware and software
information;
Microcontroller Peripherals: includes all user interface modules and RF control interface modules;
Microcontroller Coprocessors: runs computing-intensive processes in place of the Microcontroller;
DSP Peripherals: hardware accelerators for GSM/GPRS channel codec;
Multi-media Subsystem: integrates several advanced accelerators to support multi-media applications;
Voice Front End: the data path for converting analog speech to and from digital speech;
Audio Front End: the data path for converting stereo audio from an audio source;
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Video Front End: the data path for converting a video signal to NTSL/PAL format;
Baseband Front End: the data path for converting a digital signal to and from an analog signal from the RF
modules;
Timing Generator: generates the control signals related to the TDMA frame timing; and,
Power, Reset and Clock Subsystem: manages the power, reset, and clock distribution inside MT6228.
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Details of the individual subsystems and blocks are described in the following chapters.
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MIC-0
ADC
MIC-1
PATCH
UNIT
MEMORY
DSP COPROCES
SOR
TRAP
UNIT
DSP COPROCES
SOR
DAC
VOICE
AUDIO
PATH
DSP
DSP COPROCES
SOR
INTERRUPT
CONTROL
DAC
AUDIO-L
Revision 1.0
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MT6228 GSM/GPRS Baseband Processor Data Sheet
+
STEREO-L
MCU/DSP
INTERFACE
+
RX-I
ADC
RX-Q
ADC
TX-I
DAC
TX-Q
DAC
BASEBAND
PATH
BOOT
ROM
INTERRUPT
CONTROL
AFC
DAC
SECURITY
ENGINE
TV-OUT
CON
APC
DAC
APC
SERIAL RF
CONTROL
BSI
PARALLEL
RF CONTROL
BPI
CLOCK
GEN
32K
OSC
32KHZ
CRYSTAL
ON-CHIP
SRAM
EXTERNAL
MEMORY
INTERFACE
LCD
CON
GRAPHIC MEMORY
CONTROLLER
IMAGE
POST
PROC
IMAGE
DMA
2D
ENGINE
GIF/PNG
DECODE
JPEG
CODEC
NAND
LCD
MPEG-4
VIDEO
CODEC
NAND
FLASH
CON
IMAGE
SIGNAL
PROC
IMAGE RESIZER
TDMA
TIMER
SIM
GPT
RTC
WAKE UP
WDT
RESET
GPIO
PWM
ALERTER
KEYPAD
USER
INTERFACE
SDRAM
CellularRAM
FLASH
SRAM
PSRAM
TCM
Co
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DAC
SYSTEM
CLOCK
13/26MHZ
ARM7EJ-S
AFC
TVOUT
USB OTG
CACHE
CACHE
AUXADC
USB OTG
BRIDGE
AUX
ADC
ADC
DMA
CONTROL
Re
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STEREO-R
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DAC
AUDIO-R
B2PSI
SERIAL
LCD
IRDA
MMC
SD/MS
MS PRO
CMOS
SENSOR
SCCB
UART
MT6228
SERIAL PORT
CONNECTIVITY
MT
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Figure 2 MT6228 block diagram.
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2
2.1
Product Description
Pin Outs
Revision 1.0
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MT6228 GSM/GPRS Baseband Processor Data Sheet
One type of package for this product, TFBGA 13mm*13mm, 314-ball, 0.65 mm pitch Package, is offered.
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Pin-outs and the top view are illustrated in Figure 3 for this package. Outline and dimension of package is illustrated in
Figure 4, while the definition of package is shown in Table 1.
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MT6228 GSM/GPRS Baseband Processor Data Sheet
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
A
AVDD_
PLL
TVOUT
VSS33
AFC_B
YP
AUXA
DIN6
AUXA
DIN3
AVDD_
RFE
BUPAI
N
BDLAI
N
AU_VI
N1_P
AGND
_AFE
AU_O
UT0_P
AVSS_
BUF
AU_F
MINR
AU_M
OUTR
VSS33
GPIO9
GPIO8
GPIO6
A
B
SYSCL
K
AVDD_
TV
VDD33
AFC
AUXA
DIN5
AUXA
DIN2
APC
BUPAI
P
BDLAI
P
AU_VI
N1_N
AU_VR
EF_P
AU_O
UT0_N
AVDD_
BUF
AU_F
MINL
AU_M
OUTL
VSS33
MFIQ
GPIO7
VDD33
B
C
AVSS_
PLL
FRES
AVSS_
TV
AUX_R
EF
AUXA
DIN4
AUXA
DIN1
AVSS_
RFE
BUPA
QN
BDLA
QN
AU_VI
N0_N
AU_VR
EF_N
AU_MI
CBIAS
_P
AU_O
UT1_N
AU_M_
BYP
AVDD_
MBUF
NC
GPIO5
GPIO4
GPIO3
C
D
XIN
XOUT
AVDD_
RTC
VDD33
VSS33
AUXA
DIN0
AVDD_
GSMR
FTX
BUPA
QP
BDLA
QP
AU_VI
N0_P
AVDD_
AFE
AU_MI
CBIAS
_N
AU_O
UT1_P
AVSS_
MBUF
ESDM
_CK
DAIPC
MIN
GPIO2
DAISY
NC
DAIRS
T
D
E
BBWA
KEUP
VSS33
VDDK
JTRST
#
TESTM
ODE
VDD33
VSS33
AVSS_
GSMR
FTX
AGND
_RFE
AVSS_
AFE
VDD33
VSS33
VDD33
VSS33
VDD33
F
JRTCK
JTDO
JTMS
JTDI
JTCK
PLLOU
T
VDD33
VSS33
VDDK
G
BPI_B
US3
VDD33
BPI_B
US2
BPI_B
US1
BPI_B
US0
H
VSS33
BPI_B
US8
BPI_B
US7
BPI_B
US6
BPI_B
US5
J
LSCK
BSI_C
LK
BSI_D
ATA
BSI_C
S0
BPI_B
US9
K
VDD33
LSCE1
#
LSCE0
#
LSDA
L
LWR#
LPA0
LRD#
M
VSS33
VDDK
N
NRNB
P
KROW
4
KCOL3
CMDA
T9
CMPC
LK
CMMC
LK
BPI_B
US4
CMDA
T8
NLD16
NLD14
LSA0
LPCE1
#
CMDA
T7
NLD15
NLD12
LRST#
LPCE0
#
NLD7
CMDA
T6
NLD13
NLD10
NLD4
NLD5
NLD6
CMDA
T5
CMDA
T4
CMDA
T3
NLD0
NLD1
NLD2
NLD3
KROW
0
DAICL
K
DAIPC
MOUT
E
KROW
3
KROW
2
VDDK
VSS33
F
KCOL2
KCOL1
KCOL0
KROW
5
G
CMHR
EF
CMVR
EF
IRDA_
TXD
IRDA_
PDN
KCOL6
KCOL5
KCOL4
H
NLD11
CMRS
T
UTXD2
URXD3
UTXD3
VDD33
IRDA_
RXD
J
NLD9
CMPD
N
URXD1
UTXD1
UCTS1
URTS1
URXD2
K
NLD8
CMDA
T0
VSS33
SIMCL
K
SIMVC
C
SIMSE
L
SIMDA
TA
L
CMDA
T2
CMDA
T1
MCWP
MCINS
MCCK
SIMRS
T
M
VDD33
_AUX1
MCDA
2
MCDA
3
MCPW
RON
N
NCE#
NRE#
NWE#
NALE
NCLE
VDDK
VDD33
_AUX2
MCCM
0
MCDA
0
MCDA
1
P
R
VDD33
ALERT
ER
PWM2
PWM1
EA19
VSS33
_EMI
EA12
EA8
EA4
VDD33
_EMI
ECS3#
VSS33
_EMI
ECKE
EWAIT
ED0
WATC
HDOG
VSS33
_EMI
USB_D
P
USB_D
M
R
T
SRCL
KENA
N
SYSRS
T#
SRCL
KENAI
SRCL
KENA
EA20
EA16
VDD33
_EMI
EA9
EA5
EA1
EPDN#
EWR#
EDCL
K
ECAS#
ED13
ED10
VDD33
_EMI
ED2
ED1
T
U
GPIO1
EINT0
GPIO0
MIRQ
EA21
EA17
EA13
VSS33
_EMI
EA6
EA2
VSS33
_EMI
ECS0#
VDD33
_EMI
VSS33
_EMI
ED14
ED11
ED8
ED4
ED3
U
V
EINT1
EINT3
VDD33
_EMI
EA24
EA22
VDD33
_EMI
EA14
VDDK
EA7
VSS33
_EMI
ECLK
ECS1#
ELB#
VDDK
VDD33
_EMI
ED12
VDD33
_EMI
VSS33
_EMI
ED5
V
W
EINT2
VSS33
_EMI
EA25
EA23
VSS33
_EMI
EA18
EA15
EA10
VDD33
_EMI
EA3
EADV#
VDD33
_EMI
EUB#
ERAS#
ED15
VSS33
_EMI
ED9
ED7
ED6
W
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
MT6228 TFBGA Top-View
EA0
ECS2#
ERD#
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EA11
KROW
1
Re
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NLD17
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1
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Figure 3 Top View of MT6228 TFBGA 13mm*13mm, 314-ball, 0.65 mm pitch Package
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MT6228 GSM/GPRS Baseband Processor Data Sheet
Figure 4 Outlines and Dimension of TFBGA 13mm*13mm, 314-ball, 0.65 mm pitch Package
Ball Count
Ball Pitch
Ball Dia.
D
E
N
E
B
13
13
314
0.65
0.35
Package Thk.
Stand Off
Substrate
Thk.
A (Max.)
A1
C
1.2
0.3
0.36
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Body Size
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Table 1 Definition of TFBGA 13mm*13mm, 314-ball, 0.65 mm pitch Package (Unit: mm)
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Top Marking Definition
S
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MT6228T
DDDD-###
LLLLL
KKKKK
MT6228T: Part No.
DDDD:
Date Code
###:
Subcontractor Code
LLLLL: U1 Die Lot No.
KKKKK: U2 Die Lot No.
S:
Special Code
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2.3
2.3.1
DC Characteristics
Absolute Maximum Ratings
Revision 1.0
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MT6228 GSM/GPRS Baseband Processor Data Sheet
Prolonged exposure to absolute maximum ratings may reduce device reliability. Functional operation at these
maximum ratings is not implied.
Symbol
Min
Max
Unit
IO power supply
VDD33
-0.3
VDD33+0.3
V
I/O input voltage
VDD33I
-0.3
VDD33+0.3
V
Operating temperature
Topr
-20
80
Celsius
Storage temperature
Tstg
-55
125
Celsius
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Item
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2.4
Revision 1.0
Pin Description
Ball
Name
13X13
Dir Description
Mode0
Mode1
Mode2
Mode3
JTAG Port
E4
F5
F4
F3
F2
F1
JTRST#
JTCK
JTDI
JTMS
JTDO
JRTCK
I
I
I
I
O
O
JTAG test port reset input
JTAG test port clock input
JTAG test port data input
JTAG test port mode switch
JTAG test port data output
JTAG test port returned clock output
G5
G4
G3
G1
J6
H5
H4
H3
H2
J5
BPI_BUS0
BPI_BUS1
BPI_BUS2
BPI_BUS3
BPI_BUS4
BPI_BUS5
BPI_BUS6
BPI_BUS7
BPI_BUS8
BPI_BUS9
O
O
O
O
O
O
IO
IO
IO
IO
RF hard-wire control bus 0
RF hard-wire control bus 1
RF hard-wire control bus 2
RF hard-wire control bus 3
RF hard-wire control bus 4
RF hard-wire control bus 5
RF hard-wire control bus 6
RF hard-wire control bus 7
RF hard-wire control bus 4
RF hard-wire control bus 5
J4
J3
J2
BSI_CS0
BSI_DATA
BSI_CLK
O
O
O
RF 3-wire interface chip select 0
RF 3-wire interface data output
RF 3-wire interface clock output
R4
PWM1
IO
Pulse width modulated signal 1
GPIO32
PWM1
TBTXFS
R3
PWM2
IO
Pulse width modulated signal 2
GPIO33
PWM2
TBRXEN
R2
ALERTER
IO
Pulse width modulated signal for
buzzer
GPIO34
ALERTER TBRXFS
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MT6228 GSM/GPRS Baseband Processor Data Sheet
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PD
PU
PU
PU
Re
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RF Parallel Control Unit
GPIO16
GPIO17
GPIO18
GPIO19
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RF Serial Control Unit
PU/ Rese
PD t
BPI_BUS6
BPI_BUS7 13MHz
BPI_BUS8 6.5MHz
BPI_BUS9 BSI_CS1
26MHz
32KHz
BFEPRB
O
PD
PD
PD
PD
Input
Input
Input
Input
0
0
0
0
0
0
0
0
Input
Input
Input
Input
0
0
0
PWM Interface
DSP_TID
2
DSP_TID
3
DSP_TID
4
PD
Input
PD
Input
PD
Input
PU
Input
Serial LCD/PM IC Interface
J1
LSCK
K5
LSA0
K4
K3
LSDA
LSCE0#
K2
LSCE1#
IO
Serial display interface data output
GPIO20
LSCK
IO
Serial display interface address
output
Serial display interface clock output
Serial display interface chip select 0
output
Serial display interface chip select 1
output
GPIO21
LSA0
TDMA_C TBTXEN
K
TDMA_D1 TDTIRQ
PU
Input
GPIO22
GPIO23
LSDA
LSCE0#
TDMA_D0 TCTIRQ2 PU
TDMA_FS TCTIRQ1 PU
Input
Input
GPIO24
LSCE1#
LPCE2#
TEVTVA
L
PU
Input
Parallel display interface chip select 1 GPIO25
output
Parallel display interface chip select 0
output
Parallel display interface Reset Signal
Parallel display interface Read Strobe
LPCE1#
NCE1#
DSP_TID
0
PU
Input
IO
IO
IO
Parallel LCD/NAND-Flash
Interface
LPCE1#
IO
MT
K
K6
L5
LPCE0#
O
L4
L3
LRST#
LRD#
O
O
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L2
LPA0
O
L1
LWR#
O
G7
NLD17
J9
K9
J10
L9
IO
Parallel display interface address
output
Parallel display interface Write
Strobe
Parallel LCD/NAND-Flash Data 17
GPIO11
NLD17
MCDA4
NLD16
NLD15
NLD14
NDL13
IO
IO
IO
IO
Parallel LCD/NAND-Flash Data 16
Parallel LCD/NAND-Flash Data 15
Parallel LCD/NAND-Flash Data 14
Parallel LCD/NAND-Flash Data 13
GPIO10
NLD15
NLD14
NLD13
NLD16
GPIO61
GPIO60
GPIO59
MCDA5
K10
NLD12
IO
Parallel LCD/NAND-Flash Data 12
NLD12
GPIO58
J11
NLD11
IO
Parallel LCD/NAND-Flash Data 11
NLD11
GPIO57
L10
NLD10
IO
Parallel LCD/NAND-Flash Data 10
NLD10
GPIO56
K11
NLD9
IO
Parallel LCD/NAND-Flash Data 9
L11
NLD8
IO
Parallel LCD/NAND-Flash Data 8
L6
M5
M4
M3
N5
N4
N3
N2
N1
NLD7
NLD6
NLD5
NLD4
NLD3
NLD2
NLD1
NLD0
NRNB
IO
IO
IO
IO
IO
IO
IO
IO
IO
Parallel LCD/NAND-Flash Data 7
Parallel LCD/NAND-Flash Data 6
Parallel LCD/NAND-Flash Data 5
Parallel LCD/NAND-Flash Data 4
Parallel LCD/NAND-Flash Data 3
Parallel LCD/NAND-Flash Data 2
Parallel LCD/NAND-Flash Data 1
Parallel LCD/NAND-Flash Data 0
NAND-Flash Read/Busy Flag
P5
NCLE
P4
NALE
P3
P2
NWE#
NRE#
P1
NCE#
M19
L16
L17
L18
L19
SIMRST
SIMCLK
SIMVCC
SIMSEL
SIMDATA
U3
GPIO0
U1
D17
C19
C18
GPIO1
GPIO2
GPIO3
GPIO4
C17
A19
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1
1
GPIO55
NLD8
GPIO54
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NRNB
GPIO26
IO
NAND-Flash Command Latch Signal NCLE
GPIO27
IO
NAND-Flash Address Latch Signal
NALE
GPIO28
IO
IO
NAND-Flash Write Strobe
NAND-Flash Read Strobe
NWE#
NRE#
GPIO29
GPIO30
IO
NAND-Flash Chip select output
NCE#
GPIO31
O
O
O
O
IO
SIM card reset output
SIM card clock output
SIM card supply power control
SIM card supply power select
SIM card data input/output
IO
Input
PD
PD
PD
PD
Input
Input
Input
Input
PD
Input
PD
Input
PD
Input
PD
Input
PD
Input
PD
PD
PD
PD
PD
PD
PD
PD
USBSESS SWDBGD PU
VLD
2
USBVBUS SWDBGD PD
VLD
1
USBSESS SWDBGD PD
END
0
PU
USBVBUS SWDBGC PU
DSC
K
PU
Input
Input
Input
Input
Input
Input
Input
Input
Re
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NLD9
PD
fo
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DSP_TID
1
DID
DIMS
DICK
SWDBGP
KT
SWDBG
WR
SWDBGR
D
SWDBGR
OE
SWDBGA
0
SWDBGA
1
SIM Card Interface
GPIO48
SIMSEL
General purpose input/output 0
GPIO0
IO
IO
IO
IO
General purpose input/output 1
General purpose input/output 2
General purpose input/output 3
General purpose input/output 4
GPIO1
GPIO2
GPIO3
GPIO4
CMFLAS
H
BSI_RFIN
SCL
SDA
EDICK
URXD2
GPIO5
IO
General purpose input/output 5
GPIO5
EDIWS
GPIO6
IO
General purpose input/output 6
GPIO6
EDIDAT
PD
0
0
0
Input
0
MT
K
Dedicated GPIO Interface
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DSP_TID
5
PD
Input
PD
PU
PU
Input
Input
Input
SWDBGD
7
SWDBGD
6
SWDBGD
MediaTek Inc. Confidential
B18
GPIO7
IO
General purpose input/output 7
GPIO7
A18
GPIO8
IO
General purpose input/output 19
GPIO8
32KHz
A17
GPIO9
IO
General purpose input/output 21
GPIO9
26MHz
USBVBUS
ON
USBVBUS
CHG
13MHz
5
SWDBGD
4
SWDBGF
SWDBGE
Miscellaneous
I
O
System reset input active low
Watchdog reset output
O
T4
SYSRST#
WATCHDO
G#
SRCLKENA
N
SRCLKENA
T3
SRCLKENAI
IO
External TCXO enable output active
low
External TCXO enable output active
high
External TCXO enable input
E5
D15
TESTMODE I
O
ESDM_CK
TESTMODE enable input
Internal Monitor Clock
H17
H18
H19
G15
G16
G17
G18
G19
F15
F16
KCOL6
KCOL5
KCOL4
KCOL3
KCOL2
KCOL1
KCOL0
KROW5
KROW4
KROW3
Keypad column 6
Keypad column 5
Keypad column 4
Keypad column 3
Keypad column 2
Keypad column 1
Keypad column 0
Keypad row 5
Keypad row 4
Keypad row 3
F17
E16
E17
KROW2
KROW1
KROW0
U2
V1
W1
V2
U4
B17
EINT0
EINT1
EINT2
EINT3
MIRQ
MFIQ
R15
T19
T18
U19
U18
V19
W19
W18
U17
W17
T16
U16
ED0
ED1
ED2
ED3
ED4
ED5
ED6
ED7
ED8
ED9
ED10
ED11
O
Keypad Interface
GPO0
GPIO31
O
O
O
Keypad row 2
Keypad row 1
Keypad row 0
I
I
I
I
I
I
External interrupt 0
External interrupt 1
External interrupt 2
External interrupt 3
Interrupt to MCU
Interrupt to MCU
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
External memory data bus 0
External memory data bus 1
External memory data bus 2
External memory data bus 3
External memory data bus 4
External memory data bus 5
External memory data bus 6
External memory data bus 7
External memory data bus 8
External memory data bus 9
External memory data bus 10
External memory data bus 11
SRCLKE
NAN
SRCLKE
NA
SRCLKEN
AI
KROW5 GPIO44
KROW4 GPIO45
KROW3 GPIO46
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I
I
I
I
I
I
I
O
O
O
GPO1
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T1
Input
1
Re
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T2
R16
Revision 1.0
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MT6228 GSM/GPRS Baseband Processor Data Sheet
KROW2 GPIO47
0
1
PD
Input
PD
Input
PU
PU
PU
PU
PU
PU
PU
Input
Input
Input
Input
Input
Input
Input
0
0
0
ARM CK
AHB CK
FTV CK
TV CK
DSP CK
SLOW
CK
FMCU CK FUSB CK
0
0
0
External Interrupt Interface
GPIO36
GPIO63
MIRQ
MFIQ
6.5MHz
USBID
PU
PU
PU
PU
32KHz
PU
SWDBGD PU
3
Input
Input
Input
Input
Input
Input
MT
K
External Memory Interface
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Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
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T14
W14
R13
T13
V13
W13
T11
W11
ECAS#
ERAS#
ECKE
EDCLK
ELB#
EUB#
EPDN#
EADV#
O
O
O
O
O
O
O
O
V11
ECLK
O
P10
T10
U10
W10
R9
T9
U9
V9
R8
T8
W8
P8
R7
U7
V7
W7
T6
U6
W6
R5
T5
U5
V5
W4
V4
W3
EA0
EA1
EA2
EA3
EA4
EA5
EA6
EA7
EA8
EA9
EA10
EA11
EA12
EA13
EA14
EA15
EA16
EA17
EA18
EA19
EA20
EA21
EA22
EA23
EA24
EA25
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
External memory data bus 12
External memory data bus 13
External memory data bus 14
External memory data bus 15
External memory read strobe
External memory write strobe
External memory chip select 0
External memory chip select 1
External memory chip select 2
External memory chip select 3
Flash, PSRAM and CellularRAM
data ready
MobileRAM column address
MobileRAM row address
MobileRAM clock enable
MobileRAM clock
External memory lower byte strobe
External memory upper byte strobe
PSRAM power down control
Flash, PSRAM and CellularRAM
address valid
Flash, PSRAM and CellularRAM
clock
External memory address bus 0
External memory address bus 1
External memory address bus 2
External memory address bus 3
External memory address bus 4
External memory address bus 5
External memory address bus 6
External memory address bus 7
External memory address bus 8
External memory address bus 9
External memory address bus 10
External memory address bus 11
External memory address bus 12
External memory address bus 13
External memory address bus 14
External memory address bus 15
External memory address bus 16
External memory address bus 17
External memory address bus 18
External memory address bus 19
External memory address bus 20
External memory address bus 21
External memory address bus 22
External memory address bus 23
External memory address bus 24
External memory address bus 25
R18
R19
USB_DP
USB_DM
IO
IO
USB D+ Input/Output
USB D- Input/Output
MT
K
Ko
nk
a
IO
IO
IO
IO
O
O
O
O
O
O
O
PU
Re
lea
se
ED12
ED13
ED14
ED15
ERD#
EWR#
ECS0#
ECS1#
ECS2#
ECS3#
EWAIT
GPO2
Co
nf
id
en
tia
l
V16
T15
U15
W15
P12
T12
U12
V12
P11
R11
R14
Revision 1.0
fo
r
MT6228 GSM/GPRS Baseband Processor Data Sheet
EPDN#
26Mhz
13MHz
Input
Input
Input
Input
1
1
1
1
1
1
Input
1
1
1
1
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
USB Interface
Memory Card Interface
25/616
MediaTek Inc. Confidential
MCCM0
IO
SD Command/MS Bus State Output
P18
MCDA0
IO
P19
MCDA1
IO
SD Serial Data IO 0/MS Serial Data
IO
SD Serial Data IO 1
N17
MCDA2
IO
SD Serial Data IO 2
N18
MCDA3
IO
SD Serial Data IO 3
M18
MCCK
O
N19
M16
MCPWRON
MCWP
O
I
SD Serial Clock/MS Serial Clock
Output
SD Power On Control Output
SD Write Protect Input
M17
MCINS
I
SD Card Detect Input
PU/
PD
PU/
PD
PU/
PD
PU/
PD
PU/
PD
Re
lea
se
fo
r
P17
Revision 1.0
Ko
nk
a
MT6228 GSM/GPRS Baseband Processor Data Sheet
UART/IrDA Interface
K15
K16
K17
K18
K19
J15
J16
J17
URXD1
UTXD1
UCTS1
URTS1
URXD2
UTXD2
URXD3
UTXD3
I
O
I
O
IO
IO
IO
IO
UART 1 receive data
UART 1 transmit data
UART 1 clear to send
UART 1 request to send
UART 2 receive data
UART 2 transmit data
UART 3 receive data
UART 3 transmit data
J19
IRDA_RXD
IO
IrDA receive data
H15
IRDA_TXD
IO
IrDA transmit data
H16
IRDA_PDN
IO
IrDA Power Down Control
E18
DAICLK
IO
DAI clock output
GPIO49
DAICLK
E19
DAIPCMOUT IO
DAI pcm data out
GPIO50
D16
DAIPCMIN
IO
DAI pcm data input
GPIO51
D19
D18
DAIRST
DAISYNC
IO
IO
DAI reset signal input
DAI frame synchronization signal
output
GPIO52
GPIO53
DAIPCMO
UT
DAIPCMI
N
DAIRST
DAISYNC
J12
K12
H12
H11
CMRST
CMPDN
CMVREF
CMHREF
IO
IO
I
I
GPIO12
GPIO13
CMRST
CMPDN
H9
H10
H8
CMPCLK
CMMCLK
CMDAT9
I
O
I
CMOS sensor reset signal output
CMOS sensor power down control
Sensor vertical reference signal input
Sensor horizontal reference signal
input
CMOS sensor pixel clock input
CMOS sensor master clock output
CMOS sensor data input 9
J8
CMDAT8
I
CMOS sensor data input 8
K8
CMDAT7
I
CMOS sensor data input 7
GPIO37
GPIO38
GPIO39
GPIO40
URXD2
UTXD2
URXD3
UTXD3
UCTS3
URTS3
GPIO41
IRDA_RX
D
IRDA_TX
D
IRDA_PD
N
UCTS2
Co
nf
id
en
tia
l
GPIO42
GPIO43
URTS2
PU/ Input
PD
PU/ Input
PD
PU
PU
PU
PU
PU
PU
DSP_TID
6
SWDBGD PU
15
SWDBG1 PU
4
SWDBG1 PU
3
Input
1
Input
1
Input
Input
Input
Input
Input
Input
Input
Digital Audio Interface
SWDBGD
12
SWDBGD
11
SWDBGD
10
SWDBG9
SWDBG8
PU
Input
PD
Input
PU
Input
PU
PU
Input
Input
PD
PD
PD
PD
Input
Input
Input
Input
PD
MT
K
CMOS Sensor Interface
CMDAT
9
CMDAT
8
CMDAT
26/616
GPIO74
PD
Input
0
Input
GPIO73
PD
Input
GPIO72
PD
Input
MediaTek Inc. Confidential
CMDAT6
I
CMOS sensor data input 6
M8
CMDAT5
I
CMOS sensor data input 5
M9
CMDAT4
I
CMOS sensor data input 4
M10
CMDAT3
I
CMOS sensor data input 3
M11
CMDAT2
I
CMOS sensor data input 2
M12
L12
CMDAT1
CMDAT0
IO
IO
CMOS sensor data input 1
CMOS sensor data input 0
B15
A15
C14
B14
A14
D13
C13
B12
A12
C12
C11
B11
D10
C10
B10
A10
D9
AU_MOUL
AU_MOUR
AU_M_BYP
AU_FMINL
AU_FMINR
AU_OUT1_P
AU_OUT1_N
AU_OUT0_N
AU_OUT0_P
AU_MICBIA
S_P
AU_MICBIA
S_N
AU_VREF_N
AU_VREF_P
AU_VIN0_P
AU_VIN0_N
AU_VIN1_N
AU_VIN1_P
BDLAQP
C9
BDLAQN
A9
BDLAIN
B9
BDLAIP
B8
BUPAIP
A8
BUPAIN
C8
BUPAQN
D8
BUPAQP
B7
D6
C6
B6
A6
C5
B5
APC
AUXADIN0
AUXADIN1
AUXADIN2
AUXADIN3
AUXADIN4
AUXADIN5
7
CMDAT
6
CMDAT
5
CMDAT
4
CMDAT
3
CMDAT
2
GPIO50
GPIO51
Microphone bias supply (-)
Audio reference voltage (-)
Audio reference voltage (+)
Microphone 0 amplifier input (+)
Microphone 0 amplifier input (-)
Microphone 1 amplifier input (-)
Microphone 1 amplifier input (+)
Quadrature input (Q+) baseband
codec downlink
Quadrature input (Q-) baseband
codec downlink
In-phase input (I+) baseband codec
downlink
In-phase input (I-) baseband codec
downlink
In-phase output (I+) baseband codec
uplink
In-phase output (I-) baseband codec
uplink
Quadrature output (Q+) baseband
codec uplink
Quadrature output (Q-) baseband
codec uplink
Automatic power control DAC output
Auxiliary ADC input 0
Auxiliary ADC input 1
Auxiliary ADC input 2
Auxiliary ADC input 3
Auxiliary ADC input 4
Auxiliary ADC input 5
GPIO69
GPIO68
GPIO62
CMDAT1
CMDAT0
Input
PD
Input
PD
Input
PD
Input
PD
Input
PD
PD
Input
Input
Co
nf
id
en
tia
l
MT
K
D12
GPIO70
PD
Re
lea
se
Analog Interface
Audio analog output left channel
Audio analog output right channel
Audio DAC bypass pin
FM radio analog input left channel
FM radio analog input right channel
Earphone 1 amplifier output (+)
Earphone 1 amplifier output (-)
Earphone 0 amplifier output (-)
Earphone 0 amplifier output (+)
Microphone bias supply (+)
GPIO71
fo
r
L8
Revision 1.0
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nk
a
MT6228 GSM/GPRS Baseband Processor Data Sheet
27/616
MediaTek Inc. Confidential
A5
C4
AUXADIN6
AUX_REF
B4
AFC
A4
AFC_BYP
B1
F6
SYSCLK
PLLOUT
Auxiliary ADC input 6
Auxiliary ADC reference voltage
input
Automatic frequency control DAC
output
Automatic frequency control DAC
bypass capacitance
VCXO Interface
fo
r
13MHz or 26MHz system clock input
PLL reference voltage output
XIN
XOUT
BBWAKEUP O
A2
C2
TVOUT
FSRES
E3
M2
V8
V14
F18
F11
V3
VDDK
VDDK
VDDK
VDDK
VDDK
VDDK
VDD33_EMI
V6
VDD33_EMI
T7
VDD33_EMI
W9
VDD33_EMI
R10
VDD33_EMI
W12
VDD33_EMI
U13
VDD33_EMI
V15
VDD33_EMI
T17
VDD33_EMI
V17
VDD33_EMI
W5
R6
U8
V10
U11
R12
U14
W16
R17
V18
VSS33_EMI
VSS33_EMI
VSS33_EMI
VSS33_EMI
VSS33_EMI
VSS33_EMI
VSS33_EMI
VSS33_EMI
VSS33_EMI
VSS33_EMI
32.768 KHz crystal input
32.768 KHz crystal output
Baseband power on/off control
TV Interface
TV DAC Output
Supply Voltages
MT
K
Co
nf
id
en
tia
l
Supply voltage of internal logic
Supply voltage of internal logic
Supply voltage of internal logic
Supply voltage of internal logic
Supply voltage of internal logic
Supply voltage of internal logic
Supply voltage of memory interface
driver
Supply voltage of memory interface
driver
Supply voltage of memory interface
driver
Supply voltage of memory interface
driver
Supply voltage of memory interface
driver
Supply voltage of memory interface
driver
Supply voltage of memory interface
driver
Supply voltage of memory interface
driver
Supply voltage of memory interface
driver
Supply voltage of memory interface
driver
Ground of memory interface driver
Ground of memory interface driver
Ground of memory interface driver
Ground of memory interface driver
Ground of memory interface driver
Ground of memory interface driver
Ground of memory interface driver
Ground of memory interface driver
Ground of memory interface driver
Ground of memory interface driver
1
Re
lea
se
RTC Interface
D1
D2
E1
Revision 1.0
Ko
nk
a
MT6228 GSM/GPRS Baseband Processor Data Sheet
28/616
MediaTek Inc. Confidential
R1
VDD33
J18
VDD33
B19
VDD33
E15
VDD33
E13
VDD33
E11
VDD33
F9
VDD33
E6
VDD33
D4
VDD33
B3
VDD33
W2
VSS33
E2
VSS33
H1
VSS33
M1
VSS33
L15
VSS33
F19
VSS33
B16
VSS33
A16
VSS33
E14
VSS33
E12
VSS33
Supply voltage of drivers except
memory interface, USB and
MS/MMC/SD
Supply voltage of drivers except
memory interface, USB and
MS/MMC/SD
Supply voltage of drivers except
memory interface, USB and
MS/MMC/SD
Supply voltage of drivers except
memory interface, USB and
MS/MMC/SD
Supply voltage of drivers except
memory interface, USB and
MS/MMC/SD
Supply voltage of drivers except
memory interface, USB and
MS/MMC/SD
Supply voltage of drivers except
memory interface, USB and
MS/MMC/SD
Supply voltage of drivers except
memory interface, USB and
MS/MMC/SD
Supply voltage of drivers except
memory interface, USB and
MS/MMC/SD
Supply voltage of drivers except
memory interface, USB and
MS/MMC/SD
Supply voltage of drivers except
memory interface, USB and
MS/MMC/SD
Supply voltage of drivers except
memory interface, USB and
MS/MMC/SD
Ground of drivers except memory
interface, USB and MS/MMC/SD
Ground of drivers except memory
interface, USB and MS/MMC/SD
Ground of drivers except memory
interface, USB and MS/MMC/SD
Ground of drivers except memory
interface, USB and MS/MMC/SD
Ground of drivers except memory
interface, USB and MS/MMC/SD
Ground of drivers except memory
interface, USB and MS/MMC/SD
Ground of drivers except memory
interface, USB and MS/MMC/SD
Ground of drivers except memory
interface, USB and MS/MMC/SD
Ground of drivers except memory
interface, USB and MS/MMC/SD
Ground of drivers except memory
interface, USB and MS/MMC/SD
fo
r
VDD33
Supply Voltage of MS/MMC/SD
Re
lea
se
K1
MT
K
N16
Supply voltage of drivers for USB
Co
nf
id
en
tia
l
G2
VDD33_AUX
2
VDD33_AUX
1
VDD33
P16
Revision 1.0
Ko
nk
a
MT6228 GSM/GPRS Baseband Processor Data Sheet
29/616
MediaTek Inc. Confidential
VSS33
E7
VSS33
D5
VSS33
A3
VSS33
A1
C1
B2
C3
D3
AVDD_PLL
AVSS_PLL
AVDD_TV
AVSS_TV
AVDD_RTC
Ground of drivers except memory
interface, USB and MS/MMC/SD
Ground of drivers except memory
interface, USB and MS/MMC/SD
Ground of drivers except memory
interface, USB and MS/MMC/SD
Ground of drivers except memory
interface, USB and MS/MMC/SD
Supply voltage for PLL
Ground for PLL supply
Supply voltage for TV out
Ground for TV out
Supply voltage for Real Time Clock
fo
r
F10
A13
D11
AVSS_BUF
AVDD_AFE
A11
AGND_AFE
E10
E9
AVSS_AFE
AGND_RFE
E8
C7
AVSS_GSMR
FTX
AVDD_GSM
RFTX
AVSS_RFE
A7
AVDD_RFE
D7
Supply Voltage for Audio band
section
GND for Audio band section
Supply voltage for voice band
transmit section
GND for voice band transmit section
Supply voltage for voice band receive
section
GND reference voltage for voice
band section
GND for voice band receive section
GND reference voltage for baseband
section, APC, AFC and AUXADC
GND for baseband transmit section
Supply voltage for baseband transmit
section
GND for baseband receive section,
APC, AFC and AUXADC
Supply voltage for baseband receive
section, APC, AFC and AUXADC
Co
nf
id
en
tia
l
D14
B13
AVDD_MBU
F
AVSS_MBUF
AVDD_BUF
Re
lea
se
Analog Supplies
C15
Revision 1.0
Ko
nk
a
MT6228 GSM/GPRS Baseband Processor Data Sheet
MT
K
Table 2 Pin Descriptions (Bolded types are functions at reset)
30/616
MediaTek Inc. Confidential
IO Supply
VSS33
VDD33
VSS33
VDD33
VSS33
VDD33
VDDK
VSS33
VDD33
VSS33
VDD33
VSS33
CMRST
CMPDN
CMVREF
CMHREF
CMPCLK
CMMCLK
VDD33
CMDAT9
CMDAT8
CMDAT7
CMDAT6
CMDAT5
VSS33
CMDAT4
CMDAT3
CMDAT2
CMDAT1
CMDAT0
VDD33
AVDD_TV
TVOUT
FSRES
AVSS_TV
AVDD_PLL
SYSCLK
PLLOUT
AVSS_PLL
AVDD_RTC
XOUT
XIN
BBWAKEUP
VSS33
TESTMODE
VDDK
JTRST#
JTCK
MT
K
A16
E15
E14
E13
E12
E11
F11
F10
F9
E7
E6
D5
J12
K12
H12
H11
H9
H10
D4
H8
J8
K8
L8
M8
A3
M9
M10
M11
M12
L12
B3
B2
A2
C2
C3
A1
B1
F6
C1
D3
D2
D1
E1
E2
E5
E3
E4
F5
Name
IO GND
Core Supply
Core GND
Remark
Typ. 2.8V
Typ. 2.8V
fo
r
13X13
Typ. 2.8V
Typ. 1.2V
Typ. 2.8V
Typ. 2.8V
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VSS33
VSS33
VSS33
VSS33
VSS33
VSS33
VDD33
VDD33
VDD33
VDD33
VDD33
VSS33
VSS33
VSS33
VSS33
VSS33
VDD33
VDD33
VDD33
VDD33
VDD33
VSS33
VSS33
VSS33
VSS33
VSS33
Re
lea
se
Ball
Power Description
VDDK
VDDK
VDDK
VDDK
VDDK
VDDK
VSSK
VSSK
VSSK
VSSK
VSSK
VSSK
VDDK
VDDK
VDDK
VDDK
VDDK
VSSK
VSSK
VSSK
VSSK
VSSK
VDDK
VDDK
VDDK
VDDK
VDDK
VSSK
VSSK
VSSK
VSSK
VSSK
Typ. 2.8V
Co
nf
id
en
tia
l
2.5
Revision 1.0
Ko
nk
a
MT6228 GSM/GPRS Baseband Processor Data Sheet
Typ. 2.8V
Typ. 2.8V
AVDD_TV
AVDD_TV
AVSS_TV
AVSS_TV
AVDD_TV
AVDD_TV
AVSS_TV
AVSS_TV
AVDD_PLL
AVDD_PLL
AVSS_PLL
AVSS_PLL
AVDD_PLL
AVDD_PLL
AVSS_PLL
AVSS_PLL
Typ. 2.8V
Typ. 1.2V
AVDD_RTC
AVDD_RTC
AVDD_RTC
VSS33
VSS33
VSS33
AVDD_RTC
AVDD_RTC
AVDD_RTC
VSS33
VSS33
VSS33
VDD33
VSS33
VDDK
VSSK
VDD33
VDD33
VSS33
VSS33
VDDK
VDDK
VSSK
VSSK
Typ. 1.2V
31/616
MediaTek Inc. Confidential
F4
F3
F2
F1
G5
G4
G2
G3
G1
J6
H5
H4
H3
H2
H1
J5
J4
J3
J2
J1
K5
K4
K3
K2
K1
K6
L5
L4
L3
L2
L1
L6
M5
M4
M1
M2
M3
N5
N4
N3
N2
N1
P5
P4
P3
P2
P1
R1
JTDI
JTMS
JTDO
JRTCK
BPI_BUS0
BPI_BUS1
VDD33
BPI_BUS2
BPI_BUS3
BPI_BUS4
BPI_BUS5
BPI_BUS6
BPI_BUS7
BPI_BUS8
VSS33
BPI_BUS9
BSI_CS0
BSI_DATA
BSI_CLK
LSCK
LSA0
LSDA
LSCE0#
LSCE1#
VDD33
LPCE1#
LPCE0#
LRST#
LRD#
LPA0
LWR#
NLD7
NLD6
NLD5
VSS33
VDDK
NLD4
NLD3
NLD2
NLD1
NLD0
NRNB
NCLE
NALE
NWE#
NRE#
NCE#
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VSS33
VSS33
VSS33
VSS33
VSS33
VSS33
VDDK
VDDK
VDDK
VDDK
VDDK
VDDK
VSSK
VSSK
VSSK
VSSK
VSSK
VSSK
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VSS33
VSS33
VSS33
VSS33
VSS33
VSS33
VSS33
VDDK
VDDK
VDDK
VDDK
VDDK
VDDK
VDDK
VSSK
VSSK
VSSK
VSSK
VSSK
VSSK
VSSK
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VSS33
VSS33
VSS33
VSS33
VSS33
VSS33
VSS33
VSS33
VSS33
VDDK
VDDK
VDDK
VDDK
VDDK
VDDK
VDDK
VDDK
VDDK
VSSK
VSSK
VSSK
VSSK
VSSK
VSSK
VSSK
VSSK
VSSK
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VSS33
VSS33
VSS33
VSS33
VSS33
VSS33
VSS33
VSS33
VSS33
VDDK
VDDK
VDDK
VDDK
VDDK
VDDK
VDDK
VDDK
VDDK
VSSK
VSSK
VSSK
VSSK
VSSK
VSSK
VSSK
VSSK
VSSK
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VSS33
VSS33
VSS33
VSS33
VSS33
VSS33
VSS33
VSS33
VSS33
VSS33
VSS33
VDDK
VDDK
VDDK
VDDK
VDDK
VDDK
VDDK
VDDK
VDDK
VDDK
VDDK
VSSK
VSSK
VSSK
VSSK
VSSK
VSSK
VSSK
VSSK
VSSK
VSSK
VSSK
R4
PWM1
VDD33
VSS33
VDDK
VSSK
R3
PWM2
VDD33
VSS33
VDDK
VSSK
R2
ALERTER
VDD33
VSS33
VDDK
VSSK
T4
SRCLKENA
VDD33
VSS33
VDDK
VSSK
Re
lea
se
fo
r
Typ. 2.8V
Typ. 2.8V
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Typ. 1.2V
Typ. 2.8V
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SRCLKENAN
VDD33
VSS33
VDDK
VSSK
T3
SRCLKENAI
VDD33
VSS33
VDDK
VSSK
T2
SYSRST#
VDD33
VSS33
VDDK
VSSK
U3
GPIO0
VDD33
VSS33
VDDK
VSSK
U1
GPIO1
VDD33
VSS33
VDDK
VSSK
U2
EINT0
VDD33
VSS33
VDDK
VSSK
V1
EINT1
VDD33
VSS33
VDDK
VSSK
W1
EINT2
VDD33
VSS33
VDDK
VSSK
V2
EINT3
VDD33
VSS33
VDDK
VSSK
W2
VSS33
V3
VDD33_EMI
U4
MIRQ
VDD33_EMI
VSS33_EMI
VDDK
VSSK
W3
V4
W4
W5
V5
U5
T5
R5
V6
W6
U6
T6
R6
W7
V7
U7
T7
R7
P8
W8
V8
U8
T8
R8
V9
W9
U9
T9
R9
V10
W10
U10
T10
R10
P10
W11
V11
U11
T11
R11
EA25
EA24
EA23
VSS33_EMI
EA22
EA21
EA20
EA19
VDD33_EMI
EA18
EA17
EA16
VSS33_EMI
EA15
EA14
EA13
VDD33_EMI
EA12
EA11
EA10
VDDK
VSS33_EMI
EA9
EA8
EA7
VDD33_EMI
EA6
EA5
EA4
VSS33_EMI
EA3
EA2
EA1
VDD33_EMI
EA0
EADV#
ECLK
VSS33_EMI
EPDN#
ECS3#
VDD33_EMI
VDD33_EMI
VDD33_EMI
VSS33_EMI
VSS33_EMI
VSS33_EMI
VDDK
VDDK
VDDK
VSSK
VSSK
VSSK
VDD33_EMI
VDD33_EMI
VDD33_EMI
VDD33_EMI
VSS33_EMI
VSS33_EMI
VSS33_EMI
VSS33_EMI
VDDK
VDDK
VDDK
VDDK
VSSK
VSSK
VSSK
VSSK
VDD33_EMI
VDD33_EMI
VDD33_EMI
VSS33_EMI
VSS33_EMI
VSS33_EMI
VDDK
VDDK
VDDK
VSSK
VSSK
VSSK
VDD33_EMI
VDD33_EMI
VDD33_EMI
VSS33_EMI
VSS33_EMI
VSS33_EMI
VDDK
VDDK
VDDK
VSSK
VSSK
VSSK
VDD33_EMI
VDD33_EMI
VDD33_EMI
VSS33_EMI
VSS33_EMI
VSS33_EMI
VDDK
VDDK
VDDK
VSSK
VSSK
VSSK
Re
lea
se
Typ. 1.8/2.8V
Typ. 1.8/2.8V
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T1
Revision 1.0
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MT6228 GSM/GPRS Baseband Processor Data Sheet
Typ. 1.8/2.8V
Typ. 1.2V
VDD33_EMI
VDD33_EMI
VDD33_EMI
VSS33_EMI
VSS33_EMI
VSS33_EMI
VDDK
VDDK
VDDK
VSSK
VSSK
VSSK
VDD33_EMI
VDD33_EMI
VDD33_EMI
VSS33_EMI
VSS33_EMI
VSS33_EMI
VDDK
VDDK
VDDK
VSSK
VSSK
VSSK
VDD33_EMI
VDD33_EMI
VDD33_EMI
VSS33_EMI
VSS33_EMI
VSS33_EMI
VDDK
VDDK
VDDK
VSSK
VSSK
VSSK
VDD33_EMI
VDD33_EMI
VDD33_EMI
VSS33_EMI
VSS33_EMI
VSS33_EMI
VDDK
VDDK
VDDK
VSSK
VSSK
VSSK
VDD33_EMI
VDD33_EMI
VSS33_EMI
VSS33_EMI
VDDK
VDDK
VSSK
VSSK
Typ. 1.8/2.8V
Typ. 1.8/2.8V
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P11
W12
V12
U12
T12
R12
P12
W13
V13
U13
T13
ECS2#
VDD33_EMI
ECS1#
ECS0#
EWR#
VSS33_EMI
ERD#
EUB#
ELB#
VDD33_EMI
EDCLK
VDD33_EMI
VSS33_EMI
VDDK
VSSK
VDD33_EMI
VDD33_EMI
VDD33_EMI
VSS33_EMI
VSS33_EMI
VSS33_EMI
VDDK
VDDK
VDDK
VSSK
VSSK
VSSK
VDD33_EMI
VDD33_EMI
VDD33_EMI
VSS33_EMI
VSS33_EMI
VSS33_EMI
VDDK
VDDK
VDDK
VSSK
VSSK
VSSK
VDD33_EMI
VSS33_EMI
VDDK
VSSK
R13
W14
V14
U14
T14
R14
W15
V15
U15
T15
V16
W16
U16
T16
W17
V17
U17
W18
W19
V18
V19
U18
U19
T17
T18
T19
R15
R16
R17
R18
R19
P16
N16
P17
P18
P19
N17
N18
N19
M16
M17
M18
ECKE
ERAS#
VDDK
VSS33_EMI
ECAS#
EWAIT
ED15
VDD33_EMI
ED14
ED13
ED12
VSS33_EMI
ED11
ED10
ED9
VDD33_EMI
ED8
ED7
ED6
VSS33_EMI
ED5
ED4
ED3
VDD33_EMI
ED2
ED1
ED0
WATCHDOG
VSS33_EMI
USB_DP
USB_DM
VDD33_AUX2
VDD33_AUX1
MCCM0
MCDA0
MCDA1
MCDA2
MCDA3
MCPWRON
MCWP
MCINS
MCCK
VDD33_EMI
VDD33_EMI
VSS33_EMI
VSS33_EMI
VDDK
VDDK
VSSK
VSSK
Typ. 1.8/2.8V
fo
r
Typ. 1.8/2.8V
Typ. 1.2V
VSS33_EMI
VSS33_EMI
VSS33_EMI
VDDK
VSSK
VDD33_EMI
VDD33_EMI
VDD33_EMI
VSS33_EMI
VSS33_EMI
VSS33_EMI
VDDK
VDDK
VDDK
VSSK
VSSK
VSSK
VDD33_EMI
VDD33_EMI
VDD33_EMI
VSS33_EMI
VSS33_EMI
VSS33_EMI
VDDK
VDDK
VDDK
VSSK
VSSK
VSSK
VDD33_EMI
VDD33_EMI
VDD33_EMI
VSS33_EMI
VSS33_EMI
VSS33_EMI
VDDK
VDDK
VDDK
VSSK
VSSK
VSSK
VDD33_EMI
VDD33_EMI
VDD33_EMI
VSS33_EMI
VSS33_EMI
VSS33_EMI
VDDK
VDDK
VDDK
VSSK
VSSK
VSSK
VDD33_EMI
VDD33_EMI
VDD33_EMI
VDD33_EMI
VSS33_EMI
VSS33_EMI
VSS33_EMI
VSS33_EMI
VDDK
VDDK
VDDK
VDDK
VSSK
VSSK
VSSK
VSSK
VDD33_AUX2
VDD33_AUX2
VSS33
VSS33
VDDK
VDDK
VSSK
VSSK
Re
lea
se
VDD33_EMI
VDD33_EMI
VDD33_EMI
Typ. 1.8/2.8V
Typ. 1.8/2.8V
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Revision 1.0
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MT6228 GSM/GPRS Baseband Processor Data Sheet
VDD33_AUX1
VDD33_AUX1
VDD33_AUX1
VDD33_AUX1
VDD33_AUX1
VDD33_AUX1
VDD33_AUX1
VDD33_AUX1
VDD33_AUX1
VSS33
VSS33
VSS33
VSS33
VSS33
VSS33
VSS33
VSS33
VSS33
VDDK
VDDK
VDDK
VDDK
VDDK
VDDK
VDDK
VDDK
VDDK
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1.2V
Typ. 1.8/2.8V
Typ. 3.3V
Typ. 3.3V
VSSK
VSSK
VSSK
VSSK
VSSK
VSSK
VSSK
VSSK
VSSK
MediaTek Inc. Confidential
VSS33
VSS33
VSS33
VSS33
VSS33
VSS33
VSS33
VSS33
VSS33
VSS33
VSS33
VSS33
VSS33
VDDK
VDDK
VDDK
VDDK
VDDK
VDDK
VDDK
VDDK
VDDK
VDDK
VDDK
VDDK
VDDK
VSSK
VSSK
VSSK
VSSK
VSSK
VSSK
VSSK
VSSK
VSSK
VSSK
VSSK
VSSK
VSSK
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VSS33
VSS33
VSS33
VSS33
VSS33
VSS33
VSS33
VSS33
VSS33
VSS33
VSS33
VSS33
VSS33
VSS33
VDDK
VDDK
VDDK
VDDK
VDDK
VDDK
VDDK
VDDK
VDDK
VDDK
VDDK
VDDK
VDDK
VDDK
VSSK
VSSK
VSSK
VSSK
VSSK
VSSK
VSSK
VSSK
VSSK
VSSK
VSSK
VSSK
VSSK
VSSK
Ko
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VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
Re
lea
se
Typ. 2.8V
Co
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VSS33
SIMRST
SIMCLK
SIMVCC
SIMSEL
SIMDATA
URXD1
UTXD1
UCTS1
URTS1
URXD2
UTXD2
URXD3
UTXD3
VDD33
IRDA_RXD
IRDA_TXD
IRDA_PDN
KCOL6
KCOL5
KCOL4
KCOL3
KCOL2
KCOL1
KCOL0
KROW5
KROW4
KROW3
KROW2
VDDK
VSS33
KROW1
KROW0
DAICLK
DAIPCMOUT
DAIPCMIN
DAIRST
DAISYNC
GPIO2
GPIO3
GPIO4
VDD33
GPIO5
GPIO6
GPIO7
MFIQ
GPIO8
GPIO9
VSS33
AVDD_MBUF
AU_MOUTL
AU_MOUTR
AVSS_MBUF
MT
K
L15
M19
L16
L17
L18
L19
K15
K16
K17
K18
K19
J15
J16
J17
J18
J19
H15
H16
H17
H18
H19
G15
G16
G17
G18
G19
F15
F16
F17
F18
F19
E16
E17
E18
E19
D16
D19
D18
D17
C19
C18
B19
C17
A19
B18
B17
A18
A17
B16
C15
B15
A15
D14
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MT6228 GSM/GPRS Baseband Processor Data Sheet
Typ. 1.2V
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VSS33
VSS33
VSS33
VSS33
VSS33
VSS33
VSS33
VSS33
VSS33
VSS33
VDDK
VDDK
VDDK
VDDK
VDDK
VDDK
VDDK
VDDK
VDDK
VDDK
VSSK
VSSK
VSSK
VSSK
VSSK
VSSK
VSSK
VSSK
VSSK
VSSK
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VSS33
VSS33
VSS33
VSS33
VSS33
VSS33
VDDK
VDDK
VDDK
VDDK
VDDK
VDDK
VSSK
VSSK
VSSK
VSSK
VSSK
VSSK
Typ. 2.8V
Typ. 2.8V
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Typ. 2.8V
Typ. 2.8V
Re
lea
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AU_M_BYP
AU_FMINL
AU_FMINR
AU_OUT1_P
AU_OUT1_N
AU_OUT0_N
AVDD_BUF
AU_OUT0_P
AVSS_BUF
AU_MICBIAS_P
AU_MICBIAS_N
AVDD_AFE
AU_VREF_N
AU_VREF_P
AGND_AFE
AU_VIN0_P
AU_VIN0_N
AU_VIN1_N
AU_VIN1_P
AVSS_AFE
BDLAQP
BDLAQN
AGND_RFE
BDLAIN
BDLAIP
AVSS_GSMRFTX
BUPAIP
BUPAIN
AVDD_GSMRFTX
BUPAQN
BUPAQP
AVSS_RFE
APC
AVDD_RFE
AUXADIN0
AUXADIN1
AUXADIN2
AUXADIN3
AUXADIN4
AUXADIN5
AUXADIN6
AUX_REF
AFC
AFC_BYP
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C14
B14
A14
D13
C13
B12
B13
A12
A13
C12
D12
D11
C11
B11
A11
D10
C10
B10
A10
E10
D9
C9
E9
A9
B9
E8
B8
A8
D7
C8
D8
C7
B7
A7
D6
C6
B6
A6
C5
B5
A5
C4
B4
A4
Revision 1.0
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MT6228 GSM/GPRS Baseband Processor Data Sheet
Typ. 2.8V
Typ. 2.8V
MT
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Table 3 Power Descriptions
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3
Micro-Controller Unit Subsystem
Revision 1.0
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MT6228 GSM/GPRS Baseband Processor Data Sheet
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Figure 5 illustrates the block diagram of the Micro-Controller Unit Subsystem in MT6228. The subsystem utilizes a
main 32-bit ARM7EJ-S RISC processor, which plays the role of the main bus master controlling the whole subsystem.
All processor transactions go to code cache first. The code cache controller accesses TCM (128KB memory dedicated
to ARM7EJS core), cache memory, or bus according to the processor’s request address. If the requested content is
found in TCM or in cache, no bus transaction is required. If the code cache hit rate is high enough, bus traffic can be
effectively reduced and processor core performance maximized. In addition to the benefits of reuse of memory
contents, code cache also has a MPU (Memory Protection Unit), which allows cacheable and protection settings of
predefined regions. The contents of code cache are only accessible to MCU, and only MCU instructions are kept in
the cache memory (thus the name “code” cache).
Re
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se
The bus comprises of two-level system buses: Advanced High-Performance Bus (AHB) and Advanced Peripheral Bus
(APB). All bus transactions originate from bus masters, while slaves can only respond to requests from bus masters.
Before data transfer can be established, the bus master must ask for bus ownership, accomplished by request-grant
handshaking protocol between masters and arbiters.
Two levels of bus hierarchy are designed to provide optimum usage for different performance requirements.
Specifically, AHB Bus, the main system bus, is tailored toward high-speed requirements and provides 32-bit data path
with multiplex scheme for bus interconnections. The APB Bus, on the other hand, is designed to reduce interface
complexity for lower data transfer rate, and so it is isolated from high bandwidth AHB Bus by APB Bridge. APB Bus
supports 16-bit addressing and both 16-bit and 32-bit data paths. APB Bus is also optimized for minimal power
consumption by turning off the clock when there is no APB bus activity.
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During operation, if the target slave is located on AHB Bus, the transaction is conducted directly on AHB Bus.
However, if the target slave is a peripheral and is attached to the APB bus, then the transaction is conducted between
AHB and APB bus through the use of APB Bridge.
The MT6228 MCU subsystem supports only memory addressing method. Therefore all components are mapped onto
the MCU 32-bit address space. A Memory Management Unit is employed to allow for a central decode scheme.
The MMU generates appropriate selection signals for each memory-addressed module on the AHB Bus.
In order to off-load the processor core, a DMA Controller is designated to act as a master and share the bus resources
on AHB Bus to perform fast data movement between modules. This controller provides fourteen DMA channels.
The Interrupt Controller provides a software interface to manipulate interrupt events; it can handle up to 32 interrupt
sources asserted at the same time. In general, the controller generates 2 levels of interrupt requests, FIQ and IRQ, to
the processor.
A 128K Byte SRAM is provided as system memory for high-speed data access. For factory programming purposes, a
Boot ROM module is also integrated. These two modules use the same Internal Memory Controller to connect to
AHB Bus.
MT
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External Memory Interface supports both 8-bit and 16-bit devices. This interface supports both synchronous and
asynchronous components, such as Flash, SRAM and parallel LCD. This interface supports page and burst mode type
of Flash, Cellular RAM, as well as high performance MobileRAM. In order to take advantages of burst- or page-type
devices, a data cache is introduced and placed between AHB Bus and EMI, allowing the data cache to issue burst
requests to EMI whenever possible. Since AHB Bus is 32-bit wide, all data transfers are converted into several 8-bit
or 16-bit cycles depending on the data width of the target device. In contrast to code cache, contents in data cache are
queried when MCU issues data requests, or when other AHB bus masters issue memory requests to EMI.
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System ROM
ARM7EJ-S
Interrupt
Controller
System RAM
Internal Memory
Controller
AHB Bus
data
cache
MCU-DSP
Interface
APB
Bridge
fo
r
External
Memory
Interface
code
cache
DMA
Controller
USB
Re
lea
se
Ext
Bus
Arbiter
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MT6228 GSM/GPRS Baseband Processor Data Sheet
APB Bus
Peripheral
Peripheral
Figure 5 Block Diagram of the Micro-Controller Unit Subsystem in MT6228
3.1.1
Processor Core
General Description
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3.1
The Micro-Controller Unit Subsystem in MT6228 uses the 32-bit ARM7EJ-S RISC processor that is based on the Von
Neumann architecture with a single 32-bit data bus carrying both instructions and data. The memory interface of
ARM7EJ-S is totally compliant with the AMBA based bus system, which allows direct connection to the AHB Bus.
3.2
3.2.1
Memory Management
General Description
MT
K
The processor core of MT6228 supports only a memory addressing method for instruction fetch and data access. The
core manages a 32-bit address space that has addressing capability of up to 4 GB. System RAM, System ROM,
Registers, MCU Peripherals and external components are all mapped onto such 32-bit address space, as depicted in
Figure 6.
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MCU 32-bit
Addressing
Space
Reserved
AFFF_FFFh
|
A000_0000h
Reserved
9000_0000h
LCD
8FFF_FFFFh
|
8000_0000h
7FFF_FFFFh
|
7000_0000h
APB Peripherals
7800_0000h
Virtual FIFO
7000_0000h
USB
fo
r
9800_0000h
Re
lea
se
9FFF_FFFh
|
9000_0000h
TCM
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MT6228 GSM/GPRS Baseband Processor Data Sheet
MCU-DSP Interface
4FFF_FFFFh
|
4000_0000h
Internal Memory
3FFF_FFFFh
|
0000_0000h
External Memroy
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6FFF_FFFFh
|
5000_0000h
EA[25:0]
Addressing
Space
Figure 6 The Memory Layout of MT6228
The address space is organized into blocks of 256 MB each. Memory blocks 0-AFFFFFFFh are defined and currently
dedicated to specific functions, while the others are reserved for future usage. The block number is uniquely selected
by address line A31-A28 of the internal system bus.
3.2.1.1
External Access
To allow external access, the MT6228 outputs 26 bits (A25-A0) of address lines along with 4 selection signals that
correspond to associated memory blocks. That is, MT6228 can support up to 4 MCU addressable external
components. The data width of internal system bus is fixed at 32-bit wide, while the data width of the external
components can be either 8- or 16- bit.
MT
K
Since devices are usually available with varied operating grades, adaptive configurations for different applications are
needed. MT6228 provides software programmable registers to configure their wait-states to adapt to different
operating conditions.
3.2.1.2
Memory Re-mapping Mechanism
To permit more flexible system configuration, a memory re-mapping mechanism is provided. The mechanism allows
software program to swap BANK0 (ECS0#) and BANK1 (ECS1#) dynamically. Whenever the bit value of RM0 in
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register EMI_REMAP is changed, these two banks are swapped accordingly.
from System ROM as detailed in 3.2.1.3 Boot Sequence.
3.2.1.3
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MT6228 GSM/GPRS Baseband Processor Data Sheet
Furthermore, it allows system to boot
Boot Sequence
Since the ARM7EJ-S core always starts to fetch instructions from the lowest memory address at 00000000h after
system has been reset, the system is designed to have a dynamic mapping architecture capable of associating Boot Code,
external Flash or external SRAM with the memory block 0000_0000h – 07ff_ffffh.
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By default, the Boot Code is mapped onto 0000_0000h – 07ff_ffffh after a system reset. In this special boot mode,
External Memory Controller does not access external memory; instead, the EMI Controller send predefined Boot Code
back to the ARM7EJS-S core, which instructs the processor to execute the program in System ROM. This
configuration can be changed by programming bit value of RM1 in register EMI_REMAP directly.
MT6228 system provides one boot up scheme:
Re
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se
Start up system of running codes from Boot Code for factory programming or NAND flash boot.
Boot Code
The Boot Code is placed together with Memory Re-Mapping Mechanism in External Memory Controller, and
comprises of just two words of instructions as shown below. A jump instruction leads the processor to run the code
starting at address 48000000h where the System ROM is placed.
ADDRESS
00000000h
00000004h
BINARY CODE
E51FF004h
48000000h
ASSEMBLY
LDR PC, 0x4
(DATA)
Factory Programming
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The configuration for factory programming is shown in Figure 7. Usually the Factory Programming Host connects
with MT6228 via the UART interface. The download speed can be up to 921K bps while MCU is running at 26MHz.
After the system has reset, the Boot Code guides the processor to run the Factory Programming software placed in
System ROM. Then, MT6228 starts and polls the UART1 port until valid information is detected. The first
information received on the UART1 is used to configure the chip for factory programming. The Flash downloader
program is then transferred into System RAM or external SRAM.
Further information is detailed in the MT6228 Software Programming Specification.
UART
MT6228
Factory
Programming
Host
MT
K
External
Memory
Interface
FLASH
Figure 7 System configuration required for factory programming
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NAND Flash Booting
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MT6228 GSM/GPRS Baseband Processor Data Sheet
If MT6228 cannot receive data from UART1 for a certain amount of time, the program in System ROM checks if any
valid boot loader exists in NAND flash. If found, the boot loader code is copied from NAND flash to RAM (internal
or external) and executed to start the real application software. If no valid boot loader can be found in NAND flash,
MT6228 starts executing code in EMI bank0 memory. The whole boot sequence is shown in the following figure.
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Boot from
System ROM
Y
Receive
from UART
N
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Check UART
input
Valid loader
on NAND
N
Boot from
EMI bank 0
Y
Factory
programming
Copy loader from
NAND to RAM
Boot from
loader in RAM
3.2.1.4
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Figure 8 Boot sequence
Little Endian Mode
The MT6228 system always treats 32-bit words of memory in Little Endian format. In Little Endian mode, the lowest
numbered byte in a word is stored in the least significant position, and the highest numbered byte in the most
significant position. Byte 0 of the memory system is therefore connected to data lines 7 through 0.
3.3
3.3.1
Bus System
General Description
Two levels of bus hierarchy are employed in the Micro-Controller Unit Subsystem of MT6228. As depicted in Figure
5, AHB Bus and APB Bus serve as system backbone and peripheral buses, while an APB bridge connects these two
buses. Both AHB and APB Buses operate at the same or half the clock rate of processor core.
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The APB Bridge is the only bus master residing on the APB bus. All APB slaves are mapped onto memory block
MB8 in the MCU 32-bit addressing space. A central address decoder is implemented inside the bridge to generate
select signals for individual peripherals. In addition, since the base address of each APB slave is associated with
select signals, the address bus on APB contains only the value of offset address.
The maximum address space that can be allocated to a single APB slave is 64 KB, i.e. 16-bit address lines. The width
of the data bus is mainly constrained to 16 bits to minimize the design complexity and power consumption while some
use 32-bit data buses to accommodate more bandwidth. In the case where an APB slave needs large amount of
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transfers, the device driver can also request DMA channels to conduct a burst of data transfer.
data width of each peripheral are listed in Table 4.
Data
Width
Revision 1.0
The base address and
Description
Software Base ID
8000_0000h
Configuration Registers
(Clock, Power Down, Version and Reset)
16
CONFG Base
8001_0000h
External Memory Interface
32
EMI Base
8002_0000h
Interrupt Controller
32
CIRQ Base
8003_0000h
DMA Controller
32
DMA Base
8004_0000h
Reset Generation Unit
16
RGU Base
8005_0000h
Data cache controller
32
DATACACHE Base
8006_0000h
GPRS Cipher Unit
32
GCU Base
32
SWDBG Base
32
NFI Base
16
SCCB Base
16
GPT Base
16
KP Base
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Base Address
Software Debug
Reserved
8009_0000h
NAND Flash Interface
800a_0000h
Serial Camera Control Bus
8010_0000h
General Purpose Timer
8011_0000h
Keypad Scanner
8012_0000h
General Purpose Inputs/Outputs
16
GPIO Base
8013_0000h
UART 1
16
UART1 Base
8014_0000h
SIM Interface
16
SIM Base
8015_0000h
Pulse-Width Modulation Outputs
16
PWM Base
8016_0000h
Alerter Interface
16
ALTER Base
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8007_0000h
8008_0000h
8017_0000h
Cipher Hash Engine
32
CHE Base
8018_0000h
UART 2
16
UART2 Base
8019_0000h
PPP Framer
32
PFC Base
801a_0000h
IrDA
16
IRDA Base
801b_0000h
UART 3
16
UART3 Base
801c_0000h
Base-Band to PMIC Serial Interface
16
B2PSI Base
8020_0000h
TDMA Timer
32
TDMA Base
8021_0000h
Real Time Clock
16
RTC Base
8022_0000h
Base-Band Serial Interface
32
BSI Base
8023_0000h
Base-Band Parallel Interface
16
BPI Base
8024_0000h
Automatic Frequency Control Unit
16
AFC Base
8025_0000h
Automatic Power Control Unit
32
APC Base
8026_0000h
Frame Check Sequence
16
FCS Base
8027_0000h
Auxiliary ADC Unit
16
AUXADC Base
8028_0000h
Divider/Modulus Coprocessor
32
DIVIDER Base
8029_0000h
CSD Format Conversion Coprocessor
32
CSD_ACC Base
802a_0000h
MS/SD Controller
32
MSDC Base
8030_0000h
MCU-DSP Shared Register
16
SHARE Base
8031_0000h
DSP Patch Unit
16
PATCH Base
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Audio Front End
16
AFE Base
Base-Band Front End
16
BFE Base
8050_0000h
Analog Chip Interface Controller
16
MIXED Base
8060_0000h
JPEG Decoder
32
JPEG Base
8061_0000h
Post Processing Resizer
32
PRZ Base
8062_0000h
Camera Interface
32
CAM Base
8063_0000h
Image Engine
32
IMG Base
8064_0000h
PNG Decoder
32
PNGDEC Base
8065_0000h
GIF Decoder
32
GIFDEC Base
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8040_0000h
8041_0000h
2D Command Queue
32
GCMQ Base
2D Accelerator
32
G2D Base
8068_0000h
MPEG4 Codec
32
MP4 Base
8069_0000h
Image DMA
32
IMGDMA Base
806a_0000h
Capture Resizer
Drop Resizer
806c_0000h
TV Encoder
806d_0000h
TV Controller
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8066_0000h
8067_0000h
806b_0000h
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806e_0000h
Graphics Memory Controller
8070_0000h
Code cache controller and MPU
32
CRZ Base
32
DRZ Base
32
TVENC Base
32
TVCON Base
32
GMC Base
32
CODECAHE Base
Table 4 Register Base Addresses for MCU Peripherals
REGISTER ADDRESS REGISTER NAME
SYNONYM
Hardware Version Register
HW_VER
CONFG + 0004h
Software Version Register
SW_VER
CONFG + 0008h
Hardware Code Register
HW_CODE
CONFG + 0404h
APB Bus Control Register
APB_CON
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CONFG + 0000h
Table 5 APB Bridge Register Map
3.3.2
Register Definitions
CONFG+0000
Hardware Version Register
h
Bit
Name
Type
Reset
15
14
13
EXTP
RO
8
12
11
10
9
MAJREV
RO
A
8
7
HW_VERSION
6
5
RO
0
4
3
MINREV
2
1
0
RO
0
This register is used by software to determine the hardware version of the chip. The register contains a new value
whenever each metal fix or major step is performed. All values are incremented by a step of 1.
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MINREV
Minor Revision of the chip
MAJREV Major Revision of the chip
EXTP This field shows the existence of Hardware Code Register that presents the Hardware ID while the value is
other than zero.
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CONFG+0004
Software Version Register
h
Bit
Name
Type
Reset
15
14
13
EXTP
RO
8
12
11
10
9
MAJREV
RO
A
Revision 1.0
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MT6228 GSM/GPRS Baseband Processor Data Sheet
SW_VERSION
8
7
6
5
4
3
MINREV
RO
0
1
0
RO
0
All values are incremented by
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This register is used by software to determine the software version used with this chip.
a step of 1.
2
CONFG+0008
Hardware Code Register
h
Bit
Name
Type
Reset
15
14
13
CODE3
RO
6
12
11
10
9
CODE2
RO
2
8
This register presents the Hardware ID.
CODE This version of chip is coded as 6228h.
CONFG+0400
APB Bus Control Register
h
Name
Type
Reset
15
14
APB
W6
R/W
0
13
12
APB
W4
R/W
0
11
APB
W3
R/W
0
10
APB
W2
R/W
0
9
APB
W1
R/W
0
8
APB
W0
R/W
0
7
7
6
5
CODE1
RO
2
6
APBR
6
R/W
1
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Bit
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MINREV
Minor Revision of the Software
MAJREV Major Revision of the Software
EXTP This field shows the existence of Software Code Register that presents the Software ID when the value is other
than zero.
5
4
3
HW_CODE
2
1
CODE0
RO
8
0
APB_CON
4
3
2
1
0
APBR APBR APBR APBR APBR
4
3
2
1
0
R/W R/W R/W R/W R/W
1
1
1
1
1
This register is used to control the timing of Read Cycle and Write Cycle on APB Bus. Note that APB Bridge 5 is
different from other bridges: the access time is varied, and access is not complete until an acknowledge signal from
APB slave is asserted.
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APBR0-APBR6 Read Access Time on APB Bus
0 1-Cycle Access
1 2-Cycle Access
APBW0-APBW6
Write Access Time on APB Bus
0 1-Cycle Access
1 2-Cycle Access
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3.4
3.4.1
Direct Memory Access
General Description
Revision 1.0
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MT6228 GSM/GPRS Baseband Processor Data Sheet
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A generic DMA Controller is placed on Layer 2 AHB Bus to support fast data transfers and to off-load the processor.
With this controller, specific devices on AHB or APB buses can benefit greatly from quick completion of data
movement from or to memory modules such as Internal System RAM or External SRAM. Such Generic DMA
Controller can also be used to connect any two devices other than memory module as long as they can be addressed in
memory space.
Figure 9 Variety Data Paths of DMA Transfers
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Up to fourteen channels of simultaneous data transfers are supported. Each channel has a similar set of registers to be
configured to different scheme as desired. If more than fourteen devices are requesting the DMA resources at the
same time, software based arbitration should be employed. Once the service candidate is decided, the responsible
device driver should configure the Generic DMA Controller properly in order to conduct DMA transfers. Both
Interrupt and Polling based schemes in handling the completion event are supported. The block diagram of such
generic DMA Controller is illustrated in Figure 10.
Figure 10 Block Diagram of Direct memory Access Module
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3.4.1.1
Full-Size & Half-Size DMA Channels
Revision 1.0
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MT6228 GSM/GPRS Baseband Processor Data Sheet
3.4.1.2
Ring Buffer & Double Buffer Memory Data Movement
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There are three types of DMA channels in the DMA controller. The first one is called a full-size DMA channel, the
second one is called a half-size DMA channel, and the last is Virtual FIFO DMA. Channels 1 through 3 are full-size
DMA channels; channels 4 through 10 are half-size ones; and channels 11 through 14 are Virtual FIFO DMAs. The
difference between the first two types of DMA channels is that both source and destination address are programmable
in full-size DMA channels, but only the address of one side can be programmed in half-size DMA channel. In
half-size channels, only either the source or destination address can be programmed, while the addresses of the other
side is preset. Which preset address is used depends on the setting of MAS in DMA Channel Control Register.
Refer to the Register Definition section for more detail.
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DMA channels 1 through 10 support ring-buffer and double-buffer memory data movement. This can be achieved by
programming DMA_WPPT and DMA_WPTO, as well as setting WPEN in DMA_CON register to enable. Figure 11
illustrates how this function works. Once the transfer counter reaches the value of WPPT, the next address jumps to
the WPTO address after completing the WPPT data transfer. Note that only one side can be configured as ring-buffer
or double-buffer memory, and this is controlled by WPSD in DMA_CON register.
Figure 11 Ring Buffer and Double Buffer Memory Data Movement
3.4.1.3
Unaligned Word Access
The address of word access on AHB bus must be aligned to word boundary, or the 2 LSB is truncated to 00b. If
programmers do not notice this, it may cause an incorrect data fetch. In the case where data is to be moved from
unaligned addresses to aligned addresses, the word is usually first split into four bytes and then moved byte by byte.
This results in four read and four write transfers on the bus.
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To improve bus efficiency, unaligned-word access is provided in DMA4~10. While this function is enabled, DMAs
move data from unaligned address to aligned address by executing four continuous byte-read access and one
word-write access, reducing the number of transfers on the bus by three.
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Figure 12 Unaligned Word Accesses
Virtual FIFO DMA
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3.4.1.4
Revision 1.0
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MT6228 GSM/GPRS Baseband Processor Data Sheet
Virtual FIFO DMA is used to ease UART control. The difference between the Virtual FIFO DMAs and the ordinary
DMAs is that Virtual FIFO DMA contains additional FIFO controller. The read and write pointers are kept in the
Virtual FIFO DMA. During a read from the FIFO, the read pointer points to the address of the next data. During a
write to the FIFO, the write pointer moves to the next address. If the FIFO is empty, a FIFO read is not allowed.
Similarly, data is not written into the FIFO if the FIFO is full. Due to UART flow control requirements, an alert
length is programmed. Once the FIFO Space is less than this value, an alert signal is issued to enable UART flow
control. The type of flow control performed depends on the setting in UART.
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Each Virtual FIFO DMA can be programmed as RX or TX FIFO. This depends on the setting of DIR in DMA_CON
register. If DIR is “0”(READ), it means TX FIFO. On the other hand, if DIR is “1”(WRITE), the Virtual FIFO
DMA is specified as a RX FIFO.
Virtual FIFO DMA provides an interrupt to MCU. This interrupt informs MCU that there is data in the FIFO, and the
amount of data is over or under the value defined in DMA_COUNT register. With this, MCU does not need to poll
DMA to know when data must be removed from or put into the FIFO.
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Note that Virtual FIFO DMAs cannot be used as generic DMAs, i.e. DMA1~10.
Figure 13 Virtual FIFO DMA
DMA number
Address of Virtual FIFO Access Port
Associated UART
DMA11
7800_0000h
UART1 RX / ALL UART TX
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DMA12
7800_0100h
UART2 RX / ALL UART TX
DMA13
7800_0200h
UART3 RX / ALL UART TX
DMA14
7800_0300h
ALL UART TX
Table 6 Virtual FIFO Access Port
DMA1
Full Size
DMA2
Full Size
DMA3
Full Size
DMA4
Half Size
DMA5
Half Size
DMA6
Half Size
DMA7
Half Size
DMA8
Half Size
DMA9
Half Size
DMA10
Half Size
DMA11
Virtual FIFO
DMA12
Virtual FIFO
DMA13
Virtual FIFO
DMA14
Virtual FIFO
Ring Buffer Two Buffer
Burst Mode
Unaligned Word
Access
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DMA number
Table 7 Function List of DMA channels
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REGISTER ADDRESS REGISTER NAME
SYNONYM
DMA + 0000h
DMA Global Status Register
DMA_GLBSTA
DMA + 0028h
DMA Global Bandwidth Limiter Register
DMA_GLBLIMITER
DMA + 0100h
DMA Channel 1 Source Address Register
DMA1_SRC
DMA + 0104h
DMA Channel 1 Destination Address Register
DMA1_DST
DMA + 0108h
DMA Channel 1 Wrap Point Address Register
DMA1_WPPT
DMA + 010Ch
DMA Channel 1 Wrap To Address Register
DMA1_WPTO
DMA + 0110h
DMA Channel 1 Transfer Count Register
DMA1_COUNT
DMA + 0114h
DMA Channel 1 Control Register
DMA1_CON
DMA + 0118h
DMA Channel 1 Start Register
DMA1_START
DMA + 011Ch
DMA Channel 1 Interrupt Status Register
DMA1_INTSTA
DMA + 0120h
DMA Channel 1 Interrupt Acknowledge Register
DMA1_ACKINT
DMA Channel 1 Remaining Length of Current Transfer
DMA1_RLCT
DMA Channel 1 Bandwidth Limiter Register
DMA1_LIMITER
DMA + 0200h
DMA Channel 2 Source Address Register
DMA2_SRC
DMA + 0204h
DMA Channel 2 Destination Address Register
DMA2_DST
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DMA + 0124h
DMA + 0128h
DMA + 0208h
DMA Channel 2 Wrap Point Address Register
DMA2_WPPT
DMA + 020Ch
DMA Channel 2 Wrap To Address Register
DMA2_WPTO
DMA + 0210h
DMA Channel 2 Transfer Count Register
DMA2_COUNT
DMA + 0214h
DMA Channel 2 Control Register
DMA2_CON
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DMA Channel 2 Start Register
DMA2_START
DMA Channel 2 Interrupt Status Register
DMA2_INTSTA
DMA + 0220h
DMA Channel 2 Interrupt Acknowledge Register
DMA2_ACKINT
DMA + 0224h
DMA Channel 2 Remaining Length of Current Transfer
DMA2_RLCT
DMA + 0228h
DMA Channel 2 Bandwidth Limiter Register
DMA2_LIMITER
DMA + 0300h
DMA Channel 3 Source Address Register
DMA3_SRC
DMA + 0304h
DMA Channel 3 Destination Address Register
DMA3_DST
DMA + 0308h
DMA Channel 3 Wrap Point Address Register
DMA3_WPPT
DMA + 030Ch
DMA Channel 3 Wrap To Address Register
DMA3_WPTO
DMA + 0310h
DMA Channel 3 Transfer Count Register
DMA3_COUNT
DMA + 0314h
DMA Channel 3 Control Register
DMA3_CON
DMA + 0318h
DMA Channel 3 Start Register
DMA3_START
DMA + 031Ch
DMA Channel 3 Interrupt Status Register
DMA3_INTSTA
DMA + 0320h
DMA Channel 3 Interrupt Acknowledge Register
DMA3_ACKINT
DMA + 0324h
DMA Channel 3 Remaining Length of Current Transfer
DMA3_RLCT
DMA + 0328h
DMA Channel 3 Bandwidth Limiter Register
DMA3_LIMITER
DMA + 0408h
DMA Channel 4 Wrap Point Address Register
DMA4_WPPT
DMA + 040Ch
DMA Channel 4 Wrap To Address Register
DMA4_WPTO
DMA + 0410h
DMA Channel 4 Transfer Count Register
DMA4_COUNT
DMA + 0414h
DMA Channel 4 Control Register
DMA4_CON
DMA + 0418h
DMA Channel 4 Start Register
DMA4_START
DMA + 041Ch
DMA Channel 4 Interrupt Status Register
DMA4_INTSTA
DMA + 0420h
DMA Channel 4 Interrupt Acknowledge Register
DMA4_ACKINT
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DMA + 0218h
DMA + 021Ch
DMA + 0424h
DMA Channel 4 Remaining Length of Current Transfer
DMA4_RLCT
DMA + 0428h
DMA Channel 4 Bandwidth Limiter Register
DMA4_LIMITER
DMA + 042Ch
DMA Channel 4 Programmable Address Register
DMA4_PGMADDR
DMA + 0508h
DMA Channel 5 Wrap Point Address Register
DMA5_WPPT
DMA + 050Ch
DMA Channel 5 Wrap To Address Register
DMA5_WPTO
DMA + 0510h
DMA Channel 5 Transfer Count Register
DMA5_COUNT
DMA + 0514h
DMA Channel 5 Control Register
DMA5_CON
DMA + 0518h
DMA Channel 5 Start Register
DMA5_START
DMA + 051Ch
DMA Channel 5 Interrupt Status Register
DMA5_INTSTA
DMA + 0520h
DMA Channel 5 Interrupt Acknowledge Register
DMA5_ACKINT
DMA Channel 5 Remaining Length of Current Transfer
DMA5_RLCT
DMA Channel 5 Bandwidth Limiter Register
DMA5_LIMITER
DMA + 052Ch
DMA Channel 5 Programmable Address Register
DMA5_PGMADDR
DMA + 0608h
DMA Channel 6 Wrap Point Address Register
DMA6_WPPT
DMA + 060Ch
DMA Channel 6 Wrap To Address Register
DMA6_WPTO
DMA + 0610h
DMA Channel 6 Transfer Count Register
DMA6_COUNT
DMA + 0614h
DMA Channel 6 Control Register
DMA6_CON
DMA + 0618h
DMA Channel 6 Start Register
DMA6_START
DMA + 061Ch
DMA Channel 6 Interrupt Status Register
DMA6_INTSTA
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DMA + 0524h
DMA + 0528h
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DMA Channel 6 Interrupt Acknowledge Register
DMA6_ACKINT
DMA + 0624h
DMA Channel 6 Remaining Length of Current Transfer
DMA6_RLCT
DMA + 0628h
DMA Channel 6 Bandwidth Limiter Register
DMA6_LIMITER
DMA + 062Ch
DMA Channel 6 Programmable Address Register
DMA6_PGMADDR
DMA + 0708h
DMA Channel 7 Wrap Point Address Register
DMA7_WPPT
DMA + 070Ch
DMA Channel 7 Wrap To Address Register
DMA7_WPTO
DMA + 0710h
DMA Channel 7 Transfer Count Register
DMA7_COUNT
DMA + 0714h
DMA Channel 7 Control Register
DMA7_CON
DMA + 0718h
DMA Channel 7 Start Register
DMA7_START
DMA + 071Ch
DMA Channel 7 Interrupt Status Register
DMA7_INTSTA
DMA + 0720h
DMA Channel 7 Interrupt Acknowledge Register
DMA7_ACKINT
DMA + 0724h
DMA Channel 7 Remaining Length of Current Transfer
DMA7_RLCT
DMA + 0728h
DMA Channel 7 Bandwidth Limiter Register
DMA7_LIMITER
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DMA + 0620h
DMA + 072Ch
DMA Channel 7 Programmable Address Register
DMA7_PGMADDR
DMA + 0808h
DMA Channel 8 Wrap Point Address Register
DMA8_WPPT
DMA + 080Ch
DMA Channel 8 Wrap To Address Register
DMA8_WPTO
DMA + 0810h
DMA Channel 8 Transfer Count Register
DMA8_COUNT
DMA + 0814h
DMA Channel 8 Control Register
DMA8_CON
DMA + 0818h
DMA Channel 8 Start Register
DMA8_START
DMA + 081Ch
DMA Channel 8 Interrupt Status Register
DMA8_INTSTA
DMA + 0820h
DMA Channel 8 Interrupt Acknowledge Register
DMA8_ACKINT
DMA Channel 8 Remaining Length of Current Transfer
DMA8_RLCT
DMA Channel 8 Bandwidth Limiter Register
DMA8_LIMITER
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DMA + 0824h
DMA + 0828h
DMA + 082Ch
DMA Channel 8 Programmable Address Register
DMA8_PGMADDR
DMA + 0908h
DMA Channel 9 Wrap Point Address Register
DMA9_WPPT
DMA + 090Ch
DMA Channel 9 Wrap To Address Register
DMA9_WPTO
DMA + 0910h
DMA Channel 9 Transfer Count Register
DMA9_COUNT
DMA + 0914h
DMA Channel 9 Control Register
DMA9_CON
DMA + 0918h
DMA Channel 9 Start Register
DMA9_START
DMA + 091Ch
DMA Channel 9 Interrupt Status Register
DMA9_INTSTA
DMA + 0920h
DMA Channel 9 Interrupt Acknowledge Register
DMA9_ACKINT
DMA + 0924h
DMA Channel 9 Remaining Length of Current Transfer
DMA9_RLCT
DMA + 0928h
DMA Channel 9 Bandwidth Limiter Register
DMA9_LIMITER
DMA Channel 9 Programmable Address Register
DMA9_PGMADDR
DMA Channel 10 Wrap Point Address Register
DMA10_WPPT
DMA + 0A0Ch
DMA Channel 10 Wrap To Address Register
DMA10_WPTO
DMA + 0A10h
DMA Channel 10 Transfer Count Register
DMA10_COUNT
DMA + 0A14h
DMA Channel 10 Control Register
DMA10_CON
DMA + 0A18h
DMA Channel 10 Start Register
DMA10_START
DMA + 0A1Ch
DMA Channel 10 Interrupt Status Register
DMA10_INTSTA
DMA + 0A20h
DMA Channel 10 Interrupt Acknowledge Register
DMA10_ACKINT
DMA + 0A24h
DMA Channel 10 Remaining Length of Current
Transfer
DMA10_RLCT
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DMA + 092Ch
DMA + 0A08h
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DMA + 0A28h
DMA Channel 10 Bandwidth Limiter Register
DMA10_LIMITER
DMA + 0A2Ch
DMA Channel 10 Programmable Address Register
DMA10_PGMADDR
DMA + 0B10h
DMA Channel 11 Transfer Count Register
DMA11_COUNT
DMA + 0B14h
DMA Channel 11 Control Register
DMA11_CON
DMA + 0B18h
DMA Channel 11 Start Register
DMA11_START
DMA Channel 11 Interrupt Status Register
DMA11_INTSTA
DMA + 0B20h
DMA Channel 11 Interrupt Acknowledge Register
DMA11_ACKINT
DMA + 0B28h
DMA Channel 11 Bandwidth Limiter Register
DMA11_LIMITER
DMA + 0B2Ch
DMA Channel 11 Programmable Address Register
DMA11_PGMADDR
DMA + 0B30h
DMA Channel 11 Write Pointer
DMA11_WRPTR
DMA + 0B34h
DMA Channel 11 Read Pointer
DMA11_RDPTR
DMA + 0B38h
DMA Channel 11 FIFO Count
DMA11_FFCNT
DMA + 0B3Ch
DMA Channel 11 FIFO Status
DMA11_FFSTA
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DMA + 0B1Ch
DMA + 0B40h
DMA Channel 11 Alert Length
DMA11_ALTLEN
DMA + 0B44h
DMA Channel 11 FIFO Size
DMA11_FFSIZE
DMA + 0C10h
DMA Channel 12 Transfer Count Register
DMA12_COUNT
DMA + 0C14h
DMA Channel 12 Control Register
DMA12_CON
DMA + 0C18h
DMA Channel 12 Start Register
DMA12_START
DMA + 0C1Ch
DMA Channel 12 Interrupt Status Register
DMA12_INTSTA
DMA + 0C20h
DMA Channel 12 Interrupt Acknowledge Register
DMA12_ACKINT
DMA + 0C28h
DMA Channel 12 Bandwidth Limiter Register
DMA12_LIMITER
DMA Channel 12 Programmable Address Register
DMA12_PGMADDR
DMA + 0C30h
DMA Channel 12 Write Pointer
DMA12_WRPTR
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DMA + 0C2Ch
DMA + 0C34h
DMA Channel 12 Read Pointer
DMA12_RDPTR
DMA + 0C38h
DMA Channel 12 FIFO Count
DMA12_FFCNT
DMA + 0C3Ch
DMA Channel 12 FIFO Status
DMA12_FFSTA
DMA + 0C40h
DMA Channel 12 Alert Length
DMA12_ALTLEN
DMA + 0C44h
DMA Channel 12 FIFO Size
DMA12_FFSIZE
DMA + 0D10h
DMA Channel 13 Transfer Count Register
DMA13_COUNT
DMA + 0D14h
DMA Channel 13 Control Register
DMA13_CON
DMA + 0D18h
DMA Channel 13 Start Register
DMA13_START
DMA + 0D1Ch
DMA Channel 13 Interrupt Status Register
DMA13_INTSTA
DMA + 0D20h
DMA Channel 13 Interrupt Acknowledge Register
DMA13_ACKINT
DMA + 0D28h
DMA Channel 13 Bandwidth Limiter Register
DMA13_LIMITER
DMA + 0D2Ch
DMA Channel 13 Programmable Address Register
DMA13_PGMADDR
DMA + 0D30h
DMA Channel 13 Write Pointer
DMA13_WRPTR
DMA + 0D34h
DMA Channel 13 Read Pointer
DMA13_RDPTR
DMA Channel 13 FIFO Count
DMA13_FFCNT
DMA Channel 13 FIFO Status
DMA13_FFSTA
DMA + 0D40h
DMA Channel 13 Alert Length
DMA13_ALTLEN
DMA + 0D44h
DMA Channel 13 FIFO Size
DMA13_FFSIZE
DMA + 0E10h
DMA Channel 14 Transfer Count Register
DMA14_COUNT
MT
K
DMA + 0D38h
DMA + 0D3Ch
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DMA + 0E14h
DMA Channel 14 Control Register
DMA14_CON
DMA + 0E18h
DMA Channel 14 Start Register
DMA14_START
DMA + 0E1Ch
DMA Channel 14 Interrupt Status Register
DMA14_INTSTA
DMA + 0E20h
DMA Channel 14 Interrupt Acknowledge Register
DMA14_ACKINT
DMA + 0E28h
DMA Channel 14 Bandwidth Limiter Register
DMA14_LIMITER
DMA Channel 14 Programmable Address Register
DMA14_PGMADDR
DMA + 0E30h
DMA Channel 14 Write Pointer
DMA14_WRPTR
DMA + 0E34h
DMA Channel 14 Read Pointer
DMA14_RDPTR
DMA + 0E38h
DMA Channel 14 FIFO Count
DMA14_FFCNT
fo
r
DMA + 0E2Ch
DMA Channel 14 FIFO Status
DMA14_FFSTA
DMA + 0E40h
DMA Channel 14 Alert Length
DMA14_ALTLEN
DMA + 0E44h
DMA Channel 14 FIFO Size
DMA14_FFSIZE
Re
lea
se
DMA + 0E3Ch
Table 8 DMA Controller Register Map
3.4.2
Register Definitions
Register programming tips:
Start registers shall be cleared, when associated channels are being programmed.
PGMADDR, i.e. programmable address, only exists in half-size DMA channels. If DIR in Control Register
is high, PGMADDR represents Destination Address. Conversely, If DIR in Control Register is low,
PGMADDR represents Source Address.
DMA+0000h
Bit
31
Name
Type
Reset
Bit
Name
Type
Reset
15
IT8
RO
0
30
Co
nf
id
en
tia
l
Functions of ring-buffer and double-buffer memory data movement can be activated on either source side or
destination side by programming DMA_WPPT & and DMA_WPTO, as well as setting WPEN in DMA_CON
register high. WPSD in DMA_CON register determines the activated side.
14
RUN8
RO
0
DMA Global Status Register
29
13
IT7
RO
0
28
27
DMA_GLBSTA
26
25
24
23
22
21
20
19
18
RUN1
RUN1
RUN1
RUN1
RUN1
IT14
IT13
IT12
IT11
IT10
4
3
2
1
0
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
0
0
0
0
0
0
0
0
0
0
12
11
10
9
8
7
6
5
4
3
2
RUN7 IT6 RUN6 IT5 RUN5 IT4 RUN4 IT3 RUN3 IT2 RUN2
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
0
0
0
0
0
0
0
0
0
0
0
17
16
IT9
RUN9
RO
0
1
IT1
RO
0
RO
0
0
RUN1
RO
0
This register helps software program keep track of the global status of DMA channels.
MT
K
RUNN DMA channel n status
0 Channel n is stopped or has completed the transfer already.
1 Channel n is currently running.
ITN
Interrupt status for channel n
0 No interrupt is generated.
1 An interrupt is pending and waiting for service.
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DMA+0028h
DMA_GLBLIMIT
ER
DMA Global Bandwidth limiter Register
31
30
29
28
27
26
25
24
23
22
21
15
14
13
12
11
10
9
8
7
6
5
20
19
4
3
GLBLIMITER
WO
0
Please refer to the expression in DMAn_LIMITER for detailed note.
DMA_GLBLIMITER is set to all DMA channels, from 1 to 14.
2
17
16
1
0
The value of
DMA Channel n Source Address Register
31
30
29
28
27
26
25
15
14
13
12
11
10
9
Re
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DMA+0n00h
Bit
Name
Type
Reset
Bit
Name
Type
Reset
18
fo
r
Bit
Name
Type
Reset
Bit
Name
Type
Reset
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24
23
SRC[31:16]
R/W
0
8
7
SRC[15:0]
R/W
0
DMAn_SRC
22
21
20
19
18
17
16
6
5
4
3
2
1
0
Co
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The above registers contain the base or current source address that the DMA channel is currently operating on.
Writing to this register specifies the base address of transfer source for a DMA channel. Before programming these
registers, the software program should make sure that STR in DMAn_START is set to 0; that is, the DMA channel is
stopped and disabled completely. Otherwise, the DMA channel may run out of order. Reading this register returns
the address value from which the DMA is reading.
Note that n is from 1 to 3.
SRC
SRC[31:0] specifies the base or current address of transfer source for a DMA channel, i.e. channel 1, 2 or 3.
WRITE Base address of transfer source
READ Address from which DMA is reading
DMA+0n04h
Bit
Name
Type
Reset
Bit
Name
Type
Reset
31
30
15
14
DMA Channel n Destination Address Register
29
28
27
26
25
13
12
11
10
9
24
23
DST[31:16]
R/W
0
8
7
DST[15:0]
R/W
0
DMAn_DST
22
21
20
19
18
17
16
6
5
4
3
2
1
0
MT
K
The above registers contain the base or current destination address that the DMA channel is currently operating on..
Writing to this register specifies the base address of the transfer destination for a DMA channel. Before programming
these registers, the software should make sure that STR in DMAn_START is set to ‘0’; that is, the DMA channel is
stopped and disabled completely. Otherwise, the DMA channel may run out of order. Reading this register returns
the address value to which the DMA is writing.
Note that n is from 1 to 3.
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DST[31:0] specifies the base or current address of transfer destination for a DMA channel, i.e. channel 1, 2 or
3.
WRITE Base address of transfer destination.
READ Address to which DMA is writing.
DMA+0n08h
Bit
Name
Type
Reset
Bit
Name
Type
Reset
DMA Channel n Wrap Point Count Register
31
30
29
28
27
26
25
15
14
13
12
11
10
9
24
23
8
7
WPPT[15:0]
R/W
0
DMAn_WPPT
22
21
20
6
5
4
19
18
17
fo
r
DST
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3
2
1
16
0
Re
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se
The above registers are to specify the transfer count required to perform before the jump point. This can be used to
support ring buffer or double buffer style memory accesses. To enable this function, two control bits, WPEN and
WPSD, in DMA control register must be programmed. See the following register description for more details. If the
transfercounter in the DMA engine matches this value, an address jump occurs, and the next address is the address
specified in DMAn_WPTO. Before programming these registers, the software should make sure that STR in
DMAn_START is set to ‘0’, that is the DMA channel is stopped and disabled completely. Otherwise, the DMA
channel may run out of order. To enable this function, WPEN in DMA_CON is set.
Note that n is from 1 to 10.
DMA+0n0Ch
Bit
Name
Type
Reset
Bit
Name
Type
Reset
31
30
15
14
Co
nf
id
en
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l
WPPT WPPT[15:0] specifies the amount of the transfer count from start to jumping point for a DMA channel, i.e.
channel 1 – 10.
WRITE Address of the jump point.
READ Value set by the programmer.
DMA Channel n Wrap To Address Register
29
28
27
26
25
13
12
11
10
9
24
23
WPTO[31:16]
R/W
0
8
7
WPTO[15:0]
R/W
0
DMAn_WPTO
22
21
20
19
18
17
16
6
5
4
3
2
1
0
The above registers specify the address of the jump destination of a given DMA transfer to support ring buffer or
double buffer style memory accesses. To enable this function, set the two control bits, WPEN and WPSD, in the
DMA control register . See the following register description for more details. Before programming these registers,
the software should make sure that STR in DMAn_START is set to ‘0’, that is the DMA channel is stopped and
disabled completely. Otherwise, the DMA channel may run out of order. To enable this function, WPEN in
DMA_CON should be set.
Note that n is from 1 to 10.
MT
K
WPTO WPTO[31:0] specifies the address of the jump point for a DMA channel, i.e.
WRITE Address of the jump destination.
READ Value set by the programmer.
DMA+0n10h
Bit
31
30
channel 1 – 10.
DMA Channel n Transfer Count Register
29
28
27
26
25
24
23
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22
DMAn_COUNT
21
20
19
18
17
16
MediaTek Inc. Confidential
Name
Type
Reset
Bit
Name
Type
Reset
15
14
13
12
11
10
9
8
7
6
5
4
3
Revision 1.0
2
LEN
R/W
0
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1
0
fo
r
This register specifies the amount of total transfer count that the DMA channel is required to perform. Upon
completion, the DMA channel generates an interrupt request to the processor while ITEN in DMAn_CON is set as ‘1’.
Note that the total size of data being transferred by a DMA channel is determined by LEN together with the SIZE in
DMAn_CON, i.e. LEN x SIZE.
Note that n is from 1 to 14.
LEN
The amount of total transfer count
DMA+0n14h
Bit
31
30
Re
lea
se
For virtual FIFO DMA, this register is used to configure the RX threshold and TX threshold. Interrupt is triggered
while FIFO count >= RX threshold in RX path or FIFO count =< TX threshold in TX path. Note that ITEN bit in
DMA_CON register shall be set, or no interrupt is issued.
DMA Channel n Control Register
29
28
27
26
25
24
Name
23
22
MAS
14
13
12
11
10
9
BURST
R/W
0
8
7
R/W
0
6
20
19
DMAn_CON
18
DIR
R/W
0
5
4
3
2
B2W DRQ DINC SINC
R/W R/W R/W R/W
0
0
0
0
17
16
WPS
WPEN
D
R/W R/W
0
0
1
0
SIZE
R/W
0
Co
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Type
Reset
Bit
15
Name ITEN
Type R/W
Reset
0
21
This register contains all the available control schemes for a DMA channel that is ready for software programmer to
configure. Note that all these fields cannot be changed while DMA transfer is in progress or an unexpected situation
may occur.
Note that n is from 1 to 14.
SIZE
SINC
MT
K
DINC
Data size within the confine of a bus cycle per transfer.
These bits confines the data transfer size between source and destination to the specified value for individual
bus cycle. The size is in terms of byte and has maximum value of 4 bytes. It is mainly decided by the data
width of a DMA master.
00 Byte transfer/1 byte
01 Half-word transfer/2 bytes
10 Word transfer/4 bytes
11 Reserved
Incremental source address. Source addresses increase every transfer. If the setting of SIZE is Byte, Source
addresses increase by 1 every single transfer. If Half-Word, increase by 2; and if Word, increase by 4.
0 Disable
1 Enable
Incremental destination address. Destination addresses increase every transfer. If the setting of SIZE is
Byte, Destination addresses increase by 1 every single transfer. If Half-Word, increase by 2; and Iif Word,
increase by 4.
0 Disable
1 Enable
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MT
K
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DREQ Throttle and handshake control for DMA transfer
0 No throttle control during DMA transfer or transfers occurred only between memories
1 Hardware handshake management
The DMA master is able to throttle down the transfer rate by way of request-grant handshake.
B2W Word to Byte or Byte to Word transfer for the applications of transferring non-word-aligned-address data to
word-aligned-address data. Note that BURST is set to 4-beat burst while enabling this function, and the
SIZE is set to Byte.
NO effect on channel 1 – 3 & 11 - 14.
0 Disable
1 Enable
BURST Transfer Type. Burst-type transfers have better bus efficiency. Mass data movement is recommended to
use this kind of transfer. However, note that burst-type transfer does not stop until all of the beats in a burst
are completed or transfer length is reached. FIFO threshold of peripherals must be configured carefully
while being used to move data from/to the peripherals.
What transfer type can be used is restricted by the SIZE. If SIZE is 00b, i.e. byte transfer, all of the four
transfer types can be used. If SIZE is 01b, i.e. half-word transfer, 16-beat incrementing burst cannot be used.
If SIZE is 10b, i.e. byte transfer, only single and 4-beat incrementing burst can be used.
NO effect on channel 11 - 14.
000 Single
001 Reserved
010 4-beat incrementing burst
011 Reserved
100 8-beat incrementing burst
101 Reserved
110 16-beat incrementing burst
111 Reserved
ITEN DMA transfer completion interrupt enable.
0 Disable
1 Enable
WPSD The side using address-wrapping function. Only one side of a DMA channel can activate address-wrapping
function at a time.
NO effect on channel 11 - 14.
0 Address-wrapping on source .
1 Address-wrapping on destination.
WPEN Address-wrapping for ring buffer. The next address of DMA jumps to WRAP TO address when the current
address matches WRAP POINT count.
NO effect on channel 11 - 14.
0 Disable
1 Enable
DIR
Directions of DMA transfer for half-size and Virtual FIFO DMA channels, i.e. channels 4~14. The direction
is from the perspective of the DMA masters. WRITE means read from master and then write to the address
specified in DMA_PGMADDR, and vice versa.
NO effect on channel 1 - 3.
0 Read
1 Write
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Master selection. Specifies which master occupies this DMA channel. Once assigned to certain master, the
corresponding DREQ and DACK are connected. For half-size and Virtual FIFO DMA channels, i.e.
channels 4 ~ 14, a predefined address is assigned as well.
00000 SIM
00001 MSDC
00010 IrDA TX
00011 IrDA RX
00100 USB1 Write
00101 USB1 Read
00110 USB2 Write
00111 USB2 Read
01000 UART1 TX
01001 UART1 RX
01010 UART2 TX
01011 UART2 RX
01100 UART3 TX
01101 UART3 RX
01110 DSP-DMA
01111 NFI TX
10000 NFI RX
OTHERS
Reserved
Bit
31
Name
Type
Reset
Bit
15
Name STR
Type R/W
Reset
0
30
14
DMA Channel n Start Register
29
28
27
26
25
24
23
Co
nf
id
en
tia
l
DMA+0n18h
Re
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fo
r
MAS
Revision 1.0
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MT6228 GSM/GPRS Baseband Processor Data Sheet
13
12
11
10
9
8
7
DMAn_START
22
21
20
19
18
17
16
6
5
4
3
2
1
0
This register controls the activity of a DMA channel. Note that prior to setting STR to “1”, all the configurations
should be done by giving proper value to the registers. Note also that once the STR is set to “1”, the hardware does
not clear it automatically no matter if the DMA channel accomplishes the DMA transfer or not. In other works, the
value of STR stays “1” regardless of the completion of DMA transfer. Therefore, the software program should be
sure to clear STR to “0” before restarting another DMA transfer.
Note that n is from 1 to 14.
STR
Start control for a DMA channel.
0 The DMA channel is stopped.
1 The DMA channel is started and running.
DMA+0n1Ch
30
29
MT
K
Bit
31
Name
Type
Reset
Bit
15
Name INT
Type RO
Reset
0
DMA Channel n Interrupt Status Register
14
13
DMAn_INTSTA
28
27
26
25
24
23
22
21
20
19
18
17
16
12
11
10
9
8
7
6
5
4
3
2
1
0
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This register shows the interrupt status of a DMA channel.
Revision 1.0
It has the same value as DMA_GLBSTA.
Note that n is from 1 to 14.
Interrupt Status for DMA Channel
0 No interrupt request is generated.
1 One interrupt request is pending and waiting for service.
Bit
31
Name
Type
Reset
Bit
15
Name ACK
Type WO
Reset
0
DMA Channel n Interrupt Acknowledge Register
30
29
28
27
26
25
24
23
22
21
20
14
13
12
11
10
9
8
7
6
5
4
DMAn_ACKINT
19
18
17
16
3
2
1
0
fo
r
DMA+0n20h
Re
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INT
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MT6228 GSM/GPRS Baseband Processor Data Sheet
This register is used to acknowledge the current interrupt request associated with the completion event of a DMA
channel by software program. Note that this is a write-only register, and any read to it returns a value of “0”.
Note that n is from 1 to 14.
Interrupt acknowledge for the DMA channel
0 No effect
1 Interrupt request is acknowledged and should be relinquished.
DMA+0n24h
Bit
Name
Type
Reset
Bit
Name
Type
Reset
31
30
15
14
DMA Channel n Remaining Length of Current
Transfer
DMAn_RLCT
29
28
27
26
25
24
23
22
21
20
19
18
17
16
13
12
11
10
9
8
7
RLCT
RO
0
6
5
4
3
2
1
0
Co
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ACK
This register is to reflect the left amount of the transfer.
Note that n is from 1 to 10.
DMA+0n28h
31
30
15
14
DMAn_LIMITER
29
28
27
26
25
24
23
22
21
20
19
18
17
16
13
12
11
10
9
8
7
6
5
4
3
LIMITER
R/W
0
2
1
0
MT
K
Bit
Name
Type
Reset
Bit
Name
Type
Reset
DMA Bandwidth limiter Register
This register is to suppress the Bus utilization of the DMA channel. The value is from 0 to 255. 0 means no
limitation, and 255 means totally banned. The value between 0 and 255 means certain DMA can have permission to
use AHB every (4 X n) AHB clock cycles.
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Note that it is not recommended to limit the Bus utilization of the DMA channels because this increases the latency of
response to the masters, and the transfer rate decreases as well. Before using it, programmer must make sure that the
bus masters have some protective mechanism to avoid entering the wrong states.
Note that n is from 1 to 14.
LIMITER from 0 to 255. 0 means no limitation, 255 means totally banned, and others mean Bus access permission
every (4 X n) AHB clock.
31
30
29
28
27
26
15
14
13
12
11
10
25
24
23
22
PGMADDR[31:16]
R/W
0
9
8
7
6
PGMADDR[15:0]
R/W
0
21
20
5
4
DMAn_PGMAD
DR
19
18
17
16
3
2
1
0
Re
lea
se
Bit
Name
Type
Reset
Bit
Name
Type
Reset
DMA Channel n Programmable Address Register
fo
r
DMA+0n2Ch
The above registers specify the address for a half-size DMA channel. This address represents a source address if DIR
in DMA_CON is set to 0, and represents a destination address if DIR in DMA_CON is set to 1. Before being able to
program these register, the software should make sure that STR in DMAn_START is set to ‘0’, that is the DMA channel
is stopped and disabled completely. Otherwise, the DMA channel may run out of order.
Note that n is from 4 to 14.
DMA+0n30h
Bit
Name
Type
Bit
Name
Type
31
30
15
14
Co
nf
id
en
tia
l
PGMADDR PGMADDR[31:0] specifies the addresses for a half-size or a Virtual FIFO DMA channel, i.e. channel 4 –
14.
WRITE Address of the jump destination.
READ Current address of the transfer.
DMA Channel n Virtual FIFO Write Pointer Register
29
28
27
26
13
12
11
10
25
24
23
22
WRPTR[31:16]
RO
9
8
7
6
WRPTR[15:0]
RO
DMAn_WRPTR
21
20
19
18
17
16
5
4
3
2
1
0
Note that n is from 11 to 14.
WRPTR
Virtual FIFO Write Pointer.
DMA+0n34h
Bit
Name
Type
Bit
Name
Type
31
30
15
14
DMA Channel n Virtual FIFO Read Pointer Register
29
28
27
26
25
13
12
11
10
9
24
23
22
RDPTR[31:16]
RO
8
7
6
RDPTR[15:0]
RO
DMAn_RDPTR
21
20
19
18
17
16
5
4
3
2
1
0
MT
K
Note that n is from 11 to 14.
RDPTR Virtual FIFO Read Pointer.
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DMA+0n38h
Bit
Name
Type
Bit
Name
Type
DMA Channel n Virtual FIFO Data Count Register
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DMAn_FFCNT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
15
14
13
12
11
10
9
8
7
FFCNT
RO
6
5
4
3
2
17
16
1
0
FFCNT To display the number of data stored in FIFO.
FFSIZE.
Bit
Name
Type
Reset
Bit
0 means FIFO empty, and FIFO is full if FFCNT is equal to
DMA Channel n Virtual FIFO Status Register
31
30
29
28
27
26
25
24
15
14
13
12
11
10
9
8
Name
Type
Reset
Note that n is from 11 to 14.
FULL
DMA+0n40h
Bit
Name
Type
Reset
Bit
Name
Type
Reset
31
30
15
14
7
Co
nf
id
en
tia
l
To indicate FIFO is full.
0 Not Full
1 Full
EMPTY To indicate FIFO is empty.
0 Not Empty
1 Empty
ALT
To indicate FIFO Count is larger than ALTLEN.
control.
0 Not reach alert region.
1 Reach alert region.
23
22
21
DMAn_FFSTA
20
19
18
Re
lea
se
DMA+0n3Ch
fo
r
Note that n is from 11 to 14.
6
5
4
3
17
16
2
1
0
EMPT
ALT
FULL
Y
RO
RO
RO
0
1
0
DMA issues an alert signal to UART to enable UART flow
DMA Channel n Virtual FIFO Alert Length Register
DMAn_ALTLEN
29
28
27
26
25
24
23
22
21
20
19
18
17
16
13
12
11
10
9
8
7
6
5
4
3
2
ALTLEN
R/W
0
1
0
Note that n is from 11 to 14.
MT
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ALTLEN
Specifies the Alert Length of Virtual FIFO DMA. Once the remaining FIFO space is less than ALTLEN,
an alert signal is issued to UART to enable flow control. Normally, ALTLEN shall be larger than 16 for
UART application.
DMA+0n44h
Bit
31
30
DMA Channel n Virtual FIFO Size Register
29
28
27
26
25
24
23
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21
DMAn_FFSIZE
20
19
18
17
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Name
Type
Reset
Bit
Name
Type
Reset
15
14
13
12
11
10
9
8
7
FFSIZE
R/W
0
6
5
4
3
Note that n is from 11 to 14.
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1
0
3.5
3.5.1
fo
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FFSIZE Specifies the FIFO Size of Virtual FIFO DMA.
Interrupt Controller
General Description
Re
lea
se
Figure 14 outlines the major functionality of the MCU Interrupt Controller. The interrupt controller processes all
interrupt sources coming from external lines and internal MCU peripherals. Since ARM7EJ-S core supports two
levels of interrupt latency, this controller generates two request signals: FIQ for fast, low latency interrupt request and
IRQ for more general interrupts with lower priority.
EINT
TDMA
GPT
Interrupt
Input
Multiplex
IRQ
Controller
IRQ
IRQ1
IRQ2
Co
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KP
FIQ
IRQ0
SIM
UART1
FIQ
Controller
RTC
UART2
DSP2MCU
IRQn
IRQ31
SoftIRQ
APB Bus
Registers
Figure 15 Block Diagram of the Interrupt Controller
MT
K
One and only one of the interrupt sources can be assigned to FIQ Controller and have the highest priority in requesting
timing critical service. All the others share the same IRQ signal by connecting them to IRQ Controller. The IRQ
Controller manages up 32 interrupt lines of IRQ0 to IRQ31 with fixed priority in descending order.
The Interrupt Controller provides a simple software interface by mean of registers to manipulate the interrupt request
shared system. IRQ Selection Registers and FIQ Selection Register determine the source priority and connecting
relation among sources and interrupt lines. IRQ Source Status Register allows software program to identify the source
of interrupt that generates the interrupt request. IRQ Mask Register provides software to mask out undesired sources
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some time. End of Interrupt Register permits software program to indicate to the controller that a certain interrupt
service routine has been finished.
Binary coded version of IRQ Source Status Register is also made available for software program to helpfully identify
the interrupt source. Note that while taking advantage of this, it should also take the binary coded version of End of
Interrupt Register coincidently.
The essential Interrupt Table of ARM7EJ-S core is shown as Table 9.
Description
00000000h
System Reset
00000018h
IRQ
0000001Ch
FIQ
fo
r
Address
Interrupt Source Masking
Re
lea
se
Table 10 Interrupt Table of ARM7EJ-S
Interrupt controller provides the function of Interrupt Source Masking by the way of programming MASK register.
Any of them can be masked individually.
However, because of the bus latency, the masking takes effect no earlier than 3 clock cycles later. In this time, the
to-be-masked interrupts could come in and generate an IRQ pulse to MCU, and then disappear immediately. This
IRQ forces MCU going to Interrupt Service Routine and polling Status Register (IRQ_STA or IRQ_STA2), but the
register shows there is no interrupt. This might cause MCU malfunction.
There are two ways for programmer to protect their software.
Return from ISR (Interrupt Service Routine) immediately while the Status register shows no interrupt.
2.
Set I bit of MCU before doing Interrupt Masking, and then clear it after Interrupt Masking done.
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1.
Both avoid the problem, but the first item recommended to have in the ISR.
External Interrupt
This interrupt controller also integrates an External Interrupt Controller that can support up to 4 interrupt requests
coming from external sources, the EINT0~3, and 4 WakeUp interrupt requests, i.e. EINT4~7, coming from peripherals
used to inform system to resume the system clock.
The four external interrupts can be used for different kind of applications, mainly for event detections: detection of
hand free connection, detection of hood opening, detection of battery charger connection.
MT
K
Since the external event may be unstable in a certain period, a de-bounce mechanism is introduced to ensure the
functionality. The circuitry is mainly used to verify that the input signal remains stable for a programmable number of
periods of the clock. When this condition is satisfied, for the appearance or the disappearance of the input, the output
of the de-bounce logic changes to the desired state. Note that, because it uses the 32 KHz slow clock for performing
the de-bounce process, the parameter of de-bounce period and de-bounce enable takes effect no sooner than one
32 KHz clock cycle (~31.25us) after the software program sets them. However, the polarities of EINTs are clocked
with the system clock. Any changes to them take effect immediately. Note also that this External Interrupt
Controller handles only level sensitive type of interrupt sources.
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EINT4-7
EINT2
EINT1
EINT0
Debounce Logic
Interrupt
Control
Logic
Debounce Logic
EINT_IRQ
Debounce Logic
Debounce Logic
Figure 16 Block Diagram of External Interrupt Controller
REGISTER ADDRESS REGISTER NAME
CIRQ + 0000h
IRQ Selection 0 Register
CIRQ + 0004h
IRQ Selection 1 Register
IRQ Selection 2 Register
IRQ Selection 3 Register
CIRQ + 0010h
IRQ Selection 4 Register
CIRQ + 0014h
IRQ Selection 5 Register
SYNONYM
IRQ_SEL0
IRQ_SEL1
IRQ_SEL2
IRQ_SEL3
IRQ_SEL4
IRQ_SEL5
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CIRQ + 0008h
CIRQ + 000Ch
APB Bus
Re
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Registers
fo
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EINT3
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CIRQ + 0018h
IRQ Selection 6 Register
IRQ_SEL6
CIRQ + 001ch
IRQ Selection 7 Register
IRQ_SEL7
CIRQ + 0034h
FIQ Selection Register
FIQ_SEL
CIRQ + 0038h
IRQ Mask Register (LSB)
IRQ_MASKL
CIRQ + 003ch
IRQ Mask Register (MSB)
IRQ_MASKH
CIRQ + 0040h
IRQ Mask Clear Register (LSB)
IRQ_MASK_CLRL
CIRQ + 0044h
IRQ Mask Clear Register (MSB)
IRQ_MASK_CLRH
CIRQ + 0048h
IRQ Mask Set Register (LSB)
IRQ_MASK_SETL
CIRQ + 004ch
IRQ Mask Set Register (MSB)
IRQ_MASK_SETH
IRQ Status Register (LSB)
IRQ_STAL
IRQ Status Register (MSB)
IRQ_STAH
CIRQ + 0058h
IRQ End of Interrupt Register (LSB)
IRQ_EOIL
CIRQ + 005ch
IRQ End of Interrupt Register (MSB)
IRQ_EOIH
CIRQ + 0060h
IRQ Sensitive Register (LSB)
IRQ_SENSL
CIRQ + 0064h
IRQ Sensitive Register (MSB)
IRQ_SENSH
CIRQ + 0068h
IRQ Software Interrupt Register (LSB)
IRQ_SOFTL
CIRQ + 006ch
IRQ Software Interrupt Register (MSB)
IRQ_SOFTH
CIRQ + 0070h
FIQ Control Register
FIQ_CON
CIRQ + 0074h
FIQ End of Interrupt Register
FIQ_EOI
MT
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CIRQ + 0050h
CIRQ + 0054h
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c
31
30
29
28
15
14
13
IRQ11
R/W
11
12
CIRQ+0010h
Bit
Name
Type
Reset
Bit
Name
Type
Reset
30
29
28
15
14
13
IRQ16
R/W
16
12
Bit
Name
Type
Reset
Bit
Name
Type
Reset
30
29
28
15
14
13
IRQ1B
R/W
1b
12
30
29
28
15
14
13
IRQ20
R/W
20
12
31
30
29
28
15
14
13
IRQ25
R/W
25
12
CIRQ+0020h
Bit
31
30
23
22
9
8
IRQ10
R/W
10
7
6
23
22
21
20
IRQ12
R/W
12
5
4
27
26
IRQ18
R/W
18
11
10
25
27
26
IRQ1D
R/W
1d
11
10
18
3
2
IRQF
R/W
f
27
26
IRQ22
R/W
22
11
10
24
9
8
IRQ1A
R/W
1a
25
27
26
IRQ27
R/W
27
11
10
7
6
23
22
7
6
21
20
IRQ17
R/W
17
5
4
19
21
20
IRQ1C
R/W
1c
5
4
18
3
2
IRQ14
R/W
14
19
IRQ_SEL5
18
3
2
IRQ19
R/W
19
23
22
9
8
IRQ1F
R/W
1f
7
6
21
20
IRQ21
R/W
21
5
4
19
18
3
2
IRQ1E
R/W
1e
28
27
26
24
23
22
9
8
IRQ24
R/W
24
7
6
25
17
16
IRQ1B
R/W
1b
1
0
17
16
IRQ20
R/W
20
1
0
IRQ_SEL7
21
20
IRQ26
R/W
26
5
4
19
18
3
2
IRQ23
R/W
23
IRQ Selection 8 Register
29
17
16
IRQ16
R/W
16
1
0
IRQ_SEL6
24
25
17
16
IRQ11
R/W
11
1
0
IRQ_SEL4
24
9
8
IRQ15
R/W
15
25
19
IRQ Selection 7 Register
MT
K
Bit
Name
Type
Reset
Bit
Name
Type
Reset
24
IRQ Selection 6 Register
31
CIRQ+001ch
25
IRQ Selection 5 Register
31
CIRQ+0018h
27
26
IRQ13
R/W
13
11
10
IRQ_SEL3
IRQ Selection 4 Register
31
CIRQ+0014h
Bit
Name
Type
Reset
Bit
Name
Type
Reset
IRQ Selection 3 Register
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Bit
Name
Type
Reset
Bit
Name
Type
Reset
a
fo
r
CIRQ+000ch
b
Re
lea
se
Reset
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17
16
IRQ25
R/W
25
1
0
IRQ_SEL8
24
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22
21
20
19
18
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CIRQ+0034h
Bit
Name
Type
Reset
Bit
Name
Type
Reset
13
12
11
10
9
8
7
6
5
4
3
2
IRQ28
R/W
28
FIQ Selection Register
1
0
FIQ_SEL
31
30
29
28
27
26
25
24
23
22
21
20
15
14
13
12
11
10
9
8
7
6
5
4
19
18
17
16
3
2
1
0
fo
r
15
FIQ
R/W
0
Re
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Name
Type
Reset
Bit
Name
Type
Reset
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The IRQ/FIQ Selection Registers provide system designers with a flexible routing scheme to make various mappings of
priority among interrupt sources possible. The registers allow the interrupt sources to be mapped onto interrupt
requests of either FIQ or IRQ. While only one interrupt source can be assigned to FIQ, the other ones share IRQs by
mapping them onto IRQ0 to IRQ1F connected to IRQ controller. The priority sequence of IRQ0~IRQ1F is fixed, i.e.
IRQ0 > IRQ1 > IRQ2 > … > IRQ1E > IRQ1F. During the software configuration process, the Interrupt Source Code
of desired interrupt source should be written into source field of the corresponding IRQ_SEL0-IRQ_SEL4/FIQ_SEL.
Five-bit Interrupt Source Codes for all interrupt sources are fixed and defined.
Interrupt Source
STA2 (Hex)
STAH_STAL
0
000_00000001
1
000_00000002
TDMA_CTIRQ2
2
000_00000004
DSP2CPU
3
000_00000008
MT
K
Co
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GPI_FIQ
TDMA_CTIRQ1
SIM
4
000_00000010
DMA
5
000_00000020
TDMA
6
000_00000040
UART1
7
000_00000080
KeyPad
8
000_00000100
UART2
9
000_00000200
GPTimer
a
000_00000400
EINT
b
000_00000800
USB
c
000_00001000
MSDC
d
000_00002000
RTC
e
000_00004000
IrDA
f
000_00008000
LCD
10
000_00010000
UART3
11
000_00020000
GPI
12
000_00040000
WDT
13
000_00080000
SWDBG
14
000_00100000
CHE
15
000_00200000
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16
000_00400000
B2PSI
17
000_00800000
Image DMA
18
000_01000000
GIF
19
000_02000000
1a
000_04000000
1b
000_08000000
G2D
1c
000_10000000
Image Porc
1d
000_20000000
CAM
1e
000_40000000
PFC
1f
000_80000000
MPEG4_DEC
20
001_00000000
MPEG4_ENC
21
002_00000000
JPEG_DEC
22
004_00000000
JPEG_ENC
23
008_00000000
Re
lea
se
PNG
SCCB
fo
r
NFI
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MT6228 GSM/GPRS Baseband Processor Data Sheet
Resizer_crz
24
010_00000000
Resizer_drz
25
020_00000000
Resizer_prz
26
040_00000000
TVE
27
080_00000000
Table 12 Interrupt Source Code for Interrupt Sources
FIQ, IRQ0-26
The 5-bit content of this field corresponds to an Interrupt Source Code shown above.
CIRQ+0038h
31
30
Type R/W R/W
1
1
Reset
Bit
15
14
Name IRQF IRQE
Type R/W R/W
Reset
1
1
29
IRQ1
D
R/W
1
13
IRQD
R/W
1
CIRQ+003ch
IRQ Mask Register (MSB)
Name IRQ1F IRQ1E
Bit
Name
Type
Reset
Bit
Name
Type
Reset
31
30
15
14
28
IRQ1
C
R/W
1
12
IRQC
R/W
1
27
IRQ1
B
R/W
1
11
IRQB
R/W
1
26
IRQ1
A
R/W
1
10
IRQA
R/W
1
25
24
23
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Bit
IRQ Mask Register (LSB)
22
21
20
19
IRQ_MASKL
18
17
16
IRQ19 IRQ18 IRQ17 IRQ16 IRQ15 IRQ14 IRQ13 IRQ12 IRQ11 IRQ10
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
1
1
1
1
1
1
1
1
1
1
9
8
7
6
5
4
3
2
1
0
IRQ9 IRQ8 IRQ7 IRQ6 IRQ5 IRQ4 IRQ3 IRQ2 IRQ1 IRQ0
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
1
1
1
1
1
1
1
1
1
1
29
28
27
26
25
24
13
12
11
10
9
8
23
IRQ_MASKH
22
21
20
19
18
17
16
7
6
5
4
3
2
1
0
IRQ27 IRQ26 IRQ25 IRQ24 IRQ23 IRQ22 IRQ21 IRQ20
R/W R/W R/W R/W R/W R/W R/W R/W
1
1
1
1
1
1
1
1
MT
K
This register contains a mask bit for each interrupt line in IRQ Controller. The register allows each interrupt source
IRQ0 to IRQ1F to be disabled or masked separately under software control. After a system reset, all bit values are set
to 1 to indicate that interrupt requests are prohibited.
IRQ0-27
0
1
Mask control for the associated interrupt source in the IRQ controller
Interrupt is enabled.
Interrupt is disabled.
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31
30
Type W1C W1C
Bit
15
14
Name IRQF IRQE
Type W1C W1C
29
IRQ1
D
W1C
13
IRQD
W1C
CIRQ+0044h
IRQ Mask Clear Register (MSB)
Name IRQ1F IRQ1E
Bit
Name
Type
Bit
Name
Type
28
IRQ1
C
W1C
12
IRQC
W1C
27
IRQ1
B
W1C
11
IRQB
W1C
26
IRQ1
A
W1C
10
IRQA
W1C
25
24
23
22
21
20
19
18
17
16
IRQ19 IRQ18 IRQ17 IRQ16 IRQ15 IRQ14 IRQ13 IRQ12 IRQ11 IRQ10
W1C W1C W1C W1C W1C W1C W1C W1C W1C W1C
9
8
7
6
5
4
3
2
1
0
IRQ9 IRQ8 IRQ7 IRQ6 IRQ5 IRQ4 IRQ3 IRQ2 IRQ1 IRQ0
W1C W1C W1C W1C W1C W1C W1C W1C W1C W1C
31
30
29
28
27
26
25
24
15
14
13
12
11
10
9
8
IRQ_MASK_CL
RH
23
22
21
20
19
18
17
16
Re
lea
se
Bit
IRQ_MASK_CL
RL
IRQ Mask Clear Register (LSB)
fo
r
CIRQ+0040h
Revision 1.0
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7
6
5
4
3
2
1
0
IRQ27 IRQ26 IRQ25 IRQ24 IRQ23 IRQ22 IRQ21 IRQ20
W1C W1C W1C W1C W1C W1C W1C W1C
This register is used to clear bits in IRQ Mask Register. When writing to this register, the data bits that are HIGH
cause the corresponding bits in IRQ Mask Register to be cleared. Data bits that are LOW have no effect on the
corresponding bits in IRQ Mask Register.
Clear corresponding bits in IRQ Mask Register.
No effect.
Disable the corresponding MASK bit.
CIRQ+0048h
Bit
31
30
Type W1S W1S
Bit
15
14
Name IRQF IRQE
Type W1S W1S
29
IRQ1
D
W1S
13
IRQD
W1S
CIRQ+004ch
IRQ Mask SET Register (MSB)
Name IRQ1F IRQ1E
Bit
Name
Type
Bit
Name
Type
31
30
15
14
IRQ_MASK_SE
TL
IRQ Mask SET Register (LSB)
Co
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IRQ0-27
0
1
28
IRQ1
C
W1S
12
IRQC
W1S
27
IRQ1
B
W1S
11
IRQB
W1S
26
IRQ1
A
W1S
10
IRQA
W1S
25
24
23
22
21
20
19
18
17
16
IRQ19 IRQ18 IRQ17 IRQ16 IRQ15 IRQ14 IRQ13 IRQ12 IRQ11 IRQ10
W1S W1S W1S W1S W1S W1S W1S W1S W1S W1S
9
8
7
6
5
4
3
2
1
0
IRQ9 IRQ8 IRQ7 IRQ6 IRQ5 IRQ4 IRQ3 IRQ2 IRQ1 IRQ0
W1S W1S W1S W1S W1S W1S W1S W1S W1S W1S
29
28
27
26
25
24
13
12
11
10
9
8
23
IRQ_MASK_SE
TH
22
21
20
19
18
17
16
7
6
5
4
3
2
1
0
IRQ27 IRQ26 IRQ25 IRQ24 IRQ23 IRQ22 IRQ21 IRQ20
W1S W1S W1S W1S W1S W1S W1S W1S
MT
K
This register is used to set bits in the IRQ Mask Register. When writing to this register, the data bits that are HIGH
cause the corresponding bits in IRQ Mask Register to be set. Data bits that are LOW have no effect on the
corresponding bits in IRQ Mask Register.
IRQ0-27
0
1
Set corresponding bits in IRQ Mask Register.
No effect.
Enable corresponding MASK bit.
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CIRQ+0050h
Type
Reset
Bit
Name
Type
Reset
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
IRQ1 IRQ1 IRQ1 IRQ1
IRQ19 IRQ18 IRQ17 IRQ16 IRQ15 IRQ14 IRQ13 IRQ12 IRQ11 IRQ10
IRQ1F IRQ1E
D
C
B
A
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
IRQF IRQE IRQD IRQC IRQB IRQA IRQ9 IRQ8 IRQ7 IRQ6 IRQ5 IRQ4 IRQ3 IRQ2 IRQ1 IRQ0
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CIRQ+0054h
Bit
Name
Type
Reset
Bit
Name
Type
Reset
IRQ SouROe Status Register (MSB)
31
30
29
28
27
26
25
24
15
14
13
12
11
10
9
8
23
fo
r
Name
31
IRQ_STAL
IRQ_STAH
22
21
20
19
18
17
16
Re
lea
se
Bit
IRQ Source Status Register (LSB)
Revision 1.0
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MT6228 GSM/GPRS Baseband Processor Data Sheet
7
6
5
4
3
2
1
0
IRQ27 IRQ26 IRQ25 IRQ24 IRQ23 IRQ22 IRQ21 IRQ20
RO
RO
RO
RO
RO
RO
RO
RO
0
0
0
0
0
0
0
0
This Register allows software to poll which interrupt line has generated an IRQ interrupt request. A bit set to 1
indicates a corresponding active interrupt line. Only one flag is active at a time. The IRQ_STA is type of read-clear;
write access has no effect on the content.
Interrupt indicator for the associated interrupt source.
The associated interrupt source is non-active.
The associated interrupt source is asserted.
CIRQ+0058h
Bit
31
30
IRQ End of Interrupt Register (LSB)
Co
nf
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en
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l
IRQ0-27
0
1
IRQ_EOIL
29
28
27
26
25
24
23
22
21
20
19
18
17
16
IRQ1 IRQ1 IRQ1 IRQ1
IRQ19 IRQ18 IRQ17 IRQ16 IRQ15 IRQ14 IRQ13 IRQ12 IRQ11 IRQ10
D
C
B
A
Type WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reset
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name IRQF IRQE IRQD IRQC IRQB IRQA IRQ9 IRQ8 IRQ7 IRQ6 IRQ5 IRQ4 IRQ3 IRQ2 IRQ1 IRQ0
Type WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Name IRQ1F IRQ1E
CIRQ+005ch
Bit
Name
Type
Reset
Bit
Name
Type
Reset
31
30
15
14
IRQ End of Interrupt Register (MSB)
29
28
27
26
25
24
13
12
11
10
9
8
23
IRQ_EOIH
22
21
20
19
18
17
16
7
6
5
4
3
2
1
0
IRQ27 IRQ26 IRQ25 IRQ24 IRQ23 IRQ22 IRQ21 IRQ20
WO WO WO WO WO WO WO WO
0
0
0
0
0
0
0
0
MT
K
This register provides a mean for software to relinquish and to refresh the interrupt controller. Writing a 1 to a
specific bit position results in an End of Interrupt command issued internally to the corresponding interrupt line.
IRQ0-27
0
1
End of Interrupt command for the associated interrupt line.
No service is currently in progress or pending.
Interrupt request is in-service.
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31
30
Type R/W R/W
0
0
Reset
Bit
15
14
Name IRQF IRQE
Type R/W R/W
0
0
Reset
29
IRQ1
D
R/W
0
13
IRQD
R/W
0
CIRQ+0064h
IRQ Sensitive Register (MSB)
Name IRQ1F IRQ1E
Bit
Name
Type
Reset
Bit
Name
Type
Reset
28
IRQ1
C
R/W
0
12
IRQC
R/W
0
27
IRQ1
B
R/W
0
11
IRQB
R/W
0
26
IRQ1
A
R/W
0
10
IRQA
R/W
0
25
24
IRQ_SENSL
23
22
21
20
19
18
17
16
IRQ19 IRQ18 IRQ17 IRQ16 IRQ15 IRQ14 IRQ13 IRQ12 IRQ11 IRQ10
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
0
0
0
0
0
0
0
0
0
0
9
8
7
6
5
4
3
2
1
0
IRQ9 IRQ8 IRQ7 IRQ6 IRQ5 IRQ4 IRQ3 IRQ2 IRQ1 IRQ0
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
0
0
0
0
0
0
0
0
0
0
31
30
29
28
27
26
25
24
15
14
13
12
11
10
9
8
IRQ_SENSH
23
22
21
20
19
18
17
16
Re
lea
se
Bit
IRQ Sensitive Register (LSB)
fo
r
CIRQ+0060h
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7
6
5
4
3
2
1
0
IRQ27 IRQ26 IRQ25 IRQ24 IRQ23 IRQ22 IRQ21 IRQ20
R/W R/W R/W R/W R/W R/W R/W R/W
0
0
0
0
0
0
0
0
IRQ0-27
0
1
Sensitivity type of the associated Interrupt Source
Edge sensitivity with active LOW
Level sensitivity with active LOW
CIRQ+0068h
Bit
31
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All interrupt lines of IRQ Controller, IRQ0~IRQ1F can be programmed as either edge or level sensitive. By default,
all the interrupt lines are edge sensitive and should be active LOW. Once a interrupt line is programmed as edge
sensitive, an interrupt request is triggered only at the falling edge of interrupt line, and the next interrupt is not accepted
until the EOI command is given. However, level sensitive interrupts trigger is according to the signal level of the
interrupt line. Once the interrupt line become from HIGH to LOW, an interrupt request is triggered, and another
interrupt request is triggered if the signal level remain LOW after an EOI command. Note that in edge sensitive mode,
even if the signal level remains LOW after EOI command, another interrupt request is not triggered. That is because
edge sensitive interrupt is only triggered at the falling edge.
30
IRQ Software Interrupt Register (LSB)
Type R/W R/W
Reset
0
0
Bit
15
14
Name IRQF IRQE
Type R/W R/W
Reset
0
0
29
IRQ1
D
R/W
0
13
IRQD
R/W
0
CIRQ+006ch
IRQ Software Interrupt Register (MSB)
Name IRQ1F IRQ1E
31
30
29
MT
K
Bit
Name
Type
Reset
Bit
Name
Type
Reset
15
14
13
28
IRQ1
C
R/W
0
12
IRQC
R/W
0
27
IRQ1
B
R/W
0
11
IRQB
R/W
0
26
IRQ1
A
R/W
0
10
IRQA
R/W
0
25
24
23
22
IRQ_SOFTL
21
20
19
18
17
16
IRQ19 IRQ18 IRQ17 IRQ16 IRQ15 IRQ14 IRQ13 IRQ12 IRQ11 IRQ10
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
0
0
0
0
0
0
0
0
0
0
9
8
7
6
5
4
3
2
1
0
IRQ9 IRQ8 IRQ7 IRQ6 IRQ5 IRQ4 IRQ3 IRQ2 IRQ1 IRQ0
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
0
0
0
0
0
0
0
0
0
0
28
27
26
25
24
12
11
10
9
8
23
22
IRQ_SOFTH
21
20
19
18
17
16
7
6
5
4
3
2
1
0
IRQ27 IRQ26 IRQ25 IRQ24 IRQ23 IRQ22 IRQ21 IRQ20
R/W R/W R/W R/W R/W R/W R/W R/W
0
0
0
0
0
0
0
0
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Setting “1” to the specific bit position generates a software interrupt for corresponding interrupt line before mask.
This register is used for debug purpose.
IRQ0-IRQ27
Software Interrupt
CIRQ+0070h
FIQ_CON
31
30
29
28
27
26
25
24
23
22
21
20
19
18
15
14
13
12
11
10
9
8
7
6
5
4
3
2
Name
Type
Reset
17
16
1
0
MAS
SENS
K
R/W R/W
0
1
fo
r
Bit
Name
Type
Reset
Bit
FIQ Control Register
MASK Mask control for the FIQ Interrupt Source
0 Interrupt is enabled.
1 Interrupt is disabled.
SENS Sensitivity type of the FIQ Interrupt Source
0 Edge sensitivity with active LOW
1 Level sensitivity with active LOW
CIRQ+0074h
FIQ End of Interrupt Register
31
30
29
28
27
26
25
24
15
14
13
12
11
10
9
8
FIQ_EOI
23
22
21
20
19
18
17
16
7
6
5
4
3
2
1
0
EOI
WO
0
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Bit
Name
Type
Reset
Bit
Name
Type
Reset
Re
lea
se
This register provides a means for software program to control the FIQ controller.
This register provides a means for software to relinquish and to refresh the FIQ controller. Writing a ‘1’ to the
specific bit position results in an End of Interrupt command issued internally to the corresponding interrupt line.
EOI
End of Interrupt command
CIRQ+0078h
Bit
Name
Type
Reset
Bit
Name
Type
Reset
31
30
15
14
Binary Coded Value of IRQ_STATUS
IRQ_STA2
29
28
27
26
25
24
23
22
21
20
19
18
17
16
13
12
11
10
9
8
NOIR
Q
RO
0
7
6
5
4
3
2
1
0
STS
RO
0
MT
K
This Register is a binary coded version of IRQ_STA. It is used by the software program to poll which interrupt line
has generated the IRQ interrupt request in a much easier way. Any read to it has the same result as reading IRQ_STA.
The IRQ_STA2 is also read-only; write access has no effect on the content. Note that IRQ_STA2 should be coupled
with IRQ_EOI2 while using it.
STS
Binary coded value of IRQ_STA
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NOIRQ Indicating if there is an IRQ or not.
CIRQ+007ch
If there is no IRQ, this bit is HIGH, and the value of STS is 00_0000b.
Binary Coded Value of IRQ_EOI
IRQ_EOI2
31
30
29
28
27
26
25
24
23
22
21
20
19
15
14
13
12
11
10
9
8
7
6
5
4
3
18
2
EOI
WO
0
17
16
1
0
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Bit
Name
Type
Reset
Bit
Name
Type
Reset
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EOI
Binary coded value of IRQ_EOI
CIRQ+0080h
Bit
Name
Type
Reset
Bit
Name
Type
Reset
Re
lea
se
This register is a binary coded version of IRQ_EOI. It provides an easier way for software program to relinquish and
to refresh the interrupt controller. Writing a specific code results in an End of Interrupt command issued internally to
the corresponding interrupt line. Note that IRQ_EOI2 should be coupled with IRQ_STA2 while using it.
Binary Coded Value of IRQ_SOFT
31
30
29
28
27
26
25
24
15
14
13
12
11
10
9
8
This register is a binary coded version of IRQ_SOFT.
IRQ_SOFT2
23
22
21
20
19
18
17
16
7
6
5
4
3
2
SOFT
WO
0
1
0
CIRQ+0100h
Bit
Name
Type
Reset
Bit
Name
Type
Reset
31
30
15
14
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SOFT Binary Coded Value of IRQ_SOFT
EINT Interrupt Status Register
29
28
27
26
25
24
13
12
11
10
9
8
23
EINT_STA
22
21
20
19
18
17
16
7
6
5
4
3
2
1
0
EINT7 EINT6 EINT5 EINT4 EINT3 EINT2 EINT1 EINT0
RO
RO
RO
RO
RO
RO
RO
RO
0
0
0
0
0
0
0
0
This register keeps up with current status that which EINT Source generates the interrupt request.
set to edge sensitivity, EINT_IRQ is de-asserted while this register is read.
If EINT sources are
EINT0-EINT7 Interrupt status
0 No interrupt request is generated.
1 Interrupt request is pending.
CIRQ+0104h
31
30
EINT Interrupt Mask Register
29
MT
K
Bit
Name
Type
Reset
Bit
Name
Type
Reset
15
14
13
28
27
26
25
24
12
11
10
9
8
23
EINT_MASK
22
21
20
19
18
17
16
7
6
5
4
3
2
1
0
EINT7 EINT6 EINT5 EINT4 EINT3 EINT2 EINT1 EINT0
R/W R/W R/W R/W R/W R/W R/W R/W
1
1
1
1
1
1
1
1
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This register controls whether or not EINT Source is allowed to generate an interrupt request.
to the specific bit position prohibits the external interrupt line from becoming active.
EINT0-EINT7 Interrupt Mask
0 Interrupt request is enabled.
1 Interrupt request is disabled.
31
30
29
28
27
26
25
24
15
14
13
12
11
10
9
8
23
22
21
20
fo
r
Bit
Name
Type
Bit
Name
Type
Setting a “1”
EINT_MASK_C
LR
EINT Interrupt Mask Clear Register
19
18
17
16
7
6
5
4
3
2
1
0
EINT7 EINT6 EINT5 EINT4 EINT3 EINT2 EINT1 EINT0
W1C W1C W1C W1C W1C W1C W1C W1C
Re
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CIRQ+0108h
Revision 1.0
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MT6228 GSM/GPRS Baseband Processor Data Sheet
This register is used to clear individual mask bits. Only the bits set to 1 are in effect, and interrupt masks for which
the mask bit is set are cleared (set to 0). Otherwise the interrupt mask bit retains its original value.
EINT0-EINT7 Disable mask for the associated external interrupt source.
0 No effect.
1 Disable the corresponding MASK bit.
EINT_MASK_S
ET
CIRQ+010Ch EINT Interrupt Mask Set Register
31
30
29
28
27
26
25
24
15
14
13
12
11
10
9
8
23
22
21
20
19
18
17
16
7
6
5
4
3
2
1
0
EINT7 EINT6 EINT5 EINT4 EINT3 EINT2 EINT1 EINT0
W1S W1S W1S W1S W1S W1S W1S W1S
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Bit
Name
Type
Bit
Name
Type
This register is used to set individual mask bits. Only the bits set to 1 are in effect, and interrupt masks for which the
mask bit is set are set to 1. Otherwise the interrupt mask bit retains its original value.
EINT0-EINT7 Disable mask for the associated external interrupt source.
0 No effect.
1 Enable corresponding MASK bit.
CIRQ+0110h
Bit
Name
Type
Reset
Bit
Name
Type
Reset
31
30
15
14
EINT Interrupt Acknowledge Register
29
28
27
26
25
24
13
12
11
10
9
8
23
22
EINT_INTACK
21
20
19
18
17
16
7
6
5
4
3
2
1
0
EINT7 EINT6 EINT5 EINT4 EINT3 EINT2 EINT1 EINT0
WO WO WO WO WO WO WO WO
0
0
0
0
0
0
0
0
MT
K
Writing “1” to the specific bit position acknowledge the interrupt request correspondingly to the external interrupt line
source.
EINT0-EINT7 Interrupt acknowledgement
0 No effect
1 Interrupt request is acknowledged.
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CIRQ+0114h
EINT Sensitive Register
EINT_SENS
30
29
28
27
26
25
24
23
22
21
20
15
14
13
12
11
10
9
8
7
6
5
4
Sensitivity type of external interrupt source.
sensitive.
EINT0-3
0
1
Only EINT0~3 need to be specified.
19
29
28
27
26
25
24
14
13
12
11
POL
R/W
0
10
9
8
16
3
2
1
0
EINT3 EINT2 EINT1 EINT0
R/W R/W R/W R/W
1
1
1
1
CIRQ+01m0h EINTn De-bounce Control Register
30
17
EINT4~7 are always edge
Sensitivity type of the associated external interrupt source.
Edge sensitivity
Level sensitivity
Bit
31
Name
Type
Reset
Bit
15
Name EN
Type R/W
Reset
0
18
fo
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31
Re
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Bit
Name
Type
Reset
Bit
Name
Type
Reset
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MT6228 GSM/GPRS Baseband Processor Data Sheet
EINTn_CON
23
22
21
20
19
18
17
16
7
6
5
CNT
R/W
0
4
3
2
1
0
These registers control the de-bounce logic for external interrupt sources in order to minimize the possibility of false
activations. EINT4~7 have no de-bounce mechanism, therefore only bit POL is used.
CNT
POL
EN
3.6
3.6.1
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Note that n is from 0 to 7, and m is n + 2.
De-bounce duration in terms of number of 32 KHz clock cycles.
Activation type of the EINT source
0 Negative polarity
1 Positive polarity
De-bounce control circuit
0 Disable
1 Enable
Code Cache Controller
General Description
MT
K
A new subsystem consisting of cache and TCM (tightly coupled memory) is implemented in MT6228. This
subsystem is placed between MCU core and AHB bus interface, as shown in Figure 17.
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Cache
Controller
& MPU
TCM
cache
way 0
cache
way 1
AHB
bus
interface
cache
way 2
cache
way 3
AHB
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ARM7EJ
core
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MT6228 GSM/GPRS Baseband Processor Data Sheet
Figure 17 Cache and TCM subsystem
Re
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se
TCM is a high-speed (zero wait state) dedicated memory accessed by MCU exclusively. Because MCU can run at
104 MHz and on-chip bus runs at maximum of 52 MHz, latency occurs when MCU accesses memory or peripherals
through the on-chip bus. By moving timing critical code and data into TCM, MCU performance is increased and the
response to particular events can be guaranteed.
Another method to increase MCU performance is the introduction of cache. Cache is a small memory, keeping the
copy of external memory. If MCU reads a portion of cacheable data, the data is copied to cache. If MCU needs the
same data at a later time, it can retrieve the data directly from cache (called cache hit) instead of from external memory,
which takes a long time compared to accessing high-speed (zero wait state) cache memory.
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Since a large external memory maps to a small cache, cache can hold only a small portion of external memory. If
MCU accesses data not found in cache (called cache miss), some contents of cache must be dropped (flushed) and the
required data is transferred from external memory (called cache line fill) and stored in cache. On the other hand, TCM
is not a copy of external memory. The best way to use TCM is to put critical code/data in TCM in the memory usage
plan. After power on reset, the boot loader copies TCM contents from external storage (such as flash) to internal
TCM. If necessary, MCU can replace a portion of TCM content with other data on external storage in the runtime to
implement an “overlay” mechanism. TCM is also an ideal place to put stack data.
The sizes of TCM and cache can be set to one of 4 configurations:
TCM
128 KB
cache
cache
cache
cache
8KB
8 KB
8 KB
8KB
TCM
128 KB
2-way cache
TCM
TCM
cache
cache
8KB
8 KB
8KB
8 KB
TCM
1-way cache
TCM
TCM
TCM
cache
8KB
8 KB
8 KB
8KB
MT
K
128 KB
TCM
4-way cache
128 KB
no cache
TCM
TCM
TCM
TCM
8KB
8 KB
8KB
8 KB
Figure 18 Configurations of TCM and cache
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128KB TCM, 32KB cache
144KB TCM, 16KB cache
152KB TCM, 8KB cache
160KB TCM, 0KB cache
These configurations provide flexibility for software to adjust for optimum system performance.
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MT6228 GSM/GPRS Baseband Processor Data Sheet
cache
cache
cache
cache
8K
8K
8K
8K
cache
cache
TCM
TCM
TCM
128K
TCM
Re
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The address mapping of these memories is as follows:
Increasingly
adjacent
address.
No memory
holes.
Figure 19 Memory mapping of TCM and cache
3.6.2
TCM
TCM
TCM
TCM
TCM
TCM
Cache is transparent to MCU.
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In Figure 19, MCU could only access TCM explicitly.
cache
TCM
TCM
TCM
Organization of Cache
The cache system has the following features:
Write through (no write allocation)
Configurable 1/2/4 way set associative (8K/16K/32K)
Each way has 256 cache lines with 8 word line size (256*8*4=8KB)
19 bit tag address, 1 valid bit, for one cache line.
MT
K
One way of cache comprises of two memories: tag memory and data memory. Tag memory stores each line’s valid bit,
dirty bit and tag (upper part of address). Data memory stores line data. When MCU accesses memory, the address is
compared to the contents of tag memory. First the line index (address bit [12:5]) is used to locate a line, and then the
tag of the line is compared to upper part of address (bit [31:13]). If two parts match and valid bit is 1, it is a cache hit
and data from that particular way is sent back to MCU. This process is illustrated in the following figure:
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Address
31
13 12
54
8
19
V D Tag
Data
V D Tag
Data
V D Tag
Data
V D Tag
Data
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r
Index
0
1
2
0
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MT6228 GSM/GPRS Baseband Processor Data Sheet
253
254
255
32
Re
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se
19
4-to-1 multiplexor
Hit
Figure 20 Tag comparison of 4-way cache
Data
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If most memory accesses are cache hit, MCU could get data immediately without wait states and the overall system
performance is higher. There are several factors that may affect cache hit rate:
Cache size and the organization
The larger the cache size is, the higher the hit rate is. However the hit rate starts to saturate when cache size
is larger than a threshold size. Normally a cache size of 16KB and above and two or four ways achieve a
good hit rate.
Program behavior
If the system has several tasks that switch data quickly, it may cause cache contents to be flushed frequently.
Each time a new task is run, the cache holds the data. If the next task uses data in memory that occupies the
same cache entries as the previous task, the cache contents are flushed to store the data for the new task.
Interrupts also cause program flow to change dynamically. The interrupt handler code itself and the data it
processes may cause cache to flush some data used by the current task. Thus after exiting the interrupt
handler and returning to the current task, the flushed data may need to be re-cached, resulting performance
degradation.
MT
K
To help a software engineer tune system performance, the cache controller in MT6228 records the number of cache hits
and cacheable memory accesses. The cache hit rate can be obtained from these two numbers.
The cache sub system also has a module called MPU (memory protection unit). MPU can prevent illegal memory
access and specify which memory region is cacheable or non-cacheable. Two fields in CACHE_CON register control
the enable of MPU functions. MPU has its own registers to define memory region and associated regions. These
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settings only take effect after the enable bits in CACHE_CON are set to 1.
MPU portion of the specification.
3.6.3
Revision 1.0
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MT6228 GSM/GPRS Baseband Processor Data Sheet
For more details on the settings, refer to
Cache Operations
Upon power on, cache memory contains random numbers and cannot be used by MCU. Therefore MCU must have
some means to “clean” cache memory before enabling it. The cache controller provides a register which, when
written, can perform operations on cache memory. These are called cache operations, and include
fo
r
Invalidate one cache line
The user must give a memory address. If it is found within cache, that particular line is invalidated (valid bit
set to 0). Alternatively, the user can specify which set/way of cache to be invalidated.
Invalidate all cache lines
3.6.4
The cache controller hardware automatically clears all valid bits in
Re
lea
se
The user needs not to specify an address.
each tag memory.
Cache Controller Register Definition
CACHE base address is assumed 0x80700000 (subject to change).
CACHE+00h
Bit
15
14
Cache General Control Register
13
12
11
10
9
8
Name
CACHESIZE
Type
Reset
RW
00
7
6
5
4
CACHE_CON
3
2
1
0
CNTE CNTE
MCE
MPEN
N1
N0
N
RW
RW R/W R/W
0
0
0
0
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This register determines the cache size, cache hit counter and the enabling of MPU.
MT
K
CACHESIZE Cache Size Select
00 no cache (128KB TCM)
01 8KB, 1-way cache (120KB TCM)
10 16KB, 2-way cache (112KB TCM)
11 32KB, 4-way cache (96KB TCM)
CNTEN1 Enable cache hit counter 1.
If enabled, cache controller increments a 48-bit counter each time a cache hit occurs. This number can
provide a reference for performance measurement for tuning of application programs. This counter
increments only when the cacheable information is from MPU cacheable regions 4~7.
0 Disable
1 Enable
CNTEN0 Enable cache hit counter 0
If enabled, cache controller increments a 48-bit counter each time a cache hit occurs. This number can
provide a reference for performance measurement for tuning of application programs. This counter
increments only when the cacheable information is from MPU cacheable regions 0~3.
0 Disable
1 Enable
MPEN Enable MPU comparison of read/write permission setting.
If disabled, MCU can access any memory segment without any restriction. If enabled, MPU compares the
address of MCU to its setting. If an address falls into a restricted region, MPU stops this memory access and
sends an “ABORT” signal to MCU. Refer to the MPU portion of the specification for more details.
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Bit
Name
Type
Reset
Bit
Name
Type
Reset
Cache Operation
26
CACHE_OP
31
30
29
28
27
25
15
14
13
12
11
10
9
TADDR[15:5]
R/W
0
24
23
22
TADDR[31:16]
R/W
0
8
7
6
21
20
19
18
17
16
3
2
OP[3:0]
W
0
1
0
EN
W1
0
Re
lea
se
CACHE+04h
fo
r
0 Disable
1 Enable
MCEN Enable MPU comparison of cacheable/non-cacheable setting.
If disabled, MCU memory accesses are all non-cacheable, i.e., they go through AHB bus (except for TCM).
If enabled, the setting in MPU takes effect. If MCU accesses a cacheable memory region, the cache
controller returns the data in cache if found in cache, and retrieves the data through the AHB bus only if a
cache miss occurs. Refer to the MPU portion of the specification for more details.
0 Disable
1 Enable
5
4
This register defines the address and/or which kind of cache operations to perform. When MCU writes this register,
the pipeline of MCU is stopped for the cache controller to complete the operation. Bit 0 of the register must be
written 1 to enable the command.
CACHE+08h
CACHE_HCNT0
L
Cache Hit Count 0 Lower Part
31
30
29
28
27
26
15
14
13
12
11
10
MT
K
Bit
Name
Type
Reset
Bit
Name
Type
Co
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TADDR[31:5] Target Address
This field contains the address of invalidation operation. If OP[3:0]=0010, TADDR[31:5] is the address[31:5]
of a memory whose line is invalidated if it exists in the cache. If OP[3:0]=0100, TADDR[12:5] indicates the
set, while TADDR[19:16] indicates which way to clear:
0001 Way #0
0010 Way #1
0100 Way #2
1000 Way #3
OP[3:0]Operation
This field determines which cache operations are performed.
0001 Invalidate all cache lines
0010 Invalidate one cache line using address
0100 Invalidate one cache line using set/way
EN
Enable command
This enable bit must be written 1 to enable the command.
0 Disabled
1 Enabled
25
24
23
22
CHIT_CNT0[31:16]
R/W
0
9
8
7
6
CHIT_CNT0[15:0]
R/W
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21
20
19
18
17
16
5
4
3
2
1
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Reset
0
CACHE_HCNT0
U
Cache Hit Count 0 Upper Part
31
30
29
28
27
26
25
15
14
13
12
11
10
9
24
23
RESERVED
22
21
20
19
18
8
7
6
CHIT_CNT0[47:32]
R/W
0
5
4
3
2
17
16
1
0
fo
r
CACHE+0Ch
Bit
Name
Type
Reset
Bit
Name
Type
Reset
Revision 1.0
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MT6228 GSM/GPRS Baseband Processor Data Sheet
Re
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When the CNTEN0 bit in CACHE_CON register is set to 1 (enabled), this register counts each cache hit until it is
disabled. If the value increases over the maximum value (0xffffffffffff), the counter rolls over to 0 and continues
counting. The 48-bit counter provides a recording time of 31 days even if MCU runs at 104 MHz and every cycle is a
cache hit.
Note that before enabling the counter, it is recommended to write the initial value of zero to the counter.
CHIT_CNT0[47:0] Cache Hit Count 0
WRITE Writing any value to CACHE_HCNT0L or CACHE_HCNT0U clears CHIT_CNT0 to all zeros
READ Current counter value
Bit
Name
Type
Reset
Bit
Name
Type
Reset
31
30
15
14
CACHE+14h
Bit
Name
Type
Reset
Bit
Name
Type
Reset
31
30
15
14
CACHE_CCNT0
L
Cacheable Access Count 0 Lower Part
29
28
27
26
25
24
23
22
CACC_CNT0[31:16]
R/W
0
9
8
7
6
CACC_CNT0[15:0]
R/W
0
Co
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CACHE+10h
13
12
11
10
21
20
19
18
17
16
5
4
3
2
1
0
CACHE_CCNT0
U
Cacheable Access Count 0 Upper Part
29
28
27
26
25
24
23
RESERVED
22
21
20
19
18
17
16
13
12
11
10
9
8
7
6
CACC_CNT0[47:32]
R/W
0
5
4
3
2
1
0
MT
K
When the CNTEN0 bit in CACHE_CON register is set to 1 (enabled), this register is incremented at each cacheable
memory access (whether a cache hit or cache miss). If the value increases over the maximum value (0xffffffffffff), the
counter rolls over to 0 and continues counting. For 104 MHz MCU speed, if all memory accesses are cacheable and
cache hits, this counter overflows after (2^48) * 9.6ns = 31 days (the shortest time for the counter to overflow). In a
more realistic case, the system encounters cache misses, non-cacheable accesses, and idle mode that delay the counter
overflow.
CACC_CNT0[47:0] Cache Access Count 0
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WRITE Writing any value to CACHE_CCNT0L or CACHE_CCNT0U clears CACC_CNT0 to all zeros
READ Current counter value
The best way to use CACHE_HCNT0 and CACHE_CCNT0 is to set zero as initial value in both registers, enable both
counters (set CNTEN0 to 1), run a portion of program to be benchmarked, stop the counters and retrieve their values.
During this period,
Cache hit rate =
CACHE _ HCNT
× 100% .
CACHE _ CCNT
fo
r
The cache hit rate value may help tune the performance of an application program.
Note that CHIT_CNT0 and CACC_CNT0 only increment if the cacheable attribute is defined in MPU cacheable
regions 0~3.
31
30
29
28
27
26
15
14
13
12
11
10
CACHE+1Ch
Bit
Name
Type
Reset
Bit
Name
Type
Reset
31
30
15
14
25
24
23
22
CHIT_CNT1[31:16]
R/W
0
9
8
7
6
CHIT_CNT1[15:0]
R/W
0
21
20
19
18
17
16
5
4
3
2
1
0
CACHE_HCNT1
U
Cache Hit Count 1 Upper Part
29
28
27
26
25
24
23
RESERVED
22
21
20
19
18
17
16
8
7
6
CHIT_CNT1[47:32]
R/W
0
5
4
3
2
1
0
Co
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Bit
Name
Type
Reset
Bit
Name
Type
Reset
CACHE_HCNT1
L
Cache Hit Count 1 Lower Part
Re
lea
se
CACHE+18h
13
12
11
10
9
When the CNTEN1 bit in CACHE_CON register is set to 1 (enabled), this register counts each cache hit until it is
disabled. If the value increases over the maximum value (0xffffffffffff), the counter rolls over to 0 and continues
counting. The 48-bit counter provides a recording time of 31 days even if MCU runs at 104 MHz and every cycle is a
cache hit.
Note that before enabling the counter, it is recommended to write the initial value of zero to the counter.
CHIT_CNT1[47:0] Cache Hit Count
WRITE Writing any value to CACHE_HCNT1L or CACHE_HCNT1U clears CHIT_CNT1 to all zeros.
READ Current counter value
Bit
Name
Type
Reset
Bit
CACHE_CCNT1
L
Cacheable Access Count 1 Lower Part
MT
K
CACHE+20h
31
30
29
28
27
26
15
14
13
12
11
10
25
24
23
22
CACC_CNT1[31:16]
R/W
0
9
8
7
6
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21
20
19
18
17
16
5
4
3
2
1
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Name
Type
Reset
CACC_CNT1[15:0]
R/W
0
CACHE_CCNT1
U
Cacheable Access Count 1 Upper Part
31
30
29
28
27
26
25
24
23
RESERVED
22
21
20
15
14
13
12
11
10
9
8
7
6
CACC_CNT1[47:32]
R/W
0
5
4
19
18
17
fo
r
CACHE+24h
Bit
Name
Type
Reset
Bit
Name
Type
Reset
Revision 1.0
Ko
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MT6228 GSM/GPRS Baseband Processor Data Sheet
3
2
1
16
0
CACC_CNT1[47:0] Cache Access Count 1
Re
lea
se
When the CNTEN1 bit in CACHE_CON register is set to 1 (enabled), this register is incremented at each cacheable
memory access (whether a cache hit or a cache miss). If the value increases over the maximum value (0xffffffffffff),
the counter rolls over to 0 and continues counting. For 104 MHz MCU speed, if all memory accesses are cacheable
and cache hits, this counter overflows after (2^48) * 9.6ns = 31 days (the shortest time for the counter to overflow). In
a more realistic case, the system encounters cache misses, non-cacheable accesses, and idle mode that delay the counter
overflow.
Co
nf
id
en
tia
l
WRITE Writing any value to CACHE_CCNT1L or CACHE_CCNT1U clears CACC_CNT1 to all zeros
READ Current counter value
The best way to use CACHE_HCNT1 and CACHE_CCNT1 is to set zero as initial value in both registers, enable both
counters (set CNTEN1 to 1), run a portion of program to be benchmarked, stop the counters and retrieve their values.
During this period,
Cache hit rate =
CACHE _ HCNT
× 100% .
CACHE _ CCNT
The cache hit rate value may help tune the performance of application program.
Note that CHIT_CNT1 and CACC_CNT1 only increment if the cacheable attribute is defined in MPU cacheable
regions 4~7.
3.7
3.7.1
MPU
General Description
The purpose of MPU is to provide protection mechanism and cacheable indication of memory.
include
The features of MPU
8-entry protection settings.
MT
K
Determine if MCU can read/write a memory region. If the setting does not allow MCU access to a
particular memory address, MPU stops the memory access and issues an “ABORT” signal to MCU, forcing
it to enter “abort” mode. The exception handler must then process the situation.
8-entry cacheable settings.
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Determine if a memory region is cacheable or not. If cacheable, MCU keeps a small copy in its cache after
read accesses. If MCU requires the same data later, it can retrieve the data from the high-speed local copy,
instead of from low-speed external memory.
Normally the protection and cacheable attributes are combined together for the same address range, as in the example
of ARM946E. For greater flexibility, the MPU in MT6228 provides independent protection and cacheable settings.
That is to say, the memory regions defined for memory protection and for cacheable region are different and
independent of each other.
fo
r
The 4GB memory space is divided to 16 memory blocks of 256 MB, i.e., MB0~MB15. EMI uses MB0~MB3;
SYSRAM uses MB4; IDMA uses MB5; peripherals and other hardware occupy MB6~MB9; TCM (tightly-coupled
memory used by MCU exclusively) uses MB10. The characteristics of these memory blocks are listed below:
Read/write protection setting
MB0~MB4 and MB10 are determined by MPU.
Cacheable setting
MB4 and above are always non-cacheable.
MT
K
Co
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MB0~MB3 are determined by MPU.
Re
lea
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MB5 and above (except MB10) are always readable/writeable.
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3.7.2
Protection Settings
TCM
MB10
Region 4
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MT6228 GSM/GPRS Baseband Processor Data Sheet
Region 4 base address
MB9
fo
r
Peripheral
~
MB6
IDMA
MB4
SYSRAM
Region 3
Region 3 base address
Re
lea
se
MB5
Region 2
MB3
EMI
~
MB0
Region 2 base address
Region 1
Region 1 base address
Region 0
Co
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Region 0 base address
readable/writeable
non-readable/writeable
readable/non-writeable
non-readable/non-writeable
Figure 21 Protection setting
Figure 21 shows the protection setting in each memory block. Five regions are defined in the figure. Note that each
region can be continuous or non-continuous to each other, and those address ranges not covered by any region are set to
be readable/writeable automatically. One restriction exists: different regions must not overlap.
The user can define maximum 8 regions in MB0~MB4 and MB10. Each region has its own setting defined in a 32-bit
register:
10
MT
K
31
base address
7
00
6 5
prot
1
size
0
EN
Region base address (22 bits)
Region size (5 bits)
Region protection attribute (2 bits)
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Enable bit (1 bit)
MPU aborts MCU if it accesses MB11~MB15 regions.
3.7.2.1
Region base address
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MT6228 GSM/GPRS Baseband Processor Data Sheet
3.7.2.2
Region size
The bit encoding of region size and its relationship with base address are listed as follows.
4KB
8KB
16KB
32KB
64KB
128KB
256KB
512KB
1MB
2MB
4MB
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
Base address
Bit [31:10] of region start address
Bit [31:11] of region start address
Re
lea
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Bit encoding
00000
00001
Bit [31:12] of region start address
Bit [31:13] of region start address
Bit [31:14] of region start address
Bit [31:15] of region start address
Bit [31:16] of region start address
Bit [31:17] of region start address
Bit [31:18] of region start address
Bit [31:19] of region start address
Bit [31:20] of region start address
Bit [31:21] of region start address
Bit [31:22] of region start address
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Region size
1KB
2KB
fo
r
The region base address defines the start of the memory region. The user needs only to specify several upper address
bits. The number of valid address bits depends on the region size. The user must align the base address to a
region-size boundary. For example, if a region size is 8 KB, its base address must be a multiple of 8KB.
Table 13 Region size and bit encoding
3.7.2.3
Region protection attribute
This attribute has two bits.
The MSB determines read access permission, and the LSB write access permission.
Bit encoding
00
10
01
11
Permission
non-readable / non-writeable
readable / non-writeable
non-readable / writeable
readable / writeable
Table 14 Region protection attribute bit encoding
So it is
MT
K
Note that bit encoding 11b allows full read/write permission, which is the case when no region is specified.
recommended to only specify regions with protection attribute 00b, 10b or 01b.
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3.7.3
Cacheable Settings
TCM
MB10
MB9
Peripheral
~
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MT6228 GSM/GPRS Baseband Processor Data Sheet
IDMA
MB4
SYSRAM
MB3
EMI
~
Region 2
Region 2 base address
Re
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se
MB5
fo
r
MB6
Region 1
MB0
Region 1 base address
Region 0
Region 0 base address
uncacheable
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cacheable
Figure 22 Cacheable setting
Figure 22 shows the cacheable setting in each memory block. Three regions are defined in the figure. Note that
each region can be continuous or non-continuous to each other, and those address ranges not covered by any region are
set to be non-cacheable automatically. One restriction exists: different regions must not overlap.
The user can define maximum 8 regions in MB0~MB3.
31
Each region has its own setting defined in a 32-bit register:
10
base address
000
6 5
C
1
size
0
EN
Region base address (22 bits)
Region size (5 bits)
Region cacheable attribute (1 bit)
Enable bit (1 bit)
MT
K
The region base address and region size bit encoding are the same as those of protection setting. The user must also
align the base address to a region-size boundary. The cacheable attribute has the following meaning.
Bit encoding
0
1
Attribute
uncacheable
cacheable
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Table 15 Region cacheable attribute bit encoding
3.7.4
MPU Register Definition
MPU base address is assumed 0x80701000 (subject to change).
Bit
Name
Type
Reset
Bit
Name
Type
Reset
Protection setting for region 0
29
28
31
30
27
26
25
24
23
22
BASEADDR[31:16]
RW
21
20
15
14
13
12
11
BASEADDR[15:10]
RW
10
9
5
4
8
30
29
15
28
18
3
2
SIZE[4:0]
RW
00000
Protection setting for region 1
17
1
16
0
EN
RW
0
MPU_PROT1
27
26
25
24
23
22
BASEADDR[31:16]
RW
21
20
14
13
12
11
BASEADDR[15:10]
RW
10
9
5
4
MT
K
31
Co
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BASEADDR
Base address of this region
ATTR Protection attribute
00 non-readable / non-writeable
01 non-readable / writeable
10 readable / non-writeable
11 readable / writeable
SIZE Size of this region
00000 1 KB
00001 2 KB
00010 4 KB
00011 8 KB
00100 16 KB
00101 32 KB
00110 64 KB
00111 128 KB
01000 256 KB
01001 512 KB
01010 1 MB
01011 2 MB
01100 4 MB
EN
Enable this region
0 Disable
1
Enable
MPU+0004h
7
6
ATTR[1:0]
RW
11
19
Re
lea
se
This register sets protection attributes for region 0.
Bit
Name
Type
Reset
Bit
Name
Type
Reset
MPU_PROT0
fo
r
MPU+0000h
Revision 1.0
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8
7
6
ATTR[1:0]
RW
11
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19
18
17
16
3
2
SIZE[4:0]
RW
00000
1
0
EN
RW
0
MediaTek Inc. Confidential
Revision 1.0
This register sets protection attributes for region 1.
MPU+0008h
29
28
MPU_PROT2
31
30
27
26
25
24
23
22
BASEADDR[31:16]
RW
21
20
15
14
13
12
11
BASEADDR[15:10]
RW
10
9
5
4
8
7
6
ATTR[1:0]
RW
11
This register sets protection attributes for region 2.
MPU+000Ch
Protection setting for region 3
29
28
30
27
26
25
24
23
22
BASEADDR[31:16]
RW
21
20
15
14
13
12
11
BASEADDR[15:10]
RW
10
9
5
4
This register sets protection attributes for region 3.
MPU+0010h
7
6
ATTR[1:0]
RW
11
19
31
30
29
28
27
15
14
13
12
11
BASEADDR[15:10]
RW
26
10
25
24
23
22
BASEADDR[31:16]
RW
21
20
9
5
4
8
16
1
0
EN
RW
0
18
17
16
3
2
SIZE[4:0]
RW
00000
1
0
EN
RW
0
Protection setting for region 4
Co
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Bit
Name
Type
Reset
Bit
Name
Type
Reset
17
MPU_PROT3
31
8
18
3
2
SIZE[4:0]
RW
00000
Re
lea
se
Bit
Name
Type
Reset
Bit
Name
Type
Reset
19
fo
r
Bit
Name
Type
Reset
Bit
Name
Type
Reset
Protection setting for region 2
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7
6
ATTR[1:0]
RW
11
19
MPU_PROT4
18
17
16
3
2
SIZE[4:0]
RW
00000
1
0
EN
RW
0
This register sets protection attributes for region 4.
MPU+0014h
Bit
Name
Type
Reset
Bit
Name
Type
Reset
Protection setting for region 5
29
28
MPU_PROT5
31
30
27
26
25
24
23
22
BASEADDR[31:16]
RW
21
20
15
14
13
12
11
BASEADDR[15:10]
RW
10
9
5
4
8
7
6
ATTR[1:0]
RW
11
19
18
17
16
3
2
SIZE[4:0]
RW
00000
1
0
EN
RW
0
This register sets protection attributes for region 5.
Protection setting for region 6
MT
K
MPU+0018h
Bit
Name
Type
Reset
Bit
MPU_PROT6
31
30
29
28
27
26
25
24
23
22
BASEADDR[31:16]
RW
21
20
19
18
17
16
15
14
13
12
11
10
9
5
4
3
2
1
0
8
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Name
Type
Reset
BASEADDR[15:10]
RW
ATTR[1:0]
RW
11
SIZE[4:0]
RW
00000
EN
RW
0
This register sets protection attributes for region 6.
Protection setting for region 7
29
28
30
27
26
25
24
23
22
BASEADDR[31:16]
RW
21
20
15
14
13
12
11
BASEADDR[15:10]
RW
10
9
5
4
8
This register sets protection attributes for region 7.
MPU+0040h
Bit
Name
Type
Reset
Bit
Name
Type
Reset
MPU_PROT7
31
7
6
ATTR[1:0]
RW
11
19
Cacheable setting for region 0
31
30
29
28
27
26
25
24
23
22
BASEADDR[31:16]
RW
21
20
15
14
13
12
11
BASEADDR[15:10]
RW
10
9
5
4
This register sets cacheable attributes for region 0.
8
7
6
C
RW
0
18
3
2
SIZE[4:0]
RW
00000
Re
lea
se
Bit
Name
Type
Reset
Bit
Name
Type
Reset
17
fo
r
MPU+001Ch
Revision 1.0
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MT6228 GSM/GPRS Baseband Processor Data Sheet
19
1
16
0
EN
RW
0
MPU_CACHE0
18
17
16
3
2
SIZE[4:0]
RW
00000
1
0
EN
RW
0
MT
K
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BASEADDR
Base address of this region
C
Cacheable attribute
0 Uncacheable
1 Cacheable
SIZE Size of this region
00000 1 KB
00001 2 KB
00010 4 KB
00011 8 KB
00100 16 KB
00101 32 KB
00110 64 KB
00111 128 KB
01000 256 KB
01001 512 KB
01010 1 MB
01011 2 MB
01100 4 MB
EN
Enable this region
0 Disable
1 Enable
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Bit
Name
Type
Reset
Bit
Name
Type
Reset
Cacheable setting for region 1
29
28
MPU_CACHE1
31
30
27
26
25
24
23
22
BASEADDR[31:16]
RW
21
20
15
14
13
12
11
BASEADDR[15:10]
RW
10
9
5
4
8
7
6
C
RW
0
This register sets cacheable attributes for region 1.
MPU+0048h
29
28
30
27
26
25
24
23
22
BASEADDR[31:16]
RW
21
15
14
13
12
11
BASEADDR[15:10]
RW
10
9
5
This register sets cacheable attributes for region 2.
MPU+004Ch
7
20
19
29
28
6
C
RW
0
4
31
30
27
26
25
24
23
22
BASEADDR[31:16]
RW
21
20
15
14
13
12
11
BASEADDR[15:10]
RW
10
9
5
4
8
16
1
0
EN
RW
0
18
17
16
3
2
SIZE[4:0]
RW
00000
1
0
EN
RW
0
Cacheable setting for region 3
7
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Bit
Name
Type
Reset
Bit
Name
Type
Reset
17
MPU_CACHE2
31
8
18
3
2
SIZE[4:0]
RW
00000
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Bit
Name
Type
Reset
Bit
Name
Type
Reset
Cacheable setting for region 2
19
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MPU+0044h
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6
C
RW
0
19
MPU_CACHE3
18
17
16
3
2
SIZE[4:0]
RW
00000
1
0
EN
RW
0
This register sets cacheable attributes for region 3.
MPU+0050h
Bit
Name
Type
Reset
Bit
Name
Type
Reset
Cacheable setting for region 4
29
28
MPU_CACHE4
31
30
27
26
25
24
23
22
BASEADDR[31:16]
RW
21
20
15
14
13
12
11
BASEADDR[15:10]
RW
10
9
5
4
8
7
6
C
RW
0
19
18
17
16
3
2
SIZE[4:0]
RW
00000
1
0
EN
RW
0
This register sets cacheable attributes for region 4.
MPU+0054h
29
28
MPU_CACHE5
31
30
27
26
25
24
23
22
BASEADDR[31:16]
RW
21
20
15
14
13
12
11
BASEADDR[15:10]
RW
10
9
5
4
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Bit
Name
Type
Reset
Bit
Name
Type
Cacheable setting for region 5
8
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6
C
RW
19
18
17
16
3
2
SIZE[4:0]
RW
1
0
EN
RW
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Reset
0
00000
0
This register sets cacheable attributes for region 5.
Bit
Name
Type
Reset
Bit
Name
Type
Reset
Cacheable setting for region 6
29
28
MPU_CACHE6
31
30
27
26
25
24
23
22
BASEADDR[31:16]
RW
21
20
15
14
13
12
11
BASEADDR[15:10]
RW
10
9
5
4
8
7
6
C
RW
0
This register sets cacheable attributes for region 6.
Bit
Name
Type
Reset
Bit
Name
Type
Reset
Cacheable setting for region 7
31
30
29
28
27
26
25
24
23
22
BASEADDR[31:16]
RW
21
20
15
14
13
12
11
BASEADDR[15:10]
RW
10
9
5
4
This register sets cacheable attributes for region 7.
3.8.1
7
6
C
RW
0
17
16
1
0
EN
RW
0
19
MPU_CACHE7
18
17
16
3
2
SIZE[4:0]
RW
00000
1
0
EN
RW
0
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3.8 Data Cache
8
18
3
2
SIZE[4:0]
RW
00000
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MPU+005Ch
19
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MPU+0058h
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MT6228 GSM/GPRS Baseband Processor Data Sheet
General Description
The data cache is an 8-kilobyte, 8-way write-back cache that bridges the multi-layer Advanced High-speed Bus (AHB)
and the External Memory Interface (EMI). Requests from the AHBs are processed by the data cache before being
forwarded to the external bus. The two main objectives of the data cache are to reduce activity on the external bus,
and to maximize the throughput of the external bus.
The data cache contains a copy of part of the external memory. If the required data is in data cache, the data is
returned from the cache without issuing a request to external memory. This intervention on the cache’s part reduces
activity on the external bus without losing data throughput. The data cache converts all types of bus read requests into
a single type of 16-byte burst read request for the EMI. The EMI converts a 16-byte burst read request to a 16-byte
page-mode or 16-byte burst-mode access request on the external bus, depending on the type of memory on the external
bus. Page-mode and burst-mode access are more efficient ways to access external memory. The system can retrieve
more data in the same amount of time, thereby increasing throughput. The simple request types also simplify the
EMI’s design, reducing cost and improving timing.
MT
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If the data request is a data cache hit (the requested data is found in the cache), the data is returned from the data cache
in one cycle for the DMA and GMC busses, and in two cycles for an MCU running at 104MHz. These latencies are
much shorter than for an external bus access.
Figure 23 shows an overview of the bus architecture.
engines via the three AHBs.
The data cache serves all of the bus masters and multi-media
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MT6228 GSM/GPRS Baseband Processor Data Sheet
Figure 23 Overview of the Bus Architecture
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The data cache and EMI are connected by four buses. These four interfaces operate independently of each other;
requests from the interfaces can be issued at the same time. Three of the four buses are standard AHBs for reading
data from external memory, and the other is a request-acknowledgement interface for the write buffer. The EMI can
see the next request while current request is still being processed. With the capability of seeing pending requests, the
EMI can optimize its access schedule to make memory access more efficient.
The data cache comprises four parts: the AHB interface, the main controller, the line filler, and the write buffer (Figure
24).
DATA CACHE
MCU burst read
AHB I/F
1-stage
ADDR
ADDR
Queue
Queue
MCU BUS
AHB I/F
DMA BUS
GMC BUS
DATA cache
Main Controller
MCU line filler
RDATA FIFO
Line Filler
Write Buffer
EMI
AHB I/F
DG line filler
REQ/ACK
Write buffer
MT
K
Figure 24 Data Cache Architecture
The AHB interface’s responsibilities are to interface with the AHBs, to prioritize incoming requests from the buses, and
to shake hands with the Line Filler for missed data. Requests from the three buses are prioritized before entering the
main controller of the cache: requests from the MCU bus take precedence over the requests from the DMA and GMC
buses.
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The main controller is the core of the data cache: its sophisticated state machine is designed to handle the control of
cache TAG memory and DATA memory; hand-shaking with the AHB interface, the write buffer, and line fillers; and
debugging functions. The main controller features a “hit under miss” non-blocking cache: a cache miss from an AHB
does not block the other buses’ access to the cache. When a cache miss occurs, the main controller enters Line Fill
Phase: the replaced cache line is flushed (written to target memory as required), and the main controller issues a line fill
request to the Line Filler. Once the Line Filler accepts the request, the main control becomes available again for
access while the line fill is executed in background. The data cache is still accessible during the line fill.
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Two Line Fillers are implemented. They allow two cache lines being replaced concurrently, while leaving the cache
still accessible in the meantime. This feature is especially useful for a system with many bus masters. Missed data is
returned from Line Filler to the AHB interface directly to reduce the latency.
3.8.2
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The data cache contains an eight-stage write buffer. Each stage stores up to 32-bit data. The write buffer favors
sequential tags for each buffer stage. Data with sequential tags has the highest priority in the EMI: the EMI can write
data sequentially into the same row of the SDRAM memory, reducing the write time by saving on the time required to
pre-charge and activate a row.
Specification and Main Features
The MT6228 data cache implementation includes the following features:
•
8-kilobyte, 8-way write-back data cache with random cache replacement scheme.
•
64 cache lines for each cache way, and 16 bytes per cache line.
•
2 dirty bits per cache line.
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The two dirty bits indicate whether the upper 8-byte and lower 8-byte segment of a cache line have been changed
(Figure 25). Only half of the cache line is flushed before replacement if that half-line has been changed,
shortening the access latency and reducing activity on the external memory bus.
Figure 25 Two Dirty Bits per Cache Line
•
Four read/write ports to the EMI.
MT
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The EMI sees the next queued memory access request before the current request has been completed, and
pre-schedules the access based on requests from the four access ports. This capability is especially useful for
SDRAM type memory, where pre-charge and row activation for the next request can be executed in advance to
shorten latency.
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•
Missed data is returned first.
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The data requested during a cache miss is filled by the line filler and returned to the requestor starting at the
missed data.
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For example: the MCU requests data at address 0x4, but the request results in a cache miss. The data cache
dispatches a 16-byte burst request starting from 0x4 to the EMI. The data located at address 0x4 is returned first,
followed by that at addresses 0x8, 0xC, then 0x0 (Figure 26). The return of the requested data first shortens the
access latency.
Figure 26 Missed Data Is Returned First
•
Background cache line fill.
The data cache has two stand-alone line fillers, each of which can execute a cache line fill upon request from the
main controller individually. Other buses can still access the data cache during the line fill, maximizing
throughput of the data cache.
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For example: two sequential requests come from the MCU and the GMC. The MCU request is accepted before
GMC and causes a cache miss. The cache main controller allocates a cache line for the MCU data. If the cache
line is dirty, the main controller flushes the line first, then hands over the line fill request to the Line Filler. The
main controller is now available to accept the next request from the GMC (Figure 27). If the GMC request
results in another cache miss, the line fill request is issued to the second Line Filler. The main controller is still
available to process the next request from a bus. The main controller is blocked only when a third cache miss
occurs before the two previous line fills have been completed.
DATA CACHE
MCU burst read
AHB I/F
1-stage
ADDR
ADDR
Queue
Queue
MCU BUS
AHB I/F
DMA BUS
MCU line filler
RDATA FIFO
Line Filler
Write Buffer
EMI
AHB I/F
DG line filler
REQ/ACK
Write buffer
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GMC BUS
DATA cache
Main Controller
Figure 27 Background Cache Line Fill
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•
Debug support.
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MT6228 GSM/GPRS Baseband Processor Data Sheet
The data cache supports a variety of debugging functions and cache tag and data memory read access via the
Advanced Peripheral Bus (APB). The following functions can be executed anywhere and anytime without
restriction:
•
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Invalidate all cache lines.
Invalidate and clean all cache lines.
Invalidate a single cache line by specifying the set/way or address.
Invalidate and clean a single cache line by specifying the set/way or address.
Read a cache tag by specifying the set/way or address.
Read cache data by specifying the set/way or address.
Drain the write buffer.
Write buffer flushed before MCU burst read (FBBR mode).
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The data cache is specially optimized for MCU code execution, thus the user is recommended to set only code and
read-only (RO) data as code cache cacheable (refer to the Code Cache section for the definition of a cacheable
region). For regions of cacheable memory, requests are forwarded directly to the EMI through the “MCU burst
read” path (Figure 24). The requests can be accepted before write buffer is flushed, shortening access latency.
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If read-write (RW) data is set as code cache cacheable, data inconsistency may occur. Consider a write request
(WB2) followed by a read request (L1C) with the same memory address, both issued by the MCU (Figure 28 (a)).
The write data (WB2) is queued in the data cache’s write buffer, and the read request is forwarded directly to the
EMI. Because the write buffer queue contains other data ahead of WB2, WB2 is actually written to target
memory after L1C has been executed. Therefore, the MCU receives outdated data, and the consistency problem
occurs.
!"
!"
#
$ %
!"
#
$ %
#
!"
#
(a)
(b)
Figure 28 Data Consistency Problem for Cacheable RW
MT
K
The data cache provides an Flush Buffer Before Read (FBBR) mode that allows RW data to be set as code cache
cacheable without compromising data consistency. When in FBBR mode, MCU read requests are not issued to
the EMI until the write buffer is empty. This suspension of the read request prevents it from being executed
before the write request and solves the data consistency problem. Figure 28(b) shows L1C executed after WB2.
Note that in FBBR mode, more cycles are required to complete a read request because of flush cycles before the
read operation. Thus MCU access latency may increase, and MCU performance may be reduced.
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$&
'+ *
%'%( #
)
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#
*
$&
*
%'%( #
)
$ %
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#
!"
•
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Figure 29 Increased Latency of FBBR Mode Due to Write Buffer Flush
DMA and GMC AHB interfaces allow the clock ratio to switch dynamically between 1:2 and 1:1.
The maximum clock rate of the DMA and GMC buses is 52 MHz; the maximum clock rate of data cache is
104 MHz. A clock ratio bridge is implemented in the AHB interface of the data cache to convert requests and
data to different clock rates. The clock ratio of the DMA or GMC bus and data cache can be either 1:2 or 1:1.
If the data cache clock rate is lower than 52 MHz, the clock rate of DMA or GMC bus must be the same as that of
the data cache and the clock ratio is 1:1. If the data cache clock rate is 104 MHz, the AHB’s clock rate can only
be 52 MHz, and the clock ratio is 1:2. The clock ratio can be switched between 1:2 and 1:1 dynamically without
restriction, reducing the overhead for system clock rate switching software.
3.8.3
NOR flash Programming
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When data cache is enabled, an external memory access request may not actually result in physical transaction occuring
on external memory bus. For instance, when MCU issues a read request to external memory, if the request hits data
cache, the data will be returned from data cache directly instead of reading it from external memory. This means no
request took place on the external bus.
Figure 30 illustrates the normal NOR flash programming sequence. These access must be actually executed to the
NOR flash memory interface. However, as mentioned before, an internal bus request may not be reflected on the
external bus when caches are enabled, and will therefore result in MCU not being able to program the NOR flash.
write
address 0x0000aaa
data
0xaa
write
write
write
read
address 0x0000555
address 0x0000aaa
address 0x0000078
address 0x0000078
data
0x55
data
0xa0
data
0x1234
data
Figure 30 NOR flash programming sequence
MT
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To solve the problem, an IO command mode is designed in data cache. When data cache receive a memory request with
“1” at address bit 26, data cache will treat the request as an IO command. For an IO command, data cache will read or
write the external memory immediately regardless of the hit/miss condition. In addition, data cache will invalidate the
hit cache line for an IO write command. This can prevent data inconsistence between data cache and external memory.
Next read data from the same address will return from external memory, not from data cache.
illustrates the NOR flash programming using IO command. To issue an IO command, software has to OR original
address bit 26 with “1”. In the example, the address to be programmed is 0x0078. To program it with IO command, the
address bit 26 is set to “1”, and the address becomes 0x4000078.
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write
write
write
write
address 0x4000aaa
address 0x4000555
address 0x4000aaa
address 0x4000078
data
0xaa
data
0x55
data
0xa0
data
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read
address 0x4000078
0x1234
data
Figure 31 IO command for NOR flash programming
3.8.4
Register Definitions
Register Address
Register Function
L2C+0000h
Data cache control register
L2C+0004h
Data cache target register
L2C+0008h
Data cache status register
L2C+000Ch
Data cache tag register
L2C+0010h
Data cache data register
L2C+0014h
Data cache mode register
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Table 16 summarizes the registers used by the data cache.
Acronym
L2C_CON
L2C_TARGET
L2C_STA
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L2C_TAG
L2C_DATA
L2C_MODE
Table 16 Data Cache Registers
L2C+0000h
Data Cache Control Register
L2C_CON
31
EN
W
15
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
14
13
12
11
10
9
8
7
VALUE
R/W
6
5
4
3
2
1
0
CMD
Requests an operation on the data cache. Four functions are provided:
0000 Invalidate and clean the data cache.
To invalidate means to clear the valid bit of a cache line. To clean means to write the cache line data to
destination memory if dirty.
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Bit
Name
Type
Bit
Name
Type
CMD
R/W
VALUE[3:0]
Function
0100
Invalidate a single cache line with the set/way specified in the L2C_TARGET register.
0110
Invalidate and clean a single cache line with the set/way specified in the
L2C_TARGET register.
1100
Invalidate a single cache line with the address specified in the L2C_TARGET register.
The data cache finds the cache line with the same address and invalidates it.
1110
Invalidate and clean a single cache line with the address specified in the
L2C_TARGET register. The data cache finds the cache line with the same address,
and cleans and invalidates it.
0101
Invalidate all cache lines.
0111
Invalidate and clean all cache lines.
Read the data cache. Either TAG or DATA can be read.
VALUE[1:0]
Function
00
Read a TAG with the set/way specified in the L2C_TARGET register.
01
Read cache data with the set/way specified in the L2C_TARGET register.
10
Read a TAG with address specified in the L2C_TARGET register.
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0001
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11
Read cache data at the address specified in the L2C_TARGET register.
0010 Drain the write buffer.
0011 Configure the MODE bit.
VALUE
Bit
7
6
5
4
Name
FBBR
Type
Reset
W
0
1
0
MPEG4
BYPASS
W
0
W
1
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Bypass the data cache. The write buffer is still activated.
MPEG4 mode.
Gate DMA and GMC requests. Any requests from the DMA and GMC are suspended.
Normally only half a cache line is set as dirty when data is written to only half of the
cache line. When this mode is enabled, the entire cache line is set as dirty when data
is written to the line.
Flush the write buffer before issuing an MCU burst read (L1 cache line fill) to the EMI.
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BYPASS
MPEG4
GATEDG
DIRTYALL
3
2
DIRTYAL
GATEDG
L
W
W
0
0
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FBBR
Others Reserved.
VALUE Cooperates with CMD to specify a function.
EN
Executes the command specified by CMD and VALUE. While EN is set, the values of CMD and VALUE
are interpreted as a command: the data cache executes the command CMD with the parameter VALUE.
L2C+0004h
31
30
29
28
15
14
13
12
26
25
24
10
9
8
23
7
21
20
19
18
17
16
6
5
4
3
2
WORD
R/W
1
0
21
20
19
18
17
16
5
4
3
2
WORD
R/W
1
0
Data Cache Target Register (ADDRESS)
31
30
15
14
29
28
27
26
25
24
13
12
11
10
9
8
R/W
L2C_TARGET
22
IDX
R/W
L2C+0004h
Bit
Name
Type
Bit
Name
Type
27
SET
R/W
11
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Bit
Name
Type
Bit
Name
Type
Data Cache Target Register (SET/WAY)
23
22
TAG
R/W
7
6
IDX
R/W
L2C_TARGET
Specifies a SET/WAY or address for a single cache invalidation or TAG/DATA read.
L2C+0008h
Bit
Name
Type
Reset
Bit
Name
Data Cache Status Register
31
30
15
14
29
28
27
26
25
24
23
22
21
20
19
13
12
11
10
9
8
7
6
5
4
3
18
2
MISS
R
0
MT
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Type
Reset
BUSY
L2C_STA
Indicates that the current command is still being processed.
command is finished.
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16
1
0
GATE
BUSY
DG
R
R
0
0
The register is cleared when the current
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GATEDG
Indicates that DMA and GMC requests are gated. GATEDG is valid only when the BUSY register is
clear.
Indicates HIT or MISS of the commands for a single cache invalidation or TAG/DATA read. MISS is
valid only when the BUSY register is clear.
L2C+000Ch
Data Cache TAG Register
L2C_TAG
31
30
29
28
27
26
25
24
23
22
21
20
15
14
13
12
11
10
9
8
7
6
5
4
TAG
R
19
TAG
R
3
18
2
17
16
1
0
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MISS
Bit
Name
Type
Bit
Name
Type
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L2C+0010h
Bit
Name
Type
Bit
Name
Type
Data Cache DATA Register
31
30
29
28
27
26
25
15
14
13
12
11
10
9
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When a read TAG command is executed and finished, the TAG can be read from the L2C_TAG register.
24
23
DATA
R
8
7
DATA
R
L2C_DATA
22
21
20
19
18
17
16
6
5
4
3
2
1
0
When a read DATA command is executed and finished, DATA can be read from the L2C_DATA register.
Bit
Name
Type
Reset
Bit
Data Cache Mode Register
31
30
15
14
Name
Type
Reset
29
28
27
26
25
24
23
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L2C+0014h
13
12
11
10
9
8
7
22
21
20
6
5
4
19
L2C_MODE
18
17
16
3
2
1
0
DIRTY GATE MPEG BYPA
FBBR
ALL DG
4
SS
R
R
R
R
R
0
0
0
0
1
The L2C_MODE register shows the data cache’s operation mode. The setting can be changed by programming the
L2C_CON register. Refer to the L2C_CON register description for details.
BYPASS
MPEG4
GATEDG
DIRTYALL
FBBR
Bypass the data cache. The write buffer is still activated.
MPEG4 mode. This mode is valid only when the data cache is enabled (BYPASS = 0).
Gate DMA and GMC requests. Any requests from the DMA and GMC are suspended.
Normally only half of a cache line is set as dirty when data is written to only half of the cache line.
When this mode is enabled, the entire cache line is set as dirty when data is written to the line.
Flush the write buffer before issuing an MCU burst read (L1 cache line fill) to the EMI.
3.8.5
•
Initialize and Enable the Data Cache
Invalidate all cache lines.
MT
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Note: DO NOT CLEAN the cache during the first initialization, or the content of the destination memory (external
memory) may be overwritten with unpredictable values.
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•
3.9
3.9.1
Set BYPASS to ‘0’ to enable the data cache.
Internal Memory Interface
System RAM
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3.9.2
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MT6228 provides one 128 KByte size of on-chip memory modules acting as System RAM for data access with low
latency. Such a module is composed of one high speed synchronous SRAMs with AHB Slave Interface connected to the
system backbone AHB Bus, as shown in Figure 32. The synchronous SRAM operates on the same clock as the AHB
Bus and is organized as 32 bits wide with 4 byte-write signals capable for byte operations. The SRAM macro has
limited repair capability. The yield of SRAM is improved if the defects inside it can be repaired during testing.
System ROM
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The System ROM is primarily used to store software program for Factory Programming. However, due to its
advantageous low latency performance, some of the timing critical codes are also placed in System ROM. This
module is composed of high-speed VIA ROM with an AHB Slave Interface connected to a system backbone AHB,
shown in Figure 32. The module operates on the same clock as the AHB and has a 32-bit wide organization.
Bank0 SRAM
MCU AHB Bus
ROM
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DMA AHB Bus
Graphsys AHB Bus 0
Figure 32: Block Diagram of the Internal Memory Controller
3.10
3.10.1
External Memory Interface
General Description
MT6228 incorporates a powerful and flexible memory controller, External Memory Interface, to connect with a variety
of memory components. This controller provides one generic access scheme for Flash Memory, SRAM, PSRAM and
CellularRAM and another access scheme for MobileRAM. Up to 4 memory banks can be supported simultaneously,
BANK0-BANK3, with a maximum size of 64MB each.
MT
K
Since most of the Flash Memory, SRAM, PSRAM and CellularRAM have similar AC requirements, a generic
configuration scheme to interface them is desired. This way, the software program can treat different components by
simply specifying certain predefined parameters. All these parameters are based on the cycle time of system clock.
The interface definition based on such a scheme is listed in Table 17.
in Little Endian format for all types of access.
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Note that, this interface always works with data
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Signal Name
Type
Description
EA[25:0]
O
Address Bus
ED[15:0]
I/O
Data Bus
O
Write Enable Strobe/MobileRAM Command Input
O
Read Enable Strobe
ELB#
O
Lower Byte Strobe/MobileRAM Data Input & Output Mask
EUB#
O
Upper Byte Strobe/MobileRAM Data Input & Output Mask
ECS[3:0]#
O
BANK0~BANK3 Selection Signal
EPDN
O
PSRAM Power Down Control Signal
ECLK
O
Flash, SRAM, PSRAM and CellularRAM Clock Signal
EADV#
O
Flash, SRAM, PSRAM and CellularRAM Address Valid Signal
EWAIT
I
Flash, SRAM, PSRAM and CellularRAM Wait Signal Input
EDCLK
O
MobileRAM Clock Signal
ECKE
O
MobileRAM Clock Enable Signal
ERAS#
O
MobileRAM Row Address Signal
ECAS#
O
MobileRAM Column Address Signal
REGISTER ADDRESS REGISTER NAME
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Table 17 External Memory Interface Signal of MT6228
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EWR#
ERD#
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MT6228 GSM/GPRS Baseband Processor Data Sheet
SYNONYM
EMI Control Register for BANK0
EMI_CONA
EMI + 0008h
EMI Control Register for BANK1
EMI_CONB
EMI + 0010h
EMI Control Register for BANK2
EMI_CONC
EMI + 0018h
EMI Control Register for BANK3
EMI_COND
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EMI + 0000h
EMI + 0040h
EMI Control Register 0 for MobileRAM
EMI_CONI
EMI + 0048h
EMI Control Register 1 for MobileRAM
EMI_CONJ
EMI + 0050h
EMI Control Register 2 for MobileRAM
EMI_CONK
EMI + 0058h
EMI Control Register 3 for MobileRAM
EMI_CONL
EMI + 0060h
EMI Remap Control Register
EMI_REMAP
EMI + 0068h
EMI General Control Register 0
EMI_GENA
EMI + 0070h
EMI General Control Register 1
EMI_GENB
Table 18 External Memory Interface Register Map
3.10.2
Register Definitions
EMI+0000h
Bit
Name
31
EMI Control Register for BANK 0
30
29
28
C2WS
MT
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Type
R/W
Reset
0
Bit
15
14
13
Name DW RBLN BW
Type R/W R/W R/W
Reset
0
1
0
27
26
25
24
C2WH
11
10
WST
R/W
0
22
21
C2RS
R/W
0
12
23
EMI_CONA
9
8
R/W
0
7
6
WAIT PSIZE
R/W R/W
0
0
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20
19
18
PRLT
R/W
0
5
4
3
2
RLT
R/W
7
17
16
CLKE PMO
N
DE
R/W R/W
0
0
1
0
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31
Name
30
29
C2WS
EMI+0010h
31
Name
29
EMI+0018h
Name
25
24
12
11
10
WST
R/W
0
23
22
21
C2RS
R/W
0
28
C2WS
31
26
9
8
20
27
26
25
24
C2WH
11
10
WST
R/W
0
9
8
5
4
21
20
3
29
28
C2WS
19
26
25
24
C2WH
R/W
0
5
11
10
WST
R/W
0
22
21
C2RS
R/W
0
12
23
9
8
18
PRLT
R/W
0
7
6
WAIT PSIZE
R/W R/W
0
0
R/W
0
7
6
WAIT PSIZE
R/W R/W
0
0
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Type
R/W
Reset
0
Bit
15
14
13
Name DW RBLN BW
Type R/W R/W R/W
Reset
0
1
0
27
2
RLT
R/W
7
17
16
CLKE PMO
N
DE
R/W R/W
0
0
1
0
EMI_CONC
22
4
3
EMI Control Register for BANK 3
30
18
R/W
0
C2RS
R/W
0
12
23
19
PRLT
R/W
0
7
6
WAIT PSIZE
R/W R/W
0
0
EMI Control Register for BANK 2
30
Type
R/W
Reset
0
Bit
15
14
13
Name DW RBLN BW
Type R/W R/W R/W
Reset
0
1
0
Bit
27
C2WH
Type
R/W
Reset
0
Bit
15
14
13
Name DW RBLN BW
Type R/W R/W R/W
Reset
0
1
0
Bit
28
EMI_CONB
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Bit
EMI Control Register for BANK 1
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EMI+0008h
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20
19
2
RLT
R/W
7
EMI_COND
18
PRLT
R/W
0
5
4
3
17
16
CLKE PMO
N
DE
R/W R/W
0
0
1
0
2
RLT
R/W
7
17
16
CLKE PMO
N
DE
R/W R/W
0
0
1
0
For each bank (BANK0-BANK3), a dedicated control register is associated with the bank controller. These registers
have timing parameters that help the controller to convert memory access into proper timing waveform. Note that,
except for parameters CLKEN, PMODE, DW, RBLN, BW, WAIT and PSIZE, all the other parameters specified
explicitly are based on system clock speed in terms of cycle count.
Read Latency Time
Specifies the number of wait-states to insert in the bus transfer to the requesting agent. Such a parameter
must be chosen carefully to meet the timing specification requirements for common parameter tACC(address
access time) for asynchronous-read device and tCWT(chip select low to wait valid time) for synchronous-read
device. An example is shown below.
MT
K
RLT
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Access Time
Read Latency Time in 104 MHz unit
65 ns ~ 70 ns
7
85 ns ~ 90 ns
110 ns ~ 120 ns
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Figure 33 Read Wait State Timing Diagram for Asynchronous-Read Memory (CLKEN=0)
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9
12
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Table 19 Reference value of Read Latency Time for Asynchronous-Read memory Devices
Figure 34 Read Wait State Timing Diagram for Synchronous-Read Memory (CLKEN=1)
ECS# Low to EWAIT Valid
Read Latency Time in 104 MHz unit
0 ns ~ 10 ns
1
10 ns ~ 20 ns
2
Table 20 Reference value of Read Latency Time for Synchronous-Read Devices
MT
K
PSIZE This bit position describes the page size behavior of that the Page Mode enabled device.
0 8 byte, EA[22:3] remains the same
1 16 byte, EA[22:4] remains the same
WAIT Data-valid feedback operation control for Flash memory, PSRAM and CellularRAM.
0 Disable data-valid feedback operation control
1 Enable data-valid feedback operation control
WST Write Wait State
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Specifies the parameters to extend adequate setup and hold time for target component in write operation.
Such parameter must be chosen carefully to meet the timing specification requirements for common parameter
tWC(write cycle time) for asynchronous-write device and tCWT(chip select low to wait valid time) for
synchronous-write device. An example is shown in Figure 35 and Table 21.
Figure 35 Write Wait State Timing Diagram for Asynchronous-Write Memory (BW=0)
Write Pulse Width
(Write Data Setup Time)
65 ns ~ 70 ns
85 ns ~ 90 ns
110 ns ~ 120 ns
Write Wait State in 104 MHz unit
7
9
12
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Table 21 Reference value of Write Wait State for Asynchronous-Write Devices
Figure 36 Write Wait State Timing Diagram for Synchronous-Write Memory (CLKEN=1 and BW=1)
Write Wait State in 104 MHz unit
0 ns ~ 10 ns
1
10 ns ~ 20 ns
2
MT
K
ECS# Low to EWAIT Valid
Table 22 Reference value of Write Wait State for Synchronous-Write Devices
BW
Burst Mode Write Control
0 Disable burst write operation
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EMI+0040h
Bit
31
EMI Control Register 0 for MobileRAM
30
29
28
27
26
25
Name
PAUS
E_EN
Type
Reset
Bit
Name
Type
Reset
R/W
0
9
A9
R/W
0
14
BA1
R/W
0
13
BA0
R/W
0
12
A12
R/W
0
11
A11
R/W
0
10
A10
R/W
0
EMI_CONI
24
23
22
21
20
19
18
PING
DRAM_MOD
DRAM
PONG
DRAM_SIZE
E
_EN
_EN
R/W
R/W
R/W
R/W
0
2d
0
0
8
7
6
5
4
3
2
A8
A7
A6
A5
A4
A3
A2
R/W R/W R/W R/W R/W R/W R/W
0
0
0
0
0
0
0
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15
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1 Enable burst write operation
RBLN Read Byte Lane Enable
DW
Data Width
0 16 Bit
1 8 Bit
PMODE
Page Mode Control
If the target device supports page mode operations, the Page Mode Control can be enabled. Read in Page
Mode is determined by the set of parameters: PRLT and PSIZE.
0 disable page mode operation
1 enable page mode operation
PRLT Read Latency Time within the Same Page
Since page mode operation only helps to eliminate read latency in subsequent access within the same page, the
initial latency does not matter. Thus, the memory controller must still adopt the RLT parameter for the initial
read or reads between different pages, even if PMODE is set to 1.
CLKEN Clock Enable Control
C2RS Chip Select to Read Strobe Setup Time
C2WH Chip Select to Write Strobe Hold Time
C2WS Chip Select to Write Strobe Setup Time
17
16
DRAM_CS
R/W
0
1
0
A1
A0
R/W R/W
0
0
MT
K
A12-A0 Mode Register Configuration
BA1-B0
Mode Register Configuration
DRAM_CS MobileRAM Controller Chip Select Signal Control
00 Chip Select 0 is used for MobileRAM
01 Chip Select 1 is used for MobileRAM
10 Chip Select 2 is used for MobileRAM
11 Chip Select 3 is used for MobileRAM
DRAM_EN MobileRAM Controller Control
0 MobileRAM controller is disabled
1 MobileRAM controller is enabled
DRAM_SIZE MobileRAM Chip Size
00 64Mbit
01 128Mbit
10 256Mbit
11 512Mbit
DRAM_MODE MobileRAM Scrambling Table Control
00 Mode 1
01 Mode 2
10 Mode 3 (PASR is not allowed)
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11 Mode 3 (PASR is not allowed)
PINGPONG_EN
Ping-pong Operation Control
PAUSE_EN Self-Refresh Mode Control when Baseband is in Pause Mode Operation
PCA
AREF
SETM
SRF
PDN
SRFS
PDNS
EMI Control Register 1 for MobileRAM
31
30
29
28
27
26
15
14
13
12
11
10
Pre-Charge All Command
Auto-Refresh Command
Set Mode Register Command
Self-Refresh Mode Command
Power-Down Mode Command
Self-Refresh Mode Status
Power Down Mode Status
EMI+0050h
30
29
28
27
26
25
14
13
RAS_MIN
R/W
0
12
11
10
RRD
R/W
0
9
WR
R/W
0
CAS
22
21
20
19
7
6
5
4
3
18
24
23
22
RAS_MAX
R/W
0
8
7
6
RC
R/W
0
21
5
17
16
2
1
0
SETM AREF PCA
R/W R/W R/W
0
0
0
EMI Control Register 2 for MobileRAM
31
15
EMI_CONJ
23
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Bit
Name
Type
Reset
Bit
Name
Type
Reset
25
24
PDNS SRFS
R
R
0
0
9
8
PDN SRF
R/W R/W
0
0
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Bit
Name
Type
Reset
Bit
Name
Type
Reset
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EMI+0048h
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MT6228 GSM/GPRS Baseband Processor Data Sheet
EMI_CONK
20
19
18
17
16
4
3
2
1
0
CAS
R/W
0
RP
R/W
0
RCD
R/W
0
CAS Latency Control
0 CAS Latency = 2
1 CAS Latency = 3
RCD Active to Read or Write Delay
RP
Pre-charge Command Period
RC
Active Bank A to Active Bank A Period
RRD Active Bank A to Active Bank B Delay
RAS_MIN Minimum Active to Pre-charge Command Delay
RAS_MAX Maximum Active to Pre-charge Command Delay
WR
Write Recovery Time
EMI+0058h
31
ARFE
Name
N
Type R/W
Reset
0
Bit
15
Name
Type
Reset
30
29
MT
K
Bit
EMI Control Register 3 for MobileRAM
RFC
14
13
ISR
R/W
0
28
12
27
26
25
24
23
EMI_CONL
22
21
20
19
18
17
16
HYE
REFCNT
DIV
R/W
0
11
R/W
0
4
R/W
0
10
9
MRD
R/W
0
8
7
6
5
XSR
R/W
0
3
2
1
0
RFC
R/W
0
Auto Refresh Period
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MT6228 GSM/GPRS Baseband Processor Data Sheet
XSR
MRD
ISR
DIV
fo
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Exit Self Refresh to Active Command Delay
Load Mode Register Command Period
Minimum Period for Self-Refresh Mode
MobileRAM Refresh Period Pre-Divider in units of 32 KHz; this field defines the MobileRAM Refresh
Period.
00 Divide by 1 (32KHz)
01 Divide by 2 (32KHz/2)
10 Divide by 3 (32KHz/3)
11 Divide by 4 (32KHz/4)
REFCNT Number of Auto-Refresh-Command to issue per MobileRAM Refresh Period.
HYE
Reserved
ARFEN Auto Refresh Control
Bit
Name
Type
Reset
15
EMI Re-map Control Register
14
13
12
11
10
9
8
EMI_REMAP
Re
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EMI+0060h
7
6
5
4
3
2
1
RM1
R/W
0
0
RM0
R/W
0
This register accomplishes the Memory Re-mapping Mechanism. The register provides the kernel software program
or system designer with the capability to change memory configuration dynamically. Three kinds of configuration are
permitted.
RM[1:0]
Re-mapping control for Boot Code, BANK0 and BANK1, refer to Table 23.
Address 0000_0000h – 07ff_ffffh
Address 0800_0000h – 0fff_ffffh
00
Boot Code
BANK1
01
BANK1
BANK0
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RM[1:0]
10
BANK0
BANK1
11
BANk1
BANK0
Table 23 Memory Map Configuration
EMI+0068h
Bit
31
Name CKE
Type R/W
Reset
0
Bit
15
Name EDA
Type R/W
Reset
1
EMI General Control Register 0
30
29
28
DCKS
EXT_GUARD
R
R/W
R/W
0
0
14
13
12
SCKS
PDNE WPOL
R
R/W R/W R/W
0
0
0
27
DCKE
2
R/W
0
11
SCKE
2
R/W
0
26
DCKE
4
R/W
0
10
SCKE
4
R/W
0
25
DCKE
8
R/W
0
9
SCKE
4
R/W
0
24
DCKE
16
R/W
0
8
SCKE
16
R/W
0
23
EMI_GENA
22
21
20
19
18
DCKE
DCKDLY
R/W
0
7
R/W
0
6
5
4
3
2
SCKE
SCKDLY
R/W
0
R/W
0
17
16
1
0
MT
K
SCKDLY FLASH, SRAM, PSRAM and CellularRAM Clock Delay Control
SCKE FLASH, SRAM, PSRAM and CellularRAM Clock Enable Control
SCKEn FLASH, SRAM, PSRAM and CellularRAM Clock Pad Driving Control (n=2, 4, 8, 16)
SCKSR FLASH, SRAM, PSRAM and CellularRAM Pad Slew-Rate Control
WPOL FLASH, SRAM, PSRAM and CellularRAM Wait Signal Inversion Control
PDNE PSRAM Power Down Control
EDA Data Bus Active Drive Control
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Figure 37 Clock Delay Control
EMI+0070h
31
Name
Type
Reset
Bit
Name
Type
Reset
15
EMI General Control Register 1
30
29
28
27
26
25
EAE1
EDSR
EASR EAE2 EAE4 EAE8
6
R/W R/W R/W R/W R/W R/W
1
1
0
0
0
1
14
13
12
11
10
9
ERWS ERWE ERWE ERWE ERWE EADV
R
2
4
8
16
SR
R/W R/W R/W R/W R/W R/W
1
1
0
0
0
1
24
23
22
EDE2 EDE4 EDE8
R/W R/W R/W
1
0
0
8
7
6
EADV EADV EADV
E2
E4
E8
R/W R/W R/W
1
0
0
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Bit
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DCKDLY MobileRAM Clock Delay Control
DCKE MobileRAM Clock Enable Control
DCKEn MobileRAM Clock Pad Driving Control (n=2, 4, 8, 16)
DCKSR MobileRAM Clock Pad Slew-Rate Control
EXT_GUARD Extra IDLE Time for FLASH, SRAM, PSRAM and CellularRAM
CKE Dynamic MobileRAM Clock Enable Control
Revision 1.0
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21
EDE1
6
R/W
0
5
EADV
E16
R/W
0
20
ECSS
R
R/W
1
4
ERCS
R
R/W
1
19
ECSE
2
R/W
1
3
ERCE
2
R/W
1
EMI_GENB
18
ECSE
4
R/W
0
2
ERCE
4
R/W
0
17
ECSE
8
R/W
0
1
ERCE
8
R/W
0
16
ECSE
16
R/W
0
0
ERCE
16
R/W
0
MT
K
ERCEn RAS and CAS Pad Driving Control (n=2, 4, 8, 16)
ERCSR RAS and CAS Pad Slew-Rate Control
EADVEn EADV Pad Driving Control (n=2, 4, 8, 16)
EADVSR EADV Pad Slew-Rate Control
ERWEnERD, EWR, EUB and ELB Pad Driving Control (n=2, 4, 8, 16)
ERWSR
ERD, EWR, EUB and ELB Pad Slew-Rate Control
ECSEn ECS[3:0] Pad Driving Control (n=2, 4, 8, 16)
ECSSR ECS[3:0] Pad Slew-Rate Control
EDEn ED[15:0] Pad Driving Control (n=2, 4, 8, 16)
EDSR ED[15:0] Pad Slew-Rate Control
EAEn EA[25:0] Pad Driving Control (n=2, 4, 8, 16)
EASR EA[25:0] Pad Slew-Rate Control
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MT6228 GSM/GPRS Baseband Processor Data Sheet
Microcontroller Peripherals
Microcontroller (MCU) Peripherals are devices that are under direct control of the Microcontroller. Most of the
devices are attached to the Advanced Peripheral Bus (APB) of the MCU subsystem, and serve as APB slaves. Each
MCU peripheral must be accessed as a memory-mapped I/O device; that is, the MCU or the DMA bus master reads
from or writes to the specific peripheral by issuing memory-addressed transactions.
Pulse-Width Modulation Outputs
4.1.1
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4.1
General Description
Re
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Two generic pulse-width modulators are implemented to generate pulse sequences with programmable frequency and
duty cycle for LCD backlight or charging purpose. The duration of the PWM output signal is LOW as long as the
internal counter value is greater than or equal to the threshold value. The waveform is shown in Figure 38.
Internal counter
Threshold
PWM Signal
Figure 38 PWM waveform
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The frequency and volume of PWM output signal are determined by these registers: PWM_COUNT, PWM_THRES,
PWM_CON. The POWERDOWN (pdn_pwm) signal is applied to power-down the PWM module. When PWM is
deactivated (POWERDOWN=1), the output is in LOW state.
The output PWM frequency is determined by:
CLK
CLK = 13000000 when CLKSEL = 0, CLK = 32000 whenCLKSEL = 1
CLOCK _ DIV × ( PWM _ COUNT + 1)
CLOCK_DIV = 1, when CLK[1:0] = 00b
CLOCK_DIV = 2, when CLK[1:0] = 01b
CLOCK_DIV = 4, when CLK[1:0] = 10b
CLOCK_DIV = 8, when CLK[1:0] = 11b
The output PWM duty cycle is determined by:
PWM _ THRES
PWM _ COUNT + 1
Note that PWM_THRES should be less than the PWM_COUNT: if this condition is not satisfied, the output pulse of
the PWM is always HIGH.
Register Definitions
MT
K
4.1.2
PWM+0000h
Bit
15
14
PWM1 Control register
13
12
11
10
9
PWM1_CON
8
7
6
5
4
3
2
CLKS
EL
Name
Type
R/W
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CLK [1:0]
R/W
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Reset
Revision 1.0
0
CLK
Select PWM1 clock prescaler scale.
00 CLK Hz
01 CLK/2 Hz
10 CLK/4 Hz
11 CLK/8 Hz
Note: When PWM1 module is disabled, its output should be kept in the LOW state.
PWM+0004h
Bit
Name
Type
Reset
15
14
PWM1 max counter value register
13
12
11
10
9
8
0
fo
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Select PWM1 clock
CLK=13M Hz
CLK=32K Hz
PWM1_COUNT
7
6
5
PWM1_COUNT [12:0]
R/W
1FFFh
4
3
2
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CLKSEL
0
1
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1
0
PWM1_COUNT PWM1 max counter value. This value is the initial value for the internal counter. Regardless of
the operation mode, if PWM1_COUNT is written while the internal counter is counting backwards,
the new initial value does not take effect until the internal counter counts down to zero, i.e. a
complete period.
Bit
Name
Type
Reset
15
14
PWM1 Threshold Value register
13
12
11
10
9
8
PWM1_THRES
7
6
5
PWM1_THRES [12:0]
R/W
0
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PWM+0008h
4
3
2
1
0
PWM1_THRES Threshold value. When the internal counter value is greater than or equal to PWM1_THRES, the
PWM1 output signal is 0; when the internal counter is less than PWM1_THRES, the PWM1 output
signal is 1.
PWM+000Ch
Bit
15
14
Name
Type
Reset
CLK
PWM2 Control register
13
12
11
10
9
8
7
PWM2_CON
6
5
4
3
2
CLKS
EL
1
0
CLK [1:0]
R/W
0
R/W
0
Select PWM2 clock prescaler scale.
00 CLK Hz
01 CLK/2 Hz
10 CLK/4 Hz
11 CLK/8 Hz
Note: When PWM2 module is disabled, its output should be kept in the LOW state.
Select PWM2 clock
CLK=13M Hz
CLK=32K Hz
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CLKSEL
0
1
PWM+0010h
Bit
15
14
PWM2 max counter value register
13
12
11
10
9
8
7
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5
4
3
2
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Type
Reset
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PWM2_COUNT [12:0]
R/W
1FFFh
PWM2_COUNT PWM2 max counter value. This value is the initial value for the internal counter. Regardless of
the operation mode, if PWM2_COUNT is written while the internal counter is counting backwards,
the new initial value does not take effect until the internal counter counts down to zero, i.e. a
complete period.
Bit
Name
Type
Reset
15
PWM2 Threshold Value register
14
13
12
11
10
9
8
7
6
5
PWM2_THRES [12:0]
R/W
0
PWM2_THRES
4
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PWM+0014h
3
2
1
0
13MHz
PWM_COUNT = 5
PWM_THRES = 1
PWM_CON = 0b
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Figure 39 PWM waveform with register values
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PWM2_THRES Threshold value. When the internal counter value is greater than or equal to PWM2_THRES, the
PWM1 output signal is 0; when the internal counter is less than PWM2_THRES, the PWM2 output
signal is 1.
Figure 39 shows the PWM waveform with the indicated register values.
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4.2
Alerter
4.2.1
General Description
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The output of the Alerter has two sources: one is the enhanced PWM output signal, implemented within the Alerter
module; the other is the PDM signal that comes from the DSP domain directly. The output source can be selected via
the register ALERTER_CON.
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The enhanced PWM has three modes of operation and can generate a signal with programmable frequency and tone
volume. The frequency and volume are determined by four registers: ALERTER_CNT1, ALERTER_THRES,
ALERTER_CNT2, and ALERTER_CON. ALERTER_CNT1 and ALERTER_CNT2 are the initial counting values
for the internal counters counter1 and counter2, respectively.
POWERDOWN signal is applied to power down the Alerter module. When Alerter is deactivated
(POWERDOWN=1), the output is in a low state. The waveform of Alerter from the enhanced PWM source in
different modes is shown in Figure 40.
T1
Internal counter1
T2
ALERTER_THRES
Internal counter2
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enhance pwm out (mode 1)
enhance pwm out (mode 2)
enhanced pwm out (mode 3)
T1 = ALERTER_CNT1 * 1/13MHz *( ALERTER_CON[1:0]+1)
T2 = T1 *( ALERTER_CNT2+1)
Figure 40 Alerter Waveform
In Mode 1, the polarity of the Alerter output signal, given the relationship between internal counter1 and the
programmed threshold, is inverted each time internal counter2 reaches zero.
In Mode 2, each time the internal counter2 reaches zero, the Alerter output signal toggles between the normal PWM
signal (i.e. the signal is low for an internal counter1 value greater than or equals to ALERTER_THRES; high when the
internal counter1 value is less than ALERTER_THRES) and low state.
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In Mode 3, the value of internal counter2 has no effect on output signal. That is, the alerter output signal is low as
long as the internal counter 1 value is above the programmed threshold, and is high when the internal counter1 is less
than ALERTER_THRES, regardless of internal counter2’s value.
The output signal frequency is given by:
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13000000
2 × ( ALERTER _ CON [1 : 0] + 1) × ( ALERTER _ CNT 1 + 1) × ( ALERTER _ CNT 2 + 1)
13000000
( ALERTER _ CNT 1 + 1) × ( ALERTER _ CON [1 : 0])
The volume of the output signal is given by:
for mode 1 and mode 2 .
for mode 3
ALERTER _ THRES .
ALERTER _ CNT 1 + 1
Register Definitions
ALTER+0000h Alerter counter1 value register
15
14
13
12
11
10
ALERTER_CNT1
9
8
7
6
ALERTER_CNT1 [15:0]
R/W
FFFFh
5
4
3
2
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Bit
Name
Type
Reset
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4.2.2
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1
0
ALERTER_CNT1
Alerter max counter’s value. Initial value of internal counter1. In any mode, if
ALERTER_CNT1 is written when the internal counter1 is counting, the new start value does not take effect
until the next countdown period; i.e. after internal counter1 reaches zero.
ALERTER_THR
ES
ALTER+0004h Alerter threshold value register
Bit
Name
Type
Reset
15
14
13
12
11
10
9
8
7
6
ALERTER_THRES [15:0]
R/W
0
5
4
3
2
1
0
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ALERTER_THRES Threshold value. When the internal counter1 value is greater than or equals to
ALERTER_THRES, the Alerter output signal is low; when counter1 is less than ALERTER_THRES,
the Alerter output signal is high.
ALTER+0008h Alerter counter2 value register
Bit
Name
Type
Reset
15
14
13
12
11
10
9
8
7
ALERTER_CNT2
6
5
4
3
2
1
ALERTER_CNT2 [ 5:0]
R/W
111111b
0
ALERTER_CNT2
Initial value for internal counter2. The internal counter2 decreases by one each time the
internal counter1 counts down to zero; internal counter1 is a nested counter.
ALTER+000Ch Alerter control register
Bit
Name
Type
Reset
CLK
15
14
13
12
11
10
9
8
TYPE
R/W
0
7
ALERTER_CON
6
5
4
3
MODE
R/W
0
2
1
0
CLK [1:0]
R/W
0
MT
K
Select the PWM Waveform clock.
00 13 MHz
01 13/2 MHz
10 13/4 MHz
11 13/8 MHz
MODE Select the Alerter mode.
00 Mode 1 selected
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01 Mode 2 selected
10 Mode 3 selected
TYPE Select the ALERTER output source from PWM or PDM.
0 Output generated from PWM path.
1 Output generated from PDM path.
Note: When the Alerter module is powered down, its output must be kept in low state.
Figure 41 shows the Alerter waveform with the register values.
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13MHz
ALERTER_CNT1 = 5
ALERTER_CNT2 = 1
ALERTER_THRESH= 1
ALERTER_CON = 01000b
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ALERTER_CNT1 = 5
ALERTER_CNT2 = 1
ALERTER_THRESH= 1
ALERTER_CON=00000b
ALERTER_CNT1 = 5
ALERTER_CNT2 = 1
ALERTER_THRESH= 1
ALERTER_CON = 00100b
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MT6228 GSM/GPRS Baseband Processor Data Sheet
Figure 41 Alerter Output Signal from Enhanced PWM with Register Value Present
4.3
SIM Interface
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The MT6228 contains a dedicated smart card interface to allow the MCU access to the SIM card. It can operate via 5
terminals, using SIMVCC, SIMSEL, SIMRST, SIMCLK and SIMDATA.
Figure 42 SIM Interface Block Diagram
The SIMVCC is used to control the external voltage supply to the SIM card and SIMSEL determines the regulated
smart card supply voltage. SIMRST is used as the SIM card reset signal. SIMDATA and SIMCLK are used for data
exchange purpose.
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The SIM interface acts as a half duplex asynchronous communication port and its data format is composed of ten
consecutive bits: a start bit in state Low, eight information bits, and a tenth bit used for parity checking. The data format
can be divided into two modes as follows:
Direct Mode (ODD=SDIR=SINV=0)
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MT6228 GSM/GPRS Baseband Processor Data Sheet
SB D0 D1 D2 D3 D4 D5 D6 D7 PB
SB: Start Bit (in state Low)
Dx: Data Byte (LSB is first and logic level ONE is High)
PB: Even Parity Check Bit
Indirect Mode (ODD=SDIR=SINV=1)
SB N7 N6 N5 N4 N3 N2 N1 N0 PB
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SB: Start Bit (in state Low)
Nx: Data Byte (MSB is first and logic level ONE is Low)
PB: Odd Parity Check Bit
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If the receiver gets a wrong parity bit, it will respond by pulling the SIMDATA Low to inform the transmitter and the
transmitter will retransmit the character.
When the receiver is a SIM Card, the error response starts 0.5 bits after the PB and it may last for 1~2 bit periods.
When the receiver is the SIM interface, the error response starts 0.5 bits after the PB and lasts for 1.5 bit period.
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When the SIM interface is the transmitter, it will take a total of 14 bits guard period for the error response to appear. If
the receiver shows the error response, the SIM interface will retransmit the previous character again, otherwise it will
transmit the next character.
Figure 43 SIM Interface Timing Diagram
Register Definitions
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4.3.1
SIM+0000h
Bit
15
SIM module control register
14
13
12
11
10
9
8
SIM_CON
7
Name
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6
5
4
3
2
1
0
CSTO SIMO
WRST
P
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Type
Reset
W
0
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MT6228 GSM/GPRS Baseband Processor Data Sheet
R/W
0
R/W
0
Bit
15
SIM module configuration register
14
13
Name
Type
Reset
12
11
10
9
6
5
4
3
2
1
0
SIMS
TXAC RXAC
ODD SDIR SINV CPOL
HFEN T0EN T1EN TOUT
EL
K
K
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
0
0
0
0
0
0
0
0
0
0
0
7
MT
K
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RXACK SIM card reception error handshake control
0 Disable character receipt handshaking
1 Enable character receipt handshaking
TXACK SIM card transmission error handshake control
0 Disable character transmission handshaking
1 Enable character transmission handshaking
CPOL SIMCLK polarity control in clock stop mode
0 Make SIMCLK stop in LOW level
1 Make SIMCLK stop in HIGH level
SINV Data Inverter.
0 Not invert the transmitted and received data
1 Invert the transmitted and received data
SDIR Data Transfer Direction
0 LSB is transmitted and received first
1 MSB is transmitted and received first
ODD Select odd or even parity
0 Even parity
1 Odd parity
SIMSEL
SIM card supply voltage select
0 SIMSEL pin is set to LOW level
1 SIMSEL pin is set to HIGH level
TOUT SIM work waiting time counter control
0 Disable Time-Out counter
1 Enable Time-Out counter
T1EN T=1 protocol controller control
0 Disable T=1 protocol controller
1 Enable T=1 protocol controller
T0EN T=0 protocol controller control
0 Disable T=0 protocol controller
1 Enable T=0 protocol controller
HFEN Hardware flow control
8
SIM_CNF
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SIM+0004h
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SIMON SIM card power-up/power-down control
0 Initiate the card deactivation sequence
1 Initiate the card activation sequence
CSTOP Enable clock stop mode. Together with CPOL in SIM_CNF register, it determines the polarity of the SIMCLK
in this mode.
0 Enable the SIMCLK output.
1 Disable the SIMCLK output
WRST SIM card warm reset control
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0
1
Disable hardware flow control
Enable hardware flow control
SIM +0008h
Bit
Name
Type
Reset
15
14
SIM Baud Rate Register
13
12
11
10
9
SIM_BRR
8
7
6
5
BAUD[8:0]
R/W
372d
4
15
14
SIM interrupt enable register
13
12
11
Name
Type
Reset
15
14
Name
Type
Reset
SIM module status register
13
12
11
SIM_IRQEN
SIM_STA
10
9
8
7
6
5
4
3
2
1
0
EDCE T1EN RXER T0EN SIMO ATRER TXER TOU OVRU RXTID TXTID
RR
D
R
D
FF
R
R
T
N
E
E
RC
RC
RC
RC
RC
RC
RC RC RC
RO
RO
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Bit
1
0
SIMCLK[1:0]
R/W
01
10
9
8
7
6
5
4
3
2
1
0
EDCE T1EN RXER T0EN SIMO ATRER TXER TOU OVRU RXTID TXTID
RR
D
R
D
FF
R
R
T
N
E
E
R/W R/W R/W R/W R/W
R/W R/W R/W R/W R/W R/W
0
0
0
0
0
0
0
0
0
0
0
For all these bits
0 Interrupt is disabled
1 Interrupt is enabled
SIM +0014h
2
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SIM +0010h
3
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SIMCLK
Set SIMCLK frequency
00 13/2 MHz
01 13/4 MHz
10 13/8 MHz
11 13/12 MHz
BAUD Determines the baud rate as a division of SIMCLK (SIMCLK/BAUD[8:0])
Bit
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TXTIDE Transmit FIFO tide mark reached interrupt occurred
RXTIDE
Receive FIFO tide mark reached interrupt occurred
OVRUN
Transmit/Receive FIFO overrun interrupt occurred
TOUT Between character timeout interrupt occurred
TXERR Character transmission error interrupt occurred
ATRERR ATR start time-out interrupt occurred
SIMOFF
Card deactivation complete interrupt occurred
T0END Data Transfer handled by T=0 Controller completed interrupt occurred
RXERR Character reception error interrupt occurred
T1END Data Transfer handled by T=1 Controller completed interrupt occurred
EDCERR T=1 Controller CRC error occurred
SIM +0020h
15
14
13
MT
K
Bit
Name
Type
Reset
SIM retry limit register
12
11
10
9
8
TXRETRY
R/W
3h
7
SIM_RETRY
6
5
4
3
2
1
0
RXRETRY
R/W
3h
RXRETRY Specify the max. numbers of receive retries that are allowed when parity error has occurred.
TXRETRY Specify the max. numbers of transmit retries that are allowed when parity error has occurred.
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SIM +0024h
Bit
Name
Type
Reset
15
14
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SIM FIFO tide mark register
13
12
11
10
9
TXTIDE[3:0]
R/W
0h
SIM_TIDE
8
7
6
5
4
3
2
1
RXTIDE[3:0]
R/W
0h
RXTIDE
Trigger point for RXTIDE interrupt
TXTIDE Trigger point for TXTIDE interrupt
Bit
Name
Type
Reset
15
14
Data register used as Tx/Rx Data Register
13
12
11
10
9
8
7
6
SIM_DATA
5
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SIM +0030h
0
4
3
DATA[7:0]
R/W
2
1
0
SIM +0034h
Bit
Name
Type
Reset
15
14
SIM FIFO count register
13
12
11
10
9
8
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DATA Eight data digits. These correspond to the character being read or written
7
6
5
4
3
SIM_COUNT
2
1
COUNT[4:0]
R/W
0h
0
COUNT The number of characters in the SIM FIFO when read, and flushes when written.
Bit
Name
Type
Reset
15
ATIME
14
15
DTIME
14
12
11
10
9
8
7
ATIME[15:0]
R/W
AFC7h
6
5
4
3
2
1
0
SIM deactivation time register
13
12
11
10
9
8
7
SIM_DTIME
6
5
DTIME[11:0]
R/W
3E7h
4
3
2
1
0
The register defines the duration, in 13MHz clock cycles, of the time taken for each of the three stages of
the card deactivation sequence
SIM +0048h
Bit
Name
Type
Reset
13
SIM_ATIME
The register defines the duration, in SIM clock cycles, of the time taken for each of the three stages of the
card activation process
SIM +0044h
Bit
Name
Type
Reset
SIM activation time register
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SIM +0040h
15
14
Character to character waiting time register
13
12
11
10
9
8
7
WTIME[15:0]
R/W
983h
6
5
SIM_WTIME
4
3
2
1
0
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WTIME Maximum interval between the leading edge of two consecutive characters in 4 ETU unit
SIM +004Ch
Bit
Name
Type
Reset
15
14
Block to block guard time register
13
12
11
10
9
8
7
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6
5
4
3
2
1
GTIME
R/W
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MT6228 GSM/GPRS Baseband Processor Data Sheet
GTIME Minimum interval between the leading edge of two consecutive characters sent in opposite directions in ETU
unit
Bit
Name
Type
Reset
15
14
Transmit error detection register
13
12
11
10
9
8
7
SIM_ETIME
6
5
4
ETIME The register define the position for transmit error detection in ETU/16 unit
Bit
Name
Type
Reset
15
14
SIM command header register: INS
13
12
11
10
9
8
INSD
R/W
0h
7
1
0
SIM_INS
6
5
4
3
SIMINS[7:0]
R/W
0h
2
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SIM +0060h
3
2
ETIME
R/W
15d
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SIM +0050h
1
0
SIMINS This field should be identical to the INS instruction code. When writing to this register, the T=0 controller will
be activated and data transfer will be initiated.
INSD [Description for this register field]
0 T=0 controller receives data from the SIM card
1 T=0 controller sends data to the SIM card
Bit
Name
Type
Reset
15
14
SIM_P3(ICC_LE
N)
SIM command header register: P3
13
12
11
10
9
8
7
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SIM +0064h
6
5
4
3
SIMP3[8:0]
R/W
0h
2
1
0
SIMP3 This field should be identical to the P3 instruction code. It should be written prior to the SIM_INS register.
While the data transfer is going on, this field shows the no. of the remaining data to be sent or to be received
SIM +0068h
Bit
Name
Type
Reset
15
14
SIM_SW1(ICC_
LEN)
SIM procedure byte register: SW1
13
12
11
10
9
8
7
6
5
4
3
SIMSW1[7:0]
RO
0h
2
1
0
SIMSW1 This field holds the last received procedure byte for debug purpose. When the T0END interrupt occurred,
it keeps the SW1 procedure byte.
SIM +006Ch
15
14
13
12
11
10
9
8
7
MT
K
Bit
Name
Type
Reset
SIMSW2
SIM_SW2(ICC_
EDC)
SIM procedure byte register: SW2
6
5
4
3
SIMSW2[7:0]
RO
0h
2
1
0
This field holds the SW2 procedure byte
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4.3.2
SIM Card Insertion and Removal
Revision 1.0
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MT6228 GSM/GPRS Baseband Processor Data Sheet
The detection of physical connection to the SIM card and card removal is done by the external interrupt controller or by
GPIO.
4.3.3
Card Activation and Deactivation
Assert SIMRST LOW
Set SIMVCC at HIGH level and SIMDATA in reception mode
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The card activation and deactivation sequence are both controlled by hardware. The MCU initiates the activation
sequence by writing a “1” to bit 0 of the SIM_CON register, and then the interface performs the following activation
sequence:
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Enable SIMCLK clock
De-assert SIMRST HIGH (required if it belongs to active low reset SIM card)
The final step in a typical card session is contact deactivation in order to prevent the card from being electrically
damaged. The deactivation sequence is initiated by writing a “0” to bit 0 of the SIM_CON register, and then the
interface performs the following deactivation sequence:
Assert SIMRST LOW
Set SCIMCLK at LOW level
Set SIMDATA at LOW level
Set SIMVCC at LOW level
Answer to Reset Sequence
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4.3.4
After card activation, a reset operation results in an answer from the card consisting of the initial character TS, followed
by at most 32 characters. The initial character TS provides a bit synchronization sequence and defines the conventions
to interpret data bytes in all subsequent characters.
On reception of the first character, TS, MCU should read this character, establish the respective required convention
and reprogram the related registers. These processes should be completed prior to the completion of reception of the
next character. And then, the remainder of the ATR sequence is received, read via the SIM_DATA in the selected
convention and interpreted by the software.
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The timing requirement and procedures for ATR sequence are handled by hardware and shall meet the requirement of
ISO 7816-3 as shown in Figure 44.
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MT6228 GSM/GPRS Baseband Processor Data Sheet
Figure 44 Answer to Reset Sequence
Value
Comment
T1
> 400 SIMCLK
SIMCLK start to ATR appear
T2
< 200 SIMCLK
SIMCLK start to SIMDATA in reception mode
T3
> 40000 SIMCLK
SIMCLK start to SIMRST High
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Time
T4
—
SIMVCC High to SIMCLK start
T5
—
SIMRST Low to SIMCLK stop
T6
—
SIMCLK stop to SIMDATA Low
T7
—
SIMDATA Low to SIMVCC Low
Table 24 Answer to Reset Sequence Time-Out Condition
SIM Data Transfer
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4.3.5
Two transfer modes are provided, either in software controlled byte-by-byte fashion or in a block fashion using T=0
controller and DMA controller. In both modes, the time-out counter can be enabled to monitor the elapsed time between
two consecutive bytes.
4.3.5.1
Byte Transfer Mode
This mode is used during ATR and PPS procedure. In this mode, the SIM interface only ensures error free character
transmission and reception.
Receiving Character
Upon detection of the start-bit sent by SIM card, the interface transforms into reception mode and the following bits are
shifted into an internal register. If no parity error is detected or character-receive handshaking is disabled, the
received-character is written into the SIM FIFO and the SIM_CNT register is increased by one. Otherwise, the
SIMDATA line is held low for 0.5 ETU after detecting the parity error for 1.5 ETU, and the character is re-received. If a
character fails to be received correctly for the RXRETRY times, the receive-handshaking is aborted and the
last-received character is written into the SIM FIFO, the SIM_CNT is increased by one and the RXERR interrupt is
generated
MT
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When the number of characters held in the receive FIFO exceeds the level defined in the SIM_TIDE register, a
RXTIDE interrupt is generated. The number of characters held in the SIM FIFO can be determined by reading the
SIM_CNT register and writing to this register will flush the SIM FIFO.
Sending Character
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Characters that are to be sent to the card are first written into the SIM FIFO and then automatically transmitted to the
card at timed intervals. If character-transmit handshaking is enabled, the SIMDATA line is sampled at 1 ETU after the
parity bit. If the card indicates that it did not receive the character correctly, the character is retransmitted a maximum
of TXRETRY times before a TXERR interrupt is generated and the transmission is aborted. Otherwise, the succeeding
byte in the SIM FIFO is transmitted.
If a character fails to be transmitted and a TXERR interrupt is generated, the interface needs to be reset by flushing the
SIM FIFO before any subsequent transmit or receive operation.
4.3.5.2
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When the number of characters held in the SIM FIFO falls below the level defined in the SIM_TIDE register, a
TXTIDE interrupt is generated. The number of characters held in the SIM FIFO can be determined by reading the
SIM_CNT register and writing to this register will flush the SIM FIFO.
Block Transfer Mode
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Basically, the SIM interface is designed to work in conjunction with the T=0 protocol controller and the DMA
controller during non-ATR and non-PPS phase; although it is still possible for software to service the data transfer
manually as in byte transfer mode if necessary, and thus the T=0 protocol should be controlled by software.
The T=0 controller is accessed via four registers representing the instruction header bytes INS and P3, and the
procedure bytes SW1 and SW2. These registers are:
SIM_INS, SIM_P3
SIM_SW1, SIM_SW2
During characters transfer, SIM_P3 holds the number of characters to be sent or to be received and SIM_SW1 holds the
last received procedure byte including NULL, ACK, NACK and SW1 for debug purpose.
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Data Receive Instruction
Data Receive Instructions receive data from the SIM card. It is instantiated as the following procedure.
1.
2.
3.
4.
5.
Enable the T=0 protocol controller by setting the T0EN bit to 1 in SIM_CNF register
Program the SIM_TIDE register to 0x0000 (TXTIDE = 0, RXTIDE = 0)
Program the SIM_IRQEN to 0x019C (Enable RXERR, TXERR, T0END, TOUT and OVRUN interrupts)
Write CLA, INS, P1, P2 and P3 into SIM FIFO
Program the DMA controller :
DMAn_MSBSRC and DMAn_LSBSRC : address of SIM_DATA register
DMAn_MSBDST and DMAn_LSBDST : memory address reserved to store the received characters
DMAn_COUNT : identical to P3 or 256 (if P3 == 0)
DMAn_CON : 0x0078
6. Write P3 into SIM_P3 register and then INS into SIM_INS register (Data Transfer is initiated
now)
7. Enable the Time-out counter by setting the TOUT bit to 1 in SIM_CNF register
8. Start the DMA controller by writing 0x8000 into the DMAn_START register to
Upon completion of the Data Receive Instruction, T0END interrupt will be generated and then the Time-out counter
should be disabled by setting the TOUT bit back to 0 in SIM_CNF register.
MT
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If error occurs during data transfer (RXERR, TXERR, OVRUN or TOUT interrupt is generated), the SIM card should
be deactivated first and then activated prior subsequent operations.
Data Send Instruction
Data Send Instructions send data to the SIM card. It is instantiated as the following procedure.
1. Enable the T=0 protocol controller by setting the T0EN bit to 1 in SIM_CNF register
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Program the SIM_TIDE register to 0x0100 (TXTIDE = 1, RXTIDE = 0)
Program the SIM_IRQEN to 0x019C (Enable RXERR, TXERR, T0END, TOUT and OVRUN interrupts)
Write CLA, INS, P1, P2 and P3 into SIM FIFO
Program the DMA controller :
DMAn_MSBSRC and DMAn_LSBSRC : memory address reserved to store the transmitted characters
DMAn_MSBDST and DMAn_LSBDST : address of SIM_DATA register
DMAn_COUNT : identical to P3
DMAn_CON : 0x0074
6. Write P3 into SIM_P3 register and then (0x0100 | INS) into SIM_INS register (Data Transfer
is initiated now)
7. Enable the Time-out counter by setting the TOUT bit to 1 in SIM_CNF register
8. Start the DMA controller by writing 0x8000 into the DMAn_START register
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2.
3.
4.
5.
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Upon completion of the Data Send Instruction, T0END interrupt will be generated and then the Time-out counter
should be disabled by setting the TOUT bit back to 0 in SIM_CNF register.
4.4
4.4.1
Keypad Scanner
General Description
Re
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If error occurs during data transfer (RXERR, TXERR, OVRUN or TOUT interrupt is generated), the SIM card should
be deactivated first and then activated prior to subsequent operations.
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The keypad can be divided into two parts: one is the keypad interface including 7 columns and 6 rows; the other is the
key detection block which provides key pressed, key released and de-bounce mechanisms. Each time the key is
pressed or released, i.e. something different in the 7 x 6 matrix, the key detection block senses the change and
recognizes if a key has been pressed or released. Whenever the key status changes and is stable, a KEYPAD IRQ is
issued. The MCU can then read the key(s) pressed directly in KP_HI_KEY, KP_MID_KEY and KP_LOW_KEY
registers. To ensure that the key pressed information is not missed, the status register in keypad is not read-cleared by
APB read command. The status register can only be changed by the key-pressed detection FSM.
This keypad can detect one or two key-pressed simultaneously with any combination. Figure 45 shows one key
pressed condition. Figure 46(a) and Figure 46(b) illustrate two keys pressed cases. Since the key press detection
depends on the HIGH or LOW level of the external keypad interface, if keys are pressed at the same time and there
exists a key that is on the same column and the same row with the other keys, the pressed key cannot be correctly
decoded. For example, if there are three key presses: key1 = (x1, y1), key2 = (x2, y2), and key3 = (x1, y2), then both
key3 and key4 = (x2, y1) are detected, and therefore they cannot be distinguished correctly. Hence, the keypad can
detect only one or two keys pressed simultaneously at any combination. More than two keys pressed simultaneously
in a specific pattern retrieves the wrong information. If these specific patterns are excluded, the keypad-scanning
block can detect 11 keys at the same time, shown in Figure 47.
Key Pressed
De-bounce time
De-bounce time
Key-pressed Status
MT
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KP_IRQ
KEY_PRESS_IRQ
KEY_RELEASE_IRQ
Figure 45 One key pressed with de-bounce mechanism denoted
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Key 1 pressed
Key 2 pressed
S t a t us
I RQ
Key 1 pr essed
Key 2 pressed
Key 1 relea sed
Key 1 pr essed
Key 2 pressed
Key 2 relea sed
Key 2 r elea sed
Key 2 pressed
S t a t us
Key 1 r elea sed
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I RQ
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Key 1 pressed
Figure 46 (a) Two keys pressed, case 1 (b) Two keys pressed, case 2
COL6
COL5
COL4
COL3
ROW5
ROW4
ROW3
ROW2
ROW1
ROW0
Figure 47 11 keys are detected at the same time
Keypad status
Bit
Name
Type
Reset
15
STA
This register indicates the keypad status.
0 No key pressed
1 Key pressed
14
KP +0004h
15
13
13
11
10
9
8
7
KP_STA
6
5
4
3
12
11
10
14
13
12
11
10
2
1
0
STA
RO
0
The register is not cleared by the read operation.
9
8
7
KEYS [15:0]
RO
FFFFh
6
5
KP_LOW_KEY
4
3
Keypad scanning output, the medium 16 keys
MT
K
15
12
Keypad scanning output, the lower 16 keys
14
KP +0008h
Bit
Name
Type
Reset
COL0
Register Definitions
KP +0000h
Bit
Name
Type
Reset
COL1
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4.4.2
COL2
9
8
7
KEYS [31:16]
RO
FFFFh
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5
2
1
0
KP_MID_KEY
4
3
2
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KP+000Ch
Bit
Name
Type
Reset
15
Keypad scanning output, the higher 4 keys
14
13
12
11
10
9
8
7
6
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KP_HIGH_KEY
5
4
KEYS[41:32]
RO
3FF’h
3
2
1
0
KEYS Status list of the 42 keys.
Bit
Name
Type
Reset
15
KP_DEBOUNC
E
De-bounce period setting
14
13
12
11
10
9
8
7
6
5
DEBOUNCE [13:0]
R/W
400h
4
3
2
1
0
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KP +00010h
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These two registers list the status of 42 keys on the keypad. When the MCU receives the KEYPAD IRQ, both two
registers must be read. If any key is pressed, the relative bit is set to 0.
This register defines the waiting period before key press or release events are considered stale.
DEBOUNCE
4.5
De-bounce time = KP_DEBOUNCE/32 ms.
General Purpose Inputs/Outputs
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MT6228 offers 71 general-purpose I/O pins and 3 general-purpose output pins. By setting the control registers, MCU
software can control the direction, the output value, and read the input values on these pins. These GPIOs and GPOs
are multiplexed with other functionalities to reduce the pin count.
Figure 48 GPIO Block Diagram
GPIOs at RESET
Upon a hardware reset (SYSRST#), GPIOs are all configured as inputs and the following alternate usages of the GPIO
pins are enabled.
These GPIOs are used to latch the inputs upon reset to memorize the desired configuration to ensure that the system
restarts or boots up in the right mode.
MT
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Multiplexing of Signals on GPIO
The GPIO pins can be multiplexed with other signals.
DAICLK, DAIPCMIN, DAIPCMOUT, DAIRST: digital audio interface for FTA
BPI_BUS6, BPI_BUS7, BPI_BUS8, BPI_BUS9: radio hardwired control
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BSI_CS1: additional chip select signal for radio 3-wire interface
LSCK, LSA0, LSDA, LSCE0#, LSCE1#: serial display interface
LPCE1#: parallel display interface chip select signal
NRNB, NCLE, NALE, NWEB, NREB, NCEB: NAND flash control signals
PWM1, PWM2: pulse width modulation signal
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IRDA_RXD, IRDA_TXD, IRDA_PDN: IrDA control signals
URXD2, UTXD2, UCTS2, URTS2: data and flow control signals for UART2
URXD3, UTXD3, UCTS3, URTS3: data and flow control signals for UART3
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ALERTER: pulse width modulation signal for buzzer
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CMRST, CMPDN, CMDAT9, CMDAT8, CMDAT7, CMDAT6, CMDAT5, CMDAT4, CMDAT3, CMDAT2,
CMDAT1, CMDAT0: sensor interface
SRCLKENAI: external power on signal of the external VCXO LDO
NLD8, NLD9, NLD10, NLD11, NLD12, NLD13, NLD14, NLD15, NLD16, NLD17: NAND FLASH and
Parallel LCD data signals
MFIQ, MIRQ: external interrupt
MCDA4, MCDA5, MCDA6, MCDA7: MMC4.0 data signals
Multiplexed of Signals on GPO
SRCLKENA, SRCLKENAN: power on signal of the external VCXO LDO
4.5.1
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EPDN: external memory interface power down controls
Register Definitions
GPIO+0000h
Bit
GPIO direction control register 1
GPIO_DIR1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO
Name
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
GPIO +0010h GPIO direction control register 2
Bit
GPIO_DIR2
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO PGIO GPIO GPIO GPIO GPIO
Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
GPIO+0020h
GPIO direction control register 3
GPIO_DIR3
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO
Name
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
MT
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Bit
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GPIO+0030h
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GPIO direction control register 4
GPIO_DIR4
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO
Name
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reset
15
14
GPIO direction control register 5
13
Name
Type
Reset
12
11
10
9
8
7
6
5
4
GPIO GPIO GPIO GPIO GPIO GPIO GPIO
74
73
72
71
70
69
68
R/W R/W R/W R/W R/W R/W R/W
0
0
0
0
0
0
0
GPIOn GPIO direction control
0 GPIOs are configured as input
1 GPIOs are configured as output
GPIO +0050h GPIO pull-up/pull-down enable register 1
Bit
GPIO_DIR5
3
2
1
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Bit
0
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GPIO+0040h
GPIO_PULLEN
1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO
Name
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
High- High- High- High- HighNote PD
PD
PD
PD
PD
PD
HIzhZ PU
PU
PD
PD
Z
Z
Z
Z
Z
Bit
Name
Type
Reset
Note
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GPIO +0060h GPIO pull-up/pull-down enable register 2
GPIO_PULLEN
2
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO PGIO GPIO GPIO GPIO GPIO
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
PU
PU
PU
PD
PD
PU
PU
PU
PU
PU
PU
PU
PD
PD
PD
PD
GPIO+0070h
Bit
GPIO pull-up/pull-down enable register 3
GPIO_PULLEN
3
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO
Name
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
High- HighNote High-Z High-Z
PU
PU
PU
PU
PU
PU
PU
PU
PD
PD
PD
PD
Z
Z
GPIO pull-up/pull-down enable register 4
MT
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GPIO+0080h
Bit
Name
Type
Reset
Note
GPIO_PULLEN4
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
PU
PD
PD
PD
PD
PD
PD
PD
PD
PD
PU
PU
PU
PD
PU
PD
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Bit
15
14
GPIO pull-up/pull-down enable register 5
13
12
11
Name
Type
Reset
Note
10
9
8
7
6
5
4
GPIO GPIO GPIO GPIO GPIO GPIO GPIO
74
73
72
71
70
69
68
R/W R/W R/W R/W R/W R/W R/W
1
1
1
1
1
1
1
PD
PD
PD
PD
PD
PD
PD
GPIOn GPIO pull-up/pull-down control
GPIO +00A0h GPIO data inversion control register 1
GPIO_PULLEN5
3
2
1
0
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GPIO+0090h
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GPIO_DINV1
Re
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Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name INV15 INV14 INV13 INV12 INV11 INV10 INV9 INV8 INV7 INV6 INV5 INV4 INV3 INV2 INV1 INV0
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
GPIO +00B0h GPIO data inversion control register 2
GPIO_DINV2
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name INV31 INV30 INV29 INV28 INV27 INV26 INV25 INV24 INV23 INV22 INV21 INV20 INV19 IVN18 INV17 INV16
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
GPIO +00C0h GPIO data inversion control register 3
GPIO_DINV3
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Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name INV47 INV46 INV45 INV44 INV43 INV42 INV41 INV40 INV39 INV38 INV37 INV36 INV35 INV34 INV33 INV32
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
GPIO+00D0h GPIO data inversion control register 4
GPIO_DINV4
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name INV63 INV62 INV61 INV60 INV59 INV58 INV57 INV56 INV55 INV54 INV53 INV52 INV51 INV50 INV49 INV48
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
GPIO+00E0h
14
GPIO data inversion control register 5
Bit
Name
Type
Reset
15
13
12
11
INVn
GPIO inversion control
0 GPIOs data inversion disable
1 GPIOs data inversion enable
10
9
8
7
6
5
4
INV74 INV73 INV73 INV71 INV70 INV69 INV68
R/W R/W R/W R/W R/W R/W R/W
0
0
0
0
0
0
0
GPIO +00F0h GPIO data output register 1
GPIO_DINV5
3
2
1
0
GPIO_DOUT1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO
Name
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
MT
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Bit
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GPIO +0100h GPIO data output register 2
Revision 1.0
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GPIO_DOUT2
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO PGIO GPIO GPIO GPIO GPIO
Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reset
GPIO +0110h GPIO data output register 3
GPIO_DOUT3
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO
Name
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
GPIO+0120h
GPIO data output register 4
Bit
Re
lea
se
fo
r
Bit
GPIO_DOUT4
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO
Name
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
GPIO+0130h
Bit
15
14
GPIO data output register 5
13
12
Name
Type
Reset
11
10
9
8
7
6
5
4
GPIO GPIO GPIO GPIO GPIO GPIO GPIO
74
73
72
71
70
69
68
R/W R/W R/W R/W R/W R/W R/W
0
0
0
0
0
0
0
3
GPIO_DOUT5
2
1
0
Co
nf
id
en
tia
l
GPIOn GPIO data output control
0 GPIOs data output 0
1 GPIOs data output 1
GPIO +0140h GPIO data Input register 1
Bit
GPIO_DIN1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO
Name
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
GPIO +0150h GPIO data Input register 2
Bit
GPIO_DIN2
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO PGIO GPIO GPIO GPIO GPIO
Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
GPIO +0160h GPIO data Input register 3
GPIO_DIN3
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO
Name
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
MT
K
Bit
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MediaTek Inc. Confidential
GPIO+0170h
GPIO data input register 4
Revision 1.0
Ko
nk
a
MT6228 GSM/GPRS Baseband Processor Data Sheet
GPIO_DIN4
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO
Name
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Reset X
Bit
15
GPIO data input register 5
14
13
12
11
Name
Type
Reset
GPIO_DIN5
10
9
8
7
6
5
4
GPIO GPIO GPIO GPIO GPIO GPIO GPIO
74
73
72
71
70
69
68
RO
RO
RO
RO
RO
RO
RO
X
X
X
X
X
X
X
3
2
1
fo
r
GPIO+0180h
0
GPIO +0190h GPO data output register
Bit
Name
Type
Reset
15
14
13
12
11
10
9
8
GPOn GPOs data output
Re
lea
se
GPIOn GPIOs data input
7
6
5
4
GPIO +01A0h GPIO mode control register 1
15
14
GPIO7_M
R/W
00
11
10
GPIO5_M
R/W
00
9
8
GPIO4_M
R/W
00
7
6
GPIO3_M
R/W
00
5
4
GPIO2_M
R/W
00
GPIO_MODE1
3
2
GPIO1_M
R/W
00
1
0
GPIO0_M
R/W
00
GPIO mode selection
Configured as GPIO function
CMOS Sensor Flash Control Output
Reserved
DSP Task ID5
GPIO mode selection
Configured as GPIO function
BSI Auxiliary input
Reserved
Reserved
GPIO mode selection
Configured as GPIO function
SCCB Clock
Reserved
Reserved
GPIO mode selection
Configured as GPIO function
SCCB Data
Reserved
Reserved
GPO mode selection
Configured as GPIO function
MT
K
GPIO0_M
00
01
10
11
GPIO1_M
00
01
10
11
GPIO2_M
00
01
10
11
GPIO3_M
00
01
10
11
GPIO4_M
00
13
12
GPIO6_M
R/W
00
2
1
0
GPO2 GPO1 GPO0
R/W R/W R/W
0
0
0
Co
nf
id
en
tia
l
Bit
Name
Type
Reset
3
GPO_DOUT
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MediaTek Inc. Confidential
fo
r
EDI (I2S) Clock Output
UART2 RXD Signal
Software Debug Interface Data Bit 7
GPIO mode selection
Configured as GPIO function
EDI (I2S) Word Synchronization Output
UART2 TXD Signal
Software Debug Interface Data Bit 6
GPIO mode selection
Configured as GPIO function
EDI (I2S) Data Signal
Reserved
Software Debug Interface Data Bit 5
GPIO mode selection
Configured as GPIO function
Reserved
USB-OTG Bus Power On Control
Software Debug Interface Data Bit 4
Re
lea
se
01
10
11
GPIO5_M
00
01
10
11
GPIO6_M
00
01
10
11
GPIO7_M
00
01
10
11
GPIO +01B0h GPIO mode control register 2
Bit
15
14
Name GPIO15_M
Type
R/W
Reset
00
11
10
GPIO13_M
R/W
00
9
8
GPIO12_M
R/W
00
7
6
GPIO11_M
R/W
00
5
4
GPIO10_M
R/W
00
GPIO_MODE2
3
2
GPIO9_M
R/W
00
1
0
GPIO8_M
R/W
00
Co
nf
id
en
tia
l
GPIO mode selection
Configured as GPIO function
32KHz Clock
USB-OTG Bus Charging Enable Control
Software Debug Interface Full Signal
GPIO mode selection
Configured as GPIO function
26MHz Clock
13MHz Clock
Software Debug Interface Empty Signal
GPIO mode selection
Configured as GPIO function
Parallel NAND FLASH/LCD Interface Data Bit 16
MMC4.0 Data Bit 4
DID (DSP ICE Data Signal)
GPIO mode selection
Configured as GPIO function
Parallel NAND FLASH/LCD Interface Data Bit 17
MMC4.0 Data Bit 5
DSP Task ID 1
GPIO mode selection
Configured as GPIO function
Sensor Reset Signal Output
Reserved
MT
K
GPIO8_M
00
01
10
11
GPIO9_M
00
01
10
11
GPIO10_M
00
01
10
11
GPIO11_M
00
01
10
11
GPIO12_M
00
01
10
13
12
GPIO14_M
R/W
00
Revision 1.0
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nk
a
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MediaTek Inc. Confidential
fo
r
Reserved
GPIO mode selection
Configured as GPIO function
Sensor Power Down Signal Output
Reserved
Reserved
GPIO mode selection
Configured as GPIO function
Sensor Data Input 1
MMC4.0 Data Bit 6
Reserved
GPIO mode selection
Configured as GPIO function
Sensor Data Input 0
MMC4.0 Data Bit 7
Reserved
Re
lea
se
11
GPIO13_M
00
01
10
11
GPIO14_M
00
01
10
11
GPIO15_M
00
01
10
11
GPIO +01C0h GPIO mode control register 3
Bit
15
14
Name GPIO23_M
Type
R/W
Reset
00
11
10
GPIO21_M
R/W
00
9
8
GPIO20_M
R/W
00
7
6
GPIO19_M
R/W
00
5
4
GPIO18_M
R/W
00
GPIO_MODE3
3
2
GPIO17_M
R/W
00
1
0
GPIO16_M
R/W
00
Co
nf
id
en
tia
l
GPIO mode selection
Configured as GPIO function
BPI_BUS6
Reserved
Reserved
GPIO mode selection
Configured as GPIO function
BPI_BUS7
13MHz Clock
26MHz Clock
GPIO mode selection
Configured as GPIO function
BPI_BUS8
6.5MHz Clock
32KHz Clock
GPIO mode selection
Configured as GPIO function
BPI_BUS9
BSI_CS1
BFE Debug Signal Output
GPIO mode selection
Configured as GPIO function
Serial LCD Interface/PM IC Interface Clock Signal
TDMA Timer Debug Port Clock Output
TDMA Timer Uplink Frame Enable Signal
GPIO mode selection
MT
K
GPIO16_M
00
01
10
11
GPIO17_M
00
01
10
11
GPIO18_M
00
01
10
11
GPIO19_M
00
01
10
11
GPIO20_M
00
01
10
11
GPIO21_M
13
12
GPIO22_M
R/W
00
Revision 1.0
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nk
a
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fo
r
Configured as GPIO function
Serial LCD Interface Address/Data Signal
TDMA Timer Debug Port Data Output 1
TDMA Timer DIRQ Signal
GPIO mode selection
Configured as GPIO function
Serial LCD Interface Data/PM IC Interface Data Signal
TDMA Timer Debug Port Data Output 0
TDMA Timer CTIRQ2 Signal
GPIO mode selection
Configured as GPIO function
Serial LCD Interface/PM IC Interface Chip Select Signal 0
TDMA Timer Debug Port Frame Sync Signal
TDMA Timer CTIRQ1 Signal
Re
lea
se
00
01
10
11
GPIO22_M
00
01
10
11
GPIO23_M
00
01
10
11
GPIO +01D0h GPIO mode control register 4
Bit
15
14
Name GPIO31_M
Type
R/W
Reset
00
11
10
GPIO29_M
R/W
00
9
8
GPIO28_M
R/W
00
7
6
GPIO27_M
R/W
00
5
4
GPIO26_M
R/W
00
GPIO_MODE4
3
2
GPIO25_M
R/W
00
1
0
GPIO24_M
R/W
00
Co
nf
id
en
tia
l
GPIO mode selection
Configured as GPIO function
Serial LCD Interface Chip Select Signal 1
Parallel LCD Interface Chip Select Signal 2
TDMA Timer Event Validate Signal
GPIO mode selection
Configured as GPIO function
Parallel LCD Interface Chip Select Signal 1
NAND FLASH Interface Chip Select Signal 1
DSP Task ID 0
GPIO mode selection
NAND FLASH Interface Ready/Busy Signal
Configured as GPIO function
USB-OTG Session Valid Signal
Software Debug Interface Data Bit 2
GPIO mode selection
NAND FLASH Interface Command Latch Signal
Configured as GPIO function
USB-OTG VBus Valid Signal
Software Debug Interface Data Bit 1
GPIO mode selection
NAND FLASH Interface Address Latch Signal
Configured as GPIO function
USB-OTG Session End Signal
Software Debug Interface Data Bit 0
GPIO mode selection
NAND FLASH Interface Write Strobe Signal
Configured as GPIO function
MT
K
GPIO24_M
00
01
10
11
GPIO25_M
00
01
10
11
GPIO26_M
00
01
10
11
GPIO27_M
00
01
10
11
GPIO28_M
00
01
10
11
GPIO29_M
00
01
13
12
GPIO30_M
R/W
00
Revision 1.0
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nk
a
MT6228 GSM/GPRS Baseband Processor Data Sheet
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Reserved
Reserved
GPIO mode selection
NAND FLASH Interface Read Strobe Signal
Configured as GPIO function
USB-OTG Bus Power Discharging Control Signal
Software Debug Interface Clock Output Signal
GPIO mode selection
NAND FLASH Interface Chip Select Signal 0
Configured as GPIO function
Reserved
Reserved
fo
r
10
11
GPIO30_M
00
01
10
11
GPIO31_M
00
01
10
11
11
10
GPIO37_M
R/W
00
9
8
GPIO36_M
R/W
00
5
4
GPIO34_M
R/W
00
3
2
GPIO33_M
R/W
00
1
0
GPIO32_M
R/W
00
Co
nf
id
en
tia
l
GPIO mode selection
Configured as GPIO function
PWM1
TDMA Timer Uplink Frame Sync Signal
DSP Task ID2
GPIO mode selection
Configured as GPIO function
PWM2
TDMA Timer Downlink Frame Enable Signal
DSP Task ID3
GPIO mode selection
Configured as GPIO function
Alerter
TDMA Timer Downlink Frame Sync Signal
DSP Task ID4
GPIO mode selection
Configured as GPIO function
VCXO Enable Signal Input
Reserved
Reserved
GPIO mode selection
Configured as GPIO function
MIRQ Signal
6.5 MHz Clock Signal
32 KHz Clock Signal
GPIO mode selection
Configured as GPIO function
UART2 RXD Signal
UART3 CTS Signal
Reserved
7
6
GPIO35_M
R/W
00
MT
K
GPIO32_M
00
01
10
11
GPIO33_M
00
01
10
11
GPIO34_M
00
01
10
11
GPIO35_M
00
01
10
11
GPIO36_M
00
01
10
11
GPIO37_M
00
01
10
11
13
12
GPIO38_M
R/W
00
GPIO_MODE5
Re
lea
se
GPIO +01E0h GPIO mode control register 5
Bit
15
14
Name GPIO39_M
Type
R/W
Reset
00
Revision 1.0
Ko
nk
a
MT6228 GSM/GPRS Baseband Processor Data Sheet
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GPIO mode selection
Configured as GPIO function
UART2 TXD Signal
UART3 RTS Signal
Reserved
GPIO mode selection
Configured as GPIO function
UART3 RXD Signal
Reserved
Reserved
GPIO +01F0h GPIO mode control register 6
11
10
GPIO45_M
R/W
00
7
6
GPIO43_M
R/W
00
5
4
GPIO42_M
R/W
00
3
2
GPIO41_M
R/W
00
1
0
GPIO40_M
R/W
00
Co
nf
id
en
tia
l
GPIO mode selection
Configured as GPIO function
UART3 TXD Signal
Reserved
DSP Task ID5
GPIO mode selection
Configured as GPIO function
IrDA RXD Signal
UART2 CTS Signal
Software Debug Interface Data 15
GPIO mode selection
Configured as GPIO function
IrDA TXD Signal
UART2 RTS Signal
Software Debug Interface Data 14
GPIO mode selection
Configured as GPIO function
IrDA Power Down Control Signal
Reserved
Software Debug Interface Data 13
GPIO mode selection
Keypad Row 5 Scan Signal
Configured as GPIO function
ARM Clock Output
TV_CK Clock Output
GPIO mode selection
Keypad Row 4 Scan Signal
Configured as GPIO function
Internal AHB Bus Clock Output
DSP Clock Output
GPIO mode selection
Keypad Row 3 Scan Signal
9
8
GPIO44_M
R/W
00
MT
K
GPIO40_M
00
01
10
11
GPIO41_M
00
01
10
11
GPIO42_M
00
01
10
11
GPIO43_M
00
01
10
11
GPIO44_M
00
01
10
11
GPIO45_M
00
01
10
11
GPIO46_M
00
13
12
GPIO46_M
R/W
00
GPIO_MODE6
Re
lea
se
Bit
15
14
Name GPIO47_M
Type
R/W
Reset
00
Ko
nk
a
GPIO38_M
00
01
10
11
GPIO39_M
00
01
10
11
Revision 1.0
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Configured as GPIO function
TPLL Clock Output
SLOW_CK Clock Output
GPIO mode selection
Keypad Row 2 Scan Signal
Configured as GPIO function
MCU/DSP PLL Clock Output
UPLL Clock Output
GPIO +0200h GPIO mode control register 7
15
14
GPIO55
R/W
0
11
10
GPIO53
R/W
0
9
8
GPIO52
R/W
0
GPIO_MODE7
7
6
GPIO51
R/W
0
5
4
GPIO50
R/W
0
3
2
GPIO49
R/W
0
1
0
GPIO48
R/W
0
Re
lea
se
GPIO mode selection
Configured as GPIO function
SIM Interface Voltage Select Signal
Reserved
Reserved
GPIO mode selection
Configured as GPIO function
Digital Audio Interface Clock Output
Reserved
Software Debug Interface Data Bit 12
GPIO mode selection
Configured as GPIO function
Digital Audio Interface PCM Data Output
Reserved
Software Debug Interface Data Bit 11
GPIO mode selection
Configured as GPIO function
Digital Audio Interface PCM Data Input
Reserved
Software Debug Interface Data Bit 10
GPIO mode selection
Configured as GPIO function
Digital Audio Interface Reset Signal Output
Reserved
Software Debug Interface Data Bit 9
GPIO mode selection
Configured as GPIO function
Digital Audio Interface Synchronization Signal Input
Reserved
Software Debug Interface Data Bit 8
GPIO mode selection
NAND FLASH/Parallel LCD Interface Data Bit 8
Configured as GPIO function
Reserved
MT
K
GPIO48_M
00
01
10
11
GPIO49_M
00
01
10
11
GPIO50_M
00
01
10
11
GPIO51_M
00
01
10
11
GPIO52_M
00
01
10
11
GPIO53_M
00
01
10
11
GPIO54_M
00
01
10
13
12
GPIO54
R/W
0
Co
nf
id
en
tia
l
Bit
Name
Type
Reset
fo
r
01
10
11
GPIO47_M
00
01
10
11
Revision 1.0
Ko
nk
a
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11
GPIO55_M
00
01
10
11
Software Debug Interface Address Bit 1
GPIO mode selection
NAND FLASH/Parallel LCD Interface Data Bit 9
Configured as GPIO function
Reserved
Software Debug Interface Address Bit 0
GPIO +0210h GPIO mode control register 8
11
10
GPIO61
R/W
0
9
8
GPIO60
R/W
0
GPIO_MODE8
7
6
GPIO59
R/W
0
3
2
GPIO57
R/W
0
1
0
GPIO56
R/W
0
Re
lea
se
GPIO mode selection
NAND FLASH/Parallel LCD Interface Data Bit 10
Configured as GPIO function
Reserved
Software Debug Interface Read Output Enable Control
GPIO mode selection
NAND FLASH/Parallel LCD Interface Data Bit 11
Configured as GPIO function
Reserved
Software Debug Interface Read Strobe Control
GPIO mode selection
NAND FLASH/Parallel LCD Interface Data Bit 12
Configured as GPIO function
Reserved
Software Debug Interface Write Strobe Control
GPIO mode selection
NAND FLASH/Parallel LCD Interface Data Bit 13
Configured as GPIO function
Reserved
Software Debug Interface Packet End Strobe Control
GPIO mode selection
NAND FLASH/Parallel LCD Interface Data Bit 14
Configured as GPIO function
Reserved
DICK (DSP ICE Clock Input)
GPIO mode selection
NAND FLASH/Parallel LCD Interface Data Bit 15
Configured as GPIO function
Reserved
DIMS (DSP ICE Mode Select)
GPIO mode selection
Sensor Input Data Bit 2
Configured as GPIO function
Reserved
Reserved
GPIO mode selection
5
4
GPIO58
R/W
0
MT
K
GPIO56_M
00
01
10
11
GPIO57_M
00
01
10
11
GPIO58_M
00
01
10
11
GPIO59_M
00
01
10
11
GPIO60_M
00
01
10
11
GPIO61_M
00
01
10
11
GPIO62_M
00
01
10
11
GPIO63_M
13
12
GPIO62
R/W
0
fo
r
15
14
GPIO63
R/W
0
Co
nf
id
en
tia
l
Bit
Name
Type
Reset
Revision 1.0
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nk
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MediaTek Inc. Confidential
00
01
10
11
Configured as GPIO function
MFIQ Signal
USB-OTG ID
Software Debug Interface Data Bit 3
GPIO +0220h GPIO mode control register 9
11
10
GPIO69
R/W
0
9
8
GPIO68
R/W
0
GPIO mode selection
Sensor Input Data Bit 3
Configured as GPIO function
Reserved
Reserved
GPIO mode selection
Sensor Input Data Bit 4
Configured as GPIO function
Reserved
Reserved
GPIO mode selection
Sensor Input Data Bit 5
Configured as GPIO function
Reserved
Reserved
GPIO mode selection
Sensor Input Data Bit 6
Configured as GPIO function
Reserved
Reserved
7
6
5
4
GPIO +0230h GPIO mode control register 10
Bit
Name
Type
Reset
15
13
12
11
2
1
0
10
9
8
7
GPIO_MODE10
6
5
4
GPIO74
R/W
0
3
2
GPIO73
R/W
0
1
0
GPIO72
R/W
0
GPIO mode selection
Sensor Input Data Bit 7
Configured as GPIO function
Reserved
Reserved
GPIO mode selection
Sensor Input Data Bit 8
Configured as GPIO function
Reserved
Reserved
GPIO mode selection
Sensor Input Data Bit 9
MT
K
GPIO72_M
00
01
10
11
GPIO73_M
00
01
10
11
GPIO74_M
00
14
3
Re
lea
se
GPIO68_M
00
01
10
11
GPIO69_M
00
01
10
11
GPIO70_M
00
01
10
11
GPIO71_M
00
01
10
11
13
12
GPIO70
R/W
0
fo
r
15
14
GPIO71
R/W
0
GPIO_MODE9
Co
nf
id
en
tia
l
Bit
Name
Type
Reset
Revision 1.0
Ko
nk
a
MT6228 GSM/GPRS Baseband Processor Data Sheet
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MediaTek Inc. Confidential
01 Configured as GPIO function
10 Reserved
11 Reserved
GPIO +0240h GPO mode control register 1
GPO0_M
00
01
10
11
GPO1_M
00
01
10
11
GPO2_M
00
01
10
11
14
13
12
11
10
9
8
GPO_MODE1
7
6
5
4
GPO2_M
R/W
01
GPO mode selection
Configured as GPO function
VCXO Enable Signal Output Active High
Reserved
Reserved
GPO mode selection
Configured as GPO function
VCXO Enable Signal Output Active Low
Reserved
Reserved
GPO mode selection
Configured as GPO function
External Memory Interface Power Down Control for Pseudo SRAM
Reserved
Reserved
3
2
GPO1_M
R/W
01
1
0
GPO0_M
R/W
01
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Reset
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GPIO+xxx4h
GPIO xxx register SET
GPIO_XXX_SET
GPIO+xxx8h
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For all registers addresses listed above, writing to the +4h addresse offset will perform a bit-wise OR function between
the 16bit written value and the 16bit register value already existing in the corresponding GPIO_xxx registers.
Eg.
If GPIO_DIR1 (GPIO+0000h) = 16’h0F0F,
writing GPIO_DIR1_SET (GPIO+0004h) = 16’F0F0 will result in GPIO_DIR1 = 16’hFFFF.
GPIO xxx register CLR
GPIO_XXX_CLR
For all registers addresses listed above, writing to the +8h addresse offset will perform a bit-wise AND-NOT function
between the 16bit written value and the 16bit register value already existing in the corresponding GPIO_xxx registers.
Eg.
If GPIO_DIR1 (GPIO+0000h) = 16’h0F0F,
writing GPIO_DIR1_CLR (GPIO+0008h) = 16’0F0F will result in GPIO_DIR1 = 16’h0000.
4.6
4.6.1
General Purpose Timer
General Description
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Three general-purpose timers are provided. The timers are 16 bits long and run independently of each other, although
they share the same clock source. Two timers can operate in one of two modes: one-shot mode and auto-repeat mode;
the other is a free running timer. In one-shot mode, when the timer counts down and reaches zero, it is halted. In
auto-repeat mode, when the timer reaches zero, it simply resets to countdown initial value and repeats the countdown to
zero; this loop repeats until the disable signal is set to 1. Regardless of the timer’s mode, if the countdown initial
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value (i.e. GPTIMER1_DAT for GPT1 or GPTIMER_DAT2 for GPT2) is written when the timer is running, the new
initial value does not take effect until the next time the timer is restarted. In auto-repeat mode, the new countdown
start value is used on the next countdown iteration. Therefore, before enabling the gptimer, the desired values for
GPTIMER_DAT and the GPTIMER_PRESCALER registers must first be set.
Register Definitions
GPT +0000h
GPTIMER1_CO
N
GPT1 Control register
Bit
15
14
Name EN MODE
Type R/W R/W
Reset
0
0
13
12
11
10
9
8
7
6
5
4
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4.6.2
3
2
1
0
GPT +0004h
15
GPTIMER1_DA
T
GPT1 Time-Out Interval register
14
13
12
11
10
9
8
7
CNT [15:0]
R/W
FFFFh
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Bit
Name
Type
Reset
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MODE This register controls GPT1 to count repeatedly (in a loop) or just one-shot.
0 One-shot mode is selected.
1 Auto-repeat mode is selected.
EN
This register controls GPT1 to start counting or to stop.
0 GPT1 is disabled.
1 GPT1 is enabled.
6
5
CNT [15:0] Initial counting value. GPT1 counts down from GPTIMER1_DAT.
a GPT1 interrupt is generated.
GPT +0008h
Bit
15
14
Name EN MODE
Type R/W R/W
Reset
0
0
4
3
12
11
10
9
8
7
1
0
When GPT1 counts down to zero,
GPTIMER2_CO
N
GPT2 Control register
13
2
6
5
4
3
2
1
0
MODE This register controls GPT2 to count repeatedly (in a loop) or just one-shot.
0 One-shot mode is selected
1 Auto-repeat mode is selected
EN
This register controls GPT2 to start counting or to stop.
0 GPT2 is disabled.
1 GPT2 is enabled.
Bit
Name
Type
Reset
15
14
GPTIMER2_DA
T
GPT2 Time-Out Interval register
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GPT +000Ch
13
12
11
10
9
8
7
CNT [15:0]
R/W
FFFFh
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4
3
2
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CNT [15:0] Initial counting value. GPT2 counts down from GPTIMER2_DAT.
a GPT2 interrupt is generated.
GPT +0010h
Bit
Name
Type
Reset
15
14
When GPT2 counts down to zero,
GPT Status register
13
12
11
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GPTIMER_STA
9
8
7
6
5
4
3
2
1
0
GPT2 GPT1
RC
RC
0
0
Bit
Name
Type
Reset
15
14
GPTIMER1_PRES
CALER
GPT1 Prescaler register
13
12
11
10
9
8
7
6
5
4
3
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GPT +0014h
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This register illustrates the gptimer timeout status. Each flag is set when the corresponding timer countdown
completes, and can be cleared when the CPU reads the status register.
2
1
0
PRESCALER [2:0]
R/W
100b
GPT +0018h
Bit
Name
Type
Reset
15
14
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PRESCALER This register controls the counting clock for gptimer1.
000 16 KHz
001 8 KHz
010 4 KHz
011 2 KHz
100 1 KHz
101 500 Hz
110 250 Hz
111 125 Hz
GPTIMER2_PRES
CALER
GPT2 Prescaler register
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PRESCALER [2:0]
R/W
100b
PRESCALER This register controls the counting clock for gptimer2.
000 16 KHz
001 8 KHz
010 4 KHz
011 2 KHz
100 1 KHz
101 500 Hz
110 250 Hz
111 125 Hz
Bit
Name
Type
Reset
15
14
GPTIMER3_CO
N
GPT3 Control register
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GPT+001Ch
13
12
11
10
9
8
7
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0
EN
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This register controls GPT3 to start counting or to stop.
0 GPT3 is disabled.
1 GPT3 is enabled.
Bit
Name
Type
Reset
15
14
13
12
11
10
9
CNT [15:0] If EN=1, GPT3 is a free running timer .
GPT3.
GPT+0024h
Bit
Name
Type
Reset
15
GPTIMER3_DA
T
GPT3 Time-Out Interval register
8
7
CNT[15:0]
RO
0
13
12
11
10
9
5
4
3
2
1
0
Software reads this register for the countdown start value for
GPTIMER3_PRES
CALER
GPT3 Prescaler register
14
6
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GPT+0020h
8
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7
6
5
4
3
2
1
0
PRESCALER [2:0]
R/W
100b
4.7
4.7.1
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PRESCALER This register controls the counting clock for gptimer3.
000 16 KHz
001 8 KHz
010 4 KHz
011 2 KHz
100 1 KHz
101 500 Hz
110 250 Hz
112 125 Hz
UART
General Description
MT6228 houses three UARTs. The UARTs provide full duplex serial communication channels between the MT6228
and external devices.
The UART has M16C450 and M16550A modes of operation, which are compatible with a range of standard software
drivers. The extensions have been designed to be broadly software compatible with 16550A variants, but certain areas
offer no consensus.
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In common with the M16550A, the UART supports word lengths from five to eight bits, an optional parity bit and one
or two stop bits, and is fully programmable by an 8-bit CPU interface. A 16-bit programmable baud rate generator
and an 8-bit scratch register are included, together with separate transmit and receive FIFOs. Eight modem control
lines and a diagnostic loop-back mode are provided. The UART also includes two DMA handshake lines, used to
indicate when the FIFOs are ready to transfer data to the CPU. Interrupts can be generated from any of the 10
sources.
Note: The UART has been designed so that all internal operations are synchronized by the CLK signal.
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synchronization results in minor timing differences between the UART and the industry standard 16550A device, which
means that the core is not clock for clock identical to the original device.
After a hardware reset, the UART is in M16C450 mode. Its FIFOs can be enabled and the UART can then enter
M16550A mode. The UART adds further functionality beyond M16550A mode. Each of the extended functions can
be selected individually under software control.
The UART provides more powerful enhancements than the industry-standard 16550:
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Hardware flow control. This feature is very useful when the ISR latency is hard to predict and control in the
embedded applications. The MCU is relieved of having to fetch the received data within a fixed amount of
time.
Output of an IR-compatible electrical pulse with a width 3/16 of that of a regular bit period.
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Note: In order to enable any of the enhancements, the Enhanced Mode bit, EFR[4], must be set. If EFR[4] is not set,
IER[7:5], FCR[5:4], ISR[5:4] and MCR[7:6] cannot be written. The Enhanced Mode bit ensures that the UART is
backward compatible with software that has been written for 16C450 and 16550A devices.
Figure 49 shows the block diagram of the MT6228 UART device.
Baud Rate
Generator
divisor
baud
clock
TX FIFO
APB
BUS
I/F
RX FIFO
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APB Bus
TX Machine
uart_tx_data
RX Machine
uart_rx_data
Modem Outputs
Modem
Control
Modem Inputs
Figure 49 Block Diagram of UART
4.7.2
Register Definitions
n = 1, 2, 3; for uart1, uart2 and uart3 respectively.
UARTn+0000h RX Buffer Register
15
14
13
RBR
RX Buffer Register. Read-only register.
Modified when LCR[7] = 0.
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Bit
Name
Type
12
11
10
9
8
7
UARTn_RBR
6
5
4
3
RBR[7:0]
RO
15
14
13
12
11
10
1
0
The received data can be read by accessing this register.
UARTn+0000h TX Holding Register
Bit
Name
Type
2
UARTn_THR
9
8
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THR
TX Holding Register. Write-only register.
sent to the PC via serial communication.
Modified when LCR[7] = 0.
The data to be transmitted is written to this register, and then
UARTn+0004h Interrupt Enable Register
IER
By storing a ‘1’ to a specific bit position, the interrupt associated with that bit is enabled. Otherwise, the
interrupt is disabled.
IER[3:0] are modified when LCR[7] = 0.
IER[7:4] are modified when LCR[7] = 0 & EFR[4] = 1.
Masks an interrupt that is generated when a rising edge is detected on the CTS modem control line.
Note: This interrupt is only enabled when hardware flow control is enabled.
0 Unmask an interrupt that is generated when a rising edge is detected on the CTS modem control line.
1 Mask an interrupt that is generated when a rising edge is detected on the CTS modem control line.
Masks an interrupt that is generated when a rising edge is detected on the RTS modem control line.
Note: This interrupt is only enabled when hardware flow control is enabled.
0 Unmask an interrupt that is generated when a rising edge is detected on the RTS modem control line.
1 Mask an interrupt that is generated when a rising edge is detected on the RTS modem control line.
Masks an interrupt that is generated when an XOFF character is received.
Note: This interrupt is only enabled when software flow control is enabled.
0 Unmask an interrupt that is generated when an XOFF character is received.
1 Mask an interrupt that is generated when an XOFF character is received.
When set ("1"), an interrupt is generated if DDCD, TERI, DDSR or DCTS (MSR[4:1]) becomes set.
0 No interrupt is generated if DDCD, TERI, DDSR or DCTS (MSR[4:1]) becomes set.
1 An interrupt is generated if DDCD, TERI, DDSR or DCTS (MSR[4:1]) becomes set.
When set ("1"), an interrupt is generated if BI, FE, PE or OE (LSR[4:1]) becomes set.
0 No interrupt is generated if BI, FE, PE or OE (LSR[4:1]) becomes set.
1 An interrupt is generated if BI, FE, PE or OE (LSR[4:1]) becomes set.
When set ("1"), an interrupt is generated if the TX Holding Register is empty or the contents of the TX FIFO
have been reduced to its Trigger Level.
0 No interrupt is generated if the TX Holding Register is empty or the contents of the TX FIFO have been
reduced to its Trigger Level.
1 An interrupt is generated if the TX Holding Register is empty or the contents of the TX FIFO have been
reduced to its Trigger Level
When set ("1"), an interrupt is generated if the RX Buffer contains data.
0 No interrupt is generated if the RX Buffer contains data.
1 An interrupt is generated if the RX Buffer contains data.
EDSSI
ELSI
ETBEI
ERBFI
11
10
9
8
7
6
5
CTSI RTSI XOFFI
4
X
3
2
1
0
EDSSI ELSI ETBEI ERBFI
R/W
0
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XOFFI
12
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RTSI
13
UARTn_IER
Bit
Name
Type
Reset
CTSI
14
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UARTn+0008h Interrupt Identification Register
Bit
Name
Type
Reset
15
13
12
11
10
9
8
IIR
Identify if there are pending interrupts; ID4 and ID3 are presented only when EFR[4] = 1.
The following table gives the IIR[5:0] codes associated with the possible interrupts:
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UARTn_IIR
7
6
FIFOE
0
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ID4
4
ID3
0
0
RO
3
ID2
2
ID1
1
ID0
0
NINT
0
0
0
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Interrupt
Source
No interrupt pending
Line Status Interrupt
RX Data Received
RX Data Timeout
TX Holding Register Empty
Modem Status change
Software Flow Control
Hardware Flow Control
BI, FE, PE or OE set in LSR
RX Data received or RX Trigger Level reached.
Timeout on character in RX FIFO.
TX Holding Register empty or TX FIFO Trigger Level reached.
DDCD, TERI, DDSR or DCTS set in MSR
XOFF Character received
CTS or RTS Rising Edge
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IIR[5:0] Priority
Level
000001 000110 1
000100 2
001100 2
000010 3
000000 4
010000 5
100000 6
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Table 25 The IIR[5:0] codes associated with the possible interrupts
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Line Status Interrupt: A RX Line Status Interrupt (IIR[5:0`] == 000110b) is generated if ELSI (IER[2]) is set and any of
BI, FE, PE or OE (LSR[4:1]) becomes set. The interrupt is cleared by reading the Line Status Register.
RX Data Received Interrupt: A RX Received interrupt (IER[5:0] == 000100b) is generated if EFRBI (IER[0]) is set and
either RX Data is placed in the RX Buffer Register or the RX Trigger Level is reached. The interrupt is cleared by
reading the RX Buffer Register or the RX FIFO (if enabled).
RX Data Timeout Interrupt:
When virtual FIFO mode is disabled, RX Data Timeout Interrupt is generated if all of the following apply:
FIFO contains at least one character;
2.
The most recent character was received longer than four character periods ago (including all start, parity and stop
bits);
3.
The most recent CPU read of the FIFO was longer than four character periods ago.
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1.
The timeout timer is restarted on receipt of a new byte from the RX Shift Register, or on a CPU read from the RX
FIFO.
The RX Data Timeout Interrupt is enabled by setting EFRBI (IER[0]) to 1, and is cleared by reading RX FIFO.
When virtual FIFO mode is enabled, RX Data Timeout Interrupt is generated if all of the following apply:
1.
FIFO is empty;
2.
The most recent character was received longer than four character periods ago (including all start, parity and stop
bits);
3.
The most recent CPU read of the FIFO was longer than four character periods ago.
The timeout timer is restarted on receipt of a new byte from the RX Shift Register.
RX Holding Register Empty Interrupt: A TX Holding Register Empty Interrupt (IIR[5:0] = 000010b) is generated if
ETRBI (IER[1]) is set and either the TX Holding Register or, if FIFOs are enabled, the TX FIFO becomes empty. The
interrupt is cleared by writing to the TX Holding Register or TX FIFO if FIFO enabled.
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Modem Status Change Interrupt: A Modem Status Change Interrupt (IIR[5:0] = 000000b) is generated if EDSSI
(IER[3]) is set and either DDCD, TERI, DDSR or DCTS (MSR[3:0]) becomes set. The interrupt is cleared by reading
the Modem Status Register.
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Software Flow Control Interrupt: A Software Flow Control Interrupt (IIR[5:0] = 010000b) is generated if Software
Flow Control is enabled and XOFFI (IER[5]) becomes set, indicating that an XOFF character has been received. The
interrupt is cleared by reading the Interrupt Identification Register.
Hardware Flow Control Interrupt: A Hardware Flow Control Interrupt (IER[5:0] = 100000b) is generated if Hardware
Flow Control is enabled and either RTSI (IER[6]) or CTSI (IER[7]) becomes set indicating that a rising edge has been
detected on either the RTS/CTS Modem Control line. The interrupt is cleared by reading the Interrupt Identification
Register.
Bit
Name
Type
15
14
13
12
11
10
UARTn_FCR
9
8
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UARTn+0008h FIFO Control Register
7
6
5
4
3
2
1
0
RFTL1 RFTL0 TFTL1 TFTL0 DMA1 CLRT CLRR FIFOE
WO
FCR
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FCR is used to control the trigger levels of the FIFOs, or flush the FIFOs.
FCR[7:6] is modified when LCR != BFh
FCR[5:4] is modified when LCR != BFh & EFR[4] = 1
FCR[4:0] is modified when LCR != BFh
FCR[7:6] RX FIFO trigger threshold
0 1
0 6
1 12
2 22
FCR[5:4] TX FIFO trigger threshold
0 1
1 4
2 8
3 14
DMA1 This bit determines the DMA mode, which the TXRDY and RXRDY pins support. TXRDY and RXRDY act
to support single-byte transfers between the UART and memory (DMA mode 0) or multiple byte transfers
(DMA mode1). Note that this bit has no effect unless the FIFOE bit is set as well
0 The device operates in DMA Mode 0.
1 The device operates in DMA Mode 1.
TXRDY – mode0: Goes active (low) when the TX FIFO or the TX Holding Register is empty. Becomes
inactive when a byte is written to the Transmit channel.
TXRDY – mode1: Goes active (low) when there are no characters in the TX FIFO. Becomes inactive when
the TX FIFO is full.
RXRDY – mode0: Becomes active (low) when at least one character is in the RX FIFO or the RX Buffer
Register is full. Becomes inactive when there are no more characters in the RX FIFO or RX Buffer
register.
RXRDY – mode1: Becomes active (low) when the RX FIFO Trigger Level is reached or an RX FIFO
Character Timeout occurs. Goes inactive when the RX FIFO is empty.
CLRT Clear Transmit FIFO. This bit is self-clearing.
0 Leave TX FIFO intact.
1 Clear all the bytes in the TX FIFO.
CLRR Clear Receive FIFO. This bit is self-clearing.
0 Leave RX FIFO intact.
1 Clear all the bytes in the RX FIFO.
FIFOE FIFO Enabled. This bit must be set to 1 for any of the other bits in the registers to have any effect.
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0
1
Disable both the RX and TX FIFOs.
Enable both the RX and TX FIFOs.
UARTn+000Ch Line Control Register
Bit
Name
Type
Reset
15
14
13
12
11
10
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UARTn_LCR
9
8
7
DLAB
6
SB
5
SP
0
0
0
4
3
EPS PEN
R/W
0
0
2
1
0
STB WLS1 WLS0
0
0
0
LCR
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Line Control Register. Determines characteristics of serial communication signals.
Modified when LCR[7] = 0.
DLAB Divisor Latch Access Bit.
0 The RX and TX Registers are read/written at Address 0 and the IER register is read/written at Address 4.
1 The Divisor Latch LS is read/written at Address 0 and the Divisor Latch MS is read/written at Address 4.
SB
Set Break
0 No effect
1 SOUT signal is forced into the “0” state.
SP
Stick Parity
0 No effect.
1 The Parity bit is forced into a defined state, depending on the states of EPS and PEN:
If EPS=1 & PEN=1, the Parity bit is set and checked = 0.
If EPS=0 & PEN=1, the Parity bit is set and checked = 1.
EPS
Even Parity Select
0 When EPS=0, an odd number of ones is sent and checked.
1 When EPS=1, an even number of ones is sent and checked.
PEN
Parity Enable
0 The Parity is neither transmitted nor checked.
1 The Parity is transmitted and checked.
STB
Number of STOP bits
0 One STOP bit is always added.
1 Two STOP bits are added after each character is sent; unless the character length is 5 when 1 STOP bit is
added.
WLS1, 0
Word Length Select.
0 5 bits
1 6 bits
2 7 bits
3 8 bits
UARTn+0010h Modem Control Register
Bit
Name
Type
Reset
15
14
13
12
11
10
9
8
UARTn_MCR
7
6
XOFF IR
STAT ENAB
US
LE
0
0
5
X
0
4
3
2
1
LOOP OUT2 OUT1 RTS
0
R/W
0
0
0
0
DTR
0
MCR
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Modem Control Register. Control interface signals of the UART.
MCR[4:0] are modified when LCR[7] = 0,
MCR[7:6] are modified when LCR[7] = 0 & EFR[4] = 1.
XOFF Status This is a read-only bit.
0 When an XON character is received.
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Bit
15
14
13
Name
Type
Reset
LSR
12
11
10
9
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UARTn+0014h Line Status Register
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1 When an XOFF character is received.
IR Enable
Enable IrDA modulation/demodulation.
0 Disable IrDA modulation/demodulation.
1 Enable IrDA modulation/demodulation.
LOOP Loop-back control bit.
0 No loop-back is enabled.
1 Loop-back mode is enabled.
OUT2 Controls the state of the output NOUT2, even in loop mode.
0 NOUT2=1.
1 NOUT2=0.
OUT1 Controls the state of the output NOUT1, even in loop mode.
0 NOUT1=1.
1 NOUT1=0.
RTS
Controls the state of the output NRTS, even in loop mode.
0 NRTS=1.
1 NRTS=0.
DTR
Control the state of the output NDTR, even in loop mode.
0 NDTR=1.
1 NDTR=0.
8
7
6
5
FIFOE
TEMT THRE
RR
0
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1
1
UARTn_LSR
4
3
2
1
0
BI
FE
PE
OE
DR
0
0
0
0
0
R/W
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Line Status Register.
Modified when LCR[7] = 0.
FIFOERR RX FIFO Error Indicator.
0 No PE, FE, BI set in the RX FIFO.
1 Set to 1 when there is at least one PE, FE or BI in the RX FIFO.
TEMT TX Holding Register (or TX FIFO) and the TX Shift Register are empty.
0 Empty conditions below are not met.
1 If FIFOs are enabled, the bit is set whenever the TX FIFO and the TX Shift Register are empty. If FIFOs
are disabled, the bit is set whenever TX Holding Register and TX Shift Register are empty.
THRE Indicates if there is room for TX Holding Register or TX FIFO is reduced to its Trigger Level.
0 When at least one byte is written to the TX FIFO or the TX Shift Register.
1 Set whenever the contents of the TX FIFO are reduced to its Trigger Level (FIFOs are enabled), or
whenever TX Holding Register is empty and ready to accept new data (FIFOs are disabled).
BI
Break Interrupt.
0 Reset by the CPU reading this register
1 If the FIFOs are disabled, this bit is set whenever the SIN is held in the 0 state for more than one
transmission time (START bit + DATA bits + PARITY + STOP bits).
If the FIFOs are enabled, this error is associated with a corresponding character in the FIFO and is flagged
when this byte is at the top of the FIFO. When a break occurs, only one zero character is loaded into the
FIFO: the next character transfer is enabled when SIN goes into the marking state and receives the next
valid start bit.
FE
Framing Error.
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0
1
PE
Reset by the CPU reading this register
If the FIFOs are disabled, this bit is set if the received data did not have a valid STOP bit. If the FIFOs
are enabled, the state of this bit is revealed when the byte it refers to is the next to be read.
Parity Error
0 Reset by the CPU reading this register
1 If the FIFOs are disabled, this bit is set if the received data did not have a valid parity bit. If the FIFOs
are enabled, the state of this bit is revealed when the referred byte is the next to be read.
Overrun Error.
0 Reset by the CPU reading this register.
1 If the FIFOs are disabled, this bit is set if the RX Buffer was not read by the CPU before new data from
the RX Shift Register overwrote the previous contents.
If the FIFOs are enabled, an overrun error occurs when the RX FIFO is full and the RX Shift Register
becomes full. OE is set as soon as this happens. The character in the Shift Register is then overwritten,
but not transferred to the FIFO.
Data Ready.
0 Cleared by the CPU reading the RX Buffer or by reading all the FIFO bytes.
1 Set by the RX Buffer becoming full or by a byte being transferred into the FIFO.
DR
UARTn+0018h Modem Status Register
Bit
Name
Type
Reset
15
14
13
12
11
10
9
Re
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OE
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8
7
DCD
R/W
Input
6
RI
R/W
Input
5
DSR
R/W
Input
UARTn_MSR
4
3
2
1
0
CTS DDCD TERI DDSR DCTS
R/W R/W R/W R/W R/W
Input
0
0
0
0
Note: After a reset, D4-D7 are inputs. A modem status interrupt can be cleared by writing ‘0’ or set by writing ‘1’ to
this register. D0-D3 can be written to.
MSR
DCD
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Modified when LCR[7] = 0.
Modem Status Register
Data Carry Detect.
When Loop = "0", this value is the complement of the NDCD input signal.
RI
When Loop = "1", this value is equal to the OUT2 bit in the Modem Control Register.
Ring Indicator.
When Loop = "0", this value is the complement of the NRI input signal.
DSR
When Loop = "1", this value is equal to the OUT1 bit in the Modem Control Register.
Data Set Ready
When Loop = "0", this value is the complement of the NDSR input signal.
When Loop = "1", this value is equal to the DTR bit in the Modem Control Register.
CTS
Clear To Send.
When Loop = "0", this value is the complement of the NCTS input signal.
MT
K
When Loop = "1", this value is equal to the RTS bit in the Modem Control Register.
DDCD Delta Data Carry Detect.
0 The state of DCD has not changed since the Modem Status Register was last read
1 Set if the state of DCD has changed since the Modem Status Register was last read.
TERI Trailing Edge Ring Indicator
0 The NRI input does not change since this register was last read.
1 Set if the NRI input changes from “0” to “1” since this register was last read.
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DDSR Delta Data Set Ready
0 Cleared if the state of DSR has not changed since this register was last read.
1 Set if the state of DSR has changed since this register was last read.
DCTS Delta Clear To Send
0 Cleared if the state of CTS has not changed since this register was last read.
1 Set if the state of CTS has changed since this register was last read.
UARTn+001Ch Scratch Register
15
14
13
12
11
A general purpose read/write register.
UARTn_SCR
10
9
8
7
6
5
4
3
SCR[7:0]
R/W
2
1
0
fo
r
Bit
Name
Type
After reset, its value is un-defined.
Re
lea
se
Modified when LCR[7] = 0.
UARTn+0000h Divisor Latch (LS)
Bit
Name
Type
Reset
15
14
13
12
11
10
9
8
UARTn+0004h Divisor Latch (MS)
Bit
Name
Type
Reset
15
14
13
12
11
10
9
7
8
7
5
6
UARTn_DLL
4
3
DLL[7:0]
R/W
1
5
2
1
0
UARTn_DLM
4
3
DLL[7:0]
R/W
0
2
1
0
Note too that division by 1 generates a BAUD signal
Co
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Note: DLL & DLM can only be updated if DLAB is set (“1”)..
that is constantly high.
6
Modified when LCR[7] = 1.
MT
K
The table below shows the divisor needed to generate a given baud rate from CLK inputs of 13, 26 MHz and 52 MHz.
The effective clock enable generated is 16 x the required baud rate.
BAUD
110
13MHz
7386
26MHz
14773
52MHz
29545
300
1200
2400
4800
9600
19200
38400
57600
115200
2708
677
338
169
85
42
21
14
6
5417
1354
677
339
169
85
42
28
14
10833
2708
1354
677
339
169
85
56
28
Table 26 Divisor needed to generate a given baud rate
UARTn+0008h Enhanced Feature Register
Bit
15
14
13
12
11
10
9
8
UARTn_EFR
7
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AUTO AUTO
ENAB
D5
CTS RTS
LE -E
R/W R/W R/W R/W
0
0
0
0
Name
Type
Reset
SW FLOW CONT[3:0]
R/W
0
Re
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UARTn+0010h XON1
15
14
13
12
11
10
9
8
7
6
5
4
3
XON1[7:0]
R/W
0
12
11
10
9
8
7
6
5
4
3
XON2[7:0]
R/W
0
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Bit
Name
Type
Reset
fo
r
*NOTE: Only when LCR=BF’h
Auto CTS Enables hardware transmission flow control
0 Disabled.
1 Enabled.
Auto RTS Enables hardware reception flow control
0 Disabled.
1 Enabled.
Enable-E Enable enhancement features.
0 Disabled.
1 Enabled.
CONT[3:0] Software flow control bits.
00xx No TX Flow Control
10xx Transmit XON1/XOFF1 as flow control bytes
01xx Transmit XON2/XOFF2 as flow control bytes
11xx Transmit XON1 & XON2 and XOFF1 & XOFF2 as flow control words
xx00 No RX Flow Control
xx10 Receive XON1/XOFF1 as flow control bytes
xx01 Receive XON2/XOFF2 as flow control bytes
xx11 Receive XON1 & XON2 and XOFF1 & XOFF2 as flow control words
UARTn+0014h XON2
Bit
Name
Type
Reset
15
14
13
15
14
13
12
11
10
9
8
7
14
13
12
11
10
9
8
MT
K
15
7
2
1
0
2
1
0
UARTn_XOFF1
6
5
4
3
XOFF1[7:0]
R/W
0
UARTn+001Ch XOFF2
Bit
Name
Type
Reset
UARTn_XON1
UARTn_XON2
UARTn+0018h XOFF1
Bit
Name
Type
Reset
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2
1
0
UARTn_XOFF2
6
5
4
3
XOFF2[7:0]
R/W
0
2
1
0
*Note: XON1, XON2, XOFF1, XOFF2 are valid only when LCR=BFh.
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UARTn_AUTOBAU
D_EN
UARTn+0020h AUTOBAUD_EN
Bit
15
14
13
12
11
Revision 1.0
10
9
8
7
6
5
4
9
8
7
6
5
4
3
2
Name
Type
Reset
UARTn+0024h HIGH SPEED UART
14
13
12
11
10
0
AUTO
_EN
R/W
0
UARTn_HIGHSPEED
3
Re
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15
1
fo
r
AUTOBAUD_EN
Auto-baud enable signal
0 Auto-baud function disable
1 Auto-baud function enable
Bit
Name
Type
Reset
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MT6228 GSM/GPRS Baseband Processor Data Sheet
2
1
0
SPEED [1:0]
R/W
0
SPEED UART sample counter base
0 based on 16*baud_pulse, baud_rate = system clock frequency/16/{DLH, DLL}
1 based on 8*baud_pulse, baud_rate = system clock frequency/8/{DLH, DLL}
2 based on 4*baud_pulse, baud_rate = system clock frequency/4/{DLH, DLL}
3 based on sampe_count * baud_pulse, baud_rate = system clock frequency / sampe_count
The table below shows the divisor needed to generate a given baud rate from CLK inputs of 13M Hz based on different
HIGHSPEED value.
HIGHSPEED = 0 HIGHSPEED = 1 HIGHSPEED = 2
110
7386
14773
29545
300
2708
7386
14773
1200
677
2708
7386
2400
338
677
2708
4800
169
338
677
9600
85
169
338
19200
42
85
169
38400
21
42
85
57600
14
21
42
115200
7
14
21
230400
*
7
14
460800
*
*
7
921600
*
*
*
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BAUD
Table 27 Divisor needed to generate a given baud rate from 13MHz based on different HIGHSPEED value
MT
K
The table below shows the divisor needed to generate a given baud rate from CLK inputs of 26 MHz based on different
HIGHSPEED value.
BAUD
HIGHSPEED = 0 HIGHSPEED = 1 HIGHSPEED = 2
110
14773
29545
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5417
14773
29545
1200
1354
5417
14773
2400
677
1354
5417
4800
339
677
1354
9600
169
339
667
19200
85
169
339
38400
42
85
169
57600
28
42
85
115200
14
28
42
230400
7
14
28
460800
*
7
14
921600
*
*
7
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MT6228 GSM/GPRS Baseband Processor Data Sheet
Table 28 Divisor needed to generate a given baud rate from 26 MHz based on different HIGHSPEED value
The table below shows the divisor needed to generate a given baud rate from CLK inputs of 52MHz based on different
HIGHSPEED value.
BAUD
HIGHSPEED = 0 HIGHSPEED = 1 HIGHSPEED = 2
110
29545
59091
300
10833
29545
1200
2708
10833
2400
1354
2708
4800
677
1354
2708
9600
339
677
1354
19200
169
339
677
38400
85
169
339
57600
56
85
169
115200
28
56
85
230400
14
28
56
460800
7
14
28
921600
*
7
14
118182
59091
29545
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10833
Table 29 Divisor needed to generate a given baud rate from 52 MHz based on different HIGHSPEED value
UARTn_SAMPLE_COUN
T
UARTn+0028h SAMPLE_COUNT
15
14
13
12
11
10
9
8
7
MT
K
Bit
Name
Type
Reset
6
5
4
3
2
SAMPLECOUNT [7:0]
R/W
0
1
0
When HIGHSPEED=3, the sample_count is the threshold value for UART sample counter (sample_num).
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UARTn+002C
SAMPLE_POINT
h
Bit
Name
Type
Reset
15
14
13
12
11
UARTn_SAMPLE_POIN
T
10
9
8
7
6
5
4
3
2
SAMPLEPOINT [7:0]
R/W
ffh
13
12
11
10
9
8
7
6
5
4
BAUD_STAT[3:0]
RO
0
3
2
1
0
BAUDRATE[3:0]
RO
0
Re
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14
0
UARTn_AUTOBAUD_RE
G
UARTn+0030h AUTOBAUD_REG
15
1
fo
r
When HIGHSPEED=3, UART gets the input data when sample_count=sample_num.
e.g. system clock = 13MHz, 921600 = 13000000 / 14
sample_count = 14 and sample point = 7 (sample the central point to decrease the inaccuracy)
Bit
Name
Type
Reset
Revision 1.0
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MT6228 GSM/GPRS Baseband Processor Data Sheet
MT
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BAUD_RATE Autobaud baud rate
0 115200
1 57600
2 38400
3 19200
4 9600
5 4800
6 2400
7 1200
8 300
9 110
BAUDSTAT Autobaud format
0 Autobaud is detecting
1 AT_7N1
2 AT_7O1
3 AT_7E1
4 AT_8N1
5 AT_8O1
6 AT_8E1
7 at_7N1
8 at_7E1
9 at_7O1
10 at_8N1
11 at_8E1
12 at_8O1
13 Autobaud detection fails
UARTn_AUTOBAUDSA
MPLE
UARTn+0038h AUTOBAUDSAMPLE
Bit
Name
Type
15
14
13
12
11
10
9
8
7
6
R/W
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4
3
2
1
AUTOBAUDSAMPLE
R/W R/W R/W R/W R/W
0
R/W
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Reset
Revision 1.0
dh
Since the system clock may change, autobaud sample duration should change as system clock changes.
clock = 13MHz, autobaudsample = 6; when system clock = 26MHz, autobaudsample = 13.
UARTn+003C
Guard time added register
h
15
14
13
12
11
10
9
When system
UARTn_GUARD
8
7
6
5
4
3
Name
GUARD_
Type
Reset
R/W
0
EN
2
1
0
GUARD_CNT[3:0]
fo
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Bit
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MT6228 GSM/GPRS Baseband Processor Data Sheet
R/W
0
R/W
0
R/W
0
R/W
0
UARTn+0040h Escape character register
Bit
Name
Type
Reset
15
14
13
12
11
10
9
Re
lea
se
GUARD_CNT Guard interval count value. Guard interval = (1/(system clock / 16 / div )) * GUARD_CNT.
GUARD_EN
Guard interval add enable signal.
0 No guard interval added.
1 Add guard interval after stop bit.
UARTn_ESCAPE_DAT
8
7
6
5
4
3
2
ESCAPE_DAT[7:0]
R/W
FFh
1
0
ESCAPE_DAT Escape character added before software flow control data and escape character, i.e. if tx data is xon
(31h), with esc_en =1, uart transmits data as esc + CEh (~xon).
UARTn+0044h Escape enable register
15
14
Name
Type
Reset
ESC_EN
0
1
13
12
11
10
9
8
7
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Bit
UARTn_ESCAPE_EN
6
5
4
15
2
1
0
ESC_E
N
R/W
0
Add escape character in transmitter and remove escape character in receiver by UART.
Do not deal with the escape character.
Add escape character in transmitter and remove escape character in receiver.
UARTn+0048h Sleep enable register
Bit
3
14
Name
Type
Reset
13
12
11
10
9
8
7
UARTn_SLEEP_EN
6
5
4
3
2
1
0
SELL
P_EN
R/W
0
MT
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SLEEP_EN For sleep mode issue
0 Do not deal with sleep mode indicate signal
1 To activate hardware flow control or software control according to software initial setting when chip
enters sleep mode. Releasing hardware flow when chip wakes up; but for software control, uart sends
xon when awaken and when FIFO does not reach threshold level.
UARTn+004C
Virtual FIFO enable register
h
Bit
15
14
13
12
11
10
9
8
UARTn_VFIFO_EN
7
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VFIF
O_EN
R/W
0
Name
Type
Reset
4.8
fo
r
VFIFO_EN Virtual FIFO mechanism enable signal.
0 Disable VFIFO mode.
1 Enable VFIFO mode. When virtual mode is enabled, the flow control is based on the DMA threshold,
and generates a timeout interrupt for DMA.
IrDA Framer
4.8.1
General Description
4.8.2
Register Definitions
IRDA+0000h
Bit
Name
Type
Reset
15
BUF
IrDA Framer transmit or receive data.
A write to this register writes into the internal TX FIFO.
A read from this register reads from the internal RX FIFO.
IRDA+0004h
Bit
Name
Type
Reset
15
14
13
12
11
10
9
8
7
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14
TX BUF and RX BUF
Re
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se
IrDA framer is implemented to reduce the CPU loading for IrDA transmissions by performing all the physical level
protocol framing in hardware. From a software perspective, the framer need only prepare and process the raw data for
transmission and reception. Generic DMA is required to move the data between IrDA framer’s internal FIFO and
software-designated memory. The IrDA framer supports IrDA SIR, MIR, and FIR modes of operation. SIR mode
includes operation from 9600bps ~ 115200bps, MIR includes operation at 567000bps or 1152000bps, and FIR mode
includes operation at 4Mbps.
6
5
4
3
BUF[7:0]
R/W
0
TX BUF and RX BUF clear signal
13
12
11
10
9
8
7
BUF
2
1
0
BUF_CLEAR
6
5
4
3
2
1
0
CLEAR
R/W
0
CLEAR SIR mode only. When CLEAR=1, both the TX and RX FIFO are cleared. This is used primarily for debug
purpose. Normal operation does not require this. This control signaled can only be issued under SIR mode.
IRDA+0008h
Bit
Name
Type
Reset
15
14
Maximum Turn Around Time
13
12
11
10
9
8
7
6
MAX_T [13:0]
R/W
3E80h
MAX_T
5
4
3
2
1
0
MT
K
MAX_T The maximum time that a station can hold the P/F bit. This parameter along with the baud rate parameter
dictates the maximum number of bytes that a station can transmit before passing the line to another station by
transmitting a frame with the P/F bit. This parameter is used by one station to indicate the maximum time the
other station can send before it must turn the link around. For baud rates less than 115200 kbps, 500 ms is
the only valid value. The default value is 500 ms.
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IRDA+000Ch
Bit
Name
Type
Reset
15
Revision 1.0
Minimum Turn Around Time
14
13
12
11
10
9
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MT6228 GSM/GPRS Baseband Processor Data Sheet
MIN_T
8
7
MIN_T [15:0]
R/W
FDE8h
6
5
4
3
2
1
0
fo
r
MIN_T Minimum turn around time, the default value is 10 ms. The minimum turn around time parameter deals with
the time needed for a receiver to recover following saturation by transmission from the same device. This
parameter corresponds to the required time delay between the last byte of the last frame sent by a station and
the point at which it is ready to receive the first byte of a frame from another station, i.e. the latency for a
transmit to complete and be ready to receive.
Number of additional BOFs prefixed to the beginning
of a frame
Bit
Name
Type
Reset
15
14
13
12
11
10
9
8
7
TYPE
R/W
0
6
5
4
BOFS
3
2
BOFS [6:0]
R/W
1011b
Re
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IRDA+0010h
1
0
IRDA+0014h
14
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BOFs For SIR mode: the additional BOFs parameter indicates the number of additional flags needed at the beginning
of every frame. The main purpose for the additional BOFs is to provide a delay at the beginning of each frame
for devices with a long interrupt latency.
For MIR mode: This parameter indicates the number of double STA’s to transmit in the beginning. This value
should be set to 0 (for default 2 STA’s) for MIR mode, unless more are required.
For FIR mode: This parameter has no effect.
TYPE SIR mode only. Additional BOFs type.
1 BOF = C0h
0 BOF = FFh
Baud rate divisor
Bit
Name
Type
Reset
15
DIV
Transmit or receive rate divider. Rate = System clock frequency / DIV/ 16. The default value is 55h when
in contention mode. This divisor is also used to determine the RX FIFO timeout threshold.
IRDA+0018h
Bit
Name
Type
Reset
15
14
TX_FRAME_SIZE
Bit
Name
Type
Reset
15
14
12
11
10
9
8
7
DIV[15:0]
R/W
55h
6
5
4
3
13
12
11
10
9
8
7
6
5
4
TX_FRAME_SIZE[11:0]
R/W
40h
2
1
0
TX_FRAME_SIZ
E
Transmit frame size
3
2
1
0
Transmit frame size; the default value is 64 when in contention mode.
RX_FRAME1_SI
ZE
Receiving frame1 size
MT
K
IRDA+001Ch
13
DIV
13
12
11
10
9
8
7
6
5
4
RX_FRAME1_SIZE[11:0]
RO
0
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RX_FRAME1_SIZE Reports the number of byte received.
IRDA+0020h
Bit
15
14
Revision 1.0
Includes only the A+C+I fields.
Transmit abort indication
13
12
11
10
9
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MT6228 GSM/GPRS Baseband Processor Data Sheet
ABORT
8
7
6
5
4
3
2
Name
Type
Reset
1
0
ABO
RT
R/W
0
Bit
15
14
IrDA framer transmit enable signal
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TX_E
MODE
N
R/W R/W R/W
0
0
0
TX_ON TXINVE
E
RT
Name
Type
Reset
R/W
0
IRDA+0028h
15
14
Name
Type
Reset
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TX_EN Transmit enable.
MODE SIR mode only. Modulation type selection.
0 3/16 modulation
1 1.61us
TXINVERT Invert the transmit signal.
0 Transmit signal is not inverted.
1 Transmit signal is inverted.
TX_ONE: Controls the transmit enable signal is one or not.
0 tx_en is not de-asserted until software programs a so.1
automatically after one frame has been sent.
Bit
TX_EN
Re
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IRDA+0024h
fo
r
ABORT SIR mode only. When set 1, the framer transmits an abort sequence and closes the frame without an FCS field
or an ending flag.
Note: Tx abort can be achieved in MIR and FIR by simply disabling the tx_en signal.
tx_en is de-asserted (i.e. transmit disabled)
IrDA framer receive enable signal
13
12
11
10
9
8
7
RX_EN
6
5
4
3
2
1
0
RX_E
N
R/W R/W
0
0
RX_ON RXINVE
E
RT
R/W
0
RX_EN Receive enable.
RXINVERT Invert the receive signal.
0 Receive signal is not inverted.
1 Receive signal is inverted.
RX_ONE Disable receive when get one frame.
0 rx_en is not de-asserted until software programs so.
1 rx_en is de-asserted (i.e. transmit disabled) automatically after one frame has been sent.
FIFO trigger level indication
MT
K
IRDA+002Ch
Bit
Name
Type
Reset
15
14
13
12
11
10
9
8
TRIGGER
7
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6
5
4
3
2
RX_TRIG[
R/W
0
1
0
TX_TRIG
R/W
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MT6228 GSM/GPRS Baseband Processor Data Sheet
Bit
15
14
IRQ enable signal
13
IRQ_ENABLE
12
11
10
9
8
7
6
5
4
3
2
1
0
THRE FIFOTI
MAXTI MINTI RXCO TXCO
2NDR
RXRE
TXABO RXABO
ERRO RXTH TXTH
SHTIM MEOU
MEOU MEOU MPLET MPLET
X_CO
R
RES RES
START
RT
RT
EOUT
T
T
T
E
E
MP
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
0
0
0
0
0
0
0
0
0
0
0
0
Re
lea
se
IRDA+0030h
fo
r
TX_TRIG TX FIFO interrupt trigger threshold. When the amount of data in the TX FIFO is less than the specified
amount, dma req is asserted. (When TX_TRIG = 03, dma req is always asserted as long as FIFO is not full.)
00 0 byte
01 1 byte
02 8 byte
03 16 byte
RX_TRIG RX FIFO interrupt trigger threshold. When the amount of data in RX FIFO is above the specified
amount, dma req is asserted.
00 1 byte
01 2 byte
02 3 byte
Name
Type
Reset
MT
K
Co
nf
id
en
tia
l
TXRES Transmit data reaches the threshold level. (For debug only. Should be set to 0.)
0 No interrupt is generated.
1 Interrupt is generated when transmit FIFO size reaches threshold.
RXRES Receive data reaches the threshold level. (For debug only. Should be set to 0.)
0 No interrupt is generated.
1 Interrupt is generated when receive FIFO size reaches threshold.
ERROR
Error status interrupt enable.
0 No interrupt is generated.
1 Interrupt is generated when one of the error statuses occurs.
TXCOMPLETE Transmit one frame completely.
0 No interrupt is generated.
1 Interrupt is generated when transmitting one frame completely.
RXCOMPLETE Receive one frame completely.
0 No interrupt is generated.
1 Interrupt is generated when receiving one frame completely.
MINTIMEOUT Minimum time timeout.
0 No interrupt is generated.
1 Interrupt is generated when minimum timer is timed out.
MAXTIMEOUT Maximum time timeout.
0 No interrupt is generated.
1 Interrupt is generated when maximum timer is timed out.
RXABORT Receiving aborting frame.
0 No interrupt is generated.
1 Interrupt is generated when receiving aborting frame.
TXABORT SIR mode only. Transmitting aborting frame.
0 No interrupt is generated.
1 Interrupt is generated when transmitting aborting frame.
FIFOTIMEOUT FIFO timeout.
0 No interrupt is generated.
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MT6228 GSM/GPRS Baseband Processor Data Sheet
Bit
15
14
Interrupt Status
13
Name
Type
Reset
IRQ_STA
12
11
10
9
2NDR
THRE FIFOTI
RXRE
X_CO
SHTIM MEOU
START
MP
EOUT
T
RC
RC
RC
RC
0
0
0
0
8
7
6
5
4
3
2
1
0
MAXTI MINTI RXCO TXCO
TXABO RXABO
ERRO RXTR TXTRE
MEOU MEOU MPLET MPLET
RT
RT
R
ES
S
T
T
E
E
RC
0
Re
lea
se
IRDA+0034h
fo
r
1 Interrupt is generated when FIFO timeout.
THRESHTIMEOUT Threshold time timeout.
0 No interrupt is generated.
1 Interrupt is generated when threshold timer is timed out.
RXRESTART SIR mode only. Receiving a new frame before one frame is received completely.
0 No interrupt is generated.
1 Interrupt is generated when receiving a new frame before one frame is received completely.
2NDRX_COMP Receiving second frame and get P/F bit.
0 No interrupt is generated.
1
Interrupt is generated when receiving second frame and get P/F bit completely.
RC
0
RC
0
RC
0
RC
0
RC
0
RC
0
RC
0
RC
0
IRDA+0038h
Bit
Name
Type
Reset
15
14
Co
nf
id
en
tia
l
TXFIFO Transmit FIFO reaches threshold. (For debug only. Not recommended for normal usage.)
RXFIFO
Receive FIFO reaches threshold. (For debug only. Not recommended for normal usage.)
ERROR Generated when any of status in Error Status register occurs.
Once the source of an interrupt is determined to be caused by an error (bit 2), the error status register should
be read. Once read, both the error status register and the interrupt source are read-cleared. If the error
status register indicates either a frame 1 or frame 2 error, the corresponding frame status register should be
read.
TXCOMPLETE Transmitting one frame completely.
RXCOMPLETE Receiving one frame completely.
MINTIMEOUT Minimum turn around time timeout.
MAXTIMEOUT Maximum turn around time timeout.
RXABORT
Receiving aborting frame.
TXABORT
Transmitting aborting frame.
FIFOTIMEOUT FIFO is timeout.
THRESHTIMEOUT Threshold time timeout.
RXRESTART
Receiving a new frame before one frame is received completely.
2NDRX_COMP Receiving second frame and get P/F bit completely.
ERROR STATUS register
13
12
11
10
9
8
7
ERR_STATUS
6
5
4
3
2
1
0
TX FIFO FRAME FRAME
RESER RESER OVER RXSIZ
UNDERR 2 DATA 1 DATA
VED2
VED
RUN
E
UN
ERR
ERR
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
MT
K
RXSIZE
Receive frame size error.
OVERRUN Frame overrun.
RESERVED
Reserved for future use.
RESERVED2 Reserved for future use.
FRAME1 DATA ERR Indicates that an error condition occurred in RX frame1. Must check the RX frame1 status.
FRAME2 DATA ERR Indicates that an error condition occurred in RX frame2. Must check the RX frame2 status.
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TX FIFO UNDERRUN MIR and FIR mode only.
TX FIFO underrun has occurred. Data transmission is aborted.
signal.
Bit
15
Software must reset the tx_en
Transceiver power on/off control. Transceiver mode
select.
IRDA+003Ch
14
13
12
11
10
9
8
7
6
5
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MT6228 GSM/GPRS Baseband Processor Data Sheet
4
TRANSCEIVER
_PDN
3
2
TXCVR
Name
1
0
TX
TRANS_
CONFIG MANUAL
R/W
0
R/W
0
fo
r
Type
Reset
PDN
R/W
0
IRDA+0040h
Bit
Name
Type
Reset
15
Re
lea
se
TRANSCEIVER_PDN
Used for power on/off control for external IrDA transceiver.
TX_MANUAL
When txcvr config is set to 1, this bit can be used to select the operation mode of the external IrDA
transceiver (some transceivers require selection between high speed and low speed operating modes), by
software programming the desired sequence to transmit through the irda_txd pin.
TXCVR CONFIG
Irda_txd comes from core logic.
0
1
Irda_txd depends on tx_manual value.
RX_FRAME_MA
X
Maximum number of receiving frame size
14
13
12
11
10
9
8
7
6
5
4
MAX_RX_FRAME_SIZE_
R/W
0
3
2
1
0
IRDA+0044h
Bit
Name
Type
Reset
15
14
Co
nf
id
en
tia
l
RX_FRAME_MAX Receive frame I field max size, when actual receiving frame size is larger than rx_frame_max,
RXSIZE is asserted. The maximum allowed I field size is 2048.
Threshold Time
13
12
11
10
THRESH_T
9
8
7
6
DISCONNECT_TIME[15:0]
R/W
bb8h
5
4
3
2
1
0
THRESHOLD TIME Threshold time; used to control the time a station waits without receiving a valid frame before
disconnecting the link. Associated with this is the time a station waits without receiving a valid
frame before sending a status indication to the service user layer.
IRDA+0048h
Bit
15
14
Name
Type
Reset
13
IRDA+004Ch
Bit
15
14
12
11
10
9
8
7
6
5
4
3
2
THRESH
_EN
R/W
0
1
0
MIN_E MAX_
N
EN
R/W
0
R/W
0
Counter enable signals.
MT
K
COUNT_ENABLE
COUNT_ENABL
E
Counter enable signal
Indication of system clock rate
13
12
11
10
9
8
CLOCK_RATE
7
Name
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6
5
4
3
2
1
0
CLOCK_RA
TE
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MT6228 GSM/GPRS Baseband Processor Data Sheet
Type
Reset
R/W
0
CLOCK_RATE
SIR mode only Indication of the system clock rate.
0 26 MHz
1 52 MHz
2 13 MHz
Bit
15
14
System Clock Rate Fix
13
12
11
10
9
RATE_FIX
8
7
6
5
4
3
2
1
fo
r
IRDA+0050h
0
CRC
SIR
RATE_
REPOR FRAMI
FIX
T
NG SET
Name
Type
Reset
R/W
0
R/W
0
R/W
0
IRDA+0054h
Bit
15
14
FRAME1_STAT
US
RX Frame1 Status
13
12
11
10
Re
lea
se
RATE_FIX SIR mode only Fix the IrDA framer sample base clock rate as 13 MHz.
0 Clock rate based on clock_rate selection.
1 Clock rate fixed at 13 MHz.
SIR FRAMING SET SIR mode only. Framing error check condition.
0 Ignore the STOP bit of the last byte of a frame.
1 Check the STOP bit of the last byte of a frame.
CRC REPORT When set to 1, CRC error is reported via error status register and error interrupt.
9
8
7
Type
Reset
Co
nf
id
en
tia
l
Name
6
5
FIR
STO
ERR
FIR
4PPM
ERR
R/W
0
R/W
0
4
3
2
1
0
MIR
UNKNO
PF_DET CRC_FAI FRAME_
HDLC W_ERRO
ECT
L
ERROR
ERR
R
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
MT
K
FRAME_ERROR
SIR mode only. Framing error, i.e. STOP bit = 0.
0 No framing error
1 Framing error occurred
CRC_FAIL CRC check fail
2 CRC check successfully
3 CRC check fail
PF_DETECT P/F bit detect
0 Not a P/F bit frame
1 Detected P/F bit in this frame
UNKNOWN_ERROR SIR mode only. Receiving error data, i.e. escape character is followed by a character that is
not an ESC, BOF, or EOF character.
0 Data received correctly.
1 Unknown error occurred.
MIR HDLC ERR
MIR mode only. MIR HDLC encoding error
0 No error
1 Error
FIR 4PPM ERR FIR mode only. FIR 4ppm encoding error
0 No error
1 Error
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FIR STO ERR
FIR mode only. FIR STO sequence error
0 No error
1 Error
Bit
15
14
FRAME2_STAT
US
RX Frame2 Status
13
12
11
10
9
8
7
Name
Type
Reset
6
5
FIR
STO
ERR
FIR
4PPM
ERR
R/W
0
R/W
0
4
3
2
1
0
MIR
UNKNO
PF_DET CRC_FAI FRAME_
HDLC W_ERRO
ECT
L
ERROR
ERR
R
R/W
0
fo
r
IRDA+0058h
Ko
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MT6228 GSM/GPRS Baseband Processor Data Sheet
R/W
0
R/W
0
R/W
0
R/W
0
IRDA+005Ch
Bit
Name
Type
Reset
15
14
Co
nf
id
en
tia
l
Re
lea
se
FRAME_ERROR
SIR mode only. Framing error, i.e. STOP bit = 0
0 No framing error.
1 Framing error occurred.
CRC_FAIL CRC check fail.
0 CRC check successfully.
1 CRC check fail.
PF_DETECT P/F bit detect.
0 Not a P/F bit frame.
1 Detected P/F bit in this frame.
UNKNOWN_ERROR SIR mode only. Receiving error data, i.e. escape character is followed by a character that is
not an ESC, BOF, or EOF character.
0 Data receiving correctly.
1 Unknown error occurred.
MIR HDLC ERR
MIR mode only. MIR HDLC encoding error.
0 No error
1 Error
FIR 4PPM ERR FIR mode only.FIR 4ppm encoding error
0 No error
1 Error
FIR STO ERR
FIR mode only.FIR STO sequence error
0 No error
1 Error
13
12
11
10
9
8
RX_FRAME2_SIZE Reports the number of byte received.
IRDA+0060h
15
14
7
6
5
4
RX_FRAME2_SIZE[11:0]
RO
0
3
13
12
11
10
2
1
0
Includes only the A+C+I fields.
Irda Mode Select
MT
K
Bit
RX_FRAME2_SI
ZE
Receiving frame2 size
IRDA_MODE
9
8
7
6
5
4
3
2
MIR
Name
SPEED
Type
Reset
R/W
0
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0
IRDA MODE
R/W
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MediaTek Inc. Confidential
IRDA MODE
Selects the IrDA operating mode.
or receiving.
00 IR mode
01 MIR mode
10 FIR mode
MIR SPEED
Select the MIR speed.
0 0.576 Mbps
1 1.152 Mbps
Bit
15
14
NOTE: this mode selection cannot be issued while transmitting
Fifo Status
13
12
fo
r
IRDA+0064h
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MT6228 GSM/GPRS Baseband Processor Data Sheet
FIFO_STAT
11
10
9
8
7
6
5
4
3
2
1
0
RX
TX FIFO
RX FIFO
TX FIFO
RX FIFO
FIFO
RD
RD
WR FULL
WR FULL
HOLD
EMPTY
EMPTY
Name
RO
0
RO
0
Re
lea
se
Type
Reset
RO
1
RO
0
RO
1
This register indicates the real time FIFO status, for monitoring purposes.
4.9
Real Time Clock
4.9.1
General Description
4.9.2
Register Definitions
RTC+0000h
Bit
Name
Type
Co
nf
id
en
tia
l
The Real Time Clock (RTC) module provides time and data information. The clock is based on a 32.768KHz
oscillator with an independent power supply. When the mobile handset is powered off, a dedicated regulator supplies
the RTC block. If the main battery is not present, a backup supply such as a small mercury cell battery or a large
capacitor is used. In addition to providing timing data, an alarm interrupt is generated and can be used to power up
the baseband core via the BBWAKEUP pin. Regulator interrupts corresponding to seconds, minutes, hours and days
can be generated whenever the time counter value reaches a maximum value (e.g., 59 for seconds and minutes, 23 for
hours, etc.). The year span is supported up to 2127. The maximum day-of-month values, which depend on the leap
year condition, are stored in the RTC block.
15
14
Baseband power up
13
12
11
10
9
8
7
KEY_BBPU
W
RTC_BBPU
6
5
4
3
2
AUTO BBPU
R/W
R/W
1
0
WRITE_E
PWRE
N
N
R/W
R/W
MT
K
KEY_BBPU
A bus write is acceptable only when KEY_BBPU=0x43.
AUTO Controls if BBWAKEUP is automatically in the low state when SYSRST# transitions from high to low.
0 BBWAKEUP is not automatically in the low state when SYSRST# transitions from high to low.
1 BBWAKEUP is automatically in the low state when SYSRST# transitions from high to low.
BBPU Controls the power of PMIC. If powerkey1=A357h and powerkey2=67D2h, PMIC takes on the value
programmed by software; otherwise PMIC is low.
0 Power down
1 Power on
WRITE_EN When WRITE_EN is set to 0 by the software program, the RTC write interface is disabled until another
system power on.
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PWREN
0
1
RTC alarm has no action on power switch.
When an RTC alarm occurs, BBPU is set to 1, and the system powers on by RTC alarm wakeup.
RTC+0004h
Bit
15
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MT6228 GSM/GPRS Baseband Processor Data Sheet
14
RTC IRQ status
13
12
11
RTC_IRQ_STA
10
9
8
7
6
5
4
3
2
Name
Type
1
0
TCST ALST
A
A
R/C R/C
RTC+0008h
Bit
15
14
RTC IRQ enable
13
12
11
10
9
8
Name WING
Type
R/O
Re
lea
se
fo
r
ALSTA This register indicates the IRQ status and whether or not the alarm condition has been met.
0 No IRQ occurred; the alarm condition has not been met.
1 IRQ occurred; the alarm condition has been met.
TCSTA This register indicates the IRQ status and whether or not the tick condition has been met.
0 No IRQ occurred; the tick condition has not been met.
1 IRQ occurred; the tick condition has been met.
7
6
5
4
3
RTC_IRQ_EN
2
1
0
TC_E AL_E
N
N
R/W R/W R/W
ONESH
OT
RTC+000Ch
Bit
15
Name WING
Type
R/O
14
Co
nf
id
en
tia
l
ONESHOT Controls automatic reset of AL_EN and TC_EN.
AL_EN This register enables the control bit for IRQ generation if the alarm condition has been met.
0 Disable IRQ generation.
1 Enable the alarm time match interrupt. Clear the interrupt when ONESHOT is high upon generation of
the corresponding IRQ.
TC_EN This register enables the control bit for IRQ generation if the tick condition has been met.
0 Disable IRQ generation.
1 Enable the tick time match interrupt. Clear the interrupt when ONESHOT is high upon generation of the
corresponding IRQ.
WING This bit indicates that RTC is still writing to this register.
Counter increment IRQ enable
13
12
11
10
9
8
RTC_CII_EN
7
6
5
4
3
2
1
0
YEAC MTHC DOW DOM HOUC MINCI SECC
II
II
CII
CII
II
I
II
R/W R/W R/W R/W R/W R/W R/W R/W
1/8SEC 1/4SEC 1/2SEC
CII
CII
CII
R/W
R/W
This register activates or de-activates the IRQ generation when the TC counter reaches its maximum value.
MT
K
SECCII Set this bit to 1 to activate the IRQ at each second update.
MINCII Set the bit to 1 to activate the IRQ at each minute update.
HOUCII Set the bit to 1 to activate the IRQ at each hour update.
DOMCII
Set the bit to 1 to activate the IRQ at each day-of-month update.
DOWCII
Set the bit to 1 to activate the IRQ at each day-of-week update.
MTHCII Set the bit to 1 to activate the IRQ at each month update.
YEACII Set the bit to 1 to activate the IRQ at each year update.
1/2SECCII Set the bit to 1 to activate the IRQ at each one-half of a second update.
1/4SECCII Set the bit to 1 to activate the IRQ at each one-fourth of a second update.
1/8SECCII Set the bit to 1 to activate the IRQ at each one-eighth of a second update.
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WING This bit indicates RTC is still writing to this register.
RTC+0010h
Bit
15
14
RTC alarm mask
13
12
11
10
RTC_AL_MASK
9
8
7
6
5
4
3
2
1
0
YEA_M MTH_M DOW_M DOM_M HOU_M MIN_M SEC_M
SK
SK
SK
SK
SK
SK
SK
Name WING
Type
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MT6228 GSM/GPRS Baseband Processor Data Sheet
R/O
R/W
R/W
R/W
R/W
R/W
R/W
R/W
fo
r
The alarm condition for alarm IRQ generation depends on whether or not the corresponding bit in this register is
masked.
RTC+0014h
14
RTC seconds time counter register
13
MT
K
Bit
15
Name WING
Type R/O
Co
nf
id
en
tia
l
Re
lea
se
SEC_MSK
0 Condition (RTC_TC_SEC = RTC_AL_SEC) is checked to generate the alarm signal.
1 Condition (RTC_TC_SEC = RTC_AL_SEC) is masked, i.e. the value of RTC_TC_SEC does not affect
the alarm IRQ generation.
MIN_MSK
0 Condition (RTC_TC_MIN = RTC_AL_MIN) is checked to generate the alarm signal.
1 Condition (RTC_TC_MIN = RTC_AL_MIN) is masked, i.e. the value of RTC_TC_MIN does not affect
the alarm IRQ generation.
HOU_MSK
0 Condition (RTC_TC_HOU = RTC_AL_HOU) is checked to generate the alarm signal.
1 Condition (RTC_TC_HOU = RTC_AL_HOU) is masked, i.e. the value of RTC_TC_HOU does not affect
the alarm IRQ generation.
DOM_MSK
0 Condition (RTC_TC_DOM = RTC_AL_DOM) is checked to generate the alarm signal.
1 Condition (RTC_TC_DOM = RTC_AL_DOM) is masked, i.e. the value of RTC_TC_DOM does not
affect the alarm IRQ generation.
DOW_MSK
0 Condition (RTC_TC_DOW = RTC_AL_DOW) is checked to generate the alarm signal.
1 Condition (RTC_TC_DOW = RTC_AL_DOW) is masked, i.e. the value of RTC_TC_DOW does not
affect the alarm IRQ generation.
MTH_MSK
0 Condition (RTC_TC_MTH = RTC_AL_MTH) is checked to generate the alarm signal.
1 Condition (RTC_TC_MTH = RTC_AL_MTH) is masked, i.e. the value of RTC_TC_MTH does not affect
the alarm IRQ generation.
YEA_MSK
0 Condition (RTC_TC_YEA = RTC_AL_YEA) is checked to generate the alarm signal.
1 Condition (RTC_TC_YEA = RTC_AL_YEA) is masked, i.e. the value of RTC_TC_YEA does
not affect the alarm IRQ generation.
WING This bit indicates RTC is still writing to this register.
12
11
10
9
8
TC_SECOND The second initial value for the time counter.
WING This bit indicates RTC is still writing to this register.
RTC+0018h
Bit
15
14
7
RTC_TC_SEC
6
5
4
3
2
TC_SECOND
R/W
12
11
10
9
8
0
The range of its value is: 0-59.
RTC minutes time counter register
13
1
7
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RTC_TC_MIN
6
5
4
3
2
1
0
MediaTek Inc. Confidential
Name WING
Type R/O
TC_MINUTE
R/W
TC_MINUTE The minute initial value for the time counter.
WING This bit indicates RTC is still writing to this register.
14
The range of its value is: 0-59.
RTC hours time counter register
13
12
11
10
9
8
RTC_TC_HOU
7
6
5
4
TC_HOUR The hour initial value for the time counter. The range of its value is: 0-23.
WING This bit indicates RTC is still writing to this register.
Bit
15
Name WING
Type R/O
14
RTC day-of-month time counter register
13
12
11
10
9
8
TC_DOM
7
6
2
1
TC_HOUR
R/W
0
RTC_TC_DOM
5
4
3
2
1
TC_DOM
R/W
Re
lea
se
RTC+0x0020
3
fo
r
RTC+001Ch
Bit
15
Name WING
Type R/O
Revision 1.0
Ko
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MT6228 GSM/GPRS Baseband Processor Data Sheet
0
The day-of-month initial value for the time counter. The day-of-month maximum value depends on the
leap year condition, i.e. 2 LSB of year time counter are zeros.
WING This bit indicates RTC is still writing to this register.
RTC+0x0024
Bit
15
Name WING
Type R/O
14
RTC day-of-week time counter register
13
12
11
10
9
8
7
RTC+0x0028
Bit
15
Name WING
Type R/O
14
5
4
3
RTC month time counter register
13
12
11
10
9
8
TC_MONTH
The month initial value for the time counter.
WING This bit indicates RTC is still writing to this register.
7
14
13
12
11
10
9
8
1
0
TC_DOW
R/W
RTC_TC_MTH
6
5
4
3
2
1
TC_MONTH
R/W
0
The range of its value is: 1-12.
RTC+0x002C RTC year time counter register
Bit
15
Name WING
Type R/O
2
The range of its value is: 1-7.
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TC_DOW
The day-of-week initial value for the time counter.
WING This bit indicates RTC is still writing to this register.
6
RTC_TC_DOW
7
RTC_TC_YEA
6
5
4
3
2
AL_SECOND
R/W
1
0
TC_YEAR
The year initial value for the time counter. The range of its value is: 0-127. (2000-2127)
WING This bit indicates RTC is still writing to this register.
RTC+0x0030
14
13
12
11
10
9
8
7
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Bit
15
Name WING
Type R/O
RTC second alarm setting register
AL_SECOND The second value of the alarm counter setting.
WING This bit indicates RTC is still writing to this register.
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RTC_AL_SEC
6
5
4
3
2
AL_SECOND
R/W
1
0
The range of its value is: 0-59.
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Bit
15
Name WING
Type R/O
14
RTC minute alarm setting register
13
12
11
10
9
8
7
AL_MINUTE The minute value of the alarm counter setting.
WING This bit indicates RTC is still writing to this register.
RTC+0x0038
Bit
15
Name WING
Type R/O
14
RTC_AL_MIN
6
5
4
3
2
AL_MINUTE
R/W
The range of its value is: 0-59.
RTC hour alarm setting register
13
12
11
10
9
8
1
0
RTC_AL_HOU
7
6
5
4
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RTC+0x0034
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3
2
1
AL_HOUR
R/W
0
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AL_HOUR
The hour value of the alarm counter setting. The range of its value is: 0-23.
WING This bit indicates RTC is still writing to this register.
RTC+0x003C RTC day-of-month alarm setting register
Bit
15
Name WING
Type R/O
14
13
12
11
10
9
8
AL_DOM
7
6
5
4
3
RTC_AL_DOM
2
1
AL_DOM
R/W
0
The day-of-month value of the alarm counter setting. The day-of-month maximum value depends on
the leap year condition, i.e. 2 LSB of year time counter are zeros.
WING This bit indicates RTC is still writing to this register.
Bit
15
Name WING
Type R/O
14
RTC day-of-week alarm setting register
13
12
11
10
9
8
7
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RTC+0x0040
AL_DOW
The day-of-week value of the alarm counter setting.
WING This bit indicates RTC is still writing to this register.
RTC+0x0044
Bit
15
Name WING
Type R/O
14
Bit
15
Name WING
Type R/O
14
5
4
3
13
12
11
10
9
8
7
12
11
10
9
8
MT
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AL_YEAR
The year value of the alarm counter setting.
WING This bit indicates RTC is still writing to this register.
6
5
4
3
14
13
12
11
10
9
8
2
1
AL_MONTH
R/W
0
The range of its value is: 1-12.
7
RTC_AL_YEA
6
5
4
3
2
AL_YEAR
R/W
1
0
The range of its value is: 0-127. (2000-2127)
RTC_XOSCCAL
I
RTC+0x004C XOSC bias current control register
Bit
15
Name WING
Type R/O
1
0
AL_DOW
R/W
RTC_AL_MTH
RTC year alarm setting register
13
2
The range of its value is: 1-7.
RTC month alarm setting register
AL_MONTH
The month value of the alarm counter setting.
WING This bit indicates RTC is still writing to this register.
RTC+0x0048
6
RTC_AL_DOW
7
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3
2
1
XOSCCALI
WO
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XOSCCALI
This register controls the XOSC32 bias current.
XOSCCALI value is 11111b.
WING This bit indicates RTC is still writing to this register.
Bit
Name
Type
15
14
13
12
11
10
9
8
7
6
RTC_POWERKEY1
R/W
5
4
13
12
11
10
2
1
0
RTC_POWERK
EY2
RTC_POWERKEY2 register
14
3
9
8
7
6
RTC_POWERKEY2
R/W
5
4
3
2
1
0
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15
RTC_POWERK
EY1
RTC_POWERKEY1 register
RTC+0054h
Bit
Name
Type
Before the first program by software, the
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RTC+0050h
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MT6228 GSM/GPRS Baseband Processor Data Sheet
These register sets are used to determine if the real time clock has been programmed by software; i.e. the time value in
real time clock is correct. When the real time clock is first powered on, the register contents are all undefined,
therefore the time values shown are incorrect. Software needs to know if the real time clock has been programmed.
Hence, these two registers are defined to solve this power-on issue. After software programs the correct value, these
two register sets do not need to be updated. In addition to programming the correct time value, when the contents of
these register sets are wrong, the interrupt is not generated. Therefore, the real time clock does not generate the
interrupts before the software programs the registers; unwanted interrupt due to wrong time value do not occur. The
correct values of these two register sets are:
RTC+0058h
Bit
15
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RTC_POWERKEY1 A357h
RTC_POWERKEY2 67D2h
14
DBIN
Name WING
G
Type R/O R/O
PDN1
13
12
11
10
9
8
7
RTC_PDN1
6
5
4
3
2
1
0
RTC_PDN1[7:0]
R/W
MT
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RTC_PDN1[3:1] is for reset de-bounce mechanism.
0
4ms
1
16ms
2
64ms
3
256ms
4
512ms
5
1024ms
6
2048ms
7
4096ms
RTC_PDN1[7:4] & RTC_PDN1[0] is the spare register for software to keep power on and power off state
information.
DBING This bit indicates RTC is still de-bouncing.
WING This bit indicates RTC is still writing to this register.
RTC+005Ch
Bit
15
14
PDN2
13
RTC_PDN2
12
11
10
9
8
7
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Name WING
Type R/O
RTC_PDN2[7:0]
R/W
RTC_PDN2 The spare register for software to keep power on and power off state information.
WING This bit indicates RTC is still writing to this register.
RTC+0060h
Bit
15
14
RTC writing completed flag
13
12
11
10
9
RTC_WOK
8
7
6
5
4
3
Type
Auxiliary ADC Unit
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WING1 This bit indicates RTC is still writing POWERKEY1.
WING2 This bit indicates RTC is still writing POWERKEY2.
WING3
This bit indicates RTC is still writing BBPU.
2
1
0
WING WING WING
3
2
1
R/O R/O R/O
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MT6228 GSM/GPRS Baseband Processor Data Sheet
The auxiliary ADC unit is used to monitor the status of the battery and charger, to identify the plugged peripheral, and
to perform temperature measurement. Seven input channels allow diverse applications in this unit.
Each channel can operate in one of two modes: immediate mode and timer-triggered mode. The mode of each
channel can be individually selected through register AUXADC_CON0. For example, if the flag SYN0 in the register
AUXADC_CON0 is set, the channel 0 is set in timer-triggered mode. Otherwise, the channel operates in immediate
mode.
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In immediate mode, the A/D converter samples the value once only when the flag in the AUXADC_CON1 register has
been set. For example, if the flag IMM0 in AUXADC_CON1 is set, the A/D converter samples the data for channel 0.
The IMM flags must be cleared and set again to initialize another sampling.
The value sampled for channel 0 is stored in register AUXADC_DAT0, the value for channel 1 is stored in register
AUXADC_DAT1, etc.
If the AUTOSET flag in the register AUXADC_CON3 is set, the auto-sample function is enabled. The A/D converter
samples the data for the channel in which the corresponding data register has been read. For example, in the case
where the SYN1 flag is not set, the AUTOSET flag is set, when the data register AUXADC_DAT0 has been read, the
A/D converter samples the next value for channel 1 immediately.
If multiple channels are selected at the same time, the task is performed sequentially on every selected channel. For
example, if AUXADC_CON1 is set to 0x7f, that is, all 7 channels are selected, the state machine in the unit starts
sampling from channel 6 to channel 0, and saves the values of each input channel in the respective registers. The
same process also applies in timer-triggered mode.
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In timer-triggered mode, the A/D converter samples the value for the channels in which the corresponding SYN flags
are set when the TDMA timer counts to the value specified in the register TDMA_AUXEV1, which is placed in the
TDMA timer. For example, if AUXADC_CON0 is set to 0x7f, all 7 channels are selected to be in timer-triggered
mode. The state machine samples all 7 channels sequentially and save the values in registers from AUXADC_DAT0
to AUXADC_DAT6, as it does in immediate mode.
There is a dedicated timer-triggered scheme for channel 0. This scheme is enabled by setting the SYN7 flag in the
register AUXADC_CON2. The timing offset for this event is stored in the register TDMA_AUXEV0 in the TDMA
timer. The sampled data triggered by this specific event is stored in the register AUXADC_DAT7. It is used to
separate the results of two individual software routines that perform actions on the auxiliary ADC unit.
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The AUTOCLRn in the register AUXADC_CON3 is set when it is intended to sample only once after setting
timer-triggered mode. If AUTOCLR1 flag has been set, after the data for the channels in timer-triggered mode has
been stored, the SYNn flags in the register AUXADC_CON0 are cleared. If AUTOCLR0 flag has been set, after the
data for the channel 0 has been stored in the register AUXADC_DAT7, the SYN7 flag in the register AUXADC_CON2
is cleared.
The usage of the immediate mode and timer-triggered mode are mutually exclusive in terms of individual channels.
4.10.1
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The PUWAIT_EN bit in the registers AUXADC_CON3 is used to power up the analog port in advance. This ensures
that the power has ramped up to the stable state before A/D converter starts the conversion. The analog part is
automatically powered down after the conversion is completed.
Register Definitions
AUXADC+000
Auxiliary ADC control register 0
0h
15
14
13
12
11
10
9
8
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Bit
Name
Type
Reset
AUXADC_CON0
7
6
5
4
3
2
1
0
SYN6 SYN5 SYN4 SYN3 SYN2 SYN1 SYN0
R/W R/W R/W R/W R/W R/W R/W
0
0
0
0
0
0
0
SYNn These 7 bits define whether the corresponding channel is sampled or not in timer-triggered mode. It is
associated with timing offset register TDMA_AUXEV1. It supports multiple flags. The flags can be
automatically cleared after those channel have been sampled if AUTOCLR1 in the register AUXADC_CON3
is set.
0 The channel is not selected.
1 The channel is selected.
14
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AUXADC+000
Auxiliary ADC control register 1
4h
13
12
11
10
9
8
7
AUXADC_CON1
Bit
Name
Type
Reset
15
6
5
4
3
2
1
0
IMM6 IMM5 IMM4 IMM3 IMM2 IMM1 IMM0
R/W R/W R/W R/W R/W R/W R/W
0
0
0
0
0
0
0
IMMn
These 7 bits are set individually to sample the data for the corresponding channel.
0 The channel is not selected.
1 The channel is selected.
It supports multiple flags.
AUXADC+000
Auxiliary ADC control register 2
8h
Bit
Name
Type
Reset
15
14
13
12
11
10
9
8
7
AUXADC_CON2
6
5
4
3
2
1
0
SYN7
R/W
0
MT
K
SYN7 This bit is used only for channel 0 and is to be associated with timing offset register TDMA_AUXEV0 in the
TDMA timer in timer-triggered mode. The flag can be automatically cleared after channel 0 has been
sampled if AUTOCLR0 in the register AUXADC_CON3 is set.
0 The channel is not selected.
1 The channel is selected.
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AUXADC+000
Auxiliary ADC control register 3
Ch
Bit
15
Name
AUTO
SET
14
13
12
Type R/W
Reset
0
11
PUW
AIT_E
N
R/W
0
10
9
8
7
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AUXADC_CON3
6
5
4
3
2
AUTO AUTO
CLR1 CLR0
R/W
0
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1
0
STA
R/W
0
RO
0
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AUTOSET This field defines the auto-sample mode of the module. In auto-sample mode, each channel with its
sample register being read can start sampling immediately without configuring the control register
AUXADC_CON1 again.
PUWAIT_EN Thus field enables the power warm-up period to ensure power stability before the SAR process takes
place. It is recommended to activate this field.
0 The mode is not enabled.
1 The mode is enabled.
AUTOCLR1
The field defines the auto-clear mode of the module for event 1. In auto-clear mode, each
timer-triggered channel gets samples of the specified channels once the SYNn bit in the register
AUXADC_CON0 has been set. The SYNn bits are automatically cleared and the channel is not enabled
again by the timer event except when the SYNn flags are set again.
0 The automatic clear mode is not enabled.
1 The automatic clear mode is enabled.
AUTOCLR0
The field defines the auto-clear mode of the module for event 0. In auto-clear mode, the
timer-triggered channel 0 gets the sample once the SYN7 bit in the register AUXADC_CON2 has been set.
The SYN7 bit is automatically cleared and the channel is not enabled again by the timer event 0 except when
the SYN7 flag is set again.
0 The automatic clear mode is not enabled.
1 The automatic clear mode is enabled.
STA
The field defines the state of the module.
0 This module is idle.
1 This module is busy.
AUXADC+001
Auxiliary ADC channel 0 register
0h
Bit
Name
Type
Reset
15
14
13
12
11
10
9
8
7
AUXADC_DAT0
6
5
4
3
2
1
0
DAT
RO
0
The register stores the sampled data for the channel 0. There are 8 registers of the same type for the corresponding
channel . The overall register definition is listed in Table 30.
Register Function
Acronym
AUXADC+0010h
Auxiliary ADC channel 0 data register
AUXADC_DAT0
AUXADC+0014h
Auxiliary ADC channel 1 data register
AUXADC_DAT1
AUXADC+0018h
Auxiliary ADC channel 2 data register
AUXADC_DAT2
AUXADC+001Ch
Auxiliary ADC channel 3 data register
AUXADC_DAT3
AUXADC+0020h
Auxiliary ADC channel 4 data register
AUXADC_DAT4
AUXADC+0024h
Auxiliary ADC channel 5 data register
AUXADC_DAT5
MT
K
Register Address
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AUXADC+0028h
Auxiliary ADC channel 6 data register
AUXADC_DAT6
AUXADC+002Ch
Auxiliary ADC channel 0 data register for TDMA event 0
AUXADC_DAT7
Table 30 Auxiliary ADC data register list
4.11
SCCB
General Description
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4.11.1
SCCB (Serial Camera Control Bus) is a two-wire serial interface for camera control usage. The two signals are
SIO_CK and SIO_DAT. SIO_CK is a single-direction, active-high clock signal that must be driven by the master.
SIO_DAT is a bi-directional data signal that can be driven by either the master or the slave.
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Within the transmission, two situations are defined as the START and STOP conditions. A HIGH to LOW transition
on the SIO_DAT line while SIO_CK is high indicates a START condition. A LOW to HIGH transition on the
SIO_DAT line while SIO_CK is high indicates a STOP condition. The master generates START and STOP conditions
when it initiates or terminates a transmission.
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For SCCB, there are 3 kinds of transmissions: 3-phase write transmission, 2-phase write transmission, and 2-phase read
transmission cycle. A phase contains 9 bits: an 8-bit sequential data transmission followed by a 9th bit. The 9th bit is
a Do not-Care bit or an NA bit, depending on whether the transmission is a write or read phase. The 3-phase write
transmission cycle is a full write cycle and the master can write one byte of data to a specific slave. The content of a
3-phase write transmission cycle is displayed in Figure 50. The ID address indicates the specific slave that the master
wants to access. The sub address is the location of the destination register. The purpose of a 2-phase write
transmission cycle is to identify the sub-address of the specific slave the master intends to access; it is always followed
by a 2-phase read transmission cycle, which has no ability to identify the sub-address. The structure of 2-phase write
transmission cycle and 2-phase read transmission cycle are depicted in Figure 51 and Figure 52, respectively.
ID Address
Sub-address
Write Data
Figure 50 SCCB 3-phase write transmission cycle
ID Address
Sub-address
Phase 1
Phase 2
Figure 51 SCCB 2-phase write transmission cycle
ID Address
Read Data
Phase 1
Phase 2
MT
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Figure 52 SCCB 2-phase read transmission cycle
4.11.2
Register Definitions
SCCB+0000h SCCB Control Register
Bit
15
14
13
12
11
10
9
CTRL
8
7
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SCCB
_EN
R/W
0
Name
Type
Reset
SCCB_EN This bit is used to enable SCCB. The bit must be accessed when SCCB wants to communicate with the
slave, i.e. generates write or read transmission cycles.
SCCB+0008h SCCB Data Length Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
DAT_LEN
R/W
0
0
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Bit
Name
Type
Reset
DAT_LEN
SCCB+000Ch SCCB Buffer Time Register
Bit
Name
Type
Reset
15
14
13
12
11
10
9
8
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DAT_LEN This field indicates the transmission length minus 1, i.e. to set DAT_LEN = 1 for 2-phase transmission
and to sets DAT_LEN = 2 for 3-phase transmission.
7
6
5
4
TBUF
3
2
TBUF
R/W
3Eh
1
0
TBUF For SCCB, the master initiates transmission with a START condition, and ends the transmission by sending a
STOP condition. TBUF indicates the bus free time between a STOP and START condition, i.e. the interval
of the STOP and START conditions. Based on a 13 MHz clock frequency, the SCCB buffer time = (TBUF /
13000000), and the default setting is ~4.7us.
SCCB+0010h SCCB Start Hold Time
15
14
13
12
11
10
9
8
7
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Bit
Name
Type
Reset
6
5
4
THDSTA
3
2
THDSTA
R/W
34h
1
0
THDSTA START condition occurs when there is a HIGH to LOW transition on the SIO_DAT line while SIO_CK is
HIGH. The START hold time indicates that SIO_CK should be HIGH at least THDSTA length of time after
SIO_DAT becomes LOW. Based on a 13 MHz frequency, the SCCB start hold time = (THDSTA /
13000000), and the default setting is ~4us.
SCCB+0014h SCCB Data Hold Time
Bit
Name
Type
Reset
15
14
13
12
11
10
9
8
7
THDDAT
6
5
4
3
2
THDDAT
R/W
27h
1
0
THDDAT Since SCCB data can be changed only when SIO_CK is LOW, a data hold time is defined to indicate the
time interval that data cannot be changed after SIO_CK becomes LOW. Based on 13 MHz frequency, SCCB
data hold time = (THDDAT / 13000000), and the default setting is ~3us.
MT
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SCCB+0018h SCCB TLOW
Bit
Name
Type
Reset
15
14
13
12
11
TLOW
10
9
8
7
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R/W
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TLOW This field indicates the low period of serial clock. Combined with THIGH, the SIO_CK duty is adjustable.
Based on a 13MHz frequency, the SIO_CK low period = (TLOW / 13000000), and the default setting is
~5.3us.
SCCB+001Ch SCCB THIGH
15
14
13
12
11
THIGH
10
9
8
7
6
5
4
3
THIGH
R/W
3Ch
2
1
0
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Bit
Name
Type
Reset
THIGH This field indicates the high period of serial clock. Combined with TLOW, the SIO_CK duty is adjustable.
Based on a 13 MHz frequency, the SIO_CK high period = (THIGH / 13000000), and the default setting is
~4.6us.
SCCB+0020h SCCB Data Register
15
14
13
12
11
10
DATA
9
8
7
6
5
4
DATA
R/W
0
3
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Bit
Name
Type
Reset
2
1
0
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DATA SCCB write data. DATA[8] indicates whether or not the following 8bits is an ID address. If the word is an
ID address, the write or read information is hidden in DATA[0].
DATA[8] 0 The following 8-bits is a sub address or pure data.
1 The following 8-bits is an ID address field.
DATA[0]
0 When DATA [8] = 1, the data is an ID address.
DATA [0] = 0, a write cycle
DATA [0] = 1, a read cycle
1 When DATA [8] = 0, the data is not an ID address; it may be a sub address or pure data.
SCCB+0028h SCCB STOP Setup Time
Bit
Name
Type
Reset
15
14
13
12
11
10
9
8
7
TSUSTO
6
5
4
3
2
TSUSTO
R/W
34h
1
0
TSUSTO A LOW to HIGH transition on the SIO_DAT line while SIO_CK is high indicates a STOP condition.
For a STOP condition, the LOW to HIGH transition on the SIO_DAT can be generated after SCCB STOP
setup time while SIO_CK must be HIGH. Based on a 13 MHz frequency, SCCB STOP setup time =
(TSUSTOP / 13000000), and the default setting is ~4us.
SCCB+0038h SCCB MODE
Bit
15
14
Name
Type
Reset
13
12
11
10
9
8
7
MODE
6
5
4
3
2
1
0
MOD
E
R/W
0
MT
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MODE This bit indicates the SCCB operating mode
0 To operate as Slave
1 To operate as Master
SCCB+003Ch SCCB Buf Clear
Bit
15
14
13
12
11
BUF_CLEAR
10
9
8
7
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BUF_
CLEA
R
R/W
0
Name
Type
Reset
SCCB+0040h SCCB Status Register
Bit
15
14
13
12
11
10
9
8
7
6
5
Name
READ Indicates the read is complete.
0 Read command is not finished.
1 Read command is finished.
WRITE Indicates the write is complete.
0 Write command is not finished.
1 Write command is finished.
SCCB+0044h SCCB Read Data Register
15
14
READ_DATA
13
12
11
10
9
8
7
6
5
4
3
READ_DATA
RO
0
2
STA
1
0
WRIT
READ
E
R/W R/W
0
0
READ_DATA
2
1
0
The returned read data from slave.
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Bit
Name
Type
Reset
3
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Type
Reset
4
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BUF_CLEAR Buffer clear bit. Set this bit to clear the SCCB FIFO.
0 Buffer is not cleared.
1 Clear the buffer.
4.12
Cipher Hash Engine
4.12.1
General Description
The Cipher and Hash Engine (CHE) and Secure Booting module is responsible for security functions in the MT6228
that are essential for applications such as M-Payment, WAP, WIM, banking communication, and Digital Rights
Management. The hardware support allows for lower complexity and higher efficiency. The architecture is based on
Direct Memory Access (DMA) without a word-alignment constraint, increasing its flexibility for users.
MT
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For the cipher and decipher functions, CHE supports Advanced Encryption Standard (AES), Data Encryption Standard
(DES), and Triple-DES (Figure 53). These standards are used for both Electronic Codebook mode (Figure 54) and
Cipher Block Chaining mode (Figure 55). The cipher and decipher functions are symmetric functions: the same key
is used for both encryption and decryption. They are block-based algorithms: AES operates on a block size of 16
bytes and 3DES/DES on a block size of 8 bytes. The lengths of the cipher text and the plain text are typically the
same if the original length is a multiple of the block size. CHE supports all AES key lengths: 128, 192, 256 bits.
Under certain conditions, the decoding speed can be comparable to encoding speed. Write-only key registers are
given higher security level for use. The user can keep the cipher-text of raw keys and discard original keys to prevent
peepers.
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Figure 53 3DES Function
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Figure 54 ECB Mode
Figure 55 CBC Mode
For the hash function, CHE supports both Message Digest 5 (MD5 in RFC 1321) and US Secure Hash Algorithm 1
(SHA-1 in RFC 3174). The hash function is a one-way function: a message is converted into a fixed-length string of
digits. MD5 is a 128-bit message digest, and SHA-1 is 160-bit. They are very similar functions such that resources
sharing can be applied in CHE.
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A new Save and Resume feature is implemented in CHE. Because only one task can be applied on CHE at any given
time, unfinished jobs can be saved to the assigned memory addresses until the source data is ready again.
Register Definitions
Register Address
Register Function
Acronym
CHE start register
CHE_START
CHE control register
CHE_CON
CHE + 0008h
CHE key0/key4/initial vector 0/source memory address
CHE_IN0
CHE + 000ch
CHE key1/key5/initial vector 1/destination memory address CHE_IN1
CHE + 0010h
CHE key2/key6/initial vector 2/data length
CHE_IN2
CHE + 0014h
CHE key3/key7/initial vector 3/state memory address
CHE_IN3
CHE + 0018h
CHE slow down rate
CHE_SDRAT
CHE + 001ch
CHE pad count
CHE_PCNT
CHE + 0020h
CHE status
CHE_STAT
CHE + 0024h
CHE current destination address
CHE_CDES
CHE + 0028h
CHE interrupt status
CHE_INTSTA
CHE + 002ch
CHE interrupt enable
CHE_INTEN
CHE + 00c0h
CHE Secure Booting control
CHE_BCON
MT
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CHE + 0000h
CHE + 0004h
CHE + 00c4h
CHE Secure Booting source data
CHE_BSRC
CHE + 00c8h
CHE Secure Booting seed data
CHE_BSEED
CHE + 00cch
CHE Secure Booting encrypted data
CHE_BENC
CHE + 00d0h
CHE Secure Booting decrypted data
CHE_BDEC
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Table 31 CHE Registers
CHE+0000h
Bit
Name
Type
Reset
15
CHE start register
14
13
12
11
10
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CHE_START
9
8
7
6
5
4
3
2
1
0
UPIV2 UPIV0
UPDE CLEA
RKEY WKEY
RSTAT WSTAT LAST ST/UD
UPK67 UPK45 UPK23 UPK01
3
1
S
R
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
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Start register for CHE.
MT
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ST/UD This bit means Start (1) / !Update (0).
When the ST/UD bit is asserted, CHE enters NORMAL mode and performs the job pre-defined according to
the bit settings of LAST, WSTAT, RSTAT, UPDES, WKEY, RKEY and register CHE_CON. This bit must be
de-asserted after the current operation finished. Note: CHE only starts when the CHE_CON control
register ATYPE is 111 (Reserved); otherwise, CHE ends immediately and returns an error.
When ST/UD is de-asserted, CHE enters UPDATE mode. It depends on the UPIV01, UPIV23, UPK01,
UPK23, UPK45 and UPK67 to update the corresponding Initial Vectors (IV0~3) and cipher or decipher keys
0~7 in symmetric ciphering or deciphering mode. It’s suggested that writing 0x0000 into START immediately
before other operations.
LAST This bit indicates the last section for this process. If this bit is asserted, CHE finishes the current process and
resets to the initial state.
In ciphering mode, CHE outputs the last result (including padding process operation).
In deciphering mode, CHE outputs the last result and updates CHE_PCNT.
In hashing mode, CHE pads and outputs the digest.
WSTAT Write CHE states after this operation completed. CHE needs 120 bytes of space for each state to write to
address CHE_SADDR (CHE_IN3). The state can be read back by asserting RSTAT.
RSTAT Read states before the start of the operation. CHE reads 120 bytes back from address CHE_SADDR
(CHE_IN3). The states can be written beforehand by asserting WSTAT.
CLEAR Reset all states and return to the initial state. To perform a clear operation, write 0x0010 to CHE_START,
then write 0x0000 to CHE_START immediately (in the next instruction cycle) to return to the idle mode.
The clear operation has the highest priority of all. If this operation starts with RSTAT disabled, the
user is recommended to clear CHE. The user is highly recommended to clear CHE if this operation
starts without RSTAT enabled.
UPDES Force an update for CHE_DES (CHE_IN1). CHE automatically updates CHE_DES under two conditions
only: the first operation after a reset or a last operation. The user can force CHE to update the destination
address by asserting UPDES. When this bit is enabled, CHE does not update the destination address when
RSTAT is enabled.
WKEY Write key values into encrypted form. To encrypt the key after writing CHE_KEY0~ 7 (CHE_IN0~3), write
0x0041 to CHE_START. Wait for the OK state before writing 0x0000 to CHE_START to return to idle
mode. The keys are stored in encrypted form; the user cannot recover the plain text key, only restore the
encrypted key to CHE by asserting RKEY.
This operation needs 36 bytes of buffer space and uses SADDR as a target address. The WKEY process does
not affect the contents of the KEY registers in CHE. WKEY and RKEY override the NORMAL mode
operation for CHE; WKEY has higher priority than RKEY.
RKEY Restore the key values back to CHE. To retrieve a previously stored key (36 bytes), write 0x0081 to
CHE_START. Wait for the OK state before writing 0x0000 to CHE_START to return to the idle mode.
The keys can be stored by asserting WKEY.
UPIV01 Update CHE_IV0 from CHE_IN0 and CHE_IV1 from CHE_IN1 in UPDATE mode.
UPIV23 Update CHE_IV2 from CHE_IN2 and CHE_IV3 from CHE_IN3 in UPDATE mode.
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UPK01
UPK23
UPK45
UPK67
Update CHE_KEY0&1 from CHE_IN0 and CHE_IV1 in UPDATE mode.
Update CHE_KEY2&3 from CHE_IN2 and CHE_IV3 in UPDATE mode.
Update CHE_KEY4&5 from CHE_IN0 and CHE_IV1 in UPDATE mode.
Update CHE_KEY6&7 from CHE_IN2 and CHE_IV3 in UPDATE mode.
CHE+0004h
Bit
Revision 1.0
15
14
CHE control register
13
12
11
10
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CHE_CON
9
8
7
6
5
Name
2
1
0
ATYPE
R/W
000
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Type
Reset
4
3
SMOD CIPH
E
ER
R/W R/W
0
0
Control register for CHE.
CHE+0008h
Bit
Name
Type
Reset
Bit
Name
Type
Reset
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ATYPE Cipher Hash algorithm type: 000=MD5, 001=SHA-1, 010=DES, 011=3-DES, 100=AES-128, 101=AES-192,
110=AES-256. 111=Reserved.
CIPHER
0=Decipher mode, 1=Cipher mode.
SMODE
0=ECB mode, 1=CBC mode. For CBC mode, load the initialization vectors (IV) beforehand.
CHE key0/key4/initial vector 0/source address
31
30
29
28
27
26
25
15
14
13
12
11
10
9
IN0
24
23
IN0[31:16]
R/W
0
8
7
IN0[15:0]
R/W
0
CHE_IN0
22
21
20
19
18
17
16
6
5
4
3
2
1
0
CHE+000ch
31
30
15
14
CHE key1/key5/initial vector 1/destination address
29
28
27
26
25
13
12
11
10
9
MT
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Bit
Name
Type
Reset
Bit
Name
Type
Reset
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Temporary buffer to load the CHE internal registers: KEY0, KEY4, IV0 and SRC. Which registers are loaded
depends on CHE_START: in UPDATE mode, KEY0, KEY4, IV0 are loaded; in NORMAL mode, SRC is
loaded.
KEY0 When CHE is in UPDATE mode and the UPK01 bit is enabled, the content of IN0 is copied into the internal
KEY0 registers. CHE stores 8 KEYs, KEY0~KEY7. Different algorithms use different KEYs. AES-128:
[0,1,2,3]; AES-192: [0,1,2,3,4,5]; AES-256: [0,1,2,3,4,5,6,7]; DES: [0,1]; 3-DES encryption:
[0,1] [2,3] [4,5]; and 3-DES decryption: [4,5] [2,3] [0,1].
KEY4 When CHE is in UPDATE mode and UPK45 is enabled, the content of IN0 is copied into the internal KEY4
registers.
IV0
When CHE is in UPDATE mode and UPIV01 is enabled, the content of IN0 is copied into the internal IV0
registers. DES/3DES uses a 64-bit initial vector [IV0,IV1] in CBC mode. AES uses a 128-bit initial vector
[IV0,IV1,IV2,IV3] in CBC mode.
SRC When CHE is in NORMAL mode, the content of IN0 is copied into internal SRC registers. SRC is the source
address for CHE operation.
24
23
IN1[31:16]
R/W
0
8
7
IN1[15:0]
R/W
0
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IN1
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Temporary buffer to load the CHE internal registers: KEY1, KEY5, IV1 and DES. Which registers are loaded
depends on CHE_START: in UPDATE mode, KEY1, KEY5, IV1 are loaded; in NORMAL mode, DES is
loaded.
KEY1 When CHE is in UPDATE mode and UPK01 is enabled, the content of IN1 is copied into the internal KEY1
registers.
KEY5 When CHE is in UPDATE mode and UPK45 is enabled, the content of IN1 is copied into the internal KEY5
registers.
IV1
When CHE is in UPDATE mode and UPIV01 is enabled, the content of IN1 is copied into the internal IV1
registers.
DES When CHE is in NORMAL mode, the content of IN1 is copied into internal DES if UPDES is asserted or if this
operation immediately follows a reset or a last operation. DES is the destination address for a CHE operation.
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Info: About the destination buffer length:
In ciphering mode, the destination buffer length must be larger than the source data length.
len_descipher = len_srccipher + BLOCK_SIZE – (len_srccipher% BLOCK_SIZE)
In deciphering mode, the destination data length is the same as the source data length, a multiple of
BLOCK_SIZE.
In hash mode, the destination buffer length is 16 bytes in MD5 mode and 20 bytes in SHA-1 mode.
BLOCK_SIZE is 8 bytes in DES (3-DES) mode and 16 bytes in AES mode.
Bit
Name
Type
Reset
Bit
Name
Type
Reset
IN2
31
30
15
14
CHE key2/key6/initial vector 2/operation length
29
28
27
26
25
24
23
IN2[31:16]
R/W
0
8
7
IN2[15:0]
R/W
0
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CHE+0010h
13
12
11
10
9
CHE_IN2
22
21
20
19
18
17
16
6
5
4
3
2
1
0
MT
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Temporary buffer to load the CHE internal registers: KEY2, KEY6, IV2 and LEN. Which registers are loaded
in depends on CHE_START: in UPDATE mode, KEY2, KEY6, IV2 are loaded; in NORMAL move, LEN is
loaded.
KEY2 When CHE is in UPDATE mode and UPK23 is enabled, the content of IN2 is copied into the internal KEY2
registers.
KEY6 When CHE is in UPDATE mode and UPK67 is enabled, the content of IN2 is copied into the internal KEY6
registers.
IV2
When CHE is in UPDATE mode and UPIV23 is enabled, the content of IN2 is copied into the internal IV2
registers.
LEN When CHE is in NORMAL mode, the content of IN2 is copied into the internal LEN registers. LEN is the
length for the CHE operation. A zero length is allowed only in a last operation (LAST asserted); avoid using a
zero length if possible. If a zero-length setting is unavoidable, clear the CHE after this operation. If a zero
length is used in ciphering mode, the corresponding padded cipher text would be output. In deciphering mode,
CHE resets. Both of them are regardless of previous ciphering or deciphering operations.
In hash mode, if there are previous hash operations, CHE resets. Otherwise, the digest of zero length is output.
I.e., MD5 outputs “d41d8cd98f00b204e9800998ecf8427e” and SHA1 outputs
“da39a3ee5e6b4b0d3255bfef95601890afd80709".
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CHE+0014h
Bit
Name
Type
Reset
Bit
Name
Type
Reset
Revision 1.0
CHE key3/key7/initial vector 3/state address
31
30
29
28
27
26
25
15
14
13
12
11
10
9
24
23
IN3[31:16]
R/W
0
8
7
IN3[15:0]
R/W
0
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CHE_IN3
22
21
20
19
18
6
5
4
3
2
IN3
17
16
1
0
Bit
Name
Type
Reset
15
14
CHE slow down rate
13
12
11
10
9
8
7
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CHE+0018h
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Temporary buffer to load the CHE internal registers: KEY3, KEY7, IV3 and SADDR. Which registers are
loaded depends on CHE_START: in UPDATE mode, KEY3, KEY7, IV3 are loaded; in NORMAL mode,
SADDR is loaded.
KEY3 When CHE is in UPDATE mode and UPK23 is enabled, the content of IN3 is copied into internal KEY3
registers.
KEY7 When CHE is in UPDATE mode and UPK67 is enabled, the content of IN3 is copied into internal KEY7
registers.
IV3
When CHE is in UPDATE mode and UPIV23 is enabled, the content of IN3 is copied into internal IV3
registers.
SADDR When CHE is in NORMAL mode, the content of IN3 is copied into the internal SADDR registers.
SADDR is the state/KEY address for the CHE operation. If RSTAT or WSTAT is asserted, CHE treats SADDR
as a state address, and reads or writes 120 bytes from or to this address. If RKEY or WKEY is asserted, CHE
reads or stores 36-byte KEYs from or to SADDR. Note: SADDR must 4-byte aligned.
6
5
4
3
SDRAT
R/W
0
CHE_SDRAT
2
1
0
SDRAT Slow down CHE to prevent too many requests for AHB resources. Each unit increment translates into a
4-cycle delay for each bus access (read or write). The range of SDRAT is from 0 (no delay) to 255
(255*4=1020 cycles’ delay).
CHE+001ch
Bit
Name
Type
Reset
15
14
CHE pad count
13
12
11
10
9
8
7
CHE_PCNT
6
5
4
3
2
PCNT
RO
0
1
0
PCNT When performing symmetric deciphering, this register indicates the padding length.
CHE+0020h
Bit
Name
Type
Reset
15
14
CHE return status
13
12
11
10
9
8
7
CHE_STAT
6
5
4
3
2
1
STAT
RO
0
0
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STAT STAT represents the current state of CHE. 000b: OK. 001b: control field setting error. 010b: zero length
for a non-last operation, or a last operation that is not hash nor ciphering (a last operation that is deciphering).
011b: resume state, wait for the next last or non-last operation. 100b: BUSY. 101b: RKEY and WKEY at the
same time.
CHE+0024h
Bit
Name
31
30
CHE current destination address
29
28
27
26
25
24
23
CDES[31:16]
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21
20
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Type
Reset
Bit
Name
Type
Reset
Revision 1.0
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MT6228 GSM/GPRS Baseband Processor Data Sheet
RO
0
15
14
13
12
11
10
9
8
7
CDES[15:0]
RO
0
6
5
4
3
6
5
4
3
2
1
CDES CDES is the current destination address in CHE.
Bit
Name
Type
Reset
15
14
CHE interrupt status
13
12
11
10
CHE_INTSTA
9
8
7
CHE+002ch
Bit
Name
Type
Reset
15
14
CHE interrupt enable
13
12
11
10
9
8
7
6
5
4
1
0
INTSTA
RC
0
Bit 1 indicates CHE
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INTSTA Interrupt status. Bit 0 indicates CHE finished in the OK or RESUME state.
returned a failure. Further information can be obtained from CHE_STAT.
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CHE+0028h
0
3
CHE_INTEN
2
1
0
INTEN
R/W
0
INTEN Interrupt enable control register. When bit 0 is enabled, an interrupt occurs when CHE finishes in the OK or
RESUME state. If bit 1 is enabled, CHE interrupts if an error occurs.
CHE+00c0h
Bit
Name
Type
Reset
15
14
CHE Secure Booting control
13
12
11
10
9
8
7
6
5
4
CHE_BCON
3
2
1
0
PAR3 PAR2 PAR1 DIS
R/W R/W R/W R/W
0
0
0
0
DIS
CHE+00c4h
Bit
Name
Type
Reset
Bit
Name
Type
Reset
31
30
15
14
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Disable Secure Booting function. When DIS is asserted, the data read from CHE_BENC and CHE_BDEC is
the same as CHE_BSRC.
PAR1 Use inner information parameter 1 (SK) to strengthen security.
PAR2 Use inner information parameter 2 (RS) to strengthen security.
PAR3 Use inner information parameter 3 (MR) to strengthen security.
CHE Secure Booting source data
29
28
27
26
25
13
12
11
10
9
24
23
BSRC[31:16]
WO
0
8
7
BSRC[15:0]
WO
0
CHE_BSRC
22
21
20
19
18
17
16
6
5
4
3
2
1
0
BSRC Source data for Secure Booting to be encrypted (obtained from CHE_BENC) or decrypted (obtained from
CHE_BDEC).
CHE+00c8h
31
30
CHE Secure Booting seed value
29
MT
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Bit
Name
Type
Reset
Bit
Name
Type
Reset
15
14
13
28
27
26
25
12
11
10
9
24
23
22
BSEED[31:16]
WO
0
8
7
6
BSEED[15:0]
WO
0
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BSEED Seed data needed to increase security of the Boot Secure function.
Boot Secure the first time.
Bit
Name
Type
Reset
Bit
Name
Type
Reset
Set the seed value before performing
CHE Secure Booting encrypted data
31
30
29
28
27
26
25
15
14
13
12
11
10
9
24
23
BENC[31:16]
RO
0
8
7
BENC[15:0]
RO
0
CHE_BENC
22
21
20
19
18
6
5
4
3
2
22
21
20
BENC Encrypted data from CHE_BSRC.
Bit
Name
Type
Reset
Bit
Name
Type
Reset
CHE Secure Booting decrypted data
31
30
29
28
27
26
25
15
14
13
12
11
10
9
24
23
BDEC[31:16]
RO
0
8
7
BDEC[15:0]
RO
0
BDEC Decrypted data from CHE_BSRC.
4.12.2
CHE KEY Phase Transient
16
1
0
CHE_BDEC
19
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CHE+00d0h
17
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CHE+00cch
Revision 1.0
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6
5
4
3
18
17
16
2
1
0
In CHE, all cipher and decipher functions need a KEY, i.e., AES, DES, 3DES. However, due to the cost and
performance concern, all the keys are put together in a KEY buffer with four phases (Figure 56).
Phase 1: AES128 decipher phase.
2.
Phase 2: AES192 decipher phase
3.
Phase 3: AES256 decipher phase.
4.
Phase 4: Common phase, other functions which exclude the AES decipher. I.e., DES (cipher and decipher),
3DES (cipher and decipher), AES128, AES192, AES256 cipher.
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1.
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Figure 56 Key Phase Transient GraphPhases 1 through 3 are internal phases, unknown to the user. When the user
first enters the key data, the key phase is reset to the Common Phase. Transition among phases is limited to the
arrows shown in Figure 56. For example, if currently performing a 3DES cipher function, any cipher or decipher
function may follow. If currently using a AES192 decipher function, only the AES192 decipher function or the
Common Phase algorithms may be used next; otherwise an error occurs.
For security reasons and convenience, the key phase can be saved with key contents by WKEY or WSTAT. The user
is highly recommended to convert raw key data into CKEY data format (using WKEY), discard the original key data,
and to use CKEY by RKEY.
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4.12.3
Revision 1.0
Secure Booting Procedure
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MT6228 GSM/GPRS Baseband Processor Data Sheet
Secure Booting is a feature of CHE that protects the program contents on flash memory from modification, skip or hard
copy. With a secure process and a unique chip ID (UID), CHE can encrypt or decrypt a segment of instruction data in
order.
Encryption procedure:
1. Activate the eFuse module.
The same seed value is
3. Write the control value into BCON.
5. Repeat step 4 until all instructions are encrypted.
Decryption procedure:
1. Activate the eFuse module.
2. Write the seed value into BSEED.
3. Write the control value into BCON.
procedure.
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4. Write source data (instruction) into BSRC and read the cipher text from BENC.
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2. Write the seed value into BSEED. The seed value can be any 32-bit value.
necessary in the decryption procedure.
The seed value must be the same one used in the encryption procedure.
The control value must be the same one used in the encryption
4. Write the source data (instruction) into BSRC and read the plain text from BDEC.
5. Repeat step 4 until all instructions are decrypted.
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Notes:
1. A bit length equal or less than 32 bits is acceptable for Secure Boot.
0x12340000 32-bit data and decrypted in the same manner.
E.g.: a 16-bit data 0x1234 is treated as
2. For security reasons, access times to be encrypted or decrypted should not be the multiples of 4.
3. The internal states of Secure Booting function change under the following conditions, such that redundant
register access is forbidden.
Write data into BSRC
Write data into BSEED
Read data from BENC or BDEC
As an example of the encryption and decryption of 16-bit data, consider the value 0xabcd:
Encryption:
1. The data is padded with zeros to obtain a 32-bit value: 0xabcd0000.
2. The encryption operation produces a value 0x12345678.
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Decryption:
1. Only the most significant 16 bits 0x1234000 are considered and decrypted as 0xabcd7893.
2. The first 16 bits 0xabcd are retained, and 0x00007893 is ignored.
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5
Microcontroller Coprocessors
Revision 1.0
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MT6228 GSM/GPRS Baseband Processor Data Sheet
Microcontroller Coprocessors are designed to run computing-intensive processes in place of the Microcontroller
(MCU). These coprocessors especially target timing critical GSM/GPRS Modem processes that require fast response
and large data movement. Controls to the coprocessors are all through memory access via the APB.
Divider
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5.1
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To ease the processing load of the MCU, a divider is employed. The divider can perform signed and unsigned
32bit/32bit division, as well as modulus. The processing time of the divider is from 1 clock cycle to 33 clock cycles,
depending on the magnitude of the dividend. Detailed processing times are listed below in Table 32. Table 32
shows two processing times (except for when the dividend is zero) for each range of dividends, depending on whether
or not restoration is required during the last step of the division operation.
Table 32 Processing Time for Different Dividend Values
Signed Division
Unsigned Division
Dividend
Clock Cycles
Dividend
Clock Cycles
1
0000_0000h
1
0000_00ffh –
(-0000_0100h), excluding
0x0000_0000
8 or 9
0000_0001h - 0000_00ffh
8 or 9
0000_ffffh – (-0001_0000h) 16 or 17
0000_0100h - 0000_ffffh
16 or 17
00ff_ffffh – (-0100_0000h) 24 or 25
0001_0000h - 00ff_ffffh
24 or 25
7fff_ffffh – (-8000_0000h) 32 or 33
0100_0000h - ffff_ffffh
32 or 33
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0000_0000h
Table 33 Processing Time for Different Dividend Values
When the divider is started by setting the Divider Control Register START bit to 1, DIV_RDY becomes 0; this bit is
asserted when the division process is complete. MCU detects this status bit by polling it to know the correct access
timing. To simplify polling, only the value of register DIV_RDY is visible while Divider Control Register is being
read. Hence, MCU does not need to mask other bits to extract the value of DIV_RDY.
In a GSM/GPRS system, many divisions are executed with constant divisors. Therefore, oft-used constants are stored
in the divider to speed up the process. By controlling control bits IS_CNST and CNST_IDX in Divider Control
register, a division can be performed without providing a divisor. This omission of a step saves on the time for writing
a divisor in and on the instruction fetch time, thus making the process more efficient.
5.1.1
Register Definitions
DIVIDER+000
Divider Control Register
0h
31
30
29
28
27
26
25
24
23
22
15
14
13
12
11
10
9
8
7
6
MT
K
Bit
Name
Type
Reset
Bit
DIV_CON
21
20
19
5
4
3
IN_CNS
SIGN
T
Name
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18
17
16
CNST_IDX
WO
0
2
1
0
DIV_RD STAR
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Type
Reset
WO
0
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MT6228 GSM/GPRS Baseband Processor Data Sheet
WO
1
RO
1
START
DIV_RDY
WO
0
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Starts a division operation. Returns to 0 after the division has started.
Current status of the divider. Note that when DIV_CON register is read, only the value of DIV_RDY
appears; the program does not need to mask other parts of the register to extract the information in
DIV_RDY.
0
Division is in progress.
1
Division is finished
SIGN
Indicates a signed or unsigned division operation.
0
Unsigned division
1
Signed division
IS_CNST Specifies that an internal constant value should be used as a divisor. If IS_CNST is enabled, the divisor
value need not be written, and divider automatically uses the internal constant value instead. The
internal constant value used depends on the value of CNST_IDX.
0 Normal division. Divisor is written in via APB.
1 Using internal constant divisor instead.
CNST_IDX
Index of constant divisor.
0
divisor = 13
1
divisor = 26
2
divisor = 51
3
divisor = 52
4
divisor = 102
5
divisor = 104
DIVIDER
+0004h
31
30
15
14
Dividend.
DIVIDER
+0008h
29
28
27
26
13
12
11
10
25
24
23
22
DIVIDEND[31:16]
WO
0
9
8
7
6
DIVIDEND[15:0]
WO
0
DIV_DIVIDEND
21
20
19
18
17
16
5
4
3
2
1
0
Divider Divisor register
31
30
15
14
29
28
27
26
13
12
11
10
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Bit
Name
Type
Reset
Bit
Name
Type
Reset
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Bit
Name
Type
Reset
Bit
Name
Type
Reset
Divider Dividend register
25
24
23
22
DIVISOR[31:16]
WO
0
9
8
7
6
DIVISOR[15:0]
WO
0
DIV_DIVISOR
21
20
19
18
17
16
5
4
3
2
1
0
Divisor.
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DIVIDER
+000Ch
31
30
29
28
27
26
15
14
13
12
11
10
DIV_QUOTIENT
25
24
23
22
QUOTIENT[31:16]
RO
0
9
8
7
6
QUOTIENT[15:0]
RO
0
21
20
19
18
5
4
3
2
Quotient.
DIVIDER
+0010h
31
30
29
28
27
26
15
14
13
12
11
10
Remainder.
5.2.1
1
0
21
20
19
18
17
16
5
4
3
2
1
0
CSD Accelerator
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5.2
25
24
23
22
REMAINDER[31:16]
RO
0
9
8
7
6
REMAINDER[15:0]
RO
0
16
DIV_REMAINDE
R
Divider Remainder register
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Bit
Name
Type
Reset
Bit
Name
Type
Reset
17
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Bit
Name
Type
Reset
Bit
Name
Type
Reset
Divider Quotient register
Revision 1.0
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MT6228 GSM/GPRS Baseband Processor Data Sheet
General Description
This unit performs the data format conversion of RA0, RA1, and FAX in CSD service. CSD service consists of two
major functions: data flow throttling and data format conversion. The data format conversion is a bit-wise operation
and requires several instructions to complete a conversion, thus making it inefficient for the MCU to perform itself. A
coprocessor, CSD accelerator, is designed to reduce the computing power needed to perform this function.
The CSD accelerator helps in converting data format only; the data flow throttling function is still implemented by the
MCU. CSD accelerator performs three types of data format conversion: RA0, RA1, and FAX.
MT
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For RA0 conversion, too many case scenarios for the downlink path conversion greatly increase the hardware area cost,
thus only uplink RA0 data format conversion is provided. Uplink RA0 conversion consists of inserting a start bit
before and a stop bit after each a byte, for a duration of 16 bytes.
illustrates the detailed conversion table.
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Figure 57 Data Format Conversion of RA0
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MT6228 GSM/GPRS Baseband Processor Data Sheet
The RA0 converter processes data state by state. Therefore, before filling in new data, software must ensure that
converted data of in a state is withdrawn, otherwise the converted data is replaced by new data. For example, if 32
bits of data are written, the state pointer increments from state 0 to state 1, and word ready of state 0 is asserted.
Before writing the next 32-bit data, the word of state 0 must be withdrawn first, or the data is lost when the next
conversion is performed.
RA0 records the number of written bytes, the state pointer, and a ready state word.
software to perform flow control. See Register Definition for more detail.
This information helps the
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For RA1 conversion, both downlink and uplink directions are supported. The data formats vary for different data rate.
Detailed conversion tables are shown in and . The yellow part is the payload data, and the blue part is the status bit.
Figure 58 Data Format Conversion for 6k/12k RA1
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Figure 59 Data Format Conversion for 3.6k RA1
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Type 1 reversal is a bit-wise reversal (), and Type 2 is a
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For FAX, two types of bit-reversal functions are provided.
byte-wise reversal ().
Revision 1.0
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MT6228 GSM/GPRS Baseband Processor Data Sheet
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Figure 60 Type 1 Bit Reversal
Figure 61 Type 2 Bit Reversal
Register Address
Register Function
Acronym
CSD RA0 Control Register
CSD_RA0_CON
CSD RA0 Status Register
CSD_RA0_STA
CSD RA0 Input Data Register
CSD_RA0_DI
CSD + 000Ch
CSD RA0 Output Data Register
CSD_RA0_DO
CSD + 0100h
CSD RA1 6K/12K Uplink Input Data Register 0
CSD_RA1_6_12K_ULDI0
CSD + 0104h
CSD RA1 6K/12K Uplink Input Data Register 1
CSD_RA1_6_12K_ULDI1
CSD + 0108h
CSD RA1 6K/12K Uplink Status Data Register
CSD_RA1_6_12K_ULSTUS
CSD + 010Ch
CSD RA1 6K/12K Uplink Output Data Register 0
CSD_RA1_6_12K_ULDO0
CSD + 0000h
CSD + 0004h
MT
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CSD + 0008h
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MT6228 GSM/GPRS Baseband Processor Data Sheet
CSD + 0110h
CSD RA1 6K/12K Uplink Output Data Register 1
CSD_RA1_6_12K_ULDO1
CSD + 0200h
CSD RA1 6K/12K Downlink Input Data Register 0
CSD_RA1_6_12K_DLDI0
CSD + 0204h
CSD RA1 6K/12K Downlink Input Data Register 1
CSD_RA1_6_12K_DLDI1
CSD + 0208h
CSD RA1 6K/12K Downlink Output Data Register 0
CSD_RA1_6_12K_DLDO0
CSD + 020Ch
CSD RA1 6K/12K Downlink Output Data Register 1
CSD_RA1_6_12K_DLDO1
CSD RA1 6K/12K Downlink Status Data Register
CSD_RA1_6_12K_DLSTUS
CSD RA13.6K Uplink Input Data Register 0
CSD_RA1_3P6K_ULDI0
CSD + 0304h
CSD RA13.6K Uplink Status Data Register
CSD_RA1_3P6K_ULSTUS
CSD + 0308h
CSD RA13.6K Uplink Output Data Register 0
CSD_RA1_3P6K_ULDO0
CSD + 030Ch
CSD RA13.6K Uplink Output Data Register 1
CSD_RA1_3P6K_ULDO1
CSD + 0400h
CSD RA1 3.6K Downlink Input Data Register 0
CSD_RA1_3P6K_DLDI0
CSD + 0404h
CSD RA1 3.6K Downlink Input Data Register 1
CSD_RA1_3P6K_DLDI1
CSD + 0408h
CSD RA1 3.6K Downlink Output Data Register 0
CSD_RA1_3P6K_DLDO0
CSD + 040Ch
CSD RA1 3.6K Downlink Status Data Register
CSD_RA1_3P6K_DLSTUS
CSD + 0500h
CSD FAX Bit Reverse Type 1 Input Data Register
CSD_FAX_BR1_DI
CSD + 0504h
CSD FAX Bit Reverse Type 1 Output Data Register
CSD_FAX_BR1_DO
CSD + 0510h
CSD FAX Bit Reverse Type 2 Input Data Register
CSD_FAX_BR2_DI
CSD + 0514h
CSD FAX Bit Reverse Type 2 Output Data Register
CSD_FAX_BR2_DO
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CSD + 0210h
CSD + 0300h
Table 34 CSD Accelerator Registers
Register Definitions
CSD+0000h
Bit
Name
Type
Reset
Bit
Name
Type
Reset
31
30
15
14
CSD RA0 Control Register
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5.2.2
CSD_RA0_CON
29
28
27
26
25
24
23
22
13
12
11
10
9
8
7
6
21
20
5
4
RST BTS0
WO WO
0
0
19
18
3
2
17
16
1
0
VLD_BYTE
WO
100
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VLD_BYTE Specifies the number of valid bytes in the current input data. This value must be specified before filling
data.
BTS0 Back to state 0. Forces RA0 converter return back to state 0. Incomplete words are padded with stop bits.
For example, consider a back-to-state0 command that is issued after 8 bytes of data are filled in. All bits
after the 8th byte are padded with stop bits, and the second ready word byte RDYWD2 is asserted (Figure 62).
After removing state word 2, the state pointer goes back to state 0. Note that new data filling should take
place after removing state word 2, or the state pointer may be out of order.
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Figure 62 Example of Back to State 0
Resets the RA0 converter.
original state.
CSD+0004h
Bit
Name
Type
Reset
Bit
Name
Type
Reset
If an erroneous operation disorders the data, this bit restores all states to their
CSD RA0 Status Register
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RST
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MT6228 GSM/GPRS Baseband Processor Data Sheet
CSD_RA0_STA
31
30
29
28
27
26
25
24
15
14
13
12
11
10
9
BYTECNT
RO
0
8
23
7
22
21
20
19
18
17
16
6
5
CRTSTA
RO
0
4
3
2
RDYWD
RC
0
1
0
CSD+0008h
Bit
Name
Type
Reset
Bit
Name
Type
Reset
DIN
31
30
CSD RA0 Input Data Register
29
28
27
26
25
24
CSD_RA0_DI
23
22
21
20
19
18
17
16
7
6
5
4
3
2
1
0
DIN
WO
0
15
14
13
12
11
10
9
8
DIN
WO
0
The RA0 conversion input data. The ready word indicator is checked before filling in data; if any words are
ready, they are withdrawn first, otherwise the ready data in RA0 converter is replaced.
CSD+000Ch
CSD RA0 Output Data Register
31
30
29
28
27
26
25
15
14
13
12
11
10
9
MT
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Bit
Name
Type
Reset
Bit
Name
Type
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RDYWD0~4
Ready words. Indicates which state words are ready for withdrawal. If any bits asserted, data
must be withdrawn before new data is filled into CSD_RA0_DI, to avoid data loss.
0 Not ready
1 Ready
CRTSTA Current state. State0 ~ State4. Indicates which state word software is currently filling.
BYTECNT Total number of bytes being filled.
24
23
DOUT
RO
0
8
7
DOUT
RO
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22
21
20
19
18
17
16
6
5
4
3
2
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MT6228 GSM/GPRS Baseband Processor Data Sheet
0
DOUT RA0 converted data. The return data corresponds to the ready word indicator defined in CSD_RA0_STA
register. The five bits of RDYWD map to state0 ~ state 4 respectively. When CSD_RA0_DO is read, the
asserted state word is returned. If two state words asserted at the same time, the lower one is returned.
30
Bit
Name
Type
Reset
Bit
Name
Type
Reset
31
DIN
D1 to D32 of the RA1 uplink data.
29
28
27
26
25
24
23
22
21
20
7
6
5
4
DIN
WO
0
15
14
13
12
11
10
9
8
19
3
31
30
29
28
27
26
25
24
15
14
13
12
11
10
9
8
DIN
D33 to D48 of the RA1 uplink data.
17
2
1
16
0
CSD_RA1_6_12
K_ULDI1
CSD RA1 6K/12K Uplink Input Data Register 1
Bit
Name
Type
Reset
Bit
Name
Type
Reset
18
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DIN
WO
0
CSD+0104h
23
22
21
20
19
18
17
16
7
6
5
4
3
2
1
0
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DIN
WO
0
CSD+0108h
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
E7
WO
0
5
E6
WO
0
4
E5
WO
0
3
E4
WO
0
2
X
WO
0
1
SB
WO
0
0
SA
WO
0
SA
SB
X
E4
E5
E6
E7
Represents S1, S3, S6, and S8 of the status bits.
Represents S4 and S9 of the status bits.
Represents X of the status bits.
Represents E4 of the status bits.
Represents E5 of the status bits.
Represents E6 of the status bits.
Represents E7 of the status bits.
MT
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31
CSD+010Ch
31
30
CSD_RA1_6_12
K_ULSTUS
CSD RA1 6K/12K Uplink Status Data Register
Bit
Name
Type
Reset
Bit
Name
Type
Reset
Bit
Name
CSD_RA1_6_12
K_ULDI0
CSD RA1 6K/12K Uplink Input Data Register 0
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CSD+0100h
CSD_RA1_6_12
K_ULDO0
CSD RA1 6K/12K Uplink Output Data Register 0
29
28
27
26
25
24
23
DOUT
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Type
Reset
Bit
Name
Type
Reset
Revision 1.0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
DOU
RO
0
DOUT Bit 0 to bit 31 of the RA1 6K/12K uplink frame.
31
30
29
28
27
26
25
24
23
15
14
13
12
11
10
9
8
7
DOUT
RO
0
DOUT Bit 32 to bit 59 of the RA1 6K/12K uplink frame.
CSD+0200h
30
31
DIN
Bit 0 to bit 31 of the RA1 6K/12K downlink frame.
15
14
18
17
16
3
2
1
0
CSD_RA1_6_12
K_DLDI0
29
28
27
26
25
24
23
22
21
20
19
18
17
16
13
12
11
10
9
8
7
6
5
4
3
2
1
0
31
15
30
14
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DIN
WO
0
CSD_RA1_6_12
K_DLDI1
CSD RA1 6K/12K Downlink Input Data Register 1
29
13
28
12
27
11
26
10
25
9
24
23
8
7
22
21
20
19
18
17
16
5
4
3
2
1
0
DIN
WO
0
6
DIN
WO
0
Bit 32 to bit 59 of the RA1 6K/12K downlink frame.
CSD+0208h
31
30
15
14
CSD_RA1_6_12
K_DLDO0
CSD RA1 6K/12K Downlink Output Data Register 0
29
MT
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Bit
Name
Type
Reset
Bit
Name
Type
Reset
4
19
DIN
WO
0
CSD+0204h
DIN
20
CSD RA1 6K/12K Downlink Input Data Register 0
Bit
Name
Type
Reset
Bit
Name
Type
Reset
Bit
Name
Type
Reset
Bit
Name
Type
Reset
22
21
DOUT
RO
0
6
5
0
CSD_RA1_6_12
K_ULDO1
CSD RA1 6K/12K Uplink Output Data Register 1
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Bit
Name
Type
Reset
Bit
Name
Type
Reset
1
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CSD+0110h
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MT6228 GSM/GPRS Baseband Processor Data Sheet
13
28
27
26
25
12
11
10
9
24
23
DOUT
RO
0
8
7
DOUT
RO
0
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16
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5
4
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DOUT D1 to D32 of the RA1 downlink data.
CSD+020Ch
31
30
29
28
27
26
25
24
23
22
21
20
19
18
15
14
13
12
11
10
9
8
7
DOUT
RO
0
6
5
4
3
2
DOUT D33 to D48 of the RA1 downlink data.
31
30
29
28
27
26
25
24
15
14
13
12
11
10
9
8
SA
SB
X
E4
E5
E6
E7
The majority vote of the S1, S3, S6 and S8 status bits. If the vote is split, SA=0.
The majority vote of the S4 and S9 status bits. If the vote is split, SB=0.
The majority vote of the two X bits in downlink frame. If the vote is split, X=0.
Represents E4 of the status bits.
Represents E5 of the status bits.
Represents E6 of the status bits.
Represents E7 of the status bits.
DIN
31
15
30
14
13
12
27
11
26
10
25
9
24
21
20
19
18
17
16
7
6
E7
RO
0
5
E6
RO
0
4
E5
RO
0
3
E4
RO
0
2
X
RO
0
1
SB
RO
0
0
SA
RO
0
23
8
0
CSD_RA1_3P6
K_ULDI0
7
22
21
20
19
18
17
16
3
2
1
0
DIN
WO
0
6
5
4
DIN
WO
0
D1 to D24 of the RA1 3.6K uplink data.
CSD_RA1_3P6
K_ULSTUS
CSD RA1 3.6K Uplink Status Data Register
MT
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CSD+0304h
Bit
Name
Type
Reset
Bit
Name
28
1
22
CSD RA1 3.6K Uplink Input Data Register 0
29
16
23
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Bit
Name
Type
Reset
Bit
Name
Type
Reset
CSD+0300h
17
CSD_RA1_6_12
K_DLSTUS
CSD RA1 6K/12K Downlink Status Data Register
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CSD+0210h
Bit
Name
Type
Reset
Bit
Name
Type
Reset
CSD_RA1_6_12
K_DLDO1
CSD RA1 6K/12K Downlink Output Data Register 1
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Bit
Name
Type
Reset
Bit
Name
Type
Reset
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30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
E7
5
E6
4
E5
3
E4
2
X
1
SB
0
SA
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Type
Reset
31
30
29
28
27
26
25
15
14
13
12
11
10
9
24
23
DOUT
RO
0
8
7
DOUT
RO
0
31
30
15
14
21
29
28
27
26
25
24
13
12
11
10
9
WO
0
6
5
23
8
7
WO
0
WO
0
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20
19
4
3
18
17
16
2
1
0
CSD_RA1_3P6
K_ULDO1
CSD RA1 3.6K Uplink Output Data Register 1
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CSD+030Ch
22
WO
0
CSD_RA1_3P6
K_ULDO0
CSD RA1 3.6K Uplink Output Data Register 0
DOUT Bit 0 to bit 31 of the RA1 3.6K uplink frame.
Bit
Name
Type
Reset
Bit
Name
Type
Reset
WO
0
Represents S1, S3, S6, and S8 of the status bits.
Represents S4 and S9 of the status bits.
Represents X of the status bits.
Represents E4 of the status bits.
Represents E5 of the status bits.
Represents E6 of the status bits.
Represents E7 of the status bits.
CSD+0308h
Bit
Name
Type
Reset
Bit
Name
Type
Reset
WO
0
Re
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SA
SB
X
E4
E5
E6
E7
WO
0
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21
20
19
18
17
16
6
5
4
3
2
1
DOUT
RO
0
0
DOUT Bit 32 to bit 35 of the RA1 3.6K uplink frame.
CSD+0400h
30
Bit
Name
Type
Reset
Bit
Name
Type
Reset
31
DIN
Bit 0 to bit 31 of the RA1 3.6K downlink frame.
29
28
27
26
25
24
23
22
21
20
19
18
17
16
7
6
5
4
3
2
1
0
DIN
WO
0
15
14
13
12
11
10
9
8
DIN
WO
0
31
30
CSD_RA1_3P6
K_DLDI1
CSD RA1 3.6K Downlink Input Data Register 1
MT
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CSD+0404h
Bit
Name
Type
Reset
CSD_RA1_3P6
K_DLDI0
CSD RA1 3.6K Downlink Input Data Register 0
29
28
27
26
25
24
23
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Bit
Name
Type
Reset
15
14
DIN
Bit 32 to bit 35 of the RA1 3.6K downlink frame.
11
10
9
8
7
6
5
4
3
2
1
0
30
29
28
27
26
25
24
23
22
21
15
14
13
12
11
10
9
8
7
DOUT
RP
0
6
5
D1 to D24 of the RA1 3.6K downlink data.
20
19
DOUT
RO
0
4
3
30
29
28
27
26
25
24
15
14
13
12
11
10
9
8
SA
SB
X
E4
E5
E6
E7
The majority vote of the S1, S3, S6 and S8 status bits. If the vote is split, SA=0.
The majority vote of the S4 and S9 status bits. If the vote is split, SB=0.
The majority vote of the two X bits in downlink frame. If the vote is split, X=0.
Represents E4 of status bits.
Represents E5 of status bits.
Represents E6 of status bits.
Represents E7 of status bits.
27
26
25
24
1
0
21
20
19
18
17
16
7
6
E7
RO
0
5
E6
RO
0
4
E5
RO
0
3
E4
RO
0
2
X
RO
0
1
SB
RO
0
0
SA
RO
0
CSD_FAX_BR1
_DI
Bit
Name
Type
Reset
Bit
Name
Type
Reset
31
DIN
32-bit input data for a Type 1 bit reversal of the FAX data. A Type 1 bit reversal reverses the data bit by bit.
23
22
21
20
19
18
17
16
7
6
5
4
3
2
1
0
DIN
WO
0
15
14
13
12
11
10
9
8
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DIN
WO
0
CSD+0504h
Bit
Name
28
2
22
CSD FAX Bit Reverse Type 1 Input Data Register
29
16
23
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31
30
17
CSD_RA1_3P6
K_DLSTUS
CSD RA1 3.6K Downlink Status Data Register
Bit
Name
Type
Reset
Bit
Name
Type
Reset
CSD+0500h
18
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31
CSD+040Ch
CSD_RA1_3P6
K_DLDO0
CSD RA1 3.6K Downlink Output Data Register 0
Re
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DIN
12
DIN
WO
0
CSD+0408h
Bit
Name
Type
Reset
Bit
Name
Type
Reset
13
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30
CSD_FAX_BR1
_DO
CSD FAX Bit Reverse Type 1 Output Data Register
29
28
27
26
25
24
23
DOUT
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Reset
Bit
Name
Type
Reset
Revision 1.0
RO
0
15
14
13
12
11
10
9
8
7
DOUT
RO
0
6
5
4
3
2
DOUT 32-bit result data for a Type 1 bit reversal of the FAX data.
30
Bit
Name
Type
Reset
Bit
Name
Type
Reset
31
DIN
32-bit input data for a Type 2 bit reversal of the FAX data. A Type 2 bit reversal reverses the data byte by
byte.
27
26
25
24
23
22
21
20
7
6
5
4
DIN
WO
0
15
14
13
12
11
10
9
8
19
18
17
16
3
2
1
0
Re
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se
DIN
WO
0
CSD+0514h
CSD_FAX_BR2
_DO
CSD FAX Bit Reverse Type 2 Output Data Register
31
30
29
28
27
26
25
15
14
13
12
11
10
9
24
23
DOUT
RO
0
8
7
DOUT
RO
0
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Bit
Name
Type
Reset
Bit
Name
Type
Reset
28
0
CSD_FAX_BR2
_DI
CSD FAX Bit Reverse Type 2 Input Data Register
29
1
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CSD+0510h
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22
21
20
19
18
17
16
6
5
4
3
2
1
0
DOUT 32-bit result data for a Type 2 bit reversal of the FAX data.
5.3
5.3.1
FCS Codec
General Description
The Frame Check Sequence (FCS) serves to detect errors in the following information bits:
RLP-frame of CSD services in GSM: The frame length is fixed at 240 or 576 bits including the 24-bit FCS
field.
LLC-frame of GPRS service: The frame length is determined by the information field, and length of the
FCS field is 24 bits.
Generation of the FCS is very similar to CRC coding in baseband signal processing.
and 04.64 both define the coding rules as:
The CRC is the one’s complement of the modulo-2 sum of the following additives:
MT
K
1.
ETSI GSM specifications 04.22
•
the remainder of xk (x23 + x22 + x21 + … + x2 + x + 1) modulo-2 divided by the generator polynomial, where k
is the number of bits of the dividend (i.e. fill the shift registers with all ones initially before feeding data); and,
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the remainder of the modulo-2 division by the generator polynomial of the product of x24 by the dividend,
which are the information bits.
The CRC-24 generator polynomial is:
G(x) = x24 + x23 + x21 + x20 + x19 + x17 + x16 + x15 + x13 + x8 + x7 + x5 + x4 + x2 + 1
3.
The 24-bit CRC is appended to the data bits in the MSB-first manner.Decoding is identical to encoding except that
data fed into the syndrome circuit is 24 bits longer than the information bits at encoding. The dividend is also
multiplied by x24. If no error occurs, the remainder satisfies:
R(x) = x22 + x21 + x19 + x18 + x16 + x15 + x11 + x8 + x5 + x4 (0x6d8930)
The parity output word is 0x9276cf.
fo
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2.
5.3.2
Register Definitions
FCS+0000h
Bit
15
Name D15
Type WO
FCS input data register
14
D14
WO
13
D13
WO
12
D12
WO
11
D11
WO
10
D10
WO
9
D9
WO
8
D8
WO
Re
lea
se
In contrast to conventional CRC, this special coding scheme makes the encoder identical to the decoder and simplifies
the hardware design.
7
D7
WO
6
D6
WO
5
D5
WO
4
D4
WO
3
D3
WO
FCS_DATA
2
D2
WO
1
D1
WO
0
D0
WO
The data bits input. First write of this register is the starting point of the encode or decode process.
D0~15 The input format is D15·xn+ D14·xn-1+ D13·xn-2+ … + Dk·xk+ …, thus D15 is the first bit pushed into the
shift register. If the last data word is less than 16 bits, the remaining bits are neglected.
FCS+0004h
15
14
13
12
11
10
9
8
7
6
5
4
3
FCS_DLEN
2
1
0
LEN
WO
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Bit
Name
Type
Input data length indication register
The MCU specifies the total data length (in bits) to be encoded or decoded.
LEN
Data length. The length must be a multiple of 8 bits.
FCS+0x0008h FCS parity output register 1, MSB part
Bit
15
Name P15
Type RC
Reset
0
14
P14
RC
0
FCS+000Ch
Bit
Name
Type
Reset
15
14
13
P13
RC
0
12
P12
RC
0
11
P11
RC
0
10
P10
RC
0
9
P9
RC
0
8
P8
RC
0
7
P7
RC
0
6
P6
RC
0
FCS_PAR1
5
P5
RC
0
4
P4
RC
0
3
P3
RC
0
2
P2
RC
0
FCS parity output register 2, LSB part
13
12
11
10
9
8
7
P23
RC
0
6
P22
RC
0
1
P1
RC
0
0
P0
RC
0
FCS_PAR2
5
P21
RC
0
4
P20
RC
0
3
P19
RC
0
2
P18
RC
0
1
P17
RC
0
0
P16
RC
0
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Parity bits output. For FCS_PAR2, bit 8 to bit 15 are filled with zeros when reading.
P0~23 The output format is P23·D23+ P22·D22+ P21·D21+ … + Pk·Dk+ …+P1·D1+P0, thus P23 is the first bit
being popped out from the shift register and the first appended to the information bits. In other words,
{FCS_PAR2[7:0], FCS_PAR1[15:8], FCS_PAR1[7:0] } is the order of the parity bits appended to the data.
FCS+0010h
Bit
15
14
FCS codec status register
13
12
11
10
9
FCS_STAT
8
7
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BUSY FER
RC
RC
0
1
RDY
RC
0
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BUSY Indicates whether or not the current data work is available for writing. The codec works in a serial manner
and the data word is input in a parallel manner. BUSY=1 indicates that the current data word is being
processed and a write to FCS_DATA is invalid: the operation is permitted but the data may not be consistent.
BUSY=0 allows a write of FCS_DATA during an encoding or decoding process.
FER
Frame error indication, for decode mode only. FER=0 means no error has occurred; FER=1 indicates the
parity check has failed. Writing to FCS_RST.RST or the first write to FCS_DATA resets this bit to 0.
RDY When RDY=1, verify that the encode or decode process has been finished. For an encode, the parity data in
FCS_PAR1 and FCS_PAR2 are available and consistent. For a decode, FCS_STAT.FER indication is
valid. A write of FCS_RST.RST or the first write of FCS_DATA resets this bit to 0.
Bit
15
FCS codec reset register
14
13
12
11
10
9
FCS_RST
8
Name
Type
Re
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se
FCS+0014h
7
6
5
4
3
2
EN_D
PAR
E
WO WO
1
0
BIT
RST
WO
WO
RST=0 resets the CRC coprocessor. Before setup of the FCS codec, the MCU needs to set RST=0 to flush
the shift register content before encode or decode.
BIT
BIT=0 signifies not to invert the bit order in a data word byte when the codec is running. BIT=1 signifies to
reverse the bit order in a byte written in FCS_DATA.
PAR
PAR=0 means not to invert the bit order in a byte of parity words when the codec is running, including
reading FCS_PAR1 and FCS_PAR2. PAR=1 means the bit order of the parity words should be reversed,
in encoding or decoding .
EN_DE EN_DE=0 indicates an encode operation; EN_DE=1 indicates a decode operation.
5.4
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RST
PPP Framer Coprocessor
5.4.1
General Description
The PPP Framer Coprocessor (PFC) is an accelerator for PPP frame parsing; it helps pack and unpack the PPP frame
while performing:
1.
Flag sequence (0x7e) recognition,
2.
Byte stuffing handling, and
3.
16- or 32-bit frame check sequence (FCS) handling.
The PFC architecture is based on Direct Memory Access (DMA). All PPP framer parameters are configurable, such
as Address and Control Field Compression (ACFC), Protocol Field Compression (PFC), 16- or 32-bit FCS, and
Asynchronous Control Character Map (ACCM).
Register Definitions
MT
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5.4.2
Register Address
Register Function
Acronym
PFC + 0000h
PFC start register
PFC_START
PFC + 0004h
PFC control register
PFC_CON
PFC + 0008h
PFC encoding protocol
PFC_EPTC
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PFC initial byte stuffing configuration for encoding
PFC_EACCM
PFC + 0010h
PFC destination/source address
PFC_D/SRC
PFC + 0014h
PFC destination buffer/source operation length
PFC_D/SLEN
PFC + 0018h
PFC slow down rate
PFC_SDRAT
PFC + 001ch
PFC status
PFC_STAT
PFC + 0020h
PFC current source address in decoding mode
PFC_DCSRC
PFC + 0024h
PFC current source address in encoding mode
PFC_ECSRC
PFC + 0028h
PFC current destination address in decoding mode
PFC_DCDES
PFC + 002ch
PFC current destination address in encoding mode
PFC + 0030h
PFC unread source data length in decoding mode
PFC + 0034h
PFC unread source data length in encoding mode
PFC + 0038h
PFC unused write buffer length in decoding mode
PFC_DUDLEN
PFC + 003ch
PFC unused write buffer length in encoding mode
PFC_EUDLEN
PFC + 0040h
PFC decoding protocol
PFC_DPTC
PFC + 0044h
PFC interrupt status
PFC + 0048h
PFC interrupt enable
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PFC + 000ch
PFC_ECDES
PFC_DUSLEN
Re
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PFC_EUSLEN
PFC_INTSTA
PFC_INTEN
Table 35 PFC Registers
PFC+0000h
Bit
15
14
PFC start register
13
Type
Reset
11
10
9
8
7
6
5
4
3
2
1
0
ELAS ELAS DSET
EUPD DUPD
EUPS DUPS NADD DEL/
DF7E
ECLR DCLR
TD
TS
7E
EL
EL
RL
RL
R
ST
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
0
0
0
0
0
0
0
0
0
0
0
0
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Name
12
PFC_START
Start register for PPP framer coprocessor.
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DEL/ST When this bit is enabled, the PFC is started up; otherwise, the DES and DLEN statuses are updated.
NADDR
When NADDR is asserted, PFC updates only DSLEN and bypasses DSRC when updating source or
destination information.
DUPSRL Force an update of the decoding register set for SRC and SLEN. This bit only takes effect when
DEL/ST is enabled. If this bit is disabled, the operation uses the old settings, i.e., CSRC and USLEN.
EUPSRL Force an update of the encoding register set for SRC and SLEN. This bit only takes effect when
DEL/ST is enabled. If this bit is disabled, the operation uses the old settings, i.e., CSRC and USLEN.
DCLR Reset all decoding states and return to the initial state.
ECLR Reset all encoding states and return to the initial state.
DUPDEL Force an update of the decoding register set for DES and DLEN. This bit only takes effect when
DEL/ST is disabled. After asserting this bit, a de-assert should follow immediately (in the next instruction
cycle). Note: The result depends on the ENC bit. Only one of the encoder and decoder parts changes.
EUPDEL Force an update of the encoding register set for DES and DLEN. This bit only takes effect when
DEL/ST is disabled. After asserting this bit, a de-assert should follow immediately (in the next instruction
cycle). Note: The result depends on the ENC bit. Only one of the encoder and decoder parts changes.
DF7E In decoding mode, if PFC starts with DF7E enabled, PFC does nothing until a 0x7e byte is found.
DSET7E
In decoding mode, set 0x7e-found mode.
ELASTS
End the process (append the FCS and flag sequence on last) after source data has run out.
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ELASTD End the process (append the FCS and flag sequence on last) after the destination buffer is full. The
buffer may have a 0- to 4-byte space, depending on byte-stuffing conditions of FCS and the last encoded
character.
PFC+0004h
Bit
15
14
PFC control register
13
12
11
10
PFC_CON
9
Name
7
6
5
4
3
2
1
0
DACF
EACF
EDEL DF32 DPFC
EF32 EPFC
ENC
C
C
R/W R/W R/W R/W R/W R/W R/W R/W
1
0
0
0
0
0
0
0
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Type
Reset
8
Control register for PPP framer coprocessor.
PFC+0008h
Bit
Name
Type
Reset
15
14
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ENC Encode bit. If enabled, this operation is encoding; otherwise the operation is decoding.
EACFC Address and Control Field Compression in encoding mode. This Configuration Option provides a method to
negotiate the compression of the Data Link Layer Address and Control fields. By default, all
implementations MUST transmit frames with Address and Control fields appropriate to the link framing.
When the Address and Control fields are compressed, the Data Link Layer FCS field is calculated based on the
compressed frame, not the original uncompressed frame.
EPFC Protocol Field Compression in encoding mode. PPP Protocol field numbers are chosen such that some
values may be compressed into a single octet form that is clearly distinguishable from the two-octet form.
This Configuration Option is sent to inform the peer that the implementation can receive such single octet
Protocol fields. When a Protocol field is compressed, the Data Link Layer FCS field is calculated on the
compressed frame, not the original uncompressed frame.
EF32 Use FCS32 in encoding mode.
DACFC Use Address and Control Field Compression in decoding mode.
DPFC Use Protocol Field Compression in decoding mode.
DF32 Use FCS32 in decoding mode.
EDEL Escape DEL(0x7f) in encoding mode.
PFC encoding protocol
13
12
11
10
9
8
7
EPTC[15:0]
R/W
0
PFC_EPTC
6
5
4
3
2
1
0
EPTC Encoding protocol. This register contains the protocol field value for encoding a frame.
bits depends on the EPFC bit. An 8-bit protocol uses LSB.
Writing 8 or 16
PFC+000ch
PFC_EACCM
31
30
15
14
PFC byte stuffing configuration for encoding
29
28
27
26
13
12
11
10
25
24
23
22
EACCM[31:16]
R/W
0xffff
9
8
7
6
EACCM[15:0]
R/W
0xffff
21
20
19
18
17
16
5
4
3
2
1
0
EACCM
This byte stuffing control register is for encoding. Each bit of the 32-bit byte stuffing
configuration indicates whether or not to enable the byte stuffing option if that byte value is encountered
during encoding or decoding.
For example, if bit 7 is set to 1 (enabled), then each byte 0x7 encountered is encoded as {0x7d, 0x27}, i.e.
a 0x7d byte followed by the byte (here, 0x7) XOR’ed with 0x20. Similarly, if bit 0 is enabled, {0x7d,
0x20} is decoded into 0x00 by ignoring 0x7d and obtaining 0x20 XOR 0x20 = 0x0.
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Bit
Name
Type
Reset
Bit
Name
Type
Reset
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PFC+0010h
Bit
Name
Type
Reset
Bit
Name
Type
Reset
PFC destination/source address
31
30
29
28
27
26
25
15
14
13
12
11
10
9
24
23
D/SRC[31:16]
R/W
0
8
7
D/SRC[15:0]
R/W
0
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PFC_D/SRC
22
21
20
19
18
6
5
4
3
2
17
16
1
0
Bit
Name
Type
Reset
15
PFC destination/source operation length
14
13
12
11
10
9
8
7
D/SLEN[15:0]
R/W
0
6
PFC_D/SLEN
5
4
3
Re
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PFC+0014h
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D/SRC When DEL/ST is disabled, D/SRC is the destination address to load when UPDEL is enabled.
When DEL/ST is enabled, D/SRC is the source address for PFC operation.
2
1
0
D/SLEN
When DEL/ST is disabled, D/SLEN is the destination buffer length. When DEL/ST is
enabled, D/SLEN is the source length for the PFC operation. Note: Zero length is not allowed in
decoding mode. A zero length when encoding results in padding FCS and 0x7e directly regardless
of whether or not the ELAST bit is asserted.
PFC+0018h
Bit
Name
Type
Reset
15
14
PFC slow down rate
13
12
11
10
9
8
7
6
5
4
3
SDRAT[7:0]
R/W
0
PFC_SDRAT
2
1
0
PFC+001ch
14
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SDRAT Slow down the PFC to prevent too many requests for AHB resources. Each unit increment translates into a
4-cycle delay for each bus access (read or write). The range of SDRAT is from 0 (no delay) to 255
(255*4=1020 cycles’ delay).
PFC return status
Bit
Name
Type
Reset
15
STAT
Current status of PFC. 0000b: OK. 0001b: BUSY. 0010b: write buffer full. 0011b: zero source length
in decoding. 0100b: FCS error in decoding mode. 0101b: not starting with 0x7e byte in decoding mode.
0110b: address or control field error in decoding mode. 0111b:Invalid frame due to 0x7d, 0x7e sequence
occurred. 1000b: RESUME stat, wait for next last or non-last operation.
PFC+0020h
31
30
15
14
12
11
10
9
8
7
6
5
4
3
PFC current source address in decoding
29
28
27
26
25
13
12
11
10
9
MT
K
Bit
Name
Type
Reset
Bit
Name
Type
Reset
13
PFC_STAT
24
23
22
DCSRC[31:16]
RO
0
8
7
6
DCSRC[15:0]
RO
0
2
1
STAT[3:0]
RO
0
0
PFC_DCSRC
21
20
19
18
17
16
5
4
3
2
1
0
DCSRC CSRC is the current source address in the PFC in decoding mode.
PFC+0024h
Bit
31
30
PFC current source address in encoding
29
28
27
26
25
24
23
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22
PFC_ECSRC
21
20
19
18
17
16
MediaTek Inc. Confidential
Name
Type
Reset
Bit
Name
Type
Reset
15
14
13
12
11
10
9
ECSRC[31:16]
RO
0
8
7
ECSRC[15:0]
RO
0
6
5
4
3
Revision 1.0
2
ECSRC CSRC is the current source address in the PFC in encoding mode.
31
30
29
28
27
26
25
15
14
13
12
11
10
9
24
23
22
DCDES[31:16]
RO
0
8
7
6
DCDES[15:0]
RO
0
1
0
PFC_DCDES
21
20
5
4
19
18
17
16
3
2
1
0
fo
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Bit
Name
Type
Reset
Bit
Name
Type
Reset
PFC current destination address in decoding
Re
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PFC+0028h
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MT6228 GSM/GPRS Baseband Processor Data Sheet
DCDES CDES is the current destination address in the PFC in decoding mode.
PFC+002ch
Bit
Name
Type
Reset
Bit
Name
Type
Reset
PFC current destination address in encoding
31
30
29
28
27
26
25
15
14
13
12
11
10
9
24
23
22
ECDES[31:16]
RO
0
8
7
6
ECDES[15:0]
RO
0
PFC_ECDES
21
20
19
18
17
16
5
4
3
2
1
0
ECDES CDES is the current destination address in the PFC in encoding mode.
Bit
Name
Type
Reset
15
14
DUSLEN
15
15
13
14
13
9
8
7
DUSLEN[15:0]
RO
0
6
5
4
3
2
1
0
12
11
10
9
8
7
EUSLEN[15:0]
RO
0
6
5
PFC_EUSLEN
4
3
2
1
0
12
11
10
9
8
7
DUDLEN[15:0]
RO
0
6
5
4
PFC_DUDLEN
3
2
1
0
Unused write buffer space length in decoding mode.
PFC unused destination buffer length in encoding
MT
K
15
10
PFC unused destination buffer length in decoding
PFC+003ch
Bit
Name
Type
Reset
11
Unread source data length in encoding mode.
PFC+0038h
DUDLEN
12
PFC unread source data length in encoding
14
EUSLEN
Bit
Name
Type
Reset
13
PFC_DUSLEN
DUSLEN is the unread source data length in decoding mode.
PFC+0034h
Bit
Name
Type
Reset
PFC unread source data length in decoding
Co
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PFC+0030h
14
13
12
11
10
9
8
7
EUDLEN[15:0]
RO
0
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4
PFC_EUDLEN
3
2
1
0
MediaTek Inc. Confidential
EUDLEN
Unused write buffer space length in encoding mode.
PFC+0040h
Bit
Name
Type
Reset
15
Revision 1.0
PFC decoding protocol
14
13
12
11
10
9
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MT6228 GSM/GPRS Baseband Processor Data Sheet
PFC_DPTC
8
7
DPTC[15:0]
RO
0
6
5
4
3
2
1
0
Writing 8 or 16
PFC+0044h
PFC_INTSTA
Bit
Name
Type
Reset
15
PFC interrupt status
14
13
12
11
10
9
8
7
6
5
4
fo
r
DPTC Decoding protocol. This register contains the protocol field value decoded from a frame.
bits depends on the DPFC bit. An 8-bit protocol uses LSB.
PFC+0048h
Bit
Name
Type
Reset
15
PFC interrupt enable
14
13
12
11
10
9
8
7
6
5
4
2
1
0
INTSTA
RC
0
Bit 1 indicates that PFC
Re
lea
se
INTSTA
Interrupt status. Bit 0 indicates that PFC finished with OK or RESUME state.
failed. Further error information can be obtained from PFC_STAT.
3
3
PFC_INTEN
2
1
0
INTEN
R/W
0
INTEN Interrupt enable control register. When bit 0 is enabled, an interrupt occurs when PFC finishes in the OK or
RESUME state. If bit 1 is enabled, PFC interrupts if an error occurs.
5.4.3
MRU
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When a PPP task wants to transmit a set of raw data through the network, the data must be encoded first (Figure 63).
In process A, the raw data is prefixed with an Address (0xff) and Control (0x03) field* (AC), followed by Protocol
field** (PTC). An FCS is appended***.
A 0x7e byte is then added both at the front and
MT
K
In process B, the data stream resulting from process A is byte-stuffed.
at the end of the byte-stuffed stream.
Figure 63 Basic PFC Flow
* The Control field depends on the DACFC, EACFC, and EACCM bits.
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** The Protocol field depends on the DPTC and EPTC bits.
*** The FCS field depends on the DF32 and EF32 bits.
Figure 64 shows the resulting PPP frame.
Flag
Address
Control
Protocol
Information
Padding
FCS
01111110
11111111
00000011
8/16 bits
*
*
16/32 bits
Flag
01111110
MT
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Figure 64 PPP Frame Structure
Revision 1.0
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6
Multi-Media Subsystem
Revision 1.0
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MT6228 GSM/GPRS Baseband Processor Data Sheet
fo
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MT6228 is a highly integrated Baseband/Multimedia single chip. It integrates several hardware-based multimedia
accelerators to enable rich multimedia application. Hardware accelerators include Image signal processor, Image resizer,
JPEG Codec, MPEG-4 Codec, GIF Decoder, PNG Decoder, 2D graphics engine, TV encoder, and advanced hardware
LCD display controller. A lot of attractive multimedia functions can be realized through above hardware accelerators in
MT6228. The functions include camera function, JPEG/GIF/PNG image playback, MPEG-4 video recording, MPEG-4
video playback, TV out, 2D graphics acceleration, and so on. Image data paths of multi-media sub-system are shown in
Figure 1-1. Hardware data paths and Image DMA are designed to make data transfer more efficient. MT6228 also
incorporates NAND Flash, USB 1.1 OTG Controller and SD/SDIO/MMC/MS/MS Pro Controllers for mass data
transfers and storage.
PNG
Re
lea
se
GIF
Image
Buffer
IPP3
(RGB2YUV)
IPP1
PRZ
(YUV2RGB)
LCD
(Layer 2)
Memory
ISP
Photo
Frame
Buffer
CRZ
OVL
Buffer
File
Buffer
RGB565
Buffer
YUV420
TV
Controller
File
Buffer
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Sensor
MPEG4/JPEG
Codec
DRZ
IPP2
(YUV2RGB)
YUV422
TV
Encoder
Composite Video
LCD
(Layer 1)
TV
2D
Figure 6-1 Image Data Path of Multi-media Sub-system
6.1
LCD Interface
6.1.1
General Description
MT6228 contains a versatile LCD controller, which is optimized for multimedia applications. This controller supports
many types of LCD modules and contains a rich feature set to enhance the functionality. These features are:
Up to 320 x 240 resolution
The internal frame buffer supports 8bpp indexed color, RGB 565, RGB 888 and ARGB 8888 format.
Supports 8-bpp (RGB332), 12-bpp (RGB444), 16-bpp (RGB565), 18-bit (RGB666) and 24-bit (RGB888) LCD
modules.
MT
K
6 Layers Overlay with individual color depth, window size, vertical and horizontal offset, source key, alpha value
and display rotation control(90°,180°, 270°, mirror and mirror then 90°, 180° and 270°)
One color look-up table of 24bpp
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MT6228 GSM/GPRS Baseband Processor Data Sheet
For parallel LCD modules, the LCD controller can reuse external memory interface or use dedicated 8/9/16/18-bit
parallel interface to access them and 8080 type interface is supported. It can transfer the display data from the internal
SRAM or external SRAM/Flash Memory to the off-chip LCD modules.
For serial LCD modules, this interface performs parallel to serial conversion and both 8- and 9- bit format serial
interface is supported. The 8-bit format serial interface uses four pins – LSCE#, LSDA, LSCK and LSA0 – to enter
commands and data. Meanwhile, the 9-bit format serial interface uses three pins – LSCE#, LSDA and LSCK – for the
same purpose. Data read is not available with the serial interface and data entered must be 8 bits.
LSCE0#
LSCE1#
LSDA
LSA0
LSCK
>?A@&@BDC
( & % % % !*)
!*+ ## %
! " #,$ "-% %
132
%
. 0/ % !)
!+
# # %
! "&#$ " % %
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LPCE0#
LPCE1#
LRST#
LRD#
LPA0
LWR#
NLD[17:0]
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Data and command send to LCM are always through the parallel Nandflash/Lcd interface or through serial SPI/LCD
interface. Sending LCM signals through EMI is forbidden, but the pixel data produced by LCD controller can be
dumped to memory through AHB bus.
;
!
" #$ "&% % &
'
!" #$ "&% % &
=<
!
" #$ "&% % &
!" #$ "&% % &
=H
!
" #$ "&% % &
G
!" #$ "&% % &
!*)54768
9*: $ &
E F
Figure 2 LCD Interface Block Diagram
MT
K
Figure 3 shows the timing diagram of this serial interface. When the block is idle, LSCK is forced LOW and LSCE# is
forced HIGH. Once the data register contains data and the interface is enabled, LSCE# is pulled LOW and remain
LOW for the duration of the transmission.
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8-bit Serial Interface
LSCK(SPH=SPO=0)
LSDA
D7
D6
D5
D4
D3
D2
D1
D0
A0
D7
D6
D5
D4
D3
D2
D1
LSCE#
LSA0
LSDA
LSCE#
LSA0
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9-bit Serial Interface
LSCK(SPH=SPO=0)
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MT6228 GSM/GPRS Baseband Processor Data Sheet
D0
LCD = 0x9000_0000
Address
Register Function
LCD + 0000h
LCD Interface Status Register
LCD + 0004h
LCD Interface Interrupt Enable Register
LCD + 0008h
LCD Interface Interrupt Status Register
Re
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Figure 3 Serial LCD Interface Transfer Timing Diagram
LCD + 000ch
LCD Interface Frame Transfer Register
LCD + 0010h
LCD Parallel/Serial LCM Reset Register
LCD + 0014h
LCD Serial Interface Configuration Register
LCD + 0018h
LCD Parallel Interface 0 Configuration Register
Width
Acronym
16
LCD_STA
16
LCD_INTEN
16
LCD_INTSTA
16
LCD_START
16
LCD_RSTB
16
LCD_SCNF
32
LCD_PCNF0
LCD Parallel Interface 1 Configuration Register
32
LCD_PCNF1
LCD + 0020h
LCD Parallel Interface 2 Configuration Register
32
LCD_PCNF2
LCD + 0040h
LCD Main Window Size Register
32
LCD_MWINSIZE
LCD + 0044h
LCD ROI Window Write to Memory Offset Register 32
LCD_WROI_W2MOFS
LCD + 0048h
LCD ROI Window Write to Memory Control
Register
16
LCD_WROI_W2MCON
LCD + 004ch
LCD ROI Window Write to Memory Address
Register
32
LCD_WROI_W2MADD
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LCD + 001ch
LCD + 0050h
LCD ROI Window Control Register
32
LCD_WROICON
LCD + 0054h
LCD ROI Window Offset Register
32
LCD_WROIOFS
LCD + 0058h
LCD ROI Window Command Start Address Register 16
LCD_WROICADD
LCD + 005ch
LCD ROI Window Data Start Address Register
LCD_WROIDADD
16
LCD + 0060h
LCD ROI Window Size Register
32
LCD_WROISIZE
LCD + 0064h
LCD ROI Window Hardware Refresh Register
32
LCD_WROI_HWREF
LCD + 0068h
LCD ROI Window Background Color Register
32
LCD_WROI_BGCLR
LCD + 0070h
LCD Layer 0 Window Control Register
32
LCD_L0WINCON
LCD Layer 0 Source Color Key Register
32
LCD_L0WINSKEY
LCD Layer 0 Window Display Offset Register
32
LCD_L0WINOFS
LCD + 007ch
LCD Layer 0 Window Display Start Address Register 32
LCD_L0WINADD
LCD + 0080h
LCD Layer 0 Window Size
LCD_L0WINSIZE
MT
K
LCD + 0074h
LCD + 0078h
32
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MT6228 GSM/GPRS Baseband Processor Data Sheet
LCD_L1WINCON
LCD + 0090h
LCD Layer 1 Window Control Register
32
LCD + 0094h
LCD Layer 1 Source Color Key Register
32
LCD_L1WINSKEY
LCD + 0098h
LCD Layer 1 Window Display Offset Register
32
LCD_L1WINOFS
LCD + 009ch
LCD Layer 1 Window Display Start Address Register 32
LCD_L1WINADD
LCD + 00a0h
LCD Layer 1 Window Size
LCD_L1WINSIZE
32
LCD Layer 2 Window Control Register
32
LCD_L2WINCON
LCD Layer 2 Source Color Key Register
32
LCD_L2WINSKEY
LCD + 00b8h
LCD Layer 2 Window Display Offset Register
32
LCD_L2WINOFS
LCD + 00bch
LCD Layer 2 Window Display Start Address Register 32
LCD_L2WINADD
LCD + 00c0h
LCD Layer 2 Window Size
32
LCD_L2WINSIZE
LCD + 00d0h
LCD Layer 3 Window Control Register
32
LCD_L3WINCON
LCD + 00d4h
LCD Layer 3 Source Color Key Register
32
LCD_L3WINSKEY
LCD + 00d8h
LCD Layer 3 Window Display Offset Register
32
LCD_L3WINOFS
Re
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fo
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LCD + 00b0h
LCD + 00b4h
LCD + 00dch
LCD Layer 3 Window Display Start Address Register 32
LCD_L3WINADD
LCD + 00e0h
LCD Layer 3 Window Size
32
LCD_L3WINSIZE
LCD + 00f0h
LCD Layer 4 Window Control Register
32
LCD_L4WINCON
LCD + 00f4h
LCD Layer 4 Source Color Key Register
32
LCD_L4WINSKEY
LCD + 00f8h
LCD Layer 4 Window Display Offset Register
32
LCD_L4WINOFS
LCD + 00fch
LCD Layer 4 Window Display Start Address Register 32
LCD_L4WINADD
LCD + 0100h
LCD Layer 4 Window Size
32
LCD_L4WINSIZE
LCD + 0110h
LCD Layer 5 Window Control Register
32
LCD_L5WINCON
LCD Layer 5 Source Color Key Register
32
LCD_L5WINSKEY
LCD Layer 5 Window Display Offset Register
32
LCD_L5WINOFS
LCD + 011ch
LCD Layer 5 Window Display Start Address Register 32
LCD_L5WINADD
LCD + 0120h
LCD Layer 5 Window Size
32
LCD_L5WINSIZE
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LCD + 0114h
LCD + 0118h
LCD + 4000h
LCD Parallel Interface 0 Data
32
LCD_PDAT0
LCD + 4100h
LCD Parallel Interface 0 Command
32
LCD_PCMD0
LCD + 5000h
LCD Parallel Interface 1 Data
32
LCD_PDAT1
LCD + 5100h
LCD Parallel Interface 1 Command
32
LCD_PCMD1
LCD + 6000h
LCD Parallel Interface 2 Data
32
LCD_PDAT2
LCD + 6100h
LCD Parallel Interface 2 Command
32
LCD_PCMD2
LCD + 8000h
LCD Serial Interface 1 Data
16
LCD_SDAT1
LCD + 8100h
LCD Serial Interface 1 Command
16
LCD_SCMD1
LCD Serial Interface 0 Data
16
LCD_SDAT0
LCD Serial Interface 0 Command
16
LCD_SCMD0
LCD + c800h
~ cbfch
LCD Color Palette LUT Register
32
LCD_PAL
LCD + cc00h
~ ccfch
LCD Interface Command/Parameter Register
32
LCD_COMD
MT
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LCD + 9000h
LCD + 9100h
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6.1.2
Table 36 Memory map of LCD InterfaceRegister Definitions
LCD +0000h
Bit
15
LCD Interface Status Register
14
13
12
11
10
9
8
LCD_STA
7
6
5
4
3
2
1
0
CMD_ DATA
CPEN _PEN RUN
D
D
R
R
R
0
0
0
Name
fo
r
Type
Reset
RUN LCD Interface Running Status
DATA_PEND Data Pending Indicator in Hardware Trigger Mode
CMD_PEND
Command Pending Indicator in Hardware Triggered Refresh Mode
15
LCD Interface Interrupt Enable Register
14
13
12
11
10
9
8
Name
Type
Reset
7
6
LCD_INTEN
5
4
3
Re
lea
se
LCD +0004h
Bit
Revision 1.0
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MT6228 GSM/GPRS Baseband Processor Data Sheet
2
1
0
CMD_ DATA
CPL
CPL _CPL
R/W R/W R/W
0
0
0
CPL
LCD Frame Transfer Complete Interrupt Control
DATA_CPL Data Transfer Complete in Hardware Triggered Refresh Mode Interrupt Control
CMD_CPL Command Transfer Complete in Hardware Trigger Refresh Mode Interrupt Control
LCD +0008h
Bit
15
LCD Interface Interrupt Status Register
14
13
12
11
10
9
8
Type
Reset
Co
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Name
7
6
5
4
3
LCD_INTSTA
2
1
0
CMD_ DATA
CPL
CPL _CPL
R
R
R
0
0
0
CPL
LCD Frame Transfer Complete Interrupt
DATA_CPL Data Transfer Complete in Hardware Triggered Refresh Mode Interrupt
CMD_CPL Command Transfer Complete in Hardware Triggered Refresh Mode Interrupt
LCD +000Ch
Bit
15
STAR
Name
T
Type R/W
Reset
0
14
LCD Interface Frame Transfer Register
13
12
11
10
9
8
7
6
LCD_START
5
4
3
2
1
0
START Start Control of LCD Frame Transfer
LCD +0010h
15
14
13
MT
K
Bit
Name
Type
Reset
LCD Parallel/Serial Interface Reset Register
12
11
10
9
8
7
6
5
LCD_RSTB
4
3
2
1
0
RSTB
R/W
1
RSTB Parallel/Serial LCD Module Reset Control
LCD +0014h
Bit
15
Name 26M
14
13M
LCD Serial Interface Configuration Register
13
12
11
10
9
8
CSP1 CSP0
7
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5
LCD _SCNF
4
8/9
3
2
DIV
1
SPH
0
SPO
MediaTek Inc. Confidential
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Clock Polarity Control
Clock Phase Control
Serial Clock Divide Select Bits
8-bit or 9-bit Interface Selection
Serial Interface Chip Select 0 Polarity Control
Serial Interface Chip Select 1 Polarity Control
LCD +0018h
LCD Parallel Interface Configuration Register 0
Bit
Name
Type
31
30
C2WS
R/W
0
Bit
15
14
Name 26M 13M
Type R/W R/W
Reset
0
0
29
28
C2WH
R/W
0
13
12
27
11
26
25
C2RS
R/W
0
10
9
WST
R/W
0
24
23
22
21
20
R/W
0
fo
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SPO
SPH
DIV
8/9
CSP0
CSP1
R/W
0
LCD_PCNF0
19
18
17
16
DW
R/W
0
8
RLT
WST
13M
26M
DW
7
6
5
4
3
Re
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se
Type
Type
Revision 1.0
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MT6228 GSM/GPRS Baseband Processor Data Sheet
2
RLT
R/W
0
1
0
LCD +001Ch
Bit
Name
Type
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Read Latency Time
Write Wait State Time
Enable 13MHz clock gating.
Enable 26MHz clock gating.
Data width of the parallel interface.
00 8-bit.
01 9-bit
10 16-bit
11 18-bit
C2RS Chip Select (LPCE#) to Read Strobe (LRD#) Setup Time
C2WH Chip Select (LPCE#) to Write Strobe (LWR#) Hold Time
C2WS Chip Select (LPCE#) to Write Strobe (LWR#) Setup Time
31
30
C2WS
R/W
0
Bit
15
14
Name 26M 13M
Type R/W R/W
Reset
0
0
RLT
WST
13M
26M
DW
LCD Parallel Interface Configuration Register 1
29
28
C2WH
R/W
0
13
12
27
11
26
25
C2RS
R/W
0
10
9
WST
R/W
0
24
23
8
7
22
21
20
LCD_PCNF1
19
18
17
16
DW
R/W
0
6
5
4
3
2
RLT
R/W
0
1
0
MT
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Read Latency Time
Write Wait State Time
Enable 13MHz clock gating.
Enable 26MHz clock gating.
Data width of the parallel interface.
00 8-bit.
01 9-bit
10 16-bit
11 18-bit
C2RS Chip Select (LPCE#) to Read Strobe (LRD#) Setup Time
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C2WH Chip Select (LPCE#) to Write Strobe (LWR#) Hold Time
C2WS Chip Select (LPCE#) to Write Strobe (LWR#) Setup Time
Bit
Name
Type
LCD Parallel Interface Configuration Register 2
31
30
C2WS
R/W
0
Bit
15
14
Name 26M 13M
Type R/W R/W
Reset
0
0
29
28
C2WH
R/W
0
13
12
27
11
26
25
C2RS
R/W
0
10
9
WST
R/W
0
24
23
22
21
20
8
7
6
5
4
30
15
14
29
28
27
26
25
24
23
DATA[31:16]
R/W
8
7
DATA[15:0]
R/W
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31
LCD Parallel 0 Interface Data
13
12
11
10
9
3
Re
lea
se
Read Latency Time
Write Wait State Time
Enable 13MHz clock gating.
Enable 26MHz clock gating.
Data width of the parallel interface.
00 8-bit.
01 9-bit
10 16-bit
11 18-bit
C2RS Chip Select (LPCE#) to Read Strobe (LRD#) Setup Time
C2WH Chip Select (LPCE#) to Write Strobe (LWR#) Hold Time
C2WS Chip Select (LPCE#) to Write Strobe (LWR#) Setup Time
Bit
Name
Type
Bit
Name
Type
19
18
17
16
DW
R/W
0
RLT
WST
13M
26M
DW
LCD +4000h
LCD_PCNF2
2
RLT
R/W
0
1
0
fo
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LCD +0020h
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LCD_PDAT0
22
21
20
19
18
17
16
6
5
4
3
2
1
0
DATA Writing to LCD+4000 will drive LPA0 low when sending this data out in parallel BANK0, while writing to
LCD+4100 will drive LPA0 high.
LCD +5000h
Bit
Name
Type
Bit
Name
Type
31
30
15
14
LCD Parallel 1 Interface Data
29
28
27
26
25
13
12
11
10
9
24
23
DATA[31:16]
R/W
8
7
DATA[15:0]
R/W
LCD_PDAT1
22
21
20
19
18
17
16
6
5
4
3
2
1
0
DATA Writing to LCD+5000 will drive LPA1 low when sending this data out in parallel BANK1, while writing to
LCD+5100 will drive LPA1 high
LCD Parallel 2 Interface Data
MT
K
LCD +6000h
Bit
Name
Type
Bit
Name
Type
31
30
29
28
27
26
25
15
14
13
12
11
10
9
24
23
DATA[31:16]
R/W
8
7
DATA[15:0]
R/W
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LCD_PDAT2
22
21
20
19
18
17
16
6
5
4
3
2
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MT6228 GSM/GPRS Baseband Processor Data Sheet
DATA Writing to LCD+6000 will drive LPA2 low when sending this data out in parallel BANK2, while writing to
LCD+6100 will drive LPA2 high
Bit
Name
Type
15
14
LCD Serial Interface 1 Data
13
12
11
10
9
8
LCD_SDAT1
7
6
5
4
3
DATA
W
2
1
0
fo
r
LCD
+8000/8100h
DATA Writing to LCD+8000 will drive LSA0 low while sending this data out in serial BANK1, while writing to
LCD+8100 will drive LSA0 high
Bit
Name
Type
15
14
LCD Serial Interface 0 Data
13
12
11
10
9
8
LCD_SDAT0
7
6
5
4
3
DATA
W
Re
lea
se
LCD
+9000/9100h
2
1
0
DATA Writing to LCD+9000 will drive LSA0 low while sending this data out in serial BANK0, while writing to
LCD+9100 will drive LSA0 high
LCD +0040h
31
30
29
28
27
26
25
24
15
14
13
12
11
10
9
8
LCD_MWINSIZE
23
22
7
6
Co
nf
id
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Bit
Name
Type
Bit
Name
Type
Main Window Size Register
21
20
ROW
R/W
5
4
COLUMN
R/W
19
18
17
16
3
2
1
0
COLUMN 10-bit Virtual Image Window Column Size
ROW 10-bit Virtual Image Window Row Size
LCD +0044h
Bit
Name
Type
Bit
Name
Type
31
30
15
14
Region of Interest Window Write to Memory Offset
Register
29
28
27
26
25
24
23
22
13
12
11
10
9
8
7
6
21
20
Y-OFFSET
R/W
5
4
X-OFFSET
R/W
LCD_WROI_W2
MOFS
19
18
17
16
3
2
1
0
This control register is used to specify the offset of the ROI window from the LCD_WROI_W2MADDR when writing
the ROI window’s content to memory.
X-OFFSET the x offset of ROI window in the destination memory.
Y-OFFSET the y offset of ROI window in the destination memory.
Region of Interest Window Write to Memory Control
Register
MT
K
LCD +0048h
Bit
15
14
13
12
11
10
9
8
7
Name
Type
Reset
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6
5
4
LCD_WROI_W2
MOON
3
2
1
0
W2M_
DISC
W2L
FORM
ON
CM
AT
R/W R/W R/W
0
0
0
MediaTek Inc. Confidential
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MT6228 GSM/GPRS Baseband Processor Data Sheet
This control register is effective only when the W2M bit is set in LCD_WROICON register.
Region of Interest Window Write to Memory
Address Register
Bit
Name
Type
Bit
Name
Type
31
30
29
28
27
26
25
15
14
13
12
11
10
9
W2M_ADDR
Write to memory address.
LCD +0050h
22
21
20
19
6
5
4
3
Region of Interest Window Control Register
31
30
EN0 EN1
R/W R/W
15
14
ENC W2M
R/W R/W
29
EN2
R/W
13
28
EN3
R/W
12
27
26
EN4 EN5
R/W R/W
11
10
COMMAND
R/W
25
24
9
8
23
22
7
6
Co
nf
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Bit
Name
Type
Bit
Name
Type
24
23
W2M_ADDR
R/W
8
7
W2M_ADDR
R/W
LCD_WROI_W2
MADD
Re
lea
se
LCD +004Ch
fo
r
W2LCM
Write to LCM simultaneously.
W2M_FORMAT Write to memory format.
0
RGB565
1
RGB888
DISCON
Block Write Enable Control. By setting both DISCON and W2M to 1, the LCD controller will write
out the ROI pixel data as a part of MAIN window, using the width of MAIN window to calculate the write-out address.
If this bit is not set, the ROI window will be written to memory in continuous addresses.
21
20
19
PERIOD
R/W
5
4
3
FORMAT
R/W
18
17
16
2
1
0
LCD_WROICO
N
18
17
16
2
1
0
MT
K
FORMAT LCD Module Data Format
Bit 0 : in BGR sequence, otherwise in RGB sequence.
Bit 1 : LSB first, otherwise MSB first.
Bit 2 : padding bits on MSBs, otherwise on LSBs.
Bit 5-3 : 000 for RGB332, 001 for RGB444, 010 for RGB565, 011 for RGB666, 100 for RGB888.
Bit 7-6 : 00 for 8-bit interface, 01 for 16-bit interface, 10 for 9-bit interface, 11 for 18-bit interface.
Note: When the interface is configured as 9 bit or 18 bit, the field of bit5-2 is ignored.
00000000
8bit
1cycle/1pixel
RGB3.3.2
RRRGGGBB
00000001
1cycle/1pixel
RGB3.3.2
BBGGGRRR
00001000
3cycle/2pixel
RGB4.4.4
RRRRGGGG
BBBBRRRR
GGGGBBBB
00001011
3cycle/2pixel
RGB4.4.4
GGGGRRRR
RRRRBBBB
BBBBGGGG
00010000
2cycle/1pixel
RGB5.6.5
RRRRRGGG
GGGBBBBB
00010011
2cycle/1pixel
RGB5.6.5
GGGRRRRR
BBBBBGGG
00011000
3cycle/1pixel
RGB6.6.6
RRRRRRXX
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GGGGGGXX
BBBBBBXX
RGB6.6.6
00100000
3cycle/1pixel
RGB8.8.8
2cycle/1pixel
RGB6.6.6
2cycle/1pixel
RGB6.6.6
1cycle/2pixel
1cycle/2pixel
1cycle/2pixel
1cycle/2pixel
RGB3.3.2
RGB3.3.2
RGB3.3.2
RGB3.3.2
10011000
9bit
10011011
01000000
01000010
01000001
01000011
16bit
01011111
01011000
01011011
01100000
01100011
RGB4.4.4
RGB4.4.4
RGB4.4.4
RGB4.4.4
RGB5.6.5
RGB5.6.5
RGB6.6.6
18bit
3cycle/2pixel
RGB6.6.6
3cycle/2pixel
RGB6.6.6
3cycle/2pixel
RGB6.6.6
3cycle/2pixel
RGB8.8.8
3cycle/2pixel
RGB8.8.8
1cycle/1pixel
1cycle/1pixel
RGB6.6.6
RGB6.6.6
XXXXRRRRGGGGBBBB
XXXXBBBBGGGGRRRR
RRRRGGGGBBBBXXXX
BBBBGGGGRRRRXXXX
RRRRRGGGGGGBBBBB
BBBBBGGGGGGRRRRR
XXXXRRRRRRGGGGGG
XXXXBBBBBBRRRRRR
XXXXGGGGGGBBBBBB
XXXXGGGGGGRRRRRR
XXXXRRRRRRBBBBBB
XXXXBBBBBBGGGGGG
RRRRRRGGGGGGXXXX
BBBBBBRRRRRRXXXX
GGGGGGBBBBBBXXXX
GGGGGGRRRRRRXXXX
RRRRRRBBBBBBXXXX
BBBBBBGGGGGGXXXX
RRRRRRRRGGGGGGGG
BBBBBBBBRRRRRRRR
GGGGGGGGBBBBBBBB
GGGGGGGGRRRRRRRR
RRRRRRRRBBBBBBBB
BBBBBBBBRRRRRRRR
RRRRRRGGGGGGBBBBBB
BBBBBBGGGGGGRRRRRR
MT
K
11011000
11011001
1cycle/1pixel
1cycle/1pixel
1cycle/1pixel
1cycle/1pixel
1cycle/1pixel
1cycle/1pixel
3cycle/2pixel
Co
nf
id
en
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01001100
01001101
01001000
01001001
01010000
01010001
01011100
XXRRRRRR
XXGGGGGG
XXBBBBBB
RRRRRRRR
GGGGGGGG
BBBBBBBB
RRRRRRGGG
GGGBBBBBB
GGGRRRRRR
BBBBBBGGG
RRRGGGBBRRRGGGBB
RRRGGGBBRRRGGGBB
BBGGGRRRBBGGGRRR
BBGGGRRRBBGGGRRR
fo
r
3cycle/1pixel
Re
lea
se
00011100
Revision 1.0
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MT6228 GSM/GPRS Baseband Processor Data Sheet
COMMAND Number of Commands to be sent to LCD module. Maximum is 63.
W2M Enable Data Address Increasing After Each Data Transfer
ENC Command Transfer Enable Control
PERIOD
Waiting period between two consecutive transfers, effective for both data and command.
ENn
Layer Window Enable Control
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Bit
Name
Type
Bit
Name
Type
Region of Interest Window Offset Register
31
30
29
28
27
26
25
24
23
22
15
14
13
12
11
10
9
8
7
6
LCD_WROIOFS
21
20
Y-OFFSET
R/W
5
4
X-OFFSET
R/W
X-OFFSET ROI Window Column Offset
Y-OFFSET ROI Window Row Offset
3
2
14
13
12
11
10
9
8
7
ADDR
R/W
6
5
4
3
2
Re
lea
se
15
18
17
16
1
0
Region of Interest Window Command Start Address LCD_WROICAD
Register
D
LCD +0058h
Bit
Name
Type
19
fo
r
LCD +0054h
Revision 1.0
Ko
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MT6228 GSM/GPRS Baseband Processor Data Sheet
1
0
ADDR ROI Window Command Address. Only writing to LCD modules is allowed.
Region of Interest Window Data Start Address
Register
LCD +005Ch
Bit
Name
Type
15
14
13
12
11
10
9
8
7
ADDR
R/W
6
5
LCD_WROIDAD
D
4
3
2
1
0
ADDR ROI Window Data Address Only writing to LCD modules is allowed.
Bit
Name
Type
Bit
Name
Type
31
30
15
14
Region of Interest Window Size Register
29
28
27
26
25
24
23
22
13
12
11
10
9
8
7
6
Co
nf
id
en
tia
l
LCD +0060h
LCD_WROISIZE
21
20
ROW
R/W
5
4
COLUMN
R/W
19
18
17
16
3
2
1
0
COLUMN ROI Window Column Size (width)
ROW ROI Window Row Size (height)
LCD +0064h
Bit
31
30
Region of Interest Window Hardware Refresh
Register
29
28
27
26
EN1
EN2
EN3
EN4
EN5
Type R/W
Reset
0
Bit
15
IMGD
Name MA_S
EL0
Type R/W
Reset
0
R/W
0
14
IMGD
MA_S
EL1
R/W
0
R/W
0
13
IMGD
MA_S
EL2
R/W
0
R/W
0
12
IMGD
MA_S
EL3
R/W
0
R/W
0
11
IMGD
MA_S
EL4
R/W
0
R/W
0
10
IMGD
MA_S
EL5
R/W
0
MT
K
Name EN0
25
24
9
8
LCD_WROI_HW
REF
23
22
21
20
19
18
IMGD IMGD IMGD IMGD IMGD IMGD
MA0 MA1 MA2 MA3 MA4 MA5
R/W R/W R/W R/W R/W R/W
0
0
0
0
0
0
7
6
5
4
3
2
17
16
1
0
HWE
N
HWR
EF
R/W
0
R/W
0
ENn
Enable layer n source address from Image_DMA.
IMGDMAn Enable layer n source data from Image_DMA.
IMGDMA_SELnSelect layer n read from Image_DMA0 or Image_DMA1.
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0 Image_DMA0.
1 Image_DMA1
HWEN Enable hardware triggered LCD fresh.
HWREF
Starting the hardware triggered LCD frame transfer.
31
30
29
15
14
13
28
27
12
11
GREEN[7:0]
R/W
1111_1111
26
25
24
23
22
21
10
9
8
7
6
5
20
19
RED[7:0]
R/W
1111_1111
4
3
BLUE[7:0]
R/W
1111_1111
18
17
fo
r
Bit
Name
Type
Reset
Bit
Name
Type
Reset
LCD_WROI_BG
CLR
Region of Interest Background Color Register
2
Re
lea
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LCD +0068h
Ko
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MT6228 GSM/GPRS Baseband Processor Data Sheet
1
16
0
RED Red component of ROI window’s background color
GREEN Green component of ROI window’s background color
BLUE Blue component of ROI window’s background color
LCD +0070h
Bit
Name
Type
Bit
31
30
14
KEYE
Name SRC
N
Type R/W R/W
29
28
27
26
25
24
13
12
11
10
9
8
OPAE
N
R/W
ROTATE
CLRDPT
R/W
R/W
23
22
21
20
19
18
17
7
6
5
4
3
2
1
16
SWP
R/W
0
OPA
R/W
Co
nf
id
en
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15
LCD_L0WINCO
N
Layer 0 Window Control Register
MT
K
OPA Opacity value, used as constant alpha value.
OPAEN Opacity enabled
CLRDPT Color format
00 8bpp indexed color.
01 RGB 565
10 ARGB 8888
11 RGB 888
ROTATE Rotation Configuration
000 0 degree rotation
001 90 degree rotation anti-counterclockwise
010 180 degree rotation anti-counterclockwise
011 270 degree rotation anti-counterclockwise
100 Horizontal flip
101 Horizontal flip then 90 degree rotation anti-counterclockwise
110 Horizontal flip then 180 degree rotation anti-counterclockwise
111 Horizontal flip then 270 degree rotation anti-counterclockwise
KEYEN Source Key Enable Control
SRC Disable auto-increment of the source pixel address
SWP Swap high byte and low byte of pixel data
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LCD +0074h
31
30
29
28
27
26
15
14
13
12
11
10
24
23
22
SRCKEY[31:16]
R/W
9
8
7
6
SRCKEY[15:0]
R/W
20
19
18
5
4
3
2
31
30
29
28
27
26
25
24
15
14
13
12
11
10
9
8
LCD+007Ch
23
22
7
6
21
20
Y-OFFSET
R/W
5
4
X-OFFSET
R/W
19
3
29
28
27
26
25
15
14
13
12
11
10
9
24
23
ADDR
R/W
8
7
ADDR
R/W
Co
nf
id
en
tia
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30
16
1
0
18
17
16
2
1
0
LCD_L0WINAD
D
Layer 0 Window Display Start Address Register
31
17
LCD_L0WINOF
S
Layer 0 Window Display Offset Register
Y-OFFSET Layer 0 Window Row Offset
X-OFFSET Layer 0 Window Column Offset
Bit
Name
Type
Bit
Name
Type
21
Transparent color key of the source image.
LCD +0078h
Bit
Name
Type
Bit
Name
Type
25
fo
r
SRCKEY
LCD_L0WINSK
EY
Layer 0 Source Color Key Register
Re
lea
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Bit
Name
Type
Bit
Name
Type
Revision 1.0
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MT6228 GSM/GPRS Baseband Processor Data Sheet
22
21
20
19
18
17
16
6
5
4
3
2
1
0
ADDR Layer 0 Window Data Address
LCD +0080h
Bit
Name
Type
Bit
Name
Type
31
30
15
14
LCD_L0WINSIZ
E
Layer 0 Window Size
29
28
27
26
25
24
23
22
13
12
11
10
9
8
7
6
21
20
ROW
R/W
5
4
COLUMN
R/W
19
18
17
16
3
2
1
0
ROW Layer 0 Window Row Size
COLUMN Layer 0 Window Column Size
LCD +0090h
31
30
29
MT
K
Bit
Name
Type
Bit
15
14
KEYE
N
R/W R/W
Name SRC
Type
LCD_L1WINCO
N
Layer 1 Window Control Register
13
28
27
26
25
24
23
22
21
20
19
18
17
12
11
10
9
8
OPAE
N
R/W
7
6
5
4
3
2
1
ROTATE
CLRDPT
R/W
R/W
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16
SWP
R/W
0
OPA
R/W
MediaTek Inc. Confidential
31
30
29
28
27
26
15
14
13
12
11
10
SRCKEY
25
24
23
22
SRCKEY[31:16]
R/W
9
8
7
6
SRCKEY[15:0]
R/W
21
20
19
18
17
16
5
4
3
2
1
0
Transparent color key of the source image.
LCD +0098h
Bit
Name
Type
Bit
Name
Type
LCD_L1WINSK
EY
Layer 1 Source Color Key Register
Co
nf
id
en
tia
l
Bit
Name
Type
Bit
Name
Type
Re
lea
se
LCD +0094h
fo
r
OPA Opacity value, used as constant alpha value.
OPAEN Opacity enabled
CLRDPT Color format
00 8bpp indexed color.
01 RGB 565
10 ARGB 8888
11 RGB 888
ROTATE Rotation Configuration
000 0 degree rotation
001 90 degree rotation anti-counterclockwise
010 180 degree rotation anti-counterclockwise
011 270 degree rotation anti-counterclockwise
100 Horizontal flip
101 Horizontal flip then 90 degree rotation anti-counterclockwise
110 Horizontal flip then 180 degree rotation anti-counterclockwise
111 Horizontal flip then 270 degree rotation anti-counterclockwise
KEYEN Source Key Enable Control
SRC Disable auto-increment of the source pixel address
SWP Swap high byte and low byte of pixel data
Revision 1.0
Ko
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MT6228 GSM/GPRS Baseband Processor Data Sheet
31
30
15
14
LCD_L1WINOF
S
Layer 1 Window Display Offset Register
29
28
27
26
25
24
23
22
13
12
11
10
9
8
7
6
21
20
Y-OFFSET
R/W
5
4
X-OFFSET
R/W
19
18
17
16
3
2
1
0
Y-OFFSET Layer 1 Window Row Offset
X-OFFSET Layer 1 Window Column Offset
LCD+009Ch
31
30
29
28
27
26
25
15
14
13
12
11
10
9
MT
K
Bit
Name
Type
Bit
Name
Type
LCD_L1WINAD
D
Layer 1 Window Display Start Address Register
24
23
ADDR
R/W
8
7
ADDR
R/W
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21
20
19
18
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16
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5
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Revision 1.0
ADDR Layer 1 Window Data Address
Bit
Name
Type
Bit
Name
Type
LCD_L1WINSIZ
E
Layer 1 Window Size
31
30
29
28
27
26
25
24
23
22
15
14
13
12
11
10
9
8
7
6
21
20
ROW
R/W
5
4
COLUMN
R/W
ROW Layer 1 Window Row Size
COLUMN Layer 1 Window Column Size
Bit
Name
Type
Bit
31
3
2
14
KEYE
Name SRC
N
Type R/W R/W
29
28
27
26
25
24
13
12
11
10
9
8
OPAE
N
R/W
ROTATE
CLRDPT
R/W
R/W
17
16
1
0
LCD_L2WINCO
N
Layer 2 Window Control Register
30
15
18
Re
lea
se
LCD +00B0h
19
fo
r
LCD +00A0h
Ko
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MT6228 GSM/GPRS Baseband Processor Data Sheet
23
22
21
20
19
18
17
7
6
5
4
3
2
1
16
SWP
R/W
0
OPA
R/W
LCD +00B4h
LCD_L2WINSK
EY
Layer 2 Source Color Key Register
31
30
29
28
27
26
15
14
13
12
11
10
MT
K
Bit
Name
Type
Bit
Name
Type
Co
nf
id
en
tia
l
OPA Opacity value, used as constant alpha value.
OPAEN Opacity enabled
CLRDPT Color format
00 8bpp indexed color.
01 RGB 565
10 ARGB 8888
11 RGB 888
ROTATE Rotation Configuration
000 0 degree rotation
001 90 degree rotation anti-counterclockwise
010 180 degree rotation anti-counterclockwise
011 270 degree rotation anti-counterclockwise
100 Horizontal flip
101 Horizontal flip then 90 degree rotation anti-counterclockwise
110 Horizontal flip then 180 degree rotation anti-counterclockwise
111 Horizontal flip then 270 degree rotation anti-counterclockwise
KEYEN Source Key Enable Control
SRC Disable auto-increment of the source pixel address
SWP Swap high byte and low byte of pixel data
25
24
23
22
SRCKEY[31:16]
R/W
9
8
7
6
SRCKEY[15:0]
R/W
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Transparent color key of the source image.
LCD +00B8h
Bit
Name
Type
Bit
Name
Type
LCD_L2WINOF
S
Layer 2 Window Display Offset Register
31
30
29
28
27
26
25
24
23
22
15
14
13
12
11
10
9
8
7
6
21
20
Y-OFFSET
R/W
5
4
X-OFFSET
R/W
Y-OFFSET Layer 2 Window Row Offset
X-OFFSET Layer 2 Window Column Offset
Bit
Name
Type
Bit
Name
Type
31
30
29
28
27
26
25
15
14
13
12
11
10
9
LCD +00C0h
24
23
ADDR
R/W
8
7
ADDR
R/W
30
15
14
2
29
28
27
26
13
12
11
25
10
17
16
1
0
LCD_L2WINAD
D
22
21
20
19
18
17
16
6
5
4
3
2
1
0
LCD_L2WINSIZ
E
Layer 2 Window Size
24
23
Co
nf
id
en
tia
l
31
3
Layer 2 Window Display Start Address Register
ADDR Layer 1 Window Data Address
Bit
Name
Type
Bit
Name
Type
18
Re
lea
se
LCD+00BCh
19
fo
r
SRCKEY
Revision 1.0
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MT6228 GSM/GPRS Baseband Processor Data Sheet
9
8
7
22
6
21
20
ROW
R/W
5
4
COLUMN
R/W
19
18
17
16
3
2
1
0
ROW Layer 2 Window Row Size
COLUMN Layer 2 Window Column Size
LCD +00D0h
Bit
Name
Type
Bit
31
15
30
14
KEYE
Name SRC
N
Type R/W R/W
LCD_L3WINCO
N
Layer 3 Window Control Register
29
28
27
26
25
24
23
22
21
20
19
18
17
13
12
11
10
9
8
OPAE
N
R/W
7
6
5
4
3
2
1
ROTATE
CLRDPT
R/W
R/W
16
SWP
R/W
0
OPA
R/W
MT
K
OPA Opacity value, used as constant alpha value.
OPAEN Opacity enabled
CLRDPT Color format
00 8bpp indexed color.
01 RGB 565
10 ARGB 8888
11 RGB 888
ROTATE Rotation Configuration
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31
30
29
28
27
26
15
14
13
12
11
10
SRCKEY
24
23
22
SRCKEY[31:16]
R/W
9
8
7
6
SRCKEY[15:0]
R/W
Transparent color key of the source image.
LCD +00D8h
Bit
Name
Type
Bit
Name
Type
25
31
30
15
14
21
20
19
18
17
16
5
4
3
2
1
0
LCD_L3WINOF
S
Layer 3 Window Display Offset Register
29
28
27
26
25
24
23
Co
nf
id
en
tia
l
Bit
Name
Type
Bit
Name
Type
LCD_L3WINSK
EY
Layer 3 Source Color Key Register
Re
lea
se
LCD +00D4h
fo
r
000 0 degree rotation
001 90 degree rotation anti-counterclockwise
010 180 degree rotation anti-counterclockwise
011 270 degree rotation anti-counterclockwise
100 Horizontal flip
101 Horizontal flip then 90 degree rotation anti-counterclockwise
110 Horizontal flip then 180 degree rotation anti-counterclockwise
111 Horizontal flip then 270 degree rotation anti-counterclockwise
KEYEN Source Key Enable Control
SRC Disable auto-increment of the source pixel address
SWP Swap high byte and low byte of pixel data
13
12
11
10
9
8
7
Revision 1.0
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MT6228 GSM/GPRS Baseband Processor Data Sheet
22
6
21
20
Y-OFFSET
R/W
5
4
X-OFFSET
R/W
19
18
17
16
3
2
1
0
Y-OFFSET Layer 3 Window Row Offset
X-OFFSET Layer 3 Window Column Offset
LCD+00DCh
Bit
Name
Type
Bit
Name
Type
31
30
15
14
LCD_L3WINAD
D
Layer 3 Window Display Start Address Register
29
28
27
26
25
13
12
11
10
9
24
23
ADDR
R/W
8
7
ADDR
R/W
22
21
20
19
18
17
16
6
5
4
3
2
1
0
ADDR Layer 3 Window Data Address
Bit
Name
Type
Bit
Name
Type
LCD_L3WINSIZ
E
Layer 3 Window Size
MT
K
LCD +00E0h
31
30
29
28
27
26
25
24
23
22
15
14
13
12
11
10
9
8
7
6
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21
20
ROW
R/W
5
4
COLUMN
R/W
19
18
17
16
3
2
1
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MediaTek Inc. Confidential
Revision 1.0
ROW Layer 3 Window Row Size
COLUMN
Layer 3 Window Column Size
Bit
Name
Type
Bit
31
30
15
LCD_L4WINCO
N
Layer 4 Window Control Register
14
KEYE
Name SRC
N
Type R/W R/W
29
28
27
26
25
24
23
22
21
20
19
18
13
12
11
10
9
8
OPAE
N
R/W
7
6
5
4
3
2
ROTATE
CLRDPT
R/W
R/W
17
1
fo
r
LCD +00F0h
Ko
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MT6228 GSM/GPRS Baseband Processor Data Sheet
16
SWP
R/W
0
OPA
R/W
LCD +00F4h
Bit
Name
Type
Bit
Name
Type
31
30
15
14
SRCKEY
Co
nf
id
en
tia
l
Re
lea
se
OPA Opacity value, used as constant alpha value.
OPAEN Opacity enabled
CLRDPT Color format
00 8bpp indexed color.
01 RGB 565
10 ARGB 8888
11 RGB 888
ROTATE Rotation Configuration
000 0 degree rotation
001 90 degree rotation anti-counterclockwise
010 180 degree rotation anti-counterclockwise
011 270 degree rotation anti-counterclockwise
100 Horizontal flip
101 Horizontal flip then 90 degree rotation anti-counterclockwise
110 Horizontal flip then 180 degree rotation anti-counterclockwise
111 Horizontal flip then 270 degree rotation anti-counterclockwise
KEYEN Source Key Enable Control
SRC Disable auto-increment of the source pixel address
SWP Swap high byte and low byte of pixel data
29
28
27
26
13
12
11
10
25
24
23
22
SRCKEY[31:16]
R/W
9
8
7
6
SRCKEY[15:0]
R/W
21
20
19
18
17
16
5
4
3
2
1
0
Transparent color key of the source image.
LCD_L4WINOF
S
Layer 4 Window Display Offset Register
MT
K
LCD +00F8h
Bit
Name
Type
Bit
Name
Type
LCD_L4WINSK
EY
Layer 4 Source Color Key Register
31
30
29
28
27
26
25
24
23
22
15
14
13
12
11
10
9
8
7
6
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21
20
Y-OFFSET
R/W
5
4
X-OFFSET
R/W
19
18
17
16
3
2
1
0
MediaTek Inc. Confidential
Revision 1.0
Y-OFFSET Layer 4 Window Row Offset
X-OFFSET Layer 4 Window Column Offset
Bit
Name
Type
Bit
Name
Type
LCD_L4WINAD
D
Layer 4 Window Display Start Address Register
31
30
29
28
27
26
25
15
14
13
12
11
10
9
24
23
ADDR
R/W
8
7
ADDR
R/W
22
21
20
19
18
6
5
4
3
2
ADDR Layer 4 Window Data Address
Bit
Name
Type
Bit
Name
Type
31
30
29
28
27
26
25
24
15
14
13
12
11
10
9
8
ROW Layer 4 Window Row Size
COLUMN
Layer 4 Window Column Size
Bit
Name
Type
Bit
31
15
30
23
22
7
6
21
20
ROW
R/W
5
4
COLUMN
R/W
14
KEYE
Name SRC
N
Type R/W R/W
1
0
19
18
17
16
3
2
1
0
LCD_L5WINCO
N
Layer 5 Window Control Register
29
28
27
26
25
24
23
22
21
20
19
18
17
13
12
11
10
9
8
OPAE
N
R/W
7
6
5
4
3
2
1
Co
nf
id
en
tia
l
LCD +0110h
16
LCD_L4WINSIZ
E
Layer 4 Window Size
Re
lea
se
LCD +0100h
17
fo
r
LCD+00FCh
Ko
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MT6228 GSM/GPRS Baseband Processor Data Sheet
ROTATE
CLRDPT
R/W
R/W
16
SWP
R/W
0
OPA
R/W
MT
K
OPA Opacity value, used as constant alpha value.
OPAEN Opacity enabled
CLRDPT Color format
00 8bpp indexed color.
01 RGB 565
10 ARGB 8888
11 RGB 888
ROTATE Rotation Configuration
000 0 degree rotation
001 90 degree rotation anti-counterclockwise
010 180 degree rotation anti-counterclockwise
011 270 degree rotation anti-counterclockwise
100 Horizontal flip
101 Horizontal flip then 90 degree rotation anti-counterclockwise
110 Horizontal flip then 180 degree rotation anti-counterclockwise
111 Horizontal flip then 270 degree rotation anti-counterclockwise
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Revision 1.0
KEYEN Source Key Enable Control
SRC Disable auto-increment of the source pixel address
SWP Swap high byte and low byte of pixel data
31
30
29
28
27
26
15
14
13
12
11
10
SRCKEY
24
23
22
SRCKEY[31:16]
R/W
9
8
7
6
SRCKEY[15:0]
R/W
20
19
18
5
4
3
2
31
30
29
28
27
26
25
24
15
14
13
12
11
10
9
8
31
30
15
14
22
7
6
21
20
Y-OFFSET
R/W
5
4
X-OFFSET
R/W
29
28
27
26
25
13
12
11
10
9
24
23
ADDR
R/W
8
7
ADDR
R/W
16
1
0
19
18
17
16
3
2
1
0
LCD_L5WINAD
D
Layer 5 Window Display Start Address Register
Co
nf
id
en
tia
l
LCD+011Ch
23
17
LCD_L5WINOF
S
Layer 5 Window Display Offset Register
Y-OFFSET Layer 5 Window Row Offset
X-OFFSET Layer 5 Window Column Offset
Bit
Name
Type
Bit
Name
Type
21
Transparent color key of the source image.
LCD +0118h
Bit
Name
Type
Bit
Name
Type
25
Re
lea
se
Bit
Name
Type
Bit
Name
Type
LCD_L5WINSK
EY
Layer 5 Source Color Key Register
fo
r
LCD +0114h
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MT6228 GSM/GPRS Baseband Processor Data Sheet
22
21
20
19
18
17
16
6
5
4
3
2
1
0
ADDR Layer 5 Window Data Address
LCD +0120h
Bit
Name
Type
Bit
Name
Type
31
30
15
14
LCD_L5WINSIZ
E
Layer 5 Window Size
29
28
27
26
25
24
23
22
13
12
11
10
9
8
7
6
21
20
ROW
R/W
5
4
COLUMN
R/W
19
18
17
16
3
2
1
0
ROW Layer 5 Window Row Size
COLUMNLayer 5 Window Column Size
MT
K
LCD
+C800h~CBFCh
Bit
Name
Type
31
30
29
LCD Interface Color Palette LUT Registers
28
27
26
25
24
23
22
21
20
LCD_PAL
19
18
17
16
LUT
R/W
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Bit
Name
Type
15
14
13
LUT
These Bits Set LUT Data in RGB565 Format
11
10
9
8
7
5
4
3
2
30
LCD Interface Command/Parameter Registers
29
28
27
26
25
24
23
Name
22
21
20
6
5
4
C0
15
14
13
12
11
10
9
R/W
8
7
COMM[15:0]
R/W
1
0
LCD_COMD
19
18
17
16
COMM[17:16
]
R/W
1
0
fo
r
31
Type
Bit
Name
Type
6
LUT
R/W
LCD
+CC00h~CCFC
Bit
12
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3
2
6.2
NAND FLASH interface
6.2.1
General description
MT6228 provides NAND flash interface.
The NAND FLASH interface support features as follows:
Re
lea
se
COMM Command Data and Parameter Data for LCD Module
C0
Write to ROI Command Address if C0 = 1, otherwise write to ROI Data Address
ECC (Hamming code) acceleration capable of one-bit error correction or two bits error detection.
Co
nf
id
en
tia
l
Programmable ECC block size. Support 1, 2 or 4 ECC block within a page.
Word/byte access through APB bus.
Direct Memory Access for massive data transfer.
Latch sensitive interrupt to indicate ready state for read, program, erase operation and error report.
Programmable wait states, command/address setup and hold time, read enable hold time, and write enable
recovery time.
Support page size: 512(528) bytes and 2048(2112) bytes.
Support 2 chip select for NAND flash parts.
Support 8/16 bits I/O interface.
MT
K
The NFI core can automatically generate ECC parity bits when programming or reading the device. If the user approves
the way it stores the parity bits in the spare area for each page, the AUTOECC mode can be used. Otherwise, the user
can prepare the data (may contains operating system information or ECC parity bits) for the spare area with another
arrangement. In the former case, the core can check the parity bits when reading from the device. The ECC module
features the hamming code, which is capable of correcting one bit error or detecting two bits error within one ECC
block.
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6.2.2
Register definition
NFI+0000h
Bit
Name
Type
Reset
Revision 1.0
15
NAND flash access control register
14
13
12
11
10
9
C2R
R/W
0
8
7
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MT6228 GSM/GPRS Baseband Processor Data Sheet
NFI_ACCCON
6
5
W2R
R/W
0
4
3
WH
R/W
0
2
WST
R/W
0
1
0
RLT
R/W
0
RLT
WST
Re
lea
se
WH
The field represents the minimum required time from NCEB low to NREB low.
The field represents the minimum required time from NWEB high to NREB low. It’s in unit of 2T. So the
actual time ranges from 2T to 8T in step of 2T.
Write-enable hold-time.
The field specifies the hold time of NALE, NCLE, NCEB signals relative to the rising edge of NWEB. This
field is associated with WST to expand the write cycle time, and is associated with RLT to expand the read
cycle time.
Read Latency Time
The field specifies how many wait states to be inserted to meet the requirement of the read access time for the
device.
00 No wait state.
01 1T wait state.
10 2T wait state.
11 3T wait state.
Write Wait State
The field specifies the wait states to be inserted to meet the requirement of the pulse width of the NWEB
signal.
00 No wait state.
01 1T wait state.
10 2T wait state.
11 3T wait state.
NFI +0004h
Bit
Name
Type
Reset
15
Co
nf
id
en
tia
l
C2R
W2R
fo
r
This is the timing access control register for the NAND FLASH interface. In order to accommodate operations for
different system clock frequency ranges from 13MHz to 52MHz, wait states and setup/hold time margin can be
configured in this register.
NFI page format control register
14
13
12
11
10
9
8
B16E
N
R/W
0
7
NFI_PAGEFMT
6
5
4
ECCBLKSIZE
R/W
0
3
2
ADRM
ODE
R/W
0
1
0
PSIZE
R/W
0
This register manages the page format of the device. It includes the bus width selection, the page size, the associated
address format, and the ECC block size.
MT
K
B16EN 16 bits I/O bus interface enable.
ECCBLKSIZE ECC block size.
This field represents the size of one ECC block. The hardware-fuelled ECC generation provides 2 or 4 blocks
within a single page.
0 ECC block size: 128 bytes. Used for devices with page size equal to 512 bytes.
1 ECC block size: 256 bytes. Used for devices with page size equal to 512 bytes.
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MT6228 GSM/GPRS Baseband Processor Data Sheet
2
fo
r
ECC block size: 512 bytes. Used for devices with page size equal to 512 (1 ECC block) or 2048 bytes (4
ECC blocks).
3 ECC block size: 1048 bytes. Used for devices with page size equal to 2048 bytes.
4~ Reserved.
ADRMODE Address mode. This field specifies the input address format.
0 Normal input address mode, in which the half page identifier is not specified in the address assignment
but in the command set. As in Table 37, A7 to A0 identifies the byte address within half a page, A12 to A9
specifies the page address within a block, and other bits specify the block address. The mode is used
mostly for the device with 512 bytes page size.
1 Large size input address mode, in which all address information is specified in the address assignment
rather than in the command set. As in Table 38, A11 to A0 identifies the byte address within a page. The
mode is used for the device with 2048 bytes page size and 8bits I/O interface.
Large size input address mode. As in Table 38, A10 to A0 identifies the column address within a page.
The mode is used for the device with 2048 byte page size and 16bits I/O interface.
NLD7
A7
First cycle
Second cycle A16
NLD6
A6
A15
Re
lea
se
2
NLD5
A5
A14
NLD4
A4
A13
NLD3
A3
A12
NLD2
A2
A11
NLD1
A1
A10
NLD0
A0
A9
NLD1
A1
A9
NLD0
A0
A8
Table 37 Page address assignment of the first type (ADRMODE = 0)
NLD7
A7
First cycle
Second cycle 0
NLD6
A6
0
NLD5
A5
0
NLD4
A4
0
NLD3
A3
A11
NLD2
A2
A10
Table 38 Page address assignment of the second type (ADRMODE = 1 or 2)
NFI +0008h
Bit
Name
Type
Reset
15
Co
nf
id
en
tia
l
PSIZE Page Size.
The field specifies the size of one page for the device. Two most widely used page size are supported.
0 The page size is 512 bytes or 528 bytes (including 512 bytes data area and 16 bytes spare area).
1 The page size is 2048 bytes or 2112 bytes (including 2048 bytes data area and 64 bytes spare area).
2~ Reserved.
Operation control register
14
13
12
NOB
W/R
0
11
10
9
8
SRD
WO
0
7
NFI_OPCON
6
5
4
EWR ERD
WO WO
0
0
3
2
1
0
BWR BRD
R/W R/W
0
0
This register controls the burst mode and the single of the data access. In burst mode, the core supposes there are one or
more than one page of data to be accessed. On the contrary, in single mode, the core supposes there are only less than 4
bytes of data to be accessed.
Burst read mode. Setting this field to be logic-1 enables the data read operation. The NFI core will issue read
cycles to retrieve data from the device when the data FIFO is not full or the device is not in the busy state. The
NFI core supports consecutive page reading. A page address counter is built in. If the reading reaches to the
end of the page, the device will enter the busy state to prepare data of the next page, and the NFI core will
automatically pause reading and remain inactive until the device returns to the ready state. The page address
counter will restart to count from 0 after the device returns to the ready state and start retrieving data again.
MT
K
BRD
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EWR
SRD
NOB
fo
r
ERD
Burst write mode. Setting to be logic-1 enables the data burst write operation for DMA operation. Actually the
NFI core will issue write cycles once if the data FIFO is not empty even without setting this flag. But if DMA
is to be utilized, the bit should be enabled. If DMA is not to be utilized, the bit didn’t have to be enabled.
ECC read mode. Setting to be logic-1 initializes the ECC checking and correcting for the current page. The
ECC checking is only valid when a full ECC block has been read.
Setting to be logic-1 initializes the ECC parity generation for the current page. The ECC code generation is
only valid when a full ECC block has been programmed.
Setting to be logic-1 initializes the one-shot data read operation. It’s mainly used for read ID and read status
command, which requires no more than 4 read cycles to retrieve data from the device.
The field represents the number of bytes to be retrieved from the device in single mode, and the number of
bytes per AHB transaction in both single and burst mode.
0 Read 4 bytes from the device.
1 Read 1 byte from the device.
2 Read 2 bytes from the device.
3 Read 3 bytes from the device.
NFI +000Ch
Bit
Name
Type
Reset
15
Command register
14
13
12
11
10
9
8
Re
lea
se
BWR
Revision 1.0
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MT6228 GSM/GPRS Baseband Processor Data Sheet
7
6
5
4
3
NFI_CMD
2
1
0
CMD
R/W
45
This is the command input register. The user should write this register to issue a command. Please refer to device
datasheet for the command set. The core can issue some associated commands automatically. Please check out register
NFI_CON for those commands.
Command word.
NFI +0010h
Bit
Name
Type
Reset
15
Co
nf
id
en
tia
l
CMD
Address length register
14
13
12
11
10
9
8
7
NFI_ADDNOB
6
5
4
3
2
1
0
ADDR_NOB
R/W
0
This register represents the number of bytes corresponding to current command. The valid number of bytes ranges from
1 to 5. The address format depends on what device to be used and what commands to be applied. The NFI core is made
transparent to those different situations except that the user has to define the number of bytes.
The user should write the target address to the address register NFI_ADDRL before programming this register.
ADDR_NOB
NFI +0014h
Least significant address register
31
30
29
15
14
13
MT
K
Bit
Name
Type
Reset
Bit
Name
Type
Reset
Number of bytes for the address
28
27
ADDR3
R/W
0
12
11
ADDR1
R/W
0
NFI_ADDRL
26
25
24
23
22
21
10
9
8
7
6
5
20
19
ADDR2
R/W
0
4
3
ADDR0
R/W
0
18
17
16
2
1
0
This defines the least significant 4 bytes of the address field to be applied to the device. Since the device bus width is 1
byte, the NFI core arranges the order of address data to be least significant byte first. The user should put the first
address byte in the field ADDR0, the second byte in the field ADDR1, and so on.
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ADDR3 The fourth address byte.
ADDR2 The third address byte.
ADDR1 The second address byte.
ADDR0 The first address byte.
NFI +0018h
15
14
13
12
11
10
9
8
7
NFI_ADDRM
6
5
4
3
ADDR4
R/W
0
2
1
0
fo
r
Bit
Name
Type
Reset
Most significant address register
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ADDR4 The fifth address byte.
NFI +001Ch
Bit
Name
Type
Reset
Bit
Name
Type
Reset
Write data buffer
31
30
29
15
14
13
28
27
DW3
R/W
0
12
11
DW1
R/W
0
26
25
24
10
9
8
Re
lea
se
This register defines the most significant byte of the address field to be applied to the device. The NFI core supports
address size up to 5 bytes. Programming this register implicitly indicates that the number of address field is 5. In this
case, the NFI core will automatically set the ADDR_NOB to 5.
23
22
21
7
6
5
20
19
DW2
R/W
0
4
3
DW0
R/W
0
NFI_DATAW
18
17
16
2
1
0
DW3
DW2
DW1
DW0
Write data byte 3.
Write data byte 2.
Write data byte 1.
Write data byte 0.
NFI +0020h
Bit
Name
Type
Reset
Co
nf
id
en
tia
l
This is the write port of the data FIFO. It supports word access. The least significant byte DW0 is to be programmed to
the device first, then DW1, and so on.
If the data to be programmed is not word aligned, byte write access will be needed. Instead, the user should use another
register NFI_DATAWB for byte programming. Writing a word to NFI_DATAW is equivalent to writing four bytes
DW0, DW1, DW2, DW3 in order to NFI_DATAWB. Be reminded that the word alignment is from the perspective of
the user. The device bus is byte-wide. According to the flash’s nature, the page address will wrap around once it reaches
the end of the page.
15
Write data buffer for byte access
14
13
12
11
10
9
8
7
NFI_DATAWB
6
5
4
3
2
1
0
DW0
R/W
0
This is the write port for the data FIFO for byte access.
DW0
Write data byte.
Read data buffer
MT
K
NFI +0024h
Bit
Name
Type
Reset
31
30
29
28
27
DR3
RO
0
26
NFI_DATAR
25
24
23
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22
21
20
19
DR2
RO
0
18
17
16
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Bit
Name
Type
Reset
15
14
13
12
11
DR1
RO
0
10
9
8
7
6
5
4
3
Revision 1.0
2
DR0
RO
0
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1
0
Read data byte 3.
Read data byte 2.
Read data byte 1.
Read data byte 0.
NFI +0028h
Bit
Name
Type
Reset
15
Read data buffer for byte access
14
13
12
11
10
9
8
6
5
4
3
2
1
0
DR0
RO
0
This is the read port of the data FIFO for byte access.
NFI +002Ch
Bit
7
NFI_DATARB
15
NFI status
14
13
12
11
10
9
8
Re
lea
se
DR3
DR2
DR1
DR0
fo
r
This is the read port of the data FIFO. It supports word access. The least significant byte DR0 is the first byte read from
the device, then DR1, and so on.
Name
BUSY
Type
Reset
RO
0*
7
6
5
4
NFI_PSTA
3
2
1
0
DATA DATA
ADDR CMD
W
R
R/W R/W R/W R/W
0
0
0
0
Co
nf
id
en
tia
l
This register represents the NFI core control status including command mode, address mode, data program and read
mode. The user should poll this register for the end of those operations.
*The value of BUSY bit depends on the GPIO configuration. If GPIO is configured for NAND flash application, the
reset value should be 0, which represents that NAND flash is in idle status. When the NAND flash is busy, the value
will be 1.
BUSY Synchronized busy signal from the NAND flash. It’s read-only.
DATAW The NFI core is in data write mode.
DATAR The NFI core is in data read mode.
ADDR The NFI core is in address mode.
CMD The NFI core is in command mode.
NFI +0030h
Bit
Name
Type
Reset
15
FIFO control
14
13
12
11
10
9
8
7
NFI_FIFOCON
6
5
4
3
2
1
0
RESE FLUS WR_F WR_E RD_F RD_E
T
H
ULL MPTY ULL MPTY
WO WO
RO
RO
RO
RO
0
0
0
1
0
1
The register represents the status of the data FIFO.
MT
K
RESET
Reset the state machine and data FIFO.
FLUSH
Flush the data FIFO.
WR_FULL Data FIFO full in burst write mode.
WR_EMPTY
Data FIFO empty in burst write mode.
RD_FULL
Data FIFO full in burst read mode.
RD_EMPTY
Data FIFO empty in burst read mode.
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NFI +0034h
Bit
15
Name
BYTE
_RW
NFI control
14
13
Type R/W
Reset
0
12
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NFI_CON
11
10
9
8
MULT
PROG ERAS
IPAG READ
RAM_ E_CO
E_CO _CON
CON
N
N
R/W R/W R/W R/W
0
0
0
0
7
6
5
4
SW_P MULT
ROGS I_PA
PARE GE_R
_EN D_EN
R/W R/W
0
0
3
AUTO
ECC_
ENC_
EN
R/W
0
2
1
0
AUTO
DMA_ DMA_
ECC_
WR_E RD_E
DEC_
N
N
EN
R/W R/W R/W
0
0
0
fo
r
The register controls the DMA and ECC functions. For all field, Setting to be logic-1 represents enabled, while 0
represents disabled.
NFI +0038h
Bit
Name
Type
Reset
15
Co
nf
id
en
tia
l
Re
lea
se
BYTE_RW Enable APB byte access.
MULTIPAGE_CON This bit represents that the first-cycle command for read operation (00h) can be automatically
performed to read the next page automatically. Automatic ECC decoding flag AUTOECC_DEC_EN should
also be enabled for multiple page access.
READ_CON
This bit represents that the second-cycle command for read operation (30h) can be automatically
performed.
PROGRAM_CON
This bit represents that the second-cycle command for page program operation (10h) can be
automatically performed after the data for the entire page (including the spare area) has been written. It should
be associated with automatic ECC encoding mode enabled.
ERASE_CON The bit represents that the second-cycle command for block erase operation (D0h) can be
automatically performed after the block address is latched.
SW_PROGSPARE_EN
If enabled, the NFI core allows the user to program or read the spare area directly.
Otherwise, the spare area can be programmed or read by the core.
MULTI_PAGE_RD_EN
Multiple page burst read enable. If enabled, the burst read operation could continue
through multiple pages within a block. It’s also possible and more efficient to associate with DMA scheme to
read a sector of data contained within the same block.
AUTOECC_ENC_EN Automatic ECC encoding enable. If enabled, the ECC parity is written automatically to the
spare area right after the end of the data area. If SW_PROGSPARE_EN is set, however, the mode can’t be
enabled since the core can’t access the spare area.
AUTOECC_DEC_EN Automatic ECC decoding enabled, the error checking and correcting are performed
automatically on the data read from the memory and vice versa. If enabled, when the page address reaches the
end of the data read of one page, additional read cycles will be issued to retrieve the ECC parity-check bits
from the spare area to perform checking and correcting.
DMA_WR_EN
This field is used to control the activity of DMA write transfer.
DMA_RD_EN This field is used to control the activity of DMA read transfer.
Interrupt status register
14
13
NFI_INTR
12
11
10
9
8
7
6
5
4
3
2
1
0
ERAS RESE
RD
BUSY
WR_C
ERR_ ERR_ ERR_ ERR_ ERR_ ERR_ ERR_ ERR_ E_CO T_CO
_CO
_RET
OMPL
COR3 COR2 COR1 COR0 DET3 DET2 DET1 DET0 MPLE MPLE
MPLE
URN
ETE
TE
TE
TE
RC
RC
RC
RC
RC
RC
RC
RC
RC
RC
RC
RC
RC
0
0
0
0
0
0
0
0
0
0
0
0
0
MT
K
The register indicates the status of all the interrupt sources. Read this register will clear all interrupts.
BUSY_RETURN
Indicates that the device state returns from busy by inspecting the R/B# pin.
ERR_COR3
Indicates that the single bit error in ECC block 3 needs to be corrected.
ERR_COR2
Indicates that the single bit error in ECC block 2 needs to be corrected.
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Bit
15
Interrupt enable register
14
13
12
ERR_ ERR_ ERR_
Name COR3 COR2 COR1
_EN _EN _EN
Type R/W
0
Reset
R/W
0
11
10
9
NFI_INTR_EN
8
ERR_ ERR_ ERR_
DET3 DET2 DET1
_EN _EN _EN
R/W
0
R/W
0
R/W
0
7
6
5
4
3
ERAS
BUSY
ERR_ ERR_ E_CO
_RET
COR_ DET_ MPLE
URN_
EN
EN TE_E
EN
N
R/W R/W R/W R/W
0
0
0
0
Re
lea
se
NFI +003Ch
fo
r
ERR_COR1
Indicates that the single bit error in ECC block 1 needs to be corrected.
ERR_COR0
Indicates that the single bit error in ECC block 0 needs to be corrected.
ERR_DET3 Indicates an uncorrectable error in ECC block 3.
ERR_DET2 Indicates an uncorrectable error in ECC block 2.
ERR_DET1 Indicates an uncorrectable error in ECC block 1.
ERR_DET0 Indicates an uncorrectable error in ECC block 0.
ERASE_COMPLETE
Indicates that the erase operation is completed.
RESET_COMPLETE
Indicates that the reset operation is completed.
WR_COMPLETE
Indicates that the write operation is completed.
RD_COMPLETE
Indicates that the single page read operation is completed.
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R/W
0
This register controls the activity for the interrupt sources.
2
RESE
T_CO
MPLE
TE_E
N
R/W
0
1
0
WR_C
OMPL
ETE_
EN
RD_
COM
PLET
E_EN
R/W
0
R/W
0
NFI+0040h
Bit
Name
Type
Reset
15
Co
nf
id
en
tia
l
ERR_COR1_EN
The error correction interrupt enable for the 2nd ECC block.
ERR_COR2_EN
The error correction interrupt enable for the 3rd ECC block.
ERR_COR3_EN
The error correction interrupt enable for the 4th ECC block.
ERR_DET1_EN
The error detection interrupt enable for the 2nd ECC block.
ERR_DET2_EN
The error detection interrupt enable for the 3rd ECC block.
ERR_DET3_EN
The error detection interrupt enable for the 4th ECC block.
BUSY_RETURN_EN The busy return interrupt enable.
ERR_COR_EN
The error correction interrupt enable for the 1st ECC block.
ERR_DET_EN
The error detection interrupt enable for the 1st ECC block.
ERASE_COMPLETE_EN The erase completion interrupt enable.
RESET_COMPLETE_EN The reset completion interrupt enable.
WR_COMPLETE_EN
The single page write completion interrupt enable.
RD_COMPLETE_EN The single page read completion interrupt enable.
NFI_PAGECNT
R
NAND flash page counter
14
13
12
11
10
9
8
7
6
5
4
3
CNTR
R/W
0
2
1
0
MT
K
The register represents the number of pages that the NFI has read since the issuing of the read command. For some
devices, the data can be read consecutively through different pages without the need to issue another read command.
The user can monitor this register to know current page count, particularly when read DMA is enabled.
CNTR
The page counter.
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NFI+0044h
Bit
Name
Type
Reset
15
NFI_ADDRCNT
R
NAND flash page address counter
14
13
12
11
10
9
8
7
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MT6228 GSM/GPRS Baseband Processor Data Sheet
6
5
CNTR
R/W
0
4
3
2
1
0
fo
r
The register represents the current read/write address with respect to initial address input. It counts in unit of byte. In
page read and page program operation, the address should be the same as that in the state machine in the target device.
NFI supports the address counter up to 4096 bytes.
CNTR
The address count.
Bit
Name
Type
Reset
15
ECC block 0 parity error detect syndrome address
14
13
12
11
10
9
8
Re
lea
se
NFI +0050h
7
6
5
4
3
NFI_
SYM0_ADDR
2
1
0
SYM
RO
0
This register identifies the address within ECC block 0 that a single bit error has been detected.
SYM
The byte address of the error-correctable bit.
NFI +0054h
15
14
13
12
11
10
9
8
7
Co
nf
id
en
tia
l
Bit
Name
Type
Reset
NFI_SYM1_ADD
R
ECC block 1 parity error detect syndrome address
6
5
4
3
2
1
0
SYM
RO
0
This register identifies the address within ECC block 1 that a single bit error has been detected.
SYM
The byte address of the error-correctable bit.
NFI +0058h
Bit
Name
Type
Reset
15
NFI_SYM2_ADD
R
ECC block 2 parity error detect syndrome address
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SYM
RO
0
This register identifies the address within ECC block 2 that a single bit error has been detected.
SYM
The byte address of the error-correctable bit.
NFI +005Ch
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SYM
RO
0
MT
K
Bit
Name
Type
Reset
NFI_SYM3_ADD
R
ECC block 3 parity error detect syndrome address
This register identifies the address within ECC block 3 that a single bit error has been detected.
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The byte address of the error-correctable bit.
NFI +0060h
Bit
Name
Type
Reset
Bit
Name
Type
Reset
31
ECC block 0 parity error detect syndrome word
30
29
28
27
26
25
24
23
22
21
11
10
9
8
7
6
5
ED3
RO
0
15
14
13
12
ED1
RO
0
NFI_SYM0_DAT
20
19
ED2
RO
0
4
3
ED0
RO
0
18
2
17
16
1
0
fo
r
SYM
Revision 1.0
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MT6228 GSM/GPRS Baseband Processor Data Sheet
This register represents the syndrome word for the corrected ECC block 0. To correct the error, the user should first
read NFI_ SYM0_ADDR for the address of the correctable word, and then read NFI_SYM0_DAT, directly XOR the
syndrome word with the data word to obtain the correct word.
Bit
Name
Type
Reset
Bit
Name
Type
Reset
31
ECC block 1 parity error detect syndrome word
30
29
28
27
26
25
24
11
10
9
8
ED3
RO
0
15
14
13
12
ED1
RO
0
NFI_SYM1_DAT
Re
lea
se
NFI +0064h
23
22
21
7
6
5
20
19
ED2
RO
0
4
3
ED0
RO
0
18
17
16
2
1
0
NFI +0068h
Bit
Name
Type
Reset
Bit
Name
Type
Reset
31
Co
nf
id
en
tia
l
This register represents the syndrome word for the corrected ECC block 0. To correct the error, the user should first
read NFI_ SYM1_ADDR for the address of the correctable word, and then read NFI_SYM1_DAT, directly XOR the
syndrome word with the data word to obtain the correct word.
ECC block 2 parity error detect syndrome word
30
29
28
27
26
25
24
23
22
21
11
10
9
8
7
6
5
ED3
RO
0
15
14
13
12
ED1
RO
0
NFI_SYM2_DAT
20
19
ED2
RO
0
4
3
ED0
RO
0
18
17
16
2
1
0
This register represents the syndrome word for the corrected ECC block 0. To correct the error, the user should first
read NFI_ SYM2_ADDR for the address of the correctable word, and then read NFI_SYM2_DAT, directly XOR the
syndrome word with the data word to obtain the correct word.
NFI +006Ch
31
30
29
28
27
26
25
24
23
22
21
11
10
9
8
7
6
5
ED3
RO
0
15
14
13
MT
K
Bit
Name
Type
Reset
Bit
Name
Type
Reset
ECC block 3 parity error detect syndrome word
12
ED1
RO
0
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NFI_SYM3_DAT
20
19
ED2
RO
0
4
3
ED0
RO
0
18
17
16
2
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Revision 1.0
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MT6228 GSM/GPRS Baseband Processor Data Sheet
This register represents the syndrome word for the corrected ECC block 0. To correct the error, the user should first
read NFI_ SYM3_ADDR for the address of the correctable word, and then read NFI_SYM3_DAT, directly XOR the
syndrome word with the data word to obtain the correct word.\
NFI +0070h
Bit
15
NFI ECC error detect indication register
14
13
12
11
10
9
8
7
6
NFI_ERRDET
5
4
Name
fo
r
Type
Reset
This register identifies the block in which an uncorrectable error has been detected.
Bit
Name
Type
Reset
15
NFI ECC parity word 0
14
13
12
11
10
9
NFI_PAR0
8
7
6
PAR
RO
0
5
4
3
Re
lea
se
NFI +0080h
3
2
1
0
EBLK EBLK EBLK EBLK
3
2
1
0
RO
RO
RO
RO
0
0
0
0
2
1
0
This register represents the ECC parity for the ECC block 0. It’s calculated by the NFI core and can be read by the user.
It’s generated when writing or reading a page.
Register Address
Register Function
NFI +0080h
NFI ECC parity word 0
NFI +0084h
NFI ECC parity word 1
NFI +0088h
NFI ECC parity word 2
Acronym
NFI_PAR0
NFI_PAR1
NFI_PAR2
NFI ECC parity word 3
NFI ECC parity word 4
NFI_PAR4
NFI ECC parity word 5
NFI_PAR5
NFI ECC parity word 6
NFI_PAR6
NFI ECC parity word 7
NFI_PAR7
NFI +0094h
NFI +0098h
NFI +009Ch
NFI_PAR3
Co
nf
id
en
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l
NFI +008Ch
NFI +0090h
Table 39 NFI parity bits register table
NFI+0100h
Bit
Name
Type
Reset
15
NFI device select register
14
13
12
11
10
9
8
7
NFI_CSEL
6
5
4
3
2
1
0
CSEL
R/W
0
The register is used to select the target device. It decides which CEB pin to be functional. This is useful while using the
high-density device.
MT
K
CSEL Chip select. The value defaults to 0.
0 Device 1 is selected.
1 Device 2 is selected.
6.2.3
Device programming sequence
This section lists the program sequences to successfully use any compliant devices.
For block erase
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MT6228 GSM/GPRS Baseband Processor Data Sheet
Enable erase complete interrupt (NFI_INTR_EN = 8h).
2.
Write command (NFI_CMD = 60h).
3.
Write block address (NFI_ADDR).
4.
Set the number of address bytes (NFI_ADDRNOB).
5.
Check program status (NFI_PSTA) to see whether the operation has been completed. Omitted if ERASE_CON has
been set.
6.
Write command (NFI_CMD = D0h). Omitted if ERASE_CON has been set.
7.
Check the erase complete interrupt.
For status read
Write command (NFI_CMD = 70h).
2.
Set single word read for 1 byte (NFI_OPCON = 1100h).
3.
Check program status (NFI_PSTA) to see whether the operation has been completed.
4.
Read single byte (NFI_DATAR).
For page program
Re
lea
se
1.
fo
r
1.
Enable write complete interrupt (NFI_INTR_EN = 2h).
2.
Set DMA mode, and hardware ECC mode (NFI_CON = Ah).
3.
Write command (NFI_CMD = 80h).
4.
Write page address (NFI_ADDR).
5.
Set the number of address bytes (NFI_ADDRNOB).
6.
Set burst write (NFI_OPCON = 2h).
7.
In DMA mode, the signal DMA_REQ controls the access. The user can also check the status of the FIFO
(NFI_FIFOCON) and write a pre-specified number of data whenever the FIFO is not full and until the end of page
is reached.
8.
Check program status (NFI_PSTA) to see whether all operation has been completed.
9.
Set ECC parities write. Omitted if hardware ECC mode has been set.
Co
nf
id
en
tia
l
1.
10. Check program status (NFI_PSTA) to see whether the above operation has been completed.
11. Write command (NFI_CMD = 10h). Omitted if PROGRAM_CON has been set.
12. Check the program complete interrupt.
For page read
Enable busy ready, read complete, ECC correct indicator, and ECC error indicator interrupt. (NFI_INTR_EN =
41h).
2.
Set DMA mode, and hardware ECC mode. (NFI_CON = 5h).
3.
Write command (NFI_CMD = 00h).
4.
Write page address (NFI_ADDR).
5.
Set the number of address bytes (NFI_ADDRNOB).
MT
K
1.
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MT6228 GSM/GPRS Baseband Processor Data Sheet
6.
Check busy ready interrupt.
7.
Set burst read (NFI_OPCON = 1h).
8.
In DMA mode, the signal DMA_REQ controls the access. The user can also check the status of the FIFO
(NFI_FIFOCON) and read a pre-specified number of data whenever the FIFO is not empty and until the end of
page is reached.
9.
Set ECC parities check. Omitted if hardware ECC mode has been set.
fo
r
10. Check program status (NFI_PSTA) or check ECC correct and error interrupt.
11. Read the ECC correction or error information.
6.2.4
Device timing control
Re
lea
se
This section illustrates the timing diagram.
The ideal timing for write access is listed as listed in Table 40.
Parame
ter
Description
TWC1
Write cycle time
TWC2
Timing specification
Timing at 13MHz
Timing at 26MHz
Timing at 52MHz
(WST, WH) = (0,0)
(WST, WH) = (0,0)
(WST, WH) = (1,0)
3T + WST + WH
230.8ns
105.4ns
76.9ns
Write cycle time
2T + WST + WH
153.9ns
76.9ns
57.7ns
TDS
Write data setup time
1T + WST
76.9ns
38.5ns
38.5ns
TDH
Write data hold time
1T + WH
76.9ns
38.5ns
19.2ns
TWP
Write enable time
1T + WST
76.9ns
38.5ns
38.5ns
Write high time
1T + WH
76.9ns
38.5ns
19.2ns
Command latch enable
setup time
1T
76.9ns
38.5ns
19.2ns
TCLH
Command latch enable
hold time
1T + WH
76.9ns
38.5ns
19.2ns
TALS
Address latch enable
setup time
1T
76.9ns
38.5ns
19.2ns
TALH
Address latch enable
hold time
1T + WH
76.9ns
38.5ns
19.23ns
FWC
Write data rate
1 / TWC2
6.5Mbytes/s
13Mbytes/s
17.3Mbytes/s
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TWH
TCLS
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Table 40 Write access timing
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HCLK
WST
NCLE
tCLS, tALS
tCLH, tALH
tWP
NWEB
tDS
NLD
tDH
command
tCES
tCEH
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NALE
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tWC1
Figure 4 Command input cycle (1 wait state).
HCLK
WST
WST
NCLE
tCLS
NALE
tALS
NWEB
OE
(internal)
NCEB
tWC2
tWP
tWP
tWP
tWH
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NLD
tWC1
WST
A0
tCES
tALH
tWH
A1
tDH
tCLH
A2
tDH
tDH
tCEH
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Figure 5 Address input cycle (1 wait state)
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HCLK
WST
NCLE
WST
WST
tCLS
tCLH
tWC1
tWC2
NALE
NWEB
tWC2
tWP
tWP
tWH
D526
tDH
OE
(internal)
D527
tDH
tDH
tCES
tCEH
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NCEB
tWH
D0
NLD
tALH
tWP
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tALS
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Figure 6 Consecutive data write cycles (1 wait state, 0 hold time extension)
HCLK
NCLE
tCLS
WST
WH
tWC1
tWC2
NALE
tALS
NWEB
OE
(internal)
NCEB
tWP
WH
tCLH
tALH
tWH
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NLD
tWP
WST
D0
D527
tDH
tDH
tCES
tCEH
Figure 7 Consecutive data write cycles (1 wait state, 1 hold time extension)
The ideal timing for read access is as listed in Table 6.
Parame
ter
Description
Timing
specification
Timing at 13MHz
Timing at 26MHz
Timing at 52MHz
(RLT, WH) = (0,0)
(RLT, WH) = (1,0)
(RLT, WH) = (2,0)
TRC1
Read cycle time
3T + RLT + WH
230.8ns
153.8ns
96.2ns
TRC2
Read cycle time
2T + RLT + WH
153.9ns
115.4ns
76.9ns
Read data setup time
1T + RLT
76.9ns
76.9ns
57.7ns
Read data hold time
1T + WH
76.9ns
38.5ns
19.2ns
TRP
Read enable time
1T + RLT
76.9ns
76.9ns
57.7ns
MT
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TDS
TDH
TRH
Read high time
1T + WH
76.9ns
38.5ns
19.2ns
TCLS
Command latch enable
setup time
1T
76.9ns
38.5ns
19.2ns
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TCLH
Command latch enable
hold time
1T + WH
76.9ns
38.5ns
19.2ns
TALS
Address latch enable
setup time
1T
76.9ns
38.5ns
19.2ns
TALH
Address latch enable hold
time
1T + WH
76.9ns
38.5ns
19.2ns
FRC
Write data rate
1 / TRC2
6.5Mbytes/s
8.7Mbytes/s
13Mbytes/s
HCLK
RLT
RLT
WH
NCLE
tCLS
tWH
tWP
tDH
D0
NLD
D527
OE
(internal)
NCEB
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NREB
WH
tCLH, tALH
NALE
tALS
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Table 41 Read access timing
tCES
tDH
tCEH
HCLK
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Figure 8 Serial read cycle (1 wait state, 1 hold time extension)
RLT
NCLE
W2R
tCLS
NALE
tCLH
tALS
NWEB
RLT
tALH
tWP
tWHR
NREB
tDS
NLD
tDH
70h
tCES
NCEB
OE
(internal)
tRP
Status
tCEH
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Figure 9 Status read cycle (1 wait state)
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HCLK
NCLE
tCLS
tCLH
NALE
tALS
tALH
tWP
NWEB
tWP
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tWHR
NREB
tDS
tDH
90h
NLD
tRP
tDH
tDS
00h
01h, 06h
tCES
tCEH
Figure 10 ID and manufacturer read (0 wait state)
6.3
6.3.1
USB OTG Controller
General Description
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NCEB
OE
(internal)
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The USB OTG controller complies with Universal Serial Bus (USB) Specification Rev 1.1 and USB On-The-Go (OTG)
Supplement Rev. 1.0a. The USB OTG controller supports USB device mode, USB simple host mode, as well as OTG
handshaking capabilities, at full-speed (12 Mbps) operation. The cellular phone uses this widely available USB
interface to exchange data with USB hosts such as a PC or laptop; or to function as a host, allowing it to connect to
other devices. When operating in host mode, only a single peer-to-peer (no intermediate hub) connection is
supported.
The USB device controller provides 5 endpoints in addition to the mandatory control endpoint, three of which are for
TX transactions and two for RX transactions. Word, half-word, and byte access methods are allowed for loading and
unloading the FIFO buffer. Four independent DMA channels are equipped with the separate controllers to accelerate
data transfer. The features of each endpoint are as follows:
Endpoint 0 RX: A double buffer is implemented; each buffer is an 8-byte FIFO.
DMA transfer is not supported.
2.
Endpoint 0 TX: A double buffer is implemented; each buffer is an 8-byte FIFO.
DMA transfer is not supported.
3.
Endpoint 1 RX: A 64-byte FIFO that accommodates maximum packet size of 64 bytes.
supported.
DMA transfer is
4.
Endpoint 1 TX: A 64-byte FIFO that accommodates maximum packet size of 64 bytes.
supported.
DMA transfer is
5.
Endpoint 2 RX: A 64-byte FIFO that accommodates maximum packet size of 64 bytes. DMA transfer is
supported.
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1.
6.
Endpoint 2 TX: A 64-byte FIFO that accommodates maximum packet size of 64 bytes.
supported.
7.
Endpoint 3 TX: An 8-byte FIFO that accommodates maximum packet size of 8 bytes.
supported.
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DMA transfer is
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This controller is highly software configurable.
bulk, interrupt or isochronous endpoints.
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All endpoints except the control endpoint can be configured to be a
Note: The Internal Bus clock must be running at 26Mhz or higher for the USB OTG controller to operate correctly.
6.3.2
USB MEMBUF Mapping and BDT Format
USB MEMBUF Memory Map
MT
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6.3.2.1
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The controller uses a buffer descriptor table (BDT) mechanism for control information as well as address pointer into
the data buffer that contains the data for each endpoint. A single dedicated software-addressable local memory
(USB_MEMBUF) is allocated inside the USB controller to contain both the BDT and the data. Detailed descriptions
of the BDT and the USB_MEMBUF mapping follow.
Figure 11 USB Memory Buffer (96x32)
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6.3.2.2
Buffer Descriptor Byte Format
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Each Buffer Descriptor contains 8 bytes of data. The first word contains control information, and the second word
contains the address of the associated data buffer.
Bit
31:26 25:16
Name RSVD
Name
BC
15:8
7
6
5
4
3
2
1 0
DATA0 KEEP/TOK_PI NINC/TOK_PID DTS/TOK_PID[ BDT_STALL/TOK_P
0 0
RSVD OWN
/1
D[3]
[2]
1]
ID[0]
Buffer Address (32 bits)
These bits are
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(Note: VUSB refers to the USB controller hardware)
BUFFER ADDRESS The Address bits represent the 32 -bit buffer address in USB MEMBUF.
unchanged by the VUSB hardware.
The Byte Count bits represent a 10-bit Byte Count. The VUSB Serial Interface Engine (SIE) changes this
field upon completion of a RX transfer with the byte count of the data received.
OWN
The OWN bit determines who currently owns the buffer. If OWN=1, VUSB has exclusive access to the
BD. If OWN=0 the microprocessor has exclusive access to the BD. The SIE generally writes a 0 to this
bit when it has completed a token, except when KEEP=1. When OWN=0, the VUSB ignores all other
fields in the BD, and the microprocessor has access to the entire BD. This byte of the BD must be the last
byte updated by the microprocessor when initializing a BD. Once the BD has been assigned to the VUSB,
the microprocessor must not change it in any way.
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BC[9:0]
DATA0/1 The DATA0/1 bit indicates if a DATA0 field (DATA0/1=0) or a DATA1 (DATA0/1=1) field was transmitted
or received. This bit is unchanged by the VUSB.
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KEEP/TOK_PID[3] If KEEP=1, once the OWN bit is set, the BD is owned by the VUSB. Typically this bit is set
to 1 for ISO endpoints that are feeding a FIFO. The microprocessor is not informed that a token has
been processed, the data is simply transferred to or from the FIFO. The NINC bit is normally also set
when KEEP=1 to prevent address increment. KEEP must equal 0 to allow the VUSB to release the
BD when a token has been processed.
If KEEP=1, this bit is unchanged by the VUSB; otherwise bit 3 of the current token PID is written
back into the BD by the VUSB.
NINC/TOK_PID[2] The No INCrement bit disables the DMA engine address increment, forcing the DMA engine to
read from or to write to the same address. This feature is useful when data needs to be read from or
written to a single location such as a FIFO. Typically this bit is set with the KEEP bit for ISO
endpoints that interface with a FIFO.
If KEEP=1, this bit is unchanged by the VUSB; otherwise bit 2 of the current token PID is written
back into the BD by the VUSB.
DTS/TOK_PID[1]
Setting this bit enables Data Toggle Synchronization by the VUSB. When this bit is 0, no
Data Toggle Synchronization is performed.
If KEEP=1, this bit is unchanged by the VUSB; otherwise bit 1 of the current token PID is written
back into the BD by the VUSB.
MT
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BDT_STALL/TOK_PID[0] Setting this bit causes the VUSB to issue a STALL handshake if a token is received by
the SIE that would use the BDT in this location. The BDT is not changed by the SIE (the own
bit and the rest of the BDT remain unchanged) when the BDT-STALL bit is set.
If KEEP=1, this bit is unchanged by the VUSB; otherwise bit 0 of the current token PID is
written back into the BD by the VUSB.
TOK_PID The current token PID is written back into the BD by the VUSB when a transfer is complete. The token
PID takes on values from the USB specification: 0x1 for an OUT token, 0x9 for an IN token or 0xd for a
SETUP token. In host mode, this field is used to report the last returned PID or to indicate the transfer
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status. The possible values returned are: 0x3 DATA0, 0xb DATA1, 0x2 ACK, 0xe STALL, 0xa NAK, 0x0
Bus Timeout, 0xf Data Error.
6.3.3
Operating Modes
The USB_OTG controller supports 3 modes of operation.
6.3.3.1
Standard Mode
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In this mode, MEMBUF data is accessed via a single software read/write operation. Both 8-bit and 32-bit access
methods are supported. Standard mode is the most flexible operating mode with the maximum software control
flexibility. All BDT values are required to be managed by software. However, the throughput for standard mode is
slowest of the three modes due to heavy software intervention.
Direct Memory Access (DMA) Mode
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6.3.3.2
In DMA mode, MEMBUF data for endpoints 1 and 2 (TX and RX) is accessed via DMA. This access method allows
for faster data movement. To issue a DMA transfer, software must enable and disable the individual USB DMA
control via its corresponding register set. Aside from the faster data movement, everything is the same as in standard
mode.
6.3.3.3
Fast Mode
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To increase the operating throughput, the USB OTG controller provides a “fast mode” operation. This mode is most
suitable for transmission of large, regular chunks of data. While operating in this mode, DMA is enabled
automatically for endpoints 1 and 2 (TX and RX), and each packet transfer is 64 bytes. In order to minimize software
involvement and latency, all interrupts to the MCU (except for fast mode error status) are masked during the
transmission until the last packet is transferred. Fast mode supports only one endpoint and one direction.
Note:
When using fast mode, the own bit of the BDT must be 0 to avoid a software
configuration race problem. Hardware manages the own bit value and also BDT values
automatically.
6.3.4
Special Conditions
Due to the complex nature of the USB OTG controller design and software operation, some special cases must be
noted:
1.
When using DMA mode, if B2W of the generic DMA is enabled with 4-beat burst and byte access, then the
transfer count of the generic DMA controller must be set to a 4-byte multiple. Otherwise, once the controller
arranges the data into words, the few remaining bytes are incorrectly read or written one byte at a time, and each
byte is padded to a 4-byte word. The internal USB DMA controller treats each read/write as one word and
increments the address after each read/write, thereby incrementing the access pointer incorrectly.
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From a software perspective, all transfer byte counts that are not 4-byte aligned must be padded to a 4-byte
multiple; That amount of space must be allocated for receiving: the extra bytes of memory need to be reserved so
the received data does not overwrite any useful data.
For example: If generic DMA is to move 13 bytes of data from USB MEM to SRAM, software must allocate 16
bytes in SRAM for such an operation. The last 3 bytes are unknown data and are to be discarded by software.
2.
During a host mode operation, the CRC16 bit of the USB_ERR_STAT register cannot be checked.
the TOK_PID bits of the BDT to check for a data CRC error.
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When operating in fast mode, software must ignore the token_dne status bit of the USB_INT_STAT register.
4.
Interrupts can come from the following sources:
6.3.5
a.
sources listed in the USB_INT_STAT register,
b.
sources listed in the USB_OTG_INT_STAT register,
c.
sources listed in the USB_FM_ERR_STAT register, or,
d.
PHY resume interrupt.
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3.
Register Definitions
(Note: VUSB and SIE refer to the USB controller hardware internal modules)
Bit
Name
Type
Reset
USB Peripheral ID register
7
6
0
Bit
Name
Type
Reset
4
3
2
6
1
0
This number is set to 0x04 for hardware core version control.
USB Peripheral ID complement register
7
1
ID [5:0]
RO
0x04
0
DEBUG PURPOSES ONLY
ID
Configuration number.
70000004h
5
USB_PER_ID
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70000000h
5
4
3
USB_ID_COMP
2
1
0
NID [5:0]
RO
1
70000008h
Bit
Name
Type
Reset
7
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DEBUG PURPOSES ONLY
NID
One’s complement of ID. This register reads back 0xFB.
USB revision register
6
5
4
3
USB_REV
2
1
0
REV [7:0]
RO
DEBUG PURPOSES ONLY
REV
Revision ID of the hardware controller core. This register reads back 0x32.
7000000Ch
Bit
Name
Type
Reset
7
USB_ADD_INF
O
USB Peripheral additional info register
6
5
4
3
2
1
0
MT
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DEBUG PURPOSES ONLY
This register is used for debug purposes only. The register reads back 0x01.
70000010h
USB OTG Interrupt status register
Bit
7
6
Name
ID_CHG
1_MSEC
Type
R/W
R/W
5
LINE_STATE_C
HG
R/W
4
3
2
SESS_VLD_ B_SESS_CH
CHG
G
R/W
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USB_ISTAT
1
0
A_VBUS_CH
G
R/W
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Reset
0
0
0
0
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0
The OTG Interrupt Status Register records changes of the ID and VBUS signals. Software reads this register to
determine which event is causing an interrupt. Only bits that have changed since the last software read are set.
Writing a one to a bit clears the respective interrupt. The change conditions are de-bounced in hardware.
ID_CHG
1_MSEC
70000014h
Bit
7
Name
ID_EN
Type
Reset
R/W
0
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This bit is set when a change in the ID Signal from the USB connector is sensed.
This bit is set when the 1 millisecond timer expires. This bit stays asserted until cleared by software.
The interrupt must be serviced every millisecond to avoid losing 1 ms counts.
LINE_STATE_CHG This interrupt is set when the USB line state (CTL_RG SE0 and JSTATE bits) has been stable
(unchanged) for 1 millisecond, and if the line state value is different from the last time that the line
state was stable. The interrupt is set on transitions between SE0 and J, SE0 and K, and J and K.
Changes in JSTATE while SE0 is true do not cause an interrupt. This interrupt can be used in
detecting Reset, Resume, Connect and Data Line Pulse signaling.
SESS_VLD_CHG
This bit is set when a change in VBUS is detected, indicating a session has become valid or a
session is no longer valid.
B_SESS_END_CHG This bit is set when a change in VBUS is detected on a “B” device.
A_VBUS_CHG
This bit is set when a change in VBUS is detected on an “A” device.
USB OTG Interrupt Control register
6
5
LINE
1_MSEC_EN
STATE_EN
R/W
R/W
0
0
4
3
2
SESS_VLD_
B_SESS_EN
EN
R/W
0
USB_OTG_ICT
RL
1
0
A_VBUS_EN
R/W
0
70000018h
Bit
7
Name
ID
Type
Reset
R/W
0
ID
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ID_EN
Enables the ID interrupt.
1_MSEC_EN
Enables the 1 millisecond timer interrupt.
LINESTATE_EN
Enables the interrupt on a line state change.
SESS_VLD_EN Enables the session valid interrupt.
B_SESS_EN
Enables the “B” Session End Interrupt.
A_VBUS_EN Enables the “A” VBUS Valid Interrupt.
USB OTG status register
6
1_MSEC
R/W
0
5
LINE_STATE_STA
BLE
R/W
0
4
3
2
B_SESS_EN
SESS_VLD
D
R/W
0
USB_OTG_STAT
1
0
A_VBUS_VL
D
R/W
0
MT
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Indicates the current state of the ID pin on the USB connector:
0: A Type A cable has been plugged into the USB connector;
1: no cable is attached or a Type B cable has been plugged into the USB connector.
1_MSEC
DEBUG only. This bit is reserved for the 1Msec count. The bit is not useful to software.
LINE_STATE_STABLE
This bit is set when the line state (JSTATE and SE0 in the CTL_RG) has been stable for
the previous 1 millisecond. This bit is used to provide a hardware debounce of the line state for
detection of connect, disconnect and resume signaling. First read the state of JSTATE and SE0 in
the CTL_RG, then read this bit. If this bit is 1, then the value of the JSTATE and SE0 bits of the
CTL_RG have been static for the previous 1ms and can be considered debounced.
SESS_VLD
This bit is set when the VBUS voltage is above the “B” session Valid threshold.
B_SESS_END
This bit is set when the VBUS voltage is below the “B” session End threshold.
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A_VBUS_VLD
This bit is set when the VBUS voltage is above the “A” VBUS Valid threshold.
7000001Ch
USB OTG Control register
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USB_OTG_CTRL
Bit
7
6
5
4
3
2
1
Name
DP_HIGH
DM_HIGH
DP_LOW
DM_LOW
VBUS_ON
OTG_EN
VBUS_CHG
Type
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
0
VBUS_DSC
HG
R/W
0
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The OTG Control Register controls the operation of VBUS and data line termination resistors.
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When set, a pull-up resistor on the D+ Data line is enabled.
DP_HIGH
DM_HIGH When set, a pull-up resistor on the D- Data line is enabled.
DP_LOW
When set, a pull-down resistor on the D+ Data line is enabled.
DM_LOW
When set, a pull-down resistor on the D- Data line is enabled.
VBUS_ON When set, the VBUS power signal is turned on.
OTG_EN When set, the pull-up and pull-down controls in this register are used.
When OTG_EN is cleared:
• If the CTL register HOST_MODE bit is set, the D+ and D- pull-down resistors are engaged; or,
• If the CTL register HOST_MODE bit is clear and the USB_EN bit is set, the D+ pull-up is engaged.
VBUS_CHG
VBUS_DSCHG
70000020h
7
70000024h
Bit
Name
Type
Reset
7
USB_FM_PKT_NU
M_L
USB FM packet count number (low byte)
6
5
4
3
PKT_NUM[7:0]
R/W
0
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Bit
Name
Type
Reset
When set, the VBUS signal is charged through a resistor.
When set, the VBUS signal is discharged through a resistor.
2
5
4
3
PKT_NUM[15:8]
R/W
0
0
USB_FM_PKT_NU
M_H
USB FM packet count number (low byte)
6
1
2
1
0
FAST MODE ONLY
PKT_NUM
These 2 registers combined specify the number of 64-byte packets to be transferred.
70000028h
Bit
USB_FM_ERR_
STAT
USB FM error status register
7
6
STA_OVR_F FM_TOK_D
Name
LW
ONE
Type
R/W
R/W
Reset
0
0
5
4
DMA TX
R/W
0
3
2
1
0
DMA RX
SUC_ERR
NAK_ERR
SHRT_ERR
R/W
0
R/W
0
R/W
0
R/W
0
MT
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FAST MODE ONLY All status bits that are set are cleared by rewriting a 1.
STA_OVR_FLW
Indicates that during fast mode, the non-fast mode status FIFO (+0x50) has overflowed.
FM_TOK_DONE
This is the non-fast mode endpoint token done interrupt. During fast mode operation, any
non-fast mode endpoint token done signal is moved to this register bit for indication.
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SUC_ERR
NAK_ERR
register.
SHRT_ERR
70000028h
Bit
HOST mode only. Short packet error. This bit is set when the data transferred in a single
transaction is less than 64 bytes.
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DMA_RX_EN
DEBUG only. Asserted if fm dma_rx_en is asserted and USB_FM_INT_MASK (+0x6C) mask is
enabled.
DEBUG only. Asserted if fm dma_rx_en is asserted and USB_FM_INT_MASK (+0x6C) mask is
enabled.
HOST mode only. 3 successive errors. This bit is set when the error count is 3 and
USB_FM_CTRL (+0x2C) is 1, or when the error count is 1 and USB_FM_CTRL (+0x2C) is 0.
HOST mode only. This bit is set when the NAK count exceeds the IN-NAK Timeout Setting
USB FM control register
7
6
Name
TOG_BIT
Type
Reset
R/W
0
5
USB_FM_CTRL
4
3
2
1
0
SUC_ERR_E EPT0_TX_O EPT0_RX_O FASTMODE
N
DD
DD
_EN
R/W
R
R
R/w
1
0
0
0
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DMA_TX_EN
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FAST MODE ONLY
TOG_BIT
Data toggle bit. This bit indicates whether the type of data transmitted or received by hardware was
DATA0 or DATA1.
0:
DATA0
1:
DATA1
EP0_TX_ODD
Endpoint 0 TX ODD. This bit is set when using the TX ODD BDT.
EP0_RX_ODD
Endpoint 0 RX ODD. This bit is set when using the RX ODD BDT.
FASTMODE_EN
Enable Fast Mode operation. This bit is reset by hardware after the transfer is complete.
Bit
Name
Type
Reset
7
70000034h
Bit
Name
Type
Reset
7
USB_FM_PKT_CN
T_L
USB FM transfer counter register (low byte)
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70000030h
6
5
4
3
PKT_CNT[7:0]
RO
0
2
USB FM transfer counter register (high byte)
6
5
4
3
PKT_CNT[15:8]
RO
0
1
0
USB_FM_PKT_CN
T_H
2
1
0
FAST MODE ONLY
PKT_CNT
These 2 registers combined specify the number of 64-byte packets transferred.
70000038h
7
MT
K
Bit
Name
Type
Reset
USB_FM_TIMEOU
T
USB FM timeout setting register (high byte)
6
5
4
3
NAK_TIMEOUT[7:0]
R/W
1
2
1
0
FAST MODE ONLY
NAK_TIMEOUT
HOST mode only. Transfer timeout setting = 64ms * NAK_TIMEOUT
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7000003Ch
Bit
USB_FM_STAT
US
USB FM status register
7
6
5
4
Name
Type
Reset
3
2
1
0
EPT2_TX_O EPT2_RX_O EPT1_TX_O EPT1_RX_O
DD
DD
DD
DD
R
R
R
R
0
0
0
0
USB_
FM_ADD_STAT
USB FM additional status register
7
6
5
4
ENDPT[3:0]
RO
0
Re
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Bit
Name
Type
Reset
fo
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FAST MODE ONLY
EP2_TX_ODD Endpoint 2 TX ODD.
EP2_RX_ODD Endpoint 2 RX ODD.
EP1_TX_ODD Endpoint 1 TX ODD.
EP1_RX_ODD Endpoint 1 RX ODD.
70000050h
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3
TX
RO
0
2
ODD
RO
0
1
0
FAST MODE ONLY
The additional status register stores the status of non-fast mode packet during fast mode operation, to allow the
intermixing of fast mode and non-fast mode packets.
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When entering fast mode, any existing status in USB_STAT register that has not yet been cleared is automatically
transferred to this register. The format of this status register is the same as the USB_STAT register, and a 4-byte
FIFO is also used in this case. When the FM_TOK_DONE bit in USB_FM_ERR_STAT is cleared, the
FM_ADD_STAT register is updated with the contents of the next value in the FIFO. FM_TOK_DONE is asserted
until the FIFO is empty.
ENDPT[3:0]
These four bits represents the endpoint address that received or transmitted the previous token, so that
the microprocessor can determine which BDT entry was updated by the last USB transaction.
TX
This bit indicates whether the last BDT updated was for a transmit data transfer (TX=1) or for a receive data
transfer (TX=0).
ODD
This bit indicates that the last buffer descriptor updated was in the odd bank of the BDT. See the earlier
section for more information on BDT address generation.
70000068h
Bit
Name
Type
Reset
7
TX_RES
R/W
0
USB_FM_ENDP
T
USB FM endpoint register
6
DMA_DONE
R/W
1
5
OWN
R/W
0
4
TX
R/W
0
3
2
1
0
ENDPT[3:0]
R/W
0
MT
K
FAST MODE ONLY
TX_RES DEVICE mode only. Tx residue. This setting is used when the transmit byte count is not a multiple of
64 bytes. By default, fast mode operates on 64B packet boundaries, and the fast mode-done indication is
asserted once the last 64-byte packet is sent: no further USB DMA sequence takes place. If this bit is set,
the fast mode controller issues an additional dma_tx_en request to the USB DMA controller after the last
64B-aligned packet is sent, even with fast mode-done indication still asserted, allowing the USB DMA
engine to fetch the next non-64B-aligned data. Software needs to take this situation into consideration.
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DMA_DONE DEBUG only. Test only.
OWN
DEBUG only. Own bit of fast mode. This bit is used when a token is received during fast mode but the
BDT is not yet valid, or the BDT is valid but fast mode has not yet been enabled. The bit clears itself once
fast mode completes.
TX
DEVICE mode only. The endpoint direction of fast mode. TX=1 indicates a transmit (IN) direction; TX=0
indicates a receive (OUT) direction.
7
6
5
fo
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Bit
USB_FM_INT_MAS
K
USB FM interrupt mask register
4
3
2
DMA_TX_EN_M DMA_RX_EN_M
ASK
ASK
R/W
R/W
0
0
Name
Type
Reset
FAST MODE ONLY
DMA_TX_MASK
DEBUG only.
DMA_RX_MASK
DEBUG only.
70000070h
7
PHY_RESUME_
Name
INT
Type
RO
Reset
0
6
0
When set, the dma_tx_en interrupt is enabled.
When set, the dma_rx_en interrupt is enabled.
USB extra register
Bit
1
Re
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7000006Ch
5
4
3
USB_EXTRA
2
1
0
PHY_RESU PHY_SUSPN TOGGLE_TE
ME_INT_EN
D
ST
R/W
R/W
R/W
0
0
0
70000080h
Bit
Name
Type
Reset
7
STALL
R/W
0
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PHY_RESUME_INT Interrupt indicating PHY Resume. This bit can only be asserted when PHY_SUSPND =1.
This bit clears itself when PHY_SUSPND=0.
PHY_RESUME_INT_EN When set, the PHY Resume interrupt is enabled.
PHY_SUSPND
When set, the PHY is suspended.
TOGGLE_TEST
DEBUG only. Toggles USB DP/DM output automatically.
USB Interrupt status register
6
ATTACH
R/W
0
5
RESUME
R/W
0
4
SLEEP
R/W
0
3
TOK_DNE
R/W
0
USB_INT_STAT
2
SOF_TOK
R/W
0
1
ERROR
R/W
0
0
USB_RST
R/W
0
MT
K
All status bits that are set are cleared by rewriting a 1.
STALL
The stall interrupt is used in target and host modes. In target mode the stall bit is asserted when a
STALL handshake is sent by the SIE.
In host mode this bit is set if the VUSB has detected a STALL acknowledgement during the handshake
phase of a USB transaction. This interrupt is useful for determining if the last USB transaction was
completed successfully or stalled.
ATTACH This bit is set if the VUSB has detected the attachment of a USB peripheral. This signal is only valid if
HOST_MODE_EN is true. This interrupt signifies that a peripheral is now present and must be
configured. The ATTACH interrupt is asserted if there have been no transitions on the USB for 2.5us
and the current bus state is not SE0.
RESUME This bit is set when a K-state is observed on the DP/DM signals for 2.5usec. The bit can indicate a
remote wake up signal on the USB bus. When not in suspend mode, disable this interrupt.
(Note: this bit is only useful if the PHY has not been powered down into suspend mode. Otherwise, use
USB_EXTRA register status bits to resume monitoring.)
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70000084h
USB Interrupt Enable register
7
STALL
R/W
0
STALL
ATTACH
RESUME
SLEEP
TOK_DNE
SOF_TOK
6
ATTACH
R/W
0
5
RESUME
R/W
0
4
SLEEP
R/W
0
USB_INT_ENB
3
TOK_DNE
R/W
0
2
SOF_TOK
R/W
0
1
ERROR
R/W
0
0
USB_RST
R/W
0
Setting this bit enables the STALL interrupt.
Setting this bit enables the ATTACH interrupt.
Setting this bit enables the RESUME interrupt.
Setting this bit enables the SLEEP interrupt.
Setting this bit enables the TOK_DNE interrupt.
Setting this bit enables the SOF_TOK interrupt.
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Bit
Name
Type
Reset
Re
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This bit is set if the VUSB has detected a constant idle on the USB bus signals for 3 ms. The sleep timer
is reset by activity on the USB bus.
TOK_DNE This bit is set when the current token being processing is complete. The microprocessor must
immediately read the STAT register to determine the End Point and BD used for this token. Clearing this
bit (by writing a one) causes the STAT register to be cleared or the STAT holding register to be loaded into
the STAT register. (Note: When Fast Mode is enabled, DO NOT look at this bit.)
SOF_TOK This bit is set if the VUSB has received a Start Of Frame (SOF) token. In host mode, this bit is set when
the SOF threshold is reached, so that software can prepare for the next SOF.
ERROR
This bit is set when any of the error conditions in the ERR_STAT register has occurred. The
microprocessor must then read the ERR_STAT register to determine the source of the error.
USB_RST This bit is set when the VUSB has decoded a valid USB reset. An asserted USB_RST bit informs the
microprocessor to write 0x00 into the address register and enable endpoint 0. USB_RST is set once a
USB reset has been detected for 2.5 microseconds, and is not asserted again until the USB reset condition
has been removed, and then reasserted.
ERROR
Setting this bit enables the ERROR interrupt.
USB_RST Setting this bit enables the USB_RST interrupt.
70000088h
USB Error Interrupt Status register
Bit
7
Name BTS_ERR
Type
R/W
Reset
0
6
5
DMA_ERR
R/W
0
4
BTO_ERR
R/W
0
3
DFN8
R/W
0
USB_ERR_STAT
2
CRC16
R/W
0
1
CRC5/EOF
R/W
0
0
PID_ERR
R/W
0
The Error Interrupt Status Register contains bits for each of the error sources within the VUSB. Each of these bits are
qualified with their respective error enable bits (See Error Enable Register page ). The error bits are OR'
ed together
and the result is sent to the ERROR bit of the INT_STAT register. Once an interrupt bit has been set, it can only be
cleared by writing a one to the respective interrupt bit. Each bit is set as soon as the error condition is detected.
Thus, the interrupt does not typically correspond with the end of a token being processed.
MT
K
(Note: All status bits that are set are cleared by writing a 1.)
BTS_ERR A bit stuff error has been detected. If set, the corresponding packet is rejected due to a bit stuff error.
DMA_ERR This bit is set if the VUSB has requested a DMA access to read a new BDT but the bus is not available
before VUSB needs to receive or transmit data. If processing a TX transfer, a transmit data underflow
condition occurs. If processing an RX transfer, a receive data overflow condition occurs. This
interrupt is useful when developing device arbitration hardware for the microprocessor and VUSB to
minimize bus request and bus grant latency. This bit is also set if a data packet to or from the host is
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7000008Ch
BTS_ERR
DMA_ERR
BTO_ERR
DFN8
CRC16
CRC5/EOF
PID_ERR
6
5
DMA_ERR
R/W
0
4
BTO_ERR
R/W
0
3
DFN8
R/W
0
USB_ERR_ENB
2
CRC16
R/W
0
1
CRC5/EOF
R/W
0
0
PID_ERR
R/W
0
Setting this bit enables the BTS_ERR interrupt.
Setting this bit enables the DMA_ERR interrupt.
Setting this bit enables the BTO_ERR interrupt.
Setting this bit enables the DFN8_ERR interrupt.
Setting this bit enables the CRC16 interrupt.
Setting this bit enables the CRC5/EOF_ERR interrupt.
Setting this bit enables the PID_ERR interrupt.
70000090h
Bit
Name
Type
Reset
USB Error Interrupt Enable register
7
BTS_ERR
R/W
0
7
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Name
Type
Reset
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larger than the allocated buffer size in the BDT. In this case the data packet is truncated as it is placed
into the buffer memory.
BTO_ERR This bit is set if a bus turnaround timeout error has occurred. This VUSB uses a bus turnaround timer to
keep track of the amount of time elapsed between the token and data phases of a SETUP or OUT TOKEN,
or between the data and handshake phases of a IN TOKEN. If more than 16 bit times are counted from
the previous EOP before a transition from IDLE, a bus turnaround timeout error occurs.
DFN8
The data field received is not a multiple of 8 bits. The USB Specification 1.0 specifies that the data field
must be an integral number of bytes. If the data field is not an integral number of bytes, this bit is set.
CRC16
The CRC16 failed. If set, the data packet was rejected due to a CRC16 error.
(Note: When in HOST MODE, ignore this bit. Look at the BDT TOK_PID entries instead to
determine error conditions.)
CRC5/EOF This error interrupt has two functions. When the VUSB is operating in peripheral mode
(HOST_MODE_EN=0) this interrupt detects a CRC5 error in token packets generated by the host. If set,
the token packet was rejected due to a CRC5 error. When the VUSB is operating in host mode
(HOST_MODE_EN=1), this interrupt detects End of Frame (EOF) error conditions. This condition
occurs when the VUSB is transmitting or receiving data and the SOF counter has reached zero. This
interrupt is useful when developing USB packet scheduling software to ensure that no USB transactions
cross into the start of the next frame.
PID_ERR
The PID check field failed.
USB Status register
6
5
4
3
TX
RO
0
ENDPT[3:0]
RO
0
USB_ STAT
2
ODD
RO
0
1
0
MT
K
The Status Register reports the transaction status within the VUSB. When the microprocessor has received a
TOK_DNE interrupt, the Status Register should be read to determine the status of the previous endpoint
communication. The data in the status register is valid when the TOK_DNE interrupt bit is asserted. The STAT
register acts as a read window into a status FIFO maintained by the VUSB. When the VUSB uses a BD, the status
register is updated. If another USB transaction is performed before the TOK_DNE interrupt is serviced the VUSB
stores the status of the next transaction in the STAT FIFO. Thus, the STAT register is actually a 4-byte FIFO that
allows the microprocessor to process one transaction while the SIE is processing the next. Clearing the TOK_DNE bit
in the INT_STAT register causes the SIE to update the STAT register with the contents of the next STAT value. If
the data in the STAT holding register is valid, the SIE immediately reasserts the TOK_DNE interrupt.
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ENDPT[3:0]
These four bits encode the endpoint address that received or transmitted the previous token, allowing
the microprocessor to determine which BDT entry was updated by the last USB transaction.
TX
This bit indicates whether the last BDT updated was a transmit transfer (TX=1), or a receive data transfer
(TX=0).
ODD
This bit indicates that the last buffer descriptor updated was in the odd bank of the BDT. See earlier section
for more information on BDT address generation.
USB Control register
Bit
7
6
Name
JSTATE
SE0
Type
Reset
R/W
0
R/W
0
5
TXDSUSPEN
D/
TOKENBUSY
R/W
0
USB_CTL
4
3
2
RESET
HOST_MOD
E EN
RESUME
R/W
0
R/W
0
R/W
0
1
0
ODD_RST
USB_EN /
SOF_EN
R/W
0
R/W
0
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70000094h
Re
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JSTATE Live USB differential receiver JSTATE signal. The polarity of this signal is affected by the current state of
LS_EN (See the Address Register description below).
SE0
Live USB Single Ended Zero signal.
TXDSUSPEND / TOKENBUSY
This dual use control signal is used to access TXD_SUSPEND when the VUSB is a target, and Token Busy
when the VUSB is in host mode.
The TXD Suspend bit informs the processor that the SIE has disabled packet transmission and reception.
Clearing this bit allows the SIE to continue token processing. This bit is set by the SIE when a Setup Token
is received allowing software to dequeue any pending packet transactions in the BDT before resuming token
processing.
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The Token Busy bit informs the host processor that the VUSB is busy executing a USB token and that no
more token commands should be written to the Token Register. Software must check this bit before writing
any tokens to the Token Register to ensure that token command are not lost.
MT
K
RESET Setting this bit enables the VUSB to generate USB reset signaling, allowing the VUSB to reset USB
peripherals. This control signal is only valid in host mode, (i.e. HOST_MDOE_EN=1). Software must set
RESET=1 for the required amount of time and then clear it to 0 to end reset signaling. For more
information on RESET signaling see Section 7.1.4.3 of the USB specification version 1.0.
HOST_MODE_EN Setting this bit enables the VUSB to operate in host mode. In host mode the VUSB performs
USB transactions under the programmed control of the host processor.
RESUME
Setting this bit allows the VUSB to execute resume signaling, allowing the VUSB to perform remote
wake-up. Software must set RESUME=1 for the required amount of time and then clear it to 0. If the
HOST_MODE_EN bit is set, the VUSB appends a Low Speed End of Packet to the Resume signal when the
RESUME bit is cleared. For more information on RESUME signaling see Section 7.1.4.5 of the USB
specification version 1.0.
ODD_RST Setting this bit resets all the BDT ODD ping/pong bits to 0 which then specify the EVEN BDT bank.
USB_EN / SOF_EN Setting this bit enables the VUSB; clearing the bit disables the VUSB. Setting this bit causes
the SIE to reset all of its ODD bits to the BDTs. Thus, setting this bit resets much of the logic in the SIE.
When host mode is enabled clearing this bit causes the SIE to stop sending SOF tokens.
70000098h
Bit
Name
Type
Reset
7
LS_EN
R/W
0
USB Address register
6
5
USB_ADDR
4
3
ADDR[6:0]
R/W
0
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MT6228 GSM/GPRS Baseband Processor Data Sheet
The Low Speed enable bit informs the VUSB that the next token command written to the token register
must be performed at low speed. This indication enables the VUSB to perform necessary preparations
for low speed data transmissions.
ADDR[6:0] This 7-bit value defines the USB address that the VUSB decodes in peripheral mode, or transmits when in
host mode.
700000B0h
Bit
Name
Type
Reset
5
4
BDT_BA [15:8]
R/W
0
USB BDT page 2 register
7
700000B4h
Bit
Name
Type
Reset
6
6
5
6
5
2
1
0
USB_BDT_PAG
E_02
4
BDT_BA [23:16]
R/W
0
USB BDT page 3 register
7
3
fo
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7
3
2
1
0
USB_BDT_PAG
E_03
4
BDT_BA [31:24]
R/W
0
3
2
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Bit
Name
Type
Reset
USB_BDT_PAG
E_01
USB BDT page 1 register
Re
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7000009Ch
1
0
BDT_BA[31:8] These 3 registers combined forms the BDT_PAGE pointer. Set these bytes as follows:
USB_BDT_PAGE_01 = 0x0
USB_BDT_PAGE_02 = 0x0
USB_BDT_PAGE_03 = 0xBD
700000A0h
Bit
Name
Type
Reset
7
6
5
4
3
2
1
0
FRM[7:0]
RO
0
700000A4h
Bit
Name
Type
Reset
USB_FRM_NU
ML
USB Frame number low byte register
7
USB_FRM_NU
MH
USB Frame number high byte register
6
5
4
3
2
1
FRM[10:8]
RO
0
0
MT
K
FRM[10:0] These 2 registers combined represent the 11-bit frame number. The registers are updated with the
current frame number whenever a SOF TOKEN is received.
700000A8h
Bit
7
USB Token register
6
5
USB_TOKEN
4
3
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Name
Type
Reset
TOKEN_PID
R/W
0
TOKEN_ENDPT
R/W
0
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fo
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The Token Register is used when performing USB transactions when in host mode (HOST_MODE_EN=1). When
the host processor wishes to execute a USB transaction to a peripheral, it writes the TOKEN type and endpoint to this
register. Once this register has been updated the VUSB begins the specified USB transaction to the address contained
in the Address Register. The host processor must check that the TOKEN_BUSY bit in the control register is not set
before performing a write to the Token Register: checking ensures that token commands are not overwritten before they
can be executed. The address register and endpoint control register 0 are also used when performing a token
command and therefore must also be updated before the Token Register. The address register is used to select the
correct USB peripheral address to transmit by the token command. The endpoint control register determines the
handshake and retry policies used during the transfer.
TOKEN_PID
700000ACh
7
6
5
4
USB_SOF_THL
D
3
2
1
0
CNT[7:0]
R/W
0
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Bit
Name
Type
Reset
USB SOF threshold register
Re
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This 4-bit value is the token type that is executed by the VUSB. Valid tokens are:
TOKEN_PID
TOKEN type
Description
0001
OUT
VUSB performs an OUT (TX) Transaction
1001
IN
VUSB performs an IN (RX) Transaction
1101
SETUP
VUSB performs a SETUP (TX) Transaction
TOKEN_ENDPT
This 4-bit value determines the Endpoint address for the token command. The 4-bit value that
is written must be a valid endpoint.
The Start Of Frame (SOF) Threshold Registers are used only in HOST_MODE. When HOST_MODE is enabled, the
14-bit SOF counter counts the interval between SOF frames. The SOF must be transmitted every millisecond so the
SOF counter is loaded with a value of 12000 since it is based on a 12MHz internal counter. When the SOF counter
reaches zero, a SOF token is transmitted. The SOF threshold register is used to program the number of USB byte
times before the SOF to stop initiating token packet transactions. This register must be set to a value that ensures that
other packets are not actively being transmitted when the SOF timer count reaches zero. When the SOF counter
reaches the threshold value, no more tokens are transmitted until after the SOF has been transmitted. The value
programmed into the threshold register must reserve enough time to ensure that the worst case transaction completes.
In general the worst case transaction is an IN token followed by a data packet from the target, followed by the response
from the host. The actual time required is a function of the maximum packet size on the bus. Typical values for the
SOF threshold are:
Time (byte times)
64
74
32
42
16
26
8
18
MT
K
Package size (bytes)
CNT[7:0]
These bits represents the SOF count threshold in BYTE times.
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700000C0h~
700000FFh
USB Endpoint Control register
Bit
7
6
HOST_WO_
RETRY_DIS
Name
HUB
Type
R/W
R/W
0
0
Reset
5
4
USB_EP_CTLN
3
EP_CTL_DIS EP_RX_EN
R/W
0
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R/W
0
2
1
EP_TX_EN
EP_STALL
R/W
0
R/W
0
0
EP_HSHK
R/W
0
Re
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The Endpoint Control Registers contains the endpoint control bits for each of the 16 endpoints available on USB for a
decoded address. These four bits define all of the control necessary for any one endpoint. The formats for these
registers are shown in the table on the following page. Endpoint 0 (ENDP0) is associated with control pipe 0 which is
required by USB for all functions. Therefore, after a USB_RST interrupt has been received the microprocessor must
set ENDPT0 to contain 0x0D. In host mode ENDPT0 is used to determine the handshake, retry and low-speed
characteristics of the host transfer. For host mode control, bulk and interrupt transfers, the EP_HSHK bit must be set
to 1; for Isochronous transfers the EP_HSHK must be set to 0. Common values for ENDPT0 in host mode are 0x4D
for Control, Bulk and Interrupt transfers, and 0x4C for Isochronous transfers.
700000410h
7
USB DMA enable
MT
K
Bit
Name
Type
Reset
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HOST_WO_HUB
HOST mode only. This bit is only present in the control register for endpoint 0 (endpt0_rg).
When this bit is set, the host can communicate with a directly connected low-speed device. When
cleared, the host produces a PRE_PID then switches to low-speed signaling when sending a token to
a low-speed device, as required for communication with a low-speed device via a hub.
RETRY_DIS
HOST mode only. This bit is only present in the control register for endpoint 0 (endpt0_rg).
When this bit is set, the host does not reattempt NAK’ed transactions. When a transaction is
NAK’ed, the BDT PID field is updated with the NAK pid, and the token done interrupt is set. When
this bit is cleared, NAK’ed transactions are retried in hardware. This bit must be set when the host
is attempting to poll an interrupt endpoint.
EP_CTL_DIS, EP_RX_EN, EP_TX_EN
These 3 bits define if an endpoint is enabled and the direction of the endpoint. The endpoint enable/direction
control is defined as follows:
ep_ctl_dis ep_rx_en
ep_tx_en
endpoint en / direction control
X
0
0
Disable Endpoint
X
0
1
Enable Endpoint for TX transfers only
X
1
0
Enable Endpoint for RX transfers only
1
1
1
Enable Endpoint for both RX and TX transfers
0
1
1
Enable Endpoint for RX and TX and control transfers
EP_STALL
When set to 1, this bit indicates that the endpoint is stalled. This bit has priority over all other
control bits in the End Point Enable register, but is only valid if EP_TX_EN=1 or EP_RX_EN=1.
Any access to this endpoint causes the VUSB to return a STALL handshake. Once an endpoint is
stalled, intervention from the Host Controller is required.
EP_HSHK
Setting this bit determines if an endpoint performs handshaking during a transaction to this endpoint.
This bit is generally set to 1 unless the endpoint is an Isochronous endpoint.
6
5
4
3
2
TX2_DMA_EN RX2_DMA_EN
W
W
0
0
USB_DMA_EN
1
0
TX1_DMA_EN RX1_DMA_EN
W
W
0
0
These are 1 shot signal.
TX2_DMA_EN Setting this bit enablesTX2 DMA.
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RX2_DMA_EN Setting this bit enables RX2 DMA.
TX1_DMA_EN Setting this bit enables TX1 DMA.
RX1_DMA_EN Setting this bit enables RX1 DMA.
700000414h
Bit
Name
Type
Reset
USB DMA disable
7
6
5
4
USB_DMA_DIS
3
2
1
0
TX2_DMA_DIS RX2_DMA_DIS TX1_DMA_DIS RX1_DMA_DIS
W
W
W
W
0
0
0
0
USB_DMA_ADDR_CNTE
R_CLR
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Reset
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These are 1 shot signal.
TX2_DMA_DIS Setting this bit disables TX2 DMA.
RX2_DMA_DIS Setting this bit disables RX2 DMA.
TX1_DMA_DIS Setting this bit disables TX1 DMA.
RX1_DMA_DIS Setting this bit disables RX1 DMA.
700000414h
USB DMA address counter clear
7
6
5
4
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3
2
1
0
TX2_DMA_CLR RX2_DMA_CLR TX1_DMA_CLR RX1_DMA_CLR
W
W
W
W
0
0
0
0
7000041Ch
Bit
Name
Type
Reset
7
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These are 1 shot signals.
TX2_DMA_CLR
Setting this bit clears the TX2 DMA address pointer.
RX2_DMA_CLR
Setting this bit clears the RX2 DMA address pointer.
TX1_DMA_CLR
Setting this bit clears the TX1 DMA address pointer.
RX1_DMA_CLR
Setting this bit clears the RX1 DMA address pointer.
USB_DMA_FM_SELEC
T
USB DMA FM select register
6
5
4
3
2
1
0
DMA_FM_SEL
R/W
0
FAST MODE ONLY
DMA_FM_SEL Selects which USB DMA controller the FM controller should use.
00:
Use RX1 DMA
01:
Use TX1 DMA
10:
Use RX2 DMA
11:
Use TX1 DMA
70000420h
Bit
Name
7
USB_SOFT_RE
SET
USB Soft Reset
6
5
4
3
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Type
Reset
2
1
0
SOFT_RESE
T
W
0
SOFT_RESET Setting this bit to 1 invokes a synchronous soft reset. The asserted bit holds high for 4 clock counts,
therefore, software must not issue any read/write within 4T of this reset.
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70000450h
Bit
USB_PHY_CTR
L
USB PHY Control
7
6
5
4
3
2
Name
Type
Reset
1
PUSW2EB_
REG
R
0
DEBUG ONLY
MANUAL
R
0
When Manual =1, IPUSW2EB contains
Memory Stick and SD Memory Card Controller
Introduction
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The 2 register bits are used to manually control IPUSW2EB signal to PHY.
the value of IPUSW2EB_REG.
6.4
Revision 1.0
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The controller fully supports the Memory Stick bus protocol as defined in Format Specification version 2.0 of Memory
Stick Standard (Memory Stick PRO) and the SD Memory Card bus protocol as defined in SD Memory Card
Specification Part 1 Physical Layer Specification version 1.0 as well as the MultiMediaCard (MMC) bus protocol as
defined in MMC system specification version 2.2. Since SD Memory Card bus protocol is backward compatible to
MMC bus protocol, the controller is capable of working well as the host on MMC bus under control of proper firmware.
Furthermore, the controller also support SDIO card specification version 1.0 partially. However, the controller can only
be configured as either the host of Memory Stick or the host of SD/MMC Memory Card at one time. Hereafter, the
controller is also abbreviated as MS/SD controller. The following are the main features of the controller.
Interface with MCU by APB bus
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16/32-bit access on APB bus
16/32-bit access for control registers
32-bit access for FIFO
Shared pins for Memory Stick and SD/MMC Memory Card
Built-in 32 bytes FIFO buffers for transmit and receive, FIFO is shared for transmit and receive
Built-in CRC circuit
CRC generation can be disabled
DMA supported
Interrupt capabilities
Automatic command execution capability when an interrupt from Memory Stick
Data rate up to 26 Mbps in serial mode, 26x4 Mbps in parallel model, the module is targeted at 26 MHz
operating clock
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Serial clock rate on MS/SD/MMC bus is programmable
Card detection capabilities
Controllability of power for memory card
Not support SPI mode for MS/SD/MMC Memory Card
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Not support multiple SD Memory Cards
6.4.2
Overview
6.4.2.1
Pin Assignment
Revision 1.0
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No.
Name
SD_CLK
SD_DAT3
SD_DAT0
SD_DAT1
SD_DAT2
SD_CMD
SD_PWRON
SD_WP
Type
O
I/O/PP
I/O/PP
I/O/PP
I/O/PP
I/O/PP
O
SD_INS
I
I
MMC
CLK
DAT0
CMD
SD
CLK
CD/DAT3
DAT0
DAT1
DAT2
CMD
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Since the controller can only be configured as either the host of Memory Stick or the host of SD/MMC Memory Card at
one time, pins for Memory Stick and SD/MMC Memory Card are shared in order to save pin counts. The following
lists pins required for Memory Stick and SD/MMC Memory Card. Table 42 shows how they are shared. In Table 42,
all I/O pads have embedded both pull up and pull down resistor because they are shared by both the Memory Stick and
SD/MMC Memory Card. Pins 2,4,5,8 are only useful for SD/MMC Memory Card. Pull down resistor for these pins can
be used for power saving. All embedded pull-up and pull-down resistors can be disabled by programming the
corresponding control registers if optimal pull-up or pull-down resistors are required on the system board. The pin
VDDPD is used for power saving. Power for Memory Stick or SD/MMC Memory Card can be shut down by
programming the corresponding control register. The pin WP (Write Protection) is only valid when the controller is
configured for SD/MMC Memory Card. It is used to detect the status of Write Protection Switch on SD/MMC Memory
Card.
MS
SCLK
SDIO
MSPRO
SCLK
DAT3
DAT0
DAT1
BS
BS
INS
INS
Description
Clock
Data Line [Bit 3]
Data Line [Bit 0]
Data Line [Bit 1]
Data Line [Bit 2]
Command Or Bus State
VDD ON/OFF
6.4.2.2
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Table 42 Sharing of pins for Memory Stick and SD/MMC Memory Card Controller
Card Detection
For Memory Stick, the host or connector should provide a pull up resistor on the signal INS. Therefore, the signal INS
will be logic high if no Memory Stick is on line. The scenario of card detection for Memory Stick is shown in Figure
12. Before Memory Stick is inserted or powered on, on host side SW1 shall be closed and SW2 shall be opened for
card detection. It is the default setting when the controller is powered on. Upon insertion of Memory Stick, the signal
INS will have a transition from high to low. Hereafter, if Memory Stick is removed then the signal INS will return to
logic high. If card insertion is intended to not be supported, SW1 shall be opened and SW2 closed always.
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For SD/MMC Memory Card, detection of card insertion/removal by hardware is also supported. Because a pull down
resistor with about 470 KΩ resistance which is impractical to embed in an I/O pad is needed on the signal CD/DAT3,
and it has to be capable of being connected or disconnected dynamically onto the signal CD during initialization period,
an additional I/O pad is needed to switch on/off the pull down resistor on the system board. The scenario of card
detection for SD/MMC Memory Card is shown in Figure 13. Before SD/MMC Memory Card is inserted or powered
on, SW1 and SW2 shall be opened for card detection on the host side. Meanwhile, pull down resistor RCD on system
board shall attach onto the signal CD/DAT3 by the output signal RCDEN. In addition, SW3 on the card is default to be
closed. Upon insertion of SD/MMC Memory Card, the signal CD/DAT3 will have a transition from low to high. If
SD/MMC Memory Card is removed then the signal CD/DAT3 will return to logic low. After the card identification
process, pull down resistor RCD on system board shall disconnect with the signal CD/DAT3 and SW3 on the card shall
be opened for normal operation.
Since the scheme above needs a mechanical switch such as a relay on system board, it is not ideal enough. Thus, a
dedicated pin “INS” is used to perform card insertion and removal for SD/MMC. The pin “INS” will connect to the pin
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Figure 12 Card detection for Memory Stick
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“VSS2” of a SD/MMC connector. Then the scheme of card detection is the same as that for MS. It is shown in Figure
12.
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Figure 13 Card detection for SD/MMC Memory Card
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6.4.3
Revision 1.0
Register Definitions
REGISTER ADDRESS REGISTER NAME
SYNONYM
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MSDC + 0000h
MS/SD Memory Card Controller Configuration Register MSDC_CFG
MSDC + 0004h
MS/SD Memory Card Controller Status Register
MSDC_STA
MSDC + 0008h
MS/SD Memory Card Controller Interrupt Register
MSDC_INT
MSDC + 000Ch
MS/SD Memory Card Controller Data Register
MSDC_DAT
MS/SD Memory Card Pin Status Register
MSDC_PS
MS/SD Memory Card Controller IO Control Register
MSDC_IOCON
MSDC + 0020h
SD Memory Card Controller Configuration Register
SDC_CFG
MSDC + 0024h
SD Memory Card Controller Command Register
SDC_CMD
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MSDC + 00010h
MSDC + 00014h
SD Memory Card Controller Argument Register
SDC_ARG
SD Memory Card Controller Status Register
SDC_STA
MSDC + 0030h
SD Memory Card Controller Response Register 0
SDC_RESP0
MSDC + 0034h
SD Memory Card Controller Response Register 1
SDC_RESP1
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MSDC + 0028h
MSDC + 002Ch
MSDC + 0038h
SD Memory Card Controller Response Register 2
SDC_RESP2
MSDC + 003Ch
SD Memory Card Controller Response Register 3
SDC_RESP3
MSDC + 0040h
SD Memory Card Controller Command Status Register
SDC_CMDSTA
MSDC + 0044h
SD Memory Card Controller Data Status Register
SDC_DATSTA
SD Memory Card Status Register
SDC_CSTA
SD Memory Card IRQ Mask Register 0
SDC_IRQMASK0
MSDC + 0050h
SD Memory Card IRQ Mask Register 1
SDC_IRQMASK1
MSDC + 0054h
SDIO Configuration Register
SDIO_CFG
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MSDC + 0048h
MSDC + 004Ch
MSDC + 0058h
SDIO Status Register
SDIO_STA
MSDC + 0060h
Memory Stick Controller Configuration Register
MSC_CFG
MSDC + 0064h
Memory Stick Controller Command Register
MSC_CMD
MSDC + 0068h
Memory Stick Controller Auto Command Register
MSC_ACMD
MSDC + 006Ch
Memory Stick Controller Status Register
MSC_STA
Table 43 MS/SD Controller Register Map
6.4.3.1
Global Register Definitions
MSDC+0000h
Bit
31
30
MS/SD Memory Card Controller Configuration
Register
29
28
27
26
25
24
Name
FIFOTHD
PRCFG2
PRCFG1
Type
Reset
Bit
R/W
0001
14
13
R/W
01
R/W
01
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15
12
11
Name
SCLKF
Type
Reset
R/W
00000000
10
9
8
23
21
VDDP
PRCFG0
D
R/W
R/W
10
0
7
6
5
SCLK
STDB
CRED
ON
Y
R/W R/W R/W
0
0
1
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22
MSDC_CFG
20
19
18
17
RCDE DIRQ PINE DMAE
N
EN
N
N
R/W R/W R/W R/W
0
0
0
0
4
3
2
1
CLKS
NOCR
RST
RED
RC
C
R/W
W
R/W R/W
0
0
0
0
16
INTE
N
R/W
0
0
MSD
C
R/W
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The register is for general configuration of the MS/SD controller. Note that MSDC_CFG[31:16] can be accessed by
16-bit APB bus access.
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MSDC The register bit is used to configure the controller as the host of Memory Stick or as the host of SD/MMC
Memory card. The default value is to configure the controller as the host of Memory Stick.
0 Configure the controller as the host of Memory Stick
1 Configure the controller as the host of SD/MMC Memory card
RED Rise Edge Data. The register bit is used to determine that serial data input is latched at the falling edge or the
rising edge of serial clock. The default setting is at the rising edge. If serial data has worse timing, set the
register bit to ‘1’. When memory card has worse timing on return read data, set the register bit to ‘1’.
0 Serial data input is latched at the rising edge of serial clock.
1 Serial data input is latched at the falling edge of serial clock.
NOCRC
CRC Disable. A ‘1’ indicates that data transfer without CRC is desired. For write data block, data will be
transmitted without CRC. For read data block, CRC will not be checked. It is for testing purpose.
0 Data transfer with CRC is desired.
1 Data transfer without CRC is desired.
RST
Software Reset. Writing a ‘1’ to the register bit will cause internal synchronous reset of MS/SD controller, but
does not reset register settings.
0 Otherwise
1 Reset MS/SD controller
CLKSRC The register bit specifies which clock is used as source clock of memory card. If MUC clock is used, the
fastest clock rate for memory card is 52/2=26MHz. If USB clock is used, the fastest clock rate for memory
card is 48/2=24MHz.
0 Use MCU clock as source clock of memory card.
1 Use USB clock as source clock of memory card.
STDBY Standby Mode. If the module is powered down, operating clock to the module will be stopped. At the same
time, clock to card detection circuitry will also be stopped. If detection of memory card insertion and removal
is desired, write ‘1’ to the register bit. If interrupt for detection of memory card insertion and removal is
enabled, interrupt will take place whenever memory is inserted or removed.
0 Standby mode is disabled.
1 Standby mode is enabled.
CRED Card Rise Edge Data. The register bit is used to determine that serial data from memory card is output at the
falling edge or the rising edge of serial clock. The default setting is at the falling edge.
0 Serial data is output at the falling edge of serial clock.
1 Serial data is output at the rising edge of serial clock.
SCLKON Serial Clock Always On. It is for debugging purpose.
0 Not to have serial clock always on.
1 To have serial clock always on.
SCLKF The register field controls clock frequency of serial clock on MS/SD bus. Denote clock frequency of MS/SD
bus serial clock as fslave and clock frequency of the MS/SD controller as fhost which is 104 or 52 MHz. Then the
value of the register field is as follows. Note that the allowable maximum frequency of fslave is 26MHz.
00000000b fslave =(1/2) * fhost
00000001b fslave = (1/(4*1)) * fhost
00000010b fslave = (1/(4*2)) * fhost
00000011b fslave = (1/(4*3))* fhost
…
00010000b fslave = (1/(4*16))* fhost
…
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11111111b fslave = (1/(4*255)) * fhost
INTEN Interrupt Enable. Note that if interrupt capability is disabled then application software must poll the status of
the register MSDC_STA to check for any interrupt request.
0 Interrupt induced by various conditions is disabled, no matter the controller is configured as the host of
either SD/MMC Memory Card or Memory Stick.
1 Interrupt induced by various conditions is enabled, no matter the controller is configured as the host of
either SD/MMC Memory Card or Memory Stick.
DMAEN
DMA Enable. Note that if DMA capability is disabled then application software must poll the status of the
register MSDC_STA for checking any data transfer request. If DMA is desired, the register bit must be set
before command register is written.
0 DMA request induced by various conditions is disabled, no matter the controller is configured as the host
of either SD/MMC Memory Card or Memory Stick.
1 DMA request induced by various conditions is enabled, no matter the controller is configured as the host
of either SD/MMC Memory Card or Memory Stick.
PINEN Pin Interrupt Enable. The register bit is used to control if the pin for card detection is used as an interrupt
source.
0 The pin for card detection is not used as an interrupt source.
1 The pin for card detection is used as an interrupt source.
DIRQEN
Data Request Interrupt Enable. The register bit is used to control if data request is used as an interrupt
source.
0 Data request is not used as an interrupt source.
1 Data request is used as an interrupt source.
RCDEN The register bit controls the output pin RCDEN that is used for card identification process when the controller
is for SD/MMC Memory Card. Its output will control the pull down resistor on the system board to connect or
disconnect with the signal CD/DAT3.
0 The output pin RCDEN will output logic low.
1 The output pin RCDEN will output logic high.
VDDPD The register bit controls the output pin VDDPD that is used for power saving. The output pin VDDPD will
control power for memory card.
0 The output pin VDDPD will output logic low. The power for memory card will be turned off.
1 The output pin VDDPD will output logic high. The power for memory card will be turned on.
PRCFG0 Pull Up/Down Register Configuration for the pin WP. The default value is 10.
00 Pull up resistor and pull down resistor in the I/O pad of the pin WP are all disabled.
01 Pull down resistor in the I/O pad of the pin WP is enabled.
10 Pull up resistor in the I/O pad of the pin WP is enabled.
11 Use keeper of IO pad.
PRCFG1 Pull Up/Down Register Configuration for the pin CMD/BS. The default value is 0b01.
00 Pull up resistor and pull down resistor in the I/O pad of the pin CMD/BS are all disabled.
01 Pull down resistor in the I/O pad of the pin CMD/BS is enabled.
10 Pull up resistor in the I/O pad of the pin CMD/BS is enabled.
11 Use keeper of IO pad.
PRCFG2 Pull Up/Down Register Configuration for the pins DAT0, DAT1, DAT2, DAT3. The default value is 0b01.
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00 Pull up resistor and pull down resistor in the I/O pads o the pins DAT0, DAT1, DAT2, DAT3. are all
disabled.
01 Pull down resistor in the I/O pads of the pins DAT0, DAT1, DAT2, DAT3 and WP. is enabled.
10 Pull up resistor in the I/O pads of the pins DAT0, DAT1, DAT2, DAT3. is enabled.
11 Use keeper of IO pad.
FIFOTHD FIFO Threshold. The register field determines when to issue a DMA request. For write transactions, DMA
requests will be asserted if the number of free entries in FIFO are larger than or equal to the value in the
register field. For read transactions, DMA requests will be asserted if the number of valid entries in FIFO are
larger than or equal to the value in the register field. The register field must be set according to the setting of
data transfer count in DMA burst mode. If single mode for DMA transfer is used, the register field shall be set
to 0b0001.
0000 Invalid.
0001 Threshold value is 1.
0010 Threshold value is 2.
…
1000 Threshold value is 8.
others Invalid
MSDC+0004h MS/SD Memory Card Controller Status Register
Bit
15
Name BUSY
Type
Reset
R
0
14
FIFOC
LR
W
-
13
12
11
10
9
8
7
6
5
4
MSDC_STA
3
2
1
0
FIFOCNT
INT
DRQ
BE
BF
RO
0000
RO
0
RO
0
RO
0
RO
0
The register contains the status of FIFO, interrupts and data requests.
BF
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The register bit indicates if FIFO in MS/SD controller is full.
0 FIFO in MS/SD controller is not full.
1 FIFO in MS/SD controller is full.
BE
The register bit indicates if FIFO in MS/SD controller is empty.
0 FIFO in MS/SD controller is not empty.
1 FIFO in MS/SD controller is empty.
DRQ The register bit indicates if any data transfer is required. While any data transfer is required, the register bit
still will be active even if the register bit DIRQEN in the register MSDC_CFG is disabled. Data transfer can
be achieved by DMA channel alleviating MCU loading, or by polling the register bit to check if any data
transfer is requested. While the register bit DIRQEN in the register MSDC_CFG is disabled, the second
method is used.
0 No DMA request exists.
1 DMA request exists.
INT
The register bit indicates if any interrupt exists. While any interrupt exists, the register bit still will be active
even if the register bit INTEN in the register MSDC_CFG is disabled. MS/SD controller can interrupt MCU
by issuing interrupt request to Interrupt Controller, or software/application polls the register endlessly to check
if any interrupt request exists in MS/SD controller. While the register bit INTEN in the register MSDC_CFG is
disabled, the second method is used. For read commands, it is possible that timeout error takes place. Software
can read the status register to check if timeout error takes place without OS time tick support or data request is
asserted. Note that the register bit will be cleared when reading the register MSDC_INT.
0 No interrupt request exists.
1 Interrupt request exists.
FIFOCNT
FIFO Count. The register field shows how many valid entries are in FIFO.
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0000 There is 0 valid entry in FIFO.
0001 There is 1 valid entry in FIFO.
0010 There are 2 valid entries in FIFO.
…
1000 There are 8 valid entries in FIFO.
others Invalid
FIFOCLR Clear FIFO. Writing ‘1’ to the register bit will cause the content of FIFO clear and reset the status of FIFO
controller.
0 No effect on FIFO.
1 Clear the content of FIFO clear and reset the status of FIFO controller.
BUSY Status of the controller. If the controller is in busy state, the register bit will be ‘1’. Otherwise ‘0’.
0 The controller is in busy state.
1 The controller is in idle state.
Bit
15
14
13
Name
Type
Reset
12
11
10
9
8
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MSDC+0008h MS/SD Memory Card Controller Interrupt Register
MSDC_INT
7
6
5
4
3
2
1
0
SDIOI SDR1 MSIFI SDMC SDDA SDCM PINIR
DIRQ
RQ BIRQ RQ
IRQ TIRQ DIRQ
Q
RC
RC
RC
RC
RC
RC
RC
RC
0
0
0
0
0
0
0
0
The register contains the status of interrupts. Note that the register still show status of interrupt even though interrupt is
disabled, that is, the register bit INTEN of the register MSDC_CFG is set to ‘0. It implies that software interrupt can be
implemented by polling the register bit INT of the register MSDC_STA and this register. However, if hardware
interrupt is desired, remember to clear the register before setting the register bit INTEN of the register
MSDC_CFG to ‘1’. Or undesired hardware interrupt arisen from previous interrupt status may take place.
DIRQ
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Data Request Interrupt. The register bit indicates if any interrupt for data request exists. Whenever data request
exists and data request as an interrupt source is enabled, i.e., the register bit DIRQEN in the register
MSDC_CFG is set to ‘1’, the register bit will be active. It will be reset when reading it. For software, data
requests can be recognized by polling the register bit DRQ or by data request interrupt. Data request interrupts
will be generated every FIFOTHD data transfers.
0 No Data Request Interrupt.
1 Data Request Interrupt occurs.
PINIRQ Pin Change Interrupt. The register bit indicates if any interrupt for memory card insertion/removal exists.
Whenever memory card is inserted or removed and card detection interrupt is enabled, i.e., the register bit
PINEN in the register MSDC_CFG is set to ‘1’, the register bit will be set to ‘1’. It will be reset when the
register is read.
0 Otherwise.
1 Card is inserted or removed.
SDCMDIRQ
SD Bus CMD Interrupt. The register bit indicates if any interrupt for SD CMD line exists. Whenever
interrupt for SD CMD line exists, i.e., any bit in the register SDC_CMDSTA is active, the register bit will be
set to ‘1’ if interrupt is enabled. It will be reset when the register is read.
0 No SD CMD line interrupt.
1 SD CMD line interrupt exists.
SDDATIRQ SD Bus DAT Interrupt. The register bit indicates if any interrupt for SD DAT line exists. Whenever
interrupt for SD DAT line exists, i.e., any bit in the register SDC_ DATSTA is active, the register bit will be set
to ‘1’ if interrupt is enabled. It will be reset when the register is read.
0 No SD DAT line interrupt.
1 SD DAT line interrupt exists.
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SDMCIRQ SD Memory Card Interrupt. The register bit indicates if any interrupt for SD Memory Card exists.
Whenever interrupt for SD Memory Card exists, i.e., any bit in the register SDC_CSTA is active, the register
bit will be set to ‘1’ if interrupt is enabled. It will be reset when the register is read.
0 No SD Memory Card interrupt.
1 SD Memory Card interrupt exists.
MSIFIRQ MS Bus Interface Interrupt. The register bit indicates if any interrupt for MS Bus Interface exists.
Whenever interrupt for MS Bus Interface exists, i.e., any bit in the register MSC_STA is active, the register bit
will be set to ‘1’ if interrupt is enabled. It will be reset when the register MSDC_STA or MSC_STA is read.
0 No MS Bus Interface interrupt.
1 MS Bus Interface interrupt exists.
SDR1BIRQ SD/MMC R1b Response Interrupt. The register bit will be active when a SD/MMC command with R1b
response finishes and the DAT0 line has transition from busy to idle state. Single block write commands
with R1b response will cause the interrupt when the command completes no matter successfully or
with CRC error. However, multi-block write commands with R1b response do not cause the interrupt
because multi-block write commands are always stopped by STOP_TRANS commands.
STOP_TRANS commands (with R1b response) behind multi-block write commands will cause the
interrupt. Single block read command with R1b response will cause the interrupt when the command
completes but multi-block read commands do not. Note that STOP_TRANS commands (with R1b
response) behind multi-block read commands will cause the interrupt.
0 No interrupt for SD/MMC R1b response.
1 Interrupt for SD/MMC R1b response exists.
MSDC+000Ch MS/SD Memory Card Controller Data Register
31
30
29
28
27
26
25
15
14
13
12
11
10
9
24
23
DATA[31:16]
R/W
8
7
DATA[15:0]
R/W
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Bit
Name
Type
Bit
Name
Type
MSDC_DAT
22
21
20
19
18
17
16
6
5
4
3
2
1
0
The register is used to read/write data from/to FIFO inside MS/SD controller. Data access is in unit of 32 bits.
MSDC+0010h MS/SD Memory Card Pin Status Register
Bit
Name
Type
Reset
Bit
31
15
30
14
29
28
27
26
25
13
12
11
10
9
Name
CDDEBOUNCE
Type
Reset
RW
0000
24
CMD
RO
8
MSDC_PS
23
22
21
7
6
5
20
19
18
17
16
DAT
RO
4
3
2
1
0
PINC
POEN
PIN0
PIEN0 CDEN
HG
0
RC
RO R/W R/W R/W
0
1
0
0
0
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The register is used for card detection. When the memory card controller is powered on, and the system is powered on,
the power for the memory card is still off unless power has been supplied by the PMIC. Meanwhile, pad for card
detection defaults to pull down when the system is powered on. The scheme of card detection for MS is the same as
that for SD/MMC.
For detecting card insertion, first pull up INS pin, and then enable card detection and input pin at the same time. After
32 cycles of controller clock, status of pin changes will emerge. For detecting card removal, just keep enabling card
detection and input pin.
CDEN Card Detection Enable. The register bit is used to enable or disable card detection.
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0 Card detection is disabled.
1 Card detection is enabled.
PIEN0 The register bit is used to control input pin for card detection.
0 Input pin for card detection is disabled.
1 Input pin for card detection is enabled.
POEN0 The register bit is used to control output of input pin for card detection.
0 Output of input pin for card detection is disabled.
1 Output of input pin for card detection is enabled.
PIN0 The register shows the value of input pin for card detection.
0 The value of input pin for card detection is logic low.
1 The value of input pin for card detection is logic high.
PINCHG
Pin Change. The register bit indicates the status of card insertion/removal. If memory card is inserted or
removed, the register bit will be set to ‘1’ no matter pin change interrupt is enabled or not. It will be cleared
when the register is read.
0 Otherwise.
1 Card is inserted or removed.
CDDEBOUNCE The register field specifies the time interval for card detection de-bounce. Its default
value is 0. It means that de-bounce interval is 32 cycle time of 32KHz. The interval will extend one cycle
time of 32KHz by increasing the counter by 1.
DAT
Memory Card Data Lines.
CMD Memory Card Command Lines.
MSDC+0014h MS/SD Memory Card Controller IO Control Register
Bit
15
14
13
12
11
10
9
8
PRCFG3
Type
Reset
R/W
10
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Name
7
6
SRCF SRCF
G1
G0
R/W R/W
1
1
5
4
3
MSDC_IOCON
2
1
ODCCFG1
ODCCFG0
R/W
000
R/W
011
0
The register specifies Output Driving Capability and Slew Rate of IO pads for MSDC. The reset value is suggestion
setting. If output driving capability of the pins DAT0, DAT1, DAT2 and DAT3 is too large, it’s possible to arise ground
bounce and thus result in glitch on SCLK.
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ODCCFG0 Output driving capability the pins CMD/BS and SCLK
000
2mA
001
4mA
010
6mA
011
8mA
ODCCFG1 Output driving capability the pins DAT0, DAT1, DAT2 and DAT3
000
2mA
001
4mA
010
6mA
011
8mA
SRCFG0 Output driving capability the pins CMD/BS and SCLK
0 Fast Slew Rate
1 Slow Slew Rate
SRCFG1 Output driving capability the pins DAT0, DAT1, DAT2 and DAT3
0 Fast Slew Rate
1 Slow Slew Rate
PRCFG3 Pull Up/Down Register Configuration for the pin INS. The default value is 10.
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01
10
11
6.4.3.2
Pull up resistor and pull down resistor in the I/O pad of the pin INS are all disabled.
Pull down resistor in the I/O pad of the pin INS is enabled.
Pull up resistor in the I/O pad of the pin INS is enabled.
Use keeper of IO pad.
SD Memory Card Controller Register Definitions
MSDC+0020h SD Memory Card Controller Configuration Register
31
30
29
28
27
26
25
24
23
22
21
Name
DTOC
WDOD
Type
Reset
Bit
Name
Type
Reset
R/W
00000000
12
11
R/W
0000
14
13
BSYDLY
R/W
1000
10
9
8
7
6
5
BLKLEN
R/W
00000000000
4
19
18
17
16
MDL MDLE
SIEN
SDIO
W8
N
R/W R/W R/W R/W
0
0
0
0
3
2
1
0
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The register is used for configuring the MS/SD Memory Card Controller when it is configured as the host of SD
Memory Card. If the controller is configured as the host of Memory Stick, the contents of the register have no impact
on the operation of the controller. Note that SDC_CFG[31:16] can be accessed by 16-bit APB bus access.
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BLKLEN It refers to Block Length. The register field is used to define the length of one block in unit of byte in a data
transaction. The maximal value of block length is 2048 bytes.
000000000000
Reserved.
000000000001
Block length is 1 byte.
000000000010
Block length is 2 bytes.
…
011111111111
Block length is 2047 bytes.
100000000000
Block length is 2048 bytes.
BSYDLY The register field is only valid for the commands with R1b response. If the command has a response of
R1b type, MS/SD controller must monitor the data line 0 for card busy status from the bit time that is two
serial clock cycles after the command end bit to check if operations in SD/MMC Memory Card have finished.
The register field is used to expand the time between the command end bit and end of detection period to
detect card busy status. If time is up and there is no card busy status on data line 0, then the controller will
abandon the detection.
0000 No extend.
0001 Extend one more serial clock cycle.
0010 Extend two more serial clock cycles.
…
1111
Extend fifteen more serial clock cycle.
SIEN Serial Interface Enable. It should be enabled as soon as possible before any command.
0 Serial interface for SD/MMC is disabled.
1 Serial interface for SD/MMC is enabled.
MDLW8 Eight Data Line Enable. The register works when MDLEN is enabled. The register can be enabled only
when MultiMediaCard 4.0 is applied and detected by software application.
0 4-bit Data line is enabled.
1 8-bit Data line is enabled.
SDIO SDIO Enable.
0 SDIO mode is disabled
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1 SDIO mode is enabled
MDLEN Multiple Data Line Enable. The register can be enabled only when SD Memory Card is applied and detected
by software application. It is the responsibility of the application to program the bit correctly when an
MultiMediaCard is applied. If an MultiMediaCard is applied and 4-bit data line is enabled, then 4 bits will be
output every serial clock. Therefore, data integrity will fail.
0 4-bit Data line is disabled.
1 4-bit Data line is enabled.
WDOD Write Data Output Delay. The period from finish of the response for the initial host write command or the last
write data block in a multiple block write operation to the start bit of the next write data block requires at least
two serial clock cycles. The register field is used to extend the period (Write Data Output Delay) in unit of one
serial clock.
0000 No extend.
0001 Extend one more serial clock cycle.
0010 Extend two more serial clock cycles.
…
1111
Extend fifteen more serial clock cycle.
DTOC Data Timeout Counter. The period from finish of the initial host read command or the last read data block in a
multiple block read operation to the start bit of the next read data block requires at least two serial clock cycles.
The counter is used to extend the period (Read Data Access Time) in unit of 65,536 serial clock. See the
register field description of the register bit RDINT for reference.
00000000
Extend 65,536 more serial clock cycle.
00000001
Extend 65,536x2 more serial clock cycle.
00000010
Extend 65,536x3 more serial clock cycle.
…
11111111
Extend 65,536x 256 more serial clock cycle.
MSDC+0024h SD Memory Card Controller Command Register
Bit
31
30
15
14
Name
Type
Reset
Bit
29
28
27
26
25
24
23
22
21
20
19
18
17
13
12
11
10
9
8
7
6
BREA
K
R/W
0
5
4
3
2
1
Name INTC STOP RW
Type R/W
Reset
0
R/W
0
SDC_CMD
R/W
0
DTYPE
IDRT
RSPTYP
R/W
00
R/W
0
R/W
000
16
CMDF
AIL
R/W
0
0
CMD
R/W
000000
The register defines a SD Memory Card command and its attribute. Before MS/SD controller issues a transaction onto
SD bus, application shall specify other relative setting such as argument for command. After application writes the
register, MS/SD controller will issue the corresponding transaction onto SD serial bus. If the command is
GO_IDLE_STATE, the controller will have serial clock on SD/MMC bus run 128 cycles before issuing the command.
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CMD SD Memory Card command. It is totally 6 bits.
BREAK Abort a pending MMC GO_IRQ_MODE command. It is only valid for a pending GO_IRQ_MODE command
waiting for MMC interrupt response.
0 Other fields are valid.
1 Break a pending MMC GO_IRQ_MODE command in the controller. Other fields are invalid.
RSPTYP The register field defines response type for the command. For commands with R1 and R1b response, the
register SDC_CSTA (not SDC_STA) will update after response token is received. This register SDC_CSTA
contains the status of the SD/MMC and it will be used as response interrupt sources. Note that if CMD7 is
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used with all 0’s RCA then RSPTYP must be “000”. And the command “GO_TO_IDLE” also have
RSPTYP=’000’.
000 There is no response for the command. For instance, broadcast command without response and
GO_INACTIVE_STATE command.
001 The command has R1 response. R1 response token is 48-bit.
010 The command has R2 response. R2 response token is 136-bit.
011 The command has R3 response. Even though R3 is 48-bit response, but it does not contain CRC
checksum.
100 The command has R4 response. R4 response token is 48-bit. (Only for MMC)
101 The command has R5 response. R5 response token is 48-bit. (Only for MMC)
110 The command has R6 response. R6 response token is 48-bit.
111 The command has R1b response. If the command has a response of R1b type, MS/SD controller must
monitor the data line 0 for card busy status from the bit time that is two or four serial clock cycles after
the command end bit to check if operations in SD/MMC Memory Card have finished. There are two
cases for detection of card busy status. The first case is that the host stops the data transmission during
an active write data transfer. The card will assert busy signal after the stop transmission command end
bit followed by four serial clock cycles. The second case is that the card is in idle state or under a
scenario of receiving a stop transmission command between data blocks when multiple block write
command is in progress. The register bit is valid only when the command has a response token.
Note that the response type R4 and R5 mentioned above is for MMC only.
For SDIO, RSPTYP definition is different and shall be set to :
001 (i) CMD5 of SDIO is to be issued. (Where the response is defined as R4 in SDIO spec)
(ii) CMD52 or CMD53 for READ is to be issued. (Where the response is defined as R5 in SDIO
spec)
111 CMD52 for I/O abort or CMD53 for WRITE is to be issued (Where the response is defined as R5
in SDIO spec)
IDRT Identification Response Time. The register bit indicates if the command has a response with NID (that is, 5
serial clock cycles as defined in SD Memory Card Specification Part 1 Physical Layer Specification version
1.0) response time. The register bit is valid only when the command has a response token. Thus the register bit
must be set to ‘1’ for CMD2 (ALL_SEND_CID) and ACMD41 (SD_APP_OP_CMD).
0 Otherwise.
1 The command has a response with NID response time.
DTYPE The register field defines data token type for the command.
00 No data token for the command
01 Single block transaction
10 Multiple block transaction. That is, the command is a multiple block read or write command.
11 Stream operation. It only shall be used when an MultiMediaCard is applied.
RW
The register bit defines the command is a read command or write command. The register bit is valid only
when the command will cause a transaction with data token.
0 The command is a read command.
1 The command is a write command.
STOP The register bit indicates if the command is a stop transmission command. It should be set to 1 when
CMD12 (SD/MMC) or CMD52 with I/O abort (SDIO) is to be issued.
0 The command is not a stop transmission command.
1 The command is a stop transmission command.
INTC The register bit indicates if the command is GO_IRQ_STATE. If the command is GO_IRQ_STATE, the period
between command token and response token will not be limited.
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0 The command is not GO_IRQ_STATE.
1 The command is GO_IRQ_STATE.
CMDFAIL The register bit is used for controlling SDIO interrupt period when CRC error or Command/Data timeout
condition occurs. It is useful only when SDIO 4-bit mode is activated.
0 SDIO Interrupt period will re-start after a stop command (CMD12) or I/O abort command (CMD52) is
issued.
1 SDIO Interrupt period will re-start whenever DAT line is not busy.
31
30
29
28
27
26
25
15
14
13
12
11
10
9
24
23
ARG [31:16]
R/W
8
7
ARG [15:0]
R/W
22
21
20
6
5
4
19
18
17
16
3
2
1
0
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Bit
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Type
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MSDC+0028h SD Memory Card Controller Argument Register
The register contains the argument of the SD/MMC Memory Card command.
MSDC+002Ch SD Memory Card Controller Status Register
Bit
15
14
13
12
11
10
9
Name WP
Type
Reset
R
-
8
7
6
5
SDC_STA
4
3
2
1
0
R1BS
DATB CMDB SDCB
RSV
Y
USY USY USY
RO
RO
RO
RO
RO
0
0
0
0
0
The register contains various status of MS/SD controller as the controller is configured as the host of SD Memory Card.
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SDCBUSY The register field indicates if MS/SD controller is busy, that is, any transmission is going on CMD or DAT
line on SD bus.
0 MS/SD controller is idle.
1 MS/SD controller is busy.
CMDBUSY The register field indicates if any transmission is going on CMD line on SD bus.
0 No transmission is going on CMD line on SD bus.
1 There exists transmission going on CMD line on SD bus.
DATBUSY The register field indicates if any transmission is going on DAT line on SD bus. For those commands
without data but still involving DAT line, the register bit is useless. For example, if an Erase command is
issued, then checking if the register bit is ‘0’ before issuing next command with data would not
guarantee that the controller is idle. In this situation, use the register bit SDCBUSY.
0 No transmission is going on DAT line on SD bus.
1 There exists transmission going on DAT line on SD bus.
R1BSY
The register field shows the status of DAT line 0 for commands with R1b response.
0 SD/MMC Memory card is not busy.
1 SD/MMC Memory card is busy.
WP
It is used to detect the status of Write Protection Switch on SD Memory Card. The register bit shows the status
of Write Protection Switch on SD Memory Card. There is no default reset value. The pin WP (Write Protection)
is also only useful while the controller is configured for SD Memory Card.
1 Write Protection Switch ON. It means that memory card is desired to be write-protected.
0 Write Protection Switch OFF. It means that memory card is writable.
MSDC+0030h SD Memory Card Controller Response Register 0
Bit
Name
31
30
29
28
27
26
25
24
23
RESP [31:16]
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Type
Bit
Name
Type
15
14
13
12
11
10
9
RO
8
7
RESP [15:0]
RO
6
5
4
3
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0
The register contains parts of the last SD/MMC Memory Card bus response. See description for the register field
SDC_RESP3.
MSDC+0034h SD Memory Card Controller Response Register 1
31
30
29
28
27
26
25
15
14
13
12
11
10
9
24
23
RESP [63:48]
RO
8
7
RESP [47:32]
RO
22
21
20
6
5
4
19
18
17
16
3
2
1
0
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Bit
Name
Type
Bit
Name
Type
SDC_RESP1
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The register contains parts of the last SD/MMC Memory Card bus response. See description for the register field
SDC_RESP3.
MSDC+0038h SD Memory Card Controller Response Register 2
Bit
Name
Type
Bit
Name
Type
31
30
29
28
27
26
25
15
14
13
12
11
10
9
24
23
RESP [95:80]
RO
8
7
RESP [79:64]
RO
SDC_RESP2
22
21
20
19
18
17
16
6
5
4
3
2
1
0
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The register contains parts of the last SD/MMC Memory Card bus response. See description for the register field
SDC_RESP3.
MSDC+003Ch SD Memory Card Controller Response Register 3
Bit
Name
Type
Bit
Name
Type
31
30
15
14
29
28
27
26
13
12
11
10
25
24
23
22
RESP [127:112]
RO
9
8
7
6
RESP [111:96]
RO
SDC_RESP3
21
20
19
18
17
16
5
4
3
2
1
0
The register contains parts of the last SD/MMC Memory Card bus response. The register fields SDC_RESP0,
SDC_RESP1, SDC_RESP2 and SDC_RESP3 compose the last SD/MMC Memory card bus response. For response of
type R2, that is, response of the command ALL_SEND_CID, SEND_CSD and SEND_CID, only bit 127 to 0 of
response token is stored in the register field SDC_RESP0, SDC_RESP1, SDC_RESP2 and SDC_RESP3. For response
of other types, only bit 39 to 8 of response token is stored in the register field SDC_RESP0.
MSDC+0040h
Bit
15
14
SD Memory Card Controller Command Status
Register
13
12
11
10
9
8
7
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Type
Reset
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5
SDC_CMDSTA
4
3
2
1
0
RSPC
MMCI
CMDT CMD
RCER
RQ
O
RDY
R
RC
RC
RC
RC
0
0
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The register contains the status of MS/SD controller during command execution and that of MS/SD bus protocol after
command execution when MS/SD controller is configured as the host of SD/MMC Memory Card. The register will
also be used as interrupt sources. The register will be cleared when reading the register. Meanwhile, if interrupt is
enabled and thus interrupt caused by the register is generated, reading the register will deassert the interrupt.
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CMDRDY For command without response, the register bit will be ‘1’ once the command completes on SD/MMC bus.
For command with response, the register bit will be ‘1’ whenever the command is issued onto SD/MMC bus
and its corresponding response is received without CRC error.
0 Otherwise.
1 Command with/without response finish successfully without CRC error.
CMDTO
Timeout on CMD detected. A ‘1’ indicates that MS/SD controller detected a timeout condition while
waiting for a response on the CMD line.
0 Otherwise.
1 MS/SD controller detected a timeout condition while waiting for a response on the CMD line.
RSPCRCERR CRC error on CMD detected. A ‘1’ indicates that MS/SD controller detected a CRC error after
reading a response from the CMD line.
0 Otherwise.
1 MS/SD controller detected a CRC error after reading a response from the CMD line.
MMCIRQ MMC requests an interrupt. A ‘1’ indicates that a MMC supporting command class 9 issued an interrupt
request.
0 Otherwise.
1 A ‘1’ indicates that a MMC supporting command class 9 issued an interrupt request.
MSDC+0044h SD Memory Card Controller Data Status Register
Name
Type
Reset
15
14
13
12
11
10
9
8
7
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Bit
6
5
4
3
SDC_DATSTA
2
1
0
DATC
DATT BLKD
RCER
O
ONE
R
RC
RC
RC
0
0
0
The register contains the status of MS/SD controller during data transfer on DAT line(s) when MS/SD controller is
configured as the host of SD/MMC Memory Card. The register also will be used as interrupt sources. The register will
be cleared when reading the register. Meanwhile, if interrupt is enabled and thus interrupt caused by the register is
generated, reading the register will deassert the interrupt.
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BLKDONE The register bit indicates the status of data block transfer.
0 Otherwise.
1 A data block was successfully transferred.
DATTO Timeout on DAT detected. A ‘1’ indicates that MS/SD controller detected a timeout condition while waiting
for data token on the DAT line.
0 Otherwise.
1 MS/SD controller detected a timeout condition while waiting for data token on the DAT line.
DATCRCERR CRC error on DAT detected. A ‘1’ indicates that MS/SD controller detected a CRC error after reading
a block of data from the DAT line or SD/MMC signaled a CRC error after writing a block of data to the DAT
line.
0 Otherwise.
1 MS/SD controller detected a CRC error after reading a block of data from the DAT line or SD/MMC
signaled a CRC error after writing a block of data to the DAT line.
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MSDC+0048h SD Memory Card Status Register
31
30
29
28
27
26
15
14
13
12
11
10
25
24
23
22
CSTA [31:16]
RC
0000000000000000
9
8
7
6
CSTA [15:0]
RC
0000000000000000
SDC_CSTA
21
20
19
18
5
4
3
2
17
16
1
0
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Bit
Name
Type
Reset
Bit
Name
Type
Reset
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After commands with R1 and R1b response this register contains the status of the SD/MMC card and it will be used as
response interrupt sources. In all register fields, logic high indicates error and logic low indicates no error. The register
will be cleared when reading the register. Meanwhile, if interrupt is enabled and thus interrupt caused by the register is
generated, reading the register will deassert the interrupt.
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CSTA31
OUT_OF_RANGE. The command’s argument was out of the allowed range for this card.
CSTA30
ADDRESS_ERROR. A misaligned address that did not match the block length was used in the
command.
CSTA29
BLOCK_LEN_ERROR. The transferred block length is not allowed for this card, or the number of
transferred bytes does not match the block length.
CSTA28
ERASE_SEQ_ERROR. An error in the sequence of erase commands occurred.
CSTA27
ERASE_PARAM. An invalid selection of write-blocks for erase occurred.
CSTA26
WP_VIOLATION. Attempt to program a write-protected block.
CSTA25
Reserved. Return zero.
CSTA24
LOCK_UNLOCK_FAILED. Set when a sequence or password error has been detected in lock/unlock
card command or if there was an attempt to access a locked card.
CSTA23
COM_CRC_ERROR. The CRC check of the previous command failed.
CSTA22
ILLEGAL_COMMAND. Command not legal for the card state.
CSTA21
CARD_ECC_FAILED. Card internal ECC was applied but failed to correct the data.
CSTA20
CC_ERROR. Internal card controller error.
CSTA19
ERROR. A general or an unknown error occurred during the operation.
CSTA18
UNDERRUN. The card could not sustain data transfer in stream read mode.
CSTA17
OVERRUN. The card could not sustain data programming in stream write mode.
CSTA16
CID/CSD_OVERWRITE. It can be either one of the following errors: 1. The CID register has been
already written and cannot be overwritten 2. The read only section of the CSD does not match the card. 3. An
attempt to reverse the copy (set as original) or permanent WP (unprotected) bits was made.
CSTA[15:4] Reserved. Return zero.
CSTA3 AKE_SEQ_ERROR. Error in the sequence of authentication process
CSTA[2:0] Reserved. Return zero.
SDC_IRQMASK
0
MSDC+004Ch SD Memory Card IRQ Mask Register 0
31
30
29
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Bit
Name
Type
Reset
Bit
Name
Type
Reset
15
14
13
28
27
26
12
11
10
25
24
23
22
IRQMASK [31:16]
R/W
0000000000000000
9
8
7
6
IRQMASK [15:0]
R/W
0000000000000000
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The register contains parts of SD Memory Card Interrupt Mask Register. See the register description of the register
SDC_IRQMASK1 for reference. The register will mask interrupt sources from the register SDC_CMDSTA and
SDC_DATSTA. IRQMASK[15:0] is for SDC_CMDSTA and IRQMASK[31:16] for SDC_DATSTA. A ‘1’ in some bit
of the register will mask the corresponding interrupt source with the same bit position. For example, if IRQMASK[0] is
‘1’ then interrupt source from the register field CMDRDY of the register SDC_ CMDSTA will be masked. A ‘0’ in
some bit will not cause interrupt mask on the corresponding interrupt source from the register SDC_CMDSTA and
SDC_DATSTA.
31
30
29
28
27
26
15
14
13
12
11
10
25
24
23
22
IRQMASK [63:48]
R/W
0000000000000000
9
8
7
6
IRQMASK [47:32]
R/W
0000000000000000
21
20
5
4
19
18
17
16
3
2
1
0
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Bit
Name
Type
Reset
Bit
Name
Type
Reset
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SDC_IRQMASK
1
MSDC+0050h SD Memory Card IRQ Mask Register 1
The register contains parts of SD Memory Card Interrupt Mask Register. The registers SDC_IRQMASK1 and
SDC_IRQMASK0 compose the SD Memory Card Interrupt Mask Register. The register will mask interrupt sources
from the register SDC_CSTA. A ‘1’ in some bit of the register will mask the corresponding interrupt source with the
same bit position. For example, if IRQMASK[63] is ‘1’ then interrupt source from the register field OUT_OF_RANGE
of the register SDC_ CSTA will be masked. A ‘0’ in some bit will not cause interrupt mask on the corresponding
interrupt source from the register SDC_ CSTA.
MSDC+0054h SDIO Configuration Register
31
30
15
14
Name
Type
Reset
29
28
27
26
25
24
23
22
21
20
19
13
12
11
10
9
8
7
6
5
4
3
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Bit
Name
Type
Reset
Bit
SDIO_CFG
18
17
16
2
1
0
DSBS INTSE INTE
EL
L
N
R/W R/W R/W
0
0
0
The register is used to configure functionality for SDIO.
MT
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INTEN Interrupt enable for SDIO.
0 Disable
1 Enable
INTSEL Interrupt Signal Selection
0 Use data line 1 as interrupt signal
1 Use data line 5 as interrupt signal
DSBSEL Data Block Start Bit Selection.
0 Use data line 0 as start bit of data block and other data lines are ignored.
1 Start bit of a data block is received only when data line 0-3 all become low.
MSDC+0058h SDIO Status Register
Bit
Name
Type
31
30
29
28
27
26
SDIO_STA
25
24
23
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Reset
Bit
Name
Type
Reset
15
6.4.3.3
14
13
12
11
10
9
8
7
6
5
4
3
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2
Memory Stick Controller Register Definitions
Bit
15
14
PMOD
PRED
Name
E
Type R/W R/W
Reset
0
0
13
12
11
10
9
8
7
6
5
4
1
0
IRQ
RO
0
MSC_CFG
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MSDC+0060h Memory Stick Controller Configuration Register
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3
2
1
0
BUSYCNT
SIEN
R/W
101
R/W
0
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The register is used for Memory Stick Controller Configuration when MS/SD controller is configured as the host of
Memory Stick.
SIEN
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Serial Interface Enable. It should be enabled as soon as possible before any command.
0 Serial interface for Memory Stick is disabled.
1 Serial interface for Memory Stick is enabled.
BUSYCNT RDY timeout setting in unit of serial clock cycle. The register field is set to the maximum BUSY timeout
time (set value x 4 +2) to wait until the RDY signal is output from the card. RDY timeout error detection is not
performed when BUSYCNT is set to 0. The initial value is 0x5. That is, BUSY signal exceeding 5x4+2=22
serial clock cycles causes a RDY timeout error.
000 Not detect RDY timeout
001 BUSY signal exceeding 1x4+2=6 serial clock cycles causes a RDY timeout error.
010 BUSY signal exceeding 2x4+2=10 serial clock cycles causes a RDY timeout error.
…
111 BUSY signal exceeding 7x4+2=30 serial clock cycles causes a RDY timeout error.
PRED Parallel Mode Rising Edge Data. The register field is only valid in parallel mode, that is, MSPRO mode. In
parallel mode, data must be driven and latched at the falling edge of serial clock on MS bus. In order to
mitigate hold time issue, the register can be set to ‘1’ such that write data is driven by MSDC at the rising edge
of serial clock on MS bus.
0 Write data is driven by MSDC at the falling edge of serial clock on MS bus.
1 Write data is driven by MSDC at the rising edge of serial clock on MS bus.
PMODE
Memory Stick PRO Mode.
0 Use Memory Stick serial mode.
1 Use Memory Stick parallel mode.
MSDC+0064h Memory Stick Controller Command Register
Bit
Name
Type
Reset
15
14
13
12
11
10
9
8
7
PID
R/W
0000
6
5
4
DATASIZE
R/W
0000000000
MSC_CMD
3
2
1
0
MT
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The register is used for issuing a transaction onto MS bus. Transaction on MS bus is started by writing to the register
MSC_CMD. The direction of data transfer, that is, read or write transaction, is extracted from the register field PID.
16-bit CRC will be transferred for a write transaction even if the register field DATASIZE is programmed as zero under
the condition where the register field NOCRC in the register MSDC_CFG is ‘0’. If the register field NOCRC in the
register MSDC_CFG is ‘1’ and the register field DATASIZE is programmed as zero, then writing to the register
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MSC_CMD will not induce transaction on MS bus. The same applies for when the register field RDY in the register
MSC_STA is ‘0’.
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DATASIZE Data size in unit of byte for the current transaction.
0000000000 Data size is 0 byte.
0000000001 Data size is one byte.
0000000010 Data size is two bytes.
…
0111111111 Data size is 511 bytes.
1000000000 Data size is 512 bytes.
PID
Protocol ID. It is used to derive Transfer Protocol Code (TPC). The TPC can be derived by cascading PID and
its reverse version. For example, if PID is 0x1, then TPC is 0x1e, that is, 0b0001 cascades 0b1110. In addition,
the direction of the bus transaction can be determined from the register bit 15, that is, PID[3].
Bit
Name
Type
Reset
15
14
13
APID
R/W
0111
12
11
10
9
8
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MSDC+0068h Memory Stick Controller Auto Command Register
7
6
5
ADATASIZE
R/W
0000000001
4
3
MSC_ACMD
2
1
0
ACEN
R/W
0
The register is used for issuing a transaction onto MS bus automatically after the MS command defined in MSC_CMD
completed on MS bus. Auto Command is a function used to automatically execute a command like GET_INT or
READ_REG for checking status after SET_CMD ends. If auto command is enabled, the command set in the register
will be executed once the INT signal on MS bus is detected. After auto command is issued onto MS bus, the register bit
ACEN will become disabled automatically. Note that if auto command is enabled then the register bit RDY in the
register MSC_STA caused by the command defined in MSC_CMD will be suppressed until auto command completes.
Note that the register field ADATASIZE cannot be set to zero, or the result will be unpredictable.
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ACEN Auto Command Enable.
0 Auto Command is disabled.
1 Auto Command is enabled.
ADATASIZE
Data size in unit of byte for Auto Command. Initial value is 0x01.
0000000000 Data size is 0 byte.
0000000001 Data size is one byte.
0000000010 Data size is two bytes.
…
0111111111 Data size is 511 bytes.
1000000000 Data size is 512 bytes.
APID Auto Command Protocol ID. It is used to derive Transfer Protocol Code (TPC). Initial value is
GSET_INT(0x7).
MSDC+006Ch Memory Stick Controller Status Register
Bit
15
14
13
CMDN
BREQ ERR
K
Type
R
R
R
Reset
0
0
0
MT
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Name
12
11
10
9
8
7
CED
R
0
6
MSC_STA
5
4
3
2
1
HSRD CRCE
TOER SIF
Y
R
RO
RO
RO
RO
0
0
0
0
0
RDY
RO
1
The register contains various status of Memory Stick Controller, that is, MS/SD controller is configured as Memory
Stick Controller. These statuses can be used as interrupt sources. Reading the register will NOT clear it. The register
will be cleared whenever a new command is written to the register MSC_CMD.
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RDY
The register bit indicates the status of transaction on MS bus. The register bit will be cleared when writing to
the command register MSC_CMD.
0 Otherwise.
1 A transaction on MS bus is ended.
The register bit indicates the status of serial interface. If an interrupt is active on MS bus, the register bit will
be active. Note the difference between the signal RDY and SIF. When parallel mode is enabled, the signal SIF
will be active whenever any of the signal CED, ERR, BREQ and CMDNK is active. In order to separate
interrupts caused by the signals RDY and SIF, the register bit SIF will not become active until the
register MSDC_INT is read once. That is, the sequence for detecting the register bit SIF by polling is as
follows:
1. Detect the register bit RDY of the register MSC_STA
2. Read the register MSDC_INT
3. Detect the register bit SIF of the register MSC_STA
BS0
BS1
BS2
BS3
BS0
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SIF
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command execution
!
"#
" $ "# %
command finished
& "# %
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0 Otherwise.
1 An interrupt is active on MS bus
TOER The register bit indicates if a BUSY signal timeout error takes place. When timeout error occurs, the signal BS
will become logic low ‘0’. The register bit will be cleared when writing to the command register MSC_CMD.
0 No timeout error.
1 A BUSY signal timeout error takes place. The register bit RDY will also be active.
CRCER The register bit indicates if a CRC error occurs while receiving read data. The register bit will be cleared when
writing to the command register MSC_CMD.
0 Otherwise.
1 A CRC error occurs while receiving read data. The register bit RDY will also be active.
HSRDY The register bit indicates the status of handshaking on MS bus. The register bit will be cleared when writing to
the command register MSC_CMD.
0 Otherwise.
1 A Memory Stick card responds to a TPC by RDY.
CED The register bit is only valid when parallel mode is enabled. In fact, it’s value is from DAT[0] when serial
interface interrupt takes place. See Format Specification version 2.0 of Memory Stick Standard (Memory Stick
PRO) for more details.
0 Command does not terminate.
1 Command terminates normally or abnormally.
ERR The register bit is only valid when parallel mode is enabled. In fact, it’s value is from DAT[1] when serial
interface interrupt takes place. See Format Specification version 2.0 of Memory Stick Standard (Memory Stick
PRO) for more details.
0 Otherwise.
1 Indicate memory access error during memory access command.
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BREQ The register bit is only valid when parallel mode is enabled. In fact, it’s value is from DAT[2] when serial
interface interrupt takes place. See Format Specification version 2.0 of Memory Stick Standard (Memory Stick
PRO) for more details.
0 Otherwise.
1 Indicate request for data.
CMDNK
The register bit is only valid when parallel mode is enabled. In fact, it’s value is from DAT[3] when serial
interface interrupt takes place. See Format Specification version 2.0 of Memory Stick Standard (Memory Stick
PRO) for more details.
0 Otherwise
1 Indicate non-recognized command.
Application Notes
6.4.4.1
Initialization Procedures After Power On
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6.4.4
Disable power down control for MSDC module
Remember to power on MSDC module before starting any operation to it.
6.4.4.2
Card Detection Procedures
The pseudo code is as follows:
MSDC_CFG.PRCFG0 = 2’b10
MSDC_PS = 2’b11
MSDC_CFG.VDDPD = 1
if(MSDC_PS.PINCHG) { // card is inserted
. . .
}
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The pseudo code segment perform the following tasks:
1.
First pull up CD/DAT3 (INS) pin.
2.
Enable card detection and input pin at the same time.
3.
Turn on power for memory card.
4.
Detect insertion of memory card.
6.4.4.3
Notes on Commands
For MS, check if MSC_STA.RDY is ‘1’ before issuing any command.
For SD/MMC, if the command desired to be issued involves data line, for example, commands with data transfer or
R1b response, check if SDC_STA.SDCBUSY is ‘0’ before issuing. If the command desired to be issued does not
involve data line, only check if SDC_STA.CMDBUSY is ‘0’ before issuing.
6.4.4.4
Notes on Data Transfer
For SD/MMC, if multiple-block-write command is issued then only issue STOP_TRANS command
inter-blocks instead of intra-blocks.
MT
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Once SW decides to issue STOP_TRANS commands, no more data transfer from or to the controller.
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6.4.4.5
Notes on Frequency Change
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Before changing the frequency of serial clock on MS/SD/MMC bus, it is necessary to disable serial interface of the
controller. That is, set the register bit SIEN of the register SDC_CFG to ‘0’ for SD/MMC controller, and set the register
bit SIEN of the register MSC_CFG to ‘0’ for Memory Stick controller. Serial interface of the controller needs to be
enabled again before starting any operation to the memory card.
6.4.4.6
Notes on Response Timeout
1.
Read command => response time out
2.
Issue STOP_TRANS command => Get Response
3.
Read register SDC_DATSTA to clear it
6.4.4.7
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If a read command doest not receive response, that is, it terminates with a timeout, then register SDC_DATSTA needs
to be cleared by reading it. The register bit “DATTO” should be active. However, it may take a while before the register
bit becomes active. The alternative is to send the STOP_TRANS command. However, this method will receive
response with illegal-command information. Also, remember to check if the register bit SDC_STA.CMDBUSY is
active before issuing the STOP_TRANS command. The procedure is as follows:
Source or Destination Address is not word-aligned
It is possible that the source address is not word-aligned when data move from memory to MSDC. Similarly,
destination address may be not word-aligned when data move from MSDC to memory. This can be solved by setting
DMA byte-to-word functionality.
DMAn_CON.SIZE=0
2.
DMAn_CON.BTW=1
3.
DMAn_CON.BURST=2 (or 4)
4.
DMAn_COUNT=byte number instead of word number
5.
fifo threshold setting must be 1 (or 2), depending on DMAn_CON.BURST
Note n=4 ~ 11
6.4.4.8
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1.
Miscellaneous notes
Siemens MMC card: When a write command is issued and followed by a STOP_TRANS command, Siemens
MMC card will de-assert busy status even though flash programming has not yet finished. Software must use
“Get Status” command to make sure that flash programming finishes.
6.5
6.5.1
Graphic Memory Controller
General Description
MT
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Graphic memory controller provides channels to allow graphic engines to access SYSRAM and External Memory.
Simple Request-Acknowledgement handshaking scheme is employed here to ease the complexity of memory access
control circuitry in each graphic engine.
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To maximize data bandwidth, five individual access ports are implemented, which can access different memory banks
simultaneously. Figure 14 shows the connection between GMC, AHB, and memories. One access port is connected
to the SYSRAM, and the other access port for external memory access is connected to data cache directly.
Figure 14 Graphic memory controller
6.5.2
Register Definitions
GMC + 0000h
GMC + 0004h
GMC + 0008h
GMC + 000Ch
GMC + 0010h
Register Function
Acronym
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Register Address
GMC Control Register
GMC_CON
GMC Match Address Register
GMC_MATCHADDR
GMC Mask Address Register
GMC_MASKADDR
GMC INRANGE Master Register
GMC_INRANGE_MAST
GMC Bandwidth Limiter Register
GMC_LIMITER
Table 44 GMC Registers
GMC+0000h
Bit
Name
Type
Reset
Bit
31
14
GMC_CON
29
28
27
26
25
24
23
22
21
20
19
13
12
11
10
9
8
7
6
5
4
3
MT
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15
TRAP
Name
CLR
Type
W
Reset
0
30
GMC Control Register
18
17
16
2
1
0
BURS TRAP TRAP
INV
EN
T
R/W R/W R/W
1
0
0
This register is used to control the functionality for GMC.
TRAP EN
To enable address-trapping function. When this function is turned on, GMC compares the address
between the address configured in GMC Match Address Register and the address issued to memory.
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When the address is matched, the engine number that issued the request is recorded. The record can be
read from GMC INRANGE Master Register
Table 6 shows the engine number of each engine.
Engine
Number
Engine
Number
Engine Name
10
CAM (high priority)
1
2
MP4/JPEG
11
TVE (high priority)
MP4/JPEG
12
MP4_MV (high priority)
3
MP4/JPEG
13
2D WRITE
4
MP4/JPEG
14
2D COMMAND QUEUE
5
RESIZER
15
2D READ
6
RESIZER
16
GIF
7
RESIZER
17
PNG
8
IMAGE DMA
18
IPP
9
IMAGE DMA
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MP4/JPEG
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0
Engine Name
Table 45 Engine number
GMC+0004h
Bit
Name
Type
Bit
Name
Type
31
30
15
14
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TRAP INV Enable trapping range inversion. If this register bit is set, the engine, which issues the address out of the
address range specified with GMC_MATCHADDR, and GMC_MASKADDR, is trapped. The register
bit in GMC_INRANGE_MAST is set accordingly.
BURST
Enable burst mode. If burst mode is enabled, arbiter does not change the grant until finishing the burst.
On the other hand, GMC treats every request as a SINGLE transfer.
TRAP CLR This register field is used to clear the record in GMC INRANGE Master Register. This register field is a
write only register field.
GMC_MATCHA
DDR
GMC Match Address Register
29
28
27
26
25
13
12
11
10
9
24
23
ADDR
R/W
8
7
ADDR
R/W
22
21
20
19
18
17
16
6
5
4
3
2
1
0
This register is used to specify the trapping address for the address-trapping function.
ADDR The trapping address.
GMC+0008h
31
30
15
14
29
28
27
26
25
13
12
11
10
9
MT
K
Bit
Name
Type
Bit
Name
Type
GMC_MASKAD
DR
GMC Mask Address Register
24
23
MASK
R/W
8
7
MASK
R/W
22
21
20
19
18
17
16
6
5
4
3
2
1
0
This register is used to specify the address mask the address-trapping function.
address bits that is set as “1” in the GMC Mask Address Register.
The address comparator ignores the
MASK address mask.
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GMC+000Ch
Bit
31
GMC_INRANGE
_MAST
GMC INRANGE Master Register
30
29
28
27
26
25
24
23
22
21
20
19
Name
15
ENG
Name
15
Type RO
14
ENG
14
RO
13
12
ENG ENG
13
12
RO
RO
11
10
9
ENG ENG ENG
11
10
9
RO
RO
RO
8
7
6
ENG ENG ENG
8
7
6
RO
RO
RO
5
4
3
ENG ENG ENG
5
4
3
RO
RO
RO
This register is used to show the trapped engine..
ENGn The trapped address is issued by corresponding engine.
Bit
Name
Type
Reset
Bit
Name
Type
Reset
GMC Bandwidth Limiter Register
31
30
29
28
27
26
25
24
15
14
13
12
11
10
9
8
GMC_LIMITER
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GMC+0010h
18
17
16
ENG ENG ENG
18
17
16
RO
RO
RO
2
1
0
ENG ENG ENG
2
1
0
RO
RO
RO
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23
22
21
20
19
18
17
16
7
6
5
4
LIMITER
R/W
0
3
2
1
0
6.6
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This register is used for slow-down function of GMC EMI interface.
LIMITER This register field is used to specify the period that GMC EMI interface can issue a bus request to AHB.
LIMITER represents an AHB request can only be issued in LIMITER X 4 clock cycles. The value of
LIMITER is from 0 to 1023.
2D acceleration
6.6.1
2D Engine
6.6.1.1
General Description
To enhance MMI display and gaming experiences, a 2D acceleration engine is implemented. It supports ARGB8888,
RGB888, ARGB4444, RGB565 and 8-bpp color modes. Main features are listed as follows:
Rectangle fill with color gradient.
Bitblt: multi-Bitblt without transform, 7 rotate, mirror (transparent) Bitblt
Alpha blending
Binary ROP
Line drawing: normal line, dotted line, anti-alias line
Font caching: normal font, italic font
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Circle drawing
Quadratic Bezier curve drawing
Triangle drawing
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MCU can program 2D engine registers via APB. However, MCU has to make sure that the 2D engine is not BUSY
before any write to 2D engine registers occurs. An interrupt scheme is also provided for more flexibility.
DST
memory
read/write
control
Command
parser
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Command
queue
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A command parser is implemented for further offloading of MCU. The command queue can be randomly assigned in
the system memory, with a maximum depth of 2047 commands. If the command queue is enabled, MCU has to check
if the command queue has free space before writing to the command queue. Command queue parser will consume
command queue entries upon 2D engine requests. Figure 15 shows the command queue and 2D engine block diagram.
Please refer to the graphic command queue functional specification for more details.
APB
2D
engine
slave
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Graphic
Memory
Interface
SRC
memory
read
control
Figure 15 The command queue and 2D engine block diagram.
6.6.1.2
6.6.1.2.1
Features Introduction
2D Coordinate
The coordinates in the 2D engine are represented as 12-bit signed integers. The negative part is clipped during
rendering. The maximum resolution can achieve 2047x2047 pixels. The programmed base address is mapped to the
origin of the picture, which is illustrated in Figure 16.
dst_base_addr
MT
K
(0,0)
x
y
Figure 16 The coordinate of the 2D engine.
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Color format
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Bitblt (Copy, ROP)
Source color format
Destination color format
8bpp
8bpp
RGB888
ARGB4444
ARGB8888
RGB565
RGB888
RGB565
RGB888
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The 2D engine support the color format of 8bpp, RGB565, RGB888, ARGB4444, and ARGB 8888. The color
formats of source and destination can be specified separately. Note that when using the 8bpp format, the source and
destination color formats have to be the same, since table-lookup of color palette is not provided in 2D engine.
Graphic modes of Bitblt, Bitblt with alpha blending, and Bitblt with binary ROP require color format setting for both
source and destination. For other graphic modes, only destination color format needs to be specified. The possible
settings are listed as Table 46Table 47.
ARGB4444
ARGB8888
ARGB4444
ARGB8888
Table 46 source and destination color format setting for Bitblt.
Bitblt with Alpha Blending
Destination color format
8bpp
8bpp
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Source color format
RGB565
RGB888
ARGB4444
ARGB8888
RGB565
RGB888
RGB565
RGB888
RGB565
RGB888
RGB565
RGB888
Table 47 source and destination color format setting for alpha blending.
When source image is used, the source key function could be enabled or disabled. When enabled, the source color
key is in the same format of source color. Be aware that the source key is still effective for alpha blending mode.
6.6.1.2.3
Clipping Window
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The setting for clipping window is effective for all the 2D graphics. A pair of minimum and maximum boundary is
applied on destination side. The portion outside the clipping window will not be drawn to the destination, but the
pixels on the boundary will be kept. The clipping operation is illustrated in Figure 17.
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g2d_clp_max
6.6.1.2.4
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Figure 17 The clipping operation of the 2D engine.
Bitblt operation
The Bitblt function copies the pixels from source picture to destination. To be more flexible, 4 copy directions and 7
kinds of rotations are provided when doing Bitblt operation. Figure 18 illustrates the Bitblt operation and required
settings.
src_base_addr
dst_base_addr
(src_x,src_y)
(dst_x,dst_y)
D
src_h
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S
src_w
src_x_pitch
dst_x_pitch
Figure 18 The clipping operation of the 2D engine.
MT
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Note that the size of source and destination blocks can be different. If the source block is larger than destination block,
the size of destination block is used instead of the source size. When source block size is smaller than destination
block size, the pattern of source block is repeated horizontally and vertically in the destination block, which is
illustrated as Figure 19 below.
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Source
Copy direction
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Figure 19 The Bitblt operation when destination size > source size.
6.6.1.2.4.1
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When the source block and destination blocks are on the same picture, they may be overlapped by each other. To
prevent error from occurring, 4 directions for Bitblt can be programmed. However, the copy direction shall not be
enabled when doing rotation, or it will produce unwanted results. The 4 kinds of copy direction are shown in Figure
20.
D
S
D
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S
D
S
S
D
Figure 20 The 4 directions of Bitblt operation.
6.6.1.2.4.2
Rotation
MT
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To facilitate Bitblt operation, 7 kinds of rotation can be set at the same time. The rotation operation is illustrated as
Figure 21. Here the rotation is done on the destination side, while the read sequence of pixels in source block is
fixed.
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S
(src_x,src_y)
3).horizontal flip
4).vertical flip
D
D
D
D
5).90 degree rotation
6).270 degree rotation
D
D
Figure 21 The rotations of Bitblt operation.
6.6.1.2.5
Bitblt with Alpha Blending
7).90 degree rotation
+ vertical flip
D
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2).180 degree rotation
8).270 degree rotation
+ vertical flip
D
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1).No rotation
(dst_x,dst_y)
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Similar to simple Bitblt operation, alpha blending function is provided as well. The pixels in source block are blended
onto destination block. Blending is performed according the formula listed below:
C = (alpha * Cs + (255 - alpha) * Cd)/255 ,
where Cs is the source color, Cd is the destination color, and alpha is an unsigned integer range from 0 to 255.
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The alpha value programmed into the 2D control registers is called constant alpha. When no alpha channel exists, the
constant alpha is used to calculate blended color. If the alpha channel exists ( in ARGB color mode), the per-pixel
alpha is used for blending operation instead of constant alpha.
In addition, the setting of copy directions and rotations are also effective for alpha blending mode.
color format of source block can be different from destination.
6.6.1.2.6
Also, the size and
Bitblt with Binary ROP
The ROP (Raster Operation) is another block-wise functional mode. Here the 2D engine provides a set of binary
ROPs. The ROP code has 16 different combinations, which is listed in the definition of 2D control registers --G2D_SMODE_CON. Please see sec.1.1.1.3 for detail descriptions.
Similar with other block-wise functions, the copy directions and rotations are also applicable in ROP mode.
and color format of source and destination do not need to be the same.
6.6.1.2.7
The size
Rectangle Fill with Color Gradient
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Rectangle fill mode provides the configurations for color gradient for both x-direction and y-direction. Each of the
color gradient of component A, R, G, B is represented by 9.16 signed fixed point number. In order to prevent color
crossing the boundary of 0 and 255, it is clipped to 0 and 255 when performing gradient fill. When the color gradient
is disabled, the rectangle is filled by one color. An example of gradient fill is shown in Figure 22.
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start_clr
x_gradient
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y_gradient
Figure 22 Rectangle gradient fill.
6.6.1.2.8
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Line Draw
6.6.1.2.9
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The line drawing function is implemented with the mid-point algorithm. Given the two endpoints of a line, the points
on the line are calculated recursively. The line anti-aliasing is also supported but it requires extra register
configurations. In addition, dotted line is also provided for use. Simultaneously turning on anti-aliasing and
dotted-line is not recommended since the line may result in a strange look.
Circle Draw
The circle drawing is quite similar with line drawing, using the mid-point algorithm as well. A center point and a
radius have to be programmed into 2D control registers. There are 4 enable bits for each quadrant of a circle, each
determines whether the arcs shall be rendered or not. The setting of circle drawing is illustrated in Figure 23.
3
0
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radius
2
(dst_x,dst_y)
1
Figure 23 Circle drawing.
6.6.1.2.10
Bezier curve
The quadratic Bezier curve is implemented, too. The quadratic Bezier curve is defined by three control points, as
illustrated in Figure 24. The Bezier curve drawing is implemented with subdivision method. The amount of
subdivisions is programmed by software. The curve gets more detailed with the increase of subdivision factor, but it
requires more memory and computing time. To be more precise, doing n times of subdivision needs a buffer of
MT
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2 ( n +1) * 4 bytes.
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p0
Figure 24 Bezier curve.
6.6.1.2.11
Triangle Flat Fill
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The 2D engine supports the function of triangle flat fill with the help of software. First, the software divides the triangle
into upper plane and lower plane and passes them to hardware individually. Given the starting vertex’s coordinate and
the slopes of left and right edges, the 2D hardware fills the horizontal segments between the two edges until the
horizontal end is reached. The slope of each edge is in 12.16 bit signed fix-point representation. The programming
of triangle drawing is illustrated in Figure 25.
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start point
left slope
left slope
right slope
Horizontal end
Horizontal end
right slope
start point
MT
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Figure 25 Triangle drawing.
6.6.1.2.12
Font Drawing
The 2D engine helps to render fonts stored in one-bit-per-pixel format. It expends the zero bits to background color
and expands one bits to foreground color. The background color can be set as transparent. The font drawing can be
programmed as tilt, when given each line’s tilt value.
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The start bit of font drawing can be non-byte aligned to save memory usage for font caching. In addition, the rotations
can be performed at the same time when drawing fonts.
6.6.1.3
Register Definitions
Table 48 The 2D engine register mapping. summarizes the 2D engine register mapping on APB and through command
queue. The base address of 2D engine is 80670000h.
Register Function
Acronym
G2D+0100h
100h
2D engine fire mode control register
FMODE_CON
102h
Reserved
104h
2D Engine sub-mode control lower register
SMODE_CON_L
106h
2D Engine sub-mode control higher register
SMODE_CON_H
108h
2D engine common control register
COM_CON
10Ah
Reserved
110h
2D engine status register
112h
Reserved
200h
Source base address lower hword register
SRC_BASE_L
202h
Source base address higher hword register
SRC_BASE_H
204h
Source pitch register
SRC_PITCH
206h
Reserved
208h
Source y coordinate register
SRC_Y
20Ah
Source x coordinate register
SRC_X
G2D+0108h
G2D+0110h
G2D+0200h
G2D+0204h
G2D+0208h
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G2D+0104h
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CMQ
APB Address mapped
Address
STA
20Ch
Source height register
SRC_H
20Eh
Source width register
SRC_W
210h
Source color key lower hword register
SRC_KEY_L
212h
Source color key lower hword register
SRC_KEY_H
300h
Destination base address lower hword register
DST_BASE_L
302h
Destination base address higher hword register
DST_BASE_H
304h
Destination Pitch Register
DST_PITCH
306h
Reserved
G2D+0308h
308h
Destination y coordinate register 0
30Ah
Destination x coordinate register 0
DST_X0
G2D+030Ch
30Ch
Destination y coordinate register 1
DST_Y1
30Eh
Destination x coordinate register 1
DST_X1
G2D+0310h
310h
Destination y coordinate register 2
DST_Y2
312h
Destination x coordinate register 2
DST_X2
G2D+0318h
318h
Destination height register
DST_H
31Ah
Destination width register
DST_W
400h
Foreground color lower hword register
FGCLR_L
402h
Foreground color lower hword register
FGCLR_H
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G2D+020Ch
G2D+0210h
G2D+0300h
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G2D+0304h
G2D+400h
G2D+404h
DST_Y0
404h
Background color lower hword register
BGCLR_L
406h
Background color lower hword register
BGCLR_H
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Clipping minimum y coordinate register
CLP_MIN_Y
40Ah
Clipping minimum x coordinate register
CLP_MIN_X
40Ch
Clipping maximum y coordinate register
CLP_MAX_Y
40Eh
Clipping maximum x coordinate register
CLP_MAX_X
G2D+410h
410h
Rectangle color gradient x lower hword register
REC_CLRGD_X_L
412h
Rectangle color gradient x higher hword register
REC_CLRGD_X_H
G2D+414h
414h
Rectangle color gradient y lower hword register
REC_CLRGD_Y_L
416h
Rectangle color gradient y higher hword register
REC_CLRGD_Y_H
G2D+40Ch
fo
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408h
G2D+408h
TILT_0300 ~
TILT_1F1C
G2D+0700h ~
700h ~ 71Fh
G2D+071Fh
Table 48 The 2D engine register mapping.
APB
Address
CMQ
Addres Rectangle fill
s
Bitblt
Operations
G2D+0200h 200h
SRC_BASE
G2D+0204h 204h
SRC_PITCH
G2D+0208h 208h
SRC_XY
G2D+020Ch 20Ch
SRC_SIZE
G2D+0210h 210h
SRC_KEY
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There are several function modes in 2D graphics engine. Some registers are shared between different them. Table 49
summarizes the settings under different function modes.
Line/Circle
drawing
Bezier curve
drawing
SLOPE_L
DST_BASE
DST_BASE
DST_BASE
DST_BASE
G2D+0304h 304h
DST_PITCH
DST_PITCH DST_PITCH DST_PITCH
G2D+030Ch 30Ch
G2D+0310h 310h
G2D+0318h 318h
G2D+0400h 400h
G2D+0404h 404h
G2D+0408h 408h
G2D+040Ch 40Ch
G2D+0410h 410h
G2D+0414h 414h
G2D+0418h 418h
G2D+041Ch 41Ch
G2D+0420h 420h
G2D+0424h 424h
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G2D+0300h 300h
G2D+0308h 308h
DST_XY
DST_XY
Triangle drawing Font caching
SRC_BASE
SRC_KEY
DST_BASE
DST_BASE
DST_PITCH
DST_PITCH
DST_XY0
DST_XY0
DST_XY_START DST_XY
DST_XY1/
RADIUS
DST_XY1
DST_Y_END
DST_XY2
DST_SIZE
DST_SIZE
START_CLR
FGCLR
DST_KEY
XY_SQRT
CLP_MIN
CLP_MIN
CLP_MIN
CLP_MAX
CLP_MAX
CLP_MAX
FGCLR
DST_SIZE
FGCLR
FGCLR
BGCLR
CLP_MIN
CLP_MIN
CLP_MIN
CLP_MAX
CLP_MAX
CLP_MAX
ALPGD_X
BUF_STA_ADD SLOPE_R
RED_GD_X
SUBDIV_TIME
GREEN_GD_X
BLUE_GD_X
ALPGD_Y
RED_GD_Y
GREEN_GD_Y
G2D+042Ch 42Ch
BLUE_GD_Y
G2D+0700h
700h ~
~
71Fh
G2D+071Fh
TILT_0300 ~
TILT_1F1C
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G2D+0428h 428h
TILT_0300 ~
TILT_1F1C
TILT_0300 ~
TILT_1F1C
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APB
Address
CMQ
Horizontal Line
Addres
Gradient
s
Horizontal
Line Copy
with Mask
SRC_BASE
G2D+0200h 200h
G2D+0204h 204h
G2D+0208h 208h
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SRC_SIZE
G2D+020Ch 20Ch
G2D+0210h 210h
DST_BASE
DST_BASE
G2D+0318h 318h
DST_SIZE
DST_SIZE
G2D+0400h 400h
START_CLR
G2D+0300h 300h
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G2D+0304h 304h
G2D+0308h 308h
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G2D+030Ch 30Ch
G2D+0310h 310h
G2D+0404h 404h
G2D+0408h 408h
G2D+040Ch 40Ch
G2D+0410h 410h
ALPGD_X
MASK_BASE
RED_GD_X
GREEN_GD_X
G2D+041Ch 41Ch
BLUE_GD_X
G2D+0420h 420h
G2D+0424h 424h
G2D+0428h 428h
G2D+042Ch 42Ch
G2D+0700h
700h ~
~
71Fh
G2D+071Fh
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G2D+0414h 414h
G2D+0418h 418h
Table 49 2D engine common registers
Below shows common control registers.
G2D+0100h
Bit
Name
Type
Reset
15
14
G2D_FMODE_C
ON
Graphic 2D Engine Fire Mode Control Register
13
12
11
10
9
SRC_CLR_MODE
R/W
000
8
7
6
5
DST_CLR_MODE
R/W
000
4
3
2
1
0
G2D_ENG_MODE
R/W
0000
MT
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Write this register will fire the 2D engine according to the CLR_MODE and ENG_MODE field.
SRC_CLR_MODE source color mode
000 8-bpp, LUT disabled
001 16-bpp, RGB 565 format
010 32-bpp, ARGB 8888 format
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G2D+0104h
Bit
Type
Reset
30
G2D_SMODE_C
ON
Graphic 2D Engine Sub-mode Control Register
29
FMSB
Name FITA FNBG _FIRS
T
Type R/W R/W R/W
Reset
0
0
0
Bit
15
14
13
Name
31
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011 24-bpp, RGB 888 format
101 16-bpp, ARGB 4444 format
others reserved
DST_CLR_MODE destination color mode
000 8-bpp, LUT disabled
001 16-bpp, RGB 565 format
010 32-bpp, ARGB 8888 format
011 24-bpp, RGB 888 format
101 16-bpp, ARGB 4444 format
others reserved
G2D_ENG_MODE 2D engine function mode
0000 Line draw.
0001 Circle draw.
0010 Bezier curve draw.
0011 Triangle fill.
1000 Rectangle fill.
1001 Bitblt.
1010 Bitblt with alpha blending.
1011 Bitblt with ROP.
1100 Font drawing.
1101 Horizontal line fill with color gradient. In this mode, the source key and the clipping functions are
disabled automatically.
1110
Horizontal line copy with mask. In this mode, the source key and the clipping functions are disabled
automatically.
others not allowed
28
12
27
11
26
10
25
9
LDOT
R/W
0
24
23
22
21
20
19
18
17
ALPHA
ROP_CODE
R/W
0000
R/W
0000
8
7
6
DST_
LAA_
CLRG
KEY_
EN
D_EN
EN
R/W R/W R/W
0
0
0
5
4
3
2
1
BDIR
BITA
BROT
R/W
11
R/W
0
R/W
111
16
0
Write this register to set the 2D engine configuration.
MT
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FITA font italic enabled.
FNBG font drawing with no background color
FMSB_FIRST font drawing from most significant bit
ALPHA Bit 7-4 of constant alpha value. ROP_CODE is Bit3-0 of constant alpha value.
ROP_CODE
Binary ROP code. Bits 2-0 are also used to specify the start bit position for Font drawing and enabled
arcs for circle drawing.
Bitblt ROP Code
Boolean Function
Start Bit Position for Font
Drawing
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0000
0 (Black)
Bit 0
None
0001
~(S + D)
Bit 1
I
0010
~S . D
Bit 2
0011
~S
Bit 3
0100
S . ~D
Bit 4
0101
~D
Bit 5
,
0110
S^D
Bit 6
,
0111
~(S . D)
Bit 7
1000
S.D
Bit 0
1001
~(S ^ D)
Bit 1
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1010
D
Bit 2
,
1011
~S + D
Bit 3
1100
S
1101
S + ~D
1110
S+D
1111
1 (White)
,
,
,
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,
,
,
,
Bit 4
Bit 5
,
,
Bit 6
,
,
,
Bit 7
,
,
S = Source, D = Destination.
= first quadrant, II = second quadrant, III = third quadrant, IV = fourth quadrant.
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LDOT line dotted
LAA_EN line anti-aliasing enabled
DST_KEY_EN Destination key enabled for Bitblt functions
CLRGR_EN
Color gradient enabled for rectangle fill
BDIR Bitblt direction:
00 from lower right corner
01 from lower left corner
10 from upper right corner
11 from upper left corner
This field only takes effect when the Bitblt rotation is set as none (111). When doing rotation the Bitblt
direction of source image is always from upper left corner.
BITA Bitblt italic enabled, using the tilt value defined in G2D_TILT_00 ~ G2D_TILT_1F registers. The tilt
function should not be enabled in Alpha Blending and ROP mode.
BROT Bitblt rotation:
000 mirror then rotate 90
001 rotate 90
010 rotate 270
011 mirror then rotate 270
100 rotate 180
101 mirror
110 mirror then rotate 180
111 none
G2D+0108h
Bit
31
30
G2D_COM_CO
N
Graphic 2D Engine Common Control Register
29
28
27
26
25
24
23
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21
20
19
18
17
16
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Name
Type
Reset
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
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1
0
SRCK
CLP_
EY_E RST
EN
N
R/W R/W R/W
0
0
0
Name
Type
Reset
fo
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Write this register to set the 2D engine configuration.
RST
2D engine reset, only the state machine is reset, the content of control registers will not be reset.
SRCKEY_EN Source key enabled.
CLP_EN Clipping enabled.
Bit
Name
Type
Reset
Bit
Name
Type
Reset
Graphic 2D Engine Interrupt Control Register
31
30
29
28
27
26
25
24
15
14
13
12
11
10
9
8
Write this register to set the 2D engine IRQ configuration.
22
21
20
19
18
17
16
7
6
5
4
3
2
1
0
EN
R/W
0
interrupt enable. The interrupt is negative edge sensitive.
G2D+0110h
Bit
Name
Type
Reset
Bit
Name
Type
Reset
23
31
30
15
14
Graphic 2D Engine Common Status Register
G2D_COM_STA
29
28
27
26
25
24
23
22
21
20
19
18
17
16
13
12
11
10
9
8
7
6
5
4
3
2
1
0
BUSY
RO
0
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EN
G2D_IRQ_CON
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G2D+010Ch
Read this register to get the 2D engine status. 2D engine may function abnormally if any 2D engine register is modified
when BUSY.
BUSY 2D engine is busy
G2D+0200h
31
30
15
14
29
28
27
26
13
12
11
10
MT
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Bit
Name
Type
Reset
Bit
Name
Type
Reset
G2D_SRC_BAS
E
Graphic 2D Source Base Address Register
25
24
23
22
SRC_BASE[31:16]
R/W
0
9
8
7
6
SRC_BASE[15:0]
R/W
0
21
20
19
18
17
16
5
4
3
2
1
0
SRC_BASE
The base address of source image. Also, this field is used for the slope of the left triangle edges
represented in 12.16 format.
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G2D+0204h
14
SRC_PITCH
12
11
10
9
8
7
6
5
SRC_PITCH
R/W
0
4
3
2
The width of source image in the unit of pixels.
G2D+0208h
Bit
Name
Type
Reset
Bit
Name
Type
Reset
13
Graphic 2D Engine Source X and Y Register
31
30
29
28
27
26
25
24
23
15
14
13
12
11
10
9
8
7
22
21
SRC_X
R/W
0
6
5
SRC_Y
R/W
0
1
0
G2D_SRC_XY
20
4
fo
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15
G2D_SRC_PITC
H
Graphic 2D Engine Source Pitch Register
19
18
17
16
3
2
1
0
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Bit
Name
Type
Reset
Revision 1.0
Ko
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MT6228 GSM/GPRS Baseband Processor Data Sheet
SRC_Y The starting y co-ordinate of source image. It must be positive although represented as 12-bit signed integer.
SRC_X The starting x co-ordinate of source image. It must be positive although represented as 12-bit signed integer.
G2D+020Ch
31
30
29
28
27
26
25
24
15
14
13
12
11
10
9
8
23
7
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Bit
Name
Type
Reset
Bit
Name
Type
Reset
Graphic 2D Engine Source Size Register
G2D_SRC_SIZE
22
21
SRC_W
R/W
0
6
5
SRC_H
R/W
0
20
19
18
17
16
4
3
2
1
0
SRC_H The source height for Bitblt, alpha blending and ROP. It must be positive although represented as 12-bit signed
integer.
SRC_W
The source width for Bitblt, alpha blending and ROP. It must be positive although represented as 12-bit
signed integer.
G2D+0210h
Bit
Name
Type
Reset
Bit
Name
Type
Reset
31
30
15
14
Graphic 2D Engine Source Color Key Register
29
28
27
26
13
12
11
10
25
24
23
22
SRC_KEY[31:16]
R/W
0
9
8
7
6
SRC_KEY[15:0]
R/W
0
G2D_SRC_KEY
21
20
19
18
17
16
5
4
3
2
1
0
SRC_KEY The source color key. The color will be transparent if color keying is enabled.
Bit
Name
Type
Reset
31
30
G2D_DST_BAS
E
Graphic 2D Destination Base Address Register
MT
K
G2D+0300h
29
28
27
26
25
24
23
22
DST_BASE[31:16]
R/W
0
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21
20
19
18
17
16
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Bit
Name
Type
Reset
15
14
13
12
11
10
9
8
7
6
DST_BASE[15:0]
R/W
0
5
4
3
Revision 1.0
2
DST_BASE The base address of destination image.
15
14
DST_PITCH
12
11
10
9
8
7
6
5
SRC_PITCH
R/W
0
4
The width of destination image in the unit of pixels.
G2D+0308h
Bit
Name
Type
Reset
Bit
Name
Type
Reset
13
3
Graphic 2D Engine Destination X and Y Register 0
31
30
29
28
27
26
25
24
15
14
13
12
11
10
9
8
23
7
22
21
DST_X0
R/W
0
6
5
DST_Y0
R/W
0
0
G2D_DST_PITC
H
Graphic 2D Engine Destination Pitch Register
2
1
0
G2D_DST_XY0
Re
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Bit
Name
Type
Reset
1
fo
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G2D+0304h
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MT6228 GSM/GPRS Baseband Processor Data Sheet
20
19
18
17
16
4
3
2
1
0
(DST_X0 , DST_Y0) is used as the starting co-ordinate in Bitblt, alpha blending, ROP, and font drawing mode. In line
mode or triangle fill mode, it is used as one end point. For Bezier curve drawing, it is one of the control points. While
in circle drawing mode, it is the center of the circle. Also this filed is used as the starting point of triangle draw.
Represented by 12-bit signed integer. Negative co-ordinate is allowed.
Represented by 12-bit signed integer. Negative co-ordinate is allowed.
G2D+030Ch
Bit
Name
Type
Reset
Bit
Name
Type
Reset
31
30
15
14
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DST_X0
DST_Y0
Graphic 2D Engine Destination X and Y Register 1
29
28
27
26
25
24
23
13
12
11
10
9
8
7
22
21
DST_X1
R/W
0
6
5
DST_Y1
R/W
0
G2D_DST_XY1
20
19
18
17
16
4
3
2
1
0
(DST_X1 , DST_Y1) is used as one end point in Line drawing and triangle fill mode. For Bezier curve drawing, it is
one of the control points. While in circle drawing mode, DST_X1 must be positive since it is the radius of the circle.
Also, Bit 15-0 is used as the vertical end of triangle draw.
DST_X1
DST_Y1
Represented by 12-bit signed integer. Negative co-ordinate is allowed.
Represented by 12-bit signed integer. Negative co-ordinate is allowed.
Graphic 2D Engine Destination X and Y Register 2
MT
K
G2D+0310h
Bit
Name
Type
Reset
Bit
Name
31
30
29
28
27
26
25
24
23
15
14
13
12
11
10
9
8
7
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22
21
DST_X2
R/W
0
6
5
DST_Y2
G2D_DST_XY2
20
19
18
17
16
4
3
2
1
0
MediaTek Inc. Confidential
Type
Reset
Revision 1.0
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MT6228 GSM/GPRS Baseband Processor Data Sheet
R/W
0
(DST_X2 , DST_Y2) is used as one end point in triangle fill mode. For Bezier curve drawing, it is one of the control
points.
DST_X2
DST_Y2
Represented by 12-bit signed integer. Negative co-ordinate is allowed.
Represented by 12-bit signed integer. Negative co-ordinate is allowed.
31
30
29
28
27
26
25
24
23
15
14
13
12
11
10
9
8
7
22
21
DST_W
R/W
0
6
5
DST_H
R/W
0
G2D_DST_SIZE
20
4
19
18
17
16
3
2
1
0
Re
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se
Bit
Name
Type
Reset
Bit
Name
Type
Reset
Graphic 2D Engine Destination Size Register
fo
r
G2D+0318h
SRC_H The source height for Bitblt, alpha blending and ROP. It must be positive although represented as 12-bit signed
integer.
SRC_W
The source width for Bitblt, alpha blending and ROP. It must be positive although represented as 12-bit
signed integer.
G2D+0400h
Graphic 2D Engine Foreground Color Register
31
30
29
28
27
26
25
15
14
13
12
11
10
9
24
23
22
FGCLR[31:16]
R/W
0
8
7
6
FGCLR[15:0]
R/W
0
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Bit
Name
Type
Reset
Bit
Name
Type
Reset
G2D_ FGCLR
21
20
19
18
17
16
5
4
3
2
1
0
FGCLR The foreground color used for line/circle drawing and font drawing. It is also the start color of rectangle fill.
The format of foreground color depends on the source color mode set in G2D_FMODE_CON register.
G2D+0404h
Bit
Name
Type
Reset
Bit
Name
Type
Reset
31
30
15
14
Graphic 2D Engine Background Color Register
29
28
27
26
25
13
12
11
10
9
24
23
22
BGCLR[31:16]
R/W
0
8
7
6
BGCLR[15:0]
R/W
0
G2D_BGCLR
21
20
19
18
17
16
5
4
3
2
1
0
BGCLR The background color of the source. The format of background color depends on the source color mode set in
G2D_FMODE_CON register. Bit 15-0 also used as the XY_SQRT for anti-aliased line drawing. The
XY_SQRT calculation is listed as bellow.
MT
K
XY _ SQRT = 2 * ( DST _ X 1 − DST _ X 0) 2 + ( DST _ Y 1 − DST _ Y 0) 2
G2D+0408h
Bit
Name
Type
31
30
Graphic 2D Engine Clipping Minimum Register
29
28
27
26
25
24
23
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22
21
20
CLIP_MIN_X
R/W
G2D_CLIP_MIN
19
18
17
16
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14
CLIP_MIN_X
CLIP_MIN_Y
12
11
10
9
8
7
0
6
5
4
CLIP_MIN_Y
R/W
0
3
2
The minimum value of x co-ordinate in clipping window, signed 12-bit integer.
The minimum value of y co-ordinate in clipping window, signed 12-bit integer..
G2D+040ch
Bit
Name
Type
Reset
Bit
Name
Type
Reset
13
Graphic 2D Engine Clipping Maximum Register
31
30
29
28
27
26
25
24
23
15
14
13
12
11
10
9
8
7
22
21
20
CLIP_MAX_X
R/W
11111111111
6
5
4
CLIP_MAX_Y
R/W
11111111111
1
0
G2D_CLIP_MAX
19
18
17
16
3
2
1
0
fo
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15
Re
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Reset
Bit
Name
Type
Reset
Revision 1.0
Ko
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MT6228 GSM/GPRS Baseband Processor Data Sheet
CLIP_MAX_X The maximum value of x co-ordinate in clipping window, signed 12-bit integer...
CLIP_MAX_Y The maximum value of y co-ordinate in clipping window, signed 12-bit integer..
G2D+0410h
Graphic 2D X Alpha Gradient Register
31
30
29
28
27
26
25
24
23
15
14
13
12
11
10
9
8
7
6
ALPHA_GR_X[15:0]
R/W
0
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Bit
Name
Type
Reset
Bit
Name
Type
Reset
22
G2D_ALPGR_X
21
20
19
18
ALPHA_GR_X[24:16]
R/W
0
5
4
3
2
17
16
1
0
The color gradient of alpha in x direction for rectangle gradient fill. Bit 31-0 is also used as the start address of the
buffer used for Bezier curve draw. Also, this field is used for the slope of the right triangle edges represented in signed
12.16 format.
ALPHA_GR_X The color gradient of alpha channel, represented in signed 9.16 format.
G2D+0414h
Bit
Name
Type
Reset
Bit
Name
Type
Reset
31
30
15
14
Graphic 2D X Red Gradient Register
29
28
27
26
25
13
12
11
10
9
24
23
G2D_REDGR_X
22
8
7
6
RED_GR_X[15:0]
R/W
0
The color gradient of red in x direction for rectangle gradient fill.
Bezier curve drawing.
21
20
19
RED_GR_X[24:16]
R/W
0
5
4
3
18
17
16
2
1
0
Bit 3-0 also used as the times of subdivision for
MT
K
RED_GR_XThe color gradient of red component, represented in signed 9.16 format.
G2D+0418h
Bit
Name
31
30
Graphic 2D X Green Gradient Register
29
28
27
26
25
24
23
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22
G2D_
GREENGR_X
21
20
19
18
GREEN_GR_X[24:16]
17
16
MediaTek Inc. Confidential
Type
Reset
Bit
Name
Type
Reset
15
14
13
12
11
10
9
8
7
6
GREEN_GR_X[15:0]
R/W
0
5
R/W
0
4
3
Revision 1.0
2
GREEN_GR_X The color gradient of blue component, represented in signed 9.16 format.
30
29
28
27
26
25
15
14
13
12
11
10
9
23
22
8
7
6
BLUE_GR_X[15:0]
R/W
0
0
G2D_BLUEGR_X
21
20
19
BLUE_GR_X[24:16]
R/W
0
5
4
3
18
17
16
2
1
0
The color gradient of blue component, represented in signed 9.16 format.
BLUE_GR_X
G2D+0420h
Bit
Name
Type
Reset
Bit
Name
Type
Reset
24
1
fo
r
31
Graphic 2D Y Alpha Gradient Register
31
30
29
28
27
26
25
24
23
15
14
13
12
11
10
9
8
7
6
ALPHA_GR_Y[15:0]
R/W
0
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Bit
Name
Type
Reset
Bit
Name
Type
Reset
Graphic 2D X Blue Gradient Register
Re
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G2D+041Ch
Ko
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MT6228 GSM/GPRS Baseband Processor Data Sheet
22
G2D_ALPGR_Y
21
20
19
18
ALPHA_GR_Y[24:16]
R/W
0
5
4
3
2
17
16
1
0
The color gradient of alpha in x direction for rectangle gradient fill.
ALPHA_GR_Y The color gradient of alpha channel, represented in signed 9.16 format.
G2D+0424h
Bit
Name
Type
Reset
Bit
Name
Type
Reset
31
30
15
14
Graphic 2D Y Red Gradient Register
29
28
27
26
25
13
12
11
10
9
24
23
G2D_REDGR_Y
22
8
7
6
RED_GR_Y[15:0]
R/W
0
21
20
19
RED_GR_Y[24:16]
R/W
0
5
4
3
18
17
16
2
1
0
The color gradient of red in x direction for rectangle gradient fill.
RED_GR_YThe color gradient of red component, represented in signed 9.16 format.
G2D+0428h
31
30
29
28
27
26
25
15
14
13
12
11
10
9
8
7
6
GREEN_GR_Y15:0]
MT
K
Bit
Name
Type
Reset
Bit
Name
Graphic 2D Y Green Gradient Register
24
23
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22
G2D_
GREENGR_Y
21
20
19
18
GREEN_GR_Y24:16]
R/W
0
5
4
3
2
17
16
1
0
MediaTek Inc. Confidential
Type
Reset
Revision 1.0
R/W
0
GREEN_GR_Y The color gradient of blue component, represented in signed 9.16 format.
Graphic 2D Y Blue Gradient Register
31
30
29
28
27
26
25
15
14
13
12
11
10
9
BLUE_GR_Y
24
23
22
8
7
6
BLUE_GR_Y[15:0]
R/W
0
G2D_BLUEGR_Y
21
20
19
BLUE_GR_Y[24:16]
R/W
0
5
4
3
18
2
17
16
1
0
The color gradient of blue component, represented in signed 9.16 format.
6.6.2
Command Queue
6.6.2.1
General Description
Re
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se
Bit
Name
Type
Reset
Bit
Name
Type
Reset
fo
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G2D+042Ch
Ko
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MT6228 GSM/GPRS Baseband Processor Data Sheet
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To enhance MMI display and gaming experiences, a command queue parser is implemented for further offloading of
MCU. The command queue with a flexible depth setting is allocated in system memory. If the command queue is
enabled, software program has to check if the command queue has free space before writing to the command queue
data register. Command queue parser consumes the command queue entries upon 2D engine requests. Figure 15
shows the command queue and 2D engine block diagram.
Command
queue
DST
memory
read/write
control
Command
parser
APB
slave
Graphic
Memory
Interface
2D
engine
SRC
memory
read
control
Figure 26 The command queue and 2D engine block diagram.
Register Definitions
MT
K
6.6.2.2
MCU APB bus registers are listed as follows. The base address of the command queue controller is 80660000h.
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GCMQ+0000h Graphic Command Queue Control Register
Revision 1.0
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MT6228 GSM/GPRS Baseband Processor Data Sheet
GCMQ_CON
Bit
Name
Type
Reset
Bit
Name
Type
Reset
31
30
29
28
27
26
25
24
23
22
21
20
19
18
15
14
13
12
11
10
9
8
7
6
5
4
3
2
EN
WEN
Command queue enable. When EN is LOW, the command queue controller is reset.
Command queue in write mode. When WEN is LOW, the command queue consumes the commands in the
queue if command queue is not empty.
30
29
28
27
26
25
24
14
13
12
11
10
9
8
GCMQ_STA
22
21
20
19
18
17
16
7
6
5
4
3
2
1
0
FREE
RO
100000000
FREE Number of free command queue entries.
WR_RDY Ready to receive command, command-write is not allowed when this status bit is 0.
check this bit before writing command to gcmq.
31
30
15
14
ADDR [11:0]
DATA [15:0]
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GCMQ+0008h Graphic Command Queue Data Register
29
28
27
26
25
24
23
13
12
11
10
9
8
7
DATA
WO
Software has to
GCMQ_DAT
22
21
ADDR
WO
6
5
20
19
18
17
16
4
3
2
1
0
Write address for mapped 2D engine registers.
Write data for mapped 2D engine registers.
GCMQ_BASE_
ADD
GCMQ+000Ch Graphic Command Queue Base Address Register
Bit
Name
Type
Bit
Name
Type
1
0
WEN EN
R/W R/W
0
0
23
Re
lea
se
31
15
WR_R
Name
DY
Type RO
Reset
0
Bit
Name
Type
Bit
Name
Type
16
fo
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GCMQ+0004h Graphic Command Queue Status Register
Bit
Name
Type
Reset
Bit
17
31
30
15
14
29
28
27
26
13
12
11
10
25
24
23
22
BASE_ADD[31:16]
R/W
9
8
7
6
BASE_ADD[15:0]
R/W
21
20
19
18
17
16
5
4
3
2
1
0
MT
K
BASE_ADD
Starting address of the command queue in memory.
Note : This field can only be modified while the command queue is not enabled; otherwise the behavior of
the command queue is unpredictable.
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GCMQ_LENGT
H
GCMQ+0010h Graphic Command Queue Buffer Length Register
Bit
Name
Type
Bit
Name
Type
31
30
29
28
27
26
25
24
23
22
15
14
13
12
11
10
9
8
7
6
21
Revision 1.0
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MT6228 GSM/GPRS Baseband Processor Data Sheet
20
19
18
5
4
LENGTH
R/W
3
2
17
16
1
0
fo
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LENGTH[9:0] Length of the command queue. Occupied space of the command queue in the memory is LENGTH
*4Bytes.
Note : This field can only be modified while the command queue is not enabled; otherwise the behavior of
the command queue is unpredictable.
GCMQ_DMA_A
DDR
Bit
Name
Type
Bit
Name
Type
31
30
29
28
27
26
15
14
13
12
11
10
Re
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se
GCMQ+0014h Graphic Command Queue Current Register
25
24
23
22
GCMQ_DMA_ADDR
RO
9
8
7
6
GCMQ_DMA_ADDR
RO
21
20
19
18
17
16
5
4
3
2
1
0
GCMQ_DMA_ADDR Current read or write DMA address of GCMQ.
6.7
6.7.1
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6.6.2.3
Capture Resize
General Description
MT
K
This block provides the image resizing function for image and video capturing scenarios. It receives image data from
the ISP module, performs the image resizing function and outputs to the IMG_DMA module. Figure 27 shows the
block diagram. The capture resize is composed of horizontal and vertical resizing blocks. It can scale up or down
the input image by any ratio. However, the maximum sizes of input and output images are limited to 2048x2048.
Figure 27 Block diagram of the capture resize
The horizontal resizing function is a combination of 2’s power average and bi-linear interpolation. The vertical
resizing function is a bi-linear interpolation. The input and output format are both YUV444. But the internal
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working memory format is YUV422 to mitigate memory and bandwidth requirements.
employed in the capture resize for the vertical buffer read/write.
6.7.2
Revision 1.0
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MT6228 GSM/GPRS Baseband Processor Data Sheet
There is one GMC port
Register Definitions
REGISTER ADDRESS REGISTER NAME
SYNONYM
Capture Resize Configuration Register
CRZ_CFG
Capture Resize Control Register
CRZ_CON
CRZ + 0008h
Capture Resize Status Register
CRZ_STA
CRZ + 000Ch
Capture Resize Interrupt Register
CRZ + 0010h
Capture Resize Source Image Size Register 1
fo
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CRZ+ 0000h
CRZ + 0004h
CRZ_INT
CRZ_SRCSZ1
Capture Resize Target Image Size Register 1
Capture Resize Horizontal Ratio Register 1
CRZ_TARSZ1
CRZ_HRATIO1
CRZ + 001Ch
Capture Resize Vertical Ratio Register 1
CRZ_VRATIO1
CRZ + 0020h
Capture Resize Horizontal Residual Register 1
CRZ_HRES1
CRZ + 0024h
Capture Resize Vertical Residual Register 1
CRZ_VRES1
CRZ + 0040h
Capture Resize Fine Resizing Configuration Register
CRZ_FRCFG
CRZ + 005Ch
Capture Resize Pixel-Based Resizing Working Memory Base
Address
CRZ_PRWMBASE
CRZ + 00B0h
Capture Resize Information Register 0
CRZ_INFO0
CRZ + 00B4h
Capture Resize Information Register 1
CRZ_INFO1
CRZ + 00B8h
Capture Resize Information Register 2
CRZ_INFO2
CRZ + 00BCh
Capture Resize Information Register 3
CRZ_INFO3
CRZ + 00C0h
Capture Resize Information Register 4
CRZ_INFO4
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CRZ + 0014h
CRZ + 0018h
CRZ_INFO5
CRZ + 00C4h
6.7.2.1
Capture Resize Configuration Register
CRZ+0000h
Bit
Name
Type
Reset
Bit
Name
Type
Reset
Capture Resize Information Register 5
31
30
15
14
Capture Resize Configuration Register
CRZ_CFG
29
28
27
26
25
24
23
22
21
20
19
18
17
16
13
12
11
10
9
8
7
LBSE
L
R/W
0
6
5
4
3
2
1
0
PSEL PCON
R/W
0
R/W
0
PELSRC1
R/W
0000
The register is for global configuration of Capture Resize.
MT
K
PELSRC1 The register field specifies which pixel-based image source is serviced.
0 Camera Interface
1 MPEG4 Encoder DMA
2 MPEG4 Decoder DMA
3 IBW4 DMA
4 IPP
Others Reserved
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6.7.2.2
Capture Resize Control Register
CRZ+0004h
Bit
Capture Resize Control Register
31
30
29
28
27
26
25
24
15
14
13
12
11
10
9
8
Name
Type
Reset
Bit
Re
lea
se
fo
r
PCON The register bit specifies if pixel-based resizing continues whenever an image finishes processing. Once
continuous run for pixel-based resizing is enabled and pixel-based resizing is running, the only way to stop is
to reset Capture Resize. If to stop immediately is desired, reset Capture Resize directly. If the last image is
desired, set the register bit to ‘0’ first. Then wait until image resizer is not busy again. Finally reset image
resizer.
0 Single run
1 Continuous run
PSEL The register field determines if block-based image sources is serviced.
0 Block-based image source is serviced.
1 Block-based image source is NOT serviced completely. Clock for block-based processes is stopped and
block-based image input is blocked completely.
LBSEL Line buffer selection.
0 Shared memory.
1 Dedicated memory.
Name
22
21
20
19
7
6
5
4
3
Co
nf
id
en
tia
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Type
Reset
23
CRZ_CON
18
PELV
RRST
R/W
0
2
PELV
RENA
R/W
0
17
PELH
RRST
R/W
0
1
PELH
RENA
R/W
0
16
The register is for global control of Capture Resize. Note that software reset does NOT reset all register settings.
Remember to trigger Capture Resize first before triggering image sources to Capture Resize.
PELHRENA
Writing ‘1’ to the register bit causes pixel-based fine horizontal resizing proceed to work. However,
if horizontal resizing is not necessary, do not write ‘1’ to the register bit.
Writing ‘1’ to the register bit causes pixel-based fine vertical resizing proceed to work. However, if
vertical resizing is not necessary, do not write ‘1’ to the register bit.
Writing ‘1’ to the register causes pixel-based fine horizontal resizing to stop immediately and have
pixel-based fine horizontal resizing keep in reset state. In order to have pixel-based fine horizontal
resizing go to normal state, write ‘0’ to the register bit.
Writing ‘1’ to the register causes pixel-based fine vertical resizing to stop immediately and have
pixel-based fine vertical resizing keep in reset state. In order to have pixel-based fine vertical
resizing go to normal state, write ‘0’ to the register bit.
PELVRENA
PELHRRST
PELVRRST
6.7.2.3
Capture Resize Status Register
CRZ+0008h
CRZ_STA
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
MT
K
Bit
Name
Type
Reset
Bit
Capture Resize Status Register
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PELV PELH
RBUS RBUS
Y
Y
RO
RO
0
0
Name
Type
Reset
The register indicates global status of Capture Resize.
PELHRBUSY
PELVRBUSY
CRZ+000Ch
Bit
Name
Type
Reset
Bit
Capture Resize Interrupt Register
31
30
29
28
27
26
25
24
15
14
13
12
11
10
9
8
Name
Type
Reset
The register shows up the interrupt status of resizer.
23
fo
r
Capture Resize Interrupt Register
CRZ_INT
22
21
20
19
Re
lea
se
6.7.2.4
Pixel-based HR (Horizontal Resizing) Busy Status
Pixel-based VR (Vertical Resizing) Busy Status
7
6
5
4
3
18
17
2
1
PELV PELH
RINT RINT
RC
RC
0
0
16
0
6.7.2.5
Capture Resize Source Image Size Register 1
CRZ+0010h
Bit
Name
Type
Bit
Name
Type
31
Co
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PELHRINT Interrupt for PELHR (Pixel-based Horizontal Resizing). No matter the register bit
CRZ_FRCFG.HRINTEN is enabled or not, the register bit is active whenever PELHR completes. It
could be as software interrupt by polling the register bit. Clear it by reading the register.
PELVRINT Interrupt for PELVR (Pixel -based Vertical Resizing). No matter the register bit
CRZ_FRCFG.VRINTEN is enabled or not, the register bit is active whenever PELVR completes. It
could be as software interrupt by polling the register bit. Clear it by reading the register.
30
Capture Resize Source Image Size Register 1
29
28
27
26
25
24
CRZ_SRCSZ1
23
22
21
20
19
18
17
16
7
6
5
4
3
2
1
0
HS
R/W
15
14
13
12
11
10
9
8
WS
R/W
The register specifies the size of source image after coarse shrink process. The allowable maximum size is
2048x2048. Note that the width of source image must be a multiple of 8xHmax and the height of source image must be a
multiple of 8xVmax when Block Coarse Shrinking is involved.
The register field specifies the width of source image after coarse shrink process.
1 The width of source image after coarse shrink process is 1.
2 The width of source image is 2.
…
The register field specifies the height of source image after coarse shrink process.
1 The height of source image after coarse shrink process is 1.
2 The height of source image after coarse shrink process is 2.
…
MT
K
WS
HS
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6.7.2.6
Capture Resize Target Image Size Register 1
CRZ+0014h
31
30
Capture Resize Target Image Size Register 1
29
28
27
26
25
24
CRZ_TARSZ1
23
22
21
20
19
18
7
6
5
4
3
2
HT
R/W
15
14
13
12
11
10
9
8
WT
R/W
17
16
1
0
fo
r
Bit
Name
Type
Bit
Name
Type
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The register specifies the size of target image. The allowable maximum size is 2048x2048.
6.7.2.7
Capture Resize Horizontal Ratio Register 1
CRZ+0018h
Bit
Name
Type
Bit
Name
Type
Capture Resize Horizontal Ratio Register
31
30
29
28
27
26
25
15
14
13
12
11
10
9
The register specifies horizontal resizing ratio.
6.7.2.8
24
23
22
RATIO [31:16]
R/W
8
7
6
RATIO [15:0]
R/W
CRZ_HRATIO1
21
20
19
18
17
16
5
4
3
2
1
0
It is obtained by CRZ_SRCSZ.WS * 220 / CRZ_TARSZ.WT.
Capture Resize Vertical Ratio Register 1
CRZ+001Ch
Bit
Name
Type
Bit
Name
Type
Re
lea
se
HT
The register field specifies the width of target image.
1 The width of target image is 1.
2 The width of target image is 2.
…
The register field specifies the height of target image.
1 The height of target image is 1.
2 The height of target image is 2.
…
Co
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WT
31
30
15
14
Capture Resize Vertical Ratio Register 1
29
28
27
26
25
13
12
11
10
9
24
23
22
RATIO [31:16]
R/W
8
7
6
RATIO [15:0]
R/W
CRZ_VRATIO1
21
20
19
18
17
16
5
4
3
2
1
0
The register specifies vertical resizing ratio. It is obtained by CRZ_SRCSZ.HS * 220 / CRZ_TARSZ.HT.
6.7.2.9
Capture Resize Horizontal Residual Register 1
Capture Resize Horizontal Residual Register 1
MT
K
CRZ+0020h
Bit
Name
Type
Bit
Name
Type
31
30
29
28
27
26
25
15
14
13
12
11
10
9
24
23
8
7
RESIDUAL
R/W
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CRZ_HRES1
22
21
20
19
18
17
16
6
5
4
3
2
1
0
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The register specifies horizontal residual.
maximum value is 2046.
Capture Resize Vertical Residual Register 1
30
29
28
27
26
25
15
14
13
12
11
10
9
The register specifies vertical residual.
maximum value is 2046.
23
8
7
RESIDUAL
R/W
22
21
20
6
5
4
19
18
17
16
3
It is obtained by CRZ_SRCSZ.HS % CRZ_TARSZ.HT.
2
1
0
The allowable
Capture Resize Fine Resizing Configuration Register
CRZ+0040h
Bit
Name
Type
Bit
24
CRZ_VRES1
fo
r
31
6.7.2.11
The allowable
Capture Resize Vertical Residual Register 1
CRZ+0024h
Bit
Name
Type
Bit
Name
Type
It is obtained by CRZ_SRCSZ.WS % CRZ_TARSZ.WT.
Re
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6.7.2.10
Revision 1.0
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MT6228 GSM/GPRS Baseband Processor Data Sheet
Capture Resize Fine Resizing Configuration
Register
31
30
29
28
27
26
25
15
14
13
12
11
10
9
24
23
WMSZ
R/W
8
7
PCSF1
Type
Reset
R/W
00
Co
nf
id
en
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l
Name
22
6
21
20
5
4
VRINT HRIN
EN TEN
R/W R/W
0
0
CRZ_FRCFG
19
18
17
16
3
2
1
0
The register specifies various setting of control for fine resizing, including of horizontal and vertical resizing.
that all parameters must be set before horizontal and vertical resizing proceeds.
VRSS
R/W
0
Note
MT
K
VRSS The register bit specifies whether subsampling for vertical resizing is enabled. For throughput issue, vertical
resizing may be simplified by subsampling lines vertically. The register bit is only valid in pixel-based
mode.
0 Subsampling for vertical resizing is disabled.
1 Subsampling for vertical resizing is enabled.
HRINTEN HR (Horizontal Resizing) Interrupt Enable. When interrupt for HR is enabled, an interrupt is generated
whenever HR finishes.
0 Interrupt for HR is disabled.
1 Interrupt for HR is enabled.
VRINTEN VR (Vertical Resizing) Interrupt Enable. When interrupt for VR is enabled, an interrupt is generated
whenever VR finishes.
0 Interrupt for VR is disabled.
1 Interrupt for VR is enabled.
PCSF1 Coarse Shrinking Factor 1 for pixel-based resizing. Only horizontal coarse shrinking is supported for
pixel-based resizing.
00 No coarse shrinking.
01 Image width becomes 1/2 of original size after coarse shrink pass.
10 Image width becomes 1/4 of original size after coarse shrink pass.
11 Image width becomes 1/8 of original size after coarse shrink pass.
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WMSZ It stands for Working Memory SiZe. The register specifies how many lines after horizontal resizing can be
filled into working memory. Its minimum value is 4.
Capture Resize Pixel-Based Resizing Working Memory Base Address
Register
Capture Resize Pixel-Based Resizing
Working Memory Base Address Register
CRZ+005Ch
Bit
Name
Type
Bit
Name
Type
31
30
29
28
27
26
15
14
13
12
11
10
25
24
23
22
PRWMBASE [31:16]
R/W
9
8
7
6
PRWMBASE [15:0]
R/W
CRZ_PRWMBASE
21
20
5
4
6.7.2.13
17
16
3
2
1
0
It must be byte-aligned.
Capture Resize Information Register 0
CRZ+00B0h
Bit
Name
Type
Bit
Name
Type
18
Re
lea
se
The register specifies the base address of working memory in pixel-based resizing mode.
When CRZ_CFG.LB_SEL is set, this address should be set as 0x40020000.
19
fo
r
6.7.2.12
Capture Resize Information Register 0
31
30
29
28
27
26
25
15
14
13
12
11
10
9
24
23
INFO[31:16]
RO
8
7
INFO[15:0]
RO
CRZ_INFO0
22
21
20
19
18
17
16
6
5
4
3
2
1
0
INFO[31:16]
INFO[15:00]
6.7.2.14
BLKCS y
BLKCS x
Capture Resize Information Register 1
CRZ+00B4
Bit
Name
Type
Bit
Name
Type
Co
nf
id
en
tia
l
The register shows progress of BLKCS. But they are not real processed width/height. Sampling factors must be
taken into consideration. For example, if (VY, VU, VV)=(2,4,4) then real processed width/height are two times of the
register.
Capture Resize Information Register 1
31
30
15
14
29
28
27
26
25
13
12
11
10
9
24
23
INFO[31:16]
RO
8
7
INFO[15:0]
RO
CRZ_INFO1
22
21
20
19
18
17
16
6
5
4
3
2
1
0
The register shows progress of BLK2PEL.
BLK2PEL y
BLK2PEL x
MT
K
INFO[31:16]
INFO[15:00]
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Capture Resize Information Register 2
CRZ+00B8
Bit
Name
Type
Bit
Name
Type
Capture Resize Information Register 2
31
30
29
28
27
26
25
15
14
13
12
11
10
9
24
23
INFO[31:16]
RO
8
7
INFO[15:0]
RO
CRZ_INFO2
22
21
20
19
18
6
5
4
3
2
The register shows progress of pixels received from BLKCS in fine resizing stage.
INFO[31:16]
INFO[15:00]
Indicates the account of vertical lines received from BLKCS in fine resizing stage.
Indicates the account of horizontal pixels received from BLKCS in fine resizing stage.
becomes zero when resizing completes.
16
1
0
Note that it
Capture Resize Information Register 3
CRZ+00BC
Bit
Name
Type
Bit
Name
Type
Re
lea
se
6.7.2.16
17
fo
r
6.7.2.15
Revision 1.0
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MT6228 GSM/GPRS Baseband Processor Data Sheet
Capture Resize Information Register 3
31
30
29
28
27
26
25
15
14
13
12
11
10
9
24
23
INFO[31:16]
RO
8
7
INFO[15:0]
RO
CRZ_INFO3
22
21
20
19
18
17
16
6
5
4
3
2
1
0
The register shows progress of horizontal resizing in fine resizing stage.
INFO[31:16]
INFO[15:00]
Capture Resize Information Register 4
CRZ+00C0
Bit
Name
Type
Bit
Name
Type
Co
nf
id
en
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l
6.7.2.17
Indicates the account of horizontal resizing in fine resizing stage in horizontal direction.
Indicates the account of horizontal resizing in fine resizing stage in vertical direction.
Capture Resize Information Register 4
31
30
15
14
29
28
27
26
25
13
12
11
10
9
24
23
INFO[31:16]
RO
8
7
INFO[15:0]
RO
CRZ_INFO4
22
21
20
19
18
17
16
6
5
4
3
2
1
0
The register shows progress of vertical resizing in fine resizing stage.
INFO[31:16]
INFO[15:00]
6.7.2.18
Indicates the account of vertical resizing in fine resizing stage in horizontal direction.
Indicates the account of vertical resizing in fine resizing stage in vertical direction.
Capture Resize Information Register 5
Capture Resize Information Register 5
MT
K
CRZ+00C5
Bit
Name
Type
Bit
Name
Type
31
30
29
28
27
26
25
15
14
13
12
11
10
9
24
23
INFO[31:16]
RO
8
7
INFO[15:0]
RO
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21
20
19
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16
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The register shows progress of YUV-to-RGB
INFO[31:16]
INFO[15:00]
6.7.3
Indicates YUV-to-RGB in horizontal direction.
Indicates YUV-to-RGB in vertical direction.
Application Notes
Revision 1.0
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MT6228 GSM/GPRS Baseband Processor Data Sheet
Configuration procedure for pixel-based image sources
fo
r
Working memory. Maximum value is 16 and minimum 4. Remember that each pixel occupies 2 bytes.
Thus minimum requirement for working memory in pixel-based resizing is (pixel number in a line) x2x4
bytes.
Re
lea
se
CRZ_CFG.PSEL=1;
CRZ_CFG.PELSRC = 0;
CRZ_SRCSZ = source image size;
CRZ_TARSZ = target image size;
CRZ_HRATIO = horizontal ratio;
CRZ_VRATIO = vertical ratio;
CRZ_HRES = horizontal residual;
CRZ_VRES = vertical residual;
CRZ_FRCFG = working memory size, interrupt enable;
CRZ_PRWMBASE = working memory base;
CRZ_CON = 0x6;
// Then wait interrupt or polling CRZ_INT.PELHRINT or CRZ_INT.PELVRINT
Drop Resize
6.8.1
Co
nf
id
en
tia
l
6.8
General Description
This block provides a simple resizing function by performing pixel and line dropping. It receives image data from the
Video Encode DMA for videophone local display or the IBW3 DMA for thumbnail image dump, performs the image
resizing function and outputs to the image process engine module. It can scale down the input image by any ratio.
However, the maximum sizes of input and output images are limited to 2048x2048.
6.8.2
Register Definitions
6.8.2.1
Register Map
Table 50 shows the register map.
REGISTER ADDRESS REGISTER NAME
DRZ+ 0000h
Drop Resize Start Register
SYNONYM
DRZ_STR
Drop Resize Control Register
DRZ_CON
Drop Resize Status Register
DRZ_STA
DRZ + 000Ch
Drop Resize Interrupt Acknowledge Register
DRZ_ACKINT
DRZ + 0010h
Drop Resize Source Image Size Register
DRZ_SRC_SIZE
DRZ + 0014h
Drop Resize Target Image Size Register
DRZ_TAR_SIZE
DRZ + 0020h
Drop Resize Horizontal Ratio Register
DRZ_RAT_H
DRZ + 0024h
Drop Resize Vertical Ratio Register
DRZ_RAT_V
MT
K
DRZ+ 0004h
DRZ + 0008h
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Table 50 Register map.
6.8.2.2
Register Description
Followings are detail descriptions of each register.
DRZ_STR
30
29
28
27
26
25
24
23
22
21
20
R/W
0
14
R/W
0
13
R/W
0
12
R/W
0
11
R/W
0
10
R/W
0
9
R/W
0
8
R/W
0
7
R/W
0
6
R/W
0
5
R/W
0
4
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
19
18
17
16
R/W
0
3
R/W
0
2
R/W
0
1
R/W
0
R/W
0
R/W
0
R/W
0
0
STR
R/W
0
Re
lea
se
Bit
31
Name
Type R/W
Reset
0
Bit
15
Name
Type R/W
Reset
0
Drop Resize Start Register
fo
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DRZ+0000h
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MT6228 GSM/GPRS Baseband Processor Data Sheet
This register controls the activity of Drop Resize. Note that before setting STR to “1”, all the configurations shall be
done by giving proper values.
Start the Drop resize engine. Write 1 to this bit will start the FSM of Drop resize. Write 0 to this bit will reset
the FSM of Drop resize.
DRZ+0004h
31
30
Drop Resize Configuration Register
29
MT
K
Bit
Name
Type
Reset
Bit
Co
nf
id
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l
STR
15
14
13
DRZ_CON
28
27
26
25
24
23
22
21
20
12
11
10
9
8
7
6
5
4
Name
Type
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19
3
AUTO
PSEL
RSTR
R/W R/W
18
17
16
2
1
0
IT
R/W
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Reset
0
0
Revision 1.0
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MT6228 GSM/GPRS Baseband Processor Data Sheet
0
The register specifies the configuration of Drop resize.
IT
fo
r
Interrupt Enabling
0 Disable
1 Enable
AUTO RSTR Automatic restart. Drop Resize automatically restarts itself while current frame is finished.
0 Disable
1 Enable
PSEL Pixel engine selection
0 Video encode DMA
1 IBW3 DMA.
Bit
Name
Type
Reset
Bit
Name
Type
Reset
Drop Resize Status Register
31
30
29
28
27
26
25
24
15
14
13
12
11
10
9
8
DRZ_STA
Re
lea
se
DRZ+0008h
23
22
21
20
19
18
17
7
6
5
4
3
2
1
16
RUN
RO
0
0
IT
RO
0
This register helps software program being well aware of the global status of Drop Resize.
RUN
Interrupt status for Drop Resize
0 No interrupt is generated.
1 An interrupt is pending and waiting for service.
Drop Resize status
0 Drop Resize is stopped or has completed the transfer already.
1 Drop Resize is currently running.
DRZ+000Ch
Bit
Name
Type
Bit
Name
Type
31
30
15
14
Co
nf
id
en
tia
l
IT
Drop Resize Interrupt Acknowledge Register
DRZ_ACKINT
29
28
27
26
25
24
23
22
21
20
19
18
17
16
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ACK
WO
This register is used to acknowledge the current interrupt request associated with the completion event of Drop Resize
by software program. Note that this is a write-only register, and any read to it will return a value of “0”.
ACK
Interrupt acknowledge for the Drop Resize
0 No effect
1 Interrupt request is acknowledged and should be relinquished.
DRZ+0010h
31
30
29
MT
K
Bit
Name
Type
Reset
Bit
Name
Drop Resize Source Image Size Register
15
14
13
28
27
26
25
24
DRZ_SRC_SIZE
23
22
21
20
19
18
17
16
7
6
5
4
3
2
1
0
V
R/W
0
12
11
10
9
8
H
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Reset
Revision 1.0
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MT6228 GSM/GPRS Baseband Processor Data Sheet
R/W
0
The register specifies the size of source image. The maximum allowable size is 2048x2048.
the height of source image-1
the width of source image-1
Bit
Name
Type
Reset
Bit
Name
Type
Reset
31
30
Drop Resize Target Image Size Register
29
28
27
26
25
24
DRZ_TAR_SIZE
23
22
21
20
7
6
5
4
V
R/W
0
15
14
13
12
11
10
9
8
H
R/W
0
19
18
17
fo
r
DRZ+0014h
3
Re
lea
se
V
H
2
1
16
0
The register specifies the size of target image. The maximum allowable size is 2048x2048.
the height of target image-1
the width of target image-1
DRZ+0020h
Bit
Name
Type
Reset
Bit
Name
Type
Reset
Drop Resize Horizontal Ratio Register
31
30
29
28
27
26
25
15
14
13
12
11
10
9
24
23
I [31:16]
R/W
0
8
7
Q [15:0]
R/W
0
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H
DRZ_RAT_H
22
21
20
19
18
17
16
6
5
4
3
2
1
0
The register specifies horizontal resizing ratio. It is obtained by (the width of source image/the width of target image) =
I + Q/P = I + Q/the width of target image.
I [31:0] the integer part
Q [31:0]
the denominator
DRZ+0024h
Bit
Name
Type
Reset
Bit
Name
Type
Reset
31
30
15
14
Drop Resize Vertical Ratio Register
29
28
27
26
25
13
12
11
10
9
24
23
I [31:16]
R/W
0
8
7
Q [15:0]
R/W
0
DRZ_RAT_V
22
21
20
19
18
17
16
6
5
4
3
2
1
0
The register specifies horizontal resizing ratio. It is obtained by (the height of source image/the height of target image)
= I + Q/P = I + Q/the height of target image.
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I [31:0] the integer part
Q [31:0]
the denominator
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Post Resize
6.9.1
General Description
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Figure 27 shows the block diagram of post resize. It receives image data from a block-based source such as JPEG
decoder or from a scan line based source, and then performs image resizing. The capability of resizing in the block is
divided into two portions, coarse pass and fine pass. The first pass is coarse resizing pass and it is able to shrink image
by a factor of 1, 1/4, 1/16, or 1/64. The second pass is the fine resizing pass, which is composed of horizontal and
vertical resizing, and it is able to shrink or enlarge image in fractional ratio. The maximum allowable image size for the
fine resizing pass is 2048x2048. Thus the maximum allowable image size for coarse resizing pass is 16384x16384.
% &"""
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% &"""
Figure 28 Block diagram of the post resize
The strip buffer of coarse resizing pass accumulates de-compressed 8x8 YUV blocks separately. These YUV data are
packed into pixels and sent to the fine resizing pass. There is one GMC port employed in the coarse resize for the strip
buffer read/write.
The fine resizing pass is composed of horizontal and vertical resizing blocks. It can scale up or down the input image
by any ratio. However, the maximum sizes of input and output images are limited to 2048x2048. The horizontal
resizing function is a combination of 2’s power average and bi-linear interpolation. The vertical resizing function is a
bi-linear interpolation. The input and output format are both YUV444. But the internal working memory format is
YUV422 to mitigate memory and bandwidth requirements. There is one GMC port employed in the fine resize for the
vertical buffer read/write.
6.9.2
Working Memories
There are two working memories in post resize. One is the strip buffer, and the other is the vertical buffer.
6.9.2.1
Strip Buffer
MT
K
Let’s denote sampling factor for Y-component as (HY, VY), U-component as (HU, VU) and V-component as (HV, VV) in
a JPEG file. The minimum requirement of memory size for the strip buffer is (the image width of after the coarse
resizing pass) * (VY * 8 + VU * 8 + VV * 8) bytes. It is (2048) * (4 * 8 + 4 * 8 + 2 * 8) = 160K bytes for extreme cases.
To enhance the throughput of JPEG decode process, software may use double buffer scheme. Then it becomes 320K
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bytes. Please note that the strip buffer is composed of the Y buffer, U buffer, and V buffer. Software can allocate
separate memory for them.
6.9.2.2
Vertical Buffer
The minimum requirement of memory for the vertical buffer is (the target image width) * (the line number of
vertical buffer) * 2 bytes. It is (2048) * (2) * 2 = 4K bytes for extreme cases. To enhance throughputs of overall data
paths, software may use double buffer scheme. Then it becomes 8K bytes.
Source Image
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6.9.3
For the coarse resizing pass, the width of the source image must be multiples of 8 * (maximum horizontal sampling
factor). Similarly, the height of the source image must be multiples of 8 * (maximum vertical sampling factor). The
maximum size of target image is 2048x2048.
6.9.4
Re
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For the fine resizing pass, the maximum size of source image and target image are both 2048x2048.
Flow Control
For the coarse resizing pass, the coarse resizing will send pixel data to the fine resizing when they are ready with hand
shake signal. If strip buffer is full, the coarse resizing will halt image data input until the strip buffer is available.
For the fine resizing pass, the fine resizing will send pixel data to the image post processing when they are ready with
hand shake signal. If vertical buffer is full, the fine resizing will halt image data input until the vertical is available.
6.9.5
Throughput
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For block-based image sources, the process time for one pixel is about 3 cycles. Therefore if 15 frames per second are
desired and Post Resize is running at 52 MHz then the maximum pixel number per frame is about 1.15M. That is about
1075x1075.
For pixel-based image sources, the process time for one pixel is about 2.25 cycles. Therefore if 15 frames per second
are desired and Post Resize is running at 52 MHz then the maximum pixel number per frame is about 1.5M. That is
about 1241x1241.
Since memory bandwidth requirements are different for scale up and down, it may be able to enhance throughput by
adjusting the register setting of PRZ_CFG.BWA0/BWB0. When scaling up, memory bandwidth requirement for read is
higher than memory bandwidth requirements for write. However, when scaling down, memory bandwidth requirement
for write is higher than memory bandwidth requirements for read. Therefore when horizontally scaling up, throughput
can be enhance by setting PRZ_CFG.B0 with higher value than PRZ_CFG.A0. Similarly when horizontally scaling
down, throughput can be enhance by setting PRZ_CFG.A0 with higher value than PRZ_CFG.B0. Therefore when
vertically scale up throughput can be enhance by setting PRZ_CFG.B1 with higher value than PRZ_CFG.A1. Similarly
when vertically scale down throughput can be enhance by setting PRZ_CFG.A1 with higher value than PRZ_CFG.B1.
6.9.6
Register Definitions
REGISTER ADDRESS REGISTER NAME
MT
K
PRZ+ 0000h
PRZ + 0004h
SYNONYM
Post Resize Configuration Register
PRZ_CFG
Post Resize Control Register
PRZ_CON
PRZ + 0008h
Post Resize Status Register
PRZ_STA
PRZ + 000Ch
Post Resize Interrupt Register
PRZ_INT
PRZ + 0010h
Post Resize Source Image Size Register 1
PRZ_SRCSZ1
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Post Resize Target Image Size Register 1
PRZ_TARSZ1
Post Resize Horizontal Ratio Register 1
PRZ_HRATIO1
PRZ + 001Ch
Post Resize Vertical Ratio Register 1
PRZ_VRATIO1
PRZ + 0020h
Post Resize Horizontal Residual Register 1
PRZ_HRES1
PRZ + 0024h
Post Resize Vertical Residual Register 1
PRZ_VRES1
PRZ + 0030h
Post Resize Block Coarse Shrinking Configuration Register
PRZ_BLKCSCFG
PRZ + 0034h
Post Resize Y-Component Line Buffer Memory Base Address
PRZ_YLMBASE
PRZ + 0038h
Post Resize U-Component Line Buffer Memory Base Address
PRZ_ULMBASE
PRZ + 003Ch
Post Resize V-Component Line Buffer Memory Base Address
PRZ + 0040h
Post Resize Fine Resizing Configuration Register
PRZ + 0050h
Post Resize Y Line Buffer Size Register
PRZ + 005Ch
Post Resize Pixel-Based Resizing Working Memory Base Address
PRZ_PRWMBASE
PRZ + 00B0h
Post Resize Information Register 0
PRZ_INFO0
Post Resize Information Register 1
Post Resize Information Register 2
PRZ + 00BCh
Post Resize Information Register 3
PRZ + 00C0h
Post Resize Information Register 4
PRZ + 00C4h
Post Resize Information Register 5
Name
Type
Reset
PRZ_INFO1
PRZ_INFO3
PRZ_INFO4
PRZ_INFO5
Post Resize Configuration Register
PRZ+0000h
Bit
Name
Type
Reset
Bit
PRZ_FRCFG
PRZ_YLBSIZE
PRZ_INFO2
31
30
15
14
Post Resize Configuration Register
29
28
27
26
25
24
23
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6.9.6.1
PRZ_VLMBASE
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PRZ + 00B4h
PRZ + 00B8h
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PRZ + 0014h
PRZ + 0018h
13
12
11
10
9
8
7
LBSE
L
R/W
0
22
21
BWB0
R/W
0000
6
5
20
19
4
3
PSEL PCON
R/W
0
R/W
0
PRZ_CFG
18
17
BWA0
R/W
0000
2
1
16
0
PELSRC1
R/W
0000
The register is for global configuration of Post Resize.
MT
K
PELSRC1 The register field specifies which pixel-based image source is serviced.
1 MPEG4 Encoder DMA
2 MPEG4 Decoder DMA
3 IBW4 DMA
5 IPP
6 JPEG Decoder
Others Reserved
PCON The register bit specifies if pixel-based resizing continues whenever an image finishes processing. Once
continuous run for pixel-based resizing is enabled and pixel-based resizing is running, the only way to stop is
to reset Post Resize. If immediate stop is desired, reset Post Resize directly. If the last image is desired, set the
register bit to ‘0’ first. Then wait till Post Resize is not busy again. Finally reset Post Resize.
0 Single run
1 Continuous run
PSEL The register field determines if block-based image sources is serviced.
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1
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6.9.6.2
Post Resize Control Register
PRZ+0004h
Bit
31
30
15
14
Name
Type
Reset
Bit
Name
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Block-based image source will be serviced.
Block-based image source will NOT be serviced completely. Clock for block-based processes will be
stopped and block-based image input will be blocked completely.
LBSEL line buffer selection. When CRZ_CFG.LB_SEL is set, this bit should not be set.
0 Shared memory.
1 Dedicated memory.
BWA0 Bandwidth selection for port A of memory interface 0. In block-based mode, this is the memory interface
between BLKCS and BLKHR. In pixel-based mode, that’s is memory interface between PELHR and PELVR.
Each memory interface has one write port (port A) and one read port (port B). The arbitration between port A
and port B of memory interface 0 is based on the setting of the register fields BWA0 and BWB0. The
arbitration scheme is fair between port A and port B. However, if the register field BWA0 is set larger value
than the register field BWB0 then port A can get more bandwidth than port B.
0 If memory access of port A and port B take place simultaneously, then grant will be given to port B
whenever port A gets grant once.
1 If memory access of port A and port B take place simultaneously, then grant will be given to port B
whenever port A gets grant twice.
2 If memory access of port A and port B take place simultaneously, then grant will be given to port B
whenever port A gets grant three times.
…
BWB0 Bandwidth selection for port b of memory interface 0. In block-based mode, this is the memory interface
between BLKCS and BLKHR. In pixel-based mode, that’s is memory interface between PELHR and PELVR.
Each memory interface has one write port (port A) and one read port (port B). The arbitration between port A
and port B of memory interface 0 is based on the setting of the register fields BWA0 and BWB0. The
arbitration scheme is fair between port A and port B. However, if the register field BWB0 is set larger value
than the register field BWA0 then port B can get more bandwidth than port A.
0 If memory access of port A and port B take place simultaneously, then grant will be given to port A
whenever port B gets grant once.
1 If memory access of port A and port B take place simultaneously, then grant will be given to port A
whenever port B gets grant twice.
2 If memory access of port A and port B take place simultaneously, then grant will be given to port A
whenever port B gets grant three times.
…
Post Resize Control Register
PRZ_CON
29
28
27
26
25
24
23
22
21
20
19
13
12
11
10
9
8
7
6
5
4
3
MT
K
Type
Reset
18
PELV
RRST
R/W
0
2
PELV
RENA
R/W
0
17
PELH
RRST
R/W
0
1
PELH
RENA
R/W
0
16
BLKC
SRST
R/W
0
0
BLKC
SENA
R/W
0
The register is for global control of Post Resize. Note that block-based and pixel-based resizing cannot execute
parallel. Furthermore, software reset will NOT reset all register setting. Remember trigger Post Resize first
before trigger image sources to Post Resize.
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BLKCSENA
Writing ‘1’ to the register bit will cause Block Coarse Shrinking proceed to work. Block Coarse
Shrinking is designed to cooperate width JPEG decoder. It works on the fly. Bu it needs to be
restarted every time before working.
Writing ‘1’ to the register bit will cause pixel-based fine horizontal resizing proceed to work.
However, if horizontal resizing is not necessary, do not write ‘1’ to the register bit.
Writing ‘1’ to the register bit will cause pixel-based fine vertical resizing proceed to work. However,
if vertical resizing is not necessary, do not write ‘1’ to the register bit.
Writing ‘1’ to the register bit will force Block Coarse Shrinking to stop immediately and have Block
Coarse Shrinking keep in reset state. In order to have Block Coarse Shrinking go to normal state,
writing ‘0’ to the register bit.
Writing ‘1’ to the register will cause pixel-based fine horizontal resizing to stop immediately and have
pixel-based fine horizontal resizing keep in reset state. In order to have pixel-based fine horizontal
resizing go to normal state, writing ‘0’ to the register bit.
Writing ‘1’ to the register will pixel-based fine vertical resizing to stop immediately and have
pixel-based fine vertical resizing keep in reset state. In order to have pixel-based fine vertical resizing
go to normal state, writing ‘0’ to the register bit.
PELHRENA
PELVRENA
PELHRRST
PELVRRST
Post Resize Status Register
PRZ+0008h
Bit
Name
Type
Reset
Bit
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BLKCSRST
6.9.6.3
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Post Resize Status Register
31
30
29
28
27
26
25
24
15
14
13
12
11
10
9
8
23
22
21
20
19
7
6
5
4
BLKI
NTRA
BSY
RO
0
3
Type
Reset
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Name
PRZ_STA
18
17
16
2
1
0
PELV PELH BLKC
RBUS RBUS SBUS
Y
Y
Y
RO
RO
RO
0
0
0
The register indicates global status of Post Resize.
BLKCSBUSY Block-based CS (Coarse Shrinking) Busy Status
PELHRBUSY Pixel-based HR (Horizontal Resizing) Busy Status
PELVRBUSY Pixel-based VR (Vertical Resizing) Busy Status
BLKINTRABSY Block-based CS (Coarse Shrinking) Intra-Block Busy Status
6.9.6.4
Post Resize Interrupt Register
PRZ+000Ch
Bit
Name
Type
Reset
Bit
31
30
15
14
Post Resize Interrupt Register
PRZ_INT
29
28
27
26
25
24
23
22
21
20
19
13
12
11
10
9
8
7
6
5
4
3
MT
K
Name
Type
Reset
18
17
16
2
1
0
PELV PELH BLKC
RINT RINT SINT
RC
RC
RC
0
0
0
The register shows up the interrupt status of resizer.
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Post Resize Source Image Size Register 1
PRZ+0010h
Bit
Name
Type
Bit
Name
Type
31
30
Post Resize Source Image Size Register 1
29
28
27
26
25
24
PRZ_SRCSZ1
23
22
21
20
19
18
17
16
7
6
5
4
3
2
1
0
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6.9.6.5
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BLKCSINT Interrupt for BLKCS (Block-based Coarse Shrink). No matter if the register bit PRZ_BLKCSCFG.INTEN
is enabled or not, the register bit will be active whenever BLKCS completes. It could be used as software
interrupt by polling the register bit. Clear it by reading the register.
PELHRINT Interrupt for PELHR (Pixel-based Horizontal Resizing). No matter if the register bit
PRZ_FRCFG.HRINTEN is enabled or not, the register bit will be active whenever PELHR completes. It
could be used as software interrupt by polling the register bit. Clear it by reading the register.
PELVRINT Interrupt for PELVR (Pixel -based Vertical Resizing). No matter if the register bit
PRZ_FRCFG.VRINTEN is enabled or not, the register bit will be active whenever PELVR completes. It
could be used as software interrupt by polling the register bit. Clear it by reading the register.
HS
R/W
15
14
13
12
11
10
9
8
WS
R/W
The register specifies the size of source image after coarse shrink process. The maximum allowable size is 2048x2048.
Note that for the width of source image must be multiples of 8xHmax and the height of source image must be multiples
of 8xVmax when Block Coarse Shrinking is involved.
HS
The register field specifies the width of source image after coarse shrink process.
1 The width of source image after coarse shrink process is 1.
2 The width of source image is 2.
…
The register field specifies the height of source image after coarse shrink process.
1 The height of source image after coarse shrink process is 1.
2 The height of source image after coarse shrink process is 2.
…
6.9.6.6
Post Resize Target Image Size Register 1
PRZ+0014h
Bit
Name
Type
Bit
Name
Type
31
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WS
30
Post Resize Target Image Size Register 1
29
28
27
26
25
24
PRZ_TARSZ1
23
22
21
20
19
18
17
16
7
6
5
4
3
2
1
0
HT
R/W
15
14
13
12
11
10
9
8
WT
R/W
The register specifies the size of target image. The maximum allowable size is 2048x2048.
The register field specifies the width of target image.
1 The width of target image is 1.
2 The width of target image is 2.
…
The register field specifies the height of target image.
1 The height of target image is 1.
2 The height of target image is 2.
MT
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WT
HT
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…
Post Resize Horizontal Ratio Register 1
PRZ+0018h
Bit
Name
Type
Bit
Name
Type
Post Resize Horizontal Ratio Register
31
30
29
28
27
26
25
15
14
13
12
11
10
9
24
23
22
RATIO [31:16]
R/W
8
7
6
RATIO [15:0]
R/W
PRZ_HRATIO1
21
20
19
18
5
4
3
2
17
16
1
0
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6.9.6.7
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The register specifies horizontal resizing ratio. It is obtained by PRZ_SRCSZ.WS * 220 / PRZ_TARSZ.WT.
Post Resize Vertical Ratio Register 1
PRZ+001Ch
Bit
Name
Type
Bit
Name
Type
Re
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6.9.6.8
Post Resize Vertical Ratio Register 1
31
30
29
28
27
26
25
15
14
13
12
11
10
9
24
23
22
RATIO [31:16]
R/W
8
7
6
RATIO [15:0]
R/W
PRZ_VRATIO1
21
20
19
18
17
16
5
4
3
2
1
0
The register specifies vertical resizing ratio. It is obtained by PRZ_SRCSZ.HS * 220 / PRZ_TARSZ.HT.
Post Resize Horizontal Residual Register 1
PRZ+0020h
Bit
Name
Type
Bit
Name
Type
31
30
15
14
Post Resize Horizontal Residual Register 1
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6.9.6.9
29
28
27
26
25
13
12
11
10
9
24
23
8
7
RESIDUAL
R/W
PRZ_HRES1
22
21
20
19
18
17
16
6
5
4
3
2
1
0
The register specifies horizontal residual. It is obtained by PRZ_SRCSZ.WS % PRZ_TARSZ.WT. The maximum
allowable value is 2046.
6.9.6.10
Post Resize Vertical Residual Register 1
PRZ+0024h
Bit
Name
Type
Bit
Name
Type
31
30
15
14
Post Resize Vertical Residual Register 1
29
28
27
26
25
13
12
11
10
9
24
23
8
7
RESIDUAL
R/W
PRZ_VRES1
22
21
20
19
18
17
16
6
5
4
3
2
1
0
MT
K
The register specifies vertical residual. It is obtained by PRZ_SRCSZ.HS % PRZ_TARSZ.HT. The allowable
maximum value is 2046.
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6.9.6.11
Post Resize Block Coarse Shrinking Configuration Register
PRZ+0030h
Bit
Revision 1.0
31
Post Resize Block Coarse Shrinking
Configuration Register
30
29
14
13
28
27
12
11
26
25
10
9
24
23
8
7
PRZ_BLKCSCFG
22
21
6
5
20
19
18
4
3
2
15
VV
R/W
00
HV
R/W
00
VU
R/W
00
HU
R/W
00
VY
R/W
00
HY
R/W
00
17
16
INTE
N
R/W
0
1
0
CSF
R/W
00
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Type
Reset
Bit
Name
Type
Reset
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MT6228 GSM/GPRS Baseband Processor Data Sheet
HY
VY
HU
VU
MT
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HV
It stands for Coarse Shrink Factor. The value specifies the scale factor in coarse shrink pass.
00 Image size does not change after coarse shrink pass.
01 Image size becomes 1/4 of original size after coarse shrink pass.
10 Image size becomes 1/16 of original size after coarse shrink pass.
11 Image size becomes 1/64 of original size after coarse shrink pass.
Horizontal sampling factor for Y-component
00 Horizontal sampling factor for Y-component is 1.
01 Horizontal sampling factor for Y-component is 2.
10 Horizontal sampling factor for Y-component is 4.
11 No Y-component.
Vertical sampling factor for Y-component
00 Vertical sampling factor for Y-component is 1.
01 Vertical sampling factor for Y-component is 2.
10 Vertical sampling factor for Y-component is 4.
11 No Y-component.
Horizontal sampling factor for U-component
00 Horizontal sampling factor for U-component is 1.
01 Horizontal sampling factor for U-component is 2.
10 Horizontal sampling factor for U-component is 4.
11 No U-component.
Vertical sampling factor for U-component
00 Vertical sampling factor for U-component is 1.
01 Vertical sampling factor for U-component is 2.
10 Vertical sampling factor for U-component is 4.
11 No U-component.
Horizontal sampling factor for V-component
00 Horizontal sampling factor for V-component is 1.
01 Horizontal sampling factor for V-component is 2.
10 Horizontal sampling factor for V-component is 4.
11 No V-component.
Vertical sampling factor for V-component
00 Vertical sampling factor for V-component is 1.
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CSF
Re
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The register is for various configuration of Block Coarse Shrinking in Post Resize. Block Coarse Shrinking is dedicated
for JPEG decoder. Therefore all processes are based on blocks composed of 8x8 pixels. Note that all parameters must
be set before writing ‘1’ to the register bit PRZ_CON.BLKCSENA.
VV
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01 Vertical sampling factor for V-component is 2.
10 Vertical sampling factor for V-component is 4.
11 No V-component.
INTEN Interrupt Enable. When interrupt for BLKCS is enabled, interrupt will arise whenever BLKCS finishes.
0 Interrupt for BLKCS is disabled.
1 Interrupt for BLKCS is enabled.
PRZ+0034h
Bit
Name
Type
Bit
Name
Type
Post Resize Y-Component Line Buffer Memory
Base Address Register
31
30
29
28
27
26
15
14
13
12
11
10
25
24
23
22
YLMBASE [31:16]
R/W
9
8
7
6
YLMBASE [15:0]
R/W
21
20
5
4
fo
r
Post Resize Y-Component Line Buffer Memory Base Address Register
PRZ_YLMBASE
19
18
17
16
3
2
1
0
Re
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6.9.6.12
The register specifies the base address of line buffer for Y-component. It could be byte-aligned. It is only useful in
block-based mode.
Post Resize U-Component Line Buffer Memory Base Address Register
PRZ+0038h
Bit
Name
Type
Bit
Name
Type
31
30
15
14
Post Resize U-Component Line Buffer Memory
Base Address Register
29
28
27
26
25
24
23
22
ULMBASE [31:16]
R/W
9
8
7
6
ULMBASE [15:0]
R/W
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6.9.6.13
13
12
11
10
PRZ_ULMBASE
21
20
19
18
17
16
5
4
3
2
1
0
The register specifies the base address of line buffer for U-component. It could be byte -aligned. It is only useful in
block-based mode.
6.9.6.14
Post Resize V-Component Line Buffer Memory Base Address Register
PRZ+003Ch
Bit
Name
Type
Bit
Name
Type
31
30
15
14
Post Resize V-Component Line Buffer Memory
Base Address Register
29
28
27
26
13
12
11
10
25
24
23
22
VLMBASE [31:16]
R/W
9
8
7
6
VLMBASE [15:0]
R/W
PRZ_VLMBASE
21
20
19
18
17
16
5
4
3
2
1
0
MT
K
The register specifies the base address of line buffer for V-component. It could be byte -aligned. It is only useful in
block-based mode.
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Post Resize Fine Resizing Configuration Register
PRZ+0040h
Bit
Name
Type
Bit
Post Resize Fine Resizing Configuration Register
31
30
29
28
27
26
25
15
14
13
12
11
10
9
24
23
WMSZ
R/W
8
7
Name OSEL
PCSF2
PCSF1
Type R/W
Reset
0
R/W
00
R/W
00
22
6
21
20
5
4
VRINT HRIN
EN TEN
R/W R/W
0
0
PRZ_FRCFG
19
18
3
2
17
16
1
0
VRSS
fo
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6.9.6.15
Revision 1.0
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MT6228 GSM/GPRS Baseband Processor Data Sheet
R/W
0
The register specifies various setting of control for fine resizing, including of horizontal and vertical resizing. Note that
all parameters must be set before horizontal and vertical resizing proceeds.
6.9.6.16
Post Resize Y Line Buffer Size Register
PRZ+0050h
31
30
15
14
Post Resize Y Line Buffer Size Register
PRZ_YLBSIZE
29
28
27
26
25
24
23
22
21
20
19
18
17
16
13
12
11
10
9
8
7
YLBZE
R/W
6
5
4
3
2
1
0
MT
K
Bit
Name
Type
Bit
Name
Type
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VRSS The register bit specifies whether subsampling for vertical resizing is enabled. For throughput issue, vertical
resizing may be simplified by subsampling lines vertically. The register bit is only valid in pixel-based mode.
0 Subsampling for vertical resizing is disabled.
1 Subsampling for vertical resizing is enabled.
HRINTEN HR (Horizontal Resizing) Interrupt Enable. When interrupt for HR is enabled, interrupt will be issued
whenever HR finishes.
0 Interrupt for HR is disabled.
1 Interrupt for HR is enabled.
VRINTEN VR (Vertical Resizing) Interrupt Enable. When interrupt for VR is enabled, interrupt will be issued
whenever VR finishes.
0 Interrupt for VR is disabled.
1 Interrupt for VR is enabled.
PCSF1 Coarse Shrinking Factor 1 for pixel-based resizing. Only horizontal coarse shrinking is supported for
pixel-based resizing.
00 No coarse shrinking.
01 Image width becomes 1/2 of original size after coarse shrink pass.
10 Image width becomes 1/4 of original size after coarse shrink pass.
11 Image width becomes 1/8 of original size after coarse shrink pass.
OSEL The register bit is used to select output modules.
0 Image DMA.
1 IPP.
WMSZ It stands for Working Memory Size. The register specifies how many lines after horizontal resizing can be
filled into working memory. Its minimum value is 4.
The register specifies line buffer size for image data after coarse shrinking. It is only useful in block-based mode.
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Post Resize Pixel-Baed Resizing Working Memory Base Address Register
Post Resize Pixel-Based Resizing Working
Memory Base Address Register
PRZ+005Ch
Bit
Name
Type
Bit
Name
Type
Re
lea
se
6.9.6.17
fo
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YLBSZ It stands for Y-component Line Buffer Size. The register field specifies how many lines of Y-component can
be filled into line buffer. Line buffer size for U- and V-component can be determined according to the
sampling factor. For example, if (VY, VU, VV)=(4,4,2) and line buffer size for Y-component is 32, lines then
the line buffer size for U-component is also 32 lines and V-component 16 lines. If line buffer has capacity for
whole image after block coarse shrinking, then block coarse shrinking can be used for the application of
scaling down by a factor of 2, or 4, or 8. If dual line buffer is used, block coarse shrinking and horizontal
resizing can execute parallel. The maximum allowable value is 2048.
1 Line buffer size for Y-component is 1 lines.
2 Line buffer size for Y-component is 2 lines.
3 Line buffer size for Y-component is 3 lines.
…
31
30
29
28
27
26
15
14
13
12
11
10
25
24
23
22
PRWMBASE [31:16]
R/W
9
8
7
6
PRWMBASE [15:0]
R/W
PRZ_PRWMBASE
21
20
19
18
17
16
5
4
3
2
1
0
The register specifies the base address of working memory in pixel-based resizing mode. It must be byte-aligned.
When PRZ_CFG.LB_SEL is set, this address should be set as 0x40020000.
Post Resize Information Register 0
PRZ+00B0h
Bit
Name
Type
Bit
Name
Type
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6.9.6.18
Post Resize Information Register 0
31
30
15
14
29
28
27
26
25
13
12
11
10
9
24
23
INFO[31:16]
RO
8
7
INFO[15:0]
RO
PRZ_INFO0
22
21
20
19
18
17
16
6
5
4
3
2
1
0
The register shows progress of BLKCS. But they are not real processed width/height. Sampling factors must be taken
into consideration. For example, if (VY, VU, VV)=(2,4,4) then real processed width/height are two times that of the
register value.
INFO[31:16]
INFO[15:00]
6.9.6.19
BLKCS y
BLKCS x
Post Resize Information Register 1
PRZ+00B4
31
30
29
28
27
26
25
15
14
13
12
11
10
9
MT
K
Bit
Name
Type
Bit
Name
Type
Post Resize Information Register 1
24
23
INFO[31:16]
RO
8
7
INFO[15:0]
RO
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The register shows progress of BLK2PEL.
INFO[31:16]
INFO[15:00]
Post Resize Information Register 2
PRZ+00B8
Bit
Name
Type
Bit
Name
Type
Post Resize Information Register 2
31
30
29
28
27
26
25
15
14
13
12
11
10
9
24
23
INFO[31:16]
RO
8
7
INFO[15:0]
RO
PRZ_INFO2
22
21
20
6
5
4
19
18
17
16
3
2
1
0
fo
r
6.9.6.20
BLK2PEL y
BLK2PEL x
INFO[31:16]
INFO[15:00]
6.9.6.21
Indicate the account of vertical lines received from BLKCS in fine resizing stage.
Indicate the account of horizontal pixels received from BLKCS in fine resizing stage. Note that it will
become zero when resizing completes.
Post Resize Information Register 3
PRZ+00BC
Post Resize Information Register 3
31
30
29
28
27
26
25
15
14
13
12
11
10
9
24
23
INFO[31:16]
RO
8
7
INFO[15:0]
RO
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Bit
Name
Type
Bit
Name
Type
Re
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se
The register shows progress of pixels received from BLKCS in fine resizing stage.
PRZ_INFO3
22
21
20
19
18
17
16
6
5
4
3
2
1
0
The register shows progress of horizontal resizing in fine resizing stage.
INFO[31:16]
INFO[15:00]
6.9.6.22
Indicate the account of horizontal resizing in fine resizing stage in horizontal direction.
Indicate the account of horizontal resizing in fine resizing stage in vertical direction.
Post Resize Information Register 4
PRZ+00C0
Bit
Name
Type
Bit
Name
Type
Post Resize Information Register 4
31
30
15
14
29
28
27
26
25
13
12
11
10
9
24
23
INFO[31:16]
RO
8
7
INFO[15:0]
RO
PRZ_INFO4
22
21
20
19
18
17
16
6
5
4
3
2
1
0
The register shows progress of vertical resizing in fine resizing stage.
Indicate the account of vertical resizing in fine resizing stage in horizontal direction.
Indicate the account of vertical resizing in fine resizing stage in vertical direction.
MT
K
INFO[31:16]
INFO[15:00]
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Post Resize Information Register 5
PRZ+00C5
Bit
Name
Type
Bit
Name
Type
Post Resize Information Register 5
31
30
29
28
27
26
25
15
14
13
12
11
10
9
24
23
INFO[31:16]
RO
8
7
INFO[15:0]
RO
22
21
20
19
18
6
5
4
3
2
The register shows progress of YUV-to-RGB
6.9.7
Indicate YUV-to-RGB in horizontal direction.
Indicate YUV-to-RGB in vertical direction.
Application Notes
17
16
1
0
Re
lea
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INFO[31:16]
INFO[15:00]
PRZ_INFO5
fo
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6.9.6.23
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MT6228 GSM/GPRS Baseband Processor Data Sheet
Determine line buffer size by taking into consideration of CSF and sampling factor. For example, if CSF=3
and (Vy, Vu, Vv)=(4,x,x) then minimum of line buffer could be 4 instead of 32.
Working memory. Maximum value is 16 and minimum 4. Remember that each pixel occupies 2 bytes. Thus
minimum requirement for working memory in pixel-based resizing is (pixel number in a line) x2x4 bytes.
Configuration procedure for block-based image sources
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PRZ_CFG.PSEL=0;
PRZ_CFG.PELSRC = 5;
PRZ_BLKCSCFG = select CSF, sampling factor, interrupt enable;
PRZ_YLBBASE = memory base for Y-component;
PRZ_ULBBASE = memory base for U-component;
PRZ_VLBBASE = memory base for V-component;
PRZ_YLBSIZE = line buffer size for Y-component;
Other same as that for pixel-based image sources
PRZ_CON = 0x7;
// Then wait interrupt or polling PRZ_INT.BLKCSINT or PRZ_INT.BLKHRINT or
// PRZ_INT.BLKVRINT
Configuration procedure for pixel-based image sources
PRZ_CFG.PSEL=1;
PRZ_CFG.PELSRC = 1~4;
PRZ_SRCSZ = source image size;
PRZ_TARSZ = target image size;
PRZ_HRATIO = horizontal ratio;
PRZ_VRATIO = vertical ratio;
PRZ_HRES = horizontal residual;
PRZ_VRES = vertical residual;
PRZ_FRCFG = working memory size, interrupt enable;
PRZ_PRWMBASE = working memory base;
PRZ_CON = 0x6;
MT
K
// Then wait interrupt or polling PRZ_INT.PELHRINT or PRZ_INT.PELVRINT
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6.10
Revision 1.0
JPEG Decoder
6.10.1
Overview
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To boost JPEG image processing performance, a hardware block is preferred to aid software and deal with JPEG file as
much as possible. As a result, JPEG Decoder is designed to decode all baseline and progressive JPEG images with all
YUV sampling frequencies combinations. To gain the best speed performance, JPEG decoder handles all portions of
JPEG files except the 17-byte SOF marker. The software program only needs to program related control registers
based on the SOF marker and waits for an interrupt coming from hardware. Taking into consideration the limited size
of memories, hardware also supports multiple runs of JPEG progressive images and breakpoints insertion in huge JPEG
files. Multiple runs can greatly reduce memory usage by 1/N where N is the number of runs. Breakpoints insertion
allows software to load partial JPEG file from external flash to internal memory if the JPEG file is too large to sit
internally at one time.
Register Definitions
Re
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6.10.2
JPEG+0000h JPEG Decoder Control Register
Bit
31
Name
Type R/W
Bit
15
Name
Type R/W
30
29
28
27
26
R/W
14
R/W
13
R/W
12
R/W
11
R/W
10
R/W
R/W
R/W
R/W
R/W
25
24
23
22
FILE_ADDR[31:16]
R/W R/W R/W R/W
9
8
7
6
FILE_ADDR[15:0]
R/W R/W R/W R/W
The JPEG file starting address must be a multiple of 4.
21
20
19
18
17
16
R/W
5
R/W
4
R/W
3
R/W
2
R/W
1
R/W
0
R/W
R/W
R/W
R/W
R/W
R/W
Not affected by global reset and JPEG decoder abort.
Starting physical address of input JPEG file in SRAM
Co
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FILE_ADDR
JPEG_FILE_ADDR
TBLS_START_ADD
R
JPEG+0004h JPEG Decoder Control Register
Bit
31
30
29
28
27
Name
Type R/W R/W R/W R/W R/W
Bit
15
14
13
12
11
Name
START_ADDR[15:11]
Type R/W R/W R/W R/W R/W
26
25
24
23
22
START_ADDR[31:16]
R/W R/W R/W R/W
9
8
7
6
R/W
10
21
20
19
18
17
16
R/W
5
R/W
4
R/W
3
R/W
2
R/W
1
R/W
0
The table starting address must be a multiple of 2K. Not affected by global reset and JPEG decoder abort.
reprogramming for multiple runs of progressive images.
START_ADDR The starting address of the memory space for 4 quantization tables and 8 Huffman tables.
memory space must be 2K Bytes at least.
JPEG+0008h JPEG Decoder Control Register
Bit
Name
Type
Bit
30
15
14
29
28
13
12
MT
K
Name
31
Type
27
26
25
24
23
Need
The
SAMP_FACTOR
22
21
20
19
18
17
16
11
10
9
8
7
6
5
4
3
2
1
0
H_SAMP_0[ V_SAMP_0[1 H_SAMP_1[ V_SAMP_1[1 H_SAMP_2[ V_SAMP_2[
1:0]
:0]
1:0]
:0]
1:0]
1:0]
R/W
R/W
R/W
R/W
R/W
R/W
This register contains the sampling factor of YUV components.
Not affected by global reset and JPEG decoder abort.
st
H_SAMP_0 Horizontal sampling factor of the 1 component, Y.
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00 SF is 1
01 SF is 2
10 Invalid
11
SF is 4
V_SAMP_0 Vertical sampling factor of the 1st component, Y.
00 SF is 1
01 SF is 2
10 Invalid
11 SF is 4
H_SAMP_1 Horizontal sampling factor of the 2nd component, U.
00 SF is 1
01 SF is 2
10 Invalid
12
SF is 4
V_SAMP_1 Vertical sampling factor of the 2nd component, U.
00 SF is 1
01 SF is 2
10 Invalid
11
SF is 4
H_SAMP_2 Horizontal sampling factor of the 3rd component, V.
00 SF is 1
01 SF is 2
10 Invalid
13
SF is 4
V_SAMP_2 Vertical sampling factor of the 3rd component, V.
00 SF is 1
01 SF is 2
10 Invalid
11 SF is 4
Revision 1.0
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MT6228 GSM/GPRS Baseband Processor Data Sheet
JPEG+000Ch JPEG Decoder Control Register
Bit
Name
Type
Bit
Name
Type
31
30
15
14
29
28
27
26
COMP0_ID[7:0]
R/W
13
12
11
10
COMP2_ID[7:0]
R/W
COMP_ID
25
24
23
22
9
8
7
6
21
20
19
18
COMP1_ID[7:0]
R/W
5
4
3
2
17
16
1
0
This register contains the IDs of YUV components. Not affected by global reset and JPEG decoder abort.
COMP0_ID The 1st component (Y) ID is extracted from SOF marker.
COMP1_ID The 2nd component (U) ID is extracted from SOF marker.
COMP2_ID The 3rd component (V) ID is extracted from SOF marker.
JPEG+0010h JPEG Decoder Control Register
31
30
29
28
27
26
15
14
13
12
11
10
MT
K
Bit
Name
Type
Bit
Name
Type
25
24
23
22
TOTAL_MCU_NUM[31:16]
R/W
9
8
7
6
TOTAL_MCU_NUM[15:0]
R/W
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TOTAL_MCU_NUM
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19
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16
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2
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This register contains the total MCU number in interleaved scan. Note that if the MCU number is N, program (N-1)
into this register. Not affected by global reset and JPEG decoder abort.
INTLV_MCU_NUM_
PER_MCU_ROW
JPEG+0014h JPEG Decoder Control Register
31
30
29
28
27
26
25
24
15
14
13
12
11
10
9
8
23
22
21
20
Re
lea
se
30
15
14
29
28
13
12
DUMMY_DU
R/W
27
26
25
11
10
9
24
17
16
1
0
Not affected by global reset and JPEG decoder
COMP0_NONINTLV
_DU_NUM_PER_M
CU_ROW
JPEG+0018h JPEG Decoder Control Register
31
18
7
6
5
4
3
2
INTLV_MCU_NUM_PER_MCU_ROW[9:0]
R/W
This register contains the MCU number per row in interleaved scan.
abort.
Bit
Name
Type
Bit
Name
Type
19
fo
r
Bit
Name
Type
Bit
Name
Type
23
22
21
20
19
18
17
8
7
6
5
4
3
2
1
COMP0_NONINTLV_MCU_NUM_PER_MCU_ROW[9:0]
R/W
16
0
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This register contains the MCU number per row in non-interleaved scan of the 1st component (Y). Not affected by
global reset and JPEG decoder abort. Note that COMP0_NONINTLV_MCU_NUM_PER_MCU_ROW includes the
number of DUMMY_DU if any.
MT
K
DUMMY_DU Dummy data unit number in non-interleaved scan of the 1st component
00 no dummy data unit
01 one dummy data unit
10 two dummy data units
11 three dummy data units
COMP0_NONINTLV_MCU_NUM_PER_MCU_ROW The MCU number per row in non-interleaved scan of the
1st component (Y).
In progressive image, dummy data unit columns are inevitable if more than 8 redundant pixel columns are transmitted
to fill up the last MCU in a MCU row. For example, in 422 format, a MCU is composed of 16 x 16 pixels. If a
given image size is 355 x 400, for JPEG encoder to compress, the image grows to 368 x 400 first such that both width
and height are multiples of 16. It can be seen that to be divisible by 16, there are 13 redundant Y-component pixels in
the horizontal (width) direction. These 13 Y-component pixels are compressed by encoders in interleaved scans
because a complete MCU needs 16x16 pixels. It is different from non-interleaved scans, because in non-interleaved
scans a complete MCU only needs 8x8 Y-component pixels. Therefore, among the 13 redundant pixels the first 5 are
still compressed as interleaved scans while the last 8 are dropped. In this case, software must program the
DUMMY_DU field to 1 so the hardware knows one 8x8 data unit should be skipped at the last of a MCU row in
non-interleaved scan.
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COMP1_NONINTLV
_DU_NUM_PER_M
CU_ROW
JPEG+001Ch JPEG Decoder Control Register
31
30
15
14
29
28
13
12
DUMMY_DU
R/W
27
26
25
11
10
9
24
23
22
21
20
19
18
17
8
7
6
5
4
3
2
1
COMP1_NONINTLV_MCU_NUM_PER_MCU_ROW[9:0]
R/W
16
0
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Bit
Name
Type
Bit
Name
Type
Revision 1.0
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MT6228 GSM/GPRS Baseband Processor Data Sheet
This register contains the MCU number per row in non-interleaved scan of the 2nd component (Y). Not affected by
global reset and JPEG decoder abort. Note that COMP1_NONINTLV_MCU_NUM_PER_MCU_ROW includes the
number of DUMMY_DU if any.
Re
lea
se
DUMMY_DU Dummy data unit number in non-interleaved scan of the 2nd component
00 no dummy data unit
01 one dummy data unit
10 two dummy data units
11 three dummy data units
COMP1_NONINTLV_MCU_NUM_PER_MCU_ROW The MCU number per row in non-interleaved scan of the
2nd component (U).
COMP2_NONINTLV
_DU_NUM_PER_M
CU_ROW
JPEG+0020h JPEG Decoder Control Register
31
30
15
14
29
28
27
26
25
24
23
22
21
20
Co
nf
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l
Bit
Name
Type
Bit
Name
Type
13
12
DUMMY_DU
R/W
11
10
9
19
18
17
8
7
6
5
4
3
2
1
COMP2_NONINTLV_MCU_NUM_PER_MCU_ROW[9:0]
R/W
16
0
This register contains the MCU number per row in non-interleaved scan of the 3rd component (V). Not affected by
global reset and JPEG decoder abort. Note that COMP2_NONINTLV_MCU_NUM_PER_MCU_ROW includes the
number of DUMMY_DU if any.
DUMMY_DU Dummy data unit number in non-interleaved scan of the 3rd component
00 no dummy data unit
01 one dummy data unit
10 two dummy data units
11 three dummy data units
COMP2_NONINTLV_MCU_NUM_PER_MCU_ROW The MCU number per row in non-interleaved scan of the
3rd component (V).
COMP0_DATA_UNI
T_NUM
JPEG+0024h JPEG Decoder Control Register
31
30
29
28
27
15
14
13
12
11
MT
K
Bit
Name
Type
Bit
Name
Type
26
25
24
23
22
21
COMP0_DATA_UNIT_NUM[31:16]
R/W
10
9
8
7
6
5
COMP0_DATA_UNIT_NUM[15:0]
R/W
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This register contains the 8x8 data unit number of the 1st component in non-interleaved scans. Note that if the data
unit number is N, program (N-1) into this register. Not affected by global reset and JPEG decoder abort.
COMP1_DATA_UNI
T_NUM
JPEG+0028h JPEG Decoder Control Register
31
30
29
28
27
15
14
13
12
11
26
25
24
23
22
21
COMP1_DATA_UNIT_NUM[31:16]
R/W
10
9
8
7
6
5
COMP1_DATA_UNIT_NUM[15:0]
R/W
20
19
18
4
3
2
17
16
1
0
fo
r
Bit
Name
Type
Bit
Name
Type
Re
lea
se
This register contains the 8x8 data unit number of the 2nd component in non-interleaved frame. Note that if the data
unit number is N, program (N-1) into this register. Not affected by global reset and JPEG decoder abort.
COMP2_DATA_UNI
T_NUM
JPEG+002Ch JPEG Decoder Control Register
Bit
Name
Type
Bit
Name
Type
31
30
29
28
27
15
14
13
12
11
26
25
24
23
22
21
COMP2_DATA_UNIT_NUM[31:16]
R/W
10
9
8
7
6
5
COMP2_DATA_UNIT_NUM[15:0]
R/W
20
19
18
17
16
4
3
2
1
0
Co
nf
id
en
tia
l
This register contains the 8x8 data unit number of the 3rd component in non-interleaved frame. Note that if the data unit
number is N, program (N-1) into this register. Not affected by global reset and JPEG decoder abort.
JPEG+0030h JPEG Decoder Control Register
Bit
Name
Type
Bit
Name
Type
31
30
15
14
29
28
13
12
27
26
25
24
23
22
21
20
COMP0_PROGR_COEFF_START_ADDR[31:16]
R/W
11
10
9
8
7
6
5
4
COMP0_PROGR_COEFF_START_ADDR[15:0]
R/W
COMP0_PROGR_C
OEFF_START_ADD
R
19
18
17
16
3
2
1
0
This register contains the starting address of the memory space storing the intermediate progressive coefficients of the
1st component. This value must be a multiple of 4. Not affected by global reset and JPEG decoder abort.
JPEG+0034h JPEG Decoder Control Register
31
30
15
14
29
28
13
12
MT
K
Bit
Name
Type
Bit
Name
Type
27
26
25
24
23
22
21
20
COMP1_PROGR_COEFF_START_ADDR[31:16]
R/W
11
10
9
8
7
6
5
4
COMP1_PROGR_COEFF_START_ADDR[15:0]
R/W
COMP1_PROGR_C
OEFF_START_ADD
R
19
18
17
16
3
2
1
0
This register contains the starting address of the memory space storing the intermediate progressive coefficients of the
2nd component. This value must be a multiple of 4. Not affected by global reset and JPEG decoder abort.
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Bit
Name
Type
Bit
Name
Type
31
30
29
28
15
14
13
12
27
26
25
24
23
22
21
20
COMP2_PROGR_COEFF_START_ADDR[31:16]
R/W
11
10
9
8
7
6
5
4
COMP2_PROGR_COEFF_START_ADDR[15:0]
R/W
COMP2_PROGR_C
OEFF_START_ADD
R
19
18
3
2
17
16
1
0
fo
r
JPEG+0038h JPEG Decoder Control Register
Revision 1.0
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MT6228 GSM/GPRS Baseband Processor Data Sheet
This register contains the starting address of the memory space storing the intermediate progressive coefficients of the
3rd component. This value must be a multiple of 4. Not affected by global reset and JPEG decoder abort.
JPEG+003Ch JPEG Decoder Control Register
31
Name
Type
Bit
Name
Type
15
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
JPEG
_MOD
DU9[2:0]
DU8[2:0]
DU7[2:0]
DU6[2:0]
DU5[2:0]
E
R/W
R/W
R/W
R/W
R/W
R/W
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DU4[2:0]
DU3[2:0]
DU2[2:0]
DU1[2:0]
DU0[2:0]
R/W
R/W
R/W
R/W
R/W
Re
lea
se
Bit
JPEG_CTRL
This register contains 2 information: the operating mode of JPEG decoder and the order of 3 components in a MCU.
Affected by global reset and JPEG decoder abort. Need reprogramming for multiple runs of progressive images.
MT
K
Co
nf
id
en
tia
l
JPEG_MODE The operating mode of JPEG decoder.
0 Baseline mode
1 Progressive mode
DU9
The 10th data unit component category in a MCU
100 The 10th data unit is the 1st component (Y)
101 The 10th data unit is the 2nd component (U)
110 The 10th data unit is the 3rd component (V)
111 Not used in current frame
000-011
Invalid
th
DU8
The 9 data unit component category in a MCU
100 The 9th data unit is the 1st component (Y)
101 The 9th data unit is the 2nd component (U)
110 The 9th data unit is the 3rd component (V)
111 Not used in current frame
000-011
Invalid
th
DU7
The 8 data unit component category in a MCU
100 The 8th data unit is the 1st component (Y)
101 The 8th data unit is the 2nd component (U)
110 The 8th data unit is the 3rd component (V)
111 Not used in current frame
000-011
Invalid
DU6
The 7th data unit component category in a MCU
100 The 7th data unit is the 1st component (Y)
101 The 7th data unit is the 2nd component (U)
110 The 7th data unit is the 3rd component (V)
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DU3
DU2
DU1
DU0
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Re
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DU4
Co
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id
en
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DU5
111 Not used in current frame
000-011
Invalid
The 6th data unit component category in a MCU
100 The 6th data unit is the 1st component (Y)
101 The 6th data unit is the 2nd component (U)
110 The 6th data unit is the 3rd component (V)
111 Not used in current frame
000-011
Invalid
The 5th data unit component category in a MCU
100 The 5th data unit is the 1st component (Y)
101 The 5th data unit is the 2nd component (U)
110 The 5th data unit is the 3rd component (V)
111 Not used in current frame
000-011
Invalid
th
The 4 data unit component category in a MCU
100 The 4th data unit is the 1st component (Y)
101 The 4th data unit is the 2nd component (U)
110 The 4th data unit is the 3rd component (V)
111 Not used in current frame
000-011
Invalid
rd
The 3 data unit component category in a MCU
100 The 3rd data unit is the 1st component (Y)
101 The 3rd data unit is the 2nd component (U)
110 The 3rd data unit is the 3rd component (V)
111 Not used in current frame
000-011
Invalid
The 2nd data unit component category in a MCU
100 The 2nd data unit is the 1st component (Y)
101 The 2nd data unit is the 2nd component (U)
110 The 2nd data unit is the 3rd component (V)
111 Not used in current frame
000-011
Invalid
The 1st data unit component category in a MCU
100 The 1st data unit is the 1st component (Y)
101 The 1st data unit is the 2nd component (U)
110 The 1st data unit is the 3rd component (V)
111 Not used in current frame
000-011
Invalid
JPEG+0040h JPEG Decoder Control Register
31
30
15
14
29
28
27
26
25
24
13
12
11
10
9
8
JPEG_DEC_TRIG
23
22
21
20
19
18
17
16
7
6
5
4
3
2
1
0
WO
MT
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Bit
Name
Type
Bit
Name
Type
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WO
JPEG_DEC_TRIG triggers JPEG decoding operation no matter what value is programmed.
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JPEG_DEC_ABOR
T
JPEG+0044h JPEG Decoder Control Register
Bit
Name
Type
Bit
Name
Type
31
30
29
28
27
26
25
24
15
14
13
12
11
10
9
8
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MT6228 GSM/GPRS Baseband Processor Data Sheet
23
22
21
20
19
18
17
16
7
6
5
4
3
2
1
0
WO
WO
fo
r
JPEG_DEC_ABORT aborts JPEG decoding operation and reset JPEG decoder hardware no matter what value is
programmed.
JPEG+0048h JPEG Decoder Control Register
31
30
29
28
27
26
15
14
13
12
11
10
JPEG_FILE_BRP
25
24
23
22
JPEG_FILE_BRP[31:16]
R/W
9
8
7
6
JPEG_FILE_BRP[15:0]
R/W
21
20
19
Re
lea
se
Bit
Name
Type
Bit
Name
Type
5
4
3
18
17
16
2
1
0
JPEG_DEC_BRP stands for a 32-bit byte breakpoint address that hardware stalls once the breakpoint address is
encountered. This control register provides a solution for software to swap internal memory content with external
memory in case the JPEG source file is too big for internal memory to store at one time. A breakpoint interrupt fires
when hardware DMA address hits the breakpoint address. Note that the breakpoint address must be a multiple of 4.
Not affected by global reset and JPEG decoder abort.
JPEG_FILE_TOTA
L_SIZE
Bit
Name
Type
Bit
Name
Type
31
30
15
14
Co
nf
id
en
tia
l
JPEG+004Ch JPEG Decoder Control Register
29
28
27
13
12
11
26
25
24
23
22
21
JPEG_FILE_TOTAL_SIZE[31:16]
R/W
10
9
8
7
6
5
JPEG_FILE_TOTAL_SIZE[15:0]
R/W
20
19
18
17
16
4
3
2
1
0
JPEG_FILE_TOTAL_SIZE represents the JPEG source file size in bytes. Hardware fires a file overflow interrupt and
stall if the DMA address equals to this address.
Note that the breakpoint address must be a multiple of 4. If the file size is not divisible by 4, increment the size value
until it is. Not affected by global reset and JPEG decoder abort.
INTLV_FIRST_MC
U_INDEX
JPEG+0050h JPEG Decoder Control Register
Bit
31
30
15
14
Name
28
27
26
21
20
13
12
11
10
9
8
7
6
5
INTLV_FIRST_MCU_INDEX[15:0]
R/W
4
MT
K
Type
Bit
Name
Type
29
25
24
23
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19
18
17
16
INTLV_FIRST_MCU_IND
EX[19:16]
R/W
3
2
1
0
MediaTek Inc. Confidential
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MT6228 GSM/GPRS Baseband Processor Data Sheet
This control register specifies the first MCU index that hardware processes in the interleaved scans of the current image.
The JPEG decoder is able to skip certain MCUs by defining the first and last MCU index. Not affected by global reset
and JPEG decoder abort.
INTLV_LAST_MC
U_INDEX
Bit
31
30
29
28
27
26
25
24
23
22
21
20
15
14
13
12
11
10
9
8
7
6
5
INTLV_LAST_MCU_INDEX[15:0]
R/W
4
Name
Type
Bit
Name
Type
19
18
17
16
INTLV_LAST_MCU_IND
EX[19:16]
R/W
3
2
1
0
fo
r
JPEG+0054h JPEG Decoder Control Register
Re
lea
se
This control register specifies the last MCU index that hardware processes in the interleaved scans of the current image.
The JPEG decoder is able to skip certain MCUs by defining the first and last MCU index. Not affected by global reset
and JPEG decoder abort.
COMP0_FIRST_M
CU_INDEX
JPEG+0058h JPEG Decoder Control Register
Bit
31
30
29
28
27
26
25
24
21
20
15
14
13
12
11
10
9
8
7
6
5
COMP0_FIRST_MCU_INDEX[15:0]
R/W
4
Name
Type
Bit
Name
Type
23
22
19
18
17
16
COMP0_FIRST_MCU_IN
DEX[19:16]
R/W
3
2
1
0
Co
nf
id
en
tia
l
Only effective in progressive images. This control register specifies the first MCU index that hardware processes in
the non-interleaved scans containing Y component of the current image. The JPEG decoder is able to skip certain
MCUs by defining the first and last MCU index. Not affected by global reset and JPEG decoder abort.
COMP0_LAST_M
CU_INDEX
JPEG+005Ch JPEG Decoder Control Register
Bit
31
30
15
14
Name
Type
Bit
Name
Type
29
28
27
26
25
24
23
22
21
20
13
12
11
10
9
8
7
6
5
COMP0_LAST_MCU_INDEX[15:0]
R/W
4
19
18
17
16
COMP0_LAST_MCU_IN
DEX[19:16]
R/W
3
2
1
0
Only effective in progressive images. This control register specifies the last MCU index that hardware processes in
the non-interleaved scans containing Y component of the current image. The JPEG decoder is able to skip certain
MCUs by defining the first and last MCU index. Not affected by global reset and JPEG decoder abort.
COMP1_FIRST_M
CU_INDEX
MT
K
JPEG+0060h JPEG Decoder Control Register
Bit
31
30
29
28
27
26
25
24
23
22
21
20
15
14
13
12
11
10
9
8
7
6
5
4
Name
Type
Bit
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18
17
16
COMP1_FIRST_MCU_IN
DEX[19:16]
R/W
3
2
1
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Name
Type
Revision 1.0
Ko
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MT6228 GSM/GPRS Baseband Processor Data Sheet
COMP1_FIRST_MCU_INDEX[15:0]
R/W
Only effective in progressive images. This control register specifies the first MCU index that hardware processes in
the non-interleaved scans containing U component of the current image. The JPEG decoder is able to skip certain
MCUs by defining the first and last MCU index. Not affected by global reset and JPEG decoder abort.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
15
14
13
12
11
10
9
8
7
6
5
COMP1_LAST_MCU_INDEX[15:0]
R/W
4
Type
Bit
Name
Type
19
18
17
16
COMP1_LAST_MCU_IN
DEX[19:16]
R/W
3
2
1
0
Re
lea
se
Name
fo
r
COMP1_LAST_M
CU_INDEX
JPEG+0064h JPEG Decoder Control Register
Only effective in progressive images. This control register specifies the last MCU index that hardware processes in
the non-interleaved scans containing U component of the current image. The JPEG decoder is able to skip certain
MCUs by defining the first and last MCU index. Not affected by global reset and JPEG decoder abort.
COMP2_FIRST_M
CU_INDEX
JPEG+0068h JPEG Decoder Control Register
Bit
31
30
29
28
27
26
25
24
21
20
15
14
13
12
11
10
9
8
7
6
5
COMP2_FIRST_MCU_INDEX[15:0]
R/W
4
Type
Bit
Name
Type
Co
nf
id
en
tia
l
Name
23
22
19
18
17
16
COMP2_FIRST_MCU_IN
DEX[19:16]
R/W
3
2
1
0
Only effective in progressive images. This control register specifies the first MCU index that hardware processes in
the non-interleaved scans containing V component of the current image. The JPEG decoder is able to skip certain
MCUs by defining the first and last MCU index. Not affected by global reset and JPEG decoder abort.
COMP2_LAST_M
CU_INDEX
JPEG+006Ch JPEG Decoder Control Register
Bit
31
30
15
14
Name
Type
Bit
Name
Type
29
28
27
26
25
24
23
22
21
20
13
12
11
10
9
8
7
6
5
COMP2_LAST_MCU_INDEX[15:0]
R/W
4
19
18
17
16
COMP2_LAST_MCU_IN
DEX[19:16]
R/W
3
2
1
0
MT
K
Only effective in progressive images. This control register specifies the last MCU index that hardware processes in the
non-interleaved scans containing V component of the current image.
The JPEG decoder is able to skip certain
MCUs by defining the first and last MCU index. Not affected by global reset and JPEG decoder abort.
JPEG+0070h JPEG Decoder Control Register
Bit
Name
Type
31
30
29
28
27
26
25
24
23
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Bit
Name
Type
15
14
13
12
11
10
9
8
COMP0_QT_ID[3:0]
R/W
7
6
5
4
COMP1_QT_ID[3:0]
R/W
This register contains the quantization table IDs for YUV components.
abort.
3
2
1
0
COMP2_QT_ID[3:0]
R/W
Not affected by global reset and JPEG decoder
JPEG_DEC_INTE
RRUPT_STATUS
JPEG+0074h JPEG Decoder Control Register
30
29
28
27
26
25
24
15
14
13
12
11
10
9
8
The register reflects the interrupt status.
INT2
INT1
INT0
Set to 1 by file overflow interrupt
Set to 1 by breakpoint interrupt
Set to 1 by end of file interrupt
23
22
21
20
7
6
5
4
31
30
29
28
FOS BRPS EOFS
Type
Bit
15
RO
14
Name
SOS_PARSER_STATE
Type
RO
6.11
6.11.1
26
25
24
23
JPEG_DEC_STATE
22
RO
13
RO
12
11
RO
10
9
8
7
DHT_PARSER_STAT
E
RO
21
20
HUFF_DEC_STATE
Co
nf
id
en
tia
l
Name
27
3
18
17
16
2
1
0
INT2 INT1 INT0
RO
RO
RO
JPEG_DEC_STAT
US
JPEG+0078h JPEG Decoder Control Register
Bit
19
Re
lea
se
31
fo
r
COMP0_QT_ID Quantization table ID of Y component directly extracted from SOF marker
COMP1_QT_ID Quantization table ID of U component directly extracted from SOF marker
COMP2_QT_ID Quantization table ID of V component directly extracted from SOF marker
Bit
Name
Type
Bit
Name
Type
Revision 1.0
Ko
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MT6228 GSM/GPRS Baseband Processor Data Sheet
RO
6
5
4
DQT_PARSER_STA
TE
RO
19
18
17
16
MARKER_PARSER_STAT
E
RO
3
2
1
0
DATA_UNIT_STATE
RO
JPEG Encoder
General Descriptions
MT
K
The hardware JPEG encoder implements the baseline mode of Standard ISO/IEC 10918-1. It supports YUV 422 and
420 formats for color pictures and grayscale format. With the software assist and suitable destination memory address
setting, JFIF/EXIF JPEG format can also be supported. For hardware reduction, it uses standard DC and AC Huffman
tables for both the luminance and chrominance components. To adjust the picture compression ratio and picture
quality, there are 4 levels of quantization that can be programmed. After initialization by software, the hardware
JPEG encoder can generate the entire compressed file.
Figure 1 shows the procedure of the JPEG encoder. The YUV pixel data that came from image DMA are grouped
into 8x8 blocks and then down-sampled to YUV 422 and YUV420 format. For grayscale encoding, only Y
component is present. When encoding, the first thing to do is to turn the pixel data into the frequency domain using
FDCT. After the quantizer is done, the quantized DCT coefficients are encoded by RLE and VLC.
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8 x 8 blocks
Quantizer
FDCT
RLE/VLC
Table specifications
Table specifications
Register Definitions
JPEG = 0x8060_0000
Register Address
Register Function
JPEG + 008Ch
JPEG encoder reset register
Re
lea
se
Figure 1 The procedure of JPEG encoder
fo
r
Compressed image data
YUV image data
6.11.2
Revision 1.0
Ko
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MT6228 GSM/GPRS Baseband Processor Data Sheet
Acronym
JPG_ENC_RST
JPG_ENC_CTL
JPEG encoder control register
JPEG encoder interrupt status register
JPG_ENC_INTSTS
JPEG + 0098h
JPEG encoder block count register
JPG_ENC_BLK_CNT
JPEG + 009Ch
JPEG encoder quality register
JPG_ENC_QUALITY
JPEG + 00a0h
JPEG encoder base address register
JPG_ENC_DEST_ADDR
JPEG + 00a4h
JPEG encoder DMA address register
JPG_ENC_DMA_ADDR
JPEG + 00a8h
JPEG encoder STALL address register
JPG_ENC_STALL_ADDR
JPEG encoder frame number register
JPG_ENC_FRAME_NUM
JPEG encoder frame count register
JPG_ENC_FRAME_CNT
JPEG encoder base address2 register
JPG_ENC_DEST_ADDR2
JPEG encoder DMA address2 register
JPG_ENC_DMA_ADDR2
JPEG encoder STALL address2 register
JPG_ENC_STALL_ADDR2
JPEG + 00ach
JPEG + 00b0h
JPEG + 00b4h
JPEG + 00b8h
JPEG + 00bch
Co
nf
id
en
tia
l
JPEG + 0090h
JPEG + 0094h
Table 51 JPEG encoder Registers
JPEG+008ch JPEG encoder reset register
Bit
Name
Type
Reset
Bit
Name
30
15
14
29
28
27
26
25
24
23
22
21
20
19
18
17
16
13
12
11
10
9
8
7
6
5
4
ADDR
_RL
WC
0
3
2
1
0
RST
R/W
0
MT
K
Type
Reset
31
JPG_ENC_RST
RST
Reset the JPEG encoder.
ADDR_RL DMA address reload only for the stall condition. In other condition, this bit cannot be set. This is a
Write-Clear register. This register must be set once after the stall destination address is reconfigured in
the stall condition.
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Bit
Name
Type
Reset
Bit
JPEG encoder control register
JPG_ENC_CTL
31
30
29
28
27
26
25
24
23
15
14
13
12
11
10
9
8
7
Name
Type
Reset
22
21
20
6
5
4
ADDR
CONT JPG
_SW
R/W R/W R/W
0
0
0
EN
GRAY
19
18
3
2
YUV
IT
R/W
0
R/W
1
17
16
1
0
GRAY EN
R/W
0
fo
r
JPEG+0090h
Revision 1.0
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MT6228 GSM/GPRS Baseband Processor Data Sheet
R/W
0
JPEG+0094h
Bit
Name
Type
Reset
Bit
Co
nf
id
en
tia
l
Re
lea
se
Enable the JPEG encoder. This bit is cleared by hardware after encoding is done.
Do grayscale encode. Remember that the image DMA should be programmed as grayscale too.
0 color
1 grayscale
IT
Interrupt enabling
0 Disable
1 Enable
YUV
YUV format
0 YUV 422
1 YUV 420
JPG
JPEG or other application format support
0 JPEG
1 JFIF/EXIF
CONT
JPEG continuous shooting
0 OFF
1 ON
ADDR_SW JPEG destination address switch in continuous shooting mode
0 OFF, destination address accumulates
1 ON, destination address switches between JPG_ENC_DEST_ADDR and JPG_ENC_DEST_ADDR2.
31
30
29
28
27
26
25
24
23
22
15
14
13
12
11
10
9
8
7
6
Name
Type
Reset
DONE
STALL
JPEG+0098h
Bit
31
21
20
5
4
STAL STAL
L2
L1
RO
RO
0
0
19
18
3
2
17
16
1
0
STAL
DONE
L
RO
RC
0
0
Indicates that encoding operation is done. This is a Read-Clear bits.
Indicates that encoding operation is in the stall condition. This bit is not cleared until the stall condition
is cleared and reload bit is set.
Indicates that the current stall condition is caused by DMA_ADDR and STALL_ADDR.
Indicates that the current stall condition is caused by DMA_ADDR2 and STALL_ADDR2.
MT
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STALL1
STALL2
JPG_ENC_INTS
TS
JPEG encoder interrupt status register
30
JPG_ENC_BLK
_CNT
JPEG block count register
29
28
27
26
25
24
23
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22
21
20
19
18
17
16
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Name
Type
Reset
Bit
Name
Type
Reset
15
14
13
12
11
10
9
8
7
BLK_CNT
RO
0
6
5
4
3
2
BLK_CNT Block count has been encoded.
31
30
29
28
27
26
25
24
23
22
21
20
15
14
13
12
11
10
9
8
7
6
5
4
QUALITY
01
19
18
17
16
3
2
1
0
QUALITY
R/W
00
Encode quality.
00 Low quality (quality factor =50), 15~20 times compression ratio.
Fair quality (quality factor =75) , 10~15 times compression ratio
10 Good quality (quality factor =90), 6~10 times compression ratio
11 High quality (quality factor =95), 4~6 times compression ratio
JPEG+00a0h
JPG_ENC_DEST_
ADDR
JPEG encoder base address register
31
30
29
28
27
26
15
14
13
12
11
10
25
24
23
22
BS_ADDR[31:16]
R/W
0
9
8
7
6
BS_ADDR[15:0]
R/W
0
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Bit
Name
Type
Reset
Bit
Name
Type
Reset
0
JPG_ENC_QUALIT
Y
JPEG encoder quality register
Re
lea
se
Bit
Name
Type
Reset
Bit
Name
Type
Reset
1
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JPEG+009ch
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21
20
19
18
17
16
5
4
3
2
1
0
BS_ADDR Base address of encoded data.
JPEG+00a4h
Bit
Name
Type
Reset
Bit
Name
Type
Reset
JPG_ENC_CURR_
ADDR
JPEG encoder current address register
31
30
29
28
27
26
15
14
13
12
11
10
25
24
23
22
DMA_ADDR[31:16]
RO
0
9
8
7
6
DMA_ADDR[15:0]
RO
0
21
20
19
18
17
16
5
4
3
2
1
0
MT
K
CURR_ADDR The current DMA address during encoding.
JPEG+00a8h
Bit
31
30
JPG_ENC_STALL_
ADDR
JPEG encoder STALL address register
29
28
27
26
25
24
23
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22
21
20
19
18
17
16
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Name
Type
Reset
Bit
Name
Type
Reset
15
14
13
12
11
10
STALL_ADDR[31:16]
R/W
0
9
8
7
6
STALL_ADDR[15:0]
R/W
0
5
4
3
2
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1
0
JPEG+00ach
31
30
29
28
27
26
25
24
15
14
13
12
11
10
9
8
FRAME_NUM
22
21
20
7
6
5
4
19
18
3
2
FRAME_NUM
R/W
0
JPEG encoder continuous shooting current frame
count
31
30
29
28
27
26
25
24
23
22
21
20
15
14
13
12
11
10
9
8
7
6
5
4
FRAME_CNT
17
16
1
0
JPG_ENC_CUR
R_FRAME_CNT
19
18
3
2
FRAME_CNT
R/O
0
17
16
1
0
Frame count has been encoded.
JPEG+00b4h
JPG_ENC_DEST_
ADDR2
JPEG encoder 2nd base address register
31
30
29
28
27
26
15
14
13
12
11
10
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Bit
Name
Type
Reset
Bit
Name
Type
Reset
23
Frame number in continuous shooting is encoded
JPEG+00b0h
Bit
Name
Type
Reset
Bit
Name
Type
Reset
JPG_ENC_FRA
ME_NUM
JPEG encoder continuous shooting frame number
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Bit
Name
Type
Reset
Bit
Name
Type
Reset
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STALL_ADDR This field is the upper bound of JPEG encoder’s write-address. Note that the stall address must be
word-aligned. Whenever the stall address is reached, the JPEG encoder stalls and issues an interrupt to software.
After, if the software programs the JPG_ENC_STALL_ADDR to another value, the JPEG encoder resumes the
encoding procedure and automatically use the JPG_ENC_DEST_ADDR as the new starting address. It means that
before we change the value of JPG_ENC_STALL_ADDR, the JPG_ENC_DEST_ADDR has to be programmed to a
corresponding starting address. However, if the software wants to discard the uncompleted file, it can simply reset the
JPEG encoder to cancel the encode operation. Also, it is important that the value of JPG_ENC_STALL_ADDR
should be larger than JPG_ENC_DEST_ADDR by at least 604 bytes to guarantee that the header of the JPEG file can
be completely written into memory.
25
24
23
22
BS_ADDR[31:16]
R/W
0
9
8
7
6
BS_ADDR[15:0]
R/W
0
21
20
19
18
17
16
5
4
3
2
1
0
BS_ADDR Base address of 2nd encoded data.
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30
29
28
27
26
15
14
13
12
11
10
21
20
19
18
5
4
3
2
The current DMA address during 2nd encoding.
CURR_ADDR
JPEG+00bch
Bit
Name
Type
Reset
Bit
Name
Type
Reset
25
24
23
22
DMA_ADDR[31:16]
RO
0
9
8
7
6
DMA_ADDR[15:0]
RO
0
30
29
28
27
26
15
14
13
12
11
10
25
24
23
22
STALL_ADDR2[31:16]
R/W
0
9
8
7
6
STALL_ADDR2[15:0]
R/W
0
JFIF/EXIF support
1
0
21
20
19
18
17
16
5
4
3
2
1
0
STALL_ADDR2 This field is the upper bound of JPEG encoder’s write-address2.
works in continuous shooting and memory auto-switch mode.
6.11.2.1
16
JPG_ENC_STALL_
ADDR2
JPEG encoder STALL address2 register
31
17
fo
r
31
Re
lea
se
Bit
Name
Type
Reset
Bit
Name
Type
Reset
JPG_ENC_CURR_
ADDR2
JPEG encoder 2nd current address register
JPEG+00b8h
Revision 1.0
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MT6228 GSM/GPRS Baseband Processor Data Sheet
Note that the stall address2 only
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In JFIF/EXIF mode, the JPEG encoder does not generate SOI marker and related thumbnail header and small image
data. The JPEG encoder just outputs the bitstreams from DQT marker. The software needs to provide the suitable
destination address after estimating the size of SOI marker, related thumbnail header and small image data. The SOI
marker and related thumbnail header need to be handled by MCU and the small image data can be output by IMGDMA.
With the suitable destination address configuration, the JFIF/EXIF JPEG format can be generated. Figure 2 illustrates
the data partition for JFIF/EXIF support. Before JPEG encoding, three suitable address configurations provides.
The ADDR1 is provided to SOI maker and the thumbnail header. This part is handled by software. The ADDR2 is
provided to IMGDMA to write RGB small image data. The last address, ADDR3, provides to the JPEG encoder to
write out remaining bitstreams.
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SOI marker
Thumbnail header
Thumbnail (RGB)
Frame header
Sc an
EOI marker
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Table misc
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MT6228 GSM/GPRS Baseband Processor Data Sheet
6.12
6.12.1
GIF Decoder
General Description
Re
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Figure 2. The JFIF/EXIF data structure.
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GIF Decoder is aimed to decode GIF images. This hardware-assisted gif decoding alleviates the software from
computation-intensive jobs, and frees the MCU for other jobs. For a handheld device with multimedia functionality,
this kind of hardware acceleration is very beneficial for MCU off loading and achieving high performance. Figure 29
shows the GIF file structure. The GIF decoder is aimed to do LZW decompression, on-the-fly resizing down, clipping
and pitching; header parsing is performed by software.
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Global
Screen
Descriptior
Signature GIF
Version 87a 89a
Logical Screen
Width, Height
Global color table, ...
fo
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Header
R0, 1 byte
G0, 1 byte
B0, 1 byte
R1, 1 byte
G1, 1 byte
B1, 1 byte
...
h01
hF9
hFE
hFF
Extension
Block
Re
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Global
Color
Table
Plain text extension
:
Graphic control extension :
Comment extension
:
Application extension
:
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MT6228 GSM/GPRS Baseband Processor Data Sheet
Image Block
ImageHeader
Local color
Table
Minimum
code size
Data block 1
Data block 2
Data block n
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Terminator
Figure 29 GIF file structure
6.12.2
Register Definitions
GIFDEC+0000
Input File Start Address
h
Bit
Name
Type
Reset
Bit
Name
Type
Reset
31
30
15
14
29
28
27
13
12
11
INFILE_START_AD
DR
26
25
24
23
22
21
INFILE_START_ADDR[31:16]
R/W
0
10
9
8
7
6
5
INFILE_START_ADDR[15:0]
R/W
0
20
19
18
17
16
4
3
2
1
0
INFILE_START_ADDR
The input file starting address. GIF decoder gets decompression data from this address.
The address does not need to be word aligned.
MT
K
GIFDEC+0004
Input File count
h
Bit
Name
Type
Reset
31
30
29
28
27
INFILE_COUNT
26
25
24
23
22
INFILE_COUNT31:16]
R/W
0
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17
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15
14
13
INFILE_COUNT
12
11
10
9
8
7
6
INFILE_COUNT15:0]
R/W
0
5
4
30
29
28
27
26
15
14
13
12
11
10
25
24
23
22
CT_START_ADDR[31:16]
R/W
0
9
8
7
6
CT_START_ADDR [15:0]
R/W
0
21
20
5
4
19
18
17
16
3
2
1
0
30
29
28
27
26
15
14
13
12
11
10
25
24
23
22
CT_END_ADDR[31:16]
R/W
0
9
8
7
6
CT_END_ADDR[15:0]
R/W
0
21
20
19
18
17
16
5
4
3
2
1
0
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31
CT_END_ADDR
The color table end address. It needs to be word aligned.
GIFDEC+0010
LZW Decompression Tree Start Address
h
Bit
Name
Type
Reset
Bit
Name
Type
Reset
31
30
15
14
0
The color table starting address. It needs to be word aligned, and each palette entry is one word.
GIFDEC+000C
Color Table End Address
h
CT_END_ADDR
1
CT_START_AD
DR
Re
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se
31
CT_START_ADDR
Bit
Name
Type
Reset
Bit
Name
Type
Reset
2
GIF decoder supports pause-resume mechanism, i.e., gif decoder would stop decompressing
when input file is empty, and wait for notice from software. Input file count is assigned for this
issue. When gif decoder encounters infile count, it will stop and indicate by interrupt.
GIFDEC+0008
Color Table Start Address
h
Bit
Name
Type
Reset
Bit
Name
Type
Reset
3
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Bit
Name
Type
Reset
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MT6228 GSM/GPRS Baseband Processor Data Sheet
29
28
27
13
12
11
TREE_START_
ADDR
26
25
24
23
22
21
TREE_START_ADDR[31:16]
R/W
0
10
9
8
7
6
5
TREE_START_ADDR[15:0]
R/W
0
20
19
18
17
16
4
3
2
1
0
TREE_START_ADDR
The LZW decompressing tree starting address. This tree, or called ‘dictionary’, is
essential for LZW decompression. It needs to be word aligned.
MT
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GIFDEC+0014
LZW Decompression Tree END Address
h
Bit
Name
Type
Reset
Bit
Name
31
30
29
28
27
26
15
14
13
12
11
10
25
24
23
22
TREE_END_ADDR[31:16]
R/W
0
9
8
7
6
TREE_END_ADDR[15:0]
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DR
21
20
19
18
17
16
5
4
3
2
1
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Reset
R/W
0
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TREE_END_ADDR The LZW decompressing tree end address. The end address is set to prevent gif decoder from
writing the wrong memory sections. When this happens, gif decoder would stop and generates an interrupt to inform
software. It needs to be word aligned.
GIFDEC+0018
LZW Decode Stack Start Address
h
30
29
28
27
26
15
14
13
12
11
10
25
24
23
22
STK_START_ADDR[31:16]
R/W
0
9
8
7
6
STK_START_ADDR[15:0]
R/W
0
21
20
5
4
19
18
17
16
3
2
1
0
fo
r
31
Re
lea
se
Bit
Name
Type
Reset
Bit
Name
Type
Reset
STK_START_A
DDR
STK_START_ADDR The stack starting address. The stack is for LZW decompression usage. It needs word aligned.
GIFDEC+001C
LZW Decode Stack End Address
h
31
30
29
28
27
26
15
14
13
12
11
10
25
24
23
22
STK_END_ADDR[31:16]
R/W
0
9
8
7
6
STK_END_ADDR[15:0]
R/W
0
21
20
19
18
17
16
5
4
3
2
1
0
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Bit
Name
Type
Reset
Bit
Name
Type
Reset
STK_END_ADD
R
STK_END_ADDR
The stack end address. The end address is set to prevent gif decoder from writing the wrong
memory sections. When this happens, gif decoder would stop and generates an interrupt to inform software. It needs to
be word aligned.
GIFDEC+0020
Output File Start Address
h
Bit
Name
Type
Reset
Bit
Name
Type
Reset
31
30
15
14
29
28
27
13
12
11
26
25
24
23
22
21
OUTFILE_START_ADDR[31:16]
R/W
0
10
9
8
7
6
5
OUTFILE_START_ADDR[15:0]
R/W
0
OUTFILE_START_
ADDR
20
19
18
17
16
4
3
2
1
0
OUTFILE_START_ADDR Output file start address. It needs word aligned.
GIFDEC+0024
Output File End Address
h
31
30
29
28
27
15
14
13
12
11
MT
K
Bit
Name
Type
Reset
Bit
Name
OUTFILE_END_AD
DR
26
25
24
23
22
21
OUTFILE_END_ADDR[31:16]
R/W
0
10
9
8
7
6
5
OUTFILE_END_ADDR[15:0]
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16
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3
2
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Reset
R/W
0
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MT6228 GSM/GPRS Baseband Processor Data Sheet
OUTFILE_END_ADDR
Output file end address. The end address is set to prevent gif decoder from writing the
wrong memory sections. When this happens, gif decoder would stop and generates an interrupt to inform software. It
needs to be word aligned.
GIFDEC+0028
GIF Decompression Enable
h
31
30
29
28
27
26
25
24
23
22
21
20
15
14
13
12
11
10
9
8
7
6
5
4
19
18
17
3
2
1
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Bit
Name
Type
Reset
Bit
DEC_EN
Type
Reset
DEC_EN
31
30
29
28
27
26
25
24
23
22
BOUNDARY
21
20
19
18
17
16
5
4
3
2
1
0
R
0
15
14
13
12
11
10
9
8
7
6
FILE_BOUNDAARY[15:0]
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R
0
Report the file boundary that gif decoder just fetched.
GIFDEC+0030
LZW Min Code Size
h
31
30
15
14
MIN_CODE_SIZE
MIN_CODE_SIZ
E
29
28
27
26
25
24
23
22
21
20
19
13
12
11
10
9
8
7
6
5
4
3
18
17
16
2
1
0
MIN_CODE_SIZE
R/W
0
GIF min code size for LZW decompression. Reasonable value is 2-11.
GIFDEC+0034
Interlace Control Register
h
INTERLACE_CT
RL
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
MT
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Bit
Name
Type
Reset
Bit
R/W
0
FILE_BOUNDAARY[31:16]
BOUNDARY
Bit
Name
Type
Reset
Bit
Name
Type
Reset
0
DEC_
EN
GIF decoder enable signal. And it will de-asserted when decompression finishes.
GIFDEC+002C
GIF File Boundary
h
Bit
Name
Type
Reset
Bit
Name
Type
Reset
Re
lea
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Name
16
16
0
INTER
LACE
Name
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Type
Reset
R/W
0
INTERLACE
Interlace enable for GIF decoder.
0
Non-interlaced
1
Interlaced
GIFDEC+0038
Image width and height register
h
30
29
28
27
26
15
14
13
12
11
10
25
24
23
22
IMG_WIDTH[15:0]
R/W
0
9
8
7
6
IMG_HEIGHT[15:0]
R/W
0
IMG_WIDTH Image width.
IMG_HEIGHT Image height.
GIFDEC+003C
Resize control register
h
Name
Type
Reset
31
30
29
28
27
26
25
24
15
14
13
12
11
10
9
8
20
5
4
HT
19
18
17
16
3
2
1
0
RESIZE_CTRL
23
22
21
20
19
18
17
7
6
5
4
3
2
1
RESIZE_H_RATIO
RESIZE_W_RATIO
R/W
0
R/W
0
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Bit
Name
Type
Reset
Bit
21
fo
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31
Re
lea
se
Bit
Name
Type
Reset
Bit
Name
Type
Reset
IMG_WIDTH_HEIG
16
0
RESIZ
E_EN
R/W
0
MT
K
Since input file for gif decoder might be an interlaced file, the gif decoder cannot perform decompress and resize by
resizer at the same time. Hence, there needs a built-in resizer in gif decoder. There is a drop line and drop pixel sizing
down resizer in gif decoder.
RESIZE_EN
Enable resize on the fly
0: disable
1: enable
RESIZE_W_RATIO Resize ratio in width
0: no resize
1: ½
2: ¼
3: 1/8
4: 1/16
5: 1/32
6: 1/64
7: 1/128
8: 1/256
9: 1/512
10: 1/1024
11: 1/2048
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12: 1/4096
13: 1/8192
14: 1/16384
15: 1/32768
RESIZE_H_RATIO Resize ratio in height
0: no resize
1: ½
2: ¼
3: 1/8
4: 1/16
5: 1/32
6: 1/64
7: 1/128
8: 1/256
9: 1/512
10: 1/1024
11: 1/2048
12: 1/4096
13: 1/8192
14: 1/16384
15: 1/32768
GIFDEC+0040
Transparent Control Register
h
31
30
15
14
Name
29
28
27
26
25
24
23
Co
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Bit
Name
Type
Reset
Bit
13
12
11
10
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MT6228 GSM/GPRS Baseband Processor Data Sheet
9
8
7
TRANS_CTRL
22
21
20
19
18
6
5
4
3
2
TRANS_CL_KEY
Type
Reset
R/W
0
17
16
1
0
TRAN
TRAN
S_TP
S_EN
YE
R/W R/W
0
0
Since input file for gif decoder might include transparent color key, gif decoder would handle transparent files
according to setting as following.
TRANS_EN
Transparent enable.
0: disable transparent
1: enable transparent
TRANS_TYPE Transparent handling method.
0: replace transparent color as background color.
1: no output when encounter transparent color.
TRANS_CL_KEY
Transparent color key.
MT
K
GIFDEC+0044
Background Color
h
Bit
Name
Type
Reset
31
30
29
28
27
26
BG_COLOR
25
24
23
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22
21
20
19
18
BG_COLOR_B
R/W
0
17
16
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Bit
Name
Type
Reset
15
14
13
12
11
10
BG_COLOR_G
R/W
0
9
8
7
6
5
4
3
BG_COLOR_R
R/W
0
2
BG_COLOR_R Background R for transparent output.
BG_COLOR_G Background G for transparent output.
BG_COLOR_B Background B for transparent output.
GIFDEC+004C
LCD width and height register
h
30
29
28
27
26
25
15
14
13
12
11
10
9
24
23
LCD_W
R/W
0
8
7
LCD_H
R/W
0
22
21
20
6
5
4
fo
r
31
1
0
LCD_WH
19
18
17
16
3
2
1
0
Re
lea
se
Bit
Name
Type
Reset
Bit
Name
Type
Reset
Revision 1.0
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MT6228 GSM/GPRS Baseband Processor Data Sheet
To speed up gif display and reduce memory usage, gif decoder supports clipping and pitching function. To support
clipping and pitching, LCD width and height are essential for gif decoder.
LCD_W
LCD width
LCD_H
LCD height
GIFDEC+0050
Clipping window XY register
h
31
30
15
14
29
28
27
26
25
24
23
CLIP_X
R/W
0
8
7
CLIP_Y
R/W
0
Co
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Bit
Name
Type
Reset
Bit
Name
Type
Reset
13
12
11
10
9
CLIP_XY
22
21
20
19
18
17
16
6
5
4
3
2
1
0
To speed up gif display and reduce memory usage, gif decoder supports clipping and clipping function. To support
clipping and pitching, clipping window-starting point is necessary for gif decoder.
CLIP_X
CLIP_X[15] sign bit: 0: positive 1: negative
CLIP_X[14:0] coordinate X for clipping window
CLIP_Y
CLIP_Y[15] sign bit: 0: positive 1: negative
CLIP_Y[14:0] coordinate Y for clipping window
GIFDEC+0054
Clipping window width and height register
h
31
30
15
14
29
28
27
26
25
13
12
11
10
9
MT
K
Bit
Name
Type
Reset
Bit
Name
Type
Reset
24
23
CLIP_W
R/W
0
8
7
CLIP_H
R/W
0
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22
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19
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16
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Revision 1.0
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MT6228 GSM/GPRS Baseband Processor Data Sheet
To speed up gif display and reduce memory usage, gif decoder supports clipping and clipping function. To support
clipping and pitching, clipping window dimension is necessary for gif decoder.
CLIP_W
Clipping window width
CLIP_H
Clipping window height
GIFDEC+0058
Image XY
h
30
29
28
27
26
25
15
14
13
12
11
10
9
24
23
IMG_X
R/W
0
8
7
IMG_Y
R/W
0
22
21
20
6
5
4
19
18
17
fo
r
31
3
2
Re
lea
se
Bit
Name
Type
Reset
Bit
Name
Type
Reset
IMG_XY
1
16
0
To speed up gif display and reduce memory usage, gif decoder supports clipping and clipping function. To support
clipping and pitching, image-starting point is necessary for gif decoder.
IMG_X
IMG_X[15] sign bit: 0: positive 1: negative
IMG_X[14:0] X for image logic window
IMG_Y
IMG_Y[15] sign bit: 0: positive 1: negative
IMG_Y[14:0] Y for image logic window
GIFDEC+005C
Image offset XY
h
31
30
15
14
29
28
27
26
25
24
23
22
IMG_OFFSET_X
R/W
0
9
8
7
6
IMG_OFFSET_Y
R/W
0
Co
nf
id
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tia
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Bit
Name
Type
Reset
Bit
Name
Type
Reset
IMG_OFFSET_X
Y
13
12
11
10
21
20
19
18
17
16
5
4
3
2
1
0
To speed up gif display and reduce memory usage, gif decoder supports clipping and clipping function. To support
clipping and pitching, image starting offset is necessary for gif decoder.
IMG_OFFSET_X
IMG_OFFSET_X[15:0] offset X for image logic window
IMG_OFFSET_Y
IMG_OFFSET_Y[15:0] offset Y for image logic window
GIFDEC+0060
Interrupt Enable Register
h
Bit
Name
Type
Reset
Bit
31
30
15
14
29
28
27
26
25
24
23
13
12
11
10
9
8
7
MT
K
Name
Type
Reset
IMG_CMP
INEMPTY
IRQ_EN
22
21
20
19
18
17
16
6
5
4
3
2
1
0
TREE
STAC
TREE
OUTF INEM IMG_C
ERRO
KFUL PIXEL
FULL
ULL PTY MP
R
L
R/W R/W R/W R/W R/W R/W R/W
0
0
0
0
0
0
0
Image decompressed complete interrupt enable.
Input file empty interrupt enable.
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OUTFULL
PIXEL
STACKFULL
TREEFULL
TREEERROR
Output file full interrupt enable.
Pixel output num error interrupt enable.
Stack output full interrupt enable.
Tree full interrupt enable.
Decompression error interrupt enable.
GIFDEC+0064
Interrupt Status
h
IRQ_STATUS
31
30
29
28
27
26
25
24
23
15
14
13
12
11
10
9
8
7
Type
Reset
IMG_CMP
INEMPTY
OUTFULL
PIXEL
STACKFULL
TREEFULL
TREEERROR
Image decompressed complete interrupt.
Input file empty interrupt.
Output file full interrupt.
Pixel output num errors interrupt.
Stack output full interrupt.
Tree full interrupt.
Decompression error interrupt.
GIFDEC+0068
GIF Reset
h
31
30
15
14
RST
20
19
29
28
27
26
25
24
23
22
21
20
19
18
17
13
12
11
10
9
8
7
6
5
4
3
2
1
16
16
0
RST
R/W
0
Reset for GIF decoder. Write 0x1201, then hardware will reset itself.
31
30
15
14
OUT_FORMAT
29
28
27
26
25
24
23
22
21
20
19
18
17
16
13
12
11
10
9
8
PACK
_INDE
X
R/W
0
7
6
5
4
3
2
1
0
MT
K
Name
Type
Reset
17
RST
GIFDEC+006C
Color Output Format
h
Bit
Name
Type
Reset
Bit
18
6
5
4
3
2
1
0
TREE
STAC
OUTF INRM IMG_C
TREE
ERRO
KFUL PIXEL
ULL PTY MP
FULL
R
L
R
R
R
R
R
R
R
0
0
0
0
0
0
0
Co
nf
id
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tia
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Bit
Name
Type
Reset
Bit
Name
Type
Reset
21
Re
lea
se
Name
22
fo
r
Bit
Name
Type
Reset
Bit
Revision 1.0
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MT6228 GSM/GPRS Baseband Processor Data Sheet
PACK_INDEX_DEPTH
R/W
‘b1000
PARTI
AL
OUT_FORMA
T
R/W
0
OUT_FORMAT To support different applications, gif decoder output data as rgb565, rgb888 and color index mode.
2’b00: RGB565
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r
2’b01: RGB888
2’b10: Index
PARTIAL
To reduce memory usage, gif decoder support pause-resume mechanism when input file is empty
according setting as blow.
1: enable partial input, i.e. pause-resume mechanism.
0: disable partial input, i.e. pause-resume mechanism.
PACK_INDEX To reduce memory usage, gif decoder support pack index when output format is Index mode.
1: enable pack index
0: disable pack index
PACK_INDEX_DEPTH
pack index depth, 1, 2, 4, 8
GIFDEC+0074
Pack width resize
h
31
15
30
29
28
27
14
13
12
11
PACK_RESIZE_W_N [5:0]
R/W
0
26
25
24
23
PACK_RESIZE_W_D
R/W
0
10
9
8
7
22
21
20
19
18
17
16
PACK_RESIZE_W_N [9:6]
R/W
0
6
5
4
3
2
1
0
PACK_RESIZE_W_Q
R/W
0
Re
lea
se
Bit
Name
Type
Reset
Bit
Name
Type
Reset
PACK_RESIZE_
W
When in packing index mode, the resizer is different. The resize width ratio doesn’t need to be an integer. Resize ratio =
PACK_RESIZE_W_Q + (PACK_RESIZE_W_N / PACK_RESIZE_W_D)
GIFDEC+0078
Pack height resize
h
31
15
30
29
28
27
26
25
24
23
PACK_RESIZE_H_D
R/W
0
10
9
8
7
Co
nf
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tia
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Bit
Name
Type
Reset
Bit
Name
Type
Reset
PACK_RESIZE_
H
14
13
12
11
PACK_RESIZE_H_N [5:0]
R/W
0
22
21
20
19
18
17
16
PACK_RESIZE_H_N [9:6]
R/W
0
6
5
4
3
2
1
0
PACK_RESIZE_H_Q
R/W
0
When in packing index mode, the resizer is different. The resize height ratio doesn’t need to be an integer. Resize ratio
= PACK_RESIZE_H_Q + (PACK_RESIZE_H_N / PACK_RESIZE_H_D)
6.13
6.13.1
PNG Decoder
General Description
MT
K
PNG Decoder is aimed to decode PNG pictures. This hardware-assisted png decoding alleviates the software from
computation-intensive jobs, and frees the MCU for other jobs. For a handheld device with multimedia functionality,
this kind of hardware acceleration is very beneficial for MCU off loading and achieving high performance. The PNG
decoder is aimed to do ZLIB decompression, on-the-fly resizing down, clipping and pitching; header parsing is
performed by software.
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Register Definitions
PNGDEC+000
Input File Start Address
0h
Bit
Name
Type
Reset
Bit
Name
Type
Reset
31
30
29
28
27
15
14
13
12
11
INFILE_START_ADDR
26
25
24
23
22
21
INFILE_START_ADDR[31:16]
R/W
0
10
9
8
7
6
5
INFILE_START_ADDR[15:0]
R/W
0
20
19
18
4
3
2
17
16
1
0
fo
r
6.13.2
Revision 1.0
Ko
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MT6228 GSM/GPRS Baseband Processor Data Sheet
Re
lea
se
INFILE_START_ADDR
The input file starting address; PNG decoder would get decompression data from this
address. The address hasn’t to be word aligned.
PNGDEC+000
Input File count
4h
Bit
Name
Type
Reset
Bit
Name
Type
Reset
INFILE_COUNT
31
30
29
28
27
26
15
14
13
12
11
10
25
24
23
22
INFILE_COUNT31:16]
R/W
0
9
8
7
6
INFILE_COUNT15:0]
R/W
0
21
20
19
18
17
16
5
4
3
2
1
0
Co
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tia
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INFILE_COUNT
PNG decoder supports pause-resume mechanism, i.e., png decoder would stop decompressing
when input file is empty, and wait for notice from software. Input file count is assigned for this issue. When png
decoder encounters infile count, it will stop and indicate by interrupt.
PNGDEC+000
Color Table Start Address
8h
Bit
Name
Type
Reset
Bit
Name
Type
Reset
31
30
15
14
CT_START_ADDR
word.
29
28
27
26
13
12
11
10
25
24
23
22
CT_START_ADDR[31:16]
R/W
0
9
8
7
6
CT_START_ADDR [15:0]
R/W
0
CT_START_ADDR
21
20
19
18
17
16
5
4
3
2
1
0
The color table starting address. It needs to be word aligned. And each palette entry is one
PNGDEC+001
Output File Start Address
0h
31
30
29
MT
K
Bit
Name
Type
Reset
Bit
Name
Type
Reset
15
14
13
28
27
12
11
26
25
24
23
22
OUT_START_ADDR[31:16]
R/W
0
10
9
8
7
6
OUT_START_ADDR[15:0]
R/W
0
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OUT_START_ADDR Output file start address. It needs to be word aligned.
PNGDEC+001
Output file End Address
4h
31
30
29
28
27
26
15
14
13
12
11
10
OUT_END_ADDR
OUT_END_ADDR
25
24
23
22
OUT_END_ADDR[31:16]
R/W
0
9
8
7
6
OUT_END_ADDR[15:0]
R/W
0
21
20
19
18
5
4
3
2
Output file end address. It needs to be word aligned.
PNGDEC+001
Huffman HCLEN Table Start Address
8h
31
30
29
28
27
15
14
13
12
11
HCLEN_START_ADDR
26
25
24
23
22
21
HCLEN_START_ADDR[31:16]
R/W
0
10
9
8
7
6
5
HCLEN_START_ADDR[15:0]
R/W
0
30
15
14
0
19
18
17
16
4
3
2
1
0
Huffman code length code table starting address. It needs to be word aligned.
Co
nf
id
en
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31
1
20
PNGDEC+002
Huffman code length Start Address
0h
Bit
Name
Type
Reset
Bit
Name
Type
Reset
16
HCELN_START_ADDR
Re
lea
se
Bit
Name
Type
Reset
Bit
Name
Type
Reset
17
fo
r
Bit
Name
Type
Reset
Bit
Name
Type
Reset
Revision 1.0
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MT6228 GSM/GPRS Baseband Processor Data Sheet
29
28
27
26
13
12
11
10
25
24
23
22
LEN_START_ADDR[31:16]
R/W
0
9
8
7
6
LEN_START_ADDR[15:0]
R/W
0
LEN_START_ADDR
21
20
19
18
17
16
5
4
3
2
1
0
LEN_START_ADDR Huffman code length starting address. It needs to be word aligned.
PNGDEC+002
Huffman HLIT Table Start Address
8h
31
30
15
14
29
28
27
13
12
11
MT
K
Bit
Name
Type
Reset
Bit
Name
Type
Reset
26
25
24
23
22
HLIT_START_ADDR[31:16]
R/W
0
10
9
8
7
6
HLIT_START_ADDR[15:0]
R/W
0
HLIT_START_ADD
R
21
20
19
18
17
16
5
4
3
2
1
0
HLIT_START_ADDE Huffman literal code table starting address. It needs to be word aligned.
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PNGDEC+003
Huffman HDIST Table Start Address
0h
31
30
29
28
27
15
14
13
12
11
HDIST_START_ADD
R
26
25
24
23
22
21
HDIST_START_ADDR[31:16]
R/W
0
10
9
8
7
6
5
20
19
18
4
3
2
HDIST_START_ADDR[15:0]
R/W
0
HDIST_START_ADDR
30
29
28
27
15
14
13
12
11
26
25
24
23
22
21
BUFF0_START_ADDR[31:16]
R/W
0
10
9
8
7
6
5
0
20
19
18
17
16
4
3
2
1
0
BUFF0_START_ADDR[15:0]
R/W
0
Line buffer0 starting address (for de-filtering). It needs to be word aligned.
PNGDEC+004
Line Buffer1 Start Address
0h
30
15
14
29
28
27
BUFF1_START_ADD
R
26
25
24
23
22
21
BUFF1_START_ADDR[31:16]
R/W
0
10
9
8
7
6
5
BUFF1_START_ADDR[15:0]
R/W
0
Co
nf
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tia
l
31
13
BUFF1_START_ADDR
12
11
20
19
18
17
16
4
3
2
1
0
Line buffer1 starting address (for de-filtering). It needs to be word aligned.
PNGDEC+004
LZ77 Buffer Start Address
8h
Bit
Name
Type
Reset
Bit
Name
Type
Reset
1
BUFF0_START_ADD
R
Re
lea
se
31
BUFF0_START_ADDR
Bit
Name
Type
Reset
Bit
Name
Type
Reset
16
Huffman distance code table starting address. It needs to be word aligned.
PNGDEC+003
Line Buffer0 Start Address
8h
Bit
Name
Type
Reset
Bit
Name
Type
Reset
17
fo
r
Bit
Name
Type
Reset
Bit
Name
Type
Reset
Revision 1.0
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MT6228 GSM/GPRS Baseband Processor Data Sheet
31
30
15
14
29
28
27
13
12
11
LZ77_START_ADDR
26
25
24
23
22
21
LZ77_START_ADDR[31:16]
R/W
0
10
9
8
7
6
5
LZ77_START_ADDR[15:0]
R/W
0
20
19
18
17
16
4
3
2
1
0
MT
K
LZ77_START_ADDRLZ77 buffer starting address. It needs to be word aligned.
PNGDEC+005
Color_Type
0h
Bit
Name
31
30
29
28
27
COLOR_TYPE
26
25
24
23
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22
21
20
19
18
17
16
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Type
Reset
Bit
Name
Type
Reset
15
14
13
12
11
10
9
8
7
6
5
4
COLOR_DEPTH[4:0]
R/W
0
PNGDEC+005
IMG_WIDTH_HEIGHT
4h
31
30
29
28
27
26
15
14
13
12
11
10
25
24
23
22
IMG_WIDTH[15:0]
R/W
0
9
8
7
6
IMG_HEIGHT[15:0]
R/W
0
21
20
19
18
17
16
5
4
3
2
1
0
30
15
14
Name
Type
Reset
Co
nf
id
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PNGDEC+005
Decode Control Register
8h
31
0
IMG_WIDTH_HEIGHT
IMG_WIDTH Image width.
IMG_HEIGHT Image height.
Bit
Name
Type
Reset
Bit
1
R/W
0
Re
lea
se
Bit
Name
Type
Reset
Bit
Name
Type
Reset
2
COLOR_TYPE[2:0]
fo
r
COLOR_TYPE Indicate color type of PNG image.
0: greyscale
2: true color
3: palette
4: greyscale with alpha
6: true color with alpha
COLOR_DEPTH Indicate color bit depth of PNG image.
3
Revision 1.0
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MT6228 GSM/GPRS Baseband Processor Data Sheet
DECODE_CTRL
29
28
27
26
25
24
23
22
21
20
19
18
17
13
12
11
10
9
8
7
6
5
4
3
2
1
16
0
DECO
DE_E
N
R/W
0
DECODE_EN Decode enable signal.
PNGDEC+005
Interlace Enable Register
Ch
31
30
15
14
29
28
27
26
25
24
23
22
21
20
19
18
17
13
12
11
10
9
8
7
6
5
4
3
2
1
MT
K
Bit
Name
Type
Reset
Bit
INTERLACE_EN
16
0
INTER
LACE_
EN
Name
Type
Reset
R/W
0
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INTERLACE_EN
Interlace enable signal.
PNGDEC+006
ADLER_ADDR
0h
ALER_ADDR
30
29
28
27
26
25
15
14
13
12
11
10
9
ADLER
24
23
22
ADLER[31:16]
R/W
0
8
7
6
ADLER[15:0]
R/W
0
20
19
18
5
4
3
2
Adler checksum data report.
PNGDEC+006
LCD Width Height Register
8h
Bit
Name
Type
Reset
Bit
Name
Type
Reset
21
31
30
29
28
27
26
25
15
14
13
12
11
10
9
LCD_W
LCD_H
24
23
LCD_W[15:0]
R/W
0
8
7
LCD_H[15:0]
R/W
0
LCD width.
LCD height.
30
15
14
CLIP_X
Co
nf
id
en
tia
l
31
29
28
27
26
25
13
12
11
10
9
24
23
CLIP_X
R/W
0
8
7
CLIP_Y
R/W
0
1
0
22
21
20
19
18
17
16
6
5
4
3
2
1
0
CLIP_XY
22
21
20
19
18
17
16
6
5
4
3
2
1
0
CLIP_X[15] sign bit: 0: positive 1: negative
CLIP_X[14:0] X for clipping window
CLIP_Y[15] sign bit: 0: positive 1: negative
CLIP_Y[14:0] Y for clipping window
CLIP_Y
PNGDEC+007
Clipping window width and height register
0h
31
30
29
MT
K
Bit
Name
Type
Reset
Bit
Name
Type
Reset
16
LCD_WH
PNGDEC+006
Clipping XY
Ch
Bit
Name
Type
Reset
Bit
Name
Type
Reset
17
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31
Re
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Bit
Name
Type
Reset
Bit
Name
Type
Reset
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MT6228 GSM/GPRS Baseband Processor Data Sheet
15
14
13
28
27
26
25
12
11
10
9
24
23
CLIP_W
R/W
0
8
7
CLIP_H
R/W
0
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22
21
20
19
18
17
16
6
5
4
3
2
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MediaTek Inc. Confidential
CLIP_W
CLIP_H
Revision 1.0
Clipping window width
Clipping window height
PNGDEC+007
Image XY
4h
IMG_XY
30
29
28
27
26
25
15
14
13
12
11
10
9
IMG_X
24
23
IMG_X
R/W
0
8
7
IMG_Y
R/W
0
IMG_X[15] sign bit: 0: positive 1: negative
IMG_X[14:0] X for image logic window
IMG_Y[15] sign bit: 0: positive 1: negative
IMG_Y[14:0] Y for image logic window
IMG_Y
PNGDEC+007
PNG Reset
8h
31
30
29
28
27
26
25
24
15
14
13
12
11
10
9
8
RST
21
20
19
18
6
5
4
3
2
Name
Type
Reset
16
1
0
RST
22
21
20
19
18
17
7
6
5
4
3
2
1
16
0
RST
R/W
0
Reset for PNG decoder. Write 0x1201, then hardware will reset itself.
PNGDEC+007
Color Output Format
Ch
Bit
Name
Type
Reset
Bit
17
23
Co
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Bit
Name
Type
Reset
Bit
Name
Type
Reset
22
fo
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31
Re
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Bit
Name
Type
Reset
Bit
Name
Type
Reset
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MT6228 GSM/GPRS Baseband Processor Data Sheet
31
30
15
14
OUT_FORMAT
29
28
27
26
25
24
23
22
21
20
19
18
17
16
13
12
11
10
9
8
7
6
5
4
3
2
1
0
CLIP_ PARTIA
IPP_E
PARTI OUT_FORMA
PITCH L_IRQ_
N
AL
T
_EN CTRL
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
MT
K
OUT_FORMAT Output color format
2’b00: RGB565
2’b01: RGB888
2’b10: ARGB4444
2’b11: ARGB8888
PARTIAL 1: enable partial input
0: disable partial input
PARTIAL_IRQ_CTRL 1: The input file empty irq and block count end irq will be sent out according to which case
is encountered first. If the two cases are encountered at the same time, both irqs will be
sent out.
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MT6228 GSM/GPRS Baseband Processor Data Sheet
0: Both input file empty irq and block count end irq will be sent out if the left byte number of
the input file and block are smaller than 4 bytes.
CLIP_PITCH_EN
Clip end pitch enable
IPP_EN Enable ipp and png interface
PNGDEC+008
Resize Register
0h
31
30
29
28
27
26
25
24
23
22
21
20
15
14
13
12
11
10
9
8
7
6
5
4
RESIZE_W_RATIO
RESIZE_H_RATIO
Type
Reset
R/W
0
R/W
0
RESIZE_EN
18
17
2
1
16
0
RESIZ
E_EN
R/W
0
MT
K
Co
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Resize on the fly enable
0: disable
1: enable
RESIZE_W_RATIO Resize ratio in width
0: no resize
1: ½
2: ¼
3: 1/8
4: 1/16
5: 1/32
6: 1/64
7: 1/128
8: 1/256
9: 1/512
10: 1/1024
11: 1/2048
12: 1/4096
13: 1/8192
14: 1/16384
15: 1/32768
RESIZE_H_RATIO Resize ratio in height
0: no resize
1: ½
2: ¼
3: 1/8
4: 1/16
5: 1/32
6: 1/64
7: 1/128
8: 1/256
9: 1/512
10: 1/1024
11: 1/2048
3
Re
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Name
19
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Bit
Name
Type
Reset
Bit
RESIZE
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12: 1/4096
13: 1/8192
14: 1/16384
15: 1/32768
PNGDEC+008
Resume Register
4h
RESUME
31
30
29
28
27
26
25
24
23
22
21
20
15
14
13
12
11
10
9
8
7
6
5
4
Type
Reset
RESUME
18
17
2
1
16
0
RESU
ME
R/W
0
Resume when infile empty or block count end
PNGDEC+008
Interrupt Enable Register
8h
Bit
Name
Type
Reset
Bit
3
Re
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Name
19
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Bit
Name
Type
Reset
Bit
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MT6228 GSM/GPRS Baseband Processor Data Sheet
31
30
29
28
27
26
25
24
15
14
13
12
11
10
9
8
23
22
7
6
Type
Reset
Co
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Name
21
20
19
IRQ_EN
18
17
16
5
4
3
2
1
0
OVER
COLO
FILTE
_OUT
R_IN BLOC
R_BY
INEM IMG_C
PUT_
DEX_ K_CN
TE_E
PTY MP
ERRO
ERRO T
RROR
R
R
R/W R/W R/W R/W R/W R/W
0
0
0
0
0
0
IMG_CMP
Image decompressed complete irq enable
INEMPTY
Input file empty
BLOCK_CNT Block count end
COLOR_INDEX_ERROR output index error
FILTER_BYTE_ERROR decoder decode an error filter type
OVER_OUTPUT_ERROR output over out_end_addr
PNGDEC+008
Interrupt Status
Ch
Bit
Name
Type
Reset
Bit
31
30
15
14
IRQ_STATUS
29
28
27
26
25
24
23
22
13
12
11
10
9
8
7
6
MT
K
Name
Type
Reset
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21
20
19
18
17
16
5
4
3
2
1
0
OVER
COLO
FILTE
_OUT
R_IN BLOC
R_BY
INRM IMG_C
PUT_
DEX_ K_CN
TE_E
PTY MP
ERRO
ERRO T
RROR
R
R
R
R
R
R
R
R
0
0
0
0
0
0
MediaTek Inc. Confidential
IMG_CMP
Image decompressed complete irq.
INEMPTY
Input file empty irq
BLOCK_CNT Block count end irq
COLOR_INDEX_ERROR output index error
FILTER_BYTE_ERROR decoder decode an error filter type
OVER_OUTPUT_ERROR output over out_end_addr
PNGDEC+009
IDAT COUNT Register
0h
30
29
28
27
26
15
14
13
12
11
10
25
24
23
22
IDAT_COUNT[31:16]
R/W
0
9
8
7
6
IDAT_COUNT[15:0]
R/W
0
IDAT_COUNT The length (byte number) of the IDAT.
PNGDEC+009
Chunk type
4h
31
30
29
28
27
26
25
15
14
13
12
11
10
9
24
23
22
CHUNK_TYPE
R/W
0
8
7
6
CHUNK_TYPE
R/W
0
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Bit
Name
Type
Reset
Bit
Name
Type
Reset
CHUNK_TYPE
21
20
5
4
fo
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31
IDAT_COUNT
19
18
17
16
3
2
1
0
Re
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Bit
Name
Type
Reset
Bit
Name
Type
Reset
Revision 1.0
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MT6228 GSM/GPRS Baseband Processor Data Sheet
CHUNK TYPE
21
20
19
18
17
16
5
4
3
2
1
0
chunk type
PNGDEC+009
CRC
8h
Bit
Name
Type
Reset
Bit
Name
Type
Reset
31
30
15
14
CRC
29
28
27
26
25
13
12
11
10
9
24
23
CRC
R
0
8
7
CRC
R
0
CRC
22
21
20
19
18
17
16
6
5
4
3
2
1
0
read out the crc result
PNGDEC+00A
Transparency table start address
0h
31
30
29
28
27
26
25
15
14
13
12
11
10
9
MT
K
Bit
Name
Type
Reset
Bit
Name
Type
24
23
TRNS_ADDR
R/W
0
8
7
TRNS_ADDR
R/W
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TRNS_ADDR
22
21
20
19
18
17
16
6
5
4
3
2
1
0
MediaTek Inc. Confidential
Reset
0
TRAN_ADDR
transparency table staring address.
PNGDEC+00A
TRNS CTRL
4h
TRNS CTRL
31
30
29
28
27
26
25
24
23
22
21
20
19
18
15
14
13
12
11
10
9
8
7
6
5
4
3
TRAN
S_OU
T_SP
EC
R/W
0
2
Name
Re
lea
se
Type
Reset
TRANS_EN
TRANS_OUT
17
16
1
0
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Bit
Name
Type
Reset
Bit
Revision 1.0
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MT6228 GSM/GPRS Baseband Processor Data Sheet
TRAN TRAN
TRAN
S_TA S_OU
S_EN
BLE
T
R/W
0
R/W
0
R/W
0
Transparent enable
0: output transparent color as background color
1: no output when transparent
TRANS_TABLE
Transparent table exist
TRANS_OUT_SPEC Transparent color key enable
PNGDEC+00A
Transparency key1
8h
31
30
15
14
29
28
27
26
25
24
23
GREY_KEY
R/W
0
8
7
R_KEY
R/W
0
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Bit
Name
Type
Reset
Bit
Name
Type
Reset
13
12
11
10
9
TRNS_KEY1
22
21
20
19
18
17
16
6
5
4
3
2
1
0
GREY_KEY Transparent color key of grayscale image
R_KEY Transparent color key of red component
PNGDEC+00A
Transparency key2
Ch
Bit
Name
Type
Reset
Bit
Name
Type
Reset
31
30
15
14
29
28
27
26
25
13
12
11
10
9
24
23
G_KEY
R/W
0
8
7
B_KEY
R/W
0
TRNS_KEY2
22
21
20
19
18
17
16
6
5
4
3
2
1
0
MT
K
G_KEY Transparent color key of green component
B_KEY Transparent color key of blue component
PNGDEC+00B
Background Color
0h
Bit
31
30
29
28
27
26
BG_COLOR
25
24
23
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21
20
19
18
17
16
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15
BG_GREY
BG_R
BG_G
BG_B
14
13
BG_GREY
R/W
0
12
11
BG_G
R/W
0
10
9
8
7
6
background color of grayscale image
background color of red component
background color of green component
background color of blue component
PNGDEC+00B
SPECIAL BLOCK
4h
31
30
15
14
29
28
27
26
SPEC_BLOCK_BYTE3
R/W
0
13
12
11
10
SPEC_BLOCK_BYTE1
R/W
0
2
1
0
SPEC_BLOCK
25
24
9
8
23
22
7
6
21
20
19
18
SPEC_BLOCK_BYTE2
R/W
0
5
4
3
2
SPEC_BLOCK_BYTE0
R/W
0
Re
lea
se
Bit
Name
Type
Reset
Bit
Name
Type
Reset
5
BG_R
R/W
0
4
3
BG_B
R
0
fo
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Name
Type
Reset
Bit
Name
Type
Reset
Revision 1.0
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MT6228 GSM/GPRS Baseband Processor Data Sheet
17
16
1
0
This register is used for the special case when the length of one IDAT is smaller than or equal to 4 bytes.
SPEC_BLOCK_BYTEx contains the value of byte x of the IDAT.
SPEC_BLOCK_BYTE0 The byte 0 of the IDATSPEC_BLOCK_BYTE1 The byte 1 of the
IDATSPEC_BLOCK_BYTE2 The byte 2 of the IDAT
+00B8h
Bit
31
Name
Type R/W
Reset
0
Bit
15
Name
Type R/W
Reset
0
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SPEC_BLOCK_BYTE3 The byte 3 of the IDAT
INDEX NUMBER
30
INDEX_NUM
29
28
27
26
25
24
23
22
R/W
0
14
R/W
0
13
R/W
0
12
R/W
0
11
R/W
0
10
R/W
0
9
8
7
6
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
21
20
19
COLOR_NUM
R/W
0
5
4
3
TRANS_NUM
R/W
0
18
17
16
2
1
0
MT
K
COLOR_NUM color entry number
TRANS_NUM transparency entry number
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6.14
Camera Interface
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MT6228 GSM/GPRS Baseband Processor Data Sheet
Re
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se
MT6228 incorporates a feature rich image signal processor to connect with a variety of image sensor components. This
processor consists of timing generated unit (TG) and lens/sensor compensation unit and image process unit.
Timing generated unit (TG) cooperates with master type image sensor only. That means sensor should send vertical and
horizontal signals to TG. TG offers sensor required data clock and receive sensor Bayer pattern raw data by internal
auto synchronization or external pixel clock synchronization. The main purpose of TG is to create data clock for master
type image sensor and accept vertical/horizontal synchronization signal and sensor data, and then generate grabbed area
of raw data or YUV422/RGB565 data to the lens/sensor compensation unit.
Lens/sensor compensation unit generates compensated raw data to the color process unit in Bayer raw data input mode.
In YUV422/RGB565 input mode, this stage is bypassed.
6.14.1
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Image process unit accepts Bayer pattern raw data or YUV422/RGB565 data that is generated by lens/sensor
compensation unit. The output of ISP is YCbCr 888 data format which can be easily encoded by the compress engine
(JPEG encoder and MPEG4 encoder). It can be the basic data domain of other data format translation such as R/G/B
domain. The ISP is pipelined, and during processing stages ISP hardware can auto extract meaningful information for
further AE/AF/AWB calculation. These information are temporary stored on ISP registers or memory and can be read
back by MCU.
Register Table
REGISTER ADDRESS REGISTER NAME
CAM + 0000h
SYNONYM
TG Phase Counter Register
CAM_PHSCNT
Image Sensor Size Configuration Register
CAM_CAMWIN
TG Grab Range Start/End Pixel Configuration Register
CAM_GRABCOL
CAM + 000Ch
TG Grab Range Start/End Line Configuration Register
CAM_GRABROW
CAM + 0010h
CMOS Sensor Mode Configuration Register
CAM_CSMODE
Component Offset Adjustment Register
CAM_RGBOFF
View Finder Mode Control Register
CAM_VFCON
CAM + 0004h
CAM + 0008h
CAM + 0014h
CAM + 0018h
Camera Module Interrupt Enable Register
CAM_INTEN
CAM + 0020h
Camera Module Interrupt Status Register
CAM_INTSTA
CAM + 0024h
Camera Module Path Config Register
CAM_PATH
CAM + 0028h
Camera Module Input Address Register
CAM_INADDR
CAM + 002Ch
Camera Module Output Address Register
CAM_OUTADDR
MT
K
CAM + 001Ch
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MT6228 GSM/GPRS Baseband Processor Data Sheet
Preprocessing Control Register 1
CAM_CTRL1
CAM + 0034h
Component R,G, B Gain Control Register 1
CAM_RGBGAIN1
CAM + 0038h
Component R,G, B Gain Control Register 2
CAM_RGBGAIN2
CAM + 003Ch
Histogram Boundary Control Register 1
CAM_HIS0
CAM + 0040h
Histogram Boundary Control Register 2
CAM_HIS1
CAM + 0044h
Preprocessing Control Register 2
CAM_CTRL2
CAM + 0048h
Reserved
Reserved
CAM + 004Ch
Reserved
Reserved
CAM + 0050h
Reserved
CAM + 0054h
Reserved
CAM + 0058h
ATF Window 1 Register
CAM + 005Ch
ATF Window 2 Register
CAM_ AEWIN2
CAM + 0060h
ATF Window 3 Register
CAM_ AEWIN3
fo
r
CAM + 0030h
Reserved
Reserved
Re
lea
se
CAM_AEWIN1
CAM + 0064h
ATF Window 4 Register
CAM + 0068h
ATF Window 5 Register
CAM_ AEWIN4
CAM + 006Ch
AWB Window Register
CAM + 0070h
Color Processing Stage Control Register
CAM_CPSCON1
CAM + 0074h
Interpolation Register 1
CAM_INTER1
CAM + 0078h
Interpolation Register 2
CAM + 007Ch
Edge Core Register
CAM + 0080h
Edge Gain Register 1
CAM + 0084h
Edge Gain Register 2
CAM + 0088h
Edge Threshold Register
CAM_ AEWIN5
CAM_AWBWIN
CAM_INTER2
CAM_EDGCORE
CAM_EDGGAIN1
CAM_EDGGAIN2
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CAM_EDGTHRE
CAM + 008Ch
Edge Vertical Control Register
CAM_EDGVCON
CAM + 0090h
Axis RGB Gain Register
CAM_AXGAIN
CAM + 0094h
OPD Configuration Register
CAM_OPDCFG
OPD Component Parameter Register
CAM_OPDPAR
CAM + 009Ch
Color Matrix 1 Register
CAM_MATRIX1
CAM + 00A0h
Color Matrix 2 Register
CAM_MATRIX2
CAM + 0098h
Color Matrix 3 Register
CAM_MATRIX3
Color Matrix RGB Gain Register
CAM_MTXGAIN
CAM + 00ACh
Color Process Stage Control Register 2
CAM_CPSCON2
CAM + 00B0h
AWB RGB Gain Register
CAM_AWBGAIN
CAM + 00B4h
Gamma RGB Flare Register
CAM_GAMFLRE
CAM + 00B8h
Y Channel Configuration Register
CAM_YCHAN
CAM + 00BCh
UV Channel Configuration Register
CAM_UVCHAN
CAM + 00C0h
Space Convert YUV Register 1
CAM_SCONV1
CAM + 00C4h
Space Convert YUV Register 2
CAM_SCONV2
CAM + 00C8h
Gamma Operation Register 1
CAM_GAMMA1
CAM + 00CCh
Gamma Operation Register 2
CAM_GAMMA2
CAM + 00D0h
Gamma Operation Register 3
CAM_GAMMA3
CAM + 00D4h
OPD Y Result Register
CAM_OPDY
MT
K
CAM + 00A4h
CAM + 00A8h
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MT6228 GSM/GPRS Baseband Processor Data Sheet
OPD MG Result Register
CAM_OPDMG
OPD RB Result Register
CAM_OPDRB
CAM + 00E0h
OPD Pixel Counter Register
CAM_OPDCNT
CAM + 00E4h
Reserved
Reserved
CAM + 00E8h
Reserved
Reserved
CAM + 00ECh
Reserved
Reserved
CAM + 00F0h
Reserved
Reserved
CAM + 00F4h
ATF Result 1 Register
CAM_AE5RLT
CAM + 00F8h
ATF Result 2 Register
CAM + 00FCh
ATF Result 3 Register
CAM + 0100h
ATF Result 4 Register
fo
r
CAM + 00D8h
CAM + 00DCh
CAM + 0104h
ATF Result 5 Register
CAM_AE9RLT
CAM + 0108h
Cam Histogram Result 1
CAM_HISRLT0
CAM + 010Ch
Cam Histogram Result 2
CAM + 0110h
Cam Histogram Result 3
CAM + 0114h
Cam Histogram Result 4
CAM + 0118h
Cam Histogram Result 5
CAM + 011Ch
Low Pass Filter Control Register
CAM + 0120h
Y Low Pass Filter Control Register
CAM + 0124h
CbCr Low Pass Filter Control Register
CAM_CLPF
CAM + 0128h
Vertical Subsample Control Register
CAM_VSUB
CAM + 012Ch
Horizontal Subsample Control Register
CAM_HSUB
CAM + 0130h
Sensor Gamma R0 Register
CAM_SGAMMAR0
CAM + 0138h
CAM_AE7RLT
Re
lea
se
CAM_AE8RLT
CAM_HISRLT1
CAM_HISRLT2
CAM_HISRLT3
CAM_HISRLT4
CAM_LPFCON
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CAM + 0134h
CAM_AE6RLT
CAM_YLPF
Sensor Gamma R1 Register
CAM_SGAMMAR1
Sensor Gamma R2 Register
CAM_SGAMMAR2
CAM + 013Ch
Sensor Gamma G0 Register
CAM_SGAMMAG0
CAM + 0140h
Sensor Gamma G1 Register
CAM_SGAMMAG1
Sensor Gamma G2 Register
CAM_SGAMMAG2
Sensor Gamma B0 Register
CAM_SGAMMAB0
CAM + 0144h
CAM + 0148h
CAM + 014Ch
Sensor Gamma B1 Register
CAM_SGAMMAB1
CAM + 0150h
Sensor Gamma B2 Register
CAM_SGAMMAB2
Defect Pixel Configuration Register
CAM_DEFECT0
Defect Pixel Table Address Register
CAM_DEFECT1
CAM + 015Ch
Defect Pixel Table Debug Register
CAM_DEFECT2
CAM + 0160h
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
CAM + 016Ch
Reserved
Reserved
CAM + 0170h
Reserved
Reserved
CAM + 0174h
Reserved
Reserved
CAM + 0178h
Reserved
Reserved
CAM + 017Ch
Reserved
Reserved
CAM + 0154h
CAM + 0158h
CAM + 0164h
MT
K
CAM + 0168h
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MT6228 GSM/GPRS Baseband Processor Data Sheet
CAM + 0180h
Camera Interface Debug Mode Control Register
CAM + 0184h
Camera Module Debug Information Write Out Destination Address CAM_DSTADDR
CAM_DEBUG
CAM + 0188h
Camera Module Debug Information Last Transfer Destination Address
CAM_LSTADDR
CAM + 018Ch
Camera Module Frame Buffer Transfer Out Count Register
CAM_XFERCNT
CAM + 0190h
CMOS Sensor Test Module Configuration Register 1
CAM_MDLCFG1
CMOS Sensor Test Module Configuration Register 2
CAM_MDLCFG2
Reserved
Reserved
CAM + 019Ch
Reserved
Reserved
CAM + 01A0h
AE Address Register
fo
r
CAM + 0194h
CAM + 0198h
CAM_AEADDR
CAM + 01A4h
AE Window Size Register
CAM + 01A8h
AE Weight 1 Register
CAM + 01ACh
AE Weight 2 Register
CAM_AEWEIGHT1
CAM + 01B0h
AE Weight 3 Register
CAM_AEWEIGHT2
AE Weight 4 Register
AE Weight 5 Register
CAM + 01BCh
AE Weight 6 Register
CAM + 01C0h
AE Weight 7 Register
CAM + 01C4h
AE Weight 8 Register
CAM + 01C8h
AE Area Register
CAM + 01CCh
AutoDefect Control 1 Register
CAM + 01D0h
AutoDefect Control 2 Register
Flash Control Register
Cam Reset Register
CAM_AEWEIGHT3
CAM_AEWEIGHT4
CAM_AEWEIGHT5
CAM_AEWEIGHT6
CAM_AEWEIGHT7
CAM_AEAREA
CAM_AEDEFECT0
CAM_AEDEFECT1
FLASH_CTRL
CAM_RESET
Co
nf
id
en
tia
l
CAM + 01D4h
CAM + 01D8h
Re
lea
se
CAM + 01B4h
CAM + 01B8h
CAM_AESIZE
CAM_AEWEIGHT0
CAM + 01DCh
TG Status Register
TG_STATUS
CAM + 01E0h
Histogram Boundary Control Register 3
CAM_HIS2
CAM + 01E4h
Histogram Boundary Control Register 4
CAM_HIS3
CAM + 01E8h
Histogram Boundary Control Register 5
CAM_HIS4
CAM + 01ECh
Cam Histogram Result 6
CAM_HISRLT5
CAM + 01F0h
Cam Histogram Result 7
CAM_HISRLT6
Cam Histogram Result 8
CAM_HISRLT7
Cam Histogram Result 9
CAM_HISRLT8
CAM + 01FCh
Cam Histogram Result 10
CAM_HISRLT9
CAM + 0200h
Cam Histogram Result 11
CAM_HISRLTA
Cam Histogram Result 12
CAM_HISRLTB
Cam Histogram Result 13
CAM_HISRLTC
CAM + 020Ch
Cam Histogram Result 14
CAM_HISRLTD
CAM + 0210h
Cam Histogram Result 15
CAM_HISRLTE
CAM + 0214h
Shading Control 1 Register
CAM_SHADING1
CAM + 0218h
Shading Control 2 Register
CAM_SHADING2
CAM + 021Ch
Shading R Curve Register 1
CAM_SRCURVE0
CAM + 0220h
Shading R Curve Register 2
CAM_SRCURVE1
CAM + 0224h
Shading R Curve Register 3
CAM_SRCURVE2
CAM + 01F4h
CAM + 01F8h
CAM + 0204h
MT
K
CAM + 0208h
371/616
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MT6228 GSM/GPRS Baseband Processor Data Sheet
Shading G Curve Register 1
CAM_SGCURVE0
Shading G Curve Register 2
CAM_SGCURVE1
CAM + 0230h
Shading G Curve Register 3
CAM_SGCURVE2
CAM + 0234h
Shading B Curve Register 1
CAM_SBCURVE0
CAM + 0238h
Shading B Curve Register 2
CAM_SBCURVE1
CAM + 023Ch
Shading B Curve Register 3
CAM_SBCURVE2
CAM + 0240h
Cam Image-Processor Hue Register 1
CAM_HUE0
CAM + 0244h
Cam Image-Processor Hue Register 2
CAM_HUE1
CAM + 0248h
GMC Debug Register
CAM + 024Ch
Cam Version Register
fo
r
CAM + 0228h
CAM + 022Ch
CAM_GMCDEBUG
CAM_VERSION
6.14.1.1
TG Register Definitions
CAM+0000h
Bit
31
TG Phase Counter Register
30
29
28
CLKE CLKP
N
OL
R/W R/W
0
0
13
12
Name PCEN
Type R/W
Reset
0
Bit
15
14
HVALI PXCL PXCL PXCL
Name
D_EN K_EN K_INV K_IN
PCEN
CLKEN
CLKPOL
CLKCNT
R/W
0
R/W
0
25
CLKCNT
R/W
1
11
10
9
24
8
TGCL
K_SE
L
R/W
0
23
7
22
21
20
19
18
17
CLKRS
CLKFL
R/W
0
R/W
1
6
5
4
3
2
1
PIXCNT
DLATCH
R/W
1
R/W
1
16
0
TG phase counter enable control
Enable sensor master clock (mclk) output to sensor
Sensor master clock polarity control
Sensor master clock frequency divider control.
Sensor master clock will be 52Mhz/CLKCNT, where CLKCNT >=1
Sensor master clock rising edge control
Sensor master clock falling edge control
HVALID input enable
Pixel clock input monitor, used in internal clock synchronization mode
Pixel clock inverse
0
Internal clock synchronization
1
External pixel clock synchronization
Internal clock synchronization example waveform
(CLKCNT=1,CLKRS=0,CLKFL=1,PIXCNT=3,DLATCH=2)
MT
K
CLKRS
CLKFL
HVALID_EN
PXCLK_EN
PXCLK_INV
PXCLK_IN
R/W
0
26
CAM_PHSCNT
Co
nf
id
en
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Type R/W
Reset
0
27
Re
lea
se
Table 52 Camera Interface Register Map
372/616
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MT6228 GSM/GPRS Baseband Processor Data Sheet
52Mhz
ISP output signals
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
3
0
1
2
3
0
1
fo
r
mclk
Sensor output signals
pclk
Bclk
TGCLK_SEL
PIXCNT
DLATCH
0
1
2
3
0
1
2
3
0
1
15
14
29
28
27
26
25
24
23
Co
nf
id
en
tia
l
30
2
1
2
3
13
12
11
10
9
8
7
22
21
PIXELS
R/W
Fffh
6
5
LINES
R/W
Fffh
CAM_CAMWIN
20
19
18
17
16
4
3
2
1
0
Total input pixel number
Total input line number
TG Grab Range Start/End Pixel Configuration
Register
CAM+0008h
31
30
15
14
START
END
29
28
27
26
25
24
23
13
12
11
10
9
8
7
22
21
START
R/W
0
6
5
END
R/W
0
CAM_GRABCO
L
20
19
18
17
16
4
3
2
1
0
MT
K
Grab start pixel number
Grab end pixel number
CAM+000Ch
Bit
3
CMOS Sensor Size Configuration Register
31
PIXEL
LINE
Bit
Name
Type
Reset
Bit
Name
Type
Reset
2
Sensor master based clock selection (0: 52 Mhz, 1: 48 Mhz)
Sensor data latch frequency control, used in internal clock synchronization mode
Sensor data latch position control, used in internal clock synchronization mode
CAM+0004h
Bit
Name
Type
Reset
Bit
Name
Type
Reset
1
Re
lea
se
0
31
30
TG Grab Range Start/End Line Configuration
Register
29
28
27
26
25
24
23
373/616
22
21
CAM_GRABRO
W
20
19
18
17
16
MediaTek Inc. Confidential
15
14
START
END
13
11
10
9
8
3
2
30
29
28
27
26
25
24
15
14
13
12
11
10
9
8
VSPOL
HSPOL
AUTO
EN
23
22
21
1
fo
r
31
Type
Reset
0
CAM_CSMODE
20
19
7
6
5
4
3
VSPO HSPO PWR
RST AUTO
L
L
ON
R/W R/W R/W R/W R/W
0
0
0
0
0
18
17
16
2
1
0
EN
R/W
0
Image sensor VSYNC polarity
Image sensor HSYNC polarity
Auto lock sensor input horizontal pixel numbers enable
Image sensor process counter enable
31
S00
R/W
0
15
S10
R/W
0
Component R,Gr,B,Gb Offset Adjustment Register
30
14
S00
OFFSET00
S01
OFFSET01
S10
OFFSET10
S11
OFFSET11
13
27
26
OFFSET00
R/W
0
12
11
10
OFFSET10
R/W
0
25
24
23
S01
R/W
0
7
S11
R/W
0
9
8
22
21
6
5
20
19
18
OFFSET01
R/W
0
4
3
2
OFFSET11
R/W
0
30
View Finder Mode Control Register
29
MT
K
15
28
CAM_RGBOFF
17
16
1
0
Sign of raw data (0,0) offset adjustment control, 0 : positive 1: negative
Raw data (0,0) offset adjustment
Sign of raw data (0,1) offset adjustment control, 0 : positive 1: negative
Raw data (0,1) offset adjustment
Sign of raw data (1,0) offset adjustment control, 0 : positive 1: negative
Raw data (1,0) offset adjustment
Sign of raw data (1,1) offset adjustment control, 0 : positive 1: negative
Raw data (1,1) offset adjustment
CAM+0018h
31
29
Co
nf
id
en
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CAM+0014h
Bit
Name
Type
Reset
Bit
4
CMOS Sensor Mode Configuration Register
Name
Bit
Name
Type
Reset
Bit
Name
Type
Reset
7
Grab start line number
Grab end line number
CAM+0010h
Bit
Name
Type
Reset
Bit
12
START
R/W
0
6
5
END
R/W
0
Re
lea
se
Name
Type
Reset
Bit
Name
Type
Reset
Revision 1.0
Ko
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MT6228 GSM/GPRS Baseband Processor Data Sheet
14
13
28
27
26
25
24
12
11
10
9
8
Name
SP_DELAY
Type
Reset
R/W
0
23
CAM_VFCON
22
7
6
SP_M TAKE
ODE _PIC
R/W R/W
0
0
374/616
21
20
19
18
17
16
5
4
3
2
1
0
FR_CON
R/W
0
MediaTek Inc. Confidential
SP_DELAY
SP_MODE
TAKE_PIC
FR_CON
000
001
010
011
100
101
110
111
Bit
31
Camera Module Interrupt Enable Register
30
29
28
27
26
25
Name
Type
Reset
Bit
15
14
13
12
11
10
9
24
VSYN
C_INT
_EN
R/W
0
8
Name
Type
Reset
CAM+0020h
Bit
Name
Type
Reset
Bit
31
30
15
14
Name
Type
Reset
23
22
21
20
19
18
17
16
TG_INT_LINENO
R/W
ff
7
2
1
0
GMC
TG_IN ATF_I AEDO ISPD
REZO EXPD
IDLE OVRU
T
NT
NE ONE
VRUN O
N
R/W R/W R/W R/W R/W R/W R/W R/W
0
0
0
0
0
0
0
0
6
5
4
3
Vsync interrupt enable, tg_int will become vsync interrupt when it is enable
TG interrupt line number
TG interrupt
AE done interrupt enable control
ISP done interrupt enable control
Returning idle state interrupt enable control
GMC port over run interrupt enable control
Resizer over run interrupt enable control
Exposure done interrupt enable control
Co
nf
id
en
tia
l
VSYNC_INT_EN
TG_INT_LINENO
TG_INT
AEDONE
ISPDONE
LDLE
GMCOVRUN
REZOVRUN
EXPDO
CAM_INTEN
Re
lea
se
CAM+001Ch
fo
r
Still Picture Mode delay
Still Picture Mode
Take Picture Request
Frame Sampling Rate Control
Every frame is sampled
One frame is sampled every 2 frames
One frame is sampled every 3 frames
One frame is sampled every 4 frames
One frame is sampled every 5 frames
One frame is sampled every 6 frames
One frame is sampled every 7 frames
One frame is sampled every 8 frames
Revision 1.0
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a
MT6228 GSM/GPRS Baseband Processor Data Sheet
Camera Module Interrupt Status Register
CAM_INTSTA
29
28
27
26
25
24
23
22
21
20
19
13
12
11
10
9
8
7
6
5
4
3
18
17
16
2
1
0
GMC
TG_IN ATF_I AEDO ISPD
REZO EXPD
IDLE OVRU
T
NT
NE ONE
VRUN O
N
R
R
R
R
R
R
R
R
0
0
0
0
0
0
0
0
MT
K
Interrupt Status corresponding with 0x1c CAM_INTEN
CAM+0024h
Bit
31
30
Camera Module Path Config Register
29
28
27
26
25
24
23
375/616
22
CAM_PATH
21
20
19
18
17
16
MediaTek Inc. Confidential
CNTO
CNTMODE
N
Type R/W
Reset
0
Bit
15
Name
Type
Reset
WRITE_LEVEL
R/W
0
14
13
R/W
7
10
12
11
INDA
SWAP
SWAP
TA_F
_CBC
_Y
ORM
R
AT
R/W R/W R/W R/W
0
0
0
0 0
9
8
INTYPE_SEL
R/W
REZ_ REZ_
OUTP
OUTPATH_T BURSTW_TYPE[2:
DISC LPF_
ATH_
YPE
0]
ONN OFF
EN
RW
RW
R/W
R/W
R/W
0
0
0
0
0
7
6
5
4
3
2
1
0
INPAT
INPA
H_TH
INPATH_RATE
TH_S
ROTE
EL
N
R/W
R/W R/W
0
0
0
fo
r
Name
Revision 1.0
Ko
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MT6228 GSM/GPRS Baseband Processor Data Sheet
CNTON
CNTMODE
Co
nf
id
en
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Re
lea
se
Enable Debug Mode Data Transfer Counter
Data Transfer Count Selection
00 sRGB count
01 YCbCr count
REZ_DISCONN
Resizer disconnect enable
REZ_LPF_OFF
Resizer low-Pass disable
WRITE_LEVEL
Write FIFO threshold level
Outpath Type Select
OUTPATH_TYPE
00 Bayer Format
01 ISP output
02 RGB888 Format
03 RGB565 Format
BURSTW_TYPE
Burst write type selecttion
000 Single
001 2 Beat
011 4 Beat
101 8 Beat
111 16 Beat
OUTPATH_EN
Enable Output to Memory
SWAP_Y
YCbCr in Swap Y
SWAP_CBCR
YCbCr in Swap Cb Cr
INDATA_FORMAT Sensor Input Data connection
INTYPE_SEL
Input type selection
000 Bayer Format
001 YUV422 Format
101 YCbCr422 Format
010 RGB Format
INPATH_RATE
Input type rate control
INPATH_THROTEN Input path throttle enable
INPATH_SEL
Input path selection
0
Sensor input
1
From memory
Camera Module Input Address Register
MT
K
CAM+0028h
Bit
Name
Type
Reset
Bit
31
30
29
28
27
26
15
14
13
12
11
10
25
24
23
22
CAM_INADDR[31:16]
R/W
0
9
8
7
6
376/616
CAM_INADDR
21
20
19
18
17
16
5
4
3
2
1
0
MediaTek Inc. Confidential
Name
Type
Reset
Revision 1.0
CAM_INADDR[15:0]
R/W
0
CAM_INADDR Input memory address
31
30
29
28
27
26
15
14
13
12
11
10
CAM_OUTADDR
6.14.1.2
31
Output memory address
21
20
5
4
19
18
17
3
2
1
16
0
Color Process Register Definition
CAM+0030h
Bit
Name
Type
Reset
Bit
25
24
23
22
CAM_OUTADDR[31:16]
R/W
0
9
8
7
6
CAM_OUTADDR[15:0]
R/W
0
fo
r
Bit
Name
Type
Reset
Bit
Name
Type
Reset
CAM_OUTADD
R
Camera Module Output Address Register
Re
lea
se
CAM+002Ch
Ko
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MT6228 GSM/GPRS Baseband Processor Data Sheet
Preprocessing Control Register 1
30
14
PGAI
BYPP N_SC
Name
G OUNT
_EN
Type R/W R/W
Reset
0
0
13
28
27
GAIN_COMP
R/W
0
12
11
26
25
24
10
9
8
PIXELID
23
22
21
7
6
5
PGAIN_INT
R/W
0
20
19
P_LIMIT
R/W
0
4
3
18
17
16
2
1
0
PGAIN_FRAC
Co
nf
id
en
tia
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15
29
CAM_CTRL1
R/W
1
R/W
0
GAIN_COMP
Gain Compensation Control
Interpolation Limitation Control
P_LIMIT
BYPPG
Bypass pre-gain operating enable
PGAIN_SCOUNT_EN
Pre-gain saturation count
PIXELID
Bayer pixel type of the first pixel
00
R pixel
01
Gr pixel
10 Gb pixel
11 B pixel
PGAIN_INT
Pre-gain multiplier integer part
PGAIN_FRAC
Pre-gain multiplier fraction part
CAM+0034h
31
30
29
MT
K
Bit
Name
Type
Reset
Bit
Name
Type
15
14
CAM_RGBGAIN
1
Component R,G,B Gain Control Register 1
13
28
27
26
25
24
23
22
12
11
10
9
8
7
6
377/616
21
20
19
B_GAIN
R/W
80h
5
4
3
GB_GAIN
R/W
18
17
16
2
1
0
MediaTek Inc. Confidential
Reset
80h
B_GAIN
GB_GAIN
B Gain
GB Gain
30
29
28
27
26
25
24
23
22
15
14
13
12
11
10
9
8
7
6
R Gain
GR Gain
CAM+003Ch
31
30
29
15
14
13
H1_BND
H2_BND
H3_BND
H4_BND
30
15
14
26
25
24
10
9
8
29
13
28
27
H5_BND
R/W
80h
12
11
2
23
22
21
7
6
5
1
16
0
CAM_HIS0
20
19
H2_BND
R/W
20h
4
3
H4_BND
R/W
40H
18
17
16
2
1
0
CAM_HIS1
26
25
24
23
22
21
20
19
18
17
16
10
9
8
7
6
5
4
3
2
1
0
30
Preprocessing Control Register 2
29
28
27
26
12
11
AWB
ALL
R/W
10
25
24
Name
MT
K
Type
Reset
Bit
17
Histogram level 4 up boundary value
CAM+0044h
31
18
Histogram Boundary Control Register2
31
H5_BND
Bit
28
27
H1_BND
R/W
10h
12
11
H3_BND
R/W
30h
Histogram level 0 up boundary value
Histogram level 1 up boundary value
Histogram level 2 up boundary value
Histogram level 3 up boundary value
CAM+0040h
Bit
Name
Type
Reset
Bit
Name
Type
Reset
20
19
R_GAIN
R/W
80h
5
4
3
GR_GAIN
R/W
80h
Histogram Boundary Control Register1
Co
nf
id
en
tia
l
Bit
Name
Type
Reset
Bit
Name
Type
Reset
21
Re
lea
se
31
R_GAIN
GR_GAIN
CAM_RGBGAIN
2
Component R,G,B Gain Control Register 2
fo
r
CAM+0038h
Bit
Name
Type
Reset
Bit
Name
Type
Reset
Revision 1.0
Ko
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a
MT6228 GSM/GPRS Baseband Processor Data Sheet
15
14
ATFE ATFA
Name
DGEN LL
Type R/W R/W
13
9
8
GONL
RLEN
Y
R/W R/W
23
CAM_CTRL2
21
20
19
18
17
16
AEPI AEGI
AEAL CNTE
CNTC
AESE
D_PO D_PO
AEGMSEL
L
N
LR
L
L
L
R/W R/W R/W R/W R/W
R/W
R/W
0
1
0
0
0
0
0
1
7
6
5
4
3
2
1
0
378/616
22
INTEN
R/W
MediaTek Inc. Confidential
0
AEALL
CNTEN
CNTCLR
AEPID_POL
AEGID_POL
AEGMSEL
00
01
10
11
AESEL
ATFEDGEN
ATFALL
AWBALL
GONLY
RLEN
INTEN
29
15
14
13
30
15
14
25
24
10
9
8
23
22
21
7
6
5
20
19
RIGHT
R/W
0
4
3
BOTTOM
R/W
0
ATF Window 2 Register
29
13
MT
K
31
26
18
17
16
2
1
0
28
27
LEFT
R/W
0
12
11
TOP
R/W
0
CAM_ATFWIN1
26
25
24
23
22
21
10
9
8
7
6
5
24
23
22
21
20
19
RIGHT
R/W
0
4
3
BOTTOM
R/W
0
18
17
16
2
1
0
ATF 2th window left side
ATF 2th window right side
ATF 2th window top side
ATF 2th window bottom side
CAM+0060h
Bit
28
27
LEFT
R/W
0
12
11
TOP
R/W
0
CAM_ATFWIN0
ATF 1th window left side
ATF 1th window right side
ATF 1th window top side
ATF 1th window bottom side
31
LEFT
RIGHT
TOP
BOTTOM
0
fo
r
30
CAM+005Ch
Bit
Name
Type
Reset
Bit
Name
Type
Reset
0
ATF Window 1 Register
31
LEFT
RIGHT
TOP
BOTTOM
0
AE full frame single window enable
AE counter enable
AE count clear enable
Polarity of the pixel identifier swapped for AE operating
Polarity of the line identifier swapped for AE operating
AE gamma curve selection
use gamma curve 0
use gamma curve 1
use gamma curve 2
use gamma curve 3
AE path select
ATG Edge Enable Control
ATF area all control
AWB full frame single window enable
Use G component only for AE
Histogram polarity select enable. AELID_POL,AEPID_POL decide the pixel type
Interpolation FIFO enable
CAM+0058h
Bit
Name
Type
Reset
Bit
Name
Type
Reset
1
Re
lea
se
1
Co
nf
id
en
tia
l
Reset
Revision 1.0
Ko
nk
a
MT6228 GSM/GPRS Baseband Processor Data Sheet
30
ATF Window 3 Register
29
28
27
26
25
CAM_ATFWIN2
379/616
20
19
18
17
16
MediaTek Inc. Confidential
30
29
15
14
13
31
30
15
14
LEFT
RIGHT
TOP
BOTTOM
6
5
28
27
LEFT
R/W
0
12
11
TOP
R/W
0
23
22
21
29
28
27
LEFT
R/W
0
12
11
TOP
R/W
0
25
24
10
9
8
26
25
13
10
9
2
1
0
CAM_ATFWIN3
26
ATF Window 5 Register
20
19
RIGHT
R/W
0
4
3
BOTTOM
R/W
0
7
6
5
18
17
16
2
1
0
CAM_ATFWIN4
24
23
8
7
22
21
6
5
20
19
RIGHT
R/W
0
4
3
BOTTOM
R/W
0
31
30
15
14
AWB Window Register
29
13
MT
K
LEFT
RIGHT
TOP
7
18
17
16
2
1
0
ATF 5th window left side
ATF 5th window right side
ATF 5th window top side
ATF 5th window bottom side
CAM+006Ch
Bit
Name
Type
Reset
Bit
Name
Type
Reset
8
ATF 4th window left side
ATF 4th window right side
ATF 4th window top side
ATF 4th window bottom side
CAM+0068h
Bit
Name
Type
Reset
Bit
Name
Type
Reset
9
ATF Window 4 Register
31
LEFT
RIGHT
TOP
BOTTOM
10
ATF 3th window left side
ATF 3th window right side
ATF 3th window top side
ATF 3th window bottom side
CAM+0064h
Bit
Name
Type
Reset
Bit
Name
Type
Reset
13
fo
r
LEFT
RIGHT
TOP
BOTTOM
14
RIGHT
R/W
0
4
3
BOTTOM
R/W
0
Re
lea
se
15
LEFT
R/W
0
12
11
TOP
R/W
0
Co
nf
id
en
tia
l
Name
Type
Reset
Bit
Name
Type
Reset
Revision 1.0
Ko
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MT6228 GSM/GPRS Baseband Processor Data Sheet
28
27
LEFT
R/W
0
12
11
TOP
R/W
0
CAM_AWBWIN
26
25
24
23
22
21
10
9
8
7
6
5
20
19
RIGHT
R/W
0
4
3
BOTTOM
R/W
0
18
17
16
2
1
0
AWB window left side
AWB window right side
AWB window top side
380/616
MediaTek Inc. Confidential
BOTTOM
AWB window bottom side
CAM+0070h
Color Processing Stage Control Register
30
29
28
27
26
25
24
23
22
21
20
15
14
13
12
11
10
9
8
7
BYPI
NT
R/W
0
6
5
4
Type
Reset
BYPINT
NONLIN
GAVG
LEDGEN
DISLJ
Interpolation first 4 invalid output pixel used enable
Nonlinear mode enable in color correction operation
G channel average mode
Line edge enable
Disable line judge enable
CAM+0074h
Interpolation Register1
31
30
29
28
15
14
13
12
THRE_V
THRE_SM
THRE_DHV
THRE_RT
25
24
9
8
18
17
16
3
2
1
0
NONL
LEDG
GAVG
DISLJ
IN
EN
R/W R/W R/W R/W
0
0
1
0
23
22
21
20
7
6
5
4
CAM_INTER1
19
18
17
THRE_SM
R/W
05h
3
2
1
THRE_RT
R/W
10h
16
0
31
30
15
14
Co
nf
id
en
tia
l
Interpolation parameter
Interpolation parameter
Interpolation parameter
Interpolation parameter
CAM+0078h
Bit
Name
Type
Reset
Bit
Name
Type
Reset
27
26
THRE_V
R/W
0Ah
11
10
THRE_DHV
R/W
19h
19
fo
r
31
Name
Bit
Name
Type
Reset
Bit
Name
Type
Reset
CAM_CPSCON1
Re
lea
se
Bit
Name
Type
Reset
Bit
Revision 1.0
Ko
nk
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MT6228 GSM/GPRS Baseband Processor Data Sheet
Interpolation Register 2
CAM_INTER2
29
28
27
26
25
24
23
22
21
20
19
18
17
16
13
12
11
10
9
8
7
6
5
4
3
2
THRE_LEDGE
R/W
14h
1
0
THRE_LEDGE Interpolation parameter
CAM+007Ch
Bit
31
30
29
28
Name
Name
27
26
25
24
COREH
MT
K
Type
Reset
Bit
15
14
CAM_EDGCOR
E
Edge Core Register
13
12
R/W
08h
11
10
9
COREV
8
23
22
EMBO EMBO
SS1 SS2
R/W R/W
0
0
7
6
TOP_
SLOP
E
381/616
21
20
19
18
17
16
1
0
COREH2
R/W
1Fh
5
4
3
2
CORE_CON
MediaTek Inc. Confidential
Type
Reset
R/W
8h
COREH
EMBOSS1
EMBOSS2
COREH2
COREV
TOP_SLOPE
CORE_CON
30
29
28
SPECIPONL
Name SPECIGAIN
Y
Type
R/W
R/W
Reset
0
0
Bit
15
14
13
12
27
26
25
R/W
1
11
10
9
EGAIN_VB
Type
Reset
R/W
3
30
15
14
Type
Reset
22
21
20
19
29
28
27
26
25
24
13
12
11
10
9
8
18
6
5
4
3
23
17
16
EGAIN_H2
R/W
3
2
1
KNEESEL
EGAINLILNE
R/W
3
R/W
2
0
CAM_EDGGAIN
2
22
7
6
SPEC SPEC
IABS IINV
R/W R/W
0
0
21
20
19
18
17
16
5
4
3
2
1
0
EGAIN_HC
R/W
Fh
MT
K
Edge special absolute enable
Edge special invert enable
Edge gain Hc
CAM+0088h
31
7
OILE
N
R/W
0
Co
nf
id
en
tia
l
31
SPECIABS
SPECIINV
EGAIN_HC
23
Edge Gain Register 2
Name
Bit
Name
Type
8
Edge special gain value
Edge special p only value
Edge gain H value
Edge gain H2 value
Edge gain Vb value
Oil effect enable
Knee select
Edge gain line value
CAM+0084h
Bit
Name
Type
Reset
Bit
24
EGAIN_H
Name
SPECIGAIN
SPECIPONLY
EGAIN_H
EGAIN_H2
EGAIN_VB
OILEN
KNEESEL
EGAINLINE
fo
r
CAM_EDGGAIN
1
Edge Gain Register 1
Re
lea
se
31
R/W
14h
Edge parameter
Emboss effect mode 1 enable
Emboss effect mode 2 enable
Edge parameter
[3:2] Negative Slope [1:0] Positive Slope
Edge parameter
Edge parameter
CAM+0080h
Bit
R/W
0
Revision 1.0
Ko
nk
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MT6228 GSM/GPRS Baseband Processor Data Sheet
30
CAM_EDGTHR
E
Edge Threshold Register
29
28
27
ETH3
R/W
26
25
24
23
382/616
22
21
20
19
ETH_CON
R/W
18
17
16
MediaTek Inc. Confidential
32h
14
13
ETH3
ETH_CON
ONLYC
THRE_EDGE_SUP
THRL_EDGE_SUP
CAM+008Ch
14
13
8
31
30
15
14
CAM+0094h
7
6
5
4
2
THRL_EDGE_SUP
R/W
07h
R/W
07h
28
27
26
E_TH1_V
R/W
18h
12
11
10
SUP_V
R/W
0
25
24
9
8
SDN_V
R/W
2
1
0
CAM_EDGVCO
N
23
22
21
7
6
5
20
19
18
HALF_V
R/W
1Fh
4
3
2
E_TH3_V
R/W
32h
Axis RGB Gain Register
17
16
1
0
CAM_AXGAIN
29
28
27
26
25
24
23
22
21
20
13
12
11
10
G_GAIN
R/W
3Fh
9
8
7
6
5
4
23
22
21
20
19
18
R_GAIN
R/W
3Fh
3
2
B_GAIN
R/W
3Fh
17
16
1
0
Axis R component gain
Axis G component gain
Axis B component gain
AWB Configuration Register
29
28
27
26
25
24
CAM_OPDCFG
19
SUPSEL
MT
K
31
30
OPDE OPDC
Name
N
LR
Type R/W R/W
Reset
1
0
Bit
15
14
Name
Type
Reset
3
THRE_EDGE_SUP
Edge high pass enable
Edge parameter
Edge parameter
Edge parameter
Edge parameter
Edge parameter
R_GAIN
G_GAIN
B_GAIN
Bit
9
Edge Vertical Control Register
29
CAM+0090h
Bit
Name
Type
Reset
Bit
Name
Type
Reset
10
Edge threshold value
Edge parameter
Edge enhanced C component only enable
Edge parameter
Edge parameter
30
HPEN
E_TH1_V
HALF_V
SUP_V
SDN_V
E_TH3_V
80h
11
Co
nf
id
en
tia
l
Bit
31
Name HPEN
Type R/W
Reset
0
Bit
15
Name
Type
Reset
12
fo
r
15
ONLY
Name
C
Type R/W
Reset
0
Re
lea
se
Reset
Bit
Revision 1.0
Ko
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a
MT6228 GSM/GPRS Baseband Processor Data Sheet
13
12
11
10
V_GAIN
R/W
1Fh
R/W
3
9
8
7
383/616
18
17
16
U_GAIN
6
5
4
3
R/W
1Fh
2
1
Y_LIMIT
R/W
3
0
MediaTek Inc. Confidential
OPDEN
OPDCLR
SUPSEL
U_GAIN
V_GAIN
Y_LIMIT
AWB counter enable
AWB counter clear enable
AWB accumulated maximum value setting. Equation is (192 + 8 * SUPSEL).
AWB U gain value
AWB V gain value
AWB white point minimum value,
OPD Component Parameter Register
30
29
15
14
13
S_RB_P
S_RB_N
S_MG_P
S_MG_N
31
30
29
24
23
22
21
9
8
7
6
5
27
26
25
20
19
18
S_RB_N
R/W
7Fh
4
3
2
S_MG_N
R/W
7Fh
17
16
1
0
CAM_MATRIX1
24
23
22
21
20
19
18
17
16
3
2
1
0
M11
R/W
20h
15
14
13
12
11
10
9
8
7
6
5
4
Co
nf
id
en
tia
l
M12
R/W
80h
M13
R/W
80h
Color matrix 11 value
Color matrix 12 value
Color matrix 13 value
CAM+00A0h
31
15
Color Matrix 2 Register
30
14
29
13
28
27
12
11
26
10
25
9
24
8
23
7
CAM_MATRIX2
22
21
20
19
18
17
16
3
2
1
0
M21
R/W
80h
6
5
4
M22
R/W
20h
M21
M22
M23
M23
R/W
80h
Color matrix 21 value
Color matrix 22 value
Color matrix 23 value
Color Matrix 3 Register
MT
K
CAM+00A4h
Bit
Name
Type
Reset
Bit
28
CAM_OPDPAR
25
Color Matrix 1 Register
M11
M12
M13
Bit
Name
Type
Reset
Bit
Name
Type
Reset
27
26
S_RB_P
R/W
7Fh
12
11
10
S_MG_P
R/W
7Fh
AWB SR Bp value
AWB SR Bn value
AWB SM Gp value
AWB SN Gn value
CAM+009Ch
Bit
Name
Type
Reset
Bit
Name
Type
Reset
28
fo
r
31
Re
lea
se
CAM+0098h
Bit
Name
Type
Reset
Bit
Name
Type
Reset
Revision 1.0
Ko
nk
a
MT6228 GSM/GPRS Baseband Processor Data Sheet
31
15
30
14
29
13
28
27
26
25
CAM_MATRIX3
24
23
22
21
20
19
18
17
16
3
2
1
0
M31
R/W
80h
12
11
10
9
8
7
384/616
6
5
4
MediaTek Inc. Confidential
Name
Type
Reset
M32
R/W
80h
M31
M32
M33
Color Matrix RGB Gain Register
28
27
26
25
24
23
22
21
20
15
14
13
12
11
10
G_GAIN
R/W
20h
9
8
7
6
5
4
Color matrix R component gain value
Color matrix G component gain value
Color matrix B component gain value
Color Process Stage Control Register 2
31
30
29
28
27
26
25
24
15
14
13
12
11
10
9
8
BYPGM
RGBEDGAINEN
YEDGEN
OPDGM_IVT
Y_EGAIN
CAM+00B0h
31
30
15
14
22
17
16
1
0
CAM_CPSCON2
21
20
7
6
5
4
BYPG RGBE YEDG OPRG
M DGEN EN M_IVT
R/W R/W R/W R/W
1
0
0
0
19
18
17
16
3
2
1
0
Y_EGAIN
R/W
2
Bypass gamma enable
Edge enhance before gamma
Edge enhance after gamma
Gamma output inverse mode enable
Y channel edge gain value
CAM_AWBGAI
N
AWB RGB Gain Register
29
13
28
27
12
11
AWB_GGAIN
R/W
80h
26
25
24
23
22
21
10
9
8
7
6
5
20
19
AWB_RGAIN
R/W
80h
4
3
AWB_BGAIN
R/W
80h
18
17
16
2
1
0
AWB R component gain value
AWB G component gain value
AWB B component gain value
MT
K
AWB_RGAIN
AWB_GGAIN
AWB_BGAIN
23
Co
nf
id
en
tia
l
Name
Type
Reset
19
18
R_GAIN
R/W
20h
3
2
B_GAIN
R/W
20h
fo
r
29
Re
lea
se
30
CAM+00ACh
Bit
Name
Type
Reset
Bit
Name
Type
Reset
CAM_MTXGAIN
31
R_GAIN
G_GAIN
B_GAIN
Bit
Name
Type
Reset
Bit
M33
R/W
20h
Color matrix 31 value
Color matrix 32 value
Color matrix 33 value
CAM+00A8h
Bit
Name
Type
Reset
Bit
Name
Type
Reset
Revision 1.0
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MT6228 GSM/GPRS Baseband Processor Data Sheet
385/616
MediaTek Inc. Confidential
31
30
29
28
27
26
25
24
Name
Type
Reset
Bit
15
SIGN_
Name
G
Type R/W
Reset
0
14
13
29
28
27
26
25
24
14
13
12
11
10
9
8
21
20
19
18
FLARE_R
R/W
0
6
5
4
3
2
23
22
21
7
6
5
13
U11
V11
SIGN_U_OFFSET
U_OFFSET
0
17
16
1
0
UV_L
P_EN
CSUP_EDGE_GAIN
R/W
0
R/W
10h
Y channel contrast gain value
Sign bit of Y channel brightness offset value
Y channel brightness offset value
UV channel low pass enable
Chroma suppression edge gain value
28
27
26
25
24
23
CAM_UVCHAN
22
21
20
U11
R/W
20h
14
1
CAM_YCHAN
20
19
18
CONTRAST_GAIN
R/W
40h
4
3
2
UV Channel Configuration Register
29
16
R/W
0
R/W
0
30
17
FLARE_B
BRIGHT_OFFSET
MT
K
15
SIGN_
Name U_OF
FSET
Type R/W
Reset
0
22
Y Channel Configuration Register
30
CAM+00BCh
31
8
R flare sign
R flare
G flare sign
G flare
R flare sign
G flare
CONTRAST_GAIN
SIGN_BRIGHT_OFFSET
BRIGHT_OFFSET
UV_LP_EN
CSUP_EDGE_GAIN
Bit
Name
Type
Reset
Bit
9
Co
nf
id
en
tia
l
15
SIGN_
BRIG
Name HT_O
FFSE
T
Type R/W
Reset
1
10
R/W
0
CAM+00B8h
31
11
FLAIRE_G
SIGN_R
FLARE_R
SIGN_G
FLARE_G
SIGN_B
FLARE_B
Bit
Name
Type
Reset
Bit
12
23
SIGN
_R
R/W
0
7
SIGN
_B
R/W
0
fo
r
Bit
CAM_GAMFLR
E
Gamma RGB Flare Register
Re
lea
se
CAM+00B4h
Revision 1.0
Ko
nk
a
MT6228 GSM/GPRS Baseband Processor Data Sheet
12
11
U_OFFSET
R/W
0
10
9
8
7
SIGN_
V_OF
FSET
R/W
0
19
18
17
16
3
2
1
0
V22
R/W
20h
6
5
4
V_OFFSET
R/W
0
Hue U channel operating value
Hue V channel operating value
Sign bit of Hue U channel offset value
Hue U channel offset value
386/616
MediaTek Inc. Confidential
SIGN_V_OFFSET
V_OFFSET
CAM+00C0h
28
27
26
25
24
23
22
21
15
14
13
12
11
U_GAIN
R/W
91h
10
9
8
7
6
5
30
29
15
14
13
15
14
GAMMA_B1
GAMMA_B2
GAMMA_B3
GAMMA_B4
GAMMA_B5
12
11
U_OFFSET
R/W
80h
26
25
24
10
9
8
29
13
28
27
GAMMA_B1
R/W
32h
12
11
GAMMA_B3
R/W
65h
16
1
0
CAM_SCONV2
23
22
21
7
6
5
Gamma Operation Register 1
30
20
19
Y_OFFSET
R/W
01h
4
3
V_OFFSET
R/W
80h
18
17
16
2
1
0
CAM_GAMMA1
26
25
24
23
22
21
10
9
8
7
6
5
Gamma Operation Register 2
29
MT
K
15
27
17
20
19
GAMMA_B2
R/W
50h
4
3
GAMMA_B4
R/W
76h
18
17
16
2
1
0
Gamma operating B1 value
Gamma operating B2 value
Gamma operating B3 value
Gamma operating B4 value
CAM+00CCh
31
28
Space Convert Y channel offset value
Space Convert U channel offset value
Space Convert V channel offset value
30
2
Space Convert YUV Register 2
31
31
18
Re
lea
se
Space Convert Y channel gain value
Space Convert U channel gain value
Space Convert V channel gain value
CAM+00C8h
20
19
Y_GAIN
R/W
FFh
4
3
V_GAIN
R/W
B8h
fo
r
29
Y_OFFSET
U_OFFSET
V_OFFSET
Bit
Name
Type
Reset
Bit
Name
Type
Reset
CAM_SCONV1
30
CAM+00C4h
Bit
Name
Type
Reset
Bit
Name
Type
Reset
Space Convert YUV Register 1
31
Y_GAIN
U_GAIN
V_GAIN
Bit
Name
Type
Reset
Bit
Name
Type
Reset
Sign bit of Hue V channel offset value
Hue V channel offset value
Co
nf
id
en
tia
l
Bit
Name
Type
Reset
Bit
Name
Type
Reset
Revision 1.0
Ko
nk
a
MT6228 GSM/GPRS Baseband Processor Data Sheet
14
13
28
27
GAMMA_B5
R/W
94h
12
11
GAMMA_B7
R/W
C5h
CAM_GAMMA2
26
25
24
23
22
21
10
9
8
7
6
5
20
19
GAMMA_B6
R/W
Aeh
4
3
GAMMA_B8
R/W
Dah
18
17
16
2
1
0
Gamma operating B5 value
387/616
MediaTek Inc. Confidential
GAMMA_B6
GAMMA_B7
GAMMA_B8
Gamma operating B6 value
Gamma operating B7 value
Gamma operating B8 value
Gamma Operation Register 3
31
30
29
15
14
13
GAMMA_B9
GAMMA_B10
GAMMA_B11
22
21
10
9
8
7
6
5
28
27
26
25
15
14
13
12
11
10
9
20
19
GAMMA_B10
R/W
EDh
4
3
Re
lea
se
29
24
23
22
OPD_Y[31:16]
RO
0
8
7
6
OPD_Y[15:0]
RO
0
18
2
17
16
1
0
CAM_OPDY
21
20
19
18
17
16
5
4
3
2
1
0
21
20
19
18
17
16
5
4
3
2
1
0
OPD Y component accumulation result
30
15
14
OPD MG Result Register
29
28
27
26
13
12
11
10
25
24
23
22
OPD_MG[31:16]
RO
0
9
8
7
6
OPD_MG[15:0]
RO
0
OPD MG component accumulation result
31
30
15
14
OPD_RB
OPD RB Result Register
29
28
27
26
13
12
11
10
CAM_OPDRB
25
24
23
22
OPD_RB[31:16]
RO
0
9
8
7
6
OPD_RB[15:0]
RO
0
21
20
19
18
17
16
5
4
3
2
1
0
21
20
19
PXLCNT
MT
K
OPD RB component accumulation result
CAM+00E0h
31
CAM_OPDMG
Co
nf
id
en
tia
l
31
CAM+00DCh
Bit
Name
23
30
OPD_MG
Bit
Name
Type
Reset
Bit
Name
Type
Reset
24
31
CAM+00D8h
Bit
Name
Type
Reset
Bit
Name
Type
Reset
25
OPD Y Result Register
OPD_Y
CAM_GAMMA3
26
Gamma operating B9 value
Gamma operating B10 value
Gamma operating B11 value
CAM+00D4h
Bit
Name
Type
Reset
Bit
Name
Type
Reset
28
27
GAMMA_B9
R/W
E4h
12
11
GAMMA_B11
R/W
F7h
fo
r
CAM+00D0h
Bit
Name
Type
Reset
Bit
Name
Type
Reset
Revision 1.0
Ko
nk
a
MT6228 GSM/GPRS Baseband Processor Data Sheet
30
OPD Pixel Count Register
29
28
27
26
25
CAM_OPDCNT
24
23
388/616
22
18
17
16
MediaTek Inc. Confidential
R
0
14
PXLCNT
30
29
28
27
26
15
14
13
12
11
10
6
5
4
3
2
1
0
CAM_AE5RLT
25
24
23
22
21
SUM_ATF1[28:16]
RO
0
9
8
7
6
5
SUM_ATF1[15:0]
RO
0
20
19
4
3
18
17
16
2
1
0
29
28
27
26
15
14
13
12
11
10
CAM_ AE6RLT
25
24
23
22
21
SUM_ATF2[28:16]
RO
0
9
8
7
6
5
SUM_ATF2[15:0]
RO
0
Co
nf
id
en
tia
l
30
20
19
18
17
16
4
3
2
1
0
ATF window 2 accumulation result
CAM+00FCh
31
30
15
14
SUM_ATF3
ATF Result 3 Register
29
28
27
26
13
12
11
10
25
24
23
22
21
SUM_ATF3[28:16]
RO
0
9
8
7
6
5
SUM_ATF3[15:0]
RO
0
CAM_ AE7RLT
20
19
18
17
16
4
3
2
1
0
ATF window 3 accumulation result
CAM+0100h
30
ATF Result 4 Register
29
MT
K
15
8
7
PXLCNT
RO
0
ATF Result 2 Register
31
31
9
ATF window 1 accumulation result
SUM_ATF2
Bit
Name
Type
Reset
Bit
Name
Type
Reset
10
31
CAM+00F8h
Bit
Name
Type
Reset
Bit
Name
Type
Reset
11
ATF Result 1 Register
SUM_ATF1
Bit
Name
Type
Reset
Bit
Name
Type
Reset
12
OPD pixel counter accumulation result
CAM+00F4h
Bit
Name
Type
Reset
Bit
Name
Type
Reset
13
fo
r
15
Re
lea
se
Type
Reset
Bit
Name
Type
Reset
Revision 1.0
Ko
nk
a
MT6228 GSM/GPRS Baseband Processor Data Sheet
14
13
28
27
26
12
11
10
25
24
23
22
21
SUM_ATF4[28:16]
RO
0
9
8
7
6
5
SUM_ATF4[15:0]
RO
0
389/616
CAM_ AE8RLT
20
19
18
17
16
4
3
2
1
0
MediaTek Inc. Confidential
SUM_ATF4
ATF window 4 accumulation result
ATF Result 5 Register
31
30
29
28
27
26
15
14
13
12
11
10
CAM_ AE9RLT
25
24
23
22
21
SUM_ATF5[28:16]
RO
0
9
8
7
6
5
SUM_ATF5[15:0]
RO
0
SUM_ATF5 ATF window 5 accumulation result
Bit
Name
Type
Reset
Bit
Name
Type
Reset
CAM Histogram Result 1
30
29
28
27
26
25
24
22
21
15
14
13
12
11
10
9
8
7
6
CAM_HISRLT1[15:0]
RO
0
5
CAM_HISRLT1 Histogram level 1 count result
31
30
15
14
CAM Histogram Result 2
29
28
27
26
25
23
13
12
11
10
4
3
2
17
16
1
0
20
19
18
17
CAM_HISRLT1[21:16]
RO
0
4
3
2
1
16
0
CAM_HISRLT1
24
23
22
21
9
8
7
6
CAM_HISRLT2[15:0]
RO
0
5
Co
nf
id
en
tia
l
Bit
Name
Type
Reset
Bit
Name
Type
Reset
18
CAM_HISRLT0
31
CAM+010Ch
19
Re
lea
se
CAM+0108h
20
fo
r
CAM+0104h
Bit
Name
Type
Reset
Bit
Name
Type
Reset
Revision 1.0
Ko
nk
a
MT6228 GSM/GPRS Baseband Processor Data Sheet
20
19
18
17
CAM_HISRLT2[21:16]
RO
0
4
3
2
1
16
0
CAM_HISRLT2 Histogram level 2 count result
CAM+0110h
Bit
Name
Type
Reset
Bit
Name
Type
Reset
31
30
15
14
CAM Histogram Result 3
24
23
CAM_HISRLT2
29
28
27
26
25
22
21
13
12
11
10
9
8
7
6
CAM_HISRLT3[15:0]
RO
0
5
20
19
18
17
CAM_HISRLT3[21:16]
RO
0
4
3
2
1
16
0
CAM_HISRLT3 Histogram level 3 count result
CAM Histogram Result 4
MT
K
CAM+0114h
Bit
Name
Type
Reset
Bit
CAM_HISRLT3
31
30
29
28
27
26
25
24
23
22
21
15
14
13
12
11
10
9
8
7
6
5
390/616
20
19
18
17
CAM_HISRLT4[21:16]
RO
0
4
3
2
1
16
0
MediaTek Inc. Confidential
Name
Type
Reset
Revision 1.0
Ko
nk
a
MT6228 GSM/GPRS Baseband Processor Data Sheet
CAM_HISRLT4[15:0]
RO
0
CAM_HISRLT4 Histogram level 4 count result
Bit
Name
Type
Reset
Bit
Name
Type
Reset
CAM Histogram Result 5
CAM_HISRLT4
31
30
29
28
27
26
25
24
23
22
21
15
14
13
12
11
10
9
8
7
6
CAM_HISRLT5[15:0]
RO
0
5
20
19
18
17
CAM_HISRLT5[21:16]
RO
0
4
3
2
1
fo
r
CAM+0118h
16
0
CAM+011Ch
Bit
31
Low Pass Filter Control Register
30
29
28
27
26
25
24
14
13
12
C_LP
FEN
R/W
1
11
10
9
8
Name
Type
Reset
Bit
15
Y_LP
Name
FEN
Type R/W
Reset
0
Re
lea
se
CAM_HISRLT5 Histogram level 5 count result
CAM_LPFCON
23
22
21
20
19
18
17
7
6
5
4
3
2
1
16
V_LP
F_EN
R/W
0
0
CAM+0120h
Bit
Name
Type
Reset
Bit
Name
Type
Reset
31
30
15
14
Co
nf
id
en
tia
l
V_LPF_EN Enable vertical low pass filter. Vertical low pass filter will only be available in following two cases:
1.
Output image size smaller than 640 pixels.
2.
Y_LPFEN or C_LPFEN is turned on
Y_LPFEN
Enable Luminance channel low pass filter, if V_LPF_EN is off, only do horizontal low pass
C_LPFEN Enable Chrominance channel low pass filter, if V_LPF_EN is off, only do horizontal low pass
29
28
27
26
LPFY_WEIGHT0[7:0]
R/W
0
13
12
11
10
LPFY_WEIGHT2[7:0]
R/W
0
CAM+0124h
Bit
Name
Type
Reset
31
30
CAM_LPFY
25
24
23
22
9
8
7
6
21
20
19
18
LPFY_WEIGHT1[7:0]
R/W
0
5
4
3
2
LPFY_WEIGHT3[7:0]
R/W
0
17
16
1
0
Y low pass filter weighting 0
Y low pass filter weighting 1
Y low pass filter weighting 2
Y low pass filter weighting 3
MT
K
LPFY_WEIGHT0
LPFY_WEIGHT1
LPFY_WEIGHT2
LPFY_WEIGHT3
Y Low Pass Filter Control Register
CbCr Low Pass Filter Control Register
29
28
27
26
LPFC_WEIGHT0[7:0]
R/W
0
25
24
23
391/616
22
CAM_LPFC
21
20
19
18
LPFC_WEIGHT1[7:0]
R/W
0
17
16
MediaTek Inc. Confidential
14
13
12
11
10
LPFC_WEIGHT2[7:0]
R/W
0
LPFC_WEIGHT0
LPFC _WEIGHT1
LPFC _WEIGHT2
LPFC _WEIGHT3
CAM+0128h
Bit
31
15
29
14
13
31
14
H_SUB_EN
H_SUB_IN
H_SUB_OUT
31
Name
29
15
13
26
25
24
23
22
21
20
18
17
16
4
3
2
1
0
20
19
18
17
16
4
3
2
1
0
R/W
0
10
9
8
7
28
H_SU
B_EN
R/W
0
12
27
26
25
24
6
5
V_SUB_OUT
R/W
0
23
0
19
V_SUB_IN
11
1
CAM_VSUB
22
21
CAM_HSUB
H_SUB_IN
11
10
9
8
7
R/W
0
6
5
H_SUB_OUT
R/W
0
30
14
CAM_SGAMMA
R0
Sensor Gamma R0 Register
29
13
MT
K
Type
Reset
Bit
Name
Type
Reset
5
4
3
2
LPFC_WEIGHT[7:0]
R/W
0
Horizontal sub-sample enable
Source horizontal size
Sub-sample horizontal size
CAM+0130h
Bit
27
Co
nf
id
en
tia
l
15
6
Horizontal Subsample Control Register
30
Name
Type
Reset
Bit
Name
Type
Reset
28
V_SU
B_EN
R/W
0
12
Vertical sub-sample enable
Source vertical size
Sub-sample vertical size
CAM+012ch
Bit
7
Vertical Subsample Control Register
30
V_SUB_EN
V_SUB_IN
V_SUB_OUT
8
CbCr low pass filter weighting 0
CbCr low pass filter weighting 1
CbCr low pass filter weighting 2
CbCr low pass filter weighting 3
Name
Type
Reset
Bit
Name
Type
Reset
9
fo
r
15
Re
lea
se
Bit
Name
Type
Reset
Revision 1.0
Ko
nk
a
MT6228 GSM/GPRS Baseband Processor Data Sheet
28
27
SGAM
MA_E
N
R/W
0
12
11
R_B2
R/W
50h
26
10
25
9
24
SGAM
MA_I
VT
R/W
0
8
23
7
22
21
20
19
18
17
16
2
1
0
R_B1
R/W
32h
6
5
4
3
R_B3
R/W
65h
SGAMMA_EN
Sensor Gamma enable
SGAMMA_IVT Sensor Gamma output invert
R_B1
Gamma operating B1 value
R_B2
Gamma operating B2 value
392/616
MediaTek Inc. Confidential
R_B3
Gamma operating B3 value
30
29
15
14
13
30
29
15
14
13
24
23
22
21
10
9
8
7
6
5
28
27
R_B8
R/W
DAh
12
11
R_B10
R/W
EDh
20
19
R_B5
R/W
94h
4
3
R_B7
R/W
C5h
18
2
17
16
1
0
26
25
24
10
9
8
CAM_SGAMMA
R2
23
22
21
7
6
5
20
19
R_B9
R/W
D4h
4
3
R_B11
R/W
F7h
18
17
16
2
1
0
CAM_SGAMMA
G0
Sensor Gamma G0 Register
31
30
15
14
G_B1
G_B2
G_B3
G_B4
Co
nf
id
en
tia
l
Gamma operating B8 value
Gamma operating B9 value
Gamma operating B10 value
Gamma operating B11 value
CAM+013ch
29
13
28
27
G_B1
R/W
32h
12
11
G_B3
R/W
65h
26
25
24
23
22
21
10
9
8
7
6
5
20
19
G_B2
R/W
50h
4
3
G_B4
R/W
76h
18
17
16
2
1
0
MT
K
Gamma operating B1 value
Gamma operating B2 value
Gamma operating B3 value
Gamma operating B4 value
CAM+0140h
Bit
Name
Type
25
Sensor Gamma R2 Register
31
R_B8
R_B9
R_B10
R_B11
Bit
Name
Type
Reset
Bit
Name
Type
Reset
26
Gamma operating B4 value
Gamma operating B5 value
Gamma operating B6 value
Gamma operating B7 value
CAM+0138h
Bit
Name
Type
Reset
Bit
Name
Type
Reset
28
27
R_B4
R/W
76h
12
11
R_B6
R/W
AEh
fo
r
31
R_B4
R_B5
R_B6
R_B7
CAM_SGAMMA
R1
Sensor Gamma R1 Register
Re
lea
se
CAM+0134h
Bit
Name
Type
Reset
Bit
Name
Type
Reset
Revision 1.0
Ko
nk
a
MT6228 GSM/GPRS Baseband Processor Data Sheet
31
30
CAM_SGAMMA
G1
Sensor Gamma G1 Register
29
28
27
G_B5
R/W
26
25
24
23
393/616
22
21
20
19
G_B6
R/W
18
17
16
MediaTek Inc. Confidential
15
14
G_B5
G_B6
G_B7
G_B8
13
29
15
14
13
28
27
G_B9
R/W
E4h
12
11
G_B11
R/W
F7h
26
25
24
10
9
8
Gamma operating B9 value
Gamma operating B10 value
Gamma operating B11 value
Sensor Gamma B0 Register
7
6
5
AEh
4
3
G_B8
R/W
DAh
2
30
15
14
29
28
27
B_B1
R/W
32h
12
11
B_B3
R/W
65h
26
25
24
13
10
9
8
1
0
CAM_SGAMMA
G2
23
7
22
21
20
19
G_B10
R/W
EDh
4
3
6
5
18
17
16
2
1
0
CAM_SGAMMA
B0
23
Co
nf
id
en
tia
l
31
B_B1
B_B2
B_B3
B_B4
7
22
21
6
5
20
19
B_B2
R/W
50h
4
3
B_B4
R/W
76h
18
17
16
2
1
0
Gamma operating B1 value
Gamma operating B2 value
Gamma operating B3 value
Gamma operating B4 value
CAM+014ch
CAM_SGAMMA
B1
Sensor Gamma B1 Register
31
30
15
14
29
13
MT
K
B_B5
B_B6
B_B7
8
fo
r
30
CAM+0148h
Bit
Name
Type
Reset
Bit
Name
Type
Reset
9
Sensor Gamma G2 Register
31
G_B9
G_B10
G_B11
Bit
Name
Type
Reset
Bit
Name
Type
Reset
10
Gamma operating B5 value
Gamma operating B6 value
Gamma operating B7 value
Gamma operating B8 value
CAM+0144h
Bit
Name
Type
Reset
Bit
Name
Type
Reset
94h
12
11
G_B7
R/W
C5h
Re
lea
se
Reset
Bit
Name
Type
Reset
Revision 1.0
Ko
nk
a
MT6228 GSM/GPRS Baseband Processor Data Sheet
28
27
B_B5
R/W
94h
12
11
B_B7
R/W
C5h
26
25
24
23
22
21
10
9
8
7
6
5
20
19
B_B6
R/W
AEh
4
3
B_B8
R/W
DAh
18
17
16
2
1
0
Gamma operating B5 value
Gamma operating B6 value
Gamma operating B7 value
394/616
MediaTek Inc. Confidential
B_B8
Gamma operating B8 value
31
30
29
15
14
13
B_B9
B_B10
B_B11
CAM_SGAMMA
B2
Sensor Gamma B2 Register
28
27
B_B9
R/W
E4h
12
11
B_B11
R/W
F7h
26
25
24
23
22
21
10
9
8
7
6
5
20
19
B_B10
R/W
EDh
4
3
31
30
29
28
27
26
25
15
14
13
12
11
10
9
Name
DEFECT_EN
Defect table correct enable
CAM+0158h
Bit
Name
Type
Reset
Bit
Name
Type
Reset
31
30
15
14
DEFECT_ADDR
CAM+0180h
31
30
15
14
29
28
27
26
13
12
11
10
CAM+0184h
Bit
31
30
17
16
1
0
CAM_DEFECT0
23
22
21
20
19
18
17
16
7
6
5
4
3
2
1
0
Defect Pixel Table Address Register
CAM_DEFECT1
25
24
23
22
DEFFECT_ADDR[31:16]
RW
2000h
9
8
7
6
DEFECT_ADDR[15:0]
RW
0
21
20
19
18
17
16
5
4
3
2
1
0
Defect table location address
Camera Interface Debug Mode Control Register
CAM_DEBUG
29
28
27
26
25
24
23
22
21
20
19
18
17
16
13
12
11
10
9
8
7
6
5
4
3
2
1
0
MT
K
Bit
Name
Type
Reset
Bit
Name
Type
Reset
24
DEFE
CT_E
N
R/W
0
8
Co
nf
id
en
tia
l
Type
Reset
Bit
Name
Type
Reset
2
Re
lea
se
Gamma operating B9 value
Gamma operating B10 value
Gamma operating B11 value
CAM+00154h Defect Pixel Configuration Register
Bit
18
fo
r
CAM+0150h
Bit
Name
Type
Reset
Bit
Name
Type
Reset
Revision 1.0
Ko
nk
a
MT6228 GSM/GPRS Baseband Processor Data Sheet
Camera Module Debug Information Write Out
Destination Address
29
28
27
26
25
24
23
395/616
22
21
CAM_DSTADD
R
20
19
18
17
16
MediaTek Inc. Confidential
14
DST_ADD
10
5
4
3
2
30
29
28
27
26
15
14
13
12
11
10
25
24
23
22
LAST_ADD[31:16]
R/W
0
9
8
7
6
LAST_ADD[15:0]
R/W
0
21
20
5
4
1
0
CAM_LASTADD
R
fo
r
Camera Module Debug Information Last Transfer
Destination Address
19
18
17
16
3
2
1
0
Debug Information Last Transfer Destination Address
CAM+018Ch
Camera Module Frame Buffer Transfer Out Count
Register
31
30
29
28
27
26
15
14
13
12
11
10
XFER_COUNT
CAM+0190h
Bit
Name
Type
Reset
Bit
Name
Type
Reset
11
31
LAST_ADD
Bit
Name
Type
Reset
Bit
Name
Type
Reset
12
Debug Information Write Output Destination Address
CAM+0188h
Bit
Name
Type
Reset
Bit
Name
Type
Reset
13
Re
lea
se
15
DST_ADD[31:16]
R/W
4000h
9
8
7
6
DST_ADD[15:0]
R/W
0000h
31
30
15
14
25
24
23
22
XFER_COUNT [31:16]
RO
0
9
8
7
6
XFER_COUNT[15:0]
RO
0
Co
nf
id
en
tia
l
Name
Type
Reset
Bit
Name
Type
Reset
Revision 1.0
Ko
nk
a
MT6228 GSM/GPRS Baseband Processor Data Sheet
CAM_XFERCNT
21
20
19
18
17
16
5
4
3
2
1
0
Pixel Transfer Count per Frame
CAM_MDLCFG
1
CMOS Sensor Test Model Configuration Register 1
29
13
28
27
VSYNC
R/W
0
12
11
26
25
10
9
ON
R/W
0
24
23
8
7
RST STILL
R/W R/W
0
0
22
21
20
19
18
17
IDLE_PIXEL_PER_LINE
R/W
0
6
5
4
3
2
1
PATTERN
CLK_DIV
R/W
R/W
0
0
16
0
MT
K
VSYNC
VSYNC high duration in line unit(IDLE_PIXEL_PER_LINE + PIXEL)
IDLE_PIXEL_PER_LINE HSYNC low duration in pixel unit
ON
Enable CMOS Sensor Model
RST
Reset CMOS Sensor Model
STILL
Still picture Mode
PATTERN
CMOS Sensor Model Test Pattern Selection
CLK_DIV
Pixel_Clock/System_Clock Ratio
396/616
MediaTek Inc. Confidential
31
30
29
28
27
26
25
24
23
22
15
14
13
12
11
10
9
8
7
6
LINE
PIXEL
30
29
28
27
26
25
24
15
14
13
12
11
10
9
8
Reserved
4
3
2
17
16
1
0
30
29
28
27
26
25
24
15
14
13
12
11
10
9
8
30
29
28
27
26
15
14
13
12
11
10
21
20
19
18
17
16
7
6
5
4
3
2
1
0
RESERVED
23
22
21
20
19
18
17
16
7
6
5
4
3
2
1
0
25
24
23
22
AE_ADDR[31:16]
R/W
0
9
8
7
6
AE_ADDR[15:0]
R/W
0
CAM_AEADDR
21
20
19
18
17
16
5
4
3
2
1
0
AE Statistic writed out address.
High bandwidth is required, recommend to set in sram
CAM+01A4h
30
AE Window Size Register
29
MT
K
15
22
AE Address Register
31
31
23
Co
nf
id
en
tia
l
31
AE_ADDR
Bit
Name
Type
Reset
Bit
Name
Type
Reset
18
RESERVED
31
CAM+01A0h
Bit
Name
Type
Reset
Bit
Name
Type
Reset
19
Reserved
CAM+019Ch
Bit
Name
Type
Reset
Bit
Name
Type
Reset
20
CMOS Sensor Model Line Number
CMOS Sensor Model Pixel Number (HSYNC high duration in pixel unit)
CAM+0198h
Bit
Name
Type
Reset
Bit
Name
Type
Reset
21
LINE
R/W
0
5
PIXEL
R/W
0
Re
lea
se
Bit
Name
Type
Reset
Bit
Name
Type
Reset
CAM_MDLCFG
2
CMOS Sensor Test Model Configuration Register 2
fo
r
CAM +0194h
Revision 1.0
Ko
nk
a
MT6228 GSM/GPRS Baseband Processor Data Sheet
14
13
28
27
26
12
11
10
25
24
23
22
AE_VSIZE[15:0]
R/W
0
9
8
7
6
AE_HSIZE[15:0]
R/W
0
397/616
CAM_AESIZE
21
20
19
18
17
16
5
4
3
2
1
0
MediaTek Inc. Confidential
AE_VSIZE
AE_HSIZE
AE window vertical size
AE window horizontal size
Notes:
Total number of AE statistic window is 63 limited. When AE is on, vertical size and
horizontal size must be set to avoid ae window exceed 63
15
30
29
28
AE_WEIGHT00
R/W
1
14
13
12
AE_WEIGHT04
R/W
1
27
11
26
25
24
AE_WEIGHT01
R/W
1
10
9
8
AE_WEIGHT05
R/W
1
AE_WEIGHT00~07 AE window 00~07 weight
CAM+01ACh
31
15
30
29
28
AE_WEIGHT08
R/W
1
14
13
12
AE_WEIGHT12
R/W
1
27
11
26
25
24
AE_WEIGHT09
R/W
1
10
9
8
AE_WEIGHT13
R/W
1
7
23
7
Co
nf
id
en
tia
l
Bit
Name
Type
Reset
Bit
Name
Type
Reset
AE Weight 2 Register
23
22
21
20
AE_WEIGHT02
R/W
1
6
5
4
AE_WEIGHT06
R/W
1
19
22
21
20
AE_WEIGHT10
R/W
1
6
5
4
AE_WEIGHT14
R/W
1
18
17
16
AE_WEIGHT03
R/W
1
2
1
0
AE_WEIGHT07
R/W
1
fo
r
31
CAM_AEWEIG
HT0
AE Weight 1 Register
3
Re
lea
se
CAM+01A8h
Bit
Name
Type
Reset
Bit
Name
Type
Reset
Revision 1.0
Ko
nk
a
MT6228 GSM/GPRS Baseband Processor Data Sheet
19
3
CAM_AEWEIG
HT1
18
17
16
AE_WEIGHT11
R/W
1
2
1
0
AE_WEIGHT15
R/W
1
AE_WEIGHT08~15 AE window 08~15 weight
CAM+01B0h
Bit
Name
Type
Reset
Bit
Name
Type
Reset
31
15
CAM_AEWEIG
HT2
AE Weight 3 Register
30
29
28
AE_WEIGHT16
R/W
1
14
13
12
AE_WEIGHT20
R/W
1
27
11
26
25
24
AE_WEIGHT17
R/W
1
10
9
8
AE_WEIGHT21
R/W
1
23
7
22
21
20
AE_WEIGHT18
R/W
1
6
5
4
AE_WEIGHT22
R/W
1
19
3
18
17
16
AE_WEIGHT19
R/W
1
2
1
0
AE_WEIGHT23
R/W
1
AE_WEIGHT16~23 AE window 16~23 weight
CAM+01B4h
31
30
29
28
AE_WEIGHT24
R/W
1
14
13
12
AE_WEIGHT28
R/W
1
MT
K
Bit
Name
Type
Reset
Bit
Name
Type
Reset
15
CAM_AEWEIG
HT3
AE Weight 4 Register
27
11
26
25
24
AE_WEIGHT25
R/W
1
10
9
8
AE_WEIGHT29
R/W
1
23
398/616
7
22
21
20
AE_WEIGHT26
R/W
1
6
5
4
AE_WEIGHT30
R/W
1
19
3
18
17
16
AE_WEIGHT27
R/W
1
2
1
0
AE_WEIGHT31
R/W
1
MediaTek Inc. Confidential
Revision 1.0
Ko
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a
MT6228 GSM/GPRS Baseband Processor Data Sheet
AE_WEIGHT24~31 AE window 24~31 weight
Bit
Name
Type
Reset
Bit
Name
Type
Reset
31
15
CAM_AEWEIG
HT4
AE Weight 5 Register
30
29
28
AE_WEIGHT32
R/W
1
14
13
12
AE_WEIGHT36
R/W
1
27
11
26
25
24
AE_WEIGHT33
R/W
1
10
9
8
AE_WEIGHT37
R/W
1
23
7
22
21
20
AE_WEIGHT34
R/W
1
6
5
4
AE_WEIGHT38
R/W
1
CAM+01BCh
Bit
Name
Type
Reset
Bit
Name
Type
Reset
31
15
AE Weight 6 Register
30
29
28
AE_WEIGHT40
R/W
1
14
13
12
AE_WEIGHT44
R/W
1
27
11
26
25
24
AE_WEIGHT41
R/W
1
10
9
8
AE_WEIGHT45
R/W
1
AE_WEIGHT 40~47 AE window 40~47 weight
CAM+01C0h
31
15
30
29
28
AE_WEIGHT48
R/W
1
14
13
12
AE_WEIGHT52
R/W
1
27
26
25
24
AE_WEIGHT49
R/W
1
10
9
8
AE_WEIGHT53
R/W
1
23
7
23
Co
nf
id
en
tia
l
Bit
Name
Type
Reset
Bit
Name
Type
Reset
AE Weight 7 Register
11
18
17
16
AE_WEIGHT35
R/W
1
2
1
0
AE_WEIGHT39
R/W
1
3
Re
lea
se
AE_WEIGHT 32~39 AE window 32~39 weight
19
fo
r
CAM+01B8h
7
22
21
20
AE_WEIGHT42
R/W
1
6
5
4
AE_WEIGHT46
R/W
1
22
21
20
AE_WEIGHT50
R/W
1
6
5
4
AE_WEIGHT54
R/W
1
19
3
19
3
CAM_AEWEIG
HT5
18
17
16
AE_WEIGHT43
R/W
1
2
1
0
AE_WEIGHT47
R/W
1
CAM_AEWEIG
HT6
18
17
16
AE_WEIGHT51
R/W
1
2
1
0
AE_WEIGHT55
R/W
1
AE_WEIGHT 48~55 AE window 48~55 weight
CAM+01C4h
31
15
30
29
28
AE_WEIGHT56
R/W
1
14
13
12
AE_WEIGHT60
R/W
1
MT
K
Bit
Name
Type
Reset
Bit
Name
Type
Reset
CAM_AEWEIG
HT7
AE Weight 8 Register
27
11
26
25
24
AE_WEIGHT57
R/W
1
10
9
8
AE_WEIGHT61
R/W
1
23
7
22
21
20
AE_WEIGHT58
R/W
1
6
5
4
AE_WEIGHT62
R/W
1
19
3
18
17
16
AE_WEIGHT59
R/W
1
2
1
0
AE_WEIGHT 56~62 AE window 56~62 weight
CAM+01C8h
Bit
Name
31
30
AE Area Register
29
28
27
26
AE_VOFFSET[7:0]
CAM_AEAREA
25
24
23
399/616
22
21
20
19
18
AE_HOFFSET[7:0]
17
16
MediaTek Inc. Confidential
Type
Reset
Bit
Name
Type
Reset
R/W
0
15
14
Revision 1.0
Ko
nk
a
MT6228 GSM/GPRS Baseband Processor Data Sheet
R/W
0
13
12
11
10
AE_FRAMECNT[7:0]
R
0
9
8
7
6
5
4
3
2
1
AE_AREACNT[5:0]
R
0
AE_VOFFSET AE window vertical offset
AE_HOFFSET AE window horizontal offset
AE Frame interval counter
fo
r
AE_FRAMECNT
AE_AREACNT AE Window Area counter
Bit
31
30
CAM_ADEFEC
T0
AutoDefect Control 1 Register
26
25
24
23
22
DEAD
ADC_ ADL_ ADR_ ADU_ ADD_
RBCHECKS
Name
CHEC GCHECKSEL
EN
EN
EN
EN
EN
EL
K
Type R/W R/W R/W R/W R/W R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
Name
AE_INTERVAL
Type
R/W
Reset
0
ADC_En
ADL_En
ADR_En
ADU_En
ADD_En
DEADCHECK
GCHECKSEl
29
28
Re
lea
se
CAM+01CCh
27
0
21
20
19
18
17
16
BRIGHTTHD
BLACKTHD
R/W
0
4
R/W
0
1
5
3
2
0
Co
nf
id
en
tia
l
Center Autodefect cell enable
Left Autodefect cell enable
Right Autodefect cell enable
Up Autodefect cell enable
Down Autodefect cell enable
Dead pixel check enable
G pixel check method selection
00 near group check only
01 near and far groups check
10 far group check only
11 reserved
RBCHECKSEl
RB pixel check method selection
00 near group check only
01 near and far groups check
10 far group check only
11 reserved
BRIGHTTHD
Black pixel threshold = BRIGHTTHD *4
BLACKTHD
Black pixel threshold = BLACKTHD *4
AE_INTERVAL
AE frame interval
Bit
Name
Type
Reset
31
30
CAM_ADEFECT
1
AutoDefect Control 2 Register
MT
K
CAM+01D0h
29
28
27
GCHECKTHD
R/W
0
26
25
24
23
400/616
22
21
20
19
18
RBCHECKTHD
R/W
0
17
16
MediaTek Inc. Confidential
14
13
GCHECKTHD
RBCHECKTHD
GCORRECTTHD
RBCORRECTTHD
CAM+01D4h
Bit
31
30
29
28
27
26
25
FLAS
H_EN
14
13
RW
0
12
11
10
Name
FLASH_LNUNIT_NO[7:0]
Type
Reset
RW
0
FLASH_OUT
Flash out status
FLASH_EN
Flash enable
FLASH_STARTPNT
7
6
5
4
3
2
RBCORRECTTHD
R/W
0
1
9
24
FLAS
H_ST
ARTP
NT
RW
0
8
Flash start point
0
Start from vsync start
1
Start from expdone
0
CAM_FLASH
23
22
21
20
FLAS
H_PO
L
7
Co
nf
id
en
tia
l
FLASH_POL
8
Flash Control Register
R
15
9
G pixel check threshold
RB pixel check threshold
G pixel correct threshold
RB pixel correct threshold
FLAS
Name H_OU
T
Type
Reset
Bit
12
11
10
GCORRECTTHD
R/W
0
fo
r
15
19
6
5
RW
0
4
18
17
16
FLASH_LNUNIT[3:0]
Re
lea
se
Bit
Name
Type
Reset
Revision 1.0
Ko
nk
a
MT6228 GSM/GPRS Baseband Processor Data Sheet
3
RW
0
2
1
0
FLASH_FR
AME_DELA
Y[1:0]
RW
0
Flash line polarity
FLASH_LNUNIT
Flash line unit, 0~15 lines
FLASH_LNUNIT_NO
Flash line unit count
FLASH_FRAME_DELAY Flash frame delay
CAM +01D8h CAM RESET Register
Bit
Name
Type
Reset
Bit
Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
TG_STATUS
R
15
14
13
12
11
10
9
8
7
6
5
4
3
ISP_FRAME_COUNT[7:0]
MT
K
Type
Reset
CAM_RESET
ISP_FRAME_COUNT
ISP_RESET
RW
0
2
1
16
0
ISP_
RES
ET
RW
0
ISP frame counter
ISP reset
401/616
MediaTek Inc. Confidential
CAM +01DCh TG STATUS Register
31
30
29
Name
Type
Reset
Bit
Name
Type
Reset
15
14
13
28
SYN_
VFON
R
27
12
11
26
TG_STATUS
25
24
23
22
21
20
19
18
7
6
5
4
PIXEL_COUNT[11:0]
R
3
2
LINE_COUNT[11:0]
R
10
9
8
SYN_VFON
TG view finder status
LINE_COUNT TG line counter
PIXEL_COUNT TG pixel counter
Bit
Name
Type
Reset
Bit
Name
Type
Reset
Histogram Boundary Control Register3
31
30
29
15
14
13
H6_BND
H7_BND
H8_BND
H9_BND
30
15
14
13
28
27
HA_BND
R/W
a0h
12
11
HC_BND
R/W
c0h
1
0
24
10
9
8
23
22
21
7
6
5
20
19
H7_BND
R/W
70h
4
3
H9_BND
R/W
90H
CAM_HIS2
18
17
16
2
1
0
Histogram Boundary Control Register4
29
16
CAM_HIS3
26
25
24
23
22
21
10
9
8
7
6
5
20
19
HB_BND
R/W
b0h
4
3
HD_BND
R/W
d0H
18
17
16
2
1
0
20
19
HF_BND
R/W
f0h
4
3
18
17
16
2
1
0
Histogram level A up boundary value
Histogram level B up boundary value
Histogram level C up boundary value
Histogram level D up boundary value
CAM+01E8h
Histogram Boundary Control Register5
30
29
15
14
13
MT
K
31
HDE_ND
25
Co
nf
id
en
tia
l
31
HA_BND
HB_BND
HC_BND
HD_BND
Bit
Name
Type
Reset
Bit
Name
Type
Reset
26
Histogram level 6 up boundary value
Histogram level 7 up boundary value
Histogram level 8 up boundary value
Histogram level 9 up boundary value
CAM+01E4h
Bit
Name
Type
Reset
Bit
Name
Type
Reset
28
27
H6_BND
R/W
60h
12
11
H8_BND
R/W
80h
Re
lea
se
CAM+01E0h
17
fo
r
Bit
Revision 1.0
Ko
nk
a
MT6228 GSM/GPRS Baseband Processor Data Sheet
28
27
HE_BND
R/W
e0h
12
11
CAM_HIS4
26
25
24
23
22
21
10
9
8
7
6
5
Histogram level E up boundary value
402/616
MediaTek Inc. Confidential
HEF_ND
Histogram level F up boundary value
CAM+01ECh
CAM_HISRLT5
31
30
29
28
27
26
25
24
23
22
21
15
14
13
12
11
10
9
8
7
6
CAM_HISRLT6[15:0]
RO
0
5
CAM_HISRLT6 Histogram level 6 count result
CAM+01F0h
CAM Histogram Result 7
31
30
29
28
27
26
25
15
14
13
12
11
10
9
8
7
6
CAM_HISRLT7[15:0]
RO
0
24
CAM_HISRLT7 Histogram level 7 count result
CAM+01F4h
CAM Histogram Result 8
23
0
22
21
20
19
18
17
CAM_HISRLT7[21:16]
RO
0
4
3
2
1
5
16
0
CAM_HISRLT7
31
30
29
28
27
26
25
24
23
22
21
15
14
13
12
11
10
9
8
7
6
CAM_HISRLT8[15:0]
RO
0
5
Co
nf
id
en
tia
l
Bit
Name
Type
Reset
Bit
Name
Type
Reset
16
CAM_HISRLT6
Re
lea
se
Bit
Name
Type
Reset
Bit
Name
Type
Reset
20
19
18
17
CAM_HISRLT6[21:16]
RO
0
4
3
2
1
fo
r
Bit
Name
Type
Reset
Bit
Name
Type
Reset
CAM Histogram Result 6
Revision 1.0
Ko
nk
a
MT6228 GSM/GPRS Baseband Processor Data Sheet
20
19
18
17
CAM_HISRLT8[21:16]
RO
0
4
3
2
1
16
0
CAM_HISRLT8 Histogram level 8 count result
CAM+01F8h
Bit
Name
Type
Reset
Bit
Name
Type
Reset
31
30
15
14
CAM Histogram Result 9
24
23
CAM_HISRLT8
29
28
27
26
25
22
21
13
12
11
10
9
8
7
6
CAM_HISRLT9[15:0]
RO
0
5
20
19
18
17
CAM_HISRLT9[21:16]
RO
0
4
3
2
1
16
0
CAM_HISRLT9 Histogram level 9 count result
CAM+01FCh
31
30
29
MT
K
Bit
Name
Type
Reset
Bit
Name
Type
Reset
CAM Histogram Result 10
15
14
13
24
23
CAM_HISRLT9
28
27
26
25
22
21
12
11
10
9
8
7
6
CAM_HISRLTA[15:0]
RO
0
5
403/616
20
19
18
17
CAM_HISRLTA[21:16]
RO
0
4
3
2
1
16
0
MediaTek Inc. Confidential
CAM_HISRLTA Histogram level 10 count result
CAM+0200h
CAM_HISRLTA
31
30
29
28
27
26
25
24
23
22
21
15
14
13
12
11
10
9
8
7
6
CAM_HISRLTB[15:0]
RO
0
5
CAM_HISRLTB Histogram level 11 count result
CAM+0204h
CAM Histogram Result 12
31
30
29
28
27
26
25
22
21
15
14
13
12
11
10
9
8
7
6
CAM_HISRLTC[15:0]
RO
0
5
24
CAM_HISRLTC Histogram level 12 count result
Bit
Name
Type
Reset
Bit
Name
Type
Reset
31
30
15
14
CAM Histogram Result 13
29
28
27
26
25
23
13
12
11
10
0
20
19
18
17
CAM_HISRLTC[21:16]
RO
0
4
3
2
1
16
0
CAM_HISRLTC
24
23
22
21
9
8
7
6
CAM_HISRLTD[15:0]
RO
0
5
Co
nf
id
en
tia
l
CAM+0208h
16
CAM_HISRLTB
Re
lea
se
Bit
Name
Type
Reset
Bit
Name
Type
Reset
20
19
18
17
CAM_HISRLTB[21:16]
RO
0
4
3
2
1
fo
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Bit
Name
Type
Reset
Bit
Name
Type
Reset
CAM Histogram Result 11
Revision 1.0
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20
19
18
17
CAM_HISRLTD[21:16]
RO
0
4
3
2
1
16
0
CAM_HISRLTD Histogram level 13 count result
CAM+020Ch
Bit
Name
Type
Reset
Bit
Name
Type
Reset
31
30
15
14
CAM_HISRLTE
CAM+0210h
24
23
CAM_HISRLTD
29
28
27
26
25
22
21
13
12
11
10
9
8
7
6
CAM_HISRLTE[15:0]
RO
0
5
20
19
18
17
CAM_HISRLTE[21:16]
RO
0
4
3
2
1
16
0
Histogram level 14 count result
CAM Histogram Result 15
24
23
CAM_HISRLTE
31
30
29
28
27
26
25
22
21
15
14
13
12
11
10
9
8
7
6
CAM_HISRLTF[15:0]
RO
5
MT
K
Bit
Name
Type
Reset
Bit
Name
Type
CAM Histogram Result 14
404/616
20
19
18
17
CAM_HISRLTF[21:16]
RO
0
4
3
2
1
16
0
MediaTek Inc. Confidential
Reset
0
CAM_HISRLTF
Histogram level 15 count result
CAM_SHADING
1
CAM+00214h Shading Cotrol 1 Register
Type
Reset
Bit
Name
Type
Reset
30
29
28
SHAD SHAD
SHAD
ING_ ING_
ING_E
RANG RANG
N
E[8] E_EN
RW
RW
RW
0
0
0
15
14
13
12
RADIUS_FA
K_FACTOR
CTOR
R/W
R/W
0
0
27
26
25
24
23
22
21
20
19
18
17
16
SHADING_CENTERY[11:0]
RW
0
11
10
9
8
7
6
5
4
fo
r
Name
31
3
2
1
0
SHADING_CENTERX[11:0]
RW
0
SHADING_RANGE[8]
Shading range bit 8
SHADING_RANGE_EN
Shading range enable
SHADING_EN
Shading enable
Re
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Bit
Revision 1.0
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MT6228 GSM/GPRS Baseband Processor Data Sheet
Shading_out = Shading_in*(1+Compensation_Ratio)
Where
Compensation_Ratio = Effective_Range*(K>>(26-K_FACTOR))
K = KR when R pixel, KG when G pixel, KB when B pixel
Shading parameter factor, used to scale up parameter.
RADIUS_FACTOR
Radius factor, select effective radius range.
Co
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K_FACTOR
Effective_Range = ((effective_diffx)^2) + ((effective_diffy)^2)
Where effective_diffx = (x-centerx)>>(3-RADIUS_FACTOR)
effective_diffy = (y-centery)>>(3-RADIUS_FACTOR)
Because of hardware limitation,
effective maximum radius(range between center) is
00
Effective maximum radius : 4095
01
Effective maximum radius : 2047
02
Effective maximum radius : 1023
03
Effective maximum radius : 511
Shading center y coordinate x 2
SHADING_CENTERX
Shading center x coordinate x 2
MT
K
SHADING_CENTERY
CAM+0218h
Bit
Name
Type
31
30
CAM_SHADING
2
Shading Control 2 Register
29
28
27
26
SHADING_KR[7:0]
RW
25
24
23
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21
20
19
18
SHADING_KG[7:0]
RW
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16
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0
13
12
11
10
SHADING_KB[7:0]
RW
0
14
9
8
7
SHADING_KR
Shading R pixel parameter
SHADING_KG
Shading G pixel parameter
SHADING_KB
Shading B pixel parameter
SHADING_RANGE
Shading range, bit8 refer to 0x214 bit 30
Bit
31
30
15
14
29
28
27
26
25
24
SHAD
SHAD
SHADING_C
ING_
ING_I
CURV
URVE_SEL
VT
E_EN
R/W
R/W
R/W
0
0
0
13
12
11
10
9
8
SHADING_R_B2
R/W
40h
CAM+0220h
Bit
Name
Type
Reset
Bit
Name
Type
Reset
31
30
15
14
23
21
20
19
18
17
16
4
3
2
SHADING_R_B3
R/W
60h
1
0
R/W
20h
7
6
5
Shading curve enable
Shading curve output invert
Shading curve input selection
1/8 Effective_Range input
1/4 Effective_Range input
1/2 Effecitve_Range input
Effective Range input
R shading curve operating B1 value
R shading curve operating B2 value
R shading curve operating B3 value
28
27
26
SHADING_R_B4
R/W
80h
13
12
11
10
SHADING_R_B6
R/W
A0h
MT
K
SHADING_R_B4
SHADING_R_B5
SHADING_R_B6
SHADING_R_B7
22
CAM_SRCURV
E1
Shading R Curve Register 2
29
0
SHADING_R_B1
Co
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SHADING_CURVE_EN
SHADING_IVT
SHADING_CURVE_SEL
00
01
02
03
SHADING_R_B1
SHADING_R_B2
SHADING_R_B3
1
CAM_SRCURV
E0
Shading R Curve Register 1
Name
Type
Reset
Bit
Name
Type
Reset
0
5
4
3
2
SHADING_RANGE[7:0]
R/W
Ff
Re
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CAM+021Ch
6
fo
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Reset
Bit
Name
Type
Reset
Revision 1.0
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MT6228 GSM/GPRS Baseband Processor Data Sheet
25
24
23
22
9
8
7
6
21
20
19
18
SHADING_R_B5
R/W
90h
5
4
3
2
SHADING_R_B7
R/W
B0h
17
16
1
0
R shading curve operating B4 value
R shading curve operating B5 value
R shading curve operating B6 value
R shading curve operating B7 value
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31
30
15
14
29
28
27
26
SHADING_R_B8
R/W
C0h
13
12
11
10
SHADING_R_B10
R/W
E0h
SHADING_R_B8
SHADING_R_B9
SHADING_R_B10
SHADING_R_B11
CAM+0228h
Bit
Name
Type
Reset
Bit
Name
Type
Reset
31
30
15
14
31
30
15
14
29
28
27
26
SHADING_G_B1
R/W
20h
13
12
11
10
SHADING_G_B3
R/W
60h
31
30
9
8
7
6
21
20
19
18
SHADING_R_B9
R/W
D0h
5
4
3
2
SHADING_R_B11
R/W
F0h
25
24
9
8
17
16
1
0
CAM_SGCURV
E0
23
22
7
6
21
20
19
18
SHADING_G_B2
R/W
40h
5
4
3
2
SHADING_G_B4
R/W
80h
17
16
1
0
G shading curve operating B1 value
G shading curve operating B2 value
G shading curve operating B3 value
G shading curve operating B4 value
CAM_SGCURV
E1
Shading G Curve Register 2
29
28
27
26
SHADING_G_B5
R/W
90h
13
12
11
10
SHADING_G_B7
R/W
B0h
25
24
23
22
9
8
7
6
21
20
19
18
SHADING_G_B6
R/W
A0h
5
4
3
2
SHADING_G_B8
R/W
C0h
17
16
1
0
G shading curve operating B5 value
G shading curve operating B6 value
G shading curve operating B7 value
G shading curve operating B8 value
CAM_SGCURV
E2
Shading G Curve Register 3
MT
K
Bit
Name
Type
Reset
22
Shading G Curve Register 1
SHADING_G_B5
SHADING_G_B6
SHADING_G_B7
SHADING_G_B8
CAM+0230h
23
Co
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Bit
Name
Type
Reset
Bit
Name
Type
Reset
24
R shading curve operating B8 value
R shading curve operating B9 value
R shading curve operating B10 value
R shading curve operating B11 value
SHADING_G_B1
SHADING_G_B2
SHADING_G_B3
SHADING_G_B4
CAM+022Ch
25
fo
r
Bit
Name
Type
Reset
Bit
Name
Type
Reset
CAM_SRCURV
E2
Shading R Curve Register 3
Re
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se
CAM+0224h
Revision 1.0
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29
28
27
26
SHADING_G_B9
R/W
D0h
25
24
23
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21
20
19
18
SHADING_G_B10
R/W
E0h
17
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14
13
SHADING_G_B9
SHADING_G_B10
SHADING_G_B11
CAM+0234h
Bit
Name
Type
Reset
Bit
Name
Type
Reset
31
30
15
14
15
14
29
28
27
26
SHADING_B_B1
R/W
20h
13
12
11
10
SHADING_B_B3
R/W
60h
31
30
15
14
5
29
SHADING_B_B9
SHADING_B_B10
SHADING_B_B11
4
3
2
1
0
CAM_SBCURV
E0
25
24
23
22
9
8
7
6
Shading B Curve Register 2
28
27
26
SHADING_B_B5
R/W
90h
13
12
11
10
SHADING_B_B7
R/W
B0h
21
20
19
18
SHADING_B_B2
R/W
40h
5
4
3
2
SHADING_B_B4
R/W
80h
17
16
1
0
25
24
CAM_SGCURV
E1
23
9
8
7
22
6
21
20
19
18
SHADING_B_B6
R/W
A0h
5
4
3
2
SHADING_B_B8
R/W
C0h
17
16
1
0
G shading curve operating B5 value
G shading curve operating B6 value
G shading curve operating B7 value
G shading curve operating B8 value
CAM_SBCURV
E2
Shading B Curve Register 3
29
28
27
26
SHADING_B_B9
R/W
D0h
13
12
11
10
SHADING_B_B11
R/W
F0h
MT
K
Bit
Name
Type
Reset
Bit
Name
Type
Reset
6
B shading curve operating B1 value
B shading curve operating B2 value
B shading curve operating B3 value
B shading curve operating B4 value
SHADING_B_B5
SHADING_B_B6
SHADING_B_B7
SHADING_B_B8
CAM+023Ch
7
Co
nf
id
en
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30
8
Shading B Curve Register 1
CAM+0238h
31
9
G shading curve operating B9 value
G shading curve operating B10 value
G shading curve operating B11 value
SHADING_B_B1
SHADING_B_B2
SHADING_B_B3
SHADING_B_B4
Bit
Name
Type
Reset
Bit
Name
Type
Reset
12
11
10
SHADING_G_B11
R/W
F0h
fo
r
15
Re
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Bit
Name
Type
Reset
Revision 1.0
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25
24
23
22
9
8
7
6
21
20
19
18
SHADING_B_B10
R/W
E0h
5
4
3
2
17
16
1
0
B shading curve operating B9 value
B shading curve operating B10 value
B shading curve operating B11 value
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CAM+0240h
Bit
Revision 1.0
CAM IMAGE-PROCOR HUE Register 1
CAM_HUE0
31
30
29
28
27
26
25
24
23
22
21
20
19
18
15
14
13
12
11
HUE11
RW
40h
10
9
8
7
6
5
4
3
HUE12
RW
0
2
Bit
Name
Type
Reset
Bit
Name
Type
Reset
CAM IMAGE-PROCOR HUE Register 2
31
30
29
15
14
13
28
27
HUE21
RW
0
12
11
26
25
24
10
9
8
23
22
7
6
1
16
HUE
_EN
RW
0
0
CAM_HUE1
21
20
19
HUE22
RW
40
4
3
Re
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se
CAM+0244h
17
fo
r
Name
Type
Reset
Bit
Name
Type
Reset
Ko
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MT6228 GSM/GPRS Baseband Processor Data Sheet
5
18
17
16
2
1
0
HUE_EN Hue enable
This register controls the parameter of hue adjustment for the image. The effect is performed on the U and V
component of YUV color space. The user should specify the coefficients that form the transformation matrix. The
formula is listed as follows:
u0
C11 C12 ui
=
⋅
vo
C 21 C 22 vi
Co
nf
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C11 = 64 cosθ , C12 = 64 sin θ , C 21 = −64 sin θ , C 22 = 64 cosθ
where
The coefficients are in 2’s complement format and range from C0h to 40h (from –64 to 64 in decimal, while 64 is
normalized to 1 corresponding to cosine values). Any value beyond this range is invalid.
For example, to rotate the color space counterclockwise by 30 degree, the coefficients should be 37h, 20h, e0h, and
37h.
HUE11
HUE12
HUE21
HUE22
The coefficient C11 of the transformation matrix in 2’s complement format.
The coefficient C12 of the transformation matrix in 2’s complement format.
The coefficient C21 of the transformation matrix in 2’s complement format.
The coefficient C22 of the transformation matrix in 2’s complement format.
CAM +0248h
31
30
15
14
CAM_DEBUG
29
28
27
26
25
24
23
22
21
20
19
18
17
16
13
12
11
10
9
8
7
6
5
4
3
2
1
0
MT
K
Bit
Name
Type
Reset
Bit
Name
Type
Reset
CAM GMC DEBUG Register
CAM +024Ch CAM VERSION Register
Bit
31
30
29
28
27
26
25
CAM_VERSION
24
23
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YEAR[16:0]
R
YEAR
MONTH
DATE
6.15
14
13
12
11
MONTH[15:0]
R
10
9
8
7
6
5
4
3
DATE[15:0]
R
Year ASCII
Month ASCII
Date ASCII
Image DMA
6.15.1
2
1
0
fo
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15
General Description
Re
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Name
Type
Reset
Bit
Name
Type
Reset
Revision 1.0
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MT6228 GSM/GPRS Baseband Processor Data Sheet
Image DMA plays the role of moving image data between different image modules and memory.
interconnections around Image DMA. The major functions of Image DMA are list below.
Data movement
Color format conversion (RGB565
RGB888, YUV444
Data stream flow control on JPEG Encoder DMA
YUV420, YUV444
illustrates the
YUV422)
Auto double buffer switching for video capture/playback
Hardware handshaking with LCD DMA, and direct couple interface to LCD DMA
Image panning
Co
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Supporting BMP image file formats.
MT
K
Image DMA consists of nine DMA engines. They are JPEG Encode DMA, Video Encode DMA, Video Decode DMA,
Image Buffer Write 1 DMA (IBW1 DMA), Image Buffer Write 2 DMA (IBW2 DMA), Image Buffer Write 3 DMA
(IBW3 DMA), Image Buffer Write 4 DMA (IBW4 DMA), Image Buffer Read 1 DMA (IBR1 DMA), and Image Buffer
Read 2 DMA (IBR2 DMA). Each DMA engine has specific purposes. The details of each DMA engine are described in
following sections.
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Image Process Engine
By Pixel
YUV444
By Pixel
RGB888
Resizer
fo
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JPEG
Encoder
Image DMA
By Pixel
YUV444
Revision 1.0
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MT6228 GSM/GPRS Baseband Processor Data Sheet
By Block
LCD IF
0
By Pixel
By Pixel
LCD
Frame
Buffer
(RGB 565/
RGB888)
Image
Buffer
(RGB 565/
RGB888)
Image
Buffer
(RGB 565/
RGB 888/
BGR 888)
DC Mode
Figure 30 inter-connection around Image DMA
6.15.1.1
JPEG Encoder DMA
By Pixel
By Pixel
Re
lea
se
1
By Pixel
Video
Buffer
(YUV420)
JPEG
Encode
Line
Buffer
(YUV422/
YUV420)
The main function of JPEG Encoder DMA is to receive YUV 444 data from Image Engine by pixels and transmit
YUV422/ YUV420 data to JPEG Encoder by 8 X 8 blocks.
Flow Control
Co
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6.15.1.1.1
To achieve pixel to block conversion, line buffer must be given, and its line count must be multiple of 8. For better
performance, it’s recommended to have a minimum of 16 lines of buffer. For applications where images capturing from
the camera, because the data stream from camera can not be stopped, the number of lines must not be less than 16, (24
lines or more is recommended). Otherwise, data may be lost in the interface between the Image Signal Process and
Capture Resize modules.
6.15.1.1.2
Data format conversion
Since the JPEG encoder needs data of signed 2’s complement format. The JPEG Encoder DMA takes the responsibility
to handle the data format conversion. Each of Y, U, or V component values of input data is of 8-bit unsigned format,
which represents a value ranging from 0 to 255. The component value of the data is converted into 8-bit 2’s
complement format, which represents a value ranging from –128 to 127.
6.15.1.1.3
Padding
MT
K
For pictures whose frame size are not multiples of 16 X 8 blocks for YUV422 mode or 16 X 16 blocks for YUV420
mode, JPEG Encoder DMA takes the responsibility to handle the image boundary. In horizontal direction, JPEG
Encoder DMA automatically pads the last pixel of every line to the tail of the corresponding line until the number of
pixels in the line is multiple of 16. Similarly, JPEG Encoder pads the last line to the tail of the image frame until the
line count is multiples of 8 for YUV422 mode or 16 for YUV420 mode in vertical direction. An example of YUV422
mode is illustrated in . In this case, the original frame size is (16n + 13) X (8n + 6), which is not multiple of 16 X 8.
Therefore, three additional pixels are padded to the end of each line to make the pixel count multiple of 16. In the
vertical direction, two more lines are padded with last line to make line count to multiple of 8.
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16n+13
Original Frame
Padded Frame
Revision 1.0
Figure 31 Frame Padding for YUV422 mode
6.15.1.1.4
Gray Mode
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MT6228 GSM/GPRS Baseband Processor Data Sheet
JPEG Encoder DMA also supports Gray Image JPEG Encoding. That is, only Y components are transmitted to JPEG
Encoder for Encoding. For memory and bus bandwidth saving, U and V components are truncated before writing into
buffer memory. As a result, the memory size in gray mode will be half of what it is in YUV422 mode.
Furthermore, the frame padding is a little different from that in normal mode. JPEG Encode DMA will construct the
frame to the multiple of an 8 X 8 block instead of a 16 X 8 or 16 X 16 block in normal mode.
6.15.1.1.5
Auto-Restart
6.15.1.2
Co
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To overlap the Codec processing time with that of file system manipulations, an Auto-Restart mode is designed. JPEG
Encoder DMA automatically restarts itself to receive next frame without being re-configured and re-enabled by MCU.
This can enhance the Shot-to-Shot Delay performance a lot since the file system manipulations would take a long time.
JPEG Encoder DMA will not stop transfer until it is disabled by MCU. Note that associated settings must be
programmed in the Capture/Post Resize and other Image Engines as well.
Video Encode DMA
The main function of the Video Encode DMA is to move data from Capture Resize to Video Buffer. Video Buffer is
used to contain YUV420 image data for MPEG4/H.263 codec. It consists of three continuous memory buffers for Y, U,
and V component data.
For MPEG4/H.263 encoding, Video Encode DMA receives data from Capture Resize, and converts it into YUV420
format, and then writes into Y, U, V buffer separately. Software starts MPEG4/H.263 encoder after all of the frame data
are ready.
6.15.1.2.1
Auto-Restart
MT
K
To reduce MCU interrupt frequency, an Auto-Restart mode is designed. Video DMA automatically restarts itself to
receive next frame without being re-configured and re-enabled by MCU. This can save a lot of MCU time since the
MCU no longer needs to handle Image DMA at each frame boundary, which also makes the data stream smoother.
Usually, double buffer scheme are employed to smooth video encoding. Therefore, the second base address register is
provided in Video DMA to contain the second address. Video DMA automatically switches the base address between
the two addresses at every restart. For the case of single buffer scheme, the two base address registers have to be
programmed with the same address. Video DMA will not stop transfer until it is disabled by MCU. Note that associated
settings must be programmed in Capture Resize and Image Engine as well.
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6.15.1.3
Video Decode DMA
Revision 1.0
Ko
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MT6228 GSM/GPRS Baseband Processor Data Sheet
The main function of the Video Decode DMA is to move data from Video Buffer to Post Resize. Video Buffer is used
to contain YUV420 image data after MPEG4/H.263 codec. It consists of three continuous memory buffers for Y, U, and
V component data. Data format for the Post Resize is YUV444, and therefore color format conversion is needed during
data movement.
6.15.1.4
fo
r
For MPEG4/H.263 decoding, MPEG4/H.263 decoder writes out decoded data to video buffer, and Video Decode DMA
is then triggered by software to move data to the Post Resize.
Image Buffer Write 1, 2 DMA
6.15.1.4.1
Auto-Restart
Re
lea
se
The main function of IBW1, IBW2 DMA is to move RGB data from Image Engine to memory or LCD, and the format
of the written data is RGB565 or RGB888. IBW1 plays the role of saving the backup image. Whenever JPEG DMA,
Video DMA, or IBW2 DMA is dumping images, IBW1 can be enabled to dump a backup image simultaneously.
Besides, IBW1 also plays the role of writing local display under videophone scenario.
IBW1, IBW2 DMA can restart itself to receive next frame, and switch base address at every restart.
6.15.1.4.2
Hardware Handshake with LCD DMA
IBW1, IBW2 DMA issues interrupt along with the base address of the LCD buffer to LCD DMA at the end of frame
transfer. LCD DMA could start moving data into LCD based on the signals.
The advantage of hardware handshaking is to reduce interrupts to MCU. This could make system more efficient.
6.15.1.4.3
Direct Couple to LCD DMA
Co
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A more efficient and memory saving way to move frame data to LCD is through Direct Couple Interface. The interface
is between IBW1, IBW2 DMA and LCD, as depicted in , and consists of request, acknowledge, and 24-bit data bus. In
this mode, frame data skips the frame buffer and are written to LCD directly. LCD updates the data on the fly.
However this mode cannot work in camera preview. This is because LCD update could halt for a long time, and
therefore the next pixel data from the camera may not be captured in time. Thus, resulting in lost data.
6.15.1.4.4
Image Panning
IBW1, IBW2 DMA can grab a part of the image frame as a new image, as illustrated in . The advantage is that the
system does not need to prepare a large piece of memory to store the entire image frame just to show a small portion of
it. This can save memory usage, especially for large images. The detailed usage is shown in the register definition of
IMGDMA_IBW2_CON, IMGDMA_IBW2_CON.
6.15.1.4.5
Destination Pitch
To write the memory, a pitch register is defined to indicate the memory address jump per line for each base address.
This can save memory usage when writing a rectangular area of a LCD layer.
6.15.1.5
Image Buffer Write 3,4 DMA
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The main function of IBW3 DMA is to move data from a Pixel Image Engine to the DRZ, and the format is YUV444 or
RGB888. IBW3 provides the route for thumbnail image dumping. The main function of IBW4 DMA is to move data
from a Pixel Image Engine to the PRZ, and the format is YUV444 or RGB888. IBW4 provides the route for preview
scenario.
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6.15.1.5.1
Auto-Restart
IBW3 DMA can restart itself to receive next frame.
6.15.1.6
Image Buffer Read 1 DMA
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The main function of IBR1 DMA is to move RGB data from memory to Image Post Processor. The data format to
Image Post Processor is RGB888 and the data formats from memory can be RGB565, RGB888 and BGR888 (which
support BMP data format). The data placement in memory is illustrated in .
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With IBR1 DMA, RGB image data in memory can be directly used for video encoding, JPEG encoding, and image
panning.
RGB 565
Byte
14
13
12
11
10
9
8
R
RGB 888
7
6
5
4
3
2
1
0
Re
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15
G
B
Byte
15
R
G
B
14
13
12
11
10
9
12
11
10
9
BGR 888
8
7
6
5
4
3
2
1
8
7
6
5
4
3
2
1
0
Byte
15
14
13
0
6.15.1.7
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Figure 32 RGB data in memory
Image Buffer Read 2 DMA
The main function of IBR2 DMA is to read photo frame from memory, resize it to the capturing image size, look-up
palette table and overlay it onto the capturing image. The photo frame mask data format can be 1, 2, 4, 8-bpp color
index modes. A 256-entries in 24-bit YUV format palette provides a color index to color value lookup table.
6.15.1.7.1
Auto-Restart
IBR2 DMA can restart itself to read the same photo frame again and again while video capture scenario.
6.15.2
DMA Enabling Sequence
In general, the DMAs at the downstream of the data path must be enabled first. For instance, for Video capturing, the
data path is Camera module
Capture Resize
Image Engine
Video DMA
Video Buffer. Video DMA has
to be enabled before Image Processor, Capture Resize and Camera module.
The second example is video playback. The data path is Video Buffer
IBW2 DMA
Video DMA
Post Resize
IPP Engine
LCD frame buffer. IBW2 DMA has to be enabled before Post Resize and Image Engine and then
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Video DMA.
6.15.3
Register Definitions
Register Address
Register Function
Acronym
IMGDMA + 0000h
Image DMA Status Register
IMGDMA_STA
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IMGDMA + 0004h
Image DMA Interrupt Acknowledge Register
IMGDMA + 0100h
JPEG DMA Start Register
IMGDMA_JPEG_STR
IMGDMA + 0104h
JPEG DMA Control Register
IMGDMA_JPEG_CON
IMGDMA + 0108h
JPEG DMA Base Address Register
IMGDMA_JPEG_BSADDR
IMGDMA_JPEG_HSIZE
IMGDMA + 010Ch JPEG DMA Horizontal Size Register
JPEG DMA Vertical Size Register
IMGDMA_JPEG_VSIZE
JPEG DMA FIFO Length Register
IMGDMA_JPEG_FIFOLEN
IMGDMA + 0118h
JPEG Write Pointer Register
IMGDMA_JPEG_WRPTR
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IMGDMA + 0110h
IMGDMA + 0114h
IMGDMA_JPEG_WRHCNT
IMGDMA + 011Ch JPEG Write Horizontal Count Register
IMGDMA + 0120h
JPEG Write Vertical Count Register
IMGDMA_JPEG_WRVCNT
IMGDMA + 0124h
JPEG Read Pointer Register
IMGDMA_JPEG_RDPTR
IMGDMA + 0128h
JPEG Read Horizontal Count Register
IMGDMA_JPEG_RDHCNT
Re
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IMGDMA_JPEG_RDVCNT
IMGDMA + 012Ch JPEG Read Vertical Count Register
IMGDMA_JPEG_FFCNT
IMGDMA + 0130h
JPEG FIFO Line Count Register
IMGDMA + 0134h
JPEG FIFO Write Line Index Register
IMGDMA + 0138h
JPEG FIFO Read Line Index Register
IMGDMA + 0200h
Video Encode DMA Start Register
IMGDMA_JPEG_FFWRLIDX
IMGDMA_JPEG_FFRDLIDX
IMGDMA_VDOENC_STR
IMGDMA_VDOENC_CON
Video Encode DMA Control Register
Video Encode DMA Y Base Address 1 Register
IMGDMA_VDOENC_Y_BASE1
IMGDMA + 0214h
Video Encode DMA U Base Address 1 Register
IMGDMA_VDOENC_U_BASE1
IMGDMA + 0218h
Video Encode DMA V Base Address 1 Register
IMGDMA_VDOENC_V_BASE1
IMGDMA + 0220h
Video Encode DMA Y Base Address 2 Register
IMGDMA_VDOENC_Y_BASE2
IMGDMA + 0224h
Video Encode DMA U Base Address 2 Register
IMGDMA_VDOENC_U_BASE2
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IMGDMA + 0204h
IMGDMA + 0210h
IMGDMA + 0228h
Video Encode DMA V Base Address 2 Register
IMGDMA_VDOENC_V_BASE2
IMGDMA + 0230h
Video Encode DMA Horizontal Size Register
IMGDMA_VDOENC_HSIZE
IMGDMA + 0234h
Video Encode DMA Vertical Size Register
IMGDMA_VDOENC_VSIZE
IMGDMA + 0238h
Video Encode DMA Horizontal Count Register
IMGDMA_VDOENC_HCNT
IMGDMA + 023Ch Video Encode DMA Vertical Count Register
IMGDMA_VDOENC_VCNT
IMGDMA + 0280h
IMGDMA_VDODEC_STR
Video Decode DMA Start Register
IMGDMA + 0284h
Video Decode DMA Control Register
IMGDMA_VDODEC_CON
IMGDMA + 0290h
Video Decode DMA Y Base Address 1 Register
IMGDMA_VDODEC_Y_BASE1
IMGDMA + 0294h
Video Decode DMA U Base Address 1 Register
IMGDMA_VDODEC_U_BASE1
IMGDMA + 0298h
Video Decode DMA V Base Address 1 Register
IMGDMA_VDODEC_V_BASE1
IMGDMA_VDODEC_Y_BASE2
IMGDMA_VDODEC_U_BASE2
IMGDMA + 02A8h Video Decode DMA V Base Address 2 Register
IMGDMA_VDODEC_V_BASE2
IMGDMA + 02B0h Video Decode DMA Horizontal Size Register
IMGDMA_VDODEC_HSIZE
IMGDMA + 02B4h Video Decode DMA Vertical Size Register
IMGDMA_VDODEC_VSIZE
IMGDMA + 02B8h Video Decode DMA Horizontal Count Register
IMGDMA_VDODEC_HCNT
IMGDMA + 02BCh Video Decode DMA Vertical Count Register
IMGDMA_VDODEC_VCNT
IMGDMA + 0300h
Image Buffer Write DMA1 Start Register
IMGDMA_IBW1_STR
IMGDMA + 0304h
Image Buffer Write DMA1 Control Register
IMGDMA_IBW1_CON
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IMGDMA + 02A0h Video Decode DMA Y Base Address 2 Register
IMGDMA + 02A4h Video Decode DMA U Base Address 2 Register
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Image Buffer Write DMA1 Base Address 1 Register
IMGDMA_IBW1_BSADDR1
IMGDMA + 030Ch Image Buffer Write DMA1 Base Address 2 Register
IMGDMA_IBW1_BSADDR2
IMGDMA + 0310h
Image Buffer Write DMA1 Horizontal Size
IMGDMA_IBW1_HSIZE
IMGDMA + 0314h
Image Buffer Write DMA1 Vertical Size
IMGDMA_IBW1_VSIZE
IMGDMA + 0318h
Image Buffer Write DMA1 CLIP LR
IMGDMA_IBW1_CLIPLR
IMGDMA + 0308h
IMGDMA_IBW1_CLIPTB
Image Buffer Write DMA1 Destination Pitch 1
IMGDMA_IBW1_DPITCH1
IMGDMA + 0324h
Image Buffer Write DMA1 Destination Pitch2
IMGDMA_IBW1_DPITCH2
IMGDMA + 0328h
Image Buffer Write DMA1 Horizontal Count
IMGDMA_IBW1_HCNT
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IMGDMA + 031Ch Image Buffer Write DMA1 CLIP TB
IMGDMA + 0320h
IMGDMA_IBW1_VCNT
Image Buffer Write DMA2 Start Register
IMGDMA_IBW2_STR
IMGDMA + 0404h
Image Buffer Write DMA2 Control Register
IMGDMA_IBW2_CON
IMGDMA + 0408h
Image Buffer Write DMA2 Base Address 1 Register
IMGDMA_IBW2_BSADDR1
IMGDMA + 040Ch Image Buffer Write DMA2 Base Address 2 Register
IMGDMA_IBW2_BSADDR2
IMGDMA + 0410h
Image Buffer Write DMA2 Horizontal Size
IMGDMA_IBW2_HSIZE
IMGDMA + 0414h
Image Buffer Write DMA2 Vertical Size
IMGDMA_IBW2_VSIZE
IMGDMA + 0418h
Image Buffer Write DMA2 CLIP LR
IMGDMA_IBW2_CLIPLR
IMGDMA + 041Ch Image Buffer Write DMA2 CLIP TB
Re
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IMGDMA + 032Ch Image Buffer Write DMA1 Vertical Count
IMGDMA + 0400h
IMGDMA_IBW2_CLIPTB
IMGDMA + 0420h
Image Buffer Write DMA2 Destination Pitch 1
IMGDMA_IBW2_DPITCH1
IMGDMA + 0424h
Image Buffer Write DMA2 Destination Pitch2
IMGDMA_IBW2_DPITCH2
IMGDMA + 0428h
Image Buffer Write DMA2 Horizontal Count
IMGDMA_IBW2_HCNT
IMGDMA + 042Ch Image Buffer Write DMA2 Vertical Count
IMGDMA_IBW2_VCNT
IMGDMA + 0500h
IMGDMA_IBW3_STR
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Image Buffer Write DMA3 Start Register
IMGDMA + 0504h
Image Buffer Write DMA3 Control Register
IMGDMA_IBW3_CON
IMGDMA + 0510h
Image Buffer Write DMA3 Horizontal Size
IMGDMA_IBW3_HSIZE
IMGDMA + 0514h
Image Buffer Write DMA3 Vertical Size
IMGDMA_IBW3_VSIZE
IMGDMA + 0528h
Image Buffer Write DMA3 Horizontal Count
IMGDMA_IBW3_HCNT
IMGDMA + 052Ch Image Buffer Write DMA3 Vertical Count
IMGDMA_IBW3_VCNT
IMGDMA + 0580h
IMGDMA_IBW4_STR
Image Buffer Write DMA4 Start Register
IMGDMA + 0584h
Image Buffer Write DMA4 Control Register
IMGDMA_IBW4_CON
IMGDMA + 0590h
Image Buffer Write DMA4 Horizontal Size
IMGDMA_IBW4_HSIZE
IMGDMA + 0594h
Image Buffer Write DMA4 Vertical Size
IMGDMA_IBW4_VSIZE
IMGDMA + 05A8h Image Buffer Write DMA4 Horizontal Count
IMGDMA_IBW4_HCNT
IMGDMA + 05ACh Image Buffer Write DMA4 Vertical Count
IMGDMA_IBW4_VCNT
IMGDMA + 0600h
Image Buffer Read DMA1 Start Register
IMGDMA_IBR1_STR
IMGDMA + 0604h
Image Buffer Read DMA1 Control Register
IMGDMA_IBR1_CON
IMGDMA + 0608h
Image Buffer Read DMA1 Base Address Register
IMGDMA_IBR1_BSADDR
IMGDMA_IBR1_PXLNUM
IMGDMA + 0610h
Image Buffer Read DMA1 Remaining Pixels
IMGDMA_IBR1_PXLCNT
IMGDMA + 0700h
Image Buffer Read DMA2 Start Register
IMGDMA_IBR2_STR
IMGDMA + 0704h
Image Buffer Read DMA2 Control Register
IMGDMA_IBR2_CON
IMGDMA + 0708h
Image Buffer Read DMA2 Base Address Register
IMGDMA_IBR2_BSADDR
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IMGDMA + 060Ch Image Buffer Read DMA1 Number of Pixels
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IMGDMA_IBR2_CFG
IMGDMA + 070Ch Image Buffer Read DMA2 Configuration Register
IMGDMA + 0710h
Image Buffer Read DMA2 Horizontal Size
IMGDMA_IBR2_HSIZE
IMGDMA + 0714h
Image Buffer Read DMA2 Vertical Size
IMGDMA_IBR2_VSIZE
IMGDMA + 0718h
Image Buffer Read DMA2 Horizontal Count
IMGDMA_IBR2_HCNT
IMGDMA + 071Ch Image Buffer Read DMA2 Vertical Count
IMGDMA_IBR2_VCNT
IMGDMA + 0800h
IMGDMA + 0bfch
IMGDMA_PAL00~FF
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Image Buffer Read DMA2 Palette memory
Table 53 Tracer Registers
Bit
31
30
29
28
27
26
24
23
22
21
20
IBW4 IBW3 IBR2 IBR1 IBW2 IBW1
RUN RUN RUN RUN RUN RUN
Name
Type
Reset
Bit
25
IMGDMA_STA
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IMGDMA+000
Image DMA Status Register
0h
15
14
13
12
11
10
RO
0
9
RO
0
8
IBW4 IBW3
IT
IT
Name
Type
Reset
RO
0
RO
0
RO
0
7
IBR
2IT
RO
0
RO
0
6
RO
0
5
RO
0
4
IBR1 IBW2 IBW1
IT
IT
IT
RO
0
RO
0
RO
0
19
18
VDOD VDOE
EC NCR
RUN RUN
RO
RO
0
0
3
2
VDOE
VDOD
NCR
EC IT
IT
RO
RO
0
0
17
VDOE
NCW
RUN
RO
0
1
VDOE
NCW
IT
RO
0
16
JPEG
RUN
RO
0
0
JPEG
IT
RO
0
This register helps software program being well aware of the global status of Image DMA channels.
RUN
Interrupt status for DMA
2 No interrupt is generated.
3 An interrupt is pending and waiting for service.
DMA status
0 DMA is stopped or has completed the transfer already.
1 DMA is currently running.
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IT
IMGDMA+000
Image DMA Interrupt Acknowledge Register
4h
Bit
Name
Type
Bit
Name
Type
31
30
15
14
29
28
27
26
13
12
11
10
IMGDMA_ACKI
NT
25
24
23
22
21
20
9
8
7
6
5
4
WO
WO
WO
WO
18
3
2
VDOD VDOE
EC NCR
ACK ACK
WO WO WO
IBW4 IBW3 IBR2 IBR1 IBW2 IBW1
ACK ACK ACK ACK ACK ACK
WO
19
17
16
1
0
VDOE
JPEG
NCW
ACK
ACK
WO WO
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This register is used to acknowledge the current interrupt request associated with the completion event of a DMA
channel by software program. Note that this is a write-only register, and any read to it will return a value of “0”.
ACK
Interrupt acknowledge for the DMA channel
0 No effect
1 Interrupt request is acknowledged and should be relinquished.
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IMGDMA+010
JPEG DMA Start Register
0h
JPEG_STR
31
30
29
28
27
26
25
24
23
22
21
20
19
18
15
14
13
12
11
10
9
8
7
6
5
4
3
2
17
16
1
0
STR
R/W
0
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Bit
Name
Type
Reset
Bit
Name
Type
Reset
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STR
Start control for a DMA channel
0 stop DMA
1 activate DMA
IMGDMA+010
JPEG DMA Control Register
4h
Bit
Name
Type
Reset
Bit
31
30
29
28
27
26
25
24
15
14
13
12
11
10
9
8
Name
Re
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This register controls the activity of a DMA channel. Note that before setting STR to “1”, all the configurations shall be
done by giving proper values.
23
22
21
20
7
6
5
4
PSEL
R/W
0
18
17
16
3
2
1
0
AUTO MODE MODE
IT
1
0
RSTR
R/W R/W R/W R/W
0
0
0
0
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Type
Reset
19
JPEG_CON
AUTO RSTR Automatic restart. JPEG Encoder DMA automatically restarts while current frame is finished.
0 Disable
1 Enable
MODE Interrupt Enabling
00 YUV422
01 Gray
10 YUV420
11 reserved
IT
Interrupt Enabling
0 Disable
1 Enable
PSEL Pixel engine selection
0 Capture resize
1 Post resize
IMGDMA+010
JPEG DMA Base Address Register
8h
31
30
29
28
27
26
25
15
14
13
12
11
10
9
MT
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Bit
Name
Type
Bit
Name
Type
24
23
ADDR[31:16]
R/W
8
7
ADR[15:0]
R/W
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22
21
20
19
18
17
16
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4
3
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ADDR Base address of the JPEG DMA FIFO.
IMGDMA+010
JPEG DMA Horizontal Size Register
Ch
JPEG_HSIZE
31
30
29
28
27
26
25
24
23
22
21
20
19
18
15
14
13
12
11
10
9
8
7
HSIZE
R/W
6
5
4
3
2
HSIZE Horizontal dimension of image. 0 stands for 1 pixels, and n-1 stands for n pixels.
IMGDMA+011
JPEG DMA Vertical Size Register
0h
16
1
0
JPEG_VSIZE
Re
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Bit
Name
Type
Bit
Name
Type
17
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Bit
Name
Type
Bit
Name
Type
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31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
VSIZE
R/W
6
5
4
3
2
1
0
VSIZE Vertical dimension of image. 0 stands for 1 pixels, and n-1 stands for n pixels.
IMGDMA+011
JPEG DMA FIFO Length Register
4h
31
30
15
14
29
28
27
26
25
24
23
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Bit
Name
Type
Bit
Name
Type
13
12
11
10
9
8
7
FIFOLEN
R/W
JPEG_FIFOLEN
22
21
20
19
18
17
16
6
5
4
3
2
1
0
JPEG DMA FIFO Length must be the multiple of 8. The memory needed for a certain FIFO length is
HSIZE
× 16 × FIFOLEN × 2 bytes for YUV422 mode,
16
mode, and
HSIZE
× 16 × FIFOLEN × 3 bytes for YUV420
16
HSIZE
× 8 × FIFOLEN bytes for gray mode.
8
FIFOLEN
JPEG DMA FIFO Length. FIFOLEN must be the multiple of 8. recommended values are 24 for
YUV422 mode, 16 for YUV420 mode, and 16 for gray mode.
IMGDMA+011
JPEG Write Pointer Register
8h
31
30
15
14
29
28
27
26
13
12
11
10
MT
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Bit
Name
Type
Bit
Name
Type
WRPTR
25
24
23
22
WRPTR[31:16]
RO
9
8
7
6
WRPTR[15:0]
RO
JPEG_WRPTR
21
20
19
18
17
16
5
4
3
2
1
0
Write pointer to display current writing address.
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IMGDMA+011
JPEG Write Horizontal Count Register
Ch
Bit
Name
Type
Bit
Name
Type
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JPEG_WRHCNT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
15
14
13
12
11
10
9
8
7
WRHCNT
RO
6
5
4
3
2
17
16
1
0
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WRHCNT Displays the horizontal pixel count. This is a down-count counter. Hence this register reflects the
remaining pixels of a line.
IMGDMA+012
JPEG Write Vertical Count Register
0h
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
WRVCNT
RO
6
5
4
3
2
1
0
WRVCNT
Displays the vertical pixel count. This is a down-count counter. Hence this register reflects the remaining
lines.
IMGDMA+012
JPEG Read Pointer Register
4h
31
30
15
14
29
28
27
26
25
24
23
22
RDPTR[31:16]
RO
8
7
6
RDPTR[15:0]
RO
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Bit
Name
Type
Bit
Name
Type
Re
lea
se
Bit
Name
Type
Bit
Name
Type
JPEG_WRVCNT
13
12
11
10
9
JPEG_RDPTR
21
20
19
18
17
16
5
4
3
2
1
0
RDPTR Read pointer to display current reading address.
IMGDMA+012
JPEG Read Horizontal Count Register
8h
Bit
Name
Type
Bit
Name
Type
31
30
15
14
RDHCNT
JPEG_RDHCNT
29
28
27
26
25
24
23
22
21
20
19
18
17
16
13
12
11
10
9
8
7
RDHCNT
RO
6
5
4
3
2
1
0
Displays the horizontal pixel count. This is a down-count counter. Hence this register reflects the
remaining pixels of a line.
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IMGDMA+012
JPEG Read Vertical Count Register
Ch
Bit
Name
Type
Bit
Name
Type
JPEG_RDVCNT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
RDVCNT
RO
6
5
4
3
2
1
0
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RDVCNT
Displays the vertical pixel count. This is a down-count counter. Hence this register reflects the remaining
lines.
IMGDMA+013
JPEG FIFO Line Count Register
0h
JPEG_FFCNT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
15
14
13
12
11
10
9
8
7
FFCNT
RO
6
5
4
3
2
FFCNT
Displays the FIFO Line Count of JPEG FIFO.
31
30
29
28
27
26
25
24
15
14
13
12
11
10
9
8
0
23
22
21
20
19
18
17
16
7
6
5
4
3
2
1
0
Displays which FIFO line JPEG DMA is writing. YIDX = 1 ~ FIFOLEN.
IMGDMA+013
JPEG Read Line Index Register
8h
30
15
14
29
28
27
26
25
24
JPEG_FFRDLID
X
23
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31
13
12
11
10
9
8
7
22
21
20
19
18
17
16
6
5
4
3
2
1
0
YIDX
RO
YIDX
Displays which FIFO line JPEG DMA is reading, YIDX = 1 ~ FIFOLEN.
IMGDMA+020
Video Encode DMA Start Register
0h
Bit
Name
Type
Reset
Bit
Name
Type
Reset
1
YIDX
RO
YIDX
Bit
Name
Type
Bit
Name
Type
16
JPEG_FFWRLI
DX
Re
lea
se
IMGDMA+013
JPEG Write Line Index Register
4h
Bit
Name
Type
Bit
Name
Type
17
fo
r
Bit
Name
Type
Bit
Name
Type
Revision 1.0
Ko
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MT6228 GSM/GPRS Baseband Processor Data Sheet
31
30
15
14
VDOENC_STR
29
28
27
26
25
24
23
22
21
20
19
18
17
16
13
12
11
10
9
8
7
6
5
4
3
2
1
0
STR
R/W
0
This register controls the activity of a DMA channel. Note that before setting STR to “1”, all the configurations should
be done by giving proper values.
Start control for a DMA channel
0 stop DMA
1 activate DMA
MT
K
STR
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IMGDMA+020
Video Encode DMA Control Register
4h
VDOENC_CON
31
30
29
28
27
26
25
24
23
22
21
15
14
13
12
11
10
9
8
7
6
5
Name
PSEL RSEL
Type
Reset
R/W
0
R/W
0
20
19
18
4
3
2
AUTO
RD IT W2R
RSTR
R/W R/W R/W
0
0
0
17
16
1
0
WR IT
fo
r
Bit
Name
Type
Reset
Bit
Revision 1.0
Ko
nk
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MT6228 GSM/GPRS Baseband Processor Data Sheet
R/W
0
WR IT
WDMA Done Interrupt Enable. Interrupt issues when all of the transfers are done. For auto-restart mode,
interrupt issues at every restart.
Co
nf
id
en
tia
l
Re
lea
se
0 Disable
1 Enable
W2R WDMA hardware trigger to RDMA. While this function is enabled, Video Encode WDMA will write data to
video buffer first, and then a start pulse will issue to Video Encode RDMA to read back from the same buffer.
These data will pass through Resize to convert to LCD frame size.
0 Disable
1 Enable
RD IT RDMA Done Interrupt Enable.
0 Disable
1 Enable
AUTO RSTR Automatic restart. Video DMA automatically restarts while current frame is finished. Base address
will be automatically switched between VDO_BSADD1 and VDO_BSADDR2. For single buffer application,
please set VDO_BSADD1 and VDO_BSADDR2 with the same value.
0 Disable
1 Enable
RSEL RDMA output destination selection.
0 Post resize
1 Drop resize
PSEL WDMA input pixel engine selection
0 Capture resize
1 Post resize
IMGDMA+021
Video Encode Y Base Address 1 Register
0h
Bit
Name
Type
Bit
Name
Type
31
30
15
14
29
28
27
26
25
13
12
11
10
9
24
23
ADDR
R/W
8
7
ADDR
R/W
VDOENC_Y_BA
SE1
22
21
20
19
18
17
16
6
5
4
3
2
1
0
MT
K
ADDR First base address of video frame buffer.
IMGDMA+021
Video Encode U Base Address 1 Register
4h
Bit
Name
31
30
29
28
27
26
25
24
23
ADDR
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22
21
VDOENC_U_BA
SE1
20
19
18
17
16
MediaTek Inc. Confidential
Type
Bit
Name
Type
15
14
13
12
11
10
9
R/W
8
7
ADDR
R/W
6
5
4
3
2
ADDR First base address of video frame buffer.
IMGDMA+021
Video Encode VBase Address 1 Register
8h
31
30
29
28
27
26
25
15
14
13
12
11
10
9
24
23
ADDR
R/W
8
7
ADDR
R/W
22
21
20
6
5
4
19
31
30
29
28
27
26
25
15
14
13
12
11
10
9
ADDR
24
23
ADDR
R/W
8
7
ADDR
R/W
Second base address of video frame buffer.
30
15
14
ADDR
Co
nf
id
en
tia
l
31
29
28
27
26
25
13
12
11
10
9
24
23
ADDR
R/W
8
7
ADDR
R/W
1
0
21
20
19
18
17
16
6
5
4
3
2
1
0
VDOENC_U_BA
SE2
22
21
20
19
18
17
16
6
5
4
3
2
1
0
Second base address of video frame buffer.
31
30
15
14
ADDR
29
28
27
26
25
13
12
11
10
9
24
23
ADDR
R/W
8
7
ADDR
R/W
VDOENC_V_BA
SE2
22
21
20
19
18
17
16
6
5
4
3
2
1
0
Second base address of video frame buffer.
MT
K
IMGDMA+023
Video Encode Horizontal Size Register
0h
Bit
Name
Type
2
16
22
IMGDMA+022
Video Encode V Base Address 2 Register
8h
Bit
Name
Type
Bit
Name
Type
17
VDOENC_Y_BA
SE2
IMGDMA+022
Video Encode U Base Address 2 Register
4h
Bit
Name
Type
Bit
Name
Type
18
3
IMGDMA+022
Video Encode Y Base Address 2 Register
0h
Bit
Name
Type
Bit
Name
Type
0
VDOENC_V_BA
SE1
Re
lea
se
ADDR First base address of video frame buffer.
1
fo
r
Bit
Name
Type
Bit
Name
Type
Revision 1.0
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MT6228 GSM/GPRS Baseband Processor Data Sheet
31
30
29
28
27
26
25
24
23
423/616
22
VDOENC_HSIZ
E
21
20
19
18
17
16
MediaTek Inc. Confidential
Bit
Name
Type
15
14
13
12
11
10
9
8
7
6
5
4
3
29
28
27
26
25
24
23
22
21
20
15
14
13
12
11
10
9
8
7
6
5
4
SIZE
R/W
19
18
17
16
3
2
1
0
fo
r
30
Re
lea
se
Vertical dimension of a video frame. 1 stands for 1 pixel, and n stands for n pixels. Note that the vertical
size must be multiple of 16.
IMGDMA+023
Video Encode Horizontal Count Register
8h
31
30
29
28
27
26
25
24
15
14
13
12
11
10
9
8
COUNT
VDOENC_HCNT
23
22
21
20
19
18
17
16
7
6
5
4
COUNT
RO
3
2
1
0
Horizontal pixel count. 1 stands for 1 pixel, and n stands for n pixels.
31
30
15
14
COUNT
Co
nf
id
en
tia
l
IMGDMA+023
Video Encode Vertical Count Register
Ch
VDOENC_VCNT
29
28
27
26
25
24
23
22
21
20
19
18
17
16
13
12
11
10
9
8
7
6
5
4
COUNT
RO
3
2
1
0
Vertical pixel count. 1 stands for 1 pixel, and n stands for n pixels.
IMGDMA+028
Video Decode DMA Start Register
0h
31
30
15
14
VDODEC_STR
29
28
27
26
25
24
23
22
21
20
19
18
17
16
13
12
11
10
9
8
7
6
5
4
3
2
1
0
STR
R/W
0
MT
K
Bit
Name
Type
Reset
Bit
Name
Type
Reset
0
VDOENC_VSIZ
E
31
SIZE
Bit
Name
Type
Bit
Name
Type
1
Horizontal dimension of a video frame. 1 stands for 1 pixel, and n stands for n pixels. Note that the
horizontal size must be multiple of 16.
IMGDMA+023
Video Encode Vertical Size Register
4h
Bit
Name
Type
Bit
Name
Type
2
SIZE
R/W
SIZE
Bit
Name
Type
Bit
Name
Type
Revision 1.0
Ko
nk
a
MT6228 GSM/GPRS Baseband Processor Data Sheet
This register controls the activity of a DMA channel. Note that before setting STR to “1”, all the configurations should
be done by giving proper values.
STR
Start control for a DMA channel
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0
1
stop DMA
activate DMA
IMGDMA+028
Video Decode DMA Control Register
4h
VDODEC_CON
31
30
29
28
27
26
25
24
23
22
21
20
19
18
15
14
13
12
11
10
9
8
7
6
5
4
3
2
Name
Type
Reset
17
16
1
0
DONE
IT
R/W
0
fo
r
Bit
Name
Type
Reset
Bit
Revision 1.0
Ko
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MT6228 GSM/GPRS Baseband Processor Data Sheet
0
1
Disable
Enable
Re
lea
se
DONE IT DMA Done Interrupt Enabling. Interrupt issues when all of the transfers are done. For auto-restart mode,
interrupt issues at every restart.
IMGDMA+029
Video Decode Y Base Address 1 Register
0h
Bit
Name
Type
Bit
Name
Type
31
30
29
28
27
26
25
15
14
13
12
11
10
9
24
23
ADDR
R/W
8
7
ADDR
R/W
VDODEC_Y_BA
SE1
22
21
20
19
18
17
16
6
5
4
3
2
1
0
Co
nf
id
en
tia
l
ADDR First base address of video frame buffer.
IMGDMA+029
Video Decode U Base Address 1 Register
4h
Bit
Name
Type
Bit
Name
Type
31
30
15
14
29
28
27
26
25
13
12
11
10
9
24
23
ADDR
R/W
8
7
ADDR
R/W
VDODEC_U_BA
SE1
22
21
20
19
18
17
16
6
5
4
3
2
1
0
ADDR First base address of video frame buffer.
IMGDMA+029
Video Decode V Base Address 1 Register
8h
31
30
15
14
29
28
27
26
25
13
12
11
10
9
MT
K
Bit
Name
Type
Bit
Name
Type
24
23
ADDR
R/W
8
7
ADDR
R/W
VDODEC_V_BA
SE1
22
21
20
19
18
17
16
6
5
4
3
2
1
0
ADDR First base address of video frame buffer.
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IMGDMA+02A
Video Decode Y Base Address 2 Register
0h
31
30
29
28
27
26
25
15
14
13
12
11
10
9
ADDR
24
23
ADDR
R/W
8
7
ADDR
R/W
VDODEC_Y_BA
SE2
22
21
20
19
18
6
5
4
3
2
Second base address of video frame buffer.
IMGDMA+02A
Video Decode U Base Address 2 Register
4h
31
30
29
28
27
26
25
15
14
13
12
11
10
9
ADDR
24
23
ADDR
R/W
8
7
ADDR
R/W
22
Second base address of video frame buffer.
6
21
20
19
5
4
3
IMGDMA+02A
Video Decode V Base Address 2 Register
8h
31
30
29
28
27
26
25
15
14
13
12
11
10
9
ADDR
24
23
ADDR
R/W
8
7
ADDR
R/W
Co
nf
id
en
tia
l
Bit
Name
Type
Bit
Name
Type
0
18
17
16
2
1
0
22
21
20
19
18
17
16
6
5
4
3
2
1
0
Second base address of video frame buffer.
31
30
15
14
SIZE
VDODEC_HSIZ
E
29
28
27
26
25
24
23
22
21
20
19
18
17
16
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SIZE
R/W
Horizontal dimension of a video frame. 1 stands for 1 pixel, and n stands for n pixels. Note that the
horizontal size must be multiple of 16.
IMGDMA+02B
Video Decode Vertical Size Register
4h
31
30
29
MT
K
Bit
Name
Type
Bit
Name
Type
1
VDODEC_V_BA
SE2
IMGDMA+02B
Video Decode Horizontal Size Register
0h
Bit
Name
Type
Bit
Name
Type
16
VDODEC_U_BA
SE2
Re
lea
se
Bit
Name
Type
Bit
Name
Type
17
fo
r
Bit
Name
Type
Bit
Name
Type
Revision 1.0
Ko
nk
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MT6228 GSM/GPRS Baseband Processor Data Sheet
15
14
13
VDODEC_VSIZ
E
28
27
26
25
24
23
22
21
20
19
18
17
16
12
11
10
9
8
7
6
5
4
SIZE
R/W
3
2
1
0
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SIZE
Vertical dimension of a video frame. 1 stands for 1 pixel, and n stands for n pixels. Note that the vertical
size must be multiple of 16.
IMGDMA+02B
Video Decode Horizontal Count Register
8h
VDODEC_HCNT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
15
14
13
12
11
10
9
8
7
6
5
4
COUNT
RO
3
2
COUNT
Horizontal pixel count. 1 stands for 1 pixel, and n stands for n pixels.
IMGDMA+02B
Video Decode Vertical Count Register
Ch
31
30
29
28
27
26
25
24
15
14
13
12
11
10
9
8
COUNT
1
0
23
22
21
20
19
18
17
16
7
6
5
4
COUNT
RO
3
2
1
0
Vertical pixel count. 1 stands for 1 pixel, and n stands for n pixels.
IMGDMA+030
Image Buffer Write DMA1 Start Register
0h
31
30
15
14
29
28
27
26
25
24
23
Co
nf
id
en
tia
l
Bit
Name
Type
Reset
Bit
Name
Type
Reset
16
VDODEC_VCNT
Re
lea
se
Bit
Name
Type
Bit
Name
Type
17
fo
r
Bit
Name
Type
Bit
Name
Type
Revision 1.0
Ko
nk
a
MT6228 GSM/GPRS Baseband Processor Data Sheet
13
12
11
10
9
8
7
IBW1_STR
22
21
20
19
18
17
16
6
5
4
3
2
1
0
STR
R/W
0
This register controls the activity of a DMA channel. Note that before setting STR to “1”, all the configurations should
be done by giving proper value
STR
Start control for a DMA channel
0 stop DMA
1 activate DMA
IMGDMA+030
Image Buffer Write DMA1 Control Register
4h
31
30
15
14
29
28
27
26
25
13
12
11
10
9
MT
K
Bit
Name
Type
Reset
Bit
Name
Type
Reset
IT
24
23
22
21
8
7
6
5
PSEL PSEL
888M PAN
1
0
R/W R/W R/W R/W
0
0
0
0
IBW1_CON
20
19
18
17
16
4
3
2
1
0
AUTO
DC
LCD PITCH IT
RSTR
R/W R/W R/W R/W R/W
0
0
0
0
0
Interrupt Enabling
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Revision 1.0
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MT6228 GSM/GPRS Baseband Processor Data Sheet
CLIP_L
CLIP_R
Co
nf
id
en
tia
l
CLIP_T
Re
lea
se
fo
r
0 Disable
1 Enable
PITCH Destination pitch jump.
0 Disable
1 Enable
LCD
Signaling LCD DMA. Frame ready signal is issued at the beginning of frames in Direct Couple mode, and is
issued at the end of frames in Dual Buffer mode. Note that in the case of automatic restart plus direct couple
mode, this function must be enabled to trigger LCD DMA.
0 Disable
1 Enable
AUTO RSTR Automatic restart. IBW2 DMA automatically restarts itself while current frame is finished.
0 Disable
1 Enable
DC
Directly coupling to LCD DMA. Once this function is enabled, image data will dump to LCD DMA directly
instead of dumping to LCD frame buffer.
0 Disable
1 Enable
PAN
Picture panning. Once this function is enabled, only the pixels in the region specified by CLIP_L, CLIP_R,
CLIP_T, and CLIP_B are dumped. The pan window is defined as Figure 33.
CLIP_B
Figure 33 Picture Panning
MT
K
0 Disable
1 Enable
888M Output format control
0 RGB565
1 RGB888
PSEL Pixel engine selection
00 IPP 1
01 IPP 2
10 Capture resize
11 Post resize
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IMGDMA+030
Image Buffer Write DMA1 Base Address 1 Register
8h
Bit
Name
Type
Bit
Name
Type
31
30
29
28
27
26
25
15
14
13
12
11
10
9
24
23
ADDR
R/W
8
7
ADDR
R/W
IBW1_BSADDR
1
22
21
20
19
18
6
5
4
3
2
IMGDMA+030
Image Buffer Write DMA1 Base Address 2 Register
Ch
30
29
28
27
26
25
15
14
13
12
11
10
9
24
23
ADDR
R/W
8
7
ADDR
R/W
ADDR Second base address of the LCD frame buffer.
22
21
20
19
6
5
4
3
IMGDMA+031
Image Buffer Write DMA1 Horizontal Size Register
0h
31
30
29
28
27
26
25
24
15
14
13
12
11
10
9
8
17
16
2
1
0
IBW1_HSIZE
21
20
19
18
17
16
7
6
5
4
3
2
1
0
Horizontal size of a frame. 0 stands for 1 pixel, and n-1 stands for n pixels.
31
30
15
14
IBW1_VSIZE
29
28
27
26
25
24
23
22
21
20
19
18
17
16
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SIZE
R/W
SIZE
Vertical size of a frame. 0 stands for 1 pixel, and n-1 stands for n pixels.
IMGDMA+031
Image Buffer Write DMA1 Clip LR Register
8h
31
30
15
14
IBW1_CLIP_LR
29
28
27
26
25
24
23
22
21
20
19
18
17
16
13
12
11
10
9
8
7
RIGHT
R/W
6
5
4
3
2
1
0
MT
K
LEFT
RIGHT
18
22
IMGDMA+031
Image Buffer Write DMA1 Vertical Size Register
4h
Bit
Name
Type
Bit
Name
Type
0
SIZE
R/W
SIZE
Bit
Name
Type
Bit
Name
Type
1
23
Co
nf
id
en
tia
l
Bit
Name
Type
Bit
Name
Type
16
IBW1_BSADDR
2
Re
lea
se
31
17
fo
r
ADDR First base address of the LCD frame buffer.
Bit
Name
Type
Bit
Name
Type
Revision 1.0
Ko
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a
MT6228 GSM/GPRS Baseband Processor Data Sheet
Left boundary of a frame. 0 stands for the first pixel, and n-1 stands for the nth pixel.
Right boundary of a frame. 0 stands for the first pixel, and n-1 stands for the nth pixel.
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IMGDMA+031
Image Buffer Write DMA1 Clip TB Register
Ch
IBW1_CLIP_TB
31
30
29
28
27
26
25
24
23
22
21
20
19
18
15
14
13
12
11
10
9
8
7
BOTTOM
R/W
6
5
4
3
2
TOP
BOTTOM
17
16
1
0
Top boundary of a frame. 0 stands for the first pixel, and n-1 stands for the nth pixel.
Bottom boundary of a frame. 0 stands for the first pixel, and n-1 stands for the nth pixel.
fo
r
Bit
Name
Type
Bit
Name
Type
Revision 1.0
Ko
nk
a
MT6228 GSM/GPRS Baseband Processor Data Sheet
IMGDMA+032
Image Buffer Write DMA1 Destination Pitch1 Register IBW1_DPITCH1
0h
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
PITCH
R/W
6
5
4
3
2
1
0
PITCH
Re
lea
se
Bit
Name
Type
Bit
Name
Type
Line pitch in bytes corresponds to IBW2_BSADDR1.
IMGDMA+032
Image Buffer Write DMA1 Destination Pitch2 Register IBW1_DPITCH2
4h
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
PITCH
R/W
6
5
4
3
2
1
0
PITCH
Co
nf
id
en
tia
l
Bit
Name
Type
Bit
Name
Type
Line pitch in bytes corresponds to IBW2_BSADDR1.
IMGDMA+032
Image Buffer Write DMA1 Horizontal Count Register
8h
Bit
Name
Type
Bit
Name
Type
31
30
15
14
29
28
27
26
25
24
23
22
21
20
19
18
17
16
13
12
11
10
9
8
7
6
5
4
3
2
1
0
CNT
RO
CNT
Horizontal pixel count. 0 stands for 1 pixel, and n-1 stands for n pixels.
IMGDMA+032
Image Buffer Write DMA1 Vertical Count Register
Ch
31
30
29
MT
K
Bit
Name
Type
Bit
Name
Type
CNT
IBW1_HCNT
15
14
13
IBW1_VCNT
28
27
26
25
24
23
22
21
20
19
18
17
16
12
11
10
9
8
7
6
5
4
3
2
1
0
CNT
RO
Vertical line count. 0 stands for 1 line, and n-1 stands for n lines.
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MediaTek Inc. Confidential
Revision 1.0
IMGDMA+040
Image Buffer Write DMA2 Start Register
0h
IBW2_STR
31
30
29
28
27
26
25
24
23
22
21
20
19
18
15
14
13
12
11
10
9
8
7
6
5
4
3
2
17
16
1
0
STR
R/W
0
fo
r
Bit
Name
Type
Reset
Bit
Name
Type
Reset
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MT6228 GSM/GPRS Baseband Processor Data Sheet
STR
Start control for a DMA channel
0 stop DMA
1 activate DMA
Re
lea
se
This register controls the activity of a DMA channel. Note that before setting STR to “1”, all the configurations should
be done by giving proper value
IMGDMA+040
Image Buffer Write DMA2 Control Register
4h
Name
Type
Reset
IT
31
30
29
28
27
26
25
15
14
13
12
11
10
9
24
23
22
21
8
7
6
5
PSEL PSEL
888M PAN
1
0
R/W R/W R/W R/W
0
0
0
0
Co
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id
en
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Bit
Name
Type
Reset
Bit
20
19
IBW2_CON
18
17
16
4
3
2
1
0
AUTO
DC
LCD PITCH IT
RSTR
R/W R/W R/W R/W R/W
0
0
0
0
0
MT
K
Interrupt Enabling
0 Disable
1 Enable
PITCH Destination pitch jump.
0 Disable
1 Enable
LCD
Signaling LCD DMA. Frame ready signal is issued at the beginning of frames in Direct Couple mode, and is
issued at the end of frames in Dual Buffer mode. Note that in the case of automatic restart plus direct couple
mode, this function must be enabled to trigger LCD DMA.
0 Disable
1 Enable
AUTO RSTR Automatic restart. IBW2 DMA automatically restarts itself while current frame is finished.
0 Disable
1 Enable
DC
Directly coupling to LCD DMA. Once this function is enabled, image data will dump to LCD DMA directly
instead of dumping to LCD frame buffer.
0 Disable
1 Enable
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PAN Picture panning. Once this function is enabled, only the pixels in the region specified by HPITCH1, HPITCH2,
VPITCH1, and VPITCH2 are dumped. The PITCHs are defined as Figure 33.
fo
r
0 Disable
1 Enable
888M Output format control
0
RGB565
1
RGB888
PSEL Pixel engine selection
00 IPP 1
01 IPP 2
10 Capture resize
11 Post resize
Bit
Name
Type
Bit
Name
Type
31
30
29
28
27
26
25
15
14
13
12
11
10
9
IBW2_BSADDR
1
Re
lea
se
IMGDMA+040
Image Buffer Write DMA2 Base Address 1 Register
8h
24
23
ADDR
R/W
8
7
ADDR
R/W
ADDR First base address of the LCD frame buffer.
22
21
20
19
18
17
16
6
5
4
3
2
1
0
IMGDMA+040
Image Buffer Write DMA2 Base Address 2 Register
Ch
31
30
15
14
29
28
27
26
25
24
23
ADDR
R/W
8
7
ADDR
R/W
Co
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id
en
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Bit
Name
Type
Bit
Name
Type
13
12
11
10
9
IBW2_BSADDR
2
22
21
20
19
18
17
16
6
5
4
3
2
1
0
ADDR Second base address of the LCD frame buffer.
IMGDMA+041
Image Buffer Write DMA2 Horizontal Size Register
0h
Bit
Name
Type
Bit
Name
Type
31
30
15
14
IBW2_HSIZE
29
28
27
26
25
24
23
22
21
20
19
18
17
16
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SIZE
R/W
SIZE
Horizontal size of a frame. 0 stands for 1 pixel, and n-1 stands for n pixels.
MT
K
IMGDMA+041
Image Buffer Write DMA2 Vertical Size Register
4h
Bit
Name
Type
Bit
Name
IBW2_VSIZE
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SIZE
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Type
R/W
SIZE
Vertical size of a frame. 0 stands for 1 pixel, and n-1 stands for n pixels.
IMGDMA+041
Image Buffer Write DMA2 Clip LR Register
8h
IBW2_CLIP_LR
31
30
29
28
27
26
25
24
23
22
21
20
19
18
15
14
13
12
11
10
9
8
7
RIGHT
R/W
6
5
4
3
2
16
1
0
Left boundary of a frame. 0 stands for the first pixel, and n-1 stands for the nth pixel.
Right boundary of a frame. 0 stands for the first pixel, and n-1 stands for the nth pixel.
LEFT
RIGHT
Re
lea
se
IMGDMA+041
Image Buffer Write DMA2 Clip TB Register
Ch
Bit
Name
Type
Bit
Name
Type
17
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Bit
Name
Type
Bit
Name
Type
Revision 1.0
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MT6228 GSM/GPRS Baseband Processor Data Sheet
IBW2_CLIP_TB
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
BOTTOM
R/W
6
5
4
3
2
1
0
TOP
BOTTOM
Top boundary of a frame. 0 stands for the first pixel, and n-1 stands for the nth pixel.
Bottom boundary of a frame. 0 stands for the first pixel, and n-1 stands for the nth pixel.
Bit
Name
Type
Bit
Name
Type
31
30
15
14
PITCH
Co
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IMGDMA+042
Image Buffer Write DMA2 Destination Pitch1 Register IBW2_DPITCH1
0h
29
28
27
26
25
24
23
22
21
20
19
18
17
16
13
12
11
10
9
8
7
PITCH
R/W
6
5
4
3
2
1
0
Line pitch in bytes corresponds to IBW2_BSADDR1.
IMGDMA+042
Image Buffer Write DMA2 Destination Pitch2 Register IBW2_DPITCH2
4h
Bit
Name
Type
Bit
Name
Type
31
30
15
14
PITCH
29
28
27
26
25
24
23
22
21
20
19
18
17
16
13
12
11
10
9
8
7
PITCH
R/W
6
5
4
3
2
1
0
Line pitch in bytes corresponds to IBW2_BSADDR1.
MT
K
IMGDMA+042
Image Buffer Write DMA2 Horizontal Count Register
8h
Bit
Name
Type
Bit
IBW2_HCNT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
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Name
Type
CNT
RO
CNT
Horizontal pixel count. 0 stands for 1 pixel, and n-1 stands for n pixels.
IMGDMA+042
Image Buffer Write DMA2 Vertical Count Register
Ch
31
30
29
28
27
26
25
24
23
22
21
20
15
14
13
12
11
10
9
8
7
6
5
4
CNT
RO
CNT
Vertical line count. 0 stands for 1 line, and n-1 stands for n lines.
IBW2_VCNT
19
18
3
2
31
30
29
28
27
26
25
24
15
14
13
12
11
10
9
8
Re
lea
se
IMGDMA+050
Image Buffer Write DMA3 Start Register
0h
Bit
Name
Type
Reset
Bit
Name
Type
Reset
17
fo
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Bit
Name
Type
Bit
Name
Type
Revision 1.0
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MT6228 GSM/GPRS Baseband Processor Data Sheet
1
16
0
IBW3_STR
23
22
21
20
19
18
17
16
7
6
5
4
3
2
1
0
STR
R/W
0
This register controls the activity of a DMA channel. Note that before setting STR to “1”, all the configurations should
be done by giving proper value
Start control for a DMA channel
0 stop DMA
1 activate DMA
Co
nf
id
en
tia
l
STR
IMGDMA+050
Image Buffer Write DMA3 Control Register
4h
Bit
Name
Type
Reset
Bit
Name
Type
Reset
IT
31
30
15
14
29
28
27
26
25
13
12
11
10
9
24
23
8
7
PSEL PSEL
1
0
R/W R/W
0
0
IBW3_CON
22
21
20
19
18
17
16
6
5
4
3
AUTO
RSTR
R/W
0
2
1
0
IT
R/W
0
MT
K
Interrupt Enabling
0 Disable
1 Enable
AUTO RSTR Automatic restart. IBW2 DMA automatically restarts itself while current frame is finished.
0 Disable
1 Enable
PSEL Pixel engine selection
00 IPP 1
01 IPP 2
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10 Capture resize
11 Post resize
IMGDMA+051
Image Buffer Write DMA3 Horizontal Size Register
0h
31
30
29
28
27
26
25
24
23
22
21
20
19
18
15
14
13
12
11
10
9
8
7
6
5
4
3
2
SIZE
R/W
SIZE
Horizontal size of a frame. 0 stands for 1 pixel, and n-1 stands for n pixels.
31
30
29
28
27
26
25
24
15
14
13
12
11
10
9
8
0
22
21
20
19
18
17
16
7
6
5
4
3
2
1
0
Vertical size of a frame. 0 stands for 1 pixel, and n-1 stands for n pixels.
30
15
14
29
28
27
26
25
24
23
Co
nf
id
en
tia
l
31
13
12
11
10
9
8
7
IBW3_HCNT
22
21
20
19
18
17
16
6
5
4
3
2
1
0
CNT
RO
CNT
Horizontal pixel count. 0 stands for 1 pixel, and n-1 stands for n pixels.
IMGDMA+052
Image Buffer Write DMA3 Vertical Count Register
Ch
31
30
15
14
IBW3_VCNT
29
28
27
26
25
24
23
22
21
20
19
18
17
16
13
12
11
10
9
8
7
6
5
4
3
2
1
0
CNT
RO
CNT
Vertical line count. 0 stands for 1 line, and n-1 stands for n lines.
IMGDMA+058
Image Buffer Write DMA4 Start Register
0h
IBW4_STR
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
STR
R/W
MT
K
Bit
Name
Type
Reset
Bit
Name
Type
1
23
IMGDMA+052
Image Buffer Write DMA3 Horizontal Count Register
8h
Bit
Name
Type
Bit
Name
Type
16
SIZE
R/W
SIZE
Bit
Name
Type
Bit
Name
Type
17
IBW3_VSIZE
Re
lea
se
IMGDMA+051
Image Buffer Write DMA3 Vertical Size Register
4h
Bit
Name
Type
Bit
Name
Type
IBW3_HSIZE
fo
r
Bit
Name
Type
Bit
Name
Type
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Revision 1.0
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MT6228 GSM/GPRS Baseband Processor Data Sheet
Reset
0
This register controls the activity of a DMA channel. Note that before setting STR to “1”, all the configurations should
be done by giving proper value
Start control for a DMA channel
0 stop DMA
1 activate DMA
IMGDMA+058
Image Buffer Write DMA4 Control Register
4h
31
30
29
28
27
26
25
15
14
13
12
11
10
9
Name
Type
Reset
24
23
8
7
PSEL PSEL
1
0
R/W R/W
0
0
22
21
20
6
5
4
19
18
17
16
3
AUTO
RSTR
R/W
0
2
1
0
Re
lea
se
Bit
Name
Type
Reset
Bit
IBW4_CON
fo
r
STR
IT
IT
R/W
0
Co
nf
id
en
tia
l
Interrupt Enabling
0 Disable
1 Enable
AUTO RSTR Automatic restart. IBW2 DMA automatically restarts itself while current frame is finished.
0 Disable
1 Enable
PSEL Pixel engine selection
00 IPP 1
01 IPP 2
10 Capture resize
11 Post resize
IMGDMA+059
Image Buffer Write DMA4 Horizontal Size Register
0h
Bit
Name
Type
Bit
Name
Type
31
30
15
14
IBW4_HSIZE
29
28
27
26
25
24
23
22
21
20
19
18
17
16
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SIZE
R/W
SIZE
Horizontal size of a frame. 0 stands for 1 pixel, and n-1 stands for n pixels.
IMGDMA+059
Image Buffer Write DMA4 Vertical Size Register
4h
31
30
29
MT
K
Bit
Name
Type
Bit
Name
Type
SIZE
15
14
13
IBW4_VSIZE
28
27
26
25
24
23
22
21
20
19
18
17
16
12
11
10
9
8
7
6
5
4
3
2
1
0
SIZE
R/W
Vertical size of a frame. 0 stands for 1 pixel, and n-1 stands for n pixels.
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IMGDMA+05A
Image Buffer Write DMA4 Horizontal Count Register
8h
31
30
29
28
27
26
25
24
23
22
21
20
19
18
15
14
13
12
11
10
9
8
7
6
5
4
3
2
CNT
RO
CNT
Horizontal pixel count. 0 stands for 1 pixel, and n-1 stands for n pixels.
IMGDMA+05A
Image Buffer Write DMA4 Vertical Count Register
Ch
31
30
29
28
27
26
25
24
15
14
13
12
11
10
9
8
23
22
21
20
7
6
5
4
16
1
0
19
3
18
17
16
2
1
0
CNT
RO
CNT
Vertical line count. 0 stands for 1 line, and n-1 stands for n lines.
IMGDMA+060
Image Buffer Read DMA1 Start Register
0h
31
30
29
28
27
26
25
24
15
14
13
12
11
10
9
8
IBR1_STR
23
22
21
20
19
18
17
16
7
6
5
4
3
2
1
0
STR
R/W
0
Co
nf
id
en
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l
Bit
Name
Type
Reset
Bit
Name
Type
Reset
17
IBW4_VCNT
Re
lea
se
Bit
Name
Type
Bit
Name
Type
IBW4_HCNT
fo
r
Bit
Name
Type
Bit
Name
Type
Revision 1.0
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MT6228 GSM/GPRS Baseband Processor Data Sheet
This register controls the activity of a DMA channel. Note that before setting STR to “1”, all the configurations should
be done by giving proper values.
STR
Start control for a DMA channel
0 stop DMA
1 activate DMA
IMGDMA+060
Image Buffer Read DMA1 Control Register
4h
Bit
Name
Type
Reset
Bit
Name
31
30
15
14
29
28
27
26
25
24
23
22
21
20
19
13
12
11
10
9
8
7
6
5
4
3
MT
K
Type
Reset
IT
IBR1_CON
18
17
2
1
ORDE
FMT
R
R/W R/W
0
0
16
0
IT
R/W
0
Interrupt Enabling
0 Disable
1 Enable
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Revision 1.0
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MT6228 GSM/GPRS Baseband Processor Data Sheet
FMT
Data format
0 RGB565
1 RGB888
ORDER
Data order
0 BGR888, from MSB to LSB.
1 RGB888, from MSB to LSB.
31
30
29
28
27
26
25
15
14
13
12
11
10
9
24
23
ADDR
R/W
8
7
ADDR
R/W
22
21
20
6
5
4
19
18
17
16
3
2
1
0
Re
lea
se
Bit
Name
Type
Bit
Name
Type
IBR1_BSADDR
fo
r
IMGDMA+060
Image Buffer Read DMA1 Base Address Register
8h
ADDR Base address of the image buffer.
IMGDMA+060
Image Buffer Read DMA1 Number of Pixels Register
Ch
Bit
Name
Type
Bit
Name
Type
31
30
29
28
27
26
25
15
14
13
12
11
10
9
NUM
24
23
NUM
R/W
8
7
NUM
R/W
22
21
20
19
18
17
16
6
5
4
3
2
1
0
Number of pixels of the transferred image. 0 represents 1 pixel, and n-1 represents n pixels.
31
30
15
14
COUNT
Co
nf
id
en
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l
IMGDMA+061
Image Buffer Read DMA1 Remaining Pixels Register
0h
Bit
Name
Type
Bit
Name
Type
IBR1_PXLNUM
29
28
27
26
25
13
12
11
10
9
24
23
COUNT
RO
8
7
COUNT
RO
IBR1_PXLCNT
22
21
20
19
18
17
16
6
5
4
3
2
1
0
Pixel count. 0 represents 1 pixel, and n-1 represents n pixels.
IMGDMA+070
Image Buffer Read DMA2 Start Register
0h
31
30
15
14
29
28
27
26
25
24
23
22
21
20
19
18
17
16
13
12
11
10
9
8
7
6
5
4
3
2
1
0
STR
R/W
0
MT
K
Bit
Name
Type
Reset
Bit
Name
Type
Reset
IBR2_STR
This register controls the activity of a DMA channel. Note that before setting STR to “1”, all the configurations should
be done by giving proper values.
STR
Start control for a DMA channel
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0
1
stop DMA
activate DMA
IMGDMA+070
Image Buffer Read DMA2 Control Register
4h
31
30
29
28
27
26
25
24
23
22
21
15
14
13
12
11
10
9
8
7
6
5
Name
PSEL
Type
Reset
R/W
0
IBR2_CON
20
19
18
17
16
4
3
2
1
0
PALE AUTO MODE MODE
IT
N RSTR
1
0
R/W R/W R/W R/W R/W
0
0
0
0
0
fo
r
Bit
Name
Type
Reset
Bit
Revision 1.0
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MT6228 GSM/GPRS Baseband Processor Data Sheet
IT
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Re
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se
Interrupt Enabling
0 Disable
1 Enable
MODE Interrupt Enabling
00 1-bpp mode
01 2-bpp mode
10 4-bpp mode
11 8-bpp mode
AUTO RSTR Automatic restart. IBR2 DMA automatically restarts itself while current frame is finished.
0 Disable
1 Enable
PALEN
Photo frame palette Enabling. Please set this bit before any operation with the palette memory.
0 Disable.
1 Enable.
PSEL Pixel engine selection
0 Capture Resize.
1 Post Resize.
IMGDMA+070
Image Buffer Read DMA2 Base Address Register
8h
Bit
Name
Type
Bit
Name
Type
31
30
15
14
29
28
27
26
25
13
12
11
10
9
24
23
ADDR
R/W
8
7
ADDR
R/W
IBR2_BSADDR
22
21
20
19
18
17
16
6
5
4
3
2
1
0
ADDR Base address of the photo frame.
IMGDMA+070
Image Buffer Read DMA2 Configuration Register
Ch
31
30
29
MT
K
Bit
Name
Type
Bit
Name
Type
15
14
13
28
IBR2_CFG
27
26
25
24
23
22
21
20
19
18
17
16
12
11
KEY
R/W
10
9
8
7
6
5
VRATIO
R/W
4
3
2
1
HRATIO
R/W
0
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KEY
Transparent color key for overlay function.
VRATIO
Horizontal scaling ratio.
HRATIO
Vertical scaling ratio.
IMGDMA+071
Image Buffer Read DMA2 Horizontal Size Register
0h
IBR2_HSIZE
31
30
29
28
27
26
25
24
23
22
21
20
19
18
15
14
13
12
11
10
9
8
7
6
5
4
3
2
SIZE
R/W
SIZE
Horizontal size of the photo frame.
31
30
29
28
27
26
25
24
15
14
13
12
11
10
9
8
Re
lea
se
IMGDMA+071
Image Buffer Read DMA2 Vertical Size Register
4h
Bit
Name
Type
Bit
Name
Type
Vertical size of the photo frame.
0
23
22
21
20
19
18
17
16
7
6
5
4
3
2
1
0
30
15
14
29
28
27
26
25
24
23
Co
nf
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en
tia
l
31
13
12
11
10
9
8
7
IBR2_HCNT
22
21
20
19
18
17
16
6
5
4
3
2
1
0
CNT
RO
CNT
Horizontal pixel count. 0 stands for 1 pixel, and n-1 stands for n pixels.
IMGDMA+071
Image Buffer Read DMA2 Vertical Count Register
Ch
31
30
15
14
IBR2_VCNT
29
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25
24
23
22
21
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19
18
17
16
13
12
11
10
9
8
7
6
5
4
3
2
1
0
CNT
RO
CNT
Vertical line count. 0 stands for 1 line, and n-1 stands for n lines.
IMGDMA+0BF
Ch
31
30
IMGDMA_PAL0
0
Image Buffer Read DMA2 Palette Register 00~FF
MT
K
IMGDMA+080
0h
Bit
Name
1
IBR2_VSIZE
IMGDMA+071
Image Buffer Read DMA2 Horizontal Count Register
8h
Bit
Name
Type
Bit
Name
Type
16
SIZE
R/W
SIZE
Bit
Name
Type
Bit
Name
Type
17
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Name
Type
Bit
Name
Type
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~FF
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Type
Bit
Name
Type
R/W
15
14
13
12
11
10
9
8
7
COLOR
R/W
6
5
4
3
COLOR [23:0] Palette entry color value in YUV format.
1
0
Image Engine
fo
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6.16
2
Revision 1.0
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MT6228 GSM/GPRS Baseband Processor Data Sheet
The Image Engine is used to manipulate image adjustments and a variety of filtering effects. It works inside the DMA
architecture, which minimizes the intervention of the CPU. The engine can directly access the external and internal
memories and provide a large extent of flexibility for system performance consideration.
Re
lea
se
The function of the engine basically contains two categories: pixel adjustment and filtering effect.
Pixel adjustment includes brightness, contrast, and hue adjustment, color adjustment, and gamma correction. These
effects are integrated on both the encoding and decoding path of image and video material. It can provide on-the-fly
manipulation on these raw materials. For camera preview and capture, it can perform the effects on the incoming image
frame immediately, and output to both frame buffer for display and image buffer for image compression. For video
playback, it can perform the effects on the decoded frame immediately and output to the frame buffer for display.
The filtering effect includes linear and non-linear (ranking) effects. The linear filtering provides blur and sharpening
effects with programmable mask design. The non-linear filtering provides ranking filter to emulate noise reduction,
dilation and erosion effects. We can also implement other artistic effects by performing multi-pass filtering with
combination of a variety of effects.
6.16.1
Register Definitions
Register Address
IMG+0000h
IMG+0004h
IMG+0008h
IMG+000Ch
IMG+0010h
IMG+0100h
IMG+0104h
IMG+0108h
Co
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The image Engine includes three independent sub image engines. The first sub image engine, IPP1, is in charge of the
main functions of the engine (pixel adjustment and filtering effect). The second sub image engine, IPP2, only performs
YUV to RGB color conversion. This sub engine can be used to output the RGB data in the image compression or
videophone. The third sub image engine, IPP3, mainly performs RGB to YUV color space conversion and then output
to Post Resizer.
Register Function
Acronym
Image flow control register
IMGPROC_IMAGE_CON
Control register
IMGPROC_CON
Interrupt enable register
IMGPROC_INTREN
Interrupt status register
IMGPROC_INTR
Status register
IMGPROC_STATUS
Hue adjustment coefficient C11
IMGPROC_HUE11
Hue adjustment coefficient C12
IMGPROC_HUE12
Hue adjustment coefficient C21
IMGPROC_HUE21
Hue adjustment coefficient C22
IMGPROC_HUE22
Saturation adjustment coefficient
IMGPROC_SAT
IMG+0120h
Brightness adjustment coefficient B1
IMGPROC_BRIADJ1
IMG+0124h
Brightness adjustment coefficient B2
IMGPROC_BRIADJ2
IMG+0128h
Contrast adjustment coefficient
IMGPROC_CONADJ
MT
K
IMG+010Ch
IMG+0110h
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Colorize effect coefficient
Colorize effect coefficient
IMGPROC_COLORIZEV
IMG+0140h
Mask coefficient C11
IMGPROC_MASK11
IMG+0144h
Mask coefficient C12
IMGPROC_MASK12
IMG+0148h
Mask coefficient C13
IMGPROC_MASK13
IMG+014Ch
Mask coefficient C21
IMGPROC_MASK21
IMG+0150h
Mask coefficient C22
IMGPROC_MASK22
IMG+0154h
Mask coefficient C23
IMGPROC_MASK23
IMG+0158h
Mask coefficient C31
IMGPROC_MASK31
IMG+015Ch
Mask coefficient C32
IMGPROC_MASK32
IMG+0160h
Mask coefficient C33
IMGPROC_MASK33
IMG+0164h
Mask down-scaling coefficient
IMGPROC_SCALE
IMG+0170h
Gamma correction offset for segment 0
IMGPROC_GAMMA_OFF0
IMG+0174h
Gamma correction offset for segment 1
IMG+0178h
Gamma correction offset for segment 2
IMG+017Ch
Gamma correction offset for segment 3
IMG+0180h
Gamma correction offset for segment 4
IMG+0184h
Gamma correction offset for segment 5
IMG+0188h
Gamma correction offset for segment 6
IMG+018Ch
Gamma correction offset for segment 7
IMG+0190h
Gamma correction slope for segment 0
IMG+0194h
Gamma correction slope for segment 1
IMG+0198h
Gamma correction slope for segment 2
IMG+019Ch
IMG+01A0h
IMG+01A4h
IMG+01A8h
IMG+01ACh
IMG+01B0h
IMG+0200h
IMG+0204h
IMG+0208h
IMG+020Ch
IMG+0210h
IMG+0214h
IMG+0220h
IMG+0224h
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IMG+0130h
IMG+0134h
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IMGPROC_COLORIZEU
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IMGPROC_GAMMA_OFF1
IMGPROC_GAMMA_OFF2
IMGPROC_GAMMA_OFF3
IMGPROC_GAMMA_OFF4
IMGPROC_GAMMA_OFF5
IMGPROC_GAMMA_OFF6
IMGPROC_GAMMA_OFF7
IMGPROC_GAMMA_SLP0
IMGPROC_GAMMA_SLP1
IMGPROC_GAMMA_SLP2
Gamma correction slope for segment 3
IMGPROC_GAMMA_SLP3
Gamma correction slope for segment 4
IMGPROC_GAMMA_SLP4
Gamma correction slope for segment 5
IMGPROC_GAMMA_SLP5
Gamma correction slope for segment 6
IMGPROC_GAMMA_SLP6
Gamma correction slope for segment 7
IMGPROC_GAMMA_SLP7
Gamma correction control register
IMGPROC_GAMMA_CON
Color adjustment offset x for red segment 1
IMGPROC_COLOR1R_OFFX
Color adjustment offset x for red segment 2
IMGPROC_COLOR2R_OFFX
Color adjustment offset x for green segment 1
IMGPROC_COLOR1G_OFFX
Color adjustment offset x for green segment 2
IMGPROC_COLOR2G_OFFX
Color adjustment offset x for blue segment 1
IMGPROC_COLOR1B_OFFX
Color adjustment offset x for blue segment 2
IMGPROC_COLOR2B_OFFX
Color adjustment offset y for red segment 1
IMGPROC_COLOR1R_OFFY
Color adjustment offset y for red segment 2
IMGPROC_COLOR2R_OFFY
Color adjustment offset y for green segment 1
IMGPROC_COLOR1G_OFFY
Color adjustment offset y for green segment 2
IMGPROC_COLOR2G_OFFY
IMG+0230h
Color adjustment offset y for blue segment 1
IMGPROC_COLOR1B_OFFY
IMG+0234h
Color adjustment offset y for blue segment 2
IMGPROC_COLOR2B_OFFY
IMG+0240h
Color adjustment slope for red segment 0
IMGPROC_COLOR1G_SLP
MT
K
IMG+0228h
IMG+022Ch
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Color adjustment slope for red segment 1
IMGPROC_COLOR1G_SLP
IMG+0248h
Color adjustment slope for red segment 2
IMGPROC_COLOR2G_SLP
IMG+0250h
Color adjustment slope for red segment 0
IMGPROC_COLOR1G_SLP
IMG+0254h
Color adjustment slope for red segment 1
IMGPROC_COLOR1G_SLP
IMG+0258h
Color adjustment slope for red segment 2
IMGPROC_COLOR2G_SLP
IMG+0260h
Color adjustment slope for red segment 0
IMGPROC_COLOR1G_SLP
IMG+0264h
Color adjustment slope for red segment 1
IMGPROC_COLOR1G_SLP
IMG+0268h
Color adjustment slope for red segment 2
IMGPROC_COLOR2G_SLP
IMG+0304h
Image frame width register
IMGPROC_IMGWIDTH
IMG+0308h
Image frame height register
IMGPROC_IMGHEIGHT
IMG+030Ch
Image frame source start address
IMGPROC_ADDR_SRC
IMG+0310h
Image frame destination start address
IMGPROC_ADDR_DST
IMG+0314h
Image frame filtering dummy pixel
IMGPROC_DUMMYPXL
IMG+0318h
RGB to YUV source select
IMG+031Ch
Thumbnail output enable
IMG+0320h
Image engine process enable
Re
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IMG+0244h
IMGPROC_R2Y_SRC
IMGPROC_TNL_EN
IMGPROC_EN
Table 54 Image Engine Registers
Bit
Name
Type
Reset
15
IMGPROC_IMA
GE_CON
Image Engine image flow control register
14
13
GMODE
R/W
0
12
11
10
9
MASK
R/W
0
8
7
6
5
RGB GMA CLR
R/W R/W R/W
0
0
0
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IMG+0000h
4
INV
R/W
0
3
CBA
R/W
0
2
1
HSA
R/W
0
0
This register is used to define which effects are to be applied on the video stream or on the stand-alone image. The user
can simply set this register to 0 if intended to bypass Image Engine.
The MSB 4 bits controls the operating mode and image flow of the engine. They should be set prior to enabling the
respective functions; and when all are equal to 0, no operation will take effect.
The MASK field defines which mask filtering effect is to be applied. The RGB format (565/888) of image data can be
both supported by the RGB control bit. The effects comprise of linear and non-linear effects. Some linear effects, such
as Low-pass, High-pass, un-sharpening effects, should be associated with the mask table; therefore the user should
program the mask coefficients. The LP (low-pass) filter provides smoothing effects. Since it is supposed to get
un-biased data, the convolution will be normalized to its original intensity. The HP (high-pass) filter, which provides
sharpening effects, does not necessarily produce un-biased data. We provide two HP filters, one with scaling factor and
the other without. Depending on what mask type is defined, the result may reveal only edge information or may keep
the average intensity to achieve the sharpening effects. We recommend using symmetrical form of mask.
MT
K
In addition to 3x3 masks, 5x5 and 7x7 masks are also provided. But only the blur effects are provided for the later two
effects. The user does not have to program the mask coefficients.
The LSB 7 bits controls all the pixel adjustment effect.
For gamma correction and color adjustment, which are to be performed on RGB color space, the Image Engine
provides piece-wise linear programming mechanism. The user should know the slope and offset of respective segments.
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Color invert effect, performed on YUV or RGB color spaces, provides negative film effects.
Contrast and brightness, hue and saturation effects are to be performed on YUV color space. Although, the user can
also do post-processing on the image prepared in RGB form. The Image Engine can convert it into YUV space for
those operations.
MT
K
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GMODE
Graph mode. The field defines the image flow in each case.
1000 Image Encode mode. (RGB to YUV) In this mode, the Image Engine performs the color space
conversion from RGB color space to YUV color space. This mode is mainly used in image encoding,
such as JPEG encoding. IPP2 path can be enabled to support the thumbnail RGB data format. In this
mode, we assume no image effects are to be applied.
0101 IMGPROC mode. (RGB to YUV and YUV to RGB) In this mode, the Image Engine applies image
effects on the stand-alone image. The data source and destination is supposed to be in RGB color
space. In this mode, the user should program image size and related information on image DMA. The
image DMA retrieves image, performs image effects on Image Engine, and then writes to the memory.
This mode can also apply on GIF/PNG decoding.
0011 MPEG mode. (YUV to RGB) In this mode, the image is converted from YUV color space to RGB
color space in video showing. This mode is mainly used for video mode.
0010 Capture mode. (YUV to RGB and YUV to RGB) In this mode, the captured image in YUV color
space and performed color space conversion for thumbnail output. This mode is mainly used for
image capture. This mode can be applied on videophone mode. Thumbnail path can be enabled.
0001 Preview mode. (YUV to RGB) In this mode, the Image Engine performs the color space conversion
from YUV color space to RGB color space. This mode is mainly used for preview, image playback.
MASK Mask filtering effect enabling control. (Source and destination image are both in memory)
0101 Linear LP (low-pass) filtering effect enable. Mask coefficients required.
0110 Linear HP (high-pass) filtering effect enable. Mask coefficients required.
0111
Linear HP filtering (with scale down) effect enable. Mask coefficients required.
1001 Blur effect enable. (5x5 mask)
1010 More blur effect enable. (7x7 mask)
1011 Un-sharp mask effect enable. Mask coefficients required.
1100 Maximum ranking (dilation) filter effect enable
1101 Median ranking filter effect enable
1110 Minimum ranking (erosion) filter effect enable
RGB
RGB565/888 selection for filter path (only for filtering effect)
0
RGB565
1
RGB888
GMA Gamma correction enable bit
CLR
Color adjustment enable bit
INV
Color invert enable bit
CBA Contrast and brightness adjustment enable bit
HSA Hue and saturation adjustment enable
001
Gray-scale effect enable
010
Colorize effect enable
101
Hue adjustment enable
110
Saturation adjustment enable
111
Hue and saturation adjustment enable
IMG+0004h
Bit
15
Mask filtering Control register
14
13
12
11
10
9
8
IMGPROC_CON
7
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2
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Name
INIT
Type
Reset
WO
0
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STAR
T
WO WO
0
0
STOP
This register is used to control the filtering process and coefficients setting.
INIT
Writing logic-1 resets hue, saturation, brightness, and contrast adjusting coefficients. The flag is write-only.
STOP Writing logic-1 stops the image filter processing. The flag is write-only.
START Writing logic-1 starts the image filter processing. The flag is write-only.
15
14
13
12
11
10
9
8
7
6
5
4
fo
r
Bit
Name
Type
Reset
IMGPROC_INTR
EN
Interrupt enable register
3
2
Re
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IMG+0008h
1
0
EN
R/W
0
This register is the interrupt enable control register. To enable the interrupt, the flag should be set to be 1.
EN
Interrupt enable flag.
IMG +000Ch
Bit
Name
Type
Reset
15
14
Interrupt status register
13
12
11
10
9
IMGPROC_INTR
8
7
6
5
4
3
2
1
0
INTR
RC
0
This register is the interrupt status register. The core set the flag to be 1 to represent the interrupt is asserted. Reading
this register will clear the interrupt.
Interrupt status flag. The flag is read-clear.
IMG +0010h
Bit
Name
Type
Reset
15
14
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INTR
Status register
13
12
11
10
9
8
7
IMGPROC_STS
6
5
4
3
2
1
0
BUSY
RO
0
This register is the status register. The user could poll this register to see if the filtering process is ready or not. The flag
is read-only.
BUSY Filtering is in process.
IMG+0100h
Bit
Name
Type
Reset
15
14
13
15
12
11
10
9
8
7
6
5
4
3
14
13
12
11
10
9
8
7
2
1
0
C11
R/W
40h
IMGPROC_HUE
12
Hue adjustment coefficient C12
MT
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IMG+0104h
Bit
Name
Type
Reset
IMGPROC_HUE
11
Hue adjustment coefficient C11
6
5
4
3
2
1
0
C12
R/W
0
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IMG+0108h
15
14
13
12
11
10
9
8
7
6
5
4
3
2
C21
R/W
0
IMG+010Ch
Bit
Name
Type
Reset
IMGPROC_HUE
21
Hue adjustment coefficient C21
15
14
12
11
10
9
8
0
IMGPROC_HUE
22
Hue adjustment coefficient C22
13
1
7
6
5
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Name
Type
Reset
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4
3
2
1
0
C22
R/W
40h
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This register controls the parameter of hue adjustment for the image. The effect is performed on the U and V
component of YUV color space. The user should specify the coefficients that form the transformation matrix. The
formula is listed as follows:
u0
C11 C12 ui
=
⋅
vo
C 21 C 22 vi
C11 = 64 cosθ , C12 = 64 sin θ , C 21 = −64 sin θ , C 22 = 64 cosθ
where
The coefficients are in 2’s complement format and range from C0h to 40h (from –64 to 64 in decimal, while 64 is
normalized to 1 corresponding to cosine values). Any value beyond this range is invalid.
C11
C12
C21
C22
The coefficient C11 of the transformation matrix in 2’s complement format.
The coefficient C12 of the transformation matrix in 2’s complement format.
The coefficient C21 of the transformation matrix in 2’s complement format.
The coefficient C22 of the transformation matrix in 2’s complement format.
IMG+0110h
Bit
Name
Type
Reset
Co
nf
id
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l
For example, to rotate the color space counterclockwise by 30 degree, the coefficients should be 37h, 20h, e0h, and
37h.
15
IMGPROC_SAT
ADJ
Saturation adjustment coefficient
14
13
12
11
10
9
8
7
6
5
4
3
SAT
R/W
20h
2
1
0
This register defines the parameter of saturation adjustment for the image. The basics of saturation tuning is to multiply
the U and V component by a scaling factor, which could range from 0 to 127, to degrade or enhance the strength on
color components. Setting to 20h represents no scaling.
SAT
Saturation coefficient.
Bit
Name
Type
Reset
15
IMGPROC_BRI
ADJ1
Brightness adjustment coefficient B1
MT
K
IMG+0120h
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
BRI
R/W
0
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This register defines the parameter of brightness adjustment for the image. The parameter is in unsigned format. Setting
the value to be greater than 0 adds to the intensity of the image pixel. In terms of transfer curve, it represents the offset
in the y-axis. The valid value ranges from 0 to 255.
BRI
Brightness adjustment coefficient.
IMG+0124h
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DRK
R/W
0
fo
r
Bit
Name
Type
Reset
IMGPROC_BRI
ADJ2
Brightness adjustment coefficient B2
IMG+0128h
Bit
Name
Type
Reset
15
Re
lea
se
This register controls the parameter of brightness adjustment for the image. The parameter is in unsigned format.
Setting the value to be greater than 0 degrades the intensity of the image pixel. In terms of transfer curve, it represents
the offset in the x-axis. The valid value ranges from 0 to 255.
DRK Brightness adjustment coefficient
IMGPROC_CON
ADJ
Contrast adjustment coefficient
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
CON
R/W
20h
This register defines the parameter of contrast adjustment for the image pixel. The parameter is in unsigned format with
normalization factor 20h. Setting the value to be greater than 20h enhances the contrast for the image; and setting the
value to be less than 20h lowers the contrast for the image. The valid value ranges from 0 to 255.
Contrast adjustment coefficient
IMG+0130h
Bit
Name
Type
Reset
15
15
IMGPROC_COL
ORIZEU
Colorize u component coefficient
14
IMG+0134h
Bit
Name
Type
Reset
Co
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CON
13
12
11
10
9
8
7
6
5
4
3
UCOM
R/W
0
13
12
11
10
9
8
7
1
0
IMGPROC_COL
ORIZEV
Colorize v component coefficient
14
2
6
5
4
3
VCOM
R/W
0
2
1
0
These registers controls the parameters of colorize effect for the image. The valid value ranges from –128 to 127 in 2’s
complement format. If the values of both coefficients are zero, it implies the gray-scale effect.
MT
K
UCOM Colorize effect u component coefficient.
VCOM Colorize effect v component coefficient.
IMG+0140h
Bit
15
IMGPROC_MAS
K11
Mask coefficient C11
14
13
12
11
10
9
8
7
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Name
Type
Reset
C11
R/W
0
14
Bit
Name
Type
Reset
15
15
14
14
IMG+0150h
Bit
Name
Type
Reset
15
15
14
13
14
15
7
6
5
4
12
11
10
13
12
11
10
3
13
12
11
10
13
12
11
10
14
13
14
12
11
10
9
8
7
6
5
4
3
12
11
10
1
0
2
C13
R/W
0
1
0
IMGPROC_MAS
K21
9
8
7
6
5
4
3
9
8
7
9
8
7
9
8
7
2
C21
R/W
0
1
0
IMGPROC_MAS
K22
6
5
4
3
2
C22
R/W
0
1
0
IMGPROC_MAS
K23
6
5
4
3
2
C23
R/W
0
1
0
IMGPROC_MAS
K31
6
5
4
3
2
C31
R/W
0
1
0
IMGPROC_MAS
K32
Mask coefficient C32
13
2
C12
R/W
0
IMGPROC_MAS
K13
Mask coefficient C31
IMG+015Ch
Bit
Name
8
Mask coefficient C21
MT
K
15
9
Mask coefficient C23
IMG+0158h
Bit
Name
Type
Reset
10
Mask coefficient C22
IMG+0154h
Bit
Name
Type
Reset
11
Mask coefficient C13
IMG+014Ch
Bit
Name
Type
Reset
12
Re
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IMG+0148h
13
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15
IMGPROC_MAS
K12
Mask coefficient C12
fo
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IMG+0144h
Bit
Name
Type
Reset
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Type
Reset
R/W
0
15
IMGPROC_MAS
K33
Mask coefficient C33
14
13
12
11
10
9
8
7
6
5
4
3
2
C33
R/W
0
1
0
fo
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IMG+0160h
Bit
Name
Type
Reset
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MT6228 GSM/GPRS Baseband Processor Data Sheet
These registers define the 9 mask coefficients for linear filtering. The coefficients are in 2’s complement format with
range from –16 to 15. The index associated with these coefficients represents the row index followed by the column
index. The Image Engine performs the same arithmetic convolution on 3 components of the target image.
C11 C12
C13
Mask coefficient C11.
Mask coefficient C12.
Mask coefficient C13.
Mask coefficient C21.
Mask coefficient C22.
Mask coefficient C23.
Mask coefficient C31.
Mask coefficient C32.
Mask coefficient C33
IMG+0164h
Bit
Name
Type
Reset
15
Co
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C11
C12
C13
C21
C22
C23
C31
C32
C33
Re
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C 21 C 22 C 23
C 31 C 32 C 33
IMGPROC_SCA
LE
Mask data down-scaling coefficient
14
13
12
11
10
9
8
7
6
5
4
3
2
SCA
R/W
0
1
0
This register stores the value that could divide the mask data after convolution. It’s used for normalization, and only for
linear HP mode.
SCA The value used to scale down the mask data.
IMG+0170h
Bit
Name
Type
Reset
15
IMGPROC_GA
MMA_OFF0
Gamma correction offset value for segment 0
14
13
12
11
10
9
8
7
6
5
4
3
OFF0
R/W
0
2
1
0
MT
K
This register stores the y-offset value of the segment 0 for gamma correction.
OFF0
Offset value.
For offset values of other segments, please refer to Table 55.
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IMG+0190h
Bit
Name
Type
Reset
15
IMGPROC_GA
MMA_SLP0
Gamma correction slope value for segment 0
14
13
12
11
10
9
8
7
6
5
Revision 1.0
4
3
SLP0
R/W
0
2
This register stores the slope value of the segment 0 for gamma correction.
Slope value.
For slope values of other segments, please refer to Table 55.
Bit
Name
Type
Reset
15
14
13
12
11
10
9
8
This register is used to control the gamma correction mode.
GTO gamma value greater than one indicator
0 Gamma value is not greater than one.
1 Gamma value is greater than one.
IMG+0170h
IMG+0174h
IMG+0178h
IMG+017Ch
IMG+0180h
IMG+0184h
IMG+0188h
IMG+018Ch
IMG+0190h
IMG+0194h
IMG+0198h
IMG+019Ch
IMG+01A0h
IMG+01A4h
IMG+01A8h
6
5
4
3
2
1
0
GTO
R/W
0
Acronym
st
Offset value for the 1 segment
nd
IMGPROC_GAMMA_OFF0
Offset value for the 2 segment
IMGPROC_GAMMA_OFF1
Offset value for the 3rd segment
IMGPROC_GAMMA_OFF2
Offset value for the 4th segment
IMGPROC_GAMMA_OFF3
th
IMGPROC_GAMMA_OFF4
th
Offset value for the 6 segment
IMGPROC_GAMMA_OFF5
Offset value for the 7th segment
IMGPROC_GAMMA_OFF6
Offset value for the 5 segment
th
Offset value for the 8 segment
IMGPROC_GAMMA_OFF7
st
IMGPROC_GAMMA_SLP0
nd
Slope value for the 2 segment
IMGPROC_GAMMA_SLP1
Slope value for the 3rd segment
IMGPROC_GAMMA_SLP2
Slope value for the 1 segment
th
IMGPROC_GAMMA_SLP3
th
IMGPROC_GAMMA_SLP4
th
Slope value for the 6 segment
IMGPROC_GAMMA_SLP5
Slope value for the 7th segment
IMGPROC_GAMMA_SLP6
Slope value for the 4 segment
Slope value for the 5 segment
th
Slope value for the 8 segment
MT
K
IMG+01ACh
Register Function
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Register Address
7
0
IMGPROC_GAM
MA_CON
Gamma correction control register
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IMG+01B0h
1
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SLP0
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MT6228 GSM/GPRS Baseband Processor Data Sheet
IMGPROC_GAMMA_SLP7
Table 55 Gamma correction offset and slope register list
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14
15
14
15
11
10
9
8
7
6
5
4
13
12
11
10
9
8
7
6
5
3
14
13
12
11
10
9
8
2
7
6
1
0
IMGPROC_COL
OR1R_OFFY
4
3
2
1
0
IMGPROC_COL
OR1R_SLP
Color adjustment slope for 2nd segment, red
IMG+0240h
Bit
Name
Type
Reset
12
Color adjustment offset y for 2nd segment, red
IMG+0220h
Bit
Name
Type
Reset
13
fo
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15
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Bit
Name
Type
Reset
IMGPROC_COL
OR1R_OFFX
Color adjustment offset x for 2nd segment, red
IMG+0200h
Revision 1.0
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5
4
3
2
1
0
SLP
R/W
0
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The above lists part of the registers that define the color adjustment parameters.
Color adjustment in Image Engine is used to tune the red, green, and blue color dimension individually to exhibit
required color tone as a whole. We provide 3-segment piecewise linear transfer curve for the user to be configured.
The x offset defines the separation point for input color value. The y offset defines the offset for each segment. The
slope defines the contrast enhancement ratio for each segment.
For the red, green and blue components, the bit-width of the offset value is 8.
OFFX input value separation point.
OFFY output value offset.
SLP
Slope. Contrast tuning ratio within the segment.
For all the registers of color adjustment, please refer to Table 6 for detail information.
Register
Address
IMG+0200h
IMG+0204h
IMG+0208h
IMG+020Ch
IMG+0210h
IMG+0214h
IMG+0220h
Register Function
Color adjustment offset x for 2nd segment, red
Bit-width Acronym
8
IMGPROC_COLOR1R_OFFX
rd
8
IMGPROC_COLOR2R_OFFX
nd
8
IMGPROC_COLOR1G_OFFX
Color adjustment offset x for 3 segment, red
Color adjustment offset x for 2 segment, green
rd
Color adjustment offset x for 3 segment, green
8
IMGPROC_COLOR2G_OFFX
Color adjustment offset x for 2nd segment, blue
8
IMGPROC_COLOR1R_OFFX
Color adjustment offset x for 3rd segment, blue
8
IMGPROC_COLOR2R_OFFX
8
IMGPROC_COLOR1R_OFFY
nd
Color adjustment offset y for 2 segment, red
rd
Color adjustment offset y for 3 segment, red
8
IMGPROC_COLOR2R_OFFY
Color adjustment offset y for 2nd segment, green
8
IMGPROC_COLOR1G_OFFY
IMG+022Ch
Color adjustment offset y for 3rd segment, green
MT
K
IMG+0224h
IMG+0228h
IMG+0230h
IMG+0234h
8
IMGPROC_COLOR2G_OFFY
nd
8
IMGPROC_COLOR1R_OFFY
rd
8
IMGPROC_COLOR2R_OFFY
Color adjustment offset y for 2 segment, blue
Color adjustment offset y for 3 segment, blue
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IMG+0240h
Color adjustment slope for 1st segment, red
6
IMGPROC_COLOR0R_SLOPE
IMG+0244h
Color adjustment slope for 2nd segment, red
6
IMGPROC_COLOR1R_SLOPE
IMG+0248h
Color adjustment slope for 3rd segment, red
IMG+0250h
IMG+0254h
6
IMGPROC_COLOR1R_SLOPE
st
6
IMGPROC_COLOR0G_SLOPE
nd
6
IMGPROC_COLOR1G_SLOPE
Color adjustment slope for 1 segment, green
Color adjustment slope for 2 segment, green
rd
Color adjustment slope for 3 segment, green
6
IMGPROC_COLOR1G_SLOPE
Color adjustment slope for 1st segment, blue
6
IMGPROC_COLOR0B_SLOPE
IMG+0264h
Color adjustment slope for 2nd segment, blue
6
IMGPROC_COLOR1B_SLOPE
6
IMGPROC_COLOR1B_SLOPE
IMG+0268h
rd
Color adjustment slope for 3 segment, blue
MT
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Table 56 Color adjustment offset and slope register list
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IMG+0258h
IMG+0260h
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IMG+0304h
Bit
Name
Type
Reset
15
IMGPROC_IMG
WIDTH
Image frame width
14
13
12
11
10
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9
8
7
6
5
4
3
IM
R/W
0
2
1
0
Bit
Name
Type
Reset
15
IMGPROC_IMG
HEIGHT
Image frame height
14
13
12
11
10
9
8
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IMG+0308h
fo
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This register is the image frame width register. The maximum allowable frame width is 4095. The Image Engine uses it to
locate the address for every pixel in the image frame.
IM
Image frame width
7
6
5
4
3
2
1
0
IH
R/W
0
This register is the image frame height register. The maximum allowable frame height is 4095. The Image Engine uses it to
locate the address for every pixel in the image frame.
IH
Image frame width
Bit
Name
Type
Reset
Bit
Name
Type
Reset
Image frame source register
31
30
15
14
29
28
27
26
25
24
23
SRC[31:16]
R/W
0
8
7
SRC[15:0]
R/W
0
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IMG+030Ch
13
12
11
10
9
IMGPROC_ADD
R_SRC
22
21
20
19
18
17
16
6
5
4
3
2
1
0
This register defines the starting address of the source image frame. The Image Engine takes this address as that of the
top-left pixel in the source image frame, and assumes the image frame is stored continuously, such that, all other pixels in
that image frame can be addressed by an offset, which is calculated by the engine.
SRC The source address
IMG+0310h
31
30
15
14
29
28
27
26
25
13
12
11
10
9
MT
K
Bit
Name
Type
Reset
Bit
Name
Type
Reset
IMGPROC_ADD
R_DST
Image frame destination register
24
23
DST[31:16]
R/W
0
8
7
DST[15:0]
R/W
0
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19
18
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MT6228 GSM/GPRS Baseband Processor Data Sheet Revision 1.0
This register defines the starting address of the destination image frame. The Image Engine writes the processed image
pixel by pixel from the top-left corner into the memory. The target image will be stored in the continuous address in the
memory.
DST
The destination address
IMG+0314h
15
14
13
12
11
10
9
8
7
6
5
4
3
DUMMY
R/W
0
2
1
0
fo
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Bit
Name
Type
Reset
IMGPROC_DUM
MYPXL
Dummy pixel
IMG+0318h
Bit
15
R2Y source select
14
13
12
11
10
9
8
Name
Type
Reset
Re
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This register defines the dummy pixel value, which is taken to pad beyond the image frame boundary when performing the
ranking (maximum, median, and minimum) filter. The value is unsigned and is applied on all R/G/B color components
simultaneously.
For linear filtering, the Image Engine only considers the pixels within the image boundary.
DUMMY
The dummy pixel.
7
6
5
4
IMGPROC_R2Y_
SRC
3
2
PNG
R/W
0
1
0
IMGD
GIF
MA
R/W R/W
0
0
IMG+031Ch
Bit
Name
Type
Reset
15
Co
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This register defines the RGB source of IPP3 in IMGPROC mode. (Only one source can be enabled)
ON
1
OFF
0
IMGPROC_TNL_
EN
Thumbnail output enable
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TNL
R/W
0
This register defines if enable the thumbnail data path
ON
1
OFF
0
IMG+0320h
15
14
13
12
11
10
9
8
MT
K
Bit
Name
Type
Reset
Image machine enable
7
IMGPROC_EN
6
5
4
3
2
RSTB
R/W
1
1
0
EN
R/W
0
This register defines the enable and software reset signal of the image processor. Before performing image effect
adjustment, the reset is necessary.
EN
0: Machine disable, pixel-base and filtering path are both disable.
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1: Machine enable
0: low-level Reset, all configurations will be initialized.
1 : Not Reset.
6.16.2
Image Engine in MT6228
Post RESZ
Memory
YUV
YUV
RGB
IMGDMA
GIF_Dec
PNG_Dec
RGB
Fig. 1.
IPP2
RGB
IMGDMA
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Drop RESZ
fo
r
The Image Engine (IPP) plays the important role in MT6228 multimedia data path. It performs the necessary color space
conversion for next-stage needs. The path from Post-RESZ to IPP1 can also been applied the image effect. Fig.1 shows its
input/output data format and the relation with other multimedia module.
IPP1
IPP3
YUV
Post RESZ
Image Engine in MT6228.
The Graph mode setting depends on what kinds of data paths and image engines that we used. The Details are all listed in
Table 4.
Used Engine
Function
Note
Preview
IPP1
IPP1: Y2R, YUV/RGB image effect
Capture
IPP1, IPP2
IPP1 : Y2R, YUV/RGB image effect
Co
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Graph mode
IPP2: Y2R
MPEG
IPP1
IPP1: Y2R, YUV/RGB image effect
IMGPROC
IPP1, IPP3
IPP1: Y2R, YUV/RGB image effect
IPP3: R2Y
IMAGE Encode
IPP2, IPP3
IPP2: Y2R
IPP3: R2Y
Thumbnail enable must be set if
using IPP2
R2Y source (image_dma, gif, png
decorder) must be selected for IPP3
Thumbnail enable must be set if
using IPP2
Table 57. Graph mode of Image Engine.
6.16.3
Image effect application
The Image Engine is the hardware coprocessor that performs image effects on video stream or stand-alone image. It
provides the following effects:
Hue adjustment.
2.
Saturation adjustment.
3.
Contrast and intensity adjustment.
4.
Grayscale and colorization.
MT
K
1.
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5.
Gamma correction.
6.
Color adjustment.
7.
Linear filtering.
8.
Nonlinear filtering.
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MT6228 GSM/GPRS Baseband Processor Data Sheet Revision 1.0
The format of the coefficients is listed in Table 58.
Parameter group
Range (normalized factor) Format
Hue
C11, C12, C21, C22
-64 ~ 64 (64)
Saturation
SAT
0~127 (32)
Contrast and brightness
BRI1
0~255
Unsigned
BRI2
0~255
Unsigned
Contrast
0~255 (32)
Unsigned
Colorize
U, V
-128~127
2’s complement
Gamma correction
Offset
0~63
Unsigned
Slope
0~255 (16)
Unsigned
Offset for red
0~31
Unsigned
Slope for red
0~63 (16)
Unsigned
Offset for green
0~63
Unsigned
Slope for green
0~63 (16)
Unsigned
Offset for blue
0~31
Unsigned
Slope for blue
0~63 (16)
Unsigned
Mask
2’s complement
Unsigned
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Color adjustment
fo
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Function
C11, C12, C13, C21, C22, -16~15
C23, C31, C32, C33
2’s complement
Dummy pixel
Unsigned
0~63
Table 58 Coefficients format table
6.16.3.1
Gamma correction and color adjustment
Gamma correction is a nonlinear technique. We use linear-approximation scheme for it and the same curve is applied
equally on red, green, and blue components.
Two approaches are provided. For the first one, the overall input value is equally divided into 8 segments. It’s suitable for
the case when gamma is greater than 1. For the second one, the value is divided into 6 unsymmetrical segments. It’s
suitable for the case when gamma is smaller then 1.
MT
K
Color adjustment is used to adjust different colors with different curves. For each color, a 3 segment piece-wise linear curve
is applied. The user has to decide the offsets and the slopes of these 3 segments. The coefficients should be positive.
Cool tone and warm tone filters are both popular applications for color adjustment.
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Filtering coefficients for linear filter
The filtering operation in Image Engine basically imposes artifacts on the original image and aims to produce a variety of
effects.
For low pass filter, the matrix can be defined as
1
2
b
⋅ b b
1
2
b
1
b , where b is a positve number
1
are all popular examples that could
Re
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1 1 1
1 1 1
1 2 1
1
1
1
H1 =
⋅ 1 1 1 , H2 =
⋅ 1 2 1 , and H 3 =
⋅ 2 4 2
9
10
16
1 1 1
1 1 1
1 2 1
fo
r
1
H=
b+2
present blur or softening effects. The concept can be extended to larger size matrix. For H1-like matrix, we provided 5x5
and 7x7 option, which we named blur and more blur effects. The matrices are as follows:
1 1 1 1 1
H 5 x5
1
1
=
⋅ 1
25
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
H 7 x7
1
1
=
⋅ 1
49
1
1
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1 1 1 1 1 1 1
1 1 1 1 1 1 1
1 1 1 1 1 1
1 1 1 1 1 1
1 1 1 1 1 1
1 1 1 1 1 1
1 1 1 1 1 1 1
For high-pass filter, we illustrate some commonly used matrices.
0 −1
0
−1 −1 −1
1
−2
1
H1 = −1 5 − 1 , H 2 = − 1 9 − 1 , H 3 = − 2
5 −2
0 −1 0
−1 −1 −1
1 −2
1
MT
K
These filters present edge enhancement effects. They all have the property that the sum of their elements is unity in order to
avoid amplitude bias in the processed image. In Image Engine, the user can choose HP filtering option for them.
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0 −1 0
1
For matrix like H = ⋅ − 1
7 − 1 , a division-by-3 is required since the sum of its elements is not unity. For this
3
0 −1 0
case, the user should program the register IMGPROC_SCALE and choose HP filtering with scale down option.
−1 −1 −1
H = −1
8 − 1 , the sum of its elements is 0 and no division is required. The user can choose HP
fo
r
For matrix like
−1 −1 −1
filtering option for it.
Nonlinear filter
Re
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6.16.3.3
Median filter is a nonlinear technique that is useful for noise suppression in images. It consists of a 3-by-3 sliding window.
The center pixel in the window is replaced by the median of the pixels in the window.
The idea is further extended to maximum filter and minimum filter. The maximum filter presents dilation effects. It puts
more emphasis on the brighter point in the image. On the contrary, the minimum filter presents erosion effects.
6.16.4
Image process control
6.17
6.17.1
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For filtering application, the software can initialize, start, and stop the operation of the Image Engine. Setting START bit in
the register IMGPROC_CON starts the operation, and setting STOP bit stops the operation. Notice that the user should not
restart the next process before the Image Engine returns from BUSY state. The user can check the status by monitoring
BUSY bit in the register IMGPROC_STS.
MPEG-4/H.263 Video CODEC
General Description
MPEG-4 is an emerging video coding standard defined in ISO/IEC 14496-2. It is designed to cover a wide range of
bit-rates (typically, 5 kbps to 10Mbps). MPEG-4 standard has become one of the enabling factors for mobile multimedia
communications. H.263 is another video coding standard that is developed by ITU-T/SG 15 for low-bit-rate applications
below 64kbps. H.263 profile 0 level 10 is the mandatory video decoder in 3GPP specification. Therefore, our goal is to
design a video codec suited to both MPEG-4 and H.263 standard.
MT
K
There are two coding modes in MPEG-4 video compression: Intra-frame coding and Inter-frame coding. Intra-frame
coding refers to video coding techniques that achieve compression by exploiting the high spatial correlation between
neighboring pels within a video frame. Such techniques are also known as spatial redundancy reduction techniques or
still-image coding techniques. Inter-frame coding refers to video coding techniques that achieve compression by exploiting
the high temporal correlation between the frames of a video sequence. Such methods are also known as temporal
redundancy reduction techniques. Note that inter-frame coding may not be appropriate for some applications. For example,
it would be necessary to decode the complete inter-frame coded sequence before being able to randomly access individual
frames. Thus, a combined approach is normally used in which a number of frames are intra-frame coded (I-frames) at
specific intervals within the sequence and the other frames are inter-frame coded (Predicted or P-frames) with reference to
those key frames. Moreover, intra-frame coding is allowed in P-frames.
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The ISO/IEC 14496 specification is intended to be generic in the sense that it serves a wide range of applications,
bit-rates, resolutions, qualities and services. A number of coding tools are defined in the specification. Considering the
practicality of implementing the full syntax of this specification, a limited number of subsets of the syntax are also
stipulated by means of “profile” and “level”. A “profile” is a defined subset of the entire bitstream syntax that is defined by
this specification. A “level” is a defined set of constraints imposed on parameters in the bitstream. Our application is
focused on handset devices. Due to restriction of limited resource, only simple profile is supported for most of handset
devices. According to 3GPP TS 26.234 specification, H.263 profile 0 level 10 is the mandatory video decoder. MPEG-4
visual simple profile level 0 is an optional video decoder. The MPEG-4/H.263 codec supports both MPEG-4 simple profile
and H.263 baseline profile. Generally, the file extension of MPEG-4 video file is .mp4. The file extension of 3GPP video
file is .3gp.
The decode specification is as follows:
Re
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The design implements both decoder and encoder. The decoder block diagram is shown in Figure 34. The encoder
block diagram is shown in Figure 35
1.
Support ISO/IEC 14496-2 MPEG-4 simple profile @ level 0~3
2.
Support H.263 profile 0 level 10 (baseline profile)
3.
The following visual tools are supported
I-VOP
P-VOP
AC/DC Prediction
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4-MV
Unrestricted MV
Error Resilience
Slice Resynchronization
Data Partitioning
Reversible VLC
Short Header Mode
Full and Half Pel accuracy
fcode can be 1~7
Maximum horizontal luminance pixel resolution can be up to 352
Maximum vertical luminance pixel resolution can be up to 288
Error Concealment
MT
K
Single object
4.
Deblocking filter
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Source images are coded in blocks of pixels. Since correlation among spatially adjacent blocks is not taken into
account during coding, this results in block boundaries being visible when the decoded image is reconstructed.
The purpose of deblocking filter is to reduce blocking artifacts while keeping image edge intact. Blocking effect
can be reduced efficiently and image will be smooth after applying deblocking filter. A high quality deblocking
filter is embedded in the MPEG-4 Decoder. It performs both horizontal and vertical deblocking filtering
simultaneously while decoding. Memory access bandwidth is minimized in the design. Luminance as well as
chrominance data is filtered.
fo
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The encoder specification is as follows:
Support ISO/IEC 14496-2 MPEG-4 simple profile @ level 0, partially support MPEG-4 simple profile @ level 1
6.
Support H.263 profile 0 level 10
7.
The following visual tools are supported
I-VOP
P-VOP
DC Prediction
Unrestricted MV
Short Header Mode
Full and Half Pel motion estimation
Decision making logic
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5.
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fcode can be 1~3
intra_dc_vlc_threshold shall be 0
Maximum horizontal luminance pixel resolution can be up to 352
MT
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Maximum vertical luminance pixel resolution can be up to 288
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Reference VOP
Motion
Coding
Coded bitstream (Motion)
Motion
Compensation
Texture Decoding
Variable
Length
Decoding
Inverse Scan
Inverse DC &
AC Prediction
Inverse
Quantization
Reconstructed VOP
Figure 34 Block Diagram of Decoder
Reference VOP
IDCT
Motion
Estimation
Motion
Compensation
Reconstructed VOP
Delay
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Current VOP
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se
Coded bitstream (Texture)
fo
r
Delay
FDCT
Q
IDCT
IQ
Motion
Vector
Prediction
Variable
Length
Encoding
Variable
Length
Encoding
Bitstream
Packing
Coded bitstream
MT
K
Figure 35 Block Diagram of Encoder
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6.17.2
Register Definitions
6.17.2.1
Main Control
MP4_CODEC_C
OMD
Video CODEC Command Register
Bit
Name
Type
Bit
31
-
30
-
29
-
28
-
27
-
26
-
25
-
24
-
23
-
22
-
21
-
15
14
13
12
11
10
9
8
7
6
5
Name
-
-
-
-
-
-
-
-
-
-
-
This register is the main command register for video CODEC.
19
-
18
-
17
-
16
-
4
3
2
1
0
DEC_ ENC_
DEC_ ENC_ CORE
STAR STAR
RST RST _RST
T
T
WO
WO
WO
WO
WO
Re
lea
se
Type
20
-
fo
r
MP4+0000h
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MT6228 GSM/GPRS Baseband Processor Data Sheet Revision 1.0
MP4+0004h
MP4_VLC_DMA
_COMD
VLC DMA Command Register
Bit
Name
Type
Bit
31
-
30
-
15
14
Name
-
-
Type
Co
nf
id
en
tia
l
CORE_RST
Software reset control. Writing 1 to this bit will reset the hardware core excluding APB control register
set of decoder and encoder.
ENC_RST Software reset control. Writing 1 to this bit will reset the APB control register set of encoder. Note that this bit
won’t reset the hardware core.
DEC_RST Software reset control. Writing 1 to this bit will reset the APB control register set of decoder. Note that this bit
won’t reset the hardware core.
ENC_START Start the encode operation if writing 1 to this bit. The encode operation will start only when no decode
operation is running; otherwise the encode operation will queue until decode operation is done.
DEC_START Start the decode operation if writing 1 to this bit. The decode operation will start only when no encode
operation is running; otherwise the decode operation will queue until encode operation is done.
29
-
28
-
27
-
26
-
25
-
24
-
23
-
22
-
21
-
20
-
19
-
18
-
13
12
11
10
9
8
7
6
5
4
3
2
-
-
-
-
-
-
-
-
-
-
-
-
17
-
16
-
1
0
RESU
STOP
ME
WO
WO
This register is the main control of VLC DMA.
MT
K
STOP Stop the VLC DMA. Stop VLC DMA activities through SW rather than HW state machine.
RESUME Resume the VLC DMA access. VLC DMA state machine will go to a pending state if the maximum allowed
write count to target memory is reached and then an interrupt has occured. After re-allocating the target address,
SW writes RESUME to unfreeze the encoding process.
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6.17.2.2
Encoder
6.17.2.2.1
Control
MP4+0100h
Ko
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MT6228 GSM/GPRS Baseband Processor Data Sheet Revision 1.0
MP4_ENC_COD
EC_CONF
Encoder Configuration Register
31
30
29
28
27
26
25
24
23
22
21
20
19
Name
-
-
-
-
-
-
-
-
-
-
-
-
Type
Reset
Bit
0
15
0
14
0
13
0
5
0
4
Name
-
-
Type
Reset
0
0
17
-
-
-
0
3
0
2
0
1
0
0
IRQ
ENC
R/W
0
R/W
0
VPGO
DCT
B
Re
lea
se
0
0
0
0
0
0
0
12
11
10
9
8
7
6
MC_B
DQUA
FME HALF STEP_LIMIT
URST PMV
N
_EN
R/W R/W R/W R/W R/W R/W R/W R/W
0
0
0
0
0
0
0
0
18
fo
r
Bit
R/W
0
R/W
0
R/W
0
R/W
0
16
CHEC
K_TV
This register is used to configure the operating conditions and modes of video CODEC.
ENC
MT
K
Co
nf
id
en
tia
l
Video CODEC Operation Mode
0 Decode Mode
1 Encode Mode
IRQ
Control for interrupt request
0 Disable the interrupt reporting mechanism
1 Enable the interrupt reporting mechanism
DCT
DCT Control
0 Enable JPEG CODEC Operation
1 Enable MPEG-4 Video CODEC Operation
VPGOB Control for decoding Video Packet Header; keep this for legacy reason.
0 Disable: decoding in Video Packet Level. It means the software will take the responsibility for decoding
packet header of each video packet.
1 Enable: decoding in Video Object Plane Level
STEP_LIMIT Step limit for Motion Estimation. The total number of steps in a n-step search is STEP_LIMIT+2.
Increasing STEP_LIMIT can increase search range of motion vectors.
HALF Motion Estimation uses half-pel resolution
0 Disable. Perform full pel motion estimation only
1 Enable. Perform full pel motion estimation first, then half pel motion estimation
FME Fast Motion Enhancement
0 Enable Four Step Search motion estimation algorithm
1 Enable Mediatek proprietary motion estimation algorithm. This algorithm can improve visual quality in fast
motion pictures while maintaining the same quality as Four Step Search in slow motion pictures. Enabling this
algorithm does not increase search time. Thus, set FME to 1 is recommended.
DQUAN
Control for automatic update quantizer_scale process; keep this for legacy reason.
0 Disable
1 Enable
PMV Predictive Motion Vector Search. This is a two pass search algorithm. This algorithm can co-operate with both four
step search (FME=0) and Mediatek proprietary search (FME=1). The idea is to initially consider several highly
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MT6228 GSM/GPRS Baseband Processor Data Sheet Revision 1.0
MP4+0104h
Bit
Name
Type
Bit
Name
Type
Re
lea
se
fo
r
likely predictors (starting points), perform motion estimation from these predictors, and choose the best result
among these predictors. In our approach, the two predictors approach is adopted. The origin (0,0) is considered as
the predictor of first pass. The minimum BDM point found in first pass will be the predictor of the second pass.
After finishing two-pass motion estimation, choose the best result between the two minimum BDM points. This
algorithm can significantly improve PSNR by about 0.8dB. However, the search time will increase by about 60%.
Setting PMV to 1 or 0 is the trade-off between visual quality and search time.
0 Disable
1
EnableMC_BURST_EN 2-beat Burst mode enable signal in MC.
0 Diable
1 Enable
CHECK_TVEnable signal to check if TV codec is busy before starting encoding operation.
0 Do not check TV codec
1 Check TV codec
Encoder Status Register
31
30
29
28
27
26
25
RO
15
RO
14
RO
13
RO
12
RO
11
RO
10
RO
9
RO
RO
RO
RO
RO
RO
RO
24
23
STATE
RO
RO
8
7
STATE
RO
RO
MP4_ENC_STS
22
21
20
19
18
17
16
RO
6
RO
5
RO
4
RO
3
RO
2
RO
1
RO
0
RO
RO
RO
RO
RO
RO
RO
MP4+0108h
MP4_ENC_IRQ_
MASK
Encoder Interrupt Mask Register
Bit
Name
Type
Reset
Bit
31
-
30
-
15
14
Name
-
-
Type
Reset
Co
nf
id
en
tia
l
This register provides the state information of encoding sequencer for software program. It is a mirror of the HW one-hot
sequencer state machine and can be used for debugging or IRQ status judging.
29
-
28
-
27
-
26
-
25
-
24
-
23
-
22
-
21
-
20
-
19
-
18
-
13
12
11
10
9
8
7
6
5
4
3
2
-
-
-
-
-
-
-
-
-
-
17
-
16
-
1
0
BLOC
ENC_
DMA PACK K_DO
DONE
NE
R/W R/W R/W R/W
1
1
1
1
This register contains mask bit for each interrupt source in MPEG-4 Video encoder. It allows each interrupt source to be
disabled or masked out separately under software control. After System Reset or software reset, all bit values will be set to
‘0’ to indicate that interrupt requests are enabled.
Mask of VLE DMA Limit interrupt.
MT
K
DMA
PACK
Mask of video packet bit count expire interrupt.
BLOCK_DONE Mask of block procedure complete interrupt.
ENC_DONE
Mask of encode complete interrupt.
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MP4+010Ch
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MT6228 GSM/GPRS Baseband Processor Data Sheet Revision 1.0
MP4_ENC_IRQ_
STS
Encoder Interrupt Status Register
Bit
Name
Type
Bit
31
-
30
-
29
-
28
-
27
-
26
-
25
-
24
-
23
-
22
-
21
-
20
-
19
-
15
14
13
12
11
10
9
8
7
6
5
4
3
Name
-
-
-
-
-
-
-
-
-
-
-
-
18
-
17
-
16
-
1
0
BLOC
ENC_
DMA PACK K_DO
DONE
NE
RO
RO
RO
RO
fo
r
2
Type
Re
lea
se
This register allows software program to poll which interrupt source generates the interrupt request. A bit set to ‘1’ indicates
a corresponding active interrupt source. Note that IRQ control bit in MP4_ENC_CODEC_CONF should be enabled first
in order to activate the interrupt reporting mechanism.
DMA
Mask of VLC DMA interrupt. When decoder detects empty VLD stream buffer, an interrupt will inform the
driver SW to refill the VLD stream buffer.
PACK
Video Packet Bit Count Exceed interrupt. If a video packet size is larger than defined the interrupt will happen.
BLOCK_DONE Block decode or encode complete. A normal complete flag if the SW needs a block-based HW decoding
or encoding.
Encode complete. A normal condition when encoding procedure is done.
MP4+0110h
Encoder Interrupt Acknowledge Register
Bit
Name
Type
Bit
31
-
30
-
15
14
Name
-
-
Type
Co
nf
id
en
tia
l
ENC_DONE
MP4_ENC_IRQ_
ACK
29
-
28
-
27
-
26
-
25
-
24
-
23
-
22
-
21
-
20
-
19
-
18
-
13
12
11
10
9
8
7
6
5
4
3
2
-
-
-
-
-
-
-
-
-
-
17
-
16
-
1
0
BLOC
ENC_
DMA PACK K_DO
DONE
NE
WC
WC
WC
WC
This register provides a mean for software program to acknowledge the interrupt source. Writing a ‘1’ to the specific bit
position will result in an acknowledgement to the corresponding interrupt source and clear the corresponding bit in
MP4_ENC_IRQ_STS.
ENC_DONE
Encode Task Complete
BLOCK_DONE Block Task Complete
PACK
Video Packet Bit Count Expired
DMA
VLC DMA Buffer Limit Reached
Bit
Name
Type
Reset
31
-
MP4_ENC_CON
F
Encoder Configuration Register
MT
K
MP4+0114h
30
-
29
-
28
-
27
-
26
25
24
23
R/W
0
R/W
0
R/W
0
R/W
0
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22
21
PACKCNT
R/W R/W
0
0
20
19
18
R/W
0
R/W
0
R/W
0
17
16
PACK
R/W R/W
0
0
MediaTek Inc. Confidential
Bit
15
Name
Type R/W
0
Reset
14
R/W
0
13
12
R/W
0
R/W
0
11
10
INTRA
R/W R/W
0
0
9
8
R/W
0
R/W
0
7
-
6
-
5
4
R/W
0
R/W
0
3
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MT6228 GSM/GPRS Baseband Processor Data Sheet Revision 1.0
2
SKIP
R/W R/W
0
0
This register is used specially to configure the desired encode conditions and modes for video CODEC.
SKIP
1
0
R/W
0
R/W
0
Base Addresses
MP4+0124h
Bit
31
Name
Type RO
Bit
15
Name
Type R/W
MP4_ENC_VOP
_ADDR
Encoder Current VOP Base Address Register
30
RO
14
R/W
29
28
27
26
25
24
23
VOP
RO
RO
RO
9
8
7
VOP
R/W R/W R/W
Co
nf
id
en
tia
l
6.17.2.2.2
Re
lea
se
fo
r
Threshold for deciding not_coded bit. The value of SKIP is programmed by software first. The first round of
pattern code (me_pattern_code is set to 6’h0 whenever (SADy + SDAu + SADv) <= skip_threshold*16
not_coded bit will be set if pattern_code = 6’h0 and motion vector = (0,0)
INTRA Threshold for deciding INTRA Coding in P frame. The value of INTRA is programmed by software first. The
3-bits macro-block type (mb_type) is set to 3’h0 (Inter MB) if SADy < intra_threshold*1024. Otherwise, mb_type
is set to 3’h3 (Intra_MB)
PACK Use Video Packet Mode
0 Disable
1 Enable
PACKCNT Desired Bit Counts for a Video Packet. Used in encode mode to define the largest VLE buffer size of a video
packet
RO
13
RO
12
RO
11
RO
10
R/W
R/W
R/W
R/W
22
21
20
19
18
17
16
RO
6
RO
5
RO
4
RO
3
RO
2
R/W
R/W
R/W
R/W
R/W
R/W
1
-
R/W
0
-
This register describes the starting address of Current VOP Frame that is going to be encoded. Note that this base address
should be 4-byte aligned. And the required frame buffer size should be: numbers of pixel per frame * 1.5 bytes (YUV420
format).
VOP
Current VOP Base Address.
MP4+0128h
30
RO
14
R/W
29
28
27
26
RO
13
RO
12
RO
11
RO
10
R/W
R/W
R/W
R/W
25
24
23
REF
RO
RO
RO
9
8
7
REF
R/W R/W R/W
22
21
20
19
18
17
16
RO
6
RO
5
RO
4
RO
3
RO
2
R/W
R/W
R/W
R/W
R/W
R/W
1
-
R/W
0
-
MT
K
Bit
31
Name
Type RO
Bit
15
Name
Type R/W
MP4_ENC_REF_
ADDR
Encoder Reference VOP Base Address Register
This register describes the starting address of Reference VOP Frame. Note that this base address should be 4-byte aligned.
And the required frame buffer size should be: numbers of pixel per frame * 1.5 bytes (YUV420 format).
REF
Reference VOP Base Address.
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MP4+012Ch
22
21
20
19
RO
6
RO
5
RO
4
RO
3
R/W
R/W
R/W
R/W
R/W
MP4_ENC_REC
_ADDR
Encoder Reconstructed VOP Base Address Register
30
29
28
27
26
RO
14
RO
13
RO
12
RO
11
RO
10
R/W
R/W
R/W
R/W
R/W
25
24
23
REC
RO
RO
RO
9
8
7
REC
R/W R/W R/W
18
17
16
RO
2
R/W
1
-
R/W
0
-
fo
r
Bit
31
Name
Type RO
Bit
15
Name
Type R/W
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MT6228 GSM/GPRS Baseband Processor Data Sheet Revision 1.0
This register describes the starting address of Reconstructed VOP Frame. Note that this base address should be 4-byte
aligned. And the required frame buffer size should be: numbers of pixel per frame * 1.5 bytes (YUV420 format).
REC
MP4+0130h
Bit
31
Name
Type
Bit
15
Name
Type R/W
Re
lea
se
Reconstructed VOP Base Address. The high boundary address of Reconstructed VOP should not cross 1M address
boundary because the implementation of address offset counter is 20 bits. i.e. please make sure (the lower 20bits
Reconstructed base address + size of Reconstructed frame) < 220
VLE Data Load-Store LSB Base Address Register
30
29
28
27
26
14
13
12
11
10
R/W
R/W
R/W
R/W
R/W
25
24
23
STORE
9
8
STORE
R/W R/W
MP4_ENC_DAT
A_STORE_ADD
R
22
21
20
19
18
17
16
7
6
5
4
3
2
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1
-
R/W
0
-
Co
nf
id
en
tia
l
This register describes the LSB address of VLE Data Load-Store buffer in data-partitioned mode. Note that this base
address should be 4-byte aligned. And the required buffer size for encoder and decoder should be: 3K bytes and number of
macroblock per frame * 32 bytes, respectively.
STORE LSB address of VLE Data Load-Store buffer
MP4+0134h
Bit
31
Name
Type
Bit
15
Name
Type R/W
DC/AC Prediction Storage LSB Base Address Register
30
14
R/W
29
28
27
26
13
12
11
10
R/W
R/W
R/W
R/W
25
24
23
DACP
9
8
DACP
R/W R/W
MP4_ENC_DAC
P_ADDR
22
21
20
19
18
17
16
7
6
5
4
3
2
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1
-
R/W
0
-
This register describes the LSB address of DC/AC Prediction Storage buffer. Note that this base address should be 4-byte
aligned. And the required buffer size for encoder and decoder should be: 1K bytes and 4K bytes, respectively.
MT
K
DACP LSB address of DC/AC Prediction Storage buffer
MP4+0138h
Bit
Name
31
MP4_ENC_MVP
_ADDR
Motion Vector Storage LSB Base Address Register
30
29
28
27
26
25
24
23
MVP_ADDR
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22
21
20
19
18
17
16
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Type
Bit
15
Name
Type R/W
14
13
12
11
10
R/W
R/W
R/W
R/W
R/W
9
8
MVP_ADDR
R/W R/W
7
6
5
4
3
R/W
R/W
R/W
R/W
R/W
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MT6228 GSM/GPRS Baseband Processor Data Sheet Revision 1.0
2
R/W
R/W
1
-
R/W
0
-
MVP_ADDR
LSB address of Motion Vector Storage buffer
6.17.2.2.3
Data Structure
Encoder VOP Structure 0 Register
Re
lea
se
MP4+0140h
fo
r
This register describes the LSB address of Motion Vector Storage buffer. Note that this base address should be 4-byte
aligned. And the required buffer size for encoder should be mb_x_limit * 2 * 4 bytes, which equals to 320 Bytes for VGA
size.
Bit
31
30
29
28
27
26
25
24
Name
-
-
-
-
-
-
-
-
Type
Bit
15
14
13
12
11
10
9
8
R/W
R/W
R/W
R/W
R/W
Name
Type
VLCTHR
R/W
R/W
QUANT
R/W
MP4_ENC_VOP
_STRUCT0
23
22
21
20
19
18
-
-
-
-
-
-
7
6
5
17
16
ROUN
D
R/W
0
4
3
2
1
SHOR
FCODE
RVLC DATA TYPE
T
R/W R/W R/W R/W R/W R/W R/W R/W
This register is used to describe the header information of a certain Video Object Plane that is going to be processed by
video CODEC.
MT
K
Co
nf
id
en
tia
l
TYPE vop_coding_type definition, for both decode and encode.
0 This is a P-VOP frame (inter frame)
1 This is an I-VOP frame (intra frame)
DATA data_partitioned, for decode only; keep this for legacy reason.
0 Data stream is in non-data-partitioned mode
1 Data stream is in data-partitioned mode
RVLC resversible_vlc, for decode only; keep this for legacy reason.
0 Data stream contains no reversible VLC information
1 Data stream uses reversible VLC tables.
SHORT short_video_header; for both decode and encode
0 Normal MPEG-4 format
1 H.263 Compatible format
FCODE fcode size setting for both decode and encode, ranges from 0 to 7.
QUANT vop_quant. For both decode and encode. Quantizer scale of the current frame. For variable Q in decode mode,
QUANT is an initial setting of the current frame.
VLCTHR intra_dc_vlc_thr. For decode only. According to VLCTHR, the decoder has to switch from intra DC mode to
inter DC mode when the quantizer_scale is larger than a pre-defined value. VLCTHR ranges from 0 to 7.
ROUND
Rounding type of half-pel motion compensation. ROUND==1 means truncation toward zero (the pixel value
is always larger than 0); ROUND==0 means rounding-off addition.
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MP4+0144h
MP4_ENC_VOP
_STRUCT1
Encoder VOP Structure 1 Register
30
-
29
-
14
R/W
13
R/W
28
R/W
12
R/W
27
26
25
HECBIT
R/W R/W R/W
11
10
9
YLIMIT
R/W R/W R/W
24
R/W
8
R/W
23
-
22
-
21
-
20
-
7
R/W
6
R/W
5
R/W
4
19
18
17
MBLENGTH
R/W R/W R/W
3
2
1
XLIMIT
R/W R/W R/W
R/W
16
R/W
0
R/W
fo
r
Bit
31
Name
Type
Bit
15
Name
Type R/W
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MT6228 GSM/GPRS Baseband Processor Data Sheet Revision 1.0
This register is used by software program to control the start position and count limit of macroblock for a certain Video
Packet or Video Object Plane that is going to be processed by video CODEC.
MP4+0148h
Encoder VOP Structure 2 Register
31
-
30
-
29
-
28
-
27
-
15
-
14
-
13
-
12
11
R/W
26
-
25
-
10
9
VP_YPOS
R/W R/W R/W
24
R/W
8
R/W
23
22
R/W
7
-
R/W
6
-
Co
nf
id
en
tia
l
Bit
Name
Type
Bit
Name
Type
Re
lea
se
XLIMIT Macroblock count in X direction of a frame.
YLIMIT Macroblock count in Y direction of a frame.
MBLENGTH
Bit count of Macroblock Number in Video Packet Header. It is a value defined by the following formula:
MBCNT = (XLIMIT+15)/16 * (YLIMIT+15)/16. For larger MBCNT, we have larger MBLENGTH.
MBLENGTH is ranged from 1 to 14.
HECBIT
Bit count of extension header code in Video Packet Header
MP4_ENC_VOP
_STRUCT2
21
20
19
18
17
MBNO
R/W R/W R/W R/W R/W
5
4
3
2
1
VP_XPOS
R/W R/W R/W R/W
16
R/W
0
R/W
This register is used by software program to control the start position and count limit of macroblock for a certain Video
Packet or Video Object Plane that is going to be processed by video CODEC.
VP_XPOS Starting position of the current Video Packet in X coordinate.
VP_YPOS Starting position of the current Video Packet in Y coordinate.
MBNO
Macroblock count limit for a video packet or frame. For a CIF frame the value will be 396.
MP4+014Ch
Bit
Name
Type
Bit
Name
Type
31
-
30
-
15
-
14
-
MP4_VOP_STR
UCT3
VOP Structure 3 Register
29
-
28
-
27
-
26
-
25
-
24
23
22
13
-
12
11
RO
RO
10
YPOS
RO
9
RO
8
RO
RO
RO
7
-
RO
6
-
21
20
MBNO
RO
RO
5
4
RO
19
18
17
16
RO
3
RO
2
XPOS
RO
RO
1
RO
0
RO
RO
RO
MT
K
This register provides the position and count information of a certain macroblock that is currently under process of video
CODEC.
XPOS Current Macroblock Position in X coordinate
YPOS Current Macroblock Position in Y coordinate
MBNO Current Macroblock Count
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Bit
Name
Type
Bit
MP4_ENC_MB_
STRUCT0
MB Structure 0 Register
31
-
30
-
15
14
29
-
28
-
13
12
DCVL
AC
Name QUANTIZER
C
Type R/W R/W R/W R/W
27
-
26
-
25
-
24
-
23
-
22
-
21
-
20
-
19
-
11
10
9
8
7
6
5
4
3
R/W
R/W
R/W
DQUANT
R/W
R/W
PATTERN
R/W
R/W
R/W
R/W
18
17
16
QUANTIZER
R/W R/W R/W
2
1
0
CODE
TYPE
D
R/W R/W R/W
fo
r
MP4+0150h
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MT6228 GSM/GPRS Baseband Processor Data Sheet Revision 1.0
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This register is used to store the header information of current macroblock. This register is mostly used for debugging. Also
used to provide hardware certain header information if all header parsing is done by software instead of hardware.
CODED
not_coded flag of current macroblock; not_coded can be decoded by hardware from macroblock header.
TYPE
mb_coding_type of current macroblock; mb_coding_type can be decoded by hardware from mcbpc in
macroblck header.
PATTERN pattern_code of current macroblock; pattern_code can be decoded by hardware from cbpc and cbpy in
macroblock header.
DQUANT dquant. It can be –2, -1, +1 or +2; total 4 possible choices using 2 bits to represent; dquant can be decoded by
hardware from macroblock header.
AC
ac_pred_flag. It decides whether AC prediction is needed; always 0 in encoder; ac_pred_flag can be decoded
by hardware from macroblock header.
DCVLC
use_intra_dc_vlc. If this bit is 0, intra AC VLC decode is used (no intra DC exists in current macroblock).
QUANTIZER quantizer_scale, ranged from 1 to 31. It can be variable if we have dquant values.
VLC DMA
MP4+0160h
Bit
31
Name
Type R/W
Bit
15
Name
Type R/W
Co
nf
id
en
tia
l
6.17.2.2.4
MP4_ENC_VLC_
BASE_ADDR
Encoder VLC DMA Base Address Register
30
29
28
27
26
R/W
14
R/W
13
R/W
12
R/W
11
R/W
10
R/W
R/W
R/W
R/W
R/W
25
24
23
BASE
R/W R/W R/W
9
8
7
BASE
R/W R/W R/W
22
21
20
19
18
17
16
R/W
6
R/W
5
R/W
4
R/W
3
R/W
2
R/W
R/W
R/W
R/W
R/W
R/W
1
-
R/W
0
-
This register is used to describe the address of started Code Word for each VLC DMA buffer. Note that this base address
should be 4-byte aligned.
BASE VLC DMA Base Address
Bit
Name
Type
Bit
MP4_ENC_VLC_
BASE_BITCNT
Encoder VLC DMA Base Bit Count Register
MT
K
MP4+0164h
31
-
30
-
29
-
28
-
27
-
26
-
25
-
24
-
23
-
22
-
21
-
20
-
19
-
18
-
17
-
16
-
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
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Name
Type
-
-
-
-
-
-
-
-
-
-
-
R/W
R/W
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MT6228 GSM/GPRS Baseband Processor Data Sheet Revision 1.0
BIT
R/W
R/W
R/W
This register is used to describe the starting bit position of the 1st Code Word in the 1st VLC DMA buffer. For the following
VLC DMA buffers, it is assumed that they are all 4-byte aligned and always start from bit position “0”.
Start of Bit at the 1st Code Word of 1st DMA Buffer
Bit
31
Name
Type
Reset
0
Bit
15
Name
Type R/W
1
Reset
MP4_ENC_VLC_
LIMIT
Encoder VLC DMA Buffer Limit Register
fo
r
MP4+0168h
30
-
29
-
28
-
27
-
26
-
25
-
24
-
23
-
22
-
21
-
20
-
19
-
18
-
17
-
16
-
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
LIMIT
R/W R/W
1
1
Re
lea
se
BIT
R/W
1
R/W
1
R/W
1
R/W
1
This register is used to describe the buffer size of each VLC DMA buffer. Note that the value is counted in word (32-bit).
Whenever the limit is reached and the corresponding interrupt control is enabled, an interrupt request will be generated.
LIMIT DMA Buffer Size, Count in Word (32-bit)
MP4+016Ch
30
29
28
27
26
25
RO
14
RO
13
RO
12
RO
11
RO
10
RO
RO
RO
RO
RO
MP4_ENC_VLC_
WORD
22
21
20
19
18
17
16
RO
9
24
23
ADDR
RO
RO
8
7
RO
6
RO
5
RO
4
RO
3
RO
2
RO
1
RO
0
RO
RO
RO
RO
RO
RO
RO
RO
RO
Co
nf
id
en
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l
Bit
31
Name
Type RO
Bit
15
Name ADDR
Type RO
Encoder VLC DMA Current Word Register
RO
This register provides the address information of a certain code word that is under process of video CODEC. SW reads it
back after encode of a frame is done.
ADDR VLC DMA current Address
MP4+0170h
Bit
Name
Type
Bit
Name
Type
MP4_ENC_VLC_
BITCNT
Encoder VLC DMA Current Bit Count Register
31
-
30
-
15
-
14
-
29
-
28
-
27
-
26
-
25
-
24
-
23
-
22
-
21
-
20
-
19
-
13
-
12
-
11
-
10
-
9
-
8
-
7
-
6
-
5
-
4
3
RO
18
-
17
-
16
-
2
1
BITCNT
RO
RO
RO
0
RO
MT
K
This register provides the bit position information of a certain Code Word that is under process of video CODEC.
BITCNT
Current Bit Count
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30
29
28
27
26
R/W
1
14
R/W
1
13
R/W
1
12
R/W
1
11
R/W
1
10
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
25
24
23
22
JUMP_FROM_ADDR
R/W R/W R/W R/W
1
1
1
1
9
8
7
6
JUMP_FROM_ADDR
R/W R/W R/W R/W
1
1
1
1
21
20
19
18
17
16
R/W
1
5
R/W
1
4
R/W
1
3
R/W
1
2
R/W
1
1
R/W
1
0
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
fo
r
Bit
31
Name
Type R/W
Reset
1
Bit
15
Name
Type R/W
Reset
1
MP4_ENC_VLC_
JUMP_FROM_A
DDR
Encoder VLC DMA Ring Buffer Ending Address
Register
MP4+0174h
Ko
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MT6228 GSM/GPRS Baseband Processor Data Sheet Revision 1.0
Encoder VLC DMA Ring Buffer Starting Address
Register
MP4+0178h
30
29
28
27
26
R/W
1
14
R/W
1
13
R/W
1
12
R/W
1
11
R/W
1
10
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
25
24
23
22
JUMP_TO_ADDR
R/W R/W R/W R/W
1
1
1
1
9
8
7
6
JUMP_TO_ADDR
R/W R/W R/W R/W
1
1
1
1
Co
nf
id
en
tia
l
Bit
31
Name
Type R/W
1
Reset
Bit
15
Name
Type R/W
Reset
1
Re
lea
se
JUMP_FROM_ADDR
The ending address of the current DMA buffer; when a jump takes place in VLC DMA
address counter, the address will jump from the ending address of the current DMA buffer, which is
JUMP_FROM_ADDR, to the starting address of the next DMA buffer, which is JUMP_TO_ADDR.
To disable the ring buffer feature, set this register to all ones; note that the address counter will not
jump until done with the content in memory with address as JUMP_FROM_ADDR. So the memory
content with address JUMP_FROM_ADDR will be executed by hardware.
MP4_ENC_VLC_
JUMP_TO_ADD
R
21
20
19
18
17
16
R/W
1
5
R/W
1
4
R/W
1
3
R/W
1
2
R/W
1
1
R/W
1
0
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
JUMP_TO_ADDR The starting address of the next DMA buffer; when a jump takes place in VLC DMA address
counter, the address will jump from the ending address of the current DMA buffer, which is JUMP_FROM_ADDR, to the
starting address of the next DMA buffer, which is JUMP_TO_ADDR; note that the address counter will not jump until done
with the content in memory with address as JUMP_FROM_ADDR. So the memory content with address
JUMP_FROM_ADDR will be executed by hardware.
6.17.2.2.5
MPEG4 Encoder Resync Marker Configuration 0
Register
MT
K
MP4+0180h
Resync Marker
Bit
31
30
29
Name EN MODE
Type R/W R/W R/W
Reset
0
0
1
Bit
15
14
13
28
27
26
25
R/W
1
12
R/W
1
11
R/W
1
10
R/W
1
9
24
23
22
21
PERIOD_BITS
R/W R/W R/W R/W
1
1
1
1
8
7
6
5
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MP4_ENC_RES
YNC_CONF0
20
19
18
17
16
R/W
1
4
R/W
1
3
R/W
1
2
R/W
1
1
R/W
1
0
MediaTek Inc. Confidential
Name
Type R/W
Reset
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
PERIOD_BITS
R/W R/W R/W
1
1
1
R/W
1
R/W
1
R/W
1
EN
Ko
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MT6228 GSM/GPRS Baseband Processor Data Sheet Revision 1.0
R/W
1
R/W
1
R/W
1
fo
r
Resync marker insertion enable
0 Disable resync marker insertion
1 Enable resync marker insertion
MODE Resync Marker insertion mode selection
0 resync marker is inserted based on number of bits
1 resync marker is inserted based on number of macroblocks
PERIOD_BITS Period in number of bits to insert resync marker; only effective when MODE is set to 0; hardware will
insert resync marker at the next macroblock boundary once the bit length of a video packet exceeds this value.
Bit
31
Name
Type R/W
Reset
0
Bit
15
Name
Type R/W
Reset
1
MPEG4 Encoder Resync Marker Configuration 1
Register
30
R/W
0
14
29
R/W
0
13
28
R/W
0
12
27
R/W
0
11
26
R/W
0
10
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
HEC
25
R/W
0
9
Re
lea
se
MP4+0184h
24
23
22
R/W R/W R/W
0
0
0
8
7
6
PERIOD_MB
R/W R/W R/W R/W
1
1
1
1
MP4_ENC_RES
YNC_CONF1
21
R/W
0
5
20
R/W
0
4
19
R/W
0
3
18
R/W
0
2
17
R/W
0
1
16
HEC
R/W
0
0
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
MP4+0188h
Bit
31
Name
Type R/W
Reset
0
Bit
15
Name
Type R/W
Reset
0
Co
nf
id
en
tia
l
Header Extension Code; indicates the value of header_extension_code in MPEG4 standard (ISO/IEC 14496-2)
0 header_extension_code is 0.
1 header_extension_code is 1.
PERIOD_MB Period in number of macroblocks (MB) to insert resync marker; only effective when MODE is set to 1;
hardware will insert resync marker at the next macroblock boundary once the number of macroblock in current
video packet exceeds this value.
MP4_ENC_TIME
_BASE
MPEG4 Encoder Local Time Base Register
30
R/W
0
14
29
R/W
0
13
28
R/W
0
12
27
R/W
0
11
26
R/W
0
10
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
25
24
23
22
21
20
MODULO_TIME_BASE
R/W R/W R/W R/W R/W R/W
0
0
0
0
0
0
9
8
7
6
5
4
VOP_TIME_INCREMENT
R/W R/W R/W R/W R/W R/W
0
0
0
0
0
0
19
18
R/W
0
3
17
BW
R/W R/W
0
0
2
1
R/W
0
0
R/W
0
R/W
0
R/W
0
R/W
0
16
MT
K
MODULO_TIME_BASE Represent the value of modulo_time_base; value ranges from 0 to 31.
BW
Bit width of vop_time_increment. The real bit-width of vop_time_increment is (BW + 1), ranging from 1 to 16.
VOP_TIME_INCREMENT Carries the value of vop_time_increment defined in MPEG4 standard (ISO/IEC 14496-2); the
meaningful bit width of vop_time_increment is signaled by BW field.
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6.17.2.3
Decoder
MP4+0200h
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MT6228 GSM/GPRS Baseband Processor Data Sheet Revision 1.0
MP4_DEC_COD
EC_CONF
Decoder Configuration Register
31
30
29
28
27
26
25
24
23
22
21
20
19
Name
-
-
-
-
-
-
-
-
-
-
-
-
-
Type
Reset
Bit
0
15
0
14
0
13
0
6
0
5
0
4
0
3
STEP_LIMIT
R/W
0
R/W
0
17
-
-
0
2
0
1
16
CHEC
K_TV
R/W
0
0
IRQ
ENC
R/W
0
R/W
0
VPGO
DCT
B
R/W
0
R/W
0
Re
lea
se
0
0
0
0
0
0
12
11
10
9
8
7
MC_B
DEBL COPY
DQUA
Name
URST PMV
FME HALF
N
OCK _REC
_EN
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset
0
0
0
0
0
0
0
0
0
18
fo
r
Bit
R/W
0
This register is used to configure the operating conditions and modes of video CODEC.
ENC
MT
K
Co
nf
id
en
tia
l
Video CODEC Operation Mode
0 Decode Mode
1 Encode Mode
IRQ
Control for interrupt request
0 Disable the interrupt reporting mechanism
1 Enable the interrupt reporting mechanism
DCT
DCT Control
0 Enable JPEG CODEC Operation
1 Enable MPEG-4 Video CODEC Operation
VPGOB Control for decoding Video Packet Header; keep this for legacy reason.
0 Disable: decoding in Video Packet Level. It means the software will take the responsibility for decoding
packet header of each video packet.
1 Enable: decoding in Video Object Plane Level
STEP_LIMIT Step limit for Motion Estimation, for encode only; keep this for legacy reason. The total number of steps
in a n-step search is STEP_LIMIT+2. Increasing STEP_LIMIT can increase search range of motion vectors.
HALF Motion Estimation uses half-pel resolution, for encode only; keep this for legacy reason.
0 Disable. Perform full pel motion estimation only
1 Enable. Perform full pel motion estimation first, then half pel motion estimation
FME Fast Motion Enhancement, for encode only; keep this for legacy reason.
0 Enable Four Step Search motion estimation algorithm
1 Enable Mediatek proprietary motion estimation algorithm. This algorithm can improve visual quality in fast
motion pictures while maintaining the same quality as Four Step Search in slow motion pictures. Enabling this
algorithm does not increase search time. Thus, set FME to 1 is recommended.
DQUAN
Control for automatic update quantizer_scale process.
0 Disable
1 Enable
PMV Predictive Motion Vector Search, for encode only; keep this for legacy reason. This is a two pass search algorithm.
This algorithm can co-operate with both four step search (FME=0) and Mediatek proprietary search (FME=1). The
idea is to initially consider several highly likely predictors (starting points), perform motion estimation from these
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r
predictors, and choose the best result among these predictors. In our approach, the two predictors approach is
adopted. The origin (0,0) is considered as the predictor of first pass. The minimum BDM point found in first pass
will be the predictor of the second pass. After finishing two-pass motion estimation, choose the best result between
the two minimum BDM points. This algorithm can significantly improve PSNR by about 0.8dB. However, the
search time will increase by about 60%. Setting PMV to 1 or 0 is the trade-off between visual quality and search
time.
0 Disable
1 Enable
COPY_REC
Enable signal to copy reconstructed memory to deblocking memory.
0 Disable
1 Enable
DEBLOCK Enable signal for deblocking mode. 3 different combination of DEBLOCK and COPY_REC are shown below
00 (DECLOCK = 0 & COPY_REC = 0) : disable both deblocking filter and memory copy from reconstructed
memory to deblocking memory.
01 (DECLOCK = 0 & COPY_REC = 1) : disable both deblocking filter and memory copy from reconstructed
memory to deblocking memory.
10 (DECLOCK = 1 & COPY_REC = 0) : Enable deblocking filter and save deblocked frame to deblocking
memory.
11 (DECLOCK = 1 & COPY_REC = 1) : Disable deblocking filter and save non-deblocked frame to deblocking
memory.
CHECK_TVEnable signal to check if TV codec is busy before starting decoding operation.
0 Do not check TV codec
1 Check TV codec
Bit
Name
Type
Bit
Name
Type
Decoder Status Register
31
30
RO
15
RO
14
RO
RO
Co
nf
id
en
tia
l
MP4+0204h
29
28
27
26
25
RO
13
RO
12
RO
11
RO
10
RO
9
RO
RO
RO
RO
RO
24
23
STATE
RO
RO
8
7
STATE
RO
RO
MP4_DEC_STS
22
21
20
19
18
17
16
RO
6
RO
5
RO
4
RO
3
RO
2
RO
1
RO
0
RO
RO
RO
RO
RO
RO
RO
This register provides the state information of decoding sequencer for software program. It is a mirror of the HW one-hot
sequencer state machine and can be used for debugging or IRQ status judging.
MP4+0208h
31
-
30
-
15
14
29
-
28
-
27
-
26
-
25
-
24
-
23
-
22
-
21
-
13
12
11
10
9
8
7
6
5
-
-
-
-
-
-
-
MT
K
Bit
Name
Type
Reset
Bit
Name
-
MP4_DEC_IRQ_
MASK
Decoder Interrupt Mask Register
-
-
Type
Reset
475/616
20
-
19
-
18
-
17
-
4
3
2
1
BLOC
DEC_ MARK
DMA K_DO
RLD
DONE ER
NE
R/W R/W R/W R/W R/W
1
1
1
1
1
16
0
VLD
R/W
1
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MT6228 GSM/GPRS Baseband Processor Data Sheet Revision 1.0
This register contains mask bit for each interrupt sources in MPEG-4 Video Decoder. It allows each interrupt source to be
disabled or masked out separately under software control. After System Reset or software reset, all bit values will be set to
‘0’ to indicate that interrupt requests are enabled.
DMA
Mask of VLC DMA interrupt.
BLOCK_DONE Mask of block procedure complete interrupt.
DEC_DONE
Mask of marker error interrupt in decode.
RLD
Mask of run length coding error interrupt
VLD
Mask of VLD error interrupt generated in decoding process.
MP4+020Ch
Re
lea
se
MARK
fo
r
Mask of decode complete interrupt.
Decoder Interrupt Status Register
Bit
Name
Type
Bit
31
-
30
-
29
-
28
-
27
-
26
-
25
-
24
-
15
14
13
12
11
10
9
8
Name
-
-
-
-
-
-
-
-
Type
23
-
22
-
21
-
7
6
5
-
-
20
-
19
-
MP4_DEC_IRQ_
STS
18
-
17
-
4
3
2
1
BLOC
DEC_
DMA K_DO
MARK RLD
DONE
NE
RO
RO
RO
RO
RO
16
0
VLD
RO
DMA
Co
nf
id
en
tia
l
This register allows software program to poll which interrupt source generates the interrupt request. A bit set to ‘1’ indicates
a corresponding active interrupt source. Note that IRQ control bit in MP4_DEC_CODEC_CONF should be enabled first
in order to activate the interrupt reporting mechanism.
Mask of VLC DMA interrupt. When decoder detects empty VLD stream buffer, an interrupt will inform the
driver SW to refill the VLD stream buffer.
BLOCK_DONE Block decode or encode complete. A normal complete flag if the SW needs a block-based HW decoding
or encoding..
DEC_DONE
Decode complete. A normal condition when decoding procedure is done.
MARK
Marker decode error occurred.
RLD
Run length coding error. Generated when the accumulated run value is larger than 64 (the 8x8 block memory
size).
VLD
VLD error of decoding process. Generated when a code can not be correctly referenced in VLD table
MP4+0210h
31
-
30
-
29
-
28
-
27
-
26
-
25
-
24
-
23
-
22
-
21
-
20
-
19
-
18
-
17
-
16
-
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
MT
K
Bit
Name
Type
Bit
MP4_DEC_IRQ_
ACK
Decoder Interrupt Acknowledge Register
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Name
-
-
-
-
-
-
-
-
-
-
Type
Ko
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MT6228 GSM/GPRS Baseband Processor Data Sheet Revision 1.0
BLOC
DEC_
DMA K_DO
MARK RLD
DONE
NE
WC
WC
WC
WC
WC
VLD
WC
This register provides a mean for software program to acknowledge the interrupt source. Writing a ‘1’ to the specific bit
position will result in an acknowledgement to the corresponding interrupt source.
Base Address
MP4+0224h
Bit
31
Name
Type R/W
Bit
15
Name
Type R/W
Re
lea
se
6.17.2.3.1
fo
r
VLD
Variable Length Decoding Error
RLD
Run Length Decoding Error
MARK Marker Decoding Error
DEC_DONE
Decode Task Complete
BLOCK_DONE Block Task Complete
DMA VLC DMA Buffer Limit Reached
Decoder Reference VOP Base Address Register
30
29
28
27
26
R/W
14
R/W
13
R/W
12
R/W
11
R/W
10
R/W
R/W
R/W
R/W
R/W
25
24
23
REF_ADDR
R/W R/W R/W
9
8
7
REF_ADDR
R/W R/W R/W
MP4_DEC_REF_
ADDR
22
21
20
19
18
17
16
R/W
6
R/W
5
R/W
4
R/W
3
R/W
2
R/W
R/W
R/W
R/W
R/W
R/W
1
-
R/W
0
-
REF
Co
nf
id
en
tia
l
This register describes the starting address of Reference VOP Frame. Note that this base address should be 4-byte aligned.
And the required frame buffer size should be: numbers of pixel per frame * 1.5 bytes (YUV420 format).
Reference VOP Base Address.
MP4+0228h
Bit
31
Name
Type R/W
Bit
15
Name
Type R/W
MP4_DEC_REC
_ADDR
Decoder Reconstructed VOP Base Address Register
30
29
28
27
26
R/W
14
R/W
13
R/W
12
R/W
11
R/W
10
R/W
R/W
R/W
R/W
R/W
25
24
23
REC_ADDR
R/W R/W R/W
9
8
7
REC_ADDR
R/W R/W R/W
22
21
20
19
18
17
16
R/W
6
R/W
5
R/W
4
R/W
3
R/W
2
R/W
R/W
R/W
R/W
R/W
R/W
1
-
R/W
0
-
This register describes the starting address of Reconstructed VOP Frame. Note that this base address should be 4-byte
aligned. And the required frame buffer size should be: numbers of pixel per frame * 1.5 bytes (YUV420 format).
REC
Reconstructed VOP Base Address.
Bit
31
Name
Type R/W
Bit
15
MP4_DEC_DEB
LOCK_ADDR
Decoder Deblocking Base Address Register
MT
K
MP4+022Ch
30
29
28
27
26
R/W
14
R/W
13
R/W
12
R/W
11
R/W
10
25
24
23
22
DEBLOCK_ADDR
R/W R/W R/W R/W
9
8
7
6
477/616
21
20
19
18
17
16
R/W
5
R/W
4
R/W
3
R/W
2
R/W
1
R/W
0
MediaTek Inc. Confidential
Name
Type R/W
R/W
R/W
R/W
R/W
DEBLOCK_ADDR
R/W R/W R/W R/W
R/W
R/W
R/W
R/W
Ko
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MT6228 GSM/GPRS Baseband Processor Data Sheet Revision 1.0
-
R/W
-
This register describes the starting address of deblocking frame. Note that this base address should be 4-byte aligned. And
the required frame buffer size should be: numbers of pixel per frame * 1.5 bytes (YUV420 format).
DEBLOCK_ADDR
29
28
27
26
14
13
12
11
10
R/W
R/W
R/W
R/W
R/W
25
24
23
STORE
9
8
STORE
R/W R/W
22
21
20
19
18
17
16
7
6
5
4
3
2
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1
-
R/W
0
-
Re
lea
se
30
fo
r
MP4_DEC_DAT
Decoder Data Load-Store LSB Base Address Register A_STORE_ADD
R
MP4+0230h
Bit
31
Name
Type
Bit
15
Name
Type R/W
Deblocking Base Address.
This register describes the LSB address of memory buffer used to store the macroblock header, Intra DC values and motion
vectors as decoding data-partitioned MPEG4 files. Note that this base address should be 4-byte aligned. And the required
buffer size for encoder and decoder should be: 3K bytes and number of macroblock per frame * 32 bytes, respectively.
STORE LSB address of VLE Data Load-Store buffer
Bit
31
Name
Type
Bit
15
Name
Type R/W
DC/AC Prediction Storage LSB Base Address Register
30
14
R/W
29
28
27
26
25
24
23
DACP
13
12
11
10
R/W
R/W
R/W
R/W
9
8
DACP
R/W R/W
MP4_DEC_DAC
P_ADDR
22
21
20
19
18
17
16
7
6
5
4
3
2
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1
-
R/W
0
-
Co
nf
id
en
tia
l
MP4+0234h
This register describes the LSB address of DC/AC Prediction Storage buffer. Note that this base address should be 4-byte
aligned. And the required buffer size for encoder and decoder should be: 1K bytes and 4K bytes, respectively.
DACP LSB address of DC/AC Prediction Storage buffer
MP4+0238h
Bit
31
Name
Type
Bit
15
Name
Type R/W
MP4_DEC_MVP
_ADDR
Motion Vector Storage LSB Base Address Register
30
14
R/W
29
28
27
26
13
12
11
10
R/W
R/W
R/W
R/W
25
24
23
MVP_ADDR
9
8
MVP_ADDR
R/W R/W
22
21
20
19
18
17
16
7
6
5
4
3
2
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1
-
R/W
0
-
MT
K
This register describes the LSB address of Motion Vector Storage buffer. Note that this base address should be 4-byte
aligned. And the required buffer size for encoder should be mb_x_limit * 2 * 4 bytes, which equals to 320 Bytes for VGA
size.
MVP_ADDR
LSB address of Motion Vector Storage buffer
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6.17.2.3.2
Data Structure
MP4+0240h
MP4_DEC_VOP
_STRUCT0
Decoder VOP Structure 0 Register
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
Name
-
-
-
-
-
-
-
-
-
-
-
-
-
Type
Bit
15
14
13
12
11
10
9
8
7
6
5
R/W
R/W
Type
VLCTHR
R/W
R/W
QUANT
R/W
R/W
R/W
R/W
18
17
-
16
ROUN
D
R/W
0
4
3
2
1
SHOR
FCODE
RVLC DATA TYPE
T
R/W R/W R/W R/W R/W R/W R/W R/W
fo
r
Name
Ko
nk
a
MT6228 GSM/GPRS Baseband Processor Data Sheet Revision 1.0
Re
lea
se
This register is used to describe the header information of a certain Video Object Plane that is going to be processed by
video CODEC.
MP4+0244h
MP4_DEC_VOP
_STRUCT1
Decoder VOP Structure 1 Register
30
-
14
R/W
29
-
13
R/W
MT
K
Bit
31
Name
Type
Bit
15
Name
Type R/W
Co
nf
id
en
tia
l
TYPE vop_coding_type definition, for both decode and encode.
0 This is a P-VOP frame (inter frame)
1 This is an I-VOP frame (intra frame)
DATA data_partitioned, for decode only.
0 Data stream is in non-data-partitioned mode
1 Data stream is in data-partitioned mode
RVLC resversible_vlc, for decode only.
0 Data stream contains no reversible VLC information
1 Data stream uses reversible VLC tables.
SHORT short_video_header; for both decode and encode
0 Normal MPEG-4 format
1 H.263 Compatible format
FCODE fcode size setting for both decode and encode, ranges from 0 to 7.
QUANT vop_quant. For both decode and encode. Quantizer scale of the current frame. For variable Q in decode mode,
QUANT is an initial setting of the current frame.
VLCTHR intra_dc_vlc_thr. For decode only. According to VLCTHR, the decoder has to switch from intra DC mode to
inter DC mode when the quantizer_scale is larger than a pre-defined value. VLCTHR ranges from 0 to 7.
ROUND
Rounding type of half-pel motion compensation. ROUND==1 means truncation toward zero (the pixel value
is always larger than 0); ROUND==0 means rounding-off addition.
28
R/W
12
R/W
27
26
25
HECBIT
R/W R/W R/W
11
10
9
YLIMIT
R/W R/W R/W
24
R/W
8
R/W
23
-
22
-
21
-
20
-
7
R/W
6
R/W
5
R/W
4
R/W
19
18
17
MBLENGTH
R/W R/W R/W
3
2
1
XLIMIT
R/W R/W R/W
16
R/W
0
R/W
This register is used by software program to control the start position and count limit of macroblock for a certain Video
Packet or Video Object Plane that is going to be processed by video CODEC.
XLIMIT Macroblock count in X direction of a frame.
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MT6228 GSM/GPRS Baseband Processor Data Sheet Revision 1.0
YLIMIT Macroblock count in Y direction of a frame.
MBLENGTH
Bit count of Macroblock Number in Video Packet Header. It is a value defined by the following formula:
MBCNT = (XLIMIT+15)/16 * (YLIMIT+15)/16. For larger MBCNT, we have larger MBLENGTH.
MBLENGTH is ranged from 1 to 14.
HECBIT
Bit count of header extension code in Video Packet Header; this section includes modulo_time_base,
vop_time_increment, vop_coding_type, intra_dc_vlc_thr and vop_fcode_forward(only in P-VOP).
31
-
30
-
29
-
28
-
27
-
15
-
14
-
13
-
12
11
R/W
26
-
25
-
10
9
VP_YPOS
R/W R/W R/W
24
23
22
R/W
8
R/W
7
-
R/W
6
-
21
fo
r
Bit
Name
Type
Bit
Name
Type
MP4_DEC_VOP
_STRUCT2
Decoder VOP Structure 2 Register
20
19
18
17
MBNO
R/W R/W R/W R/W R/W
5
4
3
2
1
VP_XPOS
R/W R/W R/W R/W
Re
lea
se
MP4+0248h
R/W
16
R/W
0
R/W
This register is used by software program to control the start position and count limit of macroblock for a certain Video
Packet or Video Object Plane that is going to be processed by video CODEC.
VP_XPOS Starting position of the current Video Packet in X coordinate.
VP_YPOS Starting position of the current Video Packet in Y coordinate.
MBNO
Macroblock count limit for a video packet or frame. For a CIF frame the value will be 396.
Bit
Name
Type
Bit
31
-
30
-
15
14
Decoder MB Structure 0 Register
29
-
28
-
27
-
26
-
25
-
24
-
23
-
22
-
21
-
20
-
19
-
11
10
9
8
7
6
5
4
3
R/W
R/W
R/W
Co
nf
id
en
tia
l
MP4+024Ch
13
12
DCVL
Name QUANTIZER
AC
C
Type R/W R/W R/W R/W
DQUANT
R/W
R/W
PATTERN
R/W
R/W
R/W
R/W
MP4_DEC_MB_
STRUCT0
18
17
16
QUANTIZER
R/W R/W R/W
2
1
0
CODE
TYPE
D
R/W R/W R/W
MT
K
This register is used to store the header information of the current macroblock. This register is mostly used for debugging.
Also used to provide hardware certain header information if all header parsing is done by software instead of hardware.
CODED
not_coded flag of current macroblock; not_coded can be decoded by hardware from macroblock header.
TYPE
mb_coding_type of current macroblock; mb_coding_type can be decoded by hardware from mcbpc in
macroblck header.
PATTERN pattern_code of current macroblock; pattern_code can be decoded by hardware from cbpc and cbpy in
macroblock header.
DQUANT dquant. It can be –2, -1, +1 or +2; total 4 possible choices using 2 bits to represent; dquant can be decoded by
hardware from macroblock header.
AC
ac_pred_flag. It decides whether AC prediction is needed; always 0 in encoder; ac_pred_flag can be decoded
by hardware from macroblock header.
DCVLC
use_intra_dc_vlc. If this bit is 0, intra AC VLC decode is used (no intra DC exists in current macroblock).
QUANTIZER quantizer_scale, ranged from 1 to 31. It can be variable if we have dquant values.
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MT6228 GSM/GPRS Baseband Processor Data Sheet Revision 1.0
VLC DMA
.
Bit
31
Name
Type R/W
Bit
15
Name
Type R/W
MP4_DEC_VLC_
BASE_ADDR
Decoder VLC DMA Base Address Register
30
29
28
27
26
R/W
14
R/W
13
R/W
12
R/W
11
R/W
10
R/W
R/W
R/W
R/W
R/W
25
24
23
BASE
R/W R/W R/W
9
8
7
BASE
R/W R/W R/W
22
21
20
19
18
17
16
R/W
6
R/W
5
R/W
4
R/W
3
R/W
2
R/W
R/W
R/W
1
-
R/W
0
-
R/W
R/W
R/W
fo
r
MP4+0260h
BASE VLC DMA Base Address
MP4+0264h
Bit
Name
Type
Bit
Name
Type
Re
lea
se
This register is used to describe the address of started Code Word for each VLC DMA buffer. Note that this base address
should be 4-byte aligned.
Decoder VLC DMA Base Bit Count Register
31
-
30
-
29
-
28
-
27
-
26
-
25
-
24
-
15
-
14
-
13
-
12
-
11
-
10
-
9
-
8
-
MP4_DEC_VLC_
BASE_BITCNT
23
-
22
-
21
-
20
-
19
-
18
-
17
-
16
-
7
-
6
-
5
-
4
3
1
0
R/W
R/W
2
BIT
R/W
R/W
R/W
Co
nf
id
en
tia
l
This register is used to describe the starting bit position of the 1st Code Word in the 1st VLC DMA buffer. For the following
VLC DMA buffers, it is assumed that they are all 4-byte aligned and always start from bit position “0”.
Start of Bit at the 1st Code Word of 1st DMA Buffer
BIT
MP4+0268h
Bit
31
Name
Type
Reset
0
Bit
15
Name
Type R/W
Reset
1
MP4_DEC_VLC_
LIMIT
Decoder VLC DMA Buffer Limit Register
30
0
14
R/W
1
29
-
28
-
27
-
26
-
25
-
24
-
23
-
22
-
21
-
20
-
19
-
18
-
17
-
16
-
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
LIMIT
R/W R/W
1
1
This register is used to describe the buffer size of each VLC DMA buffer. Note that the value is counted in word (32-bit).
Whenever the limit is reached and the corresponding interrupt control is enabled, an interrupt request will be generated.
MT
K
LIMIT DMA Buffer Size, Count in Word (32-bit)
MP4+026Ch
Bit
Name
31
30
MP4_DEC_VLC_
WORD
Decoder VLC DMA Current Word Register
29
28
27
26
25
24
23
ADDR
481/616
22
21
20
19
18
17
16
MediaTek Inc. Confidential
Type RO
Bit
15
Name ADDR
Type RO
RO
14
RO
13
RO
12
RO
11
RO
10
RO
9
RO
8
RO
7
RO
6
RO
5
RO
4
RO
3
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
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MT6228 GSM/GPRS Baseband Processor Data Sheet Revision 1.0
RO
2
RO
1
RO
0
RO
RO
RO
This register provides the address information of a certain code word that is under process of video CODEC. SW reads it
back after decode of a frame is done.
MP4+0270h
MP4_DEC_VLC_
BITCNT
Decoder VLC DMA Current Bit Count Register
31
-
30
-
29
-
28
-
27
-
26
-
25
-
24
-
23
-
22
-
21
-
20
-
19
-
17
-
16
-
15
-
14
-
13
-
12
-
11
-
10
-
9
-
8
-
7
-
6
-
5
-
4
3
2
1
BITCNT
RO
RO
RO
0
Re
lea
se
Bit
Name
Type
Bit
Name
Type
fo
r
ADDR VLC DMA current Address
RO
18
-
RO
This register provides the bit position information of a certain Code Word that is under process of video CODEC.
Current Bit Count
Decoder VLC DMA Ring Buffer Ending Address
Register
MP4+0274h
Bit
31
Name
Type R/W
1
Reset
Bit
15
Name
Type R/W
Reset
1
30
29
28
27
26
R/W
1
14
R/W
1
13
R/W
1
12
R/W
1
11
R/W
1
10
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
25
24
23
22
JUMP_FROM_ADDR
R/W R/W R/W R/W
1
1
1
1
9
8
7
6
JUMP_FROM_ADDR
R/W R/W R/W R/W
1
1
1
1
Co
nf
id
en
tia
l
BITCNT
MP4_DEC_VLC_
JUMP_FROM_A
DDR
21
20
19
18
17
16
R/W
1
5
R/W
1
4
R/W
1
3
R/W
1
2
R/W
1
1
R/W
1
0
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
JUMP_FROM_ADDR
The ending address of the current DMA buffer; when a jump takes place in VLC DMA
address counter, the address will jump from the ending address of the current DMA buffer, which is
JUMP_FROM_ADDR, to the starting address of the next DMA buffer, which is JUMP_TO_ADDR.
To disable the ring buffer feature, set this register to all ones; note that the address counter will not
jump until done with the content in memory with address as JUMP_FROM_ADDR. So the memory
content with address JUMP_FROM_ADDR will be executed by hardware.
MP4+0278h
30
29
MT
K
Bit
31
Name
Type R/W
Reset
1
Bit
15
Name
Type R/W
MP4_DEC_VLC_
JUMP_TO_ADD
R
Decoder VLC DMA Ring Buffer Starting Address
Register
28
27
26
R/W
1
14
R/W
1
13
R/W
1
12
R/W
1
11
R/W
1
10
R/W
R/W
R/W
R/W
R/W
25
24
23
22
JUMP_TO_ADDR
R/W R/W R/W R/W
1
1
1
1
9
8
7
6
JUMP_TO_ADDR
R/W R/W R/W R/W
482/616
21
20
19
18
17
16
R/W
1
5
R/W
1
4
R/W
1
3
R/W
1
2
R/W
1
1
R/W
1
0
R/W
R/W
R/W
R/W
R/W
R/W
MediaTek Inc. Confidential
Reset
1
1
1
1
1
1
1
1
1
1
1
1
1
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1
1
1
JUMP_TO_ADDR The starting address of the next DMA buffer; when a jump takes place in VLC DMA address
counter, the address will jump from the ending address of the current DMA buffer, which is JUMP_FROM_ADDR, to the
starting address of the next DMA buffer, which is JUMP_TO_ADDR; note that the address counter will not jump until done
with the content in memory with address as JUMP_FROM_ADDR. So the memory content with address
JUMP_FROM_ADDR will be executed by hardware.
MP4+0300h
Bit
Name
Type
Reset
Bit
31
-
fo
r
Core
MP4_CORE_CO
NF
Core Configuration Register
30
-
29
-
28
-
27
-
26
-
25
-
24
-
23
R/W
0
7
22
R/W
0
6
21
R/W
0
5
20
R/W
0
4
19
R/W
0
3
18
R/W
0
2
17
R/W
0
1
16
R/W
0
0
VPGO
DCT
B
IRQ
ENC
R/W
0
R/W
0
Re
lea
se
6.17.2.4
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
DEBL
MC_B
COPY
DQUA
Name OCKI
URST PMV
FME HALF
_REC
N
_EN
NG
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset
0
0
0
0
0
0
0
0
0
STEP_LIMIT
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
This register is used to configure the operating conditions and modes of video CODEC.
ENC
MT
K
Co
nf
id
en
tia
l
Video CODEC Operation Mode
0 Decode Mode
1 Encode Mode
IRQ
Control for interrupt request
0 Disable the interrupt reporting mechanism
1 Enable the interrupt reporting mechanism
DCT
DCT Control
0 Enable JPEG CODEC Operation
1 Enable MPEG-4 CODEC Operation
VPGOB Control for decoding Video Packet Header.
0 Disable: decoding in Video Packet Level. It means the software will take the responsibility for decoding
packet header of each video packet.
1 Enable: decoding in Video Object Plane Level
STEP_LIMIT Step limit for Motion Estimation. The total number of steps in a n-step search is STEP_LIMIT+2.
Increasing STEP_LIMIT can increase search range of motion vectors.
HALF Motion Estimation uses half-pel resolution
0 Disable. Perform full pel motion estimation only
1 Enable. Perform full pel motion estimation first, then half pel motion estimation
FME Fast Motion Enhancement
0 Enable Four Step Search motion estimation algorithm
1 Enable Mediatek proprietary motion estimation algorithm. This algorithm can improve visual quality in fast
motion pictures while maintaining the same quality as Four Step Search in slow motion pictures. Enabling this
algorithm does not increase search time. Thus, set FME to 1 is recommended.
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MT6228 GSM/GPRS Baseband Processor Data Sheet Revision 1.0
MP4+0304h
Bit
31
Name
Type
Reset
Bit
15
Name
Type R/W
Reset
0
Co
nf
id
en
tia
l
Re
lea
se
fo
r
DQUAN
Control for automatic update quantizer_scale process.
0 Disable
1 Enable
PMV Predictive Motion Vector Search. This is a two pass search algorithm. This algorithm can co-operate with both four
step search (FME=0) and Mediatek proprietary search (FME=1). The idea is to initially consider several highly
likely predictors (starting points), perform motion estimation from these predictors, and choose the best result
among these predictors. In our approach, the two predictors approach is adopted. The origin (0,0) is considered as
the predictor of first pass. The minimum BDM point found in first pass will be the predictor of the second pass.
After finishing two-pass motion estimation, choose the best result between the two minimum BDM points. This
algorithm can significantly improve PSNR by about 0.8dB. However, the search time will increase by about 60%.
Setting PMV to 1 or 0 is the trade-off between visual quality and search time.
0 Disable
1 Enable
MC_BURST_EN
2-beat Burst mode enable signal in MC.
0 Diable
1 Enable
COPY_REC
Enable signal to copy reconstructed memory to deblocking memory.
0 Disable
1 Enable
DEBLOCK Enable signal for deblocking mode. Please remember to configure Deblocking Base Address Register when
DEBLOCK mode is enable.
3 different combination of DEBLOCK and COPY_REC are shown below
00 (DECLOCK = 0 & COPY_REC = 0) : disable both deblocking filter and memory copy from reconstructed
memory to deblocking memory.
01 (DECLOCK = 0 & COPY_REC = 1) : disable both deblocking filter and memory copy from reconstructed
memory to deblocking memory.
10 (DECLOCK = 1 & COPY_REC = 0) : Enable deblocking filter and save deblocked frame to deblocking
memory.
11 (DECLOCK = 1 & COPY_REC = 1) : Disable deblocking filter and save non-deblocked frame to deblocking
memory.
MP4_CORE_EN
C_CONF
Core Encoder Configuration Register
30
-
14
R/W
0
29
-
28
-
13
12
R/W
0
R/W
0
27
-
26
R/W
0
11
10
INTRA
R/W R/W
0
0
25
24
23
R/W
0
9
R/W
0
8
R/W
0
R/W
0
R/W
0
7
-
22
21
PACKCNT
R/W R/W
0
0
6
5
R/W
0
20
R/W
0
4
R/W
0
19
18
R/W R/W
0
0
3
2
SKIP
R/W R/W
0
0
17
16
PACK
R/W R/W
0
0
1
0
R/W
0
R/W
0
MT
K
This register is used specially to configure the desired encode conditions and modes for video CODEC.
SKIP
Threshold for deciding not_coded bit. The value of SKIP is programmed by software first. The first round of
pattern code (me_pattern_code is set to 6’h0 whenever (SADy + SDAu + SADv) <= skip_threshold*16
not_coded bit will be set if pattern_code = 6’h0 and motion vector = (0,0)
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MT6228 GSM/GPRS Baseband Processor Data Sheet Revision 1.0
Bit
Name
Type
Bit
Name
Type
MP4_DUPLEX_S
TS
Half Duplex Controller Status Register
31
30
29
28
27
26
15
14
13
12
11
10
RO
RO
RO
RO
RO
RO
25
24
23
22
RO
RO
8
7
6
DUPLEX_STATE
RO
RO
RO
RO
21
20
19
18
DUPLEX_STATE
RO
RO
RO
RO
5
4
3
2
17
16
RO
1
RO
0
RO
RO
RO
Re
lea
se
MP4+0308h
fo
r
INTRA Threshold for deciding INTRA Coding in P frame. The value of INTRA is programmed by software first. The
3-bits macro-block type (mb_type) is set to 3’h0 (Inter MB) if SADy < intra_threshold*1024. Otherwise, mb_type
is set to 3’h3 (Intra_MB)
PACK Use Video Packet Mode
0 Disable
1 Enable
PACKCNT Desired Bit Counts for a Video Packet. Used in encode mode to define the largest VLE buffer size of a video
packet
9
RO
RO
RO
This register is used to read back the current state of duplex controller in MPEG4 Codec.
DUPLEX_STATE
Base Addresses
MP4+0310h
Bit
31
Name
Type R/W
Bit
15
Name
Type
Core MSB Base Address Register
30
R/W
14
-
Co
nf
id
en
tia
l
6.17.2.4.1
Current state of duplex controller.
29
28
27
R/W
13
-
R/W
12
-
R/W
11
-
26
25
CODEC
R/W R/W
10
9
-
24
23
22
21
20
R/W
8
-
R/W
7
-
R/W
6
-
R/W
5
-
R/W
4
-
19
R/W
3
-
MP4_CORE_BA
SE
18
R/W
2
-
17
-
16
-
1
-
0
-
This register describes the MSB address that is used for VLE Data Load-Store and DC/AC Prediction Storage buffers. FOR
THE FOLLOWING HW-USED OFFSET ADDRESSES, their MSB’s must be confined within 1Mega. In other words,
results of (base address + offset addresses) should have the same value in bit range [31, 20].
CODEC
MPEG-4/H.263 CODEC MSB Base Address
MP4+0314h
30
RO
14
29
28
27
26
RO
13
RO
12
RO
11
RO
10
R/W
R/W
R/W
MT
K
Bit
31
Name
Type RO
Bit
15
Name
Type R/W
MP4_CORE_VO
P_ADDR
Current VOP Base Address Register
R/W
R/W
25
24
23
VOP
RO
RO
RO
9
8
7
VOP
R/W R/W R/W
485/616
22
21
20
19
18
17
16
RO
6
RO
5
RO
4
RO
3
RO
2
R/W
R/W
R/W
R/W
R/W
R/W
1
-
R/W
0
-
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MT6228 GSM/GPRS Baseband Processor Data Sheet Revision 1.0
This register describes the starting address of Current VOP Frame that is going to be encoded. Note that this base address
should be 4-byte aligned. And the required frame buffer size should be: numbers of pixel per frame * 1.5 bytes (YUV420
format).
Current VOP Base Address.
Bit
31
Name
Type RO
Bit
15
Name
Type R/W
MP4_CORE_RE
F_ADDR
Core Reference VOP Base Address Register
30
29
28
27
26
RO
14
RO
13
RO
12
RO
11
RO
10
R/W
R/W
R/W
R/W
R/W
25
24
23
REF
RO
RO
RO
9
8
7
REF
R/W R/W R/W
22
21
20
19
18
17
16
RO
6
RO
5
RO
4
RO
3
RO
2
R/W
R/W
R/W
R/W
R/W
R/W
1
-
R/W
0
-
fo
r
MP4+0318h
Re
lea
se
VOP
This register describes the starting address of Reference VOP Frame. Note that this base address should be 4-byte aligned.
And the required frame buffer size should be: numbers of pixel per frame * 1.5 bytes (YUV420 format).
Reference VOP Base Address.
MP4+031Ch
Bit
31
Name
Type RO
Bit
15
Name
Type R/W
Core Reconstructed VOP Base Address Register
30
29
28
27
26
RO
14
RO
13
RO
12
RO
11
RO
10
R/W
R/W
R/W
R/W
R/W
25
24
23
REC
RO
RO
RO
9
8
7
REC
R/W R/W R/W
Co
nf
id
en
tia
l
REF
MP4_CORE_RE
C_ADDR
22
21
20
19
18
17
16
RO
6
RO
5
RO
4
RO
3
RO
2
R/W
R/W
R/W
R/W
R/W
R/W
1
-
R/W
0
-
This register describes the starting address of Reconstructed VOP Frame. Note that this base address should be 4-byte
aligned. And the required frame buffer size should be: numbers of pixel per frame * 1.5 bytes (YUV420 format).
REC
Reconstructed VOP Base Address.
MP4+0320h
Bit
31
Name
Type RO
Bit
15
Name
Type R/W
MP4_CORE_DE
BLOCK_ADDR
Core Deblocking Base Address Register
30
RO
14
R/W
29
28
27
RO
13
RO
12
RO
11
R/W
R/W
R/W
26
25
24
23
22
DEBLOCK_ADDR
RO
RO
RO
RO
RO
10
9
8
7
6
DEBLOCK_ADDR
R/W R/W R/W R/W R/W
21
20
19
18
17
16
RO
5
RO
4
RO
3
RO
2
R/W
R/W
R/W
R/W
R/W
1
-
R/W
0
-
This register describes the starting address of deblocking frame. Note that this base address should be 4-byte aligned. And
the required frame buffer size should be: numbers of pixel per frame * 1.5 bytes (YUV420 format).
Deblocking Base Address.
MT
K
DEBLOCK_ADDR
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MP4_CORE_DA
Core VLE Data Load-Store LSB Base Address Register TA_STORE_AD
DR
30
29
28
27
26
14
13
12
11
10
R/W
R/W
R/W
R/W
R/W
25
24
23
STORE
9
8
STORE
R/W R/W
22
21
20
19
7
6
5
4
3
R/W
R/W
R/W
R/W
18
17
16
2
R/W
1
-
R/W
0
-
fo
r
MP4+0324h
Bit
31
Name
Type
Bit
15
Name
Type R/W
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MT6228 GSM/GPRS Baseband Processor Data Sheet Revision 1.0
R/W
R/W
Re
lea
se
This register describes the LSB address of VLE Data Load-Store buffer in data-partitioned mode. Note that this base
address should be 4-byte aligned. And the required buffer size for encoder and decoder should be: 3K bytes and number of
macroblock per frame * 32 bytes, respectively.
STORE LSB address of VLE Data Load-Store buffer
Core DC/AC Prediction Storage LSB Base Address
Register
MP4+0328h
Bit
31
Name
Type
Bit
15
Name
Type R/W
30
29
28
27
26
14
13
12
11
10
R/W
R/W
R/W
R/W
R/W
25
24
23
DACP
9
8
DACP
R/W R/W
MP4_CORE_DA
CP_ADDR
22
21
20
19
18
17
16
7
6
5
4
3
2
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1
-
R/W
0
-
Co
nf
id
en
tia
l
This register describes the LSB address of DC/AC Prediction Storage buffer. Note that this base address should be 4-byte
aligned. And the required buffer size for encoder and decoder should be: 512 bytes and 2K bytes, respectively.
DACP LSB address of DC/AC Prediction Storage buffer
Core Motion Vector Storage LSB Base Address
Register
MP4+032Ch
Bit
31
Name
Type
Bit
15
Name
Type R/W
30
14
R/W
29
28
27
26
13
12
11
10
R/W
R/W
R/W
R/W
25
24
23
MVD_ADDR
9
8
MVD_ADDR
R/W R/W
MP4_CORE_MV
P_ADDR
22
21
20
19
18
17
16
7
6
5
4
3
2
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1
-
R/W
0
-
This register describes the LSB address of Motion Vector Storage buffer. Note that this base address should be 4-byte
aligned. And the required buffer size for encoder should be mb_x_limit * 2 * 4 bytes, which equals to 320 Bytes for VGA
size.
LSB address of Motion Vector Storage buffer
6.17.2.4.2
Data Structure
MT
K
MVD_ADDR
MP4+0330h
Bit
31
MP4_CORE_VO
P_STRUCT0
Core VOP Structure 0 Register
30
29
28
27
26
25
24
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22
21
20
19
18
17
16
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Name
-
-
-
-
-
-
-
-
-
-
-
Type
Bit
15
14
13
12
11
10
9
8
7
6
5
R/W
R/W
Name
Type
VLCTHR
R/W
R/W
QUANT
R/W
R/W
R/W
R/W
-
-
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MT6228 GSM/GPRS Baseband Processor Data Sheet Revision 1.0
-
ROUN
D
R/W
0
4
3
2
1
SHOR
FCODE
RVLC DATA TYPE
T
R/W R/W R/W R/W R/W R/W R/W R/W
fo
r
This register is used to describe the header information of a certain Video Object Plane that is going to be processed by
video CODEC.
MP4+0334h
Bit
31
Name
Type
Bit
15
Name
Type R/W
Co
nf
id
en
tia
l
Re
lea
se
TYPE vop_coding_type definition, for both decode and encode.
0 This is a P-VOP frame (inter frame)
1 This is an I-VOP frame (intra frame)
DATA data_partitioned, for decode only.
0 Data stream is in non-data-partitioned mode
1 Data stream is in data-partitioned mode
RVLC resversible_vlc, for decode only.
0 Data stream contains no reversible VLC information
1 Data stream uses reversible VLC tables.
SHORT short_video_header; for both decode and encode
0 Normal MPEG-4 format
1 H.263 Compatible format
FCODE fcode size setting for both decode and encode, ranges from 0 to 7.
QUANT vop_quant. For both decode and encode. Quantizer scale of the current frame. For variable Q in decode mode,
QUANT is an initial setting of the current frame.
VLCTHR intra_dc_vlc_thr. For decode only. According to VLCTHR, the decoder has to switch from intra DC mode to
inter DC mode when the quantizer_scale is larger than a pre-defined value. VLCTHR ranges from 0 to 7.
ROUND
Rounding type of half-pel motion compensation. ROUND==1 means truncation toward zero (the pixel value
is always larger than 0); ROUND==0 means rounding-off addition.
MP4_CORE_VO
P_STRUCT1
Core VOP Structure 1 Register
30
-
14
R/W
29
-
13
R/W
28
R/W
12
R/W
27
26
25
HECBIT
R/W R/W R/W
11
10
9
YLIMIT
R/W R/W R/W
24
R/W
8
R/W
23
-
22
-
21
-
20
-
7
R/W
6
R/W
5
R/W
4
R/W
19
18
17
MBLENGTH
R/W R/W R/W
3
2
1
XLIMIT
R/W R/W R/W
16
R/W
0
R/W
This register is used by software program to control the start position and count limit of macroblock for a certain Video
Packet or Video Object Plane that is going to be processed by video CODEC.
MT
K
XLIMIT Macroblock count in X direction of a frame.
YLIMIT Macroblock count in Y direction of a frame.
MBLENGTH
Bit count of Macroblock Number in Video Packet Header. It is a value defined by the following formula:
MBCNT = (XLIMIT+15)/16 * (YLIMIT+15)/16. For larger MBCNT, we have larger MBLENGTH.
MBLENGTH is ranged from 1 to 14.
HECBIT
Bit count of extension header code in Video Packet Header
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MP4+0338h
MP4_CORE_VO
P_STRUCT2
Core VOP Structure 2 Register
31
-
30
-
29
-
28
-
27
-
15
-
14
-
13
-
12
11
R/W
26
-
25
-
10
9
VP_YPOS
R/W R/W R/W
24
23
22
R/W
8
R/W
7
-
R/W
6
-
R/W
21
20
19
18
17
MBNO
R/W R/W R/W R/W R/W
5
4
3
2
1
VP_XPOS
R/W R/W R/W R/W
16
R/W
0
R/W
fo
r
Bit
Name
Type
Bit
Name
Type
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MT6228 GSM/GPRS Baseband Processor Data Sheet Revision 1.0
This register is used by software program to control the start position and count limit of macroblock for a certain Video
Packet or Video Object Plane that is going to be processed by video CODEC.
MP4+033Ch
Bit
Name
Type
Bit
Name
Type
Re
lea
se
VP_XPOS Starting position of current Video Packet in X coordinate that the SW wants to update.
VP_YPOS Starting position of current Video Packet in Y coordinate that the SW wants to update.
MBNO
Macroblock count limit for a video packet or frame. For a CIF frame the value will be 396.
Core VOP Structure 3 Register
31
-
30
-
29
-
28
-
27
-
26
-
25
-
24
15
-
14
-
13
-
12
11
9
RO
8
RO
RO
10
YPOS
RO
RO
RO
23
22
RO
7
-
RO
6
-
21
20
MBNO
RO
RO
5
4
RO
MP4_CORE_VO
P_STRUCT3
19
18
17
16
RO
3
RO
2
XPOS
RO
RO
1
RO
0
RO
RO
RO
Co
nf
id
en
tia
l
This register provides the position and count information of a certain macroblock that is currently under process of video
CODEC.
XPOS Current Macroblock Position in X coordinate
YPOS Current Macroblock Position in Y coordinate
MBNO Current Macroblock Count
MP4+0340h
Bit
Name
Type
Bit
MP4_CORE_MB
_STRUCT0
Core MB Structure 0 Register
31
-
30
-
15
14
29
-
28
-
13
12
DCVL
Name QUANTIZER
AC
C
Type R/W R/W R/W R/W
27
-
26
-
25
-
24
-
23
-
22
-
21
-
20
-
19
-
11
10
9
8
7
6
5
4
3
R/W
R/W
R/W
DQUANT
R/W
R/W
PATTERN
R/W
R/W
R/W
R/W
18
17
16
QUANTIZER
R/W R/W R/W
2
1
0
CODE
TYPE
D
R/W R/W R/W
MT
K
This register is used to store the header information of current macroblock. This register is mostly used for debugging. Also
used to provide hardware certain header information if all header parsing is done by software instead of hardware.
CODED
not_coded flag of current macroblock; not_coded can be decoded by hardware from macroblock header.
TYPE
mb_coding_type of current macroblock; mb_coding_type can be decoded by hardware from mcbpc in
macroblck header.
PATTERN pattern_code of current macroblock; pattern_code can be decoded by hardware from cbpc and cbpy in
macroblock header.
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MT6228 GSM/GPRS Baseband Processor Data Sheet Revision 1.0
DQUANT
dquant. It can be –2, -1, +1 or +2; total 4 possible choices using 2 bits to represent; dquant can be decoded by
hardware from macroblock header.
AC
ac_pred_flag. It decides whether AC prediction is needed; always 0 in encoder; ac_pred_flag can be decoded
by hardware from macroblock header.
DCVLC
use_intra_dc_vlc. If this bit is 0, intra AC VLC decode is used (no intra DC exists in current macroblock).
QUANTIZER quantizer_scale, ranged from 1 to 31. It can be variable if we have dquant values.
31
-
30
-
29
-
28
-
15
-
14
-
13
-
12
-
27
26
25
24
23
R/W
11
R/W
10
R/W
9
R/W
8
R/W
7
R/W
R/W
R/W
R/W
22
21
DC[1]
R/W R/W
6
5
DC[0]
R/W R/W
fo
r
Bit
Name
Type
Bit
Name
Type
MP4_CORE_MB
_STRUCT1
Core MB Structure 1 Register
20
19
18
17
16
R/W
4
R/W
3
R/W
2
R/W
1
R/W
0
R/W
R/W
R/W
Re
lea
se
MP4+0344h
R/W
R/W
R/W
This register is used to store the DC value set 0 and 1 of current macroblock.
DC[0] DC Value for Luminance Block 0
DC[1] DC Value for Luminance Block 1
MP4+0348h
31
-
30
-
29
-
28
-
15
-
14
-
13
-
12
-
27
26
25
24
23
R/W
11
R/W
10
R/W
9
R/W
8
R/W
7
R/W
R/W
R/W
R/W
R/W
Co
nf
id
en
tia
l
Bit
Name
Type
Bit
Name
Type
Core MB Structure 2 Register
22
21
DC[3]
R/W R/W
6
5
DC[2]
R/W R/W
MP4_CORE_MB
_STRUCT2
20
19
18
17
16
R/W
4
R/W
3
R/W
2
R/W
1
R/W
0
R/W
R/W
R/W
R/W
R/W
This register is used to store the DC value set 2 and 3 of current macroblock. For debug purpose or SW encode/decode
procedure.
DC[2] DC Value for Luminance Block 2
DC[3] DC Value for Luminance Block 3
MP4+034Ch
Bit
Name
Type
Bit
Name
Type
31
-
30
-
15
-
14
-
MP4_CORE_MB
_STRUCT3
Core MB Structure 3 Register
29
-
28
-
13
-
12
-
27
26
25
24
23
R/W
11
R/W
10
R/W
9
R/W
8
R/W
7
R/W
R/W
R/W
R/W
R/W
22
21
DC[5]
R/W R/W
6
5
DC[4]
R/W R/W
20
19
18
17
16
R/W
4
R/W
3
R/W
2
R/W
1
R/W
0
R/W
R/W
R/W
R/W
R/W
MT
K
This register is used to store the DC value set 4 and 5 of current macroblock. For debug purpose or SW encode/decode
procedure.
DC[4] DC Value for Chrominance Block 4
DC[5] DC Value for Chrominance Block 5
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MP4+0350h
MP4_CORE_MB
_STRUCT4
Core MB Structure 4 Register
31
-
30
-
29
-
28
-
27
-
26
-
25
-
24
-
15
-
14
-
13
-
12
-
11
-
10
-
9
-
8
-
23
22
21
R/W
7
R/W
6
R/W
5
R/W
R/W
R/W
20
19
MVY[0]
R/W R/W
4
3
MVX[0]
R/W R/W
18
17
16
R/W
2
R/W
1
R/W
0
R/W
R/W
R/W
fo
r
Bit
Name
Type
Bit
Name
Type
Ko
nk
a
MT6228 GSM/GPRS Baseband Processor Data Sheet Revision 1.0
This register is used to store the motion vector set 0 of current macroblock. For debug purpose or SW encode/decode
procedure.
MP4+0354h
Bit
Name
Type
Bit
Name
Type
Core MB Structure 5 Register
31
-
30
-
29
-
28
-
27
-
26
-
25
-
24
-
15
-
14
-
13
-
12
-
11
-
10
-
9
-
8
-
Re
lea
se
MVX[0] X Component of Motion Vector Set 0
MVY[0] Y Component of Motion Vector Set 0
23
22
21
R/W
7
R/W
6
R/W
5
R/W
R/W
R/W
20
19
MVY[1]
R/W R/W
4
3
MVX[1]
R/W R/W
MP4_CORE_MB
_STRUCT5
18
17
16
R/W
2
R/W
1
R/W
0
R/W
R/W
R/W
This register is used to store the motion vector set 1 of current macroblock. For debug purpose or SW encode/decode
procedure.
MP4+0358h
Bit
Name
Type
Bit
Name
Type
Co
nf
id
en
tia
l
MVX[1] X Component of Motion Vector Set 1
MVY[1] Y Component of Motion Vector Set 1
MP4_CORE_MB
_STRUCT6
Core MB Structure 6 Register
31
-
30
-
15
-
14
-
29
-
28
-
27
-
26
-
25
-
24
-
13
-
12
-
11
-
10
-
9
-
8
-
23
22
21
R/W
7
R/W
6
R/W
5
R/W
R/W
R/W
20
19
MVY[2]
R/W R/W
4
3
MVX[2]
R/W R/W
18
17
16
R/W
2
R/W
1
R/W
0
R/W
R/W
R/W
This register is used to store the motion vector set 2 of current macroblock. For debug purpose or SW encode/decode
procedure.
MVX[2] X Component of Motion Vector Set 2
MVY[2] Y Component of Motion Vector Set 2
Bit
Name
Type
Bit
MP4_CORE_MB
_STRUCT7
Core MB Structure 7 Register
MT
K
MP4+035Ch
31
-
30
-
29
-
28
-
27
-
26
-
25
-
24
-
15
14
13
12
11
10
9
8
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23
22
21
R/W
7
R/W
6
R/W
5
20
19
MVY[3]
R/W R/W
4
3
18
17
16
R/W
2
R/W
1
R/W
0
MediaTek Inc. Confidential
Name
Type
-
-
-
-
-
-
-
-
R/W
R/W
R/W
MVX[3]
R/W R/W
Ko
nk
a
MT6228 GSM/GPRS Baseband Processor Data Sheet Revision 1.0
R/W
R/W
R/W
This register is used to store the motion vector set 3 of current macroblock. For debug purpose or SW encode/decode
procedure.
MVX[3] X Component of Motion Vector Set 3
MVY[3] Y Component of Motion Vector Set 3
MP4+0370h
MP4_CORE_VL
C_DMA_STS
Core VLC DMA Status Register
Bit
Name
Type
Bit
31
30
RO
15
RO
14
Name
-
-
Type
fo
r
VLC DMA
29
28
27
26
25
RO
RO
RO
RO
RO
13
12
11
10
9
GLCO GDRD
EMPT
FULL
VLD
MD
Y
Y
RO
RO
RO
RO
RO
24
23
GADDR_LSB
RO
RO
8
7
22
21
20
19
18
17
16
RO
6
RO
5
RO
4
RO
3
RO
2
RO
1
RO
0
RO
RO
Re
lea
se
6.17.2.5
VLE PACK GREQ
RO
RO
RO
STATE
RO
RO
RO
RO
This register provides software program the information of current status of VLD DMA.
MT
K
Co
nf
id
en
tia
l
STATE State of VLC DMA Engine.
GREQ request for data read/write.
0 No request.
1 Request for data read/write.
PACK VLE Buffer Maximum Size Meet.
VLE
VLE Stream Ready
0 VLE is not ready
1 VLE is ready
VLD
VLD Stream Ready
0 VLD is not ready
1 VLD is ready
EMPTY FIFO Empty
0 VLC DMA FIFO is not empty
1 VLC DMA FIFO is empty
FULL FIFO Full
0 VLC DMA FIFO is not full
1 VLC DMA FIFO is full
GDRDY
Waiting for gdrdy, a signal from GMC, to return.
0 gdrdy has been received.
1 Waiting for gdrdy to return.
GLCOMD Waitinf for glcomd, a signal from GMC, to return.
0 glcomd has been received.
1 Waiting for glcomd to return.
GADDR_LSB Lower 16 bit value of gaddr, a signal to GMC.
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MP4+0374h
MP4_CORE_VL
E_STS
Core VLE Status Register
31
30
29
28
27
26
25
24
23
22
21
20
19
RO
15
RO
14
RO
12
RO
11
RO
10
RO
5
RO
4
RO
RO
RO
RO
RO
RO
RO
9
8
7
RELOAD_CNT
RO
RO
RO
RO
6
RO
RO
13
GREQ
RO
RO
RO
RO
RO
3
DONE
RO
This register shows the status of MPEG4 VLE block and is used for hardware debugging.
MP4+0378h
Bit
Name
Type
Bit
Name
Type
Re
lea
se
STATE VLE State
DONE DC/AC coefficient reload done.
RELOAD_CNT DC/AC coefficient reload count.
GREQ VLE request to GMC.
Core VLC DMA Base Address Register
31
30
29
28
27
26
WO
15
WO
14
WO
13
WO
12
WO
11
WO
10
WO
WO
WO
WO
WO
WO
25
24
23
BASE
WO
WO
WO
9
8
7
BASE
WO
WO
WO
18
17
16
RO
2
RO
RO
1
0
STATE
RO
RO
RO
fo
r
Bit
Name
Type
Bit
Name
Type
Ko
nk
a
MT6228 GSM/GPRS Baseband Processor Data Sheet Revision 1.0
MP4_CORE_VL
C_BASE_ADDR
22
21
20
19
18
17
16
WO
6
WO
5
WO
4
WO
3
WO
2
WO
WO
WO
WO
WO
WO
1
-
WO
0
-
Co
nf
id
en
tia
l
This register is used to describe the address of started Code Word for each VLC DMA buffer. Note that this base address
should be 4-byte aligned.
BASE VLC DMA Base Address
MP4+037Ch
Bit
Name
Type
Bit
Name
Type
MP4_CORE_VL
C_BASE_BITCN
T
Core VLC DMA Base Bit Count Register
31
-
30
-
15
-
14
-
29
-
28
-
27
-
26
-
25
-
24
-
23
-
22
-
21
-
20
-
19
-
18
-
17
-
16
-
13
-
12
-
11
-
10
-
9
-
8
-
7
-
6
-
5
-
4
3
1
0
WO
WO
2
BIT
WO
WO
WO
This register is used to describe the starting bit position of the 1st Code Word in the 1st VLC DMA buffer. For the following
VLC DMA buffers, it is assumed that they are all 4-byte aligned and always start from bit position “0”.
Start of Bit at the 1st Code Word of 1st DMA Buffer
BIT
Bit
Name
Type
Reset
MP4_CORE_VL
C_LIMIT
Core VLC DMA Buffer Limit Register
MT
K
MP4+0380h
31
-
30
-
29
-
28
-
27
-
26
-
25
-
24
-
23
-
22
-
21
-
20
-
19
-
18
-
17
-
16
-
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
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Bit
15
Name
Type R/W
1
Reset
14
13
12
11
10
9
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
8
7
LIMIT
R/W R/W
1
1
6
5
4
3
R/W
1
R/W
1
R/W
1
R/W
1
Ko
nk
a
MT6228 GSM/GPRS Baseband Processor Data Sheet Revision 1.0
2
1
0
R/W
1
R/W
1
R/W
1
This register is used to describe the buffer size of each VLC DMA buffer. Note that the value is counted in word (32-bit).
Whenever the limit is reached and the corresponding interrupt control is enabled, an interrupt request will be generated.
Bit
Name
Type
Bit
Name
Type
MP4_CORE_VL
C_WORD
Core VLC DMA Current Word Register
31
30
29
28
27
26
RO
15
RO
14
RO
13
RO
12
RO
11
RO
10
RO
RO
RO
RO
RO
RO
25
24
23
ADDR
RO
RO
RO
9
8
7
ADDR
RO
RO
RO
22
21
20
19
18
17
16
RO
6
RO
5
RO
4
RO
3
RO
2
RO
RO
RO
RO
RO
RO
1
-
RO
0
-
Re
lea
se
MP4+0384h
fo
r
LIMIT DMA Buffer Size, Count in Word (32-bit)
This register provides the address information of a certain code word that is under process of video CODEC. SW reads it
back after encode of a frame is done.
ADDR VLC DMA current Address
Bit
Name
Type
Bit
Name
Type
Core VLC DMA Current Bit Count Register
31
-
30
-
15
-
14
-
29
-
28
-
27
-
26
-
25
-
24
-
23
-
Co
nf
id
en
tia
l
MP4+0388h
13
-
12
-
11
-
10
-
9
-
8
-
7
-
22
-
21
-
20
-
19
-
6
-
5
-
4
3
RO
MP4_CORE_VL
C_BITCNT
18
-
17
-
16
-
2
1
BITCNT
RO
RO
RO
0
RO
This register provides the bit position information of a certain Code Word that is under process of video CODEC.
BITCNT
Current Bit Count
MP4+038Ch
30
Core VLC DMA Ring Buffer Ending Address Register
29
28
27
26
R/W
1
14
R/W
1
13
R/W
1
12
R/W
1
11
R/W
1
10
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
25
24
23
22
JUMP_FROM_ADDR
R/W R/W R/W R/W
1
1
1
1
9
8
7
6
JUMP_FROM_ADDR
R/W R/W R/W R/W
1
1
1
1
21
20
19
18
17
16
R/W
1
5
R/W
1
4
R/W
1
3
R/W
1
2
R/W
1
1
R/W
1
0
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
MT
K
Bit
31
Name
Type R/W
Reset
1
Bit
15
Name
Type R/W
Reset
1
MP4_CORE_VL
C_JUMP_FROM
_ADDR
JUMP_FROM_ADDR
The ending address of the current DMA buffer; when a jump takes place in VLC DMA
address counter, the address will jump from the ending address of the current DMA buffer, which is
JUMP_FROM_ADDR, to the starting address of the next DMA buffer, which is JUMP_TO_ADDR. To disable the
494/616
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Ko
nk
a
MT6228 GSM/GPRS Baseband Processor Data Sheet Revision 1.0
ring buffer feature, set this register to all ones; note that the address counter will not jump until done with the
content in memory with address as JUMP_FROM_ADDR. So the memory content with address
JUMP_FROM_ADDR will be executed by hardware.
30
29
28
27
26
R/W
1
14
R/W
1
13
R/W
1
12
R/W
1
11
R/W
1
10
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
25
24
23
22
JUMP_TO_ADDR
R/W R/W R/W R/W
1
1
1
1
9
8
7
6
JUMP_TO_ADDR
R/W R/W R/W R/W
1
1
1
1
21
20
19
18
17
16
R/W
1
5
R/W
1
4
R/W
1
3
R/W
1
2
R/W
1
1
R/W
1
0
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
fo
r
Bit
31
Name
Type R/W
Reset
1
Bit
15
Name
Type R/W
Reset
1
Core VLC DMA Ring Buffer Starting Address Register
Re
lea
se
MP4+0390h
MP4_CORE_VL
C_JUMP_TO_A
DDR
JUMP_TO_ADDR The starting address of the next DMA buffer; when a jump takes place in VLC DMA address
counter, the address will jump from the ending address of the current DMA buffer, which is JUMP_FROM_ADDR,
to the starting address of the next DMA buffer, which is JUMP_TO_ADDR; note that the address counter will not
jump until done with the content in memory with address as JUMP_FROM_ADDR. So the memory content with
address JUMP_FROM_ADDR will be executed by hardware.
Software Decode Mode
MP4+0400h
Software Decode Mode Command Register
Bit
31
30
Name
-
-
Type
Bit
15
14
Name
-
-
Type
Co
nf
id
en
tia
l
6.17.2.6
29
28
27
26
25
24
23
22
21
20
-
-
-
-
-
-
-
-
-
-
13
12
11
10
5
4
-
-
-
-
AC
CBPY
WO
WO
9
8
7
6
CODE MCBP QUAN
DCT
D
C
T
WO
WO
WO
WO
19
MP4_SVLD_CO
MD
18
17
16
STAR
STOP
T
WO
WO
3
2
1
0
DMAR MMAR FLUS
MV
K
K
H
WO
WO
WO
WO
MT
K
For SW decode mode, the following control bits must be sent to HW for block-based decoding. The sequencer (or header
parser) of HW does not decode the following information by itself.
FLUSH flush bits
MMARK
Motion Marker
DMARK
DC Marker
MV
Motion Vector
CBPY cbpy
AC
ac_pred_flag
DCT
dct_coefficient
QUANT dquant
MCBPC
mcbpc
CODED
not_coded
START Block Decode Start
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STOP Block Decode Stop
MP4+0404h
31
-
30
-
29
-
28
-
27
-
26
-
25
-
24
-
23
-
22
-
21
-
20
-
19
-
15
-
14
-
13
-
12
-
11
-
10
-
9
-
8
-
7
-
6
-
5
-
4
3
R/W
Number of Bits should be flushed
MP4+0408h
31
-
30
-
29
-
28
-
27
-
26
-
25
-
24
-
15
14
13
12
11
10
9
8
Name
-
-
-
-
-
-
-
-
Type
RESYN Resync Marker
MV
Motion Marker
DC
DC Marker
19
-
18
-
17
-
16
-
7
6
5
4
3
2
1
-
-
-
-
-
DC
MV
RO
RO
0
RESY
N
RO
15
14
RO
RO
RO
14
RO
RO
28
27
26
25
RO
13
RO
12
RO
11
RO
10
RO
9
RO
RO
RO
RO
RO
MP4_SVLD_MA
RK
20
-
30
-
RO
15
29
R/W
21
-
31
-
30
0
22
-
MP4_SVLD_CO
DE
Software Decode Mode VLD Code Word Register
31
16
-
23
-
Co
nf
id
en
tia
l
MP4+040Ch
17
-
2
1
BITCNT
R/W R/W R/W
Software Decode Mode Marker Indication Register
Bit
Name
Type
Bit
18
-
fo
r
BITCNT
Bit
Name
Type
Bit
Name
Type
MP4_SVLD_BIT
CNT
Software Decode Mode Bit Count Register
Re
lea
se
Bit
Name
Type
Bit
Name
Type
Ko
nk
a
MT6228 GSM/GPRS Baseband Processor Data Sheet Revision 1.0
24
23
CODE
RO
RO
8
7
CODE
RO
RO
22
21
20
19
18
17
16
RO
6
RO
5
RO
4
RO
3
RO
2
RO
1
RO
0
RO
RO
RO
RO
RO
RO
RO
CODE Current Code Word in VLD Stream, MSB Aligned
6.17.2.6.1
Debug
MP4+0500h
29
-
28
-
27
-
26
-
13
12
11
RO
RO
RO
MT
K
Bit
Name
Type
Bit
Name
Type
Motion Estimation SAD for Y Component Register
MP4+0504h
Bit
Name
31
-
25
24
23
10
RO
9
RO
RO
RO
RO
8
7
SADY
RO
RO
MP4_SAD_Y
22
21
20
19
INTRA_MB_NUM
RO
RO
RO
RO
6
5
4
3
18
17
16
RO
2
RO
1
RO
0
RO
RO
RO
RO
RO
RO
RO
Motion Estimation SAD for U Component Register
30
-
29
-
28
-
27
-
26
-
25
-
24
-
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23
-
22
-
21
-
20
-
MP4_SAD_U
19
-
18
-
17
-
16
-
MediaTek Inc. Confidential
15
14
13
12
11
10
9
RO
RO
RO
RO
RO
RO
RO
MP4+0508h
Bit
Name
Type
Bit
Name
Type
8
7
SADU
RO
RO
6
5
4
3
RO
RO
RO
RO
Motion Estimation SAD for V Component Register
2
1
0
RO
RO
RO
MP4_SAD_V
31
-
30
-
29
-
28
-
27
-
26
-
25
-
24
-
23
-
22
-
21
-
20
-
19
-
15
14
13
12
11
10
9
6
5
4
3
RO
RO
RO
RO
RO
RO
RO
8
7
SADV
RO
RO
RO
RO
RO
RO
18
-
17
-
16
-
2
1
0
RO
RO
RO
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Type
Bit
Name
Type
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MT6228 GSM/GPRS Baseband Processor Data Sheet Revision 1.0
SADV
Re
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INTRA_MB_NUM
Total number of intra macro-block in a P frame. This register is valid after a P frame finishes
encoding. Software can decide whether to re-encode current P frame as I frame by examining this register.
SADY
SAD of luminance (Y) macroblock, for the purpose of debugging
SADU
SAD of chrominance (U) macroblock, for the purpose of debugging
SAD of chrominance (V) macroblock, for the purpose of debugging
6.17.2.6.2
Resync Marker
MP4+0600h
MPEG4 Core Resync Marker Configuration 0 Register
EN
28
27
26
R/W
1
12
R/W
1
11
R/W
1
10
R/W
1
R/W
1
R/W
1
25
24
23
22
21
PERIOD_BITS
R/W R/W R/W R/W R/W
1
1
1
1
1
9
8
7
6
5
PERIOD_BITS
R/W R/W R/W R/W R/W
1
1
1
1
1
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Bit
31
30
29
Name EN MODE
Type R/W R/W R/W
0
0
1
Reset
Bit
15
14
13
Name
Type R/W R/W R/W
Reset
1
1
1
MP4_CORE_RE
SYNC_CONF0
20
19
18
17
16
R/W
1
4
R/W
1
3
R/W
1
2
R/W
1
1
R/W
1
0
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
Resync marker insertion enable
0 Disable resync marker insertion
1 Enable resync marker insertion
MODE Resync Marker insertion mode selection
0 resync marker is inserted based on number of bits
1 resync marker is inserted based on number of macroblocks
PERIOD_BITS Period in number of bits to insert resync marker; only effective when MODE is set to 0; hardware will
insert resync marker at the next macroblock boundary once the bit length of a video packet exceeds this value.
MP4+0604h
30
R/W
0
14
29
R/W
0
13
MT
K
Bit
31
Name
Type R/W
Reset
0
Bit
15
Name
MPEG4 Core Resync Marker Configuration 1 Register
28
R/W
0
12
27
R/W
0
11
26
R/W
0
10
25
R/W
0
9
24
23
22
R/W R/W R/W
0
0
0
8
7
6
PERIOD_MB
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21
R/W
0
5
20
R/W
0
4
19
R/W
0
3
MP4_CORE_RE
SYNC_CONF1
18
R/W
0
2
17
R/W
0
1
16
HEC
R/W
0
0
MediaTek Inc. Confidential
Type R/W
Reset
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
HEC
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MT6228 GSM/GPRS Baseband Processor Data Sheet Revision 1.0
R/W
1
R/W
1
R/W
1
Bit
31
Name
Type R/W
Reset
0
Bit
15
Name
Type R/W
Reset
0
MPEG4 Core Local Time Base Register
30
R/W
0
14
29
R/W
0
13
28
R/W
0
12
27
R/W
0
11
26
R/W
0
10
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
25
24
23
22
21
20
MODULO_TIME_BASE
R/W R/W R/W R/W R/W R/W
0
0
0
0
0
0
9
8
7
6
5
4
VOP_TIME_INCREMENT
R/W R/W R/W R/W R/W R/W
0
0
0
0
0
0
MP4_CORE_TIM
E_BASE
19
R/W
0
3
17
BW
R/W R/W
0
0
2
1
R/W
0
0
R/W
0
R/W
0
R/W
0
Re
lea
se
MP4+060Ch
fo
r
Header Extension Code; indicates the value of header_extension_code in MPEG4 standard (ISO/IEC 14496-2)
0 header_extension_code is 0.
1 header_extension_code is 1.
PERIOD_MB Period in number of macroblocks (MB) to insert resync marker; only effective when MODE is set to 1;
hardware will insert resync marker at the next macroblock boundary once the number of macroblock in current
video packet exceeds this value.
18
R/W
0
16
MODULO_TIME_BASE Represent the value of modulo_time_base; value ranges from 0 to 31.
BW
Bit width of vop_time_increment. The real bit-width of vop_time_increment is (BW + 1), ranging from 1 to 16.
VOP_TIME_INCREMENT Carries the value of vop_time_increment defined in MPEG4 standard (ISO/IEC 14496-2); the
meaningful bit width of vop_time_increment is signaled by BW field.
TV Controller
6.18.1
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6.18
General Description
MT6228 supports NTSC/PAL interlaced TV format. The display function includes two components: a TV controller and a
TV encoder. The main functions of the TV controller are as follows:
1.
2.
Fetch the TV frame buffer.
•
In video playback mode, the source is from the video codec buffer in YUV420 format. In this mode, the TV
controller and MPEG4 decoder can also communicate to achieve the best performance.
•
In image playback mode, the source is in RGB565 format. In this mode, still images can be displayed. The
LCM controller can direct the image path to the TV controller. When the LCM controller sends frames to the
frame buffer as it does for the LCD display, the TV controller retrieves the frames for display.
Scale the frame size to fit the TV size. MT6228 adopts bilinear interpolation in both horizontal and vertical
dimension to scale up the frame. The user can adjust both the location and the size to achieve a suitable appearance.
MT
K
In NTSC mode, the ideal display area is 720(W) x 480(H), but the actual display area depends on the TV set. Some
boundary area may be invisible.In PAL mode, the ideal display area is 720(W) x 576(H); the actual display area also
depends on the TV set.
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MT6228 GSM/GPRS Baseband Processor Data Sheet Revision 1.0
TV frame updates consume a lot of bandwidth. For interlaced system, one frame contains 2 fields. In NTSC mode, the
field update rate is 59.94 frames per second (fps); the field update rate in PAL mode is 50 fps. Performance is bound by
the size of the source image. The larger the image size, the higher the bandwidth required to support the TV display.
The controller supports an arbitrary image size up to 640 pixels in height and 480 pixels in width.
Figure 36 depicts the block diagram of the TV controller.
fo
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APB bus
Video DMA
Re
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se
GMC bus
TV controller
Video scaler
TV encoder
YCbCr420 or
RGB565
YCbCr422
Figure 36 Block Diagram of the TV Encoder
Register Definitions
TVC+0000h
Bit
Name
Type
Reset
15
Co
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6.18.2
10 bit
Video DAC
TVC enable register
14
13
The register is double buffer.
12
11
10
9
8
7
TVC_ENA
6
5
4
3
2
1
0
TSEN TVEN
R/W R/W
0
0
At the start of each frame, the enable bit is latched into the active buffer and takes effect.
TSEN TV control test signal enable.
0 Disable the test signal display.
1 Enable the test signal display.
TVEN TV controller enable.
0 Disable the TV frame update and display.
1 Enable the TV frame update and display.
TVC reset control register
MT
K
TVC+0004h
Bit
Name
Type
Reset
15
14
13
12
11
10
9
TVC_RST
8
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7
6
5
4
3
2
1
0
RST
WO
0
MediaTek Inc. Confidential
The register is used to reset both the TV controller and the TV encoder.
RST
Reset control bit.
Bit
Name
Type
Reset
Bit
TVC control register
31
30
29
28
27
26
15
14
13
12
11
10
Name
Type
Reset
TVC_CON
25
24
9
8
AB_W AB_R
R
D
R/W R/W
0
0
23
22
7
6
21
20
19
18
5
4
3
2
BURS DPBU BLKO
NOIP
T
F
UT
R/W R/W R/W R/W
0
0
0
0
17
16
1
0
YUV_
M
R/W
0
fo
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TVC+0008h
This control bit is write-only.
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MT6228 GSM/GPRS Baseband Processor Data Sheet Revision 1.0
TVC+000Ch
31
15
TVC_YADR_SR
C
TVC Y data source address
30
29
MT
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Bit
Name
Type
Reset
Bit
Name
Type
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This register contains double buffer control, burst-mode control, buffer configuration, vertical interpolation control, and
color-space control.
AB_WR
Double buffer access control. Only five active buffers can be directly programmed through setting AB_WR:
TVC_YADR_SRC, TVC_SRCWIDTH, TVC_TARWIDTH, TVC_HCOEFX, TVC_HCOEFY.
0 Write write-buffer.
1 Write both write-buffer and active-buffer.
AB_RD Double buffer access control.
0 Read write-buffer.
1 Read active-buffer.
BURST Enable memory burst mode access. TVC supports 4-beat burst mode access to memory. Double buffer.
0 Disable burst mode access.
1 Enable burst mode access.
DPBUF Enable deeper buffer for better performance. Double buffer.
0 Disable deeper buffer.
1 Enable deeper buffer.
BLACKOUT
Fill the unfilled line buffer area with black pixels. Double buffer.
0 Do not fill with black pixels.
1 Fill with black pixels.
NOIP Bypass vertical interpolation. Enabling this bit reduces the average data access bandwidth by 2. Double buffer.
0 Enable vertical interpolation.
1 Bypass vertical interpolation.
YUV_M
Enable YUV mode. Double buffer.
0 RGB565 mode. For LCD dump buffer.
1 YUV420 mode. For MPEG buffer.
14
13
28
27
26
25
12
11
10
9
24
23
22
SRC_Y [31:16]
R/W
0
8
7
6
SRC_Y [15:0]
R/W
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21
20
19
18
17
16
5
4
3
2
1
0
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Reset
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MT6228 GSM/GPRS Baseband Processor Data Sheet Revision 1.0
0
This register is a double buffer. At the start of each frame, the enable bit is latched into the active buffer and takes effect.
In YUV mode, the register represents the Y source address. In RGB mode, the register represents the RGB source address.
31
30
29
28
27
26
25
15
14
13
12
11
10
9
24
23
22
SRC_U [31:16]
R/W
0
8
7
6
SRC_U [15:0]
R/W
0
21
20
5
4
19
18
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Bit
Name
Type
Reset
Bit
Name
Type
Reset
TVC_UADR_SR
C
TVC U data source address
3
Re
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TVC+0010h
2
17
16
1
0
This register is double buffer. At the start of each frame, the enable bit is latched into the active buffer and takes effect.
In YUV mode, the register represents the U source address. In RGB mode, this register has no function.
TVC+0014h
31
30
29
28
27
26
25
15
14
13
12
11
10
9
24
23
22
SRC_V [31:16]
R/W
0
8
7
6
SRC_V [15:0]
R/W
0
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Bit
Name
Type
Reset
Bit
Name
Type
Reset
TVC V data source address
TVC_VADR_SR
C
21
20
19
18
17
16
5
4
3
2
1
0
This register is double buffer. At the start of each frame, the enable bit is latched into the active buffer and takes effect.
In YUV mode, the register represents the V source address. In RGB mode, this register has no function.
TVC+0018h
Bit
Name
Type
Reset
15
TVC horizontal scaling coefficient X
14
13
12
11
10
9
8
7
TVC_HCOEFX
6
5
4
COEFX
R/W
0
3
2
1
0
This register is double buffer. At the start of each frame, the enable bit is latched into the active buffer and takes effect.
The scaling coefficients should follow the formula:
Ws (source width ) − 1
=
Wt (t arg et width) − 1
Y
Wt − 1 ,
256
X+
where X, Y are positive integers, and 0 < Y < Wt – 1.
MT
K
For example, if the user needs to scale the image width from 640 pixels to 720 pixels, the formula is:
371
227 +
639
719
,
=
719
256
giving values X=227 and Y=371.
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Bit
Name
Type
Reset
15
TVC horizontal scaling coefficient Y
14
13
This register is double buffer.
TVC+0020h
Bit
Name
Type
Reset
15
12
11
10
9
8
7
TVC_HCOEFY
6
13
3
2
1
0
At the start of each frame, the enable bit is latched into the active buffer and takes effect.
TVC vertical scaling coefficient X
14
5
4
COEFY
R/W
0
12
11
10
9
8
7
TVC_VCOEFX
6
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TVC+001Ch
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MT6228 GSM/GPRS Baseband Processor Data Sheet Revision 1.0
5
4
COEFX
R/W
0
3
2
1
0
TVC+0024h
Bit
Name
Type
Reset
15
TVC vertical scaling coefficient Y
14
13
TVC+0028h
15
12
11
10
9
8
7
6
5
4
COEFY
R/W
0
3
TVC frame source width control register
14
13
TVC_VCOEFY
2
1
0
At the start of each frame, the enable bit is latched into the active buffer and takes effect.
Co
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This register is double buffer.
Bit
Name
Type
Reset
Re
lea
se
This register is double buffer. At the start of each frame, the enable bit is latched into the active buffer and takes effect.
The scaling coefficients should follow the formula:
Y
X+
Hs ( source height ) − 1
Ht − 1 , X , Y ∈ positive in teger
=
Ht (t arg etn height ) − 1
256
12
11
10
9
8
7
6
TVC_SRCWIDTH
5
4
SRCWIDTH
R/W
0
3
2
1
0
This register is double buffer. At the start of each frame, the enable bit is latched into the active buffer and takes effect.
In YUV mode, the source width is a multiple of 16; in RGB mode, the source width is a multiple of 2.
TVC+002C
Bit
Name
Type
Reset
15
14
13
This register is double buffer.
15
12
11
10
9
8
7
6
5
4
SRCHEIGHT
R/W
0
3
14
13
2
1
0
At the start of each frame, the enable bit is latched into the active buffer and takes effect.
TVC frame target width control register
MT
K
TVC+0030
Bit
Name
Type
Reset
TVC_SRCHEIGH
T
TVC frame source height control register
12
11
10
9
8
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7
6
TVC_TARWIDTH
5
4
TARWIDTH
R/W
0
3
2
1
0
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MT6228 GSM/GPRS Baseband Processor Data Sheet Revision 1.0
This register is double buffer. At the start of each frame, the enable bit is latched into
the active buffer and takes effect.
15
14
13
This register is double buffer.
TVC+0038h
Bit
Name
Type
Reset
Bit
Name
Type
Reset
12
11
10
9
8
7
6
5
4
TARHEIGHT
R/W
0
3
2
1
0
At the start of each frame, the enable bit is latched into the active buffer and takes effect.
TVC start point control register
31
30
29
28
27
26
25
24
15
14
13
12
11
10
9
8
Re
lea
se
Bit
Name
Type
Reset
TVC_TARHEIGH
T
TVC frame target height control register
fo
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TVC+0034
23
22
7
6
21
20
START_PXL
R/W
0
5
4
START_LINE
R/W
0
TVC_START_PO
INT
19
18
17
16
3
2
1
0
TVC+003Ch
Bit
15
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This register is double buffer. At the start of each frame, the enable bit is latched into the active buffer and takes effect.
This register is used to control the position of frame displayed on TV. Setting START_PXL to 0 and START_LINE to
21(NTSC) or 22(PAL) aligns the frame to the top-left corner of display.
START_PXL Starting pixel position in a line.
START_LINE Starting line of display.
TVC register update control register
14
Name
Type
Reset
13
12
11
10
9
8
7
TVC_REG_RDY
6
5
4
3
2
1
0
REG_
RDY
R/W
0
This register indicates that the double buffer register data is ready to be latched into active buffer.
At the start of each frame, the hardware monitors the bit. If the bit is set to 1 by the software, the double buffer register is
latched into active buffer synchronously, and the REG_RDY bit is automatically cleared.
REG_RDY Double buffer control bit.
TVC+0040h
31
30
29
MT
K
Bit
Name
Type
Reset
Bit
Name
Type
Reset
Test signal region start line number control register 1
15
14
13
28
27
26
25
24
23
22
12
11
10
9
8
7
6
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21
20
SLINE1
R/W
0
5
4
SLINE0
RO
0
TVC_PTRN1
19
18
17
16
3
2
1
0
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MT6228 GSM/GPRS Baseband Processor Data Sheet Revision 1.0
The register specifies the starting line of the 1st and 2nd regions of the test signal to display. While the running line number
falls in the 1st region, the TV iteratively displays the 1st line buffer. While it falls in the 2nd region, the TV iteratively
displays the 2nd line buffer. The data in the line buffers is pre-filled by the user. The line length is 720 pixels.
SLINE1 The starting line of the 2nd region.
SLINE0 The starting line of the 1st region.
31
30
29
28
27
26
25
24
23
22
15
14
13
12
11
10
9
8
7
6
TVC_PTRN2
21
20
SLINE3
R/W
0
5
4
SLINE2
R/W
0
19
18
17
16
3
2
1
0
Re
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Bit
Name
Type
Reset
Bit
Name
Type
Reset
Test signal region start line number control register 2
fo
r
TVC+0044h
The register specifies the starting line of the 3rd and 4th regions of the test signal to display. While the running line number
falls in the 3rd region, the TV iteratively displays the 3rd line buffer. While it falls in the 4th region, the TV iteratively
displays the 4th line buffer. The data in the line buffers is pre-filled by the user. The line length is 720 pixels.
SLINE3 The starting line of the 4th region.
SLINE2 The starting line of the 3rd region.
Bit
Name
Type
Reset
15
Line buffer load control register
14
13
12
11
10
9
8
BUSY
RO
0
7
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TVC+0048h
6
5
4
3
LL3
WO
0
TVC_LINELOAD
2
LL2
WO
0
1
LL1
WO
0
0
LL0
WO
0
The register controls the data loading of the line buffer. Turn off TVEN and TSEN when performing the line loading
operation. The BUSY flag is asserted until the line loading operation is completed.
BUSY Line loading busy.
LL3
Writing one starts loading line buffer 3.
LL2
Writing one starts loading line buffer 2.
LL1
Writing one starts loading line buffer 1.
6.18.2.1
6.19
Writing one starts loading line buffer 0.
TV encoder
General Description
MT
K
6.19.1
LL0
TV encoder receives a YCbCr stream from the video scaler and encodes the stream into NTSC/PAL signal.
shows the block diagram of the TV encoder.
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MT6228 GSM/GPRS Baseband Processor Data Sheet Revision 1.0
APB bus
Video DMA
Video scaler
YCbCr420 or
RGB565
YCbCr422
Figure 37 Block Diagram of TV Encoder
6.19.2
Register Definitions
TVE+0000h
Encoder mode control
26
25
24
23
22
21
20
19
18
17
16
TVTYPE
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
R/W
0
0
0
0
0
0
0
0
0
0
0
11
10
9
8
7
6
5
4
3
2
1
0
SYDE
CUPO YLPO CLPO CLPS
SETU
ENCO
YDEL
CBON
L
F
N
N
EL
P
N
R/W
R/W
R/W R/W R/W R/W
R/W R/W R/W
0
0
0
0
0
0
0
0
0
TV type.
00 NTSC (525 lines, no phase alternation line)
01 PAL-M (525 lines, with phase alternation line)
10 PAL-C (625 lines, with phase alternation line)
11 PAL (625 lines, with phase alternation line)
U/V swap.
Blacker than black mode on.
Slew at the beginning and at the end of the horizontal active area off.
Delay of Y (half sample resolution).
Delay of Y (one sample resolution). (Recommended setting is 2.)
Chrominance (chroma) of component up-sample off.
Luminance (luma) low-pass filter on. (Recommended setting is 1.)
Chroma low-pass filter on. (Recommended setting is 1.)
Chroma low-pass filter coefficient selection.
7.5IRE setup enable. (M) NTSC and (M, N) PAL have a blanking pedestal.
MT
K
UVSWP
BLKER
SLOFF
SYDEL
YDEL
CUPOF
YLPON
CLPON
CLPSEL
SETUP
27
TVE_MODE
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Bit
31
30
29
28
Name
Type R/W R/W R/W R/W
Reset
0
0
0
0
Bit
15
14
13
12
UVSW BLKE SLOF
Name
P
R
F
Type R/W R/W R/W
Reset
0
0
0
TVTYPE
10 bit
Video DAC
TV encoder
Re
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GMC bus
fo
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TV controller
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CBON
ENCON
Enable the color bar.
Enable the TV encoder.
TVE+0004h
TVE_CSCALE
31
30
29
28
27
26
25
24
23
22
21
20
15
14
13
12
11
VSCALE
R/W
0x5A (90)
10
9
8
7
6
5
4
3
USCALE
R/W
0x5A (90)
Bit
31
DAC control
30
29
28
R/W
0
14
R/W
0
13
R/W
0
12
R/W
0
R/W
0
27
26
25
Name
Type R/W
Reset
0
Bit
15
Type R/W
Reset
0
TRIMSET
23
R/W R/W R/W R/W R/W
0
0
0
0
0
11
10
9
8
7
TEST
PLUG
_COM VPLUGREF _DET
P_EN
_EN
R/W R/W
R/W
R/W R/W
0
0
0
0
0
Co
nf
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Name
24
Re
lea
se
USCALE Scale of U (USCALE/128).
VSCALE Scale of V (VSCALE/128).
BLANK Luma data at this level (BLANKx4) is presented as blank.
TVE+0008h
19
18
17
BLANK
R/W
0x4
2
1
16
0
fo
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Bit
Name
Type
Reset
Bit
Name
Type
Reset
Scale control
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MT6228 GSM/GPRS Baseband Processor Data Sheet Revision 1.0
22
TVE_DACTRL
21
20
19
18
17
16
TRIMS
TRIM
ET
R/W R/W R/W
R/W
0
0
0
0
6
5
4
3
2
1
0
PDN_
PDN_
PDN_ PDN_ PDN_
DAC_
HAIBI
BGRE
DAC2 DAC1 DAC0
EN
AS
F
R/W R/W R/W R/W R/W R/W R/W
0
0
0
0
0
0
1
MT
K
Enable software trimming code setting.
0 Disable.
1 Enable.
TRIM
Trimming code for BGVref.
TEST_COMP_EN
Comparator test enable.
0
Disable.
1
Enable.
VPLUGREF
Plug-in detect threshold selection.
PLUG_DET_EN
Plug-in detect enable.
0
Disable.
1
Enable.
PDN_HAIBIAS Half bias current power down mode.
0
Power up.
1
Power down.
PDN_DAC2
DAC power down control.
0
Power up.
1
Power down.
PDN_DAC1
3/4 DAC power down control.
0
Power up.
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DAC_EN
TVE+000Ch
Bit
Name
Type
Reset
Bit
Name
Type
Reset
Burst level control
TVE_BURST
31
30
29
28
27
26
25
24
15
14
13
12
11
10
9
8
UPQINI Phase offset of the color burst.
BRSTLVL Color burst level.
TVE+0010h
Color frequency control
31
30
29
28
27
26
25
24
15
14
13
12
11
10
9
8
23
22
7
6
21
20
19
UPQINI
R/W
0
4
3
BRSTLVL
R/W
0x3A (58)
5
23
22
21
BFP2
R/W
0xdd0 (3536)
7
6
5
Co
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Bit
Name
Type
Reset
Bit
Name
Type
Reset
fo
r
PDN_BGREF
1
Power down.
1/2 DAC power down control.
0
Power up.
1
Power down.
BGVref power down control.
0
Power up.
1
Power down.
DAC enable.
Re
lea
se
PDN_DAC0
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MT6228 GSM/GPRS Baseband Processor Data Sheet Revision 1.0
20
18
17
16
2
1
0
TVE_FREQ
19
18
17
16
4
3
BFP1
R/W
0x10f (271)
2
1
0
Burst frequency control.
Burst frequency = 27MHz ×
BFP1 +
BFP2 +
4H
2048
X
625
,
where H is the pixel clock cycle number per line.
Use the following table to get BFP1 and BFP2 (in decimal).
TV type
H
NTSC
PAL
BFP2
1716
0
271
3536
1728
67
336
2061
Color burst frequency synthesis value 2.
Color burst frequency synthesis value 1.
TVE+0014h
Bit
BFP1
MT
K
BFP2
BFP1
X
31
Slew control
30
29
28
27
TVE_SLEW
26
25
24
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23
22
21
20
19
18
17
16
MediaTek Inc. Confidential
30
29
28
15
14
13
12
9
8
7
27
26
YLPF11
R/W
0x32 (-14)
11
10
25
24
9
8
23
22
2
7
6
1
0
TVE_YLPFC
21
20
19
18
YLPF10
R/W
0x2 (2)
3
2
5
4
Luma low-pass filter coefficients 12-15
31
30
29
15
14
13
YLPF15
YLPF14
YLPF13
YLPF12
28
27
26
YLPF15
R/W
0x2 (2)
12
11
10
YLPF13
R/W
0X3d (-3)
Luma low-pass filter coefficient 15.
Luma low-pass filter coefficient 14.
Luma low-pass filter coefficient 13.
Luma low-pass filter coefficient 12.
TVE+0030h
17
16
1
0
25
24
9
8
23
22
21
7
6
5
TVE_YLPFD
20
19
18
YLPF14
R/W
0x1e (30)
4
3
2
YLPF12
R/W
0X25 (-27)
31
30
15
14
29
13
28
27
YLPF19
R/W
0x90 (144)
12
11
YLPF17
R/W
0Xff (-1)
16
1
0
TVE_YLPFE
26
25
24
23
22
21
10
9
8
7
6
5
Luma low-pass filter coefficient 19.
Luma low-pass filter coefficient 18.
Luma low-pass filter coefficient 17.
Luma low-pass filter coefficient 16.
17
Signed integer.
Signed integer.
Signed integer.
Signed integer.
Luma low-pass filter coefficients 16-19
MT
K
YLPF19
YLPF18
YLPF17
YLPF16
10
Luma low-pass filter coefficient 11. Signed integer.
Luma low-pass filter coefficient 10. Signed integer.
TVE+002Ch
Bit
Name
Type
Reset
Bit
Name
Type
Reset
11
Luma low-pass filter coefficients 10-11
31
YLPF11
YLPF10
Bit
Name
Type
Reset
Bit
Name
Type
Reset
12
Begin cycle of valid pixel with slew rate control.
End cycle of valid pixel with slew rate control.
TVE+0028h
Bit
Name
Type
Reset
Bit
Name
Type
Reset
13
Re
lea
se
SLEWUP
SLEWDN
14
fo
r
15
SLEWUP
R/W
0xc8 (200)
6
5
4
3
SLEWDN
R/W
0x6A4 (1700)
Co
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Name
Type
Reset
Bit
Name
Type
Reset
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MT6228 GSM/GPRS Baseband Processor Data Sheet Revision 1.0
Must be unsigned.
Must be unsigned.
Signed integer.
Signed integer.
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20
19
YLPF18
R/W
0xb4 (180)
4
3
YLPF16
R/W
0Xc7 (-57)
18
17
16
2
1
0
Hardware extends to 9 bits.
Hardware extends to 9 bits.
MediaTek Inc. Confidential
Chrominance low-pass filter coefficients 0-3
31
30
29
28
15
14
13
12
CLPF3
CLPF2
CLPF1
CLPF0
Chrominance low-pass filter coefficient 3.
Chrominance low-pass filter coefficient 2.
Chrominance low-pass filter coefficient 1.
Chrominance low-pass filter coefficient 0.
TVE+0038h
27
26
CLPF3
R/W
0x18
11
10
CLPF1
R/W
0x10
24
23
22
21
20
9
8
7
6
5
4
19
18
CLPF2
R/W
0xd
3
2
CLPF0
R/W
0x1
Chrominance low-pass filter coefficients 4-7
31
30
29
28
15
14
13
12
CLPF7
CLPF6
CLPF5
CLPF4
Chrominance low-pass filter coefficient 7.
Chrominance low-pass filter coefficient 6.
Chrominance low-pass filter coefficient 5.
Chrominance low-pass filter coefficient 4.
TVE+003Ch
27
26
CLPF7
R/W
0x25
11
10
CLPF5
R/W
0x20
25
24
9
8
23
22
21
20
7
6
5
4
Co
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Bit
Name
Type
Reset
Bit
Name
Type
Reset
Bit
Name
Type
Reset
Bit
Name
Type
Reset
25
30
15
14
16
1
0
TVE_CLPFB
19
18
CLPF6
R/W
0x34
3
2
CLPF4
R/W
0x21
Chrominance low-pass filter coefficients 8-9
31
17
fo
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Bit
Name
Type
Reset
Bit
Name
Type
Reset
TVE_CLPFA
Re
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TVE+0034h
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MT6228 GSM/GPRS Baseband Processor Data Sheet Revision 1.0
17
16
1
0
TVE_CLPFC
29
28
27
26
25
24
23
22
21
20
19
18
17
16
13
12
11
10
CLPF9
R/W
0x27
9
8
7
6
5
4
3
2
CLPF8
R/W
0x3c
1
0
CLPF9 Chrominance low-pass filter coefficient 9.
CLPF8 Chrominance low-pass filter coefficient 8.
TVE+0040h
31
30
29
MT
K
Bit
Name
Type
Reset
Bit
Name
Type
Reset
Gamma correction coefficient 0
15
14
13
28
27
26
25
24
23
12
11
10
9
8
7
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TVE_GAMMAA
22
21
GAMMA0
R/W
0
6
5
20
19
18
17
16
4
3
2
1
0
MediaTek Inc. Confidential
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MT6228 GSM/GPRS Baseband Processor Data Sheet Revision 1.0
GAMMA0~GAMMA8 indicate the turning points of a piecewise linear approximation for a gamma curve.
values form a perfect linear equation with no gamma correction.
GAMMA8
GAMMA7
GAMMA6
GAMMA5
GAMMA4
GAMMA3
fo
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Gamma correction is performed on Luma only.
By default, the
GAMMA1
GAMMA0
GAMMA0 Gamma correction coefficient 0.
Bit
Name
Type
Reset
Bit
Name
Type
Reset
Gamma correction coefficients 1-2
31
30
15
14
29
28
27
26
25
24
23
Co
nf
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TVE+0044h
Re
lea
se
GAMMA2
13
12
11
10
9
8
7
22
21
GAMMA2
R/W
0x314
6
5
GAMMA1
R/W
0x18a
TVE_GAMMAB
20
19
18
17
16
4
3
2
1
0
GAMMA2 Gamma correction coefficient 2.
GAMMA1 Gamma correction coefficient 1.
TVE+0048h
Bit
Name
Type
Reset
Bit
Name
Type
Reset
Gamma correction coefficients 3-4
31
30
15
14
29
28
27
26
25
24
23
13
12
11
10
9
8
7
TVE_GAMMAC
22
21
GAMMA4
R/W
0x629
6
5
GAMMA3
R/W
0x49e
20
19
18
17
16
4
3
2
1
0
MT
K
GAMMA4 Gamma correction coefficient 4.
GAMMA3 Gamma correction coefficient 3.
TVE+004Ch
Bit
31
Gamma correction coefficients 5-6
30
29
28
27
26
25
24
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23
TVE_GAMMAD
22
21
20
19
18
17
16
MediaTek Inc. Confidential
15
14
13
12
11
10
9
8
7
GAMMA6
R/W
0x93d
6
5
GAMMA5
R/W
0x7b3
GAMMA6 Gamma correction coefficient 6.
GAMMA5 Gamma correction coefficient 5.
Bit
Name
Type
Reset
Bit
Name
Type
Reset
Gamma correction coefficients 7-8
31
30
29
28
27
26
25
24
15
14
13
12
11
10
9
8
GAMMA8 Gamma correction coefficient 8.
GAMMA7 Gamma correction coefficient 7.
TVE+0060h
31
30
29
28
27
26
25
24
15
14
13
12
11
10
9
8
Name
Type
Reset
7
2
1
0
TVE_GAMMAE
22
21
GAMMA8
R/W
0xc52
6
5
GAMMA7
R/W
0xac8
20
19
4
3
18
17
16
2
1
0
TVE_SWRST
23
22
21
20
19
18
17
16
7
6
5
4
3
2
1
0
SWRS
T
WO
0
Co
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Bit
Name
Type
Reset
Bit
Software reset control
23
3
Re
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TVE+0050h
4
fo
r
Name
Type
Reset
Bit
Name
Type
Reset
Ko
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MT6228 GSM/GPRS Baseband Processor Data Sheet Revision 1.0
Writing a 1 invokes a software reset.
TVE+0070h
Bit
Name
Type
15
Plug-in detection
14
13
12
11
10
9
8
7
TVE_PLUG
6
5
4
3
2
1
0
PLUG
RO
The TV encoder can detect cable plug-in by sensing the output impedance. To enable plug-in detection, set the
TVE_DACTRL register PLUG_DETECT_EN bit. If PLUG_DETECT_EN is enabled, when the cable is plugged in, the
PLUG bit is set to 1. The user can use polling or interrupt schemes (refer to TVE_INTREN and TVE_INTR) for plug-in
detection.
MT
K
PLUG Plug-in detection.
0 Cable not plugged in.
1 Cable plugged in.
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7
7.1
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MT6228 GSM/GPRS Baseband Processor Data Sheet Revision 1.0
Audio Front-End
General Description
fo
r
The audio front-end essentially consists of voice and audio data paths. Figure 38 shows the block diagram of the audio
front-end. All voice band data paths comply with the GSM 03.50 specification. Mono hands-free audio or external FM
radio playback paths are also provided. The audio stereo path facilitates CD-quality playback, external FM radio, and
voice playback through a headset.
MUX
Audio Amp-L
Audio
Signal
,!- .!(#
Re
lea
se
Audio
LCH-DAC
,!- .!(
MUX
Stereoto-Mono
Audio
RCH-DAC
Audio Amp-R
,!-* %'#
Stereoto-Mono
* 0,
+
1
,!-* %'
,!-.!( -'
Voice
Signal
Voice DAC
Voice Amp-0
,!-.!( -/
MUX
Co
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Voice Amp-1
,!-.!( -/
,!-2%' -/
PGA
Voice ADC
MUX
Voice
Signal
,!-.!( -'
,!-2%' -'
,!-2%' -'
,!-2%' -/
Figure 38 Block diagram of audio front-end
MT
K
Figure 39 shows the digital circuits block diagram of the audio front-end. The APB register block is an APB peripheral
that stores settings from the MCU. The DSP audio port block interfaces with the DSP for control and data
communications. The digital filter block performs filter operations for voice band and audio band signal processing.
The Digital Audio Interface (DAI) block communicates with the System Simulator for FTA or external Bluetooth modules.
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4
45
,/
3
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MT6228 GSM/GPRS Baseband Processor Data Sheet Revision 1.0
5
+
fo
r
,%
,
Re
lea
se
4/
,
4/
,
+
/+
3
*
,
,
Figure 39 Block diagram of digital circuits of the audio front-end
- 6
-
"
-
"
-7
-7
Co
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To communicate with the external Bluetooth module, the master-mode PCM interface and master-mode I2S/EIAJ interface
are supported. The clock of PCM interface is 256 KHz, and the frame sync is 8 KHz. Both long sync and short sync
interfaces are supported. The PCM interface can transmit 16-bit stereo or 32-bit mono 8KHz sampling rate voice signal.
Figure 40 shows the timing diagram of the PCM interface. Note that the serial data changes when the clock is rising and
is latched when the clock is falling.
)
)
)
:
8
9
)
)
)
)
:
8
9
)
MT
K
Figure 40 Timing diagram of Bluetooth application
I2S/EIAJ interface is designed to transmit high quality audio data. Figure 40 and Figure 41 illustrate the timing diagram
of the two types of interfaces. I2S/EIAJ can support 32KHz, 44.1KHz, and 48KHz sampling rate audio signals. The
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clock frequency of I2S/EIAJ can be 32×(sampling frequency), or 64×(sampling frequency).
Ko
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MT6228 GSM/GPRS Baseband Processor Data Sheet Revision 1.0
For example, to transmit a
44.1KHz CD-quality music, the clock frequency should be 32×44.1KHz = 1.4112MHz or 64×44.1KHz = 2.8224MHz.
I2S/EIAJ interface is not only used for Bluetooth module, but also for external DAC components.
be sent to the external DAC through the I2S/EIAJ interface.
Audio data can easily
In this document, the I2S/EIAJ interface is referred to as EDI (External DAC Interface).
EDI_WS
EDI_DAT
Left Channel
6
5
4
3
2
1
0
15
14
13
12
11
10
9
8
7
Right Channel
6
5
4
3
2
1
0
15
14
13
12
11
10
9
8
EDI_CLK
EDI_DAT
Left Channel
6
5
4
3
2
1
0
15
14
13
12
11
10
9
8
6
5
4
3
2
1
0
15
14
13
5
4
3
2
1
0
15
14
13
Right Channel
7
6
5
4
3
2
Figure 42 EDI Format 2: I2S (FMT = 1).
7.1.1
7
Re
lea
se
Figure 41 EDI Format 1: EIAJ (FMT = 0).
EDI_WS
fo
r
EDI_CLK
DAI, PCM and EDI Pin Sharing
DAI, PCM, and EDI interfaces share the same pins.
1
0
15
14
13
12
11
10
9
8
7
6
The pin mapping is listed in Table 59.
DAI
PCM
EDI
DAI_CLK (OUTPUT)
DAI_CLK
PCM_CLK
EDI_CLK
DAI_TX
PCM_OUT
EDI_DAT
DAI_RX
PCM_IN
-
PCM_SYNC
DAI_TX (OUTPUT)
DAI_RX (INPUT)
Co
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PIN NAME
BT_SYNC (OUTPUT)
EDI_WS
Table 59 Pin mapping of DAI, PCM, and EDI interfaces.
With the dedicated pins, PCM and EDI
MT
K
Beside the shared pins, the EDI interface can also use other dedicated pins.
interfaces can operate at the same time.
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MT6228 GSM/GPRS Baseband Processor Data Sheet Revision 1.0
Dedicated Shared
Pins
Pins
PCM DAI
DSP
IO BUS
BYPASS
=00
int
1
BYPASS
=11
BYPASS
=10
int
2
Figure 43 DAI, PCM, EDI interfaces
7.2
Register Definitions
MCU APB bus registers in audio front-end are listed as follows.
Bit
15
AFE Voice MCU Control Register
14
Name
Type
Reset
Co
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AFE+0000h
SD-DAC
upsampling
FIR
Re
lea
se
BYPASS
=01
fo
r
EDI
13
12
11
10
9
8
7
6
5
4
3
SDM
AFE_VMCU_CO
N0
2
1
0
VAFE
ON
R/W
0
MCU sets this register to start AFE voice operation. A synchronous reset signal is issued, then periodical interrupts of
8-KHz frequency are issued. Clearing this register stops the interrupt generation.
VAFEON
Turn on audio front-end operations.
AFE+000Ch
Bit
15
Name
Type
Reset
AFE_VMCU_CO
N1
AFE Voice Analog-Circuit Control Register 1
14
13
12
11
10
9
MT
K
Set this register for consistency of analog circuit setting.
8
7
VRSD
ON
R/W
0
6
5
4
3
2
1
0
Suggested value is 80h.
VRSDON Turn on the voice-band redundant signed digit function.
0: 1-bit 2-level mode
1: 2-bit 3-level mode
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AFE+0014h
Bit
15
AFE Voice DAI Bluetooth Control Register
14
13
12
11
10
9
8
7
Name
Type
Reset
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MT6228 GSM/GPRS Baseband Processor Data Sheet Revision 1.0
AFE_VDB_CON
6
5
4
3
EDIO VDAI PCMO VBTS
N
ON
N
YNC
RW R/W R/W R/W
0
0
0
0
Set this register for DAI test mode and Bluetooth application.
2
1
VBTSLEN
R/W
000
Turn on the Bluetooth PCM function.
VBTSYNC Bluetooth PCM frame sync type
Re
lea
se
fo
r
EDION EDI signals are selected as the output of DAI, PCM, EDI shared interface.
0 EDI is not selected. A dedicated EDI interface can be enabled by programming the GPIO selection.
refer to GPIO section for details.
1 EDI is selected. VDAION and VBTON are not set.
VDAION Turn on the DAI function.
VBTON
0
Please
0: short
1: long
VBTSLEN Bluetooth PCM long frame sync length = VBTSLEN+1
AFE+0018h
Bit
15
AFE Voice Look-Back mode Control Register
14
13
12
11
10
9
8
7
6
5
4
Co
nf
id
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l
Name
Type
Reset
AFE_VLB_CON
3
2
1
0
VBYP VDAPI VINTI VDEC
ASSII NMOD NMOD INMO
R
E
E
DE
R/W R/W R/W R/W
0
0
0
0
Set this register for AFE voice digital circuit configuration control. Several loop back modes are implemented for test
purposes. Default values correspond to the normal function mode.
VBYPASSIIR Bypass hardware IIR filters.
VDAPINMODE DSP audio port input mode control
0 Normal mode
1 Loop back mode
VINTINMODE interpolator input mode control
0 Normal mode
1 Loop back mode
VDECINMODE decimator input mode control
0 Normal mode
1
MT
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Loop back mode
AFE+0020h
Bit
15
AFE_AMCU_CO
N0
AFE Audio MCU Control Register 0
14
13
12
11
10
9
8
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AAFE
ON
R/W
0
Name
Type
Reset
Bit
15
AFE Audio Control Register 1
14
13
12
11
10
Name
BYPASS
Type
Reset
RW
00
9
8
ADITH
ON
R/W
0
7
6
5
4
ADITHVAL
ARAMPSP
R/W
00
R/W
00
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AFE+0024h
fo
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MCU sets this register to start AFE audio operation. A synchronous reset signal is
issued, then periodical interrupts of 1/6 sampling frequency are issued. Clearing this
register stops the interrupt generation.
AFE_AMCU_CON
3
2
AMUTE AMUTE
R
L
R/W
R/W
0
0
MCU sets this register to inform hardware of the sampling frequency of audio being played back.
BYPASS To bypass part of the audio hardware path.
00 No bypass. The input data rate is 1/4 sampling frequency. For example, if the sampling frequency is
32KHz, then the input data rate is 8KHz.
01 Bypass the first stage of interpolation. The input data rate is 1/2 the sampling frequency.
10 Bypass two stages of interpolation. The input data rate is the same as the sampling frequency.
11 Bypass two stages of interpolation and EQ filter. The input data rate is the same as the sampling frequency.
DSP
IO BUS
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EDI
BYPASS
=01
BYPASS
=00
int
1
BYPASS
=11
BYPASS
=10
int
2
FIR
SD-DAC
upsampling
SDM
Figure 44 Block diagram of the audio path.
ADITHON Turn on the audio dither function.
ADITHVAL
1/4
1/2
1
2
ramp up/down speed selection
MT
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00
01
10
11
ARAMPSP
Dither scaling setting.
00
01
10
11
8, 4096/AFS
16, 2048/AFS
24, 1024/AFS
32, 512/AFS
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AFS
R/W
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AMUTER Mute the audio R-channel, with a soft ramp up/down.
AMUTEL Mute the audio L-channel, with a soft ramp up/down.
AFS Sampling frequency setting.
AFE+0028h
Bit
Name
Type
Reset
15
fo
r
32-KHz
44.1-KHz
48-KHz
reserved
AFE EDI Control Register
14
13
12
11
10
AFE_EDI_CON
9
8
7
6
5
4
3
WCYCLE
R/W
01111
2
1
FMT
R/W
0
Re
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00
01
10
11
This register is used to control the EDI
EN
EDI_CLK
EDI_WS
EDI_DAT
6
5
4
3
2
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Enable EDI. When EDI is disabled, EDI_DAT and EDI_WS hold low.
0 disable EDI
1 enable EDI
FMT
EDI format
0 EIAJ
1 I2S
WCYCLE Clock cycle count in a word. Cycle count = WCYCLE + 1, and WCYCLE can be 15 or 31 only.
values result in an unpredictable error.
15 Cycle count is 16.
31 Cycle count is 32.
1
16 cycles
16 cycles
Left Channel
Right Channel
0 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
EN
R/W
0
Any other
0 15 14 13
Figure 45 Cycle count is 16 for I2S format.
EDI_CLK
EDI_WS
EDI_DAT
6
5
4
3
2
1
0 15 14 13 12
32 cycles
32 cycles
Left Channel
Right Channel
2
1
0
15 14 13 12
2
1
0
15 14 13
MT
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Figure 46 Cycle count is 32 for I2S format.
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AFE+0040h~00
AFE Audio Equalizer Filter Coefficient Register
F0h
Bit
Name
Type
15
14
13
12
11
10
9
8
7
6
5
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AFE_EQCOEF
4
3
A
WO
2
1
0
7.3
Programming Guide
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Audio front-end provides a 45-tap equalizer filter. The filter is shown below.
DO = (A44 X DI44 + A43 X DI43 … + A1 X DI1 + A0 X DI0)/32768.
DIn is the input data, and An is the coefficient of the filter, which is a 16-bit 2’s complement signed integer. DI0 is the last
input data.
The coefficient cannot be programmed when the audio path is enabled, or unpredictable noise may be generated. If
coefficient programming is necessary while the audio path is enabled, the audio path must be muted during programming.
After programming is complete, the audio path is not to be resumed (unmated) for 100 sampling periods.
A
Coefficient of the filter.
Several cases – including speech call, voice memo record, voice memo playback, melody playback and DAI tests – requires
that partial or the whole audio front-end be turned on.
The following are the recommended voice band path programming procedures to turn on audio front-end:
MCU programs the AFE_DAI_CON, AFE_LB_CON, AFE_VAG_CON, AFE_VAC_CON0, AFE_VAC_CON1
and AFE_VAPDN_CON registers for specific operation modes. Refer also to the analog chip interface
specification.
2.
MCU clears the VAFE bit of the PDN_CON2 register to ungate the clock for the voice band path.
software power down control specification.
3.
MCU sets AFE_VMCU_CON to start operation of the voice band path.
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1.
Refer to the
The following are the recommended voice band path programming procedures to turn off audio front-end:
1.
MCU programs AFE_VAPDN_CON to power down the voice band path analog blocks.
2.
MCU clears AFE_VMCU_CON to stop operation of the voice band path.
3.
MCU sets VAFE bit of PDN_CON2 register to gate the clock for the voice band path.
To start the DAI test, the MS first receives a GSM Layer 3 TEST_INTERFACE message from the SS and puts the speech
transcoder into one of the following modes:
Normal mode (VDAIMODE[1:0]: 00)
Test of speech encoder/DTX functions (VDAIMODE[1:0]: 10)
MT
K
Test of speech decoder/DTX functions (VDAIMODE[1:0]: 01)
Test of acoustic devices and A/D & D/A (VDAIMODE[1:0]: 11)
The MS then waits for DAIRST# signaling from the SS. Recognizing this, DSP starts to transmit to and/or receive from
the DSP. For further details, refer to the GSM 11.10 specification.
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The following are the recommended audio band path programming procedures to turn on audio front-end:
1.
MCU programs the AFE_MCU_CON1, AFE_AAG_CON, AFE_AAC_CON, and AFE_AAPDN_CON registers
for specific configurations. Refer also to the analog chip interface specification.
2.
MCU clears the AAFE bit of the PDN_CON2 register to ungate the clock for the audio band path.
software power down control specification.
3.
MCU sets AFE_AMCU_CON0 to start operation of the audio band path.
Refer to the
fo
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The following are the recommended audio band path programming procedures to turn off audio front-end:
MCU programs the AFE_AAPDN_CON to power down the audio band path analog blocks.
analog block specification for further details.
2.
MCU clears AFE_AMCU_CON0 to stop operation of the audio band path.
3.
MCU sets the AAFE bit of the PDN_CON2 register to gate the clock for the audio band path.
Refer also to the
MT
K
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MT6228 GSM/GPRS Baseband Processor Data Sheet Revision 1.0
Radio Interface Control
This chapter details the MT6228 interface control with the radio part of a GSM terminal. Providing a comprehensive
control scheme, the MT6228 radio interface consists of Baseband Serial Interface (BSI), Baseband Parallel Interface (BPI),
Automatic Power Control (APC) and Automatic Frequency Control (AFC), together with APC-DAC and AFC-DAC.
Baseband Serial Interface
fo
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8.1
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The Baseband Serial Interface controls external radio components. A 3-wire serial bus transfers data to RF circuitry for
PLL frequency change, reception gain setting, and other radio control purposes. In this unit, BSI data registers are
double-buffered in the same way as the TDMA event registers. The user writes data into the write buffer and the data is
transferred from the write buffer to the active buffer when a TDMA_EVTVAL signal (from the TDMA timer) is pulsed.
Each data register BSI_Dn_DAT is associated with one data control register BSI_Dn_CON, where n denotes the index.
Each data control register identifies which events (signaled by TDMA_BSISTRn, generated by the TDMA timer) trigger
the download process of the word in register BSI_Dn_DAT. The word and its length (in bits) is downloaded via the serial
bus. A special event is triggered when the IMOD flag is set to 1: it provides immediate download process without
software programming the TDMA timer.
If more than one data word is to be downloaded on the same BSI event, the word with the lowest address among them is
downloaded first, followed by the next lowest and so on.
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The total download time depends on the word length, the number of words to download, and the clock rates. The
programmer must space the successive event to provide enough time. If the download process of the previous event is not
complete before a new event arrives, the latter is suppressed.
The unit has four output pins: BSI_CLK is the output clock, BSI_DATA is the serial data port, and BSI_CS0 and BSI_CS1
are the select pins for 2 external components. BSI_CS1 is multiplexed with another function. Please refer to GPIO table
for more detail.
In order to support bi-directional read and write operations of the RF chip, software can directly write values to BSI_CLK,
BSI_DATA and BSI_CS by programming the BSI_DOUT register. Data from the RF chip can be read by software via the
register BSI_DIN. If the RF chip interface is a 3-wire interface, then BSI_DATA is bi-directional. Before software can
program the 3-wire behavior, the BSI_IO_CON register must be set. An additional signal path from GPIO accommodates
RF chips with a 4-wire interface.
MT
K
The block diagram of the BSI unit is as depicted in Figure 47.
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TDMA_EVTVAL
(from TDMA timer)
Control
APB
BUS
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MT6228 GSM/GPRS Baseband Processor Data Sheet Revision 1.0
TDMA_BSISTR (0~15)
(from TDMA timer)
IMOD
SETENV
BSI_DIN_GPIO (read from RFIC)
(GPIO)
Write
buffer
Serial port
control
Active
buffer
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BSI_CLK
BSI_DATA
BSI_CS0
Re
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BSI_CS1 (GPIO)
BSI Unit
Figure 47
Block diagram of BSI unit.
BSI_CLK
(invert)
BSI_CLK
(true)
BSI_CSx
(long)
BSI_CSx
(short)
Figure 48
8.1.1
Timing characteristic of BSI interface.
Register Definitions
BSI+0000h
Bit
15
Name
Type
Reset
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BSI_DATA
BSI control register
14
13
12
11
10
This register is the control register for the BSI unit.
9
BSI_CON
8
7
6
5
4
3
SETE EN1_ EN1_ EN0_ EN0_
IMOD
NV
POL LEN POL LEN
R/W R/W R/W R/W R/W WO
0
0
0
0
0
N/A
2
1
CLK_SPD
R/W
0
0
CLK_
POL
R/W
0
The register controls the signal type of the 3-wire interface.
MT
K
CLK_POL Controls the polarity of BSI_CLK. Refer to Figure 48.
0 True clock polarity
1 Inverted clock polarity
CLK_SPD Defines the clock rate of BSI_CLK. The 3-wire interface provides 4 choices of data bit rate. The default is
13/2 MHz.
00 13/2 MHz
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MT6228 GSM/GPRS Baseband Processor Data Sheet Revision 1.0
BSI+0004h
Bit
15
Name ISB
Type R/W
Control part of data register 0
14
13
12
11
10
LEN
R/W
9
8
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01 13/4 MHz
10 13/6 MHz
11 13/8 MHz
IMOD Enables immediate mode. If the user writes 1 to the flag, the download is triggered immediately without waiting
for the timer events. The words for which the register event ID equals 1Fh are downloaded following this signal.
This flag is write-only. The immediate write is exercised only once: the programmer must write the flag again to
invoke another immediate download. Setting the flag does not disable the other events from the timer; the
programmer can disable all events by setting BSI_ENA to all zeros.
ENX_LEN Controls the type of signals BSI_CS0 and BSI_CS1. Refer to Figure 47.
0 Long enable pulse
1 Short enable pulse
ENX_POL Controls the polarity of signals BSI_CS0 and BSI_CS1.
0 True enable pulse polarity
1 Inverted enable pulse polarity
SETENV Enables the write operation of the active buffer.
0 The user writes to the write buffer. The data is then latched in the active buffer after TDMA_EVTVAL is
pulsed.
1 The user writes data directly to the active buffer.
7
6
5
4
3
BSI_D0_CON
2
EVT_ID
R/W
1
0
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This register is the control part of the data register 0. The register determines the required length of the download data
word, the event to trigger the download process of the word, and the targeted device.
Table 61 lists the 27 data registers of this type. Multiple data control registers may contain the same event ID: the data
words of all registers with the same event ID are downloaded when the event occurs.
MT
K
EVT_ID Stores the event ID for which the data word awaits to be downloaded.
00000~01111 Synchronous download of the word with the selected EVT_ID event.
this field and the event is listed as Table 60.
Event ID (in binary) – EVT_ID
Event name
00000
TDMA_BSISTR0
00001
TDMA_BSISTR1
00010
TDMA_BSISTR2
00011
TDMA_BSISTR3
00100
TDMA_BSISTR4
00101
TDMA_BSISTR5
00110
TDMA_BSISTR6
00111
TDMA_BSISTR7
01000
TDMA_BSISTR8
01001
TDMA_BSISTR9
01010
TDMA_BSISTR10
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01011
TDMA_BSISTR11
01100
TDMA_BSISTR12
01101
TDMA_BSISTR13
01110
TDMA_BSISTR14
01111
TDMA_BSISTR15
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MT6228 GSM/GPRS Baseband Processor Data Sheet Revision 1.0
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Table 60 The relationship between the value of EVT_ID field in the BSI control registers and the TDMA_BSISTR
events.
LEN
ISB
BSI +0008h
Bit
Name
Type
Bit
Name
Type
Data part of data register 0
31
30
29
28
27
26
25
15
14
13
12
11
10
9
The value ranges from 0
Re
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10000~11110 Reserved
11111
Immediate download
Stores the length of the data word. The actual length is defined as LEN + 1 (in bits).
to 31, corresponding to 1 to 32 bits in length.
The flag selects the target device.
0 Device 0 is selected.
1 Device 1 is selected.
24
23
DAT [31:16]
R/W
8
7
DAT [15:0]
R/W
BSI_D0_DAT
22
21
20
19
18
17
16
6
5
4
3
2
1
0
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This register is the data part of the data register 0. The legal length of the data is up to 32 bits. The actual number of bits
to be transmitted is specified in LEN field in the BSI_D0_CON register.
DAT
The field signifies the data part of the data register.
Table 61 lists the address mapping and function of the 27 pairs of data registers.
Register Address
Register Function
Acronym
BSI +0004h
Control part of data register 0
BSI_D0_CON
Data part of data register 0
BSI_D0_DAT
Control part of data register 1
BSI_D1_CON
Data part of data register 1
BSI_D1_ DAT
Control part of data register 2
BSI_D2_CON
Data part of data register 2
BSI_D2_ DAT
Control part of data register 3
BSI_D3_CON
Data part of data register 3
BSI_D3_ DAT
Control part of data register 4
BSI_D4_CON
BSI +0028h
Data part of data register 4
BSI_D4_ DAT
BSI +002Ch
Control part of data register 5
BSI_D5_CON
BSI +0030h
Data part of data register 5
BSI_D5_ DAT
BSI +0034h
Control part of data register 6
BSI_D6_CON
BSI +0038h
Data part of data register 6
BSI_D6_ DAT
BSI +0008h
BSI +000Ch
BSI +0010h
BSI +0014h
BSI +0018h
BSI +001Ch
BSI +0020h
MT
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BSI +0024h
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MT6228 GSM/GPRS Baseband Processor Data Sheet Revision 1.0
Control part of data register 7
BSI_D7_CON
BSI +0040h
Data part of data register 7
BSI_D7_ DAT
BSI +0044h
Control part of data register 8
BSI_D8_CON
BSI +0048h
Data part of data register 8
BSI_D8_ DAT
BSI +004Ch
Control part of data register 9
BSI_D9_CON
BSI +0050h
Data part of data register 9
BSI_D9_ DAT
BSI +0054h
Control part of data register 10
BSI_D10_CON
BSI +0058h
Data part of data register 10
BSI +005Ch
Control part of data register 11
BSI +0060h
Data part of data register 11
BSI +0064h
Control part of data register 12
BSI_D12_CON
BSI +0068h
Data part of data register 12
BSI_D12_ DAT
BSI +006Ch
Control part of data register 13
BSI +0070h
Data part of data register 13
BSI +0074h
Control part of data register 14
BSI +0078h
Data part of data register 14
BSI +007Ch
Control part of data register 15
BSI +0080h
Data part of data register 15
BSI +0084h
Control part of data register 16
BSI +0088h
Data part of data register 16
BSI +008Ch
Control part of data register 17
BSI_D17_CON
BSI +0090h
Data part of data register 17
BSI_D17_ DAT
Control part of data register 18
BSI_D18_CON
Data part of data register 18
BSI_D18_ DAT
Control part of data register 19
BSI_D19_CON
Data part of data register 19
BSI_D19_ DAT
Control part of data register 20
BSI_D20_CON
Data part of data register 20
BSI_D20_ DAT
Control part of data register 21
BSI_D21_CON
Data part of data register 21
BSI_D21_ DAT
Control part of data register 22
BSI_D22_CON
Data part of data register 22
BSI_D22_ DAT
Control part of data register 23
BSI_D23_CON
Data part of data register 23
BSI_D23_ DAT
Control part of data register 24
BSI_D24_CON
BSI +00C8h
Data part of data register 24
BSI_D24_ DAT
BSI +00CCh
Control part of data register 25
BSI_D25_CON
BSI +00D0h
Data part of data register 25
BSI_D25_ DAT
BSI +00D4h
Control part of data register 26
BSI_D26_CON
BSI +0098h
BSI +009Ch
BSI +00A0h
BSI +00A4h
BSI +00A8h
BSI +00ACh
BSI +00B0h
BSI +00B4h
BSI +00B8h
BSI +00BCh
BSI +00C0h
MT
K
BSI +00C4h
BSI_D10_ DATA
BSI_D11_CON
Re
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BSI_D11_ DAT
BSI_D13_CON
BSI_D13_ DAT
BSI_D14_CON
BSI_D14_ DAT
BSI_D15_CON
BSI_D15_ DAT
BSI_D16_CON
BSI_D16_ DAT
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BSI +0094h
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BSI +003Ch
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BSI +00D8h
BSI_D26_ DAT
Data part of data register 26
Table 61 BSI data registers
BSI event enable register
Bit
15
14
13
12
11
10
9
Name BSI15 BSI14 BSI13 BSI12 BSI11 BSI10 BSI9
Type R/W R/W R/W R/W R/W R/W R/W
Reset
1
1
1
1
1
1
1
BSI_ENA
8
BSI8
R/W
1
This register enables an event by setting the corresponding bit.
bits are also set to 1 after TDMA_EVTVAL pulse.
BSIx
7
BSI7
R/W
1
6
BSI6
R/W
1
5
BSI5
R/W
1
4
BSI4
R/W
1
3
BSI3
R/W
1
2
BSI2
R/W
1
1
BSI1
R/W
1
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BSI +0190h
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0
BSI0
R/W
1
After a hardware reset, all bits are initialized to 1. These
BSI +0194h
Bit
15
BSI IO mode control register
14
13
12
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Name
Type R/W
0
Reset
Re
lea
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Enables downloading of the words corresponding to the events signaled by TMDA_BSI.
0 The event is not enabled.
1 The event is enabled.
7
6
5
4
R/W
0
R/W
0
R/W
0
R/W
0
BSI_IO_CON
3
2
1
0
SEL_ 4_WIR DAT_
MODE
CS1
E
DIR
R/W R/W R/W R/W
0
0
1
0
BSI +0198h
Software-programmed data out
14
R/W
0
BSI_DOUT
13
12
11
10
9
8
7
6
5
4
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
MT
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Bit
15
Name
Type R/W
Reset
0
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MODE Defines the source of BSI signal.
0 BSI signal is generated by the hardware.
1 BSI signal is generated by the software. In this mode, the BSI clock depends on the value of the field
DOUT.CLK. BSI_CS depends on the value of the field DOUT.CS and BSI_DATA depends on the value of
the field DOUT.DATA.
DAT_DIR Defines the direction of BSI_DATA.
0 BSI _DATA is configured as input. The 3-wire interface is used and BSI_DATA is bi-directional.
1 BSI_DATA is configured as output.
4_WIRE
Defines the BSI_DIN source.
0 The 3-wire interface is used and BSI_DATA is bi-directional. BSI_DIN comes from the same pin as
BSI_DATA.
1 The 4-wire interface is used. Another pin (GPIO) is used as BSI_DIN.
SEL_CS1 Defines which of the BSI_CSx (BSI_CS0 or BSI_CS1) is written by the software.
0 BSI_CS0 is selected.
1 BSI_CS1 is selected.
3
2
DATA
R/W
W
0
0
1
CS
W
0
0
CLK
W
0
CLK
Signifies the BSI_CLK signal.
CS
Signifies the BSI_CS signal.
DATA Signifies the BSI_DATA signal.
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BSI +019ch
Bit
15
Name
Type R/W
Reset
0
DIN
Input data from RF chip
BSI_DIN
14
13
12
11
10
9
8
7
6
5
4
3
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Baseband Parallel Interface
8.2.1
2
1
R/W
0
R/W
0
0
DIN
R
0
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Registers the input value of BSI_DATA from the RF chip.
8.2
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General Description
TDMA_EVTVAL
(from TDMA timer)
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The Baseband Parallel Interface features 10 control pins, which are used for timing-critical external circuits. These pins
typically control front-end components which must be turned on or off at specific times during GSM operation, such as
transmit-enable, band switching, TR-switch, etc.
TDMA_BPISTR (0~21)
(from TDMA timer)
Event Register
Write
buffer
MUX
Active
buffer
APB I/F
Output
buffer
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MUX
petev
Immediate mode
!
"
# $ % &'( ') * + , - , . '/'01 '2 + 3 ) 4'* 5 &, . /$ 6
# $ % &'( ') * + , - , . '/'01 '2 4'7 $ % 6
Figure 49
Block
diagram of BPI interface
The user can program 22 sets of 10-bit registers to set the output value of BPI_BUS0~BPI_BUS9. The data is stored in
the write buffers. The write buffers are then forwarded to the active buffers when the TDMA_EVTVAL signal is pulsed,
usually once per frame. Each of the 22 write buffers corresponds to an active buffer, as well as to a TDMA event.
MT
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Each TDMA_BPISTR event triggers the transfer of data in the corresponding active buffer to the output buffer, thus
changing the value of the BPI bus. The user can disable the events by programming the enable registers in the TDMA
timer. If the TDMA_BPISTR event is disabled, the corresponding signal TDMA_BPISTR is not pulsed, and the value on
the BPI bus remains unchanged.
For applications in which BPI signals serve as the switch, current-driving components are typically added to enhance
driving capability. Four configurable output pins provide current up to 8 mA, and help reduce the number of external
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components. The output pins BPI_BUS6, BPI_BUS7, BPI_BUS8, and BPI_BUS9 are multiplexed with GPIO.
refer to the GPIO table for more detailed information.
8.2.2
Register Definitions
BPI+0000h
Bit
15
BPI control register
14
13
12
11
10
BPI_CON
9
8
7
6
5
4
3
2
1
0
PETE
PINM3 PINM2 PINM1 PINM0
V
WO
WO
WO
WO R/W
0
0
0
0
0
fo
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Name
Type
Reset
The register controls the direct access mode of the active buffer and
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This register is the control register of the BPI unit.
the current driving capability for the output pins.
Please
The driving capabilities of BPI_BUS0, BPI_BUS1, BPI_BUS2, and BPI_BUS3 can be 2 mA or 8 mA, determined by the
value of PINM0, PINM1, PINM2, and PINM3, respectively. These output pins provide a higher driving capability and
save on external current-driving components. In addition to the configurable pins, pins BPI_BUS4 to BPI_BUS9 provide
a driving capability of 2 mA (fixed).
BPI +0004h
Bit
Name
Type
15
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PETEV Enables direct access to the active buffer.
0 The user writes data to the write buffer. The data is latched in the active buffer after the TDMA_EVTVAL
signal is pulsed.
1 The user directly writes data to the active buffer without waiting for the TDMA_EVTVAL signal.
PINM0 Controls the driving capability of BPI_BUS0.
0 The output driving capability is 2mA.
1 The output driving capability is 8mA.
PINM1 Controls the driving capability of BPI_BUS1.
0 The output driving capability is 2mA.
1 The output driving capability is 8mA.
PINM2 Controls the driving capability of BPI_BUS2.
0 The output driving capability is 2mA.
1 The output driving capability is 8mA.
PINM3 Controls the driving capability of BPI_BUS3.
0 The output driving capability is 2mA.
1 The output driving capability is 8mA.
BPI data register 0
14
13
12
11
10
9
PO9
R/W
8
PO8
R/W
7
PO7
R/W
BPI_BUF0
6
PO6
R/W
5
PO5
R/W
4
PO4
R/W
3
PO3
R/W
2
PO2
R/W
1
PO1
R/W
0
PO0
R/W
This register defines the BPI signals that are associated with the event TDMA_BPI0.
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Table 62 lists 22 registers of the same structure, each of which is associated with one specific event signal from the TDMA
timer. The data registers are all double-buffered. When PETEV is set to 0, the data register links to the write buffer.
When PETEV is set to 1, the data register links to the active buffer.
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One register, BPI_BUFI, is dedicated for use in immediate mode.
change in the corresponding BPI signal and bus.
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Writing a value to that register effects an immediate
POx
This flag defines the corresponding signals for BPIx after the TDMA event 0 takes place.
The overall data register definition is listed in Table 62.
Register Function
Acronym
BPI +0004h
BPI pin data for event TDMA_BPI 0
BPI_BUF0
BPI +0008h
BPI pin data for event TDMA_BPI 1
BPI_BUF1
BPI +000Ch
BPI pin data for event TDMA_BPI 2
BPI +0010h
BPI pin data for event TDMA_BPI 3
BPI +0014h
BPI pin data for event TDMA_BPI 4
BPI +0018h
BPI pin data for event TDMA_BPI 5
BPI_BUF5
BPI +001Ch
BPI pin data for event TDMA_BPI 6
BPI_BUF6
BPI +0020h
BPI pin data for event TDMA_BPI 7
BPI_BUF7
BPI +0024h
BPI pin data for event TDMA_BPI 8
BPI_BUF8
BPI +0028h
BPI pin data for event TDMA_BPI 9
BPI_BUF9
BPI +002Ch
BPI pin data for event TDMA_BPI 10
BPI_BUF10
BPI +0030h
BPI pin data for event TDMA_BPI 11
BPI_BUF11
BPI +0034h
BPI pin data for event TDMA_BPI 12
BPI_BUF12
BPI +0038h
BPI pin data for event TDMA_BPI 13
BPI_BUF13
BPI +003Ch
BPI pin data for event TDMA_BPI 14
BPI_BUF14
BPI +0040h
BPI pin data for event TDMA_BPI 15
BPI_BUF15
BPI pin data for event TDMA_BPI 16
BPI_BUF16
BPI pin data for event TDMA_BPI 17
BPI_BUF17
BPI pin data for event TDMA_BPI 18
BPI_BUF18
BPI pin data for event TDMA_BPI 19
BPI_BUF19
BPI pin data for event TDMA_BPI 20
BPI_BUF20
BPI pin data for event TDMA_BPI 21
BPI_BUF21
BPI pin data for immediate mode
BPI_BUFI
BPI +0048h
BPI +004Ch
BPI +0050h
BPI +0054h
BPI +0058h
BPI +005Ch
BPI_BUF2
BPI_BUF3
BPI_BUF4
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BPI +0044h
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Register Address
Table 62 BPI Data Registers.
BPI +0060h
Bit
BPI event enable register 0
BPI_ENA0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
BEN1 BEN1 BEN1 BEN1 BEN1 BEN1
Name
BEN9 BEN8 BEN7 BEN6 BEN5 BEN4 BEN3 BEN2 BEN1 BEN0
5
4
3
2
1
0
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
MT
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This register enables the events that are signaled by the TDMA timer: by clearing a register bit, the corresponding event
signal is ignored. After a hardware reset, all the enable bits default to 1 (enabled). Upon receiving a TDMA_EVTVAL
pulse, all register bits are also set to 1 (enabled).
BENn This flag indicates whether event n signals are heeded or ignored.
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0
1
Event n is disabled (ignored).
Event n is enabled.
BPI+0064h
Bit
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15
BPI event enable register 1
14
13
12
11
10
9
BPI_ENA1
8
7
6
Name
fo
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Type
Reset
5
4
3
2
1
0
BEN2 BEN2 BEN1 BEN1 BEN1 BEN1
1
0
9
8
7
6
R/W R/W R/W R/W R/W R/W
0
0
0
0
0
0
8.3
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This register enables the events that are signaled by the TDMA timing generator: by clearing a register bit, the
corresponding event signal is ignored. After a hardware reset, all the enable bits default to 1 (enabled). Upon receiving
the TDMA_EVTVAL pulse, all register bits are also set to 1 (enabled).
BENn This flag indicates whether event n signals are heeded or ignored.
0 Event n is disabled (ignored).
1
Event n is enabled.
Automatic Power Control (APC) Unit
8.3.1
General Description
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The Automatic Power Control (APC) unit controls the Power Amplifier (PA) module. Through APC unit, the proper
transmit power level of the handset can be set to ensure that burst power ramping requirements are met. In one TDMA
frame, up to 7 TDMA events can be enabled to support multi-slot transmission. In practice, 5 banks of ramp profiles are
used in one frame to make up 4 consecutive transmission slots.
The shape and magnitude of the ramp profiles are configurable to fit ramp-up (ramp up from zero), intermediate ramp
(ramp between transmission windows), and ramp-down (ramp down to zero) profiles. Each bank of the ramp profile
consists of 16 8-bit unsigned values, which are adjustable for different conditions.
The entries from one bank of the ramp profile are partitioned into two parts, with 8 values in each half. In normal
operation, the entries in the left half are multiplied by a 10-bit left scaling factor, and the entries in the right half are
multiplied by a 10-bit right scaling factor. The values are then truncated to form 16 10-bit intermediate values. Finally
the intermediate ramp profile are linearly interpolated into 32 10-bit values and sequentially used to update the D/A
converter. The block diagram of the APC unit is shown in Figure 50 .
The
MT
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The APB bus interface is 32 bits wide. Four write accesses are required to program each bank of ramp profile.
detailed register allocations are listed in Table 63.
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PDN_APC
( from global
control)
Power and
clock
control
APB
I/F
DAC_PU
Ramp profile,
scaling factor,
& offset
Multiplier &
interpolator
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APB BUS
(32bits
data bus)
TDMA_APCSTR (0~6)
TDMA_APCEN
( from TDMA timer ) ( from TDMA timer) QBIT_EN
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MT6228 GSM/GPRS Baseband Processor Data Sheet Revision 1.0
Output
buffer
APC_BUS
(10 bits)
50 Block diagram of APC unit.
8.3.2
Register Definitions
APC+0000h
Bit
Name
Type
Bit
Name
Type
APC 1st ramp profile #0
31
30
29
15
14
13
28
27
ENT3
R/W
12
11
ENT1
R/W
26
25
24
10
9
8
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APC unit
23
22
21
7
6
5
20
19
ENT2
R/W
4
3
ENT0
R/W
Figure
APC_PFA0
18
17
16
2
1
0
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The register stores the first four entries of the first power ramp profile. The first entry resides in the least significant byte
[7:0], the second entry in the second byte [15:8], the third entry in the third byte [23:16], and the fourth in the most
significant byte [31:24]. Since this register provides no hardware reset, the programmer must configure it before any APC
event takes place.
ENT3
The field signifies the 4th entry of the 1st ramp profile.
ENT2
The field signifies the 3rd entry of the 1st ramp profile.
ENT1
The field signifies the 2nd entry of the 1st ramp profile.
ENT0
The field signifies the 1st entry of the 1st ramp profile.
The overall ramp profile register definition is listed in Table 63.
Register Address
APC +0000h
APC +0004h
APC +0008h
APC +000Ch
MT
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APC +0020h
Register Function
Acronym
st
APC_PFA0
st
APC_PFA1
st
APC 1 ramp profile #2
APC_PFA2
APC 1st ramp profile #3
APC_PFA3
APC 1 ramp profile #0
APC 1 ramp profile #1
nd
APC_PFB0
nd
APC 2 ramp profile #0
APC +0024h
APC 2 ramp profile #1
APC_PFB1
APC +0028h
APC 2nd ramp profile #2
APC_PFB2
APC +002Ch
APC 2nd ramp profile #3
APC_PFB3
APC +0040h
rd
APC_PFC0
APC 3 ramp profile #0
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APC +0044h
APC 3rd ramp profile #1
APC_PFC1
APC +0048h
APC 3rd ramp profile #2
APC_PFC2
APC +004Ch
APC 3rd ramp profile #3
APC_PFC3
APC +0060h
th
APC_PFD0
th
APC 4 ramp profile #0
APC +0064h
APC 4 ramp profile #1
APC_PFD1
APC +0068h
APC 4th ramp profile #2
APC_PFD2
APC +006Ch
th
APC_PFD3
th
APC_PFE0
APC +0080h
APC 5 ramp profile #0
APC +0084h
APC 5th ramp profile #1
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APC 4 ramp profile #3
APC_PFE1
th
APC +0088h
APC_PFE2
APC 5 ramp profile #2
th
APC +008Ch
APC_PFE3
APC 5 ramp profile #3
th
APC 6 ramp profile #0
APC_PFF0
APC +00A4h
APC 6th ramp profile #1
APC_PFF1
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APC +00A0h
th
APC +00A8h
APC_PFF2
APC 6 ramp profile #2
th
APC +00ACh
APC 6 ramp profile #3
APC +00C0h
APC 7th ramp profile #0
APC_PFF3
APC_PFG0
th
APC +00C4h
APC_PFG1
APC 7 ramp profile #1
th
APC +00C8h
APC 7 ramp profile #2
APC +00CCh
APC 7th ramp profile #3
APC_PFG2
APC_PFG3
Table 63 APC ramp profile registers
Bit
Name
Type
Reset
15
14
APC 1st ramp profile left scaling factor
13
12
11
10
9
8
7
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APC +0010h
6
5
4
SF
R/W
1_0000_0000
3
APC_SCAL0L
2
1
0
The register stores the left scaling factor of the 1st ramp profile. This factor multiplies the first 8 entries of the 1st ramp
profile to provide the scaled profile, which is then interpolated to control the D/A converter.
After a hardware reset, the initial value of the register is 256. In this case, no scaling is done (each entry of the ramp
profile is multiplied by 1), because the 8 least significant bits are truncated after multiplication.
The overall scaling factor register definition is listed in Table 64 .
SF
Scaling factor.
APC +0014h
15
14
APC 1st ramp profile right scaling factor
13
12
11
10
9
8
7
6
APC_SCAL0R
5
4
SF
R/W
1_0000_0000
3
2
1
0
MT
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Bit
Name
Type
Reset
After a hardware reset, the value is 256.
The register stores the right scaling factor of the 1st ramp profile. This factor multiplies the last 8 entries of the 1st ramp
profile to provide the scaled profile, which is then interpolated to control the D/A converter.
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After a hardware reset, the initial value of the register is 256. In this case, no scaling is done (each entry of the ramp
profile is multiplied by 1), because the 8 least significant bits are truncated after multiplication.
The overall scaling factor register definition is listed in Table 64 .
Scaling factor.
APC+0018h
Bit
Name
Type
Reset
15
After a hardware reset, the value is 256.
APC 1st ramp profile offset value
14
13
12
11
10
9
8
7
APC_OFFSET0
6
5
4
OFFSET
R/W
0
3
2
1
0
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SF
There are 7 offset values for the corresponding ramp profile.
OFFSET Offset value for the corresponding ramp profile.
The overall offset register definition is listed in Table 64.
Register Address
Register Function
After a hardware reset, the default value is 0.
Acronym
st
APC +0010h
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The 1st offset value also serves as the pedestal value. The value is used to power up the APC D/A converter before the RF
signals start to transmit. The D/A converter is then biased on the value, to provide the initial control voltage for the
external control loop. The exact value depends on the characteristics of the external components. The timing to output
the pedestal value is configurable through the TDMA_BULCON2 register of the timing generator; its valid range is 0~127
quarter-bits of time after the baseband D/A converter is powered up.
APC 1 ramp profile left scaling factor
st
APC_SCAL0L
APC 1 ramp profile right scaling factor
APC_SCAL0R
APC +0018h
APC 1st ramp profile offset value
APC_OFFSET0
APC +0030h
APC +0034h
APC +0038h
APC +0050h
APC +0054h
APC +0058h
APC +0070h
APC +0074h
APC +0078h
APC +0090h
APC +0094h
APC +0098h
APC +00B0h
APC +00B4h
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APC +0014h
APC +00B8h
nd
APC_SCAL1L
nd
APC 2 ramp profile right scaling factor
APC_SCAL1R
APC 2nd ramp profile offset value
APC_OFFSET1
APC 2 ramp profile left scaling factor
rd
APC_SCAL2L
rd
APC 3 ramp profile right scaling factor
APC_SCAL2R
APC 3rd ramp profile offset value
APC_OFFSET2
APC 3 ramp profile left scaling factor
th
APC_SCAL3L
th
APC_SCAL3R
th
APC 4 ramp profile offset value
APC_OFFSET3
APC 5th ramp profile left scaling factor
APC_SCAL4L
APC 4 ramp profile left scaling factor
APC 4 ramp profile right scaling factor
th
APC_SCAL4R
th
APC 5 ramp profile offset value
APC_OFFSET4
APC 6th ramp profile left scaling factor
APC_SCAL5L
APC 5 ramp profile right scaling factor
th
APC_SCAL5R
th
APC_OFFSET5
th
APC 6 ramp profile right scaling factor
APC 6 ramp profile offset value
APC 7 ramp profile left scaling factor
APC_SCAL6L
APC +00D4h
APC 7th ramp profile right scaling factor
APC_SCAL6R
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APC +00D0h
APC +00D8h
th
APC 7 ramp profile offset value
APC_OFFSET6
Table 64 APC scaling factor and offset value registers
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APC+00E0h
13
12
11
10
APC_CON
Bit
Name
Type
Reset
15
9
8
7
6
5
4
3
2
1
GSM
R/W
1
0
FPU
R/W
0
GSM
Defines the operation mode of the APC module. In GSM mode, each frame has only one slot, thus only one
scaling factor and one offset value must be configured. If the GSM bit is set, the programmer needs only to
configure APC_SCAL0L and APC_OFFSET0. If the bit is not set, the APC module is operating in GPRS mode.
0 The APC module is operating in GPRS mode.
1 The APC module is operating in GSM mode. Default value.
Forces the APC D/A converter to power up. Test only.
0 The APC D/A converter is not forced to power up. The converter is only powered on when the transmission
window is opened. Default value.
1 The APC D/A converter is forced to power up.
FPU
8.3.3
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APC control register
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MT6228 GSM/GPRS Baseband Processor Data Sheet Revision 1.0
Ramp Profile Programming
The first value of the first normalized ramp profile must be written in the least significant byte of the APC_PFA0 register.
The second value must be written in the second least significant byte of the APC_PFA0, and so on.
Each ramp profile can be programmed to form an arbitrary shape.
RX
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The start of ramping is triggered by one of the TDMA_APCSTR signals. The timing relationship between
TDMA_APCSTR and TDMA slots is depicted in Figure 51 for 4 consecutive time slots case. The power ramping profile
must comply with the timing mask defined in GSM SPEC 05.05. The timing offset values for 7 ramp profiles are stored
in the TDMA timer register from TDMA_APC0 to TDMA_APC6.
TX
TX
TX
TX
MX
RX
Figure 51 Timing diagram of TDMA_APCSTR.
Because the APC unit provides more than 5 ramp profiles, up to 4 consecutive transmission slots can accommodated. The
2 additional ramp profiles are useful particularly when the timing between the last 2 transmission time slots and CTIRQ is
uncertain; software can begin writing the ramp profiles for the succeeding frame during the current frame, alleviating the
risk of not writing the succeeding frame’s profile data in time.
MT
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In GPRS mode, to fit the intermediate ramp profile between different power levels, a simple scaling scheme is used to
synthesize the ramp profile. The equation is as follows:
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DA 0 = OFF + S 0 ⋅
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MT6228 GSM/GPRS Baseband Processor Data Sheet Revision 1.0
DN 15, pre + DN 0
2
DN k −1 + DN k
DA 2 k = OFF + S l ⋅
, k = 1,...,15
2
DA 2 k +1 = OFF + S l ⋅ DN k , k = 0,1,...,15
DA
DN
S0
S1
OFF
=
=
=
=
=
the data to present to the D/A converter,
the normalized data which is stored in the register APC_PFn,
the left scaling factor stored in register APC_SCALnL,
the right scaling factor stored in register APC_SCALnR, and
the offset value stored in the register APC_OFFSETn.
fo
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where
if 8 > k ≥ 0
if 15 ≥ k ≥ 8
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0,
1,
l=
The subscript n denotes the index of the ramp profile.
The ramp calculation before interpolation is as depicted in Figure 52.
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During each ramp process, each word of the normalized profile is first multiplied by 10-bit scaling factors and added to an
offset value to form a bank of 18-bit words. The first 8 words (in the left half part as in Figure 52) are multiplied by the
left scaling factor S0 and the last 8 words (in the right half part as in Figure 52) are multiplied by the right scaling factor S1.
The lowest 8 bits of each word are then truncated to get a 10-bit result. The scaling factor is 0x100, which represents no
scaling on reset. A value smaller than 0x100 scales the ramp profile down, and a value larger than 100 scales the ramp
profile up.
DN15 * S1 + OFF
DN12 * S1 + OFF
16 Qb
DN8 * S1 + OFF
DN4 * S0 + OFF
DN0 * S0 + OFF
DN4 * S0
DN8 * S1
OFF
Figure 52
The timing diagram of the APC ramp.
MT
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The 16 10-bit words are linearly interpolated into 32 10-bit words. A 10-bit D/A converter is then used to convert these 32
ramp values at a rate of 1.0833 MHz, that is, at quarter-bit rate. The timing diagram is shown in Figure 53 and the final
value is retained on the output until the next event occurs.
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TDMA_APCSTR0
TDMA_APCSTR1
TDMA_APCSTR2
TDMA_APCSTRx
TDMA_APCEN
TX
offset
Ramp Profile
Ramp Profile
TX Burst
TDMA_APCSTR1
APC_DATA
Figure 53
Timing diagram of the APC ramping.
Ramp Profile
TX Burst
~29.5us
~29.5us
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MT6228 GSM/GPRS Baseband Processor Data Sheet Revision 1.0
The APC unit is only powered up when the APC window is open. The APC window is controlled by configuring the
TDMA registers TDMA_BULCON1 and TDMA_BULCON2. Please refer to the TDMA timer unit for more detailed
information.
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The first offset value stored in the register APC_OFFSET0 also serves as the pedestal value, which is used to provide the
initial power level for the PA.
Since the profile is not double-buffered, the timing to write the ramping profile is critical. The programmer must be
restricted from writing to the data buffer during the ramping process, otherwise the ramp profile may be incorrect and lead
to a malfunction.
8.4
Automatic Frequency Control (AFC) Unit
8.4.1
General Description
MT
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The Automatic Frequency Control (AFC) unit provides the direct control of the oscillator for frequency offset and Doppler
shift compensation. The block diagram is of the AFC unit depicted in Figure 54. The module utilizes a 13-bit D/A
converter to achieve high-resolution control. Two modes of operation provide flexibility when controlling the oscillator;
they are described as follows.
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TDMA_EVTVAL
( from TDMA timer )
APB
BUS
TDMA_AFC
( from TDMA timer )
AFC_BUS
+ 0'( $
. 5 44$ &
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MT6228 GSM/GPRS Baseband Processor Data Sheet Revision 1.0
: 5 0- 5 0
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VC
AFC
9 9 $ % ', 0$ 8 &'0$
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F_MODE
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I_MODE
nPDN_DAC
AFC unit
PDN_AFC
( from global control )
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Figure 54 Block Diagram of the AFC Controller
In timer-triggered mode, the TDMA timer controls the AFC enabling events. Each TDMA frame can pulse at most four
events. Double buffer architecture is supported. AFC values can be written to the write buffers. When the signal
TDMA_EVTVAL is received, the values in the write buffers are latched into the active buffers. However, AFC values can
also be written to the active buffers directly. Each event is associated with an active buffer sharing the same index.
When a TDMA event is triggered by TDMA_AFC, the value in the corresponding active buffer takes effect. Figure 55
shows a timing diagram of AFC events with respect to TX/RX/MX windows. In this mode, the D/A converter can stay
powered on or be powered on for a programmable duration (256 quarter-bits, by default). The latter option is for power
saving.
MX
TX
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RX
AFC_STR0
AFC_STR1
MX
AFC_STR2
AFC_STR3
Figure 55 Timing Diagram for the AFC Controller
In immediate mode, the MCU can directly control the AFC value without event-triggering. The value written by the MCU
takes effect immediately. In this mode, the D/A converter must be powered on continuously. When transitioning from
immediate mode into timer-triggered mode (by setting flag I_MODE in the register AFC_CON to be 0), the D/A converter
is kept powered on for a programmable duration (256 quarter-bits by default) if a TDMA_AFC is not been pulsed. The
duration is prolonged upon receiving events.
8.4.2
Register Definitions
AFC+0000h
Bit
15
Name
AFC control register
14
13
12
11
10
9
8
7
AFC_CON
6
5
MT
K
Type
Reset
4
3
2
1
0
RDAC F_MO FETE I_MO
T
DE
NV
DE
R/W R/W R/W R/W
0
0
0
0
Four control modes are defined and can be controlled through the AFC control register.
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AFC +0004h
Bit
Name
Type
15
AFC data register 0
14
13
12
11
10
9
8
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RDACT The flag enables the direct read operation from the active buffer. Note that the control flag is only applicable to
the four data buffers AFC_DAT0, AFC_DAT1, AFC_DAT2, and AFC_DAT3.
0 APB read from the write buffer.
1 APB read from the active buffer.
FETENV The flag enables the direct write operation to the active buffer. Note that the control flag is only applicable
to the four data buffers AFC_DAT0, AFC_DAT1, AFC_DAT2, and AFC_DAT3.
0 APB write to the write buffer.
1 APB write to the active buffer.
F_MODE The flag enables the force power up mode.
0 The force power up mode is not enabled.
1 The force power up mode is enabled.
I_MODE
The flag enables immediate mode. To enable immediate mode, force power up mode must also be enabled.
0 Immediate mode is not enabled.
1 Immediate mode is enabled.
7
6
AFCD
R/W
5
4
3
AFC_DAT0
2
1
0
The register stores the AFC value for the event 0 triggered by the TDMA timer in timer-triggered mode. When the
RDACT or FETENV bit (of the AFC_CON register) is set, the data transfer operates on the active buffer. When neither
flag is set, the data transfer operates on the write buffer.
AFCD The AFC sample for the D/A converter.
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Four registers (AFC_DAT0, AFC_DAT1, AFC_DAT2, AFC_DAT3) of the same type correspond to the event triggered by
the TDMA timer. The four registers are summarized in Table 65.
Register Address
Register Function
Acronym
AFC +0004h
AFC control value 0
AFC_DAT0
AFC +0008h
AFC control value 1
AFC_DAT1
AFC +000Ch
AFC control value 2
AFC_DAT2
AFC +0010h
AFC control value 3
AFC_DAT3
Table 65 AFC Data Registers
Immediate mode can only use AFC_DAT0. In this mode, only the control value in the AFC_DAT0 write buffer is used to
control the D/A converter. Unlike timer-triggered mode, the control value in AFC_DAT0 write buffer can bypass the
active buffer stage and be directly coupled to the output buffer in immediate mode. To use immediate mode, program the
AFC_DAT0 in advance and then enable immediate mode by setting the I_MODE flag in the AFC_CON register.
MT
K
The registers AFC_DATA0, AFC_DAT1, AFC_DAT2, and AFC_DAT3 have no initial values, thus the register must be
programmed before any AFC event takes place. The AFC value for the D/A converter, i.e., the output buffer value, is
initially 0 after power up before any event occurs.
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AFC +0014h
Bit
Name
Type
Reset
15
14
AFC power up period
13
12
11
10
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AFC_PUPER
9
8
7
6
PU_PER
R/W
ff
5
4
3
2
1
0
Stores the AFC power up period.
After hardware power up, the field is initialized to 255.
MT
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PU_PER
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This register stores the AFC power up period, which is 13 bits wide. The value ranges from 0 to 8191. If the I_MODE
or F_MODE flag is set, this register has no effect since the D/A converter is powered up continuously. If neither flag is set,
the register controls the power up duration of the D/A converter. During that period, the signal nPDN_DAC in Figure 54
is set to 1(power up).
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Baseband Front End
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Baseband Front End is a modem interface between TX/RX mixed-signal modules and digital signal processor (DSP). We
can divide this block into two parts (see Figure 56). The first is the uplink (transmitting) path, which converts bit-stream
from DSP into digital in-phase (I) and quadrature (Q) signals for TX mixed-signal module. The second part is the downlink
(receiving) path, which receives digital in-phase (I) and quadrature (Q) signals from RX mixed-signal module, performs
FIR filtering and then sends results to DSP. Figure 56 illustrates interconnection around Baseband Front End. In the figure
the shadowed blocks compose Baseband Front End. The uplink path is mainly composed of GMSK Modulator and uplink
parts of Baseband Serial Ports, and the downlink path is mainly composed of RX digital FIR filter and downlink parts of
Baseband Serial Ports. Baseband Serial Ports is a serial interface used to communicate with DSP. In addition, there is a set
of control registers in Baseband Front End that is intended for control of TX/RX mixed-signal modules, inclusive of
calibration of DC offset and gain mismatch of downlink analog-to-digital (A/D) converters as well as uplink
digital-to-analog (D/A) converters in TX/RX mixed-signal modules. The timing of bit streaming through Baseband Front
End is completely under control of TDMA timer. Usually only either of uplink and downlink paths is active at one moment.
However, both of the uplink and downlink paths will be active simultaneously when Baseband Front End is in loopback
mode.
When either of TX windows in TDMA timer is opened, the uplink path in Baseband Front End will be activated.
Accordingly components on the uplink path such as GMSK Modulator will be powered on, and then TX mixed-signal
module is also powered on. The subblock Baseband Serial Ports will sink TX data bits from DSP and then forward them to
GMSK Modulator. The outputs from GMSK Modulator are sent to TX mixed-signal module in format of I/Q signals.
Finally D/A conversions are performed in TX mixed-signal module and the output analog signal is output to RF module.
MT
K
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Similarly, while either of RX windows in TDMA timer is opened, the downlink path in Baseband Front End will be
activated. Accordingly components on the downlink path such as RX mixed-signal module and RX digital FIR filter are
then powered on. First A/D conversions are performed in RX mixed-signal module, and then the results in format of I/Q
signals are sourced to RX digital FIR filter. Low-Pass filtering is performed in RX digital FIR filter. Finally the results will
be sourced to DSP through Baseband Serial Ports.
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"
#
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Figure 56 Block Diagram Of Baseband Front End
9.1
Baseband Serial Ports
General Description
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9.1.1
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MT6228 GSM/GPRS Baseband Processor Data Sheet Revision 1.0
Baseband Front End communicates with DSP through the sub block of Baseband Serial Ports. Baseband Serial Ports
interfaces with DSP in serial manner. It implies that DSP must be configured carefully in order to have Baseband Serial
Ports cooperate with DSP core correctly.
If downlink path is programmed in bypass-filter mode (NOT bypass-filter loopback mode), behavior of Baseband Serial
Ports will completely be different from that in normal function mode. The special mode is for testing purpose. Please see
the subsequent section of Downlink Path for details.
TX and RX windows are under control of TDMA timer. Please refer to functional specification of TDMA timer for the
details how to open/close a TX/RX window. Opening/Closing of TX/RX windows has two major effects on Baseband Front
End. They are power on/off of corresponding components and data souring/sinking. It is worth noticing that Baseband
Serial Ports is only intended for sinking TX data from DSP or sourcing data to DSP. It does not involve power on/off of
TX/RX mixed-signal modules.
MT
K
As far as downlink path is concerned, if a RX window is opened by TDMA timer Baseband Front End will have RX
mixed-signal module proceed to make A/D conversion, RX digital filter proceed to perform filtering and Baseband Serial
Ports be activated to source data from RX digital filter to DSP no matter the data is meaningful or not. However, the
interval between the moment that RX mixed-signal module is powered on and the moment that data proceed to be dumped
by Baseband Serial Ports can be well controlled in TDMA timer. Lets denote as RX enable window the interval that RX
mixed-signal module is powered on and denote as RX dump window the interval that data is dumped by Baseband Serial
Ports. If the first samples from RX digital filter desire to be discarded, the corresponding RX enable window must cover the
corresponding RX dump window. Notes that RX dump windows always win over RX enable windows. It means that a RX
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dump window will always raise a RX enable window. RX enable windows can be raised by TDMA timer or by
programming RX power-down bit in global control registers to be ‘0’. It is useful in debugging environment.
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Similarly, a TX dump window refers to the interval that Baseband Serial Ports sinks data from DSP on uplink path and a
TX enable window refers to the interval that TX mixed-signal module is powered on. A TX window controlled by TDMA
timer involves a TX dump window and a TX enable window simultaneously. The interval between the moment that TX
mixed-signal module is powered on and the moment that data proceed to be forwarded from DSP to GMSK modulator by
Baseband Serial Ports can be well controlled in TDMA timer. TX dump windows always win over TX enable windows. It
means that a TX dump window will always raise a TX enable window. TX enable windows can be raised by TDMA timer
or by programming TX power-down bit in global control registers to be ‘0’. It is useful in debugging environment.
9.1.2
Register Definitions
BFE+0000h
Bit
15
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Accordingly, Baseband Serial Ports are only under control of TX/RX dump window. Note that if TX/RX dump window is
not integer multiplies of bit-time it will be extended to be integer multiplies of bit-time. For example, if TX/RX dump
window has interval of 156.25 bit-times then it will be extended as 157 bit-times in Baseband Serial Ports.
Base-band Common Control Register
14
13
12
11
10
9
8
Name
Type
Reset
7
6
5
4
3
BFE_CON
2
1
0
BCIE
N
R/W
0
This register is for common control of Baseband Front End. It consists of ciphering encryption control.
BFE +0004h
Bit
15
Name
Type
Reset
14
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BCIEN The bit is for ciphering encryption control. If the bit is set to ‘1’, XOR will performed on some TX bits (payload of
Normal Burst) and ciphering pattern bit from DSP, and then the result is forwarded to GMSK Modulator.
Meanwhile, Baseband Front End will generate signals to drive DSP ciphering process produce corresponding
ciphering pattern bits if the bit is set to ‘1’. If the bit is set to ‘0’, the TX bit from DSP will be forwarded to GMSK
modulator directly. Baseband Front End will not activate DSP ciphering process.
0 Disable ciphering encryption.
1 Enable ciphering encryption.
Base-band Common Status Register
13
12
11
10
9
8
7
BFE_STA
6
5
4
3
2
1
0
BULF BULE BDLF BDLE
S
N
S
N
RO
RO
RO
RO
0
0
0
0
MT
K
This register indicates status of Baseband Front End. Under control of TDMA timer, Baseband Front End can be driven in
several statuses. If downlink path is enabled, then the bit BDLEN will be ‘1’. Otherwise the bit BDLEN will be ‘0’. If
downlink parts of Baseband Serial Ports is enabled, the bit BDLFS will be ‘1’. Otherwise the bit BDLFS will be ‘0’. If
uplink path is enabled, then the bit BULEN will be ‘1’. Otherwise the bit BULEN will be 0. If uplink parts of Baseband
Serial Ports is enabled, the bit BULFS will be ‘1’. Otherwise the bit BULFS will be ‘0’. Once downlink path is enabled, RX
mixed-signal module will also be powered on. Similarly, once uplink path is enabled, TX mixed-signal module will also be
powered on. Furthermore, enabling Baseband Serial Ports for downlink path refers to dumping results from RX digital FIR
filter to DSP. Similarly, enabling Baseband Serial Ports for uplink path refers to forwarding TX bit from DSP to GMSK
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9.2
Downlink Path (RX Path)
9.2.1
General Description
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BDLEN Indicate if downlink path is enabled.
0 Disabled
1 Enabled
BDLFS Indicate if Baseband Serial Ports for downlink path is enabled.
0 Disabled
1 Enabled
BULEN Indicate if uplink path is enabled.
0 Disabled
1 Enabled
BULFS Indicate if Baseband Serial Ports for uplink path is enabled.
0 Disabled
1 Enabled
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modulator. BDLEN stands for “Baseband DownLink ENable”. BULEN stands for “Baseband UpLink ENable”. BDLFS
stands for “Baseband DownLink FrameSync”. BULFS stands for “Baseband UpLink FrameSync”.
On downlink path, the subblock between RX mixed-signal module and Baseband Serial Ports is RX Path. It mainly consists
of a digital FIR filter, two sets of multiplexing paths for loopback modes, interface for RX mixed-signal module and
interface for Baseband Serial Ports. The block diagram is shown in Figure 57.
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While RX enable windows are opened, RX Path will issue control signals to have RX mixed-signal module proceed to
make A/D conversion. As each conversion is finished, one set of I/Q signals will be latched. There exists a digital FIR filter
for these I/Q signals. The result of filtering will be dumped to Baseband Serial Ports whenever RX dump windows are
opened.
In addition to normal function, there are two loopback modes in RX Path. One is bypass-filter loopback mode, and the other
is through-filter loopback mode. They are intended for verification of DSP firmware and hardware. The bypass-filter
loopback mode refers to that RX digital FIR filter is not on the loopback path. However, the through-filter loopback mode
refers to that RX digital FIR filter is on the loopback path.
The I/Q swap functionality is used to swap I/Q channel signals from RX mixed-signal module before they are latched into
RX digital FIR filter. It is intended to provide flexibility for I/Q connection with RF modules.
MT
K
There is a special data path not shown in Figure 57. It is a data path from RX mixed-signal module to Baseband Serial
Ports. If downlink path is programmed in “Bypass RX digital FIR filter” mode, ADC outputs out of RX mixed-signal
module will be directed into Baseband Serial Ports directly. Therefore these data can be dumped into DSP and RX FIR
filtering will not be performed on them. Limited by bandwidth of the serial interface between Baseband Serial Ports and
DSP, only ADC outputs which are from either I-channel or Q-channel ADC can be dumped into DSP. Both of I- and
Q-channel ADC outputs cannot be dumped simultaneously. Which channel will be dumped is controlled by the register bit
SWAP of the register RX_CFG when downlink path is programmed in “Bypass RX digital FIR filter” mode. See register
definition below for details. The mode is for measurement of performance of A/D converters in RX mixed-signal module.
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! #
+
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Figure 57 Block Diagram Of RX Path
Register Definitions
BFE +0010h
Bit
15
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RX Configuration Register
14
13
Name
LPDN
Type
Reset
R/W
0000
12
11
10
9
8
7
RX_CFG
6
5
4
3
2
1
0
BYPF SWA
LTR
P
R/W R/W
0
0
This register is for configuration of downlink path, inclusive of configuration of RX mixed-signal module and RX path in
Baseband Front End.
MT
K
SWAP The register bit is for control of whether I/Q channel signals need swap before they are input to Baseband Front
End. It provides flexibility of connection of I/Q channel signals between RF module and baseband module. The
register bit has another purpose when the register bit “BYPFLTR” is set to 1. Please see description for the register
bit “BYPFLTR”.
0 I- and Q-channel signals are not swapped
1 I- and Q-channel signals are swapped
BYPFLTR Bypass RX FIR filter control. The register bit is used to configure Baseband Front End in the state called
“Bypass RX FIR filter state” or not. Once the bit is set to ‘1’, RX FIR filter will be bypassed. That is, ADC outputs
of RX mixed-signal module that are 11-bit resolution and at sampling rate of 1.083MHz can be dumped into DSP
by Baseband Serial Ports and RX FIR filtering will not be performed on them. Limited by bandwidth of the serial
interface between Baseband Serial Ports and DSP, these ADC outputs are all from either I-channel or Q-channel
ADC. Both of I- and Q-channel ADC outputs cannot be dumped simultaneously. When the bit is set to ‘1’ and the
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BFE +0014h
Bit
Name
Type
Reset
15
14
RX Control Register
13
12
11
10
9
8
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register bit “SWAP” is set to ‘0’, ADC outputs of I-channel will be dumped. When the bit is set to ‘1’ and the
register bit “SWAP” is set to ‘1’, ADC outputs of Q-channel will be dumped.
0 Not bypass RX FIR filter
1
Bypass RX FIR filter
LPDN Late power down control. RX mixed-signal module needs two power down signals. There must exist some delay
between them. The register field is used to control the late-arriving power-down signal.
0000 The delay between two power-down signals is one 13 MHz period.
0001 The delay between two power-down signals is two 13 MHz period.
0010 The delay between two power-down signals is three 13 MHz period.
…
0001 The delay between two power-down signals is 256 13 MHz period.
7
6
5
4
3
RX_CON
2
1
0
BLPEN[1:0]
R/W
0
This register is for control of downlink path, inclusive of control of RX mixed-signal module and RX path in Baseband
Front End module.
BFE +0020h
Bit
Name
Type
Reset
15
14
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BLPEN The register field is for loopback configuration selection in Baseband Front End.
00 Configure Baseband Front End in normal function mode
01 Configure Baseband Front End in bypass-filter loopback mode
10 Configure Baseband Front End in through-filter loopback mode
11 Reserved
RX Digital FIR Filter Coefficient Register 0
13
12
11
10
9
D9
R/W
0
8
D8
R/W
0
7
D7
R/W
0
6
D6
R/W
0
RX_FIR_COEF0
5
D5
R/W
0
4
D4
R/W
0
3
D3
R/W
0
2
D2
R/W
0
1
D1
R/W
0
0
D0
R/W
0
MT
K
The register is for RX digital FIR filter coefficient 0. It is coded in 2’s complement. That is, its maximum is 255 and its
minimum is –256. It will be applied on the latest and the oldest taps of 31 taps. The equivalent process flow of RX digital
FIR filtering is shown in Figure 58.
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MT6228 GSM/GPRS Baseband Processor Data Sheet Revision 1.0
.
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1
9
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0
2
3
4
5
, 3
'
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'
, 1
'
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06
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07
1/
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Figure 58 Equivalent Process Flow Of RX Digital FIR Filtering
BFE +0024h
Bit
Name
Type
Reset
15
14
RX Digital FIR Filter Coefficient Register 1
13
12
11
10
9
D9
R/W
0
8
D8
R/W
0
7
D7
R/W
0
6
D6
R/W
0
RX_FIR_COEF1
5
D5
R/W
0
4
D4
R/W
0
3
D3
R/W
0
2
D2
R/W
0
1
D1
R/W
0
0
D0
R/W
0
The register is for RX digital FIR filter coefficient 1. It is coded in 2’s complement. That is, its maximum is 255 and its
minimum is –256.
RX Digital FIR Filter Coefficient Register 2
MT
K
BFE +0028h
Bit
Name
Type
Reset
15
14
13
12
11
10
9
D9
R/W
0
8
D8
R/W
0
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7
D7
R/W
0
6
D6
R/W
0
RX_FIR_COEF2
5
D5
R/W
0
4
D4
R/W
0
3
D3
R/W
0
2
D2
R/W
0
1
D1
R/W
0
0
D0
R/W
0
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MT6228 GSM/GPRS Baseband Processor Data Sheet Revision 1.0
The register is for RX digital FIR filter coefficient 2. It is coded in 2’s complement. That is, its maximum is 255 and its
minimum is –256.
Bit
Name
Type
Reset
15
14
RX Digital FIR Filter Coefficient Register 3
13
12
11
10
9
D9
R/W
0
8
D8
R/W
0
7
D7
R/W
0
6
D6
R/W
0
RX_FIR_COEF3
5
D5
R/W
0
4
D4
R/W
0
3
D3
R/W
0
2
D2
R/W
0
1
D1
R/W
0
0
D0
R/W
0
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BFE +002Ch
The register is for RX digital FIR filter coefficient 3. It is coded in 2’s complement. That is, its maximum is 255 and its
minimum is –256.
Bit
Name
Type
Reset
15
14
RX Digital FIR Filter Coefficient Register 4
13
12
11
10
9
D9
R/W
0
8
D8
R/W
0
7
D7
R/W
0
6
D6
R/W
0
RX_FIR_COEF4
5
D5
R/W
0
4
D4
R/W
0
3
D3
R/W
0
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BFE +0030h
2
D2
R/W
0
1
D1
R/W
0
0
D0
R/W
0
The register is for RX FIR filter coefficient 4. It is coded in 2’s complement. That is, its maximum is 255 and its minimum
is –256.
BFE +0034h
Bit
Name
Type
Reset
15
14
RX Digital FIR Filter Coefficient Register 5
13
12
11
10
9
D9
R/W
0
8
D8
R/W
0
7
D7
R/W
0
6
D6
R/W
0
5
D5
R/W
0
4
D4
R/W
0
3
D3
R/W
0
RX_FIR_COEF5
2
D2
R/W
0
1
D1
R/W
0
0
D0
R/W
0
BFE +0038h
Bit
Name
Type
Reset
15
14
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The register is for RX digital FIR filter coefficient 5. It is coded in 2’s complement. That is, its maximum is 255 and its
minimum is –256.
RX Digital FIR Filter Coefficient Register 6
13
12
11
10
9
D9
R/W
0
8
D8
R/W
0
7
D7
R/W
0
6
D6
R/W
0
RX_FIR_COEF6
5
D5
R/W
0
4
D4
R/W
0
3
D3
R/W
0
2
D2
R/W
0
1
D1
R/W
0
0
D0
R/W
0
The register is for RX digital FIR filter coefficient 6. It is coded in 2’s complement. That is, its maximum is 255 and its
minimum is –256.
BFE +003Ch
Bit
Name
Type
Reset
15
14
RX Digital FIR Filter Coefficient Register 7
13
12
11
10
9
D9
R/W
0
8
D8
R/W
0
7
D7
R/W
0
6
D6
R/W
0
RX_FIR_COEF7
5
D5
R/W
0
4
D4
R/W
0
3
D3
R/W
0
2
D2
R/W
0
1
D1
R/W
0
0
D0
R/W
0
MT
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The register is for RX digital FIR filter coefficient 7. It is coded in 2’s complement. That is, its maximum is 255 and its
minimum is –256.
BFE +0040h
Bit
Name
15
14
RX Digital FIR Filter Coefficient Register 8
13
12
11
10
9
D9
8
D8
547/616
7
D7
6
D6
RX_FIR_COEF8
5
D5
4
D4
3
D3
2
D2
1
D1
0
D0
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Type
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
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MT6228 GSM/GPRS Baseband Processor Data Sheet Revision 1.0
R/W
0
R/W
0
R/W
0
The register is for RX digital FIR filter coefficient 8. It is coded in 2’s complement. That is, its maximum is 255 and its
minimum is –256.
Bit
Name
Type
Reset
15
14
RX Digital FIR Filter Coefficient Register 9
13
12
11
10
9
D9
R/W
0
8
D8
R/W
0
7
D7
R/W
0
6
D6
R/W
0
RX_FIR_COEF9
5
D5
R/W
0
4
D4
R/W
0
3
D3
R/W
0
2
D2
R/W
0
1
D1
R/W
0
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BFE +0044h
0
D0
R/W
0
BFE +0048h
Bit
Name
Type
Reset
15
14
Re
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The register is for RX digital FIR filter coefficient 9. It is coded in 2’s complement. That is, its maximum is 255 and its
minimum is –256.
RX Digital FIR Filter Coefficient Register 10
13
12
11
10
9
D9
R/W
0
8
D8
R/W
0
7
D7
R/W
0
6
D6
R/W
0
5
D5
R/W
0
4
D4
R/W
0
3
D3
R/W
0
RX_FIR_COEF1
0
2
D2
R/W
0
1
D1
R/W
0
0
D0
R/W
0
The register is for RX digital FIR filter coefficient 10. It is coded in 2’s complement. That is, its maximum is 255 and its
minimum is –256.
Bit
Name
Type
Reset
15
14
RX Digital FIR Filter Coefficient Register 11
13
12
11
10
9
D9
R/W
0
8
D8
R/W
0
7
D7
R/W
0
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BFE +004Ch
6
D6
R/W
0
5
D5
R/W
0
4
D4
R/W
0
3
D3
R/W
0
RX_FIR_COEF1
1
2
D2
R/W
0
1
D1
R/W
0
0
D0
R/W
0
The register is for RX digital FIR filter coefficient 11. It is coded in 2’s complement. That is, its maximum is 255 and its
minimum is –256.
BFE +0050h
Bit
Name
Type
Reset
15
14
RX_FIR_COEF1
2
RX Digital FIR Filter Coefficient Register 12
13
12
11
10
9
D9
R/W
0
8
D8
R/W
0
7
D7
R/W
0
6
D6
R/W
0
5
D5
R/W
0
4
D4
R/W
0
3
D3
R/W
0
2
D2
R/W
0
1
D1
R/W
0
0
D0
R/W
0
The register is for RX digital FIR filter coefficient 12. It is coded in 2’s complement. That is, its maximum is 255 and its
minimum is –256.
Bit
Name
Type
Reset
15
14
RX_FIR_COEF1
3
RX Digital FIR Filter Coefficient Register 13
MT
K
BFE +0054h
13
12
11
10
9
D9
R/W
0
8
D8
R/W
0
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7
D7
R/W
0
6
D6
R/W
0
5
D5
R/W
0
4
D4
R/W
0
3
D3
R/W
0
2
D2
R/W
0
1
D1
R/W
0
0
D0
R/W
0
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MT6228 GSM/GPRS Baseband Processor Data Sheet Revision 1.0
The register is for RX digital FIR filter coefficient 13. It is coded in 2’s complement. That is, its maximum is 255 and its
minimum is –256.
Bit
Name
Type
Reset
15
14
RX_FIR_COEF1
4
RX Digital FIR Filter Coefficient Register 14
13
12
11
10
9
D9
R/W
0
8
D8
R/W
0
7
D7
R/W
0
6
D6
R/W
0
5
D5
R/W
0
4
D4
R/W
0
3
D3
R/W
0
2
D2
R/W
0
1
D1
R/W
0
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BFE +0058h
0
D0
R/W
0
The register is for RX digital FIR filter coefficient 14. It is coded in 2’s complement. That is, its maximum is 255 and its
minimum is –256.
Bit
Name
Type
Reset
15
14
RX Digital FIR Filter Coefficient Register 15
13
12
11
10
9
D9
R/W
0
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BFE +005Ch
8
D8
R/W
0
7
D7
R/W
0
6
D6
R/W
0
5
D5
R/W
0
4
D4
R/W
0
3
D3
R/W
0
RX_FIR_COEF1
5
2
D2
R/W
0
1
D1
R/W
0
0
D0
R/W
0
The register is for RX digital FIR filter coefficient 15. It is coded in 2’s complement. That is, its maximum is 255 and its
minimum is –256.
Uplink Path (TX Path)
9.3.1
General Description
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9.3
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The purpose of the uplink path inside Baseband Front End is to sink TX symbols, one bit for each symbol, from DSP, then
perform GMSK modulation on them, then perform offset cancellation on I/Q digital signals out of GMSK modulator, and
finally control TX mixed-signal module to make D/A conversion on I/Q signals out of GMSK Modulator with offset
cancellation. Accordingly, the uplink path is composed of uplink parts of Baseband Serial Ports, GSM Encryptor, GMSK
Modulator and Offset Cancellation. The block diagram of uplink path is shown in Figure 59. On uplink path, the content of
a burst, including tail bits, data bits, and training sequence bits is sent from DSP. Translated by GMSK Modulator, these bits
will become I/Q digital signals. Offset cancellation will be performed on these I/Q digital signals to compensate offset error
of D/A converters (DAC) in TX mixed-signal module. Finally the generated I/Q digital signals will be input to TX
mixed-signal module that contains two DAC for I/Q signal respectively. The details of each subblock will be described in
subsequent sections.
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MT6228 GSM/GPRS Baseband Processor Data Sheet Revision 1.0
Figure 59 Block Diagram Of Uplink Path
9.3.2
Register Definitions
BFE +0060h
Bit
15
14
TX Configuration Register
13
12
11
10
9
8
Re
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TDMA timer having a quarter-bit timing accuracy gives the timing windows for uplink operation. Uplink operation is
controlled by TX enable window and TX dump window of TDMA timer. Usually TX enable window is opened earlier than
TX dump window. When TX enable window of TDMA timer is opened, uplink path in Baseband Front End will power on
GSK TX mixed-signal module and thus has it drive valid outputs to RF module. However, uplink parts of Baseband Serial
Ports still don’t sink data from DSP through the serial interface between Baseband Serial Ports and DSP until now. Uplink
parts of Baseband Serial Ports will not sink data from DSP until TX dump window of TDMA timer is opened.
7
6
5
4
3
TX_CFG
2
Type
Reset
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Name
1
0
APND
EN
R/W
0
This register is for configuration of uplink path, inclusive of configuration of TX mixed-signal module and TX path in
Baseband Front End.
APNDEN
0
1
Appending Bits Enable. The register bit is used to control the ending scheme of GMSK modulation.
Suitable for GPRS. If a TX enable window contains several TX dump window, then GMSK modulator will
still output in the intervals between two TX dump window and all 1’s will be fed into GMSK modulator. Note
that when the bit is set to ‘0’, the interval between the moment at which TX enable window is activated
and the moment at which TX dump window is activated must be multiples of one bit time.
Suitable for GSM only. After a TX dump window, GMSK modulator will only output for some bit time.
BFE +0064h
Bit
15
Name
14
TX Control Register
13
12
11
10
9
8
MT
K
Type
Reset
7
TX_CON
6
5
4
3
2
1
0
CALR IQSW
CEN
P
R/W R/W
0
0
This register is for control of uplink path, inclusive of control of TX mixed-signal module and TX path in Baseband Front
End.
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MT6228 GSM/GPRS Baseband Processor Data Sheet Revision 1.0
CALRCEN Calibration for TX low-pass-filter Enable. The procedure to make calibration processing for smoothing filter
in BBTX mixed-signal module is as follows:
1. Write ‘1’ to the register bit CARLC in the register TX_CON of Baseband Front End in order to activate clock
required for calibration process. Initiate calibration process.
Write ‘1’ to the register bit STARTCALRC of Analog Chip Interface. Start calibration process.
3.
Read the register bit CALRCDONE of Analog Chip Interface. If read as ‘1’, then calibration process finished.
Otherwise repeat the step.
4.
Write ‘0’ to the register bit STARTCALRC of Analog Chip Interface. Stop calibration process.
5.
Write ‘0’ to the register bit CARLC in the register TX_CON of Baseband Front End in order to deactivate
clock required for calibration process. Terminate calibration process.
6.
The result of calibration process can be read from the register field CALRCOUT of the register
BBTX_AC_CON1 of Analog Chip Interface. Software can set the value to the register field CALRCSEL for
3-dB cutoff frequency selection of smoothing filter in DAC of BBTX of Analog Chip Interface.
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2.
0 Dectivate clock required for calibration process.
1 Activate clock required for calibration process.
IQSWP The register bit is for control of I/Q swapping. When the bit is set to ‘1’, phase on I/Q plane will rotate in inverse
direction.
0: I and Q are not swapped.
1: I and Q are swapped.
Bit
Name
Type
Reset
15
14
TX I/Q Channel Offset Compensation Register
13
12
11
10
OFFQ[5:0]
R/W
000000
9
8
7
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BFE +0068h
6
5
4
3
2
OFFI[5:0]
R/W
000000
TX_OFF
1
0
The register is for offset cancellation of I-channel DAC in TX mixed-signal module. It is for compensation of offset error
caused by I/Q-channel DAC in TX mixed-signal module. It is coded in 2’s complement, that is, with maximum 31 and
minimum –32.
MT
K
OFFI Value of offset cancellation for I-channel DAC in TX mixed-signal module
OFFQ Value of offset cancellation for Q-channel DAC in TX mixed-signal module
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10 Timing Generator
Timing is the most critical issue in GSM/GPRS applications. The TDMA timer provides a simple interface for the MCU to
program all the timing-related events for receive event control, transmit event control, and timing adjustment. Detailed
descriptions are mentioned in Section 10.1.
10.1
TDMA timer
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In pause mode, the 13MHz reference clock may be switched off temporarily for the purpose of power saving and the
synchronization to the base-station is maintained by using a low power 32KHz crystal oscillator. The 32KHz oscillator is
not accurate and therefore it should be calibrated prior to entering pause mode. The calibration sequence, pause begin
sequence and the wake up sequence are described in Section 10.2.
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The TDMA timer unit is composed of three major blocks: Quarter bit counter, Signal generator and Event registers.
Figure 60 The block diagram of TDMA timer
By default, the quarter-bit counter continuously counts from 0 to the wrap position. In order to apply to cell synchronization
and neighboring cell monitoring, the wrap position can be changed by the MCU to shorten or lengthen a TDMA frame. The
wrap position is held in the TDMA_WRAP register and the current value of the TDMA quarter bit counter may be read by
the MCU via the TDMA_TQCNT register.
The signal generator handles the overall comparing and event-generating processes. When a match has occurred between
the quarter bit counter and the event register, a predefined control signal is generated. These control signals may be used for
on-chip and off-chip purposes. Signals that change state more than once per frame make use of more than one event
register.
MT
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The event registers are programmed to contain the quarter bit position of the event that is to occur. The event registers are
double buffered. The MCU writes into the first register, and the event TDMA_EVTVAL transfers the data from the write
buffer to the active buffer, which is used by the signal generator for comparison with the quarter bit count. The
TDMA_EVTVAL signal itself may be programmed at any quarter bit position. These event registers could be classified into
four groups:
On-chip Control Events
TDMA_EVTVAL
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This event allows the data values written by the MCU to pass through to the active buffers.
TDMA_WRAP
TDMA quarter bit counter wrap position. This sets the position at which the TDMA quarter bit counter resets back to zero.
The default value is 4999, changing this value will advance or retard the timing events in the frame following the next
TDMA_EVTVAL signal.
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TDMA_DTIRQ
DSP TDMA interrupt requests. DTIRQ triggers the DSP to read the command from the MCU/DSP Shard RAM to schedule
the activities that will be executed in the current frame.
TDMA_CTIRQ1/CTIRQ2
MCU TDMA interrupt requests.
TDMA_AUXADC [1:0]
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This signal triggers the monitoring ADC to measure the voltage, current, temperature, device id etc..
TDMA_AFC [3:0]
This signal powers up the automatic frequency control DAC for a programmed duration after this event.
Note: For both MCU and DSP TDMA interrupt requests, these signals are all active Low during one quarter bit duration
and they should be used as edge sensitive events by the respective interrupt controllers.
On-chip Receive Events
TDMA_BDLON [5:0]
These registers are a set of six which contain the quarter bit event that initiates the receive window assertion sequence
which powers up and enables the receive ADC, and then enables loading of the receive data into the receive buffer.
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TDMA_BDLOFF [5:0]
These registers are a set of six which contain the quarter bit event that initiates the receive window de-assertion sequence
which disables loading of the receive data into the receive buffer, and then powers down the receive ADC.
TDMA_RXWIN[5:0]
DSP TDMA interrupt requests. TDMA_RXWIN is usually used to initiate the related RX processing including two modes.
In single-shot mode, TDMA_RXWIN is generated when the BRXFS signal is de-asserted. In repetitive mode,
TDMA_RXWIN will be generated both regularly with a specific interval after BRXFS signal is asserted and when the
BRXFS signal is de-asserted.
Figure 61 The timing diagram of BRXEN and BRXFS
Note: TDMA_BDLON/OFF event registers, together with TDMA_BDLCON register, generate the corresponding BRXEN
and BRXFS window used to power up/down baseband downlink path and control the duration of data transmission to the
DSP, respectively.
MT
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On-chip Transmit Events
TDMA_APC [6:0]
These registers initiate the loading of the transmit burst shaping values from the transmit burst shaping RAM into the
transmit power control DAC.
TDMA_BULON [3:0]
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This register contains the quarter bit event that initiates the transmit window assertion sequence which powers up the
modulator DAC and then enables reading of bits from the transmit buffer into the GMSK modulator.
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TDMA_BULOFF [3:0]
This register contains the quarter bit event that initiates the transmit window de-assertion sequence which disables the
reading of bits from the transmit buffer into the GMSK modulator, and then power down the modulator DAC.
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Figure 62 The timing diagram of BTXEN and BTXFS
Note: TDMA_BULON/OFF event registers, together with TDMA_BULCON1, TDMA_BULCON2 register, generate the
corresponding BTXEN, BTXFS and APCEN window used to power up/down the baseband uplink path, control the duration
of data transmission from the DSP and power up/down the APC DAC, respectively.
Off-chip Control Events
TDMA_BSI [15:0]
The quarter bit positions of these 16 BSI events are used to initiate the transfer of serial words to the transceiver and
synthesizer for gain control and frequency adjustment.
10.1.1
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TDMA_BPI [21:0]
The quarter bit positions of these 22 BPI events are used to generate changes of state on the output pins to control the
external radio components.
Register Definitions
TDMA_EVTENA
0
TDMA+0150h Event Enable Register 0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
Name AFC3 AFC2 AFC1 AFC0 BDL5 BDL4 BDL3 BDL2 BDL1 BDL0
Type R/W
Reset
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
2
1
0
CTIRQ CTIRQ DTIR
2
1
Q
R/W R/W R/W
0
0
0
MT
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DTIRQ Enable TDMA_DTIRQ
CTIRQn
Enable TDMA_CTIRQn
AFCn Enable TDMA_AFCn
BDLn Enable TDMA_BDLONn and TDMA_BDLOFFn
For all these bits,
0 function is disabled
1 function is enabled
TDMA_EVTENA
1
TDMA+0154h Event Enable Register 1
Bit
15
14
13
12
11
10
9
8
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BUL3 BUL2 BUL1 BUL0
R/W R/W R/W R/W
0
0
0
0
APC6 APC5 APC4 APC3 APC2 APC1 APC0
R/W R/W R/W R/W R/W R/W R/W
0
0
0
0
0
0
0
APCn Enable TDMA_APCn
BULn Enable TDMA_BULONn and TDMA_BULOFFn
For all these bits,
0 function is disabled
1 function is enabled
TDMA_EVTENA
2
TDMA +0158h Event Enable Register 2
BSIn
8
BSI8
R/W
0
BSI event enable control
0 Disable TDMA_BSIn
1 Enable TDMA_BSIn
TDMA +015Ch Event Enable Register 3
8
BPI8
R/W
0
7
BPI7
R/W
0
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Bit
15
14
13
12
11
10
9
Name BPI15 BPI14 BPI13 BPI12 BPI11 BPI10 BPI9
Type R/W R/W R/W R/W R/W R/W R/W
Reset
0
0
0
0
0
0
0
7
BSI7
R/W
0
6
BSI6
R/W
0
5
BSI5
R/W
0
4
BSI4
R/W
0
3
BSI3
R/W
0
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Bit
15
14
13
12
11
10
9
Name BSI15 BSI14 BSI13 BSI12 BSI11 BSI10 BSI9
Type R/W R/W R/W R/W R/W R/W R/W
Reset
0
0
0
0
0
0
0
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Name GPRS
Type R/W
Reset
0
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6
BPI6
R/W
0
5
BPI5
R/W
0
4
BPI4
R/W
0
3
BPI3
R/W
0
15
14
13
12
BPIn
BPI event enable control
0 Disable TDMA_BPIn
1 Enable TDMA_BPIn
11
10
9
8
7
6
14
13
12
11
AUX
Auxiliary ADC event enable control
0 Disable Auxiliary ADC event
1 Enable Auxiliary ADC event
10
9
8
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15
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7
0
BSI0
R/W
0
TDMA_EVTENA
3
2
BPI2
R/W
0
1
BPI1
R/W
0
0
BPI0
R/W
0
5
4
3
2
1
0
BPI21 BPI20 BPI19 BPI18 BPI17 BPI16
R/W R/W R/W R/W R/W R/W
0
0
0
0
0
0
TDMA_EVTENA
5
TDMA+0164h Event Enable Register 5
Bit
Name
Type
Reset
1
BSI1
R/W
0
TDMA_EVTENA
4
TDMA+0160h Event Enable Register 4
Bit
Name
Type
Reset
2
BSI2
R/W
0
6
5
4
3
2
1
0
AUX1 AUX0
R/W R/W
0
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TDMA_WRAPOF
S
TDMA +0170h Qbit Timer Offset Control Register
Bit
Name
Type
Reset
15
13
12
11
10
9
8
7
6
5
TOI
This register defines the value used to advance the Qbit timer in unit of 1/4 quarter bit; the timing advance will be
take place as soon as the TDMA_EVTVAL is occurred, and it will be cleared automatically.
14
13
12
11
10
9
8
7
6
TQ_BIAS[13:0]
R/W
0
5
4
3
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15
3
2
1
0
TOI[1:0]
R/W
0
TDMA_REGBIA
S
TDMA +0174h Qbit Timer Biasing Control Register
Bit
Name
Type
Reset
4
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2
1
0
TQ_BIAS This register defines the Qbit offset value which will be added to the registers being programmed. It only
takes effects on AFC, BDLON/OFF, BULON/OFF, APC, AUXADC, BSI and BPI event registers.
TDMA +0180h DTX Control Register
Bit
Name
Type
15
13
12
11
10
9
8
7
DTX
DTX flag is used to disable the associated transmit signals
0 BULON0, BULOFF0, APC_EV0 & APC_EV1 are controlled by TDMA_EVTENA1 register
1 BULON0, BULOFF0, APC_EV0 & APC_EV1 are disabled
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14
6
5
4
TDMA_DTXCON
3
2
1
0
DTX3 DTX2 DTX1 DTX0
R/W R/W R/W R/W
TDMA +0184h Receive Interrupt Control Register
Bit
15
14
13
12
11
10
Name MOD5 MOD4 MOD3 MOD2 MOD1 MOD0
Type R/W R/W R/W R/W R/W R/W
9
8
7
TDMA_RXCON
6
5
4
RXINTCNT[9:0]
R/W
3
2
1
0
RXINTCNT TDMA_RXWIN interrupt generation interval in quarter bit unit
MODn Mode of Receive Interrupts
0 Single shot mode for the corresponding receive window
1 Repetitive mode for the corresponding receive window
TDMA +0188h Baseband Downlink Control Register
Bit
Name
Type
15
14
13
12
11
ADC_ON
R/W
10
9
8
7
TDMA_BDLCON
6
5
4
3
2
ADC_OFF
R/W
1
0
MT
K
ADC_ON BRXEN to BRXFS setup up time in quarter bit unit.
ADC_OFF BRXEN to BRXFS hold up time in quarter bit unit.
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TDMA_BULCON
1
TDMA +018Ch Baseband Uplink Control Register 1
15
14
13
12
11
DAC_ON
R/W
10
9
8
7
6
5
DAC_ON BTXEN to BTXFS setup up time in quarter bit unit.
DAC_OFF BTXEN to BTXFS hold up time in quarter bit unit.
14
13
12
11
10
9
8
7
1
0
6
5
4
3
APC_HYS
R/W
2
1
0
Re
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15
3
2
DAC_OFF
R/W
TDMA_BULCON
2
TDMA +0190h Baseband Uplink Control Register 2
Bit
Name
Type
4
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Bit
Name
Type
APC_HYS APCEN to BTXEN hysteresis time in quarter bit unit.
Type
Width
Reset Value
Name
Description
+0000h
+0004h
+0008h
+000Ch
+0010h
+0014h
+0018h
+0020h
+0024h
+0028h
+002Ch
+0030h
+0034h
+0038h
+003Ch
+0040h
+0044h
+0048h
+004Ch
+0050h
+0054h
+0058h
+005Ch
+0060h
+0064h
+0068h
+006Ch
+0070h
+0074h
+0078h
+007Ch
+0090h
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
[13:0]
[13:0]
[13:0]
[13:0]
[13:0]
[13:0]
[13:0]
[13:0]
[13:0]
[13:0]
[13:0]
[13:0]
[13:0]
[13:0]
[13:0]
[13:0]
[13:0]
[13:0]
[13:0]
[13:0]
[13:0]
[13:0]
[13:0]
[13:0]
[13:0]
[13:0]
[13:0]
[13:0]
[13:0]
[13:0]
[13:0]
[13:0]
—
0x1387
0x1387
0x0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TDMA_TQCNT
TDMA_WRAP
TDMA_WRAPIMD
TDMA_EVTVAL
TDMA_DTIRQ
TDMA_CTIRQ1
TDMA_CTIRQ2
TDMA_AFC0
TDMA_AFC1
TDMA_AFC2
TDMA_AFC3
TDMA_BDLON0
TDMA_BDLOFF0
TDMA_BDLON1
TDMA_BDLOFF1
TDMA_BDLON2
TDMA_BDLOFF2
TDMA_BDLON3
TDMA_BDLOFF3
TDMA_BDLON4
TDMA_BDLOFF4
TDMA_BDLON5
TDMA_BDLOFF5
TDMA_BULON0
TDMA_BULOFF0
TDMA_BULON1
TDMA_BULOFF1
TDMA_BULON2
TDMA_BULOFF2
TDMA_BULON3
TDMA_BULOFF3
TDMA_APC0
MT
K
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Address
557/616
Read quarter bit counter
Latched Qbit counter reset position
Direct Qbit counter reset position
Event latch position
DSP software control
MCU software control 1
MCU software control 2
The 1st AFC control
The 2nd AFC control
The 3rd AFC control
The 4th AFC control
Data serialization of the 1st RX block
Data serialization of the 2nd RX block
Data serialization of the 3rd RX block
Data serialization of the 4th RX block
Data serialization of the 5th RX block
Data serialization of the 6th RX block
Data serialization of the 1st TX slot
Data serialization of the 2nd TX slot
Data serialization of the 3rd TX slot
Data serialization of the 4th TX slot
The 1st APC control
MediaTek Inc. Confidential
TDMA_APC1
TDMA_APC2
TDMA_APC3
TDMA_APC4
TDMA_APC5
TDMA_APC6
TDMA_BSI0
TDMA_BSI1
TDMA_BSI2
TDMA_BSI3
TDMA_BSI4
TDMA_BSI5
TDMA_BSI6
TDMA_BSI7
TDMA_BSI8
TDMA_BSI9
TDMA_BSI10
TDMA_BSI11
TDMA_BSI12
TDMA_BSI13
TDMA_BSI14
TDMA_BSI15
TDMA_BPI0
TDMA_BPI1
TDMA_BPI2
TDMA_BPI3
TDMA_BPI4
TDMA_BPI5
TDMA_BPI6
TDMA_BPI7
TDMA_BPI8
TDMA_BPI9
TDMA_BPI10
TDMA_BPI11
TDMA_BPI12
TDMA_BPI13
TDMA_BPI14
TDMA_BPI15
TDMA_BPI16
TDMA_BPI17
TDMA_BPI18
TDMA_BPI19
TDMA_BPI20
TDMA_BPI21
TDMA_AUXEV0
TDMA_AUXEV1
TDMA_EVTENA0
TDMA_EVTENA1
TDMA_EVTENA2
TDMA_EVTENA3
The 2nd APC control
The 3rd APC control
The 4th APC control
The 5th APC control
The 6th APC control
The 7th APC control
BSI event 0
BSI event 1
BSI event 2
BSI event 3
BSI event 4
BSI event 5
BSI event 6
BSI event 7
BSI event 8
BSI event 9
BSI event 10
BSI event 11
BSI event 12
BSI event 13
BSI event 14
BSI event 15
BPI event 0
BPI event 1
BPI event 2
BPI event 3
BPI event 4
BPI event 5
BPI event 6
BPI event 7
BPI event 8
BPI event 9
BPI event 10
BPI event 11
BPI event 12
BPI event 13
BPI event 14
BPI event 15
BPI event 16
BPI event 17
BPI event 18
BPI event 19
BPI event 20
BPI event 21
Auxiliary ADC event 0
Auxiliary ADC event 1
Event Enable Control 0
Event Enable Control 1
Event Enable Control 2
Event Enable Control 3
fo
r
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0x0000
0x0000
0x0000
0x0000
Re
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[13:0]
[13:0]
[13:0]
[13:0]
[13:0]
[13:0]
[13:0]
[13:0]
[13:0]
[13:0]
[13:0]
[13:0]
[13:0]
[13:0]
[13:0]
[13:0]
[13:0]
[13:0]
[13:0]
[13:0]
[13:0]
[13:0]
[13:0]
[13:0]
[13:0]
[13:0]
[13:0]
[13:0]
[13:0]
[13:0]
[13:0]
[13:0]
[13:0]
[13:0]
[13:0]
[13:0]
[13:0]
[13:0]
[13:0]
[13:0]
[13:0]
[13:0]
[13:0]
[13:0]
[13:0]
[13:0]
[15:0]
[15:0]
[15:0]
[15:0]
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R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
MT
K
+0094h
+0098h
+009Ch
+00A0h
+00A4h
+00A8h
+00B0h
+00B4h
+00B8h
+00BCh
+00C0h
+00C4h
+00C8h
+00CCh
+00D0h
+00D4h
+00D8h
+00DCh
+00E0h
+00E4h
+00E8h
+00ECh
+0100h
+0104h
+0108h
+010Ch
+0110h
+0114h
+0118h
+011Ch
+0120h
+0124h
+0128h
+012Ch
+0130h
+0134h
+0138h
+013Ch
+0140h
+0144h
+0148h
+014Ch
+01A0h
+01A4h
+01B0h
+01B4h
+0150h
+0154h
+0158h
+015Ch
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R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
[5:0]
[0]
[1:0]
[13:0]
[3:0]
[15:0]
[15:0]
[15:0]
[7:0]
0x0000
0x0000
0x0000
0x0000
—
—
—
—
—
TDMA_EVTENA4
TDMA_EVTENA5
TDMA_WRAPOFS
TDMA_REGBIAS
TDMA_DTXCON
TDMA_RXCON
TDMA_BDLCON
TDMA_BULCON1
TDMA_BULCON2
Slow Clocking Unit
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10.2
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Table 66 TDMA Timer Register Map
Event Enable Control 4
Event Enable Control 5
TQ Counter Offset Control Register
Biasing Control Register
DTX Control Register
Receive Interrupt Control Register
Downlink Control Register
Uplink Control Register 1
Uplink Control Register 2
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+0160h
+0164h
+0170h
+0174h
+0180h
+0184h
+0188h
+018Ch
+0190h
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MT6228 GSM/GPRS Baseband Processor Data Sheet Revision 1.0
Figure 63 The block diagram of the slow clocking unit
The slow clocking unit is provided to maintain the synchronization to the base-station timing using a 32KHz crystal
oscillator while the 13MHz reference clock is switched off. As shown in Figure 63, this unit is composed of frequency
measurement unit, pause unit, and clock management unit.
Because of the inaccuracy of the 32KHz oscillator, a frequency measurement unit is provided to calibrate the 32KHz crystal
taking the accurate 13MHz source as the reference. The calibration procedure always takes place prior to the pause period.
MT
K
The pause unit is used to initiate and terminate the pause mode procedure and it also works as a coarse time-base during the
pause period.
The clock management unit is used to control the system clock while switching between the normal mode and the pause
mode. SRCLKENA is used to turn on/off the clock squarer, DSP PLL and off-chip TCVCXO. CLOCK_OFF signal is used
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MT6228 GSM/GPRS Baseband Processor Data Sheet Revision 1.0
for gating the main MCU and DSP clock, and VCXO_OFF is used as the acknowledgement signal of the CLOCK_OFF
request.
10.2.1
Register Definitions
TDMA +0218h Slow clocking unit control register
Bit
15
14
13
12
11
10
9
8
7
SM_CON
6
5
4
3
1
0
PAUSE_STA FM_STAR
RT
T
W
W
0
0
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Name
2
Type
Reset
Re
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FM_START
Initiate the frequency measurement procedure
PAUSE_STARTInitiate the pause mode procedure at the next timer wrap position
TDMA +0220h Slow clocking unit status register
Bit
15
14
13
12
Name
Type
Bit
7
6
5
4
PAUSE_RQS
SETTLE_CP
Name
PAUSE_CPL PAUSE_INT
L
T
Type
R
R
R
R
SM_STA
11
10
9
3
2
1
8
PAUSE_ABO
RT
R
0
FM_CPL
FM_RQST
R
R
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FM_RQST
Frequency measurement procedure is requested
FM_CPL
Frequency measurement procedure is completed
PAUSE_RQST Pause mode procedure is requested
PAUSE_INT
Asynchronous wake up from pause mode
PAUSE_CPL Pause period is completed
SETTLE_CPL Settling period is completed
PAUSE_ABORT
Pause mode is aborted because of the reception of interrupt prior to entering pause mode
TDMA +022Ch Slow clocking unit configuration register
Bit
Name
Type
Reset
15
13
FM
SM
KP
EINT
RTC
MSDC
Enable interrupt generation upon completion of frequency measurement procedure
Enable interrupt generation upon completion of pause mode procedure
Enable asynchronous wake-up from pause mode by key press
Enable asynchronous wake-up from pause mode by external interrupt
Enable asynchronous wake-up from pause mode by real time clock interrupt
Enable asynchronous wake-up from pause mode by memory card insertion interrupt
MT
K
14
12
11
10
9
8
7
TDMA +0300h Power-down indication of DSP ROM
Bit
Name
Type
15
14
13
12
6
SM_CNF
5
4
MSDC RTC
R/W R/W
0
0
3
EINT
R/W
0
2
KP
R/W
0
1
SM
R/W
1
0
FM
R/W
1
DSPROMPD
11
10
9
8
7
6
5
4
3
2
1
0
PD_11 PD_10 PD_9 PD_8 PD_7 PD_6 PD_5 PD_4 PD_3 PD_2 PD_1 PD_0
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
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Reset
0
0
0
0
0
0
0
0
0
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MT6228 GSM/GPRS Baseband Processor Data Sheet Revision 1.0
0
0
0
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PD_X Power-down indication of page X of DSP CM ROM, X = 5:0
0 power down disabled
1 power down enabled
PD_X Power-down indication of page X of DSP PM ROM, X = 11:6
0 power down disabled
1 power down enabled
This register is for controlling the VIA-ROM, which requires a reset signal whenever the ROM is wakened up from
power-down mode. It means that as long as MCU plans to interrupt DSP from slow idle, the register should be programmed
in advance by 15us, otherwise the read data would be unknown. Total of 12 pages are programmable and is to be reserveed
for future usage, by which the MCU can dynamically wake-up only the pages that needs to be accessed. However, for now,
MCU can just simply program the register to all one’s or all zero’s. In view of the hardware, the 12 bits are ANDED as a
power-down indication. As the indication turns from high to low, a counter will be triggered to count the 15-us interval
according to the MCU clock, then a negative pulse will be generated as the ROM reset.
Address
Type
Width
Reset Value
Name
+0200h
+0204h
+0208h
+020Ch
+0210h
+0214h
+0218h
+021Ch
+0220h
+0224h
+0228h
+022Ch
R/W
R/W
R/W
R
R
R
W
R
R/W
R
R
R/W
[2:0]
[15:0]
[13:0]
[2:0]
[15:0]
[13:0]
[1:0]
[7:3,1:0]
[15:0]
[9:0]
[15:0]
[4:0]
—
—
—
—
—
—
SM_PAUSE_M
SM_PAUSE_L
SM_CLK_SETTLE
SM_FINAL_PAUSE_M
SM_FINAL_PAUSE_L
SM_QBIT_START
SM_CON
SM_STA
SM_FM_DURATION
SM_FM_RESULT_M
SM_FM_RESULT_L
SM_CNF
—
—
—
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10.2.2
0x0000
0x0000
Description
0x0000
MSB of pause duration
16 LSB of pause duration
Off-chip VCXO settling duration
MSB of final pause count
16 LSB of final pause count
TQ_ COUNT value at the start of the pause
SM control register
SM status register
32KHz measurement duration
10 MSB of frequency measurement result
16 LSB of frequency measurement result
SM configuration register
Frequency Measurement
Figure 64 Block Diagram of Frequency Measurement Unit
MT
K
The MCU writes into the SM_FM_DURATION register the number of clock cycles during which the 32768 Hz clock will
be measured. Then, the MCU sets the FM_START bit in the SM_CON register, the hardware sets the FM_RQST flag and
resets the FM_CPL flag automatically, and the 32kHz and 13MHz counters are simultaneously started from zero.
When the 32kHz counter reaches the terminal value determined by the SM_FM_DURATION register, the current value of
the 13MHz counter is stored in the SM_FM_RESULT register, the counters are stopped, the FM_RQST is reset, and the
FM_CPL flag is set.
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The SM_FM_DURATION is 16 bits wide, and the 32K counter counts 2 × ( N + 1) cycles of 32768Hz. This gives a
maximum of almost 4.00s measurement duration.
Measured _ frequency =
10.2.3
2 × ( SM _ FM _ DURATION + 1) × 13 × 10 6
SM _ FM _ RESULT
Pause Mode Operation
fo
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The MCU writes the pause and settling time into the SM_PAUSE_M, SM_PAUSE_L and SM_CLK_SETTLE registers and
the sum of the pause time and settling time must be as close as possible to the TDMA frame boundary, taking into account
of the frequency measurement result.
Re
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se
The MCU should set the PAUSE_START bit ahead of the TDMA_EVTVAL event. The hardware sets the PAUSE_RQST
flag and resets the PAUSE_INT, PAUSE_CPL, SETTLE_CPL, PAUSE_ABORT flags automatically, and the pause mode
operation will be initiated at the next timer wrap position.
When the pause duration reaches the programmed terminal value or the asynchronous wake up event is received, the pause
mode operation is ended/stopped/aborted and the corresponding flag is set (PAUSE_CPL, PAUSE_INT and
PAUSE_ABORT). Then, the MCU calculates the timing offset and adjusts the TDMA_WRAPIMD position accordingly.
The number of quarter bit time elapsed during the pause operation is:
Nb _ quarter _ bit = Kqbit × ( SM _ FINAL _ PAUSE + SM _ CLK _ SETTLE ) − ∆qbit
∆qbit = TQ _ WRAP − SM _ QBIT _ START
32k _ period _ duration
SM _ FM _ RESULT
=
quarter _ bit _ duration 24 × ( SM _ FM _ DURATION + 1)
MT
K
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Kqbit =
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MT6228 GSM/GPRS Baseband Processor Data Sheet Revision 1.0
11 Power, Clocks and Reset
fo
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This chapter describes the power, clock and reset management functions provided by MT6228. Together with Power
Management IC (PMIC), MT6228 offers both fine and coarse resolutions of power control through software programming.
With this efficient method, the developer can turn on selective resources accordingly in order to achieve optimized power
consumption. The operating modes of MT6228 as well as main power states provided by the PMIC are shown in Figure
65.
Active Mode
Software
Program
MT6228
Processors
Power On
Power Down
Mode
MT6228
Peripherals
Active State
Software
Program
Software
Program
Active Mode
Pause Mode
MT6228
Standby State
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Phone Power State
MT6228 Operating Mode
Sleep Mode
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Power On
Figure 65 Major Phone Power States and Operating Modes for MT6228 based terminal
11.1
11.1.1
B2PSI
General Description
MT
K
MT6228 uses a 3-wire B2PSI interface to connect to PMIC. This bi-directional serial bus interface allows baseband to
write to or read from PMIC. The bus protocol utilizes a 16-bit format. B2PSICK is the serial bus clock and is driven by
the master. B2PSIDAT is the serial data; master or slave can drive it. B2PSICS is the bus selection signal. Once the
B2PSICS goes LOW, baseband starts to transfer the 4 register bits followed by a read/write bit, then waits 3 clock cycles
for the PMIC B2PSI state machine to decode the operation for the next 8 data bits. The state machine should count 16
clocks to complete the data transfer.
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B 2 P S IC K
R3
R2
R1
R0
W
X
R e ce iv e
In d e x
B 2 P S IC S
X
X
D7
D6
R eg iste r
D ec o d e
D5
D4
D3
D2
B 2 P S IC K
R3
R2
R1
R0
R
X
R e ce iv e
In d e x
B 2 P S IC S
X
X
Register Definitions
B2PSI+0000h B2PSI data register
15
14
13
12
11
10
D6
9
D5
D4
D3
D2
R e a d R eg iste r C o n t en t
Figure 66 B2PSI bus timing
Bit
Name
Type
Reset
D7
R eg iste r
D ec o d e
T > 10 0nsec
11.1.2
D0
D1
D0
Re
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B 2 P S ID A T
D1
W rite R eg iste r C o n t en t
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B 2 P S ID A T
8
7
6
B2PSI_DATA [15:0]
R/W
0
5
4
3
B2PSI_DATA
2
1
0
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B2PSI_DATA The B2PSI DATA format contains 4 bit register + 3 bit do not care + write / read bit + 8 bit data.
0 Read operation
1 Write operation
To prevent a writing error, B2PSI_DATA must be set to 8216h before the actual data write.
B2PSI +0008h B2PSI baud rate divider register
Bit
Name
Type
Reset
15
14
13
12
B2PSI_DIV B2PSI clock rate divisor.
11
10
9
B2PSI _DIV
8
7
6
B2PSI _DIV [15:0]
R/W
0
5
4
3
15
Name
14
13
12
1
0
B2PSICK = system clock rate / div.
B2PSI+0010h B2PSI status register
Bit
2
11
10
9
8
MT
K
Type
Reset
7
B2PSI_STAT
6
5
4
3
2
1
0
WRIT
READ
E_SU
_REA
CCES
DT
S
RC
RC
0
0
READ_READY Read data ready.
0 Read data is not ready yet.
1 Read data is ready. The bit is cleared by reading B2PSI_STAT register or if B2PSI initializes a new transmit.
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WRITE_SUCCESS B2PSI write successfully.
0 B2PSI write is not finished yet.
1 B2PSI write has finished. The bit is cleared by reading B2PSI_STAT register or if B2PSI initializes a new
transmit.
B2PSI+0014h B2PSI CS to CK time register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
B2PSI_TIME
R/W
0
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Bit
Name
Type
Reset
B2PSI_TIME
11.2
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B2PSI_TIME The time interval that first B2PSICK is started after the B2PSICS is active low.
Time interval = 1/system clock * B2PSI_time.
Clocks
There are two major time bases in MT6228. The faster one is the 13 MHz clock originating from an off-chip
temperature-compensated voltage controlled oscillator (TCVCXO) that can be either 13 MHz or 26 MHz. This signal is
the input from the SYSCLK pad that is then converted to the square-wave signal by the clock squarer. The other time base
is the 32768 Hz clock generated by an on-chip oscillator connected to an external crystal. Figure 67 shows the clock
sources as well as their utilizations inside the chip.
104MHz ~
13MHz
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DSP
DCM
DSPCLK
ARMCLK
MCU_DIV2
MD PLL
SYSCLK
/2
Clock
Squarer
CLKSQ_PLD
32KHz
OSC
XIN
104MHz ~
13MHz
ARM
DCM
MCU
DCM
MCU
MCU Clock
AHB Bus Clock
52MHz ~
AHB
13MHz
104MHz
MPLL
MCUCLK
USB PLL
CLKSEL
APB Bus Clock
USB Clock
TV Clock
TV PLL
CLKSEL
32KHz Clock
XOUT
MT
K
MT6228 I/O
MT6228 Core
Figure 67 Clock distributions inside the MT6228.
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MT6228 GSM/GPRS Baseband Processor Data Sheet Revision 1.0
32.768 KHz Time Base
The 32768 Hz clock is always running. It is mainly used as the time base of the Real Time Clock (RTC) module, which
maintains time and date with counters. Therefore, the 32768 Hz oscillator and the RTC module are powered by separate
voltage supplies that are not be powered down when the other power supplies are.
11.2.2
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In low power mode, the 13 MHz time base is turned off, so the 32768 Hz clock is employed to update critical TDMA timer
and Watchdog Timer. This time base is also used to clock the keypad scanner logic.
13 MHz Time Base
A 1/2-divider, for MCU Clock, exists to allow usage of either 26 or 13 MHz TCVCXO as clock input.
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Three phase-locked loops (MDPLL, TPLL and UPLL) are used to generate four primary clocks, MCU_CLOCK,
DSP_CLOCK, USB_CLOCK and TV_CLOCK, and to clock modules in the MCU Clock Domain and DSP Clock Domain,
USB and TV Encoder, respectively. These PLLs require no off-chip components for operations and can be turned off
independently in order to save power. After power-on, all the PLLs are off by default and the source clock signal is
selected through multiplexers. The software takes care of the PLL lock time while changing the clock selections. The
PLLs and their usages are listed below.
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MDPLL provides the MCU system clock (MCU_CLOCK) and DSP system clock (DSP_CLOCK. DPLL).
MCU_CLOCK clocks the MCU core, MCU memory system and MCU peripherals as well.
DSP_CLOCK clocks DSP core and DSP-related modules. MDPLL can be programmed to provide
1X to 8X output of 13 MHz reference. However, because of the employment of DCM (dynamic
clock manager), the output of MDPLL are set as 104 MHz. The clock rates of MCU system and
DSP system can only be changed by programming the clock rate setting of MCU DCM and DSP
DCM.
UPLL provides the USB clock, USB_CLOCK. The UPLL input is a 4 MHz clock, which comes from 104 MHz
clock generated by MDPLL and then divided by 26. UPLL pumps the input clock source 12 times to generate 48
MHz for USB module.
TPLL provides the TV encoder clock, TV_CLOCK. The TPLL input is a 3 MHz clock, which comes from the
48 MHz clock generated by UPLL and then divided by 16. TPLL pumps the input clock source 9 times to
generate 27 MHz for TV encoder.
Note that PLLs need some time to become stable after being powered up. The software takes care of the PLL lock time
before switching them to the proper frequency. Usually, a software loop longer than the PLL lock time is employed to
deal with the problem.
For power management, the MCU software program may stop MCU Clock by setting the Sleep Control Register.
interrupt requests to MCU can terminate the sleep mode, and thus returning MCU to the running mode.
Any
MT
K
AHB can also be stopped by setting the Sleep Control Register. However, the behavior of AHB in sleep mode is a little
different from that of MCU. After entering Sleep Mode, it can be temporarily waken up by any “hreq” (bus request), and
then go back to sleep automatically after all “hreqs” de-assert. Therefore, any transactions can still take place as usual
during AHB sleep mode, and power is saved when there are no transactions. The penalty associated with this is that the
system loses some efficiency due to the switching on and off of the bus clock, but this impact is small.
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Dynamic Clock Switch of MCU Clock
Dynamic Clock Manager is implemented to allow MCU and DSP switching clock dynamically without any jitter, and
enabling signal drift, and system can operate stably during any clock rate switch.
Please note that MDPLL must be enabled and the frequency is set as 104 MHz. Before switching to the 104 MHz clock
rate, the clock from MD DIV2 feeds through dynamic clock manager (DCM) directly. That means if MD DIV2 is enabled,
the internal clock rate is the half of SYSCLK. Contrarily, the internal clock rate is identical to SYSCLK.
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However, the settings of some hardware modules are required to change before or after clock rate change. Software has
the responsibility of changing them at the proper timing. The following table is a list of hardware modules that need to
change their settings during a clock rate change.
Module Name
Programming Sequence
NAND
Wait state is changed before clock rate change if the clock rate changes from low
to high, and after clock rate change if the clock rate changes from high to low.
New wait state will not take effect until current EMI access is complete. Software
should insert a period of time before switching clock.
LCD
Change wait state while LCD in IDLE state.
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EMI
Wait state is changed before clock rate change if the clock rate changes from low
to high, and after the clock rate change if the clock rate changes from high to low.
The new wait state does not take effect until the current EMI access is complete.
Software should insert a period of time before switching clock.
Table 67 Programming sequence during clock switch
Register Definitions
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11.2.4
CONFG+0100h MDPLL Frequency Register
15
13
12
11
10
CALI
R/W
0
9
8
7
RST
R/W
0
6
SPD
Selects the Output Clock Rate for MDPLL.
Note: The output of MDPLL is a 104 MHz clock for normal function.
system is adjusted by programming MCU DCM and DSP DCM.
000
power down
001
13MHz x 2
010
13MHz x 3
011
13MHz x 4
000
13MHz x 5
101
13MHz x 6
110
13MHz x 7
111
13MHz x 8
Resets Control of MDPLL
0
Normal Operation
5
4
3
2
1
SPD
R/W
0
0
The clock rate of MCU system and DSP
MT
K
Bit
Name
Type
Reset
RST
14
MDPLL
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CALI
1
Reset the MDPLL
Calibration Control for MDPLL
CONFG+108h UPLL Frequency register
RST
Resets Control of UPLL
0
Normal Operation
1
Reset the UPLL
Calibration Control for UPLL
CALI
14
13
12
11
10
CALI
R/W
0
9
8
CONFG+10Ch TPLL Frequency register
Bit
Name
Type
Reset
15
RST
Reset Control of TPLL
0
Normal Operation
1
Reset the TPLL
Calibration Control for TPLL
CALI
14
13
12
11
10
CALI
R/W
0
9
8
CONFG+110h Clock Control Register
15
14
13
USB_ DSP_
TV_E
EXTC EXTC
Name
XTCK
K
K
Type R/W R/W R/W
Reset
0
0
0
12
11
10
9
8
7
RST
R/W
0
6
6
7
6
MDPL
TPLL_ UPLL
L_TM
TMA _TMA
A
R/W R/W R/W
0
0
0
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Bit
7
RST
R/W
0
5
4
3
2
1
0
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15
UPLL
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Bit
Name
Type
Reset
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MT6228 GSM/GPRS Baseband Processor Data Sheet Revision 1.0
5
5
4
3
4
3
CLKS
MD_D
Q_PL
IV2
D
R/W R/W
0
0
TPLL
2
1
0
CLK_CON
2
1
0
MDPL
L
R/W
0
MT
K
MDPLL Selects MCU and DSP clock source
0 MDPLL bypassed
1 Using MDPLL Clock
MD_DIV2 Control the x2 clock divider for MDPLL reference clock input.
0 Divider bypassed
1 Divider not bypassed
CLKSQ_PLD Pull Down Control
0 Disable
1 Enables
MDPLL_TMA MDPLL test mode
0 Disable
1 Enable
UPLL_TMA UPLL test mode
0 Disable
1 Enable
TPLL_TMA TPLL test mode
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CONFG+114h Sleep Control Register
12
11
10
9
8
7
MCU
Stops the MCU Clock to force MCU Processor to enter sleep mode. MCU clock resumes as long as there is an
interrupt request or system is reset.
0 MCU Clock is running
1 MCU Clock is stopped
Stops the AHB Bus Clock to force the entire bus to enter sleep mode. AHB clock resumes as long as there is an
interrupt request or system is reset.
0 AHB Bus Clock is running
1 AHB Bus Clock is stopped
Stops the DSP Clock.
0 DSP Bus Clock is running
1 DSP Bus Clock is stopped
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15
DSP
13
6
5
4
3
SLEEP_CON
Bit
Name
Type
Reset
AHB
14
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0 Disable
1 Enable
DSP_EXTCK DSP external clock. When enabled, an external clock source from PIN EINT0 is used instead of DSP
clock from MDPLL output.
0 Disable
1 Enable
USB_EXTCK USB external clock. When enabled, an external clock source from EINT1 is used instead of UPLL
output.
0 Disable
1 Enable
TV_EXTCK TV external clock. When enabled, an external clock source from EINT3 is used instead of TPLL output.
0 Disable
1 Enable
CONFG+0118h MCU Clock Control Register
Bit
Name
Type
Reset
15
14
13
12
11
10
9
ARM_FSEL
R/W
3
8
7
2
DSP
WO
0
1
AHB
WO
0
0
MCU
WO
0
MCUCLK_CON
6
5
4
3
2
1
MCU_FSEL
R/W
3
0
MT
K
MCU_FSELMCU clock frequency selection. This control register is used to control the output clock frequency of MCU
Dynamic Clock Manager. The clock frequency is from 13MHz to 52MHz. The waveforms of the output clock
are shown below.
Note that the clock period of 39MHz is not uniform. The shortest period of 39MHz clock is the same as the
period of 52MHz. As a result, the wait states of external interfaces, such as EMI, NAND, and so on, have
to be configured based on 52MHz timing. Therefore, the MCU performance executing in external memory
at 39MHz may be worse than at 26MHz.
Also note that the maximum latency of clock switch is 8 104MHz-clock periods. Software provides at least
8T locking time after clock switch command.
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104MHz
91MHz
78MHz
65MHz
52MHz
39MHz
26MHz
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13MHz
Figure 68 Output of Dynamic Clock Manager
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0
13MHz
1
26MHz
2
39MHz
3
52MHz
Others reserved
ARM_FSELARM clock frequency selection. This control register is used to control the output clock frequency of ARM
Dynamic Clock Manager. The clock frequency is from 13MHz to 104MHz. 39MHz is not a uniform period
clock.
0
13MHz
1
26MHz
2
39MHz
3
52MHz
4
reserved
5
reserved
6
reserved
7
104MHz
Others reserved
CONFG+011C
DSP Clock Control Register
h
Bit
Name
Type
Reset
15
14
13
12
11
10
9
8
7
DSPCLK_CON
6
5
4
3
2
1
DSP_FSEL
R/W
3
0
MT
K
DSP_FSEL DSP clock frequency selection. This control register is used to control the output clock frequency of DSP
Dynamic Clock Manager. The clock frequency is from 13MHz to 104MHz. 39MHz, 65MHz, 78MHz, and
91MHz are not a uniform period clock rate.
0
13MHz
1
26MHz
2
39MHz
3
52MHz
4
65MHz
5
78MHz
6
91MHz
7
104MHz
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Others reserved
11.3
Reset Generation Unit (RGU)
MT6228 provides three kinds of resets: hardware reset, watchdog
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Figure 69 shows the reset scheme used in MT6228.
reset, and software reset.
Figure 69 Reset Scheme Used in MT6228
General Description
11.3.1.1
Hardware Reset
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11.3.1
This reset is input through the SYSRST# pin, which is driven low during power-on. The hardware reset has a global
effect on the chip: all digital and analog circuits are initialized, except the Real Time Clock module. The initial states of
the MT6228 sub-blocks are as follows:.
All analog circuits are turned off.
All PLLs are turned off and bypassed.
base.
The 13 MHz system clock is the default time
Special trap states in GPIO.
11.3.1.2
Watchdog Reset
A watchdog reset is generated when the Watchdog Timer expires: the MCU software failed to re-program the timer counter
in time. This situation is typically induced by abnormal software execution, which can be aborted by a hardwired
watchdog reset. Hardware blocks that are affected by the watchdog reset are:
MT
K
MCU subsystem,
DSP subsystem, and
External components (trigged by software).
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MT6228 GSM/GPRS Baseband Processor Data Sheet Revision 1.0
Software Resets
Software resets are local reset signals that initialize specific hardware components. For example, if hardware failures are
detected, the MCU or DSP software may write to software reset trigger registers to reset those specific hardware modules to
their initial states.
The following modules have software resets.
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DSP Core
DSP Coprocessors
Register Definitions
RGU +0000h
Bit
15
14
Watchdog Timer Control Register
13
Name
12
11
10
9
8
KEY[7:0]
Type
Reset
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11.3.2
7
6
5
4
3
AUTO
-REST IRQ
ART
R/W R/W
0
0
WDT_MODE
2
1
0
EXTE EXTP ENAB
N
OL
LE
R/W
0
R/W
0
R/W
1
RGU +0004h
KEY
15
14
Watchdog Time-Out Interval Register
13
MT
K
Bit
Name
Type
Reset
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ENABLE Enables the Watchdog Timer.
0 Disables the Watchdog Timer.
1 Enables the Watchdog Timer.
EXTPOL Defines the polarity of the external watchdog pin.
0 Active low.
1
Active high.
EXTEN Specifies whether or not to generate an external watchdog reset signal.
0 The watchdog does not generate an external watchdog reset signal.
1 If the watchdog counter reaches zero, an external watchdog signal is generated.
IRQ
Issues an interrupt instead of a Watchdog Timer reset. For debug purposes, RGU issues an interrupt to the MCU
instead of resetting the system.
0 Disable.
1 Enable.
AUTO-RESTART
Restarts the Watchdog Timer counter with the value of WDT_LENGTH while task ID is written
into Software Debug Unit.
0 Disable. The counter restarts by writing KEY into the WDT_RESTART register.
1 Enable. The counter restarts by writing KEY into the WDT_RESTART register or by writing
task ID into the software debug unit.
KEY
Write access is allowed if KEY=0x22.
12
11
10
9
TIMEOUT[10:0]
WO
111_1111_1111b
8
7
WDT_LENGTH
6
5
4
3
2
KEY[4:0]
1
0
Write access is allowed if KEY=08h.
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TIMEOUT The counter is restarted with {TIMEOUT [10:0], 1_1111_1111b}. Thus the Watchdog Timer time-out
period is a multiple of 512*T32k=15.6ms.
Bit
Name
Type
Reset
15
14
Watchdog Timer Restart Register
13
12
11
10
9
8
7
KEY[15:0]
WDT_RESTART
6
5
KEY Restart the counter if KEY=1971h.
Bit
15
14
SW_W
Name WDT
DT
Type RO
RO
0
0
Reset
Watchdog Timer Status Register
13
12
11
10
9
8
3
2
1
0
WDT_STA
7
6
5
4
3
2
1
0
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RGU +000Ch
4
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RGU +0008h
WDT
RGU +0010h
Bit
15
14
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Indicates the cause of the watchdog reset.
0 Reset not due to Watchdog Timer.
1 Reset because the Watchdog Timer time-out period expired.
SW_WDT Indicates if the watchdog was triggered by software.
0 Reset not due to software-triggered Watchdog Timer.
1 Reset due to software-triggered Watchdog Timer.
NOTE: A system reset does not affect this register. This bit is cleared when the WTU_MODE register ENABLE bit is
written.
SW_PERIPH_RS
TN
CPU Peripheral Software Reset Register
13
12
11
10
9
8
7
6
5
4
DAMR USBR
ST
ST
Name
Type
Reset
R/W
0
3
2
1
0
KEY
R/W
0
KEY
Write access is allowed if KEY=37h.
DMARST Reset the DMA peripheral.
0 No reset.
1 Invoke a reset.
USBRST Reset the USB.
0 No reset.
1 Invoke a reset.
RGU +0014h
RST
14
13
MT
K
Bit
15
Name RST
Type R/W
Reset
0
DSP Software Reset Register
12
11
10
9
8
7
SW_DSP_RSTN
6
5
4
3
2
1
0
Controls the DSP System Reset Control.
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0
1
No reset.
Invoke a reset.
Bit
Name
Type
Reset
15
14
13
12
11
10
9
8
7
6
5
LENGTH[ 11:0]
R/W
FFFh
LENGTH This register indicates the reset duration when Watchdog Timer times out.
register IRQ bit is set to 1, an interrupt is issued instead of a reset.
Bit
Name
Type
Reset
15
14
4
3
Watchdog Timer Software Reset Register
13
12
11
10
9
8
7
KEY[15:0]
6
2
1
WDT_SWRST
5
4
3
2
1
Software-triggered Watchdog Timer reset. If the register content matches the KEY, a watchdog reset is issued.
if the WDT_MODE register IRQ bit is set to 1, an interrupt is issued instead of a reset.
KEY
1209h
0
However,
Software Power Down Control
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11.4
0
However, if the WDT_MODE
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RGU+001Ch
WDT_RSTINTRE
VAL
Watchdog Timer Reset Signal Duration Register
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RGU +0018h
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MT6228 GSM/GPRS Baseband Processor Data Sheet Revision 1.0
In addition to the Pause Mode capability while in the Standby State, the software program can also put each peripheral
independently into Power Down Mode while in the Active State by gating off their clock. The typical logic
implementation is depicted in Figure 70. For all configuration bits, 1 signifies that the function is in Power Down Mode,
and 0 means the function is in the Active Mode.
POWER DOWN
TESTMODE
CLOCK
Figure 70 Power Down Control at Block Level
11.4.1
Register Definitions
CONFG+300h Power Down Control 0 Register
15
14
13
MT
K
Bit
Name
MDPL
L
Type
R/W
12
11
10
9
8
CLK_ CLKS
UPLL TPLL
DIV2
Q
R/W
R/W
R/W
PDN_CON0
7
6
5
PPP
R/W
R/W
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4
3
2
WAVE
CHE TABL GCU
E
R/W R/W R/W
1
0
USB
DMA
R/W
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Reset
1
1
0
1
1
1
1
1
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CONFG +304h Power Down Control 1 Register
Bit
15
1
1
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DMA
Controls the DMA Controller Power Down.
USB
Controls the USB Controller Power Down.
GCU
Controls the GCU Controller Power Down.
WAVETALBE Controls the DSP WaveTable DMA Power Down.
CHE
Controls the CHE Power Down.
PPP
Controls the PPP Framer Power Down.
TPLL
Controls the TPLL Power Down.
UPLL
Controls the UPLL Power Down.
CLKSQ
Controls the Clock squarer Power Down.
CLK_DIV2 Controls the Input Clock DIV2 Power Down.
MDPLL
Controls the MCU and DSP PLL Power Down.
1
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MT6228 GSM/GPRS Baseband Processor Data Sheet Revision 1.0
PDN_CON1
14
13
12
11
10
9
8
7
6
5
4
3
2
UART
SWDB
UART
ALTE
UART
Name IRDA
B2PSI NFI PWM2
MSDC
LCD
PWM1 SIM
GPIO
3
G
2
R
1
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
0
KP
GPT
R/W
1
R/W
1
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GPT
Controls the General Purpose Timer Power Down.
KP
Controls the Keypad Scanner Power Down.
GPIO Controls the GPIO Power Down.
UART1 Controls the UART1 Controller Power Down.
SIM
Controls the SIM Controller Power Down.
PWM1 Controls the PWM1 Generator Power Down.
ALTER Controls the Alerter Generator Power Down.
LCD
Controls the Serial LCD Controller Power Down.
UART2 Controls the UART2 Controller Power Down.
MSDC Controls the MS/SD Controller Power Down.
PWM2 Controls the PWM2 Generator Power Down.
SWDBG
Controls the MCU/DSP Software Debug Power Down.
NFI
Controls the NAND FLASH Interface Power Down.
B2PSI Controls the Serial Port Interface Power Down.
UART3 Controls the UART3 Controller Power Down.
IRDA Controls the IrDA Framer Power Down.
CONFG +308h Power Down Control 2 Register
15
14
11
10
Name GMSK BBRX SCCB AAFE
DIV
GCC
Type R/W
Reset
1
R/W
1
R/W
1
R/W
1
13
R/W
1
MT
K
Bit
12
R/W
1
9
8
7
6
AUXA
BFE VAFE
FCS
D
R/W R/W R/W R/W
1
1
1
1
PDN_CON2
5
4
3
2
1
0
APC
AFC
BPI
BSI
RTC TDMA
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
TDMA Controls the TDMA Power Down.
RTC
Controls the RTC Power Down.
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BSI
Controls the BSI Power Down. This control is not be updated until both tdma_evtval and qbit_en are asserted.
BPI
Controls the BPI Power Down. This control is not be updated until both tdma_evtval and qbit_en are asserted.
AFC
Controls the AFC Power Down. This control is not be updated until both tdma_evtval and qbit_en are asserted.
APC
Controls the APC Power Down. This control is not be updated until both tdma_evtval and qbit_en are asserted.
FCS
Controls the FCS Power Down.
AUXAD Controls the AUX ADC Power Down.
VAFE Controls the Audio Front End of VBI Power Down.
BFE
Controls the Base-Band Front End Power Down.
GCU Controls the GCU Power Down.
DIV
Controls the Divider Power Down.
AAFE Controls the Audio Front End of MP3 Power Down.
SCCB Controls the SCCB Power Down.
BBRX Controls the BB RX Power Down.
GMSK Controls the GMSK Power Down.
CONFG +30Ch Power Down Control 3 Register
Bit
15
14
13
IMGD
Name DRZ
DCT
MA
Type R/W R/W R/W
Reset
1
1
1
12
11
10
9
8
7
6
5
4
3
ISP
PRZ JPEG MP4
G2D GCMQ GIF
PNG
IPP
TV
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
PDN_CON3
2
1
0
RESZ
CRZ
ICE
LB
R/W R/W R/W
1
1
1
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ICE
Enables the debug feature of the ARM7EJS core. Controls the DBGEN pin of the ICEBreaker.
RESZ LB
Controls the Post Resizer Power Down.
TV
Controls the TV Encoder Power Down.
CRZ
Controls the Capture Resizer Power Down.
IPP
Controls the Image Processor Power Down.
PNG
Controls the PNG Decoder Power Down.
GIF
Controls the GIF Decoder Power Down.
GCMQ
Controls the Graphic Command Queue Power Down.
G2D
Controls the 2D Accelerator Power Down.
MP4
Controls the MPEG-4 Power Down.
JPEG
Controls the JPEG Power Down.
REZ
Controls the Resizer Power Down.
ISP
Controls the Image Signal Processor Power Down.
DCT
Controls the DCT Power Down.
IMGDMA
Controls the Image DMA Power Down.
DRZ
Controls the Drop Resizer Power Down.
CONFG +330h Power Down Control 4 Register
15
14
13
BSI
BPI
Controls the BSI Power Down.
Controls the BPI Power Down.
MT
K
Bit
Name
Type
Reset
12
11
10
9
8
7
PDN_CON4
6
5
APC
WO
1
4
AFC
WO
1
3
BPI
WO
1
2
BSI
WO
1
1
0
This control is updated immediately.
This control is updated immediately.
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AFC
APC
Controls the AFC Power Down.
Controls the APC Power Down.
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MT6228 GSM/GPRS Baseband Processor Data Sheet Revision 1.0
This control is updated immediately.
This control is updated immediately.
CONFG+0310h Power Down Set 0 Register
15
14
Name
MDPL
L
Type
W1S
13
12
11
10
9
8
7
6
5
CLK_ CLKS
UPLL TPLL
DIV2
Q
PPP
W1S
W1S
W1S
W1S
W1S
CONFG+0314h Power Down Set 1 Register
15
14
13
12
UART
B2PSI NFI
Name IRDA
3
Type W1S W1S W1S W1S
11
10
15
10
Name GMSK BBRX SCCB AAFE
DIV
GCC
Type
W1S
W1S
W1S
13
W1S
12
W1S
9
9
8
7
6
AUXA
BFE VAFE
FCS
D
W1S W1S W1S W1S
CONFG+031C
Power Down Set 3 Register
h
15
14
13
IMGD
Name DRZ
DCT
MA
Type W1S W1S W1S
12
11
10
9
8
7
15
14
13
W1S
W1S
6
APC
AFC
BPI
BSI
RTC TDMA
W1S
W1S
W1S
W1S
W1S
5
4
3
IPP
TV
W1S
W1S
W1S
W1S
W1S
W1S
W1S
W1S
11
10
9
8
7
W1S
2
PNG
W1S
GPT
3
G2D GCMQ GIF
W1S
0
4
REZ JPEG MP4
12
DMA
PDN_SET2
1
0
W1S
PDN_SET3
2
1
0
RESZ
CRZ
ICE
LB
W1S W1S W1S
CONFG+0334h Power Down Set 4 Register
Bit
Name
Type
USB
5
ISP
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Bit
0
8
7
6
5
4
3
2
1
UART
ALTE
UART
LCD
PWM1 SIM
GPIO KP
TRC PWM2 MSDC
2
R
1
W1S W1S W1S W1S W1S W1S W1S W1S W1S W1S W1S
11
W1S
14
1
PDN_SET1
CONFG+0318h Power Down Set 2 Register
Bit
3
2
WAVE
CHE TABL GCU
E
W1S W1S W1S
Re
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Bit
4
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Bit
PDN_SET0
PDN_SET4
6
5
APC
W1S
4
AFC
W1S
3
BPI
W1S
2
BSI
W1S
1
0
These registers are used to set power down control bit individually. Only bits set to 1 are in effect. Setting the bits to 1
sets the corresponding power down control bits to 1. Otherwise, the bits retain their original value.
EACH BIT Set the Associated Power Down Control Bit to 1.
0 No effect.
1 Set corresponding bit to 1.
CONFG+0320h Power Down Clear 0 Register
Bit
15
14
13
12
11
10
9
8
7
PDN_CLR0
6
5
MDPL
L
CLK_ CLKS
UPLL TPLL
DIV2
Q
PPP
Type
W1C
W1C
W1C
MT
K
Name
W1C
W1C
W1C
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4
3
2
WAVE
CHE TABL GCU
E
W1C W1C W1C
1
0
USB
DMA
W1C W1C
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MT6228 GSM/GPRS Baseband Processor Data Sheet Revision 1.0
CONFG+0324h Power Down Clear 1 Register
Bit
15
14
13
12
UART
Name IRDA
B2PSI NFI
3
Type W1C W1C W1C W1C
11
10
PDN_CLR1
9
8
7
6
5
4
3
2
1
0
UART
ALTE
UART
TRC PWM2 MSDC
LCD
PWM1 SIM
GPIO KP
GPT
1
2
R
W1C W1C W1C W1C W1C W1C W1C W1C W1C W1C W1C W1C
CONFG+0328h Power Down Clear 2 Register
14
11
10
Name GMSK BBRX SCCB AAFE
DIV
GCC
Type W1C
W1C
W1C
W1C
13
W1C
12
W1C
9
8
7
6
AUXA
BFE VAFE
FCS
D
W1C W1C W1C W1C
CONFG+032C
Power Down Clear 3 Register
h
Bit
15
14
13
IMGD
DCT
Name DRZ
MA
Type W1C W1C W1C
12
ISP
W1C
11
10
9
8
15
14
13
12
4
3
2
APC
AFC
BPI
BSI
RTC TDMA
W1C
W1C
W1C
W1C
W1C W1C
7
6
5
4
3
REZ JPEG MP4
G2D GCMQ GIF
PNG
IPP
TV
W1C
W1C
W1C
W1C
W1C
W1C
W1C
CONFG+0338h Power Down Clear 4 Register
Bit
Name
Type
5
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15
Re
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Bit
PDN_CLR2
11
10
9
8
W1C
7
W1C
6
5
APC
W1C
4
AFC
W1C
3
BPI
W1C
1
0
PDN_CLR3
2
1
0
RESZ
ICE
CRZ
LB
W1C W1C W1C
PDN_CLR4
2
BSI
W1C
1
0
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These registers are used to clear power down control bits individually. Only the bits set to 1 are in effect. Setting the
bits to 1 sets the corresponding power down control bits to 0. Otherwise, the bits retain their original value.
MT
K
EACH BIT Clear the Associated Power Down Control Bit.
0 no effect
1 Set corresponding bit to 0
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MT6228 GSM/GPRS Baseband Processor Data Sheet Revision 1.0
12 Analog Front-end & Analog Blocks
12.1
General Description
fo
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To communicate with analog blocks, a common control interface for all analog blocks is implemented. In addition, there are
some dedicated interfaces for data transfer. The common control interface translates APB bus write and read cycle for
specific addresses related to analog front-end control. During writing or reading of any of these control registers, there is a
latency associated with transferring of data to or from the analog front-end. Dedicated data interface of each analog block is
implemented in the corresponding digital block. The Analog Blocks includes the following analog function for complete
GSM/GPRS base-band signal processing:
Base-band RX: For I/Q channels base-band A/D conversion
2.
Base-band TX: For I/Q channels base-band D/A conversion and smoothing filtering, DC level shifting
3.
RF Control: Two DACs for automatic power control (APC) and automatic frequency control (AFC) are included.
Their outputs are provided to external RF power amplifier and VCXO), respectively.
4.
Auxiliary ADC: Providing an ADC for battery and other auxiliary analog function monitoring
5.
Audio mixed-signal blocks: It provides complete analog voice signal processing including microphone amplification,
A/D conversion, D/A conversion, earphone driver, and etc. Besides, dedicated stereo D/A conversion and
amplification for audio signals are included).
6.
Clock Generation: A clock squarer for shaping system clock, and three PLLs that provide clock signals to DSP, MCU,
and USB units are included
7.
XOSC32: It is a 32-KHz crystal oscillator circuit for RTC application Analog Block Descriptions
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1.
12.1.1
BBRX
12.1.1.1
Block Descriptions
The receiver (RX) performs base-band I/Q channels downlink analog-to-digital conversion:
1. Analog input multiplexer: For each channel, a 4-input multiplexer that supports offset and gain calibration is included.
2. A/D converter: Two 14-bit sigma-delta ADCs perform I/Q digitization for further digital signal processing.
12.1.1.2
Functional Specifications
The functional specifications of the base-band downlink receiver are listed in the following table.
Symbol
Parameter
N
Resolution
FC
FS
Min
Typical
Max
Unit
Bit
Clock Rate
26
MHz
Output Sampling Rate
13/12
MSPS
Input Swing
When GAIN=’0’
0.8*AVDD
Vpk
0.4*AVDD
Vpk
MT
K
14
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When GAIN=’1’
OE
Offset Error
+/- 10
FSE
Full Swing Error
+/- 30
I/Q Gain Mismatch
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MT6228 GSM/GPRS Baseband Processor Data Sheet Revision 1.0
mV
mV
0.5
Signal to Noise and Distortion Ratio
- 45kHz sine wave in [0:90] kHz bandwidth
- 145kHz sine wave in [10:190] kHz
bandwidth
dB
dB
ICN
Idle channel noise
- [0:90] kHz bandwidth
- [10:190] kHz bandwidth
DR
Dynamic Range
- [0:90] kHz bandwidth
- [10:190] kHz bandwidth
74
70
dB
dB
RIN
Input Resistance
75
k
DVDD
Digital Power Supply
1.6
1.8
2.0
V
AVDD
Analog Power Supply
2.5
2.8
3.1
V
T
Operating Temperature
-20
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SINAD
-74
-70
dB
dB
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Current Consumption
Power-up
Power-Down
65
65
dB
80
5
5
mA
A
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Table 68 Base-band Downlink Specifications
12.1.2
BBTX
12.1.2.1
Block Descriptions
The transmitter (TX) performs base-band I/Q channels up-link digital-to-analog conversion. Each channel includes:
1. 10-Bits D/A Converter: It converts digital GMSK modulated signals to analog domain. The input to the DAC is sampled
at 4.33-MHz rate with 10-bits resolution.
2. Smoothing Filter: The low-pass filter performs smoothing function for DAC output signals with a 350-kHz 2nd-order
Butterworth frequency response.
12.1.2.2
Function Specifications
The functional specifications of the base-band uplink transmitter are listed in the following table.
Parameter
N
Resolution
10
Bit
FS
Sampling Rate
4.33
MSPS
SINAD
Signal to Noise and Distortion Ratio
57
60
dB
Output Swing
0.18*AVDD
Output CM Voltage
0.34*AVDD
MT
K
Symbol
VOCM
Min
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Typical
0.5*AVDD
Max
Unit
0.89*AVDD
V
0.62*AVDD
V
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Output Capacitance
20
10
K
DNL
Differential Nonlinearity
+/- 0.5
INL
Integral Nonlinearity
+/- 1.0
OE
Offset Error
+/- 15
FSE
Full Swing Error
+/- 30
FCUT
Filter –3dB Cutoff Frequency
300
350
ATT
Filter Attenuation at
100-KHz
270-KHz
4.33-MHz
0.1
2.2
46.4
0.0
1.3
43.7
LSB
mV
mV
400
KHz
0.0
0.8
41.4
dB
dB
dB
+/- 0.5
I/Q Gain Mismatch Correction Range
-1.18
DVDD
Digital Power Supply
1.6
AVDD
Analog Power Supply
2.5
T
Operating Temperature
-20
Current Consumption
Power-up
Power-Down
LSB
Re
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I/Q Gain Mismatch
PF
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Output Resistance
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MT6228 GSM/GPRS Baseband Processor Data Sheet Revision 1.0
dB
+1.18
dB
1.8
2.0
V
2.8
3.1
V
80
5
5
mA
A
Table 69 Base-band Uplink Transmitter Specifications
AFC-DAC
12.1.3.1
Block Descriptions
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12.1.3
As shown in the following figure, together with a 2nd-oder digital sigma-delta modulator, AFC-DAC is designed to produce
a single-ended output signal at AFC pin. AFC pin should be connected to an external 1st-order R-C low pass filter to meet
the 13-bits resolution (DNL) requirement2.
The AFC_BYP pin is the mid-tap of a resistor divider inside the chip to offer the AFC output common-mode level. Nominal
value of this common-mode voltage is half the analog power supply, and typical value of output impedance of AFC_BYP
pin is about 21k . To suppress the noise on common mode level, it is suggested to add an external capacitance between
AFC_BYP pin and ground. The value of the bypass capacitor should be chosen as large as possible but still meet the
settling time requirement set by overall AFC algorithm3.
2
3
MT
K
DNL performance depends on external output RC filter bandwidth: the narrower the bandwidth, the better the DNL. Thus,
there exists a tradeoff between output setting speed and DNL performance
AFC_BYP output impedance and bypass capacitance determine the common-mode settling RC time constant. Insufficient
common-mode settling will affect the INL performance. A typical value of 1nF is suggested.
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MT6228 GSM/GPRS Baseband Processor Data Sheet Revision 1.0
Figure 71 Block diagram of AFC-DAC
Functional Specifications
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12.1.3.2
The following table gives the electrical specification of AFC-DAC.
Symbol
Parameter
Min
N
Resolution
FS
Sampling Rate
DVDD
Digital Power Supply
1.6
AVDD
Analog Power Supply
2.6
T
Operating Temperature
-20
Max
Bit
6500
KHz
1.8
2.0
V
2.8
3.1
V
80
1.2
Output Swing
1
0.75*AVDD
Output Resistor
(in AFC output RC network)
Unit
13
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Current Consumption
Power-up
Power-Down
Typical
mA
A
V
1
K
DNL
Differential Nonlinearity
+1/-1
LSB
INL
Integral Nonlinearity
+4.0/-4.0
LSB
Table 70 Functional specification of AFC-DAC
12.1.4
APC-DAC
12.1.4.1
Block Descriptions
The APC-DAC is a 10-bits DAC with output buffer aimed for automatic power control. Here blow are its analog pin
assignment and functional specification tables.
12.1.4.2
Function Specifications
Parameter
N
Resolution
FS
Min
MT
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Symbol
SINAD
Typical
Max
10
Sampling Rate
Bit
1.0833
Signal to Noise and Distortion Ratio
50
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Unit
MSPS
dB
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(10-KHz Sine with 1.0V Swing & 100-KHz BW)
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MT6228 GSM/GPRS Baseband Processor Data Sheet Revision 1.0
99% Settling Time (Full Swing on Maximal Capacitance)
5
Output Swing
AVDD-0.2
V
Output Capacitance
200
pF
10
K
DNL
Differential Nonlinearity
+/- 0.5
INL
Integral Nonlinearity
+/- 1.0
OE
Offset Error
+/- 10
mV
FSE
Full Swing Error
+/- 10
mV
DVDD
Digital Power Supply
1.6
1.8
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Output Resistance
S
LSB
2.0
V
AVDD
Analog Power Supply
2.5
2.8
3.1
V
T
Operating Temperature
-20
Re
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LSB
Current Consumption
Power-up
Power-Down
80
600
1
A
A
Table 71 APC-DAC Specifications
12.1.5
Auxiliary ADC
12.1.5.1
Block Descriptions
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The auxiliary ADC includes the following functional blocks:
1.
Analog Multiplexer: The analog multiplexer selects signal from one of the seven auxiliary input pins. Real word
message to be monitored, like temperature, should be transferred to the voltage domain.
2.
10 bits A/D Converter: The ADC converts the multiplexed input signal to 10-bit digital data.
12.1.5.2
Function Specifications
The functional specifications of the auxiliary ADC are listed in the following table.
Symbol
Parameter
N
Resolution
FC
Clock Rate
FS
Sampling Rate @ N-Bit
Min
0.1
Typical
Max
10
1.0833
Unit
Bit
5
MHz
5/(N+1)
MSPS
Input Swing
1.0
AVDD
V
VREFP
Positive Reference Voltage
(Defined by AUX_REF pin)
1.0
AVDD
V
CIN
Input Capacitance
Unselected Channel
Selected Channel
MT
K
RIN
50
1.2
Input Resistance
Unselected Channel
Selected Channel
10
1.8
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RS
Resistor String Between AUX_REF pin & ground
Power Up
Power Down
35
10
50
65
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MT6228 GSM/GPRS Baseband Processor Data Sheet Revision 1.0
K
M
Clock Latency
11
DNL
Differential Nonlinearity
+0.5/-0.5
INL
Integral Nonlinearity
+1.0/-1.0
OE
Offset Error
+/- 10
mV
FSE
Full Swing Error
+/- 10
mV
SINAD
Signal to Noise and Distortion Ratio (10-KHz Full
Swing Input & 13-MHz Clock Rate)
50
DVDD
Digital Power Supply
1.6
1.8
AVDD
Analog Power Supply
2.5
2.8
T
Operating Temperature
LSB
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LSB
dB
2.0
V
3.1
V
Re
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Current Consumption
Power-up
Power-Down
1/FC
-20
80
300
1
A
A
Table 72 The Functional specification of Auxiliary ADC
12.1.6
Audio mixed-signal blocks
12.1.6.1
Block Descriptions
MT
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Audio mixed-signal blocks (AMB) integrate complete voice uplink/downlink and audio playback functions. As shown in
the following figure, it includes mainly three parts. The first consists of stereo audio DACs and speaker amplifiers for audio
playback. The second is the voice downlink path, including voice-band DACs and amplifiers, which produces voice signal
to earphone or other auxiliary output device. Amplifiers in these two blocks are equipped with multiplexers to accept
signals from internal audio/voice or external radio sources. The last is the voice uplink path, which is the interface between
microphone (or other auxiliary input device) input and MT6228 DSP. A set of bias voltage is provided for external electret
microphone..
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MT6228 GSM/GPRS Baseband Processor Data Sheet Revision 1.0
Figure 72 Block diagram of audio mixed-signal blocks.
12.1.6.2
Functional Specifications
The following table gives functional specifications of voice-band uplink/downlink blocks.
Parameter
FS
Sampling Rate
4096
KHz
CREF
Decoupling Cap Between AU_VREF_P
And AU_VREF_N
47
NF
DVDD
Digital Power Supply
1.6
1.8
2.0
V
AVDD
Analog Power Supply
2.5
2.8
3.1
V
T
Operating Temperature
-20
IDC
Current Consumption
5
mA
VMIC
Microphone Biasing Voltage
1.9
V
MT
K
Symbol
Min
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Typical
Max
Unit
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IMIC
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MT6228 GSM/GPRS Baseband Processor Data Sheet Revision 1.0
2
Current Draw From Microphone Bias
Pins
mA
Uplink Path4
Signal to Noise and Distortion Ratio
Input Level: -40 dbm0
Input Level: 0 dbm0
29
RIN
Input Impedance (Differential)
13
ICN
XT
dB
dB
69
27
K
Idle Channel Noise
-67
dBm0
Crosstalk Level
-66
dBm0
Downlink Path
20
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SINAD
5
Signal to Noise and Distortion Ratio
Input Level: -40 dBm0
Input Level: 0 dBm0
29
RLOAD
Output Resistor Load (Differential)
28
CLOAD
Output Capacitor Load
ICN
Idle Channel Noise of Transmit Path
XT
Crosstalk Level on Transmit Path
69
Re
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SINAD
dB
dB
200
pF
-67
dBm0
-66
dBm0
Table 73 Functional specifications of analog voice blocks
Functional specifications of the audio blocks are described in the following.
Parameter
Clock Frequency
Fs
Sampling Rate
AVDD
Min
Typical
Fs*128
Max
Unit
KHz
32
44.1
48
KHz
Power Supply
2.6
2.8
3.1
V
T
Operating Temperature
-20
IDC
Current Consumption
5
mA
PSNR
Peak Signal to Noise Ratio
80
dB
DR
Dynamic Range
80
dB
VOUT
Output Swing for 0dBFS Input Level
0.85
Vrms
THD
Total Harmonic Distortion
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Symbol
FCK
80
-40
-60
dB
4
5
MT
K
For uplink-path, not all gain setting of VUPG meets the specification listed on table, especially for the several highest
gains. The maximum gain that meets the specification is to be determined.
For downlink-path, not all gain setting of VDPG meets the specification listed on table, especially for the several lowest
gains. The minimum gain that meets the specification is to be determined.
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RLOAD
Output Resistor Load (Single-Ended)
CLOAD
Output Capacitor Load
200
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MT6228 GSM/GPRS Baseband Processor Data Sheet Revision 1.0
XT
L-R Channel Cross Talk
TBD
dB
Load
22mW at 32
Load
dB
16
pF
fo
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45mW at 16
12.1.7
Clock Squarer
12.1.7.1
Block Descriptions
Re
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Table 74 Functional specifications of the analog audio blocks
For most VCXO, the output clock waveform is sinusoidal with too small amplitude (about several hundred mV) to make
MT6228 digital circuits function well. Clock squarer is designed to convert such a small signal to a rail-to-rail clock signal
with excellent duty-cycle. It provides also a pull-down function when the circuit is powered-down.
12.1.7.2
Function Specifications
The functional specification of clock squarer is shown in Table 75.
Parameter
Fin
Input Clock Frequency
Fout
Output Clock Frequency
Vin
DcycIN
DcycOUT
TR
TF
DVDD
AVDD
T
Min
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Symbol
Typical
Unit
13
MHz
13
MHz
Input Signal Amplitude
500
Input Signal Duty Cycle
50
Output Signal Duty Cycle
Max
DcycIN-5
AVDD
mVpp
%
DcycIN+5
%
Rise Time on Pin CLKSQOUT
5
ns/pF
Fall Time on Pin CLKSQOUT
5
ns/pF
Digital Power Supply
1.3
1.5
1.7
V
Analog Power Supply
2.5
2.8
3.1
V
Operating Temperature
-20
Current Consumption
80
TBD
A
Table 75 The Functional Specification of Clock Squarer
12.1.7.3
Application Notes
MT
K
Here below in the figure is an equivalent circuit of the clock squarer. Please be noted that the clock squarer is designed to
accept a sinusoidal input signal. If the input signal is not sinusoidal, its harmonic distortion should be low enough to not
produce a wrong clock output. As an reference, for a 13MHz sinusoidal signal input with amplitude of 0.2V the harmonic
distortion should be smaller than 0.02V.
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MT6228 GSM/GPRS Baseband Processor Data Sheet Revision 1.0
12.1.8
Phase Locked Loop
12.1.8.1
Block Descriptions
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Figure 73 Equivalent circuit of Clock Squarer.
MT6228 includes three PLLs: DSP PLL, MCU PLL, and USB PLL. DSP PLL and MCU PLL are identical and
programmable to provide either 52MHz or 78 MHz output clock while accepts 13MHz signal. USB PLL is designed to
accept 4MHz input clock signal and provides 48MHz output clock.
12.1.8.2
Function Specifications
The functional specification of DSP/MCU PLL is shown in the following table.
Parameter
Min
Fin
Input Clock Frequency
Fout
Output Clock Frequency
52
Lock-in Time
Output Clock Duty Cycle
Typical
Max
13
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Symbol
40
Output Clock Jitter
Unit
MHz
78
MHz
TBD
50
s
60
%
650
ps
DVDD
Digital Power Supply
1.6
1.8
2.0
V
AVDD
Analog Power Supply
2.5
2.8
3.1
V
T
Operating Temperature
-20
Current Consumption
80
TBD
A
Table 76 The Functional Specification of DSP/MCU PLL
The functional specification of USB PLL is shown below.
Parameter
Fin
Input Clock Frequency
4
MHz
Fout
Output Clock Frequency
48
MHz
MT
K
Symbol
Min
Lock-in Time
Output Clock Duty Cycle
Typical
Max
TBD
40
Output Clock Jitter
50
650
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DVDD
Digital Power Supply
1.3
1.5
1.7
AVDD
Analog Power Supply
2.5
2.8
3.1
T
Operating Temperature
-20
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MT6228 GSM/GPRS Baseband Processor Data Sheet Revision 1.0
V
V
80
Current Consumption
TBD
A
12.1.9
32-KHz Crystal Oscillator
12.1.9.1
Block Descriptions
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Table 77 The Functional Specification of USB PLL
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The low-power 32-KHz crystal oscillator XOSC32 is designed to work with an external piezoelectric 32.768kHz crystal
and a load composed of two functional capacitors, as shown in the following figure.
12.1.9.2
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Figure 74 Block diagram of XOSC32
Functional specifications
The functional specification of XOSC32 is shown in the following table.
Symbol
Parameter
AVDDRTC Analog power supply
Tosc
Dcyc
TR
TF
Min
Typical
Max
Unit
1.08
1.2
1.65
V
5
sec
Start-up time
Duty cycle
50
%
Rise time on XOSCOUT
TBD
ns/pF
Fall time on XOSCOUT
TBD
ns/pF
Current consumption
Leakage current
T
Operating temperature
5
1
-20
A
A
80
Table 78 Functional Specification of XOSC32
MT
K
Here below are a few recommendations for the crystal parameters for use with XOSC32.
Symbol
Parameter
F
Frequency range
Min
Typical
32768
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Max
Unit
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GL
Drive level
f/f
5
Frequency tolerance
+/- 20
Ppm
ESR
Series resistance
50
K
C0
Static capacitance
1.6
pF
12.5
pF
6
fo
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Load capacitance
6
CL
Table 79 Recommended Parameters of the 32kHz crystal
12.2
MCU Register Definitions
12.2.1
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MT6228 GSM/GPRS Baseband Processor Data Sheet Revision 1.0
BBRX
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MCU APB bus registers for BBRX ADC are listed as followings.
MIXED+0300h BBRX ADC Analog-Circuit Control Register
Bit
15
14
13
12
11
10
9
8
Name
QSEL
ISEL
Type
Reset
R/W
00
R/W
00
Set this register for analog circuit configuration controls.
7
6
5
PDNC
RSV
GAIN
HP
R/W R/W R/W
0
0
0
4
3
BBRX_AC_CON
2
1
0
CALBIAS
R/W
00000
6
MT
K
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CALBIAS The register field is for control of biasing current in BBRX mixed-signal module. It is coded in 2’s complement.
That is, its maximum is 15 and minimum is –16. Biasing current in BBRX mixed-signal module has impact on
the performance of A/D conversion. The larger the value of the register field, the larger the biasing current in
BBRX mixed-signal module, and the larger the SNR.
GAIN The register bit is for configuration of gain control of analog inputs in GSM RX mixed-signal module. When the
bit is set to 1, gain control for analog inputs will be turned on and thus GSM RX mixed-signal module can provide
higher resolutions. When the bit is set to 0, gain control for analog inputs will be turned off and thus GSM RX
mixed-signal module can only provide lower resolutions.
0 Gain control for analog inputs in GSM RX mixed-signal module will be turned off.
1 Gain control for analog inputs in GSM RX mixed-signal module will be turned on.
PDNCHP Power down control for charge pumping of GSM RX ADC.
0 Power down charge pumping of GSM RX ADC.
1 Power up charge pumping of GSM RX ADC.
ISEL Loopback configuration selection for I-channel in BBRX mixed-signal module
00 Normal mode
01 Loopback TX analog I
10 Loopback TX analog Q
11 Select the grounded input
QSEL Loopback configuration selection for Q-channel in BBRX mixed-signal module
00 Normal mode
CL is the parallel combination of C1 and C2 in the block diagram.
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MT6228 GSM/GPRS Baseband Processor Data Sheet Revision 1.0
01 Loopback TX analog Q
10 Loopback TX analog I
11 Select the grounded input
12.2.2
BBTX
MCU APB bus registers for BBTX DAC are listed as followings.
15
14
CALR STAR
Name CDON TCAL
E
RC
Type
R
R/W
Reset
0
0
13
12
11
10
9
8
GAIN
CALRCSEL
R/W
000
R/W
000
7
6
5
4
3
TRIMI
R/W
0000
2
1
0
TRIMQ
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Bit
BBTX_AC_CON
0
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MIXED+0400h BBTX DAC Analog-Circuit Control Register 0
R/W
0000
Set this register for analog circuit configuration controls. The procedure to perform calibration processing for smoothing
filter in BBTX mixed-signal module is as follows:
7.
Write 1 to the register bit CARLC in the register TX_CON of Baseband Front End in order to activate clock
required for calibration process. Initiate calibration process.
8.
Write 1 to the register bit STARTCALRC. Start calibration process.
9.
Read the register bit CALRCDONE. If read as 1, then calibration process finished. Otherwise repeat the step.
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10. Write 0 to the register bit STARTCALRC. Stop calibration process.
11. Write 0 to the register bit CARLC in the register TX_CON of Baseband Front End in order to deactivate clock
required for calibration process. Terminate calibration process.
12. The result of calibration process can be read from the register field CALRCOUT of the register
BBTX_AC_CON1. Software can set the value to the register field CALRCSEL for 3-dB cutoff frequency
selection of smoothing filter in DAC of BBTX.
Remember to set the register field CALRCCONT of the register BBTX_AC_CON1 to 0xb before the calibration process. It
only needs to be set once.
MT
K
TRIMQ The register field is used to control gain trimming of Q-channel DAC in BBTX mixed-signal module. It is coded
in 2’s complement, that is, with maximum 15 and minimum –16.
TRIMI The register field is used to control gain trimming of I-channel DAC in BBTX mixed-signal module. It is coded in
2’s complement, that is, with maximum 15 and minimum –16.
CALRCSEL
The register field is for selection of cutoff frequency of smoothing filter in BBTX mixed-signal module.
It is coded in 2’s complement. That is, its maximum is 3 and minimum is –4.
GAIN The register field is used to control gain of DAC in BBTX mixed-signal module. It has impact on both of I- and
Q-channel DAC in BBTX mixed-signal module. It is coded in 2’s complement, that is, with maximum 3 and
minimum –4.
STARTCALRC Whenever 1 is writing to the bit, calibration process for smoothing filter in BBTX mixed-signal module
will be triggered. Once the calibration process is completed, the register bit CARLDONE will be read as 1.
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CALRCDONE The register bit indicates if calibration process for smoothing filter in BBTX mixed-signal module has
finished. When calibration processing finishes, the register bit will be 1. When the register bit STARTCALRC is
set to 0, the register bit becomes 0 again.
BBTX_AC_CON
1
MIXED+0404h BBTX DAC Analog-Circuit Control Register 1
15
14
13
Name
CALRCOUT
Type
Reset
R
-
12
FLOA
T
R/W
0
11
10
9
8
7
6
5
CALRCCNT
CALBIAS
R/W
0000
R/W
00000
Set this register for analog circuit configuration controls.
CMV
4
3
2
1
0
CMV
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Bit
R/W
000
12.2.3
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The register field is used to control common voltage in BBTX mixed-signal module. It is coded in 2’s complement,
that is, with maximum 3 and minimum –4.
CALBIAS The register field is for control of biasing current in BBTX mixed-signal module. It is coded in 2’s
complement. That is, its maximum is 15 and minimum is –16. Biasing current in BBTX mixed-signal module has
impact on performance of D/A conversion. Larger the value of the register field, the larger the biasing current in
BBTX mixed-signal module.
CALRCCNT
Parameter for calibration process of smoothing filter in BBTX mixed-signal module. Default value is
eleven. Note that it is NOT coded in 2’s complement. Therefore the range of its value is from 0 to 15. Remember
to set it to 0xb before BBTX calibration process. It only needs to be set once.
FLOAT The register field is used to have the outputs of DAC in BBTX mixed-signal module float or not.
CALRCOUT
After calibration processing for smoothing filter in BBTX mixed-signal module, a set of 3-bit value is
obtained. It is coded in 2’s complement.
AFC DAC
MCU APB bus registers for AFC DAC are listed as follows.
MIXED+0500h AFC DAC Analog-Circuit Control Register
Bit
15
Name
Type
Reset
14
13
12
11
10
9
8
7
TEST
R/W
0
6
5
PDN_
CHPU
MP
R/W
0
AFC_AC_CON
4
3
2
1
0
CALI
R/W
0
Set this register for analog circuit configuration controls. Please refer to analog functional specification for more details.
TEST test control
PDN_CHPUMP charge pump power down
CALI biasing current control
APC DAC
MT
K
12.2.4
MCU APB bus registers for APC DAC are listed as followings.
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MIXED+0600h APC DAC Analog-Circuit Control Register
Bit
Name
Type
Reset
15
14
13
12
11
10
9
8
7
6
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MT6228 GSM/GPRS Baseband Processor Data Sheet Revision 1.0
APC_AC_CON
5
BYP
R/W
0
4
3
2
CALI
R/W
0
1
0
Set this register for analog circuit configuration controls. Please refer to analog functional specification for more details.
bypass output buffer
biasing current control
12.2.5
fo
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BYP
CALI
Auxiliary ADC
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MCU APB bus registers for AUX ADC are listed as followings.
MIXED+0700h Auxiliary ADC Analog-Circuit Control Register
Bit
Name
Type
Reset
15
14
13
12
11
10
9
8
7
6
5
4
3
AUX_AC_CON
2
CALI
R/W
0
1
0
Set this register for analog circuit configuration controls. Please refer to analog functional specification for more details.
CALI
biasing current control
12.2.6
Voice Front-end
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MCU APB bus registers for speech are listed as followings.
MIXED+0100h AFE Voice Analog Gain Control Register
Bit
Name
Type
Reset
15
14
13
12
11
10
VUPG
R/W
0000
9
8
7
AFE_VAG_CON
6
5
VDPG0
R/W
0000
4
3
2
1
VDPG1
R/W
0000
0
Set this register for analog PGA gains. VUPG is set for microphone input volume control. And VDPG0 and VDPG1 are set
for two output volume controls
VUPG voice-band up-link PGA gain control bits
VCFG [2] =’0’
VCFG [2] =’1’
Gain
VUPG [4:0]
Gain
11111
42 dB
XX111
-21dB
11110
40 dB
XX110
-18dB
11101
38 dB
XX101
-15dB
11100
36 dB
XX100
-12dB
11011
34 dB
XX011
-9dB
11010
32 dB
XX010
-6dB
11001
30 dB
XX001
-3dB
MT
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VUPG [4:0]
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26 dB
10110
24 dB
10101
22 dB
10100
20 dB
10011
18 dB
10010
16 dB
10001
14 dB
10000
12 dB
01111
10 dB
01110
8 dB
01101
6 dB
01100
4 dB
01011
2 dB
01010
0 dB
01001
-2 dB
01000
-4 dB
00111
-6 dB
00110
-8 dB
00101
-10 dB
00100
-12 dB
00011
-14 dB
00010
-16 dB
00001
-18 dB
00000
-20 dB
0dB
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10111
XX000
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28 dB
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11000
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MT6228 GSM/GPRS Baseband Processor Data Sheet Revision 1.0
Table 80 Uplink PGA gain setting (VUPG [4:0])
VDPG0 voice-band down-link PGA0 gain control bits
VDPG1 voice-band down-link PGA1 gain control bits
Gain
1111
8dB
1110
6dB
1101
4dB
1100
2dB
1011
0dB
1010
-2dB
1001
-4dB
1000
-6dB
0111
-8dB
MT
K
VDPG0 [3:0] / VDPG1 [3:0]
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-10dB
0101
-12dB
0100
-14dB
0011
-16dB
0010
-18dB
0001
-20dB
0000
-22dB
Table 81 Downlink power amplifier gain setting
MIXED+0104h AFE Voice Analog-Circuit Control Register 0
15
14
13
12
11
10
9
8
VCFG
R/W
0000
Set this register for analog circuit configuration controls.
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VCFG[3] microphone biasing control
0 differential biasing
1 single-ended biasing
VCFG[2] gain mode control
0 amplification
1 attenuation
VCFG[1] coupling control
0 AC
1 DC
VCFG[0] input select control
0 input 0
1 input 1
VDSEND[1]single-ended configuration control for out1
VDSEND[0]single-ended configuration control for out0
VCALI biasing current control, in 2’s complement format
7
6
5
VDSEND
R/W
00
AFE_VAC_CON0
4
3
MIXED+0108h AFE Voice Analog-Circuit Control Register 1
Bit
15
14
Name
13
12
11
10
VBG_CTRL
Type
Reset
R/W
000
2
VCALI
R/W
00000
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Bit
Name
Type
Reset
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0110
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MT6228 GSM/GPRS Baseband Processor Data Sheet Revision 1.0
9
8
7
6
5
VPDN
VFLO VRSD VRES VBUF
_CHP
AT
ON
SW 0SEL
UMP
R/W R/W R/W R/W R/W
0
0
0
0
0
1
0
AFE_VAC_CON1
4
3
VBUF1SEL
R/W
000
2
1
0
VADC VDAC
INMO INMO
DE
DE
R/W R/W
0
0
MT
K
Set this register for analog circuit configuration controls. There are several loop back modes and test modes implemented
for test purposes. Suggested value is 0084h.
VBG_CTRL
voice-band band-gap control
VPDN_CHPUMP
voice-band charge pump power down
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MT6228 GSM/GPRS Baseband Processor Data Sheet Revision 1.0
0: power down (normal operating mode)
1: charge pump on (for fab. process)
VFLOAT voice-band output driver float
0: normal operating mode
1: float mode
VRSDON voice-band redundant signed digit function on
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0: 1-bit 2-level mode
1: 2-bit 3-level mode
VRESSW
voice-band output buffer 1 output DC voltage control.
VBUF0SEL voice buffer 0 input selection (reserved.)
VBUF1SEL voice buffer 1 input selection
001: voice DAC output
010: external FM radio input
100: audio DAC output
OTHERS: reserved.
VADCINMODE Voice-band ADC output mode.
0: normal operating mode
1: the ADC input from the DAC output
VDACINMODE Voice-band DAC input mode.
0: normal operating mode
1: the DAC input from the ADC output
AFE_VAPDN_C
ON
Bit
15
14
Name
Type
Reset
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MIXED+010Ch AFE Voice Analog Power Down Control Register
13
12
11
10
9
8
7
6
5
4
3
2
1
0
VPDN VPDN
VPDN VPDN VPDN VPDN
_OUT _OUT
_BIAS _LNA _ADC _DAC
1
0
R/W R/W R/W R/W R/W R/W
0
0
0
0
0
0
Set this register to power up analog blocks. 0: power down, 1: power up.
VPDN_BIAS bias block
VPDN_LNAlow noise amplifier block
VPDN_ADC
ADC block
VPDN_DAC
DAC block
VPDN_OUT1 OUT1 buffer block
VPDN_OUT0 OUT0 buffer block
Bit
MT
K
MIXED+0110h AFE Voice AGC Control Register
Name
Type
Reset
15
14
AFE_VAGC_CO
N
13
12
11
10
9
8
7
6
5
4
3
2
1
0
AGCT RELNOIDUR RELNOILEV
ATTC HYST AGCE
FRELCKSEL SRELCKSEL ATTTHDCAL
EST
SEL
SEL
KSEL EREN N
R/W
R/W
R/W
R/W
R/W
R/W
R/W R/W R/W
0
00
00
00
00
00
0
0
0
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MT6228 GSM/GPRS Baseband Processor Data Sheet Revision 1.0
Set this register for analog circuit configuration controls. There are several loop back modes and test modes implemented
for test purposes. Suggested value is 0dcfh.
AGCEN
AGC hysteresis function enable
ATTCKSEL
attack clock selection
12.2.7
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0: 16 KHz
1: 32 KHz
ATTTHDCAL attack threshold calibration
SRELCKSEL release slow clock selection
00: 1000/512 Hz
01: 1000/256 Hz
10: 1000/128 Hz
11: 1000/64 Hz
FRELCKSEL release fast clock selection
00: 1000/64 Hz
01: 1000/32 Hz
10: 1000/16 Hz
11: 1000/8 Hz
RELNOILEVSEL
release noise level selection
00: -8 dB
01: -14 dB
10: -20 dB
11: -26 dB
RELNOIDURSEL
release noise duration selection
00: 64 ms
01: 32 ms
10: 16 ms
11: 8 ms, 32768/4096
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HYSTEREN
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AGC function enable
Audio Front-end
MCU APB bus registers for audio are listed as followings.
MIXED+0200h AFE Audio Analog Gain Control Register
Bit
15
Name
13
12
11
10
9
8
AMUT AMUT
ER
EL
R/W R/W
0
0
7
6
5
4
3
2
1
APGR
APGL
R/W
0000
R/W
0000
0
MT
K
Type
Reset
14
AFE_AAG_CON
Set this register for analog PGA gains.
AMUTER
AMUTEL
audio PGA L-channel mute control
audio PGA R-channel mute control
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APGR
APGL
audio PGA R-channel gain control
audio PGA L-channel gain control
MIXED+0204h AFE Audio Analog-Circuit Control Register
15
14
13
12
Name
Type
Reset
11
ARCO
N
R/W
0
10
9
8
7
6
AFE_AAC_CON
5
4
3
2
ABUFSELR
ABUFSELL
ACALI
R/W
000
R/W
000
R/W
00000
1
0
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Bit
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MT6228 GSM/GPRS Baseband Processor Data Sheet Revision 1.0
Set this register for analog circuit configuration controls.
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ARCON
audio external RC control
ABUFSELR
audio buffer R-channel input selection
000: audio DAC R/L-channel output; stereo to mono
001: audio DAC R-channel output
010: voice DAC output
100: external FM R/L-channel radio output, stereo to mono
101: external FM R-channel radio output
OTHERS: reserved.
ABUFSELL audio buffer L-channel input selection
000: audio DAC R/L-channel output; stereo to mono
001: audio DAC L-channel output
010: voice DAC output
100: external FM R/L-channel radio output, stereo to mono
101: external FM L-channel radio output
OTHERS: reserved.
ACALI
audio bias current control, in 2’s complement format
AFE_AAPDN_C
ON
MIXED+0208h AFE Audio Analog Power Down Control Register
Bit
15
Name
Type
Reset
14
13
12
11
10
9
8
7
ACNR
R/W
000000
6
5
4
3
2
1
0
APDN APDN APDN APDN
APDN
_DAC _DAC _OUT _OUT
_BIAS
R
L
R
L
R/W R/W R/W R/W R/W
0
0
0
0
0
Set this register to power up analog blocks. 0: power down, 1: power up. Suggested value is 00ffh.
MT
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ACNR audio click noise reduction
APDN_BIAS
BIAS block
APDN_DACR
R-channel DAC block
APDN_DACL
L-channel DAC block
APDN_OUTR
R-channel OUT buffer block
APDN_OUTL
L-channel OUT buffer block
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12.2.8
Reserved
Some registers are reserved for further extensions.
RES0_AC_CON
0
MIXED+0800h Reserved 0 Analog Circuit Control Register 0
14
13
12
11
10
9
8
7
6
5
4
3
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
MIXED+0804h Reserved 0 Analog Circuit Control Register 1
14
13
12
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
13
12
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
14
R/W
0
14
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
RES1_AC_CON
1
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
RES2_AC_CON
0
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
13
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14
R/W
0
RES1_AC_CON
0
7
RES2_AC_CON
1
MIXED+0A04h Reserved 2 Analog Circuit Control Register 1
Bit
15
Name
Type R/W
Reset
0
R/W
0
4
MIXED+0A00h Reserved 2 Analog Circuit Control Register 0
Bit
15
Name
Type R/W
0
Reset
R/W
0
5
MIXED+0904h Reserved 1 Analog Circuit Control Register 1
Bit
15
Name
Type R/W
Reset
0
R/W
0
6
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14
0
7
MIXED+0900h Reserved 1 Analog Circuit Control Register 0
Bit
15
Name
Type R/W
Reset
0
1
RES0_AC_CON
1
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Bit
15
Name
Type R/W
Reset
0
2
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Bit
15
Name
Type R/W
Reset
0
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R/W
0
12
11
10
9
8
7
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
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RES3_AC_CON
0
MIXED+0B00h Reserved 3 Analog Circuit Control Register 0
14
13
12
11
10
9
8
7
6
5
4
3
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
MIXED+0B04h Reserved 3 Analog Circuit Control Register 1
10
9
8
7
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
14
13
12
11
10
9
8
RES4_AC_CON
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
13
12
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
14
R/W
0
14
R/W
0
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
RES5_AC_CON0
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
RES5_AC_CON1
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
13
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14
R/W
0
RES4_AC_CON1
7
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14
MIXED+0E00h Reserved 6 Analog Circuit Control Register 0
Bit
15
Name
Type R/W
Reset
0
R/W
0
11
MIXED+0D04h Reserved 5 Analog Circuit Control Register 1
Bit
15
Name
Type R/W
Reset
0
R/W
0
12
MIXED+0D00h Reserved 5 Analog Circuit Control Register 0
Bit
15
Name
Type R/W
Reset
0
R/W
0
13
MIXED+0C04h Reserved 4 Analog Circuit Control Register 1
Bit
15
Name
Type R/W
Reset
0
0
14
MIXED+0C00h Reserved 4 Analog Circuit Control Register 0
Bit
15
Name
Type R/W
Reset
0
1
RES3_AC_CON
1
Re
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Bit
15
Name
Type R/W
Reset
0
2
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Bit
15
Name
Type R/W
Reset
0
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R/W
0
RES6_AC_CON0
12
11
10
9
8
7
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
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MIXED+0E04h Reserved 6 Analog Circuit Control Register 1
Bit
15
Name
Type R/W
Reset
0
RES6_AC_CON1
14
13
12
11
10
9
8
7
6
5
4
3
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
MIXED+0F00h Reserved 7 Analog Circuit Control Register 0
1
0
R/W
0
R/W
0
R/W
0
RES7_AC_CON0
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Re
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MIXED+0F04h Reserved 7 Analog Circuit Control Register 1
Bit
15
Name
Type R/W
Reset
0
2
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Bit
15
Name
Type R/W
Reset
0
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MT6228 GSM/GPRS Baseband Processor Data Sheet Revision 1.0
14
13
12
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
12.3
Programming Guide
12.3.1
BBRX Register Setup
RES7_AC_CON1
7
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
The register used to control analog base-band receiver is BBRX_AC_CON.
Programmable Biasing Current
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12.3.1.1
To maximize the yield in modern digital process, the receiver features providing 5-bit 32-level programmable current to
bias internal analog blocks. The 5-bits registers CALBIAS [4:0] is coded with 2’s complement format.
12.3.1.2
Offset / Gain Calibration
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The base-band downlink receiver (RX), together with the base-band uplink transmitter (TX) introduced in the next section,
provides necessary analog hardware for DSP algorithm to correct the mismatch and offset error. The connection for
measurement of both RX/TX mismatch and gain error is shown in Figure 75, and the corresponding calibration procedure
is described below.
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Figure 75 Base-band A/D and D/A Offset and Gain Calibration
12.3.1.3
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MT6228 GSM/GPRS Baseband Processor Data Sheet Revision 1.0
Downlink RX Offset Error Calibration
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The RX offset measurement is achieved by selecting grounded input to A/D converter (set ISEL [1:0] =’11’ and QSEL [1:0]
=’11’ to select channel 3 of the analog input multiplexer, as shown in Figure 76. The output of the ADC is sent to DSP for
further offset cancellation. The offset cancellation accuracy depends on the number of samples being converted. That is,
more accurate measurement can be obtained by collecting more samples followed by averaging algorithm.
Figure 76 Downlink ADC Offset Error Measurement
12.3.1.4
Downlink RX and Uplink TX Gain Error Calibration
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To measure the gain mismatch error, both I/Q uplink TXs should be programmed to produce full-scale pure sinusoidal
waves output. Such signals are then fed to downlink RX for A/D conversion, in the following two steps.
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A. The uplink I-channel output are connected to the downlink I-channel input, and the uplink Q-channel output are
connected to the downlink Q-channel input. This can be achieved by setting ISEL [1:0] =’01’ and QSEL [1:0] =’01’
(shown in Figure 77 (A))..
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B. The uplink I-channel output are then connected to the downlink Q-channel input, and the uplink Q-channel output are
connected to the downlink I-channel input. This can be achieved by setting ISEL [1:0] =’10’ and QSEL [1:0] =’10’
(shown in Figure 77 (B)).
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Figure 77 Downlink RX and Up-link TX Gain Mismatch Measurement (A) I/Q TX connect to I/Q RX (B) I/Q TX connect
to Q/I RX
Once above successive procedures are completed, RX/TX gain mismatch could be easily obtained because the amplitude
mismatch on RX digitized result in step A and B is the sum and difference of RX and TX gain mismatch, respectively.
The gain error of the downlink RX can be corrected in the DSP section and the uplink TX gain error can be corrected by the
gain trimming facility that TX block provide.
12.3.1.5
Uplink TX Offset Error Calibration
Once the offset of the downlink RX is known and corrected, the offset of the uplink TX alone could be easily estimated.
The offset error of TX should be corrected in the digital domain by means of the programmable feature of the digital
GMSK modulator.
Finally, it is important that above three calibration procedures should be exercised in order, that is, correct the RX offset
first, then RX/TX gain mismatch, and finally TX offset. This is owing to that analog gain calibration in TX will affect its
offset, while the digital offset correction has no effect on gain.
12.3.2
BBTX Register Setup
MT
K
The register used to control analog base-band transmitter is BBTX_AC_CON0 and BBTX_AC_CON1.
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12.3.2.1
Output Gain Control
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The output swing of the uplink transmitter is controlled by register GAIN [2:0] coded in 2’s complement with about 2dB
step. When TRIMI [3:0] / TRIMQ [3:0] = 0 the swing is listed in Table 82, defined to be the difference between positive
and negative output signal.
Output Swing
For AVDD=2.8 (V)
+3 (011)
AVDD*0.900 (+6.02 dB)
2.52
+2 (010)
AVDD*0.720 (+4.08 dB)
2.02
+1 (001)
AVDD*0.576 (+2.14 dB)
1.61
+0 (000)
AVDD*0.450 (+0.00 dB)
1.26
-1 (111)
AVDD*0.360 (-1.94 dB)
1
-2 (110)
AVDD*0.288 (-3.88 dB)
0.81
-3 (101)
AVDD*0.225 (-6.02 dB)
0.63
-4 (100)
AVDD*0.180 (-7.95 dB)
0.5
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GAIN [2:0]
Table 82 Output Swing Control Table
12.3.2.2
Output Gain Trimming
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I/Q channels can also be trimmed separately to compensate gain mismatch in the base-band transmitter or the whole
transmission path including RF module. The gain trimming is adjusted in 16 steps spread from –1.18dB to +1.18dB (Table
83), compared to the full-scale range set by GAIN [2:0].
TRIMI [3:0] / TRIMQ [3:0]
Gain Step (dB)
+7 (0111)
1.18
+6 (0110)
1.00
+5 (0101)
0.83
+4 (0100)
0.66
+3 (0011)
0.49
+2 (0010)
0.32
+1 (0001)
0.16
+0 (0000)
0.00
-1 (1111)
-0.16
-2 (1110)
-0.31
-3 (1101)
-0.46
-4 (1100)
-0.61
-5 (1011)
-0.75
-6 (1010)
-0.90
-7 (1001)
-1.04
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-1.18
Table 83 Gain Trimming Control Table
12.3.2.3
Output Common-Mode Voltage
Common-Mode Voltage
+3 (011)
AVDD*0.62
+2 (010)
AVDD*0.58
+1 (001)
AVDD*0.54
+0 (000)
AVDD*0.50
-1 (111)
AVDD*0.46
-2 (110)
-3 (101)
-4 (100)
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CMV [2:0]
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The output common-mode voltage is controlled by CMV [2:0] with about 0.08*AVDD step, as listed in the following table.
AVDD*0.42
AVDD*0.38
AVDD*0.34
Table 84 Output Common-Mode Voltage Control Table
12.3.2.4
Programmable Biasing Current
The transmitter features providing 5-bit 32-level programmable current to bias internal analog blocks. The 5-bits registers
CALBIAS [4:0] is coded with 2’s complement format.
Smoothing Filter Characteristic
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12.3.2.5
The 2nd –order Butterworth smoothing filter is used to suppress the image at DAC output: it provides more than 40dB
attenuation at the 4.44MHz sampling frequency. To tackle with the digital process component variation, programmable
cutoff frequency control bits CALRCSEL [2:0] are included. User can directly change the filter cut-off frequency by
different CALRCSEL value (coded with 2’s complement format and with a default value 0). In addition, an internal
calibration process is provided, by setting START CALRC to high and CALRCCNT to an appropriate value (default is 11).
After the calibration process, the filter cut-off frequency is calibrated to 350kHz +/- 50 kHz and a new CALRCOUT value
is stored in the register. During the calibration process, the output of the cell is high-impedance.
12.3.3
AFC-DAC Register Setup
The register used to control the APC DAC is AFC_AC_CON, which providing 5-bit 32-level programmable current to bias
internal analog blocks. The 5-bits registers CALI [4:0] is coded with 2’s complement format.
12.3.4
APC-DAC Register Setup
MT
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The register used to control the APC DAC is AFC_AC_CON, which providing 5-bit 32-level programmable current to bias
internal analog blocks. The 5-bits registers CALI [4:0] is coded with 2’s complement format.
12.3.5
Auxiliary A/D Conversion Register Setup
The register used to control the Aux-ADC is AUX_AC_CON. For this register, which providing 5-bit 32-level
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programmable current to bias internal analog blocks. The 5-bits registers CALI [4:0] is coded with 2’s complement format.
12.3.6
Voice-band Blocks Register Setup
The registers used to control AMB are AFE_VAG_CON, AFE_VAC_CON0, AFE_VAC_CON1, and AFE_VAPDN_CON.
For these registers, please refer to chapter “Analog Chip Interface”
Reference Circuit
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12.3.6.1
The voice-band blocks include internal bias circuits, a differential bandgap voltage reference circuit and a differential
microphone bias circuit. Internal bias current could be calibrated by varying VCALI[4:0] (coded with 2’s complement
format).
Symbol
Parameter
Min
V0dBm0,UP 0dBm0 Voltage for Uplink Path, Applied
Differentially Between Positive and
Negative Microphone Input Pins
0dBm0 voltage for Downlink Path,
Appeared Differentially Between Positive
and Negative Power Amplifier Output Pins
Typical
Max
Unit
0.2V
V-rms
0.6V
V-rms
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V0dBm0,Dn
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The differential bandgap circuit generates a low temperature dependent voltage for internal use. For proper operation, there
should be an external 47nF capacitor connected between differential output pins AU_VREFP and AU_VREFN. The
bandgap voltage (~1.24V7, typical) also defines the dBm0 reference level through out the audio mixed-signal blocks. The
following table illustrates typical 0dBm0 voltage when uplink/downlink programmable gains are unity. For other gain
setting, 0dBm0 reference level should be scaled accordingly.
Table 85 0dBm0 reference level for unity uplink/downlink gain
The microphone bias circuit generates a differential output voltage between AU_MICBIAS_P and AU_MICBIAS_N for
external electret type microphone. Typical output voltage is 1.9 V. In singled-ended mode, by set VCFG[3] =1,
AU_MICBIAS_N is pull down while output voltage is present on AU_MICBIAS_P, respect to ground. The max current
supplied by microphone bias circuit is 2mA.
12.3.6.2
Uplink Path
Uplink path of voice-band blocks includes an uplink programmable gain amplifier and a sigma-delta modulator.
12.3.6.2.1
Uplink Programmable Gain Amplifier
Input to the PGA is a multiplexer controlled by VCFG [3:0], as described in the following table. In normal operation, both
input AC and DC coupling are feasible for attenuation the input signal (gain <= 0dB). However, only AC coupling is
suggested if amplification of input signal is desired (gain>=0dB).
7
Function
Descriptions
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Control
The bandgap voltage could be calibrated by adjusting control signal VBG_CTRL[1:0]. Its default value is [00].
VBG_CTRL not only adjust the bandgap voltage but also vary its temperature dependence. Optimal value of VBG_CTRL
is to be determined.
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Signal
VCFG [0]
Input Selector
VCFG [1]
Coupling Mode 0: AC Coupling
1: DC Coupling
VCFG [2]
Gain Mode
0: Amplification Mode (gain >= 0 dB)
1: Attenuation Mode (gain <= 0dB)
VCFG [3]
Microphone
Biasing
0: Differential Biasing (Take Bias Voltage Between AU_MICBIAS_P
and AU_MICBIAS_N)
1: Signal-Ended Biasing (Take Bias Voltage From AU_MICBIAS_P
Respected to Ground. AU_MICBIAS_N Is Connected to Ground)
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0: Input 0 (From AU_VIN0_P / AU_VIN0_N) Is Selected
1: Input 1 (From AU_VIN1_P / AU_VIN1_N) Is Selected
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Table 86 Uplink PGA input configuration setting
The PGA itself provides programmable gain (through VUPG [3:0]) with step of 3dB, as listed in the following table.
VCFG [2] =’0’
VCFG [2] =’1’
Gain
VUPG [3:0]
Gain
1111
NA
X111
-21dB
1110
42dB
X110
-18dB
1101
39dB
X101
-15dB
1100
36dB
X100
-12dB
1011
33dB
X011
-9dB
1010
30dB
X010
-6dB
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VUPG [3:0]
1001
27dB
X001
-3dB
1000
24dB
X000
0dB
0111
21dB
0110
18dB
0101
15dB
0100
12dB
0011
9dB
0010
6dB
0001
3dB
0000
0dB
Table 87 Uplink PGA gain setting (VUPG [3:0])
The following table illustrates typically the 0dBm0 voltage applied at the microphone inputs, differentially, for several gain
settings.
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VCFG [2] =’0’
VCFG [2] =’1’
VUPG [3:0]
0dBm0 (V-rms)
VUPG [3:0]
0dBm0 (V-rms)
1100
3.17mV
X110
1.59V
1000
12.6mV
X100
0.8V
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0100
50.2mV
X010
0.4V
0000
0.2V
X000
0.2V
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Table 88 0dBm0 voltage at microphone input pins
12.3.6.2.2
Sigma-Delta Modulator
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Analog-to-digital conversion in uplink path is made with a second-order sigma-delta modulator (SDM) whose sampling
rate is 4096kHz. Output signals are coded in either one-bit or RSD format, optionally controlled by VRSDON register.
For test purpose, one can set VADCINMODE to HI to form a look-back path from downlink DAC output to SDM input.
The default value of VADCINMODE is zero.
12.3.6.3
Downlink Path
12.3.6.3.1
Re
lea
se
Downlink path of voice-band blocks includes a digital to analog converter (DAC) and two programmable output power
amplifiers.
Digital to Analog Converter
The DAC converts input bit-stream to analog signal by sampling rate of 4096kHz. . Besides, it performs a 2nd-order 40kHz
butterworth filtering. The DAC receives input signals from MT6228 DSP by set VDACINMODE = 0. It can also take
inputs from SDM output by setting VDACINMODE = 1.
12.3.6.3.2
Downlink Programmable Power Amplifier
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Voice-band analog blocks include two identical output power amplifiers with programmable gain. Amplifier 0 and amplifier
1 can be configured to either differential or single-ended mode by adjusting VDSEND [0] and VDSEND [1], respectively.
In single-ended mode, when VDSEND[0] =1, output signal is present at AU_VOUT0_P pin respect to ground. Same as
VDSEND[1] for AU_VOUT1_P pin.
For the amplifier itself, programmable gain setting is described in the following table.
Gain
1111
8dB
1110
6dB
1101
4dB
1100
2dB
1011
0dB
1010
-2dB
1001
-4dB
1000
-6dB
0111
-8dB
0110
-10dB
MT
K
VDPG0 [3:0] / VDPG1 [3:0]
0101
-12dB
0100
-14dB
0011
-16dB
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0010
-18dB
0001
-20dB
0000
-22dB
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MT6228 GSM/GPRS Baseband Processor Data Sheet Revision 1.0
Table 89 Downlink power amplifier gain setting
fo
r
Control signal VFLOAT, when set to ‘HI’, is used to make output nodes totally floating in power down mode. If VFLOAT
is set to ‘LOW” in power down mode, there will be a resistor of 50k ohm (typical) between AU_VOUT0_P and
AU_VOUT0_N, as well as between AU_VOUT0_P and AU_VOUT0_N.
VDPG
Output Signal
Level (V-rms)
0010
0.11
0110
0.27
1010
0.69
1110
1.74
Re
lea
se
The amplifiers deliver signal power to drive external earphone. The minimum resistive load is 28 ohm and the upper limit
of the output current is 50mA. On the basis that 3.14dBm0 digital input signal into downlink path produces DAC output
differential voltage of 0.87V-rms (typical), the following table illustrates the power amplifier output signal level (in V-rms)
and signal power for an external 32 ohm resistive load.
Output Signal Power
(mW / dBm)
0.37/-4.3
2.28/3.6
14.8/11.7
94.6/19.8
Table 90 Output signal level/power for 3.14dBm0 input. External resistive load = 32 ohm
The following table illustrates the output signal level and power for different resistive load when VDPG =1110.
Output Signal
Level (V-rms)
Output Signal Power
(mW / dBm)
30
1.74
101/20
100
1.74
30.3/14.8
600
1.74
5/7
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RLOAD
Table 91 Output signal level/power for 3.14dBm0 input, VDPG =1110
12.3.6.4
Power Down Control
Each block inside audio mixed-signal blocks features dedicated power-down control, as illustrated in the following table.
Control
Signal
Descriptions
VPDN_BIAS Power Down Reference Circuits (Active Low)
Power Down Uplink PGA (Active Low)
VPDN_ADC
Power Down Uplink SDM (Active Low)
MT
K
VPDN_LNA
VPDN_DAC
Power Down DAC (Active Low)
VPDN_OUT0 Power Down Downlink Power Amp 0 (Active Low)
VPDN_OUT1 Power Down Downlink Power Amp 1 (Active Low)
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Table 92 Voice-band blocks power down control
12.3.7
Audio-band Blocks Register Setup
The registers used to control audio blocks are AFE_AAG_CON, AFE_AAC_CON, and AFE_AAPDN_CON. For these
registers, please refer to chapter “Analog Chip Interface”
12.3.7.1
Output Gain Control
Re
lea
se
fo
r
Audio blocks include stereo audio DACs and programmable output power amplifiers. The DACs convert input bit-stream
to analog signal by sampling rate of Fs*128 where Fs could be 32kHz, 44.1kHz, or 48kHz. Besides, it performs a 2nd-order
butterworth filtering. The two identical output power amplifiers with programmable gain are designed to driving external
AC-coupled single-end speaker. The minimum resistor load is 16 ohm and the maximum driving current is 50mA. The
programmable gain setting, controlled by APGR[] and APGL[], is the same as that of the voice-band amplifiers.
Unlike voice signals, 0dBFS defines the full-scale audio signals amplitude. Based on bandgap reference voltage again, the
following table illustrates the power amplifier output signal level (in V-rms) and signal power for an external 16 ohm
resistive load.
APGR[]/
APGL[]
Output Signal
Level (V-rms)
0010
0.055
0110
0.135
1010
0.345
1110
0.87
Output Signal Power
(mW / dBm)
0.19/-7.2
1.14/0.6
7.44/8.7
47.3/16.7
12.3.7.2
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Table 93 Output signal level/power for 0dBFS input. External resistive load = 16 ohm
Mute Function and Power Down Control
By setting AMUTER (AMUTEL) to high, right (Left) channel output will be muted.
Each block inside audio mixed-signal blocks features dedicated power-down control, as illustrated in the following table.
Control Signal Descriptions
APDN_BIAS
Power Down Reference Circuits (Active Low)
APDN_DACL Power Down L-Channel DAC (Active Low)
APDN_DACR Power Down R-Channel DAC (Active Low)
APDN_OUTL Power Down L-Channel Audio Amplifier (Active Low)
APDN_OUTR Power Down R-Channel Audio Amplifier (Active Low)
Table 94 Audio-band blocks power down control
Multiplexers for Audio and Voice Amplifiers
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12.3.8
The audio/voice amplifiers feature accepting signals from various signal sources including AU_FMINR/AU_FMINL pins,
that aimed to receive stereo AM/FM signal from external radio chip:
1) Voice-band amplifier 0 accepts signals from voice DAC output only.
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MT6228 GSM/GPRS Baseband Processor Data Sheet Revision 1.0
2) Voice-band amplifier 1 accepts signal from either voice DAC, audio DAC, or AM/FM radio input pins (controlled
by register VBUF1SEL[] ). For the last two cases, left and right channel signals will be summed together to form a
mono signal first.
3) Audio left/right channel amplifiers receive signals from either voice DAC, audio DAC, or AM/FM radio input pins
(controlled by registers ABUFSELL[] and ABUFSELR[] ), too. Left and right channel amplifiers will produce
identical output waveforms when receiving mono signals from voice DAC.
Clock Squarer Register Setup
fo
r
12.3.9
The register used to control clock squarer is CLK_CON. For this register, please refer to chapter “Clocks”
CLKSQ_PLD is used to bypass the clock squarer.
Re
lea
se
12.3.10 Phase-Locked Loop Register Setup
For registers control the PLL, please refer to chapter “Clocks” and “Software Power Down Control”
12.3.10.1 Frequency Setup
The DSP/MCU PLL itself could be programmable to output either 52MHz or 78MHz clocks. Accompanied with additional
digital dividers, 13/26/39/52/65/78 MHz clock outputs are supported.
12.3.10.2 Programmable Biasing Current
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The PLLs feature providing 5-bit 32-level programmable current to bias internal analog blocks. The 5-bits registers CALI
[4:0] is coded with 2’s complement format.
12.3.11 32-khz Crystal Oscillator Register Setup
For registers that control the oscillator, please refer to chapter “Real Time Clock” and “Software Power Down Control”.
XOSCCALI[4:0] is the calibration control registers of the bias current, and is coded with 2’s complement format.
CL is the parallel combination of C1 and C2 in the block diagram.
MT
K
1
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MT6228 GSM/GPRS Baseband Processor Data Sheet Revision 1.0
13 Digital Pin Electrical Characteristics
Based on I/O power supply (VDD33) = 3.3 V
Vil (max) = 0.8 V
Vih (min) = 2.0 V
Dir
Driving Iol &
Ioh Typ (mA)
Vol at Iol Max Voh at Ioh Min PU/PD Resistor
(V)
(V)
Min
Typ
JTAG Port
BPI_BUS0
BPI_BUS1
BPI_BUS2
BPI_BUS3
BPI_BUS4
BPI_BUS5
BPI_BUS6
BPI_BUS7
BPI_BUS8
BPI_BUS9
I
I
I
I
O
O
4
4
O
O
O
O
O
O
IO
IO
IO
IO
RF Parallel Control Unit
2/8
0.4
2/8
0.4
2/8
0.4
2/8
0.4
2
0.4
2
0.4
2
0.4
2
0.4
2
0.4
2
0.4
0.4
0.4
Cin
(pF)
Max
40K
40K
40K
40K
75K
75K
75K
75K
190K
190K
190K
190K
PD
PU
PU
PU
2
2
2
2
40K
40K
40K
40K
75K
75K
75K
75K
190K
190K
190K
190K
PD
PD
PD
PD
2
2
2
2
Re
lea
se
G5
G4
G3
G1
J6
H5
H4
H3
H2
J5
JTRST#
JTCK
JTDI
JTMS
JTDO
JRTCK
2.4
2.4
2.4
2.4
2.4
2.4
2.4
2.4
2.4
2.4
2.4
2.4
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E4
F5
F4
F3
F2
F1
Pull
fo
r
Ball
Name
13x13
RF Serial Control Unit
J4
J3
J2
BSI_CS0
BSI_DATA
BSI_CLK
R4
R3
R2
PWM1
PWM2
ALERTER
J1
K5
K4
K3
K2
LSCK
LSA0
LSDA
LSCE0#
LSCE1#
O
O
O
2
2
2
IO
IO
IO
2
2
2
IO
IO
IO
IO
IO
2/4/6/8
2/4/6/8
2/4/6/8
2/4/6/8
2/4/6/8
0.4
0.4
0.4
2.4
2.4
2.4
0.4
0.4
0.4
2.4
2.4
2.4
40K
40K
40K
75K
75K
75K
190K
190K
190K
PD
PD
PD
2
2
2
2.4
2.4
2.4
2.4
2.4
40K
40K
40K
40K
40K
75K
75K
75K
75K
75K
190K
190K
190K
190K
190K
PU
PU
PU
PU
PU
2
2
2
2
2
2.4
40K
75K
190K
PU
2
PWM Interface
Serial LCD/PM IC Interface
0.4
0.4
0.4
0.4
0.4
K6
L5
L4
L3
MT
K
Parallel LCD/NAND-Flash
Interface
LPCE1#
LPCE0#
LRST#
LRD#
IO
O
O
O
2/4/6/8
2/4/6/8
2/4/6/8
2/4/6/8
0.4
612/616
MediaTek Inc. Confidential
O
O
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
2/4/6/8
2/4/6/8
2/4/6/8
2/4/6/8
2/4/6/8
2/4/6/8
2/4/6/8
2/4/6/8
2/4/6/8
2/4/6/8
2/4/6/8
2/4/6/8
2/4/6/8
2/4/6/8
2/4/6/8
2/4/6/8
2/4/6/8
2/4/6/8
2/4/6/8
2/4/6/8
2/4/6/8
2/4/6/8
2/4/6/8
2/4/6/8
2/4/6/8
2/4/6/8
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
2.4
2.4
2.4
2.4
2.4
2.4
2.4
2.4
2.4
2.4
2.4
2.4
2.4
2.4
2.4
2.4
2.4
2.4
2.4
2.4
2.4
2.4
2.4
2.4
40K
40K
40K
40K
40K
40K
40K
40K
40K
40K
40K
40K
40K
40K
40K
40K
40K
40K
40K
40K
40K
40K
40K
40K
75K
75K
75K
75K
75K
75K
75K
75K
75K
75K
75K
75K
75K
75K
75K
75K
75K
75K
75K
75K
75K
75K
75K
75K
190K
190K
190K
190K
190K
190K
190K
190K
190K
190K
190K
190K
190K
190K
190K
190K
190K
190K
190K
190K
190K
190K
190K
190K
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PU
PD
PD
PU
PU
PU
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
40K
75K
190K
PD
2
2
40K
40K
40K
40K
75K
75K
75K
75K
190K
190K
190K
190K
PD
PD
PU
PU
2
2
2
2
2
2
2
2
2
2
fo
r
LPA0
LWR#
NLD17
NLD16
NLD15
NLD14
NDL13
NLD12
NLD11
NLD10
NLD9
NLD8
NLD7
NLD6
NLD5
NLD4
NLD3
NLD2
NLD1
NLD0
NRNB
NCLE
NALE
NWE#
NRE#
NCE#
Re
lea
se
L2
L1
G7
J9
K9
J10
L9
K10
J11
L10
K11
L11
L6
M5
M4
M3
N5
N4
N3
N2
N1
P5
P4
P3
P2
P1
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MT6228 GSM/GPRS Baseband Processor Data Sheet Revision 1.0
M19
L16
L17
L18
L19
SIMRST
SIMCLK
SIMVCC
SIMSEL
SIMDATA
U3
U1
D17
C19
C18
C17
A19
B18
A18
A17
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
T2
R16
T1
T4
T3
SYSRST#
WATCHDOG#
SRCLKENAN
SRCLKENA
SRCLKENAI
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SIM Card Interface
O
O
O
IO
IO
2
2
2
2/4/6/8
2
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
2
2
2
2
2/4/6/8
2/4/6/8
2/4/6/8
2/4/6/8
4
4
0.4
0.4
0.4
0.4
0.4
2.4
2.4
2.4
2.4
2.4
Dedicated GPIO Interface
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
2.4
2.4
2.4
2.4
2.4
2.4
2.4
2.4
2.4
2.4
0.4
0.4
0.4
0.4
2.4
2.4
2.4
2.4
Miscellaneous
MT
K
I
O
O
O
IO
2
4
2
2
2
613/616
40K
75K
190K
PD
2
MediaTek Inc. Confidential
E5
D15
TESTMODE
ESDM_CK
I
O
40K
75K
190K
PD
2
40K
40K
40K
40K
40K
40K
40K
75K
75K
75K
75K
75K
75K
75K
190K
190K
190K
190K
190K
190K
190K
PU
PU
PU
PU
PU
PU
PU
2
2
2
2
2
2
2
190K
190K
190K
190K
190K
190K
PU
PU
PU
PU
PU
PU
2
2
2
2
2
2
I
I
I
I
I
I
I
O
O
O
O
O
O
U2
V1
W1
V2
U4
B17
EINT0
EINT1
EINT2
EINT3
MIRQ
MFIQ
I
I
I
I
I
I
4
2/4/6/8
R15
T19
T18
U19
U18
V19
W19
W18
U17
W17
T16
U16
V16
T15
U15
W15
P12
T12
U12
V12
P11
R11
R14
T14
W14
ED0
ED1
ED2
ED3
ED4
ED5
ED6
ED7
ED8
ED9
ED10
ED11
ED12
ED13
ED14
ED15
ERD#
EWR#
ECS0#
ECS1#
ECS2#
ECS3#
EWAIT
ECAS#
ERAS#
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
O
O
O
O
O
O
O
O
O
External Memory Interface
2~32
0.4
2~32
0.4
2~32
0.4
2~32
0.4
2~32
0.4
2~32
0.4
2~32
0.4
2~32
0.4
2~32
0.4
2~32
0.4
2~32
0.4
2~32
0.4
2~32
0.4
2~32
0.4
2~32
0.4
2~32
0.4
2~32
0.4
2~32
0.4
2~32
0.4
2~32
0.4
2~32
0.4
2~32
0.4
2~32
2~32
0.4
2~32
0.4
2
2
2
2
2
2
2
2/8
2/8
2/8
2/8
2
2
0.4
0.4
0.4
0.4
0.4
0.4
2.4
2.4
2.4
2.4
2.4
2.4
External Interrupt Interface
2.4
2.4
40K
40K
40K
40K
40K
40K
75K
75K
75K
75K
75K
75K
2.4
2.4
2.4
2.4
2.4
2.4
2.4
2.4
2.4
2.4
2.4
2.4
2.4
2.4
2.4
2.4
2.4
2.4
2.4
2.4
2.4
2.4
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
MT
K
Co
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0.4
0.4
Re
lea
se
KCOL6
KCOL5
KCOL4
KCOL3
KCOL2
KCOL1
KCOL0
KROW5
KROW4
KROW3
KROW2
KROW1
KROW0
fo
r
Keypad Interface
H17
H18
H19
G15
G16
G17
G18
G19
F15
F16
F17
E16
E17
Ko
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MT6228 GSM/GPRS Baseband Processor Data Sheet Revision 1.0
40K
75K
190K
PU
2.4
2.4
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MCCM0
MCDA0
MCDA1
MCDA2
MCDA3
MCCK
MCPWRON
MCWP
MCINS
2~32
2~32
2~32
2~32
10
2~32
2~32
2~32
2~32
2~32
2~32
2~32
2~32
2~32
2~32
2~32
2~32
2~32
2~32
2~32
2~32
2~32
2~32
2~32
2~32
2~32
2~32
2~32
2~32
2~32
2~32
2~32
2~32
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
2.4
2.4
2.4
2.4
2.4
2.4
2.4
2.4
2.4
2.4
2.4
2.4
2.4
2.4
2.4
2.4
2.4
2.4
2.4
2.4
2.4
2.4
2.4
2.4
2.4
2.4
2.4
2.4
2.4
2.4
2.4
2.4
2.4
IO
IO
IO
IO
IO
O
O
I
I
2/4/6/8
2/4/6/8
2/4/6/8
2/4/6/8
2/4/6/8
2/4/6/8
2
2
2
0.4
0.4
0.4
0.4
0.4
0.4
0.4
2.4
2.4
2.4
2.4
2.4
2.4
2.4
fo
r
P17
P18
P19
N17
N18
M18
N19
M16
M17
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
Re
lea
se
ECKE
EDCLK
ELB#
EUB#
EPDN#
EADV#
ECLK
EA0
EA1
EA2
EA3
EA4
EA5
EA6
EA7
EA8
EA9
EA10
EA11
EA12
EA13
EA14
EA15
EA16
EA17
EA18
EA19
EA20
EA21
EA22
EA23
EA24
EA25
Co
nf
id
en
tia
l
R13
T13
V13
W13
T11
W11
V11
P10
T10
U10
W10
R9
T9
U9
V9
R8
T8
W8
P8
R7
U7
V7
W7
T6
U6
W6
R5
T5
U5
V5
W4
V4
W3
Ko
nk
a
MT6228 GSM/GPRS Baseband Processor Data Sheet Revision 1.0
40K
40K
40K
40K
40K
75K
75K
75K
75K
75K
190K
190K
190K
190K
190K
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
2
2
2
2
2
40K
40K
75K
75K
190K
190K
PU/PD
PU/PD
2
2
40K
75K
190K
PU
2
40K
75K
190K
PU
2
40K
75K
190K
PU
2
UART/IrDA Interface
URXD1
UTXD1
UCTS1
URTS1
URXD2
I
O
I
O
IO
MT
K
K15
K16
K17
K18
K19
2/4/6/8
2/4/6/8
2/4/6/8
2/4/6/8
2/4/6/8
0.4
2.4
0.4
0.4
2.4
2.4
615/616
MediaTek Inc. Confidential
J15
J16
J17
J19
H15
H16
UTXD2
URXD3
UTXD3
IRDA_RXD
IRDA_TXD
IRDA_PDN
IO
IO
IO
IO
IO
IO
2/4/6/8
2/4/6/8
2/4/6/8
2/4/6/8
2/4/6/8
2/4/6/8
0.4
0.4
0.4
0.4
0.4
0.4
2.4
2.4
2.4
2.4
2.4
2.4
40K
40K
40K
40K
40K
40K
75K
75K
75K
75K
75K
75K
190K
190K
190K
190K
190K
190K
PU
PU
PU
PU
PU
PU
2
2
2
2
2
2
2.4
2.4
2.4
2.4
2.4
40K
40K
40K
40K
40K
75K
75K
75K
75K
75K
190K
190K
190K
190K
190K
PU
PD
PU
PU
PU
2
2
2
2
2
0.4
0.4
2.4
2.4
40K
40K
40K
40K
40K
75K
75K
75K
75K
75K
190K
190K
190K
190K
190K
PD
PD
PD
PD
PD
2
2
2
2
2
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
2.4
2.4
2.4
2.4
2.4
2.4
2.4
2.4
2.4
2.4
2.4
40K
40K
40K
40K
40K
40K
40K
40K
40K
40K
75K
75K
75K
75K
75K
75K
75K
75K
75K
75K
190K
190K
190K
190K
190K
190K
190K
190K
190K
190K
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
2
2
2
2
2
2
2
2
2
2
DAICLK
DAIPCMOUT
DAIPCMIN
DAIRST
DAISYNC
IO
IO
IO
IO
IO
2/4/6/8
2/4/6/8
2/4/6/8
2/4/6/8
2/4/6/8
J12
K12
H12
H11
H9
H10
H8
J8
K8
L8
M8
M9
M10
M11
M12
L12
CMRST
CMPDN
CMVREF
CMHREF
CMPCLK
CMMCLK
CMDAT9
CMDAT8
CMDAT7
CMDAT6
CMDAT5
CMDAT4
CMDAT3
CMDAT2
CMDAT1
CMDAT0
IO
IO
I
I
I
O
I
I
I
I
I
I
I
I
IO
IO
2
2
2
2
2
2/4/6/8
2/4/6/8
2/4/6/8
2/4/6/8
2/4/6/8
2/4/6/8
2/4/6/8
2/4/6/8
2/4/6/8
2/4/6/8
2/4/6/8
0.4
0.4
0.4
0.4
0.4
MT
K
Co
nf
id
en
tia
l
Re
lea
se
CMOS Sensor Interface
fo
r
Digital Audio Interface
E18
E19
D16
D19
D18
Ko
nk
a
MT6228 GSM/GPRS Baseband Processor Data Sheet Revision 1.0
616/616
MediaTek Inc. Confidential
www.s-manuals.com
Source Exif Data:
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