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MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 Apr 07, 2008 MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 Revision History Revision Date Comments 1.00 Sept 18, 2007 First Release 1.01 Dec 13, 2007 1. 2. Update GPIO10 GPIO11 mode definition Update ch8 audio front end and ch13 analog front end & analog blocks for PMU ball name change (VMC,VSW_A, VCAMERA) > (VBT, VCAM_A, VCAM_D) 1.02 Apr 07, 2008 1. Update RGU, MCU, RTC, SIM, EMI, GLCON, TG, System Overview, and Product Description 2/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 TABLE OF CONTENTS Revision History...................................................................................................................................... 2 Preface...................................................................................................................................................... 5 1. System Overview............................................................................................................................... 6 Platform Features................................................................................................................................................................. 9 1.1 MODEM Features.....................................................................................................................................................11 1.2 Multi-Media Features............................................................................................................................................... 12 1.3 General Description ................................................................................................................................................. 13 2 Product Description........................................................................................................................ 15 2.1 2.2 2.3 2.4 2.5 Pin Outs.................................................................................................................................................................... 15 Top Marking Definition ........................................................................................................................................... 18 DC Characteristics ................................................................................................................................................... 19 Pin Description......................................................................................................................................................... 20 Power Description.................................................................................................................................................... 32 3 Micro-Controller Unit Subsystem ................................................................................................. 40 3.1 3.2 3.3 3.4 3.5 3.6 3.7 Processor Core ......................................................................................................................................................... 41 Memory Management .............................................................................................................................................. 41 Bus System............................................................................................................................................................... 44 Direct Memory Access............................................................................................................................................. 48 Interrupt Controller .................................................................................................................................................. 66 BUS Monitor (BM).................................................................................................................................................. 82 External Memory Interface (6235)........................................................................................................................... 93 4 Microcontroller Peripherals ........................................................................................................ 104 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 4.10 4.11 4.12 Security Engine with JTAG control ....................................................................................................................... 104 EFUSE Controller (efusec) .................................................................................................................................... 107 Pulse-Width Modulation Outputs............................................................................................................................111 SIM Interface ......................................................................................................................................................... 150 Keypad Scanner ..................................................................................................................................................... 159 General Purpose Inputs/Outputs ............................................................................................................................ 162 General Purpose Timer........................................................................................................................................... 181 UART..................................................................................................................................................................... 184 IrDA Framer........................................................................................................................................................... 199 Real Time Clock..................................................................................................................................................... 208 Auxiliary ADC Unit ............................................................................................................................................... 216 I2C / SCCB Controller ........................................................................................................................................... 220 5 Microcontroller Coprocessors ..................................................................................................... 232 5.1 5.2 5.3 5.4 Divider ................................................................................................................................................................... 232 CSD Accelerator .................................................................................................................................................... 234 FCS Codec ............................................................................................................................................................. 246 GPRS Cipher Unit.................................................................................................................................................. 248 6 MCU/DSP Interface...................................................................................................................... 252 6.1 6.2 6.3 MCU/DSP Shared Registers .................................................................................................................................. 254 MCU/DSP Shared RAM ........................................................................................................................................ 261 AHB-to-DDMA Bridge.......................................................................................................................................... 263 7 Multi-Media Subsystem ............................................................................................................... 268 7.1 7.2 LCD Interface ........................................................................................................................................................ 268 Capture Resize ....................................................................................................................................................... 292 3/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 7.3 7.4 7.5 7.6 7.7 NAND FLASH interface ....................................................................................................................................... 300 USB 2.0 High-Speed Dual-Role Controller ........................................................................................................... 320 Memory Stick and SD Memory Card Controller ................................................................................................... 358 2D acceleration ...................................................................................................................................................... 383 Camera Interface .................................................................................................................................................... 410 8 Audio Front-End........................................................................................................................... 422 8.1 8.2 8.3 8.4 General Description ............................................................................................................................................... 422 Register Definitions ............................................................................................................................................... 425 DSP Register Definitions ....................................................................................................................................... 439 Programming Guide............................................................................................................................................... 444 9 Radio Interface Control ............................................................................................................... 446 9.1 9.2 9.3 9.4 Baseband Serial Interface....................................................................................................................................... 446 Baseband Parallel Interface.................................................................................................................................... 454 Automatic Power Control (APC) Unit ................................................................................................................... 457 Automatic Frequency Control (AFC) Unit ............................................................................................................ 464 10 Baseband Front End..................................................................................................................... 467 10.1 Baseband Serial Ports............................................................................................................................................. 468 10.2 Downlink Path (RX Path) ...................................................................................................................................... 472 10.3 Uplink Path (TX Path) ........................................................................................................................................... 480 11 Timing Generator ......................................................................................................................... 487 11.1 TDMA timer........................................................................................................................................................... 487 11.2 Slow Clocking Unit................................................................................................................................................ 499 12 Power, Clocks and Reset .............................................................................................................. 503 12.1 Clocks .................................................................................................................................................................... 503 12.2 Reset Generation Unit (RGU)................................................................................................................................ 507 12.3 Global Configuration Registers...............................................................................................................................511 13 Analog Front-end & Analog Blocks ............................................................................................ 526 13.1 General Description ............................................................................................................................................... 526 13.2 MCU Register Definitions ..................................................................................................................................... 537 13.3 Programming Guide............................................................................................................................................... 579 14 Digital Pin Electrical Characteristics.......................................................................................... 593 4/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 Preface Acronym for Register Type R/W Capable of both read and write access RO Read only RC Read only. After reading the register bank, each bit which is HIGH(1) will be cleared to LOW(0 ) automatically. WO Write only W1S Write only. When writing data bits to register bank, each bit which is HIGH(1) will cause the corresponding bit to be set to 1. Data bits which are LOW(0) has no effect on the corresponding bit. W1C Write only. When writing data bits to register bank, each bit which is HIGH(1) will cause the corresponding bit to be cleared to 0. Data bits which are LOW(0) has no effect on the corresponding bit. 5/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 1. System Overview MT6235 is a highly-integrated and extremely powerful single-chip solution for GSM/GPRS/EDGE mobile phones. Based on the 32-bit ARM926EJ-STM RISC processor, MT6235’s superb processing power, along with high bandwidth architecture and dedicated hardware support, provides an unprecedented platform for high performance GPRS/EDGE Class 12 MODEM application. Overall, MT6235 presents a revolutionary platform for mobile devices. Typical application diagram is shown in Figure 1. Platform MT6235 is capable of running the ARM926EJ-STM RISC processor at up to 208 MHz, thus providing fast data processing capabilities. In addition to the high clock frequency, separate CODE and DATA caches are also included to further improve the overall system efficiency. For large amounts of data transfer, high performance DMA (Direct Memory Access) with hardware flow control is implemented, which greatly enhances the data movement speed while reducing MCU processing load. Targeted as a high performance platform for mobile applications, hardware flash content protection is also provided to prevent unauthorized porting of the software load to protect the manufacturer’s development investment. Memory To provide the greatest capacity for expansion and maximum bandwidth for data intensive applications such as multimedia features, MT6235 supports up to 4 external state-of-the-art devices through its 8/16-bit host interface. High performance devices such as Mobile SDRAM and Cellular RAM are supported for maximum bandwidth. Traditional devices such as burst/page mode flash, page mode SRAM, and Pseudo SRAM are also supported. For greatest compatibility, the memory interface can also be used to connect to legacy devices such as Color/Parallel LCD, and multi-media companion chips are all supported through this interface. To minimize power consumption and ensure low noise, this interface is designed for flexible I/O voltage and allows lowering of the supply voltage down to 1.8V. The driving strength is configurable for signal integrity adjustment. Multi-media The MT6235 multi-media subsystem provides a connection to a CMOS image sensor and supports a resolution up to 2.0 Mpixels. With its high performance application platform, MT6235 allows efficient processing of image and video data. In addition to image and video features, MT6235 utilizes high resolution DAC, digital audio, and audio synthesis technology to provide superior audio features for all future multi-media needs. Connectivity and Storage To take advantage of its incredible multimedia strengths, MT6235 incorporates myriads of advanced connectivity and storage options for data storage and communication. MT6235 supports UART, Fast IrDA, USB 2.0, SDIO, Bluetooth, Touch Screen Controller, WIFI Interface, and MMC/SD/MS/MS Pro storage systems. These interfaces provide MT6235 users with the highest degree of flexibility in implementing solutions suitable for the targeted application. To achieve a complete user interface, MT6235 also brings together all the necessary peripheral blocks for a multi-media GSM/GPRS/EDGE phone. The peripheral blocks include the Keypad Scanner with the capability to detect multiple key presses, SIM Controller, Alerter, Real Time Clock, PWM, Serial LCD Controller, and General Purpose Programmable I/Os. Furthermore, to provide much better configurability and bandwidth for multi-media products, an additional 18-bit parallel interface is incorporated. This interface enables connection to LCD panels as well as NAND flash devices for additional multi-media data storage. Audio 6/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 Using a highly integrated mixed-signal Audio Front-End, the MT6235 architecture allows for easy audio interfacing with direct connection to the audio transducers. The audio interface integrates D/A and A/D Converters for Voice band, as well as high resolution Stereo D/A Converters for Audio band. In addition, MT6235 also provides Stereo Input and Analog MUX. advanced low leakage CMOS process, hence providing an overall ultra low leakage solution. Package The MT6235 device is offered in a 13mm×13mm, 362-ball, 0.5 mm pitch, TFBGA package. MT6235 supports AMR codec to adaptively optimize speech and audio quality. Moreover, HE-AAC codec is implemented to deliver CD-quality audio at low bit rates. On the whole, MT6235’s audio features provide a rich solution for multi-media applications. Radio MT6235 integrates a mixed-signal baseband front-end in order to provide a well-organized radio interface with flexibility for efficient customization. The front-end contains gain and offset calibration mechanisms, and filters with programmable coefficients for comprehensive compatibility control on RF modules. This approach allows the usage of a high resolution D/A Converter for controlling VCXO or crystal, reducing the need for an expensive TCVCXO. MT6235 achieves great MODEM performance by utilizing a 14-bit high resolution A/D Converter in the RF downlink path. Furthermore, to reduce the need for extra external current-driving component, the driving strength of some BPI outputs is designed to be configurable. Debug Function The JTAG interface enables in-circuit debugging of the software program with the ARM926EJ-S core. With this standardized debugging interface, MT6235 provides developers with a wide set of options in choosing ARM development kits from different third party vendors. Power Management The MT6235 offers various low-power features to help reduce system power consumption. These features include a Pause Mode of 32 KHz clocking in Standby State, Power Down Mode for individual peripherals, and Processor Sleep Mode. MT6235 is also fabricated in an 7/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 Figure 1 Typical application of MT6235 8/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 Platform Features General z z Integrated voice-band, audio-band and base-band analog front ends TFBGA 13mm×13mm, 362-ball, 0.5 mm pitch package MCU Subsystem z ARM926EJ-S 32-bit RISC processor z High performance multi-layer AMBA bus z Java hardware acceleration for fast Java-based games and applets z Operating frequency: 26/52/104/208 MHz z Dedicated DMA bus z 14 DMA channels z 512K bits on-chip SRAM z 384K bits Instruction-TCM z 640K bits Data-TCM z z Supports Flash and SRAM/PSRAM with page mode or burst mode z Industry standard Parallel LCD interface z Supports multi-media companion chips with 8/16 bits data width z Flexible I/O voltage of 1.8V ~ 2.8V for memory interface z Configurable driving strength for memory interface User Interfaces z 8-row × 8-column keypad controller with hardware scanner z Supports multiple key presses for gaming z SIM/USIM controller with hardware T=0/T=1 protocol control z Real Time Clock (RTC) operating with a separate power supply 128K bits Instruction-Cache z General Purpose I/Os (GPIOs) z 128K bits Data-Cache z 4 sets of Pulse Width Modulation (PWM) output z On-chip boot ROM for Factory Flash Programming z Alerter output with Enhanced PWM or PDM z 8 external interrupt lines z Watchdog timer for system crash recovery z 3 sets of General Purpose Timer z Circuit Switch Data coprocessor z Division coprocessor z PPP Framer coprocessor z External Memory Interface z Supports up to 4 external memory devices z Supports 8-bit or 16-bit memory components with maximum size of up to 128M Bytes each z Supports Mobile SDRAM and Cellular RAM Security 9/599 Supports security key and 126 bit chip unique ID Connectivity z 3 UARTs with hardware flow control and speeds up to 921600 bps z IrDA modulator/demodulator with hardware framer. Supports SIR/MIR/FIR operating speeds. z USB 2.0 capability z Multi Media Card, Secure Digital Memory Card, Memory Stick, Memory Stick Pro host controller with flexible I/O voltage power MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 z Supports SDIO interface for SDIO peripherals as well as WIFI connectivity z DAI/PCM and I2S interface for Audio application Power Management z Power Down Mode for analog and digital circuits z Processor Sleep Mode z Pause Mode of 32 KHz clocking in Standby State z 4-channel Auxiliary 10-bit A/D Converter for charger and battery monitoring and photo sensing Test and Debug z Built-in digital and analog loop back modes for both Audio and Baseband Front-End z DAI port complying with GSM Rec.11.10 z JTAG port for debugging embedded MCU 10/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 1.1 Radio Interface and Baseband Front End z GMSK modulator with analog I and Q channel outputs z 10-bit D/A Converter for uplink baseband I and Q signals z 14-bit high resolution A/D Converter for downlink baseband I and Q signals z Calibration mechanism of offset and gain mismatch for baseband A/D Converter and D/A Converter z 10-bit D/A Converter for Automatic Power Control z 13-bit high resolution D/A Converter for Automatic Frequency Control z Programmable Radio RX filter z 2 channels Baseband Serial Interface (BSI) with 3-wire control z Bi-directional BSI interface. RF chip register read access with 3-wire or 4-wire interface. z 10-Pin Baseband Parallel Interface (BPI) with programmable driving strength z MODEM Features Multi-band support z GSM/GPRS quad vocoders for adaptive multirate (AMR), enhanced full rate (EFR), full rate (FR) and half rate (HR) z GSM channel coding, equalization and A5/1, A5/2 and A5/3 ciphering z GPRS GEA1, GEA2 and GEA3 ciphering z Programmable GSM/GPRS/EDGE modem z Packet Switched Data with CS1/CS2/CS3/CS4 coding schemes z GSM Circuit Switch Data z GPRS/EDGE Class 12 Voice Interface and Voice Front End z Two microphone inputs sharing one low noise amplifier with programmable gain and automatic gain control (AGC) mechanisms z Voice power amplifier with programmable gain z 2nd order Sigma-Delta A/D Converter for voice uplink path z D/A Converter for voice downlink path z Supports half-duplex hands-free operation z Compliant with GSM 03.50 Voice and Modem CODEC z Dial tone generation z Voice memo z Noise reduction z Echo suppression z Advanced sidetone Oscillation Reduction z Digital sidetone generator with programmable gain z Two programmable acoustic compensation filters 11/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 1.2 LCD/NAND Flash Interface z Horizontal scaling in averaging method z z Vertical scaling in bilinear method z YUV and RGB color space conversion z Boundary padding z Dedicated Parallel Interface supports 3 external devices with 8-/16-bit NAND flash interface, 8-/9-/16-/18-bit Parallel interface, and Serial interface for LCM Built-in NAND Flash Controller with 1-bit ECC for mass storage 2D Accelerator z Supports 32-bpp ARGB8888, 24-bpp RGB888, 16-bpp RGB565, and 8-bpp index color modes Supports simultaneous connection to up to 3 parallel LCD and 2 serial LCD modules z Supports SVG Tiny z Rectangle gradient fill z Supports LCM format: RGB332, RGB444, RGB565, RGB666, RGB888 z BitBlt: multi-BitBlt with 7 rotation, 16 binary ROP z Supports LCD module with maximum resolution up to 800x600 at 24bpp z Alpha blending with 7 rotation z z Per pixel alpha channel Line drawing: normal line, dotted line, anti-aliasing z True color engine z Circle drawing z Supports hardware display rotation z Bezier curve drawing z Capable of combining display memories with up to 6 blending layers z Triangle flat fill z Font caching: normal font, italic font z Command queue with max depth of 2047 LCD Controller z Multi-Media Features Image Signal Processor Audio CODEC z 8 bit YUV format image input z Capable of processing image of size up to 2.0 M pixels z Supports HE-AAC codec decode z Supports AAC codec decode z IEEE Std 1180-1990 IDCT standards compliance z Wavetable synthesis with up to 64 tones z Supports progressive image processing to minimize storage space requirement z Advanced wavetable synthesizer capable of generating simulated stereo z Supports reload-able DMA for VLD stream z Wavetable including GM full set of 128 instruments and 47 sets of percussions Image Data Processing z Supports Digital Zoom z PCM Playback and Record z Supports RGB888/565, YUV444 image processing z Digital Audio Playback z High throughput hardware scaler. Capable of tailoring an image to an arbitrary size. Audio Interface and Audio Front End z 12/599 Supports I2S interface MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 z z 1.3 High resolution D/A Converters for Stereo Audio playback z Analog multiplexer for stereo audio z Stereo to mono conversion Stereo analog input for stereo audio source General Description Figure 2 depicts the block diagram of MT6235. Based on a dual-processor architecture, MT6235 integrates both an ARM926EJ-S core and a digital signal processor core. ARM926EJ-S is the main processor responsible for running high-level GSM/GPRS protocol software as well as multi-media applications. The digital signal processor manages the low-level MODEM as well as advanced audio functions. Except for a few mixed-signal circuitries, the other building blocks in MT6235 are connected to either the microcontroller or the digital signal processor. MT6235consists of the following subsystems: z Microcontroller Unit (MCU) Subsystem: includes an ARM926EJ-S RISC processor and its accompanying memory management and interrupt handling logics; z Digital Signal Processor (DSP) Subsystem: includes a DSP and its accompanying memory, memory controller, and interrupt controller; z MCU/DSP Interface: the junction at which the MCU and the DSP exchange hardware and software information; z Microcontroller Peripherals: includes all user interface modules and RF control interface modules; z Microcontroller Coprocessors: runs computing-intensive processes in place of the Microcontroller; z DSP Peripherals: hardware accelerators for GSM/GPRS/EDGE channel codec; z Multi-media Subsystem: integrates several advanced accelerators to support multi-media applications; z Voice Front End: the data path for converting analog speech to and from digital speech; z Audio Front End: the data path for converting stereo audio from an audio source; z Baseband Front End: the data path for converting a digital signal to and from an analog signal from the RF modules; z Timing Generator: generates the control signals related to the TDMA frame timing; and, z Power, Reset and Clock Subsystem: manages the power, reset, and clock distribution inside MT6235. Details of the individual subsystems and blocks are described in the following chapters. 13/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 Figure 2 MT6235 block diagram. 14/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 2 2.1 Product Description Pin Outs One type of package for this product, TFBGA 13mm*13mm, 362-ball, 0.5 mm pitch package, is offered. Pin-outs and the top view are illustrated in Figure 3 for this package. Outline and dimension of package is illustrated in Figure 4, while the definition of package is shown in Table 1. 15/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 Figure 3 Top view of MT6235 TFBGA 13mm*13mm, 362-ball, 0.5 mm pitch package Notes: RFU is reserved for future use and leave as NC in normal operation. 16/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 Figure 4 Outlines and dimension of TFBGA 13mm*13mm, 362-ball, 0.5 mm pitch package Body Size Ball Count Ball Pitch Ball Dia. Package Thk. Stand Off Substrate Thk. D E N e b A (MAX) A1(NOM) C 13 13 362 0.5 0.3 1.2 0.21 0.36 Table 1 Definition of TFBGA 13mm*13mm, 362-ball, 0.5 mm pitch package (Unit: mm) 17/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 2.2 Top Marking Definition MT6235A DDDD-### LLLLL S MT6235A: Part No. DDDD: Date Code ###: Subcontractor Code LLLLL: U1 Die Lot No. S: Special Code 18/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 2.3 2.3.1 DC Characteristics Absolute Maximum Ratings Prolonged exposure to absolute maximum ratings may reduce device reliability. Functional operation at these maximum ratings is not implied. Item Symbol Min Max IO power supply VDD33 -0.3 VDD33+0.3 V I/O input voltage VDD33 -0.3 VDD33+0.3 V Operating temperature Topr -20 80 Celsius Storage temperature Tstg -55 125 Celsius 19/599 Unit MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 2.4 Pin Description Ball Description 13X13 Name Dir Mode0 Mode1 Mode2 Mode3 PU/ Rese PD t JTAG Port G4 JTRST_B I JTAG test port reset input PD PD G3 JTCK I JTAG test port clock input PU PU G2 JTDI I JTAG test port data input PU PU G1 JTMS I JTAG test port mode switch PU PU H1 JTDO IO JTAG test port data output H2 JRTCK IO JTAG test port returned clock output RF Parallel Control Unit AE6 BPI_BUS0 IO RF hard-wire control bus 0 AD7 BPI_BUS1 IO RF hard-wire control bus 1 AC7 BPI_BUS2 IO RF hard-wire control bus 2 AC6 BPI_BUS3 IO RF hard-wire control bus 3 AE8 BPI_BUS4 IO RF hard-wire control bus 4 AD8 BPI_BUS5 IO RF hard-wire control bus 5 AC8 BPI_BUS6 IO AB8 BPI_BUS7 IO GPIO19 BPI_BUS3 PU/ PD PD RF hard-wire control bus 6 GPIO20 BPI_BUS6 PU/ PD PD RF hard-wire control bus 7 GPIO21 BPI_BUS7 PU/ PD PD 20/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 AE9 BPI_BUS8 IO RF hard-wire control bus 8 GPIO22 BPI_BUS8 AD9 BPI_BUS9 IO RF hard-wire control bus 9 GPIO23 BPI_BUS9 PU/ PD PD BSI_CS1 PU/ PD PD RF Serial Control Unit AC9 BSI_CS0 IO RF 3-wire interface chip select 0 AE10 BSI_DATA IO RF 3-wire interface data output IO RF 3-wire interface clock output AD10 BSI_CLK PWM Interface AC10 PWM0 IO Pulse width modulated signal 0 GPIO39 PWM0 PU/ PD PD AB10 PWM1 IO Pulse width modulated signal 1 GPIO40 PWM1 AC5 PWM2 IO Pulse width modulated signal 2 GPIO17 PWM2 D2_TID5 PU/ PD PD AE5 PWM3 IO Pulse width modulated signal 3 GPIO18 PWM3 D2_TID6 PU/ PD PD BSI_RFIN PU/ PD PD Camera Control Interface AE4 SCL IO GPIO15 SCL D2_TID3 PU/ PU PD AD5 SDA IO GPIO16 SDA D2_TID4 PU/ PU PD Serial LCD/PM IC Interface AC11 LSCK IO Serial display interface data output GPIO24 LSCK DSP_GPO2 IRQ0 PU/ PD PD U11 LSA0 IO Serial display interface address output GPIO25 LSA0 DSP_GPO3 IRQ1 PU/ PD PD 21/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 AD12 LSDA IO Serial display interface clock output GPIO26 LSDA CLKM1 TDTIRQ PU/ PD PD AE12 LSCE0B IO Serial display interface chip select 0 output GPIO27 LSCE0B CLKM2 TCTIRQ2 PU/ PU PD AC12 LSCE1B IO Serial display interface chip select 1 output GPIO28 LSCE1B LPCE2B TCTIRQ1 PU/ PU PD GPIO29 LPCE1B NCE1B TEVTVAL PU/ PU PD GPIO30 LPTE PU/ PD PD GPIO31 NLD17 PU/ PD PD PU/ PD PD PD PD PD PD PD PD PD PD PD PD PD PD PD PD PD PD PU/ PU PD PU/ PD PU/ PD PU/ PD PU/ PD Parallel LCD/NAND-Flash Interface AB12 LPCE1B IO U12 LPCE0B IO AE13 LPTE IO Parallel display interface chip select 1 output Parallel display interface chip select 0 output AC13 LRSTB AD13 LRDB U13 LPA0 IO IO IO AE14 LWRB AD14 NLD17 IO IO Parallel display interface Reset Signal Parallel display interface Read Strobe Parallel display interface address output Parallel display interface Write Strobe Parallel LCD/NAND-Flash Data 17 AC14 NLD16 IO Parallel LCD/NAND-Flash Data 16 GPIO32 NLD16 AB14 U14 AE15 AD15 AC15 AB15 AE16 AD16 AC16 AB16 U16 AE17 AD17 AC17 AE18 AD18 AC18 IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO Parallel LCD/NAND-Flash Data 15 Parallel LCD/NAND-Flash Data 14 Parallel LCD/NAND-Flash Data 13 Parallel LCD/NAND-Flash Data 12 Parallel LCD/NAND-Flash Data 11 Parallel LCD/NAND-Flash Data 10 Parallel LCD/NAND-Flash Data 9 Parallel LCD/NAND-Flash Data 8 Parallel LCD/NAND-Flash Data 7 Parallel LCD/NAND-Flash Data 6 Parallel LCD/NAND-Flash Data 5 Parallel LCD/NAND-Flash Data 4 Parallel LCD/NAND-Flash Data 3 Parallel LCD/NAND-Flash Data 2 Parallel LCD/NAND-Flash Data 1 Parallel LCD/NAND-Flash Data 0 NAND-Flash Read/Busy Flag GPIO33 NRNB AB18 NCLE IO NAND-Flash Command Latch Signal GPIO34 NCLE AE19 NALE IO NAND-Flash Address Latch Signal GPIO35 NALE AD19 NWEB IO NAND-Flash Write Strobe GPIO36 NWEB AC19 NREB IO NAND-Flash Read Strobe GPIO37 NREB NLD15 NLD14 NDL13 NLD12 NLD11 NLD10 NLD9 NLD8 NLD7 NLD6 NLD5 NLD4 NLD3 NLD2 NLD1 NLD0 NRNB 22/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 AB19 NCEB IO NAND-Flash Chip select output GPIO38 PU/ PD NCE0B Miscellaneous F25 G23 U10 SYSRST_B I WATCHDOG IO SRCLKENAN IO AE11 SRCLKENA IO System reset input active low Watchdog reset output External TCXO enable output active low External TCXO enable output active high External TCXO enable input PU GPIO42 GPIO41 IO B14 Y4 AA1 AD6 AE7 TESTMODE VCCQ FSOURCE SECU_EN XBOOT I I I I I A22 KCOL7 IO Keypad column 7 GPIO55 KCOL7 B22 KCOL6 IO Keypad column 6 GPIO56 KCOL6 A21 B21 C21 D21 A20 B20 C20 KCOL5 KCOL4 KCOL3 KCOL2 KCOL1 KCOL0 KROW7 IO IO IO IO IO IO IO Keypad column 5 Keypad column 4 Keypad column 3 Keypad column 2 Keypad column 1 Keypad column 0 Keypad row 7 GPIO57 KROW7 D20 KROW6 IO Keypad row 6 GPIO58 KROW6 A19 B19 C19 A18 B18 C18 KROW5 KROW4 KROW3 KROW2 KROW1 KROW0 IO IO IO IO IO IO Keypad row 5 Keypad row 4 Keypad row 3 Keypad row 2 Keypad row 1 Keypad row 0 GPIO43 PU/ PD PU/ PD PU/ PD PD PD PD SRCLKEN AN SRCLKEN A SRCLKEN AI AD11 SRCLKENAI PU TESTMODE enable input PD PD PU/ PD PU/ PD PU PU PU PU PU PU PU/ PD PU/ PD PU Keypad Interface IRDA_PDN CLKM4 PU PU PU PU PU PU PU PD PD External Interrupt Interface F24 F23 E25 E24 EINT0 EINT1 EINT2 EINT3 IO IO IO IO External interrupt 0 External interrupt 1 External interrupt 2 External interrupt 3 GPIO44 EINT3 E23 EINT4 IO External interrupt 4 GPIO45 EINT4 DRF_DAT A DRF_EN D23 EINT5 IO External interrupt 5 GPIO46 EINT5 EDICK D25 EINT6 IO External interrupt 6 GPIO47 EINT6 EDIWS D24 EINT7 IO External interrupt 7 GPIO48 EINT7 EDIDAT 23/599 IRQ2 CLKM3 PU PU PU PU/ PD PU/ PD PU/ PD PU/ PD PU/ PD PU PU PU PU PU PU PU PU MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 K17 MFIQ IO Interrupt to MCU GPIO66 :nFIQ CLKM7 PU/ PU PD External Memory Interface G24 G22 G25 H24 H23 J23 J24 K22 H25 J25 K23 K24 K25 L17 L23 L24 M25 N17 L25 M17 M23 M24 R25 ED0 ED1 ED2 ED3 ED4 ED5 ED6 ED7 ED8 ED9 ED10 ED11 ED12 ED13 ED14 ED15 ERD_B EWR_B ECS0_B ECS1_B ECS2_B ECS3_B EWAIT IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO N25 P24 P23 N22 T17 ECAS_B ERAS_B ECKE ED_CLK EADMUX IO IO IO O IO R17 P25 P17 EDQM1 EDQM0 EADV_B IO IO O N24 EC_CLK O T23 T22 T24 T25 U23 U24 U25 V23 V24 V25 W22 EA0 EA1 EA2 EA3 EA4 EA5 EA6 EA7 EA8 EA9 EA10 IO IO IO IO IO IO IO IO IO IO IO External memory data bus 0 External memory data bus 1 External memory data bus 2 External memory data bus 3 External memory data bus 4 External memory data bus 5 External memory data bus 6 External memory data bus 7 External memory data bus 8 External memory data bus 9 External memory data bus 10 External memory data bus 11 External memory data bus 12 External memory data bus 13 External memory data bus 14 External memory data bus 15 External memory read strobe External memory write strobe External memory chip select 0 External memory chip select 1 External memory chip select 2 External memory chip select 3 Flash, PSRAM and CellularRAM data ready MobileRAM column address MobileRAM row address MobileRAM clock enable MobileRAM clock PD GPIO65 EADMUX CLKM6 PU/ PD Flash, PSRAM and CellularRAM address valid Flash, PSRAM and CellularRAM clock External memory address bus 0 External memory address bus 1 External memory address bus 2 External memory address bus 3 External memory address bus 4 External memory address bus 5 External memory address bus 6 External memory address bus 7 External memory address bus 8 External memory address bus 9 External memory address bus 10 24/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 W23 W24 W25 Y23 Y24 Y25 AA23 AA24 AA25 AB24 AB25 AC23 AC24 AC25 AD24 AD25 EA11 EA12 EA13 EA14 EA15 EA16 EA17 EA18 EA19 EA20 EA21 EA22 EA23 EA24 EA25 EA26 IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO External memory address bus 11 External memory address bus 12 External memory address bus 13 External memory address bus 14 External memory address bus 15 External memory address bus 16 External memory address bus 17 External memory address bus 18 External memory address bus 19 External memory address bus 20 External memory address bus 21 External memory address bus 22 External memory address bus 23 External memory address bus 24 External memory address bus 25 External memory address bus 26 AD20 AE20 AE21 AD22 AC21 AD23 AE22 AE23 USB_XTALI USB_XTALO VSSCA_USB VSSCD_USB VRT VSS33_USB USB_DP USB_DM IO IO IO IO IO IO IO IO USB D+ Input/Output USB D- Input/Output B16 MCCM0 IO C16 MCDA0 IO D16 MCDA1 J16 GPIO64 EA26 CLKM5 SD Command/MS Bus State Output GPIO67 MC0CM0 GPIO68 MC0DA0 IO SD Serial Data IO 0/MS Serial Data IO SD Serial Data IO 1 GPIO69 MC0DA1 MCDA2 IO SD Serial Data IO 2 GPIO70 MC0DA2 C15 MCDA3 IO SD Serial Data IO 3 GPIO71 MC0DA3 D15 MCCK IO GPIO72 MC0CK J15 MCPWRON IO SD Serial Clock/MS Serial Clock Output SD Power On Control Output GPIO73 C14 MCWP IO SD Write Protect Input GPIO74 MC0PWR ON MC0WP D14 MCINS IO SD Card Detect Input GPIO75 MC0INS C25 C24 C23 URXD1 UTXD1 UCTS1 IO IO IO UART 1 receive data UART 1 transmit data UART 1 clear to send GPIO49 UCTS1 UCTS2 B25 URTS1 IO UART 1 request to send GPIO50 URTS1 URTS2 PU/ PD USB Interface Memory Card Interface TDMA_C K TDMA_D 1 TDMA_D 0 TDMA_FS CLKM8 CLKM9 PU/ PD PU/ PD PU/ PD PU/ PD PU/ PD PU/ PD PU/ PD PU/ PD PU/ PD PU PU PU PU PU PU PU PU PU UART/IrDA Interface PU 25/599 PU/ PU PD PU/ MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 PD PU/ PD PU/ PD PU/ PD PU/ PD A24 URXD2 IO UART 2 receive data GPIO51 URXD2 UCTS3 B24 UTXD2 IO UART 2 transmit data GPIO52 UTXD2 URTS3 A23 URXD3 IO UART 3 receive data GPIO53 URXD3 B23 UTXD3 IO UART 3 transmit data GPIO54 UTXD3 IRDA_RX D IRDA_TX D D18 DAICLK IO DAI clock output GPIO59 DAICLK A17 DAIPCMOUT IO DAI pcm data out GPIO60 B17 DAIPCMIN IO DAI pcm data input GPIO61 C17 DAIRST IO DAI reset signal input GPIO62 DAIPCMO UT DAIPCMI N DAIRST D17 DAISYNC IO DAI frame synchronization signal output GPIO63 DAISYNC AA2 CMRST IO CMOS sensor reset signal output GPIO0 CMRST AA3 CMPDN IO CMOS sensor power down control GPIO1 CMPDN AB3 CMVREF IO Sensor vertical reference signal input GPIO2 CMVREF TBTXEN AB2 CMHREF IO GPIO3 CMHREF TBTXFS AA4 CMPCLK IO Sensor horizontal reference signal input CMOS sensor pixel clock input GPIO4 CMPCLK TBRXEN AB6 CMMCLK IO CMOS sensor master clock output GPIO5 CMMCLK TBRXFS AC2 CMDAT7 IO CMOS sensor data input 7 GPIO6 CMDAT7 D1ICK AC3 CMDAT6 IO CMOS sensor data input 6 GPIO7 CMDAT6 D1ID AC1 CMDAT5 IO CMOS sensor data input 5 GPIO8 CMDAT5 D1IMS AD1 CMDAT4 IO CMOS sensor data input 4 GPIO9 CMDAT4 D2ICK AE2 CMDAT3 IO CMOS sensor data input 3 GPIO10 CMDAT3 D2ID AD3 CMDAT2 IO CMOS sensor data input 2 GPIO11 CMDAT2 D2IMS AD4 CMDAT1 IO CMOS sensor data input 1 GPIO12 CMDAT1 D2_TID0 AE3 CMDAT0 IO CMOS sensor data input 0 GPIO13 CMDAT0 D2_TID1 AC4 CMFLASH IO GPIO14 CMFLASH D2_TID2 J1 AU_MOUTL O PU PU PU PU Digital Audio Interface PU/ PD PU/ PD PU/ PD PU/ PD PU/ PD PD PU/ PD PU/ PD PU/ PD PU/ PD PU/ PD PU/ PD PU/ PD PU/ PD PU/ PD PU/ PD PU/ PD PU/ PD PU/ PD PU/ PD PU/ PD PD PD PD PD PD CMOS Sensor Interface CLKM0 DSP_GPO 0 DSP_GPO 1 D1_TID0 D1_TID1 PD PD PD PD PD PD PD PD PD PD PD PD PD PD Analog Interface Audio analog output left channel 26/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 J2 K4 K3 K2 K1 L2 M2 M1 N1 N2 N3 N4 P1 AU_MOUTR AU_FMINL AU_FMINR AU_OUT0_N AU_OUT0_P AU_MICBIAS _P AU_MICBIAS _N AU_VREF_N AU_VREF_P AU_VIN0_P AU_VIN0_N AU_VIN1_N AU_VIN1_P BDLAQP P2 BDLAQN I R1 BDLAIN I R2 BDLAIP I T3 T4 U2 U4 V2 U1 U3 V1 W3 V3 V4 APC AUXADIN0 AUXADIN1 AUXADIN2 AUXADIN3 AUX_REF XP XM YP YM AFC I I I I I I I I I I O W2 AFC_BYP O B1 C2 C1 E3 F2 C12 D11 A11 C11 B11 BATDET VRF_SENSE VRF VTCXO VREF VIBRATOR LED VCORE VCORE_FB BAT_BACKU P VA VM VM_SENSE I I I I I O O I I I L1 F1 A9 D10 O I I O O O Audio analog output right channel FM radio analog input left channel FM radio analog input right channel Earphone 0 amplifier output (-) Earphone 0 amplifier output (+) Microphone bias supply (+) O Microphone bias supply (-) O O I I I I I Audio reference voltage (-) Audio reference voltage (+) Microphone 0 amplifier input (+) Microphone 0 amplifier input (-) Microphone 1 amplifier input (-) Microphone 1 amplifier input (+) Quadrature input (Q+) baseband codec downlink Quadrature input (Q-) baseband codec downlink In-phase input (I+) baseband codec downlink In-phase input (I-) baseband codec downlink Automatic power control DAC output Auxiliary ADC input 0 Auxiliary ADC input 1 Auxiliary ADC input 2 Auxiliary ADC input 3 Auxiliary ADC reference voltage input Automatic frequency control DAC output Automatic frequency control DAC bypass capacitance I I 27/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 C10 D8 II I A7 VCAM_D VCAM_A_SE NSE VCAM_A C8 A6 C7 A5 C5 C6 D5 A4 B4 C4 A3 B3 C3 A2 B2 VBT VIO VUSB VSIM SIO PWRKEY ISENSE VMSEL GATEDRV CHRIN SCLK BATSENSE SRST RESET RSTCAP I I I I IO I I I I I I I O I IO Y1 SYSCLK I A14 A15 B13 XIN XOUT BBWAKEUP I O IO H3 AB7 AB20 Y22 F22 J14 AB23 VDDK VDDK VDDK VDDK VDDK VDDK VDD33_EMI V22 VDD33_EMI R22 VDD33_EMI M22 VDD33_EMI J22 VDD33_EMI AD2 AB13 AB17 AC22 AB21 D13 VDD33_CAM VDD33_LCD VDD33_LCD VDD33_USB VDDC_USB VDD33_MC I VCXO Interface 13MHz or 26MHz system clock input RTC Interface 32.768 KHz crystal input 32.768 KHz crystal output Baseband power on/off control Supply Voltages Supply voltage of internal logic Supply voltage of internal logic Supply voltage of internal logic Supply voltage of internal logic Supply voltage of internal logic Supply voltage of internal logic Supply voltage of memory interface driver Supply voltage of memory interface driver Supply voltage of memory interface driver Supply voltage of memory interface driver Supply voltage of memory interface driver 28/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 H4 VDD33 AB9 VDD33 E22 VDD33 D19 VDD33 F4 VSS33 Y3 VSS33 AB5 VSS33 AB11 VSS33 U15 VSS33 AC20 VSS33 AE24 VSS33 AA22 VSS33 U22 VSS33 P22 VSS33 L22 VSS33 H22 VSS33 C22 VSS33 A16 VSS33 A13 VSS33 L9 VSS33 L11 VSS33 L12 VSS33 L13 VSS33 L14 VSS33 L15 VSS33 Supply voltage of drivers except memory interface, USB and MS/MMC/SD Supply voltage of drivers except memory interface, USB and MS/MMC/SD Supply voltage of drivers except memory interface, USB and MS/MMC/SD Supply voltage of drivers except memory interface, USB and MS/MMC/SD Ground of drivers except memory interface, USB and MS/MMC/SD Ground of drivers except memory interface, USB and MS/MMC/SD Ground of drivers except memory interface, USB and MS/MMC/SD Ground of drivers except memory interface, USB and MS/MMC/SD Ground of drivers except memory interface, USB and MS/MMC/SD Ground of drivers except memory interface, USB and MS/MMC/SD Ground of drivers except memory interface, USB and MS/MMC/SD Ground of drivers except memory interface, USB and MS/MMC/SD Ground of drivers except memory interface, USB and MS/MMC/SD Ground of drivers except memory interface, USB and MS/MMC/SD Ground of drivers except memory interface, USB and MS/MMC/SD Ground of drivers except memory interface, USB and MS/MMC/SD Ground of drivers except memory interface, USB and MS/MMC/SD Ground of drivers except memory interface, USB and MS/MMC/SD Ground of drivers except memory interface, USB and MS/MMC/SD Ground of drivers except memory interface, USB and MS/MMC/SD Ground of drivers except memory interface, USB and MS/MMC/SD Ground of drivers except memory interface, USB and MS/MMC/SD Ground of drivers except memory interface, USB and MS/MMC/SD Ground of drivers except memory interface, USB and MS/MMC/SD Ground of drivers except memory interface, USB and MS/MMC/SD 29/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 M9 VSS33 M11 VSS33 M15 VSS33 N11 VSS33 N13 VSS33 N15 VSS33 P9 VSS33 P11 VSS33 P15 VSS33 R9 VSS33 R11 VSS33 R12 VSS33 R13 VSS33 R14 VSS33 R15 VSS33 T9 VSS33 W1 Y2 B15 AVCC12_PLL AVSS12_PLL VRTC Ground of drivers except memory interface, USB and MS/MMC/SD Ground of drivers except memory interface, USB and MS/MMC/SD Ground of drivers except memory interface, USB and MS/MMC/SD Ground of drivers except memory interface, USB and MS/MMC/SD Ground of drivers except memory interface, USB and MS/MMC/SD Ground of drivers except memory interface, USB and MS/MMC/SD Ground of drivers except memory interface, USB and MS/MMC/SD Ground of drivers except memory interface, USB and MS/MMC/SD Ground of drivers except memory interface, USB and MS/MMC/SD Ground of drivers except memory interface, USB and MS/MMC/SD Ground of drivers except memory interface, USB and MS/MMC/SD Ground of drivers except memory interface, USB and MS/MMC/SD Ground of drivers except memory interface, USB and MS/MMC/SD Ground of drivers except memory interface, USB and MS/MMC/SD Ground of drivers except memory interface, USB and MS/MMC/SD Ground of drivers except memory interface, USB and MS/MMC/SD Supply voltage for Real Time Clock Analog Supplies J4 K9 AVDD28_MB UF AVSS28_MBU F AVDD28_BUF L3 L4 AVSS28_BUF AVDD28_AFE M3 AGND28_AFE N9 P4 AVSS28_AFE AGND28_RFE P3 AVSS28_GSM RFTX J3 Supply Voltage for Audio band section GND for Audio band section Supply voltage for voice band transmit section GND for voice band transmit section Supply voltage for voice band receive section GND reference voltage for voice band section GND for voice band receive section GND reference voltage for baseband section, APC, AFC and AUXADC GND for baseband transmit section 30/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 R3 T2 AVDD28_GS MRFTX AVSS28_RFE T1 AVDD28_RFE D1 D3 E4 E2 E1 F3 D12 A12 A10 VBAT_VRF AGND_VRF GND_LDOS VBAT_VA VBAT_VA AGND_VA GND_DRV GND_VCORE VBAT_VCOR E VBAT_LDOS1 VBAT_LDOS1 VBAT_LDOS2 GND_LDOS VBAT_LDOS2 VBAT_LDOS3 GND_LDOS GND_LDOS B10 B9 B8 D7 B7 B6 D6 D9 Supply voltage for baseband transmit section GND for baseband receive section, APC, AFC and AUXADC Supply voltage for baseband receive section, APC, AFC and AUXADC Table 2 Pin Descriptions (Bolded types are functions at reset) 31/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 2.5 Power Description BALL NAME B1 C2 C1 D1 D3 E4 E3 E2 F1 E1 F2 F3 G4 F4 G3 G2 G1 H1 H3 H2 H4 J4 J2 J3 J1 K3 K4 K9 K2 K1 L3 L2 L1 L4 M2 M1 M3 N1 N2 N3 N4 N9 P3 P4 R3 BATDET VRF_SENSE VRF VBAT_VRF AGND_VRF GND_LDOS VTCXO VBAT_VA VA VBAT_VA VREF AGND_VA JTRST_B VSS33 JTCK JTDI JTMS JTDO VDDK JRTCK VDD33 AVDD28_MBUF AU_MOUTR AVSS28_MBUF AU_MOUTL AU_FMINR AU_FMINL AVDD28_BUF AU_OUT0_N AU_OUT0_P AVSS28_BUF AU_MICBIAS_P AU_MICBIAS_N AVDD28_AFE AU_VREF_N AU_VREF_P AGND28_AFE AU_VIN0_P AU_VIN0_N AU_VIN1_N AU_VIN1_P AVSS28_AFE AVSS28_GSMRFTX AGND28_RFE AVDD28_GSMRFTX IO SUPPLY IO GND CORE SUPPLY CORE GND VDD33 VSS33 VDDK VSS33 VDD33 VDD33 VDD33 VDD33 VSS33 VSS33 VSS33 VSS33 VDDK VDDK VDDK VDDK VSS33 VSS33 VSS33 VSS33 VDD33 VSS33 VDDK VSS33 32/599 REMARK MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 P1 P2 R1 R2 T3 T1 U1 T4 U2 T2 U3 U4 V1 V2 V3 V4 W3 W2 W1 Y1 Y2 Y3 Y4 AA1 AA2 AA3 AB3 AB2 AA4 AB6 AC2 AC3 AC1 AD2 AD1 AE2 AD3 AD4 AE3 AC4 AB7 AE4 AD5 AC5 AE5 AB5 AD6 AE7 AE6 BDLAQP BDLAQN BDLAIN BDLAIP APC AVDD28_RFE AUX_REF AUXADIN0 AUXADIN1 AVSS28_RFE XP AUXADIN2 XM AUXADIN3 YM AFC YP AFC_BYP AVCC12_PLL SYSCLK AVSS12_PLL VSS33 VCCQ FSOURCE CMRST CMPDN CMVREF CMHREF CMPCLK CMMCLK CMDAT7 CMDAT6 CMDAT5 VDD33_CAM CMDAT4 CMDAT3 CMDAT2 CMDAT1 CMDAT0 CMFLASH VDDK SCL SDA PWM2 PWM3 VSS33 SECU_EN XBOOT BPI_BUS0 AVCC12_PLL AVSS12_PLL AVCC12_PLL AVSS12_PLL VDD33_CAM VDD33_CAM VDD33_CAM VDD33_CAM VDD33_CAM VDD33_CAM VDD33_CAM VDD33_CAM VDD33_CAM VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VDDK VDDK VDDK VDDK VDDK VDDK VDDK VDDK VDDK VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VDD33_CAM VDD33_CAM VDD33_CAM VDD33_CAM VDD33_CAM VDD33_CAM VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VDDK VDDK VDDK VDDK VDDK VDDK VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VDD33_CAM VDD33_CAM VDD33_CAM VDD33_CAM VSS33 VSS33 VSS33 VSS33 VDDK VDDK VDDK VDDK VSS33 VSS33 VSS33 VSS33 VDD33 VDD33 VDD33 VSS33 VSS33 VSS33 VDDK VDDK VDDK VSS33 VSS33 VSS33 33/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 AD7 AC7 AC6 AE8 AD8 AC8 AB8 AE9 AB9 AD9 AC9 AE10 AD10 AC10 AB10 U10 AE11 AD11 AB11 AC11 U11 AD12 AE12 AC12 AB12 U12 AE13 AC13 AD13 AB13 U13 AE14 AD14 AC14 AB14 U14 AE15 AD15 AC15 U15 AB15 AE16 AD16 AC16 AB16 U16 AE17 AD17 AC17 BPI_BUS1 BPI_BUS2 BPI_BUS3 BPI_BUS4 BPI_BUS5 BPI_BUS6 BPI_BUS7 BPI_BUS8 VDD33 BPI_BUS9 BSI_CS0 BSI_DATA BSI_CLK PWM0 PWM1 SRCLKENAN SRCLKENA SRCLKENAI VSS33 LSCK LSA0 LSDA LSCE0B LSCE1B LPCE1B LPCE0B LPTE LRSTB LRDB VDD33_LCD LPA0 LWRB NLD17 NLD16 NLD15 NLD14 NLD13 NLD12 NLD11 VSS33 NLD10 NLD9 NLD8 NLD7 NLD6 NLD5 NLD4 NLD3 NLD2 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VDDK VDDK VDDK VDDK VDDK VDDK VDDK VDDK VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VDDK VDDK VDDK VDDK VDDK VDDK VDDK VDDK VDDK VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VDD33_LCD VDD33_LCD VDD33_LCD VDD33_LCD VDD33_LCD VDD33_LCD VDD33_LCD VDD33_LCD VDD33_LCD VDD33_LCD VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VDDK VDDK VDDK VDDK VDDK VDDK VDDK VDDK VDDK VDDK VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VDD33_LCD VDD33_LCD VDD33_LCD VDD33_LCD VDD33_LCD VDD33_LCD VDD33_LCD VDD33_LCD VDD33_LCD VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VDDK VDDK VDDK VDDK VDDK VDDK VDDK VDDK VDDK VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VDD33_LCD VDD33_LCD VDD33_LCD VDD33_LCD VDD33_LCD VDD33_LCD VDD33_LCD VDD33_LCD VDD33_LCD VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VDDK VDDK VDDK VDDK VDDK VDDK VDDK VDDK VDDK VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 34/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 AB17 AE18 AD18 AC18 AB18 AE19 AD19 AC19 AB19 AB20 AC20 AD20 AE20 AE21 AD22 AB21 AC21 AD23 AC22 AE22 AE23 AE24 AD25 AD24 AC25 AC24 AC23 AB25 AA22 AB24 AA25 AA24 AB23 AA23 Y25 Y22 Y24 Y23 W25 W24 V22 W23 W22 V25 V24 V23 U25 U24 U23 VDD33_LCD NLD1 NLD0 NRNB NCLE NALE NWEB NREB NCEB VDDK VSS33 USB_XTALI USB_XTALO VSSCA_USB VSSCD_USB VDDC_USB VRT VSS33_USB VDD33_USB USB_DP USB_DM VSS33 EA26 EA25 EA24 EA23 EA22 EA21 VSS33 EA20 EA19 EA18 VDD33_EMI EA17 EA16 VDDK EA15 EA14 EA13 EA12 VDD33_EMI EA11 EA10 EA9 EA8 EA7 EA6 EA5 EA4 VDD33_LCD VDD33_LCD VDD33_LCD VDD33_LCD VDD33_LCD VDD33_LCD VDD33_LCD VDD33_LCD VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VDDK VDDK VDDK VDDK VDDK VDDK VDDK VDDK VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VDD33_EMI VDD33_EMI VDD33_EMI VDD33_EMI VDD33_EMI VDD33_EMI VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VDDK VDDK VDDK VDDK VDDK VDDK VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VDD33_EMI VDD33_EMI VDD33_EMI VSS33 VSS33 VSS33 VDDK VDDK VDDK VSS33 VSS33 VSS33 VDD33_EMI VDD33_EMI VSS33 VSS33 VDDK VDDK VSS33 VSS33 VDD33_EMI VDD33_EMI VDD33_EMI VDD33_EMI VSS33 VSS33 VSS33 VSS33 VDDK VDDK VDDK VDDK VSS33 VSS33 VSS33 VSS33 VDD33_EMI VDD33_EMI VDD33_EMI VDD33_EMI VDD33_EMI VDD33_EMI VDD33_EMI VDD33_EMI VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VDDK VDDK VDDK VDDK VDDK VDDK VDDK VDDK VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 35/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 T25 U22 T24 T22 T23 T17 R25 R17 P25 P24 N25 R22 P17 N22 P22 N24 P23 N17 M25 M24 M23 M17 L25 L24 M22 L23 L17 K25 L22 K24 K23 J25 H25 K22 J24 J23 H23 H24 J22 G25 G22 G24 K17 G23 H22 F22 F25 F24 F23 EA3 VSS33 EA2 EA1 EA0 EADMUX EWAIT EDQM1 EDQM0 ERAS_B ECAS_B VDD33_EMI EADV_B ED_CLK VSS33 EC_CLK ECKE EWR_B ERD_B ECS3_B ECS2_B ECS1_B ECS0_B ED15 VDD33_EMI ED14 ED13 ED12 VSS33 ED11 ED10 ED9 ED8 ED7 ED6 ED5 ED4 ED3 VDD33_EMI ED2 ED1 ED0 MFIQ WATCHDOG VSS33 VDDK SYSRST_B EINT0 EINT1 VDD33_EMI VSS33 VDDK VSS33 VDD33_EMI VDD33_EMI VDD33_EMI VDD33_EMI VDD33_EMI VDD33_EMI VDD33_EMI VDD33_EMI VDD33_EMI VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VDDK VDDK VDDK VDDK VDDK VDDK VDDK VDDK VDDK VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VDD33_EMI VDD33_EMI VSS33 VSS33 VDDK VDDK VSS33 VSS33 VDD33_EMI VDD33_EMI VDD33_EMI VDD33_EMI VDD33_EMI VDD33_EMI VDD33_EMI VDD33_EMI VDD33_EMI VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VDDK VDDK VDDK VDDK VDDK VDDK VDDK VDDK VDDK VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VDD33_EMI VDD33_EMI VDD33_EMI VSS33 VSS33 VSS33 VDDK VDDK VDDK VSS33 VSS33 VSS33 VDD33_EMI VDD33_EMI VDD33_EMI VDD33_EMI VDD33_EMI VDD33_EMI VDD33_EMI VDD33_EMI VDD33_EMI VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VDDK VDDK VDDK VDDK VDDK VDDK VDDK VDDK VDDK VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VDD33_EMI VDD33_EMI VDD33_EMI VDD33_EMI VDD33_EMI VSS33 VSS33 VSS33 VSS33 VSS33 VDDK VDDK VDDK VDDK VDDK VSS33 VSS33 VSS33 VSS33 VSS33 VDD33 VDD33 VDD33 VSS33 VSS33 VSS33 VDDK VDDK VDDK VSS33 VSS33 VSS33 36/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 E25 E24 E23 D23 D25 D24 E22 C25 C24 C23 B25 A24 B24 A23 B23 C22 A22 B22 A21 B21 C21 D21 A20 B20 C20 D20 A19 D19 B19 C19 A18 B18 C18 D18 A17 B17 C17 A16 D17 B16 C16 D16 J16 C15 D15 J15 C14 J14 D14 EINT2 EINT3 EINT4 EINT5 EINT6 EINT7 VDD33 URXD1 UTXD1 UCTS1 URTS1 URXD2 UTXD2 URXD3 UTXD3 VSS33 KCOL7 KCOL6 KCOL5 KCOL4 KCOL3 KCOL2 KCOL1 KCOL0 KROW7 KROW6 KROW5 VDD33 KROW4 KROW3 KROW2 KROW1 KROW0 DAICLK DAIPCMOUT DAIPCMIN DAIRST VSS33 DAISYNC MCCM0 MCDA0 MCDA1 MCDA2 MCDA3 MCCK MCPWRON MCWP VDDK MCINS VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VDDK VDDK VDDK VDDK VDDK VDDK VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VDDK VDDK VDDK VDDK VDDK VDDK VDDK VDDK VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VDDK VDDK VDDK VDDK VDDK VDDK VDDK VDDK VDDK VDDK VDDK VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VDDK VDDK VDDK VDDK VDDK VDDK VDDK VDDK VDDK VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VDD33 VDD33_MC VDD33_MC VDD33_MC VDD33_MC VDD33_MC VDD33_MC VDD33_MC VDD33_MC VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VDDK VDDK VDDK VDDK VDDK VDDK VDDK VDDK VDDK VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VDD33_MC VSS33 VDDK VSS33 37/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 D13 B15 A15 A14 B13 B14 A13 C12 D12 D11 A12 A11 C11 A10 B11 A9 D10 B10 C10 B9 D9 D8 A7 C8 B8 A6 D7 C7 B7 A5 C5 C6 B6 D6 D5 A4 B4 C4 A3 B3 C3 A2 B2 L9 L11 L12 L13 L14 L15 VDD33_MC VRTC XOUT XIN BBWAKEUP TESTMODE VSS33 VIBRATOR GND_DRV LED GND_VCORE VCORE VCORE_FB VBAT_VCORE BAT_BACKUP VM VM_SENSE VBAT_LDOS1 VCAM_D VBAT_LDOS1 GND_LDOS VCAM_A_SENSE VCAM_A VBT VBAT_LDOS2 VIO GND_LDOS VUSB VBAT_LDOS2 VSIM SIO PWRKEY VBAT_LDOS3 GND_LDOS ISENSE VMSEL GATEDRV CHRIN SCLK \BATSENSE SRST RESET RSTCAP VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VRTC VRTC VRTC VRTC VSS33 VSS33 VSS33 VSS33 VDDK VDDK VDDK VDDK 38/599 VSS33 VSS33 VSS33 VSS33 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 M9 M11 M15 N11 N13 N15 P9 P11 P15 R9 R11 R12 R13 R14 R15 T9 VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 Table 3 Power Descriptions 39/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 3 Micro-Controller Unit Subsystem Figure 5 illustrates the block diagram of the Micro-Controller Unit Subsystem in MT6235.The subsystem utilizes a main 32-bit ARM926EJ-S RISC processor, which plays the role of the main bus master controlling the whole subsystem. The ARM926EJ-S RISC is equipped with instruction cache, instruction TCM, data cache, and data TCM. The size of instruction cache and data cache are both 16KB. The size of instruction TCM is 48KB. The size of data TCM is 80KB. If the requested content is found in TCM or in cache, no bus transaction is required. If the code cache hit rate is high enough, bus traffic can be effectively reduced and processor core performance maximized. The bus comprises of two-level system buses: Advanced High-Performance Bus (AHB) and Advanced Peripheral Bus (APB). All bus transactions originate from bus masters, while slaves can only respond to requests from bus masters. Before data transfer can be established, the bus master must ask for bus ownership, accomplished by request-grant handshaking protocol between masters and arbiters. Two levels of bus hierarchy are designed to provide optimum usage for different performance requirements. Specifically, AHB Bus, the main system bus, is tailored toward high-speed requirements and provides 32-bit data path with multiplex scheme for bus interconnections. The APB Bus, on the other hand, is designed to reduce interface complexity for lower data transfer rate, and so it is isolated from high bandwidth AHB Bus by APB Bridge. APB Bus supports 16-bit addressing and both 16-bit and 32-bit data paths. APB Bus is also optimized for minimal power consumption by turning off the clock when there is no APB bus activity. During operation, if the target slave is located on AHB Bus, the transaction is conducted directly on AHB Bus. However, if the target slave is a peripheral and is attached to the APB bus, then the transaction is conducted between AHB and APB bus through the use of APB Bridge. The MT6235 MCU subsystem supports only memory addressing method. Therefore all components are mapped onto the MCU 32-bit address space. A Memory Management Unit is employed to allow for a central decode scheme. The MMU generates appropriate selection signals for each memory-addressed module on the AHB Bus. In order to off-load the processor core, a DMA Controller is designated to act as a master and share the bus resources on AHB Bus to perform fast data movement between modules. This controller provides fourteen DMA channels. The Interrupt Controller provides a software interface to manipulate interrupt events; it can handle up to 50 interrupt sources asserted at the same time. In general, the controller generates 2 levels of interrupt requests, FIQ and IRQ, to the processor. A 64K Byte SRAM is provided as system memory for high-speed data access. For factory programming purposes, a Boot ROM module is also integrated. These two modules use the same Internal Memory Controller to connect to AHB Bus. External Memory Interface supports both 8-bit and 16-bit devices. This interface supports both synchronous and asynchronous components, such as Flash, SRAM, SDRAM and parallel LCD. This interface supports page and burst mode type of Flash, Cellular RAM, as well as high performance MobileRAM. Since AHB Bus is 32-bit wide, all data transfers are converted into several 8-bit or 16-bit cycles depending on the data width of the target device. 40/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 AHB Masters 48KB ITCM 80KB DTCM ARM926EJ-S 16KB ICACHE 16KB DCACHE Other AHB Masters (DMA , USB, ...) Graphic AHB Layer 1 AHB Layer 2 AHB Layer 3 EMI Controller AHB Layer 4 System RAM (64KB) System ROM AHB/APB Bridge LCD Controller AHB Slaves APB Bus APB APB Peripherals APB Peripherals Peripherals APB Slaves Figure 5 Block Diagram of the Micro-Controller Unit Subsystem in MT6235 3.1 3.1.1 Processor Core General Description The Micro-Controller Unit Subsystem in MT6235 uses the 32-bit ARM926EJ-S RISC processor that is based on the Von Neumann architecture with a single 32-bit data bus carrying both instructions and data. The memory interface of ARM926EJ-S is totally compliant with the AMBA based bus system, which allows direct connection to the AHB Bus. 3.2 3.2.1 Memory Management General Description The processor core of MT6235 supports only a memory addressing method for instruction fetch and data access. The core manages a 32-bit address space that has addressing capability of up to 4 GB. System RAM, System ROM, Registers, MCU Peripherals and external components are all mapped onto such 32-bit address space, as depicted in Figure 6. 41/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 BANK Base Address Description BANK0 0000_0000h EMI Band 0 / Boot Code BANK1 1000_0000h EMI Bank 1 BANK2 2000_0000h EMI Bank 2 BANK3 3000_0000h EMI Bank 3 4000_0000h System RAM BANK4 4800_0000h System ROM BANK5 5000_0000h TCM BANK6 6000_0000h USB 6100_0000h Virtual FIFO Slave BANK7 7000_0000h Reserved BANK8 8000_0000h APB Peripheral BANK9 9000_0000h LCD BANK10 A000_0000h CPU-DSP Share RAM1 A100_0000h CPU-DSP Share RAM2 A200_0000h DSP IDMA Port 1 A300_0000h DSP IDMA Port 2 BANK11 B000_0000h Reserved BANK12 C000_0000h Reserved BANK13 D000_0000h Reserved BANK14 E000_0000h Reserved BANK15 F000_0000h Reserved Figure 6 The Memory Layout of MT6235 The address space is organized into blocks of 256 MB each. The block number is uniquely selected by address line A31-A28 of the internal system bus. 3.2.1.1 External Access To allow external access, the MT6235 can output 27bits (A26-A0) of address lines along with 4 selection signals that correspond to the associated memory blocks. That is, MT6235 can support up to 4 MCU addressable external components. The data width of internal system bus is fixed at 32-bit wide, while the data width of the external components is either 16– bit or 8-bit. Since devices are usually available with varied operating grades, adaptive configurations for different applications are needed. MT6235 provides software programmable registers to configure their wait-states to adapt to different operating conditions. 3.2.1.2 Memory Re-mapping Mechanism To permit more flexible system configuration, a memory re-mapping mechanism is provided. The mechanism allows software program to swap BANK0 (ECS0#) and BANK1 (ECS1#) dynamically. Whenever the bit value of RM0 in register EMI_REMAP is changed, these two banks are swapped accordingly. Furthermore, it allows system to boot from System ROM as detailed in 3.2.1.3 Boot Sequence. 42/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 3.2.1.3 Boot Sequence Since the ARM926EJ-S core always starts to fetch instructions from the lowest memory address at 00000000h after system has been reset, the system is designed to have a dynamic mapping architecture capable of associating Boot Code, external Flash or external SRAM with the memory block 0000_0000h – 0fff_ffffh. By default, the Boot Code is mapped onto 0000_0000h – 0fff_ffffh after a system reset. In this special boot mode, External Memory Controller does not access external memory; instead, the EMI Controller send predefined Boot Code back to the ARM926EJ-S core, which instructs the processor to execute the program in System ROM. This configuration can be changed by programming bit value of RM1 in register EMI_REMAP directly. MT6235 system provides one boot up scheme: z Start up system of running codes from Boot Code for factory programming or NAND flash boot. 3.2.1.3.1 Boot Code The Boot Code is placed together with Memory Re-Mapping Mechanism in External Memory Controller, and comprises of just two words of instructions as shown below. A jump instruction leads the processor to run the code starting at address 48000000h where the System ROM is placed. ADDRESS 00000000h 00000004h BINARY CODE E51FF004h 48000000h ASSEMBLY LDR PC, 0x4 (DATA) 3.2.1.3.2 Factory Programming The configuration for factory programming is shown in Figure 7. Usually the Factory Programming Host connects with MT6235 via the UART interface. The download speed can be up to 921K bps while MCU is running at 26MHz. After the system has reset, the Boot Code guides the processor to run the Factory Programming software placed in System ROM. Then, MT6235 starts and polls the UART1 port until valid information is detected. The first information received on the UART1 is used to configure the chip for factory programming. The Flash downloader program is then transferred into System RAM or external SRAM. Further information is detailed in the MT6235 Software Programming Specification. UART MT6235 Factory Programming Host External Memory Interface FLASH Figure 7 System configuration required for factory programming 43/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 3.2.1.3.3 NAND Flash Booting If MT6235 cannot receive data from UART1 for a certain amount of time, the program in System ROM checks if any valid boot loader exists in NAND flash. If found, the boot loader code is copied from NAND flash to RAM (internal or external) and executed to start the real application software. If no valid boot loader can be found in NAND flash, MT6235 starts executing code in EMI bank0 memory. The whole boot sequence is shown in the following figure. Boot from System ROM Check UART input Y Receive from UART N Valid loader on NAND N Boot from EMI bank 0 Y Factory programming Copy loader from NAND to RAM Boot from loader in RAM Figure 8 Boot sequence 3.2.1.4 Little Endian Mode The MT6235 system always treats 32-bit words of memory in Little Endian format. In Little Endian mode, the lowest numbered byte in a word is stored in the least significant position, and the highest numbered byte in the most significant position. Byte 0 of the memory system is therefore connected to data lines 7 through 0. 3.3 3.3.1 Bus System General Description Two levels of bus hierarchy are employed in the Micro-Controller Unit Subsystem of MT6235. As depicted in Figure 5, AHB Bus and APB Bus serve as system backbone and peripheral buses, while an APB bridge connects these two buses. Both AHB and APB Buses operate at the same or half the clock rate of processor core. The APB Bridge is the only bus master residing on the APB bus. All APB slaves are mapped onto memory block MB8 in the MCU 32-bit addressing space. A central address decoder is implemented inside the bridge to generate select signals for individual peripherals. In addition, since the base address of each APB slave is associated with select signals, the address bus on APB contains only the value of offset address. 44/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 The maximum address space that can be allocated to a single APB slave is 64 KB, i.e. 16-bit address lines. The width of the data bus is mainly constrained to 16 bits to minimize the design complexity and power consumption while some use 32-bit data buses to accommodate more bandwidth. In the case where an APB slave needs large amount of transfers, the device driver can also request DMA channels to conduct a burst of data transfer. The base address and data width of each peripheral are listed in Table 4. Data Width Base Address Description Software Base ID 8001_0000h EFUSE Control 32 EFUSEC Base 8001_0000h Configuration Registers (Clock, Power Down, Version and Reset) 16 CONFG Base 8002_0000h General Purpose Inputs/Outputs 16 GPIO Base 8003_0000h Reset Generation Unit 16 RGU Base 8100_0000h External Memory Interface 32 EMI Base 8101_0000h Interrupt Controller 32 CIRQ Base 8102_0000h DMA Controller 32 DMA Base 8103_0000h UART 1 16 UART1 Base 8104_0000h UART 2 16 UART2 Base 8105_0000h UART 3 16 UART3 Base 8106_0000h General Purpose Timer 16 GPT Base 8107_0000h Reserved 16 Reserved 8108_0000h Keypad Scanner 16 KP Base 8109_0000h Pulse-Width Modulation Outputs 32 PWM Base 810a_0000h SIM Interface 16 SIM Base 810b_0000h Reserved 810c_0000h Real Time Clock 16 RTC Base 810d_0000h Secure Engine 32 SEJ Base 810e_0000h Bus Monitor 32 BM Base 810f_0000h IrDA 16 IRDA Base 8110_0000h I2C 16 I2C Base 8111_0000h MS/SD Controller 32 MSDC Base 8112_0000h NAND Flash Interface 32 NFI Base 8113_0000h Reserved 8114_0000h Second MS/SD Interface 16 MSDC2 Base 8200_0000h TDMA Timer 32 TDMA Base 8201_0000h Base-Band Serial Interface 32 BSI Base 8202_0000h Base-Band Parallel Interface 16 BPI Base 8203_0000h Automatic Frequency Control Unit 16 AFC Base 8204_0000h Automatic Power Control Unit 32 APC Base 8205_0000h Auxiliary ADC Unit 16 AUXADC Base 8206_0000h Divider/Modulus Coprocessor 32 DIVIDER Base 45/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 8207_0000h Frame Check Sequence 16 FCS Base 8208_0000h GPRS Cipher Unit 32 GCU Base 8209_0000h CSD Format Conversion Coprocessor 32 CSD_ACC Base 820a_0000h MCU-DSP Shared Register 1 16 SHARE1 Base 820b_0000h IRDBG1 16 IRDBG Base 820c_0000h MCU-DSP Shared Register 2 16 SHARE2 Base 820d_0000h IRDBG2 16 IRDBG2 Bas3 820e_0000h DSP Patch Unit 16 PATCH Base 820f_0000h Audio Front End 16 AFE Base 8210_0000h Base-Band Front End 16 BFE Base 8211_0000h Reserved 8212_0000h Reserved 8300_0000h PLL / Clock square configuration 16 PLL_CLKSQ Base 8301_0000h Analog Chip Interface Controller 16 ACIF Base 8302_0000h Reserved 8400_0000h Graphics Memory Controller 32 GMC Base 8401_0000h 2D Accelerator 32 G2D Base 8402_0000h 2D Command Queue 32 GCMQ Base 8403_0000h Reserved 8404_0000h Reserved 8405_0000h Reserved 8406_0000h Reserved 8407_0000h Reserved 8408_0000h Reserved 8409_0000h Reserved 840a_0000h Reserved 840b_0000h Camera Interface 32 CAM Base 840c_0000h Reserved 840d_0000h Reserved 840e_0000h Capture Resizer 32 CRZ Base 840f_0000h Reserved 8410_0000h Reserved 8411_0000h Reserved Table 4 Register Base Addresses for MCU Peripherals REGISTER ADDRESS REGISTER NAME SYNONYM CONFG + 0000h Hardware Version Register HW_VER CONFG + 0004h Software Version Register SW_VER CONFG + 0008h Hardware Code Register HW_CODE 46/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 CONFG + 0404h APB Bus Control Register APB_CON CONFG + 0500h IRWIN Control Register IRWIN_CON Table 5 APB Bridge Register Map 3.3.2 Register Definitions CONFG+0000h Hardware Version Register Bit Name Type Reset 15 14 13 EXTP RO 8 12 11 10 9 MAJREV RO A HW_VERSION 8 7 6 5 4 3 MINREV 2 RO 0 1 0 RO 0 This register is used by software to determine the hardware version of the chip. The register contains a new value whenever each metal fix or major step is performed. All values are incremented by a step of 1. MINREV Minor Revision of the chip MAJREV Major Revision of the chip EXTP This field shows the existence of Hardware Code Register that presents the Hardware ID while the value is other than zero. CONFG+0004h Software Version Register Bit Name Type Reset 15 14 13 EXTP RO 8 12 11 10 9 MAJREV RO A SW_VERSION 8 7 6 5 4 3 MINREV RO 0 2 1 0 RO 0 This register is used by software to determine the software version used with this chip. All values are incremented by a step of 1. MINREV Minor Revision of the Software MAJREV Major Revision of the Software EXTP This field shows the existence of Software Code Register that presents the Software ID when the value is other than zero. CONFG+0008h Hardware Code Register Bit Name Type Reset 15 14 13 CODE3 RO 6 12 11 10 9 CODE2 RO 2 HW_CODE 8 7 6 5 CODE1 RO 3 4 3 2 1 CODE0 RO 5 0 This register presents the Hardware ID. CODE This version of chip is coded as 6235h. CONFG+0404h APB Bus Control Register Bit Name Type Reset 15 14 13 APB_CON 12 11 10 9 8 APBW APBW APBW APBW APBW 4 3 2 1 0 R/W R/W R/W R/W R/W 0 0 0 0 0 47/599 7 6 5 4 3 2 1 0 APBR APBR APBR APBR APBR 4 3 2 1 0 R/W R/W R/W R/W R/W 1 1 1 1 1 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 This register is used to control the timing of Read Cycle and Write Cycle on APB Bus. Note that APB Bridge 2 is different from other bridges: the access time is varied, and access is not complete until an acknowledge signal from APB slave is asserted. APBR0-APBR6 Read Access Time on APB Bus 0 1-Cycle Access 1 2-Cycle Access APBW0-APBW6 Write Access Time on APB Bus 0 1-Cycle Access 1 2-Cycle Access 3.4 3.4.1 Direct Memory Access General Description A generic DMA Controller is placed on Layer 2 AHB Bus to support fast data transfers and to off-load the processor. With this controller, specific devices on AHB or APB buses can benefit greatly from quick completion of data movement from or to memory modules such as Internal System RAM or External SRAM, excluding TCM. TCM is invisible for DMA engine.. Such Generic DMA Controller can also be used to connect any two devices other than memory module as long as they can be addressed in memory space. Figure 9 Variety Data Paths of DMA Transfers Up to fourteen channels of simultaneous data transfers are supported. Each channel has a similar set of registers to be configured to different scheme as desired. If more than fourteen devices are requesting the DMA resources at the same time, software based arbitration should be employed. Once the service candidate is decided, the responsible device driver should configure the Generic DMA Controller properly in order to conduct DMA transfers. Both Interrupt and Polling based schemes in handling the completion event are supported. The block diagram of such generic DMA Controller is illustrated in Figure 10. 48/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 Figure 10 Block Diagram of Direct memory Access Module 3.4.1.1 Full-Size & Half-Size DMA Channels There are three types of DMA channels in the DMA controller. The first one is called a full-size DMA channel, the second one is called a half-size DMA channel, and the last is Virtual FIFO DMA. Channels 1 through 3 are full-size DMA channels; channels 4 through 10 are half-size ones; and channels 11 through 14 are Virtual FIFO DMAs. The difference between the first two types of DMA channels is that both source and destination address are programmable in full-size DMA channels, but only the address of one side can be programmed in half-size DMA channel. In half-size channels, only either the source or destination address can be programmed, while the addresses of the other side is preset. Which preset address is used depends on the setting of MAS in DMA Channel Control Register. Refer to the Register Definition section for more detail. 3.4.1.2 Ring Buffer & Double Buffer Memory Data Movement DMA channels 1 through 10 support ring-buffer and double-buffer memory data movement. This can be achieved by programming DMA_WPPT and DMA_WPTO, as well as setting WPEN in DMA_CON register to enable. Figure 11 illustrates how this function works. Once the transfer counter reaches the value of WPPT, the next address jumps to the WPTO address after completing the WPPT data transfer. Note that only one side can be configured as ring-buffer or double-buffer memory, and this is controlled by WPSD in DMA_CON register. 49/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 Figure 11 Ring Buffer and Double Buffer Memory Data Movement 3.4.1.3 Unaligned Word Access The address of word access on AHB bus must be aligned to word boundary, or the 2 LSB is truncated to 00b. If programmers do not notice this, it may cause an incorrect data fetch. In the case where data is to be moved from unaligned addresses to aligned addresses, the word is usually first split into four bytes and then moved byte by byte. This results in four read and four write transfers on the bus. To improve bus efficiency, unaligned-word access is provided in DMA4~10. While this function is enabled, DMAs move data from unaligned address to aligned address by executing four continuous byte-read access and one word-write access, reducing the number of transfers on the bus by three. Figure 12 Unaligned Word Accesses 50/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 3.4.1.4 Virtual FIFO DMA Virtual FIFO DMA is used to ease UART control. The difference between the Virtual FIFO DMAs and the ordinary DMAs is that Virtual FIFO DMA contains additional FIFO controller. The read and write pointers are kept in the Virtual FIFO DMA. During a read from the FIFO, the read pointer points to the address of the next data. During a write to the FIFO, the write pointer moves to the next address. If the FIFO is empty, a FIFO read is not allowed. Similarly, data is not written into the FIFO if the FIFO is full. Due to UART flow control requirements, an alert length is programmed. Once the FIFO Space is less than this value, an alert signal is issued to enable UART flow control. The type of flow control performed depends on the setting in UART. Each Virtual FIFO DMA can be programmed as RX or TX FIFO. This depends on the setting of DIR in DMA_CON register. If DIR is “0”(READ), it means TX FIFO. On the other hand, if DIR is “1”(WRITE), the Virtual FIFO DMA is specified as a RX FIFO. Virtual FIFO DMA provides an interrupt to MCU. This interrupt informs MCU that there is data in the FIFO, and the amount of data is over or under the value defined in DMA_COUNT register. With this, MCU does not need to poll DMA to know when data must be removed from or put into the FIFO. Note that Virtual FIFO DMAs cannot be used as generic DMAs, i.e. DMA1~10. Figure 13 Virtual FIFO DMA DMA number Address of Virtual FIFO Access Port Associated UART DMA11 6100_0000h UART1 RX / ALL UART TX DMA12 6100_0100h UART2 RX / ALL UART TX DMA13 6100_0200h UART3 RX / ALL UART TX DMA14 6100_0300h ALL UART TX Table 6 Virtual FIFO Access Port DMA number Type Ring Buffer Double Buffer Burst Mode DMA1 Full Size ● ● ● DMA2 Full Size ● ● ● 51/599 Unaligned Word Access MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 DMA3 Full Size ● ● ● DMA4 Half Size ● ● ● ● DMA5 Half Size ● ● ● ● DMA6 Half Size ● ● ● ● DMA7 Half Size ● ● ● ● DMA8 Half Size ● ● ● ● DMA9 Half Size ● ● ● ● DMA10 Half Size ● ● ● ● DMA11 Virtual FIFO ● DMA12 Virtual FIFO ● DMA13 Virtual FIFO ● DMA14 Virtual FIFO ● Table 7 Function List of DMA channels REGISTER ADDRESS REGISTER NAME SYNONYM DMA + 0000h DMA Global Status Register DMA_GLBSTA DMA + 0028h DMA Global Bandwidth Limiter Register DMA_GLBLIMITER DMA + 0100h DMA Channel 1 Source Address Register DMA1_SRC DMA + 0104h DMA Channel 1 Destination Address Register DMA1_DST DMA + 0108h DMA Channel 1 Wrap Point Address Register DMA1_WPPT DMA + 010Ch DMA Channel 1 Wrap To Address Register DMA1_WPTO DMA + 0110h DMA Channel 1 Transfer Count Register DMA1_COUNT DMA + 0114h DMA Channel 1 Control Register DMA1_CON DMA + 0118h DMA Channel 1 Start Register DMA1_START DMA + 011Ch DMA Channel 1 Interrupt Status Register DMA1_INTSTA DMA + 0120h DMA Channel 1 Interrupt Acknowledge Register DMA1_ACKINT DMA + 0124h DMA Channel 1 Remaining Length of Current Transfer DMA1_RLCT DMA + 0128h DMA Channel 1 Bandwidth Limiter Register DMA1_LIMITER DMA + 0200h DMA Channel 2 Source Address Register DMA2_SRC DMA + 0204h DMA Channel 2 Destination Address Register DMA2_DST DMA + 0208h DMA Channel 2 Wrap Point Address Register DMA2_WPPT DMA + 020Ch DMA Channel 2 Wrap To Address Register DMA2_WPTO DMA + 0210h DMA Channel 2 Transfer Count Register DMA2_COUNT DMA + 0214h DMA Channel 2 Control Register DMA2_CON DMA + 0218h DMA Channel 2 Start Register DMA2_START DMA + 021Ch DMA Channel 2 Interrupt Status Register DMA2_INTSTA DMA + 0220h DMA Channel 2 Interrupt Acknowledge Register DMA2_ACKINT DMA + 0224h DMA Channel 2 Remaining Length of Current Transfer DMA2_RLCT DMA + 0228h DMA Channel 2 Bandwidth Limiter Register DMA2_LIMITER 52/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 DMA + 0300h DMA Channel 3 Source Address Register DMA3_SRC DMA + 0304h DMA Channel 3 Destination Address Register DMA3_DST DMA + 0308h DMA Channel 3 Wrap Point Address Register DMA3_WPPT DMA + 030Ch DMA Channel 3 Wrap To Address Register DMA3_WPTO DMA + 0310h DMA Channel 3 Transfer Count Register DMA3_COUNT DMA + 0314h DMA Channel 3 Control Register DMA3_CON DMA + 0318h DMA Channel 3 Start Register DMA3_START DMA + 031Ch DMA Channel 3 Interrupt Status Register DMA3_INTSTA DMA + 0320h DMA Channel 3 Interrupt Acknowledge Register DMA3_ACKINT DMA + 0324h DMA Channel 3 Remaining Length of Current Transfer DMA3_RLCT DMA + 0328h DMA Channel 3 Bandwidth Limiter Register DMA3_LIMITER DMA + 0408h DMA Channel 4 Wrap Point Address Register DMA4_WPPT DMA + 040Ch DMA Channel 4 Wrap To Address Register DMA4_WPTO DMA + 0410h DMA Channel 4 Transfer Count Register DMA4_COUNT DMA + 0414h DMA Channel 4 Control Register DMA4_CON DMA + 0418h DMA Channel 4 Start Register DMA4_START DMA + 041Ch DMA Channel 4 Interrupt Status Register DMA4_INTSTA DMA + 0420h DMA Channel 4 Interrupt Acknowledge Register DMA4_ACKINT DMA + 0424h DMA Channel 4 Remaining Length of Current Transfer DMA4_RLCT DMA + 0428h DMA Channel 4 Bandwidth Limiter Register DMA4_LIMITER DMA + 042Ch DMA Channel 4 Programmable Address Register DMA4_PGMADDR DMA + 0508h DMA Channel 5 Wrap Point Address Register DMA5_WPPT DMA + 050Ch DMA Channel 5 Wrap To Address Register DMA5_WPTO DMA + 0510h DMA Channel 5 Transfer Count Register DMA5_COUNT DMA + 0514h DMA Channel 5 Control Register DMA5_CON DMA + 0518h DMA Channel 5 Start Register DMA5_START DMA + 051Ch DMA Channel 5 Interrupt Status Register DMA5_INTSTA DMA + 0520h DMA Channel 5 Interrupt Acknowledge Register DMA5_ACKINT DMA + 0524h DMA Channel 5 Remaining Length of Current Transfer DMA5_RLCT DMA + 0528h DMA Channel 5 Bandwidth Limiter Register DMA5_LIMITER DMA + 052Ch DMA Channel 5 Programmable Address Register DMA5_PGMADDR DMA + 0608h DMA Channel 6 Wrap Point Address Register DMA6_WPPT DMA + 060Ch DMA Channel 6 Wrap To Address Register DMA6_WPTO DMA + 0610h DMA Channel 6 Transfer Count Register DMA6_COUNT DMA + 0614h DMA Channel 6 Control Register DMA6_CON DMA + 0618h DMA Channel 6 Start Register DMA6_START DMA + 061Ch DMA Channel 6 Interrupt Status Register DMA6_INTSTA DMA + 0620h DMA Channel 6 Interrupt Acknowledge Register DMA6_ACKINT DMA + 0624h DMA Channel 6 Remaining Length of Current Transfer DMA6_RLCT 53/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 DMA + 0628h DMA Channel 6 Bandwidth Limiter Register DMA6_LIMITER DMA + 062Ch DMA Channel 6 Programmable Address Register DMA6_PGMADDR DMA + 0708h DMA Channel 7 Wrap Point Address Register DMA7_WPPT DMA + 070Ch DMA Channel 7 Wrap To Address Register DMA7_WPTO DMA + 0710h DMA Channel 7 Transfer Count Register DMA7_COUNT DMA + 0714h DMA Channel 7 Control Register DMA7_CON DMA + 0718h DMA Channel 7 Start Register DMA7_START DMA + 071Ch DMA Channel 7 Interrupt Status Register DMA7_INTSTA DMA + 0720h DMA Channel 7 Interrupt Acknowledge Register DMA7_ACKINT DMA + 0724h DMA Channel 7 Remaining Length of Current Transfer DMA7_RLCT DMA + 0728h DMA Channel 7 Bandwidth Limiter Register DMA7_LIMITER DMA + 072Ch DMA Channel 7 Programmable Address Register DMA7_PGMADDR DMA + 0808h DMA Channel 8 Wrap Point Address Register DMA8_WPPT DMA + 080Ch DMA Channel 8 Wrap To Address Register DMA8_WPTO DMA + 0810h DMA Channel 8 Transfer Count Register DMA8_COUNT DMA + 0814h DMA Channel 8 Control Register DMA8_CON DMA + 0818h DMA Channel 8 Start Register DMA8_START DMA + 081Ch DMA Channel 8 Interrupt Status Register DMA8_INTSTA DMA + 0820h DMA Channel 8 Interrupt Acknowledge Register DMA8_ACKINT DMA + 0824h DMA Channel 8 Remaining Length of Current Transfer DMA8_RLCT DMA + 0828h DMA Channel 8 Bandwidth Limiter Register DMA8_LIMITER DMA + 082Ch DMA Channel 8 Programmable Address Register DMA8_PGMADDR DMA + 0908h DMA Channel 9 Wrap Point Address Register DMA9_WPPT DMA + 090Ch DMA Channel 9 Wrap To Address Register DMA9_WPTO DMA + 0910h DMA Channel 9 Transfer Count Register DMA9_COUNT DMA + 0914h DMA Channel 9 Control Register DMA9_CON DMA + 0918h DMA Channel 9 Start Register DMA9_START DMA + 091Ch DMA Channel 9 Interrupt Status Register DMA9_INTSTA DMA + 0920h DMA Channel 9 Interrupt Acknowledge Register DMA9_ACKINT DMA + 0924h DMA Channel 9 Remaining Length of Current Transfer DMA9_RLCT DMA + 0928h DMA Channel 9 Bandwidth Limiter Register DMA9_LIMITER DMA + 092Ch DMA Channel 9 Programmable Address Register DMA9_PGMADDR DMA + 0A08h DMA Channel 10 Wrap Point Address Register DMA10_WPPT DMA + 0A0Ch DMA Channel 10 Wrap To Address Register DMA10_WPTO DMA + 0A10h DMA Channel 10 Transfer Count Register DMA10_COUNT DMA + 0A14h DMA Channel 10 Control Register DMA10_CON DMA + 0A18h DMA Channel 10 Start Register DMA10_START DMA + 0A1Ch DMA Channel 10 Interrupt Status Register DMA10_INTSTA DMA + 0A20h DMA Channel 10 Interrupt Acknowledge Register DMA10_ACKINT 54/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 DMA + 0A24h DMA Channel 10 Remaining Length of Current Transfer DMA10_RLCT DMA + 0A28h DMA Channel 10 Bandwidth Limiter Register DMA10_LIMITER DMA + 0A2Ch DMA Channel 10 Programmable Address Register DMA10_PGMADDR DMA + 0B10h DMA Channel 11 Transfer Count Register DMA11_COUNT DMA + 0B14h DMA Channel 11 Control Register DMA11_CON DMA + 0B18h DMA Channel 11 Start Register DMA11_START DMA + 0B1Ch DMA Channel 11 Interrupt Status Register DMA11_INTSTA DMA + 0B20h DMA Channel 11 Interrupt Acknowledge Register DMA11_ACKINT DMA + 0B28h DMA Channel 11 Bandwidth Limiter Register DMA11_LIMITER DMA + 0B2Ch DMA Channel 11 Programmable Address Register DMA11_PGMADDR DMA + 0B30h DMA Channel 11 Write Pointer DMA11_WRPTR DMA + 0B34h DMA Channel 11 Read Pointer DMA11_RDPTR DMA + 0B38h DMA Channel 11 FIFO Count DMA11_FFCNT DMA + 0B3Ch DMA Channel 11 FIFO Status DMA11_FFSTA DMA + 0B40h DMA Channel 11 Alert Length DMA11_ALTLEN DMA + 0B44h DMA Channel 11 FIFO Size DMA11_FFSIZE DMA + 0C10h DMA Channel 12 Transfer Count Register DMA12_COUNT DMA + 0C14h DMA Channel 12 Control Register DMA12_CON DMA + 0C18h DMA Channel 12 Start Register DMA12_START DMA + 0C1Ch DMA Channel 12 Interrupt Status Register DMA12_INTSTA DMA + 0C20h DMA Channel 12 Interrupt Acknowledge Register DMA12_ACKINT DMA + 0C28h DMA Channel 12 Bandwidth Limiter Register DMA12_LIMITER DMA + 0C2Ch DMA Channel 12 Programmable Address Register DMA12_PGMADDR DMA + 0C30h DMA Channel 12 Write Pointer DMA12_WRPTR DMA + 0C34h DMA Channel 12 Read Pointer DMA12_RDPTR DMA + 0C38h DMA Channel 12 FIFO Count DMA12_FFCNT DMA + 0C3Ch DMA Channel 12 FIFO Status DMA12_FFSTA DMA + 0C40h DMA Channel 12 Alert Length DMA12_ALTLEN DMA + 0C44h DMA Channel 12 FIFO Size DMA12_FFSIZE DMA + 0D10h DMA Channel 13 Transfer Count Register DMA13_COUNT DMA + 0D14h DMA Channel 13 Control Register DMA13_CON DMA + 0D18h DMA Channel 13 Start Register DMA13_START DMA + 0D1Ch DMA Channel 13 Interrupt Status Register DMA13_INTSTA DMA + 0D20h DMA Channel 13 Interrupt Acknowledge Register DMA13_ACKINT DMA + 0D28h DMA Channel 13 Bandwidth Limiter Register DMA13_LIMITER DMA + 0D2Ch DMA Channel 13 Programmable Address Register DMA13_PGMADDR DMA + 0D30h DMA Channel 13 Write Pointer DMA13_WRPTR DMA + 0D34h DMA Channel 13 Read Pointer DMA13_RDPTR DMA + 0D38h DMA Channel 13 FIFO Count DMA13_FFCNT 55/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 DMA + 0D3Ch DMA Channel 13 FIFO Status DMA13_FFSTA DMA + 0D40h DMA Channel 13 Alert Length DMA13_ALTLEN DMA + 0D44h DMA Channel 13 FIFO Size DMA13_FFSIZE DMA + 0E10h DMA Channel 14 Transfer Count Register DMA14_COUNT DMA + 0E14h DMA Channel 14 Control Register DMA14_CON DMA + 0E18h DMA Channel 14 Start Register DMA14_START DMA + 0E1Ch DMA Channel 14 Interrupt Status Register DMA14_INTSTA DMA + 0E20h DMA Channel 14 Interrupt Acknowledge Register DMA14_ACKINT DMA + 0E28h DMA Channel 14 Bandwidth Limiter Register DMA14_LIMITER DMA + 0E2Ch DMA Channel 14 Programmable Address Register DMA14_PGMADDR DMA + 0E30h DMA Channel 14 Write Pointer DMA14_WRPTR DMA + 0E34h DMA Channel 14 Read Pointer DMA14_RDPTR DMA + 0E38h DMA Channel 14 FIFO Count DMA14_FFCNT DMA + 0E3Ch DMA Channel 14 FIFO Status DMA14_FFSTA DMA + 0E40h DMA Channel 14 Alert Length DMA14_ALTLEN DMA + 0E44h DMA Channel 14 FIFO Size DMA14_FFSIZE Table 8 DMA Controller Register Map 3.4.2 Register Definitions Register programming tips: z Start registers shall be cleared, when associated channels are being programmed. z PGMADDR, i.e. programmable address, only exists in half-size DMA channels. If DIR in Control Register is high, PGMADDR represents Destination Address. Conversely, If DIR in Control Register is low, PGMADDR represents Source Address. z Functions of ring-buffer and double-buffer memory data movement can be activated on either source side or destination side by programming DMA_WPPT & and DMA_WPTO, as well as setting WPEN in DMA_CON register high. WPSD in DMA_CON register determines the activated side. DMA+0000h Bit 31 30 DMA Global Status Register 29 Name Type Reset Bit Name Type Reset 15 IT8 RO 0 14 RUN8 RO 0 13 IT7 RO 0 28 27 DMA_GLBSTA 26 25 24 23 22 21 20 19 18 RUN1 RUN1 RUN1 RUN1 RUN1 IT14 IT13 IT12 IT11 IT10 4 3 2 1 0 RO RO RO RO RO RO RO RO RO RO 0 0 0 0 0 0 0 0 0 0 12 11 10 9 8 7 6 5 4 3 2 RUN7 IT6 RUN6 IT5 RUN5 IT4 RUN4 IT3 RUN3 IT2 RUN2 RO RO RO RO RO RO RO RO RO RO RO 0 0 0 0 0 0 0 0 0 0 0 17 16 IT9 RUN9 RO 0 1 IT1 RO 0 RO 0 0 RUN1 RO 0 This register helps software program keep track of the global status of DMA channels. RUNN DMA channel n status 56/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 ITN 0 Channel n is stopped or has completed the transfer already. 1 Channel n is currently running. Interrupt status for channel n 0 No interrupt is generated. 1 An interrupt is pending and waiting for service. DMA+0028h Bit Name Type Reset Bit Name Type Reset 31 30 29 28 27 26 25 24 23 22 21 15 14 13 12 11 10 9 8 7 6 5 Please refer to the expression in DMAn_LIMITER for detailed note. DMA channels, from 1 to 14. DMA+0n00h Bit Name Type Reset Bit Name Type Reset DMA_GLBLIMIT ER DMA Global Bandwidth limiter Register 20 19 4 3 GLBLIMITER WO 0 18 17 16 2 1 0 The value of DMA_GLBLIMITER is set to all DMA Channel n Source Address Register 31 30 29 28 27 26 25 15 14 13 12 11 10 9 24 23 SRC[31:16] R/W 0 8 7 SRC[15:0] R/W 0 DMAn_SRC 22 21 20 19 18 17 16 6 5 4 3 2 1 0 The above registers contain the base or current source address that the DMA channel is currently operating on. Writing to this register specifies the base address of transfer source for a DMA channel. Before programming these registers, the software program should make sure that STR in DMAn_START is set to 0; that is, the DMA channel is stopped and disabled completely. Otherwise, the DMA channel may run out of order. Reading this register returns the address value from which the DMA is reading. Note that n is from 1 to 3 and SRC can’t be TCM address. SRC SRC[31:0] specifies the base or current address of transfer source for a DMA channel, i.e. channel 1, 2 or 3. WRITE Base address of transfer source READ Address from which DMA is reading DMA+0n04h Bit Name Type Reset Bit Name Type Reset TCM is not accessible by DMA.. DMA Channel n Destination Address Register 31 30 29 28 27 26 25 15 14 13 12 11 10 9 24 23 DST[31:16] R/W 0 8 7 DST[15:0] R/W 0 57/599 DMAn_DST 22 21 20 19 18 17 16 6 5 4 3 2 1 0 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 The above registers contain the base or current destination address that the DMA channel is currently operating on.. Writing to this register specifies the base address of the transfer destination for a DMA channel. Before programming these registers, the software should make sure that STR in DMAn_START is set to ‘0’; that is, the DMA channel is stopped and disabled completely. Otherwise, the DMA channel may run out of order. Reading this register returns the address value to which the DMA is writing. Note that n is from 1 to 3 and DST can’t be TCM address. TCM is not accessible by DMA. DST DST[31:0] specifies the base or current address of transfer destination for a DMA channel, i.e. channel 1, 2 or 3. WRITE Base address of transfer destination. READ Address to which DMA is writing. DMA+0n08h Bit Name Type Reset Bit Name Type Reset DMA Channel n Wrap Point Count Register 31 30 29 28 27 26 25 15 14 13 12 11 10 9 24 23 8 7 WPPT[15:0] R/W 0 DMAn_WPPT 22 21 20 19 18 17 16 6 5 4 3 2 1 0 The above registers are to specify the transfer count required to perform before the jump point. This can be used to support ring buffer or double buffer style memory accesses. To enable this function, two control bits, WPEN and WPSD, in DMA control register must be programmed. See the following register description for more details. If the transfercounter in the DMA engine matches this value, an address jump occurs, and the next address is the address specified in DMAn_WPTO. Before programming these registers, the software should make sure that STR in DMAn_START is set to ‘0’, that is the DMA channel is stopped and disabled completely. Otherwise, the DMA channel may run out of order. To enable this function, WPEN in DMA_CON is set. Note that the total size of data specify in the wrap point count in a DMA channel is determined by LEN together with the SIZE in DMAn_CON, i.e. WPPT x SIZE. Note that n is from 1 to 10. WPPT WPPT[15:0] specifies the amount of the transfer count from start to jumping point for a DMA channel, i.e. channel 1 – 10. WRITE Wrap point transfer count. READ Value set by the programmer. DMA+0n0Ch Bit Name Type Reset Bit Name Type Reset DMA Channel n Wrap To Address Register 31 30 29 28 27 26 25 15 14 13 12 11 10 9 24 23 WPTO[31:16] R/W 0 8 7 WPTO[15:0] R/W 0 DMAn_WPTO 22 21 20 19 18 17 16 6 5 4 3 2 1 0 The above registers specify the address of the jump destination of a given DMA transfer to support ring buffer or double buffer style memory accesses. To enable this function, set the two control bits, WPEN and WPSD, in the DMA control register . See the following register description for more details. Before programming these registers, the software 58/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 should make sure that STR in DMAn_START is set to ‘0’, that is the DMA channel is stopped and disabled completely. Otherwise, the DMA channel may run out of order. To enable this function, WPEN in DMA_CON should be set. Note that n is from 1 to 10. WPTO WPTO[31:0] specifies the address of the jump point for a DMA channel, i.e. channel 1 – 10. WRITE Address of the jump destination. READ Value set by the programmer. DMA+0n10h Bit Name Type Reset Bit Name Type Reset DMA Channel n Transfer Count Register 31 30 29 28 27 26 25 24 15 14 13 12 11 10 9 8 DMAn_COUNT 23 22 21 20 19 18 17 16 7 6 5 4 3 2 1 0 LEN R/W 0 This register specifies the amount of total transfer count that the DMA channel is required to perform. Upon completion, the DMA channel generates an interrupt request to the processor while ITEN in DMAn_CON is set as ‘1’. Note that the total size of data being transferred by a DMA channel is determined by LEN together with the SIZE in DMAn_CON, i.e. LEN x SIZE. For virtual FIFO DMA, this register is used to configure the RX threshold and TX threshold. Interrupt is triggered while FIFO count >= RX threshold in RX path or FIFO count =< TX threshold in TX path. Note that ITEN bit in DMA_CON register shall be set, or no interrupt is issued. Note that n is from 1 to 14. LEN The amount of total transfer count DMA+0n14h Bit 31 Name Type Reset Bit 15 Name ITEN Type R/W Reset 0 DMA Channel n Control Register DMAn_CON 30 29 28 27 26 25 24 23 14 13 12 11 10 9 BURST R/W 0 8 7 22 MAS R/W 0 6 21 5 B2W R/W 0 20 19 18 17 16 DIR WPEN WPSD R/W R/W R/W 0 0 0 4 3 2 1 0 DRQ DINC SINC SIZE R/W R/W R/W R/W 0 0 0 0 This register contains all the available control schemes for a DMA channel that is ready for software programmer to configure. Note that all these fields cannot be changed while DMA transfer is in progress or an unexpected situation may occur. Note that n is from 1 to 14. SIZE Data size within the confine of a bus cycle per transfer. These bits confines the data transfer size between source and destination to the specified value for individual bus cycle. The size is in terms of byte and has maximum value of 4 bytes. It is mainly decided by the data width of a DMA master. 00 Byte transfer/1 byte 59/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 01 Half-word transfer/2 bytes 10 Word transfer/4 bytes 11 Reserved SINC Incremental source address. Source addresses increase every transfer. If the setting of SIZE is Byte, Source addresses increase by 1 every single transfer. If Half-Word, increase by 2; and if Word, increase by 4. 0 Disable 1 Enable DINC Incremental destination address. Destination addresses increase every transfer. If the setting of SIZE is Byte, Destination addresses increase by 1 every single transfer. If Half-Word, increase by 2; and Iif Word, increase by 4. 0 Disable 1 Enable DREQ Throttle and handshake control for DMA transfer 0 No throttle control during DMA transfer or transfers occurred only between memories 1 Hardware handshake management The DMA master is able to throttle down the transfer rate by way of request-grant handshake. B2W Word to Byte or Byte to Word transfer for the applications of transferring non-word-aligned-address data to word-aligned-address data. Note that BURST is set to 4-beat burst while enabling this function, and the SIZE is set to Byte. NO effect on channel 1 – 3 & 11 - 14. 0 Disable 1 Enable BURST Transfer Type. Burst-type transfers have better bus efficiency. Mass data movement is recommended to use this kind of transfer. However, note that burst-type transfer does not stop until all of the beats in a burst are completed or transfer length is reached. FIFO threshold of peripherals must be configured carefully while being used to move data from/to the peripherals. What transfer type can be used is restricted by the SIZE. If SIZE is 00b, i.e. byte transfer, all of the four transfer types can be used. If SIZE is 01b, i.e. half-word transfer, 16-beat incrementing burst cannot be used. If SIZE is 10b, i.e. word transfer, only single and 4-beat incrementing burst can be used. NO effect on channel 11 - 14. 000 Single 001 Reserved 010 4-beat incrementing burst 011 Reserved 100 8-beat incrementing burst 101 Reserved 110 16-beat incrementing burst 111 Reserved ITEN DMA transfer completion interrupt enable. 0 Disable 1 Enable WPSD The side using address-wrapping function. Only one side of a DMA channel can activate address-wrapping function at a time. NO effect on channel 11 - 14. 60/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 0 Address-wrapping on source . 1 Address-wrapping on destination. WPEN Address-wrapping for ring buffer and double buffer. The next address of DMA jumps to WRAP TO address when the current address matches WRAP POINT count. NO effect on channel 11 - 14. 0 Disable 1 Enable DIR Directions of DMA transfer for half-size and Virtual FIFO DMA channels, i.e. channels 4~14. The direction is from the perspective of the DMA masters. WRITE means read from master and then write to the address specified in DMA_PGMADDR, and vice versa. NO effect on channel 1 - 3. 0 Read 1 Write MAS Master selection. Specifies which master occupies this DMA channel. Once assigned to certain master, the corresponding DREQ and DACK are connected. For half-size and Virtual FIFO DMA channels, i.e. channels 4 ~ 14, a predefined address is assigned as well. 00000 SIM 00001 MSDC 00010 IrDA TX 00011 IrDA RX 00100 Reserved 00101 Reserved 00110 Reserved 00111 Reserved 01000 UART1 TX 01001 UART1 RX 01010 UART2 TX 01011 UART2 RX 01100 UART3 TX 01101 UART3 RX 01110 DSP-DMA1 01111 NFI TX 10000 NFI RX 10001 DSP-DMA2 10010 I2C TX 10011 I2C RX 10100 Reserved 10101 Reserved OTHERS Reserved DMA+0n18h Bit Name Type Reset 31 30 DMA Channel n Start Register 29 28 27 26 25 24 61/599 DMAn_START 23 22 21 20 19 18 17 16 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 Bit 15 Name STR Type R/W Reset 0 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 This register controls the activity of a DMA channel. Note that prior to setting STR to “1”, all the configurations should be done by giving proper value to the registers. Note also that once the STR is set to “1”, the hardware does not clear it automatically no matter if the DMA channel accomplishes the DMA transfer or not. In other works, the value of STR stays “1” regardless of the completion of DMA transfer. Therefore, the software program should be sure to clear STR to “0” before restarting another DMA transfer. If this bit is cleared to “0” during DMA transfer is active, software should polling MDDMA_GLBSTA RUNN after this bit is cleared to ensure current DMA transfer is terminated by DMA engine. Note that n is from 1 to 14. STR Start control for a DMA channel. 0 The DMA channel is stopped. 1 The DMA channel is started and running. DMA+0n1Ch Bit Name Type Reset Bit Name Type Reset DMA Channel n Interrupt Status Register DMAn_INTSTA 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 INT RO 0 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 This register shows the interrupt status of a DMA channel. It has the same value as DMA_GLBSTA. Note that n is from 1 to 14. INT Interrupt Status for DMA Channel 0 No interrupt request is generated. 1 One interrupt request is pending and waiting for service. DMA+0n20h Bit 31 Name Type Reset Bit 15 Name ACK Type WO Reset 0 DMA Channel n Interrupt Acknowledge Register DMAn_ACKINT 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 This register is used to acknowledge the current interrupt request associated with the completion event of a DMA channel by software program. Note that this is a write-only register, and any read to it returns a value of “0”. Note that n is from 1 to 14. ACK Interrupt acknowledge for the DMA channel 0 No effect 62/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 1 Interrupt request is acknowledged and should be relinquished. DMA+0n24h Bit Name Type Reset Bit Name Type Reset DMA Channel n Remaining Length of Current Transfer DMAn_RLCT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 RLCT RO 0 6 5 4 3 2 1 0 This register is to reflect the left count of the transfer. Note that this value is transfer count not the transfer data size. Note that n is from 1 to 10. DMA+0n28h Bit Name Type Reset Bit Name Type Reset DMA Bandwidth limiter Register DMAn_LIMITER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 LIMITER R/W 0 2 1 0 This register is to suppress the Bus utilization of the DMA channel. The value is from 0 to 255. 0 means no limitation, and 255 means totally banned. The value between 0 and 255 means certain DMA can have permission to use AHB every (4 X n) AHB clock cycles. Note that it is not recommended to limit the Bus utilization of the DMA channels because this increases the latency of response to the masters, and the transfer rate decreases as well. Before using it, programmer must make sure that the bus masters have some protective mechanism to avoid entering the wrong states. Note that n is from 1 to 14. LIMITER from 0 to 255. 0 means no limitation, 255 means totally banned, and others mean Bus access permission every (4 X n) AHB clock. DMA+0n2Ch Bit Name Type Reset Bit Name Type Reset DMAn_PGMADD R DMA Channel n Programmable Address Register 31 30 29 28 27 26 15 14 13 12 11 10 25 24 23 22 PGMADDR[31:16] R/W 0 9 8 7 6 PGMADDR[15:0] R/W 0 21 20 19 18 17 16 5 4 3 2 1 0 The above registers specify the address for a half-size DMA channel. This address represents a source address if DIR in DMA_CON is set to 0, and represents a destination address if DIR in DMA_CON is set to 1. Before being able to 63/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 program these register, the software should make sure that STR in DMAn_START is set to ‘0’, that is the DMA channel is stopped and disabled completely. Otherwise, the DMA channel may run out of order. Note that n is from 4 to 14 and PGMADDR can’t be TCM address. TCM is not accessible by DMA. PGMADDR PGMADDR[31:0] specifies the addresses for a half-size or a Virtual FIFO DMA channel, i.e. channel 4 – 14. WRITE Base address of transfer source or destination according to DIR bit READ Current address of the transfer. DMA+0n30h Bit Name Type Bit Name Type DMA Channel n Virtual FIFO Write Pointer Register 31 30 29 28 27 26 25 15 14 13 12 11 10 9 24 23 22 WRPTR[31:16] RO 8 7 6 WRPTR[15:0] RO DMAn_WRPTR 21 20 19 18 17 16 5 4 3 2 1 0 Note that n is from 11 to 14. Virtual FIFO Write Pointer. WRPTR DMA+0n34h Bit Name Type Bit Name Type DMA Channel n Virtual FIFO Read Pointer Register 31 30 29 28 27 26 25 15 14 13 12 11 10 9 24 23 RDPTR[31:16] RO 8 7 RDPTR[15:0] RO DMAn_RDPTR 22 21 20 19 18 17 16 6 5 4 3 2 1 0 Note that n is from 11 to 14. RDPTR Virtual FIFO Read Pointer. DMA+0n38h Bit Name Type Bit Name Type DMA Channel n Virtual FIFO Data Count Register DMAn_FFCNT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 FFCNT RO 6 5 4 3 2 1 0 Note that n is from 11 to 14. FFCNT To display the number of data stored in FIFO. 0 means FIFO empty, and FIFO is full if FFCNT is equal to FFSIZE. DMA+0n3Ch Bit Name Type Reset Bit DMA Channel n Virtual FIFO Status Register DMAn_FFSTA 31 30 29 28 27 26 25 24 23 22 21 20 19 18 15 14 13 12 11 10 9 8 7 6 5 4 3 2 Name 64/599 17 16 1 0 EMPT ALT FULL Y MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 Type Reset RO 0 RO 1 RO 0 Note that n is from 11 to 14. To indicate FIFO is full. 0 Not Full 1 Full EMPTY To indicate FIFO is empty. 0 Not Empty 1 Empty ALT To indicate FIFO Count is larger than ALTLEN. DMA issues an alert signal to UART to enable UART flow control. 0 Not reach alert region. 1 Reach alert region. FULL DMA+0n40h Bit Name Type Reset Bit Name Type Reset DMA Channel n Virtual FIFO Alert Length Register DMAn_ALTLEN 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 ALTLEN R/W 0 1 0 Note that n is from 11 to 14. ALTLEN Specifies the Alert Length of Virtual FIFO DMA. Once the remaining FIFO space is less than ALTLEN, an alert signal is issued to UART to enable flow control. Normally, ALTLEN shall be larger than 16 for UART application. DMA+0n44h Bit Name Type Reset Bit Name Type Reset DMA Channel n Virtual FIFO Size Register DMAn_FFSIZE 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 FFSIZE R/W 0 6 5 4 3 2 1 0 Note that n is from 11 to 14. FFSIZE Specifies the FIFO Size of Virtual FIFO DMA. 65/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 3.5 3.5.1 Interrupt Controller General Description Figure 14 outlines the major functionality of the MCU Interrupt Controller. The interrupt controller processes all interrupt sources coming from external lines and internal MCU peripherals. Since ARM9EJ-S core supports two levels of interrupt latency, this controller generates two request signals: FIQ for fast, low latency interrupt request and IRQ for more general interrupts with lower priority. 31 (hex) Figure 15 Block Diagram of the Interrupt Controller One and only one of the interrupt sources can be assigned to FIQ Controller and have the highest priority in requesting timing critical service. All the others share the same IRQ signal by connecting them to IRQ Controller. The IRQ Controller manages up 50 interrupt lines of IRQ0 to IRQ31 with fixed priority in descending order. The Interrupt Controller provides a simple software interface by mean of registers to manipulate the interrupt request shared system. IRQ Selection Registers and FIQ Selection Register determine the source priority and connecting relation among sources and interrupt lines. IRQ Source Status Register allows software program to identify the source of interrupt that generates the interrupt request. IRQ Mask Register provides software to mask out undesired sources some time. End of Interrupt Register permits software program to indicate to the controller that a certain interrupt service routine has been finished. Binary coded version of IRQ Source Status Register is also made available for software program to helpfully identify the interrupt source. Note that while taking advantage of this, it should also take the binary coded version of End of Interrupt Register coincidently. The essential Interrupt Table of ARM926EJ-S core is shown as Table 9. 66/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 Address Description 00000000h System Reset 00000018h IRQ 0000001Ch FIQ Table 10 Interrupt Table of ARM926EJ-S 3.5.1.1 Interrupt Source Masking Interrupt controller provides the function of Interrupt Source Masking by the way of programming MASK register. Any of them can be masked individually. However, because of the bus latency, the masking takes effect no earlier than 3 clock cycles later. In this time, the to-be-masked interrupts could come in and generate an IRQ pulse to MCU, and then disappear immediately. This IRQ forces MCU going to Interrupt Service Routine and polling Status Register (IRQ_STA(IRQ_STAH+IRQ_STAL) or IRQ_STA2), but the register shows there is no interrupt. This might cause MCU malfunction. There are two ways for programmer to protect their software. 1. Return from ISR (Interrupt Service Routine) immediately while the Status register shows no interrupt. 2. Set I bit of MCU before doing Interrupt Masking, and then clear it after Interrupt Masking done. Both avoid the problem, but the first item recommended to have in the ISR. 3.5.1.2 External Interrupt This interrupt controller also integrates an External Interrupt Controller that can support up to 8 interrupt requests coming from external sources, the EINT0~7, and 4 WakeUp interrupt requests, i.e. EINT8-B, coming from peripherals. All external interrupts can inform system to resume the system clock. The eight external interrupts can be used for different kind of applications, mainly for event detections: detection of hand free connection, detection of hood opening, detection of battery charger connection. Since the external event may be unstable in a certain period, a de-bounce mechanism is introduced to ensure the functionality. The circuitry is mainly used to verify that the input signal remains stable for a programmable number of periods of the clock. When this condition is satisfied, for the appearance or the disappearance of the input, the output of the de-bounce logic changes to the desired state. Note that, because it uses the 32 KHz slow clock for performing the de-bounce process, the parameter of de-bounce period and de-bounce enable takes effect no sooner than one 32 KHz clock cycle (~31.25us) after the software program sets them. When the sources of External Interrupt Controller are used to resume the system clock in sleep mode, the de-bounce mechanism must be enabled. However, the polarities of EINTs are clocked with the system clock. Any changes to them take effect immediately. 67/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 Figure 16 Block Diagram of External Interrupt Controller 3.5.1.3 External Interrupt Input Pins EINT EINT0 EINT1 EINT2 EINT3 EINT4 EINT5 EINT6 EINT7 Edge / Level HW Debounce Edge / Level Yes Edge / Level Yes Edge / Level Yes Edge / Level Yes Edge / Level Yes Edge / Level Yes Edge / Level Yes Edge / Level Yes SOURCE PIN SUPPLEMENT EINT0 EINT1 EINT2 if(GPIO44_M==1) then EINT3=EINT3 else EINT3=1 if(GPIO45_M==1) then EINT4=EINT4 else EINT4=1 if(GPIO46_M==1) then EINT5=EINT5 else EINT5=1 if(GPIO47_M==1) then EINT6=EINT6 else EINT6=1 if(GPIO48_M==1) then EINT7=EINT7 else EINT7=1 EINT8 Edge / Level Yes PMIC Charge Detection (Low Active) EINT9 Edge / Level Yes URXD1 68/599 1. GPIOs should be in the input mode and are effected by GPIO data input inversion registers. 2. GPIOxx_M is the GPIO mode control registers, please refer to GPIO segment. MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 EINTA Edge / Level Yes URXD2 EINTB Edge / Level Yes URXD3 REGISTER ADDRESS REGISTER NAME SYNONYM CIRQ + 0000h IRQ Selection 0 Register IRQ_SEL0 CIRQ + 0004h IRQ Selection 1 Register IRQ_SEL1 CIRQ + 0008h IRQ Selection 2 Register IRQ_SEL2 CIRQ + 000Ch IRQ Selection 3 Register IRQ_SEL3 CIRQ + 0010h IRQ Selection 4 Register IRQ_SEL4 CIRQ + 0014h IRQ Selection 5 Register IRQ_SEL5 CIRQ + 0018h IRQ Selection 6 Register IRQ_SEL6 CIRQ + 001ch IRQ Selection 7 Register IRQ_SEL7 CIRQ + 0020h IRQ Selection 8 Register IRQ_SEL8 CIRQ + 0034h FIQ Selection Register FIQ_SEL CIRQ + 0038h IRQ Mask Register (LSB) IRQ_MASKL CIRQ + 003ch IRQ Mask Register (MSB) IRQ_MASKH CIRQ + 0040h IRQ Mask Clear Register (LSB) IRQ_MASK_CLRL CIRQ + 0044h IRQ Mask Clear Register (MSB) IRQ_MASK_CLRH CIRQ + 0048h IRQ Mask Set Register (LSB) IRQ_MASK_SETL CIRQ + 004ch IRQ Mask Set Register (MSB) IRQ_MASK_SETH CIRQ + 0050h IRQ Status Register (LSB) IRQ_STAL CIRQ + 0054h IRQ Status Register (MSB) IRQ_STAH CIRQ + 0058h IRQ End of Interrupt Register (LSB) IRQ_EOIL CIRQ + 005ch IRQ End of Interrupt Register (MSB) IRQ_EOIH CIRQ + 0060h IRQ Sensitive Register (LSB) IRQ_SENSL CIRQ + 0064h IRQ Sensitive Register (MSB) IRQ_SENSH CIRQ + 0068h IRQ Software Interrupt Register (LSB) IRQ_SOFTL CIRQ + 006ch IRQ Software Interrupt Register (MSB) IRQ_SOFTH CIRQ + 0070h FIQ Control Register FIQ_CON CIRQ + 0074h FIQ End of Interrupt Register FIQ_EOI CIRQ + 0078h Binary Coded Value of IRQ_STATUS IRQ_STA2 CIRQ + 007ch Binary Coded Value of IRQ_EOI IRQ_EOI2 CIRQ + 0080h Binary Coded Value of IRQ_SOFT IRQ_SOFT2 CIRQ + 0100h EINT Status Register EINT_STA CIRQ + 0104h EINT Mask Register EINT_MASK CIRQ + 0108h EINT Mask Disable Register EINT_MASK_DIS CIRQ + 010Ch EINT Mask Enable Register EINT_MASK_EN 69/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 CIRQ + 0110h EINT Interrupt Acknowledge Register EINT_INTACK CIRQ + 0114h EINT Sensitive Register EINT_SENS CIRQ + 0120h EINT0 De-bounce Control Register EINT0_CON CIRQ + 0130h EINT1 De-bounce Control Register EINT1_CON CIRQ + 0140h EINT2 De-bounce Control Register EINT2_CON CIRQ + 0150h EINT3 De-bounce Control Register EINT3_CON CIRQ + 0160h EINT4 De-bounce Control Register EINT4_CON CIRQ + 0170h EINT5 De-bounce Control Register EINT5_CON CIRQ + 0180h EINT6 De-bounce Control Register EINT6_CON CIRQ + 0190h EINT7 De-bounce Control Register EINT7_CON CIRQ + 01a0h EINT8 De-bounce Control Register EINT8_CON CIRQ + 01b0h EINT9 De-bounce Control Register EINT9_CON CIRQ + 01c0h EINTA De-bounce Control Register EINT10_CON CIRQ + 01d0h EINTB De-bounce Control Register EINT11_CON Table 11 Interrupt Controller Register Map 3.5.2 Register Definitions CIRQ+0000h Bit Name Type Reset Bit Name Type Reset 31 30 29 28 15 14 13 IRQ2 R/W 0x2 12 CIRQ+0004h Bit Name Type Reset Bit Name Type Reset 27 26 IRQ4 R/W 0x4 11 10 IRQ_SEL0 25 24 23 22 9 8 7 6 21 20 IRQ3 R/W 0x3 5 4 19 18 17 16 IRQ2 R/W 3 2 1 IRQ1 R/W 0x1 30 29 28 15 14 13 IRQ7 R/W 0x7 12 27 26 IRQ9 R/W 0x9 11 10 IRQ_SEL1 25 24 23 22 9 8 7 6 21 20 IRQ8 R/W 0x8 5 4 IRQ6 R/W 0x6 19 18 17 16 IRQ7 R/W 3 2 1 30 29 28 15 14 13 IRQC R/W 12 27 26 IRQE R/W 0xe 11 10 0 IRQ5 R/W 0x5 IRQ Selection 2 Register 31 0 IRQ0 R/W 0x0 IRQ Selection 1 Register 31 CIRQ+0008h Bit Name Type Reset Bit Name Type IRQ Selection 0 Register IRQ_SEL2 25 24 23 22 9 8 7 6 IRQB R/W 70/599 21 20 IRQD R/W 0xD 5 4 19 18 3 2 IRQA R/W 17 16 IRQC R/W 1 0 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 Reset 0xc CIRQ+000ch Bit Name Type Reset Bit Name Type Reset 30 29 28 15 14 13 IRQ11 R/W 0x11 12 Bit Name Type Reset Bit Name Type Reset 30 29 28 15 14 13 IRQ16 R/W 0x16 12 Bit Name Type Reset Bit Name Type Reset 30 29 28 15 14 13 IRQ1B R/W 0x1b 12 Bit Name Type Reset Bit Name Type Reset IRQ_SEL3 24 23 22 9 8 IRQ10 R/W 0x10 7 6 21 20 IRQ12 R/W 0x12 5 4 19 18 17 16 IRQ11 R/W 3 2 1 27 26 IRQ18 R/W 0x18 11 10 25 27 26 IRQ1D R/W 0x1d 11 10 IRQ_SEL4 24 23 22 9 8 IRQ15 R/W 0x15 7 6 25 30 29 28 15 14 13 IRQ20 R/W 0x20 12 27 26 IRQ22 R/W 0x22 11 10 21 20 IRQ17 R/W 0x17 5 4 19 18 3 2 IRQ14 R/W 0x14 23 22 9 8 IRQ1A R/W 0x1a 7 6 21 20 IRQ1C R/W 0x1c 5 4 19 18 3 2 IRQ19 R/W 0x19 30 29 28 15 14 13 IRQ25 R/W 0x25 12 27 26 IRQ27 R/W 0x27 11 10 24 23 22 9 8 IRQ1F R/W 0x1f 7 6 24 23 22 9 8 IRQ24 R/W 0x24 7 6 25 1 0 17 16 IRQ1B R/W 1 0 IRQ_SEL6 21 20 IRQ21 R/W 0x21 5 4 19 21 20 IRQ26 R/W 0x26 5 4 19 18 3 2 IRQ1E R/W 0x1e IRQ Selection 7 Register 31 17 16 IRQ16 R/W IRQ_SEL5 24 25 0 IRQF R/W 0xf IRQ Selection 6 Register 31 CIRQ+001ch 25 IRQ Selection 5 Register 31 CIRQ+0018h 27 26 IRQ13 R/W 0x13 11 10 IRQ Selection 4 Register 31 CIRQ+0014h 0xa IRQ Selection 3 Register 31 CIRQ+0010h Bit Name Type Reset Bit Name Type Reset 0xb 17 16 IRQ20 R/W 1 0 IRQ_SEL7 71/599 18 3 2 IRQ23 R/W 0x23 17 16 IRQ25 R/W 1 0 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 CIRQ+0020h Bit Name Type Reset Bit Name Type Reset 31 30 29 28 15 14 13 IRQ2A R/W 0x2a 12 CIRQ+0024h Bit Name Type Reset Bit Name Type Reset 27 26 IRQ2C R/W 0x2c 11 10 25 IRQ_SEL8 24 23 22 9 8 IRQ29 R/W 0x29 7 6 21 20 IRQ2B R/W 0x2b 5 4 19 18 3 2 IRQ28 R/W 0x28 IRQ Selection 9 Register 31 30 29 28 15 14 13 IRQ2F R/W 0x2f 12 CIRQ+0034h Bit Name Type Reset Bit Name Type Reset IRQ Selection 8 Register 27 26 IRQ31 R/W 0x31 11 10 25 17 16 IRQ2A R/W 1 0 IRQ_SEL9 24 23 22 19 6 21 20 IRQ30 R/W 0x30 5 4 9 8 IRQ2E R/W 0x2e 7 18 3 2 IRQ2D R/W 0x2d FIQ Selection Register 17 16 IRQ2F R/W 1 0 FIQ_SEL 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIQ R/W 0 The IRQ/FIQ Selection Registers provide system designers with a flexible routing scheme to make various mappings of priority among interrupt sources possible. The registers allow the interrupt sources to be mapped onto interrupt requests of either FIQ or IRQ. While only one interrupt source can be assigned to FIQ, the other ones share IRQs by mapping them onto IRQ0 to IRQ1F connected to IRQ controller. The priority sequence of IRQ0~IRQ31 is fixed, i.e. IRQ0 > IRQ1 > IRQ2 > … > IRQ30 > IRQ31. During the software configuration process, the Interrupt Source Code of desired interrupt source should be written into source field of the corresponding IRQ_SEL0-IRQ_SEL9/FIQ_SEL. Six-bit Interrupt Source Codes for all interrupt sources are fixed and defined. Interrupt Source STA2 (Hex) STAH_STAL GPI_FIQ 0 000_00000001 TDMA_CTIRQ1 1 000_00000002 TDMA_CTIRQ2 2 000_00000004 DSP2CPU 3 000_00000008 SIM 4 000_00000010 DMA 5 000_00000020 72/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 TDMA 6 000_00000040 UART1 7 000_00000080 KeyPad 8 000_00000100 UART2 9 000_00000200 GPTimer a 000_00000400 EINT b 000_00000800 USB MC c 000_00001000 MSDC d 000_00002000 RTC e 000_00004000 IrDA f 000_00008000 LCD 10 000_00010000 UART3 11 000_00020000 GPI0 12 000_00040000 WDT 13 000_00080000 Reserved 14 000_00100000 Reserved 15 000_00200000 NFI 16 000_00400000 Reserved 17 000_00800000 Reserved 18 000_01000000 Reserved 19 000_02000000 Reserved 1a 000_04000000 I2C 1b 000_08000000 G2D 1c 000_10000000 Reserved 1d 000_20000000 CAM 1e 000_40000000 Reserved 1f 000_80000000 Reserved 20 001_00000000 Reserved 21 002_00000000 Reserved 22 004_00000000 Reserved 23 008_00000000 Resizer_crz 24 010_00000000 Reserved 25 020_00000000 Reserved 26 040_00000000 Reserved 27 080_00000000 DSPINT 28 100_00000000 USB DMA 29 200_00000000 PWM 2A 400_00000000 GPI1 2B 800_00000000 GPI2 2C 1000_00000000 IRDebug1 2D 2000_00000000 73/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 IRDebug2 2E 4000_00000000 Reserved 2F 8000_00000000 Reserved 30 10000_00000000 AUXADC 31 20000_00000000 Table 12 Interrupt Source Code for Interrupt Sources FIQ, IRQ0-31 CIRQ+0038h Bit Name Type Reset Bit Name Type Reset The 5-bit content of this field corresponds to an Interrupt Source Code shown above. IRQ Mask Register (LSB) 31 30 29 28 27 26 25 IRQ1F IRQ1E IRQ1D IRQ1C IRQ1B IRQ1A IRQ19 R/W R/W R/W R/W R/W R/W R/W 1 1 1 1 1 1 1 15 14 13 12 11 10 9 IRQF IRQE IRQD IRQC IRQB IRQA IRQ9 R/W R/W R/W R/W R/W R/W R/W 1 1 1 1 1 1 1 CIRQ+003ch IRQ_MASKL 24 IRQ18 R/W 1 8 IRQ8 R/W 1 23 IRQ17 R/W 1 7 IRQ7 R/W 1 22 IRQ16 R/W 1 6 IRQ6 R/W 1 21 IRQ15 R/W 1 5 IRQ5 R/W 1 20 IRQ14 R/W 1 4 IRQ4 R/W 1 19 IRQ13 R/W 1 3 IRQ3 R/W 1 IRQ Mask Register (MSB) 18 IRQ12 R/W 1 2 IRQ2 R/W 1 17 IRQ11 R/W 1 1 IRQ1 R/W 1 16 IRQ10 R/W 1 0 IRQ0 R/W 1 IRQ_MASKH Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 Name IRQ31 Type R/W Reset 1 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Name IRQ2F IRQ2E IRQ2D IRQ2C IRQ2B IRQ2A IRQ29 IRQ28 IRQ27 IRQ26 IRQ25 IRQ24 IRQ23 IRQ22 IRQ21 Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 16 IRQ30 R/W 1 0 IRQ20 R/W 1 This register contains a mask bit for each interrupt line in IRQ Controller. The register allows each interrupt source IRQ0 to IRQ1F to be disabled or masked separately under software control. After a system reset, all bit values are set to 1 to indicate that interrupt requests are prohibited. IRQ0-31 0 1 Mask control for the associated interrupt source in the IRQ controller Interrupt is enabled. Interrupt is disabled. CIRQ+0040h Bit Name Type Bit Name Type IRQ_MASK_CL RL IRQ Mask Clear Register (LSB) 31 30 29 28 27 26 25 IRQ1F IRQ1E IRQ1D IRQ1C IRQ1B IRQ1A IRQ19 W1C W1C W1C W1C W1C W1C W1C 15 14 13 12 11 10 9 IRQF IRQE IRQD IRQC IRQB IRQA IRQ9 W1C W1C W1C W1C W1C W1C W1C 24 IRQ18 W1C 8 IRQ8 W1C 74/599 23 IRQ17 W1C 7 IRQ7 W1C 22 IRQ16 W1C 6 IRQ6 W1C 21 IRQ15 W1C 5 IRQ5 W1C 20 IRQ14 W1C 4 IRQ4 W1C 19 IRQ13 W1C 3 IRQ3 W1C 18 IRQ12 W1C 2 IRQ2 W1C 17 IRQ11 W1C 1 IRQ1 W1C 16 IRQ10 W1C 0 IRQ0 W1C MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 CIRQ+0044h IRQ_MASK_CL RH IRQ Mask Clear Register (MSB) Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 Name IRQ31 Type W1C Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Name IRQ2F IRQ2E IRQ2D IRQ2C IRQ2B IRQ2A IRQ29 IRQ28 IRQ27 IRQ26 IRQ25 IRQ24 IRQ23 IRQ22 IRQ21 Type W1C W1C W1C W1C W1C W1C W1C W1C W1C W1C W1C W1C W1C W1C W1C 16 IRQ30 W1C 0 IRQ20 W1C This register is used to clear bits in IRQ Mask Register. When writing to this register, the data bits that are HIGH cause the corresponding bits in IRQ Mask Register to be cleared. Data bits that are LOW have no effect on the corresponding bits in IRQ Mask Register. IRQ0-31 0 1 Clear corresponding bits in IRQ Mask Register. No effect. Disable the corresponding MASK bit. CIRQ+0048h Bit Name Type Bit Name Type 31 30 29 28 27 26 25 IRQ1F IRQ1E IRQ1D IRQ1C IRQ1B IRQ1A IRQ19 W1S W1S W1S W1S W1S W1S W1S 15 14 13 12 11 10 9 IRQF IRQE IRQD IRQC IRQB IRQA IRQ9 W1S W1S W1S W1S W1S W1S W1S CIRQ+004ch IRQ_MASK_SET L IRQ Mask SET Register (LSB) 24 IRQ18 W1S 8 IRQ8 W1S 23 IRQ17 W1S 7 IRQ7 W1S IRQ Mask SET Register (MSB) 22 IRQ16 W1S 6 IRQ6 W1S 21 IRQ15 W1S 5 IRQ5 W1S 20 IRQ14 W1S 4 IRQ4 W1S 19 IRQ13 W1S 3 IRQ3 W1S 18 IRQ12 W1S 2 IRQ2 W1S 17 IRQ11 W1S 1 IRQ1 W1S 16 IRQ10 W1S 0 IRQ0 W1S IRQ_MASK_SET H Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 Name IRQ31 Type W1S Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Name IRQ2F IRQ2E IRQ2D IRQ2C IRQ2B IRQ2A IRQ29 IRQ28 IRQ27 IRQ26 IRQ25 IRQ24 IRQ23 IRQ22 IRQ21 Type W1S W1S W1S W1S W1S W1S W1S W1S W1S W1S W1S W1S W1S W1S W1S 16 IRQ30 W1S 0 IRQ20 W1S This register is used to set bits in the IRQ Mask Register. When writing to this register, the data bits that are HIGH cause the corresponding bits in IRQ Mask Register to be set. Data bits that are LOW have no effect on the corresponding bits in IRQ Mask Register. IRQ0-31 0 1 Set corresponding bits in IRQ Mask Register. No effect. Enable corresponding MASK bit. CIRQ+0050h IRQ Source Status Register (LSB) IRQ_STAL Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name IRQ1F IRQ1E IRQ1D IRQ1C IRQ1B IRQ1A IRQ19 IRQ18 IRQ17 IRQ16 IRQ15 IRQ14 IRQ13 IRQ12 IRQ11 IRQ10 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name IRQF IRQE IRQD IRQC IRQB IRQA IRQ9 IRQ8 IRQ7 IRQ6 IRQ5 IRQ4 IRQ3 IRQ2 IRQ1 IRQ0 75/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 Type Reset RO 0 RO 0 CIRQ+0054h RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 IRQ Source Status Register (MSB) RO 0 RO 0 RO 0 IRQ_STAH Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name IRQ31 IRQ30 Type RO RO Reset 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name IRQ2F IRQ2E IRQ2D IRQ2C IRQ2B IRQ2A IRQ29 IRQ28 IRQ27 IRQ26 IRQ25 IRQ24 IRQ23 IRQ22 IRQ21 IRQ20 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 This Register allows software to poll which interrupt line has generated an IRQ interrupt request. A bit set to 1 indicates a corresponding active interrupt line. Only one flag is active at a time. The IRQ_STA is type of read-clear; write access has no effect on the content. IRQ0-31 0 1 Interrupt indicator for the associated interrupt source. The associated interrupt source is non-active. The associated interrupt source is asserted. CIRQ+0058h IRQ End of Interrupt Register (LSB) Bit 31 30 29 28 27 26 25 Name IRQ1F IRQ1E IRQ1D IRQ1C IRQ1B IRQ1A IRQ19 Type WO WO WO WO WO WO WO Reset 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 Name IRQF IRQE IRQD IRQC IRQB IRQA IRQ9 Type WO WO WO WO WO WO WO Reset 0 0 0 0 0 0 0 CIRQ+005ch 24 IRQ18 WO 0 8 IRQ8 WO 0 23 IRQ17 WO 0 7 IRQ7 WO 0 IRQ End of Interrupt Register (MSB) IRQ_EOIL 22 IRQ16 WO 0 6 IRQ6 WO 0 21 IRQ15 WO 0 5 IRQ5 WO 0 20 IRQ14 WO 0 4 IRQ4 WO 0 19 IRQ13 WO 0 3 IRQ3 WO 0 18 IRQ12 WO 0 2 IRQ2 WO 0 17 IRQ11 WO 0 1 IRQ1 WO 0 16 IRQ10 WO 0 0 IRQ0 WO 0 IRQ_EOIH Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 Name IRQ31 Type WO Reset 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Name IRQ2F IRQ2E IRQ2D IRQ2C IRQ2B IRQ2A IRQ29 IRQ28 IRQ27 IRQ26 IRQ25 IRQ24 IRQ23 IRQ22 IRQ21 Type WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 IRQ30 WO 0 0 IRQ20 WO 0 This register provides a mean for software to relinquish and to refresh the interrupt controller. Writing a 1 to a specific bit position results in an End of Interrupt command issued internally to the corresponding interrupt line. IRQ0-31 0 1 End of Interrupt command for the associated interrupt line. No service is currently in progress or pending. Interrupt request is in-service. CIRQ+0060h IRQ Sensitive Register (LSB) IRQ_SENSL Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name IRQ1F IRQ1E IRQ1D IRQ1C IRQ1B IRQ1A IRQ19 IRQ18 IRQ17 IRQ16 IRQ15 IRQ14 IRQ13 IRQ12 IRQ11 IRQ10 Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 76/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name IRQF IRQE IRQD IRQC IRQB IRQA IRQ9 IRQ8 IRQ7 IRQ6 IRQ5 IRQ4 IRQ3 IRQ2 IRQ1 IRQ0 Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CIRQ+0064h IRQ Sensitive Register (MSB) IRQ_SENSH Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 Name IRQ31 Type R/W Reset 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Name IRQ2F IRQ2E IRQ2D IRQ2C IRQ2B IRQ2A IRQ29 IRQ28 IRQ27 IRQ26 IRQ25 IRQ24 IRQ23 IRQ22 IRQ21 Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 IRQ30 R/W 0 0 IRQ20 R/W 0 All interrupt lines of IRQ Controller, IRQ0~IRQ31 can be programmed as either edge or level sensitive. By default, all the interrupt lines are edge sensitive and should be active LOW. Once a interrupt line is programmed as edge sensitive, an interrupt request is triggered only at the falling edge of interrupt line, and the next interrupt is not accepted until the EOI command is given. However, level sensitive interrupts trigger is according to the signal level of the interrupt line. Once the interrupt line become from HIGH to LOW, an interrupt request is triggered, and another interrupt request is triggered if the signal level remain LOW after an EOI command. Note that in edge sensitive mode, even if the signal level remains LOW after EOI command, another interrupt request is not triggered. That is because edge sensitive interrupt is only triggered at the falling edge. IRQ0-31 0 1 Sensitivity type of the associated Interrupt Source Edge sensitivity with active LOW Level sensitivity with active LOW CIRQ+0068h Bit Name Type Reset Bit Name Type Reset IRQ Software Interrupt Register (LSB) 31 30 29 28 27 26 25 IRQ1F IRQ1E IRQ1D IRQ1C IRQ1B IRQ1A IRQ19 R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 15 14 13 12 11 10 9 IRQF IRQE IRQD IRQC IRQB IRQA IRQ9 R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 CIRQ+006ch 24 IRQ18 R/W 0 8 IRQ8 R/W 0 23 IRQ17 R/W 0 7 IRQ7 R/W 0 22 IRQ16 R/W 0 6 IRQ6 R/W 0 IRQ Software Interrupt Register (MSB) IRQ_SOFTL 21 IRQ15 R/W 0 5 IRQ5 R/W 0 20 IRQ14 R/W 0 4 IRQ4 R/W 0 19 IRQ13 R/W 0 3 IRQ3 R/W 0 18 IRQ12 R/W 0 2 IRQ2 R/W 0 17 IRQ11 R/W 0 1 IRQ1 R/W 0 IRQ_SOFTH Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 Name IRQ31 Type R/W Reset 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Name IRQ2F IRQ2E IRQ2D IRQ2C IRQ2B IRQ2A IRQ29 IRQ28 IRQ27 IRQ26 IRQ25 IRQ24 IRQ23 IRQ22 IRQ21 Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Setting “1” to the specific bit position generates a software interrupt for corresponding interrupt line before mask. register is used for debug purpose. 77/599 16 IRQ10 R/W 0 0 IRQ0 R/W 0 16 IRQ30 R/W 0 0 IRQ20 R/W 0 This MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 Software Interrupt IRQ0-IRQ31 CIRQ+0070h Bit Name Type Reset Bit Name Type Reset FIQ Control Register FIQ_CON 31 30 29 28 27 26 25 24 23 22 21 20 19 18 15 14 13 12 11 10 9 8 7 6 5 4 3 2 17 16 1 0 SENS MASK R/W R/W 0 1 This register provides a means for software program to control the FIQ controller. MASK Mask control for the FIQ Interrupt Source 0 Interrupt is enabled. 1 Interrupt is disabled. SENS Sensitivity type of the FIQ Interrupt Source 0 Edge sensitivity with active LOW 1 Level sensitivity with active LOW CIRQ+0074h Bit Name Type Reset Bit Name Type Reset FIQ End of Interrupt Register FIQ_EOI 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EOI WO 0 This register provides a means for software to relinquish and to refresh the FIQ controller. Writing a ‘1’ to the specific bit position results in an End of Interrupt command issued internally to the corresponding interrupt line. EOI End of Interrupt command CIRQ+0078h Bit Name Type Reset Bit Binary Coded Value of IRQ_STATUS IRQ_STA2 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 NOIR Q RC 0 7 6 5 4 3 2 1 0 Name Type Reset STS RC 0 This Register is a binary coded version of IRQ_STA. It is used by the software program to poll which interrupt line has generated the IRQ interrupt request in a much easier way. Any read to it has the same result as reading IRQ_STA. The IRQ_STA2 is also read-only and read-clear; write access has no effect on the content. Note that IRQ_STA2 should be coupled with IRQ_EOI2 while using it. STS Binary coded value of IRQ_STA 78/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 NOIRQ Indicating if there is an IRQ or not. If there is no IRQ, this bit is HIGH, and the value of STS is 00_0000b. CIRQ+007ch Bit Name Type Reset Bit Name Type Reset Binary Coded Value of IRQ_EOI IRQ_EOI2 31 30 29 28 27 26 25 24 23 22 21 20 19 15 14 13 12 11 10 9 8 7 6 5 4 3 18 17 16 2 1 0 EOI WO 0 This register is a binary coded version of IRQ_EOI. It provides an easier way for software program to relinquish and to refresh the interrupt controller. Writing a specific code results in an End of Interrupt command issued internally to the corresponding interrupt line. Note that IRQ_EOI2 should be coupled with IRQ_STA2 while using it. EOI Binary coded value of IRQ_EOI CIRQ+0080h Bit Name Type Reset Bit Name Type Reset Binary Coded Value of IRQ_SOFT IRQ_SOFT2 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 SOFT WO 0 1 0 This register is a binary coded version of IRQ_SOFT. SOFT Binary Coded Value of IRQ_SOFT CIRQ+0100h Bit Name Type Reset Bit Name Type Reset EINT Interrupt Status Register 31 30 29 28 15 14 13 12 27 26 25 24 EINT_STA 23 22 21 20 19 18 17 16 11 10 9 8 7 6 5 4 3 2 1 0 EINTB EINTA EINT9 EINT8 EINT7 EINT6 EINT5 EINT4 EINT3 EINT2 EINT1 EINT0 RO RO RO RO RO RO RO RO RO RO RO RO 0 0 0 0 0 0 0 0 0 0 0 0 This register keeps up with current status that which EINT Source generates the interrupt request. If EINT sources are set to edge sensitivity, EINT_IRQ is de-asserted while this register is read. EINT0-EINTB Interrupt status 0 No interrupt request is generated. 1 Interrupt request is pending. CIRQ+0104h Bit Name Type Reset 31 30 EINT Interrupt Mask Register 29 28 27 26 25 24 79/599 EINT_MASK 23 22 21 20 19 18 17 16 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 Bit Name Type Reset 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EINTB EINTA EINT9 EINT8 EINT7 EINT6 EINT5 EINT4 EINT3 EINT2 EINT1 EINT0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 1 1 1 1 1 1 1 1 1 1 1 1 This register controls whether or not EINT Source is allowed to generate an interrupt request. Setting a “1” to the specific bit position prohibits the external interrupt line from becoming active. EINT0-EINTB Interrupt Mask 0 Interrupt request is enabled. 1 Interrupt request is disabled. CIRQ+0108h Bit Name Type Bit Name Type EINT_MASK_CL R EINT Interrupt Mask Clear Register 31 30 29 28 15 14 13 12 27 26 25 24 23 22 21 20 19 18 17 16 11 10 9 8 7 6 5 4 3 2 1 0 EINTB EINTA EINT9 EINT8 EINT7 EINT6 EINT5 EINT4 EINT3 EINT2 EINT1 EINT0 W1C W1C W1C W1C W1C W1C W1C W1C W1C W1C W1C W1C This register is used to clear individual mask bits. Only the bits set to 1 are in effect, and interrupt masks for which the mask bit is set are cleared (set to 0). Otherwise the interrupt mask bit retains its original value. EINT0-EINTB Disable mask for the associated external interrupt source. 0 No effect. 1 Disable the corresponding MASK bit. CIRQ+010Ch Bit Name Type Bit Name Type EINT_MASK_SE T EINT Interrupt Mask Set Register 31 30 29 28 15 14 13 12 27 26 25 24 23 22 21 20 19 18 17 16 11 10 9 8 7 6 5 4 3 2 1 0 EINTB EINTA EINT9 EINT8 EINT7 EINT6 EINT5 EINT4 EINT3 EINT2 EINT1 EINT0 W1S W1S W1S W1S W1S W1S W1S W1S W1S W1S W1S W1S This register is used to set individual mask bits. Only the bits set to 1 are in effect, and interrupt masks for which the mask bit is set are set to 1. Otherwise the interrupt mask bit retains its original value. EINT0-EINTB Disable mask for the associated external interrupt source. 0 No effect. 1 Enable corresponding MASK bit. CIRQ+0110h Bit Name Type Reset Bit Name Type EINT Interrupt Acknowledge Register 31 30 29 28 15 14 13 12 27 26 25 24 23 EINT_INTACK 22 21 20 19 18 17 16 11 10 9 8 7 6 5 4 3 2 1 0 EINTB EINTA EINT9 EINT8 EINT7 EINT6 EINT5 EINT4 EINT3 EINT2 EINT1 EINT0 WO WO WO WO WO WO WO WO WO WO WO WO 80/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 Reset 0 0 0 0 0 0 0 0 0 0 0 0 Writing “1” to the specific bit position acknowledge the interrupt request correspondingly to the external interrupt line source. EINT0-EINTB Interrupt acknowledgement 0 No effect 1 Interrupt request is acknowledged. CIRQ+0114h Bit Name Type Reset Bit Name Type Reset EINT Sensitive Register 31 30 29 28 15 14 13 12 27 26 25 EINT_SENS 24 23 22 21 20 19 18 17 16 11 10 9 8 7 6 5 4 3 2 1 0 EINTB EINTA EINT9 EINT8 EINT7 EINT6 EINT5 EINT4 EINT3 EINT2 EINT1 EINT0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 1 1 1 1 1 1 1 1 1 1 1 1 Sensitivity type of external interrupt source. EINT0-B 0 1 Sensitivity type of the associated external interrupt source. Edge sensitivity with active LOW. Level sensitivity with active LOW. CIRQ+01m0h Bit 31 Name Type Reset Bit 15 Name EN Type R/W Reset 0 EINTn De-bounce Control Register EINTn_CON 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 14 13 12 11 POL R/W 0 10 9 8 7 6 5 CNT R/W 0 4 3 2 1 0 These registers control the de-bounce logic for external interrupt sources in order to minimize the possibility of false activations. Note that n is from 0 to 11, and m is n + 2. When the external interrupt sources is used to resume the system clock from the sleep mode, the De-bounce control circuit must be enabled. CNT POL EN De-bounce duration in terms of number of 32 KHz clock cycles. Activation type of the EINT source 0 Negative polarity 1 Positive polarity De-bounce control circuit 0 Disable 1 Enable 81/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 3.6 BUS Monitor (BM) 3.6.1 General Description MT6235 contains 4-layer AHB BUS. Most of them contain AHB master and slave modules. BUS Monitor (BM) provides an interface to provide the BUS access usage to help analyze system performance. In BM, only EN is cleared to 0 after reset. Other registers do not effect by reset. 3.6.2 Register Definitions BM+0000h BM control BM_CON Bit Name Type Reset Bit Name Type Reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 CLR WO 0 EN R/W 0 EN Enable the BM. BM is off after reset. You have to turn on it by write EN =1. 0 BM is disabled. 1 BM is enabled. All statistics recorded in BM is going to clear if you write CLR=1. CLR is a one-shot control bit. CLR BM+0004h Bit Name Type Bit Name Type BM_LYR2_HMA STER Layer-2 AHB master filter 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 MASEN R/W 2 1 0 MASEN 0 1 Master enable filter. Disable the logging when the transaction is caused by the corresponding master. Enable the logging when the transaction is caused by the corresponding master. bit0VFF Port bit1DMA bit2Wavetable bit3USB bit4IRDBG1 bit5IRDBG2 82/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 bit6IRDA bit7PWM BM+0008h Bit Name Type Bit Name Type BM_CYCLE_CN T BM cycle count 31 30 29 28 27 26 15 14 13 12 11 10 25 24 23 22 CYCLE_CNT[31:16] RO 9 8 7 6 CYCLE_CNT[15:0] RO 21 20 19 18 17 16 5 4 3 2 1 0 CYCLE_CNT CYCLE_CNT indicates how many cycles passed when EN=1. CYCLE_CNT is only cleared by CLR and is not affected by RESET. BM+0010h Bit Name Type Bit Name Type BM_LYR1_ACC NT Layer-1 AHB active cycle count 31 30 29 28 27 26 15 14 13 12 11 10 25 24 23 22 LYR1_ACCNT[31:16] RO 9 8 7 6 LYR1_ACCNT[15:0] RO 21 20 19 18 17 16 5 4 3 2 1 0 LYR1_ACCNT LYR1_ACCNT indicates how many cycles HTRANS is (non-IDLE and non-BUSY) and increments in every cycle when (EN=1) and (HTRANS=NON-SEQ or SEQ). LYR1_ACCNT is only cleared by CLR and is not affected by RESET. BM+0014h Bit Name Type Bit Name Type BM_LYR1_TCN T Layer-1 AHB transaction count 31 30 29 28 27 26 15 14 13 12 11 10 25 24 23 22 LYR1_TCNT[31:16] RO 9 8 7 6 LYR1_TCNT[15:0] RO 21 20 19 18 17 16 5 4 3 2 1 0 LYR1_TCNT LYR1_TCNT indicates transaction accumulation and increments in every cycle when (EN=1) and (HTRANS=NON-SEQ or SEQ) and (HREADY=1). LYR1_ACNT is only cleared by CLR and is not affected by RESET. BM+0018h Bit Name 31 BM_LYR1_WCN T Layer-1 AHB word count 30 29 28 27 26 25 24 23 22 LYR1_WCNT[31:16] 83/599 21 20 19 18 17 16 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 Type Bit Name Type 15 14 13 12 11 10 9 RO 8 7 6 LYR1_WCNT[15:0] RO 5 4 3 2 1 0 LYR1_WCNT LYR1_WCNT indicates transaction of word counts been transferred and increases depends HSIZE in every cycle when (EN=1) and (HTRANS=NON-SEQ or SEQ) and (HREADY=1). A word means 4 bytes (32-bit) in this document. The total data counts transferred less then 1 word is truncated. (For example, the BUS transfers 33 bytes after EN=1. you will get 8 in WCNT. The last byte count is ignored.) LYR1_WCNT is only cleared by CLR and is not affected by RESET. HSIZE=00 8-bit data. WCNT increases 1. HSIZE=01 16-bit data. WCNT increases 2. HSIZE=10 32-bit data. WCNT increases 4. OTHER Not supported. BM+0020h Bit Name Type Bit Name Type 31 15 BM+0024h Bit Name Type Bit Name Type 31 15 BM+0028h Bit Name Type Bit Name Type 31 15 BM+002ch Bit Name 31 BM_LYR1_FIFO 0 Layer-1 AHB status FIFO 0~3 30 29 28 LYR1_HDY3 RO 14 13 12 LYR1_HDY1 RO 27 11 26 25 24 LYR1_HSEL3 RO 10 9 8 LYR1_HSEL1 RO 23 7 22 21 20 LYR1_HDY2 RO 6 5 4 LYR1_HDY0 RO 19 3 BM_LYR1_FIFO 4 Layer-1 AHB status FIFO 4~7 30 29 28 LYR1_HDY7 RO 14 13 12 LYR1_HDY5 RO 27 11 26 25 24 LYR1_HSEL7 RO 10 9 8 LYR1_HSEL5 RO 23 7 22 21 20 LYR1_HDY6 RO 6 5 4 LYR1_HDY4 RO 19 3 27 11 26 25 24 LYR1_HSEL11 RO 10 9 8 LYR1_HSEL9 RO 23 7 22 21 20 LYR1_HDY10 RO 6 5 4 LYR1_HDY8 RO 19 3 27 26 25 24 LYR1_HSEL15 84/599 18 17 16 LYR1_HSEL10 RO 2 1 0 LYR1_HSEL8 RO BM_LYR1_FIFO C Layer-1 AHB status FIFO 12~15 30 29 28 LYR1_HDY15 18 17 16 LYR1_HSEL6 RO 2 1 0 LYR1_HSEL4 RO BM_LYR1_FIFO 8 Layer-1 AHB status FIFO 8~11 30 29 28 LYR1_HDY11 RO 14 13 12 LYR1_HDY9 RO 18 17 16 LYR1_HSEL2 RO 2 1 0 LYR1_HSEL0 RO 23 22 21 20 LYR1_HDY14 19 18 17 16 LYR1_HSEL14 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 Type Bit Name Type 15 RO 14 13 12 LYR1_HDY13 RO 11 RO 10 9 8 LYR1_HSEL13 RO 7 RO 6 5 4 LYR1_HDY12 RO 3 RO 2 1 0 LYR1_HSEL12 RO BM keeps FIFOs internal recording HSEL and HREADY status on BUS for each layer. 0th is the latest one and 15th is the oldest. The FIFO only shifts when (EN=1) and (HTRANS=SEQ or NON-SEQ) and (HREADY=0) and (slaves’ HREADYs differ from HDY0). If all above conditions meet, then (HRDY0=current HREADY on BUS) and (HRDY1=HRDY0) and (HRDY2=HRDY1) and … and (HRDY15=HRDY14). HSEL follows the same rules. HSELx The xth HSEL status on BUS bit0EMI bit1System memory bit2LCD HRDYx The xth HREADY status on BUS bit0EMI bit1System memory bit2LCD BM+0030h Bit Name Type Bit Name Type BM_LYR2_ACC NT Layer-2 AHB active cycle count 31 30 29 28 27 26 15 14 13 12 11 10 25 24 23 22 LYR2_ACCNT[31:16] RO 9 8 7 6 LYR2_ACCNT[15:0] RO 21 20 19 18 17 16 5 4 3 2 1 0 LYR2_ACCNT LYR2_ACCNT indicates how many cycles HTRANS is (non-IDLE and non-BUSY) and increments in every cycle when (EN=1) and (HTRANS=NON-SEQ or SEQ). LYR2_ACCNT is only cleared by CLR and is not affected by RESET. BM+0034h Bit Name Type Bit Name Type BM_LYR2_TCN T Layer-2 AHB transaction count 31 30 29 28 27 26 15 14 13 12 11 10 25 24 23 22 LYR2_TCNT[31:16] RO 9 8 7 6 LYR2_TCNT[15:0] RO 21 20 19 18 17 16 5 4 3 2 1 0 LYR2_TCNT LYR2_TCNT indicates transaction accumulation and increments in every cycle when (EN=1) and (HTRANS=NON-SEQ or SEQ) and (HREADY=1). LYR2_ACNT is only cleared by CLR and is not affected by RESET. 85/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 BM+0038h Bit Name Type Bit Name Type BM_LYR2_WCN T Layer-2 AHB word count 31 30 29 28 27 26 15 14 13 12 11 10 25 24 23 22 LYR2_WCNT[31:16] RO 9 8 7 6 LYR2_WCNT[15:0] RO 21 20 19 18 17 16 5 4 3 2 1 0 LYR2_WCNT LYR2_WCNT indicates transaction of word counts been transferred and increases depends HSIZE in every cycle when (EN=1) and (HTRANS=NON-SEQ or SEQ) and (HREADY=1). A word means 4 bytes (32-bit) in this document. The total data counts transferred less then 1 word is truncated. (For example, the BUS transfers 33 bytes after EN=1. you will get 8 in WCNT. The last byte count is ignored.) LYR2_WCNT is only cleared by CLR and is not affected by RESET. HSIZE=00 8-bit data. WCNT increases 1. HSIZE=01 16-bit data. WCNT increases 2. HSIZE=10 32-bit data. WCNT increases 4. OTHER Not supported. BM+0040h Bit Name Type Bit Name Type 31 30 29 28 15 14 13 12 BM+0044h Bit Name Type Bit Name Type 27 26 25 LYR2_HDY1 RO 11 10 9 LYR2_HDY0 RO 24 23 22 21 20 8 7 6 5 4 31 30 29 28 15 14 13 12 27 26 25 LYR2_HDY3 RO 11 10 9 LYR2_HDY2 RO 24 23 22 21 20 8 7 6 5 4 30 29 28 15 14 13 12 27 26 25 LYR2_HDY5 RO 11 10 9 LYR2_HDY4 RO 24 23 22 21 20 8 7 6 5 4 86/599 16 0 19 18 17 LYR2_HSEL3 RO 3 2 1 LYR2_HSEL2 RO 16 0 BM_LYR2_FIFO 4 Layer-2 AHB status FIFO 4~5 31 19 18 17 LYR2_HSEL1 RO 3 2 1 LYR2_HSEL0 RO BM_LYR2_FIFO 2 Layer-2 AHB status FIFO 2~3 BM+0048h Bit Name Type Bit Name Type BM_LYR2_FIFO 0 Layer-2 AHB status FIFO 0~1 19 18 17 LYR2_HSEL5 RO 3 2 1 LYR2_HSEL4 RO 16 0 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 BM+004ch Bit Name Type Bit Name Type 31 30 29 28 15 14 13 12 BM+0050h Bit Name Type Bit Name Type 31 30 29 28 15 14 13 12 31 30 29 28 15 14 13 12 23 22 21 20 8 7 6 5 4 27 26 25 LYR2_HDY9 RO 11 10 9 LYR2_HDY8 RO 27 26 25 LYR2_HDY11 RO 11 10 9 LYR2_HDY10 RO 31 30 29 28 15 14 13 12 27 26 25 LYR2_HDY13 RO 11 10 9 LYR2_HDY12 RO 24 23 22 21 20 8 7 6 5 4 30 29 28 15 14 13 12 27 26 25 LYR2_HDY15 RO 11 10 9 LYR2_HDY14 RO 16 0 19 18 17 LYR2_HSEL9 RO 3 2 1 LYR2_HSEL8 RO 16 0 BM_LYR2_FIFO A 24 23 22 21 20 8 7 6 5 4 19 18 17 LYR2_HSEL11 RO 3 2 1 LYR2_HSEL10 RO 16 0 BM_LYR2_FIFO C 24 23 22 21 20 8 7 6 5 4 19 18 17 LYR2_HSEL13 RO 3 2 1 LYR2_HSEL12 RO 16 0 BM_LYR2_FIFO E Layer-2 AHB status FIFO 14~15 31 19 18 17 LYR2_HSEL7 RO 3 2 1 LYR2_HSEL6 RO BM_LYR2_FIFO 8 Layer-2 AHB status FIFO 12~13 BM+005ch Bit Name Type Bit Name Type 24 Layer-2 AHB status FIFO 10~11 BM+0058h Bit Name Type Bit Name Type 27 26 25 LYR2_HDY7 RO 11 10 9 LYR2_HDY6 RO Layer-2 AHB status FIFO 8~9 BM+0054h Bit Name Type Bit Name Type BM_LYR2_FIFO 6 Layer-2 AHB status FIFO 6~7 24 23 22 21 20 8 7 6 5 4 19 18 17 LYR2_HSEL15 RO 3 2 1 LYR2_HSEL14 RO 16 0 BM keeps FIFOs internal recording HSEL and HREADY status on BUS for each layer. 0th is the latest one and 15th is the oldest. The FIFO only shifts when (EN=1) and (HTRANS=SEQ or NON-SEQ) and (HREADY=0) and (slaves’ HREADYs 87/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 differ from HDY0). If all above conditions meet, then (HRDY0=current HREADY on BUS) and (HRDY1=HRDY0) and (HRDY2=HRDY1) and … and (HRDY15=HRDY14). HSEL follows the same rules. HSELx The xth HSEL status on BUS bit0APB bit1SHARE1 bit2SHARE2 bit3IDMA1 bit4IDMA2 HRDYx The xth HREADY status on BUS bit0APB bit1SHARE1 bit2SHARE2 bit3IDMA1 bit4IDMA2 BM+0060h Bit Name Type Bit Name Type 31 15 BM+0064h Bit Name Type Bit Name Type 31 15 BM_LYR2_MFIF O0 Layer-2 AHB master FIFO 0~7 30 29 28 LYR2_MSEL7 RO 14 13 12 LYR2_MSEL3 RO 27 11 26 25 24 LYR2_MSEL6 RO 10 9 8 LYR2_MSEL2 RO 23 7 22 21 20 LYR2_MSEL5 RO 6 5 4 LYR2_MSEL1 RO 19 3 BM_LYR2_MFIF O8 Layer-2 AHB master FIFO 8~15 30 29 28 LYR2_MSEL15 RO 14 13 12 LYR2_MSEL11 RO 27 11 26 25 24 LYR2_MSEL14 RO 10 9 8 LYR2_MSEL10 RO 18 17 16 LYR2_MSEL4 RO 2 1 0 LYR2_MSEL0 RO 23 7 22 21 20 LYR2_MSEL13 RO 6 5 4 LYR2_MSEL9 RO 19 3 18 17 16 LYR2_MSEL12 RO 2 1 0 LYR2_MSEL8 RO BM keeps a specific FIFO for layer-2 AHB to record HMASTER. 0th is the latest one and 15th is the oldest. The FIFO only shifts when (EN=1) and (HTRANS=SEQ or NON-SEQ) and (HREADY=1) and (the bus transaction is caused by master which is enabled in LYR2_HMASTER). If all above conditions meet, then (MSEL0=current HMASTER_ENC) and (MSEL1=MSEL0) and (MSEL2=MSEL1) and … and (MSEL15=MSEL14). MSELx The xth MSEL status on BUS. 000 Vitual FIFO 001 DMA 010 Wavetable 011 USB 88/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 100 IRDGB1 101 IRDBG2 110 IRDA 111 PWM BM+0070h Bit Name Type Bit Name Type BM_LYR3_ACC NT Layer-3 AHB active cycle count 31 30 29 28 27 26 15 14 13 12 11 10 25 24 23 22 LYR3_ACCNT[31:16] RO 9 8 7 6 LYR3_ACCNT[15:0] RO 21 20 19 18 17 16 5 4 3 2 1 0 LYR3_ACCNT LYR3_ACCNT indicates how many cycles HTRANS is (non-IDLE and non-BUSY) and increments in every cycle when (EN=1) and (HTRANS=NON-SEQ or SEQ). LYR3_ACCNT is only cleared by CLR and is not affected by RESET. BM+0074h Bit Name Type Bit Name Type BM_LYR3_TCN T Layer-3 AHB transaction count 31 30 29 28 27 26 15 14 13 12 11 10 25 24 23 22 LYR3_TCNT[31:16] RO 9 8 7 6 LYR3_TCNT[15:0] RO 21 20 19 18 17 16 5 4 3 2 1 0 LYR3_TCNT LYR3_TCNT indicates transaction accumulation and increments in every cycle when (EN=1) and (HTRANS=NON-SEQ or SEQ) and (HREADY=1). LYR3_ACNT is only cleared by CLR and is not affected by RESET. BM+0078h Bit Name Type Bit Name Type BM_LYR3_WCN T Layer-3 AHB word count 31 30 29 28 27 26 15 14 13 12 11 10 25 24 23 22 LYR3_WCNT[31:16] RO 9 8 7 6 LYR3_WCNT[15:0] RO 21 20 19 18 17 16 5 4 3 2 1 0 LYR3_WCNT LYR3_WCNT indicates transaction of word counts been transferred and increases depends HSIZE in every cycle when (EN=1) and (HTRANS=NON-SEQ or SEQ) and (HREADY=1). A word means 4 bytes (32-bit) in this document. The total data counts transferred less then 1 word is truncated. (For example, the BUS transfers 33 bytes after EN=1. you will get 8 in WCNT. The last byte count is ignored.) LYR3_WCNT is only cleared by CLR and is not affected by RESET. HSIZE=00 8-bit data. WCNT increases 1. 89/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 HSIZE=01 HSIZE=10 OTHER BM+0090h Bit Name Type Bit Name Type 16-bit data. WCNT increases 2. 32-bit data. WCNT increases 4. Not supported. BM_LYR4_ACC NT Layer-4 AHB active cycle count 31 30 29 28 27 26 15 14 13 12 11 10 25 24 23 22 LYR4_ACCNT[31:16] RO 9 8 7 6 LYR4_ACCNT[15:0] RO 21 20 19 18 17 16 5 4 3 2 1 0 LYR4_ACCNT LYR4_ACCNT indicates how many cycles HTRANS is (non-IDLE and non-BUSY) and increments in every cycle when (EN=1) and (HTRANS=NON-SEQ or SEQ). LYR4_ACCNT is only cleared by CLR and is not affected by RESET. BM+0094h Bit Name Type Bit Name Type BM_LYR4_TCN T Layer-4 AHB transaction count 31 30 29 28 27 26 15 14 13 12 11 10 25 24 23 22 LYR4_TCNT[31:16] RO 9 8 7 6 LYR4_TCNT[15:0] RO 21 20 19 18 17 16 5 4 3 2 1 0 LYR4_TCNT LYR4_TCNT indicates transaction accumulation and increments in every cycle when (EN=1) and (HTRANS=NON-SEQ or SEQ) and (HREADY=1). LYR4_ACNT is only cleared by CLR and is not affected by RESET. BM+0098h Bit Name Type Bit Name Type BM_LYR4_WCN T Layer-4 AHB word count 31 30 29 28 27 26 15 14 13 12 11 10 25 24 23 22 LYR4_WCNT[31:16] RO 9 8 7 6 LYR4_WCNT[15:0] RO 21 20 19 18 17 16 5 4 3 2 1 0 LYR4_WCNT LYR4_WCNT indicates transaction of word counts been transferred and increases depends HSIZE in every cycle when (EN=1) and (HTRANS=NON-SEQ or SEQ) and (HREADY=1). A word means 4 bytes (32-bit) in this document. The total data counts transferred less then 1 word is truncated. (For example, the BUS transfers 33 bytes after EN=1. you will get 8 in WCNT. The last byte count is ignored.) LYR4_WCNT is only cleared by CLR and is not affected by RESET. HSIZE=00 8-bit data. WCNT increases 1. HSIZE=01 16-bit data. WCNT increases 2. 90/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 HSIZE=10 OTHER BM+00a0h Bit 31 BM_LYR4_FIFO 0 Layer-4 AHB FIFO 0~3 30 Name Type Bit 32-bit data. WCNT increases 4. Not supported. 29 28 27 26 LYR4_HDY3 25 14 13 23 22 LYR4_HSEL3 RO 15 24 21 11 10 9 7 6 5 4 LYR4_HDY1 LYR4_HSEL1 LYR4_HDY0 Type RO RO RO Bit 31 30 29 28 27 26 LYR4_HDY7 25 14 13 24 23 22 LYR4_HSEL7 21 11 10 9 7 6 5 4 LYR4_HDY5 LYR4_HSEL5 LYR4_HDY4 RO RO RO 31 30 29 28 27 26 LYR4_HDY11 RO 15 14 13 12 11 10 25 24 LYR4_HSEL1 1 RO 9 8 23 22 21 20 6 5 4 LYR4_HSEL9 LYR4_HDY8 RO RO RO 30 29 28 27 26 LYR4_HDY15 RO 15 3 2 14 13 12 Name LYR4_HDY13 Type RO 11 10 17 16 LYR4_HSEL 10 RO 1 0 LYR4_HSEL 8 RO BM_LYR4_FIFO C Layer-4 AHB FIFO 12~15 Name Type Bit 18 RO 7 LYR4_HDY9 BM+00ach 19 LYR4_HDY10 Type 31 2 17 16 LYR4_HSEL 6 RO 1 0 LYR4_HSEL 4 RO BM_LYR4_FIFO 8 Name Bit 3 Layer-4 AHB FIFO 8~11 Name Type Bit 18 RO 8 Type BM+00a8h 19 LYR4_HDY6 RO 12 20 Name Bit 2 17 16 LYR4_HSEL 2 RO 1 0 LYR4_HSEL 0 RO BM_LYR4_FIFO 4 RO 15 3 Layer-4 AHB FIFO 4~7 Name Type Bit 18 RO 8 Name BM+00a4h 19 LYR4_HDY2 RO 12 20 25 24 LYR4_HSEL1 5 RO 9 8 LYR4_HSEL1 3 RO 23 22 21 20 19 18 3 2 LYR4_HDY14 RO 7 6 5 4 LYR4_HDY12 RO 17 16 LYR4_HSEL 14 RO 1 0 LYR4_HSEL 12 RO BM keeps FIFOs internal recording HSEL and HREADY status on BUS for each layer. 0th is the latest one and 15th is the oldest. The FIFO only shifts when (EN=1) and (HTRANS=SEQ or NON-SEQ) and (HREADY=0) and (slaves’ HREADYs 91/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 differ from HDY0). If all above conditions meet, then (HRDY0=current HREADY on BUS) and (HRDY1=HRDY0) and (HRDY2=HRDY1) and … and (HRDY15=HRDY14). HSEL follows the same rules. HSELx The xth HSEL status on BUS bit0EMI bit1System memory HRDYx The xth HREADY status on BUS bit0EMI bit1System memory 92/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 3.7 External Memory Interface (6235) 3.7.1 General Description MT6235 incorporates a powerful and flexible memory controller, External Memory Interface, to connect with a variety of memory components. This controller provides one generic access scheme for FLASH Memory, SRAM, PSRAM and. Up to 4 memory banks can be supported simultaneously, BANK0-BANK3, with a maximum size of 128MB each. This controller also provides another access scheme for DRAM (SDR), and only one bank can be supported, with a maximum size of 128MB. The software program can treat different components by simply specifying certain predefined parameters. All these parameters are based on cycle time of system clock. The interface definition based on such scheme is listed in Table 13. Note that, this interface always operates data in Little Endian format for all types of accesses. Signal Name Type Description XADMUX I Define ADMUX or not in NOR flash / PSRAM EWAIT I Wait Signal Input ED[15:0] I/O Data Bus EA[26:0] I/O Address Bus ECS# [3:0] O BANK3~BANK0 Selection Signal EWR# O Write Enable Strobe ERD# O Read Enable Strobe EDQM[1:0]# O Data mask EADV# O Burst Mode FLASH Memory Address Latch Signal ERAS# O Row address latch signal (SDR DRAM) ECAS# O Column address latch signal (SDR DRAM) ECKE# O CLOK enable signal (SDR DRAM) EC_CLK O Burst Mode FLASH/PSRAM Memory Clock Signal ED_CLK O REGISTER ADDRESS DRAM clock signal Table 13 External Memory Interface of MT6235 REGISTER NAME SYNONYM EMI + 0000h PSRAM controller register for BANK0 EMI_CONA EMI + 0008h PSRAM controller register for BANK1 EMI_CONB EMI + 0010h PSRAM controller register for BANK2 EMI_CONC EMI + 0018h PSRAM controller register for BANK3 EMI_COND EMI + 0040h DRAM MR/EMR EMI_CONI EMI + 0048h DRAM controller timing configuration I EMI_CONJ 93/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 EMI + 0050h DRAM controller timing configuration II EMI_CONK EMI + 0058h DRAM controller read data path configuration EMI_CONL EMI + 0060h DRAM controller read delay timing configuration EMI_CONM EMI + 0068h DRAM controller function configuration EMI_CONN EMI + 0070h EMI General Control Register A EMI_GENA EMI + 0078h EMI General Control Register B EMI_GENB EMI + 0080h EMI General Control Register C EMI_GENC EMI + 0088h EMI General Control Register D EMI_GEND Table 14 External Memory Interface Register Map 3.7.2 Registers +0000h ~ 0018h Register Bit 31 30 Name PSIZE Type Reset Bit R/W 0 15 14 EMI_CONA~D 29 28 27 26 25 24 23 SRAM AD_M ADV_ AS_R AS_W AP_R WPLO _16 UX EN D R D R/W R/W R/W R/W R/W R/W R/W 0 1 0 0 1 1 0 13 12 11 10 9 8 7 22 6 21 20 19 18 17 16 AS_WAIT CS_END SY_SET R/W 7 5 R/W 1 R/W 0 4 Name WR_WAIT_1ST RD_WAIT_1ST AS_ADV AS_SET Type Reset R/W F R/W F R/W 3 R/W 3 3 2 1 0 WAIT_ RESE AS_HOLD EN RVED R/W R/W 0 3 PSIZE : Page size for page read mode PSIZE Sram_16 = 1 Sram_16 = 0 00 8 byte 4 byte 01 16 byte 8 byte 10 32 byte 16 byte WPOL : 1: Wait polarity change 0: Wait polarity not change SRAM_16 : 1: Data bit [15:0] 0: Data bit [ 7:0] ADMUX: 1: ADMUX type memory 0: Non ADMUX type memory ADVEN: 1: ADV enable in asynchronous read / write 0: ADV disable in asynchronous read / write 94/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 AS_RD: 1: Turn on asynchronous read 0: Turn off asynchronous read AS_WR: 1: Turn on asynchronous write 0: Turn off asynchronous write AP_RD: 1: Turn on asynchronous page read (burst-page read) 0: Turn off asynchronous page read(burst-page read) AS_WAIT: Adjust wait time in every transaction of asynchronous mode ( 0: 1clk , 1: 2clk ……) CS_END: Adjust CS disable time in the end of every transaction ( 0: 1clk , 1: 2clk ……) SY_SET: Adjust init set up time in every transaction of synchronous mode ( 0: 1clk , 1: 2clk ……) WR_WAIT_1st: Adjust first write wait time in every transaction of page read mode ( 0: 1clk , 1: 2clk ……) RD_WAIT_1st: Adjust first read wait time in every transaction of page read mode ( 0: 1clk , 1: 2clk ……) For synchronous mode, RD_WAIT_1st[1:0] is used to adjust read wait time in every transaction AS_ADV: Adjust ADV time in every transaction of asynchronous mode ( 0: 1clk , 1: 2clk ……) AS_SET: Adjust init set up time in every transaction of asynchronous mode ( 0: 1clk , 1: 2clk ……) WAIT_EN: 1: Pass XWAIT signal from external memory to controller 0: Skip XWAIT signal and pass 1 to controller AS_HOLD: Adjust hold time in every transaction of asynchronous and synchronus mode ( 0: 1clk , 1: 2clk ……) 95/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 +0040h Register EMI_CONI Bit 31 30 29 28 27 Name MBA1 MBA0 MA12 MA11 Type R/W R/W R/W R/W R/W Reset 0 0 0 0 0 Bit 15 14 13 12 11 EBA1 EBA1 Name EBA1 EBA0 2 1 Type R/W R/W R/W R/W R/W Reset 0 0 0 0 0 26 MA10 R/W 0 10 EBA1 0 R/W 0 25 MA9 R/W 0 9 24 MA8 R/W 0 8 23 MA7 R/W 0 7 22 MA6 R/W 0 6 21 MA5 R/W 0 5 20 MA4 R/W 0 4 19 MA3 R/W 0 3 18 MA2 R/W 0 2 17 MA1 R/W 0 1 16 MA0 R/W 0 0 EBA9 EBA8 EBA7 EBA6 EBA5 EBA4 EBA3 EBA2 EBA1 EBA0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 MBA1~0 : DRAM bank address setting when load mode register to DRAM MA12~0 : DRAM mode register value EBA1~0 : DRAM bank address setting when load extended mode register to DRAM EA12~0 : DRAM extended mode register value +0048h Bit 31 Name E_ES Type R/W Reset 0 Bit 15 Register 30 29 28 PRAL_CYC R/W 0 14 13 12 EMI_CONJ 27 11 26 25 REF_CYC R/W 0 10 9 24 8 Name ACT_RC_CYC ACT_RR_CYC Type Reset R/W 0 R/W 0 E_ES : Extend EXIT_SREF_CYC PRAL_CYC : DRAM pre-charge cycle time ( TRP) 23 22 21 20 EXIT_SREF_CYC R/W 0 7 6 5 4 WR_WAIT_C YC R/W 0 REF_CYC : DRAM refresh cycle time (TRFC) EXIT_SREF_CYC : DRAM exit self refresh to first valid command cycle time (TXSR) LDMR_CYC 19 18 3 2 17 16 LDMR_CYC R/W 0 1 0 RD_WAIT_C YC R/W 0 : DRAM load mode/e-mode register cycle time (TMRD) ACT_RC_CYC : DRAM active to read/write command delay cycle time (TRCD) ACT_RR_CYC : DRAM active bank A to active bank b delay cycle time (TRRD) WR_WAIT_CYC : DRAM write recovery cycle time (TWR) RD_WAIT_CYC : DRAM read command to pre-charge delay cycle time ( adjust final read command to pre-charge command delay cycle time 96/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 +0050h Bit Name Type Reset Bit Register EMI_CONK 31 30 29 28 27 26 25 24 15 14 PW_E N R/W 0 13 12 11 10 9 8 Name Type Reset PW_EN : Power on wait-count enable PW_CYC : Power on wait cycle time 31 15 20 19 18 17 16 5 4 3 2 1 0 18 R/W 0 : Auto refresh period cycle time ( TREF ) Bit Name Type Reset Bit Name Type Reset 21 PW_CYC REFP_CYC +0058h 23 22 REEP_CYC R/W 0 7 6 Register 30 29 EMI_CONL 28 27 26 25 24 DW_PSEL R/W 0 14 13 12 11 10 9 8 RAS_MIN_CYC PATH_SEL R/W R/W 0 0 23 22 21 20 19 7 6 5 4 3 17 16 DPD_CYC R/W 0 2 1 0 RD_DEL_SEL R/W 0 DW_PSEL : Define EMI output clock to DRAM phase select DW_PSEL[5:0] : Adjust phase delay --- > 1 tape (0.3~0.5 ns) DPD_CYC : Enter and exit DRAM power down state cycle time RAS_MIN_CYC : Active to pre-charge minimum cycle time PATH_SEL : Data input path select from external memory RD_DEL_SEL : Read data delay cycle time to read command (SDR SDRAM), include CAS latency, IO pad delay, PCB delay +0060h Bit Name 31 Register 30 29 28 EMI_CONM 27 26 25 24 97/599 23 22 21 20 19 18 17 16 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 Type Reset Bit Name Type Reset 15 14 13 12 11 10 RD_PDEL_SEL_BY1 R/W 0 9 8 7 6 RD_PDEL_SEL_BY1 : Read phase delay for DRAM input data bit [15:8] RD_PDEL_SEL_BY0 : Read phase delay for DRAM input data bit [ 7:0] +0068h Bit 31 15 4 3 2 RD_PDEL_SEL_BY0 R/W 0 Register 30 29 Name Type Reset Bit 5 14 13 1 0 EMI_CONN 28 27 26 25 24 PRAL AREF AREF LDMR LDEM _EN 1_EN 2_EN _EN R_EN R/W R/W R/W R/W R/W 0 0 0 0 0 12 11 10 9 8 23 22 7 21 20 19 Type Reset R/W 0 17 16 ADDR_TYPE DGB_EN R/W 0 5 R/W 0 6 4 3 SREF PDN_ SREF PDN_ _ST ST _EN EN Name 18 R/W 0 R/W 0 R/W 0 2 1 0 REF_ DRA CNT_ M_EN EN R/W R/W 0 0 PRAL_EN : Single pre-charge all enable ( for DRAM initialize) ARF1_EN : Single auto-refresh-1 enable ( for DRAM initialize) ARF2_EN : Single auto-refresh-2 enable ( for DRAM initialize) LDMR_EN : Single load mode register enable ( for DRAM initialize) LDEM_EN : Single load extended mode register enable ( for DRAM initialize) ADDR_TYPE : DRAM address type ADDR_TYPE 000 001 010 011 100 101 110 Row address bits 11 11 12 12 13 13 14 Bank address bits 1 2 2 2 2 2 2 Column address bits 8 8 8 9 9 10 10 DBG_EN : 00 : Normal mode Others : Internal debug mode, and do not set! 98/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 SREF_ST : 1 : DRAM in self refresh status 0 : DRAM exit self refresh status PDN_ST : 1 : DRAM in power down status 0 : DRAM exit power down status SREF_EN : 1 : DRAM enter self refresh 0 : DRAM exit self refresh PDN_EN : 1 : DRAM enter power down, when dram controller is IDLE ( the controller will exit power down status, and exercise auto refresh step to keep data correctable in DRAM, if the refresh time is end) 0 : DRAM will not enter power down . REF_CNT_EN : 1 : Enable auto refresh 0 : Disable auto refresh DRAM_EN : 1 : Enable DRAM controller 0 : Disable DRAM controller +0070h Bit 31 Register 30 29 28 EMI_GENA 27 Name SW_PSEL Type Reset Bit R/W 0 11 15 Name HDD Type R/W Reset 0 14 26 25 24 23 22 21 20 19 18 CRE_ SYW_ SYR_ CRE_ WRPS LSS VALU WTD WTD EN E R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 7 6 5 4 3 2 17 16 EST L2_E N R/W 0 1 R/W 1 0 13 12 10 9 8 SWAI SDAT SDAT SDAT AS_A ACTIV ACTIV M1_T M0_T T_NL A_NL CRAT SCLK DCLK RM1 _DLA _NDA P_RD E_WR E_RD OP OP E _EN _EN AT_E AT_E _DIS _DIS T_EN T_EN _D N N R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 0 0 0 0 0 RM0 R/W 0 SW_PSEL : Define EMI output clock to PSRAM phase select SW_PSEL[5:0] : Adjust phase delay --- > 1 tape (0.3~0.5 ns) CRE_EN 1: Assign EA26 as GPIO function for PSRAM CRE 0: disable CRE_VALUE Assign CRE output value 99/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 SYW_WTD : 1: Wait signal delay 1 more cycle at synchronous write mode of PSRAM 0: disable SYR_WTD : 1: Wait signal delay 1 more cycle at synchronous read mode of PSRAM 0: disable WRPS : 1: WRAP mode only PSRAM ( The PSRAM cannot support continues access mode) 0: disable LSS : 1: Low speed PSRAM ( clock rate of EMI to PSRAM is 2:1) 0: disable EST : 1: Extended PSRAM AS_WAIT timing 1 bit. 0: disable L2_EN : 1: Resolve data consistence problem from L2. 0: disable HDD : 1: Enable DRAM access at enough bus data rate without concern FIFO condition. 0: disable SWAIT_NLAT_EN : 1: Latch XWAIT signal by negative edge of HCLK_CK enable (for low speed operation , especially in FPGA ENV) 0: disable SDATA_NLAT_EN : 1: Latch XDATA(DEMUX) or XADDR(ADMUX) signal by negative edge of HCLK_CK enable (for low speed operation , especially in FPGA ENV) 0: disable CRATE: 1: If HDD is enable 0: disable SCLKEN : : SRAM controller clock out enable 1: Enable 0: Disable DCLKEN : 1: Enable 0: Disable DRAM controller clock out enable SDAT_DLAT_EN: SRAM input data sampled by DLAT_CLK positive edge like DRAM 100/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 1: Enable 0: Disable SDAT_NDLAT_EN: 1: Enable 0: Disable SRAM input data sampled by DLAT_CLK negative edge like DRAM AS_AP_RD_D: 1: Enable 0: Disable SRAM input data delay 1T ACTIVE_WR_DIS: 1: Enable 0: Disable Continuous active next access bank for DRAM write without pre-charge ACTIVE_RD_DIS: 1: Enable 0: Disable Continuous active next access bank for DRAM read without pre-charge M1_TOP : 1: Master-1 top priority on 0: Master-1 top priority off M0_TOP : 1: Master-0 top priority on 0: Master-0 top priority off 1: External boot 0: Internal boot When internal boot (RM1 = 0) is selected, ARM will fetch 2 fixed instructions from EMI and jump into the boot ROM area. During the boot ROM execution, RM1 must be set to 1 before burst transactions to EMI! RM1 : 1: CS[0]/CS[1] change 0: CS[0]/CS[1] not change RM0 : +0078h Bit Name Type Reset Bit Register EMI_GENB 31 30 29 28 27 26 15 14 13 12 11 10 Name Type Reset DCKSR : DCK Pad Slew Rate Control DCKEx : DCK Pad Driving Control SCKSR : SCK Pad Slew Rate Control 25 24 23 22 21 20 19 18 17 16 9 8 7 6 5 4 3 2 1 0 DCKS DCKE DCKE DCKE DCKE SCKS SCKE SCKE SCKE SCKE R 2 4 8 16 R 2 4 8 16 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 0 0 101/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 SCKEx : SCK Pad Driving Control +0080h Bit 31 Name Type Reset Bit 15 Name Type Reset Register 30 29 28 EMI_GENC 27 26 EAE1 EASR EAE2 EAE4 EAE8 6 R/W R/W R/W R/W R/W 0 0 0 0 0 14 13 12 11 10 ERWS ERWE ERWE ERWE ERWE R 2 4 8 16 R/W R/W R/W R/W R/W 0 0 0 0 0 EASR : Address Pad Slew Rate Control EAEx : Address Pad Driving Control EDSR : Data Pad Slew Rate Control EDEx : Data Pad Driving Control ECSSR : CS Pad Slew Rate Control ECSEx : CS Pad Driving Control ERWSR : RD/WR Pad Slew Rate Control ERWEx : RD/WR Pad Driving Control 25 24 23 22 EDSR EDE2 EDE4 EDE8 R/W R/W R/W R/W 0 0 0 0 9 8 7 6 EADV EADV EADV EADV SR E2 E4 E8 R/W R/W R/W R/W 0 0 0 0 21 EDE1 6 R/W 0 5 EADV E16 R/W 0 20 ECSS R R/W 0 4 ERCS R R/W 0 19 ECSE 2 R/W 0 3 ERCE 2 R/W 0 18 ECSE 4 R/W 0 2 ERCE 4 R/W 0 17 ECSE 8 R/W 0 1 ERCE 8 R/W 0 16 ECSE 16 R/W 0 0 ERCE 16 R/W 0 EADVSR : ADV Pad Slew Rate Control EADVEx : ADV Pad Driving Control ERCSR : ERCEx : RAS/CAS Pad Slew Rate Control RAS/CAS Pad Driving Control +0088h Bit 31 Name Type R/W Reset 0 Bit 15 Name Type R/W Reset 0 Register 30 R/W 0 14 R/W 0 29 28 27 S_PSEL_BY1 R/W R/W R/W 0 0 0 13 12 11 S_PSEL_BY0 R/W R/W R/W 0 0 0 EMI_GEND 26 25 24 23 22 21 20 R/W 0 10 R/W 0 9 R/W 0 8 R/W 0 7 R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 19 18 17 16 DRAM_CS_EN R/W R/W R/W R/W 0 0 0 0 3 2 1 0 SRAM_CS_EN R/W R/W R/W R/W 1 1 1 1 S_PDEL_SEL_BY1 : Read phase delay for SRAM input data bit [15:8] S_PDEL_SEL_BY0 : Read phase delay for SRAM input data bit [ 7:0] DRAM_CS_EN : From bank_3 to bank_0 ( only one bank can be turned on for DRAM controller) 102/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 1: Enable 0: Disable SRAM_CS_EN : 1: Enable 0: Disable From bank_3 to bank_0 ( all banks can be turned on, except the bank assigned to DRAM) 103/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 4 Microcontroller Peripherals Microcontroller (MCU) Peripherals are devices that are under direct control of the Microcontroller. Most of the devices are attached to the Advanced Peripheral Bus (APB) of the MCU subsystem, and serve as APB slaves. Each MCU peripheral must be accessed as a memory-mapped I/O device; that is, the MCU or the DMA bus master reads from or writes to the specific peripheral by issuing memory-addressed transactions. 4.1 Security Engine with JTAG control 4.1.1 General Description The Secure Engine module is responsible for security functions in the MT6235. SEJ realizes an efficient scheme to protect the program in non-volatile memory. Applying the flows in the IC with Chip-ID can: a) encrypted codes to protect the codes to be cracked (Confidentiality); b) guarantee the integrity; c) Copyright protection. To protect the program in the novo memory, SEJ references 1: Chip UID; 2: custom seed; 3: Internal reproducible noise to enlarge the entropy space of ciphering. After proper configuration in BCON and BSEED, users can encrypt program plaintext into cipher-texts and store them onto NoVo memory. Due to the program are stored in ciphered mode, it’s not easy to be disassembled. Further, the encryption process has referred to Chip UID, which may be different between two different chips, the cipher-text encrypted referred to Chip UIDA is very likely decrypted to wrong one referred to other IDs. 4.1.2 Register Definitions Figure 17: SEJ Registers Register Address Register Function Acronym SEJ + 00c0h SEJ Secure Booting control SEJ_BCON SEJ + 00c4h SEJ Secure Booting source data SEJ_BSRC SEJ + 00c8h SEJ Secure Booting seed data SEJ_BSEED SEJ + 00cch SEJ Secure Booting encrypted data SEJ_BENC SEJ + 00d0h SEJ Secure Booting decrypted data SEJ_BDEC SEJ + 00e0h SEJ Soft OTP SEJ_SO0 SEJ + 00e4h SEJ Soft OTP SEJ_SO1 SEJ + 00e8h SEJ Soft OTP SEJ_SO2 SEJ + 00ech SEJ Soft OTP SEJ_SO3 SEJ + 00f0h SEJ Soft OTP SEJ_SO4 SEJ + 00f4h SEJ Soft OTP SEJ_SO5 SEJ + 00f8h SEJ Soft OTP SEJ_SO6 SEJ + 00fch SEJ Soft OTP SEJ_SO7 SEJ+00c0h SEJ Secure Booting control Bit 31 Name Type 30 29 28 27 26 25 24 SEJ_BCON 23 22 104/599 21 20 19 18 17 16 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 Reset Bit 15 Name Type Reset 14 13 12 11 10 9 8 7 6 5 4 3 2 1 SOTP_LOCK R/W 0 0 DIS R/W 0 Disable Secure Booting function. When DIS is asserted, the data read from SEJ_BENC and SEJ_BDEC is the same as SEJ_BSRC. SOTP_LOCK SoftOTP lock bit. This bit can be modified from 0 to 1 and never return from 1 to 0. SEJ_SOx can be modified when OTP_LCOK=0. DIS SEJ+00c4h Bit Name Type Reset Bit Name Type Reset SEJ Secure Booting source data 31 30 29 28 27 26 25 15 14 13 12 11 10 9 24 23 BSRC[31:16] WO 0 8 7 BSRC[15:0] WO 0 SEJ_BSRC 22 21 20 19 18 17 16 6 5 4 3 2 1 0 BSRC Source data for Secure Booting to be encrypted (obtained from SEJ_BENC) or decrypted (obtained from SEJ_BDEC). SEJ+00c8h Bit Name Type Reset Bit Name Type Reset SEJ Secure Booting seed value 31 30 29 28 27 26 25 15 14 13 12 11 10 9 24 23 BSEED[31:16] WO 0 8 7 BSEED[15:0] WO 0 SEJ_BSEED 22 21 20 19 18 17 16 6 5 4 3 2 1 0 BSEED Seed data needed to increase security of the Boot Secure function. Secure the first time. SEJ+00cch Bit Name Type Reset Bit Name Type Reset Set the seed value before performing Boot SEJ Secure Booting encrypted data 31 30 29 28 27 26 25 15 14 13 12 11 10 9 24 23 BENC[31:16] RO 0 8 7 BENC[15:0] RO 0 SEJ_BENC 22 21 20 19 18 17 16 6 5 4 3 2 1 0 BENC Encrypted data from SEJ_BSRC. SEJ+00d0h Bit Name Type Reset Bit Name Type SEJ Secure Booting decrypted data 31 30 29 28 27 26 25 15 14 13 12 11 10 9 24 23 BDEC[31:16] RO 0 8 7 BDEC[15:0] RO 105/599 SEJ_BDEC 22 21 20 19 18 17 16 6 5 4 3 2 1 0 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 Reset 0 BDEC Decrypted data from SEJ_BSRC. SEJ+00e0h Bit Name Type Reset Bit Name Type Reset SEJ Soft OTP 31 30 29 28 27 26 25 24 23 22 SOFT_OTP[31:16] R/W 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 SOFT_OTP[15:0] R/W 5 4 3 2 1 0 SEJ+00e4h Bit Name Type Reset Bit Name Type Reset SEJ Soft OTP 30 29 28 27 26 25 24 23 22 SOFT_OTP[63:48] R/W 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 SOFT_OTP[47:32] R/W 5 4 3 2 1 0 SEJ Soft OTP 30 29 28 27 26 25 24 23 22 SOFT_OTP[95:80] R/W 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 SOFT_OTP[79:64] R/W 5 4 3 2 1 0 SEJ Soft OTP SEJ_SO3 31 30 29 28 27 26 25 24 23 22 SOFT_OTP[127:112] R/W 21 20 19 18 17 16 15 14 13 12 11 10 9 5 4 3 2 1 0 SEJ+00f0h Bit Name Type Reset Bit Name Type Reset SEJ_SO2 31 SEJ+00ech Bit Name Type Reset Bit Name Type Reset SEJ_SO1 31 SEJ+00e8h Bit Name Type Reset Bit Name Type Reset SEJ_SO0 8 7 6 SOFT_OTP[111:96] R/W SEJ Soft OTP SEJ_SO4 31 30 29 28 27 26 25 24 23 22 SOFT_OTP[159:144] R/W 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 SOFT_OTP[143:128] R/W 5 4 3 2 1 0 106/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 SEJ+00f4h Bit Name Type Reset Bit Name Type Reset SEJ Soft OTP 31 30 29 28 27 26 25 24 23 22 SOFT_OTP[191:176] R/W 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 SOFT_OTP[175:160] R/W 5 4 3 2 1 0 SEJ+00f8h Bit Name Type Reset Bit Name Type Reset SEJ Soft OTP SEJ_SO6 31 30 29 28 27 26 25 24 23 22 SOFT_OTP[223:208] R/W 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 SOFT_OTP[207:192] R/W 5 4 3 2 1 0 SEJ+00fch Bit Name Type Reset Bit Name Type Reset SEJ_SO5 SEJ Soft OTP SEJ_SO7 31 30 29 28 27 26 25 24 23 22 SOFT_OTP[255:240] R/W 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 SOFT_OTP[239:224] R/W 5 4 3 2 1 0 SEJ_SO Software control values for Secure Booting usage (SEJ_BENC/SEJ_BDEC). SOFTOTP is one parameter of all for encryption/decryption function. This register can be modify when OTP_LOCK=0. 4.2 EFUSE Controller (efusec) 4.2.1 General Description There are six 64-bit EFUSE macros in the chip. EFUSE macro is a one-time-programming non-volatile memory. We usually use it as storage of sensitive and important data. EFUSE controller delivers EFUSE status and re-initializes EFUSE macro. You can program the EFUSE via EFUSE controller with proper configuration and sequences. 4.2.2 Register Definitions EFUSEC+0000 EFUSE control h Bit Name Type Reset Bit EFUSEC_CON 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 107/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 Name Type Reset ESEL R/W 0 WSEL R/W 0 F52M R/W 0 RD WO 0 BUSY VLD RO RO 0 0 Indicate if EFUSE data are valid or not. EFUSEC will initialize all EFUSE macros automatically. After finishing the initialization, this bit will change to 1 from 0. In other case, if you initialize EFUSE macros by write RD=1 manually, the VLD will go to low. After RD process done, VLD will go to high again. BUSY EFUSE controller is busy. You can write EFUSEC control registers only when BUSY is low. RD Initialize EFUSE macros manually. The BUSY is 1 and VLD is 0 while EFUSEC re-initialize all EFUSE macros. After finishing the initialization, BUSY changes to 0 and VLD changes to 1. F52M System bus speed selection. Change this field depends on the reality. 0 System bus frequency is 26MHz 1 System bus frequency is 52MHz WSEL EFUSE word selection. There are 2 32-bit words in each EFUSE macro. You should decide which word you will program ESEL EFUSE macro selection. There are 6 EFUSE macros in the system. You should decide which macro you will program ESEL WSEL EFUSE_Dx VLD 001 001 010 010 011 011 100 100 101 101 0 1 0 1 0 1 0 1 0 1 EFUSE_D0 EFUSE_D1 EFUSE_D2 EFUSE_D3 EFUSE_D4 EFUSE_D5 EFUSE_D6 EFUSE_D7 EFUSE_D8 EFUSE_D9 EFUSEC+0004 EFUSE write data h Bit Name Type Reset Bit Name Type Reset EFUSEC_WDAT 31 30 29 28 27 26 25 15 14 13 12 11 10 9 24 23 WDAT[31:16] R/W N/A 8 7 WDAT[15:0] R/W N/A 22 21 20 19 18 17 16 6 5 4 3 2 1 0 WDAT After setting the EFUSE_SEL and WSEL, you can write WDAT with values you want to program. Once you write EFUSEC_WDAT, EFUSEC starts blowing EFUSE operation. The BUSY flag rises. After the EFUSEC finished the blowing process, the BUSY flag lowers. You can follow the guidelines below: 1. Wait until BUSY is 0 2. Set VCCQ=3.7V from 2.8V; VFSOURCE=3.7V from Hi-Z or Ground 3. Set ESEL and WSEL. 4. Write EFUSEC_WDAT with your prefer value. 5. Wait until BUSY is 0 108/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 6. If you want to blow other EFUSE macro, jump step 1 7. Set VCCQ=2.8V; VFSOURCE=Hi-Z or Ground 8. Write RD = 1. Wait BUSY=0 and VALID=1. Check the EFUSE contents you blew. Notice: each bit valued 1 in WDAT means a blowing operation. Blown bits can not be blown again. Such that the final EFUSE content should be the original EFUSE content OR WDAT. EFUSEC+0010 EFUSE data out h Bit Name Type Reset Bit Name Type Reset EFUSE_D0 31 30 29 28 27 26 25 15 14 13 12 11 10 9 24 23 EFUSE_D0 R/W 0 8 7 EFUSE_D0 R/W 0 22 21 20 19 18 17 16 6 5 4 3 2 1 0 EFUSEC+0014 EFUSE data out h Bit 31 D01W Name P Type R/W Reset 0 Bit 15 Name Type Reset 30 29 28 27 EFUSE_D1 26 25 24 23 22 21 20 19 18 17 16 6 5 4 3 2 1 0 EFUSE_D1 14 13 12 11 10 9 R/W 0 8 7 EFUSE_D1 R/W 0 EFUSEC+0018 EFUSE data out h Bit Name Type Reset Bit Name Type Reset EFUSE_D2 31 30 29 28 27 26 25 15 14 13 12 11 10 9 24 23 EFUSE_D2 R/W 0 8 7 EFUSE_D2 R/W 0 22 21 20 19 18 17 16 6 5 4 3 2 1 0 EFUSEC+001c EFUSE data out h Bit 31 D23W Name P Type R/W Reset 0 Bit 15 Name 30 29 28 27 EFUSE_D3 26 25 24 23 22 21 20 19 18 17 16 6 5 4 3 2 1 0 EFUSE_D3 14 13 12 11 10 9 R/W 0 8 7 EFUSE_D3 109/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 Type Reset R/W 0 EFUSEC+0020 EFUSE data out h Bit Name Type Reset Bit Name Type Reset EFUSE_D4 31 30 29 28 27 26 25 15 14 13 12 11 10 9 24 23 EFUSE_D4 R/W 0 8 7 EFUSE_D4 R/W 0 22 21 20 19 18 17 16 6 5 4 3 2 1 0 EFUSEC+0024 EFUSE data out h Bit 31 D45W Name P Type R/W Reset 0 Bit 15 Name Type Reset 30 29 28 27 EFUSE_D5 26 25 24 23 22 21 20 19 18 17 16 6 5 4 3 2 1 0 EFUSE_D5 14 13 12 11 10 9 R/W 0 8 7 EFUSE_D5 R/W 0 EFUSEC+0028 EFUSE data out h Bit Name Type Reset Bit Name Type Reset EFUSE_D6 31 30 29 28 27 26 25 15 14 13 12 11 10 9 24 23 EFUSE_D6 R/W 0 8 7 EFUSE_D6 R/W 0 22 21 20 19 18 17 16 6 5 4 3 2 1 0 EFUSEC+002c EFUSE data out h Bit 31 D67W Name P Type R/W Reset 0 Bit 15 Name Type Reset 30 29 28 27 EFUSE_D7 26 25 24 23 22 21 20 19 18 17 16 6 5 4 3 2 1 0 EFUSE_D7 14 13 12 11 10 9 R/W 0 8 7 EFUSE_D7 R/W 0 110/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 EFUSEC+0030 EFUSE data out h Bit Name Type Reset Bit Name Type Reset EFUSE_D8 31 30 29 28 27 26 25 15 14 13 12 11 10 9 24 23 EFUSE_D8 R/W 0 8 7 EFUSE_D8 R/W 0 22 21 20 19 18 17 16 6 5 4 3 2 1 0 EFUSEC+0034 EFUSE data out h Bit 31 D89W Name P Type R/W Reset 0 Bit 15 Name Type Reset 30 29 28 27 EFUSE_D9 26 25 24 23 22 21 20 19 18 17 16 6 5 4 3 2 1 0 EFUSE_D9 14 13 12 11 10 9 R/W 0 8 7 EFUSE_D9 R/W 0 EFUSE_Dx EFUSE Dx output data DxyWP Write protection bit for EFUSE_Dx and EFUSE_Dy 0 EFUSE_Dx and EFUSE_Dy can be blown. 1 EFUSE_Dx and EFUSE_Dy can not be blown. 4.3 4.3.1 Pulse-Width Modulation Outputs General Description Six generic pulse-width modulators are implemented to generate pulse sequences with programmable frequency and duration for LCD backlight, charging or other purpose. Before enabling PWM, the pulse sequences must be prepared either in the memory or registers. Then PWM, as shown in Fig. 1, will read the pulse sequences to generate random waveform to meet all kinds of applications. ...... DATA PWM 32-bit Fig. 1 The generation procedure of PWM. 111/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 There are two basic operational modes about PWM, which is set by PWM_MODE. In periodical mode, all pulse sequence with be repeatedly generated by the number of WAVE_NUM[15:0]. If WAVE_NUM is 0 which means infinite, the waveform generation could be stopped by PWM_EN. As for the pulse sequence data source in the periodical mode, if the data are less than or equal to 64 bits, they can be directly set in SEND_DATA0[31:0] and SEND_DATA1[31:0] and SRCSEL=0 to reduce memory bandwidth. STOP_BITPOS[5:0] is used to indicate the stop bit position in the total 64-bits data. For example, if STOP_BITPOS is 0, only SEND_DATA0[0] will be generated, and so on until SEND_DATA1[31]. If SRCSEL=1 which means memory mode, the pulse sequence data are put in memory with address set by BUF0_BASE_ADDR and the length is BUF0_SIZE. STOP_BITPOS[4:0] is to indicate the stop bit position in the last 32-bits data. The format of pulse sequences that stored in periodical mode is as shown in Fig. 2. SEND DATA1 Memory SEND DATA0 64-bit or 32-bit Fig. 2 The pulse sequence in periodical mode. On the other hand, the pulse sequence is stored in dual memory buffers in random mode. The format of pulse sequences that stored in the memory is as shown in Fig. 3. Valid bit is used to indicate data are ready in the respective memory buffer. The PWM generation will clear this bit after all data in that buffer are fetched. The memory buffers are set by address BUF0_BASE_ADDR and BUF0_SIZE for memory buffer0 and BUF1_BASE_ADDR and BUF1_SIZE for memory buffer1. The program should prepare the pulse sequence and set the valid to 1 in time before all data in the other memory buffer are fetched or the HW will issue UNDERFLOW interrupt to inform pulse generation will be stopped because of no valid data. Valid 0 Memory 1 Memory 0 Valid 1 32-bit 32-bit Fig. 3 The pulse sequence in random mode PWM always reference bus block clock or 13MHz clock as base, and CLKDIV[2:0] and CLKSEL can decide the sample rate of each PWM. When system is in the sleep mode, block clock will be disabled and only OLD_PWM_MODE with CLKSEL=1 (32 KHz) is supported. Only PWM1, PWM2 and PWM3 support OLD_PWM_MODE. For each sample 112/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 output, the duration is decided by HDURATION[15:0] when output is high and LDURATION[15:0] when output is low. If the pulse sequence is repeated which is specified by WAVE_NUM[15:0], a special output could be set by GUARD_VALUE and GUARD_DURATION[15:0] between these pulse sequence. The PWM output will be the value specified by IDLE_VALUE when PWM is not enabled or the pulse sequence is finished. lduration hduration guard_value ~ 0 1 idle_value ~ ~ … 1 0 … 0 1 ~ … 1 1 0 … 1 guard_duration send_data1 send_data0 send_data1 send_data0 Fig. 4 The pulse sequence output pattern In order to provide precise timing relation between different PWM outputs, we provide PWM_SEQ_MODE. In this mode, the starting position of waveform outputs of PWM3, PWM4, PWM5 and PWM6 will follow the previous one by the delay values PWM4_DEALY_DURATION[15:0], PWM5_DEALY_DURATION[15:0] and PWM6_DEALY_DURATION[15:0]. Also the clock scale of each delay can be specified by PWM4_DELAY_CLKSEL, PWM5_DELAY_CLKSEL and PWM6_DELAY_CLKSEL. PWM3 PWM4_delay_duration PWM4 PWM5_delay_duration PWM5 PWM6_delay_duration PWM6 Fig. 5 The sequential output mode Also PWM1, PWM2 and PWM3 support original PWM output mode. The output waveform is specified by DATA_WIDTH[12:0] and THRESH[12:0]. The output waveform is shown in Fig. 6. guard_value pwm_thresh pwm_thresh data_width guard_period data_width Fig. 6 The old PWM mode For hardware and system consideration, CLKSRC might be slightly different in different situations. The following table is to summary all possible situations. 113/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 PWM_OLD_MODE PWM_CLKSEL PWM_FIX_CLK_MODE CLKSRC 0 block clock 1 13 MHz NA* 32 KHz 0 1 1 0 0 1 0 block clock 1 13 MHz 0 block clock / 1625 1 13 MHz/1625 = 8 KHz *: When both PWM_OLD_MODE and PWM_CLKSEL equal to 1, PWM_FIX_CLK_MODE should be 0 to avoid malfunction. 4.3.2 Register Table Register Address Register Function Acronym PWM + 0000h PWM enable register PWM_ENABLE PWM + 0004h PWM4 delay duration register PWM4_DELAY PWM + 0008h PWM5 delay duration register PWM5_DELAY PWM + 000Ch PWM6 delay duration register PWM6_DELAY PWM + 0010h PWM1 control register PWM1_CON PWM + 0014h PWM1 high duration register PWM1_HDURATION PWM + 0018h PWM1 low duration register PWM1_LDURATION PWM + 001Ch PWM1 guard duration register PWM1_GDURATION PWM + 0020h PWM1 buffer0 base address register PWM1_BUF0_BASE_ADDR PWM + 0024h PWM1 buffer0 size register PWM1_BUF0_SIZE PWM + 0028h PWM1 buffer1 base address register PWM1_BUF1_BASE_ADDR PWM + 002Ch PWM1 buffer1 size register PWM1_BUF1_SIZE PWM + 0030h PWM1 send data0 register PWM1_SEND_DATA0 PWM + 0034h PWM1 send data1 register PWM1_SEND_DATA1 PWM + 0038h PWM1 wave number register PWM1_WAVE_NUM PWM + 003Ch PWM1 data width PWM1_DATA_WIDTH PWM + 0040h PWM1 threshold register PWM1_THRESH PWM + 0044h PWM1 send waveform number register PWM1_SEND_WAVENUM PWM + 0048h PWM1 valid register PWM1_VALID PWM + 0050h PWM2 control register PWM2_CON PWM + 0054h PWM2 high duration register PWM2_HDURATION PWM + 0058h PWM2 low duration register PWM2_LDURATION 114/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 PWM + 005Ch PWM2 guard duration register PWM2_GDURATION PWM + 0060h PWM2 buffer0 base address register PWM2_BUF0_BASE_ADDR PWM + 0064h PWM2 buffer0 size register PWM2_BUF0_SIZE PWM + 0068h PWM2 buffer1 base address register PWM2_BUF1_BASE_ADDR PWM + 006Ch PWM2 buffer1 size register PWM2_BUF1_SIZE PWM + 0070h PWM2 send data0 register PWM2_SEND_DATA0 PWM + 0074h PWM2 send data1 register PWM2_SEND_DATA1 PWM + 0078h PWM2 wave number register PWM2_WAVE_NUM PWM + 007Ch PWM2 data width PWM2_DATA_WIDTH PWM + 0080h PWM2 threshold register PWM2_THRESH PWM + 0084h PWM2 send waveform number register PWM2_SEND_WAVENUM PWM + 0088h PWM2 valid register PWM2_VALID PWM + 0090h PWM3 control register PWM3_CON PWM + 0094h PWM3 high duration register PWM3_HDURATION PWM + 0098h PWM3 low duration register PWM3_LDURATION PWM + 009Ch PWM3 guard duration register PWM3_GDURATION PWM + 00A0h PWM3 buffer0 base address register PWM3_BUF0_BASE_ADDR PWM + 00A4h PWM3 buffer0 size register PWM3_BUF0_SIZE PWM + 00A8h PWM3 buffer1 base address register PWM3_BUF1_BASE_ADDR PWM + 00ACh PWM3 buffer1 size register PWM3_BUF1_SIZE PWM + 00B0h PWM3 send data0 register PWM3_SEND_DATA0 PWM + 00B4h PWM3 send data1 register PWM3_SEND_DATA1 PWM + 00B8h PWM3 wave number register PWM3_WAVE_NUM PWM + 00BCh PWM3 data width PWM3_DATA_WIDTH PWM + 00C0h PWM3 threshold register PWM3_THRESH PWM + 00C4h PWM3 send waveform number register PWM3_SEND_WAVENUM PWM + 00C8h PWM3 valid register PWM3_VALID PWM + 00D0h PWM4 control register PWM4_CON PWM + 00D4h PWM4 high duration register PWM4_HDURATION PWM + 00D8h PWM4 low duration register PWM4_LDURATION PWM + 00DCh PWM4 guard duration register PWM4_GDURATION PWM + 00E0h PWM4 buffer0 base address register PWM4_BUF0_BASE_ADDR PWM + 00E4h PWM4 buffer0 size register PWM4_BUF0_SIZE PWM + 00E8h PWM4 buffer1 base address register PWM4_BUF1_BASE_ADDR PWM + 00ECh PWM4 buffer1 size register PWM4_BUF1_SIZE PWM + 00F0h PWM4 send data0 register PWM4_SEND_DATA0 PWM + 00F4h PWM4 send data1 register PWM4_SEND_DATA1 115/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 PWM + 00F8h PWM4 wave number register PWM4_WAVE_NUM PWM + 00FCh PWM4 send waveform number register PWM4_SEND_WAVENUM PWM + 0100h PWM4 valid register PWM4_VALID PWM + 0110h PWM5 control register PWM5_CON PWM + 0114h PWM5 high duration register PWM5_HDURATION PWM + 0118h PWM5 low duration register PWM5_LDURATION PWM + 011Ch PWM5 guard duration register PWM5_GDURATION PWM + 0120h PWM5 buffer0 base address register PWM5_BUF0_BASE_ADDR PWM + 0124h PWM5 buffer0 size register PWM5_BUF0_SIZE PWM + 0128h PWM5 buffer1 base address register PWM5_BUF1_BASE_ADDR PWM + 012Ch PWM5 buffer1 size register PWM5_BUF1_SIZE PWM + 0130h PWM5 send data0 register PWM5_SEND_DATA0 PWM + 0134h PWM5 send data1 register PWM5_SEND_DATA1 PWM + 0138h PWM5 wave number register PWM5_WAVE_NUM PWM + 013Ch PWM5 send waveform number register PWM5_SEND_WAVENUM PWM + 0140h PWM5 valid register PWM5_VALID PWM + 0150h PWM6 control register PWM6_CON PWM + 0154h PWM6 high duration register PWM6_HDURATION PWM + 0158h PWM6 low duration register PWM6_LDURATION PWM + 015Ch PWM6 guard duration register PWM6_GDURATION PWM + 0160h PWM6 buffer0 base address register PWM6_BUF0_BASE_ADDR PWM + 0164h PWM6 buffer0 size register PWM6_BUF0_SIZE PWM + 0168h PWM6 buffer1 base address register PWM6_BUF1_BASE_ADDR PWM + 016Ch PWM6 buffer1 size register PWM6_BUF1_SIZE PWM + 0170h PWM6 send data0 register PWM6_SEND_DATA0 PWM + 0174h PWM6 send data1 register PWM6_SEND_DATA1 PWM + 0178h PWM6 wave number register PWM6_WAVE_NUM PWM + 017Ch PWM6 send waveform number register PWM6_SEND_WAVENUM PWM + 0180h PWM6 valid register PWM6_VALID PWM + 0190h PWM interrupt enable register PWM_INT_ENABLE PWM + 0194h PWM interrupt status register PWM_INT_STATUS PWM + 0198h PWM interrupt acknowledge register PWM_INT_ACK Table 15 PWM Registers 116/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 4.3.3 Register Definitions PWM+0000h Bit Name Type Reset Bit PWM Enable register PWM_ENABLE 31 30 29 28 27 26 25 24 15 14 13 12 11 10 9 8 Name Type Reset 23 22 21 20 19 18 17 16 7 6 5 4 3 2 1 0 PWM_ DELA PWM_ PWM6 PWM5 PWM4 PWM3 PWM2 PWM1 Y_FIX SEQ_ _CLK _EN _EN _EN _EN _EN _EN MODE _MOD E R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 PWM1_EN Set to 1 to enable PWM1 PWM2_EN Set to 1 to enable PWM2 PWM3_EN Set to 1 to enable PWM3 PWM4_EN Set to 1 to enable PWM4 PWM5_EN Set to 1 to enable PWM5 PWM6_EN Set to 1 to enable PWM6 PWM_SEQ_MODE Set to 1 to enable PWM3, PWM4, PWM5 and PWM6 sequential delay mode. In this mode, PWM3 starts first and then after PWM4_DELAY_TIME, PWM4 will start. After PWM4 starts, PWM5 will start after PWM5_DELAY_TIME and so on for PWM6. Note: The output of PWM_SEQ_MODE is started after PWM3 is enabled. And PWM_SEQ_MODE should be set before PWM4, PWM5 and PWM6 are enabled or at the same time. Also this mode doesn’t work when PWM3 is set at OLD_PWM_MODE and CLKSEL=1. PWM_DELAY_FIX_CLK_MODE Set to 1 to force all delay between PWM3, PWM4, PWM5 and PWM6 in unit of 13MHz clock rather than block clock. PWM+0004h Bit PWM4 Delay Duration register 25 24 PWM4_DELAY 31 30 29 28 27 26 23 22 21 20 19 18 17 15 14 13 12 11 10 9 8 7 6 5 PWM4_DELAY_DURATION[15:0] R/W 0 4 3 2 1 Name Type Reset Bit Name Type Reset 16 DELA Y_CL KSEL R/W 0 0 PWM4_DELAY_DURATION The time difference between PWM3 and PWM4. DELAY_CLKSEL The clock unit of PWM4_DELAY_DURATION. 0 CLK=CLKSRC 1 CLK=CLKSRC/1625 117/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 PWM+0008h Bit PWM5 Delay Duration register 25 24 PWM5_DELAY 31 30 29 28 27 26 23 22 21 20 19 18 17 15 14 13 12 11 10 9 8 7 6 5 PWM5_DELAY_DURATION[15:0] R/W 0 4 3 2 1 Name Type Reset Bit Name Type Reset 16 DELA Y_CL KSEL R/W 0 0 PWM5_DELAY_DURATION The time difference between PWM4 and PWM5. DELAY_CLKSEL The clock unit of PWM5_DELAY_DURATION. 0 CLK=CLKSRC 1 CLK=CLKSRC/1625 PWM+000Ch Bit PWM6 Delay Duration register 25 24 PWM6_DELAY 31 30 29 28 27 26 23 22 21 20 19 18 17 15 14 13 12 11 10 9 8 7 6 5 PWM6_DELAY_DURATION[15:0] R/W 0 4 3 2 1 Name Type Reset Bit Name Type Reset 16 DELA Y_CL KSEL R/W 0 0 PWM6_DELAY_DURATION The time difference between PWM5 and PWM6. DELAY_CLKSEL The clock unit of PWM6_DELAY_DURATION. 0 CLK=CLKSRC 1 CLK=CLKSRC/1625 PWM+0010h Bit Name Type Reset Bit 31 15 OLD_ Name PWM_ MODE Type R/W Reset 0 PWM1 Control register 30 29 28 27 26 25 14 13 12 11 10 9 STOP_BITPOS[5:0] R/W 3Fh PWM1_CON 24 23 22 21 8 7 6 5 GUAR IDLE_ SRCS D_VA VALU MODE EL E LUE R/W R/W R/W R/W 0 0 0 0 20 19 4 3 FIX_C CLKS LK_M EL ODE R/W R/W 0 0 18 17 16 2 1 0 CLKDIV [2:0] R/W 0 CLKDIV Select PWM1 clock scale. 000 CLK Hz 001 CLK/2 Hz 010 CLK/4 Hz 118/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 011 CLK/8 Hz 100 CLK/16 Hz 101 CLK/32 Hz 110 CLK/64 Hz 111 CLK/128 Hz CLKSEL Select PWM1 clock 0 CLK=CLKSRC 1 CLK=CLKSRC/1625 FIX_CLK_MODE Select PWM1 clock reference 0 CLKSRC= block clock 1 CLKSRC= 13 MHz SRCSEL Select PWM1 data source 0 FIFO mode 1 Memory mode MODE Select Random Generator mode 0 Periodical PWM mode. 1 Random PWM mode Note: When using random generator mode, the data source comes from dual buffers in memory. IDLE_VALUE PWM1 output value when idle state. GUARD_VALUE PWM1 output value when guard time. STOP_BITPOS The stop bit position for source data in periodical mode. In FIFO mode, it’s used to indicate the stop bit position in total 64 bits. In Memory mode, it’s for the stop bit position in the last 32 bits. OLD_PWM_MODE Use old PWM mode 0 New PWM mode 1 Old PWM mode Note: Using old PWM mode also means periodical mode. So SRCSEL and MODE is ignored in this situation. Only old PWM mode with 32 KHz clock source could work in the system sleep-mode. PWM+0014h Bit Name Type Reset Bit Name Type Reset PWM1_HDURAT ION PWM1 High Duration register 31 30 29 28 27 26 25 15 14 13 12 11 10 9 24 23 22 21 20 19 18 17 16 8 7 6 HDURATION[15:0] R/W 1 5 4 3 2 1 0 HDURATION PWM1 pulse duration based on the current clock when PWM output is high. If duration =N, need to program N-1 in this register. Note: The duration of PWM must not be 0. 119/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 PWM+0018h Bit Name Type Reset Bit Name Type Reset PWM1_LDURAT ION PWM1 Low Duration register 31 30 29 28 27 26 25 15 14 13 12 11 10 9 24 23 22 21 20 19 18 17 16 8 7 6 LDURATION[15:0] R/W 1 5 4 3 2 1 0 LDURATION PWM1 pulse duration based on the current clock when PWM output is low. If duration =N, need to program N-1 in this register. Note: The duration of PWM must not be 0. PWM+001Ch Bit Name Type Reset Bit Name Type Reset PWM1_GDRUA TION PWM1 Guard Duration register 31 30 29 28 27 26 15 14 13 12 11 10 25 24 23 22 9 8 7 6 GUARD_DURATION[15:0] R/W 0 21 20 19 18 17 16 5 4 3 2 1 0 GUDAR_DURATION It’s the guarding interval between individual waveforms and the output is decided by GUARD_VALUE. Also if it equals to N, it needs to program N-1 in this register. Note: If this duration is 0, it means no guarding interval. PWM+0020h Bit Name Type Reset Bit Name Type Reset 31 30 29 28 27 26 15 14 13 12 11 10 BUF0_BS_ADDR PWM+0024h Bit Name 31 30 PWM1_BUF0_BAS E_ ADDR PWM1 Buffer0 Base Address register 25 24 23 22 BUF0_BS_ADDR[31:16] R/W 0 9 8 7 6 BUF0_BS_ADDR[15:0] R/W 0 21 20 19 18 17 16 5 4 3 2 1 0 The base address of memory buffer0 for PWM1’s waveform data. PWM1_BUF0_SI ZE PWM1 Buffer0 Size register 29 28 27 26 25 24 120/599 23 22 21 20 19 18 17 16 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 Type Reset Bit Name Type Reset 15 14 13 12 11 10 9 8 7 6 BUF0_SIZE[15:0] R/W 0 5 4 3 2 1 0 BUF0_SIZEThe length of the waveform data in memory buffer0 that PWM1 should generate. If it equals to N, need to program N-1 in this register. Note: The size is in unit of 32-bit data. PWM+0028h Bit Name Type Reset Bit Name Type Reset PWM1_BUF1_ _BASE_ ADDR PWM1 Buffer1 Base Address register 31 30 29 28 27 26 15 14 13 12 11 10 25 24 23 22 BUF1_BS_ADDR[31:16] R/W 0 9 8 7 6 BUF1_BS_ADDR[15:0] R/W 0 21 20 19 18 17 16 5 4 3 2 1 0 BUF1_BS_ADDR The base address of memory buffer1 for PWM1’s waveform data. Note: The memory buffer1 is useless in periodical mode. PWM+002Ch Bit Name Type Reset Bit Name Type Reset PWM1_BUF1_SI ZE PWM1 Buffer1 Size register 31 30 29 28 27 26 25 15 14 13 12 11 10 9 24 23 22 21 20 19 18 17 16 8 7 6 BUF1_SIZE[15:0] R/W 0 5 4 3 2 1 0 BUF1_SIZEThe length of the waveform data in memory buffer1 that PWM1 should generate. If it equals to N, need to program N-1 in this register. PWM+0030h Bit Name Type Reset Bit Name Type Reset PWM1_SEND_DAT A0 PWM1 Send Data0 register 31 30 29 28 27 26 15 14 13 12 11 10 25 24 23 22 SEND_DATA0 [31:16] R/W 0 9 8 7 6 SEND_DATA0[15:0] R/W 0 121/599 21 20 19 18 17 16 5 4 3 2 1 0 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 SEND_DATA0 PWM1 local buffer0 of pulse sequence data to be generated. Note: This value should be written only in periodically FIFO mode. In other mode, this buffer is for internal memory access. PWM+0034h Bit Name Type Reset Bit Name Type Reset PWM1_SEND_DAT A1 PWM1 Send Data1 register 31 30 29 28 27 26 15 14 13 12 11 10 25 24 23 22 SEND_DATA1[31:16] R/W 0 9 8 7 6 SEND_DATA1[15:0] R/W 0 21 20 19 18 17 16 5 4 3 2 1 0 SEND_DATA1 PWM1 local buffer0 of pulse sequence data to be generated. Note: This value should be written only in periodically FIFO mode. In other mode, this buffer is for internal memory access. PWM+0038h Bit Name Type Reset Bit Name Type Reset PWM1_WAVE_ NUM PWM1 Wave Number register 31 30 29 28 27 26 25 15 14 13 12 11 10 9 24 23 22 21 20 19 18 17 16 8 7 6 WAVE_NUM[15:0] R/W 0 5 4 3 2 1 0 WAVE_NUM The number by which PWM1 will generate from the pulse data repeatedly. Note: If WAVE_NUM=0, the waveform generation will not stop until it is disabled. PWM+003Ch Bit Name Type Reset Bit Name Type Reset PWM1_DATA_ WIDTH PWM1 Data Width register 31 30 29 28 27 26 25 24 15 14 13 12 11 10 9 8 23 22 21 7 6 5 DATA_WIDTH[12:0] R/W 0 20 19 18 17 16 4 3 2 1 0 DATA_WIDTH The PWM1 pulse data width in the old PWM mode. 122/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 PWM+0040h Bit Name Type Reset Bit Name Type Reset 30 29 28 27 26 25 24 23 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 THRESH[12:0] R/W 0 4 3 2 1 0 22 The PWM1 pulse data high/low switching threshold in the old PWM mode. PWM+0044h 30 29 28 27 26 15 14 13 12 11 10 PWM+0048h PWM1_SEND_ WAVENUM PWM1 Send Wave Number register 31 SEND_WAVENUM mode. Bit Name Type Reset Bit PWM1_THRESH 31 THRESH Bit Name Type Reset Bit Name Type Reset PWM1 Thresh register 25 24 23 22 21 20 19 18 17 16 9 8 7 6 SEND_WAVENUM[15:0] RO 0 5 4 3 2 1 0 The number by which PWM1 has already generated from the specified data source in the periodical PWM1 Valid register PWM1_VALID 31 30 29 28 27 26 25 24 23 22 21 20 15 14 13 12 11 10 9 8 7 6 5 4 Name Type Reset 19 18 17 16 3 2 1 0 BUF1 BUF0 BUF1 BUF0 _VALI _VALI _VALI _VALI D_WE D_WE D D N N W R/W W R/W 0 0 0 0 BUF0_VALID The valid status is used to indicate pulse data in memory buffer0 is ready. BUF0_VALID_WEN This bit must be set to modify BUF0_VALID. BUF1_VALID The valid status is used to indicate pulse data in memory buffer1 is ready. BUF1_VALID_WEN This bit must be set to modify BUF1_VALID. Note: The program should set these bits after data are prepared in memory. The HW will clear these bits after it has used all data in the specified memory. PWM+0050h Bit 31 30 PWM2 Control register 29 28 27 26 25 PWM2_CON 24 123/599 23 22 21 20 19 18 17 16 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 Name Type Reset Bit 15 OLD_ Name PWM_ MODE Type R/W Reset 0 14 13 12 11 10 STOP_BITPOS[5:0] R/W 3Fh 9 8 7 6 5 GUAR IDLE_ SRCS D_VA VALU MODE EL E LUE R/W R/W R/W R/W 0 0 0 0 4 3 FIX_C CLKS LK_M EL ODE R/W R/W 0 0 2 1 0 CLKDIV [2:0] R/W 0 CLKDIV Select PWM2 clock scale. 000 CLK Hz 001 CLK/2 Hz 010 CLK/4 Hz 011 CLK/8 Hz 100 CLK/16 Hz 101 CLK/32 Hz 110 CLK/64 Hz 111 CLK/128 Hz CLKSEL Select PWM1 clock 0 CLK=CLKSRC 1 CLK=CLKSRC/1625 FIX_CLK_MODE Select PWM1 clock reference 0 CLKSRC= block clock 1 CLKSRC= 13 MHz SRCSEL Select PWM2 data source 0 FIFO mode 1 Memory mode MODE Select Random Generator mode 0 Periodical PWM mode. 1 Random PWM mode Note: When using random generator mode, the data source comes from dual buffers in memory. IDLE_VALUE PWM2 output value when idle state. GUARD_VALUE PWM2 output value when guard time. STOP_BITPOS The stop bit position for source data in periodical mode. In FIFO mode, it’s used to indicate the stop bit position in total 64 bits. In Memory mode, it’s for the stop bit position in the last 32 bits. OLD_PWM_MODE Use old PWM mode 0 New PWM mode 1 Old PWM mode Note: Using old PWM mode also means periodical mode. So SRCSEL and MODE is ignored in this situation. Only old PWM mode with 32 KHz clock source could work in the system sleep-mode. 124/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 PWM+0054h Bit Name Type Reset Bit Name Type Reset PWM2_HDURAT ION PWM2 High Duration register 31 30 29 28 27 26 25 15 14 13 12 11 10 9 24 23 22 21 20 19 18 17 16 8 7 6 HDURATION[15:0] R/W 1 5 4 3 2 1 0 HDURATION PWM2 pulse duration based on the current clock when PWM output is high. If duration =N, need to program N-1 in this register. Note: The duration of PWM must not be 0. PWM+0058h Bit Name Type Reset Bit Name Type Reset PWM2_LDURAT ION PWM2 Low Duration register 31 30 29 28 27 26 25 15 14 13 12 11 10 9 24 23 22 21 20 19 18 17 16 8 7 6 LDURATION[15:0] R/W 1 5 4 3 2 1 0 LDURATION PWM2 pulse duration based on the current clock when PWM output is low. If duration =N, need to program N-1 in this register. Note: The duration of PWM must not be 0. PWM+005Ch Bit Name Type Reset Bit Name Type Reset PWM2_GDRUA TION PWM2 Guard Duration register 31 30 29 28 27 26 15 14 13 12 11 10 25 24 23 22 9 8 7 6 GUARD_DURATION[15:0] R/W 0 21 20 19 18 17 16 5 4 3 2 1 0 GUDAR_DURATION It’s the guarding interval between individual waveforms and the output is decided by GUARD_VALUE. Also if it equals to N, it needs to program N-1 in this register. Note: If this duration is 0, it means no guarding interval. 125/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 PWM+0060h Bit Name Type Reset Bit Name Type Reset 31 30 29 28 27 26 15 14 13 12 11 10 BUF0_BS_ADDR PWM+0064h Bit Name Type Reset Bit Name Type Reset PWM2_BUF0_BAS E_ ADDR PWM2 Buffer0 Base Address register 25 24 23 22 BUF0_BS_ADDR[31:16] R/W 0 9 8 7 6 BUF0_BS_ADDR[15:0] R/W 0 21 20 19 18 17 16 5 4 3 2 1 0 The base address of memory buffer0 for PWM2’s waveform data. PWM2_BUF0_SI ZE PWM2 Buffer0 Size register 31 30 29 28 27 26 25 15 14 13 12 11 10 9 24 23 22 21 20 19 18 17 16 8 7 6 BUF0_SIZE[15:0] R/W 0 5 4 3 2 1 0 BUF0_SIZEThe length of the waveform data in memory buffer0 that PWM2 should generate. If it equals to N, need to program N-1 in this register. PWM+0068h Bit Name Type Reset Bit Name Type Reset PWM2_BUF1_ _BASE_ ADDR PWM2 Buffer1 Base Address register 31 30 29 28 27 26 15 14 13 12 11 10 25 24 23 22 BUF1_BS_ADDR[31:16] R/W 0 9 8 7 6 BUF1_BS_ADDR[15:0] R/W 0 21 20 19 18 17 16 5 4 3 2 1 0 BUF1_BS_ADDR The base address of memory buffer1 for PWM2’s waveform data. Note: The memory buffer1 is useless in periodical mode. PWM+006Ch Bit Name Type Reset Bit PWM2_BUF1_SI ZE PWM2 Buffer1 Size register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 126/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 Name Type Reset BUF1_SIZE[15:0] R/W 0 BUF1_SIZEThe length of the waveform data in memory buffer1 that PWM2 should generate. If it equals to N, need to program N-1 in this register. PWM+0070h Bit Name Type Reset Bit Name Type Reset PWM2_SEND_DAT A0 PWM2 Send Data0 register 31 30 29 28 27 26 15 14 13 12 11 10 25 24 23 22 SEND_DATA0 [31:16] R/W 0 9 8 7 6 SEND_DATA0[15:0] R/W 0 21 20 19 18 17 16 5 4 3 2 1 0 SEND_DATA0 PWM2 local buffer0 of pulse sequence data to be generated. Note: This value should be written only in periodically FIFO mode. In other mode, this buffer is for internal memory access. PWM+0074h Bit Name Type Reset Bit Name Type Reset PWM2_SEND_DAT A1 PWM2 Send Data1 register 31 30 29 28 27 26 15 14 13 12 11 10 25 24 23 22 SEND_DATA1[31:16] R/W 0 9 8 7 6 SEND_DATA1[15:0] R/W 0 21 20 19 18 17 16 5 4 3 2 1 0 SEND_DATA1 PWM2 local buffer0 of pulse sequence data to be generated. Note: This value should be written only in periodically FIFO mode. In other mode, this buffer is for internal memory access. PWM+0078h Bit Name Type Reset Bit Name Type Reset 31 30 29 28 27 26 25 15 14 13 12 11 10 9 WAVE_NUM PWM2_WAVE_ NUM PWM2 Wave Number register 24 23 22 21 20 19 18 17 16 8 7 6 WAVE_NUM[15:0] R/W 0 5 4 3 2 1 0 The number by which PWM2 will generate from the pulse data repeatedly. 127/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 Note: If WAVE_NUM=0, the waveform generation will not stop until it is disabled. PWM+007Ch Bit Name Type Reset Bit Name Type Reset PWM2_DATA_ WIDTH PWM2 Data Width register 31 30 29 28 27 26 25 24 15 14 13 12 11 10 9 8 23 22 21 7 6 5 DATA_WIDTH[12:0] R/W 0 20 19 18 17 16 4 3 2 1 0 DATA_WIDTH The PWM2 pulse data width in the old PWM mode. PWM+0080h Bit Name Type Reset Bit Name Type Reset 29 28 27 26 25 24 23 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 THRESH[12:0] R/W 0 4 3 2 1 0 22 The PWM2 pulse data high/low switching threshold in the old PWM mode. PWM+0084h 30 29 28 27 26 15 14 13 12 11 10 PWM+0088h PWM2_SEND_ WAVENUM PWM2 Send Wave Number register 31 SEND_WAVENUM mode. Bit Name Type Reset Bit PWM2_THRESH 30 THRESH Bit Name Type Reset Bit Name Type Reset PWM2 Thresh register 31 25 24 23 22 21 20 19 18 17 16 9 8 7 6 SEND_WAVENUM[15:0] RO 0 5 4 3 2 1 0 The number by which PWM2 has already generated from the specified data source in the periodical PWM2 Valid register PWM2_VALID 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 128/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 BUF0 BUF1 BUF0 BUF1 _VALI _VALI _VALI _VALI D_WE D_WE D D N N W R/W W R/W 0 0 0 0 Name Type Reset BUF0_VALID The valid status is used to indicate pulse data in memory buffer0 is ready. BUF0_VALID_WEN This bit must be set to modify BUF0_VALID. BUF1_VALID The valid status is used to indicate pulse data in memory buffer1 is ready. BUF1_VALID_WEN This bit must be set to modify BUF1_VALID. Note: The program should set these bits after data are prepared in memory. The HW will clear these bits after it has used all data in the specified memory. PWM+0090h Bit Name Type Reset Bit 31 15 OLD_ Name PWM_ MODE Type R/W Reset 0 PWM3 Control register 30 29 28 27 26 25 14 13 12 11 10 9 STOP_BITPOS[5:0] R/W 3Fh PWM3_CON 24 23 22 21 8 7 6 5 GUAR IDLE_ SRCS D_VA VALU MODE EL LUE E R/W R/W R/W R/W 0 0 0 0 20 19 4 3 FIX_C CLKS LK_M EL ODE R/W R/W 0 0 18 17 16 2 1 0 CLKDIV [2:0] R/W 0 CLKDIV Select PWM3 clock scale. 000 CLK Hz 001 CLK/2 Hz 010 CLK/4 Hz 011 CLK/8 Hz 100 CLK/16 Hz 101 CLK/32 Hz 110 CLK/64 Hz 111 CLK/128 Hz CLKSEL Select PWM1 clock 0 CLK=CLKSRC 1 CLK=CLKSRC/1625 FIX_CLK_MODE Select PWM1 clock reference 0 CLKSRC= block clock 1 CLKSRC= 13 MHz SRCSEL Select PWM3 data source 0 FIFO mode 1 Memory mode MODE Select Random Generator mode 0 Periodical PWM mode. 1 Random PWM mode 129/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 Note: When using random generator mode, the data source comes from dual buffers in memory. IDLE_VALUE PWM3 output value when idle state. GUARD_VALUE PWM3 output value when guard time. STOP_BITPOS The stop bit position for source data in periodical mode. In FIFO mode, it’s used to indicate the stop bit position in total 64 bits. In Memory mode, it’s for the stop bit position in the last 32 bits. OLD_PWM_MODE Use old PWM mode 0 New PWM mode 1 Old PWM mode Note: Using old PWM mode also means periodical mode. So SRCSEL and MODE is ignored in this situation. Only old PWM mode with 32 KHz clock source could work in the system sleep-mode. PWM+0094h Bit Name Type Reset Bit Name Type Reset PWM3_HDURAT ION PWM3 High Duration register 31 30 29 28 27 26 25 15 14 13 12 11 10 9 24 23 22 21 20 19 18 17 16 8 7 6 HDURATION[15:0] R/W 1 5 4 3 2 1 0 HDURATION PWM3 pulse duration based on the current clock when PWM output is high. If duration =N, need to program N-1 in this register. Note: The duration of PWM must not be 0. PWM+0098h Bit Name Type Reset Bit Name Type Reset PWM3_LDURAT ION PWM3 Low Duration register 31 30 29 28 27 26 25 15 14 13 12 11 10 9 24 23 22 21 20 19 18 17 16 8 7 6 LDURATION[15:0] R/W 1 5 4 3 2 1 0 LDURATION PWM3 pulse duration based on the current clock when PWM output is low. If duration =N, need to program N-1 in this register. Note: The duration of PWM must not be 0. PWM+009Ch Bit Name 31 30 PWM3_GDRUA TION PWM3 Guard Duration register 29 28 27 26 25 24 130/599 23 22 21 20 19 18 17 16 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 Type Reset Bit Name Type Reset 15 14 13 12 11 10 9 8 7 6 GUARD_DURATION[15:0] R/W 0 5 4 3 2 1 0 GUDAR_DURATION It’s the guarding interval between individual waveforms and the output is decided by GUARD_VALUE. Also if it equals to N, it needs to program N-1 in this register. Note: If this duration is 0, it means no guarding interval. PWM+00A0h Bit Name Type Reset Bit Name Type Reset 31 30 29 28 27 26 15 14 13 12 11 10 BUF0_BS_ADDR PWM+00A4h Bit Name Type Reset Bit Name Type Reset PWM3_BUF0_BAS E_ ADDR PWM3 Buffer0 Base Address register 25 24 23 22 BUF0_BS_ADDR[31:16] R/W 0 9 8 7 6 BUF0_BS_ADDR[15:0] R/W 0 21 20 19 18 17 16 5 4 3 2 1 0 The base address of memory buffer0 for PWM3’s waveform data. PWM3_BUF0_SI ZE PWM3 Buffer0 Size register 31 30 29 28 27 26 25 15 14 13 12 11 10 9 24 23 22 21 20 19 18 17 16 8 7 6 BUF0_SIZE[15:0] R/W 0 5 4 3 2 1 0 BUF0_SIZEThe length of the waveform data in memory buffer0 that PWM3 should generate. If it equals to N, need to program N-1 in this register. PWM+00A8h Bit Name Type Reset Bit Name Type Reset PWM3_BUF1_ _BASE_ ADDR PWM3 Buffer1 Base Address register 31 30 29 28 27 26 15 14 13 12 11 10 25 24 23 22 BUF1_BS_ADDR[31:16] R/W 0 9 8 7 6 BUF1_BS_ADDR[15:0] R/W 0 131/599 21 20 19 18 17 16 5 4 3 2 1 0 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 BUF1_BS_ADDR The base address of memory buffer1 for PWM3’s waveform data. Note: The memory buffer1 is useless in periodical mode. PWM+00ACh Bit Name Type Reset Bit Name Type Reset PWM3_BUF1_SI ZE PWM3 Buffer1 Size register 31 30 29 28 27 26 25 15 14 13 12 11 10 9 24 23 22 21 20 19 18 17 16 8 7 6 BUF1_SIZE[15:0] R/W 0 5 4 3 2 1 0 BUF1_SIZEThe length of the waveform data in memory buffer1 that PWM3 should generate. If it equals to N, need to program N-1 in this register. PWM+00B0h Bit Name Type Reset Bit Name Type Reset PWM3_SEND_DAT A0 PWM3 Send Data0 register 31 30 29 28 27 26 15 14 13 12 11 10 25 24 23 22 SEND_DATA0 [31:16] R/W 0 9 8 7 6 SEND_DATA0[15:0] R/W 0 21 20 19 18 17 16 5 4 3 2 1 0 SEND_DATA0 PWM3 local buffer0 of pulse sequence data to be generated. Note: This value should be written only in periodically FIFO mode. In other mode, this buffer is for internal memory access. PWM+00B4h Bit Name Type Reset Bit Name Type Reset PWM3_SEND_DAT A1 PWM3 Send Data1 register 31 30 29 28 27 26 15 14 13 12 11 10 25 24 23 22 SEND_DATA1[31:16] R/W 0 9 8 7 6 SEND_DATA1[15:0] R/W 0 21 20 19 18 17 16 5 4 3 2 1 0 SEND_DATA1 PWM3 local buffer0 of pulse sequence data to be generated. Note: This value should be written only in periodically FIFO mode. In other mode, this buffer is for internal memory access. 132/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 PWM+00B8h Bit Name Type Reset Bit Name Type Reset PWM3_WAVE_ NUM PWM3 Wave Number register 31 30 29 28 27 26 25 15 14 13 12 11 10 9 24 23 22 21 20 19 18 17 16 8 7 6 WAVE_NUM[15:0] R/W 0 5 4 3 2 1 0 WAVE_NUM The number by which PWM3 will generate from the pulse data repeatedly. Note: If WAVE_NUM=0, the waveform generation will not stop until it is disabled. PWM+00BCh Bit Name Type Reset Bit Name Type Reset PWM3_DATA_ WIDTH PWM3 Data Width register 31 30 29 28 27 26 25 24 15 14 13 12 11 10 9 8 23 22 21 7 6 5 DATA_WIDTH[12:0] R/W 0 20 19 18 17 16 4 3 2 1 0 DATA_WIDTH The PWM3 pulse data width in the old PWM mode. PWM+00C0h Bit Name Type Reset Bit Name Type Reset PWM3_THRESH 31 30 29 28 27 26 25 24 23 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 THRESH[12:0] R/W 0 4 3 2 1 0 THRESH 22 The PWM3 pulse data high/low switching threshold in the old PWM mode. PWM+00C4h Bit Name Type Reset Bit Name Type PWM3 Thresh register PWM3_SEND_ WAVENUM PWM3 Send Wave Number register 31 30 29 28 27 26 15 14 13 12 11 10 25 24 22 21 20 19 18 17 16 9 8 7 6 SEND_WAVENUM[15:0] RO 5 4 3 2 1 0 133/599 23 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 Reset 0 SEND_WAVENUM mode. PWM+00C8h Bit Name Type Reset Bit The number by which PWM3 has already generated from the specified data source in the periodical PWM3 Valid register PWM3_VALID 31 30 29 28 27 26 25 24 23 22 21 20 15 14 13 12 11 10 9 8 7 6 5 4 Name Type Reset 19 18 17 16 3 2 1 0 BUF0 BUF1 BUF0 BUF1 _VALI _VALI _VALI _VALI D_WE D_WE D D N N W R/W W R/W 0 0 0 0 BUF0_VALID The valid status is used to indicate pulse data in memory buffer0 is ready. BUF0_VALID_WEN This bit must be set to modify BUF0_VALID. BUF1_VALID The valid status is used to indicate pulse data in memory buffer1 is ready. BUF1_VALID_WEN This bit must be set to modify BUF1_VALID. Note: The program should set these bits after data are prepared in memory. The HW will clear these bits after it has used all data in the specified memory. PWM+00D0h Bit Name Type Reset Bit 31 15 OLD_ Name PWM_ MODE Type R/W Reset 0 PWM4 Control register 30 29 28 27 26 25 14 13 12 11 10 9 STOP_BITPOS[5:0] R/W 3Fh PWM4_CON 24 23 22 21 8 7 6 5 GUAR IDLE_ SRCS D_VA VALU MODE EL E LUE R/W R/W R/W R/W 0 0 0 0 20 19 4 3 FIX_C CLKS LK_M EL ODE R/W R/W 0 0 18 17 16 2 1 0 CLKDIV [2:0] R/W 0 CLKDIV Select PWM4 clock scale. 000 CLK Hz 001 CLK/2 Hz 010 CLK/4 Hz 011 CLK/8 Hz 100 CLK/16 Hz 101 CLK/32 Hz 110 CLK/64 Hz 111 CLK/128 Hz CLKSEL Select PWM1 clock 0 CLK=CLKSRC 1 CLK=CLKSRC/1625 134/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 FIX_CLK_MODE Select PWM1 clock reference 0 CLKSRC= block clock 1 CLKSRC= 13 MHz SRCSEL Select PWM4 data source 0 FIFO mode 1 Memory mode MODE Select Random Generator mode 0 Periodical PWM mode. 1 Random PWM mode Note: When using random generator mode, the data source comes from dual buffers in memory. IDLE_VALUE PWM4 output value when idle state. GUARD_VALUE PWM4 output value when guard time. STOP_BITPOS The stop bit position for source data in periodical mode. In FIFO mode, it’s used to indicate the stop bit position in total 64 bits. In Memory mode, it’s for the stop bit position in the last 32 bits. PWM+00D4h Bit Name Type Reset Bit Name Type Reset PWM4_HDURAT ION PWM4 High Duration register 31 30 29 28 27 26 25 15 14 13 12 11 10 9 24 23 22 21 20 19 18 17 16 8 7 6 HDURATION[15:0] R/W 1 5 4 3 2 1 0 HDURATION PWM4 pulse duration based on the current clock when PWM output is high. If duration =N, need to program N-1 in this register. Note: The duration of PWM must not be 0. PWM+00D8h Bit Name Type Reset Bit Name Type Reset PWM4_LDURAT ION PWM4 Low Duration register 31 30 29 28 27 26 25 15 14 13 12 11 10 9 24 23 22 21 20 19 18 17 16 8 7 6 LDURATION[15:0] R/W 1 5 4 3 2 1 0 LDURATION PWM4 pulse duration based on the current clock when PWM output is low. If duration =N, need to program N-1 in this register. Note: The duration of PWM must not be 0. 135/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 PWM+00DCh Bit Name Type Reset Bit Name Type Reset PWM4_GDRUA TION PWM4 Guard Duration register 31 30 29 28 27 26 15 14 13 12 11 10 25 24 23 22 9 8 7 6 GUARD_DURATION[15:0] R/W 0 21 20 19 18 17 16 5 4 3 2 1 0 GUDAR_DURATION It’s the guarding interval between individual waveforms and the output is decided by GUARD_VALUE. Also if it equals to N, it needs to program N-1 in this register. Note: If this duration is 0, it means no guarding interval. PWM+00E0h Bit Name Type Reset Bit Name Type Reset 31 30 29 28 27 26 15 14 13 12 11 10 BUF0_BS_ADDR PWM+00E4h Bit Name Type Reset Bit Name Type Reset PWM4_BUF0_BAS E_ ADDR PWM4 Buffer0 Base Address register 25 24 23 22 BUF0_BS_ADDR[31:16] R/W 0 9 8 7 6 BUF0_BS_ADDR[15:0] R/W 0 21 20 19 18 17 16 5 4 3 2 1 0 The base address of memory buffer0 for PWM4’s waveform data. PWM4_BUF0_SI ZE PWM4 Buffer0 Size register 31 30 29 28 27 26 25 15 14 13 12 11 10 9 24 23 22 21 20 19 18 17 16 8 7 6 BUF0_SIZE[15:0] R/W 0 5 4 3 2 1 0 BUF0_SIZEThe length of the waveform data in memory buffer0 that PWM4 should generate. If it equals to N, need to program N-1 in this register. PWM+00E8h Bit Name Type 31 30 PWM4_BUF1_ _BASE_ ADDR PWM4 Buffer1 Base Address register 29 28 27 26 25 24 23 22 BUF1_BS_ADDR[31:16] R/W 136/599 21 20 19 18 17 16 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 Reset Bit Name Type Reset 15 14 13 12 11 10 0 9 8 7 6 BUF1_BS_ADDR[15:0] R/W 0 5 4 3 2 1 0 BUF1_BS_ADDR The base address of memory buffer1 for PWM4’s waveform data. Note: The memory buffer1 is useless in periodical mode. PWM+00ECh Bit Name Type Reset Bit Name Type Reset PWM4_BUF1_SI ZE PWM4 Buffer1 Size register 31 30 29 28 27 26 25 15 14 13 12 11 10 9 24 23 22 21 20 19 18 17 16 8 7 6 BUF1_SIZE[15:0] R/W 0 5 4 3 2 1 0 BUF1_SIZEThe length of the waveform data in memory buffer1 that PWM4 should generate. If it equals to N, need to program N-1 in this register. PWM+00F0h Bit Name Type Reset Bit Name Type Reset PWM4_SEND_DAT A0 PWM4 Send Data0 register 31 30 29 28 27 26 15 14 13 12 11 10 25 24 23 22 SEND_DATA0 [31:16] R/W 0 9 8 7 6 SEND_DATA0[15:0] R/W 0 21 20 19 18 17 16 5 4 3 2 1 0 SEND_DATA0 PWM4 local buffer0 of pulse sequence data to be generated. Note: This value should be written only in periodically FIFO mode. In other mode, this buffer is for internal memory access. PWM+00F4h Bit Name Type Reset Bit Name Type Reset PWM4_SEND_DAT A1 PWM4 Send Data1 register 31 30 29 28 27 26 15 14 13 12 11 10 25 24 23 22 SEND_DATA1[31:16] R/W 0 9 8 7 6 SEND_DATA1[15:0] R/W 0 137/599 21 20 19 18 17 16 5 4 3 2 1 0 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 SEND_DATA1 PWM4 local buffer0 of pulse sequence data to be generated. Note: This value should be written only in periodically FIFO mode. In other mode, this buffer is for internal memory access. PWM+00F8h Bit Name Type Reset Bit Name Type Reset PWM4_WAVE_ NUM PWM4 Wave Number register 31 30 29 28 27 26 25 15 14 13 12 11 10 9 24 23 22 21 20 19 18 17 16 8 7 6 WAVE_NUM[15:0] R/W 0 5 4 3 2 1 0 WAVE_NUM The number by which PWM4 will generate from the pulse data repeatedly. Note: If WAVE_NUM=0, the waveform generation will not stop until it is disabled. PWM+00FCh Bit Name Type Reset Bit Name Type Reset 31 30 29 28 27 26 15 14 13 12 11 10 SEND_WAVENUM mode. PWM+0100h Bit Name Type Reset Bit PWM4_SEND_ WAVENUM PWM4 Send Wave Number register 25 24 23 22 21 20 19 18 17 16 9 8 7 6 SEND_WAVENUM[15:0] RO 0 5 4 3 2 1 0 The number by which PWM4 has already generated from the specified data source in the periodical PWM4 Valid register PWM4_VALID 31 30 29 28 27 26 25 24 23 22 21 20 15 14 13 12 11 10 9 8 7 6 5 4 Name Type Reset 19 18 17 16 3 2 1 0 BUF0 BUF1 BUF0 BUF1 _VALI _VALI _VALI _VALI D_WE D_WE D D N N W R/W W R/W 0 0 0 0 BUF0_VALID The valid status is used to indicate pulse data in memory buffer0 is ready. BUF0_VALID_WEN This bit must be set to modify BUF0_VALID. BUF1_VALID The valid status is used to indicate pulse data in memory buffer1 is ready. BUF1_VALID_WEN This bit must be set to modify BUF1_VALID. 138/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 Note: The program should set these bits after data are prepared in memory. The HW will clear these bits after it has used all data in the specified memory. PWM+0110h Bit Name Type Reset Bit 31 15 OLD_ Name PWM_ MODE Type R/W Reset 0 PWM5 Control register 30 29 28 27 26 25 14 13 12 11 10 9 STOP_BITPOS[5:0] R/W 3Fh PWM5_CON 24 23 22 21 8 7 6 5 GUAR IDLE_ SRCS D_VA VALU MODE EL LUE E R/W R/W R/W R/W 0 0 0 0 20 19 4 3 FIX_C CLKS LK_M EL ODE R/W R/W 0 0 18 17 16 2 1 0 CLKDIV [2:0] R/W 0 CLKDIV Select PWM5 clock scale. 000 CLK Hz 001 CLK/2 Hz 010 CLK/4 Hz 011 CLK/8 Hz 100 CLK/16 Hz 101 CLK/32 Hz 110 CLK/64 Hz 111 CLK/128 Hz CLKSEL Select PWM1 clock 0 CLK=CLKSRC 1 CLK=CLKSRC/1625 FIX_CLK_MODE Select PWM1 clock reference 0 CLKSRC= block clock 1 CLKSRC= 13 MHz SRCSEL Select PWM5 data source 0 FIFO mode 2 Memory mode MODE Select Random Generator mode 2 Periodical PWM mode. 3 Random PWM mode Note: When using random generator mode, the data source comes from dual buffers in memory. IDLE_VALUE PWM5 output value when idle state. GUARD_VALUE PWM5 output value when guard time. STOP_BITPOS The stop bit position for source data in periodical mode. In FIFO mode, it’s used to indicate the stop bit position in total 64 bits. In Memory mode, it’s for the stop bit position in the last 32 bits. 139/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 PWM+0114h Bit Name Type Reset Bit Name Type Reset PWM5_HDURAT ION PWM5 High Duration register 31 30 29 28 27 26 25 15 14 13 12 11 10 9 24 23 22 21 20 19 18 17 16 8 7 6 HDURATION[15:0] R/W 1 5 4 3 2 1 0 HDURATION PWM5 pulse duration based on the current clock when PWM output is high. If duration =N, need to program N-1 in this register. Note: The duration of PWM must not be 0. PWM+0118h Bit Name Type Reset Bit Name Type Reset PWM5_LDURAT ION PWM5 Low Duration register 31 30 29 28 27 26 25 15 14 13 12 11 10 9 24 23 22 21 20 19 18 17 16 8 7 6 LDURATION[15:0] R/W 1 5 4 3 2 1 0 LDURATION PWM5 pulse duration based on the current clock when PWM output is low. If duration =N, need to program N-1 in this register. Note: The duration of PWM must not be 0. PWM+011Ch Bit Name Type Reset Bit Name Type Reset PWM5_GDRUA TION PWM5 Guard Duration register 31 30 29 28 27 26 15 14 13 12 11 10 25 24 23 22 9 8 7 6 GUARD_DURATION[15:0] R/W 0 21 20 19 18 17 16 5 4 3 2 1 0 GUDAR_DURATION It’s the guarding interval between individual waveforms and the output is decided by GUARD_VALUE. Also if it equals to N, it needs to program N-1 in this register. Note: If this duration is 0, it means no guarding interval. 140/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 PWM+0120h Bit Name Type Reset Bit Name Type Reset 31 30 29 28 27 26 15 14 13 12 11 10 BUF0_BS_ADDR PWM+0124h Bit Name Type Reset Bit Name Type Reset PWM5_BUF0_BAS E_ ADDR PWM5 Buffer0 Base Address register 25 24 23 22 BUF0_BS_ADDR[31:16] R/W 0 9 8 7 6 BUF0_BS_ADDR[15:0] R/W 0 21 20 19 18 17 16 5 4 3 2 1 0 The base address of memory buffer0 for PWM5’s waveform data. PWM5_BUF0_SI ZE PWM5 Buffer0 Size register 31 30 29 28 27 26 25 15 14 13 12 11 10 9 24 23 22 21 20 19 18 17 16 8 7 6 BUF0_SIZE[15:0] R/W 0 5 4 3 2 1 0 BUF0_SIZEThe length of the waveform data in memory buffer0 that PWM5 should generate. If it equals to N, need to program N-1 in this register. PWM+0128h Bit Name Type Reset Bit Name Type Reset PWM5_BUF1_ _BASE_ ADDR PWM5 Buffer1 Base Address register 31 30 29 28 27 26 15 14 13 12 11 10 25 24 23 22 BUF1_BS_ADDR[31:16] R/W 0 9 8 7 6 BUF1_BS_ADDR[15:0] R/W 0 21 20 19 18 17 16 5 4 3 2 1 0 BUF1_BS_ADDR The base address of memory buffer1 for PWM5’s waveform data. Note: The memory buffer1 is useless in periodical mode. PWM+012Ch Bit Name Type Reset Bit PWM5_BUF1_SI ZE PWM5 Buffer1 Size register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 141/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 Name Type Reset BUF1_SIZE[15:0] R/W 0 BUF1_SIZEThe length of the waveform data in memory buffer1 that PWM5 should generate. If it equals to N, need to program N-1 in this register. PWM+0130h Bit Name Type Reset Bit Name Type Reset PWM5_SEND_DAT A0 PWM5 Send Data0 register 31 30 29 28 27 26 15 14 13 12 11 10 25 24 23 22 SEND_DATA0 [31:16] R/W 0 9 8 7 6 SEND_DATA0[15:0] R/W 0 21 20 19 18 17 16 5 4 3 2 1 0 SEND_DATA0 PWM5 local buffer0 of pulse sequence data to be generated. Note: This value should be written only in periodically FIFO mode. In other mode, this buffer is for internal memory access. PWM+0134h Bit Name Type Reset Bit Name Type Reset PWM5_SEND_DAT A1 PWM5 Send Data1 register 31 30 29 28 27 26 15 14 13 12 11 10 25 24 23 22 SEND_DATA1[31:16] R/W 0 9 8 7 6 SEND_DATA1[15:0] R/W 0 21 20 19 18 17 16 5 4 3 2 1 0 SEND_DATA1 PWM5 local buffer0 of pulse sequence data to be generated. Note: This value should be written only in periodically FIFO mode. In other mode, this buffer is for internal memory access. PWM+0138h Bit Name Type Reset Bit Name Type Reset 31 30 29 28 27 26 25 15 14 13 12 11 10 9 WAVE_NUM PWM5_WAVE_ NUM PWM5 Wave Number register 24 23 22 21 20 19 18 17 16 8 7 6 WAVE_NUM[15:0] R/W 0 5 4 3 2 1 0 The number by which PWM5 will generate from the pulse data repeatedly. 142/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 Note: If WAVE_NUM=0, the waveform generation will not stop until it is disabled. PWM+013Ch Bit Name Type Reset Bit Name Type Reset 31 30 29 28 27 26 15 14 13 12 11 10 SEND_WAVENUM mode. PWM+0140h Bit Name Type Reset Bit PWM5_SEND_ WAVENUM PWM5 Send Wave Number register 25 24 23 22 21 20 19 18 17 16 9 8 7 6 SEND_WAVENUM[15:0] RO 0 5 4 3 2 1 0 The number by which PWM5 has already generated from the specified data source in the periodical PWM5 Valid register PWM5_VALID 31 30 29 28 27 26 25 24 23 22 21 20 15 14 13 12 11 10 9 8 7 6 5 4 Name Type Reset 19 18 17 16 3 2 1 0 BUF0 BUF1 BUF0 BUF1 _VALI _VALI _VALI _VALI D_WE D_WE D D N N W R/W W R/W 0 0 0 0 BUF0_VALID The valid status is used to indicate pulse data in memory buffer0 is ready. BUF0_VALID_WEN This bit must be set to modify BUF0_VALID. BUF1_VALID The valid status is used to indicate pulse data in memory buffer1 is ready. BUF1_VALID_WEN This bit must be set to modify BUF1_VALID. Note: The program should set these bits after data are prepared in memory. The HW will clear these bits after it has used all data in the specified memory. PWM+0150h Bit Name Type Reset Bit 31 15 OLD_ Name PWM_ MODE Type R/W Reset 0 CLKDIV PWM6 Control register 30 29 28 27 26 25 14 13 12 11 10 9 STOP_BITPOS[5:0] R/W 3Fh PWM6_CON 24 23 22 21 8 7 6 5 GUAR IDLE_ SRCS D_VA VALU MODE EL E LUE R/W R/W R/W R/W 0 0 0 0 20 19 4 3 FIX_C CLKS LK_M EL ODE R/W R/W 0 0 18 17 16 2 1 0 CLKDIV [2:0] R/W 0 Select PWM6 clock scale. 143/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 000 CLK Hz 001 CLK/2 Hz 010 CLK/4 Hz 011 CLK/8 Hz 100 CLK/16 Hz 101 CLK/32 Hz 110 CLK/64 Hz 111 CLK/128 Hz CLKSEL Select PWM1 clock 0 CLK=CLKSRC 1 CLK=CLKSRC/1625 FIX_CLK_MODE Select PWM1 clock reference 0 CLKSRC= block clock 1 CLKSRC= 13 MHz SRCSEL Select PWM6 data source 0 FIFO mode 3 Memory mode MODE Select Random Generator mode 4 Periodical PWM mode. 5 Random PWM mode Note: When using random generator mode, the data source comes from dual buffers in memory. IDLE_VALUE PWM6 output value when idle state. GUARD_VALUE PWM6 output value when guard time. STOP_BITPOS The stop bit position for source data in periodical mode. In FIFO mode, it’s used to indicate the stop bit position in total 64 bits. In Memory mode, it’s for the stop bit position in the last 32 bits. PWM+0154h Bit Name Type Reset Bit Name Type Reset PWM6_HDURAT ION PWM6 High Duration register 31 30 29 28 27 26 25 15 14 13 12 11 10 9 24 23 22 21 20 19 18 17 16 8 7 6 HDURATION[15:0] R/W 1 5 4 3 2 1 0 HDURATION PWM6 pulse duration based on the current clock when PWM output is high. If duration =N, need to program N-1 in this register. Note: The duration of PWM must not be 0. 144/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 PWM+0158h Bit Name Type Reset Bit Name Type Reset PWM6_LDURAT ION PWM6 Low Duration register 31 30 29 28 27 26 25 15 14 13 12 11 10 9 24 23 22 21 20 19 18 17 16 8 7 6 LDURATION[15:0] R/W 1 5 4 3 2 1 0 LDURATION PWM6 pulse duration based on the current clock when PWM output is low. If duration =N, need to program N-1 in this register. Note: The duration of PWM must not be 0. PWM+015Ch Bit Name Type Reset Bit Name Type Reset PWM6_GDRUA TION PWM6 Guard Duration register 31 30 29 28 27 26 15 14 13 12 11 10 25 24 23 22 9 8 7 6 GUARD_DURATION[15:0] R/W 0 21 20 19 18 17 16 5 4 3 2 1 0 GUDAR_DURATION It’s the guarding interval between individual waveforms and the output is decided by GUARD_VALUE. Also if it equals to N, it needs to program N-1 in this register. Note: If this duration is 0, it means no guarding interval. PWM+0160h Bit Name Type Reset Bit Name Type Reset 31 30 29 28 27 26 15 14 13 12 11 10 BUF0_BS_ADDR PWM+0164h Bit Name 31 30 PWM6_BUF0_BAS E_ ADDR PWM6 Buffer0 Base Address register 25 24 23 22 BUF0_BS_ADDR[31:16] R/W 0 9 8 7 6 BUF0_BS_ADDR[15:0] R/W 0 21 20 19 18 17 16 5 4 3 2 1 0 The base address of memory buffer0 for PWM6’s waveform data. PWM6_BUF0_SI ZE PWM6 Buffer0 Size register 29 28 27 26 25 24 145/599 23 22 21 20 19 18 17 16 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 Type Reset Bit Name Type Reset 15 14 13 12 11 10 9 8 7 6 BUF0_SIZE[15:0] R/W 0 5 4 3 2 1 0 BUF0_SIZEThe length of the waveform data in memory buffer0 that PWM6 should generate. If it equals to N, need to program N-1 in this register. PWM+0168h Bit Name Type Reset Bit Name Type Reset PWM6_BUF1_ _BASE_ ADDR PWM6 Buffer1 Base Address register 31 30 29 28 27 26 15 14 13 12 11 10 25 24 23 22 BUF1_BS_ADDR[31:16] R/W 0 9 8 7 6 BUF1_BS_ADDR[15:0] R/W 0 21 20 19 18 17 16 5 4 3 2 1 0 BUF1_BS_ADDR The base address of memory buffer1 for PWM6’s waveform data. Note: The memory buffer1 is useless in periodical mode. PWM+016Ch Bit Name Type Reset Bit Name Type Reset PWM6_BUF1_SI ZE PWM6 Buffer1 Size register 31 30 29 28 27 26 25 15 14 13 12 11 10 9 24 23 22 21 20 19 18 17 16 8 7 6 BUF1_SIZE[15:0] R/W 0 5 4 3 2 1 0 BUF1_SIZEThe length of the waveform data in memory buffer1 that PWM6 should generate. If it equals to N, need to program N-1 in this register. PWM+0170h Bit Name Type Reset Bit Name Type Reset PWM6_SEND_DAT A0 PWM6 Send Data0 register 31 30 29 28 27 26 15 14 13 12 11 10 25 24 23 22 SEND_DATA0 [31:16] R/W 0 9 8 7 6 SEND_DATA0[15:0] R/W 0 146/599 21 20 19 18 17 16 5 4 3 2 1 0 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 SEND_DATA0 PWM6 local buffer0 of pulse sequence data to be generated. Note: This value should be written only in periodically FIFO mode. In other mode, this buffer is for internal memory access. PWM+0174h Bit Name Type Reset Bit Name Type Reset PWM6_SEND_DAT A1 PWM6 Send Data1 register 31 30 29 28 27 26 15 14 13 12 11 10 25 24 23 22 SEND_DATA1[31:16] R/W 0 9 8 7 6 SEND_DATA1[15:0] R/W 0 21 20 19 18 17 16 5 4 3 2 1 0 SEND_DATA1 PWM6 local buffer0 of pulse sequence data to be generated. Note: This value should be written only in periodically FIFO mode. In other mode, this buffer is for internal memory access. PWM+0178h Bit Name Type Reset Bit Name Type Reset PWM6_WAVE_ NUM PWM6 Wave Number register 31 30 29 28 27 26 25 15 14 13 12 11 10 9 24 23 22 21 20 19 18 17 16 8 7 6 WAVE_NUM[15:0] R/W 0 5 4 3 2 1 0 WAVE_NUM The number by which PWM6 will generate from the pulse data repeatedly. Note: If WAVE_NUM=0, the waveform generation will not stop until it is disabled. PWM+017Ch Bit Name Type Reset Bit Name Type Reset 31 30 29 28 27 26 15 14 13 12 11 10 SEND_WAVENUM mode. PWM6_SEND_ WAVENUM PWM6 Send Wave Number register 25 24 23 22 21 20 19 18 17 16 9 8 7 6 SEND_WAVENUM[15:0] RO 0 5 4 3 2 1 0 The number by which PWM6 has already generated from the specified data source in the periodical 147/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 PWM+0180h Bit Name Type Reset Bit PWM6 Valid register PWM6_VALID 31 30 29 28 27 26 25 24 23 22 21 20 15 14 13 12 11 10 9 8 7 6 5 4 Name Type Reset 19 18 17 16 3 2 1 0 BUF0 BUF1 BUF0 BUF1 _VALI _VALI _VALI _VALI D_WE D_WE D D N N W R/W W R/W 0 0 0 0 BUF0_VALID The valid status is used to indicate pulse data in memory buffer0 is ready. BUF0_VALID_WEN This bit must be set to modify BUF0_VALID. BUF1_VALID The valid status is used to indicate pulse data in memory buffer1 is ready. BUF1_VALID_WEN This bit must be set to modify BUF1_VALID. Note: The program should set these bits after data are prepared in memory. The HW will clear these bits after it has used all data in the specified memory. PWM+0190h Bit Name Type Reset Bit Name Type Reset PWM_INT_ENA BLE PWM Interrupt Enable register 31 30 29 28 15 14 13 12 27 26 25 24 23 22 21 20 19 18 17 16 11 10 9 8 7 6 5 4 3 2 1 0 PWM4 PWM5 PWM1 PWM3 PWM2 PWM6 PWM4 PWM5 PWM1 PWM6 PWM2 PWM3 _INT_ _INT_ _INT_ _INT_ _INT_ _INT_ _INT_ _INT_ _INT_ _INT_ _INT_ _INT_ UNDE UNDE UNDE UNDE UNDE UNDE FINIS FINIS FINIS FINIS FINIS FINIS RFLO RFLO RFLO RFLO RFLO RFLO H_EN H_EN H_EN H_EN H_EN H_EN W_EN W_EN W_EN W_EN W_EN W_EN R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 0 0 0 0 PWM1_INT_FINISH_EN Set to 1 to enable PWM1 finish interrupt PWM1_INT_UNDERFLOW_EN Set to 1 to enable PWM1 underflow interrupt PWM2_INT_FINISH_EN Set to 1 to enable PWM2 finish interrupt PWM2_INT_UNDERFLOW_EN Set to 1 to enable PWM2 underflow interrupt PWM3_INT_FINISH_EN Set to 1 to enable PWM3 finish interrupt PWM3_INT_UNDERFLOW_EN Set to 1 to enable PWM3 underflow interrupt PWM4_INT_FINISH_EN Set to 1 to enable PWM4 finish interrupt PWM4_INT_UNDERFLOW_EN Set to 1 to enable PWM4 underflow interrupt PWM5_INT_FINISH_EN Set to 1 to enable PWM5 finish interrupt PWM5_INT_UNDERFLOW_EN Set to 1 to enable PWM5 underflow interrupt PWM6_INT_FINISH_EN Set to 1 to enable PWM6 finish interrupt PWM6_INT_UNDERFLOW_EN Set to 1 to enable PWM6 underflow interrupt 148/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 PWM+0194h Bit Name Type Reset Bit PWM_INT_STAT US PWM Interrupt Status register 31 30 29 28 15 14 13 12 Name Type Reset 27 26 25 24 23 22 21 20 19 18 17 16 11 10 9 8 7 6 5 4 3 2 1 0 PWM4 PWM5 PWM1 PWM3 PWM2 PWM6 PWM4 PWM5 PWM1 PWM6 PWM2 PWM3 _INT_ _INT_ _INT_ _INT_ _INT_ _INT_ _INT_ _INT_ _INT_ _INT_ _INT_ _INT_ UNDE UNDE UNDE UNDE UNDE UNDE FINIS FINIS FINIS FINIS FINIS FINIS RFLO RFLO RFLO RFLO RFLO RFLO H_ST H_ST H_ST H_ST H_ST H_ST W_ST W_ST W_ST W_ST W_ST W_ST R R R R R R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 PWM1_INT_FINISH_ST PWM1 finish status PWM1_INT_UNDERFLOW_ST PWM1 underflow status PWM2_INT_FINISH_ST PWM2 finish status PWM2_INT_UNDERFLOW_ST PWM2 underflow status PWM3_INT_FINISH_ST PWM3 finish status PWM3_INT_UNDERFLOW_ST PWM3 underflow status PWM4_INT_FINISH_ST PWM4 finish status PWM4_INT_UNDERFLOW_ST PWM4 underflow status PWM5_INT_FINISH_ST PWM5 finish status PWM5_INT_UNDERFLOW_ST PWM5 underflow status PWM6_INT_FINISH_ST PWM6 finish status PWM6_INT_UNDERFLOW_ST PWM6 underflow status Note: The interrupt status will be auto-cleared if interrupt enable or PWM enable is cleared. PWM+0198h Bit Name Type Reset Bit Name Type Reset PWM Interrupt Acknowledge register 31 30 29 28 15 14 13 12 27 26 25 24 23 PWM_INT_ACK 22 21 20 19 18 17 16 11 10 9 8 7 6 5 4 3 2 1 0 PWM4 PWM5 PWM1 PWM6 PWM3 PWM2 PWM4 PWM5 PWM1 PWM6 PWM3 PWM2 _INT_ _INT_ _INT_ _INT_ _INT_ _INT_ _INT_ _INT_ _INT_ _INT_ _INT_ _INT_ UNDE UNDE UNDE UNDE UNDE UNDE FINIS FINIS FINIS FINIS FINIS FINIS RFLO RFLO RFLO RFLO RFLO RFLO H_AC H_AC H_AC H_AC H_AC H_AC W_AC W_AC W_AC W_AC W_AC W_AC K K K K K K K K K K K K W W W W W W W W W W W W 0 0 0 0 0 0 0 0 0 0 0 0 PWM1_INT_FINISH_ACK Set to 1 to clear PWM1 finish interrupt PWM1_INT_UNDERFLOW_ACK Set to 1 to clear PWM1 underflow interrupt PWM2_INT_FINISH_ACK Set to 1 to clear PWM2 finish interrupt PWM2_INT_UNDERFLOW_ACK Set to 1 to clear PWM2 underflow interrupt PWM3_INT_FINISH_ACK Set to 1 to clear PWM3 finish interrupt 149/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 PWM3_INT_UNDERFLOW_ACK Set to 1 to clear PWM3 underflow interrupt PWM4_INT_FINISH_ACK Set to 1 to clear PWM4 finish interrupt PWM4_INT_UNDERFLOW_ACK Set to 1 to clear PWM4 underflow interrupt PWM5_INT_FINISH_ACK Set to 1 to clear PWM5 finish interrupt PWM5_INT_UNDERFLOW_ACK Set to 1 to clear PWM5 underflow interrupt PWM6_INT_FINISH_ACK Set to 1 to clear PWM6 finish interrupt PWM6_INT_UNDERFLOW_ACK Set to 1 to clear PWM6 underflow interrupt 4.4 SIM Interface The MT6235 contains a dedicated smart card interface to allow the MCU to access. It can operate via 5 terminals, using SIMVCC, SIMSEL, SIMRST, SIMCLK and SIMDATA. Figure 18 SIM Interface Block Diagram The SIMVCC is used to control the external voltage supply to the SIM card and SIMSEL determines the regulated smart card supply voltage. SIMRST is used as the SIM card reset signal. Besides, SIMDATA and SIMCLK are used for data exchange purpose. Basically, the SIM interface acts as a half duplex asynchronous communication port and its data format is composed of ten consecutive bits: a start bit in state Low, eight information bits, and a tenth bit used for parity checking. The data format can be divided into two modes as follows: Direct Mode (ODD=SDIR=SINV=0) SB D0 D1 D2 D3 D4 D5 D6 D7 PB SB: Start Bit (in state Low) Dx: Data Byte (LSB is first and logic level ONE is High) PB: Even Parity Check Bit Indirect Mode (ODD=SDIR=SINV=1) SB N7 N6 N5 N4 N3 N2 N1 N0 PB SB: Start Bit (in state Low) 150/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 Nx: Data Byte (MSB is first and logic level ONE is Low) PB: Odd Parity Check Bit If the receiver gets a wrong parity bit, it will respond by pulling the SIMDATA Low to inform the transmitter and the transmitter will retransmit the character. When the receiver is a SIM Card, the error response starts 0.5 bits after the PB and it may last for 1~2 bit periods. When the receiver is the SIM interface, the error response starts 0.5 bits after the PB and lasts for 1.5 bit period. When the SIM interface is the transmitter, it will take totally 14 bits guard period whether the error response appears. If the receiver shows the error response, the SIM interface will retransmit the previous character again else it will transmit the next character. Figure 19 SIM Interface Timing Diagram 4.4.1 Register Definitions SIM+0000h Bit 15 SIM module control register 14 13 12 11 10 9 8 Name Type Reset SIM_CONT 7 6 5 4 3 2 1 0 CSTO SIMO WRST P N W R/W R/W 0 0 0 SIMON SIM card power-up/power-down control 0 Initiate the card deactivation sequence 1 Initiate the card activation sequence CSTOP Enable clock stop mode. Together with CPOL in SIM_CNF register, it determines the polarity of the SIMCLK in this mode. 151/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 0 Enable the SIMCLK output. 1 Disable the SIMCLK output WRST SIM card warm reset control SIM+0004h Bit Name Type Reset 15 SIM module configuration register 14 13 12 11 10 9 8 SIM_CONF 7 6 5 4 3 2 1 0 SIMS TXAC RXAC HFEN T0EN T1EN TOUT ODD SDIR SINV CPOL EL K K R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 0 0 0 RXACK SIM card reception error handshake control 0 Disable character receipt handshaking 1 Enable character receipt handshaking TXACK SIM card transmission error handshake control 0 Disable character transmission handshaking 1 Enable character transmission handshaking CPOL SIMCLK polarity control in clock stop mode 0 Make SIMCLK stop in LOW level 1 Make SIMCLK stop in HIGH level SINV Data Inverter. 0 Not invert the transmitted and received data 1 Invert the transmitted and received data SDIR Data Transfer Direction 0 LSB is transmitted and received first 1 MSB is transmitted and received first ODD Select odd or even parity 0 Even parity 1 Odd parity SIMSEL SIM card supply voltage select 0 SIMSEL pin is set to LOW level 1 SIMSEL pin is set to HIGH level TOUT SIM work waiting time counter control 0 Disable Time-Out counter 1 Enable Time-Out counter T1EN T=1 protocol controller control 0 Disable T=1 protocol controller 1 Enable T=1 protocol controller T0EN T=0 protocol controller control 0 Disable T=0 protocol controller 1 Enable T=0 protocol controller HFEN Hardware flow control 0 Disable hardware flow control 1 Enable hardware flow control 152/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 SIM +0008h Bit Name Type Reset 15 SIM Baud Rate Register 14 13 12 11 10 SIM_BRR 9 8 7 6 5 ETU[8:0] R/W 372d 4 3 2 1 0 SIMCLK[1:0] R/W 01 SIMCLK Set SIMCLK frequency 00 13/2 MHz 01 13/4 MHz 10 13/8 MHz 11 13/32 MHz ETU Determines the duration of elementary time unit in unit of SIMCLK SIM +0010h Bit 15 SIM interrupt enable register 14 13 12 11 Name Type Reset SIM_IRQEN 10 9 8 7 6 5 4 3 2 1 0 EDCE T1EN RXER T0EN SIMO ATRER TXER TOU OVRU RXTID TXTID RR D R D FF R R T N E E R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 0 0 0 For all these bits 0 Interrupt is disabled 1 Interrupt is enabled SIM +0014h Bit 15 SIM module status register 14 13 12 11 Name Type Reset SIM_STS 10 9 8 7 6 5 4 3 2 1 0 EDCE T1EN RXER T0EN SIMO ATRER TXER TOU OVRU RXTID TXTID RR D R D FF R R T N E E R/C R/C R/C R/C R/C R/C R/C R/C R/C R R — — — — — — — — — — — TXTIDE Transmit FIFO tide mark reached interrupt occurred RXTIDE Receive FIFO tide mark reached interrupt occurred OVRUN Transmit/Receive FIFO overrun interrupt occurred TOUT Between character timeout interrupt occurred TXERR Character transmission error interrupt occurred ATRERR ATR start time-out interrupt occurred SIMOFF Card deactivation complete interrupt occurred T0END Data Transfer handled by T=0 Controller completed interrupt occurred RXERR Character reception error interrupt occurred T1END Data Transfer handled by T=1 Controller completed interrupt occurred EDCERR T=1 Controller CRC error occurred SIM +0020h Bit Name Type Reset 15 SIM retry limit register 14 13 12 11 10 SIM_RETRY 9 8 TXRETRY R/W 3h 153/599 7 6 5 4 3 2 1 0 RXRETRY R/W 3h MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 RXRETRY Specify the max. numbers of receive retries that are allowed when parity error has occurred. TXRETRY Specify the max. numbers of transmit retries that are allowed when parity error has occurred. SIM+0024h Bit Name Type Reset 15 SIM FIFO tide mark register 14 13 12 11 10 9 TXTIDE[3:0] R/W 0h SIM_TIDE 8 7 6 5 4 3 2 1 RXTIDE[3:0] R/W 0h 0 RXTIDE Trigger point for RXTIDE interrupt TXTIDE Trigger point for TXTIDE interrupt SIM +0030h Bit Name Type Reset 15 Data register used as Tx/Rx Data Register 14 13 12 11 10 9 8 7 6 SIM_DATA 5 4 3 DATA[7:0] R/W — 2 1 0 DATA Eight data digits. These correspond to the character being read or written SIM +0034h Bit Name Type Reset 15 SIM FIFO count register 14 13 12 11 10 SIM_COUNT 9 8 7 6 5 4 3 2 1 COUNT[4:0] R/W 0h 0 COUNT The number of characters in the SIM FIFO when read, and flushes when written. SIM +0040h Bit Name Type Reset 15 SIM activation time register 14 SIM +0044h 15 11 10 9 8 7 ATIME[15:0] R/W AFC7h 6 5 4 3 2 1 0 SIM deactivation time register 14 13 12 11 10 9 8 SIM_DTIME 7 6 5 DTIME[11:0] R/W 3E7h 4 3 2 1 0 The register defines the duration, in 13MHz clock cycles, of the time taken for each of the three stages of the card deactivation sequence DTIME SIM+0048h Bit Name Type Reset 12 The register defines the duration, in SIM clock cycles, of the time taken for each of the three stages of the card activation process ATIME Bit Name Type Reset 13 SIM_ATIME 15 Character to character waiting time register 14 13 12 11 10 9 8 7 WTIME[15:0] R/W 983h 6 5 SIM_WTIME 4 3 2 1 0 WTIME Maximum interval between the leading edge of two consecutive characters in 4 ETU unit 154/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 SIM+004Ch Bit Name Type Reset 15 Block to block guard time register 14 13 12 11 10 9 8 7 SIM_GTIME 6 5 4 3 2 1 GTIME R/W 10d 0 GTIME Minimum interval between the leading edge of two consecutive characters sent in opposite directions in ETU unit SIM +0050h Bit Name Type Reset 15 Block to error signal time register 14 13 12 11 10 9 8 7 SIM_ETIME 6 5 4 3 2 ETIME 1 0 R/W 15d ETIME The register defines the interval, in 1/16 ETU unit, between the end of transmitted parity bit and time to check parity error signal sent from SIM card. SIM +0060h Bit Name Type Reset 15 SIM command header register: INS 14 13 12 11 10 9 8 INSD R/W 0h 7 SIM_INS 6 5 4 3 SIMINS[7:0] R/W 0h 2 1 0 SIMINS This field should be identical to the INS instruction code. When writing to this register, the T=0 controller will be activated and data transfer will be initiated. INSD [Description for this register field] 0 T=0 controller receives data from the SIM card 1 T=0 controller sends data to the SIM card SIM +0064h Bit Name Type Reset 15 SIM_P3 (ICC_LEN) SIM command header register: P3 14 13 12 11 10 9 8 7 6 5 4 3 SIMP3[8:0] R/W 0h 2 1 0 SIMP3 This field should be identical to the P3 instruction code. It should be written prior to the SIM_INS register. While the data transfer is going on, this field shows the no. of the remaining data to be sent or to be received SIM +0068h Bit Name Type Reset 15 SIM_SW1 (ICC_LEN) SIM procedure byte register: SW1 14 13 12 11 10 9 8 7 6 5 4 3 SIMSW1[7:0] R 0h 2 1 0 SIMSW1 This field holds the last received procedure byte for debug purpose. When the T0END interrupt occurred, it keeps the SW1 procedure byte. SIM +006Ch Bit 15 14 SIM_SW2 (ICC_EDC) SIM procedure byte register: SW2 13 12 11 10 9 8 155/599 7 6 5 4 3 2 1 0 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 Name Type Reset SIMSW2[7:0] R 0h SIMSW2 This field holds the SW2 procedure byte 4.4.2 SIM Card Insertion and Removal The detection of physical connection to the SIM card and card removal is done by the external interrupt controller or by GPIO. 4.4.3 Card Activation and Deactivation The card activation and deactivation sequence both are controlled by H/W. The MCU initiates the activation sequence by writing a “1” to bit 0 of the SIM_CON register, and then the interface performs the following activation sequence: z Assert SIMRST LOW z Set SIMVCC at HIGH level and SIMDATA in reception mode z Enable SIMCLK clock z De-assert SIMRST HIGH (required if it belongs to active low reset SIM card) The final step in a typical card session is contact deactivation in order that the card is not electrically damaged. The deactivation sequence is initiated by writing a “0” to bit 0 of the SIM_CONT register, and then the interface performs the following deactivation sequence: z Assert SIMRST LOW z Set SCIMCLK at LOW level z Set SIMDATA at LOW level z Set SIMVCC at LOW level 4.4.4 Answer to Reset Sequence After card activation, a reset operation results in an answer from the card consisting of the initial character TS, followed by at most 32 characters. The initial character TS provides a bit synchronization sequence and defines the conventions to interpret data bytes in all subsequent characters. On reception of the first character, TS, MCU should read this character, establish the respective required convention and reprogram the related registers. These processes should be completed prior to the completion of reception of the next character. And then, the remainder of the ATR sequence is received, read via the SIM_DATA in the selected convention and interpreted by the S/W. The timing requirement and procedures for ATR sequence are handled by H/W and shall meet the requirement of ISO 7816-3 as shown in Figure 20. 156/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 Figure 20 Answer to Reset Sequence Time Value Comment T1 > 400 SIMCLK SIMCLK start to ATR appear T2 < 200 SIMCLK SIMCLK start to SIMDATA in reception mode T3 > 40000 SIMCLK SIMCLK start to SIMRST High T4 — SIMVCC High to SIMCLK start T5 — SIMRST Low to SIMCLK stop T6 — SIMCLK stop to SIMDATA Low T7 — SIMDATA Low to SIMVCC Low Table 16 Answer to Reset Sequence Time-Out Condition 4.4.5 SIM Data Transfer Two transfer modes are provided, either in software controlled byte by byte fashion or in a block fashion using T=0 controller and DMA controller. In both modes, the time-out counter could be enabled to monitor the elapsed time between two consecutive bytes. 1.1.1.1. Byte Transfer Mode This mode is used during ATR and PPS procedure. In this mode, the SIM interface only ensures error free character transmission and reception. Receiving Character Upon detection of the start-bit sent by SIM card, the interface transforms into reception mode and the following bits are shifted into an internal register. If no parity error is detected or character-receive handshaking is disabled, the received-character is written into the SIM FIFO and the SIM_COUNT register is increased by one. Otherwise, the SIMDATA line is held low at 0.5 etu after detecting the parity error for 1.5 etus, and the character is re-received. If a character fails to be received correctly for the RXRETRY times, the receive-handshaking is aborted and the last-received character is written into the SIM FIFO, the SIM_COUNT is increased by one and the RXERR interrupt is generated When the number of characters held in the receive FIFO exceeds the level defined in the SIM_TIDE register, a RXTIDE interrupt is generated. The number of characters held in the SIM FIFO can be 157/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 determined by reading the SIM_COUNT register and writing to this register will flush the SIM FIFO. Sending Character Characters that are to be sent to the card are first written into the SIM FIFO and then automatically transmitted to the card at timed intervals. If character-transmit handshaking is enabled, the SIMDATA line is sampled at 1 etu after the parity bit. If the card indicates that it did not receive the character correctly, the character is retransmitted a maximum of TXRETRY times before a TXERR interrupt is generated and the transmission is aborted. Otherwise, the succeeding byte in the SIM FIFO is transmitted. If a character fails to be transmitted and a TXERR interrupt is generated, the interface needs to be reset by flushing the SIM FIFO before any subsequent transmit or receive operation. When the number of characters held in the SIM FIFO falls below the level defined in the SIM_TIDE register, a TXTIDE interrupt is generated. The number of characters held in the SIM FIFO can be determined by reading the SIM_COUNT register and writing to this register will flush the SIM FIFO. 1.1.1.2. Block Transfer Mode Basically, the SIM interface is designed to work in conjunction with the T=0 protocol controller and the DMA controller during non-ATR and non-PPS phase, though it is still possible for software to service the data transfer manually like in byte transfer mode if necessary and thus the T=0 protocol should be controlled by software. The T=0 controller is accessed via four registers representing the instruction header bytes INS and P3, and the procedure bytes SW1 and SW2. These registers are: SIM_INS, SIM_P3 SIM_SW1, SIM_SW2 During characters transfer, SIM_P3 holds the number of characters to be sent or to be received and SIM_SW1 holds the last received procedure byte including NULL, ACK, NACK and SW1 for debug purpose. Data Receive Instruction Data Receive Instructions receive data from the SIM card. It is instantiated as the following procedure. 1. 2. 3. 4. 5. Enable the T=0 protocol controller by setting the T0EN bit to 1 in SIM_CONF register Program the SIM_TIDE register to 0x0000 (TXTIDE = 0, RXTIDE = 0) Program the SIM_IRQEN to 0x019C (Enable RXERR, TXERR, T0END, TOUT and OVRUN interrupts) Write CLA, INS, P1, P2 and P3 into SIM FIFO Program the DMA controller : DMAn_MSBSRC and DMAn_LSBSRC : address of SIM_DATA register DMAn_MSBDST and DMAn_LSBDST : memory address reserved to store the received characters DMAn_COUNT : identical to P3 or 256 (if P3 == 0) DMAn_CON : 0x0078 6. Write P3 into SIM_P3 register and then INS into SIM_INS register (Data Transfer is initiated now) 7. Enable the Time-out counter by setting the TOUT bit to 1 in SIM_CONF register 8. Start the DMA controller by writing 0x8000 into the DMAn_START register to Upon completion of the Data Receive Instruction, T0END interrupt will be generated and then the Time-out counter should be disabled by setting the TOUT bit back to 0 in SIM_CONF register. 158/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 If error occurs during data transfer (RXERR, TXERR, OVRUN or TOUT interrupt is generated), the SIM card should be deactivated first and then activated prior subsequent operations. Data Send Instruction Data Send Instructions send data to the SIM card. It is instantiated as the following procedure. 1. 2. 3. 4. 5. Enable the T=0 protocol controller by setting the T0EN bit to 1 in SIM_CONF register Program the SIM_TIDE register to 0x0100 (TXTIDE = 1, RXTIDE = 0) Program the SIM_IRQEN to 0x019C (Enable RXERR, TXERR, T0END, TOUT and OVRUN interrupts) Write CLA, INS, P1, P2 and P3 into SIM FIFO Program the DMA controller : DMAn_MSBSRC and DMAn_LSBSRC : memory address reserved to store the transmitted characters DMAn_MSBDST and DMAn_LSBDST : address of SIM_DATA register DMAn_COUNT : identical to P3 DMAn_CON : 0x0074 6. Write P3 into SIM_P3 register and then (0x0100 | INS) into SIM_INS register (Data Transfer is initiated now) 7. Enable the Time-out counter by setting the TOUT bit to 1 in SIM_CONF register 8. Start the DMA controller by writing 0x8000 into the DMAn_START register Upon completion of the Data Send Instruction, T0END interrupt will be generated and then the Time-out counter should be disabled by setting the TOUT bit back to 0 in SIM_CONF register. If error occurs during data transfer (RXERR, TXERR, OVRUN or TOUT interrupt is generated), the SIM card should be deactivated first and then activated prior subsequent operations. 4.5 4.5.1 Keypad Scanner General Description The keypad can be divided into two parts: one is the keypad interface including 8 columns and 8 rows with one dedicated power-key, as shown in Fig. 7 錯誤! 找不到參照來源。錯誤! 找不到參照來源。; the other is the key detection block which provides key pressed, key released and de-bounce mechanisms. Each time the key is pressed or released, i.e. something different in the 8 x 8 matrix or power-key, the key detection block senses the change and recognizes if a key has been pressed or released. Whenever the key status changes and is stable, a KEYPAD IRQ is issued. The MCU can then read the key(s) pressed directly in KP_HI_KEY, KP_MID_KEY and KP_LOW_KEY registers. To ensure that the key pressed information is not missed, the status register in keypad is not read-cleared by APB read command. The status register can only be changed by the key-pressed detection FSM. This keypad can detect one or two key-pressed simultaneously with any combination. Fig. 8 shows one key pressed condition. Fig. 9 (a) and Fig. 9 (b) illustrate two keys pressed cases. Since the key press detection depends on the HIGH or LOW level of the external keypad interface, if keys are pressed at the same time and there exists a key that is on the same column and the same row with the other keys, the pressed key cannot be correctly decoded. For example, if there are three key presses: key1 = (x1, y1), key2 = (x2, y2), and key3 = (x1, y2), then both key3 and key4 = (x2, y1) are detected, and therefore they cannot be distinguished correctly. Hence, the keypad can detect only one or two keys pressed simultaneously at any combination. More than two keys pressed simultaneously in a specific pattern retrieve the wrong information. 159/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 (8 x 8 + o n e p o w e r -k e y ) k e y m a tr ix COL0 ROW 7 D e d ic a te d fo r P o w e r -k e y C O L 1 C O L 2 C O L 3 C O L 4 C O L 5 C O L 6 C O L 7 PW R _K E Y 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ROW 6 ROW 5 ROW 4 ROW 3 ROW 2 ROW 1 ROW 0 B a seb a n d P M IC P M I C in te g r a te d B B c h ip Fig. 7 8x8 matrix with one power-key Key Pressed De-bounce time De-bounce time Key-pressed Status KP_IRQ KEY_PRESS_IRQ KEY_RELEASE_IRQ Fig. 8. One key pressed with de-bounce mechanism denoted 160/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 Key 1 pr essed Key 2 pr essed S t a t us I RQ Key 1 pr essed Key 2 pr essed Key 1 r elea sed Key 2 r elea sed Key 2 r elea sed Key 1 r elea sed (a) Key 1 pr essed Key 2 pr essed S t a t us I RQ Key 2 pr essed Key 1 pr essed (b ) Fig. 9. (a) Two keys pressed, case 1 (b) Two keys pressed, case 2 4.5.2 Register Definitions KP +0000h Keypad status 14 Bit Name Type Reset 15 STA This register indicates the keypad status. 0 No key pressed 1 Key pressed KP +0004h Bit Name Type Reset 15 13 12 11 KP_STA 10 9 8 7 6 5 4 3 2 13 12 11 10 0 STA RO 0 The register is not cleared by the read operation. Keypad scanning output Register 14 1 9 8 7 KEYS [15:0] RO 16’hFFFF KP_MEM1 6 5 4 3 2 1 0 The register shows up the key-press status of key0~key15 KP +0008h Bit Name Type Reset 15 Keypad scanning output Register 14 13 12 11 10 9 8 7 KEYS [15:0] RO 16’hFFFF KP_MEM2 6 5 4 3 2 1 0 The register shows up the key-press status of key16~key31 KP +000Ch Bit 15 Keypad scanning output Register 14 13 12 11 10 9 8 161/599 7 KP_MEM3 6 5 4 3 2 1 0 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 Name Type Reset KEYS [15:0] RO 16’hFFFF The register shows up the key-press status of key32~key47 KP +0010h Bit Name Type Reset 15 Keypad scanning output Register 14 13 12 11 10 9 8 7 KEYS [15:0] RO 16’hFFFF KP_MEM4 6 5 4 3 2 1 0 The register shows up the key-press status of key48~key63 KP +0014h Bit Name Type Reset 15 Keypad scanning output Register 14 13 12 11 10 9 8 7 KP_MEM5 6 5 4 3 KEYS [7:0] RO 8’hFF 2 1 0 The register shows up the key-press status of key64~key71 These two registers list the status of 35 keys on the keypad but KEY[8], KEY[17], KEY[26], KEY[35], KEY[44] , KEY[53] , KEY[62] , KEY[71] is dedicated for power key. When the MCU receives the KEYPAD IRQ, both two registers must be read. If any key is pressed, the relative bit is set to 0. KEYS Status list of the 72 keys. KP +00018h Bit Name Type Reset 15 De-bounce period setting 14 13 12 11 10 9 KP_DEBOUNCE 8 7 6 5 DEBOUNCE [13:0] R/W 400h 4 3 2 1 0 This register defines the waiting period before key press or release events are considered stale. DEBOUNCE 4.6 De-bounce time = KP_DEBOUNCE/32 ms. General Purpose Inputs/Outputs MT6235 offers 76 general-purpose I/O pins. By setting the control registers, MCU software can control the direction, the output value, and read the input values on these pins. These GPIOs are multiplexed with other functionalities to reduce the pin count. There are 10 clock-out ports embedded in 76 GPIO pins, and each clock-out can be programmed to output appropriate clock source. 162/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 Figure 21 GPIO Block Diagram GPIOs at RESET Upon hardware reset (SYSRST#), GPIOs are all configured as inputs and the following alternative usages of GPIO pins are enabled: These GPIOs are used to latch the inputs upon reset to memorize the desired configuration to make sure that the system restarts or boots in the right mode. Multiplexing of Signals on GPIO The GPIO pins can be multiplexed with other signals. z CMRST, CMPDN, CMVREF, CMHREF, CMPCLK, CMMCLK, CMDAT7~0, CMFLASH: CMOS sensor interface z SCL, SDL: I2C interface z DAICLK, DAIPCMIN, DAIPCMOUT, DAIRST, DAISYNC: digital audio interface for FTA z BPI_BUS3, BPI_BUS6, BPI_BUS7, BPI_BUS8, BPI_BUS9: radio hard-wire control z BSI_CS1: additional chip select signal for radio 3-wire interface z LSCK, LSA0, LSDA, LSCE0#, LSCE1#: serial display interface z NRNB, NCLE, NALE, NWEB, NCE0# NCE1#: Nandflash interface z NLD17, NLD16, LPCE1#, LPECE2#, LPTE: parallel display interface data and chip select signal z PWM0, PWM1, PWM2, PWM3 : pulse width modulation signal z URTS1, UCTS1: data and flow control signals for UART1 z URXD2, UTXD2, URTS2, UCTS2: data and flow control signals for UART2 z URXD3, UTXD3, URTS3, UCTS3: data signals for UART3 z IDRA_RXD, IRDA_TXD, IRDA_PDN: IrDA interface signals z SRCLKENAI, SRCLKENA, SRCLKENAN: external power on signal of the external VCXO LDO z EINT3, EINT4, EINT5, EINT6, EINT7: External interrupt signals z KCOL7, KCOL6, KROW7, KROW6: Keypad signals 163/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 z EADMUX: External Memory AD-MUX select signal z EA26: external memory interface address bit 26 z MC0CM0, MC0DA0~3, MC0CK, MC0PWRON, MC0WP, MC0INS : MMC Card 0 interface z IRQ2, IRQ1, IRQ0 : external interrupt z 32KHz, 6.5MHz, 13MHz, 26MHz clocks 4.6.1 Register Definitions GPIO+0000h GPIO direction control register 1 GPIO_DIR1 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 GPIO1 GPIO1 GPIO1 GPIO1 GPIO1 GPIO1 GPIO Name GPIO9 GPIO8 GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 5 4 3 2 1 0 0 Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GPIO +0040h GPIO direction control register 2 GPIO_DIR2 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 GPIO3 GPIO3 GPIO2 GPIO2 GPIO2 GPIO2 GPIO2 GPIO2 GPIO2 GPIO2 GPIO2 PGIO2 GPIO1 GPIO1 GPIO1 GPIO Name 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 16 Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GPIO+0080h GPIO direction control register 3 GPIO_DIR3 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 GPIO4 GPIO4 GPIO4 GPIO4 GPIO4 GPIO4 GPIO4 GPIO4 GPIO3 GPIO3 GPIO3 GPIO3 GPIO3 GPIO3 GPIO3 GPIO Name 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 32 Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GPIO+00C0h GPIO direction control register 4 GPIO_DIR4 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 GPIO6 GPIO6 GPIO6 GPIO6 GPIO5 GPIO5 GPIO5 GPIO5 GPIO5 GPIO5 GPIO5 GPIO5 GPIO5 GPIO5 GPIO4 GPIO Name 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 48 Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GPIO+0100h Bit Name Type Reset 15 14 GPIO direction control register 5 13 12 GPIO_DIR5 11 10 9 8 7 6 5 4 3 2 1 0 GPIO7 GPIO7 GPIO7 GPIO7 GPIO7 GPIO7 GPIO6 GPIO6 GPIO6 GPIO6 GPIO6 GPIO 5 4 3 2 1 0 9 8 7 6 5 64 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 0 0 0 0 GPIOn GPIO direction control 0 GPIOs are configured as input 1 GPIOs are configured as output 164/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 GPIO +0200h GPIO pull-up/pull-down enable register 1 GPIO_PULLEN1 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 GPIO1 GPIO1 GPIO1 GPIO1 GPIO1 GPIO1 GPIO Name GPIO9 GPIO8 GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 5 4 3 2 1 0 0 Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 GPIO +0240h GPIO pull-up/pull-down enable register 2 GPIO_PULLEN2 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 GPIO3 GPIO3 GPIO2 GPIO2 GPIO2 GPIO2 GPIO2 GPIO2 GPIO2 GPIO2 GPIO2 PGIO2 GPIO1 GPIO1 GPIO1 GPIO Name 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 16 Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 GPIO+0280h GPIO pull-up/pull-down enable register 3 GPIO_PULLEN3 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 GPIO4 GPIO4 GPIO4 GPIO4 GPIO4 GPIO4 GPIO4 GPIO4 GPIO3 GPIO3 GPIO3 GPIO3 GPIO3 GPIO3 GPIO3 GPIO Name 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 32 Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 0 0 1 1 0 0 0 0 0 1 1 GPIO+02C0h GPIO pull-up/pull-down enable register 4 GPIO_PULLEN4 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 GPIO6 GPIO6 GPIO6 GPIO6 GPIO5 GPIO5 GPIO5 GPIO5 GPIO5 GPIO5 GPIO5 GPIO5 GPIO5 GPIO5 GPIO4 GPIO Name 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 48 Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 GPIO+0300h Bit 15 14 Name Type Reset GPIO pull-up/pull-down enable register 5 13 12 GPIO_PULLEN5 11 10 9 8 7 6 5 4 3 2 1 0 GPIO7 GPIO7 GPIO7 GPIO7 GPIO7 GPIO7 GPIO6 GPIO6 GPIO6 GPIO6 GPIO6 GPIO 5 4 3 2 1 0 9 8 7 6 5 64 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 1 1 1 1 1 1 1 1 1 1 0 0 GPIOn GPIO pull up/down enable 0 GPIOs pull up/down is not enabled 1 GPIOs pull up/down is enabled GPIO +0400h GPIO pull-up/pull-down select register 1 GPIO_PULLSEL 1 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 GPIO1 GPIO1 GPIO1 GPIO1 GPIO1 GPIO1 GPIO Name GPIO9 GPIO8 GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 5 4 3 2 1 0 0 Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 165/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 GPIO +0440h GPIO_PULLSEL 2 GPIO pull-up/pull-down select register 2 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 GPIO3 GPIO3 GPIO2 GPIO2 GPIO2 GPIO2 GPIO2 GPIO2 GPIO2 GPIO2 GPIO2 PGIO2 GPIO1 GPIO1 GPIO1 GPIO Name 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 16 Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 1 GPIO+0480h GPIO_PULLSEL 3 GPIO pull-up/pull-down select register 3 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 GPIO4 GPIO4 GPIO4 GPIO4 GPIO4 GPIO4 GPIO4 GPIO4 GPIO3 GPIO3 GPIO3 GPIO3 GPIO3 GPIO3 GPIO3 GPIO Name 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 32 Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 0 GPIO+04C0h GPIO_PULLSEL 4 GPIO pull-up/pull-down select register 4 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 GPIO6 GPIO6 GPIO6 GPIO6 GPIO5 GPIO5 GPIO5 GPIO5 GPIO5 GPIO5 GPIO5 GPIO5 GPIO5 GPIO5 GPIO4 GPIO Name 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 48 Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 1 0 0 0 0 0 1 1 1 1 1 1 0 1 1 GPIO+0500h Bit 15 14 Name Type Reset GPIO_PULLSEL 5 GPIO pull-up/pull-down select register 5 13 12 11 10 9 8 7 6 5 4 3 2 1 0 GPIO7 GPIO7 GPIO7 GPIO7 GPIO7 GPIO7 GPIO6 GPIO6 GPIO6 GPIO6 GPIO6 GPIO 5 4 3 2 1 0 9 8 7 6 5 64 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 1 1 1 1 1 1 1 1 1 1 0 0 GPIOn GPIO pull up/down selection 0 GPIOs pull down is selected 1 GPIOs pull up is selected GPIO +0600h GPIO data inversion control register 1 Bit 15 14 13 12 11 10 9 Name INV15 INV14 INV13 INV12 INV11 INV10 INV9 Type R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 GPIO +0640h 8 INV8 R/W 0 7 INV7 R/W 0 6 INV6 R/W 0 GPIO data inversion control register 2 GPIO_DINV1 5 INV5 R/W 0 4 INV4 R/W 0 3 INV3 R/W 0 2 INV2 R/W 0 1 INV1 R/W 0 0 INV0 R/W 0 GPIO_DINV2 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name INV31 INV30 INV29 INV28 INV27 INV26 INV25 INV24 INV23 INV22 INV21 INV20 INV19 IVN18 INV17 INV16 Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 166/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 GPIO +0680h GPIO data inversion control register 3 GPIO_DINV3 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name INV47 INV46 INV45 INV44 INV43 INV42 INV41 INV40 INV39 INV38 INV37 INV36 INV35 INV34 INV33 INV32 Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GPIO+06C0h GPIO data inversion control register 4 GPIO_DINV4 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name NV63 INV62 INV61 INV60 INV59 INV58 INV57 INV56 INV55 INV54 INV53 INV52 INV51 INV50 INV49 INV48 Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GPIO+0700h 14 GPIO data inversion control register 5 Bit Name Type Reset 15 INVn GPIO inversion control 0 GPIOs data inversion disable 1 GPIOs data inversion enable GPIO +0800h 13 12 GPIO_DINV5 11 10 9 8 7 6 5 4 3 2 1 0 INV75 INV74 INV73 INV72 INV71 INV70 INV69 INV68 INV67 INV66 INV65 INV64 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 0 0 0 0 GPIO data output register 1 GPIO_DOUT1 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 GPIO1 GPIO1 GPIO1 GPIO1 GPIO1 GPIO1 GPIO Name GPIO9 GPIO8 GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 5 4 3 2 1 0 0 Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GPIO +0840h GPIO data output register 2 GPIO_DOUT2 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 GPIO3 GPIO3 GPIO2 GPIO2 GPIO2 GPIO2 GPIO2 GPIO2 GPIO2 GPIO2 GPIO2 PGIO2 GPIO1 GPIO1 GPIO1 GPIO Name 4 3 2 1 0 9 8 7 16 1 0 9 8 7 6 5 Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GPIO +0880h GPIO data output register 3 GPIO_DOUT3 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 GPIO4 GPIO4 GPIO4 GPIO4 GPIO4 GPIO4 GPIO4 GPIO4 GPIO3 GPIO3 GPIO3 GPIO3 GPIO3 GPIO3 GPIO3 GPIO Name 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 32 Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GPIO+08C0h Bit 15 14 GPIO data output register 4 13 12 11 10 9 GPIO_DOUT4 8 167/599 7 6 5 4 3 2 1 0 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 GPIO6 GPIO6 GPIO6 GPIO6 GPIO5 GPIO5 GPIO5 GPIO5 GPIO5 GPIO5 GPIO5 GPIO5 GPIO5 GPIO5 GPIO4 GPIO 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 48 Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Name GPIO+0900h Bit 15 14 GPIO data output register 5 13 12 Name Type Reset GPIO_DOUT5 11 10 9 8 7 6 5 4 3 2 1 0 GPIO7 GPIO7 GPIO7 GPIO7 GPIO7 GPIO7 GPIO6 GPIO6 GPIO6 GPIO6 GPIO6 GPIO 5 4 3 2 1 0 9 8 7 6 5 64 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 0 0 0 0 GPIOn GPIO data output control 0 GPIOs data output 1 1 GPIOs data output 0 GPIO +0A00h GPIO data Input register 1 GPIO_DIN1 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 GPIO1 GPIO1 GPIO1 GPIO1 GPIO1 GPIO1 GPIO Name GPIO9 GPIO8 GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 5 4 3 2 1 0 0 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset X X X X X X X X X X X X X X X X GPIO +0A40h GPIO data Input register 2 GPIO_DIN2 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 GPIO3 GPIO3 GPIO2 GPIO2 GPIO2 GPIO2 GPIO2 GPIO2 GPIO2 GPIO2 GPIO2 PGIO2 GPIO1 GPIO1 GPIO1 GPIO Name 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 16 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset X X X X X X X X X X X X X X X X GPIO +0A80h GPIO data Input register 3 GPIO_DIN3 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 GPIO4 GPIO4 GPIO4 GPIO4 GPIO4 GPIO4 GPIO4 GPIO4 GPIO3 GPIO3 GPIO3 GPIO3 GPIO3 GPIO3 GPIO3 GPIO Name 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 32 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset X X X X X X X X X X X X X X X X GPIO+0AC0h GPIO data input register 4 GPIO_DIN4 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 GPIO6 GPIO6 GPIO6 GPIO6 GPIO5 GPIO5 GPIO5 GPIO5 GPIO5 GPIO5 GPIO5 GPIO5 GPIO5 GPIO5 GPIO4 GPIO Name 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 48 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset X X X X X X X X X X X X X X X X GPIO+0B00h Bit 15 14 GPIO data input register 5 13 Name Type Reset 12 GPIO_DIN5 11 10 9 8 7 6 5 4 3 2 1 0 GPIO7 GPIO7 GPIO7 GPIO7 GPIO7 GPIO7 GPIO6 GPIO6 GPIO6 GPIO6 GPIO6 GPIO 5 4 3 2 1 0 9 8 7 6 5 64 RO RO RO RO RO RO RO RO RO RO RO RO X X X X X X X X X X X X GPIOn GPIOs data input 168/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 GPIO +1000h Bit Name Type Reset 15 14 GPIO7_M R/W 00 GPIO0_M 00 01 10 11 GPIO1_M 00 01 10 11 GPIO2_M 00 01 10 11 GPIO3_M 00 01 10 11 GPIO4_M 00 01 10 11 GPIO5_M 00 01 10 11 GPIO6_M 00 01 10 11 GPIO7_M 00 GPIO mode control register 1 13 12 GPIO6_M R/W 00 11 10 GPIO5_M R/W 00 9 8 GPIO4_M R/W 00 GPIO_MODE1 7 6 GPIO3_M R/W 00 5 4 GPIO2_M R/W 00 3 2 GPIO1_M R/W 00 1 0 GPIO0_M R/W 00 GPIO mode selection Configured as GPIO function CMOS Sensor Reset control Signal (CMRST) clk_out0 DSP_GPO0 (DSP_GPO0) GPIO mode selection Configured as GPIO function CMOS Sensor Power Down control Signal (CMPDN) DSP_GPO1 (DSP_GPO1) Reserved GPIO mode selection Configured as GPIO function CMOS Sensor Vertical Reference input (CMVREF) TDMA Debug (TBTXEN) Master DSP Task ID bit 0(D1_TID0) GPIO mode selection Configured as GPIO function CMOS Sensor Horizontal Reference input (CMHREF) TDMA Debug (TBTXFS) Reserved GPIO mode selection Configured as GPIO function CMOS Sensor Clock input signal (CMPCLK) TDMA Debug (TBRXEN) Master DSP Task ID bit 1(D1_TID1) GPIO mode selection Configured as GPIO function CMOS Sensor Clock output signal (CMMCLK) TDMA Debug (TBRXFS) Reserved GPIO mode selection Configured as GPIO function CMOS Sensor Data input signal bit7 (CMDAT7) Reserved Master DSP ICE Clock (D1ICK)) GPIO mode selection Configured as GPIO function 169/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 01 CMOS Sensor Data input signal bit6 (CMDAT6) 10 Reserved 11 Master DSP ICE Data (D1ID) GPIO +1100h Bit Name Type Reset 15 14 GPIO15_M R/W 00 GPIO8_M 00 01 10 11 GPIO9_M 00 01 10 11 GPIO10_M 00 01 10 11 GPIO11_M 00 01 10 11 GPIO12_M 00 01 10 11 GPIO13_M 00 01 10 11 GPIO14_M 00 01 10 11 GPIO mode control register 2 13 12 GPIO14_M R/W 00 11 10 GPIO13_M R/W 00 9 8 GPIO12_M R/W 00 GPIO_MODE2 7 6 GPIO11_M R/W 00 5 4 GPIO10_M R/W 00 3 2 GPIO9_M R/W 00 1 0 GPIO8_M R/W 00 GPIO mode selection Configured as GPIO function CMOS Sensor Data input signal bit5 (CMDAT5) Reserved Master DSP ICE Model Select (D1IMS) GPIO mode selection Configured as GPIO function CMOS Sensor Data input signal bit4 (CMDAT4) Reserved Slave DSP ICE Clock (D2ICK) GPIO mode selection Configured as GPIO function CMOS Sensor Data input signal bit3 (CMDAT3) Reserved Slave DSP ICE Data (D2ID) GPIO mode selection Configured as GPIO function CMOS Sensor Data input signal bit2 (CMDAT2) Reserved Slave DSP ICE Mode Select (D2IMS) GPIO mode selection Configured as GPIO function CMOS Sensor Data input signal bit1 (CMDAT1) Reserved Slave DSP Task ID Bit0 (D2_TID0) GPIO mode selection Configured as GPIO function CMOS Sensor Data input signal bit 0 (CMDAT0) Resereved Slave DSP Task ID Bit1 (D2_TID1) GPIO mode selection Configured as GPIO function CMOS Sensor Flash Control (CMFLASH) Reserved Slave DSP Task ID Bit2 (D2_TID2) 170/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 GPIO15_M 00 01 10 11 GPIO mode selection Configured as GPIO function I2C Clock (SCL) Reserved Slave DSP Task ID Bit3 (D2_TID3) GPIO +1200h Bit Name Type Reset 15 14 GPIO23_M R/W 00 GPIO16_M 00 01 10 11 GPIO17_M 00 01 10 11 GPIO18_M 00 01 10 11 GPIO19_M 00 01 10 11 GPIO20_M 00 01 10 11 GPIO21_M 00 01 10 11 GPIO22_M 00 01 GPIO mode control register 3 13 12 GPIO22_M R/W 00 11 10 GPIO21_M R/W 00 9 8 GPIO20_M R/W 00 GPIO_MODE3 7 6 GPIO19_M R/W 00 5 4 GPIO18_M R/W 00 3 2 GPIO17_M R/W 00 1 0 GPIO16_M R/W 00 GPIO mode selection Configured as GPIO function I2C Data (SDA) Reserved Slave DSP Task ID Bit4 (D2_TID4) GPIO mode selection Configured as GPIO function PWM2 (PWM2) Reserved Slave DSP Task ID Bit5 (D2_TID5) GPIO mode selection Configured as GPIO function PWM3 (PWM3) Reserved Slave DSP Task ID Bit6 (D2_TID6) GPIO mode selection Configured as GPIO function BPI_BUS3 (BPI_BUS3) Reserved Reserved GPIO mode selection Configured as GPIO function BPI_BUS6 (BPI_BUS6) Reserved Reserved GPIO mode selection Configured as GPIO function BPI_BUS7 (BPI_BUS7) Reserved Reserved GPIO mode selection Configured as GPIO function BPI_BUS8 (BPI_BUS8) 171/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 10 11 GPIO23_M 00 01 10 11 Reserved Reserved GPIO mode selection Configured as GPIO function BPI_BUS9 (BPI_BUS9) BSI_CS1 (BS1_CS1) Reserved GPIO +1300h Bit Name Type Reset 15 14 GPIO31_M R/W 00 GPIO24_M 00 01 10 11 GPIO25_M 00 01 10 11 GPIO26_M 00 01 10 11 GPIO27_M 00 01 10 11 GPIO28_M 00 01 10 11 GPIO29_M 00 01 10 11 GPIO mode control register 4 13 12 GPIO30_M R/W 00 11 10 GPIO29_M R/W 00 9 8 GPIO28_M R/W 00 GPIO_MODE4 7 6 GPIO27_M R/W 00 5 4 GPIO26_M R/W 00 3 2 GPIO25_M R/W 00 1 0 GPIO24_M R/W 00 GPIO mode selection Configured as GPIO function Serial LCD Clock Output (LSCK) DSP_GPO2 Interrupt Input 0 (IRQ0) GPIO mode selection Configured as GPIO function Serial LCD Address (LSA0) DSP_GPO3 Interrupt Input 1 (IRQ1) GPIO mode selection Configured as GPIO function Serial LCD Data (LSDA) clk_out1 TDMA Timer Debug (TDTIRQ) GPIO mode selection Configured as GPIO function Serial LCD Chip Select 0 (LSCE0#) clk_out2 TDMA Timer Debug (TCTIRQ2) GPIO mode selection Configured as GPIO function Serial LCD Chip Select 1 (LSCE1#) Parallel LCD Chip Select 2 (LPCE2#) TDMA Timer Debug (TCTIRQ1) GPIO mode selection Configured as GPIO function Parallel LCD Chip Select 1 (LPCE1#) Nandflash Interface Chip Select 1 (NCE1#) TDMA Timer Debug (TEVTVAL) 172/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 GPIO30_M 00 01 10 11 GPIO31_M 00 01 10 11 GPIO mode selection Configured as GPIO function LCD LPTE (LPTE) Reserved Reserved GPIO mode selection Configured as GPIO function Parallel LCD Data Bit17 (NLD17) Reserved Reserved GPIO +1400h Bit Name Type Reset 15 14 GPIO39_M R/W 00 GPIO32_M 00 01 10 11 GPIO33_M 00 01 10 11 GPIO34_M 00 01 10 11 GPIO35_M 00 01 10 11 GPIO36_M 00 01 10 11 GPIO37_M 00 01 GPIO mode control register 5 13 12 GPIO38_M R/W 01 11 10 GPIO37_M R/W 01 9 8 GPIO36_M R/W 01 GPIO_MODE5 7 6 GPIO35_M R/W 01 5 4 GPIO34_M R/W 01 3 2 GPIO33_M R/W 01 1 0 GPIO32_M R/W 00 GPIO mode selection Configured as GPIO function Nandflash/Parallel LCD Interface Bit16 (NLD16) Reserved Reserved GPIO mode selection Configured as GPIO function Nandflash Interface Ready/Busy Signal (NRNB) Reserved Reserved GPIO mode selection Configured as GPIO function Nandflash Interface Command Latch Signal (NCLE) Reserved Reserved GPIO mode selection Configured as GPIO function Nandflash Interface Address Latch Signal (NALE) Reserved Reserved GPIO mode selection Configured as GPIO function Nandflash Interface Write Enable Signal (NWEB) Reserved Reserved GPIO mode selection Configured as GPIO function Nandflash Interface Read Enable Signal (NREB) 173/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 10 11 GPIO38_M 00 01 10 11 GPIO39_M 00 01 10 11 Reserved Reserved GPIO mode selection Configured as GPIO function Nandflash Interface Chip Select 0 (NCE0#) Reserved Reserved GPIO mode selection Configured as GPIO function PWM0 (PWM0) Reserved Reserved GPIO +1500h Bit Name Type Reset 15 14 GPIO47_M R/W 00 GPIO40_M 00 01 10 11 GPIO41_M 00 01 10 11 GPIO42_M 00 01 10 11 GPIO43_M 00 01 10 11 GPIO44_M 00 01 10 11 GPIO mode control register 6 13 12 GPIO46_M R/W 00 11 10 GPIO45_M R/W 00 9 8 GPIO44_M R/W 00 GPIO_MODE6 7 6 GPIO43_M R/W 00 5 4 GPIO42_M R/W 01 3 2 GPIO41_M R/W 01 1 0 GPIO40_M R/W 00 GPIO mode selection Configured as GPIO function PWM1 (PWM1) BSI_RFIN(BSI_RFIN) Reserved GPIO mode selection Configured as GPIO function VCXO enable output signal high active (SRCLKENA) Reserved Reserved GPIO mode selection Configured as GPIO function VCXO enable output signal low active (SRCLKENAN) Reserved Reserved GPIO mode selection Configured as GPIO function VCXO enable input signal (SRCLKENAI) Reserved Reserved GPIO mode selection Configured as GPIO function External Interrupt 3 (EINT3) Reserved Interrupt Input 2 (IRQ2) 174/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 GPIO45_M 00 01 10 11 GPIO46_M 00 01 10 11 GPIO47_M 00 01 10 11 GPIO mode selection Configured as GPIO function External Interrupt 4 (EINT4) Reserved clock_out3 GPIO mode selection Configured as GPIO function External Interrupt 5 (EINT5) EDICK (EDICK) Reserved GPIO mode selection Configured as GPIO function External Interrupt 6 (EINT6) EDIWS (EDIWS) Reserved GPIO +1600h Bit Name Type Reset 15 14 GPIO55 R/W 00 GPIO48_M 00 01 10 11 GPIO49_M 00 01 10 11 GPIO50_M 00 01 10 11 GPIO51_M 00 01 10 11 GPIO52_M 00 01 GPIO mode control register 7 13 12 GPIO54 R/W 00 11 10 GPIO53 R/W 00 9 8 GPIO52 R/W 00 GPIO_MODE7 7 6 GPIO51 R/W 00 5 4 GPIO50 R/W 01 3 2 GPIO49 R/W 01 1 0 GPIO48 R/W 00 GPIO mode selection Configured as GPIO function External Interrupt 7 (EINT7) EDIDAT (EDIDAT) Reserved GPIO mode selection Configured as GPIO function UART1 CTS Signal (UCTS1) UART2 CTS Signal (UCTS2) Reserved GPIO mode selection Configured as GPIO function UART1 RTC Signal (URTS1) UART2 RTC Signal (URTS2) Reserved GPIO mode selection Configured as GPIO function UART2 RXD Signal (URXD2) UART3 CTS Signal (UCTS3) Reserved GPIO mode selection Configured as GPIO function UART2 TXD Signal (UTXD2) 175/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 10 UART3 RTS Signal (URTS3) 11 Reserved GPIO53_M GPIO mode selection 00 Configured as GPIO function 01 UART3 RXD Signal (URXD3) 10 IrDA RXD Signal (IRDA_RXD) 11 Reserved GPIO54_M GPIO mode selection 00 Configured as GPIO function 01 UART3 TXD Signal (UTXD3) 10 IrDA TXD Signal (IRDA_TXD) 11 Reserved GPIO55_M GPIO mode selection 00 Configured as GPIO function 01 Keyboard Column 7 (KCOL7) 10 IrDA Power Down Signal (IRDA_PDN) 11 Reserved GPIO +1700h Bit Name Type Reset 15 14 GPIO63 R/W 00 GPIO56_M 00 01 10 11 GPIO57_M 00 01 10 11 GPIO58_M 00 01 10 11 GPIO59_M 00 01 10 11 GPIO mode control register 8 13 12 GPIO62 R/W 00 11 10 GPIO61 R/W 00 9 8 GPIO60 R/W 00 GPIO_MODE8 7 6 GPIO59 R/W 00 5 4 GPIO58 R/W 00 3 2 GPIO57 R/W 00 1 0 GPIO56 R/W 00 GPIO mode selection Configured as GPIO function Keyboard Column 6 (KCOL6) Reserved Reserved GPIO mode selection Configured as GPIO function Keyboard Row 7 (KROW7) clock-out4 Reserved GPIO mode selection Configured as GPIO function Keyboard Row 6 (KROW6) Reserved Reserved GPIO mode selection Configured as GPIO function Digital Audio Interface PCM Clock Output (DAICLK) Reserved Reserved 176/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 GPIO60_M GPIO mode selection 00 Configured as GPIO function 01 Digital Audio Interface PCM Data Output (DAIPCMOUT) 10 Reserved 11 Reserved GPIO61_M GPIO mode selection 00 Configured as GPIO function 01 Digital Audio Interface PCM Data Input (DAIPCMIN) 10 Reserved 11 Reserved GPIO62_M GPIO mode selection 00 Configured as GPIO function 01 Digital Audio Interface Reset Signal (DAIRST) 10 Reserved 11 Reserved GPIO63_M GPIO mode selection 00 Configured as GPIO function 01 Digital Audio Interface Sync Signal (DAISYNC) 10 Reserved 11 Reserved GPIO +1800h Bit Name Type Reset 15 14 GPIO71 R/W 00 GPIO64_M 00 01 10 11 GPIO65_M 00 01 10 11 GPIO66_M 00 01 10 11 GPIO67_M 00 GPIO mode control register 9 13 12 GPIO70 R/W 00 11 10 GPIO69 R/W 00 9 8 GPIO68 R/W 00 GPIO_MODE9 7 6 GPIO67 R/W 00 5 4 GPIO66 R/W 00 3 2 GPIO65 R/W 01 1 0 GPIO64 R/W 01 GPIO mode selection Configured as GPIO function External memory address bit 26 (EA26) clock_out5 Reserved GPIO mode selection Configured as GPIO function EADMUX Only used when being boot-up. After system reset, EADMUX is of no use. clock_out6 Reserved GPIO mode selection Configured as GPIO function MFIQ (MFIQ) clock_out7 Reserved GPIO mode selection Configured as GPIO function 177/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 01 Memory Card 0 Command signal (MC0CM0) 10 Reserved 11 TDMA Timer Debug (TDMA_CK) GPIO68_M GPIO mode selection 00 Configured as GPIO function 01 Memory Card 0 Data Bit 0 (MC0DA0) 10 Reserved 11 TDMA Timer Debug (TDMA_D1) GPIO69_M GPIO mode selection 00 Configured as GPIO function 01 Memory Card 0 Data Bit 1 (MC0DA1) 10 Reserved 11 TDMA Timer Debug (TDMA_D0) GPIO70_M GPIO mode selection 00 Configured as GPIO function 01 Memory Card 0 Data Bit 2 (MC0DA2) 10 Reserved 11 TDMA Timer Debug (TDMA_FS) GPIO71_M GPIO mode selection 00 Configured as GPIO function 01 Memory Card 0 Data Bit 3 (MC0DA3) 10 Reserved 11 Reserved GPIO +1900h Bit Name Type Reset 15 GPIO72_M 00 01 10 11 GPIO73_M 00 01 10 11 GPIO74_M 00 01 10 14 GPIO mode control register A 13 12 11 10 9 8 GPIO_MODEA 7 6 GPIO75 R/W 00 5 4 GPIO74 R/W 00 3 2 GPIO73 R/W 00 1 0 GPIO72 R/W 00 GPIO mode selection Configured as GPIO function Memory Card 0 Clock output (MC0CK) Reserved Reserved GPIO mode selection Configured as GPIO function Memory Card 0 Power On (MC0PWRON) clock_out8 Reserved GPIO mode selection Configured as GPIO function Memory Card 0 Write Protection (MC0WP) clock_out9 178/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 11 GPIO75_M 00 01 10 11 Reserved GPIO mode selection Configured as GPIO function Memory Card 0 Card insertion identification (MC0INS) Reserved Reserved GPIO+3000h Bit 15 Name Type R/W Reset 0 CLK_OUT1 setting CLK_OUT1 14 13 12 11 10 9 8 7 6 5 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 8 7 6 5 4 3 2 1 CLKOUT R/W 0 4 3 2 1 CLKOUT R/W 0 0 CLKOUT select the clock output source of clk_out0 0 f65m_ck, 6.5MHz 1 f104m_ck 2 f52m_ck 3 f26m_ck 4 f13m_ck 5 fmcu_ck 6 f32k_ck 7 gdsp1_ck 8 gdsp2_ck 9 mcu_hclk_ck, A 104Mhz AHB clock B mclk_ck C slow_ck D fdsp_ck E fusb_ck F f48m_ck 10 f52m_en Other Reserved GPIO+3100h Bit Name Type Reset 15 CLKOUT 14 15 13 12 11 10 CLK_OUT2 9 0 select the clock output source of clk_out1 GPIO+3200h Bit Name CLK_OUT2 setting 14 CLK_OUT3 setting 13 12 11 10 CLK_OUT3 9 8 179/599 7 6 5 4 3 2 1 CLKOUT 0 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 Type Reset R/W 0 select the clock output source of clk_out2 CLKOUT GPIO+3300h Bit Name Type Reset 15 CLK_OUT4 setting 14 GPIO+3400h 15 4 3 2 1 CLKOUT R/W 0 0 13 12 11 10 CLK_OUT5 9 8 7 6 5 4 3 2 1 CLKOUT R/W 0 0 13 12 11 10 CLK_OUT6 9 8 7 6 5 4 3 2 1 CLKOUT R/W 0 0 13 12 11 10 CLK_OUT7 9 8 7 6 5 4 3 2 1 CLKOUT R/W 0 8 7 6 5 4 3 2 1 CLKOUT R/W 0 0 13 12 11 10 CLK_OUT8 9 0 select the clock output source of clk_out7 GPIO+3800h 15 5 CLK_OUT8 setting 14 CLKOUT Bit 6 select the clock output source of clk_out6 GPIO+3700h 15 7 CLK_OUT7 setting 14 CLKOUT Bit Name Type Reset 8 select the clock output source of clk_out5 GPIO+3600h 15 9 CLK_OUT6 setting 14 CLKOUT Bit Name Type Reset 10 select the clock output source of clk_out4 GPIO+3500h 15 11 CLK_OUT5 setting 14 CLKOUT Bit Name Type Reset 12 select the clock output source of clk_out3 CLKOUT Bit Name Type Reset 13 CLK_OUT4 14 CLK_OUT9 setting 13 12 11 10 CLK_OUT9 9 8 180/599 7 6 5 4 3 2 1 0 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 Name Type Reset CLKOUT R/W 0 select the clock output source of clk_out8 CLKOUT GPIO+3900h Bit Name Type Reset 15 CLK_OUT10 setting 14 13 12 11 10 CLK_OUT10 9 8 7 6 5 4 3 2 1 CLKOUT R/W 0 0 select the clock output source of clk_out9 CLKOUT GPIO+xxx4h GPIO xxx register SET GPIO_XXX_SET For all registers addresses listed above, writing to the +4h addresse offset will perform a bit-wise OR function between the 16bit written value and the 16bit register value already existing in the corresponding GPIO_xxx registers. Eg. If GPIO_DIR1 (GPIO+0000h) = 16’h0F0F, writing GPIO_DIR1_SET (GPIO+0004h) = 16’F0F0 will result in GPIO_DIR1 = 16’hFFFF. GPIO+xxx8h GPIO xxx register CLR GPIO_XXX_CLR For all registers addresses listed above, writing to the +8h addresse offset will perform a bit-wise AND-NOT function between the 16bit written value and the 16bit register value already existing in the corresponding GPIO_xxx registers. Eg. If GPIO_DIR1 (GPIO+0000h) = 16’h0F0F, writing GPIO_DIR1_CLR (GPIO+0008h) = 16’0F0F will result in GPIO_DIR1 = 16’h0000. 4.7 4.7.1 General Purpose Timer General Description Three general-purpose timers are provided. The timers are 16 bits long and run independently of each other, although they share the same clock source. Two timers can operate in one of two modes: one-shot mode and auto-repeat mode; the other is a free running timer. In one-shot mode, when the timer counts down and reaches zero, it is halted. In auto-repeat mode, when the timer reaches zero, it simply resets to countdown initial value and repeats the countdown to zero; this loop repeats until the disable signal is set to 1. Regardless of the timer’s mode, if the countdown initial value (i.e. GPTIMER1_DAT for GPT1 or GPTIMER_DAT2 for GPT2) is written when the timer is running, the new initial value does not take effect until the next time the timer is restarted. In auto-repeat mode, the new countdown start value is used on the next countdown iteration. Therefore, before enabling the gptimer, the desired values for GPTIMER_DAT and the GPTIMER_PRESCALER registers must first be set. 181/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 4.7.2 Register Definitions GPT +0000h Bit 15 14 Name EN MODE Type R/W R/W Reset 0 0 GPT1 Control register 13 12 11 10 GPTIMER1_CON 9 8 7 6 5 4 3 2 1 0 MODE This register controls GPT1 to count repeatedly (in a loop) or just one-shot. 0 One-shot mode is selected. 1 Auto-repeat mode is selected. EN This register controls GPT1 to start counting or to stop. 0 GPT1 is disabled. 1 GPT1 is enabled. GPT +0004h Bit Name Type Reset 15 14 GPT1 Time-Out Interval register 13 12 11 10 9 GPTIMER1_DAT 8 7 CNT [15:0] R/W FFFFh 6 5 4 3 2 1 0 CNT [15:0] Initial counting value. GPT1 counts down from GPTIMER1_DAT. When GPT1 counts down to zero, a GPT1 interrupt is generated. GPT +0008h Bit 15 14 Name EN MODE Type R/W R/W Reset 0 0 GPT2 Control register 13 12 11 10 GPTIMER2_CON 9 8 7 6 5 4 3 2 1 0 MODE This register controls GPT2 to count repeatedly (in a loop) or just one-shot. 0 One-shot mode is selected 1 Auto-repeat mode is selected EN This register controls GPT2 to start counting or to stop. 0 GPT2 is disabled. 1 GPT2 is enabled. GPT +000Ch Bit Name Type Reset 15 14 GPT2 Time-Out Interval register 13 12 11 10 9 GPTIMER2_DAT 8 7 CNT [15:0] R/W FFFFh 6 5 4 3 2 1 0 CNT [15:0] Initial counting value. GPT2 counts down from GPTIMER2_DAT. When GPT2 counts down to zero, a GPT2 interrupt is generated. GPT +0010h Bit Name Type 15 14 GPT Status register 13 12 11 10 GPTIMER_STA 9 8 182/599 7 6 5 4 3 2 1 0 GPT2 GPT1 RC RC MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 Reset 0 0 This register illustrates the gptimer timeout status. Each flag is set when the corresponding timer countdown completes, and can be cleared when the CPU reads the status register. GPT +0014h Bit Name Type Reset 15 14 GPTIMER1_PRES CALER GPT1 Prescaler register 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PRESCALER [2:0] R/W 100b PRESCALER This register controls the counting clock for gptimer1. 000 16384 Hz 001 8192 Hz 010 4096 Hz 011 2048 Hz 100 1024 Hz 101 512 Hz 110 256 Hz 111 128 Hz GPT +0018h Bit Name Type Reset 15 14 GPTIMER2_PRES CALER GPT2 Prescaler register 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PRESCALER [2:0] R/W 100b PRESCALER This register controls the counting clock for gptimer2. 000 16384 Hz 001 8192 Hz 010 4096 Hz 011 2048 Hz 100 1024 Hz 101 512 Hz 110 256 Hz 111 128 Hz GPT+001Ch 14 GPT3 Control register 13 12 11 10 GPTIMER3_CON Bit Name Type Reset 15 9 8 EN This register controls GPT3 to start counting or to stop. 0 GPT3 is disabled. 1 GPT3 is enabled. 183/599 7 6 5 4 3 2 1 0 EN R/W 0 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 GPT+0020h Bit Name Type Reset 15 GPT3 Time-Out Interval register 14 13 12 11 10 9 CNT [15:0] If EN=1, GPT3 is a free running timer . GPT+0024h Bit Name Type Reset 15 GPTIMER3_DAT 8 7 CNT[15:0] RO 0 6 5 4 13 12 11 10 2 1 0 Software reads this register for the countdown start value for GPT3. GPTIMER3_PRES CALER GPT3 Prescaler register 14 3 9 8 7 6 5 4 3 2 1 0 PRESCALER [2:0] R/W 100b PRESCALER This register controls the counting clock for gptimer3. 000 16384 Hz 001 8192 Hz 010 4096 Hz 011 2048 Hz 100 1024 Hz 101 512 Hz 110 256 Hz 111 128 Hz 4.8 4.8.1 UART General Description The baseband chipset houses three UARTs. baseband chipset and external devices. The UARTs provide full duplex serial communication channels between The UART has M16C450 and M16550A modes of operation, which are compatible with a range of standard software drivers. The extensions have been designed to be broadly software compatible with 16550A variants, but certain areas offer no consensus. In common with the M16550A, the UART supports word lengths from five to eight bits, an optional parity bit and one or two stop bits, and is fully programmable by an 8-bit CPU interface. A 16-bit programmable baud rate generator and an 8-bit scratch register are included, together with separate transmit and receive FIFOs. Eight modem control lines and a diagnostic loop-back mode are provided. The UART also includes two DMA handshake lines, used to indicate when the FIFOs are ready to transfer data to the CPU. Interrupts can be generated from any of the 10 sources. Note: The UART has been designed so that all internal operations are synchronized by the CLK signal. This synchronization results in minor timing differences between the UART and the industry standard 16550A device, which means that the core is not clock for clock identical to the original device. After a hardware reset, the UART is in M16C450 mode. Its FIFOs can be enabled and the UART can then enter 184/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 M16550A mode. The UART adds further functionality beyond M16550A mode. selected individually under software control. Each of the extended functions can be The UART provides more powerful enhancements than the industry-standard 16550: z Hardware flow control. This feature is very useful when the ISR latency is hard to predict and control in the embedded applications. The MCU is relieved of having to fetch the received data within a fixed amount of time. z Output of an IR-compatible electrical pulse with a width 3/16 of that of a regular bit period. Note: In order to enable any of the enhancements, the Enhanced Mode bit, EFR[4], must be set. If EFR[4] is not set, IER[7:5], FCR[5:4], ISR[5:4] and MCR[7:6] cannot be written. The Enhanced Mode bit ensures that the UART is backward compatible with software that has been written for 16C450 and 16550A devices. Figure 22 shows the block diagram of the UART device. Baud Rate Generator divisor baud clock TX FIFO APB BUS I/F APB Bus RX FIFO TX Machine uart_tx_data RX Machine uart_rx_data Modem Outputs Modem Control Modem Inputs Figure 22 Block Diagram of UART 4.8.2 Register Definitions n = 1, 2, 3; for uart1, uart2 and uart3 respectively. UARTn+0000h RX Buffer Register 14 13 12 11 10 UARTn_RBR Bit Name Type 15 9 8 7 6 5 4 3 RBR[7:0] RO RBR RX Buffer Register. Read-only register. The received data can be read by accessing this register. Modified when LCR[7] = 0. UARTn+0000h TX Holding Register Bit Name Type 15 14 13 12 11 10 2 1 0 UARTn_THR 9 8 185/599 7 6 5 4 3 THR[7:0] WO 2 1 0 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 THR TX Holding Register. Write-only register. The data to be transmitted is written to this register, and then sent to the PC via serial communication. Modified when LCR[7] = 0. UARTn+0004h Interrupt Enable Register Bit Name Type Reset 15 IER By storing a ‘1’ to a specific bit position, the interrupt associated with that bit is enabled. Otherwise, the interrupt is disabled. IER[3:0] are modified when LCR[7] = 0. IER[7:4] are modified when LCR[7] = 0 & EFR[4] = 1. Masks an interrupt that is generated when a rising edge is detected on the CTS modem control line. Note: This interrupt is only enabled when hardware flow control is enabled. 0 Unmask an interrupt that is generated when a rising edge is detected on the CTS modem control line. 1 Mask an interrupt that is generated when a rising edge is detected on the CTS modem control line. Masks an interrupt that is generated when a rising edge is detected on the RTS modem control line. Note: This interrupt is only enabled when hardware flow control is enabled. 0 Unmask an interrupt that is generated when a rising edge is detected on the RTS modem control line. 1 Mask an interrupt that is generated when a rising edge is detected on the RTS modem control line. Masks an interrupt that is generated when an XOFF character is received. Note: This interrupt is only enabled when software flow control is enabled. 0 Unmask an interrupt that is generated when an XOFF character is received. 1 Mask an interrupt that is generated when an XOFF character is received. When set ("1"), an interrupt is generated if DDCD, TERI, DDSR or DCTS (MSR[4:1]) becomes set. 0 No interrupt is generated if DDCD, TERI, DDSR or DCTS (MSR[4:1]) becomes set. 1 An interrupt is generated if DDCD, TERI, DDSR or DCTS (MSR[4:1]) becomes set. When set ("1"), an interrupt is generated if BI, FE, PE or OE (LSR[4:1]) becomes set. 0 No interrupt is generated if BI, FE, PE or OE (LSR[4:1]) becomes set. 1 An interrupt is generated if BI, FE, PE or OE (LSR[4:1]) becomes set. When set ("1"), an interrupt is generated if the TX Holding Register is empty or the contents of the TX FIFO have been reduced to its Trigger Level. 0 No interrupt is generated if the TX Holding Register is empty or the contents of the TX FIFO have been reduced to its Trigger Level. 1 An interrupt is generated if the TX Holding Register is empty or the contents of the TX FIFO have been reduced to its Trigger Level When set ("1"), an interrupt is generated if the RX Buffer contains data. 0 No interrupt is generated if the RX Buffer contains data. 1 An interrupt is generated if the RX Buffer contains data. CTSI RTSI XOFFI EDSSI ELSI ETBEI ERBFI 14 13 12 11 10 9 UARTn_IER 8 7 6 5 CTSI RTSI XOFFI 4 X 3 2 1 0 EDSSI ELSI ETBEI ERBFI R/W 0 UARTn+0008h Interrupt Identification Register Bit Name Type 15 14 13 12 11 10 9 8 UARTn_IIR 7 6 FIFOE 5 ID4 4 ID3 3 ID2 2 ID1 1 ID0 0 NINT RO 186/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 Reset IIR 0 0 0 0 0 0 0 1 Identify if there are pending interrupts; ID4 and ID3 are presented only when EFR[4] = 1. The following table gives the IIR[5:0] codes associated with the possible interrupts: IIR[5:0] Priority Level Interrupt 000001 No interrupt pending 000110 1 Line Status Interrupt 000100 2 RX Data Received 001100 2 RX Data Timeout 000010 3 TX Holding Register Empty 000000 4 Modem Status change 010000 5 Software Flow Control 100000 6 Hardware Flow Control Source BI, FE, PE or OE set in LSR RX Data received or RX Trigger Level reached. Timeout on character in RX FIFO. TX Holding Register empty or TX FIFO Trigger Level reached. DDCD, TERI, DDSR or DCTS set in MSR XOFF Character received CTS or RTS Rising Edge Table 17 The IIR[5:0] codes associated with the possible interrupts Line Status Interrupt: A RX Line Status Interrupt (IIR[5:0`] == 000110b) is generated if ELSI (IER[2]) is set and any of BI, FE, PE or OE (LSR[4:1]) becomes set. The interrupt is cleared by reading the Line Status Register. RX Data Received Interrupt: A RX Received interrupt (IER[5:0] == 000100b) is generated if EFRBI (IER[0]) is set and either RX Data is placed in the RX Buffer Register or the RX Trigger Level is reached. The interrupt is cleared by reading the RX Buffer Register or the RX FIFO (if enabled). RX Data Timeout Interrupt: When virtual FIFO mode is disabled, RX Data Timeout Interrupt is generated if all of the following apply: 1. FIFO contains at least one character; 2. The most recent character was received longer than four character periods ago (including all start, parity and stop bits); 3. The most recent CPU read of the FIFO was longer than four character periods ago. The timeout timer is restarted on receipt of a new byte from the RX Shift Register, or on a CPU read from the RX FIFO. The RX Data Timeout Interrupt is enabled by setting EFRBI (IER[0]) to 1, and is cleared by reading RX FIFO. When virtual FIFO mode is enabled, RX Data Timeout Interrupt is generated if all of the following apply: 1. FIFO is empty; 2. The most recent character was received longer than four character periods ago (including all start, parity and stop bits); 3. The most recent CPU read of the FIFO was longer than four character periods ago. The timeout timer is restarted on receipt of a new byte from the RX Shift Register. RX Holding Register Empty Interrupt: A TX Holding Register Empty Interrupt (IIR[5:0] = 000010b) is generated if ETRBI (IER[1]) is set and either the TX Holding Register or, if FIFOs are enabled, the TX FIFO becomes empty. The interrupt is cleared by writing to the TX Holding Register or TX FIFO if FIFO enabled. 187/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 Modem Status Change Interrupt: A Modem Status Change Interrupt (IIR[5:0] = 000000b) is generated if EDSSI (IER[3]) is set and either DDCD, TERI, DDSR or DCTS (MSR[3:0]) becomes set. The interrupt is cleared by reading the Modem Status Register. Software Flow Control Interrupt: A Software Flow Control Interrupt (IIR[5:0] = 010000b) is generated if Software Flow Control is enabled and XOFFI (IER[5]) becomes set, indicating that an XOFF character has been received. The interrupt is cleared by reading the Interrupt Identification Register. Hardware Flow Control Interrupt: A Hardware Flow Control Interrupt (IER[5:0] = 100000b) is generated if Hardware Flow Control is enabled and either RTSI (IER[6]) or CTSI (IER[7]) becomes set indicating that a rising edge has been detected on either the RTS/CTS Modem Control line. The interrupt is cleared by reading the Interrupt Identification Register. UARTn+0008h FIFO Control Register Bit Name Type 15 14 13 12 11 10 UARTn_FCR 9 8 7 6 5 4 3 2 1 0 RFTL1 RFTL0 TFTL1 TFTL0 DMA1 CLRT CLRR FIFOE WO FCR is used to control the trigger levels of the FIFOs, or flush the FIFOs. FCR[7:6] is modified when LCR != BFh FCR[5:4] is modified when LCR != BFh & EFR[4] = 1 FCR[4:0] is modified when LCR != BFh FCR[7:6] RX FIFO trigger threshold 0 1 1 6 2 12 3 RXTRIG FCR[5:4] TX FIFO trigger threshold 0 1 1 4 2 8 3 14 (FIFOSIZE - 2) DMA1 This bit determines the DMA mode, which the TXRDY and RXRDY pins support. TXRDY and RXRDY act to support single-byte transfers between the UART and memory (DMA mode 0) or multiple byte transfers (DMA mode1). Note that this bit has no effect unless the FIFOE bit is set as well 0 The device operates in DMA Mode 0. 1 The device operates in DMA Mode 1. TXRDY – mode0: Goes active (low) when the TX FIFO or the TX Holding Register is empty. Becomes inactive when a byte is written to the Transmit channel. TXRDY – mode1: Goes active (low) when there are no characters in the TX FIFO. Becomes inactive when the TX FIFO is full. RXRDY – mode0: Becomes active (low) when at least one character is in the RX FIFO or the RX Buffer Register is full. Becomes inactive when there are no more characters in the RX FIFO or RX Buffer register. RXRDY – mode1: Becomes active (low) when the RX FIFO Trigger Level is reached or an RX FIFO Character Timeout occurs. Goes inactive when the RX FIFO is empty. CLRT Clear Transmit FIFO. This bit is self-clearing. 0 Leave TX FIFO intact. FCR 188/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 1 Clear all the bytes in the TX FIFO. CLRR Clear Receive FIFO. This bit is self-clearing. 0 Leave RX FIFO intact. 1 Clear all the bytes in the RX FIFO. FIFOE FIFO Enabled. This bit must be set to 1 for any of the other bits in the registers to have any effect. 0 Disable both the RX and TX FIFOs. 1 Enable both the RX and TX FIFOs. UARTn+000Ch Line Control Register Bit Name Type Reset 15 14 13 12 11 10 UARTn_LCR 9 8 7 DLAB 6 SB 5 SP 0 0 0 4 3 EPS PEN R/W 0 0 2 1 0 STB WLS1 WLS0 0 0 0 Line Control Register. Determines characteristics of serial communication signals. Modified when LCR[7] = 0. DLAB Divisor Latch Access Bit. 0 The RX and TX Registers are read/written at Address 0 and the IER register is read/written at Address 4. 1 The Divisor Latch LS is read/written at Address 0 and the Divisor Latch MS is read/written at Address 4. SB Set Break 0 No effect 1 SOUT signal is forced into the “0” state. SP Stick Parity 0 No effect. 1 The Parity bit is forced into a defined state, depending on the states of EPS and PEN: If EPS=1 & PEN=1, the Parity bit is set and checked = 0. If EPS=0 & PEN=1, the Parity bit is set and checked = 1. EPS Even Parity Select 0 When EPS=0, an odd number of ones is sent and checked. 1 When EPS=1, an even number of ones is sent and checked. PEN Parity Enable 0 The Parity is neither transmitted nor checked. 1 The Parity is transmitted and checked. STB Number of STOP bits 0 One STOP bit is always added. 1 Two STOP bits are added after each character is sent; unless the character length is 5 when 1 STOP bit is added. WLS1, 0 Word Length Select. 0 5 bits 1 6 bits 2 7 bits 3 8 bits LCR UARTn+0010h Modem Control Register Bit 15 14 13 12 11 10 9 UARTn_MCR 8 189/599 7 6 5 4 3 2 1 0 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 XOFF IR STAT ENAB US LE Name Type Reset X LOOP OUT2 OUT1 RTS DTR R/W 0 0 0 0 0 0 0 0 Modem Control Register. Control interface signals of the UART. MCR[4:0] are modified when LCR[7] = 0, MCR[7:6] are modified when LCR[7] = 0 & EFR[4] = 1. XOFF Status This is a read-only bit. 0 When an XON character is received. 1 When an XOFF character is received.LOOP Loop-back control bit. 0 No loop-back is enabled. 1 Loop-back mode is enabled. OUT2 Controls the state of the output NOUT2, even in loop mode. 0 NOUT2=1. 1 NOUT2=0. OUT1 Controls the state of the output NOUT1, even in loop mode. 0 NOUT1=1. 1 NOUT1=0. RTS Controls the state of the output NRTS, even in loop mode. 0 NRTS=1. 1 NRTS=0. DTR Control the state of the output NDTR, even in loop mode. 0 NDTR=1. 1 NDTR=0. MCR UARTn+0014h Line Status Register Bit Name 15 14 13 12 11 10 UARTn_LSR 9 8 7 6 5 FIFOE TEMT THRE RR Type Reset 4 3 2 1 0 BI FE PE OE DR 0 0 0 0 R/W 0 1 1 0 Line Status Register. Modified when LCR[7] = 0. FIFOERR RX FIFO Error Indicator. 0 No PE, FE, BI set in the RX FIFO. 1 Set to 1 when there is at least one PE, FE or BI in the RX FIFO. TEMT TX Holding Register (or TX FIFO) and the TX Shift Register are empty. 0 Empty conditions below are not met. 1 If FIFOs are enabled, the bit is set whenever the TX FIFO and the TX Shift Register are empty. If FIFOs are disabled, the bit is set whenever TX Holding Register and TX Shift Register are empty. THRE Indicates if there is room for TX Holding Register or TX FIFO is reduced to its Trigger Level. 0 Reset whenever the contents of the TX FIFO are more than its Trigger Level (FIFOs are enabled), or whenever TX Holding Register is not empty(FIFOs are disabled). LSR 190/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 Set whenever the contents of the TX FIFO are reduced to its Trigger Level (FIFOs are enabled), or whenever TX Holding Register is empty and ready to accept new data (FIFOs are disabled). Break Interrupt. 0 Reset by the CPU reading this register 1 If the FIFOs are disabled, this bit is set whenever the SIN is held in the 0 state for more than one transmission time (START bit + DATA bits + PARITY + STOP bits). If the FIFOs are enabled, this error is associated with a corresponding character in the FIFO and is flagged when this byte is at the top of the FIFO. When a break occurs, only one zero character is loaded into the FIFO: the next character transfer is enabled when SIN goes into the marking state and receives the next valid start bit. Framing Error. 0 Reset by the CPU reading this register 1 If the FIFOs are disabled, this bit is set if the received data did not have a valid STOP bit. If the FIFOs are enabled, the state of this bit is revealed when the byte it refers to is the next to be read. Parity Error 0 Reset by the CPU reading this register 1 If the FIFOs are disabled, this bit is set if the received data did not have a valid parity bit. If the FIFOs are enabled, the state of this bit is revealed when the referred byte is the next to be read. Overrun Error. 0 Reset by the CPU reading this register. 1 If the FIFOs are disabled, this bit is set if the RX Buffer was not read by the CPU before new data from the RX Shift Register overwrote the previous contents. If the FIFOs are enabled, an overrun error occurs when the RX FIFO is full and the RX Shift Register becomes full. OE is set as soon as this happens. The character in the Shift Register is then overwritten, but not transferred to the FIFO. Data Ready. 0 Cleared by the CPU reading the RX Buffer or by reading all the FIFO bytes. 1 Set by the RX Buffer becoming full or by a byte being transferred into the FIFO. 1 BI FE PE OE DR UARTn+0018h Modem Status Register Bit Name Type Reset 15 14 13 12 Note: After a reset, D4-D7 are inputs. register. D0-D3 can be written to. 11 10 9 UARTn_MSR 8 7 DCD R/W Input 6 RI R/W Input 5 DSR R/W Input 4 3 2 1 0 CTS DDCD TERI DDSR DCTS R/W R/W R/W R/W R/W Input 0 0 0 0 A modem status interrupt can be cleared by writing ‘0’ or set by writing ‘1’ to this Modified when LCR[7] = 0. MSR DCD RI Modem Status Register Data Carry Detect. When Loop = "0", this value is the complement of the NDCD input signal. When Loop = "1", this value is equal to the OUT2 bit in the Modem Control Register. Ring Indicator. When Loop = "0", this value is the complement of the NRI input signal. 191/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 DSR When Loop = "1", this value is equal to the OUT1 bit in the Modem Control Register. Data Set Ready When Loop = "0", this value is the complement of the NDSR input signal. When Loop = "1", this value is equal to the DTR bit in the Modem Control Register. CTS Clear To Send. When Loop = "0", this value is the complement of the NCTS input signal. When Loop = "1", this value is equal to the RTS bit in the Modem Control Register. DDCD Delta Data Carry Detect. 0 The state of DCD has not changed since the Modem Status Register was last read 1 Set if the state of DCD has changed since the Modem Status Register was last read. TERI Trailing Edge Ring Indicator 0 The NRI input does not change since this register was last read. 1 Set if the NRI input changes from “0” to “1” since this register was last read. DDSR Delta Data Set Ready 0 Cleared if the state of DSR has not changed since this register was last read. 1 Set if the state of DSR has changed since this register was last read. DCTS Delta Clear To Send 0 Cleared if the state of CTS has not changed since this register was last read. 1 Set if the state of CTS has changed since this register was last read. UARTn+001Ch Scratch Register Bit Name Type 15 14 13 12 11 UARTn_SCR 10 9 8 7 6 5 4 3 SCR[7:0] R/W 2 1 0 A general purpose read/write register. After reset, its value is un-defined. Modified when LCR[7] = 0. UARTn+0000h Divisor Latch (LS) Bit Name Type Reset 15 14 13 12 11 10 UARTn_DLL 9 8 7 6 5 4 3 DLL[7:0] R/W 1 2 9 8 7 6 5 4 3 DLL[7:0] R/W 0 2 UARTn+0004h Divisor Latch (MS) Bit Name Type Reset 15 14 13 12 11 10 1 0 UARTn_DLM Note: DLL & DLM can only be updated if DLAB is set (“1”).. is constantly high. 1 0 Note too that division by 1 generates a BAUD signal that Modified when LCR[7] = 1. 192/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 The table below shows the divisor needed to generate a given baud rate from CLK inputs of 13, 26 MHz and 52 MHz. The effective clock enable generated is 16 x the required baud rate. BAUD 110 300 1200 2400 4800 9600 19200 38400 57600 115200 13MHz 7386 2708 677 338 169 85 42 21 14 6 26MHz 14773 5417 1354 677 339 169 85 42 28 14 52MHz 29545 10833 2708 1354 677 339 169 85 56 28 Table 18 Divisor needed to generate a given baud rate UARTn+0008h Enhanced Feature Register Bit 15 14 13 12 11 10 9 UARTn_EFR 8 Name Type Reset 7 6 5 4 AUTO AUTO ENAB D5 CTS RTS LE -E R/W R/W R/W R/W 0 0 0 0 3 2 1 0 SW FLOW CONT[3:0] R/W 0 *NOTE: Only when LCR=BF’h Auto CTS Enables hardware transmission flow control 0 Disabled. 1 Enabled. Auto RTS Enables hardware reception flow control 0 Disabled. 1 Enabled. Enable-E Enable enhancement features. 0 Disabled. 1 Enabled. CONT[3:0] Software flow control bits. 00xx No TX Flow Control 10xx Transmit XON1/XOFF1 as flow control bytes 01xx Transmit XON2/XOFF2 as flow control bytes 11xx Transmit XON1 & XON2 and XOFF1 & XOFF2 as flow control words xx00 No RX Flow Control xx10 Receive XON1/XOFF1 as flow control bytes xx01 Receive XON2/XOFF2 as flow control bytes xx11 Receive XON1 & XON2 and XOFF1 & XOFF2 as flow control words UARTn+0010h XON1 Bit 15 14 13 UARTn_XON1 12 11 10 9 8 193/599 7 6 5 4 3 2 1 0 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 Name Type Reset XON1[7:0] R/W 0 UARTn+0014h XON2 Bit Name Type Reset 15 14 13 UARTn_XON2 12 11 10 9 8 7 6 5 4 3 XON2[7:0] R/W 0 11 10 9 8 7 6 5 4 3 XOFF1[7:0] R/W 0 UARTn+0018h XOFF1 Bit Name Type Reset 15 14 13 12 15 14 13 12 1 0 UARTn_XOFF1 UARTn+001Ch XOFF2 Bit Name Type Reset 2 2 1 0 UARTn_XOFF2 11 10 9 8 7 6 5 4 3 XOFF2[7:0] R/W 0 2 1 0 *Note: XON1, XON2, XOFF1, XOFF2 are valid only when LCR=BFh. UARTn_AUTOBAUD _EN UARTn+0020h AUTOBAUD_EN Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 Name Type Reset 1 0 AUTO _EN R/W 0 AUTOBAUD_EN Auto-baud enable signal 0 Auto-baud function disable 1 Auto-baud function enable UARTn+0024h HIGH SPEED UART Bit Name Type Reset 15 14 13 12 11 10 UARTn_HIGHSPEED 9 8 7 6 5 4 3 2 1 0 SPEED [1:0] R/W 0 SPEED UART sample counter base 0 based on 16*baud_pulse, baud_rate = system clock frequency/16/{DLH, DLL} 1 based on 8*baud_pulse, baud_rate = system clock frequency/8/{DLH, DLL} 2 based on 4*baud_pulse, baud_rate = system clock frequency/4/{DLH, DLL} 3 based on sampe_count * baud_pulse, baud_rate = system clock frequency / sampe_count 194/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 The table below shows the divisor needed to generate a given baud rate from CLK inputs of 13M Hz based on different HIGHSPEED value. BAUD HIGHSPEED = 0 HIGHSPEED = 1 HIGHSPEED = 2 110 7386 14773 29545 300 2708 7386 14773 1200 677 2708 7386 2400 338 677 2708 4800 169 338 677 9600 85 169 338 19200 42 85 169 38400 21 42 85 57600 14 21 42 115200 7 14 21 230400 * 7 14 460800 * * 7 921600 * * * Table 19 Divisor needed to generate a given baud rate from 13MHz based on different HIGHSPEED value The table below shows the divisor needed to generate a given baud rate from CLK inputs of 26 MHz based on different HIGHSPEED value. BAUD HIGHSPEED = 0 HIGHSPEED = 1 HIGHSPEED = 2 110 14773 29545 59091 300 5417 14773 29545 1200 1354 5417 14773 2400 677 1354 5417 4800 339 677 1354 9600 169 339 667 19200 85 169 339 38400 42 85 169 57600 28 42 85 115200 14 28 42 230400 7 14 28 460800 * 7 14 921600 * * 7 Table 20 Divisor needed to generate a given baud rate from 26 MHz based on different HIGHSPEED value 195/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 The table below shows the divisor needed to generate a given baud rate from CLK inputs of 52MHz based on different HIGHSPEED value. BAUD HIGHSPEED = 0 HIGHSPEED = 1 HIGHSPEED = 2 110 29545 59091 118182 300 10833 29545 59091 1200 2708 10833 29545 2400 1354 2708 10833 4800 677 1354 2708 9600 339 677 1354 19200 169 339 677 38400 85 169 339 57600 56 85 169 115200 28 56 85 230400 14 28 56 460800 7 14 28 921600 * 7 14 Table 21 Divisor needed to generate a given baud rate from 52 MHz based on different HIGHSPEED value UARTn_SAMPLE_COUN T UARTn+0028h SAMPLE_COUNT Bit Name Type Reset 15 14 13 12 11 10 9 8 7 6 5 4 3 2 SAMPLECOUNT [7:0] R/W 0 1 0 When HIGHSPEED=3, the sample_count is the threshold value for UART sample counter (sample_num). Count from 0 to sample_count. For example, this register shall be set to 13 when you want to diveded by 14. UARTn+002Ch SAMPLE_POINT Bit Name Type Reset 15 14 13 12 11 UARTn_SAMPLE_POINT 10 9 8 7 6 5 4 3 2 SAMPLEPOINT [7:0] R/W Ffh 1 0 When HIGHSPEED=3, UART gets the input data when sample_count=sample_num. e.g. system clock = 13MHz, 921600 = 13000000 / 14 sample_count = 14 and sample point = 7 (sample the central point to decrease the inaccuracy) The SAMPLE_POINT is usually (SAMPLE_COUNT/2). UARTn_AUTOBAUD_RE G UARTn+0030h AUTOBAUD_REG Bit 15 14 13 12 11 10 9 8 196/599 7 6 5 4 3 2 1 0 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 Name Type Reset BAUD_STAT[3:0] RO 0 BAUDRATE[3:0] RO 0 BAUD_RATE Autobaud baud rate 0 115200 1 57600 2 38400 3 19200 4 9600 5 4800 6 2400 7 1200 8 300 9 110 BAUDSTAT Autobaud format 0 Autobaud is detecting 1 AT_7N1 2 AT_7O1 3 AT_7E1 4 AT_8N1 5 AT_8O1 6 AT_8E1 7 at_7N1 8 at_7E1 9 at_7O1 10 at_8N1 11 at_8E1 12 at_8O1 13 Autobaud detection fails UARTn+0034h Rate Fix Address Bit 15 14 13 12 11 10 UARTn_RATEFIX_AD 9 8 7 6 5 Name Type Reset RATE_FIX When you set "rate_fix"(34H[0]), you can transmit and receive data only if 4 3 2 1 0 AUTO REST FREQ BAUD RXTE_ RICT _SEL _RAT FIX E_FIX R/W R/W R/W R/W 0 0 0 0 1) the f13m_en is enable and the freq_sel (34H[2]) is set to 1, or 2) the f26m_en is enable and the freq_sel (34H[2]) is set to 0. AUTOBAUD_RATE_FIX When you set "autobaud_rate_fix"(34H[1]), you can tx/rx the autobaud packet only if 1) the f13m_en is enable and the freq_sel (34H[2]) is set to 1, or 2) the f26m_en is enable and the freq_sel (34H[2]) is set to 0. 197/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 FREQ_SEL 0 Select f26m_en for rate_fix and autobaud_rate_fix 1 Select f13m_en for rate_fix and autobaud_rate_fix The "restrict" (34H[3]) is used to set a more condition for the autobaud fsm starting point RESTRICT UARTn_AUTOBAUDSAM PLE UARTn+0038h AUTOBAUDSAMPLE Bit Name Type Reset 15 14 13 12 11 10 9 8 7 6 R/W 5 4 3 2 1 AUTOBAUDSAMPLE R/W R/W R/W R/W R/W dh 0 R/W Since the system clock may change, autobaud sample duration should change as system clock changes. When system clock = 13MHz, autobaudsample = 6; when system clock = 26MHz, autobaudsample = 13. UARTn+003Ch Guard time added register Bit 15 14 13 12 11 10 9 UARTn_GUARD 8 7 6 5 4 3 Name GUARD_ Type Reset R/W 0 2 1 0 GUARD_CNT[3:0] EN R/W 0 R/W 0 R/W 0 R/W 0 GUARD_CNT Guard interval count value. Guard interval = (1/(system clock / div_step / div )) * GUARD_CNT. GUARD_EN Guard interval add enable signal. 0 No guard interval added. 1 Add guard interval after stop bit. UARTn+0040h Escape character register Bit Name Type Reset 15 14 13 12 11 10 9 UARTn_ESCAPE_DAT 8 7 6 5 4 3 2 ESCAPE_DAT[7:0] WO FFh 1 0 ESCAPE_DAT Escape character added before software flow control data and escape character, i.e. if tx data is xon (31h), with esc_en =1, uart transmits data as esc + CEh (~xon). UARTn+0044h Escape enable register Bit 15 14 13 12 11 10 9 UARTn_ESCAPE_EN 8 7 6 5 4 3 2 1 0 Name ESC_E N Type Reset R/W 0 ESC_EN 0 1 Add escape character in transmitter and remove escape character in receiver by UART. Do not deal with the escape character. Add escape character in transmitter and remove escape character in receiver. UARTn+0048h Sleep enable register Bit 15 14 13 12 11 10 UARTn_SLEEP_EN 9 8 198/599 7 6 5 4 3 2 1 0 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 SELL P_EN R/W 0 Name Type Reset SLEEP_EN For sleep mode issue 0 Do not deal with sleep mode indicate signal 1 To activate hardware flow control or software control according to software initial setting when chip enters sleep mode. Releasing hardware flow when chip wakes up; but for software control, uart sends xon when awaken and when FIFO does not reach threshold level. UARTn+004Ch Virtual FIFO enable register Bit 15 14 13 12 11 10 9 UARTn_VFIFO_EN 8 7 6 5 4 3 2 1 Name Type Reset 0 VFIFO _EN R/W 0 VFIFO_EN Virtual FIFO mechanism enable signal. 0 Disable VFIFO mode. 1 Enable VFIFO mode. When virtual mode is enabled, the flow control is based on the DMA threshold, and generates a timeout interrupt for DMA. UARTn_RXTRI_ AD UARTn+0050h Rx Trigger Address Bit Name Type Reset 15 14 13 12 11 RXTRIG 4.9 4.9.1 10 9 8 7 6 5 4 3 2 1 RXTRIG[3:0] R/W 0 0 When {rtm,rtl}=2’b11, The Rx FIFO threshold will be Rxtrig. IrDA Framer General Description IrDA framer is implemented to reduce the CPU loading for IrDA transmissions by performing all the physical level protocol framing in hardware. From a software perspective, the framer need only prepare and process the raw data for transmission and reception. Generic DMA is required to move the data between IrDA framer’s internal FIFO and software-designated memory. The IrDA framer supports IrDA SIR, MIR, and FIR modes of operation. SIR mode includes operation from 9600bps ~ 115200bps, MIR includes operation at 567000bps or 1152000bps, and FIR mode includes operation at 4Mbps. 199/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 4.9.2 Register Definitions IRDA+0000h TX BUF and RX BUF 14 15 BUF IrDA Framer transmit or receive data. A write to this register writes into the internal TX FIFO. A read from this register reads from the internal RX FIFO. IRDA+0004h Bit Name Type Reset 15 13 12 11 10 BUF Bit Name Type Reset 9 8 7 6 5 4 3 BUF[7:0] R/W 0 2 7 6 5 4 2 TX BUF and RX BUF clear signal 14 13 12 11 10 9 8 1 0 BUF_CLEAR 3 1 0 CLEAR R/W 0 CLEAR SIR mode only. When CLEAR=1, both the TX and RX FIFO are cleared. This is used primarily for debug purpose. Normal operation does not require this. This control signaled can only be issued under SIR mode. IRDA+0008h Bit Name Type Reset 15 Maximum Turn Around Time 14 13 12 11 10 9 8 7 6 MAX_T [13:0] R/W 3E80h 5 4 3 2 MAX_T The maximum time that a station can hold the P/F bit. This parameter along with the baud rate parameter dictates the maximum number of bytes that a station can transmit before passing the line to another station by transmitting a frame with the P/F bit. This parameter is used by one station to indicate the maximum time the other station can send before it must turn the link around. For baud rates less than 115200 kbps, 500 ms is the only valid value. The default value is 500 ms. IRDA+000Ch Bit Name Type Reset 15 14 Minimum Turn Around Time 13 12 11 10 9 MIN_T 8 7 MIN_T [15:0] R/W FDE8h 6 5 4 3 2 1 0 MIN_T Minimum turn around time, the default value is 10 ms. The minimum turn around time parameter deals with the time needed for a receiver to recover following saturation by transmission from the same device. This parameter corresponds to the required time delay between the last byte of the last frame sent by a station and the point at which it is ready to receive the first byte of a frame from another station, i.e. the latency for a transmit to complete and be ready to receive. IRDA+0010h Bit Name 15 14 Number of additional BOFs prefixed to the beginning of a frame 13 12 11 10 9 8 7 TYPE 200/599 6 5 4 3 2 BOFS [6:0] BOFS 1 0 MediaTek Inc. Confidential 1 MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 Type Reset R/W 0 R/W 1011b BOFs For SIR mode: the additional BOFs parameter indicates the number of additional flags needed at the beginning of every frame. The main purpose for the additional BOFs is to provide a delay at the beginning of each frame for devices with a long interrupt latency. For MIR mode: This parameter indicates the number of double STA’s to transmit in the beginning. This value should be set to 0 (for default 2 STA’s) for MIR mode, unless more are required. For FIR mode: This parameter has no effect. TYPE SIR mode only. Additional BOFs type. 1 BOF = C0h 0 BOF = FFh IRDA+0014h 14 Baud rate divisor Bit Name Type Reset 15 DIV Transmit or receive rate divider. Rate = System clock frequency / DIV/ 16. The default value is 55h when in contention mode. This divisor is also used to determine the RX FIFO timeout threshold. IRDA+0018h Bit Name Type Reset 15 14 TX_FRAME_SIZE IRDA+001Ch Bit Name Type Reset 15 14 13 12 11 10 DIV 9 8 7 DIV[15:0] R/W 55h Bit 15 14 5 4 3 13 12 11 10 2 1 0 TX_FRAME_SIZ E Transmit frame size 9 8 7 6 5 4 TX_FRAME_SIZE[11:0] R/W 40h 3 2 1 0 Transmit frame size; the default value is 64 when in contention mode. RX_FRAME1_SI ZE Receiving frame1 size 13 12 11 10 9 8 RX_FRAME1_SIZE Reports the number of byte received. IRDA+0020h 6 7 6 5 4 RX_FRAME1_SIZE[11:0] RO 0 3 2 12 11 10 9 0 Includes only the A+C+I fields. Transmit abort indication 13 1 ABORT 8 Name Type Reset 7 6 5 4 3 2 1 0 ABOR T R/W 0 ABORT SIR mode only. When set 1, the framer transmits an abort sequence and closes the frame without an FCS field or an ending flag. Note: Tx abort can be achieved in MIR and FIR by simply disabling the tx_en signal. 201/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 IRDA+0024h Bit 15 IrDA framer transmit enable signal 14 13 12 11 10 9 8 7 6 5 4 3 Name Type Reset R/W 0 TX_EN Transmit enable. MODE SIR mode only. Modulation type selection. 0 3/16 modulation 1 1.61us TXINVERT Invert the transmit signal. 0 Transmit signal is not inverted. 1 Transmit signal is inverted. TX_ONE: Controls the transmit enable signal is one or not. 0 tx_en is not de-asserted until software programs a so. 1 tx_en is de-asserted (i.e. transmit disabled) automatically after one frame has been sent. IRDA+0028h Bit 15 14 IrDA framer receive enable signal 13 12 11 10 9 8 7 RX_EN 6 5 4 3 2 1 0 RX_E N R/W R/W 0 0 RX_ON RXINVE E RT Name Type Reset R/W 0 RX_EN Receive enable. RXINVERT Invert the receive signal. 0 Receive signal is not inverted. 1 Receive signal is inverted. RX_ONE Disable receive when get one frame. 0 rx_en is not de-asserted until software programs so. 1 rx_en is de-asserted (i.e. transmit disabled) automatically after one frame has been sent. IRDA+002Ch Bit Name Type Reset 2 TXINVER TX_ONE T 15 14 FIFO trigger level indication 13 12 11 10 9 8 TRIGGER 7 6 5 4 3 2 RX_TRIG[ R/W 0 1 0 TX_TRIG R/W 0 TX_TRIG TX FIFO interrupt trigger threshold. When the amount of data in the TX FIFO is less than the specified amount, dma req is asserted. (When TX_TRIG = 03, dma req is always asserted as long as FIFO is not full.) 00 0 byte 01 1 byte 02 8 byte 03 16 byte RX_TRIG RX FIFO interrupt trigger threshold. When the amount of data in RX FIFO is above the specified amount, dma req is asserted. 00 1 byte 202/599 MediaTek Inc. Confidential R/W 0 1 MODE R/W 0 MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 01 2 byte 02 3 byte IRDA+0030h Bit Name Type Reset 15 14 IRQ enable signal 13 IRQ_ENABLE 12 11 10 9 8 7 6 5 4 3 2 1 0 THRES FIFOTI 2NDR MAXTI MINTI RXCO TXCO ERRO RXTHR TXTHR RXRES TXABO RXABO HTIME MEOU X_CO MEOU MEOU MPLET MPLET R ES ES TART RT RT E E T T MP OUT T R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 0 0 0 0 TXRES Transmit data reaches the threshold level. (For debug only. Should be set to 0.) 0 No interrupt is generated. 1 Interrupt is generated when transmit FIFO size reaches threshold. RXRES Receive data reaches the threshold level. (For debug only. Should be set to 0.) 0 No interrupt is generated. 1 Interrupt is generated when receive FIFO size reaches threshold. ERROR Error status interrupt enable. 0 No interrupt is generated. 1 Interrupt is generated when one of the error statuses occurs. TXCOMPLETE Transmit one frame completely. 0 No interrupt is generated. 1 Interrupt is generated when transmitting one frame completely. RXCOMPLETE Receive one frame completely. 0 No interrupt is generated. 1 Interrupt is generated when receiving one frame completely. MINTIMEOUT Minimum time timeout. 0 No interrupt is generated. 1 Interrupt is generated when minimum timer is timed out. MAXTIMEOUT Maximum time timeout. 0 No interrupt is generated. 1 Interrupt is generated when maximum timer is timed out. RXABORT Receiving aborting frame. 0 No interrupt is generated. 1 Interrupt is generated when receiving aborting frame. TXABORT SIR mode only. Transmitting aborting frame. 0 No interrupt is generated. 1 Interrupt is generated when transmitting aborting frame. FIFOTIMEOUT FIFO timeout. 0 No interrupt is generated. 1 Interrupt is generated when FIFO timeout. THRESHTIMEOUT Threshold time timeout. 0 No interrupt is generated. 1 Interrupt is generated when threshold timer is timed out. RXRESTART SIR mode only. Receiving a new frame before one frame is received completely. 0 No interrupt is generated. 203/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 1 Interrupt is generated when receiving a new frame before one frame is received completely. 2NDRX_COMP Receiving second frame and get P/F bit. 0 No interrupt is generated. 1 Interrupt is generated when receiving second frame and get P/F bit completely. IRDA+0034h Bit 15 14 Interrupt Status 13 Name Type Reset IRQ_STA 12 11 10 9 THRES FIFOTI 2NDR RXRES HTIME MEOU X_CO TART OUT T MP RC RC RC RC 0 0 0 0 8 7 6 5 4 3 2 1 0 MAXTI MINTI RXCO TXCO TXABO RXABO ERRO RXTRE TXTRE MEOU MEOU MPLET MPLET RT RT R S S T T E E RC 0 RC 0 RC 0 RC 0 RC 0 RC 0 RC 0 RC 0 RC 0 TXFIFO Transmit FIFO reaches threshold. (For debug only. Not recommended for normal usage.) RXFIFO Receive FIFO reaches threshold. (For debug only. Not recommended for normal usage.) ERROR Generated when any of status in Error Status register occurs. Once the source of an interrupt is determined to be caused by an error (bit 2), the error status register should be read. Once read, both the error status register and the interrupt source are read-cleared. If the error status register indicates either a frame 1 or frame 2 error, the corresponding frame status register should be read. TXCOMPLETE Transmitting one frame completely. RXCOMPLETE Receiving one frame completely. MINTIMEOUT Minimum turn around time timeout. MAXTIMEOUT Maximum turn around time timeout. RXABORT Receiving aborting frame. TXABORT Transmitting aborting frame. FIFOTIMEOUT FIFO is timeout. THRESHTIMEOUT Threshold time timeout. RXRESTART Receiving a new frame before one frame is received completely. 2NDRX_COMP Receiving second frame and get P/F bit completely. IRDA+0038h Bit 15 14 ERROR STATUS register 13 12 11 10 9 ERR_STATUS 8 7 6 5 4 3 2 1 0 TX FIFO FRAME FRAME RESER RESER OVER RXSIZ UNDERR 2 DATA 1 DATA RUN E VED2 VED UN ERR ERR Name Type Reset R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 RXSIZE Receive frame size error. OVERRUN Frame overrun. RESERVED Reserved for future use. RESERVED2 Reserved for future use. FRAME1 DATA ERR Indicates that an error condition occurred in RX frame1. Must check the RX frame1 status. FRAME2 DATA ERR Indicates that an error condition occurred in RX frame2. Must check the RX frame2 status. TX FIFO UNDERRUN MIR and FIR mode only. TX FIFO underrun has occurred. Data transmission is aborted. Software must reset the tx_en signal. 204/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 IRDA+003Ch Bit 15 14 Transceiver power on/off control. Transceiver mode select. 13 12 11 10 9 8 7 6 5 4 TRANSCEIVER_ PDN 3 Name 2 1 0 TXCVR TX TRANS_ CONFIG MANUAL Type Reset R/W 0 R/W 0 PDN R/W 0 TRANSCEIVER_PDN Used for power on/off control for external IrDA transceiver. TX_MANUAL When txcvr config is set to 1, this bit can be used to select the operation mode of the external IrDA transceiver (some transceivers require selection between high speed and low speed operating modes), by software programming the desired sequence to transmit through the irda_txd pin. TXCVR CONFIG 0 Irda_txd comes from core logic. 1 Irda_txd depends on tx_manual value. IRDA+0040h Bit Name Type Reset 15 14 RX_FRAME_MA X Maximum number of receiving frame size 13 12 11 10 9 8 7 6 5 4 MAX_RX_FRAME_SIZE_ R/W 0 3 2 1 0 RX_FRAME_MAX Receive frame I field max size, when actual receiving frame size is larger than rx_frame_max, RXSIZE is asserted. The maximum allowed I field size is 2048. IRDA+0044h Bit Name Type Reset 15 14 Threshold Time 13 12 11 THRESH_T 10 9 8 7 6 DISCONNECT_TIME[15:0] R/W bb8h 5 4 3 2 1 0 THRESHOLD TIME Threshold time; used to control the time a station waits without receiving a valid frame before disconnecting the link. Associated with this is the time a station waits without receiving a valid frame before sending a status indication to the service user layer. IRDA+0048h Bit 15 14 COUNT_ENABL E Counter enable signal 13 12 11 10 9 8 7 6 5 4 3 2 Name THRESH Type Reset R/W 0 _EN COUNT_ENABLE IRDA+004Ch Bit 15 14 1 0 MIN_E MAX_E N N R/W 0 R/W 0 Counter enable signals. Indication of system clock rate 13 12 11 10 9 8 Name 205/599 CLOCK_RATE 7 6 5 4 3 2 1 0 CLOCK_RAT E MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 Type Reset R/W 0 CLOCK_RATE SIR mode only Indication of the system clock rate. 0 26 MHz 1 52 MHz 2 13 MHz IRDA+0050h Bit 15 System Clock Rate Fix 14 13 12 11 10 RATE_FIX 9 8 7 6 5 4 3 2 1 0 MIR CRC SIR RATE_F TIMING REPOR FRAMIN IX TUNE T G SET Name Type Reset R/W 0 R/W 0 R/W 0 R/W 0 RATE_FIX SIR mode only Fix the IrDA framer sample base clock rate as 13 MHz. 0 Clock rate based on clock_rate selection. 1 Clock rate fixed at 13 MHz. SIR FRAMING SET SIR mode only. Framing error check condition. 0 Ignore the STOP bit of the last byte of a frame. 1 Check the STOP bit of the last byte of a frame. CRC REPORT When set to 1, CRC error is reported via error status register and error interrupt. MIR TIMING TUNE MIR mode only. For some transceivers, in MIR 0.576mbps mode, the RX output pulse does not conform to IRDA specification. Therefore, this option is used to detect the RX output from those transceivers correctly. 0 For transceivers that conform to spec. 1 For transceivers that do not conform to spec, and the RX output pulse is half of that specified. IRDA+0054h Bit 15 RX Frame1 Status 14 13 12 11 FRAME1_S 10 9 8 7 6 5 FIR STO FIR 4PPM ERR ERR Name Type Reset R/W 0 R/W 0 4 MIR HDLC ERR R/W 0 3 UNKNOW_ PF_DETEC ERROR T R/W 0 R/W 0 FRAME_ERROR SIR mode only. Framing error, i.e. STOP bit = 0. 0 No framing error 1 Framing error occurred CRC_FAIL CRC check fail 2 CRC check successfully 3 CRC check fail PF_DETECT P/F bit detect 0 Not a P/F bit frame 1 Detected P/F bit in this frame UNKNOWN_ERROR SIR mode only. Receiving error data, i.e. escape character is followed by a character that is not an ESC, BOF, or EOF character. 0 Data received correctly. 206/599 2 MediaTek Inc. Confidential 1 CRC_FAI R/W 0 MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 1 Unknown error occurred. MIR HDLC ERR MIR mode only. MIR HDLC encoding error 0 No error 1 Error FIR 4PPM ERR FIR mode only. FIR 4ppm encoding error 0 No error 1 Error FIR STO ERR FIR mode only. FIR STO sequence error 0 No error 1 Error IRDA+0058h Bit 15 14 FRAME2_STAT US RX Frame2 Status 13 12 11 10 9 8 7 6 5 FIR FIR STO 4PPM ERR ERR Name Type Reset R/W 0 R/W 0 4 3 2 1 0 MIR UNKNOW PF_DETE CRC_FAI FRAME_ HDLC _ERROR CT L ERROR ERR R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 FRAME_ERROR SIR mode only. Framing error, i.e. STOP bit = 0 0 No framing error. 1 Framing error occurred. CRC_FAIL CRC check fail. 0 CRC check successfully. 1 CRC check fail. PF_DETECT P/F bit detect. 0 Not a P/F bit frame. 1 Detected P/F bit in this frame. UNKNOWN_ERROR SIR mode only. Receiving error data, i.e. escape character is followed by a character that is not an ESC, BOF, or EOF character. 0 Data receiving correctly. 1 Unknown error occurred. MIR HDLC ERR MIR mode only. MIR HDLC encoding error. 0 No error 1 Error FIR 4PPM ERR FIR mode only.FIR 4ppm encoding error 0 No error 1 Error FIR STO ERR FIR mode only.FIR STO sequence error 0 No error 1 Error IRDA+005Ch Bit 15 14 RX_FRAME2_SI ZE Receiving frame2 size 13 12 11 10 9 8 207/599 7 6 5 4 3 2 1 0 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 Name Type Reset RX_FRAME2_SIZE[11:0] RO 0 RX_FRAME2_SIZE Reports the number of byte received. IRDA+0060h Bit Name Type Reset 15 Irda Mode Select 14 13 12 IRDA_ 11 10 9 8 7 6 5 4 3 2 MIR SPEED R/W 0 IRDA MODE Selects the IrDA operating mode. receiving. 00 IR mode 01 MIR mode 10 FIR mode MIR SPEED Select the MIR speed. 0 0.576 Mbps 1 1.152 Mbps IRDA+0064h Bit Includes only the A+C+I fields. 15 14 NOTE: this mode selection cannot be issued while transmitting or Fifo Status 13 12 FIFO_STAT 11 10 9 8 7 6 5 4 3 RX FIFO TX FIFO HOLD WR FULL Name Type Reset RO 0 RO 0 2 TX FIFO RD EMPTY RO 1 1 RX FIFO WR FULL RO 0 0 RX FIFO RD EMPTY RO 1 This register indicates the real time FIFO status, for monitoring purposes. 4.10 4.10.1 Real Time Clock General Description The Real Time Clock (RTC) module provides time and data information. The clock is based on a 32.768KHz oscillator with an independent power supply. When the mobile handset is powered off, a dedicated regulator supplies the RTC block. If the main battery is not present, a backup supply such as a small mercury cell battery or a large capacitor is used. In addition to providing timing data, an alarm interrupt is generated and can be used to power up the baseband core via the BBWAKEUP pin. Regulator interrupts corresponding to seconds, minutes, hours and days can be generated whenever the time counter value reaches a maximum value (e.g., 59 for seconds and minutes, 23 for hours, etc.). The year span is supported up to 2127. The maximum day-of-month values, which depend on the leap year condition, are stored in the RTC block. 208/599 MediaTek Inc. Confidential 1 IRDA R MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 4.10.2 Register Definitions RTC+0000h Bit 15 Baseband power up 14 13 12 11 Name KEY_BBPU Type WO 10 RTC_BBPU 9 8 7 6 5 4 3 2 1 0 DBIN CBUS RELOA CLRPK WRITE_E PWRE AUTO BBPU N G Y D Y N RO RO WO WO R/W R/W R/W R/W A bus write is acceptable only when KEY_BBPU=0x43. DBING This bit indicates RTC is still de-bouncing. CBUSY The read/write channels between RTC / Core is busy. This bit indicates high after software program sequence to anyone of RTC data registers and enable the transfer by RTC_WRTGR=1. By the way, it is high after the reset from low to high because RTC reload process. RELOAD Reload the values from RTC domain to Core domain. Generally speaking, RTC will reload synchronize the data from RTC to core when reset from 0 to 1. This bit can be treated as debug bit. CLRPKY Clear powerkey1 and powerkey2 at the same time. In some cases, software may clear powerkey1 & powerkey2. The BBWAKEUP depends on the matching specific patterns of powerkey1 and powerkey2. If any one of powerkey1 or powerkey2 or BBPU is cleared, BBWAKEUP goes low immediately. Software can’t program the other control bits without power. By program RTC_BBPU with CLRPKY=1 and BBPU=0 condition, RTC can clear powerkey1, powerkey2 and BBPU at the same moment. AUTO Controls if BBWAKEUP is automatically in the low state when SYSRST# transitions from high to low. 0 BBWAKEUP is not automatically in the low state when SYSRST# transitions from high to low. 1 BBWAKEUP is automatically in the low state when SYSRST# transitions from high to low. BBPU Controls the power of PMIC. If powerkey1=A357h and powerkey2=67D2h, PMIC takes on the value programmed by software; otherwise PMIC is low. 0 Power down 1 Power on WRITE_EN When WRITE_EN is write 0 by the MCU, the RTC programing interface is disabled immediately (MCU can't program RTC). After the debounce counter is time-out, the interface enabled again (MCU can program RTC). The debounce counter time-out period is decided by RTC_PDN1. Note that the WRITE_EN value read out is meaningless. The hardware only care about the "write-0 action" to WRITE_EN control bit. When WRITE_EN==0, avoid to "read out RTC_BBPU, AND/OR something and write back", like this -> *RTC_BBPU=*RTC_BBPU|RTC_BBPU_KEY|0x1. This would disable RTC write interface for a while and hard to debug. PWREN 0 RTC alarm has no action on power switch. 1 When an RTC alarm occurs, BBPU is set to 1 and the system powers on by RTC alarm wakeup. KEY_BBPU RTC+0004h Bit 15 RTC IRQ status 14 13 12 11 RTC_IRQ_STA 10 9 8 7 6 5 4 3 Name Type 2 1 0 TCST ALST A A R/C R/C ALSTA This register indicates the IRQ status and whether or not the alarm condition has been met. 0 No IRQ occurred; the alarm condition has not been met. 209/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 1 IRQ occurred; the alarm condition has been met. TCSTA This register indicates the IRQ status and whether or not the tick condition has been met. 0 No IRQ occurred; the tick condition has not been met. 1 IRQ occurred; the tick condition has been met. RTC+0008h Bit 15 RTC IRQ enable 14 13 12 11 RTC_IRQ_EN 10 9 8 7 6 5 4 3 2 Name ONESHO Type R/W T 1 0 TC_E AL_E N N R/W R/W The function is only active when RTC_POWERKEY1 & RTC_POWERKEY2 match the correct values. ONESHOT Controls automatic reset of AL_EN and TC_EN. AL_EN This register enables the control bit for IRQ generation if the alarm condition has been met. 0 Disable IRQ generations. 1 Enable the alarm time match interrupt. Clear the interrupt when ONESHOT is high upon generation of the corresponding IRQ. TC_EN This register enables the control bit for IRQ generation if the tick condition has been met. 0 Disable IRQ generations. 1 Enable the tick time match interrupt. Clear the interrupt when ONESHOT is high upon generation of the corresponding IRQ. RTC+000Ch Bit 15 14 Counter increment IRQ enable 13 12 11 10 9 8 RTC_CII_EN 7 6 5 4 3 2 1 0 YEACI MTHC DOW DOMC HOUC SECC MINCII I II CII II II II R/W R/W R/W R/W R/W R/W R/W R/W 1/8SEC 1/4SEC 1/2SEC CII CII CII Name Type R/W R/W This register activates or de-activates the IRQ generation when the TC counter reaches its maximum value. SECCII Set this bit to 1 to activate the IRQ at each second update. MINCII Set the bit to 1 to activate the IRQ at each minute update. HOUCII Set the bit to 1 to activate the IRQ at each hour update. DOMCII Set the bit to 1 to activate the IRQ at each day-of-month update. DOWCII Set the bit to 1 to activate the IRQ at each day-of-week update. MTHCII Set the bit to 1 to activate the IRQ at each month update. YEACII Set the bit to 1 to activate the IRQ at each year update. 1/2SECCII Set the bit to 1 to activate the IRQ at each one-half of a second update. 1/4SECCII Set the bit to 1 to activate the IRQ at each one-fourth of a second update. 1/8SECCII Set the bit to 1 to activate the IRQ at each one-eighth of a second update. RTC+0010h Bit 15 RTC alarm mask 14 13 12 11 RTC_AL_MASK 10 9 8 7 6 5 4 3 2 1 0 YEA_M MTH_M DOW_M DOM_M HOU_M MIN_MS SEC_M SK SK SK SK SK K SK Name Type R/W 210/599 R/W R/W R/W R/W R/W R/W MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 The alarm condition for alarm IRQ generation depends on whether or not the corresponding bit in this register is masked. Warning: If you set all bits 1 in RTC_AL_MASK (i.e. RTC_AL_MASK=0x7f) and PWREN=1 in RTC_BBPU, it means alarm comes EVERY SECOND, not disabled. SEC_MSK 0 Condition (RTC_TC_SEC = RTC_AL_SEC) is checked to generate the alarm signal. 1 Condition (RTC_TC_SEC = RTC_AL_SEC) is masked, i.e. the value of RTC_TC_SEC does not affect the alarm IRQ generation. MIN_MSK 0 Condition (RTC_TC_MIN = RTC_AL_MIN) is checked to generate the alarm signal. 1 Condition (RTC_TC_MIN = RTC_AL_MIN) is masked, i.e. the value of RTC_TC_MIN does not affect the alarm IRQ generation. HOU_MSK 0 Condition (RTC_TC_HOU = RTC_AL_HOU) is checked to generate the alarm signal. 1 Condition (RTC_TC_HOU = RTC_AL_HOU) is masked, i.e. the value of RTC_TC_HOU does not affect the alarm IRQ generation. DOM_MSK 0 Condition (RTC_TC_DOM = RTC_AL_DOM) is checked to generate the alarm signal. 1 Condition (RTC_TC_DOM = RTC_AL_DOM) is masked, i.e. the value of RTC_TC_DOM does not affect the alarm IRQ generation. DOW_MSK 0 Condition (RTC_TC_DOW = RTC_AL_DOW) is checked to generate the alarm signal. 1 Condition (RTC_TC_DOW = RTC_AL_DOW) is masked, i.e. the value of RTC_TC_DOW does not affect the alarm IRQ generation. MTH_MSK 0 Condition (RTC_TC_MTH = RTC_AL_MTH) is checked to generate the alarm signal. 1 Condition (RTC_TC_MTH = RTC_AL_MTH) is masked, i.e. the value of RTC_TC_MTH does not affect the alarm IRQ generation. YEA_MSK 0 Condition (RTC_TC_YEA = RTC_AL_YEA) is checked to generate the alarm signal. 1 Condition (RTC_TC_YEA = RTC_AL_YEA) is masked, i.e. the value of RTC_TC_YEA does not affect the alarm IRQ generation. RTC+0014h Bit Name Type 15 TC_SECOND RTC seconds time counter register 14 15 TC_MINUTE 12 11 10 9 8 7 6 5 4 3 2 TC_SECOND R/W 1 0 The second initial value for the time counter. The range of its value is: 0-59. RTC+0018h Bit Name Type 13 RTC_TC_SEC RTC minutes time counter register 14 13 12 11 10 9 8 7 RTC_TC_MIN 6 5 4 3 2 TC_MINUTE R/W 1 0 The minute initial value for the time counter. The range of its value is: 0-59. 211/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 RTC+001Ch Bit Name Type 15 RTC hours time counter register 14 13 12 11 10 9 8 RTC_TC_HOU 7 6 5 4 3 2 1 TC_HOUR R/W 0 TC_HOUR The hour initial value for the time counter. The range of its value is: 0-23. RTC+0x0020 Bit Name Type 15 TC_DOM RTC day-of-month time counter register 14 15 15 9 8 7 6 5 4 3 2 1 TC_DOM R/W 0 14 RTC+0x0030 AL_SECOND 11 10 9 8 7 6 5 4 3 2 1 0 TC_DOW R/W 13 12 11 10 9 8 RTC_TC_MTH 7 6 5 4 3 2 1 TC_MONTH R/W 0 RTC year time counter register 13 12 11 10 9 8 RTC_TC_YEA 7 6 5 4 3 2 AL_SECOND R/W 1 0 The year initial value for the time counter. The range of its value is: 0-127. (2000-2127) TC_YEAR 15 12 The month initial value for the time counter. The range of its value is: 1-12. RTC+0x002C 15 13 RTC_TC_DOW RTC month time counter register 14 TC_MONTH Bit Name Type 10 The day-of-week initial value for the time counter. The range of its value is: 1-7. RTC+0x0028 Bit Name Type 11 RTC day-of-week time counter register 14 TC_DOW Bit Name Type 12 The day-of-month initial value for the time counter. The day-of-month maximum value depends on the leap year condition, i.e. 2 LSB of year time counter are zeros. RTC+0x0024 Bit Name Type 13 RTC_TC_DOM RTC second alarm setting register 14 13 12 11 10 9 8 7 RTC_AL_SEC 6 5 4 3 2 AL_SECOND R/W 1 0 The second value of the alarm counter setting. The range of its value is: 0-59. 212/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 RTC+0x0034 Bit Name Type 15 RTC minute alarm setting register 14 RTC+0x0038 15 AL_HOUR 15 AL_DOM 14 15 14 AL_YEAR 6 5 4 3 2 AL_MINUTE R/W 1 0 13 12 11 10 9 8 RTC_AL_HOU 7 6 5 4 3 2 1 AL_HOUR R/W RTC day-of-month alarm setting register 13 12 11 10 9 0 The range of its value is: 0-23. 8 7 6 RTC_AL_DOM 5 4 3 13 12 11 10 9 8 7 6 2 1 AL_DOM R/W 0 RTC_AL_DOW 5 4 3 14 13 12 11 10 9 8 7 2 1 0 AL_DOW R/W The range of its value is: 1-7. RTC month alarm setting register RTC_AL_MTH 6 5 4 3 2 1 AL_MONTH R/W 0 The month value of the alarm counter setting. The range of its value is: 1-12. RTC+0x0048 15 7 The day-of-week value of the alarm counter setting. AL_MONTH Bit Name Type 8 RTC day-of-week alarm setting register 14 RTC+0x0044 15 9 The day-of-month value of the alarm counter setting. The day-of-month maximum value depends on the leap year condition, i.e. 2 LSB of year time counter are zeros. AL_DOW Bit Name Type 10 The hour value of the alarm counter setting. RTC+0x0040 Bit Name Type 11 RTC hour alarm setting register RTC+0x003C Bit Name Type 12 The minute value of the alarm counter setting. The range of its value is: 0-59. AL_MINUTE Bit Name Type 13 RTC_AL_MIN RTC year alarm setting register 14 13 12 11 10 9 8 RTC_AL_YEA 7 6 5 4 3 2 AL_YEAR R/W 1 0 The year value of the alarm counter setting. The range of its value is: 0-127. (2000-2127) 213/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 RTC+0x004C Bit Name Type 15 XOSCCALI 14 15 15 12 11 10 9 8 7 6 5 4 3 2 1 XOSCCALI RO 0 RTC_POWERKE Y1 RTC_POWERKEY1 register 14 RTC+0054h Bit Name Type 13 RTC_XOSCCALI This register controls the XOSC32 bias current. RTC+0050h Bit Name Type XOSC bias current control register 13 12 11 10 9 8 7 6 RTC_POWERKEY1 R/W 5 4 3 13 12 11 10 9 1 0 RTC_POWERKE Y2 RTC_POWERKEY2 register 14 2 8 7 6 RTC_POWERKEY2 R/W 5 4 3 2 1 0 These register sets are used to determine if the real time clock has been programmed by software; i.e. the time value in real time clock is correct. When the real time clock is first powered on, the register contents are all undefined, therefore the time values shown are incorrect. Software needs to know if the real time clock has been programmed. Hence, these two registers are defined to solve this power-on issue. After software programs the correct value, these two register sets do not need to be updated. In addition to programming the correct time value, when the contents of these register sets are wrong, the interrupt is not generated. Therefore, the real time clock does not generate the interrupts before the software programs the registers; unwanted interrupt due to wrong time value do not occur. The correct values of these two register sets are: RTC_POWERKEY1 A357h RTC_POWERKEY2 67D2h RTC+0058h Bit Name Type 15 PDN1 14 13 RTC_PDN1 12 11 10 9 8 7 6 5 4 3 2 RTC_PDN1[7:0] R/W 1 0 RTC_PDN1[3:1] is for reset de-bounce mechanism. When RTC_POWERKEY1 & RTC_POWERKEY2 do not match the correct values, RTC_PDN1[3:1] is set to 3 (011 in binary). 0 2ms 1 8ms 2 32ms 3 128ms 4 256ms 5 512ms 6 1024ms 7 2048ms RTC_PDN1[7:4] & RTC_PDN1[0] is the spare register for software to keep power on and power off state information. 214/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 RTC+005Ch Bit Name Type 15 PDN2 14 13 RTC_PDN2 12 11 10 9 8 7 6 5 4 3 2 RTC_PDN2[7:0] R/W 1 0 RTC_PDN2 The spare register for software to keep power on and power off state information. RTC+0064h Bit Name Type 15 RTC_SPARX Spare register for specific purpose 14 15 12 11 10 9 8 7 RTC_SPAR1 R/W 6 5 4 3 2 1 0 These registers are reserved for specific purpose. RTC+006ch Bit Name Type 13 RTC_SPAR1 One-time calibration offset 14 13 12 11 10 9 RTC_DIFF 8 7 6 5 RTC_DIFF R/W 4 3 2 1 0 The function is only active when RTC_POWERKEY1 & RTC_POWERKEY2 match the correct values. RTC_DIFF These registers are used to adjust the internal counter of RTC. It effects once and returns to zero in done. In some cases, you observe the RTC is faster or slower than the standard. To change RTC_TC_SEC is coarse and may cause alarm problem. RTC_DIFF provides a finer time unit. An internal 15-bit counter accumulates in each 32768-HZ clock. Entering a non-zero value into the RTC_DIFF causes the internal RTC counter increases or decreases RTC_DIFF when RTC_DIFF changes to zero again. RTC_DIFF represents as 2’s completement form. For example, if you fill in 0xfff into RTC_DIFF, the internal counter decreases 1 when RTC_DIFF returns to zero. In other words, you can only use RTC_DIFF continuously if RTC_DIFF is equal to zero now. Note: RTC_DIFF ranges from 0x800 (-2048) to 0x7fd (2045). 0x7ff & 0x7fe are forbid to use. RTC+0070h Bit Name Type 15 Repeat calibration offset 14 13 12 11 10 9 RTC_CALI 8 7 6 5 4 3 2 RTC_CALI WO 1 0 The function is only active when RTC_POWERKEY1 & RTC_POWERKEY2 match the correct values. RTC_CALI These registers provide a repeat calibration scheme. RTC_CALI provides 7-bit calibration capability in 8-second duration; in other words, 5-bit calibration capability in each second. RTC_CALI represents in 2’s complement form, such that you can adjust RTC increasing or decreasing. 215/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 Due to RTC_CALI is revealed in 8 seconds, the resolution is less than a 1/32768 clock. Avg. resolution: 1/32768/8=3.81us Avg. adjust range: -0.244~0.240ms/sec in 2’s complement: -0x40~0x3f (-64~63) RTC+0074h Bit 15 Enable the transfers from core to RTC in the queue 14 13 12 11 10 9 8 7 6 5 4 RTC_WRTGR 3 2 1 0 Name WRTG R Type WO WRTGR This register enables the transfers from core to RTC. After you modify all the RTC registers you’d like to change, you must write RTC_WRTGR to 1 to trigger the transfer. The prior writing operations are queued at core power domain. The pending data will not be transferred to RTC domain until WRTGR=1. After WRTGR=1, the pending data is transferred to RTC domain sequentially in order of register address, from low to high. For example: RTC_BBPU -> RTC_IRQ_EN -> RTC_CII_EN -> RTC_AL_MASK -> RTC_TC_SEC -> etc. The CBUSY in RTC_BBPU is equal to 1 in writing process. You can observe CBUSY to determine when the transmission completes. 4.11 Auxiliary ADC Unit The auxiliary ADC unit is used to monitor the status of the battery and charger, to identify the plugged peripheral, and to perform temperature measurement. Seven input channels allow diverse applications in this unit. Each channel can operate in one of two modes: immediate mode and timer-triggered mode. The mode of each channel can be individually selected through register AUXADC_CON0. For example, if the flag SYN0 in the register AUXADC_CON0 is set, the channel 0 is set in timer-triggered mode. Otherwise, the channel operates in immediate mode. In immediate mode, the A/D converter samples the value once only when the flag in the AUXADC_CON1 register has been set. For example, if the flag IMM0 in AUXADC_CON1 is set, the A/D converter samples the data for channel 0. The IMM flags must be cleared and set again to initialize another sampling. The value sampled for channel 0 is stored in register AUXADC_DAT0, the value for channel 1 is stored in register AUXADC_DAT1, etc. If the AUTOSET flag in the register AUXADC_CON3 is set, the auto-sample function is enabled. The A/D converter samples the data for the channel in which the corresponding data register has been read. For example, in the case where the SYN1 flag is not set, the AUTOSET flag is set, when the data register AUXADC_DAT0 has been read, the A/D converter samples the next value for channel 1 immediately. If multiple channels are selected at the same time, the task is performed sequentially on every selected channel. For example, if AUXADC_CON1 is set to 0x7f, that is, all 7 channels are selected, the state machine in the unit starts sampling from channel 6 to channel 0, and saves the values of each input channel in the respective registers. The same process also applies in timer-triggered mode. 216/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 In timer-triggered mode, the A/D converter samples the value for the channels in which the corresponding SYN flags are set when the TDMA timer counts to the value specified in the register TDMA_AUXEV1, which is placed in the TDMA timer. For example, if AUXADC_CON0 is set to 0x7f, all 7 channels are selected to be in timer-triggered mode. The state machine samples all 7 channels sequentially and save the values in registers from AUXADC_DAT0 to AUXADC_DAT6, as it does in immediate mode. There is a dedicated timer-triggered scheme for channel 0. This scheme is enabled by setting the SYN7 flag in the register AUXADC_CON2. The timing offset for this event is stored in the register TDMA_AUXEV0 in the TDMA timer. The sampled data triggered by this specific event is stored in the register AUXADC_DAT7. It is used to separate the results of two individual software routines that perform actions on the auxiliary ADC unit. The AUTOCLRn in the register AUXADC_CON3 is set when it is intended to sample only once after setting timer-triggered mode. If AUTOCLR1 flag has been set, after the data for the channels in timer-triggered mode has been stored, the SYNn flags in the register AUXADC_CON0 are cleared. If AUTOCLR0 flag has been set, after the data for the channel 0 has been stored in the register AUXADC_DAT7, the SYN7 flag in the register AUXADC_CON2 is cleared. The usage of the immediate mode and timer-triggered mode are mutually exclusive in terms of individual channels. The PUWAIT_EN bit in the registers AUXADC_CON3 is used to power up the analog port in advance. This ensures that the power has ramped up to the stable state before A/D converter starts the conversion. The analog part is automatically powered down after the conversion is completed. In MT6235, there are only four external pins (channel 0~3) for voltage detection. The other channels (4~6) are for battery voltage, battery current, and charger, respectively. 4.11.1 Register Definitions AUXADC+0000 Auxiliary ADC control register 0 h Bit Name Type Reset 15 14 13 12 11 10 9 8 AUXADC_CON0 7 6 5 4 3 2 1 0 SYN6 SYN5 SYN4 SYN3 SYN2 SYN1 SYN0 R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 SYNn These 7 bits define whether the corresponding channel is sampled or not in timer-triggered mode. It is associated with timing offset register TDMA_AUXEV1. It supports multiple flags. The flags can be automatically cleared after those channel have been sampled if AUTOCLR1 in the register AUXADC_CON3 is set. To monitor ISENSE and BATSNS, the register INT_NODE_MUX[2] must be set to 1 in advanced. 0 The channel is not selected. 1 The channel is selected. AUXADC+0004 Auxiliary ADC control register 1 h 14 13 12 11 10 9 8 AUXADC_CON1 Bit Name Type Reset 15 IMMn These 7 bits are set individually to sample the data for the corresponding channel. 217/599 7 6 5 4 3 2 1 0 IMM6 IMM5 IMM4 IMM3 IMM2 IMM1 IMM0 R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 It supports multiple flags. MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 0 1 The channel is not selected. The channel is selected. AUXADC+0008 Auxiliary ADC control register 2 h Bit Name Type Reset 15 14 13 12 11 10 9 8 AUXADC_CON2 7 6 5 4 3 2 1 0 SYN7 R/W 0 SYN7 This bit is used only for channel 0 and is to be associated with timing offset register TDMA_AUXEV0 in the TDMA timer in timer-triggered mode. The flag can be automatically cleared after channel 0 has been sampled if AUTOCLR0 in the register AUXADC_CON3 is set. 0 The channel is not selected. 1 The channel is selected. AUXADC+000 Auxiliary ADC control register 3 Ch Bit 15 AUTO Name SET Type R/W Reset 0 14 13 12 11 PUWA IT_EN R/W 0 10 9 8 AUTO AUTO CLR1 CLR0 R/W R/W 0 0 AUXADC_CON3 7 6 5 4 3 2 1 0 STA RO 0 AUTOSET This field defines the auto-sample mode of the module. In auto-sample mode, each channel with its sample register being read can start sampling immediately without configuring the control register AUXADC_CON1 again. PUWAIT_EN Thus field enables the power warm-up period to ensure power stability before the SAR process takes place. It is recommended to activate this field. 0 The mode is not enabled. 1 The mode is enabled. AUTOCLR1 The field defines the auto-clear mode of the module for event 1. In auto-clear mode, each timer-triggered channel gets samples of the specified channels once the SYNn bit in the register AUXADC_CON0 has been set. The SYNn bits are automatically cleared and the channel is not enabled again by the timer event except when the SYNn flags are set again. 0 The automatic clear mode is not enabled. 1 The automatic clear mode is enabled. AUTOCLR0 The field defines the auto-clear mode of the module for event 0. In auto-clear mode, the timer-triggered channel 0 gets the sample once the SYN7 bit in the register AUXADC_CON2 has been set. The SYN7 bit is automatically cleared and the channel is not enabled again by the timer event 0 except when the SYN7 flag is set again. 0 The automatic clear mode is not enabled. 1 The automatic clear mode is enabled. STA The field defines the state of the module. 0 This module is idle. 1 This module is busy. 218/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 AUXADC+0010 Auxiliary ADC channel 0 register h Bit Name Type Reset 15 14 13 12 11 10 9 8 AUXADC_DAT0 7 6 5 4 3 2 1 0 DAT RO 0 The register stores the sampled data for the channel 0. There are 8 registers of the same type for the corresponding channel . The overall register definition is listed in Table 22. Register Address Register Function Acronym AUXADC+0010h Auxiliary ADC channel 0 data register AUXADC_DAT0 AUXADC+0014h Auxiliary ADC channel 1 data register AUXADC_DAT1 AUXADC+0018h Auxiliary ADC channel 2 data register AUXADC_DAT2 AUXADC+001Ch Auxiliary ADC channel 3 data register AUXADC_DAT3 AUXADC+0020h Auxiliary ADC channel 4 data register AUXADC_DAT4 AUXADC+0024h Auxiliary ADC channel 5 data register AUXADC_DAT5 AUXADC+0028h Auxiliary ADC channel 6 data register AUXADC_DAT6 AUXADC+002Ch Auxiliary ADC channel 0 data register for TDMA event 0 AUXADC_DAT7 Table 22 Auxiliary ADC data register list AUXADC Touch Screen Debounce Time +0030h Bit Name Type Reset 15 14 13 12 11 10 9 8 AUX_TS_DEBT 7 6 5 DEBOUNCE TIME R/W 0 4 3 2 1 0 DEBOUNCE TIME While the analog touch screen irq signal is from high to low level, auxadc will issue an interrupt after the debounce time. AUXADC Touch Screen Sample Command +0034h Bit Name Type Reset 15 ADDRESS 14 13 12 11 10 9 8 AUX_TS_CMD 7 6 5 4 3 2 1 0 ADDRESS MODE SE/DF PD R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 Define which x or y or z data will be sampled. 001 Y Position 011 Z1 Position 100 Z2 Position 101 X Position 219/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 Reserved Others MODE Select the sample resolution 0 10-bit resolution 1 8-bit resolution SE/DF Mode selection 0 Differential mode 1 Single-end mode PD Power down control for analog IRQ signal and touch screen sample control signal 00 Turn on Y-_drive signal and PDN_sh_ref 01 Turn on PDN_IRQ and PDN_sh_ref 10 Reserved 11 Turn on PDN_IRQ AUXADC Touch Screen Control +0038h Bit Name Type Reset 15 SPL Touch Screen Sample Trigger 0 No Action 1 While SW writes 1’b1, auxadc will trigger the touch screen process. After the sample process of touch screen finishes, this bit will be disserted. Touch Screen Status 0 Touch Screen is idle. 1 Touch Screen is touched. ST 14 AUXADC 15 12 11 10 9 8 7 6 5 4 3 Touch Screen Sample DATA +003Ch Bit Name Type Reset 13 AUX_TS_CON 14 13 12 11 10 9 8 2 1 ST R 0 0 SPL R/W 0 AUX_TS_DAT0 7 6 5 4 3 2 1 0 DAT RO 0 This register stores the touch screen sample data. 4.12 4.12.1 I2C / SCCB Controller General Description I2C (Inter-IC) /SCCB (Serial Camera Control Bus) is a two-wire serial interface. The two signals are SCL and SDA. SCL is a clock signal that is driven by the master. SDA is a bi-directional data signal that can be driven by either the master or the slave. This generic controller supports the master role and conforms to the I2C specification. 220/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 4.12.1.1 Feature Support I2C compliant master mode operation Adjustable clock speed for LS/FS mode operation. 7bit/10 bit addressing support. High Speed mode support. Slave Clock Extension support. START/STOP/REPEATED START condition Manual/DMA Transfer Mode Multi write per transfer (up to 8 data bytes for non dma mode and 255 data bytes for dma mode) Multi read per transfer (up to 8 data bytes for non dma mode and 255 data bytes for dma mode) Multi transfer per transaction (up to 256 write transfers or 256 read transfers with dma mode) DMA mode with Fifo Flow Control and bus signal holding Combined format transfer with length change capability. Active drive / wired-and I/O configuration 4.12.1.2 Manual/DMA Transfer Mode The controller offers 2 types of transfer mode, Manual and DMA. When Manual mode is selected, in addition to the slave address register, the controller has a built-in 8byte deep FIFO which allows mcu to prepare up to 8 bytes of data for a write transfer, or read up to 8 bytes of data for a read transfer. When DMA mode is enabled, the data to and from the FIFO is controlled via DMA transfer and can therefore support up to 255 bytes of consecutive read or write, with the data read from or write to another memory space. When DMA mode is enabled, flow control mechanism is also implemented to hold the bus clk when FIFO underflow or overflow condition is encountered. 4.12.1.3 Transfer format support This controller has been designed to be as generic as possible in order to support a wide range of devices that may utilize different combinations of transfer formats. Here are the transfer format types that can be supported through different software configuration: (Wording convention note: transfer = anything encapsulated within a Start and Stop or Repeated Start. transfer length = the number of bytes within the transfer. transaction = this is the top unit. Everything combined equals 1 transaction. Transaction length = the number of transfers to be conducted. ) 221/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 Master to slave dir Slave to master dir Single Byte Access Single Byte Write S Slave Address A DATA A P A DATA nA P A DATA A P A/ nA P Single Byte Read S Slave Address Multi Byte Access Multi Byte Write S Slave Address N bytes + ack Multi Byte Read S Slave Address DATA A N bytes + ack/nak Multi Byte Transfer + Multi Transfer (same direction) Multi Byte Write + Multi Transfer S Slave Address A DATA A P + wait time + P + wait time + N bytes + ack/nak X transfers Multi Byte Read + Multi Transfer S Slave Address A DATA A/ nA N bytes + ack/nak X transfers Multi Byte Transfer + Multi Transfer w RS (same direction) 222/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 Multi Byte Write + Multi Transfer + Repeated Start Slave Address S A DATA A R + P + P N bytes + ack/nak X transfers Multi Byte Read + Multi Transfer + Repeated Start Slave Address + S A DATA A/ nA R N bytes + ack/nak X transfers Combined Write/Read with Repeated Start (direction change) (Note: Only supports Write and then Read sequence. Read and then Write is not supported) Combined Multi Byte Write + Multi Byte Read Slave Address S A DATA A Slave Address R A A P M bytes + ack/nak N bytes + ack/nak 4.12.2 DATA Programming Examples Common Transfer Programmable Parameters Programmable Parameters slave_addr S Slave A Address slave_addr + dir change rs_stop DATA A DATA P/ A RS delay_len S Slave A Address DATA A DATA A P/ RS transfer_len / aux transfer_len transfer_len transac_len Output Waveform Timing Programmable Parameters 223/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 Sample width = sample_cnt_div * (1/13Mhz) step_cnt_div = number of samples half pulse width = step_cnt_div * sample_cnt_div * (1/13Mhz) 4.12.3 Register Definitions I2CREG+0000h Data Port Register Bit Name Type Reset 15 14 13 12 11 10 DATA_PORT 9 8 7 6 5 4 3 FIFO DATA R/W 0 2 1 0 DATA_PORT[7:0] This is the FIFO access port. During master write sequences (slave_addr[0] = 0), this port can be written by APB, and during master read sequences (slave_addr[0] = 1), this port can be read by APB. (NOTE) Slave_addr must be set correctly before accessing the fifo. (DEBUG ONLY) If the fifo_apb_debug bit is set, then the FIFO can be read and write by the APB I2CREG+0004h Slave Address Register Bit Name Type Reset 15 14 13 12 11 10 9 SLAVE_ADDR 8 7 6 5 4 3 SLAVE_ADDR R/W 0 2 1 0 SLAVE_ADDR [7:0] This specifies the slave address of the device to be accessed. Bit 0 is defined by the I2C protocol as a bit that indicates the direction of transfer. 1 = master read, 0 = master write. I2CREG+0008h Interrupt Mask Register Bit 15 14 13 12 11 10 9 INTR_MASK 8 Name Type Reset 7 6 5 4 3 2 1 0 TRAN HS_N ACKE DEBU SAC_ ACKE RR G COMP R R.W R/W R/W R/W 1 1 1 1 This register provides masks for the corresponding interrupt sources as indicated in intr_stat register. 1 = allow interrupt 0 = disable interrupt Note: while disabled, the corresponding interrupt will not be asserted, however the intr_stat will still be updated with the status. Ie. mask does not affect intr_stat register values. 224/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 I2CREG+000C Interrupt Status Register h Bit 15 14 13 12 11 10 9 INTR_STAT 8 7 6 5 4 3 Name Type Reset 2 1 0 TRAN HS_N ACKE SAC_ ACKE RR COMP RR W1C W1C W1C 0 0 0 When an interrupt is issued by i2c controller, this register will need to be read by mcu to determine the cause for the interrupt. After this status has been read and appropriate actions are taken, the corresponding interrupt source will need to be write 1 cleared. HS_NACKERR This status is asserted if hs master code nack error detection is enabled. If enabled, hs master code nack err will cause transaction to end and stop will be issued. ACKERR This status is asserted if ACK error detection is enabled. If enabled, ackerr will cause transaction to end and stop will be issued. TRANSAC_COMP This status is asserted when a transaction has completed successfully. I2CREG+0010h Control Register Bit 15 14 13 12 11 CONTROL 10 9 8 Name Type Reset 7 6 TRAN SFER _LEN _CHA NGE R/W 0 5 4 3 2 1 0 ACKE DIR_C CLK_ DMA_ RS_S RR_D HANG EXT ET_E EN TOP EN E N R/W 0 RW 0 RW 0 RW 0 RW 0 R/W 0 TRANSFER_LEN_CHANGEThis options specifies whether or not to change the transfer length after the fist transfer completes. If enabled, the transfers after the first transfer will use the transfer_len_aux parameter. ACKERR_DET_EN This option enables slave ack error detection. When enabled, if slave ack error is detected, the master shall terminate the transaction by issuing a STOP condition and then asserts ackerr interrupt. Mcu shall handle this case appropriately and then resets the fifo address before reissuing transaction again. If this option is disabled, the controller will ignore slave ack error and keep on scheduled transaction. DIR_CHANGE 0 disable 1 enable This option is used for combined transfer format, where the direction of transfer is to be changed from write to read after the FIRST RS condition. Note: when set to 1, the transfers after the direction change will be based on the transfer_len_aux parameter. CLK_EXT_EN 0 disable 1 enable I2C spec allows slaves to hold the SCL line low if it is not yet ready for further processing. Therefore, if this bit is set to 1, master controller will enter a high wait state until the slave releases the SCL line. 225/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 DMA_EN By default, this is disabled, and fifo data shall be manually prepared by mcu. This default setting should be used for transfer sizes of less than 8 data bytes and no multiple transfer is configured. When enabled, dma requests are turned on, and the fifo data should be prepared in memory. RS_STOP In LS/FS mode, this bit affects multi-transfer transaction only. It controls whether or not REPEATED-START condition is used between transfers. The last ending transfer always ends with a STOP. In HS mode, this bit must be set to 1. I2CREG+0014h Bit Name Type Reset 15 14 0 use STOP 1 use REPEATED-START Transfer Length Register (Number of Bytesper Transfer) 13 12 11 10 9 8 TRANSFER_LEN_AUX R/W ‘h1 7 6 5 TRANSFER_LEN 4 3 2 TRANSFER_LEN 1 0 R/W ‘h1 TRANSFER_LEN_AUX[4:0]This field is valid only when dir_change is set to 1. This indicates the number of DATA BYTES to be transferred in 1 transfer unit (excluding slave address byte) for the transfers following the direction change. I.e., if dir_change =1, then the first write transfer length depends on transfer_len, while the second read transfer length depend on transfer_len_aux. Dir change is always after the first transfer. (NOTE) The value must be set greater than 1, otherwise no transfer will take place. TRANSFER_LEN[7:0] This indicates the number of DATA BYTES to be transferred in 1 transfer unit (excluding slave address byte) (NOTE) I2CREG+0018h Bit Name Type Reset 15 14 The value must be set greater than 1, otherwise no transfer will take place. Transaction Length Register (Number of Transfers per TRANSAC_LEN Transaction) 13 12 11 10 9 8 7 6 5 4 3 2 TRANSAC_LEN 1 0 R/W ‘h1 TRANSAC_LEN[7:0] This indicates the number of TRANSFERS to be transferred in 1 transaction (NOTE) The value must be set greater than 1, otherwise no transfer will take place. I2CREG+001C Inter Delay Length Register h Bit Name Type Reset 15 14 13 12 11 10 9 DELAY_LEN 8 226/599 7 6 5 4 3 DELAY_LEN R/W ‘h2 2 1 0 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 DELAY_LEN[3:0] This sets the wait delay between consecutive transfers when RS_STOP bit is set to 0. (the unit is same as the half pulse width) I2CREG+0020h Timing Control Register Bit 15 14 13 12 DATA Name READ DATA_READ_TIME ADJ Type R/W R/W Reset ‘h0 ‘h1 11 10 TIMING 9 8 7 6 5 4 3 2 1 SAMPLE_CNT_DIV STEP_CNT_DIV R/W ‘h3 R/W ‘h3 0 LS/FS only. This register is used to control the output waveform timing. Each half pulse width (ie. each high or low pulse) is equal to = step_cnt_div * (sample_cnt_div * 1/13Mhz) SAMPLE_CNT_DIV[2:0] Used for LS/FS only. This adjusts the width of each sample. (sample width = sample_cnt_div * 1/13Mhz) STEP_CNT_DIV[5:0] This specifies the number of samples per half pulse width (ie. each high or low pulse) DATA_READ_ADJ When set to 1, data latch in sampling time during master reads are adjusted according to DATA_READ_TIME value. Otherwise, by default, data is latched in at half of the high pulse width point. This value must be set to less or equal to half the high pulse width. DATA_READ_TIME[2:0] This value is valid only when DATA_READ_ADJ is set to 1. This can be used to adjust so that data is latched in at earlier sampling points (assuming data is settled by then) I2CREG+0024h Start Register Bit 15 14 13 12 11 START 10 9 8 7 6 5 4 3 2 1 Name Type Reset START This register starts the transaction on the bus. It is auto deasserted at the end of the transaction. I2CREG+0030h Fifo Status Register Bit 0 STAR T R/W 0 15 14 13 12 11 10 FIFO_STAT 9 8 7 6 5 Name RD_ADDR WR_ADDR FIFO_OFFSET Type Reset RO 0 RO 0 RO 0 4 3 2 0 0 RD_ADDR[3:0] The current rd address pointer. (only bit [2:0] has physical meaning) WR_ADDR[3:0] The current wr address pointer. (only bit [2:0] has physical meaning) 1 0 WR_F RD_E ULL MPTY RO RO 0 0 FIFO_OFFSET[3:0] wr_addr[3:0] – rd_addr[3:0] WR_FULL This indicates that the fifo is full. RD_EMPTY This indicates that the fifo is empty. I2CREG+0034h Fifo Thresh Register Bit 15 14 13 12 11 10 FIFO_THRESH 9 8 227/599 7 6 5 4 3 2 1 0 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 Name Type Reset TX_TRIG_THRESH RW ‘h7 DEBUG ONLY. RX_TRIG_THRESH R/W ‘h0 By default, these values do not need to be adjusted. Note! for RX, no timeout mechanism is implemented. Therefore, RX_trig_thresh must be left at 0, or there would be data left in the fifo that is not fetched by DMA controller. TX_TRIG_THRESH[2:0] When tx fifo level is below this value, tx dma request is asserted. RX_TRIG_THRESH[2:0] When rx fifo level is above this value, rx dma request is asserted. FIFO_ADDR_CL R I2CREG+0038h Fifo Address Clear Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Name Type Reset FIFO_ADDR_CLR When written with a 1’b1, a 1 pulse fifo_addr_clr is generated to clear the fifo address to back to 0. I2CREG+0040h IO Config Register Bit 15 14 0 FIFO_ ADDR _CR WO 0 13 12 11 10 IO_CONFIG 9 8 7 6 5 4 3 Name Type Reset 2 IO SYNC EN R/W 0 1 SDA_I O_CO NFIG R/W 0 0 SCL_I O_CO NFIG R/W 0 This register is used to configure the I/O for the sda and scl lines to select between normal i/o mode, or open-drain mode to support wired-and bus. IO_SYNC_EN DEBUG ONLY: When set to 1, scl and sda inputs will be first dual synced by bclk_ck. This should not be needed. Only reserved for debugging. SDA_IO_CONFIG 0 normal tristate io mode 1 open-drain mode 0 normal tristate io mode 1 open-drain mode SCL_IO_CONFIG I2CREG+0044h RESERVED DEBUG Register Bit Name Type Reset 15 14 13 12 11 10 9 8 DEBUG 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 NOTE: This register is for DEBUG ONLY. The bits are R/W, do not change the values from the default value. 228/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 I2CREG+0048h High Speed Mode Register Bit 15 14 13 12 11 10 9 HS 8 7 6 5 4 Name HS_SAMPLE_CNT DIV HS_STEP_CNT_DIV MASTER_CODE Type Reset R/W 0 R/W 1 R/W 0 3 2 1 0 HS_N ACKE HS_E RR_D N ET_E N R/W R/W 1 0 This register contains options for supporting high speed operation features Each HS half pulse width (ie. each high or low pulse) is equal to = step_cnt_div * (sample_cnt_div * 1/13Mhz) HS_SAMPLE_CNT_DIV[2:0]When high speed mode is entered after the master code transfer has been completed, the sample width becomes dependent on this parameter. HS_STEP_CNT_DIV[2:0] When high speed mode is entered after the master code transfer has been completed, the number of samples per half pulse width becomes dependent on this value. MASTER_CODE[2:0] This is the 3 bit programmable value for the master code to be transmitted. HS_NACKERR_DET_EN This enables NACKERR detection during the master code transmission. When enabled, if NACK is not received after master code has been transmitted, the transaction will terminated with a STOP condition. HS_EN This enables the high speed transaction. (note: rs_stop must be set to 1 as well) I2CREG+0050h Soft Reset Register Bit 15 14 13 12 11 10 SOFTRESET 9 8 7 6 5 4 3 2 1 Name Type Reset SOFT_RESET When written with a 1’b1, a 1 pulse soft reset is used as synchronous reset to reset the I2C internal hardware circuits. I2CREG+0064h Debug Status Register Bit 15 0 SOFT _RES ET WO 0 14 13 12 11 10 DEBUGSTAT 9 8 Name Type Reset 7 6 5 4 MAST MAST BUS_ ER_W ER_R BUSY RITE EAD RO RO RO 0 1 0 3 2 1 0 MASTER_STATE RO 0 BUS_BUSY DEBUG ONLY: valid when bus_detect_en is 1. bus_busy = 1 indicates a start transaction has been detected and no stop condition has been detected yet. MASTER_WRITE DEBUG ONLY: 1 = current transfer is in the master write dir MASTER_READ DEBUG ONLY: 1 = current transfer is in the master read dir MASTER_STATE[3:0] DEBUG ONLY: reads back the current master_state. 229/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 I2CREG+0068h Debug Control Register Bit 15 14 13 12 11 10 9 DEBUGCTRL 8 7 6 5 4 3 2 1 Name APB_ DEBU G_RD Type Reset WO 0 APB_DEBUG_RD 0 FIFO_ APB_ DEBU G R/W 0 This bit is only valid when fifo_apb_debug is set to 1. Writing to this register will generate a 1 pulsed fifo apb rd signal for reading the fifo data. FIFO_APB_DEBUG This is used for trace32 debug purposes. When using trace32, and the memory map is shown, turning this bit on will block the normal apb read access. Apb read access to the fifo is then enabled by writing to apb_debug_rd. 0 1 disable enable 230/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 231/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 5 Microcontroller Coprocessors Microcontroller Coprocessors are designed to run computing-intensive processes in place of the Microcontroller (MCU). These coprocessors especially target timing critical GSM/GPRS Modem processes that require fast response and large data movement. Controls to the coprocessors are all through memory access via the APB. 5.1 Divider To ease the processing load of MCU, a divider is employed here. The divider can operate signed and unsigned 32bit/32bit division, as well as modulus. The processing time of the divider is from 1 clock cycle to 33 clock cycles, which depends upon the magnitude of the value of the dividend. The detailed processing time is listed below in Table 18. From the table we can see that there are two kind of processing time (except for when the dividend is zero) in an item. Which kind depends on whether there is the need for restoration at the last step of the division operation. After the divider is started by setting START to “1” in Divider Control Register, DIV_RDY will go low, and it will be asserted after the division process is finished. MCU could detect this status bit by polling it to know the correct access timing. In order to simplify polling, only the value of register DIV_RDY will appear while Divider Control Register is read. Hence, MCU does not need to mask other bits to extract the value of DIV_RDY. In GSM/GPRS system, many divisions are executed with some constant divisors. Therefore, some often-used constants are stored in the divider to speed up the process. By controlling control bits IS_CNST and CNST_IDX in Divider Control register, one can start a division without giving a divisor. This could save the time for writing divisor in and the instruction fetch time, and thus make the process more efficient. Signed Division Unsigned Division Dividend Clock Cycles 0000_0000h Dividend 1 Clock Cycles 0000_0000h 1 0000_00ffh – (-0000_0100h), 8 or 9 excluding 0x0000_0000 0000_0001h - 0000_00ffh 8 or 9 0000_ffffh – (-0001_0000h) 16 or 17 0000_0100h - 0000_ffffh 16 or 17 00ff_ffffh – (-0100_0000h) 24 or 25 0001_0000h - 00ff_ffffh 24 or 25 7fff_ffffh – (-8000_0000h) 32 or 33 0100_0000h - ffff_ffffh 32 or 33 Table 23 Processing time in different value of dividend. 5.1.1 Register Definitions DIVIDER+0000 Divider Control Register h Bit Name Type Reset Bit DIV_CON 31 30 29 28 27 26 25 24 23 22 15 14 13 12 11 10 9 8 7 6 Name 232/599 21 20 5 4 IN_CN SIGN ST 19 3 18 17 16 CNST_IDX WO 0 2 1 0 DIV_R STAR DY T MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 Type Reset WO 0 WO 1 RO 1 WO 0 To start division. It will return to 0 after division has started. Current status of divider. Note that when DIV_CON register is read, only the value of DIV_RDY will appear. That means program does not need to mask other part of the register to extract the information of DIV_RDY. 0 division is in progress. 1 division is finished. SIGN To indicate signed or unsigned division. 0 Unsigned division. 1 Signed division. IS_CNST To indicate if internal constant value should be used as a divisor. If IS_CNST is enabled, User does not need to write the value of the divisor, and divider will automatically use the internal constant value instead. What value divider will use depends on the value of CNST_IDX. 0 Normal division. Divisor is written in via APB 1 Using internal constant divisor instead. CNST_IDX Index of constant divisor. 0 divisor = 13 1 divisor = 26 2 divisor = 51 3 divisor = 52 4 divisor = 102 5 divisor = 104 START DIV_RDY DIVIDER +0004h Bit Name Type Reset Bit Name Type Reset Divider Dividend register 31 30 29 28 27 26 15 14 13 12 11 10 DIV_DIVIDEND 25 24 23 22 DIVIDEND[31:16] WO 0 9 8 7 6 DIVIDEND[15:0] WO 0 21 20 19 18 17 16 5 4 3 2 1 0 Dividend. DIVIDER +0008h Bit Name Type Reset Bit Name Type Reset Divider Divisor register 31 30 29 28 27 26 15 14 13 12 11 10 DIV_DIVISOR 25 24 23 22 DIVISOR[31:16] R/W 0 9 8 7 6 DIVISOR[15:0] R/W 0 21 20 19 18 17 16 5 4 3 2 1 0 Divisor. 233/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 DIVIDER +000Ch Bit Name Type Reset Bit Name Type Reset Divider Quotient register 31 30 29 28 27 26 15 14 13 12 11 10 DIV_QUOTIENT 25 24 23 22 QUOTIENT[31:16] RO 0 9 8 7 6 QUOTIENT[15:0] RO 0 21 20 19 18 17 16 5 4 3 2 1 0 Quotient. DIVIDER +0010h Bit Name Type Reset Bit Name Type Reset DIV_REMAINDE R Divider Remainder register 31 30 29 28 27 26 15 14 13 12 11 10 25 24 23 22 REMAINDER[31:16] RO 0 9 8 7 6 REMAINDER[15:0] RO 0 21 20 19 18 17 16 5 4 3 2 1 0 Remainder. 5.2 5.2.1 CSD Accelerator General Description This unit performs the data format conversion of RA0, RA1, and FAX in CSD service. CSD service consists of two major functions: data flow throttling and data format conversion. The data format conversion is a bit-wise operation and takes a number of instructions to complete a conversion. Therefore, it is not efficient to do by MCU itself. A coprocessor, CSD accelerator, is designed here to reduce the computing power needed to perform this function. CSD accelerator only helps in converting data format; the data flow throttling function is still implemented by the MCU. CSD accelerator performs three types of data format conversion, RA0, RA1, and FAX. For RA0 conversion, only uplink RA0 data format conversion is provided here. This is because there are too many judgments on the downlink path conversion, which will greatly increase area cost. Uplink RA0 conversion is to insert one start bit and one stop bit before and after a byte, respectively, during 16 bytes. Figure 23 illustrates the detailed conversion table. RA0 converter can only process RA0 data state by state. Before filling in new data, software must make sure the converted data of certain state is withdrawn, or the converted data will be replaced by the new data. For example, if 32-bit data is written, and the state pointer goes from state 0 to state 1, and word ready of state 0 is asserted; then, before writing the next 32-bit data, the word of state 0 should be withdrawn first, or the data will be lost. 234/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 RA0 records the number of written bytes, state pointer, and ready state word. The information can help software to perform flow control. See Register Definition for more detail. Data bits Start bit Stop bit State 0 State 1 State 2 State 3 State 4 Figure 23 data format conversion of RA0 For RA1 conversion, both directions, downlink and uplink, are supported. The data formats vary in different data rate. The detailed conversion table is shown in Figure 24 and Figure 25. The yellow part is the payload data, and the blue part is the status bit. 235/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 Bit 0 Bit 6 D1 D2 D3 D6 S1 D7 D8 D9 D10 D11 D12 X D13 D14 D15 D16 D17 D18 S3 D19 D20 D21 D22 D23 D24 S4 E4 E5 D4 D5 E6 E7 D25 D26 D27 D28 D29 D30 S6 D31 D32 D33 D34 D35 D36 X D37 D38 D39 D40 D41 D42 S8 D43 D44 D45 D46 D47 D48 S9 Bit 59 Figure 24 data format conversion for 6k/12k RA1 Figure 25 data format conversion for 3.6k RA1 For FAX, two types of bit-reversal functions are provided. One is bit-wise reversal, and the other is byte-wise reversal, which are illustrated in Figure 26 and Figure 27, respectively. 236/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 b31 b30 b29 b0 b0 b31 b1 b2 Figure 26 Type 1 bit reverse b31 b23 b15 b7 b7 b0 b15 b8 b23 b16 b31 b0 b24 Figure 27 Type 2 bit reverse Register Address Register Function Acronym CSD + 0000h CSD RA0 Control Register CSD_RA0_CON CSD + 0004h CSD RA0 Status Register CSD_RA0_STA CSD + 0008h CSD RA0 Input Data Register CSD_RA0_DI CSD + 000Ch CSD RA0 Output Data Register CSD_RA0_DO CSD + 0100h CSD RA1 6K/12K Uplink Input Data Register 0 CSD_RA1_6K_12K_ULDI0 CSD + 0104h CSD RA1 6K/12K Uplink Input Data Register 1 CSD_RA1_6K_12K_ULDI1 CSD + 0108h CSD RA1 6K/12K Uplink Status Data Register CSD_RA1_6K_12K_ULSTUS CSD + 010Ch CSD RA1 6K/12K Uplink Output Data Register 0 CSD_RA1_6K_12K_ULDO0 CSD + 0110h CSD RA1 6K/12K Uplink Output Data Register 1 CSD_RA1_6K_12K_ULDO1 CSD + 0200h CSD RA1 6K/12K Downlink Input Data Register 0 CSD_RA1_6K_12K_DLDI0 CSD + 0204h CSD RA1 6K/12K Downlink Input Data Register 1 CSD_RA1_6K_12K_DLDI1 CSD + 0208h CSD RA1 6K/12K Downlink Output Data Register 0 CSD_RA1_6K_12K_DLDO0 CSD + 020Ch CSD RA1 6K/12K Downlink Output Data Register 1 CSD_RA1_6K_12K_DLDO1 CSD + 0210h CSD RA1 6K/12K Downlink Status Data Register CSD_RA1_6K_12K_DLSTUS CSD + 0300h CSD RA13.6K Uplink Input Data Register 0 CSD_RA1_3P6K_ULDI0 CSD + 0304h CSD RA13.6K Uplink Status Data Register CSD_RA1_3P6K_ULSTUS CSD + 0308h CSD RA13.6K Uplink Output Data Register 0 CSD_RA1_3P6K_ULDO0 CSD + 030Ch CSD RA13.6K Uplink Output Data Register 1 CSD_RA1_3P6K_ULDO1 CSD + 0400h CSD RA1 3.6K Downlink Input Data Register 0 CSD_RA1_3P6K_DLDI0 CSD + 0404h CSD RA1 3.6K Downlink Input Data Register 1 CSD_RA1_3P6K_DLDI1 237/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 CSD + 0408h CSD RA1 3.6K Downlink Output Data Register 0 CSD_RA1_3P6K_DLDO0 CSD + 040Ch CSD RA1 3.6K Downlink Status Data Register CSD_RA1_3P6K_DLSTUS CSD + 0500h CSD FAX Bit Reverse Type 1 Input Data Register CSD_FAX_BR1_DI CSD + 0504h CSD FAX Bit Reverse Type 1 Output Data Register CSD_FAX_BR1_DO CSD + 0510h CSD FAX Bit Reverse Type 2 Input Data Register CSD_FAX_BR2_DI CSD + 0514h CSD FAX Bit Reverse Type 2 Output Data Register CSD_FAX_BR2_DO Table 24 CSD Accelerater Registers 5.2.2 Register Definitions CSD+0000h Bit Name Type Reset Bit Name Type Reset CSD RA0 Control Register CSD_RA0_CON 31 30 29 28 27 26 25 24 23 22 15 14 13 12 11 10 9 8 7 6 21 20 5 4 RST BTS0 WO WO 0 0 19 18 3 2 17 16 1 0 VLD_BYTE WO 100 VLD_BYTE Specify how many valid bytes in the current input data. It must be specified before filling data in. BTS0 Back to state 0. Force RA0 converter go back to state 0. Incomplete word will be padded by STOP bit. For instance, back-to-state0 command is issued after 8 byte data are filled in. Then these bit after the 8th byte will be padded with stop bits, and RDYWD2 is asserted. After removing state word 2, the state pointer goes back to state 0. Note that new data filling should take place after removing state word 2, or the state pointer may be out of order. Data bits Start bit Stop bit State 0 State 1 State 2 Figure 28 Example of Back to state 0 RST Reset RA0 converter. In case, erroneously operation makes data disordered. This bit can restore all state to original state. 238/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 CSD+0004h Bit Name Type Reset Bit Name Type Reset CSD RA0 Status Register CSD_RA0_STA 31 30 29 28 27 26 25 24 23 15 14 13 12 11 10 9 BYTECNT RO 0 8 7 22 21 20 19 18 17 16 6 5 CRTSTA RO 0 4 3 2 RDYWD RC 0 1 0 RDYWD0~4 Ready word. To indicate which state word is ready for withdrawal. Data should be withdrawn before next data fills into CSD_RA0_DI, if there are any bits asserted. 0 Not ready 1 Ready CRTSTA current state. State0 ~ state4. To indicate which state word software is filling in. BYTECNT The total number of bytes software is filling in. CSD+0008h CSD RA0 Input Data Register 30 Bit Name Type Reset Bit Name Type Reset 31 DIN The RA0 convert input data. Ready word indicator shall be check before filling in data. If any words are ready, withdraw them first; otherwise the ready data in RA0 converter will be replaced. 28 27 26 25 24 23 22 21 20 19 18 17 16 7 6 5 4 3 2 1 0 DIN WO 0 15 14 13 12 11 10 9 8 DIN WO 0 CSD+000Ch Bit Name Type Reset Bit Name Type Reset 29 CSD_RA0_DI CSD RA0 Output Data Register 31 30 29 28 27 26 25 15 14 13 12 11 10 9 CSD_RA0_DO 24 23 DOUT RO 0 8 7 DOUT RO 0 22 21 20 19 18 17 16 6 5 4 3 2 1 0 DOUT RA0 converted data. The return data corresponds to the ready word indicator defined in CSD_RA0_STA register. The five bit of RDYWD map to state0 ~ state 4 accordingly. When CSD_RA0_DO is read, the asserted state word will be returned. If there are two state words asserted at the same time, the lower one will be returned. CSD+0100h Bit Name Type Reset Bit 31 CSD_RA1_6K_1 2K_ULDI0 CSD RA1 6K/12K Uplink Input Data Register 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 7 6 5 4 3 2 1 0 DIN WO 0 15 14 13 12 11 10 9 8 239/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 Name Type Reset DIN DIN WO 0 The D1 to D32 of RA1 uplink data. CSD+0104h CSD_RA1_6K_1 2K_ULDI1 CSD RA1 6K/12K Uplink Input Data Register 1 Bit Name Type Reset Bit Name Type Reset 31 30 29 28 27 26 25 24 15 14 13 12 11 10 9 8 DIN The D33 to D48 of RA1 uplink data. 23 22 21 20 19 18 17 16 7 6 5 4 3 2 1 0 DIN WO 0 CSD+0108h CSD_RA1_6K_1 2K_ULSTUS CSD RA1 6K/12K Uplink Status Data Register Bit Name Type Reset Bit Name Type Reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 E7 WO 0 5 E6 WO 0 4 E5 WO 0 3 E4 WO 0 2 X WO 0 1 SB WO 0 0 SA WO 0 SA SB X E4 E5 E6 E7 Represents S1, S3, S6, and S8 of status bits. Represents S4 and S9 of status bits. Represents X of status bits. Represents E4 of status bits. Represents E5 of status bits. Represents E6 of status bits. Represents E7 of status bits. CSD+010Ch Bit Name Type Reset Bit Name Type Reset CSD_RA1_6K_1 2K_ULDO0 CSD RA1 6K/12K Uplink Output Data Register 0 31 30 29 28 27 26 25 15 14 13 12 11 10 9 24 23 DOUT RO 0 8 7 DOU RO 0 22 21 20 19 18 17 16 6 5 4 3 2 1 0 DOUT The bit 0 to bit 31 of RA1 6K/12K uplink frame. 240/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 CSD+0110h Bit Name Type Reset Bit Name Type Reset CSD_RA1_6K_1 2K_ULDO1 CSD RA1 6K/12K Uplink Output Data Register 1 31 30 29 28 27 26 25 24 23 15 14 13 12 11 10 9 8 7 DOUT RO 0 22 21 DOUT RO 0 6 5 20 19 18 17 16 4 3 2 1 0 DOUT The bit32 to bit 59 of RA1 6K/12K uplink frame. CSD+0200h Bit Name Type Reset Bit Name Type Reset 31 DIN The bit 0 to bit 31 of RA1 6K/12K downlink frame. 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 7 6 5 4 3 2 1 0 DIN WO 0 15 14 13 12 11 10 9 8 DIN WO 0 CSD+0204h CSD_RA1_6K_1 2K_DLDI1 CSD RA1 6K/12K Downlink Input Data Register 1 Bit Name Type Reset Bit Name Type Reset 31 DIN The bit32 to bit 59 of RA1 6K/12K downlink frame. 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 5 4 3 2 1 0 DIN WO 0 15 14 13 12 11 10 9 8 7 6 DIN WO 0 CSD+0208h Bit Name Type Reset Bit Name Type Reset CSD_RA1_6K_1 2K_DLDI0 CSD RA1 6K/12K Downlink Input Data Register 0 CSD_RA1_6K_1 2K_DLDO0 CSD RA1 6K/12K Downlink Output Data Register 0 31 30 29 28 27 26 25 15 14 13 12 11 10 9 24 23 DOUT RO 0 8 7 DOUT RO 0 22 21 20 19 18 17 16 6 5 4 3 2 1 0 DOUT The D1 to D32 of RA1 downlink data. 241/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 CSD+020Ch Bit Name Type Reset Bit Name Type Reset CSD_RA1_6K_1 2K_DLDO1 CSD RA1 6K/12K Downlink Output Data Register 1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 DOUT RO 0 6 5 4 3 2 1 0 DOUT The D33 to D48 of RA1 downlink data. CSD+0210h CSD_RA1_6K_1 2K_DLSTUS CSD RA1 6K/12K Downlink Status Data Register Bit Name Type Reset Bit Name Type Reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 E7 RO 0 5 E6 RO 0 4 E5 RO 0 3 E4 RO 0 2 X RO 0 1 SB RO 0 0 SA RO 0 SA SB X E4 E5 E6 E7 The result of majority votes of S1, S3, S6 and S8. SA is “0” if equal vote. The result of majority votes of S4 and S9. SB is “0” if equal vote. The result of majority votes of two X bits in downlink frame. X is “0” if equal vote. Represents E4 of status bits. Represents E5 of status bits. Represents E6 of status bits. Represents E7 of status bits. CSD+0300h Bit Name Type Reset Bit Name Type Reset 31 DIN The D1 to D24 of RA1 3.6K uplink data. 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 3 2 1 0 DIN WO 0 15 14 13 12 11 10 9 8 7 6 5 4 DIN WO 0 CSD+0304h Bit Name Type CSD_RA1_3P6K _ULDI0 CSD RA1 3.6K Uplink Input Data Register 0 31 CSD_RA1_3P6K _ULSTUS CSD RA1 3.6K Uplink Status Data Register 30 29 28 27 26 25 24 242/599 23 22 21 20 19 18 17 16 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 Reset Bit Name Type Reset SA SB X E4 E5 E6 E7 15 14 12 11 10 9 8 7 6 E7 WO 0 5 E6 WO 0 4 E5 WO 0 3 E4 WO 0 2 X WO 0 1 SB WO 0 0 SA WO 0 Represents S1, S3, S6, and S8 of status bits. Represents S4 and S9 of status bits. Represents X of status bits. Represents E4 of status bits. Represents E5 of status bits. Represents E6 of status bits. Represents E7 of status bits. CSD+0308h Bit Name Type Reset Bit Name Type Reset 13 CSD_RA1_3P6K _ULDO0 CSD RA1 3.6K Uplink Output Data Register 0 31 30 29 28 27 26 25 15 14 13 12 11 10 9 24 23 DOUT RO 0 8 7 DOUT RO 0 22 21 20 19 18 17 16 6 5 4 3 2 1 0 DOUT The bit 0 to bit 31 of RA1 3.6K uplink frame CSD+030Ch Bit Name Type Reset Bit Name Type Reset CSD_RA1_3P6K _ULDO1 CSD RA1 3.6K Uplink Output Data Register 1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 DOUT RO 0 0 DOUT The bit 32 to bit 35 of RA1 3.6K uplink frame CSD+0400h CSD_RA1_3P6K _DLDI0 CSD RA1 3.6K Downlink Input Data Register 0 Bit Name Type Reset Bit Name Type Reset 31 30 29 28 27 26 25 DIN The bit 0 to bit 31 of RA1 3.6K downlink frame 24 23 22 21 20 19 18 17 16 7 6 5 4 3 2 1 0 DIN WO 0 15 14 13 12 11 10 9 8 DIN WO 0 243/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 CSD+0404h CSD_RA1_3P6K _DLDI1 CSD RA1 3.6K Downlink Input Data Register 1 Bit Name Type Reset Bit Name Type Reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 15 14 13 12 11 10 9 8 7 6 5 4 3 2 DIN The bit 32 to bit 35 of RA1 3.6K downlink frame 17 16 1 0 DIN WO 0 CSD+0408h CSD_RA1_3P6K _DLDO0 CSD RA1 3.6K Downlink Output Data Register 0 Bit Name Type Reset Bit Name Type Reset 31 30 29 28 27 26 25 24 23 22 21 15 14 13 12 11 10 9 8 7 DOUT RO 0 6 5 DIN The D1 to D24 of RA1 3.6K downlink data. CSD+040Ch 20 19 DOUT RO 0 4 3 18 17 16 2 1 0 CSD_RA1_3P6K _DLSTUS CSD RA1 3.6K Downlink Status Data Register Bit Name Type Reset Bit Name Type Reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 E7 RO 0 5 E6 RO 0 4 E5 RO 0 3 E4 RO 0 2 X RO 0 1 SB RO 0 0 SA RO 0 SA SB X E4 E5 E6 E7 The result of majority votes of S1, S3, S6 and S8. SA is “0” if equal vote. The result of majority votes of S4 and S9. SB is “0” if equal vote. The result of majority votes of two X bits in downlink frame. X is “0” if equal vote. Represents E4 of status bits. Represents E5 of status bits. Represents E6 of status bits. Represents E7 of status bits. CSD+0500h Bit Name Type 31 CSD_FAX_BR1_ DI CSD FAX Bit Reverse Type 1 Input Data Register 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 DIN WO 244/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 Reset Bit Name Type Reset DIN 0 15 14 12 11 10 9 8 7 6 5 4 3 2 1 0 DIN WO 0 32-bit input data for type 1 bit reverse of FAX data. The action of Type 1 bit reverse is to reverse this word by word. CSD+0504h Bit Name Type Reset Bit Name Type Reset 13 CSD_FAX_BR1_ DO CSD FAX Bit Reverse Type 1 Output Data Register 31 30 29 28 27 26 25 15 14 13 12 11 10 9 24 23 DOUT RO 0 8 7 DOUT RO 0 22 21 20 19 18 17 16 6 5 4 3 2 1 0 DOUT 32-bit result data for type 1 bit reverse of FAX data. CSD+0510h CSD_FAX_BR2_ DI CSD FAX Bit Reverse Type 2 Input Data Register Bit Name Type Reset Bit Name Type Reset 31 30 DIN 32-bit input data for type 2 bit reverse of FAX data. The action of Type 1 bit reverse is to reverse this word by byte. 28 27 26 25 24 23 22 21 20 19 18 17 16 7 6 5 4 3 2 1 0 DIN WO 0 15 14 13 12 11 10 9 8 DIN WO 0 CSD+0514h Bit Name Type Reset Bit Name Type Reset 29 CSD_FAX_BR2_ DO CSD FAX Bit Reverse Type 2 Output Data Register 31 30 29 28 27 26 25 15 14 13 12 11 10 9 24 23 DOUT RO 0 8 7 DOUT RO 0 22 21 20 19 18 17 16 6 5 4 3 2 1 0 DOUT 32-bit result data for type 2 bit reverse of FAX data. 245/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 5.3 FCS Codec 5.3.1 General Description FCS (Frame Check Sequence) is used to detect errors in the following information bits: z RLP-frame of CSD services in GSM. The frame length is fixed as 240 or 576 bits including the 24-bit FCS field. z LLC-frame of GPRS service. The frame length is determined by the information field, and length of the FCS field is 24-bit. Generation of the frame check sequence is very similar to the CRC coding in baseband signal processing. ETSI GSM specifications 04.22 and 04.64 both define the coding rule. The coding rules are: The CRC shall be ones complement of the modulo-2 sum of: 1. z the remainder of xkx(x23+x22+x21+…+x2+x+1) modulo-2 divided by the generator polynomial, where k is the number of bits of the dividend. (i.e. fill the shift registers with all ones initially before feeding data) z the remainder of the modulo-2 division by the generator polynomial of the product of x24 by the dividend, which are the information bits. The CRC-24 generator polynomial is: 2. G(x)=x24+x23+x21+x20+x19+x17+x16+x15+x13+x8+x7+x5+x4+x2+1 The 24-bit CRC are appended to the data bits in the MSB-first manner. 3. 4. Decoding is identical to encoding except that data fed into the syndrome circuit is 24-bit longer than the information bits at encoding. The dividend is also multiplied by x24. If no error occurs, the remainder should satisfy R(x)=x22+x21+x19+x18+x16+x15+x11+x8+x5+x4 (0x6d8930) And the parity output word will be 0x9276cf. In contrast to conventional CRC, this special coding scheme makes the encoder fully identical to the decoder and simplifies the hardware design. 5.3.2 Register Definitions FCS+0000h Bit 15 Name D15 Type R/W THE DX FCS input data register 14 D14 R/W 12 D12 R/W 11 D11 R/W 10 D10 R/W 9 D9 R/W 8 D8 R/W 7 D7 R/W 6 D6 R/W 5 D5 R/W 4 D4 R/W 3 D3 R/W 2 D2 R/W 1 D1 R/W 0 D0 R/W data bits input. First write of this register is the starting point of the encode or decode process. X=0…15. The input format is D15·xn+ D14·xn-1+ D13·xn-2+ … + Dk·xk+ …, thus D15 is the first bit being pushed into the shift register. If the last data word is less than 16 bits, the rest bits are neglected. FCS+0004h Bit Name Type 13 D13 R/W FCS_DATA 15 Input data length indication register 14 13 12 11 10 9 8 7 FCS_DLEN 6 5 4 3 2 1 0 LEN WO 246/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 THE LEN MCU specifies the total data length in bits to be encoded or decoded. The data length. A number of multiple-of-8 is required (Number_of_Bytes x 8) FCS+0x0008h FCS parity output register 1, MSB part Bit Name Type Reset 15 P15 RC 0 14 P14 RC 0 FCS+000Ch Bit Name Type Reset 15 14 13 P13 RC 0 12 P12 RC 0 11 P11 RC 0 10 P10 RC 0 9 P9 RC 0 8 P8 RC 0 7 P7 RC 0 FCS_PAR1 6 P6 RC 0 5 P5 RC 0 4 P4 RC 0 3 P3 RC 0 2 P2 RC 0 FCS parity output register 2, LSB part 13 12 11 10 9 8 7 P23 RC 0 1 P1 RC 0 0 P0 RC 0 FCS_PAR2 6 P22 RC 0 5 P21 RC 0 4 P20 RC 0 3 P19 RC 0 2 P18 RC 0 1 P17 RC 0 0 P16 RC 0 PARITY bits output. For FCS_PAR2, bit 8 to bit15 will be filled by zeros when reading. PX X=0…23. The output format is P23·D23+ P22·D22+ P21·D21+ … + Pk·Dk+ …+P1·D1+P0, thus P23 is the earliest bit being popped out from the shift register and first appended to the information bits. In other words, {FCS_PAR2[7:0], FCS_PAR1[15:8], FCS_PAR1[7:0] } is the order of appending parity to data. FCS+0010h Bit Name Type Reset 15 FCS codec status register 14 13 12 11 10 9 FCS_STAT 8 7 6 5 4 3 2 1 BUSY FER RC RC 0 1 0 RDY RC 0 BUSY Since the codec works in serial manner and the data word is input in parallel manner, BUSY = 1 indicates that current data word is being processed and write to FCS_DATA is invalid. BUSY = 0 allows write of FCS_DATA during encode or decode process. FER Frame error indication, only for decode mode. FER = 0 means no error occurs and FER = 1 means the parity check has failed. Write of FCS_RST.RST or first write of FCS_DATA will reset this bit to 0. RDY When RDY = 1, the encode or decode process has been finished. For encode, the parity data in FCS_PAR1 and FCS_PAR2 are correctly available. For decode, FCS_STAT.FER indication is valid. Write of FCS_RST.RST or first write of FCS_DATA will reset this bit to 0. FCS+0014h Bit 15 FCS codec reset register 14 13 12 11 10 9 FCS_RST 8 Name Type 7 6 5 4 3 2 EN_D PAR E WO WO 1 0 BIT RST WO WO RST = 0 resets the CRC coprocessor. Before setup of FCS codec, the MCU needs to set RST = 0 to flush the shift register content before encode or decode. BIT BIT = 0 means not to invert the bit order in a byte of data words when the codec is running. BIT = 1 means the bit order in a byte written in FCS_DATA should be reversed. PAR PAR = 0 means not to invert the bit order in a byte of parity words when the codec is running, include reading of FCS_PAR1 and FCS_PAR2. PAR = 1 means bit order of parity words should be reversed, in decoding or encoding. EN_DE EN_DE = 0 means encode; EN_DE = 1 means decode RST 247/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 5.4 GPRS Cipher Unit 5.4.1 General Description The unit implements the GPRS encryption/decryption scheme that accelerates the computation of encryption and decryption GPRS pattern. The block accelerates the computation of the key stream. However the bit-wise encryption/decryption of the data is still done by the MCU. Both GEA and GEA2 are supported. Register Address Register Function Acronym GCU+0000h GPRS Encryption Algorithm Control Register GCU_CON GCU+0004h GPRS Encryption Algorithm Status Register GCU_SAT GCU+0008h GPRS Secret Key Kc 0 Register GCU_SKEY0 GCU+000Ch GPRS Secret Key Kc 1 Register GCU_SKEY1 GCU+0010h GPRS Message Key Register GCU_MKEY GCU+0014h GPRS Ciphered Data Register GCU_CDATA Table 25 GCU Registers 5.4.2 Register Definitions GCU+0000h Bit Name Type Reset Bit Name Type Reset GPRS Encryption Algorithm Control Register GCU_CON 31 30 29 28 27 26 25 24 23 22 21 20 15 14 13 12 11 10 9 8 7 6 5 RBO R/W 0 4 KS R/W 10 19 18 3 2 SINIT WO 0 17 16 1 0 DIR GEA2 R/W R/W 0 0 This register controls the key generation function of the GPRS Encryption Algorithm. GEA2 DIR SINIT KS RBO Choose the encryption/decryption scheme. 1 = GEA2, while 0 = GEA. The DIRECTION input of the GPRS Encryption Algorithm. Start initialization. The MCU writes 1 to start initialization. The bit is always read at 0. Control the read access. 00 = byte access, 01 = half word (16 bits) access, 10 = word access, 11 reserved. Default value is 10. Reversal Byte Order bit. If the bit was set to 1, the byte order of GCU_SKEY0, GCU_SKEY1, GCU_MKEY in write operation and GCU_SKEY0, GCU_SKEY1, GCU_MKEY, GCU_CDATA in read operation would be the reverse of baseband processor, and if the bit was 0, the behavior would be the same as baseband processor. Byte-order of GCU_CON and GCU_SAT is not affected. The default value is 0 which is different from that in MT6217. 248/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 GCU+0004h Bit Name Type Reset Bit GPRS Encryption Algorithm Status Register GCU_SAT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 KEY_ COM RO 0 1 0 Name STAT Type Reset RO 110 INIT RO 0 This register shows the status of the GPRS Encryption unit. INIT Initialization flag. 1 = the GCU is currently performing the initialization phase. KEY_COM Key-stream computation. 1 = the GCU is computing new key stream, while 0 = a new key is available or the GCU is in initialization phase. STAT The state of GCU core. For debug purpose. GCU+0008h Bit Name Type Reset Bit Name Type Reset 31 30 29 28 27 26 25 15 14 13 12 11 10 9 GCU+000Ch Bit Name Type Reset Bit Name Type Reset GPRS Secret Key Kc 0 Register 24 23 KC[31:16] R/W 0 8 7 KC[15:0] R/W 0 GCU_SKEY0 22 21 20 19 18 17 16 6 5 4 3 2 1 0 GPRS Secret Key Kc 1 Register 31 30 29 28 27 26 25 15 14 13 12 11 10 9 24 23 KC[63:48] R/W 0 8 7 KC[47:32] R/W 0 GCU_SKEY1 22 21 20 19 18 17 16 6 5 4 3 2 1 0 This set of registers shall be programmed with the GPRS Encryption Algorithm secret key. GCU+0010h Bit Name Type Reset Bit Name Type Reset GPRS Message Key Register 31 30 29 28 27 26 25 15 14 13 12 11 10 9 24 23 MKEY[31:16] R/W 0 8 7 MKEY[15:0] R/W 0 GCU_MKEY 22 21 20 19 18 17 16 6 5 4 3 2 1 0 This register shall be programmed with the “message key” for the GPRS Encryption Algorithm. 249/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 GCU+0014h Bit Name Type Bit Name Type GPRS Ciphered DATA Register 31 30 29 28 27 26 25 15 14 13 12 11 10 9 24 23 CDATA[31:16] RO 8 7 CDATA[15:0] RO GCU_CDATA 22 21 20 19 18 17 16 6 5 4 3 2 1 0 The register contains the key stream. GCU will continue to generate next word of key while current word of key is removed. 250/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 251/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 6 MCU/DSP Interface MCU/DSP Interface resides between the Microcontroller Unit Subsystem and the Digital Signal Processor Subsystem. It serves as the command and data exchange medium by which the MCU and the DSP communicate with each other. As shown in Figure 29, MCU/DSP Interface is composed of three parts, namely: z MCU/DSP Shared Registers, which are used for hardware controls and status signaling; z MCU/DSP Shared RAM, where software of both sides exchange commands and data; z AHB-to-DDMA Bridge, which translates AHB cycles to the DSP’s Internal DMA cycles and allows an AHB master to access the memory of the DSP. On the MCU Subsystem side, MCU/DSP Shared Registers are connected to APB, while MCU/DSP Shared RAM and AHB-to-DDMA Bridge are connected to AHB. Therefore, MCU/DSP Shared Registers are allocated an APB address space, whereas MCU/DSP Shared RAM and AHB-to-DDMA Bridge are mapped to AHB pages. On the DSP Subsystem side, MCU/DSP Shared RAM and most MCU/DSP Shared Registers are attached to the DSP I/O bus through DSP I/O Hub. Cont rols I/O Bus DSP Int errupt s I/O Hub I DM A M C U/ DSP Shared Regist ers M C U/ DSP Shar ed RA M Interrupt APB APB Br idge M CU AHB AHB-to-DDMA Bridge Figure 29 MCU/DSP Interface block diagram. Referring to Figure 1, the 640 16-bit words of MCU/DSP Shared RAM are allocated to the beginning of the AHB page at 50000000h for master DSP and at 58000000h for slave DSP. This memory can be accessed in 16-bit half-words or 8-bit bytes by an AHB master, but not in 32-bit words. The AHB pages beginning from 60000000h and from 68000000h are devoted to AHB-to-DDMA Bridges of the master and slave DSP, which link DSP memories to AHB like AHB slaves. Specifically, the master DSP Code Memory, Program Memory and Data Memory are mapped to the 1M-byte areas starting at 60000000h, 60100000h and 60200000h, respectively (or 68000000h, 68100000h, and 68200000h for slave DSP). Each 1M-byte area is evenly partitioned to sixteen 64K-byte blocks corresponding to the 16 pages of one type of DSP memory. Because CM is 24-bit wide, its word is zero extended to 32 bits over AHB and thus must be accessed in 32-bit words. PM and DM are both 16-bit wide, thus shall be accessed in half-words (16-bit). Moreover, the PM data are protected when written through IDMA of slave DSP. Correspondingly, L1 should prepare the PM data by specific encryption method in advance, and the hardware should take responsibility of decryption before writing them into PM RAM through IDMA. The following block diagram depicts the relation. 252/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 ecryption PM data L1 XOR pm_e_mess AHB-to-IDMA bridge PM_XOR_MASK decryption PM RAM XOR pm_d_mess Figure 30 PM data encryption/decryption 6FFFFFFFh FFFFh Reserved 60320000h 6031FFFFh 60310000h DSP DDMAShort Read/Write Page 64 KBytes DSP DDMALong Read/Write Page 64 KBytes 6030FFFFh 60300000h Reserved 16384 Words x 16 Bits 8000h DSP Data Memory Page 15 64 KBytes 602FFFFFh 602F0000h DSP Data Memory Page 0 64 KBytes 6020FFFFh 60200000h DSP Program Memory Page 15 64 KBytes 601FFFFFh 601F0000h 7FFFh DSP Data Memory Page 16384 Words x 16 Bits 0000h FFFFh Reserved 16384 Words x 16 Bits 8000h 7FFFh 60100000h 600F0000h DSP Program Memory Page 0 64 KBytes 6010FFFFh DSP Code Memory Page 15 64 KBytes 600FFFFFh DSP Program Memory Page 16384 Words x 16 Bits 0000h DSP Code Memory Page 16384 Words x 32 Bits 60000000h DSP Code Memory Page 0 64 KBytes 6000FFFFh MCU Bytes Reserved 50000000h MCU/DSP Shared RAM 352 x 16-bit MSB 3 DSP Code Word 500002BFh 2 1 23:16 15:8 FFFFh LSB 0 7:0 0000h Figure 3 Mapping of MCU/Master DSP Interface on the MCU memory space. For the MCU/Slave DSP Interface, the difference is 08000000h base address offset at MCU side only. 253/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 6FFFFFFFh Reserved FFFFh 68320000h 6831FFFFh 68310000h DSP DDMAShort Read/WritePage 64 KBytes 6830FFFFh 68300000h DSP DDMALongRead/WritePage 64 KBytes Reserved 16384 Words x 16 Bits 8000h DSPData Memory Page15 64 KBytes 682FFFFFh 682F0000h DSPDataMemory Page0 64 KBytes 6820FFFFh 68200000h 681FFFFFh 681F0000h DSP ProgramMemory Page15 64 KBytes 7FFFh DSP Data Memory Page 16384 Words x 16 Bits 0000h FFFFh Reserved 16384 Words x 16 Bits 8000h 7FFFh 6810FFFFh 68100000h DSPProgramMemory Page0 64 KBytes 680FFFFFh 680F0000h DSPCodeMemory Page15 64 KBytes DSP ProgramMemory Page 16384 Words x 16 Bits 0000h DSPCodeMemory Page 16384 Words x 32 Bits 68000000h DSPCodeMemory Page0 64 KBytes 6800FFFFh MCUBytes Reserved 58000000h MCU/DSP Shared RAM 688 x 16-bit MSB 3 DSPCodeWord 5800055Fh 2 1 23:16 15:8 FFFFh LSB 0 7:0 0000h Figure 31 Mapping of MCU/Slave DSP Interface on the MCU memory space. For the MCU/Master DSP Interface, the difference is 08000000h base address offset at MCU side only 6.1 6.1.1 MCU/DSP Shared Registers General Description MCU/DSP Shared Registers are a set of registers that are accessible by both the MCU and the DSP for z the control of the DSP hardware, such as reset and power-down; z the identification of the ongoing DSP tasks, 254/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 z the recognition of the DSP to MCU Interrupt, which informs the MCU of certain events happening in the DSP side; z the generation of the MCU to DSP Interrupt, by which the MCU sends commands and messages to the DSP; z TDMA frame counts, which are referenced by the software for TDMA timing and are employed by GSM Cipher Coprocessor in generating ciphering keys. Functionalities of MCU/DSP Shared Registers are hardwired, which is different from MCU/DSP Shared RAM whose usage is software-defined. 6.1.2 Register Definitions Table 26 and Table2 list MCU/DSP Shared Registers and their address mapping to the MCU address space and DSP I/O space. The MCU register addresses are the offsets from the base address 80300000h for master DSP (DSP1) and 80320000h for slave DSP (DSP2) on APB bus. MCU Register Address DSP Register Address Register Function Acronym 0000h N/A DSP1 Control Register SHARE_DSP1CTL 0004h 601h MCU-to-DSP1 Interrupt 1 Register SHARE_M2D1I1 0008h 602h MCU-to-DSP1 Interrupt 2 Register SHARE_M2D1I2 000Ch N/A DSP1-to-MCU Interrupt Control Register SHARE_D12MCTL 0010h N/A DSP1-to-MCU Interrupt Status Register SHARE_D12MSTA 0014h 605h DSP1 Task Identification Register SHARE_D12MTID 0018h 606h TDMA Counter Enable Register SHARE_1TDMAEN 001Ch 607h TDMA T1 Counter SHARE_1TDMAT1 0020h 608h TDMA T2 Counter SHARE_1TDMAT2 0024h 608h TDMA T3 Counter SHARE_1TDMAT3 0028h 60Ah DSP1 Debugging Control SHARE_DSP1DBG 0030h N/A DSP1 Task 1 Time Out SHARE_DSP1T1TO 0034h N/A DSP1 Task 2 Time Out SHARE_DSP1T2TO N/A 60Bh DSP power-down source SHREG_1PWDNSRC 0048h 60Ch DSP self power-down control SHARE_1PWDNCON N/A 60Dh DSP PC SHREG_D1PC N/A 60Eh DSP CNTR SHREG_D1CNTR 004Ch N/A DSP slow-idle mode switch SHARE_DSP1CKR Table 26 MCU/DSP1 Shared Registers MCU Register Address DSP Register Address Register Function Acronym 0000h N/A DSP2 Control Register SHARE_DSP2CTL 255/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 0004h 601h MCU-to-DSP2 Interrupt 1 Register SHARE_M2D2I1 0008h 602h MCU-to-DSP2 Interrupt 2 Register SHARE_M2D2I2 000Ch N/A DSP2-to-MCU Interrupt Control Register SHARE_D22MCTL 0010h N/A DSP2-to-MCU Interrupt Status Register SHARE_D22MSTA 0014h 605h DSP2 Task Identification Register SHARE_D22MTID 0018h 606h TDMA Counter Enable Register SHARE_2TDMAEN 001Ch 607h TDMA T1 Counter SHARE_2TDMAT1 0020h 608h TDMA T2 Counter SHARE_2TDMAT2 0024h 608h TDMA T3 Counter SHARE_2TDMAT3 0028h 60Ah DSP2 Debugging Control SHARE_DSP2DBG 002Ch N/A DSP2 Task 0 Time Out SHARE_DSP2T0TO 0030h N/A DSP2 Task 1 Time Out SHARE_DSP2T1TO 0034h N/A DSP2 Task 2 Time Out SHARE_DSP2T2TO 0038h N/A DSP2 Task 3 Time Out SHARE_DSP2T3TO 003Ch N/A DSP2 Task 4 Time Out SHARE_DSP2T4TO N/A 60Bh DSP power-down source SHREG_2PWDNSRC 0048h 60Ch DSP self power-down control SHARE_2PWDNCON N/A 60Dh DSP PC SHREG_D1PC N/A 60Eh DSP CNTR SHREG_D1CNTR 004Ch N/A DSP slow-idle mode switch SHARE_DSP2CKR Table 2 MCU/DSP2 Shared Registers +0000hMCU Bit 15 14 DSP1 CONTROL REGISTER N/ADSP 13 12 11 10 9 8 Name Type Reset 7 6 5 4 3 2 1 0 PWDA PWDN BOOT RSTN CK R R/W R/W R/W 0 1 1 0 This register directly controls the DSP signals: RSTn, BMODE, and PWDn. After the hardware reset, the RSTN bit and BOOT bit are reset to 0 and 1, respectively, thus keeping the DSP in reset state with BMODE = 1. The MCU shall then write 1 to RSTN to end the reset and to start booting of the DSP. Only bit 0 is accessible by DSP, by which DSP can learn how it is reset, whether by MCU (RSTN = 1) or due to DSP-code crazy execution. Therefore after normal DSP booting sequence from MCU, DSP code should read back the RSTN bit before entering any task. PWDACK DSP power-down mode acknowledgement. This bit is read true when the DSP enter the IDLE state. PWDN DSP power-down control. This bit is connected to the PWDN pin of the DSP. A 1-to-0 transition of this bit causes the DSP to enter power-down mode, while a 0-to-1 transition of this bit wakes the DSP. BOOT DSP boot mode. This bit is connected to the BMODE pin of the DSP. If BMODE is 1 when RSTn transit from 0 to 1, the DSP will enter the boot mode waiting for the completion of its program download. 256/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 RSTN DSP reset. This bit controls the RSTn input of the DSP. 0 Reset DSP. +0000hMCU Bit 15 14 DSP2 CONTROL REGISTER N/ADSP 13 12 11 10 9 8 7 6 5 4 Name Type Reset 3 2 1 0 PWDA PWDN BOOT RSTN CK R R/W R/W R/W 0 1 1 1 This register resides at slave DSP side with the same function with SHARE_DSP1CTL. However, since slave DSP should be reset from DSP1, therefore RSTN of SHARE_DSP2CTL has to be initialized to be bit 0. Only bit 0 is accessible by DSP, by which DSP can learn how it is reset, whether by MCU (RSTN = 1) or due to DSP-code crazy execution. Therefore after normal DSP booting sequence from MCU, DSP code should read back the RSTN bit before entering any task. +0004hMCU Bit Name Type 15 14 MCU-TO-DSP1 INTERRUPT 1 REGISTER 601hDSP 13 12 11 10 9 8 7 6 INTERRUPT LABEL R/W 5 4 3 2 1 0 This register is written by the MCU to generate an interrupt request to the DSP. The generated interrupt shall have a higher priority in the DSP side so that it can be serviced regardless of the status of DSP tasks. Contents of the register have no hardware significance but shall be referenced by the MCU and DSP as the reason for the interrupt. +0008hMCU Bit Name Type 15 14 MCU-TO-DSP1 INTERRUPT 2 REGISTER 602hDSP 13 12 11 10 9 8 7 6 INTERRUPT LABEL R/W 5 4 3 2 1 0 This register is written by the MCU to generate an interrupt request to the DSP. The generated interrupt should have a lower priority in the DSP side; therefore it may or may not be serviced immediately, depending on the status of DSP tasks. Contents of the register have no hardware significance but shall be referenced by the MCU and DSP as the reason for the interrupt. +000ChMCU Bit 15 14 DSP1-TO-MCU INTERRUPT CONTROL REGISTER N/ADSP 13 12 11 10 9 8 257/599 7 6 5 4 3 2 1 0 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 TASK TASK TASK TASK TASK TASK TASK TASK 7 6 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Name Type Reset This register is programmed by the MCU to enable or disable the task interrupts asserted by the DSP. The interrupt for Task X is asserted when TASKX is set and the MCU/DSP Shared RAM word at address X is written by the DSP. TASKX Task Interrupt X Enable. 0 Disable the interrupt for Task X. 1 Enable the interrupt for Task X. +0010hMCU Bit 15 14 DSP1-TO-MCU INTERRUPT STATUS REGISTER N/ADSP 13 12 11 10 9 8 Name Type Reset 7 6 5 4 3 2 1 0 TASK TASK TASK TASK TASK TASK TASK TASK 7 6 5 4 3 2 1 0 RC RC RC RC RC RC RC RC 0 0 0 0 0 0 0 0 Bits of this register are set by the DSP to assert an interrupt to the MCU. When the DSP writes to the word address X in MCU/DSP Shared RAM, the corresponding TASKX bit is set in this register. An MCU interrupt will be generated if TASKX is not masked in SHARE_D1MCTL. To acknowledge the interrupt, the MCU shall read this register for the interrupt status. After the read the interrupt flags will be cleared so that new Task Interrupts can be generated. TASKX Task X Interrupt flag. 0 Task X Interrupt has not been asserted. 1 Task X Interrupt has been asserted. +0014hMCU Bit Name Type 15 14 DSP1 TASK IDENTIFICATIO N REGISTER 605hDSP 13 12 11 10 9 8 7 6 5 4 3 2 1 TASK IDENTIFICATION CODE R 0 This register is used by the DSP software posting its task status to the MCU. Contents of the register are observable as debug signals. +0018hMCU Bit Name Type 15 14 TDMA COUNTER ENABLE REGISTER 606hDSP 13 12 11 10 9 8 258/599 7 6 5 4 3 2 1 0 T3EN T2EN T1EN R/W R/W R/W MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 This register is programmed by the MCU software to enable or disable the TDMA frame counter (T1, T2, T3) Shared Registers. Contents of T1, T2 and T3 are referenced by the GSM Cipher Coprocessor for key generations. T3EN T2EN T1EN T3 counter enable. 0 Disable SHARE_TDMAT3 counting so that it will not be updated by DTIRQ. 1 Enable SHARE_TDMAT3 counting so that it will be updated by DTIRQ. T2 counter enable. 0 = disable, 1 = enable. 0 Disable SHARE_TDMAT2 counting so that it will not be updated by DTIRQ. 1 Enable SHARE_TDMAT2 counting so that it will be updated by DTIRQ. T1 counter enable. 0 = disable, 1 = enable. 0 Disable SHARE_TDMAT1 counting so that it will not be updated by DTIRQ. 1 Enable SHARE_TDMAT1 counting so that it will be updated by DTIRQ. +001ChMCU Bit Name Type 15 14 607hDSP 13 12 T1 COUNTER 11 10 9 8 7 6 5 T1 R/W 4 3 2 1 0 This register is the T1 part of the reduced TDMA frame number (RFN), i.e., T1 = TDMA frame number div (26 × 51). At the asserting edge of the TDMA Frame Interrupt for DSP (DTIRQ), if the MCU has written to this register in advance, T1 will be initialized to the written value. Otherwise T1 will be incremented by 1 if T2 = 25, T3 = 50 and T1EN = T2EN = T3EN = 1. +0020hMCU Bit Name Type 15 14 608hDSP 13 12 T2 COUNTER 11 10 9 8 7 6 5 4 3 2 T2 R/W 1 0 This register is the T2 part of the reduced TDMA frame number, i.e., T2 = TDMA frame number modulo 26. At the asserting edge of DTIRQ, if the MCU has written to this register in advance, T2 will be initialized to the written value. Otherwise T2 will be incremented by 1 modulo 26 if T2EN = 1. +0024hMCU Bit Name Type 15 14 609hDSP 13 12 T3 COUNTER 11 10 9 8 7 6 5 4 3 2 1 0 T3 R/W This register is the T3 count for calculating T3′ of the reduced TDMA frame number. Specifically, T3 = TDMA frame number modulo 51. At the asserting edge of DTIRQ, if the MCU has written to this register in advance, T3 will be initialized to the written value. Otherwise T3 will be incremented by 1 modulo 51 if T3EN = 1. 259/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 +0048hMCU Bit 15 SELF Name _PWD NEN Type R/W 14 DSP SELF POWER-DOWN CONTROL 60ChDSP 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DSP_CNTR_WORD R/W SEL_PWDNEN self power-down enable, programmed by MCU to enable the DSP self power-down mechanism through CNTR internal register. 0 disable 1 enable DSP_CNTR_WORD programmed by MCU to indicate the upper bound of CNTR value +004ChMCU Bit Name Type Reset 15 14 SHARE_DSP1C KR N/ADSP 13 12 11 10 9 8 7 6 5 4 3 2 HOST_DEEP_CKR R/W 0 1 0 DEEP_CKR To further saving host DSP power dissipation, the traditional CKR (DSP clock divider ratio for slow IDLE mode) is split to two selections. One is for deep-sleep control, as configured by this register; the other is for shallow sleep, which is programmed through SHRAM as before. Whenever RX frames assert, the CKR switch from HOST_DEEP_CKR to another accordingly. +004ChMCU Bit Name Type Reset 15 14 SHARE_DSP2C KR N/ADSP 13 12 11 10 9 8 7 6 5 4 3 2 SLAVE_DEEP_CKR R/W 0 1 0 DEEP_CKR To further saving slave DSP power dissipation, the traditional CKR (DSP clock divider ratio for slow IDLE mode) is split to two selections. One is for deep-sleep control, as configured by this register; the other is for shallow sleep, which is programmed through SHRAM as before. Whenever TX frames assert, the CKR switch from SLAVE_DEEP_CKR to another accordingly. 260/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 N/AMCU Bit 15 DSP POWER-DOWN SOURCE 60BhDSP 14 13 12 11 10 9 8 7 6 5 4 3 2 Name Type Reset 1 0 DSP_ HW_P PWDN WDN RO RO 0 0 This register is used to indicate the power-down source comes either from HW or DSP self. The signal is active high. And the HW_PWDN includes the effect of MCU power-down (write through SHARE_DSPCTL), trap indicator (see the spec. of patch unit), timeout indication (debug unit in sherif), and stack error. N/AMCU Bit Name Type Reset 15 60DhDSP 14 N/AMCU Bit Name Type Reset 6.2 6.2.1 15 13 12 SHREG_DXPC 11 10 9 8 7 DSP_PC R/W 0 6 5 4 3 13 12 1 0 SHREG_DXCNT R 60EhDSP 14 2 11 10 9 8 7 DSP_CNTR R/W 0 6 5 4 3 2 1 0 MCU/DSP Shared RAM General Description This is a 640 words × 16 bits dual-port static RAM that is accessible by both the MCU and the DSP. It serves as the command and data exchange medium between the two processors. Except for some MCU/DSP Shared RAM words that trigger interrupts, the software can allocate the memory for whatever purposes, such as z Speech algorithm control parameters, z Software task control parameters, z Downlink channel processing results, z Downlink channel data buffers, and z Uplink channel data buffers. 261/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 The first eight MCU/DSP Shared RAM words are used for DSP event reports. When the DSP writes to one of these words, a respective bit will be set in the SHARE_D2MSTA register and the DSP-to-MCU Interrupt will be asserted. Then the MCU may read the MCU/DSP Shared RAM word to see the reason for the interrupt. MCU/DSP Shared RAM can be accessed by the MCU in halfwords (16 bits) or bytes, but not in words (32 bits). Simultaneous accesses from the MCU and the DSP are allowed, but simultaneous writes from both sides to the same word should be avoided by the software as the word content would be undefined. 6.2.2 MCU/DSP Shared RAM Utilizations Table3 and Table4 are the utilization of MCU/DSP Shared RAM, whose base address in the MCU side is 50000000h for DSP1 and 58000000h for DSP2. MCU Address DSP I/O Address Acronym Description 0000h 0000h DP_D12M_TASK0 First DSP task interrupt. 0002h 0001h DP_D12M_TASK1 Second DSP task interrupt. 0004h 0002h DP_D12M_TASK2 Third DSP task interrupt. 0006h 0003h DP_D12M_TASK3 Fourth DSP task interrupt. 0008h 0004h DP_D12M_TASK4 Fifth DSP task interrupt. 000Ah 0005h DP_D12M_TASK5 Sixth DSP task interrupt. 000Ch 0006h DP_D12M_TASK6 Seventh DSP task interrupt. 000Eh 0007h DP_D12M_TASK7 Eighth DSP task interrupt. 0010h | 02BFh 0008h | 014Fh N/A Software defined. Table 3 MCU/DSP1 Shared RAM utilizations. MCU Address DSP I/O Address Acronym Description 0000h 0000h DP_D22M_TASK0 First DSP task interrupt. 0002h 0001h DP_D22M_TASK1 Second DSP task interrupt. 0004h 0002h DP_D22M_TASK2 Third DSP task interrupt. 0006h 0003h DP_D22M_TASK3 Fourth DSP task interrupt. 0008h 0004h DP_D22M_TASK4 Fifth DSP task interrupt. 000Ah 0005h DP_D22M_TASK5 Sixth DSP task interrupt. 000Ch 0006h DP_D22M_TASK6 Seventh DSP task interrupt. 000Eh 0007h DP_D22M_TASK7 Eighth DSP task interrupt. 0010h | 055Fh 0008h | 02B0h N/A Software defined. Table 4 MCU/DSP2 Shared RAM utilizations. 262/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 6.3 6.3.1 AHB-to-DDMA Bridge General Description AHB-to-DDMA Bridge links the AHB to the DSP DDMA port, which allows an external host to read from or write to the DSP memory directly, so the AHB masters, i.e., the MCU and the AHB DMA Controller, can access the DSP program and data memory without interrupting the DSP. This capability is useful in z DSP Program downloading or uploading, z DSP Data exchange, and z DSP booting. Referring to Figure 3, AHB-to-DDMA Bridge works in the AHB memory space beginning from 60000000h to 67FFFFFFh for DSP1 and from 68000000h to 6FFFFFFFh for DSP2. As for the memory mapping on AHB bus, MCU/DSP1and MCU/DSP2 interfaces differ in nothing more than the base address, therefore the following description is illustrated by DSP1 case only. The DSP Program Code Memory space comprising of sixteen 16384 × 24-bit pages is mapped to the AHB region from 60000000h to 600FFFFFh. The region further consists of sixteen 65536-byte blocks corresponding to the sixteen DSP Program Code overlay pages, whose data words are transferred to or from AHB as 32-bit words. The second 1M-byte AHB region from 60100000h to 601FFFFFh is mapped to the sixteen 16384 × 16-bit DSP Program Data Memory pages. Again the region is partitioned to sixteen 65536-byte blocks. In each block the lower 32768 bytes are mapped to one DSP Program Data overlay page and the upper 32768 bytes are reserved. Data in this region shall be accessed as halfwords over AHB. The third 1M-byte AHB region from 60200000h to 602FFFFFh is mapped to the sixteen 16384 × 16-bit DSP Data Memory pages. The region is also partitioned to sixteen 65536-byte blocks, whose lower halves correspond to the sixteen DSP Data Memory overlay pages. Data in this region shall be accessed as halfwords over AHB. Access to the above three regions are converted to the DSP DDMA cycles carrying data and address information, thus are called addressed DDMA cycles. The inclusion of address information enables random access at the expense of lower transfer rate. For sequential read or write to the DSP memory, a more efficient way would be to provide address information for the very first data transfer, and then rely on the auto-incrementing DDMA address register in the DSP core to provide addresses of the rest of the data transfers. This way, the transfer rate can be improved as address information is not converted every time. Contrary to the addressed DDMA cycles produced by AHB accessing 6000000h to 602FFFFFh, the DDMA Short Read/Write port (0x60310000 ~ 0x6031FFFF) may be used. This port relies on the DDMA address maintained within the DSP core, thus generates no address latching cycles when they are accessed. Whenever a DDMA read/write is completed, the DSP increments the internal DDMA address by one, so the next word can be accessed readily. Therefore, to access a DSP memory block, only the first word needs to be accessed with an explicitly addressed DDMA cycle. All the other words can be read or written through the Long or Short DDMA port. An AHB-to-DDMA access will sometimes introduce wait states on AHB by toggling idma_hready. For write operations, if throttle control is carefully executed (i.e., two DDMA transfers are expanded by enough cycles that the first transaction has enough time to complete), idma_hready will never be toggled. For read operations, things are different in address mode access and short mode access. For address mode, idma_hready always toggles until the read transaction is completed. In 263/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 short mode, since the actual read data is fetched at the previous transaction, idma_hready will not be toggled unless the consecutive request comes too soon. The Short DDMA ports shall be accessed in words if the DSP Program Code memory is targeted; or in half-words if the DSP Program Data or DSP Data memory is targeted. During DSP booting, the DSP program execution is held off until the DDMA writes to the Program Code Memory address zero. Therefore, MCU software should load all necessary DSP memory locations with proper code/data before writing to the DSP Program Code Memory address 0, which is mapped to MCU address 0x60000000. As for the PM encryption/decryption, the PM_XOR_MASK is 0xBF96, and the following table can describe the encryption Before encryption After encryption pm_data[0] pm_e_data[13] pm_data[1] pm_e_data[4] pm_data[2] pm_e_data[15] pm_data[3] pm_e_data[1] pm_data[4] pm_e_data[12] pm_data[5] pm_e_data[3] pm_data[6] pm_e_data[8] pm_data[7] pm_e_data[0] pm_data[8] pm_e_data[9] pm_data[9] pm_e_data[11] pm_data[10] pm_e_data[5] pm_data[11] pm_e_data[10] pm_data[12] pm_e_data[6] pm_data[13] pm_e_data[7] pm_data[14] pm_e_data[2] pm_data[15] pm_e_data[14] Table 5 PM encription 6.3.2 Register Definitions 60310000h Bit Name Type 15 DDMA Short Read/Write Port 14 13 12 11 10 9 8 7 DDMA_SHORT R/W DDMA_SHORT 6 5 4 3 2 1 0 This is the read/write port for AHB-to-DDMA data access using short DDMA cycles. When this port is read, an DDMA read cycle is sent to the DSP, which returns the content of DDMA data buffer to AHB via AHB-to-DDMA Bridge, then reads a specific location in its memory and puts the read data into the DDMA data buffer. When this port is written, a DDMA write cycle is sent to the DSP, which writes the AHB data to a specific location in its memory. Meanwhile, another AHB transaction can be proceeding. 264/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 For CM transfers, bits 0 to 23 contain the data word. For PM or DM transfers, only bits 0 to 15 are used. The unused bits have undefined values if read. 265/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 266/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 267/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 7 Multi-Media Subsystem MT6235 is specially designed to support multi-media terminals. It integrates several hardware based accelerators, like advanced LCD display controller and hardware Image Resizer. Besides, MT6235 also incorporates NAND Flash, USB 2.0 Device and SD/MMC/MS/MS Pro Controllers for massive data transfers and storages. This chapter describes those functional blocks in detail. 7.1 LCD Interface 7.1.1 General Description MT6235 contains a versatile LCD controller which is optimized for multimedia applications. This controller supports many types of LCD modules and contains a rich feature set to enhance the functionality. These features are: z Up to 320 x 240 resolution z The internal frame buffer supports 8bpp indexed color, RGB 565, RGB 888 and ARGB 8888 format. z Supports 8-bpp (RGB332), 12-bpp (RGB444), 16-bpp (RGB565), 18-bit (RGB666) and 24-bit (RGB888) LCD modules. z 6 Layers Overlay with individual color depth, window size, vertical and horizontal offset, source key, alpha value and display rotation control(90°,180°, 270°, mirror and mirror then 90°, 180° and 270°) z One Color Look-Up Table z Three Gamma Correction Tables For parallel LCD modules, the LCD controller can reuse external memory interface or use dedicated 8/9/16/18-bit parallel interface to access them and 8080 type interface is supported. It can transfer the display data from the internal SRAM or external SRAM/Flash Memory to the off-chip LCD modules. For serial LCD modules, this interface performs parallel to serial conversion and both 8- and 9- bit serial interface is supported. The 8-bit serial interface uses four pins – LSCE#, LSDA, LSCK and LSA0 – to enter commands and data. Meanwhile, the 9-bit serial interface uses three pins – LSCE#, LSDA and LSCK – for the same purpose. Data read is not available with the serial interface and data entered must be 8 bits. 268/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 LPCE0# LPCE1# LRST# LRD# LPA0 LWR# NLD[17:0] LSCE0# LSCE1# LSDA LSA0 LSCK Layer 0 Controller Parallel LCD Channel Controller Layer 1 Controller Layer 2 Controller Overlay Serial LCD Channel Controller Layer 3 Controller Layer 4 Controller Layer 5 Controller LCD AHB Master AHB BUS LUT Figure 32 LCD Interface Block Diagram Figure 33 shows the timing diagram of this serial interface. When the block is idle, LSCK is forced LOW and LSCE# is forced HIGH. Once the data register contains data and the interface is enabled, LSCE# is pulled LOW and remain LOW for the duration of the transmission. 8-bit Serial Interface LSCK(SPH=SPO=0) LSDA D7 D6 D5 D4 D3 D2 D1 D0 A0 D7 D6 D5 D4 D3 D2 D1 LSCE# LSA0 9-bit Serial Interface LSCK(SPH=SPO=0) LSDA D0 LSCE# LSA0 Figure 33 LCD Interface Transfer Timing Diagram LCD = 0x9000_0000 269/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 Address Register Function Width Acronym LCD + 0000h LCD Interface Status Register 16 LCD_STA LCD + 0004h LCD Interface Interrupt Enable Register 16 LCD_INTEN LCD + 0008h LCD Interface Interrupt Status Register 16 LCD_INTSTA LCD + 000ch LCD Interface Frame Transfer Register 16 LCD_START LCD + 0010h LCD Parallel/Serial LCM Reset Register 16 LCD_RSTB LCD + 0014h LCD Serial Interface Configuration Register 16 LCD_SCNF LCD + 0018h LCD Parallel Interface 0 Configuration Register 32 LCD_PCNF0 LCD + 001ch LCD Parallel Interface 1 Configuration Register 32 LCD_PCNF1 LCD + 0020h LCD Parallel Interface 2 Configuration Register 32 LCD_PCNF2 LCD + 0024h LCD Tearing Control Register 32 LCD_TECON LCD + 0040h LCD Main Window Size Register 32 LCD_MWINSIZE LCD + 0044h LCD ROI Window Write to Memory Offset Register 32 LCD_WROI_W2MOFS LCD + 0048h LCD ROI Window Write to Memory Control Register 24 LCD_WROI_W2MCON LCD + 004ch LCD ROI Window Write to Memory Address Register 32 LCD_WROI_W2MADD LCD + 0050h LCD ROI Window Control Register 32 LCD_WROICON LCD + 0054h LCD ROI Window Offset Register 32 LCD_WROIOFS LCD + 0058h LCD ROI Window Command Start Address Register 16 LCD_WROICADD LCD + 005ch LCD ROI Window Data Start Address Register 16 LCD_WROIDADD LCD + 0060h LCD ROI Window Size Register 32 LCD_WROISIZE LCD + 0064h LCD ROI Window Hardware Refresh Register 32 LCD_WROI_HWREF LCD + 0068h LCD ROI Window Background Color Register 32 LCD_WROI_BGCLR LCD + 0070h LCD Layer 0 Window Control Register 32 LCD_L0WINCON LCD + 0074h LCD Layer 0 Source Color Key Register 32 LCD_L0WINSKEY LCD + 0078h LCD Layer 0 Window Display Offset Register 32 LCD_L0WINOFS LCD + 007ch LCD Layer 0 Window Display Start Address Register 32 LCD_L0WINADD LCD + 0080h LCD Layer 0 Window Size 32 LCD_L0WINSIZE LCD + 0090h LCD Layer 1 Window Control Register 32 LCD_L1WINCON LCD + 0094h LCD Layer 1 Source Color Key Register 32 LCD_L1WINSKEY LCD + 0098h LCD Layer 1 Window Display Offset Register 32 LCD_L1WINOFS LCD + 009ch LCD Layer 1 Window Display Start Address Register 32 LCD_L1WINADD LCD + 00a0h LCD Layer 1 Window Size 32 LCD_L1WINSIZE LCD + 00b0h LCD Layer 2 Window Control Register 32 LCD_L2WINCON LCD + 00b4h LCD Layer 2 Source Color Key Register 32 LCD_L2WINSKEY LCD + 00b8h LCD Layer 2 Window Display Offset Register 32 LCD_L2WINOFS LCD + 00bch LCD Layer 2 Window Display Start Address Register 32 LCD_L2WINADD LCD + 00c0h LCD Layer 2 Window Size 32 LCD_L2WINSIZE LCD + 00d0h LCD Layer 3 Window Control Register 32 LCD_L3WINCON LCD + 00d4h LCD Layer 3 Source Color Key Register 32 LCD_L3WINSKEY 270/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 LCD + 00d8h LCD Layer 3 Window Display Offset Register 32 LCD_L3WINOFS LCD + 00dch LCD Layer 3 Window Display Start Address Register 32 LCD_L3WINADD LCD + 00e0h LCD Layer 3 Window Size 32 LCD_L3WINSIZE LCD + 00f0h LCD Layer 4 Window Control Register 32 LCD_L4WINCON LCD + 00f4h LCD Layer 4 Source Color Key Register 32 LCD_L4WINSKEY LCD + 00f8h LCD Layer 4 Window Display Offset Register 32 LCD_L4WINOFS LCD + 00fch LCD Layer 4 Window Display Start Address Register 32 LCD_L4WINADD LCD + 0100h LCD Layer 4 Window Size 32 LCD_L4WINSIZE LCD + 0110h LCD Layer 5 Window Control Register 32 LCD_L5WINCON LCD + 0114h LCD Layer 5 Source Color Key Register 32 LCD_L5WINSKEY LCD + 0118h LCD Layer 5 Window Display Offset Register 32 LCD_L5WINOFS LCD + 011ch LCD Layer 5 Window Display Start Address Register 32 LCD_L5WINADD LCD + 0120h LCD Layer 5 Window Size 32 LCD_L5WINSIZE LCD + 4000h LCD Parallel Interface 0 Data 32 LCD_PDAT0 LCD + 4100h LCD Parallel Interface 0 Command 32 LCD_PCMD0 LCD + 5000h LCD Parallel Interface 1 Data 32 LCD_PDAT1 LCD + 5100h LCD Parallel Interface 1 Command 32 LCD_PCMD1 LCD + 6000h LCD Parallel Interface 2 Data 32 LCD_PDAT2 LCD + 6100h LCD Parallel Interface 2 Command 32 LCD_PCMD2 LCD + 8000h LCD Serial Interface 1 Data 16 LCD_SDAT1 LCD + 8100h LCD Serial Interface 1 Command 16 LCD_SCMD1 LCD + 9000h LCD Serial Interface 0 Data 16 LCD_SDAT0 LCD + 9100h LCD Serial Interface 0 Command 16 LCD_SCMD0 LCD + c000h ~ c3fch LCD Gamma Correction LUT Register 32 LCD_GAMMA LCD + c400h ~ c7fch LCD Color Palette LUT Register 32 LCD_PAL LCD + c800h ~ c87c LCD Interface Command/Parameter0 Register 32 LCD_COMD0 LCD + c880h ~ c8fch LCD Interface Command/Parameter1 Register 32 LCD_COMD1 Table 27 Memory map of LCD Interface 7.1.2 Register Definitions LCD +0000h Bit 15 14 LCD Interface Status Register 13 12 11 10 9 8 Name Type Reset 271/599 LCD_STA 7 6 5 4 3 2 1 0 CMD_ DATA TE_P CPEN _PEN RUN END D D R/W R R R 0 0 0 0 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 RUN LCD Interface Running Status DATA_PEND Data Pending Indicator in Hardware Trigger Mode CMD_PEND Command Pending Indicator in Hardware Triggered Refresh Mode TE_PEND Frame update pending for tearing input LCD +0004h Bit 15 14 LCD Interface Interrupt Enable Register 13 12 11 10 9 8 7 6 LCD_INTEN 5 4 Name Type Reset 3 2 1 0 TE_C CMD_ DATA CPL PL CPL _CPL R/W R/W R/W R/W 0 0 0 0 CPL LCD Frame Transfer Complete Interrupt Control DATA_CPL Data Transfer Complete in Hardware Triggered Refresh Mode Interrupt Control CMD_CPL Command Transfer Complete in Hardware Trigger Refresh Mode Interrupt Control TE_CPL Issue an interrupt when TE pending complete LCD +0008h Bit 15 14 LCD Interface Interrupt Status Register 13 12 11 10 9 8 7 6 LCD_INTSTA 5 4 Name Type Reset 3 2 1 0 TE_ CMD_ DATA CPL CPL CPL _CPL R R R R 0 0 0 0 CPL LCD Frame Transfer Complete Interrupt DATA_CPL Data Transfer Complete in Hardware Triggered Refresh Mode Interrupt CMD_CPL Command Transfer Complete in Hardware Triggered Refresh Mode Interrupt TE_ CPL Frame update pending for tearing input LCD +000Ch Bit 15 STAR Name T Type R/W Reset 0 14 LCD Interface Frame Transfer Register 13 12 11 10 9 8 7 6 LCD_START 5 4 3 2 1 0 START Start Control of LCD Frame Transfer LCD +0010h Bit Name Type Reset 15 14 LCD Parallel/Serial Interface Reset Register 13 12 11 10 9 8 7 6 5 LCD_RSTB 4 3 2 1 0 RSTB R/W 1 RSTB Parallel/Serial LCD Module Reset Control LCD +0014h Bit 15 Name 26M Type R/W Type 0 14 13M R/W 0 LCD Serial Interface Configuration Register 13 12 GAMMA_ID R/W 0 11 10 9 8 CSP1 CSP0 R/W R/W 0 0 272/599 7 6 5 LCD _SCNF 4 8/9 R/W 0 3 2 DIV R/W 0 1 SPH R/W 0 0 SPO R/W 0 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 SPO Clock Polarity Control SPH Clock Phase Control DIV Serial Clock Divide Select Bits 8/9 8-bit or 9-bit Interface Selection CSP0 Serial Interface Chip Select 0 Polarity Control CSP1 Serial Interface Chip Select 1 Polarity Control GAMMA_ID Gamma correction LUT ID 00 table 0 01 table 1 10 table 2 11 no table selected 13M Enable 13MHz clock gating. 26M Enable 26MHz clock gating. LCD +0018h Bit 31 30 LCD Parallel Interface Configuration Register 0 29 28 27 26 25 Name C2WS C2WH C2RS Type R/W 0 R/W 0 R/W 0 Bit 15 Name 52M Type R/W Reset 0 14 26M R/W 0 13 12 11 10 WST R/W 0 9 24 8 LCD_PCNF0 23 22 21 20 19 18 GAMMA_ID_ GAMMA_ID_ GAMMA_ID_ R G B R/W R/W R/W 0 0 0 7 6 5 4 3 2 RLT R/W 0 17 16 DW R/W 0 1 0 Read Latency Time Actual Read Latency cycles = RLT+2 cycles WST Write Wait State Time 26M Enable 26MHz clock gating. 52M Enable 52MHz clock gating. DW Data width of the parallel interface 00 8-bit. 01 9-bit 10 16-bit 11 18-bit GAMMA_ID_R Gamma Correction LUT ID for Red Component 00 table 0 01 table 1 10 table 2 11 no table selected GAMMA_ID_G Gamma correction LUT ID for Green Component 00 table 0 01 table 1 10 table 2 11 no table selected GAMMA_ID_B Gamma correction LUT ID for Blue Component RLT 273/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 00 table 0 01 table 1 10 table 2 11 no table selected C2RS Chip Select (LPCE#) to Read Strobe (LRD#) Setup Time C2WH Chip Select (LPCE#) to Write Strobe (LWR#) Hold Time C2WS Chip Select (LPCE#) to Write Strobe (LWR#) Setup Time LCD +001Ch Bit Name Type 31 30 C2WS R/W 0 Bit 15 14 Name 52M 26M Type R/W R/W Reset 0 0 LCD Parallel Interface Configuration Register 1 29 28 C2WH R/W 0 13 12 27 11 26 25 C2RS R/W 0 10 9 WST R/W 0 24 8 23 7 22 6 21 20 GAMMA_ID R/W 11 5 4 LCD_PCNF1 19 18 17 16 DW R/W 0 3 2 RLT R/W 0 1 0 Read Latency Time Actual Read Latency cycles = RLT+2 cycles WST Write Wait State Time 26M Enable 26MHz clock gating. 52M Enable 52MHz clock gating. DW Data width of the parallel interface 00 8-bit. 01 9-bit 10 16-bit 11 18-bit GAMMA_ID Gamma correction LUT ID 00 table 0 01 table 1 10 table 2 11 no table selected C2RS Chip Select (LPCE#) to Read Strobe (LRD#) Setup Time C2WH Chip Select (LPCE#) to Write Strobe (LWR#) Hold Time C2WS Chip Select (LPCE#) to Write Strobe (LWR#) Setup Time RLT LCD +0020h Bit Name Type 31 30 C2WS R/W 0 Bit 15 14 Name 52M 26M Type R/W R/W Reset 0 0 RLT LCD Parallel Interface Configuration Register 2 29 28 C2WH R/W 0 13 12 27 11 26 25 C2RS R/W 0 10 9 WST R/W 0 24 8 23 7 22 6 21 20 GAMMA_ID R/W 0 5 4 LCD_PCNF2 19 18 17 16 DW R/W 0 3 2 RLT R/W 0 1 0 Read Latency Time Actual Read Latency cycles = RLT+2 cycles 274/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 Write Wait State Time Enable 26MHz clock gating. Enable 52MHz clock gating. Data width of the parallel interface. 00 8-bit. 01 9-bit 10 16-bit 11 18-bit GAMMA_ID Gamma correction LUT ID 00 table 0 01 table 1 10 table 2 11 no table selected C2RS Chip Select (LPCE#) to Read Strobe (LRD#) Setup Time C2WH Chip Select (LPCE#) to Write Strobe (LWR#) Hold Time C2WS Chip Select (LPCE#) to Write Strobe (LWR#) Setup Time WST 26M 52M DW LCD Controller Synchronization Modes When TE_EN is enabled, LCD controller will synchronize its updating to LCM refresh timing. And it supports two synchronizing modes depending on TE_MODE. TE Signal Polarity TE_EDGE_SEL can be used to select TE polarity for TE signal detection. TE_EDGE_SEL value TE signal detection 0 Detect a TE signal at its rising edge. This setting is for active high TE signal. 1 Detect a TE signal at its falling edge. This setting if for active low TE signal. Table 2 TE Signal Polarity Vertical Synchronization Mode MT6235 LCD supports vertical synchronization mode to avoid tearing effect. In this mode, LCD controller starts to update LCM after each rising edge of the TE input (or falling edge, if TE_EDGE_SEL is set to 1) (see Figure 3). Vertical Synchro TE input LCD updating Figure 34 Vertical Synchronization Mode LCD +0024h Bit 31 30 LCD Tearing Control Register 29 28 27 26 25 24 275/599 LCD_TECON 23 22 21 20 19 18 17 16 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 Name Type Reset Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 Name Type Reset TE_EN Enable tearing control. TE_EDGE_SELSelect sync edge. 0 Rising edge 1 Falling edge LCD +4000h Bit Name Type Bit Name Type 1 0 TE_E TE_E DGE_ N SEL R/W R/W 0 0 LCD controller will synchronize to LCM refresh timing. LCD Parallel 0 Interface Data 31 30 29 28 27 26 25 15 14 13 12 11 10 9 LCD_PDAT0 24 23 DATA[31:16] R/W 8 7 DATA[15:0] R/W 22 21 20 19 18 17 16 6 5 4 3 2 1 0 DATA Writing to LCD+4000 will drive LPA0 low when sending this data out in parallel BANK0, while writing to LCD+4100 will drive LPA0 high. LCD +5000h Bit Name Type Bit Name Type LCD Parallel 1 Interface Data 31 30 29 28 27 26 25 15 14 13 12 11 10 9 LCD_PDAT1 24 23 DATA[31:16] R/W 8 7 DATA[15:0] R/W 22 21 20 19 18 17 16 6 5 4 3 2 1 0 DATA Writing to LCD+5000 will drive LPA1 low when sending this data out in parallel BANK1, while writing to LCD+5100 will drive LPA1 high LCD +6000h Bit Name Type Bit Name Type LCD Parallel 2 Interface Data 31 30 29 28 27 26 25 15 14 13 12 11 10 9 LCD_PDAT2 24 23 DATA[31:16] R/W 8 7 DATA[15:0] R/W 22 21 20 19 18 17 16 6 5 4 3 2 1 0 DATA Writing to LCD+6000 will drive LPA2 low when sending this data out in parallel BANK2, while writing to LCD+6100 will drive LPA2 high LCD +8000/8100h Bit Name 15 14 LCD Serial Interface 1 Data 13 12 11 10 9 LCD_SDAT1 8 276/599 7 6 5 4 3 DATA 2 1 0 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 Type W DATA Writing to LCD+8000 will drive LSA0 low while sending this data out in serial BANK1, while writing to LCD+8100 will drive LSA0 high LCD +9000/9100h Bit Name Type 15 14 LCD Serial Interface 0 Data 13 12 11 10 9 LCD_SDAT0 8 7 6 5 4 3 DATA W 2 1 0 DATA Writing to LCD+9000 will drive LSA0 low while sending this data out in serial BANK0, while writing to LCD+9100 will drive LSA0 high LCD +0040h Bit Name Type Bit Name Type Main Window Size Register LCD_MWINSIZE 31 30 29 28 27 26 25 24 23 22 15 14 13 12 11 10 9 8 7 6 21 20 ROW R/W 5 4 COLUMN R/W 19 18 17 16 3 2 1 0 COLUMN 10-bit Virtual Image Window Column Size ROW 10-bit Virtual Image Window Row Size LCD +0044h Bit Name Type Bit Name Type Region of Interest Window Write to Memory Offset Register 31 30 29 28 27 26 25 24 23 22 15 14 13 12 11 10 9 8 7 6 LCD_WROI_W2M OFS 21 20 Y-OFFSET R/W 5 4 X-OFFSET R/W 19 18 17 16 3 2 1 0 This control register is used to specify the offset of the ROI window from the LCD_WROI_W2MADDR when writing the ROI window’s content to memory. X-OFFSET the x offset of ROI window in the destination memory. Y-OFFSET the y offset of ROI window in the destination memory. LCD +0048h Bit Name Type Reset Bit Region of Interest Window Write to Memory Control Register 31 30 29 28 27 26 25 24 23 22 21 15 14 13 12 11 10 9 8 7 6 5 Name OUTPUT_ALPHA Type Reset R/W 0xff 277/599 20 LCD_WROI_W2M CON 19 18 17 16 4 3 2 1 0 ADDI DC_O NC_DI DISC W2M_FORM W2LC UT_E SABL ON AT M N E R/W R/W R/W R/W R/W 0 0 0 0 0 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 This control register is effective only when the W2M bit is set in LCD_WROICON register. W2LCM Write to LCM simultaneously. W2M_FORMAT Write to memory format. 00 RGB565 01 RGB888 10 ARGB8888 DISCON Block Write Enable Control. By setting both DISCON and W2M to 1, the LCD controller will write out the ROI pixel data as a part of MAIN window, using the width of MAIN window to calculate the write-out address. If this bit is not set, the ROI window will be written to memory in continuous addresses. ADDINC_DISABLE Disable address increase when writing to memory. DC_OUT_EN Enable direct couple to rotator 3. OUTPUT_ALPHA Output Alpha value. LCD +004Ch Bit Name Type Bit Name Type Region of Interest Window Write to Memory Address LCD_WROI_W2M Register ADD 31 30 29 28 27 26 25 15 14 13 12 11 10 9 24 23 W2M_ADDR R/W 8 7 W2M_ADDR R/W 22 21 20 19 18 17 16 6 5 4 3 2 1 0 W2M_ADDR Write to memory address. For better memory write efficiency, it is recommended to 64 bytes alignment, but it is not restricted to 64 bytes alignment. LCD +0050h Bit 31 Name EN0 Type R/W Bit 15 Name ENC Type R/W 30 EN1 R/W 14 Region of Interest Window Control Register 29 28 EN2 EN3 R/W R/W 13 12 COM_ W2M SEL R/W R/W 27 EN4 R/W 11 26 EN5 R/W 10 25 24 23 22 9 8 7 6 LCD_WROICON 21 20 PERIOD R/W 5 4 19 18 17 16 3 2 1 0 COMMAND FORMAT R/W R/W FORMAT LCD Module Data Format Bit 0 : in BGR sequence, otherwise in RGB sequence. Bit 1 : LSB first, otherwise MSB first. Bit 2 : padding bits on MSBs, otherwise on LSBs. Bit 5-3 : 000 for RGB332, 001 for RGB444, 010 for RGB565, 011 for RGB666, 100 for RGB888. Bit 7-6 : 00 for 8-bit interface, 01 for 16-bit interface, 10 for 9-bit interface, 11 for 18-bit interface. Note: When the interface is configured as 9 bit or 18 bit, the field of bit5-2 is ignored. 00000000 8bit 1cycle/1pixel RGB3.3.2 RRRGGGBB 00000001 1cycle/1pixel RGB3.3.2 BBGGGRRR 00001000 3cycle/2pixel RGB4.4.4 RRRRGGGG BBBBRRRR GGGGBBBB 278/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 00001011 3cycle/2pixel RGB4.4.4 00010000 2cycle/1pixel RGB5.6.5 00010011 2cycle/1pixel RGB5.6.5 00011000 3cycle/1pixel RGB6.6.6 00011100 3cycle/1pixel RGB6.6.6 00100000 3cycle/1pixel RGB8.8.8 2cycle/1pixel RGB6.6.6 2cycle/1pixel RGB6.6.6 1cycle/2pixel 1cycle/2pixel 1cycle/2pixel 1cycle/2pixel 1cycle/1pixel 1cycle/1pixel 1cycle/1pixel 1cycle/1pixel 1cycle/1pixel 1cycle/1pixel 3cycle/2pixel RGB3.3.2 RGB3.3.2 RGB3.3.2 RGB3.3.2 RGB4.4.4 RGB4.4.4 RGB4.4.4 RGB4.4.4 RGB5.6.5 RGB5.6.5 RGB6.6.6 01011111 3cycle/2pixel RGB6.6.6 01011000 3cycle/2pixel RGB6.6.6 01011011 3cycle/2pixel RGB6.6.6 01100000 3cycle/2pixel RGB8.8.8 10xxxx00 9bit 10xxxx11 01000000 01000010 01000001 01000011 01001100 01001101 01001000 01001001 01010000 01010001 01011100 16bit 279/599 GGGGRRRR RRRRBBBB BBBBGGGG RRRRRGGG GGGBBBBB GGGRRRRR BBBBBGGG RRRRRRXX GGGGGGXX BBBBBBXX XXRRRRRR XXGGGGGG XXBBBBBB RRRRRRRR GGGGGGGG BBBBBBBB RRRRRRGGG GGGBBBBBB GGGRRRRRR BBBBBBGGG RRRGGGBBRRRGGGBB RRRGGGBBRRRGGGBB BBGGGRRRBBGGGRRR BBGGGRRRBBGGGRRR XXXXRRRRGGGGBBBB XXXXBBBBGGGGRRRR RRRRGGGGBBBBXXXX BBBBGGGGRRRRXXXX RRRRRGGGGGGBBBBB BBBBBGGGGGGRRRRR XXXXRRRRRRGGGGGG XXXXBBBBBBRRRRRR XXXXGGGGGGBBBBBB XXXXGGGGGGRRRRRR XXXXRRRRRRBBBBBB XXXXBBBBBBGGGGGG RRRRRRGGGGGGXXXX BBBBBBRRRRRRXXXX GGGGGGBBBBBBXXXX GGGGGGRRRRRRXXXX RRRRRRBBBBBBXXXX BBBBBBGGGGGGXXXX RRRRRRRRGGGGGGGG MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 01100011 11xxxx00 11xxxx01 11100000 18bit 11100011 3cycle/2pixel RGB8.8.8 1cycle/1pixel 1cycle/1pixel 3cycle/2pixel RGB6.6.6 RGB6.6.6 RGB8.8.8 3cycle/2pixel RGB8.8.8 BBBBBBBBRRRRRRRR GGGGGGGGBBBBBBBB GGGGGGGGRRRRRRRR RRRRRRRRBBBBBBBB BBBBBBBBRRRRRRRR RRRRRRGGGGGGBBBBBB BBBBBBGGGGGGRRRRRR RRRRRRRRGGGGGGGG BBBBBBBBRRRRRRRR GGGGGGGGBBBBBBBB GGGGGGGGRRRRRRRR RRRRRRRRBBBBBBBB BBBBBBBBRRRRRRRR COM_SEL Command Queue ID Selection COMMAND Number of Commands to be sent to LCD module. Maximum is 31. W2M Enable Write to Memory ENC Command Transfer Enable Control PERIOD Waiting period between two consecutive transfers, effective for both data and command. ENn Layer Window Enable Control LCD +0054h Bit Name Type Bit Name Type Region of Interest Window Offset Register 31 30 29 28 27 26 25 24 23 22 15 14 13 12 11 10 9 8 7 6 LCD_WROIOFS 21 20 Y-OFFSET R/W 5 4 X-OFFSET R/W 19 18 17 16 3 2 1 0 X-OFFSET ROI Window Column Offset Y-OFFSET ROI Window Row Offset LCD +0058h Bit Name Type 15 14 Region of Interest Window Command Start Address Register 13 12 11 10 9 8 7 ADDR R/W 6 5 4 LCD_WROICAD D 3 2 1 0 ADDR ROI Window Command Address. Only writing to LCD modules is allowed. LCD +005Ch Bit Name Type 15 14 Region of Interest Window Data Start Address Register 13 12 11 10 9 8 7 ADDR R/W 6 5 4 3 LCD_WROIDAD D 2 1 0 ADDR ROI Window Data Address Only writing to LCD modules is allowed. 280/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 LCD +0060h Bit Name Type Bit Name Type Region of Interest Window Size Register 31 30 29 28 27 26 25 24 23 22 15 14 13 12 11 10 9 8 7 6 LCD_WROISIZE 21 20 ROW R/W 5 4 COLUMN R/W 19 18 17 16 3 2 1 0 COLUMN ROI Window Column Size ROW ROI Window Row Size LCD +0064h Bit 31 Name EN0 Type R/W Reset 0 Bit 15 30 EN1 R/W 0 14 Region of Interest Window Hardware Refresh Register 29 EN2 R/W 0 13 28 EN3 R/W 0 12 27 EN4 R/W 0 11 26 EN5 R/W 0 10 LCD_WROI_HW REF 25 24 23 22 21 20 19 18 9 8 7 6 5 4 3 2 Name HWEN Type Reset R/W 0 17 16 HWREF_SEL R/W 0 1 0 HWR EF R/W 0 ENn Enable layer n source address from Image_DMA. HWEN Enable hardware triggered LCD fresh. HWREF_SEL Select hardware triggered source. 00 triggered by IRT1. 01 triggered by IBW1. 10 triggered by IRT2 (without base address). 11 triggered by IBW2 (without base address). HWREF Starting the hardware triggered LCD frame transfer. LCD +0068h Bit 31 30 Name EN0 EN1 Type R/W R/W Reset 0 0 Bit 15 14 Name DC_SEL0 Type R/W Reset 0 Region of Interest Window Direct Couple Register 29 28 EN2 EN3 R/W R/W 0 0 13 12 DC_SEL1 R/W 0 27 26 EN4 EN5 R/W R/W 0 0 11 10 DC_SEL2 R/W 0 25 24 9 8 DC_SEL3 R/W 0 23 22 7 6 DC_SEL4 R/W 0 21 LCD_WROI_DC 20 19 18 17 16 5 4 DC_SEL5 R/W 0 3 2 1 0 ENn Enable layer n source data from Image_DMA. DC_SELnSelect source layer n data. 00 Reserved. 01 IBW1 10 IRT2 11 IBW2 Note : When direct couple is enabled on mulitple layers, the source data of each layer should be different. 281/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 LCD +006Ch Bit Name Type Reset Bit Name Type Reset LCD_WROI_BG CLR Region of Interest Background Color Register 31 30 29 15 14 13 28 27 12 11 GREEN[7:0] R/W 1111_1111 26 25 24 23 22 21 10 9 8 7 6 5 20 19 RED[7:0] R/W 1111_1111 4 3 BLUE[7:0] R/W 1111_1111 18 17 16 2 1 0 RED Red component of ROI window’s background color GREEN Green component of ROI window’s background color BLUE Blue component of ROI window’s background color LCD +0070h Bit 31 30 LCD_L0WINCO N Layer 0 Window Control Register 29 28 27 26 25 24 23 22 21 Name Type Bit 15 14 KEYE Name SRC N Type R/W R/W 13 12 11 10 9 ROTATE CLRDPT R/W R/W 8 OPAE N R/W 7 6 5 20 READ _CAC HE_DI S R/W 4 19 18 17 16 SWP 3 2 1 R/W 0 OPA R/W OPA Opacity value, used as constant alpha value. OPAEN Opacity enabled CLRDPT Color format 00 8bpp indexed color. 01 RGB 565 10 ARGB 8888 11 RGB 888 ROTATE Rotation Configuration 000 0 degree rotation 001 90 degree rotation anti-counterclockwise 010 180 degree rotation anti-counterclockwise 011 270 degree rotation anti-counterclockwise 100 Horizontal flip 101 Horizontal flip then 90 degree rotation anti-counterclockwise 110 Horizontal flip then 180 degree rotation anti-counterclockwise 111 Horizontal flip then 270 degree rotation anti-counterclockwise KEYEN Source Key Enable Control SRC Disable auto-increment of the source pixel address SWP Swap high byte and low byte of pixel data READ_CACHE_DIS Disable read cache, issue single access 282/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 LCD +0074h Bit Name Type Bit Name Type 31 30 29 28 27 26 15 14 13 12 11 10 SRCKEY 25 24 23 22 SRCKEY[31:16] R/W 9 8 7 6 SRCKEY[15:0] R/W 21 20 19 18 17 16 5 4 3 2 1 0 Transparent color key of the source image. LCD +0078h Bit Name Type Bit Name Type LCD_L0WINSKE Y Layer 0 Source Color Key Register Layer 0 Window Display Offset Register 31 30 29 28 27 26 25 24 23 22 15 14 13 12 11 10 9 8 7 6 LCD_L0WINOFS 21 20 Y-OFFSET R/W 5 4 X-OFFSET R/W 19 18 17 16 3 2 1 0 Y-OFFSET Layer 0 Window Row Offset X-OFFSET Layer 0 Window Column Offset LCD+007Ch Bit Name Type Bit Name Type Layer 0 Window Display Start Address Register 31 30 29 28 27 26 25 15 14 13 12 11 10 9 24 23 ADDR R/W 8 7 ADDR R/W LCD_L0WINADD 22 21 20 19 18 17 16 6 5 4 3 2 1 0 ADDR Layer 0 Window Data Address. Note that the layer start address must be word-aligned. LCD +0080h Bit Name Type Bit Name Type LCD_L0WINSIZ E Layer 0 Window Size 31 30 29 28 27 26 25 24 23 22 15 14 13 12 11 10 9 8 7 6 21 20 ROW R/W 5 4 COLUMN R/W 19 18 17 16 3 2 1 0 ROW Layer 0 Window Row Size COLUMN Layer 0 Window Column Size LCD +0090h Bit Name Type Bit LCD_L1WINCO N Layer 1 Window Control Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 283/599 16 SWP R/W 0 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 KEYE N R/W R/W Name SRC Type ROTATE CLRDPT R/W R/W OPAE N R/W OPA R/W OPA Opacity value, used as constant alpha value. OPAEN Opacity enabled CLRDPT Color format 00 8bpp indexed color. 01 RGB 565 10 ARGB 8888 11 RGB 888 ROTATE Rotation Configuration 000 0 degree rotation 001 90 degree rotation anti-counterclockwise 010 180 degree rotation anti-counterclockwise 011 270 degree rotation anti-counterclockwise 100 Horizontal flip 101 Horizontal flip then 90 degree rotation anti-counterclockwise 110 Horizontal flip then 180 degree rotation anti-counterclockwise 111 Horizontal flip then 270 degree rotation anti-counterclockwise KEYEN Source Key Enable Control SRC Disable auto-increment of the source pixel address SWP Swap high byte and low byte of pixel data READ_CACHE_DIS Disable read cache, issue single access LCD +0094h Bit Name Type Bit Name Type 31 30 29 28 27 26 15 14 13 12 11 10 SRCKEY 25 24 23 22 SRCKEY[31:16] R/W 9 8 7 6 SRCKEY[15:0] R/W 21 20 19 18 17 16 5 4 3 2 1 0 Transparent color key of the source image. LCD +0098h Bit Name Type Bit Name Type LCD_L1WINSKE Y Layer 1 Source Color Key Register Layer 1 Window Display Offset Register 31 30 29 28 27 26 25 24 23 22 15 14 13 12 11 10 9 8 7 6 LCD_L1WINOFS 21 20 Y-OFFSET R/W 5 4 X-OFFSET R/W 19 18 17 16 3 2 1 0 Y-OFFSET Layer 1 Window Row Offset X-OFFSET Layer 1 Window Column Offset LCD+009Ch Bit 31 30 Layer 1 Window Display Start Address Register 29 28 27 26 25 24 284/599 23 22 21 LCD_L1WINADD 20 19 18 17 16 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 Name Type Bit Name Type 15 14 13 12 11 10 9 ADDR R/W 8 7 ADDR R/W 6 5 4 3 2 1 0 ADDR Layer 1 Window Data Address. Note that the layer start address must be word-aligned. LCD +00A0h Bit Name Type Bit Name Type LCD_L1WINSIZ E Layer 1 Window Size 31 30 29 28 27 26 25 24 23 22 15 14 13 12 11 10 9 8 7 6 21 20 ROW R/W 5 4 COLUMN R/W 19 18 17 16 3 2 1 0 ROW Layer 1 Window Row Size COLUMN Layer 1 Window Column Size LCD +00B0h Bit Name Type Bit 31 15 30 14 KEYE Name SRC N Type R/W R/W LCD_L2WINCO N Layer 2 Window Control Register 29 28 27 26 25 24 23 22 21 20 19 18 17 13 12 11 10 9 8 OPAE N R/W 7 6 5 4 3 2 1 ROTATE CLRDPT R/W R/W 16 SWP R/W 0 OPA R/W OPA Opacity value, used as constant alpha value. OPAEN Opacity enabled CLRDPT Color format 00 8bpp indexed color. 01 RGB 565 10 ARGB 8888 11 RGB 888 ROTATE Rotation Configuration 000 0 degree rotation 001 90 degree rotation anti-counterclockwise 010 180 degree rotation anti-counterclockwise 011 270 degree rotation anti-counterclockwise 100 Horizontal flip 101 Horizontal flip then 90 degree rotation anti-counterclockwise 110 Horizontal flip then 180 degree rotation anti-counterclockwise 111 Horizontal flip then 270 degree rotation anti-counterclockwise KEYEN Source Key Enable Control SRC Disable auto-increment of the source pixel address SWP Swap high byte and low byte of pixel data 285/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 READ_CACHE_DIS Disable read cache, issue single access LCD +00B4h Bit Name Type Bit Name Type 31 30 29 28 27 26 15 14 13 12 11 10 SRCKEY 25 24 23 22 SRCKEY[31:16] R/W 9 8 7 6 SRCKEY[15:0] R/W 21 20 19 18 17 16 5 4 3 2 1 0 Transparent color key of the source image. LCD +00B8h Bit Name Type Bit Name Type LCD_L2WINSKE Y Layer 2 Source Color Key Register Layer 2 Window Display Offset Register 31 30 29 28 27 26 25 24 23 22 15 14 13 12 11 10 9 8 7 6 LCD_L2WINOFS 21 20 Y-OFFSET R/W 5 4 X-OFFSET R/W 19 18 17 16 3 2 1 0 Y-OFFSET Layer 2 Window Row Offset X-OFFSET Layer 2 Window Column Offset LCD+00BCh Bit Name Type Bit Name Type Layer 2 Window Display Start Address Register 31 30 29 28 27 26 25 15 14 13 12 11 10 9 ADDR Layer 1 Window Data Address LCD +00C0h Bit Name Type Bit Name Type 24 23 ADDR R/W 8 7 ADDR R/W LCD_L2WINADD 22 21 20 19 18 17 16 6 5 4 3 2 1 0 Note that the layer start address must be word-aligned. LCD_L2WINSIZ E Layer 2 Window Size 31 30 29 28 27 26 25 24 23 22 15 14 13 12 11 10 9 8 7 6 21 20 ROW R/W 5 4 COLUMN R/W 19 18 17 16 3 2 1 0 ROW Layer 2 Window Row Size COLUMN Layer 2 Window Column Size LCD +00D0h Bit Name Type Bit LCD_L3WINCO N Layer 3 Window Control Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 286/599 16 SWP R/W 0 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 KEYE N R/W R/W Name SRC Type ROTATE CLRDPT R/W R/W OPAE N R/W OPA R/W OPA Opacity value, used as constant alpha value. OPAEN Opacity enabled CLRDPT Color format 00 8bpp indexed color. 01 RGB 565 10 ARGB 8888 11 RGB 888 ROTATE Rotation Configuration 000 0 degree rotation 001 90 degree rotation anti-counterclockwise 010 180 degree rotation anti-counterclockwise 011 270 degree rotation anti-counterclockwise 100 Horizontal flip 101 Horizontal flip then 90 degree rotation anti-counterclockwise 110 Horizontal flip then 180 degree rotation anti-counterclockwise 111 Horizontal flip then 270 degree rotation anti-counterclockwise KEYEN Source Key Enable Control SRC Disable auto-increment of the source pixel address SWP Swap high byte and low byte of pixel data READ_CACHE_DIS Disable read cache, issue single access LCD +00D4h Bit Name Type Bit Name Type 31 30 29 28 27 26 15 14 13 12 11 10 SRCKEY 25 24 23 22 SRCKEY[31:16] R/W 9 8 7 6 SRCKEY[15:0] R/W 21 20 19 18 17 16 5 4 3 2 1 0 Transparent color key of the source image. LCD +00D8h Bit Name Type Bit Name Type LCD_L3WINSKE Y Layer 3 Source Color Key Register Layer 3 Window Display Offset Register 31 30 29 28 27 26 25 24 23 22 15 14 13 12 11 10 9 8 7 6 LCD_L3WINOFS 21 20 Y-OFFSET R/W 5 4 X-OFFSET R/W 19 18 17 16 3 2 1 0 Y-OFFSET Layer 3 Window Row Offset X-OFFSET Layer 3 Window Column Offset LCD+00DCh Bit 31 30 Layer 3 Window Display Start Address Register 29 28 27 26 25 24 287/599 23 22 21 LCD_L3WINADD 20 19 18 17 16 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 Name Type Bit Name Type 15 14 13 12 11 ADDR Layer 3 Window Data Address LCD +00E0h Bit Name Type Bit Name Type 10 9 ADDR R/W 8 7 ADDR R/W 6 5 4 3 2 1 0 Note that the layer start address must be word-aligned. LCD_L3WINSIZ E Layer 3 Window Size 31 30 29 28 27 26 25 24 23 22 15 14 13 12 11 10 9 8 7 6 21 20 ROW R/W 5 4 COLUMN R/W 19 18 17 16 3 2 1 0 ROW Layer 3 Window Row Size COLUMN Layer 3 Window Column Size LCD +00F0h Bit Name Type Bit 31 15 30 14 KEYE Name SRC N Type R/W R/W LCD_L4WINCO N Layer 4 Window Control Register 29 28 27 26 25 24 23 22 21 20 19 18 17 13 12 11 10 9 8 OPAE N R/W 7 6 5 4 3 2 1 ROTATE CLRDPT R/W R/W 16 SWP R/W 0 OPA R/W OPA Opacity value, used as constant alpha value. OPAEN Opacity enabled CLRDPT Color format 00 8bpp indexed color. 01 RGB 565 10 ARGB 8888 11 RGB 888 ROTATE Rotation Configuration 000 0 degree rotation 001 90 degree rotation anti-counterclockwise 010 180 degree rotation anti-counterclockwise 011 270 degree rotation anti-counterclockwise 100 Horizontal flip 101 Horizontal flip then 90 degree rotation anti-counterclockwise 110 Horizontal flip then 180 degree rotation anti-counterclockwise 111 Horizontal flip then 270 degree rotation anti-counterclockwise KEYEN Source Key Enable Control SRC Disable auto-increment of the source pixel address SWP Swap high byte and low byte of pixel data 288/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 READ_CACHE_DIS Disable read cache, issue single access LCD +00F4h Bit Name Type Bit Name Type 31 30 29 28 27 26 15 14 13 12 11 10 SRCKEY 25 24 23 22 SRCKEY[31:16] R/W 9 8 7 6 SRCKEY[15:0] R/W 21 20 19 18 17 16 5 4 3 2 1 0 Transparent color key of the source image. LCD +00F8h Bit Name Type Bit Name Type LCD_L4WINSKE Y Layer 4 Source Color Key Register Layer 4 Window Display Offset Register 31 30 29 28 27 26 25 24 23 22 15 14 13 12 11 10 9 8 7 6 LCD_L4WINOFS 21 20 Y-OFFSET R/W 5 4 X-OFFSET R/W 19 18 17 16 3 2 1 0 Y-OFFSET Layer 4 Window Row Offset X-OFFSET Layer 4 Window Column Offset LCD+00FCh Bit Name Type Bit Name Type Layer 4 Window Display Start Address Register 31 30 29 28 27 26 25 15 14 13 12 11 10 9 ADDR Layer 4 Window Data Address LCD +0100h Bit Name Type Bit Name Type 24 23 ADDR R/W 8 7 ADDR R/W LCD_L4WINADD 22 21 20 19 18 17 16 6 5 4 3 2 1 0 Note that the layer start address must be word-aligned. LCD_L4WINSIZ E Layer 4 Window Size 31 30 29 28 27 26 25 24 23 22 15 14 13 12 11 10 9 8 7 6 21 20 ROW R/W 5 4 COLUMN R/W 19 18 17 16 3 2 1 0 ROW Layer 4 Window Row Size COLUMN Layer 4 Window Column Size LCD +0110h Bit Name Type Bit LCD_L5WINCO N Layer 5 Window Control Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 289/599 16 SWP R/W 0 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 KEYE N R/W R/W Name SRC Type ROTATE CLRDPT R/W R/W OPAE N R/W OPA R/W OPA Opacity value, used as constant alpha value. OPAEN Opacity enabled CLRDPT Color format 00 8bpp indexed color. 01 RGB 565 10 ARGB 8888 11 RGB 888 ROTATE Rotation Configuration 000 0 degree rotation 001 90 degree rotation anti-counterclockwise 010 180 degree rotation anti-counterclockwise 011 270 degree rotation anti-counterclockwise 100 Horizontal flip 101 Horizontal flip then 90 degree rotation anti-counterclockwise 110 Horizontal flip then 180 degree rotation anti-counterclockwise 111 Horizontal flip then 270 degree rotation anti-counterclockwise KEYEN Source Key Enable Control SRC Disable auto-increment of the source pixel address SWP Swap high byte and low byte of pixel data READ_CACHE_DIS Disable read cache, issue single access LCD +0114h Bit Name Type Bit Name Type 31 30 29 28 27 26 15 14 13 12 11 10 SRCKEY 25 24 23 22 SRCKEY[31:16] R/W 9 8 7 6 SRCKEY[15:0] R/W 21 20 19 18 17 16 5 4 3 2 1 0 Transparent color key of the source image. LCD +0118h Bit Name Type Bit Name Type LCD_L5WINSKE Y Layer 5 Source Color Key Register Layer 5 Window Display Offset Register 31 30 29 28 27 26 25 24 23 22 15 14 13 12 11 10 9 8 7 6 LCD_L5WINOFS 21 20 Y-OFFSET R/W 5 4 X-OFFSET R/W 19 18 17 16 3 2 1 0 Y-OFFSET Layer 5 Window Row Offset X-OFFSET Layer 5 Window Column Offset LCD+011Ch Bit 31 30 Layer 5 Window Display Start Address Register 29 28 27 26 25 24 290/599 23 22 21 LCD_L5WINADD 20 19 18 17 16 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 Name Type Bit Name Type 15 14 13 12 11 ADDR Layer 5 Window Data Address LCD +0120h Bit Name Type Bit Name Type 10 9 ADDR R/W 8 7 ADDR R/W 6 5 4 3 2 1 0 Note that the layer start address must be word-aligned. LCD_L5WINSIZ E Layer 5 Window Size 31 30 29 28 27 26 25 24 23 22 15 14 13 12 11 10 9 8 7 6 21 20 ROW R/W 5 4 COLUMN R/W 19 18 17 16 3 2 1 0 ROW Layer 5 Window Row Size COLUMNLayer 5 Window Column Size LCD +C000h~C3FCh Bit Name Type Bit Name Type LCD Interface Gamma Correction LUT Registers 31 30 29 15 14 13 28 27 12 11 GAMM_LUT1 R/W 26 25 24 23 22 21 10 9 8 7 6 5 LCD_GAMMA 20 19 18 GAMMA_LUT2 R/W 4 3 2 GAMMA_LUT0 R/W 17 16 1 0 GAMMA_LUT0 These Bits Set Gamma LUT 0. GAMMA_LUT1 These Bits Set Gamma LUT 1. GAMMA_LUT2 These Bits Set Gamma LUT 2. LCD +C400h~C7FCh 30 LCD Interface Color Palette LUT Registers Bit Name Type Bit Name Type 31 29 28 27 26 25 LUT These Bits Set Color Palette in RGB888 format. 24 23 22 21 LCD_PAL 20 19 18 17 16 3 2 1 0 LUT R/W 15 14 13 12 11 10 9 8 7 6 5 4 LUT R/W LCD +C800h~C8FC LCD Interface Command/Parameter Registers Bit 31 30 29 28 27 26 25 24 Name Type Bit Name Type 23 LCD_COMD 22 21 20 19 18 6 5 4 3 2 C0 15 14 13 12 11 10 9 R/W 8 7 COMM[15:0] R/W 291/599 17 16 COMM[17:16 ] R/W 1 0 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 COMM Command Data and Parameter Data for LCD Module C0 Write to ROI Command Address if C0 = 1, otherwise write to ROI Data Address 7.2 Capture Resize 7.2.1 General Description This block provides the image resizing function for image and video capturing scenarios. It receives image data from the ISP module, performs the image resizing function and outputs to the IMG_DMA module. Figure 35 shows the block diagram. The capture resize is composed of horizontal and vertical resizing blocks. It can scale up or down the input image by any ratio. However, the maximum sizes of input and output images are limited to 4095x4095. Horizontal resize ISP Vertical resize YUV422 YUV444 IMG_DMA YUV444 vert. buffer Figure 35 Block diagram of the capture resize The resizing function is cubic interpolation. The input and output format are both YUV444. But the internal working memory format is YUV422 to mitigate memory and bandwidth requirements. 7.2.2 Register Definitions REGISTER ADDRESS REGISTER NAME SYNONYM CRZ+ 0000h Capture Resize Configuration Register CRZ_CFG CRZ + 0004h Capture Resize Control Register CRZ_CON CRZ + 0008h Capture Resize Status Register CRZ_STA CRZ + 000Ch Capture Resize Interrupt Register CRZ_INT CRZ + 0010h Capture Resize Source Image Size Register 1 CRZ_SRCSZ1 CRZ + 0014h Capture Resize Target Image Size Register 1 CRZ_TARSZ1 CRZ + 0018h Capture Resize Horizontal Ratio Register 1 CRZ_HRATIO1 CRZ + 001Ch Capture Resize Vertical Ratio Register 1 CRZ_VRATIO1 CRZ +003Ch Capture Resize Coefficient Table CRZ_GMCBASE CRZ + 0040h Capture Resize Coefficient Table CRZ_FRCFG CRZ+0044h Capture Resize YUV Y-Component Target Memory Base Address Register CRZ_TMBASE_Y CRZ+0048h Capture Resize YUV U-Component Target Memory Base Address Register CRZ_TMBASE_U CRZ+004Ch Capture Resize YUV V-Component Target Memory Base Address CRZ_TMBASE_V 292/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 Register CRZ+0084h Capture Resize Target Memory Base Address Register 1 CRZ_TMBASE1 CRZ+0088h Capture Resize Target Memory Base Address Register 2 CRZ_TMBASE1 7.2.2.1 Capture Resize Configuration Register CRZ+0000h Bit Name Type Reset Bit 31 Capture Resize Configuration Register 30 29 28 27 26 25 24 15 14 13 12 11 10 9 8 NORG NORF VSRS INTEN INTEN LBSE Name ECV PCON BDB DB TEN [1] [0] L Type R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 1 0 23 22 7 6 CRZ_CFG 21 20 LBMAX R/W 0 5 4 19 18 17 16 3 2 1 0 OUTFMT R/W 0 The register is for global configuration of Capture Resize. OUTFMT The register field specifies which format reszier outputs 0 RGB565 1 YUV420 3 YUV422 Others Reserved Note: If YUV420 or YUV422 is selected, output width will be padded to 16’s multiples. PCON The register bit specifies if pixel-based resizing continues whenever an image finishes processing. Once continuous run for pixel-based resizing is enabled and pixel-based resizing is running, the only way to stop is to reset Capture Resize. If to stop immediately is desired, reset Capture Resize directly. If the last image is desired, set the register bit to ‘0’ first. Then wait until image resizer is not busy again. Finally reset image resizer. 0 Single run 1 Continuous run LBSEL Line buffer selection. 0 CRZ cant work! 1 Dedicated memory. INTEN[0] Frame Done Interrupt Enable. When interrupt is enabled, an interrupt is generated whenever CRZ finishes. 0 Interrupt for is disabled. 1 Interrupt for is enabled. INTEN[1] Frame Start Interrupt Enable. When interrupt is enabled, an interrupt is generated whenever CRZ begin working. 0 Interrupt for is disabled. 1 Interrupt for is enabled. ECV The register field determines whether using ‘ec’ algorithm for vertical downscaling 0 cubic 1 ec. It helps when bandwidth is very critical. VSRSTEN The register field determines whether force reset when vsync arise but previous frame not done yet. 0 Not force reset 293/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 1 Force reset when vsync NORFDB The register field determines not double buffer some registers. 0 Double buffering registers 1 No double buffering registers NORGBDB The register field determines whether base address of RGB565 output switching or not. 0 Auto switching between CRZ_TMBASE1 and CRZ_TMBASE2 1 No auto switching. Always CRZ_TMBASE1. LBMAX Number of lines used in upsampling scenario : WMIN = ((WS > WT) ? WT : WS); // use for Width down, and Height up WMIN_EVEN = WMIN + WMIN%2; (int)(1600 / WMIN_EVEN) * 6; 7.2.2.2 Capture Resize Control Register CRZ+0004h Bit Capture Resize Control Register CRZ_CON 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Name Type Reset Bit 16 PELR ST R/W 0 PELE NA R/W 0 Name Type Reset The register is for global control of Capture Resize. Note that software reset does NOT reset all register settings. Remember to trigger Capture Resize first before triggering image sources to Capture Resize. PELENA PELRST 7.2.2.3 Writing ‘1’ to the register bit causes CRZ proceed to work. Writing ‘1’ to the register causes CRZ to stop immediately and keep in reset state. In order to go to normal state, write ‘0’ to the register bit. Capture Resize Status Register CRZ+0008h Bit Name Type Reset Bit Capture Resize Status Register CRZ_STA 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Name Type Reset 16 0 BUSY BUSYI O RO RO The register indicates global status of Capture Resize. BUSYI Input interface busy. 294/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 Output interface busy. BUSYO 7.2.2.4 Capture Resize Interrupt Register CRZ+000Ch Bit Name Type Reset Bit Capture Resize Interrupt Register CRZ_INT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 15 14 13 12 11 10 9 8 7 6 5 4 3 2 Name Type Reset 17 16 1 0 FSTIN PELIN T T RC RC 0 0 The register shows up the interrupt status of resizer. Interrupt for CRZ. No matter the register bit CRZ_CFG.INTEN[0] is enabled or not, the register bit is active whenever CRZ completes. It could be as software interrupt by polling the register bit. Clear it by reading the register. Interrupt for CRZ. No matter the register bit CRZ_CFG.INTEN[1] is enabled or not, the register bit is active whenever CRZ start working. It could be as software interrupt by polling the register bit. Clear it by reading the register. PELINT FSTINT 7.2.2.5 Capture Resize Source Image Size Register 1 CRZ+0010h Bit Name Type Bit Name Type 31 Capture Resize Source Image Size Register 1 30 29 28 27 26 25 24 CRZ_SRCSZ1 23 22 21 20 19 18 17 16 7 6 5 4 3 2 1 0 HS R/W 15 14 13 12 11 10 9 8 WS R/W The register specifies the size of source image after coarse shrink process. The allowable maximum size is 4095x4095 with limitation written in application notes. WS HS The register field specifies the width of source image after coarse shrink process. 1 The width of source image after coarse shrink process is 1. 2 The width of source image is 2. … The register field specifies the height of source image after coarse shrink process. 1 The height of source image after coarse shrink process is 1. 2 The height of source image after coarse shrink process is 2. … 295/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 7.2.2.6 Capture Resize Target Image Size Register 1 CRZ+0014h Bit Name Type Bit Name Type 31 Capture Resize Target Image Size Register 1 30 29 28 27 26 25 24 CRZ_TARSZ1 23 22 21 20 19 18 17 16 7 6 5 4 3 2 1 0 HT R/W 15 14 13 12 11 10 9 8 WT R/W The register specifies the size of target image. The allowable maximum size is 4095x4095 with limitation written in application notes. WT HT The register field specifies the width of target image. 1 The width of target image is 1. 2 The width of target image is 2. … The register field specifies the height of target image. 1 The height of target image is 1. 2 The height of target image is 2. … 7.2.2.7 Capture Resize Horizontal Ratio Register 1 CRZ+0018h Bit Name Type Bit Name Type Capture Resize Horizontal Ratio Register 31 30 29 28 27 26 25 15 14 13 12 11 10 9 The register specifies horizontal resizing ratio. 24 23 RATIO [31:16] R/W 8 7 RATIO [15:0] R/W CRZ_HRATIO1 22 21 20 19 18 17 16 6 5 4 3 2 1 0 22 21 20 19 18 17 16 6 5 4 3 2 1 0 It is obtained by CRZ_SRCSZ.HS > CRZ_TARSZ.HT ? ((CRZ_TARSZ.HT - 1)* 220 + (CRZ_SRCSZ.HS -1)/2) / (CRZ_SRCSZ.HS -1) : ((CRZ_SRCSZ.HS - 1)* 220 + (CRZ_TARSZ.HT-1)/2) / (CRZ_TARSZ.HT-1). 7.2.2.8 Capture Resize Vertical Ratio Register 1 CRZ+001Ch Bit Name Type Bit Name Type Capture Resize Vertical Ratio Register 1 31 30 29 28 27 26 25 15 14 13 12 11 10 9 The register specifies vertical resizing ratio. 24 23 RATIO [31:16] R/W 8 7 RATIO [15:0] R/W CRZ_VRATIO1 It is obtained by 296/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 CRZ_SRCSZ.VS > CRZ_TARSZ.VT ? ((CRZ_TARSZ.VT - 1)* 220 + (CRZ_SRCSZ.VS -1)/2) / (CRZ_SRCSZ.VS -1) : ((CRZ_SRCSZ.VS - 1)* 220 + (CRZ_TARSZ.VT-1)/2) / (CRZ_TARSZ.VT-1). 7.2.2.9 Capture Resize GMC BASE Register CRZ+003Ch Bit Name Type Reset Bit Name Type Reset Capture Resize Coefficient Table 31 30 29 28 27 15 14 13 12 11 26 CRZ_GMCBASE 25 24 23 22 GMCBASE[31:16] R/W 0 10 9 8 7 6 GMCBASE[15:2] R/W 0 21 20 19 18 17 16 5 4 3 2 1 0 The register specifies the base address of GMC buffer address. It should be word-aligned. And it is meaningful to use internal ram. When CRZ_FRCFG..GMCPIXLE = 0, this register is meaningless. 7.2.2.10 Capture Resize Coefficient Table Register CRZ+0040h Bit Name Type Reset Bit Name Type Reset Capture Resize Coefficient Table 31 30 29 28 27 26 25 15 14 13 12 11 9 0 1 10 USEL R/W 1 0 24 23 GMCPIXEL R/W 0 8 7 CRZ_FRCFG 22 21 20 19 18 17 16 6 5 4 3 1 0 0 1 2 DSEL R/W 1 0 1 1 The register specifies the coefficient table for resizing. Valid number is form 0 to 19. While ‘1’ is the most blur and ‘19’ is the sharpest. ‘0’ is a special case, may or may not sharp than ‘1’. USEL choose ‘USEL’ > 12 may get undesirable result, ‘8’ is recommended. DSEL ‘15’ is recommended. GMCPIXEL Use how many bytes of internal memory as additional resizer buffer. Only even numbers are allowed. 0 Disable this feature. 2 2 pixels; 4 bytes. 4 4 pixels; 8 bytes. 6 6 pixels; 12 bytes. 297/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 … Capture Resize YUV Y-Component Target Memory Base Address Register CRZ+0044h Bit Name Type Bit Name Type 31 30 29 28 27 15 14 13 12 11 26 25 24 23 22 TMBASE_Y[31:16] R/W 10 9 8 7 6 TMBASE_Y[15:2] R/W CRZ_TMBASE_Y 21 20 19 18 17 16 5 4 3 2 1 0 The register specifies the base address of YUV output for Y-component. It should be word-aligned. It’s only useful in YUV mode. Capture Resize YUV U-Component Target Memory Base Address Register CRZ+0048h Bit Name Type Bit Name Type 31 30 29 28 27 15 14 13 12 11 26 25 24 23 22 TMBASE_U[31:16] R/W 10 9 8 7 6 TMBASE_U[15:2] R/W CRZ_TMBASE_U 21 20 19 18 17 16 5 4 3 2 1 0 The register specifies the base address of YUV output for U-component. It should be word-aligned. It’s only useful in mode. CRZ+004Ch Bit Name Type Bit Name Type Capture Resize YUV V-Component Target Memory Base Address Register 31 30 29 28 27 15 14 13 12 11 26 25 24 23 22 TMBASE_V[31:16] R/W 10 9 8 7 6 TMBASE_V[15:2] R/W CRZ_TMBASE_V 21 20 19 18 17 16 5 4 3 2 1 0 The register specifies the base address of YUV output for V-component. It should be word-aligned. It’s only useful in YUV mode. Capture Resize Target Memory Base Address Register CRZ+0084h Bit Name Type Bit Name Type 31 30 29 28 27 26 15 14 13 12 11 10 25 24 23 22 TMBASE1 [31:16] R/W 9 8 7 6 TMBASE1 [15:1] R/W 298/599 CRZ_TMBASE1 21 20 19 18 17 16 5 4 3 2 1 0 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 The register specifies the base address of target memory for RGB565 mode. Target memory is memory space for destination of YUV2RGB. It’ must be half-word (2 bytes) aligned. RESZ_TMBASE1 and RESZ_TMBASE2 are auto-switched by hardware, so both two registers should be filled. If dual buffer is not required, please fill these two registers with the same value. Capture Resize Target Memory Base Address Register CRZ+0088h Bit Name Type Bit Name Type 31 30 29 28 27 26 15 14 13 12 11 10 25 24 23 22 TMBASE2 [31:16] R/W 9 8 7 6 TMBASE2 [15:1] R/W CRZ_TMBASE2 21 20 19 18 17 16 5 4 3 2 1 0 The register specifies the base address of target memory for RGB565 mode. Target memory is memory space for destination of YUV2RGB. It’ must be half-word (2 bytes) aligned. RESZ_TMBASE1 and RESZ_TMBASE2 are auto-switched by hardware, so both two registers should be filled. If dual buffer is not required, please fill these two registers with the same value. 7.2.3 z Application Notes SRCSZ and TARSZ limitation for upscaling CRZ_SRCSZ.WS >= 3; CRZ_SRCSZ.HS >= 3; (CRZ_TARSZ.WT-1) / (CRZ_SRCSZ.WS-1) <= 64; z SRCSZ and TARSZ limitation for downcaling 2 <= CRZ_TARSZ.WT <= 1600; 2 <= CRZ_TARSZ.HT <= 1600; (CRZ_TARSZ.WT-1) / (CRZ_SRCSZ.WS-1) >= 1/2048; z Configuration procedure for pixel-based image sources CRZ_SRCSZ = source image size; CRZ_TARSZ = target image size; CRZ_CFG.LBSEL = 1; // must be 1, crz cant work when set to 0 CRZ_CFG.OUTFMT = 3 or 1 or 0; WMIN = (WS > WT) ? WT : WS; // use for Width down and Height up WMIN_EVEN = WMIN + WMIN%2; CRZ_CFG.LBMAX = (int)(1600/ WMIN_EVEN) * 6; CRZ_HRATIO = horizontal ratio; CRZ_VRATIO = vertical ratio; CRZ_TMBASE* CRZ_CON = 0x1; 299/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 7.3 NAND FLASH interface 7.3.1 General description MT6235 provides NAND flash interface. The NAND FLASH interface support features as follows: z ECC (Hamming code) acceleration capable of one-bit error correction or two bits error detection. z Programmable ECC block size. Support 1, 2 or 4 ECC block within a page. z Word/byte access through APB bus. z Direct Memory Access for massive data transfer. z Latch sensitive interrupt to indicate ready state for read, program, erase operation and error report. z Programmable wait states, command/address setup and hold time, read enable hold time, and write enable recovery time. z Support page size: 512(528) bytes and 2048(2112) bytes. z Support 2 chip select for NAND flash parts. z Support 8/16 bits I/O interface. The NFI core can automatically generate ECC parity bits when programming or reading the device. If the user approves the way it stores the parity bits in the spare area for each page, the AUTOECC mode can be used. Otherwise, the user can prepare the data (may contains operating system information or ECC parity bits) for the spare area with another arrangement. In the former case, the core can check the parity bits when reading from the device. The ECC module features the hamming code, which is capable of correcting one bit error or detecting two bits error within one ECC block. 7.3.2 Registers Memory Map Software responsibility and controllable functions Register Address Acronym Register Function NFI +0000h NFI_ACCCON NAND Flash Access Control NFI +0004h NFI_PAGEFMT NFI Page Format Control NFI +0008h NFI_OPCON Operation Control NFI +0010h NFI_CMD Command NFI +0020h NFI_ADDRNOB Address Length NFI +0024h NFI_ADDRL Least Significant Address NFI +0028h NFI_ADDRM Most Significant Address NFI +0030h NFI_DATAW Write Data Buffer NFI +0034h NFI_DATAWB Write Data Buffer for Byte Access 300/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 NFI +0038h NFI_DATAR Read Data Buffer NFI +003Ch NFI_DATARB Read Data Buffer for Byte Access NFI +0040h NFI_PSTA NFI Status NFI +0044h NFI_FIFOSTA NFI FIFO Status NFI +0050h NFI_FIFODATA0 NFI FIFO Data 0 NFI +0054h NFI_FIFODATA1 NFI FIFO Data 1 NFI +0058h NFI_FIFODATA2 NFI FIFO Data 2 NFI +005Ch NFI_FIFODATA3 NFI FIFO Data 3 NFI +0060h NFI_CON NFI Control NFI +0064h NFI_INTR NFI Interrupt Status NFI +0068h NFI_INTR_EN NFI Interrupt Enable NFI +0070h NFI_PAGECNTR NAND Flash Page Counter NFI +0074h NFI_ADDRCNTR NAND Flash Page Address Counter Main Area ECC NFI +0080h NFI_SYM0_ADDR ECC Block 0 Parity Error Detect Syndrome Address NFI +0084h NFI_SYM1_ADDR ECC Block 1 Parity Error Detect Syndrome Address NFI +0088h NFI_SYM2_ADDR ECC Block 2 Parity Error Detect Syndrome Address NFI +008Ch NFI_SYM3_ADDR ECC Block 3 Parity Error Detect Syndrome Address NFI +0090h NFI_SYM4_ADDR ECC Block 4 Parity Error Detect Syndrome Address NFI +0094h NFI_SYM5_ADDR ECC Block 5 Parity Error Detect Syndrome Address NFI +0098h NFI_SYM6_ADDR ECC Block 6 Parity Error Detect Syndrome Address NFI +009Ch NFI_SYM7_ADDR Spare ECC Block 7 Parity Error Detect Syndrome Address NFI +00A0h NFI_SYMS0_ADDR Spare ECC Block 0 Parity Error Detect Syndrome Address NFI +00A4h NFI_SYMS1_ADDR Spare ECC Block 1 Parity Error Detect Syndrome Address NFI +00A8h NFI_SYMS2_ADDR Spare ECC Block 2 Parity Error Detect Syndrome Address NFI +00ACh NFI_SYMS3_ADDR Spare ECC Block 3 Parity Error Detect Syndrome Address NFI +00B0h NFI_SYM0_DATA ECC Block 0 Parity Error Detect Syndrome Word NFI +00B4h NFI_SYM1_DATA ECC Block 1 Parity Error Detect Syndrome Word NFI +00B8h NFI_SYM2_DATA ECC Block 2 Parity Error Detect Syndrome Word NFI +00BCh NFI_SYM3_DATA ECC Block 3 Parity Error Detect Syndrome Word NFI +00C0h NFI_SYM4_DATA ECC Block 4 Parity Error Detect Syndrome Word NFI +00C4h NFI_SYM5_DATA ECC Block 5 Parity Error Detect Syndrome Word 301/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 NFI +00C8h NFI_SYM6_DATA ECC Block 6 Parity Error Detect Syndrome Word NFI +00CCh NFI_SYM7_DATA ECC Block 7 Parity Error Detect Syndrome Word NFI +00D0h NFI_SYMS0_DATA Spare ECC Block 0 Parity Error Detect Syndrome Word NFI +00D4h NFI_SYMS1_DATA Spare ECC Block 1 Parity Error Detect Syndrome Word NFI +00D8h NFI_SYMS2_DATA Spare ECC Block 2 Parity Error Detect Syndrome Word NFI +00DCh NFI_SYMS3_DATA Spare ECC Block 3 Parity Error Detect Syndrome Word NFI +00E0h NFI_PAR_0P NFI ECC Parity Word 0 NFI +00E4h NFI_PAR_0C NFI ECC Parity Word 0 NFI +00E8h NFI_PAR_1P NFI ECC Parity Word 1 NFI +00ECh NFI_PAR_1C NFI ECC Parity Word 1 NFI +00F0h NFI_PAR_2P NFI ECC Parity Word 2 NFI +00F4h NFI_PAR_2C NFI ECC Parity Word 2 NFI +00F8h NFI_PAR_3P NFI ECC Parity Word 3 NFI +00FCh NFI_PAR_3C NFI ECC Parity Word 3 NFI +0100h NFI_PAR_4P NFI ECC Parity Word 4 NFI +0104h NFI_PAR_4C NFI ECC Parity Word 4 NFI +0108h NFI_PAR_5P NFI ECC Parity Word 5 NFI +010Ch NFI_PAR_5C NFI ECC Parity Word 5 NFI +0110h NFI_PAR_6P NFI ECC Parity Word 6 NFI +0114h NFI_PAR_6C NFI ECC Parity Word 6 NFI +0118h NFI_PAR_7P NFI ECC Parity Word 7 NFI +011Ch NFI_PAR_7C NFI ECC Parity Word 7 NFI +0120h NFI_PARS_0P NFI Spare ECC Parity Word 0 NFI +0124h NFI_PARS_0C NFI Spare ECC Parity Word 0 NFI +0128h NFI_PARS_1P NFI Spare ECC Parity Word 1 NFI +012Ch NFI_PARS_1C NFI Spare ECC Parity Word 1 NFI +0130h NFI_PARS_2P NFI Spare ECC Parity Word 2 NFI +0134h NFI_PARS_2C NFI Spare ECC Parity Word 2 NFI +0138h NFI_PARS_3P NFI Spare ECC Parity Word 3 NFI +013Ch NFI_PARS_3C NFI Spare ECC Parity Word 3 NFI +0140h NFI_ECCDET NFI ECC Error Detect Indication NFI +0144h NFI_PARECC NFI ECC Parity Error Indication NFI +0148h NFI_SCON NFI Spare ECC Control I/O Pin Control NFI +0200h NFI_CSEL NAND Flash Device Select 302/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 NFI_IOCON NFI +0204h NFI IO Control Table 5 Registers Memory Map Table 7.3.3 Register definition NFI+0000h Bit Name Type Reset Bit Name Type Reset 31 15 NAND flash access control register 30 29 LCD2NAND R/W 0 14 13 W2R R/W 0 28 27 26 12 11 10 NFI_ACCCON 25 24 23 22 21 20 9 8 7 6 5 4 WH R/W 0 WST R/W 0 19 18 17 C2R R/W 0 3 2 1 RLT R/W 0 16 0 This is the timing access control register for the NAND FLASH interface. In order to accommodate operations for different system clock frequency ranges from 13MHz to 52MHz, wait states and setup/hold time margin can be configured in this register. The field represents the minimum required time from NCEB low to NREB low. The field represents the minimum required time from NWEB high to NREB low. It’s in unit of 2T. So the actual time ranges from 2T to 8T in step of 2T. WH Write-enable hold-time. The field specifies the hold time of NALE, NCLE, NCEB signals relative to the rising edge of NWEB. This field is associated with WST to expand the write cycle time, and is associated with RLT to expand the read cycle time. RLT Read Latency Time The field specifies how many wait states to be inserted to meet the requirement of the read access time for the device. 00 No wait state. 01 1T wait state. 10 2T wait state. 11 3T wait state. WST Write Wait State The field specifies the wait states to be inserted to meet the requirement of the pulse width of the NWEB signal. 00 No wait state. 01 1T wait state. 10 2T wait state. 11 3T wait state. LCD2NAND Arbitration Wait State The field specifies the wait states to be inserted for the APB arbitrator when bus user changes. C2R W2R NFI +0004h Bit 15 NFI page format control register 14 13 12 11 10 9 8 303/599 NFI_PAGEFMT 7 6 5 4 3 2 1 0 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 B16E N R/W 0 Name Type Reset ECCBLKSIZE ADRMODE PSIZE R/W 0 R/W 0 R/W 0 This register manages the page format of the device. It includes the bus width selection, the page size, the associated address format, and the ECC block size. B16EN 16 bits I/O bus interface enable. ECCBLKSIZE ECC block size. This field represents the size of one ECC block. The hardware-fuelled ECC generation provides 2 or 4 blocks within a single page. 0 ECC block size: 128 bytes. Used for devices with page size equal to 512 bytes. 1 ECC block size: 256 bytes. Used for devices with page size equal to 512 bytes. 2 ECC block size: 512 bytes. Used for devices with page size equal to 512 (1 ECC block) or 2048 bytes (4 ECC blocks). 3 ECC block size: 1024 bytes. Used for devices with page size equal to 2048 bytes. 4~ Reserved. ADRMODE Address mode. This field specifies the input address format. 0 Normal input address mode, in which the half page identifier is not specified in the address assignment but in the command set. As in Table 28, A7 to A0 identifies the byte address within half a page, A12 to A9 specifies the page address within a block, and other bits specify the block address. The mode is used mostly for the device with 512 bytes page size. 1 Large size input address mode, in which all address information is specified in the address assignment rather than in the command set. As in Table 29, A11 to A0 identifies the byte address within a page. The mode is used for the device with 2048 bytes page size and 8bits I/O interface. 2 Large size input address mode. As in Table 29, A10 to A0 identifies the column address within a page. The mode is used for the device with 2048 byte page size and 16bits I/O interface. First cycle Second cycle NLD7 A7 A16 NLD6 A6 A15 NLD5 A5 A14 NLD4 A4 A13 NLD3 A3 A12 NLD2 A2 A11 NLD1 A1 A10 NLD0 A0 A9 Table 28 Page address assignment of the first type (ADRMODE = 0) NLD7 A7 First cycle Second cycle 0 NLD6 A6 0 NLD5 A5 0 NLD4 A4 0 NLD3 A3 A11 NLD2 A2 A10 NLD1 A1 A9 NLD0 A0 A8 Table 29 Page address assignment of the second type (ADRMODE = 1 or 2) PSIZE Page Size. The field specifies the size of one page for the device. Two most widely used page size are supported. 0 The page size is 512 bytes or 528 bytes (including 512 bytes data area and 16 bytes spare area). 1 The page size is 2048 bytes or 2112 bytes (including 2048 bytes data area and 64 bytes spare area). 2~ Reserved. 304/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 NFI +0008h Bit 15 Operation control register 14 13 12 Name NOB Type Reset W/R 0 11 10 FIFO_ FIFO_ FLUS RST H WO WO 0 0 9 NFI_OPCON 8 7 6 5 4 3 2 1 0 SRD BWR BRD WO 0 R/W 0 R/W 0 This register controls the burst mode and the single of the data access. In burst mode, the core supposes there are one or more than one page of data to be accessed. On the contrary, in single mode, the core supposes there are only less than 4 bytes of data to be accessed. This is recommended to reset the state machine, data FIFO and flush the data FIFO before starting a new command sequence. Burst read mode. Setting this field to be logic-1 enables the data read operation. The NFI core will issue read cycles to retrieve data from the device when the data FIFO is not full or the device is not in the busy state. The NFI core supports consecutive page reading. A page address counter is built in. If the reading reaches to the end of the page, the device will enter the busy state to prepare data of the next page, and the NFI core will automatically pause reading and remain inactive until the device returns to the ready state. The page address counter will restart to count from 0 after the device returns to the ready state and start retrieving data again. BWR Burst write mode. Setting to be logic-1 enables the data burst write operation for DMA operation. Actually the NFI core will issue write cycles once if the data FIFO is not empty even without setting this flag. But if DMA is to be utilized, the bit should be enabled. If DMA is not to be utilized, the bit didn’t have to be enabled. SRD Setting to be logic-1 initializes the one-shot data read operation. It’s mainly used for read ID and read status command, which requires no more than 4 read cycles to retrieve data from the device. NOB The field represents the number of bytes to be retrieved from the device in single mode, and the number of bytes per AHB transaction in both single and burst mode. 0 Read 4 bytes from the device. 1 Read 1 byte from the device. 2 Read 2 bytes from the device. 3 Read 3 bytes from the device. FIFO_RST Reset the state machine and data FIFO. FIFO_FLUSH Flush the data FIFO. BRD NFI +0010h Bit Name Type Reset 15 Command register 14 13 12 11 10 NFI_CMD 9 8 7 6 5 4 3 2 1 0 CMD R/W 45 This is the command input register. The user should write this register to issue a command. Please refer to device datasheet for the command set. The core can issue some associated commands automatically. Please check out register NFI_CON for those commands. Command word. CMD NFI +0020h Bit Name 15 Address length register 14 13 12 11 10 9 NFI_ADDRNOB 8 305/599 7 6 5 4 3 2 1 ADDR_NOB 0 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 Type Reset R/W 0 This register represents the number of bytes corresponding to current command. The valid number of bytes ranges from 1 to 8. The address format depends on what device to be used and what commands to be applied. The NFI core is made transparent to those different situations except that the user has to define the number of bytes. The user should write the target address to the address register NFI_ADDRL before programming this register. ADDR_NOB Number of bytes for the address NFI +0024h Bit Name Type Reset Bit Name Type Reset Least significant address register 31 30 29 15 14 13 28 27 ADDR3 R/W 0 12 11 ADDR1 R/W 0 NFI_ADDRL 26 25 24 23 22 21 10 9 8 7 6 5 20 19 ADDR2 R/W 0 4 3 ADDR0 R/W 0 18 17 16 2 1 0 This defines the least significant 4 bytes of the address field to be applied to the device. Since the device bus width is 1 byte, the NFI core arranges the order of address data to be least significant byte first. The user should put the first address byte in the field ADDR0, the second byte in the field ADDR1, and so on. The n-th address byte. ADDRn NFI +0028h Bit Name Type Reset Bit Name Type Reset Most significant address register 31 30 29 15 14 13 28 27 ADDR7 R/W 0 12 11 ADDR5 R/W 0 NFI_ADDRM 26 25 24 23 22 21 10 9 8 7 6 5 20 19 ADDR6 R/W 0 4 3 ADDR4 R/W 0 18 17 16 2 1 0 This register defines the most significant byte of the address field to be applied to the device. The NFI core supports address size up to 8 bytes. Programming this register implicitly indicates that the number of address field is larger than 4. The n-th address byte. ADDRn NFI +0030h Bit Name Type Reset Bit Name Type Reset Write data buffer 31 30 29 15 14 13 28 27 DW3 R/W 0 12 11 DW1 R/W 0 NFI_DATAW 26 25 24 23 22 21 10 9 8 7 6 5 20 19 DW2 R/W 0 4 3 DW0 R/W 0 18 17 16 2 1 0 This is the write port of the data FIFO. It supports word access. The least significant byte DW0 is to be programmed to the device first, then DW1, and so on. If the data to be programmed is not word aligned, byte write access will be needed. Instead, the user should use another 306/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 register NFI_DATAWB for byte programming. Writing a word to NFI_DATAW is equivalent to writing four bytes DW0, DW1, DW2, DW3 in order to NFI_DATAWB. Be reminded that the word alignment is from the perspective of the user. The device bus is byte-wide. According to the flash’s nature, the page address will wrap around once it reaches the end of the page. Write data byte 3. Write data byte 2. Write data byte 1. Write data byte 0. DW3 DW2 DW1 DW0 NFI +0034h Bit Name Type Reset 15 Write data buffer for byte access 14 13 12 11 10 9 8 NFI_DATAWB 7 6 5 4 3 2 1 0 DW0 R/W 0 This is the write port for the data FIFO for byte access. Write data byte. DW0 NFI +0038h Bit Name Type Reset Bit Name Type Reset 31 Read data buffer 30 29 28 NFI_DATAR 27 26 25 24 23 22 21 11 10 9 8 7 6 5 DR3 RO 0 15 14 13 12 DR1 RO 0 20 19 DR2 RO 0 4 3 DR0 RO 0 18 17 16 2 1 0 This is the read port of the data FIFO. It supports word access. The least significant byte DR0 is the first byte read from the device, then DR1, and so on. Read data byte 3. Read data byte 2. Read data byte 1. Read data byte 0. DR3 DR2 DR1 DR0 NFI +003Ch Bit Name Type Reset 15 Read data buffer for byte access 14 13 12 11 10 9 8 NFI_DATARB 7 6 5 4 3 2 1 0 DR0 RO 0 This is the read port of the data FIFO for byte access. DR0 Read data byte 0. NFI +0040h Bit Name Type Reset 31 NFI status 30 29 28 NFI_PSTA 27 26 25 NAND_FSM RO 0 24 307/599 23 22 21 20 19 18 17 NFI_FSM RO 0 16 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 Bit 15 Name Type Reset 14 13 12 11 10 9 8 NAND _BUS BUSY Y RO RO 0 0* 7 6 5 4 3 2 1 0 DATA DATA ADDR CMD W R RO 0 RO 0 RO 0 RO 0 This register represents the NFI core control status including command mode, address mode, data program and read mode. The user should poll this register for the end of those operations. *The value of BUSY/NAND_BUSY bit depends on the GPIO configuration. If GPIO is configured for NAND flash application, the reset value should be 0, which represents that NAND flash is in idle status. When the NAND flash is busy, the value will be 1. BUSY NAND_BUSY DATAW DATAR ADDR CMD NFI_FSM 0000 0001 0010 0011 0100 0101 1000 1001 NAND_FSM 00000 00101 00110 00111 00100 01001 01010 01011 01000 01100 10001 10010 10011 11000 11001 11010 11011 Synchronized busy signal from the NAND flash. It’s read-only. This signal is sampled from NFI Asynchronized busy signal from the output pin of the NAND flash. It’s read-only. The NFI core is in data write mode. The NFI core is in data read mode. The NFI core is in address mode. The NFI core is in command mode. The field represents the state of NFI internal FSM. idle. reset. Reset command to ready read busy. read data. program busy program data. Input data command to program command erase busy. Erase command to ready erase data. Erase command 1 to erase command 2 The field represents the state of NAND interface FSM. IDLE. idle. CMD_WRST. command write set up CMD_WR. Command write enable. CMD_WRHD. Command write hold. CMD_WRRDY ADDR_WRST. Address write set up ADDR_WR. Address write enable ADDR_WRHD. Address write hold ADDR_WRRDY. CA2DEXT. Command address write extension. DATA_RDST. Data read set up. DATA_RD. Data read enable. DATA_RDHD. Data read hold. DATA_WRRDY. DATA_WRST. Data write set up. DATA_WR. Data write enable. DATA_WRHD. Data write hold. 308/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 NFI +0044h FIFO Status Bit 15 14 WR_F WR_E Name ULL MPTY Type RO RO Reset 0 1 13 12 NFI_FIFOSTA 11 10 9 8 WR_REMAIN RO 0 7 6 RD_F RD_E ULL MPTY RO RO 0 1 5 4 3 2 1 0 RD_REMAIN RO 0 The register represents the status of the data FIFO. WR_FULL WR_EMPTY RD_FULL RD_EMPTY RD_REMAIN Data FIFO full in burst write mode. Data FIFO empty in burst write mode. Data FIFO full in burst read mode. Data FIFO empty in burst read mode. Data FIFO remaining byte number in burst read mode. WR_REMAIN Data FIFO remaining byte number in burst write mode. NFI +0050h Bit Name Type Reset Bit Name Type Reset FIFO Content Data 0 NFI_FIFODATA0 31 30 29 28 27 26 25 15 14 13 12 11 10 9 24 23 FIFO_DATA0 RO 0 8 7 FIFO_DATA0 RO 0 22 21 20 19 18 17 16 6 5 4 3 2 1 0 This register represents the content data 0 of fifo. NFI +0054h Bit Name Type Reset Bit Name Type Reset FIFO Content Data 1 NFI_FIFODATA1 31 30 29 28 27 26 25 15 14 13 12 11 10 9 24 23 FIFO_DATA1 RO 0 8 7 FIFO_DATA1 RO 0 22 21 20 19 18 17 16 6 5 4 3 2 1 0 24 23 FIFO_DATA2 RO 0 8 7 FIFO_DATA2 RO 0 22 21 20 19 18 17 16 6 5 4 3 2 1 0 This register represents the content data 1 of fifo. NFI +0058h Bit Name Type Reset Bit Name Type Reset FIFO Content Data 2 NFI_FIFODATA2 31 30 29 28 27 26 25 15 14 13 12 11 10 9 This register represents the content data 2 of fifo. 309/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 NFI +005Ch Bit Name Type Reset Bit Name Type Reset FIFO Content Data 3 NFI_FIFODATA3 31 30 29 28 27 26 25 15 14 13 12 11 10 9 24 23 FIFO_DATA3 RO 0 8 7 FIFO_DATA3 RO 0 22 21 20 19 18 17 16 6 5 4 3 2 1 0 6 5 This register represents the content data 3 of fifo. NFI +0060h Bit 15 Name BYTE _RW NFI control 14 13 12 NFI_CON 11 10 9 8 MAIN SPAR _ECC E_EC _EN C_EN Type R/W Reset 0 R/W 0 R/W 0 7 4 MULTI DMA_ SPAR _PAG PAUS E_EN E_RD E_EN _EN R/W R/W R/W 0 0 0 3 AUTO ECC_ ENC_ EN R/W 0 2 1 0 AUTO DMA_ DMA_ ECC_ WR_E RD_E DEC_ N N EN R/W R/W R/W 0 0 0 The register controls the DMA and ECC functions. For all field, Setting to be logic-1 represents enabled, while 0 represents disabled. BYTE_RW SPARE_EN MULTI_PAGE_RD_EN AUTOECC_ENC_EN AUTOECC_DEC_EN DMA_WR_EN DMA_RD_EN DMA_PAUSE_EN This field is used to enable generation of ECC parities for main area. This field is used to enable generation of ECC parities for spare area. If SPARE_EN is not set, however, the mode can’t be enabled since the core can’t access the spare area. MAIN_ECC_EN SPARE_ECC_EN NFI +0064h Bit Name Type 31 Enable byte access. The valid bytes read from NFI_DATAR and NFI_DATAW is only DR0 and DW0 if BYTE_RW is enabled. If enabled, the NFI core allows the user to program or read the spare area directly. Otherwise, the spare area can be programmed or read by the core. Multiple page burst read enable. If enabled, the burst read operation could continue through multiple pages within a block. It’s also possible and more efficient to associate with DMA scheme to read a sector of data contained within the same block. Automatic ECC encoding enable. If enabled, the ECC parity is written automatically to the spare area. If disable ECC encoding engine, it write the default parity in the spare area. Automatic ECC decoding enabled, the error checking and correcting are performed automatically on the data read from the memory and vice versa. If enabled, when the page address reaches the end of the data read of one page This field is used to control the activity of DMA write transfer. This field is used to control the activity of DMA read transfer. DMA pause Interrupt status register 30 29 NFI_INTR 28 27 26 25 24 23 22 21 20 19 18 17 16 BUSY ERRS ERRS ERRS ERRS ERR_ ERR_ ERR_ ERR_ ERR_ ERR_ ERR_ ERR_ _RET _COR _COR _COR _COR COR7 COR6 COR5 COR4 COR3 COR2 COR1 COR0 0 1 2 3 URN RC RC RC RC RC RC RC RC RC RC RC RC RC 310/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 Reset Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RD ERAS RESE ERRS ERRS ERRS ERRS WR_C _COM ERR_ ERR_ ERR_ ERR_ ERR_ ERR_ ERR_ ERR_ E_CO T_CO _DET _DET _DET _DET OMPL Name DET7 DET6 DET5 DET4 DET3 DET2 DET1 DET0 PLET MPLE MPLE 0 1 2 3 ETE E TE TE Type RC RC RC RC RC RC RC RC RC RC RC RC RC RC RC RC Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 The register indicates the status of all the interrupt sources. Read this register will clear all interrupts. Indicates that the device state returns from busy by inspecting the R/B# pin. Indicates that the single bit error in ECC block n needs to be corrected. Indicates an uncorrectable error in ECC block n. Indicates that the single bit error in spare ECC block n needs to be corrected. Indicates an uncorrectable error in spare ECC block n. Indicates that the erase operation is completed. Indicates that the reset operation is completed. Indicates that the write operation is completed. Indicates that the single page read operation is completed. BUSY_RETURN ERR_CORn ERR_DETn ERRS_CORn ERRS_DETn ERASE_COMPLETE RESET_COMPLETE WR_COMPLETE RD_COMPLETE NFI +0068h Bit 31 Interrupt enable register 30 29 Name Type Reset Bit 15 ERAS E_CO Name MPLE TE_E N Type R/W Reset 0 14 RESE T_CO MPLE TE_E N R/W 0 13 28 BUSY _RET URN_ EN R/W 0 12 27 26 25 NFI_INTR_EN 24 23 22 21 20 19 18 17 16 ERRS ERRS ERRS ERRS ERR_ ERR_ ERR_ ERR_ ERR_ ERR_ ERR_ ERR_ _COR _COR _COR _COR COR7 COR6 COR5 COR4 COR3 COR2 COR1 COR0 3_EN 2_EN 1_EN 0_EN _EN _EN _EN _EN _EN _EN _EN _EN R/W 0 11 R/W 0 10 R/W 0 9 R/W 0 8 R/W 0 7 R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 WR_C RD_ ERRS ERRS ERRS ERRS ERR_ ERR_ ERR_ ERR_ ERR_ ERR_ ERR_ ERR_ OMPL COMP _DET _DET _DET _DET DET7 DET6 DET5 DET4 DET3 DET2 DET1 DET0 ETE_ LETE 3_EN 2_EN 1_EN 0_EN _EN _EN _EN _EN _EN _EN _EN _EN _EN EN R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 This register controls the activity for the interrupt sources. ERR_CORn_EN ERR_DETn_EN ERRS_DETn_EN ERRS_DETn_EN BUSY_RETURN_EN ERASE_COMPLETE_EN RESET_COMPLETE_EN WR_COMPLETE_EN RD_COMPLETE_EN NFI+0070h Bit 15 The error correction interrupt enable for the n ECC block. The error detection interrupt enable for the n ECC block. The error detection interrupt enable for the n spare ECC block. The error detection interrupt enable for the n spare ECC block. The busy return interrupt enable. The erase completion interrupt enable. The reset completion interrupt enable. The single page write completion interrupt enable. The single page read completion interrupt enable. NAND flash page counter 14 13 12 11 10 9 NFI_PAGECNTR 8 311/599 7 6 5 4 3 2 1 0 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 Name Type Reset CNTR RO 0 The register represents the number of pages that the NFI has read since the issuing of the read command. For some devices, the data can be read consecutively through different pages without the need to issue another read command. The user can monitor this register to know current page count, particularly when read DMA is enabled. The page counter. CNTR NFI+0074h Bit Name Type Reset 15 NAND flash page address counter 14 13 12 11 10 9 8 7 NFI_ADDRCNTR 6 5 CNTR RO 0 4 3 2 1 0 The register represents the current read/write address with respect to initial address input. It counts in unit of byte. In page read and page program operation, the address should be the same as that in the state machine in the target device. NFI supports the address counter up to 4096 bytes. The address count. CNTR NFI +0080h Bit Name Type Reset 15 ECC block 0 parity error detect syndrome address 14 13 12 11 10 9 8 7 6 5 NFI_ SYM0_ADDR 4 3 2 1 0 SYM RO 0 This register identifies the address within ECC block 0 that a single bit error has been detected. SYM The byte address of the error-correctable bit. Register Address Register Function Acronym NFI +0080h NFI ECC Syndrome address 0 NFI_SYM0_ADDR NFI +0084h NFI ECC Syndrome address 1 NFI_SYM1_ADDR NFI +0088h NFI ECC Syndrome address 2 NFI_SYM2_ADDR NFI +008Ch NFI ECC Syndrome address 3 NFI_SYM3_ADDR NFI +0090h NFI ECC Syndrome address 4 NFI_SYM4_ADDR NFI +0094h NFI ECC Syndrome address 5 NFI_SYM5_ADDR NFI +0098h NFI ECC Syndrome address 6 NFI_SYM6_ADDR NFI +009Ch NFI ECC Syndrome address 7 NFI_SYM7_ADDR NFI +00A0h NFI Spare ECC Syndrome address 0 NFI_SYMS0_ADDR NFI +00A4h NFI Spare ECC Syndrome address 1 NFI_SYMS1_ADDR NFI +00A8h NFI Spare ECC Syndrome address 2 NFI_SYMS2_ADDR NFI +00ACh NFI Spare ECC Syndrome address 3 NFI_SYMS3_ADDR Table 30 NFI Syndrome address register table 312/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 NFI +00B0h Bit Name Type Reset Bit Name Type Reset 31 ECC block 0 parity error detect syndrome word 30 29 28 27 26 25 24 23 22 21 11 10 9 8 7 6 5 ED3 RO 0 15 14 13 12 ED1 RO 0 NFI_SYM0_DATA 20 19 ED2 RO 0 4 3 ED0 RO 0 18 17 16 2 1 0 This register represents the syndrome word for the corrected ECC block 0. To correct the error, the user should first read NFI_ SYM0_ADDR for the address of the correctable word, and then read NFI_SYM0_DAT, directly XOR the syndrome word with the data word to obtain the correct word. Register Address Register Function Acronym NFI +00B0h NFI ECC Syndrome data 0 NFI_SYM0_DATA NFI +00B4h NFI ECC Syndrome data 1 NFI_SYM1_DATA NFI +00B8h NFI ECC Syndrome data 2 NFI_SYM2_DATA NFI +00BCh NFI ECC Syndrome data 3 NFI_SYM3_DATA NFI +00C0h NFI ECC Syndrome data 4 NFI_SYM4_DATA NFI +00C4h NFI ECC Syndrome data 5 NFI_SYM5_DATA NFI +00C8h NFI ECC Syndrome data 6 NFI_SYM6_DATA NFI +00CCh NFI ECC Syndrome data 7 NFI_SYM7_DATA NFI +00D0h NFI Spare ECC Syndrome data 0 NFI_SYMS0_DATA NFI +00D4h NFI Spare ECC Syndrome data 1 NFI_SYMS1_DATA NFI +00D8h NFI Spare ECC Syndrome data 2 NFI_SYMS2_DATA NFI +00DCh NFI Spare ECC Syndrome data 3 NFI_SYMS3_DATA Table 4 NFI Syndrome data register table NFI +00E0h Bit Name Type Reset 15 NFI ECC parity word 0 14 13 12 11 10 NFI_PAR_0P 9 8 7 6 PAR RO 0 5 4 3 2 1 0 This register represents the ECC parity for the ECC block 0. It’s calculated by the NFI core and can be read by the user. It’s generated when writing or reading a page. Register Address Register Function Acronym NFI +00E0h NFI ECC parity word 0 NFI_PAR_0P NFI +00E4h NFI ECC parity word 0 NFI_PAR_0C NFI +00E8h NFI ECC parity word 1 NFI_PAR_1P NFI +00ECh NFI ECC parity word 1 NFI_PAR_1C NFI +00F0h NFI ECC parity word 2 NFI_PAR_2P 313/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 NFI +00F4h NFI ECC parity word 2 NFI_PAR_2C NFI +00F8h NFI ECC parity word 3 NFI_PAR_3P NFI +00FCh NFI ECC parity word 3 NFI_PAR_3C NFI +0100h NFI ECC parity word 4 NFI_PAR_4P NFI +0104h NFI ECC parity word 4 NFI_PAR_4C NFI +0108h NFI ECC parity word 5 NFI_PAR_5P NFI +010Ch NFI ECC parity word 5 NFI_PAR_5C NFI +0110h NFI ECC parity word 6 NFI_PAR_6P NFI +0114h NFI ECC parity word 6 NFI_PAR_6C NFI +0118h NFI ECC parity word 7 NFI_PAR_7P NFI +011Ch NFI ECC parity word 7 NFI_PAR_7C NFI +0120h NFI ECC parity word 0 NFI_PARS_0P NFI +0124h NFI ECC parity word 0 NFI_PARS_0C NFI +0128h NFI ECC parity word 1 NFI_PARS_1P NFI +012Ch NFI ECC parity word 1 NFI_PARS_1C NFI +0130h NFI ECC parity word 2 NFI_PARS_2P NFI +0134h NFI ECC parity word 2 NFI_PARS_2C NFI +0138h NFI ECC parity word 3 NFI_PARS_3P NFI +013Ch NFI ECC parity word 3 NFI_PARS_3C Table 5 NFI parity bits register table NFI +0140h Bit NFI ECC error detect indication register 31 30 29 28 15 14 13 12 Name Type Reset Bit Name Type Reset NFI_ERRDET 27 26 25 24 23 22 21 20 19 18 17 16 CES_ CES_ CES_ CES_ CE_B CE_B CE_B CE_B CE_B CE_B CE_B CE_B BLK3 BLK2 BLK1 BLK0 LK7 LK6 LK5 LK4 LK3 LK2 LK1 LK0 RO RO RO RO RO RO RO RO RO RO RO RO 0 0 0 0 0 0 0 0 0 0 0 0 11 10 9 8 7 6 5 4 3 2 1 0 ESBL ESBL ESBL ESBL EBLK EBLK EBLK EBLK EBLK EBLK EBLK EBLK K3 K2 K1 K0 7 6 5 4 3 2 1 0 RO RO RO RO RO RO RO RO RO RO RO RO 0 0 0 0 0 0 0 0 0 0 0 0 This register identifies the block in which an uncorrectable error has been detected. EBLKn CE_BLKn ESBLKn CES_BLKn The uncorrectable errors in the block n. The correctable error of the block n. The uncorrectable errors in the spare block n. The correctable error of the spare block n. NFI +0144h Bit Name Type 31 NFI ECC parity error indication register 30 29 28 NFI_PARERR 27 26 25 24 23 22 21 20 19 18 17 16 PES_ PES_ PES_ PES_ PE_B PE_B PE_B PE_B PE_B PE_B PE_B PE_B BLK3 BLK2 BLK1 BLK0 LK7 LK6 LK5 LK4 LK3 LK2 LK1 LK0 RO RO RO RO RO RO RO RO RO RO RO RO 314/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 Reset Bit 15 14 13 12 Name Type Reset 0 0 0 0 0 0 0 0 0 0 0 0 11 10 9 8 7 6 5 4 3 2 1 0 NO_E NO_E NO_E NO_E NO_E NO_E NO_E NO_E NO_E NO_E NO_E NO_E SBLK SBLK SBLK SBLK BLK7 BLK6 BLK5 BLK4 BLK3 BLK2 BLK1 BLK0 3 2 1 0 RO RO RO RO RO RO RO RO RO RO RO RO 0 0 0 0 0 0 0 0 0 0 0 0 This register identifies the block in which an uncorrectable error has been detected. NO_EBLKn PE_BLKn NO_ESBLKn PES_BLKn No errors in the block n. The correctable error in parities of the block n. No errors in the spare block n. The correctable error in parities of the spare block n. NFI+0148h NFI Spare ECC Control register Bit Name Type Reset 15 14 13 12 11 10 9 8 SPARE_ECC_STR R/W 0 NFI_SCON 7 6 5 4 3 2 1 0 SPARE_ECC_NUM R/W 0 The register is used to control ECC for spare data. SPARE_ECC_NUM byte number in spare for ECC. (0-8) SPARE_ECC_STR start byte number in spare for ECC. (0-7) NFI+0200h Bit Name Type Reset 15 NFI device select register 14 13 12 11 10 9 NFI_CSEL 8 7 6 5 4 3 2 1 0 CSEL R/W 0 The register is used to select the target device. It decides which CEB pin to be functional. This is useful while using the high-density device. CSEL Chip select. The value defaults to 0. 0 Device 1 is selected. 1 Device 2 is selected. NFI+0204h Bit 15 NFI IO Control register 14 13 12 11 10 NFI_IOCON 9 8 Name Type Reset 7 6 5 4 3 2 1 0 NLD_ PD R/W 0 Data bus pull down when no use. NLD_PD 0 1 data bus pull down when no use. disable. enable. 315/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 7.3.4 Device timing control This section illustrates the timing diagram. The ideal timing for write access is listed as listed in Table 31. Parame ter Description Timing specification TWC1 Write cycle time TWC2 3T + WST + WH Timing at 13MHz Timing at 26MHz Timing at 52MHz (WST, WH) = (0,0) (WST, WH) = (0,0) (WST, WH) = (1,0) 230.8ns 105.4ns 76.9ns Write cycle time 2T + WST + WH 153.9ns 76.9ns 57.7ns TDS Write data setup time 1T + WST 76.9ns 38.5ns 38.5ns TDH Write data hold time 1T + WH 76.9ns 38.5ns 19.2ns TWP Write enable time 1T + WST 76.9ns 38.5ns 38.5ns TWH Write high time 1T + WH 76.9ns 38.5ns 19.2ns TCLS Command latch enable setup time 1T 76.9ns 38.5ns 19.2ns TCLH Command latch enable hold time 1T + WH 76.9ns 38.5ns 19.2ns TALS Address latch enable setup time 1T 76.9ns 38.5ns 19.2ns TALH Address latch enable hold time 1T + WH 76.9ns 38.5ns 19.23ns FWC Write data rate 1 / TWC2 6.5Mbytes/s 13Mbytes/s 17.3Mbytes/s Table 31 Write access timing HCLK WST NCLE tCLS, tALS tCLH, tALH NALE tWP NWEB tDS tDH command NLD tCES tCEH NCEB tWC1 Figure 36 Command input cycle (1 wait state). 316/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 HCLK WST WST WST NCLE tCLH tCLS NALE tWC2 tWC1 tALS tALH tWP tWP NWEB tWP tWH A0 NLD A1 tDH OE (internal) NCEB tWH A2 tDH tDH tCEH tCES Figure 37 Address input cycle (1 wait state) HCLK WST NCLE WST WST tCLS tCLH tWC1 tWC2 NALE tWC2 tALS tALH tWP tWP NWEB tWP tWH D0 NLD D526 tDH OE (internal) NCEB tWH D527 tDH tDH tCEH tCES Figure 38 Consecutive data write cycles (1 wait state, 0 hold time extension) 317/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 HCLK WST WH WH WST tCLS NCLE tCLH tWC1 tWC2 NALE tALS tALH tWP NWEB tWP tWH D0 NLD tDH OE (internal) NCEB D527 tDH tCES tCEH Figure 39 Consecutive data write cycles (1 wait state, 1 hold time extension) The ideal timing for read access is as listed in Table 18. Parame ter Description TRC1 Timing specification Timing at 13MHz Timing at 26MHz Timing at 52MHz (RLT, WH) = (0,0) (RLT, WH) = (1,0) (RLT, WH) = (2,0) Read cycle time 3T + RLT + WH 230.8ns 153.8ns 96.2ns TRC2 Read cycle time 2T + RLT + WH 153.9ns 115.4ns 76.9ns TDS Read data setup time 1T + RLT 76.9ns 76.9ns 57.7ns TDH Read data hold time 1T + WH 76.9ns 38.5ns 19.2ns TRP Read enable time 1T + RLT 76.9ns 76.9ns 57.7ns TRH Read high time 1T + WH 76.9ns 38.5ns 19.2ns TCLS Command latch enable setup time 1T 76.9ns 38.5ns 19.2ns TCLH Command latch enable hold time 1T + WH 76.9ns 38.5ns 19.2ns TALS Address latch enable setup time 1T 76.9ns 38.5ns 19.2ns TALH Address latch enable hold time 1T + WH 76.9ns 38.5ns 19.2ns FRC Write data rate 1 / TRC2 6.5Mbytes/s 8.7Mbytes/s 13Mbytes/s Table 32 Read access timing 318/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 HCLK RLT RLT WH WH NCLE tCLS tCLH, tALH NALE tWH tALS tWP NREB tDH tDH D0 NLD D527 OE (internal) NCEB tCES tCEH Figure 40 Serial read cycle (1 wait state, 1 hold time extension) HCLK RLT RLT W2R NCLE tCLS tCLH NALE tALS tALH tWP NWEB tWHR NREB tRP tDH tDS Status 70h NLD tCES tCEH NCEB OE (internal) Figure 41 Status read cycle (1 wait state) 319/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 HCLK NCLE tCLS tCLH NALE tALS tALH tWP tWP NWEB tWHR NREB tDH tDS 90h NLD tDH tDS tRP 01h, 06h 00h tCES tCEH NCEB OE (internal) Figure 42 ID and manufacturer read (0 wait state) 7.4 USB 2.0 High-Speed Dual-Role Controller 7.4.1 General Description The USB2.0 Controller can support 4 Tx and 3 Rx endpoints(excluding Endpoint 0). These endpoints can be individually configured in software to handle either Bulk transfers, Interrupt transfers or Isochronous transfers. There are 4 DMA channels and the embedded RAM size is 4Kbytes. The embedded RAM can be dynamically configured to each endpoint. Here is provided features. Operates as the peripheral in point-to-point communications with another USB function Complies with the USB 2.0 standard for high-speed (480Mbps) functions Supports point-to-point communications with one high- or full-speed device Supports Suspend and Resume signaling Supports High-Bandwidth Isochronous & Interrupt transfers UTMI+ Level 2 Transceiver Interface Synchronous RAM interface for FIFOs Support for DMA access to FIFOs Software connect/disconnect option Supports multi-layer operations on the AHB bus Performs all transaction scheduling in hardware 320/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 The USB2.0 Controller Block Diagram is as illustrated. Endpoint Control CPU Interface Packet Encode Packet Decode RAM controller Rx Buffer CRC Gen/Check Tx Buffer UTMI UTM Synchronization DMA controller AHB slave AHB master RAM 7.4.2 Register Definitions USB COMMON REGISTER USB+0000h Function Address Register FADDR Bit Name Type Reset 7 6 5 R 0 4 3 2 FUNCTION ADDRESS R/W 0 1 0 Function Address FAddr is an 8-bit register that should be written with the 7-bit address of the peripheral part of the transaction. When the USB2.0 controller is being used in Peripheral mode (DevCtl.bit2=0), this register should be written with the address received through a SET_ADDRESS command, which will then be used for decoding the function address in subsequent token packets. When the USB2.0 controller is being used in Host mode (DevCtl.bit2=1), this register should be set to the value sent in a SET_ADDRESS command during device enumeration as the address for the peripheral device. Peripheral Mode USB+0001h Bit 15 Power Management Register 14 13 12 11 10 9 8 321/599 POWER 7 6 5 4 3 2 1 0 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 ENAB ISO SUSP LE SOFT HS HS RESE RESU UPDA END SUSP CONN ENAB MODE T ME TE MODE ENDM R/W R/W R/W R R R/W R R/W 0 0 1 0 0 0 0 0 Name Type Reset Host Mode USB+0001h Bit 15 Power Management Register 14 13 12 11 10 9 8 POWER 7 6 Name Type Reset 5 4 3 2 1 0 ENAB SUSP LE HS HS RESE RESU END SUSP ENAB MODE T ME MODE ENDM R/W R R/W R/W set R/W 1 0 0 0 0 0 EnableSuspendM Set by the CPU to enable the SUSPENDM output SuspendMode In Host mode, this bit is set by the CPU to enter Suspend mode. In Peripheral mode, this bit is set on entry into Suspend mode. It is cleared when the CPU reads the interrupt register, or sets the Resume bit above. Resume Set by the CPU to generate Resume signaling when the function is in Suspend mode. The CPU should clear this bit after 10 ms (a maximum of 15 ms) to end Resume signaling. In Host mode, this bit is also automatically set when Resume signaling from the target is detected while the USB2.0 controller is suspended. Reset This bit is set when Reset signaling is present on the bus. Note: This bit is Read/Write from the CPU in Host Mode but Read-Only in Peripheral Mode. HSMode When set, this read-only bit indicates High-speed mode successfully negotiated during USB reset. In Peripheral Mode, becomes valid when USB reset completes (as indicated by USB reset interrupt). In Host Mode, becomes valid when Reset bit is cleared. Remains valid for the duration of the session. Note: Allowance is made for Tiny-J signaling in determining the transfer speed to select. HSEnab When set by the CPU, the USB2.0 controller will negotiate for High-speed mode when the device is reset by the hub. If not set, the device will only operate in Full-speed mode. SoftConn If Soft Connect/Disconnect feature is enabled, then the USB D+/D- lines is enabled when this bit is set by the CPU and tri-stated when this bit is cleared by the CPU. Note: Only valid in Peripheral Mode. ISOupdate When set by the CPU, the USB2.0 controller will wait for an SOF token from the time TxPktRdy is set before sending the packet. If an IN token is received before an SOF token, then a zero length data packet will be sent. Note: Only valid in Peripheral Mode. Also, this bit only affects endpoints performing Isochronous transfers. USB+0002h Bit 15 Tx Interrupt Status Register 14 13 12 11 10 9 INTRTX 8 Name 322/599 7 6 5 EP5 TX 4 EP4 TX 3 EP3 TX 2 EP2 TX 1 EP1 TX 0 EP0 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 Type Reset R 0 R 0 R 0 R 0 R 0 R 0 EP0 Endpoint0 interrupt event EP1_TX Tx Endpoint 1 interrupt event EP2_TX Tx Endpoint 2 interrupt event EP3_TX Tx Endpoint 3 interrupt event EP4_TX Tx Endpoint 4 interrupt event EP5_TX Tx Endpoint 5 interrupt event USB+0004h Bit 15 Rx Interrupt Status Register 14 13 12 11 10 9 8 INTRRX 7 6 5 4 3 EP3 RX R/W 0 2 EP2 RX R/W 0 7 6 5 EP5 TXE R/W 1 4 EP4 TXE R/W 1 3 EP3 TXE R/W 1 2 EP2 TXE R/W 1 Name Type Reset 1 EP1 RX R/W 0 0 INTRRX[15:0] Rx Interrupt Status register is “write 0 clear” EP1_RX Rx Endpoint 1 interrupt event EP2_RX Rx Endpoint 2 interrupt event EP3_RX Rx Endpoint 3 interrupt event USB+0006h Bit 15 Tx Interrupt Enable Register 14 13 12 11 10 9 8 INTRTXE Name Type Reset 1 EP1 TXE R/W 1 0 EP0 E R/W 1 EP0_E 0: Endpoint0 interrupt event disable 1: Endpoint0 interrupt event enable EP1_TXE 0:Tx Endpoint 1 interrupt event disable 1:Tx Endpoint 1 interrupt event enable EP2_TXE 0:Tx Endpoint 2 interrupt event disable 1:Tx Endpoint 2 interrupt event enable EP3_TXE 0:Tx Endpoint 3 interrupt event disable 1:Tx Endpoint 3 interrupt event enable EP4_TXE 0:Tx Endpoint 4 interrupt event disable 1:Tx Endpoint 4 interrupt event enable EP5_TXE 0:Tx Endpoint 5 interrupt event disable 1:Tx Endpoint 5 interrupt event enable USB+0008h Bit 15 Rx Interrupt Enable Register 14 13 12 11 10 9 8 Name Type Reset INTRRXE 7 6 5 4 3 EP3 RXE R/W 1 2 EP2 RXE R/W 1 1 EP1 RXE R/W 1 0 EP1_RXE 0:Rx Endpoint 1 interrupt event disable 1:Rx Endpoint 1 interrupt event enable EP2_RXE 0:rx Endpoint 2 interrupt event disable 1:Rx Endpoint 2 interrupt event enable EP3_RXE 0:Rx Endpoint 3 interrupt event disable 1:Rx Endpoint 3 interrupt event enable 323/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 USB+000Ah Bit 15 14 Common USB interrupts Register 13 12 11 10 9 8 Name Type Reset INTRUSB 7 6 5 4 3 2 1 0 RESE VBUS RESU SUSP SESS DISC CONN SOF T/BAB ERRO ME END REQ ON BLE R R R R R R R R R 0 0 0 0 0 0 0 0 Suspend Set when Suspend signaling is detected on the bus. Only valid in Peripheral mode. Resume Set when Resume signaling is detected on the bus while the USB2.0 controller is in Suspend mode. Reset Set in Peripheral mode when Reset signaling is detected on the bus. Babble Set in Host mode when babble is detected. Note: Only active after first SOF has been sent. SOF Set when a new frame starts. Conn Set when a device connection is detected. Only valid in Host mode. Valid at all transaction speeds. Discon Set in Host mode when a device disconnect is detected. Set in Peripheral mode when a session ends. Valid at all transaction speeds. SessReq Set when Session Request signaling has been detected. Only valid when USB2.0 controller is ‘A’ device. VBusError Set when VBus drops below the VBus Valid threshold during a session. Only valid when USB2.0 controller is ‘A’ device. USB+000Bh Bit 15 14 Common USB interrupts Enable Register 13 12 11 10 9 8 Name Type Reset 7 6 INTRUSBE 5 4 3 2 1 0 RESE SUSP VBUS SESS DISC CONN SOF_ T/BAB RESU END_ ERRO REQ_ BLE_ ME_E ON_E _E E E E R_E E R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 1 1 0 SuspendE Suspend interrupt enable. ResumeE Resume interrupt enable Reset/BabbleE Reset/Babble interrupt enable SOFE SOF interrupt enable ConnE Conn interrupt enable DisconE Discon interrupt enable SessReqE SessReq interrupt enable VBusErrorE VBusError interrupt enable USB+000Ch Bit Name Type Reset 15 14 Frame Number Register 13 0 R 0 12 11 10 9 FRAME 8 7 6 5 FRAME NUMBER R 0 4 3 2 1 0 FRAME Frame is a 11-bit read-only register that holds the last received frame number. 324/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 USB+000Eh Bit Name Type Reset 15 14 Endpoint Selecting Index Register 13 12 11 10 9 8 7 INDEX 6 5 4 3 2 1 0 SELECTED ENDPOINT R/W 0 INDEX Each Tx endpoint and each Rx endpoint have their own set of control/status registers located between 29900h – 299FFh. In addition one set of Tx control/status and one set of Rx control/status registers appear at 29810h – 2981Fh. Index is a 4-bit register that determines which endpoint control/status registers are accessed. Before accessing an endpoint’s control/status registers at 29810h – 2981Fh, the endpoint number should be written to the Index register to ensure that the correct control/status registers appear in the memory map. USB+000Fh Bit 15 14 Test Mode Enable Register 13 12 11 10 Name Type Reset 9 TESTMODE 8 7 6 5 4 3 2 1 0 TEST TEST FORC FIFO_ TEST TEST FORC FORC _SE0_ _PAC E_HO ACCE _K J E_FS E_HS NAK KET SS ST R/W SET R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Test_SE0_NAK (High-speed mode) The CPU sets this bit to enter the Test_SE0_NAK test mode. In this mode, the USB2.0 controller remains in High-speed mode but responds to any valid IN token with a NAK. Test_J (High-speed mode) The CPU sets this bit to enter the Test_J test mode. In this mode, the USB2.0 controller transmits a continuous J on the bus. Test_K (High-speed mode) The CPU sets this bit to enter the Test_K test mode. In this mode, the USB2.0 controller transmits a continuous K on the bus. Test_Packet (High-speed mode) The CPU sets this bit to enter the Test_Packet test mode. In this mode, the USB2.0 controller repetitively transmits on the bus a 53-byte test packet, the form of which is defined in the Universal Serial Bus Specification Revision 2.0, Section 7.1.20. Note: The test packet has a fixed format and must be loaded into the Endpoint 0 FIFO before the test mode is entered. Force_HS The CPU sets this bit either in conjunction with bit 7 above or to force the USB2.0 controller into High-speed mode when it receives a USB reset. Force_FS The CPU sets this bit either in conjunction with bit 7 above or to force the USB2.0 controller into Fullspeed mode when it receives a USB reset. FIFO_Access The CPU sets this bit to transfer the packet in the Endpoint 0 Tx FIFO to the Endpoint 0 Rx FIFO. It is cleared automatically. Force_Host The CPU sets this bit to instruct the core to enter Host mode when the Session bit is set, regardless of whether it is connected to any peripheral. The state of the CID input, HostDisconnect and LineState signals are ignored. The core will then remain in Host mode until the Session bit is cleared, even if a device is disconnected, and if the Force_Host bit remains set, will re-enter Host mode the next time the Session bit is set.While in this 325/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 mode, the status of the HOSTDISCON signal from the PHY may be read from bit 7 of the ACTLR0.DevCtl register. The operating speed is determined from the Force_HS and Force_FS bits as follows: Force_HS Force_FS Operating Speed 0 0 Low Speed 0 1 Full Speed 1 0 High Speed 1 1 Undefined USB INDEXED REGISTER EP0 INDEXED REGISTER Peripheral Mode USB+0100h Bit 15 EP0 Control Status Register 14 13 12 11 10 9 Name Type Reset CSR0 8 7 6 5 4 3 2 1 0 SERVI SERVI SEND SEND TXPK RXPK SETU DATA FLUS CESE CED STAL STAL TRDY TRDY PEND END HFIFO TUPE RXPK L L ND TRDY R/CLE SET SET SET SET R SET R/SET R AR 0 0 0 0 0 0 0 0 0 RxPktRdy This bit is set when a data packet has been received. An interrupt is generated when this bit is set. The CPU clears this bit by setting the ServicedRxPktRdy bit. TxPktRdy The CPU sets this bit after loading a data packet into the FIFO. It is cleared automatically when a data packet has been transmitted. An interrupt is also generated at this point (if enabled). SentStall This bit is set when a STALL handshake is transmitted. The CPU should clear this bit. DataEnd The CPU sets this bit: 1. When setting TxPktRdy for the last data packet. 2. When clearing RxPktRdy after unloading the last data packet. 3. When setting TxPktRdy for a zero length data packet. It is cleared automatically. SetupEnd This bit will be set when a control transaction ends before the DataEnd bit has been set. An interrupt will be generated and the FIFO flushed at this time. The bit is cleared by the CPU writing a 1 to the ServicedSetupEnd bit. SendStall The CPU writes a 1 to this bit to terminate the current transaction. The STALL handshake will be transmitted and then this bit will be cleared automatically. Note: The FIFO should be flushed before SendStall is set. ServiceRxPktRdy The CPU writes a 1 to this bit to clear the RxPktRdy bit. It is cleared automatically. 326/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 ServiceSetupEnd The CPU writes a 1 to this bit to clear the SetupEnd bit. It is cleared automatically. FlushFIFO The CPU writes a 1 to this bit to flush the next packet to be transmitted/read from the Endpoint 0 FIFO. It is cleared automatically. The FIFO pointer is reset and the TxPktRdy/RxPktRdy bit (below) is cleared. Note: FlushFIFO should only be used when TxPktRdy/RxPktRdy is set. At other times, it may cause data to be corrupted. Host Mode USB+0100h Bit 15 EP0 Control Status Register 14 13 12 11 Name DIS PING Type R/W Reset 0 10 9 CSR0 8 7 6 5 4 3 2 1 0 NAK STAT REQ ERRO SETU RXST TXPK RXPK FLUS TIME USPK PKT R PPKT ALL TRDY TRDY HFIFO T OUT R/CLE R/CLE R/CLE R/CLE R/CLE SET R/W R/W R/SET AR AR AR AR AR 0 0 0 0 0 0 0 0 0 RxPktRdy This bit is set when a data packet has been received. An interrupt is generated (if enabled) when this bit is set. The CPU should clear this bit when the packet has been read from the FIFO. TxPktRdy The CPU sets this bit after loading a data packet into the FIFO. It is cleared automatically when a data packet has been transmitted. An interrupt is also generated at this point (if enabled). RxStall This bit is set when a STALL handshake is received. The CPU should clear this bit. SetupPkt The CPU sets this bit, at the same time as the TxPktRdy bit is set, to send a SETUP token instead of an OUT token for the transaction. Note: Setting this bit also clears the DataToggle. Error This bit will be set when three attempts have been made to perform a transaction with no response from the peripheral. The CPU should clear this bit. An interrupt is generated when this bit is set. ReqPkt The CPU sets this bit to request an IN transaction. It is cleared when RxPktRdy is set. StatusPkt The CPU sets this bit at the same time as the TxPktRdy or ReqPkt bit is set, to perform a status stage transaction. Setting this bit ensures that the data toggle is set to 1 so that a DATA1 packet is used for the Status Stage transaction. NAKTimeout This bit will be set when Endpoint 0 is halted following the receipt of NAK responses for longer than the time set by the NAKLimit0 register. The CPU should clear this bit to allow the endpoint to continue. FlushFIFO The CPU writes a 1 to this bit to flush the next packet to be transmitted/read from the Endpoint 0 FIFO. The FIFO pointer is reset and the TxPktRdy/RxPktRdy bit (below) is cleared. Note: FlushFIFO should only be used when TxPktRdy/RxPktRdy is set. At other times, it may cause data to be corrupted. DisPing The CPU writes a 1 to this bit to instruct the core not to issue PING tokens in data and status phases of a high-speed Control transfer (for use with devices that do not respond to PING) USB+0108h Bit Name Type Reset 15 EP0 Received bytes Register 14 13 12 11 10 9 8 327/599 COUNT0 7 6 5 4 3 2 EP0 RX COUNT R 0 1 0 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 EP0 RX Count0 Count0 is a 7-bit read-only register that indicates the number of received data bytes in the Endpoint 0 FIFO. The value returned changes as the contents of the FIFO change and is only valid while RxPktRdy (IDXEPR0.CSR0.bit0) is set. Host Mode USB+010Bh Bit 15 14 NAK Limit Register 13 12 11 10 NAKLIMT0 9 8 7 6 5 4 3 Name Type Reset 2 NAK LIMIT0 R/W 0 1 0 NAKLimit0 NAKLimit0 is a 5-bit register that sets the number of frames/microframes (High-Speed transfers) after which Endpoint 0 should timeout on receiving a stream of NAK responses. (Equivalent settings for other endpoints can be made through their TxInterval and RxInterval registers.). The number of frames/microframes selected is 2(m-1) (where m is the value set in the register, valid values 2 – 16). If the host receives NAK responses from the target for more frames than the number represented by the Limit set in this register, the endpoint will be halted. Note: A value of 0 or 1 disables the NAK timeout function. USB+010Fh Bit 15 14 Core Configuration Register 13 12 11 10 9 CONFIGDATA 8 Name Type Reset UTMIDataWidth Indicates selected UTMI+ data width. 0 7 6 MP RXE MP TXE R R 8 bits; 1 5 4 3 2 1 0 UTMI DYNFI BIGE SOFT DATA HBRX HBTX FOSIZ NDIA CONE WIDT E E ING N H R R R R R R 16 bits. SoftConE When set to ‘1’ indicates Soft Connect/Disconnect option selected. DynFIFOSizeing When set to ‘1’ indicates Dynamic FIFO Sizing option selected. HBTxE When set to ‘1’ indicates High-bandwidth Tx ISO Endpoint Support selected. HBRxE When set to ‘1’ indicates High-bandwidth Rx ISO Endpoint Support selected BigEndian When set to ‘1’ indicates Big Endian ordering is selected. MPTxE When set to ‘1’, automatic splitting of bulk packets is selected. MPRxE When set to ‘1’, automatic amalgamation of bulk packets is selected. EP1 INDEXED REGISTER USB+0110h Bit Name Type Reset 15 TXMAP Register 14 13 M-1 R/W 0 12 11 TXMAP 10 9 8 7 6 5 4 3 2 MAXIMUM PAYLOAD TRANSACTION R/W 0 1 0 TxMaxP Maxmum payload size for indexed TX endpoint m-1 Packet multiplier m 328/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 TxMaxP Register The TxMaxP register defines the maximum amount of data that can be transferred through the selected Tx endpoint in a single operation. There is a TxMaxP register for each Tx endpoint (except Endpoint 0). Bits 10:0 define (in bytes) the maximum payload transmitted in a single transaction. The value set can be up to 1024 bytes but is subject to the constraints placed by the USB Specification on packet sizes for Bulk, Interrupt and Isochronous transfers in Fullspeed and High-speed operations. Where the option of High-bandwidth Isochronous/Interrupt endpoints or of packet splitting on Bulk endpoints has been taken when the core is configured, the register includes either 2 or 5 further bits that define a multiplier m which is equal to one more than the value recorded. In the case of Bulk endpoints with the packet splitting option enabled, the multiplier m can be up to 32 and defines the maximum number of ‘USB’ packets (i.e. packets for transmission over the USB) of the specified payload into which a single data packet placed in the FIFO should be split, prior to transfer. (If the packet splitting option is not enabled, bit15–13 is not implemented and bit12–11(if included) is ignored.) Note: The data packet is required to be an exact multiple of the payload specified by bits 10:0, which is itself required to be either 8, 16, 32, 64 or (in the case of High Speed transfers) 512 bytes. For Isochronous/Interrupt endpoints operating in High-Speed mode and with the High-bandwidth option enabled, m may only be either 2 or 3 (corresponding to bit 11 set or bit 12 set, respectively) and it specifies the maximum number of such transactions that can take place in a single microframe. If either bit 11 or bit 12 is non-zero, the USB2.0 controller will automatically split any data packet written to the FIFO into up to 2 or 3 ‘USB’ packets, each containing the specified payload (or less). The maximum payload for each transaction is 1024 bytes, so this allows up to 3072 bytes to be transmitted in each microframe. (For Isochronous/Interrupt transfers in Full-speed mod, bits 11 and 12 are ignored.) The value written to bits 10:0 (multiplied by m in the case of high-bandwidth Isochronous/Interrupt transfers) must match the value given in the wMaxPacketSize field of the Standard Endpoint Descriptor for the associated endpoint (see USB Specification Revision 2.0, Chapter 9). A mismatch could cause unexpected results. The total amount of data represented by the value written to this register (specified payload × m) must not exceed the FIFO size for the Tx endpoint, and should not exceed half the FIFO size if double-buffering is required. If this register is changed after packets have been sent from the endpoint, the Tx endpoint FIFO should be completely flushed (using the FlushFIFO bit in TxCSR) after writing the new value to this register. Peripheral Mode USB+0112h Bit 15 Tx CSR Register 14 13 12 11 TXCSR 10 9 AUTO FRCD DMAR SETE AUTO DMAR ATAT EQMO Name ISO MODE N_SP SET EQEN DE OG KT Type R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 8 7 6 5 4 3 2 1 0 FIFON CLRD SENT SEND TXPK FLUS UNDE INCO OTEM ATAT STAL STAL TRDY HFIFO RRUN MPTX PTY L L OG R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R 0 R/W 0 TxPktRdy The CPU sets this bit after loading a data packet into the FIFO. It is cleared automatically when a data packet has been transmitted. An interrupt is also generated at this point (if enabled). TxPktRdy is also 329/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 automatically cleared (but no interrupt is generated) prior to loading a second packet into a double-buffered FIFO. FIFONotEmpty The USB sets this bit when there is at least 1 packet in the TxFIFO. UnderRun The USB sets this bit if an IN token is received when the TxPktRdy bit not set. The CPU should clear this bit (write 0 clear). FlushFIFO The CPU writes a 1 to this bit to flush the latest packet from the endpoint TxFIFO. The FIFO pointer is reset, the TxPktRdy bit is cleared and an interrupt is generated. May be set simultaneously with TxPktRdy to abort the packet that is currently being loaded into the FIFO. Note: FlushFIFO should only be used when TxPktRdy is set. At other times, it may cause data to be corrupted. Also note that, if the FIFO is double-buffered, FlushFIFO may need to be set twice to completely clear the FIFO. SendStall The CPU writes a 1 to this bit to issue a STALL handshake to an IN token. The CPU clears this bit to terminate the stall condition. Note: This bit has no effect where the endpoint is being used for Isochronous transfer. SentStall This bit is set when a STALL handshake is transmitted. The FIFO is flushed and the TxPktRdy bit is cleared. The CPU should clear this bit. ClrDataTog The CPU writes a 1 to this bit to reset the endpoint data toggle to 0. IncompTx When the endpoint is being used for high-bandwidth Isochronous/Interrupt transfers, this bit is set to indicate where a large packet has been split into 2 or 3 packets for transmission but insufficient IN tokens have been received to send all the parts. Note: In anything other than a high-bandwidth transfer, this bit will always return 0. AutoSetEn_SPKT If the CPU sets this bit, TxPktRdy will be automatically set when the short packet is loaded into the TxFIFO completely. But, this function only works in Tx endpoint 1 and 2. Besides, Tx endpoint 1 has to use DMA channel 1 to move data and Tx endpoint 2 has to use DMA channel 2 to move data. DMAReqMode The CPU sets this bit to select DMA Request Mode 1 and clears it to select DMA Request Mode 0. Note: This bit must not be cleared either before or in the same cycle as the DMAReqEn bit is cleared. FrcDataTog The CPU sets this bit to force the endpoint data toggle to switch and the data packet to be cleared from the FIFO, regardless of whether an ACK was received. This can be used by Interrupt Tx endpoints that are used to communicate rate feedback for Isochronous endpoints. DMAReqEn The CPU sets this bit to enable the DMA request for the Tx endpoint. Mode The CPU sets this bit to enable the endpoint direction as Tx, and clears the bit to enable it as Rx. Note: This bit only has any effect where the same endpoint FIFO is used for both Tx and Rx transactions. ISO The CPU sets this bit to enable the Tx endpoint for Isochronous transfers, and clears it to enable the Tx endpoint for Bulk or Interrupt transfers. Note: This bit only has any effect in Peripheral mode. In Host mode, it always returns zero. AutoSet If the CPU sets this bit, TxPktRdy will be automatically set when data of the maximum packet size (value in TxMaxP) is loaded into the TxFIFO. If a packet of less than the maximum packet size is loaded, then TxPktRdy will have to be set manually if AutoSetEn_SPKT is not enabled. 330/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 Host Mode USB+0112h Tx CSR Register 14 13 Bit 15 Name AUTO SET Type R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 MODE 12 11 TXCSR 10 FRCD DMAR DMAR ATAT EQMO EQEN OG DE 9 8 7 NAK TIME OUT/I NCOM PTX R/CLE AR 0 6 5 4 CLRD RXST ATAT ALL OG SET 0 R/CLE AR 0 3 2 1 0 FIFON TXPK FLUS ERRO OTEM TRDY HFIFO R PTY SET 0 R/CLE R/CLE R/SET AR AR 0 0 0 TxPktRdy The CPU sets this bit after loading a data packet into the FIFO. It is cleared automatically when a data packet has been transmitted. An interrupt is also generated at this point (if enabled). TxPktRdy is also automatically cleared prior to loading a second packet into a double-buffered FIFO. FIFONotEmpty The USB sets this bit when there is at least 1 packet in the Tx FIFO. Error The USB sets this bit when 3 attempts have been made to send a packet and no handshake packet has been received. When the bit is set, an interrupt is generated, TxPktRdy is cleared and the FIFO is completely flushed. The CPU should clear this bit. Valid only when the endpoint is operating in Bulk or Interrupt mode. FlushFIFO The CPU writes a 1 to this bit to flush the latest packet from the endpoint Tx FIFO. The FIFO pointer is reset, the TxPktRdy bit (below) is cleared and an interrupt is generated. May be set simultaneously with TxPktRdy to abort the packet that is currently being loaded into the FIFO. Note: FlushFIFO should only be used when TxPktRdy is set. At other times, it may cause data to be corrupted. Also note that, if the FIFO is double-buffered, FlushFIFO may need to be set twice to completely clear the FIFO. RxStall This bit is set when a STALL handshake is received. When this bit is set, any DMA request that is in progress is stopped, the FIFO is completely flushed and the TxPktRdy bit is cleared (see below). The CPU should clear this bit. ClrDataTog The CPU writes a 1 to this bit to reset the endpoint data toggle to 0. NAKTimeout Bulk endpoints only: This bit will be set when the Tx endpoint is halted following the receipt of NAK responses for longer than the time set as the NAK Limit by the TxInterval register. The CPU should clear this bit to allow the endpoint to continue. IncompTx High-bandwidth Interrupt endpoints only: This bit will be set if no response is received from the device to which the packet is being sent. DMAReqMode The CPU sets this bit to select DMA Request Mode 1 and clears it to select DMA Request Mode 0. Note: This bit must not be cleared either before or in the same cycle as the above DMAReqEnab bit is cleared. FrcDataTog The CPU sets this bit to force the endpoint data toggle to switch and the data packet to be cleared from the FIFO, regardless of whether an ACK was received. This can be used by Interrupt Tx endpoints that are used to communicate rate feedback for Isochronous endpoints. DMAReqEnab The CPU sets this bit to enable the DMA request for the Tx endpoint. 331/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 Mode The CPU sets this bit to enable the endpoint direction as Tx, and clears it to enable the endpoint direction as Rx. Note: This bit only has any effect where the same endpoint FIFO is used for both Tx and Rx transactions. AutoSet If the CPU sets this bit, TxPktRdy will be automatically set when a packet of the maximum packet size (TxMaxP) is loaded into the Tx FIFO. If a packet of less than the maximum packet size is loaded, then TxPktRdy will have to be set manually. Note: Should not be set for either high-bandwidth Isochronous endpoints or high-bandwidth Interrupt endpoints. USB+0114h Bit Name Type Reset 15 RXMAP Register 14 13 M-1 R/W 0 12 11 RXMAP 10 9 8 7 6 5 4 3 2 MAXIMUM PAYLOA TRANSACTION R/W 0 1 0 RxMaxP Maxmum payload size for indexed RX endpoint m-1 Packet multiplier m RxMaxP Register The RxMaxP register defines the maximum amount of data that can be transferred through the selected Rx endpoint in a single operation. There is a RxMaxP register for each Rx endpoint (except Endpoint 0). Bits 10:0 define (in bytes) the maximum payload transmitted in a single transaction. The value set can be up to 1024 bytes but is subject to the constraints placed by the USB Specification on packet sizes for Bulk, Interrupt and Isochronous transfers in Full-speed and High-speed operations. Where the option of High-bandwidth Isochronous/Interrupt endpoints or of combining Bulk packets has been taken when the core is configured, the register includes either 2 or 5 further bits that define a multiplier m which is equal to one more than the value recorded. For Bulk endpoints with the packet combining option enabled, the multiplier m can be up to 32 and defines the number of USB packets of the specified payload which are to be combined into a single data packet within the FIFO. (If the packet splitting option is not enabled, bit15–bit13 is not implemented and bit12–bit11 (if included) is ignored.) For Isochronous/Interrupt endpoints operating in High-Speed mode and with the High-bandwidth option enabled, m may only be either 2 or 3 (corresponding to bit 11 set or bit 12 set, respectively) and it specifies the maximum number of such transactions that can take place in a single microframe. If either bit 11 or bit 12 is non-zero, the USB2.0 controller will automatically combine the separate USB packets received in any microframe into a single packet within the Rx FIFO. The maximum payload for each transaction is 1024 bytes, so this allows up to 3072 bytes to be received in each microframe. (For Isochronous/Interrupt transfers in Full-speed mode or if High-bandwidth is not enabled, bits 11 and 12 are ignored.) The value written to bits 10:0 (multiplied by m in the case of high-bandwidth Isochronous/Interrupt transfers) must match the value given in the wMaxPacketSize field of the Standard Endpoint Descriptor for the associated endpoint (see USB Specification Revision 2.0, Chapter 9). A mismatch could cause unexpected results. 332/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 The total amount of data represented by the value written to this register (specified payload × m) must not exceed the FIFO size for the OUT endpoint, and should not exceed half the FIFO size if double-buffering is required. Peripheral Mode USB+0116h Bit 15 Rx CSR Register 14 13 12 11 10 AUTO DISNY DMAR AUTO CLRE DMAR ET/PI EQMO Name CLEA ISO N_SP EQEN DERR DE R KT Type R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 RXCSR 9 8 7 6 5 4 3 2 1 0 INCO CLRD SENT SEND MPRX INCO FLUS DATA OVER FIFOF RXPK ATAT STAL STAL HFIFO ERR RUN ULL TRDY INTRE MPRX L L OG N R/W R/W R/W R/W R/W R/W R/W R/W R R/W 0 0 0 0 0 0 0 0 0 0 RxPktRdy This bit is set when a data packet has been received (to RxFIFO). The CPU should clear this bit when the packet has been unloaded from the RxFIFO. An interrupt is generated when the bit is set. FIFOFull This bit is set when no more packets can be loaded into the RxFIFO. OverRun This bit is set if an OUT packet cannot be loaded into the RxFIFO. The CPU should clear this bit (write 0 clear). Note: This bit is only valid when the endpoint is operating in ISO mode. In Bulk Mode, it always returns zero. The new incoming packet won’t be written to RxFIFO. An interrupt is generated when the bit is set and OverRunIntrEn is set. DataError This bit is set when RxPktRdy is set if the data packet has a CRC or bit-stuff error. The CPU should write 0 to clear this bit. Note: This bit is only valid when the endpoint is operating in ISO mode. In Bulk Mode, it always returns zero. An interrupt is generated when the bit is set and DataErrIntrEn is set. FlushFIFO The CPU writes a 1 to this bit to flush the next packet to be read from the endpoint RxFIFO. The RxFIFO pointer is reset and the RxPktRdy bit is cleared. Note: FlushFIFO should only be used when RxPktRdy is set. At other times, it may cause data to be corrupted. Also note that, if the RxFIFO is double buffered, FlushFIFO may need to be set twice to completely clear the RxFIFO. SendStall The CPU writes a 1 to this bit to issue a STALL handshake. The CPU clears this bit to terminate the stall condition. Note: This bit has no effect where the endpoint is being used for ISO transfers. SentStall This bit is set when a STALL handshake is transmitted. The CPU should clear this bit. An interrupt is generated when the bit is set. ClrDataTog The CPU writes a 1 to this bit to reset the endpoint data toggle to 0. IncompRx This bit is set in a high-bandwidth Isochronous/Interrupt transfer if the packet in the RxFIFO is incomplete because parts of the data were not received. It is cleared when RxPktRdy is cleared or write 0 to clear. Note: In anything other than a high-bandwidth transfer, this bit will always return 0. An interrupt is generated when the bit is set and IncompRxIntrEn is set. IncompRxIntrEn IncompRx and PidErr interrupt enable. AutoClrEn_SPKT The CPU write a 1 to this bit to enable short packets’ RxPktRdy to be automatically cleared. Whe this bit is turned on, AutoClear must also be turned on. If ISO and AutoClrEn_SPKT are both set, when 333/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 short packets are unloaded, RxPktRdy will be cleared automatically. But, these short packets must have no IncompRx, PidErr, DataErr or OverRun status. DMAReqMode The CPU sets this bit to select DMA Request Mode 1 and clears it to select DMA Request Mode 0. DMA Request Mode 1: Rx endpoint interrupt is generated only when DMA Request Mode 1 and received a short packet. RxDMAReq is generated when receiving a Max-Packet-size packet. DMA Request Mode 0: No Rx endpoint interrupt. RxDMAReq is generated when RxPktRdy is set. DisNyet(bulk/interrupt transactions) The CPU sets this bit to disable the sending of NYET handshakes. When set, all successfully received Rx packets are ACK’d including at the point at which the RxFIFO becomes full. Note: This bit only has any effect in High-speed mode, in which mode it should be set for all interrupt endpoint. PidErr(ISO transactions) This bit is set when there is a PID error in the received packet. It is cleared when RxPktRdy is cleared or write 0 to clear. An interrupt is generated when the bit is set and IncompRxIntrEn is set. DMAReqEn The CPU sets this bit to enable the DMA request for the Rx endpoint. ISO The CPU sets this bit to enable the Rx endpoint for Isochronous transfers, and clears it to enable the Rx endpoint for Bulk/Interrupt transfers. AutoClear If the CPU sets this bit then the RxPktRdy bit will be automatically cleared when a packet of RxMaxP bytes has been unloaded from the RxFIFO. When packets of less than the maximum packet size are unloaded, RxPktRdy will have to be cleared manually if AutoClrEn_SPKT is not enabled. Host Mode USB+0116h Bit 15 Rx CSR Register 14 13 12 11 RXCSR 10 9 0 0 DMAR DMAR AUTO PIDER AUTO EQMO EQEN Name CLEA ROR REQ DE AB R Type R/W R/W R/W R R/W Reset 0 0 0 0 0 8 7 6 5 4 3 2 1 0 DATA CLRD ERR/ ERRO FIFOF RXPK RXST REQP FLUS INCO ATAT NAKTI R ULL TRDY ALL KT HFIFO MPRX MREO OG UT R/CLE R/CLE R/CLE R/CLE R/CLE R/W R/W SET R AR AR AR AR AR 0 0 0 0 0 0 0 0 0 RxPktRdy This bit is set when a data packet has been received. The CPU should clear this bit when the packet has been unloaded from the Rx FIFO. An interrupt is generated when the bit is set. FIFOFull This bit is set when no more packets can be loaded into the Rx FIFO. Error The USB sets this bit when 3 attempts have been made to receive a packet and no data packet has been received. The CPU should clear this bit. An interrupt is generated when the bit is set. Note: This bit is only valid when the Rx endpoint is operating in Bulk or Interrupt mode. In ISO mode, it always returns zero. NAKTimeout In Bulk mode, this bit will be set when the Rx endpoint is halted following the receipt of NAK responses for longer than the time set as the NAK Limit by the RxInterval register. DataError When operating in ISO mode, this bit is set when RxPktRdy is set if the data packet has a CRC or bit-stuff error and cleared when RxPktRdy is cleared. 334/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 FlushFIFO The CPU writes a 1 to this bit to flush the next packet to be read from the endpoint Rx FIFO. The FIFO pointer is reset and the RxPktRdy bit (below) is cleared. Note: FlushFIFO should only be used when RxPktRdy is set. At other times, it may cause data to be corrupted. Also note that, if the FIFO is double-buffered, FlushFIFO may need to be set twice to completely clear the FIFO. ReqPkt The CPU writes a 1 to this bit to request an IN transaction. It is cleared when RxPktRdy is set. RxStall When a STALL handshake is received, this bit is set and an interrupt is generated. The CPU should clear this bit. ClrDataTog The CPU writes a 1 to this bit to reset the endpoint data toggle to 0. IncompRx This bit will be set in a high-bandwidth Isochronous/Interrupt transfer if the packet received is incomplete. It will be cleared when RxPktRdy is cleared. Note: If USB protocols are followed correctly, this bit should never be set. The bit becoming set indicates a failure of the associated Peripheral device to behave correctly. (In anything other than a high-bandwidth transfer, this bit will always return 0.) DMAReqMode The CPU sets this bit to select DMA Request Mode 1 and clears it to select DMA Request Mode 0. Note: This bit should not be cleared in the same cycle as RxPktRdy is cleared PIDError ISO Transactions Only: The core sets this bit to indicate a PID error in the received packet. Bulk/Interrupt Transactions: The setting of this bit is ignored. DMAReqEnab The CPU sets this bit to enable the DMA request for the Rx endpoint. AutoReq If the CPU sets this bit, the ReqPkt bit will be automatically set when the RxPktRdy bit is cleared. Note: This bit is automatically cleared when a short packet is received. AutoClr f the CPU sets this bit then the RxPktRdy bit will be automatically cleared when a packet of RxMaxP bytes has been unloaded from the Rx FIFO. When packets of less than the maximum packet size are unloaded, RxPktRdy will have to be cleared manually. Note: Should not be set for highbandwidth Isochronous endpoints. USB+0118h Bit Name Type Reset 15 Rx Count Register 14 13 12 11 10 RXCOUNT 9 8 7 6 RXCOUNT R 0 5 4 3 2 1 0 RxCount It is a 14-bit read-only register that holds the number of received data bytes in the packet in the RxFIFO. Note: The value returned changes as the FIFO is unloaded and is only valid while RxPktRdy(RxCSR.D0) is set. Host Mode USB+011Ah Bit 15 14 TxType Register 13 12 11 TXTYPE 10 9 8 Name Type Reset 7 6 5 4 3 2 1 0 TX_PROTOC TX_TARGET EP NUMBER OL R/W R/W 0 0 Target EndpointNumber (Host Mode Only) The CPU should set this value to the endpoint number contained in the Tx endpoint descriptor returned to the USB2.0 Controller during device enumeration. 335/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 Protocol (Host Mode Only) The CPU should set this to select the required protocol for the Tx endpoint: 00 : Illegal 01 : Isochronous 10 : Bulk 11 : Interrupt USB+011Bh Bit Name Type Reset 15 14 TxInterval Register 13 12 11 10 TXINTERVAL 9 8 7 6 5 4 3 2 1 TX POLLING INTERVAL/NAK LIMIT M R/W 0 0 TxInterval Register TxInterval is an 8-bit register that, for Interrupt and Isochronous transfers, defines the polling interval for the currently-selected Tx endpoint. For Bulk endpoints, this register sets the number of frames/microframes after which the endpoint should timeout on receiving a stream of NAK responses. There is a TxInterval register for each configured Tx endpoint (except Endpoint 0). Tx Polling Interval / NAK Limit (m), (Host Mode Only) In each case the value that is set defines a number of frames/microframes (High Speed transfers), as follows: Transfer Type Speed Valid value s (m) 1– 255 Interrupt Low Speed or Full Speed High Speed 1 – 16 Polling interval is 2 microframes Isochronous Full Speed or High Speed 1 – 16 Polling interval is 2(m-1) frames/microframes Bulk Full Speed or High Speed 2 – 16 NAK Limit is 2(m-1) frames/microframes. Note: A value of 0 or 1 disables the NAK timeout function. USB+011Ch Bit 15 14 Interpretation Polling interval frames. 12 m (m-1) RxType Register 13 is 11 RXTYPE 10 9 8 Name 336/599 7 6 5 4 3 2 1 0 RX_PROTOC RX_TARGET EP NUMBER OL MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 Type Reset R/W 0 R/W 0 Target EndpointNumber (Host Mode Only) The CPU should set this value to the endpoint number contained in the Tx endpoint descriptor returned to the USB2.0 Controller during device enumeration. Protocol (Host Mode Only) The CPU should set this to select the required protocol for the Tx endpoint: 00 : Illegal 01 : Isochronous 10 : Bulk 11 : Interrupt USB+011Dh Bit Name Type Reset 15 14 RxInterval Register 13 12 11 10 RXINTERVAL 9 8 7 6 5 4 3 2 1 RX POLLING INTERVAL/NAK LIMIT M R/W 0 0 RxInterval Register RxInterval is an 8-bit register that, for Interrupt and Isochronous transfers, defines the polling interval for the currently-selected Rx endpoint. For Bulk endpoints, this register sets the number of frames/microframes after which the endpoint should timeout on receiving a stream of NAK responses. There is a RxInterval register for each configured Rx endpoint (except Endpoint 0). Rx Polling Interval / NAK Limit (m), (Host Mode Only) In each case the value that is set defines a number of frames/microframes (High Speed transfers), as follows: Speed Valid values (m) Low Speed or Full Speed 1– 255 High Speed 1 – 16 Polling interval microframes Isochronous Full Speed or High Speed 1 – 16 Polling interval is frames/microframes Bulk Full Speed or High Speed 2 – 16 NAK Limit is 2 frames/microframes. Note: A value of 0 or 1 disables the NAK timeout function. Transfer Type Interrupt Interpretation Polling interval is m frames. is 2(m-1) 2 (m-1) (m-1) Peripheral Mode USB+011Fh Bit 15 Configured FIFO Size Register 14 13 12 11 10 9 8 337/599 FIFOSIZE 7 6 5 4 3 2 1 0 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 Name Type Reset RXFIFOSIZE R TXFIFOSIZE R TxFIFOSize Indicate the TxFIFO size of 2n bytes, (ex: value 10 means 210 = 1024 bytes.) RxFIFOSize Indicate the RxFIFO size of 2n bytes, (ex: value 10 means 210 = 1024 bytes.) USB+0120h ~ USB+012Fh stands for Endpoint 2 Registers and their behaviors are the same as Endpoint 1. USB+0130h ~ USB+013Fh stands for Endpoint 3 Registers and their behaviors are the same as Endpoint 1. USB+0140h ~ USB+014Fh stands for Endpoint 4 Registers and their behaviors are the same as Endpoint 1. USB+0150h ~ USB+015Fh stands for Endpoint 5 Registers and their behaviors are the same as Endpoint 1. USB ENDPOINT FIFOS REGISTER USB+0020h~ USB+005F Bit Name Type Reset Bit Name Type Reset USB Endpoint FIFO Register 31 30 29 28 27 26 15 14 13 12 11 10 FIFOX 25 24 23 22 FIFO_DATA[31:16] R/W 0 9 8 7 6 FIFODATA[15:0] R/W 0 21 20 19 18 17 16 5 4 3 2 1 0 FIFOData 32-bits FIFO data access window The Endpoint FIFO Registers provides 5 addresses for CPU access to the FIFOs for each endpoint. Writing to these addresses loads data into the TxFIFO for the corresponding endpoint. Reading from these addresses unloads data from the RxFIFO for the corresponding endpoint. ote: (i) Transfers to and from FIFOs may be 8-bit, 16-bit or 32-bit as required, and any combination of access is allowed provided the data accessed is contiguous. However, all the transfers associated with one packet must be of the same width so that the data is consistently byte-, word- or double-word-aligned. The last transfer may however contain fewer bytes than the previous transfers in order to complete an odd-byte or odd-word transfer. (ii) Depending on the size of the FIFO and the expected maximum packet size, the FIFOs support either single-packet or double-packet buffering. However, burst writing of multiple packets is not supported as flags need to be set after each packet is written. (iii) Following a STALL response or a Tx Strike Out error on Endpoint 0 – 4, the associated FIFO is completely flushed USB ADDITIONAL CONTROL AND CONFIGURATION REGISTER USB+0060h Bit 15 OTG device control Register 14 13 12 11 10 9 8 338/599 DEVCTL 7 6 5 4 3 2 1 0 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 B-DE VICE R/W 0 Name Type Reset FS DEV R/W 0 LS DEV R/W 0 VBUS R/W 0 HOST HOST SESSI MODE REQ ON R/W R/W R/W 0 0 0 Session When operating as an ‘A’ device, this bit is set or cleared by the CPU to start or end a session. When operating as a ‘B’ device, this bit is set/cleared by the USB2.0 controller when a session starts/ends. It is also set by the CPU to initiate the Session Request Protocol. When the USB2.0 controller is in Suspend mode, the bit may be cleared by the CPU to perform a software disconnect. Note: Clearing this bit when the core is not suspended will result in undefined behavior. HostReq When set, the USB2.0 controller will initiate the Host Negotiation when Suspend mode is entered. It is cleared when Host Negotiation is completed. (‘B’ device only) HostMode This Read-only bit is set when the USB2.0 controller is acting as a Host. VBus These Read-only bits encode the current VBus level as follows: Bit4 Bit3 Meaning 0 0 Below SessionEnd 0 1 Above SessionEnd, below AValid 1 0 Above AValid, below VBusValid 1 1 Above VBusValid LSDev This Read-only bit is set when a low-speed device has been detected being connected to the port. Only valid in Host mode. FSDev This Read-only bit is set when a full-speed or high-speed device has been detected being connected to the port. (High-speed devices are distinguished from full-speed by checking for high-speed chirps when the device is reset.) Only valid in Host mode. B-Device This Read-only bit indicates whether the USB2.0 controller is operating as the ‘A’ device or the ‘B’ device. 0 ⇒ ‘A’ device; 1 ⇒ ‘B’ device. Only valid while a session is in progress. Note: If the core is in Force_Host mode (i.e. a session has been started with Testmode Register, 2980Ch.bit24 = 1), this bit will indicate the state of the HOSTDISCON input signal from the PHY. USB+0061h Power Up Counter Register Bit Name Type Reset PWRUPCNT 7 6 5 4 3 2 1 PWRUPCNT R/W 4’hf 0 PWRUPCNT[3:0] Power Up Counter Limit. Power Up Counter is used to count the K state duration during suspend and when it is timeout, the resume interrupt will be issued. The register should be configured according to AHB clock speed. 339/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 USB+0062h Bit 15 Tx FIFO Size Register 14 13 12 11 10 9 TXFIFOSZ 8 7 6 5 Name Type Reset 4 TX DPB R/W 0 3 2 1 0 TXSZ R/W 0 TXDPB Defines whether double-packet buffering supported for TxFIFO. When ‘1’, double-packet buffering is supported. When ‘0’, only single-packet buffering is supported. TXSZ Maximum packet size to be allowed for (before any splitting within the FIFO of Bulk/High-Bandwidth packets prior to transmission). If TxDPB = 0, the FIFO will also be this size; if TxDPB = 1, the FIFO will be twice this size TxSZ[3:0] Packet Size (Bytes) 0 0 0 0 8 0 0 0 1 16 0 0 1 0 32 0 0 1 1 64 0 1 0 0 128 0 1 0 1 256 0 1 1 0 512 0 1 1 1 1024 1 0 0 0 2048 (Single-packet buffering only) 1 0 0 1 4096 (Single-packet buffering only) 1 1 1 1 3072 (Single-packet buffering only) USB+0063h Bit 15 Rx FIFO Size Register 14 13 12 11 10 9 RXFIFOSZ 8 7 Name Type Reset 6 5 4 RX DPB R/W 0 3 2 1 0 RXSZ R/W 0 RXDPB Defines whether double-packet buffering supported for TxFIFO. When ‘1’, double-packet buffering is supported. When ‘0’, only single-packet buffering is supported. RXSZ Maximum packet size to be allowed for (before any splitting within the FIFO of Bulk/High-Bandwidth packets prior to transmission). If TxDPB = 0, the FIFO will also be this size; if TxDPB = 1, the FIFO will be twice this size 340/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 TxSZ[3:0] Packet Size (Bytes) 0 0 0 0 8 0 0 0 1 16 0 0 1 0 32 0 0 1 1 64 0 1 0 0 128 0 1 0 1 256 0 1 1 0 512 0 1 1 1 1024 1 0 0 0 2048 (Single-packet buffering only) 1 0 0 1 4096 (Single-packet buffering only) 1 1 1 1 3072 (Single-packet buffering only) USB+0064h Bit Name Type Reset 15 Tx FIFO Address Register 14 13 12 11 10 9 TXFIFOADD 8 7 6 5 TXFIFOADD R/W 0 4 3 2 1 0 TxFIFOadd TxFIFOadd is a 13-bit register which controls the start address of the selected Rx endpoint FIFO. TxFIFOadd[12:0] Start Address 0 0 0 0 0000 0 0 0 1 0008 0 0 0 2 0010 0 0 0 3 0018 … 1 F USB+0066h Bit 15 DATA ERRI Name NTRE N Type R/W Reset 0 14 OVER RUNI NTRE N R/W 0 … F F FFF8 Rx FIFO Address Register 13 12 11 10 9 RXFIFOADD 8 7 6 5 4 3 2 1 0 RXFIFOADD R/W 0 RxFIFOadd RxFIFOadd is a 13-bit register which controls the start address of the selected Rx endpoint FIFO. 341/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 RxFIFOadd[12:0] Start Address 0 0 0 0 0000 0 0 0 1 0008 0 0 0 2 0010 0 0 0 3 0018 … 1 F … F F FFF8 OVERRUNINTREN OverRun interrupt enable. The OverRun status bit is in RxCSR[2] and it should be write 0 to clear. DATAERRINTREN DataErr interrupt enable. The DataErr status bit is in RxCSR[3] and it should be write 0 to clear. USB+006Ch Bit Name Type Reset 15 RC R 0 14 Register 13 12 XX R 0 HWVERS 11 10 9 8 7 6 5 4 3 2 1 0 YY R 0 RC Set to ‘1’ if RTL used from a Release Candidate rather than from a full release of the core. XX Major Version Number (Range 0 – 31). YYY Minor Version Number (Range 0 – 999). HWVers register is a 16-bit read-only register that returns information about the version of the RTL from which the core hardware was generated, in particular the RTL version number (vxx.yyy). USB+0070h Bit 15 Software Reset Register 14 13 12 11 10 Name OPSTATE Type Reset RO 0 9 SWRST 8 7 6 5 4 3 2 1 REDU UNDO FRC_ SWRS CEDL _SRP VBUS T Y FIX VALID R/W R/W R/W R/W 0 0 0 0 0 DISU SBRE SET R/W 0 DisUSBReset The CPU sets this bit to Disable USBReset function. And, then the CPU can reset the hardware by SwRst. USBReset will be asserted when doing High Speed Detection Handshake. (This bit will only be reset when hardware reset.) SWRst The CPU sets this bit to reset the endpoint and RAM interface hardware. FRC_VbusValid The CPU sets this bit to force VBusVal = 1, VBusSess = 1 and VBusLo = 0. Undo_SRPFix The CPU sets this bit to recover to the original circuit of USB2.0 IP about SRP. ReduceDly The CPU can set this bit to reduce inter-pkt delay. OpState This register indicates the USB controller state information. 342/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 USB+0078h Bit Name Type Reset 15 Info. about number of Tx and Rx Register 14 13 12 11 10 9 8 7 EPINFO 6 5 RXENDPOINTS R 0 4 3 2 1 TXENDPOINTS R 0 0 TxEndPoints The number of Tx endpoints implemented in the design. RxEndPoints The number of Rx endpoints implemented in the design. This 8-bit read-only register allows read-back of the number of Tx and Rx endpoints included in the design. Info. about the width of RAM and the number of DMA channel Register USB+0079h Bit Name Type Reset RamBits 15 14 13 12 11 10 9 8 7 6 5 DMACHANS R 0 4 RAMINFO 3 2 1 RAMBITS R 0 0 The width of the RAM address bus – 1. DMA Channels The number of DMA channels implemented in the design. This 8-bit read-only register provides information about the width of the RAM and the number of DMA channels. USB+007Ah Bit Name Type Reset 15 Info. about delay to be applied 14 13 12 11 10 9 8 Register 7 LINKINFO 6 5 WTCON R/W 4 3 2 1 0 WTID R/W 8’h5C Wait ID Filter Sets the delay to be applied from IDPULLUP being asserted to IDDIG being considered valid in units of 4.369ms. (The default setting corresponds to 52.43ms.) Wait Connect Filter Sets the wait to be applied to allow for the user’s connect/disconnect filter in units of 533.3ns. (The default setting corresponds to 2.667µs.) This 8-bit register allows some delays to be specified. USB+007Bh Bit Name Type Reset 15 14 VBus Pulsing Charge Register 13 12 11 10 9 8 VPLEN 7 6 5 4 3 VPLEN R/W 8’h3C 2 1 0 VPLen Sets the duration of the VBus pulsing charge in units of 136.5 us. (The default setting corresponds to 8.19ms) This 8-bit register sets the duration of the VBus pulsing charge. 343/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 USB+007Ch Bit Name Type Reset 15 14 Time buffer available on HS transactions Register 13 12 11 10 9 8 7 6 5 HS_EOF1 4 3 HS_EOF1 R/W 8’h80 2 1 0 High-Speed End-Of-Frame 1 Sets for High-speed transactions the time before EOF to stop beginning new transactions, in units of 133.3ns. (The default setting corresponds to 17.07µs.) USB+007Dh Bit Name Type Reset 15 14 Time buffer available on FS transactions Register 13 12 11 10 9 8 7 6 5 FS_EOF1 4 3 FS_EOF1 R/W 8’h77 2 1 0 Full-Speed End-Of-Frame 1 Sets for Full-speed transactions the time before EOF to stop beginning new transactions, in units of 533.3ns. (The default setting corresponds to 63.46µs.) USB+007Eh Bit Name Type Reset 15 14 Time buffer available on LS transactions Register 13 12 11 10 9 8 7 6 5 LS_EOF1 4 3 LS_EOF1 R/W 8’h72 2 1 0 Low-Speed End-Of-Frame 1 Sets for Low-speed transactions the time before EOF to stop beginning new transactions, in units of 1.067µs. (The default setting corresponds to 121.6µs.). USB+007Fh RESET Information Register Bit Name Type Reset RSTINFO 7 6 5 WTFSSE0 R/W 0 4 3 2 1 WTCHRP R/W 0 0 WTChrp Sets the delay to be applied from detecting Reset to sending chirp K (for Device only). The duration = 272.8 x WTChrp + 0.1 usec. (This register will only be reset when hardware reset.) WTFSSE0 The field signifies the SE0 signal duration before issue the reset signal(for Device only). The duration = 272.8 x WTFSSE0 + 2.5 usec. (This register will only be reset when hardware reset.) USB RQPKTCOUNT REGISTER USB+0300h Bit Name Type Reset 15 EP1 RxPktCount Register 14 13 12 11 10 9 8 7 6 EP1RXPKTCOUNT R/W 0 EP1RXPKTCOUNT 5 4 3 2 1 0 EP1RqPktCount (Host Mode Only) Sets the number of packets of Rx Endpoint 1 size MaxP that are to be transferred in a block transfer. Only used in Host mode when AutoReq is set. Has no effect in Peripheral mode or when AutoReq is not set. 344/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 USB+0302h Bit Name Type Reset 15 EP2 RxPktCount Register 14 13 12 11 10 9 8 7 6 EP1RXPKTCOUNT R/W 0 EP2RXPKTCOUNT 5 4 3 2 1 0 EP2RqPktCount (Host Mode Only) Sets the number of packets of Rx Endpoint 1 size MaxP that are to be transferred in a block transfer. Only used in Host mode when AutoReq is set. Has no effect in Peripheral mode or when AutoReq is not set. USB+0304h Bit Name Type Reset 15 EP3 RxPktCount Register 14 13 12 11 10 9 8 7 6 EP1RXPKTCOUNT R/W 0 EP3RXPKTCOUNT 5 4 3 2 1 0 EP3RqPktCount (Host Mode Only) Sets the number of packets of Rx Endpoint 1 size MaxP that are to be transferred in a block transfer. Only used in Host mode when AutoReq is set. Has no effect in Peripheral mode or when AutoReq is not set. RqPktCount (Host Mode Only) For each Rx Endpoint 1 – 3, the USB2.0 controller provides a 16-bit RqPktCount register. This read/write register is used in Host mode to specify the number of packets that are to be transferred in a block transfer of one or more Bulk packets of length MaxP to Rx Endpoint n. The core uses the value recorded in this register to determine the number of requests to issue where the AutoReq option (included in the RxCSR register) has been set. Note: Multiple packets combined into a single bulk packet within the FIFO count as one packet. USB DMA CONTROL REGISTER USB+0200h Bit DMA Interrupt Status Register 31 30 29 28 27 26 25 24 15 14 13 12 11 10 9 8 Name Type Reset Bit Name Type Reset DMA_INTR 23 22 21 20 19 18 17 16 PPB_ PPA_ PPB_ PPA_ PPB_ PPA_ PPB_ PPA_ FINIS FINIS FINIS FINIS FINIS FINIS FINIS FINIS H1 H1 H2 H2 H3 H3 H4 H4 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 DMA_INTR R/W 0 DMA_INTR Indicates pending DMA interrupts, one bit per DMA channel implemented. Bit 0 is used for DMA channel 1, Bit 1 is used for DMA channel 2 etc. Write 0 clear. PPA_Finish1 Indicates dma channel 1 PingPongA finish status. Write 0 clear. PPB_Finish1 Indicates dma channel 1 PingPongB finish status. Write 0 clear. PPA_Finish2 Indicates dma channel 2 PingPongA finish status. Write 0 clear. PPB_Finish2 Indicates dma channel 2 PingPongB finish status. Write 0 clear. PPA_Finish3 Indicates dma channel 3 PingPongA finish status. Write 0 clear. PPB_Finish3 Indicates dma channel 3 PingPongB finish status. Write 0 clear. 345/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 PPA_Finish4 Indicates dma channel 4 PingPongA finish status. Write 0 clear. PPB_Finish4 Indicates dma channel 4 PingPongB finish status. Write 0 clear. USB+0204h Bit 15 DMA Channel 1 Control Register 14 Name Type Reset 13 12 11 10 9 8 ENDM PP_R PP_E BURST_MOD BUS_ AMOD ST N E ERR E2 R/W R/W R/W R/W R/W 0 0 0 0 0 DMA_CNTL1 7 6 5 4 3 2 1 0 INT_E DMA_ DMA_ DMA_ N MODE DIR EN ENDPNT R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 DMA_EN Enable DMA. The bit will be cleared when the DMA transfer is completed. DMA_DIR Direction. 0 : DMA Write(Rx endpoint), 1 : DMA Read(Tx endpoint). DMA_MODE DMA Mode. INT_EN Interrupt Enable. EndPnt[3 :0] Endpoint number. BUS_ERR Bus Error. BURST_MODE Burst Mode. 00 : Burst Mode 0 : Bursts of unspecified length. 01: Burst Mode 1 : INCR4 or unspecified length. 10: Burst Mode 2 : INCR8, INCR4 or unspecified length. 11: Burst Mode 3 : INCR16, INCR8, INCR4 or unspecified length. PP_EN PingPong Buffer Enable. PP_RST The CPU writes 1 to this bit to reset PingPong Buffer Sequence. The bit stands for current PingPong Buffer Sequence when read. EnDMAMode2 Enable DMA mode 2 function. DMA mode 2: The short packets will be moved even the short packets are not the last transfer of this DMA Count. DMA_CNTL2, DMA_CNTL3, DMA_CNTL4, DMA_CNTL5 and DMA_CNTL6 have the same modification. USB+0208h Bit Name Type Reset Bit Name Type Reset DMA Channel 1 ADDRESS Register 31 30 29 28 27 26 15 14 13 12 11 10 25 24 23 22 DMA_ADDR1[31:16] R/W 0 9 8 7 6 DMA_ADDR1[15:0] R/W 0 DMA_ADDR1 21 20 19 18 17 16 5 4 3 2 1 0 DMA_ADDR1 32bits DMA start address, updated (increase) by USB2.0 controller automatically while multiple packet DMA (DMA Mode = 1) is used DMA_ADDR2, DMA_ADDR3, DMA_ADDR4, DMA_ADDR5 and DMA_ADDR6 have the same modification. 346/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 USB+020Ch Bit Name Type Reset Bit Name Type Reset DMA Channel 1 BYTE COUNT Register 31 30 29 28 27 26 15 14 13 12 11 10 25 24 23 22 DMA_COUNT1[31:16] R/W 0 9 8 7 6 DMA_COUNT1[15:0] R/W 0 DMA_COUNT1 21 20 19 18 17 16 5 4 3 2 1 0 DMA_COUNT1 32bits DMA transfer count with byte unit, updated (decrease) by USB2.0 controller automatically while each packet is transferred. DMA_ COUNT 2, DMA_ COUNT3, DMA_ COUNT4, DMA_ COUNT5 and DMA_ COUNT6 have the same modification. USB+0210h Bit Name Type Reset Bit Name Type Reset DMA Channel 1 Limiter Register 31 30 29 15 14 13 28 27 DMA_LIMITER1 26 25 24 23 22 21 20 19 18 17 16 12 11 10 DMA_LIMITER R/W 0 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 DMA_LIMITER This register is to suppress the Bus utilization of the DMA channel. The value is from 0 to 255. 0 means no limitation, and 255 means totally banned. The value between 0 and 255 means certain DMA can have permission to use AHB every (4 X n) AHB clock cycles. Note that it is not recommended to limit the Bus utilization of the DMA channels because this increases the latency of response to the masters, and the transfer rate decreases as well. Before using it, programmer must make sure that the bus masters have some protective mechanism to avoid entering the wrong states. USB+0214h ~ USB+0220h stands for DMA Channel 2 Registers and their behaviors are the same as DMA channel 1. USB+0224h ~ USB+0230h stands for DMA Channel 3 Registers and their behaviors are the same as DMA channel 1. USB+0234h ~ USB+0240h stands for DMA Channel 4 Registers and their behaviors are the same as DMA channel 1. USB+0244h ~ USB+0250h stands for DMA Channel 5 Registers and their behaviors are the same as DMA channel 1. USB+0254h ~ USB+0260h stands for DMA Channel 6 Registers and their behaviors are the same as DMA channel 1. USB+0284h Bit 15 DMA Channel 1 PingPong Control Register 14 13 12 11 10 9 8 Name Type Reset 7 6 DMA_PP_CNTL1 5 4 3 2 1 0 DMA_ EN R/W 0 DMA_EN Enable DMA(PingPong Buffer DMA). The bit will be cleared when the DMA transfer is completed. 347/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 USB+0288h Bit Name Type Reset Bit Name Type Reset DMA_PP_ADDR 1 DMA Channel 1 PingPong Address Register 31 30 29 28 27 26 15 14 13 12 11 10 25 24 23 22 DMA_PP_ADDR1[31:16] R/W 0 9 8 7 6 DMA_PP_ADDR1[15:0] R/W 0 21 20 19 18 17 16 5 4 3 2 1 0 DMA_PP_ADDR1[31:0] DMA(PingPong Buffer DMA) Channel 1 AHB Memory Address. USB+028Ch Bit Name Type Reset Bit Name Type Reset DMA Channel 1 PingPong Count Register 31 30 29 28 27 26 15 14 13 12 11 10 25 24 23 22 DMA_PP_CNT1[31:16] R/W 0 9 8 7 6 DMA_PP_CNT1[15:0] R/W 0 DMA_PP_CNT1 21 20 19 18 17 16 5 4 3 2 1 0 DMA_PP_CNT1[31:0] DMA(PingPong Buffer DMA) Channel 1 Byte Count. USB+0294h ~ USB+029Ch stands for DMA Channel 2 PingPong Registers and their behaviors are the same as DMA channel 1. USB+02A4h ~ USB+02ACh stands for DMA Channel 3 PingPong Registers and their behaviors are the same as DMA channel 1. USB+02B4h ~ USB+02BCh stands for DMA Channel 4 PingPong Registers and their behaviors are the same as DMA channel 1. USB+02C4h ~ USB+02CCh stands for DMA Channel 5 PingPong Registers and their behaviors are the same as DMA channel 1. USB+02D4h ~ USB+02DCh stands for DMA Channel 6 PingPong Registers and their behaviors are the same as DMA channel 1. USB+0400h Bit Name Type Reset Bit Name Type Reset DMA Channel 1 Real Count Register 31 30 29 28 27 26 15 14 13 12 11 10 25 24 23 22 DMA_REALCNT[31:16] R 0 9 8 7 6 DMA_REACNT[15:0] R 0 DMA_REALCNT 21 20 19 18 17 16 5 4 3 2 1 0 DMA_REALCNT[31:0] Indicate current transferred bytes of DMA channel 1. USB+0404h Bit Name Type Reset Bit Name DMA_PP_REAL CNT DMA Channel 1 PingPong Real Count Register 31 30 29 28 27 26 15 14 13 12 11 10 25 24 23 22 DMA_PP_REALCNT[31:16] R 0 9 8 7 6 DMA_PP_REALCNT[15:0] 348/599 21 20 19 18 17 16 5 4 3 2 1 0 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 Type Reset R 0 DMA_PP_REALCNT[31:0] Indicate current transferred bytes of DMA channel 1 PingPong. USB+0408h Bit 15 DMA Channel 1 Timer Register 14 Name Type Reset 13 12 11 10 9 8 7 TIME OUT_ ENTIM STAT ER US R/W R/W 0 0 DMA_TIMER 6 5 4 3 2 1 0 REG_TIMEOUT R/W 0 EnTimer Enable timer. When the timer is enabled and there is no this DMA transaction during the reg_timeout duration, then DMA interrupt will be issued. The timer will be reset whenever EnTimer = 0 or (DMA_EN = 0 and DAM_EN_PP = 0). REG_TIMEOUT To config timeout duration. Timeout duration = 1280 * reg_timeout + 2.5 us. Timeout_Status Indicates the DMA channel has timeout situation. Write 0 clear. USB+0410h ~ USB+0418h stands for DMA Channel 2 Registers and their behaviors are the same as DMA channel 1. USB+0420h ~ USB+0428h stands for DMA Channel 3 Registers and their behaviors are the same as DMA channel 1. USB+0430h ~ USB+0438h stands for DMA Channel 4 Registers and their behaviors are the same as DMA channel 1. USB+0440h ~ USB+0448h stands for DMA Channel 5 Registers and their behaviors are the same as DMA channel 1. USB+0450h ~ USB+0458h stands for DMA Channel 6 Registers and their behaviors are the same as DMA channel 1. 349/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 350/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 USB PHY CONTROL REGISTER USB+0600h Bit 31 HS_T X_I_E Name N_MO DE Type R/W Reset 1 Bit 15 Name Type R/W Reset 0 PHY Control Register 1 30 29 28 27 HS_S HS_T HS_SQ_INIT Q_EN X_SP _EN_DG[1:0] _DG _SEL R/W 0 14 R/W 0 13 R/W 1 12 R/W 1 11 R/W 0 R/W 0 PLL_CCP[3:0] R/W 1 R/W 1 PHYCR1 26 25 24 23 22 21 20 HS_S HS_R Q_EN HS_S CV_E HS_RCVB[3:0] _MOD QS N_MO E DE R/W R/W R/W R/W R/W R/W R/W 1 0 0 0 1 0 0 10 9 8 7 6 5 4 NEG_ USB2 EN_L PLL_ PLL_ TRI_E 0_TX_ S_CM EN CLF N_B TST PSAT R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 19 18 17 16 PLL_VCOG[1 PLL_VCOB[1 :0] :0] R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 GATE BIDI_ CDR_TST _ MODE [1:0] EN_B R/W R/W R/W R/W 0 0 0 0 GATED_EN_B High level clock gating enable 0: enable 1: disable CDR_TST CDR function option ,CDR_TST[1]: phase accumulation option,0: accumulation disable,1: accumulation enable CDR_TST[0]: reference phase number option,0: 4 phases,1: 6 phases BIDI_MODE UTMI data bus bi-directional mode 0: disable,1: enable USB20_TX_TST TX macro test option, debug usage,0: disable,1: enable NEG_TRI_EN_B UTMI output signal aligned to negative edge for hold time issue,0: negative edge triggered output,1: positive edge triggered output PLL_EN USB2.0 PHY PLL enable,0: disable,1: enable EN_LS_CMPSAT LS Tx mode DM RPU compensation enable when in client mode,0: disable,1: enable PLL_CLF PLL loop filter control,0: disable,1: enable PLL_CPP PLL CP bias current selection,charge pump current = 3.125uA * n,0001 : 3.125uA * 1,0010 : 3.125uA * 2…1111 : 3.125uA * 15 PLL_VCOB PLL VCO bias current selection,00: 0uA,01: 25uA * 1.5,10: 25uA * 2.5,11: 25uA * 3.5 PLL_VCOG PLL VCO gain selection ,x0 : enhance Kvco gain,x1: normal Kvco gain HS_RCVB HS RCV bias selection, HS RCV 1st stage bias current,xxx0: 600u,xxx1: 675u HS_RCV_EN_MODE HS RCV enable mode selection,0: HS RCV enable by HS RCV,1: HS RCV always enabled while USB operating in HS mode HS_SQS HS SQ hystress mode Reserved HS_SQ_EN_MODE HS SQ enable mode selection,0: SQ enable by HS RCV,1: SQ always enabled while USB operating HS_SQ_EN_DG HS SQ de-glitch time after HS RCV enabled,0:SQ output de-glitch 4T 480M CLK,1:SQ output de-glitch 5T 480M CLK HS_SQ_INIT_EN_DG HS SQ first time initializing de-glitch:gated by 351/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 00: 1T ref CLK 01: 1.5T ref CLK 10: 2T ref CLK 11: 2.5T ref CLK HS_TX_SP_SEL HS TX LOAD sampling point selection,0: sampling the HS TX data at rising edge,1: sampling the HS TX data at falling edge HS_TX_I_EN_MODE HS TX I enable mode selection,0: HS TX current always enabled while HS TERM enabled,1: HS_TX current enabled when HS TX module enabled USB+0604h Bit 31 FORC E_DR Name V_VB US Type R/W Reset 0 Bit 15 Name Type R/W Reset 0 PHY Control Register 2 30 29 28 FORC FORC E_DM E_DP _PUL _PUL LDOW LDOW N N R/W R/W R/W 0 0 0 14 13 12 HS_SQTL[2:0] R/W R/W R/W 0 1 1 27 26 25 PHYCR2 24 23 R/W 0 21 20 19 18 17 16 FORC FORC HS_T HS_DISCN[1: HS_DISCP[1: E_DA E_TX ERM_ 0] 0] TA_IN VALID SEL HS_TERMC[4:0] R/W 1 11 22 R/W R/W R/W 0 0 0 10 9 8 HS_SQTH[2:0] R/W R/W R/W 1 0 0 R/W 0 7 R/W R/W R/W 0 0 0 6 5 4 HS_SQD[3:0] R/W R/W R/W R/W 0 0 1 0 R/W 0 3 R/W R/W R/W 0 0 1 2 1 0 HS_SQB[3:0] R/W R/W R/W R/W 0 1 0 0 HS_SQB HS SQ bias selection,HS_SQB[0]: HS SQ 1st stage bias current,xxx0: 600uA,xxx1: 675uA HS_SQD HS SQ de-glitch control xx00: 16u (min current, max de-glitch) xx01: 32u xx10: 61u xx11: 122u (max current, min de-glitch) HS_SQTH HS SQ threshold high selection 000: 165mV 001: 155mV 010: 145mV 011: 135mV 100: 125mV 101: 115mV 110: 105mV 111: 95mV HS_SQTL HS SQ threshold low selection,Reserved HS_DISCP HS_DISCP[0] : see HS_DISCN[1:0] ,HS_DISCP[1]: disconnect 1st stage bias current, 0: 420uA 1: 490uA 352/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 HS_DISCN HS DISC reference level HS_DISCP[0],HS_DISCN[1:0] 000: 615mV 001: 605mV 010: 595mV 011: 585mV 100: 575mV 101: 565mV 110: 555mV 111: 545mV HS_TERM_SEL HS TERM module selection (see HS_TERMC),0: analog termination,1: digital termination FORCE_TAVALID FORCE PHY TXVALID SIGNAL ENABLE WHEN PHY_TESTMODE = 1,1: enable 0: disable FORCE_TAVALIDH FORCE PHY TXVALIDH SIGNAL ENABLE WHEN PHY_TESTMODE = 1,1: enable 0: disable HS_TERMC HS TERM impedence control code (see HS_TERM_SEL),In analog termination mode HS_TERM_SEL: 0 internal reference voltage: x0000: 480mV x0001: 470mV x0010: 460mV x0011: 450mV x0100: 440mV x0101: 430mV x0110: 420mV x0111: 410mV x1000: 400mV x1001: 390mV x1010: 380mV x1011: 370mV the final output swing is about (the termnation voltage + 400mv)/2. In digital termination mode HS_TERM_SEL: 1 00000: for max swing ... 11111: for min swing FORCE_DP_PULLDOWN FORCE PHY DP_PULLDOWN SIGNAL ENABLE WHEN PHY_TESTMODE = 1,1: enable 0: disable 353/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 FORCE_DM_PULLDOWN FORCE PHY DM_PULLDOWN SIGNAL ENABLE WHEN PHY_TESTMODE = 1,1: enable 0: disable FORCE_DRV_VBUS FORCE PHY DRV_VBUS SIGNAL ENABLE WHEN PHY_TESTMODE = 1,1: enable 0: disable USB+0608h Bit 31 Name Type R/W Reset 0 Bit 15 Name Type R/W Reset 0 IADJ PHY Control Register 3 30 29 28 27 26 25 PHYCR3 24 23 22 21 20 CLKM AIO1_SEL[2:0] GHX_SEL[3:0] XTAL_BIAS[2:0] ODE R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 1 1 0 1 1 1 1 1 0 0 0 14 13 12 11 10 9 8 7 6 5 4 FEN_ FEN_ FEN_ IREF_ FS_L PLL_DR[5:0] HS_T FS_L MODE S_RC X_I S_TX _SEL V R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 1 0 1 0 0 0 0 0 19 18 17 16 TEST_CTRL[3:0] R/W 0 3 R/W 0 2 FEN_ HS_R CV R/W 0 R/W 0 1 R/W 0 0 IADJ[2:0] R/W 1 R/W 0 R/W 0 HS TX bias current selection 000: 840mV/( Rext + 300) 001: 830mV/( Rext + 300) 010: 820mV/( Rext + 300) 011: 810mV/( Rext + 300) 100: 800mV/( Rext + 300) 101: 790mV/( Rext + 300) 110: 780mV/( Rext + 300) 111: 770mV/( Rext + 300) Rext = 5.1k (typ.) FEN_HS_RCV Forced HS RCV and Squelch enable for test purpose,0: disable,1: enable IREF_MODE_SEL HS SQ reference current mode selection ,0: HS SQ current always enabled while USB operating ,1: HS SQ current enabled while HS RX module enabled FEN_FS_LS_TX Forced FS/LS output enable for test purpose,0: disable,1: enable FEN_FS_LS_RCV Forced FS/LS RCV enable for test purpose,0: disable,1: enable FEN_HS_TX_I Forced HS TX current source enable for test purpose,0: disable,1: enable PLL_DR PLL div ratio 480/reference CLK=PLL_DR ex: 30MHz xtal case, PLL_DR = 480/30 = 16 = 0x10 TEST_CTRL Test mode control TEST_CTRL[3]:0: normal UTMI operation 1: 240MHz clock ouput, with while TEST_CTRL[0]=1 and FEN_HS_TX_I=11 TEST_CTRL[2:1]: 0x: termination resistor connected to PAD_VRT 10: termination resistor connected to PAD_VRT1 354/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 11: termination resistor connected to inaccurate internal 5.1k TEST_CTRL[0]: 0: normal UTMI operation 1: TX controlled by FEN_HS_TX_I/FEN_FS_LS_TX XTAL_BIAS XTAL bias selection Reserved CLKMODE External/Internal input CLK source selection x00: internal clk source USB_INTA1_CK x01: internal clk source USB_INTA2_CK x10: internal clk source USB_INTD_CK GHX_SEL GHX Digital output selection xx00: none xx01: HS DISC output for USB 2.0 RX DC test (see DOUT1_SEL) xx10: HS SQ output for USB 2.0 RX DC test (see DOUT1_SEL) xx11: HS RX output for USB 2.0 RX DC test (see DOUT1_SEL) AIO1_SEL Analog IO1 selection for test (IO via XTALI pin) 0xxx: diable AIO1 100: external bgr input 101: monitor internal bgr voltage 110: monitor internal pll loop filter voltage 111: monitor internal hs termination control voltage AIO ouput only valid for XTALI_GPIO_EN=1 & XTALI_GPIO_OE=0 USB+060Ch Bit 31 PHY Control Register 4 30 29 R/W 0 14 R/W 0 13 28 Name Type R/W Reset 0 Bit 15 R/W 0 12 BGR_ BGR_DIV[1:0 Name SELP ] H Type R/W R/W R/W R/W Reset 0 1 0 0 27 PHYCR4 26 25 24 23 22 21 20 19 18 17 16 XTAL XTALI XTAL XTAL XTAL XTALI XTALI XTALI XTALI XTALI O_GPI _GPIO O_GPI O_GPI O_GPI O_GPI _GPIO _GPIO _GPIO _GPI _I O_OE O_E8 O_EN O_I _OE _E8 _EN O_I O_O R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 0 0 0 0 11 10 9 8 7 6 5 4 3 2 1 0 BGR_ BGR_I BGR_ BGR_ DOUT2_SEL[2:0] DOUT1_SEL[2:0] CHIP_ SRC_ CLK_ BGR_ EN EN EN EN R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 1 0 0 0 0 1 0 0 0 1 0 0 DOUT1_SEL Digital output 1 selection for test (output via VRT pin) 000: normal function 001: bgr ph1 010: bgr ph1s_ 011: bgr pheq_ 100: USB 2.0 RX DC test (see GHX_SEL) 355/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 101: USB 1.1 RXM 110: USB 1.1 RXP 111: USB 1.1 RXD DOUT1 ouput only valid for XTALI_GPIO_EN=1 & XTALI_GPIO_OE=1 DOUT2_SEL Digital output 2 selection for test (output via VRT pin) 000: normal function x01: bgr ph2 x10: bgr ph2s_ x11: bgr pho_ DOUT2 ouput only valid for XTALO_GPIO_EN=1 & XTALO_GPIO_OE=1 BGR_BGR_EN Force BGR enable 0: disable 1: enableBGRCLKEN BGR_CLK_EN Force BGR chop clock enable 0: disable 1: enable BGR_ISRC_EN Force BGR current source generator enable 0: disable 1: enable BGR_CHP_EN BGR_DIV BGR chop enable 0: disable 1: enable BGR chop clk rate 00: 836k 11: 836k/2 10: 836k/4 11: 836k/8 XTALI_GPIO_I XTALI pin GPIO output data Reserved XTALI_GPIO_EN XTALI output pin GPIO enable Reserved XTALI_GPIO_E8 XTALI output pin GPIO output capability control Reserved XTALI_GPIO_OE XTALI output pin GPIO direction selection Reserved XTALO_GPIO_I XTALO pin GPIO output data Reserved XTALO_GPIO_EN XTALO output pin GPIO enable Reserved XTALO_GPIO_E8 XTALO output pin GPIO output capability control Reserved XTALO_GPIO_OE XTALO output pin GPIO direction selection reserved XTALI_GPIO_I XTALI pin GPIO output data Reserved XTALO_GPIO_I XTALO pin GPIO output data Reserved USB+0610h Bit 31 PHY Control Register 5 30 29 28 27 26 DM_P DP_P TERM ULL_ ULL_ XCVR_SELE SUSP _SEL Name DOW DOW CT[1:0] ENDM ECT N N Type R/W Reset 0 Bit 15 R/W 0 14 R/W 0 13 R/W 0 12 R/W 0 11 R/W 0 10 25 PHYCR5 24 19 FORC FORC UTMI_ E_XC USB_MODE[ OP_MODEL[ E_IDP VR_S MUXS ULLU 1:0] 1:0] EL ELEC P T R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 9 8 7 6 5 4 3 356/599 23 22 21 20 18 FORC E_SU SPEN DM R/W 1 2 17 16 FORC E_TE FORC RM_S E_OP ELEC MODE T R/W R/W 0 0 1 0 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 Name PROBE_SEL[7:0] Type R/W Reset 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 VBUS CMP_ CLK_DIV_CNT[2:0] EN R/W R/W R/W R/W R/W 0 1 0 0 0 CDR_FILT[3:0] R/W 0 R/W 0 R/W 1 R/W 0 CDR_FILT CDR low pass filter selection, debug usage CLK_DIVC_CNT The divide ratio of div_ck PROBE_SEL Debug signal selection FORCE_OPMODE FORCE PHY OPMODE SIGNAL ENABLE WHEN PHY_TESTMODE = 1,1: enable 0: disable FORCE_TERM_SELECT FORCE PHY TERM_SELECT SIGNAL ENABLE WHEN PHY_TESTMODE = 1,1: enable 0: disable FORCE_SUSPENDM FORCE PHY SUSPENDM SIGNAL ENABLE WHEN PHY_TESTMODE = 1,1: enable 0: disable FORCE_XCVR_SELECT FORCE PHY XCVR_SELECT SIGNAL ENABLE WHEN PHY_TESTMODE = 1,1: enable 0: disable USB_MODE Test mode selection ( for testing) 00: normal operation 01: loop-back mode1 enable, the pseudo random number will be generated inside USB2.0 PHY macro and transmit onto USB bus. The data will be received by receiver and then be compared. The compared result is muxed on line_state[1] and should be always be 1. 10: loop-back mode2 enable, the packet is longer. UTMI_MUXSEL FORCE PHY UTMI SIGNAL ENABLE WHEN PHY_TESTMODE = 1,1: enable 0: disable FORCE_IDPULLUP FORCE PHY IDPULLUP SIGNAL ENABLE WHEN PHY_TESTMODE = 1,1: enable 0: disable OPMODE It controls the USB2.0 controller to PHY output signal: OPMODE[1:0] when PHY_TESTMODE = 1 TERMSEL It controls the USB2.0 controller to PHY output signal: TERMSEL when PHY_TESTMODE = 1 SUSPENDM It controls the USB2.0 controller to PHY output signal: SUSPENDM when PHY_TESTMODE = 1 XCVRSEL It controls the USB2.0 controller to PHY output signal: XCVRSEL[1:0] when PHY_TESTMODE = 1 DPPULLDOWN It controls the USB2.0 controller to PHY output signal: DPPULLDOWN when PHY_TESTMODE =1 DMPULLDOWN It controls the USB2.0 controller to PHY output signal: DMPULLDOWN when PHY_TESTMODE =1 USB+0614h Bit 31 PHY UTMI Interface Register 1 30 29 28 27 26 25 24 HOST TXRE RXER RXAC RXVA RXVA LINESTATE[ Name DISC ADY ROR TIVE LIDH LID 1:0] ON 357/599 PHYIR1 23 22 21 20 19 18 17 16 XDATA_OUT[15:8] MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 Type Reset Bit R 0 15 R 0 14 R 0 13 Name Type Reset R 0 12 R 0 11 R 0 10 R 0 9 R 0 8 R 0 R 0 R 0 XDATA_OUT[7:0] R 0 R 0 R 0 R 0 R 0 R 0 7 R 0 6 R 0 5 R 0 4 R R R R 0 0 0 0 3 2 1 0 TX_V TX_V DRVV IDPUL XDATA_IN[7:4] ALIDH ALID BUS LUP R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 IDPULLUP It controls the USB2.0 controller to PHY output signal: IDPULLUP when PHY_TESTMODE = 1 DRVVBUS It controls the USB2.0 controller to PHY output signal: DRVVBUS when PHY_TESTMODE = 1 TX_VALID It controls the USB2.0 controller to PHY output signal: TX_VALID when PHY_TESTMODE = 1 TX_VALIDH It controls the USB2.0 controller to PHY output signal: TX_VALIDH when PHY_TESTMODE = 1 XDATA_IN It controls the USB2.0 controller to PHY input signal: XDATA_IN[15:0] when PHY_TESTMODE = 1 XDATA_OUT It controls the USB2.0 controller to PHY input signal: XDATA_OUT[15:0] when PHY_TESTMODE =1 RXVALID It controls the USB2.0 controller to PHY input signal: RXVALID when PHY_TESTMODE = 1 RXVALIDH It controls the USB2.0 controller to PHY input signal: RXVALIDH when PHY_TESTMODE = 1 RXACTIVE It controls the USB2.0 controller to PHY input signal: RXACTIVE when PHY_TESTMODE = 1 RXERROR It controls the USB2.0 controller to PHY input signal: RXERROR when PHY_TESTMODE = 1 TXREADY It controls the USB2.0 controller to PHY input signal: TXREADY when PHY_TESTMODE = 1 HOSTDISCON It controls the USB2.0 controller to PHY input signal: HOSTDISCON when PHY_TESTMODE = 1 LINE_STATE It controls the USB2.0 controller to PHY input signal: LINE_STATE when PHY_TESTMODE = 1 USB+0618h Bit Name Type Reset Bit PHY UTMI Interface Register 2 PHYIR2 31 30 29 28 27 26 25 24 23 22 21 20 19 15 14 13 12 11 10 9 8 7 6 5 4 3 Name Type Reset 18 17 16 2 1 0 VBUS SESS AVALI IDDIG VALID END D R R R R 0 0 0 0 AVALID It controls the USB2.0 controller to PHY input signal: AVALID when PHY_TESTMODE = 1 SESSEND It controls the USB2.0 controller to PHY input signal: SESSEND when PHY_TESTMODE = 1 VBUSVALID It controls the USB2.0 controller to PHY input signal: VBUSVALID when PHY_TESTMODE = 1 IDDIG It controls the USB2.0 controller to PHY input signal: IDDIG when PHY_TESTMODE = 1 7.5 7.5.1 Memory Stick and SD Memory Card Controller Introduction The controller fully supports the Memory Stick bus protocol as defined in Format Specification version 2.0 of Memory Stick Standard (Memory Stick PRO) and the SD Memory Card bus protocol as defined in SD Memory Card Specification 358/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 Part 1 Physical Layer Specification version 1.0 as well as the MultiMediaCard (MMC) bus protocol as defined in MMC system specification version 2.2. Since SD Memory Card bus protocol is backward compatible to MMC bus protocol, the controller is capable of working well as the host on MMC bus under control of proper firmware. Furthermore, the controller also support SDIO card specification version 1.0 partially. However, the controller can only be configured as either the host of Memory Stick or the host of SD/MMC Memory Card at one time. Hereafter, the controller is also abbreviated as MS/SD controller. The following are the main features of the controller. z Interface with MCU by APB bus z 16/32-bit access on APB bus z 16/32-bit access for control registers z 32-bit access for FIFO z Shared pins for Memory Stick and SD/MMC Memory Card z Built-in 32 bytes FIFO buffers for transmit and receive, FIFO is shared for transmit and receive z Built-in CRC circuit z CRC generation can be disabled z DMA supported z Interrupt capabilities z Automatic command execution capability when an interrupt from Memory Stick z Data rate up to 26 Mbps in serial mode, 26x4 Mbps in parallel model, the module is targeted at 26 MHz operating clock z Serial clock rate on MS/SD/MMC bus is programmable z Card detection capabilities z Controllability of power for memory card z Not support SPI mode for MS/SD/MMC Memory Card z Not support multiple SD Memory Cards 7.5.2 Overview 7.5.2.1 Pin Assignment Since the controller can only be configured as either the host of Memory Stick or the host of SD/MMC Memory Card at one time, pins for Memory Stick and SD/MMC Memory Card are shared in order to save pin counts. The following lists pins required for Memory Stick and SD/MMC Memory Card. Table 33 shows how they are shared. In Table 33, all I/O pads have embedded both pull up and pull down resistor because they are shared by both the Memory Stick and SD/MMC Memory Card. Pins 2,4,5,8 are only useful for SD/MMC Memory Card. Pull down resistor for these pins can be used for power saving. All embedded pull-up and pull-down resistors can be disabled by programming the corresponding control registers if optimal pull-up or pull-down resistors are required on the system board. The pin VDDPD is used for power saving. Power for Memory Stick or SD/MMC Memory Card can be shut down by programming the corresponding control 359/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 register. The pin WP (Write Protection) is only valid when the controller is configured for SD/MMC Memory Card. It is used to detect the status of Write Protection Switch on SD/MMC Memory Card. No. 1 2 3 4 5 6 7 8 9 Name SD_CLK SD_DAT3 SD_DAT0 SD_DAT1 SD_DAT2 SD_CMD SD_PWRON SD_WP Type O I/O/PP I/O/PP I/O/PP I/O/PP I/O/PP O SD_INS I MMC CLK MS SCLK CMD SD CLK CD/DAT3 DAT0 DAT1 DAT2 CMD BS MSPRO SCLK DAT3 DAT0 DAT1 DAT2 BS VSS2 VSS2 INS INS DAT0 SDIO I Description Clock Data Line [Bit 3] Data Line [Bit 0] Data Line [Bit 1] Data Line [Bit 2] Command Or Bus State VDD ON/OFF Write Protection Switch in SD Card Detection Table 33 Sharing of pins for Memory Stick and SD/MMC Memory Card Controller 7.5.2.2 Card Detection For Memory Stick, the host or connector should provide a pull up resistor on the signal INS. Therefore, the signal INS will be logic high if no Memory Stick is on line. The scenario of card detection for Memory Stick is shown in Figure 43. Before Memory Stick is inserted or powered on, on host side SW1 shall be closed and SW2 shall be opened for card detection. It is the default setting when the controller is powered on. Upon insertion of Memory Stick, the signal INS will have a transition from high to low. Hereafter, if Memory Stick is removed then the signal INS will return to logic high. If card insertion is intended to not be supported, SW1 shall be opened and SW2 closed always. For SD/MMC Memory Card, detection of card insertion/removal by hardware is also supported. Because a pull down resistor with about 470 KΩ resistance which is impractical to embed in an I/O pad is needed on the signal CD/DAT3, and it has to be capable of being connected or disconnected dynamically onto the signal CD during initialization period, an additional I/O pad is needed to switch on/off the pull down resistor on the system board. The scenario of card detection for SD/MMC Memory Card is shown in Figure 44. Before SD/MMC Memory Card is inserted or powered on, SW1 and SW2 shall be opened for card detection on the host side. Meanwhile, pull down resistor RCD on system board shall attach onto the signal CD/DAT3 by the output signal RCDEN. In addition, SW3 on the card is default to be closed. Upon insertion of SD/MMC Memory Card, the signal CD/DAT3 will have a transition from low to high. If SD/MMC Memory Card is removed then the signal CD/DAT3 will return to logic low. After the card identification process, pull down resistor RCD on system board shall disconnect with the signal CD/DAT3 and SW3 on the card shall be opened for normal operation. Since the scheme above needs a mechanical switch such as a relay on system board, it is not ideal enough. Thus, a dedicated pin “INS” is used to perform card insertion and removal for SD/MMC. The pin “INS” will connect to the pin “VSS2” of a SD/MMC connector. Then the scheme of card detection is the same as that for MS. It is shown in Figure 43. 360/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 HOST CARD output enable RPU SW1 DAT3 OUT PAD INS RPD CD/DAT3 IN SW2 Figure 43 Card detection for Memory Stick output enable HOST CARD RPU 10-90 K SW1 SW3 DAT3 OUT PAD PAD RPD 470 Kohm SW2 RCDEN output enable CD/DAT3 IN Figure 44 Card detection for SD/MMC Memory Card 361/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 7.5.3 Register Definitions REGISTER ADDRESS REGISTER NAME SYNONYM MSDC + 0000h MS/SD Memory Card Controller Configuration Register MSDC_CFG MSDC + 0004h MS/SD Memory Card Controller Status Register MSDC_STA MSDC + 0008h MS/SD Memory Card Controller Interrupt Register MSDC_INT MSDC + 000Ch MS/SD Memory Card Controller Data Register MSDC_DAT MSDC + 00010h MS/SD Memory Card Pin Status Register MSDC_PS MSDC + 00014h MS/SD Memory Card Controller IO Control Register MSDC_IOCON MSDC + 0020h SD Memory Card Controller Configuration Register SDC_CFG MSDC + 0024h SD Memory Card Controller Command Register SDC_CMD MSDC + 0028h SD Memory Card Controller Argument Register SDC_ARG MSDC + 002Ch SD Memory Card Controller Status Register SDC_STA MSDC + 0030h SD Memory Card Controller Response Register 0 SDC_RESP0 MSDC + 0034h SD Memory Card Controller Response Register 1 SDC_RESP1 MSDC + 0038h SD Memory Card Controller Response Register 2 SDC_RESP2 MSDC + 003Ch SD Memory Card Controller Response Register 3 SDC_RESP3 MSDC + 0040h SD Memory Card Controller Command Status Register SDC_CMDSTA MSDC + 0044h SD Memory Card Controller Data Status Register SDC_DATSTA MSDC + 0048h SD Memory Card Status Register SDC_CSTA MSDC + 004Ch SD Memory Card IRQ Mask Register 0 SDC_IRQMASK0 MSDC + 0050h SD Memory Card IRQ Mask Register 1 SDC_IRQMASK1 MSDC + 0054h SDIO Configuration Register SDIO_CFG MSDC + 0058h SDIO Status Register SDIO_STA MSDC + 0060h Memory Stick Controller Configuration Register MSC_CFG MSDC + 0064h Memory Stick Controller Command Register MSC_CMD MSDC + 0068h Memory Stick Controller Auto Command Register MSC_ACMD MSDC + 006Ch Memory Stick Controller Status Register MSC_STA Table 34 MS/SD Controller Register Map 7.5.3.1 Global Register Definitions MSDC+0000h MS/SD Memory Card Controller Configuration Register Bit 31 30 29 28 27 26 25 24 Name FIFOTHD PRCFG2 PRCFG1 Type Reset Bit R/W 0001 14 13 R/W 01 R/W 01 15 12 11 Name SCLKF Type R/W 10 9 8 21 VDDP PRCFG0 D R/W R/W 10 0 7 6 5 SCLK STDB RED ON Y R/W R/W R/W 362/599 23 22 MSDC_CFG 20 19 18 17 16 RCDE DIRQ DMAE PINEN INTEN N EN N R/W R/W R/W R/W R/W 0 0 0 0 0 4 3 2 1 0 CLKS NOCR RST MSDC RC C R/W W R/W R/W MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 Reset 00000000 0 0 1 0 0 0 0 The register is for general configuration of the MS/SD controller. Note that MSDC_CFG[31:16] can be accessed by 16-bit APB bus access. MSDC The register bit is used to configure the controller as the host of Memory Stick or as the host of SD/MMC Memory card. The default value is to configure the controller as the host of Memory Stick. 0 Configure the controller as the host of Memory Stick 1 Configure the controller as the host of SD/MMC Memory card NOCRC CRC Disable. A ‘1’ indicates that data transfer without CRC is desired. For write data block, data will be transmitted without CRC. For read data block, CRC will not be checked. It is for testing purpose. 0 Data transfer with CRC is desired. 1 Data transfer without CRC is desired. RST Software Reset. Writing a ‘1’ to the register bit will cause internal synchronous reset of MS/SD controller, but does not reset register settings. 0 Otherwise 1 Reset MS/SD controller CLKSRC The register bit specifies which clock is used as source clock of memory card. If MUC clock is used, the fastest clock rate for memory card is 52/2=26MHz. If USB clock is used, the fastest clock rate for memory card is 48/2=24MHz. 0 Use MCU clock as source clock of memory card. 1 Use USB clock as source clock of memory card. STDBY Standby Mode. If the module is powered down, operating clock to the module will be stopped. At the same time, clock to card detection circuitry will also be stopped. If detection of memory card insertion and removal is desired, write ‘1’ to the register bit. If interrupt for detection of memory card insertion and removal is enabled, interrupt will take place whenever memory is inserted or removed. 0 Standby mode is disabled. 1 Standby mode is enabled. RED Rise Edge Data. The register bit is used to determine that serial data input is latched at the falling edge or the rising edge of serial clock. The default setting is at the rising edge. If serial data has worse timing, set the register bit to ‘1’. When memory card has worse timing on return read data, set the register bit to ‘1’. 0 Serial data input is latched at the rising edge of serial clock. 1 Serial data input is latched at the falling edge of serial clock. SCLKON Serial Clock Always On. It is for debugging purpose. 0 Not to have serial clock always on. 1 To have serial clock always on. SCLKF The register field controls clock frequency of serial clock on MS/SD bus. Denote clock frequency of MS/SD bus serial clock as fslave and clock frequency of the MS/SD controller as fhost which is 104 or 52 MHz. Then the value of the register field is as follows. Note that the allowable maximum frequency of fslave is 26MHz. 00000000b fslave =(1/2) * fhost 00000001b fslave = (1/(4*1)) * fhost 00000010b fslave = (1/(4*2)) * fhost 00000011b fslave = (1/(4*3))* fhost … 00010000b fslave = (1/(4*16))* fhost 363/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 … 11111111b fslave = (1/(4*255)) * fhost INTEN Interrupt Enable. Note that if interrupt capability is disabled then application software must poll the status of the register MSDC_STA to check for any interrupt request. 0 Interrupt induced by various conditions is disabled, no matter the controller is configured as the host of either SD/MMC Memory Card or Memory Stick. 1 Interrupt induced by various conditions is enabled, no matter the controller is configured as the host of either SD/MMC Memory Card or Memory Stick. DMAEN DMA Enable. Note that if DMA capability is disabled then application software must poll the status of the register MSDC_STA for checking any data transfer request. If DMA is desired, the register bit must be set before command register is written. 0 DMA request induced by various conditions is disabled, no matter the controller is configured as the host of either SD/MMC Memory Card or Memory Stick. 1 DMA request induced by various conditions is enabled, no matter the controller is configured as the host of either SD/MMC Memory Card or Memory Stick. PINEN Pin Interrupt Enable. The register bit is used to control if the pin for card detection is used as an interrupt source. 0 The pin for card detection is not used as an interrupt source. 1 The pin for card detection is used as an interrupt source. DIRQEN Data Request Interrupt Enable. The register bit is used to control if data request is used as an interrupt source. 0 Data request is not used as an interrupt source. 1 Data request is used as an interrupt source. RCDEN The register bit controls the output pin RCDEN that is used for card identification process when the controller is for SD/MMC Memory Card. Its output will control the pull down resistor on the system board to connect or disconnect with the signal CD/DAT3. 0 The output pin RCDEN will output logic low. 1 The output pin RCDEN will output logic high. VDDPD The register bit controls the output pin VDDPD that is used for power saving. The output pin VDDPD will control power for memory card. 0 The output pin VDDPD will output logic low. The power for memory card will be turned off. 1 The output pin VDDPD will output logic high. The power for memory card will be turned on. PRCFG0 Pull Up/Down Register Configuration for the pin WP. The default value is 10. 00 Pull up resistor and pull down resistor in the I/O pad of the pin WP are all disabled. 01 Pull down resistor in the I/O pad of the pin WP is enabled. 10 Pull up resistor in the I/O pad of the pin WP is enabled. 11 Use keeper of IO pad. PRCFG1 Pull Up/Down Register Configuration for the pin CMD/BS. The default value is 0b01. 00 Pull up resistor and pull down resistor in the I/O pad of the pin CMD/BS are all disabled. 01 Pull down resistor in the I/O pad of the pin CMD/BS is enabled. 10 Pull up resistor in the I/O pad of the pin CMD/BS is enabled. 11 Use keeper of IO pad. PRCFG2 Pull Up/Down Register Configuration for the pins DAT0, DAT1, DAT2, DAT3. The default value is 0b01. 00 Pull up resistor and pull down resistor in the I/O pads o the pins DAT0, DAT1, DAT2, DAT3. are all disabled. 01 Pull down resistor in the I/O pads of the pins DAT0, DAT1, DAT2, DAT3 and WP. is enabled. 10 Pull up resistor in the I/O pads of the pins DAT0, DAT1, DAT2, DAT3. is enabled. 364/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 11 Use keeper of IO pad. FIFOTHD FIFO Threshold. The register field determines when to issue a DMA request. For write transactions, DMA requests will be asserted if the number of free entries in FIFO are larger than or equal to the value in the register field. For read transactions, DMA requests will be asserted if the number of valid entries in FIFO are larger than or equal to the value in the register field. The register field must be set according to the setting of data transfer count in DMA burst mode. If single mode for DMA transfer is used, the register field shall be set to 0b0001. 0000 Invalid. 0001 Threshold value is 1. 0010 Threshold value is 2. … 1000 Threshold value is 8. others Invalid MSDC+0004h MS/SD Memory Card Controller Status Register Bit 15 14 FIFOC Name BUSY LR Type R W Reset 0 - 13 12 11 10 9 8 7 6 5 MSDC_STA 4 3 2 1 0 FIFOCNT INT DRQ BE BF RO 0000 RO 0 RO 0 RO 0 RO 0 The register contains the status of FIFO, interrupts and data requests. The register bit indicates if FIFO in MS/SD controller is full. 0 FIFO in MS/SD controller is not full. 1 FIFO in MS/SD controller is full. BE The register bit indicates if FIFO in MS/SD controller is empty. 0 FIFO in MS/SD controller is not empty. 1 FIFO in MS/SD controller is empty. DRQ The register bit indicates if any data transfer is required. While any data transfer is required, the register bit still will be active even if the register bit DIRQEN in the register MSDC_CFG is disabled. Data transfer can be achieved by DMA channel alleviating MCU loading, or by polling the register bit to check if any data transfer is requested. While the register bit DIRQEN in the register MSDC_CFG is disabled, the second method is used. 0 No DMA request exists. 1 DMA request exists. INT The register bit indicates if any interrupt exists. While any interrupt exists, the register bit still will be active even if the register bit INTEN in the register MSDC_CFG is disabled. MS/SD controller can interrupt MCU by issuing interrupt request to Interrupt Controller, or software/application polls the register endlessly to check if any interrupt request exists in MS/SD controller. While the register bit INTEN in the register MSDC_CFG is disabled, the second method is used. For read commands, it is possible that timeout error takes place. Software can read the status register to check if timeout error takes place without OS time tick support or data request is asserted. Note that the register bit will be cleared when reading the register MSDC_INT. 0 No interrupt request exists. 1 Interrupt request exists. FIFOCNT FIFO Count. The register field shows how many valid entries are in FIFO. 0000 There is 0 valid entry in FIFO. 0001 There is 1 valid entry in FIFO. BF 365/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 0010 There are 2 valid entries in FIFO. … 1000 There are 8 valid entries in FIFO. others Invalid FIFOCLR Clear FIFO. Writing ‘1’ to the register bit will cause the content of FIFO clear and reset the status of FIFO controller. 0 No effect on FIFO. 1 Clear the content of FIFO clear and reset the status of FIFO controller. BUSY Status of the controller. If the controller is in busy state, the register bit will be ‘1’. Otherwise ‘0’. 0 The controller is in busy state. 1 The controller is in idle state. MSDC+0008h MS/SD Memory Card Controller Interrupt Register Bit Name Type Reset 15 14 13 12 11 10 9 8 MSDC_INT 7 6 5 4 3 2 1 0 SDIOI SDR1 MSIFI SDMC SDDA SDCM PINIR DIRQ RQ BIRQ RQ IRQ TIRQ DIRQ Q RC RC RC RC RC RC RC RC 0 0 0 0 0 0 0 0 The register contains the status of interrupts. Note that the register still show status of interrupt even though interrupt is disabled, that is, the register bit INTEN of the register MSDC_CFG is set to ‘0. It implies that software interrupt can be implemented by polling the register bit INT of the register MSDC_STA and this register. However, if hardware interrupt is desired, remember to clear the register before setting the register bit INTEN of the register MSDC_CFG to ‘1’. Or undesired hardware interrupt arisen from previous interrupt status may take place. Data Request Interrupt. The register bit indicates if any interrupt for data request exists. Whenever data request exists and data request as an interrupt source is enabled, i.e., the register bit DIRQEN in the register MSDC_CFG is set to ‘1’, the register bit will be active. It will be reset when reading it. For software, data requests can be recognized by polling the register bit DRQ or by data request interrupt. Data request interrupts will be generated every FIFOTHD data transfers. 0 No Data Request Interrupt. 1 Data Request Interrupt occurs. PINIRQ Pin Change Interrupt. The register bit indicates if any interrupt for memory card insertion/removal exists. Whenever memory card is inserted or removed and card detection interrupt is enabled, i.e., the register bit PINEN in the register MSDC_CFG is set to ‘1’, the register bit will be set to ‘1’. It will be reset when the register is read. 0 Otherwise. 1 Card is inserted or removed. SDCMDIRQ SD Bus CMD Interrupt. The register bit indicates if any interrupt for SD CMD line exists. Whenever interrupt for SD CMD line exists, i.e., any bit in the register SDC_CMDSTA is active, the register bit will be set to ‘1’ if interrupt is enabled. It will be reset when the register is read. 0 No SD CMD line interrupt. 1 SD CMD line interrupt exists. SDDATIRQ SD Bus DAT Interrupt. The register bit indicates if any interrupt for SD DAT line exists. Whenever interrupt for SD DAT line exists, i.e., any bit in the register SDC_ DATSTA is active, the register bit will be set to ‘1’ if interrupt is enabled. It will be reset when the register is read. 0 No SD DAT line interrupt. DIRQ 366/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 1 SD DAT line interrupt exists. SDMCIRQ SD Memory Card Interrupt. The register bit indicates if any interrupt for SD Memory Card exists. Whenever interrupt for SD Memory Card exists, i.e., any bit in the register SDC_CSTA is active, the register bit will be set to ‘1’ if interrupt is enabled. It will be reset when the register is read. 0 No SD Memory Card interrupt. 1 SD Memory Card interrupt exists. MSIFIRQ MS Bus Interface Interrupt. The register bit indicates if any interrupt for MS Bus Interface exists. Whenever interrupt for MS Bus Interface exists, i.e., any bit in the register MSC_STA is active, the register bit will be set to ‘1’ if interrupt is enabled. It will be reset when the register MSDC_STA or MSC_STA is read. 0 No MS Bus Interface interrupt. 1 MS Bus Interface interrupt exists. SDR1BIRQ SD/MMC R1b Response Interrupt. The register bit will be active when a SD/MMC command with R1b response finishes and the DAT0 line has transition from busy to idle state. Single block write commands with R1b response will cause the interrupt when the command completes no matter successfully or with CRC error. However, multi-block write commands with R1b response do not cause the interrupt because multi-block write commands are always stopped by STOP_TRANS commands. STOP_TRANS commands (with R1b response) behind multi-block write commands will cause the interrupt. Single block read command with R1b response will cause the interrupt when the command completes but multi-block read commands do not. Note that STOP_TRANS commands (with R1b response) behind multi-block read commands will cause the interrupt. 0 No interrupt for SD/MMC R1b response. 1 Interrupt for SD/MMC R1b response exists. MSDC+000Ch MS/SD Memory Card Controller Data Register Bit Name Type Bit Name Type 31 30 29 28 27 26 25 15 14 13 12 11 10 9 24 23 DATA[31:16] R/W 8 7 DATA[15:0] R/W MSDC_DAT 22 21 20 19 18 17 16 6 5 4 3 2 1 0 The register is used to read/write data from/to FIFO inside MS/SD controller. Data access is in unit of 32 bits. MSDC+0010h MS/SD Memory Card Pin Status Register Bit Name Type Reset Bit 31 15 30 14 29 13 Name CDDEBOUNCE Type Reset RW 0000 28 12 27 11 26 10 25 9 24 CMD RO 8 23 22 MSDC_PS 21 20 19 18 17 16 DAT RO 7 6 5 4 3 2 1 0 PINC POEN PIN0 PIEN0 CDEN HG 0 RC RO R/W R/W R/W 0 1 0 0 0 The register is used for card detection. When the memory card controller is powered on, and the system is powered on, the power for the memory card is still off unless power has been supplied by the PMIC. Meanwhile, pad for card detection defaults to pull down when the system is powered on. The scheme of card detection for MS is the same as that for SD/MMC. 367/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 For detecting card insertion, first pull up INS pin, and then enable card detection and input pin at the same time. After 32 cycles of controller clock, status of pin changes will emerge. For detecting card removal, just keep enabling card detection and input pin. CDEN Card Detection Enable. The register bit is used to enable or disable card detection. 0 Card detection is disabled. 1 Card detection is enabled. PIEN0 The register bit is used to control input pin for card detection. 0 Input pin for card detection is disabled. 1 Input pin for card detection is enabled. POEN0 The register bit is used to control output of input pin for card detection. 0 Output of input pin for card detection is disabled. 1 Output of input pin for card detection is enabled. PIN0 The register shows the value of input pin for card detection. 0 The value of input pin for card detection is logic low. 1 The value of input pin for card detection is logic high. PINCHG Pin Change. The register bit indicates the status of card insertion/removal. If memory card is inserted or removed, the register bit will be set to ‘1’ no matter pin change interrupt is enabled or not. It will be cleared when the register is read. 0 Otherwise. 1 Card is inserted or removed. CDDEBOUNCE The register field specifies the time interval for card detection de-bounce. Its default value is 0. It means that de-bounce interval is 32 cycle time of 32KHz. The interval will extend one cycle time of 32KHz by increasing the counter by 1. DAT Memory Card Data Lines. CMD Memory Card Command Lines. MSDC+0014h MS/SD Memory Card Controller IO Control Register Bit Name Type Reset Bit 31 15 CMDR Name E Type R/W Reset 0 30 14 29 28 27 26 25 24 13 DLT R/W 00000010 12 11 10 9 8 PRCFG3 R/W 10 23 22 7 6 SRCF SRCF G1 G0 R/W R/W 1 1 MSDC_IOCON 21 20 19 18 17 16 5 4 3 2 1 0 ODCCFG1 ODCCFG0 R/W 000 R/W 011 The register specifies Output Driving Capability and Slew Rate of IO pads for MSDC. The reset value is suggestion setting. If output driving capability of the pins DAT0, DAT1, DAT2 and DAT3 is too large, it’s possible to arise ground bounce and thus result in glitch on SCLK. ODCCFG0 Output driving capability the pins CMD/BS and SCLK 000 4mA 010 8mA 100 12mA 110 16mA ODCCFG1 Output driving capability the pins DAT0, DAT1, DAT2 and DAT3 368/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 000 4mA 010 8mA 100 12mA 110 16mA SRCFG0 Output driving capability the pins CMD/BS and SCLK 0 Fast Slew Rate 1 Slow Slew Rate SRCFG1 Output driving capability the pins DAT0, DAT1, DAT2 and DAT3 0 Fast Slew Rate 1 Slow Slew Rate PRCFG3 Pull Up/Down Register Configuration for the pin INS. The default value is 10. 00 Pull up resistor and pull down resistor in the I/O pad of the pin INS are all disabled. 01 Pull down resistor in the I/O pad of the pin INS is enabled. 10 Pull up resistor in the I/O pad of the pin INS is enabled. 11 Use keeper of IO pad. CMDRE The register bit is used to determine whether the host should latch response token (which is sent from card on CMD line ) at rising edge or falling edge of serial clock. 0 Host latches response at rising edge of serial clock 1 Host latches response at falling edge of serial clock DLT Data Latch Timing. The register is used for SW to select the latch timing on data line. Figure 3 illustrates the data line latch timing. sclk_out is the serial clock output to card. div_clk is the internal clock used for generating divided clock. The number “1 2 1 2” means the current sclk_out is divided from div_clk by a ratio of 2. data_in is the output data from card, and latched_data(r)/(f) is the rising/falling edge latched data inside the host (configured by RED in MSDC_CFG). In this example, SCLKF(in MSDC_CFG) is set to 8’b0 which means the division ratio is 2, and DLT is set to 1. Note that the value of DLT CANNOT be set as 0 and its value should not exceed the division ratio ( in the example, the division ratio is 2). Also note that, the latching time will be one div_clk later than the indicated DLT value and the falling edge is always half div_clk ahead from rising edge. The default value of DLT is set to 8’b2. Figure 3 Illustration of data line latch timing 369/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 7.5.3.2 SD Memory Card Controller Register Definitions MSDC+0020h SD Memory Card Controller Configuration Register Bit 31 30 29 28 27 26 25 24 23 22 21 Name DTOC WDOD Type Reset Bit Name Type Reset R/W 00000000 12 11 R/W 0000 15 14 13 BSYDLY R/W 1000 10 9 8 7 6 5 BLKLEN R/W 00000000000 20 4 SDC_CFG 19 18 17 16 MDLW MDLE SDIO SIEN 8 N R/W R/W R/W R/W 0 0 0 0 3 2 1 0 The register is used for configuring the MS/SD Memory Card Controller when it is configured as the host of SD Memory Card. If the controller is configured as the host of Memory Stick, the contents of the register have no impact on the operation of the controller. Note that SDC_CFG[31:16] can be accessed by 16-bit APB bus access. BLKLEN It refers to Block Length. The register field is used to define the length of one block in unit of byte in a data transaction. The maximal value of block length is 2048 bytes. 000000000000 Reserved. 000000000001 Block length is 1 byte. 000000000010 Block length is 2 bytes. … 011111111111 Block length is 2047 bytes. 100000000000 Block length is 2048 bytes. BSYDLY The register field is only valid for the commands with R1b response. If the command has a response of R1b type, MS/SD controller must monitor the data line 0 for card busy status from the bit time that is two serial clock cycles after the command end bit to check if operations in SD/MMC Memory Card have finished. The register field is used to expand the time between the command end bit and end of detection period to detect card busy status. If time is up and there is no card busy status on data line 0, then the controller will abandon the detection. 0000 No extend. 0001 Extend one more serial clock cycle. 0010 Extend two more serial clock cycles. … 1111 Extend fifteen more serial clock cycle. SIEN Serial Interface Enable. It should be enabled as soon as possible before any command. 0 Serial interface for SD/MMC is disabled. 1 Serial interface for SD/MMC is enabled. MDLW8 Eight Data Line Enable. The register works when MDLEN is enabled. The register can be enabled only when MultiMediaCard 4.0 is applied and detected by software application. 0 4-bit Data line is enabled. 1 8-bit Data line is enabled. SDIO SDIO Enable. 0 SDIO mode is disabled 1 SDIO mode is enabled MDLEN Multiple Data Line Enable. The register can be enabled only when SD Memory Card is applied and detected by software application. It is the responsibility of the application to program the bit correctly when an 370/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 MultiMediaCard is applied. If an MultiMediaCard is applied and 4-bit data line is enabled, then 4 bits will be output every serial clock. Therefore, data integrity will fail. 0 4-bit Data line is disabled. 1 4-bit Data line is enabled. WDOD Write Data Output Delay. The period from finish of the response for the initial host write command or the last write data block in a multiple block write operation to the start bit of the next write data block requires at least two serial clock cycles. The register field is used to extend the period (Write Data Output Delay) in unit of one serial clock. 0000 No extend. 0001 Extend one more serial clock cycle. 0010 Extend two more serial clock cycles. … 1111 Extend fifteen more serial clock cycle. DTOC Data Timeout Counter. The period from finish of the initial host read command or the last read data block in a multiple block read operation to the start bit of the next read data block requires at least two serial clock cycles. The counter is used to extend the period (Read Data Access Time) in unit of 65,536 serial clock. See the register field description of the register bit RDINT for reference. 00000000 Extend 65,536 more serial clock cycle. 00000001 Extend 65,536x2 more serial clock cycle. 00000010 Extend 65,536x3 more serial clock cycle. … 11111111 Extend 65,536x 256 more serial clock cycle. MSDC+0024h SD Memory Card Controller Command Register Bit SDC_CMD 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 15 14 13 12 11 10 9 8 7 6 BREA K R/W 0 5 4 3 2 1 Name Type Reset Bit Name INTC STOP RW DTYPE IDRT RSPTYP Type R/W Reset 0 R/W 0 R/W 00 R/W 0 R/W 000 R/W 0 16 CMDF AIL R/W 0 0 CMD R/W 000000 The register defines a SD Memory Card command and its attribute. Before MS/SD controller issues a transaction onto SD bus, application shall specify other relative setting such as argument for command. After application writes the register, MS/SD controller will issue the corresponding transaction onto SD serial bus. If the command is GO_IDLE_STATE, the controller will have serial clock on SD/MMC bus run 128 cycles before issuing the command. CMD SD Memory Card command. It is totally 6 bits. BREAK Abort a pending MMC GO_IRQ_MODE command. It is only valid for a pending GO_IRQ_MODE command waiting for MMC interrupt response. 0 Other fields are valid. 1 Break a pending MMC GO_IRQ_MODE command in the controller. Other fields are invalid. RSPTYP The register field defines response type for the command. For commands with R1 and R1b response, the register SDC_CSTA (not SDC_STA) will update after response token is received. This register SDC_CSTA 371/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 contains the status of the SD/MMC and it will be used as response interrupt sources. Note that if CMD7 is used with all 0’s RCA then RSPTYP must be “000”. And the command “GO_TO_IDLE” also have RSPTYP=’000’. 000 There is no response for the command. For instance, broadcast command without response and GO_INACTIVE_STATE command. 001 The command has R1 response. R1 response token is 48-bit. 010 The command has R2 response. R2 response token is 136-bit. 011 The command has R3 response. Even though R3 is 48-bit response, but it does not contain CRC checksum. 100 The command has R4 response. R4 response token is 48-bit. (Only for MMC) 101 The command has R5 response. R5 response token is 48-bit. (Only for MMC) 110 The command has R6 response. R6 response token is 48-bit. 111 The command has R1b response. If the command has a response of R1b type, MS/SD controller must monitor the data line 0 for card busy status from the bit time that is two or four serial clock cycles after the command end bit to check if operations in SD/MMC Memory Card have finished. There are two cases for detection of card busy status. The first case is that the host stops the data transmission during an active write data transfer. The card will assert busy signal after the stop transmission command end bit followed by four serial clock cycles. The second case is that the card is in idle state or under a scenario of receiving a stop transmission command between data blocks when multiple block write command is in progress. The register bit is valid only when the command has a response token. Note that the response type R4 and R5 mentioned above is for MMC only. For SDIO, RSPTYP definition is different and shall be set to : 001 (i) CMD5 of SDIO is to be issued. (Where the response is defined as R4 in SDIO spec) (ii) CMD52 or CMD53 for READ is to be issued. (Where the response is defined as R5 in SDIO spec) 111 CMD52 for I/O abort or CMD53 for WRITE is to be issued (Where the response is defined as R5 in SDIO spec) Identification Response Time. The register bit indicates if the command has a response with NID (that is, 5 serial clock cycles as defined in SD Memory Card Specification Part 1 Physical Layer Specification version 1.0) response time. The register bit is valid only when the command has a response token. Thus the register bit must be set to ‘1’ for CMD2 (ALL_SEND_CID) and ACMD41 (SD_APP_OP_CMD). 0 Otherwise. 1 The command has a response with NID response time. DTYPE The register field defines data token type for the command. 00 No data token for the command 01 Single block transaction 10 Multiple block transaction. That is, the command is a multiple block read or write command. 11 Stream operation. It only shall be used when an MultiMediaCard is applied. RW The register bit defines the command is a read command or write command. The register bit is valid only when the command will cause a transaction with data token. 0 The command is a read command. 1 The command is a write command. STOP The register bit indicates if the command is a stop transmission command. It should be set to 1 when CMD12 (SD/MMC) or CMD52 with I/O abort (SDIO) is to be issued. 0 The command is not a stop transmission command. 1 The command is a stop transmission command. IDRT 372/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 The register bit indicates if the command is GO_IRQ_STATE. If the command is GO_IRQ_STATE, the period between command token and response token will not be limited. 0 The command is not GO_IRQ_STATE. 1 The command is GO_IRQ_STATE. CMDFAIL The register bit is used for controlling SDIO interrupt period when CRC error or Command/Data timeout condition occurs. It is useful only when SDIO 4-bit mode is activated. 0 SDIO Interrupt period will re-start after a stop command (CMD12) or I/O abort command (CMD52) is issued. 1 SDIO Interrupt period will re-start whenever DAT line is not busy. INTC MSDC+0028h SD Memory Card Controller Argument Register Bit Name Type Bit Name Type 31 30 29 28 27 26 25 15 14 13 12 11 10 9 24 23 ARG [31:16] R/W 8 7 ARG [15:0] R/W SDC_ARG 22 21 20 19 18 17 16 6 5 4 3 2 1 0 The register contains the argument of the SD/MMC Memory Card command. MSDC+002Ch SD Memory Card Controller Status Register Bit 15 Name WP Type Reset R - 14 13 12 11 10 9 8 7 6 5 SDC_STA 4 3 2 1 0 R1BS DATB CMDB SDCB RSV Y USY USY USY RO RO RO RO RO 0 0 0 0 0 The register contains various status of MS/SD controller as the controller is configured as the host of SD Memory Card. SDCBUSY The register field indicates if MS/SD controller is busy, that is, any transmission is going on CMD or DAT line on SD bus. 0 MS/SD controller is idle. 1 MS/SD controller is busy. CMDBUSY The register field indicates if any transmission is going on CMD line on SD bus. 0 No transmission is going on CMD line on SD bus. 1 There exists transmission going on CMD line on SD bus. DATBUSY The register field indicates if any transmission is going on DAT line on SD bus. For those commands without data but still involving DAT line, the register bit is useless. For example, if an Erase command is issued, then checking if the register bit is ‘0’ before issuing next command with data would not guarantee that the controller is idle. In this situation, use the register bit SDCBUSY. 0 No transmission is going on DAT line on SD bus. 1 There exists transmission going on DAT line on SD bus. R1BSY The register field shows the status of DAT line 0 for commands with R1b response. 0 SD/MMC Memory card is not busy. 1 SD/MMC Memory card is busy. 373/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 WP It is used to detect the status of Write Protection Switch on SD Memory Card. The register bit shows the status of Write Protection Switch on SD Memory Card. There is no default reset value. The pin WP (Write Protection) is also only useful while the controller is configured for SD Memory Card. 1 Write Protection Switch ON. It means that memory card is desired to be write-protected. 0 Write Protection Switch OFF. It means that memory card is writable. MSDC+0030h SD Memory Card Controller Response Register 0 Bit Name Type Bit Name Type 31 30 29 28 27 26 25 15 14 13 12 11 10 9 24 23 RESP [31:16] RO 8 7 RESP [15:0] RO SDC_RESP0 22 21 20 19 18 17 16 6 5 4 3 2 1 0 The register contains parts of the last SD/MMC Memory Card bus response. See description for the register field SDC_RESP3. MSDC+0034h SD Memory Card Controller Response Register 1 Bit Name Type Bit Name Type 31 30 29 28 27 26 25 15 14 13 12 11 10 9 24 23 RESP [63:48] RO 8 7 RESP [47:32] RO SDC_RESP1 22 21 20 19 18 17 16 6 5 4 3 2 1 0 The register contains parts of the last SD/MMC Memory Card bus response. See description for the register field SDC_RESP3. MSDC+0038h SD Memory Card Controller Response Register 2 Bit Name Type Bit Name Type 31 30 29 28 27 26 25 15 14 13 12 11 10 9 24 23 RESP [95:80] RO 8 7 RESP [79:64] RO SDC_RESP2 22 21 20 19 18 17 16 6 5 4 3 2 1 0 The register contains parts of the last SD/MMC Memory Card bus response. See description for the register field SDC_RESP3. MSDC+003Ch SD Memory Card Controller Response Register 3 Bit Name Type Bit Name Type 31 30 29 28 27 26 15 14 13 12 11 10 25 24 23 22 RESP [127:112] RO 9 8 7 6 RESP [111:96] RO SDC_RESP3 21 20 19 18 17 16 5 4 3 2 1 0 The register contains parts of the last SD/MMC Memory Card bus response. The register fields SDC_RESP0, SDC_RESP1, SDC_RESP2 and SDC_RESP3 compose the last SD/MMC Memory card bus response. For response of type R2, that is, response of the command ALL_SEND_CID, SEND_CSD and SEND_CID, only bit 127 to 0 of response token is stored in 374/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 the register field SDC_RESP0, SDC_RESP1, SDC_RESP2 and SDC_RESP3. For response of other types, only bit 39 to 8 of response token is stored in the register field SDC_RESP0. MSDC+0040h SD Memory Card Controller Command Status Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 Name Type Reset SDC_CMDSTA 3 2 1 0 RSPC CMDT CMDR MMCI RCER O DY RQ R RC RC RC RC 0 0 0 0 The register contains the status of MS/SD controller during command execution and that of MS/SD bus protocol after command execution when MS/SD controller is configured as the host of SD/MMC Memory Card. The register will also be used as interrupt sources. The register will be cleared when reading the register. Meanwhile, if interrupt is enabled and thus interrupt caused by the register is generated, reading the register will deassert the interrupt. CMDRDY For command without response, the register bit will be ‘1’ once the command completes on SD/MMC bus. For command with response, the register bit will be ‘1’ whenever the command is issued onto SD/MMC bus and its corresponding response is received without CRC error. 0 Otherwise. 1 Command with/without response finish successfully without CRC error. CMDTO Timeout on CMD detected. A ‘1’ indicates that MS/SD controller detected a timeout condition while waiting for a response on the CMD line. 0 Otherwise. 1 MS/SD controller detected a timeout condition while waiting for a response on the CMD line. RSPCRCERR CRC error on CMD detected. A ‘1’ indicates that MS/SD controller detected a CRC error after reading a response from the CMD line. 0 Otherwise. 1 MS/SD controller detected a CRC error after reading a response from the CMD line. MMCIRQ MMC requests an interrupt. A ‘1’ indicates that a MMC supporting command class 9 issued an interrupt request. 0 Otherwise. 1 A ‘1’ indicates that a MMC supporting command class 9 issued an interrupt request. MSDC+0044h SD Memory Card Controller Data Status Register Bit 15 14 13 12 11 10 9 8 7 Name Type Reset 6 5 4 SDC_DATSTA 3 2 1 0 DATC DATT BLKD RCER O ONE R RC RC RC 0 0 0 The register contains the status of MS/SD controller during data transfer on DAT line(s) when MS/SD controller is configured as the host of SD/MMC Memory Card. The register also will be used as interrupt sources. The register will be cleared when reading the register. Meanwhile, if interrupt is enabled and thus interrupt caused by the register is generated, reading the register will deassert the interrupt. BLKDONE The register bit indicates the status of data block transfer. 0 Otherwise. 375/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 1 A data block was successfully transferred. DATTO Timeout on DAT detected. A ‘1’ indicates that MS/SD controller detected a timeout condition while waiting for data token on the DAT line. 0 Otherwise. 1 MS/SD controller detected a timeout condition while waiting for data token on the DAT line. DATCRCERR CRC error on DAT detected. A ‘1’ indicates that MS/SD controller detected a CRC error after reading a block of data from the DAT line or SD/MMC signaled a CRC error after writing a block of data to the DAT line. 0 Otherwise. 1 MS/SD controller detected a CRC error after reading a block of data from the DAT line or SD/MMC signaled a CRC error after writing a block of data to the DAT line. MSDC+0048h SD Memory Card Status Register Bit Name Type Reset Bit Name Type Reset 31 30 29 28 27 26 15 14 13 12 11 10 25 24 23 22 CSTA [31:16] RC 0000000000000000 9 8 7 6 CSTA [15:0] RC 0000000000000000 SDC_CSTA 21 20 19 18 17 16 5 4 3 2 1 0 After commands with R1 and R1b response this register contains the status of the SD/MMC card and it will be used as response interrupt sources. In all register fields, logic high indicates error and logic low indicates no error. The register will be cleared when reading the register. Meanwhile, if interrupt is enabled and thus interrupt caused by the register is generated, reading the register will deassert the interrupt. CSTA31 OUT_OF_RANGE. The command’s argument was out of the allowed range for this card. CSTA30 ADDRESS_ERROR. A misaligned address that did not match the block length was used in the command. CSTA29 BLOCK_LEN_ERROR. The transferred block length is not allowed for this card, or the number of transferred bytes does not match the block length. CSTA28 ERASE_SEQ_ERROR. An error in the sequence of erase commands occurred. CSTA27 ERASE_PARAM. An invalid selection of write-blocks for erase occurred. CSTA26 WP_VIOLATION. Attempt to program a write-protected block. CSTA25 Reserved. Return zero. CSTA24 LOCK_UNLOCK_FAILED. Set when a sequence or password error has been detected in lock/unlock card command or if there was an attempt to access a locked card. CSTA23 COM_CRC_ERROR. The CRC check of the previous command failed. CSTA22 ILLEGAL_COMMAND. Command not legal for the card state. CSTA21 CARD_ECC_FAILED. Card internal ECC was applied but failed to correct the data. CSTA20 CC_ERROR. Internal card controller error. CSTA19 ERROR. A general or an unknown error occurred during the operation. CSTA18 UNDERRUN. The card could not sustain data transfer in stream read mode. CSTA17 OVERRUN. The card could not sustain data programming in stream write mode. CSTA16 CID/CSD_OVERWRITE. It can be either one of the following errors: 1. The CID register has been already written and cannot be overwritten 2. The read only section of the CSD does not match the card. 3. An attempt to reverse the copy (set as original) or permanent WP (unprotected) bits was made. CSTA[15:4] Reserved. Return zero. 376/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 CSTA3 AKE_SEQ_ERROR. Error in the sequence of authentication process CSTA[2:0] Reserved. Return zero. MSDC+004Ch SD Memory Card IRQ Mask Register 0 Bit Name Type Reset Bit Name Type Reset 31 30 29 28 27 26 15 14 13 12 11 10 SDC_IRQMASK0 25 24 23 22 IRQMASK [31:16] R/W 0000000000000000 9 8 7 6 IRQMASK [15:0] R/W 0000000000000000 21 20 19 18 17 16 5 4 3 2 1 0 The register contains parts of SD Memory Card Interrupt Mask Register. See the register description of the register SDC_IRQMASK1 for reference. The register will mask interrupt sources from the register SDC_CMDSTA and SDC_DATSTA. IRQMASK[15:0] is for SDC_CMDSTA and IRQMASK[31:16] for SDC_DATSTA. A ‘1’ in some bit of the register will mask the corresponding interrupt source with the same bit position. For example, if IRQMASK[0] is ‘1’ then interrupt source from the register field CMDRDY of the register SDC_ CMDSTA will be masked. A ‘0’ in some bit will not cause interrupt mask on the corresponding interrupt source from the register SDC_CMDSTA and SDC_DATSTA. MSDC+0050h SD Memory Card IRQ Mask Register 1 Bit Name Type Reset Bit Name Type Reset 31 30 29 28 27 26 15 14 13 12 11 10 SDC_IRQMASK1 25 24 23 22 IRQMASK [63:48] R/W 0000000000000000 9 8 7 6 IRQMASK [47:32] R/W 0000000000000000 21 20 19 18 17 16 5 4 3 2 1 0 The register contains parts of SD Memory Card Interrupt Mask Register. The registers SDC_IRQMASK1 and SDC_IRQMASK0 compose the SD Memory Card Interrupt Mask Register. The register will mask interrupt sources from the register SDC_CSTA. A ‘1’ in some bit of the register will mask the corresponding interrupt source with the same bit position. For example, if IRQMASK[63] is ‘1’ then interrupt source from the register field OUT_OF_RANGE of the register SDC_ CSTA will be masked. A ‘0’ in some bit will not cause interrupt mask on the corresponding interrupt source from the register SDC_ CSTA. MSDC+0054h SDIO Configuration Register Bit Name Type Reset Bit SDIO_CFG 31 30 29 28 27 26 25 24 23 22 21 20 19 15 14 13 12 11 10 9 8 7 6 5 4 3 Name Type Reset 18 17 16 2 1 0 DSBS INTSE INTEN EL L R/W R/W R/W 0 0 0 The register is used to configure functionality for SDIO. INTEN Interrupt enable for SDIO. 377/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 0 Disable 1 Enable INTSEL Interrupt Signal Selection 0 Use data line 1 as interrupt signal 1 Use data line 5 as interrupt signal DSBSEL Data Block Start Bit Selection. 0 Use data line 0 as start bit of data block and other data lines are ignored. 1 Start bit of a data block is received only when data line 0-3 all become low. MSDC+0058h SDIO Status Register Bit Name Type Reset Bit Name Type Reset 7.5.3.3 SDIO_STA 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 IRQ RO 0 Memory Stick Controller Register Definitions MSDC+0060h Memory Stick Controller Configuration Register Bit 15 14 PMOD Name PRED E Type R/W R/W Reset 0 0 13 12 11 10 9 8 7 6 5 MSC_CFG 4 3 2 1 0 BUSYCNT SIEN R/W 101 R/W 0 The register is used for Memory Stick Controller Configuration when MS/SD controller is configured as the host of Memory Stick. Serial Interface Enable. It should be enabled as soon as possible before any command. 0 Serial interface for Memory Stick is disabled. 1 Serial interface for Memory Stick is enabled. BUSYCNT RDY timeout setting in unit of serial clock cycle. The register field is set to the maximum BUSY timeout time (set value x 4 +2) to wait until the RDY signal is output from the card. RDY timeout error detection is not performed when BUSYCNT is set to 0. The initial value is 0x5. That is, BUSY signal exceeding 5x4+2=22 serial clock cycles causes a RDY timeout error. 000 Not detect RDY timeout 001 BUSY signal exceeding 1x4+2=6 serial clock cycles causes a RDY timeout error. 010 BUSY signal exceeding 2x4+2=10 serial clock cycles causes a RDY timeout error. … 111 BUSY signal exceeding 7x4+2=30 serial clock cycles causes a RDY timeout error. PRED Parallel Mode Rising Edge Data. The register field is only valid in parallel mode, that is, MSPRO mode. In parallel mode, data must be driven and latched at the falling edge of serial clock on MS bus. In order to mitigate SIEN 378/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 hold time issue, the register can be set to ‘1’ such that write data is driven by MSDC at the rising edge of serial clock on MS bus. 0 Write data is driven by MSDC at the falling edge of serial clock on MS bus. 1 Write data is driven by MSDC at the rising edge of serial clock on MS bus. PMODE Memory Stick PRO Mode. 0 Use Memory Stick serial mode. 1 Use Memory Stick parallel mode. MSDC+0064h Memory Stick Controller Command Register Bit Name Type Reset 15 14 13 PID R/W 0000 12 11 10 9 8 7 6 MSC_CMD 5 4 DATASIZE R/W 0000000000 3 2 1 0 The register is used for issuing a transaction onto MS bus. Transaction on MS bus is started by writing to the register MSC_CMD. The direction of data transfer, that is, read or write transaction, is extracted from the register field PID. 16-bit CRC will be transferred for a write transaction even if the register field DATASIZE is programmed as zero under the condition where the register field NOCRC in the register MSDC_CFG is ‘0’. If the register field NOCRC in the register MSDC_CFG is ‘1’ and the register field DATASIZE is programmed as zero, then writing to the register MSC_CMD will not induce transaction on MS bus. The same applies for when the register field RDY in the register MSC_STA is ‘0’. DATASIZE Data size in unit of byte for the current transaction. 0000000000 Data size is 0 byte. 0000000001 Data size is one byte. 0000000010 Data size is two bytes. … 0111111111 Data size is 511 bytes. 1000000000 Data size is 512 bytes. PID Protocol ID. It is used to derive Transfer Protocol Code (TPC). The TPC can be derived by cascading PID and its reverse version. For example, if PID is 0x1, then TPC is 0x1e, that is, 0b0001 cascades 0b1110. In addition, the direction of the bus transaction can be determined from the register bit 15, that is, PID[3]. MSDC+0068h Memory Stick Controller Auto Command Register Bit Name Type Reset 15 14 13 APID R/W 0111 12 11 10 9 8 7 6 5 ADATASIZE R/W 0000000001 4 MSC_ACMD 3 2 1 0 ACEN R/W 0 The register is used for issuing a transaction onto MS bus automatically after the MS command defined in MSC_CMD completed on MS bus. Auto Command is a function used to automatically execute a command like GET_INT or READ_REG for checking status after SET_CMD ends. If auto command is enabled, the command set in the register will be executed once the INT signal on MS bus is detected. After auto command is issued onto MS bus, the register bit ACEN will become disabled automatically. Note that if auto command is enabled then the register bit RDY in the register MSC_STA caused by the command defined in MSC_CMD will be suppressed until auto command completes. Note that the register field ADATASIZE cannot be set to zero, or the result will be unpredictable. ACEN Auto Command Enable. 0 Auto Command is disabled. 379/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 1 Auto Command is enabled. ADATASIZE Data size in unit of byte for Auto Command. Initial value is 0x01. 0000000000 Data size is 0 byte. 0000000001 Data size is one byte. 0000000010 Data size is two bytes. … 0111111111 Data size is 511 bytes. 1000000000 Data size is 512 bytes. APID Auto Command Protocol ID. It is used to derive Transfer Protocol Code (TPC). Initial value is GSET_INT(0x7). MSDC+006Ch Memory Stick Controller Status Register Bit 15 14 13 CMDN Name BREQ ERR K Type R R R Reset 0 0 0 12 11 10 9 8 7 6 CED R 0 MSC_STA 5 4 3 2 HSRD CRCE TOER Y R RO RO RO 0 0 0 1 0 SIF RDY RO 0 RO 1 The register contains various status of Memory Stick Controller, that is, MS/SD controller is configured as Memory Stick Controller. These statuses can be used as interrupt sources. Reading the register will NOT clear it. The register will be cleared whenever a new command is written to the register MSC_CMD. RDY SIF The register bit indicates the status of transaction on MS bus. The register bit will be cleared when writing to the command register MSC_CMD. 0 Otherwise. 1 A transaction on MS bus is ended. The register bit indicates the status of serial interface. If an interrupt is active on MS bus, the register bit will be active. Note the difference between the signal RDY and SIF. When parallel mode is enabled, the signal SIF will be active whenever any of the signal CED, ERR, BREQ and CMDNK is active. In order to separate interrupts caused by the signals RDY and SIF, the register bit SIF will not become active until the register MSDC_INT is read once. That is, the sequence for detecting the register bit SIF by polling is as follows: 1. Detect the register bit RDY of the register MSC_STA 2. Read the register MSDC_INT 3. Detect the register bit SIF of the register MSC_STA BS BS0 BS1 BS2 SDIO BS3 BS0 command execution command finished INT IRQ RDY IRQ clear 0 1 SIF IRQ clear Otherwise. An interrupt is active on MS bus 380/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 TOER The register bit indicates if a BUSY signal timeout error takes place. When timeout error occurs, the signal BS will become logic low ‘0’. The register bit will be cleared when writing to the command register MSC_CMD. 0 No timeout error. 1 A BUSY signal timeout error takes place. The register bit RDY will also be active. CRCER The register bit indicates if a CRC error occurs while receiving read data. The register bit will be cleared when writing to the command register MSC_CMD. 0 Otherwise. 1 A CRC error occurs while receiving read data. The register bit RDY will also be active. HSRDY The register bit indicates the status of handshaking on MS bus. The register bit will be cleared when writing to the command register MSC_CMD. 0 Otherwise. 1 A Memory Stick card responds to a TPC by RDY. CED The register bit is only valid when parallel mode is enabled. In fact, it’s value is from DAT[0] when serial interface interrupt takes place. See Format Specification version 2.0 of Memory Stick Standard (Memory Stick PRO) for more details. 0 Command does not terminate. 1 Command terminates normally or abnormally. ERR The register bit is only valid when parallel mode is enabled. In fact, it’s value is from DAT[1] when serial interface interrupt takes place. See Format Specification version 2.0 of Memory Stick Standard (Memory Stick PRO) for more details. 0 Otherwise. 1 Indicate memory access error during memory access command. BREQ The register bit is only valid when parallel mode is enabled. In fact, it’s value is from DAT[2] when serial interface interrupt takes place. See Format Specification version 2.0 of Memory Stick Standard (Memory Stick PRO) for more details. 0 Otherwise. 1 Indicate request for data. CMDNK The register bit is only valid when parallel mode is enabled. In fact, it’s value is from DAT[3] when serial interface interrupt takes place. See Format Specification version 2.0 of Memory Stick Standard (Memory Stick PRO) for more details. 0 Otherwise 1 Indicate non-recognized command. 7.5.4 Application Notes 7.5.4.1 Initialization Procedures After Power On Disable power down control for MSDC module Remember to power on MSDC module before starting any operation to it. 7.5.4.2 Card Detection Procedures The pseudo code is as follows: 381/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 MSDC_CFG.PRCFG0 = 2’b10 MSDC_PS = 2’b11 MSDC_CFG.VDDPD = 1 if(MSDC_PS.PINCHG) { // card is inserted . . . } The pseudo code segment perform the following tasks: 1. First pull up CD/DAT3 (INS) pin. 2. Enable card detection and input pin at the same time. 3. Turn on power for memory card. 4. Detect insertion of memory card. 7.5.4.3 Notes on Commands For MS, check if MSC_STA.RDY is ‘1’ before issuing any command. For SD/MMC, if the command desired to be issued involves data line, for example, commands with data transfer or R1b response, check if SDC_STA.SDCBUSY is ‘0’ before issuing. If the command desired to be issued does not involve data line, only check if SDC_STA.CMDBUSY is ‘0’ before issuing. 7.5.4.4 Notes on Data Transfer z For SD/MMC, if multiple-block-write command is issued then only issue STOP_TRANS command inter-blocks instead of intra-blocks. z Once SW decides to issue STOP_TRANS commands, no more data transfer from or to the controller. 7.5.4.5 Notes on Frequency Change Before changing the frequency of serial clock on MS/SD/MMC bus, it is necessary to disable serial interface of the controller. That is, set the register bit SIEN of the register SDC_CFG to ‘0’ for SD/MMC controller, and set the register bit SIEN of the register MSC_CFG to ‘0’ for Memory Stick controller. Serial interface of the controller needs to be enabled again before starting any operation to the memory card. 7.5.4.6 Notes on Response Timeout If a read command doest not receive response, that is, it terminates with a timeout, then register SDC_DATSTA needs to be cleared by reading it. The register bit “DATTO” should be active. However, it may take a while before the register bit becomes active. The alternative is to send the STOP_TRANS command. However, this method will receive response with illegal-command information. Also, remember to check if the register bit SDC_STA.CMDBUSY is active before issuing the STOP_TRANS command. The procedure is as follows: 1. Read command => response time out 2. Issue STOP_TRANS command => Get Response 3. Read register SDC_DATSTA to clear it 382/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 7.5.4.7 Source or Destination Address is not word-aligned It is possible that the source address is not word-aligned when data move from memory to MSDC. Similarly, destination address may be not word-aligned when data move from MSDC to memory. This can be solved by setting DMA byte-to-word functionality. 1. DMAn_CON.SIZE=0 2. DMAn_CON.BTW=1 3. DMAn_CON.BURST=2 (or 4) 4. DMAn_COUNT=byte number instead of word number 5. fifo threshold setting must be 1 (or 2), depending on DMAn_CON.BURST Note n=4 ~ 11 7.5.4.8 z Miscellaneous notes Siemens MMC card: When a write command is issued and followed by a STOP_TRANS command, Siemens MMC card will de-assert busy status even though flash programming has not yet finished. Software must use “Get Status” command to make sure that flash programming finishes. 7.6 2D acceleration 7.6.1 2D Engine 7.6.1.1 General Description To enhance MMI display and gaming experiences, a 2D acceleration engine is implemented. It supports ARGB8888, RGB888, ARGB4444, RGB565 and 8-bpp color modes. Main features are listed as follows: z Rectangle fill with color gradient. z Bitblt: multi-Bitblt without transform, 7 rotate, mirror (transparent) Bitblt z Alpha blending z Binary ROP z Line drawing: normal line, dotted line, anti-alias line z Font caching: normal font, italic font z Circle drawing or circle fill z Quadratic Bezier curve drawing z Triangle drawing z Polygon fill with single color or image pattern 383/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 z Thick line drawing z Specific output color replacement MCU can program 2D engine registers via APB. However, MCU has to make sure that the 2D engine is not BUSY before any write to 2D engine registers occurs. An interrupt scheme is also provided for more flexibility. A command parser is implemented for further offloading of MCU. The command queue can be randomly assigned in the system memory, with a maximum depth of 2047 commands. If the command queue is enabled, MCU has to check if the command queue has free space before writing to the command queue. Command queue parser will consume command queue entries upon 2D engine requests. Figure 45 shows the command queue and 2D engine block diagram. Please refer to the graphic command queue functional specification for more details. Command queue DST memory read/write control Command parser APB 2D engine slave Graphic Memory Interface SRC memory read control Figure 45 The command queue and 2D engine block diagram. 7.6.1.2 7.6.1.2.1 Features Introduction 2D Coordinate The coordinates in the 2D engine are represented as 12-bit signed integers. The negative part is clipped during rendering. The maximum resolution can achieve 2047x2047 pixels. The programmed base address is mapped to the origin of the picture, which is illustrated in Figure 46. 384/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 dst_base_addr x (0,0) y Figure 46 The coordinate of the 2D engine. 7.6.1.2.2 Color format The 2D engine support the color format of 8bpp, RGB565, RGB888, ARGB4444, and ARGB 8888. The color formats of source and destination can be specified separately. Note that when using the 8bpp format, the source and destination color formats have to be the same, since table-lookup of color palette is not provided in 2D engine. Graphic modes of Bitblt, Bitblt with alpha blending, and Bitblt with binary ROP require color format setting for both source and destination. For other graphic modes, only destination color format needs to be specified. The possible settings are listed as Table 35Table 36. Bitblt (Copy, ROP) Source color format Destination color format 8bpp 8bpp RGB565 RGB565 RGB888 RGB565 RGB888 RGB888 ARGB4444 ARGB8888 ARGB4444 ARGB8888 ARGB4444 ARGB8888 Table 35 source and destination color format setting for Bitblt. Bitblt with Alpha Blending Source color format Destination color format 8bpp 8bpp RGB565 RGB888 RGB565 RGB888 RGB565 385/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 RGB888 RGB565 ARGB4444 RGB888 RGB565 ARGB8888 RGB888 Table 36 source and destination color format setting for alpha blending. When source image is used, the source key function could be enabled or disabled. When enabled, the source color key is in the same format of source color. Be aware that the source key is still effective for alpha blending mode. 7.6.1.2.3 Clipping Window The setting for clipping window is effective for all the 2D graphics. A pair of minimum and maximum boundary is applied on destination side. The portion outside the clipping window will not be drawn to the destination, but the pixels on the boundary will be kept. The clipping operation is illustrated in Figure 47. dst_base_addr (0,0) g2d_clp_min g2d_clp_max Figure 47 The clipping operation of the 2D engine. 7.6.1.2.4 Bitblt operation The Bitblt function copies the pixels from source picture to destination. To be more flexible, 4 copy directions and 7 kinds of rotations are provided when doing Bitblt operation. Figure 48 illustrates the Bitblt operation and required settings. dst_base_addr src_base_addr (dst_x,dst_y) (src_x,src_y) D S src_h src_w dst_x_pitch src_x_pitch 386/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 Figure 48 The clipping operation of the 2D engine. Note that the size of source and destination blocks can be different. If the source block is larger than destination block, the size of destination block is used instead of the source size. When source block size is smaller than destination block size, the pattern of source block is repeated horizontally and vertically in the destination block, which is illustrated as Figure 49 below. Source Destination Figure 49 The Bitblt operation when destination size > source size. 7.6.1.2.4.1 Copy direction When the source block and destination blocks are on the same picture, they may be overlapped by each other. To prevent error from occurring, 4 directions for Bitblt can be programmed. However, the copy direction shall not be enabled when doing rotation, or it will produce unwanted results. The 4 kinds of copy direction are shown in Figure 50. D S S D S D D S Figure 50 The 4 directions of Bitblt operation. 7.6.1.2.4.2 Rotation To facilitate Bitblt operation, 7 kinds of rotation can be set at the same time. The rotation operation is illustrated as Figure 51. Here the rotation is done on the destination side, while the read sequence of pixels in source block is fixed. 387/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 S (src_x,src_y) 1).No rotation 2).180 degree rotation 3).horizontal flip 4).vertical flip D D D D 5).90 degree rotation (dst_x,dst_y) 6).270 degree rotation 7).90 degree rotation + vertical flip D D D 8).270 degree rotation + vertical flip D Figure 51 The rotations of Bitblt operation. 7.6.1.2.5 Bitblt with Alpha Blending Similar to simple Bitblt operation, alpha blending function is provided as well. The pixels in source block are blended onto destination block. Blending is performed according the formula listed below: C = (alpha * Cs + (255 - alpha) * Cd)/255 , where Cs is the source color, Cd is the destination color, and alpha is an unsigned integer range from 0 to 255. The alpha value programmed into the 2D control registers is called constant alpha. When no alpha channel exists, the constant alpha is used to calculate blended color. If the alpha channel exists ( in ARGB color mode), the per-pixel alpha is used for blending operation instead of constant alpha. In addition, the setting of copy directions and rotations are also effective for alpha blending mode. format of source block can be different from destination. 7.6.1.2.6 Also, the size and color Bitblt with Binary ROP The ROP (Raster Operation) is another block-wise functional mode. Here the 2D engine provides a set of binary ROPs. The ROP code has 16 different combinations, which is listed in the definition of 2D control registers --G2D_SMODE_CON. Please see sec.7.6.1.3 for detail descriptions. Similar with other block-wise functions, the copy directions and rotations are also applicable in ROP mode. color format of source and destination do not need to be the same. 7.6.1.2.7 The size and Rectangle Fill with Color Gradient Rectangle fill mode provides the configurations for color gradient for both x-direction and y-direction. Each of the color gradient of component A, R, G, B is represented by 9.16 signed fixed point number. In order to prevent color crossing the boundary of 0 and 255, it is clipped to 0 and 255 when performing gradient fill. When the color gradient is disabled, the rectangle is filled by one color. An example of gradient fill is shown in Figure 52. 388/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 start_clr x_gradient y_gradient Figure 52 Rectangle gradient fill. 7.6.1.2.8 Line Draw The line drawing function is implemented with the mid-point algorithm. Given the two endpoints of a line, the points on the line are calculated recursively. The line anti-aliasing is also supported but it requires extra register configurations. In addition, dotted line is also provided for use. Simultaneously turning on anti-aliasing and dotted-line is not recommended since the line may result in a strange look. 7.6.1.2.9 Circle Draw The circle drawing is quite similar with line drawing, using the mid-point algorithm as well. A center point and a radius have to be programmed into 2D control registers. There are 4 enable bits for each quadrant of a circle, each determines whether the arcs shall be rendered or not. The setting of circle drawing is illustrated in Figure 53. 3 0 radius (dst_x,dst_y) 2 1 Figure 53 Circle drawing. 7.6.1.2.10 Bezier curve The quadratic Bezier curve is implemented, too. The quadratic Bezier curve is defined by three control points, as illustrated in Figure 54. The Bezier curve drawing is implemented with subdivision method. The amount of subdivisions is programmed by software. The curve gets more detailed with the increase of subdivision factor, but it requires more memory and computing time. bytes. To be more precise, doing n times of subdivision needs a buffer of 2 ( n +1) * 4 389/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 p1 p2 p0 Figure 54 Bezier curve. 7.6.1.2.11 Triangle Flat Fill The 2D engine supports the function of triangle flat fill with the help of software. First, the software divides the triangle into upper plane and lower plane and passes them to hardware individually. Given the starting vertex’s coordinate and the slopes of left and right edges, the 2D hardware fills the horizontal segments between the two edges until the horizontal end is reached. The slope of each edge is in 12.16 bit signed fix-point representation. The programming of triangle drawing is illustrated in Figure 55. start point left slope right slope Horizontal end Horizontal end left slope right slope start point Figure 55 Triangle drawing. 390/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 7.6.1.2.12 Font Drawing The 2D engine helps to render fonts stored in one-bit-per-pixel format. It expends the zero bits to background color and expands one bits to foreground color. The background color can be set as transparent. The font drawing can be programmed as tilt, when given each line’s tilt value. The start bit of font drawing can be non-byte aligned to save memory usage for font caching. be performed at the same time when drawing fonts. 7.6.1.2.13 In addition, the rotations can Polygon Fill In MT6511, 2D engine supports the function of polygon fill with its edges specified in memory. The maximum number of edge is 2047, which will occupy 32KB memory space (16 bytes per edge) during polygon fill processing. Software need to indicate the starting address of input edge list by setting G2D_BUF_STA_ADDR_0 and allocate another memory space for the polygon fill processing by setting G2D_BUF_STA_ADDR_1. It’s noted that filling a polygon with a list of cross edges will cause an un-expected result. Dividing this kind of polygon into several ones without cross edges is recommended. Polygon fill with image is also supported. The maximum image pattern size is 64x64 which is needed to be put in memory starting from BUF_STA_ADDR_2. Figure 56 Polygon fill. Figure 57 Cross edges. Divide into 1 - 5 triangles is recommended. Figure 14 Polygon fill with image pattern. 391/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 7.6.1.2.14 Thick Line Drawing 2D engine line drawing with thickness, i.e. thick line drawing. The two end caps of the thick line could be selected as round type or flat (no end cap). Line pattern is also supported in thick line drawing mode. No end cap would be added in patterned thick line. Figure 16 Thick Line Drawing, odd thickness and even thickness. 7.6.1.3 Register Definitions Table 37 The 2D engine register mapping. summarizes the 2D engine register mapping on APB and through command queue. The base address of 2D engine is 80670000h. CMQ APB Address mapped Address Register Function Acronym G2D+0100h 100h 2D engine fire mode control register FMODE_CON 102h Reserved 104h 2D Engine sub-mode control lower register SMODE_CON_L 106h 2D Engine sub-mode control higher register SMODE_CON_H 108h 2D engine common control register COM_CON 10Ah Reserved 110h 2D engine status register 112h Reserved 200h Source base address lower hword register SRC_BASE_L 202h Source base address higher hword register SRC_BASE_H 204h Source pitch register SRC_PITCH 206h Reserved 208h Source y coordinate register SRC_Y 20Ah Source x coordinate register SRC_X G2D+0104h G2D+0108h G2D+0110h G2D+0200h G2D+0204h G2D+0208h G2D+020Ch G2D+0210h STA 20Ch Source height register SRC_H 20Eh Source width register SRC_W 210h Source color key lower hword register SRC_KEY_L 212h Source color key lower hword register SRC_KEY_H 392/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 G2D+0300h G2D+0304h G2D+0308h G2D+030Ch G2D+0310h G2D+0318h G2D+320 G2D+324 G2D+400h G2D+404h G2D+408h G2D+40Ch G2D+410h G2D+414h G2D+418h G2D+41Ch G2D+420h 300h Destination base address lower hword register DST_BASE_L 302h Destination base address higher hword register DST_BASE_H 304h Destination Pitch Register DST_PITCH 306h Reserved 308h Destination y coordinate register 0 DST_Y0 30Ah Destination x coordinate register 0 DST_X0 30Ch Destination y coordinate register 1 DST_Y1 30Eh Destination x coordinate register 1 DST_X1 310h Destination y coordinate register 2 DST_Y2 312h Destination x coordinate register 2 DST_X2 318h Destination height register DST_H 31Ah Destination width register DST_W 320h Pattern width and height register PAT_WH 322h Pattern x and y offset register PAT_XY 324h Pattern pitch Register PAT_PITCH 400h Foreground color lower hword register FGCLR_L 402h Foreground color lower hword register FGCLR_H 404h Background color lower hword register BGCLR_L 406h Background color lower hword register BGCLR_H 408h Clipping minimum y coordinate register CLP_MIN_Y 40Ah Clipping minimum x coordinate register CLP_MIN_X 40Ch Clipping maximum y coordinate register CLP_MAX_Y 40Eh Clipping maximum x coordinate register CLP_MAX_X 410h Rectangle color gradient of alpha componet x lower hword register ALPGR_X_L 412h Rectangle color gradient of alpha componet x higher hword register ALPGR_X_H 414h Rectangle color gradient of red component y lower hword register REDGR_X_L 416h Rectangle color gradient of red component y higher hword register REDGR_X_H 418h Rectangle color gradient of green component x lower hword register GREENGR_X_L 41Ah Rectangle color gradient of green component x higher hword register GREENGR_X_H 41Ch Rectangle color gradient of blue component x lower hword register BLUEGR_X_L 41Eh Rectangle color gradient of blue component x higher hword register BLUE_X_H 420h Rectangle color gradient of alpha component y lower hword register ALPGR_Y_L 422h Rectangle color gradient of alpha component y ALPGR_Y_H 393/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 higher hword register G2D+424h G2D+428h G2D+42Ch G2D+430h G2D+434h G2D+438h 424h Rectangle color gradient of red component y lower hword register REDGR_Y_L 426h Rectangle color gradient of red component y higher hword register REDGR_Y_H 428h Rectangle color gradient of green component y lower hword register GREENGR_Y_L 42Ah Rectangle color gradient of green component y higher hword register GREENGR_Y_H 42Ch Rectangle color gradient of blue component y lower hword register BLUEGR_Y_L 42Eh Rectangle color gradient of blue component y higher hword register BLUEGR_Y_H 430h Buffer 0 start address lower hword register BUF_STA_ADDR_0 _L 432h Buffer 0 start address higher hword register BUF_STA_ADDR_0 _H 434h Buffer 1 start address lower hword register BUF_STA_ADDR_1 _L 436h Buffer 1 start address higher hword register BUF_STA_ADDR_1 _H 438h Buffer 2 start address lower hword register BUF_STA_ADDR_2 _L 43Ah Buffer 2 start address higher hword register BUF_STA_ADDR_2 _H G2D+0700h ~ 700h ~ 71Fh G2D+071Fh TILT_0300 ~ TILT_1F1C Table 37 The 2D engine register mapping. There are several function modes in 2D graphics engine. Some registers are shared between different them. Table 38 summarizes the settings under different function modes. APB Address CMQ Addres Rectangle fill s Bitblt Operations G2D+0200h 200h SRC_BASE G2D+0204h 204h SRC_PITCH G2D+0208h 208h SRC_XY G2D+020Ch 20Ch SRC_SIZE G2D+0210h 210h SRC_KEY Line/Circle drawing Bezier curve drawing Triangle drawing Font caching SLOPE_L SRC_BASE SRC_KEY G2D+0214h 214h AVO_CLR AVO_CLR AVO_CLR AVO_CLR AVO_CLR AVO_CLR G2D+0218h 218h REP_CLR REP_CLR REP_CLR REP_CLR REP_CLR REP_CLR G2D+0300h 300h DST_BASE DST_BASE DST_BASE DST_BASE DST_BASE DST_BASE G2D+0304h 304h DST_PITCH DST_PITCH DST_PITCH DST_PITCH DST_PITCH DST_PITCH G2D+0308h 308h DST_XY DST_XY DST_XY_START DST_XY DST_XY0 394/599 DST_XY0 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 DST_XY1/ RADIUS G2D+030Ch 30Ch G2D+0310h 310h G2D+0318h 318h DST_XY1 DST_Y_END DST_XY2 DST_SIZE DST_SIZE DST_SIZE G2D+0320h 320h G2D+0324h 324h G2D+0400h 400h START_CLR G2D+0404h 404h FGCLR DST_KEY XY_SQRT FGCLR FGCLR FGCLR BGCLR G2D+0408h 408h CLP_MIN CLP_MIN CLP_MIN CLP_MIN CLP_MIN CLP_MIN G2D+040Ch 40Ch CLP_MAX CLP_MAX CLP_MAX CLP_MAX CLP_MAX CLP_MAX G2D+0410h 410h ALPGD_X G2D+0414h 414h RED_GD_X G2D+0418h 418h GREEN_GD_X G2D+041Ch 41Ch BLUE_GD_X G2D+0420h 420h ALPGD_Y G2D+0424h 424h RED_GD_Y G2D+0428h 428h GREEN_GD_Y G2D+042Ch 42Ch BLUE_GD_Y G2D+430h 430h G2D+434h 434h G2D+438h 438h G2D+0700h 700h ~ ~ 71Fh G2D+071Fh APB Address SUBDIV_TIME BUF_STA_ADD SLOPE_R TILT_0300 ~ TILT_1F1C CMQ Horizontal Line Addres Gradient s G2D+0200h 200h TILT_0300 ~ TILT_1F1C Horizontal Line Copy with Mask TILT_0300 ~ TILT_1F1C Polygon Fill with Image Pattern Thick Line Drawing SRC_BASE G2D+0204h 204h G2D+0208h 208h G2D+020Ch 20Ch SRC_SIZE G2D+0210h 210h G2D+0214h 214h AVO_CLR AVO_CLR AVO_CLR AVO_CLR G2D+0218h 218h REP_CLR REP_CLR REP_CLR REP_CLR G2D+0300h 300h DST_BASE DST_BASE DST_BASE DST_BASE DST_PITCH DST_PITCH G2D+0304h 304h G2D+0308h 308h DST_XY0 G2D+030Ch 30Ch DST_XY1 G2D+0310h 310h 395/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 G2D+0318h 318h DST_SIZE DST_SIZE G2D+320h 320h PAT_XYWH G2D+324h 324h PAT_PITCH G2D+0400h 400h START_CLR FG_CLR FG_CLR G2D+0408h 408h CLP_MIN CLP_MIN G2D+040Ch 40Ch CLP_MAX CLP_MAX G2D+0404h 404h G2D+0410h 410h ALPGD_X G2D+0414h 414h RED_GD_X G2D+0418h 418h GREEN_GD_X G2D+041Ch 41Ch BLUE_GD_X TLINE_CON G2D+0420h 420h G2D+0424h 424h G2D+0428h 428h G2D+042Ch 42Ch G2D+430h 430h MASK_BASE EDGE_ADDR EDGE_ADDR G2D+434h 434h SORT_ADDR SORT_ADDR G2D+438h 438h PAT_ADDR G2D+0700h 700h ~ ~ 71Fh G2D+071Fh Table 38 2D engine common registers Below shows common control registers. G2D+0100h Bit Name Type Reset 15 G2D_FMODE_C ON Graphic 2D Engine Fire Mode Control Register 14 13 12 11 10 9 SRC_CLR_MODE R/W 000 8 7 6 5 DST_CLR_MODE R/W 000 4 3 2 1 0 G2D_ENG_MODE R/W 0000 Write this register will fire the 2D engine according to the CLR_MODE and ENG_MODE field. SRC_CLR_MODE source color mode 000 8-bpp, LUT disabled 001 16-bpp, RGB 565 format 010 32-bpp, ARGB 8888 format 011 24-bpp, RGB 888 format 101 16-bpp, ARGB 4444 format others reserved DST_CLR_MODE destination color mode 000 8-bpp, LUT disabled 001 16-bpp, RGB 565 format 396/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 010 32-bpp, ARGB 8888 format 011 24-bpp, RGB 888 format 101 16-bpp, ARGB 4444 format others reserved G2D_ENG_MODE 2D engine function mode 0000 Line draw. 0001 Circle draw. 0010 Bezier curve draw. 0011 Triangle fill. 0110 Polygon fill. 0111 Thick line mode. 1000 Rectangle fill. 1001 Bitblt. 1010 Bitblt with alpha blending. 1011 Bitblt with ROP. 1100 Font drawing. 1101 Horizontal line fill with color gradient. In this mode, the source key and the clipping functions are disabled automatically. 1110 Horizontal line copy with mask. In this mode, the source key and the clipping functions are disabled automatically. others not allowed G2D+0104h Bit 31 G2D_SMODE_C ON Graphic 2D Engine Sub-mode Control Register 30 29 FMSB Name FITA FNBG _FIRS T Type R/W R/W R/W Reset 0 0 0 Bit 15 14 13 28 12 27 26 CLR_ CF_E REP_ N EN R/W R/W 0 0 11 10 Name LDOT Type Reset R/W 0 25 9 24 8 23 22 21 20 19 18 17 ALPHA ROP_CODE R/W 0000 R/W 0000 7 6 DST_ CLRG LAA_ KEY_ LIMG D_EN EN EN R/W R/W R/W R/W 0 0 0 0 5 4 3 2 1 BDIR BITA BROT R/W 11 R/W 0 R/W 111 16 0 Write this register to set the 2D engine configuration. FITA font italic enabled. FNBG font drawing with no background color FMSB_FIRST font drawing from most significant bit CLR_REP_EN Output color replacement enable. CF_EN Circle fill enabled. ALPHA Bit 7-4 of constant alpha value. ROP_CODE is Bit3-0 of constant alpha value. ROP_CODE Binary ROP code. Bits 2-0 are also used to specify the start bit position for Font drawing and enabled arcs for circle drawing. 397/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 Bitblt ROP Code Boolean Function Start Bit Position for Font Drawing Enabled Arcs 0000 0 (Black) Bit 0 None 0001 ~(S + D) Bit 1 I 0010 ~S . D Bit 2 Ⅱ 0011 ~S Bit 3 Ⅰ, Ⅱ 0100 S . ~D Bit 4 Ⅲ 0101 ~D Bit 5 Ⅰ, Ⅲ 0110 S^D Bit 6 Ⅱ, Ⅲ 0111 ~(S . D) Bit 7 Ⅰ,Ⅱ, Ⅲ 1000 S.D Bit 0 Ⅳ 1001 ~(S ^ D) Bit 1 Ⅰ, Ⅳ 1010 D Bit 2 Ⅱ, Ⅲ 1011 ~S + D Bit 3 Ⅰ, Ⅱ, Ⅳ 1100 S Bit 4 Ⅲ, Ⅳ 1101 S + ~D Bit 5 Ⅰ, Ⅲ, Ⅳ 1110 S+D Bit 6 Ⅱ, Ⅲ, Ⅳ 1111 1 (White) Bit 7 S = Source, D = Destination. I = first quadrant, II = second quadrant, III = third quadrant, IV = fourth quadrant. Ⅰ, Ⅱ, Ⅲ, Ⅳ LIMG Polygon fill with image pattern. LDOT line dotted LAA_EN line anti-aliasing enabled DST_KEY_EN Destination key enabled for Bitblt functions CLRGR_EN Color gradient enabled for rectangle fill BDIR Bitblt direction: 00 from lower right corner 01 from lower left corner 10 from upper right corner 11 from upper left corner This field only takes effect when the Bitblt rotation is set as none (111). When doing rotation the Bitblt direction of source image is always from upper left corner. BITA Bitblt italic enabled, using the tilt value defined in G2D_TILT_00 ~ G2D_TILT_1F registers. The tilt function should not be enabled in Alpha Blending and ROP mode. BROT Bitblt rotation: 000 mirror then rotate 90 001 rotate 90 010 rotate 270 011 mirror then rotate 270 100 rotate 180 398/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 101 mirror 110 mirror then rotate 180 111 none G2D+0108h Bit Name Type Reset Bit Graphic 2D Engine Common Control Register G2D_COM_CON 31 30 29 28 27 26 25 24 23 22 21 20 19 18 15 14 13 12 11 10 9 8 7 6 5 4 3 2 Name Type Reset 17 16 1 0 SRCK CLP_ EY_E RST EN N R/W R/W R/W 0 0 0 Write this register to set the 2D engine configuration. RST 2D engine reset, only the state machine is reset, the content of control registers will not be reset. SRCKEY_EN Source key enabled. CLP_EN Clipping enabled. G2D+010Ch Bit Name Type Reset Bit Name Type Reset Graphic 2D Engine Interrupt Control Register G2D_IRQ_CON 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EN R/W 0 Write this register to set the 2D engine IRQ configuration. EN interrupt enable. The interrupt is negative edge sensitive. G2D+0110h Bit Name Type Reset Bit Name Type Reset Graphic 2D Engine Common Status Register G2D_COM_STA 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BUSY RO 0 Read this register to get the 2D engine status. 2D engine may function abnormally if any 2D engine register is modified when BUSY. BUSY 2D engine is busy 399/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 G2D+0200h Bit Name Type Reset Bit Name Type Reset G2D_SRC_BAS E Graphic 2D Source Base Address Register 31 30 29 28 27 26 15 14 13 12 11 10 25 24 23 22 SRC_BASE[31:16] R/W 0 9 8 7 6 SRC_BASE[15:0] R/W 0 21 20 19 18 17 16 5 4 3 2 1 0 SRC_BASE The base address of source image. Also, this field is used for the slope of the left triangle edges represented in 12.16 format. G2D+0204h Bit Name Type Reset 15 14 13 12 11 10 9 8 7 6 5 SRC_PITCH R/W 0 4 3 2 1 0 The width of source image in the unit of pixels. SRC_PITCH G2D+0208h Bit Name Type Reset Bit Name Type Reset G2D_SRC_PITC H Graphic 2D Engine Source Pitch Register Graphic 2D Engine Source X and Y Register 31 30 29 28 27 26 25 24 23 15 14 13 12 11 10 9 8 7 22 21 SRC_X R/W 0 6 5 SRC_Y R/W 0 G2D_SRC_XY 20 19 18 17 16 4 3 2 1 0 SRC_Y The starting y co-ordinate of source image. It must be positive although represented as 12-bit signed integer. SRC_X The starting x co-ordinate of source image. It must be positive although represented as 12-bit signed integer. G2D+020Ch Bit Name Type Reset Bit Name Type Reset Graphic 2D Engine Source Size Register 31 30 29 28 27 26 25 24 23 15 14 13 12 11 10 9 8 7 22 21 SRC_W R/W 0 6 5 SRC_H R/W 0 G2D_SRC_SIZE 20 19 18 17 16 4 3 2 1 0 SRC_H The source height for Bitblt, alpha blending and ROP. It must be positive although represented as 12-bit signed integer. SRC_W The source width for Bitblt, alpha blending and ROP. It must be positive although represented as 12-bit signed integer. 400/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 G2D+0210h Bit Name Type Reset Bit Name Type Reset Graphic 2D Engine Source Color Key Register 31 30 29 28 27 26 15 14 13 12 11 10 25 24 23 22 SRC_KEY[31:16] R/W 0 9 8 7 6 SRC_KEY[15:0] R/W 0 G2D_SRC_KEY 21 20 19 18 17 16 5 4 3 2 1 0 SRC_KEY The source color key. The color will be transparent if color keying is enabled. G2D+0214h Bit Name Type Reset Bit Name Type Reset G2D_DST_AVO_ CLR Graphic 2D Engine Destination Avoidance Color 31 30 29 28 27 26 15 14 13 12 11 10 25 24 23 22 DST_AVO_CLR[31:16] R/W 0 9 8 7 6 DST_AVO_CLR[15:0] R/W 0 21 20 19 18 17 16 5 4 3 2 1 0 DST_AVO_CLR The output color with DST_AVO_CLR would be replaced with DST_REP_CLR when CLR_REP_EN is enabled. G2D+0218h Bit Name Type Reset Bit Name Type Reset G2D_DST_REP_ CLR Graphic 2D Engine Destination Replacement Color 31 30 29 28 27 26 15 14 13 12 11 10 25 24 23 22 DST_REP_CLR[31:16] R/W 0 9 8 7 6 DST_REP_CLR[15:0] R/W 0 21 20 19 18 17 16 5 4 3 2 1 0 DST_REP_CLR The output color with DST_AVO_CLR would be replaced with DST_REP_CLR when CLR_REP_EN is enabled. G2D+0300h Bit Name Type Reset Bit Name Graphic 2D Destination Base Address Register 31 30 29 28 27 26 15 14 13 12 11 10 25 24 23 22 DST_BASE[31:16] R/W 0 9 8 7 6 DST_BASE[15:0] 401/599 G2D_DST_BASE 21 20 19 18 17 16 5 4 3 2 1 0 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 Type Reset R/W 0 DST_BASE The base address of destination image. G2D+0304h Bit Name Type Reset 15 14 13 12 11 10 9 8 7 6 5 SRC_PITCH R/W 0 4 3 2 1 0 The width of destination image in the unit of pixels. DST_PITCH G2D+0308h Bit Name Type Reset Bit Name Type Reset G2D_DST_PITC H Graphic 2D Engine Destination Pitch Register Graphic 2D Engine Destination X and Y Register 0 31 30 29 28 27 26 25 24 23 15 14 13 12 11 10 9 8 7 22 21 DST_X0 R/W 0 6 5 DST_Y0 R/W 0 G2D_DST_XY0 20 19 18 17 16 4 3 2 1 0 (DST_X0 , DST_Y0) is used as the starting co-ordinate in Bitblt, alpha blending, ROP, and font drawing mode. In line mode or triangle fill mode, it is used as one end point. For Bezier curve drawing, it is one of the control points. While in circle drawing mode, it is the center of the circle. Also this filed is used as the starting point of triangle draw. DST_X0 DST_Y0 Represented by 12-bit signed integer. Negative co-ordinate is allowed. Represented by 12-bit signed integer. Negative co-ordinate is allowed. G2D+030Ch Bit Name Type Reset Bit Name Type Reset Graphic 2D Engine Destination X and Y Register 1 31 30 29 28 27 26 25 24 23 15 14 13 12 11 10 9 8 7 22 21 DST_X1 R/W 0 6 5 DST_Y1 R/W 0 G2D_DST_XY1 20 19 18 17 16 4 3 2 1 0 (DST_X1 , DST_Y1) is used as one end point in Line drawing and triangle fill mode. For Bezier curve drawing, it is one of the control points. While in circle drawing mode, DST_X1 must be positive since it is the radius of the circle. Also, Bit 15-0 is used as the vertical end of triangle draw. DST_X1 DST_Y1 Represented by 12-bit signed integer. Negative co-ordinate is allowed. Represented by 12-bit signed integer. Negative co-ordinate is allowed. G2D+0310h Bit Name Type 31 Graphic 2D Engine Destination X and Y Register 2 30 29 28 27 26 25 24 402/599 23 22 21 DST_X2 R/W 20 G2D_DST_XY2 19 18 17 16 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 Reset Bit Name Type Reset 15 14 13 12 11 10 9 8 7 0 6 5 DST_Y2 R/W 0 4 3 2 1 0 (DST_X2 , DST_Y2) is used as one end point in triangle fill mode. For Bezier curve drawing, it is one of the control points. DST_X2 DST_Y2 Represented by 12-bit signed integer. Negative co-ordinate is allowed. Represented by 12-bit signed integer. Negative co-ordinate is allowed. G2D+0318h Bit Name Type Reset Bit Name Type Reset Graphic 2D Engine Destination Size Register 31 30 29 28 27 26 25 24 23 15 14 13 12 11 10 9 8 7 22 21 DST_W R/W 0 6 5 DST_H R/W 0 G2D_DST_SIZE 20 19 18 17 16 4 3 2 1 0 SRC_H The source height for Bitblt, alpha blending and ROP. It must be positive although represented as 12-bit signed integer. SRC_W The source width for Bitblt, alpha blending and ROP. It must be positive although represented as 12-bit signed integer. G2D+0320h Bit Name Type Reset Bit Name Type Reset G2D_PAT_XYW H Graphic 2D Engine Pattern X Y W H Register 31 30 29 28 15 14 13 12 27 26 PAT_X R/W 0 11 10 PAT_W R/W 0 25 24 23 22 21 20 9 8 7 6 5 4 19 18 PAT_Y R/W 0 3 2 PAT_H R/W 0 17 16 1 0 PAT_X The starting x co-ordinate of pattern image for Polygon-Fill. PAT_Y The starting y co-ordinate of pattern image for Polygon-Fill. PAT_W The pattern width for Polygon-Fill. PAT_H The pattern height for Polygon-Fill. G2D+0324h Bit Name Type Reset Bit Name G2D_PAT_PITC H Graphic 2D EnginePattern Pitch Register 31 30 29 28 27 26 25 24 23 22 21 20 15 14 13 12 11 10 9 8 7 6 5 4 403/599 19 18 3 2 PAT_PITCH 17 16 1 0 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 Type Reset R/W 0 PAT_PITCH The width of pattern in the unit of pixels. G2D+0400h Bit Name Type Reset Bit Name Type Reset The maximum width of pattern is 32. Graphic 2D Engine Foreground Color Register 31 30 29 28 27 26 25 15 14 13 12 11 10 9 24 23 FGCLR[31:16] R/W 0 8 7 FGCLR[15:0] R/W 0 G2D_ FGCLR 22 21 20 19 18 17 16 6 5 4 3 2 1 0 FGCLR The foreground color used for line/circle drawing and font drawing. It is also the start color of rectangle fill. The format of foreground color depends on the source color mode set in G2D_FMODE_CON register. G2D+0404h Bit Name Type Reset Bit Name Type Reset Graphic 2D Engine Background Color Register 31 30 29 28 27 26 25 15 14 13 12 11 10 9 24 23 BGCLR[31:16] R/W 0 8 7 BGCLR[15:0] R/W 0 G2D_BGCLR 22 21 20 19 18 17 16 6 5 4 3 2 1 0 BGCLR The background color of the source. The format of background color depends on the source color mode set in G2D_FMODE_CON register. Bit 15-0 also used as the XY_SQRT for anti-aliased line drawing. The XY_SQRT calculation is listed as bellow. XY _ SQRT = 2 * ( DST _ X 1 − DST _ X 0) 2 + ( DST _ Y 1 − DST _ Y 0) 2 G2D+0408h Bit Name Type Reset Bit Name Type Reset Graphic 2D Engine Clipping Minimum Register 31 30 29 28 27 26 25 24 23 15 14 13 12 11 10 9 8 7 CLIP_MIN_X CLIP_MIN_Y 31 19 18 17 16 3 2 1 0 The minimum value of x co-ordinate in clipping window, signed 12-bit integer. The minimum value of y co-ordinate in clipping window, signed 12-bit integer.. G2D+040ch Bit Name Type 22 21 20 CLIP_MIN_X R/W 0 6 5 4 CLIP_MIN_Y R/W 0 G2D_CLIP_MIN Graphic 2D Engine Clipping Maximum Register 30 29 28 27 26 25 24 404/599 23 22 21 20 CLIP_MAX_X R/W G2D_CLIP_MAX 19 18 17 16 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 Reset Bit Name Type Reset 15 14 13 12 11 10 9 8 11111111111 6 5 4 CLIP_MAX_Y R/W 11111111111 7 3 2 1 0 CLIP_MAX_X The maximum value of x co-ordinate in clipping window, signed 12-bit integer... CLIP_MAX_Y The maximum value of y co-ordinate in clipping window, signed 12-bit integer.. G2D+0410h Bit Name Type Reset Bit Name Type Reset Graphic 2D X Alpha Gradient Register 31 30 29 28 27 26 25 24 23 22 15 14 13 12 11 10 9 8 7 6 ALPHA_GR_X[15:0] R/W 0 G2D_ALPGR_X 21 20 19 ALPHA_GR_X[24:16] R/W 0 5 4 3 18 17 16 2 1 0 The color gradient of alpha in x direction for rectangle gradient fill. ALPHA_GR_X The color gradient of alpha channel, represented in signed 9.16 format. G2D+0414h Bit Name Type Reset Bit Name Type Reset Graphic 2D X Red Gradient Register 31 30 29 28 27 26 25 15 14 13 12 11 10 9 24 23 G2D_REDGR_X 22 8 7 6 RED_GR_X[15:0] R/W 0 The color gradient of red in x direction for rectangle gradient fill. curve drawing. 21 20 19 RED_GR_X[24:16] R/W 0 5 4 3 18 17 16 2 1 0 Bit 3-0 also used as the times of subdivision for Bezier RED_GR_XThe color gradient of red component, represented in signed 9.16 format. G2D+0418h Bit Name Type Reset Bit Name Type Reset G2D_ GREENGR_X Graphic 2D X Green Gradient Register 31 30 29 28 27 26 25 24 23 22 15 14 13 12 11 10 9 8 7 6 GREEN_GR_X[15:0] R/W 0 21 20 19 18 GREEN_GR_X[24:16] R/W 0 5 4 3 2 17 16 1 0 GREEN_GR_X The color gradient of blue component, represented in signed 9.16 format. GREEN_GR_X[15] Enable thick line pattern. GREEN_GR_X[14] Thick line starting point cap drawing enable. 405/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 GREEN_GR_X[13] Thick line end point cap drawing enable. GREEN_GR_X[12] Thickness error auto compensation enable. GREEN_GR_X[11] Adjusted polygon fill algorithm for thick line drawing. GREEN_GR_X[10:0]Thickness of the thick line. G2D+041Ch Bit Name Type Reset Bit Name Type Reset Graphic 2D X Blue Gradient Register 31 30 29 28 27 26 25 15 14 13 12 11 10 9 BLUE_GR_X 23 22 8 7 6 BLUE_GR_X[15:0] R/W 0 21 20 19 BLUE_GR_X[24:16] R/W 0 5 4 3 18 17 16 2 1 0 The color gradient of blue component, represented in signed 9.16 format. G2D+0420h Bit Name Type Reset Bit Name Type Reset 24 G2D_BLUEGR_X Graphic 2D Y Alpha Gradient Register 24 23 G2D_ALPGR_Y 31 30 29 28 27 26 25 22 15 14 13 12 11 10 9 8 7 6 ALPHA_GR_Y[15:0] R/W 0 21 20 19 ALPHA_GR_Y[24:16] R/W 0 5 4 3 18 17 16 2 1 0 The color gradient of alpha in x direction for rectangle gradient fill. ALPHA_GR_Y The color gradient of alpha channel, represented in signed 9.16 format. G2D+0424h Bit Name Type Reset Bit Name Type Reset Graphic 2D Y Red Gradient Register 31 30 29 28 27 26 25 15 14 13 12 11 10 9 24 23 G2D_REDGR_Y 22 8 7 6 RED_GR_Y[15:0] R/W 0 21 20 19 RED_GR_Y[24:16] R/W 0 5 4 3 18 17 16 2 1 0 The color gradient of red in x direction for rectangle gradient fill. RED_GR_YThe color gradient of red component, represented in signed 9.16 format. G2D+0428h Bit Name Type Reset Bit G2D_ GREENGR_Y Graphic 2D Y Green Gradient Register 31 30 29 28 27 26 25 24 23 22 15 14 13 12 11 10 9 8 7 6 406/599 21 20 19 GREEN_GR_Y24:16] R/W 0 5 4 3 18 17 16 2 1 0 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 Name Type Reset GREEN_GR_Y15:0] R/W 0 GREEN_GR_Y The color gradient of blue component, represented in signed 9.16 format. G2D+042Ch Bit Name Type Reset Bit Name Type Reset Graphic 2D Y Blue Gradient Register 31 30 29 28 27 26 25 15 14 13 12 11 10 9 BLUE_GR_Y 23 22 8 7 6 BLUE_GR_Y[15:0] R/W 0 21 20 19 BLUE_GR_Y[24:16] R/W 0 5 4 3 18 17 16 2 1 0 The color gradient of blue component, represented in signed 9.16 format. G2D+0430h Bit Name Type Reset Bit Name Type Reset 24 G2D_BLUEGR_Y G2D_BUF_STA_ ADDR_0 Graphic 2D Engine Buffer Start Address 0 31 30 29 28 27 26 15 14 13 12 11 10 25 24 23 22 BUF_STA_ADDR_0[31:16] R/W 0 9 8 7 6 BUF_STA_ADDR_0[15:0] R/W 0 21 20 19 18 17 16 5 4 3 2 1 0 BUF_STA_ADDR_0 The buffer 0 start address. Buffer 0 is used for storing temporal CP data for Bezier Curve function, raw edge data for Polygon-Fill function, and temporary edge (4 edges) storage for thick line drawing. Also, this field is used for the slope of the right triangle edges represented in signed 12.16 format and mask address of horizontal line copy with mask function. G2D+0434h Bit Name Type Reset Bit Name Type Reset G2D_BUF_STA_ ADDR_1 Graphic 2D Engine Buffer Start Address 1 31 30 29 28 27 26 15 14 13 12 11 10 25 24 23 22 BUF_STA_ADDR_1[31:16] R/W 0 9 8 7 6 BUF_STA_ADDR_1[15:0] R/W 0 21 20 19 18 17 16 5 4 3 2 1 0 BUF_STA_ADDR_1 The buffer 1 start address. Buffer 1 is used for storing edge processing temporal data for Polygon-Fill function. G2D+0438h Bit 31 G2D_BUF_STA_ ADDR_2 Graphic 2D Engine Buffer Start Address 2 30 29 28 27 26 25 24 407/599 23 22 21 20 19 18 17 16 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 Name Type Reset Bit Name Type Reset 15 14 13 12 11 10 BUF_STA_ADDR_2[31:16] R/W 0 9 8 7 6 BUF_STA_ADDR_2[15:0] R/W 0 5 4 3 2 1 0 BUF_STA_ADDR_2 The buffer 2 start address. Buffer 2 is used for storing image data for polygon fill with image pattern. 7.6.2 Command Queue 7.6.2.1 General Description To enhance MMI display and gaming experiences, a command queue controllrt is implemented for further offloading of MCU. If the command queue is enabled, software program has to check the command queue free space before writing to the command queue data register. Command queue parser will consume command queue entries upon 2D engine requests. Figure 45 shows the command queue and 2D engine block diagram. DST memory read/write control Command parser Command queue APB slave 2D engine SRC memory read control Register bank Figure 58 The command queue and 2D engine block diagram. 7.6.2.2 Register Definitions MCU APB bus registers are listed as followings. The base address of the command queue controller is 80660000h. GCMQ+0000h Graphic Command Queue Control Register Bit Name 31 30 29 28 27 26 25 24 408/599 23 22 21 GCMQ_CON 20 19 18 17 16 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 Type Reset Bit Name Type Reset EN WEN 15 14 13 12 11 10 9 8 7 6 5 4 3 2 31 15 WR_R Name DY Type RO Reset 0 GCMQ_STA 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FREE RO 100000000 FREE number of free command queue entries WR_RDY ready to receive command, command-write is not allowed when this status bit is 0. this bit before writing command to gcmq. Software has to check GCMQ+0008h Graphic Command Queue Data Register Bit Name Type Bit Name Type 31 30 29 28 27 26 25 24 15 14 13 12 11 10 9 8 7 DATA WO ADDR [11:0] DATA [15:0] 23 GCMQ_DAT 22 21 ADDR WO 6 5 20 19 18 17 16 4 3 2 1 0 write address for mapped 2D engine registers write data for mapped 2D engine registers GCMQ_BASE_A DD GCMQ+000Ch Graphic Command Queue Base Address Register Bit Name Type Bit Name Type 0 EN R/W 0 command queue enable. When EN is low, the command queue controller will be reset. command queue in write mode. When WEN is low, the command queue will consume the commands in the queue if command queue is not empty. GCMQ+0004h Graphic Command Queue Status Register Bit Name Type Reset Bit 1 WEN R/W 0 31 30 29 28 27 26 15 14 13 12 11 10 25 24 23 22 BASE_ADD[31:16] R/W 9 8 7 6 BASE_ADD[15:0] R/W 21 20 19 18 17 16 5 4 3 2 1 0 BASE_ADD the starting address of the command queue in the memory. Note : This field only can be modified while the command queue is not enabled. Otherwise the behavior of the command queue will be unpredictable. GCMQ+0010h Graphic Command Queue Buffer Length Register Bit 31 30 29 28 27 26 25 24 409/599 23 22 21 20 GCMQ_LENGTH 19 18 17 16 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 Name Type Bit Name Type 15 14 13 12 11 10 9 8 7 6 5 LENGTH R/W 4 3 2 1 0 LENGTH[9:0] the occupied space of the command queue in the memory is LENGTH *4Bytes. Note : This field only can be modified while the command queue is not enabled. Otherwise the behavior of the command queue will be unpredictable. GCMQ_DMA_AD DR GCMQ+0014h Graphic Command Queue Current Register Bit Name Type Bit Name Type 31 30 29 28 27 26 15 14 13 12 11 10 25 24 23 22 GCMQ_DMA_ADDR RO 9 8 7 6 GCMQ_DMA_ADDR RO 21 20 19 18 17 16 5 4 3 2 1 0 GCMQ_DMA_ADDR the current read or write DMA address of GCMQ. 7.7 Camera Interface ISP Hue Grab Sensor (SOC) TG Saturation Color Process Brightness Contrast DownSample MT6235 ISP support VGA/XGA Sensor YUV422/RGB565 interface. Included Functions are Brightness、Contrast、 Saturation、Hue Tuning and Input Image Grab Window. Down Sample Function can be used before image output from ISP. 7.7.1 Register Table REGISTER ADDRESS REGISTER NAME SYNONYM CAM + 0000h TG Phase Counter Register CAM_PHSCNT CAM + 0004h Sensor Size Configuration Register CAM_CAMWIN CAM + 0008h TG Grab Range Start/End Pixel Configuration Register CAM_GRABCOL CAM + 000Ch TG Grab Range Start/End Line Configuration Register CAM_GRABROW 410/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 CAM + 0010h Sensor Mode Configuration Register CAM_CSMODE CAM + 0018h View Finder Mode Control Register CAM_VFCON CAM + 001Ch Camera Module Interrupt Enable Register CAM_INTEN CAM + 0020h Camera Module Interrupt Status Register CAM_INTSTA CAM + 0024h Camera Module Path Config Register CAM_PATH CAM + 0028h Camera Module Input Address Register CAM_INADDR CAM + 002Ch Camera Module Output Address Register CAM_OUTADDR CAM + 0030h Preprocessing Control Register 1 CAM_CTRL1 CAM + 00B8h Y Channel Configuration Register CAM_YCHAN CAM + 00BCh UV Channel Configuration Register CAM_UVCHAN CAM + 00C0h Space Convert YUV Register 1 CAM_SCONV1 CAM + 00C4h Space Convert YUV Register 2 CAM_SCONV2 CAM + 0128h Vertical Subsample Control Register CAM_VSUB CAM + 012Ch Horizontal Subsample Control Register CAM_HSUB CAM + 0174h Result Window Vertical Size Register RWINV_SEL CAM + 0178h Result Window Horizontal Size Register RWINH_SEL CAM + 0180h Camera Interface Debug Mode Control Register CAM_DEBUG CAM + 0184h Camera Module Debug Information Write Out Destination Address CAM_DSTADDR CAM + 0188h Camera Module Debug Information Last Transfer Destination Address CAM_LSTADDR CAM + 018Ch Camera Module Frame Buffer Transfer Out Count Register CAM_XFERCNT CAM + 0190h Sensor Test Module Configuration Register 1 CAM_MDLCFG1 CAM + 0194h Sensor Test Module Configuration Register 2 CAM_MDLCFG2 CAM + 01D8h Cam Reset Register CAM_RESET CAM + 01DCh TG Status Register TG_STATUS CAM + 0248h GMC Debug Register CAM_GMCDEBUG CAM + 0274h Cam Version Register CAM_VERSION Table 39 Camera Interface Register Map 7.7.1.1 TG Register Definitions CAM+0000h Bit 31 30 Name PCEN Type R/W Reset 0 Bit 15 14 TG Phase Counter Register 29 28 CLKE CLKP N OL R/W R/W 0 0 13 12 27 11 CLKF HVALI PXCL PXCL PXCL Name L_PO D_EN K_EN K_INV K_IN L Type R/W R/W R/W R/W R/W Reset 0 0 0 0 0 26 25 24 CAM_PHSCNT 23 22 21 20 19 18 17 CLKCNT CLKRS CLKFL R/W 1 R/W 0 R/W 1 10 9 8 TGCL K_SE L R/W 0 411/599 7 6 5 4 3 2 1 PIXCNT DLATCH R/W 1 R/W 1 16 0 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 TG phase counter enable control Enable sensor master clock (mclk) output to sensor Sensor master clock polarity control Sensor master clock frequency divider control. Sensor master clock will be 52Mhz/CLKCNT, where CLKCNT >=1. Sensor master clock rising edge control Sensor master clock falling edge control Sensor hvalid or href enable Sensor clock input monitor. Pixel clock inverse Pixel clock sync enable. If sensor master based clock is 48 Mhz, PXCLK_IN must be enabled. Sensor clock falling edge polarity Sensor master based clock selection (0: 52 Mhz, 1: 48 Mhz) Sensor data latch frequency control Sensor data latch position control Example waveform(CLKCNT=1,CLKRS=0,CLKFL=1,PIXCNT=3,DLATCH=2) PCEN CLKEN CLKPOL CLKCNT CLKRS CLKFL HVALID_EN PXCLK_EN PXCLK_INV PXCLK_IN CLKFL_POL TGCLK_SEL PIXCNT DLATCH Internal Clock Sync 52Mhz ISP output signals CLKCNT=1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 2 0 1 0 1 3 0 1 2 0 1 3 0 CLKRS=0 mclk CLKFL=1 Sensor output signals hsync pclk Bclk 0 PIXCNT=3 Pixel_ID 1 2 0 3 0 1 1 2 3 0 1 2 2 3 3 4 1 5 DLATCH=2 CAM+0004h Bit Name Type Reset Bit Name Type Reset PIXEL LINE Sensor Size Configuration Register 31 30 29 28 27 26 25 24 23 15 14 13 12 11 10 9 8 7 CAM_CAMWIN 22 21 PIXELS R/W fffh 6 5 LINES R/W fffh 20 19 18 17 16 4 3 2 1 0 Total input pixel number Total input line number 412/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 CAM+0008h Bit Name Type Reset Bit Name Type Reset TG Grab Range Start/End Pixel Configuration Register CAM_GRABCOL 31 30 29 28 27 26 25 24 23 15 14 13 12 11 10 9 8 7 CAM+000Ch 30 29 28 27 26 25 24 23 15 14 13 12 11 10 9 8 7 18 17 16 4 3 2 1 0 22 21 START R/W 0 6 5 END R/W 0 CAM_GRABRO W 20 19 18 17 16 4 3 2 1 0 Grab start line number Grab end line number CAM+0010h Sensor Mode Configuration Register 31 30 29 28 27 26 25 24 15 14 13 12 11 10 9 8 Name Type Reset CAM+0018h 31 AV_S Name YNC_ SEL Type R/W Reset 0 Bit 15 23 CAM_CSMODE 22 21 7 6 5 VSPO HSPO PWR L L ON R/W R/W R/W 0 0 0 20 19 18 17 16 4 3 2 1 0 RST AUTO EN R/W 0 R/W 0 R/W 0 20 19 18 17 16 3 2 1 0 Sensor Vsync input polarity Sensor Hsync input polarity Auto lock sensor input horizontal pixel numbers enable Sensor process counter enable VSPOL HSPOL AUTO EN Bit 19 TG Grab Range Start/End Line Configuration Register 31 START END Bit Name Type Reset Bit 20 Grab start pixel number Grab end pixel number START END Bit Name Type Reset Bit Name Type Reset 22 21 START R/W 0 6 5 END R/W 0 30 View Finder Mode Control Register 29 28 27 26 25 24 23 CAM_VFCON 22 21 AV_SYNC_LINENO[11:0] R/W 0 14 13 12 11 10 9 8 413/599 7 6 5 4 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 Name SP_DELAY Type Reset R/W 0 AV_SYNC_SEL 0 1 AV_SYNC_LINENO SP_DELAY SP_MODE TAKE_PIC FR_CON 000 001 010 011 100 101 110 111 CAM+001Ch Bit 31 VSYN Name C_INT _SEL Type R/W Reset 0 Bit 15 R/W 0 Camera Module Interrupt Enable Register 30 29 28 27 26 25 14 13 12 11 10 9 Type Reset VSYNC_SEL 0 1 AV_SYNC_INT VSYNC_INT ISPDONE IDLE GMCOVRUN REZOVRUN EXPDO CAM+0020h 31 FR_CON Av_sync start point selection Start from AV_SYNC_LINENO Start from vsync Av_sync start point line counts Still Picture Mode delay Still Picture Mode Take Picture Request Frame Sampling Rate Control Every frame is sampled One frame is sampled every 2 frames One frame is sampled every 3 frames One frame is sampled every 4 frames One frame is sampled every 5 frames One frame is sampled every 6 frames One frame is sampled every 7 frames One frame is sampled every 8 frames Name Bit SP_M TAKE ODE _PIC R/W R/W 0 0 30 24 23 8 7 AV_S VSYN YNC_I C_INT NT R/W R/W 0 0 CAM_INTEN 22 21 20 19 18 17 16 6 5 4 3 2 1 0 ISPDO GMCO REZO EXPD IDLE NE VRUN VRUN O R/W 0 R/W 0 20 19 R/W 0 R/W 0 R/W 0 Vsync interrupt selection From Vsync Falling Edge From Vsync Rising Edge AV sync interrupt Vsync interrupt ISP done interrupt enable control Returning idle state interrupt enable control GMC port over run interrupt enable control Resizer over run interrupt enable control Exposure done interrupt enable control Camera Module Interrupt Status Register 29 28 27 26 25 24 414/599 23 22 CAM_INTSTA 21 18 17 16 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 Name Type Reset Bit 15 14 13 12 11 10 9 Name Type Reset CAM+0024h Bit Name 31 30 29 28 27 14 26 R/W 3 13 12 11 SWAP INDAT SWAP _CBC A_FO _Y R RMAT R/W 0 CNTON CNTMODE REZ_DISCONN REZ_LPF_OFF WRITE_LEVEL BAYER10_OUT OUTPATH_TYPE OUTPATH_EN SWAP_Y SWAP_CBCR INDATA_FORMAT INTYPE_SEL 25 WRITE_LEVEL R/W 0 Name Type Reset 6 5 4 3 2 R/W 0 R/W 0 R/W 0 10 9 1 0 ISPD GMCO REZO EXPD IDLE ONE VRUN VRUN O R 0 R 0 R 0 Camera Module Path Config Register CNTO CNTMODE N Type R/W Reset 0 Bit 15 8 7 AV_S VSYN YNC_I C_INT NT R/W R 0 0 R 0 R 0 CAM_PATH 24 23 22 21 20 BAYE REZ_ REZ_ OUTPATH_T R10_ DISC LPF_ YPE OUT ONN OFF R/W RW RW R/W 0 0 0 0 8 7 6 5 4 INTYPE_SEL INPATH_RATE R/W 1 R/W 0 19 18 3 2 17 16 OUTP ATH_ EN R/W 0 0 1 INPAT INPA H_TH TH_S ROTE EL N R/W R/W 0 0 Enable Debug Mode Data Transfer Counter Data Transfer Count Selection 00 sRGB count 01 YCbCr count Resizer disconnect enable Resizer low-Pass disable Write FIFO threshold level 10-bit Bayer Format output. Outpath type should be set to 00. Outpath Type Select 00 Bayer Format 01 ISP output 02 RGB888 Format 03 RGB565 Format Enable Output to Memory YCbCr in Swap Y YCbCr in Swap Cb Cr Sensor Input Data connection Input type selection 000 Bayer Format 001 YUV422 Format Default Input Format : UYVY 101 YCbCr422 Format 010 RGB Format 415/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 To enable YUV422/YCbCr422 input fast mode, refer to CAM + 011C bit 20 INPATH_RATE Input type rate control INPATH_THROTEN Input path throttle enable INPATH_SEL Input path selection 0 Sensor input 1 From memory CAM+0028h Bit Name Type Reset Bit Name Type Reset Camera Module Input Address Register 31 30 29 28 27 26 15 14 13 12 11 10 Bit Name Type Reset Bit Name Type Reset 30 29 28 27 26 15 14 13 12 11 10 19 18 17 16 5 4 3 2 1 0 25 24 23 22 CAM_OUTADDR[31:16] R/W 0 9 8 7 6 CAM_OUTADDR[15:0] R/W 0 CAM_OUTADDR 21 20 19 18 17 16 5 4 3 2 1 0 Output memory address CAM_OUTADDR Color Process Register Definition CAM+00B8h Bit Name Type Reset Bit 20 Camera Module Output Address Register 31 7.7.1.2 CAM_INADDR 21 Input memory address CAM_INADDR CAM+002Ch 25 24 23 22 CAM_INADDR[31:16] R/W 0 9 8 7 6 CAM_INADDR[15:0] R/W 0 31 15 SIGN_ BRIG Name HT_O FFSE T Type R/W Reset 1 Y Channel Configuration Register CAM_YCHAN 30 29 28 27 26 25 24 23 22 21 14 13 12 11 10 9 8 7 6 5 CONTRAST_GAIN SIGN_BRIGHT_OFFSET BRIGHT_OFFSET VSUP_EN UV_LP_EN 20 19 18 CONTRAST_GAIN R/W 40h 4 3 2 17 16 1 0 BRIGHT_OFFSET VSUP _EN UV_L P_EN CSUP_EDGE_GAIN R/W 0 R/W 0 R/W 0 R/W 10h Y channel contrast gain value Sign bit of Y channel brightness offset value Y channel brightness offset value Vertical Edge color suppression enable UV channel low pass enable 416/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 Chroma suppression edge gain value(1.3) CSUP_EDGE_GAIN CAM+00BCh Bit Name Type Reset Bit 31 30 UV Channel Configuration Register 29 14 13 25 24 23 22 21 20 12 11 10 9 8 7 SIGN_ V_OF FSET R/W 0 6 5 18 17 16 4 3 2 1 0 V_OFFSET R/W 0 Hue U channel operating value Hue V channel operating value Sign bit of Hue U channel offset value Hue U channel offset value Sign bit of Hue V channel offset value Hue V channel offset value Space Convert YUV Register 1 CAM_SCONV1 31 30 29 28 27 26 25 24 23 22 21 15 14 13 12 11 U_GAIN R/W 91h 10 9 8 7 6 5 20 19 Y_GAIN R/W FFh 4 3 V_GAIN R/W B8h 18 17 16 2 1 0 Space Convert Y channel gain value Space Convert U channel gain value Space Convert V channel gain value Y_GAIN U_GAIN V_GAIN CAM+00C4h Space Convert YUV Register 2 31 30 29 15 14 13 28 27 12 11 U_OFFSET R/W 80h CAM_SCONV2 26 25 24 23 22 21 10 9 8 7 6 5 22 21 20 19 Y_OFFSET R/W 01h 4 3 V_OFFSET R/W 80h 18 17 16 2 1 0 Space Convert Y channel offset value Space Convert U channel offset value Space Convert V channel offset value Y_OFFSET U_OFFSET V_OFFSET CAM+0128h 31 19 V22 R/W 20h R/W 0 CAM+00C0h Bit 26 U_OFFSET U11 V11 SIGN_U_OFFSET U_OFFSET SIGN_V_OFFSET V_OFFSET Bit Name Type Reset Bit Name Type Reset 27 U11 R/W 20h 15 SIGN_ Name U_OF FSET Type R/W Reset 0 Bit Name Type Reset Bit Name Type Reset 28 CAM_UVCHAN 30 Vertical Subsample Control Register 29 28 27 26 25 24 417/599 23 CAM_VSUB 20 19 18 17 16 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 Name Type Reset Bit Name Type Reset 15 14 13 CAM+012ch 31 15 30 14 CAM+0174h 31 29 13 15 30 14 RWIN_EN RWINV_START RWINV_END CAM+0178h Bit Name Type Reset Bit Name Type Reset 10 9 8 7 6 5 V_SUB_OUT R/W 0 4 3 2 1 0 28 H_SU B_EN R/W 0 12 27 26 25 24 23 CAM_HSUB 22 21 20 19 18 17 16 4 3 2 1 0 H_SUB_IN R/W 0 11 10 9 8 7 6 5 H_SUB_OUT R/W 0 Result Window Vertical Size Register 29 Name Type Reset Bit Name Type Reset 11 Horizontal sub-sample enable Source horizontal size Sub-sample horizontal size H_SUB_EN H_SUB_IN H_SUB_OUT Bit R/W 0 Horizontal Subsample Control Register Name Type Reset Bit Name Type Reset V_SUB_IN Vertical sub-sample enable Source vertical size Sub-sample vertical size V_SUB_EN V_SUB_IN V_SUB_OUT Bit V_SU B_EN R/W 0 12 13 28 RWIN _EN R/W 0h 12 27 26 25 24 22 21 20 19 18 17 16 4 3 2 1 0 RWINV_START R/W 0h 11 10 9 8 7 6 5 RWINV_END R/W 0h Result window enable Result window vertical start line Result window vertical end line Result Window Horizontal Size Register 31 30 29 28 27 26 25 24 15 14 13 12 11 10 9 8 RWINH_START 23 RWINV_SEL 23 22 21 20 RWINH_START R/W 0h 7 6 5 4 RWINH_END R/W 0h RWINH_SEL 19 18 17 16 3 2 1 0 Result window horizontal start pixel 418/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 Result window horizontal end pixel RWINH_END CAM+0180h Bit Name Type Reset Bit Name Type Reset 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 30 29 28 27 26 15 14 13 12 11 10 25 24 23 22 DST_ADD[31:16] R/W 4000h 9 8 7 6 DST_ADD[15:0] R/W 0000h CAM_DSTADDR 21 20 19 18 17 16 5 4 3 2 1 0 Debug Information Write Output Destination Address CAM+0188h Camera Module Debug Information Last Transfer Destination Address 31 30 29 28 27 26 15 14 13 12 11 10 25 24 23 22 LAST_ADD[31:16] R/W 0 9 8 7 6 LAST_ADD[15:0] R/W 0 CAM_LASTADD R 21 20 19 18 17 16 5 4 3 2 1 0 Debug Information Last Transfer Destination Address LAST_ADD CAM+018Ch Bit Name Type Reset Bit Name Type Reset Camera Module Debug Information Write Out Destination Address 31 DST_ADD Bit Name Type Reset Bit Name Type Reset CAM_DEBUG 31 CAM+0184h Bit Name Type Reset Bit Name Type Reset Camera Interface Debug Mode Control Register Camera Module Frame Buffer Transfer Out Count Register 31 30 29 28 27 26 15 14 13 12 11 10 XFER_COUNT 25 24 23 22 XFER_COUNT [31:16] RO 0 9 8 7 6 XFER_COUNT[15:0] RO 0 CAM_XFERCNT 21 20 19 18 17 16 5 4 3 2 1 0 Pixel Transfer Count per Frame 419/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 CAM+0190h Bit Name Type Reset Bit 31 30 15 14 Name Type Reset Sensor Test Model Configuration Register 1 29 28 27 VSYNC R/W 0 13 12 11 LINEC GRAY HG_E _LEV EL N R/W R/W 0 0 VSYNC IDLE_PIXEL_PER_LINE LINECHG_EN GRAY_LEVEL ON RST STILL PATTERN PIXEL_SEL CLK_DIV CAM +0194h Bit Name Type Reset Bit Name Type Reset 24 23 22 10 9 8 7 6 ON RST STILL R/W 0 R/W 0 R/W 0 21 20 19 18 IDLE_PIXEL_PER_LINE R/W 0 5 4 3 2 PATT PIXEL_SEL ERN R/W 0 17 16 1 0 CLK_DIV R/W 0 R/W 0 VSYNC high duration in line unit(IDLE_PIXEL_PER_LINE + PIXEL) HSYNC low duration in pixel unit Pattern 0 2 lines change mode enable Sensor Model Gray Level Enable. When gray level is enable, increased gray level pattern will be generated. Enable Sensor Model. Reset Sensor Model Still picture Mode Sensor Model Test Pattern Selection Sensor Model output pixel selection. 00 All pixels 01 01 pixel 10 10 pixel 11 00 and 11 pixels Pixel_Clock/System_Clock Ratio 31 30 29 28 27 26 25 24 23 22 15 14 13 12 11 10 9 8 7 6 21 LINE R/W 0 5 PIXEL R/W 0 CAM_MDLCFG2 20 19 18 17 16 4 3 2 1 0 Sensor Model Line Number Sensor Model Pixel Number (HSYNC high duration in pixel unit) CAM +01D8h Name 25 Sensor Test Model Configuration Register 2 LINE PIXEL Bit Name Type Reset Bit 26 CAM_MDLCFG1 CAM RESET Register CAM_RESET 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 TG_STATUS R 15 14 13 12 11 10 9 8 7 6 5 4 3 ISP_FRAME_COUNT[7:0] 420/599 2 1 16 0 ISP_ RES ET MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 Type Reset RW 0 ISP_FRAME_COUNT ISP_RESET RW 0 ISP frame counter ISP reset CAM +01DCh TG STATUS Register Bit 31 30 29 Name Type Reset Bit Name Type Reset 15 14 13 28 SYN_ VFON R 27 12 11 26 TG_STATUS 25 24 10 9 8 CAM +0248h CAM GMC DEBUG Register 20 19 18 17 16 7 6 5 4 PIXEL_COUNT[11:0] R 3 2 1 0 CAM_DEBUG 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 22 21 20 19 6 5 CAM +0274h YEAR MONTH DATE 21 R TG view finder status TG line counter TG pixel counter Bit Name Type Reset Bit Name Type Reset 22 LINE_COUNT[11:0] SYN_VFON LINE_COUNT PIXEL_COUNT Bit Name Type Reset Bit Name Type Reset 23 CAM VERSION Register 31 30 29 15 14 13 28 27 12 11 MONTH[15:0] R 26 25 10 9 CAM_VERSION 24 23 YEAR[16:0] R 8 7 4 3 DATE[15:0] R 18 17 16 2 1 0 Year ASCII Month ASCII Date ASCII 421/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 8 8.1 Audio Front-End General Description The audio front-end essentially consists of voice and audio data paths. Figure 59 shows the block diagram of the audio front-end. All voice band data paths comply with the GSM 03.50 specification. Mono hands-free audio or external FM radio playback paths are also provided. The audio stereo path facilitates CD-quality playback, external FM radio, and voice playback through a headset. MUX Audio Amp-L Audio LCH-DAC AU_MOUTR MUX Audio Signal AU_MOUTL Audio RCH-DAC Audio Amp-R AU_FMINL FM/AM radio chip Stereoto-Mono Voice Signal AU_FMINR Voice DAC Voice Amp-1 AU_OUT0_P AU_OUT0_N AU_VIN0_P PGA Voice ADC MUX Voice Signal AU_VIN0_N AU_VIN1_N AU_VIN1_P Figure 59 Block diagram of audio front-end Figure 60 shows the digital circuits block diagram of the audio front-end. The APB register block is an APB peripheral that stores settings from the MCU. The DSP audio port (DAP) block interfaces with the DSP for control and data communications. The digital filter block performs filter operations for voice band and audio band signal processing. The Digital Audio Interface (DAI) block communicates with the System Simulator for FTA or external Bluetooth modules. 422/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 Figure 60 Block diagram of digital circuits of the audio front-end To communicate with the external Bluetooth module, the master-mode PCM interface and master-mode I2S/EIAJ interface are supported. The clock of PCM interface is 256 kHz while the frame sync is 8 kHz. Both long sync and short sync interfaces are supported. The PCM interface can transmit 16-bit stereo or 32-bit mono 8 kHz sampling rate voice signal. Figure 61 shows the timing diagram of the PCM interface. Note that the serial data changes when the clock is rising and is latched when the clock is falling. 423/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 dai_clk bt_sync(s) bt_sync(l) dai_tx 3 2 1 0 31 30 29 28 27 26 25 24 23 22 dai_rx 3 2 1 0 31 30 29 28 27 26 25 24 23 22 Figure 61 Timing diagram of Bluetooth application I2S/EIAJ interface is designed to transmit high quality audio data. Figure 62 and Figure 63 EDI Format 2: I2S (FMT = 1). illustrate the timing diagram of the two types of interfaces. I2S/EIAJ can support 32 kHz, 44.1 kHz, and 48 kHz sampling rate audio signals. The clock frequency of I2S/EIAJ can be 32×(sampling frequency), or 64×(sampling frequency). For example, to transmit a 44.1 kHz CD-quality music, the clock frequency should be 32 × 44.1 kHz = 1.4112 MHz or 64 × 44.1 kHz = 2.8224 MHz. I2S/EIAJ interface is not only used for Bluetooth module, but also for external DAC components. be sent to the external DAC through the I2S/EIAJ interface. Audio data can easily In this document, the I2S/EIAJ interface is referred to as EDI (External DAC Interface). EDI_CLK EDI_WS EDI_DAT Left Channel 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 Right Channel 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 7 6 5 4 3 2 1 0 15 14 13 Figure 62 EDI Format 1: EIAJ (FMT = 0). EDI_CLK EDI_WS EDI_DAT Left Channel 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 Right Channel 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 Figure 63 EDI Format 2: I2S (FMT = 1). 8.1.1 DAI, PCM and EDI Pin Sharing DAI, PCM, and EDI interfaces share the same pins. The pin mapping is listed in Table 40. PIN NAME DAI PCM EDI DAI_CLK (OUTPUT) DAI_CLK PCM_CLK EDI_CLK DAI_TX (OUTPUT) DAI_TX PCM_OUT EDI_DAT DAI_RX (INPUT) DAI_RX PCM_IN 424/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 BT_SYNC (OUTPUT) - PCM_SYNC EDI_WS Table 40 Pin mapping of DAI, PCM, and EDI interfaces. Beside the shared pins, the EDI interface can also use other dedicated pins. interfaces can operate at the same time. With the dedicated pins, PCM and EDI Dedicated Shared Pins Pins EDI 32k 44.1k 48k DSP IO BUS PCM DAI EQ 16X upsampling / 1st Order SRC 8X upsampling 1X Fs 8X Fs SDM D/A 6.5MHz Figure 64 DAI, PCM, EDI interfaces 8.2 Register Definitions MCU APB bus registers in audio front-end are listed as follows. 0x820F0000 Bit 15 14 AFE_VMCU_CO N0 AFE Voice MCU Control Register 13 12 11 10 9 8 7 6 5 4 3 2 1 Name Type Reset 0 VAFE ON R/W 0 MCU sets this register to start AFE voice operation. A synchronous reset signal is issued, then periodical interrupts of 8-KHz frequency are issued. Clearing this register stops the interrupt generation. VAFEON 0 1 Turn on voice front-end operations. off on 0x820F000C Bit 15 14 AFE_VMCU_CO N1 AFE Voice Analog-Circuit Control Register 1 13 12 11 10 9 8 425/599 7 6 5 4 3 2 1 0 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 VDLDI VAFE VRSD VDL_IIRMOD VUL_IIRMOD VDLDITH_VA VMOD TH_O CLR_ ON E E L E4K N EN R/W R/W R/W R/W R/W R/W R/W 0 0 0 00 00 00 0 Name Type Reset Set this register for consistency of analog circuit setting. Suggested value is 80h. VMODE4K DSP data mode selection 0 8k mode 1 4k mode VAFECLR_EN Enable signal to reset voice downlink buffer or not while VAFE is powered down. 0 NO reset voice downlink buffer while VAFE is powered down 1 Reset voice downlink buffer while VAFE is powered down VRSDON Turn on the voice-band redundant signed digit function. 0 1-bit 2-level mode 1 2-bit 3-level mode VDL_IIRMODE Voice downlink IIR coefficients set selection 00 4k : 90Hz, 8k: 180Hz. 01 4k : 160Hz, 8k: 320Hz. 10 4k : 200Hz, 8k: 400Hz 11 4k : 320Hz, 8k: 640Hz VUL_IIRMODE Voice uplink IIR coefficients set selection 00 4k : 90Hz, 8k: 180Hz. 01 4k : 160Hz, 8k: 320Hz. 10 4k : 200Hz, 8k: 400Hz 11 4k : 320Hz, 8k: 640Hz VDITHVAL Voice downlink dither scaling setting 00 1 01 2 10 4 11 8 VDITHON Turn on the voice downlink dither function. 0 Turn off 1 Turn on 0x820F0014 Bit 15 14 AFE Voice DAI Bluetooth Control Register 13 12 11 10 9 8 Name Type Reset AFE_VDB_CON 7 6 5 4 3 VDAI BT_C EDIO VDAI VBTO VBTS N ON N YNC LR_E N R/W RW R/W R/W R/W 0 0 0 0 0 2 1 0 VBTSLEN R/W 000 Set this register for DAI test mode and Bluetooth application. DAIBT_CLR_EN Enable signal to reset DAIBT buffer or not while VAFE is powered down. 426/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 0 NO reset DAIBT buffer while VAFE is powered down 1 Reset DAIBT buffer while VAFE is powered down EDION EDI signals are selected as the output of DAI, PCM, EDI shared interface. 0 EDI is not selected. A dedicated EDI interface can be enabled by programming the GPIO selection. refer to GPIO section for details. 1 EDI is selected. VDAION and VBTON are not set. VDAION Turn on the DAI function. 0 1 VBTON Please off on Turn on the Bluetooth PCM function. 0 off 1 on VBTSYNCBluetooth PCM frame sync type 0: short 1: long VBTSLEN Bluetooth PCM long frame sync length = VBTSLEN+1 0x820F0018 Bit 15 14 AFE Voice Look-Back mode Control Register 13 12 11 10 9 8 Name Type Reset 7 6 AFE_VLB_CON 5 4 3 2 1 0 VDSP VDSP VBYP VDAPI VINTI VDEC BYPA CSMO ASSII NMOD NMOD INMO DE E E R DE SS R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 Set this register for AFE voice digital circuit configuration control. Several loop back modes are implemented for test purposes. Default values correspond to the normal function mode. VDSPBYPASS Loopback data won’t be gated by VDSPRDY. 0 Normal Mode 1 Bypass DSP loopback mode VDSPCSMODE DSP COSIM only, to align DATA. 0 Normal mode 1 DSP COSIM mode VBYPASSIIR Bypass IIR filter 0 Normal mode 1 Bypass VDAPINMODE DSP audio port input mode control 0 Normal mode 1 Loop back mode VINTINMODE interpolator input mode control 427/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 0 Normal mode 1 Loop back mode VDECINMODE decimator input mode control 0 Normal mode 1 Loop back mode 0x820F0020 Bit 15 14 AFE Audio MCU Control Register 0 13 12 11 10 9 8 7 AFE_AMCU_CON0 6 5 4 3 2 1 Name Type Reset 0 AAFE ON R/W 0 MCU sets this register to start AFE audio operation. A synchronous reset signal is issued, and then periodical interrupts of 1/6 sampling frequency are issued. Clearing this register stops the interrupt generation. AAFEON 0 1 Turn on audio front-end operations. off on 0x820F0024 Bit 15 14 ASDM Name CK_P MONO HASE Type R/W R/W Reset 0 0 AFE Audio Control Register 1 13 12 11 10 9 AFE_AMCU_CON1 8 7 6 5 4 SEL_I DWA BYPASS SDM_ MODE GAIN ARAMPSP R/W 1 RW 00 R/W 0 R/W 0 R/W 00 3 2 AMUT AMUT ER EL R/W 0 R/W 0 1 0 AFS R/W 00 MCU sets this register to inform hardware of the sampling frequency of audio being played back. ASDMCK_PHASE Phase of Audio SDM Clock. Please set to 0. SEL_IDWA IDWA function selection. 0 Disable IDWA 1 Enable IDWA MONO Mono mode select. AFE HW will do (left + right) / 2 operation to the audio sample pair. Thus both right/left channels DAC will have the same inputs. 0 Disable mono mode. 1 Enable mono mode. BYPASS To bypass part of the audio hardware path. Bit 1 please always set to 1 to bypass Interpolation. 00 No bypass. The input data rate is 1/4 sampling frequency. For example, if the sampling frequency is 32 KHz, then the input data rate is 8 KHz. 01 Bypass the first stage of interpolation. The input data rate is 1/2 the sampling frequency. 10 Bypass two stages of interpolation. The input data rate is the same as the sampling frequency. 11 Bypass two stages of interpolation and EQ filter. The input data rate is the same as the sampling frequency. 428/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 EDI 32k 44.1k 48k DSP IO BUS EQ 16X upsampling / 1st Order SRC 8X upsampling 1X Fs 8X Fs SDM D/A 6.5MHz Figure 65 Block diagram of the audio path. SDM_MODE SDM mode control 0 zero extension. 1 sign extension. GAIN Gain Setting at Audio SDM input, Please set to 1. 0 1X 1 1/2X ramp up/down speed selection ARAMPSP 00 8, 4096/AFS 01 16, 2048/AFS 10 24, 1024/AFS 11 32, 512/AFS AMUTER Mute the audio R-channel, with a soft ramp up/down. 0 no mute 1 mute AMUTEL Mute the audio L-channel, with a soft ramp up/down. 0 no mute 1 mute AFS Sampling frequency setting. 00 01 10 11 32-KHz 44.1-KHz 48-KHz reserved 0x820F0028 Bit Name Type Reset 15 14 AFE EDI Control Register 13 12 11 10 9 AFE_EDI_CON 8 DIR R/W 0 7 SRC R/W 0 6 5 4 3 WCYCLE R/W 01111 2 1 FMT R/W 0 0 EN R/W 0 This register is used to control the EDI 429/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 Enable EDI. When EDI is disabled, EDI_DAT and EDI_WS hold low. 0 disable EDI 1 enable EDI FMT EDI format 0 EIAJ 1 I2S WCYCLE Clock cycle count in a word. Cycle count = WCYCLE + 1, and WCYCLE can be 15 or 31 only. Any other values result in an unpredictable error. 15 Cycle count is 16. 31 Cycle count is 32. SRC I2S clock and WS signal source. 0 Internal mode. The clock and word select signals are fed to external device from AFE. 1 External mode. The clock and word select signals are fed externally from the connected device. There is a buffer control mechanism to deal with the clock mismatch between internal and external clocks. DIR Serial data bit direction 0 Output mode. Audio data is fed out to the external device. 1 Input mode or recording mode. By this recording mechanism, DSP can do some post processing or voice memos. EN 16 cycles 16 cycles Left Channel Right Channel EDI_CLK EDI_WS EDI_DAT 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 Figure 66 Cycle count is 16 for I2S format. 32 cycles 32 cycles Left Channel Right Channel EDI_CLK EDI_WS EDI_DAT 6 5 4 3 2 1 0 15 14 13 12 2 1 0 15 14 13 12 2 1 0 15 14 13 Figure 67 Cycle count is 32 for I2S format. 0x820F0030 Bit 15 Name VON Type R/W Reset 0 Audio/Voice DAC SineWave Generator 14 13 AON MUTE R/W R/W 0 0 12 11 10 9 8 AMP_DIV R/W 111 7 6 AFE_DAC_TEST 5 4 3 FREQ_DIV R/W 0000_0001 2 1 0 This register is only for analog design verification on audio/voice DACs. VON Makes voice DAC output the test sine wave. 0 Voice DAC inputs are normal voice samples 1 Voice DAC inputs are sine waves 430/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 AON Makes audio DAC output the test sine wave. 0 Audio DAC inputs are normal audio samples 1 Audio DAC inputs are sine waves MUTE Mute switch. 0 Turn on the sine wave output in this test mode. 1 Mute the sine wave output. AMP_DIV Amplitude setting. 111 full scale 110 1/2 full scale 101 1/4 full scale 100 1/8 full scale FREQ_DIV Frequency setting, 1 hot. 0000_0001 0000_0010 0000_0100 0000_1000 0001_0000 0010_0000 0100_0000 1000_0000 0x820F0034 Bit 15 Name A2V Type R/W Reset 0 14 1X frequency 2X frequency 3X frequency 4X frequency 8X frequency 16X frequency 32X frequency 64X frequency Audio/Voice Interactive Mode Setting 13 12 11 10 9 8 7 AFE_VAM_SET 6 5 4 3 2 1 0 PER_VAL R/W 101 Redirect audio interrupt to voice interrupt. In other words, replace voice interrupt by audio interrupt. 0 [voice interrupt / audio interrupt] Æ [voice / audio] 1 [audio interrupt / no interrupt] Æ [voice / audio] PER_VAL Counter reset value for audio interrupt generation period setting. For example, by default, the setting = 5 causes interrupt per 6 L/R samples. Changing this value can change the rate of audio interrupt. A2V 0x820F0040~ 0x820F00F0 Bit Name Type 15 14 AFE Audio Equalizer Filter Coefficient Register 13 12 11 10 9 8 7 6 5 AFE_EQCOEF 4 3 2 1 0 A WO Audio front-end provides a 45-tap equalizer filter. The filter is shown below. DO = (A44 X DI44 + A43 X DI43 … + A1 X DI1 + A0 X DI0)/32768. DIn is the input data, and An is the coefficient of the filter, which is a 16-bit 2’s complement signed integer. DI0 is the last input data. 431/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 The coefficient cannot be programmed when the audio path is enabled, or unpredictable noise may be generated. If coefficient programming is necessary while the audio path is enabled, the audio path must be muted during programming. After programming is complete, the audio path is not to be resumed (unmated) for 100 sampling periods. A Coefficient of the filter. Address Coefficient 0x820f0040 0x820f0044 0x820f0048 0x820f004C 0x820f0050 0x820f0054 0x820f0058 0x820f005C 0x820f0060 0x820f0064 0x820f0068 0x820f006C 0x820f0070 0x820f0074 0x820f0078 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 0x820F0100 Bit 15 14 Address Coefficient Address Coefficient A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 0x820f00B8 0x820f00BC 0x820f00C0 0x820f00C4 0x820f00C8 0x820f00CC 0x820f00D0 0x820f00D4 0x820f00D8 0x820f00DC 0x820f00E0 0x820f00E4 0x820f00E8 0x820f00EC 0x820f00F0 A30 A31 A32 A33 A34 A35 A36 A37 A38 A39 A40 A41 A42 A43 A44 0x820f007C 0x820f0080 0x820f0084 0x820f0088 0x820f008C 0x820f0090 0x820f0094 0x820f0098 0x820f009C 0x820f00A0 0x820f00A4 0x820f00A8 0x820f00Ac 0x820f00B0 0x820f00B4 Table 41 AFE AGC Control Register 0 13 12 11 10 9 8 AFE_VAGC_CON0 7 6 Name MINPGAGAIN PGAGAIN Type Reset R/W 001010 R/W 101000 5 4 3 2 1 0 FRFL RATK SATK AGCO G FLG FLG N R/W R/W R/W R/W 0 1 1 1 This register sets the control signals for AGC. AGCON Switch of the AGC 0 Off 1 On SATKFLG Sample Attack Flag 0 off 1 on RATKFLG RMS Attack Flag 0 off 1 on FRFLG Free Release Flag 0 off 1 on PGAGAIN PGA gain settings (from -43dB to 20 dB), it is also the maximum PGA gain settings while AGC is on. 432/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 000000 000001 | -43dB -42dB 111110 111111 19dB 20dB MINPGAGAIN minima PGA gain settings (from -43 to 20 dB). PGA gain is always larger than MINPGAGAIN. 000000 -43dB 000001 -42dB | 111110 111111 0x820F0104 Bit Name Type Reset 15 14 19dB 20dB AFE AGC Control Register 1 13 12 VAGC VSDM VAGC _CTR _GAIN _SEL L R/W R/W R/W 0 1 0 11 10 9 8 AFE_VAGC_CON1 7 6 5 4 3 2 1 ECNTRRLZS ECNTRRLZF ECNTRATK R/W 1100 R/W 1100 R/W 1000 0 This register sets the control signals for AGC and VSDM. VSDM_GAIN Input gain before Voice SDM 0 1/2 X 1 1X VAGC_SEL Selection of AGC output. 0 bypass AGC. 1 AGC compensation on. VAGC_CTRL Selection the AGC gain control master. 0 Control by AFE. 1 Control by DSP. ECNTRATK Attack counter, control attack speed.(unit: N samples@52kHz ). Attach will be triggered if N samples amplitude exceed attack threshold (ENTHDATK) 0 always attack, please don’t set to this values. 1~15 N=1~15 ECNTRRLZF Fast release counter, control fast release speed.(unit: N samples@52kHz ). Release will be triggered if N samples amplitude lower than slow release threshold (ENTHDRLS) 0 1 1 3 2 7 3 15 433/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 4 5 6 7 8 9 10 11 12 13 14 15 31 63 127 255 511 1023 2043 4095 8191 16383 32767 65535 ECNTRRLZS Slow release counter, control slow release speed.(unit: N samples@52kHz ). Release will be triggered if N samples amplitude lower than hysteresis threshold (ENTHDHYS) 0 1 1 3 2 7 3 15 4 31 5 63 6 127 7 255 8 511 9 1023 10 2043 11 4095 12 8191 13 16383 14 32767 15 65535 0x820F0108 Bit Name Type Reset 15 AFE AGC Control Register 2 14 13 12 ERMSFBATTF R/W 1010 11 10 9 ERMSFBATTR R/W 0100 8 AFE_VAGC_CON2 7 6 5 ERMSFBF R/W 1011 4 3 2 1 ERMSFBR R/W 0101 0 This register sets the control signals for AGC. ERMSFBR RMS rising factor. The larger the number; the slower the signal energy estimation. 0 1x RMS power estimation. 1 2x RMS power estimation. 2 4x RMS power estimation. 434/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 3 8x RMS power estimation. | 14 16384x RMS power estimation. 15 32768x RMS power estimation. ERMSFBF 0 1 2 3 RMS falling factor. The larger the number; the slower the signal energy estimation. 1x RMS power estimation. 2x RMS power estimation. 4x RMS power estimation. 8x RMS power estimation. | 14 16384x RMS power estimation. 15 32768x RMS power estimation. ERMSFBATTR RMS for Attack rising factor. The larger the number; the slower the signal energy estimation. 0 1x RMS power estimation. 1 2x RMS power estimation. 2 4x RMS power estimation. 3 8x RMS power estimation. | 14 16384x RMS power estimation. 15 32768x RMS power estimation. ERMSFBATTF RMS for Attack falling factor. The larger the number; the slower the signal energy estimation. 0 1x RMS power estimation. 1 2x RMS power estimation. 2 4x RMS power estimation. 3 8x RMS power estimation. | 14 16384x RMS power estimation. 15 32768x RMS power estimation. 0x820F010C Bit 15 14 AFE AGC Control Register 3 13 12 11 10 9 8 AFE_VAGC_CON3 7 6 5 4 3 2 1 0 EGAINCOMP_FC_T EGAINCOMP EGAINCOMP Name EGAINCOMP_CSS EGAINCOMP_CSM EGAINCOMP_CSF HD _LOWER _UPPER Type R/W R/W R/W R/W R/W R/W Reset 001 011 011 101 01 01 This register sets the control signals for AGC. 435/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 Figure 68 Gain Compensation procedures. EGAINCOMP_UPPER procedures.) 00 33095 01 33423 10 33751 11 34078 Gain compensation upper threshold, 32768 = 0dB (Figure 68 Gain Compensation EGAINCOMP_LOWER procedures.) 00 32440 01 32112 10 31784 11 31457 Gain compensation lower threshold, 32768 = 0dB (Figure 68 Gain Compensation EGAINCOMP_FC_THD 000 34406 001 36044 010 37683 011 39321 100 40960 101 42598 110 44236 111 45875 Gain compensation convergence threshold (Figure 68 Gain Compensation procedures.). EGAINCOMP_FC_CSF Gain compensation fast converge speed. (While compensation gain is 0.3dB far from 32768, the convergence speed is fast) 000 31948 (8X) 001 31129 (7X) 010 30310 (6X) 011 29491 (5X) 436/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 100 28672 (4X) 101 27852 (3X) 110 27033 (2X) 111 26214 (1X) EGAINCOMP_FC_CSM Gain compensation converge speed middle. (While compensation gain is 0.15dB ~ 0.3dB from 32768, the convergence speed is middle) 000 32686 (8X) 001 32604 (7X) 010 32552 (6X) 011 32440 (5X) 100 32358 (4X) 101 32276 (3X) 110 32194 (2X) 111 32112 (1X) EGAINCOMP_FC_CSS Gain compensation converge speed slow. (While compensation gain is inside 0.15dB from 32768, the convergence speed is slow) 000 32751 (8X) 001 32735 (7X) 010 32718 (6X) 011 32702 (5X) 100 32686 (4X) 101 32669 (3X) 110 32653 (2X) 111 32636 (1X) 0x820F0110 Bit Name Type Reset 15 14 AFE AGC Control Register 4 13 12 11 ENTHDATKRMS R/W 000100 10 9 8 AFE_VAGC_CON4 7 6 ENTHDATK R/W 000001 5 4 3 2 1 0 ESRELWINWIDTH1 R/W 1000 This register sets the control signals for AGC. ESRELWINWIDTH1 speech release window width for strong VAD 0 10 @ 52kHz samples 1 20 @ 52kHz samples 2 40 @ 52kHz samples 3 80 @ 52kHz samples 4 160 @ 52kHz samples 5 325 @ 52kHz samples 6 650 @ 52kHz samples 7 1300 @ 52kHz samples 437/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 8 9 10 11 12 13 14 15 2600 @ 52kHz samples 5200 @ 52kHz samples 10000 @ 52kHz samples 15000 @ 52kHz samples 20000 @ 52kHz samples 25000 @ 52kHz samples 30000 @ 52kHz samples 32767 @ 52kHz samples ENTHDATK Attack threshold [0~63] is map to [-63~0]dB FS ENTHDATKRMS RMS attack threshold [0~63] is map to [-63~0]dB FS 0x820F0114 Bit Name Type Reset 15 14 AFE AGC Control Register 5 13 12 ENTHDRLS R/W 001101 11 10 9 8 AFE_VAGC_CON5 7 6 ENTHDHYS R/W 000111 5 4 3 2 1 0 ESRELWINWIDTH2 R/W 1000 This register sets the control signals for AGC. ESRELWINWIDTH2 speech release window width for weak VAD 0 10 @ 52kHz samples 1 20 @ 52kHz samples 2 40 @ 52kHz samples 3 80 @ 52kHz samples 4 160 @ 52kHz samples 5 325 @ 52kHz samples 6 650 @ 52kHz samples 7 1300 @ 52kHz samples 8 2600 @ 52kHz samples 9 5200 @ 52kHz samples 10 10000 @ 52kHz samples 11 15000 @ 52kHz samples 12 20000 @ 52kHz samples 13 25000 @ 52kHz samples 14 30000 @ 52kHz samples 15 32767 @ 52kHz samples ENTHDHYS Hysteresis threshold [0~63] is map to [-63~0]dB FS ENTHDRLS Slow release threshold 438/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 [0~63] is map to [-63~0]dB FS 0x820F0118 Bit 15 AFE AGC Control Register 6 14 13 12 11 10 9 Name EPATTLIMITER PATTRELD Type Reset R/W 0100 R/W 0000 8 AFE_VAGC_CON6 7 6 PATT NATK RELF FLG LG R/W R/W 1 1 5 4 3 2 1 0 ENTHDNOZ R/W 111101 This register sets the control signals for AGC. ENTHDNOZ Idle threshold [0~63] is map to [-63~0]dB FS PATTRELFLG post attack/release flag 0 off 1 on NATKFLG noise adaptive attenuation enable attack flag 0 off 1 on PATTRELD Post attack/release latency 0~15 is map to 0~15 sample @260kHz sampling rate EPATTLIMITER Post attack limiter [0,15] is map to [0,-7.5dBFs], the spacing is 0.5dB 8.3 DSP Register Definitions 0x640 Bit Name Type Reset AFE Voice Uplink Data Register 0 15 14 13 12 11 10 9 8 7 VUL_DAT0 RO 0 AFE_VUL_DAT0 6 5 4 3 2 1 0 Voice band uplink transmission data register 0. The content of this register is updated by uplink digital filter outputs. This register is read by DSP in an 8K ISR. 0x641 Bit Name Type Reset AFE Voice Uplink Data Register 1 15 14 13 12 11 10 9 8 7 VUL_DAT1 RO 0 439/599 AFE_VUL_DAT1 6 5 4 3 2 1 0 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 Voice band uplink transmission data register 1. The content of this register is updated by uplink digital filter outputs. This register is read by DSP in an 8K ISR if VBYPASSIIR of AFE_LB_CON is set. 0x642 Bit Name Type Reset AFE Voice Downlink Data Register 0 15 14 13 12 11 10 Voice band downlink receiving data register 0. is used as downlink digital filter inputs. 0x643 Bit Name Type Reset 9 8 7 VDL_DAT0 WO 0 AFE_VDL_DAT0 6 5 4 3 14 13 12 11 10 1 0 This register is written by DSP in an 8K ISR. The content of this register AFE Voice Downlink Data Register 1 15 2 9 8 7 VDL_DAT1 WO 0 AFE_VDL_DAT1 6 5 4 3 2 1 0 Voice band downlink receiving data register 1. This register is written by DSP in an 8K ISR if VBYPASSIIR of AFE_VLB_CON is set. The content of this register is used as downlink digital filter inputs. AFE Voice DAI Bluetooth Transmission Data Register AFE_VDBTX_DA 0 T0 0x644 Bit Name Type Reset 15 14 13 12 11 10 9 8 7 VDBTX_DAT0 WO 0 6 5 4 3 2 1 0 DAI Bluetooth transmission data register 0. This register is written by DSP in an 8K ISR if the Bluetooth function is turned on. The content of this register is shifted out to the Bluetooth interface. AFE Voice DAI Bluetooth Transmission Data Register AFE_VDBTX_DA 1 T1 0x645 Bit Name Type Reset 15 14 13 12 11 10 9 8 7 VDBTX_DAT 1 WO 0 6 5 4 3 2 1 0 DAI Bluetooth transmission data register 1. This register is written by DSP in an 8K ISR if the corresponding DAI test is set or the Bluetooth function is turned on. The content of this register is shifted out to the SS or Bluetooth interface. 0x646 Bit Name Type Reset AFE_VDBRX_D AT0 AFE Voice DAI Bluetooth Receiving Data Register 0 15 14 13 12 11 10 9 8 7 VDBRX_DAT 0 RO 0 440/599 6 5 4 3 2 1 0 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 DAI Bluetooth receiving data register 0. This register is read by DSP in an 8K ISR if the Bluetooth function is turned on. The content of this register is shifted in from the Bluetooth interface. 0x647 Bit Name Type Reset AFE_VDBRX_DA T1 AFE Voice DAI Bluetooth Receiving Data Register 1 15 14 13 12 11 10 9 8 7 VDBRX_DAT 1 RO 0 6 5 4 3 2 1 0 DAI Bluetooth receiving data register 1. This register is read by DSP in an 8K ISR if the corresponding DAI test is set or the Bluetooth function is turned on. The content of this register is shifted in from the SS or Bluetooth module. 0x648 Bit AFE Voice DAI Bluetooth Control Register 15 14 13 12 11 10 9 8 7 6 AFE_VDSP_CON 5 4 3 2 1 Name Type Reset 0 VDSP _RDY R/W 0 DSP sets this register to inform hardware that it is ready for data transmission. In DAI test modes, DSP starts a test by setting vdsp_rdy when speech samples are required or are ready. In normal mode, the DSP asserts this bit to ungate the downlink path data. Otherwise, the downlink data remains zero. VDSP_RDY 0 1 Ready indication to start the voice band data path. DSP data is not ready. DSP data is ready. 0x649 Bit Name Type Reset AFE I2S Input Mode Buffer 15 14 13 12 11 10 9 AFE_EDI_RDATA 8 7 RDATA RO 0 6 5 4 3 2 1 0 This is the register for reading I2S input data. For each audio interrupt, DSP should read 6 pairs (total 12 reads) of the input data. If DSP is reading too fast or too slow, there is a 2-word margin for repeating or dropping the samples that DSP read rate can not match-up with audio front end. Read data port. Left channel first, and then right channel. DATA 0x64A Bit AFE AGC DSP Control 15 14 13 12 11 10 AEF_VAGC_VAD 9 8 7 6 5 4 Name NADPATT_DBGAIN Type Reset R/W 000000 3 2 1 0 NGAT EOPE VAD2 VAD N R/W R/W R/W 0 0 0 This register is for DSP to read/write the parameter of AGC. 441/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 Strong VAD flag 0 off 1 on VAD2 Weak VAD flag 0 off 1 on NGATEOPEN noise gate flag 0 noise gate close 1 noise gate open NADPATT_DBGAIN noise adaptive attenuation DB gain [0,63] 0~63dB VAD 0x64B Bit AFE AGC DSP Control 15 14 13 12 11 10 AEF_VAGC_CNTR 9 8 7 Name CNTR_REL_FF Type Reset R/W 000000000000000 6 5 4 3 2 1 0 TONE FLG R/W 0 This register is for DSP to read/write the parameter of AGC. TONEFLG Tone flag 0 off 1 on CNTR_REL_FF Proceed very fast release if N samples value smaller than the fast release threshold 0~32767 N=0~32767 @ 52kHz sampling rate. 0x64C Bit Name Type Reset AFE AGC DSP Control1 15 14 13 12 11 NCNTRRLZ RO 0000_0000 10 9 AEF_VAGC_CNTR1 8 7 6 5 4 3 NCNTRATK RO 0000_0000 2 1 0 This register is for DSP to read the parameter of AGC. NCNTRRLZ Release counter (in unit of 52kHz/256 sampling rate). NCNTRATK Attack counter (in unit of 52kHz/16 sampling rate). 0x64D Bit Name Type Reset AFE AGC DSP Control 15 14 13 12 11 10 AEF_VAGC_STETE 9 8 442/599 7 6 SSTATE RO 00 5 4 3 2 FGAINDB RO 000000 1 0 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 This register is for DSP to read the parameter of AGC. FGAINDB Current PGA gain (from 0 to 63 dB). SSTATE Current AGC state. 0x64E Bit Name Type Reset AFE AGC DSP Control 15 14 13 12 11 SIGRMSATT RO 00000000 10 AEF_VAGC_RMS 9 8 7 6 5 4 3 SIGRMS RO 00000000 2 1 0 This register is for DSP to read the parameter of AGC. SIGRMS SIGRMSATT RMS of signal RMS of signal for attack usage 0x64F Bit AFE Audio Control Register 15 14 13 12 11 10 9 8 AFE_ADSP_CON 7 6 5 4 3 2 Name Type Reset DSP sets this register to inform hardware that it is ready for data transmission. path data. Otherwise, the audio path data remains zero. ADSP_RDY Ready to ungate audio data path. ARST_FIFO Reset the FIFO read/write pointers and the interrupt counter. 0x650 Bit Name Type Reset DSP asserts this bit to ungate the audio AFE_ARCH_DA T0 AFE Audio Right-Channel Data Register 0 15 14 13 12 11 10 9 8 7 ARCH_DAT0 W 0 6 1 0 ARST ADSP _FIFO _RDY R/W R/W 0 0 5 4 3 2 1 0 Audio right channel data register 0. The content of this register is used as the right channel digital filter inputs. The frequency of audio interrupts varies with the audio sampling rate and bypass setting, and can be 1/6 the audio sampling rate, or 1/12 the sampling rate, or 1/24 the sampling rate. The frequency depends on the setting of BYPASS. z BYPASS = 00b: 1/24 the sampling rate. z BYPASS = 01b: 1/12 the sampling rate. z BYPASS = 10b: 1/6 the sampling rate. z BYPASS = 11b: 1/6 the sampling rate. For DSP, 6 audio samples are written when an interrupt is received. 443/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 0x651 Bit Name Type Reset AFE AGC DSP GAIN 15 14 13 12 11 10 AFE_VAGC_GAIN 9 8 7 6 5 4 3 2 VAGC_GAIN R/W 000000 1 0 AGC Gain setting by AGC. It is only validate while VAGC_CTRL is set to 1. 0x658 Bit Name Type Reset 15 14 13 12 Audio left channel data register 0. 8.4 AFE_ALCH_DAT 0 AFE Audio Left-Channel Data Register 0 11 10 9 8 7 ALCH_DAT0 W 0 6 5 4 3 2 1 0 The content of this register is used as the left channel digital filter inputs. Programming Guide Several cases – including speech call, voice memo record, voice memo playback, melody playback and DAI tests – requires that partial or the whole audio front-end be turned on. The following are the recommended voice band path programming procedures to turn on audio front-end: 1. MCU programs the AFE_VMCU_CON1, AFE_DAI_CON, AFE_VAGC_CON1, AFE_VAGC_CON2, AFE_VAGC_CON3, AFE_VAGC_CON4, AFE_VAGC_CON5, AFE_VAGC_CON6, AFE_VLB_CON, AFE_VAG_CON, AFE_VAC_CON0, AFE_VAC_CON1 and AFE_VAPDN_CON registers for specific operation modes. Refer also to the analog chip interface specification. 2. MCU clears the VAFE bit of the PDN_CON2 register to ungate the clock for the voice band path. software power down control specification. Refer to the 3. MCU sets AFE_VMCU_CON0 to start operation of the voice band path. The following are the recommended voice band path programming procedures to turn off audio front-end: 1. MCU programs AFE_VAPDN_CON to power down the voice band path analog blocks. 2. MCU clears AFE_VMCU_CON0 to stop operation of the voice band path. 3. MCU sets VAFE bit of PDN_CON2 register to gate the clock for the voice band path. The following are the recommended audio band path programming procedures to turn on audio front-end: 1. MCU programs the AFE_AMCU_CON1, AFE_AAG_CON, AFE_AAC_CON, and AFE_AAPDN_CON registers for specific configurations. Refer also to the analog chip interface specification. 444/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 2. MCU clears the AAFE bit of the PDN_CON2 register to ungate the clock for the audio band path. to the software power down control specification. Refer 3. MCU sets AFE_AMCU_CON0 to start operation of the audio band path. The following are the recommended audio band path programming procedures to turn off audio front-end: 1. MCU programs the AFE_AAPDN_CON to power down the audio band path analog blocks. also to the analog block specification for further details. Refer 2. MCU clears AFE_AMCU_CON0 to stop operation of the audio band path. 3. MCU sets the AAFE bit of the PDN_CON2 register to gate the clock for the audio band path. 445/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 9 Radio Interface Control This chapter details the MT6235 interface control with the radio part of a GSM terminal. Providing a comprehensive control scheme, the MT6235 radio interface consists of Baseband Serial Interface (BSI), Baseband Parallel Interface (BPI), Automatic Power Control (APC) and Automatic Frequency Control (AFC), together with APC-DAC and AFC-DAC. 9.1 Baseband Serial Interface The Baseband Serial Interface controls external radio components. A 3-wire serial bus transfers data to RF circuitry for PLL frequency change, reception gain setting, and other radio control purposes. In this unit, BSI data registers are double-buffered in the same way as the TDMA event registers. The user writes data into the write buffer and the data is transferred from the write buffer to the active buffer when a TDMA_EVTVAL signal (from the TDMA timer) is pulsed. Each data register BSI_Dn_DAT is associated with one data control register BSI_Dn_CON, where n denotes the index. Each data control register identifies which events (signaled by TDMA_BSISTRn, generated by the TDMA timer) trigger the download process of the word in register BSI_Dn_DAT. The word and its length (in bits) is downloaded via the serial bus. A special event is triggered when the IMOD flag is set to 1: it provides immediate download process without software programming the TDMA timer. If more than one data word is to be downloaded on the same BSI event, the word with the lowest address among them is downloaded first, followed by the next lowest and so on. The total download time depends on the word length, the number of words to download, and the clock rates. The programmer must space the successive event to provide enough time. If the download process of the previous event is not complete before a new event arrives, the latter is suppressed. The unit has four output pins: BSI_CLK is the output clock, BSI_DATA is the serial data port, and BSI_CS0 and BSI_CS1 are the select pins for 2 external components. BSI_CS1 is multiplexed with another function. Please refer to GPIO table for more detail. In order to support bi-directional read and write operations of the RF chip, software can directly write values to BSI_CLK, BSI_DATA and BSI_CS by programming the BSI_DOUT register. Data from the RF chip can be read by software via the register BSI_DIN. If the RF chip interface is a 3-wire interface, then BSI_DATA is bi-directional. Before software can program the 3-wire behavior, the BSI_IO_CON register must be set. An additional signal path from GPIO accommodates RF chips with a 4-wire interface. The block diagram of the BSI unit is as depicted in Figure 69. 446/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 TDMA_EVTVAL (from TDMA timer) Control APB BUS TDMA_BSISTR (0~15) (from TDMA timer) IMOD SETENV BSI_DIN_GPIO (read from RFIC) (GPIO) BSI_CLK Active buffer Write buffer Serial port control BSI_DATA BSI_CS0 BSI_CS1 (GPIO) BSI Unit z Figure 69 Block diagram of BSI unit. BSI_CLK (invert) BSI_CLK (true) MSB BSI_DATA LSB BSI_CSx (long) BSI_CSx (short) z Figure 70 9.1.1 Register Definitions BSI+0000h Bit Timing characteristic of BSI interface. 15 BSI control register 14 13 12 11 10 Name Type Reset This register is the control register for the BSI unit. BSI_CON 9 8 7 6 5 4 3 SETE EN1_ EN1_ EN0_ EN0_ IMOD NV POL LEN POL LEN R/W R/W R/W R/W R/W WO 0 0 0 0 0 N/A 2 1 CLK_SPD R/W 0 0 CLK_ POL R/W 0 The register controls the signal type of the 3-wire interface. CLK_POL Controls the polarity of BSI_CLK. Refer to Figure 70. 0 True clock polarity 1 Inverted clock polarity CLK_SPD Defines the clock rate of BSI_CLK. The 3-wire interface provides 4 choices of data bit rate. The default is 52/2 MHz. 00 52/2 MHz 447/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 01 52/4 MHz 10 52/6 MHz 11 52/8 MHz IMOD Enables immediate mode. If the user writes 1 to the flag, the download is triggered immediately without waiting for the timer events. The words for which the register event ID equals 1Fh are downloaded following this signal. This flag is write-only. The immediate write is exercised only once: the programmer must write the flag again to invoke another immediate download. Setting the flag does not disable the other events from the timer; the programmer can disable all events by setting BSI_ENA to all zeros. ENX_LEN Controls the type of signals BSI_CS0 and BSI_CS1. Refer to Figure 69. 0 Long enable pulse 1 Short enable pulse ENX_POL Controls the polarity of signals BSI_CS0 and BSI_CS1. 0 True enable pulse polarity 1 Inverted enable pulse polarity SETENV Enables the write operation of the active buffer. 0 The user writes to the write buffer. The data is then latched in the active buffer after TDMA_EVTVAL is pulsed. 1 The user writes data directly to the active buffer. BSI+0004h Bit 15 Name ISB Type R/W Control part of data register 0 14 13 12 11 LEN R/W 10 9 8 BSI_D0_CON 7 6 5 4 3 2 EVT_ID R/W 1 0 This register is the control part of the data register 0. The register determines the required length of the download data word, the event to trigger the download process of the word, and the targeted device. Table 43 lists the 44 data registers of this type. The max length of the first 40 data registers is 32 bits, and that of the last 4 data registers is 78 bits. Multiple data control registers may contain the same event ID. The data words of all registers with the same event ID are downloaded when the event occurs. EVT_ID Stores the event ID for which the data word awaits to be downloaded. 00000~10011 Synchronous download of the word with the selected EVT_ID event. between this field and the event is listed as Table 42. Event ID (in binary) – EVT_ID Event name 00000 TDMA_BSISTR0 00001 TDMA_BSISTR1 00010 TDMA_BSISTR2 00011 TDMA_BSISTR3 00100 TDMA_BSISTR4 00101 TDMA_BSISTR5 00110 TDMA_BSISTR6 00111 TDMA_BSISTR7 01000 TDMA_BSISTR8 01001 TDMA_BSISTR9 448/599 The relationship MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 Table 42 LEN ISB TDMA_BSISTR10 01011 TDMA_BSISTR11 01100 TDMA_BSISTR12 01101 TDMA_BSISTR13 01110 TDMA_BSISTR14 01111 TDMA_BSISTR15 10000 TDMA_BSISTR16 10001 TDMA_BSISTR17 10010 TDMA_BSISTR18 TDMA_BSISTR19 10011 The relationship between the value of EVT_ID field in the BSI control registers and the TDMA_BSISTR events. 10100~11110Reserved 11111 Immediate download The field stores the length of the data word. The actual length is defined as LEN + 1 in units of bits. For data registers 0~39, the value ranges from 0 to 31, corresponding to 1 to 32 bits in length. For data registers 40~43, the value ranges from 0 to 77, corresponding to 1 to 78 bits in length. The flag selects the target device. 0 Device 0 is selected. 1 Device 1 is selected. BSI +0008h Bit Name Type Bit Name Type 01010 Data part of data register 0 31 30 29 28 27 26 25 15 14 13 12 11 10 9 24 23 DAT [31:16] R/W 8 7 DAT [15:0] R/W BSI_D0_DAT 22 21 20 19 18 17 16 6 5 4 3 2 1 0 This register is the data part of the data register 0. The legal length of the data is up to 32 bits. to be transmitted is specified in LEN field in the BSI_D0_CON register. DAT The field signifies the data part of the data register. Table 43 lists the address mapping and function of the 44 pairs of data registers. The actual number of bits Register Address Register Function Acronym BSI +0004h Control part of data register 0 BSI_D0_CON BSI +0008h Data part of data register 0 BSI_D0_DAT BSI +000Ch Control part of data register 1 BSI_D1_CON BSI +0010h Data part of data register 1 BSI_D1_ DAT BSI +0014h Control part of data register 2 BSI_D2_CON BSI +0018h Data part of data register 2 BSI_D2_ DAT BSI +001Ch Control part of data register 3 BSI_D3_CON BSI +0020h Data part of data register 3 BSI_D3_ DAT 449/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 BSI +0024h Control part of data register 4 BSI_D4_CON BSI +0028h Data part of data register 4 BSI_D4_ DAT BSI +002Ch Control part of data register 5 BSI_D5_CON BSI +0030h Data part of data register 5 BSI_D5_ DAT BSI +0034h Control part of data register 6 BSI_D6_CON BSI +0038h Data part of data register 6 BSI_D6_ DAT BSI +003Ch Control part of data register 7 BSI_D7_CON BSI +0040h Data part of data register 7 BSI_D7_ DAT BSI +0044h Control part of data register 8 BSI_D8_CON BSI +0048h Data part of data register 8 BSI_D8_ DAT BSI +004Ch Control part of data register 9 BSI_D9_CON BSI +0050h Data part of data register 9 BSI_D9_ DAT BSI +0054h Control part of data register 10 BSI_D10_CON BSI +0058h Data part of data register 10 BSI_D10_ DATA BSI +005Ch Control part of data register 11 BSI_D11_CON BSI +0060h Data part of data register 11 BSI_D11_ DAT BSI +0064h Control part of data register 12 BSI_D12_CON BSI +0068h Data part of data register 12 BSI_D12_ DAT BSI +006Ch Control part of data register 13 BSI_D13_CON BSI +0070h Data part of data register 13 BSI_D13_ DAT BSI +0074h Control part of data register 14 BSI_D14_CON BSI +0078h Data part of data register 14 BSI_D14_ DAT BSI +007Ch Control part of data register 15 BSI_D15_CON BSI +0080h Data part of data register 15 BSI_D15_ DAT BSI +0084h Control part of data register 16 BSI_D16_CON BSI +0088h Data part of data register 16 BSI_D16_ DAT BSI +008Ch Control part of data register 17 BSI_D17_CON BSI +0090h Data part of data register 17 BSI_D17_ DAT BSI +0094h Control part of data register 18 BSI_D18_CON BSI +0098h Data part of data register 18 BSI_D18_ DAT BSI +009Ch Control part of data register 19 BSI_D19_CON BSI +00A0h Data part of data register 19 BSI_D19_ DAT BSI +00A4h Control part of data register 20 BSI_D20_CON BSI +00A8h Data part of data register 20 BSI_D20_ DAT BSI +00ACh Control part of data register 21 BSI_D21_CON BSI +00B0h Data part of data register 21 BSI_D21_ DAT BSI +00B4h Control part of data register 22 BSI_D22_CON BSI +00B8h Data part of data register 22 BSI_D22_ DAT BSI +00BCh Control part of data register 23 BSI_D23_CON 450/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 BSI +00C0h Data part of data register 23 BSI_D23_ DAT BSI +00C4h Control part of data register 24 BSI_D24_CON BSI +00C8h Data part of data register 24 BSI_D24_ DAT BSI +00CCh Control part of data register 25 BSI_D25_CON BSI +00D0h Data part of data register 25 BSI_D25_ DAT BSI +00D4h Control part of data register 26 BSI_D26_CON BSI +00D8h Data part of data register 26 BSI_D26_ DAT BSI +00DCh Control part of data register 27 BSI_D27_CON BSI +00E0h Data part of data register 27 BSI_D27_ DAT BSI +00E4h Control part of data register 28 BSI_D28_CON BSI +00E8h Data part of data register 28 BSI_D28_ DAT BSI +00ECh Control part of data register 29 BSI_D29_CON BSI +00F0h Data part of data register 29 BSI_D29_ DAT BSI +00F4h Control part of data register 30 BSI_D30_CON BSI +00F8h Data part of data register 30 BSI_D30_ DAT BSI +00FCh Control part of data register 31 BSI_D31_CON BSI +0100h Data part of data register 31 BSI_D31_ DAT BSI +0104h Control part of data register 32 BSI_D32_CON BSI +0108h Data part of data register 32 BSI_D32_ DAT BSI +010Ch Control part of data register 33 BSI_D33_CON BSI +0110h Data part of data register 33 BSI_D33_ DAT BSI +0114h Control part of data register 34 BSI_D34_CON BSI +0118h Data part of data register 34 BSI_D34_ DAT BSI +011Ch Control part of data register 35 BSI_D35_CON BSI +0120h Data part of data register 35 BSI_D35_ DAT BSI +0124h Control part of data register 36 BSI_D36_CON BSI +0128h Data part of data register 36 BSI_D36_ DAT BSI +012Ch Control part of data register 37 BSI_D37_CON BSI +0130h Data part of data register 37 BSI_D37_ DAT BSI +0134h Control part of data register 38 BSI_D38_CON BSI +0138h Data part of data register 38 BSI_D38_ DAT BSI +013Ch Control part of data register 39 BSI_D39_CON BSI +0140h Data part of data register 39 BSI_D39_ DAT BSI +0144h Control part of data register 40 BSI_D40_CON BSI +0148h Data part of data register 40 (MSB 14 bits) BSI_D40_ DAT2 BSI +014Ch Data part of data register 40 BSI_D40_ DAT1 BSI +0150h Data part of data register 40 (LSB 32 bits) BSI_D40_ DAT0 BSI +0154h Control part of data register 41 BSI_D41_CON BSI +0158h Data part of data register 41 (MSB 14 bits) BSI_D41_ DAT2 451/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 BSI +015Ch Data part of data register 41 BSI_D41_ DAT1 BSI +0160h Data part of data register 41 (LSB 32 bits) BSI_D41_ DAT0 BSI +0164h Control part of data register 42 BSI_D42_CON BSI +0168h Data part of data register 42 (MSB 14 bits) BSI_D42_ DAT2 BSI +016Ch Data part of data register 42 BSI_D42_ DAT1 BSI +0170h Data part of data register 42 (LSB 32 bits) BSI_D42_ DAT0 BSI +0174h Control part of data register 43 BSI_D43_CON BSI +0178h Data part of data register 43 (MSB 14 bits) BSI_D43_ DAT2 BSI +017Ch Data part of data register 43 BSI_D43_ DAT1 BSI +0180h Data part of data register 43 (LSB 32 bits) Table 43 BSI data registers BSI_D43_ DAT0 BSI +0190h BSI event enable register Bit 15 14 13 12 11 10 9 Name BSI15 BSI14 BSI13 BSI12 BSI11 BSI10 BSI9 Type R/W R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1 1 BSI_ENA_0 8 BSI8 R/W 1 This register enables an event by setting the corresponding bit. bits are also set to 1 after TDMA_EVTVAL pulse. BSIx 6 BSI6 R/W 1 5 BSI5 R/W 1 4 BSI4 R/W 1 3 BSI3 R/W 1 2 BSI2 R/W 1 1 BSI1 R/W 1 After a hardware reset, all bits are initialized to 1. 0 BSI0 R/W 1 These Enables downloading of the words corresponding to the events signaled by TMDA_BSI. 0 The event is not enabled. 1 The event is enabled. BSI +0194h Bit Name Type Reset 7 BSI7 R/W 1 15 BSI event enable register – MSB 4 bits 14 13 12 11 10 9 8 7 6 BSI_ENA_1 5 4 3 2 1 0 BSI19 BSI18 BSI17 BSI16 R/W R/W R/W R/W 1 1 1 1 The register could enable the event by setting the corresponding bit. After hardware reset, all bits are initialized as 1. Besides, those bits are set as 1 after TDMA_EVTVAL is pulsed. BSIx The flag enables the downloading of the words that corresponds to the events signaled by TMDA_BSI. 0 The event is not enabled. The event is enabled. BSI +0198h Bit 15 BSI IO mode control register BSI_IO_CON 14 13 12 11 10 9 8 7 6 5 4 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Name Type R/W Reset 0 3 2 1 0 SEL_ 4_WIR DAT_ MODE CS1 E DIR R/W R/W R/W R/W 0 0 1 0 MODE Defines the source of BSI signal. 0 BSI signal is generated by the hardware. 452/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 BSI signal is generated by the software. In this mode, the BSI clock depends on the value of the field DOUT.CLK. BSI_CS depends on the value of the field DOUT.CS and BSI_DATA depends on the value of the field DOUT.DATA. DAT_DIR Defines the direction of BSI_DATA. 0 BSI _DATA is configured as input. The 3-wire interface is used and BSI_DATA is bi-directional. 1 BSI_DATA is configured as output. 4_WIRE Defines the BSI_DIN source. 0 The 3-wire interface is used and BSI_DATA is bi-directional. BSI_DIN comes from the same pin as BSI_DATA. 1 The 4-wire interface is used. Another pin (GPIO) is used as BSI_DIN. SEL_CS1 Defines which of the BSI_CSx (BSI_CS0 or BSI_CS1) is written by the software. 0 BSI_CS0 is selected. 1 BSI_CS1 is selected. 1 BSI +019Ch Bit 15 Name Type R/W Reset 0 Software-programmed data out BSI_DOUT 14 13 12 11 10 9 8 7 6 5 4 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 3 2 DATA R/W W 0 0 1 CS W 0 0 CLK W 0 CLK Signifies the BSI_CLK signal. CS Signifies the BSI_CS signal. DATA Signifies the BSI_DATA signal. BSI +01A0h Bit 15 Name Type R/W Reset 0 DIN Input data from RF chip BSI_DIN 14 13 12 11 10 9 8 7 6 5 4 3 2 1 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 0 DIN R 0 Registers the input value of BSI_DATA from the RF chip. BSI +01A4h Bit 15 Name Type R/W Reset 0 BSI data pair number BSI_PAIR_NUM 14 13 12 11 10 9 8 7 6 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 5 4 3 2 PAIR_NUM R 28 1 0 PAIR_NUM The software can program how many pairs of data register to be used. The default value is 28 pairs. This value must be smaller or equal to 44. The first 40 pairs are 32-bit long, and the last four pairs are 78-bit long. 453/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 9.2 Baseband Parallel Interface 9.2.1 General Description The Baseband Parallel Interface features 10 control pins, which are used for timing-critical external circuits. These pins typically control front-end components which must be turned on or off at specific times during GSM operation, such as transmit-enable, band switching, TR-switch, etc. TDMA_EVTVAL (from TDMA timer) TDMA_BPISTR (0~41) (from TDMA timer) BPI_BUS0 BPI_BUS1 BPI_BUS2 BPI_BUS3 BPI_BUS4 BPI_BUS5 BPI_BUS6 BPI_BUS7 BPI_BUS8 BPI_BUS9 Event Register Write buffer Active buffer MUX APB I/F Output buffer MUX petev Immediate mode The driving capability is configurable. The driving capability is fixed. Figure 71 Block diagram of BPI interface The user can program 42 sets of 10-bit registers to set the output value of BPI_BUS0~BPI_BUS9. The data is stored in the write buffers. The write buffers are then forwarded to the active buffers when the TDMA_EVTVAL signal is pulsed, usually once per frame. Each of the 42 write buffers corresponds to an active buffer, as well as to a TDMA event. Each TDMA_BPISTR event triggers the transfer of data in the corresponding active buffer to the output buffer, thus changing the value of the BPI bus. The user can disable the events by programming the enable registers in the TDMA timer. If the TDMA_BPISTR event is disabled, the corresponding signal TDMA_BPISTR is not pulsed, and the value on the BPI bus remains unchanged. For applications in which BPI signals serve as the switch, current-driving components are typically added to enhance driving capability. Three configurable output pins provide current up to 8 mA, and help reduce the number of external components. The output pins BPI_BUS6, BPI_BUS7, BPI_BUS8, and BPI_BUS9 are multiplexed with GPIO. Please refer to the GPIO table for more detailed information. 9.2.2 Register Definitions BPI+0000h Bit 15 BPI control register 14 13 12 11 10 BPI_CON 9 8 454/599 7 6 5 4 3 2 1 0 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 Name PINM2 PINM1 PINM0 Type Reset WO 0 This register is the control register of the BPI unit. the current driving capability for the output pins. WO 0 WO 0 PETE V R/W 0 The register controls the direct access mode of the active buffer and The driving capabilities of BPI_BUS0, BPI_BUS1 and BPI_BUS2 can be 2 mA or 8 mA, determined by the value of PINM0, PINM1 and PINM2 respectively. These output pins provide a higher driving capability and save on external current-driving components. In addition to the configurable pins, pins BPI_BUS3 to BPI_BUS9 provide a driving capability of 2 mA (fixed). PETEV Enables direct access to the active buffer. 0 The user writes data to the write buffer. The data is latched in the active buffer after the TDMA_EVTVAL signal is pulsed. 1 The user directly writes data to the active buffer without waiting for the TDMA_EVTVAL signal. PINM0 Controls the driving capability of BPI_BUS0. 0 The output driving capability is 2mA. 1 The output driving capability is 8mA. PINM1 Controls the driving capability of BPI_BUS1. 0 The output driving capability is 2mA. 1 The output driving capability is 8mA. PINM2 Controls the driving capability of BPI_BUS2. 0 The output driving capability is 2mA. 1 The output driving capability is 8mA. BPI +0004h Bit Name Type 15 BPI data register 0 14 13 12 11 10 BPI_BUF0 9 PO9 R/W 8 PO8 R/W 7 PO7 R/W 6 PO6 R/W 5 PO5 R/W 4 PO4 R/W 3 PO3 R/W 2 PO2 R/W 1 PO1 R/W 0 PO0 R/W This register defines the BPI signals that are associated with the event TDMA_BPI0. Table 44 lists 42 registers of the same structure, each of which is associated with one specific event signal from the TDMA timer. The data registers are all double-buffered. When PETEV is set to 0, the data register links to the write buffer. When PETEV is set to 1, the data register links to the active buffer. One register, BPI_BUFI, is dedicated for use in immediate mode. change in the corresponding BPI signal and bus. Writing a value to that register effects an immediate POx This flag defines the corresponding signals for BPIx after the TDMA event 0 takes place. The overall data register definition is listed in Table 44. Register Address Register Function Acronym BPI +0004h BPI pin data for event TDMA_BPI 0 BPI_BUF0 BPI +0008h BPI pin data for event TDMA_BPI 1 BPI_BUF1 BPI +000Ch BPI pin data for event TDMA_BPI 2 BPI_BUF2 BPI +0010h BPI pin data for event TDMA_BPI 3 BPI_BUF3 455/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 BPI +0014h BPI pin data for event TDMA_BPI 4 BPI_BUF4 BPI +0018h BPI pin data for event TDMA_BPI 5 BPI_BUF5 BPI +001Ch BPI pin data for event TDMA_BPI 6 BPI_BUF6 BPI +0020h BPI pin data for event TDMA_BPI 7 BPI_BUF7 BPI +0024h BPI pin data for event TDMA_BPI 8 BPI_BUF8 BPI +0028h BPI pin data for event TDMA_BPI 9 BPI_BUF9 BPI +002Ch BPI pin data for event TDMA_BPI 10 BPI_BUF10 BPI +0030h BPI pin data for event TDMA_BPI 11 BPI_BUF11 BPI +0034h BPI pin data for event TDMA_BPI 12 BPI_BUF12 BPI +0038h BPI pin data for event TDMA_BPI 13 BPI_BUF13 BPI +003Ch BPI pin data for event TDMA_BPI 14 BPI_BUF14 BPI +0040h BPI pin data for event TDMA_BPI 15 BPI_BUF15 BPI +0044h BPI pin data for event TDMA_BPI 16 BPI_BUF16 BPI +0048h BPI pin data for event TDMA_BPI 17 BPI_BUF17 BPI +004Ch BPI pin data for event TDMA_BPI 18 BPI_BUF18 BPI +0050h BPI pin data for event TDMA_BPI 19 BPI_BUF19 BPI +0054h BPI pin data for event TDMA_BPI 20 BPI_BUF20 BPI +0058h BPI pin data for event TDMA_BPI 21 BPI_BUF21 BPI +005Ch BPI pin data for event TDMA_BPI 22 BPI_BUF22 BPI +0060h BPI pin data for event TDMA_BPI 23 BPI_BUF23 BPI +0064h BPI pin data for event TDMA_BPI 24 BPI_BUF24 BPI +0068h BPI pin data for event TDMA_BPI 25 BPI_BUF25 BPI +006Ch BPI pin data for event TDMA_BPI 26 BPI_BUF26 BPI +0070h BPI pin data for event TDMA_BPI 27 BPI_BUF27 BPI +0074h BPI pin data for event TDMA_BPI 28 BPI_BUF28 BPI +0078h BPI pin data for event TDMA_BPI 29 BPI_BUF29 BPI +007Ch BPI pin data for event TDMA_BPI 30 BPI_BUF30 BPI +0080h BPI pin data for event TDMA_BPI 31 BPI_BUF31 BPI +0084h BPI pin data for event TDMA_BPI 32 BPI_BUF32 BPI +0088h BPI pin data for event TDMA_BPI 33 BPI_BUF33 BPI +008Ch BPI pin data for event TDMA_BPI 34 BPI_BUF34 BPI +0090h BPI pin data for event TDMA_BPI 35 BPI_BUF35 BPI +0094h BPI pin data for event TDMA_BPI 36 BPI_BUF36 BPI +0098h BPI pin data for event TDMA_BPI 37 BPI_BUF37 BPI +009Ch BPI pin data for event TDMA_BPI 38 BPI_BUF38 BPI +00A0h BPI pin data for event TDMA_BPI 39 BPI_BUF39 BPI +00A4h BPI pin data for event TDMA_BPI 40 BPI_BUF40 BPI +00A8h BPI pin data for event TDMA_BPI 41 BPI_BUF41 BPI +00ACh BPI pin data for immediate mode BPI_BUFI 456/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 Table 44 BPI +00B0h BPI Data Registers. BPI event enable register 0 BPI_ENA0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name BEN15 BEN14 BEN13 BEN12 BEN11 BEN10 BEN9 BEN8 BEN7 BEN6 BEN5 BEN4 BEN3 BEN2 BEN1 BEN0 Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 This register enables the events that are signaled by the TDMA timer: by clearing a register bit, the corresponding event signal is ignored. After a hardware reset, all the enable bits default to 1 (enabled). Upon receiving a TDMA_EVTVAL pulse, all register bits are also set to 1 (enabled). BENn This flag indicates whether event n signals are heeded or ignored. 0 Event n is disabled (ignored). 1 Event n is enabled. BPI+00B4h BPI event enable register 1 BPI_ENA1 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name BEN31 BEN30 BEN29 BEN28 BEN27 BEN26 BEN25 BEN24 BEN23 BEN22 BEN21 BEN20 BEN19 BEN18 BEN17 BEN16 Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 This register enables the events that are signaled by the TDMA timing generator: by clearing a register bit, the corresponding event signal is ignored. After a hardware reset, all the enable bits default to 1 (enabled). Upon receiving the TDMA_EVTVAL pulse, all register bits are also set to 1 (enabled). BENn This flag indicates whether event n signals are heeded or ignored. 0 Event n is disabled (ignored). 1 Event n is enabled. BPI+00B8h Bit Name Type Reset 15 BPI event enable register 2 14 13 12 11 10 9 BPI_ENA2 8 7 6 5 4 3 2 1 0 BEN41 BEN40 BEN39 BEN38 BEN37 BEN36 BEN35 BEN34 BEN33 BEN32 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 The register is used to enable the events that are signaled by the TDMA timing generator. After hardware reset, all the enable bits defaults to be 1 (enabled). Upon receiving the TDMA_EVTVAL pulse, those bits are also set to 1 (enabled). BENn The flag controls the function of event n. 0 The event n is disabled. 1 The event n is enabled. 9.3 9.3.1 Automatic Power Control (APC) Unit General Description The Automatic Power Control (APC) unit controls the Power Amplifier (PA) module. Through APC unit, the proper transmit power level of the handset can be set to ensure that burst power ramping requirements are met. In one TDMA 457/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 frame, up to 7 TDMA events can be enabled to support multi-slot transmission. used in one frame to make up 4 consecutive transmission slots. In practice, 5 banks of ramp profiles are The shape and magnitude of the ramp profiles are configurable to fit ramp-up (ramp up from zero), intermediate ramp (ramp between transmission windows), and ramp-down (ramp down to zero) profiles. Each bank of the ramp profile consists of 16 8-bit unsigned values, which are adjustable for different conditions. The entries from one bank of the ramp profile are partitioned into two parts, with 8 values in each half. In normal operation, the entries in the left half are multiplied by a 10-bit left scaling factor, and the entries in the right half are multiplied by a 10-bit right scaling factor. The values are then truncated to form 16 10-bit intermediate values. Finally the intermediate ramp profile are linearly interpolated into 32 10-bit values and sequentially used to update the D/A converter. The block diagram of the APC unit is shown in Figure 72 . The APB bus interface is 32 bits wide. Four write accesses are required to program each bank of ramp profile. detailed register allocations are listed in Table 45. PDN_APC ( from global control) TDMA_APCSTR (0~6) TDMA_APCEN ( from TDMA timer ) ( from TDMA timer) QBIT_EN Power and clock control APB BUS (32bits data bus) The DAC_PU APB I/F Ramp profile, scaling factor, & offset Multiplier & interpolator Output buffer DAC APC_BUS (10 bits) APC unit z Figure 72 Block diagram of APC unit. 9.3.2 Register Definitions APC+0000h Bit Name Type Bit Name Type APC 1st ramp profile #0 31 30 29 15 14 13 28 27 ENT3 R/W 12 11 ENT1 R/W APC_PFA0 26 25 24 23 22 21 10 9 8 7 6 5 20 19 ENT2 R/W 4 3 ENT0 R/W 18 17 16 2 1 0 The register stores the first four entries of the first power ramp profile. The first entry resides in the least significant byte [7:0], the second entry in the second byte [15:8], the third entry in the third byte [23:16], and the fourth in the most significant byte [31:24]. Since this register provides no hardware reset, the programmer must configure it before any APC event takes place. ENT3 ENT2 The field signifies the 4th entry of the 1st ramp profile. The field signifies the 3rd entry of the 1st ramp profile. 458/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 ENT1 The field signifies the 2nd entry of the 1st ramp profile. ENT0 The field signifies the 1st entry of the 1st ramp profile. The overall ramp profile register definition is listed in Table 45. Register Address Register Function Acronym st APC +0000h APC 1 ramp profile #0 APC_PFA0 APC +0004h APC 1st ramp profile #1 APC_PFA1 APC +0008h APC 1st ramp profile #2 APC_PFA2 st APC +000Ch APC 1 ramp profile #3 APC_PFA3 APC +0020h APC 2nd ramp profile #0 APC_PFB0 nd APC 2 ramp profile #1 APC +0024h APC_PFB1 nd APC +0028h APC 2 ramp profile #2 APC_PFB2 APC +002Ch APC 2nd ramp profile #3 APC_PFB3 rd APC +0040h APC 3 ramp profile #0 APC_PFC0 APC +0044h APC 3rd ramp profile #1 APC_PFC1 rd APC 3 ramp profile #2 APC +0048h APC_PFC2 rd APC +004Ch APC 3 ramp profile #3 APC_PFC3 APC +0060h APC 4th ramp profile #0 APC_PFD0 APC +0064h APC 4th ramp profile #1 APC_PFD1 APC +0068h APC 4th ramp profile #2 APC_PFD2 th APC 4 ramp profile #3 APC +006Ch APC_PFD3 th APC +0080h APC 5 ramp profile #0 APC_PFE0 APC +0084h APC 5th ramp profile #1 APC_PFE1 th APC +0088h APC 5 ramp profile #2 APC_PFE2 APC +008Ch APC 5th ramp profile #3 APC_PFE3 th APC 6 ramp profile #0 APC +00A0h APC_PFF0 th APC +00A4h APC 6 ramp profile #1 APC_PFF1 APC +00A8h APC 6th ramp profile #2 APC_PFF2 th APC 6 ramp profile #3 APC +00ACh APC_PFF3 th APC +00C0h APC 7 ramp profile #0 APC_PFG0 APC +00C4h APC 7th ramp profile #1 APC_PFG1 th APC +00C8h APC 7 ramp profile #2 APC_PFG2 APC +00CCh APC 7th ramp profile #3 APC_PFG3 Table 45 APC ramp profile registers APC +0010h Bit Name Type Reset 15 14 APC 1st ramp profile left scaling factor 13 12 11 10 9 8 7 6 APC_SCAL0L 5 4 SF R/W 1_0000_0000 3 2 1 0 The register stores the left scaling factor of the 1st ramp profile. This factor multiplies the first 8 entries of the 1st ramp profile to provide the scaled profile, which is then interpolated to control the D/A converter. 459/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 After a hardware reset, the initial value of the register is 256. In this case, no scaling is done (each entry of the ramp profile is multiplied by 1), because the 8 least significant bits are truncated after multiplication. The overall scaling factor register definition is listed in Table 46 . SF Scaling factor. APC +0014h Bit Name Type Reset 15 After a hardware reset, the value is 256. APC 1st ramp profile right scaling factor 14 13 12 11 10 9 8 7 6 APC_SCAL0R 5 4 SF R/W 1_0000_0000 3 2 1 0 The register stores the right scaling factor of the 1st ramp profile. This factor multiplies the last 8 entries of the 1st ramp profile to provide the scaled profile, which is then interpolated to control the D/A converter. After a hardware reset, the initial value of the register is 256. In this case, no scaling is done (each entry of the ramp profile is multiplied by 1), because the 8 least significant bits are truncated after multiplication. The overall scaling factor register definition is listed in Table 46 . SF Scaling factor. APC+0018h Bit Name Type Reset 15 After a hardware reset, the value is 256. APC 1st ramp profile offset value 14 13 12 11 10 9 8 7 APC_OFFSET0 6 5 4 OFFSET R/W 0 3 2 1 0 There are 7 offset values for the corresponding ramp profile. The 1st offset value also serves as the pedestal value. The value is used to power up the APC D/A converter before the RF signals start to transmit. The D/A converter is then biased on the value, to provide the initial control voltage for the external control loop. The exact value depends on the characteristics of the external components. The timing to output the pedestal value is configurable through the TDMA_BULCON2 register of the timing generator; its valid range is 0~127 quarter-bits of time after the baseband D/A converter is powered up. OFFSET Offset value for the corresponding ramp profile. The overall offset register definition is listed in Table 46. Register Address After a hardware reset, the default value is 0. Register Function Acronym st APC +0010h APC 1 ramp profile left scaling factor APC_SCAL0L APC +0014h APC 1st ramp profile right scaling factor APC_SCAL0R APC +0018h APC 1st ramp profile offset value APC_OFFSET0 nd APC +0030h APC 2 ramp profile left scaling factor APC_SCAL1L APC +0034h APC 2nd ramp profile right scaling factor APC_SCAL1R APC +0038h nd APC 2 ramp profile offset value rd APC_OFFSET1 APC +0050h APC 3 ramp profile left scaling factor APC_SCAL2L APC +0054h APC 3rd ramp profile right scaling factor APC_SCAL2R APC +0058h rd APC 3 ramp profile offset value 460/599 APC_OFFSET2 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 APC +0070h APC 4th ramp profile left scaling factor APC_SCAL3L APC +0074h APC 4th ramp profile right scaling factor APC_SCAL3R th APC +0078h APC 4 ramp profile offset value APC_OFFSET3 APC +0090h APC 5th ramp profile left scaling factor APC_SCAL4L th APC 5 ramp profile right scaling factor APC +0094h APC_SCAL4R th APC +0098h APC 5 ramp profile offset value APC_OFFSET4 APC +00B0h APC 6th ramp profile left scaling factor APC_SCAL5L APC +00B4h APC 6th ramp profile right scaling factor APC_SCAL5R APC +00B8h APC 6th ramp profile offset value APC_OFFSET5 th APC 7 ramp profile left scaling factor APC +00D0h APC_SCAL6L th APC +00D4h APC 7 ramp profile right scaling factor APC_SCAL6R APC +00D8h APC 7th ramp profile offset value APC_OFFSET6 Table 46 APC scaling factor and offset value registers APC+00E0h 15 GSM Defines the operation mode of the APC module. In GSM mode, each frame has only one slot, thus only one scaling factor and one offset value must be configured. If the GSM bit is set, the programmer needs only to configure APC_SCAL0L and APC_OFFSET0. If the bit is not set, the APC module is operating in GPRS mode. 0 The APC module is operating in GPRS mode. 1 The APC module is operating in GSM mode. Default value. Forces the APC D/A converter to power up. Test only. 0 The APC D/A converter is not forced to power up. The converter is only powered on when the transmission window is opened. Default value. 1 The APC D/A converter is forced to power up. 9.3.3 13 12 11 10 APC_CON Bit Name Type Reset FPU 14 APC control register 9 8 7 6 5 4 3 2 1 GSM R/W 1 0 FPU R/W 0 Ramp Profile Programming The first value of the first normalized ramp profile must be written in the least significant byte of the APC_PFA0 register. The second value must be written in the second least significant byte of the APC_PFA0, and so on. Each ramp profile can be programmed to form an arbitrary shape. The start of ramping is triggered by one of the TDMA_APCSTR signals. The timing relationship between TDMA_APCSTR and TDMA slots is depicted in Figure 73 for 4 consecutive time slots case. The power ramping profile must comply with the timing mask defined in GSM SPEC 05.05. The timing offset values for 7 ramp profiles are stored in the TDMA timer register from TDMA_APC0 to TDMA_APC6. 461/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 TDMA_APCSTR0 RX TDMA_APCSTR1 TX TDMA_APCSTR2 TX TDMA_APCSTR3 TX TDMA_APCSTR4 TX MX RX Figure 73 Timing diagram of TDMA_APCSTR. Because the APC unit provides more than 5 ramp profiles, up to 4 consecutive transmission slots can accommodated. The 2 additional ramp profiles are useful particularly when the timing between the last 2 transmission time slots and CTIRQ is uncertain; software can begin writing the ramp profiles for the succeeding frame during the current frame, alleviating the risk of not writing the succeeding frame’s profile data in time. In GPRS mode, to fit the intermediate ramp profile between different power levels, a simple scaling scheme is used to synthesize the ramp profile. The equation is as follows: DA 0 = OFF + S0 ⋅ DN 15, pre + DN 0 2 DN k −1 + DN k DA 2 k = OFF + S l ⋅ , k = 1,...,15 2 DA 2 k +1 = OFF + S l ⋅ DN k , k = 0,1,...,15 ⎧0, l=⎨ ⎩1, where DA DN S0 S1 OFF if 8 > k ≥ 0 if 15 ≥ k ≥ 8 = = = = = the data to present to the D/A converter, the normalized data which is stored in the register APC_PFn, the left scaling factor stored in register APC_SCALnL, the right scaling factor stored in register APC_SCALnR, and the offset value stored in the register APC_OFFSETn. The subscript n denotes the index of the ramp profile. The ramp calculation before interpolation is as depicted in Figure 74. During each ramp process, each word of the normalized profile is first multiplied by 10-bit scaling factors and added to an offset value to form a bank of 18-bit words. The first 8 words (in the left half part as in Figure 74) are multiplied by the left scaling factor S0 and the last 8 words (in the right half part as in Figure 74) are multiplied by the right scaling factor S1. The lowest 8 bits of each word are then truncated to get a 10-bit result. The scaling factor is 0x100, which represents no scaling on reset. A value smaller than 0x100 scales the ramp profile down, and a value larger than 100 scales the ramp profile up. 462/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 DN15 * S1 + OFF DN12 * S1 + OFF 16 Qb DN8 * S1 + OFF DN4 * S0 + OFF DN0 * S0 + OFF DN4 * S0 DN8 * S1 OFF z Figure 74 The timing diagram of the APC ramp. The 16 10-bit words are linearly interpolated into 32 10-bit words. A 10-bit D/A converter is then used to convert these 32 ramp values at a rate of 1.0833 MHz, that is, at quarter-bit rate. The timing diagram is shown in Figure 75 and the final value is retained on the output until the next event occurs. TDMA_APCSTR1 TDMA_APCSTR0 TDMA_APCSTR2 TDMA_APCSTRx TDMA_APCEN TX TX offset Ramp Profile Ramp Profile TX Burst Ramp Profile TX Burst ~29.5us ~29.5us ~29.5us TDMA_APCSTR1 0 APC_DATA 1 2 3 29 30 31 z Figure 75 Timing diagram of the APC ramping. The APC unit is only powered up when the APC window is open. The APC window is controlled by configuring the TDMA registers TDMA_BULCON1 and TDMA_BULCON2. Please refer to the TDMA timer unit for more detailed information. 463/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 The first offset value stored in the register APC_OFFSET0 also serves as the pedestal value, which is used to provide the initial power level for the PA. Since the profile is not double-buffered, the timing to write the ramping profile is critical. The programmer must be restricted from writing to the data buffer during the ramping process, otherwise the ramp profile may be incorrect and lead to a malfunction. 9.4 9.4.1 Automatic Frequency Control (AFC) Unit General description The Automatic Frequency Control (AFC) unit provides the direct control of the oscillator for frequency offset and Doppler shift compensation. The block diagram is of the AFC unit depicted in Figure 76. The module utilizes a 13-bit D/A converter to achieve high-resolution control. Two modes of operation provide flexibility when controlling the oscillator; they are described as follows. TDMA_EVTVAL ( from TDMA timer ) APB BUS Write buffer Active buffer TDMA_AFC ( from TDMA timer ) AFC_BU S Output buffer DAC VC AFC Immediate write oscillator I_MODE Control register H_MODE Power control HOLDN_DAC F_MODE PDN_DAC AFC unit PDN_AFC ( from global control ) Figure 76 The block diagram of the AFC controller In timer-triggered mode, the TDMA timer controls the AFC enabling events. Each TDMA frame can pulse at most four events. Double buffer architecture is supported. AFC values can be written to the write buffers. When the signal TDMA_EVTVAL is received, the values in the write buffers are latched into the active buffers. However, AFC values can also be written to the active buffers directly. Each event is associated with an active buffer sharing the same index. When a TDMA event is triggered by TDMA_AFC, the value in the corresponding active buffer takes effect. Figure 77 shows a timing diagram of AFC events with respect to TX/RX/MX windows. In this mode, the D/A converter can stay powered on or be powered on for a programmable duration (256 quarter-bits, by default). The latter option is for power saving. RX MX TX AFC_STR0 AFC_STR1 AFC_STR2 MX AFC_STR3 Figure 77 Timing Diagram for the AFC Controller 464/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 In immediate mode, the MCU can directly control the AFC value without event-triggering. The value written by the MCU takes effect immediately. In this mode, the D/A converter must be powered on continuously. When transitioning from immediate mode into timer-triggered mode (by setting flag I_MODE in the register AFC_CON to be 0), the D/A converter is kept powered on for a programmable duration (256 quarter-bits by default) if a TDMA_AFC is not been pulsed. The duration is prolonged upon receiving events. 9.4.2 Register Definitions AFC+0000h Bit 15 AFC control register 14 13 12 11 10 AFC_CON 9 8 7 6 5 Name Type Reset 4 3 2 1 0 H_MO RDAC F_MO FETE I_MO DE T DE NV DE R/w R/W R/W R/W R/W 0 0 0 0 0 Four control modes are defined and can be controlled through the AFC control register. F_MODE enables the force power up mode. FETENV enables the direct write operation to the active buffer. I_MODE enables the immediate mode. RDACT enables the direct read operation from the active buffer. HOLD_ON enables the AFC DAC hold mode. RDACT The flag enables the direct read operation from the active buffer. Note the control flag is only applicable to the four data buffer including AFC_DAT0, AFC_DAT1, AFC_DAT2, and AFC_DAT3. 0 APB read from the write buffer. 1 APB read from the active buffer. FETENV The flag enables the direct write operation to the active buffer. Note the control flag is only applicable to the for data buffer including AFC_DAT0, AFC_DAT1, AFC_DAT2, and AFC_DAT3. 0 APB write to the write buffer. 1 APB write to the active buffer. F_MODE The flag enables the force power up mode. 0 The force power up mode is not enabled. 1 The force power up mode is enabled. I_MODE The flag enables the immediate mode. To enable the immediate mode also enable the force power up mode. 0 The immediate mode is not enabled. 1 The immediate mode is enabled. H_MODE The flag enables the hold mode of AFC DAC. If this mode is enabled, the DAC will keep the previous voltage level instead of power down. 0 The hold mode is not enabled. 1 The hold mode is enabled. While SRCLKENAI = 1’b1, AFC DAC will be turned on at the normal mode. SRCLKENAI is a gpio_mux pin. Make sure that the gpio mode is configured at the correct mode before BB enters the sleep mode. AFC +0004h Bit Name Type 15 14 AFC data register 0 13 12 11 10 AFC_DAT0 9 8 465/599 7 6 AFCD R/W 15 4 3 2 1 0 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 The register stores the AFC value for the event 0 triggered by the TDMA timer in timer-triggered mode. When the RDACT or FETENV bit (of the AFC_CON register) is set, the data transfer operates on the active buffer. When neither flag is set, the data transfer operates on the write buffer. AFCD The AFC sample for the D/A converter. Four registers (AFC_DAT0, AFC_DAT1, AFC_DAT2, AFC_DAT3) of the same type correspond to the event triggered by the TDMA timer. The four registers are summarized in Table 1. Table 1 Register Address Register Function Acronym AFC +0004h AFC control value 0 AFC_DAT0 AFC +0008h AFC control value 1 AFC_DAT1 AFC +000Ch AFC control value 2 AFC_DAT2 AFC +0010h AFC control value 3 AFC_DAT3 AFC Data Registers Immediate mode can only use AFC_DAT0. In this mode, only the control value in the AFC_DAT0 write buffer is used to control the D/A converter. Unlike timer-triggered mode, the control value in AFC_DAT0 write buffer can bypass the active buffer stage and be directly coupled to the output buffer in immediate mode. To use immediate mode, program the AFC_DAT0 in advance and then enable immediate mode by setting the I_MODE flag in the AFC_CON register. The registers AFC_DATA0, AFC_DAT1, AFC_DAT2, and AFC_DAT3 have no initial values, thus the register must be programmed before any AFC event takes place. The AFC value for the D/A converter, i.e., the output buffer value, is initially 0 after power up before any event occurs. AFC +0014h Bit Name Type Reset 15 14 AFC power up period 13 12 11 10 AFC_PUPER 9 8 7 6 PU_PER R/W ff 5 4 3 2 1 0 This register stores the AFC power up period, which is 13 bits wide. The value ranges from 0 to 8191. If the I_MODE or F_MODE flag is set, this register has no effect since the D/A converter is powered up continuously. If neither flag is set, the register controls the power up duration of the D/A converter. During that period, the signal PDN_DAC in Figure 76 is set to 1(power up). PU_PER Stores the AFC power up period. After hardware power up, the field is initialized to 255. 466/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 10 Baseband Front End Baseband Front End is a modem interface between TX/RX mixed-signal modules and digital signal processor (DSP). We can divide this block into two parts (see Figure 78). The first is the uplink (transmitting) path, which converts bit-stream from DSP into digital in-phase (I) and quadrature (Q) signals for TX mixed-signal module. The second part is the downlink (receiving) path, which receives digital in-phase (I) and quadrature (Q) signals from RX mixed-signal module, performs FIR filtering and then sends results to DSP. Figure 78 illustrates interconnection around Baseband Front End. In the figure the shadowed blocks compose Baseband Front End. To enhance the capability of data processing of mobile phone and base station, the Enhanced Data for GSM Evolution (EDGE), which used 8PSK Modulation rather than GMSK Modulation in GSM system may provide the triple data transmission rate of 384 kbps for system to supply the solution of voice, data, Internet linkage, and other kinds of mutual linkage, while 3bits per symbols in 8PSK Modulation and 1 bit per symbol in GMSK Modulation. The uplink path is mainly composed of GMSK Modulator or 8PSK Modulator and uplink parts of Baseband Serial Ports, and the downlink path is mainly composed of RX digital FIR filter and downlink parts of Baseband Serial Ports. Baseband Serial Ports is a serial interface used to communicate with DSP. In addition, there is a set of control registers in Baseband Front End that is intended for control of TX/RX mixed-signal modules, inclusive of several compensation circuit :calibration of I/Q DC offset, I/Q Quadrature Phase Compensation and I/Q Gain Mismatch of uplink analog-to-digital (D/A) converters as well as I/Q Gain Mismatch for downlink digital-to-analog (A/D) converters in TX/RX mixed-signal modules. The timing of bit streaming through Baseband Front End is completely under control of TDMA timer. Usually only either of uplink and downlink paths is active at one moment. However, both of the uplink and downlink paths will be active simultaneously when Baseband Front End is in loopback mode. When either of TX windows in TDMA timer is opened, the uplink path in Baseband Front End will be activated. Accordingly components on the uplink path such as GMSK Modulator or 8PSK Modulator will be powered on, and then TX mixed-signal module is also powered on. The subblock Baseband Serial Ports will sink TX data bits from DSP and then forward them to GMSK Modulator or 8PSK Modulator. The outputs from GMSK Modulator or 8PSK Modulator are sent to TX mixed-signal module in format of I/Q signals. Finally D/A conversions are performed in TX mixed-signal module and the output analog signal is output to RF module. Additionally, 8PSK Modulation intrinsically extends the bursts window and reports in 8MVD (8PSK Modulation Valid) in BFE_STA status register. Similarly, while either of RX windows in TDMA timer is opened, the downlink path in Baseband Front End will be activated. Accordingly components on the downlink path such as RX mixed-signal module and RX digital FIR filter are then powered on. First A/D conversions are performed in RX mixed-signal module, and then the results in format of I/Q signals are sourced to Low Pass Filtering with different bandwidth (Narrow one about Fc = 90 khz, Wide one about FC = 110khz), Interference Detection Circuit to determine which Filter to be used by judging receiving power on current burst, Additionally, “I/Q Compensation Circuit” is an option in data path for modifying Receiving I/Q pair gain mismatch.. Finally the results will be sourced to DSP through Baseband Serial Ports. 467/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 Figure 78 Block Diagram Of Baseband Front End 10.1 10.1.1 Baseband Serial Ports General Description Baseband Front End communicates with DSP through the sub block of Baseband Serial Ports. Baseband Serial Ports interfaces with DSP in serial manner. This implies that DSP must be configured carefully in order to have Baseband Serial Ports cooperate with DSP core correctly. If downlink path is programmed in bypass-filter mode (NOT bypass-filter loopback mode), behavior of Baseband Serial Ports will be completely be different from that in normal function mode. The special mode is for testing purpose. Please see the subsequent section of Downlink Path for more details. TX and RX windows are under control of TDMA timer. Please refer to functional specification of TDMA timer for the details on how to open/close a TX/RX window. Opening/Closing of TX/RX windows have two major effects on Baseband Front End : power on/off of corresponding components and data souring/sinking. It is worth noticing that Baseband Serial Ports is only intended for sinking TX data from DSP or sourcing data to DSP. It does not involve power on/off of TX/RX mixed-signal modules. As far as downlink path is concerned, if a RX window is opened by TDMA timer Baseband Front End will have RX mixed-signal module proceed to make A/D conversion, two parallel RX digital filter proceed to performiltering and Baseband Serial Ports be activated to source data from RX digital filter to Master DSP while Power Measurement through Baseband Serial Ports to Slave DSP no matter the data is meaningful or not However, the interval between the moment that 468/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 RX mixed-signal module is powered on and the moment that data proceed to be dumped by Baseband Serial Ports can be well controlled in TDMA timer. Let us denote RX enable window as the interval that RX mixed-signal module is powered on and denote RX dump window as the interval that data is dumped by Baseband Serial Ports. If the first samples from RX digital filter desire to be discarded, the corresponding RX enable window must cover the corresponding RX dump window. Note that RX dump windows always win over RX enable windows. It means that a RX dump window will always raise a RX enable window. RX enable windows can be raised by TDMA timer or by programming RX power-down bit in global control registers to be ‘0’. This is useful in debugging environment. Similarly, a TX dump window refers to the interval that Baseband Serial Ports sinks data from DSP on uplink path and a TX enable window refers to the interval that TX mixed-signal module is powered on. A TX window controlled by TDMA timer involves a TX dump window and a TX enable window simultaneously. The interval between the moment that TX mixed-signal module is powered on and the moment that data proceed to be forwarded from DSP to GMSK or 8PSK modulator by Baseband Serial Ports can be well controlled in TDMA timer. TX dump windows always win over TX enable windows. It means that a TX dump window will always raise a TX enable window. TX enable windows can be raised by TDMA timer or by programming TX power-down bit in global control registers to be ‘0’. It is useful in debugging environment. Accordingly, Baseband Serial Ports are only under the control of TX/RX dump window. Note that if TX/RX dump window is not integer multiplies of bit-time it will be extended to be integer multiplies of bit-time. For example, if TX/RX dump window has interval of 156.25 bit-times then it will be extended to 157 bit-times in Baseband Serial Ports. For uplink path, if uplink path is enabled, then the bit BULEN (Baseband Up-Link Enable) will be ‘1’. Otherwise the bit BULEN will be 0. The MDSEL( Modulation Mode Select[3:0]) in TX_CONF control register needs to be latched in MDSEL shadow register according to the rising edge of TDMA Event Validate signal from TDMA controller, which used to indicate the modulation scheme selection between 8PSK or GMSK modulator for four transmit Burst. Generally there will at most 4 sequential Bursts, 1st Burst, 2nd Burst, 3rd Bursts, and 4th Bursts, which are not necessary to be all turn on in a burst sequence. The BTXEN1, BTXEN2, BTXEN3, BTXEN4 will be asserted prior to each Bursts, and their rising edge will update the Mode selection control bit to select appropriate Modulation type for current input data symbols in each bursts. Additionally, this Mode selection status for each bursts will be stored in BFE_STA status register, including MDSTS1(MoDulation mode StatuS1) , MDSTS2(MoDulation mode StatuS2), MDSTS3(MoDulation mode StatuS3), MDSTS4(MoDulation mode StatuS4), respectively.(Figure 79 Uplink Modulation Mode Selection Status Timing Diagram) During these 4 bursts valid period, the bit BULFS (Baseband Uplink Frame Sync) in BFE_STA status register will be ‘1’. Otherwise will be ‘0’. Meanwhile, uplink path will forward TX bit from DSP to GMSK modulator or 8PSK Modulation 469/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 MDSEL from APB Bus TDMA Event VAlidate MDSEL Shadow Register 4'b1111 MDSEL1 BULTXEN1 for 1st Burst MDSTS1 BULTXEN2 for 2nd Burst MDSTS2 BULTXEN3 for 3rd Burst MDSTS3 BULTXEN4 for 4th Burst MDSTS4 1st Burst BULFS 2nd Burst 3rd Burst 4th Burst Figure 79 Uplink Modulation Mode Selection Status Timing Diagram For downlink path, if BDLEN(Baseband DownLink Enable) is enabled, RX mixed-signal module will also be powered on. Similarly, once uplink path is enabled, TX mixed-signal module will also be powered on. Furthermore, enabling BDLFS(Baseband Down-Link FrameSync)Baseband Serial Ports for downlink path refers to dumping results from RX digital FIR filter to DSP. 10.1.2 Register Definitions BFE+0000h Bit 15 Base-band Common Control Register 14 13 12 11 10 9 8 7 BFE_CON 6 5 4 3 Name Type Reset 2 1 0 BCIE N R/W 0 This register is for common control of Baseband Front End. It consists of ciphering encryption control. BCIEN The bit is for ciphering encryption control. If the bit is set to ‘1’, XOR will be performed on some TX bits (payload of Normal Burst) and ciphering pattern bit from DSP, and then the result is forwarded to GMSK Modulator only. Meanwhile, Baseband Front End will generate signals to drive DSP ciphering process and produce corresponding ciphering pattern bits if the bit is set to ‘1’. If the bit is set to ‘0’, the TX bit from DSP will be forwarded to GMSK modulator directly. Baseband Front End will not activate DSP ciphering process. 0 Disable ciphering encryption. 1 Enable ciphering encryption. 470/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 BFE +0004h Bit 15 Name Type Reset 14 Base-band Common Status Register BFE_STA 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MDST MDST MDST MDST BULE BULE BULE BULE BULF BULF BULF BULF BDLF BDLE S1 N4 N3 N2 N1 S4 S3 S2 S1 S N S4 S3 S2 RO RO RO RO RO RO RO RO RO RO RO RO RO RO 0 0 0 0 0 0 0 0 0 0 0 0 0 0 This register indicates status of Baseband Front End This register indicates status of Baseband Front End. Under control of TDMA timer, Baseband Front End can be driven in several statuses. If downlink path is enabled, then the bit BDLEN will be ‘1’. Otherwise the bit BDLEN will be ‘0’. If downlink parts of Baseband Serial Ports is enabled, the bit BDLFS will be ‘1’. Otherwise the bit BDLFS will be ‘0’. If uplink path is enabled, then the bit BULEN will be ‘1’. Otherwise the bit BULEN will be 0. If uplink parts of Baseband Serial Ports is enabled, the bit BULFS will be ‘1’. Otherwise the bit BULFS will be ‘0’. Once downlink path is enabled, RX mixed-signal module will also be powered on. Similarly, once uplink path is enabled, TX mixed-signal module will also be powered on. Furthermore, enabling Baseband Serial Ports for downlink path refers to dumping results from RX digital FIR filter to DSP. Similarly, enabling Baseband Serial Ports for uplink path refers to forwarding TX bit from DSP to GMSK modulator. BDLEN stands for “Baseband DownLink Enable”. BULEN stands for “Baseband UpLink Enable”. BDLFS stands for “Baseband DownLink FrameSync”. BULFS stands for “Baseband UpLink FrameSync”. BDLEN 0 1 BDLFS 0 1 BULFS1 0 1 BULFS2 0 1 BULFS3 0 1 BULFS4 0 1 BULEN1 0 1 BULEN2 0 1 BULEN3 0 Indicate if downlink path is enabled. Disabled Enabled Indicate if Baseband Serial Ports for downlink path is enabled. Disabled Enabled Indicate if Baseband Serial Ports for uplink path is enabled in 1st burst Disabled Enabled Indicate if Baseband Serial Ports for uplink path is enabled in 2nd burst Disabled Enabled Indicate if Baseband Serial Ports for uplink path is enabled in 3rd burst Disabled Enabled Indicate if Baseband Serial Ports for uplink path is enabled in 4th burst Disabled Enabled Indicate if uplink path is enabled in 1st burst. Disabled Enabled Indicate if uplink path is enabled in 2nd burst. Disabled Enabled Indicate if uplink path is enabled in 3rd burst. Disabled 471/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 1 BULEN4 0 1 MDSTS1 0 1 MDSTS2 0 1 MDSTS3 0 1 MDSTS4 0 1 10.2 10.2.1 Enabled Indicate if uplink path is enabled in 4th burst. Disabled Enabled Indicate the current Modulation Mode Selection in 1st burst GMSK Modulation 8PSK Modulation Indicate the current Modulation Mode Selection in 2nd burst GMSK Modulation 8PSK Modulation Indicate the current Modulation Mode Selection in 3rd burst GMSK Modulation 8PSK Modulation Indicate the current Modulation Mode Selection in 4th burst GMSK Modulation 8PSK Modulation Downlink Path (RX Path) General Description On the downlink path, the sub-block between RX mixed-signal module and Baseband Serial Ports is RX Path. It mainly consists of two parallel digital FIR filter with programmable tap number, two sets of multiplexing paths for loopback modes, interface for RX mixed-signal module, Interference Detection Circuit, I/Q Gain Mismatch compensation circuit, and interface for Baseband Serial Ports. The block diagram is shown in Figure 80 Block Diagram of RX Path. While RX enable windows are open, RX Path will issue control signals to have RX mixed-signal module proceed to make A/D conversion. As each conversion is finished, one set of I/Q signals will be latched. There exists a digital FIR filter for these I/Q signals. The result of filtering will be dumped to Baseband Serial Ports whenever RX dump windows are opened. 472/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 RX Dump Window RX Enable Window Loopback Path bypass FIR BBRX Narrow Filter (Fc= 90khz) BBRX A/D BBRX I/Q Mismatch Comp CKT Loopback Path thru FIR BBRX Wide Filter (Fc= 110khz) BBRX Interference Detection Receiving I/Q Pair Master DSP RX Sports1 BBRX Baseband Serial Port PWR Measurement Output Slave DSP RX Sport1 Loopback Path from BBTX Figure 80 Block Diagram of RX Path 10.2.2 Comb Filter The comb filter which takes the 2-bit A/D converter as input, and output the 18-bit I/Q data words to the baseband receiving path. The system is designed as 48X over-sampling with symbol period 541.7 kHz, thus the data inputs are 26MHz 2-bit signal. The input 2-bit signals are formed in (sign, magnitude) manner; that is, total 3 values are permitted as input: (-1, 0, +1). The data path is mainly a decimation filter which contains the integration stages and the decimation stages. For a 3rd order design with 48X over-sampling, gain of the data path is 483 = 110592, which locates between 216 and 217. Thus the internal word-length must be set to 18-bit to avoid overflow in the integration process. 473/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 10.2.3 Compensation Circuit - I/Q Gain Mismatch In order to compensate I/Q Gain Mismatch , configure IGAINSEL(I Gain Selection) in RX_CON control register, the I over Q ratio can be compensate for 0.3 dB/step, totally 11 steps resulted in dynamic range up to +/-1.5dB. I A/D Q A/D 14 I/Q mismatch compensation 14 16 RX_filter 14 Figure 81 I/Q Mismatch Compensation Block Diagram The I/Q swap functionality can be setting “1” for SWAP(I/Q Swapping) in RX_CFG control register, which is used to swap I/Q channel signals from RX mixed-signal module before they are latched into RX digital FIR filter. It is intended to provide flexibility for I/Q connection with RF modules 10.2.4 Phase De-rotation Circuit Phase De-rotation Mode will usually turn on during FCB Detection for down conversion the wide spread receiving power to 67.7khz single tone. Two separate control for implement this mode on data path through NarrowFIR filter or WideFIR filter by setting ‘1’ to PHROEN_N(Phase Rotate Enable for NarrowFIR) or PHROEN_W(Phase Rotate Enable for WideFIR) in RX_CON control register, respectively. 10.2.5 Adaptive Bandwidth & Programmable Digital FIR Filter For the two parallel digital FIR Filter, the total tap number is programmable by FIRTPNO(FIR Tap number) in RX_CFG control register, which will configure the filter with different tap buffer depth. 10.2.5.1 Programmable tap & programmable Coefficient for FIR In order to satisfy the signal requirements in both of idle and traffic modes, two sets of coefficients must be provided for the RX digital FIR filter. Therefore, the RX digital FIR filter is implemented as a FIR filter with programmable coefficients which can be accessed on the APB bus. The coefficient number can be programmable, range from from 1~31. Each coefficient is ten-bit wide and coded in 2’s complement. Take 21 Tap Coefficient for example, based on assumption that the FIR filter has symmetric coefficients, only 11 coefficients are implemented as programmable registers to save gate count. Denoting these digital filter coefficients as RX_RAM0_CS0 ~ RX_RAM0_CS11(RX_RAM0 Coefficient Set 0~11), and these tap registers for I/Q channel signals as I/QTAPR [0:20], then the RX digital FIR filtering can be represented as the following equation: 474/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 11 20 = BDLDFCR [11] * ITAPR [11] + ∑ BDLDFCR [ i ] * ( ITAPR [ i ] + ITAPR [ 20 − i ]) I out ( m ) = ∑ BDLDFCR [ i ] * ITAPR [ i ] i =0 i =0 at time n + 4m 20 11 Q out ( m ) = ∑ BDLDFCR [ i ] * QTAPR [ i ] = BDLDFCR [11] * QTAPR [11] + ∑ BDLDFCR [ i ] * ( QTAPR [ i ] + QTAPR [ 20 − i ]) i =0 i =0 at time n + 4m BDLDFCR [ i ] = BDLDFCR [ 20 − i ], i = 0 ,1,...,11 where ITAPR [0] and QTAPR [0] are the latest samples for I- and Q-channel respectively and assume I out (0), Qout (0) are obtained based on the content of tap registers at time moment n. From the equation above it follows that the digital RX FIR filter will produce one output every four data conversions out of A/D converters. That is, filtering and decimation are performed simultaneously to achieve low power design. However, different “Coefficient Set ID“(CS ID) will be dump to Slave DSP RX buffer to represent the current selecting of coefficient Set from either 2 ROM table or 2 set of programmable RAM table according to different burst mode, while ROM table are fixed coefficient and RAM table can be programmed through 2set of 16 control register (RX_RAM0_CS0~ RX_RAM_CS15, (RX_RAM1_CS0~RX_RAM1_CS15). Generally, CSID = 0 represent ROM table selection, while CSID 2~ CSID 15 represent RAM table selection. Please be noted that the total coefficient number in a RAM table should be greater than half of the FIRTPNO(total FIR Tap number) and smaller than half of maximum tap number(15) since the FIR function in symmetric behavior. Additionally, the data sequence of two parallel FIR filter output will dump to Master DSP RX buffer in following order : “I channel output from Narrow FIR”=> “ I channel output from Wide FIR””=>“Q channel output from Narrow FIR=>” Q channel output from Wide FIR. 10.2.5.1.1 Coefficient Set Selection The Coefficient Set used for digital FIR can be changed during different burst mode switching. For example, during Normal Burst while no FB_STROBE (Frequency Burst Strobe, comes from TDMA controller) assertion, defined as “State B”, “Coefficient Set ID” ( CS ID) selection for both Narrow/Wide filter can be configured by ST_B_WCOF_SEL(State B Wide FIR Coefficient Selection) and “ST_B_NCOF_SEL” (State B Narrow FIR Coefficient Selection) on RX_FIR_CSID_CON control register, respectively. Usually during State B, Layer 1 software will select RAM table confidence from either RAM0 or RAM1 table in condition I for Narrow FIR and Wide FIR, respectively. The CS ID for both Narrow / Wide FIR filter be stored at Slave DSP RX buffer once TDMA trigger RX interrupt to DSP..ST_A_NCOF_SEL” (State A Narrow FIR Coefficient Selection) on RX_FIR_CSID_CON control register. During FCB detection, MCU will notice TDMA controller by assertion FB_STROBE, defined as “StateA”. “Coefficient Set ID” ( CS ID) selection for both Narrow/Wide filter can be configured by ST_A_WCOF_SEL(State A Wide FIR Coefficient Selection) and “ST_A_NCOF_SEL” (State A Narrow FIR Coefficient Selection) on RX_FIR_CSID_CON control register, respectively. Usually during State B, Layer 1 software will select CS ID 2 and CSID 3 from either ROM0 or ROM1 table or RAM0 or RAM1 table in Condition II for Narrow FIR and Wide FIR, respectively. 10.2.5.2 Interference Detection Circuit for Adaptive Bandwidth Scheme Used to compare the power of Co-channel Interference and Adjacent-channel Interference for determine if WideFIR filter is needed rather than default NarrowFIR filter. Two parallel path of power measurement for evaluating Co-channel effect or Adjacent Channel Effect by analyzing power after High Pass Filter(HPF) or Band Pass Filter(BPF), respectively. If Co-channel effect is worse than Adjacent Channel effect, WideFIR filter is needed. 475/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 The power measurement is accumulate I/Q Root Mean Square (RMS) power over the whole RX burst window, while exact accumulation period within the burst can be adjusted the starting point offset and duration length.. The “starting point Offset” and be configured by “RXID_PWR_OFF[7:0]” ( RX Interference Detection Power Starting Point Offset) and duration period by “ RXID_PWR_PER[7:0]”(RX Interference Detection Power Duration Period) in RX_PM_CON control register, while default value for starting offset is 11 and duration period is 141. The two accumulated power measurement output for Co-channel and Adjacent-channel will be dump to Slave DSP RX buffer alternatively at the end of the duration period within a burst. However, if the duration period is longer than the RX Dump Window, the accumulated measurement output will be dump out at falling edge of RX_DUMP_Window rather than the end of configured duration priod. Additionally, the power measurement data sequence at Slave DSP RX buffer will be “Coefficient Set ID for NarrowFIR filter”=> “Coefficient Set ID for WideFIR filter”=>“Power output of HPF(Co-channel)=>”Power output of BPF(Adjacent-channel), while the coefficient Set ID (CSID) is for DSP debug purpose. The power result can be further scale down by control the PWR_SHFT_NO( power right Shift Number) in RX_CON control register. E.g. set to “1” will divied the power output by two. 10.2.6 Debug Mode 10.2.6.1 Normal Mode bypass Filter By setting “1” for BYPFLTR(Bypass Filter) in RX_CFG control register, the ADC outputs out of RX mixed-signal module will be directed into Baseband Serial Ports directly without through FIR. Limited by bandwidth of the serial interface between Baseband Serial Ports and DSP, only ADC outputs which are from either I-channel or Q-channel ADC can be dumped into DSP. Both I- and Q-channel ADC outputs cannot be dumped simultaneously. Which channel will be dumped is controlled by the register bit SWAP of the control register RX_CFG when downlink path is programmed in “Bypass RX digital FIR filter” mode. See register definition below for more details. The mode is for measurement of performance of A/D converters in RX mixed-signal module. 10.2.6.2 TX-RX Digital Loopback Mode (Debug Mode) In addition to normal function, there are two loopback modes in RX Path. One is bypass-filter loopback mode, and the other is through-filter loopback mode. They are intended for verification of DSP firmware and hardware. The bypass-filter loopback mode refers to that RX digital FIR filter is not on the loopback path. However, the through-filter loopback mode refers to that RX digital FIR filter is on the loopback path, while “ thru-Filter Loopback Mode” can be configured by setting “2’b10” for BLPEN(Baseband Loopback Enable) or “bypass-Filter Loopback Mode” by setting “ 2’b01” for BLPEN in RX_CON control register. 10.2.7 10.2.7.1 Register Definitions APB Register BFE +0010h Bit 15 14 RX Configuration Register 13 12 11 10 9 RX_CFG 8 7 6 Name FIRTPNO Type Reset R/W 000000 476/599 5 4 3 2 1 0 BYPF SWA LTR P R/W R/W 0 0 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 This register is for configuration of downlink path, inclusive of configuration of RX mixed-signal module and RX path in Baseband Front End. SWAP This register bit is for control of whether I/Q channel signals need to swap before they are inputted to Baseband Front End. It provides flexibility flexible of connection of I/Q channel signals between RF module and baseband module. The register bit has another purpose when the register bit “BYPFLTR” is set to 1. Please see description for the register bit “BYPFLTR”. 0 I- and Q-channel signals are not swapped 1 I- and Q-channel signals are swapped BYPFLTR Bypass RX FIR filter control. The register bit is used to configure Baseband Front End in the state called “Bypass RX FIR filter state” or not. Once the bit is set to ‘1’, RX FIR filter will be bypassed. That is, ADC outputs of RX mixed-signal module that are has 14-bit resolution and at sampling rate of 571 kHz can be dumped into DSP by Baseband Serial Ports and RX FIR filtering will not be performed on them. 0 Not bypass RX FIR filter 1 Bypass RX FIR filter FIRTPNO RX FIR filter tap no. select. This control register will control the two parallel digital filter with different tap buffer depth since the FIR function in symmetric behavior. The maximum tap number is 31, minimum is 1., ODD number only. BFE+0014h Bit 15 RX Control Register 14 13 12 11 10 RX_CON 9 8 7 6 5 Name PWR_SHFT_NO IGAINSEL Type Reset R/W 0000 R/W 0000 4 3 2 PH_R PH_R OEN_ OEN_ N W R/W R/W 0 0 1 0 BLPEN R/W 00 This register is for control of downlink path, inclusive of control of RX mixed-signal module and RX path in Baseband Front End module. BLPEN The register field is for loopback configuration selection in Baseband Front End. 00 Configure Baseband Front End in normal function mode 01 Configure Baseband Front End in bypass-filter loopback mode 10 Configure Baseband Front End in through-filter loopback mode 11 Reserved PH_ROEN_W Enable for I/Q pair Phase De-rotation in Wide FIR Data Path, 0 Disable Phase De-rotation for I/Q pair 1 Enable Phase De-rotation for I/Q pair PH_ROEN_N Enable for I/Q pair Phase De-rotation in Narrow FIR Data Path, 0 Disable Phase De-rotation for I/Q pair. 1 Enable Phase De-rotation for I/Q pair IGAINSEL RX I data Gain Compensation Select. 0.3dB/step, totally 11 steps and dynamic range up to +/-1.5dB for 0000 compensate 0dB for I/Q 0001 compensate 0.3dB for I/Q 0010 compensate 0.6dB for I/Q 0011 compensate 0.9dB for I/Q 477/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 0100 compensate 1.2dB for I/Q 0101 compensate 1.5dB for I/Q 1001 compensate –0.3dB for I/Q 1010 compensate -0.6dB for I/Q 1011 compensate –0.9dB for I/Q 1100 compensate –1.2dB for I/Q 1101 compensate –1.5dB for I/Q Default no compensation for I/Q PWR_SHFT_NO Power measuring Result Right Shift Number. The Power level measurement result can be right shift from 0 to 16 bits. RX Interference Detection Power Measurement Control Register BFE+0018h Bit Name Type Reset 15 14 13 12 11 10 RXID_PWR_PER R/W 8D 9 8 7 6 5 RX_PM_CON 4 3 2 RXID_PWR_OFF R/W b 1 0 RXID_PWR_OFF RX Interference Detection Power Measurement Starting Offset. Setting this register will delay the starting time of Interference Detection Power Measurement in symbol time unit. Maximum value is 156, while default value is 11 (0xB). RXID_PWR_PER RX Interference Detection Power Measurement Accumulation Period. By setting this control register will determine the length of accumulation duration for power Measurement. Minimum value is 0, Maximum value is 156, while default value is 141(0x8D). Please notice that RXID_PWR_OFF + RXID_PWR_PER should less than 154 due to hardware implementation limitation. BFE+001Ch Bit Name Type Reset 15 RX_FIR_CSID_C ON RX FIR Coefficient Set ID Control Register 14 13 12 ST_A_NCOF_SEL R/W 0000 11 10 9 8 7 6 5 4 ST_B_NCOF_SEL R/W 0010 3 2 1 0 ST_B_WCOF_SEL R/W 0011 These three set of Coefficient Set ID will be dump to slave DSP RX Buffer for indicating the current selection of FIR coefficient from either RAM or ROM table, while CSID= 0 represents ROM table selection, and CSID2~CSID15 represent RAM table selection. ST_B_WCOF_SEL State B Coefficient Set Selection for Wide FIR. ST_B_NCOF_SEL State B Coefficient Set Selection for Narrow FIR. ST_A_NCOF_SEL State A Coefficient Set Selection for Narrow FIR. BFE +0070h Bit Name Type Reset 15 14 RX RAM0Coefficient Set 0Register 13 12 11 10 9 8 478/599 7 RX_RAM0_CS0 6 5 4 RX_RAM0_CS0 R/W 000000000 3 2 1 0 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 This register is 1st of the 16 coefficient in RAM0 table, Coefficient Set ID 2 or 4. The content is coded in 2’s complement. That is, its maximum is 255 and its minimum is –256, while the total coefficient number in this Coefficient Set has to be greater than half of TAPNO(programmable Tap no.) and smaller than half of maximum tap no(15). Register Address Register Function Acronym BFE +0070h RX RAM0Coefficient Set 0 Register RX_RAM0_CS0 BFE +0074h RX RAM0Coefficient Set 1 Register RX_RAM0_CS1 BFE +0078h RX RAM0Coefficient Set 2 Register RX_RAM0_CS2 BFE +007Ch RX RAM0Coefficient Set 3 Register RX_RAM0_CS3 BFE +0080h RX RAM0Coefficient Set 4 Register RX_RAM0_CS4 BFE +0084h RX RAM0Coefficient Set 5 Register RX_RAM0_CS5 BFE +0088h RX RAM0Coefficient Set 6 Register RX_RAM0_CS6 BFE +008Ch RX RAM0Coefficient Set 7 Register RX_RAM0_CS7 BFE +0090h RX RAM0Coefficient Set 8 Register RX_RAM0_CS8 BFE +0094h RX RAM0Coefficient Set 9 Register RX_RAM0_CS9 BFE +0098h RX RAM0Coefficient Set 10 Register RX_RAM0_CS10 BFE +009Ch RX RAM0Coefficient Set 11Register RX_RAM0_CS11 BFE +00a0h RX RAM0Coefficient Set 12Register RX_RAM0_CS12 BFE +00a4h RX RAM0Coefficient Set 13Register RX_RAM0_CS13 BFE +00a8h RX RAM0Coefficient Set 14 Register RX_RAM0_CS14 BFE +00aCh RX RAM0Coefficient Set 15 Register RX_RAM0_CS15 BFE +0020h RX RAM1 Coefficient Set 0 Register Bit 15 Name Type Reset 14 13 12 11 10 9 8 7 6 5 4 3 RX_RAM1_CS0 R/W 000000000 RX_RAM1_CS0 2 1 0 This register is 1st of the 16 coefficient in RAM1 table, Coefficient Set ID 2 or 4. The content is coded in 2’s complement. That is, its maximum is 255 and its minimum is –256, while the total coefficient number in this Coefficient Set has to be greater than half of TAPNO(programmable Tap no.) and smaller than half of maximum tap no(15). Register Address Register Function Acronym BFE +0020h RX RAM1 Coefficient Set 0 Register RX_RAM1_CS0 BFE +0024h RX RAM1 Coefficient Set 1Register RX_RAM1_CS1 BFE +0028h RX RAM1 Coefficient Set 2 Register RX_RAM1_CS2 BFE +002Ch RX RAM1 Coefficient Set 3 Register RX_RAM1_CS3 BFE +0030h RX RAM1 Coefficient Set 4 Register RX_RAM1_CS4 BFE +0034h RX RAM1 Coefficient Set 5 Register RX_RAM1_CS5 BFE +0038h RX RAM1 Coefficient Set 6 Register RX_RAM1_CS6 BFE +003Ch RX RAM1 Coefficient Set 7 Register RX_RAM1_CS7 BFE +0040h RX RAM1 Coefficient Set 8 Register RX_RAM1_CS8 BFE +0044h RX RAM1 Coefficient Set 9 Register RX_RAM1_CS9 BFE +0048h RX RAM1 Coefficient Set 10 Register RX_RAM1_CS10 479/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 BFE +004Ch RX RAM1 Coefficient Set 11 Register RX_RAM1_CS11 BFE +0050h RX RAM1 Coefficient Set 12 Register RX_RAM1_CS12 BFE +0054h RX RAM1 Coefficient Set 13 Register RX_RAM1_CS13 BFE +0058h RX RAM1 Coefficient Set 14 Register RX_RAM1_CS14 BFE +005Ch RX RAM1 Coefficient Set 15 Register RX_RAM1_CS15 BFE+00B0h Bit 15 Name Type Reset RX Interference Detection HPF Power Register 14 13 12 11 10 9 8 7 6 RX_PWR_HPF R/O 0000000000000000 5 RX_HPWR_ST S 4 3 2 1 0 This register is for read the power measurement result of the HPF interference detection filter. RX_PWR_HPF Value of the power measurement result for the outband interference detection. BFE+00B4h Bit Name Type Reset 15 RX Interference Detection BPF Power Register 14 13 12 11 10 9 8 7 6 RX_PWR_BPF R/O 0000000000000000 5 RX_BPWR_STS 4 3 2 1 0 This register is for read the power measurement result of the BPF interference detection filter. RX_PWR_BPF Value of the power measurement result for the inband interference detection 10.3 Uplink Path (TX Path) 10.3.1 General Description The purpose of the uplink path inside Baseband Front End is to sink TX symbols, from DSP, then perform GMSK modulation or 8PSK Modulation on them, then perform offset cancellation on I/Q digital signals, and finally control TX mixed-signal module to make D/A conversion on I/Q signals out of GMSK Modulator or 8PSK Modulator with offset cancellation. Accordingly, the uplink path is composed of uplink parts of Baseband Serial Ports, GSM Encryptor, GMSK Modulator, 8PSK Modulator and several compensation circuit including I/Q DC offset, I/Q Quadrature Phase Compensation, and I/Q Gain Mismatch. The block diagram of uplink path is shownas followed. I/Q GSM TX MixedSignal Module GMSK Modulator 1-bit TX GSM Encryptor Offset Cancellation I/Q 8PSK Modulator 1-bit TX Uplink Patrts Of Baseband Serial Ports 1-bit TX DSP 3-bit TX Symbol Figure 82 Block Diagram Of Uplink Path 480/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 On uplink path, the content of a burst, including tail bits, data bits, and training sequence bits is sent from DSP. DSP outputs will be t Translated by either GMSK Modulator or 8PSK Modulator. The Modulation Mode Selection is controlled by MDSEL1 (Modulation Mode Select1) MDSEL2, MDSEL3, MDSEL4 in TX_CFG control register, and these translated bits after modulation will become I/Q digital signals with certain latency. TDMA timer having a quarter-bit timing accuracy gives the timing windows for uplink operation. Uplink operation is controlled by TX enable window and TX dump window of TDMA timer. Usually, TX enable window is opened earlier than TX dump window. When TX enable window of TDMA timer is opened, uplink path in Baseband Front End will power-on GSK TX mixed-signal module and thus drive valid outputs to RF module. However, uplink parts of Baseband Serial Ports still do not sink data from DSP through the serial interface between Baseband Serial Ports and DSP until TX dump window of TDMA timer is opened. 10.3.2 10.3.2.1 Compensation Circuit Quadrature Phase For 8PSK Modulation, in order to improve the EVM performance, use PHSEL[2:0](Phase Select) in TX_CFG control register to compensate the quadrature phase. 6 steps, 1degree/step, up to +/3 degree dynamic range. 10.3.2.2 DC offset Cancellation Offset cancellation will be performed on these I/Q digital signals to compensate offset error of D/A converters (DAC) in TX mixed-signal module. Finally the generated I/Q digital signals will be input to TX mixed-signal module that contains two DAC for I/Q signal respectively. 10.3.3 Auxiliary Calibration Circuit - 540khz Sine Tone Generator By setting ‘1’ to SGEN(Sine Tone Generation) in TX_CFG control register, the BBTX output will become 540khz single sine tone, which is used for Factory Calibration scheme for Mixed Signal Low Pass Filter Cut-off Frequency Accuracy. 10.3.4 GSM Encryptor When uplink parts of Baseband Serial Ports pass a TX symbol to GSM Encryptor, GSM Encryptor will perform encryption on the TX symbol if set ‘1’ to BCIEN(Baseband Ciphering Encryption) in BFE_CON register. Otherwise, the TX symbol will be directed to GMSK modulator directly. 10.3.5 Modulation 10.3.5.1 GMSK Modulation GMSK Modulator is used to convert bit stream of GSM bursts into in-phase and quadrature-phase outputs by means of GMSK modulation scheme. It consists of a ROM table, timing control logic and some state registers for GMSK modulation scheme. GMSK Modulator is activated when TX dump window is opened. There is latency between assertion of TX dump window and the first valid output of GMSK Modulator. The reason is because the bit rate of TX symbols is 270.833 KHz and the output rate of GMSK Modulator is 4.333 MHz, and therefore timing synchronization is necessary between the two rates. 481/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 Additionally, in order to prevent phase discontinuity in between the multiple-burst Mode, the GMSK modulator will output continuous 67.7khs sine tone outside the burst once RX DAC Enable window is still asserted. Once RX DAC Enable window is disserted, GMSK modulator will park at DC level. 10.3.5.2 8PSK Modulation 8PSK Modulator is used to convert bit stream of EDGE bursts into basically 8 phase I/Q pair output by means of 8PSK modulation scheme. It consists of ROM table, timing control logic and some state registers for 8PSK modulation scheme. The conversion is based on 5 sequential symbol and performed moving average from the ROM table lookup. 8PSK Modulator is activated when TX dump window is opened. There is one clock delay between assertion of TX dump window and the first valid output of 8PSK Modulator. The reason is because the bit rate of TX symbols is 270.833 KHz and the output rate of 8PSK Modulator is 4.333 MHz, and therefore timing synchronization is necessary between the two rates. 10.3.5.2.1 8PSK Ramp Profile During 8PSKModulation, there will be 3 Ramp Profile to select to choose the BBTX I/Q output during the guard period, where the DAC_ON is asserted while TX_WINDOW is de-asserted. This control register is an option to adjust the transmitter performance on “Modulation Transient Spectrum” requirement of ETSI SPEC if different companion Power Amplifier solution is chosen By setting RPSEL (Ramp Profile Select) in TX_CFG control register to ‘0’will configured 8PSK Modulator to Ramp Profile I and I/Q output will be about 50 kHz Sine-tone before the first rising edge of BULFS, after the last falling edge of BULFS, and in between the bursts. For Ramp Profile II, BBTX I/Q output will be quiescent low DC (null-DC) level during the guard period. For Ramp Profile III, initial guard period will be 50 kHz sine-tone, while the reset guard period will be null-DC level. BTXEN BULFS Ramp Profile I Ramp Profile II Ramp Profile III Figure 83 Ramp Profile I/II/III in 8PSK Modulation for Multi-Bursts configuration.. 10.3.5.3 I/Q Swap By setting ‘1’ to IQSWP in TX_CFG control register, phase on I/Q plane will rotate in inverse direction. This option is to meet the different requirement form RF chip regarding I/Q plane. This control signal is for GMSK Modulation only. 482/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 10.3.5.4 Modulation Output Latency Adjustment For Multiple bursts, there maybe are consecutive bursts with different modulation mode. (E.g. switch GMSK to 8PSK or vice versa). However, there are about 8 to 10 QB output latencies for either GMSK/8PSKmodulation output. In order to match the transition timing of power ramp control in the power amplifier outside the baseband chip, we have to precisely control the SW_QBCNT (modulation Switching Quarter Bit CouNT) in TX_CFG control register. , which will program the mode switching timing in QB count unit during the inter-slot period. Normally the inter-slot period is about 33 QB Count, and the default value to switch the modulation mode is 24 QB count (8 QB count after the middle point) Additionally, by programming GMSK_DTAP_SYM(GMSK Delay Tap) in TX_CFG and GMSK_DTAP_QB in TX_CON control register, the output latency for GMSK modulation output can be adjust to compensate the offset between GMSK/8PSK modulator. The GMSK_DTAP_SYM adjust the output latency in symbol time(3.69us), while GMSK_DTA_QB adjust in Quarter Bit(QB) Time ( 0.92us).Default value is delay 1 symbol ( 3.69us) of GMSK modulator output. 10.3.5.5 Modulation Mode Switching By setting ‘1’ to INTEN(Interpolation Enable) in TX_CFG control register, if two consecutive bursts belongs to 8PSK Modulation and GMSK Modulation, or vice versa, 32 steps interpolation between two Modulator outputs for 4quater bit long in guard period.. 10.3.5.6 Debug Mode 10.3.5.6.1 Modulation Bypass Mode For DSP debug purpose, set both ‘1’ for MDBYP(Modulator Bypass) in TX_CFG control register and BYPFLR(Bypass RX Filter) in RX_CFG control register for directly loopback DSP 16-bits data ( 10bits valid data plus sign or zero extension) through DAC only. 10.3.5.6.2 Force GMSK/8PSK Modulator turn on By setting ‘1’ to APNDEN(Append Enable) bit in TX CFG control register, both GMSK and 8PSK modulator will park on constant DC level during the non-burst period, while the I/Q pair output phase maybe discontinuous since both modulator will be reset at the beginning of the burst. However, the reset of the modulator will be helpful for the debugging purpose. 10.3.6 Register Definitions BFE +0060h Bit Name Type Reset 15 TX Configuration Register 14 13 GMSK_DTAP _SYM R/W 00 12 11 10 9 TX_CFG 8 SW_QBCNT RW 18 7 6 5 4 3 MDBY ALL_10_EN SGEN INTEN P RW R/W R/W R/W 00 0 0 0 2 1 RPSEL R/WR/W 00 0 APND EN R/W 0 This register is for configuration of uplink path, inclusive of configuration of TX mixed-signal module and TX path in Baseband Front End. APNDEN Appending Bits Enable.(For DSP digital loopback debug mode) The register bit is used to control the ending scheme of GPRS Mode GMSK modulation only. 483/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 Suitable for GPRS /EDGE mode. If a TX enable window contains several TX dump window, then GMSK modulator will still output in the intervals between two TX dump window and all 1’s will be fed into GMSK modulator. In the other word, mainly used PA to perform the power ramp up/down, while Modulator output low amplitude sinewave. Note that when the bit is set to ‘0’, the interval between the moment at which TX enable window is activated and the moment at which TX dump window is activated must be multiples of one bit time. 1 Suitable for GSM only. After a TX dump window, GMSK modulator will only output for some bit time. RPSEL Ramp Profile Select for 8PSK Modulation. The register bit is used to select either Ramp Profile I / Ramp Profile II for EDGE Mode 8PSK Modulation only. 0 Ramp Profile I. Generate 50Khz sine tone during the guard period among BBTX bursts by repeated input pattern [7 7 7 7] 1 Ramp Profile II. Generate null DC I/Q output during guard period among BBTX bursts 2 Reserved 3 Ramp Profile III , Generate 50 kHz sine tone after DAC_ON asserted and before TX_WIDNOW asserted if 1st burst is 8PSK modulation, while the reset guard period always output null DC I/Q output. If the 1st burst is GMSK modulation, the I/Q output will be always null DC as Ramp Profile II. INTEN Interpolation Enable. During Multi-bursts Mode, if two consecutive bursts belongs to 8PSK Modulation and GMSK Modulation, and vise versa or vice versa, set this bit to select either takes 32 steps interpolation between two Modulator outputs in guard period.. 0 Regular Transition Mode. 1 Interpolation Transition Mode. MDBYP Modulator Bypass (For DSP Debug Mode) Select. The register bit is used to select the bypass mode for I/Q pair outputs bypassed both the GMSK/8PSK modulator 0 Regular Modulation Mode 1 Bypass Modulator Mode (DSP Debug Mode). SGEN SineTone Generator Enable.(For Factory Calibration Purpose). The register bit is used to select the TX modulator output switch to 540 kHz Sine Tone. 0 BBTX output from regulator modulator output. 1 BBTX output switch to 540 kHz sine Tone ALL_10GEN For Debug mode of BBTX. Generate all 1’s or zero’s input during BBTX valid burst. For GMSK modulation, set 2’b1 or 2’b10 will generate 67.7 kHz sine tone, while 8PSK modulator will generate 50khz sine tone. Default value 2’b00 is normal mode. 0 Normal Mode, regular modulator input from Slave DSP TX Buffer. 1 Debug Mode, All zero’s input pattern generated; GMSK modulator will generate 67.7 kHz sine tone. 8PSK modulator will generate 50 kHz sine tone. 2 Debug Mode All 1’s input pattern generated; GMSK modulator will generate 67.7 kHz sine tone. 8PSK modulator will generate 50 kHz sine tone. SW_QBCNT Control the mode switching timing in the inter-slot period in Quarter Bit Count for modulation mode switching in multiple bursts. Normally the inter-slot period is about 33 QB Count, and the default value to switch the modulation mode is 24 QB count (8 QB count after the middle point). Program range from “5~31”, while default value is 24. GMSK_DTAP_SYM Control the GMSK modulator output latency in symbol time (3.69us/symbol) in order to match the output latency offset between 8PSK /GMSK modulator 0 Delay 1 TAP for GMSK modulator output 0 484/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 1 2 No delay for GMSK modulator output Delay 2 TAP for GMSK modulator output BFE +0064h Bit Name Type Reset 15 14 TX Control Register 13 12 GMSK_DTAP _QB R/W 00 11 10 TX_CON 9 8 PHSEL R/W 0000 7 6 5 4 3 2 MDSE MDSE MDSE MDSE L4 L3 L2 L1 R/W R/W R/W R/W 0 0 0 0 1 0 IQSW P R/W 0 This register is for control of uplink path, inclusive of control of TX mixed-signal module and TX path in Baseband Front End. IQSWP The register bit is for control of I/Q swapping. When the bit is set to ‘1’, phase on I/Q plane will rotate in inverse direction. Moreover, this register is double buffered by EVENT_VALIDATE. 0 I and Q are not swapped. 1 I and Q are swapped. MDSEL1 Modulation Mode Select for 1st Burst. The register bit is used to select either GMSK or 8PSK Modulation for GSM/GPRS mode or EDGE mode. 0 GMSK Modulation for GSM/GPRS mode. 1 8PSK Modulation for EDGE mode. MDSEL2 Modulation Mode Select for 2nd Burst. The register bit is used to select either GMSK or 8PSK Modulation for GSM/GPRS mode or EDGE mode. 0 GMSK Modulation for GSM/GPRS mode. 1 8PSK Modulation for EDGE mode. MDSEL3 Modulation Mode Select for 3rd Burst. The register bit is used to select either GMSK or 8PSK Modulation for GSM/GPRS mode or EDGE mode. 0 GMSK Modulation for GSM/GPRS mode. 1 8PSK Modulation for EDGE mode. MDSEL4 Modulation Mode Select for 4th Burst. The register bit is used to select either GMSK or 8PSK Modulation for GSM/GPRS mode or EDGE mode. 0 GMSK Modulation for GSM/GPRS mode. 1 8PSK Modulation for EDGE mode. PHSEL Quadrature phase compensation select 0000: 0 degree compensation. 0001: 1 degree compensation. 0010: 2 degree compensation. 0011: 3 degree compensation. 0100: 4 degree compensation. 0101: 5 degree compensation. 1010: -5 degree compensation. 1011: -4 degree compensation. 1100: -3 degree compensation. 1101: -2 degree compensation. 1110: -1 degree compensation. 1111: 0 degree compensation. 485/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 GMSK_DTAP_QB Control the GMSK modulator output latency in Quarter Bit(QB) Time (0.92us/QB) in order to match the output latency offset between 8PSK /GMSK modulator 0 No Delay GMSK modulator output 1 Delay 1QB for GMSK modulator output 2 Delay 2 QB for GMSK modulator output 3 Delay 3QB for GMSK modulator output BFE +0068h Bit 15 OFF_ Name TYP Type R/W Reset 0 14 TX I/Q Channel Offset Compensation Register 13 12 11 10 9 8 7 6 5 TX_OFF 4 3 2 OFFQ[5:0] OFFI[5:0] R/W 000000 R/W 000000 1 0 The register is for offset cancellation of I-channel DAC in TX mixed-signal module. It is for compensation of offset error caused by I/Q-channel DAC in TX mixed-signal module. It is coded in 2’s complement, that is, with maximum 31 and minimum –32. OFFI Value of offset cancellation for I-channel DAC in TX mixed-signal module OFFQ Value of offset cancellation for Q-channel DAC in TX mixed-signal module OFF_TYP Type of the OFFI and OFFQ register. While OFF_TYP = 1, the offset values are double buffered and can be chaneged burst by burst after EVENT_VALIDATE comes. Otherwise, the offset values would change immidately after the coming of APB commands, which can't be adjusted burst by burst. 0 No double buffer 1 Double buffered 486/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 11 Timing Generator Timing is the most critical issue in GSM/GPRS applications. The TDMA timer provides a simple interface for the MCU to program all the timing-related events for receive event control, transmit event control and the timing adjustment. Detailed descriptions are mentioned in Section 11.1. 11.1 TDMA timer The TDMA timer unit is composed of three major blocks: Quarter bit counter, Signal generator and Event registers. Figure 84 The block diagram of TDMA timer By default, the quarter-bit counter continuously counts from 0 to the wrap position. In order to apply to cell synchronization and neighboring cell monitoring, the wrap position can be changed by the MCU to shorten or lengthen a TDMA frame. The wrap position is held in the TDMA_WRAP register and the current value of the TDMA quarter bit counter may be read by the MCU via the TDMA_TQCNT register. The signal generator handles the overall comparing and event-generating processes. When a match has occurred between the quarter bit counter and the event register, a predefined control signal is generated. These control signals may be used for on-chip and off-chip purposes. Signals that change state more than once per frame make use of more than one event register. 487/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 The event registers are programmed to contain the quarter bit position of the event that is to occur. The event registers are double buffered. The MCU writes into the write buffers of the registers, and the event TDMA_EVTVAL trigger HW to transfer the data from the write buffers to the active buffers. Caution: values in the active buffers are updated at the end of qbit count (TDMA_EVTVAL). The TDMA_EVTVAL signal itself may be programmed at any quarter bit position. These event registers could be classified into four groups: On-chip Control Events TDMA_EVTVAL This event allows the data values written by the MCU to pass through to the active buffers. TDMA_WRAP TDMA quarter bit counter wrap position. This sets the position at which the TDMA quarter bit counter resets back to zero. The default value is 4999, changing this value will advance or retard the timing events in the frame following the next TDMA_EVTVAL signal. Caution: The wrap value of the first frame after the sleep mode will refer to TQWRAP_SM value if SW enables turbo sleep mode. TDMA_DTIRQ DSP TDMA interrupt requests. DTIRQ triggers the DSP to read the command from the MCU/DSP Shard RAM to schedule the activities that will be executed in the current frame. TDMA_CTIRQ1/CTIRQ2 MCU TDMA interrupt requests. CTIRQx triggers the ARM to schedule the activities that will be executed in the next frame. TDMA_AUXADC [1:0] This signal triggers the monitoring ADC to measure the voltage, current, temperature, device id etc.. TDMA_AFC [3:0] This signal powers up the automatic frequency control DAC for a programmed duration after this event. Note: For both MCU and DSP TDMA interrupt requests, these signals are all active Low during one quarter bit duration and they should be used as edge sensitive events by the respective interrupt controllers. On-chip Receive Events TDMA_BDLON [5:0] 488/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 These registers are a set of six which contain the quarter bit event that initiates the receive window assertion sequence which powers up and enables the receive ADC, and then enables loading of the receive data into the receive buffer. TDMA_BDLOFF [5:0] These registers are a set of six which contain the quarter bit event that initiates the receive window de-assertion sequence which disables loading of the receive data into the receive buffer, and then powers down the receive ADC. TDMA_RXWIN[5:0] DSP TDMA interrupt requests. TDMA_RXWIN is usually used to initiate the related RX processing including two modes. In single-shot mode, TDMA_RXWIN is generated when the BRXFS signal is de-asserted. In repetitive mode, TDMA_RXWIN will be generated both regularly with a specific interval after BRXFS signal is asserted and when the BRXFS signal is de-asserted. Figure 85 The timing diagram of BRXEN and BRXFS Note: TDMA_BDLON/OFF event registers, together with TDMA_BDLCON register, generate the corresponding BRXEN and BRXFS window used to power up/down baseband downlink path and control the duration of data transmission to the DSP, respectively. On-chip Transmit Events TDMA_APC [6:0] These registers initiate the loading of the transmit burst shaping values from the transmit burst shaping RAM into the transmit power control DAC. TDMA_BULON [3:0] This register contains the quarter bit event that initiates the transmit window assertion sequence which powers up the modulator DAC and then enables reading of bits from the transmit buffer into the GMSK modulator. TDMA_BULOFF [3:0] This register contains the quarter bit event that initiates the transmit window de-assertion sequence which disables the reading of bits from the transmit buffer into the GMSK modulator, and then power down the modulator DAC. Figure 86 The timing diagram of BTXEN and BTXFS Note: TDMA_BULON/OFF event registers, together with TDMA_BULCON1, TDMA_BULCON2 register, generate the corresponding BTXEN, BTXFS and APCEN window used to power up/down the baseband uplink path, control the duration of data transmission from the DSP and power up/down the APC DAC, respectively. Off-chip Control Events TDMA_BSI [19:0] 489/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 The quarter bit positions of these 20 BSI events are used to initiate the transfer of serial words to the transceiver and synthesizer for gain control and frequency adjustment. TDMA_BPI [41:0] The quarter bit positions of these 30 BPI events are used to generate changes of state on the output pins to control the external radio components. 11.1.1 Register Definitions 0x82000150 Bit 15 TDMA_EVTENA 0 Event Enable Register 0 14 13 12 11 10 9 8 7 6 5 4 3 Name AFC3 AFC2 AFC1 AFC0 BDL5 BDL4 BDL3 BDL2 BDL1 BDL0 Type R/W Reset 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 2 1 0 CTIRQ CTIRQ DTIR 2 1 Q R/W R/W R/W 0 0 0 DTIRQ Enable TDMA_DTIRQ CTIRQn Enable TDMA_CTIRQn AFCn Enable TDMA_AFCn BDLn Enable TDMA_BDLONn and TDMA_BDLOFFn For all these bits, 0 function is disabled 1 function is enabled 0x82000154h Bit 15 Name GPRS 14 TDMA_EVTENA 1 Event Enable Register 1 13 12 11 10 9 8 7 6 5 4 3 2 1 0 APC6 APC5 APC4 APC3 APC2 APC1 APC0 BUL3 BUL2 BUL1 BUL0 Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 GPRS Indicate which mode is on-going. 0 TDMA_APC0 & TDMA_APC1 events are controlled by APC0 & APC1 in the register TDMA_EVTENA1 & TDMA_DTXCON. (GSM mode) 1 TDMA_APC0 & TDMA_APC1 events are controlled by APC0 & APC1 in the register TDMA_EVTENA1 only. (GPRS mode) APCn Enable TDMA_APCn BULn Enable TDMA_BULONn and TDMA_BULOFFn For all these bits, 0 function is disabled 1 function is enabled 0x82000158 TDMA_EVTENA 2 Event Enable Register 2 Bit 15 14 13 12 11 10 9 Name BSI15 BSI14 BSI13 BSI12 BSI11 BSI10 BSI9 8 BSI8 490/599 7 BSI7 6 BSI6 5 BSI5 4 BSI4 3 BSI3 2 BSI2 1 BSI1 0 BSI0 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 Type R/W Reset 0 R/W 0 0x8200015C 14 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 15 13 12 BSIn BSI event enable control 0 Disable TDMA_BSIn 1 Enable TDMA_BSIn 11 10 9 8 7 6 5 4 0x82000164 R/W 0 R/W 0 3 2 1 0 BSI19 BSI18 BSI17 BSI16 R/W R/W R/W R/W 0 0 0 0 TDMA_EVTENA 4 Event Enable Register 4 Bit 15 14 13 12 11 10 9 Name BPI15 BPI14 BPI13 BPI12 BPI11 BPI10 BPI9 Type R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 R/W 0 TDMA_EVTENA 3 Event Enable Register 3 Bit Name Type Reset 0x82000160 R/W 0 8 BPI8 R/W 0 7 BPI7 R/W 0 6 BPI6 R/W 0 5 BPI5 R/W 0 4 BPI4 R/W 0 3 BPI3 R/W 0 2 BPI2 R/W 0 1 BPI1 R/W 0 0 BPI0 R/W 0 TDMA_EVTENA 5 Event Enable Register 5 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name BPI31 BPI30 BPI29 BPI28 BPI27 BPI26 BPI25 BPI24 BPI23 BPI22 BPI21 BPI20 BPI19 BPI18 BPI17 BPI16 Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BPIn BPI event enable control 0 Disable TDMA_BPIn 1 Enable TDMA_BPIn 0x82000168 TDMA_EVTENA 6 Event Enable Register 6 Bit Name Type Reset 15 14 13 12 BPIn BPI event enable control 0 Disable TDMA_BPIn 1 Enable TDMA_BPIn 11 10 9 8 7 6 5 4 3 2 1 0 BPI41 BPI40 BPI39 BPI38 BPI37 BPI36 BPI35 BPI34 BPI33 BPI32 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 0 0 491/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 0x8200016C 14 Bit Name Type Reset 15 AUX Auxiliary ADC event enable control 0 Disable Auxiliary ADC event 1 Enable Auxiliary ADC event 0x82000170 TDMA_EVTENA 7 Event Enable Register 7 13 12 11 10 9 8 7 6 5 4 3 Bit Name Type Reset 15 TOI This register defines the value used to advance the Qbit timer in unit of 1/4 quarter bit; the timing advance will be take place as soon as the TDMA_EVTVAL is occurred, and it will be cleared automatically. 0x82000174 Bit Name Type Reset 15 13 12 11 10 9 8 7 1 0 AUX1 AUX0 R/W R/W 0 0 TDMA_WRAPOF S Qbit Timer Offset Control Register 14 2 6 5 4 3 13 12 11 10 9 8 1 0 TOI[1:0] R/W 0 TDMA_REGBIA S Qbit Timer Biasing Control Register 14 2 7 6 TQ_BIAS[13:0] R/W 0 5 4 3 2 1 0 TQ_BIAS This register defines the Qbit offset value which will be added to the registers being programmed. It only takes effects on AFC, BDLON/OFF, BULON/OFF, APC, AUXADC, BSI and BPI event registers. 0x82000180 DTX Control Register 15 DTX DTX flag is used to disable the associated transmit signals 0 BULON0~3, BULOFF0~3, APC_EV0 & APC_EV1 are controlled by TDMA_EVTENA1 register 1 BULON0~3, BULOFF0~3, APC_EV0 & APC_EV1 are disabled 0x82000184 14 13 12 11 10 TDMA_DTXCON Bit Name Type 9 8 7 6 5 4 3 2 1 0 DTX3 DTX2 DTX1 DTX0 R/W R/W R/W R/W Receive Interrupt Control Register Bit 15 14 13 12 11 10 Name MOD5 MOD4 MOD3 MOD2 MOD1 MOD0 Type R/W R/W R/W R/W R/W R/W 9 8 492/599 7 TDMA_RXCON 6 5 4 RXINTCNT[9:0] R/W 3 2 1 0 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 RXINTCNT TDMA_RXWIN interrupt generation interval in quarter bit unit MODn Mode of Receive Interrupts 0 Single shot mode for the corresponding receive window 1 Repetitive mode for the corresponding receive window 0x82000188 Bit Name Type 15 Baseband Downlink Control Register 14 13 12 11 ADC_ON R/W 10 9 8 7 TDMA_BDLCON 6 5 4 3 2 ADC_OFF R/W 1 0 ADC_ON BRXEN to BRXFS setup up time in quarter bit unit. ADC_OFF BRXEN to BRXFS hold up time in quarter bit unit. 0x8200018C Bit Name Type 15 14 TDMA_BULCON 1 Baseband Uplink Control Register 1 13 12 11 DAC_ON R/W 10 9 8 7 6 5 4 3 DAC_OFF R/W 2 1 0 DAC_ON BTXEN to BTXFS setup up time in quarter bit unit. DAC_OFF BTXEN to BTXFS hold up time in quarter bit unit. 0x82000190 Bit Name Type 15 TDMA_BULCON 2 Baseband Uplink Control Register 2 14 13 12 11 10 9 8 7 6 5 4 3 APC_HYS R/W 2 1 0 APC_HYS APCEN to BTXEN hysteresis time in quarter bit unit. 0x82000194 Bit 15 TDMA_FB_FLA G Frequency Burst Indication Register 14 13 12 11 10 9 8 Name Type 7 6 5 4 3 2 1 0 FBDL FBDL FBDL FBDL FBDL FBDL 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W FBDLn Indication of frequency burst for RX window n The register is double-buffered. The value at the write buffers will be auto-cleared at the next event-validate (TDMA_EVTVAL) and its value will be at the same time loaded to the active buffer. The exact FB indication comes from the active buffer and the corresponding mode in register TDMA_RXCON (Bit15~Bit10). It will be asserted after TDMA_EVTVAL signals if the corresponding FBDLx & TDMA_RXCON[x+10] are set to 1. The FB indication de-assertion only depends TDMA_FB_CLRI and the falling edge of the corresponding RX window. 493/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 0x82000198 Bit Name Type 15 Direct Frequency Burst Closing 14 13 12 11 10 9 8 TDMA_FB_CLRI 7 6 5 4 3 2 1 0 As long as the register is written, active buffer for FB indication will be reset then therefore the frequency burst indication will be forced to 0. Address Type Width Reset Value Name Description 0x80000000 R [13:0] — TDMA_TQCNT Read quarter bit counter 0x82000004 R/W [13:0] 0x1387 TDMA_WRAP Latched Qbit counter reset position 0x82000008 R/W [13:0] 0x1387 TDMA_WRAPIMD Direct Qbit counter reset position 0x8200000C R/W [13:0] 0x0000 TDMA_EVTVAL Event latch position 0x82000010 R/W [13:0] — TDMA_DTIRQ DSP software control 0x82000014 R/W [13:0] — TDMA_CTIRQ1 MCU software control 1 0x82000018 R/W [13:0] — TDMA_CTIRQ2 MCU software control 2 0x82000020 R/W [13:0] — TDMA_AFC0 The 1st AFC control 0x82000024 R/W [13:0] — TDMA_AFC1 The 2nd AFC control 0x82000028 R/W [13:0] — TDMA_AFC2 The 3rd AFC control 0x8200002C R/W [13:0] — TDMA_AFC3 The 4th AFC control 0x82000030 R/W [13:0] — TDMA_BDLON0 0x82000034 R/W [13:0] — TDMA_BDLOFF0 0x82000038 R/W [13:0] — TDMA_BDLON1 0x8200003C R/W [13:0] — TDMA_BDLOFF1 0x82000040 R/W [13:0] — TDMA_BDLON2 0x82000044 R/W [13:0] — TDMA_BDLOFF2 0x82000048 R/W [13:0] — TDMA_BDLON3 0x8200004C R/W [13:0] — TDMA_BDLOFF3 0x82000050 R/W [13:0] — TDMA_BDLON4 0x82000054 R/W [13:0] — TDMA_BDLOFF4 0x82000058 R/W [13:0] — TDMA_BDLON5 0x8200005C R/W [13:0] — TDMA_BDLOFF5 0x82000060 R/W [13:0] — TDMA_BULON0 0x82000064 R/W [13:0] — TDMA_BULOFF0 0x82000068 R/W [13:0] — TDMA_BULON1 0x8200006C R/W [13:0] — TDMA_BULOFF1 0x82000070 R/W [13:0] — TDMA_BULON2 0x82000074 R/W [13:0] — TDMA_BULOFF2 0x82000078 R/W [13:0] — TDMA_BULON3 0x8200007C R/W [13:0] — TDMA_BULOFF3 494/599 Data serialization of the 1st RX block Data serialization of the 2nd RX block Data serialization of the 3rd RX block Data serialization of the 4th RX block Data serialization of the 5th RX block Data serialization of the 6th RX block Data serialization of the 1st TX slot Data serialization of the 2nd TX slot Data serialization of the 3rd TX slot Data serialization of the 4th TX slot MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 0x82000090 R/W [13:0] — TDMA_APC0 The 1st APC control 0x82000094 R/W [13:0] — TDMA_APC1 The 2nd APC control 0x82000098 R/W [13:0] — TDMA_APC2 The 3rd APC control 0x8200009C R/W [13:0] — TDMA_APC3 The 4th APC control 0x820000A0 R/W [13:0] — TDMA_APC4 The 5th APC control 0x820000A4 R/W [13:0] — TDMA_APC5 The 6th APC control 0x820000A8 R/W [13:0] — TDMA_APC6 The 7th APC control 0x820000B0 R/W [13:0] — TDMA_BSI0 BSI event 0 0x820000B4 R/W [13:0] — TDMA_BSI1 BSI event 1 0x820000B8 R/W [13:0] — TDMA_BSI2 BSI event 2 0x820000BC R/W [13:0] — TDMA_BSI3 BSI event 3 0x820000C0 R/W [13:0] — TDMA_BSI4 BSI event 4 0x820000C4 R/W [13:0] — TDMA_BSI5 BSI event 5 0x820000C8 R/W [13:0] — TDMA_BSI6 BSI event 6 0x820000CC R/W [13:0] — TDMA_BSI7 BSI event 7 0x820000D0 R/W [13:0] — TDMA_BSI8 BSI event 8 0x820000D4 R/W [13:0] — TDMA_BSI9 BSI event 9 0x820000D8 R/W [13:0] — TDMA_BSI10 BSI event 10 0x820000DC R/W [13:0] — TDMA_BSI11 BSI event 11 0x820000E0 R/W [13:0] — TDMA_BSI12 BSI event 12 0x820000E4 R/W [13:0] — TDMA_BSI13 BSI event 13 0x820000E8 R/W [13:0] — TDMA_BSI14 BSI event 14 0x820000EC R/W [13:0] — TDMA_BSI15 BSI event 15 0x820000F0 R/W [13:0] — TDMA_BSI16 BSI event 16 0x820000F4 R/W [13:0] — TDMA_BSI17 BSI event 17 0x820000F8 R/W [13:0] — TDMA_BSI18 BSI event 18 0x820000FC R/W [13:0] — TDMA_BSI19 BSI event 19 0x82000100 R/W [13:0] — TDMA_BPI0 BPI event 0 0x82000104 R/W [13:0] — TDMA_BPI1 BPI event 1 0x82000108 R/W [13:0] — TDMA_BPI2 BPI event 2 0x8200010C R/W [13:0] — TDMA_BPI3 BPI event 3 0x82000110 R/W [13:0] — TDMA_BPI4 BPI event 4 0x82000114 R/W [13:0] — TDMA_BPI5 BPI event 5 0x82000118 R/W [13:0] — TDMA_BPI6 BPI event 6 0x8200011C R/W [13:0] — TDMA_BPI7 BPI event 7 0x82000120 R/W [13:0] — TDMA_BPI8 BPI event 8 0x82000124 R/W [13:0] — TDMA_BPI9 BPI event 9 0x82000128 R/W [13:0] — TDMA_BPI10 BPI event 10 0x8200012C R/W [13:0] — TDMA_BPI11 BPI event 11 495/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 0x82000130 R/W [13:0] — TDMA_BPI12 BPI event 12 0x82000134 R/W [13:0] — TDMA_BPI13 BPI event 13 0x82000138 R/W [13:0] — TDMA_BPI14 BPI event 14 0x8200013C R/W [13:0] — TDMA_BPI15 BPI event 15 0x82000140 R/W [13:0] — TDMA_BPI16 BPI event 16 0x82000144 R/W [13:0] — TDMA_BPI17 BPI event 17 0x82000148 R/W [13:0] — TDMA_BPI18 BPI event 18 0x8200014C R/W [13:0] — TDMA_BPI19 BPI event 19 0x820001A0 R/W [13:0] — TDMA_BPI20 BPI event 20 0x820001A4 R/W [13:0] — TDMA_BPI21 BPI event 21 0x820001A8 R/W [13:0] — TDMA_BPI22 BPI event 22 0x820001AC R/W [13:0] — TDMA_BPI23 BPI event 23 0x820001B0 R/W [13:0] — TDMA_BPI24 BPI event 24 0x820001B4 R/W [13:0] — TDMA_BPI25 BPI event 25 0x820001B8 R/W [13:0] — TDMA_BPI26 BPI event 26 0x820001BC R/W [13:0] — TDMA_BPI27 BPI event 27 0x820001C0 R/W [13:0] — TDMA_BPI28 BPI event 28 0x820001C4 R/W [13:0] — TDMA_BPI29 BPI event 29 0x820001C8 R/W [13:0] — TDMA_BPI30 BPI event 30 0x820001CC R/W [13:0] — TDMA_BPI31 BPI event 31 0x820001D0 R/W [13:0] — TDMA_BPI32 BPI event 32 0x820001D4 R/W [13:0] — TDMA_BPI33 BPI event 33 0x820001D8 R/W [13:0] — TDMA_BPI34 BPI event 34 0x820001DC R/W [13:0] — TDMA_BPI35 BPI event 35 0x820001E0 R/W [13:0] — TDMA_BPI36 BPI event 36 0x820001E4 R/W [13:0] — TDMA_BPI37 BPI event 37 0x820001E8 R/W [13:0] — TDMA_BPI38 BPI event 38 0x820001EC R/W [13:0] — TDMA_BPI39 BPI event 39 0x820001F0 [13:0] — TDMA_BPI40 BPI event 40 R/W 0x820001F4 R/W [13:0] — TDMA_BPI41 BPI event 41 0x82000400 R/W [13:0] — TDMA_AUXEV0 Auxiliary ADC event 0 0x82000404 R/W [13:0] — TDMA_AUXEV1 Auxiliary ADC event 1 0x82000150 R/W [15:0] 0x0000 TDMA_EVTENA0 Event Enable Control 0 0x82000154 R/W [15:0] 0x0000 TDMA_EVTENA1 Event Enable Control 1 0x82000158 R/W [15:0] 0x0000 TDMA_EVTENA2 Event Enable Control 2 0x8200015C R/W [3:0] 0x0000 TDMA_EVTENA3 Event Enable Control 3 0x82000160 R/W [15:0] 0x0000 TDMA_EVTENA4 Event Enable Control 4 0x82000164 R/W [13:0] 0x0000 TDMA_EVTENA5 Event Enable Control 5 0x82000168 R/W [1:0] 0x0000 TDMA_EVTENA6 Event Enable Control 6 496/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 0x8200016C R/W [11:0] 0x0000 TDMA_EVTENA7 Event Enable Control 7 0x82000170 R/W [1:0] 0x0000 TDMA_WRAPOFS TQ Counter Offset Control Register 0x82000174 R/W [13:0] 0x0000 TDMA_REGBIAS Biasing Control Register 0x82000180 R/W [3:0] — TDMA_DTXCON DTX Control Register 0x82000184 R/W [15:0] — TDMA_RXCON Receive Interrupt Control Register 0x82000188 R/W [15:0] — TDMA_BDLCON Downlink Control Register 0x8200018C R/W [15:0] — TDMA_BULCON1 Uplink Control Register 1 0x82000190 R/W [7:0] — TDMA_BULCON2 Uplink Control Register 2 0x82000194 R/W [5:0] — TDMA_FB_FLAG FB indicator 0x82000198 W — TDMA_FB_CLRI Direct clear of FB indicator Table 47 TDMA Timer Register Map 11.1.2 Application Note Figure 87 RX Timing Set Example The TDMA timing and data setting are described in 2 parts. One part is that before turning on RX SPORT to receiving I/Q data. And the other part is after turning off RX SPORT to finish receiving I/Q data. To describe these two parts easily, the timing of turning on RX SPORT is taken as one base named R0. And the timing of turning off RX SPORT is taken as one base named R1. RX ADC part: To setup the timing of RX ADC and SPORT, 2 timings need to be defined in l1d_custom_rf.h. The time from RX ADC enabling to RX SPORT turning on (R0) is defined as QB_RX_FENA_2_FSYNC.The time from RX SPORT turning on (R1) to RX ADC disabling is defined as QB_RX_FSYNC_2_FENA. The value of this two aliases should be positive or zero. These two values is defined in the register TDMA_BDLCON. BSI part: 497/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 BSI data and events need to be set in serial to a 3-wire base RF module. Each RX window is allocated 3 BSI events. Usually 1'st BSI event is used to warm up the synthesizer and set its N-counter to lock the operation frequency. The 2'nd BSI is used to set the receiving amplifier gain of transceiver. The 3'rd BSI is used to command transceiver entering idle mode. BSI events are defined in the registers TDMA_BSI0~19. BPI part: The connection of HW signals of BPI data bus and RF module is flexible and depends on customer's design. The setting timing and data setting of BPI bus are used to specify at what time and which BPI states are changed. The BPI data may be varied by the operation band, so the dedicate BPI data of each band should be defined. The states transient of BPI signals are decided by the time of event, therefore the active time and the BPI states for each band shall be defined. BPI events are defined in the registers TDMA_BPI0~41. TX ADC part: To setup the timing of TX DAC and SPORT, 2 timings need to be defined in l1d_custom.h. The time from TX DAC enabling to TX SPORT turning on (T0) is defined as QB_TX_FENA_2_FSYNC.The time from TX SPORT turning on (T1) to TX DAC disabling is defined as QB_TX_FSYNC_2_FENA. The value of this two aliases should be positive or zero. These two values is defined in the register TDMA_BULCON1. BSI part: BSI data and events need to be set in order to sent serial data to 3-wire devices on RF module. Each TX window is allocated 3 BSI events. Usually 1'st BSI event is used to warm up the set synthesizer and set its N-counter to lock the 498/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 operation frequency. The 2'nd BSI is used to set the transmit command and indicate the operation band. The 3'rd BSI is used to command transceiver entering idle mode. BSI events are defined in the registers TDMA_BSI0~19. BPI parts: The setting of BPI bus includes timing and data setting to specify at what time what BPI states are changed. The BPI data may be varied by operation band, so the BPI data of each band should be defined. The 1'st BPI event is usually used to activate the RF components on RF module in transmit mode. The 2'nd BPI event is usually used to select band and switch R/TX. The 3'rd BPI event is usually used to force the RF module into idle mode. BPI events are defined in the registers TDMA_BPI0~41. APC parts: In addition to TX DAC, TX SPORT, BSI, BPI unit needs to be set, the control of PA is important for TX window. The PA is control by the APC unit of MT62xx. Before the data transmission, APC ramps up the PA to the indicated power level. Data is transmitted at that level. After finishing transmission, APC ramps down the PA. Before PA ramping up, A DC offset of PA is performed to let PA ramp up smoothly. APC events are defined in the registers TDMA_APC0~6. 11.2 Slow Clocking Unit Figure 88 The block diagram of the slow clocking unit The slow clocking unit is provided to maintain the synchronization to the base-station timing using a 32KHz crystal oscillator while the 13MHz reference clock is switched off. As shown in Figure 88, this unit is composed of frequency measurement unit, pause unit, and clock management unit. Because of the inaccuracy of the 32KHz oscillator, a frequency measurement unit is provided to calibrate the 32KHz crystal taking the accurate 13MHz source as the reference. The calibration procedure always takes place prior to the pause period. 499/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 The pause unit is used to initiate and terminate the pause mode procedure and it also works as a coarse time-base during the pause period. The clock management unit is used to control the system clock while switching between the normal mode and the pause mode. SRCLKENA is used to turn on/off the clock squarer, DSP PLL and off-chip TCVCXO. CLOCK_OFF signal is used for gating the main MCU and DSP clock, and VCXO_OFF is used as the acknowledgement signal of the CLOCK_OFF request. 11.2.1 Register Definitions 0x82000218 Bit 15 Slow clocking unit control register 14 13 12 11 10 9 8 7 SM_CON 6 5 4 3 Name Type Reset 2 1 0 PAUSE_STA FM_STAR RT T W W 0 0 FM_START Initiate the frequency measurement procedure PAUSE_STARTInitiate the pause mode procedure at the next timer wrap position 0x8200021C Bit Slow clocking unit status register 15 14 13 12 SM_STA 11 10 9 3 2 1 8 PAUSE_ABO RT R 0 FM_CPL FM_RQST R R Name Type Bit 7 6 5 4 SETTLE_CP PAUSE_RQS PAUSE_CPL PAUSE_INT Name L T Type R R R R FM_RQST Frequency measurement procedure is requested FM_CPL Frequency measurement procedure is completed PAUSE_RQST Pause mode procedure is requested PAUSE_INT Asynchronous wake up from pause mode PAUSE_CPL Pause period is completed SETTLE_CPL Settling period is completed PAUSE_ABORT Pause mode is aborted because of the reception of interrupt prior to entering pause mode 0x8200022C 14 Slow clocking unit configuration register 13 12 11 10 9 8 15 FM SM KP EINT RTC MSDC Enable interrupt generation upon completion of frequency measurement procedure Enable interrupt generation upon completion of pause mode procedure Enable asynchronous wake-up from pause mode by key press Enable asynchronous wake-up from pause mode by external interrupt Enable asynchronous wake-up from pause mode by real time clock interrupt Enable asynchronous wake-up from pause mode by memory card insertion interrupt 500/599 7 TP R/W 0 6 SM_CNF Bit Name Type Reset 5 4 MSDC RTC R/W R/W 0 0 3 EINT R/W 0 2 KP R/W 0 1 SM R/W 1 0 FM R/W 1 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 TP Enable asynchronous wake-up from pause mode by touch panel press 0x82000238 Bit 15 Name EN Type R/W Reset 1 TIME EN WAKE_PLL_ SETTING WAKE_PLL_SETTING (TIME & ENABLE) 14 13 12 11 10 9 8 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 7 6 TIME R/W R/W 0 0 5 4 3 2 1 0 R/W 1 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 The time sleep control generates a reset signal for PLL in the clk setting time. Enable the generation of the reset signal 0 Disable 1 Enable Address Type Width Reset Value Name Description 0x82000200 R/W [2:0] — SM_PAUSE_M MSB of pause duration 0x82000204 R/W [15:0] — SM_PAUSE_L 16 LSB of pause duration 0x82000208 R/W [13:0] — SM_CLK_SETTLE Off-chip VCXO settling duration 0x8200020C R [2:0] — SM_FINAL_PAUSE_M MSB of final pause count 0x82000210 R [15:0] — SM_FINAL_PAUSE_L 16 LSB of final pause count 0x82000214 R [13:0] — SM_QBIT_START TQ_ COUNT value at the start of the pause 0x82000218 W [1:0] 0x0000 SM_CON SM control register 0x8200021C R [7:3,1:0] 0x0000 SM_STA SM status register 0x82000220 R/W [15:0] — SM_FM_DURATION 32KHz measurement duration 0x82000224 R [9:0] — SM_FM_RESULT_M 10 MSB of frequency measurement result 0x82000228 R [15:0] — SM_FM_RESULT_L 16 LSB of frequency measurement result 0x8200022C R/W [4:0] 0x0000 SM_CNF SM configuration register 0x82000230 R [23:0] 0x000000 RTCCOUNT 501/599 RTC count MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 0x82000238 R/W [15:0] 0x8020 WAKE_PLL_SETTING PLL RST time in the clk settling time. 502/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 12 Power, Clocks and Reset 12.1 Clocks There are two major time bases in the MT6235. For the faster one is the 13 MHz clock originating from an off-chip temperature-compensated voltage controlled oscillator (TCVCXO) that can be either 13MHz or 26MHz. This signal is the input from the SYSCLK pad then is converted to the square-wave signal. The other time base is the 32768 Hz clock generated by an on-chip oscillator connected to an external crystal. Figure 89 shows the clock sources as well as their utilizations inside the chip. Figure 89 Clock distributions inside the MT6235 12.1.1 32.768 KHz Time Base The 32768 Hz clock is always running. It’s mainly used as the time base of the Real Time Clock (RTC) module, which maintains time and date with counters. Therefore, both the 32768Hz oscillator and the RTC module is powered by separate voltage supplies that shall not be powered down when the other supplies do. In low power mode, the 13 MHz time base is turned off, so the 32768 Hz clock shall be employed to update the critical TDMA timer and Watchdog Timer. This time base is also used to clocks the keypad scanner logic. 12.1.2 13 MHz Time Base One 1/2-dividers for PLL existing to allow using 26 or 13 MHz TCVCXO. 503/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 One phase-locked loops (PLL) to generate 624Mhz clock output, then a frequency divider futher divide 6, 3, 13 to generate 104Mhz, 208Mhz, 48Mhz for three primary clocks, DSP_CLOCK, MCU_CLOCK and USB_CLOCK, respectively. These three primary clocks then feed to DSP Clock Domain and MCU Clock Domain and USB, respectively. The PLL require no off-chip components for operations and can be turn off in order to save power. After power-on, the PLLs are off by default and the source clock signal is selected through multiplexers. The software shall take cares of the PLL lock time while changing the clock selections. The PLL and usages are listed below. PLL supplies three clock source DSP system clock, DSP_CLOCK. The outputted 104MHz clock is connected to DSP DCM (dynamic clock manager) for dynamically adjusting clock rate by digital clock divider. MCU system clock, MCU_CLOCK, which paces the operations of the MCU cores, MCU memory system, and MCU peripherals as well. The outputted 208MHz clock is connected to ARM DCM and AHB DCM for dynamically adjusting clock rate by digital clock divider. The usage of DCM is described in MCUCLK_CON registers of CONFIG. USB system clock, USB_CLOCK. The 48MHz is sent to USB module for its operation. Note that PLL need some time to become stable after being powered up. The software shall take cares of the PLL lock time before switching them to the proper frequency. Usually, a software loop longer than the PLL lock time is employed to deal with the problem. For power management, the MCU software program may stop MCU Clock by setting the Sleep Control Register. Any interrupt requests to MCU can pause the sleep mode, and thus MCU return to the running mode. AHB also can be stop by setting the Sleep Control Register. However the behavior of AHB in sleep mode is a little different from that of MCU. After entering Sleep Mode, it can be temporarily waken up by any “hreq” (bus request), and then goes back to sleep automatically after all “hreqs” de-assert. Any transactions can take place as usual in sleep mode, and it can save power while there is no transaction on it. However the penalty is losing a little system efficiency for switching on and off bus clock, but the impact is small. 12.1.3 Dynamic Clock Switch of MCU Clock Dynamic Clock Manager is implemented to allow MCU and DSP switching clock dynamically without any jitter, and enabling signal drift, and system can operate stably during any clock rate switch. Please note that PLL must be enabled and the frequency shall be set as 624MHz, therefore the required MCU/DSP/USB clocks can be generated from 624MHz. Before switching to 52MHz clock rate, the clock from the CLKSQ will feed through the dynamic clock manager (DCM) directly. That means if CLKSQ divider is enabled (MPLL_DIV2=1) and PLL clock is bypassed (MPLL_SEL=00), the internal clock rate is the half of SYSCLK. Contrarily, the internal clock rate is identical to SYSCLK. However, the settings of some hardware modules is required to be changed before or after clock rate change. Software has the responsibility to change them at proper timing. The following table is list of hardware modules needed to be changed their setting during clock rate change. EMI clock is always fixed at 104Mhz when MCU clock is dynamically changed. Module Name NAND Programming Sequence 1. Low clock speed -> high clock speed 504/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 Changing wait state before clock change. New wait state will not take effect until current EMI access is complete. Software should insert a period of time before switching clock. 2. High clock speed -> low clock speed Changing wait state after clock change. LCD Change wait state while LCD in IDLE state. Table 48 Programming sequence during clock switch 12.1.4 Standard PLL Power-on Sequence // 0x8300001C, Power on DSP_DIV2, MPLL, DPLL, MCU_DIV2, and CLKSQ *(volatile kal_uint16 *)PDN_CON = 0x0000; // 0x83000108, Switch to 13MHz input for PLL reference clock *(volatile kal_uint16 *)CLK_CON = 0x0003; // After power-on PLL..... *PLL = 0x0080; // 0x83000000, reset PLL *PLL = 0x0000; // 0x83000000, reset release, and wait for PLL output stable for (i=0;i<200;i++); *PLL = 0x0070; // 0x83000000, select PLL output 12.1.5 Register Definitions PLL_CLKSQ+0 MPLL(DPLL, UPLL) Frequency Register1 000h Bit 15 14 13 12 11 10 Name CALI Type Reset R/W 0 9 8 7 6 5 UPLL DPLL RST SEL SEL R/W R/W R/W 0 0 0 PLL 4 3 2 1 0 MPLLSEL PLLVCOSEL R/W 0 R/W 00 PLLVCOSEL Selects VCO in PLL frequency for PLL debug purpose. Default value is 0x0. MPLLSEL Select MCU Clock source. Using this mux to gate out unstable clock output from PLL after system boot up 00 PLL bypassed, using CLK from CLKSQ, default value after chip power up. 01 PLL bypassed, using CLK from SYSCLK 10 Using PLL Clock for MCU 505/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 11 Reserved DPLLSEL Select DSP Clock source. Using this mux to gate out unstable clock output from PLL after system boot up 0 PLL bypassed, using CLK from CLKSQ 1 Using PLL Clock for DSP UPLLSEL Select USB Clock source. Using this mux to gate out unstable clock output from PLL after system boot up 0 PLL bypassed, using CLK from CLKSQ 1 Using PLL Clock for USB RST Reset Control of PLL 0 Normal Operation 1 Reset the PLL CALI Calibration Control for PLL PLL_CLKSQ +0004h Bit Name Type Reset 15 MPLL(DPLL, UPLL) Frequency Register2 14 13 12 PLL_DIVCTRL R/W 1110 11 10 9 8 7 6 PLL2 5 4 3 2 1 PLL_TEST R/W 0 0 PLL_TEST Entering test mode PLL_DIVCTRL Just for test purpose. Fine tune the 624MHz main frequency of VCO in PLL (PLL_DIVCTRL + 2) x 3 x13 = 624 PLL_CLKSQ+0 Clock Control Register 018h Bit 15 14 13 12 11 10 9 CLK_CON 8 7 CLKS Name Q_TE ST SRCC LK Type R/W Reset 0 R/W 1 6 5 4 3 2 1 0 CLKS CLKS CLKS Q_DIV Q_DIV Q_PL 2_MC 2_DS D U P R/W R/W R/W 0 0 0 CLKSQ_DIV2_DSP Control the clock divider for DSP clock domain 0 Divider bypassed 1 Divider not bypassed CLKSQ_DIV2_MCU Control the x2 clock divider for MCU clock domain 0 Divider bypassed 1 Divider not bypassed CLKSQ_PLD Pull Down Control 0 Disable 506/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 1 Enables CLKSQ_TEST CLKSQ test mode SRCCLK Indicate the frequency of SYSCLK 0 13MHz 1 26MHz PLL_CLKSQ+0 Power-down control 01Ch Bit 15 DSP_ Name DIV2 Type R/W Reset 1 14 13 12 11 MCU_ CLKS PLL DIV2 Q R/W R/W R/W 1 1 0 10 PDN_CON 9 8 7 6 5 4 3 2 1 0 CLKSQ Control CLKSQ power-down MCU_DIV2 Control CLKSQ divide-by-2 power-down for MCU clock DSP_DIV2 Control CLKSQ divide-by-2 power-down for DSP clock PLL Control MPLL(including DPLL and UPLL) power-down 12.2 Reset Generation Unit (RGU) Figure 90 shows the reset scheme used in MT6235. reset, and software reset. SYSRST# Watchdog Timer Peri. Soft Reset DSP Soft Reset MT6235 provides three kinds of resets: hardware reset, watchdog R12 MCU Subsystem R123 MCU Peripheral R124 DSP Subsystem R1 R2 R3 R4 DSP Coprocessor WATCHDOG# Figure 90 Reset Scheme Used in MT6235 507/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 12.2.1 General Description 12.2.1.1 Hardware Reset This reset is input through the SYSRST# pin, which is driven low during power-on. The hardware reset has a global effect on the chip: all digital and analog circuits are initialized, except the Real Time Clock module. The initial states of the MT6235 sub-blocks are as follows:. • All analog circuits are turned off. • All PLLs are turned off and bypassed. The 13 MHz system clock is the default time base. 12.2.1.2 Watchdog Reset A watchdog reset is generated when the Watchdog Timer expires: the MCU software failed to re-program the timer counter in time. This situation is typically induced by abnormal software execution, which can be aborted by a hardwired watchdog reset. Hardware blocks that are affected by the watchdog reset are: • MCU subsystem, • DSP subsystem, and • External components (trigged by software). 12.2.1.3 Software Resets Software resets are local reset signals that initialize specific hardware components. For example, if hardware failures are detected, the MCU or DSP software may write to software reset trigger registers to reset those specific hardware modules to their initial states. The following modules have software resets. 12.2.2 15 DSP Core • DSP Coprocessors Register Definitions RGU +0000h Bit • 14 Watchdog Timer Control Register 13 12 11 Name KEY[7:0] Type Reset WO ENABLE 0 1 EXTPOL 0 1 10 9 8 7 WDT_MODE 6 5 4 3 2 1 0 AUTO EXTE EXTP ENAB -REST IRQ N OL LE ART R/W R/W R/W R/W R/W 0 0 0 0 1 Enables the Watchdog Timer. Disables the Watchdog Timer. Enables the Watchdog Timer. Defines the polarity of the external watchdog pin. Active low. Active high. 508/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 EXTEN Specifies whether or not to generate an external watchdog reset signal. 0 The watchdog does not generate an external watchdog reset signal. 1 If the watchdog counter reaches zero, an external watchdog signal is generated. IRQ Issues an interrupt instead of a Watchdog Timer reset. For debug purposes, RGU issues an interrupt to the MCU instead of resetting the system. 0 Disable. 1 Enable. AUTO-RESTART Restarts the Watchdog Timer counter with the value of WDT_LENGTH while task ID is written into Software Debug Unit. 0 Disable. The counter restarts by writing KEY into the WDT_RESTART register. 1 Enable. The counter restarts by writing KEY into the WDT_RESTART register or by writing task ID into the software debug unit. KEY Write access is allowed if KEY=0x22. RGU +0004h Bit Name Type Reset 15 14 Watchdog Time-Out Interval Register 13 12 11 10 9 TIMEOUT[10:0] R/W 111_1111_1111b 8 7 WDT_LENGTH 6 KEY Write access is allowed if KEY=08h. TIMEOUT The counter is restarted with {TIMEOUT [10:0], 1_1111_1111b}. is a multiple of 512*T32k=15.6ms. RGU +0008h Bit Name Type Reset 15 14 5 4 3 12 11 10 9 8 7 KEY[15:0] WO 1 0 Thus the Watchdog Timer time-out period Watchdog Timer Restart Register 13 2 KEY[4:0] WO WDT_RESTART 6 5 4 3 2 1 0 KEY Restart the counter if KEY=1971h. RGU +000Ch Bit 15 14 SW_W Name WDT DT Type RO RO Reset 0 0 Watchdog Timer Status Register 13 12 11 10 9 8 WDT_STA 7 6 5 4 3 2 1 0 Indicates the cause of the watchdog reset. 0 Reset not due to Watchdog Timer. 1 Reset because the Watchdog Timer time-out period expired. SW_WDT Indicates if the watchdog was triggered by software. 0 Reset not due to software-triggered Watchdog Timer. 1 Reset due to software-triggered Watchdog Timer. NOTE: A system reset does not affect this register. This bit is cleared when the WTU_MODE register ENABLE bit is written. WDT 509/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 RGU +0010h Bit 15 14 Name DMAR ST Type Reset R/W 0 SW_PERIPH_RS TN CPU Peripheral Software Reset Register 13 12 11 10 9 8 7 6 5 4 3 2 1 0 KEY WO KEY Write access is allowed if KEY=37h. DMARST Reset the DMA peripheral. 0 No reset. 1 Invoke a reset. RGU +0014h Bit 15 Name RST Type R/W Reset 0 RST 14 13 12 11 10 9 8 SW_DSP_RSTN 7 6 5 3 2 15 14 RGU+001Ch 13 12 11 10 9 8 7 6 5 LENGTH[ 11:0] R/W FFFh 15 14 4 3 0 12 11 10 9 8 7 KEY[15:0] WO 6 1 0 However, if the WDT_MODE Watchdog Timer Software Reset Register 13 2 WDT_SWRST 5 4 3 2 Software-triggered Watchdog Timer reset. If the register content matches the KEY, a watchdog reset is issued. if the WDT_MODE register IRQ bit is set to 1, an interrupt is issued instead of a reset. KEY 1 WDT_RSTINTRE VAL Watchdog Timer Reset Signal Duration Register LENGTH This register indicates the reset duration when Watchdog Timer times out. register IRQ bit is set to 1, an interrupt is issued instead of a reset. Bit Name Type Reset 4 Controls the DSP System Reset Control. 0 No reset. 1 Invoke a reset. RGU +0018h Bit Name Type Reset DSP Software Reset Register 1 0 However, 1209h 510/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 12.3 Global Configuration Registers 12.3.1 Register Definitions CONFG+0000h Hardware Version Register Bit Name Type Reset 15 14 13 EXTP RO 8 12 11 10 9 MAJREV RO A HW_VERSION 8 7 6 5 MINREV RO 0 4 3 2 1 0 HFIX RO 0 This register is useful for software program to determine the hardware version of the chip. It will have a new value whenever each metal fix or major step is performed. All these values are incremented by a step of 1. HFIX MINREV MAJREV EXTP Iteration to fix a hardware bug, in case of some layer mask fixed Minor Revision of the chip, in case of all layer masks changed Major Revision of the chip This field shows the existence of Hardware Code Register that presents the Hardware ID while the value is other than zero. CONFG+0004h Firmware Version Register Bit Name Type Reset 15 14 13 EXTP RO 8 12 11 10 9 MAJREV RO A FW_VERSION 8 7 6 5 MINREV RO 0 4 3 2 1 0 FFIX RO 0 This register is useful for software program to determine the Firmware ROM version that is included in this chip. All these values are incremented by a step of 1. FFIX MINREV MAJREV EXTP Iteration to fix a firmware bug Minor Revision of the firmware Major Revision of the firmware This field shows the existence of Hardware Code Register that presents the Hardware ID when the value is other than zero. CONFG+0008h Hardware Code Register Bit Name Type Reset 15 14 13 CODE3 RO 6 12 11 10 9 CODE2 RO 2 HW_CODE 8 7 6 5 CODE1 RO 3 4 3 2 1 CODE0 RO 5 0 This register presents the Hardware ID. CONFG+114h Sleep Control Register Bit Name 15 14 13 12 11 10 9 SLEEP_CON 8 511/599 7 6 5 4 3 2 1 DSP2 DSP1 AHB 0 MCU MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 Type Reset WO 0 WO 0 WO 0 RO 0 Interrupt status. This bit represents if any irq or fiq occurs. 0 There is irq or firq 1 There is no irq and firq To make MCU clock off, this bit should in 1 state and an instruction should be executed . MCR p15,0,,c7,c0,4 AHB Stops the AHB Bus Clock to force the entire bus to enter sleep mode. AHB clock resumes as long as there is an interrupt request or system is reset. 0 AHB Bus Clock is running 1 AHB Bus Clock is stopped DSP1 Stops the DSP1 Clock. 0 DSP1 Bus Clock is running 1 DSP1 Bus Clock is stopped DSP2 Stops the DSP2Clock. 0 DSP2 Bus Clock is running 1 DSP2 Bus Clock is stopped MCU This version of chip is coded as 6235h. CODE CONFG+0118h Bit Name Type Reset 15 14 13 EMICLK R 0111 MCU Clock Control Register 12 11 10 9 ARMCLK R/W 0111 8 MCUCLK_CON 7 6 5 AHBX4CLK R/W 0011 4 3 2 1 AHBX8CLK R/W 0111 0 The register specifies MCU Subsystem and ARM clock frequency. ARMCLK is used for ARM926 MCU processor. AHBX8CLK is used for 104Mhz AHB bus system and AHBX4CLK is used for 52Mhz AHB bus system. EMICLK must be 0111 for normal operation and other settings are only used for debug purpose. The clock rate must be ARM CLOCK > AHBX8CLK > AHBX4CLK. The max operation frequency for ARMCLK is 208Mhz (1111), for AHBX8CLK is 104Mhz (0111), for AHBX4CLK is 52Mhz. MCUCLK_CON control register is only active when internal PLL is enabled. Be sure to turn MCUCLK_CON to its default setting before turn clock source from PLL to clock squarer. ARMCLK Select the Output Clock Rate for ARM926 0000 13Mhz 0001 13MHz x 2 0010 reserved 0011 13MHz x 4 0100 reserved 0101 reserved 0110 reserved 0111 13MHz x 8 512/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 1111 13MHz x 16 OTHERS reserved AHBX8CLK Select the Clock Rate for 104Mhz Bus clock 0000 13Mhz 0001 13MHz x 2 0010 reserved 0011 13MHz x 4 0100 reserved 0101 reserved 0110 reserved 0111 13MHz x 8 1111 reserved OTHERS reserved AHBX4CLK Select the Clock Rate for 52Mhz Bus clock 0000 13Mhz 0001 13MHz x 2 0010 reserved 0011 13MHz x 4 0100 reserved 0101 reserved 0110 reserved 0111 reserved 1111 reserved OTHERS reserved CONFG+011Ch Bit Name Type Reset 15 SPDM, SPDS 0000 0001 0010 0011 0100 0101 0110 0111 14 DSP Clock Control Register 13 15 11 10 9 8 7 6 5 SPDS R/W 0000 4 3 2 1 SPDM R/W 0000 0 Select the Output Clock Rate for Master/Slave DSPCLK power down 13MHz x 2 13MHz x 3 13MHz x 4 13MHz x 5 13MHz x 6 13MHz x 7 13MHz x 8 CONFG+0200h Bit 12 DSPCLK_CON 14 Internal Debug Select Register 13 12 11 10 9 8 513/599 7 IDN_SEL 6 5 4 3 2 1 0 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 DSP_ TV_E EXTC XTCK K Type R/W R/W Reset 0 0 Name IRWIN ROM_ WAIT R/W 0 R/W 0 AHB_ CLKS RESE TDMA SLEE RVED Q P R/W R/W R/W R/W 0 0 0 0 MPLL R/W 0 TV_EXTCK DSP_EXTCK IRWIN Use EINT3 as clock source of TV logic instead of internal PLL Use EINT2 as clock source of DSP logic instead of internal PLL IRDMA has highest priority at DMA AMBA bus ROM_WAIT AHB_SLEEP TDMA MPLL Controls the wait cycle of SYSROM when bus is run at 104Mhz When this bit is 0, then AHB Clock only can stop when the MCU is in idle power down mode TDMA Internal Debug Signal MCU PLL Internal Debug Signal CONFG+300h Power Down Control 0 Register Bit 15 14 13 12 11 IRDB IRDB G2 G1 Name Type Reset R 1 10 9 SIM2 R 1 8 PDN_CON0 7 PWM PWM3 R 1 R 1 R 1 6 5 IR R 1 4 3 2 WAVE SEJ TABL GCU E R R R 1 1 1 1 0 USB DMA R 1 R 1 DMA Controls the DMA Controller Power Down USB Controls the USB Controller Power Down GCU Controls the GCU Controller Power Down WAVETALBE Controls the DSP WaveTable DMA Power Down SEJ Controls the Secure Engine Power Down IR Controls the IR (IR DMA) Power Down PWM3 Controls the the 3rd PWM Generator Power Down PWM Controls the Main PWM Generator Power Down. Only set this bit when all PWM are in power down. SIM2 Controls the second SIM Controller Power Down IRDBG1 Controls the IRDBG1 Power Down IRDBG2 Controls the IRDBG2 Power Down CONFG +304h Power Down Control 1 Register Bit 14 UART Name IRDA 3 Type R R Reset 1 1 GPT KP 15 13 12 11 NFI PWM2 R 1 R 1 10 TP R 1 9 8 7 UART MSDC LCD 2 R R R 1 1 1 PDN_CON1 6 5 4 3 2 UART PWM1 SIM GPIO 1 R R R R 1 1 0 1 1 0 KP GPT R 1 R 1 Controls the General Purpose Timer Power Down Controls the Keypad Scanner Power Down 514/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 GPIO Controls the GPIO Power Down UART1 Controls the UART1 Controller Power Down SIM Controls the SIM Controller Power Down PWM1 Controls the 1st PWM Generator Power Down LCD Controls the Serial LCD Controller Power Down UART2 Controls the UART2 Controller Power Down MSDC Controls the MS/SD Controller Power Down TP Controls the Touch Panel Power Down PWM2 Controls the 2nd PWM Generator Power Down NFI Controls the NAND FLASH Interface Power Down UART3 Controls the UART3 Controller Power Down IRDA Controls the IrDA Framer Power Down CONFG +308h Power Down Control 2 Register Bit 15 14 Name GMSK BBRX Type Reset R 1 R 1 13 12 11 10 I2C AAFE DIV GCC R 1 R 1 R 1 R 1 9 PDN_CON2 8 7 6 AUXA BFE VAFE FCS D R R R R 1 1 1 1 5 4 3 2 1 APC AFC BPI BSI R 1 R 1 R 1 R 1 0 RTC TDMA R 1 R 1 TDMA Controls the TDMA Power Down RTC Controls the RTC Power Down BSI Controls the BSI Power Down. This control will not be updated until both tdma_evtval and qbit_en are asserted. BPI Controls the BPI Power Down. This control will not be updated until both tdma_evtval and qbit_en are asserted. AFC Controls the AFC Power Down. This control will not be updated until both tdma_evtval and qbit_en are asserted. APC Controls the APC Power Down. This control will not be updated until both tdma_evtval and qbit_en are asserted. FCS Controls the FCS Power Down AUXAD Controls the AUX ADC Power Down VAFE Controls the Audio Front End of VBI Power Down BFE Controls the Base-Band Front End Power Down GCU Controls the GCU Power Down DIV Controls the Divider Power Down AAFE Controls the Audio Front End of MP3 Power Down I2C Controls the I2C Power Down BBRX Controls the BB RX Power Down GMSK Controls the GMSK Power Down CONFG +30Ch Power Down Control 3 Register Bit Name Type Reset CRZ GCMQ G2D ISP 15 14 13 12 ISP R 1 11 10 9 8 7 G2D GCMQ R R 1 1 PDN_CON3 6 5 4 3 2 CRZ R 1 1 0 Controls CRZ Power Down Controls the Graphic Command Queue Power Down Controls the 2D Accelerator Power Down Controls the Image Signal Processor Power Down 515/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 CONFG+0310h Power Down Set 0 Register Bit 15 14 12 11 IRDB IRDB G2 G1 Name Type 13 W1S W1S W1S W1S 10 9 SIM2 W1S W1S PDN_SET0 8 7 PWM PWM3 W1S W1S W1S 6 5 IR W1S W1S 4 3 2 WAVE SEJ TABL GCU E W1S W1S W1S CONFG+0314h Power Down Set 1 Register Bit 15 14 13 UART Name IRDA 3 Type W1S W1S W1S 12 11 10 15 14 Name GMSK BBRX Type W1S W1S 12 11 10 I2C AAFE DIV GCC W1S W1S W1S W1S 13 W1S W1S DMA W1S W1S 8 7 6 5 4 3 2 1 UART ALTE UART NFI PWM2 TP MSDC LCD PWM1 SIM GPIO KP 2 R 1 W1S W1S W1S W1S W1S W1S W1S W1S W1S W1S W1S W1S 13 14 USB 9 9 12 ISP W1S 7 6 AUXA BFE VAFE FCS D W1S W1S W1S W1S 11 10 9 W1S W1S W1S 0 GPT W1S PDN_SET2 8 5 4 3 2 1 APC AFC BPI BSI RTC TDMA W1S W1S W1S W1S W1S CONFG+031Ch Power Down Set 3 Register Bit 15 Name Type W1S 0 PDN_SET1 CONFG+0318h Power Down Set 2 Register Bit 1 0 W1S PDN_SET3 8 7 6 G2D GCMQ W1S W1S W1S 5 4 3 W1S W1S W1S 2 CRZ W1S 1 0 W1S These registers are used to individually set power down control bit. Only the bits set to 1 are in effect. Setting the bits to 1 also sets the corresponding power down control bits will to 1. Otherwise, the bits keep their original value. However, the control bits APC, AFC, BPI and BSI in PDN_SET2 register will NOT be updated until both tdma_evtval and qbit_en are asserted. EACH BIT Set the Associated Power Down Control Bit to 1. 0 no effect 1 Set corresponding bit to 1 CONFG+0320h Power Down Clear 0 Register Bit 15 14 12 11 IRDB IRDB G2 G1 Name Type 13 W1C W1C W1C W1C 10 9 SIM2 W1C W1C 8 PDN_CLR0 7 PWM PWM3 W1C W1C W1C 6 5 IR W1C W1C 4 3 2 WAVE SEJ TABL GCU E W1C W1C W1C CONFG+0324h Power Down Clear 1 Register Bit 15 14 13 12 11 10 1 0 USB DMA W1C W1C PDN_CLR1 9 8 7 6 5 4 3 2 1 UART ALTE UART Name IRDA UART3 NFI PWM2 TP MSDC LCD PWM1 SIM GPIO KP 2 R 1 Type W1C W1C W1C W1C W1C W1C W1C W1C W1C W1C W1C W1C W1C W1C W1C CONFG+0328h Power Down Clear 2 Register Bit 15 14 13 12 11 10 9 8 516/599 0 GPT W1C PDN_CLR2 7 6 5 4 3 2 1 0 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 Name GMSK BBRX Type W1C W1C AUXA FCS D W1C W1C W1C I2C AAFE DIV GCC BFE VAFE APC AFC BPI BSI RTC TDMA W1C W1C W1C W1C W1C W1C W1C W1C W1C W1C CONFG+032Ch Power Down Clear 3 Register Bit 15 Name Type W1C 14 W1C 13 12 ISP W1C W1C 11 10 9 W1C W1C W1C W1C PDN_CLR3 8 7 6 G2D GCMQ W1C W1C W1C 5 4 3 W1C W1C W1C 2 CRZ W1C 1 0 W1C These registers are used to individually clear power down control bit. Only the bits set to 1 are in effect. Setting the bits to 1 also sets the corresponding power down control bits to 0. Otherwise, the bits keep their original value. However, the control bits APC, AFC, BPI and BSI in PDN_SET2 register will NOT be updated until both tdma_evtval and qbit_en are asserted. EACH BIT Clear the Associated Power Down Control Bit. 0 no effect 1 Set corresponding bit to 0 CONFG +330h Power Down Control 4 Register 14 Bit Name Type Reset 15 BSI BPI AFC APC Controls the BSI Power Down. This control will be updated immediately. Controls the BPI Power Down. This control will be updated immediately. Controls the AFC Power Down. This control will be updated immediately. Controls the APC Power Down. This control will be updated immediately. CONFG+334 Bit Name Type Reset 15 14 13 12 11 10 9 8 PDN_CON4 7 6 5 APC WO 1 4 AFC WO 1 3 BPI WO 1 2 BSI WO 1 1 Power Down Set 4 Register 13 12 11 10 9 0 PDN_SET4 8 7 6 5 APC W1S 1 4 AFC W1S 1 3 BPI W1S 1 2 BSI W1S 1 1 0 EACH BIT Set the Associated Power Down Control Bit to 1. This control will be updated immediately 0 no effect 1 Set corresponding bit to 1 CONFG+338 Bit Name Type Reset 15 14 Power Down Clear 4 Register 13 12 11 10 9 8 PDN_CLR4 7 6 5 APC W1C 1 4 AFC W1C 1 3 BPI W1C 1 2 BSI W1C 1 1 0 EACH BIT Clear the Associated Power Down Control Bit to 1. This control will be updated immediately 0 no effect 1 Set corresponding bit to 0 517/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 CONFG+0404h APB Bus Control Register Bit 15 14 13 Name Type Reset APB_CON 12 11 10 9 8 APBW APBW APBW APBW APBW 4 3 2 1 0 R/W R/W R/W R/W R/W 0 0 0 0 0 7 6 5 4 3 2 1 0 APBR APBR APBR APBR APBR 4 3 2 1 0 R/W R/W R/W R/W R/W 1 1 1 1 1 This register is used to control the timing of Read Cycle and Write Cycle on APB Bus. Note that APB Bridge 2 is different from other bridges. The access time is varied, and access is not completed until acknowledge signal from APB slave is asserted and must be configured as 2-Cycle Read/Write Access. APBR0-APBR4 Read Access Time on APB Bus 0 1-Cycle Access 1 2-Cycle Access APBW0-APBW4 Write Access Time on APB Bus 0 1-Cycle Access 1 2-Cycle Access CONFG+0408h Slow Down Control Register Bit Name Type Reset 15 14 13 12 11 10 DIS Slow Down Disable Control 0 Others 1 Disable all slow down functionality. 9 8 SLOWDN_CON 7 6 5 4 3 CONFG+040C IRDMA CON h Bit Name Type Reset 15 14 13 2 1 0 DIS R/W 0 IRDMA_CON 12 11 10 WAVETABLE_SD 9 8 7 6 5 4 3 IRDMA_SD 2 1 0 IRDMA_SD IRDMA Slow Down Limit Count WAVETABLE_SD Wavetable Slow Down Limit Count CONFG+0700h Analog Chip Interface Control Register 0 Bit 15 14 13 12 11 10 9 8 7 6 Name NLI_OD NAND_OD LCD_OD Type Reset R/W 000 R/W 000 R/W 000 ACIF_CON0 5 4 3 CMPC LK_S MT RW 0 2 1 0 CMMCLK_OD R/W 000 The register specifies IO driving capability of external interface. 518/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 CONFG+0704h Analog Chip Interface Control Register 1 Bit Name Type Reset 15 14 13 UR2_OD R/W 000 12 11 10 9 UR1_OD R/W 000 8 7 ACIF_CON1 6 5 SDA_OD R/W 000 4 3 2 1 SCL_OD R/W 000 0 The register specifies IO driving capability of external interface. UR2_OD UART2 output driving control UR1_OD UART1 output driving control SDA1_OD PAD SDA output driving control SCL_OD PAD SCL output driving control CONFG+0708h Analog Chip Interface Control Register 2 Bit 15 CMVR Name EF_P D_B Type R/W Reset 0 14 CMHR EF_P D_B R/W 0 13 12 11 10 9 8 CMPC CMDA EWAI MFIQ_ PWM2 PWM3 LK_P T_PU T_PD PU_B _OD _OD D_B _B _B R/W R/W R/W R/W 0 0 0 0 7 6 ACIF_CON2 5 4 ED_C LK_B DIS R/W 0 3 2 1 0 EADMUX_OD R/W 0000 CMVREF_PD_B Pull down enable of CMVREF (0: enable, 1: disable) CMHREF_PD_B Pull down enable of CMHREF(0: enable, 1: disable) CMPCLK_PD_B Pull down enable of CMPCLK(0: enable, 1: disable) CMDAT_PU_B Pull down enable of CMDAT[9:0] (0: enable, 1: disable) EADMUX_OD Pad EADMUX output driving control ED_CLK_B DIS ED_CLK_B output enable control (0: enable output 1:disable output) The following 28 registers specify the setting of the sense amplifier delay for MediaTek in-house made ROM and RAM macros. ROM_DELSEL 0 CONFG+0900h MCU ROM Setting Control Register 0 Bit Name Type Reset 15 14 13 12 11 10 MDSP_MCN0 R/W 00001100 9 8 7 6 5 4 3 MCUROM R/W 00001100 15 14 13 12 11 MDSP_MPN0 R/W 00000011 10 9 8 519/599 1 0 ROM_DELSEL 1 CONFG+0904h ROM Setting Control Register 1 Bit Name Type Reset 2 7 6 5 4 3 MDSP_MCN1 R/W 00001100 2 1 0 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 ROM_DELSEL 2 CONFG+0908h ROM Setting Control Register 2 Bit Name Type Reset 15 14 13 12 11 10 SDSP_SDC20 R/W 00001100 9 8 7 6 5 4 3 SDSP_SC21 R/W 00001100 15 14 13 12 11 SDSP_SC10 R/W 00001100 10 9 8 7 6 5 4 3 SDSP_SC11 R/W 00001100 15 14 13 12 11 SDSP_SC00 R/W 00001100 10 9 8 7 6 5 4 3 SDSP_SC01 R/W 00001100 15 14 13 12 11 SDSP_SC51 R/W 00001100 10 9 8 7 6 5 4 3 SDSP_SC60 R/W 00001100 15 14 CONFG+091Ch Bit Name Type Reset 15 14 13 12 11 SDSP_SC31 R/W 00001100 10 9 8 7 6 5 4 3 SDSP_SC50 R/W 00001100 12 11 SDSP_SP10 R/W 00001100 10 9 8 520/599 0 2 1 0 2 1 0 2 1 0 ROM_DELSEL 7 ROM Setting Control Register 7 13 1 ROM_DELSEL 6 CONFG+0918h ROM Setting Control Register 6 Bit Name Type Reset 2 ROM_DELSEL 5 CONFG+0914h ROM Setting Control Register 5 Bit Name Type Reset 0 ROM_DELSEL 4 CONFG+0910h ROM Setting Control Register 4 Bit Name Type Reset 1 ROM_DELSEL 3 CONFG+090Ch ROM Setting Control Register 3 Bit Name Type Reset 2 7 6 5 4 3 SDSP_SC30 R/W 00001100 2 1 0 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 CONFG+0920h Bit Name Type Reset 15 14 ROM_DELSEL 8 ROM Setting Control Register 8 13 12 11 SDSP_SP31 R/W 00000011 10 9 8 7 6 5 4 3 SDSP_SP00 R/W 00000011 15 14 13 12 11 SDSP_SP50 R/W 00001100 10 9 8 7 6 5 4 3 SDSP_SP40 R/W 00001100 15 14 13 MDSP_MPN1 R/W 0001 CONFG+0A04h Bit Name Type Reset 15 Bit Name Type Reset 15 11 10 9 MDSP_MCN2 R/W 0001 8 7 2 6 5 MDSP_MD00 R/W 0001 4 3 12 11 10 9 SDSP_SC40 R/W 0011 8 12 11 10 9 SDSP_SD20 R/W 0101 8 7 6 5 MDSP_MD02 R/W 0101 4 3 2 1 MDSP_MD01 R/W 0001 15 14 13 SDSP_SD12 R/W 0001 CONFG+0A10h Bit 15 14 12 11 10 9 SDSP_SD30 R/W 0101 8 7 6 5 SDSP_SD11 R/W 0001 4 3 2 1 SDSP_SPN1 R/W 0001 12 11 10 9 8 521/599 0 0 RAM _DELSEL3 7 6 5 SDSP_SD01 R/W 0001 4 3 2 1 SDSP_SDN3 R/W 0001 0 RAM _DELSEL4 RAM Setting Control Register 4 13 0 RAM _DELSEL2 CONFG+0A0Ch RAM Setting Control Register 3 Bit Name Type Reset 0 RAM _DELSEL1 RAM Setting Control Register 2 14 13 SDSP_SD10 R/W 0001 1 2 1 L2CACHE R/W 0101 RAM Setting Control Register 1 14 13 SDSP_SP30 R/W 0101 CONFG+0A08h 12 0 RAM_DELSEL 0 CONFG+0A00h MCU RAM Setting Control Register 0 Bit Name Type Reset 1 ROM_DELSEL 9 CONFG+0924h ROM Setting Control Register 9 Bit Name Type Reset 2 7 6 5 4 3 2 1 0 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 Name Type Reset BSI_RAM R/W 0001 CONFG+0A14h Bit Name Type Reset 15 14 ISP_AWB R/W 01 15 SHARE_RAM1 R/W 0001 VTB_MEM R/W 0001 RAM _DELSEL5 RAM Setting Control Register 5 13 12 ISP_SHAD R/W 01 CONFG+0A18h Bit Name Type Reset SHARE_RAM2 R/W 0001 11 10 9 8 RESZ_LB_RAM R/W 0001 7 6 IMG_RAM R/W 01 5 4 PRF_RAM R/W 01 3 2 EQ_RAM R/W 01 RAM _DELSEL6 RAM Setting Control Register 6 14 13 LCD_RAM R/W 0001 12 11 10 9 TVC_RAM R/W 0001 8 7 6 5 4 3 ISP_COLOR R/W 00010101 2 15 14 13 ISP_DM0[7:4] R/W 0001 CONFG+0A20h Bit Name Type Reset 15 15 14 13 12 ISP_DM0[23:20] R/W 0001 14 10 9 ISP_DM[3:0] R/W 0001 11 10 9 8 ISP_DM0[19:16] R/W 0001 13 12 11 10 R/W 0001 15 14 8 7 6 5 USB RAM R/W 0001 4 3 9 7 6 5 4 ISP_DM0[15:12] R/W 0001 3 8 7 ISP_DM1[15:0] 6 5 4 3 R/W 0001 R/W 0001 11 10 9 8 7 ISP_NR11[15:0] R/W 0001 2 1 ISP_DM0[11:8] R/W 0001 0 2 1 0 RAM_DELSEL 10 6 5 R/W 0001 522/599 0 R/W 0001 RAM Setting Control Register10 12 2 1 GMC_RAM R/W 0001 RAM_DELSEL 9 R/W 0001 13 0 RAM_DELSEL 8 RAM Setting Control Register 9 CONFG+0A28h Bit Name Type Reset 11 RAM Setting Control Register 8 CONFG+0A24h Bit Name Type Reset 12 1 RAM _DELSEL7 CONFG+0A1Ch RAM Setting Control Register 7 Bit Name Type Reset 1 0 AFE_RAM R/W 01 4 3 2 1 0 R/W 0001 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 RAM _DELSEL11 CONFG+0A2Ch RAM Setting Control Register 11 Bit 15 14 13 Name ARM_M32[3:0] Type Reset R/W 0001 CONFG+0A30 Bit Name Type Reset 15 14 ARM_M6 R/W 01 CONFG+0A34 Bit Name Type Reset 15 14 ARM_M10 R/W 01 CONFG+0A38 Bit Name Type Reset 15 14 ARM_M15 R/W 01 CONFG+0A3C Bit Name Type Reset 15 14 ARM_M23 R/W 01 CONFG+0A40 Bit Name Type Reset 15 14 ARM_M27 R/W 01 CONFG+0A44 Bit 15 14 ARM_M31[1: Name 0] Type R/W 12 11 10 9 8 7 6 5 4 ARM_M31[3: ISP_AWBSB ISP_AWBSG ISP_AWBSR 2] R/W R/W R/W R/W 00 01 01 01 3 2 12 11 ARM_M5 R/W 0001 10 9 8 ARM_M4 R/W 01 ISP_3A R/W 01 R/W 01 RAM_DELSEL 12 7 6 ARM_M3 R/W 01 5 4 ARM_M2 R/W 01 3 2 ARM_M1 R/W 01 12 11 ARM_M9 R/W 0001 10 9 8 7 ARM_M8 R/W 0001 6 5 4 3 ARM_M7 R/W 0001 11 10 ARM_M13 R/W 01 9 8 7 ARM_M12 R/W 0001 6 5 4 3 ARM_M11 R/W 0001 11 10 ARM_M21 R/W 01 9 8 ARM_M20 R/W 01 7 6 ARM_M19 R/W 01 5 4 ARM_M18 R/W 01 12 11 ARM_M26 R/W 0001 10 9 12 11 10 9 8 7 ARM_M25 R/W 0001 8 1 0 ARM_M10 R/W 00 1 0 ARM_M16 R/W 01 RAM_DELSEL 16 6 5 4 3 ARM_M24 R/W 0001 2 1 0 ARM_M23 R/W 00 RAM_DELSEL 17 RAM Setting Control Register17 13 2 3 2 ARM_M17 R/W 01 RAM Setting Control Register16 13 1 0 ARM_M6 R/W 00 RAM_DELSEL 15 RAM Setting Control Register15 13 12 ARM_M22 R/W 01 2 RAM_DELSEL 14 RAM Setting Control Register14 13 12 ARM_M14 R/W 01 1 0 ARM_M0 R/W 01 RAM_DELSEL 13 RAM Setting Control Register13 13 0 ISP_AEHI RAM Setting Control Register12 13 1 7 6 5 4 3 2 1 0 ARM_M30 ARM_M29 ARM_M28 ARM_M27 R/W R/W R/W R/W 523/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 Reset 01 0001 0001 524/599 0001 00 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 525/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 13 Analog Front-end & Analog Blocks 13.1 General Description To communicate with analog blocks, a common control interface for all analog blocks is implemented. In addition, there are some dedicated interfaces for data transfer. The common control interface translates APB bus write and read cycle for specific addresses related to analog front-end control. During writing or reading of any of these control registers, there is a latency associated with transferring of data to or from the analog front-end. Dedicated data interface of each analog block is implemented in the corresponding digital block. The Analog Blocks includes the following analog function for complete GSM/GPRS base-band signal processing: 1. Base-band RX: For I/Q channels base-band A/D conversion 2. Base-band TX: For I/Q channels base-band D/A conversion and smoothing filtering, DC level shifting 3. RF Control: Two DACs for automatic power control (APC) and automatic frequency control (AFC) are included. Their outputs are provided to external RF power amplifier and VCXO), respectively. 4. Auxiliary ADC: Providing an ADC for battery and other auxiliary analog function monitoring 5. Audio mixed-signal blocks: It provides complete analog voice signal processing including microphone amplification, A/D conversion, D/A conversion, earphone driver, and etc. Besides, dedicated stereo D/A conversion and amplification for audio signals are included). 6. Clock Generation: A clock squarer for shaping system clock, and three PLLs that provide clock signals to DSP, MCU, and USB units are included 7. XOSC32: It is a 32-KHz crystal oscillator circuit for RTC application Analog Block Descriptions 13.1.1 BBRX 13.1.1.1 Block Descriptions The receiver (RX) performs base-band I/Q channels downlink analog-to-digital conversion: 1. Analog input multiplexer: For each channel, a 4-input multiplexer that supports offset and gain calibration is included. 2. A/D converter: Two 14-bit sigma-delta ADCs perform I/Q digitization for further digital signal processing. 13.1.1.2 Functional Specifications The functional specifications of the base-band downlink receiver are listed in the following table. Symbol Parameter Min 526/599 Typical Max Unit MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 N Resolution 14 Bit FC Clock Rate 26 MHz FS Output Sampling Rate 13/12 MSPS Input Swing When GAIN=’0’ 0.8*AVDD Vpk When GAIN=’1’ 0.4*AVDD Vpk OE Offset Error +/- 10 mV FSE Full Swing Error +/- 30 mV I/Q Gain Mismatch SINAD ICN DR 0.5 Signal to Noise and Distortion Ratio - 45kHz sine wave in [0:90] kHz bandwidth - 145kHz sine wave in [10:190] kHz bandwidth dB dB dB 65 65 Idle channel noise - [0:90] kHz bandwidth - [10:190] kHz bandwidth -74 -70 dB dB Dynamic Range - [0:90] kHz bandwidth - [10:190] kHz bandwidth 74 70 dB dB RIN Input Resistance 75 kΩ DVDD Digital Power Supply 1.1 1.2 1.3 V AVDD Analog Power Supply 2.5 2.8 3.1 V T Operating Temperature -20 80 ℃ Current Consumption Power-up Power-Down 5 5 mA µA Table 49 Base-band Downlink Specifications 13.1.2 BBTX 13.1.2.1 Block Descriptions The transmitter (TX) performs base-band I/Q channels up-link digital-to-analog conversion. Each channel includes: 1. 10-Bits D/A Converter: It converts digital GMSK modulated signals to analog domain. The input to the DAC is sampled at 4.33-MHz rate with 10-bits resolution. 2. Smoothing Filter: The low-pass filter performs smoothing function for DAC output signals with a 350-kHz 2nd-order Butterworth frequency response. 527/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 13.1.2.2 Function Specifications The functional specifications of the base-band uplink transmitter are listed in the following table. Symbol Parameter Min Typical Max Unit N Resolution 10 Bit FS Sampling Rate 4.33 MSPS SINAD Signal to Noise and Distortion Ratio 57 60 dB Output Swing 0.18*AVDD Output CM Voltage 0.34*AVDD VOCM 0.5*AVDD Output Capacitance Output Resistance 0.89*AVDD V 0.62*AVDD V 20 PF 10 KΩ DNL Differential Nonlinearity +/- 0.5 LSB INL Integral Nonlinearity +/- 1.0 LSB OE Offset Error +/- 15 mV FSE Full Swing Error +/- 30 mV FCUT Filter –3dB Cutoff Frequency 300 350 400 KHz ATT Filter Attenuation at 100-KHz 270-KHz 4.33-MHz 0.01 1.81 69.4 0.0 0.85 65.7 0.0 0.39 61.9 dB dB dB I/Q Gain Mismatch +/- 0.5 I/Q Gain Mismatch Correction Range -0.96 DVDD Digital Power Supply 1.1 AVDD Analog Power Supply 2.5 T Operating Temperature -20 Current Consumption Power-up Power-Down dB +0.84 dB 1.2 1.3 V 2.8 3.1 V 80 ℃ 5 5 mA µA Table 50 Base-band Uplink Transmitter Specifications 13.1.3 13.1.3.1 AFC-DAC Block Descriptions As shown in the following figure, together with a 2nd-oder digital sigma-delta modulator, AFC-DAC is designed to produce a single-ended output signal at AFC pin. AFC pin should be connected to an external 1st-order R-C low pass filter to meet the 13-bits resolution (DNL) requirement1. 1 DNL performance depends on external output RC filter bandwidth: the narrower the bandwidth, the better the DNL. Thus, there exists a tradeoff between output setting speed and DNL performance 528/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 The AFC_BYP pin is the mid-tap of a resistor divider inside the chip to offer the AFC output common-mode level. Nominal value of this common-mode voltage is half the analog power supply, and typical value of output impedance of AFC_BYP pin is about 21kΩ. To suppress the noise on common mode level, it is suggested to add an external capacitance between AFC_BYP pin and ground. The value of the bypass capacitor should be chosen as large as possible but still meet the settling time requirement set by overall AFC algorithm2. Figure 91 Block diagram of AFC-DAC 13.1.3.2 Functional Specifications The following table gives the electrical specification of AFC-DAC. Symbol Parameter Min Typical Max Unit N Resolution 13 Bit FS Sampling Rate 1083.3 KHz DVDD Digital Power Supply 1.08 1.2 1.32 V AVDD Analog Power Supply 2.6 2.8 3.1 V T Operating Temperature -20 80 ℃ 1 mA µA Current Consumption Power-up Power-Down 0.3 Output Swing @GAINSEL=0 Output Swing @GAINSEL=1 0.75*AVDD AVDD Output Resistor (in AFC output RC network) 1 V KΩ DNL Differential Nonlinearity +1/-1 LSB INL Integral Nonlinearity +4.0/-4.0 LSB Table 51 Functional specification of AFC-DAC 2 AFC_BYP output impedance and bypass capacitance determine the common-mode settling RC time constant. Insufficient common-mode settling will affect the INL performance. A typical value of 1nF is suggested. 529/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 13.1.4 13.1.4.1 APC-DAC Block Descriptions The APC-DAC is a 10-bits DAC with output buffer aimed for automatic power control. Here blow are its analog pin assignment and functional specification tables. 13.1.4.2 Symbol Function Specifications Parameter Min N Resolution FS Sampling Rate SINAD Signal to Noise and Distortion Ratio (10-KHz Sine with 1.0V Swing & 100-KHz BW) Typical Max Unit 1.0833 MSPS 10 Bit 50 dB 99% Settling Time (Full Swing on Maximal Capacitance) 5 µS Output Swing AVDD-0.2 V Output Capacitance 200 pF Output Resistance 10 KΩ DNL Differential Nonlinearity +/- 0.5 LSB INL Integral Nonlinearity +/- 1.0 LSB OE Offset Error +/- 10 mV FSE Full Swing Error +/- 10 mV DVDD Digital Power Supply 1.1 1.2 1.3 V AVDD Analog Power Supply 2.5 2.8 3.1 V T Operating Temperature -20 80 ℃ Current Consumption Power-up Power-Down µA µA 400 1 Table 52 APC-DAC Specifications 13.1.5 Auxiliary ADC 13.1.5.1 Block Descriptions The auxiliary ADC includes the following functional blocks: 1. Analog Multiplexer: The analog multiplexer selects signal from one of the seven auxiliary input pins. Real word message to be monitored, like temperature, should be transferred to the voltage domain. 2. 10 bits A/D Converter: The ADC converts the multiplexed input signal to 10-bit digital data. 13.1.5.2 Function Specifications The functional specifications of the auxiliary ADC are listed in the following table. Symbol Parameter Min 530/599 Typical Max Unit MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 N Resolution 10 FC Clock Rate FS Sampling Rate @ N-Bit 0.1 1.0833 Bit 5 MHz 5/(N+1) MSPS Input Swing 1.0 AVDD V VREFP Positive Reference Voltage (Defined by AUX_REF pin) 1.0 AVDD V CIN Input Capacitance Unselected Channel Selected Channel 50 1.2 fF pF RIN RS DNL Input Resistance Unselected Channel Selected Channel 10 1.8 Resistor String Between AUX_REF pin & ground Power Up Power Down 35 10 MΩ MΩ 50 65 KΩ MΩ Clock Latency 11 1/FC Differential Nonlinearity +0.5/-0.5 LSB INL Integral Nonlinearity +1.0/-1.0 LSB OE Offset Error +/- 10 mV FSE Full Swing Error +/- 10 mV SINAD Signal to Noise and Distortion Ratio (10-KHz Full Swing Input & 13-MHz Clock Rate) 50 dB DVDD Digital Power Supply 1.1 1.2 1.3 V AVDD Analog Power Supply 2.5 2.8 3.1 V T Operating Temperature -20 80 ℃ Current Consumption Power-up Power-Down 150 1 µA µA Table 53 The Functional specification of Auxiliary ADC 13.1.6 Audio mixed-signal blocks 13.1.6.1 Block Descriptions Audio mixed-signal blocks (AMB) integrate complete voice uplink/downlink and audio playback functions. As shown in the following figure, it includes mainly three parts. The first consists of stereo audio DACs and speaker amplifiers for audio playback. The second is the voice downlink path, including voice-band DACs and amplifiers, which produces voice signal to earphone or other auxiliary output device. Amplifiers in these two blocks are equipped with multiplexers to accept signals from internal audio/voice or external radio sources. The last is the voice uplink path, which 531/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 MUX MUX is the interface between microphone (or other auxiliary input device) input and MT6235 DSP. A set of bias voltage is provided for external electret microphone.. MUX Figure 92 Block diagram of audio mixed-signal blocks. 13.1.6.2 Functional Specifications The following table gives functional specifications of voice-band uplink/downlink blocks. Symbol Parameter Min FS Sampling Rate 6500 KHz CREF Decoupling Cap Between AU_VREF_P And AU_VREF_N 47 NF DVDD Digital Power Supply 1.08 1.2 1.32 V AVDD Analog Power Supply 2.5 2.8 3.1 V T Operating Temperature -20 80 ℃ IDC Current Consumption 5 mA VMIC Microphone Biasing Voltage 1.9 V IMIC Current Draw From Microphone Bias 532/599 Typical Max 2 Unit mA MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 Pins Uplink Path3 Signal to Noise and Distortion Ratio Input Level: -40 dbm0 Input Level: 0 dbm0 29 RIN Input Impedance (Differential) 13 ICN XT SINAD dB dB 69 20 27 KΩ Idle Channel Noise -67 dBm0 Crosstalk Level -66 dBm0 4 Downlink Path Signal to Noise and Distortion Ratio Input Level: -40 dBm0 Input Level: 0 dBm0 29 RLOAD Output Resistor Load (Differential) 28 CLOAD Output Capacitor Load 200 pF ICN Idle Channel Noise of Transmit Path -67 dBm0 XT Crosstalk Level on Transmit Path -66 dBm0 SINAD dB dB 69 Ω Table 54 Functional specifications of analog voice blocks Functional specifications of the audio blocks are described in the following. Symbol FCK Parameter Clock Frequency Min Typical 6.5 Max Unit MHz Fs Sampling Rate 32 44.1 48 KHz AVDD Power Supply 2.6 2.8 3.1 V T Operating Temperature -20 80 ℃ IDC Current Consumption 5 mA PSNR Peak Signal to Noise Ratio 80 dB DR Dynamic Range 80 dB VOUT Output Swing for 0dBFS Input Level 0.85 Vrms THD Total Harmonic Distortion -40 45mW at 16 Ω Load dB dB 3 For uplink-path, not all gain setting of VUPG meets the specification listed on table, especially for the several highest gains. The maximum gain that meets the specification is to be determined. 4 For downlink-path, not all gain setting of VDPG meets the specification listed on table, especially for the several lowest gains. The minimum gain that meets the specification is to be determined. 533/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 -60 22mW at 32 Ω Load RLOAD Output Resistor Load (Single-Ended) 16 Ω CLOAD Output Capacitor Load 200 pF XT L-R Channel Cross Talk TBD dB Table 55 Functional specifications of the analog audio blocks 13.1.7 Clock Squarer 13.1.7.1 Block Descriptions For most VCXO, the output clock waveform is sinusoidal with too small amplitude (about several hundred mV) to make MT6235 digital circuits function well. Clock squarer is designed to convert such a small signal to a rail-to-rail clock signal with excellent duty-cycle. It provides also a pull-down function when the circuit is powered-down. 13.1.7.2 Function Specifications The functional specification of clock squarer is shown in Table 56. Symbol Parameter Min Typical Fin Input Clock Frequency 13 MHz Fout Output Clock Frequency 13 MHz Vin Input Signal Amplitude 500 DcycIN Input Signal Duty Cycle 50 DcycOUT Output Signal Duty Cycle TR DcycIN-5 Max AVDD Unit mVpp % DcycIN+5 % Rise Time on Pin CLKSQOUT 5 ns/pF TF Fall Time on Pin CLKSQOUT 5 ns/pF DVDD Digital Power Supply 1.08 1.2 1.32 V AVDD Analog Power Supply 2.6 2.8 3.0 V T Operating Temperature -20 80 ℃ Current Consumption TBD ΜA Table 56 The Functional Specification of Clock Squarer 13.1.7.3 Application Notes Here below in the figure is an equivalent circuit of the clock squarer. Please be noted that the clock squarer is designed to accept a sinusoidal input signal. If the input signal is not sinusoidal, its harmonic distortion should be low enough to not produce a wrong clock output. As an reference, for a 13MHz sinusoidal signal input with amplitude of 0.2V the harmonic distortion should be smaller than 0.02V. 534/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 Figure 93 Equivalent circuit of Clock Squarer. 13.1.8 Phase Locked Loop 13.1.8.1 Block Descriptions MT6235 includes three PLLs: DSP PLL, MCU PLL, and USB PLL. DSP PLL and MCU PLL are identical and programmable to provide 104MHz and 208 MHz output clock while accepts 13MHz signal. USB PLL is designed to also accept 13MHz input clock signal and provides 48MHz output clock. 13.1.8.2 Function Specifications The functional specification of DSP/MCU PLL is shown in the following table. Symbol Parameter Min Fin Input Clock Frequency Fout Output Clock Frequency 208 MHz Lock-in Time TBD Μs Output Clock Duty Cycle Typical Max 13 40 Output Clock Jitter 50 Unit MHz 60 % 650 ps DVDD Digital Power Supply 1.08 1.2 1.32 V AVDD Analog Power Supply 2.6 2.8 3.0 V T Operating Temperature -20 80 ℃ Current Consumption TBD µA Table 57 The Functional Specification of DSP/MCU PLL The functional specification of USB PLL is shown below. Symbol Parameter Min Fin Input Clock Frequency 13 MHz Fout Output Clock Frequency 48 MHz Lock-in Time TBD µs 535/599 Typical Max Unit MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 Output Clock Duty Cycle 40 50 Output Clock Jitter 60 % 650 ps DVDD Digital Power Supply 1.08 1.2 1.32 V AVDD Analog Power Supply 2.5 2.8 3.1 V T Operating Temperature -20 80 ℃ Current Consumption TBD µA Table 58 The Functional Specification of USB PLL 13.1.9 13.1.9.1 32-KHz Crystal Oscillator Block Descriptions The low-power 32-KHz crystal oscillator XOSC32 is designed to work with an external piezoelectric 32.768kHz crystal and a load composed of two functional capacitors, as shown in the following figure. Figure 94 Block diagram of XOSC32 13.1.9.2 Functional specifications The functional specification of XOSC32 is shown in the following table. Symbol Parameter AVDDRTC Analog power supply Tosc Start-up time Dcyc Duty cycle Min Typical Max Unit 1.08 1.2 1.32 V 5 sec 50 % TR Rise time on XOSCOUT TBD ns/pF TF Fall time on XOSCOUT TBD ns/pF Current consumption 5 Leakage current T Operating temperature 1 -20 µA µA 80 ℃ Table 59 Functional Specification of XOSC32 Here below are a few recommendations for the crystal parameters for use with XOSC32. 536/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 Symbol Parameter F Frequency range GL Drive level ∆f/f Frequency tolerance ESR Series resistance 50 KΩ C0 Static capacitance 1.6 pF 12.5 pF CL 5 Min Typical Max Unit 32768 Hz 5 uW +/- 20 Load capacitance Ppm 6 Table 60 Recommended Parameters of the 32kHz crystal 13.2 MCU Register Definitions 13.2.1 BBRX MCU APB bus registers for BBRX ADC are listed as followings. 0x83010300 Bit Name 15 BBRX ADC Analog-Circuit Control Register 14 13 12 DITHE N 11 10 9 8 7 QSEL ISEL RSV Type R/W R/W R/W R/W Reset 0 00 00 0 6 5 GAIN R/W 00 BBRX_AC_CON 4 3 2 1 0 CALBIAS R/W 00000 Set this register for analog circuit configuration controls. CALBIAS The register field is for control of biasing current in BBRX mixed-signal module. It is coded in 2’s complement. That is, its maximum is 15 and minimum is –16. Biasing current in BBRX mixed-signal module has impact on the performance of A/D conversion. The larger the value of the register field, the larger the biasing current in BBRX mixed-signal module, and the larger the SNR. GAIN The register bit is for configuration of gain control of analog inputs in GSM RX mixed-signal module. 00 Input range is 0.8x AVDD for analog inputs in GSM RX mixed-signal module. 01 Input range is 0.4x AVDD for analog inputs in GSM RX mixed-signal module. 10 Input range is 0.57x AVDD for analog inputs in GSM RX mixed-signal module. 11 Input range is 0.33x AVDD for analog inputs in GSM RX mixed-signal module. ISEL Loopback configuration selection for I-channel in BBRX mixed-signal module 00 Normal mode 01 Loopback TX analog I 10 Loopback TX analog Q 11 Select the grounded input QSEL Loopback configuration selection for Q-channel in BBRX mixed-signal module 00 Normal mode 01 Loopback TX analog Q 5 CL is the parallel combination of C1 and C2 in the block diagram. 537/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 10 Loopback TX analog I 11 Select the grounded input DITHDIS Dither feature Disable control register, which can effectively reduce the THD ( total harmonic distortion) of the BBRX ADC. 0 turn on the dither (default value) 1 Disable the dither 13.2.2 BBTX MCU APB bus registers for BBTX DAC are listed as followings. 0x83010400 Bit BBTX_AC_CON 0 BBTX DAC Analog-Circuit Control Register 0 15 14 CALR STAR Name CDON TCAL E RC Type R R/W Reset 0 0 13 12 11 10 9 8 7 6 5 4 3 2 1 GAIN CALRCSEL TRIMI TRIMQ R/W 000 R/W 000 R/W 0000 R/W 0000 0 Set this register for analog circuit configuration controls. The procedure to perform calibration processing for smoothing filter in BBTX mixed-signal module is as follows: 1. Write 1 to the register bit STARTCALRC. Start calibration process. 2. Read the register bit CALRCDONE. If read as 1, then calibration process finished. Otherwise repeat the step. 3. Write 0 to the register bit STARTCALRC. Stop calibration process. 4. The result of calibration process can be read from the register field CALRCOUT of the register BBTX_AC_CON1. Software can set the value to the register field CALRCSEL for 3-dB cutoff frequency selection of smoothing filter in DAC of BBTX. Remember to set the register field CALRCCONT of the register BBTX_AC_CON1 to 0xb before the calibration process. It only needs to be set once. TRIMQ The register field is used to control gain trimming of Q-channel DAC in BBTX mixed-signal module. It is coded in 2’s complement, that is, with maximum 7 and minimum –8. TRIMI The register field is used to control gain trimming of I-channel DAC in BBTX mixed-signal module. It is coded in 2’s complement, that is, with maximum 7 and minimum –8. CALRCSEL The register field is for selection of cutoff frequency of smoothing filter in BBTX mixed-signal module. It is coded in 2’s complement. That is, its maximum is 3 and minimum is –4. GAIN The register field is used to control gain of DAC in BBTX mixed-signal module. It has impact on both of I- and Q-channel DAC in BBTX mixed-signal module. It is coded in 2’s complement, that is, with maximum 3 and minimum –4. STARTCALRC Whenever 1 is writing to the bit, calibration process for smoothing filter in BBTX mixed-signal module will be triggered. Once the calibration process is completed, the register bit CARLDONE will be read as 1. 538/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 CALRCDONE The register bit indicates if calibration process for smoothing filter in BBTX mixed-signal module has finished. When calibration processing finishes, the register bit will be 1. When the register bit STARTCALRC is set to 0, the register bit becomes 0 again. 0x83010404 Bit 15 BBTX_AC_CON 1 BBTX DAC Analog-Circuit Control Register 1 14 13 Name CALRCOUT Type Reset R/O - 12 FLOA T R/W 0 11 10 9 8 CALRCCNT 7 6 5 4 CALBIAS R/W 00000 3 2 1 0 CMV R./W 0000 R/W 000 Set this register for analog circuit configuration controls. The register field is used to control common voltage in BBTX mixed-signal module. It is coded in 2’s complement, that is, with maximum 3 and minimum –4. CALBIAS The register field is for control of biasing current in BBTX mixed-signal module. It is coded in 2’s complement. That is, its maximum is 7 and minimum is –8. Biasing current in BBTX mixed-signal module has impact on performance of D/A conversion. Larger the value of the register field, the larger the biasing current in BBTX mixed-signal module. CALRCCNT Parameter for calibration process of smoothing filter in BBTX mixed-signal module. Default value is ‘22’. Note that it is NOT coded in 2’s complement. Therefore the range of its value is from 0 to 31. Remember to set it to 0x16 before BBTX calibration process if clock sent to BBTX is 26Mhz. Otherwise set to 0xb if clock is 13Mhz. It only needs to be set once. In MT6235, only 26MHz clock is available FLOAT The register field is used to have the outputs of DAC in BBTX mixed-signal module float or not. CALRCOUT After calibration processing for smoothing filter in BBTX mixed-signal module, a set of 3-bit value is obtained. It is coded in 2’s complement. CMV 0x83010408 Bit 15 Name Type Reset BBTX_AC_CON 2 BBTX DAC Analog-Circuit Control Register 2 14 13 12 11 10 9 8 DCCOARSE DCCOARSEI Q R/W 00 R/W 00 7 6 5 4 3 2 DAC_PTR DWAE N COARSE R/W 000 R/W 0 R/W 0 1 0 CALR CALR CAUT COPE OL N R/W R/W 0 0 Set this register for analog circuit configuration controls. CALRCOPEN The register field is used to control normal Mode( close loop) or debug mode (open loop) for BBTX comparator in mixed signal 0 normal Mode (close loop) 1 debug Mode (open Loop) CALRCAUTO The register field is used to control the result of calibration process of smoothing filter can automatically load to control the smoothing filter or not. 0 Not auto load, need manual load (default) 539/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 1 Auto load The register field is used to control the central nominal value of BBTX DAC output COARSE 00 01 central nominal @ 1V central nominal @ 1V –0.2V 10 reserved 11 central nominal @ 1V +0.2V DWAEN The register field is used to turn on the DWA scheme of the BBTX DAC, 0 DWA scheme off (default) 1 DWA scheme on DACPTR The register field is used to configured the staring pointer of 1 hot pulling of LSB[7:0] signal to BBTX DAC, range from 0~7. There is two different configuration. For DWAEN = 0, pointer always starts from the configuration value (e.g. if DACPTR = 3’b1, 1 hot will start pulling from LSB[1]). However, for DWAEN=1, the initial starting pointer will follow the configuration, while the pointer will move to most significant 1 hot pointer + 1 from the last LSB[7:0] input. ( e.g. if DACPTR = 3’b1,and LSB[7:0] maybe 8’b00001110, then the next starting poiter will starts from LSB[4].). Defulat value is 0h. DCCOARSEI 00 01 The register field is used to control the central nominal value of BBTX DAC for I channel offset central nominal @ +0mV central nominal @ +30mV 11 central nominal @ - 30mV 10 reserved DCCOARSEQ The register field is used to control the central nominal value of BBTX DAC for Q channel offset 00 01 central nominal @ +0mV central nominal @ +30mV 11 central nominal @ - 30mV 10 reserved 13.2.3 AFC DAC MCU APB bus registers for AFC DAC are listed as follows. 0x83010500 Bit Name Type Reset 15 AFC DAC Analog-Circuit Control Register 14 13 12 11 10 9 8 GAIN SEL R/W 0 7 6 AFC_AC_CON 5 4 3 2 11BS CALI R/W 0 R/W 0 1 0 Set this register for analog circuit configuration controls. Please refer to analog functional specification for more details. 540/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 GAINSEL gain selection of output swing 0 3/4VDD 1 Full VDD 11BS Test purpose. Degrade the resolution of AFC from 13 bits to 11 bits CALI biasing current control 13.2.4 APC DAC MCU APB bus registers for APC DAC are listed as followings. CALI biasing current control 13.2.4 APC DAC MCU APB bus APC DAC Analog-Circuit Control Register APC_AC_CON registers for APC DAC are listed as followings. 0x83010600 Bit Name Type Reset 15 14 13 12 11 10 9 8 7 6 5 BYP R/W 0 4 3 2 CALI R/W 0 1 0 Set this register for analog circuit configuration controls. Please refer to analog functional specification for more details. BYP CALI bypass output buffer biasing current control 13.2.5 Auxiliary ADC MCU APB bus registers for AUX ADC are listed as followings. 0x83010700 Bit Name Type Reset 15 Auxiliary ADC Analog-Circuit Control Register 14 13 12 11 10 9 8 7 6 ENB R/W 0 5 AUX_AC_CON 4 3 2 CALI R/W 0 1 0 Set this register for analog circuit configuration controls. Please refer to analog functional specification for more details. CALI Biasing current control 541/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 ENB Comparator switch enable signal. 13.2.6 Voice Front-end MCU APB bus registers for speech are listed as followings. 0x83010100 Bit 15 AFE Voice Analog Gain Control Register 14 13 12 11 10 9 8 7 6 AFE_VAG_CON 5 Name VUPG VDPG0 Type Reset R/W 000000 R/W 0000 4 3 2 1 0 VAGC _GAI N_ST EP R/W 0 Set this register for analog PGA gains. VUPG is set for microphone input volume control. And VDPG0 and VDPG1 are set for two output volume controls VAGC_GAIN_STEP Gain step for old AGC. 0 1 dB 1 2 dB VUPG voice-band up-link PGA gain control bits. For VCFG[3] = 1, it is only valid for INPUT 1. VCFG[3] = 0 Gain value = VUPG - 20 VCFG[3] = 1 Gain value fixed at 0dB VCFG [3] =’0’ VCFG [3] =’1’ VUPG [5:0] Gain VUPG [5:0] Gain 111111 43 dB XXXXXX 0dB 111110 42 dB 111101 41 dB 111100 40 dB 111011 39 dB 111010 38 dB 111001 37 dB 111000 36 dB 110111 35 dB 110110 34 dB 110101 33 dB 110100 32 dB 110011 31dB 110010 30 dB 542/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 110001 29 dB 110000 28 dB 101111 27 dB 101110 26 dB 101101 25 dB 101100 24 dB 1101011 23 dB 101010 22 dB 101001 21 dB 101000 20 dB 100111 19 dB 100110 18 dB 100101 17 dB 100100 16 dB 100011 15 dB 100010 14 dB 100001 13 dB 100000 12 dB 011111 11 dB 011110 10 dB 011101 9 dB 011100 8 dB 011011 7 dB 011010 6 dB 011001 5 dB 011000 4 dB 010111 3 dB 010110 2 dB 010101 1 dB 010100 0 dB 010011 -1dB 010010 -2 dB 010001 -3 dB 010000 -4 dB 001111 -5 dB 001110 -6 dB 001101 -7 dB 001100 -8 dB 0101011 -9 dB 543/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 001010 -10 dB 001001 -11 dB 001000 -12 dB 000111 -13 dB 000110 -14 dB 000101 -15 dB 000100 -16 dB 000011 -17 dB 000010 -18 dB 000001 -19 dB 000000 -20 dB VDPG0 voice-band down-link PGA0 gain control bits 0x83010104 Bit VDPG0 [3:0] Gain 1111 8dB 1110 6dB 1101 4dB 1100 2dB 1011 0dB 1010 -2dB 1001 -4dB 1000 -6dB 0111 -8dB 0110 -10dB 0101 -12dB 0100 -14dB 0011 -16dB 0010 -18dB 0001 -20dB 0000 -22dB AFE Voice Analog-Circuit Control Register 0 15 14 13 12 VDC_ VMIC_ Name COUP SHOR VMIC_VREF LE T Type R/W R/W R/W Reset 0 0 00 11 10 9 8 7 6 5 AFE_VAC_CON0 4 3 2 VCFG VDSE ND0 VCALI R/W 00000 R/W 0 R/W 00000 1 0 Set this register for analog circuit configuration controls. VDC_COUPLE Selectively choose DC couple microphone sense. 544/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 0 Disable DC couple sense of microphone 1 Enable DC couple sense of microphone VMIC_SHORT Selectively short AU_MICBIASP / AU_MICBIASN. float MIC_BIASN and short it to MIC_BIASP when handsfree mode mic is plugged in short MIC_BIASN to ground when handsfree mode mic is plugged in. In this mode, differential mic has current leakage and cause power loss. VMIC_VREF Tuning MICBIASP DC voltage. 00 1.9V 01 2.0V 10 2.1V 11 2.2V VCFG[4] microphone biasing control 0 differential biasing 1 single-ended biasing VCFG[3] gain mode control. This control register is only valid to input 1. Others can be amplification mode only. 0 amplification 1 attenuation VCFG[2] coupling control 0 AC 1 DC VCFG[1:0] input select control 00 input 0 01 input 1 10 FM 11 reserved VDSEND0 single-ended configuration control for out0 VCALI biasing current control, in 2’s complement format 0 1 0x83010108 Bit Name 15 AFE Voice Analog-Circuit Control Register 1 14 13 VUPO VBIAS_EN P_EN Type R/W Reset 0 R/W 0 12 11 10 VOC_ EN VBG_CTRL R/W 0 R/W 000 9 8 7 6 AFE_VAC_CON1 5 4 3 2 1 0 VADC VADC VADC VDAC VIBO VFLO VRSD VGBO _DVR VDIFF _DEN INMO INMO OT AT ON OT EF_C _BIAS B DE DE AL R/W R/W R/W R/W R/W R/W R/W R/W R/W 1 0 0 0 0 0 0 0 0 Set this register for analog circuit configuration controls. There are several loop back modes and test modes implemented for test purposes. Suggested value is 0280h. VUPOP_EN de-pop noise enable 0: disable 1: enable VBIAS_EN voice downlink buffer bias current control 1: normal bias current 0: increase bias current 545/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 VOC_EN voice downlink buffer over current protection 0: disable 1: enable VBG_CTRL voice-band bandgap control voice downlink DAC bias current control IBOOT 0: increase bias current 1: normal bias current VFLOAT voice-band output driver float 0: normal operating mode 1: float mode VRSDON voice-band redundant signed digit function on 0: 1-bit 2-level mode 1: 2-bit 3-level mode VGBOOT VBI DAC Gain boost 0 2X 1 1X VADC_DVREF_CAL ADC Dither Reference Voltage Calibration VADC_DENB ADC Dither Enable VDIFF_BIAS Differential Bandgap Reference Activated Register 0: Single-ended reference 1: Differential reference VADCINMODE Voice-band ADC output mode. 0: normal operating mode 1: the ADC input from the DAC output VDACINMODE Voice-band DAC input mode. 0: normal operating mode 1: the DAC input from the ADC output 0x8301010C Bit 15 14 AFE_VAPDN_C ON AFE Voice Analog Power Down Control Register 13 12 11 10 9 8 7 6 5 4 3 2 VPDN VPDN VPDN VPDN _BIAS _LNA _ADC _DAC Name Type Reset R/W 0 R/W 0 R/W 0 R/W 0 1 0 VPDN _OUT 0 R/W 0 Set this register to power up analog blocks. 0: power down, 1: power up. VPDN_BIAS bias block VPDN_LNAlow noise amplifier block VPDN_ADC ADC block VPDN_DAC DAC block VPDN_OUT0 OUT0 buffer block 546/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 0x83010110 AFE Voice AGC Control Register AFE_VAGC_CO N Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 AGC_ AAGC AGCT RELNOIDUR RELNOILEV ATTC HYST DAGC FRELCKSEL SRELCKSEL ATTTHDCAL Name MODE EN EST SEL SEL KSEL EREN EN Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 00 00 00 00 00 0 0 0 Set this register for analog circuit configuration controls. There are several loop back modes and test modes implemented for test purposes. Suggested value is 4dcfh. DAGCEN Digital AGC function enable. The loop-back path of AGC comprises analog comparators and digital gain control circuitry. This control register is used to enable the digital gain control circuitry. For normal function, DAGCEN and AAGCEN shall be set to “1” to enable voice AGC function. HYSTEREN AGC hysteresis function enable ATTCKSEL attack clock selection 0: 16 KHz 1: 32 KHz ATTTHDCAL attack threshold calibration SRELCKSEL release slow clock selection 00: 1000/512 Hz 01: 1000/256 Hz 10: 1000/128 Hz 11: 1000/64 Hz FRELCKSEL release fast clock selection 00: 1000/64 Hz 01: 1000/32 Hz 10: 1000/16 Hz 11: 1000/8 Hz RELNOILEVSEL release noise level selection 00: -8 dB 01: -14 dB 10: -20 dB 11: -26 dB RELNOIDURSEL release noise duration selection 00: 64 ms 01: 32 ms 10: 16 ms 11: 8 ms, 32768/4096 AAGCEN Analog AGC function enable. This control bit is used to enable the comparators of AGC loop-back path. AGC_MODE AGC algorithm selection. 0 New digital algorithm. 1 Original analog algorithm. 547/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 13.2.7 Audio Front-end MCU APB bus registers for audio are listed as followings. 0x83010200 Bit 15 AFE Audio Analog Gain Control Register 14 13 12 11 10 Name Type Reset 9 8 AMUT AMUT ER EL R/W R/W 0 0 7 6 AFE_AAG_CON 5 4 3 2 1 APGR APGL R/W 0000 R/W 0000 0 Set this register for analog PGA gains. AMUTER AMUTEL APGR APGL audio PGA L-channel mute control audio PGA R-channel mute control audio PGA R-channel gain control audio PGA L-channel gain control APGR [3:0] / APGL [3:0] Gain 1111 23dB 1110 20dB 1101 17dB 1100 14dB 1011 13dB 1010 8dB 1001 5dB 1000 2dB 0111 -1dB 0110 -4dB 0101 -7dB 0100 -10dB 0011 -13dB 0010 -16dB 0001 -19dB 0000 -22dB 0x83010204 Bit Name Type Reset 15 AFE Audio Analog-Circuit Control Register 14 13 12 APRO ADEP _SC OP R/W R/W 0 0 11 10 9 8 7 6 AFE_AAC_CON 5 4 3 2 ABUFSELR ABUFSELL ACALI R/W 000 R/W 000 R/W 00000 1 0 Set this register for analog circuit configuration controls. APRO_SC Short circuit protection. 548/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 0 disable 1 enable ADEPOP De-POP noise. 0 disable 1 enable ABUFSELR audio buffer R-channel input selection 00X: audio DAC R-channel output 010: voice DAC output 100: external FM R/L-channel radio output, stereo to mono 101: external FM R-channel radio output OTHERS: reserved. ABUFSELL audio buffer L-channel input selection 00X: audio DAC L-channel output 010: voice DAC output 100: external FM R/L-channel radio output, stereo to mono 101: external FM L-channel radio output OTHERS: reserved. ACALI audio bias current control, in 2’s complement format 0x83010208 Bit 15 AFE_AAPDN_C ON AFE Audio Analog Power Down Control Register 14 13 12 11 10 9 8 7 6 5 Name Type Reset 4 3 2 1 0 APDN APDN APDN APDN APDN _DAC _DAC _OUT _OUT _BIAS R L R L R/W R/W R/W R/W R/W 0 0 0 0 0 Set this register to power up analog blocks. 0: power down, 1: power up. Suggested value is 00ffh. BIAS block R-channel DAC block L-channel DAC block R-channel OUT buffer block L-channel OUT buffer block APDN_BIAS APDN_DACR APDN_DACL APDN_OUTR APDN_OUTL 0x8301020C Bit 15 14 Enhanced Audio Analog Front End Control & Parameters 13 12 11 10 9 8 7 6 5 AFE_AAC_NEW 4 3 Name BUF_BIAS MUX Type Reset R/W 0 R/W 2 1 VCM_ MODE R/W 0 0 MT6235 ehnahced audio DAC application circuitry selection and control parameters. BUF_BIAS Select buffer quasi-current. 00 Nominal bias current 01 Larger bias current 549/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 10 Smallest bias current 11 Smaller bias current MUX Mux audio DAC output to DM R/L pins. 00 FM input 01 FM input 10 Left channel DAC 11 Right channel O/P VCM_MODE Change common mode generation circuitry. 0 New VCM circuitry 1 Old VCM circuitry 13.2.8 Register setting path 0x8301000C Bit 15 14 Switch the register configuring path 13 12 11 10 9 8 Name Type Reset 7 CCI_WR_PATH 6 5 4 3 2 1 MODE AD_IN PMIC_ VBI_ M_WR F_PA WR_P WR_P _PAT TH ATH ATH H R/W R/W R/W R/W 0 0 0 0 0 ABI_ WR_P ATH R/W 0 WR_PATH 0 Switch the register setting to MCU side 1 Switch the register setting to manually control by TRACE32 through JTAG The bit is to facilitate ACD members for verifying purpose; the hardware supports write path switching, without being disturbed by existing MCU load. However, when with manually control, all register address are offset by 0x1000. For example, MCU configures AFE_AAC_NEW through the address 0x8301020c, while the manually control path take effect when configuring 0x8301120c. Notice that before finishing manual control, the register must be reset to be 0. The modem part includes BBRX, BBTX, APC, AFC, and AUXADC. AD_INF_PATH The register bit decides the input/output path of the mixed-mode module. For ABI and VBI, it can be configured to feed the pattern from AFE or from CHIP I/O (shared with A_FUNC_MODE). For BBTX, APC, and AFC, the input selection interface is divided at either MIX_DIG or CHIP I/O (also shared with A_FUNC_MODE). As for the BBRX, the output pattern can be bypass to CHIPIO with this register bit being true. The bit is for convenient debug-use in normal mode, such that the data pattern can be observed or be feed-in by external device, while control register setting still comes from the chip internally(By use of JTAG). It should be notice that this special debug mode should be accompanied by proper setting of GPIO, which decides the PAD OE when in normal function. 0 data pattern comes from chip internally, and the output data cannot be bypassed to chip I/O 1 analog debug mode in normal function 550/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 13.2.9 Power Management Control Power management unit, so called PMU, is integrated into analog part. To facilitate software control and interface design, PMU control share the CCI interface along with other analog parts, such as BBTX, BBRX, and ABI, etc. 13.2.9.1 Block Description Low Dropout Regulators ( LDOs ), Buck converterand Reference The PMU Integrates 12 LDOs that are optimized for their given functions by balancing quiescent current, dropout voltage, line/load regulation, ripple rejection, and output noise. RF LDO (Vrf) The RF LDO is a linear regulator that could source 250mA (max) with 2.8V output voltage. It supplies the RF circuitry of the handset. The LDO is optimized for high performance and adequate quiescent current. Digital Core Buck Converter (Vcore) The digital core regulator is a DC-DC step-down converter (Buck converter) that could source 350mA (max) with 1.2V to 0.9V programmable output voltage based on software register setting. It supplies the baseband circuitry of the SoC. The buck converter is optimized for high efficiency and low quiescent current. Digital IO LDO (Vio) The digital IO LDO is a linear regulator that could source 100mA (max) with 2.8V output voltage. It supplies the baseband circuitry of the SoC. The LDO is optimized for very low quiescent current and turns on automatically together with Vm/Va LDOs. Analog LDO (Va) The analog LDO is a linear regulator that could source 125mA (max) with 2.8V output voltage. It supplies the analog sections of the SoC. The LDO is optimized for low frequency ripple rejection in order to reject the ripple coming from the burst at 217Hz of RF power amplifier. TCXO LDO (Vtcxo) The TCXO LDO is a linear regulator that could source 40mA (max) with 2.8V output voltage. It supplies the temperature compensated crystal oscillator, which needs ultra low noise supply with very good ripple rejection. Two-Step RTC LDO (Vrtc) The two-step RTC LDO is a set of regulators that could source 600µA (max) with 1.2V output voltage. The first-step LDO charges up a capacitor-type backup coin cell to 2.6V; the second-step LDO utilizes the backup coin to regulate the 1.2V Vrtc which supplies the real-time clock module even at the absence of the battery. The first-step LDO features the reverse current protection and the second-step LDO is optimized for ultra low quiescent current while sustaining the RTC function as long as possible. 551/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 Memory LDO (Vm) The memory LDO is a linear regulator that could source 300mA (max) with 1.8V or 2.8V output voltage selection based on the supply specification of memory chips. It supplies the memory circuitry in the handset. The LDO is optimized for very low quiescent current with wide output loading range. SIM LDO (Vsim) The SIM LDO is a linear regulator that could source 80mA (max) with 1.8V or 3.0V output voltage selection based on the supply specs of subscriber identity modules (SIM) card. It supplies the SIM card and SIM level shifter circuitry in the handset. The Vsim LDO is controlled independently by the register named VSIM_EN. SIM2 LDO (Vsim2) The SIM2 LDO is a linear regulator that could source 20mA (max) with 1.8V or 3.0V output voltage selection based on the supply specs of the 2nd subscriber identity modules (SIM) card. It supplies the 2nd SIM card and SIM level shifter circuitry in the handset. The Vsim2 LDO is controlled independently by the register named VSIM2_EN. USB LDO (Vusb) The USB LDO is a linear regulator that could source 75mA (max) with 3.3V output dedicated for USB circuitry. It is controlled independently by the register named VUSB_EN. Memory Card / Bluetooth LDO (Vbt) The VBT LDO is a linear regulator that could source 100mA (max) with 2.8V or 3.0V output for memory card or Bluetooth module. It is controlled independently by the register named VBT_EN. Analog Camera LDO (Vcam_a) The VCAM_A LDO is a linear regulator that could source 250mA (max) with 1.5V, 1.8V, 2.5V or 2.8V output which is selected by the register named VCAM_A_SEL[1:0]. It supplies the analog power of the camera module. VCAM_A is controlled independently by the register named VCAM_A_EN. Digital Camera LDO (Vcam_d) The VCAM_D LDO is a linear regulator that could source 75mA (max) with 1.3V, 1.5V, 1.8V or 2.8V output which is selected by the register named VCAM_D_SEL[1:0]. It supplies the digital power of the camera module. VCAM_D is controlled independently by the register named VCAM_D_EN. 552/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 Reference Voltage Output (Vref) The reference voltage output is a low noise, high PSRR and high precision reference with a guaranteed accuracy of 1.5% over temperature. It is used as the voltage reference in PMU internally. For the sake of accuracy, special care should be taken for the Vref output. Avoid loading the reference voltage and bypass Vref to GND with 100 nF minimum. SIM Card Interface There are two SIM card interface modules to support two SIM cards simultaneously. The SIM card interface circuitry of PMU meets all ETSI and IMT-2000 SIM interface requirements. It provides level shifting needs for low voltage GSM controller to communicate with either 1.8V or 3V SIM cards. All SIM cards contain a clock input, a reset input, and a bi-directional data input/output. The clock and reset inputs to SIM cards are level shifted from the supply of digital IO (Vio) of baseband chipset to the SIM supply (Vsim). The bi-directional data bus is internal pull high to Vsim via 10kohm resistor. The 2nd SIM card interface can be used for supporting another SIM card or mobile TV. The interface pins such as SIO2/SRST2/SCLK2 can be configured as GPIO when there is no need to use the 2nd SIM card interface. All pins that connect to the SIM card (Vsim, SRST, SCLK, SIO) withstand over ??(5kV) of human body mode ESD. In order to ensure proper ESD protection, careful board layout is required. Vibrator and Keypad LED Switches Two built-in open-drain output switches drive the vibrator motor and Keypad LED in the handset. Each switch is controlled by baseband with enable registers. The switch of keypad LED can sink 150mA. The switch of vibrator can sink 250mA. And both the open-drain output switches are high impedance when disabled. Power-on Sequence and Protection Logic The PMU handles the powering ON and OFF of the handset. There are three ways to power-on the handset system : Push PWRKEY (Pull the PWRKEY pin to the low level) RTC module generate PWRBB to wakeup the system Valid charger plug-in (CHRIN voltage is within the valid range) Pulling PWRKEY low is the typical way to turn on the handset. The Vcore buck converter will be turned-on first, and then Va/Vio/Vm LDOs turn-on at the same time. After that, the supplies for the baseband are ready and it will send the PWRBB signal back to PMU for acknowledgement. To successfully power-on the handset, PWRKEY should be kept low until PMU receives the PWRBB from BB. Besides, the system reset ends at the moment when the Vcore/Va/Vio/Vm are fully turned-on to ensure the correct timing and function. If the RTC module is scheduled to wakeup the handset at some time, the PWRBB signal will directly control the PMU. In this case, PWRBB becomes high at the specific moment and let PMU power-on just like the on-sequence described above. This is the case named RTC alarm. Charger plugging-in will also turn on the handset if the charger is a valid charger. However, if the battery voltage is too low to power-on the handset (UVLO state), the system won’t be turned-on by any of the three ways. In this case, charger will charge the battery first and the handset will be powered-on automatically as long as the battery voltage is high enough. Table 1 shows states of the handset and the regulators Table 1. States of Mobile Handset and regulator 553/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 Vrtc Phone State CHRON UVLO PWRKEY && (~PWRBB) Vtcxo, Vrf (1 step) Vcore, Vio, Vm, Va st No Battery or Vbat < 2.5V X H X Off Off Off 2.5V < Vbat < 3.2V L H X On Off Off Pre-Charging H H X On Off Off Charger-on (Vbat>3.2V) H L X On On On Switched off L L H On Off Off Stand-by L L L On On Off Active L L L On On On Under-voltage Lockout (UVLO) The UVLO state in the PMU prevents startup if the initial voltage of the main battery is below the 3.2V threshold. It ensures that the handset is powered-on with the battery in good condition. The UVLO function is performed by a hysteretic comparator which can ensure the smooth power-on sequence. In addition, when the battery voltage is getting lower and lower, it will enter UVLO state and the PMU will be turned-off by itself, except for Vrtc LDO, to prevent further discharging. Once the PMU enters UVLO state, it draws low quiescent current. The 1st-step RTC LDO is still working until the DDLO disables it. Deep Discharge Lockout (DDLO) PMU will enter to the deep discharge lockout (DDLO) state when the battery voltage drops below 2.5V. In this state, the 1st step Vrtc LDO will be shutdown. Besides, it draws very low quiescent current to prevent further discharging or even damage to the cells. Reset The PMU contains a reset control circuit which takes effect at both power-up and power-down. The SYSRST pin is held at low in the beginning of power-up and returns to high after the pre-determined delay time. The delay is set by an external capacitor on RSTCAP: t Delay = 2 ms × CRSTCAP nF (1) At power-off, RESET will return to low immediately without any delay. 554/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 Over-temperature Protection If the die temperature of PMU exceeds 150°C, the PMU will automatically disable all the LDOs except the Vrtc. Once the over-temperature state is resolved, a new power on sequence is required to enable the LDOs. Battery Charger The battery charger is optimized for the Li-ion batteries. The typical charging procedure can be divided into three phases: pre-charging, constant current mode charging, and constant voltage mode charging. Figure 2 shows the flow chart of the charging procedure. Most of the charger circuits are integrated in the PMU except for one PMOS, one diode and one accurate resistor for current sensing. Those components should be applied externally. 555/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 NO-CHARGING CHARGER DETECTOR CHRIN > BATSNS NO YES VBAT > 3.2V YES NO PRE-CHARGING CONSTANT CURRENT MODE VBAT > 4.2V NO YES CONSTANT VOLTAGE MODE VBAT > 4.3V (OV) NO YES CHARGER OFF NO VBAT < 4.3V YES Figure 2. Battery Charger Flow Chart Charge Detection The PMU charger block has a detection circuit that senses the charger plug-in/out and provides the correct information to the baseband. If the CHRIN voltage is over 7V, the detection circuit reports invalid charger and CHRDET signal goes low to stop charging. Pre-Charging mode When the battery voltage is below the UVLO threshold, the charging status is in the pre-charging mode. There are two steps in this mode. While the battery voltage is deeply discharged below 2V, a 10mA trickle current generated internally charges the battery. When the battery voltage exceeds 2V, the closed-loop pre-charge mode is enabled, which allows 10mV (typically) voltage drop across the external current sense resistor. The pre-charge current can be calculated: 556/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 I PRE _ CHARGING = VSENSE 10mV = RSENSE RSENSE (2) Constant Current Charging Mode Once the battery voltage has exceeded the UVLO threshold, the charger will switch to the constant current charging mode. It allows up to 800mA constant charging current which is controlled by the registers. The relation between the voltage drop across the external current sense resistor and the charging current is as follows, I CONSTANT = VSENSE RSENSE (3) Before the battery voltage reaches 4.2V, the charger will be in the constant current charging mode. Constant Voltage Charging Mode If the battery voltage has reached 4.2V, a constant voltage is applied to the battery and keeps it at 4.2V. As the charger is kept in the constant voltage charging mode, the charging current will be lower and lower until the charge completion. The charge termination is determined by the baseband, which will set the register CHR_EN to stop the charger. Once the battery voltage exceeds 4.3V, a hardware over voltage protection (OV) should be activated and turn off the charger immediately. External Components Selection Input Capacitor Selection For each of input pins (VBAT) of PMU, a local bypass capacitor is recommended. Use a 10µF, low ESR capacitor. MLCC capacitors provide the best combination of low ESR and small size. Using a 10µF Tantalum capacitor with a small (1µF or 2.2µF) ceramic in parallel is an alternative low cost solution. For charger input pin (CHRIN), a bypass 1µF ceramic capacitor is recommended. LDO/Buck converter Capacitor/inductor Selection The analog and RF LDOs require a 4.7µF capacitor, the digital core buck converter requires a 2.2uF capacitor??, and the other LDOs require a 1µF capacitor. Large value capacitor may be used for desired noise or PSRR requirement. But the acceptable settling time should be taken into consideration. The MLCC X5R type capacitors must be used with VRF, VTCXO, VCAM_A and VA LDOs for good system performance. For other LDOs, MLCC X5R type capacitors are also recommended to use. 557/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 RESET Capacitor Selection RESET is held low at power-up until a delay time when LDOs are on. The delay is set by an external capacitor on RESCAP pin. It can be determined by the Eq.(1). For example, a 100nF capacitor can produce 200ms delay. Setting the Charge Current PMU is capable of charging battery. The charging current is controlled with an external sense resistor, Rsense. It is calculated as the Eq.(3). If the charge current is pre-defined, Rsense can be determined. Accurate sense resistors are available from the following vendors: Vishay Dale, IRC, Panasonic. Charger FET Selection The PMOS FET selection used in charger should consider the minimum drain-source breakdown voltage (BVDS), the minimum turn-on threshold voltage (VGS), and heat-dissipating ability. These specifications can be calculated as below: VGS = VCHRIN - VGATEDRV VDS = VCHRIN - VDIODE - VSENSE - VBAT RDS(ON) = VDS ICHR PDISS = ( VCHRIN-VDIODE-VSENSE-VBAT) x ICHR Appropriate PMOS FETs are available from the following vendors: Siliconix, IR, Fairchild. Charger Diode Selection The diode is used to prevent the battery from discharging through the PMOS’s body diode into the charger’s internal circuits. Choose a diode with sufficient current rating to handle the battery charging current and voltage rating greater than Vbat. Layout Guideline Use the general guidelines listed below to design the printed circuit boards: 1. Split battery connection to the VBAT, VBATRF and AVBAT pins for PMU. Place the input capacitor as close to the power pins as possible. 2. Va and Vtcxo capacitors should be returned to AGND. Vrf capacitor should be returned to AGND_RF. 3. Split the ground connection. Use separate traces or planes for the analog, digital, and power grounds (i.e. AGND, AGND_RF, DGND, PGND pins of PMU, respectively) and tie them together at a single point, preferably close to battery return. 4. Place a separate trace from the BATSNS pin to the battery input to prevent voltage drop error when sensing the battery voltage. 5. Kelvin-connect the charge current sense resistor by placing separate traces to the BATSNS and ISENSE pins. Make sure that the traces are terminated as close to the resistor’s body as possible. 6. Careful use of copper area, weight, and multi-layer construction will help to improve thermal performance. 13.2.9.2 13.2.9.2.1 Functional Specification Electrical Characteristics VBAT = 3 V ~ 5 V, minimum loads applied on all outputs, unless other noted. Typical values are at TA = 25 °C. 558/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 Parameter Conditions Min. Typical Max. Unit Switch-Off Mode: Supply Current VBAT < 2.5 V 2.5 V < VBAT < 3.3 V 3.3 V < VBAT TBD TBD RTC LDO OFF VBAT=3.3V µA µA TBD VBAT=4.2V µA Operation: Supply Current VBAT=4.2V TBD µA VBAT=4.2V VSIM, VSIM2, VTXCO, VRF, VUSB, VCAM_A, VCAM_D, VBT off; all others on TBD µA All outputs on Under Voltage (UV) Under voltage falling threshold 1 UV_SEL[1:0] = 00 Under voltage falling threshold 2 Under voltage falling threshold 3 Under voltage falling threshold 4 UV_SEL[1:0] = Under voltage rising threshold 01 10 UV_SEL[1:0] = 11 UV_SEL[1:0] = xx UV_SEL[1:0] = 2.85 2.7 2.55 2.35 3.1 2.9 2.75 2.6 2.5 3.2 2.95 2.8 2.65 2.65 3.3 V V V V V Reset Generator Output High Output Low Output Current On Delay Time per Unit Capacitance VIO-0.5 4 V V mA ms/nF 0.3*VBAT V V 0.2 1.5 TBD 2.5 Power Key Input High Voltage Low Voltage 0.7*VBAT Control Input Voltage Other Control Input High Other Control Input Low 2.0 V 0.5 Thermal Shutdown Threshold Hysteresis LDO Enable Response Time 13.2.9.2.2 150 40 250 degree degree µs Regulator Output Parameter Conditions Min. Typical Max. Unit 1.7 1.4 1.1 1.8 1.5 1.2 350 1.9 1.6 1.3 V V V mA Digital Core Voltage Output voltage (V_D) Register VOSEL=0 Register VO_SEL=1 Output current (Id_max) 559/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 Line regulation Load regulation TBD TBD mV mV 2.9 V mA mV mV Digital IO Voltage Output voltage (V_IO) 2.7 Output current (Iio_max) 2.8 100 TBD TBD Line regulation Load regulation RF Voltage Output voltage (V_A) 2.7 Output current (Ia_max) 2.8 250 TBD TBD Line regulation Load regulation Output noise voltage Ripple rejection f = 1k Hz to 100 kHz at 1kHz Analog Voltage Output voltage (V_A) 40 65 2.7 Output current (Ia_max) 2.8 125 Load regulation Ripple rejection 2.9 TBD TBD Line regulation Output noise voltage 2.9 f = 10 Hz to 100 kHz 10 Hz < freq. < 3 kHz 3 kHz < freq. < 1 MHz 50 65 40 V mA mV mV uVrms dB V mA mV mV uVrms dB dB VTCXO Voltage Output voltage (V_TCXO) 2.7 Output current (Itcxo_max) 2.8 40 TBD TBD Line regulation Load regulation Output noise voltage Ripple rejection 2.9 f = 10 Hz to 100 kHz 10 Hz < freq. < 3 kHz 3 kHz < freq. < 1 MHz 50 65 40 V mA mV mV µVrms dB dB RTC Voltage 1st stage output voltage 2nd stage output voltage (V_RTC) Output current limit (Irtc_max) RTC_SEL=H 1st stage RTC 2.5 TBD 2.6 1.2 0.6 1 TBD TBD V V mA µA 1.7 2.7 1.8 2.8 300 1.9 2.9 TBD TBD V V mA mV mV 1.89 V Off reverse input current External Memory Voltage Output voltage (V_M) VMSEL=L VMSEL=H Output current (Im_max) Line regulation Load regulation SIM Voltage Output voltage (V_SIM) Register VSIM_SEL=L 560/599 1.71 1.8 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 Register VSIM_SEL=H 2.82 Output current (Isim_max) 3.0 80 3.18 TBD TBD Line regulation Load regulation V mA mV mV SIM2 Voltage Output voltage (V_SIM2) Register VSIM2_SEL=L Register VSIM2_SEL=H 1.71 2.82 Output current (Isim2_max) 1.8 3.0 20 1.89 3.18 TBD TBD Line regulation Load regulation V V mA mV mV Memory card/Blue-Tooth Voltage Output voltage (V_BT) Register VBT_SEL=L Register VBT_SEL=H 2.7 2.8 Output current (Ibt_max) 2.8 3.0 100 2.9 3.2 TBD TBD Line regulation Load regulation V V mA mV mV USB Voltage 2.97 Output voltage (V_USB) Output current (Iusb_max) 3.3 75 Line regulation Load regulation 3.63 TBD TBD V mA mV mV Digital Camera Voltage Output voltage (V_CAM_D) Register VCAM_D_SEL=00 Register VCAM_D_SEL=01 Register VCAM_D_SEL=10 Register VCAM_D_SEL=11 1.4 1.5 1.6 V 1.7 1.8 1.9 V 2.4 2.5 2.6 V 2.7 2.8 75 2.9 TBD TBD V mA mV mV Output current (Icamera_max) Line regulation Load regulation Analog Camera Voltage Output voltage (V_CAM_A) Register VCAM_A_SEL=00 Register VCAM_A_SEL=01 Register VCAM_A_SEL=10 Register VCAM_A_SEL=11 Output current (Icamera_max) 1.2 1.3 1.4 V 1.4 1.5 1.6 V 1.7 1.8 1.9 V 2.7 2.8 250 2.9 V mA mV mV TBD TBD Line regulation Load regulation 561/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 LED /Vibrator Driver Sink Current of Key-Pad LED Driver Von<0.5V 150 mA Sink Current of Vibrator Driver Von<0.5V 250 mA 13.2.9.2.3 SIM interface Parameter Conditions Min. Typical Max. Unit 0.4 V Interface to 3 V SIM Card Volrst I = 20 µA Vohrst I = -200 µA Volclk I = 20 µA Vohclk I = -200 µA Vihsio , Vohsio Iil I = ±20 µA Vil = 0 V Vol Iol = 1 mA 0.9*VSI M V 0.4 0.9*VSI M VSIM-0.4 V V -1 0.15*VSI M V mA V Interface to 1.8 V SIM Card Volrst I = 20 µA Vohrst I = -200 µA Volclk I = 20 µA Vohclk I = -200 µA 0.2*VSI M 0.9*VSI M V 0.2*VSI M 0.9*VSI M 0.15*VSI M I = ±20 µA Vil = 0 V Vol Iol = 1 mA V V Vil Vihsio , Vohsio Iil V VSIM-0.4 -1 0.15*VSI M V V mA V SIM Card Interface Timing SIO pull-up resistance to VSIM SRST, SIO rise/fall times SCLK rise/fall times SCLK frequency SCLK duty cycle 8 VSIM = 3, 1.8 V, load with 30 pF VSIM = 3 V, CLK load with 30 pF VSIM = 1.8 V, CLK load with 30 pF CLK load with 30 pF SIMCLK Duty = 50%, fsimclk = 5 MHz 562/599 10 12 1 kΩ µs 18 ns 50 ns 5 47 MHz 53 % MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 SCLK propagation delay 13.2.9.2.4 30 50 ns Max. Unit Charger Circuit Parameter Conditions Min. Typical AC charger input voltage 4.2 8 V AC charger detect on threshold (Vchg_on) VBAT<3.2V 4.2 7 V VBAT +120mV 7 V VBAT>=3.2V Maximum charging current (AC charging) VBAT>=3.2V Pre-charging current VBAT<2.3V VBAT>=2.3V 0.16 / Rsense TBD 10 100 A TBD mA mA Pre-charging off threshold 3.2 V Pre-charging off hysteresis 0.3 V CC mode to CV mode threshold 4.15 BAT_ON (Vih) GATEDRV rising time (Tr) BAT_ON, or OV 4.25 V 2.4 2.6 V 1 5 µs Over voltage protection threshold (OV) 13.2.9.2.5 4.2 4.3 V Regulators and Drivers Item LDO Voltage Current 1.8V/1.2V / 0.9V 350 mA Digital core VIO 2.8V 100 mA Digital IO 3 VRF 2.8V 250 mA RF chip 4 VA 2.8V 125 mA Analog baseband 5 VRTC 1.2V 0.6 mA Real-time clock 6 VM 1.8V / 2.8V 300 mA External memory, selectable 7 VSIM 1.8V / 3.0V 80 mA SIM card, selectable 8 VTCXO 2.8V 40 mA 13/26 MHz reference clock 9 VSIM2 1.8V / 3.0V 20 mA SIM2 card, selectable 10 VUSB 3.3V 75 mA USB 1 VCORE 2 563/599 Description MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 11 VBT 12 13 2.8V / 3.0V 100 mA Memory card or Bluetooth VCAM_A 1.5V / 1.8V / 2.5V / 2.8V 250 mA Analog camera power VCAM_D 1.3V / 1.5V / 1.8V / 2.8V 75 mA Digital camera power Driver Type Current Description Open-drain NMOS switch 150 mA Drives the keypad LEDs VIBRATOR Open-drain NMOS switch 250 mA Drives the vibrator LED The output current ratings for the above drivers already include a 50% margin on their nominal current consumption, e.g. if a regulator output is listed as 150 mA, the peak consumption current is 100 mA. In the active state, the phone consumes peak output current at each driver, which must be considered for the thermal design. 13.2.9.2.6 Register Setting 0x83010800 Bit 15 Control LDO of VRF and test setting 14 13 12 11 10 9 8 7 Name TPSEL VRF_ ON_S EL VRF_CAL Type Reset R/W 0 R/W 0 R/W 0 PMIC_CON0 6 5 4 3 VRF_ PLNM ICALRF_EN OS_DI S R/W R/W 0 0 2 1 0 VRF_ VRF_ VRF_ EN_F STAT EN ORCE US R/W 0 R/W 0 RO 0 VRF_STATUS RF LDO ON/OFF Status excluding Force-Enable VRF_EN RF LDO Enable Control Signal 0 Disable 1 Enable VRF_EN_FORCE RF LDO Force-Enable Control Signal 0 Disable 1 Enable VRF_PLNMOS_DIS RF LDO Pull-low NMOS disable Signal 0 Enable pull-low 1 Disable pull-low ICALRF_EN RF LDO Bias Current Calibration Code 0 x1 1 x0.5 2 x2 3 x3 VRF_CAL RF LDO Output Voltage Calibration Code in monotonic transfer function 0000 maximum value 1111 minimum value VRF_ON_SEL RF LDO Enable Control Signal 0 enable with VTCXO_EN(equivalent to “PMIC_CON4[2] | SRCLKENA”) 564/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 1 TPSEL enable with VRF_EN Internal Node-set Selection for Mux-out on LED PAD. Reserved for the testing purpose. 0x83010804 Bit 15 Control LDO of VCORE , VRTC, and status of VIO and VM 14 13 12 VRTC VM_S VIO_S VRTC _EN_ Name TATU TATU _STA FORC S S TUS E Type RO RO R/W RO Reset 0 0 0 0 11 10 9 8 7 6 5 4 ACC_OUT_INIT R/W 1100 PMIC_CON1 3 2 1 0 VCOR FAST ADC_I PWM E_EN _SLO N_ED _FOR B W GE CE R/W R/W R/W R/W 1 1 0 0 VCORE_EN_FORCE VCORE LDO Force-Enable Control Signal for MCU write. When being read, this register returns the value of VCORE_STATUS, which is quite different from other LDO’s force enable bit 0 Disable 1 Enable ADC_IN_EDGE use positive/ negative edge as ADC_COUNTER input 0 negative 1 positive FAST_SLOW PWM switching frequency 0 26MHz divided by 32 1 26MHz divided by 16 PWMB select PWM bit resolution 0 3 bits 1 4 bits ACC_OUT_INIT PID compensator integrator initial value setup VRTC_STATUS VRTC LDO ON/OFF Status excluding Force-Enable VRTC_EN_FORCE VRTC LDO Force-Enable Control Signal 0 Disable 1 Enable VIO_STATUS VIO LDO ON/OFF Status excluding Force-Enable VM LDO ON/OFF Status excluding Force-Enable VM_STATUS 0x83010808 Bit 15 Control LDO of VIO and VM 14 13 Name VM_CAL Type Reset R/W 0 VIO_EN_FORCE 0 Disable 1 Enable ICALIO_EN 12 PMIC_CON2 11 10 9 8 ANTIU VM_E DSH_ ICALM_EN N_FO M_DN RCE R/W R/W R/W 0 0 0 7 6 5 VIO_CAL R/W 0 4 3 2 1 0 ANTIU VIO_E DSH_I ICALIO_EN N_FO O_DN RCE R/W R/W R/W 0 0 0 VIO LDO Force-Enable Control Signal VIO LDO Bias Current Calibration Code 565/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 0 x1 1 x0.5 2 x2 3 x3 ANTIUDSH_IO_DN VIO LDO Anti-Undershoot Disable Control Signal 0 Enable function 1 Disable function VIO_CAL VIO LDO Output Voltage Calibration Code 0000 maximum 1111 minimum VM_EN_FORCE VM LDO Force-Enable Control Signal 0 Disable 1 Enable ICALM_EN VM LDO Bias Current Calibration Code 0 x1 1 x0.5 2 x2 3 x3 ANTIUDSH_M_DN VM LDO Anti-Undershoot Disable Control Signal 0 Enable function 1 Disable function VM_CAL VM LDO Output Voltage Calibration Code in monotonic transfer function 0000 maximum 1111 minimum 0x8301080C Bit 15 14 Control and Status of LDO of VSIM, Calibration of VRTC 13 12 11 10 VRTC_STEP2_CAL VRTC_STEP1_CAL Type Reset R/W 0 R/W 0 9 8 7 VSIM_CAL R/W 0 6 PMIC_CON3 5 4 3 2 1 0 VSIM_ ANTIU VSIM_ VSIM_ PLNM DSH_ ICALSIM_EN EN_F STAT OS_DI SIM_D ORCE US S N R/W R/W R/W R/W RO 0 0 0 0 0 VSIM_STATUS VSIM LDO ON/OFF Status excluding Force-Enable VSIM_EN_FORCE VSIM LDO Force-Enable Control Signal 0 Disable 1 Enable ICALSIM_EN VSIM LDO Bias Current Calibration Code 0 x1 1 x0.5 2 x2 3 x3 ANTIUDSH_SIM_DN VSIM LDO Anti-Undershoot Disable Control Signal 0 Enable function 566/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 1 Disable function VSIM_PLNMOS_DIS VSIM LDO Pull-low NMOS disable Signal 0 Enable pull low 1 Disable pull low VSIM_CAL VSIM LDO Output Voltage Calibration Code in monotonic transfer function 0000 maximum value 1111 minimum value VRTC LDO1 Output Voltage Calibration Code in 2's complements monotonic transfer function for the 1st step. Configuration of the register must be followed by toggling VRTC_CAL_LATCH_EN (VRTC_STEP1_CAL -> VRTC_CAL_LATCH_EN “TRUE” -> VRTC_CAL_LATCH_EN “FALSE”) 000 nominal value 111 minimum value 011 maximum value VRTC_STEP2_CAL VRTC LDO2 Output Voltage Calibration Code in 2's complement monotonic transfer function for the 2nd step. Configuration of the register must be followed by toggling VRTC_CAL_LATCH_EN(VRTC_STEP2_CAL -> VRTC_CAL_LATCH_EN “TRUE” -> VRTC_CAL_LATCH_EN “FALSE”) 000 nominal value 111 minimum value 111 maximum value VRTC_STEP1_CAL 0x83010810 Bit 15 VRTC _CAL Name _LAT CH_E N Type R/W Reset 0 Control and Status of LDO of VTCXO and VA 14 13 12 VA_CAL R/W 0 11 10 9 8 VA_E VA_E VA_S N_SE N_FO TATU L RCE S R/W 0 R/W 0 RO 0 7 6 PMIC_CON4 5 VTCXO_CAL R/W 0 4 3 2 1 0 VTCX VTCX RG_V VTCX O_PL O_EN TCXO O_ST NMOS _FOR _EN ATUS _DIS CE R/W 0 R/W 0 R/W 0 RO 0 VCTXP_STATUS VTCXO LDO ON/OFF Status excluding Force-Enable VCTXO_EN_FORCE VTCXO LDO Force-Enable Control Signal 0 Disable 1 Enable RG_VCTXO_EN VTCXO LDO Enable Control Signal 0 Disable 1 Enable. Will force VCTXO LDO enabled discarding sleep mode control (SRCLKENA) VCTXO_PLNMOS_DIS VTCXO LDO Pull-low NMOS disable Signal 0 Enable pull low 1 Disable pull low VCTXO_CAL VTCXO LDO Output Voltage Calibration Code in monotonic transfer function 0000 maximum value 1111 minimum value 567/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 VA_STATUS VA LDO ON/OFF Status excluding Force-Enable VA_EN_FORCE VA LDO Force-Enable Control Signal 0 Disable 1 Enable VA_EN_SEL VA LDO Enable Control Selection VA_CAL VA LDO Output Voltage Calibration Code 0000 maximum value 1111 minimum value VRTC_CAL_LATCH_EN Latch enable for the VRTC calibration bits. To stabilize the VRTC right after VCORE power-on, analog PMIC unit needs to latch the VRTC_STEP1_CAL and VRTC_STEP2_CAL in advance (before VCORE power off). 0 Disable 1 Enable 0x83010814 Bit 15 CHRG Name _DIS Type RO Reset 0 Driver Control and Charger Status 14 CV RO 0 13 12 11 10 9 8 AC_D BAT_ CHR_ VSIM_ VSIM_ OVP ET ON DET SEL EN RO RO RO RO R/W R/W 0 0 0 0 0 0 7 PMIC_CON5 6 5 INT_NODE_MUX R/W 0 4 3 2 1 0 BLED GLED RLED KPLE VIBR_ _EN _EN _EN D_EN EN R/W R/W R/W R/W R/W 0 0 0 0 0 VIBR_EN Vibrator Driver Enable Control Signal 0 Disable. 1 Enable. Controlled by hardware PWM2 output signal KPLED_EN KPLED Driver Enable Control Signal 0 Disable. 1 Enable. Controlled by hardware PWM1 output signal RLED_EN Reserved GLED_EN BLED_EN VSIM_EN Reserved Reserved Only valid for analog test mode. For normal operation, this LDO enable is actually connected to “simvcc” port of SIM hardware. 0 Disable 1 Enable VSIM_SEL Only valid for analog test mode. For normal operation, this LDO voltage select is actually connected to “simsel” port of SIM hardware. VSIM LDO voltage selection 0 1.8V 1 1.3V OVP Charger OV occurred 0 AC<7V 1 AC>7V CHR_DET Charger detected 0 No charger 568/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 1 With charger. The signal is connected to EINT8(active low), acting as an internal interrupt, and can wakeup baseband chip even in sleep mode BAT_ON Battery is connected 0 Battery is connected 1 Battery is removed AC_DET AC power detected. Reserved CV CV mode Indication 0 Not in CV mode 1 In CV mode CHRG_DIS Not in Charging. Reserved. This register is used by PMU to indicate the test mode when being true. Under the test mode, the system reset, power key, and SIM card data input would come from external PMIC, rather than from PMU. INT_NODE_MUX MUX the PMU internal nodes, to be monitored by AUXADC. The function is reserved for the testing purpose. 000 GND (Reserved) 001 GND (Reserved) 010 GND (Reserved) 011 VREG12D_DCV (DC-DC internal LDO voltage) 100 internal charger BGR voltage 101 Ratioed Battery voltage 110 Ratioed ISENSE voltage 111 Ratioed CHRIN voltage 0x83010818 Bit Name 15 Charger and GPIO Control 14 GPIO_ MTV_ DRV EN Type R/W Reset 0 R/W 0 13 12 11 10 9 PMIC_CON6 8 CV_TUNE CV_RT R/W 0 R/W 0 7 CHRO N_FO RCE R/W 0 6 5 4 3 2 1 0 CLASS_D CHOFST CHR_ EN R/W 0 R/W 0 R/W 0 CHR_EN Enable Charging (CC and CV mode) 0 Disable 1 Enable CHOFST Charging Current Offset (for CC mode current calibration) 000 No offset 001 plus 1 step 010 plus 2 step 011 No offset 100 No offset 101 No offset 110 minus 2 step 111 minus 1 step 569/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 CC mode charge current level 50mA 87.5mA 150mA 225mA 300mA 450mA 650mA 800mA CLASS_D 000 001 010 011 100 101 110 111 CHRON_FORCE Charger Force-Enable Control Signal 0 Disable (normal) 1 Enable (force charge on) CV_RT Coarse tune the CV voltage according to VREF CV_TUNE Fine tune the CV voltage according to VREF 000 VBG = 1.2V 001 VBG = 1.205V 010 VBG = 1.210V 011 VBG = 1.215V 100 VBG = 1.18V 101 VBG = 1.185V 110 VBG = 1.190V 111 VBG = 1.195V MTV_EN Define Mobile TV application, the register is only for test purpose. If GPIO in normal function is intended, please refer to “General-purpose IO” chapter 0 Non-Mobile-TV application, SCLK2/SRST2/SIO2 are used as GPIO pins 1 Mobile-TV application, SCLK2/SRST2/SIO2 are used as SIM2 interface GPIO_DRV SCLK2/SRST2/SIO2 GPIO Driving Strength Control 0 8mA 1 4mA 0x8301081C Bit 15 14 PWRK Name EY_D EB Type Reset RO 0 UV_SEL 00 2.9V Start Up 13 12 11 BIAS_ OV_T OV_H GEN_ H_FR YS_E FORC EEZE NB E R/W R/W R/W 0 0 0 PMIC_CON7 10 9 IBIASSEL R/W 0 8 7 CKSE OSCE L N R/W 0 R/W 0 6 5 4 3 2 1 0 IBGSEL RBGSEL UV_SEL R/W 0 R/W 0 R/W 0 UVLO High to Low Threshold Selection 570/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 01 2.75V 10 2.6V 11 Follow DDLO RBGSEL Bandgap T.C. fine tuning 000 initial setting 001 plus 1 step 010 plus 2 step 011 plus 3 step 100 minus 4 step 101 minus 3 step 110 minus 2 step 111 minus 1 step IBGSEL Current setting for bandgap and oscillator 00 initial setting 01 plus 1 step 10 minus 2 step 11 minus 1 step Enable the oscillator in bandgap block OSCEN 0 1 Disable Enable Setting the clock rate of CKMON 0 ~10kHz 1 ~5kHz VBSSEL Internal reference current tuning (global bias of PMU) 00 VBG/1200K 01 VBG/1320K 10 VBG/960K 11 VBG/1080K BIAS_GEN_EN_FORCE Force the IBIAS/VBIAS Generator ON in the Testmode 0 Normal 1 Force on CKSEL OV_TH_HIGH Set the OV threshold when RG_OV_THFREEZE=1 0 Lower 1 Higher OV_TH_FREEZE OV threshold freeze at 4.3V 0 OV threshold auto tuning 1 Fixed OV threshold PWRKEY_DEB De-bounced PWRKEY signal 0x83010820 Bit 15 DC-DC controller for VCORE 14 13 12 11 10 9 8 571/599 PMIC_CON8 7 6 5 4 3 2 1 0 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 SDM_ VOSE Name FB_E L N Type R/W R/W Reset 1 1 DUTY_INIT GAIN_D GAIN GAIN_P R/W 1000 R/W 010 R/W 100 R/W 010 SDM_ ORDE R R/W 1 SDM_ORDER select SDM order 0 1st order 1 2nd order GAIN_P PID proportional gain select MSB: 00 0.25 01 0.5 01 1 11 2 LSB: x 1.5 GAIN PID integration gain select MSB: 00 0.015625 01 0.03125 01 0.0625 11 0.125 LSB: x 1.5 GAIN_D PID derivative gain select MSB: 00 2 01 4 01 8 11 16 LSB: x 1.5 DUTY_INIT DCV test mode monitor select VOSEL vcore voltage select 0 1.8V 1 1.2V SDM_FB_EN SDM feedback path enable 0 Disable 1 Enable 0x83010824 Bit 15 DC-DC controller for VCORE 14 13 12 11 DCV_ MODE MODE MODE MODE Name TEST SEL1 CMP EN[0] SET _EN A Type R/W Reset 0 R/W 1 R/W 0 R/W 1 R/W 1 10 9 8 PMIC_CON9 7 6 ADJCKSEL ISEL R/W 100 R/W 10 572/599 5 4 DIRE DCV_ CT_C CK_S TRL_ EL EN R/W R/W 1 0 3 2 1 0 VFBADJ R/W 1000 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 VFBADJ output voltage soft adjustment(4 bits resolution)“0000” ~ “1111” 16 step, 50mV/step when not in sleep mode(SRLKENA high) 0000 minimum: 0.8V 1111 maximum: 1.6V DIRECT_CTRL_EN voltage feedback direct feed through 0 DVFS 1 direct feed through DCV_CK_SEL DCV digital PWM clock source select 0 internal free run ring oscillator 1 CLK_TCXO ISEL reference gen bias current select 00 0.25X 01 1.5X 10 1X 11 2X ADJCKSEL internal free run ring oscilltor frequency adjustment, 000~111 MODESET Manual mode setting 0 PFM mode 1 PWM mode MODEEN Enable auto mode change, bit 1 is located at PMIC_CONB[11] 0 Manual change 1 Auto mode change MODECMP select comparator entering PWM mode 0 low offset comparator 1 auto-zero comparator MODESEL1A Select average current mode 0 NCD mode 1 average current mode DCV_TEST_EN DCV test mode enable 0 normal mode 1 test mode 0x83010828 Bit Name Type Reset 15 14 RSEL R/W 01 DC-DC controller for VCORE 13 12 IASEL R/W 01 11 10 9 DCVTRIM R/W 011 8 7 NCDOF R/W 10 PMIC_CONA 6 5 4 3 PFMSEL R/W 0000110 2 1 0 PFMSEL[3:0] PFM max load current select (constant bias) 3 160mA 2 80mA 573/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 1 40mA 0 20mA PFMSEL[6:4] PFM max load current select (proportional to Vin) 6 50ohm 5 100phm 4 200ohm NCDOF NCD comparator offset 00 -3mV 01 5mV 10 12mV 11 17mV DCVTRIM reference voltage trimming . Each step = 10mV (for Vout=1.2V ) IASEL select vavgl 00 50mV 01 100mV 10 150mV 11 200mV RSEL curdet bias current select 00 32k 01 28k 10 24k 11 18k 0x8301082C Bit 15 Control and Status of LDO of VUSB 14 13 12 11 10 9 8 Name VFBADJ_SLP MODE N[1] VUSB_CAL Type Reset R/W 0000 R/W 0 R/W 0 VUSB_STATUS VUSB_EN_FORCE 0 Disable 1 Enable VUSB_EN 0 Disable 1 Enable ICALUSB_EN 0 x1 1 x0.5 2 x2 3 x3 ANTIUDSH_USB_DN 7 PMIC_CONB 6 VUSB _PLN MOS_ DIS R/W 0 5 4 3 2 1 0 ANTIU VSUB VUSB DSH_ ICALUSB_E VUSB _EN_ _STA USB_ N _EN FORC TUS DN E R/W R/W R/W R/W RO 0 0 0 0 0 VUSB LDO ON/OFF Status excluding Force-Enable VUSB LDO Force-Enable Control Signal VUSB LDO Enable Control Signal VUSB LDO Bias Current Calibration Code VUSB LDO Anti-Undershoot Disable Control Signal 574/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 0 Enable function 1 Disable function VUSB_PLNMOS_DIS VUSB LDO Pull-low NMOS disable Signal 0 Enable pull low 1 Disable pull low VUSB_CAL VUSB LDO Output Voltage Calibration Code in monotonic transfer function 0000 maximum value 1111 minimum value VFBADJ_SLP output voltage soft adjustment(4 bits resolution)“0000” ~ “1111” 16 step, 50mV/step when in sleep mode(SRLKENA low) 0000 minimum: 0.8V 1111 maximum: 1.6V 0x83010830 Bit 15 Control and Status of LDO of VSIM2 14 VSIM2 VSIM2 _SEL _EN Type R/W Reset 0 R/W 0 13 12 VSIM_ PWR_ SAVIN G R/W 0 11 VTCX O_ON _SEL R/W 0 10 CLK_ SOUR CE_S EL R/W 0 9 8 7 PMIC_CONC 6 VSIM2_CAL R/W 0 5 4 3 2 1 0 VSIM2 ANTIU VSIM2 VSIM2 _PLN DSH_ ICALSIM2_E _EN_ _STA MOS_ SIM2_ N FORC TUS DIS DN E R/W R/W R/W R/W RO 0 0 0 0 0 CLK_SOURCE_SEL Select 26MHz clock source for VCORE PWM control 0 2.8V 26MHz directly from CLKSQ 1 1.2V 26MHz clock from TCXO26M_CK VTCXO_ON_SEL VTCXO LDO enable control signal 0 Enable with VTCXO_EN (equivalent to “PMIC_CON4[2] | SRCLKENA”) 1 Enable with RG_VTCXO_EN(PMIC_CON4[2]) VSIM2_STATUS VSIM2_EN_FORCE 0 Disable 1 Enable ICALSIM2_EN 0 x1 1 x0.5 2 x2 3 x3 ANTIUDSH_SIM2_DN 0 Enable function 1 Disable function VSIM2_PLNMOS_DIS 0 Disable pull low 1 Enable pull low VSIM LDO ON/OFF Status excluding Force-Enable VSIM LDO Force-Enable Control Signal VSIM LDO Bias Current Calibration Code VSIM LDO Anti-Undershoot Disable Control Signal VSIM LDO Pull-low NMOS disable Signal 575/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 VSIM LDO Output Voltage Calibration Code in monotonic transfer function VSIM2_CAL 0000 1111 VSIM2_EN maximum value minimum value Only valid for analog test mode. For normal operation, this LDO enable is actually connected to “simvcc” port of SIM hardware. 0 Disable 1 Enable VSIM2_SEL Only valid for analog test mode. For normal operation, this LDO voltage select is actually connected to “simsel” port of SIM hardware. VSIM LDO voltage selection 0 1.8V 1 1.3V VSIM_PWR_SAVING Used for power saving. Since design topology of SIM LS, SIM data out path tends to conduct leakage current when VSIM LDO is not enable if default SIM data output is kept low. If the power saving is enabled, SIM data output will keep high before VSIM LDO is turned on. 0 Disable 1 Enable 0x83010834 Bit 15 Control and Status of LDO of VBT 14 VBT_ VBT_ SEL EN Type R/W Reset 0 R/W 0 13 12 11 10 9 8 PMIC_COND 7 VBT_CAL R/W 0 6 5 4 3 2 1 0 VBT_ ANTIU VBT_ VBT_ PLNM DSH_ ICALBT_EN EN_F STAT OS_DI BT_D ORCE US S N R/W R/W R/W R/W RO 0 0 0 0 0 VBT_STATUS VBT LDO ON/OFF Status excluding Force-Enable VBT_EN_FORCE VBT LDO Force-Enable Control Signal 0 Disable 1 Enable ICALBT_EN VBT LDO Bias Current Calibration Code 0 x1 1 x0.5 2 x2 3 x3 ANTIUDSH_BT_DN VBT LDO Anti-Undershoot Disable Control Signal 0 Enable function 1 Disable function VBT_PLNMOS_DIS VBT LDO Pull-low NMOS disable Signal 0 Enable pull low 1 Disable pull low VBT_CAL VBT LDO Output Voltage Calibration Code in monotonic transfer function 576/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 0000 maximum value 1111 minimum value VBT_EN VBT LDO Enable Control Signal 0 Disable 1 Enable VBT_SEL VBT LDO Voltage Selection 0 2.8V 1 1.3V 0x83010838 Bit 15 Control and Status of LDO of Vcam_d 14 13 12 11 10 VCAM VCAM_D_SE _D_E DCV_SLEW_CTRL L N Type Reset R/W 0 R/W 0 R/W 0 9 8 7 VCAM_D_CAL R/W 0 PMIC_CONE 6 5 4 3 2 1 0 VCAM VCAM VCAM ANTIU _D_E _D_E _D_P DSH_ ICALCAM_D RA_E RA_S LNMO CAM_ _EN N_FO TATU S_DIS D_DN RCE S R/W R/W R/W R/W RO 0 0 0 0 0 VCAM_D_STATUS VCAM_D LDO ON/OFF Status excluding Force-Enable VCAM_D_EN_FORCE VCAM_D LDO Force-Enable Control Signal 0 Disable 1 Enable ICALCAM_D_EN VCAM_D LDO Bias Current Calibration Code 0 x1 1 x0.5 2 x2 3 x3 ANTIUDSH_CAM_D_DN VCAM_D LDO Anti-Undershoot Disable Control Signal 0 Enable function 1 Disable function VCAM_D_PLNMOS_DIS VCAM_D LDO Pull-low NMOS disable Signal 0 Enable pull low 1 Disable pull low VCAM_D_CAL VCAM_D LDO Output Voltage Calibration Code in monotonic transfer function 0000 maximum value 1111 minimum value VCAM_D_EN VCAM_D LDO Enable Control Signal 0 Disable 1 Enable VCAM_D_SEL VCAM_D LDO Voltage Selection 0 2.8V 1 1.3V DCV_SLEW_CTRL DCV power slew-rate control 577/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 0x8301083C Bit 15 14 Control and Status of LDO of Vcam_a , Vtcxo , and Va 13 12 11 10 9 OC_F VCAM ICALTCXO_E OLD_ _A_E ICALA_EN N EN N Type R/W Reset 0 R/W 0 R/W 0 8 7 6 VCAM_A_CAL R/W 0 R/W 0 5 4 PMIC_CONF 3 2 1 0 VCAM VCAM VCAM_A_SE ICALCAM_A _A_E _A_S N_FO TATU L _EN RCE S R/W R/W R/W RO 0 0 0 0 VCAM_A_STATUS VCAM_A LDO ON/OFF Status excluding Force-Enable VCAM_A_EN_FORCE VCAM_A LDO Force-Enable Control Signal 0 Disable 1 Enable ICALCAM_A_EN VCAM_A LDO Bias Current Calibration Code 0 x1 1 x0.5 2 x2 3 x3 VCAM_A_CAL VCAM_A LDO Output Voltage Calibration Code in monotonic transfer function 0000 maximum value 1111 minimum value VCAM_A_EN VCAM_A LDO Enable Control Signal 0 Disable 1 Enable VCAN_A_SEL VCAM_A LDO Voltage Selection 0 2.8V 1 1.3V ICALTCXO_EN VTCXO LDO Bias Current Calibration Code 0 x1 1 x0.5 2 x2 3 x3 ICALA_EN VA LDO Bias Current Calibration Code 0 x1 1 x0.5 2 x2 3 x3 OC_FOLD_EN Reserved 0x83010840 Bit 15 Start Up & AUXADC Related Control Register 2 14 13 12 11 10 9 8 578/599 7 6 5 PMIC_CONG 4 3 2 1 0 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 Name Type R/W Reset 0 VBAT _OUT _EN R/W R/W 0 0 ISENS E_OU T_EN R/W 0 LDO_ SOFT _ST R/W 0 TPSEL_LED R/W 0 THR_SEL VREF_BG R/W 0 R/W 0 VREF_BG Reference voltage fine tuning according to VBG 000 initial setting 001 plus 1 step 010 plus 2 step 011 plus 3 step 100 minus 4 step 101 minus 3 step 110 minus 2 step 111 minus 1 step THR_SEL Thermal shut-down threshold fine tuning 00 Initial setting 01 +10˚C 10 -20˚C 11 -10˚C LDO_SOFT_STDisable the LDO soft-start function 0 VM/VIO/VA/VTCXO has soft-start function when turning-on 1 VM/VIO/VA/VTCXO has no soft-start function when turning-on TPSEL_LED Internal Node-set Selection for Mux-out on SCLK/SRST/SCLK2/SRST2. It’s reserved for testing purpose. ISENSE_OUT_EN Pass ISENSE voltage to one of the AUXADC channel 0 Disable 1 Enable VBAT_OUT_EN Pass Battery voltage to one of the AUXADC channel 0 Disable 1 Enable 13.3 Programming Guide 13.3.1 BBRX Register Setup The register used to control analog base-band receiver is BBRX_AC_CON. 579/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 13.3.1.1 Programmable Biasing Current To maximize the yield in modern digital process, the receiver features providing 5-bit 32-level programmable current to bias internal analog blocks. The 5-bits registers CALBIAS [4:0] is coded with 2’s complement format. 13.3.1.2 Offset / Gain Calibration The base-band downlink receiver (RX), together with the base-band uplink transmitter (TX) introduced in the next section, provides necessary analog hardware for DSP algorithm to correct the mismatch and offset error. The connection for measurement of both RX/TX mismatch and gain error is shown in Figure 95, and the corresponding calibration procedure is described below. Figure 95 Base-band A/D and D/A Offset and Gain Calibration 13.3.1.3 Downlink RX Offset Error Calibration The RX offset measurement is achieved by selecting grounded input to A/D converter (set ISEL [1:0] =’11’ and QSEL [1:0] =’11’ to select channel 3 of the analog input multiplexer, as shown in Figure 96. The output of the ADC is sent to DSP for further offset cancellation. The offset cancellation accuracy depends on the number of samples being converted. That is, more accurate measurement can be obtained by collecting more samples followed by averaging algorithm. 580/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 Figure 96 Downlink ADC Offset Error Measurement 13.3.1.4 Downlink RX and Uplink TX Gain Error Calibration To measure the gain mismatch error, both I/Q uplink TXs should be programmed to produce full-scale pure sinusoidal waves output. Such signals are then fed to downlink RX for A/D conversion, in the following two steps. A. The uplink I-channel output are connected to the downlink I-channel input, and the uplink Q-channel output are connected to the downlink Q-channel input. This can be achieved by setting ISEL [1:0] =’01’ and QSEL [1:0] =’01’ (shown in Figure 97 (A)).. B. The uplink I-channel output are then connected to the downlink Q-channel input, and the uplink Q-channel output are connected to the downlink I-channel input. This can be achieved by setting ISEL [1:0] =’10’ and QSEL [1:0] =’10’ (shown in Figure 97 (B)). Figure 97 Downlink RX and Up-link TX Gain Mismatch Measurement (A) I/Q TX connect to I/Q RX (B) I/Q TX connect to Q/I RX 581/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 Once above successive procedures are completed, RX/TX gain mismatch could be easily obtained because the amplitude mismatch on RX digitized result in step A and B is the sum and difference of RX and TX gain mismatch, respectively. The gain error of the downlink RX can be corrected in the DSP section and the uplink TX gain error can be corrected by the gain trimming facility that TX block provide. 13.3.1.5 Uplink TX Offset Error Calibration Once the offset of the downlink RX is known and corrected, the offset of the uplink TX alone could be easily estimated. The offset error of TX should be corrected in the digital domain by means of the programmable feature of the digital GMSK modulator. Finally, it is important that above three calibration procedures should be exercised in order, that is, correct the RX offset first, then RX/TX gain mismatch, and finally TX offset. This is owing to that analog gain calibration in TX will affect its offset, while the digital offset correction has no effect on gain. 13.3.2 BBTX Register Setup The register used to control analog base-band transmitter is BBTX_AC_CON0 and BBTX_AC_CON1. 13.3.2.1 Output Gain Control The output swing of the uplink transmitter is controlled by register GAIN [2:0] coded in 2’s complement with about 2dB step. When TRIMI [3:0] / TRIMQ [3:0] = 0 the swing is listed in Table 61, defined to be the difference between positive and negative output signal. GAIN [2:0] Output Swing For AVDD=2.8 (V) +3 (011) AVDD*0.453 (+2.0 dB) 1.27 +2 (010) AVDD*0.418 (+1.3 dB) 1.17 +1 (001) AVDD*0.386 (+0.6 dB) 1.08 +0 (000) AVDD*0.360 (+0.00 dB) 1 -1 (111) AVDD*0.336 (-0.6dB) 0.94 -2 (110) AVDD*0.310 (-1.3 dB) 0.87 -3 (101) AVDD*0.286 (-2.0 dB) 0.80 -4 (100) AVDD*0.267 (-2.6 dB) 0.74 Table 61 Output Swing Control Table 582/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 13.3.2.2 Output Gain Trimming I/Q channels can also be trimmed separately to compensate gain mismatch in the base-band transmitter or the whole transmission path including RF module. The gain trimming is adjusted in 16 steps spread from -0.96dB to +0.84dB (Table 62), compared to the full-scale range set by GAIN [2:0]. TRIMI [3:0] / TRIMQ [3:0] Gain Step (dB) +7 (0111) 0.84 +6 (0110) 0.72 +5 (0101) 0.60 +4 (0100) 0.48 +3 (0011) 0.36 +2 (0010) 0.24 +1 (0001) 0.12 +0 (0000) 0.00 -1 (1111) -0.12 -2 (1110) -0.24 -3 (1101) -0.36 -4 (1100) -0.48 -5 (1011) -0.60 -6 (1010) -0.72 -7 (1001) -0.84 -8 (1000) -0.96 Table 62 Gain Trimming Control Table 13.3.2.3 Output Common-Mode Voltage The output common-mode voltage is controlled by CMV [2:0] with about 0.08*AVDD step, as listed in the following table. CMV [2:0] Common-Mode Voltage +3 (011) AVDD*0.62 +2 (010) AVDD*0.58 +1 (001) AVDD*0.54 +0 (000) AVDD*0.50 -1 (111) AVDD*0.46 -2 (110) AVDD*0.42 -3 (101) AVDD*0.38 -4 (100) AVDD*0.34 Table 63 Output Common-Mode Voltage Control Table 583/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 13.3.2.4 Programmable Biasing Current The transmitter features providing 5-bit 32-level programmable current to bias internal analog blocks. The 5-bits registers CALBIAS [4:0] is coded with 2’s complement format. 13.3.2.5 Smoothing Filter Characteristic The 2nd –order Butterworth smoothing filter is used to suppress the image at DAC output: it provides more than 40dB attenuation at the 4.44MHz sampling frequency. To tackle with the digital process component variation, programmable cutoff frequency control bits CALRCSEL [2:0] are included. User can directly change the filter cut-off frequency by different CALRCSEL value (coded with 2’s complement format and with a default value 0). In addition, an internal calibration process is provided, by setting START CALRC to high and CALRCCNT to an appropriate value (default is 11). After the calibration process, the filter cut-off frequency is calibrated to 350kHz +/- 50 kHz and a new CALRCOUT value is stored in the register. During the calibration process, the output of the cell is high-impedance. 13.3.3 AFC-DAC Register Setup The register used to control the APC DAC is AFC_AC_CON, which providing 5-bit 32-level programmable current to bias internal analog blocks. The 5-bits registers CALI [4:0] is coded with 2’s complement format. 13.3.4 APC-DAC Register Setup The register used to control the APC DAC is AFC_AC_CON, which providing 5-bit 32-level programmable current to bias internal analog blocks. The 5-bits registers CALI [4:0] is coded with 2’s complement format. 13.3.5 Auxiliary A/D Conversion Register Setup The register used to control the Aux-ADC is AUX_AC_CON. For this register, which providing 5-bit 32-level programmable current to bias internal analog blocks. The 5-bits registers CALI [4:0] is coded with 2’s complement format. 13.3.6 Voice-band Blocks Register Setup The registers used to control AMB are AFE_VAG_CON, AFE_VAC_CON0, AFE_VAC_CON1, and AFE_VAPDN_CON. For these registers, please refer to chapter “Analog Chip Interface” 13.3.6.1 Reference Circuit The voice-band blocks include internal bias circuits, a differential bandgap voltage reference circuit 584/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 and a differential microphone bias circuit. Internal bias current could be calibrated by varying VCALI[4:0] (coded with 2’s complement format). The differential bandgap circuit generates a low temperature dependent voltage for internal use. For proper operation, there should be an external 47nF capacitor connected between differential output pins AU_VREFP and AU_VREFN. The bandgap voltage (~1.24V6, typical) also defines the dBm0 reference level through out the audio mixed-signal blocks. The following table illustrates typical 0dBm0 voltage when uplink/downlink programmable gains are unity. For other gain setting, 0dBm0 reference level should be scaled accordingly. Symbol Parameter Min V0dBm0,UP 0dBm0 Voltage for Uplink Path, Applied Differentially Between Positive and Negative Microphone Input Pins V0dBm0,Dn 0dBm0 voltage for Downlink Path, Appeared Differentially Between Positive and Negative Power Amplifier Output Pins Typical Max Unit 0.2V V-rms 0.6V V-rms Table 64 0dBm0 reference level for unity uplink/downlink gain The microphone bias circuit generates a differential output voltage between AU_MICBIAS_P and AU_MICBIAS_N for external electret type microphone. Typical output voltage is 1.9 V. In singled-ended mode, by set VCFG[3] =1, AU_MICBIAS_N is pull down while output voltage is present on AU_MICBIAS_P, respect to ground. The max current supplied by microphone bias circuit is 2mA. 13.3.6.2 Uplink Path Uplink path of voice-band blocks includes an uplink programmable gain amplifier and a sigma-delta modulator. 13.3.6.2.1 Uplink Programmable Gain Amplifier Input to the PGA is a multiplexer controlled by VCFG [3:0], as described in the following table. In normal operation, both input AC and DC coupling are feasible for attenuation the input signal (gain <= 0dB). However, only AC coupling is suggested if amplification of input signal is desired (gain>=0dB). Control Signal Function Descriptions VCFG [0] Input Selector 0: Input 0 (From AU_VIN0_P / AU_VIN0_N) Is Selected 1: Input 1 (From AU_VIN1_P / AU_VIN1_N) Is Selected 6 The bandgap voltage could be calibrated by adjusting control signal VBG_CTRL[1:0]. Its default value is [00]. VBG_CTRL not only adjust the bandgap voltage but also vary its temperature dependence. Optimal value of VBG_CTRL is to be determined. 585/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 VCFG [1] Coupling Mode 0: AC Coupling 1: DC Coupling VCFG [2] Gain Mode 0: Amplification Mode (gain >= 0 dB) 1: Attenuation Mode (gain <= 0dB) VCFG [3] Microphone Biasing 0: Differential Biasing (Take Bias Voltage Between AU_MICBIAS_P and AU_MICBIAS_N) 1: Signal-Ended Biasing (Take Bias Voltage From AU_MICBIAS_P Respected to Ground. AU_MICBIAS_N Is Connected to Ground) Table 65 Uplink PGA input configuration setting The PGA itself provides programmable gain (through VUPG [3:0]) with step of 3dB, as listed in the following table. VCFG [2] =’0’ VCFG [2] =’1’ VUPG [3:0] Gain VUPG [3:0] Gain 1111 NA X111 -21dB 1110 42dB X110 -18dB 1101 39dB X101 -15dB 1100 36dB X100 -12dB 1011 33dB X011 -9dB 1010 30dB X010 -6dB 1001 27dB X001 -3dB 1000 24dB X000 0dB 0111 21dB 0110 18dB 0101 15dB 0100 12dB 0011 9dB 0010 6dB 0001 3dB 0000 0dB Table 66 Uplink PGA gain setting (VUPG [3:0]) The following table illustrates typically the 0dBm0 voltage applied at the microphone inputs, differentially, for several gain settings. VCFG [2] =’0’ VCFG [2] =’1’ VUPG [3:0] 0dBm0 (V-rms) VUPG [3:0] 0dBm0 (V-rms) 1100 3.17mV X110 1.59V 1000 12.6mV X100 0.8V 0100 50.2mV X010 0.4V 586/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 0000 0.2V X000 0.2V Table 67 0dBm0 voltage at microphone input pins 13.3.6.2.2 Sigma-Delta Modulator Analog-to-digital conversion in uplink path is made with a second-order sigma-delta modulator (SDM) whose sampling rate is 4096kHz. Output signals are coded in either one-bit or RSD format, optionally controlled by VRSDON register. For test purpose, one can set VADCINMODE to HI to form a look-back path from downlink DAC output to SDM input. The default value of VADCINMODE is zero. 13.3.6.3 Downlink Path Downlink path of voice-band blocks includes a digital to analog converter (DAC) and two programmable output power amplifiers. 13.3.6.3.1 Digital to Analog Converter The DAC converts input bit-stream to analog signal by sampling rate of 4096kHz. . Besides, it performs a 2nd-order 40kHz butterworth filtering. The DAC receives input signals from MT6235 DSP by set VDACINMODE = 0. It can also take inputs from SDM output by setting VDACINMODE = 1. 13.3.6.3.2 Downlink Programmable Power Amplifier Voice-band analog blocks include two identical output power amplifiers with programmable gain. Amplifier 0 and amplifier 1 can be configured to either differential or single-ended mode by adjusting VDSEND [0] and VDSEND [1], respectively. In single-ended mode, when VDSEND[0] =1, output signal is present at AU_VOUT0_P pin respect to ground. Same as VDSEND[1] for AU_VOUT1_P pin. For the amplifier itself, programmable gain setting is described in the following table. VDPG0 [3:0] / VDPG1 [3:0] Gain 1111 8dB 1110 6dB 1101 4dB 1100 2dB 1011 0dB 1010 -2dB 1001 -4dB 1000 -6dB 0111 -8dB 587/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 0110 -10dB 0101 -12dB 0100 -14dB 0011 -16dB 0010 -18dB 0001 -20dB 0000 -22dB Table 68 Downlink power amplifier gain setting Control signal VFLOAT, when set to ‘HI’, is used to make output nodes totally floating in power down mode. If VFLOAT is set to ‘LOW” in power down mode, there will be a resistor of 50k ohm (typical) between AU_VOUT0_P and AU_VOUT0_N, as well as between AU_VOUT0_P and AU_VOUT0_N. The amplifiers deliver signal power to drive external earphone. The minimum resistive load is 28 ohm and the upper limit of the output current is 50mA. On the basis that 3.14dBm0 digital input signal into downlink path produces DAC output differential voltage of 0.87V-rms (typical), the following table illustrates the power amplifier output signal level (in V-rms) and signal power for an external 32 ohm resistive load. VDPG Output Signal Level (V-rms) Output Signal Power (mW / dBm) 0010 0.11 0.37/-4.3 0110 0.27 2.28/3.6 1010 0.69 14.8/11.7 1110 1.74 94.6/19.8 Table 69 Output signal level/power for 3.14dBm0 input. External resistive load = 32 ohm The following table illustrates the output signal level and power for different resistive load when VDPG =1110. RLOAD Output Signal Level (V-rms) Output Signal Power (mW / dBm) 30 1.74 101/20 100 1.74 30.3/14.8 600 1.74 5/7 Table 70 Output signal level/power for 3.14dBm0 input, VDPG =1110 13.3.6.4 Power Down Control 588/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 Each block inside audio mixed-signal blocks features dedicated power-down control, as illustrated in the following table. Control Signal Descriptions VPDN_BIAS Power Down Reference Circuits (Active Low) VPDN_LNA Power Down Uplink PGA (Active Low) VPDN_ADC Power Down Uplink SDM (Active Low) VPDN_DAC Power Down DAC (Active Low) VPDN_OUT0 Power Down Downlink Power Amp 0 (Active Low) VPDN_OUT1 Power Down Downlink Power Amp 1 (Active Low) Table 71 Voice-band blocks power down control 13.3.7 Audio-band Blocks Register Setup The registers used to control audio blocks are AFE_AAG_CON, AFE_AAC_CON, and AFE_AAPDN_CON. For these registers, please refer to chapter “Analog Chip Interface” 13.3.7.1 Output Gain Control Audio blocks include stereo audio DACs and programmable output power amplifiers. The DACs convert input bit-stream to analog signal by sampling rate of Fs*128 where Fs could be 32kHz, 44.1kHz, or 48kHz. Besides, it performs a 2nd-order butterworth filtering. The two identical output power amplifiers with programmable gain are designed to driving external AC-coupled single-end speaker. The minimum resistor load is 16 ohm and the maximum driving current is 50mA. The programmable gain setting, controlled by APGR[] and APGL[], is the same as that of the voice-band amplifiers. Unlike voice signals, 0dBFS defines the full-scale audio signals amplitude. Based on bandgap reference voltage again, the following table illustrates the power amplifier output signal level (in V-rms) and signal power for an external 16 ohm resistive load. APGR[]/ APGL[] Output Signal Level (V-rms) Output Signal Power (mW / dBm) 0010 0.055 0.19/-7.2 0110 0.135 1.14/0.6 1010 0.345 7.44/8.7 1110 0.87 47.3/16.7 Table 72 Output signal level/power for 0dBFS input. External resistive load = 16 ohm 589/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 13.3.7.2 Mute Function and Power Down Control By setting AMUTER (AMUTEL) to high, right (Left) channel output will be muted. Each block inside audio mixed-signal blocks features dedicated power-down control, as illustrated in the following table. Control Signal Descriptions APDN_BIAS Power Down Reference Circuits (Active Low) APDN_DACL Power Down L-Channel DAC (Active Low) APDN_DACR Power Down R-Channel DAC (Active Low) APDN_OUTL Power Down L-Channel Audio Amplifier (Active Low) APDN_OUTR Power Down R-Channel Audio Amplifier (Active Low) Table 73 Audio-band blocks power down control 13.3.8 Multiplexers for Audio and Voice Amplifiers The audio/voice amplifiers feature accepting signals from various signal sources including AU_FMINR/AU_FMINL pins, that aimed to receive stereo AM/FM signal from external radio chip: 1) Voice-band amplifier 0 accepts signals from voice DAC output only. 2) Voice-band amplifier 1 accepts signal from either voice DAC, audio DAC, or AM/FM radio input pins (controlled by register VBUF1SEL[] ). For the last two cases, left and right channel signals will be summed together to form a mono signal first. 3) Audio left/right channel amplifiers receive signals from either voice DAC, audio DAC, or AM/FM radio input pins (controlled by registers ABUFSELL[] and ABUFSELR[] ), too. Left and right channel amplifiers will produce identical output waveforms when receiving mono signals from voice DAC. 13.3.9 Preferred Microphone and Earphone Connections In this section, preferred microphone and earphone connections are discussed. Differential connection of microphone is shown below. This is the preferred method to obtain the possible best performance. C1 and Rin form an AC coupling and high-pass network. C1*Rin should be chosen such that the in-band signal will not be attenuated too much. For differential minimum resistance of 13k ohm, minimum value of C1 is 170nF for less than 1dB attenuation at 300Hz. R2 is determined by microphone sensitivity. C2 and R2 form another low-pass filter to filtering noise coming from microphone bias pins. Pole frequency less than 50Hz is recommended. 590/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 Figure 6 Differential Microphone Connection For reference, single-ended connection method of microphone is shown below. R1 and R3 are chosen based on microphone sensitivity requirement. C1 and Rin form an AC coupling and high-pass network. R2 and C2 constitute a low-pass network for filtering out noise from microphone bias pins. Figure 7 Single-ended Microphone Connection For earphone, both differential and single-ended connections can be used. Advantage of differential connection includes lower cost and better click-noise immunity. For single-ended connection, an additional AC-coupling capacitor is necessary to not provide DC voltage to earphone. The high-pass cut-off frequency formed by AC-coupling capacitor and earphone equivalent load should be low enough (e.g. < 300 Hz). 591/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 13.3.10 Clock Squarer Register Setup The register used to control clock squarer is CLK_CON. For this register, please refer to chapter “Clocks” CLKSQ_PLD is used to bypass the clock squarer. 13.3.11 Phase-Locked Loop Register Setup For registers control the PLL, please refer to chapter “Clocks” and “Software Power Down Control” 13.3.11.1 Frequency Setup The DSP/MCU PLL itself could be programmable to output either 52MHz or 78MHz clocks. Accompanied with additional digital dividers, 13/26/39/52/65/78 MHz clock outputs are supported. 13.3.11.2 Programmable Biasing Current The PLLs feature providing 5-bit 32-level programmable current to bias internal analog blocks. The 5-bits registers CALI [4:0] is coded with 2’s complement format. 13.3.12 32-khz Crystal Oscillator Register Setup For registers that control the oscillator, please refer to chapter “Real Time Clock” and “Software Power Down Control”. 592/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 14 Digital Pin Electrical Characteristics z Based on I/O power supply (VDD33) = 3.3 V z Vil (max) = 0.8 V z Vih (min) = 2.0 V Name Ball 13x13 Dir G4 G3 G2 G1 H1 H2 JTRST_B JTCK JTDI JTMS JTDO JRTCK I I I I IO IO AE6 AD7 AC7 AC6 AE8 AD8 BPI_BUS0 BPI_BUS1 BPI_BUS2 BPI_BUS3 BPI_BUS4 BPI_BUS5 IO IO IO IO IO IO 2/4/6/8 2/4/6/8 2/4/6/8 2 2 2 0.4 0.4 0.4 0.4 0.4 0.4 2.4 2.4 2.4 2.4 2.4 2.4 AC8 BPI_BUS6 IO 2 0.4 AB8 BPI_BUS7 IO 2 AE9 BPI_BUS8 IO AD9 BPI_BUS9 IO Driving Iol & Ioh Typ (mA) Vol at Iol Max Voh at Ioh Min PU/PD Resistor (V) (V) Min Typ Pull Cin (pF) Max JTAG Port 40K 40K 40K 40K 75K 75K 75K 75K 190K 190K 190K 190K PD PU PU PU 2 2 2 2 40K 75K 190K PU/PD 2 2.4 40K 75K 190K PU/PD 2 0.4 2.4 40K 75K 190K PU/PD 2 2 0.4 2.4 40K 75K 190K PU/PD 2 2 0.4 2.4 40K 75K 190K PU/PD 2 75K 75K 75K 75K 190K 190K 190K 190K PU/PD PU/PD PU/PD PU/PD 2 2 2 2 75K 75K 190K 190K PU/PD PU/PD 2 2 2/4 2/4 0.4 0.4 2.4 2.4 RF Parallel Control Unit RF Serial Control Unit AC9 BSI_CS0 AE10 BSI_DATA AD10 BSI_CLK IO IO IO AC10 AB10 AC5 AE5 PWM0 PWM1 PWM2 PWM3 IO IO IO IO AE4 AD5 SCL SDA IO IO 2 2/4/6/8 2 0.4 0.4 0.4 2.4 2.4 2.4 0.4 0.4 2.4 2.4 0.4 2.4 40K 40K 40K 40K 2.4 2.4 40K 40K PWM Interface 2/4/6/8 2 4/8 4/8 Camera Control Interface 4/8/12/16 4/8/12/16 0.4 0.4 Serial LCD/PM IC Interface 593/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 AC11 U11 AD12 AE12 AC12 LSCK LSA0 LSDA LSCE0B LSCE1B IO IO IO IO IO 2/4/6/8 2/4/6/8 2/4/6/8 2/4/6/8 2/4/6/8 0.4 0.4 0.4 0.4 0.4 2.4 2.4 2.4 2.4 2.4 40K 40K 40K 40K 40K 75K 75K 75K 75K 75K 190K 190K 190K 190K 190K PU/PD PU/PD PU/PD PU/PD PU/PD 2 2 2 2 2 40K 75K 190K PU/PD 2 Parallel LCD/NAND-Flash Interface AB12 U12 AE13 AC13 AD13 U13 AE14 AD14 AC14 AB14 U14 AE15 AD15 LPCE1B LPCE0B LPTE LRSTB LRDB LPA0 LWRB NLD17 NLD16 NLD15 NLD14 NDL13 NLD12 IO IO IO IO IO IO IO IO IO IO IO IO IO 2/4/6/8 2/4/6/8 2/4/6/8 2/4/6/8 2/4/6/8 2/4/6/8 2/4/6/8 2/4/6/8 2/4/6/8 2/4/6/8 2/4/6/8 2/4/6/8 2/4/6/8 0.4 0.4 0.4 0.4 0.4 0.4 0.4 0.4 0.4 0.4 0.4 0.4 0.4 2.4 2.4 2.4 2.4 2.4 2.4 2.4 2.4 2.4 2.4 2.4 2.4 2.4 40K 75K 190K PU/PD 2 40K 40K 40K 40K 40K 40K 75K 75K 75K 75K 75K 75K 190K 190K 190K 190K 190K 190K PU/PD PU/PD PD PD PD PD 2 2 2 2 2 2 AC15 NLD11 IO 2/4/6/8 0.4 2.4 40K 75K 190K PD 2 AB15 NLD10 IO 2/4/6/8 0.4 2.4 40K 75K 190K PD 2 AE16 NLD9 IO 2/4/6/8 0.4 2.4 40K 75K 190K PD 2 AD16 NLD8 IO 2/4/6/8 0.4 2.4 40K 75K 190K PD 2 AC16 NLD7 IO 2/4/6/8 0.4 2.4 40K 75K 190K PD 2 AB16 NLD6 IO 2/4/6/8 0.4 2.4 40K 75K 190K PD 2 U16 NLD5 IO 2/4/6/8 0.4 2.4 40K 75K 190K PD 2 AE17 NLD4 IO 2/4/6/8 0.4 2.4 40K 75K 190K PD 2 AD17 NLD3 IO 2/4/6/8 0.4 2.4 40K 75K 190K PD 2 AC17 NLD2 IO 2/4/6/8 0.4 2.4 40K 75K 190K PD 2 AE18 NLD1 IO 2/4/6/8 0.4 2.4 40K 75K 190K PD 2 AD18 NLD0 IO 2/4/6/8 0.4 2.4 40K 75K 190K PD 2 AC18 NRNB IO 2/4/6/8 0.4 2.4 40K 75K 190K PU/PD 2 AB18 NCLE IO 2/4/6/8 0.4 2.4 40K 75K 190K PU/PD 2 AE19 NALE IO 2/4/6/8 0.4 2.4 40K 75K 190K PU/PD 2 594/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 AD19 NWEB IO 2/4/6/8 0.4 2.4 40K 75K 190K PU/PD 2 AC19 NREB IO 2/4/6/8 0.4 2.4 40K 75K 190K PU/PD 2 AB19 NCEB IO 2/4/6/8 0.4 2.4 40K 75K 190K PU/PD 2 AD20 AE20 AE21 AD22 IO IO IO IO 40K 75K 190K PU 2 0.4 0.4 0.4 0.4 2.4 2.4 2.4 2.4 40K 40K 40K 40K 75K 75K 75K 75K 190K 190K 190K 190K PU/PD PU/PD PU/PD PD 2 2 2 2 40K 75K 190K PD 2 USB Interface USB_XTALI USB_XTALO VSSCA_USB VSSCD_USB AC21 VRT IO AD23 VSS33_USB IO AE22 USB_DP IO AE23 USB_DM IO F25 G23 U10 AE11 AD11 B14 SYSRST_B WATCHDOG SRCLKENAN SRCLKENA SRCLKENAI TESTMODE I IO IO IO IO I Y4 VCCQ I AA1 FSOURCE I AD6 SECU_EN I AE7 XBOOT I A22 B22 A21 B21 C21 D21 A20 KCOL7 KCOL6 KCOL5 KCOL4 KCOL3 KCOL2 KCOL1 IO IO IO IO IO IO IO 2/4 2/4 2/4/6/8 2/4/6/8 2/4/6/8 2/4/6/8 2/4/6/8 0.4 0.4 0.4 0.4 0.4 0.4 0.4 2.4 2.4 2.4 2.4 2.4 2.4 2.4 40K 40K 40K 40K 40K 40K 40K 75K 75K 75K 75K 75K 75K 75K 190K 190K 190K 190K 190K 190K 190K PU/PD PU/PD PU PU PU PU PU 2 2 2 2 2 2 2 B20 KCOL0 IO 2/4/6/8 0.4 2.4 40K 75K 190K PU 2 C20 KROW7 IO 2/4/6/8 0.4 2.4 40K 75K 190K PU/PD 2 D20 KROW6 IO 2/4/6/8 0.4 2.4 40K 75K 190K PU/PD 2 Miscellaneous 2 2 2 2 Keypad Interface 595/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 A19 KROW5 IO 2/4/6/8 0.4 2.4 B19 KROW4 IO 2/4/6/8 0.4 2.4 C19 KROW3 IO 2/4/6/8 0.4 2.4 A18 KROW2 IO 2 0.4 2.4 B18 KROW1 IO 2 0.4 2.4 C18 KROW0 IO 2 0.4 2.4 External Interrupt Interface F24 F23 E25 E24 E23 EINT0 EINT1 EINT2 EINT3 EINT4 IO IO IO IO IO 2 2 2 2/4/6/8 2 0.4 0.4 0.4 0.4 0.4 2.4 2.4 2.4 2.4 2.4 40K 40K 40K 40K 40K 75K 75K 75K 75K 75K 190K 190K 190K 190K 190K PU PU PU PU/PD PU/PD 2 2 2 2 2 D23 EINT5 IO 2/4/6/8 0.4 2.4 40K 75K 190K PU/PD 2 D25 EINT6 IO 2 0.4 2.4 40K 75K 190K PU/PD 2 D24 EINT7 IO 2 0.4 2.4 40K 75K 190K PU/PD 2 K17 MFIQ IO 2 0.4 2.4 40K 75K 190K PU/PD 2 External Memory Interface G24 G22 G25 H24 H23 J23 J24 K22 H25 J25 K23 K24 K25 L17 L23 L24 M25 N17 L25 M17 M23 M24 ED0 ED1 ED2 ED3 ED4 ED5 ED6 ED7 ED8 ED9 ED10 ED11 ED12 ED13 ED14 ED15 ERD_B EWR_B ECS0_B ECS1_B ECS2_B ECS3_B IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO 2~16 2~16 2~16 2~16 2~16 2~16 2~16 2~16 2~16 2~16 2~16 2~16 2~16 2~16 2~16 2~16 2~16 2~16 2~16 2~16 2~16 2~16 0.4 0.4 0.4 0.4 0.4 0.4 0.4 0.4 0.4 0.4 0.4 0.4 0.4 0.4 0.4 0.4 0.4 0.4 0.4 0.4 0.4 0.4 2.4 2.4 2.4 2.4 2.4 2.4 2.4 2.4 2.4 2.4 2.4 2.4 2.4 2.4 2.4 2.4 2.4 2.4 2.4 2.4 2.4 2.4 596/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 R25 N25 P24 P23 N22 EWAIT ECAS_B ERAS_B ECKE ED_CLK IO IO IO IO O 2~16 2~16 2~16 2~16 2~16 0.4 0.4 0.4 0.4 0.4 2.4 2.4 2.4 2.4 2.4 40K 75K 190K PD 2 T17 EADMUX IO 2~16 0.4 2.4 40K 75K 190K PU/PD 2 R17 EDQM1 IO 2~16 0.4 2.4 P25 EDQM0 IO 2~16 0.4 2.4 P17 EADV_B O 2~16 0.4 2.4 N24 EC_CLK O 2~16 0.4 2.4 T23 EA0 IO 2~16 0.4 2.4 T22 EA1 IO 2~16 0.4 2.4 T24 EA2 IO 2~16 0.4 2.4 T25 EA3 IO 2~16 0.4 2.4 U23 EA4 IO 2~16 0.4 2.4 U24 EA5 IO 2~16 0.4 2.4 U25 EA6 IO 2~16 0.4 2.4 V23 EA7 IO 2~16 0.4 2.4 V24 EA8 IO 2~16 0.4 2.4 V25 EA9 IO 2~16 0.4 2.4 W22 EA10 IO 2~16 0.4 2.4 W23 EA11 IO 2~16 0.4 2.4 W24 EA12 IO 2~16 0.4 2.4 W25 EA13 IO 2~16 0.4 2.4 Y23 EA14 IO 2~16 0.4 2.4 Y24 EA15 IO 2~16 0.4 2.4 Y25 EA16 IO 2~16 0.4 2.4 AA23 EA17 IO 2~16 0.4 2.4 597/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 AA24 EA18 IO 2~16 0.4 2.4 AA25 EA19 IO 2~16 0.4 2.4 AB24 EA20 IO 2~16 0.4 2.4 AB25 EA21 IO 2~16 0.4 2.4 AC23 EA22 IO 2~16 0.4 2.4 AC24 EA23 IO 2~16 0.4 2.4 AC25 EA24 IO 2~16 0.4 2.4 AD24 EA25 IO 2~16 0.4 2.4 AD25 EA26 IO 2~16 0.4 2.4 40K 75K 190K PU/PD 2 B16 C16 D16 J16 MCCM0 MCDA0 MCDA1 MCDA2 IO IO IO IO 4/8/12/16 4/8/12/16 4/8/12/16 4/8/12/16 0.4 0.4 0.4 0.4 2.4 2.4 2.4 2.4 40K 40K 40K 40K 75K 75K 75K 75K 190K 190K 190K 190K PU/PD PU/PD PU/PD PU/PD 2 2 2 2 C15 MCDA3 IO 4/8/12/16 0.4 2.4 40K 75K 190K PU/PD 2 D15 MCCK IO 4/8/12/16 0.4 2.4 40K 75K 190K PU/PD 2 J15 MCPWRON IO 4/8/12/16 0.4 2.4 40K 75K 190K PU/PD 2 C14 MCWP IO 4/8/12/16 0.4 2.4 40K 75K 190K PU/PD 2 D14 MCINS IO 4 0.4 2.4 40K 75K 190K PU/PD 2 C25 C24 C23 B25 URXD1 UTXD1 UCTS1 URTS1 IO IO IO IO 4/8/12/16 4/8/12/16 4/8/12/16 4/8/12/16 0.4 0.4 0.4 0.4 2.4 2.4 2.4 2.4 40K 75K 190K PU 2 40K 40K 75K 75K 190K 190K PU/PD PU/PD 2 2 A24 URXD2 IO 4/8/12/16 0.4 2.4 40K 75K 190K PU/PD 2 B24 UTXD2 IO 4/8/12/16 0.4 2.4 40K 75K 190K PU/PD 2 A23 URXD3 IO 4/8/12/16 0.4 2.4 40K 75K 190K PU/PD 2 B23 UTXD3 IO 4/8/12/16 0.4 2.4 40K 75K 190K PU/PD 2 2.4 2.4 40K 40K 75K 75K 190K 190K PU/PD PU/PD 2 2 Memory Card Interface UART/IrDA Interface Digital Audio Interface D18 A17 DAICLK DAIPCMOUT IO IO 2/4 2/4 0.4 0.4 598/599 MediaTek Inc. Confidential MT6235 GSM/GPRS Baseband Processor Data Sheet Revision 1.02 B17 C17 D17 DAIPCMIN DAIRST DAISYNC IO IO IO 2/4 2/4/6/8 2/4/6/8 AA2 AA3 AB3 AB2 AA4 AB6 AC2 CMRST CMPDN CMVREF CMHREF CMPCLK CMMCLK CMDAT7 IO IO IO IO IO IO IO 4 4 4/8/12/16 4/8/12/16 4/8/12/16 4/8/12/16 4/8/12/16 AC3 CMDAT6 IO AC1 CMDAT5 AD1 0.4 0.4 0.4 2.4 2.4 2.4 40K 40K 40K 75K 75K 75K 190K 190K 190K PU/PD PU/PD PU/PD 2 2 2 0.4 0.4 0.4 0.4 0.4 0.4 0.4 2.4 2.4 2.4 2.4 2.4 2.4 2.4 40K 40K 40K 40K 40K 40K 40K 75K 75K 75K 75K 75K 75K 75K 190K 190K 190K 190K 190K 190K 190K PU/PD PU/PD PU/PD PU/PD PU/PD PU/PD PU/PD 2 2 2 2 2 2 2 4/8/12/16 0.4 2.4 40K 75K 190K PU/PD 2 IO 4/8/12/16 0.4 2.4 40K 75K 190K PU/PD 2 CMDAT4 IO 4/8/12/16 0.4 2.4 40K 75K 190K PU/PD 2 AE2 CMDAT3 IO 4 0.4 2.4 40K 75K 190K PU/PD 2 AD3 CMDAT2 IO 4 0.4 2.4 40K 75K 190K PU/PD 2 AD4 CMDAT1 IO 4 0.4 2.4 40K 75K 190K PU/PD 2 AE3 CMDAT0 IO 4 0.4 2.4 40K 75K 190K PU/PD 2 AC4 CMFLASH IO 4 0.4 2.4 40K 75K 190K PU/PD 2 CMOS Sensor Interface 599/599 MediaTek Inc. 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