Xilinx PG047 LogiCORE IP Ethernet 1000BASE X PCS/PMA Or SGMII V11.4, Product Guide Gig Eth Pcs Pma
User Manual: 1000BASE-X
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LogiCORE IP Ethernet
1000BASE-X PCS/PMA or
SGMII v11.4
Product Guide
PG047 October 16, 2012
Table of Contents
SECTION I: SUMMARY
IP Facts
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Chapter 1: Overview
Core Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Recommended Design Experience . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
System Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Licensing and Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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19
20
20
22
23
Chapter 2: Product Specification
Overview of Ethernet Architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Speed Grades . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Resource Utilization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Register Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
24
25
26
27
28
28
34
49
Chapter 3: Designing with the Core
General Design Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Clocking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Chapter 4: The Ten-Bit Interface
Ten-Bit-Interface Logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Clock Sharing across Multiple Cores with TBI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Example Designs for the Ten-Bit Interface (TBI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
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Chapter 5: 1000BASE-X with Transceivers
Transceiver Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Clock Sharing Across Multiple Cores with Transceivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Example Design for 1000BASE-X with Transceivers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Chapter 6: SGMII / Dynamic Standards Switching with Transceivers
Receiver Elastic Buffer Implementations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Logic Using the Transceiver Rx Elastic Buffer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transceiver Logic with the FPGA Logic Rx Elastic Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock Sharing - Multiple Cores with Transceivers, FPGA Logic Elastic Buffer . . . . . . . . . . . . . . . .
SGMII Example Design / Dynamic Switching Example Design Using a Transceiver . . . . . . . . . . .
181
184
184
206
222
Chapter 7: SGMII over LVDS
Synchronous SGMII over Virtex7/Kintex 7 FPGA LVDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
SGMII Support Using Asynchronous Oversampling over Virtex-6 FPGA LVDS . . . . . . . . . . . . . . . 260
Chapter 8: Using the Client-Side GMII Datapath
Using the Core Netlist Client-side GMII for the 1000BASE-X Standard . . . . . . . . . . . . . . . . . . . . . 290
Using the Core Netlist Client-Side GMII for the SGMII Standard . . . . . . . . . . . . . . . . . . . . . . . . . . 296
Additional Client-Side SGMII Logic Provided in the Example Design . . . . . . . . . . . . . . . . . . . . . . . 299
Chapter 9: Auto-Negotiation
Overview of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Setting the Configurable Link Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Using the Auto-Negotiation Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Use of Clock Correction Sequences in Device Specific Transceivers (1000BASE-X Standard). . . .
Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
306
311
312
312
313
Chapter 10: Dynamic Switching of 1000BASE-X and SGMII Standards
Typical Application. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314
Operation of the Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315
Chapter 11: GMII to PHY EDK Application for Zynq-7000 Device Processor
Subsystem
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GMII to 1000BASEX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GMII to SGMII Using Zynq-7000 Device Gigabit Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GMII to SGMII Using Zynq-7000 Device LVDS Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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320
322
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Chapter 12: Interfacing to Other Cores
Integration of the Tri-Mode Ethernet MAC for 1000BASE-X Operation . . . . . . . . . . . . . . . . . . . . 325
Integration of the Tri-Mode Ethernet MAC for Tri-speed SGMII Operation . . . . . . . . . . . . . . . . . 344
Chapter 13: Special Design Considerations
Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369
Start-up Sequencing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369
Loopback. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 370
SECTION II: VIVADO DESIGN SUITE
Chapter 14: Customizing and Generating the Core
GUI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373
Output Generation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378
Chapter 15: Constraining the Core
Required Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Device, Package, and Speed Grade Selections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I/O Standard and Placement. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
379
379
380
381
Chapter 16: Detailed Example Design
Example Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382
Demonstration Test Bench . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382
SECTION III: ISE DESIGN SUITE
Chapter 17: Customizing and Generating the Core
GUI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 384
Parameter Values in the XCO File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389
Output Generation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 390
Chapter 18: Constraining the Core
Device, Package, and Speed Grade Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I/O Location Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Placement Constraints. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Virtex-4 FPGA MGT Transceivers for 1000BASE-X Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Virtex-4 FPGA RocketIO MGT Transceivers for SGMII or Dynamic Standards
Switching Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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392
392
392
394
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Virtex-5 FPGA RocketIO GTP Transceivers for 1000BASE-X Constraints . . . . . . . . . . . . . . . . . . . .
Virtex-5 FPGA RocketIO GTP Transceivers for SGMII or Dynamic Standards
Switching Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Virtex-5 FPGA RocketIO GTX Transceivers for SGMII or Dynamic Standards
Switching Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Virtex-6 FPGA GTX Transceivers for 1000BASE-X Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Virtex-6 FPGA GTX Transceivers for SGMII or Dynamic Standards Switching Constraints . . . . . .
Spartan-6 FPGA GTP Transceivers for 1000BASE-X Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . .
Spartan-6 FPGA GTP Transceivers for SGMII or Dynamic Standards Switching Constraints . . . .
7 Series and Zynq-7000 Device Transceivers for 1000BASE-X Constraints . . . . . . . . . . . . . . . . . .
7 Series and Zynq-7000 Device Transceivers for SGMII or Dynamic Standards
Switching Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SGMII over LVDS Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Ten-Bit Interface Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Constraints When Implementing an External GMII. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Understanding Timing Reports for Setup/Hold Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
394
395
397
398
399
400
401
402
403
404
404
411
418
Chapter 19: Implementing the Design
Pre-implementation Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Using the Simulation Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Synthesis. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Post-Implementation Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Other Implementation Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
419
419
420
421
422
423
Chapter 20: Detailed Example Design
Directory Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Directory and File Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Example Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Demonstration Test Bench . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Implementation Scripts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Simulation Scripts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
425
426
430
430
430
431
SECTION IV: APPENDICES
Appendix A: Verification, Compliance, and Interoperability
Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433
Hardware Testing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433
Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 434
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Appendix B: Migrating
Appendix C: 1000BASE-X State Machines
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 436
Start of Frame Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 437
End of Frame Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 440
Appendix D: Rx Elastic Buffer Specifications
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Rx Elastic Buffers: Depths and Maximum Frame Sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum Frame Sizes for Sustained Frame Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Jumbo Frame Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
444
444
450
451
452
Appendix E: Implementing External GMII
GMII Transmitter Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 453
GMII Receiver Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 460
Appendix F: Calculating the DCM Fixed Phase Shift or IODelay Tap Setting
DCM Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 462
IODelay Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 464
Appendix G: Debugging
Solution Centers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
General Checks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Problems with the MDIO. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Problems with Data Reception or Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Problems with Auto-Negotiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Problems in Obtaining a Link (Auto-Negotiation Disabled) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Problems with a High Bit Error Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
466
466
466
467
467
468
469
Appendix H: Additional Resources
Xilinx Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Additional Core Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Feedback. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Notice of Disclaimer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1000BASE-X PCS/PMA or SGMII v11.4
PG047 October 16, 2012
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471
471
472
472
473
474
474
6
SECTION I: SUMMARY
IP Facts
Overview
Product Specification
Designing with the Core
The Ten-Bit Interface
1000BASE-X with Transceivers
SGMII / Dynamic Standards Switching with
Transceivers
SGMII over LVDS
Using the Client-Side GMII Datapath
Auto-Negotiation
GMII to PHY EDK Application for Zynq-7000
Device Processor Subsystem
1000BASE-X PCS/PMA or SGMII v11.4
PG047 October 16, 2012
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7
Chapter :
Dynamic Switching of 1000BASE-X and SGMII
Standards
Interfacing to Other Cores
Special Design Considerations
1000BASE-X PCS/PMA or SGMII v11.4
PG047 October 16, 2012
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8
IP Facts
Introduction
LogiCORE IP Facts Table
The LogiCORE™ Ethernet 1000BASE-X
PCS/PMA or Serial Gigabit Media Independent
Interface (SGMII) core provides a flexible
solution for connection to an Ethernet Media
Access Controller (MAC) or other custom logic.
It supports two standards of operation that can
be dynamically selected:
•
•
1000BASE-X Physical Coding Sublayer (PCS)
and Physical Medium Attachment (PMA)
operation, as defined in the IEEE
802.3-2008 standard
Gigabit Media Independent Interface (GMII)
to Serial-GMII (SGMII) bridge or SGMII to
GMII bridge, as defined in the Serial-GMII
specification (ENG-46158)
Core Specifics
Supported
Device
Family (1)
Zynq-7000 (2), Virtex-7, Kintex-7, Artix-7
Virtex-6, Virtex-5, Virtex-4,
Spartan-6, Spartan-3, Spartan-3E,
Spartan-3A/3A DSP
Supported
User Interfaces
Resources
GMII
See Table 2-2, Table 2-3, Table 2-4,
Table 2-5, Table 2-7, Table 2-8, and
Table 2-9
Provided with Core
Design Files
Example
Designs
ISE®: VHDL and Verilog, NGC Netlist
Vivado™: Encrypted RTL
1000BASE-X PCS/PMA using a transceiver
1000BASE-X PCS with Ten-Bit Interface (3)
GMII to SGMII Bridge for all supported
interfaces(3)
Test Bench
Demonstration Test Bench
Constraints File
User Constraints File (.ucf)
Simulation
Model
Features
Verilog and VHDL
Supported
S/W Driver
•
Supported physical interfaces for
1000BASE-X and SGMII standards:
•
Integrated transceiver interface using one
of the following:
NA
Tested Design Flows (4)
°
Zynq™-7000 device GTX Transceiver
°
Virtex ®-7 FPGA GTH Transceiver
°
Virtex-7 and Kintex™-7 FPGA GTX
Transceiver
ISE® Design Suite 14.3
Vivado Design Suite 2012.3 (5)
Design Entry
Simulation
Synthesis
Mentor Graphics ModelSim
Cadence Incisive Enterprise Simulator
Synopsys Verilog Compiled Simulator (VCS) and
VCS MX
Xilinx Synthesis Technology (XST)
Vivado Synthesis
Support
°
Artix ™-7 FPGA GTP Transceiver
Provided by Xilinx, Inc.@ www.xilinx.com/support
°
Virtex-6 FPGA GTX Transceiver
Voltage Requirements
°
Virtex-5 FPGA RocketIO™ GTP or GTX
Transceiver
°
Virtex-4 FPGA RocketIO Multi-Gigabit
Transceiver (MGT)
°
Spartan®-6 FPGA GTP Transceiver
1000BASE-X PCS/PMA or SGMII v11.4
PG047 October 16, 2012
1. For a complete listing of supported devices, see the
release notes for this core. For supported family
configurations see Table 2-1. For supported speed grades
see Speed Grades.
2. Supported in ISE Design Suite implementations only.
3. See Licensing and Ordering Information.
4. For the supported versions of the tools, see the Xilinx Design
Tools: Release Notes Guide . Also see Simulation for more
information.
5. Supports only 7 series devices.
www.xilinx.com
9
Product Specification
Features
Features
•
Support for SGMII over Select Input/Output (I/O) Low Voltage Differential Signaling (LVDS) in
Virtex-7, Kintex-7 and Virtex-6 FPGA -2 and faster devices
•
Configured and monitored through the serial Management Data Input/Output (MDIO)
Interface (MII Management), which can optionally be omitted from the core
•
Supports 1000BASE-X Auto-Negotiation for information exchange with a link partner, which
can optionally be omitted from the core
•
Supports SGMII Auto-Negotiation for communication with the external Physical-Side Interface
(PHY) device
1000BASE-X PCS/PMA or SGMII v11.4
PG047 October 16, 2012
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10
Product Specification
Chapter 1
Overview
This product guide provides information for generating a Xilinx Ethernet 1000BASE-X
Physical Coding Sublayer/Physical Medium Attachment (PCS/PMA) or Serial Gigabit Media
Independent Interface (SGMII) core, customizing and simulating the core using the
provided example design, and running the design files through implementation using the
Xilinx tools.
The Ethernet 1000BASE-X PCS/PMA or SGMII IP core is a fully-verified solution that
supports Verilog Hardware Description Language (HDL) and VHSIC Hardware Description
Language (VHDL.) In addition, the example design provided with the core supports both
Verilog and VHDL.
For detailed information about the core, see the Ethernet 100BASE-X PCS/PMA product
page.
Transceivers are defined by device family in the following way:
•
Zynq™-7000 devices, GTX Transceivers
•
For Virtex®-7 devices, GTX and GTH transceivers
•
For Artix™-7 devices, GTP transceivers
•
Kintex™-7 devices, GTX transceivers
•
For Virtex-6 devices, GTX transceivers
•
For Virtex-5 LXT and SXT devices, RocketIO™ GTP transceivers; Virtex-5 FXT and TXT
devices, RocketIO GTX transceivers
•
For Virtex-4 devices, RocketIO Multi-Gigabit transceivers (MGT)
•
For Spartan®-6 devices, GTP transceivers
1000BASE-X PCS/PMA or SGMII v11.4
PG047 October 16, 2012
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11
Chapter 1: Overview
Core Overview
This section contains the following subsections:
•
Ethernet 1000BASE-X PCS/PMA or SGMII Support Using a Device Specific Transceiver
•
Ethernet 1000BASE-X PCS/PMA or SGMII Support with Ten-Bit Interface
•
SGMII over LVDS
Ethernet 1000BASE-X PCS/PMA or SGMII Support Using a
Device Specific Transceiver
Using the Ethernet 1000BASE-X PCS/PMA or SGMII core with the device-specific transceiver
provides the functionality to implement the 1000BASE-X PCS and PMA sublayers.
Alternatively, it can be used to provide a GMII to SGMII bridge.
The core interfaces to a device-specific transceiver, which provides some of the PCS layer
functionality such as 8B/10B encoding/decoding, the PMA Serializer/Deserializer (SerDes),
and clock recovery. Figure 1-1 illustrates the remaining PCS sublayer functionality and the
major functional blocks of the core. A description of the functional blocks and signals is
provided in subsequent sections.
X-Ref Target - Figure 1-1
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Ethernet 1000BASE-X PCS/PMA or SGMII Core Using a Device-Specific Transceiver
1000BASE-X PCS/PMA or SGMII v11.4
PG047 October 16, 2012
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12
Chapter 1: Overview
GMII Block
The core provides a client-side GMII. This can be used as an internal interface for
connection to an embedded Ethernet MAC or other custom logic. Alternatively, the core
GMII can be routed to device Input/Output Blocks (IOBs) to provide an off-chip GMII.
Virtex-7 devices support GMII at 3.3 V or lower only in certain parts and packages; see the
7 Series FPGAs SelectIO Resources User Guide. Virtex-6 devices support GMII at 2.5 V only;
see the Virtex-6 FPGA Data Sheet: DC and Switching Characteristics. Kintex-7, Artix-7,
Spartan-6, Virtex-5, Virtex-4 and Spartan-3 devices support GMII at 3.3 V or lower.
PCS Transmit Engine
The PCS transmit engine converts the GMII data octets into a sequence of ordered sets by
implementing the state diagrams of IEEE 802.3-2008 (Figures 36-5 and 36-6).
PCS Receive Engine and Synchronization
The synchronization process implements the state diagram of IEEE 802.3-2008 (Figure
36-9). The PCS receive engine converts the sequence of ordered sets to GMII data octets by
implementing the state diagrams of IEEE 802.3-2008 (Figures 36-7a and 36-7b).
Optional Auto-Negotiation Block
IEEE 802.3-2008 clause 37 describes the 1000BASE-X Auto-Negotiation function that allows
a device to advertise the supported modes of operation to a device at the remote end of a
link segment (link partner), and to detect corresponding operational modes that the link
partner might be advertising. Auto-Negotiation is controlled and monitored through the
PCS Management registers.
Optional PCS Management Registers
Configuration and status of the core, including access to and from the optional
Auto-Negotiation function, is performed with the 1000BASE-X PCS Management registers
as defined in IEEE 802.3-2008 clause 37. These registers are accessed through the serial
Management Data Input/Output Interface (MDIO), defined in IEEE 802.3-2008 clause 22, as
if it were an externally connected PHY.
An additional configuration interface is provided to program Control register (Register 0)
and Auto-Negotiation advertisement (Register 4) independent of the MDIO interface.
The PCS Management registers can be omitted from the core when the core is performing
the 1000BASE-X standard. In this situation, configuration and status is made possible by
using additional configuration vector and status signals. When the core is performing the
SGMII standard, PCS Management registers become mandatory and information in the
registers takes on a different interpretation.
1000BASE-X PCS/PMA or SGMII v11.4
PG047 October 16, 2012
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13
Chapter 1: Overview
Transceiver Interface Block
The interface block enables the core to connect to a device-specific transceiver.
Ethernet 1000BASE-X PCS/PMA or SGMII Support with Ten-Bit
Interface
When used with the TBI, the Ethernet 1000BASE-X PCS/PMA or SGMII core provides the
functionality to implement the 1000BASE-X PCS sublayer (or to provide SGMII support) with
use of an external SerDes.
X-Ref Target - Figure 1-2
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SGMII Core with TBI
The optional TBI is used in place of the device-specific transceiver to provide a parallel
interface for connection to an external PMA SerDes device, allowing an alternative
implementation for families without device-specific transceivers. In this implementation,
additional logic blocks are required in the core to replace some of the device-specific
transceiver functionality. These blocks are surrounded by a dashed line (see Figure 1-2).
Other blocks are identical to those previously defined.
Zynq-7000, Artix-7 and Virtex-7 devices do not support TBI. Virtex-6 devices support TBI at
2.5 V only; see the Virtex-6 FPGA Data Sheet: DC and Switching Characteristics. Kintex-7,
Spartan-6, Virtex-5, Virtex-4 and Spartan-3 devices support TBI at 3.3 V or lower.
8B/10B Encoder
8B/10B encoding, as defined in IEEE 802.3-2008 specification (Tables 36-1a to 36-1e and
Table 36-2), is implemented in a block SelectRAM™ memory, configured as ROM, and used
as a large look-up table.
1000BASE-X PCS/PMA or SGMII v11.4
PG047 October 16, 2012
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14
Chapter 1: Overview
8B/10B Decoder
8B/10B decoding, as defined in IEEE 802.3-2008 specification (Tables 36-1a to 36-1e and
Table 36-2), is implemented in a block SelectRAM memory, configured as ROM, and used as
a large look-up table.
Receiver Elastic Buffer
The Receiver Elastic Buffer enables the 10-bit parallel TBI data, received from the PMA
sublayer synchronously to the TBI receiver clocks, to be transferred onto the core internal
125 MHz clock domain.
The Receiver Elastic Buffer is an asynchronous First In First Out (FIFO) implemented in
internal RAM. The operation of the Receiver Elastic Buffer attempts to maintain a constant
occupancy by inserting or removing Idle sequences as necessary. This causes no corruption
to the frames of data.
TBI Block
The core provides a TBI interface, which should be routed to device IOBs to provide an
off-chip TBI.
SGMII over LVDS
Synchronous SGMII over Virtex7/Kintex7 LVDS
Kintex-7/Virtex-7 devices, -2 speed grade or higher on HR Banks and -1 or higher for HP
Banks, can fully support SGMII using standard LVDS SelectIO™ technology logic resources.
This enables direct connection to external PHY devices without the use of an FPGA
Transceiver. This implementation is illustrated in Figure 1-3.
1000BASE-X PCS/PMA or SGMII v11.4
PG047 October 16, 2012
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15
Chapter 1: Overview
X-Ref Target - Figure 1-3
COMPONENT?NAME?EXAMPLE?DESIGN
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for SGMII
The core netlist in this implementation remains identical to that of Figure 1-1 and all core
netlist blocks are identical to those described in Ethernet 1000BASE-X PCS/PMA or SGMII
Support Using a Device Specific Transceiver.
As illustrated in Figure 1-3, the Hardware Description Language (HDL) example design for
this implementation provides additional logic to form the "LVDS transceiver." The LVDS
transceiver block fully replaces the functionality otherwise provided by a 7 series FPGA
GTX/GTH transceiver. This is only possible at a serial line rate of 1.25 Gb/s. See Figure 1-4
for a block diagram of the LVDS transceiver.
1000BASE-X PCS/PMA or SGMII v11.4
PG047 October 16, 2012
www.xilinx.com
16
Chapter 1: Overview
X-Ref Target - Figure 1-4
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LVDS Transceiver Block Level Representation
The following subsections describe design requirements.
SGMII Only
The interface implemented using this method supports SGMII between the FPGA and an
external PHY device; the interface cannot directly support 1000BASE-X.
Supported Devices
•
Kintex-7 devices, -2 speed grade or faster for devices with HR Banks or -1 speed grade
or faster for devices with HP banks.
•
Virtex-7 devices, -2 speed grade or faster for devices with HR Banks or -1 speed grade
or faster for devices with HP banks.
Recommended for Chip-to-Chip Copper Implementations Only
This interface supports an SGMII link between the FPGA and an external PHY device across
a single PCB; keep the SGMII copper signal lengths to a minimum.
SGMII Support Using Asynchronous Oversampling over 7 Series FPGAs LVDS
See XAPP523 LVDS 4x Asynchronous Oversampling Using 7 Series FPGAs for information
about 7 series devices using asynchronous oversampling.
1000BASE-X PCS/PMA or SGMII v11.4
PG047 October 16, 2012
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17
Chapter 1: Overview
SGMII Support Using Asynchronous Oversampling over Virtex-6 FPGA LVDS
Virtex-6 devices, -2 speed grade or higher, can fully support SGMII using standard LVDS
SelectIO™ technology logic resources. This enables direct connection to external PHY
devices without the use of a Virtex-6 FPGA GTX transceiver.
X-Ref Target - Figure 1-5
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Figure 1-5:
Functional Block Diagram of the Core with Standard SelectIO Technology Support
for SGMII
This implementation is illustrated in Figure 1-5.
The core netlist in this implementation remains identical to that of Figure 1-1 and all core
netlist blocks are identical to those described in Ethernet 1000BASE-X PCS/PMA or SGMII
Support Using a Device Specific Transceiver.
As illustrated in Figure 1-5, the Hardware Description Language (HDL) example design for
this implementation provides additional logic to form the “LVDS transceiver” block which
fully replaces the functionality otherwise provided by a Virtex-6 FPGA GTX transceiver. The
LVDS transceiver block contains IODELAY and ISERDES elements along with a Data Recovery
Unit (DRU). This block uses the Virtex-6 FPGA ISERDES elements in a new asynchronous
oversampling mode as described in XAPP881 1.25Gbs 4x Asynchronous Oversampling over
Virtex-6 LVDS. The full transceiver functionality is then completed with Comma Alignment,
8B/10B Decoder and Rx Elastic buffer blocks.
1000BASE-X PCS/PMA or SGMII v11.4
PG047 October 16, 2012
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18
Chapter 1: Overview
Figure 1-5 also illustrates the inclusion of the “I/O Bank Clocking.” This block creates all of
the clock frequencies and clock phases that are required by the LVDS transceiver block. As
the name of the block suggests, this logic can be shared across a single Virtex-6 FPGA I/O
bank. This I/O bank can be used for multiple instances of the core with LVDS I/O to create
several independent SGMII ports.
The following four subsections describe design requirements.
SGMII Only
The interface implemented using this asynchronous oversampling method supports SGMII
between the FPGA and an external PHY device; the interface cannot directly support
1000BASE-X.
Supported in Virtex-6 Devices, -2 Speed Grade or Faster
The SGMII LVDS implementation has only been characterized in the -2 speed grade and
faster Virtex-6 devices.
Timing closure of this interface is challenging; perform the layout and placement steps
described in Layout and Placement in Chapter 7.
Receiver UI Specification
The DRU must have at least two valid sampling points per data bit, requiring 0.5 UI of
opening. The settings of the FPGA add 0.125 UI of requirement making a total opening
requirement at the receiver of 0.625 UI.
Recommended for Chip-to-Chip Copper Implementations Only
This interface supports an SGMII link between the FPGA and an external PHY device across
a single PCB; keep the SGMII copper signal lengths to a minimum.
Recommended Design Experience
Although the Ethernet 1000BASE-X PCS/PMA or SGMII core is a fully-verified solution, the
challenge associated with implementing a complete design varies depending on the
configuration and functionality of the application. For best results, previous experience
building high-performance, pipelined Field Programmable Gate Array (FPGA) designs using
Xilinx implementation software and the User Constraint Files (UCF) is recommended.
Contact your local Xilinx representative for a closer review and estimation for your specific
requirements.
1000BASE-X PCS/PMA or SGMII v11.4
PG047 October 16, 2012
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19
Chapter 1: Overview
System Requirements
For a list of System Requirements, see the Xilinx Design Tools: Release Notes Guide.
Applications
Typical applications for the Ethernet 1000BASE-X PCS/PMA or SGMII core include the
following:
•
Ethernet 1000BASE-X
•
Serial-GMII
EDK specific applications targeting Gigabit Ethernet MAC (GEM) embedded in Zynq™-7000
devices is shown in Chapter 11, GMII to PHY EDK Application for Zynq-7000 Device
Processor Subsystem.
Ethernet 1000BASE-X
Figure 1-6 illustrates a typical application for the Ethernet 1000BASE-X PCS/PMA or SGMII
core with the core operating to the 1000BASE-X standard using a device-specific
transceiver to provide the Physical Coding Sublayer (PCS) and Physical Medium Attachment
(PMA) sublayers for 1-Gigabit Ethernet.
•
The PMA is connected to an external off-the-shelf Gigabit Interface Converter (GBIC) or
Small Form-Factor Pluggable (SFP) optical transceiver to complete the Ethernet port.
•
The GMII of the Ethernet 1000BASE-X PCS/PMA is connected to an embedded Ethernet
Media Access Controller (MAC), for example, the Xilinx Tri-Mode Ethernet MAC core.
X-Ref Target - Figure 1-6
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1000BASE-X PCS/PMA or SGMII v11.4
PG047 October 16, 2012
Typical 1000BASE-X Application
www.xilinx.com
20
Chapter 1: Overview
Serial-GMII
Ethernet 1000BASE-X PCS/PMA or SGMII core can operate in two modes as shown in the
following subsections.
GMII to SGMII Bridge
Figure 1-7 illustrates a typical application for the Ethernet 1000BASE-X PCS/PMA or SGMII
core, which shows the core providing a GMII to SGMII bridge using a device-specific
transceiver to provide the serial interface.
•
The device-specific transceiver is connected to an external off-the-shelf Ethernet PHY
device that also supports SGMII. (This can be a tri-mode PHY providing 10BASE-T,
100BASE-T, and 1000BASE-T operation.)
•
The GMII of the Ethernet 1000BASE-X PCS/PMA or SGMII core is connected to an
embedded Ethernet MAC, for example, the Xilinx Tri-Mode Ethernet MAC core.
X-Ref Target - Figure 1-7
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SGMII to GMII Bridge
Figure 1-8 illustrates a typical application for the Ethernet 1000BASE-X PCS/PMA or SGMII
core, which shows the core providing a SGMII to GMII bridge using a device-specific
transceiver to provide the serial interface.
•
The device-specific transceiver is connected to an external off-the-shelf Ethernet MAC
device that also supports SGMII. (This can be a tri-mode MAC providing 10/100/1000
Mb/s operation, for example, the Xilinx Tri-Mode Ethernet MAC core connected to
1000BASE-X PCS/PMA or SGMII core operating in GMII to SGMII Mode)
•
The GMII of the Ethernet 1000BASE-X PCS/PMA or SGMII core is connected to a
tri-mode PHY providing 10BASE-T, 100BASE-T, and 1000BASE-T operation.
1000BASE-X PCS/PMA or SGMII v11.4
PG047 October 16, 2012
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21
Chapter 1: Overview
X-Ref Target - Figure 1-8
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Verification
The Ethernet 1000BASE-X PCS/PMA or SGMII core has been verified with extensive
simulation and hardware verification.
Simulation
A highly parameterizable transaction-based test bench was used to test the core. The tests
included the following:
•
Register access
•
Loss of synchronization
•
Auto-negotiation and error handling
•
Frame transmission and error handling
•
Frame reception and error handling
•
Clock compensation in the elastic buffers
Zynq-7000, Virtex-7, Kintex-7, Artix-7, Virtex-6, Virtex-5, Virtex-4 and Spartan-6 device
designs incorporating a device-specific transceiver require a Verilog LRM-IEEE 1364-2005
encryption-compliant simulator. For VHDL simulation, a mixed Hardware Description
Language (HDL) license is required.
1000BASE-X PCS/PMA or SGMII v11.4
PG047 October 16, 2012
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22
Chapter 1: Overview
Hardware Verification
The core has been tested in several hardware test platforms at Xilinx to represent a variety
of parameterizations, including the following:
•
The core used with a device-specific transceiver and performing the 1000BASE-X
standard has been tested with the Xilinx Tri-Mode Ethernet MAC core, which follows
the architecture shown in Figure 1-6. A test platform was built around these cores,
including a back-end FIFO capable of performing a simple ping function, and a test
pattern generator. Software running on the embedded PowerPC® processor provided
access to all configuration and status registers. Version 3.0 of this core was taken to the
University of New Hampshire Interoperability Lab (UNH IOL) where conformance and
interoperability testing was performed.
•
The core used with a device-specific transceiver and performing the SGMII standard
has been tested with the LogiCORE Intellectual Property (IP) Tri-Mode Ethernet MAC
core. This was connected to an external PHY capable of performing 10BASE-T,
100BASE-T, and 1000BASE-T, and the system was tested at all three speeds. This follows
the architecture shown in Figure 1-7 and also includes the PowerPC-based processor
test platform described previously.
Licensing and Ordering Information
This Xilinx LogiCORE™ IP module is provided at no additional cost with the Xilinx Vivado™
Design Suite and ISE® Design Suite tools under the terms of the Xilinx End User License.
Information about this and other Xilinx LogiCORE IP modules is available at the Xilinx
Intellectual Property page. For information about pricing and availability of other Xilinx
LogiCORE IP modules and tools, contact your local Xilinx sales representative.
1000BASE-X PCS/PMA or SGMII v11.4
PG047 October 16, 2012
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23
Chapter 2
Product Specification
Overview of Ethernet Architecture
Figure 2-1 illustrates the 1-Gigabit Ethernet PCS and PMA sublayers provided by this core,
which are part of the Ethernet architecture. The part of this architecture, from the Ethernet
MAC to the right, is defined in the IEEE 802.3-2008 specification. This figure also shows
where the supported interfaces fit into the architecture.
X-Ref Target - Figure 2-1
'-))
3'-))
4#0
&)&/
)&
)0
-!#
4RANSCEIVER
3ERIAL
4")
0#3
0-!
0-$
0-$
8
Figure 2-1:
Overview of Ethernet Architecture
MAC
The Ethernet Media Access Controller (MAC) is defined in IEEE 802.3-2008, clauses 2, 3, and
4. A MAC is responsible for the Ethernet framing protocols and error detection of these
frames. The MAC is independent of, and can connect to, any type of physical layer device.
GMII / SGMII
The Gigabit Media Independent Interface (GMII), a parallel interface connecting a MAC to
the physical sublayers (PCS, PMA, and PMD), is defined in IEEE 802.3-2008, clause 35. For a
MAC operating at a speed of 1 Gigabit per second (Gb/s), the full GMII is used; for a MAC
operating at a speed of 10 Mb/s or 100 Mb/s, the GMII is replaced with a Media
Independent Interface (MII) that uses a subset of the GMII signals.
The Serial-GMII (SGMII) is an alternative interface to the GMII/MII that converts the parallel
interface of the GMII/MII into a serial format capable of carrying traffic at speeds of
10 Mb/s, 100 Mb/s, and 1 Gb/s. This radically reduces the I/O count and for this reason is
often preferred by Printed Circuit Board (PCB) designers. The SGMII specification is closely
related to the 1000BASE-X PCS and PMA sublayers, which enables it to be offered in this
core.
1000BASE-X PCS/PMA or SGMII v11.4
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Chapter 2: Product Specification
PCS
The Physical Coding Sublayer (PCS) for 1000BASE-X operation is defined in IEEE 802.3-2008,
clauses 36 and 37, and performs these operations:
•
Encoding (and decoding) of GMII data octets to form a sequence of ordered sets
•
8B/10B encoding (and decoding) of the sequence ordered sets
•
1000BASE-X Auto-Negotiation for information exchange with the link partner
Ten Bit Interface
The Ten-Bit-Interface (TBI), defined in IEEE 802.3-2008 clause 36 is a parallel interface
connecting the PCS to the PMA and transfers the 8B/10B encoded sequence-ordered sets.
The TBI should be used with an external SERDES device to implement the PMA functionality.
Physical Medium Attachment
The Physical Medium Attachment (PMA) for 1000BASE-X operation, defined in IEEE
802.3-2008 clause 36, performs the following:
•
Serialization (and deserialization) of code-groups for transmission (and reception) on
the underlying serial Physical Medium Dependent (PMD)
•
Recovery of the clock from the 8B/10B-coded data supplied by the PMD
The device-specific transceivers provide the serial interface required to connect the PMD.
Physical Medium Dependent
The PMD sublayer is defined in IEEE 802.3-2008 clause 38 for 1000BASE-LX and
1000BASE-SX (long and short wavelength laser). This type of PMD is provided by the
external GBIC or SFP optical transceivers. An alternative PMD for 1000BASE-CX (short-haul
copper) is defined in IEEE 802.3-2008 clause 39.
Standards
•
Designed to Ethernet Standard 802.3-2008 Clauses 22, 35, 36 and 38.
•
Serial-GMII Specification V1.7 (CISCO SYSTEMS, ENG-46158)
1000BASE-X PCS/PMA or SGMII v11.4
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25
Chapter 2: Product Specification
Performance
This section details the performance information for various core configurations.
Maximum Frequencies
1000Base-X PCS/PMA or SGMII core operates at 125 MHz.
Core Latency
The stand-alone core does not meet all the latency requirements specified in IEEE
802.3-2008 because of the latency of the Elastic Buffers in both TBI and device-specific
transceiver versions. However, the core can be used for backplane and other applications
where strict adherence to the IEEE latency specification is not required.
Where strict adherence to the IEEE 802.3-2008 specification is required, the core can be
used with an Ethernet MAC core that is within the IEEE specified latency for a MAC sublayer.
For example, when the core is connected to the Xilinx Tri-Mode Ethernet MAC core, the
system as a whole is compliant with the overall IEEE 802.3-2008 latency specifications.
Latency for 1000BASE-X PCS with TBI
The following measurements are for the core only and do not include any IOB registers or
the Transmitter Elastic Buffer added in the example design.
Transmit Path Latency
As measured from a data octet input into gmii_txd[7:0] of the transmitter side GMII
until that data appears on tx_code_group[9:0] on the TBI interface, the latency through
the core in the transmit direction is 5 clock periods of gtx_clk.
Receive Path Latency
Measured from a data octet input into the core on rx_code_group0[9:0] or
rx_code_group1[9:0] from the TBI interface (until that data appears on
gmii_rxd[7:0] of the receiver side GMII), the latency through the core in the receive
direction is equal to 16 clock periods of gtx_clk, plus an additional number of clock
cycles equal to the current value of the Receiver Elastic Buffer.
The Receiver Elastic Buffer is 32 words deep. The nominal occupancy will be at half-full,
thereby creating a nominal latency through the receiver side of the core equal to 16 + 16=
32 clock cycles of gtx_clk.
1000BASE-X PCS/PMA or SGMII v11.4
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Chapter 2: Product Specification
Latency for 1000BASE-X PCS and PMA Using a Transceiver
These measurements are for the core only; they do not include the latency through the
Virtex®-4 FPGA serial transceiver, Virtex-5 FPGA GTP transceiver, Virtex-5 FPGA GTX
RocketIO™ transceiver, Virtex-6 FPGA GTX transceiver, Spartan®-6 FPGA GTP transceiver,
Virtex-7 FPGA GTX/GTH transceiver, Zynq™-7000 or Kintex™-7 device GTX transceiver,
Artix ™-7 FPGA GTP transceiver, or the Transmitter Elastic Buffer added in the example
design.
Transmit Path Latency
As measured from a data octet input into gmii_txd[7:0] of the transmitter side GMII
(until that data appears on txdata[7:0] on the serial transceiver interface), the latency
through the core in the transmit direction is 4 clock periods of userclk2.
Receive Path Latency
As measured from a data octet input into the core on rxdata[7:0] from the serial
transceiver interface (until that data appears on gmii_rxd[7:0] of the receiver side
GMII), the latency through the core in the receive direction is 6 clock periods of userclk2.
Latency for SGMII
When performing the SGMII standard, the core latency figures are identical to the Latency
for 1000BASE-X PCS and PMA using the serial transceiver. Again these figures do not
include the latency through the serial transceiver or any Elastic Buffers added in the
example design.
Throughput
1000BASE-X PCS and PMA or SGMII core operates at a full lane rate of 1.25 Gb/s
Voltage Requirements
Virtex-7 devices support GMII at 3.3 V or lower only in certain parts and packages; see the
7 Series FPGAs SelectIO Resources User Guide. Virtex-6 devices support TBI or GMII at 2.5 V
only; see the Virtex-6 FPGA Data Sheet: DC and Switching Characteristics. Kintex-7,
Spartan-6, Virtex-5, Virtex-4 and Spartan-3 devices support TBI and GMII at 3.3 V or lower.
Artix-7 and Zynq-7000 devices support GMII at 3.3 V or lower.
1000BASE-X PCS/PMA or SGMII v11.4
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Chapter 2: Product Specification
Speed Grades
Zynq-7000, Virtex-7, Kintex-7, Artix-7, Virtex-6, Virtex-5, Virtex-4 devices support speed
grade -1; Virtex-4 FPGA supports -10 speed grade; Spartan-6 FPGAs support -2 speed
grade. All other supported Spartan devices support -4 speed grade.
Resource Utilization
Resources required for this core have been estimated for the Zynq-7000, Virtex-7, Kintex-7,
Artix-7, Virtex-6, Virtex-5, and Spartan-6 devices, See Table 2-2 through Table 2-9. These
values were generated using Xilinx® CORE Generator™ tools, v14.3. They are derived from
post-synthesis reports, and might change during MAP and PAR. Similar values are expected
for Vivado IP catalog v2012.3.
Table 2-1:
Family Support for the 1000BASE-X PCS/PMA or SGMII Core
LogiCORE IP Functionality
Device
Family
Zynq-7000
Virtex-7
With TBI
Using
Device
Specific
Transceiver
Not
Supported
Supported
Not
Supported
Supported
1000BASE-X and SGMII
Standards with Dynamic
Switching
GMII to SGMII Bridge or
SGMII to GMII Bridge
1000BASE-X
With TBI
Using
Device
Specific
Transceiver
Using
Synchronous
LVDS
SelectIO
Not
Supported
Supported
Not
supported
Not
Supported
Using
Asynchronous
LVDS SelectIO
With TBI
Using Device
Specific
Transceiver
Not supported
Not
Supported
Supported
Supported
Supported
in -2 speed
grade and
faster parts for
HR banks; -1
speed grade
and faster for
HP banks
Available
through
XAPP523
Not
Supported
Supported
Available
through
XAPP523
Supported
Supported
Kintex-7
Supported
Supported
Supported
Supported
Supported
in -2 speed
grade and
faster parts for
HR banks; -1
speed grade
and faster for
HP banks
Artix-7
Not
Supported
Supported
Not
Supported
Supported
Not
supported
Not supported
Not
Supported
Supported
Virtex-6
Supported
Supported
Supported
Supported
Not
supported
Supported in -2
speed grade
and faster parts
Supported(1)
Supported
1000BASE-X PCS/PMA or SGMII v11.4
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Chapter 2: Product Specification
Table 2-1:
Family Support for the 1000BASE-X PCS/PMA or SGMII Core (Cont’d)
LogiCORE IP Functionality
Device
Family
With TBI
Using
Device
Specific
Transceiver
Virtex-5
Supported
Virtex-4
1000BASE-X and SGMII
Standards with Dynamic
Switching
GMII to SGMII Bridge or
SGMII to GMII Bridge
1000BASE-X
With TBI
Using
Device
Specific
Transceiver
Using
Synchronous
LVDS
SelectIO
Supported
Supported
Supported
Not
supported
Supported
Supported
Supported
Supported
Spartan-6
Supported
Supported
Supported
Spartan-3
Supported
Not
supported
Spartan-3E
Supported
Spartan-3
A
Supported
Using
Asynchronous
LVDS SelectIO
With TBI
Using Device
Specific
Transceiver
Not Supported
Supported
Supported
Not
supported
Not Supported
Supported
Supported
Supported
Not
supported
Not Supported
Supported
Supported
Supported
Not
supported
Not
supported
Not Supported
Supported
Not
supported
Not
supported
Supported
Not
supported
Not
supported
Not Supported
Supported
Not
supported
Not
supported
Supported
Not
supported
Not
supported
Not Supported
Supported
Not
supported
1. Virtex-6 devices support TBI at 2.5 V only; see the Virtex-6 FPGA Data Sheet: DC and Switching Characteristics.
Device Utilization
Zynq-7000, Virtex-7, Kintex-7, Artix-7, Virtex-6, Virtex-5 and Spartan-6 families contain six
input LUTs; all other families contain four input LUTs. For this reason, the device utilization
is listed separately. See one of the following for more information:
•
Zynq-7000, Virtex-7, Kintex-7, Artix-7, Virtex-6, Virtex-5, and Spartan-6 Devices
•
Other Device Families
Zynq-7000, Virtex-7, Kintex-7, Artix-7, Virtex-6, Virtex-5, and Spartan-6
Devices
Table 2-2, Table 2-3, and Table 2-4 provide approximate utilization figures for various core
options when a single instance of the core is instantiated in a Virtex-5 device.
Utilization figures are obtained by implementing the block-level wrapper for the core. This
wrapper is part of the example design and connects the core to the selected physical
interface.
1000BASE-X PCS/PMA or SGMII v11.4
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Chapter 2: Product Specification
BUFG Usage
•
BUFG usage does not consider multiple instantiations of the core, where clock
resources can often be shared.
•
BUFG usage does not include the reference clock required for IDELAYCTRL. This clock
source can be shared across the entire device and is not core specific.
1000BASE-X
Table 2-2:
Device Utilization for the 1000BASE-X Standard
Parameter Values
Physical Interface
Device Resources
MDIO
AutoInterface Negotiation Slices LUTs
FFs
Block
RAMs
BUFGs
MMCMs
Transceiver
TBI
Yes
No
Yes
Yes
330
370
470
0
1(2)
0 (2)
Yes
No
Yes
No
190
215
240
0
1 (2)
0 (2)
Yes
No
No
N/A (1)
140
170
180
0
1 (2)
0 (2)
No
Yes
Yes
Yes
380
410
590
1
3 (3)
0
No
Yes
Yes
No
230
280
370
1
3 (3)
0
No
Yes
No
N/A (1)
190
230
315
1
3 (3)
0
1. Auto-negotiation is only available when the MDIO Interface is selected.
2. These figures are for use with GTP transceivers; GTX transceivers require three BUFGs and one DCM.
3. Only two BUFGs might be required (see the User Guide)
SGMII Bridge
Table 2-3: Device Utilization for the GMII to SGMII or SGMII to GMII Bridge (Using Device
Specific Transceivers or TBI
Parameter Values
Physical Interface
Device Resources
MDIO
AutoInterface Negotiation Slices
LUTs
FFs
Block
RAMs
BUFGs
MMCMs
Transceiver
TBI
Yes
No
Yes
Yes
430
435
665
1
1 (2)
0 (2)
Yes
No
Yes
No
310
330
500
1
1 (2)
0 (2)
Yes
No
No
N/A (1)
280
270
450
1
1 (2)
0 (2)
No
Yes
Yes
Yes
400
460
620
1
3 (3)
0
No
Yes
Yes
No
290
360
460
1
3 (3)
0
No
Yes
No
N/A (1)
240
320
410
1
3 (3)
0
1. Auto-negotiation is only available when the MDIO Interface is selected.
2. These figures are for use with GTP transceivers; GTX transceivers require three BUFGs and one DCM.
3. Only two BUFGs might be required (see the User Guide)
1000BASE-X PCS/PMA or SGMII v11.4
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Chapter 2: Product Specification
1000BASE-X and SGMII Standards with Dynamic Switching
Table 2-4:
Device Utilization for 1000BASE-X and SGMII Standards with Dynamic Switching
Parameter Values
Physical Interface
Device Resources
MDIO
AutoInterface Negotiation Slices
LUTs
FFs
Block
RAMs
BUFGs
MMCMs
Transceiver
TBI
Yes
No
Yes
Yes
445
510
745
1
1 (2)
0 (2)
Yes
No
Yes
No
320
330
500
1
1 (2)
0 (2)
Yes
No
No
N/A (1)
280
285
440
1
1 (2)
0 (2)
No
Yes
Yes
Yes
405
530
700
1
3 (3)
0
No
Yes
Yes
No
275
365
460
1
3 (3)
0
No
Yes
No
N/A (1)
270
320
410
1
3 (3)
0
1. Auto-negotiation is only available when the MDIO Interface is selected.
2. These figures are for use with GTP transceivers; GTX transceivers require three BUFGs and one DCM.
3. Only two BUFGs might be required (see the User Guide).
Table 2-5: Device Utilization for the GMII to SGMII or SGMII to GMII Bridge over Select I/O
LVDS in Virtex-6 FPGAs
Parameter Values
Logical
block
MDIO
AutoInterface Negotiation
I/O Bank
clocking
logic (2)
Per SGMII
port
Device Resources
N/A
Slices
LUTs
FFs
Block
RAMs
Clock
Buffers
MMCMs
1
15
30
22
0
2 BUFIO
1 BUFR
3 BUFG
Yes
Yes
380
775
820
0
0
0
Yes
No
310
640
660
0
0
0
No
N/A (1)
265
590
615
0
0
0
1. Auto-negotiation is only available when the MDIO Interface is selected.
2. The I/O Bank clocking logic is only required once for multiple SGMII cores that place their LVDS I/O in the same I/O
Bank. Any SGMII ports that are required to be placed in additional I/O Banks require a new instantiation of the I/O
Bank clocking logic for each I/O Bank utilized.
1000BASE-X PCS/PMA or SGMII v11.4
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Chapter 2: Product Specification
Table 2-6: Device Utilization for GMII to SGMII or SGMII to GMII Bridge over Synchronous LVDS
in Virtex-7/Kintex-7 FPGAS
Parameter Values
Logical Block
Clocking Logic
Per SGMII port
MDIO
Interface
Device Resources
AutoNegotiation
N/A
Slices
LUTs
FFs
Block
RAMs
Clock
Buffers
MMCMs
1
0
0
0
0
5 BUFGs or
1 BUFG,
1 BUFIO
and 3
BUFRs or
1 BUFG
and 4
BUFHs
Yes
Yes
462
884
985
0
0
0
Yes
No
363
735
741
0
0
0
No
N/A
337
670
693
0
0
0
•
Auto-negotiation is only available when the MDIO Interface is selected.
•
The clocking logic is only required once for multiple SGMII cores.
Other Device Families
Table 2-7, Table 2-8, and Table 2-9 provide approximate utilization figures for various core
options when a single instance of the core is instantiated in a Virtex-4 device. Other families
have similar utilization figures, except as indicated. Utilization figures are obtained by
implementing the block-level wrapper for the core. This wrapper is part of the example
design and connects the core to the selected physical interface.
When the physical interface is a Virtex-4 FPGA RocketIO™ transceiver, utilization figures
include GT11 Calibration blocks and GT11 initialization/reset circuitry.
BUFG Usage
BUFG usage does not consider multiple instantiations of the core, where clock resources
can often be shared.
1000BASE-X PCS/PMA or SGMII v11.4
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Chapter 2: Product Specification
1000BASE-X
Table 2-7:
Device Utilization for the 1000BASE-X Standard
Parameter Values
Physical Interface
Device Resources
MDIO
AutoInterface Negotiation Slices
LUTs
FFs
Block
RAMs
BUFGs
DCMs
820
730
640
0
2 (2)
0
No
490
500
420
0
2 (2)
0
No
N/A (1)
430
440
360
0
2 (2)
0
Yes
Yes
Yes
650
640
600
2
3 (3)
1 (4)
No
Yes
Yes
No
420
410
380
2
3 (3)
1 (4)
No
Yes
No
N/A (1)
350
360
330
2
3 (3)
1 (4)
RocketIO
TBI
Yes
No
Yes
Yes
Yes
No
Yes
Yes
No
No
1. Auto-negotiation is only available when the MDIO Interface is selected.
2. For Virtex-4 devices, this includes the clock shared between the Calibration Blocks and the GT11 Dynamic
Reconfiguration Port (DRP).
3. Only two BUFGs might be required (see the User Guide).
4. Spartan-3, Spartan-3E and Spartan-3A devices require two DCMs to meet TBI setup and hold times.
SGMII Bridge
Table 2-8:
Device Utilization for the GMII to SGMII or SGMII to GMII Bridge
Parameter Values
Physical Interface
Device Resources
RocketIO
TBI
MDIO
Interface
AutoNegotiation Slices
LUTs
FFs
Block
RAMs
BUFGs
DCMs
Yes
No
Yes
Yes
970
780
860
1
2 (2)
0
Yes
No
Yes
No
730
620
670
1
2 (2)
0
Yes
No
No
N/A(1)
700
570
640
1
2 (2)
0
No
Yes
Yes
Yes
800
970
630
2
3 (3)
1 (4)
No
Yes
Yes
No
610
830
470
2
3 (3)
1 (4)
No
Yes
No
N/A(1)
560
770
420
2
3 (3)
1 (4)
1. Auto-negotiation is only available when the MDIO Interface is selected.
2. For Virtex-4 devices, this includes the clock shared between the Calibration Blocks and the GT11 Dynamic
Reconfiguration Port (DRP).
3. Only two BUFGs might be required.
4. Spartan-3, Spartan-3E and Spartan-3A devices require two DCMs to meet TBI setup and hold times.
1000BASE-X PCS/PMA or SGMII v11.4
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Chapter 2: Product Specification
1000BASE-X and SGMII Standards with Dynamic Switching
Table 2-9:
Device Utilization for the 1000BASE-X and SGMII Standards with Dynamic Switching
Parameter Values
Physical Interface
Device Resources
RocketIO
TBI
MDIO
Interface
AutoNegotiation Slices
LUTs
FFs
Block
RAMs
BUFGs
DCMs
Yes
No
Yes
Yes
1100
900
940
1
2 (2)
0
Yes
No
Yes
No
780
640
700
1
2 (2)
0
Yes
No
No
N/A (1)
700
570
640
1
2 (2)
0
No
Yes
Yes
Yes
910
1090
710
2
3 (3)
1 (4)
No
Yes
Yes
No
640
830
480
2
3 (3)
1 (4)
No
Yes
No
N/A (1)
560
770
420
2
3 (3)
1 (4)
1. Auto-negotiation is only available when the MDIO Interface is selected.
2. For Virtex-4 devices, this includes the clock shared between the Calibration Blocks and the GT11 Dynamic
Reconfiguration Port (DRP).
3. Only two BUFGs might be required (see the User Guide).
4. Spartan-3, Spartan-3E and Spartan-3A devices require two DCMs to meet TBI setup and hold times.
Port Descriptions
All ports of the core are internal connections in FPGA logic. An HDL example design
(delivered with the core) connects the core, where appropriate, to a device-specific
transceiver, LVDS transceiver logic and/or add IBUFs, OBUFs. IOB flip-flops to the external
signals of the GMII and TBI. IOBs are added to the remaining unconnected ports to take the
example design through the Xilinx implementation software.
All clock management logic is placed in this example design, allowing you more flexibility in
implementation (such as designs using multiple cores). This example design is provided in
both VHDL and Verilog.
For more information on the example design provided, see one of the following chapters
depending on your chosen standard and physical interface.
•
Chapter 4, The Ten-Bit Interface
•
Chapter 5, 1000BASE-X with Transceivers
•
Chapter 6, SGMII / Dynamic Standards Switching with Transceivers
•
Chapter 7, SGMII over LVDS
1000BASE-X PCS/PMA or SGMII v11.4
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Chapter 2: Product Specification
Figure 2-2 shows the pinout for the Ethernet 1000BASE-X PCS/PMA or SGMII core using a
device-specific transceiver, or LVDS transceiver logic, with the optional PCS Management
registers. The signals shown in the Auto-Negotiation box are included only when the core
includes the Auto-Negotiation functionality. For 7 series and Zynq-7000 devices, data width
of rxdata and txdata signals received from the device-specific transceiver is 16 bits. A
conversion logic is used to convert to 8 bits for core interface. For more information, see
Chapter 17, Customizing and Generating the Core.
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Figure 2-3 shows the pinout for the Ethernet 1000BASE-X PCS/PMA or SGMII core using a
device-specific transceiver, or LVDS transceiver logic without the optional PCS Management
registers For 7 series and Zynq-7000 devices, data width of rxdata and txdata signals
received from the device-specific transceiver is 16 bits. A conversion logic is used to
convert to 8 bits for core interface.
1000BASE-X PCS/PMA or SGMII v11.4
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Chapter 2: Product Specification
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Figure 2-3: Component Pinout Using a Transceiver
without PCS Management Registers
Figure 2-4 shows the pinout for the Ethernet 1000BASE-X PCS/PMA or SGMII core when
using the TBI with optional PCS Management registers. The signals shown in the
Auto-Negotiation box are included only when the core includes the Auto-Negotiation
functionality (see Chapter 17, Customizing and Generating the Core).
1000BASE-X PCS/PMA or SGMII v11.4
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Chapter 2: Product Specification
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Figure 2-4:
1000BASE-X PCS/PMA or SGMII v11.4
PG047 October 16, 2012
Component Pinout Using the Ten-Bit Interface
with PCS Management Registers
www.xilinx.com
37
Chapter 2: Product Specification
Figure 2-5 shows the pinout for the Ethernet 1000BASE-X PCS/PMA or SGMII core when
using a TBI without the optional PCS Management registers.
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Figure 2-5: Component Pinout Using Ten-Bit Interface
without PCS Management Registers
Figure 2-6 shows the pinout for the Ethernet 1000BASE-X PCS/PMA or SGMII core using the
optional dynamic switching logic (between 1000BASE-X and SGMII standards). This mode is
shown used with a device-specific transceiver interface. For 7 series and Zynq-7000 devices,
data width of rxdata and txdata signals received from the device-specific transceiver is
16 bits. A conversion logic is used to convert to 8 bits for core interface. For more
information, see Chapter 10, Dynamic Switching of 1000BASE-X and SGMII Standards.
1000BASE-X PCS/PMA or SGMII v11.4
PG047 October 16, 2012
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Chapter 2: Product Specification
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8
Figure 2-6:
Component Pinout with the Dynamic Switching Logic
Client Side Interface
GMII Pinout
Table 2-10 describes the GMII-side interface signals of the core common to all
parameterizations of the core. These are typically attached to an Ethernet MAC, either
off-chip or internally integrated. The HDL example design delivered with the core connects
these signals to IOBs to provide a place-and-route example.
1000BASE-X PCS/PMA or SGMII v11.4
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Chapter 2: Product Specification
For more information, see Chapter 8, Using the Client-Side GMII Datapath.
Table 2-10:
GMII Interface Signal Pinout
Signal
Direction
Description
Input
GMII Transmit data from MAC.
Input
GMII Transmit control signal from MAC.
Input
GMII Transmit control signal from MAC.
gmii_rxd[7:0](2)
Output
GMII Received data to MAC.
gmii_rx_dv
(2)
Output
GMII Received control signal to MAC.
gmii_rx_er
(2)
Output
GMII Received control signal to MAC.
Output
IOB 3-state control for GMII Isolation. Only of use when
implementing an External GMII as illustrated by the example
design HDL.
gmii_txd[7:0]
gmii_tx_en
gmii_tx_er
(1)
(1)
(1)
gmii_isolate
(2)
Notes:
1. When the Transmitter Elastic Buffer is present, these signals are synchronous to gmii_tx_clk. When the Transmitter
Elastic Buffer is omitted, see (2).
2. These signals are synchronous to the internal 125 MHz reference clock of the core. This is userclk2 when the core
is used with the device-specific transceiver; gtx_clk when the core is used with TBI.
Common Signal Pinout
Table 2-11 describes the remaining signals common to all parameterizations of the core.
Signals are synchronous to the core internal 125 MHz reference clock; userclk2 when
used with a device-specific transceiver; gtx_clk when used with TBI.
Table 2-11:
Other Common Signals
Signal
Direction
Clock Domain
Description
reset
Input
n/a
Asynchronous reset for the entire core. Active-High.
• Bit[0]: Link Status
This signal indicates the status of the link.
When high, the link is valid: synchronization of the link has
been obtained and Auto-Negotiation (if present and
enabled) has successfully completed.
When low, a valid link has not been established. Either link
synchronization has failed or Auto-Negotiation (if present
and enabled) has failed to complete.
When auto-negotiation is enabled, this signal is identical
to Status Register Bit 1.2: Link Status.
When auto-negotiation is disabled, this signal is identical
to status_vector Bit[1]. In this case, either of the bits can
be used.
1000BASE-X PCS/PMA or SGMII v11.4
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Chapter 2: Product Specification
Table 2-11:
Other Common Signals (Cont’d)
Signal
Direction
Clock Domain
Description
• Bit[1]: Link Synchronization
This signal indicates the state of the synchronization state
machine (IEEE802.3 figure 36-9) which is based on the
reception of valid 8B/10B code groups. This signal is
similar to Bit[0] (Link Status), but is not qualified with
Auto-Negotiation.
When high, link synchronization has been obtained and in
the synchronization state machine, sync_status=OK.
When low, synchronization has failed.
• Bit[2]: RUDI(/C/)
The core is receiving /C/ ordered sets (Auto-Negotiation
Configuration sequences).
status_vector[15:0]
Output
See note
• Bit[3]: RUDI(/I/)
The core is receiving /I/ ordered sets (Idles)
• Bit[4]: RUDI(INVALID)
The core has received invalid data while receiving/C/ or /I/
ordered set.
• Bit[5]: RXDISPERR
The core has received a running disparity error during the
8B/10B decoding function.
• Bit[6]: RXNOTINTABLE
The core has received a code group which is not
recognized from the 8B/10B coding tables.
• Bit[7]: PHY Link Status (SGMII mode only)
When operating in SGMII mode, this bit represents the
link status of the external PHY device attached to the
other end of the SGMII link (high indicates that the PHY
has obtained a link with its link partner; low indicates that
is has not linked with its link partner).
When operating in 1000BASE-X mode, this bit remains low
and should be ignored
• Bit[9:8]: Remote Fault Encoding
This signal indicates the remote fault encoding (IEEE802.3
table 37-3). This signal is validated by bit 13 of
status_vector and is only valid when Auto-Negotiation is
enabled.
This signal has no significance when the core is in SGMII
mode with PHY side implementation and indicates “00”. In
all the remaining modes the signal indicates the remote
fault encoding.
1000BASE-X PCS/PMA or SGMII v11.4
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Chapter 2: Product Specification
Table 2-11:
Other Common Signals (Cont’d)
Signal
Direction
Clock Domain
Description
• Bit [11:10]: SPEED
This signal indicates the speed negotiated and is only
valid when Auto-Negotiation is enabled. The signal
encoding follows:
Bit[11] Bit[10]
1
1
Reserved
1
0
1000 Mb/s
0
1
100 Mb/s
0
0
10 Mb/s
status_vector[15:0]
(Continued)
Output
See note
• Bit[12]: Duplex Mode
This bit indicates the Duplex mode negotiated with the
link partner
1 = Full Duplex
0 = Half Duplex
• Bit[13] Remote Fault
When this bit is logic one, it indicates that a remote fault
is detected and the type of remote fault is indicated by
status_vector bits[9:8].
Note: This bit is only deasserted when a MDIO read is
made to status register (register1). This signal has no
significance in SGMII PHY mode.
• Bits[15;14]: Pause
These bits reflect the bits [8:7] of Register 5 (Link Partner
Base AN Register)
Bit[15] Bit[14]
0
0
No Pause
0
1
Symmetric Pause
1
0
Asymmetric Pause towards Link partner
1
1
Both Symmetric Pause and Asymmetric
Pause towards link partner
MDIO Management Interface Pinout (Optional)
Table 2-12 describes the optional MDIO interface signals of the core that are used to access
the PCS Management registers. These signals are typically connected to the MDIO port of
a MAC device, either off-chip or to an internally integrated MAC core. For more information,
see Management Registers.
1000BASE-X PCS/PMA or SGMII v11.4
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Chapter 2: Product Specification
Table 2-12:
Optional MDIO Interface Signal Pinout
Signal
Direction
Clock Domain
Description
mdc
Input
N/A
Management clock (<= 2.5 MHz).
Input
mdc
Input data signal for communication with MDIO
controller (for example, an Ethernet MAC). Tie high
if unused.
Output
mdc
Output data signal for communication with MDIO
controller (for example, an Ethernet MAC).
Output
mdc
3-state control for MDIO signals; ‘0’ signals that the
value on mdio_out should be asserted onto the
MDIO interface.
Input
N/A
Physical Address of the PCS Management register
set. It is expected that this signal will be tied off to
a logical value.
mdio_ina
mdio_out(a)
mdio_tri(a)
phyad[4:0]
a. These signals can be connected to a 3-state buffer to create a bidirectional mdio signal suitable for connection to
an external MDIO controller (for example, an Ethernet MAC).
1000BASE-X PCS/PMA or SGMII v11.4
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Chapter 2: Product Specification
Additional Configuration Vector Interface
Table 2-13 shows the additional interface to program Management Registers 0 and 4
irrespective of the optional MDIO interface.
Table 2-13:
Additional Configuration and Status Vectors
Signal
Direction
configuration_vector[4:0]
configuration_valid
Input
Input
Clock
Domain
Description
See note
• Bit[0]:
Unidirectional Enable
When set to 1, Enable Transmit irrespective of
state of RX (802.3ah). When set to 0, Normal
operation
• Bit[1]: Loopback Control
When the core with a device-specific
transceiver is used, this places the core into
internal loopback mode. With the TBI version,
Bit 1 is connected to ewrap. When set to 1, this
signal indicates to the external PMA module to
enter loopback mode.
• Bit[2]: Power Down
When the Zynq-7000, Virtex-7, Kintex-7,
Artix-7, Virtex-6, Virtex-5 or Spartan-6 device
transceivers are used and set to 1, the
device-specific transceiver is placed in a
low-power state. A reset must be applied to
clear. With the TBI version this bit is unused.
• Bit[3] Isolate
When set to 1, the GMII should be electrically
isolated. When set to 0, normal operation is
enabled.
• Bit[4] Auto-Negotiation Enable
This signal is valid only if the AN module is
enabled through the CORE Generator™ GUI).
When set to 1, the signal enables the AN
feature. When set to 0, AN is disabled.
See Note
This signal is valid only when the MDIO
interface is present. The rising edge of this
signal is the enable signal to overwrite the
Register 0 contents that were written from the
MDIO interface. For triggering a fresh update
of Register 0 through configuration_vector, this
signal should be deasserted and then
reasserted.
Note: Signals are synchronous to the core internal 125 MHz reference clock; userclk2 when used with a
device-specific transceiver; gtx_clk when used with TBI.
1000BASE-X PCS/PMA or SGMII v11.4
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Chapter 2: Product Specification
Auto-Negotiation Signal Pinout
Table 2-14 describes the signals present when the optional Auto-Negotiation functionality
is present. For more information, see Chapter 9, Auto-Negotiation.
Table 2-14:
Optional Auto-Negotiation Interface Signal Pinout
Signal
link_timer_value[8:0]
Direction
Input
Clock
Domain
Description
See note
Used to configure the duration of the Auto-Negotiation
function Link Timer. The duration of this timer is set to the
binary number input into this port multiplied by 4096 clock
periods of the 125 MHz reference clock (8 ns).
It is expected that this signal will be tied off to a logical value.
This port is replaced when using the dynamic switching mode.
In SGMII operating in MAC Mode, the AN_ADV register is hard
wired internally to “0x4001” and this bus has no effect. For
1000BaseX and SGMII operating in PHY mode, the AN_ADV
register is programmed by this bus as specified for the following
bits.
• Bit[0]:
For 1000 BASEX-Reserved.
For SGMII- Always 1
• Bits [4:1]: Reserved
• Bit [5]:
For 1000 BASEX- Full Duplex
1 = Full Duplex Mode is advertised
0 = Full Duplex Mode is not advertised
For SGMII- Reserved
an_adv_config_vector
[15:0]
Input
See
Note
• Bit [6]: Reserved
• Bits [8:7]:
For 1000 BASEX- Pause
0 0 No Pause
0 1 Symmetric Pause
1 0 Asymmetric Pause towards link partner
1 1 Both Symmetric Pause and Asymmetric Pause towards link
partner
For SGMII - Reserved
• Bit [9]: Reserved
• Bits [11:10]:
For 1000 BASEX- Reserved
For SGMII- Speed
1 1 Reserved
1 0 1000 Mb/s
0 1 100 Mb/s
0 0 10 Mb/s
1000BASE-X PCS/PMA or SGMII v11.4
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Chapter 2: Product Specification
Table 2-14:
Optional Auto-Negotiation Interface Signal Pinout (Cont’d)
Signal
an_adv_config_vector
[15:0]
Direction
Input
Clock
Domain
Description
See
Note
• Bits [13:12]:
For 1000 BASEX- Remote Fault
0 0 No Error
0 1 Offline
1 0 Link Failure
1 1 Auto-Negotiation Error
For SGMII- Bit[13]: Reserved
• Bit[12]: Duplex Mode
1 Full Duplex
0 Half Duplex
• Bit [14]:
For 1000 BASEX- Reserved
For SGMII- Acknowledge
• Bit [15]:
For 1000 BASEX- Reserved
For SGMII- PHY Link Status
1 Link Up
0 Link Down
an_adv_config_val
an_restart_config
an_interrupt
Input
See
Note
This signal is valid only when the MDIO interface is present. The
rising edge of this signal is the enable signal to overwrite the
Register 4 contents that were written from the MDIO interface.
For triggering a fresh update of Register 4 through
an_adv_config_vector, this signal should be deasserted and then
reasserted.
Input
See
Note
This signal is valid only when AN is present. The rising edge of
this signal is the enable signal to overwrite Bit 9 or Register 0.
For triggering a fresh AN Start, this signal should be deasserted
and then reasserted.
See
Note
When the MDIO module is selected through the GUI interface,
this signal indicates an active-High interrupt for
Auto-Negotiation cycle completion which needs to be cleared
though MDIO. This interrupt can be enabled/disabled and
cleared by writing to the appropriate PCS Management register.
See the Ethernet 1000BASE-X PCS/PMA or SGMII User Guide.
When the MDIO module is not selected, this signal indicates AN
Complete, which is asserted as long as the Auto-Negotiation is
complete and AN is not restarted and cannot be cleared.
Output
Note: Signals are synchronous to the core internal 125 MHz reference clock, userclk2 when the core is used
with the device-specific transceiver, and gtx_clk when the core is used with TBI.
1000BASE-X PCS/PMA or SGMII v11.4
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Chapter 2: Product Specification
Dynamic Switching Signal Pinout
Table 2-15 describes the signals present when the optional Dynamic Switching mode
(between 1000BASE-X and SGMII standards) is selected. In this case, the MDIO (Table 2-12)
and device-specific transceiver (Table 2-16) interfaces are always present.
Table 2-15:
Optional Dynamic Standard Switching Signals
Signal
Direction
link_timer_basex[8:0] (1)
link_timer_sgmii[8:0](1)
basex_or_sgmii (1)
Description
Input
Used to configure the duration of the Auto-Negotiation Link
Timer period when performing the 1000BASE-X standard. The
duration of this timer is set to the binary number input into this
port multiplied by 4096 clock periods of the 125 MHz reference
clock (8 ns). It is expected that this signal will be tied off to a
logical value.
Input
Used to configure the duration of the Auto-Negotiation Link
Timer period when performing the SGMII standard. The
duration of this timer is set to the binary number input into this
port multiplied by 4096 clock periods of the 125 MHz reference
clock (8 ns). It is expected that this signal will be tied off to a
logical value.
Input
Used as the reset default to select the standard. It is expected
that this signal will be tied off to a logical value.
‘0’ signals that the core will come out of reset operating as
1000BASE-X.
‘1’ signals that the core will come out of reset operating as
SGMII.
Note: The standard can be set following reset through the
MDIO Management.
Notes:
1. Clock domain is userclk2.
Physical Side Interface
1000BASE-X PCS with PMA Using Transceiver Signal Pinout (Optional)
Table 2-16 describes the optional interface to the device-specific transceiver, or LVDS
transceiver logic. The core is connected to the chosen transceiver in the appropriate HDL
example design delivered with the core. For more information, see Appendix C, 1000BASE-X
State Machines.
•
Chapter 5, 1000BASE-X with Transceivers
•
Chapter 6, SGMII / Dynamic Standards Switching with Transceivers
•
Chapter 7, SGMII over LVDS
1000BASE-X PCS/PMA or SGMII v11.4
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Chapter 2: Product Specification
Table 2-16:
Optional Transceiver Interface Pinout
Signal
Direction
Description
mgt_rx_reset
(1)
Output
Reset signal issued by the core to the device-specific transceiver
receiver path. Connect to RXRESET signal of device-specific
transceiver.
mgt_tx_reset
(1)
Output
Reset signal issued by the core to the device-specific transceiver
transmitter path. Connect to TXRESET signal of device-specific
transceiver.
userclk
Input
Also connected to TXUSRCLK and RXUSRCLK of the
device-specific transceiver. Clock domain is not applicable.
userclk2
Input
Also connected to TXUSRCLK2 and RXUSRCLK2 of the
device-specific transceiver. Clock domain is not applicable.
Input
A Digital Clock Manager (DCM) can be used to derive userclk and
userclk2. This is implemented in the HDL design example
delivered with the core. The core uses this input to hold the
device-specific transceiver in reset until the DCM obtains lock.
Clock domain is not applicable. If DCM is not used, this signal
should be tied to '1'.
Input
Connect to device-specific transceiver signal of the same name.
Input
Connects to device-specific transceiver signal of the same name.
Input
Connects to device-specific transceiver signal of the same name.
Input
Connect to device-specific transceiver signal of the same name.
Input
Connect to device-specific transceiver signal of the same name.
Input
Connects to device-specific transceiver signal of the same name.
Input
Connects to device-specific transceiver signal of the same name.
Input
Connects to device-specific transceiver signal of the same name.
Input
Connects to device-specific transceiver signal of the same name.
Output
Connects to device-specific transceiver signal of the same name.
Output
Connects to device-specific transceiver signal of the same name.
txchardispval (1)
Output
Connects to device-specific transceiver signal of the same name.
txcharisk
Output
Connects to device-specific transceiver signal of the same name.
Output
Connect to device-specific transceiver signal of the same name.
Output
Allows the transceivers to serially realign to a comma character.
Connects to ENMCOMMAALIGN and ENPCOMMAALIGN of the
device-specific transceiver.
dcm_locked
rxbufstatus[1:0]
rxchariscomma
rxcharisk
rxdata[7:0]
txbuferr
(1)
(1)
(1)
rxnotintable
rxrundisp
(1)
(1)
rxclkcorcnt[2:0]
rxdisperr
(1)
(1)
(1)
(1)
powerdown
(1)
txchardispmode
(1)
txdata[7:0]
(1)
enablealign
(1)
(1)
Notes:
1. When the core is used with a device-specific transceiver, userclk2 is used as the 125 MHz reference clock for the
entire core.
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Chapter 2: Product Specification
1000BASE-X PCS with TBI Pinout
Table 2-17 describes the optional TBI signals, used as an alternative to the transceiver
interfaces. The appropriate HDL example design delivered with the core connects these
signals to IOBs to provide an external TBI suitable for connection to an off-device PMA
SERDES device. When the core is used with the TBI, gtx_clk is used as the 125 MHz
reference clock for the entire core. For more information, see Chapter 4, The Ten-Bit
Interface.
Table 2-17:
Optional TBI Interface Signal Pinout
Signal
Direction
Clock Domain
Description
gtx_clk
Input
N/A
Clock signal at 125 MHz. Tolerance must be
within IEEE 802.3-2008 specification.
tx_code_group[9:0]
Output
gtx_clk
10-bit parallel transmit data to PMA Sublayer
(SERDES).
loc_ref
Output
N/A
Causes the PMA sublayer clock recovery unit
to lock to pma_tx_clk. This signal is currently
tied to Ground.
ewrap
Output
gtx_clk
When ’1,’ this indicates to the external PMA
SERDES device to enter loopback mode. When
’0,’ this indicates normal operation
rx_code_group0[9:0]
Input
pma_rx_clk0
10-bit parallel received data from PMA
Sublayer (SERDES). This is synchronous to
pma_rx_clk0.
rx_code_group1[9:0]
Input
pma_rx_clk1
10-bit parallel received data from PMA
Sublayer (SERDES). This is synchronous to
pma_rx_clk1.
pma_rx_clk0
Input
N/A
Received clock signal from PMA Sublayer
(SERDES) at 62.5 MHz.
pma_rx_clk1
Input
N/A
Received clock signal from PMA Sublayer
(SERDES) at 62.5 MHz. This is 180 degrees out
of phase with pma_rx_clk0.
en_cdet
Output
gtx_clk
Enables the PMA Sublayer to perform comma
realignment. This is driven from the PCS
Receive Engine during the Loss-Of-Sync state.
Register Space
This section provides general guidelines for configuring and monitoring the Ethernet
1000BASE-X PCS/PMA or SGMII core, including a detailed description of the core
management registers. It also describes Configuration Vector and status signals, an
alternative to using the optional MDIO Management interface.
1000BASE-X PCS/PMA or SGMII v11.4
PG047 October 16, 2012
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49
Chapter 2: Product Specification
MDIO Management Interface
When the optional MDIO Management interface is selected, configuration and status of the
core is achieved by the Management registers accessed through the serial Management
Data Input/Output Interface (MDIO).
MDIO Bus System
The MDIO interface for 1 Gb/s operation (and slower speeds) is defined in IEEE 802.3-2008,
clause 22. Figure 2-7 illustrates an example MDIO bus system. This two-wire interface
consists of a clock (MDC) and a shared serial data line (MDIO). The maximum permitted
frequency of Management Data Clock (MDC) is set at 2.5 MHz. An Ethernet MAC is shown
as the MDIO bus master (the Station Management (STA) entity). Two PHY devices are shown
connected to the same bus, both of which are MDIO slaves (MDIO Managed Device (MMD)
entities).
X-Ref Target - Figure 2-7
-!# 34!
0(9 --$
#ONFIGURATION
2EGISTERS TO
2%'!$
(OST
"US )&
-$)/
MASTER
-$)/ SLAVE
-$)/
-$#
0HYSICAL
!DDRESS
0(9!$
0(9 --$
#ONFIGURATION
2EGISTERS TO
2%'!$
-$)/ SLAVE
0HYSICAL
!DDRESS
0(9!$
8
Figure 2-7:
1000BASE-X PCS/PMA or SGMII v11.4
PG047 October 16, 2012
A Typical MDIO-Managed System
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50
Chapter 2: Product Specification
The MDIO bus system is a standardized interface for accessing the configuration and status
registers of Ethernet PHY devices. In the example illustrated, the Management Host Bus I/F
of the Ethernet MAC is able to access the configuration and status registers of two PHY
devices using the MDIO bus.
MDIO Transactions
All transactions, read or write, are initiated by the MDIO master. All MDIO slave devices,
when addressed, must respond. MDIO transactions take the form of an MDIO frame,
containing fields for transaction type, address and data. This MDIO frame is transferred
across the MDIO wire synchronously to MDC. The abbreviations are used in this section are
explained in Table 2-18.
Table 2-18:
Abbreviations and Terms
Abbreviation
Term
PRE
Preamble
ST
Start of frame
OP
Operation code
PHYAD
Physical address
REGAD
Register address
TA
Turnaround
Write Transaction
Figure 2-8 shows a write transaction across the MDIO, defined as OP=”01.” The addressed
PHY device (with physical address PHYAD) takes the 16-bit word in the Data field and writes
it to the register at REGAD.
X-Ref Target - Figure 2-8
34! DRIVES -$)/
MDC
MDIO
: : 0 0 0 0 0 2 2 2 2 2 $ $ $ $
$
$
$
$
: :
$ $ $ $
$
$
$
$
)$,%
BITS
02%
34
/0
0(9!$
2%'!$
4!
BIT 72)4% $!4!
)$,%
8
Figure 2-8:
1000BASE-X PCS/PMA or SGMII v11.4
PG047 October 16, 2012
MDIO Write Transaction
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51
Chapter 2: Product Specification
Read Transaction
Figure 2-9 shows a read transaction, defined as OP=”10.” The addressed PHY device (with
physical address PHYAD) takes control of the MDIO wire during the turnaround cycle and
then returns the 16-bit word from the register at REGAD.
X-Ref Target - Figure 2-9
34! DRIVES -$)/
!DDRESSED --$ DRIVES -$)/
MDC
MDIO
: : 0 0 0 0 0 2 2 2 2 2 : $ $ $ $
$
$
$
$
: :
$ $ $ $
$
$
$
$
)$,%
BITS
02%
34
/0
0(9!$
2%'!$
4!
BIT 2%!$ $!4!
)$,%
8
Figure 2-9:
MDIO Read Transaction
MDIO Addressing
MDIO Addresses consists of two stages: Physical Address (PHYAD) and Register Address
(REGAD).
Physical Address (PHYAD)
As shown in Figure 2-7, two PHY devices are attached to the MDIO bus. Each of these has a
different physical address. To address the intended PHY, its physical address should be
known by the MDIO master (in this case an Ethernet MAC) and placed into the PHYAD field
of the MDIO frame (see MDIO Transactions).
The PHYAD field for an MDIO frame is a 5-bit binary value capable of addressing 32 unique
addresses. However, every MDIO slave must respond to physical address 0. This
requirement dictates that the physical address for any particular PHY must not be set to 0
to avoid MDIO contention. Physical Addresses 1 through to 31 can be used to connect up
to 31 PHY devices onto a single MDIO bus.
Physical Address 0 can be used to write a single command that is obeyed by all attached
PHYs, such as a reset or power-down command.
Register Address (REGAD)
Having targeted a particular PHY using PHYAD, the individual configuration or status
register within that particular PHY must now be addressed. This is achieved by placing the
individual register address into the REGAD field of the MDIO frame (see MDIO
Transactions).
1000BASE-X PCS/PMA or SGMII v11.4
PG047 October 16, 2012
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52
Chapter 2: Product Specification
The REGAD field for an MDIO frame is a 5-bit binary value capable of addressing 32 unique
addresses. The first 16 of these (registers 0 to 15) are defined by the IEEE 802.3-2008. The
remaining 16 (registers 16 to 31) are reserved for PHY vendors own register definitions.
For details of the register map of PHY layer devices and a more extensive description of the
operation of the MDIO Interface, see IEEE 802.3-2008.
Connecting the MDIO to an Internally Integrated STA
The MDIO ports of the Ethernet 1000BASE-X PCS/PMA or SGMII core can be connected to
the MDIO ports of an internally integrated Station Management (STA) entity, such as the
MDIO port of the Tri-Mode Ethernet MAC core (see Chapter 12, Interfacing to Other Cores).
Connecting the MDIO to an External STA
Figure 2-10 shows the MDIO ports of the Ethernet 1000BASE-X PCS/PMA or SGMII core
connected to the MDIO of an external STA entity. In this situation, mdio_in, mdio_out,
and mdio_tri must be connected to a 3-state buffer to create a bidirectional wire, mdio.
This 3-state buffer can either be external to the FPGA or internally integrated by using an
IOB IOBUF component with an appropriate SelectIO™ interface standard suitable for the
external PHY.
X-Ref Target - Figure 2-10
%THERNET "!3% 8 0#30-!
OR 3'-)) ,OGI#/2%
)/" ,/')#
)"5&
MDC
/
)
)0!$
MDC
)/0!$
MDIO
)/" ,/')#
)/"5&
MDIO?TRI
4
MDIO?OUT
)
)/
MDIO?IN
/
8
Figure 2-10:
1000BASE-X PCS/PMA or SGMII v11.4
PG047 October 16, 2012
Creating an External MDIO Interface
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53
Chapter 2: Product Specification
Management Registers
The contents of the Management registers can be accessed using the REGAD field of the
MDIO frame. Contents will vary depending on the CORE Generator™ or Vivado™ IP catalog
tool options, and are defined in the following sections in this guide.
•
1000BASE-X Standard Using the Optional Auto-Negotiation
•
1000BASE-X Standard Without the Optional Auto-Negotiation
•
SGMII Standard Using the Optional Auto-Negotiation
•
SGMII Standard without the Optional Auto-Negotiation
•
Both 1000BASE-X and SGMII Standards
The core can be reset three ways: reset, DCM_LOCKED and soft reset. All of these methods
reset all the registers to the default values.
1000BASE-X Standard Using the Optional Auto-Negotiation
More information on the 1000BASE-X PCS registers can be found in clause 22 and clause 37
of the IEEE 802.3-2006 specification. Registers at undefined addresses are read-only and
return 0s. The core can be reset three ways: reset, DCM_LOCKED and soft reset. All of these
methods reset all the registers to the default values.
Table 2-19:
MDIO Registers for 1000BASE-X with Auto-Negotiation
Register Address
Register Name
0
Control Register
1
Status Register
2,3
PHY Identifier
4
Auto-Negotiation Advertisement Register
5
Auto-Negotiation Link Partner Ability Base Register
6
Auto-Negotiation Expansion Register
7
Auto-Negotiation Next Page Transmit Register
8
Auto-Negotiation Next Page Receive Register
15
Extended Status Register
16
Vendor Specific: Auto-Negotiation Interrupt Control
1000BASE-X PCS/PMA or SGMII v11.4
PG047 October 16, 2012
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54
Chapter 2: Product Specification
Register 0: Control Register
X-Ref Target - Figure 2-11
$50,%8 -/$%
#/,,)3)/. 4%34
30%%$
5.)$)2%#4)/.!, %.!",%
2EG
2%3%26%$
2%34!24 !54/ .%'
)3/,!4%
0/7%2 $/7.
Table 2-20:
!54/ .%' %.!",%
30%%$
,//0"!#+
2%3%4
Figure 2-11:
8
MDIO Register 0: Control Register
Control Register (Register 0)
Bit(s)
Name
Description
Attributes
Default
Value
0.15
Reset
1 = Core Reset
0 = Normal Operation
Read/write
Self clearing
0
0.14
Loopback
1 = Enable Loopback Mode
0 = Disable Loopback Mode
When used with a device-specific
transceiver, the core is placed in internal
loopback mode.
With the TBI version, Bit 1 is connected to
ewrap. When set to ‘1,’ indicates to the
external PMA module to enter loopback
mode.
See Loopback.
Read/write
0
0.13
Speed Selection
(LSB)
Always returns a 0 for this bit. Together
with bit 0.6, speed selection of 1000 Mb/s
is identified
Returns 0
0
0.12
Auto-Negotiation
Enable
1 = Enable Auto-Negotiation Process
0 = Disable Auto-Negotiation Process
Read/write
1
0.11
Power Down
1 = Power down
0 = Normal operation
With the PMA option, when set to ’1’ the
device-specific transceiver is placed in a
low-power state. This bit requires a reset
(see bit 0.15) to clear.
With the TBI version this register bit has
no effect.
Read/ write
0
0.10
Isolate
1 = Electrically Isolate PHY from GMII
0 = Normal operation
Read/write
1
1000BASE-X PCS/PMA or SGMII v11.4
PG047 October 16, 2012
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55
Chapter 2: Product Specification
Table 2-20:
Control Register (Register 0) (Cont’d)
Bit(s)
Name
Description
Attributes
Default
Value
0.9
Restart AutoNegotiation
1 = Restart Auto-Negotiation Process
0 = Normal Operation
Read/write
Self clearing
0
0.8
Duplex Mode
Always returns a ‘1’ for this bit to signal
Full-Duplex Mode.
Returns 1
1
0.7
Collision Test
Always returns a ‘0’ for this bit to disable
COL test.
Returns 0
0
0.6
Speed Selection
(MSB)
Always returns a ‘1’ for this bit. Together
with bit 0.13, speed selection of 1000
Mb/s is identified.
Returns 1
1
0.5
Unidirectional
Enable
Enable transmit regardless of whether a
valid link has been established. This
feature is only possible if
Auto-Negotiation Enable bit 0.12 is
disabled
Read/ write
0
0.4:0
Reserved
Always return 0s, writes ignored.
Returns 0s
00000
Register 1: Status Register
X-Ref Target - Figure 2-12
%84%.$%$ 34!453
5.)$)2%#4)/.!, !.),)49
-& 02%!-",% 35002%33)/.
!54/ .%' #/-0,%4%
2%-/4% &!5,4
!54/ .%' !"),)49
,).+ 34!453
*!""%2 $%4%#4
2EG
%84%.$%$ #!0!"),)49
"!3% 4 (!,& $50,%8
"!3% 4 &5,, $50,%8
-BS (!,& $50,%8
-BS &5,, $50,%8
"!3% 8 (!,& $50,%8
"!3% 8 &5,, $50,%8
"!3% 4
8
Figure 2-12:
Table 2-21:
MDIO Register 1: Status Register
Status Register (Register 1)
Bit(s)
Name
Description
Attributes
Default
Value
1.15
100BASE-T4
Always returns a ‘0’ as 100BASE-T4 is not
supported.
Returns 0
0
1.14
100BASE-X Full Duplex
Always returns a ‘0’ as 100BASE-X full duplex
is not supported.
Returns 0
0
1.13
100BASE-X Half Duplex
Always returns a ‘0’ as 100BASE-X half
duplex is not supported.
Returns 0
0
1000BASE-X PCS/PMA or SGMII v11.4
PG047 October 16, 2012
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56
Chapter 2: Product Specification
Table 2-21:
Status Register (Register 1) (Cont’d)
Bit(s)
Name
Description
Attributes
Default
Value
1.12
10 Mb/s Full Duplex
Always returns a ‘0’ as 10 Mb/s full duplex is
not supported.
Returns 0
0
1.11
10 Mb/s Half Duplex
Always returns a ‘0’ as 10 Mb/s half duplex is
not supported
Returns 0
0
1.10
100BASE-T2 Full
Duplex
Always returns a ‘0’ as 100BASE-T2 full
duplex is not supported.
Returns 0
0
1.9
100BASE-T2 Half
Duplex
Always returns a ‘0’ as 100BASE-T2 Half
Duplex is not supported.
Returns 0
0
1.8
Extended Status
Always returns a ‘1’ to indicate the presence
of the Extended Register (Register 15).
Returns 1
1
1.7
Unidirectional Ability
Always returns a ‘1,’ writes ignored
Returns 1
1
1.6
MF Preamble
Suppression
Always returns a ‘1’ to indicate that
Management Frame Preamble Suppression
is supported.
Returns 1
1
1.5
Auto- Negotiation
Complete
1 = Auto-Negotiation process completed
0 = Auto-Negotiation process not
completed
Read only
0
1.4
Remote Fault
1 = Remote fault condition detected
0 = No remote fault condition detected
Read only
Selfclearing on
read
0
1.3
Auto- Negotiation
Ability
Always returns a ‘1’ for this bit to indicate
that the PHY is capable of Auto-Negotiation.
Returns 1
1
1.2
Link Status
1 = Link is up
0 = Link is down (or has been down)
Latches '0' if Link Status goes down. Clears to
current Link Status on read.
See the following Link Status section for
further details.
Read only
Self
clearing on
read
0
1.1
Jabber Detect
Always returns a ‘0’ for this bit because
Jabber Detect is not supported.
Returns 0
0
1.0
Extended Capability
Always returns a ‘0’ for this bit because no
extended register set is supported.
Returns 0
0
Link Status
When high, the link is valid and has remained valid after this register was last read;
synchronization of the link has been obtained and Auto-Negotiation (if enabled) has
completed.
When low, either:
1000BASE-X PCS/PMA or SGMII v11.4
PG047 October 16, 2012
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57
Chapter 2: Product Specification
•
A valid link has not been established: link synchronization has failed or
Auto-Negotiation (if enabled) has failed to complete.
OR
•
Link synchronization was lost at some point after this register was previously read.
However, the current link status might be good. Therefore read this register a second
time to get confirmation of the current link status.
Regardless of whether Auto-Negotiation is enabled or disabled, there can be some delay to
the deassertion of Link Status following the loss of synchronization of a previously
successful link. This is due to the Auto-Negotiation state machine which requires that
synchronization is lost for an entire link timer duration before changing state. For more
information, see the 802.3 specification (the an_sync_status variable).
Registers 2 and 3: PHY Identifiers
X-Ref Target - Figure 2-13
2EG
/2'!.):%
5.)15% )$
2EG
2%6)3)/. ./
-!5&!#452%2
-/$%, ./
/2'!.):%
5.)15% )$
8
Figure 2-13:
Table 2-22:
Registers 2 and 3: PHY Identifiers
PHY Identifier (Registers 2 and 3)
Bit(s)
Name
Description
Attributes
Default Value
2.15:0
Organizationally Unique
Identifier
Always return 0s
returns 0s
0000000000000000
3.15:10
Organizationally Unique
Identifier
Always return 0s
returns 0s
000000
3.9:4
Manufacturer model
number
Always return 0s
returns 0s
000000
3.3:0
Revision Number
Always return 0s
returns 0s
0000
1000BASE-X PCS/PMA or SGMII v11.4
PG047 October 16, 2012
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58
Chapter 2: Product Specification
Register 4: Auto-Negotiation Advertisement
X-Ref Target - Figure 2-14
&5,, $50,%8
(!,& $50,%8
2EG
2%3%26%$
0!53%
2%3%26%$
2%-/4% &!5,4
Table 2-23:
2%3%26%$
.%84 0!'%
Figure 2-14:
8
MDIO Register 4: Auto-Negotiation Advertisement
Auto-Negotiation Advertisement Register (Register 4)
Bit(s)
Name
Description
Attributes
Default
Value
4.15
Next Page
Core currently does not support Next Page.
Can be enabled, if requested. Writes ignored.
read/write
0
4.14
Reserved
Always returns ‘0,’ writes ignored
returns 0
0
4.13:12
Remote
Fault
00
01
10
11
read/write
self clearing to 00
after
Auto-Negotiation
00
4.11:9
Reserved
Always return 0s, writes ignored
returns 0
0
4.8:7
Pause
00 = No PAUSE
01 = Symmetric PAUSE
10 = Asymmetric PAUSE towards link partner
11 = Both Symmetric PAUSE and Asymmetric
PAUSE towards link partner
read/write
11
4.6
Half Duplex
Always returns a ‘0’ for this bit because Half
Duplex Mode is not supported
returns 0
0
4.5
Full Duplex
1 = Full Duplex Mode is advertised
0 = Full Duplex Mode is not advertised
read/write
1
4.4:0
Reserved
Always return 0s , writes ignored
returns 0s
00000
=
=
=
=
No Error
Offline
Link Failure
Auto-Negotiation Error
1000BASE-X PCS/PMA or SGMII v11.4
PG047 October 16, 2012
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59
Chapter 2: Product Specification
Register 5: Auto-Negotiation Link Partner Base
X-Ref Target - Figure 2-15
&5,, $50,%8
(!,& $50,%8
2EG
2%3%26%$
0!53%
2%3%26%$
2%-/4% &!5,4
Table 2-24:
!#+./7,%$'%
.%84 0!'%
Figure 2-15:
8
MDIO Register 5: Auto-Negotiation Link Partner Base
Auto-Negotiation Link Partner Ability Base Register (Register 5)
Bit(s)
Name
Description
Attributes
Default
Value
5.15
Next Page
1 = Next Page functionality is supported
0 = Next Page functionality is not supported
read only
0
5.14
Acknowledge
Used by Auto-Negotiation function to indicate
reception of a link partner’s base or next page
read only
0
5.13:12
Remote Fault
00
01
10
11
read only
00
5.11:9
Reserved
Always return 0s
returns 0s
000
5.8:7
Pause
00 = No PAUSE
01 = Symmetric PAUSE
10 = Asymmetric PAUSE towards link partner
11 = Both Symmetric PAUSE and Asymmetric
PAUSE supported
read only
00
5.6
Half Duplex
1 = Half Duplex Mode is supported
0 = Half Duplex Mode is not supported
read only
0
5.5
Full Duplex
1 = Full Duplex Mode is supported
0 = Full Duplex Mode is not supported
read only
0
5.4:0
Reserved
Always return 0s
returns 0s
00000
1000BASE-X PCS/PMA or SGMII v11.4
PG047 October 16, 2012
=
=
=
=
No Error
Offline
Link Failure
Auto-Negotiation Error
www.xilinx.com
60
Chapter 2: Product Specification
Register 6: Auto-Negotiation Expansion
X-Ref Target - Figure 2-16
.%84 0!'% !",%
0!'% 2%#%)6%$
2EG
2%3%26%$
2%3%26%$
8
Figure 2-16:
Table 2-25:
MDIO Register 6: Auto-Negotiation Expansion
Auto-Negotiation Expansion Register (Register 6)
Bit(s)
Name
Description
Attributes
Default Value
6.15:3
Reserved
Always returns 0s
returns 0s
0000000000000
6.2
Next Page
Able
This bit is ignored as the core
currently does not support next
page. This feature can be enabled on
request.
returns 1
1
6.1
Page
Received
1 = A new page has been received
0 = A new page has not been
received
read only
self clearing on
read
0
6.0
Reserved
Always returns 0s
returns 0s
0000000
Register 7: Next Page Transmit
X-Ref Target - Figure 2-17
2EG
-%33!'% #/$%
4/'',%
1000BASE-X PCS/PMA or SGMII v11.4
PG047 October 16, 2012
!#+./7,%$'%
-%33!'% 0!'%
2%3%26%$
.%84 0!'%
Figure 2-17:
8
MDIO Register 7: Next Page Transmit
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61
Chapter 2: Product Specification
Table 2-26:
Auto-Negotiation Next Page Transmit (Register 7)
Bit(s)
Name
Description
Attributes
Default
Value1
7.15
Next Page
1 = Additional Next Page(s) will follow
0 = Last page
read/
write
0
7.14
Reserved
Always returns ‘0’
returns 0
0
7.13
Message Page
1 = Message Page
0 = Unformatted Page
read/
write
1
7.12
Acknowledge 2
1 = Comply with message
0 = Cannot comply with message
read/
write
0
7.11
Toggle
Value toggles between subsequent Next
Pages
read only
0
7.10:0
Message /
Unformatted Code
Field
Message Code Field or Unformatted Page
Encoding as dictated by 7.13
read/
write
00000000001
(Null Message
Code)
Notes:
1. This register returns the default values as the core currently does not support next page. This feature can be
enabled on request.
Register 8: Next Page Receive
X-Ref Target - Figure 2-18
2EG
-%33!'% #/$%
4/'',%
Table 2-27:
!#+./7,%$'%
-%33!'% 0!'%
!#+./7,%$'%
.%84 0!'%
Figure 2-18:
8
MDIO Register 8: Next Page Receive
Auto-Negotiation Next Page Receive (Register 8)
Bit(s)
Name
Description
Attributes
Default Value
8.15
Next Page
1 = Additional Next Page(s) will follow
0 = Last page
read only
0
8.14
Acknowledge
Used by Auto-Negotiation function to
indicate reception of a link partner’s
base or next page
read only
0
8.13
Message Page
1 = Message Page
0 = Unformatted Page
read only
0
1000BASE-X PCS/PMA or SGMII v11.4
PG047 October 16, 2012
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62
Chapter 2: Product Specification
Table 2-27:
Auto-Negotiation Next Page Receive (Register 8) (Cont’d)
Bit(s)
Name
Description
Attributes
Default Value
8.12
Acknowledge 2
1 = Comply with message
0 = Cannot comply with message
read only
0
8.11
Toggle
Value toggles between subsequent
Next Pages
read only
0
8.10:0
Message /
Unformatted Code
Field
Message Code Field or Unformatted
Page Encoding as dictated by 8.13
read only
00000000000
Register 15: Extended Status
X-Ref Target - Figure 2-19
2EG
2%3%26%$
"!3% 4 (!,& $50,%8
"!3% 4 &5,, $50,%8
Table 2-28:
"!3% 8 (!,& $50,%8
"!3% 8 &5,, $50,%8
Figure 2-19:
8
MDIO Register 15: Extended Status Register
Extended Status Register (Register 15)
Bit(s)
Name
Description
Attributes
Default Value
15.15
1000BASE-X Full
Duplex
Always returns a ‘1’ for this bit because
1000BASE-X Full Duplex is supported
returns 1
1
15.14
1000BASE-X Half
Duplex
Always returns a ‘0’ for this bit because
1000BASE-X Half Duplex is not
supported
returns 0
0
15.13
1000BASE-T Full
Duplex
Always returns a ‘0’ for this bit because
1000BASE-T Full Duplex is not
supported
returns 0
0
15.12
1000BASE-T Half
Duplex
Always returns a ‘0’ for this bit because
1000BASE-T Half Duplex is not
supported
returns 0
0
15:11:0
Reserved
Always return 0s
returns 0s
000000000000
1000BASE-X PCS/PMA or SGMII v11.4
PG047 October 16, 2012
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63
Chapter 2: Product Specification
Register 16: Vendor-Specific Auto-Negotiation Interrupt Control
X-Ref Target - Figure 2-20
2EG
).4%22504 %.!",%
).4%22504 34!453
2%3%26%$
8
Figure 2-20:
Table 2-29:
MDIO Register 16: Vendor Specific Auto-Negotiation Interrupt Control
Vendor Specific Register: Auto-Negotiation Interrupt Control Register (Register 16)
Bit(s)
Name
Description
Attributes
Default Value
16.15:2
Reserved
Always return 0s
returns 0s
00000000000000
read/
write
0
read/
write
1
Interrupt
Status
16.1
1 = Interrupt is asserted
0 = Interrupt is not asserted
If the interrupt is enabled, this bit is
asserted on the completion of an
Auto-Negotiation cycle; it is only
cleared by writing ‘0’ to this bit.
If the Interrupt is disabled, the bit is set
to ‘0.’
Note: The an_interrupt port of the
core is wired to this bit.
Interrupt
Enable
16.0
1 = Interrupt enabled
0 = Interrupt disabled
1000BASE-X Standard Without the Optional Auto-Negotiation
It is not in the scope of this document to fully describe the 1000BASE-X PCS registers. See
clauses 22 and 37 of the IEEE 802.3-2008 specification for further information.
Registers at undefined addresses are read-only and return 0s. The core can be reset three
ways: reset, DCM_LOCKED and soft reset. All of these methods reset all the registers to the
default values.
Table 2-30:
MDIO Registers for 1000BASE-X without Auto-Negotiation
Register Address
Register Name
0
Control Register
1
Status Register
2,3
PHY Identifier
15
Extended Status Register
1000BASE-X PCS/PMA or SGMII v11.4
PG047 October 16, 2012
www.xilinx.com
64
Chapter 2: Product Specification
Register 0: Control Register
X-Ref Target - Figure 2-21
$50,%8 -/$%
#/,,)3)/. 4%34
30%%$
5.)$)2%#4)/.!, %.!",%
2EG
2%3%26%$
2%34!24 !54/ .%'
)3/,!4%
0/7%2 $/7.
Table 2-31:
!54/ .%' %.!",%
30%%$
,//0"!#+
2%3%4
Figure 2-21:
8
MDIO Register 0: Control Register
Control Register (Register 0)
Bit(s)
Name
Description
Attributes
Default
Value
0.15
Reset
1 = PCS/PMA reset
0 = Normal Operation
read/write
self clearing
0
0.14
Loopback
1 = Enable Loopback Mode
0 = Disable Loopback Mode
When used with a device-specific
transceiver, the core is placed in internal
loopback mode.
With the TBI version, Bit 1 is connected to
ewrap. When set to ‘1’ indicates to the
external PMA module to enter loopback
mode.
See Loopback.
read/write
0
0.13
Speed Selection
(LSB)
Always returns a 0 for this bit. Together with
bit 0.6, speed selection of 1000 Mb/s is
identified.
returns 0
0
0.12
Auto-Negotiation
Enable
Ignore this bit because Auto-Negotiation is
not included.
read/ write
1
0.11
Power Down
1 = Power down
0 = Normal operation
With the PMA option, when set to ’1’ the
device-specific transceiver is placed in a
low- power state. This bit requires a reset
(see bit 0.15) to clear.
With the TBI version this register bit has no
effect.
read/ write
0
0.10
Isolate
1 = Electrically Isolate PHY from GMII
0 = Normal operation
read/write
1
0.9
Restart AutoNegotiation
Ignore this bit because Auto-Negotiation is
not included.
read/ write
0
1000BASE-X PCS/PMA or SGMII v11.4
PG047 October 16, 2012
www.xilinx.com
65
Chapter 2: Product Specification
Table 2-31:
Control Register (Register 0) (Cont’d)
Bit(s)
Name
Description
Attributes
Default
Value
0.8
Duplex Mode
Always returns a ‘1’ for this bit to signal
Full-Duplex Mode.
returns 1
1
0.7
Collision Test
Always returns a ‘0’ for this bit to disable
COL test.
returns 0
0
0.6
Speed Selection
(MSB)
Always returns a ‘1’ for this bit. Together with
bit 0.13, speed selection of 1000 Mb/s is
identified
returns 1
1
0.5
Unidirectional
Enable
Enables transmit irrespective of receive.
Unidirectional feature is enabled
automatically when this bit is set because
optional Auto-Negotiation is not present.
read/ write
0
0.4:0
Reserved
Always return 0s , writes ignored.
returns 0s
00000
Register 1: Status Register
X-Ref Target - Figure 2-22
%84%.$%$ 34!453
5.)$)2%#4)/.!, !.),)49
-& 02%!-",% 35002%33)/.
!54/ .%' #/-0,%4%
2%-/4% &!5,4
!54/ .%' !"),)49
,).+ 34!453
*!""%2 $%4%#4
2EG
%84%.$%$ #!0!"),)49
"!3% 4 (!,& $50,%8
"!3% 4 &5,, $50,%8
-BS (!,& $50,%8
-BS &5,, $50,%8
"!3% 8 (!,& $50,%8
"!3% 8 &5,, $50,%8
"!3% 4
8
Figure 2-22:
Table 2-32:
MDIO Register 1: Status Register
Status Register (Register 1)
Bit(s)
Name
Description
Attributes
Default
Value
1.15
100BASE-T4
Always returns a ‘0’ for this bit because
100BASE-T4 is not supported
returns 0
0
1.14
100BASE-X Full Duplex
Always returns a ‘0’ for this bit because
100BASE-X Full Duplex is not supported
returns 0
0
1.13
100BASE-X Half Duplex
Always returns a ‘0’ for this bit because
100BASE-X Half Duplex is not supported
returns 0
0
1.12
10 Mb/s Full Duplex
Always returns a ‘0’ for this bit because 10
Mb/s Full Duplex is not supported
returns 0
0
1000BASE-X PCS/PMA or SGMII v11.4
PG047 October 16, 2012
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66
Chapter 2: Product Specification
Table 2-32:
Status Register (Register 1) (Cont’d)
Bit(s)
Name
Description
Attributes
Default
Value
1.11
10 Mb/s Half Duplex
Always returns a ‘0’ for this bit because 10
Mb/ s Half Duplex is not supported
returns 0
0
1.10
100BASE-T2 Full Duplex
Always returns a ‘0’ for this bit because
100BASE-T2 Full Duplex is not supported
returns 0
0
1.9
100BASE-T2 Half
Duplex
Always returns a ‘0’ for this bit because
100BASE-T2 Half Duplex is not supported
returns 0
0
1.8
Extended Status
Always returns a ‘1’ for this bit to indicate the
presence of the Extended Register (Register
15)
returns 1
1
1.7
Unidirectional Ability
Always returns 1, writes ignored
returns 1
1
1.6
MF Preamble
Suppression
Always returns a ‘1’ for this bit to indicate
that Management Frame Preamble
Suppression is supported
returns 1
1
1.5
Auto- Negotiation
Complete
Ignore this bit because Auto-Negotiation is
not included.
returns 1
1
1.4
Remote Fault
Always returns a ‘0’ for this bit because
Auto-Negotiation is not included.
returns 0
0
1.3
Auto- Negotiation
Ability
Ignore this bit because Auto-Negotiation is
not included.
returns 0
0
1.2
Link Status
1 = Link is up
0 = Link is down
Latches '0' if Link Status goes down. Clears to
current Link Status on read.
See the following Link Status section for
further details.
read only
self
clearing on
read
0
1.1
Jabber Detect
Always returns a ‘0’ for this bit because
Jabber Detect is not supported
returns 0
0
1.0
Extended Capability
Always returns a ‘0’ for this bit because no
extended register set is supported
returns 0
0
Link Status
When high, the link is valid and has remained valid after this register was last read;
synchronization of the link has been obtained.
When low, either:
•
A valid link has not been established; link synchronization has failed.
OR
1000BASE-X PCS/PMA or SGMII v11.4
PG047 October 16, 2012
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67
Chapter 2: Product Specification
•
Link synchronization was lost at some point after this register was previously read.
However, the current link status might be good. Therefore read this register a second
time to get confirmation of the current link status.
Registers 2 and 3: Phy Identifier
X-Ref Target - Figure 2-23
2EG
/2'!.):%
5.)15% )$
2EG
2%6)3)/. ./
-!5&!#452%2
-/$%, ./
/2'!.):%
5.)15% )$
8
Figure 2-23:
Table 2-33:
MDIO Registers 2 and 3: PHY Identifier
PHY Identifier (Registers 2 and 3)
Bit(s)
Name
Description
Attributes
Default Value
2.15:0
Organizationally Unique
Identifier
Always return 0s
returns 0s
0000000000000000
3.15:10
Organizationally Unique
Identifier
Always return 0s
returns 0s
000000
3.9:4
Manufacturer model number
Always return 0s
returns 0s
000000
3.3:0
Revision Number
Always return 0s
returns 0s
0000
1000BASE-X PCS/PMA or SGMII v11.4
PG047 October 16, 2012
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68
Chapter 2: Product Specification
Register 15: Extended Status
X-Ref Target - Figure 2-24
2EG
2%3%26%$
Table 2-34:
"!3% 4 (!,& $50,%8
"!3% 4 &5,, $50,%8
"!3% 8 (!,& $50,%8
"!3% 8 &5,, $50,%8
Figure 2-24:
8
MDIO Register 15: Extended Status
Extended Status (Register 15)
Bit(s)
Name
Description
Attributes
Default Value
15.15
1000BASE-X Full
Duplex
Always returns a ‘1’ because
1000BASE-X Full Duplex is
supported
returns 1
1
15.14
1000BASE-X Half
Duplex
Always returns a ‘0’ because
1000BASE-X Half Duplex is not
supported
returns 0
0
15.13
1000BASE-T Full
Duplex
Always returns a ‘0’ because
1000BASE-T Full Duplex is not
supported
returns 0
0
15.12
1000BASE-T Half
Duplex
Always returns a ‘0’ because
1000BASE-T Half Duplex is not
supported
returns 0
0
15:11:0
Reserved
Always return 0s
returns 0s
000000000000
SGMII Standard Using the Optional Auto-Negotiation
The registers provided for SGMII operation in this core are adaptations of those defined in
clauses 22 and 37 of the IEEE 802.3-2008 specif ication. In an SGMII implementation, two
different types of links exist. They are the SGMII link between the MAC and PHY (SGMII link)
and the link across the Ethernet Medium itself (Medium). See Figure 9-2.
Information regarding the state of both of these links is contained within the following
registers. Where applicable, the abbreviations SGMII link and Medium are used in the
register descriptions. Registers at undefined addresses are read-only and return 0s. The
core can be reset three ways: reset, DCM_LOCKED and soft reset. All of these methods reset
all the registers to the default values.
1000BASE-X PCS/PMA or SGMII v11.4
PG047 October 16, 2012
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69
Chapter 2: Product Specification
.
Table 2-35:
MDIO Registers for SGMII with Auto-Negotiation
Register Address
Register Name
0
SGMII Control Register
1
SGMII Status Register
2,3
PHY Identifier
4
SGMII Auto-Negotiation Advertisement Register
5
SGMII Auto-Negotiation Link Partner Ability Base Register
6
SGMII Auto-Negotiation Expansion Register
7
SGMII Auto-Negotiation Next Page Transmit Register
8
SGMII Auto-Negotiation Next Page Receive Register
15
SGMII Extended Status Register
16
SGMII Vendor Specific: Auto-Negotiation Interrupt Control
Register 0: SGMII Control
X-Ref Target - Figure 2-25
$50,%8 -/$%
#/,,)3)/. 4%34
30%%$
5.)$)2%#4)/.!, %.!",%
2EG
2%3%26%$
2%34!24 !54/ .%'
)3/,!4%
1000BASE-X PCS/PMA or SGMII v11.4
PG047 October 16, 2012
0/7%2 $/7.
!54/ .%' %.!",%
30%%$
,//0"!#+
2%3%4
Figure 2-25:
8
MDIO Register 0: SGMII Control
www.xilinx.com
70
Chapter 2: Product Specification
Table 2-36:
SGMII Control (Register 0)
Bit(s)
Name
Description
Attributes
Default
Value
0.15
Reset
1 = Core Reset
0 = Normal Operation
read/write
self clearing
0
0.14
Loopback
1 = Enable Loopback Mode
0 = Disable Loopback Mode
When used with a device-specific
transceiver, the core is placed in
internal loopback mode.
With the TBI version, Bit 1 is connected
to ewrap. When set to ‘1’ indicates to
the external PMA module to enter
loopback mode.
See Loopback.
read/write
0
0.13
Speed Selection
(LSB)
Always returns a ‘0’ for this bit.
Together with bit 0.6, speed selection
of 1000 Mb/s is identified
returns 0
0
Auto-Negotiation
Enable
1 = Enable SGMII Auto-Negotiation
Process
0 = Disable SGMII Auto-Negotiation
Process
read/write
1
0.11
Power Down
1 = Power down
0 = Normal operation
With the PMA option, when set to ’1’
the device-specific transceiver is
placed in a low-power state. This bit
requires a reset (see bit 0.15) to clear.
With the TBI version this register bit
has no effect.
read/ write
0
0.10
Isolate
1 = Electrically Isolate SGMII logic from
GMII
0 = Normal operation
read/write
1
0.9
Restart AutoNegotiation
1 = Restart Auto-Negotiation Process
across SGMII link
0 = Normal Operation
read/write
self clearing
0
0.8
Duplex Mode
Always returns a ‘1’ for this bit to signal
Full-Duplex Mode
returns 1
1
0.7
Collision Test
Always returns a ‘0’ for this bit to
disable COL test
returns 0
0
0.6
Speed Selection
(MSB)
Always returns a ‘1’ for this bit.
Together with bit 0.13, speed selection
of 1000 Mb/s is identified
returns 1
1
0.12
1000BASE-X PCS/PMA or SGMII v11.4
PG047 October 16, 2012
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71
Chapter 2: Product Specification
Table 2-36:
SGMII Control (Register 0) (Cont’d)
Name
Description
Attributes
Default
Value
0.5
Unidirectional
Enable
Enable transmit regardless of whether
a valid link has been established. This
feature is only possible if
Auto-Negotiation Enable bit 0.12 is
disabled.
read/ write
0
0.4:0
Reserved
Always return 0s , writes ignored
returns 0s
00000
Bit(s)
Register 1: SGMII Status
X-Ref Target - Figure 2-26
%84%.$%$ 34!453
5.)$)2%#4)/.!, !.),)49
-& 02%!-",% 35002%33)/.
!54/ .%' #/-0,%4%
2%-/4% &!5,4
!54/ .%' !"),)49
,).+ 34!453
*!""%2 $%4%#4
2EG
%84%.$%$ #!0!"),)49
"!3% 4 (!,& $50,%8
"!3% 4 &5,, $50,%8
-BS (!,& $50,%8
-BS &5,, $50,%8
"!3% 8 (!,& $50,%8
"!3% 8 &5,, $50,%8
"!3% 4
8
Figure 2-26:
Table 2-37:
MDIO Register 1: SGMII Status
SGMII Status (Register 1)
Bit(s)
Name
Description
Attributes
Default
Value
1.15
100BASE-T4
Always returns a ‘0’ for this bit because
100BASE-T4 is not supported
returns 0
0
1.14
100BASE-X Full Duplex
Always returns a ‘0’ for this bit because
100BASE-X Full Duplex is not supported
returns 0
0
1.13
100BASE-X Half Duplex
Always returns a ‘0’ for this bit because
100BASE-X Half Duplex is not supported
returns 0
0
1.12
10 Mb/s Full Duplex
Always returns a ‘0’ for this bit because 10
Mb/s Full Duplex is not supported
returns 0
0
1.11
10 Mb/s Half Duplex
Always returns a ‘0’ for this bit because 10
Mb/s Half Duplex is not supported
returns 0
0
1.10
100BASE-T2 Full
Duplex
Always returns a ‘0’ for this bit because
100BASE-T2 Full Duplex is not supported
returns 0
0
1.9
100BASE-T2 Half
Duplex
Always returns a ‘0’ for this bit because
100BASE-T2 Half Duplex is not supported
returns 0
0
1000BASE-X PCS/PMA or SGMII v11.4
PG047 October 16, 2012
www.xilinx.com
72
Chapter 2: Product Specification
Table 2-37:
SGMII Status (Register 1) (Cont’d)
Bit(s)
Name
Description
Attributes
Default
Value
1.8
Extended Status
Always returns a ‘1’ for this bit to indicate the
presence of the Extended Register (Register
15)
returns 1
1
1.7
Unidirectional Ability
Always returns ‘1,’ writes ignored
returns 1
1
1.6
MF Preamble
Suppression
Always returns a ‘1’ for this bit to indicate
that Management Frame Preamble
Suppression is supported
returns 1
1
Auto- Negotiation
Complete
1 = Auto-Negotiation process completed
across SGMII link
0 = Auto-Negotiation process not
completed across SGMII link
read only
0
1.4
Remote Fault
1 = A fault on the Medium has been
detected
0 = No fault of the Medium has been
detected
read only
self clearing
on read
0
1.3
Auto- Negotiation
Ability
Always returns a ‘1’ for this bit to indicate
that the SGMII core is capable of
Auto-Negotiation
returns 1
1
1.2
SGMII Link Status
1 = SGMII Link is up
0 = SGMII Link is down
Latches '0' if SGMII Link Status goes down.
Clears to current SGMII Link Status on read.
See the following Link Status section for
further details.
read only
self clearing
on read
0
1.1
Jabber Detect
Always returns a ‘0’ for this bit because
Jabber Detect is not supported
returns 0
0
1.0
Extended Capability
Always returns a ‘0’ for this bit because no
extended register set is supported
returns 0
0
1.5
Link Status
When high, the link is valid and has remained valid after this register was last read:
synchronization of the link has been obtained and Auto-Negotiation (if enabled) has
completed.
When low, either:
•
A valid link has not been established; link synchronization has failed or
Auto-Negotiation (if enabled) has failed to complete.
OR
1000BASE-X PCS/PMA or SGMII v11.4
PG047 October 16, 2012
www.xilinx.com
73
Chapter 2: Product Specification
•
Link synchronization was lost at some point when the register was previously read.
However, the current link status might be good. Therefore read this register a second
time to get confirmation of the current link status.
Regardless of whether Auto-Negotiation is enabled or disabled, there can be some delay to
the deassertion of Link Status following the loss of synchronization of a previously
successful link. This is due to the Auto-Negotiation state machine which requires that
synchronization is lost for an entire link timer duration before changing state. For more
information, see the 802.3 specification (the an_sync_status variable).
Registers 2 and 3: PHY Identifier
X-Ref Target - Figure 2-27
2EG
/2'!.):%
5.)15% )$
2EG
2%6)3)/. ./
-!5&!#452%2
-/$%, ./
/2'!.):%
5.)15% )$
8
Figure 2-27:
Table 2-38:
MDIO Registers 2 and 3: PHY Identifier
PHY Identifier (Registers 2 and 3)
Bit(s)
Name
Description
Attributes
Default Value
2.15:0
Organizationally Unique
Identifier
Always return 0s
returns 0s
0000000000000000
3.15:10
Organizationally Unique
Identifier
Always return 0s
returns 0s
000000
3.9:4
Manufacturer model number
Always return 0s
returns 0s
000000
3.3:0
Revision Number
Always return 0s
returns 0s
0000
1000BASE-X PCS/PMA or SGMII v11.4
PG047 October 16, 2012
www.xilinx.com
74
Chapter 2: Product Specification
Register 4: SGMII Auto-Negotiation Advertisement
MAC Mode of Operation
X-Ref Target - Figure 2-28
&5,, $50,%8
(!,& $50,%8
2EG
2%3%26%$
0!53%
2%3%26%$
2%-/4% &!5,4
Table 2-39:
2%3%26%$
.%84 0!'%
Figure 2-28:
8
MDIO Register 4: SGMII Auto-Negotiation Advertisement
SGMII Auto-Negotiation Advertisement (Register 4)
Bit(s)
Name
Description
Attributes
Default Value
4.15:0
All bits
SGMII defined value sent from the
MAC to the PHY
read only
0100000000000001
PHY Mode of Operation
X-Ref Target - Figure 2-29
2EG
2%3%26%$
2%3%26%$
30%%$
$50,%8 -/$%
2%3%26%$
Table 2-40:
!#+./7,%$'%
0(9 ,).+ 34!453
Figure 2-29:
8
MDIO Register 4: SGMII Auto-Negotiation Advertisement
SGMII Auto-Negotiation Advertisement in PHY Mode (Register 4)
Name
Description
Attributes
Default
Value
4.15
PHY Link Status
This refers to the link status of the PHY with
its link partner across the Medium.
1 = Link Up
0 = Link Down
read/write
0
4.14
Acknowledge
Used by Auto-Negotiation function to
indicate reception of a link partner’s base or
next page
read/write
0
4.13
Reserved
Always returns ‘0,’ writes ignored
returns 0
0
Bit(s)
1000BASE-X PCS/PMA or SGMII v11.4
PG047 October 16, 2012
www.xilinx.com
75
Chapter 2: Product Specification
Table 2-40:
SGMII Auto-Negotiation Advertisement in PHY Mode (Register 4) (Cont’d)
Bit(s)
Name
Description
Attributes
Default
Value
4.12
Duplex Mode
1= Full Duplex
0 = Half Duplex
read/write
0
4.11:10
Speed
11
10
01
00
4.9:1
Reserved
4:0
Reserved
=
=
=
=
Reserved
1 Gb/s
100 Mb/s
10 Mb/s
read/write
00
Always return 0s
returns 0s
000000000
Always returns ‘1’
returns 1
1
Register 5: SGMII Auto-Negotiation Link Partner Ability
X-Ref Target - Figure 2-30
2EG
2%3%26%$
2%3%26%$
30%%$
$50,%8 -/$%
2%3%26%$
!#+./7,%$'%
0(9 ,).+ 34!453
Figure 2-30:
8
MDIO Register 5: SGMII Auto-Negotiation Link Partner Ability
The Auto-Negotiation Ability Base Register (Register 5) contains information related to the
status of the link between the PHY and its physical link partner across the Medium.
Table 2-41:
SGMII Auto-Negotiation Link Partner Ability Base (Register 5)
Name
Description
Attributes
Default
Value
5.15
PHY Link Status
This refers to the link status of the PHY with
its link partner across the Medium.
1 = Link Up
0 = Link Down
read only
1
5.14
Acknowledge
Used by Auto-Negotiation function to
indicate reception of a link partner’s base or
next page
read only
0
5.13
Reserved
Always returns ‘0,’ writes ignored
returns 0
0
5.12
Duplex Mode
1= Full Duplex
0 = Half Duplex
read only
0
Speed
11
10
01
00
read only
00
Bit(s)
5.11:10
1000BASE-X PCS/PMA or SGMII v11.4
PG047 October 16, 2012
=
=
=
=
Reserved
1 Gb/s
100 Mb/s
10 Mb/s
www.xilinx.com
76
Chapter 2: Product Specification
Table 2-41:
SGMII Auto-Negotiation Link Partner Ability Base (Register 5) (Cont’d)
Bit(s)
Name
Description
Attributes
Default
Value
5.9:1
Reserved
Always return 0s
returns 0s
000000000
5:0
Reserved
Always returns ‘1’
returns 1
1
Register 6: SGMII Auto-Negotiation Expansion
X-Ref Target - Figure 2-31
.%84 0!'% !",%
0!'% 2%#%)6%$
2EG
2%3%26%$
2%3%26%$
8
Figure 2-31:
Table 2-42:
MDIO Register 6: SGMII Auto-Negotiation Expansion
SGMII Auto-Negotiation Expansion (Register 6)
Bit(s)
Name
Description
Attributes
Default Value
6.15:3
Reserved
Always return 0s
returns 0s
0000000000000
6.2
Next Page
Able
This bit is ignored as the core
currently does not support next
page. This feature can be enabled on
request.
returns 1
1
6.1
Page
Received
1 = A new page has been received
0 = A new page has not been
received
read only
self clearing on
read
0
6.0
Reserved
Always return 0s
returns 0s
0000000
1000BASE-X PCS/PMA or SGMII v11.4
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Chapter 2: Product Specification
Register 7: SGMII Auto-Negotiation Next Page Transmit
X-Ref Target - Figure 2-32
2EG
-%33!'% #/$%
4/'',%
!#+./7,%$'%
-%33!'% 0!'%
Table 2-43:
2%3%26%$
.%84 0!'%
Figure 2-32:
8
MDIO Register 7: SGMII Auto-Negotiation Next Page Transmit
SGMII Auto-Negotiation Next Page Transmit (Register 7)
Bit(s)
Name
Description
Attributes
Default Value(1)
7.15
Next Page
1 = Additional Next Page(s) will follow
0 = Last page
read/
write
0
7.14
Reserved
Always returns ‘0’
returns 0
0
7.13
Message Page
1 = Message Page
0 = Unformatted Page
read/
write
1
7.12
Acknowledge 2
1 = Comply with message
0 = Cannot comply with message
read/
write
0
7.11
Toggle
Value toggles between subsequent
Next Pages
read only
0
7.10:0
Message /
Unformatted
Code Field
Message Code Field or Unformatted
Page Encoding as dictated by 7.13
read/
write
00000000001
(Null Message
Code)
Notes:
1. This register returns the default values because the core does not support next page. The feature can be enabled,
if requested.
Register 8: SGMII Next Page Receive
X-Ref Target - Figure 2-33
2EG
-%33!'% #/$%
4/'',%
!#+./7,%$'%
1000BASE-X PCS/PMA or SGMII v11.4
PG047 October 16, 2012
-%33!'% 0!'%
!#+./7,%$'%
.%84 0!'%
Figure 2-33:
8
MDIO Register 8: SGMII Next Page Receive
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Chapter 2: Product Specification
Table 2-44:
SGMII Auto-Negotiation Next Page Receive (Register 8)
Bit(s)
Name
Description
Attributes
Default Value
8.15
Next Page
1 = Additional Next Page(s) will follow
0 = Last page
read only
0
8.14
Acknowledge
Used by Auto-Negotiation function to
indicate reception of a link partner’s
base or next page
read only
0
8.13
Message Page
1 = Message Page
0 = Unformatted Page
read only
0
8.12
Acknowledge 2
1 = Comply with message
0 = Cannot comply with message
read only
0
8.11
Toggle
Value toggles between subsequent
Next Pages
read only
0
8.10:0
Message /
Unformatted Code
Field
Message Code Field or Unformatted
Page Encoding as dictated by 8.13
read only
00000000000
Register 15: SGMII Extended Status
X-Ref Target - Figure 2-34
2EG
2%3%26%$
"!3% 4 (!,& $50,%8
Table 2-45:
"!3% 4 &5,, $50,%8
"!3% 8 (!,& $50,%8
"!3% 8 &5,, $50,%8
Figure 2-34:
8
MDIO Register 15: SGMII Extended Status
SGMII Extended Status Register (Register 15)
Bit(s)
Name
Description
Attributes
Default Value
15.15
1000BASE-X Full
Duplex
Always returns a ‘1’ for this bit because
1000BASE-X Full Duplex is supported
returns 1
1
15.14
1000BASE-X Half
Duplex
Always returns a ‘0’ for this bit because
1000BASE-X Half Duplex is not
supported
returns 0
0
15.13
1000BASE-T Full
Duplex
Always returns a ‘0’ for this bit because
1000BASE-T Full Duplex is not
supported
returns 0
0
1000BASE-X PCS/PMA or SGMII v11.4
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Chapter 2: Product Specification
Table 2-45:
SGMII Extended Status Register (Register 15)
Bit(s)
Name
Description
Attributes
Default Value
15.12
1000BASE-T Half
Duplex
Always returns a ‘0’ for this bit because
1000BASE-T Half Duplex is not
supported
returns 0
0
15:11:0
Reserved
Always return 0s
returns 0s
000000000000
Register 16: SGMII Auto-Negotiation Interrupt Control
X-Ref Target - Figure 2-35
2EG
).4%22504 %.!",%
).4%22504 34!453
2%3%26%$
8
Figure 2-35:
Table 2-46:
MDIO Register 16: SGMII Auto-Negotiation Interrupt Control
SGMII Auto-Negotiation Interrupt Control (Register 16)
Bit(s)
Name
Description
Attributes
Default Value
16.15:2
Reserved
Always return 0s
returns 0s
00000000000000
16.1
Interrupt
Status
1 = Interrupt is asserted
0 = Interrupt is not asserted
If the interrupt is enabled, this bit is
asserted on completion of an
Auto-Negotiation cycle across the
SGMII link; it is only cleared by writing
‘0’ to this bit.
If the Interrupt is disabled, the bit is set
to ‘0.’
The an_interrupt port of the core is
wired to this bit.
read/
write
0
16.0
Interrupt
Enable
1 = Interrupt enabled
0 = Interrupt disabled
read/
write
1
1000BASE-X PCS/PMA or SGMII v11.4
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Chapter 2: Product Specification
SGMII Standard without the Optional Auto-Negotiation
The registers provided for SGMII operation in this core are adaptations of those defined in
clauses 22 and 37 of the IEEE 802.3-2008 specif ication. In an SGMII implementation, two
different types of links exist. They are the SGMII link between the MAC and PHY (SGMII link)
and the link across the Ethernet Medium itself (Medium). See Figure 9-2. Information about
the state of the SGMII link is available in registers that follow.
The state of the link across the Ethernet Medium itself is not directly available when SGMII
Auto-Negotiation is not present. For this reason, the status of the link and the results of the
PHYs Auto-Negotiation (for example, Speed and Duplex mode) must be obtained directly
from the management interface of connected PHY module. Registers at undefined
addresses are read-only and return 0s.
The core can be reset three ways: reset, DCM_LOCKED and soft reset. All of these methods
reset all the registers to the default values.
Table 2-47:
MDIO Registers for SGMII with Auto-Negotiation
Register Address
Register Name
0
SGMII Control Register
1
SGMII Status Register
2,3
PHY Identifier
4
SGMII Auto-Negotiation Advertisement Register
15
SGMII Extended Status Register
Register 0: SGMII Control
X-Ref Target - Figure 2-36
$50,%8 -/$%
#/,,)3)/. 4%34
30%%$
5.)$)2%#4)/.!, %.!",%
2EG
2%3%26%$
2%34!24 !54/ .%'
)3/,!4%
1000BASE-X PCS/PMA or SGMII v11.4
PG047 October 16, 2012
0/7%2 $/7.
!54/ .%' %.!",%
30%%$
,//0"!#+
2%3%4
Figure 2-36:
8
MDIO Register 0: SGMII Control
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Chapter 2: Product Specification
Table 2-48:
SGMII Control (Register 0)
Bit(s)
Name
Description
Attributes
Default
Value
0.15
Reset
1 = Core Reset
0 = Normal Operation
read/write
self clearing
0
0.14
Loopback
1 = Enable Loopback Mode
0 = Disable Loopback Mode
When used with a device-specific
transceiver, the core is placed in
internal loopback mode.
With the TBI version, Bit 1 is connected
to ewrap. When set to ‘1’ indicates to
the external PMA module to enter
loopback mode.
See Loopback.
read/write
0
0.13
Speed Selection
(LSB)
Always returns a ‘0’ for this bit.
Together with bit 0.6, speed selection
of 1000 Mb/s is identified
returns 0
0
Auto-Negotiation
Enable
1 = Enable SGMII Auto-Negotiation
Process
0 = Disable SGMII Auto-Negotiation
Process
read/write
1
0.11
Power Down
1 = Power down
0 = Normal operation
With the PMA option, when set to ’1’
the device-specific transceiver is
placed in a low-power state. This bit
requires a reset (see bit 0.15) to clear.
With the TBI version this register bit
has no effect.
read/ write
0
0.10
Isolate
1 = Electrically Isolate SGMII logic from
GMII
0 = Normal operation
read/write
1
0.9
Restart AutoNegotiation
1 = Restart Auto-Negotiation Process
across SGMII link
0 = Normal Operation
read/write
self clearing
0
0.8
Duplex Mode
Always returns a ‘1’ for this bit to signal
Full-Duplex Mode
returns 1
1
0.7
Collision Test
Always returns a ‘0’ for this bit to
disable COL test
returns 0
0
0.6
Speed Selection
(MSB)
Always returns a ‘1’ for this bit.
Together with bit 0.13, speed selection
of 1000 Mb/s is identified
returns 1
1
0.5
Unidirectional
Enable
Enable transmit regardless of whether
a valid link has been established
read/ write
0
0.4:0
Reserved
Always return 0s , writes ignored
returns 0s
00000
0.12
1000BASE-X PCS/PMA or SGMII v11.4
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Chapter 2: Product Specification
Register 1: SGMII Status
X-Ref Target - Figure 2-37
%84%.$%$ 34!453
5.)$)2%#4)/.!, !.),)49
-& 02%!-",% 35002%33)/.
!54/ .%' #/-0,%4%
2%-/4% &!5,4
!54/ .%' !"),)49
,).+ 34!453
*!""%2 $%4%#4
2EG
%84%.$%$ #!0!"),)49
"!3% 4 (!,& $50,%8
"!3% 4 &5,, $50,%8
-BS (!,& $50,%8
-BS &5,, $50,%8
"!3% 8 (!,& $50,%8
"!3% 8 &5,, $50,%8
"!3% 4
8
Figure 2-37:
Table 2-49:
MDIO Register 1: SGMII Status
SGMII Status (Register 1)
Bit(s)
Name
Description
Attributes
Default
Value
1.15
100BASE-T4
Always returns a ‘0’ for this bit because
100BASE-T4 is not supported
returns 0
0
1.14
100BASE-X Full Duplex
Always returns a ‘0’ for this bit because
100BASE-X Full Duplex is not supported
returns 0
0
1.13
100BASE-X Half Duplex
Always returns a ‘0’ for this bit because
100BASE-X Half Duplex is not supported
returns 0
0
1.12
10 Mb/s Full Duplex
Always returns a ‘0’ for this bit because 10
Mb/s Full Duplex is not supported
returns 0
0
1.11
10 Mb/s Half Duplex
Always returns a ‘0’ for this bit because 10
Mb/s Half Duplex is not supported
returns 0
0
1.10
100BASE-T2 Full
Duplex
Always returns a ‘0’ for this bit because
100BASE-T2 Full Duplex is not supported
returns 0
0
1.9
100BASE-T2 Half
Duplex
Always returns a ‘0’ for this bit because
100BASE-T2 Half Duplex is not supported
returns 0
0
1.8
Extended Status
Always returns a ‘1’ for this bit to indicate the
presence of the Extended Register (Register
15)
returns 1
1
1.7
Unidirectional Ability
Always returns ‘1,’ writes ignored
returns 1
1
1.6
MF Preamble
Suppression
Always returns a ‘1’ for this bit to indicate
that Management Frame Preamble
Suppression is supported
returns 1
1
1.5
Auto-Negotiation
Complete
Ignore this bit because Auto-Negotiation is
not included.
returns 1
0
1000BASE-X PCS/PMA or SGMII v11.4
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Chapter 2: Product Specification
Table 2-49:
SGMII Status (Register 1) (Cont’d)
Bit(s)
Name
Description
Attributes
Default
Value
1.4
Remote Fault
Ignore this bit because Auto-Negotiation is
not included
returns 0
0
1.3
Auto-Negotiation
Ability
Ignore this bit because Auto-Negotiation is
not included
returns 0
0
1.2
SGMII Link Status
1 = SGMII Link is up
0 = SGMII Link is down
Latches '0' if SGMII Link Status goes down.
Clears to current SGMII Link Status on read.
See the following Link Status section for
further details.
read only
self clearing
on read
0
1.1
Jabber Detect
Always returns a ‘0’ for this bit because
Jabber Detect is not supported
returns 0
0
1.0
Extended Capability
Always returns a ‘0’ for this bit because no
extended register set is supported
returns 0
0
Link Status
When high, the link is valid and has remained valid after this register was last read;
synchronization of the link has been obtained.
When low, either:
•
A valid link has not been established; link synchronization has failed.
OR
•
Link synchronization was lost at some point when this register was previously read.
However, the current link status might be good. Therefore read this register a second
time to get confirmation of the current link status.
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Chapter 2: Product Specification
Registers 2 and 3: PHY Identifier
X-Ref Target - Figure 2-38
2EG
/2'!.):%
5.)15% )$
2EG
2%6)3)/. ./
-!5&!#452%2
-/$%, ./
/2'!.):%
5.)15% )$
8
Figure 2-38:
Table 2-50:
MDIO Registers 2 and 3: PHY Identifier
PHY Identifier (Registers 2 and 3)
Bit(s)
Name
Description
Attributes
Default Value
2.15:0
Organizationally Unique
Identifier
Always return 0s
returns 0s
0000000000000000
3.15:10
Organizationally Unique
Identifier
Always return 0s
returns 0s
000000
3.9:4
Manufacturer model number
Always return 0s
returns 0s
000000
3.3:0
Revision Number
Always return 0s
returns 0s
0000
Register 4: SGMII Auto-Negotiation Advertisement
X-Ref Target - Figure 2-39
2EG
,/')#
,/')# gS
8
Figure 2-39:
Table 2-51:
MDIO Register 4: SGMII Auto-Negotiation Advertisement
SGMII Auto-Negotiation Advertisement (Register 4)
Bit(s)
Name
Description
Attributes
Default Value
4.15:0
All bits
Ignore this register because
Auto-Negotiation is not included
read only
0000000000000001
1000BASE-X PCS/PMA or SGMII v11.4
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Chapter 2: Product Specification
Register 15: SGMII Extended Status
X-Ref Target - Figure 2-40
2EG
2%3%26%$
"!3% 4 (!,& $50,%8
Table 2-52:
"!3% 4 &5,, $50,%8
"!3% 8 (!,& $50,%8
"!3% 8 &5,, $50,%8
Figure 2-40:
8
MDIO Register 15: SGMII Extended Status
SGMII Extended Status Register (Register 15)
Bit(s)
Name
Description
Attributes
Default Value
15.15
1000BASE-X Full
Duplex
Always returns a ‘1’ for this bit because
1000BASE-X Full Duplex is supported
returns 1
1
15.14
1000BASE-X Half
Duplex
Always returns a ‘0’ for this bit because
1000BASE-X Half Duplex is not
supported
returns 0
0
15.13
1000BASE-T Full
Duplex
Always returns a ‘0’ for this bit because
1000BASE-T Full Duplex is not
supported
returns 0
0
15.12
1000BASE-T Half
Duplex
Always returns a ‘0’ for this bit because
1000BASE-T Half Duplex is not
supported
returns 0
0
15:11:0
Reserved
Always return 0s
returns 0s
000000000000
Both 1000BASE-X and SGMII Standards
Table 2-53 describes Register 17, the vendor-specific Standard Selection Register. This
register is only present when the core is generated with the capability to dynamically switch
between 1000BASE-X and SGMII standards. The component name is used as the base name
of the output files generated for the core. See Component Name.
When this register is configured to perform the 1000BASE-X standard, registers 0 to 16
should be interpreted as per 1000BASE-X Standard Using the Optional Auto-Negotiation or
1000BASE-X Standard Without the Optional Auto-Negotiation.
When this register is configured to perform the SGMII standard, registers 0 to 16 should be
interpreted as per SGMII Standard Using the Optional Auto-Negotiation or 1000BASE-X
Standard Without the Optional Auto-Negotiation. This register can be written to at any
time. See Chapter 10, Dynamic Switching of 1000BASE-X and SGMII Standards for more
information.
1000BASE-X PCS/PMA or SGMII v11.4
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Chapter 2: Product Specification
Register 17: Vendor-Specific Standard Selection Register
2EG
"!3%8 /2 3'-))
2%3%26%$
8
Figure 2-40:
Table 2-53:
Dynamic Switching (Register 17)
Vendor-specific Register: Standard Selection Register (Register 17)
Bit(s)
Name
Description
Attributes
Default Value
17.15:1
Reserved
Always return 0s
Returns 0s
000000000000000
Standard
0 = Core performs to the 1000BASE-X
standard. Registers 0 to 16 behave as
per 1000BASE-X Standard Using the
Optional Auto-Negotiation
1= Core performs to the SGMII
standard. Registers 0 to 16 behave as
per SGMII Standard Using the
Optional Auto-Negotiation.
read/write
Determined by the
basex_or_sgmii port
16.0
Additional Configuration Vector
Additional signals are brought out of the core to program Register 0 independent of the
MDIO Management Interface. These signals are bundled into the
CONFIGURATION_VECTOR signal as defined in Table 2-54.
1000BASE-X PCS/PMA or SGMII v11.4
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Chapter 2: Product Specification
These signals can be changed by the user application at any time. The Clock Domain
heading denotes the clock domain the configuration signal is registered in before use by
the core. It is not necessary to drive the signal from this clock domain.
Table 2-54:
Optional Configuration and Status Vectors
Signal
configuration_vector[4:0]
Direction
Input
Clock
Domain
Description
See note1
Bit[0]: Unidirectional Enable
When set to 1, Enable Transmit irrespective
of state of RX (802.3ah). When set to 0,
Normal operation
Bit[1]: Loopback Control
• When used with a device-specific
transceiver, the core is placed in internal
loopback mode.
• With the TBI version, Bit 1 is connected to
ewrap. When set to ‘1,’ this indicates to the
external PMA module to enter loopback
mode. See Loopback.
Bit[2]: Power Down
• When a device-specific transceiver is
used, a setting of ‘1’ places the
device-specific transceiver in a low-power
state. A reset must be applied to clear.
• With the TBI version, this bit is unused.
Bit[3]: Isolate
• When set to ‘1,’ the GMII should be
electrically isolated.
• When set to ‘0,’ normal operation is
enabled.
Bit[4] Auto-Negotiation Enable
• This signal is valid only if the AN module
is enabled through the CORE Generator or
Vivado IP catalog tool Graphical User
Interface (GUI).
• When set to 1, the signal enables the AN
feature. When set to 0, AN is disabled.
Notes:
1. Signals are synchronous to the internal 125 MHz reference clock of the core; this is userclk2 when used with a
device-specific transceiver; gtx_clk when used with TBI.
1000BASE-X PCS/PMA or SGMII v11.4
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Chapter 3
Designing with the Core
This chapter includes guidelines and additional information to make designing with the
core easier.
General Design Guidelines
Following are some design guidelines.
Understand the Features and Interfaces Provided by the Core
Netlist
Chapter 1, Overview introduces the features and interfaces that are present in the logic of
the Ethernet 1000BASE-X PCS/PMA or SGMII netlist. This chapter assumes a working
knowledge of the IEEE802.3-2008 Ethernet specification, in particular the Gigabit Ethernet
1000BASE-X sections: clauses 34 through to 37.
Customize and Generate the Core
ISE Design Tools
Generate the core with your desired options using the Xilinx CORE Generator™ tool, as
described in Chapter 17, Customizing and Generating the Core.
Vivado Design Suite
Generate the core with your desired options using Xilinx Vivado™ IP catalog, as described in
Chapter 14, Customizing and Generating the Core.
Examine the Example Design Provided with the Core
An HDL example design built around the core is provided through the CORE Generator tool
and Vivado tools that allow for a demonstration of core functionality using either a
simulation package or in hardware if placed on a suitable board.
1000BASE-X PCS/PMA or SGMII v11.4
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Chapter 3: Designing with the Core
Five different example designs are provided depending upon the core customization
options that have been selected. See the example design description in the appropriate
chapter:
•
Example Design for 1000BASE-X with Transceivers
•
Example Designs for the Ten-Bit Interface (TBI)
•
SGMII Example Design / Dynamic Switching Example Design with Ten-Bit Interface
•
SGMII Example Design / Dynamic Switching Example Design Using a Transceiver
•
SGMII over LVDS
Before implementing the core in your application, examine the example design provided
with the core to identify the steps that can be performed:
1. Edit the HDL top level of the example design file to change the clocking scheme, add or
remove Input/Output Blocks (IOBs) as required, and replace the GMII IOB logic with
user-specific application logic (for example, an Ethernet MAC).
2. Synthesize the entire design.
3. Implement the entire design. After implementation is complete you can also create a
bitstream that can be downloaded to a Xilinx device.
4. Download the bitstream to a target device.
Implement the Ethernet 1000BASE-X PCS/PMA or SGMII Core
in Your Application
Before implementing your application, examine the example design delivered with the core
for information about the following:
•
Instantiating the core from HDL
•
Connecting the physical-side interface of the core (device-specific transceiver or TBI)
•
Deriving the clock management logic
It is expected that the block level module from the example design will be instantiated
directly into customer designs rather than the core netlist itself. The block level contains the
core and a completed physical interface.
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Chapter 3: Designing with the Core
Write an HDL Application
After reviewing the example design delivered with the core, write an HDL application that
uses single or multiple instances of the block level module for the Ethernet 1000BASE-X
PCS/PMA or SGMII core. Client-side interfaces and operation of the core are described in
Chapter 8, Using the Client-Side GMII Datapath. See the following information for
additional details: using the Ethernet 1000BASE-X PCS/PMA or SGMII core in conjunction
with the Tri-Mode Ethernet MAC core in Chapter 12, Interfacing to Other Cores.
Synthesize your Design and Create a Bitstream
Synthesize your entire design using the desired synthesis tool.
IMPORTANT: Care must be taken to constrain the design correctly; the constraints provided with the
core should be used as the basis for your own. See the constraint chapters in either the Vivado Design
Suite or ISE Design Suite sections as appropriate.
Simulate and Download your Design
After creating a bitstream that can be downloaded to a Xilinx device, simulate the entire
design and download it to the desired device.
Know the Degree of Difficulty
An Ethernet 1000BASE-X PCS/PMA or SGMII core is challenging to implement in any
technology and as such, all Ethernet 1000BASE-X PCS/PMA or SGMII core applications
require careful attention to system performance requirements. Pipelining, logic mapping,
placement constraints, and logic duplication are all methods that help boost system
performance.
Keep it Registered
To simplify timing and to increase system performance in an FPGA design, keep all inputs
and outputs registered between the user application and the core. All inputs and outputs
from the user application should come from, or connect to, a flip-flop. While registering
signals might not be possible for all paths, it simplifies timing analysis and makes it easier
for the Xilinx tools to place and route the design.
Recognize Timing Critical Signals
The constraints provided with the example design for the core identifies the critical signals
and the timing constraints that should be applied. See Chapter 15, Constraining the Core
(Vivado tools) and Chapter 18, Constraining the Core (CORE Generator tool) for more
information.
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Chapter 3: Designing with the Core
Use Supported Design Flows
The core is pre-synthesized and is delivered as an NGC netlist. The example implementation
scripts provided currently uses ISE® v14.2 tools as the synthesis tool for the HDL example
design delivered with the core. Other synthesis tools can be used for the user application
logic. The core will always be unknown to the synthesis tool and should appear as a black
box. Post synthesis, only ISE v14.2 tools are supported.
Make Only Allowed Modifications
The Ethernet 1000BASE-X PCS/PMA or SGMII core should not be modified. Modifications
can have adverse effects on system timing and protocol compliance. Supported user
configurations of the Ethernet 1000BASE-X PCS/PMA or SGMII core can only be made by
selecting the options from within the CORE Generator or Vivado IP catalog tool when the
core is generated. See Chapter 17, Customizing and Generating the Core for Core Generator
tool and Chapter 14, Customizing and Generating the Core for Vivado Design Suite.
Clocking
For clocking frequencies for Vivado tools, see Clock Frequencies in Chapter 15 or
Chapter 18, Constraining the Core for CORE Generator tool.
For clocking information on client interface in SGMII mode, see Clock Generation in
Chapter 8.
For clocking information on Phy interface, see the following:
•
For TBI Clocking, see Chapter 4, The Ten-Bit Interface.
•
For 1000 Base-X, see Chapter 5, 1000BASE-X with Transceivers.
•
For SGMII and Dynamic Switching, see Chapter 6, SGMII / Dynamic Standards Switching
with Transceivers.
•
For Asynchronous Oversampling over LVDS for V6 devices see Clocking Logic in SGMII
Support Using Asynchronous Oversampling over Virtex-6 FPGA LVDS in Chapter 7.
•
For System Synchronous SGMII over Virtex7/Kintex 7 LVDS, see Clocking Logic in
Synchronous SGMII over Virtex7/Kintex 7 FPGA LVDS in Chapter 7.
1000BASE-X PCS/PMA or SGMII v11.4
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92
Chapter 3: Designing with the Core
Resets
Due to the number of clock domains in this IP core, the reset structure is not simple and
involves several separate reset regions, with the number of regions being dependent upon
the particular parameterization of the core.
1000BASE-X PCS/PMA or SGMII v11.4
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Chapter 3: Designing with the Core
Reset Structure for Ethernet 1000BASE-X PCS/PMA or SGMII
core with Transceiver
Figure 3-1 shows the most common reset structure for the core connected to the serial or
LVDS Transceiver. The grayed out region of the figure indicates the logic that is activated
under certain conditions based on parameterization of the core.
X-Ref Target - Figure 3-1
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Reset Structure for Ethernet 1000BASE-X PCS/PMA or SGMII Core with Transceiver
1000BASE-X PCS/PMA or SGMII v11.4
PG047 October 16, 2012
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94
Chapter 3: Designing with the Core
Reset Structure for Ethernet 1000BASE-X PCS/PMA or SGMII
core with TBI
Figure 3-2 shows the most common reset structure for the core with TBI. The grayed out
region of the figure indicates the logic that is activated under certain conditions based on
parameterization of the core.
X-Ref Target - Figure 3-2
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Figure 3-2:
Reset Structure for Ethernet 1000BASE-X PCS/PMA or SGMII core with TBI
1000BASE-X PCS/PMA or SGMII v11.4
PG047 October 16, 2012
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95
Chapter 4
The Ten-Bit Interface
This chapter provides general guidelines for creating 1000BASE-X, SGMII or Dynamic
Standards Switching designs using the Ten-Bit Interface (TBI).
This chapter is organized into the following main sections:
•
Ten-Bit-Interface Logic
This section provides an explanation of the TBI physical interface logic in all supported
device families. This section is common to both 1000BASE-X and SGMII
implementations.
•
Clock Sharing across Multiple Cores with TBI
Providing guidance for using several core instantiations; clock sharing should occur
whenever possible to save device resources.
•
Example Designs for the Ten-Bit Interface (TBI)
Providing an introduction to the CORE Generator™ and Vivado™ IP catalog tools
example design deliverables, this section is split into the following two sub-sections:
°
Example Design for 1000BASE-X with Ten-Bit Interface
°
SGMII Example Design / Dynamic Switching Example Design with Ten-Bit Interface
This section also provides an overview of the demonstration test bench that is provided
with the example designs.
Virtex®-6 devices support TBI at 2.5 V only. See the Virtex-6 FPGA Data Sheet: DC and
Switching Characteristics for more information. Kintex™-7, Virtex-5, Virtex-4, Spartan®-6,
and Spartan-3 devices support TBI at 3.3 V or lower.
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Chapter 4: The Ten-Bit Interface
Ten-Bit-Interface Logic
The example design delivered with the core is split between two hierarchical layers, as
illustrated in both Figure 4-14 and Figure 4-16. The block level is designed so that it can be
instantiated directly into customer designs and provides the following functionality:
•
Instantiates the core from HDL
•
Connects the physical-side interface of the core to device IOBs, creating an external TBI
The TBI logic implemented in the block level is illustrated in all the figures in this chapter.
Transmitter Logic
Figure 4-1 illustrates the use of the physical transmitter interface of the core to create an
external TBI in a Virtex-5 device. The signal names and logic shown exactly match those
delivered with the example design when TBI is chosen. If other families are chosen,
equivalent primitives and logic specific to that family are automatically used in the example
design.
Figure 4-1 shows that the output transmitter datapath signals are registered in device IOBs
before driving them to the device pads. The logic required to forward the transmitter clock
is also shown. The logic uses an IOB output Double-Data-Rate (DDR) register so that the
clock signal produced incurs exactly the same delay as the data and control signals. This
clock signal, pma_tx_clk, is inverted with respect to gtx_clk so that the rising edge of
pma_tx_clk occurs in the center of the data valid window to maximize setup and hold
times across the interface.
1000BASE-X PCS/PMA or SGMII v11.4
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Chapter 4: The Ten-Bit Interface
X-Ref Target - Figure 4-1
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Figure 4-1:
1000BASE-X PCS/PMA or SGMII v11.4
PG047 October 16, 2012
Ten-Bit Interface Transmitter Logic
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98
Chapter 4: The Ten-Bit Interface
Receiver Logic
X-Ref Target - Figure 4-2
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Figure 4-2:
Input TBI timing
Figure 4-2 illustrates the input timing for the TBI interface as defined in IEEE802.3-2008
clause 36 (see also TBI Input Setup/Hold Timing for further information).
The important point is that the input TBI data bus, rx_code_group[9:0], is synchronous
to two clock sources: pma_rx_clk0 and pma_rx_clk1. As defined by the standard, the
TBI data should be sampled alternatively on the rising edge of pma_rx_clk0, then
pma_rx_clk1. Minimum setup and hold constraints are specified and apply to both clock
sources.
In the IEEE802.3-2008 specification, there is no exact requirement that pma_rx_clk0 and
pma_rx_clk1 be exactly 180 degrees out of phase with each other, so the safest approach
is to use both pma_rx_clk0 and pma_rx_clk1 clocks as the specification intends. This is
at the expense of clocking resources.
However, the data sheet for a particular external SERDES device that connects to the TBI
might well specify that this is the case; that pma_rx_clk0 and pma_rx_clk1 are exactly
180 degrees out of phase. If this is the case, the TBI receiver clock logic can be simplified by
ignoring the pma_rx_clk1 clock altogether, and simply using both the rising and falling
edges of pma_rx_clk0.
For this reason, the following sections describe two different alternatives methods for
implementing the TBI receiver clock logic: one which uses both pma_rx_clk0 and
pma_rx_clk1 clock, and a second which only uses pma_rx_clk0 (but both rising and
falling edges). Select the method carefully by referring to the data sheet of the external
SERDES.
The example designs provided with the core only provides one of these methods (which
vary on a family-by-family basis). However, the example HDL design can easily be edited to
convert to the alternative method.
1000BASE-X PCS/PMA or SGMII v11.4
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Chapter 4: The Ten-Bit Interface
Spartan-3, Spartan-3E and Spartan-3A Devices
Method 1: Using Both pma_rx_clk0 and pma_rx_clk1 (Provided by the Example Design)
X-Ref Target - Figure 4-3
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Figure 4-3:
TBI Receiver Logic for Spartan-3, Spartan-3E, and Spartan-3A Devices (Example Design)
This is the implementation provided by the example design for the Spartan-3 families. This
uses the pma_rx_clk0 and pma_rx_clk1 clocks as intended by the TBI specification.
Contrast this with Method 2 which can save on clock resources if the external SERDES
devices guarantee that they provide pma_rx_clk0 and pma_rx_clk1 exactly 180
degrees out of phase with each other.
In this implementation, a DCM is used on both the pma_rx_clk0 and pma_rx_clk1 clock
paths (see Figure 4-3). Phase shifting should then be applied to the DCM to fine-tune the
setup and hold times at the TBI IOB input flip-flops. Fixed phase shift is applied to the DCM
using constraints in the example UCF for the example design. See Ten-Bit Interface
Constraints for more information.
1000BASE-X PCS/PMA or SGMII v11.4
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100
Chapter 4: The Ten-Bit Interface
Method 2: An Alternative Using Only pma_rx_clk0
X-Ref Target - Figure 4-4
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Figure 4-4:
TBI Receiver Logic for Spartan-3, Spartan-3E, and Spartan-3A Devices
In this implementation, the falling edge of pma_rx_clk0 is used instead of pma_rx_clk1
(see Figure 4-4).
The DCM is used on the pma_rx_clk0 clock path. Phase shifting should then be applied to
the DCM to fine-tune the setup and hold times at the rx_code_group[9:0] IOB input
flip-flops.
The clock derived from the DCM should be inverted, as illustrated, before routing it to the
pma_rx_clk1 input of the core. This does not create a clock on local routing. Instead the
tools then use local clock inversion directly at the clock input of the flip-flops that this clock
is routed to.
1000BASE-X PCS/PMA or SGMII v11.4
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101
Chapter 4: The Ten-Bit Interface
CAUTION! This logic relies on pma_rx_clk0 and pma_rx_clk1 being exactly 180 degrees out of phase
with each other because the falling edge of pma_rx_clk0 is used in place of pma_rx_clk1. See the data
sheet for the attached SERDES to verify that this is the case.
Virtex-4 Devices
Method 1: Using Only pma_rx_clk0 (Provided by the Example Design)
X-Ref Target - Figure 4-5
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Figure 4-5:
Ten-Bit Interface Receiver Logic - Virtex-4 Device (Example Design)
The Virtex-4 FPGA logic used by the example design delivered with the core is illustrated in
Figure 4-5. This shows a Virtex-4 device IDDR primitive used with the DDR_CLK_EDGE
attribute set to SAME_EDGE (see the Virtex-4 FPGA User Guide). This uses local inversion of
pma_rx_clk0 within the IOB logic to receive the rx_code_group[9:0] data bus on
both the rising and falling edges of pma_rx_clk0. The SAME_EDGE attribute causes the
IDDR to output both Q1 and Q2 data on the rising edge of pma_rx_clk0.
1000BASE-X PCS/PMA or SGMII v11.4
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Chapter 4: The Ten-Bit Interface
For thisto
routed
pma_rx_clk1
illustrated.
reason,
both pma_rx_clk0
pma_rx_clk0
clock inputs of the
and
cancore
be as
CAUTION! This logic relies on pma_rx_clk0 and pma_rx_clk1 being exactly 180 degrees out of phase
with each other because the falling edge of pma_rx_clk0 is used in place of pma_rx_clk1. See the data
sheet for the attached SERDES to verify that this is the case.
The DCM is used on the pma_rx_clk0 clock path. Phase shifting should then be applied to
the DCM to fine-tune the setup and hold times at the rx_code_group[9:0] IOB input
flip-flops. Fixed phase shift is applied to the DCM using constraints in the example UCF for
the example design. See Ten-Bit Interface Constraints for more information.
Method 2: An Alternative Using Both pma_rx_clk0 and pma_rx_clk1
X-Ref Target - Figure 4-6
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Figure 4-6:
Alternate Ten-Bit Interface Receiver Logic for Virtex-4 Devices
1000BASE-X PCS/PMA or SGMII v11.4
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Chapter 4: The Ten-Bit Interface
This logic from Method 1 relies on pma_rx_clk0 and pma_rx_clk1 being exactly 180
degrees out of phase with each other because the falling edge of pma_rx_clk0 is used in
place of pma_rx_clk1. See the data sheet for the attached SERDES to verify that this is the
case. If not, then the logic of Figure 4-6 illustrates an alternative implementation where
both pma_rx_clk0 and pma_rx_clk1 are used as intended. Each bit of
rx_code_group[9:0] must be routed to two separate device pads.
In this implementation, a DCM is used on both the pma_rx_clk0 and pma_rx_clk1 clock
paths (see Figure 4-6). Phase shifting should then be applied to the DCMs to fine-tune the
setup and hold times at the TBI IOB input flip-flops.
Virtex-5 Devices
Method 1: Using Only pma_rx_clk0 (Provided by the Example Design)
X-Ref Target - Figure 4-7
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Ten-Bit Interface Receiver Logic - Virtex-5 Device (Example Design)
1000BASE-X PCS/PMA or SGMII v11.4
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Chapter 4: The Ten-Bit Interface
The Virtex-5 FPGA logic used by the example design delivered with the core is illustrated in
Figure 4-7. This shows a Virtex-5 device IDDR primitive used with the DDR_CLK_EDGE
attribute set to SAME_EDGE (see the Virtex-5 FPGA User Guide). This uses local inversion of
pma_rx_clk0 within the IOB logic to receive the rx_code_group[9:0] data bus on
both the rising and falling edges of pma_rx_clk0. The SAME_EDGE attribute causes the
IDDR to output both Q1 and Q2 data on the rising edge of pma_rx_clk0.
For this reason, pma_rx_clk0 can be routed to both pma_rx_clk0 and pma_rx_clk1
clock inputs of the core as illustrated.
CAUTION! This logic relies on pma_rx_clk0 and pma_rx_clk1 being exactly 180 degrees out of phase
with each other because the falling edge of pma_rx_clk0 is used in place of pma_rx_clk1. See the data
sheet for the attached SERDES to verify that this is the case.
Setup and Hold is achieved using a combination of IODELAY elements on the data, and
using BUFIO and BUFR regional clock routing for the pma_rx_clk0 input clock, as
illustrated in Figure 4-7.
This design provides a simpler solution than the DCM logic required for Virtex-4 devices
(see Figure 4-5). It has therefore been chosen as the example design from version 10.1 of
the core onwards. However, the Virtex-4 FPGA approach could alternatively be adopted.
In the Figure 4-7 implementation, a BUFIO is used to provide the lowest form of clock
routing delay from input clock to input rx_code_group[9:0] signal sampling at the
device IOBs. However, this creates placement constraints; a BUFIO capable clock input pin
must be selected for pma_rx_clk0, and all rx_code_group[9:0] input signals must be
placed in the respective BUFIO region. Consult the Virtex-5 FPGA User Guide.
The clock is then placed onto regional clock routing using the BUFR component and the
input rx_code_group[9:0] data immediately resampled as illustrated.
The IODELAY elements can be adjusted to fine-tune the setup and hold times at the TBI IOB
input flip-flops. The delay is applied to the IODELAY element using constraints in the UCF;
these can be edited if desired. See Ten-Bit Interface Constraints for more information.
1000BASE-X PCS/PMA or SGMII v11.4
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Chapter 4: The Ten-Bit Interface
Method 2: An Alternative Using Both pma_rx_clk0 and pma_rx_clk1
X-Ref Target - Figure 4-8
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Figure 4-8:
Alternate Ten-Bit Interface Receiver Logic - Virtex-5 Devices
The logic from Method 1 relies on pma_rx_clk0 and pma_rx_clk1 being exactly 180
degrees out of phase with each other because the falling edge of pma_rx_clk0 is used in
place of pma_rx_clk1. See the data sheet for the attached SERDES to verify that this is the
case. If not, the logic of Figure 4-8 illustrates an alternate implementation where both
pma_rx_clk0 and pma_rx_clk1 are used as intended.
In this method, the logic used on pma_rx_clk0 in Figure 4-7 is duplicated for
pma_rx_clk1. A IDDR_CLK2 primitive replaces the IDDR primitive; this contains two clock
inputs as illustrated.
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Chapter 4: The Ten-Bit Interface
Kintex-7 and Virtex-6 Devices
Method 1: Using Only pma_rx_clk0 (Provided by the Example Design)
X-Ref Target - Figure 4-9
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Figure 4-9:
Ten-Bit Interface Receiver Logic - Kintex-7 and Virtex-6 Devices (Example Design)
The FPGA logic used by the example design delivered with the core is illustrated in
Figure 4-7. This shows an IDDR primitive used with the DDR_CLK_EDGE attribute set to
SAME_EDGE. This uses local inversion of pma_rx_clk0 within the IOB logic to receive the
rx_code_group[9:0] data bus on both the rising and falling edges of pma_rx_clk0.
The SAME_EDGE attribute causes the IDDR to output both Q1 and Q2 data on the rising
edge of pma_rx_clk0.
For this reason, pma_rx_clk0 can be routed to both pma_rx_clk0 and pma_rx_clk1
clock inputs of the core as illustrated.
1000BASE-X PCS/PMA or SGMII v11.4
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Chapter 4: The Ten-Bit Interface
CAUTION! This logic relies on pma_rx_clk0 and pma_rx_clk1 being exactly 180 degrees out of phase
with each other because the falling edge of pma_rx_clk0 is used in place of pma_rx_clk1. See the data
sheet for the attached SERDES to verify that this is the case.
Setup and Hold is achieved using a combination of IODELAY elements on the data and
using BUFIO and BUFR regional clock routing for the pma_rx_clk0 input clock, as
illustrated in Figure 4-9.
This design provides a simpler solution than the DCM logic required for Virtex-4 devices. It
has therefore been chosen as the example design for the Kintex-7 and Virtex-6 family.
However, the Virtex-4 FPGA approach could alternatively be adopted; simply replace the
DCM with a Mixed-Mode Clock Manager (MMCM) module (see Figure 4-5).
In the Figure 4-9 implementation, a BUFIO is used to provide the lowest form of clock
routing delay from input clock to input rx_code_group[9:0] signal sampling at the
device IOBs. However, this creates placement constraints; a BUFIO capable clock input pin
must be selected for pma_rx_clk0, and all rx_code_group[9:0] input signals must be
placed in the respective BUFIO region. Consult the FPGA user guides.
The clock is then placed onto regional clock routing using the BUFR component and the
input rx_code_group[9:0] data immediately resampled as illustrated.
The IODELAY elements can be adjusted to fine-tune the setup and hold times at the TBI IOB
input flip-flops. The delay is applied to the IODELAY element using constraints in the UCF;
these can be edited if desired. See Ten-Bit Interface Constraints for more information.
1000BASE-X PCS/PMA or SGMII v11.4
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Chapter 4: The Ten-Bit Interface
Method 2: An Alternative Using Both pma_rx_clk0 and pma_rx_clk1
X-Ref Target - Figure 4-10
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Figure 4-10:
Alternate Ten-Bit Interface Receiver Logic - Kintex-7 and Virtex-6 Devices
This logic from Method 1 relies on pma_rx_clk0 and pma_rx_clk1 being exactly 180
degrees out of phase with each other because the falling edge of pma_rx_clk0 is used in
place of pma_rx_clk1. See the data sheet for the attached SERDES to verify that this is the
case. If not, the logic of Figure 4-10 illustrates an alternate implementation where both
pma_rx_clk0 and pma_rx_clk1 are used as intended. Each bit of
rx_code_group[9:0] must be routed to two separate device pads.
In this method, the logic used on pma_rx_clk0 in Figure 4-9 is duplicated for
pma_rx_clk1. A IDDR_CLK2 primitive replaces the IDDR primitive; this contains two clock
inputs as illustrated.
1000BASE-X PCS/PMA or SGMII v11.4
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Chapter 4: The Ten-Bit Interface
Spartan-6 Devices
Method 1: Using Only pma_rx_clk0 (Provided by the Example Design)
X-Ref Target - Figure 4-11
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Figure 4-11:
Ten-Bit Interface Receiver Logic - Spartan-6 Device (Example Design)
The Spartan-6 FPGA logic used by the example design delivered with the core is illustrated
in Figure 4-11. This figure shows a Spartan-6 device IDDR2 primitive used with the
DDR_ALIGNMENT attribute set to C0 (see the Spartan-6 FPGA User Guide). This
DDR_ALIGNMENT attribute causes the IDDR2 to output both Q1 and Q2 data on the rising
edge of pma_rx_clk0.
For this reason, pma_rx_clk0 can be routed to both pma_rx_clk0 and pma_rx_clk1
clock inputs of the core as illustrated.
1000BASE-X PCS/PMA or SGMII v11.4
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Chapter 4: The Ten-Bit Interface
CAUTION! This logic relies on pma_rx_clk0 and pma_rx_clk1 being exactly 180 degrees out of phase
with each other because the falling edge of pma_rx_clk0 is used in place of pma_rx_clk1. See the data
sheet for the attached SerDes to verify that this is the case.
Setup and Hold is achieved using a combination of IODELAY2 elements on the data and
using BUFIO2 elements and BUFG global clock routing for the pma_rx_clk0 input clock, as
illustrated in Figure 4-11.
This design provides a simpler solution than the DCM logic required for Virtex-4 devices. It
has therefore been chosen as the example design for the Spartan-6 family. However, the
Virtex-4 FPGA approach could alternatively be adopted; simply replace the DCM with a
MMCM module (see Figure 4-5).
In the Figure 4-11 implementation, two BUFIO2s are used to provide the lowest form of
clock routing delay from input clock to input rx_code_group[9:0] signal sampling at
the device IOBs. One BUFIO2 element is used for the rising edge logic; no clock inversion is
performed and the DIVCLK output connects to the BUFG to provide global clock routing;
the IOCLK output of this BUFIO2 is routed to the IDDR2 primitive to sample data on the
rising edge. The second BUFIO2 element is configured to invert the clock; the IOCLK output
is routed to the IDDR2 to effectively sample the data on the falling edge position of
pma_rx_clk0. The DIVCLK output of this BUFIO2 is not used and is left unconnected.
The IODELAY2 elements can be adjusted to fine-tune the setup and hold times at the TBI
IOB input flip-flops. The delay is applied to the IODELAY element using constraints in the
UCF; these can be edited if desired. See Ten-Bit Interface Constraints for more information.
However, this logic creates placement constraints; rx_code_group[9:0] input signals
must be placed in the respective half-bank region for the two BUFIO2 elements in use.
Consult the Spartan-6 FPGA User Guide.
1000BASE-X PCS/PMA or SGMII v11.4
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Chapter 4: The Ten-Bit Interface
Method 2: An Alternative Using Both pma_rx_clk0 and pma_rx_clk1
X-Ref Target - Figure 4-12
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Figure 4-12:
Alternate Ten-Bit Interface Receiver Logic - Spartan-6 Devices
This logic from Method 1 relies on pma_rx_clk0 and pma_rx_clk1 being exactly 180
degrees out of phase with each other because the falling edge of pma_rx_clk0 is used in
place of pma_rx_clk1. See the data sheet for the attached SERDES to verify that this is the
case. If not, the logic of Figure 4-12 illustrates an alternate implementation where both
pma_rx_clk0 and pma_rx_clk1 are used as intended. Each bit of
rx_code_group[9:0] must be routed to two separate device pads.
In this method, the logic used on pma_rx_clk0 in Figure 4-11 is duplicated for
pma_rx_clk1.
In the figure, a simplified view of the BUFIO2 elements are provided. The connected output
of each BUFIO is the IOCLK port. Other BUFIO2 output ports are unused and unconnected.
1000BASE-X PCS/PMA or SGMII v11.4
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Chapter 4: The Ten-Bit Interface
Clock Sharing across Multiple Cores with TBI
X-Ref Target - Figure 4-13
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Figure 4-13:
Clock Management, Multiple Core Instances with Ten-Bit Interface
Figure 4-13 illustrates sharing clock resources across multiple instantiations of the core
when using the TBI. For all implementations, gtx_clk can be shared between multiple
cores, resulting in a common clock domain across the device.
The receiver clocks pma_rx_clk0 and pma_rx_clk1 (if used) cannot be shared. Each core
is provided with its own versions of these receiver clocks from its externally connected
SERDES.
Figure 4-13 illustrates only two cores. However, more can be added using the same
principle. This is done by instantiating the cores using the block level (from the example
design) and sharing gtx_clk across all instantiations. The receiver clock logic cannot be
shared and must be unique for every instance of the core.
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Chapter 4: The Ten-Bit Interface
Example Designs for the Ten-Bit Interface (TBI)
Chapter 20, Detailed Example Design provides a full list and description of the directory and
file structure that is provided with the core, including the location of the HDL example
design provided.
Example Design for 1000BASE-X with Ten-Bit Interface
Figure 4-14 illustrates the example design for a top-level HDL with a 10-bit interface (TBI).
X-Ref Target - Figure 4-14
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Figure 4-14:
Example Design HDL for the Ethernet 1000BASE-X PCS with TBI
As illustrated, the example is split between two hierarchical layers. The block level is
designed so that it can be instantiated directly into customer designs and performs the
following functions:
•
Instantiates the core from HDL
•
Connects the physical-side interface of the core to device IOBs, creating an external
TBI.
1000BASE-X PCS/PMA or SGMII v11.4
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Chapter 4: The Ten-Bit Interface
The top level of the example design creates a specific example that can be simulated,
synthesized, implemented, and if required, placed on a suitable board and demonstrated in
hardware. The top level of the example design performs the following functions:
•
Instantiates the block level from HDL
•
Derives the clock management logic for the core
•
Implements an external GMII
The next few pages in this section describe each of the example design blocks (and
associated HDL files) in detail, and conclude with an overview of the demonstration test
bench provided for the design.
Top-Level Example Design HDL
The following files describe the top-level example design for the Ethernet 1000BASE-X
PCS/PMA core with TBI:
VHDL
ISE® Design Suite:
//example_design/_example_design.vhd
Vivado™ Design Suite:
//.srcs/sources1/ip///example_design/_example_design.vhd
Verilog
ISE Design Suite:
//example_design/_example_design.v
Vivado Design Suite:
//.srcs/sources1/ip//
|/example_design/_example_design.v
The HDL example design top-level contains the following:
•
An instance of the Ethernet 1000BASE-X PCS/PMA block level
•
Clock management logic, including DCM and Global Clock Buffer instances, where
required
•
A transmitter elastic buffer
•
GMII interface logic, including IOB and DDR registers instances, where required
1000BASE-X PCS/PMA or SGMII v11.4
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Chapter 4: The Ten-Bit Interface
The example design HDL top level connects the GMII of the block level to external IOBs. This
allows the functionality of the core to be demonstrated using a simulation package as
described in this guide. The example design can also be synthesized and placed on a
suitable board and demonstrated in hardware, if required.
Block Level HDL
The following files describe the block level design for the Ethernet 1000BASE-X PCS/PMA
core with TBI:
VHDL
ISE Design Suite:
//example_design/_block.vhd
Vivado Design Suite:
//.srcs/sources1/ip//
/example_design/_block.vhd
Verilog
ISE Design Suite:
//example_design/_block.v
Vivado Design Suite:
//.srcs/sources1/ip//
/example_design/_block.v
The block level HDL contains the following:
•
An instance of the Ethernet 1000BASE-X PCS/PMA core
•
TBI interface logic, including IOB and DDR registers instances, where required
The block-level HDL connects the TBI of the core to external IOBs (the most useful part of
the example design) and should be instantiated in all customer designs that use the core.
1000BASE-X PCS/PMA or SGMII v11.4
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Chapter 4: The Ten-Bit Interface
Transmitter Elastic Buffer
The Transmitter Elastic Buffer is described in the following files:
VHDL
ISE Design Suite:
//example_design/
_tx_elastic_buffer.vhd
Vivado Design Suite:
//.srcs/sources1/ip//
/example_design/_tx_elastic_buffer.vhd
Verilog
ISE Design Suite:
//example_design/_tx_elastic_buffer.v
Vivado Design Suite:
//.srcs/sources1/ip//
/example_design/_tx_elastic_buffer.v
When the GMII is used externally (as in this example design), the GMII transmit signals
(inputs to the core from a remote Ethernet MAC at the other end of the interface) are
synchronous to a clock, which is likely to be derived from a different clock source to the
core. For this reason, GMII transmit signals must be transferred into the core main clock
domain before they can be used by the core. This is achieved with the Transmitter Elastic
Buffer, an asynchronous FIFO implemented in distributed RAM. The operation of the elastic
buffer is to attempt to maintain a constant occupancy by inserting or removing Idle
sequences as necessary. This causes no corruption to the frames of data.
When the GMII is used as an internal interface, it is expected that the entire interface will be
synchronous to a single clock domain, and the Transmitter Elastic Buffer should be
discarded.
1000BASE-X PCS/PMA or SGMII v11.4
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Chapter 4: The Ten-Bit Interface
Demonstration Test Bench
Figure 4-15 illustrates the demonstration test bench for the Ethernet 1000BASE-X PCS with
TBI. The demonstration test bench is a simple VHDL or Verilog program to exercise the
example design and the core itself.
X-Ref Target - Figure 4-15
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Figure 4-15:
Demonstration Test Bench for the Ethernet
1000BASE-X PCS with TBI
The top-level test bench entity instantiates the example design for the core, which is the
Device Under Test (DUT). A stimulus block is also instantiated and clocks, resets and test
bench semaphores are created. The following files describe the top-level of the
demonstration test bench:
VHDL
ISE Design Suite:
//simulation/demo_tb.vhd
Vivado Design Suite:
//.srcs/sources1/ip//
/simulation/demo_tb.vhd
1000BASE-X PCS/PMA or SGMII v11.4
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Chapter 4: The Ten-Bit Interface
Verilog
ISE Design Suite:
//simulation/demo_tb.v
Vivado Design Suite:
//.srcs/sources1/ip//
/simulation/demo_tb.v
The stimulus block entity, instantiated from within the test bench top level, creates the
Ethernet stimulus in the form of four Ethernet frames, which are injected into the GMII and
PHY interfaces of the DUT. The output from the DUT is also monitored for errors. The
following files describe the stimulus block of the demonstration test bench:
VHDL
ISE Design Suite:
//simulation/stimulus_tb.vhd
Vivado Design Suite:
//.srcs/sources1/ip//
/simulation/stimulus_tb.vhd
Verilog
ISE Design Suite:
//simulation/stimulus_tb.v
Vivado Design Suite:
//.srcs/sources1/ip//
/simulation/stimulus_tb.v
Together, the top-level test bench file and the stimulus block combine to provide the full
test bench functionality, described in the sections that follow.
Core with MDIO Interface
The demonstration test bench performs the following tasks:
•
Input clock signals are generated.
•
A reset is applied to the example design.
•
The Ethernet 1000BASE-X PCS/PMA core is configured through the MDIO interface by
injecting an MDIO frame into the example design. This disables Auto-Negotiation (if
present) and takes the core out of the Isolate state.
1000BASE-X PCS/PMA or SGMII v11.4
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Chapter 4: The Ten-Bit Interface
•
The following frames are injected into the GMII transmitter by the GMII stimulus block:
°
the first is a minimum-length frame
°
the second is a type frame
°
the third is an errored frame
°
the fourth is a padded frame
•
The data received at the TBI transmitter interface is 8B/10B decoded. The resulting
frames are checked by the TBI Monitor against the stimulus frames injected into the
GMII transmitter to ensure data integrity.
•
The same four frames are generated by the TBI Stimulus block. These are 8B/10B
encoded and injected into the TBI receiver interface.
•
Data frames received at the GMII receiver are checked by the GMII Monitor against the
stimulus frames injected into the TBI receiver to ensure data integrity.
Core without MDIO Interface
The demonstration test bench performs the following tasks.
•
Input clock signals are generated.
•
A reset is applied to the example design.
•
The Ethernet 1000BASE-X PCS/PMA core is configured through the Configuration
Vector to take the core out of the Isolate state.
•
The following frames are injected into the GMII transmitter by the GMII stimulus block.
°
the first is a minimum length frame
°
the second is a type frame
°
the third is an errored frame
°
the fourth is a padded frame
•
The data received at the TBI transmitter interface is 8B/10B decoded. The resultant
frames are checked by the TBI Monitor against the stimulus frames injected into the
GMII transmitter to ensure data is the same.
•
The same four frames are generated by the TBI Stimulus block. These are 8B/10B
encoded and injected into the TBI receiver interface.
•
Data frames received at the GMII receiver are checked by the GMII Monitor against the
stimulus frames injected into the TBI receiver to ensure data is the same.
Customizing the Test Bench
This section provides information about making modifications to the demonstration test
bench files.
1000BASE-X PCS/PMA or SGMII v11.4
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Chapter 4: The Ten-Bit Interface
Changing Frame Data
You can change the contents of the four frames used by the demonstration test bench by
changing the data and valid fields for each frame defined in the stimulus block. Frames can
be added by defining a new frame of data. Any modified frames are automatically updated
in both stimulus and monitor functions.
Changing Frame Error Status
Errors can be inserted into any of the predefined frames in any position by setting the error
field to ‘1’ in any column of that frame. Injected errors are automatically updated in both
stimulus and monitor functions.
Changing the Core Configuration
The configuration of the Ethernet 1000BASE-X PCS/PMA core used in the demonstration
test bench can be altered.
CAUTION! Certain configurations of the core can cause the test bench to fail or cause processes to run
indefinitely. For example, the demonstration test bench does not auto-negotiate with the design
example. Determine the configurations that can safely be used with the test bench.
If the MDIO interface option has been selected, the core can be reconfigured by editing the
injected MDIO frame in the demonstration test bench top level. Management Registers 0
and 4 can additionally be written though configuration_vector[4:0] and
an_adv_config_vector[15:0] interface signals respectively
If the MDIO interface option has not been selected, the core can be reconfigured by
modifying the configuration vector directly.
1000BASE-X PCS/PMA or SGMII v11.4
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Chapter 4: The Ten-Bit Interface
SGMII Example Design / Dynamic Switching Example Design
with Ten-Bit Interface
Figure 4-16 illustrates an example design for top-level HDL for the Ethernet 1000BASE-X
PCS/PMA or SGMII core in SGMII mode (or dynamic switching standard) with the TBI.
X-Ref Target - Figure 4-16
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Figure 4-16:
Example Design HDL for the Ethernet 1000BASE-X PCS/PMA or
SGMII Core in SGMII Mode with TBI
As illustrated, the example is split between two hierarchical layers. The block level is
designed so that it can be instantiated directly into customer designs and performs the
following functions:
•
Instantiates the core from HDL
•
Connects the physical-side interface of the core to device IOBs, creating an external
TBI.
•
Connects the client side GMII of the core to an SGMII Adaptation Module, which
provides the functionality to operate at speeds of 1 Gb/s, 100 Mb/s and 10 Mb/s.
The top level of the example design creates a specific example which can be simulated,
synthesized and implemented. The top level of the example design performs the following
functions:
1000BASE-X PCS/PMA or SGMII v11.4
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Chapter 4: The Ten-Bit Interface
•
Instantiates the block level from HDL
•
Derives the clock management logic for the core
•
Implements an external GMII-style interface
The next few pages in this section describe each of the example design blocks (and
associated HDL files) in detail, and conclude with an overview of the demonstration test
bench provided for the design.
Top-Level Example Design HDL
The top-level example design for the Ethernet 1000BASE-X PCS/PMA core in SGMII mode is
described in the following files:
VHDL
ISE Design Suite:
//example_design/_example_design.vhd
Vivado Design Suite:
//.srcs/sources1/ip//
/example_design/_example_design.vhd
Verilog
ISE Design Suite:
//example_design/_example_design.v
Vivado Design Suite
//.srcs/sources1/ip//
/example_design/_example_design.v
The example design HDL top level contains the following:
•
An instance of the SGMII block level
•
Clock management logic, including DCM and Global Clock Buffer instances, where
required
•
External GMII logic, including IOB and DDR register instances, where required
The example design HDL top level connects the GMII of the block level to external IOBs. This
allows the functionality of the core to be demonstrated using a simulation package, as
described in this guide.
1000BASE-X PCS/PMA or SGMII v11.4
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Chapter 4: The Ten-Bit Interface
Block Level HDL
The following files describe the block level for the Ethernet 1000BASE-X PCS/PMA core in
SGMII mode:
VHDL
ISE Design Suite:
//example_design/_block.vhd
Vivado Design Suite:
//.srcs/sources1/ip//
/example_design/_block.vhd
Verilog
ISE Design Suite:
//example_design/_block.v
Vivado Design Suite:
//.srcs/sources1/ip//
/example_design/_block.v
The block level contains the following:
•
An instance of the Ethernet 1000BASE-X PCS/PMA core in SGMII mode.
•
TBI interface logic, including IOB and DDR registers instances, where required.
•
An SGMII adaptation module containing:
°
°
The clock management logic required to enable the SGMII example design to
operate at 10 Mb/s, 100 Mb/s, and 1 Gb/s.
GMII logic for both transmitter and receiver paths; the GMII style 8-bit interface is
run at 125 MHz for 1 Gb/s operation; 12.5 MHz for 100 Mb/s operation; 1.25 MHz
for 10 Mb/s operation.
The block level HDL connects the TBI of the core to external IOBs and the client side to
SGMII Adaptation logic as illustrated in Figure 4-16. This is the most useful part of the
example design and should be instantiated in all customer designs that use the core.
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Chapter 4: The Ten-Bit Interface
SGMII Adaptation Module
The SGMII Adaptation Module is described in the following files:
VHDL
ISE Design Suite:
//example_design/sgmii_adapt/
Vivado Design Suite:
//.srcs/sources1/ip//
/example_design/sgmii_adapt/
_sgmii_adapt.vhd
_clk_gen.vhd
_johnson_cntr.vhd
_tx_rate_adapt.vhd
_rx_rate_adapt.vhd
Verilog
ISE Design Suite:
//example_design/sgmii_adapt/
Vivado Design Suite:
//.srcs/sources1/ip//
/example_design/sgmii_adapt/
_sgmii_adapt.v
_clk_gen.v
_johnson_cntr.v
_tx_rate_adapt.v
_rx_rate_adapt.v
The GMII of the core always operates at 125 MHz. The core makes no differentiation
between the three speeds of operation; it always effectively operates at 1 Gb/s. However, at
100 Mb/s, every data byte run through the core should be repeated 10 times to achieve the
required bit rate; at 10 Mb/s, each data byte run through the core should be repeated 100
times to achieve the required bit rate. Dealing with this repetition of bytes is the function of
the SGMII adaptation module and its component blocks.
The SGMII adaptation module and component blocks are described in detail in Chapter 8,
Additional Client-Side SGMII Logic Provided in the Example Design.
1000BASE-X PCS/PMA or SGMII v11.4
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Chapter 4: The Ten-Bit Interface
Demonstration Test Bench
Figure 4-17 illustrates the demonstration test bench for the Ethernet 1000BASE-X PCS/PMA
or SGMII Core in SGMII mode with the TBI. The demonstration test bench is a simple VHDL
or Verilog program to exercise the example design and the core itself.
X-Ref Target - Figure 4-17
$EMONSTRATION 4EST "ENCH
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Figure 4-17:
Demonstration Test Bench for the Ethernet 1000BASE-X PCS/PMA
or SGMII Core in SGMII Mode with TBI
The top-level test bench entity instantiates the example design for the core, which is the
Device Under Test (DUT). A stimulus block is also instantiated and clocks, resets and test
bench semaphores are created. The following files describe the top-level of the
demonstration test bench.
VHDL
ISE Design Suite:
//simulation/demo_tb.vhd
Vivado Design Suite:
//.srcs/sources1/ip//
/simulation/demo_tb.vhd
1000BASE-X PCS/PMA or SGMII v11.4
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Chapter 4: The Ten-Bit Interface
Verilog
ISE Design Suite:
//simulation/demo_tb.v
Vivado Design Suite:
//.srcs/sources1/ip//
/simulation/demo_tb.v
The stimulus block entity, instantiated from within the top-level test bench, creates the
Ethernet stimulus in the form of four Ethernet frames, which are injected into GMII and TBI
interfaces of the DUT. The output from the DUT is also monitored for errors. The following
files describe the stimulus block of the demonstration test bench.
VHDL
ISE Design Suite:
//simulation/stimulus_tb.vhd
Vivado Design Suite:
//.srcs/sources1/ip//
/simulation/stimulus_tb.vhd
Verilog
ISE Design Suite:
//simulation/stimulus_tb.v
Vivado Design Suite:
//.srcs/sources1/ip//
/simulation/stimulus_tb.v
Together, the top-level test bench file and the stimulus block combine to provide the full
test bench functionality which is described in the sections that follow.
Test Bench Functionality
The demonstration test bench performs the following tasks:
•
Input clock signals are generated.
•
A reset is applied to the example design.
•
The Ethernet 1000BASE-X PCS/PMA core is configured through the MDIO interface by
injecting an MDIO frame into the example design. This disables Auto-Negotiation and
takes the core out of Isolate state.
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Chapter 4: The Ten-Bit Interface
•
The following frames are injected into the GMII transmitter by the GMII stimulus block
at 1 Gb/s.
°
the first is a minimum length frame
°
the second is a type frame
°
the third is an errored frame
°
the fourth is a padded frame
•
The data received at the TBI transmitter interface is 8B/10B decoded. The resulting
frames are checked by the TBI Monitor against the stimulus frames injected into the
GMII transmitter to ensure data integrity.
•
The same four frames are generated by the TBI Stimulus block. These are 8B/10B
encoded and injected into the TBI receiver interface.
•
Data frames received at the GMII receiver are checked by the GMII Monitor against the
stimulus frames injected into the device-specific transceiver receiver to ensure data
integrity.
Customizing the Test Bench
Changing Frame Data
You can change the contents of the four frames used by the demonstration test bench by
changing the data and valid fields for each frame defined in the stimulus block. New frames
can be added by defining a new frame of data. Modified frames are automatically updated
in both stimulus and monitor functions.
Changing Frame Error Status
Errors can be inserted into any of the predefined frames in any position by setting the error
field to ‘1’ in any column of that frame. Injected errors are automatically updated in both
stimulus and monitor functions.
Changing the Core Configuration
The configuration of the Ethernet 1000BASE-X PCS/PMA core used in the demonstration
test bench can be altered.
CAUTION! Certain configurations of the core cause the test bench to fail or cause processes to run
indefinitely. For example, the demonstration test bench does not auto-negotiate with the design
example. Determine the configurations that can safely be used with the test bench.
The core can be reconfigured by editing the injected MDIO frame in the demonstration test
bench top level.
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Chapter 4: The Ten-Bit Interface
Changing the Operational Speed
SGMII can be used to carry Ethernet traffic at 10 Mb/s, 100 Mb/s or 1 Gb/s. By default, the
demonstration test bench is configured to operate at 1 Gb/s. The speed of both the
example design and test bench can be set to the desired operational speed by editing the
following settings, recompiling the test bench, then running the simulation again.
1 Gb/s Operation
set speed_is_10_100 to logic 0
100 Mb/s Operation
set speed_is_10_100 to logic 1
set speed_is_100 to logic 1
10 Mb/s Operation
set speed_is_10_100 to logic 1
set speed_is_100 to logic 0
1000BASE-X PCS/PMA or SGMII v11.4
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Chapter 5
1000BASE-X with Transceivers
This chapter provides general guidelines for creating 1000BASE-X designs that use
transceivers for Virtex®-4, Virtex-5, Virtex-6, Virtex-7, Kintex™-7, Artix ™-7, Zynq™-7000,
and Spartan®-6 devices. ISE® Design Suite supports Virtex-4, Virtex-5, Virtex-6, Virtex-7,
Kintex-7, Artix-7, Zynq-7000, and Spartan-6 devices. Vivado™ Design Suite supports only
Virtex-7, Kintex-7 and Artix-7 devices.
This chapter is organized into the following main sections, with each section being
organized into FPGA families:
•
Transceiver Logic
Provides a more detailed look that the device-specific transceivers and their
connections to the netlist of the core.
•
Clock Sharing Across Multiple Cores with Transceivers
Provides guidance for using several cores and transceiver instantiations; clock sharing
should occur whenever possible to save device resources.
•
Example Design for 1000BASE-X with Transceivers
Introduces the CORE Generator™ tool example design deliverables.
Introduces the Vivado IP catalog tool example design deliverables.
This section also has an overview of the demonstration test bench that is provided with
the example design.
1000BASE-X PCS/PMA or SGMII v11.4
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Chapter 5: 1000BASE-X with Transceivers
Transceiver Logic
The example is split between two discrete hierarchical layers, as illustrated in Figure 5-18.
The block level is designed so that it can be instantiated directly into customer designs and
provides the following functionality:
•
Instantiates the core from HDL
•
Connects the physical-side interface of the core to a Virtex-4, Virtex-5, Virtex-6,
Virtex-7, Kintex-7, Artix-7, Zynq-7000, or Spartan-6 device transceiver
The logic implemented in the block level is illustrated in all the figures and described in
further detail for the remainder of this chapter.
Virtex-4 FX Devices
The core is designed to integrate with the Virtex-4 FPGA RocketIO™ MGT transceiver.
Figure 5-1 illustrates the connections and logic required between the core and MGT—the
signal names and logic in the figure precisely match those delivered with the example
design when an MGT is used.
Note: A small logic shim (included in the block-level wrapper) is required to convert between the
port differences of the Virtex-5 and Virtex-4 FPGA RocketIO transceivers.
The MGT clock distribution in Virtex-4 devices is column-based and consists of multiple
MGT tiles (each tile contains two MGTs). For this reason, the MGT wrapper delivered with
the core always contains two MGT instantiations, even if only a single MGT transceiver is in
use. Figure 5-1 illustrates a single MGT tile for clarity.
A GT11CLK_MGT primitive is also instantiated to derive the reference clocks required by the
MGT column-based tiles. See the UG076 Virtex-4 RocketIO Multi-Gigabit Transceiver User
Guide for information about layout and clock distribution.
The 250 MHz reference clock from the GT11CLK_MGT primitive is routed to the MGT
transceiver, configured to internally synthesize a 125 MHz clock. This is output on the
TXOUTCLK1 port of the MGT and after being placed onto global clock routing, can be used
by all core logic. This clock is input back into the MGT transceiver on the user interface clock
ports rxusrclk2 and txusrclk2. With the attribute settings applied to the MGT
transceiver from the example design, the txusrclk and rxusrclk ports are derived
internally within the MGT transceiver using the internal clock dividers and do not need to be
provided from the FPGA logic.
1000BASE-X PCS/PMA or SGMII v11.4
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Chapter 5: 1000BASE-X with Transceivers
The Virtex-4 FX FPGA RocketIO MGT transceivers require the inclusion of a calibration block
in the logic; the example design provided with the core instantiates calibration blocks as
required. Calibration blocks require a clock source of between 25 to 50 MHz that is shared
with the Dynamic Reconfiguration Port (DRP) of the MGT transceiver, which is named dclk
in the example design. See Xilinx Answer Record 22477 for more information.
Figure 5-1 also illustrates the TX_SIGNAL_DETECT and RX_SIGNAL_DETECT ports of the
calibration block, which should be driven to indicate whether or not dynamic data is being
transmitted and received through the MGT transceiver (see Virtex-4 Errata). However,
RX_SIGNAL_DETECT is connected to the signal_detect port of the example design.
signal_detect is intended to be connected to the optical transceiver to indicate the
presence of light. When light is detected, the optical transceiver provides dynamic data to
the Rx ports of the MGT transceiver. When no light is detected, the calibration block
switches the MGT into loopback to force dynamic data through the MGT transceiver
receiver path. Vivado IP Packager does not support Virtex-4 devices. Virtex-4 devices are
supported only through ISE design suite.
CAUTION! signal_detect is an optional port in the IEEE 802.3-2008 specification. If this is not used, the
RX_SIGNAL_DETECT port of the calibration block must be driven by an alternative method. See
XAPP732 for more information.
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Chapter 5: 1000BASE-X with Transceivers
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1000BASE-X PCS/PMA or SGMII v11.4
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Chapter 5: 1000BASE-X with Transceivers
Virtex-5 LXT and SXT Devices
The core is designed to integrate with the Virtex-5 FPGA RocketIO GTP transceiver.
Figure 5-2 illustrates the connections and logic required between the core and the GTP
transceiver— the signal names and logic in the figure precisely match those delivered with
the example design when a GTP transceiver is used.
A GTP transceiver tile consists of a pair of transceivers. For this reason, the GTP transceiver
wrapper delivered with the core always contains two GTP instantiations, even if only a single
GTP transceiver tile is in use. Figure 5-2 illustrates a single GTP transceiver tile.
The 125 MHz differential reference clock is routed directly to the GTP transceiver. The GTP
transceiver is configured to output a version of this clock on the REFCLKOUT port and after
placement onto global clock routing, can be used by all core logic. This clock is input back
into the GTP transceiver on the user interface clock ports rxusrclk, rxusrclk2,
txusrclk, and txusrclk2. Vivado IP Packager does not support Virtex-5 devices.
Virtex-5 devices are supported only through ISE design suite.
See also Virtex-5 FPGA RocketIO GTP Transceivers for 1000BASE-X Constraints.
Virtex-5 FPGA RocketIO GTX Wizard
The two wrapper files immediately around the GTP transceiver pair,
RocketIO_wrapper_gtp_tile and RocketIO_wrapper_gtp (see Figure 5-2), are
generated from the RocketIO GTP Wizard. These files apply all the gigabit Ethernet
attributes. Consequently, these files can be regenerated by customers and therefore be
easily targeted at ES or Production silicon. This core targets production silicon.
The CORE Generator tool log file (XCO file) which was created when the RocketIO GTP
Wizard project was generated is available in the following location:
//example_design/transceiver/
_RocketIO_wrapper_gtp.xco
This file can be used as an input to the CORE Generator tool to regenerate the
device-specific RocketIO transceiver wrapper files. The XCO file itself contains a list of all of
the GTP transceiver wizard attributes that were used. For further information, see the
Virtex-5 FPGA RocketIO GTP Wizard Getting Started Guide (UG188) and the CORE Generator
Guide, at www.xilinx.com/support/software_manuals.htm
1000BASE-X PCS/PMA or SGMII v11.4
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Chapter 5: 1000BASE-X with Transceivers
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1000BASE-X PCS/PMA or SGMII v11.4
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Chapter 5: 1000BASE-X with Transceivers
Virtex-5 FXT and TXT Devices
The core is designed to integrate with the Virtex-5 FPGA RocketIO GTX transceiver.
Figure 5-3 illustrates the connections and logic required between the core and the GTX
transceiver—the signal names and logic in the figure precisely match those delivered with
the example design when a GTX transceiver is used.
A GTX transceiver tile consists of a pair of transceivers. For this reason, the GTX transceiver
wrapper delivered with the core always contains two GTX transceiver instantiations, even if
only a single GTX transceiver tile is in use. Figure 5-3 illustrates a single GTX transceiver tile.
The 125 MHz differential reference clock is routed directly to the GTX transceiver. The GTX
transceiver is configured to output a version of this clock on the REFCLKOUT port; this is
then routed to a DCM through a BUFG (global clock routing).
From the DCM, the CLK0 port (125 MHz) is placed onto global clock routing and can be
used as the 125 MHz clock source for all core logic; this clock is also input back into the GTX
transceiver on the user interface clock ports rxusrclk2 and txusrclk2.
From the DCM, the CLKDV port (62.5 MHz) is placed onto global clock routing and is input
back into the GTX transceiver on the user interface clock ports rxusrclk and txusrclk.
Vivado IP Packager does not support Virtex-5 devices. Virtex-5 devices are supported only
through the ISE design suite.
See also Virtex-5 FPGA RocketIO GTX Transceivers for 1000BASE-X Constraints.
Virtex-5 FPGA RocketIO GTX Wizard
The two wrapper files immediately around the GTX transceiver pair,
RocketIO_wrapper_gtx_tile and RocketIO_wrapper_gtx (see Figure 5-3), are
generated from the RocketIO GTX Wizard. These files apply all the gigabit Ethernet
attributes. Consequently, these files can be regenerated by customers and therefore be
easily targeted at ES or Production silicon. This core targets production silicon.
The CORE Generator tool log file (XCO file) that was created when the RocketIO GTX Wizard
project was generated is available in the following location:
//example_design/transceiver/
_RocketIO_wrapper_gtx.xco
This file can be used as an input to the CORE Generator tool to regenerate the
device-specific RocketIO transceiver wrapper files. The XCO file itself contains a list of all of
the GTX transceiver wizard attributes that were used. For further information, see the
Virtex-5 FPGA RocketIO GTX Wizard Getting Started Guide and the CORE Generator Guide, at
www.xilinx.com/support/software_manuals.htm
1000BASE-X PCS/PMA or SGMII v11.4
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Chapter 5: 1000BASE-X with Transceivers
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Chapter 5: 1000BASE-X with Transceivers
Virtex-6 Devices
The core is designed to integrate with the Virtex-6 FPGA GTX transceiver. Figure 5-4
illustrates the connections and logic required between the core and the GTX
transceiver—the signal names and logic in the figure precisely match those delivered with
the example design.
The 125 MHz differential reference clock is routed directly to the GTX transceiver from the
specialized IBUFDS_GTXE1 primitive. The GTX transceiver is configured to output a version
of this clock on the TXOUTCLK port and after placement onto global clock routing, can be
used by all core logic. This clock is input back into the GTX transceiver on the user interface
clock ports rxusrclk2 and txusrclk2. The rxusrclk and txusrclk clocks are derived
internally and can be grounded. Vivado IP Packager does not support Virtex-6 devices.
Virtex-6 devices are supported only through ISE design suite.
Virtex-6 FPGA GTX Transceiver Wizard
The two wrapper files immediately around the GTX transceiver, gtx_wrapper_gtx and
gtx_wrapper (see Figure 5-4), are generated from the Virtex-6 FPGA GTX Transceiver
Wizard. These files apply all the gigabit Ethernet attributes. Consequently, these files can
be regenerated by customers and therefore be easily targeted at silicon/device versions.
The CORE Generator tool log file (XCO file) that was created when the Virtex-6 FPGA GTX
Transceiver Wizard project was generated is available in the following location:
//example_design/transceiver/
_gtx_wrapper_gtx.xco
This file can be used as an input to the CORE Generator tool to regenerate the transceiver
wrapper files. The XCO file itself contains a list of all of the wizard attributes that were used.
For further information, see the Virtex-6 FPGA GTX Transceiver Wizard Getting Started Guide
and the CORE Generator Guide, at www.xilinx.com/support/software_manuals.htm.
1000BASE-X PCS/PMA or SGMII v11.4
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Chapter 5: 1000BASE-X with Transceivers
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1000BASE-X PCS/PMA or SGMII v11.4
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Chapter 5: 1000BASE-X with Transceivers
Spartan-6 LXT Devices
The core is designed to integrate with the Spartan-6 FPGA GTP transceiver. Figure 5-5
illustrates the connections and logic required between the core and the GTP
transceiver—the signal names and logic in the figure precisely match those delivered with
the example design when a GTP transceiver is used.
A GTP transceiver tile consists of a pair of transceivers. For this reason, the GTP transceiver
wrapper delivered with the core always contains two GTP transceiver instantiations, even if
only a single GTP transceiver tile is in use. Figure 5-5 illustrates a single GTP transceiver tile.
The 125 MHz differential reference clock is routed directly to the GTP transceiver. The GTP
transceiver is configured to output a version of this clock on the GTPCLKOUT port and after
placement through a BUFIO2 and BUFG onto global clock routing, can be used by all core
logic. This clock is input back into the GTP transceiver on the user interface clock ports
rxusrclk, rxusrclk2, txusrclk, and txusrclk2.
Vivado IP Packager does not support Spartan-6 devices. Spartan-6 devices are supported
only through ISE design suite. See also Spartan-6 FPGA GTP Transceivers for 1000BASE-X
Constraints.
Spartan-6 FPGA GTP Transceiver Wizard
The two wrapper files immediately around the GTP transceiver pair, gtp_wrapper_tile
and gtp_wrapper (see Figure 5-5), are generated from the Spartan-6 FPGA GTP
Transceiver Wizard. These files apply all the gigabit Ethernet attributes. Consequently, these
files can be regenerated by customers and therefore be easily targeted at ES or Production
silicon. This core targets production silicon.
The CORE Generator tool log file (XCO file) that was created when the GTP Transceiver
Wizard project was generated is available in the following location:
//example_design/transceiver/gtp_wrapper.xco
This file can be used as an input to the CORE Generator tool to regenerate the
device-specific transceiver wrapper files. The XCO file itself contains a list of all of the GTP
transceiver wizard attributes that were used. For further information, see the Spartan-6
FPGA GTP Wizard Getting Started Guide and the CORE Generator Guide, at
www.xilinx.com/support/software_manuals.htm
1000BASE-X PCS/PMA or SGMII v11.4
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Chapter 5: 1000BASE-X with Transceivers
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1000BASE-X PCS/PMA or SGMII v11.4
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Chapter 5: 1000BASE-X with Transceivers
Virtex-7 Devices
The core is designed to integrate with the 7 series FPGA transceiver. Figure 5-6 illustrates
the connections and logic required between the core and the transceiver—the signal names
and logic in the figure precisely match those delivered with the example design when a 7
series FPGA transceiver is used.
The 125 MHz differential reference clock is routed directly to the 7 series FPGA transceiver.
The transceiver is configured to output a version of this clock (62.5 MHz) on the TXOUTCLK
port; this is then routed to a MMCM. From the MMCM, the CLKOUT1 port (62.5 MHz) is
placed onto global clock routing and is input back into the GTXE2/GTHE2 transceiver on the
user interface clock ports rxusrclk, rxusrclk2, txusrclk, and txusrclk2. The CLKOUT0 port (125
MHz) of MMCM is placed onto global clock routing and can be used as the 125 MHz clock
source for all core logic. See also Chapter 18, 7 Series and Zynq-7000 Device Transceivers
for 1000BASE-X Constraints.
7 Series FPGA Transceiver Wizard
The two wrapper files immediately around the GTX/GTH transceiver pair, gtwizard and
gtwizard_gt (Figure 5-6), are generated from the 7 series FPGA Transceiver Wizard. These
files apply all the gigabit Ethernet attributes. Consequently, these files can be regenerated
by customers. The CORE Generator tool log file (XCO file) that was created when the 7 series
FPGA Transceiver Wizard project was generated is available in the following location:
ISE Design Suite
//example_design/transceiver/_gtwizard
.xco
Vivado Design Suite
//.srcs/sources1/ip//
/example_design/transceiver/_gtwizard.xco.
This file can be used as an input to the CORE Generator tool to regenerate the device
specific transceiver wrapper files. This file can be used as an input to Vivado project by
clicking in the Flow Navigator task bar and selecting the XCO file. The XCO
file itself contains a list of all of the Transceiver Wizard attributes that were used. For further
information, see the 7 Series FPGAs GTX Transceivers User Guide and 7 Series FPGAs GTH
Transceivers User Guide.
1000BASE-X PCS/PMA or SGMII v11.4
PG047 October 16, 2012
www.xilinx.com
142
Chapter 5: 1000BASE-X with Transceivers
X-Ref Target - Figure 5-6
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Figure 5-6:
1000BASE-X Connection to Virtex-7 Transceivers
1000BASE-X PCS/PMA or SGMII v11.4
PG047 October 16, 2012
www.xilinx.com
143
Chapter 5: 1000BASE-X with Transceivers
Kintex-7 and Zynq-7000 Devices
The core is designed to integrate with the 7 series FPGA transceiver. Figure 5-7 illustrates
the connections and logic required between the core and the transceiver—the signal names
and logic in the figure precisely match those delivered with the example design when a 7
series FPGA transceiver is used.
The 125 MHz differential reference clock is routed directly to the 7 series FPGA transceiver.
The transceiver is configured to output a version of this clock (62.5 MHz) on the TXOUTCLK
port; this is then routed to a MMCM through a BUFG (global clock routing). From the
MMCM, the CLKOUT1 port (62.5 MHz) is placed onto global clock routing and is input back
into the GTXE2 transceiver on the user interface clock ports rxusrclk, rxusrclk2,
txusrclk and txusrclk2. The CLKOUT0 port (125 MHz) of MMCM is placed onto global
clock routing and can be used as the 125 MHz clock source for all core logic. See also 7
Series FPGA Transceivers for 1000BASE-X Constraints.
7 Series FPGA Transceiver Wizard
The two wrapper files immediately around the GTX transceiver pair, gtwizard and
gtwizard_gt (Figure 5-7), are generated from the 7 series FPGA Transceiver Wizard. These
files apply all the gigabit Ethernet attributes. Consequently, these files can be regenerated
by customers.
The CORE Generator tool log file (XCO file) that was created when the 7 series FPGA
Transceiver Wizard project was generated is available in the location:
ISE Design Suite
//example_design/transceiver/_gtwizard
.xco
Vivado Design Suite
//.srcs/sources1/ip//
/example_design/transceiver/_gtwizard.xco
This file can be used as an input to the CORE Generator tool to regenerate the device
specific transceiver wrapper files. This file can be used as an input to Vivado project by
clicking on in the Flow Navigator task bar and selecting the XCO file. The
XCO file itself contains a list of all of the transceiver wizard attributes that were used. For
further information, see the 7 Series FPGAs GTX Transceivers User Guide.
1000BASE-X PCS/PMA or SGMII v11.4
PG047 October 16, 2012
www.xilinx.com
144
Chapter 5: 1000BASE-X with Transceivers
X-Ref Target - Figure 5-7
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Figure 5-7:
1000BASE-X Connection to Kintex-7 and Zynq-7000 Device Transceivers
1000BASE-X PCS/PMA or SGMII v11.4
PG047 October 16, 2012
www.xilinx.com
145
Chapter 5: 1000BASE-X with Transceivers
Artix-7 Devices
The core is designed to integrate with the 7 series FPGA transceiver. Figure 5-8 illustrates
the connections and logic required between the core and the transceiver-the signal names
and logic in the figure precisely match those delivered with the example design when a
7 series FPGA transceiver is used.
The 125 MHz differential reference clock is routed directly to the 7 series FPGA transceiver.
The transceiver is configured to output a version of this clock (62.5 MHz) on the TXOUTCLK
port. The clock is then routed to a MMCM through a BUFG (global clock routing). From the
MMCM, the CLKOUT1 port (62.5 MHz) is placed onto global clock routing and is input back
into the GTPE2 transceiver on the user interface clock ports rxusrclk, rxusrclk2,
txusrclk and txusrclk2. The CLKOUT0 port (125 MHz) of MMCM is placed onto global
clock routing and can be used as the 125 MHz clock source for all core logic. See also 7
Series and Zynq-7000 Device Transceivers for 1000BASE-X Constraints in Chapter 18.
7 Series FPGA Transceiver Wizard
The two wrapper files immediately around the GTP transceiver pair, gtwizard and
gtwizard_gt (Figure 5-8), are generated from the 7 series FPGA Transceiver Wizard. These
files apply all the gigabit Ethernet attributes. Consequently, these files can be regenerated
by customers.
The CORE Generator tool log file (XCO file) that was created when the 7 series FPGA
Transceiver Wizard project was generated is available in the location:
ISE Design Suite
//example_design/transceiver/_gtwizard
.xco
Vivado Design Suite
//.srcs/sources1/ip//
/example_design/transceiver/_gtwizard.xco
This file can be used as an input to the CORE Generator tool to regenerate the device
specific transceiver wrapper files. This file can be used as an input to Vivado project by
clicking on in the Flow Navigator task bar and selecting the XCO file.The
XCO file itself contains a list of all of the transceiver wizard attributes that were used. For
further information, see the 7 Series FPGAs GTP Transceivers User Guide.
1000BASE-X PCS/PMA or SGMII v11.4
PG047 October 16, 2012
www.xilinx.com
146
Chapter 5: 1000BASE-X with Transceivers
X-Ref Target - Figure 5-8
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Figure 5-8:
1000BASE-X PCS/PMA or SGMII v11.4
PG047 October 16, 2012
1000BASE-X Connection to Artix-7 Transceiver
www.xilinx.com
147
Chapter 5: 1000BASE-X with Transceivers
Clock Sharing Across Multiple Cores with
Transceivers
Virtex-4 FX Devices
Figure 5-9 illustrates sharing clock resources across multiple instantiations of the core when
using MGTs. The example design, when using the Virtex-4 family, can be generated to
connect either a single instance of the core, or connect a pair of core instances to the
transceiver pair present in an MGT tile. Figure 5-9 shows two instantiations of the block
level, where each block contains a pair of cores, subsequently illustrating clock sharing
between four cores in total.
More cores can be added by continuing to instantiate extra block-level modules. Share
clocks only between the MGTs in a single column. For each column, use a single
brefclk_p and brefclk_n differential clock pair and connect this to a GT11CLK_MGT
primitive. The clock output from this primitive should be shared across all used RocketIO
transceiver tiles in the column. See the Virtex-4 RocketIO Multi-Gigabit Transceiver User
Guide (UG076) for more information.
To provide the 125 MHz clock for all core instances, select a TXOUTCLK1 port from any MGT.
This can be routed onto global clock routing using a BUFG as illustrated, and shared
between all cores and MGTs in the column. Although not illustrated in Figure 5-9, dclk (the
clock used for the calibration blocks and for the Dynamic Reconfiguration Port (DRP) of the
MGT transceivers) can also be shared.
1000BASE-X PCS/PMA or SGMII v11.4
PG047 October 16, 2012
www.xilinx.com
148
Chapter 5: 1000BASE-X with Transceivers
X-Ref Target - Figure 5-9
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Figure 5-9:
Clock Management - Multiple Core Instances, MGT Transceivers for 1000BASE-X
1000BASE-X PCS/PMA or SGMII v11.4
PG047 October 16, 2012
www.xilinx.com
149
Chapter 5: 1000BASE-X with Transceivers
Virtex-5 LXT and SXT Devices
Figure 5-10 illustrates sharing clock resources across multiple instantiations of the core
when using Virtex-5 FPGA RocketIO GTP transceivers.
The example design can be generated to connect either a single instance of the core or
connect a pair of core instances to the transceiver pair present in a GTP transceiver tile.
Figure 5-10 illustrates two instantiations of the block level, and each block level contains a
pair of cores, consequently illustrating clock sharing between a total of four cores.
Additional cores can be added by continuing to instantiate extra block level modules. Share
the brefclk_p and brefclk_n differential clock pair. See the Virtex-5 FPGA RocketIO GTP
Transceiver User Guide (UG196) for more information.
To provide the 125 MHz clock for all core instances, select a REFCLKOUT port from any GTP
transceiver. This can be routed onto global clock routing using a BUFG as illustrated and
shared between all cores and GTP transceivers.
1000BASE-X PCS/PMA or SGMII v11.4
PG047 October 16, 2012
www.xilinx.com
150
Chapter 5: 1000BASE-X with Transceivers
X-Ref Target - Figure 5-10
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Figure 5-10:
Clock Management - Multiple Core Instances, Virtex-5 FPGA
RocketIO GTP Transceivers for 1000BASE-X
X-Ref Target - Figure 5-11
1000BASE-X PCS/PMA or SGMII v11.4
PG047 October 16, 2012
www.xilinx.com
151
Chapter 5: 1000BASE-X with Transceivers
Virtex-5 FXT and TXT Devices
Figure 5-12 illustrates sharing clock resources across multiple instantiations of the core
when using Virtex-5 FPGA RocketIO GTX transceivers.
The example design can be generated to connect either a single instance of the core or
connect a pair of core instances to the transceiver pair present in a GTX transceiver tile.
Figure 5-12 illustrates two instantiations of the block level, and each block level contains a
pair of cores, consequently illustrating clock sharing between a total of four cores.
Additional cores can be added by continuing to instantiate extra block level modules. Share
the brefclk_p and brefclk_n differential clock pair. See the Virtex-5 FPGA RocketIO GTX
Transceiver User Guide for more information.
To provide the FPGA logic clocks for all core instances, select a REFCLKOUT port from any
GTX transceiver and route this to a single DCM through a BUFG (global clock routing). The
CLK0 (125 MHz) and CLKDV (62.5 MHz) outputs from this DCM, placed onto global clock
routing using BUFGs, can be shared across all core instances and GTX transceivers as
illustrated.
1000BASE-X PCS/PMA or SGMII v11.4
PG047 October 16, 2012
www.xilinx.com
152
Chapter 5: 1000BASE-X with Transceivers
X-Ref Target - Figure 5-12
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Figure 5-12:
Clock Management - Multiple Core Instances, Virtex-5 FPGA RocketIO GTX
Transceivers for 1000BASE-X
1000BASE-X PCS/PMA or SGMII v11.4
PG047 October 16, 2012
www.xilinx.com
153
Chapter 5: 1000BASE-X with Transceivers
Virtex-6 Devices
Figure 5-13 illustrates sharing clock resources across two instantiations of the core when
using Virtex-6 FPGA GTX transceivers. Additional cores can be added by continuing to
instantiate extra block level modules.
Share the mgtrefclk_p and mgtrefclk_n differential clock pair clock source across all of
the transceivers in use. To provide the 125 MHz clock for all core instances, select a
TXOUTCLK port from any GTX transceiver. This can be routed onto global clock routing
using a BUFG as illustrated and shared between all cores and GTX transceivers.
See the Virtex-6 GTX Transceiver User Guide for more information on GTX transceiver clock
resources.
1000BASE-X PCS/PMA or SGMII v11.4
PG047 October 16, 2012
www.xilinx.com
154
Chapter 5: 1000BASE-X with Transceivers
X-Ref Target - Figure 5-13
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Figure 5-13:
Clock Management - Multiple Core Instances, Virtex-6 FPGA GTX Transceivers for
1000BASE-X
1000BASE-X PCS/PMA or SGMII v11.4
PG047 October 16, 2012
www.xilinx.com
155
Chapter 5: 1000BASE-X with Transceivers
Spartan-6 LXT Devices
Figure 5-13 illustrates sharing clock resources across multiple instantiations of the core
when using Spartan-6 FPGA GTP transceivers.
The example design can be generated to connect either a single instance of the core or
connect a pair of core instances to the transceiver pair present in a GTP transceiver tile.
Figure 5-13 illustrates two instantiations of the block level, and each block level contains a
pair of cores, consequently illustrating clock sharing between a total of four cores.
Additional cores can be added by continuing to instantiate extra block level modules. Share
the brefclk_p and brefclk_n differential clock pair. See the Spartan-6 FPGA GTP
Transceiver User Guide for more information.
To provide the 125 MHz clock for all core instances, select a GTPCLKOUT port from any GTP
transceiver. This can be routed onto global clock routing using a BUFIO2 and BUFG as
illustrated and shared between all cores and GTP transceivers.
1000BASE-X PCS/PMA or SGMII v11.4
PG047 October 16, 2012
www.xilinx.com
156
Chapter 5: 1000BASE-X with Transceivers
X-Ref Target - Figure 5-14
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8
Figure 5-14:
Clock Management-Multiple Core Instances, Spartan-6 FPGA
GTP Transceivers for 1000BASE-X
1000BASE-X PCS/PMA or SGMII v11.4
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Chapter 5: 1000BASE-X with Transceivers
Virtex-7 Devices
Figure 5-15 illustrates sharing clock resources across two instantiations of the core when
using 7 series FPGAs Transceivers. Additional cores can be added by continuing to
instantiate extra block level modules.
To provide the FPGA logic clocks for all core instances, select a TXOUTCLK port from any
transceiver and route this to a single MMCM. The CLKOUT0 (125 MHz) and CLKOUT1 (62.5
MHz) outputs from this MMCM, placed onto global clock routing using BUFGs, can be
shared across all core instances and transceivers as illustrated.
1000BASE-X PCS/PMA or SGMII v11.4
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Chapter 5: 1000BASE-X with Transceivers
X-Ref Target - Figure 5-15
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Figure 5-15:
Clock Management-Multiple Core Instances, Virtex-7 FPGA Transceivers for 1000BASE-X
1000BASE-X PCS/PMA or SGMII v11.4
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Chapter 5: 1000BASE-X with Transceivers
Kintex-7 and Zynq-7000 Devices
Figure 5-16 illustrates sharing clock resources across two instantiations of the core when
using 7 series FPGAs transceivers. Additional cores can be added by continuing to
instantiate extra block level modules.
To provide the FPGA logic clocks for all core instances, select a TXOUTCLK port from any
transceiver and route this to a single MMCM through a BUFG (global clock routing). The
CLKOUT0 (125 MHz) and CLKOUT1 (62.5 MHz) outputs from this MMCM, placed onto
global clock routing using BUFGs, can be shared across all core instances and transceivers as
illustrated.
1000BASE-X PCS/PMA or SGMII v11.4
PG047 October 16, 2012
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160
Chapter 5: 1000BASE-X with Transceivers
X-Ref Target - Figure 5-16
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Figure 5-16:
Clock Management-Multiple Core Instances, Kintex-7/Zynq-7000 Device Transceivers for
1000BASE-X
1000BASE-X PCS/PMA or SGMII v11.4
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Chapter 5: 1000BASE-X with Transceivers
Artix-7 Devices
Figure 5-17 illustrates sharing clock resources across two instantiations of the core when
using 7 series FPGAs Transceivers. Additional cores can be added by continuing to
instantiate extra block level modules.
To provide the FPGA logic clocks for all core instances, select a TXOUTCLK port from any
transceiver and route this to a single MMCM. The CLKOUT0 (125 MHz) and CLKOUT1 (62.5
MHz) outputs from this MMCM, placed onto global clock routing using BUFGs, can be
shared across all core instances and transceivers as illustrated.
1000BASE-X PCS/PMA or SGMII v11.4
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162
Chapter 5: 1000BASE-X with Transceivers
X-Ref Target - Figure 5-17
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Figure 5-17:
Clock Management-Multiple Core Instances, Artix-7 FPGA Transceivers for
1000BASE-X
1000BASE-X PCS/PMA or SGMII v11.4
PG047 October 16, 2012
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Chapter 5: 1000BASE-X with Transceivers
Example Design for 1000BASE-X with
Transceivers
Chapter 20, Detailed Example Design contains a full list and description of the directory and
file structure that is provided with the core, including the location of the HDL example
design.
Figure 5-18 illustrates the complete example design for the Ethernet 1000BASE-X PCS/PMA
using the transceiver specific to the target device (Virtex-4, Virtex-5, Virtex-6, Virtex-7,
Kintex-7, Artix-7, Zynq-7000 or Spartan-6). Virtex-7, Kintex-7, and Artix-7 devices support
Vivado tools. Other families support only ISE tool.
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Example Design HDL for the Ethernet 1000BASE-X PCS/PMA
Using a Device-Specific Transceiver
As illustrated, the example is split between two hierarchical layers. The block level is
designed so that it can be instantiated directly into your design and performs the following
functions:
•
Instantiates the core from HDL
•
Connects the physical-side interface of the core to a device-specific transceiver
The top level of the example design creates a specific example that can be simulated,
synthesized, implemented, and if required, placed on a suitable board and demonstrated in
hardware. The top level of the example design performs the following functions:
1000BASE-X PCS/PMA or SGMII v11.4
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Chapter 5: 1000BASE-X with Transceivers
•
Instantiates the block level from HDL
•
Derives the clock management logic for a device-specific transceiver and the core
•
Implements an external GMII
The next few pages in this section describe each of the example design blocks (and
associated HDL files) in detail, and conclude with an overview of the demonstration test
bench provided for the design.
Top-Level Example Design HDL
The following files describe the top-level example design for the Ethernet 1000BASE-X
PCS/PMA core using a transceiver specific to the desired device.
VHDL
ISE Design Suite:
//example_design/_example_design.vhd
Vivado Design Suite:
//.srcs/sources1/ip//
/example_design/_example_design.vhd
Verilog
ISE Design Suite:
//example_design/_example_design.v
Vivado Design Suite:
//.srcs/sources1/ip//
/example_design/_example_design.v
The example design HDL top level contains the following:
•
An instance of the Ethernet 1000BASE-X PCS/PMA block level
•
Clock management logic for the core and the device-specific transceiver, including
DCM (if required) and Global Clock Buffer instances
•
A transmitter elastic buffer
•
GMII interface logic, including IOB instances
The example design HDL top-level connects the GMII of the block level to external IOBs.
This configuration allows the functionality of the core to be demonstrated using a
simulation package as discussed in this guide. The example design can also be synthesized
and, if required, placed on a suitable board and demonstrated in hardware.
1000BASE-X PCS/PMA or SGMII v11.4
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Chapter 5: 1000BASE-X with Transceivers
Note: In the Virtex-4, Virtex-5 and Spartan-6 architectures, transceivers are provided in pairs. When
generated with the appropriate options, the example design is capable of connecting two instances
of the core to the transceiver pair.
Block Level HDL
The following files describe the block-level design for the Ethernet 1000BASE-X PCS/PMA
core using a device-specific transceiver specific to the target device.
VHDL
ISE Design Suite:
//example_design/_block.vhd
Vivado Design Suite:
//.srcs/sources1/ip//
/example_design/_block.vhd
Verilog
ISE Design Suite:
//example_design/_block.v
Vivado Design Suite:
//.srcs/sources1/ip//
/example_design/_block.v
The block-level HDL contains the following:
•
An instance(s) of the Ethernet 1000BASE-X PCS/PMA core
•
An instance(s) of a transceiver specific to a Virtex-4, Virtex-5, Virtex-6, Virtex-7,
Kintex-7, Artix-7, Zynq-7000 or Spartan-6 device
The block-level HDL connects the PHY side interface of the core to a device-specific
transceiver, as illustrated in Figure 5-18. This is the most useful part of the example design
and should be instantiated in all customer designs that use the core.
Note: In the Virtex-4, Virtex-5 and Spartan-6 architectures, transceivers are provided in pairs. When
generated with the appropriate options, the block level is capable of connecting two instances of the
core to the transceiver.
1000BASE-X PCS/PMA or SGMII v11.4
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Chapter 5: 1000BASE-X with Transceivers
Transceiver Files for Zynq-7000, Virtex-7, Kintex-7, Artix-7 and
Devices
Transceiver Wrapper
This device-specific transceiver wrapper is instantiated from the block-level HDL file of the
example design and is described in the following files:
VHDL
ISE Design Suite:
//example_design/transceiver/
_transceiver.vhd
Vivado Design Suite: