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User Manual: Motherboard Quanta BU1 DABU1MB16E0 - Schematics. Free.
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1 2 3 4 5 6 7 8 BU1 Block Diagram PCB STACK UP LAYER 1 : TOP LAYER 2 : SGND Intel LAYER 3 : IN1 A CLOCK GENERATOR Merom LAYER 4 : IN2 CK505 ICS9LPR363 (35W) A Page 2 LAYER 5 : VCC Page 3,4 LAYER 6 : BOT FSB(667/800MHZ) R.G.B CRT Page 18 VCC_CORE LVDS X1 LCD(WXGA 13W) 533/ 667 MHZ DDR II Crestline GM DDRII-SODIMM1 DDRII-SODIMM2 Page 18 Page 12,13 +1.5V SATA SATA - HDD Page 5,7,8,9,10,11 G SENSOR Page 19 +1.05V PATA IDE - ODD DMI(x2/x4) Page 19 B +1.25V B System 0 Page 24 +1.8VSUS USB PORT 0 PCI-Express System 1 Page 24 +3VPCU +3V_S5 +3VSUS +3V +5VPCU +5V_S5 +5V SMDDR_VTERM SMDDR_VREF USB PORT 1 ICH8M System 2 Page 24 USB 2.0 USB PORT 2 Page 23 DAUGHTER BORD NEW CARD Page 23 Page 23 Page 24 (BOT) 100/10 LAN RTL8101E (BOT) USB PORT 3 Azalia Finger Printer (BOT) Page 24 Page 24 Page 20 Page 24 (BOT) 32.768KHz PCMCIA Controller (CB 1410) Page 21 (BOT) Card Reader/1394 (R5C833) RJ45 RJ11 USB Page 22 C USB PORT 6 PCMCIA (BOT) (BOT) USB PORT 7 Page 26 (BOT) USB PORT 8 AUDIO/FM/USB DAUGHTER BOARD AUDIO CODEC (ALC262) 5 IN 1 1394 (BOT) WPC8763LDG FAN HP AMP RJ11/RJ45/USB DAUGHTER BOARD (BOT) Camera Page 18 LPC USB PORT 5 Reserved Page 23 Connector PCI Bus Page 14,15,16,17 USB PORT 4 New Card C INT SPK MINI CARD WLAN Bluetooth HP MINI CARD WLAN Touch PAD Key Board PCI ROUTING IDSEL TABLE REQ0# / GNT0# AD17 INTERUPT DEVICE INTA#,INTB# R5C832 REQ1# / GNT1# AD20 INTC# CB1410 FLASH ROM Connector BTO BOM OPTION SPK AMP MDC 1.5 CB@ : CARD BUS FP@ : FINGER PRINTER BT@ : BLUETOOTH CM@ : CAMERA GS@ : G-SENSOR NEW@ : NEW CARD LCD@ : LCD TYPE PANEL LED@ : LED TYPE PANEL 1394@ : 1394 D Page 25 USB D Quanta Computer Inc. RJ11 1 2 PROJECT : BU1 Santa Rosa 3 4 5 6 7 Size Document Number Date: Monday, March 26, 2007 Rev 1A Block Diagram Sheet 1 8 of 33 5 4 3 2 Clock Generator 1 Clock Gen Differential IO power L26 +3V PBY160808T-301Y-N_6 +1.25V L25 PBY160808T-301Y-N_6 C411 .1U_4 'EMI FILTER BKP1608HS181-T(180,1.5A)' C426 C427 C428 C422 C425 C424 C419 C420 C416 R90 C414 .1U_4 *10U_810U_8 .1U_4 .1U_4 .1U_4 .1U_4 .1U_4 .1U_4 10U_8 0_6 D C408 10U_8 H=1.2mm C43 .1U_4 C418 .1U_4 R404 C412 .1U_4 2 9 16 61 VDD_CK_VDD_PCI VDD_CK_VDD_CPU 39 55 0_6 +1.25V_VDD C415 .1U_4 0_6 [23,26] PCLK_DEBUGPCI4/SRC5_EN: PU be used, the CK505 will be configured to use Pin37/38 to SRC5 clock.If PD be detect at powe-on,the CK505 will setting Pin 37/38 to PCI_STOP/CUP_SOTP(Default is setting to PCI_STOP/CUP_SOTP) [21] PCLK_PCM +3V [22] PCLK_R5C833 [26] PCLK_591 +3V R86 10K_4 R82 *10K_4 R74 R79 +3V [15] PCLK_ICH PCIF5/ITP_EN: PU be used, the CK505 will be configured to use Pin46/47 to CPU ITP clock.If PD be detect at powe-on,the CK505 will setting Pin 46/47 to SRC8(Default is setting to SRC8) [16] CLKUSB_48 [16] 14M_ICH R409 R407 10K_4 R72 1 PCI0/CR#_A R81 56_4 PCLK_PCM_R 3 PCI1/CR#_B R78 56_4 PCLK_R5C833_R 4 PCI2/TME R405 56_4 PCLK_591_R 5 PCI3 R73 22_4 PCI_CLK_SIO_R 6 PCI4/SRC5_EN R406 56_4 PCLK_ICH_R 7 PCIF5/ITP_EN CLK_BSEL2 R87 R88 CG_XIN 60 XTAL_IN CG_XOUT 59 XTAL_OUT 10 USB_48/FSA 33_4 FSA 2.2K_4 FSC 2.2K_4 33_4 57 FSB/TEST/MODE 62 REF0/FSC/TESTSEL 8 11 15 19 52 23 29 42 58 48 SCLK SDA 64 63 SRC5/PCI_STOP# SRC5#/CPU_STOP# 38 37 VDD_96_IO VDD_PLL3_IO VDD_SRC_IO_1 VDD_SRC_IO_3 VDD_SRC_IO_2 VDD_CPU_IO PCLK_DEBUG_R 10K_4 IO_VOUT CK505 VDD_SRC VDD_CPU 56_4 R71 CLK_BSEL0 CLK_BSEL1 IC(64P) ICS9LPRS365BGLFT(TSSOP) VDD_PCI VDD_48 VDD_PLL3 VDD_REF R85 *10K_4 *10K_4 12 20 26 45 36 49 0.1U close to each VDD_IO Power pin VSS_PCI VSS_48 VSS_IO VSS_PLL3 VSS_CPU VSS_SRC1 VSS_SRC2 VSS_SRC3 VSS_REF CGCLK_SMB CGDAT_SMB PM_STPPCI# [16] PM_STPCPU# [16] CPU0 CPU0# 54 53 CLK_CPU_BCLK_R CLK_CPU_BCLK#_R RP50 CPU1 CPU1# 51 50 CLK_MCH_BCLK_R CLK_MCH_BCLK#_R RP52 SRC8/ITP SRC8#/ITP# 47 46 RP58 1 3 2 0X2 4 CLK_CPU_BCLK [3] CLK_CPU_BCLK# [3] 1 3 2 0X2 4 CLK_MCH_BCLK [5] CLK_MCH_BCLK# [5] 1 3 2 0X2 4 CLK_PCIE_3GPLL# [6] CLK_PCIE_3GPLL [6] SRC10# SRC10 35 34 CLK_PCIE_3GPLL#_R CLK_PCIE_3GPLL_R SRC11/CR#_H SRC11#/CR#_G 33 32 CLK_MCH_OE#_R NEW_CLKREQ#_R SRC9 SRC9# 30 31 CLK_PCIE_NEW_R CLK_PCIE_NEW_R# RP59 3 1 4 0X2 2 SRC7/CR#_F SRC7#/CR#_E 44 43 CLK_PCIE_MINI2_R CLK_PCIE_MINI2#_R RP54 1 3 2 0X2 4 SRC6 SRC6# 41 40 CLK_PCIE_MINI_R CLK_PCIE_MINI#_R RP56 1 3 2 0X2 4 CLK_PCIE_MINI [23] CLK_PCIE_MINI# [23] SRC4 SRC4# 27 28 CLK_PCIE_LAN_R CLK_PCIE_LAN#_R RP57 3 1 4 0X2 2 CLK_PCIE_LAN [20] CLK_PCIE_LAN# [20] SRC3/CR#_C SRC3#/CR#_D 24 25 CLK_PCIE_ICH_R CLK_PCIE_ICH#_R RP55 3 1 4 0X2 2 CLK_PCIE_ICH [15] CLK_PCIE_ICH# [15] SRC2/SATA SRC2#/SATA# 21 22 CLK_PCIE_SATA_R CLK_PCIE_SATA#_R RP53 3 1 4 0X2 2 CLK_PCIE_SATA [14] CLK_PCIE_SATA# [14] SRC1/SE1 SRC1#/SE2 17 18 DREFSSCLK_R DREFSSCLK#_R RP13 1 3 2 0X2 4 SRC0/DOT96 SRC0#/DOT96# 13 14 DREFCLK_R DREFCLK#_R RP51 3 1 4 0X2 2 CKPWRGD/PWRDWN# 56 R410 R412 2 CG_XIN CL=20p C406 30P_4 (2)PCI4/SRC5_EN: PU be used, the CK505 will be configured to use Pin37/38 to SRC5 clock. If PD be detect at powe-on,the CK505 will setting Pin 37/38 to PCI_STOP/CUP_SOTP (Default is setting to PCI_STOP/CUP_SOTP) CG_XOUT XTAL length < 500mils Clock Gen I2C Q3 RHU002N06 (3)PCIF5/ITP_EN: PU be used, the CK505 will be configured to use Pin46/47 to CPU ITP clock. If PD be detect at powe-on,the CK505 will setting Pin 46/47 to SRC8 (Default is setting to SRC8) [13,16,19,23,24] (4)SLG8SP512 Pin 6 select Pin 17, 18 output is LCDCLK or 27 M, PD is LCDCLK, PU is 27 M , Pin 37, 38 will fixed be use CPU_Stop and PCI_Stop. BSEL Frequency Select Table FSB FSA Frequency 0 0 0 266Mhz 0 0 1 133Mhz 0 1 1 166Mhz DREFSSCLK [6] DREFSSCLK# [6] DREFCLK [6] DREFCLK# [6] SDATA [3] CPU_BSEL0 +1.05V R59 0_4 R66 *56_4 R65 *1K_4 R80 0_4 R77 *0_4 CLK_BSEL0 +3V 3 B R94 1 10K_4 CGDAT_SMB +3V (5)SLG505YC64 CK505 Standar parts follow standar setting FSC C (1)PCI2/TME: PU be used, the CK505 cannot over clock any of the clock for Trust Mode security purposes. Y6 14.318MHZ 1 B CLK_PCIE_MINI2 [23] CLK_PCIE_MINI2# [23] CK_PWRGD [16] H=1.5mm 30P_4 CLK_MCH_OE# [6] NEW_CLKREQ# [24] CLK_PCIE_NEW [24] CLK_PCIE_NEW# [24] During initial power-up be used to sample FSB speed with FSA/B/C ICS9LPRS365AGLFT/ SLG8SP512T C407 475_4 475_4 2 R68 U22 VDD_CK_VDD_PCI VDD_CK_VDD_48 VDD_CK_VDD_PCI VDD_CK_VDD_REF ICS9LPRS365BGLFT SLG8SP512T: AL8SP512K05 Q4 RHU002N06 CPU Clock select MCH_BSEL0 [6] [13,16,19,23,24] SCLK R95 2 D C +1.25V_VDD 3 1 10K_4 CGCLK_SMB FSA +3V [3] CPU_BSEL1 0 A 1 MCH_BSEL1 [6] R411 200Mhz 0 CLK_BSEL1 A1A: (9/20) Remove 0ohm 1 1 400Mhz 0 +1.05V 1 1 1 Reserved 1 0 1 100Mhz 1 0 0 333Mhz [3] CPU_BSEL2 +1.05V 5 4 R408 *1K_4 R55 0_4 R62 *0_4 R56 *1K_4 CLK_BSEL2 10K_4 NEW_CLKREQ#_R FSB A MCH_BSEL2 [6] Quanta Computer Inc. FSC 3 PROJECT : BU1 Santa Rosa 2 Size Document Number Date: Monday, March 26, 2007 Rev 1A CLK. GEN./ CK505 Sheet 1 2 of 33 5 4 A20M# FERR# IGNNE# D5 C6 B4 A3 STPCLK# LINT0 LINT1 SMI# M4 N5 T2 V3 B2 C3 D2 D22 D3 F6 RSVD[01] RSVD[02] RSVD[03] RSVD[04] RSVD[05] RSVD[06] RSVD[07] RSVD[08] RSVD[09] RSVD[10] H_STPCLK_R# T3 T5 T8 T1 T146 T7 T6 T9 T4 T12 TP_CPU_RSVD01 TP_CPU_RSVD02 TP_CPU_RSVD03 TP_CPU_RSVD04 TP_CPU_RSVD05 TP_CPU_RSVD06 TP_CPU_RSVD07 TP_CPU_RSVD08 TP_CPU_RSVD09 TP_CPU_RSVD10 H5 F21 E1 H_DEFER# [5] H_DRDY# [5] H_DBSY# [5] F1 +3V H_BREQ#0 [5] D20 H_IERR# B3 R16 56.2_4 +1.05V +3V H_INIT# [14] H4 H_LOCK# [5] RESET# RS[0]# RS[1]# RS[2]# TRDY# C1 F3 F4 G3 G2 H_CPURST# [5] H_RS#0 [5] H_RS#1 [5] H_RS#2 [5] H_TRDY# [5] HIT# HITM# G6 E4 H_HIT# [5] H_HITM# [5] BPM[0]# BPM[1]# BPM[2]# BPM[3]# PRDY# PREQ# TCK TDI TDO TMS TRST# DBR# AD4 AD3 AD1 AC4 AC2 AC1 AC5 AA6 AB3 AB5 AB6 C20 THERMTRIP# H CLK BCLK[0] BCLK[1] R19 0_4 R17 56.2_4 R18 *2.2K_4 Q34 RHU002N06 [5] [5] [5] [5] H_DSTBN#0 H_DSTBP#0 H_DINV#0 H_D#[31:16] Layout note: Z=55 ohm H_GTLREF<0.5" R11 1K_4 [5] H_DSTBN#1 [5] H_DSTBP#1 [5] H_DINV#1 R21 R20 A T10 R9 2K_6 C14 T2 T11 [2] CPU_BSEL0 [2] CPU_BSEL1 [2] CPU_BSEL2 *0_4 THERM_ALERT#_R R438 10K_4 THER_SHD# H_GTLREF AD26 *1K_4 CPU_TEST1 C23 *1K_4 CPU_TEST2 D25 CPU_TEST3 C24 *.1U_4 CPU_TEST4 AF26 CPU_TEST5 AF1 CPU_TEST6 A26 GTLREF TEST1 TEST2 TEST3 TEST4 TEST5 TEST6 B22 B23 C21 BSEL[0] BSEL[1] BSEL[2] 4 AE24 AD24 AA21 AB22 AB21 AC26 AD20 AE22 AF23 AC25 AE21 AD21 AC22 AD23 AF22 AC23 AE25 AF24 AC20 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63 COMP[0] COMP[1] COMP[2] COMP[3] R26 U26 AA1 Y1 COMP0 COMP1 COMP2 COMP3 DPRSTP# DPSLP# DPWR# PWRGOOD SLP# PSI# E5 B5 D24 D6 D7 AE6 MISC ALERT# DXN 3 2200P_4 OVERT# GND 5 H_THERMDC Layout Note:Routing 10:10 mils and away from noise source with ground gard H_PROCHOT# [29] CPU FAN +3V C R458 330_4 H_D#[47:32] [5] D[48]# D[49]# D[50]# D[51]# D[52]# D[53]# D[54]# D[55]# D[56]# D[57]# D[58]# D[59]# D[60]# D[61]# D[62]# D[63]# DSTBN[3]# DSTBP[3]# DINV[3]# DXP C454 +1.05V +3V Q37 MMBT3904 1 R1 3 SYS_SHDN# [28] 2 +5V H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 SDA 2 ADDRESS: 98H 10K_4 [26] FANSIG CN34 U26 Y22 AB24 V24 V26 V23 T22 U25 U23 Y25 W22 Y23 W24 W25 AA23 AA24 AB25 Y26 AA26 U22 1 SYS_RST# [16] .1U_4 1 4 [26] VFAN VIN VO GND /FON GND GND VSET GND TH_FAN_POWER 3 5 6 7 8 G995 1 2 3 C489 C491 C9 10U_8 .01U_4 *.01U_4 4 5 PTI_CWY030-B0G1Z FANPWR = 1.6*VSET PU/PD (ITP700) Thermal Trip +1.05V B +1.05V H_DSTBN#2 [5] H_DSTBP#2 [5] H_DINV#2 [5] H_D#[63:48] [5] [6,16,29] DELAY_VR_PWRGOOD XDP_TMS R7 39_4 XDP_TDI R6 150_4 2 +1.05V Q1 R23 D3 FDV301N *10K_4 *BAS316 C35 *1U_6 R25 56.2_4 THERMTRIP#_PWR Layout note: L<0.5" COMP0/2 Z=27.4ohm COMP1/3 Z=54.9 H_DSTBN#3 [5] H_DSTBP#3 [5] H_DINV#3 [5] R14 R13 R10 R8 27.4_6 54.9_4 27.4_6 54.9_4 H_DPSLP# [14] H_DPWR# [5] H_CPUSLP# [5] PSI# [29] XDP_TCK R5 27_4 XDP_TRST# R4 680_4 1 Q2 MMBT3904 3 R24 Layout Note:Connect from SB and daisy chain to CPU CORE VR.Not use T connect.(SB/VR/CPU/NB) SYS_SHDN# [28] *0_4 PM_THRMTRIP# [6,14] Layout Note: Thermal trip should connect to ICH8 & GMCH without T-ing (ZS1 default NC) A ICH_DPRSTP# [6,14,29] H_PWRGD [14] Quanta Computer Inc. Merom Ball-out Rev 1a 5 6 H_THERMDA VCC SCLK 3 D[16]# D[17]# D[18]# D[19]# D[20]# D[21]# D[22]# D[23]# D[24]# D[25]# D[26]# D[27]# D[28]# D[29]# D[30]# D[31]# DSTBN[1]# DSTBP[1]# DINV[1]# 7 MAX6657 H=1.75mm DATA GRP 2 N22 K25 P26 R23 L23 M24 L22 M23 P25 P23 P22 T24 R24 L25 T25 N25 L26 M26 N24 DATA GRP 1 +1.05V H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 8 R435 CLK_CPU_BCLK [2] CLK_CPU_BCLK# [2] D[32]# D[33]# D[34]# D[35]# D[36]# D[37]# D[38]# D[39]# D[40]# D[41]# D[42]# D[43]# D[44]# D[45]# D[46]# D[47]# DSTBN[2]# DSTBP[2]# DINV[2]# .1U_4 H=1.75mm R434 +3V Default PU 56ohm if no use. Serial R NC, If connect to power side PU 68ohm. Serial R 2.2K THERMTRIP#_PWR D LM86VCC C455 1 [16] THERM_ALERT# XDP_TMS XDP_TRST# XDP_DBRESET# A22 A21 DATA GRP 3 B D[0]# D[1]# D[2]# D[3]# D[4]# D[5]# D[6]# D[7]# D[8]# D[9]# D[10]# D[11]# D[12]# D[13]# D[14]# D[15]# DSTBN[0]# DSTBP[0]# DINV[0]# 200_6 U23 3 +3V XDP_TCK XDP_TDI Merom Ball-out Rev 1a U24B E22 F24 E26 G22 F23 G25 E25 E23 K24 G24 J24 J23 H22 F26 K22 H23 J26 H26 H25 R437 10K_4 +3V THER_SHD# DATA GRP 0 H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 R432 10K_4 1 C290 [5] H_D#[15:0] R431 *10K_4 D21 H_PROCHOT_R# A24 H_THERMDA B25 H_THERMDC C7 3 [18,26,27] MBCLK [18,26,27] MBDATA THERMAL PROCHOT# THERMDA THERMDC Q33 RHU002N06 2 LOCK# ICH 0_4 CPU Thermal monitor 1 A6 A5 C4 H_ADS# [5] H_BNR# [5] H_BPRI# [5] 1 2 [14] H_A20M# [14] H_FERR# [14] H_IGNNE# A[17]# A[18]# A[19]# A[20]# A[21]# A[22]# A[23]# A[24]# A[25]# A[26]# A[27]# A[28]# A[29]# A[30]# A[31]# A[32]# A[33]# A[34]# A[35]# ADSTB[1]# IERR# INIT# H1 E2 G5 2 [5] H_ADSTB1# [14] H_INTR [14] H_NMI [14] H_SMI# BR0# REQ[0]# REQ[1]# REQ[2]# REQ[3]# REQ[4]# Y2 U5 R3 W6 U4 Y5 U1 R4 T5 T3 W2 W5 Y4 U2 V4 W3 AA4 AB2 AA3 V1 R26 [14] H_STPCLK# H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35 DEFER# DRDY# DBSY# ADDR GROUP 1 C K3 H2 K2 J3 L1 ADS# BNR# BPRI# 2 2 [5] H_A#[35:17] H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4 A[3]# A[4]# A[5]# A[6]# A[7]# A[8]# A[9]# A[10]# A[11]# A[12]# A[13]# A[14]# A[15]# A[16]# ADSTB[0]# CONTROL [5] H_ADSTB0# [5] H_REQ#[4:0] J4 L5 L4 K5 M3 N2 J1 N3 P5 P2 L2 P4 P1 R1 M1 XDP/ITP SIGNALS D H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 ADDR GROUP 0 CPU(HOST) 3 U24A RESERVED [5] H_A#[16:3] PROJECT : BU1 Santa Rosa 4 3 2 Size Document Number Date: Monday, March 26, 2007 Rev 3A CPU(1 of 2)/FAN/Thermal Sheet 1 3 of 33 5 4 3 2 1 CPU(Power) VCC_CORE U24D U24C D C465 C25 C466 C461 C473 C472 C477 C471 C21 C476 10U_8 10U_8 10U_8 10U_8 10U_8 10U_8 10U_8 10U_8 10U_8 10U_8 C475 C469 C463 C474 C464 C19 C20 C23 C459 C460 10U_8 10U_8 10U_8 10U_8 10U_8 10U_8 10U_8 10U_8 10U_8 10U_8 C31 C28 C470 C462 C30 C467 10U_8 10U_8 10U_8 10U_8 10U_8 10U_8 DESIGN GUIDE CHANGE FROM 22UF *20 TO 10UF *32 C C468 C27 C458 C24 C26 10U_8 10U_8 10U_8 10U_8 10U_8 + C32 + C13 330U_7343 *330U_7343 C457 10U_8 CH6102K9A01 'CAP CHIP 10U 10V(+-10%,X5R,0805)' + C29 330U_7343 Option1:330U*6(ESR=1.5m ohm aggregate , ESL=0.8nH/6) and 22U*20(ESR=3mohm typ/20 , ESL=0.6nH/20) Option2:330U*6(ESR=1.5m ohm aggregate , ESL=1.8nH/6) and 22U*32(ESR=3mohm typ/32 , ESL=0.6nH/32) B A7 A9 A10 A12 A13 A15 A17 A18 A20 B7 B9 B10 B12 B14 B15 B17 B18 B20 C9 C10 C12 C13 C15 C17 C18 D9 D10 D12 D14 D15 D17 D18 E7 E9 E10 E12 E13 E15 E17 E18 E20 F7 F9 F10 F12 F14 F15 F17 F18 F20 AA7 AA9 AA10 AA12 AA13 AA15 AA17 AA18 AA20 AB9 AC10 AB10 AB12 AB14 AB15 AB17 AB18 VCC[001] VCC[002] VCC[003] VCC[004] VCC[005] VCC[006] VCC[007] VCC[008] VCC[009] VCC[010] VCC[011] VCC[012] VCC[013] VCC[014] VCC[015] VCC[016] VCC[017] VCC[018] VCC[019] VCC[020] VCC[021] VCC[022] VCC[023] VCC[024] VCC[025] VCC[026] VCC[027] VCC[028] VCC[029] VCC[030] VCC[031] VCC[032] VCC[033] VCC[034] VCC[035] VCC[036] VCC[037] VCC[038] VCC[039] VCC[040] VCC[041] VCC[042] VCC[043] VCC[044] VCC[045] VCC[046] VCC[047] VCC[048] VCC[049] VCC[050] VCC[051] VCC[052] VCC[053] VCC[054] VCC[055] VCC[056] VCC[057] VCC[058] VCC[059] VCC[060] VCC[061] VCC[062] VCC[063] VCC[064] VCC[065] VCC[066] VCC[067] VCC[068] VCC[069] VCC[070] VCC[071] VCC[072] VCC[073] VCC[074] VCC[075] VCC[076] VCC[077] VCC[078] VCC[079] VCC[080] VCC[081] VCC[082] VCC[083] VCC[084] VCC[085] VCC[086] VCC[087] VCC[088] VCC[089] VCC[090] VCC[091] VCC[092] VCC[093] VCC[094] VCC[095] VCC[096] VCC[097] VCC[098] VCC[099] VCC[100] AB20 AB7 AC7 AC9 AC12 AC13 AC15 AC17 AC18 AD7 AD9 AD10 AD12 AD14 AD15 AD17 AD18 AE9 AE10 AE12 AE13 AE15 AE17 AE18 AE20 AF9 AF10 AF12 AF14 AF15 AF17 AF18 AF20 VCCP[01] VCCP[02] VCCP[03] VCCP[04] VCCP[05] VCCP[06] VCCP[07] VCCP[08] VCCP[09] VCCP[10] VCCP[11] VCCP[12] VCCP[13] VCCP[14] VCCP[15] VCCP[16] G21 V6 J6 K6 M6 J21 K21 M21 N21 N6 R21 R6 T21 T6 V21 W21 CPU_G21 CPU_V6 VCCA[01] VCCA[02] B26 C26 +VCCA_PROC Ivcc Max 52A Ivccp Max 6A(VCCP supply before Vcc stable) Max 2A(VCCP supply after Vcc stable) Ivcca Max 130mA +1.05V VCCSENSE AF7 VSSSENSE AE7 R15 R12 C16 C18 C17 C456 C15 C22 .1U_6 .1U_6 .1U_6 .1U_6 .1U_6 .1U_6 +1.05V R for test only 0_4 0_4 + C36 330U_7343 ESR=12m ohm +1.5V .01U near to B26 ball AD6 AF5 AE5 AF4 AE3 AF3 AE2 VID[0] VID[1] VID[2] VID[3] VID[4] VID[5] VID[6] A4 A8 A11 A14 A16 A19 A23 AF2 B6 B8 B11 B13 B16 B19 B21 B24 C5 C8 C11 C14 C16 C19 C2 C22 C25 D1 D4 D8 D11 D13 D16 D19 D23 D26 E3 E6 E8 E11 E14 E16 E19 E21 E24 F5 F8 F11 F13 F16 F19 F2 F22 F25 G4 G1 G23 G26 H3 H6 H21 H24 J2 J5 J22 J25 K1 K4 K23 K26 L3 L6 L21 L24 M2 M5 M22 M25 N1 N4 N23 N26 P3 R22 H_VID0 H_VID1 H_VID2 H_VID3 H_VID4 H_VID5 H_VID6 [29] [29] [29] [29] [29] [29] [29] VCC_CORE C33 C34 .01U_4 10U_8 0_6 R2 100/F_6 VCCSENSE [29] VSSSENSE [29] Merom Ball-out Rev 1a . R3 100/F_6 Routing 27.4ohm with 50mils spacing PU/PD near to CPU 1" VSS[001] VSS[002] VSS[003] VSS[004] VSS[005] VSS[006] VSS[007] VSS[008] VSS[009] VSS[010] VSS[011] VSS[012] VSS[013] VSS[014] VSS[015] VSS[016] VSS[017] VSS[018] VSS[019] VSS[020] VSS[021] VSS[022] VSS[023] VSS[024] VSS[025] VSS[026] VSS[027] VSS[028] VSS[029] VSS[030] VSS[031] VSS[032] VSS[033] VSS[034] VSS[035] VSS[036] VSS[037] VSS[038] VSS[039] VSS[040] VSS[041] VSS[042] VSS[043] VSS[044] VSS[045] VSS[046] VSS[047] VSS[048] VSS[049] VSS[050] VSS[051] VSS[052] VSS[053] VSS[054] VSS[055] VSS[056] VSS[057] VSS[058] VSS[059] VSS[060] VSS[061] VSS[062] VSS[063] VSS[064] VSS[065] VSS[066] VSS[067] VSS[068] VSS[069] VSS[070] VSS[071] VSS[072] VSS[073] VSS[074] VSS[075] VSS[076] VSS[077] VSS[078] VSS[079] VSS[080] VSS[081] P6 P21 P24 R2 R5 R22 R25 T1 T4 T23 T26 U3 U6 U21 U24 V2 V5 V22 V25 W1 W4 W23 W26 Y3 Y6 Y21 Y24 AA2 AA5 AA8 AA11 AA14 AA16 AA19 AA22 AA25 AB1 AB4 AB8 AB11 AB13 AB16 AB19 AB23 AB26 AC3 AC6 AC8 AC11 AC14 AC16 AC19 AC21 AC24 AD2 AD5 AD8 AD11 AD13 AD16 AD19 AD22 AD25 AE1 AE4 AE8 AE11 AE14 AE16 AE19 AE23 AE26 A2 AF6 AF8 AF11 AF13 AF16 AF19 AF21 A25 AF25 VSS[082] VSS[083] VSS[084] VSS[085] VSS[086] VSS[087] VSS[088] VSS[089] VSS[090] VSS[091] VSS[092] VSS[093] VSS[094] VSS[095] VSS[096] VSS[097] VSS[098] VSS[099] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106] VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158] VSS[159] VSS[160] VSS[161] VSS[162] VSS[163] D C B Merom Ball-out Rev 1a . A A Quanta Computer Inc. PROJECT : BU1 Santa Rosa 5 4 3 2 Size Document Number Date: Monday, March 26, 2007 Rev 1A CPU(2 of 2) Sheet 1 4 of 33 5 4 3 2 NB(HOST) R416 221/F_4 H_SWING R417 100/F_4 C436 .1U_4 0.1U close to B3 H_RCOMP 10:20 mils(Width:Spacing) R415 C 24.9/F_4 +1.05V R76 54.9/F_4 Impedance 55ohm H_SCOMP B +1.05V R75 Impedance 55ohm 54.9/F_4 H_SCOMP# +1.05V H_D#_0 H_D#_1 H_D#_2 H_D#_3 H_D#_4 H_D#_5 H_D#_6 H_D#_7 H_D#_8 H_D#_9 H_D#_10 H_D#_11 H_D#_12 H_D#_13 H_D#_14 H_D#_15 H_D#_16 H_D#_17 H_D#_18 H_D#_19 H_D#_20 H_D#_21 H_D#_22 H_D#_23 H_D#_24 H_D#_25 H_D#_26 H_D#_27 H_D#_28 H_D#_29 H_D#_30 H_D#_31 H_D#_32 H_D#_33 H_D#_34 H_D#_35 H_D#_36 H_D#_37 H_D#_38 H_D#_39 H_D#_40 H_D#_41 H_D#_42 H_D#_43 H_D#_44 H_D#_45 H_D#_46 H_D#_47 H_D#_48 H_D#_49 H_D#_50 H_D#_51 H_D#_52 H_D#_53 H_D#_54 H_D#_55 H_D#_56 H_D#_57 H_D#_58 H_D#_59 H_D#_60 H_D#_61 H_D#_62 H_D#_63 H_SWING H_RCOMP B3 C2 H_SWING H_RCOMP H_SCOMP H_SCOMP# W1 W2 H_SCOMP H_SCOMP# B6 E5 H_CPURST# H_CPUSLP# [3] H_CPURST# [3] H_CPUSLP# R418 E2 G2 G7 M6 H7 H3 G4 F3 N8 H2 M10 N12 N9 H5 P13 K9 M2 W10 Y8 V4 M3 J1 N5 N3 W6 W9 N2 Y7 Y9 P4 W3 N1 AD12 AE3 AD9 AC9 AC7 AC14 AD11 AC11 AB2 AD7 AB1 Y3 AC6 AE2 AC5 AG3 AJ9 AH8 AJ14 AE9 AE11 AH12 AJ5 AH5 AJ6 AE7 AJ7 AJ2 AE5 AJ3 AH2 AH13 HOST H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63 +1.05V D H_A#[35:3] [3] U21A [3] H_D#[63:0] 1K_4 H_AVREF A R422 C432 2K_4 .1U_4 B9 A9 1 H_A#_3 H_A#_4 H_A#_5 H_A#_6 H_A#_7 H_A#_8 H_A#_9 H_A#_10 H_A#_11 H_A#_12 H_A#_13 H_A#_14 H_A#_15 H_A#_16 H_A#_17 H_A#_18 H_A#_19 H_A#_20 H_A#_21 H_A#_22 H_A#_23 H_A#_24 H_A#_25 H_A#_26 H_A#_27 H_A#_28 H_A#_29 H_A#_30 H_A#_31 H_A#_32 H_A#_33 H_A#_34 H_A#_35 J13 B11 C11 M11 C15 F16 L13 G17 C14 K16 B13 L16 J17 B14 K19 P15 R17 B16 H20 L19 D17 M17 N16 J19 B18 E19 B17 B15 E17 C18 A19 B19 N19 H_ADS# H_ADSTB#_0 H_ADSTB#_1 H_BNR# H_BPRI# H_BREQ# H_DEFER# H_DBSY# HPLL_CLK HPLL_CLK# H_DPWR# H_DRDY# H_HIT# H_HITM# H_LOCK# H_TRDY# G12 H17 G20 C8 E8 F12 D6 C10 AM5 AM7 H8 K7 E4 C6 G10 B7 H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35 D H_A#[35:32] are not supported in Calero Interposer Crestline support 36 bit address C H_ADS# [3] H_ADSTB0# [3] H_ADSTB1# [3] H_BNR# [3] H_BPRI# [3] H_BREQ#0 [3] H_DEFER# [3] H_DBSY# [3] CLK_MCH_BCLK [2] CLK_MCH_BCLK# [2] H_DPWR# [3] H_DRDY# [3] H_HIT# [3] H_HITM# [3] H_LOCK# [3] H_TRDY# [3] H_DINV#[3:0] H_DINV#0 H_DINV#1 H_DINV#2 H_DINV#3 H_DINV#_0 H_DINV#_1 H_DINV#_2 H_DINV#_3 K5 L2 AD13 AE13 H_DSTBN#_0 H_DSTBN#_1 H_DSTBN#_2 H_DSTBN#_3 M7 K3 AD2 AH11 H_DSTBN#0 H_DSTBN#1 H_DSTBN#2 H_DSTBN#3 H_DSTBP#_0 H_DSTBP#_1 H_DSTBP#_2 H_DSTBP#_3 L7 K2 AC2 AJ10 H_DSTBP#0 H_DSTBP#1 H_DSTBP#2 H_DSTBP#3 H_REQ#_0 H_REQ#_1 H_REQ#_2 H_REQ#_3 H_REQ#_4 M14 E13 A11 H13 B12 H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4 H_RS#_0 H_RS#_1 H_RS#_2 E12 D7 D8 H_RS#0 H_RS#1 H_RS#2 [3] B H_DSTBN#[3:0] [3] H_DSTBP#[3:0] [3] H_REQ#[4:0] H_RS#[2:0] [3] [3] H_AVREF H_DVREF A CRESTLINE_1p0 0.1U close to B9 Quanta Computer Inc. PROJECT : BU1 Santa Rosa 5 4 3 2 Size Document Number Date: Monday, March 26, 2007 Rev 1A GMCH HOST(1 of 7) Sheet 1 5 of 33 5 4 3 2 1 U21B MCH_CFG_6 MCH_CFG_7 MCH_CFG_8 MCH_CFG_10 MCH_CFG_11 T33 T27 [11] MCH_CFG_12 [11] MCH_CFG_13 MCH_CFG_14 MCH_CFG_15 T13 T23 [11] MCH_CFG_16 MCH_CFG_17 MCH_CFG_18 T26 T21 [11] MCH_CFG_19 [11] MCH_CFG_20 B R50 R45 R38 R97 R64 R42 0_4 PM_BMBUSY#_R 0_4 ICH_DPRSTP#_R PM_EXTTS#0 0_4 PM_EXTTS#1_R G41 L39 L36 J36 AW49 100_4RST_IN#_MCH AV20 PM_THRMTRIP#_GMCH N20 *0_4 0_4PM_DPRSLPVR_GMCH G36 BJ51 BK51 BK50 BL50 BL49 BL3 BL2 BK1 BJ1 E1 A5 C51 B50 A50 A49 BK2 M_CLK_DDR#0 M_CLK_DDR#1 M_CLK_DDR#3 M_CLK_DDR#4 SM_CKE_0 SM_CKE_1 SM_CKE_3 SM_CKE_4 BE29 AY32 BD39 BG37 M_CKE0 M_CKE1 M_CKE3 M_CKE4 [12,13] [12,13] [12,13] [12,13] SM_CS#_0 SM_CS#_1 SM_CS#_2 SM_CS#_3 BG20 BK16 BG16 BE13 M_CS#0 M_CS#1 M_CS#2 M_CS#3 [12,13] [12,13] [12,13] [12,13] SM_ODT_0 SM_ODT_1 SM_ODT_2 SM_ODT_3 BH18 BJ15 BJ14 BE16 M_ODT0 M_ODT1 M_ODT2 M_ODT3 [12,13] [12,13] [12,13] [12,13] SM_RCOMP SM_RCOMP# BL15 BK14 M_RCOMP M_RCOMP# SM_RCOMP_VOH SM_RCOMP_VOL BK31 BL31 SM_RCOMP_VOH SM_RCOMP_VOL SM_VREF_0 SM_VREF_1 AR49 AW4 DPLL_REF_CLK DPLL_REF_CLK# DPLL_REF_SSCLK DPLL_REF_SSCLK# B42 C42 H48 H47 PEG_CLK PEG_CLK# K44 K45 NC_1 NC_2 NC_3 NC_4 NC_5 NC_6 NC_7 NC_8 NC_9 NC_10 NC_11 NC_12 NC_13 NC_14 NC_15 NC_16 L_BKLT_CTRL L_BKLT_EN L_CTRL_CLK L_CTRL_DATA L_DDC_CLK L_DDC_DATA L_VDD_EN L41 L43 N41 N40 D46 C45 D44 E42 LVDS_IBG LVDS_VBG LVDS_VREFH LVDS_VREFL LVDSA_CLK# LVDSA_CLK LVDSB_CLK# LVDSB_CLK [18] INT_TXLOUT0[18] INT_TXLOUT1[18] INT_TXLOUT2- G51 E51 F49 LVDSA_DATA#_0 LVDSA_DATA#_1 LVDSA_DATA#_2 [18] INT_TXLOUT0+ [18] INT_TXLOUT1+ [18] INT_TXLOUT2+ G50 E50 F48 LVDSA_DATA_0 LVDSA_DATA_1 LVDSA_DATA_2 G44 B47 B45 LVDSB_DATA#_0 LVDSB_DATA#_1 LVDSB_DATA#_2 E44 A47 A45 LVDSB_DATA_0 LVDSB_DATA_1 LVDSB_DATA_2 E27 G27 K27 TVA_DAC TVB_DAC TVC_DAC F27 J27 L27 TVA_RTN TVB_RTN TVC_RTN M35 P33 TV_DCONSEL_0 TV_DCONSEL_1 H32 G32 K29 J29 F29 E29 CRT_BLUE CRT_BLUE# CRT_GREEN CRT_GREEN# CRT_RED CRT_RED# K33 G35 F33 C32 E33 CRT_DDC_CLK CRT_DDC_DATA CRT_HSYNC CRT_TVO_IREF CRT_VSYNC [18] INT_LVDS_PWM [18,26] INT_LVDS_BLON +3V [13] [13] [13] [13] R57 LVDS_IBG T25 [18] INT_TXLCLKOUT[18] INT_TXLCLKOUT+ SMDDR_VREF_MCH R107 R98 DREFCLK DREFCLK# DREFSSCLK DREFSSCLK# R108 0_6 *10K_6 *10K_6 +1.8VSUS DREFCLK [2] DREFCLK# [2] DREFSSCLK [2] DREFSSCLK# [2] CLK_PCIE_3GPLL [2] CLK_PCIE_3GPLL# [2] DMI_TXN[3:0] [15] DMI_RXN_0 DMI_RXN_1 DMI_RXN_2 DMI_RXN_3 AN47 AJ38 AN42 AN46 DMI_TXN0 DMI_TXN1 DMI_TXN2 DMI_TXN3 DMI_RXP_0 DMI_RXP_1 DMI_RXP_2 DMI_RXP_3 AM47 AJ39 AN41 AN45 DMI_TXP0 DMI_TXP1 DMI_TXP2 DMI_TXP3 DMI_TXN_0 DMI_TXN_1 DMI_TXN_2 DMI_TXN_3 AJ46 DMI_RXN0 AJ41 DMI_RXN1 AM40 DMI_RXN2 AM44 DMI_RXN3 DMI_TXP_0 DMI_TXP_1 DMI_TXP_2 DMI_TXP_3 AJ47 DMI_RXP0 AJ42 DMI_RXP1 AM39 DMI_RXP2 AM43 DMI_RXP3 DMI_TXP[3:0] [15] R34 R37 CRT_B [18] CRT_B DMI_RXP[3:0] [15] CRT_G [18] CRT_G CRT_R [18] CRT_R 1.3K_6 DDCCLK DDCDAT 30_4 HSYNC_A CRTIREF R40 30_4 VSYNC_A [18] DDCCLK [18] DDCDAT [18] HSYNC R41 [18] VSYNC GFX_VID_0 GFX_VID_1 GFX_VID_2 GFX_VID_3 GFX_VR_EN E35 A39 C38 B39 E36 T16 T144 T133 T140 T143 SDVO_CTRL_CLK SDVO_CTRL_DATA CLK_REQ# ICH_SYNC# TEST_1 TEST_2 AM49 AK50 AT43 AN49 AM50 +1.25V_CL_VREF A37 GMCH_TEST1 R32 GMCH_TEST2 N43 EXP_A_COMPX M43 PEG_RX#_0 PEG_RX#_1 PEG_RX#_2 PEG_RX#_3 PEG_RX#_4 PEG_RX#_5 PEG_RX#_6 PEG_RX#_7 PEG_RX#_8 PEG_RX#_9 PEG_RX#_10 PEG_RX#_11 PEG_RX#_12 PEG_RX#_13 PEG_RX#_14 PEG_RX#_15 J51 L51 N47 T45 T50 U40 Y44 Y40 AB51 W49 AD44 AD40 AG46 AH49 AG45 AG41 PEG_RX_0 PEG_RX_1 PEG_RX_2 PEG_RX_3 PEG_RX_4 PEG_RX_5 PEG_RX_6 PEG_RX_7 PEG_RX_8 PEG_RX_9 PEG_RX_10 PEG_RX_11 PEG_RX_12 PEG_RX_13 PEG_RX_14 PEG_RX_15 J50 L50 M47 U44 T49 T41 W45 W41 AB50 Y48 AC45 AC41 AH47 AG49 AH45 AG42 PEG_TX#_0 PEG_TX#_1 PEG_TX#_2 PEG_TX#_3 PEG_TX#_4 PEG_TX#_5 PEG_TX#_6 PEG_TX#_7 PEG_TX#_8 PEG_TX#_9 PEG_TX#_10 PEG_TX#_11 PEG_TX#_12 PEG_TX#_13 PEG_TX#_14 PEG_TX#_15 N45 U39 U47 N51 R50 T42 Y43 W46 W38 AD39 AC46 AC49 AC42 AH39 AE49 AH44 PEG_TX_0 PEG_TX_1 PEG_TX_2 PEG_TX_3 PEG_TX_4 PEG_TX_5 PEG_TX_6 PEG_TX_7 PEG_TX_8 PEG_TX_9 PEG_TX_10 PEG_TX_11 PEG_TX_12 PEG_TX_13 PEG_TX_14 PEG_TX_15 M45 T38 T46 N50 R51 U43 W42 Y47 Y39 AC38 AD47 AC50 AD43 AG39 AE50 AH43 R67 24.9_4 D C R46 150_4 CRT_B R52 150_4 CRT_G R49 150_4 CRT_R B R84 CL_CLK0 [16] CL_DATA0 [16] MPWROK [16] CL_RST#0 [16] 1K_4 T17 T24 H35 K36 G39 CLK_MCH_OE# G40 PEG_COMPI PEG_COMPO CRESTLINE_1p0 +1.25V_AXD CL_CLK CL_DATA CL_PWROK CL_RST# CL_VREF *0_4 *0_4 DMI_RXN[3:0] [15] C67 R83 .1U_4 392_6 CLK_MCH_OE# [2] MCH_ICH_SYNC# [16] R428 R70 0_4 20K_4 +1.8VSUS +3V R106 1K_4 SM_RCOMP_VOH R104 C93 C95 3.01K_4 .01U_4 2.2U_6 A SM_RCOMP_VOL R102 R105 R44 10K_4 CLK_MCH_OE# 20_4 R39 10K_4 PM_EXTTS#0 R32 10K_4 PM_EXTTS#1 20_4 M_RCOMP 5 2.4K_4 SMDDR_VREF A +1.8VSUS 10K_4 10K_4 [18] INT_LVDS_EDIDCLK [18] INT_LVDS_EDIDDATA [18] INT_LVDS_DIGON CRESTLINE_1p0 M_RCOMP# R414 R429 GRAPHICS AW30 BA23 AW25 AW23 J40 H39 E39 E40 C37 D35 K40 PCI-EXPRESS MUXING DDR CLK PM_BM_BUSY# PM_DPRSTP# PM_EXT_TS#_0 PM_EXT_TS#_1 PWROK RSTIN# THERMTRIP# DPRSLPVR NC TP_MCH_NC1 TP_MCH_NC2 TP_MCH_NC3 TP_MCH_NC4 TP_MCH_NC5 TP_MCH_NC6 TP_MCH_NC7 TP_MCH_NC8 TP_MCH_NC9 TP_MCH_NC10 TP_MCH_NC11 TP_MCH_NC12 TP_MCH_NC13 TP_MCH_NC14 TP_MCH_NC15 TP_MCH_NC16 T122 T123 T120 T118 T114 T117 T115 T121 T124 T126 T139 T127 T128 T137 T136 T119 SM_CK#_0 SM_CK#_1 SM_CK#_3 SM_CK#_4 [13] [13] [13] [13] R419 PM [16] PM_BMBUSY# [3,14,29] ICH_DPRSTP# [13] PM_EXTTS#0 [13] PM_EXTTS#1 3,16,29] DELAY_VR_PWRGOOD [15] PLTRST#_NB [3,14] PM_THRMTRIP# [16,29] PM_DPRSLPVR M_CLK_DDR0 M_CLK_DDR1 M_CLK_DDR3 M_CLK_DDR4 VGA [11] MCH_CFG_9 CFG T29 T19 T20 CFG_0 CFG_1 CFG_2 CFG_3 CFG_4 CFG_5 CFG_6 CFG_7 CFG_8 CFG_9 CFG_10 CFG_11 CFG_12 CFG_13 CFG_14 CFG_15 CFG_16 CFG_17 CFG_18 CFG_19 CFG_20 DMI T130 T134 [11] MCH_CFG_5 P27 N27 N24 C21 C23 F23 N23 G23 J20 C20 R24 L23 J23 E23 E20 K23 M20 M24 L32 N33 L35 MCH_CFG_3 MCH_CFG_4 GRAPHICS VID [2] MCH_BSEL0 [2] MCH_BSEL1 [2] MCH_BSEL2 RSVD20 RSVD21 RSVD22 RSVD23 RSVD24 RSVD25 RSVD26 RSVD27 RSVD28 RSVD29 RSVD30 RSVD31 RSVD32 RSVD33 RSVD34 RSVD35 RSVD36 RSVD37 RSVD38 RSVD39 RSVD40 RSVD41 RSVD42 RSVD43 RSVD44 RSVD45 AV29 BB23 BA25 AV23 TV MCH_RSVD34 MCH_RSVD35 MCH_RSVD36 MCH_RSVD37 MCH_RSVD38 MCH_RSVD39 MCH_RSVD40 MCH_RSVD41 MCH_RSVD42 MCH_RSVD43 MCH_RSVD44 MCH_RSVD45 T45 T44 T52 T141 T15 T132 T135 T142 T145 T129 T138 T131 C H10 B51 BJ20 BK22 BF19 BH20 BK18 BJ18 BF23 BG23 BC23 BD24 BJ29 BE24 BH39 AW20 BK20 C48 D47 B44 C44 A35 B37 B36 B34 C34 SM_CK_0 SM_CK_1 SM_CK_3 SM_CK_4 LVDS MCH_RSVD20 MCH_RSVD21 MCH_RSVD22 MCH_RSVD23 MCH_RSVD24 MCH_RSVD25 MCH_RSVD26 MCH_RSVD27 MCH_RSVD28 MCH_RSVD29 MCH_RSVD30 MCH_RSVD31 T18 T125 T112 T113 T47 T51 T116 T53 T49 T50 T48 T46 [12,13] M_A_A14 [12,13] M_B_A14 .1U_4 ME C41 +VCC_PEG U21C RSVD1 RSVD2 RSVD3 RSVD4 RSVD5 RSVD6 RSVD7 RSVD8 RSVD9 RSVD10 RSVD11 RSVD12 RSVD13 RSVD14 MISC D P36 P37 R35 N35 AR12 AR13 AM12 AN13 J12 AR37 AM36 AL36 AM37 D20 RSVD MCH_RSVD1 MCH_RSVD2 MCH_RSVD3 MCH_RSVD4 MCH_RSVD5 MCH_RSVD6 MCH_RSVD7 MCH_RSVD8 MCH_RSVD9 MCH_RSVD10 MCH_RSVD11 MCH_RSVD12 MCH_RSVD13 MCH_RSVD14 T30 T32 T31 T28 T40 T41 T36 T37 T22 T39 T38 T35 T34 T14 4 Quanta Computer Inc. 3 R103 C97 C98 1K_4 .01U_4 2.2U_6 2 PROJECT : BU1 Santa Rosa Size Document Number Date: Monday, March 26, 2007 Rev 1A GMCH DMI/VIDEO(2 of 7) Sheet 1 6 of 33 5 4 3 2 1 NB(Memory controller) B SA_CAS# BL17 SA_DM_0 SA_DM_1 SA_DM_2 SA_DM_3 SA_DM_4 SA_DM_5 SA_DM_6 SA_DM_7 AT45 BD44 BD42 AW38 AW13 BG8 AY5 AN6 M_A_DM0 M_A_DM1 M_A_DM2 M_A_DM3 M_A_DM4 M_A_DM5 M_A_DM6 M_A_DM7 SA_DQS_0 SA_DQS_1 SA_DQS_2 SA_DQS_3 SA_DQS_4 SA_DQS_5 SA_DQS_6 SA_DQS_7 SA_DQS#_0 SA_DQS#_1 SA_DQS#_2 SA_DQS#_3 SA_DQS#_4 SA_DQS#_5 SA_DQS#_6 SA_DQS#_7 AT46 BE48 BB43 BC37 BB16 BH6 BB2 AP3 AT47 BD47 BC41 BA37 BA16 BH7 BC1 AP2 M_A_DQS0 M_A_DQS1 M_A_DQS2 M_A_DQS3 M_A_DQS4 M_A_DQS5 M_A_DQS6 M_A_DQS7 M_A_DQS#0 M_A_DQS#1 M_A_DQS#2 M_A_DQS#3 M_A_DQS#4 M_A_DQS#5 M_A_DQS#6 M_A_DQS#7 SA_MA_0 SA_MA_1 SA_MA_2 SA_MA_3 SA_MA_4 SA_MA_5 SA_MA_6 SA_MA_7 SA_MA_8 SA_MA_9 SA_MA_10 SA_MA_11 SA_MA_12 SA_MA_13 BJ19 BD20 BK27 BH28 BL24 BK28 BJ27 BJ25 BL28 BA28 BC19 BE28 BG30 BJ16 M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 SA_RAS# SA_RCVEN# BE18 AY20 SA_WE# BA19 TP_SA_RCVEN# M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8 M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15 M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31 M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39 M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46 M_B_DQ47 M_B_DQ48 M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ55 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60 M_B_DQ61 M_B_DQ62 M_B_DQ63 [12,13] [12,13] [12,13] [12,13] M_A_DM[7:0] [13] M_A_DQS[7:0] [13] M_A_DQS#[7:0] [13] M_A_A[13:0] [12,13] T43 M_A_RAS# [12,13] M_A_WE# [12,13] CRESTLINE_1p0 U21E AP49 AR51 AW50 AW51 AN51 AN50 AV50 AV49 BA50 BB50 BA49 BE50 BA51 AY49 BF50 BF49 BJ50 BJ44 BJ43 BL43 BK47 BK49 BK43 BK42 BJ41 BL41 BJ37 BJ36 BK41 BJ40 BL35 BK37 BK13 BE11 BK11 BC11 BC13 BE12 BC12 BG12 BJ10 BL9 BK5 BL5 BK9 BK10 BJ8 BJ6 BF4 BH5 BG1 BC2 BK3 BE4 BD3 BJ2 BA3 BB3 AR1 AT3 AY2 AY3 AU2 AT2 SB_DQ_0 SB_DQ_1 SB_DQ_2 SB_DQ_3 SB_DQ_4 SB_DQ_5 SB_DQ_6 SB_DQ_7 SB_DQ_8 SB_DQ_9 SB_DQ_10 SB_DQ_11 SB_DQ_12 SB_DQ_13 SB_DQ_14 SB_DQ_15 SB_DQ_16 SB_DQ_17 SB_DQ_18 SB_DQ_19 SB_DQ_20 SB_DQ_21 SB_DQ_22 SB_DQ_23 SB_DQ_24 SB_DQ_25 SB_DQ_26 SB_DQ_27 SB_DQ_28 SB_DQ_29 SB_DQ_30 SB_DQ_31 SB_DQ_32 SB_DQ_33 SB_DQ_34 SB_DQ_35 SB_DQ_36 SB_DQ_37 SB_DQ_38 SB_DQ_39 SB_DQ_40 SB_DQ_41 SB_DQ_42 SB_DQ_43 SB_DQ_44 SB_DQ_45 SB_DQ_46 SB_DQ_47 SB_DQ_48 SB_DQ_49 SB_DQ_50 SB_DQ_51 SB_DQ_52 SB_DQ_53 SB_DQ_54 SB_DQ_55 SB_DQ_56 SB_DQ_57 SB_DQ_58 SB_DQ_59 SB_DQ_60 SB_DQ_61 SB_DQ_62 SB_DQ_63 SB_BS_0 SB_BS_1 SB_BS_2 B M_A_BS#0 M_A_BS#1 M_A_BS#2 M_A_CAS# MEMORY BB19 BK19 BF29 SYSTEM A SA_BS_0 SA_BS_1 SA_BS_2 MEMORY SA_DQ_0 SA_DQ_1 SA_DQ_2 SA_DQ_3 SA_DQ_4 SA_DQ_5 SA_DQ_6 SA_DQ_7 SA_DQ_8 SA_DQ_9 SA_DQ_10 SA_DQ_11 SA_DQ_12 SA_DQ_13 SA_DQ_14 SA_DQ_15 SA_DQ_16 SA_DQ_17 SA_DQ_18 SA_DQ_19 SA_DQ_20 SA_DQ_21 SA_DQ_22 SA_DQ_23 SA_DQ_24 SA_DQ_25 SA_DQ_26 SA_DQ_27 SA_DQ_28 SA_DQ_29 SA_DQ_30 SA_DQ_31 SA_DQ_32 SA_DQ_33 SA_DQ_34 SA_DQ_35 SA_DQ_36 SA_DQ_37 SA_DQ_38 SA_DQ_39 SA_DQ_40 SA_DQ_41 SA_DQ_42 SA_DQ_43 SA_DQ_44 SA_DQ_45 SA_DQ_46 SA_DQ_47 SA_DQ_48 SA_DQ_49 SA_DQ_50 SA_DQ_51 SA_DQ_52 SA_DQ_53 SA_DQ_54 SA_DQ_55 SA_DQ_56 SA_DQ_57 SA_DQ_58 SA_DQ_59 SA_DQ_60 SA_DQ_61 SA_DQ_62 SA_DQ_63 SYSTEM C [13] M_B_DQ[63:0] U21D AR43 AW44 BA45 AY46 AR41 AR45 AT42 AW47 BB45 BF48 BG47 BJ45 BB47 BG50 BH49 BE45 AW43 BE44 BG42 BE40 BF44 BH45 BG40 BF40 AR40 AW40 AT39 AW36 AW41 AY41 AV38 AT38 AV13 AT13 AW11 AV11 AU15 AT11 BA13 BA11 BE10 BD10 BD8 AY9 BG10 AW9 BD7 BB9 BB5 AY7 AT5 AT7 AY6 BB7 AR5 AR8 AR9 AN3 AM8 AN10 AT9 AN9 AM9 AN11 DDR M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63 DDR [13] M_A_DQ[63:0] D AY17 BG18 BG36 M_B_BS#0 M_B_BS#1 M_B_BS#2 M_B_CAS# SB_CAS# BE17 SB_DM_0 SB_DM_1 SB_DM_2 SB_DM_3 SB_DM_4 SB_DM_5 SB_DM_6 SB_DM_7 AR50 BD49 BK45 BL39 BH12 BJ7 BF3 AW2 M_B_DM0 M_B_DM1 M_B_DM2 M_B_DM3 M_B_DM4 M_B_DM5 M_B_DM6 M_B_DM7 SB_DQS_0 SB_DQS_1 SB_DQS_2 SB_DQS_3 SB_DQS_4 SB_DQS_5 SB_DQS_6 SB_DQS_7 SB_DQS#_0 SB_DQS#_1 SB_DQS#_2 SB_DQS#_3 SB_DQS#_4 SB_DQS#_5 SB_DQS#_6 SB_DQS#_7 AT50 BD50 BK46 BK39 BJ12 BL7 BE2 AV2 AU50 BC50 BL45 BK38 BK12 BK7 BF2 AV3 M_B_DQS0 M_B_DQS1 M_B_DQS2 M_B_DQS3 M_B_DQS4 M_B_DQS5 M_B_DQS6 M_B_DQS7 M_B_DQS#0 M_B_DQS#1 M_B_DQS#2 M_B_DQS#3 M_B_DQS#4 M_B_DQS#5 M_B_DQS#6 M_B_DQS#7 SB_MA_0 SB_MA_1 SB_MA_2 SB_MA_3 SB_MA_4 SB_MA_5 SB_MA_6 SB_MA_7 SB_MA_8 SB_MA_9 SB_MA_10 SB_MA_11 SB_MA_12 SB_MA_13 BC18 BG28 BG25 AW17 BF25 BE25 BA29 BC28 AY28 BD37 BG17 BE37 BA39 BG13 M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13 SB_RAS# SB_RCVEN# AV16 AY18 TP_SB_RCVEN# SB_WE# BC17 D [12,13] [12,13] [12,13] [12,13] M_B_DM[7:0] [13] M_B_DQS[7:0] [13] M_B_DQS#[7:0] [13] C M_B_A[13:0] [12,13] M_B_RAS# [12,13] T42 B M_B_WE# [12,13] CRESTLINE_1p0 A A Quanta Computer Inc. PROJECT : BU1 Santa Rosa Size Document Number Rev 1A MCH DDR(3 of 7) Date: 5 4 3 2 Monday, March 26, 2007 Sheet 1 7 of 33 5 4 3 2 +3V_VCCSYNC NB(Power-1) R61 10_4 +1.05V C89 C102 C108 .1U_4 22U_8 22U_8 POWER AU32 AU33 AU35 AV33 AW33 AW35 AY35 BA32 BA33 BA35 BB33 BC32 BC33 BC35 BD32 BD35 BE32 BE33 BE35 BF33 BF34 BG32 BG33 BG35 BH32 BH34 BH35 BJ32 BJ33 BJ34 BK32 BK33 BK34 BK35 BL33 AU30 C VCC_SM_1 VCC_SM_2 VCC_SM_3 VCC_SM_4 VCC_SM_5 VCC_SM_6 VCC_SM_7 VCC_SM_8 VCC_SM_9 VCC_SM_10 VCC_SM_11 VCC_SM_12 VCC_SM_13 VCC_SM_14 VCC_SM_15 VCC_SM_16 VCC_SM_17 VCC_SM_18 VCC_SM_19 VCC_SM_20 VCC_SM_21 VCC_SM_22 VCC_SM_23 VCC_SM_24 VCC_SM_25 VCC_SM_26 VCC_SM_27 VCC_SM_28 VCC_SM_29 VCC_SM_30 VCC_SM_31 VCC_SM_32 VCC_SM_33 VCC_SM_34 VCC_SM_35 VCC_SM_36 +1.05V A VCC_AXG_1 VCC_AXG_2 VCC_AXG_3 VCC_AXG_4 VCC_AXG_5 VCC_AXG_6 VCC_AXG_7 VCC_AXG_8 VCC_AXG_9 VCC_AXG_10 VCC_AXG_11 VCC_AXG_12 VCC_AXG_13 VCC_AXG_14 VCC_AXG_15 VCC_AXG_16 VCC_AXG_17 VCC_AXG_18 VCC_AXG_19 VCC_AXG_20 VCC_AXG_21 VCC_AXG_22 VCC_AXG_23 VCC_AXG_24 VCC_AXG_25 VCC_AXG_26 VCC_AXG_27 VCC_AXG_28 VCC_AXG_29 VCC_AXG_30 VCC_AXG_31 VCC_AXG_32 VCC_AXG_33 VCC_AXG_34 AW45 BC39 BE39 BD17 BD4 AW8 AT6 +1.05V + C423 330U_3528 C74 C59 C73 C63 22U_8 .22U_4 .22U_4 .1U_4 C81 C61 C57 C58 C76 C60 1U_6 10U_8 22U_8 .1U_4 .1U_4 +1.05V + C413 + C417 330U_3528 .47U_6 330U_3528 AB33 AB36 AB37 AC33 AC35 AC36 AD35 AD36 AF33 AF36 AH33 AH35 AH36 AH37 AJ33 AJ35 AK33 AK35 AK36 AK37 AD33 AJ36 AM35 AL33 AL35 AA33 AA35 AA36 AP35 AP36 AR35 AR36 Y32 Y33 Y35 Y36 Y37 T30 T34 T35 U29 U31 U32 U33 U35 U36 V32 V33 V36 V37 VCC_NCTF_1 VCC_NCTF_2 VCC_NCTF_3 VCC_NCTF_4 VCC_NCTF_5 VCC_NCTF_6 VCC_NCTF_7 VCC_NCTF_8 VCC_NCTF_9 VCC_NCTF_10 VCC_NCTF_11 VCC_NCTF_12 VCC_NCTF_13 VCC_NCTF_14 VCC_NCTF_15 VCC_NCTF_16 VCC_NCTF_17 VCC_NCTF_18 VCC_NCTF_19 VCC_NCTF_20 VCC_NCTF_21 VCC_NCTF_22 VCC_NCTF_23 VCC_NCTF_24 VCC_NCTF_25 VCC_NCTF_26 VCC_NCTF_27 VCC_NCTF_28 VCC_NCTF_29 VCC_NCTF_30 VCC_NCTF_31 VCC_NCTF_32 VCC_NCTF_33 VCC_NCTF_34 VCC_NCTF_35 VCC_NCTF_36 VCC_NCTF_37 VCC_NCTF_38 VCC_NCTF_39 VCC_NCTF_40 VCC_NCTF_41 VCC_NCTF_42 VCC_NCTF_43 VCC_NCTF_44 VCC_NCTF_45 VCC_NCTF_46 VCC_NCTF_47 VCC_NCTF_48 VCC_NCTF_49 VCC_NCTF_50 C66 C70 C71 C62 C69 C64 22U_8 .22U_4 .22U_4 .1U_4 .1U_4 .1U_4 D T27 T37 U24 U28 V31 V35 AA19 AB17 AB35 AD19 AD37 AF17 AF35 AK17 AM17 AM24 AP26 AP28 AR15 AR19 AR28 C POWER VCC_AXM_NCTF_1 VCC_AXM_NCTF_2 VCC_AXM_NCTF_3 VCC_AXM_NCTF_4 VCC_AXM_NCTF_5 VCC_AXM_NCTF_6 VCC_AXM_NCTF_7 VCC_AXM_NCTF_8 VCC_AXM_NCTF_9 VCC_AXM_NCTF_10 VCC_AXM_NCTF_11 VCC_AXM_NCTF_12 VCC_AXM_NCTF_13 VCC_AXM_NCTF_14 VCC_AXM_NCTF_15 VCC_AXM_NCTF_16 VCC_AXM_NCTF_17 VCC_AXM_NCTF_18 VCC_AXM_NCTF_19 VSS_SCB1 VSS_SCB2 VSS_SCB3 VSS_SCB4 VSS_SCB5 VSS_SCB6 A3 B2 C1 BL1 BL51 A51 +1.05V R89 +1.05V AL24 AL26 AL28 AM26 AM28 AM29 AM31 AM32 AM33 AP29 AP31 AP32 AP33 AL29 AL31 AL32 AR31 AR32 AR33 VSS_NCTF_1 VSS_NCTF_2 VSS_NCTF_3 VSS_NCTF_4 VSS_NCTF_5 VSS_NCTF_6 VSS_NCTF_7 VSS_NCTF_8 VSS_NCTF_9 VSS_NCTF_10 VSS_NCTF_11 VSS_NCTF_12 VSS_NCTF_13 VSS_NCTF_14 VSS_NCTF_15 VSS_NCTF_16 VSS_NCTF_17 VSS_NCTF_18 VSS_NCTF_19 VSS_NCTF_20 VSS_NCTF_21 VSS NCTF VCC_SM_LF1 VCC_SM_LF2 VCC_SM_LF3 VCC_SM_LF4 VCC_SM_LF5 VCC_SM_LF6 VCC_SM_LF7 VCC SM LF R20 T14 W13 W14 Y12 AA20 AA23 AA26 AA28 AB21 AB24 AB29 AC20 AC21 AC23 AC24 AC26 AC28 AC29 AD20 AD23 AD24 AD28 AF21 AF26 AA31 AH20 AH21 AH23 AH24 AH26 AD31 AJ20 AN14 VCC GFX B T17 T18 T19 T21 T22 T23 T25 U15 U16 U17 U19 U20 U21 U23 U26 V16 V17 V19 V20 V21 V23 V24 Y15 Y16 Y17 Y19 Y20 Y21 Y23 Y24 Y26 Y28 Y29 AA16 AA17 AB16 AB19 AC16 AC17 AC19 AD15 AD16 AD17 AF16 AF19 AH15 AH16 AH17 AH19 AJ16 AJ17 AJ19 AK16 AK19 AL16 AL17 AL19 AL20 AL21 AL23 AM15 AM16 AM19 AM20 AM21 AM23 AP15 AP16 AP17 AP19 AP20 AP21 AP23 AP24 AR20 AR21 AR23 AR24 AR26 V26 V28 V29 Y31 VSS SCB +1.8VSUS VCC_AXG_NCTF_1 VCC_AXG_NCTF_2 VCC_AXG_NCTF_3 VCC_AXG_NCTF_4 VCC_AXG_NCTF_5 VCC_AXG_NCTF_6 VCC_AXG_NCTF_7 VCC_AXG_NCTF_8 VCC_AXG_NCTF_9 VCC_AXG_NCTF_10 VCC_AXG_NCTF_11 VCC_AXG_NCTF_12 VCC_AXG_NCTF_13 VCC_AXG_NCTF_14 VCC_AXG_NCTF_15 VCC_AXG_NCTF_16 VCC_AXG_NCTF_17 VCC_AXG_NCTF_18 VCC_AXG_NCTF_19 VCC_AXG_NCTF_20 VCC_AXG_NCTF_21 VCC_AXG_NCTF_22 VCC_AXG_NCTF_23 VCC_AXG_NCTF_24 VCC_AXG_NCTF_25 VCC_AXG_NCTF_26 VCC_AXG_NCTF_27 VCC_AXG_NCTF_28 VCC_AXG_NCTF_29 VCC_AXG_NCTF_30 VCC_AXG_NCTF_31 VCC_AXG_NCTF_32 VCC_AXG_NCTF_33 VCC_AXG_NCTF_34 VCC_AXG_NCTF_35 VCC_AXG_NCTF_36 VCC_AXG_NCTF_37 VCC_AXG_NCTF_38 VCC_AXG_NCTF_39 VCC_AXG_NCTF_40 VCC_AXG_NCTF_41 VCC_AXG_NCTF_42 VCC_AXG_NCTF_43 VCC_AXG_NCTF_44 VCC_AXG_NCTF_45 VCC_AXG_NCTF_46 VCC_AXG_NCTF_47 VCC_AXG_NCTF_48 VCC_AXG_NCTF_49 VCC_AXG_NCTF_50 VCC_AXG_NCTF_51 VCC_AXG_NCTF_52 VCC_AXG_NCTF_53 VCC_AXG_NCTF_54 VCC_AXG_NCTF_55 VCC_AXG_NCTF_56 VCC_AXG_NCTF_57 VCC_AXG_NCTF_58 VCC_AXG_NCTF_59 VCC_AXG_NCTF_60 VCC_AXG_NCTF_61 VCC_AXG_NCTF_62 VCC_AXG_NCTF_63 VCC_AXG_NCTF_64 VCC_AXG_NCTF_65 VCC_AXG_NCTF_66 VCC_AXG_NCTF_67 VCC_AXG_NCTF_68 VCC_AXG_NCTF_69 VCC_AXG_NCTF_70 VCC_AXG_NCTF_71 VCC_AXG_NCTF_72 VCC_AXG_NCTF_73 VCC_AXG_NCTF_74 VCC_AXG_NCTF_75 VCC_AXG_NCTF_76 VCC_AXG_NCTF_77 VCC_AXG_NCTF_78 VCC_AXG_NCTF_79 VCC_AXG_NCTF_80 VCC_AXG_NCTF_81 VCC_AXG_NCTF_82 VCC_AXG_NCTF_83 VCC AXM VCC_13 PDZ5.6B 2 VCC NCTF +1.8VSUS R30 1 VCC_AXM_1 VCC_AXM_2 VCC_AXM_3 VCC_AXM_4 VCC_AXM_5 VCC_AXM_6 VCC_AXM_7 0_6 AT33 AT31 AK29 AK24 AK23 AJ26 AJ23 VCC AXM NCTF +1.05V_VCC_GMCH_VCC13 VCC GFX NCTF 0_4 VCC CORE R69 D4 U21F VCC SM D VCC_1 VCC_2 VCC_3 VCC_5 VCC_4 VCC_6 VCC_7 VCC_8 VCC_9 VCC_10 VCC_11 VCC_12 VCCGFPLLOW ADD 10ohm THEY ONLY USE IN UMA (GM OR GML) +1.05V U21G AT35 AT34 AH28 AC32 AC31 AK32 AJ31 AJ28 AH32 AH31 AH29 AF32 1 +1.05V B CRESTLINE_1p0 VCCSM_LF1 VCCSM_LF2 VCCSM_LF3 VCCSM_LF4 VCCSM_LF5 VCCSM_LF6 VCCSM_LF7 A C82 C84 C90 C88 C92 C86 C85 .1U_4 .1U_4 .22U_4 .22U_4 .47U_6 1U_6 1U_6 Quanta Computer Inc. PROJECT : BU1 Santa Rosa Size Rev 1A GMCH Power-1(4 of 7) CRESTLINE_1p0 5 Document Number Date: 4 3 2 Thursday, February 01, 2007 Sheet 1 8 of 33 5 4 NB(Power-2) +3V_VCCSYNC R33 +3V 'IND CHIP 10UH(20%,100MA,LB2012T100MR)' L1 +1.25V 3 + C451 +3V .1U_4 LVDS Disable/Enable guideline CRT/TV Disable/Enable guideline C45 Ball .1U_4 C39 470U_7343 1 External VGA with EV@part,Internal VGA with IV@ part 0_6 INT VGA disable VCCSYNC connect to GND 10UH_8 2 L29 PBY160808T-301Y-N_6 D C446 C430 C448 R421 *22U_8 .1U_4 22N_4 *0_4 If SDVO Disable LVDS Disable If SDVO enable LVDS Disable If SDVO enable LVDS enable Enable Disable Ball Enable Disable Signal VCCA_CRT 3.3V GND VCCA_C_TVO 3.3V GND VCCD_LVDS GND 1.8V 1.8V VCCD_CRT 1.5V GND VCCD_TVO 1.5V 1.5V VCCA_LVDS GND GND 1.8V VCCDQ_CRT 1.5V GND VCCABG_DAC 3.3V GND VCCTX_LVDS GND GND 1.8V VCCA_A_TVO 3.3V GND VSSABG_DAC GND GND VCCA_B_TVO 3.3V GND VCC_SYNC GND 3.3V EXTERNAL INTERNAL D +1.05V A30 VCCA_MPLL A41 VCCA_LVDS B41 VSSA_LVDS K50 VCCA_PEG_BG K49 VSSA_PEG_BG .1U_4 +3V_VCCA_PEG_BG 0_8 C48 .1U_4 R118 +1.25V_VCCD_PEG_PLL 0_6 +1.25VM_VCCA_SM C399 C103 C79 C110 C80 100U_3528 *22U_8 4.7U_6 22U_8 1U_6 + +1.25V R110 0_6 +3V_TV_DAC L28 PBY160808T-301Y-N_6 C105 C106 C107 C87 *1U_6 *1U_6 22U_8 .1U_4 +1.25VM_VCCA_SM_CK +3V C433 C447 R413 .1U_4 22N_4 *0_4 B C441 C444 R427 .1U_4 22N_4 *0_4 R60 *0_4 R31 0_6 +1.5V_VCCD_CRT +1.5V_VCCD_TVDAC +1.5V_VCCD_QDAC R92 +1.25V +1.25VM_MCH_VCCD_HPLL 0_6 C78 +1.25V_VCCD_PEG_PLL .1U_4 C445 C449 C439 C431 R423 22U_8 10U_8 .1U_4 22N_4 *0_4 VTT VCCA_HPLL AM2 1000P_4 R53 +3V V1.25M_MPLL_RC +1.25V AL2 +1.25VM_VCCA_MPLL C54 .1U_4 +1.25V L3 U51 VCCA_PEG_PLL AW18 AV19 AU19 AU18 AU17 VCCA_SM_1 VCCA_SM_2 VCCA_SM_3 VCCA_SM_4 VCCA_SM_5 AT22 AT21 AT19 AT18 AT17 AR17 AR16 VCCA_SM_7 VCCA_SM_8 VCCA_SM_9 VCCA_SM_10 VCCA_SM_11 VCCA_SM_NCTF_1 VCCA_SM_NCTF_2 BC29 BB29 VCCA_SM_CK_1 VCCA_SM_CK_2 POWER C25 B25 C27 B27 B28 A28 VCCA_TVA_DAC_1 VCCA_TVA_DAC_2 VCCA_TVB_DAC_1 VCCA_TVB_DAC_2 VCCA_TVC_DAC_1 VCCA_TVC_DAC_2 M32 L29 VCCD_CRT VCCD_TVDAC N28 VCCD_QDAC AN2 VCCD_HPLL U48 VCCD_PEG_PLL J41 H42 VCCD_LVDS_1 VCCD_LVDS_2 PBY160808T-301Y-N_6 CRESTLINE_1p0 R43 C55 1_8 .1U_4 VTT_1 VTT_2 VTT_3 VTT_4 VTT_5 VTT_6 VTT_7 VTT_8 VTT_9 VTT_10 VTT_11 VTT_12 VTT_13 VTT_14 VTT_15 VTT_16 VTT_17 VTT_18 VTT_19 VTT_20 VTT_21 VTT_22 AT23 AU28 AU24 AT29 AT25 AT30 VCC_AXD_NCTF AR29 VCC_AXF_1 VCC_AXF_2 VCC_AXF_3 VCC_DMI +1.05V U13 U12 U11 U9 U8 U7 U5 U3 U2 U1 T13 T11 T10 T9 T7 T6 T5 T3 T2 R3 R2 R1 VCC_AXD_1 VCC_AXD_2 VCC_AXD_3 VCC_AXD_4 VCC_AXD_5 VCC_AXD_6 B23 B21 A21 C51 C52 C56 4.7U_8 4.7U_8 2.2U_8 .47U_6 R93 C83 C77 1U_6 *22U_8 C443 C442 1U_6 10U_8 0_6 +1.25V 0_6 +1.25V .1U_4 +1.25V_VCC_AXF L5 C94 VCC_HV_1 VCC_HV_2 C40 B40 AH50 AH51 +1.25V C68 A43 VCC_RXR_DMI_1 VCC_RXR_DMI_2 0_6 C VCC_TX_LVDS AD51 W50 W51 V49 V50 330U_3528 R91 AJ50 +1.25V_VCC_DMI VCC_PEG_1 VCC_PEG_2 VCC_PEG_3 VCC_PEG_4 VCC_PEG_5 + C421 R424 BK24 +1.8VSUS_VCC_SM_CK BK23 BJ24 BJ23 VTTLF1 VTTLF2 VTTLF3 C53 +1.25V_AXD VCC_SM_CK_1 VCC_SM_CK_2 VCC_SM_CK_3 VCC_SM_CK_4 HV 22U_8 +1.25VM_VCCA_HPLL C435 C75 R403 0.5_6 VCCA_DPLLB +1.8VSUS_VCC_TX_LVDS PBY160808T-301Y-N_6 C H49 VTTLF .1U_4 VCCA_DPLLA +1.25V_VCCA_DPLLB AXD 22U_8 VSSA_DAC_BG B49 AXF C72 B32 +1.25V_VCCA_DPLLA SM CK L24 C410 VCCA_DAC_BG PEG 'EMI FILTER BKP1608HS181-T(180,1.5A)' L23 PBY160808T-301Y-N_6 C409 +3V_VCCA_DAC_BG DMI .1U_4 PLL *0_4 C44 470U_7343 A LVDS R425 22N_4 VCCA_CRT_DAC_1 VCCA_CRT_DAC_2 A PEG C438 .1U_4 A33 B33 A SM C429 VCCSYNC +3V_VCCA_CRT_DAC A CK 0_6 TV + C452 +1.25V R426 +3V_TV_DAC D TV/CRT 10UH_8 LVDS L2 +1.25V CRT U21H J32 1UH_8 C96 .1U_4 22U_8 R109 +1.8VSUS +V1.8_SMCK_RC 1_6 +1.8VSUS_VCC_TX_LVDS C119 22U_8 L27 C434 +3V_VCC_HV 1UH_8 +1.8VSUS + C450 1000P_4 220U_7343 +VCC_PEG B L22 A7 F2 AH1 C405 C65 C42 C437 .47U_4 .47U_4 .47U_4 91nH +1.05V + C400 10U_8 330U_3528 VCC_RXR_DMI and VCC_PEG connect to+1.05V +V1.25S_PEGPLL_FB C40 +1.5V R30 10U_8 0_6 A C47 C38 .1U_4 22N_4 +1.05V D26 2 1 PDZ5.6B +1.05V_SD A +3V_VCC_HV R420 +1.8VSUS R29 5 100/F_6 C50 C37 C49 .1U_4 22N_4 1U_6 0_6 +1.8V_VCCD_LVDS C46 C440 1U_6 *10U_8 R436 10_4 R433 +3V 0_4 4 3 Quanta Computer Inc. C453 +1.25V AND +1.25M shall be +1.5V for Calero Interposer .1U_4 2 PROJECT : BU1 Santa Rosa Size Document Number Date: Tuesday, February 06, 2007 Rev 1A GMCH Power-2(5 of 7) Sheet 1 9 of 33 5 4 3 2 1 NB(Power-3) U21I U21J A13 A15 A17 A24 AA21 AA24 AA29 AB20 AB23 AB26 AB28 AB31 AC10 AC13 AC3 AC39 AC43 AC47 AD1 AD21 AD26 AD29 AD3 AD41 AD45 AD49 AD5 AD50 AD8 AE10 AE14 AE6 AF20 AF23 AF24 AF31 AG2 AG38 AG43 AG47 AG50 AH3 AH40 AH41 AH7 AH9 AJ11 AJ13 AJ21 AJ24 AJ29 AJ32 AJ43 AJ45 AJ49 AK20 AK21 AK26 AK28 AK31 AK51 AL1 AM11 AM13 AM3 AM4 AM41 AM45 AN1 AN38 AN39 AN43 AN5 AN7 AP4 AP48 AP50 AR11 AR2 AR39 AR44 AR47 AR7 AT10 AT14 AT41 AT49 AU1 AU23 AU29 AU3 AU36 AU49 AU51 AV39 AV48 AW1 AW12 AW16 D C B A VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8 VSS_9 VSS_10 VSS_11 VSS_12 VSS_13 VSS_14 VSS_15 VSS_16 VSS_17 VSS_18 VSS_19 VSS_20 VSS_21 VSS_22 VSS_23 VSS_24 VSS_25 VSS_26 VSS_27 VSS_28 VSS_29 VSS_30 VSS_31 VSS_32 VSS_33 VSS_34 VSS_35 VSS_36 VSS_37 VSS_38 VSS_39 VSS_40 VSS_41 VSS_42 VSS_43 VSS_44 VSS_45 VSS_46 VSS_47 VSS_48 VSS_49 VSS_50 VSS_51 VSS_52 VSS_53 VSS_54 VSS_55 VSS_56 VSS_57 VSS_58 VSS_59 VSS_60 VSS_61 VSS_62 VSS_63 VSS_64 VSS_65 VSS_66 VSS_67 VSS_68 VSS_69 VSS_70 VSS_71 VSS_72 VSS_73 VSS_74 VSS_75 VSS_76 VSS_77 VSS_78 VSS_79 VSS_80 VSS_81 VSS_82 VSS_83 VSS_84 VSS_85 VSS_86 VSS_87 VSS_88 VSS_89 VSS_90 VSS_91 VSS_92 VSS_93 VSS_94 VSS_95 VSS_96 VSS_97 VSS_98 VSS_99 VSS VSS_100 VSS_101 VSS_102 VSS_103 VSS_104 VSS_105 VSS_106 VSS_107 VSS_108 VSS_109 VSS_110 VSS_111 VSS_112 VSS_113 VSS_114 VSS_115 VSS_116 VSS_117 VSS_118 VSS_119 VSS_120 VSS_121 VSS_122 VSS_123 VSS_124 VSS_125 VSS_126 VSS_127 VSS_128 VSS_129 VSS_130 VSS_131 VSS_132 VSS_133 VSS_134 VSS_135 VSS_136 VSS_137 VSS_138 VSS_139 VSS_140 VSS_141 VSS_142 VSS_143 VSS_144 VSS_145 VSS_146 VSS_147 VSS_148 VSS_149 VSS_150 VSS_151 VSS_152 VSS_153 VSS_154 VSS_155 VSS_156 VSS_157 VSS_158 VSS_159 VSS_160 VSS_161 VSS_162 VSS_163 VSS_164 VSS_165 VSS_166 VSS_167 VSS_168 VSS_169 VSS_170 VSS_171 VSS_172 VSS_173 VSS_174 VSS_175 VSS_176 VSS_177 VSS_178 VSS_179 VSS_180 VSS_181 VSS_182 VSS_183 VSS_184 VSS_185 VSS_186 VSS_187 VSS_188 VSS_189 VSS_190 VSS_191 VSS_192 VSS_193 VSS_194 VSS_195 VSS_196 VSS_197 VSS_198 AW24 AW29 AW32 AW5 AW7 AY10 AY24 AY37 AY42 AY43 AY45 AY47 AY50 B10 B20 B24 B29 B30 B35 B38 B43 B46 B5 B8 BA1 BA17 BA18 BA2 BA24 BB12 BB25 BB40 BB44 BB49 BB8 BC16 BC24 BC25 BC36 BC40 BC51 BD13 BD2 BD28 BD45 BD48 BD5 BE1 BE19 BE23 BE30 BE42 BE51 BE8 BF12 BF16 BF36 BG19 BG2 BG24 BG29 BG39 BG48 BG5 BG51 BH17 BH30 BH44 BH46 BH8 BJ11 BJ13 BJ38 BJ4 BJ42 BJ46 BK15 BK17 BK25 BK29 BK36 BK40 BK44 BK6 BK8 BL11 BL13 BL19 BL22 BL37 BL47 C12 C16 C19 C28 C29 C33 C36 C41 C46 C50 C7 D13 D24 D3 D32 D39 D45 D49 E10 E16 E24 E28 E32 E47 F19 F36 F4 F40 F50 G1 G13 G16 G19 G24 G28 G29 G33 G42 G45 G48 G8 H24 H28 H4 H45 J11 J16 J2 J24 J28 J33 J35 J39 VSS_199 VSS_200 VSS_201 VSS_202 VSS_203 VSS_204 VSS_205 VSS_206 VSS_207 VSS_208 VSS_209 VSS_210 VSS_211 VSS_212 VSS_213 VSS_214 VSS_215 VSS_216 VSS_217 VSS_218 VSS_219 VSS_220 VSS_221 VSS_222 VSS_223 VSS_224 VSS_225 VSS_226 VSS_227 VSS_228 VSS_229 VSS_230 VSS_231 VSS_232 VSS_233 VSS_234 VSS_235 VSS_236 VSS_237 VSS_238 VSS_239 VSS_240 VSS_241 VSS_242 VSS_243 K12 K47 K8 L1 L17 L20 L24 L28 L3 L33 L49 M28 M42 M46 M49 M5 M50 M9 N11 N14 N17 N29 N32 N36 N39 N44 N49 N7 P19 P2 P23 P3 P50 R49 T39 T43 T47 U41 U45 U50 V2 V3 VSS_245 VSS_246 VSS_247 VSS_248 VSS_249 VSS_250 VSS_251 VSS_252 VSS_253 VSS_254 VSS_255 VSS_256 VSS_257 VSS_258 VSS_259 VSS_260 VSS_261 VSS_262 VSS_263 VSS_264 VSS_265 VSS_266 VSS_267 VSS_268 VSS_269 VSS_270 VSS_271 VSS_272 VSS_273 VSS_274 VSS_275 VSS_276 VSS_277 VSS_278 VSS_279 VSS_280 VSS_281 VSS_282 VSS_283 VSS_284 VSS_285 VSS_286 VSS_287 VSS_288 VSS_289 VSS_290 VSS_291 VSS_292 VSS_293 VSS_294 VSS_295 VSS_296 VSS_297 VSS_298 VSS_299 VSS_300 VSS_301 VSS_302 VSS_303 VSS_304 VSS_305 W11 W39 W43 W47 W5 W7 Y13 Y2 Y41 Y45 Y49 Y5 Y50 Y11 P29 T29 T31 T33 R28 VSS_306 VSS_307 VSS_308 VSS_309 VSS_310 VSS_311 VSS_312 VSS_313 AA32 AB32 AD32 AF28 AF29 AT27 AV25 H50 D VSS_GMCH_T29 VSS_GMCH_T31 VSS_GMCH_T33 VSS_GMCH_R28 0_4 0_4 0_4 0_4 C VSS B CRESTLINE_1p0 A Quanta Computer Inc. CRESTLINE_1p0 5 R35 R27 R28 R63 PROJECT : BU1 Santa Rosa 4 3 2 Size Document Number Date: Thursday, February 01, 2007 Rev 1A GMCH Power-3(6 of 7) Sheet 1 10 of 33 5 4 3 2 1 Strap table All strap are sampled with respect to the leading edge of the GMCH Power OK(PWROK) Signal CFG[17:3] Have internal Pull-up CFG[18:19] Have internal Pull-down Any CFG signal strapping option not list below should be left NC Pin Pin Name Strap description Configuration CFG[2:0] FSB Frequency Select 010 = FSB 800MHz 011 = FSB 667MHz D C D CFG[4:3] Reserved CFG5 DMI X2 Select CFG6 Reserved CFG7 CPU Strap 0 = Reserved 1 = Mobile CPU(Default) CFG8 Low power PCI Express 0 = Normal mode 1 = Low Power mode CFG9 PCI Express Graphics Lane Reversal 0 = Reverse Lanes 1 = Normal operation(Default) CFG[11:10] Reserved CFG[13:12] XOR/ALLZ CFG[15:14] Reserved CFG16 FSB Dynamic ODT CFG[18:17] Reserved SDVO_CTRLDATA SDVO Present 0 = No SDVO Card present(Default) 1 = SDVO Card Present CFG19 DMI Lane Reversal 0 = Normal operation(Default) 1 = Reverse Lanes CFG20 SDVO/PCIe concurrent 0 = Only SDVO or PCIE x1 is operation(Default) 1 = SDVO and PCIE x1 are operating simultaneously via the PEG port 0 = DMI X2 1 = DMI X4(Default) 00 01 10 11 = = = = C Reserved XOR Mode Enable All-Z Mode Enabled Normal operation(Default) 0 = Dynamic ODT disable 1 = Dynamic ODT Enable(Default) B B DMI X2 Select MCH_CFG_5 DMI Lane Reversal Low = DMIX2 High = IDMIX4(Default) MCH_CFG_19 XOR /ALLz /Clock Un-gating Low = Normal operation(Default) High = Reverse Lane MCH_CFG_12MCH_CFG_13 PCI Express Graphics Configuration 0 0 0 1 1 0 ALL-z Mode Enable 1 1 Normal operation(Default) MCH_CFG_9 R51 [6] MCH_CFG_9 XOR Mode Enable R47 R36 *4.02K_4 *4.02K_4 Strap define at External DVI control page Clock gating disable +3V [6] MCH_CFG_5 SDVO Present Low = Reverse Lane High = Normal operation(Default) *4.02K_4 [6] MCH_CFG_19 FSB Dynamic ODT MCH_CFG_16 A SDVO/PCIE Concurrent operation Low = ODT Disable High = ODT Enable(Default) MCH_CFG_20 Low = Only SDVO or PCIE X1 is operational(Default) High = SDVO andPCIE X1 are operating simultaneously via the PEG port [6] MCH_CFG_12 [6] MCH_CFG_13 [6] MCH_CFG_16 A +3V R58 *4.02K_4 R430 R48 R54 *4.02K_4 *4.02K_4 Quanta Computer Inc. *4.02K_4 PROJECT : BU1 Santa Rosa Size Document Number Date: Monday, March 26, 2007 [6] MCH_CFG_20 5 4 3 2 Rev 1A GMCH Strap(7 of 7) Sheet 1 11 of 33 1 2 3 4 5 6 7 8 DDR2 Dual channel A/B PU A A M_A_A[13..0] M_A_A[13..0] [7,13] M_B_A[13..0] M_B_A[13..0] [7,13] DDRII A CHANNEL SMDDR_VTERM DDRII B CHANNEL SMDDR_VTERM C176 C145 C143 C148 C195 C146 C230 C201 C228 C227 C142 C173 C200 C174 C172 C177 C175 C231 C196 C197 .1U_4 .1U_4 .1U_4 .1U_4 .1U_4 .1U_4 .1U_4 .1U_4 .1U_4 .1U_4 .1U_4 .1U_4 .1U_4 .1U_4 .1U_4 .1U_4 .1U_4 .1U_4 .1U_4 .1U_4 C199 .1U_4 C171 C144 C226 C147 C225 .1U_4 .1U_4 .1U_4 .1U_4 .1U_4 Place one cap close to every 2 pull-up resistor terminated to SMDDR_VTERM B B M_A_A3 M_A_A1 RP16 1 3 2 56X2 4 M_A_A9 M_A_A5 RP18 1 3 2 56X2 4 M_A_A2 M_A_A4 RP21 1 3 2 56X2 4 [6,13] M_CKE3 [7,13] M_B_BS#2 M_A_A11 RP23 1 3 2 56X2 4 [6,13] M_ODT1 [6,13] M_CS#1 RP19 1 3 2 56X2 4 1 3 2 56X2 4 1 3 2 56X2 4 [6,13] M_CKE1 [6,13] M_CKE0 M_A_A8 M_A_A12 RP20 [7,13] M_A_BS#2 SMDDR_VTERM M_A_A7 M_A_A6 [6,13] M_ODT3 [7,13] M_B_BS#0 M_A_A10 RP22 1 3 2 56X2 4 RP32 1 3 2 56X2 4 RP14 1 3 2 56X2 4 RP33 1 3 2 56X2 4 RP17 1 3 2 56X2 4 RP15 1 3 2 56X2 4 RP26 1 3 2 56X2 4 RP29 1 3 2 56X2 4 RP39 1 3 2 56X2 4 RP37 1 3 2 56X2 4 RP24 1 3 2 56X2 4 RP36 1 3 2 56X2 4 [7,13] M_A_BS#0 [7,13] M_A_BS#1 RP25 M_A_A0 [7,13] M_A_CAS# [7,13] M_A_WE# SMDDR_VTERM C C [6,13] M_CS#0 [7,13] M_A_RAS# M_B_A10 RP30 [7,13] M_B_WE# M_B_A3 M_B_A1 RP31 1 3 2 56X2 4 1 3 2 56X2 4 SMDDR_VTERM [7,13] M_B_CAS# [6,13] M_CS#3 M_B_A6 [6,13] M_CKE4 [7,13] M_B_BS#1 RP38 M_B_A0 M_B_A7 M_B_A11 RP35 M_B_A8 M_B_A5 RP27 1 3 2 56X2 4 1 3 2 56X2 4 1 3 2 56X2 4 [6,13] M_ODT2 [7,13] M_B_RAS# [6,13] M_ODT0 M_A_A13 M_B_A13 [6,13] M_CS#2 D M_B_A2 M_B_A4 RP34 1 3 2 56X2 4 M_B_A9 M_B_A12 RP28 1 3 2 56X2 4 D INTEL FAE (08/17) ADD MA14 FOR DUAL LAYERS RAM R199 R219 [6,13] M_A_A14 [6,13] M_B_A14 56_4 56_4 Quanta Computer Inc. SMDDR_VTERM PROJECT : BU1 Santa Rosa Size Document Number Rev 1A DDR RES. ARRAY Date: 1 2 3 4 5 6 Monday, March 26, 2007 7 Sheet 12 8 of 33 +1.8VSUS +1.8VSUS CN30 M_A_DQS#0 M_A_DQS0 M_A_DQ2 M_A_DQ3 A M_A_DQ9 M_A_DQ8 M_A_DQS#1 M_A_DQS1 M_A_DQ14 M_A_DQ11 M_A_DQ17 M_A_DQ20 M_A_DQS#2 M_A_DQS2 M_A_DQ23 M_A_DQ19 M_A_DQ28 M_A_DQ25 M_A_DM3 M_A_DQ26 M_A_DQ27 B [6,12] M_CKE0 [7,12] M_A_BS#2 M_A_A12 M_A_A9 M_A_A8 M_A_A5 M_A_A3 M_A_A1 M_A_A10 [7,12] M_A_BS#0 [7,12] M_A_WE# [7,12] M_A_CAS# [6,12] M_CS#1 [6,12] M_ODT1 M_A_DQ36 M_A_DQ37 M_A_DQS#4 M_A_DQS4 M_A_DQ39 M_A_DQ34 M_A_DQ40 M_A_DQ41 C M_A_DM5 M_A_DQ42 M_A_DQ46 M_A_DQ53 M_A_DQ49 M_A_DQS#6 M_A_DQS6 M_A_DQ50 M_A_DQ51 M_A_DQ56 M_A_DQ60 M_A_DM7 M_A_DQ62 M_A_DQ63 DDRDAT_SMB DDRCLK_SMB +3V +3V 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 VREF VSS47 DQ0 DQ1 VSS37 DQS#0 DQS0 VSS48 DQ2 DQ3 VSS38 DQ8 DQ9 VSS49 DQS#1 DQS1 VSS39 DQ10 DQ11 VSS50 VSS46 DQ4 DQ5 VSS15 DM0 VSS5 DQ6 DQ7 VSS16 DQ12 DQ13 VSS17 DM1 VSS53 CK0 CK0# VSS41 DQ14 DQ15 VSS54 PC4800 DDR2 SDRAM SO-DIMM (200P) M_A_DQ6 M_A_DQ5 VSS18 DQ16 DQ17 VSS1 DQS#2 DQS2 VSS19 DQ18 DQ19 VSS22 DQ24 DQ25 VSS23 DM3 NC4 VSS9 DQ26 DQ27 VSS4 CKE0 VDD7 NC1 A16_BA2 VDD9 A12 A9 A8 VDD5 A5 A3 A1 VDD10 A10/AP BA0 WE# VDD2 CAS# S1# VDD3 ODT1 VSS11 DQ32 DQ33 VSS26 DQS#4 DQS4 VSS2 DQ34 DQ35 VSS27 DQ40 DQ41 VSS29 DM5 VSS51 DQ42 DQ43 VSS40 DQ48 DQ49 VSS52 NCTEST VSS30 DQS#6 DQS6 VSS31 DQ50 DQ51 VSS33 DQ56 DQ57 VSS3 DM7 VSS34 DQ58 DQ59 VSS14 SDA SCL VDD(SPD) VSS20 DQ20 DQ21 VSS6 NC3 DM2 VSS21 DQ22 DQ23 VSS24 DQ28 DQ29 VSS25 DQS#3 DQS3 VSS10 DQ30 DQ31 VSS8 CKE1 VDD8 A15 A14 VDD11 A11 A7 A6 VDD4 A4 A2 A0 VDD12 BA1 RAS# S0# VDD1 ODT0 A13 VDD6 NC2 VSS12 DQ36 DQ37 VSS28 DM4 VSS42 DQ38 DQ39 VSS55 DQ44 DQ45 VSS43 DQS#5 DQS5 VSS56 DQ46 DQ47 VSS44 DQ52 DQ53 VSS57 CK1 CK1# VSS45 DM6 VSS32 DQ54 DQ55 VSS35 DQ60 DQ61 VSS7 DQS#7 DQS7 VSS36 DQ62 DQ63 VSS13 SA0 SA1 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 TYCO_1-1734071-1 D 4 5 +1.8VSUS M_B_DQ0 M_B_DQ5 M_A_DM0 M_B_DQS#0 M_B_DQS0 M_A_DQ7 M_A_DQ1 M_B_DQ7 M_B_DQ3 M_A_DQ13 M_A_DQ12 M_B_DQ9 M_B_DQ8 M_A_DM1 M_B_DQS#1 M_B_DQS1 M_CLK_DDR0 [6] M_CLK_DDR#0 [6] M_B_DQ11 M_B_DQ10 M_A_DQ10 M_A_DQ15 M_B_DQ20 M_B_DQ17 M_A_DQ16 M_A_DQ21 M_B_DQS#2 M_B_DQS2 PM_EXTTS#0 [6] M_B_DQ22 M_B_DQ23 M_A_DQ18 M_A_DQ22 M_B_DQ29 M_B_DQ28 M_A_DQ29 M_A_DQ24 M_B_DM3 M_A_DQS#3 M_A_DQS3 M_B_DQ26 M_B_DQ27 M_A_DQ30 M_A_DQ31 [6,12] M_CKE3 M_CKE1 [6,12] [7,12] M_B_BS#2 M_A_A14 [6,12] M_A_A11 M_A_A7 M_A_A6 M_B_A12 M_B_A9 M_B_A8 INTEL FAE (08/17) ADD MA14 FOR DUAL LAYERS RAM M_B_A5 M_B_A3 M_B_A1 M_A_A4 M_A_A2 M_A_A0 M_B_A10 M_A_BS#1 [7,12] M_A_RAS# [7,12] M_CS#0 [6,12] M_ODT0 [6,12] M_A_A13 [7,12] M_B_BS#0 [7,12] M_B_WE# [7,12] M_B_CAS# [6,12] M_CS#3 [6,12] M_ODT3 M_B_DQ37 M_B_DQ38 M_A_DQ32 M_A_DQ33 M_A_DM4 M_B_DQS#4 M_B_DQS4 M_A_DQ35 M_A_DQ38 M_B_DQ34 M_B_DQ35 M_A_DQ44 M_A_DQ45 M_B_DQ40 M_B_DQ41 M_A_DQS#5 M_A_DQS5 M_B_DM5 M_B_DQ46 M_B_DQ43 M_A_DQ43 M_A_DQ47 M_B_DQ53 M_B_DQ49 M_A_DQ48 M_A_DQ52 M_CLK_DDR1 [6] M_CLK_DDR#1 [6] M_B_DQS#6 M_B_DQS6 M_A_DM6 M_B_DQ51 M_B_DQ54 M_A_DQ54 M_A_DQ55 M_B_DQ56 M_B_DQ57 M_A_DQ61 M_A_DQ57 M_B_DM7 M_A_DQS#7 M_A_DQS7 M_B_DQ59 M_B_DQ62 M_A_DQ58 M_A_DQ59 R202 R201 +1.8VSUS DDRDAT_SMB DDRCLK_SMB +3V 10K_4 10K_4 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 VREF VSS47 DQ0 DQ1 VSS37 DQS#0 DQS0 VSS48 DQ2 DQ3 VSS38 DQ8 DQ9 VSS49 DQS#1 DQS1 VSS39 DQ10 DQ11 VSS50 VSS18 DQ16 DQ17 VSS1 DQS#2 DQS2 VSS19 DQ18 DQ19 VSS22 DQ24 DQ25 VSS23 DM3 NC4 VSS9 DQ26 DQ27 VSS4 CKE0 VDD7 NC1 A16_BA2 VDD9 A12 A9 A8 VDD5 A5 A3 A1 VDD10 A10/AP BA0 WE# VDD2 CAS# S1# VDD3 ODT1 VSS11 DQ32 DQ33 VSS26 DQS#4 DQS4 VSS2 DQ34 DQ35 VSS27 DQ40 DQ41 VSS29 DM5 VSS51 DQ42 DQ43 VSS40 DQ48 DQ49 VSS52 NCTEST VSS30 DQS#6 DQS6 VSS31 DQ50 DQ51 VSS33 DQ56 DQ57 VSS3 DM7 VSS34 DQ58 DQ59 VSS14 SDA SCL VDD(SPD) VSS46 DQ4 DQ5 VSS15 DM0 VSS5 DQ6 DQ7 VSS16 DQ12 DQ13 VSS17 DM1 VSS53 CK0 CK0# VSS41 DQ14 DQ15 VSS54 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 VSS20 DQ20 DQ21 VSS6 NC3 DM2 VSS21 DQ22 DQ23 VSS24 DQ28 DQ29 VSS25 DQS#3 DQS3 VSS10 DQ30 DQ31 VSS8 CKE1 VDD8 A15 A14 VDD11 A11 A7 A6 VDD4 A4 A2 A0 VDD12 BA1 RAS# S0# VDD1 ODT0 A13 VDD6 NC2 VSS12 DQ36 DQ37 VSS28 DM4 VSS42 DQ38 DQ39 VSS55 DQ44 DQ45 VSS43 DQS#5 DQS5 VSS56 DQ46 DQ47 VSS44 DQ52 DQ53 VSS57 CK1 CK1# VSS45 DM6 VSS32 DQ54 DQ55 VSS35 DQ60 DQ61 VSS7 DQS#7 DQS7 VSS36 DQ62 DQ63 VSS13 SA0 SA1 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 TYCO_292564-4 7 M_B_DM[0..7] [7] M_B_DQ[0..63] [7] M_B_DQS[0..7] [7] M_B_DQS#[0..7] [7] M_B_A[0..13] [7,12] CN25 M_A_DQ4 M_A_DQ0 M_A_DM2 6 SMDDR_VREF_DIMM M_A_DM[0..7] [7] M_A_DQ[0..63] [7] M_A_DQS[0..7] [7] M_A_DQS#[0..7] [7] M_A_A[0..13] [7,12] 8 +1.8VSUS M_B_DQ4 M_B_DQ1 + C370 330U_3528 2.2U_6 M_B_DQ2 M_B_DQ6 C379 C367 C368 C380 2.2U_6 2.2U_6 2.2U_6 2.2U_6 M_B_DQ12 M_B_DQ13 A M_B_DM1 +1.8VSUS M_CLK_DDR3 [6] M_CLK_DDR#3 [6] M_B_DQ14 M_B_DQ15 +3V SMDDR_VREF_DIMM C185 C183 C369 C182 C202 C198 C141 C150 .1U_4 .1U_4 .1U_4 .1U_4 .1U_4 2.2U_6 2.2U_6 .1U_4 C365 C377 C366 C378 2.2U_6 2.2U_6 2.2U_6 2.2U_6 M_B_DQ16 M_B_DQ21 PM_EXTTS#1 [6] M_B_DM2 Close to DIMM0 M_B_DQ18 M_B_DQ19 M_B_DQ24 M_B_DQ25 +1.8VSUS M_B_DQS#3 M_B_DQS3 M_B_DQ30 M_B_DQ31 + C364 C375 330U_3528 M_CKE4 [6,12] 2.2U_6 B M_B_A14 [6,12] M_B_A11 M_B_A7 M_B_A6 INTEL FAE (08/17) ADD MA14 FOR DUAL LAYERS RAM +1.8VSUS M_B_A4 M_B_A2 M_B_A0 M_B_BS#1 [7,12] M_B_RAS# [7,12] M_CS#2 [6,12] SMDDR_VREF_DIMM +3V C184 C187 C181 C186 C149 C140 C193 C194 .1U_4 .1U_4 .1U_4 .1U_4 .1U_4 2.2U_6 2.2U_6 .1U_4 M_ODT2 [6,12] M_B_A13 Close to DIMM1 M_B_DQ32 M_B_DQ36 M_B_DM4 M_B_DQ39 M_B_DQ33 +3V M_B_DQ44 M_B_DQ45 M_B_DQS#5 M_B_DQS5 M_B_DQ42 M_B_DQ47 [2,16,19,23,24] Q9 R225 R224 RHU002N06 10K_4 10K_4 3 SDATA C DDRDAT_SMB 1 M_B_DQ52 M_B_DQ48 +3V M_CLK_DDR4 [6] M_CLK_DDR#4 [6] Q8 M_B_DM6 M_B_DQ55 M_B_DQ50 [2,16,19,23,24] RHU002N06 3 SCLK DDRCLK_SMB 1 M_B_DQ60 M_B_DQ61 M_B_DQS#7 M_B_DQS7 M_B_DQ63 M_B_DQ58 R217 R216 SMDDR_VREF_DIMM 10K_4 10K_4 +3V SO-DIMM0 SPD Address is 0xA0 SO-DIMM0 TS Address is 0x30 C376 M_B_DM0 2 3 2 2 PC4800 DDR2 SDRAM SO-DIMM (200P) 1 DDR2 Dual channel A/B CONN SMDDR_VREF_DIMM SO-DIMM1 SPD Address is 0xA4 SO-DIMM1 TS Address is 0x34 R209 *10K_4 R208 0_6 R117 *10K_4 SMDDR_VREF +1.8VSUS D H: 10.1mm H: 5.6mm CLOCK 0,1 CLOCK 3,4 CKE 0,1 CKE 2,3 Quanta Computer Inc. PROJECT : BU1 Santa Rosa 1 2 3 4 5 6 Size Document Number Date: Monday, March 26, 2007 Rev 3A DDR SO-DIMM(200P) 7 Sheet 13 8 of 33 5 RTC 4 3 Delay 18~25ms 20K_6 C383 15P_4 G1 2 1M_6 C237 1U_6 Y4 R375 32.768KHZ 10M_6 *SHORT_PAD C386 CN24 1 1 2 2 15P_4 U16A CLK_32KX1 CLK_32KX2 AG25 AF24 RTCX1 RTCX2 RTCRST# AF23 RTCRST# SM_INTRUDER# AD22 ACS_85204-0200L CMOS Setting Clear CMOS Keep CMOS ICH_INTVRMEN LAN100_SLP G1 Short Open +5VPCU 8.66K/F_4 VCCRTC_1 R240 R248 8.66K/F_4 VCCRTC_2 3 Q10 4.7K_4 R222 +1.5V_PCIE 1 *24.9_4 GLAN_COMP_SB ACZ_BCLK ACZ_SYNC MMBT3904 GLAN_CLK D22 LAN_RSTSYNC C21 B21 C22 LAN_RXD0 LAN_RXD1 LAN_RXD2 D21 E20 C20 LAN_TXD0 LAN_TXD1 LAN_TXD2 AJ16 AJ15 ACZ_SDOUT AE13 HDA_SDOUT AE10 AG14 HDA_DOCK_EN#/GPIO33 HDA_DOCK_RST#/GPIO34 AF10 SATALED# AF6 AF5 AH5 AH6 SATA0RXN SATA0RXP SATA0TXN SATA0TXP AG3 AG4 AJ4 AJ3 SATA1RXN SATA1RXP SATA1TXN SATA1TXP AF2 AF1 AE4 AE3 SATA2RXN SATA2RXP SATA2TXN SATA2TXP [2] CLK_PCIE_SATA# [2] CLK_PCIE_SATA AB7 AC6 SATA_CLKN SATA_CLKP R139 AG1 AG2 SATARBIAS# SATARBIAS R480 *10K_4 T109 T58 C136 C138 C135 C132 SATA_RXN0 SATA_RXP0 SATA_TXN0 SATA_TXP0 3900P_4 3900P_4 3900P_4 3900P_4 SATA_LED# SATA_RXN0_C SATA_RXP0_C SATA_TXN0_C SATA_TXP0_C SATA Disable 24.9_4 SATA_BIAS L<500mils SB Strap ICH8-M Internal VR Enable strap (Internal VR for Vccsus1_05,VccSus1_5 and VccCL1_5) Low = Internal VR disable High = Internal VR enable(Default) ICH8-M LAN100_SLP Strap (Internal VR for VccLAN1_05 and VccCL1.05) LAN100_SLP Low = Internal VR disable High = Internal VR enable(Default) E5 F5 G8 F6 LAD0 LAD1 LAD2 LAD3 +1.05V_V_CPU_IO C4 LFRAME# [23,26] LDRQ0# LDRQ1#/GPIO23 G9 E6 T68 LDRQ#1 [23] LDRQ#1 A20GATE A20M# AF13 AG26 GATEA20 DPRSTP# DPSLP# AF26 AE26 H_DPRSTP#_R H_DPSLP#_R FERR# AD24 CPUPWRGD/GPIO49 AG29 HDA_RST# [23,26] [23,26] [23,26] [23,26] FWH4/LFRAME# AF27 INIT# INTR RCIN# AE24 AC20 AH14 RCIN# NMI SMI# AD23 AG28 H_SMI#_R STPCLK# AA24 THRMTRIP# AE27 H_THERMTRIP_R TP8 AA23 ICH_TP8 DD0 DD1 DD2 DD3 DD4 DD5 DD6 DD7 DD8 DD9 DD10 DD11 DD12 DD13 DD14 DD15 V1 U2 V3 T1 V4 T5 AB2 T6 T3 R2 T4 V6 V5 U1 V2 U6 PDD0 PDD1 PDD2 PDD3 PDD4 PDD5 PDD6 PDD7 PDD8 PDD9 PDD10 PDD11 PDD12 PDD13 PDD14 PDD15 DA0 DA1 DA2 AA4 AA1 AB3 PDA0 PDA1 PDA2 DCS1# DCS3# Y6 Y5 DIOR# DIOW# DDACK# IDEIRQ IORDY DDREQ W4 W3 Y2 Y3 Y1 W5 GATEA20 [26] H_A20M# [3] R161 R169 R153 0_4 H_PWRGD [3] H_INIT# [3] H_INTR [3] RCIN# [26] R154 +1.05V_V_CPU_IO H_NMI [3] H_SMI# [3] 0_4 R203 T63 24_6 R206 56.2_4 Placement close SB L<2" R205 *0_4 PM_THRMTRIP# [3,6] C PDD[15:0] [19] +3V 0810 UR FAE: RCIN# DOESN'T NEED PU +3V R131 R379 10K_4 8.2K_4 RCIN# GATEA20 PDA[2:0] [19] PDCS1# [19] PDCS3# [19] PDIOR# [19] PDIOW# [19] PDDACK# [19] IRQ14 [19] PDIORDY [19] PDDREQ [19] B HDA ACZ_SDOUT ICH_RSV0 HDA_SDOUT Description 0 0 0 1 1 0 Normal opration(Default) 1 1 Set PCIE port config bit 1 R392 33_4 R393 33_4 R130 33_4 R129 33_4 ACZ_SDOUT_AUDIO ACZ_SYNC Enter XOR Chain R364 R365 R394 *1K_6 R172 R167 [24] ACZ_SDOUT_MDC [25] RSVD +3V R147 332K_6 ACZ_SYNC_AUDIO ACZ_SYNC_MDC 33_4 [24] [25] BIT_CLK_AUDIO [24] 33_4 BIT_CLK_MDC [25] 33_4 ACZ_RST#_AUDIO [24] 33_4 A ACZ_RST#_MDC [25] ACZ_SDOUT ICH_TP3 [16] Quanta Computer Inc. R150 *0_4 4 ICH_DPRSTP# [3,6,29] H_DPSLP# [3] H_STPCLK# [3] XOR Chain Entrance Strap LAN100_SLP 5 R175 56.2_4 ACZ_RST# R162 *0_4 *56.2_4 H_IGNNE# [3] A ICH_INTVRMEN R164 *56.2_4 ICH8M REV 1.0 VCCRTC R149 332K_6 R165 0_4 0_4 ACZ_BCLK VCCRTC +1.05V_V_CPU_IO H_FERR# [3] H_PWRGD_R IGNNE# HDA_BIT_CLK HDA_SYNC HDA_SDIN0 HDA_SDIN1 HDA_SDIN2 HDA_SDIN3 [25] SATA_LED# 1.Connect to GND: SATA[2:0]RXp/n , SATARBIAS , SATARBIAS# , SATA_CLKP , SATACLKN 2.NC: SATA[2:0]TXp/n , SATALED# 3.VccSATAPLL should be connected directly to Vcc1_5,Filter cap are not required 4.BIOS disable GLAN_COMPI GLAN_COMPO ACZ_SDIN2 ACZ_SDIN3 T56 T54 [19] [19] [19] [19] D25 C25 AJ17 AH17 AH15 AD13 +3V 15K_4 GLAN_DOCK#/GPIO13 AE14 R247 INTVRMEN B24 ACZ_RST# [24] ACZ_SDIN0 [25] ACZ_SDIN1 B INTVRMEN LAN100_SLP AH21 2 R245 INTRUDER# AF25 AD21 VCCRTC_3 D FWH0/LAD0 FWH1/LAD1 FWH2/LAD2 FWH3/LAD3 RTC LPC R226 1K_4 LAN / GLAN CPU R246 IHDA R232 1U_6 IDE CH500H-40 C247 SATA D12 VCCRTC 1 CH500H-40 2 D11 1 VCCRTC_4 C 1 VCCRTC +3VPCU D 2 R361 *1K_4 3 PROJECT : BU1 Santa Rosa 2 Size Document Number Date: Tuesday, March 27, 2007 Rev 2A ICH8M HOST(1 of 4) Sheet 1 14 of 33 5 4 3 2 1 SB-PCIE/USB/DMI U16D D To 3G To New Card PCIE_RXN1 PCIE_RXP1 PCIE_TXN1 PCIE_TXP1 [20] [20] [20] [20] PCIE_RXN4 PCIE_RXP4 PCIE_TXN4 PCIE_TXP4 [23] [23] [23] [23] PCIE_RXN3 PCIE_RXP3 PCIE_TXN3 PCIE_TXP3 [24] [24] [24] [24] PCIE_RXN2 PCIE_RXP2 PCIE_TXN2 PCIE_TXP2 C204 C192 C222 C219 C214 C209 C229 C234 PCIE_TXN1_C PCIE_TXP1_C P27 P26 N29 N28 PERN1 PERP1 PETN1 PETP1 PCIE_TXN4_C PCIE_TXP4_C M27 M26 L29 L28 PERN2 PERP2 PETN2 PETP2 PCIE_TXN3_C PCIE_TXP3_C K27 K26 J29 J28 PERN3 PERP3 PETN3 PETP3 PCIE_TXN2_C PCIE_TXP2_C H27 H26 G29 G28 PERN4 PERP4 PETN4 PETP4 T71 T69 T103 T102 F27 F26 E29 E28 PERN5 PERP5 PETN5 PETP5 T76 T72 T78 T74 D27 D26 C29 C28 PERN6/GLAN_RXN PERP6/GLAN_RXP PETN6/GLAN_TXN PETP6/GLAN_TXP T77 T101 T75 C23 B23 E22 SPI_CLK SPI_CS0# SPI_CS1# D23 F21 SPI_MOSI SPI_MISO .1U_4 .1U_4 .1U_4 .1U_4 .1U_4 .1U_4 .1U_4 .1U_4 SPI_CS1# T73 T70 USBOC#0 USBOC#1 USBOC#2 USBOC#3 USBOC#4 USBOC#5 USBOC#6 USBOC#7 USBOC#8 USBOC#9 C AJ19 AG16 AG15 AE15 AF15 AG17 AD12 AJ18 AD14 AH18 DMI0RXN DMI0RXP DMI0TXN DMI0TXP V27 V26 U29 U28 DMI_RXN0 DMI_RXP0 DMI_TXN0 DMI_TXP0 [6] [6] [6] [6] DMI1RXN DMI1RXP DMI1TXN DMI1TXP Y27 Y26 W29 W28 DMI_RXN1 DMI_RXP1 DMI_TXN1 DMI_TXP1 [6] [6] [6] [6] DMI2RXN DMI2RXP DMI2TXN DMI2TXP AB26 AB25 AA29 AA28 DMI_RXN2 DMI_RXP2 DMI_TXN2 DMI_TXP2 [6] [6] [6] [6] DMI3RXN DMI3RXP DMI3TXN DMI3TXP AD27 AD26 AC29 AC28 DMI_RXN3 DMI_RXP3 DMI_TXN3 DMI_TXP3 [6] [6] [6] [6] DMI_CLKN DMI_CLKP T26 T25 CLK_PCIE_ICH# [2] CLK_PCIE_ICH [2] DMI_ZCOMP DMI_IRCOMP Y23 Y24 PCI-Express Direct Media Interface To LAN [23] [23] [23] [23] SPI To WLAN OC0# OC1#/GPIO40 OC2#/GPIO41 OC3#/GPIO42 OC4#/GPIO43 OC5#/GPIO29 OC6#/GPIO30 OC7#/GPIO31 OC8# OC9# USB USBP0N USBP0P USBP1N USBP1P USBP2N USBP2P USBP3N USBP3P USBP4N USBP4P USBP5N USBP5P USBP6N USBP6P USBP7N USBP7P USBP8N USBP8P USBP9N USBP9P G3 G2 H5 H4 H2 H1 J3 J2 K5 K4 K2 K1 L3 L2 M5 M4 M2 M1 N3 N2 USBRBIAS# USBRBIAS F2 F3 A16 SWAP Override strap PCI_GNT#3 GNT3# USBP0USBP0+ USBP1USBP1+ USBP8USBP8+ USBP3USBP3+ USBP4USBP4+ USBP5USBP5+ USBP6USBP6+ USBP7USBP7+ USBP2USBP2+ T64 T65 D PCI_GNT#0 +1.5V_PCIE 24.9_4 [24] [24] [24] [24] [18] [18] [23] [23] [24] [24] [24] [24] [24] [24] [23] [23] [24] [24] To USB BOARD(Audio) 0 1 SPI(Default) 1 0 PCI 1 1 LPC SPI_CS1# R220 *1K_4 GNT0# R223 *1K_4 To Camera To WLAN To Finger Printer To Bluetooth C To New Card To 3G To USB BOARD(LAN) +3V RP42 SERR# REQ0# INTH# R351 +3V 6 7 8 9 10 5 4 3 2 1 INTC# INTB# 5 4 3 2 1 USBOC#2 USBOC#3 USBOC#4 USBOC#6 8.2KX8 22.6_6 +3V_S5 RP47 USBOC#0 USBOC#7 USBOC#5 USBOC#1 U16B D20 E19 D19 A20 D17 A21 A19 C19 A18 B16 A12 E16 A14 G16 A15 B6 C11 A9 D11 B12 C12 D10 C7 F13 E11 E13 E12 D8 A6 E8 D6 A3 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 INTA# INTB# INTC# INTD# F9 B5 C5 A10 PIRQA# PIRQB# PIRQC# PIRQD# PCI REQ0# GNT0# REQ1#/GPIO50 GNT1#/GPIO51 REQ2#/GPIO52 GNT2#/GPIO53 REQ3#/GPIO54 GNT3#/GPIO55 A4 D7 E18 C18 B19 F18 A11 C10 C/BE0# C/BE1# C/BE2# C/BE3# C17 E15 F16 E17 REQ0# GNT0# REQ1# GNT1# REQ2# GNT2# REQ3# GNT3# REQ0# GNT0# REQ1# GNT1# 8.2KX8 T80 USBOC#8 R188 8.2K_4 USBOC#9 R363 8.2K_4 +3V_S5 +3V_S5 T81 IRDY# PAR PCIRST# DEVSEL# PERR# PLOCK# SERR# STOP# TRDY# FRAME# C8 D9 G6 D16 A7 B7 F10 C16 C9 A17 IRDY# PLTRST# PCICLK PME# AG24 B10 G7 PLT_RST-R# PCLK_ICH B +3V CBE0# CBE1# CBE2# CBE3# [21,22] [21,22] [21,22] [21,22] RP40 IRDY# [21,22] PAR [21,22] PCIRST# [21,22] DEVSEL# [21,22] PERR# [21,22] DEVSEL# PERR# LOCK# SERR# STOP# TRDY# FRAME# REQ1# DEVSEL# FRAME# STOP# 6 7 8 9 10 LOCK# IRDY# PERR# INTF# 6 7 8 9 10 +3V 5 4 3 2 1 REQ2# TRDY# INTG# 8.2KX8 +3V RP41 SERR# [21,22] STOP# [21,22] TRDY# [21,22] FRAME# [21,22] R148 +3V 0_6 PLTRST#_NB [6] 5 4 3 2 1 INTE# INTD# REQ3# INTA# 8.2KX8 PCLK_ICH [2] PCI_PME# [21,22] +3V Interrupt I/F PIRQE#/GPIO2 PIRQF#/GPIO3 PIRQG#/GPIO4 PIRQH#/GPIO5 F8 G11 F12 B3 INTE# INTF# INTG# INTH# C382 R241 0_4 U3 CRT_SENSE# [18,26] PLT_RST-R# .1U_4 INTERUPT DEVICE INTA#,INTB# R5C833 REQ1# / GNT1# AD20 INTC# CB1410 A 2 4 1 PCI ROUTING IDSEL TABLE REQ0# / GNT0# AD17 4 +3V_S5 [22] [22] [21] [21] 6 7 8 9 10 5 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 ICH8M REV 1.0 5 Boot BIOS Location To USB BOARD(Audio) TC7SH08FU 3 [22] INTA# [22] INTB# [21] INTC# T79 SPI_CS#1 R186 SB-PCI A *1K_4 ICH8 Boot BIOS select USB_RBIAS_PN USB_RBIAS_PN<500mils B R227 DMI_IRCOMP_R ICH8M REV 1.0 [21,22] AD[0..31] Low = A16 swap override enabled High = Default PLTRST# [16,19,20,23,24,26] Quanta Computer Inc. R384 100K_6 3 2 PROJECT : BU1 Santa Rosa Size Document Number Date: Monday, March 26, 2007 Rev 1A ICH8M PCIE(2 of 4)/ BIOS Sheet 1 15 of 33 4 3 R127 *10K_4 D R124 *10K_4 0_4 0_4 [22,26] CLKRUN# [20,23,24] PCIE_WAKE# [21,22,23,26] SERIRQ [3] THERM_ALERT# T106 D25 [26] KBSMI# SUS_STAT#/LPCPD# SYS_RESET# AG12 BMBUSY#/GPIO0 SMB_ALERT# AG22 SMBALERT#/GPIO11 PM_STPPCI_ICH# PM_STPCPU_ICH# AE20 AG18 STP_PCI#/GPIO15 STP_CPU#/GPIO25 CLKRUN# AH11 CLKRUN#/GPIO32 PCIE_WAKE# SERIRQ THERM_ALERT# AE17 AF12 AC13 WAKE# SERIRQ THRM# VR_PWRGD_CLKEN AJ20 VRMPWRGD ICH_TP7 AJ22 TP7 AJ8 AJ9 AH9 AE16 AC19 AG8 AH12 AE11 AG10 AH25 AD16 AG13 AF9 AJ11 AD10 TACH1/GPIO1 TACH2/GPIO6 TACH3/GPIO7 GPIO8 GPIO12 TACH0/GPIO17 GPIO18 GPIO20 SCLOCK/GPIO22 QRT_STATE0/GPIO27 QRT_STATE1/GPIO28 SATACLKREQ#/GPIO35 SLOAD/GPIO38 SDATAOUT0/GPIO39 SDATAOUT1/GPIO48 SCI# GPIO12 BOARD_ID0 BOARD_ID1 BOARD_ID3 ICH_GPIO22 ICH_GPIO27 ICH_GPIO28 GPIO35 RST_HDD# ICH_GPIO39 ICH_GPIO48 T111 T149 [19] RST_HDD# SPKR [24] SPKR R369 [6] MCH_ICH_SYNC# 0_4 AD9 MCH_ICH_SYNC#_R [14] ICH_TP3 SPKR AJ13 MCH_SYNC# AJ21 TP3 SATA0GP/GPIO21 SATA1GP/GPIO19 SATA2GP/GPIO36 SATA3GP/GPIO37 SATA GPIO F4 AD15 SMB RI# BAS316 KBSMI#_ICH [26] SCI# C AF17 SYS_RST# R125 R126 T107 T108 RI# [6] PM_BMBUSY# [2] PM_STPPCI# [2] PM_STPCPU# CRB STP_PCI# PU is no stuff. CRB STP_CPU# always keeps high to ensure ME alive in M1 state. (CLK_MCH_BCLK/# must keep alive to make ME work) I think there will be update for this design, I suggest you to keep PU and 0Ω isolation resistors for this signal. SMBCLK SMBDATA LINKALERT# SMLINK0 SMLINK1 CLK14 CLK48 Clocks [22] LPC_PD# [3] SYS_RST# AJ26 AD19 AG21 AC17 AE19 SYS GPIO +3V SCLK SDATA CL_RST#1 SMLINK0 SMLINK1 Power MGT [2,13,19,23,24] SCLK [2,13,19,23,24] SDATA [23] CL_RST#1 T60 T59 2 U16C MISC GPIO Controller Link 5 SB-GPIO ICH8M REV 1.0 AJ12 AJ10 AF11 AG11 BOARD_ID4 BOARD_ID2 GPIO36 GPIO37 AG9 G5 14M_ICH CLKUSB_48 SUSCLK D3 AG23 AF21 AD18 S4_STATE#/GPIO26 AH27 PWROK AE23 ICH_PWROK DPRSLPVR/GPIO16 AJ14 PM_DPRSLPVR_R BATLOW# AE21 PM_BATLOW#_R PWRBTN# C2 DNBSWON# LAN_RST# AH20 PM_LAN_ENABLE_R RSMRST# AG27 RSMRST#_R CK_PWRGD E1 CLPWROK E3 R168 R385 100_4 100_4 T61 AJ25 14M_ICH R160 *10_4 *33_4 T94 C208 C128 SUSB# [26] SUSC# [26] *10P_4 *10P_4 Since your CPU VRM has no DPRSTP# pin, connect PM_DPRSLPVR to IMVP6 is correct T104 R367 100_4 PM_DPRSLPVR D PM_DPRSLPVR [6,29] If no use internal LAN MAC connect LAN_RST# to PLTRST# Use internal LAN MAC connect LAN_RST# to RSMRST# PLTRST# [15,19,20,23,24,26] should go high no sooner than 10 ms after both VccLAN3_3 and VccLAN1_5 have reached their nominal voltages. CK_PWRGD [2] ECPWROK [26] MPWROK [6] +3V_S5 DNBSWON# [26] R123 *0_4 PLTRST# ECPWROK SLP_M# CLKUSB_48 R211 14M_ICH [2] CLKUSB_48 [2] SLP_S3# SLP_S4# SLP_S5# SLP_S3# SLP_S4# SLP_S5# 1 R221 0_4 CL_CLK0 CL_CLK1 F23 AE18 CL_CLK0 [6] CL_CLK1 [23] CL_DATA0 CL_DATA1 F22 AF19 CL_DATA0 [6] CL_DATA1 [23] CL_VREF0 CL_VREF1 D24 AH23 CL_RST# AJ23 MEM_LED/GPIO24 ME_EC_ALERT/GPIO10 EC_ME_ALERT/GPIO14 WOL_EN/GPIO9 AJ27 AJ24 AF22 AG19 R378 3.24K_6 C235 C134 CL_RST#0 [6] ECPWROK R377 453_4 HDPACT [19,26] 2 1 2 3 [29] VR_PWRGD_CK410# R233 100K_4 TC7SH08FU 5 C R230 453_4 HDPINT [19,26] U5 4 .1U_4 ICH_PWROK +3V 3 U17 5 DELAY_VR_PWRGOOD 1 [3,6,29] DELAY_VR_PWRGOOD .1U_4 .1U_4 ICH_GPIO24 HDPACT ICH_GPIO14 HDPINT Controller Link 1 VREF for IAMT support only C250 C130 .1U_4 R229 3.24K_6 CL_VREF0_SB CL_VREF1_SB +3VSUS +3V +3V T105 INTEL CRB NEED THOSE PU & PD. INTEL FAE (08/17) "Add RSMRST# isolation (important!!! See ww22 Santa Rosa MoW)" VR_PWRGD_CLKEN 4 NC7SZ04 +3V_S5 PM_LAN_ENABLE_R Low = Default High = No Reboot +3V BIOS/ ERIC: UNSTUFF SPKR A R178 SMLINK1 R184 SYS_RST# R179 10K_4 DNBSWON# R239 *10K_4 *10K_4 R122 10K_4 Q5 MMBT3906 INTEL CRB SHOW IT RSMRST#_R 3 10K_4 GPIO35 R380 10K_4 ICH_GPIO24 THERM_ALERT# R187 8.2K_4 HDPACT R140 *10K_4 SERIRQ R157 10K_4 RI# R145 10K_4 CLKRUN# R371 8.2K_4 MCH_ICH_SYNC#_R R381 *10K_4 SCLK R359 2.2K_4 CL_RST#1 R151 10K_4 SDATA R128 2.2K_4 KBSMI#_ICH R390 10K_4 SMB_ALERT# R360 10K_4 SCI# R366 10K_4 PCIE_WAKE# R146 1K_4 ICH_GPIO22 R134 10K_4 PM_BATLOW#_R R158 8.2K_4 ICH_GPIO48 R138 10K_4 GPIO12 10K_4 RST_HDD# R137 10K_4 GPIO36 R133 8.2K_4 GPIO37 R132 8.2K_4 PM_DPRSLPVR R368 100K_4 ICH_PWROK R170 10K_4 ICH_GPIO14 R166 10K_4 HDPINT R468 *10K_4 5 R183 R155 10K_4 4 ID4 ID3 ID2 ID1 ID0 NEW CARD 0 0 0 0 1 CARD BUS 0 0 0 1 0 G-SENSOR 0 0 1 0 0 CCD 0 1 0 0 0 ROBSON 1 0 0 0 0 B R200 4.7K_4 +3VSUS D8 BAV99 3 ICH_GPIO39 R372 10K_4 INTEL CRB SHOW IT PM_LAN_ENABLE_R D9 BAV99 3 R121 *0_4 R210 2.2K_4 DISABLE LAN: STUFF +3V Board ID RSMRST# [26] FROM uR(EC) *10K_4 Internal Pull up R358 1 TO ICH8 1 SPKR 10K_4 2 B R185 2 SMLINK0 No Reboot strap 2 100K_4 1 R362 +3V R290 *10K_4 BOARD_ID4 R269 10K_4 3 +3V R120 *10K_4 BOARD_ID3 R141 10K_4 +3V R136 *10K_4 BOARD_ID2 R135 10K_4 +3V R382 A R373 *10K_4 *10K_4 BOARD_ID1 R370 BOARD_ID0 Quanta Computer Inc. R374 10K_4 10K_4 2 PROJECT : BU1 Santa Rosa Size Document Number Date: Monday, March 26, 2007 Rev 2A ICH8M GPIO(3 of 4) Sheet 1 16 of 33 5 4 +3V R235 100/F_6 +5VREF_SB .1U_4 .1U_4 +5VREF_SUS_SB +1.5V_PCIE L18 FBMJ2125HS420-T_8 Intel use 0.5UH inductor + C372 330U_3528 C210 C203 C167 22U_8 22U_8 2.2U_6 +1.5V 0_8+1.5V_SATA R383 0_8+1.5V_APLL_RR +1.5V_APLL L19 10UH_8 CV01001MN08 C385 C384 10U_6 1U_6 C C217 1U_6 C212 1U_6 R349 B 0_6 +1.5V_USB C205 .1U_4 C221 1_8 A 10U_6 VCC1_5_A[01] VCC1_5_A[02] VCC1_5_A[03] VCC1_5_A[04] VCC1_5_A[05] AC1 AC2 AC3 AC4 AC5 VCC1_5_A[06] VCC1_5_A[07] VCC1_5_A[08] VCC1_5_A[09] VCC1_5_A[10] AC10 AC9 VCC1_5_A[11] VCC1_5_A[12] AA5 AA6 VCC1_5_A[13] VCC1_5_A[14] G12 G17 H7 VCC1_5_A[15] VCC1_5_A[16] VCC1_5_A[17] AC7 AD7 VCC1_5_A[18] VCC1_5_A[19] +1.5V_SATA W23 VCC1_5_A[25] TP_VCCLAN1_05_ICH_1 TP_VCCLAN1_05_ICH_2 F17 G18 VCCLAN1_05[1] VCCLAN1_05[2] +3V_VCCLAN F19 G20 VCCLAN3_3[1] VCCLAN3_3[2] A24 VCCGLANPLL A26 A27 B26 B27 B28 VCCGLAN1_5[1] VCCGLAN1_5[2] VCCGLAN1_5[3] VCCGLAN1_5[4] VCCGLAN1_5[5] +1.5V_VCCGLANPLL C238 AE7 AF7 AG7 AH7 AJ7 VCC1_5_A[20] VCC1_5_A[21] VCC1_5_A[22] VCC1_5_A[23] VCC1_5_A[24] L7 PBY160808T-301Y-N_6 VCCSATAPLL C241 B25 2.2U_6 VCCGLAN3_3 GLAN POWER R244 AJ6 VCCUSBPLL .1U_4 +1.5V VCC1_5_B[01] VCC1_5_B[02] VCC1_5_B[03] VCC1_5_B[04] VCC1_5_B[05] VCC1_5_B[06] VCC1_5_B[07] VCC1_5_B[08] VCC1_5_B[09] VCC1_5_B[10] VCC1_5_B[11] VCC1_5_B[12] VCC1_5_B[13] VCC1_5_B[14] VCC1_5_B[15] VCC1_5_B[16] VCC1_5_B[17] VCC1_5_B[18] VCC1_5_B[19] VCC1_5_B[20] VCC1_5_B[21] VCC1_5_B[22] VCC1_5_B[23] VCC1_5_B[24] VCC1_5_B[25] VCC1_5_B[26] VCC1_5_B[27] VCC1_5_B[28] VCC1_5_B[29] VCC1_5_B[30] VCC1_5_B[31] VCC1_5_B[32] VCC1_5_B[33] VCC1_5_B[34] VCC1_5_B[35] VCC1_5_B[36] VCC1_5_B[37] VCC1_5_B[38] VCC1_5_B[39] VCC1_5_B[40] VCC1_5_B[41] VCC1_5_B[42] VCC1_5_B[43] VCC1_5_B[44] VCC1_5_B[45] VCC1_5_B[46] USB CORE 0_6 V5REF_SUS AA25 AA26 AA27 AB27 AB28 AB29 D28 D29 E25 E26 E27 F24 F25 G24 H23 H24 J23 J24 K24 K25 L23 L24 L25 M24 M25 N23 N24 N25 P24 P25 R24 R25 R26 R27 T23 T24 T27 T28 T29 U24 U25 V23 V24 V25 W25 Y25 F1 L6 L7 M6 M7 .1U_4 R213 G4 D1 C371 +3V V5REF[1] V5REF[2] VCCA3GP R388 VCCRTC A16 T7 ATX C191 AD25 ARX C218 D +1.5V 1 +1.05V CORE PDZ5.6B +5V 2 U16F VCCP_CORE .1U_4 IDE C152 .1U_4 PCI 10_6 C154 1U_4 1 R353 1 PDZ5.6B +5V_S5 C153 VCCPSUS D10 VCCPUSB D24 3 VCCRTC 2 2 +3V_S5 VCC1_05[01] VCC1_05[02] VCC1_05[03] VCC1_05[04] VCC1_05[05] VCC1_05[06] VCC1_05[07] VCC1_05[08] VCC1_05[09] VCC1_05[10] VCC1_05[11] VCC1_05[12] VCC1_05[13] VCC1_05[14] VCC1_05[15] VCC1_05[16] VCC1_05[17] VCC1_05[18] VCC1_05[19] VCC1_05[20] VCC1_05[21] VCC1_05[22] VCC1_05[23] VCC1_05[24] VCC1_05[25] VCC1_05[26] VCC1_05[27] VCC1_05[28] +1.05V_SB A13 B13 C13 C14 D14 E14 F14 G14 L11 L12 L14 L16 L17 L18 M11 M18 P11 P18 T11 T18 U11 U18 V11 V12 V14 V16 V17 V18 R238 0_1206 U16E C190 C180 .1U_4 10U_8 +1.5V VCCDMIPLL_ICH L6 R204 1_8 PBY160808T-301Y-N_6 C188 C189 .01U_4 10U_6 +1.25V +1.25V_DMI R356 +1.05V 0_8 C374 R192 22U_8 C159 C164 C165 .1U_4 .1U_4 4.7U_6 0_6 VCCDMIPLL R29 VCC_DMI[1] VCC_DMI[2] AE28 AE29 V_CPU_IO[1] V_CPU_IO[2] AC23 AC24 VCC3_3[01] AF29 +V3.3_DMI_ICH R357 0_6 VCC3_3[02] AD2 +V3.3_SATA_ICH R176 0_6 VCC3_3[03] VCC3_3[04] VCC3_3[05] VCC3_3[06] AC8 AD8 AE8 AF8 +V3.3S_VCCPCORE_ICH VCC3_3[07] VCC3_3[08] VCC3_3[09] VCC3_3[10] VCC3_3[11] VCC3_3[12] VCC3_3[13] AA3 U7 V7 W1 W6 W7 Y7 +V3.3S_IDE_ICH VCC3_3[14] VCC3_3[15] VCC3_3[16] VCC3_3[17] VCC3_3[18] VCC3_3[19] VCC3_3[20] VCC3_3[21] VCC3_3[22] VCC3_3[23] VCC3_3[24] A8 B15 B18 B4 B9 C15 D13 D5 E10 E7 F11 +V3.3S_PCI_ICH +1.05V_V_CPU_IO +3V C155 C381 .1U_4 .1U_4 C168 .1U_4 C236 C223 C233 .1U_4 .1U_4 .1U_4 VCCHDA AC12 +3V_1.5V_HDA_IO_ICH VCCSUSHDA AD11 +VCCSUSHDA VCCSUS1_05[1] VCCSUS1_05[2] J6 AF20 TP_VCCSUS1_05_ICH_1 TP_VCCSUS1_05_ICH_2 VCCSUS1_5[1] AC16 TP_VCCSUS1_5_ICH_1 VCCSUS1_5[2] J7 TP_VCCSUS1_5_ICH_2 VCCSUS3_3[01] C3 VCCSUS3_3[02] VCCSUS3_3[03] VCCSUS3_3[04] VCCSUS3_3[05] VCCSUS3_3[06] AC18 AC21 AC22 AG20 AH28 VCCSUS3_3[07] VCCSUS3_3[08] VCCSUS3_3[09] VCCSUS3_3[10] VCCSUS3_3[11] VCCSUS3_3[12] VCCSUS3_3[13] VCCSUS3_3[14] VCCSUS3_3[15] VCCSUS3_3[16] VCCSUS3_3[17] VCCSUS3_3[18] VCCSUS3_3[19] P6 P7 C1 N7 P1 P2 P3 P4 P5 R1 R3 R5 R6 R189 +V3.3A_ICH 0_6 R190 0_6 R234 0_6 0_6 R386 R391 +3V_S5 0_6 *0_6 +3V +1.5V C161 C166 .1U_4 .1U_6 +3V_S5 R228 C127 C163 .1U_4 22N_4 +V3.3A_USB_ICH R173 0_6 R352 0_8 C373 4.7U_6 VCCCL1_05 G22 TP_VCCCL1_05_ICH VCCCL1_5 A22 VCCCL1_5_INT_ICH VCCCL3_3[1] VCCCL3_3[2] F20 G21 +V3.3M_ICH TP_VCCLAN1_05_ICH_1 TP_VCCLAN1_05_ICH_2 C216 C215 .1U_6 .1U_6 TP_VCCSUS1_05_ICH_1 TP_VCCSUS1_05_ICH_2 C211 C157 .1U_6 .1U_6 TP_VCCSUS1_5_ICH_1 TP_VCCSUS1_5_ICH_2 TP_VCCCL1_05_ICH C240 C239 1U_6 *.1U_4 T62 T66 T67 A23 A5 AA2 AA7 A25 AB1 AB24 AC11 AC14 AC25 AC26 AC27 AD17 AD20 AD28 AD29 AD3 AD4 AD6 AE1 AE12 AE2 AE22 AD1 AE25 AE5 AE6 AE9 AF14 AF16 AF18 AF3 AF4 AG5 AG6 AH10 AH13 AH16 AH19 AH2 AF28 AH22 AH24 AH26 AH3 AH4 AH8 AJ5 B11 B14 B17 B2 B20 B22 B8 C24 C26 C27 C6 D12 D15 D18 D2 D4 E21 E24 E4 E9 F15 E23 F28 F29 F7 G1 E2 G10 G13 G19 G23 G25 G26 G27 H25 H28 H29 H3 H6 J1 J25 J26 J27 J4 J5 K23 K28 K29 K3 K6 VSS[001] VSS[002] VSS[003] VSS[004] VSS[005] VSS[006] VSS[007] VSS[008] VSS[009] VSS[010] VSS[011] VSS[012] VSS[013] VSS[014] VSS[015] VSS[016] VSS[017] VSS[018] VSS[019] VSS[020] VSS[021] VSS[022] VSS[023] VSS[024] VSS[025] VSS[026] VSS[027] VSS[028] VSS[029] VSS[030] VSS[031] VSS[032] VSS[033] VSS[034] VSS[035] VSS[036] VSS[037] VSS[038] VSS[039] VSS[040] VSS[041] VSS[042] VSS[043] VSS[044] VSS[045] VSS[046] VSS[047] VSS[048] VSS[049] VSS[050] VSS[051] VSS[052] VSS[053] VSS[054] VSS[055] VSS[056] VSS[057] VSS[058] VSS[059] VSS[060] VSS[061] VSS[062] VSS[063] VSS[064] VSS[065] VSS[066] VSS[067] VSS[068] VSS[069] VSS[070] VSS[071] VSS[072] VSS[073] VSS[074] VSS[075] VSS[076] VSS[077] VSS[078] VSS[079] VSS[080] VSS[081] VSS[082] VSS[083] VSS[084] VSS[085] VSS[086] VSS[087] VSS[088] VSS[089] VSS[090] VSS[091] VSS[092] VSS[093] VSS[094] VSS[095] VSS[096] VSS[097] VSS[098] VSS[099] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106] VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158] VSS[159] VSS[160] VSS[161] VSS[162] VSS[163] VSS[164] VSS[165] VSS[166] VSS[167] VSS[168] VSS[169] VSS[170] VSS[171] VSS[172] VSS[173] VSS[174] VSS[175] VSS[176] VSS[177] VSS[178] VSS[179] VSS[180] VSS[181] VSS[182] VSS[183] VSS[184] K7 L1 L13 L15 L26 L27 L4 L5 M12 M13 M14 M15 M16 M17 M23 M28 M29 M3 N1 N11 N12 N13 N14 N15 N16 N17 N18 N26 N27 N4 N5 N6 P12 P13 P14 P15 P16 P17 P23 P28 P29 R11 R12 R13 R14 R15 R16 R17 R18 R28 R4 T12 T13 T14 T15 T16 T17 T2 U12 U13 U14 U15 U16 U17 U23 U26 U27 U3 U5 V13 V15 V28 V29 W2 W26 W27 Y28 Y29 Y4 AB4 AB23 AB5 AB6 AD5 U4 W24 VSS_NCTF[01] VSS_NCTF[02] VSS_NCTF[03] VSS_NCTF[04] VSS_NCTF[05] VSS_NCTF[06] VSS_NCTF[07] VSS_NCTF[08] VSS_NCTF[09] VSS_NCTF[10] VSS_NCTF[11] VSS_NCTF[12] A1 A2 A28 A29 AH1 AH29 AJ1 AJ2 AJ28 AJ29 B1 B29 D C B ICH8M REV 1.0 A ICH8M REV 1.0 +1.5V_PCIE C220 R212 4.7U_6 +3V 5 R231 0_6 0_6 +3V Quanta Computer Inc. +3V_GLAN PROJECT : BU1 Santa Rosa 4 3 2 Size Document Number Date: Tuesday, March 27, 2007 Rev 3A ICH8M Power(4 of 4) Sheet 1 17 of 33 5 4 3 2 +3V CRT PORT 1A SSM14 1 C3 2 [6] CRT_R [6] CRT_G [6] CRT_B 25 MIL L34 BLM18BA220SN1D_6 CRT_R1 CRT_G L33 BLM18BA220SN1D_6 CRT_G1 CRT_B L32 BLM18BA220SN1D_6 CRT_B1 R452 150_4 C11 10P_4 R451 150_4 C10 10P_4 C5 10P_4 CN35 C486 1000P_4 .1U_4 U25 [6] INT_LVDS_DIGON 6 IN OUT 1 4 IN GND 2 3 ON/OFF GND 5 LCDVCC_1 R440 0_8 LCDVCC C481 C484 C479 C478 C480 C526 .1U_4 10U_8 .1U_4 .01U_4 10U_8 .1U_4 C6 10P_4 AAT4280 6 1 7 2 8 3 9 4 10 5 C8 10P_4 D2 11 MTW355 Crestline suggest 100K G73 suggest 10K(ZS1 Default) 8/27 change back to 100K CRT_SENSE# [15,26] 12 13 R441 100K_4 D 14 15 LCD/LED TYPE CONNECTOR 17 C12 10P_4 C485 *.1U_4 CRT_DSUB-070546FR015SX05ZX- CRT_R R453 150_4 C527 .1U_4 5V_CRT2 1 FUSE1A6V_POLY-1A-6V D 1 +3V F2 16 +5V D1 2 +3V +3V R445 2.2K_4 INT_LVDS_EDIDDATA R447 2.2K_4 INT_LVDS_EDIDCLK U27 5V_CRT2 1 +5V C492 +3V CRT_R1 CRT_G1 CRT_B1 VSYNC1 HSYNC1 15 13 VSYNC HSYNC DDC_IN1 DDC_IN2 10 11 DDCCLK DDCDAT DDC_OUT1 DDC_OUT2 9 12 CRTDCLK CRTDDAT 2 3 4 5 VIDEO_1 VIDEO_2 VIDEO_3 6 GND 7 8 .22U_6 16 14 VCC_SYNC SYNC_OUT2 SYNC_OUT1 VCC_DDC BYP SYNC_IN2 VCC_VIDEO SYNC_IN1 R449 R448 39_4 39_4 VSYNC1_CRT HSYNC1_CRT L30 L31 VSYNC [6] HSYNC [6] BLM18BA220SN1 CRTVSYNC CRTHSYNC BLM18BA220SN1 C2 C4 5V_CRT2 DDCCLK [6] DDCDAT [6] 10P_4 R454 R455 2.7K_4 2.7K_4 RP2 LCD_EDIDCLK LCD_EDIDDATA 10P_4 CM2009 H=1.75mm +3V +5V DDCCLK R446 2.2K_4 DDCDAT R450 2.2K_4 LCD@0_4P2R_S 4 3 2 1 C1 C7 10P_4 10P_4 RP1 LED_EDIDDATA LED_EDIDCLK LED@0_4P2R_S 4 3 2 1 RP4 LCD_TXLCLKOUTLCD_TXLCLKOUT+ LCD@0_4P2R_S 4 3 2 1 RP3 LED_TXLCLKOUT+ LED_TXLCLKOUT- LED@0_4P2R_S 4 3 2 1 USBP8-_LCD USBP8+_LCD +3V LCD@0_4P2R_S RP12 2 1 4 3 RP11 C C494 .1U_4 USBP8-_LED USBP8+_LED C493 .1U_4 RP10 INT_LVDS_EDIDCLK INT_LVDS_EDIDDATA INT_LVDS_EDIDCLK [6] INT_LVDS_EDIDDATA [6] LED_TXLOUT2+ LED_TXLOUT2- INT_TXLCLKOUT- [6] INT_TXLCLKOUT+ [6] 0_8 1 C488 R444 INVCC0 C490 10U-25V_1210 1 2 +3V LID591# 2 + 1000P_4 USBP8-_LCD USBP8+_LCD 4 1 4 1 3 2 2 3 2 3 USBP8USBP8+ L38 3 .1U_4 3 2 L37 MR1 EC2648-B3-F C495 USBP8-_LED USBP8+_LED R253 1K_4 1 4 1 4 DLW21HN900SQ2L DISPON D15 BAS316 LID591# [26] R442 [6] INT_LVDS_PWM [26] CONTRAST D13 BAS316 R250 B 0_4 INT_LVDS_BLON [6,26] *0_4 LCD_VADJ R439 0_4 C483 *.1U_4 R243 R251 *1K_4 LCD_VADJ 100K_4 R483 10K_4 3 VIN 2 C531 EC_FPBACK# [26] DISPON 2 1 Q24 R487 10K_4 F1 LITTLE-0603-2A-32V 1 DTC144EU HALL SENSOR LCD_VADJ_O2 C532 LED_SW LED_PWR 10UH-88mR C496 C497 B140 C525 .1U_4 C499 1U/X7R-25V_6 RP7 LED_TXLOUT1+ LED_TXLOUT1- USBP8- [15] USBP8+ [15] LCD_TXLOUT0LCD_TXLOUT0+ 4 2 RP5 LED_TXLOUT0+ LED_TXLOUT0- LCD@0_4P2R_S 3 1 INT_TXLOUT1INT_TXLOUT1+ LCD@0_4P2R_S 3 1 INT_TXLOUT1- [6] INT_TXLOUT1+ [6] INT_TXLOUT0INT_TXLOUT0+ INT_TXLOUT0- [6] INT_TXLOUT0+ [6] LED@0_4P2R_S 4 3 2 1 C CN1 CHI MEI LED PANEL MODULE 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 +3V USBP8-_LCD USBP8+_LCD CCD_POWER LCDVCC LCDVCC INT_TXLOUT2- [6] INT_TXLOUT2+ [6] LED@0_4P2R_S 4 3 2 1 RP6 USBP8USBP8+ INT_TXLOUT2INT_TXLOUT2+ +3V LED_TXLOUT1+ LED_TXLOUT1- LCD_VADJ DISPON CCD_POWER LCDVCC LCDVCC INVCC0 INVCC0 D-MIC_CLK_LCD D-MIC_DATA_LCD LCD_EDIDCLK LCD_EDIDDATA LED_TXLOUT0+ LED_TXLOUT0- LCD_TXLCLKOUTLCD_TXLCLKOUT+ LED_TXLCLKOUT+ LED_TXLCLKOUT- LCD_TXLOUT0LCD_TXLOUT0+ LED_EDIDDATA LED_EDIDCLK LCD_TXLOUT1LCD_TXLOUT1+ LED_GND1 LED_GND2 LED_GND3 LED_GND4 LED_GND5 LED_GND6 LCD_TXLOUT2LCD_TXLOUT2+ USBP8-_LED USBP8+_LED LED_TXLOUT2+ LED_TXLOUT2- 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 31 32 31 32 LCD@ACS_88242-3001 LED_PWR LCD PANEL MODULE INT_MIC D-MIC_CLK_LCD D-MIC_DATA_LCD D-MIC_CLK_LCD D-MIC_DATA_LCD 2 1 C529 *1000P_4 C530 CN2 *1000P_4 10U/Y5V-50V_1210 ISEN6 R469 10/F_4 LED_GND6 ISEN5 ISEN4 GNDA ISEN3 ISEN2 15 14 13 12 11 ISEN5 ISEN4 R470 R471 10/F_4 10/F_4 LED_GND5 LED_GND4 ISEN3 ISEN2 R472 R473 10/F_4 10/F_4 PAD 21 LED_GND3 LED_GND2 ISEN1 R475 10/F_4 LED_GND1 GND OZ9956 A LED_PWR R476 C500 1n_4 SSTCMP C501 1n_4 C502 1n_4 C503 1n_4 C504 1n_4 C505 1n_4 1M_6 1 2 CCD_POWERON [26] R477 R478 75K_4 10K/F_6 OVP Q36 CM@DTC144EU C506 1n_4 R479 75K_4 Quanta Computer Inc. C507 10n_4 PROJECT : BU1 Santa Rosa Size Date: 5 4 B 20 19 18 17 16 OVP NC ISET SSTCMP ISEN1 51K_4 6 7 8 9 10 R474 R443 CM@4.7K_4 CM@1000P_4 3 A CM@10U_8 LED_VREF C487 1 2 C482 Q35 CM@AO3413 + CCD_POWER 3 ENA NC VREF VIN RT 2 +5V 1 2 3 4 5 PWM NC SW NC ISEN6 LED_VIN U28 DISPON_O2 4 2 CN4 LVC-C40SFYG-40P C498 10U/Y5V-50V_1210 LCD_VADJ_O2 CAMERA MODULE 1 10n_4 D27 L35 10U/X6S-25V_1206 +5V 1n_4 DISPON_O2 45 46 DLW21HN900SQ2L 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 LCD_TXLOUT1LCD_TXLOUT1+ LCD@0_4P2R_S 3 1 LED@0_4P2R_S 4 3 2 1 RP8 INT_TXLCLKOUTINT_TXLCLKOUT+ LED@0_4P2R_S 4 3 2 1 44 43 42 41 VIN R268 100K_4 4 2 RP9 TOSHIBA LED PANEL MODULE +3VPCU LCD_TXLOUT2LCD_TXLOUT2+ 3 2 Document Number Rev 3A LCD/CRT/LID/CAMERA Sunday, April 01, 2007 Sheet 1 18 of 33 5 4 3 ODD PDIOW# PDIORDY IRQ14 PDA1 PDA0 PDCS1# ODD_LED# ODD_LED# [25] ODD_LED# +5V R345 470_6 IN for Master 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 51 52 PDD[0..15] 51 52 D -IDERST PDD7 PDD6 PDD5 PDD4 PDD3 PDD2 PDD1 PDD0 PDDREQ PDIOW# PDIOR# PDIORDY PDDACK# IRQ14 PDA1 PDA0 PDCS1# PDA2 PDCS3# PDDREQ PDIOW# PDIOR# PDIORDY PDDACK# IRQ14 PDA1 PDA0 PDCS1# PDA2 PDCS3# 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 PDD8 PDD9 PDD10 PDD11 PDD12 PDD13 PDD14 PDD15 PDDREQ PDIOR# CN33 PDDACK# DIAG# PDA2 PDCS3# R350 *10K_4 +5V +5V 80 mils C248 C246 C249 .1U_4 1000P_6 .1U_4 C252 C254 10U_8 150U/6.3V_7343 ODD_CONN NC for Slave RES-TYPE 2 +3V C [16] RST_HDD# [15,16,20,23,24,26] PLTRST# R347 *0_4 R348 0_4 Must be PU even when IDE device is not use +5V +3V Q25 DTC144EU 1 R346 10K_4 +3V 1 SATA HDD CN23 [14] PDD[0..15] [14] [14] [14] [14] [14] [14] [14] [14] [14] [14] [14] 2 R215 4.7K_4 PDIORDY R214 8.2K_4 IRQ14 GND23 23 GND1 RXP RXN GND2 TXN TXP GND3 1 2 3 4 5 6 7 3.3V 3.3V 3.3V GND GND GND 5V 5V 5V GND RSVD GND 12V 12V 12V 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 GND24 24 D SATA_TXP0 SATA_TXN0 SATA_TXP0 [14] SATA_TXN0 [14] SATA_RXN0 SATA_RXP0 SATA_RXN0 [14] SATA_RXP0 [14] +3.3VSATA C388 C391 *4.7U_8 *.1U_4 +5VSATA C100 C101 C389 .1U_4 .1U_4 10U_8 R395 *0_8 R387 0_8 +3V +5V C387 150U/6.3V_7343 SA@Serial_ATA C -IDERST 3 +3V_HDP +3V_HDP U19 SHDN 2 GND 3 VIN C396 VO 4 SET 5 Q32 GS@2N7002 ADDRESS: 32H C398 GS@10U_8 [26] 2ND_MBDATA [2,13,16,23,24] SDATA R484 0_4 R485 *0_4 +3V_HDP 3 +3V_HDP 43 44 NC NC NC 42 40 39 38 37 36 35 41 NC NC NC NC NC NC 34 [26] 2ND_MBCLK 32 NC NC 2 31 NC NC 3 30 NC GND 4 29 NC 28 Reserved 27 VDD 5 Vouty 6 Reserved ST 7 26 Reserved Voutx 8 25 NC NC 9 24 NC NC 10 NC 11 NC 3 1 2 Vcc Reset# GND R101 GS@10K_4 0_4 R488 *0_4 3 1 ACCELX ACCELY ACCELZ AXSTST +3V_HDP C91 AXSTST GS@.1U-10V_4 ACCELX 4 2 2 GS@4.7K_4P2R_S 3 KXP84_SCL 1 [16,26] HDPACT [16,26] HDPINT XOUT_G R398 GND HD_PINT GS@1K_4 16 7 VCC VCC 18 17 15 2 ACCELX ACCELY ACCELZ AXSTST 11 10 9 HDPACT HDPPD HDPINT R96 GS@47K/F_6 5 HDPSCL HDPSDA RESET MODE VSS Reserved Reserved Reserved Reserved Reserved Reserved 1 20 FS (Full Scale) selection 0 0 Normal Mode C394 Y5 C395 GS*22P_6 B GS*22P_6 ACCELX 1 +3V_HDP KXP84_SCL KXP84_SDA 3 8 G-RESET# R399 R401 GS@10K_4 GS@10K_4 4 6 12 13 14 19 XIN_G XOUT_G R99 R400 GS@10K_4 GS@10K_4 HDPPD selection GS@R5F211B4D11SP 2g Full-Scale XIN_G U20 ACCELY PD FS GS@.1U-10V_4 GS*8 MHz U29 FS C397 GS@.1U-10V_4 +3V_HDP G-RESET# HDPPD 0 1 Normal Mode Power-down mode ACCELY 6g Full-Scale ACCELZ C401 PD (Power Down) selection A R486 12 PD NC 13 14 Voutz 15 FS 16 Reserved 17 Reserved 18 Reserved 19 Reserved 20 22 R100 GS@*10K_4 Reserved NC 23 GS@LIS3L02AQ3 [2,13,16,23,24] SCLK +3V_HDP G691L308T73UF-SOT23 1 NC Reserved +3V_HDP NC 21 +3V_HDP NC NC 33 +3V_HDP RP49 GS@G913-C Q31 GS@2N7002 B C403 +3V_HDP GS@.1U-10V_4 U1 KXP84_SDA 1 1 +5V_S5 1 2 [26,30,31,32] MAINON 2 G SENSOR GS@33n-16V_4 1 C402 GS@33n-16V_4 C404 GS@33n-16V_4 A Power-down mode ACCELZ Close Chipset Quanta Computer Inc. PROJECT : BU1 Santa Rosa Size Document Number Date: Monday, March 26, 2007 Close Chipset 5 4 3 2 Rev 2A PATA/ODD/G SENSOR Sheet 1 19 of 33 5 4 DVDD15 AVDD33 3 2 DVDD15 LAN_ACT# AVDD33 LAN_LINK# XTAL1 1 93C56: STUFF 93C46: NOSTUFF LAN_ACT# [24] LAN_LINK# [24] T87 Y2 33P_6 33P_6 C316 C318 0.1U/10V_4 0.1U/10V_4 CTRL15 R304 2K/F_4 GVDD VDD33 VDD33 CTRL15 DVDD15 DVDD15 RSET DVDD15 DVDD15 GND U10 [24] MDI1+ [24] MDI1T93 T89 CTRL18 AVDD33 CTRL18 AVDD33 AVDD18 AVDD18 AVDD18 AVDD18 AVDD18 AVDD18 AVDD18 DVDD15 VDD33 AVDD18 DVDD15 VDD33 Tx MDI1 Pair Rx MDI3+ MDI3- 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 R313 R312 2 EECS EESK EEDI EEDO *10K_4 1 3.6K_6 1 2 3 4 CS SK DI DO 8 7 6 5 VCC DC ORG GND D C355 .1U/16V_4 93C46-3GR VCTRL18 AVDD33 MDIP0 MDIN0 AVDD18 MDIP1 MDIN1 AVDD18 MDIP2 MDIN2 AVDD18 MDIP3 MDIN3 AVDD18 VDD15 VDD33 EESK EEDI VDD33 EEDO EECS VDD15 NC RTL8111B/8111C/8101E VDD1 NC NC VDD15 VDD33 ISOLATEB# NC NC VDD15 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 EESK EEDI VDD33 VDD33 DVDD15 DVDD15 DVDD15 DVDD15 EEDO EECS +3V close chipset R330 MDI0+ R298 49.9/F_4 MDI0- R299 49.9/F_4 MDI1+ R335 49.9/F_4 MDI1- R334 49.9/F_4 C295 .01U/16V_4 C353 .01U/16V_4 1K_4 DVDD15 VDD33 ISOLATEB DVDD15 VDD33 DVDD15 DVDD15 close connector R329 C 15K_4 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 2 MDI0 Pair MDI1+ MDI1MDI2+ MDI2- T90 T92 C MDI0+ MDI0- PCLK_SMB PDAT_SMB LANWAKEB# PERSTB# VDD15 EVDD18 HSIP HSIN EGND REFCLK_P REFCLK_N EVDD18 HSOP HSON EGND VDD15 100Ohm [24] MDI0+ [24] MDI0- VDD33 +3V_S5 1 C314 65 25.0000 MHz C323 VDD33 U11 T86 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 D 2 RSET VCTRL15 GVDD CKTAL2 CKTAL1 AVDD33 VDD15 LED0 LED1 LED2 LED3 VDD33 VDD15 NC NC VDD15 1 XTAL2 T91 T88 [16,23,24] PCIE_WAKE# [15,16,19,23,24,26] PLTRST# R302 DVDD15 EVDD18 [15] PCIE_TXP4 [15] PCIE_TXN4 To SB TX R488 0_6 +3V_S5 DVDD15 EGND PCIE_RXN4_R C328 .1U_4 PCIE_RXP4_R C326 .1U_4 EVDD18 CLK_PCIE_LAN# CLK_PCIE_LAN EGND PCIE_WAKE# PERSTB DVDD15 EVDD18 PCIE_TXP4 PCIE_TXN4 0_4 L16 LANVCC PBY160808T-301Y-N_6 VDD33 C352 C305 C322 C325 C341 C345 22U/10V_8 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 DVDD15 EGND EGND VDD33 CTRL18 L12 AVDD33 1 2 5 6 C538 0.1U/10V_4 0.1U/10V_4 AVDD18 AVDD33 C308 C294 C300 C301 C302 C296 C303 22U_8 22U_8 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 R306 0_6 *0.1U/X7R-50V_6 EVDD18 Q40 *AO6402 3 LANVCC B AVDD18 PBY160808T-301Y-N_6 4 [26] LANVCC_EN C320 AVDD18 [23,24] L13 CTRL18 BK1608HS220_6 C312 To SB RX CLK_PCIE_LAN# [2] CLK_PCIE_LAN [2] B +3VPCU PCIE_RXN4 [15] PCIE_RXP4 [15] EVDD18 EVDD18 C324 C317 0.1U/10V_4 0.1U/10V_4 L14 BK1608HS220_6 C539 *0.1U/X7R-50V_6 L15 BK1608HS220_6 EGND A A CTRL15 L17 CTRL15 DVDD15 DVDD15 PBY160808T-301Y-N_6 C354 C340 C347 C304 C333 C315 C346 C344 C343 C342 C332 C327 C321 22U_8 22U_8 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 Quanta Computer Inc. PROJECT : BU1 Santa Rosa 5 4 3 2 Size Document Number Date: Thursday, March 29, 2007 Rev 3A PCIE LAN 10/100M RTL8101E Sheet 1 20 of 33 5 4 3 PCLK_PCM +3V C245 C263 C253 C258 R237 CB@*22_4 PCLK_PCM_R CB_RSMRST# C363 CB@.1U_4 CB@.1U_4 CB@.1U_4 CB@.1U_4 CB@.1U_4 R340 R338 C244 CB@*0_6 CB@100K_6 2 1 CB@*10p_4 A_CCD1# A_CCD2# PCIRST# +3V C359 C255 delay 10ms at least CB@.22U_6 CB@10P_4 C357 CB@10P_4 +3V CB@47_4 R337 A_CCD1# A_CCD2# A_CVS1# A_CVS2# VCCD0# VCCD1# 1 2 3 4 5 6 7 8 +5V VCCD0# VCCD1# 3.3V 3.3V 5V 5V GND OC# SHDN# VPPD0 VPPD1 AVCC AVCC AVCC AVPP 12V 16 15 14 13 12 11 10 9 C286 CB@4.7U_6 C283 CB@.1U_4 C287 5 C270 CB@.1U_4 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 VPP1 A16- CCLK A15- CIRDY A12- CCBE2 A7 - CAD18 A6 - CAD20 A5 - CAD21 A4 - CAD22 A3 - CAD23 A2 - CAD24 A1 - CAD25 A0 - CAD26 D0 - CAD27 D1 - CAD29 D2 - RFU WP,IOIS16-CKRUN GND C6 D9 CVS1/VS1 CVS2/VS2 L12 A4 CCD1#/CD1# CCD2#/CD2# CCLKRUN#/WP/IOIS16# CRST#/RESET CCLK/A16 CAD31/D10 CAD30/D9 CAD29/D1 CAD28/D8 CAD27/D0 CAD26/A0 CAD25/A1 CAD24/A2 CAD23/A3 CAD22/A4 CAD21/A5 CAD20/A6 CAD19/A25 CAD18/A7 CAD17/A24 CAD16/A17 CAD15/IOWR# CAD14/A9 CAD13/IORD# CAD12/A11 CAD11/OE# CAD10/CE2# CAD9/A10 CAD8/D15 CAD7/D7 CAD6/D13 CAD5/D6 CAD4/D12 CAD3/D5 CAD2/D11 CAD1/D4 CAD0/D3 B2 C3 B3 A3 C4 A6 D7 C7 A8 D8 A9 C9 A10 B10 D10 E12 F10 E13 F13 F11 G10 G11 G12 H12 H10 J11 J12 K13 J10 K10 K12 L13 A_CAD31 A_CAD30 A_CAD29 A_CAD28 A_CAD27 A_CAD26 A_CAD25 A_CAD24 A_CAD23 A_CAD22 A_CAD21 A_CAD20 A_CAD19 A_CAD18 A_CAD17 A_CAD16 A_CAD15 A_CAD14 A_CAD13 A_CAD12 A_CAD11 A_CAD10 A_CAD9 A_CAD8 A_CAD7 A_CAD6 A_CAD5 A_CAD4 A_CAD3 A_CAD2 A_CAD1 A_CAD0 A_CCD1# A_CAD2 A_CAD4 A_CAD6 A_CRSVD/D14 A_CAD8 A_CAD10 A_CVS1# A_CAD13 A_CAD15 A_CAD16 A_CRSVD/A18 A_CBLOCK# A_CSTOP# A_CDEVSEL# 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 GND CD1- CCD1 D11- CAD2 D12- CAD4 D13- CAD6 D14- RFU D15- CAD8 CE2- CAD10 RFSH,VS*1-CVS1 IORD-CAD13 IOWR-CAD15 A17- CAD16 A18- RFU A19- CBLOCK A20- CSTOP A21- CDEVSEL VCC A_CTRDY# A_CFRAME# A_CAD17 A_CAD19 A_CVS2# A_CRST# A_CSERR# A_CREQ# A_CC/BE3# A_CAUDIO A_CSTSCHG A_CAD28 A_CAD30 A_CAD31 A_CCD2# 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 VPP2 A22- CTRDY A23- CFRAME A24- CAD17 A25- CAD19 NC - CVS2 RESET-CRST WAIT-CSERR INPACK-CREQ REG- CCBE3 BVD2,SP-CAUDIO BVD1,STSCHG-C* D8 - CAD28 D9 - CAD30 D10- CAD31 CD2- CCD2 GND CCBE0#/CE1# CCBE1#/A8 CCBE2#/A12 CCBE3#/REG# CPAR/A13 H13 E11 A11 B7 D13 A_CC/BE0# A_CC/BE1# A_CC/BE2# A_CC/BE3# A_CPAR AVCC AVPP CB@CB1410 D5 B9 B12 A2 J13 E10 M12 N12 VPPD1 VPPD0 RSVD/D2 RSVD/D14 RSVD/A18 CSTOP#/A20 CDEVSEL#/A21 CTRDY#/A22 CIRDY#/A15 CFRAME#/A23 U6 C B 69 70 71 72 73 74 CB@SANTA-1310671-68P AVCC +3V AVPP R_A_CCLK AVCC CB@4.7U_6 CSERR#/WAIT# CPERR#/A14 M13 N13 VCCD1# VCCD0# SUSPEND# SPKROUT RI_OUT#/PME# L11 M9 L8 M10 G_RST# B1 A1 F4 +3V AVCC C265 CB@4.7U_6 AVPP C273 C269 C267 CB@.1U_4 CB@.1U_4 CB@.1U_4 C268 CB@4.7U_6 4 R272 CB@10_4 A_CCLK A_CRST# A_CCLKRUN# A_CFRAME# A_CIRDY# A_CTRDY# A_CDEVSEL# A_CSTOP# A_CPERR# A_CSERR# A_CREQ# A_CGNT# A_CBLOCK# A_CINT# A_CSTSCHG A_CAUDIO A +3V A_CCLK A_CIRDY# A_CC/BE2# A_CAD18 A_CAD20 A_CAD21 A_CAD22 A_CAD23 A_CAD24 A_CAD25 A_CAD26 A_CAD27 A_CAD29 A_CRSVD/D2 A_CCLKRUN# VPPD0 VPPD1 CB@ENE CP-2211 +5V GND D3 - CAD0 D4 - CAD1 D5 - CAD3 D6 - CAD5 D7 - CAD7 CE1- CCBE0 A10- CAD9 OE - CAD11 A11- CAD12 A9 - CAD14 A8 - CCBE1 A13- CPAR A14- CPERR WE/PGM - CGNT RDY/BSY,IRQ*INT VCC +3V U8 +3V D3 H2 L4 M8 K11 F12 C10 B6 H=1.4mm H=2mm IDSEL CBE0# CBE1# CBE2# CBE3# PAR PCIGNT# PCIREQ# N5 N1 J3 E1 M2 PCICLK PCIRST# CBE0# CBE1# CBE2# CBE3# PAR GND1 GND2 GND3 GND4 GND5 GND6 GND7 GND8 [15,22] CBE0# [15,22] CBE1# [15,22] CBE2# [15,22] CBE3# [15,22] PAR C12 B13 A13 A12 B11 B A5 C13 : GNT1# CGNT#/WE# CREQ#/INPACK# Grant Indicate H1 G4 PCM_SUS# : INTC# Request Indicate : REQ1# VCCA1 VCCA2 VCC8 VCC9 VCC10 : AD20 Interrupt Pin AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 AVPP PCMCIA SOCKET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 A_CAD0 A_CAD1 A_CAD3 R284 A_CAD5 A_CAD7 CB@43K_6 A_CC/BE0# A_CAD9 A_CAD11 A_CAD12 A_CAD14 A_CC/BE1# A_CPAR A_CPERR# A_CGNT# A_CINT# AVCC G13 A7 D12 C8 B4 ID Select N8 K7 L7 N7 M7 N6 M6 K6 M5 L5 K5 M4 K4 N3 M3 N2 J2 J1 H4 H3 G3 G2 F1 F2 E2 E3 E4 D1 D2 D4 C1 C2 VCC1 VCC2 VCC3 VCC4 VCC5 VCC6 VCC7 ENE1410 AJ014100T41 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 F3 G1 K2 N4 L6 L9 H11 M1 L3 L2 L1 K3 K1 J4 C SERR# PERR# STOP# DEVSEL# TRDY# IRDY# FRAME# AD[31..0] [15,22] AD[31..0] AVCC A_CRSVD/D2 A_CRSVD/D14 A_CRSVD/A18 PCM_IDSEL FRAME# IRDY# TRDY# DEVSEL# STOP# PERR# SERR# [15,22] FRAME# [15,22] IRDY# [15,22] TRDY# [15,22] DEVSEL# [15,22] STOP# [15,22] PERR# [15,22] SERR# VPPD1 VPPD0 +3V C11 B8 [15,22] PCIRST# [2] PCLK_PCM CN15 T82 T84 [15] REQ1# [15] GNT1# PCM_PME# T85 T83 T100 CB@.1U_4 CB@.1U_4 CB@.1U_4 CB@.1U_4 CB@.1U_4 D VCCD1# VCCD0# CB@0_4 GND GND GND GND GND GND INTC# SERIRQ PCI_PME# R344 PCMSPK CB_RSMRST# REQ1# GNT1# AD20 R236 PCIRST# PCLK_PCM [15] INTC# [16,22,23,26] SERIRQ [15,22] PCI_PME# [24] PCMSPK C243 CAUDIO/BVD2/SPKR# CSTSCHG/BVD1/STSCHG# CINT#/READY/IREQ# CBLOCK#/A19 C360 B5 C5 D6 D11 C256 M11 N11 L10 N10 K9 N9 K8 C242 CB@43K_4 C361 MFUNC6 MFUNC5 MFUNC4 MFUNC3 MFUNC2 MFUNC1 MFUNC0 D C271 CB@.1U_4 3 2 A Quanta Computer Inc. PROJECT : BU1 Santa Rosa Size Document Number Date: Monday, March 26, 2007 Rev 1A PCMCIA(CB1410) -OPTION Sheet 1 21 of 33 B .1U_4 C213 .01U_4 C158 10U_6 .01U_4 .01U_4 VCC_ROUT_832 4 C170 C114 .01U_4 .01U_4 C115 .47U_4 10 20 27 32 41 128 VCC_PCI1 VCC_PCI2 VCC_PCI3 VCC_PCI4 VCC_PCI5 VCC_PCI6 61 VCC_RIN 16 34 64 114 120 C133 .47U_4 VCC_3V AD17 R163 150/F_4 R5C833_IDSEL PowerOnReset for Vcc [15,21] PAR [15,21] CBE3# [15,21] CBE2# [15,21] CBE1# [15,21] CBE0# +3VSUS PCLK_R5C833 R5C833_IDSEL R177 22K_4 GRST#_832 [15] REQ0# [15] GNT0# [15,21] FRAME# [15,21] IRDY# [15,21] TRDY# [15,21] DEVSEL# [15,21] STOP# [15,21] PERR# [15,21] SERR# R116 *22_4 C156 .1U_4 C104 *22P_4 GRST#_832 [15,21] PCIRST# [2] PCLK_R5C833 125 126 127 1 2 3 5 6 9 11 12 14 15 17 18 19 36 37 38 39 40 42 43 44 46 47 48 49 50 51 52 53 33 7 21 35 45 8 AD31 AD30 AD29 AD28 AD27 AD26 AD25 AD24 AD23 AD22 AD21 AD20 AD19 AD18 AD17 AD16 AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 PAR C/BE3# C/BE2# C/BE1# C/BE0# IDSEL 124 123 23 24 25 26 29 30 31 REQ# GNT# FRAME# IRDY# TRDY# DEVSEL# STOP# PERR# SERR# 71 119 GBRST# PCIRST# 121 PCICLK [15,21] PCI_PME# 70 [16,26] CLKRUN# 117 1394_XIN 2 22P_4 94 H=1.2mm GND1 GND2 GND3 GND4 GND5 GND6 GND7 GND8 GND9 GND10 AGND1 AGND2 AGND3 AGND4 AGND5 HWSPND# C121 *.01U_4 1 22P_4 1394_XOUT FIL0_PWR 96 FIL0 R5C832 stuff only R115 C113 10K/F_4 .01U_4 REXT 101 VREF_PWR 100 97 99 102 103 107 111 69 U4 4 R181 10K_4 When HWSPND# is controlled by system, the pull-up resistor(R4059) dose not need to apply. C206 5 EN 3 GND 2 VO 1 IN IN *1U_4 D7 832_SUS# *BAS316 2 1 2.2U_6 C125 C120 C117 .01U_4 .01U_4 .01U_4 MC_PWR_CTRL_0 VCC_XD C232 VCC_XD CN28 XD_D0/MS_D0/SD_D0 XD_D1/MS_D1/SD_D1_C XD_D2/MS_D2/SD_D2_C XD_D3/MS_D3/SD_D3 XD_RE#/CLK XD_WE#/MS_BS/SD_CMD SD_CDZ XD_R/B#/SD_WP# 58 R195 10K_4 55 R198 10K_4 UDIO5 57 R197 R196 UDIO3 UDIO4 65 59 SCL_CARD SDA_CARD UDIO2 56 UDIO1 60 UDIO0/SRIRQ# 72 SERIRQ [16,21,23,26] INTA# 115 INTA# [15] INTB# 116 INTB# [15] 100K_4 *100K_4 XD_D0/MS_D0/SD_D0 XD_D1/MS_D1/SD_D1 XD_D2/MS_D2/SD_D2 XD_D3/MS_D3/SD_D3 XD_RE#/CLK MS_CDZ XD_WE#/MS_BS/SD_CMD Default setting: INTA# is assert to 1394 INTB# is assert to Cardreader 21 31 34 9 11 25 15 39 41 SD-VCC SD-DAT0 SD-DAT1 SD-DAT2 SD-DAT3 SD-CLK SD-CMD SD-C/D SD-WP 19 29 40 SD-VSS1 SD-VSS2 SD-GND 12 22 24 20 16 14 18 26 MS-VCC MS-DATA0 MS-DATA1 MS-DATA2 MS-DATA3 MS-SCLK MS-INS MS-BS 10 28 42 66 MS-VSS1 MS-VSS2 GND1 XD-VCC 38 XD-CD XD-R/B XD-RE XD-CE XD-CLE XD-ALE XD-WE XD-WP 2 3 4 5 6 7 8 13 XD_CDZ XD_R/B#/SD_WP# XD_RE#/CLK XD_CE# XD_CLE XD_ALE XD_WE#/MS_BS/SD_CMD XD_WPO# XD-D0 XD-D1 XD-D2 XD-D3 XD-D4 XD-D5 XD-D6 XD-D7 23 27 30 32 33 35 36 37 XD_D0/MS_D0/SD_D0 XD_D1/MS_D1/SD_D1 XD_D2/MS_D2/SD_D2 XD_D3/MS_D3/SD_D3 XD_D4 XD_D5 XD_D6 XD_D7 XD-GND1 XD-GND2 GND2 1 17 43 3 +3VSUS 22ohm/1A C118 C390 C109 10U_6 .1U_4 .01U_4 1000P_4 98 106 110 112 TPBIAS0 TPBN0 TPBP0 TPAN0 TPAP0 113 104 105 108 109 TPBIAS0 TPB0N TPB0P TPA0N TPA0P MDIO17 MDIO16 MDIO15 MDIO14 MDIO13 MDIO12 MDIO11 MDIO10 87 92 89 91 90 93 81 82 XD_D7 XD_D6 XD_D5 XD_D4 XD_D3/MS_D3/SD_D3 XD_D2/MS_D2/SD_D2 XD_D1/MS_D1/SD_D1 XD_D0/MS_D0/SD_D0 MDIO05 MDIO08 MDIO19 MDIO18 MDIO02 MDIO03 75 88 83 85 78 77 XD_WPO# XD_WE#/MS_BS/SD_CMD XD_ALE XD_CLE XD_CE# XD_R/B#/SD_WP# MDIO00 80 SD_CDZ MDIO01 79 MS_CDZ MDIO09 MDIO04 MDIO06 MDIO07 84 76 74 73 MS_SD_CLK MC_PWR_CTRL_0 TP_XD_LED# RSV 1394 Reserve MS DUO card issue (For A-test only) BK1608HS220 C111 AVCC_PHY1 AVCC_PHY2 AVCC_PHY3 AVCC_PHY4 REXT VREF L4 TPBIAS0 R376 0_4 R114 Q28 XD_D1/MS_D1/SD_D1 R355 3 1 *10K_4 XD_D1/MS_D1/SD_D1_C XD_D2/MS_D2/SD_D2_C R113 1394@56.2/F_4 1394@56.2/F_4 2 D5 2 D6 SD_CDZ AS CLOSE AS POSSIBLE TO R5C833 *2N7002E Q26 3 XD_D2/MS_D2/SD_D2 1394@.01U_4 2 TPB0P TPB0N RN2 R112 R111 1394@56.2/F_4 1394@56.2/F_4 1394_COM *2N7002E 10K_4 XD_CDZ RN1 1 R180 1 BAS316 1 BAS316 R152 TPA0P TPA0N R354 0_4 R389 L1394_TPA0+ L1394_TPA0- L1394_TPB0+ 4 L1394_TPB02 1394@0_4P2R_S 3 1 1394@*CL-2M2012-121JT 1 1 2 2 4 4 3 3 L21 1394@270P_4 1394@5.1K/F_4 56.2/F_4 XD_RE#/CLK XD_RE#/CLK should TP_XD_LED# [25] shield GND. EEPROM H=1.4mm * NOT Use EEPROM : CN32 ==>UDIO5 need pull-high. * Use EEPROM : L1394_TPB0L1394_TPA0L1394_TPA0+ L1394_TPB0+ +3VSUS +3VSUS Close to CONN. SD_CDZ L20 1394@0_4P2R_S 1 2 3 4 C392 ==>UDIO5 need pull-down. XD_WE#/MS_BS/SD_CMD R144 *2.7K_4 XD_D0/MS_D0/SD_D0 R156 *2.7K_4 C137 C139 XD_D1/MS_D1/SD_D1 R159 *2.7K_4 *270P_4 *270P_4 XD_D2/MS_D2/SD_D2 R142 *2.7K_4 XD_D3/MS_D3/SD_D3 R143 *2.7K_4 MS_CDZ SDA_CARD SCL_CARD R193 R194 10K_4 10K_4 5 1 3 4 2 6 7 8 1 1394@1394-C13118-102-4P-V Quanta Computer Inc. Reduced external noise by FAE confirm PROJECT : BU1 Santa Rosa Size SD can't recognize issue in ES1 sample Date: B C99 1394@.33U_6 1394@*CL-2M2012-121JT 4 4 3 3 1 1 2 2 Q27 2 +3VSUS Close to CONN. GRST# C112 *2N7002E +5V 1 A C224 150K_4 VCC_XD VCC PCLK(33MHz) R218 *G5241T1U LPC_PD# [16] XDEN >60 ns >100 ns VCC_XD VCC_XD *4.7U_6 1394_AVCC R5C833 PRST# 2 4 +3VSUS +3VSUS R5C833 AS CLOSE AS POSSIBLE TO R5C833 and GUARD GND > 1 ms 4 13 22 28 54 62 63 68 118 122 MSEN TEST XI XO Q7 MC_PWR_CTRL_0# MC_PWR_CTRL_0 86 CLKRUN# 95 10K_4 3 *CARD_READER_PROCONN-MXP038-A0-4010 better than 50ppm C123 Q6 +3VSUS 24.576MHz Y1 2 R207 30mil PME# U2A C124 10U_6 AO3403 IEEE1394/SD 3 When GRESET# is controlled by system, the pull-up resistor and capacitor do not need to apply. C179 .01U_4 VCC_ROUT1 VCC_ROUT2 VCC_ROUT3 VCC_ROUT4 VCC_ROUT5 PCI / OTHER AD17 INTA#,B# C131 2N7002 [15,21] AD[31..0] REQ0# GNT0# +3VSUS 67 1 VCC_MD AD31 AD30 AD29 AD28 AD27 AD26 AD25 AD24 AD23 AD22 AD21 AD20 AD19 AD18 AD17 AD16 AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 CARDREADER POWER 5 IN 1 CARD READER If VCC_3V tied to +3V, PME# function is not supported U2B 3 .01U_4 C116 E 2 10U_6 C126 2 C129 D 2 C169 +3VSUS 3 C207 C R5C832 : AJ5C8320H26 R5C833 : AJ5C8330H05 1 +3V 1 A +3VSUS C D Document Number Rev 3A R5C832/833(5IN1/1394) Wednesday, March 28, 2007 E Sheet 22 of 33 4 C329 .1U_4 1U_6 R308 R309 R310 R311 *0_4 *0_4 *0_4 *0_4 +3V PLTRST#_PCIE R461 *0_4 PCIE_TXP1 PCIE_TXN1 [15] PCIE_TXP1 [15] PCIE_TXN1 D PCIE_RXP1 PCIE_RXN1 [15] PCIE_RXP1 [15] PCIE_RXN1 [26] uR_SOUT_CR [26] uR_SWD 2N7002E-LF Q23 [16,20,24] 3 PCIE_WAKE# 51 49 47 45 43 41 39 37 35 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1 CLK_PCIE_MINI CLK_PCIE_MINI# [2] CLK_PCIE_MINI [2] CLK_PCIE_MINI# +1.5V +3V_S5 CN20 SERIRQ LDRQ#1 PLTRST# PCLK_MINI [16,21,22,26] SERIRQ [14] LDRQ#1 [15,16,19,20,24,26] PLTRST# [2,26] PCLK_DEBUG 0_4 0_4 0_4 WCS_CLKR WCS_DATR 1 NC C-Link_RST C-Link_DAT C-Link_CLK GND NC NC GND GND PETp0 PETn0 GND GND PERp0 PERn0 GND NC NC +3.3V GND +1.5V LED_WPAN# LED_WLAN# NC NC USB_D+ USB_DGND SMB_DATA SMB_CLK +1.5V GND +3.3Vaux PERST# W_DISABLE# GND GND REFCLK+ REFCLKGND CLKREQ# BT_CHCLK BT_DATA WAKE# NC NC NC NC NC +1.5V GND +3.3V +1.5V 52 50 48 46 44 42 40 38 36 34 32 30 28 26 24 22 20 18 C348 C350 C330 C349 C351 .1U_4 10U_8 .001U_4 .1U_4 10U_8 +3V 4 2 C331 R481 R467 R466 1 +3V RP46 USBP3+_C USBP3-_C R462 R331 R332 *0_4 0_4 0_4 R326 R327 0_4 WL_SMDATA 0_4 WL_SMCLK PLTRST# 0_4 R325 LFRAME#_PCIE LAD3_PCIE LAD2_PCIE LAD1_PCIE LAD0_PCIE 16 14 12 10 8 6 4 2 *0_4 *0_4 *0_4 *0_4 *0_4 R320 R321 R322 R323 R324 4.7KX2 USBP3+ [15] USBP3- [15] LFRAME# LAD3 LAD2 LAD1 LAD0 [2,13,16,19,24] Q20 2N7002E 3 SDATA 3 1 [16] CL_RST#1 [16] CL_DATA1 [16] CL_CLK1 +3VSUS 2 2 Mini PCI-E Card WLAN 3 D WL_SMDATA 1 PLTRST# [15,16,19,20,24,26] RF_EN [26] +3V LFRAME# [14,26] LAD3 [14,26] LAD2 [14,26] LAD1 [14,26] LAD0 [14,26] 2 5 [2,13,16,19,24] Q21 2N7002E 3 SCLK WL_SMCLK 1 +3V minipai-c15706-52p-ldv 2 +3V_S5 R291 WCS_CLK R314 WCS_DAT R315 [24] WCS_CLK [24] WCS_DAT 10K_4 BT@0_4WCS_CLKR BT@0_4WCS_DATR To BT +3G_VDD +3V 80ohm/4A L11 Peak: 2.75A +3G_VDD FBJ3216HS800 +3G_VDD 1 MINI-Card C306 10U/10V_8 C292 .1U_4 C289 .1U_4 C297 .47U_6 +3G_VDD C298 10P_4 2 C307 10U/10V_8 +1.5V C C CN21 [15] PCIE_TXP3 [15] PCIE_TXN3 PCIE_RXP3 PCIE_RXN3 [15] PCIE_RXP3 [15] PCIE_RXN3 15 13 11 9 7 5 3 1 [2] CLK_PCIE_MINI2 [2] CLK_PCIE_MINI2# GND REFCLK+ REFCLKGND CLKREQ# Reserved Reserved WAKE# +3.3V GND +1.5V LED_WPAN# LED_WLAN# LED_WWAN# GND USB_D+ USB_DGND SMB_DATA SMB_CLK +1.5V GND +3.3Vaux PERST# W_DISABLE# GND 52 50 48 46 44 42 40 38 36 34 32 30 28 26 24 22 20 18 UIM_VPP UIM_RESET UIM_CLK UIM_DATA UIM_PWR +1.5V GND +3.3V 16 14 12 10 8 6 4 2 GND 0_4 PCIE_TXP3 PCIE_TXN3 Reserved Reserved Reserved Reserved GND +3.3Vaux +3.3Vaux GND GND PETp0 PETn0 GND GND PERp0 PERn0 GND Reserved Reserved GND R460 51 49 47 45 43 41 39 37 35 33 31 29 27 25 23 21 19 17 USBP7+_R USBP7-_R R459 R294 R293 PLTRST# *0_4 0_4 0_4 USBP7+ [15] USBP7- [15] PLTRST# [15,16,19,20,24,26] MINI CARD SINK 1 2 3 HOLE13 H-C197D122P2-8 7 6 8 5 9 4 1 2 3 1 2 3 HOLE3 HOLE5 HOLE4 HOLE6 H-C165D122P2-8 H-C165D122P2-8 H-C165D122P2-8 H-C165D122P2-8 7 6 7 6 7 6 7 6 8 5 8 5 8 5 8 5 9 4 9 4 9 4 9 4 1 2 3 HOLE21 *H-C236D94P2-8 7 6 8 5 9 4 HOLE12 *H-TC295BC236D94P2-8 7 6 8 5 9 4 C512 1500P/X7R-50V_4 HOLE18 *H-C177D138P2-8 7 6 8 5 9 4 +3V VIN C510 1500P/X7R-50V_4 +3V +3V VIN +1.5V C511 1500P/X7R-50V_4 +3VSUS +5V_S5 +5V_S5 +1.5V +1.5V +5V_S5 +5V +5V C519 C508 C514 C509 C513 C516 .1U_4 .1U_4 .1U_4 .1U_4 .1U_4 .1U_4 +3VPCU +3VPCU +3VPCU +3VPCU AVDD18 +1.05V 1 2 3 HOLE15 *H-C197D94P2-8 7 6 8 5 9 4 MDC PCMCIA SINK HOLE11 H-C165D122P2-8 7 6 8 5 9 4 C549 C550 C551 C515 C517 C518 C528 C524 C523 C520 C521 C522 .1U_4 .1U_4 .1U_4 .1U_4 .1U_4 .1U_4 .1U_4 .1U_4 .1U_4 .1U_4 .1U_4 .1U_4 HOLE22 *H-C177D138P2-8 7 6 8 5 9 4 1 2 3 1 2 3 1 2 3 HOLE19 *H-C189D189N 7 6 8 5 9 4 1 2 3 HOLE2 *H-C236D106P2-8 7 6 8 5 9 4 1 2 3 1 2 3 1 2 3 HOLE10 *H-C236D94P2-8 7 6 8 5 9 4 1 2 3 1 2 3 1 2 3 HOLE16 *H-C315D94P2-8 7 6 8 5 9 4 VIN 1 2 3 HOLE20 *H-C236D94P2-8 7 6 8 5 9 4 HOLE17 *H-C177D138P2-8 7 6 8 5 9 4 1 2 3 HOLE1 *H-C236D106P2-8 7 6 8 5 9 4 B HOLE14 H-C197D122P2-8 7 6 8 5 9 4 PCMCIA SINK MB SINK HOLE7 *H-C236D94P2-8 7 6 8 5 9 4 EMI 1 2 3 HOLE9 H-C165D122P2-8 7 6 8 5 9 4 1 2 3 1 2 3 HOLE8 H-C165D122P2-8 7 6 8 5 9 4 CPU SINK 1 2 3 NB SINK 1 2 3 B 54 53 3G@minipai-c15706-52p-ldv +3V +3V A A C547 C548 .1U_4 .1U_4 Quanta Computer Inc. PROJECT : BU1 Santa Rosa 5 4 3 2 Size Document Number Date: Thursday, March 29, 2007 Rev 3A MINI PCIE/HOLE Sheet 1 23 of 33 5 2 CAPSLED FN_F10 NUMLED [26] CAPSLED [26] FN_F10 [26] NUMLED 100Px4 CP3 R249 +3V C533 *15P_4 C537 *15p_4 U18 4 C535 *15P_4 BEEP [26] AMP_MUTE# [26] DIGVOL_UP [26] DIGVOL_DN [26] LED_LOGO [26] USB_EN2# SN74LVC1G86DCKR PAD1 EMIPAD134X71 T/P Finger Printer BLUETOOTH MODULE CONNECTOR L10 C279 4.7U_8 C274 .1U_4 1 2 BLM18PG181SN1D CN9 +5V CN11 BL121-28R-TAND-28P-L-BU1 TPDATA TPCLK R276 R275 0_4 0_4 C276 C275 *10P_4 6 5 4 3 2 1 FP@0_6 USBP4-_C FP@0_6 USBP4+_C R317 R316 [15] USBP4[15] USBP4+ 8 +5V_TP TPDATA_1 TPCLK_1 [15] USBP5+ [15] USBP5[23] WCS_CLK CN14 +3VSUS *10P_4 1 2 3 4 [23] WCS_DAT FP@88266-040XX-XXX-4P-R 1 2 3 4 5 6 7 8 9 10 WCS_CLK BT_RESET WCS_DAT +3V USB_DETACH BT@88266-100XX-XXX-10P-R 7 BT@*0_4 BT_RESET R271 *88058-6 [26] BT_EN MY3 MY2 MY1 MY0 8 6 4 2 Wire Cable 1.25mm Pitch BT@0_4 USB_DETACH R270 USB_DETACH: Low USB connect High USB disconnect Wire Cable 1.25mm Pitch CN10 RJ45/USB CN37 36 36 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 CN6 MY4_K MY2_K MX2_K MX1_K MY1_K MY0_K MX0_K MX3_K MY5_K MY6_K MX5_K MX6_K MX4_K MY12_K MY7_K MY3_K MX7_K MY13_K MY9_K MY8_K MY11_K MY10_K MY14_K MY15_K K_LED_P_K CAPSLED_K FN_F10_K NUMLED_K 196130-340201-34P-R 0_4 2 3 IN1 IN2 4 1 9 EN# GND GND-C OUT3 OUT2 OUT1 OC# 8 7 6 USBPWR1 5 R333 *6.34K/F_6 1 2 3 4 5 6 7 8 9 10 11 12 USBPWR1 USBP2USBP2+ MDI1+ MDI1MDI0+ MDI0- [15] USBP2[15] USBP2+ [20] MDI1+ [20] MDI1[20] MDI0+ [20] MDI0[20] LAN_ACT# [20] LAN_LINK# [20,23] AVDD18 C BL123-12R-12P-L-BU1 FFC Cable 1.0mm Pitch Wire Cable 1.25mm Pitch +3V [21] PCMSPK +3V BUTTONS ON KB COVER C540 D32 2 C541 .1U_4 PCM-2 3 PCM-1 C542 0.1U/X7R-50V_6 CN13 1 .1U_4 2 1 2 PCM-3 3 12 1 2 3 4 5 6 7 8 9 10 11 PCMSPK_DELAY 4 CHN217 D33 C544 0.1U/X7R-50V_6 U30 TC7SH08FU C545 0.1U/X7R-50V_6 R492 10K_4 MY16 FR FF STOP PLAY/PAUSE MEDIDA WWW NBSWON# [26] MY16 [26] MX3 [26] MX2 [26] MX1 [26] MX0 [26] MEDIDA [26] WWW [26] NBSWON# C543 .1U_4 1 CHN217 PCM-4 29 88171-3400L-34P-R R336 [26] USB_EN# C356 .1U_4 BL123-06R-6P-L 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 35 +5VPCU 7 30 MY4_K MY2_K MX2_K MX1_K MY1_K MY0_K MX0_K MX3_K MY5_K MY6_K MX5_K MX6_K MX4_K MY12_K MY7_K MY3_K MX7_K MY13_K MY9_K MY8_K MY11_K MY10_K MY14_K MY15_K K_LED_P_K CAPSLED_K FN_F10_K NUMLED_K U12 G545B2RD1U 80mil 3 MY4_K MY2_K MX2_K MX1_K MY1_K MY0_K MX0_K MX3_K MY5_K MY6_K MX5_K MX6_K MX4_K MY12_K MY7_K MY3_K MX7_K MY13_K MY9_K MY8_K MY11_K MY10_K MY14_K MY15_K K_LED_P_K CAPSLED_K FN_F10_K NUMLED_K +3V_S5 6 5 4 3 2 1 C 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 CN19 8 +5V_TP TPDATA_1 TPCLK_1 CN5 5 100Px4 CP6 D BL121-14R-TAND-14P-L-BU1-BU1 FFC Cable 0.5mm Pitch 100Px4 CP5 7 5 3 1 1 PCMSPK_DELAY 2 Wire Cable 1.25mm Pitch MY7 MY6 MY5 MY4 8 6 4 2 C536 *15P_4 C534 *15P_4 29 150_4 K_LED_P SPKR [16] SPKR 5 ACZ_SDIN0 BT@88266-100XX-XXX-10P-R [26] TPDATA [26] TPCLK 7 5 3 1 ACZ_RST#_AUDIO 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 12 MY15 MY14 MY13 MY12 +5V +3V 0_4 *4.7u_4 11 8 6 4 2 100Px4 CP2 7 5 3 1 MY15 MY14 MY13 MY12 MY11 MY10 MY9 MY8 MY7 MY6 MY5 MY4 MY3 MY2 MY1 MY0 [15] USBP0[15] USBP0+ [15] USBP1[15] USBP1+ [14] ACZ_RST#_AUDIO [14] ACZ_SYNC_AUDIO [14] ACZ_SDIN0 [14] BIT_CLK_AUDIO [14] ACZ_SDOUT_AUDIO C393 BIT_CLK_AUDIO 13 MX5 MX6 MX4 MX7 MY15 MY14 MY13 MY12 MY11 MY10 MY9 MY8 MY7 MY6 MY5 MY4 MY3 MY2 MY1 MY0 1 2 3 4 5 6 7 8 9 10 +5V_S5 +5V_S5 R396 14 8 6 4 2 100Px4 CP1 7 5 3 1 [26] [26] [26] [26] [26] [26] [26] [26] [26] [26] [26] [26] [26] [26] [26] [26] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 CN7 ACZ_SYNC_AUDIO CN12 6 MX2 MX1 MX0 MX3 MX0 MX1 MX2 MX3 MX4 MX5 MX6 MX7 MY4 MY2 MX2 MX1 MY1 MY0 MX0 MX3 MY5 MY6 MX5 MX6 MX4 MY12 MY7 MY3 MX7 MY13 MY9 MY8 MY11 MY10 MY14 MY15 K_LED_P CAPSLED FN_F10 NUMLED 5 8 6 4 2 [26] [26] [26] [26] [26] [26] [26] [26] MX0 MX1 MX2 MX3 MX4 MX5 MX6 MX7 3 MX6 MX4 MX7 MX3 +3V 1 1 2 3 4 5 7 5 3 1 B 1 ACZ_SDOUT_AUDIO 12 10 9 8 7 6 10KX8 D 3 Audio Board 30 11 INT KeyBoard RP43 MX5 MX0 MX1 MX2 4 CN8 +3VPCU R490 3 4 R491 86.6K/F_4 C546 0.1U/X7R-50V_6 BL121-28R-TAND-28P-L-BU1 SW1 PCM-5 200K/F_4 1 2 BL123-10R-TAND-10P-L-BU1 NBSWON# FFC Cable 1.0mm Pitch B Keyboard Side New card (BTO) NEW CARD'S POWER SWITCH +NEW_3V CN16 4 2 [15] PCIE_TXP2 [15] PCIE_TXN2 RP44 SDATA SDATA 3 1 3.3VIN 3.3VIN +3V_S5 18 AUXIN 16 15 NEW_SMDATA NEW@2N7002E +1.5V +NEW_3V Q14 [2,13,16,19,23] SCLK SCLK 3 PLTRST# 2 [15,16,19,20,23,26] 1 NEW_SMCLK NEW@2N7002E PLTRST# 3.3VOUT 3.3VOUT +NEW_3V AUXOUT 17 +NEW_3VAUX +NEW_1.5V 1.5VIN 1.5VIN 1.5VOUT 1.5VOUT 14 13 1 2 SYSRST# SHDN# 3 12 11 19 9 10 STBY# CPPE# CPUSB# RCLKEN NC GND PERST# OC# 8 20 [16,20,23] PCIE_WAKE# PCIE_WAKE# CPPE# [2] NEW_CLKREQ# +NEW_3V PERST# +NEW_3VAUX Q13 NEW@*DTC144EU 3 1 +NEW_1.5V CPPE# CPUSB# PERST#_R NEW_SMDATA NEW_SMCLK R288 PERST# R305 NEW@0_4 NEW@28.7K/F CPUSB# C319 NEW@3300P_4 CPPE# : ( Internal Pull Up , active low when card support PCIE ) A [2] CLK_PCIE_NEW [2] CLK_PCIE_NEW# +3V_S5 6 7 2 +3V 4 5 3 1 [2,13,16,19,23] [15] PCIE_RXP2 [15] PCIE_RXN2 H=1.2mm U9 NEW@TPS2231PWG4 NEW@4.7KX2_4 2 Q15 [15] USBP6+ [15] USBP6- R286 R287 NEW@0_4 NEW@0_4 USBP6+_R USBP6-_R 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 CPUSB# : ( Internal Pull Up , active low when card support USB ) +3V C310 C309 C337 +NEW_3V NEW@.1U_4 NEW@.1U_4 NEW@.1U_4 C299 C311 C313 Quanta Computer Inc. C339 C338 PROJECT : BU1 Santa Rosa NEW@.1U_4 NEW@.1U_4 5 +NEW_1.5V C336 C335 NEW@.1U_4 A +1.5V +NEW_3VAUX C334 29 30 NEW@13160171-1 SHDN# : ( Internal Pull Up ) +3V_S5 GND1 GND29 PETp0 GND30 PETn0 GND2 PERp0 PERn0 GND3 REFCLK+ REFCLKCPPE# CLKREQ# +3.3V1 +3.3V2 PERST# +3.3VAUX WAKE# +1.5V1 +1.5V2 SMB_DATA SMB_CLK RESERVED1 RESERVED2 CPUSB# USB_D+ USB_DGND4 4 NEW@4.7U_8 NEW@.1U_4 3 NEW@.1U_4 NEW@4.7U_8 NEW@.1U_4 2 Size Document Number Date: Thursday, March 29, 2007 Rev 3A New Card/Keyboard/WTB Sheet 1 24 of 33 5 4 3 2 1 ODD / HDD +5VPCU R301 330_4 -BATLED1 R303 220_4 1 LED5 BATLED1# [26] LED_Y_LTST-C190KFKT 330_4 330_4 2 PWRLED# [26] 1 LED3 LED_Y_LTST-C190KFKT TP_XD_LED#_R R328 150_4 CARDREADER TP_XD_LED# [22] +5V Blue R307 LED9 2 1 150_4 RF_LED_R R242 150_4 W-LAN&BT RF_LED [26] LED_Y_LTST-C190KFKT Amber POWER D Power On --> Blue S3 --> Orange +5V LED6 LED_B_LTST-C190TBKT 2 [26] SUSLED_EC R318 Q19 DTC144EU DISK LED 1 R297 R289 3 LED_B_LTST-C190TBKT -PWRLED 1 1 LED_B_LTST-C190TBKT 10K_4 1 LED2 2 BATERRY Full Charge --> Blue Charging --> Orange +3VPCU D LED7 2 2 2 +5V BATLED0# [26] IDE_LED LED4 LED_B_LTST-C190TBKT -BATLED0 2 1 ACIN LED 1 10K_4 +5VPCU IDE_LED# 3 R255 LED1 2 R252 330_4 LED_B_LTST-C190TBKT 2 +5VPCU Q11 ACIN 2 D22 1 BAS316 ACIN [26,27] R319 MMBT3906 1 +3VPCU D28 DA204U ODD_LED# [19] Q12 DTC144EU 2 D23 1 BAS316 10K_4 IDELED +5V Q22 MMBT3906 1 3 +5VPCU BATLED1# SATA_LED# [14] 2 C C D29 DA204U 1 3 BATLED0# 2 D30 DA204U 1 3 +5V PWRLED# 2 D31 DA204U 1 3 TP_XD_LED# +3VPCU 2 R342 10K_4 SW2 2 B W_LAN&BT / 3G DC-IN / Power / Battery /HDD(ODD) / Bridge Media access (Amber) (Blue) (Blue) (Blue) (Amber) (Blue) (Blue) B 1 [26] KILL_SW 3 +3VPCU (Blue) (Amber) D34 *DA204U SW-NSS506-212F-AABD1B 1 3 2 MDC +1.5V +1.5V +1.5V [4,9,17,23,24,32] R191 *0_6 CN31 [14] ACZ_SDOUT_MDC [14] ACZ_SYNC_MDC [14] ACZ_SDIN1 [14] ACZ_RST#_MDC A R174 33_4 MDC_SDIN1 1 3 5 7 9 11 GND AC_SDO GND AC_SYNC AC_SDI AC_RST# +3V RSV RSV 3.3V GND GND AC_BCLK 2+1.5V_MDC 4 6 8 10 12 +3V_S5 R182 0_6 C151 .1U-10V_4 A BIT_CLK_MDC [14] ACS_88018-124L R171 *22_4 C162 *10P-50V_4 Quanta Computer Inc. PROJECT : BU1 Santa Rosa C160 *10P-50V_4 Size Document Number Rev 3A TP/SW/LED Date: 5 4 3 2 Sunday, April 01, 2007 Sheet 1 25 of 33 5 4 3 2 DNBSWON#_uR DIGVOL_UP DIGVOL_DN SM BUS PU C262 .1U_4 +3VPCU +A3VPCU [16,22] CLKRUN# [14] GATEA20 121 GA20 122 KBRST SCI#_uR 29 ECSCI D18 [16] SCI# BAS316 6 C285 *10P_4 124 [15,16,19,20,23,24] PLTRST# PLTRST# T96 [16,21,22,23] 08/10 FAE: SMI DOESN'T NEED DIODE SERIRQ 7 TP_uR_PWUREQ# 123 PWUREQ SERIRQ 125 SERIRQ 9 [16] KBSMI# [24] [24] [24] [24] [24] [24] [24] [24] MX0 MX1 MX2 MX3 MX4 MX5 MX6 MX7 [24] MY0 [24] MY1 [24] MY2 [24] MY3 [24] MY4 [24] MY5 [24] MY6 [24] MY7 [24] MY8 [24] MY9 [24] MY10 [24] MY11 [24] MY12 [24] MY13 [24] MY14 [24] MY15 [24] MY16 FOLLOW INTEL ME-EC INTERFACE SPECIFICATION, 2ND_SMB IS DEDICATED FOR ICH8 CONTROLLER LINK BUS. MX0 MX1 MX2 MX3 MX4 MX5 MX6 MY16 MY17 KBSOUT0/JENK KBSOUT1/TCK KBSOUT2/TMS KBSOUT3/TDI KB KBSOUT4 KBSOUT5/TDO KBSOUT6/RDY KBSOUT7 KBSOUT8 KBSOUT9 KBSOUT10 KBSOUT11 KBSOUT12/GPIO64 KBSOUT13/GPIO63 KBSOUT14/GPIO62 KBSOUT15/GPIO61/XOR_OUT KBSOUT16/GPIO60 KBSOUT17/GPIO57/HGPIO03 72 71 10 11 12 13 PSCLK1 PSDAT1 PSCLK2/GPIO26 PSDAT2/GPIO27 PSCLK3/GPIO25 PSDAT3/GPIO12 77 32KX1/32KCLKIN 8768_32KX2 20M_6 H=2.5mm Y3 4 3 C362 15P_4 SCL1 SDA1 SCL2 SDA2 4 64 95 93 94 119 109 120 65 66 15 16 17 20 21 22 23 24 25 26 27 28 91 110 112 ACIN [25,27] NBSWON# [24] LID591# [18] SUSB# [16] EC_FPBACK# [18] LANVCC_EN [20] BATLED0# [25] BATLED1# [25] PWRLED# [25] VRON [29] MAINON [19,30,31,32] RF_LED [25] AMP_MUTE# [24] ID [27] SUSON [31,32] T99 T147 D/C# [27] S5_ON [28] BT_EN [24] TA1/GPIO56 TA2/GPIO20 TB1/GPIO14/HGPIO4 31 117 63 A_PWM0 A_PWM1/GPIO21 B_PWM0/GPIO13 32 118 62 TIMER SPI 32KX2 PS/2 SPI_DI/GPIO77 SPI_DO/GPO76/SHBM SPI_SCK/GPIO75 WWW MEDIDA DIGVOL_UP DIGVOL_DN HWPG DNBSWON#_uR 4.7K_4 4.7K_4 4.7K_4 4.7K_4 4.7K_4 4.7K_4 D 08/10 FAE: ADD ONE GAD PAD UNDER X'TAL, AND KEEP CLEANCE. 4.7K_4 BAS316 Index Data 00 XOR TREE TEST MODE 01 CORE DEFINED 10 2Eh 2Fh 11 164Eh 164Fh SHBM=0: Enable shared memory with host BIOS [25] BADDR0 BADDR0 R278 10K_4 BADDR1 SOUT_CR_DEBUG R273 *10K_4 SHBM RF_EN R265 10K_4 1/13 Comfirm by vendor mail : Disabled ('1') if using FWH device on LPC. Enabled ('0') if using SPI flash for both system BIOS and EC firmware ID H=1.75mm 6 5 7 A0 A1 A2 1 2 3 VCC GND 8 4 SCL SDA WP 24LC08BT-I DNBSWON# [16] LED_LOGO [24] C +3VPCU U13 MBCLK MBDATA C257 .1U_4 ADDRESS: A0H 84 83 82 GS@*0_4 GS@*0_4 HDPACT [16,19] HDPINT [16,19] FANSIG [3] SPI FLASH CONTRAST [18] KILL_SW [25] CRT_SENSE# RF_EN 86 87 90 92 SPI_SDI_uR SPI_SDO_uR SPI_CS0#_uR SPI_SCK_uR SWD/GPIO66 81 SWD_DEBUG CLKOUT/GPIO55 30 VREF D14 R456 R457 F_SDI F_SDO F_CS0 F_SCK VCC_POR R266 I/O ADDRESS SETTING TEMP_MBAT [27] INT_LVDS_BLON [6,18] WWW [24] MEDIDA [24] DIGVOL_UP [24] DIGVOL_DN [24] 0_4 BADDR0 RSMRST#_uR FIU R482 SUSLED_EC 75 73 74 113 14 114 111 IRRX1/GPIO72 IRRX2_IRSL0/GPIO70 IRTX/GPIO71 SIN_CR/CIRRX/GPIO87 GPIO34/CIRRX2 CIRTX/GPIO16/HGPIO04 SOUT_CR/GPO83/BADDR1 SMB WPC8763LDG R341 33K_6 1 2 32.768KHZ 79 GPIO01 GPIO03 GPIO06/HGPIO06 GPIO07/HGPIP07 GPIO23 GPIO30 GPIO31 GPIO32 GPIO33 GPIO36 GPIO40 GPIO42/TCK GPIO GPIO43/TMS GPIO44/TDI GPIO45 GPIO46/TRST GPO47/JEN0 GPIO50/TDO GPIO51 GPIO52/RDY GPIO53 GPIO81 GPO82/HGPIO00/TRIS GPO84/HGPIO01/BADDR0 IR [24] TPCLK [24] TPDATA [24] USB_EN2# [24] CAPSLED [24] FN_F10 [24] NUMLED R339 80 53 52 51 50 49 48 47 43 42 41 40 39 38 37 36 35 34 33 MBCLK 70 MBDATA 69 2ND_MBCLK 67 2ND_MBDATA 68 8768_32KX1 C358 15P_4 KBSIN0 KBSIN1 KBSIN2 KBSIN3 KBSIN4 KBSIN5 KBSIN6 KBSIN7 [3,18,27] MBCLK [3,18,27] MBDATA [19] 2ND_MBCLK [19] 2ND_MBDATA B 0810 FAE: CHECK X'TAL'S FOOTPRINT CEECK RESULT: OK SMI 54 55 56 57 58 59 60 61 R259 R258 R256 R257 R282 R283 I/O Address CC-SET [27] VFAN [3] LPC CRT_SENSE# BADDR1-0 DA0/GPI94 DA1/GPI95 DA2/GPI96 DA3/GPI97 D/A LREST H=1.6mm 101 105 106 107 CLKRUN/GPIO11/HGPIO02 LPCPD/GPIO10/HGPIO00 1/13 Comfirm by vendor mail: VBAT for keep PLL power let power up can quick. If no VBAT will switch to VCCpower. If PLL no power will cause boot time delay. 97 98 99 100 108 96 A/D LDRQ/GPIO24/HGPIO01 +3V AD0/GPI90 AD1/GPI91 AD2/GPI92 AD3/GPI93 AD4/GPIO05 AD5/GPIO04 VCORF [14] RCIN# 10U_8 08/10 FAE: 0.1UF AGND R285 *22_4 C LFRAME LAD0 LAD1 LAD2 LAD3 LCLK 8 C288 .1U_4 CRT_SENSE# [15,18] RF_EN [23] CELL-SET [27] 0_6 R254 PWROK_EC_uR R262 0_4 SOUT_CR_DEBUG R274 0_4 RSMRST# [16] SUSC# [16] ECPWROK [16] CCD_POWERON USB_EN# [24] uR_SOUT_CR H=2.16mm R463 33_4 SPI_SDI SPI_SDO_uR R464 33_4 SPI_SDO 5 SPI_SCK_uR R465 33_4 SPI_SCK 2 10K_4 VDD 8 HOLD 7 SO SI 6 SPI_CS0#_uR R343 +3VPCU U14 SPI_SDI_uR SCK 1 CE WP 3 VSS 4 C251 .1U_4 W25X80VSSIG +3VPCU 1/13 Comfirm by vendor mail : If the Southbridge enables 'Long Wait Abort' by default, the flash device should be 50MHz (or faster) [18] [23] EC_ME_ALERT: (Intel 08/28) Logic high = “AC present”, Logic low = “AC not present (DC operation)”. EC must not drive a high value on pin until SUS Well is fully powered to prevent leakage. AC/DC indication should be de-bounced by EC. R264 0_4 B uR_SWD [23] T95 85 VCC_POR# R267 104 VREF_uR R263 4.7K_4 +3VPCU +5V 0_4 +A3VPCU TPCLK TPDATA 0~AVCC power for DA pin power reference 44 PCLK_591 3 126 127 128 1 2 C284 .1U_4 R261 R260 10K_4 10K_4 08/14 FAE: Please connect VREF(uRider pin104) to +A3VPCU instead of +3VPCU. VCORF_uR LFRAME# LAD0 LAD1 LAD2 LAD3 PCLK_591 [14,23] LFRAME# [14,23] LAD0 [14,23] LAD1 [14,23] LAD2 [14,23] LAD3 [2] PCLK_591 +3VPCU MBCLK MBDATA 2ND_MBCLK 2ND_MBDATA WWW MEDIDA C291 .1U_4 BLM18AG601SN1 C264 VBAT U7 C272 .1U_4 +3V 8769AGND 102 C259 .1U_4 10U_8 AVCC C278 .1U_4 C266 .1U_4 GND1 GND2 GND3 GND4 GND5 GND6 C282 .1U_4 C260 5 18 45 78 89 116 C261 .1U_4 VCC1 VCC2 VCC3 VCC4 VCC5 C277 .1U_4 19 46 76 88 115 D L36 VDD BLM18AG601SN1 103 L8 C281 10U_8 1/13 Comfirm by vendor mail: VDD must power up after VCC/AVCC 1/13 Vendor mail: Dedicate cap for AVCC 1 C280 To Keyboard +3V 1/13 Comfirm by vendor mail : Connect to AGND 8769AGND L9 HZ0603B601R-00 [28] SYS_HWPG A [30] HWPG_1.05V [31] HWPG_1.8V [32] HWPG_1.5V INTERNAL KEYBOARD STRIP SET R281 10K_4 +3VPCU 8769AGND [32] HWPG_2.5V 1U_6 D16 BAS316 D21 BAS316 D17 BAS316 D19 BAS316 D20 BAS316 HWPG 08/10 FAE: L83 CAN CHANGE FROM BEAD TO SHORT. BUT, PLEASE PUT AGND & 32K CAP & AVCC CAP AT ONE POINT. ZS1 STILL USE BEAD FOR SAFE. MY0 MY16 MY17 DEBUG PORTS EC Debug Port CN17 1 2 3 4 +3V 1 2 3 4 CN18 *ACES_88231-0400 [2,23] PCLK_DEBUG -- DAISY CHAIN TOPOLOGY -- 5 4 3 10K_4 10K_4 10K_4 Reserved for LPC debug card +3VPCU SOUT_CR_DEBUG SWD_DEBUG R277 R279 R280 LAD0 LAD1 LAD2 LAD3 LFRAME# PLTRST# SERIRQ 10 9 8 7 6 5 4 3 2 1 A 10 9 8 7 6 5 4 3 2 1 Quanta Computer Inc. *ACS PROJECT : BU1 Santa Rosa 2 Size Document Number Date: Tuesday, March 27, 2007 Rev 3A EC-PC8763 Sheet 1 26 of 33 4 3 HI0805R800R-00_8 PL3 3 LITTLE-1206-7A PF2 1 2 2 1 2 PC49 .1U/X7R-25V_8 PL4 *LITTLE-1206-7A HI0805R800R-00_8 2 PC48 .1U/X7R-25V_8 1 2 PD6 PDS1040S 4 PC50 PC51 .1U/X7R-50V_8 .1U/X7R-50V_8 PC52 0.1U/X7R-25V_8 PR76 220K/F_6 PR75 220K/F_6 PD7 PR70 ACIN_1 [25,26] ACIN 6 2 5 1 PR73 33K_6 PC125 0.1U/X7R-25V_8 PR77 D 8 7 6 5 PR74 10K_6 0_6 D/C# [26] 4 PQ12 IMD2AT108 2 CSIN ZD12V PR69 PR71 6.8K/F_6 1 3 2 10K_6 PQ40 FDS6675BZ 1 2 3 3 PD5 RB500V 1 87288-044L 3 3 1 1 4 PQ41 SUD45P03-15-LF 2P PF1 1P PCN1 1 VIN 0.02_3720 PR72 VA D 2 4 5 PQ11 2N7002E CSIP 1 10K_6 VIN PC37 2.2U/X5R-10V_8 ISL6251_VDD 1 2 PR61 18_6 PR58 4.7_6 PC42 0.1U/X7R-50V_6 CSIN_1 PC126 10U/X6S-25V_1206 PC127 .1U/X7R-50V_8 PL14 HI0805R800R-00_8 PC46 4.7U/X5R-10_8 1 2 ISL6251_VDDP C 22 UGATE CSON 18 ISL6251_PHASE LGATE 14 ISL6251_LGATE PGND 13 PHASE PC38 23 0.1U/X7R-50V_6 ACPRN 47P/NPO-50V_4 SUYIN BATTERY B ADDRESS: 16H PR78 100_4 PR79 100_4 10K_6 +3VPCU ISL6251_VDD 6251EN PR57 10K_6 TEMP_MBAT PR56 *10K_6 TEMP_MBAT [26] 1 1 1 6251CELLS_1 MBCLK [3,18,26] PD8 ZD5.6V PR52 *10K_6 3 PR51 *100K_6 2 PR53 *100K_6 10 PQ10 *2N7002E PC43 *100P_4 VADJ CHLIM VRFE ICM 6 G2 3 5 S2 4 VA3 PL13 MPL73-6R8 PR139 .03_3720 6251LR 1 2 BAT-V 2.2_F_6 PR67 33K_6 CSOP PC122 PC123 10U/X6S-25V_1206 10U/X6S-25V_1206 CSON PC142 2200P_50V_6 Float = 4.2V / CELL ACLIM PU3 ISL6251A PR154 PR64 *514K_F_6 PR68 *514K_F_6 B CC-SET [26] LIM = 1/R2(((0.05/VREF=2.39)VACLM)+0.050) CURRNT LIMIT POINT = 3.750A 3.750A=1/0.02((0.05/2.365)Vaclm+0.05) Vaclm=1.1950V PR63 ICMNT PR62 3.3K/F_4 *100_4 PC41 .01U/X7R-16V_4 1 [26] CELL-SET 1 PQ9 *2N7002E 6251CELLS_1 ACLIM D1 2 VREF PR66 33K_6 PC47 100P_4 PC40 .01U/X7R-16V_4 6251CELLS_2 2 2 2 PC55 .01U/X7R-50V_6 8 0.1U/X7R-50V_6 PR80 MBDATA [3,18,26] PD9 ZD5.6V EN 7 PC56 11 ACSET PR60 10K_6 47P/NPO-50V_4 MBCLK 2 3 HI0805R800R-00_8 12 D1 1 7 S1/D2 PC124 .01U/X7R-50V_6 VREF PC54 2 PC53 6251ACSET 2 4 1 TEMP_MBAT PR59 130K/F_6 PL11 *3216FF20-1206-20A ID [26] BAT-V VCOMP 2 ICOMP 1 GND VADJ DCIN 6 ID 100P_4 24 6251VCOMP2 MBAT+ 10 1 2 11 3 4 5 6 7 12 8 9 13 DCIN HI0805R800R-00_8 PL12 PF4 CELLS CN26 6251VCOMP1 3216FF20-1206-20A PF3 1 2 PC57 6251ICOMP 5 PR153 10K_4 3 PR81 *100K_4 9 +3VPCU ISL6251_UGATE 17 G1 8 2P CSON PQ42 FDS6900AS PR65 2.7_6 PC45 .1U/X7R-50V_8 6251B_2 6251B_1 16 1P 1 15 2 BOOT 1 PC39 1U/X7R-25V_8 PD4 RB500V VDDP CSOP VDD CSOP_1 21 CSIP PR55 2.2/F_6 CSOP CSIN 19 20 C PC44 2 *3300P/X7R-50V_4 1 PR54 0_4 CELL-SET = Hi ----> Cells = VDD ---->4S CELL-SET = Low ----> Cells = GND ---->3S A A Quanta Computer Inc. PROJECT : BU1 Santa Rosa 5 4 3 2 Size Document Number Date: Sunday, April 01, 2007 Rev 3A ISL6251 Sheet 1 27 of 33 5 4 3 2 1 E E MAIND MAIND [32] SUSD SUSD [32] 1 [3] SYS_SHDN# 2 ISL6236_3V PR102 0_4 PL5 PL6 VIN VIN VL HI0805R800R-00_8 HI0805R800R-00_8 2 VL 1 5V_DL 4 PC95 0.1U/X7R-50V_6 1 PQ19 FDS6690AS 1 2 3 PR107 0_4 1 2 C PD12 PR116 1_6 2 1 2 4 2 PU5 ISL6236 32 31 30 29 28 27 26 25 REFIN2 ILIM2 OUT2 SKIP# PGOOD2 EN2 DH2 LX2 1 VL PC101 0.1U/X7R-50V_6 2 BYP OUT1 FB1 ILIM1 PGOOD1 EN1 DH1 LX1 PAD PAD PR119 PR106 287K/F_4 2 1 8 7 6 +3VPCU 3 +3VPCU 3V_LX PC83 PC77 + 0.1U/X7R-50V_6 330U/6.3V_6X5.7 PC82 0.1U/X7R-50V_6 3V_DL C DDPWRGD_R 0_6 SYS_HWPG [26] PC90 1U/10V_6 3 PL7 2.5uH_7.5A DDPWRGD_R 3V5V_EN PR113 1_6 2 D OCP : 6.25A 3V_DH 1 8 7 6 5 4 3 2 1 PC88 0.1U/X7R-50V_6 1 10U/X6S-25V_1206 330U/6.3V_6X5.7 9 10 11 12 2 267K/F_4 DDPWRGD_R 13 3V5V_EN 14 15 16 37 36 PAD PAD PAD 1 2 3 PR100 *0_4 PC86 + 1 PR108 8 7 6 5 2 PC81 5V_LX 17 18 19 20 21 22 23 24 +5VPCU PL8 3.3uH +5VPCU 35 34 33 +5VPCU LDOREFIN LDO VIN RTC ONLDO VCC TON REF FDS8884 3V_DH PR95 *0_4 BST1 DL1 VDD SECFB GND PGND DL2 BST2 150K/F_4 5 8 7 6 5 OCP: 12A 5V_DH PC75 PC76 0.1U/X7R-50V_6 10U/X6S-25V_1206 2200P/X7R-50V_4 G1 4 PQ18 1 PR99 *0_4 S1/D2 PR92 PC79 10U/X6S-25V_1206 PQ28 FDS6900AS 2 2 2 3V5V_EN 3 1 1 PC67 0.1U/X7R-50V_6 1 2 PC68 1U/10V_6 D1 PC70 .01U/X7R-16V_4 G2 PC69 0.1U/X7R-50V_6 S2 PC65 PC71 PC63 2200P/X7R-50V_4 10U/X6S-25V_1206 10U/X6S-25V_1206 PC84 3V_DL PR103 0_4 D1 PC72 0.1U/X7R-50V_6 D PC66 4.7U/X7R-10V_8 PR97 0_4 2 1 PR93 390K_4 PR101 39K/F_4 PR109 0_6 1 OCP:12A CHN217 PD11 PC97 0.1U/X7R-50V_6 3 2 CHN217 +15V_ALWP 22_8 1 2 PR122 200K/F_4 PR123 39K/F_4 +3VPCU PC87 1 2 5 6 2 PC102 0.1U/X7R-50V_6 Iocp=6.25-(2.18/2)=5.16A Vth=5.16A*28mOhm=145mV R(Ilim)=(145mV*10)/5uA ~294K 1 PR124 15V L(ripple current) =(19-3.3)*3.3/(2.5u*0.5M*19) ~2.18A PD10 BAT54-7-F 1 Iocp=12-(6/2)=9A Vth=9A*15mOhm=135mV R(Ilim)=(135mV*10)/5uA ~270K OCP:6.25A 2 1 L(ripple current) =(19-5)*5/(1.5u*0.4M*19) ~6A PC100 0.1U/X7R-50V_6 +3VPCU +5VPCU 0.1U/X7R-50V_6 PQ15 AO6402 3 B 4 B SUSD +5VPCU MAIND PQ30 AO6402 3 +5V_S5 PC103 0.1U/X7R-50V_6 0.1U/X7R-50V_6 PQ20 AO6402 3 +3V 4 PQ29 AO6402 3 MAIND 0.1U/X7R-50V_6 +5V 4.5A +3VSUS 1.5A PC62 0.1U/X7R-50V_6 4 0.1U/X7R-50V_6 4 S5D PC99 1 2 5 6 1 2 5 6 PC98 1 2 5 6 PC85 4.5A 3.5A PC78 0.1U/X7R-50V_6 PC104 0.1U/X7R-50V_6 +3VPCU VIN +5V_S5 +3V_S5 15V PC80 0.1U/X7R-50V_6 PR118 22_6 1M_6 PR137 22_6 PR135 1M_6 1 2 5 6 PR128 A A 3 PQ16 AO6402 4 3 3 S5D 3 3 S5_ON_G 5 4 2 +3V_S5 2 PQ35 2N7002E 3 PQ31 2N7002E 1.5A Quanta Computer Inc. PC64 0.1U/X7R-50V_6 PROJECT : BU1 Santa Rosa 1 PQ26 2N7002E 1 PQ33 DTC144EU 2 PR129 1M_6 1 2 1 [26] S5_ON 2 Size Document Number Date: Monday, March 26, 2007 Rev 1A SYSTEM 5V/3V Sheet 1 28 of 33 5 4 3 2 1 PL1 HI0805R800R-00_8 VIN_6262 PL2 HI0805R800R-00_8 +1.05V PR144 10_6 for ISL6262A 6262_LG1 4 1 2 3 PC26 1 2 + PQ5 *AOL1412 PQ4 AOL1412 + PC135 330u_2V_7343 PC136 330u_2V_7343 36 PC24 0.22U/X5R-25V_8 C H_VID1 38 VID1 UGATE2 27 H_VID2 39 VID2 BOOT2 26 H_VID3 40 VID3 H_VID4 41 VID4 H_VID5 PHASE2 28 42 VID5 LGATE2 30 PGND2 29 ISEN2 23 PR33 [6,16] PM_DPRSLPVR [3,6,14] ICH_DPRSTP# [16] VR_PWRGD_CK410# VR_ON 0_4 PR32 499/F_4 PR31 0_4 PR30 0_4 PR14 DPRSLPVR CLKEN# 43 VID6 44 VR_ON 45 DPRSLPVR 46 DPRSTP# 47 CLK_EN# 13 VDIFF 12 FB2 VSUM 19 2 PC16 1 2 2 2 2 68N/X7R-25V_6 VSUM 2 PC13 10 PR141 NTC_10K_6 COMP VO + PR147 PC138 PR148 330u_2V_7343 0_6 0_6 PC137 330u_2V_7343 B Panasonic ERT-J1VR103J 1 2 1 1 PC7 .01U/X7R-16V_4 1K_4 1 DFB 2 3.65K/F_6 PR142 10K/F_6 PR149 1_6 PR143 *0_6 ISEN1 PR13 3.48K/F_4 2 2 PC14 .01U/X7R-16V_4 PR146 18 PR11 17 15 1000P/X7R-50V_6 DROOP RTN VW PC18 1 2 16 9 VSEN 6.81K/F_4 14 PR17 + PQ2 *AOL1412 ED8-B -0623-33nf to 68nf PR3 PR8 11K/F_4 2.7K_4 0.22U/X7R-10V_6 ED8-B -0623-390p to330p A 1 1 220P/X7R-50V_4 PQ1 AOL1412 VSUM 1 FB PC19 1 470P/X7R-50V_4 .36uH PD1 *SSM24PT-LF 4 PC5 11 2 PL18 2 1 1000P/X7R-50V_4 PR19 13.3K/F_4 1K/F_4 2 PC2 0.1U/X7R-50V_6 PC140 2200P_50V_6 4 ISEN2 25 8 PC1 10U/X6S-25V_1206 6262_PH2 PC11 0.22U/X5R-25V_6 OCSET PC25 10U/X6S-25V_1206 PQ3 AOL1414 PC20 1000P/X7R-50V_6 97.6K/F_4 2.2_F_6 4 6262_LG2 PR15 PR18 6262_UG2 PR16 2.2/F_6 1 2 PC17 0.22U/X5R-25V_8 NC PC15 1 2 255/F_4 4.7U/X6S-25V_8 1K/F_4 PR12 2 1 VID0 1 2 [4] H_VID6 B 37 H_VID6 [26] VRON PVCC 31 1 [4] H_VID5 PR151 PC21 2 [4] H_VID4 PC12 +5V_S5 0.22U/X5R-25V_6 SOFT 4 [4] H_VID3 ISEN1 3 [4] H_VID2 24 1 [4] H_VID1 33 ISEN1 5 H_VID0 [4] H_VID0 NTC PGND1 2 Panasonic ERT-J0EV474J 6 7 1 PC22 22N/X7R-50V_6 2 2 VR_TT# 1 PC23 1 .01U/X7R-16V_4 RBIAS 5 C VIN_6262 5 PR140 PR21 470K_4 NTC 4.02K/F_4 PGD_IN 4 1 2 3 [3] H_PROCHOT# 3 *0_6 ISEN2 5 147K/F_6 32 1 2 3 *0_4 PR25 LGATE1 2 PGD_IN PR24 PSI# 1_6 PR5 1 2 34 1 VR_ON PR22 10K_4 PSI#_1 0_4 PHASE1 2 PR27 10K_6 PR4 2 PSI# PR6 PR23 2.2/F_6 1 2 +3VSUS 0_6 1 35 BOOT1 1 UGATE1 PR1 0_6 2 GND_T VSUM 1 2 3 GND 49 3.65K/F_6 1 21 PR7 2 ISL6262A PR2 1 48 1 3V3 PGOOD 20 PU1 VIN PC10 1U/X7R-25V_8 VCC 2 0_8 1 PR20 22 2 0.1U/X7R-50V_6 2 .36uH PD2 *SSM24PT-LF 4 1 PC9 0.1U/X7R-50V_6 2 PR145 10_6 1 1.91K/F_4 1 PSI# [3] PSI# 1 PR28 VCC_CORE PL17 6262_PH1 PR29 10_4 +5V_S5 2 2 PC27 0.1U/X7R-50V_6 PQ6 AOL1414 5 1 2 1 PWR_MON 4 +3V VIN_6262 4.99K/F_6 PGD_IN 1 1 2 3 6262_UG1 PR26 1 H_VID0 Merom: VCC_CORE/ 44A 2 H_VID1 1 H_VID2 2 H_VID3 3 H_VID4 PC128 470U/25V PC3 PC149 PC29 10U/X6S-25V_1206 PC28 0.1U/X7R-50V_4 0.1U/X7R-50V_6 PC139 10U/X6S-25V_1206 2200P_50V_6 1 H_VID5 D PC148 1500P/X7R-50V_4 2.2_F_6 2 H_VID6 [3,6,16] + 4 DELAY_VR_PWRGOOD 2 PR150 1 PR41 *0_6 2 PR37 *0_6 1 PR40 *0_6 5 PR36 *0_6 1 2 3 PR39 *0_6 5 D PR35 *0_6 2 VIN PR38 *0_6 PC4 0.22U/X5R-25V_6 PC8 180P/NPO-50V_4 ISL6262_VO 1 PC6 .01U/X7R-16V_4 A Parallel PR9 0_4 PR10 0_4 VCCSENSE [4] VSSSENSE [4] Quanta Computer Inc. PROJECT : BU1 Santa Rosa 5 4 3 2 Size Document Number Date: Thursday, March 29, 2007 Rev 2A CPU CAORE (6262A) 1 Sheet 29 of 33 1 2 3 4 5 A A 1500P/X7R-50V_4 PC153 VIN-1.5V PL15 VIN +5V_S5 HI0805R800R-00_8 PR43 PD3 *.1U/50V_6 SW1010C 11 ILIM 10 1 1 VDDP 9 FBK 4 PGOOD DL 8 VSSA PGND 7 5 NC TPAD 17 14 NC 6 18 2 2 PC30 PC32 PC33 0.1U/X7R-50V_6 1000P/X7R-50V_6 .01U/X7R-50V_6 VCCA 3 1 2 3 16A 2 DH-1.05V PL16 +1.05V PR50 DL-1.05V 6.65K_6 1R0UH-9mR 4 PQ44 AOL1412 PR152 1 LX 2.2_F_6 + + PR42 11K_6 PC141 2200P_50V_6 GND PR45 10K_6 4 1 VOUT PC129 PC131 560U/2.5V_6X5.7 PC31 33P/NPO-50V_6 2 12 PC132 .1U/X7R-50V_8 10U/X6S-25V_1206 10U/X6S-25V_1206 2 13 DH 2 4.7U/Y5V-10V_8 5 BST VIN 1 [26] HWPG_1.05V B EN/PSV 16 GND PR47 *10K_6 15 PC134 PQ43 AOL1414 21 +3V GND 0_6 GND PR48 PC36 PC34 .1U/X7R-50V_8 20 MAINON PU2 SC411MLTRT 19 [19,26,31,32] 1 1M_6 0.1U/X7R-50V_6 5 PC35 1 2 3 10_6 PR46 1 2 PC152 PC133 PC130 10U/Y5U-10V_8 560U/2.5V_6X5.7 PR44 10K_6 B VOUT=(1+R2/R3)*0.5 C C D D Quanta Computer Inc. PROJECT : BU1 Santa Rosa 1 2 3 4 Size Document Number Date: Thursday, March 29, 2007 Rev 2A VTT 1.05V (SC11) 5 Sheet 30 of 33 5 4 3 2 1 E E PL9 VIN 5 6 7 8 +1.8VSUS PR138 PC120 VLDOIN DRVH 19 2 VTT VBST 20 PC121 4 VTTSNS LL 18 10U/Y5V-10V_1206 5 GND DRVL 17 3 VTTGND PGND 16 6 MODE S3 11 S3_1.8V PR90 0_6 S5 12 S5_1.8V PR91 0_6 5VIN 0_6 PC59 .033U/50V_6 5VIN PR86 7 VTTREF 8 COMP 9 VDDSNS 10 V5IN 14 PGOOD 13 CS 15 VDDQSET 21 22 23 24 25 26 27 0_6 FOR DDR II *0_6 DIS_MODE PR88 +1.8VSUS PR82 5 6 7 8 3 2 1 PR85 4 +1.8VSUS MAX Current 10A 1R5UH-3.8mR PR98 4 MAINON [19,26,30,32] 2.2_F_6 PC117 + PC115 10U/Y5V-10V_8 560U/2.5V_6X5.7 SUSON [26,32] +3VPCU +3VPCU PQ38 FDS6690AS PQ37 FDS6690AS PC73 2200P_50V_6 D S3_1.8V PR89 *0_6 S5_1.8V 8.25K/F_6 1 HWPG_1.8V [26] 2 0_6 1500P/X7R-50V_4 PL10 100K_6 5VIN 0_6 10U/X6S-25V_1206 0.1U/X7R-50V_6 5 6 7 8 PR87 PC60 +5VPCU 10U/X6S-25V_1206 5VIN *1000P_50V_6 PR83 PC118 2200P_50V_6 PC150 PC151 0.1U/X7R-50V_6 PC113 10U/X6S-25V_1206 3 2 1 SMDDR_VREF PC58 3 2 1 DIS_MODE PR84 GND GND GND GND GND GND GND 10U/Y5V-10V_1206 PQ39 FDS8884 1 SMDDR_VTERM PC112 PC116 4 PU4 TPS51116 D HI0805R800R-00_8 2.2_F_6 10U/Y5V-10V_1206 PC119 2200P/X7R-50V_6 PC111 PC61 4.7U/X5R-6.3V_6 C C B B A A Quanta Computer Inc. PROJECT : BU1 Santa Rosa 5 4 3 2 Size Document Number Date: Sunday, April 01, 2007 Rev 3A DDR2 1.8V(TP1116) Sheet 1 31 of 33 4 3 PQ36 +1.8VSUS PC107 + PC114 E 1 2 3 0.1U/Y5V-16V_4 10U/X5R-6.3V_6 9338DRV 560U/2.5V_6X5.7 E PR134 +1.25V 0_6 +3V PC105 3 [26] HWPG_2.5V MAINON PR130 3A +1.25V [2,9,17] 100K_4 9338EN 4 0_4 1 +5VPCU PGD DRV 6 ADJ 5 .01U/X7R-25V_4 Rg EN VCC PR121 15K/F_6 PC109 PU7 0.1U/Y5V-16V_4 G9338 ADJ 0.1U/Y5V-16V_4 PR125 10K_6 Vout1 = (1+Rg/Rh)*0.5 2 PC94 GND PR132 1 FDS8884 8 7 6 5 PC106 2 4 5 PC110 + PC108 10U/X5R-6.3V_6 Rh 560U/2.5V_6X5.7 D D +5VPCU PR114 1M_6 +3VSUS PR115 22_6 15V PR136 22_6 PC89 2 1 PR120 1M_6 [19,26,30,31] 2 PQ27 2N7002E PC93 *2200P_4 PC91 10U/10V-LF_8 1 PQ34 2N7002E 1 1 1 2 PQ24 2N7002E 4 VPP PGOOD 1 2 VEN VO 6 3 8 9 VIN GND GND NC 5 PC92 .1U/50V-LF_6 2 2 PR117 1M_6 1 PQ25 DTC144EU 2 +1.8VSUS 2 [26,31] SUSON MAINON 3 SUSD [28] 3 3 SUSD 3 SUS_ON_G PU6 G966-25-LF .1U/50V-LF PR127 1 0_6 ADJ +1.8VSUS 7 VIN HWPG_1.5V [26] +1.5V 1.5A PC96 10U/10V-LF_8 PR131 1 2 30K/F_6 PR133 34K/F_6 VO=0.8(R1+R2)/R2 C C VIN +1.25V +1.05V VCC_CORE +3V +3V PR111 PR126 PR49 PR34 PR96 1M_6 22_6 22_6 22_6 *22_6 +5V PR112 22_6 +1.5V PR104 22_6 15V PR94 22_6 PR105 1M_6 B 3 3 3 3 3 3 MAIND [28] 3 3 MAIND B 3 RUN_ON_G PQ14 *2N7002E 2 PQ23 2N7002E 2 PQ22 2N7002E PQ13 2N7002E PQ17 2N7002E PC74 *2200P_4 1 PQ7 2N7002E 2 1 PQ8 2N7002E 2 1 PQ32 2N7002E 2 1 2 1 PR110 1M_6 1 1 PQ21 DTC144EU 2 1 MAINON 2 1 [19,26,30,31] 2 A A Quanta Computer Inc. PROJECT : BU1 Santa Rosa 5 4 3 2 Size Document Number Date: Monday, March 26, 2007 Rev 1A DISCHARGE/1.5V/VCC1.25 Sheet 1 32 of 33 5 Model 4 REV DATE 00 20061218 BU1 D 01 20061225 1A 20061227 2A C 20070201 3A 20070326 B 20070327 20070328 20070329 3 2 1 NOTE CHANGE LIST FIRST RELEASED : 20061218 Page02: Change CLK GEN. low power outs from +1.05V to +1.25V.Because VDD_IO will drop out when high loading Page02: REV_01 Remove CLK_MCH_OE#_R had pull up resistor,because had be pull up at NB side Page03: Del R382,R383,Q60,D39 Page04: Del R176 for FBS signals batter return path under +1.05V plane Page08: Change Crestline VCC_AXM to 1.25V, reference to SR ww48 MoW. reserved 0 ohm resister Page16: Add D43 to avoid leakage from EC to SB,Del R242 Page18: REV_01 Reserved LCD/LED type panel module and Digital/analogy MIC Page19: Modify G-Sensor circuit Page22: Reserved LPC_PD# control signal from SB to R5C833 Page23: Increase HOLE Page24: Add 0.1u CAP. C810 from +5VPCU to GND Page25: Modify IDE LED circuit Page26: Reserved R756,R766 for EC control G-Sensor Page27: Add 3 cell Battery always setting circuit Page28: Add +3V_S5 discharge circuit Page30: Reserved PD resistor to avoid leakage voltage Page32: Reserve +3V discharge circuit Circuit modify Circuit modify Circuit modify Circuit modify Circuit modify Circuit modify Circuit modify Circuit modify Circuit modify Circuit modify Circuit modify Circuit modify Circuit modify Circuit modify Circuit modify Circuit modify Circuit modify D A TEST (PCB REV_1A) RELEASED : 20061227 Page03: Modify thermal protect circuit and FAN control Page14: Modify RTC charge current / SB strip setting / Reserved PU resistor on SATALED# signal / Change XTAL capacitor value Page16: Reserver Pull down resistor on HDPINT signal / Reserved C-Link to WLAN / Delete FM function / Add Board ID Page18: Change panel backlight signal pull up resistor / Change camera power source / Add LED type panel circuit / Add fuse on CRT power / Reserved EMI choke on USB signals and add EMI solution / Add RC circuit on LED panel driver IC Page19: Modify LDO power source / Add Microprocessor reset IC / Reserved G-sensor SMBUS to SB chipset Page22: Reserved Cardreader external EEPROM Page23: Separate RF enable/disable pin from WLAN and 3G card / Add EMI solution and Reserved C-Link circuit / Delete 3G card function / Add HOLE for card Bus connector Page24: Increase CN7 pin for control illumination logo and enable/disable USB port power / Add capacitor on keyboard signals for EMI / Change LAN/B cable connector / Delete FM function Page25: Modify battery LED and RF SW power source / Delete 3G card LED Page26: Modify EC control circuit / Add EMI solution / Change XTAL capacitor value Page27: Change fuse rating and switch MOS Page29: Add EMI solution Page30: Add EMI solution Page31: Add EMI solution Page32: Add EMI solution Page03: Add CAP to GND for FAN controller IC U12 power pin decoupling Page13: Change DDR socket height Page18: Exchange Dioid and Fuse placement Page20: Add control LAN power circuit to enable/disable LAN Page22: Change 1394 connector type and delete card reader connector 2nd source Page23: Change mini-card 3V power source from +3VSUS to +3V_S5 for support wake on WLAN from S3/S4 / Change HOLE pad size Page24: Reserve EMI capacitor / add solve insert PCMCIA Card speaker has bo sound circuit Page25: Add ESD protect circuit Page27: Change MOS footprint Page14: Modify RTC short pad footprint Page17: Modify inductance type Page23: Add capacitors for EMI Page24: Modify FFC connector footprint Page26: Add capacitor for EMI Page27: Reserve EMI circuit Page22: Delete card reader external EEPROM Page23: Add pull up resistor on PCIE_WAKE# signal Page18: Delete CMO LED type connector Page25: Reserve ESD protect on kill-switch Page31: Stuff R/C Snubber for EMI Circuit modify BOM/Circuit modify Circuit modify BOM/Circuit modify Circuit modify Circuit modify Circuit modify Circuit modify Circuit modify Circuit modify Circuit modify Circuit modify BOM/Circuit modify Circuit modify Circuit modify Circuit modify Circuit modify Circuit modify Circuit modify Circuit modify Circuit modify Circuit modify Circuit modify Circuit modify Circuit modify Circuit modify Circuit modify Circuit modify Circuit modify Circuit modify Circuit modify Circuit modify Circuit modify Circuit modify Circuit modify Circuit modify Circuit modify BOM modify C B A A Quanta Computer Inc. PROJECT : BU1 Santa Rosa 5 4 3 2 Size Document Number Date: Sunday, April 01, 2007 Rev 3A Change List Sheet 1 33 of 33 www.s-manuals.com
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File Type : PDF File Type Extension : pdf MIME Type : application/pdf PDF Version : 1.4 Linearized : No XMP Toolkit : Adobe XMP Core 4.0-c316 44.253921, Sun Oct 01 2006 17:14:39 Producer : Acrobat Distiller 7.0 (Windows); modified using iTextSharp 5.0.5 (c) 1T3XT BVBA Creator Tool : PScript5.dll Version 5.2 Modify Date : 2016:06:12 14:12:36+03:00 Create Date : 2007:04:01 21:50:41+08:00 Metadata Date : 2016:06:12 14:12:36+03:00 Format : application/pdf Title : Quanta BU1 - Schematics. www.s-manuals.com. Creator : Subject : Quanta BU1 - Schematics. www.s-manuals.com. Document ID : uuid:8b5153f4-5df2-404e-96b2-99d376b834f7 Instance ID : uuid:ea136b98-b4ac-44cc-bbb2-99c2266d1691 Page Count : 34 Keywords : Quanta, BU1, -, Schematics., www.s-manuals.com. Warning : [Minor] Ignored duplicate Info dictionaryEXIF Metadata provided by EXIF.tools