Quanta LX3, LX5 Schematics. Www.s Manuals.com. R1a Schematics
User Manual: Motherboard Quanta LX3, LX5 (Huror River) - Schematics. Free.
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1 2 3 RED":N"UVCEM"WR A 5 Intel Sandy PAGE 13 DDR3-SODIMM2 DDR3 1066,1333 MT/s CPU 45Watt 35Watt 4 Core PAGE 14 REK/Gzrtguu Igp4"Z"38 ATI Capliano Pro (128bit) (FCBGA) 962p 29X29mm DMI*4 26 32.768KHz 27MHz PCH CLK 27M UCVC2"522OD1u PCH 3.5Watt UCVC2"522OD1u B UCVC"/"4pf"JFF UCVC2"522OD1u UCVC"/"EF/TQO PAGE 34 G/UCVC1WUD"Rqtv *3+ USB2.0 Port Z4 POWER LED Platform Controller Hub PAGE 34 PAGE 7-12 USB2.0 48M UCVC2"522OD1u 2 0 Fingerprint PAGE 32 UODWU Ceegngtqogvgt JR524FNVT: iGPU HDMI LVDS CRT 6 USB2.0 Port PAGE 32 BlueTooth PAGE 32 4 10 Webcam w/ Mic PAGE 32 PCI-E 100M PAGE 30 Z3 URK"TQO LAN LPC Realtek PCIE-LAN Audio PAGE 42 RTL8111(E) GigaLAN KFV;4JF:2 PAGE 29 SYSTEM CHARGER(P2806) Z3 half size mini-card (Wireless LAN Shirley Peak 802.11a/b/g/n) PAGE 36 PAGE 33 Form 15" PAGE 32 8,9 7 34 11 3 USB2.0 Port Realtek RTS5138 Azalia PAGE 7 HDD LED Form 17" PAGE 32 Card Reader B USB2.0 Port POWER LED HDD LED PAGE 32 BATTERY SELECTOR CRTPAGE PAGE 24 HDMI CON (1920*1200) PAGE 27 PAGE 15-19 BCLK133M DMI100M DP120M A Fwcn"Ejcppgn"NXFU Display Owz LVDS CRT HDMI ATI Robson M2 (128bit) ( rPGA 989 ) DDR III SMDDR_VTERM and GPU+1.5V/+1.0V(RT8207G) LCD CONN for dual channel (15.6",17") PAGE 25 PAGE 20-23 PAGE 34 Form 15" PAGE 32 Touchscreen PAGE 32 PAGE 24 C 5-in-1 flash media slot(SD/MS/MMC/ XD/MSP) PAGE 24 32.768KHz PAGE 44 25MHz Mg{dqctf Vqwej"Rcf Nkijv"Ugpuqt PAGE 37 SYSTEM POWER RT8206B PAGE 38 +1.05V_VTT and GPU +1.8V/+3V(VT358) ENE KBC GMT G991P1U PAGE 36 VCCP +1.05V/+1.8V(RT8204) RJ45 PAGE 33 Cornkhkgt VRC5333F3 KB3926 D2 U[UVGO"HCP PAGE 39 PAGE 27 PAGE 35 DKQU *U[UVGO"DKQU+ PAGE 32 PAGE 41 D D FOKE VGACORE/VDDCI(RT8208/RT9018A) PAGE 42 PAGE 30 Cwfkq"Lcem" *Jgcfrjqpg1OKE+ PAGE 30 Lcem"vq Urgcmgt PAGE 30 Lcem"vq Uwd/Yqqhgt RTQLGEV"<"NZ517*Jwtqp"Tkxgt+ Swcpvc"Eqorwvgt"Kpe0 PAGE 31 CPU CORE (ADP3212) PAGE 40 PD7 Size Custom Document Number 2 3 4 5 6 7 Rev 1A BLOCK DIAGRAM Date: Friday, October 01, 2010 1 23 8 54,54"qt"86,38 DDR3 1066,1333 MT/s UCVC"JFF"3UV C 7 VRAM GDDR5*8 DDR3-SODIMM1 PAGE 3-6 PAGE 43 6 NZ517"*Jwtqp"Tkxgt+"DNQEM"FKCITCO Dis. NC[GT"3"<"VQR NC[GT"4"<"UIPF NC[GT"5"<"KP3*Jkij+ NC[GT"6"<"KP4*Nqy+ NC[GT"7"<"UXEE NC[GT"8"<"KP5*Jkij+ NC[GT"9"<"UIPF NC[GT":"<"DQV 4 Sheet 1 8 of 47 1 2 3 4 5 6 7 24 8 A A 4/7 DB del for PDC update. B B C C D D RTQLGEV"<"NZ517*Jwtqp"Tkxgt+ Swcpvc"Eqorwvgt"Kpe0 PD7 Size Custom Document Number Date: Friday, October 01, 2010 1 2 3 4 5 6 7 Rev 1A Clock Gen(9LRS3197)/HOLES Sheet 2 8 of 47 5 4 3 2 Sandy Bridge Processor (DMI,PEG,FDI) Sandy Bridge Processor (CLK,MISC,JTAG) DMI_TX#[0] DMI_TX#[1] DMI_TX#[2] DMI_TX#[3] [7] [7] [7] [7] DMI_RXP0 DMI_RXP1 DMI_RXP2 DMI_RXP3 G22 D22 F20 C21 DMI_TX[0] DMI_TX[1] DMI_TX[2] DMI_TX[3] [7] [7] [7] [7] [7] [7] [7] [7] FDI_TXN0 FDI_TXN1 FDI_TXN2 FDI_TXN3 FDI_TXN4 FDI_TXN5 FDI_TXN6 FDI_TXN7 A21 H19 E19 F18 B21 C20 D18 E17 FDI0_TX#[0] FDI0_TX#[1] FDI0_TX#[2] FDI0_TX#[3] FDI1_TX#[0] FDI1_TX#[1] FDI1_TX#[2] FDI1_TX#[3] [7] [7] [7] [7] [7] [7] [7] [7] FDI_TXP0 FDI_TXP1 FDI_TXP2 FDI_TXP3 FDI_TXP4 FDI_TXP5 FDI_TXP6 FDI_TXP7 A22 G19 E20 G18 B20 C19 D19 F17 FDI0_TX[0] FDI0_TX[1] FDI0_TX[2] FDI0_TX[3] FDI1_TX[0] FDI1_TX[1] FDI1_TX[2] FDI1_TX[3] [7] [7] FDI_FSYNC0 FDI_FSYNC1 J18 J17 [7] FDI_INT H20 FDI_INT [7] [7] FDI_LSYNC0 FDI_LSYNC1 J19 H17 FDI0_LSYNC FDI1_LSYNC eDP_COMP INT_eDP_HPD_Q B FDI0_FSYNC FDI1_FSYNC A18 A17 B16 eDP_COMPIO eDP_ICOMPO eDP_HPD C15 D15 eDP_AUX eDP_AUX# C17 F16 C16 G15 eDP_TX[0] eDP_TX[1] eDP_TX[2] eDP_TX[3] C18 E16 D16 F15 eDP_TX#[0] eDP_TX#[1] eDP_TX#[2] eDP_TX#[3] PEG_RX[0] PEG_RX[1] PEG_RX[2] PEG_RX[3] PEG_RX[4] PEG_RX[5] PEG_RX[6] PEG_RX[7] PEG_RX[8] PEG_RX[9] PEG_RX[10] PEG_RX[11] PEG_RX[12] PEG_RX[13] PEG_RX[14] PEG_RX[15] J33 L35 K34 H35 H32 G34 G31 F33 F30 E35 E33 F32 D34 E31 C33 B32 PEG_RX0 PEG_RX1 PEG_RX2 PEG_RX3 PEG_RX4 PEG_RX5 PEG_RX6 PEG_RX7 PEG_RX8 PEG_RX9 PEG_RX10 PEG_RX11 PEG_RX12 PEG_RX13 PEG_RX14 PEG_RX15 SNB_IVB# SNB_IVB# N.A at SNB EDS #27637 0.7v1 SKTOCC# TP12 AN34 SKTOCC# TP11 TP_CATERR# AL33 CATERR# BCLK BCLK# A28 A27 DPLL_REF_SSCLK DPLL_REF_SSCLK# A16 A15 CLK_DPLL_SSCLKP_R CLK_DPLL_SSCLKN_R R8 CPU_DRAMRST# AK1 A5 A4 SM_RCOMP_0 R136 SM_RCOMP_1 R356 SM_RCOMP_2 R355 R99 43_4 H_PECI AN33 PECI [35,40] H_PROCHOT# R141 56.2/F_4 H_PROCHOT#_R AL32 PROCHOT# [10,35] PM_THRMTRIP# R523 [35] PEG_RX[0..15] [15] EC_PECI PEG_TX#[0] PEG_TX#[1] PEG_TX#[2] PEG_TX#[3] PEG_TX#[4] PEG_TX#[5] PEG_TX#[6] PEG_TX#[7] PEG_TX#[8] PEG_TX#[9] PEG_TX#[10] PEG_TX#[11] PEG_TX#[12] PEG_TX#[13] PEG_TX#[14] PEG_TX#[15] M29 M32 M31 L32 L29 K31 K28 J30 J28 H29 G27 E29 F27 D28 F26 E25 C_PEG_TX#0 C_PEG_TX#1 C_PEG_TX#2 C_PEG_TX#3 C_PEG_TX#4 C_PEG_TX#5 C_PEG_TX#6 C_PEG_TX#7 C_PEG_TX#8 C_PEG_TX#9 C_PEG_TX#10 C_PEG_TX#11 C_PEG_TX#12 C_PEG_TX#13 C_PEG_TX#14 C_PEG_TX#15 PEG_TX[0] PEG_TX[1] PEG_TX[2] PEG_TX[3] PEG_TX[4] PEG_TX[5] PEG_TX[6] PEG_TX[7] PEG_TX[8] PEG_TX[9] PEG_TX[10] PEG_TX[11] PEG_TX[12] PEG_TX[13] PEG_TX[14] PEG_TX[15] M28 M33 M30 L31 L28 K30 K27 J29 J27 H28 G28 E28 F28 D27 E26 D25 C_PEG_TX0 C_PEG_TX1 C_PEG_TX2 C_PEG_TX3 C_PEG_TX4 C_PEG_TX5 C_PEG_TX6 C_PEG_TX7 C_PEG_TX8 C_PEG_TX9 C_PEG_TX10 C_PEG_TX11 C_PEG_TX12 C_PEG_TX13 C_PEG_TX14 C_PEG_TX15 PM_THRMTRIP#_R AN32 *0_4/S R503 *0_4/S PM_SYNC_R AM34 PM_SYNC [10] H_PWRGOOD R514 *0_4/S H_PWRGOOD_R *0_4/ AP33 UNCOREPW RGOOD R513 10K_4 PM_DRAM_PWRGD_R V8 3/26 DB del for DG update. 8/16 PV Modify [9,33,35,36,37] +1.05V_VTT U37 CPU RESET# PLTRST# 3 GND OUT 2 IN 1 THERMTRIP# PM_SYNC [7] 4 CPU_PLTRST# +3VS5 NC VCC 75_4 R524 43_4 CPU_PLTRST#_R AR33 RESET# R521 5 74LVC1G07GW R529 R527 SM_DRAMPW ROK C685 SM_DRAMRST# SM_RCOMP[0] SM_RCOMP[1] SM_RCOMP[2] 4/20 DB add. 4/20 DB add. SM_DRAMPWROK Processor Input. +3VS5 SM_RCOMP[0] W:20mils/S:20mils/L: 500mils, SM_RCOMP[1] W:20mils/S:20mils/L: 500mils, SM_RCOMP[2] W:15mils/S:20mils/L: 500mils, PRDY# PREQ# AP29 AP27 XDP_PRDY# XDP_PREQ# TP52 TP15 TCK TMS TRST# AR26 AR27 AP30 XDP_TCLK XDP_TMS XDP_TRST# TP50 TP47 TP46 TDI TDO AR28 AP26 XDP_TDI_R XDP_TDO DBR# BPM#[0] BPM#[1] BPM#[2] BPM#[3] BPM#[4] BPM#[5] BPM#[6] BPM#[7] 8/6 PV NA. U1 PM_DRAM_PWRGD_PU 1 NC VCC A R427 R447 0_4 0_4 0_4 2 IN 3 FDI_FSYNC0 FDI_FSYNC1 FDI_LSYNC0 FDI_LSYNC1 1K_4 1K_4 FDI_FSYNC can gang all these 4 signals together and tie them with only one 1K resistor to GND (DG V0.5 Ch2.2.9). XDP_DBRST# [7] TP49 TP45 TP53 TP43 TP41 TP44 TP51 TP48 +1.5VSUS R32 1K_4 R29 [13,14] DDR3_DRAMRST# R33 1K_4 3 R19 *0_4 GND OUT PM_DRAM_PWRGD_C R13 R15 130/F_4 PM_DRAM_PWRGD_R [9] DRAMRST_CNTRL_PCH R24 Q4 2N7002 R9 2 PM_DRAM_PWRGD_C *0_4/S R10 10/13 *3K/F_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 PEG_TX0 PEG_TX1 PEG_TX2 PEG_TX3 PEG_TX4 PEG_TX5 PEG_TX6 PEG_TX7 PEG_TX8 PEG_TX9 PEG_TX10 PEG_TX11 PEG_TX12 PEG_TX13 PEG_TX14 PEG_TX15 0.22uF AC coupling Caps for PCIE GEN1/2/3 R23 4.99K/F_4 C23 0.047U/10V_4 6/4 DB2 Modify. MV Modify. MAIN_ONG [5,45] +1.05V_VTT [5,11,39,40] +1.5V_CPU [5] +3VS5 [7,8,9,10,11,45] +3V [7,8,9,10,11,13,14,18,19,25,26,27,28,29,30,31,32,33,34,35,36,37,39,40,41,43,45,46,47] Q2 *2N7002 Embedded Display PLL Clock [15] PEG_TX#[0..15] 8/17: PV Modify. 3/26 DB change Part reference. C_PEG_TX#0 C_PEG_TX#1 C_PEG_TX#2 C_PEG_TX#3 C_PEG_TX#4 C_PEG_TX#5 C_PEG_TX#6 C_PEG_TX#7 C_PEG_TX#8 C_PEG_TX#9 C_PEG_TX#10 C_PEG_TX#11 C_PEG_TX#12 C_PEG_TX#13 C_PEG_TX#14 C_PEG_TX#15 C694 C689 C684 C681 C675 C674 C664 C665 C661 C646 C642 C636 C633 C631 C621 C612 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 PEG_TX#0 PEG_TX#1 PEG_TX#2 PEG_TX#3 PEG_TX#4 PEG_TX#5 PEG_TX#6 PEG_TX#7 PEG_TX#8 PEG_TX#9 PEG_TX#10 PEG_TX#11 PEG_TX#12 PEG_TX#13 PEG_TX#14 PEG_TX#15 CLK_DPLL_SSCLKP_R CLK_DPLL_SSCLKN_R Ra 3 1 4 2 CLK_DPLL_SSCLKP [9] CLK_DPLL_SSCLKN [9] Processor pull-up (CPU) DP & PEG Compensation +1.05V_VTT +1.05V_VTT R360 R361 10K_4 +1.05V_VTT INT_eDP_HPD_Q H_PROCHOT# XDP_TDO XDP_TMS XDP_TDI_R XDP_PREQ# XDP_TCLK XDP_TRST# 24.9/F_4 eDP_COMP *0_4P2R_4 CLK_DPLL_SSCLKP_R CLK_DPLL_SSCLKN_R Rb R365 Rc R364 0_4 eDP_COMPIO and ICOMPO signals should be shorted near balls and routed with typical impedance <25 mohms 0_4 +1.05V_VTT Ra Rb Rc DIS NC Stuff Stuff SG/UMA Stuff NC NC 0.22uF AC coupling Caps for PCIE GEN1/2/3 R145 R534 R535 R156 R158 R162 R526 4 3 62_4 51_4 51_4 51_4 *51_4 51_4 51_4 A 24.9/F_4 PEG_COMP R58 PEG_ICOMPI and RCOMPO signals should be routed within 500 mils typical impedance = 43 mohms PEG_ICOMPO signals should be routed within 500 mils typical impedance = 14.5 mohms RTQLGEV"<"NZ517*Jwtqp"Tkxgt+ Swcpvc"Eqorwvgt"Kpe0 PD7 Size Custom Document Number 2 Rev 1A SNB 1/4 (PCIE&DMI&FDI) Date: Wednesday, October 13, 2010 5 B *0_4/S *74LVC1G07GW *39_4 CPU_DRAMRST# 1 CPU_DRAMRST#_R R4 200/F_4 4 *0_4 PM_DRAM_PWRGD [7] [15] PEG_TX[0..15] FDI_INT +3V DDR3 DRAM RESET C24 *0.1U/10V_4 5 RP12 R436 R422 R441 AT28 AR29 AR30 AT30 AP32 AR31 AT31 AR32 XDP_BPM0 XDP_BPM1 XDP_BPM2 XDP_BPM3 XDP_BPM4 XDP_BPM5 XDP_BPM6 XDP_BPM7 C *1K_4 +3VS5 R16 *10K_4 PEG x16 disable (UMA only remove) C690 C686 C682 C676 C671 C668 C658 C662 C650 C640 C638 C632 C627 C626 C619 C599 XDP_DBRST# Sandy Bridge_rPGA_Rev0p61 rpga989-47989-socket DGG^9000014 IC SOCKET RPGA 989P(P1.0,M/H3.0) 6/4 DB2 Modify. C_PEG_TX0 C_PEG_TX1 C_PEG_TX2 C_PEG_TX3 C_PEG_TX4 C_PEG_TX5 C_PEG_TX6 C_PEG_TX7 C_PEG_TX8 C_PEG_TX9 C_PEG_TX10 C_PEG_TX11 C_PEG_TX12 C_PEG_TX13 C_PEG_TX14 C_PEG_TX15 AL35 CPU XDP TP14 TP42 R501 +1.5V_CPU 3/26 DB del for DG update. 140/F_4 26.1/F_4 200/F_4 *750/F_4 0.1U/10V_4 *1.5K/F_4 eDP_COMP connect to PIN A18 W:4mils/S:15mils/L: 500mils. eDP_COMP connect to PIN A17 W:12mils/S:15mils/L: 500mils. 8/17: PV Modify. D Placement close to EC. Sandy Bridge_rPGA_Rev0p61 rpga989-47989-socket DGG^9000014 IC SOCKET RPGA 989P(P1.0,M/H3.0) FDI disable (DIS only stuff) CLK_CPU_BCLKP [9] CLK_CPU_BCLKN [9] 2 G21 E22 F21 D21 C26 H_SNB_IVB# CLOCKS DMI_RXN0 DMI_RXN1 DMI_RXN2 DMI_RXN3 [8] DDR3 MISC [7] [7] [7] [7] PEG_RX#[0..15] [15] JTAG & BPM DMI_RX[0] DMI_RX[1] DMI_RX[2] DMI_RX[3] PEG_RX#0 PEG_RX#1 PEG_RX#2 PEG_RX#3 PEG_RX#4 PEG_RX#5 PEG_RX#6 PEG_RX#7 PEG_RX#8 PEG_RX#9 PEG_RX#10 PEG_RX#11 PEG_RX#12 PEG_RX#13 PEG_RX#14 PEG_RX#15 MISC B28 B26 A24 B23 K33 M35 L34 J35 J32 H34 H31 G33 G30 F35 E34 E32 D33 D31 B33 C32 3/26 DB for H/W modify. THERMAL DMI_TXP0 DMI_TXP1 DMI_TXP2 DMI_TXP3 PEG_RX#[0] PEG_RX#[1] PEG_RX#[2] PEG_RX#[3] PEG_RX#[4] PEG_RX#[5] PEG_RX#[6] PEG_RX#[7] PEG_RX#[8] PEG_RX#[9] PEG_RX#[10] PEG_RX#[11] PEG_RX#[12] PEG_RX#[13] PEG_RX#[14] PEG_RX#[15] PEG_COMP connect to PIN H22&J22 W:4mils/S:15mils/L: 500mils. PEG_COMP connect to PIN J21 W:12mils/S:15mils/L: 500mils. PWR MANAGEMENT [7] [7] [7] [7] J22 J21 H22 3 DMI_RX#[0] DMI_RX#[1] DMI_RX#[2] DMI_RX#[3] PEG_COMP PEG_ICOMPI PEG_ICOMPO PEG_RCOMPO 1 B27 B25 A25 B24 PCI EXPRESS* - GRAPHICS DMI_TXN0 DMI_TXN1 DMI_TXN2 DMI_TXN3 Intel(R) FDI [7] [7] [7] [7] eDP C U31B DMI U31A D 25 1 1 Sheet 3 of 47 5 4 3 2 26 1 Sandy Bridge Processor (DDR3) U31C U31D D M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63 C B [13] [13] [13] [13] [13] [13] M_A_BS#0 M_A_BS#1 M_A_BS#2 M_A_CAS# M_A_RAS# M_A_WE# C5 D5 D3 D2 D6 C6 C2 C3 F10 F8 G10 G9 F9 F7 G8 G7 K4 K5 K1 J1 J5 J4 J2 K2 M8 N10 N8 N7 M10 M9 N9 M7 AG6 AG5 AK6 AK5 AH5 AH6 AJ5 AJ6 AJ8 AK8 AJ9 AK9 AH8 AH9 AL9 AL8 AP11 AN11 AL12 AM12 AM11 AL11 AP12 AN12 AJ14 AH14 AL15 AK15 AL14 AK14 AJ15 AH15 SA_DQ[0] SA_DQ[1] SA_DQ[2] SA_DQ[3] SA_DQ[4] SA_DQ[5] SA_DQ[6] SA_DQ[7] SA_DQ[8] SA_DQ[9] SA_DQ[10] SA_DQ[11] SA_DQ[12] SA_DQ[13] SA_DQ[14] SA_DQ[15] SA_DQ[16] SA_DQ[17] SA_DQ[18] SA_DQ[19] SA_DQ[20] SA_DQ[21] SA_DQ[22] SA_DQ[23] SA_DQ[24] SA_DQ[25] SA_DQ[26] SA_DQ[27] SA_DQ[28] SA_DQ[29] SA_DQ[30] SA_DQ[31] SA_DQ[32] SA_DQ[33] SA_DQ[34] SA_DQ[35] SA_DQ[36] SA_DQ[37] SA_DQ[38] SA_DQ[39] SA_DQ[40] SA_DQ[41] SA_DQ[42] SA_DQ[43] SA_DQ[44] SA_DQ[45] SA_DQ[46] SA_DQ[47] SA_DQ[48] SA_DQ[49] SA_DQ[50] SA_DQ[51] SA_DQ[52] SA_DQ[53] SA_DQ[54] SA_DQ[55] SA_DQ[56] SA_DQ[57] SA_DQ[58] SA_DQ[59] SA_DQ[60] SA_DQ[61] SA_DQ[62] SA_DQ[63] AE10 AF10 V6 SA_BS[0] SA_BS[1] SA_BS[2] AE8 AD9 AF9 SA_CAS# SA_RAS# SA_W E# SA_CLK[0] SA_CLK#[0] SA_CKE[0] AB6 AA6 V9 M_A_CLKP0 [13] M_A_CLKN0 [13] M_A_CKE0 [13] SA_CLK[1] SA_CLK#[1] SA_CKE[1] AA5 AB5 V10 M_A_CLKP1 [13] M_A_CLKN1 [13] M_A_CKE1 [13] SA_CLK[2] SA_CLK#[2] SA_CKE[2] AB4 AA4 W9 SA_CLK[3] SA_CLK#[3] SA_CKE[3] AB3 AA3 W 10 SA_CS#[0] SA_CS#[1] SA_CS#[2] SA_CS#[3] AK3 AL3 AG1 AH1 M_A_CS#0 [13] M_A_CS#1 [13] SA_ODT[0] SA_ODT[1] SA_ODT[2] SA_ODT[3] AH3 AG3 AG2 AH2 M_A_ODT0 [13] M_A_ODT1 [13] SA_DQS#[0] SA_DQS#[1] SA_DQS#[2] SA_DQS#[3] SA_DQS#[4] SA_DQS#[5] SA_DQS#[6] SA_DQS#[7] C4 G6 J3 M6 AL6 AM8 AR12 AM15 M_A_DQSN0 M_A_DQSN1 M_A_DQSN2 M_A_DQSN3 M_A_DQSN4 M_A_DQSN5 M_A_DQSN6 M_A_DQSN7 SA_DQS[0] SA_DQS[1] SA_DQS[2] SA_DQS[3] SA_DQS[4] SA_DQS[5] SA_DQS[6] SA_DQS[7] D4 F6 K3 N6 AL5 AM9 AR11 AM14 M_A_DQSP0 M_A_DQSP1 M_A_DQSP2 M_A_DQSP3 M_A_DQSP4 M_A_DQSP5 M_A_DQSP6 M_A_DQSP7 SA_MA[0] SA_MA[1] SA_MA[2] SA_MA[3] SA_MA[4] SA_MA[5] SA_MA[6] SA_MA[7] SA_MA[8] SA_MA[9] SA_MA[10] SA_MA[11] SA_MA[12] SA_MA[13] SA_MA[14] SA_MA[15] AD10 W1 W2 W7 V3 V2 W3 W6 V1 W5 AD8 V4 W4 AF8 V5 V7 M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14 M_A_A15 [14] M_B_DQ[63:0] M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8 M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15 M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31 M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39 M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46 M_B_DQ47 M_B_DQ48 M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ55 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60 M_B_DQ61 M_B_DQ62 M_B_DQ63 M_A_DQSN[7:0] [13] M_A_DQSP[7:0] [13] M_A_A[15:0] [13] [14] [14] [14] [14] [14] [14] Sandy Bridge_rPGA_Rev0p61 rpga989-47989-socket DGG^9000014 IC SOCKET RPGA 989P(P1.0,M/H3.0) M_B_BS#0 M_B_BS#1 M_B_BS#2 M_B_CAS# M_B_RAS# M_B_WE# C9 A7 D10 C8 A9 A8 D9 D8 G4 F4 F1 G1 G5 F5 F2 G2 J7 J8 K10 K9 J9 J10 K8 K7 M5 N4 N2 N1 M4 N5 M2 M1 AM5 AM6 AR3 AP3 AN3 AN2 AN1 AP2 AP5 AN9 AT5 AT6 AP6 AN8 AR6 AR5 AR9 AJ11 AT8 AT9 AH11 AR8 AJ12 AH12 AT11 AN14 AR14 AT14 AT12 AN15 AR15 AT15 SB_DQ[0] SB_DQ[1] SB_DQ[2] SB_DQ[3] SB_DQ[4] SB_DQ[5] SB_DQ[6] SB_DQ[7] SB_DQ[8] SB_DQ[9] SB_DQ[10] SB_DQ[11] SB_DQ[12] SB_DQ[13] SB_DQ[14] SB_DQ[15] SB_DQ[16] SB_DQ[17] SB_DQ[18] SB_DQ[19] SB_DQ[20] SB_DQ[21] SB_DQ[22] SB_DQ[23] SB_DQ[24] SB_DQ[25] SB_DQ[26] SB_DQ[27] SB_DQ[28] SB_DQ[29] SB_DQ[30] SB_DQ[31] SB_DQ[32] SB_DQ[33] SB_DQ[34] SB_DQ[35] SB_DQ[36] SB_DQ[37] SB_DQ[38] SB_DQ[39] SB_DQ[40] SB_DQ[41] SB_DQ[42] SB_DQ[43] SB_DQ[44] SB_DQ[45] SB_DQ[46] SB_DQ[47] SB_DQ[48] SB_DQ[49] SB_DQ[50] SB_DQ[51] SB_DQ[52] SB_DQ[53] SB_DQ[54] SB_DQ[55] SB_DQ[56] SB_DQ[57] SB_DQ[58] SB_DQ[59] SB_DQ[60] SB_DQ[61] SB_DQ[62] SB_DQ[63] AA9 AA7 R6 SB_BS[0] SB_BS[1] SB_BS[2] AA10 AB8 AB9 SB_CAS# SB_RAS# SB_W E# SB_CLK[0] SB_CLK#[0] SB_CKE[0] AE2 AD2 R9 M_B_CLKP0 [14] M_B_CLKN0 [14] M_B_CKE0 [14] SB_CLK[1] SB_CLK#[1] SB_CKE[1] AE1 AD1 R10 M_B_CLKP1 [14] M_B_CLKN1 [14] M_B_CKE1 [14] SB_CLK[2] SB_CLK#[2] SB_CKE[2] AB2 AA2 T9 SB_CLK[3] SB_CLK#[3] SB_CKE[3] AA1 AB1 T10 SB_CS#[0] SB_CS#[1] SB_CS#[2] SB_CS#[3] AD3 AE3 AD6 AE6 M_B_CS#0 [14] M_B_CS#1 [14] SB_ODT[0] SB_ODT[1] SB_ODT[2] SB_ODT[3] AE4 AD4 AD5 AE5 M_B_ODT0 [14] M_B_ODT1 [14] C DDR SYSTEM MEMORY B [13] M_A_DQ[63:0] DDR SYSTEM MEMORY A D SB_DQS#[0] SB_DQS#[1] SB_DQS#[2] SB_DQS#[3] SB_DQS#[4] SB_DQS#[5] SB_DQS#[6] SB_DQS#[7] D7 F3 K6 N3 AN5 AP9 AK12 AP15 M_B_DQSN0 M_B_DQSN1 M_B_DQSN2 M_B_DQSN3 M_B_DQSN4 M_B_DQSN5 M_B_DQSN6 M_B_DQSN7 SB_DQS[0] SB_DQS[1] SB_DQS[2] SB_DQS[3] SB_DQS[4] SB_DQS[5] SB_DQS[6] SB_DQS[7] C7 G3 J6 M3 AN6 AP8 AK11 AP14 M_B_DQSP0 M_B_DQSP1 M_B_DQSP2 M_B_DQSP3 M_B_DQSP4 M_B_DQSP5 M_B_DQSP6 M_B_DQSP7 SB_MA[0] SB_MA[1] SB_MA[2] SB_MA[3] SB_MA[4] SB_MA[5] SB_MA[6] SB_MA[7] SB_MA[8] SB_MA[9] SB_MA[10] SB_MA[11] SB_MA[12] SB_MA[13] SB_MA[14] SB_MA[15] AA8 T7 R7 T6 T2 T4 T3 R2 T5 R3 AB7 R1 T1 AB10 R5 R4 M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13 M_B_A14 M_B_A15 M_B_DQSN[7:0] [14] M_B_DQSP[7:0] [14] B M_B_A[15:0] [14] Sandy Bridge_rPGA_Rev0p61 rpga989-47989-socket DGG^9000014 IC SOCKET RPGA 989P(P1.0,M/H3.0) A A RTQLGEV"<"NZ517*Jwtqp"Tkxgt+ Swcpvc"Eqorwvgt"Kpe0 PD7 Size Custom Document Number Date: Wednesday, October 13, 2010 5 4 3 2 Rev 1A SNB 2/4 (DDR3 I/F) 1 Sheet 4 of 47 4 3 2 C67 22U/6.3V_8 C635 *22U/6.3VS_8 C126 22U/6.3V_8 C85 22U/6.3V_8 C106 22U/6.3V_8 C122 22U/6.3V_8 C147 22U/6.3V_8 C99 22U/6.3V_8 C643 *22U/6.3VS_8 C76 22U/6.3V_8 C672 *22U/6.3VS_8 C558 22U/6.3V_8 B C576 22U/6.3V_8 C617 22U/6.3V_8 C477 22U/6.3VS_8 C110 22U/6.3V_8 C557 22U/6.3VS_8 C660 *22U/6.3VS_8 22uF_8 x8 Socket TOP cavity 22uF_8 x10 Socket BOT cavity 22uF_8 x8 Socket TOP edge 470uF_7343 x4 3/26 DB change 10U FP to 0805. A +VCC_CORE [40] +VCC_GFX [40] +VCCSA [41] +1.05V_VTT [3,11,39,40] +1.5V_CPU [3] +1.5V_CPU [3] +1.5VSUS [3,11,13,14,43,45] C86 22U/6.3VS_8 C176 22U/6.3VS_8 C591 *22U/6.3V_8 C130 *22U/6.3V_8 C70 *22U/6.3VS_8 C105 22U/6.3VS_8 C585 22U/6.3VS_8 C145 *22U/6.3V_8 C177 *22U/6.3V_8 C597 *22U/6.3VS_8 C94 *22U/6.3VS_8 5/14 modify C547 C31 22U/6.3VS_8 *22U/6.3VS_8 C68 *22U/6.3VS_8 C573 *22U/6.3VS_8 C563 22U/6.3VS_8 C552 22U/6.3VS_8 C30 *22U/6.3VS_8 C143 *22U/6.3V_8 C590 *22U/6.3V_8 C149 *22U/6.3VS_8 C178 *22U/6.3V_8 C123 *22U/6.3V_8 C120 *22U/6.3VS_8 C589 *22U/6.3V_8 C63 22U/6.3VS_8 C133 *22U/6.3V_8 22uF_8 x7 Socket TOP cavity 5/4: add C8260/ C8322 22uF_8 x5 Socket BOT cavity 22uF_8 x2 Socket TOP cavity (no stuff) 8/17: PV Modify 22uF_8 x5 Socket BOT cavity (no stuff) 330uF_7343 x2 C121 *22U/6.3V_8 C598 *22U/6.3V_8 Ra R522 0_4 DIS Ra +1.8V VIDALERT# VIDSCLK VIDSOUT AJ29 AJ30 AJ28 R59 *0_4/S H_CPU_SVIDALRT# H_CPU_SVIDCLK H_CPU_SVIDDAT NC SNB: 1.5A C492 10U/6.3V_6 6/7 DB2 Modify C495 1U/6.3V_4 C494 1U/6.3V_4 + C486 330U/2V_7343 B6 A6 A2 330uF x1, 10uF_8 x1, 1uF_4 x2 Socket BOT edge. R175 1 VCCPLL1 VCCPLL2 VCCPLL3 VCC_SENSE VSS_SENSE R137 AJ35 AJ34 B10 A10 C89 10U/6.3V_6 C127 10U/6.3V_6 C549 10U/6.3V_8 H23 VCCUSA_SENSE_R VCCSA_SENSE Sandy Bridge_rPGA_Rev0p61 rpga989-47989-socket DGG^9000014 IC SOCKET RPGA 989P(P1.0,M/H3.0) +1.05V_VTT H_CPU_SVIDALRT# R96 +1.5V_CPU R747 Place PU resistor close to VR +1.5VSUS 10/01: modify *0_4/S R363 10K_4 R357 10K_4 4 3 40mile routing +1.5V_CPU +1.5VSUS Q39 AON7410 R2 220_8 1 2 3 4/27: layout modify C710 0.1U/10V_4 C712 0.1U/10V_4 C715 0.1U/10V_4 C699 0.1U/10V_4 3/26 DB add for Intel. Placement close to CPU. 2 C18 *470P/50V_4 MAIN_ONG [3,45] A 5/6: modify Q1 2N7002 CPU VDDQ RTQLGEV"<"NZ517*Jwtqp"Tkxgt+ Swcpvc"Eqorwvgt"Kpe0 SVID ALERT VR_SVID_ALERT# [40] 2 VCCUSA_SENSE [41] +1.5V PD7 Size Custom Document Number Rev 1A SNB 3/4 (POWER) Date: Wednesday, October 13, 2010 5 C485 *10U/6.3V_8 VCCSA_SEL [41] JP1 *SOLDERJUMPER-2 2 1 75_4 43_4 C545 10U/6.3V_8 5/11: Add for intel CRB 0_8 3/26 DB Modify. R89 C482 10U/6.3V_8 +VCCSA B 3/26 DB Modify. 5/12: modify Place PU resistor close to CPU *0.1U/10V_4 C714 *330U_2.5V_5.0x5.9_ESR10m C22 H_FC_C22 C24 FC_C22 VCCSA_VID1 VR_SVID_DATA [40] C921 C174 10U/6.3V_6 R358 SVID DATA H_CPU_SVIDDAT Trace Route to Power IC area. C 330uF x1, 10uF_8 x1 Socket BOT edge, 10uF_8 x2 Socket BOT cavity. 5 R100 *130/F_4 C112 10U/6.3V_6 5/23: na SNB: 6A M27 M26 L26 J26 J25 J24 H26 H25 VCCSA1 VCCSA2 VCCSA3 VCCSA4 VCCSA5 VCCSA6 VCCSA7 VCCSA8 +1.05V_VTT +1.05V_VTT R108 130/F_4 C155 10U/6.3V_6 + MAIND Place PU resistor close to CPU TP37 +1.5V_CPU 3/26 DB change 10U FP to 0805. 3/26 DB Modify. VCCP_SENSE [39] C109 10U/6.3V_8 [45] 4/27: layout modify VR_SVID_CLK [40] +1.05V_VTT MAIND 330uF x1, 10uF_8 x6 Socket BOT edge. SVID CLK *54.9/F_4 H_CPU_SVIDCLK 100_4 VSSP_SENSE R120 3 Q13 2N7002 SNB: 5A +VCC_CORE VCC_SENSE [40,46] VSS_SENSE [40,46] R135 VCCIO_SENSE VSSIO_SENSE 100_4 Place PU resistor close to VR Layout note: need routing together and ALERT need between CLK and DATA. DDR_VTTREF [13,14,43] 5/14 modify AF7 AF4 AF1 AC7 AC4 AC1 Y7 Y4 Y1 U7 U4 U1 P7 P4 P1 VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8 VDDQ9 VDDQ10 VDDQ11 VDDQ12 VDDQ13 VDDQ14 VDDQ15 5/13: modify 3/26 DB Modify. *0_8 3/26 DB change 10U FP to 0805. Sandy Bridge_rPGA_Rev0p61 rpga989-47989-socket DGG^9000014 IC SOCKET RPGA 989P(P1.0,M/H3.0) 3/26 DB change 10U FP to 0805. CAD Note: +VDDR_REF_CPU should have 10 mil trace width +VDDR_REF_CPU MAIND +1.05V_VTT +1.05V_VTT_40 D Stuff AL1 SM_VREF 100_4 SG/UMA R170 100K_4 SG/UMA Stuff DIS R130 NC 2 C131 22U/6.3VS_8 SENSE LINES J23 SNB: 21.5A VREF VCCIO40 +VCC_GFX 1 C 27 +VCC_GFX VCC_AXG_SENSE [40,46] VSS_AXG_SENSE [40,46] R124 2 C587 22U/6.3V_8 E11 D14 D13 D12 D11 C14 C13 C12 C11 B14 B12 A14 A13 A12 A11 9/26: MV Modify AK35 AK34 VAXG_SENSE VSSAXG_SENSE 3 C95 22U/6.3V_8 VCCIO25 VCCIO26 VCCIO27 VCCIO28 VCCIO29 VCCIO30 VCCIO31 VCCIO32 VCCIO33 VCCIO34 VCCIO35 VCCIO36 VCCIO37 VCCIO38 VCCIO39 C541 22U/6.3VS_8 VAXG1 VAXG2 VAXG3 VAXG4 VAXG5 VAXG6 VAXG7 VAXG8 VAXG9 VAXG10 VAXG11 VAXG12 VAXG13 VAXG14 VAXG15 VAXG16 VAXG17 VAXG18 VAXG19 VAXG20 VAXG21 VAXG22 VAXG23 VAXG24 VAXG25 VAXG26 VAXG27 VAXG28 VAXG29 VAXG30 VAXG31 VAXG32 VAXG33 VAXG34 VAXG35 VAXG36 VAXG37 VAXG38 VAXG39 VAXG40 VAXG41 VAXG42 VAXG43 VAXG44 VAXG45 VAXG46 VAXG47 VAXG48 VAXG49 VAXG50 VAXG51 VAXG52 VAXG53 VAXG54 *100_4 1 C179 22U/6.3V_8 C132 22U/6.3V_8 C69 22U/6.3VS_8 AT24 AT23 AT21 AT20 AT18 AT17 AR24 AR23 AR21 AR20 AR18 AR17 AP24 AP23 AP21 AP20 AP18 AP17 AN24 AN23 AN21 AN20 AN18 AN17 AM24 AM23 AM21 AM20 AM18 AM17 AL24 AL23 AL21 AL20 AL18 AL17 AK24 AK23 AK21 AK20 AK18 AK17 AJ24 AJ23 AJ21 AJ20 AJ18 AJ17 AH24 AH23 AH21 AH20 AH18 AH17 R130 4 C575 22U/6.3V_8 C71 22U/6.3VS_8 +1.05V_VTT DDR3 -1.5V RAILS C577 22U/6.3V_8 C555 22U/6.3V_8 AH13 AH10 AG10 AC10 Y10 U10 P10 L10 J14 J13 J12 J11 H14 H12 H11 G14 G13 G12 F14 F13 F12 F11 E14 E12 3/26 DB Modify. SA RAIL C564 22U/6.3V_8 VCCIO1 VCCIO2 VCCIO3 VCCIO4 VCCIO5 VCCIO6 VCCIO7 VCCIO8 VCCIO9 VCCIO10 VCCIO11 VCCIO12 VCCIO13 VCCIO14 VCCIO15 VCCIO16 VCCIO17 VCCIO18 VCCIO19 VCCIO20 VCCIO21 VCCIO22 VCCIO23 VCCIO24 U31G 22uF_8 x2 Socket TOP cavity 22uF_8 x2 Socket BOT cavity 22uF_8 x4 Socket TOP edge 22uF_8 x4 Socket BOT edge 470uF_7343 x2 MISC C574 22U/6.3V_8 C586 22U/6.3V_8 PEG AND DDR C623 22U/6.3V_8 SNB: 8.5A VCC1 VCC2 VCC3 VCC4 VCC5 VCC6 VCC7 VCC8 VCC9 VCC10 VCC11 VCC12 VCC13 VCC14 VCC15 VCC16 VCC17 VCC18 VCC19 VCC20 VCC21 VCC22 VCC23 VCC24 VCC25 VCC26 VCC27 VCC28 VCC29 VCC30 VCC31 VCC32 VCC33 VCC34 VCC35 VCC36 VCC37 VCC38 VCC39 VCC40 VCC41 VCC42 VCC43 VCC44 VCC45 VCC46 VCC47 VCC48 VCC49 VCC50 VCC51 VCC52 VCC53 VCC54 VCC55 VCC56 VCC57 VCC58 VCC59 VCC60 VCC61 VCC62 VCC63 VCC64 VCC65 VCC66 VCC67 VCC68 VCC69 VCC70 VCC71 VCC72 VCC73 VCC74 VCC75 VCC76 VCC77 VCC78 VCC79 VCC80 VCC81 VCC82 VCC83 VCC84 VCC85 VCC86 VCC87 VCC88 VCC89 VCC90 VCC91 VCC92 VCC93 VCC94 VCC95 VCC96 VCC97 VCC98 VCC99 VCC100 SVID C596 22U/6.3V_8 AG35 AG34 AG33 AG32 AG31 AG30 AG29 AG28 AG27 AG26 AF35 AF34 AF33 AF32 AF31 AF30 AF29 AF28 AF27 AF26 AD35 AD34 AD33 AD32 AD31 AD30 AD29 AD28 AD27 AD26 AC35 AC34 AC33 AC32 AC31 AC30 AC29 AC28 AC27 AC26 AA35 AA34 AA33 AA32 AA31 AA30 AA29 AA28 AA27 AA26 Y35 Y34 Y33 Y32 Y31 Y30 Y29 Y28 Y27 Y26 V35 V34 V33 V32 V31 V30 V29 V28 V27 V26 U35 U34 U33 U32 U31 U30 U29 U28 U27 U26 R35 R34 R33 R32 R31 R30 R29 R28 R27 R26 P35 P34 P33 P32 P31 P30 P29 P28 P27 P26 SENSE LINES D U31F +VCC_CORE CORE SUPPLY SNB: 55A Sandy Bridge Processor (GRAPHIC POWER) 9/29 MV for Power Modify. GRAPHICS Sandy Bridge Processor (POWER) 1 1.8V RAIL 5 1 Sheet 5 of 47 4 3 2 Sandy Bridge Processor (GND) U31H D C B AT35 AT32 AT29 AT27 AT25 AT22 AT19 AT16 AT13 AT10 AT7 AT4 AT3 AR25 AR22 AR19 AR16 AR13 AR10 AR7 AR4 AR2 AP34 AP31 AP28 AP25 AP22 AP19 AP16 AP13 AP10 AP7 AP4 AP1 AN30 AN27 AN25 AN22 AN19 AN16 AN13 AN10 AN7 AN4 AM29 AM25 AM22 AM19 AM16 AM13 AM10 AM7 AM4 AM3 AM2 AM1 AL34 AL31 AL28 AL25 AL22 AL19 AL16 AL13 AL10 AL7 AL4 AL2 AK33 AK30 AK27 AK25 AK22 AK19 AK16 AK13 AK10 AK7 AK4 AJ25 VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59 VSS60 VSS61 VSS62 VSS63 VSS64 VSS65 VSS66 VSS67 VSS68 VSS69 VSS70 VSS71 VSS72 VSS73 VSS74 VSS75 VSS76 VSS77 VSS78 VSS79 VSS80 VSS VSS81 VSS82 VSS83 VSS84 VSS85 VSS86 VSS87 VSS88 VSS89 VSS90 VSS91 VSS92 VSS93 VSS94 VSS95 VSS96 VSS97 VSS98 VSS99 VSS100 VSS101 VSS102 VSS103 VSS104 VSS105 VSS106 VSS107 VSS108 VSS109 VSS110 VSS111 VSS112 VSS113 VSS114 VSS115 VSS116 VSS117 VSS118 VSS119 VSS120 VSS121 VSS122 VSS123 VSS124 VSS125 VSS126 VSS127 VSS128 VSS129 VSS130 VSS131 VSS132 VSS133 VSS134 VSS135 VSS136 VSS137 VSS138 VSS139 VSS140 VSS141 VSS142 VSS143 VSS144 VSS145 VSS146 VSS147 VSS148 VSS149 VSS150 VSS151 VSS152 VSS153 VSS154 VSS155 VSS156 VSS157 VSS158 VSS159 VSS160 T35 T34 T33 T32 T31 T30 T29 T28 T27 T26 P9 P8 P6 P5 P3 P2 N35 N34 N33 N32 N31 N30 N29 N28 N27 N26 M34 L33 L30 L27 L9 L8 L6 L5 L4 L3 L2 L1 K35 K32 K29 K26 J34 J31 H33 H30 H27 H24 H21 H18 H15 H13 H10 H9 H8 H7 H6 H5 H4 H3 H2 H1 G35 G32 G29 G26 G23 G20 G17 G11 F34 F31 F29 Sandy Bridge_rPGA_Rev0p61 rpga989-47989-socket DGG^9000014 IC SOCKET RPGA 989P(P1.0,M/H3.0) U31E VSS161 VSS162 VSS163 VSS164 VSS165 VSS166 VSS167 VSS168 VSS169 VSS170 VSS171 VSS172 VSS173 VSS174 VSS175 VSS176 VSS177 VSS178 VSS179 VSS180 VSS181 VSS182 VSS183 VSS184 VSS185 VSS186 VSS187 VSS188 VSS189 VSS190 VSS191 VSS192 VSS193 VSS194 VSS195 VSS196 VSS197 VSS198 VSS199 VSS200 VSS201 VSS202 VSS203 VSS204 VSS205 VSS206 VSS207 VSS208 VSS209 VSS210 VSS211 VSS212 VSS213 VSS214 VSS215 VSS216 VSS217 VSS218 VSS219 VSS220 VSS221 VSS222 VSS223 VSS224 VSS225 VSS226 VSS227 VSS228 VSS229 VSS230 VSS231 VSS232 VSS233 VSS For CPU debug. F22 F19 E30 E27 E24 E21 E18 E15 E13 E10 E9 E8 E7 E6 E5 E4 E3 E2 E1 D35 D32 D29 D26 D20 D17 C34 C31 C28 C27 C25 C23 C10 C1 B22 B19 B17 B15 B13 B11 B9 B8 B7 B5 B3 B2 A35 A32 A29 A26 A23 A20 A3 CFG0 TP9 TP10 CFG2 TP13 CFG4 CFG5 CFG6 CFG7 [13] SMDDR_VREF_DQ0_M3 [14] SMDDR_VREF_DQ1_M3 R359 *1K_4 [39] R362 H_VTTVID1 R354 *1K_4 *0_4/S AK28 AK29 AL26 AL27 AK26 AL29 AL30 AM31 AM32 AM30 AM28 AM26 AN28 AN31 AN26 AM27 AK31 AN29 CFG[0] CFG[1] CFG[2] CFG[3] CFG[4] CFG[5] CFG[6] CFG[7] CFG[8] CFG[9] CFG[10] CFG[11] CFG[12] CFG[13] CFG[14] CFG[15] CFG[16] CFG[17] AJ31 AH31 AJ33 AH33 RSVD1 RSVD2 RSVD3 RSVD4 AJ26 RSVD5 B4 D1 RSVD6 RSVD7 F25 F24 F23 D24 G25 G24 E23 D23 C30 A31 B30 B29 D30 B31 A30 C29 RSVD8 RSVD9 RSVD10 RSVD11 RSVD12 RSVD13 RSVD14 RSVD15 RSVD16 RSVD17 RSVD18 RSVD19 RSVD20 RSVD21 RSVD22 RSVD23 J20 B18 A19 RSVD24 RSVD25 RSVD26 J15 RSVD27 RSVD28 RSVD29 RSVD30 RSVD31 RSVD32 L7 AG7 AE7 AK2 W8 RSVD33 RSVD34 RSVD35 AT26 AM33 AJ27 RSVD37 RSVD38 RSVD39 RSVD40 T8 J16 H16 G16 RSVD41 RSVD42 RSVD43 RSVD44 RSVD45 AR35 AT34 AT33 AP35 AR34 RSVD46 RSVD47 RSVD48 RSVD49 RSVD50 B34 A33 A34 B35 C35 RSVD51 RSVD52 AJ32 AK32 RSVD53 AH27 RSVD54 RSVD55 AN35 AM35 D C TP40 TP39 #27636 SNB EDS0.7v1 no function. RSVD56 RSVD57 RSVD58 AT2 AT1 AR1 For rPGA socket, RSVD59 pin should be left NC. KEY B1 B Sandy Bridge_rPGA_Rev0p61 rpga989-47989-socket DGG^9000014 IC SOCKET RPGA 989P(P1.0,M/H3.0) CFG[6:5] (PCIE Port Bifurcation Straps) The CFG signals have a default value of '1' if not terminated on the board. 1 CFG2 (PEG Static Lane Reversal) VSS234 VSS235 VSS236 VSS237 VSS238 VSS239 VSS240 VSS241 VSS242 VSS243 VSS244 VSS245 VSS246 VSS247 VSS248 VSS249 VSS250 VSS251 VSS252 VSS253 VSS254 VSS255 VSS256 VSS257 VSS258 VSS259 VSS260 VSS261 VSS262 VSS263 VSS264 VSS265 VSS266 VSS267 VSS268 VSS269 VSS270 VSS271 VSS272 VSS273 VSS274 VSS275 VSS276 VSS277 VSS278 VSS279 VSS280 VSS281 VSS282 VSS283 VSS284 VSS285 Sandy Bridge_rPGA_Rev0p61 rpga989-47989-socket DGG^9000014 IC SOCKET RPGA 989P(P1.0,M/H3.0) Processor Strapping A 11: 10: 01: 00: 0 Normal Operation Lane Reversed CFG4 (DP Presence Strap) Disable; No physical DP attached to eDP Enable; An ext DP device is connected to eDP CFG7 (PEG Defer Training) PEG train immediately following xxRESETB de assertion PEG wait for BIOS training (Default) x16 - Device 1 functions 1 and 2 disabled x8, x8 - Device 1 function 1 enabled ; function 2 disabled Reserved - (Device 1 function 1 disabled ; function 2 enabled) x8,x4,x4 - Device 1 functions 1 and 2 enabled A CFG2 R151 1K_4 CFG4 R149 *1K_4 CFG7 R144 *1K_4 CFG5 R139 *1K_4 CFG6 R146 *1K_4 RTQLGEV"<"NZ517*Jwtqp"Tkxgt+ Swcpvc"Eqorwvgt"Kpe0 PD7 Size Custom Document Number 4 3 2 Rev 1A SNB 4/4 (GND) Date: Wednesday, October 13, 2010 5 28 Sandy Bridge Processor (RESERVED, CFG) U31I AJ22 AJ19 AJ16 AJ13 AJ10 AJ7 AJ4 AJ3 AJ2 AJ1 AH35 AH34 AH32 AH30 AH29 AH28 AH26 AH25 AH22 AH19 AH16 AH7 AH4 AG9 AG8 AG4 AF6 AF5 AF3 AF2 AE35 AE34 AE33 AE32 AE31 AE30 AE29 AE28 AE27 AE26 AE9 AD7 AC9 AC8 AC6 AC5 AC3 AC2 AB35 AB34 AB33 AB32 AB31 AB30 AB29 AB28 AB27 AB26 Y9 Y8 Y6 Y5 Y3 Y2 W 35 W 34 W 33 W 32 W 31 W 30 W 29 W 28 W 27 W 26 U9 U8 U6 U5 U3 U2 1 RESERVED 5 1 Sheet 6 of 47 5 4 3 2 Cougar Point (DMI,FDI,PM) Cougar Point (LVDS,DDI) DMI0TXP DMI1TXP DMI2TXP DMI3TXP FDI_INT AW 16 FDI_INT DMI_ZCOMP FDI_FSYNC0 R282 49.9/F_4 DMI_COMP BG25 DMI_IRCOMP FDI_FSYNC1 BC10 FDI_FSYNC1 [3] R276 750/F_4 DMI_RBIAS BH21 DMI2RBIAS FDI_LSYNC0 AV14 FDI_LSYNC0 [3] FDI_LSYNC1 BB10 FDI_LSYNC1 [3] SUSACK#_R From EC XDP_DBRST# [25,35] EC_PWROK EC_PWROK_R W AKE# *0_4/S *0_4 SYS_PWROK_R R618 *0_4/S EC_PWROK_R L22 R256 *0_4/S APWROK_R L10 PM_DRAM_PWRGD B13 DRAMPW ROK RSMRST# C21 RSMRST# SUS_PWR_ACK_R K16 SUSW ARN#/SUSPW RDNACK/GPIO30 PW RBTN# RSMRST# *0_4/S P12 R624 [35] DNBSWON# R638 *0_4/S DNBSWON#_R E20 [35] AC_PRESENT R630 *0_4 AC_PRESENT_R H20 B PW ROK APW ROK (+3VS5) [35] SUS_PWR_ACK 8/6: PV modify SYS_PW ROK B9 CLKRUN# / GPIO32 N3 6/30 : add TP DSWVREN R642 PCIE_WAKE# SUSCLK / GPIO62 N14 5/12: modify CLKRUN# *0_4/S PCH_SUSCLK [35] SLP_S5 SLP_S4# H4 R219 *0_4/S SUSC# [35] SLP_S3# F4 R600 *0_4/S SUSB# [35] G10 SLP_SUS# PMSYNCH AP14 +3VS5 R615 10K_4 PM_BATLOW# R616 *8.2K_4 PCIE_WAKE# R614 10K_4 SLP_LAN# R632 ACPRESENT / GPIO31 TP25 5/11: R627 10K_4 AC_PRESENT_R R629 10K_4 A E10 BATLOW # / GPIO72 PM_RI# A10 RI# (+3VS5) SLP_LAN# / GPIO29 INT LVDS & CRT disable (DIS only remove) 3/26 DB change net name. 8/17: PV modify +3V CTRL_CLK CTRL_DATA R690 R691 *2.2K_4 *2.2K_4 R294 *2.37K/F_4 LVD_IBG R323 R325 [24] PCH_HSYNC [24] PCH_VSYNC *33_4 *33_4 LVDSA_DATA#0 LVDSA_DATA#1 LVDSA_DATA#2 LVDSA_DATA#3 [24] PCH_LA_DATAP0 [24] PCH_LA_DATAP1 [24] PCH_LA_DATAP2 PCH_LA_DATAP0 PCH_LA_DATAP1 PCH_LA_DATAP2 AN47 AM49 AK49 AJ47 LVDSA_DATA0 LVDSA_DATA1 LVDSA_DATA2 LVDSA_DATA3 PCH_LB_CLK# PCH_LB_CLK AF40 AF39 LVDSB_CLK# LVDSB_CLK PCH_LB_DATAN0 PCH_LB_DATAN1 PCH_LB_DATAN2 AH45 AH47 AF49 AF45 LVDSB_DATA#0 LVDSB_DATA#1 LVDSB_DATA#2 LVDSB_DATA#3 PCH_LB_DATAP0 PCH_LB_DATAP1 PCH_LB_DATAP2 AH43 AH49 AF47 AF43 LVDSB_DATA0 LVDSB_DATA1 LVDSB_DATA2 LVDSB_DATA3 K14 +3V PD Res place close to PCH PCH_HSYNC_R PCH_VSYNC_R 8/13: PV add PCH_CRT_B XDP_DBRST# R583 10K_4 R576 *1K_4 R313 *150/F_4 PCH_CRT_B RSMRST# R647 10K_4 R318 *150/F_4 PCH_CRT_G SYS_PWROK R621 *10K_4 R321 *150/F_4 PCH_CRT_R N48 P49 T49 CRT_BLUE CRT_GREEN CRT_RED T39 M40 CRT_DDC_CLK CRT_DDC_DATA M47 M49 CRT_HSYNC CRT_VSYNC T43 T42 DAC_IREF CRT_IRTN DAC_IREF PCH_CRT_G C915 C916 SLP_LAN# R689 1K/F_4 PCH_CRT_R C917 TP9041 PM_SYNC [3] INT HDMI disable (DIS only remove) AM42 AM40 SDVO_INTN SDVO_INTP AP39 AP40 D P38 M39 SDVO_CLK [27] SDVO_DATA [27] DDPB_AUXN DDPB_AUXP DDPB_HPD AT49 AT47 AT40 DPB_HPD_Q DDPB_0N DDPB_0P DDPB_1N DDPB_1P DDPB_2N DDPB_2P DDPB_3N DDPB_3P AV42 AV40 AV45 AV46 AU48 AU47 AV47 AV49 DPB_LANE0_N DPB_LANE0_P DPB_LANE1_N DPB_LANE1_P DPB_LANE2_N DPB_LANE2_P DPB_LANE3_N DPB_LANE3_P DDPC_CTRLCLK DDPC_CTRLDATA P46 P42 DDPC_AUXN DDPC_AUXP DDPC_HPD AP47 AP49 AT38 DDPC_0N DDPC_0P DDPC_1N DDPC_1P DDPC_2N DDPC_2P DDPC_3N DDPC_3P AY47 AY49 AY43 AY45 BA47 BA48 BB47 BB49 DDPD_CTRLCLK DDPD_CTRLDATA C M43 M36 DDPD_AUXN DDPD_AUXP DDPD_HPD AT45 AT43 BH41 DDPD_0N DDPD_0P DDPD_1N DDPD_1P DDPD_2N DDPD_2P DDPD_3N DDPD_3P BB43 BB45 BF44 BE44 BF42 BE42 BJ42 BG42 CougarPoint_Rev_0p7 fcbga989-intel-cougarpoint AJ0QNJH0T03 IC CTRL(989P)PCH-HM65 QNJH FCBGA TOP B/S B +1.05V [8,9,11,34,35,41] +3V_RTC [8,11] +3V_DSW [8,11] +3VPCU [8,25,32,34,35,36,37,38,39,40,42,44,45,47] +3VS5 [3,8,9,10,11,45] +3V [3,8,9,10,11,13,14,18,19,25,26,27,28,29,30,31,32,33,34,35,36,37,39,40,41,43,45,46,47] +5V [8,11,19,25,26,27,29,30,32,34,36,37,45] System PWR_OK(CLG) DPWROK FOR DSW +3VPCU +3VS5 DPB_LANE0_N DPB_LANE0_P DPB_LANE1_N DPB_LANE1_P DPB_LANE2_N DPB_LANE2_P DPB_LANE3_N DPB_LANE3_P C420 C421 C422 C426 C433 C432 C434 C435 *0_4/S *0_4/S *0_4/S *0_4/S *0_4/S *0_4/S *0_4/S *0_4/S IN_D2# IN_D2 IN_D1# IN_D1 IN_D0# IN_D0 IN_CLK# IN_CLK [27] [27] [27] [27] [27] [27] [27] [27] R715 DPB_HPD_Q R711 *100K_4 *0_4 1 SYS_PWROK Q47 *2N7002K +3V_DSW DPWROK 0_4 R633 330K_4 2 +3VPCU Q44 *PDTC144EU DSWVREN R637 RTQLGEV"<"NZ517*Jwtqp"Tkxgt+ Swcpvc"Eqorwvgt"Kpe0 *330K_4 PD7 Size Custom Document Number 3 2 Rev 1A PCH 1/6 (DMI/FDI/VIDEO) Date: Wednesday, October 13, 2010 4 A Q43 *2N7002 6/4 :DB2 modify [27] High = Enable (Default) Low = Disable 7/2 SI modify add cap to timing tune 2 *RB500V-40 On Die DSW VR Enable +5V C780 *0.1U/10V_4 D17 R620 100K_4 8/13 PV update. R246 R626 *10K_4 +3VS5 *RB500V-40 +3V_RTC R707 *100K_4 EC_PWROK R631 *10K_4 D16 IMVP_PWRGD [40] 4 4/20 DB update. HDMI_HPD_CON 5/12: modify *0.1U/10V_4 2 1 9/26: MV modify 3 +3VPCU C779 U43 *TC7SH08FU 4/29 modify PCH to Res routeing 50 ohm Impedance. Res to connector filter routeing 37.5ohm Impedance. PCH_CRT_B PCH_CRT_G PCH_CRT_R [24] PCH_DDCCLK [24] PCH_DDCDATA INT HDMI Detect Function R591 5 AN48 AM47 AK47 AJ48 add TP9048 PCH_HSYNC_R PCH_VSYNC_R CLKRUN# 8.2K_4 PCH_LA_DATAN0 PCH_LA_DATAN1 PCH_LA_DATAN2 TP54 5/7: DEL R8304 , Add (+3VS5) PM_BATLOW# *10K_4 SUS_PWR_ACK [24] PCH_LA_DATAN0 [24] PCH_LA_DATAN1 [24] PCH_LA_DATAN2 (DSW) 2 PM_RI# LVDSA_CLK# LVDSA_CLK [24] PCH_CRT_B [24] PCH_CRT_G [24] PCH_CRT_R CougarPoint_Rev_0p7 fcbga989-intel-cougarpoint AJ0QNJH0T03 IC CTRL(989P)PCH-HM65 QNJH FCBGA TOP B/S PCH Pull-high/low(CLG) AK39 AK40 [24] PCH_LB_DATAP0 [24] PCH_LB_DATAP1 [24] PCH_LB_DATAP2 TP29 [35] G16 PCH_LA_CLK# PCH_LA_CLK SDVO_STALLN SDVO_STALLP SDVO_CTRLCLK SDVO_CTRLDATA TP26 PCH_SUSCLK_L R271 D10 SLP_A# LVD_VREFH LVD_VREFL [24] PCH_LB_DATAN0 [24] PCH_LB_DATAN1 [24] PCH_LB_DATAN2 CLKRUN# [35] (+3VS5) SLP_S5# / GPIO63 LVD_IBG LVD_VBG PCIE_WAKE# [33,36] G8 (+3VS5) AF37 AF36 AE48 AE47 [24] PCH_LB_CLK# [24] PCH_LB_CLK *0_4/S RSMRST# DPWROK *0_4/S (+3VS5) SUS_STAT# / GPIO61 L_CTRL_CLK L_CTRL_DATA TP67 R645 (+3V) R625 R617 [3] PM_DRAM_PWRGD [35] SYS_RESET# DPW ROK E22 T45 P39 AP43 AP45 5 SYS_PWROK K3 A18 CTRL_CLK CTRL_DATA *220P/50V_4 XDP_DBRST# SUSACK# DSW VRMEN [3] *220P/50V_4 5/7: DEL R8293 for SUSACK# C12 System Power Management *0_4/S L_DDC_CLK L_DDC_DATA T2 [3] FDI_FSYNC0 L_BKLTCTL T40 K47 LVD_IBG AV12 SUS_PWR_ACK_R R623 [3] 3/26 DB change net name. [24] PCH_LA_CLK# [24] PCH_LA_CLK TP66 C [24] PCH_EDIDCLK [24] PCH_EDIDDATA *220P/50V_4 +1.05V BJ24 P45 PCH_EDIDCLK PCH_EDIDDAT [24] PCH_DPST_PWM SDVO_TVCLKINN SDVO_TVCLKINP 3 AY24 AY20 AY18 AU18 L_BKLTEN L_VDD_EN 1 DMI_TXP0 DMI_TXP1 DMI_TXP2 DMI_TXP3 [3] [3] [3] [3] [3] [3] [3] [3] J47 M45 3 [3] [3] [3] [3] FDI_TXP0 FDI_TXP1 FDI_TXP2 FDI_TXP3 FDI_TXP4 FDI_TXP5 FDI_TXP6 FDI_TXP7 [24] PCH_LVDS_BLON [24] PCH_DISP_ON 1 DMI0TXN DMI1TXN DMI2TXN DMI3TXN BG14 BB14 BF14 BG13 BE12 BG12 BJ10 BH9 [3] [3] [3] [3] [3] [3] [3] [3] Digital Display Interface AW 24 AW 20 BB18 AV18 FDI_RXP0 FDI_RXP1 FDI_RXP2 FDI_RXP3 FDI_RXP4 FDI_RXP5 FDI_RXP6 FDI_RXP7 FDI_TXN0 FDI_TXN1 FDI_TXN2 FDI_TXN3 FDI_TXN4 FDI_TXN5 FDI_TXN6 FDI_TXN7 CRT DMI_TXN0 DMI_TXN1 DMI_TXN2 DMI_TXN3 BJ14 AY14 BE14 BH13 BC12 BJ12 BG10 BG9 INT. HDMI [3] [3] [3] [3] FDI_RXN0 FDI_RXN1 FDI_RXN2 FDI_RXN3 FDI_RXN4 FDI_RXN5 FDI_RXN6 FDI_RXN7 3 DMI0RXP DMI1RXP DMI2RXP DMI3RXP FDI BE24 BC20 BJ18 BJ20 DMI_RXP0 DMI_RXP1 DMI_RXP2 DMI_RXP3 U44D DMI0RXN DMI1RXN DMI2RXN DMI3RXN DMI [3] [3] [3] [3] D BC24 BE20 BG18 BG20 DMI_RXN0 DMI_RXN1 DMI_RXN2 DMI_RXN3 LVDS U44C [3] [3] [3] [3] 29 1 1 Sheet 7 of 47 5 4 U44A [29] N34 ACZ_SYNC L34 HDA_SYNC SPKR T10 SPKR ACZ_RST# K34 HDA_RST# TP32 SERIRQ E34 HDA_SDIN0 G34 HDA_SDIN1 HDA_SDIN3 A36 HDA_SDO (+3V) GPIO33 TP31 C36 HDA_DOCK_EN# / GPIO33 N32 HDA_DOCK_RST# / GPIO13 (+3VS5) 0.01U/25V_4 0.01U/25V_4 0.01U/25V_4 0.01U/25V_4 SATA1RXN SATA1RXP SATA1TXN SATA1TXP AM10 AM8 AP11 AP10 SATA_RXN1_C SATA_RXP1_C SATA_TXN1_C SATA_TXP1_C C688 C683 C375 C373 0.01U/25V_4 0.01U/25V_4 0.01U/25V_4 0.01U/25V_4 SATA2RXN SATA2RXP SATA2TXN SATA2TXP AD7 AD5 AH5 AH4 SATA3RXN SATA3RXP SATA3TXN SATA3TXP AB8 AB10 AF3 AF1 SATA4RXN SATA4RXP SATA4TXN SATA4TXP Y7 Y5 AD3 AD1 SATA_RXN4_C SATA_RXP4_C SATA_TXN4_C SATA_TXP4_C C562 C566 C365 C366 0.01U/25V_4 0.01U/25V_4 0.01U/25V_4 0.01U/25V_4 SATA_RXN5_C SATA_RXP5_C SATA_TXN5_C SATA_TXP5_C C716 C713 C372 C371 0.01U/25V_4 0.01U/25V_4 0.01U/25V_4 0.01U/25V_4 JTAG_TCK SATA5RXN SATA5RXP SATA5TXN SATA5TXP TP18 PCH_JTAG_TMS H7 JTAG_TMS SATAICOMPO Y11 TP17 PCH_JTAG_TDI_R K5 JTAG_TDI SATAICOMPI Y10 TP16 PCH_JTAG_TDO_R H1 JTAG_TDO R572 *10K_4 PCH_SPI_CS1# PCH_SPI_SI PCH_SPI_SO Y14 SPI_CS1# V4 SPI_MOSI JTAG 5/6: modify RTC Circuitry(RTC) +3V_RTC R327 R260 5/6: modify SATA_RXN4 [34] SATA_RXP4 [34] SATA_TXN4 [34] SATA_TXP4 [34] R263 49.9/F_4 SATA3RBIAS AH1 SATA3_RBIAS R597 750/F_4 SATA1GP / GPIO19 FOR DSW +3VPCU R330 *0_6/S +3V_RTC_2 1K_4 +3V_RTC_1 C438 1U/6.3V_4 R317 20K/F_4 J2 *SOLDERJUMPER-2 SRTC_RST# CN29 BAT_CONN 4/29: modify D6 BAT54C C440 1U/6.3V_4 C428 1U/6.3V_4 J1 *SOLDERJUMPER-2 C 4/20 DB add. RTC Power trace width 20mils. E-SATA RTC_RST# 6/9 : DB2 Modify Footprint +1.05V *0_6 SRTC_RST# R297 PCH JTAG Debug(CLG) HDA Bus(CLG) 5/3 : modify +3VS5 SATA_LED# [32] SPI_MISO *0_6 ODD (SATA1 1.5Gb/s) SATA_RXN5 [32] SATA_RXP5 [32] SATA_TXN5 [32] SATA_TXP5 [32] 37.4/F_4 SATA3_COMP (+3V) +3V_DSW R319 3/26 DB modify for placement. SATA_COMP AB13 SATA0GP / GPIO21 RTC_RST# 5/12: modify DG recommended that AC coupling capacitors should be close to the connector (<100 mils) for optimal signal quality. SATA3COMPI SATALED# 30mils HDD1 (SATA3 6.0Gb/s) 20K/F_4 SATA3RCOMPO (+3V) U3 HDD0 (SATA3 6.0Gb/s) SATA_RXN1 [34] SATA_RXP1 [34] SATA_TXN1 [34] SATA_TXP1 [34] SPI_CS0# T1 D RTC_X2 5/6: modify SATA_RXN0 [34] SATA_RXP0 [34] SATA_TXN0 [34] SATA_TXP0 [34] 3/26 DB modify for placement. AB12 SPI_CLK SPI PCH_SPI_CS0# T3 R641 10M_4 [35] +3V_RTC_0 R328 J3 PCH_SPI_CLK +3VPCU C882 C881 C368 C363 PCH_JTAG_TCK_R 6/30 SI Modify +3V SERIRQ SATA_RXN0_C SATA_RXP0_C SATA_TXN0_C SATA_TXP0_C TP23 C Y4 32.768KHZ 8.2K_4 AM3 AM1 AP7 AP5 Y3 Y1 AB3 AB1 18P/50V_4 TP33 TP34 R245 SATA0RXN SATA0RXP SATA0TXN SATA0TXP HDA_SDIN2 A34 C788 RTC_X1 2 1 SERIRQ HDA_BCLK C34 ACZ_SDOUT PCH_DRQ#0 PCH_DRQ#1 V5 INTVRMEN ACZ_BCLK ACZ_SDIN0 E36 K36 (+3V) TP70 SPKR LDRQ0# LDRQ1# / GPIO23 18P/50V_4 1 C17 C789 2 INTRUDER# PCH_INVRMEN LFRAME# [35,36] 1 SRTCRST# K22 D36 2 G22 SM_INTRUDER# FW H4 / LFRAME# 3 4 RTCRST# R590 P3 V14 DGT_STOP# P1 BBS_BIT0 10K_4 [29] BIT_CLK_AUDIO R299 33_4 ACZ_BCLK [29] ACZ_RST#_AUDIO R666 33_4 ACZ_RST# [29] ACZ_SDOUT_AUDIO R656 33_4 ACZ_SDOUT +3V +5V R748 10K_4 10/13: MV modify 4/29: modify R239 *210/F_4 R208 *210/F_4 R204 *210/F_4 PCH_JTAG_TMS PCH_JTAG_TDI_R PCH_JTAG_TDO_R PCH_JTAG_TCK_R 2 D20 SRTC_RST# [35,36] [35,36] [35,36] [35,36] 1 RTCX2 RTC_RST# LAD0 LAD1 LAD2 LAD3 LPC C20 C38 A38 B37 C37 SATA 6G 1M_4 RTC_X2 LAD0 LAD1 LAD2 LAD3 FW H0 / FW H1 / FW H2 / FW H3 / SATA R275 RTCX1 RTC TP74 A20 RTC Clock 32.768KHz +1.05V [7,9,11,34,35,41] +1.8V [5,11,39,45] +3V_RTC [7,11] +3V_DSW [7,11] +3VPCU [7,25,32,34,35,36,37,38,39,40,42,44,45,47] +3V [3,7,9,10,11,13,14,18,19,25,26,27,28,29,30,31,32,33,34,35,36,37,39,40,41,43,45,46,47] +V3.3A_1.5A_HDA_IO [11] 3/26 DB change net name. RTC_X1 IHDA 6/30 SI Modify [29] 2: 1 2 TP69 +3V_RTC 2 Cougar Point (HDA,JTAG,SATA) 4/29 DB change net name. TP68 D 3 DGT_STOP# [32] Bios swap GPIO 4/23. DGT_STOP# 10K_4 R661 [29] ACZ_SYNC_AUDIO 3 ACZ_SYNC 33_4 1 Q48 B PCH Strap Table Pin Name SPKR Strap description Different from Calpella No reboot mode setting Sampled PWROK 0 = Default (weak pull-down 20K) 1 = Setting to No-Reboot mode SPKR R568 R687 R700 Top-Block Swap Override PWROK INTVRMEN Integrated 1.05V VRM enable ALWAYS Should be always pull-up PCH_INVRMEN HDA_DOCK_EN#/GPIO33 Flash Descriptor Security Only for Interposer PWROK 0 = Override 1 = Default (weak pull-up 20K) GPIO33 GPIO19 Boot BIOS Selection 1 [bit-1] Boot BIOS Selection 0 [bit-0] PWROK GNT1# GNT0# 1 0 1 0 PWROK Boot Location ESI strap (Server only) PWROK NV_ALE Intel Anti-Theft HDD protection Only for Interposer PWROK 0 = Disable (Internal pull-down 20kohm) HDA_SYNC On-Die PLL VR Voltage Select HDA_SDO Flash Descriptor Security GPIO8 GPIO28 Different from Calpella SPI_MOSI PWROK RSMRST PWROK +3V *1M_4 R240 *100/F_4 2N7002K weak pull-down 20kohm +3V R209 *100/F_4 R640 330K_4 R659 1 4/23. +3V_RTC 0_4 2 BIOS_WP# [Need external pull-down for LPC BIOS] Default weak pull-up on GNT0/1# 9/30: MV modify 6/28 SI modify PCH_SPI_CS0# PCH_SPI_CLK PCH_SPI_SI PCH_SPI_SO +1.8V +1.8V 0 = Support by 1.8V (weak pull-down) 1 = Support by 1.5V 0 = Override 1 = Default (weak pull-up 20K) R595 +3VS5 R596 +3V CE# SCK SI SO HOLD# 7 3 W P# VSS 4 VDD 8 R639 3.3K_4 C784 0.1U/10V_4 SPI Flash Socket R603 BIOS_WP# 3.3K_4 9/30: MV modify TP59 NV_ALE R609 R307 1 6 5 2 BBS_BIT1 [9] *1K_4 2.2K_4 +3V U42 PCH_SPI1_CLK_R PCH_SPI1_SI_R PCH_SPI1_SO_R *0_4/S *0_4/S *0_4/S BBS_BIT0 *1K_4 *1K_4 4.7K_4 1K_4 [9] [9]N.A at CPT EDS 0.7 NV_CLE H_SNB_IVB# [3] ACZ_SYNC P/N Vender Size EON 4MB AKE39FN0Q00 (EN25F32-100HIP) Winbond 4MB AKE391P0N00 (W25Q32BVSSIG) Socket A DG008000031 8/12 PV Modify. [35] ACZ_SDOUT GPIO33_E Integrated Clock Chip Enable RSMRST# Should be pull-down (weak pull-up 20K) R619 On-die PLL Voltage Regulator RSMRST# 0 = Disable 1 = Enable (Default) R608 *1K_4 iTPM function Disable APWROK 0 = Default (weak pull-down 20K) 1 = Enable R634 1K_4 4 R233 *51_4 PCH SPI ROM(CLG) TP57 TP58 C783 *22P/50V_4 USE GPIO PIN 4/29 modify R636 R635 R606 TP64 TP65 *1K_4 R662 *1K_4 +V3.3A_1.5A_HDA_IO 4/29 reserve. ICC_EN# RTQLGEV"<"NZ517*Jwtqp"Tkxgt+ Swcpvc"Eqorwvgt"Kpe0 [10] PLL_ODVR_EN [10] Size PCH_SPI_SI PD7 +3V Document Number Custom PCH 2/6 (SATA/HDA/SPI) Date: Wednesday, October 13, 2010 5 R205 *100/F_4 B 6/23: SI modify PCI_GNT3# [9] Bios request, for can't boot Capella R573 R686 GNT2# / GPIO53 DMI Termination voltage +3V *1K_4 *1K_4 10K_4 SPI LPC Should not be pull-down (weak pull-up 20K) NV_CLE R785 9/30 : MV Modify 6/4 : DB2 Modify GNT3# / GPIO55 Different from Calpella R215 Circuit Configuration 0 = "top-block swap" mode 1 = Default (weak pull-up 20K) GNT1# / GPIO51 A CougarPoint_Rev_0p7 fcbga989-intel-cougarpoint AJ0QNJH0T03 IC CTRL(989P)PCH-HM65 QNJH FCBGA TOP B/S 3 2 1 Sheet 8 Rev 1A of 47 5 4 3 2 Cougar Point-M (PCI,USB,NVRAM) 10K_10P8R_6 3/26 DB change Part reference. +3VS5 RP20 10 9 8 7 6 USB_OC4# USB_OC1# USB_OC2# USB_OC3# USB_OC6# USB_OC0# USB_OC7# USB_OC5# 1 2 3 4 5 B21 M20 AY16 BG46 TP21 TP22 TP23 TP24 NV_ALE NV_CLE NV_RCOMP NV_RB# 10K_10P8R_6 MPC Switch Control MPC_PWR_CTRL# Low = MPC ON High = MPC OFF (Default) MPC_PWR_CTRL# R682 *1K_4 C CLK_33M_DEBUG L63 CLK_33M_KBC L64 C897 *27P/50V_4 BE28 BC30 BE32 BJ32 BC28 BE30 BF32 BG32 AV26 BB26 AU28 AY30 AU26 AY26 AV28 AW30 *33nH/600mA_6 TP25 TP26 TP27 TP28 TP29 TP30 TP31 TP32 TP33 TP34 TP35 TP36 TP37 TP38 TP39 TP40 NV_RE#_WRB0 NV_RE#_WRB1 NV_WE#_CK0 NV_WE#_CK1 C898 *27P/50V_4 *33nH/600mA_6 [8] BBS_BIT1 PWM_SELECT# [8] PCI_GNT3# [25] LCD_BK [37] DGPU_HOLD_RST# [30] INTH# Bios swap GPIO 4/23. BT_COMBO_EN# DGPU_SELECT# C46 C44 E40 REQ1# / GPIO50 REQ2# / GPIO52 REQ3# / GPIO54 BBS_BIT1 PWM_SELECT# PCI_GNT3# D47 E42 F46 GNT1# / GPIO51 (+3V) GNT2# / GPIO53 (+3V) GNT3# / GPIO55 (+3V) MPC_PWR_CTRL# LCD_BK DGPU_HOLD_RST# INTH# G42 G40 C42 D44 PCI_PME# K10 TP24 PCI_PLTRST# B CLK_PCI_TPM_R CLK_PCI_CARD_R TP56 TP36 [36] CLK_33M_DEBUG [35] CLK_33M_KBC R324 R316 CLK_PCI_FB R315 22_4 22_4 C6 H49 H43 J48 K42 H40 PIRQE# / GPIO2 PIRQF# / GPIO3 PIRQG# / GPIO4 PIRQH# / GPIO5 USBRBIAS (+3VS5) (+3VS5) (+3VS5) (+3VS5) (+3VS5) (+3VS5) (+3VS5) (+3VS5) PLTRST# CLKOUT_PCI0 CLKOUT_PCI1 CLKOUT_PCI2 CLKOUT_PCI3 CLKOUT_PCI4 4/20 modify [14,30,35] MBCLK2 AY5 BA2 OC0# / GPIO59 OC1# / GPIO40 OC2# / GPIO41 OC3# / GPIO42 OC4# / GPIO43 OC5# / GPIO9 OC6# / GPIO10 OC7# / GPIO14 PLTRST# 3 Q14 PLTRST# C24 A24 C25 B25 C26 A26 K28 H28 E28 D28 C28 A28 C29 B29 N28 M28 L30 K30 G30 E30 C30 A30 L32 K32 G32 E32 C32 A32 C33 3 1 2 R300 4.7K_4 R298 4.7K_4 +3V 2 6/9: modify 3 Q18 2N7002K DGPU_PWROK_1 [43] 3 4 PCH_CLK_27M [18] SMB_PCH_CLK 3 E-Sata Fingerprint 1 CLK_PCH_SRC0N CLK_PCH_SRC0P Y40 Y39 SMB_RUN_CLK [13,14] SMBUS CL_CLK1 CLK_PCIE_REQ0# J2 Webcam CLK_PCH_SRC2N CLK_PCH_SRC2P AB49 AB47 CLK_PCIE_REQ1# CL_DATA1 CL_RST1# CLKOUT_PEG_A_N CLKOUT_PEG_A_P (+3VS5) M1 CLKOUT_PCIE2N CLKOUT_PCIE2P V10 PCIECLKRQ2# / GPIO20 Y37 Y36 CLKOUT_PCIE3N CLKOUT_PCIE3P (+3V) Right_USB 15" CLK_PCIE_REQ3# A8 CLK_PCIE_REQ4# R654 22.6/F_4 CLKOUT_PCIE4N CLKOUT_PCIE4P L12 [10] M16 SMB_ME1_DAT M7 CL_CLK_R TP19 T11 CL_DAT_R TP21 P10 CL_RST#_R TP20 M10 CLK_PEGA_REQ# AB37 AB38 CLK_PCH_PEGAN CLK_PCH_PEGAP TP28 BF18 BE18 CLK_BUF_PCIE_3GPLL# CLK_BUF_PCIE_3GPLL BJ30 BG30 CLK_BUF_BCLK_N CLK_BUF_BCLK_P G24 E24 CLK_BUF_DREFCLK# CLK_BUF_DREFCLK AK7 AK5 CLK_BUF_DREFSSCLK# CLK_BUF_DREFSSCLK K45 CLK_PCH_14M H45 CLK_PCI_FB REFCLK14IN TP71 CLKIN_PCILOOPBACK (+3VS5) CLK_PEGB_REQ# 3/26 DB del external clock generator. C830 18P/50V_4 PCIECLKRQ5# / GPIO44 AB42 AB40 TP22 C CLKIN_DMI_N CLKIN_DMI_P CLKOUT_PCIE5N CLKOUT_PCIE5P L14 BOARD_ID0 SMB_ME1_CLK CLK_DPLL_SSCLKN [3] CLK_DPLL_SSCLKP [3] CLKIN_SATA_N CLKIN_SATA_P (+3VS5) USB_OC0# USB_OC1# USB_OC2# USB_OC3# USB_OC4# USB_OC5# USB_OC6# USB_OC7# SML1ALERT#_R CLKOUT_PEG_B_N CLKOUT_PEG_B_P E6 XTAL25_IN XTAL25_OUT V47 V49 R683 1M_4 XTAL25_IN XTAL25_OUT R238 R229 BOARD_ID1 [10] BOARD_ID2 C829 18P/50V_4 PEG_B_CLKRQ# / GPIO56 V40 V42 +3V 10K_4 10K_4 PCIECLKRQ6# / GPIO45 CLKOUT_PCIE7N CLKOUT_PCIE7P CLK_PCH_ITPN CLK_PCH_ITPP +3VS5 CLK_PCIE_REQ0# CLK_PCIE_REQ3# CLK_PCIE_REQ4# R599 R610 R247 10K_4 10K_4 10K_4 CLK_PEGB_REQ# CLK_PEGA_REQ# CLK_PEGA_REQ# R244 10K_4 R289 R288 10K_4 10K_4 CLK_BUF_PCIE_3GPLL# CLK_BUF_PCIE_3GPLL CLK_BUF_DREFCLK# CLK_BUF_DREFCLK CLK_BUF_DREFSSCLK# CLK_BUF_DREFSSCLK CLK_PCH_14M R269 R265 R290 R286 R242 R243 R309 10K_4 10K_4 10K_4 10K_4 10K_4 10K_4 10K_4 Y47 XCLK_RCOMP R688 PCIECLKRQ7# / GPIO46 (+3VS5) CLKOUT_ITPXDP_N CLKOUT_ITPXDP_P CougarPoint_Rev_0p7 fcbga989-intel-cougarpoint CLKOUTFLEX0 / GPIO64 (+3V) CLKOUTFLEX1 / GPIO65 (+3V) CLKOUTFLEX2 / GPIO66 (+3V) CLKOUTFLEX3 / GPIO67 K43 F47 CLK_FLEX1 R304 [36] PCIE_CLKREQ_WLAN# K49 CLK_FLEX3 R692 *0_4/S CLK_PCIE_REQ0# CLK_PCH_SRC2N CLK_PCH_SRC2P [33] CLK_PCIE_LANN [33] CLK_PCIE_LANP [33] PCIE_CLKREQ_LAN# R589 *0_4/S CLK_PCIE_REQ1# [15] CLK_PCIE_VGA# [15] CLK_PCIE_VGA +3VS5 +3V CLOCK TERMINATION for FCIM RP14 2 0_4P2R_4 4 1 3 CLK_PCH_PEGAN CLK_PCH_PEGAP Remove for UMA only. [3,7,8,10,11,45] [3,7,8,10,11,13,14,18,19,25,26,27,28,29,30,31,32,33,34,35,36,37,39,40,41,43,45,46,47] R250 1K_4 DRAMRST_CNTRL_PCH R252 R268 R264 R607 R261 R258 10K_4 2.2K_4 2.2K_4 2.2K_4 2.2K_4 10K_4 SMBALERT# SMB_PCH_CLK SMB_PCH_DAT SMB_ME0_CLK SMB_ME0_DAT SML1ALERT#_R PD7 Size Custom Document Number 4 3 2 Rev 1A PCH 3/6 (PCIE/USB/CLK) Date: Wednesday, October 13, 2010 5 A RTQLGEV"<"NZ517*Jwtqp"Tkxgt+ Swcpvc"Eqorwvgt"Kpe0 3/26 DB change Part reference. GPU SMBus/Pull-up(CLG) +3VS5 3/26 DB change Part reference. LAN *22_4 PCH_CLK_27M_1 Remove Ra, Rb for UMA & SG. 27MHz support DIS only. CLK_PCH_SRC0N CLK_PCH_SRC0P R577 CLK_48M_CR [28] TP55 Rb 3/26 DB change Part reference. WLAN 22_4 H47 CLK_FLEX2 AJ0QNJH0T03 IC CTRL(989P)PCH-HM65 QNJH FCBGA TOP B/S [36] CLK_PCIE_WLANN [36] CLK_PCIE_WLANP +1.05V remove CLK_27M_VGA 5/13: modify CLK_48M to CLK_FLEX1 (+3V) (+3VS5) 90.9/F_4 TP354/29: CLK_FLEX0 PCIE Clock *10K_4 Ra R236 10K_4 Rb R227 SG : Rb ; UMA : Ra CLK_BUF_BCLK_N CLK_BUF_BCLK_P XCLK_RCOMP V38 V37 AK14 AK13 TP30 TP27 TP72 CLKOUT_PCIE6N CLKOUT_PCIE6P T13 K12 B Y5 25MHz (+3VS5) [10] D [3] PCIECLKRQ4# / GPIO26 V45 V46 4/23. C13 E14 AM12 AM13 CLKIN_DOT_96N CLKIN_DOT_96P (+3VS5) Y43 Y45 USB_BIAS SMB_ME0_DAT CLKOUT_DP_N CLKOUT_DP_P CLKIN_GND1_N CLKIN_GND1_P PCIECLKRQ3# / GPIO25 Card Reaer Blue tooth G12 DRAMRST_CNTRL_PCH CLK_CPU_BCLKN [3] CLK_CPU_BCLKP [3] CLOCKS PCIECLKRQ1# / GPIO18 Right_USB 15" WLAN SMB_ME0_CLK AV22 AU22 CLKOUT_DMI_N CLKOUT_DMI_P CLKOUT_PCIE1N CLKOUT_PCIE1P (+3V) CLK_PCIE_REQ2# DRAMRST_CNTRL_PCH PCIECLKRQ0# / GPIO73 AA48 AA47 Right_USB 17" A12 C8 (+3VS5) CLKOUT_PCIE0N CLKOUT_PCIE0P Touchscreen SMB_RUN_DAT [13,14] Q17 2N7002K SML1DATA / GPIO75 PEG_A_CLKRQ# / GPIO47 2.2K_4 SMB_ME1_DAT SML0CLK (+3VS5) PERN8 PERP8 PETN8 PETP8 Left_USB Bios swap GPIO A14 K20 B17 C16 L16 A16 D14 C14 (+3VS5) SML0ALERT# / GPIO60 (+3VS5) PERN7 PERP7 PETN7 PETP7 BE38 BC38 AW38 AY38 3/26 DB change from Port5 & Port6 to Port12 & Port13 for DF PCH. USBP8- [32] USBP8+ [32] USBP9- [32] USBP9+ [32] USBP10- [36] USBP10+ [36] USBP11- [32] USBP11+ [32] USBP5- [28] USBP5+ [28] USBP6- [32] USBP6+ [32] SMB_PCH_DAT (+3VS5) PERN6 PERP6 PETN6 PETP6 BG40 BJ40 AY40 BB40 2.2K_4 R270 2 SMB_PCH_DAT Q29 *2N7002 [32] [32] [32] [32] [32] [32] [32] [32] [25] [25] Q15 2N7002K [3,33,35,36,37] CLK_PEGA_REQ# USBP0USBP0+ USBP1USBP1+ USBP2USBP2+ USBP3USBP3+ USBP4USBP4+ B33 +3VS5 1 [14,30,35] MBDATA2 PEG Clock detect (SG only) 2 *74LVC1G126 2 PLTRST# PCH_CLK_27M_1 AT12 BF3 CLK_REQ/Strap Pin(CLG) R257 R212 100K_4 modify U49 SMB_ME1_CLK +3V 2 3 4/29 DGPU_PWROK [10,35,42,43,47] SMB_PCH_CLK C9 SML1ALERT# / PCHHOT# / GPIO74 PERN5 PERP5 PETN5 PETP5 AT8 C892 *.1U/10V_4 H14 SML1CLK / GPIO58 BJ38 BG38 AU36 AV36 +3V SMBCLK SML0DATA PERN4 PERP4 PETN4 PETP4 9/26: MV modify [8] [8] CLK_PCIE_REQ1# CLK_PCIE_REQ2# 2N7002K 1 1 U18 *TC7SH08FU NV_ALE NV_CLE SMBALERT# / GPIO11 SMBALERT# SMBDATA PERN3 PERP3 PETN3 PETP3 BG37 BH37 AY36 BB36 7/2 : Modify +3v NV_ALE NV_CLE CougarPoint_Rev_0p7 fcbga989-intel-cougarpoint AJ0QNJH0T03 IC CTRL(989P)PCH-HM65 QNJH FCBGA TOP B/S 5 *0.1U/10V_4 4 1 USBRBIAS# 5/13: add for leakage AV10 SMBus/Pull-up(CLG) C362 A (+3V) (+3V) (+3V) (+3V) PCIE_TXN2_LAN_C PCIE_TXP2_LAN_C PERN2 PERP2 PETN2 PETP2 BF36 BE36 AY34 BB34 PME# +3VS5 2 PCI_PLTRST# (+3V) (+3V) (+3V) 0.1U/10V_4 0.1U/10V_4 BE34 BF34 BB32 AY32 BG36 BJ36 AV34 AU34 22_4 CLK_PCI_FB_R CLK_PCI_LPC_R CLK_PCI_EC_R PLTRST#(CLG) PIRQA# PIRQB# PIRQC# PIRQD# USB [36] BT_COMBO_EN# DGPU_SELECT# EDID_SELECT# K40 K38 H38 G38 PCI PCI_PIRQA# PCI_PIRQB# PCI_PIRQC# PCI_PIRQD# 6/28: DB2 reserve R228 *0_4/S USBP0N USBP0P USBP1N USBP1P USBP2N USBP2P USBP3N USBP3P USBP4N USBP4P USBP5N USBP5P USBP6N USBP6P USBP7N USBP7P USBP8N USBP8P USBP9N USBP9P USBP10N USBP10P USBP11N USBP11P USBP12N USBP12P USBP13N USBP13P AV5 AY1 C418 C419 PCIE_TXN1_C PCIE_TXP1_C E12 2 DGPU_HOLD_RST# INTH# BT_COMBO_EN# DGPU_SELECT# LAN AU2 AT4 AT3 AT1 AY3 AT5 AV3 AV1 BB1 BA3 BB5 BB3 BB7 BE8 BD4 BF6 PCIE_RXN2_LAN PCIE_RXP2_LAN PCIE_TXN2_LAN PCIE_TXP2_LAN 0.1U/10V_4 0.1U/10V_4 (+3VS5) 1 1 2 3 4 5 [33] [33] [33] [33] C414 C410 PERN1 PERP1 PETN1 PETP1 Link EDID_SELECT# LCD_BK NV_DQ0 / NV_IO0 NV_DQ1 / NV_IO1 NV_DQ2 / NV_IO2 NV_DQ3 / NV_IO3 NV_DQ4 / NV_IO4 NV_DQ5 / NV_IO5 NV_DQ6 / NV_IO6 NV_DQ7 / NV_IO7 NV_DQ8 / NV_IO8 NV_DQ9 / NV_IO9 NV_DQ10 / NV_IO10 NV_DQ11 / NV_IO11 NV_DQ12 / NV_IO12 NV_DQ13 / NV_IO13 NV_DQ14 / NV_IO14 NV_DQ15 / NV_IO15 WLAN BG34 BJ34 AV32 AU32 Controller 10 9 8 7 6 MPC_PWR_CTRL# AT10 BC8 PCIE_RXN1 PCIE_RXP1 PCIE_TXN1 PCIE_TXP1 FLEX CLOCKS RP21 NV_DQS0 NV_DQS1 [36] [36] [36] [36] PCI-E* 3/26 DB change Part reference. +3V AY7 AV7 AU3 BG4 1 D TP1 TP2 TP3 TP4 TP5 TP6 TP7 TP8 TP9 TP10 TP11 TP12 TP13 TP14 TP15 TP16 TP17 TP18 TP19 TP20 NV_CE#0 NV_CE#1 NV_CE#2 NV_CE#3 5 8.2K_4 8.2K_4 8.2K_4 8.2K_4 NVRAM R310 R670 R296 R302 U44B RSVD +3V PCI_PIRQA# PCI_PIRQB# PCI_PIRQC# PCI_PIRQD# BG26 BJ26 BH25 BJ16 BG16 AH38 AH37 AK43 AK45 C18 N30 H3 AH12 AM4 AM5 Y13 K24 L24 AB46 AB45 2; Cougar Point-M (PCI-E,SMBUS,CLK) U44E PCI/USBOC# Pull-up(CLG) 1 1 Sheet 9 of 47 5 4 にイオわらェえへイゑィォえぐはへぱぷごまほほょぶにぼのごぺほまぬけ 5/23: stuff for bios *0_4/S S_GPIO R222 PCI_SERR# [35] SIO_EXT_SMI# 4/29 modify [35] SIO_EXT_SCI# [32,36] BT_OFF# [32] ACCLED_EN [8] ICC_EN# D R248 R580 [33] LAN_DISABLE# [36] Reserve R213 [9,35,42,43,47] T7 *0_4 *0_4 Bios swap GPIO 4/23. TACH1 / GPIO1 H36 TACH2 / GPIO6 BT_OFF# E38 TACH3 / GPIO7 ICC_EN# C10 *0_4/S 9/26: MV Modify R231 [35,42,43] DGPU_PWR_EN *0_4 C Bios swap GPIO [32] 4/23. DGT_RESET (+3V) TACH5 / GPIO69 (+3V) (+3V) TACH6 / GPIO70 (+3V) (+3V) TACH7 / GPIO71 (+3V) Clock Gen Power OK (CLG) 5/11 stuff R9144 LAN_PHY_PW R_CTRL / GPIO12 RF_OFF# G2 GPIO15 ODD_PRSNT#_R U2 (+3VS5) A20GATE (+3VS5) SATA4GP / GPIO16 (+3V) D40 TACH0 / GPIO17 (+3V) BIOS_REC T5 SCLOCK / GPIO22 BOARD_ID5 E8 GPIO24 / MEM_LED (+3V) R675 10K_4 +3V B41 GPIO69 R676 R680 1.5K/F_4 *1.5K/F_4 C41 GPIO70 +3V A40 GPIO71 GPIO28 BOARD_ID3 K1 STP_PCI# / GPIO34 BOARD_ID4 K4 D PECI RCIN# P4 P5 PROCPW RGD AY11 THRMTRIP# AY10 INIT3_3V# EC_RCIN# EC_RCIN# [35] H_PWRGOOD [3] PCH_THRMTRIP# R253 390_4 MFG-TEST PM_THRMTRIP# [3,35] T14 (+3VS5) (+3V) NC_1 AH8 NC_2 AK11 NC_3 AH10 NC_4 AK10 NC_5 P37 VSS_NCTF_15 BG2 VSS_NCTF_16 BG48 VSS_NCTF_17 BH3 VSS_NCTF_18 BH47 VSS_NCTF_19 BJ4 GPIO35 (+3V) V8 SATA2GP / GPIO36 M5 SATA3GP / GPIO37 MFG_MODE N2 (+3V) (+3V) R575 10K_4 R574 *0_4 R249 *0_4/S Bios swap GPIO 4/23. SLOAD / GPIO38 (+3V) DGPU_PRSNT# M3 SDATAOUT0 / GPIO39 TEST_SET_UP V13 SDATAOUT1 / GPIO48 (+3V) DGT_RESET V3 SATA5GP / GPIO49 SV_DET D6 GPIO57 +3V DG rev0.9 suggest to TS_VSS connect to GND 4/23. (+3V) (+3V) VSS_NCTF_1 VSS_NCTF_2 VSS_NCTF_20 BJ44 A45 VSS_NCTF_3 VSS_NCTF_21 BJ45 VSS_NCTF_22 BJ46 NCTF A44 VSS_NCTF_4 A BOARD_ID5 BOARD_ID4 BOARD_ID3 BOARD_ID2 VSS_NCTF_5 VSS_NCTF_23 BJ5 A6 VSS_NCTF_6 VSS_NCTF_24 BJ6 B3 VSS_NCTF_7 VSS_NCTF_25 C2 B47 VSS_NCTF_8 VSS_NCTF_26 C48 BD1 VSS_NCTF_9 VSS_NCTF_27 D1 BD49 VSS_NCTF_10 VSS_NCTF_28 D49 BE1 VSS_NCTF_11 VSS_NCTF_29 E1 BE49 VSS_NCTF_12 VSS_NCTF_30 E49 BF1 VSS_NCTF_13 VSS_NCTF_31 F1 BF49 VSS_NCTF_14 VSS_NCTF_32 F49 S_GPIO R305 R679 R308 R223 R224 R578 R673 R668 R214 R303 10K_4 10K_4 10K_4 10K_4 10K_4 10K_4 1.5K/F_4 1.5K/F_4 10K_4 10K_4 R221 R216 10K_4 *0_4 DGPU_PWROK GPIO27 R306 R267 *10K_4 10K_4 0 0 0 LX5 UMA 0 0 0 0 0 1 N Z N 5 Z "LX3 Capilano XT - SG 7 F LX5 Capilano K" XT F - SG U LX5 Capilano XT KE SG/Subwoofer U T LX5 DISCRETE E G Subwoofer T V G G V G 0 0 0 0 1 0 +3VS5 +3V RF_OFF# R598 1K_4 Intel ME Crypto Transport Layer Security (TLS) cipher suite BIOS_REC *0_4 BIOS RECOVERY Low = Disable (Default) High = Enable R207 10K_4 High = Disable (Default) Low = Enable +3V R234 *0_4 TEST_SET_UP R232 +3V 10K_4 R602 100K_4 SV_DET R601 SV_SET_UP TEST DETECT High = Strong (Default) Low = Default DGPU_PWR_EN_R [9] [9] [9] R611 R220 0 0 0 0 1 1 0 0 0 1 0 0 0 0 0 1 0 1 0 0 0 1 1 0 R255 R594 R567 R311 1 1 BOARD_ID0 BOARD_ID1 BOARD_ID2 RD0 RD1 RD2 RD3 RD4 RD5 BOARD_ID0 BOARD_ID1 BOARD_ID2 *10K_4 BOARD_ID0 R612 B *10K_4 *10K_4 BOARD_ID1 R226 10K_4 BOARD_ID2 R254 10K_4 BOARD_ID3 R592 10K_4 BOARD_ID4 R566 10K_4 BOARD_ID5 R301 RU1 RU2 RU3 RU4 RU5 10K_4 +3V 200K/F_4 R218 Low = Tx, Rx terminated to same voltage (DC Coupling Mode) (DEFAULT) DMI TERMINATION VOLTAGE OVERRIDE RU0 R230 100K_4 FDI TERMINATION VOLTAGE OVERRIDE FDI_OVRVLTG R217 +3VS5 10K_4 *10K_4 Rb R581 +3V *100K_4 DGPU_PRSNT# *10K_4 *10K_4 A GFX Present *10K_4 +3VS5 4/29 modify 4 *1K_4 LOW - Tx, Rx terminated to same voltage +3V Ra R582 SG UMA Stuff Ra Rb NC Rb Ra 10K_4 RTQLGEV"<"NZ517*Jwtqp"Tkxgt+ Swcpvc"Eqorwvgt"Kpe0 PD7 Size Custom Document Number 3 2 Rev 1A PCH 4/6 (GPIO/MISC) Date: Wednesday, October 13, 2010 5 C 4/29 modify BOARD_ID0 0 1 SIO_EXT_SCI# SIO_EXT_SMI# BT_OFF# EC_A20GATE EC_RCIN# DGT_RESET GPIO70 GPIO71 ODD_PRSNT#_R DGPU_PWROK +3V BOARD_ID1 0 0 10K_4 10K_4 CougarPoint_Rev_0p7 IC CTRL(989P)PCH-HM65 QNJH FCBGA TOP B/S fcbga989-intel-cougarpoint AJ0QNJH0T03 0 0 R579 R251 R206 A5 LX3 UMA 0 LAN_DISABLE#_R ACCLED_EN +3V BOARD ID SETTING Model GPIO Pull-up/Pull-down(CLG) +3V MFG_MODE FDI_OVRVLTG [3,7,8,9,11,45] [3,7,8,9,11,13,14,18,19,25,26,27,28,29,30,31,32,33,34,35,36,37,39,40,41,43,45,46,47] EC_A20GATE [35] AU16 (DSW) DGPU_PWR_EN_R A46 3/26 DB del external clock generator. +3VS5 GPIO27 P8 B GPIO68 (+3VS5) E16 PLL_ODVR_EN_R A4 C40 (+3VS5) C4 (+3VS5) +3VS5 +3V 32 1 (+3V) GPIO8 LAN_DISABLE#_R GPIO27 R613 [8] PLL_ODVR_EN TACH4 / GPIO68 (+3V) A42 SIO_EXT_SCI# DGPU_PWROK DGPU_PWROK BMBUSY# / GPIO0 SIO_EXT_SMI# *0_4/S RF_OFF# [34] ODD_PRSNT# 2 U44F CPU/MISC [35] 4/23. GPIO Bios swap GPIO 3 1 Sheet 10 of 47 4 3 2 Cougar Point-M (POWER) +1.05V_VCCUSBCORE U44J 5/12: modify PCH_VCCDSW C389 0.1U/10V_4 V12 DCPSUSBYP *0.1U/10V_4 C786 *1U/6.3V_4 +1.05V AA19 R293 *0_6/S +1.05V_VCCEPW 1.01A (60mils) C395 1U/6.3V_4 C402 1U/6.3V_4 VCCASW [2] AA24 VCCASW [3] AA26 VCCASW [4] AA27 VCCASW [5] AA31 6/9: DB2 modify AC26 7/1: SI DEL C408 22U/6.3VS_8 C409 22U/6.3VS_8 R604 +1.05V VCCASW [10] AC31 VCCASW [11] VCCASW [13] W 21 VCCASW [14] W 23 VCCASW [15] W 24 VCCASW [16] +VCCAFDI_VRM +1.05V_VCCA_A_DPL C840 1U/6.3V_4 R685 *0_6/S +VCCDIFFCLK +VCCDIFFCLKN 55mA (10mils) +V1.05V_SSCVCC *0_6 +VCCSST C383 0.1U/10V_4 +V1.05M_VCCSUS R273 V_PROC_IO=1mA (10mils) A C778 0.1U/10V_4 A22 C808 1U/6.3V_4 C807 0.1U/10V_4 C806 0.1U/10V_4 VCCSUS3_3[9] V23 VCCSUS3_3[10] V24 +3V_VCCPUSB *0_6/S C391 10U/6.3VS_6 VCCSUS3_3[6] P24 +3V_VCCAUBG VCCIO[34] T26 +VCCAUPLL R287 V5REF_SUS M26 +VCCA_USBSUS AN24 +3V_VCCPSUS +1.05V +1.05V_VCCAPLL_EXP L48 AN19 C791 *10U/6.3V_6 VCCIO[28] 119mA (15mils) +3V_VCCPSUS R272 *0_6/S +3VS5 P22 C393 1U/6.3V_4 VCC3_3[1] AA16 VCC3_3[8] W 16 VCC3_3[4] T34 +1.05V_VCCIO C412 1U/6.3V_4 266mA (20mils) +3V_VCCPCORE +3V R210 *0_6/S C416 10U/6.3VS_6 +3V C360 0.1U/10V_4 AJ2 C411 1U/6.3V_4 6/9: DB2 modify 7/1: SI DEL C398 1U/6.3V_4 +3V C404 1U/6.3V_4 +3V_VCC_EXP AH13 VCCIO[13] AH14 VCCIO[6] AF14 +V1.05S_SATA3 C799 0.1U/10V_4 R241 *0_8/S +1.05V C374 1U/6.3V_4 AK1 +V1.1LAN_VCCAPLL AF11 +VCCAFDI_VRM +VCCAFDI_VRM (Mobile 1.5V) +1.5V R708 *0_6/S +1.05V R709 *0_6 L45 *10uH/100mA_8 +1.05V +1.05V C772 *10U/6.3V_6 AN16 VCCIO[15] AC17 VCCIO[4] AD17 +1.05V_VCCIO1 R225 AN17 VCCIO[16] AN21 VCCIO[17] AN26 VCCIO[18] AN27 VCCIO[19] AP21 VCCIO[20] AP23 VCCIO[21] AP24 VCCIO[22] AP26 VCCIO[23] AT24 VCCIO[24] AN33 VCCIO[25] AN34 VCCIO[26] BH29 VCC3_3[3] +VCCAFDI_VRM AP16 VCCVRM[2] R588 *0_8 R259 *0_8/S BG6 VccAFDIPLL AP17 *0_6/S +1.05V +1.05V_VCCEPW VCCASW [21] T19 VCCSUSHDA CougarPoint_Rev_0p7 fcbga989-intel-cougarpoint AJ0QNJH0T03 IC CTRL(989P)PCH-HM65 QNJH FCBGA TOP B/S AK36 VSSALVDS AK37 *0_6 8/17: PV modify +3V *0_4 Rb R667 0_4 +VCC_TX_LVDS Ra L51 *0.1uH/250mA_8 VCCTX_LVDS[1] AM37 VCCTX_LVDS[2] AM38 VCCTX_LVDS[3] AP36 R693 0_4 AP37 C832 *22U/6.3VS_8 C836 *0.01U/25V_4 C826 *0.01U/25V_4 Rb +1.05V 65mA (10mils) +1.05V_VCCA_B_DPL L50 10uH/100MA_8 +V3.3A_1.5A_HDA_IO V34 C813 0.1U/10V_4 42mA (10mils) VCCVRM[3] AT16 VCCDMI[1] AT20 VCCCLKDMI AB36 R652 *0_4 R651 *0_4/S +1.5VSUS +3V +3VS5 C800 *1U/6.3V_4 *0_6 +3V_SUS_CLKF33 R720 1/F_4 +3V_SUS_CLKF33_R +1.05V +VCC_DMI_CCI R724 *1/F_4 R730 *0_4/S 4 3 *0_4/S C390 1U/6.3V_4 C870 *10U/6.3V_6 VCCPNAND[1] AG16 VCCPNAND[2] AG17 R237 VCCPNAND[3] AJ16 C385 0.1U/10V_4 VCCPNAND[4] AJ17 +VCCP_NAND +1.8V *0_8/S B 20mA (10mils) +3V_VCCME_SPI +3V R571 V1 *0_6/S VCCDMI[2] C774 1U/6.3V_4 R295 C818 10_4 +5V 1U/6.3V_4 D5 C407 1U/6.3V_4 V5REF= 1mA *220U/2.5V_3528 RB500V-40 +3V 1U/6.3V_4 *220U/2.5V_3528 +5V_PCH_VCC5REFSUS VCC5REFSUS=1mA C852 1U/6.3V_4 C853 10U/6.3VS_6 L55 10uH/100mA_8 +3V_RTC [7,8] +3V_DSW [7,8] +3VS5 [3,7,8,9,10,45] +3V [3,7,8,9,10,13,14,18,19,25,26,27,28,29,30,31,32,33,34,35,36,37,39,40,41,43,45,46,47] +5VS5 [45] +5V [7,8,19,25,26,27,29,30,32,34,36,37,45] +1.05V_VTT R277 190 mA (15mils) 5/14 modify 20mA (10mils) R714 +1.1V_VCC_DMI +VCCAFDI_VRM +1.1V_VCC_DMI_CCI VCCSPI C831 C824 C798 0.1U/10V_4 VCC3_3[7] C *0_6/S PD7 2 10_4 +5VS5 RB500V-40 +3VS5 A RTQLGEV"<"NZ517*Jwtqp"Tkxgt+ Swcpvc"Eqorwvgt"Kpe0 +1.1V_VCC_DMI_CCI L54 *10uH/100mA_8 R291 D4 C405 0.1U/10V_4 Size Custom Document Number Rev 1A PCH 5/6 (POWER) Date: Wednesday, October 13, 2010 5 +1.8V +3V R669 8mA (10mils) 10mA (10mils) P32 V33 +5V_PCH_VCC5REF +1.05V_VCCA_A_DPL L53 10uH/100MA_8 VCC3_3[6] 20mA (10mils) +1.05V [7,8,9,34,35,41] +1.05V_VTT [3,5,39,40] +1.5VSUS [3,5,13,14,43,45] +1.8V [5,8,39,45] R703 R665 CougarPoint_Rev_0p7 fcbga989-intel-cougarpoint AJ0QNJH0T03 IC CTRL(989P)PCH-HM65 QNJH FCBGA TOP B/S C867 V21 VCCALVDS C855 1U/6.3V_4 VCCIO[27] AU20 +1.05V_VTT C384 1U/6.3V_4 T21 VCCASW [23] 0.01U/25V_4 +3V_VCC_GIO +1.05V_VCCDPLL_FDI AC16 VCCIO[3] VCCASW [22] 0.1U/10V_4 C844 D SG & UMA : Ra DIS : Rb +1.05V_VCCAPLL_FDI DCPSUS[1] DCPSUS[2] 10U/6.3VS_6 C837 +VCCALVDS 160mA (15mils) AF13 DCPSST C846 1mA (10mils) VCCAPLLEXP *0_8/S +3V C406 0.1U/10V_4 VCCIO[2] U47 VCCTX_LVDS[4] BJ22 N20 P20 VCCVRM[1] VSSADAC HCB1608KF-181T15/1.5A_6 Ra *1U/6.3V_4 +1.05V N22 VCCAPLLSATA U48 *0_6/S +1.05V C392 VCCADAC +5V_PCH_VCC5REF P34 VCCSUS3_3[4] VCCSUS3_3[5] +3V 60mA (10mils) R646 VCCADPLLB VCCRTC *0_6/S +1.05V_PCH_VCCDPLL_EXP R283 VCCCORE[1] VCCCORE[2] VCCCORE[3] VCCCORE[4] VCCCORE[5] VCCCORE[6] VCCCORE[7] VCCCORE[8] VCCCORE[9] VCCCORE[10] VCCCORE[11] VCCCORE[12] VCCCORE[13] VCCCORE[14] VCCCORE[15] VCCCORE[16] VCCCORE[17] *1uH/25mA_6 VCCSUS3_3[3] VCCIO[12] V_PROC_IO +1.05V +5V_PCH_VCC5REFSUS AN23 C399 1U/6.3V_4 AA23 AC23 AD21 AD23 AF21 AF23 AG21 AG23 AG24 AG26 AG27 AG29 AJ23 AJ26 AJ27 AJ29 AJ31 2.925 A (140mils) VCCSUS3_3[2] VCC3_3[2] VCCADPLLA C394 1U/6.3V_4 *0_6/S C403 0.1U/10V_4 V5REF C400 1U/6.3V_4 6/9: DB2 modify C396 0.1U/10V_4 R279 1.01A (60mils) C781 0.1U/10V_4 +3V_RTC VCCRTC<1mA (10mils) T24 VCCVRM[4] VCCSSC BJ8 C785 4.7U/6.3V_6 R280 C775 0.1U/10V_4 +VTT_VCCPCPU *0_4/S T23 VCCSUS3_3[8] VCCIO[5] AG33 T17 V19 119mA (20mils) 7/1: SI DEL VCCSUS3_3[7] VCCSUS3_3[1] DCPRTC VCCIO[7] VCCDIFFCLKN[1] VCCDIFFCLKN[2] VCCDIFFCLKN[3] V16 C828 1U/6.3V_4 +3VS5 VCCASW [20] AF17 AF33 AF34 AG34 95mA (10mils) C387 *1U/6.3V_4 +1.05V_VTT BF47 8mA (10mils) C833 1U/6.3V_4 R278 BD47 65mA (10mils) +1.05V_VCCA_B_DPL +1.05V VCCASW [19] 160mA (20mils) B +1.05V VCCASW [18] W 31 Y49 VCCIO[33] T29 +VCCA_DAC_1_2 L52 VCCASW [17] W 29 +VCCRTCEXT N16 C380 0.1U/10V_4 *0_6/S VCCASW [12] AD31 W 33 R699 VCCASW [8] VCCASW [9] *0_6/S C777 1U/6.3V_4 VCCASW [7] AC29 W 26 +1.05V VCCASW [6] AC27 AD29 T27 DCPSUS[4] CPU C VCCIO[32] VCCASW [1] AA21 AA29 C401 1U/6.3V_4 DCPSUS[3] RTC +1.05V USB AL24 C795 *10U/6.3V_6 VCCIO[14] PCI/GPIO/LPC +VCCSUS1 *10uH/100mA_8 AL29 P28 VCCAPLLDMI2 SATA +VCCDPLL_CPY L49 BH23 MISC 4/29: modify +VCCAPLL_CPY_PCH HDA 8/6: PV modify +1.05V P26 VCCIO[31] VCC3_3[5] Clock and Miscellaneous +3V_SUS_CLKF33 T38 VCCIO[30] VCCDSW 3_3 1mA (10mils) U44G CRT C377 D T16 +1.05V_PCH_VCC LVDS +VCCPDSW 3mA (10mils) 33 COUGAR POINT (POWER) 1.3 A (60mils) +1.05V *0_8/S HVCMOS *0_4 VCCIO[29] R684 DMI R281 +3V_DSW VCCACLK N26 NAND / SPI *0_4/S AD49 VCC CORE R274 +VCCACLK VCCIO +3VS5 +1.05V *0_8 + R695 + +1.05V 1 FDI 5 1 Sheet 11 of 47 5 4 3 IBEX PEAK-M (GND) 2 34 1 IBEX PEAK-M (GND) U44I U44H AY4 AY42 AY46 AY8 B11 B15 B19 B23 B27 B31 B35 B39 B7 F45 BB12 BB16 BB20 BB22 BB24 BB28 BB30 BB38 BB4 BB46 BC14 BC18 BC2 BC22 BC26 BC32 BC34 BC36 BC40 BC42 BC48 BD46 BD5 BE22 BE26 BE40 BF10 BF12 BF16 BF20 BF22 BF24 BF26 BF28 BD3 BF30 BF38 BF40 BF8 BG17 BG21 BG33 BG44 BG8 BH11 BH15 BH17 BH19 H10 BH27 BH31 BH33 BH35 BH39 BH43 BH7 D3 D12 D16 D18 D22 D24 D26 D30 D32 D34 D38 D42 D8 E18 E26 G18 G20 G26 G28 G36 G48 H12 H18 H22 H24 H26 H30 H32 H34 F3 D C B A VSS[159] VSS[160] VSS[161] VSS[162] VSS[163] VSS[164] VSS[165] VSS[166] VSS[167] VSS[168] VSS[169] VSS[170] VSS[171] VSS[172] VSS[173] VSS[174] VSS[175] VSS[176] VSS[177] VSS[178] VSS[179] VSS[180] VSS[181] VSS[182] VSS[183] VSS[184] VSS[185] VSS[186] VSS[187] VSS[188] VSS[189] VSS[190] VSS[191] VSS[192] VSS[193] VSS[194] VSS[195] VSS[196] VSS[197] VSS[198] VSS[199] VSS[200] VSS[201] VSS[202] VSS[203] VSS[204] VSS[205] VSS[206] VSS[207] VSS[208] VSS[209] VSS[210] VSS[211] VSS[212] VSS[213] VSS[214] VSS[215] VSS[216] VSS[217] VSS[218] VSS[219] VSS[220] VSS[221] VSS[222] VSS[223] VSS[224] VSS[225] VSS[226] VSS[227] VSS[228] VSS[229] VSS[230] VSS[231] VSS[232] VSS[233] VSS[234] VSS[235] VSS[236] VSS[237] VSS[238] VSS[239] VSS[240] VSS[241] VSS[242] VSS[243] VSS[244] VSS[245] VSS[246] VSS[247] VSS[248] VSS[249] VSS[250] VSS[251] VSS[252] VSS[253] VSS[254] VSS[255] VSS[256] VSS[257] VSS[258] VSS[259] VSS[260] VSS[261] VSS[262] VSS[263] VSS[264] VSS[265] VSS[266] VSS[267] VSS[268] VSS[269] VSS[270] VSS[271] VSS[272] VSS[273] VSS[274] VSS[275] VSS[276] VSS[277] VSS[278] VSS[279] VSS[280] VSS[281] VSS[282] VSS[283] VSS[284] VSS[285] VSS[286] VSS[287] VSS[288] VSS[289] VSS[290] VSS[291] VSS[292] VSS[293] VSS[294] VSS[295] VSS[296] VSS[297] VSS[298] VSS[299] VSS[300] VSS[301] VSS[302] VSS[303] VSS[304] VSS[305] VSS[306] VSS[307] VSS[308] VSS[309] VSS[310] VSS[311] VSS[312] VSS[313] VSS[314] VSS[315] VSS[316] VSS[317] VSS[318] VSS[319] VSS[320] VSS[321] VSS[322] VSS[323] VSS[324] VSS[325] VSS[328] VSS[329] VSS[330] VSS[331] VSS[333] VSS[334] VSS[335] VSS[337] VSS[338] VSS[340] VSS[342] VSS[343] VSS[344] VSS[345] VSS[346] VSS[347] VSS[348] VSS[349] VSS[350] VSS[351] VSS[352] H46 K18 K26 K39 K46 K7 L18 L2 L20 L26 L28 L36 L48 M12 P16 M18 M22 M24 M30 M32 M34 M38 M4 M42 M46 M8 N18 P30 N47 P11 P18 T33 P40 P43 P47 P7 R2 R48 T12 T31 T37 T4 W 34 T46 T47 T8 V11 V17 V26 V27 V29 V31 V36 V39 V43 V7 W 17 W 19 W2 W 27 W 48 Y12 Y38 Y4 Y42 Y46 Y8 BG29 N24 AJ3 AD47 B43 BE10 BG41 G14 H16 T36 BG22 BG24 C22 AP13 M14 AP3 AP1 BE16 BC16 BG28 BJ28 H5 AA17 AA2 AA3 AA33 AA34 AB11 AB14 AB39 AB4 AB43 AB5 AB7 AC19 AC2 AC21 AC24 AC33 AC34 AC48 AD10 AD11 AD12 AD13 AD19 AD24 AD26 AD27 AD33 AD34 AD36 AD37 AD38 AD39 AD4 AD40 AD42 AD43 AD45 AD46 AD8 AE2 AE3 AF10 AF12 AD14 AD16 AF16 AF19 AF24 AF26 AF27 AF29 AF31 AF38 AF4 AF42 AF46 AF5 AF7 AF8 AG19 AG2 AG31 AG48 AH11 AH3 AH36 AH39 AH40 AH42 AH46 AH7 AJ19 AJ21 AJ24 AJ33 AJ34 AK12 AK3 VSS[0] VSS[1] VSS[2] VSS[3] VSS[4] VSS[5] VSS[6] VSS[7] VSS[8] VSS[9] VSS[10] VSS[11] VSS[12] VSS[13] VSS[14] VSS[15] VSS[16] VSS[17] VSS[18] VSS[19] VSS[20] VSS[21] VSS[22] VSS[23] VSS[24] VSS[25] VSS[26] VSS[27] VSS[28] VSS[29] VSS[30] VSS[31] VSS[32] VSS[33] VSS[34] VSS[35] VSS[36] VSS[37] VSS[38] VSS[39] VSS[40] VSS[41] VSS[42] VSS[43] VSS[44] VSS[45] VSS[46] VSS[47] VSS[48] VSS[49] VSS[50] VSS[51] VSS[52] VSS[53] VSS[54] VSS[55] VSS[56] VSS[57] VSS[58] VSS[59] VSS[60] VSS[61] VSS[62] VSS[63] VSS[64] VSS[65] VSS[66] VSS[67] VSS[68] VSS[69] VSS[70] VSS[71] VSS[72] VSS[73] VSS[74] VSS[75] VSS[76] VSS[77] VSS[78] VSS[79] VSS[80] VSS[81] VSS[82] VSS[83] VSS[84] VSS[85] VSS[86] VSS[87] VSS[88] VSS[89] VSS[90] VSS[91] VSS[92] VSS[93] VSS[94] VSS[95] VSS[96] VSS[97] VSS[98] VSS[99] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106] VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158] AK38 AK4 AK42 AK46 AK8 AL16 AL17 AL19 AL2 AL21 AL23 AL26 AL27 AL31 AL33 AL34 AL48 AM11 AM14 AM36 AM39 AM43 AM45 AM46 AM7 AN2 AN29 AN3 AN31 AP12 AP19 AP28 AP30 AP32 AP38 AP4 AP42 AP46 AP8 AR2 AR48 AT11 AT13 AT18 AT22 AT26 AT28 AT30 AT32 AT34 AT39 AT42 AT46 AT7 AU24 AU30 AV16 AV20 AV24 AV30 AV38 AV4 AV43 AV8 AW 14 AW 18 AW 2 AW 22 AW 26 AW 28 AW 32 AW 34 AW 36 AW 40 AW 48 AV11 AY12 AY22 AY28 D C B CougarPoint_Rev_0p7 A RTQLGEV"<"NZ517*Jwtqp"Tkxgt+ Swcpvc"Eqorwvgt"Kpe0 CougarPoint_Rev_0p7 PD7 Size Custom Document Number Date: Wednesday, October 13, 2010 5 4 3 2 Rev 1A PCH 6/6 (GND) 1 Sheet 12 of 47 4 D R153 R152 10K_4 10K_4 [4] [4] [4] [4] [4] [4] [4] [4] [4] [4] [4] [4] [4] [4] M_A_BS#0 M_A_BS#1 M_A_BS#2 M_A_CS#0 M_A_CS#1 M_A_CLKP0 M_A_CLKN0 M_A_CLKP1 M_A_CLKN1 M_A_CKE0 M_A_CKE1 M_A_CAS# M_A_RAS# M_A_WE# [9,14] SMB_RUN_CLK [9,14] SMB_RUN_DAT [4] [4] 98 97 96 95 92 91 90 86 89 85 107 84 83 119 80 78 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC# A13 A14 A15 DIMM0_SA0 DIMM0_SA1 SMB_RUN_CLK SMB_RUN_DAT 109 108 79 114 121 101 103 102 104 73 74 115 110 113 197 201 202 200 BA0 BA1 BA2 S0# S1# CK0 CK0# CK1 CK1# CKE0 CKE1 CAS# RAS# W E# SA0 SA1 SCL SDA 116 120 ODT0 ODT1 11 28 46 63 136 153 170 187 DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7 12 29 47 64 137 154 171 188 10 27 45 62 135 152 169 186 DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 DQS#0 DQS#1 DQS#2 DQS#3 DQS#4 DQS#5 DQS#6 DQS#7 M_A_ODT0 M_A_ODT1 M_A_DM1 C M_A_DM2 [4] M_A_DQSP[7:0] [4] M_A_DQSN[7:0] M_A_DQSP0 M_A_DQSP1 M_A_DQSP2 M_A_DQSP3 M_A_DQSP4 M_A_DQSP5 M_A_DQSP6 M_A_DQSP7 M_A_DQSN0 M_A_DQSN1 M_A_DQSN2 M_A_DQSN3 M_A_DQSN4 M_A_DQSN5 M_A_DQSN6 M_A_DQSN7 2 M_A_DQ[63:0] [4] JDIM1A M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14 M_A_A15 PC2100 DDR3 SDRAM SO-DIMM (204P) [4] M_A_A[15:0] 3 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 5 7 15 17 4 6 16 18 21 23 33 35 22 24 34 36 39 41 51 53 40 42 50 52 57 59 67 69 56 58 68 70 129 131 141 143 130 132 140 142 147 149 157 159 146 148 158 160 163 165 175 177 164 166 174 176 181 183 191 193 180 182 192 194 M_A_DQ4 M_A_DQ5 M_A_DQ7 M_A_DQ6 M_A_DQ1 M_A_DQ0 M_A_DQ3 M_A_DQ2 M_A_DQ9 M_A_DQ8 M_A_DQ15 M_A_DQ10 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ11 M_A_DQ21 M_A_DQ16 M_A_DQ19 M_A_DQ18 M_A_DQ20 M_A_DQ17 M_A_DQ23 M_A_DQ22 M_A_DQ25 M_A_DQ24 M_A_DQ30 M_A_DQ26 M_A_DQ28 M_A_DQ29 M_A_DQ31 M_A_DQ27 M_A_DQ36 M_A_DQ37 M_A_DQ34 M_A_DQ38 M_A_DQ32 M_A_DQ33 M_A_DQ35 M_A_DQ39 M_A_DQ41 M_A_DQ45 M_A_DQ47 M_A_DQ46 M_A_DQ40 M_A_DQ44 M_A_DQ42 M_A_DQ43 M_A_DQ49 M_A_DQ48 M_A_DQ54 M_A_DQ55 M_A_DQ53 M_A_DQ52 M_A_DQ50 M_A_DQ51 M_A_DQ61 M_A_DQ60 M_A_DQ62 M_A_DQ63 M_A_DQ56 M_A_DQ57 M_A_DQ59 M_A_DQ58 2.48A +1.5VSUS JDIM1B 75 76 81 82 87 88 93 94 99 100 105 106 111 112 117 118 123 124 VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8 VDD9 VDD10 VDD11 VDD12 VDD13 VDD14 VDD15 VDD16 VDD17 VDD18 199 VDDSPD 77 122 125 NC1 NC2 NCTEST PM_EXTTS#0 198 30 EVENT# RESET# +SMDDR_VREF_DQ0 +SMDDR_VREF_DIMM 1 126 VREF_DQ VREF_CA +3V +3V [14] PM_EXTTS#0 [3,14] DDR3_DRAMRST# [6] SMDDR_VREF_DQ0_M3 SMDDR_VREF_DQ0_M1 R27 0_6 SMDDR_VREF_DQ0_M3 R17 *0_6 R133 10K_4 2 3 8 9 13 14 19 20 25 26 31 32 37 38 43 6/28: SI add for RF +1.5VSUS +1.5V C893 2.2U/6.3V_6 C894 2.2U/6.3V_6 C895 2.2U/6.3V_6 C896 2.2U/6.3V_6 35 1 VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 PC2100 DDR3 SDRAM SO-DIMM (204P) 5 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 44 48 49 54 55 60 61 65 66 71 72 127 128 133 134 138 139 144 145 150 151 155 156 161 162 167 168 172 173 178 179 184 185 189 190 195 196 D C VTT1 VTT2 203 204 GND GND 205 206 +0.75V_DDR_VTT DDR3-DIMM0_H=5.2_RVS DDR-78279-001-RVS-204P DGMK4000125 IC SOCKET DDRIII SO-DIMM(204P,H5.2,RVS) +0.75V_DDR_VTT [14,43,45] +1.5VSUS [3,5,11,14,43,45] +3VPCU [7,8,25,32,34,35,36,37,38,39,40,42,44,45,47] +3V [3,7,8,9,10,11,14,18,19,25,26,27,28,29,30,31,32,33,34,35,36,37,39,40,41,43,45,46,47] +5VPCU [32,35,38,39,40,41,42,43,44,45] DDR3-DIMM0_H=5.2_RVS DDR-78279-001-RVS-204P DGMK4000125 IC SOCKET DDRIII SO-DIMM(204P,H5.2,RVS) B B VREF DQ0 M2 Solution Place these Caps near So-Dimm0. +1.5VSUS 6/23 : Del M2 solution A VREF DQ0 M1 Solution +1.5VSUS +0.75V_DDR_VTT C88 1U/6.3V_4 C645 1U/6.3V_4 C93 1U/6.3V_4 C639 1U/6.3V_4 C72 1U/6.3V_4 C634 1U/6.3V_4 C56 1U/6.3V_4 C628 1U/6.3V_4 C98 10U/6.3VS_6 C622 10U/6.3V_6 C61 10U/6.3VS_6 C657 *10U/6.3V_6 C46 10U/6.3VS_6 C52 10U/6.3VS_6 C83 10U/6.3VS_6 C65 10U/6.3VS_6 C47 *10U/6.3V_6 C40 10U/6.3V_8 C38 10U/6.3V_8 R31 1K/F_4 DDR_VTTREF R112 *0_6 +1.5VSUS SMDDR_VREF_DQ0_M1 R97 10K_4 R106 1K/F_4 +SMDDR_VREF_DIMM [5,14,43] C186 0.1U/10V_4 C136 2.2U/6.3V_6 4/27: layout modify 5/23: na 5 4 *0_6 +SMDDR_VREF_DIMM R95 10K_4 C157 470P/50V_4 +SMDDR_VREF_DQ0 A C21 0.1U/10V_4 C26 2.2U/6.3V_6 C198 0.1U/10V_4 C258 2.2U/6.3V_6 RTQLGEV"<"NZ517*Jwtqp"Tkxgt+ Swcpvc"Eqorwvgt"Kpe0 +3V 4/29: reserve M2 solution R125 DDR_VTTREF PD7 6/28: SI del C717 3 Size Custom Document Number Date: Wednesday, October 13, 2010 2 Rev 1A DDR3 DIMM0-RVS (5.2H) 1 Sheet 13 of 47 4 10K_4 10K_4 M_B_BS#0 M_B_BS#1 M_B_BS#2 M_B_CS#0 M_B_CS#1 M_B_CLKP0 M_B_CLKN0 M_B_CLKP1 M_B_CLKN1 M_B_CKE0 M_B_CKE1 M_B_CAS# M_B_RAS# M_B_WE# 109 108 79 114 121 101 103 102 104 73 74 115 110 113 197 201 202 200 BA0 BA1 BA2 S0# S1# CK0 CK0# CK1 CK1# CKE0 CKE1 CAS# RAS# W E# SA0 SA1 SCL SDA 116 120 ODT0 ODT1 M_B_DM2 11 28 46 63 136 153 170 187 DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7 M_B_DQSP0 M_B_DQSP1 M_B_DQSP2 M_B_DQSP3 M_B_DQSP4 M_B_DQSP5 M_B_DQSP6 M_B_DQSP7 M_B_DQSN0 M_B_DQSN1 M_B_DQSN2 M_B_DQSN3 M_B_DQSN4 M_B_DQSN5 M_B_DQSN6 M_B_DQSN7 12 29 47 64 137 154 171 188 10 27 45 62 135 152 169 186 DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 DQS#0 DQS#1 DQS#2 DQS#3 DQS#4 DQS#5 DQS#6 DQS#7 DIMM1_SA0 DIMM1_SA1 [9,13] SMB_RUN_CLK [9,13] SMB_RUN_DAT [4] [4] M_B_ODT0 M_B_ODT1 C M_B_DM1 [4] M_B_DQSP[7:0] [4] M_B_DQSN[7:0] B DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 5 7 15 17 4 6 16 18 21 23 33 35 22 24 34 36 39 41 51 53 40 42 50 52 57 59 67 69 56 58 68 70 129 131 141 143 130 132 140 142 147 149 157 159 146 148 158 160 163 165 175 177 164 166 174 176 181 183 191 193 180 182 192 194 M_B_DQ5 M_B_DQ4 M_B_DQ3 M_B_DQ2 M_B_DQ0 M_B_DQ1 M_B_DQ6 M_B_DQ7 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ10 M_B_DQ8 M_B_DQ9 M_B_DQ11 M_B_DQ15 M_B_DQ20 M_B_DQ21 M_B_DQ18 M_B_DQ22 M_B_DQ17 M_B_DQ16 M_B_DQ19 M_B_DQ23 M_B_DQ25 M_B_DQ29 M_B_DQ27 M_B_DQ26 M_B_DQ28 M_B_DQ24 M_B_DQ31 M_B_DQ30 M_B_DQ36 M_B_DQ37 M_B_DQ35 M_B_DQ34 M_B_DQ33 M_B_DQ32 M_B_DQ39 M_B_DQ38 M_B_DQ44 M_B_DQ40 M_B_DQ42 M_B_DQ43 M_B_DQ45 M_B_DQ41 M_B_DQ46 M_B_DQ47 M_B_DQ49 M_B_DQ48 M_B_DQ54 M_B_DQ55 M_B_DQ52 M_B_DQ53 M_B_DQ50 M_B_DQ51 M_B_DQ61 M_B_DQ56 M_B_DQ62 M_B_DQ63 M_B_DQ57 M_B_DQ60 M_B_DQ59 M_B_DQ58 36 +1.5VSUS JDIM2B 2.48A 75 76 81 82 87 88 93 94 99 100 105 106 111 112 117 118 123 124 VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8 VDD9 VDD10 VDD11 VDD12 VDD13 VDD14 VDD15 VDD16 VDD17 VDD18 +3V 199 VDDSPD 77 122 125 NC1 NC2 NCTEST PM_EXTTS#0 198 30 EVENT# RESET# +SMDDR_VREF_DQ1 1 126 VREF_DQ VREF_CA R511 +3V 10K_4 [3,13] DDR3_DRAMRST# [6] SMDDR_VREF_DQ1_M3 SMDDR_VREF_DQ1_M1 R483 0_6 SMDDR_VREF_DQ1_M3 R71 *0_6 +SMDDR_VREF_DIMM 2 3 8 9 13 14 19 20 25 26 31 32 37 38 43 VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 44 48 49 54 55 60 61 65 66 71 72 127 128 133 134 138 139 144 145 150 151 155 156 161 162 167 168 172 173 178 179 184 185 189 190 195 196 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 D C VTT1 VTT2 203 204 GND GND 205 206 +0.75V_DDR_VTT DDR3-DIMM1_H=9.2_RVS DDR-AS0A626-UARN-7F-204P DGMK4000126 IC SOCKET DDRIII SO-DIMM(204P,H9.2,RVS) DDR3 Thermal Sensor U11 [9,30,35] MBCLK2 DDR3-DIMM1_H=9.2_RVS DDR-AS0A626-UARN-7F-204P DGMK4000126 IC SOCKET DDRIII SO-DIMM(204P,H9.2,RVS) [9,30,35] MBDATA2 [13] PM_EXTTS#0 +0.75V_DDR_VTT [13,43,45] +1.5VSUS [3,5,11,13,43,45] +3VPCU [7,8,25,32,34,35,36,37,38,39,40,42,44,45,47] +3V [3,7,8,9,10,11,13,18,19,25,26,27,28,29,30,31,32,33,34,35,36,37,39,40,41,43,45,46,47] +5VPCU [32,35,38,39,40,41,42,43,44,45] C261 MBCLK2 8 SCLK VCC 1 MBDATA2 7 SDA DXP 2 PM_EXTTS#0 6 ALERT# DXN 3 PM_EXTTS#0_EC 4 OVERT# GND 5 0.01U/25V_4 +3V DDR_THERMDA 3 +3V R154 R512 [4] [4] [4] [4] [4] [4] [4] [4] [4] [4] [4] [4] [4] [4] A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC# A13 A14 A15 1 C206 2200P/50V_4 DDR_THERMDC R134 +3V VREF DQ1 M2 Solution Place these Caps near So-Dimm1. +0.75V_DDR_VTT +1.5VSUS 6/23 : Del M2 solution A 4/29 reserve M2 solution 10K_4 G780P81U VREF DQ1 M1 Solution +SMDDR_VREF_DIMM +1.5VSUS C84 1U/6.3V_4 C254 1U/6.3V_4 C195 0.1U/10V_4 C39 1U/6.3V_4 C246 1U/6.3V_4 C156 2.2U/6.3V_6 C66 1U/6.3V_4 C238 1U/6.3V_4 C64 1U/6.3V_4 C265 1U/6.3V_4 C59 10U/6.3VS_6 C260 10U/6.3V_6 C594 0.1U/10V_4 C111 10U/6.3VS_6 C225 *10U/6.3V_6 C582 2.2U/6.3V_6 C104 10U/6.3VS_6 C53 10U/6.3VS_6 C90 10U/6.3VS_6 C669 0.1U/10V_4 C96 10U/6.3VS_6 C670 2.2U/6.3V_6 C74 *10U/6.3V_6 C125 10U/6.3V_8 C103 10U/6.3V_8 R490 1K/F_4 +SMDDR_VREF_DQ1 [5,13,43] DDR_VTTREF R90 SMDDR_VREF_DQ1_M1 *0_6 R84 1K/F_4 +3V A RTQLGEV"<"NZ517*Jwtqp"Tkxgt+ Swcpvc"Eqorwvgt"Kpe0 PD7 Size Custom Document Number 4 3 2 Rev 1A DDR3 DIMM1-RVS (9.2H) Date: Wednesday, October 13, 2010 5 B Q10 MMBT3904-7-F 2 1 D 98 97 96 95 92 91 90 86 89 85 107 84 83 119 80 78 2 M_B_DQ[63:0] [4] JDIM2A M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13 M_B_A14 M_B_A15 PC2100 DDR3 SDRAM SO-DIMM (204P) [4] M_B_A[15:0] 3 PC2100 DDR3 SDRAM SO-DIMM (204P) 5 1 Sheet 14 of 47 5 4 3 2 37 1 U33H U33A DP C/D POWER D [3] [3] PEG_TX15 PEG_TX#15 PEG_TX15 AA38 PEG_TX#15 Y37 [3] [3] PEG_TX14 PEG_TX#14 PEG_TX14 Y35 PEG_TX#14 W36 [3] [3] [3] [3] PEG_TX12 PEG_TX#12 PEG_TX12 V35 PEG_TX#12 U36 [3] [3] PEG_TX11 PEG_TX#11 PEG_TX11 U38 PEG_TX#11 T37 [3] [3] PEG_TX10 PEG_TX#10 PEG_TX10 T35 PEG_TX#10 R36 [3] [3] PEG_TX9 PEG_TX#9 PEG_TX9 R38 PEG_TX#9 P37 [3] [3] PEG_TX8 PEG_TX#8 PEG_TX8 P35 PEG_TX#8 N36 [3] [3] PEG_TX7 PEG_TX#7 PEG_TX7 N38 PEG_TX#7 M37 [3] [3] PEG_TX6 PEG_TX#6 PEG_TX6 M35 PEG_TX#6 L36 PEG_TX5 PEG_TX#5 L38 K37 PEG_TX4 PEG_TX#4 K35 J36 [3] [3] PEG_TX5 PEG_TX#5 [3] [3] PEG_TX4 PEG_TX#4 [3] [3] PEG_TX3 PEG_TX#3 PEG_TX3 J38 PEG_TX#3 H37 [3] [3] PEG_TX2 PEG_TX#2 PEG_TX2 H35 PEG_TX#2 G36 [3] [3] PEG_TX1 PEG_TX#1 [3] [3] PEG_TX0 PEG_TX#0 PEG_TX1 G38 PEG_TX#1 F37 PCIE_TX0P PCIE_TX0N Y33 Y32 C_PEG_RXP15 C_PEG_RXN15 C187 C193 0.1U/10V_4 0.1U/10V_4 PCIE_RX1P PCIE_RX1N PCIE_TX1P PCIE_TX1N W33 W32 C_PEG_RXP14 C_PEG_RXN14 C175 C189 0.1U/10V_4 0.1U/10V_4 PCIE_RX2P PCIE_RX2N PCIE_TX2P PCIE_TX2N T33 T32 C_PEG_RXP11 C_PEG_RXN11 C213 C224 0.1U/10V_4 0.1U/10V_4 T30 T29 C_PEG_RXP10 C_PEG_RXN10 C233 C245 0.1U/10V_4 0.1U/10V_4 P33 P32 C_PEG_RXP9 C_PEG_RXN9 C227 C239 0.1U/10V_4 0.1U/10V_4 P30 P29 C_PEG_RXP8 C_PEG_RXN8 C231 C242 0.1U/10V_4 0.1U/10V_4 PCIE_RX8P PCIE_RX8N N33 N32 C_PEG_RXP7 C_PEG_RXN7 C247 C256 0.1U/10V_4 0.1U/10V_4 PCIE_RX9P PCIE_RX9N N30 N29 C_PEG_RXP6 C_PEG_RXN6 C255 C259 0.1U/10V_4 0.1U/10V_4 L33 L32 C_PEG_RXP5 C_PEG_RXN5 C262 C264 0.1U/10V_4 0.1U/10V_4 PCIE_RX10P PCIE_RX10N PCIE_RX11P PCIE_RX11N PCIE_TX11P PCIE_TX11N L30 L29 C_PEG_RXP4 C_PEG_RXN4 C263 C270 0.1U/10V_4 0.1U/10V_4 PCIE_RX12P PCIE_RX12N PCIE_TX12P PCIE_TX12N K33 K32 C_PEG_RXP3 C_PEG_RXN3 C266 C271 0.1U/10V_4 0.1U/10V_4 PCIE_RX13P PCIE_RX13N J33 J32 C_PEG_RXP2 C_PEG_RXN2 C273 C275 0.1U/10V_4 0.1U/10V_4 PCIE_TX5P PCIE_TX5N PCIE_TX6P PCIE_TX6N PCIE_TX7P PCIE_TX7N PCIE_TX8P PCIE_TX8N PCIE_TX9P PCIE_TX9N PCIE_TX10P PCIE_TX10N PCIE_TX13P PCIE_TX13N PCIE_RX14P PCIE_RX14N PCIE_TX14P PCIE_TX14N PCIE_RX15P PCIE_RX15N PCIE_TX15P PCIE_TX15N PEG_RX15 [3] PEG_RX#15 [3] K30 K29 C_PEG_RXP1 C_PEG_RXN1 C278 C279 0.1U/10V_4 0.1U/10V_4 H33 H32 C_PEG_RXP0 C_PEG_RXN0 C276 C277 0.1U/10V_4 0.1U/10V_4 +1.8V_DPC_VDD18 AP20 AP21 +1.0V_DPC_VDD10 AP13 AT13 F35 E37 PEG_RX13 [3] PEG_RX#13 [3] AN17 AP16 AP17 AW14 AW16 PEG_RX12 [3] PEG_RX#12 [3] PEG_RX11 [3] PEG_RX#11 [3] +1.8V_DPC_VDD18 AP22 AP23 +1.0V_DPC_VDD10 AP14 AP15 PEG_RX9 [3] PEG_RX#9 [3] AN19 AP18 AP19 AW20 AW22 PEG_RX8 [3] PEG_RX#8 [3] PEG_RX7 [3] PEG_RX#7 [3] 150/F_4DPCD_CALR AW18 R426 PEG_RX6 [3] PEG_RX#6 [3] B PEG_RX5 [3] PEG_RX#5 [3] [37] R62 10K/F_4 R198 PEGX_RST# VGA_RST# AA30 *0_4/S NC#1 NC#2 PWRGOOD DPC_VSSR#1 DPC_VSSR#2 DPC_VSSR#3 DPC_VSSR#4 DPC_VSSR#5 DPA_VSSR#1 DPA_VSSR#2 DPA_VSSR#3 DPA_VSSR#4 DPA_VSSR#5 DPD_VDD18#1 DPD_VDD18#2 DPB_VDD18#1 DPB_VDD18#2 DPD_VDD10#1 DPD_VDD10#2 DPB_VDD10#1 DPB_VDD10#2 DPD_VSSR#1 DPD_VSSR#2 DPD_VSSR#3 DPD_VSSR#4 DPD_VSSR#5 DPB_VSSR#1 DPB_VSSR#2 DPB_VSSR#3 DPB_VSSR#4 DPB_VSSR#5 DPCD_CALR DPAB_CALR AH34 AJ34 PCIE_CALRN Y30 PCIE_CALRP R102 1.27K/F_4 Y29 PCIE_CALRN R94 2K/F_4 AP31 AP32 +1.0V_VGA D +1.0V_DPA_VDD10 HCB1608KF-181T15/1.5A_6 C92 10U/6.3V_8 AN27 AP27 AP28 AW24 AW26 C91 1U/6.3V_4 C100 0.1U/10V_4 +1.8V_DPA_VDD18 AP25 AP26 +1.0V_DPE_VDD10 AL33 AM33 DPE_VDD10#1 DPE_VDD10#2 AN33 AP33 AN29 AP29 AP30 AW30 AW32 AW28 DPAB_CALR R424 DP PLL POWER DPA_PVDD DPA_PVSS AU28 AV27 DPB_PVDD DPB_PVSS AV29 AR28 150/F_4 C +1.8V_VGA L5 +1.8V_DPB_PVDD HCB1608KF-181T15/1.5A_6 C51 10U/6.3V_8 PEG_RX3 [3] PEG_RX#3 [3] AN34 AP39 AR39 AU37 PEG_RX2 [3] PEG_RX#2 [3] DPE_VSSR#1 DPE_VSSR#2 DPE_VSSR#3 DPE_VSSR#4 DPC_PVDD DPC_PVSS PEG_RX1 [3] PEG_RX#1 [3] AF34 AG34 DPF_VDD18#1 DPF_VDD18#2 PEG_RX0 [3] PEG_RX#0 [3] DPE_PVDD DPE_PVSS AK33 AK34 AF39 AH39 AK39 AL34 AM34 +1.0V_VGA R460 PERSTB 150/F_4 DPEF_CALR AM39 C540 1U/6.3V_4 C531 0.1U/10V_4 AU18 AV17 ( DPC/D_PVDD:1.8V@20mA+20mA) DPD_PVDD DPD_PVSS DPF_VDD10#1 DPF_VDD10#2 NC_DPF_PVDD NC_DPF_PVSS PCIE_CALRP +1.8V_DPA_VDD18 ( DPA/B_PVDD : 1.8V@20mA+20mA) PEG_RX4 [3] PEG_RX#4 [3] CALIBRATION AJ21 AK21 PWRGOOD_BUF AH16 DPA_VDD10#1 DPA_VDD10#2 +1.8V_DPE_VDD18 PCIE_REFCLKP PCIE_REFCLKN Seymour/Whistler:SWAPLOCKA Madison/Capilano :NC DPC_VDD10#1 DPC_VDD10#2 DP E/F POWER DPE_VDD18#1 DPE_VDD18#2 +1.0V_DPE_VDD10 [9] CLK_PCIE_VGA [9] CLK_PCIE_VGA# AN24 AP24 PEG_RX10 [3] PEG_RX#10 [3] CLOCK CLK_PCIE_VGA AB35 CLK_PCIE_VGA# AA36 DPA_VDD18#1 DPA_VDD18#2 L9 +1.8V_DPE_VDD18 PEG_TX0 PEG_TX#0 DP A/B POWER DPC_VDD18#1 DPC_VDD18#2 ( DPA/B_VDD10 : 1.0V@115mA+115mA) PEG_RX14 [3] PEG_RX#14 [3] 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 PCIE_TX4P PCIE_TX4N PCIE_RX7P PCIE_RX7N C207 C215 C202 C208 PCIE_RX4P PCIE_RX4N PCIE_RX6P PCIE_RX6N C_PEG_RXP13 C_PEG_RXN13 C_PEG_RXP12 C_PEG_RXN12 PCIE_TX3P PCIE_TX3N PCIE_RX5P PCIE_RX5N U33 U32 U30 U29 PCIE_RX3P PCIE_RX3N PCI EXPRESS INTERFACE C PEG_TX13 W38 PEG_TX#13 V37 PEG_TX13 PEG_TX#13 PCIE_RX0P PCIE_RX0N DPF_VSSR#1 DPF_VSSR#2 DPF_VSSR#3 DPF_VSSR#4 DPF_VSSR#5 +1.8V_VGA +1.8V_DPC_PVDD AV19 AR18 AM37 AN38 +1.8V_VGA ( DPE/F_PVDD1.8V@20mA+20mA) AL38 AM35 L35 +1.8V_DPE_PVDD HCB1608KF-181T15/1.5A_6 C565 10U/6.3V_8 C568 0.1U/10V_4 B C569 0.1U/10V_4 DPEF_CALR Capilano Pro/Robson_M2 PV Change to Short Pad Capilano Pro/Robson_M2 +1.8V_VGA ( DPE/F_VDD18 : 1.8V@200mA+200mA) L37 +1.8V_DPE_VDD18 +1.8V_VGA +1.8V_VGA +1.8V_VGA ( VDD10 M97 1.0V/M96 1.1V) ( DPE/F_VDD10 : 1.0V@115mA+115mA ) HCB1608KF-181T15/1.5A_6 C581 10U/6.3V_8 +1.0V_VGA C580 1U/6.3V_4 C583 0.1U/10V_4 L14 +1.0V_DPE_VDD10 C124 0.1U/10V_4 C588 0.1U/10V_4 C773 0.1U/10V_4 HCB1608KF-181T15/1.5A_6 C113 10U/6.3V_8 C118 1U/6.3V_4 C119 0.1U/10V_4 ( DPA/B_VDD18 : 1.8V@200mA+200mA) +1.8V_VGA L31 +1.8V_DPA_VDD18 A A MV EMI Request HCB1608KF-181T15/1.5A_6 SI Del R43,R38,C57 ( DPC/D_VDD10 : 1.0V@115mA+115mA) C528 C532 10U/6.3VS_6 1U/6.3V_4 +1.0V_VGA C542 0.1U/10V_4 SI Change +1.0V_DPC_VDD10 +1.0V_VGA [17,19,43] +1.8V_VGA [17,19,42] +1.8V_VGA RTQLGEV"<"NZ517*Jwtqp"Tkxgt+ Swcpvc"Eqorwvgt"Kpe0 ( DPC/D_VDD18 : 1.8V@200mA+200mA) +1.8V_DPC_VDD18 PD7 Size Custom Document Number Date: Wednesday, October 13, 2010 5 4 3 2 Rev 1A CATI APILANO-PRO (MEM)1/5 1 Sheet 15 of 47 5 4 3 2 38 1 [20] DQA0_[0..31] Park, M92M Use Channel B Memory Interface Only +1.5V_VGA Ra R536 40.2/F_4 L18 L20 MVREFDA MVREFSA CKEA0 CKEA1 MEM_CALRN0 MEM_CALRN1 MEM_CALRN2 5/3: stuff R88,R89 by AMD request MVREFDA MVREFSA B Rb R532 100/F_4 C695 +1.5V_VGA 0.1U/10V_4 243/F_4 R562 243/F_4 R148 243/F_4 R79 L27 N12 AG12 243/F_4 R147 243/F_4 R563 243/F_4 R434 M12 M27 AH12 +1.5V_VGA MAA0_0/MAA_0 MAA0_1/MAA_1 MAA0_2/MAA_2 MAA0_3/MAA_3 MAA0_4/MAA_4 MAA0_5/MAA_5 MAA0_6/MAA_6 MAA0_7/MAA_7 MAA1_0/MAA_8 MAA1_1/MAA_9 MAA1_2/MAA_10 MAA1_3/MAA_11 MAA1_4/MAA_12 MAA1_5/MAA_13_BA2 MAA1_6/MAA_14_BA0 MAA1_7/MAA_A15_BA1 WCKA0_0/DQMA_0 WCKA0B_0/DQMA_1 WCKA0_1/DQMA_2 WCKA0B_1/DQMA_3 WCKA1_0/DQMA_4 WCKA1B_0/DQMA_5 WCKA1_1/DQMA_6 WCKA1B_1/DQMA_7 GDDR5/DDR2/GDDR3 EDCA0_0/QSA_0/RDQSA_0 EDCA0_1/QSA_1/RDQSA_1 EDCA0_2/QSA_2/RDQSA_2 EDCA0_3/QSA_3/RDQSA_3 EDCA1_0/QSA_4/RDQSA_4 EDCA1_1/QSA_5/RDQSA_5 EDCA1_2/QSA_6/RDQSA_6 EDCA1_3/QSA_7/RDQSA_7 A32 C32 D23 E22 C14 A14 E10 D9 WCKA0_0 WCKA0_0# WCKA0_1 WCKA0_1# WCKA1_0 WCKA1_0# WCKA1_1 WCKA1_1# C34 D29 D25 E20 E16 E12 J10 D7 EDCA0_0 EDCA0_1 EDCA0_2 EDCA0_3 EDCA1_0 EDCA1_1 EDCA1_2 EDCA1_3 A34 E30 E26 C20 C16 C12 J11 F8 DBIA0_0 DBIA0_1 DBIA0_2 DBIA0_3 DBIA1_0 DBIA1_1 DBIA1_2 DBIA1_3 MAA1_[0..8] MAB0_[0..8] [23] MAB1_[0..8] WCKA0_0 [20] WCKA0_0# [20] WCKA0_1 [20] WCKA0_1# [20] WCKA1_0 [21] WCKA1_0# [21] WCKA1_1 [21] WCKA1_1# [21] DBIA0_0 DBIA0_1 DBIA0_2 DBIA0_3 DBIA1_0 DBIA1_1 DBIA1_2 DBIA1_3 [20] [20] [20] [20] [21] [21] [21] [21] J21 G19 ADBIA0# ADBIA1# [20] [21] H27 G27 CLKA0 CLKA0# [20] [20] J14 H14 CLKA1 CLKA1# [21] [21] K23 K19 RASA0# RASA1# [20] [21] K20 K17 CASA0# CASA1# [20] [21] K24 K27 CSA0# [20] M13 K16 CSA1# K21 J20 CKEA0# CKEA1# [20] [21] WEA0B WEA1B K26 L15 WEA0# WEA1# [20] [21] MAA0_8 MAA1_8 H23 J19 CLKA0 CLKA0B CLKA1 CLKA1B RASA0B RASA1B CASA0B CASA1B CSA0B_0 CSA0B_1 CSA1B_0 CSA1B_1 +1.5V_VGA [21] R142 40.2/F_4 Ra MAA0_8 MAA1_8 DQB0_0 DQB0_1 DQB0_2 DQB0_3 DQB0_4 DQB0_5 DQB0_6 DQB0_7 DQB0_8 DQB0_9 DQB0_10 DQB0_11 DQB0_12 DQB0_13 DQB0_14 DQB0_15 DQB0_16 DQB0_17 DQB0_18 DQB0_19 DQB0_20 DQB0_21 DQB0_22 DQB0_23 DQB0_24 DQB0_25 DQB0_26 DQB0_27 DQB0_28 DQB0_29 DQB0_30 DQB0_31 DQB1_0 DQB1_1 DQB1_2 DQB1_3 DQB1_4 DQB1_5 DQB1_6 DQB1_7 DQB1_8 DQB1_9 DQB1_10 DQB1_11 DQB1_12 DQB1_13 DQB1_14 DQB1_15 DQB1_16 DQB1_17 DQB1_18 DQB1_19 DQB1_20 DQB1_21 DQB1_22 DQB1_23 DQB1_24 DQB1_25 DQB1_26 DQB1_27 DQB1_28 DQB1_29 DQB1_30 DQB1_31 [23] DQB1_[0..31] [22] [20] [20] [20] [20] [21] [21] [21] [21] ADBIA0/ODTA0 ADBIA1/ODTA1 U33D DDR2 GDDR3/GDDR5 DDR3 [22] DQB0_[0..31] EDCA0_0 EDCA0_1 EDCA0_2 EDCA0_3 EDCA1_0 EDCA1_1 EDCA1_2 EDCA1_3 DDBIA0_0/QSA_0B/WDQSA_0 DDBIA0_1/QSA_1B/WDQSA_1 DDBIA0_2/QSA_2B/WDQSA_2 DDBIA0_3/QSA_3B/WDQSA_3 DDBIA1_0/QSA_4B/WDQSA_4 DDBIA1_1/QSA_5B/WDQSA_5 DDBIA1_2/QSA_6B/WDQSA_6 DDBIA1_3/QSA_7B/WDQSA_7 MEM_CALRP1 MEM_CALRP0 MEM_CALRP2 G24 J23 H24 J24 H26 J26 H21 G21 H19 H20 L13 G16 J16 H16 J17 H17 MAA0_0 MAA0_1 MAA0_2 MAA0_3 MAA0_4 MAA0_5 MAA0_6 MAA0_7 MAA1_0 MAA1_1 MAA1_2 MAA1_3 MAA1_4 MAA1_5 MAA1_6 MAA1_7 [21] MVREFDB MVREFSB R140 100/F_4 Rb +3V_VGA C223 SI 0.1U/10V_4 Ra RSVD Capilano Pro/Robson_M2 For PARK MEM_CALRNP1 stuff MEM_CALRNP2 A C197 0.1U/10V_4 stuff ** GDDR3 DDR3 1.5V 1.8V/1.5V 1.5V Ra 40.2R 40.2R 40.2R Rb 100R 100R 100R +1.5V_VGA WCKB0_0/DQMB_0 WCKB0B_0/DQMB_1 WCKB0_1/DQMB_2 WCKB0B_1/DQMB_3 WCKB1_0/DQMB_4 WCKB1B_0/DQMB_5 WCKB1_1/DQMB_6 WCKB1B_1/DQMB_7 GDDR5/DDR2/GDDR3 EDCB0_0/QSB_0/RDQSB_0 EDCB0_1/QSB_1/RDQSB_1 EDCB0_2/QSB_2/RDQSB_2 EDCB0_3/QSB_3/RDQSB_3 EDCB1_0/QSB_4/RDQSB_4 EDCB1_1/QSB_5/RDQSB_5 EDCB1_2/QSB_6/RDQSB_6 EDCB1_3/QSB_7/RDQSB_7 DDBIB0_0/QSB_0B/WDQSB_0 DDBIB0_1/QSB_1B/WDQSB_1 DDBIB0_2/QSB_2B/WDQSB_2 DDBIB0_3/QSB_3B/WDQSB_3 DDBIB1_0/QSB_4B/WDQSB_4 DDBIB1_1/QSB_5B/WDQSB_5 DDBIB1_2/QSB_6B/WDQSB_6 DDBIB1_3/QSB_7B/WDQSB_7 ADBIB0/ODTB0 ADBIB1/ODTB1 R127 *51/F_4 WCKB0_0 WCKB0_0# WCKB0_1 WCKB0_1# WCKB1_0 WCKB1_0# WCKB1_1 WCKB1_1# F6 K3 P3 V5 AB5 AH1 AJ9 AM5 EDCB0_0 EDCB0_1 EDCB0_2 EDCB0_3 EDCB1_0 EDCB1_1 EDCB1_2 EDCB1_3 G7 K1 P1 W4 AC4 AH3 AJ8 AM3 DBIB0_0 DBIB0_1 DBIB0_2 DBIB0_3 DBIB1_0 DBIB1_1 DBIB1_2 DBIB1_3 T7 W7 [22] [22] [22] [22] [23] [23] [23] [23] DBIB0_0 DBIB0_1 DBIB0_2 DBIB0_3 DBIB1_0 DBIB1_1 DBIB1_2 DBIB1_3 [22] [22] [22] [22] [23] [23] [23] [23] [23] [23] RASB0# RASB1# [22] [23] W10 AA10 CASB0# CASB1# [22] [23] P10 L10 CSB0# [22] AD10 AC10 CSB1# [23] U10 AA11 CKEB0# CKEB1# [22] [23] WEB0B WEB1B N10 AB11 WEB0# WEB1# [22] [23] MAB0_8 MAB1_8 T8 W8 CSB0B_0 CSB0B_1 CSB1B_0 CSB1B_1 DRAM_RST C539 *0.1U/10V_4 MAB0_8 MAB1_8 [22] [22] 4 3 4/29 modify AH11 R420 *51/F_4 VM_RST_1 R83 R80 ** 10_4 R81 51_4 VM_RST# [20,21,22,23] ** R_MEM_3 C75 ** ** R_MEM_1 120P/50V_4 C_MEM R_MEM_2 5K/F_4 Designator 5/6: change R68 from 10k to 5.11k for AMD MV del R567 add R68 in BOM R_MEM_1 5K R_MEM_2 10R R_MEM_3 51R C_MEM 120pF A This basic topology should be used for DRAM_RST for DDR3/GDDR3/GDDR5.These Capacitors and Resistor values are an example only. The Series R and || Cap values will depend on the DRAM load and will have to be calculated for different Memory ,DRAM Load and board to pass Reset Signal Spec. 2 B 25mm (max) 5mm (max) 25mm (max) RTQLGEV"<"NZ517*Jwtqp"Tkxgt+ Swcpvc"Eqorwvgt"Kpe0 PD7 Size Custom Document Number Rev 1A ATI CAPILANO-PRO (MEM)2/5 Date: Wednesday, October 13, 2010 5 C ADBIB0# [22] ADBIB1# [23] T10 Y10 CASB0B CASB1B +1.5V_VGA EDCB0_0 EDCB0_1 EDCB0_2 EDCB0_3 EDCB1_0 EDCB1_1 EDCB1_2 EDCB1_3 CLKB0 CLKB0# CKEB0 CKEB1 [19,20,21,22,23,47] WCKB0_0 [22] WCKB0_0# [22] WCKB0_1 [22] WCKB0_1# [22] WCKB1_0 [23] WCKB1_0# [23] WCKB1_1 [23] WCKB1_1# [23] CLKB1 CLKB1# RASB0B RASB1B CLKTESTA CLKTESTB H3 H1 T3 T5 AE4 AF5 AK6 AK5 D AD8 AD7 CLKB1 CLKB1B TESTEN MAB0_0 MAB0_1 MAB0_2 MAB0_3 MAB0_4 MAB0_5 MAB0_6 MAB0_7 MAB1_0 MAB1_1 MAB1_2 MAB1_3 MAB1_4 MAB1_5 MAB1_6 MAB1_7 L9 L8 CLKB0 CLKB0B MVREFDB MVREFSB P8 T9 P9 N7 N8 N9 U9 U8 Y9 W9 AC8 AC9 AA7 AA8 Y8 AA9 Place all these components very close to GPU (Within 25mm) and keep all component close to each Other (within 5mm) except Rser2 DDR3/GDDR3 Memory Stuff Option GDDR5 MAB0_0/MAB_0 MAB0_1/MAB_1 MAB0_2/MAB_2 MAB0_3/MAB_3 MAB0_4/MAB_4 MAB0_5/MAB_5 MAB0_6/MAB_6 MAB0_7/MAB_7 MAB1_0/MAB_8 MAB1_1/MAB_9 MAB1_2/MAB_10 MAB1_3/MAB_11 MAB1_4/MAB_12 MAB1_5/BA2 MAB1_6/BA0 MAB1_7/BA1 R131 100/F_4 Rb stuff DQB0_0/DQB_0 DQB0_1/DQB_1 DQB0_2/DQB_2 DQB0_3/DQB_3 DQB0_4/DQB_4 DQB0_5/DQB_5 DQB0_6/DQB_6 DQB0_7/DQB_7 DQB0_8/DQB_8 DQB0_9/DQB_9 DQB0_10/DQB_10 DQB0_11/DQB_11 DQB0_12/DQB_12 DQB0_13/DQB_13 DQB0_14/DQB_14 DQB0_15/DQB_15 DQB0_16/DQB_16 DQB0_17/DQB_17 DQB0_18/DQB_18 DQB0_19/DQB_19 DQB0_20/DQB_20 DQB0_21/DQB_21 DQB0_22/DQB_22 DQB0_23/DQB_23 DQB0_24/DQB_24 DQB0_25/DQB_25 DQB0_26/DQB_26 DQB0_27/DQB_27 DQB0_28/DQB_28 DQB0_29/DQB_29 DQB0_30/DQB_30 DQB0_31/DQB_31 DQB1_0/DQB_32 DQB1_1/DQB_33 DQB1_2/DQB_34 DQB1_3/DQB_35 DQB1_4/DQB_36 DQB1_5/DQB_37 DQB1_6/DQB_38 DQB1_7/DQB_39 DQB1_8/DQB_40 DQB1_9/DQB_41 DQB1_10/DQB_42 DQB1_11/DQB_43 DQB1_12/DQB_44 DQB1_13/DQB_45 DQB1_14/DQB_46 DQB1_15/DQB_47 DQB1_16/DQB_48 DQB1_17/DQB_49 DQB1_18/DQB_50 DQB1_19/DQB_51 DQB1_20/DQB_52 DQB1_21/DQB_53 DQB1_22/DQB_54 DQB1_23/DQB_55 DQB1_24/DQB_56 DQB1_25/DQB_57 DQB1_26/DQB_58 DQB1_27/DQB_59 DQB1_28/DQB_60 DQB1_29/DQB_61 DQB1_30/DQB_62 DQB1_31/DQB_63 Capilano Pro/Robson_M2 R123 5.11K/F_4 MEM_CALRNP0 C719 0.1U/10V_4 AD28 R132 40.2/F_4 Ra For Madison Y12 AA12 TEST_MCLK AK10 TEST_YCLK AL10 C153 *0.1U/10V_4 R548 40.2/F_4 R545 100/F_4 Rb TESTEN R115 *10K/F_4 +1.5V_VGA AL31 Add C5 C3 E3 E1 F1 F3 F5 G4 H5 H6 J4 K6 K5 L4 M6 M1 M3 M5 N4 P6 P5 R4 T6 T1 U4 V6 V1 V3 Y6 Y1 Y3 Y5 AA4 AB6 AB1 AB3 AD6 AD1 AD3 AD5 AF1 AF3 AF6 AG4 AH5 AH6 AJ4 AK3 AF8 AF9 AG8 AG7 AK9 AL7 AM8 AM7 AK1 AL4 AM6 AM1 AN4 AP3 AP1 AP5 DDR2 GDDR5/GDDR3 DDR3 GDDR5 C DQA0_0/DQA_0 DQA0_1/DQA_1 DQA0_2/DQA_2 DQA0_3/DQA_3 DQA0_4/DQA_4 DQA0_5/DQA_5 DQA0_6/DQA_6 DQA0_7/DQA_7 DQA0_8/DQA_8 DQA0_9/DQA_9 DQA0_10/DQA_10 DQA0_11/DQA_11 DQA0_12/DQA_12 DQA0_13/DQA_13 DQA0_14/DQA_14 DQA0_15/DQA_15 DQA0_16/DQA_16 DQA0_17/DQA_17 DQA0_18/DQA_18 DQA0_19/DQA_19 DQA0_20/DQA_20 DQA0_21/DQA_21 DQA0_22/DQA_22 DQA0_23/DQA_23 DQA0_24/DQA_24 DQA0_25/DQA_25 DQA0_26/DQA_26 DQA0_27/DQA_27 DQA0_28/DQA_28 DQA0_29/DQA_29 DQA0_30/DQA_30 DQA0_31/DQA_31 DQA1_0/DQA_32 DQA1_1/DQA_33 DQA1_2/DQA_34 DQA1_3/DQA_35 DQA1_4/DQA_36 DQA1_5/DQA_37 DQA1_6/DQA_38 DQA1_7/DQA_39 DQA1_8/DQA_40 DQA1_9/DQA_41 DQA1_10/DQA_42 DQA1_11/DQA_43 DQA1_12/DQA_44 DQA1_13/DQA_45 DQA1_14/DQA_46 DQA1_15/DQA_47 DQA1_16/DQA_48 DQA1_17/DQA_49 DQA1_18/DQA_50 DQA1_19/DQA_51 DQA1_20/DQA_52 DQA1_21/DQA_53 DQA1_22/DQA_54 DQA1_23/DQA_55 DQA1_24/DQA_56 DQA1_25/DQA_57 DQA1_26/DQA_58 DQA1_27/DQA_59 DQA1_28/DQA_60 DQA1_29/DQA_61 DQA1_30/DQA_62 DQA1_31/DQA_63 GDDR5 D C37 C35 A35 E34 G32 D33 F32 E32 D31 F30 C30 A30 F28 C28 A28 E28 D27 F26 C26 A26 F24 C24 A24 E24 C22 A22 F22 D21 A20 F20 D19 E18 C18 A18 F18 D17 A16 F16 D15 E14 F14 D13 F12 A12 D11 F10 A10 C10 G13 H13 J13 H11 G10 G8 K9 K10 G9 A8 C8 E8 A6 C6 E6 A5 MEMORY INTERFACE A DQA0_0 DQA0_1 DQA0_2 DQA0_3 DQA0_4 DQA0_5 DQA0_6 DQA0_7 DQA0_8 DQA0_9 DQA0_10 DQA0_11 DQA0_12 DQA0_13 DQA0_14 DQA0_15 DQA0_16 DQA0_17 DQA0_18 DQA0_19 DQA0_20 DQA0_21 DQA0_22 DQA0_23 DQA0_24 DQA0_25 DQA0_26 DQA0_27 DQA0_28 DQA0_29 DQA0_30 DQA0_31 DQA1_0 DQA1_1 DQA1_2 DQA1_3 DQA1_4 DQA1_5 DQA1_6 DQA1_7 DQA1_8 DQA1_9 DQA1_10 DQA1_11 DQA1_12 DQA1_13 DQA1_14 DQA1_15 DQA1_16 DQA1_17 DQA1_18 DQA1_19 DQA1_20 DQA1_21 DQA1_22 DQA1_23 DQA1_24 DQA1_25 DQA1_26 DQA1_27 DQA1_28 DQA1_29 DQA1_30 DQA1_31 DDR2 GDDR5/GDDR3 DDR3 MEMORY INTERFACE B U33C DDR2 GDDR3/GDDR5 DDR3 MAA0_[0..8] From GPU [21] DQA1_[0..31] [20] 1 Sheet 16 of 47 5 4 3 2 U33G U33B R73 MUTI GFX DPA D NC on Park/Robson/Seymour +1.8V_VGA 5/3: modify for GDDR5 table *10K/F_4 MEM_ID0 10K/F_4 MEM_ID1 *10K/F_4 MEM_ID2 *10K/F_4 MEM_ID3 R453 R455 R448 R446 SI Add for AMD request +3V_VGA TP38 R77 *10K/F_4 GPIO24_TRSTB R76 *10K/F_4 XTALIN R429 GPIO27_TMS *0_4 GPIO26_TCK MV del in BOM 5/5:add a TP 6/30 :Modify TP NC on Park/Robson/Seymour AR8 AU8 AP8 AW8 AR3 AR1 AU1 AU3 AW3 AP6 AW5 AU5 AR6 AW6 AU6 AT7 AV7 AN7 AV9 AT9 AR10 AW10 AU10 AP10 AV11 AT11 AR12 AW12 AU12 AP12 DVPCNTL_MVP_0 DVPCNTL_MVP_1 DVPCNTL_0 DVPCNTL_1 DVPCNTL_2 DVPCLK DVPDATA_0 DVPDATA_1 DVPDATA_2 DVPDATA_3 DVPDATA_4 DVPDATA_5 DVPDATA_6 DVPDATA_7 DVPDATA_8 DVPDATA_9 DVPDATA_10 DVPDATA_11 DVPDATA_12 DVPDATA_13 DVPDATA_14 DVPDATA_15 DVPDATA_16 DVPDATA_17 DVPDATA_18 DVPDATA_19 DVPDATA_20 DVPDATA_21 DVPDATA_22 DVPDATA_23 5/6 add for AMD R56 R57 +3V_VGA AH20 AH18 AN16 AH23 AJ23 6/11 R425 0_4 AH17 8/13 AJ17 AK17 [18,24] GPU_LVDS_BLON VGA_GPIO8 AJ13 SI-2 Add 4/29 add. [18] VGA_GPIO8 VGA_GPIO9 AH15 [18] VGA_GPIO9 VGA_GPIO10 AJ16 [18] VGA_GPIO10 +3V_VGA VGA_GPIO11 AK16 [18] VGA_GPIO11 AL16 [18] VGA_GPIO12 AM16 [18] VGA_GPIO13 AM14 AM13 [18,42] GFX_CORE_CNTRL0 R74 AK14 TP7 AG30 *10K/F_4 [18,35] VGA_ALERT AN14 AM17 4/29 modify. AL13 [18,42] GFX_CORE_CNTRL1 VGA_GPIO21_BBEN AJ14 AK13 [18] VGA_GPIO22 AN13 GPIO24_TRSTB AM23 TP5 GPIO25_TDI R109 AN23 TP6 GPIO26_TCK AK23 *10K/F_4 [18] GPIO26_TCK GPIO27_TMS AL24 TP1 GPIO28_TDO AM24 TP4 AJ19 [18] GENERICA AK19 TP8 AJ20 [18] GENERICC AK20 Seymour/Whistler: Stereo sync output AJ24 Madison/Capilano: Alternate DP clock source & Stereo sync output AH26 6/30 SI Modify TP GenericF/G is NC on PARK AH24 AK24 TMDS_HPD TX1P_DPA1P TX1M_DPA1N AU26 AV25 TXCLK_UP_DPF3P TXCLK_UN_DPF3N AK35 AL36 GPU_TXUCLKOUT+ [24] GPU_TXUCLKOUT- [24] TX2P_DPA0P TX2M_DPA0N AT27 AR26 TXOUT_U0P_DPF2P TXOUT_U0N_DPF2N AJ38 AK37 GPU_TXUOUT0+ [24] GPU_TXUOUT0- [24] AH35 AJ36 GPU_TXUOUT1+ [24] GPU_TXUOUT1- [24] AG38 AH37 GPU_TXUOUT2+ [24] GPU_TXUOUT2- [24] TX4P_DPB1P TX4M_DPB1N TX5P_DPB0P TX5M_DPB0N TXCCP_DPC3P TXCCM_DPC3N TX0P_DPC2P TX0M_DPC2N DPC TX1P_DPC1P TX1M_DPC1N TX2P_DPC0P TX2M_DPC0N TXCDP_DPD3P TXCDM_DPD3N TX4P_DPD1P TX4M_DPD1N TX5P_DPD0P TX5M_DPD0N GPIO_0 GPIO_1 GPIO_2 GPIO_3_SMBDATA GPIO_4_SMBCLK GPIO_5_AC_BATT GPIO_6 GPIO_7_BLON GPIO_8_ROMSO GPIO_9_ROMSI GPIO_10_ROMSCK GPIO_11 GPIO_12 GPIO_13 GPIO_14_HPD2 GPIO_15_PWRCNTL_0 GPIO_16_SSIN GPIO_17_THERMAL_INT GPIO_18_HPD3 GPIO_19_CTF GPIO_20_PWRCNTL_1 GPIO_21_BB_EN GPIO_22_ROMCSB GPIO_23_CLKREQB JTAG_TRSTB JTAG_TDI JTAG_TCK JTAG_TMS JTAG_TDO GENERICA GENERICB GENERICC GENERICD GENERICE_HPD4 GENERICF GENERICG G GB B BB DAC1 HSYNC VSYNC RSET AVDD AVSSQ VDD1DI VSS1DI R2 R2B G2 G2B B2 B2B N_TXC_HDMI+ [27] N_TXC_HDMI- [27] TXOUT_U1P_DPF1P TXOUT_U1N_DPF1N AV31 AU30 N_TX0_HDMI+ [27] N_TX0_HDMI- [27] TXOUT_U2P_DPF0P TXOUT_U2N_DPF0N AR32 AT31 N_TX1_HDMI+ [27] N_TX1_HDMI- [27] TXOUT_U3P TXOUT_U3N AT33 AU32 N_TX2_HDMI+ [27] N_TX2_HDMI- [27] TXCLK_LP_DPE3P TXCLK_LN_DPE3N AT15 AR14 TXOUT_L0P_DPE2P TXOUT_L0N_DPE2N AU16 AV15 AT17 AR16 TXOUT_L1P_DPE1P TXOUT_L1N_DPE1N DP Channel D is NC on Park, Robson and Seymour TXOUT_L2P_DPE0P TXOUT_L2N_DPE0N C918 5.6P/16V_4 AU20 AT19 AT21 AR20 C Y COMP H2SYNC V2SYNC HPD1 A2VDDQ VREFG A2VSSQ C82 0.1U/10V_4 R2SET GPU_CRT_R R482 150/F_4 C919 5.6P/16V_4 GPU_CRT_G R480 150/F_4 C920 5.6P/16V_4 GPU_CRT_B R477 TXOUT_L3P TXOUT_L3N DDC/AUX PLL/CLOCK GND Option If XO_IN/XO_IN2 not used For M97, XO_IN and XO_IN2 should be grounded [18] [18] +1.0VDPLL_VDDC CLK_27M CLK_100M TP3 TP2 AN31 AW34 AW35 AV33 AU34 DPLL_PVDD DPLL_PVSS [18] [18] GFX_THMD+ GFX_THMD- +1.8V_TSVDD DDC1CLK DDC1DATA AUX1P AUX1N DPLL_VDDC DDC2CLK DDC2DATA XO_IN XO_IN2 XTALIN XTALOUT AUX2P AUX2N DDCCLK_AUX3P DDCDATA_AUX3N 4/20 DB modify. A AF29 AG29 AK32 AJ32 AJ33 AF35 AG36 AP34 AR34 GPU_TXLCLKOUT+ [24] GPU_TXLCLKOUT- [24] AW37 AU35 GPU_TXLOUT0+ [24] GPU_TXLOUT0- [24] AR37 AU39 GPU_TXLOUT1+ [24] GPU_TXLOUT1- [24] AP35 AR35 GPU_TXLOUT2+ [24] GPU_TXLOUT2- [24] DPLL_VDCC AN36 AP37 M97 1.0V/M96 1.1V +1.8V_VGA (1.8V@150mA DPLL_PVDD) L11 HCB1608KF-181T15/1.5A_6 +1.8VDPLL_PVDD 8/13 PV modify AU22 AV21 10/13 PV2 EMI request Capilano Pro/Robson_M2 C97 10U/6.3V_8 AT23 AR22 C107 1U/6.3V_4 C101 0.1U/10V_4 150/F_4 AD39 AD37 GPU_CRT_R C AE36 AD35 GPU_CRT_G (1.0V@300mA DPLL_VDDC) GPU_CRT_R [24] +1.8V_VGA DPLUS DMINUS THERMAL DDCCLK_AUX4P DDCDATA_AUX4N DDCCLK_AUX5P DDCDATA_AUX5N TS_FDO TSVDD TSVSS L8 L13 GPU_CRT_B AF37 AE38 AC36 AC38 HCB1608KF-181T15/1.5A_6 +1.8V_AVDD GPU_CRT_B [24] (DAC1_AVDD: 1.8V@70mA+42mA) VGA STRAPS ( A2VDDQ: 1.8V@1mA) GPU_HSYNC [18,24] GPU_VSYNC [18,24] AB34 DAC1_RSET HCB1608KF-181T15/1.5A_6 +1.0VDPLL_VDDC GPU_CRT_G [24] L38 HCB1608KF-181T15/1.5A_6 C571 R105 499/F_4 +1.8V_A2VDDQ AD34 AE34 C73 10U/6.3V_8 C78 1U/6.3V_4 C79 0.1U/10V_4 +1.8V_VGA C579 1U/6.3V_4 (1.8V@20mA TSVDD) 0.1U/10V_4 L16 +1.8V_TSVDD HCB1608KF-181T15/1.5A_6 +1.8V_AVDD +VDD1D AC33 AC34 C114 10U/6.3V_8 C108 1U/6.3V_4 +1.8V_VGA AC30 AC31 (DAC1_VDD1DI:1.8V@100mA) Seymour/Whistler: DAC2 is NC AD30 AD31 AF30 AF31 +VDD1D L12 HCB1608KF-181T15/1.5A_6 C141 C561 10U/6.3VS_6 1U/6.3V_4 Madison/Capilano: DAC2 can be used for PS2(CRT) output or be left unconnected Seymour/Whistler: DAC2 is NC Madison/Capilano:DAC2 Output-C Madison/Capilano:DAC2 Output-Y AC32 AD32 AF32 C560 0.1U/10V_4 SI Add AD29 AC29 HSYNC_DAC2 [18] VSYNC_DAC2 [18] B AG31 VDD2D R476 R464 AG32 *0_4/S *0_4/S Seymour/Whistler: GENCLK_CLK Seymour/Whistler: GENCLK_VSYNC DDC6CLK DDC6DATA NC_DDCCLK_AUX7P NC_DDCDATA_AUX7N GPIO15 GPIO20 +VGACORE +1.8V_VGA For future back compatibility AG33 A2VDD R488 *0_4/S +3V_VGA R465 *0_4/S +1.8V_A2VDDQ AD33 For FL/GL support on Seymour/Whistler only Low Low 1.05V Low High 1V High Low 0.95V High High 0.9V NC on Seymour/Whistler AF33 AA29 DAC2_RSET R129 715/F_4 Seymour/Whistler:TSVSSQ Temperature sensor quiet ground. AM32 AN32 D VGA STRAPS A2VDD +1.8VDPLL_PVDD 10K_4 LVTMDP AU14 AV13 DAC2 R78 499/F_4 R117 249/F_4 AR30 AT29 GPU_DPST_PWM [24] GPU_DISP_ON [24] +1.0V_VGA R RB VDD2DI VSS2DI +VGA_VREFG AH13 R72 SCL SDA +1.8V_VGA PLACE VREFG DIVIDER AND CAP CLOSE TO ASIC AT25 AR24 10K_4 GPU_DPST_PWM GPU_DISP_ON AK27 AJ27 GENERAL PURPOSE I/O [18] VGA_GPIO0 [18] VGA_GPIO1 [18] VGA_GPIO2 [18] G_SMBDAT DB2 modify [18] G_SMBCLK PV modify [35] GPU_PROCHOT [27] TX0P_DPA2P TX0M_DPA2N LVDS CONTROL VARY_BL DIGON TX3P_DPB2P TX3M_DPB2N DPB I2C AK26 AJ26 GPIO0: option to control PSI in future products - not currently qualified B AU24 AV23 TXCBP_DPB3P TXCBM_DPB3N DPD *4.7K_4 *4.7K_4 [24] GPU_EDIDCLK [24] GPU_EDIDDATA TXCAP_DPA3P TXCAM_DPA3N TX3P_DPD2P TX3M_DPD2N Access to SCL and SDA is mandatory on BACO designs for debug purposes C 39 1 AM26 AN26 AM27 AL27 AM19 AL19 AN20 AM20 Madison/Capilano: A2VSSQ. HDMI_SCL [27] HDMI_SDA [27] DDC1 AND AUX1 CAN BE JOINTED TOGETHER FOR DUAL DCC/AUX FUNCTION REFER THE DATABOOK FOR DETAIL DDC2 AND AUX2 CAN BE JOINTED TOGETHER FOR DUAL DCC/AUX FUNCTION REFER THE DATABOOK FOR DETAIL AL30 AM30 DDCxx_AUX3x is NC on M92M2 AL29 AM29 DDCxx_AUX4x is NC on M92M2 and Park/Robson/Seymour OGO""KF 5 4 3 2 Xgtqpc FXRFCVC 5 4 3 2 IFFT7"V{rg 3 2 2 2 3 4 2 2 3 2 5 2 2 3 3 Eqphkiwtcvkqp Uk¦g Ucouwpi"M6I32547HG/JE27"*602Idru+" 54,54"qt"86,38"z":"reu 3I J{pkz"J7IS3J46CHT/V2E"DIC *602Idru+ 54,54"qt"86,38"z":"reu 3I A AN21 AM21 AJ30 AJ31 AK30 AK29 GPU_DDCCLK [24] GPU_DDCDATA [24] DDCxx_AUX7x is NC on M9x and Park/Robson/Seymour GPIO6 +VDDCI High 1.07V Low 1.12V [15,19,43] +1.0V_VGA [15,19,42] +1.8V_VGA [16,18,19,27,42] +3V_VGA Capilano Pro/Robson_M2 RTQLGEV"<"NZ517*Jwtqp"Tkxgt+ Swcpvc"Eqorwvgt"Kpe0 PD7 Size Custom Document Number 5 4 3 2 Rev 1A ATI CAPILANO-PRO DISPLAY3/5 Date: Wednesday, October 13, 2010 1 Sheet 17 of 47 5 4 3 STRAPS U33F D C B A AB39 E39 F34 F39 G33 G34 H31 H34 H39 J31 J34 K31 K34 K39 L31 L34 M34 M39 N31 N34 P31 P34 P39 R34 T31 T34 T39 U31 U34 V34 V39 W31 W34 Y34 Y39 F15 F17 F19 F21 F23 F25 F27 F29 F31 F33 F7 F9 G2 G6 H9 J2 J27 J6 J8 K14 K7 L11 L17 L2 L22 L24 L6 M17 M22 M24 N16 N18 N2 N21 N23 N26 N6 R15 R17 R2 R20 R22 R24 R27 R6 T11 T13 T16 T18 T21 T23 T26 U15 U17 U2 U20 U22 U24 U27 U6 V11 V16 V18 V21 V23 V26 W2 W6 Y15 Y17 Y20 Y22 Y24 Y27 U13 V13 PCIE_VSS#1 PCIE_VSS#2 PCIE_VSS#3 PCIE_VSS#4 PCIE_VSS#5 PCIE_VSS#6 PCIE_VSS#7 PCIE_VSS#8 PCIE_VSS#9 PCIE_VSS#10 PCIE_VSS#11 PCIE_VSS#12 PCIE_VSS#13 PCIE_VSS#14 PCIE_VSS#15 PCIE_VSS#16 PCIE_VSS#17 PCIE_VSS#18 PCIE_VSS#19 PCIE_VSS#20 PCIE_VSS#21 PCIE_VSS#22 PCIE_VSS#23 PCIE_VSS#24 PCIE_VSS#25 PCIE_VSS#26 PCIE_VSS#27 PCIE_VSS#28 PCIE_VSS#29 PCIE_VSS#30 PCIE_VSS#31 PCIE_VSS#32 PCIE_VSS#33 PCIE_VSS#34 PCIE_VSS#35 GND#100 GND#101 GND#102 GND#103 GND#104 GND#105 GND#106 GND#107 GND#108 GND#109 GND#110 GND#111 GND#112 GND#113 GND#114 GND#115 GND#116 GND#117 GND#118 GND#119 GND#120 GND#121 GND#122 GND#123 GND#124 GND#125 GND#126 GND#127 GND#128 GND#129 GND#130 GND#131 GND#132 GND#133 GND#134 GND#135 GND#136 GND#137 GND#138 GND#139 GND#140 GND#141 GND#142 GND#143 GND#144 GND#145 GND#146 GND#147 GND#148 GND#149 GND#150 GND#151 GND#153 GND#154 GND#155 GND#156 GND#157 GND#158 GND#159 GND#160 GND#161 GND#163 GND#164 GND#165 GND#166 GND#167 GND#168 GND#169 GND#170 GND#171 GND#172 GND#173 GND#174 GND#175 GND#152 GND#162 GND#1 GND#2 GND#3 GND#4 GND#5 GND#6 GND#7 GND#8 GND#9 GND#10 GND#11 GND#12 GND#13 GND#14 GND#15 GND#16 GND#17 GND#18 GND#19 GND#20 GND#21 GND#22 GND#23 GND#24 GND#25 GND#26 GND#27 GND#28 GND#29 GND#30 GND#31 GND#32 GND#33 GND#34 GND#35 GND#36 GND#37 GND#38 GND#39 GND#40 GND#41 GND#42 GND#43 GND#44 GND#45 GND#46 GND#47 GND#48 GND#49 GND#50 GND#51 GND#52 GND#53 GND#54 GND#55 GND#56 GND#57 GND#58 GND#59 GND#60 GND/PX_EN#61 GND#62 GND#63 GND#64 GND#65 GND#66 GND#67 GND#68 GND#69 GND#70 GND#71 GND#72 GND#73 GND#74 GND#75 GND#76 GND#77 GND#78 GND GND#80 GND#81 GND#82 GND#83 GND#84 GND#85 GND#86 GND#87 GND#88 GND#89 GND#90 GND#91 GND#92 GND#93 GND#94 GND#95 GND#96 GND#97 GND#98 GND#99 A3 A37 AA16 AA18 AA2 AA21 AA23 AA26 AA28 AA6 AB12 AB15 AB17 AB20 AB22 AB24 AB27 AC11 AC13 AC16 AC18 AC2 AC21 AC23 AC26 AC28 AC6 AD15 AD17 AD20 AD22 AD24 AD27 AD9 AE2 AE6 AF10 AF16 AF18 AF21 AG17 AG2 AG20 AG22 AG6 AG9 AH21 AJ10 AJ11 AJ2 AJ28 AJ6 AK11 AK31 AK7 AL11 AL14 AL17 AL2 AL20 AL21 AL23 AL26 AL32 AL6 AL8 AM11 AM31 AM9 AN11 AN2 AN30 AN6 AN8 AP11 AP7 AP9 AR5 B11 B13 B15 B17 B19 B21 B23 B25 B27 B29 B31 B33 B7 B9 C1 C39 E35 E5 F11 F13 [17] VGA_GPIO0 [17] VGA_GPIO1 [17] VGA_GPIO2 [17] VGA_GPIO8 [17] VGA_GPIO9 5/6: Add pu down for GPIO table [17] VGA_GPIO13 [17] VGA_GPIO12 [17] VGA_GPIO11 [17] 2 +3V_VGA R107 10K/F_4 R110 10K/F_4 R405 *10K/F_4 R381 *10K/F_4 R75 *10K/F_4 R396 R406 *10K/F_4 10K/F_4 R61 R69 10K/F_4 *10K/F_4 R410 R409 CONFIGURATION STRAPS RECOMMENDED SETTINGS 0= DO NOT INSTALL RESISTOR 1 = INSTALL 10K RESISTOR X = DESIGN DEPENDANT NA = NOT APPLICABLE ALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE GPIOS ARE USED, THEY MUST NOT CONFLICT DURING RESET t PIN STRAPS TX_PWRS_ENB DESCRIPTION OF DEFAULT SETTINGS Transmitter Power Savings Enable GPIO0 1 0: 50% Tx output swing for mobile mode 1: full Tx output swing (Default setting for Desktop) PCI Express Transmitter De-emphasis Enable *10K/F_4 10K/F_4 TX_DEEMPH_EN GPIO1 BIF_GEN2_EN_A GPIO2 RSVD BIF_VGA_DIS RSVD GPIO8 GPIO9 GPIO21 D 1 0: Tx de-emphasis disabled for mobile mode 1: Tx de-emphasis enabled (Default setting for Desktop) 0 = Advertises the PCI-E device as 2.5 GT/s capable at power-on. 1 = Advertises the PCI-E device as 5.0 GT/s capable at power-on. 0 5.0 GT/s capability will be controlled by software. R392 VGA_GPIO10 add GPIO10 for EEPROM *10K/F_4 4/23. [17] GENERICC R66 *10K/F_4 R393 10K/F_4 BIOS_ROM_EN [17] VGA_GPIO22 [17,24] GPU_VSYNC [17,24] GPU_HSYNC [17] VSYNC_DAC2 [17] HSYNC_DAC2 R484 10K/F_4 R489 10K/F_4 R119 *10K/F_4 R118 *10K/F_4 R343 R378 R379 [17,24] GPU_LVDS_BLON [17,42] GFX_CORE_CNTRL0 [17,42] GFX_CORE_CNTRL1 0 0 0 VGA ENABLED GPIO_22_ROMCSB ROMIDCFG(2:0) 5/6: Add for Enable EEPROM ENABLE EXTERNAL BIOS ROM GPIO[13:11] 0 SERIAL ROM TYPE OR MEMORY APERTURE SIZE SELECT VIP_DEVICE_STRAP_ENA V2SYNC RSVD AUD[1] AUD[0] GENERICC HSYNC VSYNC 0 0 1 IGNORE VIP DEVICE STRAPS 0 0 0 11 AUD[1] AUD[0] 0 0 No audio function 0 1 Audio for DisplayPort and HDMI if dongle is detected 1 0 Audio for DisplayPort only 1 1 Audio for both DisplayPort and HDMI 10K/F_4 3K/F_4 3K/F_4 5/10 add pu down by AMD request. +3V 27MHz + 100Mhz OSC Option C 5/10 modify 4/29 reserve PCH_CLK C551 Y3 2 TP60 R442 R437 10K/F_4 *10K/F_4 C543 6/23: SI modify 12P/50V_4 SS_SEL0 12P/50V_4 1 SS_SEL1 TP61 27MHZ R444 1M/F_4 R451 R452 10K/F_4 10K/F_4 R457 PX_EN_1 *0_4/S U28 +3V *0_4 [9] PCH_CLK_27M L7 +3V_VGA R461 1 1 2 HCB1608KF-181T15_6 4 8 C537 L4 1 C556 SS_SEL0 SS_SEL1 2 7 3 .1U/10V_4 *HCB1608KF-181T15_6 .1U/10V_4 6 2 11 Fghcwnv XTALIN XTALOUT VDD_100M VDD_27M 100M_OUT SS_SEL0 SS_SEL1 27M_OUT 10 5 CLK_100M_R 9 CLK_27M_R R449 *0_4/S GENERICA [17] R445 *0_4/S CLK_100M [17] R433 *0_4/S R435 *0_4/S GND_100M GND_27M GND_PAD C546 SL16010DCT 10P/50V_4 GPIO26_TCK [17] CLK_27M [17] C530 B 10P/50V_4 It is a shared pin strap with CONFIG[2:0] if BIOS_ROM_EN is set to 0. Tgugtxg"hqt"uwrrqtv"DCEQ"oqfg 4/19: change only from VGA PX_EN_1 R91 *0_4/S R92 *0_4 [35] [35] PX_EN R419 R428 GPUT_CLK GPUT_DATA *0_4/S *0_4/S [19] G_SMBCLK [17] G_SMBDAT [17] Vjgtocn"Ugpuqt +3V_VGA For PX_EN, refer to the BACO reference schematics for detail 781-1_3V R54 U6 R68 R67 +3V_VGA +3V_VGA Hqt"IFFT7"GGRTQO [17,35] VGA_ALERT R64 GPUT_CLK 8 SMCLK VCC 4.7K_4 GPUT_DATA 7 SMDATA DXP 2 DXN 3 -OVT 4 10K_4 VGA_ALERT R423 *0_4/S 6 -ALT 5 GND *200/F_6 C50 4.7K_4 +3V_VGA *0.1U/10V_4 1 GFX_THMD+ C527 *2200P/50V_4 GFX_THMD+ [17] w/s 10 / 10 GFX_THMD- GFX_THMD- [17] *G781-1P8@EV K4E"CFFTGUU<";CJ R383 4/20 DB update -VGATHRM R63 +3V_VGA *10K_4 A 10K/F_4 U22 VSS_MECH#1 VSS_MECH#2 VSS_MECH#3 A39 AW1 AW39 [17] [17] [17] [17] VGA_GPIO22 VGA_GPIO10 VGA_GPIO9 VGA_GPIO8 +3V_VGA Capilano Pro/Robson_M2 6/23: SI modify R384 R367 R368 R385 R387 TP62 TP63 33_4 33_4 33_4 33_4 1 6 5 2 10K/F_4 3 CE# SCK SI SO WP# VDD 8 RTQLGEV"<"NZ517*Jwtqp"Tkxgt+ Swcpvc"Eqorwvgt"Kpe0 HOLD# 7 C490 VSS 4 0.1U/10V_4 [16,17,19,27,42] +3V_VGA PD7 Size Custom Document Number 4 3 2 Rev 1A ATI CAPILANO-PRO(GD&Str)4/5 Date: Wednesday, October 13, 2010 5 3: 1 1 Sheet 18 of 47 5 4 3 2 MEM I/O D C610 10U/6.3V_8 + + C41 C753 C117 22U/6.3VS_8 C191 C752 22U/6.3VS_8 22U/6.3VS_8 2 330u_2.5V_3528 C320 10U/6.3V_8 2 330u_2.5V_3528 C763 10U/6.3V_8 1 1 C733 2.2U/6.3V_4 +1.8V_VDDC_CT VDDC#1 VDDC#2 VDDC#3 VDDC#4 VDDC#5 VDDC#6 VDDC#7 VDDC#8 VDDC#9 VDDC#10 VDDC#11 VDDC#12 VDDC#13 VDDC#14 VDDC#15 VDDC#16 VDDC#17 VDDC#18 VDDC#19 VDDC#20 VDDC#21 VDDC#22 VDDC#23 VDDC#24 VDDC#25 VDDC#26 VDDC#27 VDDC#28 VDDC#29 VDDC#30 VDDC#31 VDDC#32 VDDC#33 VDDC#34 VDDC#35 VDDC#36 VDDC#37 VDDC#38 VDDC#39 VDDC#40 VDDC#41 VDDC#42 VDDC#43 VDDC#44 VDDC#45 VDDC#46 VDDC#47 VDDC#48 VDDC#49 VDDC#50 VDDC#51 VDDC#52 VDDC#53 VDDC#54 VDDC#55 VDDC#56 VDDC#57 VDDC#58 AA15 AA17 AA20 AA22 AA24 AA27 AB16 AB18 AB21 AB23 AB26 AB28 AC17 AC20 AC22 AC24 AC27 AD18 AD21 AD23 AD26 AF17 AF20 AF22 AG16 AG18 AG21 AH22 AH27 AH28 M26 N24 N27 R18 R21 R23 R26 T17 T20 T22 T24 T27 U16 U18 U21 U23 U26 V17 V20 V22 V24 V27 Y16 Y18 Y21 Y23 Y26 Y28 HCB1608KF-181T15/1.5A_6 L17 HCB1608KF-181T15/1.5A_6 AF26 AF27 AG26 AG27 +VDDR4 C VDDCI#1 VDDCI#2 VDDCI#3 VDDCI#4 VDDCI#5 VDDCI#6 VDDCI#7 VDDCI#8 VDDCI#9 VDDCI#10 VDDCI#11 VDDCI#12 VDDCI#13 VDDCI#14 ISOLATED VDDCI#15 CORE I/O VDDCI#16 VDDCI#17 VDDCI#18 VDDCI#19 VDDCI#20 VDDCI#21 VDDCI#22 AA13 AB13 AC12 AC15 AD13 AD16 M15 M16 M18 M23 N13 N15 N17 N20 N22 R12 R13 R16 T12 T15 V15 Y13 LEVEL TRANSLATION (1.8V@136mA VDD_CT) C57 10U/6.3V_8 C140 1U/6.3V_4 C137 0.1U/10V_4 VDD_CT#1 VDD_CT#2 VDD_CT#3 VDD_CT#4 I/O SI Change BOM C171 C142 10U/6.3VS_6 1U/6.3V_4 (3.3V@60mA VDDR3) C139 0.1U/10V_4 C379 10U/6.3V_8 +MPV18 L20 HCB1608KF-181T15/1.5A_6 SI Change BOM AF23 AF24 AG23 AG24 +3V_VGA +VDDR4 C489 1U/6.3V_4 AF13 AF15 AG13 AG15 VDDR4 for DVPDATA[12..23] C322 1U/6.3V_4 C325 10U/6.3VS_6 +VDDR4 C327 0.1U/10V_4 (VDDR4_5 : 1.8V@20/170mA) AD12 AF11 AF12 AG11 VDDR5 for DVPDATA[0..11] VDDR3#1 VDDR3#2 VDDR3#3 VDDR3#4 POWER L10 VDDR4#4 VDDR4#5 VDDR4#7 VDDR4#8 VDDR4#1 VDDR4#2 VDDR4#3 VDDR4#6 +SPV18 L33 HCB1608KF-181T15/1.5A_6 SI Change BOM C77 10U/6.3V_8 M20 M21 C536 1U/6.3V_4 C80 0.1U/10V_4 V12 U12 NC_VDDRHA NC_VSSRHA NC_VDDRHB NC_VSSRHB B L39 HCB1608KF-181T15/1.5A_6 PLL (1.8V@40mA PCIE_PVDD) +PCIE_PVDD AB37 +MPV18 SI Change BOM C595 10U/6.3V_8 C615 1U/6.3V_4 C614 1U/6.3V_4 H7 H8 SI Change BOM L32 AM10 HCB1608KF-181T15/1.5A_6 +SPV10 AN9 AN10 } +5V +3V 3 *0_4 Q9 *2N7002 2 Q42 *2N7002 2 SPV10 SPVSS AF28 FB_VDDC AG28 FB_VDDCI Q40 *2N7002 AH29 FB_GND SI Del R46 1 R88 C538 0.1U/10V_4 SPV18 3 3 PX_EN 1 [18] PX_MODE MPV18#1 MPV18#2 VOLTAGE SENESE PX_EN## PX_EN# Q5 *2N7002 2 C81 1U/6.3V_4 R34 *1K_4 R36 *1K_4 R41 *10K_4 [47] C33 10U/6.3V_8 +5V ラ "0#1j"cラSW PCIE_PVDD A PX_EN## C150 2.2U/6.3V_4 C182 2.2U/6.3V_4 C183 2.2U/6.3V_4 C236 2.2U/6.3V_4 2 1 C248 1U/6.3V_4 C216 2.2U/6.3V_4 + C229 2.2U/6.3V_4 C184 2.2U/6.3V_4 C237 C534 2.2U/6.3V_4 *330u_2.5V_3528 C241 2.2U/6.3V_4 C250 10U/6.3V_8 C199 2.2U/6.3V_4 C181 2.2U/6.3V_4 C220 2.2U/6.3V_4 C151 2.2U/6.3V_4 C200 2.2U/6.3V_4 C201 2.2U/6.3V_4 C209 2.2U/6.3V_4 C194 2.2U/6.3V_4 C185 2.2U/6.3V_4 C221 2.2U/6.3V_4 C235 2.2U/6.3V_4 C C203 10U/6.3VS_6 C228 22U/6.3VS_8 C214 10U/6.3VS_6 SI MODIFY C230 10U/6.3VS_6 + C535 SI ADD C135 C192 C173 10U/6.3VS_6 10U/6.3VS_6 10U/6.3VS_6 SI MODIFY C152 C188 10U/6.3VS_610U/6.3VS_6 SI ADD BIF_VDDC BIF_VDDC R556 *0_4/S +VGACORE C725 For non-BACO designs, connect BIF_VDDC to VDDC. For BACO designs - see BACO reference schematics (ref138) C720 C217 C205 *10U/6.3VS_6 *2.2U/6.3V_4 *10U/6.3VS_6 *2.2U/6.3V_4 4/20 DB add. B (For MP7, 1.12V@4A VDDCI). +VGACORE VDDCI L30 UPB201212T-121Y-N/5A_8 SI Change BOM C251 2.2U/6.3V_4 C252 2.2U/6.3V_4 C196 1U/6.3V_4 C234 2.2U/6.3V_4 C240 2.2U/6.3V_4 SI MODIFY and ADD + C253 C44 C533 BIF_VDDC *2N7002 D +VGACORE C219 2.2U/6.3V_4 22U/6.3VS_8 22U/6.3VS_8 22U/6.3VS_8 Q41 +VGACORE C257 1U/6.3V_4 3 PX_EN# Change BOM +1.0V_VGA C723 *22U/6.3VS_8 A C510 22U/6.3VS_8 RTQLGEV"<"NZ517*Jwtqp"Tkxgt+ Swcpvc"Eqorwvgt"Kpe0 [15,17,43] +1.0V_VGA [42] +VGACORE [16,20,21,22,23,47] +1.5V_VGA [15,17,42] +1.8V_VGA 3 2 1 1 C129 SI 10U/6.3V_8 (1.0V@2000mA PCIE_VDDC) C218 0.1U/10V_4 C43 Capilano Pro/Robson_M2 +1.0V_VGA C148 1U/6.3V_4 +SPV18 (SPV10 :1.0V@120mA) +1.0V_VGA G30 G31 H29 H30 J29 J30 L28 M28 N28 R28 T28 U28 CORE +1.8V_VGA SI Change BOM PCIE_VDDC#1 PCIE_VDDC#2 PCIE_VDDC#3 PCIE_VDDC#4 PCIE_VDDC#5 PCIE_VDDC#6 PCIE_VDDC#7 PCIE_VDDC#8 PCIE_VDDC#9 PCIE_VDDC#10 PCIE_VDDC#11 PCIE_VDDC#12 C138 1U/6.3V_4 1 C749 2.2U/6.3V_4 2 C608 2.2U/6.3V_4 C162 2.2U/6.3V_4 HCB1608KF-181T15/1.5A_6 L15 (1.8V@500mA PCIE_VDDR) +1.8V_PCIE_VDDR 1 C159 2.2U/6.3V_4 C739 2.2U/6.3V_4 AA31 AA32 AA33 AA34 V28 W29 W30 Y31 2 C165 2.2U/6.3V_4 C741 1U/6.3V_4 PCIE_VDDR#1 PCIE_VDDR#2 PCIE_VDDR#3 PCIE_VDDR#4 PCIE_VDDR#5 PCIE_VDDR#6 PCIE_VDDR#7 PCIE_VDDR#8 *330u_2.5V_3528 C348 2.2U/6.3V_4 VDDR1#1 VDDR1#2 VDDR1#3 VDDR1#4 VDDR1#5 VDDR1#6 VDDR1#7 VDDR1#8 VDDR1#9 VDDR1#10 VDDR1#11 VDDR1#12 VDDR1#13 VDDR1#14 VDDR1#15 VDDR1#16 VDDR1#17 VDDR1#18 VDDR1#19 VDDR1#20 VDDR1#21 VDDR1#22 VDDR1#23 VDDR1#24 VDDR1#25 VDDR1#26 VDDR1#27 VDDR1#28 VDDR1#29 VDDR1#30 VDDR1#31 VDDR1#32 VDDR1#33 VDDR1#34 1 C702 2.2U/6.3V_4 PCIE AC7 AD11 AF7 AG10 AJ7 AK8 AL9 G11 G14 G17 G20 G23 G26 G29 H10 J7 J9 K11 K13 K8 L12 L16 L21 L23 L26 L7 M11 N11 P7 R11 U11 U7 Y11 Y7 *330u_2.5V_3528 (VDDR1: 1.5V@9.1A ) C603 2.2U/6.3V_4 +1.8V_VGA 2 +1.5V_VGA 3; 1 U33E [16,17,18,27,42] +3V_VGA PD7 Size Custom Document Number ATI CAPILANO-PRO(POWER) 5/5 Date: Wednesday, October 13, 2010 5 4 3 2 1 Sheet 19 of 47 Rev 1A 5 4 3 2 42 1 1GB GDDR5 : CHANNEL A-0 (64M x 16) [16] DQA0_[31..0] [16] MAA0_[8..0] U39 U15 MAA0_7 K4 MAA0_6 K5 MAA0_5 K10 MAA0_4 K11 MAA0_3 H10 MAA0_2 H11 MAA0_1 H5 MAA0_0 H4 D [16] DBIA0_2 DBIA0_2 [16] DBIA0_0 DBIA0_0 +1.5V_VGA R558 [16] EDCA0_2 *0_4/S [16] EDCA0_0 [16] [16] [16] [16] RASA0# CASA0# CSA0# WEA0# EDCA0_2 C2 C13 EDCA0_0 R13 R2 RASA0# CASA0# CSA0# WEA0# G3 L3 G12 L12 MAA0_8 A5 J5 U5 0_4 J1 6/29: SI add R758 R551 [16,21,22,23] VM_RST# R760 [16] C C728 R553 +1.5V_VGA C738 R557 120_4 VM_RST# 0_4 1U/6.3V_4 2.37K_4 VREFC_VMA1 VREFD_VMA1 VREFD_VMAU1 +1.5V_VGA 1U/6.3V_4 5.49K_4 C765 1U/6.3V_4 R564 2.37K_4 J2 J10 J14 A10 U10 DQ0/DQ24 DQ1/DQ25 DQ2/DQ26 DQ3/DQ27 DQ4/DQ28 DQ5/DQ29 DQ6/DQ30 DQ7/DQ31 DBI0#/DBI3# DBI1#/DBI2# DBI2#/DBI1# DBI3#/DBI0# DQ8/DQ16 DQ9/DQ17 DQ10/DQ18 DQ11/DQ19 DQ12/DQ20 DQ13/DQ21 DQ14/DQ22 DQ15/DQ23 EDC0/EDC3 EDC1/EDC2 EDC2/EDC1 EDC3/EDC0 DQ16/DQ8 DQ17/DQ9 DQ18/DQ10 DQ19/DQ11 DQ20/DQ12 DQ21/DQ13 DQ22/DQ14 DQ23/DQ15 RAS#/CAS# CAS#/RAS# CS#/WE# WE#/CS# NC1 NC2 NC3 DQ24/DQ0 DQ25/DQ1 DQ26/DQ2 DQ27/DQ3 DQ28/DQ4 DQ29/DQ5 DQ30/DQ6 DQ31/DQ7 MF ZQ RESET# SEN ABI# VREFC WCK01/WCK23 WCK01#/WCK23# WCK23/WCK01 WCK23#/WCK01# CK# CK CKE# VREFD#A10 A4 A2 B4 B2 E4 E2 F4 F2 DQA0_16 DQA0_18 DQA0_19 DQA0_17 DQA0_20 DQA0_23 DQA0_21 DQA0_22 MF=1 Mirror A11 A13 B11 B13 E11 E13 F11 F13 U11 U13 T11 T13 N11 N13 M11 M13 [16] DBIA0_3 [16] DBIA0_1 [16] EDCA0_1 6/29: SI add U4 U2 T4 T2 N4 N2 M4 M2 +1.5V_VGA R759 J11 J12 J3 VM_RST# WCKA0_1 WCKA0_1# WCKA0_0 WCKA0_0# CLKA0# CLKA0 CKEA0# WCKA0_1 WCKA0_1# WCKA0_0 WCKA0_0# CLKA0# CLKA0 CKEA0# [16] [16] [16] [16] [16] [16] [16] 1U/6.3V_4 5.49K_4 VREFC_VMA2 J14 C336 R192 1U/6.3V_4 2.37K_4 VREFD_VMA2 A10 VREFD_VMAU2 C324 R184 1U/6.3V_4 2.37K_4 WCKA0_1 WCKA0_1# WCKA0_0 WCKA0_0# J11 J12 J3 CLKA0# CLKA0 CKEA0# C VREFD#U10 +1.5V_VGA C767 C769 10U/6.3V_8 10U/6.3V_8 A1 A3 C1 C3 C4 E1 E3 F5 H2 K2 M5 N1 N3 R1 R3 R4 U1 U3 A12 A14 C11 C12 C14 E12 E14 F10 H13 K13 M10 N12 N14 R11 R12 R14 U12 U14 1U/6.3V_4 +1.5V_VGA B C328 C346 C321 1U/6.3V_4 1U/6.3V_4 10U/6.3V_8 10U/6.3V_8 VSSQ#A1 VSSQ#A3 VSSQ#C1 VSSQ#C3 VSSQ#C4 VSSQ#E1 VSSQ#E3 VSSQ#F5 VSSQ#H2 VSSQ#K2 VSSQ#M5 VSSQ#N1 VSSQ#N3 VSSQ#R1 VSSQ#R3 VSSQ#R4 VSSQ#U1 VSSQ#U3 VSSQ#A12 VSSQ#A14 VSSQ#C11 VSSQ#C12 VSSQ#C14 VSSQ#E12 VSSQ#E14 VSSQ#F10 VSSQ#H13 VSSQ#K13 VSSQ#M10 VSSQ#N12 VSSQ#N14 VSSQ#R11 VSSQ#R12 VSSQ#R14 VSSQ#U12 VSSQ#U14 2.2U/10V_4 K4G52324FG A 170-BALL SDRAM GDDR5 +1.5V_VGA B5 G5 H1 K1 L5 T5 B10 D10 G10 H14 K14 L10 P10 T10 C326 +1.5V_VGA VDDQ#B1 VDDQ#B3 VDDQ#D1 VDDQ#D3 VDDQ#E5 VDDQ#F1 VDDQ#F3 VDDQ#G2 VDDQ#H3 VDDQ#K3 VDDQ#L2 VDDQ#M1 VDDQ#M3 VDDQ#N5 VDDQ#P1 VDDQ#P3 VDDQ#T1 VDDQ#T3 VDDQ#B12 VDDQ#B14 VDDQ#D12 VDDQ#D14 VDDQ#E10 VDDQ#F12 VDDQ#F14 VDDQ#G13 VDDQ#H12 VDDQ#K12 VDDQ#L13 VDDQ#M12 VDDQ#M14 VDDQ#N10 VDDQ#P12 VDDQ#P14 VDDQ#T12 VDDQ#T14 K4G52324FG VSS#B5 VSS#G5 VSS#H1 VSS#K1 VSS#L5 VSS#T5 VSS#B10 VSS#D10 VSS#G10 VSS#H14 VSS#K14 VSS#L10 VSS#P10 VSS#T10 C351 B1 B3 D1 D3 E5 F1 F3 G2 H3 K3 L2 M1 M3 N5 P1 P3 T1 T3 B12 B14 D12 D14 E10 F12 F14 G13 H12 K12 L13 M12 M14 N10 P12 P14 T12 T14 VDD#C5 VDD#G1 VDD#G4 VDD#L1 VDD#L4 VDD#R5 VDD#C10 VDD#D11 VDD#G11 VDD#G14 VDD#L11 VDD#L14 VDD#P11 VDD#R10 C737 C5 G1 G4 L1 L4 R5 C10 D11 G11 G14 L11 L14 P11 R10 2.2U/10V_4 60.4_4 CK# CK CKE# VREFD#A10 D4 D5 P4 P5 2.2U/10V_4 60.4_4 VREFC WCK01/WCK23 WCK01#/WCK23# WCK23/WCK01 WCK23#/WCK01# C352 R201 CLKA0# R202 CLKA0 1U/6.3V_4 2.37K_4 ABI# 2.2U/10V_4 A1 A3 C1 C3 C4 E1 E3 F5 H2 K2 M5 N1 N3 R1 R3 R4 U1 U3 A12 A14 C11 C12 C14 E12 E14 F10 H13 K13 M10 N12 N14 R11 R12 R14 U12 U14 1U/6.3V_4 5.49K_4 C761 R200 SEN 1U/6.3V_4 +1.5V_VGA C353 R199 U10 RESET# C338 VSSQ#A1 VSSQ#A3 VSSQ#C1 VSSQ#C3 VSSQ#C4 VSSQ#E1 VSSQ#E3 VSSQ#F5 VSSQ#H2 VSSQ#K2 VSSQ#M5 VSSQ#N1 VSSQ#N3 VSSQ#R1 VSSQ#R3 VSSQ#R4 VSSQ#U1 VSSQ#U3 VSSQ#A12 VSSQ#A14 VSSQ#C11 VSSQ#C12 VSSQ#C14 VSSQ#E12 VSSQ#E14 VSSQ#F10 VSSQ#H13 VSSQ#K13 VSSQ#M10 VSSQ#N12 VSSQ#N14 VSSQ#R11 VSSQ#R12 VSSQ#R14 VSSQ#U12 VSSQ#U14 1U/6.3V_4 5.49K_4 ZQ U4 U2 T4 T2 N4 N2 M4 M2 2.2U/10V_4 170-BALL SDRAM GDDR5 +1.5V_VGA C319 R181 DQ24/DQ0 DQ25/DQ1 DQ26/DQ2 DQ27/DQ3 DQ28/DQ4 DQ29/DQ5 DQ30/DQ6 DQ31/DQ7 MF DQA0_12 DQA0_9 DQA0_15 DQA0_8 DQA0_13 DQA0_10 DQA0_14 DQA0_11 C768 B VDDQ#B1 VDDQ#B3 VDDQ#D1 VDDQ#D3 VDDQ#E5 VDDQ#F1 VDDQ#F3 VDDQ#G2 VDDQ#H3 VDDQ#K3 VDDQ#L2 VDDQ#M1 VDDQ#M3 VDDQ#N5 VDDQ#P1 VDDQ#P3 VDDQ#T1 VDDQ#T3 VDDQ#B12 VDDQ#B14 VDDQ#D12 VDDQ#D14 VDDQ#E10 VDDQ#F12 VDDQ#F14 VDDQ#G13 VDDQ#H12 VDDQ#K12 VDDQ#L13 VDDQ#M12 VDDQ#M14 VDDQ#N10 VDDQ#P12 VDDQ#P14 VDDQ#T12 VDDQ#T14 B5 G5 H1 K1 L5 T5 B10 D10 G10 H14 K14 L10 P10 T10 NC1 NC2 NC3 U11 U13 T11 T13 N11 N13 M11 M13 C751 B1 B3 D1 D3 E5 F1 F3 G2 H3 K3 L2 M1 M3 N5 P1 P3 T1 T3 B12 B14 D12 D14 E10 F12 F14 G13 H12 K12 L13 M12 M14 N10 P12 P14 T12 T14 VSS#B5 VSS#G5 VSS#H1 VSS#K1 VSS#L5 VSS#T5 VSS#B10 VSS#D10 VSS#G10 VSS#H14 VSS#K14 VSS#L10 VSS#P10 VSS#T10 J4 C332 R191 DQ16/DQ8 DQ17/DQ9 DQ18/DQ10 DQ19/DQ11 DQ20/DQ12 DQ21/DQ13 DQ22/DQ14 DQ23/DQ15 RAS#/CAS# CAS#/RAS# CS#/WE# WE#/CS# A11 A13 B11 B13 E11 E13 F11 F13 C740 2.37K_4 J10 ADBIA0# +1.5V_VGA J2 EDC0/EDC3 EDC1/EDC2 EDC2/EDC1 EDC3/EDC0 D 2.2U/10V_4 R183 0_4 J13 DQ8/DQ16 DQ9/DQ17 DQ10/DQ18 DQ11/DQ19 DQ12/DQ20 DQ13/DQ21 DQ14/DQ22 DQ15/DQ23 DQA0_29 DQA0_30 DQA0_26 DQA0_25 DQA0_27 DQA0_28 DQA0_24 DQA0_31 C732 1U/6.3V_4 J1 DBI0#/DBI3# DBI1#/DBI2# DBI2#/DBI1# DBI3#/DBI0# A4 A2 B4 B2 E4 E2 F4 F2 2.2U/10V_4 C323 A5 J5 U5 DQ0/DQ24 DQ1/DQ25 DQ2/DQ26 DQ3/DQ27 DQ4/DQ28 DQ5/DQ29 DQ6/DQ30 DQ7/DQ31 2.2U/10V_4 1U/6.3V_4 5.49K_4 MAA0_8 A8/A7_A10/A0 A11/A6_A9/A1 BA1/A5_BA3/A3 BA2/A4_BA0/A2 BA3/A3_BA1/A5 BA0/A2_BA2/A4 A9/A1_A11/A6 A10/A0_A8/A7 C736 C318 R180 G3 L3 G12 L12 120_4 R761 D4 D5 P4 P5 CASA0# RASA0# WEA0# CSA0# 0_4 R189 VREFD#U10 VDD#C5 VDD#G1 VDD#G4 VDD#L1 VDD#L4 VDD#R5 VDD#C10 VDD#D11 VDD#G11 VDD#G14 VDD#L11 VDD#L14 VDD#P11 VDD#R10 C2 C13 R13 R2 [16] EDCA0_3 *0_4/S R186 DQA0_5 DQA0_1 DQA0_4 DQA0_3 DQA0_6 DQA0_2 DQA0_7 DQA0_0 K4 K5 K10 K11 H10 H11 H5 H4 D2 D13 P13 P2 +1.5V_VGA +1.5V_VGA C5 G1 G4 L1 L4 R5 C10 D11 G11 G14 L11 L14 P11 R10 MAA0_0 MAA0_1 MAA0_3 MAA0_2 MAA0_5 MAA0_4 MAA0_6 MAA0_7 C764 +1.5V_VGA C766 R565 J13 ADBIA0# J4 ADBIA0# 1U/6.3V_4 5.49K_4 D2 D13 P13 P2 A8/A7_A10/A0 A11/A6_A9/A1 BA1/A5_BA3/A3 BA2/A4_BA0/A2 BA3/A3_BA1/A5 BA0/A2_BA2/A4 A9/A1_A11/A6 A10/A0_A8/A7 Change 1u to 2.2,for ATI Request 1212 A [16,19,21,22,23,47] +1.5V_VGA RTQLGEV"<"NZ517*Jwtqp"Tkxgt+ Swcpvc"Eqorwvgt"Kpe0 PD7 Size Custom Document Number 5 4 3 2 Rev 1A VRAM-A0 Date: Wednesday, October 13, 2010 1 Sheet 20 of 47 5 4 3 2 1 21 1GB GDDR5 : CHANNEL A-1 (64M x 16) [16] DQA1_[31..0] [16] MAA1_[8..0] U40 U16 MAA1_7 K4 MAA1_6 K5 MAA1_5 K10 MAA1_4 K11 MAA1_3 H10 MAA1_2 H11 MAA1_1 H5 MAA1_0 H4 D [16] DBIA1_0 DBIA1_0 [16] DBIA1_2 DBIA1_2 +1.5V_VGA R544 [16] EDCA1_0 *0_4/S [16] EDCA1_2 EDCA1_0 C2 C13 EDCA1_2 R13 R2 6/29: SI add R762 R552 R764 [16] C734 R554 C +1.5V_VGA C735 R555 RASA1# CASA1# CSA1# WEA1# G3 L3 G12 L12 MAA1_8 A5 J5 U5 0_4 120_4 [16,20,22,23] VM_RST# ADBIA1# VM_RST# 0_4 ADBIA1# VREFD_VMA3 VREFD_VMAU3 +1.5V_VGA 1U/6.3V_4 5.49K_4 C731 R550 1U/6.3V_4 2.37K_4 RAS#/CAS# CAS#/RAS# CS#/WE# WE#/CS# NC1 NC2 NC3 DQ24/DQ0 DQ25/DQ1 DQ26/DQ2 DQ27/DQ3 DQ28/DQ4 DQ29/DQ5 DQ30/DQ6 DQ31/DQ7 MF ZQ RESET# SEN ABI# VREFC WCK01/WCK23 WCK01#/WCK23# WCK23/WCK01 WCK23#/WCK01# CK# CK CKE# VREFD#A10 U11 U13 T11 T13 N11 N13 M11 M13 R193 DQA1_17 DQA1_18 DQA1_16 DQA1_19 DQA1_23 DQA1_22 DQA1_20 DQA1_21 for DB2 U4 U2 T4 T2 N4 N2 M4 M2 D4 D5 P4 P5 J11 J12 J3 [16] DBIA1_1 [16] DBIA1_3 [16] EDCA1_1 *0_4/S [16] EDCA1_3 [16] [16] [16] [16] CASA1# RASA1# WEA1# CSA1# +1.5V_VGA G3 L3 G12 L12 MAA1_8 A5 J5 U5 0_4 R190 120_4 R765 0_4 VM_RST# 6/29: SI add WCKA1_0 WCKA1_0# WCKA1_1 WCKA1_1# CLKA1# CLKA1 CKEA1# WCKA1_0 WCKA1_0# WCKA1_1 WCKA1_1# [16] [16] [16] [16] CLKA1# CLKA1 CKEA1# [16] [16] [16] ADBIA1# C329 R188 +1.5V_VGA C330 R187 1U/6.3V_4 5.49K_4 1U/6.3V_4 2.37K_4 VREFC_VMA4 VREFD_VMA4 VREFC_VMAU4 C345 R195 1U/6.3V_4 2.37K_4 RESET# SEN ABI# VREFC WCK01/WCK23 WCK01#/WCK23# WCK23/WCK01 WCK23#/WCK01# CK# CK CKE# VREFD#A10 U4 U2 T4 T2 N4 N2 M4 M2 D4 D5 P4 P5 WCKA1_0 WCKA1_0# WCKA1_1 WCKA1_1# J11 J12 J3 CLKA1# CLKA1 CKEA1# K4G52324FG CLKA1# R182 60.4_4 +1.5V_VGA +1.5V_VGA VDD#C5 VDD#G1 VDD#G4 VDD#L1 VDD#L4 VDD#R5 VDD#C10 VDD#D11 VDD#G11 VDD#G14 VDD#L11 VDD#L14 VDD#P11 VDD#R10 VDDQ#B1 VDDQ#B3 VDDQ#D1 VDDQ#D3 VDDQ#E5 VDDQ#F1 VDDQ#F3 VDDQ#G2 VDDQ#H3 VDDQ#K3 VDDQ#L2 VDDQ#M1 VDDQ#M3 VDDQ#N5 VDDQ#P1 VDDQ#P3 VDDQ#T1 VDDQ#T3 VDDQ#B12 VDDQ#B14 VDDQ#D12 VDDQ#D14 VDDQ#E10 VDDQ#F12 VDDQ#F14 VDDQ#G13 VDDQ#H12 VDDQ#K12 VDDQ#L13 VDDQ#M12 VDDQ#M14 VDDQ#N10 VDDQ#P12 VDDQ#P14 VDDQ#T12 VDDQ#T14 170-BALL SDRAM GDDR5 VSS#B5 VSS#G5 VSS#H1 VSS#K1 VSS#L5 VSS#T5 VSS#B10 VSS#D10 VSS#G10 VSS#H14 VSS#K14 VSS#L10 VSS#P10 VSS#T10 VSSQ#A1 VSSQ#A3 VSSQ#C1 VSSQ#C3 VSSQ#C4 VSSQ#E1 VSSQ#E3 VSSQ#F5 VSSQ#H2 VSSQ#K2 VSSQ#M5 VSSQ#N1 VSSQ#N3 VSSQ#R1 VSSQ#R3 VSSQ#R4 VSSQ#U1 VSSQ#U3 VSSQ#A12 VSSQ#A14 VSSQ#C11 VSSQ#C12 VSSQ#C14 VSSQ#E12 VSSQ#E14 VSSQ#F10 VSSQ#H13 VSSQ#K13 VSSQ#M10 VSSQ#N12 VSSQ#N14 VSSQ#R11 VSSQ#R12 VSSQ#R14 VSSQ#U12 VSSQ#U14 B5 G5 H1 K1 L5 T5 B10 D10 G10 H14 K14 L10 P10 T10 C161 10U/6.3V_8 B1 B3 D1 D3 E5 F1 F3 G2 H3 K3 L2 M1 M3 N5 P1 P3 T1 T3 B12 B14 D12 D14 E10 F12 F14 G13 H12 K12 L13 M12 M14 N10 P12 P14 T12 T14 60.4_4 C350 10U/6.3V_8 A1 A3 C1 C3 C4 E1 E3 F5 H2 K2 M5 N1 N3 R1 R3 R4 U1 U3 A12 A14 C11 C12 C14 E12 E14 F10 H13 K13 M10 N12 N14 R11 R12 R14 U12 U14 R185 VREFD#U10 +1.5V_VGA C5 G1 G4 L1 L4 R5 C10 D11 G11 G14 L11 L14 P11 R10 C CLKA1 C760 10U/6.3V_8 1U/6.3V_4 2.37K_4 ZQ C334 1U/6.3V_4 1U/6.3V_4 5.49K_4 C730 R549 U10 DQ24/DQ0 DQ25/DQ1 DQ26/DQ2 DQ27/DQ3 DQ28/DQ4 DQ29/DQ5 DQ30/DQ6 DQ31/DQ7 MF DQA1_26 DQA1_29 DQA1_27 DQA1_28 DQA1_25 DQA1_31 DQA1_24 DQA1_30 C357 10U/6.3V_8 C721 R546 A10 NC1 NC2 NC3 U11 U13 T11 T13 N11 N13 M11 M13 C340 1U/6.3V_4 +1.5V_VGA 1U/6.3V_4 5.49K_4 J14 DQ16/DQ8 DQ17/DQ9 DQ18/DQ10 DQ19/DQ11 DQ20/DQ12 DQ21/DQ13 DQ22/DQ14 DQ23/DQ15 RAS#/CAS# CAS#/RAS# CS#/WE# WE#/CS# C743 1U/6.3V_4 +1.5V_VGA C344 R194 J4 EDC0/EDC3 EDC1/EDC2 EDC2/EDC1 EDC3/EDC0 D A11 A13 B11 B13 E11 E13 F11 F13 C729 1U/6.3V_4 VSSQ#A1 VSSQ#A3 VSSQ#C1 VSSQ#C3 VSSQ#C4 VSSQ#E1 VSSQ#E3 VSSQ#F5 VSSQ#H2 VSSQ#K2 VSSQ#M5 VSSQ#N1 VSSQ#N3 VSSQ#R1 VSSQ#R3 VSSQ#R4 VSSQ#U1 VSSQ#U3 VSSQ#A12 VSSQ#A14 VSSQ#C11 VSSQ#C12 VSSQ#C14 VSSQ#E12 VSSQ#E14 VSSQ#F10 VSSQ#H13 VSSQ#K13 VSSQ#M10 VSSQ#N12 VSSQ#N14 VSSQ#R11 VSSQ#R12 VSSQ#R14 VSSQ#U12 VSSQ#U14 B5 G5 H1 K1 L5 T5 B10 D10 G10 H14 K14 L10 P10 T10 J2 J10 DQ8/DQ16 DQ9/DQ17 DQ10/DQ18 DQ11/DQ19 DQ12/DQ20 DQ13/DQ21 DQ14/DQ22 DQ15/DQ23 DQA1_9 DQA1_8 DQA1_11 DQA1_10 DQA1_12 DQA1_15 DQA1_13 DQA1_14 C333 2.2U/10V_4 170-BALL SDRAM GDDR5 VSS#B5 VSS#G5 VSS#H1 VSS#K1 VSS#L5 VSS#T5 VSS#B10 VSS#D10 VSS#G10 VSS#H14 VSS#K14 VSS#L10 VSS#P10 VSS#T10 J1 J13 DBI0#/DBI3# DBI1#/DBI2# DBI2#/DBI1# DBI3#/DBI0# A4 A2 B4 B2 E4 E2 F4 F2 +1.5V_VGA A1 A3 C1 C3 C4 E1 E3 F5 H2 K2 M5 N1 N3 R1 R3 R4 U1 U3 A12 A14 C11 C12 C14 E12 E14 F10 H13 K13 M10 N12 N14 R11 R12 R14 U12 U14 C331 2.2U/10V_4 VDDQ#B1 VDDQ#B3 VDDQ#D1 VDDQ#D3 VDDQ#E5 VDDQ#F1 VDDQ#F3 VDDQ#G2 VDDQ#H3 VDDQ#K3 VDDQ#L2 VDDQ#M1 VDDQ#M3 VDDQ#N5 VDDQ#P1 VDDQ#P3 VDDQ#T1 VDDQ#T3 VDDQ#B12 VDDQ#B14 VDDQ#D12 VDDQ#D14 VDDQ#E10 VDDQ#F12 VDDQ#F14 VDDQ#G13 VDDQ#H12 VDDQ#K12 VDDQ#L13 VDDQ#M12 VDDQ#M14 VDDQ#N10 VDDQ#P12 VDDQ#P14 VDDQ#T12 VDDQ#T14 CASA1# RASA1# WEA1# CSA1# R763 VREFD#U10 VDD#C5 VDD#G1 VDD#G4 VDD#L1 VDD#L4 VDD#R5 VDD#C10 VDD#D11 VDD#G11 VDD#G14 VDD#L11 VDD#L14 VDD#P11 VDD#R10 C2 C13 R13 R2 DQ0/DQ24 DQ1/DQ25 DQ2/DQ26 DQ3/DQ27 DQ4/DQ28 DQ5/DQ29 DQ6/DQ30 DQ7/DQ31 C727 2.2U/10V_4 C5 G1 G4 L1 L4 R5 C10 D11 G11 G14 L11 L14 P11 R10 D2 D13 P13 P2 +1.5V_VGA +1.5V_VGA B1 B3 D1 D3 E5 F1 F3 G2 H3 K3 L2 M1 M3 N5 P1 P3 T1 T3 B12 B14 D12 D14 E10 F12 F14 G13 H12 K12 L13 M12 M14 N10 P12 P14 T12 T14 B DQ16/DQ8 DQ17/DQ9 DQ18/DQ10 DQ19/DQ11 DQ20/DQ12 DQ21/DQ13 DQ22/DQ14 DQ23/DQ15 A11 A13 B11 B13 E11 E13 F11 F13 A8/A7_A10/A0 A11/A6_A9/A1 BA1/A5_BA3/A3 BA2/A4_BA0/A2 BA3/A3_BA1/A5 BA0/A2_BA2/A4 A9/A1_A11/A6 A10/A0_A8/A7 C337 2.2U/10V_4 1U/6.3V_4 2.37K_4 A10 U10 EDC0/EDC3 EDC1/EDC2 EDC2/EDC1 EDC3/EDC0 MAA1_0 K4 MAA1_1 K5 MAA1_3 K10 MAA1_2 K11 MAA1_5 H10 MAA1_4 H11 MAA1_6 H5 MAA1_7 H4 MF=1 Mirror C335 2.2U/10V_4 C758 R560 J14 DQ8/DQ16 DQ9/DQ17 DQ10/DQ18 DQ11/DQ19 DQ12/DQ20 DQ13/DQ21 DQ14/DQ22 DQ15/DQ23 DQA1_6 DQA1_4 DQA1_7 DQA1_3 DQA1_5 DQA1_0 DQA1_1 DQA1_2 C724 2.2U/10V_4 1U/6.3V_4 5.49K_4 J4 DBI0#/DBI3# DBI1#/DBI2# DBI2#/DBI1# DBI3#/DBI0# A4 A2 B4 B2 E4 E2 F4 F2 C349 2.2U/10V_4 C757 R559 J2 J10 DQ0/DQ24 DQ1/DQ25 DQ2/DQ26 DQ3/DQ27 DQ4/DQ28 DQ5/DQ29 DQ6/DQ30 DQ7/DQ31 C750 2.2U/10V_4 +1.5V_VGA C722 R547 J1 J13 1U/6.3V_4 5.49K_4 VREFC_VMA3 1U/6.3V_4 2.37K_4 D2 D13 P13 P2 A8/A7_A10/A0 A11/A6_A9/A1 BA1/A5_BA3/A3 BA2/A4_BA0/A2 BA3/A3_BA1/A5 BA0/A2_BA2/A4 A9/A1_A11/A6 A10/A0_A8/A7 B Change 1u to 2.2,for ATI Request 1212 K4G52324FG A A [16,19,20,22,23,47] RTQLGEV"<"NZ517*Jwtqp"Tkxgt+ Swcpvc"Eqorwvgt"Kpe0 +1.5V_VGA PD7 Size Custom Document Number 5 4 3 2 Rev 1A VRAM-A1 Date: Wednesday, October 13, 2010 1 Sheet 21 of 47 5 4 3 2 1 1GB GDDR5 : CHANNEL B-0 (64M x 16) [16] DQB0_[0..31] [16] MAB0_[0..8] 22 U36 U12 MAB0_7 K4 MAB0_6 K5 MAB0_5 K10 MAB0_4 K11 MAB0_3 H10 MAB0_2 H11 MAB0_1 H5 MAB0_0 H4 D [16] DBIB0_2 DBIB0_2 [16] DBIB0_0 DBIB0_0 [16] EDCB0_2 *0_4/S +1.5V_VGA R166 [16] EDCB0_0 [16] [16] [16] [16] RASB0# CASB0# CSB0# WEB0# EDCB0_2 C2 C13 EDCB0_0 R13 R2 RASB0# CASB0# CSB0# WEB0# G3 L3 G12 L12 MAB0_8 A5 J5 U5 6/29: SI add R767 R167 R769 [16] C C285 R168 +1.5V_VGA C281 R169 0_4 120_4 [16,20,21,23] VM_RST# ADBIB0# 0_4 ADBIB0# VREFD_VMB1 A10 U10 DQ8/DQ16 DQ9/DQ17 DQ10/DQ18 DQ11/DQ19 DQ12/DQ20 DQ13/DQ21 DQ14/DQ22 DQ15/DQ23 EDC0/EDC3 EDC1/EDC2 EDC2/EDC1 EDC3/EDC0 DQ16/DQ8 DQ17/DQ9 DQ18/DQ10 DQ19/DQ11 DQ20/DQ12 DQ21/DQ13 DQ22/DQ14 DQ23/DQ15 RAS#/CAS# CAS#/RAS# CS#/WE# WE#/CS# NC1 NC2 NC3 DQ24/DQ0 DQ25/DQ1 DQ26/DQ2 DQ27/DQ3 DQ28/DQ4 DQ29/DQ5 DQ30/DQ6 DQ31/DQ7 MF ZQ RESET# SEN ABI# VREFC WCK01/WCK23 WCK01#/WCK23# WCK23/WCK01 WCK23#/WCK01# CK# CK CKE# VREFD#A10 DQB0_21 DQB0_18 DQB0_20 DQB0_16 DQB0_19 DQB0_23 DQB0_17 DQB0_22 MF=1 Mirror A11 A13 B11 B13 E11 E13 F11 F13 U11 U13 T11 T13 N11 N13 M11 M13 R541 DQB0_2 DQB0_1 DQB0_3 DQB0_0 DQB0_6 DQB0_5 DQB0_7 DQB0_4 U4 U2 T4 T2 N4 N2 M4 M2 G3 L3 G12 L12 MAB0_8 A5 J5 U5 R766 0_4 R539 120_4 R768 0_4 VM_RST# ADBIB0# D4 D5 P4 P5 J11 J12 J3 WCKB0_1 WCKB0_1# WCKB0_0 WCKB0_0# CLKB0# CLKB0 CKEB0# WCKB0_1 WCKB0_1# WCKB0_0 WCKB0_0# CLKB0# CLKB0 CKEB0# [16] [16] [16] [16] [16] [16] [16] C703 R540 C711 R538 +1.5V_VGA 1U/6.3V_4 2.37K_4 VREFD_VMB2 +1.5V_VGA A10 1U/6.3V_4 5.49K_4 C698 R537 1U/6.3V_4 2.37K_4 C282 R174 1U/6.3V_4 5.49K_4 C286 R173 1U/6.3V_4 2.37K_4 ABI# VREFC WCK01/WCK23 WCK01#/WCK23# WCK23/WCK01 WCK23#/WCK01# CK# CK CKE# VREFD#A10 D4 D5 P4 P5 J11 J12 J3 WCKB0_1 WCKB0_1# WCKB0_0 WCKB0_0# CLKB0# CLKB0 CKEB0# C +1.5V_VGA VREFD#U10 +1.5V_VGA C5 G1 G4 L1 L4 R5 C10 D11 G11 G14 L11 L14 P11 R10 VDDQ#B1 VDDQ#B3 VDDQ#D1 VDDQ#D3 VDDQ#E5 VDDQ#F1 VDDQ#F3 VDDQ#G2 VDDQ#H3 VDDQ#K3 VDDQ#L2 VDDQ#M1 VDDQ#M3 VDDQ#N5 VDDQ#P1 VDDQ#P3 VDDQ#T1 VDDQ#T3 VDDQ#B12 VDDQ#B14 VDDQ#D12 VDDQ#D14 VDDQ#E10 VDDQ#F12 VDDQ#F14 VDDQ#G13 VDDQ#H12 VDDQ#K12 VDDQ#L13 VDDQ#M12 VDDQ#M14 VDDQ#N10 VDDQ#P12 VDDQ#P14 VDDQ#T12 VDDQ#T14 170-BALL SDRAM GDDR5 VSS#B5 VSS#G5 VSS#H1 VSS#K1 VSS#L5 VSS#T5 VSS#B10 VSS#D10 VSS#G10 VSS#H14 VSS#K14 VSS#L10 VSS#P10 VSS#T10 VSSQ#A1 VSSQ#A3 VSSQ#C1 VSSQ#C3 VSSQ#C4 VSSQ#E1 VSSQ#E3 VSSQ#F5 VSSQ#H2 VSSQ#K2 VSSQ#M5 VSSQ#N1 VSSQ#N3 VSSQ#R1 VSSQ#R3 VSSQ#R4 VSSQ#U1 VSSQ#U3 VSSQ#A12 VSSQ#A14 VSSQ#C11 VSSQ#C12 VSSQ#C14 VSSQ#E12 VSSQ#E14 VSSQ#F10 VSSQ#H13 VSSQ#K13 VSSQ#M10 VSSQ#N12 VSSQ#N14 VSSQ#R11 VSSQ#R12 VSSQ#R14 VSSQ#U12 VSSQ#U14 B5 G5 H1 K1 L5 T5 B10 D10 G10 H14 K14 L10 P10 T10 +1.5V_VGA A1 A3 C1 C3 C4 E1 E3 F5 H2 K2 M5 N1 N3 R1 R3 R4 U1 U3 A12 A14 C11 C12 C14 E12 E14 F10 H13 K13 M10 N12 N14 R11 R12 R14 U12 U14 C606 10U/6.3V_8 +1.5V_VGA B1 B3 D1 D3 E5 F1 F3 G2 H3 K3 L2 M1 M3 N5 P1 P3 T1 T3 B12 B14 D12 D14 E10 F12 F14 G13 H12 K12 L13 M12 M14 N10 P12 P14 T12 T14 VDD#C5 VDD#G1 VDD#G4 VDD#L1 VDD#L4 VDD#R5 VDD#C10 VDD#D11 VDD#G11 VDD#G14 VDD#L11 VDD#L14 VDD#P11 VDD#R10 C280 10U/6.3V_8 60.4_4 SEN C158 1U/6.3V_4 CLKB0# R163 RESET# U4 U2 T4 T2 N4 N2 M4 M2 C160 1U/6.3V_4 60.4_4 ZQ 2.2U/10V_4 R159 U10 DQ24/DQ0 DQ25/DQ1 DQ26/DQ2 DQ27/DQ3 DQ28/DQ4 DQ29/DQ5 DQ30/DQ6 DQ31/DQ7 MF DQB0_13 DQB0_10 DQB0_11 DQB0_12 DQB0_15 DQB0_8 DQB0_14 DQB0_9 C48 CLKB0 C691 R530 J4 J14 VREFD_VMBU2 +1.5V_VGA A1 A3 C1 C3 C4 E1 E3 F5 H2 K2 M5 N1 N3 R1 R3 R4 U1 U3 A12 A14 C11 C12 C14 E12 E14 F10 H13 K13 M10 N12 N14 R11 R12 R14 U12 U14 VREFC_VMB2 J2 J10 NC1 NC2 NC3 U11 U13 T11 T13 N11 N13 M11 M13 C604 10U/6.3V_8 B5 G5 H1 K1 L5 T5 B10 D10 G10 H14 K14 L10 P10 T10 1U/6.3V_4 5.49K_4 J1 J13 DQ16/DQ8 DQ17/DQ9 DQ18/DQ10 DQ19/DQ11 DQ20/DQ12 DQ21/DQ13 DQ22/DQ14 DQ23/DQ15 RAS#/CAS# CAS#/RAS# CS#/WE# WE#/CS# C609 2.2U/10V_4 VSSQ#A1 VSSQ#A3 VSSQ#C1 VSSQ#C3 VSSQ#C4 VSSQ#E1 VSSQ#E3 VSSQ#F5 VSSQ#H2 VSSQ#K2 VSSQ#M5 VSSQ#N1 VSSQ#N3 VSSQ#R1 VSSQ#R3 VSSQ#R4 VSSQ#U1 VSSQ#U3 VSSQ#A12 VSSQ#A14 VSSQ#C11 VSSQ#C12 VSSQ#C14 VSSQ#E12 VSSQ#E14 VSSQ#F10 VSSQ#H13 VSSQ#K13 VSSQ#M10 VSSQ#N12 VSSQ#N14 VSSQ#R11 VSSQ#R12 VSSQ#R14 VSSQ#U12 VSSQ#U14 CASB0# RASB0# WEB0# CSB0# EDC0/EDC3 EDC1/EDC2 EDC2/EDC1 EDC3/EDC0 C611 2.2U/10V_4 B VDDQ#B1 VDDQ#B3 VDDQ#D1 VDDQ#D3 VDDQ#E5 VDDQ#F1 VDDQ#F3 VDDQ#G2 VDDQ#H3 VDDQ#K3 VDDQ#L2 VDDQ#M1 VDDQ#M3 VDDQ#N5 VDDQ#P1 VDDQ#P3 VDDQ#T1 VDDQ#T3 VDDQ#B12 VDDQ#B14 VDDQ#D12 VDDQ#D14 VDDQ#E10 VDDQ#F12 VDDQ#F14 VDDQ#G13 VDDQ#H12 VDDQ#K12 VDDQ#L13 VDDQ#M12 VDDQ#M14 VDDQ#N10 VDDQ#P12 VDDQ#P14 VDDQ#T12 VDDQ#T14 C2 C13 R13 R2 C605 2.2U/10V_4 B1 B3 D1 D3 E5 F1 F3 G2 H3 K3 L2 M1 M3 N5 P1 P3 T1 T3 B12 B14 D12 D14 E10 F12 F14 G13 H12 K12 L13 M12 M14 N10 P12 P14 T12 T14 170-BALL SDRAM GDDR5 EDCB0_1 D A11 A13 B11 B13 E11 E13 F11 F13 C667 10U/6.3V_8 1U/6.3V_4 2.37K_4 EDCB0_3 *0_4/S [16] DQ8/DQ16 DQ9/DQ17 DQ10/DQ18 DQ11/DQ19 DQ12/DQ20 DQ13/DQ21 DQ14/DQ22 DQ15/DQ23 C167 1U/6.3V_4 C249 R150 [16] DBI0#/DBI3# DBI1#/DBI2# DBI2#/DBI1# DBI3#/DBI0# C522 1U/6.3V_4 1U/6.3V_4 5.49K_4 DBIB0_1 D2 D13 P13 P2 DQ0/DQ24 DQ1/DQ25 DQ2/DQ26 DQ3/DQ27 DQ4/DQ28 DQ5/DQ29 DQ6/DQ30 DQ7/DQ31 C607 2.2U/10V_4 C267 R155 VSS#B5 VSS#G5 VSS#H1 VSS#K1 VSS#L5 VSS#T5 VSS#B10 VSS#D10 VSS#G10 VSS#H14 VSS#K14 VSS#L10 VSS#P10 VSS#T10 [16] +1.5V_VGA VREFD#U10 VDD#C5 VDD#G1 VDD#G4 VDD#L1 VDD#L4 VDD#R5 VDD#C10 VDD#D11 VDD#G11 VDD#G14 VDD#L11 VDD#L14 VDD#P11 VDD#R10 DBIB0_3 6/29: SI add +1.5V_VGA C5 G1 G4 L1 L4 R5 C10 D11 G11 G14 L11 L14 P11 R10 [16] +1.5V_VGA A8/A7_A10/A0 A11/A6_A9/A1 BA1/A5_BA3/A3 BA2/A4_BA0/A2 BA3/A3_BA1/A5 BA0/A2_BA2/A4 A9/A1_A11/A6 A10/A0_A8/A7 C601 2.2U/10V_4 1U/6.3V_4 2.37K_4 J4 DBI0#/DBI3# DBI1#/DBI2# DBI2#/DBI1# DBI3#/DBI0# A4 A2 B4 B2 E4 E2 F4 F2 DQB0_24 DQB0_25 DQB0_27 DQB0_28 DQB0_31 DQB0_30 DQB0_26 DQB0_29 C602 2.2U/10V_4 +1.5V_VGA C283 R171 J10 DQ0/DQ24 DQ1/DQ25 DQ2/DQ26 DQ3/DQ27 DQ4/DQ28 DQ5/DQ29 DQ6/DQ30 DQ7/DQ31 A4 A2 B4 B2 E4 E2 F4 F2 C709 2.2U/10V_4 +1.5V_VGA 1U/6.3V_4 5.49K_4 J2 J14 VREFD_VMBU1 C284 R165 J1 J13 VM_RST# 1U/6.3V_4 5.49K_4 VREFC_VMB1 1U/6.3V_4 2.37K_4 D2 D13 P13 P2 A8/A7_A10/A0 A11/A6_A9/A1 BA1/A5_BA3/A3 BA2/A4_BA0/A2 BA3/A3_BA1/A5 BA0/A2_BA2/A4 A9/A1_A11/A6 A10/A0_A8/A7 MAB0_0 K4 MAB0_1 K5 MAB0_3 K10 MAB0_2 K11 MAB0_5 H10 MAB0_4 H11 MAB0_6 H5 MAB0_7 H4 B Change 1u to 2.2,for ATI Request 1212 K4G52324FG K4G52324FG A A RTQLGEV"<"NZ517*Jwtqp"Tkxgt+ Swcpvc"Eqorwvgt"Kpe0 [16,19,20,21,23,47] +1.5V_VGA PD7 +1.5V_VGA [16,19,20,21,23,47] Size Custom Document Number 5 4 3 2 Rev 1A VRAM-B0 Date: Wednesday, October 13, 2010 1 Sheet 22 of 47 5 4 3 2 1 23 1GB GDDR5 : CHANNEL B-1 (64M x 16) [16] DQB1_[0..31] [16] MAB1_[0..8] U8 U30 MAB1_7 K4 MAB1_6 K5 MAB1_5 K10 MAB1_4 K11 MAB1_3 H10 MAB1_2 H11 MAB1_1 H5 MAB1_0 H4 D [16] DBIB1_0 DBIB1_0 [16] DBIB1_2 DBIB1_2 [16] EDCB1_0 *0_4/S +1.5V_VGA R401 [16] EDCB1_0 C2 C13 EDCB1_2 R13 R2 EDCB1_2 6/29: SI add R771 R402 [16,20,21,22] [16] +1.5V_VGA MAB1_8 A5 J5 U5 0_4 C519 R403 1U/6.3V_4 5.49K_4 C513 R407 1U/6.3V_4 2.37K_4 J14 VREFD_VMB3 A10 VREFD_VMBU3 U10 RESET# SEN ABI# VREFC WCK01/WCK23 WCK01#/WCK23# WCK23/WCK01 WCK23#/WCK01# CK# CK CKE# VREFD#A10 R82 DQB1_16 DQB1_19 DQB1_17 DQB1_18 DQB1_21 DQB1_20 DQB1_23 DQB1_22 for DB2 U4 U2 T4 T2 N4 N2 M4 M2 G3 L3 G12 L12 MAB1_8 A5 J5 U5 R770 0_4 J1 R52 120_4 VM_RST# R772 0_4 ADBIB1# D4 D5 P4 P5 WCKB1_0 WCKB1_0# WCKB1_1 WCKB1_1# WCKB1_0 WCKB1_0# WCKB1_1 WCKB1_1# [16] [16] [16] [16] J11 J12 J3 CLKB1# CLKB1 CKEB1# CLKB1# CLKB1 CKEB1# [16] [16] [16] +1.5V_VGA 1U/6.3V_4 2.37K_4 +1.5V_VGA C518 R400 1U/6.3V_4 5.49K_4 C517 R399 +1.5V_VGA 1U/6.3V_4 2.37K_4 U10 CK# CK CKE# VREFD#A10 D4 D5 P4 P5 WCKB1_0 WCKB1_0# WCKB1_1 WCKB1_1# J11 J12 J3 CLKB1# CLKB1 CKEB1# CLKB1 R70 60.4_4 CLKB1# R65 60.4_4 C +1.5V_VGA +1.5V_VGA VREFD#U10 +1.5V_VGA C5 G1 G4 L1 L4 R5 C10 D11 G11 G14 L11 L14 P11 R10 VDD#C5 VDD#G1 VDD#G4 VDD#L1 VDD#L4 VDD#R5 VDD#C10 VDD#D11 VDD#G11 VDD#G14 VDD#L11 VDD#L14 VDD#P11 VDD#R10 170-BALL SDRAM GDDR5 +1.5V_VGA C212 C163 C168 C232 C164 2.2U/10V_4 2.2U/10V_4 1U/6.3V_4 10U/6.3V_8 10U/6.3V_8 A1 A3 C1 C3 C4 E1 E3 F5 H2 K2 M5 N1 N3 R1 R3 R4 U1 U3 A12 A14 C11 C12 C14 E12 E14 F10 H13 K13 M10 N12 N14 R11 R12 R14 U12 U14 2.2U/10V_4 VSSQ#A1 VSSQ#A3 VSSQ#C1 VSSQ#C3 VSSQ#C4 VSSQ#E1 VSSQ#E3 VSSQ#F5 VSSQ#H2 VSSQ#K2 VSSQ#M5 VSSQ#N1 VSSQ#N3 VSSQ#R1 VSSQ#R3 VSSQ#R4 VSSQ#U1 VSSQ#U3 VSSQ#A12 VSSQ#A14 VSSQ#C11 VSSQ#C12 VSSQ#C14 VSSQ#E12 VSSQ#E14 VSSQ#F10 VSSQ#H13 VSSQ#K13 VSSQ#M10 VSSQ#N12 VSSQ#N14 VSSQ#R11 VSSQ#R12 VSSQ#R14 VSSQ#U12 VSSQ#U14 B5 G5 H1 K1 L5 T5 B10 D10 G10 H14 K14 L10 P10 T10 2.2U/10V_4 VDDQ#B1 VDDQ#B3 VDDQ#D1 VDDQ#D3 VDDQ#E5 VDDQ#F1 VDDQ#F3 VDDQ#G2 VDDQ#H3 VDDQ#K3 VDDQ#L2 VDDQ#M1 VDDQ#M3 VDDQ#N5 VDDQ#P1 VDDQ#P3 VDDQ#T1 VDDQ#T3 VDDQ#B12 VDDQ#B14 VDDQ#D12 VDDQ#D14 VDDQ#E10 VDDQ#F12 VDDQ#F14 VDDQ#G13 VDDQ#H12 VDDQ#K12 VDDQ#L13 VDDQ#M12 VDDQ#M14 VDDQ#N10 VDDQ#P12 VDDQ#P14 VDDQ#T12 VDDQ#T14 K4G52324FG VSS#B5 VSS#G5 VSS#H1 VSS#K1 VSS#L5 VSS#T5 VSS#B10 VSS#D10 VSS#G10 VSS#H14 VSS#K14 VSS#L10 VSS#P10 VSS#T10 C166 B1 B3 D1 D3 E5 F1 F3 G2 H3 K3 L2 M1 M3 N5 P1 P3 T1 T3 B12 B14 D12 D14 E10 F12 F14 G13 H12 K12 L13 M12 M14 N10 P12 P14 T12 T14 A1 A3 C1 C3 C4 E1 E3 F5 H2 K2 M5 N1 N3 R1 R3 R4 U1 U3 A12 A14 C11 C12 C14 E12 E14 F10 H13 K13 M10 N12 N14 R11 R12 R14 U12 U14 VREFC WCK01/WCK23 WCK01#/WCK23# WCK23/WCK01 WCK23#/WCK01# 10U/6.3V_8 C102 R86 VREFD_VMBU4 ABI# C648 1U/6.3V_4 5.49K_4 A10 SEN 10U/6.3V_8 C87 R85 VREFD_VMB4 J14 RESET# C169 1U/6.3V_4 2.37K_4 J4 ZQ U4 U2 T4 T2 N4 N2 M4 M2 1U/6.3V_4 C60 R60 VREFC_VMB4 J10 DQ24/DQ0 DQ25/DQ1 DQ26/DQ2 DQ27/DQ3 DQ28/DQ4 DQ29/DQ5 DQ30/DQ6 DQ31/DQ7 MF DQB1_27 DQB1_30 DQB1_25 DQB1_29 DQB1_26 DQB1_28 DQB1_24 DQB1_31 C705 1U/6.3V_4 5.49K_4 J2 NC1 NC2 NC3 U11 U13 T11 T13 N11 N13 M11 M13 2.2U/10V_4 B5 G5 H1 K1 L5 T5 B10 D10 G10 H14 K14 L10 P10 T10 C54 R51 J13 DQ16/DQ8 DQ17/DQ9 DQ18/DQ10 DQ19/DQ11 DQ20/DQ12 DQ21/DQ13 DQ22/DQ14 DQ23/DQ15 RAS#/CAS# CAS#/RAS# CS#/WE# WE#/CS# 2.2U/10V_4 A VSSQ#A1 VSSQ#A3 VSSQ#C1 VSSQ#C3 VSSQ#C4 VSSQ#E1 VSSQ#E3 VSSQ#F5 VSSQ#H2 VSSQ#K2 VSSQ#M5 VSSQ#N1 VSSQ#N3 VSSQ#R1 VSSQ#R3 VSSQ#R4 VSSQ#U1 VSSQ#U3 VSSQ#A12 VSSQ#A14 VSSQ#C11 VSSQ#C12 VSSQ#C14 VSSQ#E12 VSSQ#E14 VSSQ#F10 VSSQ#H13 VSSQ#K13 VSSQ#M10 VSSQ#N12 VSSQ#N14 VSSQ#R11 VSSQ#R12 VSSQ#R14 VSSQ#U12 VSSQ#U14 CASB1# RASB1# WEB1# CSB1# EDC0/EDC3 EDC1/EDC2 EDC2/EDC1 EDC3/EDC0 A11 A13 B11 B13 E11 E13 F11 F13 C170 B VDDQ#B1 VDDQ#B3 VDDQ#D1 VDDQ#D3 VDDQ#E5 VDDQ#F1 VDDQ#F3 VDDQ#G2 VDDQ#H3 VDDQ#K3 VDDQ#L2 VDDQ#M1 VDDQ#M3 VDDQ#N5 VDDQ#P1 VDDQ#P3 VDDQ#T1 VDDQ#T3 VDDQ#B12 VDDQ#B14 VDDQ#D12 VDDQ#D14 VDDQ#E10 VDDQ#F12 VDDQ#F14 VDDQ#G13 VDDQ#H12 VDDQ#K12 VDDQ#L13 VDDQ#M12 VDDQ#M14 VDDQ#N10 VDDQ#P12 VDDQ#P14 VDDQ#T12 VDDQ#T14 170-BALL SDRAM GDDR5 CASB1# RASB1# WEB1# CSB1# C2 C13 R13 R2 DQ8/DQ16 DQ9/DQ17 DQ10/DQ18 DQ11/DQ19 DQ12/DQ20 DQ13/DQ21 DQ14/DQ22 DQ15/DQ23 D C272 B1 B3 D1 D3 E5 F1 F3 G2 H3 K3 L2 M1 M3 N5 P1 P3 T1 T3 B12 B14 D12 D14 E10 F12 F14 G13 H12 K12 L13 M12 M14 N10 P12 P14 T12 T14 VSS#B5 VSS#G5 VSS#H1 VSS#K1 VSS#L5 VSS#T5 VSS#B10 VSS#D10 VSS#G10 VSS#H14 VSS#K14 VSS#L10 VSS#P10 VSS#T10 [16] [16] [16] [16] +1.5V_VGA VREFD#U10 VDD#C5 VDD#G1 VDD#G4 VDD#L1 VDD#L4 VDD#R5 VDD#C10 VDD#D11 VDD#G11 VDD#G14 VDD#L11 VDD#L14 VDD#P11 VDD#R10 EDCB1_3 6/29: SI add +1.5V_VGA C5 G1 G4 L1 L4 R5 C10 D11 G11 G14 L11 L14 P11 R10 EDCB1_1 *0_4/S [16] DBI0#/DBI3# DBI1#/DBI2# DBI2#/DBI1# DBI3#/DBI0# DQB1_9 DQB1_10 DQB1_15 DQB1_8 DQB1_11 DQB1_13 DQB1_14 DQB1_12 C666 1U/6.3V_4 2.37K_4 VREFC_VMB3 ZQ [16] D2 D13 P13 P2 A4 A2 B4 B2 E4 E2 F4 F2 2.2U/10V_4 1U/6.3V_4 5.49K_4 C514 R408 J4 DQ24/DQ0 DQ25/DQ1 DQ26/DQ2 DQ27/DQ3 DQ28/DQ4 DQ29/DQ5 DQ30/DQ6 DQ31/DQ7 MF DBIB1_3 DQ0/DQ24 DQ1/DQ25 DQ2/DQ26 DQ3/DQ27 DQ4/DQ28 DQ5/DQ29 DQ6/DQ30 DQ7/DQ31 C704 C523 R404 ADBIB1# NC1 NC2 NC3 U11 U13 T11 T13 N11 N13 M11 M13 DBIB1_1 [16] +1.5V_VGA A8/A7_A10/A0 A11/A6_A9/A1 BA1/A5_BA3/A3 BA2/A4_BA0/A2 BA3/A3_BA1/A5 BA0/A2_BA2/A4 A9/A1_A11/A6 A10/A0_A8/A7 2.2U/10V_4 1U/6.3V_4 2.37K_4 J10 DQ16/DQ8 DQ17/DQ9 DQ18/DQ10 DQ19/DQ11 DQ20/DQ12 DQ21/DQ13 DQ22/DQ14 DQ23/DQ15 RAS#/CAS# CAS#/RAS# CS#/WE# WE#/CS# [16] K4 K5 K10 K11 H10 H11 H5 H4 C706 C516 R398 0_4 EDC0/EDC3 EDC1/EDC2 EDC2/EDC1 EDC3/EDC0 A11 A13 B11 B13 E11 E13 F11 F13 MAB1_0 MAB1_1 MAB1_3 MAB1_2 MAB1_5 MAB1_4 MAB1_6 MAB1_7 2.2U/10V_4 1U/6.3V_4 5.49K_4 J2 DQ8/DQ16 DQ9/DQ17 DQ10/DQ18 DQ11/DQ19 DQ12/DQ20 DQ13/DQ21 DQ14/DQ22 DQ15/DQ23 MF=1 Mirror DQB1_6 DQB1_5 DQB1_7 DQB1_1 DQB1_4 DQB1_3 DQB1_2 DQB1_0 C707 C515 R397 J13 VM_RST# ADBIB1# J1 DBI0#/DBI3# DBI1#/DBI2# DBI2#/DBI1# DBI3#/DBI0# A4 A2 B4 B2 E4 E2 F4 F2 2.2U/10V_4 +1.5V_VGA G3 L3 G12 L12 DQ0/DQ24 DQ1/DQ25 DQ2/DQ26 DQ3/DQ27 DQ4/DQ28 DQ5/DQ29 DQ6/DQ30 DQ7/DQ31 C708 +1.5V_VGA RASB1# CASB1# CSB1# WEB1# 120_4 VM_RST# R773 C D2 D13 P13 P2 A8/A7_A10/A0 A11/A6_A9/A1 BA1/A5_BA3/A3 BA2/A4_BA0/A2 BA3/A3_BA1/A5 BA0/A2_BA2/A4 A9/A1_A11/A6 A10/A0_A8/A7 B Change 1u to 2.2,for ATI Request 1212 A K4G52324FG [16,19,20,21,22,47] RTQLGEV"<"NZ517*Jwtqp"Tkxgt+ Swcpvc"Eqorwvgt"Kpe0 +1.5V_VGA PD7 Size Custom Document Number 5 4 3 2 Rev 1A VRAM-B1 Date: Wednesday, October 13, 2010 1 Sheet 23 of 47 A B C FOR DIS ONLY OPTION SIGNAL FROM NB to LVDS for DIS 4 GPU_TXLCLKOUT+ GPU_TXLCLKOUTGPU_TXLOUT0+ GPU_TXLOUT0GPU_TXLOUT1+ GPU_TXLOUT1GPU_TXLOUT2+ GPU_TXLOUT2- RP22 3 1 RP23 1 3 RP24 1 3 RP25 3 1 4 2 2 4 2 4 4 2 0_4P2R_4 0_4P2R_4 0_4P2R_4 0_4P2R_4 TXLCLKOUT+ TXLCLKOUTTXLOUT0+ TXLOUT0TXLOUT1+ TXLOUT1TXLOUT2+ TXLOUT2- TXLCLKOUT+ [25] TXLCLKOUT- [25] TXLOUT0+ [25] TXLOUT0- [25] TXLOUT1+ [25] TXLOUT1- [25] TXLOUT2+ [25] TXLOUT2- [25] OPTION Back Light SIGNAL FROM NB to LVDS for DIS [17,18] GPU_LVDS_BLON [17] GPU_DISP_ON RP27 GPU_LVDS_BLON 1 GPU_DISP_ON 3 0_4P2R_4 LVDS_BLON 2 DISP_ON 4 RP29 3 1 GPU_EDIDCLK GPU_EDIDDATA [17] GPU_DPST_PWM [35] PWM_VADJ GPU_DPST_PWM *0_4 0_4 0_4 CRT_R_CON GPU_CRT_G R777 0_4 CRT_G_CON [17] GPU_CRT_B GPU_CRT_B R778 0_4 CRT_B_CON 0_4P2R_4 HSYNC_COM 4 VSYNC_COM 2 9/26 :MV Modify CRT_R_CON [26] CRT_G_CON [26] CRT_B_CON [26] 4 HSYNC_COM [26] VSYNC_COM [26] RP28 GPU_DDCCLK 3 GPU_DDCDATA 1 0_4P2R_4 DDCCLK_COM 4 DDCDATA_COM 2 DDCCLK_COM [26] DDCDATA_COM [26] FOR UMA ONLY EDIDCLK [25] EDIDDATA [25] DPST_PWM *100K_4 *100K_4 *100K_4 OPTION SIGNAL FROM NB to CRT for DIS [17] GPU_DDCCLK [17] GPU_DDCDATA 0_4P2R_4 EDIDCLK 4 EDIDDATA 2 R752 GPU_CRT_R R776 [17] GPU_CRT_G LVDS_BLON [25] DISP_ON [25] OPTION SIGNAL FROM NB to LVDS for DIS [17] GPU_EDIDCLK [17] GPU_EDIDDATA [17] GPU_CRT_R RP26 GPU_HSYNC 3 GPU_VSYNC 1 R340 R8 R775 8/6 :PV Add OPTION SIGNAL FROM NB to CRT for DIS [17,18] GPU_HSYNC [17,18] GPU_VSYNC 46 E PCH_LVDS_BLON PCH_DISP_ON GPU_LVDS_BLON FOR DIS ONLY [17] GPU_TXLCLKOUT+ [17] GPU_TXLCLKOUT[17] GPU_TXLOUT0+ [17] GPU_TXLOUT0[17] GPU_TXLOUT1+ [17] GPU_TXLOUT1[17] GPU_TXLOUT2+ [17] GPU_TXLOUT2- D OPTION SIGNAL FROM NB to CRT for UMA DPST_PWM [25] R779 [7] PCH_CRT_R PCH_CRT_R R389 *0_4 CRT_R_CON [7] PCH_CRT_G PCH_CRT_G R388 *0_4 CRT_G_CON [7] PCH_CRT_B PCH_CRT_B R377 *0_4 CRT_B_CON [7] PCH_HSYNC [7] PCH_VSYNC PCH_HSYNC PCH_VSYNC 1 3 2 4 HSYNC_COM VSYNC_COM RP16 FOR UMA ONLY *0_4P2R_4 OPTION SIGNAL FROM NB to LVDS for UMA 3 [7] PCH_LA_CLK [7] PCH_LA_CLK# [7] PCH_LA_DATAP0 [7] PCH_LA_DATAN0 [7] PCH_LA_DATAP1 [7] PCH_LA_DATAN1 [7] PCH_LA_DATAP2 [7] PCH_LA_DATAN2 PCH_LA_CLK PCH_LA_CLK# PCH_LA_DATAP0 PCH_LA_DATAN0 PCH_LA_DATAP1 PCH_LA_DATAN1 PCH_LA_DATAP2 PCH_LA_DATAN2 RP6 1 3 3 1 3 1 1 3 RP3 RP4 RP5 2 4 4 2 4 2 2 4 *0_4P2R_4 TXLCLKOUT+ TXLCLKOUT*0_4P2R_4 TXLOUT0+ TXLOUT0*0_4P2R_4 TXLOUT1+ TXLOUT1*0_4P2R_4 TXLOUT2+ TXLOUT2- 5/11:for Layout modify 3 OPTION SIGNAL FROM NB to CRT for UMA [7] PCH_DDCCLK [7] PCH_DDCDATA PCH_DDCCLK PCH_DDCDATA RP17 1 3 *0_4P2R_4 DDCCLK_COM 2 DDCDATA_COM 4 OPTION Back Light SIGNAL FROM NB to LVDS for UMA RP1 [7] PCH_LVDS_BLON [7] PCH_DISP_ON [7] PCH_EDIDDATA [7] PCH_EDIDCLK PCH_LVDS_BLON PCH_DISP_ON PCH_EDIDDATA PCH_EDIDCLK *0_4P2R_4 4 LVDS_BLON DISP_ON 2 3 1 3 1 4 2 RP2 EDIDDATA EDIDCLK *0_4P2R_4 OPTION SIGNAL FROM NB to LVDS for UMA [7] PCH_DPST_PWM [35] PWM_VADJ PCH_DPST_PWM R353 *0_4 *0_4 DPST_PWM R780 FOR UMA/SG 2 2 FOR 17"DIS ONLY [17] GPU_TXUCLKOUT+ [17] GPU_TXUCLKOUT[17] GPU_TXUOUT0+ [17] GPU_TXUOUT0[17] GPU_TXUOUT1+ [17] GPU_TXUOUT1[17] GPU_TXUOUT2+ [17] GPU_TXUOUT2- GPU_TXUCLKOUT+ GPU_TXUCLKOUTGPU_TXUOUT0+ GPU_TXUOUT0GPU_TXUOUT1+ GPU_TXUOUT1GPU_TXUOUT2+ GPU_TXUOUT2- RP30 3 1 RP31 3 1 RP32 3 1 RP33 3 1 4 2 4 2 4 2 4 2 0_4P2R_4 0_4P2R_4 0_4P2R_4 0_4P2R_4 TXUCLKOUT+ TXUCLKOUTTXUOUT0+ TXUOUT0TXUOUT1+ TXUOUT1TXUOUT2+ TXUOUT2- TXUCLKOUT+ [25] TXUCLKOUT- [25] TXUOUT0+ [25] TXUOUT0- [25] TXUOUT1+ [25] TXUOUT1- [25] TXUOUT2+ [25] TXUOUT2- [25] FOR 17"UMA ONLY [7] PCH_LB_CLK [7] PCH_LB_CLK# [7] PCH_LB_DATAP0 [7] PCH_LB_DATAN0 [7] PCH_LB_DATAP1 [7] PCH_LB_DATAN1 [7] PCH_LB_DATAP2 [7] PCH_LB_DATAN2 PCH_LB_CLK PCH_LB_CLK# PCH_LB_DATAP0 PCH_LB_DATAN0 PCH_LB_DATAP1 PCH_LB_DATAN1 PCH_LB_DATAP2 PCH_LB_DATAN2 RP10 1 3 RP7 1 3 RP8 1 3 RP9 1 3 2 4 2 4 2 4 2 4 *0_4P2R_4 TXUCLKOUT+ TXUCLKOUT*0_4P2R_4 TXUOUT0+ TXUOUT0*0_4P2R_4 TXUOUT1+ TXUOUT1*0_4P2R_4 TXUOUT2+ TXUOUT2- 1 1 +3V +5V +1.8V [3,7,8,9,10,11,13,14,18,19,25,26,27,28,29,30,31,32,33,34,35,36,37,39,40,41,43,45,46,47] [7,8,11,19,25,26,27,29,30,32,34,36,37,45] [5,8,11,39,45] RTQLGEV"<"NZ517*Jwtqp"Tkxgt+ Swcpvc"Eqorwvgt"Kpe0 PD7 Size Custom Document Number A B C D Rev 1A SWITCHABLE Date: Wednesday, October 13, 2010 E Sheet 24 of 47 1 2 3 4 5 6 7 47 8 +3V +12VALW R25 1 1 3 Q24 AO3404 LCDONG +3VLCD EDIDCLK EDIDDATA L27 [24] [24] C468 1000P/50V_4 [24] [24] TXLOUT0TXLOUT0+ [24] [24] TXLOUT2TXLOUT2+ HCB2012KF-600T30/3A_8 SI Add BOM DIGITAL_CLK TXLOUT1TXLOUT1+ 3 C470 C469 *0.01U/25V_4 0.1U/10V_4 C475 10U/6.3V_8 C10 10P/50V_4 1 2 1 R349 22_8 [24] TXLCLKOUT[24] TXLCLKOUT+ C11 10P/50V_4 [24] TXUOUT0[24] TXUOUT0+ LCDDISCHG 3 C464 0.027U/25V_6 3 LCDON# [24] TXUOUT1[24] TXUOUT1+ Close to CN2 1 2 Q22 2N7002 [24] TXUOUT2[24] TXUOUT2+ Q25 2N7002 2 2 +5V 1 1 DISP_ON 41 +3VLCD_CON DIGITAL_D1 2 2 2 [24] [24] [24] +3V 1 R345 100K_4 Q23 PDTC144EU EDIDDATA 2.2K_4 R341 330K_6 +5VSUS A +3VLCD_CON C467 0.1U/10V_4 2 14.5v EDIDCLK 2.2K_4 R3 [24] TXUCLKOUT[24] TXUCLKOUT+ 75/F_6 [29] DIGITAL_D1 [29] DIGITAL_CLK R342 100K_4 C16 1000P/50V_4 [24] [9] [9] +LOGO_PWR1 DIGITAL_CLK_L SBK160808T-601Y-N/0.2A_6 L2 +3.9V_CAM 4 3 1 2 USBP4USBP4+ L21 DPST_PWM USBP4USBP4+ *WCM2012-90 BLON_CON B +VIN_BLIGHT C9 *4.7U/6.3V_6 +VIN_BLIGHT L1 UPB201209T-330Y-N/5A_8 C7 22P/50V_4 A 42 45 46 43 B CN3 GS12401-1011-9F +VIN_BLIGHT R334 4/29 modify 5/7 stuff R9079 R336 1K_4 R338 100K_4 D8 C8 *10U/25V_12 EMI Request BLON_CON 47K_4 *RB500V-40 LID_EC# +3VPCU [35,36] 5/7 : na D7 3 LVDS_BLON C3 C5 0.01U/25V_4 0.1U/50V_6 22P/50V_4 R333 [24] C1 0.1U/50V_6 RB500V-40 *0_4/S PN_BLON R335 100K_4 C458 D7 [35] LID_CONTROL C887 0.1U/50V_6 2 1 +VIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 44 R28 +3V [9] LCD_BK 2 +3VPCU Q3 *PDTC144EU +VIN +VIN +VIN C 1 C +5V C462 0.1U/10V_4 C496 *0.1U/25V_4 C12 *0.1U/25V_4 +3.9V_CAM C891 *0.1U/25V_4 U20 3 VIN 1 SHDN C457 1U/6.3V_4 [7,35] EC_PWROK PV EMI request VOUT R1 MV EMI Request 2 GND 4 SET C460 10U/6.3V_8 R337 *215K/F_4 C461 0.01U/25V_4 5 AP2128K-3.9TRG1 R339 *100K/F_4 R2 Vout=1.25(1+R1/R2) D D [3,7,8,9,10,11,13,14,18,19,26,27,28,29,30,31,32,33,34,35,36,37,39,40,41,43,45,46,47] +3V [7,8,11,19,26,27,29,30,32,34,36,37,45] +5V [31,38,39,41,42,43,44,45] +VIN [7,8,32,34,35,36,37,38,39,40,42,44,45,47] +3VPCU [34,37,42,44,45] +12VALW RTQLGEV"<"NZ517*Jwtqp"Tkxgt+ Swcpvc"Eqorwvgt"Kpe0 PD7 Size Custom Document Number Date: Wednesday, October 13, 2010 1 2 3 4 5 6 7 Rev 1A LCD CONN/LID function Sheet 25 8 of 47 4 3 C471 +5VCRT F1 2 +5V 10/13 PV2 EMI request 40 mils SI Change SSM14 spec is 40V 1A CRT_R_CON L29 BLM18BA470SN1D/0.3A_6 CRT_R1 [24] CRT_G_CON CRT_G_CON L28 BLM18BA470SN1D/0.3A_6 CRT_G1 [24] CRT_B_CON CRT_B_CON L26 BLM18BA470SN1D/0.3A_6 CRT_B1 [24] CRT_R_CON D R21 150/F_4 R12 150/F_4 C22 C20 *5.6P/16V_4 *5.6P/16V_4 *5.6P/16V_4 C478 C484 C488 5.6P/16V_4 5.6P/16V_4 5.6P/16V_4 6 1 7 2 8 3 9 4 10 5 11 D 12 13 14 15 17 R26 150/F_4 C25 48 1 ETV"RQTV 0.1U/10V_4 40 MIL +5VCRT 1 FUSE1A6V_POLY 2 16 5 CRT CONN CN19 SI2 EMI Request +3V +5V 8/13: PV Add R11 22_4 CRTVSYNC_2 R346 22_4 CRTHSYNC_2 R5 *0_4/S short0402 *0_4/S short0402 DDCCLK3 R350 C501 0.1U/10V_4 DDCDAT3 C15 C913 0.1U/10V_4 *220P/50V_4 ESD PROTECTION U4 C CRT_R1 CRT_G1 CRT_B1 1 2 3 4 5 6 7 8 VCC_SYNC VCC_VIDEO VIDEO_1 VIDEO_2 VIDEO_3 GND VCC_DDC BYP C45 0.22U/6.3V_4 SYNC_OUT2 SYNC_IN2 SYNC_OUT1 SYNC_IN1 DDC_OUT2 DDC_IN2 DDC_IN1 DDC_OUT1 16 15 14 13 12 11 10 9 CRTVSYNC_1 VSYNC_COM CRTHSYNC_1 HSYNC_COM DDCCLK2 DDCCLK_COM DDCDATA_COM DDCDAT2 C463 *470P/50V_4 VSYNC_COM [24] HSYNC_COM [24] C466 C473 10P/50V_4 *47P/50V_4 SI EMI Request C479 10P/50V_4 C SI EMI Request DDCCLK_COM [24] DDCDATA_COM [24] CM2009 R6 2.2K_4 D1 +5VCRT 2 R20 2.2K_4 RB501V-40 +5V_CRT2 1 B B +3V +5V [3,7,8,9,10,11,13,14,18,19,25,27,28,29,30,31,32,33,34,35,36,37,39,40,41,43,45,46,47] [7,8,11,19,25,27,29,30,32,34,36,37,45] A A RTQLGEV"<"NZ517*Jwtqp"Tkxgt+ Swcpvc"Eqorwvgt"Kpe0 PD7 Size Custom Document Number Date: Wednesday, October 13, 2010 5 4 3 2 Rev 1A CRT/HDMI Conn 1 Sheet 26 of 47 R473 0_4 HDMI_SDA_R [17] HDMI_SCL HDMI_SCL R468 0_4 HDMI_SCL_R TMDS_HPD 0_4 HDMI_DET_P 2 5/3 modify for AMD request R458 200K/F_4 2 1 1 HDMI_SCLK HDMI_SDATA R462 *200K/F_4 R413 10K_4 FKU1UI<"609M WOC<"404M HDMI_HPD_3V R474 R111 R122 4.7K_4 R121 0_4 +3V_VGA C_TX2_HDMI+ 8/16 PV modify C_TX2_HDMIC_TX1_HDMI+ 3 HDMI_SDATA FDV301N C_TX1_HDMIC_TX0_HDMI+ C_TX0_HDMIC_TXC_HDMI+ R475 +3V_HDMI2 4.7K_4 C_TXC_HDMI- 1 Q34 2A 3 HDMI_SCLK FDV301N +5V F2 FUSE1A6V_POLY 2 1 HDMI_SCLK_R HDMI_SDATA_R +5V_HDMVCC HDMI_HPD_L [7] SDVO_DATA R486 *0_4 HDMI_SDA_R [7] SDVO_CLK SDVO_CLK R487 *0_4 HDMI_SCL_R C_TX2_HDMI+ R500 C_TX1_HDMI+ R499 C_TX0_HDMI+ R494 C_TXC_HDMI+ R491 C_TXC_HDMIC_TXC_HDMI+ C_TX0_HDMIC_TX0_HDMI+ C_TX1_HDMIC_TX1_HDMI+ C_TX2_HDMIC_TX2_HDMI+ C_TX2_HDMI*100_4 C_TX1_HDMI*100_4 C_TX0_HDMI*100_4 C_TXC_HDMI*100_4 21 HDMI CONN B GOK HDMI_HPD R466 HDMI_HPD_3V 0_4 3 *0_4 +3V 1 Q37 2N7002K 2 R520 1 499/F_4 C_TX2_HDMI+ R508 499/F_4 C_TX2_HDMI- R507 499/F_4 C_TX1_HDMI+ R506 499/F_4 C_TX1_HDMI- R502 499/F_4 C_TX0_HDMI+ R504 499/F_4 C_TX0_HDMI- R516 499/F_4 C_TXC_HDMI+ R515 499/F_4 C_TXC_HDMI- 2 C115 0.1U/10V_4 1 +3V 3 2 R463 100K_4 A RTQLGEV"<"NZ517*Jwtqp"Tkxgt+ Swcpvc"Eqorwvgt"Kpe0 100K_4 C677 C572 0.1U/10V_4 HDMI_HPD_R 10K_4 D13 *BAV99W 8/11 PV Modify R782 R781 0.1U/10V_4 PD7 Size Custom Document Number 4 3 2 Rev 1A KB/POWER CONN Date: Wednesday, October 13, 2010 5 C +3V +5V R509 C134 0.1U/10V_4 20 C584 220P/50V_4 [35] HDMI_HPD C116 0.1U/10V_4 SHELL1 D2+ D2 Shield D2D1+ D1 Shield D1D0+ D0 Shield D0CK+ CK Shield CKCE Remote NC DDC CLK DDC DATA GND +5V HP DET SHELL2 4/20 DB update SDVO_DATA A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 PBY160808T-470Y-N/3A_6 L36 C190 C204 C210 C222 C243 C244 C268 C269 [7] HDMI_HPD_CON C172 *10P/50V_4 CN24 HDMI_HPD_R IN_CLK# IN_CLK IN_D0# IN_D0 IN_D1# IN_D1 IN_D2# IN_D2 *0_4 HDMI_SCLK_R HDMI_SDATA_R +3V 7/#"10.;"*&/+ HDMI_HPD_CON R418 D R128 2.2K_4 *0_4/S *0_4/S *0_4 1 Q33 HDMI_SCL_R *0.1U/10V_4 *0.1U/10V_4 *0.1U/10V_4 *0.1U/10V_4 *0.1U/10V_4 *0.1U/10V_4 *0.1U/10V_4 *0.1U/10V_4 R98 2.2K_4 R104 2 FKU1UI<"609M WOC<"404M IN_CLK# IN_CLK IN_D0# IN_D0 IN_D1# IN_D1 IN_D2# IN_D2 RB501V-40 C128 *10P/50V_4 HDMI_SDA_R [7] [7] [7] [7] [7] [7] [7] [7] C914 C717 RB501V-40 +5V_HDMVCC D14 5/10 modify for AMD request C B +5V_HDMVCC D21 HDMI_HPD 8/16 PV for EMI reserve 49 10/13 PV2 EMI request 1000P/50V_4 +3V_VGA 2 R421 0_4 1 C_TXC_HDMIC_TXC_HDMI+ C_TX0_HDMIC_TX0_HDMI+ C_TX1_HDMIC_TX1_HDMI+ C_TX2_HDMIC_TX2_HDMI+ 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 HDMI_SDA TMDS_HPD R439 10/13 PV2 EMI request [17] HDMI_SDA [17] +3V 9/26: MV Del C906,C914 9/26: MV Add D21 2 C618 C620 C624 C630 C637 C641 C649 C655 *0_4 1 +3V_HDMI2 N_TXC_HDMIN_TXC_HDMI+ N_TX0_HDMIN_TX0_HDMI+ N_TX1_HDMIN_TX1_HDMI+ N_TX2_HDMIN_TX2_HDMI+ N_TXC_HDMIN_TXC_HDMI+ N_TX0_HDMIN_TX0_HDMI+ N_TX1_HDMIN_TX1_HDMI+ N_TX2_HDMIN_TX2_HDMI+ R430 Q30 MMBT3904-7-F HDMI_HPD_3V [17] [17] [17] [17] [17] [17] [17] [17] 2 3 &+5マ5)"*&/+ D *&/+"%10 %1/ 3 1000P/50V_4 4 +3V_HDMI1 5 Sheet 1 27 of 47 7 *0_4/S C873 *5.6P/50V_4 C871 1 [9] [9] U47 RTS5138_RREF 1 2 3 4 5 RTS5138_VREG 6 USBP5USBP5+ +3V +3VCARD XD_D7 SP14 SP13 SP12 SP11 RTS5138_CLK_IN 2 *100P/50V_4 R729 6.19K/F_4 C848 1U/10V_4 3 SD_CLK R723 33_4 SP8 MS_CLK R704 33_4 SP1 2 SP1 SP2 SP3 SP4 SP5 SP6 SP7 SP8 SP9 SP10 SP11 SP12 SP13 SP14 For Layout change RREF SP10 DM GPIO0 DP SP9 RTS5138 SP8 3V3_IN CARD_3V3 SP7 V18 SP6 GND SP10 18 17 16 15 14 13 SP9 SP8 SP7 SP6 XD_CD# XD_RDY XD_RE# XD_CE# XD_CLE XD_ALE XD_WE# XD_WP XD_D0 XD_D1 XD_D2 XD_D3 XD_D4 XD_D5 XD_D6 XD_D7 4: 1 SD_WP MS_CLK MS_INS# SD_D1 SD_D0 SD_D7 SD_CD# SD_D6 SD_CLK SD_D5 SD_CMD SD_D4 SD_D3 SD_D2 MS_D3 MS_D2 MS_D0 D MS_D1 MS_BS Share Pin 7 8 9 10 11 12 25 4 24 23 22 21 20 19 D R734 5 CLK_IN XD_D7 SP14 SP13 SP12 SP11 [9] CLK_48M_CR 6 XD_CD# SP1 SP2 SP3 SP4 SP5 8 XD_CD# SP1 SP2 SP5 SP4 SP3 ENQUG"EP35 +3V +3VCARD +3VCARD +3VCARD C C MS_CLK_R SD_CLK_R C872 *10p/50V_4 C866 C443 2.2U/6.3V_6 *10p/50V_4 B +3VCARD +3VCARD C456 R733 C449 0.1U/10V_4 C441 0.1U/10V_4 C864 0.1U/10V_4 C863 4.7U/6.3V_6 C851 *0.1U/10V_4 C849 *0.1U/10V_4 C850 *0.1U/10V_4 B +3VCARD CN16 XD_RDY MS_CLK C455 0.1U/10V_4 XD,MMC/SD,MS/MSP 5 IN1 CARD READER *270P/25V_4 XD_RE# XD_CE# XD_CLE XD_ALE XD_WE# XD_WP XD_D0 XD_D1 SD_D2 SD_D3 SD_CMD R332 *10K_4 R326 150K/F_4 *0_4/S MS_CLK_R MS_D3 MS_INS# MS_D2 MS_D0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 XD-R/B XD-RE XD-CE XD-CLE XD-ALE XD-W E XD-W P XD-D0 XD-D1 SD-DAT2 SD-DAT3 SD-CMD 4IN1-GND1 MS-VCC MS-SCLK MS-DATA3 MS-INS MS-DATA2 MS-DATA0 A MS-DATA1 MS-BS 4IN1-GND2 SD-VCC SD-CLK SD-DAT0 XD-D2 XD-D3 XD-D4 SD-DAT1 XD-D5 XD-D6 XD-D7 XD-VCC XD-CD-SW SD-W P-SW SD-CD-SW 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 SHIELD1-GND SHIELD2-GND BOS BOS 37 38 39 40 MS_D1 MS_BS SD_CLK_R R735 SD_D0 XD_D2 XD_D3 XD_D4 SD_D1 XD_D5 XD_D6 XD_D7 *0_4/SSD_CLK XD_CD# SD_WP SD_CD# A +3V CARD READER SOCKET [3,7,8,9,10,11,13,14,18,19,25,26,27,29,30,31,32,33,34,35,36,37,39,40,41,43,45,46,47] 5 IN1 CARD-READER (PUSH-PUSH) RTQLGEV"<"NZ517*Jwtqp"Tkxgt+ Swcpvc"Eqorwvgt"Kpe0 Support SD/SD PRO/MMC/MS/MS PRO/xD Cards PD7 Size Custom Document Number Date: Wednesday, October 13, 2010 8 7 6 5 4 3 2 Rev 1A RTS5138 & CR SOCKET Sheet 28 1 of 47 A B C D [3,7,8,9,10,11,13,14,18,19,25,26,27,28,30,31,32,33,34,35,36,37,39,40,41,43,45,46,47] +3V [31] +4.75VAVDD [7,8,11,19,25,26,27,30,32,34,36,37,45] +5V 4; E SI Add for subwoofer noies +4.75VAVDD +5V U19 L24 >40mils trace +4.75VAVDD HCB1608KF-181T15/1.5A_6 2 Close to CODEC +3V_DVDD_CORE C825 C796 10U/6.3VS_6 1U/6.3V_4 +3V C817 0.1U/10V_4 C436 0.1U/10V_4 Del L48 C424 4.7U/6.3V_6 [8] ACZ_SDOUT_AUDIO [8] ACZ_SYNC_AUDIO 33_4 HD_SDIN0 R657 C810 R677 C819 *0_4/S HD_SDOUT *10P/50V_4 *0_4/S HD_SYNC *10P/50V_4 C803 10P/50V_4 R650 R655 DMIC_CLK_R 100_4 *0_4/S DMIC0 [8] ACZ_RST#_AUDIO VQ"Fkikvcn"OKE [25] DIGITAL_CLK [25] DIGITAL_D1 C804 IDT_GPIO0 1 DVDD_CORE 9 DVDD D19 6 8 5 DVDD_IO HDA_BITCLK HDA_SDI HDA_SDO 10 HDA_SYNC 11 HDA_RST# 2 4 46 10K_4 ADC_EAPD# VOLMUTE# RB500V-40 AVDD AVDD 27 38 PVDD PVDD 39 45 SPDIF_OUT_0 47 EAPD 7 DVSS 13 SENSE_A SENSE_B 14 SENSE_B HP0_PORT_A_L HP0_PORT_A_R VREFOUT_A_or_F 28 29 23 MIC_L MIC_R VREFOUT_A HP1_PORT_B_L 31 HPOUT_L HP1_PORT_B_R 32 PORT_C_L PORT_C_R VREFOUT_C 19 20 24 SPKR_PORT_D_L+ SPKR_PORT_D_L- 40 41 L_SPK+ L_SPK- SPKR_PORT_D_RSPKR_PORT_D_R+ 43 44 R_SPKR_SPK+ PORT_E_L PORT_E_R 15 16 PORT_F_L PORT_F_R 17 18 PC_BEEP 12 37 92HD80B1 C437 0.1U/10V_4 C431 0.047U/10V_4 C427 1U/6.3V_4 C413 0.1U/10V_4 C430 10U/6.3V_8 TPS793475 AGND R320 10K_4 +5V +5V >40mils trace C797 0.1U/10V_4 C790 10U/6.3VS_6 SENSE_B R674 2.49K/F_4 C429 1000P/50V_4 R671 100K/F_4 C814 *1000P/50V_4 MIC_L [30] VQ"Cwfkq"Lcem"OKE MIC_R [30] VREFOUT_A [30] AGND SHIELD HPOUT_L [30] HPOUT_R AGND SHIELD +5V_AVDD AGND +5V_AVDD AGND HPOUT_R [30] SI Del R518,R521 VQ"Jgcfrjqpg"lcem AGND SHIELD PV Change +5V to +5V_AVDD VQ"Kpvgtpcn"Urgcmgtu +5V_AVDD 1 Changed by IDT recommend C10625 close C10629, and C10625 close Chip R696 10K_4 C820 0.1U/10V_4 AMP_BEEP C834 0.1U/10V_4 AMP_BEEP_L R681 47K_4 AMP_BEEP_R2 3 MONO_OUT CAP2 DAP FOR EMI AGND 3 SENSE_A [30] BASS_OUT PV Del R239,R243, R678 10K_4 C821 0.1U/10V_4 25 PVSS 49 VREFFILT 42 Analog 22 AVSS AVSS AVSS V- C815 33P/50V_4 CAP+ 33 30 26 21 CAP+ 36 VREG 1 C801 4.7U/6.3V_6 CAP- 34 ACZ_SDIN0 C812 33P/50V_4 35 2 BIT_CLK_AUDIO EN SENSE_A SENSE_A DMIC1/GPIO0/SPDIF_OUT_1 CAP- Close to CODEC GND C423 1U/6.3V_4 AGND DMIC_CLK/GPIO1 DMIC0/GPIO2 48 Close to CODEC C793 1U/6.3V_4 [31] ADC_EAPD# 1 BYP 2 1 Vset=1.242V 10P/50V_4 R648 +3V [35] 4 Vin U45 Digital R664 [8] ACZ_SDIN0 JFC"Dwu *0_4/S HD_BCLK R660 [8] BIT_CLK_AUDIO C827 10U/6.3V_8 AGND 3 C805 0.1U/10V_4 Vout AGND AGND +3V C425 0.1U/10V_4 2 SPKR [8] R644 *0_4/S R698 *0_4/S R266 *0_4/S R622 *0_4/S 2N7002 Q46 1 C816 1U/6.3V_4 C792 10U/6.3VS_6 5 1 +5V_AVDD R10453 close R10454 BASS_OUT [31] 6/17 AGND AGND MUTE_LED +3V [37] MUTE_LED# ADC_CAP2 ADC_VREFFILT R672 *100K_4 ADC_V- High-->un-Mute ADC_VREG Low -->MUTE 1 AGND 10K_4 D18 3 BAT54A Q45 2N7002 C823 10U/6.3VS_6 C822 1U/6.3V_4 AGND AGND AGND EMI Request Close to CODEC AGND MUTE_LED_R 2 *0_4/S R725 *0_4/S PV EMI Request INT. SPEAKER INT SPEAKER CONN L_SPK+ L_SPKR_SPKR_SPK+ L59 L58 L57 L56 L_SPK+_R SBK160808T-221Y-N/0.2A_6 L_SPK-_R SBK160808T-221Y-N/0.2A_6 SBK160808T-221Y-N/0.2A_6 R_SPK-_R SBK160808T-221Y-N/0.2A_6 R_SPK+_R 1 C858 1000P/50V_4 1 IDT_GPIO0 2 R649 C802 10U/6.3VS_6 3 +3V VOLMUTE# 2 C794 4.7U/6.3V_6 R746 1 2 3 4 CN13 C859 1000P/50V_4 C860 1000P/50V_4 C861 1000P/50V_4 RTQLGEV"<"NZ517*Jwtqp"Tkxgt+ Swcpvc"Eqorwvgt"Kpe0 AGND PD7 Size Custom Document Number Date: Wednesday, October 13, 2010 A B C D Rev 2A Azalia 92HD80 E Sheet 29 of 47 1 2 3 4 5 6 7 52 8 Line out SI-2 Change AGND SHIELD AGND SHIELD AGND SHIELD A [29] HPOUT_L [29] HPOUT_R CN30 HPOUT_L R663 30.1/F_4 HPOUT_L1 L23 SBK160808T-301Y-N/0.2A_6 HPOUT_L2 HPOUT_R R653 30.1/F_4 HPOUT_R1 L22 SBK160808T-301Y-N/0.2A_6 HPOUT_R2 1 2 6 3 4 5 +5V 7 A 8 HP-JACK-GREEN R312 SENSE_A C417 150P/50V_4 SENSE_A [29] 3 Normal Close C811 C809 0.1U/10V_4 0.1U/10V_4 PV IDT Request 20K/F_4 R322 47K_4 C415 150P/50V_4 SENSE_PHONE AGND Q19 AGND SENSE_PHONE 2 5/6: modify 1 2N7002K AGND +5V VREFOUT_A [29] VREFOUT_A R285 39.2K/F_4 SENSE_A R643 4.7K_4 B R628 4.7K_4 C386 100P/50V_4 B AGND Q16 SENSE_MIC MIC C378 1U/6.3V_4 3 R284 47K_4 5/6: modify 2 [29] MIC_L [29] MIC_R MIC_L C787 2.2U/6.3V_6 AGND MIC_L1 L47 MIC_R C782 2.2U/6.3V_6 MIC_R1 L46 CN28 SBK160808T-301Y-N/0.2A_6MIC_IN_L SBK160808T-301Y-N/0.2A_6MIC_IN_R 1 2 6 3 4 5 2N7002K 1 AGND 7 8 C382 100P/50V_4 MIC-JACK-PINK AGND Normal Close AGND SENSE_MIC SGT-LIS302DLTR interrupt pin default is low / active Hi , BIOS need to programming 22h to change status from active Hi to low C Accelerometer Sensor C 6/23: SI Add +3V U34 *HP302DLTR8 1 6 C625 *10U/6.3V_8 C656 0.1U/10V_4 C663 0.1U/10V_4 3 11 U50 HP3DCTR +3V Vdd_IO VDD C226 *22P/50V_4 8 9 INTH# G_INT2# [9,14,35] MBDATA2 [9,14,35] MBCLK2 +3V R495 *10K_4 12 13 14 7 Vdd_IO VDD 11 9 INT1 INT2 7 6 4 SDO SDA SCL 8 CS NC NC 2 3 Reserved Reserved INTH# [9] [35] 1 14 INTH# G_INT2# INT1 INT2 SDO SDA/SDI/SDO SCL/SPC CS R756 GND GND GND GND *0_4/S MBDATA2 MBCLK2 2 4 5 10 +3V R757 *0_4/S RESERVED RESERVED RESERVED RESERVED 10 13 15 16 GND GND 5 12 D D Pin 12: Low 38hex Pin 12: unconnected/floating 3Ahex RTQLGEV"<"NZ517*Jwtqp"Tkxgt+ Swcpvc"Eqorwvgt"Kpe0 PD7 Size Custom Document Number Date: Wednesday, October 13, 2010 1 2 3 4 5 6 7 Rev 1A Audio Jack/Accelerometer Sheet 30 8 of 47 1 2 3 4 5 6 7 53 8 EQ FOR SUBWOOFER SI Change OUT_BY C857 10U/6.3VS_6 C868 0.1U/10V_4 R717 +4.75VAVDD 1NS R718 10K/F_4 C835 0.027U/25V_6 VREF_2R A 1IN-_1S C838 HPOUT C842 OUT_S 5600P/50V_6 R697 C856 A R710 10K/F_6 VREF_2R 60.4K/F_6 + 13 - 14 1 C839 2 1U/10V_6 C865 R719 10 2IN-_1S 9 - 10K/F_6 5 8 U46C TLV2464CPWRG4 R713 R712 C845 100P/50V_4 EQ_S1 + 0.027U/25V_6 60.4K/F_6 U46D TLV2464CPWRG4 AGND 2OUT_1S 0.027U/25V_6 C854 100P/50V_4 12 60.4K/F_6 R716 EQ_S 10K/F_6 1 C862 + 7 U46B TLV2464CPWRG4 C869 5600P/50V_6 6 R731 2 SUB_OUT 10K/F_6 1U/10V_6 AGND C843 100P/50V_4 2 HPOUTL_EQ R706 1U/10V_6 1 U46A TLV2464CPWRG4 10K/F_6 VREF_2R C847 1 - AGND VREF_2R BASS_OUT 2 1OUT_1S R694 10K/F_6 2NS [29] + 0.027U/25V_6 60.4K/F_6 R701 R702 3 SI Change 11 C841 100P/50V_4 AGND for subwoofer work 4/23. *0_6 10K/F_4 +4.75VAVDD 4 R721 VREF_2R Change 4EQ to 2EQ 10K/F_6 PV Change for HP request B B PVCC2 Sub-Woofer power R743 +3V U48 C886 1U/25V_6 ADC_EAPD# [29] ADC_EAPD# R744 PVCC2 10_6 100K_4 C884 R737 R739 C879 1 SD PVCCL 28 2 FAULT PVCCL 27 3 NC_3 BSN_26 26 4 NC_4 OUTN_25 25 *0_6/S 5 GAIN0 PGND 24 R741 *0_6/S 6 GAIN1 OUTN_23 23 1U/25V_6 47.5K/F_6 SUB_GND 27.4K/F_6 1U/25V_6 7 AVCC BSN_22 22 8 AGND BSP_21 21 9 GVDD OUTP_20 20 10 PLIMIT PGND 19 C877 1U/25V_6 11 INN OUTP_18 18 C876 1U/25V_6 12 INP BSP_17 17 13 NC_13 PVCC 16 PVCC 15 SUB_GND R736 AGND 10K_6 14 AVCC SUB_OUT 5/14 modify L61 SUB_GND PBY160808T-151Y-N CN1 C885 0.22U/50V_8 C880 0.22U/50V_8 SUB_OUT+ SUB_OUT- L60 SUB_GND PBY160808T-151Y-N 2 1 C 88266-020L C2 1000P/50V_4 C4 1000P/50V_4 5/14 modify 88266-020L-2p-r PVCC2 C878 0.22U/50V_8 R1 L62 1 PVCC2 SUB_GND C875 1000P/50V_6 SUB_GND 0.22U/50V_8 C874 0.1U/50V_6 HPA00836 SUB_GND C888 R742 C SUB_GND 1 100U/25V L-F +3V PV change to short pad R740 + C883 GND *0_8/S short0805 *100K_6 *100K_4 29 R726 *100K_6 R722 2 PVCC2 R727 C889 1000P/50V_6 PV remove BOM C890 0.1U/50V_6 +VIN 5/3 Change C951 to 100uf PVCC2 R738 R172 *0_4/S 2 *0_8/S *0_6/S *0_4/S EMI Request 5/3 del C964 SUB_GND SUB_GND SUB_GND 4/20 DB add. D GAIN1 GAIN0 *0_8 R745 *0_8 0 0 0 1 18 R728 SUB_GND *0_8/S 1 0 23.6 1 1 36 AGND D dB R732 12 RTQLGEV"<"NZ517*Jwtqp"Tkxgt+ Swcpvc"Eqorwvgt"Kpe0 +3V [3,7,8,9,10,11,13,14,18,19,25,26,27,28,29,30,32,33,34,35,36,37,39,40,41,43,45,46,47] +4.75VAVDD [29] +VIN [25,38,39,41,42,43,44,45] SUB_GND PD7 Size Custom Document Number Date: Wednesday, October 13, 2010 1 2 3 4 5 6 7 Rev 1A SUBWOOFER (EQ & AMP.) Sheet 31 8 of 47 5 4 3 BLUETOOTH D R783 BTCON_P1 BLUELED USBP6-_L USBP6+_L T3 BLUELED [35,36] 0R Close to CN10015 C180 L65 1 4 +3VPCU_BT 2 3 *WCM2012-90 R784 USBP6USBP6+ L19 0R [9] [9] [9] [9] 1 4 USBP8+ USBP8- L18 1 4 USBP9+ USBP9- +3VSUS USB_ENABLE# SATA_LED# ACCLED_EN PWR_LED# RP11 *0_4P2R_4 +3V 1 3 3 24mil Q21 PDTC144EU 2 BT_OFF# [9] [9] L25 4 1 USBP11+ USBP11- *WCM2012-90 3 USBP11+_1 2 USBP11-_1 USB_ENABLE# Close to CN10014 C17 C58 470P/50V_4 PV Add for USB *0.1U/10V_4 +5VPCU USBP9+_R USBP9-_R 4 1 3 2 L3 1 2 3 4 5 6 7 8 9 10 11 12 USBP9+_E USBP9-_E *WCM2012-90 USB_ENABLE# [8] SATA_LED# [10] ACCLED_EN [35,36] PWR_LED# +3V PWR_LED# CN2 *DUAL USB CONN C474 *0.1U/10V_4 C154 470P/50V_4 D 10/01 MV Modify. PV EMI request CN12 *USB CONN 6/28 : SI modify. PV Add for USB CN11 +5VPCU CN15 C444 1U/6.3V_4 C447 *10U/6.3V_8 C446 0.1U/10V_4 +5VPCU 2 1 2 1 1 [10,36] +5VPCU 1 2 3 4 5 6 USBP9+_R USBP9-_R FOR 15" ONLY +3VPCU_BT *0.1U/10V_4 PV EMI request CN6 DUAL USB CONN 1 3 Q20 ME2303T1 2 C445 1 2 3 4 5 6 7 8 9 10 11 12 13 14 *WCM2012-90 USBP8+ 2 USBP83 *WCM2012-90 USBP9+ 2 USBP93 2 4 8/16 PV add. 10/13 PV2 EMI request R331 4.7K_4 Close to CN9063 +5VPCU PV EMI request [9] [9] C480 1000P/50V_4 +3VPCU 0.1U/10V_4 54 1 RIGHT SIDE USB for 15" RIGHT SIDE USBX2 for 17" CN14 BLUE TOOTH CONN 87213-0600-6P-L 6 5 4 3 2 1 2 *88266-020L *88266-020L PV new Add C C E-SATA USB fingerprint CON 1. USBP2- 10/13 PV2 EMI Stuff. +5VPCU U13 2 3 IO1 Vin IO2 Gnd 4 1 +3V 2 3 4 1 *PJSR05 2. USBP2+ [35] USB_ENABLE# 3 +3V FINGER PRINTER CONN [9] [9] 5. SYSTEM GND USBP2USBP2+ +3V +5V 6. SYSTEM GND 1 2 3 4 5 6 C687 0.1U/10V_4 VIN1 VIN2 EN GND OUT3 OUT2 OUT1 OC G547F2P81U C726 1U/6.3V_4 4. +5V 80 mils (Iout=2A) U14 +5VSUS_USBP0 8 7 6 5 USB & ESATA 4/20 DB add. R542 5/14 modify. *0R CN26 L42 C700 470P/50V_4 C701 0.1U/10V_4 + C697 100U/16V [9] [9] 1 4 USBP1USBP1+ +5VSUS_USBP0 1 USBP1-_E 2 USBP1+_E 3 4 2 3 WCM2012-90 R543 *0R [8] [8] 5 6 7 8 9 10 11 SATA_TXP5 SATA_TXN5 [8] SATA_RXN5 [8] SATA_RXP5 CN8 B 4/29 modify. USB Vcc DD+ GND GND A+ AGND BB+ GND Shield 14 Shield 15 Shield 12 Shield 13 B USB_ESATA_COMBO usb-1-2006102-3-11p-v DFHS11FR047 CONN DIP ESATA+USB 11P 2R FR(H7.7) Touch screen for 15" LEFT USB PORT CN4 L6 10/13 PV2 EMI Stuff. 4/20 DB add. [9] [9] USBP3+ USBP3- USBP3+ USBP3- 4 1 FWE 1 2 3 4 5 6 7 8 9 10 USBP3+ USBP3- 3 2 *WCM2012-90 A [9] [9] USBP0USBP0+ 2 3 WCM2012-90 R587 *0R *PJSD05TS D3 1 1 4 D2 8 7 6 5 2 L44 C762 0.1U/10V_4 CN27 +5VSUS_USBP0 1 1 GND USBP0-_U 2 2 GND USBP0+_U 3 3 GND 4 4 GND 1A 1 *0R 2 R584 [8] DGT_STOP# [10] DGT_RESET +5V *PJSD05TS DGT_STOP# DGT_RESET Change the power from +3V to +5V. GND A *TS-FFC-connect USB CONN RTQLGEV"<"NZ517*Jwtqp"Tkxgt+ Swcpvc"Eqorwvgt"Kpe0 PD7 Size Custom Document Number Date: Wednesday, October 13, 2010 5 4 3 2 Rev 1A BT/WC/FT/Touchscreen 1 Sheet 32 of 47 5 4 3 2 +3V_LAN For EMI 0 ~ 22 ohm +3V_LAN +3VLANVCC R203 10_4 C361 C343 C339 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 +1.05V_LAN R196 Y1 XTAL2 2 LANRSET 2.49K/F_4 49 48 47 46 45 44 43 42 41 40 39 38 37 MDI0+ MDI0- 1 2 3 4 5 6 7 8 9 10 11 12 MDI1+ MDI1- AL08111DB00 4/23 modify RTL8111DL-GR MDI2+ MDI2- U38 MDI0V_DAC1 *0_4/S MDI1+ MDI1- V_DAC2 *0_4/S MDI2+ MDI2- MCT1 24 2 TD1+ MX1+ 23 LAN_MX0+ 3 TD1- MX1- 22 LAN_MX0- 4 TCT2 MCT2 21 LAN_MCT1 C287 5 TD2+ MX2+ 20 LAN_MX1+ 6 TD2- MX2- 19 LAN_MX1- 7 TCT3 MCT3 18 LAN_MCT2 C288 8 TD3+ MX3+ 17 LAN_MX2+ TD3- MX3- 16 LAN_MX2- TCT4 MCT4 15 LAN_MCT3 C289 TD4+ MX4+ 14 LAN_MX3+ TD4- MX4- 13 LAN_MX3- 9 V_DAC3 10 *0_4/S C744 0.01U/25V_4 LAN_MCT0 C290 TCT1 MDI3+ 11 MDI3- 12 *0_4/S R176 *0_4/S R177 75_4 *0_4/S R178 +3V_LAN 75_4 *0_4/S R179 75_4 [9] PCIE_CLKREQ_LAN# C718 10P/3KV_1808 IND SMD 4.7UH +-20% 680MA(CBC2518T4R7M) CV-4707MZ00 Power trace Layout >60mil +1.05V_LAN_O L43 PCIE_CLKREQ_LAN# R561 *0_4/S PCIE_TXP2_LAN PCIE_TXN2_LAN SROUT1 VDDSR VDDSR ENSR EEDI/SDA LED3/EDO EECS/SCL DVDD1 LANW AKEB VDD3 ISOLATEB PERSTP 36 35 34 33 32 31 30 29 28 27 26 25 LAN_GLINK10# R235 PCIE_WAKE# 10K/F_4 +1.05V_LAN PCIE_WAKE# [7,36] +3V_LAN ISOLATEB PLTRST# PLTRST# [3,9,35,36,37] C +3V PCIE_RXN2_LAN_L C358 0.1U/10V_4 PCIE_RXP2_LAN_L C355 0.1U/10V_4 R605 1K_4 PCIE_RXN2_LAN [9] ISOLATEB PCIE_RXP2_LAN [9] R586 *100_4 2 +1.05V_LAN R593 LAN_DISABLE# [10] 1 *RB501V-40 15K/F_4 LAN_GLINK100# LAN_GLED# LAN_TX# LAN_YLED# D15 +1.05V_LAN Link C370 C356 *1000P/50V_4 *1000P/50V_4 B +3V_LAN C759 0.1U/10V_4 if ISOLATEB pin pull-low,the LAN chip will not drive it's PCI-E outputs ( excluding PCIE_WAKE# pin ) 1 > 60mil C754 0.1U/10V_4 Trace<30 mil Width > 60 mil +3V_LAN 10K/F_4 LAN_ECS_SCL R585 CLK_PCIE_LANP CLK_PCIE_LANN [9] CLK_PCIE_LANP [9] CLK_PCIE_LANN >60mil CBC2518T4R7M RTL8111E-VB-GR LAN_SMBDAT 10K/F_4 [9] PCIE_TXP2_LAN [9] PCIE_TXN2_LAN 10/13 PV2 EMI Request 4/29 modify MDIP0 MDIN0 AVDD1(NC) MDIP1 MDIN1 AVDD1(NC) MDIP2(NC) MDIN2(NC) AVDD1(NC) MDIP3(NC) MDIN3(NC) AVDD3(NC) +1.05V_LAN R197 NS892405 B MDI3+ MDI3- 75_4 LAN_MCTG MDI0+ 1 D +3V_LAN 13 14 15 16 17 18 19 20 21 22 23 24 V_DAC0 *0_4/S C364 0.1U/10V_4 +1.05V_LAN_O 2 4/23 modify C745 C776 22U/6.3VS_8 +3V_LAN LAN_GLINK100# GND AVDD33 AVDD33(NC) RSET AVDD1 CKXTAL2 CKXTAL1 AVDD3(AVDD1) VDD1(NC) LED0 VDD3 GPO/SMBALERT LED1/EESK U17 +1.05V_LAN 9/29: Modify footprint C742 R211 1K/F_4 Close to Pin 35/34 C354 33P/50V_4 C747 LAN_GPIOS GND VIA x 9 Pcs C359 33P/50V_4 C LAN_TX# +3V_LAN 25MHz C746 +1.05V_LAN LAN_CLKRQ 1 +3V_LAN DVDD1 SMBCLK(NC) SMBDATA(NC) CLKREQB HSIP HSIN REFCLK_P REFCLK_M EVDD1 HSOP HSON GNDTX D C341 XTAL1 XTAL2 XTAL1 LAN_XTAL1 55 1 C342 0.1U/10V_4 C369 0.1U/10V_4 R438 330_4 C550 C756 4.7U/6.3V_6 +1.05V_LAN C367 0.1U/10V_4 C748 0.1U/10V_4 C347 C771 0.1U/10V_4 0.1U/10V_4 R395 12 11 LAN_MX3+ LAN_MX3LAN_MX2LAN_MX1LAN_MX1+ LAN_MX2+ LAN_MX0+ LAN_MX0- 8 7 6 5 4 3 2 1 LAN_GLED LAN_GLED# 330_4 4/23 modify C507 4/23 modify CN22 LAN_YLED LAN_YLED# FOR EMI +3V_LAN A RJ45 1000P/50V_4 C755 0.1U/10V_4 10 9 1000P/50V_4 LED_GRE_P LED_GRE_N RX1RX1+ RX0TX1TX1+ RX0+ TX0TX0+ GND1 14 GND 13 LED_YEL_P LED_YEL_N A RJ45_CONN Close to Pin 21 RTQLGEV"<"NZ517*Jwtqp"Tkxgt+ Swcpvc"Eqorwvgt"Kpe0 PD7 Size Custom Document Number Date: Wednesday, October 13, 2010 5 4 3 2 Rev 1A RTL 8111EL/RJ45 1 Sheet 33 of 47 A B C SATA HDD CONNECTOR D 56 E SATA CD-ROM 120 mils +5V_ODD C592 10U/6.3VS_6 DFHD20MR005 C600 0.1U/10V_4 C616 C593 C613 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 DC Current rating: 0.5 A +5V CN31 SATA HDD(1ST) +5V: 2 A(4 Pin) C452 10U/6.3V_8 20 +3V: 2 A(4 Pin) C453 10U/6.3V_8 C451 4.7U/6.3V_6 C450 0.1U/10V_4 Gnd : (5 Pin) CN23 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 1 Main HDD D 120 mils 23 24 21 22 D [8] SATA_RXN4 [8] SATA_RXP4 [10] ODD_PRSNT# SATA_RXN0 [8] SATA_RXP0 [8] +5V R481 1 5/6: modify 2 1K_4 +5V_ODD ODD_EJECT# 5/6: modify +5V +3V +5V_ODD +3V_HDD R485 0_8 C R329 19 SATA_TXP0 [8] SATA_TXN0 [8] +3V_HDD SATA_TXP4 SATA_TXN4 1 [8] [8] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 C 6/4 DB2 Modify *0_8 10/13 PV2 Modify SATA ODD SI chenage footprint SATA_2 CONNECTOR FOR 17.3" +5V 8/11 PV Modify PV modify R496 *10K_4 120 mils ODD_EJECT# *0_4 R40 EJECT# [35] C653 10U/6.3V_8 5/7: Modify 10/13 PV2 Modify 10/13 PV2 Modify CN25 C673 *10U/6.3V_8 1 B C629 0.1U/10V_4 Q35 *AO3404 +5V_ODD 2 SATA_RXN1 [8] SATA_RXP1 [8] 3 1 High : ODD power down Low : ODD power on 5/6: modify R493 *22_8 1 +3V ODD_PD 0_4 R459 +5V 2 Q31 2N7002 1 [35] 2 Main HDD C680 0.1U/10V_4 SATA_TXP1 [8] SATA_TXN1 [8] AO3404 ID current 5.8A 6/4 DB2 Modify C211 0.027U/25V_6 1 1 +3V R138 330K_6 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 +5V +12VALW 2 B 2 C652 0.1U/10V_4 3 C651 4.7U/6.3V_6 3 C654 10U/6.3V_8 +3V 6/4 DB2 Modify 2 Q32 2N7002 19 1 PV EMI request 2nd SATA HDD(2ST) SI chenage footprint A A 5/6: EMI request reserve +3V C647 *0.1U/10V_4 +3VPCU C388 *0.1U/10V_4 C6 *0.1U/10V_4 C459 *0.1U/10V_4 +1.05V C376 *0.1U/10V_4 C381 *0.1U/10V_4 +5V RTQLGEV"<"NZ517*Jwtqp"Tkxgt+ Swcpvc"Eqorwvgt"Kpe0 +3VPCU [7,8,25,32,35,36,37,38,39,40,42,44,45,47] +1.05V [7,8,9,11,35,41] +3V [3,7,8,9,10,11,13,14,18,19,25,26,27,28,29,30,31,32,33,35,36,37,39,40,41,43,45,46,47] +5V [7,8,11,19,25,26,27,29,30,32,36,37,45] +12VALW [25,37,42,44,45] C397 *0.1U/10V_4 PD7 Size Custom Document Number Date: Wednesday, October 13, 2010 A B C D Rev 1A ODD/HDD/ANT E Sheet 34 of 47 4 3 +3VPCU PSCLK1/GPIO4A PSDAT1/GPIO4B PSCLK2/GPIO4C PSDAT2/GPIO4D PSCLK3/GPIO4E PSDAT3/GPIO4F BIOS_RD# BIOS_WR# BIOS_CS# [10] PCI_SERR# [46] CPU_ICC 4/29 modify from EC request *0_4/S R376 R 376 [7] SUS_PWR_ACK [37] KEYLED_CN [36] RF_LINK# [27] [3] B HDMI_HPD EC_PECI *0_4 [32] USB_ENABLE# [43,45] SUSON [38,39,41,43,44,45] MAINON [45] LAN_POWER [45] S5_ON [36] BLED_COMBO *0_4/S 119 120 128 89 CPU_ICC 76 DGPU_PR_EN_E 109 EC_GPXD1 110 112 KEYLED_CN 114 115 BLUELED 116 117 R412 118 USB_ENABLE# SUSON MAINON LAN_POWER S5_ON R456 APD_120W [7] AC_PRESENT [44] MBATLED0# [44] AC_LED_ON# [37] WIRELESS_ON# [37] WIRELESS_OFF# 5/7 AD0/GPI38 AD1/GPI39 AD2/GPI3A AD3/GPI3B DA0/GPO3C DA1/GPO3D DA2/GPO3E DA3/GPO3F 68 70 71 72 VFAN D/C# PW M1/GPIOE PW M2/GPIO10 21 23 PWM_VADJ KB_LED_EN FANPW M1/GPIO12 FANPW M2/GPIO13 FANFB1/GPIO14 FANFB2/GPIO15 26 27 28 29 G_INT2# LID_CONTROL FAN1SIG SCL1/GPIO44 SDA1/GPIO45 SCL2/GPIO46 SDA2/GPIO47 77 78 79 80 MBCLK MBDATA MBCLK2 MBDATA2 RD WR SELMEM/SPICS SELIO/GPIO50 SELIO2/GPIO43 D0/GPXD0 D1/GPXD1 D2/GPXD2 D3/GPXD3 D4/GPXD4 D5/GPXD5 D6/GPXD6 D7/GPXD7 97 98 99 100 101 102 103 104 105 106 107 108 A0/GPXA0 A1/GPXA1 A2/GPXA2 A3/GPXA3 A4/GPXA4 A5/GPXA5 A6/GPXA6 A7/GPXA7 A8/GPXA8 A9/GPXA9 A10/GPXA10 A11/GPXA11 modify from EC request 124 V18R 2 [44] [44] 4 NR/FB 2 R518 6 SUSB# GPIO7 GPIO8 14 15 HWPG CPU_PROCHOT GPIOA GPIOB GPIOC GPIOD GPIO11 GPIO16 GPIO17 GPIO18 16 17 18 19 25 30 31 32 SUSC# DGPU_PWR_EN_1 GPIO33_E1 NBSWON1# [44] [44] For [9,14,30] [9,14,30] Remove AC: AC_IN-->low, CPU_PROCHOT-->low , H_PROCHOT#-->low 5/7 modify from EC request Remove AC and re-cove prochot: AC_IN-->low, CPU_PROCHOT--> high, H_PROCHOT#--> high +3VPCU Battery charge/charge and cap board For PCH SMB/DDR Thermal IC/G-sensor GPIO19 GPIO1A 34 36 VRON R50 SUSB# [7] HWPG [38,39,41,42,43] SUSC# R160 R143 10K_4 VRON ACIN R157 GPIO33_E [8] CIR_RX/GPIO40 GPIO41 GPIO42 GPIO52 GPIO53 GPIO54 GPIO55 GPIO56 GPIO57 GPIO58 GPIO59 73 74 75 90 91 92 93 95 121 126 127 XCLKO 123 R101 *0_4 CRY2 XCLKI 122 GND1 GND2 GND3 GND4 GND5 AGND 11 24 35 94 113 69 R116 R103 CPU_VCC [46] CAPSLED# [37] PWR_LED# [32,36] EC_PWROK [7,25] RSMRST# [7] VOLMUTE# [29] R47 LID_EC# 0_4 *0_4 CRY2 CLK_33M_KBC R390 2N7002EPT_SC70 *10_4 C511 *10P/50V_4 3920_RST# SI CHANGE POWER EC_PECI [3] GFX_VR_ICC [46] R394 10K_4 NBSWON1# R479 4.7K_4 MBCLK R48 R478 +3V C37 22P/50V_4 If use PCH SUSCLK should change to 20P. FOR DIS ONLY 4/19 modify from EC request PCH_SUSCLK [7] DGPU_PWR_EN_1 4.7K_4 MBCLK2 R471 4.7K_4 MBDATA2 R658 *10K_4 GPIO33_E R380 +1.05V 220P/50V_4 PV Change 1 PM_THRMTRIP# [3,10] 10K_4 G_INT2# PV Remove BOM 9/26: MV stuff +3VPCU 9/26: MV Modify 0_4 C36 MMBT3904-7-F R472 R411 4.7K_4 MBDATA 3 [25,36] *0_4/S 4.7K_4 5/13: modify from EC request *27P/50V_4 R55 2 thermal shutdown circuit BIOS_SPI_CLK_I 33_4 Y2 *32.768KHZ C62 CPU_PROCHOT 2 Q8 20P/50V_4 CRY1 PQ27 For EMI +3VPCU C55 *0_4 PV modify MV Stuff 4/19 modify from EC request GFX_VR_VCC [46] DNBSWON#1 CAPSLED# PWR_LED# EC_PWROK RSMRST# VOLMUTE# BIOS_SPI_CLK LID_EC# PQ28 [40] MV modify H_PROCHOT# [3,40] PQ29 2N7002EPT_SC70 2 *2N7002EPT_SC70 8/12 9/26 4/23, add strap, for indentify LX M/B 9/29 *0_4/S C Q28 *2N7002EPT_SC70 2 D20 NBSWON1# [36] SLP_S5 [7] EC_DEBUG1 [36] EJECT# [34] 1K_4 CPU_PROCHOT_1 [7] RB500V-40 KBSMI#1 TPDATA 4.7K_4 AC present: AC_IN-->high, CPU_PROCHOT-->low , H_PROCHOT#-->high G_INT2# [30] LID_CONTROL [25] FAN1SIG [36] ODD_PD [34] VGA_ALERT [17,18] GPIO4 TPCLK 4.7K_4 close conn PWM_VADJ [24] KB_LED_EN [37] MBCLK MBDATA MBCLK2 MBDATA2 R517 +3VSUS C554 *TPS73133 *1U/6.3V_4 GPU_PROCHOT [17] VFAN [36] D/C# [44] B adapter Type check D11 1SS355 DGPU_PWR_EN [10,42,43] 2 C525 4.7U/6.3V_6 AD_AIR SYS_I D *1U/6.3V_4 KB3930QF A1 R414 100K_4 AD_TYPE R93 10K_4 R7 100_4 AD_ID 7/2 add U26 colay R431 BLUELED 100K_4 [44] BLUELED [32,36] 1 1 C512 0.1U/10V_4 TEMP_MBAT [44] T1 C692 10P/50V_4 3 83 84 85 86 87 88 GND C693 10P/50V_4 C559 1 GPUT_CLK GPUT_DATA GFX_HWPG ACIN TPCLK TPDATA SHDN 3 3 KSO0/GPIO20 KSO1/GPIO21 KSO2/GPIO22 KSO3/GPIO23 KSO4/GPIO24 KSO5/GPIO25 KSO6/GPIO26 KSO7/GPIO27 KSO8/GPIO28 KSO9/GPIO29 KSO10/GPIO2A KSO11/GPIO2B KSO12/GPIO2C KSO13/GPIO2D KSO14/GPIO2E KSO15/GPIO2F KSO16/GPIO48 KSO17/GPIO49 TEMP_MBAT AD_TYPE AD_AIR SYS_I 2 5/7 modify from EC request 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 81 82 1 1 2 3 4 5 6 TPDATA-1 TPCLK-1 PBY160808T-470Y-N/3A_6 PBY160808T-470Y-N/3A_6 1 GPUT_CLK GPUT_DATA [40] GFX_HWPG [44,45] ACIN MY0 MY1 MY2 MY3 MY4 MY5 MY6 MY7 MY8 MY9 MY10 MY11 MY12 MY13 MY14 MY15 MY16 MY17 VIN C548 4.7U/6.3V_6 CN10 PWR BTN CONN 2 [18] For GPU thermal [18] KSI0/GPIO30 KSI1/GPIO31 KSI2/GPIO32 KSI3/GPIO33 KSI4/GPIO34 KSI5/GPIO35 KSI6/GPIO36 KSI7/GPIO37 VOUT L41 L40 1 MY0 MY1 MY2 MY3 MY4 MY5 MY6 MY7 MY8 MY9 MY10 MY11 MY12 MY13 MY14 MY15 MY16 MY17 55 56 57 58 59 60 61 62 5 0.1U/10V_4 63 64 65 66 TPDATA TPCLK 3 [37] [37] [37] [37] [37] [37] [37] [37] [37] [37] [37] [37] [37] [37] [37] [37] [37] [37] MX0 MX1 MX2 MX3 MX4 MX5 MX6 MX7 +5VPCU U29 0.1U/10V_4 1 MX0 MX1 MX2 MX3 MX4 MX5 MX6 MX7 SCI/GPIOE GA20/GPIO0 KBRST/GPIO1 ECRST C567 C696 +3VSUS L34 PBY160808T-470Y-N/3A_6 +3VPCU_EC 57 TOUCH PAD CONNECTOR & ON/OFF BOTTOM +3VPCU 3 C [37] [37] [37] [37] [37] [37] [37] [37] 20 1 2 37 9 22 33 96 111 125 67 2 [10] EC_A20GATE [10] EC_RCIN# SCI1# EC_A20GATE EC_RCIN# 3920_RST# VCC1 VCC2 VCC3 VCC4 VCC5 VCC6 AVCC 4 D SERIRQ LFRAME LAD0 LAD1 LAD2 LAD3 PCICLK PCIRST/GPIO5 CLKRUN 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 *10U/6.3V_8 1 [8] SERIRQ R46 [8,36] LFRAME# R44 [8,36] LAD0 R43 [8,36] LAD1 R42 [8,36] LAD2 R45 [8,36] LAD3 [9] CLK_33M_KBC [3,9,33,36,37] PLTRST# [7] CLKRUN# +3VPCU_EC C570 C544 C529 C524 C508 C505 C506 1 3 U7 SERIRQ 3 *0_4/S LFRAME#_R 4 *0_4/S LAD0_R 10 *0_4/S LAD1_R 8 *0_4/S LAD2_R 7 *0_4/S LAD3_R 5 12 13 CLKRUN# 38 2 1 5 C42 FOR SG/DIS [9,10,42,43,47] 0.1U/10V_4 +3VPCU U25 DGPU_PWROK [42,43,47] DGPU_PR_EN R443 0_4 EC_GPXD1 R450 0_4 DGPU_PR_EN_E FOR UMA ONLY A BIOS_CS# BIOS_SPI_CLK_I BIOS_WR# BIOS_RD# +3VPCU R454 *100K_4 R53 1 6 5 2 SPI_3P 10K_4 3 CE# SCK SI SO VDD 8 HOLD# 7 W P# VSS 4 +3VPCU SPI_7P R49 R417 47K_4 5/23: modify for +3VPCU R432 1 2 RB501V-40 SIO_EXT_SCI# [10] DNBSWON#1 D12 1 2 RB500V-40 DNBSWON# [7] KBSMI#1 D9 5 1 2 RB500V-40 SIO_EXT_SMI# [10] BIOS_CS# BIOS_SPI_CLK_I BIOS_WR# BIOS_RD# 1 6 5 2 SPI_3P 3 +3VPCU CE# SCK SI SO VDD 8 HOLD# 7 W P# VSS 4 Socket: DG008000031 MXIC AKE3KZP0001 SPI_7P WINBOND AKE37ZN0N00 AMIT 512K byte SPI EC ROM *MX25L4005AM2C-12G 4 R467 12.1K/F_4 C465 100P/50V_4 APD_120W R440 5/7 *10K_4 modify from power support 230w A adapter select for EC U26 D10 C578 0.1U/10V_4 0.1U/10V_4 stuff SG 10K_4 W25X40BVSSIG Change to RB500 as Current loss C526 10K_4 Hi ==> 120W SCI1# 3920_RST# AKE38ZN0800 R432 R440 Low ==> 65W/90W SG/DIS 10K NA UMA NA 10K PV Change BOM RTQLGEV"<"NZ517*Jwtqp"Tkxgt+ Swcpvc"Eqorwvgt"Kpe0 PD7 Size Custom Document Number Date: Wednesday, October 13, 2010 3 2 Rev 1A KB3926/ROM/TP 1 Sheet 35 of 47 A B Mini PCI-E Card 1 WLAN 6/7 :DB2 modify BT_OFF# +3V R749 0_4 R750 *4.7K_4 R344 +5V modify 6/29: SI add 4/19 modify from EC request +1.5V *0_6 EC debug pin [35] EC_DEBUG1 D 6/7 :DB2 modify [9] [9] [9] [9] PCIE_TXP1 PCIE_TXN1 PCIE_TXP1 PCIE_TXN1 PCIE_RXP1 PCIE_RXN1 R755 R751 R754 +3V [10,32] BT_OFF# [9] CLK_33M_DEBUG PCIE_RXP1 PCIE_RXN1 *4.7K_4 *0_4 0_4 PLTRST# CLK_PCIE_WLANP CLK_PCIE_WLANN [9] CLK_PCIE_WLANP [9] CLK_PCIE_WLANN MV Add [9] PCIE_CLKREQ_WLAN# [9] BT_COMBO_EN# 58 E +3V 8/6 :PV CN20 FOR KBC DEBUG D R705 BT_COMBO_EN_M *0_4 MINICAR_PME# 51 49 47 45 43 41 39 37 35 33 31 29 27 25 23 21 19 17 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved GND PETp0 PETn0 GND GND PERp0 PERn0 GND Reserved Reserved 15 13 11 9 7 5 3 1 GND REFCLK+ REFCLKGND CLKREQ# BT_CHCLK BT_DATA W AKE# BT_DATA,BT_CHCLK,CLKREQ# internal pull-DOWN 100k ohm +3.3V GND +1.5V LED_W PAN# LED_W LAN# LED_W W AN# GND USB_D+ USB_DGND SMB_DATA SMB_CLK +1.5V GND +3.3Vaux PERST# W _DISABLE# GND 52 50 48 46 44 42 40 38 36 34 32 30 28 26 24 22 20 18 Reserved Reserved Reserved Reserved Reserved +1.5V GND +3.3V 16 14 12 10 8 6 4 2 MINI_BLED R374 R375 R347 *10K_4 +3V *0_4 *0_4 BLUELED R774 0_4 +1.5V BLED_COMBO [35] BLUELED [32,35] RF_LINK# R352 R348 5/11 :stuff R9149 PLTRST# LAD0 LAD1 LAD2 LAD3 LFRAME# C503 0.1U/10V_4 C472 10U/6.3VS_6 10K_4 CLK_33M_DEBUG R366 *0_4 C493 C504 0.1U/10V_4 C476 10U/6.3VS_6 D USBP10+ [9] USBP10- [9] PLTRST# RF_OFF# [3,9,33,35,37] [10] LAD0 LAD1 LAD2 LAD3 LFRAME# [8,35] [8,35] [8,35] [8,35] [8,35] INTEL WLAN CARD PIN 20 W_DISABLE# have internal pull-up 110k ohm +3VSUS R391 3 [7,33] PCIE_WAKE# *10K_4 MINICAR_PME# 1 Q27 *PDTC144EU C *33P/50V_4 +3V +5V +1.5V +3VPCU for EMI request CPU FAN C491 0.1U/10V_4 +3V MINI PCIE H=9.0 DFHD52MS029 MIPCI-800055FB052GX00PL-52P-smt C C19 0.1U/10V_4 RF_LINK# [35] 0_4 5/6:modify from HP request C487 0.01U/25V_4 +3V 2 [10,32] C [3,7,8,9,10,11,13,14,18,19,25,26,27,28,29,30,31,32,33,34,35,37,39,40,41,43,45,46,47] [7,8,11,19,25,26,27,29,30,32,34,37,45] [5,11,13,45] [7,8,25,32,34,35,37,38,39,40,42,44,45,47] POWER BOTTON CONNECT +3V R386 4.7K_4 NBSWON1# [35] NBSWON1# +3VPCU FAN1SIG 1. +3VPCU(LIDSWITCH PWR) 1 CN21 1 2 3 1 2 3 4 4 FAN CONN C498 0.1U/10V_4 C509 0.1U/10V_4 C502 0.1U/10V_4 PWR_LED# 4/20 DB add. LID_EC# +5V R370 [35] +5V 10K_4 THERM_OVER# 1 VIN VO GND /FON GND GND VSET GND 4 VFAN +5V 3 5 6 7 8 C520 0.1U/10V_4 +5V_FAN C521 0.1U/10V_4 R373 R382 [25,35] LID_EC# [35] NBSWON1# [32,35] PWR_LED# *0_4/S *0_4/S PWR_LED# 5. PWRLED# 1 2 3 4 5 6 6. GND 7 30 MIL U24 2 B 3. LIDSWITCH 4. NBSWON1# DFHD03MR008 FANPWR = 1.6*VSET 2. +3VPCU(LIDSWITCH PWR) 8 C499 2.2U/6.3V_6 G1 *SOLDERJUMPER-2 2 +5V_FAN B CN5 PWR BTN CONN G991PV11 8 C497 1U/6.3V_4 7 6 5 G995 layout notice Gnd shape 1 2 3 4 A A RTQLGEV"<"NZ517*Jwtqp"Tkxgt+ Swcpvc"Eqorwvgt"Kpe0 PD7 Size Custom Document Number Date: Wednesday, October 13, 2010 A B C D Rev 1A MINI PCIE CONN/FAN E Sheet 36 of 47 1 2 3 4 5 6 MG[DQCTF"RWNN/WR [35] RP18 MY1 MY5 MY0 MY9 10 9 8 7 6 MY13 MY12 MY3 MY6 10 9 8 7 6 MY2 MY4 MY7 MY8 1 2 3 4 5 8/6: PV del *8.2K_10P8R_6 +3VPCU A 7 MY5 MY6 MY3 MY7 C308 C301 C299 C303 220P/50V_4 220P/50V_4 220P/50V_4 220P/50V_4 MY1 MY2 MY4 MY0 C307 C305 C304 C311 220P/50V_4 220P/50V_4 220P/50V_4 220P/50V_4 MY8 MY9 MY10 MY11 C302 C314 C294 C295 220P/50V_4 220P/50V_4 220P/50V_4 220P/50V_4 MX4 MX6 MX3 MX2 C313 C315 C309 C310 220P/50V_4 220P/50V_4 220P/50V_4 220P/50V_4 MX7 MX0 MX5 MX1 C316 C306 C312 C317 MY12 MY13 MY14 MY15 MY16 MY17 C298 C297 C296 C293 C292 C291 220P/50V_4 220P/50V_4 220P/50V_4 220P/50V_4 MX[0..7] MX[0..7] KB CONN MX1 MX7 MX6 MY9 MX4 MX5 MY0 MX2 MX3 MY5 MY1 MX0 MY2 MY4 MY7 MY8 MY6 MY3 MY12 MY13 MY14 MY11 MY10 MY15 MY16 MY17 220P/50V_4 220P/50V_4 220P/50V_4 220P/50V_4 220P/50V_4 220P/50V_4 RP19 MY14 MY11 MY10 MY15 1 2 3 4 5 *8.2K_10P8R_6 R470 R469 *8.2K_4 *8.2K_4 PV Change BOM SI Add MY16 MY17 +5V PV Change BOM +5V R505 1K_4 R519 2 R531 1K_4 1 *200/F_6 R525 2 1 *200/F_6 WIRELESS_OFF_R 2 [35] WIRELESS_ON# 11 LEDs for 17” (Total LED current 220mA) Q36 PDTC144EU WIRELESS_ON_R WIRELESS_OFF_R R533 200/F_4 R528 200/F_4 [29] MUTE_LED# [35] CAPSLED# 2 [35] WIRELESS_OFF# Q38 PDTC144EU 1 7 LEDs for 15.4” (total LED current 140mA) [35] KEYLED_CN 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 R415 +3V 1K_4 KEYLED_CN_R 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A 1 clear ABS 758 resin for key cap. 3 3 WIRELESS_ON_R 59 MY[0..17] MY[0..17] [35] 8 R416 100K_4 C300 0.1U/10V_4 CN9 MV Add B KB backlight for 15" B 3 +5V R164 R161 *1M_4 2 3 +12VALW *100K_4 Q12 *AO3404 Q11 *2N7002K C679 *0.1U/10V_4 140 mA +5V_LED_KBLIGHT 2 KB_LED_EN 1 [35] 1 C274 *0.01U/25V_4 C678 *0.1U/10V_4 4.LEDVCC CN7 3. LEDVCC 4 3 2 1 2. GND 1. GND *KB LIGHT CONN DFFC04FR042 88513-0401-4p-l-smt C C +3V FOR SG ONLY H13 *H-TC315BC354D118P2 H11 H3 *H-TC315I138BC354D118P2 *H-TC315BC354D118P2 GPU H9 *H-TC276I169BC217D150P2 H6 *H-TC276I169BC217D150P2 H8 *H-TC276I169BC217D150P2 CPU [3,9,33,35,36] H10 *H-TC315I138BC354D118P2 H4 *H-TC315BC354D118P2 H12 *H-TC315I138BC354D118P2 *SPAD-RE118X197NP SPAD-RE118X197NP DGPU_HIN_RST# R570 6/7 :DB2 Modify *SPAD-RE118X197NP SPAD-RE118X197NP [3,9,33,35,36] PLTRST# +3V [3,7,8,9,10,11,13,14,18,19,25,26,27,28,29,30,31,32,33,34,35,36,39,40,41,43,45,46,47] +5V [7,8,11,19,25,26,27,29,30,32,34,36,45] +3VPCU [7,8,25,32,34,35,36,38,39,40,42,44,45,47] +3V_VGA [16,17,18,19,27,42] +12VALW [25,34,42,44,45] +1.0V_VGA [15,17,19,43] +1.5V_VGA [16,19,20,21,22,23,47] +1.8V_VGA [15,17,19,42] FOR DIS ONLY PLTRST# R753 D PEGX_RST# 0_4 PEGX_RST# [15] RTQLGEV"<"NZ517*Jwtqp"Tkxgt+ Swcpvc"Eqorwvgt"Kpe0 PD7 Size Custom Document Number 2 3 4 5 6 7 Rev 1A KB Date:Wednesday, October 13, 2010 1 PEGX_RST# [15] 1 *100K_4 8/6 :PV Modify H5 *H-TC315I138BC354D118P2 1 1 1 *330_4 PAD2 5/4: add for PDC request 1 4 R569 3 PAD1 1 H7 *INTEL-CPU-BRACKET 3 2 4 1 JQNG 5/10: del H6,H7,H11,H12 1 H1 *H-TC315BC354D118P2 1 D 2 PLTRST# [9] DGPU_HOLD_RST# H2 *H-TC236BC354D130P2 1 1 H15 *H-TC236BC354D130P2 C770 *0.1U/10V_4 1 1 1 1 1 1 1 1 1 U41 *MC74VHC1G08DFT2G 5 H17 H16 H14 H-C217D126P2 H-C217D126P2 *H-TC315BC354D118P2 Sheet 37 8 of 47 5 4 3 2 5: 1 DC/DC +3V_ALW/+5V_ALW/+5V_ALW2 /+15V_ALW 5VPCU setting D D +VIN DB Change PD8 1 +5V_VCC1 + G S 4 PC111 Rds(on) 5m ohm 38 35 34 33 17 18 19 20 21 22 23 24 4 0.1U/25V_4 0.1U/10V_4 PR125 *0_4 5V_DH 5V_LX 3 2 1 220U/6.3V_6X4.5ESR18 G S PC237 3 2 1 PC221 2200P/50V_4 PC216 PQ46 RJK03D3D D REFIN2 ILIM2 OUT2 SKIP PGOOD2 ON2 DH2 LX2 PR121 5V_DL 2200P/50V_4 4.7U/25V_8 4.7U/25V_8 +3.3V_ALWP 3V_FB2 PR91 205K/F_4 PR222 2.2_8 3V_DL PR224 *0_2/S PGOOD2 + 4 3V_DH 3V_LX PC246 PQ48 AON7702 PC79 3V_BST2 PR98 5V_BST1 2_6 32 31 30 29 28 27 26 25 1 PU5 RT8206B PL17 2.2UH/8A PC254 0.1U/10V_4 PC250 2 5V_FB1 PR123 130K/F_4 PGOOD1 BYP OUT1 FB1 ILIM1 PGOOD1 ON1 DH1 LX1 PAD PAD PAD PAD PR93 *0_4/S PV change PR92 *0_4/S PV change Rds(on) 14m ohm 220U/6.3V_6X4.5ESR18 PQ13 RJK03D3D D 5 5 PR216 2.2_8 *0_2/S + 9 10 11 12 13 14 15 16 37 36 39 40 0.1U/10V_4 C +3VPCU 4 2 4 PL13 1.5UH/16A PR202 1 S 3 2 1 3 2 1 4 5V_DH G +5V_VCC1 1 D S 2 PQ47 RJK03B9D PQ49 AON7410 PC86 PAD PAD PAD PAD BST1 DL1 VDD N.C AGND PGND DL2 BST2 D 5 5 PQ16 RJK03B9D +5VPCU B PC94 PC102 4.7U/6.3V_6 G +5V_ALWP 0.1U/25V_4 DB Change PR100 *0_4 2200P/50V_4 +5V +/- 5% 35W/45W CPU Countinue current:9A/12A Peak current :12A/15A OCP minimum :15A/20A +3.3V +/- 5% Countinue current:6A Peak current:7.5A OCP minimum 9A +5VALW DB Change 35W CPU NA C PC238 5 POP PC96 3 2 1 DC-15G0M000 PC106 5 1.5uH PC100 3 2 1 45W CPU PC240 PR108 0_4 0.1U/25V_4 No POP PC243 1U/6.3V_4 DC-22C0M000 PC95 2 2.2uH PC104 1 35W CPU PC105 PAD PAD P/N PC91 42 41 Value 2 2 PC38 PC97 PC285 100U/25V L-F PL13 100U/25V L-F PC286 0.1U/25V_4 + 1 POP +VIN Place these CAPs close to FETs 150K/F_4 8 7 6 *0.1U/10V_4 2 5 4 3 2 1 CS41302FB00 0.1U/25V_4 130k 2200P/50V_4 45W CPU PR109 UDZ5V6B-7-F 4.7U/25V_8 No POP 4.7U/25V_8 CS41332FB06 PR99 2 1K_4 4.7U/25V_8 133k Place these CAPs close to FETs 1 35W CPU 1 +VIN 8206ON_LDO PQ16/PQ13 P/N LDOREFIN LDO IN N.C ONLDO VCC TON REF PR123 Value PR90 *0_4 2_6 B 2 +5VALW +3VPCU PGOOD2 PC99 1U/6.3V_4 1 PR124 *0_4/S PV change PR88 *0_4/S PD11 BAS316/DG 1 2 PGOOD1 PR129 PR131 10K_4 HWPG [35,39,41,42,43] SYSON +5VALW 1 100K_4 REF OT 2 PU17 5 4 +5VSUS PC112 2.2U/6.3V_6 VIN 1 GND 2 EN 6 PR235 *576/F_4 PC239 *0.1U/10V_4 3 PC245 *0.1U/10V_4 NTC need place under CPU Socket CPU Thermal protection at 90 +/-3 degrreC *0.22U/10V_6 PC252 A NTC *RT9726 PR237 *10K/F_NTC_0603 PR231 *0_4 A +VIN [25,31,39,41,42,43,44,45] +3VPCU [7,8,25,32,34,35,36,37,39,40,42,44,45,47] +5VPCU [32,35,39,40,41,42,43,44,45] MAINON [35,39,41,43,44,45] PR234 *100K/F_4 RTQLGEV"<"NZ517*Jwtqp"Tkxgt+ Swcpvc"Eqorwvgt"Kpe0 PD7 Size Custom Document Number Date: Wednesday, October 13, 2010 5 4 3 2 Rev 1A +5V/+3V (RT8206B) 1 Sheet 38 of 47 4 3 2 +5VPCU +VIN_1.05V_VTT +VIN PR58 3 4.7U/25V_8 4.7U/25V_8 0.1U/25V_4 3 2 1 PR1 PR162 2.2_8 *0_2/S + 4 PR228 4.02K/F_4 10K/F_4 PC251 PQ41 AON7702 PC190 1500P/50V_4 RDSon=14m ohm PR233 + PC24 PC88 PC234 PC3 C 5/12: for EMI request *10K/F_4 3 *100P/50V_4 0.1U/25V_4 5 0.1U/25V_4 232K/F_4 PR223 PV change 600 mils 0.1U/10V_4 DB change +1.05VVTT_S2 PL6 2.2UH/8A PR220 1 FB D +1.05V_VTT *0.1U/10V_4 14 RTDL PC214 2 PAD 8 PC203 *330U_2.5V_7343 17 16 DL TON PC202 2 EN/DEM PC192 PQ43 AON7410 4 5 NC RTTON PC191 2200P/50V_4 1U/6.3V_4 13 9 RT8209A 15 *0.33U/6.3V_4 C BST PGOOD PC244 PHASE RTLX 3 2 1 10/F_4 RTDH 11 RTFB MAINON RTEN 12 VOUT [35,38,41,43,44,45] 5 PR217 DH PGND PV change MAINON CS PC227 1 [41] 1.05V_VTT_PWRGD 1 *0_4/S VDD RTILIM 10 11.3K/F_4 HWPG_S2A 4 VDDP PU16 PR213 7 2 PR229 2 PR227 100K_4 1 BAS316/DG GND 2 NC PD17 HWPG RTBST 2_6 6 DB change UPB201212T-800Y-N RTBST_1 PR215 RTVDD 1U/6.3V_4 PC110 +3V +1.05V Volt +/- 5% Countinue current:6A Peak current: 8A OCP minimum: 9A PL10 PC226 10_6 1 D 5; 1 330U_2.5V_7343 5 Vo=0.75(R1+R2)/R2 2 PR232 H_VTTVID1 [6] 1 *1K/F_4 PR225 *0_4 PQ50 *MMBT3904-7-F H_VTTVID1=Low, 1V H_VTTVID1=High, 1.05V PR221 0_4 VCCP_SENSE [5] B B +1.8V +/- 5% Countinue current:1.2A Peak current:2A +3VPCU 4 VDD 1 PGOOD 6 GND 8 GND1 9 7 1 1U/6.3V_4 PC223 PR208 *0_4/S A 2 R2 PV change [35,38,41,42,43] VOUT 1.8VADJ PR206 R1 127K/F_4 PR207 PC218 PC53 PC215 0.1U/10V_4 *0.33U/6.3V_4 EN ADJ +5VPCU PC219 2 +1.8V 10U/6.3V_8 PU15 RT9025 10K/F_4 5 10U/6.3V_8 0.1U/10V_4 PR205 NC VIN VO=(0.8(R1+R2)/R2) R2<120Kohm A 100K/F_4 MAINON PC220 10U/6.3V_8 3 PC222 RTQLGEV"<"NZ517*Jwtqp"Tkxgt+ Swcpvc"Eqorwvgt"Kpe0 HWPG PD7 Size Custom Document Number 5 4 3 2 Rev 1A +1.05V/+1.8V (RT8204C) Date: Wednesday, October 13, 2010 1 Sheet 39 of 47 4 3 2 62 1 PV change PR78 SPHASE0_CORE SPHASE1_CORE SPHASE2_CORE 10U/6.3V_8 10U/6.3V_8 10U/6.3V_8 1U/6.3V_4 1U/6.3V_4 0.1U/10V_4 D 2 +5VPCU_GFX PR24 PC196 7.87K/F_4 IDES_N_CORE1 PC193 *0.022U/25V_4 4700PF/25V_4 PR175 PR38 PR35 3.09K/F_4 IDES_P_CORE1 7.87K/F_4 PR27 PC25 1 3 2 [5,46] VCC_SENSE 2 PR178 0_4 PR177 PC267 PR256 *10U/6.3V_8 2 VCCSENSE_1 +VCC_GFX PU20 *VT1317S SPHASE AVDD AVDD AVDD AVDD 1 *0.1uH_PCMC063T-R10MN PC144 PC147 PC138 PC146 PC139 PC298 PC299 PC300 1 VX_GFX 2 PC145 *22U/6.3V_8 DB[0] DB[1] DB[2] H6 H5 H4 H3 H2 H1 F6 F5 F4 F3 F2 F1 D6 D5 D4 D3 D2 D1 1 IDES_N IDES_P PL19 VX VX VX VX VX VX VX VX VX VX VX VX VX VX VX VX VX VX *22U/6.3V_8 SPHASE_GFX G1317AGND B6 PR141 B5 B4 *10_6 A3 B3 +5VPCU_GFX 1 VSSSENSE_1 1 IGPU Power 2 A6 A1 B1 2 1 0_4 VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH A5 A4 DB0_GFX DB1_GFX DB2_GFX 1 1 *10U/6.3V_8 [5,46] VSS_SENSE *2200P/50V_4 AVDD AVDD AVDD AVDD IDES_N_GFX1 IDES_P_GFX1 C DB change 2 *0.1U/10V_4 2 PC230 UMA co-layout *0.1U/10V_4 PU14 VT1317S SPHASE H6 H5 H4 H3 H2 H1 F6 F5 F4 F3 F2 F1 D6 D5 D4 D3 D2 D1 *10U/6.3V_8 1 PC235 2 PC233 E4 E5 E6 C4 C5 C6 G4 G5 G6 J4 J5 J6 DB change DB[0] DB[1] DB[2] 2 PC231 *22U/6.3V_8 *1U/6.3V_4 *1U/6.3V_4 E4 E5 E6 C4 C5 C6 G4 G5 G6 J4 J5 J6 VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH PC31 PR173 *10K_4 7.87K/F_4 PR291 200_4 10_6 B5 B4 A3 B3 IDES_N IDES_P *10U/6.3V_8 PC228 *10U/6.3V_8 5 VX1_CORE 4 GND GND GND GND GND GND GND GND GND GND GND GND PV change +5VPCU C1317AGND B6 PR26 +5VPCU_VCORE PR14 7.87K/F_4 *10U/6.3V_8 0.1U/10V_4 A6 A1 B1 VX VX VX VX VX VX VX VX VX VX VX VX VX VX VX VX VX VX AGND AGND IDES_P_CORE 1316AGND *10U/6.3V_8 1U/6.3V_4 A5 A4 DB0_CORE DB1_CORE DB2_CORE SPHASE2_CORE 1000P/50V_4 B IDES_N_CORE2 IDES_P_CORE2 PC18 PV change PC271 PC68 0.1U/10V_4 1 VX2_CORE 6 VX0_CORE 2 J3 J2 J1 G3 G2 G1 E3 E2 E1 C3 C2 C1 1000P/50V_4 PC274 B2 A2 PC26 IDES_N_CORE PC149 PC280 *10U/6.3V_6 *0.1U/10V_4 *2200P/50V_4 2 Discrete Only change to 0ohm 3.09K/F_4 IDES_P_CORE0 7.87K/F_4 GND GND GND GND GND GND GND GND GND GND GND GND PR32 PC276 J3 J2 J1 G3 G2 G1 E3 E2 E1 C3 C2 C1 *10K_4 PC283 1 1 1 3 VX0_CORE 2 PL15 *50nH/50A DB change DB change PR171 AGND AGND 1 PC12 PC200 B2 A2 PR42 DCMDRP2 PC189 0.1U/10V_4 *97.6K/F_4 4700PF/25V_4 PR185 PC187 1U/6.3V_4 7.87K/F_4 *0.022U/25V_4 PC9 10U/6.3V_8 PC208 IDES_N_CORE0 PC195 PC182 10U/6.3V_8 PR20 PC7 PC87 *22U/6.3V_8 PJP3 *POWER_JP/S 2 *10U/6.3V_8 1 2 *10U/6.3V_8 2 *10U/6.3V_8 GND GND GND GND GND GND GND GND GND GND GND GND 1 VX1_CORE 4 +5VPCU [35] PC236 2200P/50V_4 VRON PC75 PL14 50nH/50A B1317AGND PR297 1K_4 PC229 *22U/6.3V_8 2 PC302 PV change PC232 +VCC_CORE *0_4/S 1 PQ64 DMN601K-7 PC78 2 PR31 H6 H5 H4 H3 H2 H1 F6 F5 F4 F3 F2 F1 D6 D5 D4 D3 D2 D1 2 AVDD AVDD AVDD AVDD PC34 *0_4/S PU13 VT1317S SPHASE VX VX VX VX VX VX VX VX VX VX VX VX VX VX VX VX VX VX *10U/6.3V_8 DB[0] DB[1] DB[2] B1317AGND B6 PR25 B5 B4 10_6 A3 B3 AGND AGND +5VPCU_VCORE A6 A1 B1 DB change 1 E4 E5 E6 C4 C5 C6 G4 G5 G6 J4 J5 J6 VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH DB0_CORE DB1_CORE DB2_CORE SPHASE1_CORE IDES_N IDES_P J3 J2 J1 G3 G2 G1 E3 E2 E1 C3 C2 C1 GND GND GND GND GND GND GND GND GND GND GND GND AGND AGND AVDD AVDD AVDD AVDD A5 A4 B2 A2 SPHASE IDES_N_CORE1 IDES_P_CORE1 0.1U/10V_4 PU12 VT1317S H6 H5 H4 H3 H2 H1 F6 F5 F4 F3 F2 F1 D6 D5 D4 D3 D2 D1 1 0.022U/25V_4 DB[0] DB[1] DB[2] VX VX VX VX VX VX VX VX VX VX VX VX VX VX VX VX VX VX 200P/50V_4 8.25K/F_4 PC188 E4 E5 E6 C4 C5 C6 G4 G5 G6 J4 J5 J6 VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH PR30 IDES_N IDES_P 10U/6.3V_8 PR16 PR160 *51.1K/F_4 442K/F_4 PC17 *10U/6.3V_8 *0.022U/25V_4 DB1_GFX PR9 0_4 PC2 2200P/50V_4 0.1U/10V_4 1 1 2 90.9K/F_4 PC184 A1317AGND 1000P/50V_4 7.87K/F_4 PR6 5/12: Add for GPU cap. [5,46] VSS_AXG_SENSE 2 [5,46] VCC_AXG_SENSE 2 PR179 *0_4 PR180 1 VSS_AXG_SENSE_1 1 VCC_AXG_SENSE_1 B *0_4 *0_4/S PR292 0_4 *0_4/S G1317AGND 1 0_4 2 PC6 PC21 7.87K/F_4 PR103 1 PC32 IREPORT_CORE PC181 Discrete Only NA PR165 VRON 2 VCC_AXG_SENSE_1 VSS_AXG_SENSE_1 VSSSENSE_1 VCCSENSE_1 +1.05V_VTT DCMDRP1 PR296 10K_4 +5VPCU 1316AGND PR19 A1317AGND B6 PR36 B5 B4 +5VPCU_VCORE 10_6 A3 B3 SPHASE0_CORE 3 PC11 A6 A1 B1 DB1_CORE DB2_CORE +5VPCU PR295 1K_4 IDES_P_CORE IDES_N_CORE DB change A5 A4 DB0_CORE IDES_P_CORE DB change 44.2K/F_4 DB1_CORE 2.94K/F_4 PR47 IDES_N_CORE0 IDES_P_CORE0 DCMDRP2 DCMDRP1 PR8 +1.05V_VTT 1316AGND Discrete Only 0ohm 9/29: MV modify SPHASE_GFX DB0_GFX DB1_GFX DB2_GFX TEMPSENSE_GFX TEMPSENSE IDES_P_GFX IDES_N_GFX 44.2K/F_4 IREPORT_GFX IREPORT_CORE [46] VCORE_IMON PR18 DB change 0_4 PC5 DB change PQ62 PC13 1316AGND DB change PC186 PR11 PR12 0_4 DB change PC16 1U/6.3V_4 49 48 47 46 45 44 43 42 41 40 39 38 37 VT1316MAF 36 35 34 33 32 31 30 29 28 27 26 25 PC180 J3 J2 J1 G3 G2 G1 E3 E2 E1 C3 C2 C1 IREPORT_GFX VGT_IMON QFN PR60 DB1[1] DB1[2] SPHASE2 DB2[0] DB2[1] DB2[2] TEMP_SENSE2 TEMP_SENSE1 IDES2_P IDES2_N R_REF2 IMON2 PC4 B2 A2 1316AGND [46] PC27 0.1U/10V_4 DB change R_SEL[1] R_SEL[0] GND VDIO VCLK VR_ENABLE ALERT# VR1_READY VR2_READY VR_TT1# GND VDD5 PC183 3 10_6 GND_TAB R_SEL[2] R_SEL[3] R_SEL[4] R_SEL[5] R_SEL[6] VDD3 VDD3 R_OSC SPHASE1[0] SPHASE1[1] SPHASE1[2] DB1[0] 1 2 3 4 5 6 7 8 9 10 11 12 DB0_CORE DB1_CORE DB2_CORE SENSE1+ SENSE1SENSE2SENSE2+ NC DCMDRP1 DCMDRP2/STB NC IMON1 R_REF1 IDES1_N IDES1_P 1316AGND +5VPCU PU1 13 14 15 16 17 18 19 20 21 22 24 23 PC303 *49.9/F_4 1316AGND *56_4 PR21 DB change 1316AGND PR41 0_4 PR46 130/F_4 56_4 10K_4 PR53 10K_4 PR56 PR192 PR49 PR174 [5] VR_SVID_DATA [5] VR_SVID_CLK [35] VRON [5] VR_SVID_ALERT# [7] IMVP_PWRGD [35] GFX_HWPG [3,35] H_PROCHOT# +1.05V_VTT *0.1U/10V_4 +3V 5/12: Modify for DG PC38 1U/6.3V_4 35W CPU 0ohm 0.1U/10V_4 D C + PC8 *0_4 10U/6.3V_8 PR75 +5VPCU 10U/6.3V_8 1316AGND 2 *0_4/S 3.74K/F_4 39.2K/F_4 27.4K/F_4 32.4K/F_4 39.2K/F_4 32.4K/F_4 49.9K/F_4 DMN601K-7 PR80 PR79 PR81 PR77 PR76 PR70 PR65 +5VPCU 1 f=1/N*(39.5n+R*2.09n/k) N=4 (1-phase & 2-phase) N=3 (3-phase) 10_6 PR2 +5VPCU_VCORE 220U/6.3V_7343 PR203 +3VPCU 1316AGND 10U/6.3V_8 DB change 0.1U/10V_4 5/12: change to 27.4k by power request 178K/F_4 *22U/6.3V_8 PC217 *10U/6.3V_8 5 CPU Core(VT1316M+VT317S) 1000P/50V_4 C1317AGND PQ65 ME2301 PC22 2 PC301 0.01u/50V_4 1000P/50V_4 PR17 7.87K/F_4 PR22 PC198 7.87K/F_4 H_PROCHOT# IDES_N_CORE2 PC199 PR170 *0.022U/25V_4 4700PF/25V_4 PR186 TEMPSENSE 5.9K/F_4 *10K_4 PR34 7.87K/F_4 7.87K/F_4 1000P/50V_4 PC178 *2200P/50V_4 1 2 PR193 100K_4 NTC 40.2K/F_4 2200P/50V_4 A PR200 PC266 *2700P/50V_4 3.09K/F_4 IDES_P_CORE2 PC30 PC213 TEMPSENSE_GFX *2.49K/F_4 IDES_N_GFX 1 PR294 *130K/F_4 PR43 PR293 *130K/F_4 35W CPU NA PR265 PR267 *100K_4 NTC PR194 PR181 *59K/F_4 H_PROCHOT# 2 3 DB1_CORE PR258 *3.16K/F_4 PR261 PC148 *11.5K/F_4 *0.022U/25V_4 *4700PF/25V_4 PR140 IDES_P_GFX DB change PR257 PR260 *10K_4 *3.16K/F_4 IDES_N_GFX1 PC268 PR259 *3.09K/F_4 IDES_P_GFX1 *11.5K/F_4 PC265 PUT COLSE TO V_GT HOT SPOT Discrete Only NA A DB change *2700P/50V_4 PUT COLSE TO VCORE HOT SPOT RTQLGEV"<"NZ517*Jwtqp"Tkxgt+ Swcpvc"Eqorwvgt"Kpe0 PD7 Size Custom Document Number 4 3 2 Rev 1A +VCC_CORE (ISL95831) Date: Wednesday, October 13, 2010 5 1 Sheet 40 of 47 5 4 3 2 PR37 62872PVCC +VIN_VCCSA 10_6 BOOT 18 PHASE 16 2 PR230 [5] VCCSA_SEL 62872VID0 1 *0_4/S EN PU11 ISL62872 5 VID1 6 VID0 LGATE 1 62872LGATE 7 SREF OCSET 14 62872_OCSET PL16 2.2UH/8A PR57 2.2_8 PR204 *0_2/S *0_2/S PR209 *0_2/S 0 1 0.8V 1 0 0.8V 1 1 0.8V 62872SET1 62872SET2 PR167 34.8K/F_4 12 62872FB RDSon=14m ohm 2 FB 1500P/50V_4 SET1 VO 62872VO 3 2 1 9 11 0.9V PR161 0_4 62872PG 0 SET0 + PC59 13 PR190 18.7K/F_4 PC209 PC225 PC241 0.01U/50V_4 PR214 100_4 PR189 C 18.7K/F_4 PR187 PR168 280K/F_4 100/F_4 PR7 *0_4/S PR236 62872FB_SENSE 2.49K/F_4 PR188 PR176 4.12K/F_4 1 0 8 SET2 VCCSA 62872SET0 10 C VCCSA_SEL 0.068UF/10V_4 PC176 PGOOD 4 PQ7 AON7702 PV change 500 mils PR212 0.1U/10V_4 PV change 4 4 PC211 PR191 62872BTRC 62872BOOT 1 2 2_6 0.1U/25V_4 62872PHASE 1 62872EN 1 *0_4/S 62872UPGATE D +VCCSA 330U_2.5V_7343 NC 5 17 5 2 PR166 0.1U/25V_4 20 UGATE *0.22U/10V_4 [39] 1.05V_VTT_PWRGD 4.7U/25V_8 GND PC72 0.1U/25V_4 PGND 3 PC65 2200P/50V_4 2 PC71 3 2 1 PC185 100K_4 PC76 PQ8 AON7410 PR172 +3V UPB201212T-800Y-N PVCC2 VCC 15 19 1U/6.3V_4 D +VIN PL3 PC19 10U/6.3V_8 PC197 63 +VCCSA +/- 5% Countinue current:4A Peak current:6A OCP minimum 8A +5VPCU 62872VCC 1 VCCUSA_SENSE [5] 0_4 PC201 2700P/50V_4 2 PV change [35,38,39,42,43] HWPG +5VPCU +VIN_1.05V PR145 1U/6.3V_4 PR279 4.02K/F_4 A PV change 500 mils 0.1U/25V_4 4.7U/25V_8 *4.7U/25V_8 2.2uH/8A PQ58 AON7702 PR284 2.2_8 PR275 *0_2/S + 4 PC294 PR277 10K/F_4 PC292 RDSon=14m ohm *100P/50V_4 0.1U/25V_4 2200P/50V_4 +1.05V_S2 PL21 Vo=0.75(R1+R2)/R2 PC291 PC290 0.1U/10V_4 FB +1.05V 390U/2.5V_6X5.8ESR10 PAD PC163 B 1 232K/F_4 RTDL1.05V 3 PC295 3 2 1 8 PC161 1500P/50V_4 EN/DEM TON PC162 +1.05V Volt +/- 5% Countinue current:4A Peak current: 6A PC296 OCP minimum: 8A 4 PQ59 AON7410 5 13 DL BST 9 2 VDDP 16 PR283 RTTON1.05V RTFB1.05V PR282 *1M/F_4 PHASE RTLX1.05V 3 2 1 17 RTDH1.05V 11 VOUT RTEN1.05V 15 10/F_4 12 1 MAINON PGND PR281 [35,38,39,43,44,45] NC GND 5 PC293 DH RT8209A 7 *0_4/S CS HWPG_S2A1.05V 4 PGOOD NC HWPG 1 RTILIM1.05V10 6 [35,38,39,42,43] 2 10.5K/F_4 14 PR278 PR276 RTBST1.05V 2_6 VDD PU22 PV change RTBST_11.05VPR280 5 RTVDD1.05V 1U/6.3V_4 PC156 +VIN PL22 UPB201212T-800Y-N 0.1U/25V_4 B 5/12: modify footprint -SMT for Layout request 2 PC289 10_6 A RTQLGEV"<"NZ517*Jwtqp"Tkxgt+ Swcpvc"Eqorwvgt"Kpe0 PD7 Size Custom Document Number Date: Wednesday, October 13, 2010 5 4 3 2 Rev 1A +1.05V_VTT (VT358) 1 Sheet 41 of 47 2 3 VGA Core 4 +5VPCU 3 1 3 1.12V 2200P/50V_4 0.1U/25V_4 4.7U/25V_8 4.7U/25V_8 4.7U/25V_8 *4.7U/25V_8 0.1U/25V_4 RDSon=5m ohm PC143 + 2 PC135 2 PC134 0.1U/10V_4 + PC136 330U_2.5V_7343 + PC253 1 1 *0_2/S 1 PR241 2.2_8 S 330U_2.5V_7343 10K/F_4 G PQ56 RJK03D2D PR245 600 mils 2 5 5 1 2 3 +VGACORE PL18 0.36U28A(ETQP4LR36AFC) 5 4 S A PR254 D G 6/11 change 15k to 10k PQ55 RJK03D2D 2 PQ53 DMN601K-7 High 1.05V Medium 0.95V Low CTRL1 Low 4 +VGACORE +/- 5% Countinue current:19A Peak current:21A OCP minimum 26A S D PR247 10K/F_4 *100P/50V_4 PC117 B 0.90V 1 1 5/10 NA GFX_CORE_CNTRL1 High 8208RTD11 PC256 PC126 Calpilano Pro Setting PQ54 *DMN601K-7 Park XT Setting 5 2K/F_4 PC123 PR251 10K_4 2 [17,18] GFX_CORE_CNTRL1 D1 PR238 PC122 Vo=0.75(R1+R2)/R2 2 PQ52 DMN601K-7 B 232K/F_4 8208RTDL1 30K/F_4 PC127 330U_2.5V_7343 +3VPCU 8208TON1 8 8208RTFB1 PC128 2200P/50V_4 7 8208VOUT1 3 PR244 10K_4 4 S G PC120 PR239 16 DL PR249 8208RTD10 4 D G 1 2 3 G1 D PQ23 RJK03B9D 1 2 3 VDDP VDD 14 PQ24 RJK03B9D 1 2 3 TON PAD BST EN/DEM 17 RT8208A [17,18] GFX_CORE_CNTRL0 13 2 9 8208RTLX2 D0 PC255 0.1U/10V_4 +3VPCU 11 FB PV change 12 PHASE 6 10K_4 *0_4 DH PGOOD CS 1 8208RTPG1 4 *0_4/S 8208RTEN1 15 3 PR240 10 7.87K/F_4 2 PR243 8208RTDH1 VOUT 0_4 R369 BACO_EN 2 BAS316/DG R35 [10,35,43] DGPU_PWR_EN [47] 1 HWPG DGPU_PWROK PC261 1_6 8208CS1 64 +VIN PL4 8208BST1_1PR252 G0 [35,38,39,41,43] [9,10,35,43,47] +VIN_VGACORE 8 PC262 1U/6.3V_4 PU19 PR253 7 UPB201212T-800Y-N 1 PR242 10K_4 PD13 6 10_6 5 PC125 1U/6.3V_4 A 8208RTVDD1 +3VSUS 5 PD20 RB501V-40 2 1 8208RTBST1 PR134 0.1U/25V_4 1 0.90V CTRL0 Vo 0 0 1.05 0 1 1 1 0 0.95 1 1 0.9 +12VALW 1 0.9 PR187 PR188 PQ58 PQ59 PQ61 PQ25 PC122 PC121 ㎏㎝𤏐 PC150 3VGFX_OND PC122 PQ31 *DMN601K-7 PQ57 DMN601K-7 2 C 4 VDD PC260 1 PGOOD PR246 *0_4/S 2 R2 PV change 8 9 1.2VADJ1.8V 1 9/29: MV modify GND GND1 7 PC258 1U/6.3V_4 D 6 R1 PR218 PC247 PC288 PC248 0.1U/10V_4 +5VPCU 1U/6.3V_4 20K/F_4 VOUT PC153 PC152 C907 +1.8V_VGA 10U/6.3V_8 EN ADJ 2 [35,43,47] DGPU_PR_EN 5 10U/6.3V_8 0.1U/10V_4 PU18 RT9025 DGPU_PR_EN NC VIN PR226 127K/F_4 D VO=(0.8(R1+R2)/R2) R2<120Kohm +VIN [25,31,38,39,41,43,44,45] +3VPCU [7,8,25,32,34,35,36,37,38,39,40,44,45,47] +5VPCU [32,35,38,39,40,41,43,44,45] +1.5VSUS [3,5,11,13,14,43,45] +3V_VGA [16,17,18,19,27] +VGACORE [19] +1.5V_VGA [16,19,20,21,22,23,47] +1.8V_VGA [15,17,19] +12VALW [25,34,37,44,45] 100K/F_4 PC257 10U/6.3V_8 3 PC259 DGPU_PWROK RTQLGEV"<"NZ517*Jwtqp"Tkxgt+ Swcpvc"Eqorwvgt"Kpe0 Size PD7 2 3 4 5 6 7 Document Number Rev 1A GPU CORE(ISL6264) Date: 1 7/1 SI Add C *0.01U/25V_4 2 +1.8V +/- 5% Countinue current:1.2A Peak current:3A +3VPCU PR250 1 PR144 1M_4 PQ32 PDTC144EU +3V_VGA PC151 DGPU_PWR_EN 2 1 PR190=6.81k ( CS26812FB01 ) PR195=9.09k ( CS29092FB02 ) PQ24=RJK03B9D( BAM03B90000 ) PQ60=RJK03D3D( BAM03D30000 ) 1 弭鯱 PC120 PC121=CH733RM8831 0.24A 2 3 弭鯱 3 PQ30 ME3424D 1 ㎏㎝𤏐 PR211 1M_4 PR143 *22_8 PR142 1M_4 *220P/50V_4 0 +3VPCU *10U/6.3V_8 1.12 0.1U/10V_4 0 0.1U/10V_4 0 +3V_VGA 1 2 5 6 +VIN 4 Vo 3 CTRL1 3 CTRL0 Wednesday, October 13, 2010 Sheet 42 8 of 47 1 2 3 4 +1.5VSUS PR112 4 PQ44 RJK03B9D 23 *0.1U/50V_6 2_6 GND 5 VTTREF PHASE 20 1116LL 7 NC LGATE 19 1116DRVL +1.5VSUS_1 PQ38 RJK03D3D PR210 2.2_8 RB501V-40 PR106 [35,45] [35,38,39,41,42] 100K_4 SUSON11 SUSON HWPG 13 HWPG + 18 CS_GND 17 VDDP 15 PC77 1U/6.3V_4 S5 PGOOD PR61 *0_2/S G 4 S PC224 PR96 10_6 PC90 0.1U/10V_4 +VIN PR101 1116TONSET 12 619K/F_4 PR107 10K/F_4 TON CS 16 1116CS PC66 PC57 6/9: DB2 del PC297, PC298 PR86 7.5K/F_4 9 FB DEM 6 8 VDDQSNS VDD 14 V5FILT B PC89 RT8207AGQW PC80 1U/6.3V_4 PR105 10K/F_4 *100P/50V_4 B PGND S3 +5VPCU 2200P/50V_4 10 2 +1.5VSUS PL8 1U18A(PCMB103T-1R0MS) 0.1U/25V_4 1 2 3 1 MAINON S 2 D PD10 [35,38,39,41,44,45] 1 1 PC82 0.033U/10V_4 1116VBST 2 [5,13,14] DDR_VTTREF VBST G 4 PC58 PR66 0.1U/10V_4 25 22 1116DRVH A 1 ( 3mA ) 21 PC205 2 UGATE PC48 330U_2.5V_7343 GND PC212 1 2 3 VTTGND 3 5 1 PC29 2200P/50V_4 VLDOIN *4.7U/25V_8 VTTSNS 4.7U/25V_8 VTT D 10U/6.3V_8 10U/6.3V_8 PC70 PC50 0.1U/25V_4 2 PC61 DB Change *0_4 MODE 24 A +1.5V +/- 5% Countinue current:6A Peak current:12A OCP minimum 15A PR89 0_4 PU4 +VIN_CHARGER 5 ( VTT/2A ) +0.75V_DDR_VTT 65 5 SG & Discrete Only +1.0V +/- 5% Countinue current:1.7A Peak current:3A +1.5VSUS +1.0V_VGA VDD 1 PGOOD PC129 5 VOUT 6 GND 8 GND1 9 PC133 PC132 PC130 0.1U/10V_4 1U/6.3V_4 1 2 DGPU_PR_EN [35,42,47] C442 *0.1U/10V_4 4 ADJ +5VPCU PC137 EN NC 7 6/9: DB2 modify 2 1.2VADJ1.0VPR138 2 +3V PU7 RT9025 1 10K/F_4 2 DGPU_PWR_EN VIN 1U/6.3V_4 [10,35,42] PC124 0.1U/10V_4 PR255 PC131 10U/6.3V_8 3 6/9: DB2 modify 10U/6.3V_8 C 10U/6.3V_8 C R1 25.5K/F_4 PR139 [9,10,35,42,47] [9] DGPU_PWROK_1 6/9: DB2 modify +5VPCU C439 0.1U/10V_4 2 1 C481 0.1U/10V_4 2 1 2 1 2 C483 0.1U/10V_4 PR137 100K/F_4 VO=(0.8(R1+R2)/R2) R2<120Kohm *0_4 PC297 *0.33U/6.3V_4 D 1 +3V D R2 PR288 PV EMI Request 8/16 PV EMI Request 0_4 1 10/13 PV2 EMI request DGPU_PWROK +3V [3,7,8,9,10,11,13,14,18,19,25,26,27,28,29,30,31,32,33,34,35,36,37,39,40,41,45,46,47] +VIN [25,31,38,39,41,42,44,45] +5VPCU [32,35,38,39,40,41,42,44,45] +1.5VSUS [3,5,11,13,14,45] +1.0V_VGA [15,17,19] +0.75V_DDR_VTT [13,14,45] C448 *0.1U/10V_4 MV EMI Request RTQLGEV"<"NZ517*Jwtqp"Tkxgt+ Swcpvc"Eqorwvgt"Kpe0 PD7 Size Custom Document Number Date: Wednesday, October 13, 2010 1 2 3 4 Rev 1A DDR3 (RT8207) 5 Sheet 43 of 47 3 Do Not add test pad on BATDIS_G signal PR119 8681_ACAV 2 ACAV 8681HDR LX 14 8681LX LDR 16 8681COMP 8 PQ37 AON7702 ICHM 4 1 COMP 2 1 UDZ5V6B-7-F 1 *100P/50V_4 2 2 *100P/50V_4 0.1U/25V_4 4.7U/25V_8 PC23 PC41 PC15 2200P/50V_4 PC33 PC40 PC210 PC118 PR198 *0_2/S PR197 *0_2/S PD1 PR118 PR116 10_4 10_4 8681CSP 8681CSM PR130 PC107 0.01U/50V_4 ACOK_IN [35] 1 SYS_I 2 10_4 B PC264 0.01U/50V_4 PR133 3 2 8681ICHP 8681ICHM PC98 2 2 6 1 PC114 0.47U/10V_4 1 2 1 0.01U/50V_4 PR120 0_4 5 4 0.1U/25V_4 0.1U/25V_4 4.7U/25V_8 5 8681LR PC103 1 3 +BATCHG PR199 0.02/F_1206 PR10 2.2_8 5 PC81 1U/25V_8 PQ19 IMD2 Place this cap close to EC 6/9: DB2 modify footprint PQ42 AON7410 3 2 1 VAC 1 Place this cap close to EC PC43 C 4 ICHP BAS316/DG PR113 12.4K/F_4 PC44 PC35 PC140 4 8681LDR IAC 2 UDZ5V6B-7-F 2 13 7 MAINON 1 GND [35,38,39,41,43,45] PC39 TEMP_MBAT [35] 1K_4 PC28 PCMC063T-6R8MN OZ8681 DCIN PD18 B HDR PU6 10_8 BAS316/DG PC141 0.1U/10V_4 PC206 PD2 PL5 8681_ACAV 9 100K_4 17 PR114 75K/F_4 PC207 PR102 1 PD19 AD_AIR PD6 RB501V-40 PR104 PC84 2_6 8681B_2 8681B_1 12 1U/6.3V_4 PD7 BAS316/DG [35] 1U/10V_4 100K_4 +VAD_1 2 +VIN_CHARGER PC83 2 1 8681_VDDP D PR45 10K_4 2 SDL PR126 +VAD_1 PD9 BAS316/DG 2 1 8 BP02083-B79B5-9H DFHD08MR096 bat-bp02083-b6ab5-7h-8p-l-v 0.1U/25V_4 ACIN 7 8 1 ACIN 7 6 1 2 [35,45] 5 RB501V-40 +VA 1M_4 5 PR44 8681_VDDP 0.1U/50V_6 11 *0_4/S PR50 +VA SCL PR97 100_4 BST PR115 MBDATA 9 4.7U/25V_8 PQ14 PDTC144EU 6/11: DB2 modify for power request 10 *0_4/S 9 4.7U/25V_8 MBCLK PR62 1K_6 PC93 2 1 2.2U/10V_6 PR117 4 PR39 330_4 4.7U/25V_8 1 6 1M_4 4 B_TEMP_MBAT 6 PD3 4.7U/25V_8 MBATLED0# [35] MBCLK 4.7U/25V_8 2 1 *0.1U/25V_4 PC85 PC51 1U/6.3V_4 8681IAC 18681IAC C 3 PR63 ACIN 1M_4 MBDATA [35] PL2 UPB201212T-800Y-N 5 1 PQ5 Q1 UMT1N Q2 PR64 2 2 +5VPCU *2.43K/F_6 3 3 PR287 PQ2 2 [35] 1000P/50V_4 PQ61 1 *DMN601K-7 PR111 10_4 8681IACM MBATLED0 PR110 10_4 10 SMC 1 1 PR29 1U/10V_4 1 PQ1 DMN601K-7 1 4 3 *0_4/S ACOK_IN PD5 BAS316/DG 2 1 VDDP 1K/F_6 2ACOK# PR51 220K_4 2 PR286 *1M_4 +VAD 8681_VDDA PQ60 *PDTC144EU 6 2 PQ15 PDTC144EU PC108 VDDA 3 +12VALW PR55 *100K_4 PR52 CSIN PR28 PR201 *0_2/S 3 PR23 100_4 3 10 PC242 PL1 PD4 8681_VDDA 0.1U/25V_4 8681_VDDP MBATLED0# 3 +3VPCU PR40 330_4 IACM AC_LED_ON# [35] 2 2 SMD PC36 BATDIS_G PR195 *0_2/S 2 2 +VAD PR48 220K_4 CN17 BATT+ UPB201212T-800Y-N PC45 +VIN *UPB201212T-800Y-N 150K/F_4 8 7 6 5 3 2 1 PR33 BATDIS_G 1 +VH28 5 PR94 +5VPCU *100_4 CSIP 3 +5VPCU 1 *0.1U/25V_4 PC92 PR15 1 2 3 4 P1003EVG PR196 RC2512-R010 1 2 8681IACP 1K/F_6 ACOK_IN UPB201212T-800Y-N PL7 PQ45 PV change PC20 0.22U/25V_8 15 4 0.1U/25V_4 0.1U/25V_4 *10K/F_6 +VA PR95 PC14 0.1U/50V_6 1 PR285 AC_LED_ON PC204 0.1U/25V_4 IDEA_G *0.1U/25V_4 PC67 PC46 2 UPB201212T-800Y-N 5 6 8 GND GND GND 3 GND MMBT3904-7-F 4 PC47 D 100K_4 AD_ID PQ40 P0603BDG 4 3 1 3 UPB201212T-800Y-N PL11 PD16 P4SMAJ20A 2 1 PQ39 FDMC4435BZ 1 5 2 3 100K_4 VDD LED2 VDD LED1 VDD 2 1 +VAD PL12 17.3" DFHD08MR096 PL9 P4SMAJ20A +VA 7 9 10 1 CN18 DC-IN CONN +BATCHG C905 6/30:SI Add +PRWSRC 66 1 15.6" DFHD08MR094 *10U/25V_0805 5/12: Mpdify footprint -SMT for layout request IACP 6/28: SI modify footprint AD_ID 2 +VIN 0.01U/25V_4 4 0.01U/25V_4 5 TOP DC_JACK 65W/90W PQ18 PDTC144EU 0_4 +VAD PD12 2 D/C#_S6A 1 2 D/C# [35] 1 *BAS316/DG PC115 *10U/6.3V_8 A A +VA [45] +VH28 [45] +VAD_1 [45] +3VPCU [7,8,25,32,34,35,36,37,38,39,40,42,45,47] +5VPCU [32,35,38,39,40,41,42,43,45] +BATCHG [45] RTQLGEV"<"NZ517*Jwtqp"Tkxgt+ Swcpvc"Eqorwvgt"Kpe0 PD7 Size Custom Document Number 5 4 3 2 Rev 1A Charger (BQ24704) Date: Wednesday, October 13, 2010 1 Sheet 44 of 47 5 4 3 PD14 1 MAINON 1 1 [35,44] PR153 *0_4/S 0.47u/25V_6 D +VAD_1 ON1 PG 2 ON2 VSENSE 3 ON3 REG 2 15 G5934PG PV change PR154 750K/F_4 4/20 Del 1 17 VOUT ACIN 2 G5934CN 19 PC167 1U/35V_6 PC168 2 1 14 G5934VSENSE C982,C992 for dummy net 2 [35,38,39,41,43,44] MAINON CN VIN 20 0.1U/25V_4 [35] LAN_POWER G5934CP 1 2 PC164 0.1U/25V_4 2 1 PC160 18 D PV change 2 1 *RB501V-40 PR151 *0_4/S PR146 22_6 CP 2 PR148 *22_6 16 PD15 +BATCHG +VA [44] +5V [7,8,11,19,25,26,27,29,30,32,34,36,37] +VIN [25,31,38,39,41,42,43,44] +1.5V [5,11,13,36] +1.8V [5,8,11,39] +3VS5 [3,7,8,9,10,11] +5VS5 [11] +VH28 [44] +VAD_1 [44] +3VSUS [32,35,36,42] +5VSUS [25,38] +3VPCU [7,8,25,32,34,35,36,37,38,39,40,42,44,47] +5VPCU [32,35,38,39,40,41,42,43,44] +12VALW [25,34,37,42,44] +BATCHG [44] +1.5VSUS [3,5,11,13,14,43] +3VLANVCC [33] +0.75V_DDR_VTT [13,14,43] +VAD *RB501V-40 67 1 +VH28 1 D_CAP 2 +VA 2 +12VALW +5VSUS ON4 7 G5934DISC3 2 DISC2 6 G5934DISC2 2 5 1 2 5 6 3 2 2 1 1 PR83 1M_4 MAIN_ONG 1 B MAIN_ONG [3,5] 6/29: SI add for EMI +5VPCU 1 5/3: modify for leakage *0.1U/10V_4 2 *0.1U/10V_4 *0.1U/10V_4 *0.1U/50V_6 C903 C904 *100P/50V_4 +3VLANVCC 7/1 : SI add for EMI 1 C909 C911 *220P/50V_4 C910 *220P/50V_4 C908 *220P/50V_4 *10U/6.3V_8 2 PC113 *220P/50V_4 1 C912 2 0.1U/10V_4 2 2 0.1U/10V_4 2 C902 *1500P/50V_4 1 2 5 6 4 1 S5_ONG C901 +5V 0.17A PC109 PC42 C900 +3VS5 PQ17 ME3424D 1 1 2 PC37 *10U/6.3V_8 PR128 1M_4 1 1 2 1 1 3 1 +5VS5 PC52 C899 +1.5VSUS PC101 3 10mA PQ6 DMN601K-7 2 A 0.1U/10V_4 2 2200P/50V_4 2 PQ20 DMN601K-7 3 3 3 2 PQ9 DMN601K-7 PC49 2 PQ3 DMN601K-7 S5_OND 1 1 PR73 1M_4 PR127 22_8 3 +VIN +3VPCU *0.1U/10V_4 +5VPCU +3VS5 0.1U/10V_4 +5VS5 +5VPCU 2 +5VPCU 1 +3VS5 1 0.1U/10V_4 PC263 *10U/6.3V_8 PC157 PR122 1M_4 A RTQLGEV"<"NZ517*Jwtqp"Tkxgt+ Swcpvc"Eqorwvgt"Kpe0 8/16 : PV add for EMI PD7 Size Custom Document Number 4 3 2 Rev 1A Dis-charge IC (P2806) Date: Wednesday, October 13, 2010 5 PQ51 DMN601K-7 2 [5] +VIN 1 PQ11 *DMN601K-7 PQ10 DMN601K-7 +12VALW PQ21 PDTC144EU PQ4 *DMN601K-7 PR248 22_8 1 PC74 2 2 PC64 *0.1U/10V_4 MAIND PC119 0.1U/10V_4 2 PR69 *22_8 1 PC166 2200P/50V_4 +3VLANVCC PQ34 ME3424D +0.75V_DDR_VTT 3 PR84 1M_4 3 +1.5V *10U/6.3V_8 0.67A PC171 *10U/6.3V_8 1 2 5 6 LAN_ON 3 +1.8V PR67 *22_8 0.5A 3 4 3 2 1 PQ12 *ME3424D +5V 0.1U/10V_4 PC155 2 6 5 2 1 +1.5V +VIN PC60 3 6A PQ36 AON7410 PC172 PR54 22_8 S5_ON 4 PC142 0.1U/10V_4 PQ22 ME3424D PQ26 *DMN601K-7 [35] C 5/13: reserve +1.5VSUS 1 +3V 3 4 2 3 1 2 PR136 *1M_4 *10U/6.3V_8 PC121 2 PV EMI Request 1 2 6 5 2 1 PC175 2200P/50V_4 1 3 PR135 *1M_4 21 10 1 +3VSUS C13 *0.1U/10V_4 +3VPCU PV change PC249 0.1U/10V_4 0.1A PR132 *22_8 0.1U/10V_4 PC116 B +5V +5VPCU PV change PU8 P2806 MAIND SUSD 1 2 +VIN C14 *0.1U/10V_4 2 PQ33 ME3424D *10U/6.3V_8 +3VSUS +5VSUS 1 *0_6/S PC169 2200P/50V_4 PR152 *0_6/S 3 4 +5VSUS +3VPCU PQ25 *DMN601K-7 0.1U/10V_4 1 *10U/6.3V_8 2 0.24A PC159 0.1U/10V_4 1 *0_6/S PR149 PC170 PC154 PC165 GND DRIVER2 DRIVER1 9 DISC4 +5VPCU PC173 2200P/50V_4 1 2 3 +3V MAIND3.3V 4 4 0.1U/10V_4 4.6A 12 PQ35 AON7410 PC158 G5934DISC4 8 DRIVER4 5 PV change DRIVER3 DISC1 *0_6/S 11 +3VLANVCC +3VPCU C 1 G5934DISC1 5 +1.5VSUS PR150 DISC3 0.1U/10V_4 4 PR147 2 C454 *0.1U/10V_4 PC174 1U/16V_4 MAINON +1.5VSUS PR155 100K/F_4 13 *0.1U/10V_4 SUSON 1 [35,43] 1 Sheet 45 of 47 5 4 3 2 68 1 D D PC179 PR68 *49.9K/F_4 IMONAGND IMONAGND 2 PR4 *7.32K/F_4 [40] VCORE_IMON +3V PR87 *49.9K/F_4 PC62 *0.1U/10V_4 PC1 3 PR169 *15K/F_4 PC10 *0.1U/10V_4 1 PU10 *G1214AT11U CPU_ICC [35] 5 CPU_VCC [35] *0.1U/10V_4 1 PU2 *G1214AT11U 5 PC73 *390P/50V_4 3 + PR82 *49.9K/F_4 4 - PC63 *390P/50V_4 [5,40] VCC_SENSE PR5 *15K/F_4 IMONAGND 2 PC55 *1000P/50V_4 4 + PR74 *49.9K/F_4 [5,40] VSS_SENSE - IMONAGND C *0.1U/10V_4 PR164 *45.3K/F_4 PR13 *45.3K/F_4 +3V C PC177 *0.1U/10V_4 IMONAGND IMONAGND IMONAGND IMONAGND IMONAGND PC56 *0.1U/10V_4 PR59 *30.1K/F_4 PR163 *100K/F_4 IMONAGND [40] VGT_IMON +3V 2 4 IMONAGND GFX_VR_VCC [35] 5 1 PU9 *G1214AT11U 3 PR71 *10K/F_4 PC69 *0.1U/10V_4 1 PU3 *G1214AT11U GFX_VR_ICC [35] 5 2 *100K/F_4 PR184 + 3 - 4 + [5,40] VSS_AXG_SENSE [5,40] VCC_AXG_SENSE PR183 *49.9K/F_4 B IMONAGND PR72 *10K/F_4 - PR182 *49.9K/F_4 PR85 *30.1K/F_4 PC194 *0.1U/10V_4 B +3V PC54 *0.1U/10V_4 IMONAGND IMONAGND IMONAGND IMONAGND PR3 *0_4/S 1316AGND A Vender EON Winbond Socket Size IMONAGND A P/N 128KB 512KB AKE37ZN0Q01 (EN25F40-100HIP) 128KB AKE35FN0N00 (W25X10BVSNIG) 512KB AKE37FN0N01 (W25X40BVSSIG) RTQLGEV"<"NZ517*Jwtqp"Tkxgt+ Swcpvc"Eqorwvgt"Kpe0 DG008000031 PD7 Size Custom Document Number Date: Wednesday, October 13, 2010 5 4 3 2 Rev 1A IMON 1 Sheet 46 of 47 5 4 3 2 69 1 BACO_EN [42] +1.5V_VGA [16,19,20,21,22,23] +3VPCU [7,8,25,32,34,35,36,37,38,39,40,42,44,45] D D 9/29: MV modify 1.5VVGA_SENSEOE_1.5VVGA PR271 8.2K_4 PC284 *POWER_JP/S 5 2200P/50V_4 A5 VDES_1.5VVGA OE 2 R_SEL_1.5VVGA A2 A3 VDES C PR266 10_6 AVDD_1.5VGA D1 D2 D3 D4 D5 PL20 LX_1.5VVGA 0.22uH_PCMC063T-R22MN VSENSE+ A4 VSENSE_1.5VVGA PR262 PJP1 *POWER_JP/S 1 VX VX VX VX VX PU21 VT357 B3 10U/6.3V_8 10U/6.3V_8 0.1U/10V_4 0.01U/16V_4 PC275 PC279 PC277 PC272 +1.5V_VGA *0_2/S 1.5VVGA_SENSE- PR263 *0_2/S PC273 PC278 PC282 PC269 PC270 0.1U/10V_4 STAT VDD VDD VDD VDD +1.5V_VGA Volt +/- 5% Countinue current:8A Peak current: 12A OCP minimum: 16A 6800P/50V_4 +3V_1.5VGA 1 PX_MODE [19] 22U/6.3V_8 2 DGPU_PR_EN [35,42,43] 1 22U/6.3V_8 +3VPCU 2 4 10U/6.3V_8 E5 C5 C4 E4 R_SEL BIAS_1.5VVGA A1 BIAS PV change PJP2 BACO_EN U5 *TC7SH08FU AGND GND GND GND GND GND GND DGPU_PWROK R87 +1.5V_VGA_S1 TEMP AVDD [9,10,35,42,43] B4 1 STAT_1.5VVGA B5 *0.1U/10V_4 *0_4 IRIPL B1 C1 C2 C3 E1 E2 E3 34.8K/F_4 *0.47U/6.3V_4 54.9K/F_4 IRIPL_1.5VVGA B2 5.11K/F_4 PR270 2 PR264 *0_4/S 44.2K/F_4 PR273 *0_4/S C35 3 PR272 PR268 PR269 +3V PC287 C DGPU_PR_EN [35,42,43] PC281 0.22U/6.3V_4 B B A A RTQLGEV"<"NZ517*Jwtqp"Tkxgt+ Swcpvc"Eqorwvgt"Kpe0 PD7 Size Custom Document Number Date: Wednesday, October 13, 2010 5 4 3 2 Rev 1A +1.5V_VGA 1 Sheet 47 of 47 www.s-manuals.com
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File Type : PDF File Type Extension : pdf MIME Type : application/pdf PDF Version : 1.6 Linearized : No XMP Toolkit : Adobe XMP Core 4.0-c316 44.253921, Sun Oct 01 2006 17:14:39 Producer : GPL Ghostscript 9.05 Modify Date : 2013:03:21 22:40:14+02:00 Create Date : 2012:04:24 22:36:13+07:00 Creator Tool : www.freemypdf.com Metadata Date : 2013:03:21 22:40:14+02:00 Document ID : uuid:b1a946b9-ca80-11ed-0000-7cf7f2d75f73 Instance ID : uuid:392f7910-a0bb-4b2b-ba92-4f2cee42ba32 Format : application/pdf Title : Quanta LX3, LX5 - Schematics. www.s-manuals.com. Creator : Description : () Subject : Quanta LX3, LX5 - Schematics. www.s-manuals.com. Page Count : 48 Keywords : Quanta LX3, LX5 - Schematics. www.s-manuals.com.EXIF Metadata provided by EXIF.tools