Quanta OP8 Schematics. Www.s Manuals.com. R1a Schematics

User Manual: Notebook HP Compaq Presario CQ61 - Service manuals and Schematics, Disassembly / Assembly. Free.

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1

2

3

A

1
2
3
4
5
6

:
:
:
:
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5

6

7

8

OP8 SYSTEM DIAGRAM

PCB STACK UP
LAYER
LAYER
LAYER
LAYER
LAYER
LAYER

4

DDRII-SODIMM1

TOP
IN1
IN2
VCC
IN3
BOT

DDRII

667/800 MHz

Lion
Sabie

AMD
Tigris

PAGE 6,7
DDRII-SODIMM2

DDRII

01

CPU THERMAL
SENSOR

S1G2 Processor

667/800 MHz

PAGE 6,7

A

14.318MHz

PAGE 5

638P (uPGA)/35W
PAGE 3,4,5

CPU_CLK
NBGFX_CLK

CLOCK GEN

NBGPP_CLK

ICS9LPRS476AKLFT-->HP

SBLINK_CLK

SLG8SP628VTR-->HP

HT3

RTM880N-796 -->HP

PAGE 2

PCI-Express 16X

PCI-E
X1

NORTH BRIDGE

X1
Mini PCI-E
Card

LAN
Realtek
PCIE-LAN
RTL8103E

(Wireless LAN)

B

(10/100)

PAGE 30

HDMI
PAGE 25

ATI M92-S
for
Discrete
only

CRT
PAGE 24

RS880
A12

64 Bit,DDR2*4

LVDS
PAGE 23

21mm X 21mm, 528pin BGA
Side port

PAGE 33

PAGE 8

ALINK X4

PAGE 30

3

Webcam
X1 PAGE 23

Flash Media
RTS5159
PAGE 26

21mm X 21mm, 528pin BGA

PAGE 29

4.5W(Ext)
4.3W(Int)

SATA1 150MB

E-SATA

PAGE 29

VCCP +1.1V AND +1.2V(RT8204)

2

Blueflame
PAGE 29

SB710 A14

SATA4 150MB

SATA - CD-ROM

5

USB2.0 Ports
PAGE 29
X2

SOUTH BRIDGE

PAGE 29

PAGE 37

SBSRC_CLK

1,8,9

SATA0 150MB

SATA - HDD

PAGE 34

C

PCI-E WLAN Card x1
PAGE 33

USB2.0

SYSTEM CHARGER(ISL6251)

DDR II SMDDR_VTERM
1.8V/1.8VSUS(RT8207)

10

256mb RAM
for UMA only

RJ45

SYSTEM POWER ISL6237

B

PAGE 17,18,19
20,21,22

PAGE 8,9,10,11

PAGE 40

M92-S2

C

Azalia

PAGE 12,13.14.15.16

PAGE 35
IDT
92HD75B2

LPC
VGACORE(1.1V~1.2V)Oz8118

MDC CONN

PAGE 38
Keyboard
Touch Pad

CPU CORE ISL6265HRTZ-T

PAGE 32
PAGE 32

ENE KBC

PAGE 27

PAGE 28
AUDIO
Amplifier
TPA6017A2

KB3926 Dx

PAGE 36
SMBUS TABLE
SB--SCL0/SD0

PAGE 28

PAGE 32

Clock gen/Robson/TV tuner
/DDR2/DDR2 thermal/Accelerometer

+3V

D

D

Ang MIC

AUDIO CONN

epress card

(Phone/ MIC)

Wlan Card

+3VS5

FAN
EC --SCL/SD

Battery charge/discharge

+3VPCU

EC--SCL2/SD2

VGA thermal/system thermal

+3V

SPI

PAGE 28

PAGE 28

Audio
Conn
PAGE 27

PROJECT : OP8
Quanta Computer Inc.

PAGE 28 PAGE 35

Size
Custom
NB5/RD2

Document Number

Date: Friday, March 20, 2009
1

2

3

4

5

6

7

Rev
1A

Block Diagram
Sheet

1
8

of

42

5

4

3

600 ohm, 0.5A
+1.2V

CLOCKS name

L45
BLM18PG181SN1D(180,1.5A)_6

+3V

C489
0.1U/10V_4

C468
0.1U/10V_4

C494
0.1U/10V_4

C490
0.1U/10V_4

C428
0.1U/10V_4

C485
0.1U/10V_4

RS780

RP48 STUFF

RP48 STUFF

to NB for VGA reference clock

Clock pin function

EXT_GFX_CLKP
EXT_GFX_CLKN

RP47 STUFF

RP47 NC

to M92-S external reference clock -RX780 only

to NB for AC-LINK reference clock
RP43 STUFF

D

RP43 STUFF

+3V_CLKVDD

L46
BLM18PG181SN1D(180,1.5A)_6
C430
C511
22U/6.3V_8

02

RX780

NBGFX_CLKP
NBGFX_CLKN

SBLINK_CLKP
SBLINK_CLKN

+3V_CLKVDD

600 ohm, 0.5A

1

+1.2V_CLKVDDIO

C492
22U/6.3V_8

D

2

2.2U/6.3V_6

C434
0.1U/10V_4

C481
0.1U/10V_4

C491
0.1U/10V_4

C479
0.1U/10V_4

C446
0.1U/10V_4

C423
0.1U/10V_4

C412
0.1U/10V_4

CLK_VGA_27M_SS
CLK_VGA_27M_NSS

C424
0.1U/10V_4

R213,R215
STUFF

R213,R215
NC

To M92-S 27Mhz - RX780 only

Need check the net name for the short pad

+3V_CLKVDD

Place very
close to
C/G

+3V_CLKVDD
L35
BLM18PG181SN1D(180,1.5A)_6

+3V_CLK_VDDA

4
16
26
35
40
48
55
56
63

4
2

3 *0_4P2R_4 CPUCLKP
CPUCLKN
1

NBGFX_CLKP
NBGFX_CLKN
EXT_GFX_CLKP_L
EXT_GFX_CLKN_L

RP48

4
2
4
2

3 *0_4P2R_4 NBGFX_CLKP
NBGFX_CLKN
1
3 0_4P2R_4 EXT_GFX_CLKP
EXT_GFX_CLKN
1

37
36
32
31

SBLINK_CLKP
SBLINK_CLKN
SBSRC_CLKP
SBSRC_CLKN

RP43

4
2
4
2

3 *0_4P2R_4 SBLINK_CLKP
SBLINK_CLKN
1
3 *0_4P2R_4 SBSRC_CLKP
SBSRC_CLKN
1

C

0.1U/10V_4
+1.2V_CLKVDDIO

33P/50V_4

C405

33P/50V_4

CG_XIN

2

C406

1

Y1
14.318MHZ
CG_XOUT

CG_XIN
CG_XOUT

can remove MOSFET level shift
SB/clock gen / DDR2 is 3.3V/S0
power level

PCLK_SMB
PDAT_SMB

6,7,13,33 PCLK_SMB
6,7,13,33 PDAT_SMB

SBLINK_CLKP 10
SBLINK_CLKN 10
SBSRC_CLKP 12
SBSRC_CLKN 12

SRC0T
SRC0C
SRC1T
SRC1C
SRC2T
SRC2C
SRC3T
SRC3C
SRC4T
SRC4C
SRC7T/27M_SS
SRC7C/27M
SRC6T/SATAT
SRC6C/SATAC

22
21
20
19
15
14
13
12
9
8
6
5
42
41

PCIE_MINI1_CLKP
PCIE_MINI1_CLKN

RP45

4
2

3 *0_4P2R_4 PCIE_MINI1_CLKP
PCIE_MINI1_CLKN
1

PCIE_MINI1_CLKP
PCIE_MINI1_CLKN

PCIE_LAN_CLKP
PCIE_LAN_CLKN

RP44

4
2

3 *0_4P2R_4 PCIE_LAN_CLKP
PCIE_LAN_CLKN
1

PCIE_LAN_CLKP
PCIE_LAN_CLKN

CLK_VGA_27M_SS
CLK_VGA_27M_NSS

R217
R213
R215

HTT0T/66M
HTT0C/66M

54
53

NBHTREFCLK0P
NBHTREFCLK0N

48MHz_0

64

CLK48MUSB

REF0/SEL_HTT66
REF1/SEL_SATA
REF2/SEL_27

59
58
57

*8.2K_4

R190

8.2K_4

GND48
GNDDOT
GNDSRC
GNDSRC
GNDATIG
GNDSB
GNDSATA
GNDCPU
GNDHTT
GNDREF

61
62

X1
X2

QFN64

50
49

ATIG0T
ATIG0C
ATIG1T
ATIG1C

30
29
28
27

SB_SRC0T
SB_SRC0C
SB_SRC1T
SB_SRC1C

SMBCLK
SMBDAT
PD#

23
38
39
44
45

*CLKREQ0#
*CLKREQ4#
*CLKREQ3#
*CLKREQ2#
*CLKREQ1#

RP47

CPUCLKP 3
CPUCLKN 3

Clock for Dis only
RP46

33_4
75/F_4
100/F_4

OSC_SPREAD

to NB for external Graphics
reference clock
to M92-S -RX780 only

NBGFX_CLKP 10
NBGFX_CLKN 10
EXT_GFX_CLKP 17
EXT_GFX_CLKN 17

to NB for AC-LINK reference clock
C

to SB
33
33

to WLAN

30
30

OSC_SPREAD 18
EVGA-XTALI 18

SSIN - for M82 - 3.3V level input
X_TALIN --for M92 -1.8V level input

27Mhz for Dis only

SEL_HT66
SEL_SATA
SEL_27

R188
R189

*0_4/S NBHT_REFCLKP
*0_4/S NBHT_REFCLKN

R174
R191

22_4
22_4

NBHT_REFCLKP
NBHT_REFCLKN

CLK_48M_USB
CLK_48M_CR

10
10

CLK_48M_USB 13
CLK_48M_CR 26
R171

R186

33_4

EXT_SB_OSC 12

Ra

R169

T25

158/F_4
90.9/F_4

EXT_NB_OSC 10

B

Rb
RX880

TGND

R207

1
7
10
18
24
33
43
46
52
60

51
CLKREQ0#
CLKREQ4#
CLKREQ3#
CLKREQ2#
CLKREQ1#

+3V

VDDSRC_IO
VDDSRC_IO
VDDATIG_IO
VDDSB_IO
VDDCPU_IO

2
3

CLK_PD#

B

11
17
25
34
47

CPUK8_0T
CPUK8_0C

CPUCLKP
CPUCLKN

*261_4

RP42

VDDDOT
VDDSRC
VDDATIG
VDDSB
VDD_SATA
VDDCPU
VDDHTT
VDDREF
VDD48

C411
C396
2.2U/6.3V_6

R178

Place within 0.5"
of CLKGEN

U11

CLKREQ1#
CLK_PD#

RS880

1.8V

65

RTM880N-796_QFN64

SI change 1.2V to 3.3V from AMD request

1.1V

Ra

82.5R

158R

Rb

130R

90.9R

For EMI
+3V
C399

*10P/50V_4

EXT_NB_OSC

C404

*10P/50V_4

CLK_48M_USB

C440

*10P/50V_4

EVGA-XTALI

C456

*10P/50V_4

OSC_SPREAD

R247
R212
R222
R231

*8.2K_4
*8.2K_4
*8.2K_4
*8.2K_4

CLKREQ0#
CLKREQ2#
CLKREQ3#
CLKREQ4#

RES CHIP 130 1/16W +-1%(0402)L-F -->CS11302FB15
RES CHIP 158 1/16W +-1%(0402) -->CS11582FB00
RES CHIP 90.9 1/16W +-1%(0402) -->CS09092FB15
RES CHIP 82.5 1/16W +-1%(0402) -->CS08252FB11

+3V_CLKVDD

SLG
RTL

if use clock
request pin , need
to pull Hi for
default sttting

SLG8SP628VTR--AL8SP628000
RTM880N-796-- AL000880001
* default

R173
*8.2K_4

R176
8.2K_4

66 MHz 3.3V single ended HTT clock
1

SEL_27
SEL_SATA
SEL_HT66

SEL_HTT66
0*

A

100 MHz differential HTT clock
100 MHz non-spreading differential SRC clock

SEL_SATA

SEL_27

1
0*

100 MHz spreading differential SRC clock

1*

27MHz non-spreading singled clock

0

100 MHz spreading differential SRC clock

R192
8.2K_4

Clock chip has internal serial
terminations
for differencial pairs, external resistors
are
reserved for debug purpose.

not need to
stuff ,
R169 have
pull LOW

R185
*8.2K_4

PROJECT : OP8
Quanta Computer Inc.

RS780M/RX780M
Size
Custom
NB5/RD2

Document Number

4

3

2

Rev
1A

Clock Generator

Date: Friday, March 20, 2009
5

A

Sheet
1

2

of

42

5

4

3

BLM21PG221SN1D(220,100M,2A)_8
+CPUVDDA

+2.5V

2

L32

CPU CLK

VLDT use 1.5A Max current
+1.2V

+1.2V_VLDT
R384

*0_6/S

R383

*0_6/S

C340
LS0805-100M-N
4.7U/6.3V_6

C294
0.22U/6.3V_4

C292
3300P/50V_4

2
2

U24A

C645
C662
C676
C671

HT_NB_CPU_CAD_H[15..0]

8 HT_NB_CPU_CAD_H[15..0]

HT_NB_CPU_CAD_L[15..0]

8 HT_NB_CPU_CAD_L[15..0]

HT_NB_CPU_CLK_H[1..0]

8 HT_NB_CPU_CLK_H[1..0]

HT_NB_CPU_CLK_L[1..0]

8 HT_NB_CPU_CLK_L[1..0]

HT_NB_CPU_CTL_H[1..0]

8 HT_NB_CPU_CTL_H[1..0]

HT_NB_CPU_CTL_L[1..0]

8 HT_NB_CPU_CTL_L[1..0]

HT_CPU_NB_CAD_H[15..0]

8 HT_CPU_NB_CAD_H[15..0]

HT_CPU_NB_CAD_L[15..0]

8 HT_CPU_NB_CAD_L[15..0]

HT_CPU_NB_CLK_H[1..0]

8 HT_CPU_NB_CLK_H[1..0]

HT_CPU_NB_CLK_L[1..0]

8 HT_CPU_NB_CLK_L[1..0]

HT_CPU_NB_CTL_H[1..0]

8 HT_CPU_NB_CTL_H[1..0]

HT_CPU_NB_CTL_L[1..0]

8 HT_CPU_NB_CTL_L[1..0]

+1.2V_VLDT
+1.2V_VLDT
+1.2V_VLDT
+1.2V_VLDT

10U/6.3V_8
10U/6.3V_8
0.22U/6.3V_4
180P/50V_4

D1
D2
D3
D4

HT_NB_CPU_CAD_H0
HT_NB_CPU_CAD_L0
HT_NB_CPU_CAD_H1
HT_NB_CPU_CAD_L1
HT_NB_CPU_CAD_H2
HT_NB_CPU_CAD_L2
HT_NB_CPU_CAD_H3
HT_NB_CPU_CAD_L3
HT_NB_CPU_CAD_H4
HT_NB_CPU_CAD_L4
HT_NB_CPU_CAD_H5
HT_NB_CPU_CAD_L5
HT_NB_CPU_CAD_H6
HT_NB_CPU_CAD_L6
HT_NB_CPU_CAD_H7
HT_NB_CPU_CAD_L7
HT_NB_CPU_CAD_H8
HT_NB_CPU_CAD_L8
HT_NB_CPU_CAD_H9
HT_NB_CPU_CAD_L9
HT_NB_CPU_CAD_H10
HT_NB_CPU_CAD_L10
HT_NB_CPU_CAD_H11
HT_NB_CPU_CAD_L11
HT_NB_CPU_CAD_H12
HT_NB_CPU_CAD_L12
HT_NB_CPU_CAD_H13
HT_NB_CPU_CAD_L13
HT_NB_CPU_CAD_H14
HT_NB_CPU_CAD_L14
HT_NB_CPU_CAD_H15
HT_NB_CPU_CAD_L15

E3
E2
E1
F1
G3
G2
G1
H1
J1
K1
L3
L2
L1
M1
N3
N2
E5
F5
F3
F4
G5
H5
H3
H4
K3
K4
L5
M5
M3
M4
N5
P5

HT_NB_CPU_CLK_H0
HT_NB_CPU_CLK_L0
HT_NB_CPU_CLK_H1
HT_NB_CPU_CLK_L1

J3
J2
J5
K5

HT_NB_CPU_CTL_H0
HT_NB_CPU_CTL_L0
HT_NB_CPU_CTL_H1
HT_NB_CPU_CTL_L1

N1
P1
P3
P4

FOX PZ63826-284R-41F
DG0^8000004 IC SOCKET SMD 638P S1(P1.27,H3.2)
MLX 47296-4131
DG0^8000003 IC SOCKET SMD 638P S1(P1.27,H3.2)
TYC 4-1903401-2
DG0^8000005 IC SOCKET SMD 638P S1(P1.27,H3.2)

CNTR_VREF
C776

VLDT_A0
VLDT_A1
VLDT_A2
VLDT_A3

HT LINK

L0_CADIN_H0
L0_CADIN_L0
L0_CADIN_H1
L0_CADIN_L1
L0_CADIN_H2
L0_CADIN_L2
L0_CADIN_H3
L0_CADIN_L3
L0_CADIN_H4
L0_CADIN_L4
L0_CADIN_H5
L0_CADIN_L5
L0_CADIN_H6
L0_CADIN_L6
L0_CADIN_H7
L0_CADIN_L7
L0_CADIN_H8
L0_CADIN_L8
L0_CADIN_H9
L0_CADIN_L9
L0_CADIN_H10
L0_CADIN_L10
L0_CADIN_H11
L0_CADIN_L11
L0_CADIN_H12
L0_CADIN_L12
L0_CADIN_H13
L0_CADIN_L13
L0_CADIN_H14
L0_CADIN_L14
L0_CADIN_H15
L0_CADIN_L15

VLDT_B0
VLDT_B1
VLDT_B2
VLDT_B3

L0_CADOUT_H0
L0_CADOUT_L0
L0_CADOUT_H1
L0_CADOUT_L1
L0_CADOUT_H2
L0_CADOUT_L2
L0_CADOUT_H3
L0_CADOUT_L3
L0_CADOUT_H4
L0_CADOUT_L4
L0_CADOUT_H5
L0_CADOUT_L5
L0_CADOUT_H6
L0_CADOUT_L6
L0_CADOUT_H7
L0_CADOUT_L7
L0_CADOUT_H8
L0_CADOUT_L8
L0_CADOUT_H9
L0_CADOUT_L9
L0_CADOUT_H10
L0_CADOUT_L10
L0_CADOUT_H11
L0_CADOUT_L11
L0_CADOUT_H12
L0_CADOUT_L12
L0_CADOUT_H13
L0_CADOUT_L13
L0_CADOUT_H14
L0_CADOUT_L14
L0_CADOUT_H15
L0_CADOUT_L15

L0_CLKIN_H0
L0_CLKIN_L0
L0_CLKIN_H1
L0_CLKIN_L1

L0_CLKOUT_H0
L0_CLKOUT_L0
L0_CLKOUT_H1
L0_CLKOUT_L1

L0_CTLIN_H0
L0_CTLIN_L0
L0_CTLIN_H1
L0_CTLIN_L1

L0_CTLOUT_H0
L0_CTLOUT_L0
L0_CTLOUT_H1
L0_CTLOUT_L1

AE2
AE3
AE4
AE5

+1.2V_VLDT 10U/6.3V_8
+1.2V_VLDT 0.22U/6.3V_4
+1.2V_VLDT 180P/50V_4
+1.2V_VLDT

AD1
AC1
AC2
AC3
AB1
AA1
AA2
AA3
W2
W3
V1
U1
U2
U3
T1
R1
AD4
AD3
AD5
AC5
AB4
AB3
AB5
AA5
Y5
W5
V4
V3
V5
U5
T4
T3

HT_CPU_NB_CAD_H0
HT_CPU_NB_CAD_L0
HT_CPU_NB_CAD_H1
HT_CPU_NB_CAD_L1
HT_CPU_NB_CAD_H2
HT_CPU_NB_CAD_L2
HT_CPU_NB_CAD_H3
HT_CPU_NB_CAD_L3
HT_CPU_NB_CAD_H4
HT_CPU_NB_CAD_L4
HT_CPU_NB_CAD_H5
HT_CPU_NB_CAD_L5
HT_CPU_NB_CAD_H6
HT_CPU_NB_CAD_L6
HT_CPU_NB_CAD_H7
HT_CPU_NB_CAD_L7
HT_CPU_NB_CAD_H8
HT_CPU_NB_CAD_L8
HT_CPU_NB_CAD_H9
HT_CPU_NB_CAD_L9
HT_CPU_NB_CAD_H10
HT_CPU_NB_CAD_L10
HT_CPU_NB_CAD_H11
HT_CPU_NB_CAD_L11
HT_CPU_NB_CAD_H12
HT_CPU_NB_CAD_L12
HT_CPU_NB_CAD_H13
HT_CPU_NB_CAD_L13
HT_CPU_NB_CAD_H14
HT_CPU_NB_CAD_L14
HT_CPU_NB_CAD_H15
HT_CPU_NB_CAD_L15

Y1
W1
Y4
Y3

HT_CPU_NB_CLK_H0
HT_CPU_NB_CLK_L0
HT_CPU_NB_CLK_H1
HT_CPU_NB_CLK_L1

R2
R3
T5
R5

HT_CPU_NB_CTL_H0
HT_CPU_NB_CTL_L0
HT_CPU_NB_CTL_H1
HT_CPU_NB_CTL_L1

R146

20K/F_4

CPUCLKP
CPUCLKN

5

+1.8VSUS

A9
A8

CLKIN_H
CLKIN_L

CPU_SIC
CPU_SID
CPU_ALERT

R74
R123

+1.2V_VLDT

R36

300/F_4

CPUTEST23

+1.8VSUS

R133
R87

R73

300/F_4

R376

300/F_4

+1.8VSUS
R372

*300_4
R440

W7
W8

CPU_THERMDC
CPU_THERMDA

VDDIO_FB_H
VDDIO_FB_L

F6
E6

VDD0_FB_H
VDD0_FB_L

VDDIO_FB_H
VDDIO_FB_L

W9
Y9

Y6
AB6

VDD1_FB_H
VDD1_FB_L

VDDNB_FB_H
VDDNB_FB_L

H6
G6

H10
G9

DBRDY
TMS
TCK
TRST_L
TDI

TEST21
TEST20
TEST24
TEST22
TEST12
TEST27
TEST9
TEST6

A3
A5
B3
B5
C1

RSVD1
RSVD2
RSVD3
RSVD4
RSVD5

CPU_DBREQ# R143
CPU_TDO

J7
H8

CPUTEST28H
CPUTEST28L

TEST17
TEST16
TEST15
TEST14

D7
E7
F7
C7

CPUTEST17
CPUTEST16
CPUTEST15
CPUTEST14

TEST7
TEST10

C3
K8

TEST28_H
TEST28_L

TEST25_H
TEST25_L

CPU_VDDNB_RUN_FB_H
CPU_VDDNB_RUN_FB_L

AE9

TDO

TEST18
TEST19

VDDIO_FB_H 37
VDDIO_FB_L 37

E10

DBREQ_L

TEST23

C2
AA6

TEST8
TEST29_H
TEST29_L
RSVD10
RSVD9
RSVD8
RSVD7
RSVD6

R525

36
36

300/F_4
+1.8V

T13
T14
C

T19
T18
T16
T21

*300/F_4

C4

+1.2V_VLDT

SI Add from AMD request
CPUTEST29H
CPUTEST29L

C9
C8

T20
T22

H18
H19
AA7
D5
C5

R137
R456
R457

CPU_SVC_R
CPU_SVD_R
CPU_PWRGD

2

R144
1K/F_4
R129
*0_4/S

1

CPU_LDT_REQ# 10

CPU_LDT_RST#

R444
R443
R138
R453
R452
R139

CPU_LDT_RST_HTPA#
3
Q20
BSS138_NL/SOT23

1

VFIX MODE

SI Change from AMD request
*2.2K_4
1K/F_4
1K/F_4

CPU_SVC
CPU_SVD
CPU_PWRGD_SVID_REG

*0_4/S
*0_4/S
*0_4/S

CPU_SVC 36
CPU_SVD 36
CPU_PWRGD_SVID_REG

36

*220_4
*220_4
*220_4

VID Override Circuit

SVC

SVD

0
0
1
1

0
1
0
1

B

Voltage Output

1.4V
1.2V
1.0V
0.8V

G1
*SHORT_ PAD1

10K/F_4
2

for debug only
R35

300_4
3

Q10
MMBT3904
CPU_MEMHOT#
1

CPUTEST20
CPUTEST22
CPUTEST12
CPUTEST15
CPUTEST14
CPUTEST19
CPUTEST18

HDT Connector

CPU_MEMHOT# 7,13

+1.8VSUS

R370

R29

+1.8VSUS

R371

2

300_4

CPU_PROCHOT_L#

1

300_4

CPU_THERMTRIP_L#

1

Q9
MMBT3904
3

CPU_DBREQ#
CPU_DBRDY
CPU_TCK
CPU_TMS
CPU_TDI
CPU_TRST#
CPU_TDO

CPU_THERMTRIP# 13

Q39

3
MMBT3904

R28
R30
R70
R86
R116
R83
R85

300/F_4
300/F_4
*300/F_4
*300/F_4
*300/F_4
*300/F_4
*300/F_4

10K/F_4

10K/F_4
5 CPU_THERMTRIP_L#

R369

+1.8VSUS

2

A

+1.8VSUS

THERMDC
THERMDA

HT_REF0
HT_REF1

THERMTRIP_L
PROCHOT_L
MEMHOT_L

Serial VID

34.8K/F_4

*0_4/S

CPU_MEMHOT_L#

+1.8VSUS

CPU_THERMTRIP_L#
CPU_PROCHOT_L#
CPU_MEMHOT_L#

R6
P6

510/F_4CPUTEST25H
E9
510/F_4CPUTEST25L
E8
place them to CPU within 1.5"
CPUTEST21
AB8
CPUTEST20
AF7
T64
CPUTEST24
AE7
CPUTEST22
AE8
CPUTEST12
AC8
T1
CPUTEST27
AF8
*0_4/S

AF6
AC7
AA8

SIC
SID
ALERT_L

AD7

CPUTEST18
CPUTEST19

T12
T17

CPU_SVC_R
CPU_SVD_R

AF4
AF5
AE6

G10
AA9
AC9
AD9
AF9

D

A6
A4

SVC
SVD

RESET_L
PWROK
LDTSTOP_L
LDTREQ_L

36 CPU_VDD0_RUN_FB_H
36 CPU_VDD0_RUN_FB_L

CPU_DBRDY
CPU_TMS
CPU_TCK
CPU_TRST#
CPU_TDI

M11
W18

B7
A7
F10
C6

44.2/F_4
CPU_HTREF0
CPU_HTREF1
44.2/F_4
place them to CPU within 1.5"

36 CPU_VDD1_RUN_FB_H
36 CPU_VDD1_RUN_FB_L

KEY1
KEY2

2

R26

CPUCLKIN
CPUCLKIN#

CPU_SIC
CPU_SID
CPU_ALERT

5

+3V

2
+1.8VSUS

VDDA1
VDDA2

CPU_LDT_RST#
CPU_PWRGD
CPU_LDT_STOP#
CPU_LDT_REQ#_CPU

+1.8V

U24D
F8
F9

3900P/25V_4
3900P/25V_4

R128
R136
R132
R458

SOCKET_638_PIN

CNTR_VREF

R463

C326
C327

SideBand Temp sense I2C 5

CNTR_VREF 5

*BSS138_NL/SOT23
3

CPUCLKIN#

169/F_4

10,12 CPU_LDT_RST#
12 CPU_PWRGD
10,12 CPU_LDT_STOP#

+1.8V

Q46
CPU_LDT_REQ#_CPU 1

R125

250mA

300_4
300_4
300_4
300/F_4

W/S= 15 mil/20mil
+CPUVDDA
+CPUVDDA

SOCKET_638_PIN

0.1U/10V_4

R152

CPUCLKIN

C766
C745
C757

B

+3V

+CPUVDDA

SI Change from AMD request

03

H_THRMDC 5
H_THRMDA 5

CPU_LDT_RST#
CPU_PWRGD
CPU_LDT_STOP#
CPU_LDT_REQ#

CPUCLKP
CPUCLKN

CPUCLKP
CPUCLKN

Keep trace from resisor to CPU within 0.6"
keep trace from caps to CPU within 1.2"

D

C

C313
4.7U/6.3V_6

+1.2V_VLDT

SI Change from AMD request

1

CPU_THERMDC
CPU_THERMDA

W/S= 15 mil/20mil

CPU_PROCHOT# 12

C28

*0.1U/10V_4

1
3
5
7
9
11
13
15
17
19
21
23
KEY

2
4
6
8
10
12
14
16
18
20
22
24
25

A

PROJECT : OP8
Quanta Computer Inc.

CPU_LDT_RST_HTPA#
Size
Custom

CN5 *HDT CONN

NB5/RD2

Document Number

5

4

3

2

Rev
1A

S1G2 HT,CTL I/F 1/3

Date: Friday, March 20, 2009

Sheet
1

3

of

42

A

B

+0.9VSMVTT

PLACE THEM CLOSE TO
CPU WITHIN 1"

+1.8VSUS
T15

39.2/F_4 M_ZP
39.2/F_4 M_ZN

AF10
AE10

MEM_MA_RESET# H16

4

6,7 MEM_MA0_ODT0
6,7 MEM_MA0_ODT1

6,7 MEM_MA0_CS#0
6,7 MEM_MA0_CS#1

6,7 MEM_MA_CKE0
6,7 MEM_MA_CKE1

VTT1
VTT2
VTT3
VTT4

MEM:CMD/CTRL/CLK VTT5
VTT6
VTT7
VTT8
VTT9

MEMZP
MEMZN

VTT_SENSE

RSVD_M1

T19
V22
U21
V19

MA0_ODT0
MA0_ODT1
MA1_ODT0
MA1_ODT1

T20
U19
U20
V20

MA0_CS_L0
MA0_CS_L1
MA1_CS_L0
MA1_CS_L1

J22
J20

MA_CKE0
MA_CKE1

Y10

CPU_VTT_SENSE

W 17 MEMVREF_CPU

RSVD_M2

B18 MEM_MB_RESET#

R62
MEM_MB0_ODT0 6,7
2K/F_4
MEM_MB0_ODT1 6,7

MB0_CS_L0
MB0_CS_L1
MB1_CS_L0

V26
W 25
U22

MEM_MB0_CS#0 6,7
MEM_MB0_CS#1 6,7

MB_CKE0
MB_CKE1

J25
H26

MEM_MB_CKE0 6,7
MEM_MB_CKE1 6,7

MEM_MB_CLK1_P
MEM_MB_CLK1_N
MEM_MB_CLK7_P
MEM_MB_CLK7_N

MB_CLK_H5
MB_CLK_L5
MB_CLK_H1
MB_CLK_L1
MB_CLK_H7
MB_CLK_L7
MB_CLK_H4
MB_CLK_L4

N21
M20
N22
M19
M22
L20
M24
L21
L19
K22
R21
L22
K20
V24
K24
K19

MA_ADD0
MA_ADD1
MA_ADD2
MA_ADD3
MA_ADD4
MA_ADD5
MA_ADD6
MA_ADD7
MA_ADD8
MA_ADD9
MA_ADD10
MA_ADD11
MA_ADD12
MA_ADD13
MA_ADD14
MA_ADD15

MB_ADD0
MB_ADD1
MB_ADD2
MB_ADD3
MB_ADD4
MB_ADD5
MB_ADD6
MB_ADD7
MB_ADD8
MB_ADD9
MB_ADD10
MB_ADD11
MB_ADD12
MB_ADD13
MB_ADD14
MB_ADD15

P24
N24
P26
N23
N26
L23
N25
L24
M26
K26
T26
L26
L25
W 24
J23
J24

6,7 MEM_MA_BANK0
6,7 MEM_MA_BANK1
6,7 MEM_MA_BANK2

R20
R23
J21

MA_BANK0
MA_BANK1
MA_BANK2

MB_BANK0
MB_BANK1
MB_BANK2

R24
U26
J26

MEM_MB_BANK0 6,7
MEM_MB_BANK1 6,7
MEM_MB_BANK2 6,7

6,7 MEM_MA_RAS#
6,7 MEM_MA_CAS#
6,7 MEM_MA_WE#

R19
T22
T24

MA_RAS_L
MA_CAS_L
MA_W E_L

MB_RAS_L
MB_CAS_L
MB_W E_L

U25
U24
U23

MEM_MB_RAS# 6,7
MEM_MB_CAS# 6,7
MEM_MB_WE# 6,7

MEM_MA_ADD0
MEM_MA_ADD1
MEM_MA_ADD2
MEM_MA_ADD3
MEM_MA_ADD4
MEM_MA_ADD5
MEM_MA_ADD6
MEM_MA_ADD7
MEM_MA_ADD8
MEM_MA_ADD9
MEM_MA_ADD10
MEM_MA_ADD11
MEM_MA_ADD12
MEM_MA_ADD13
MEM_MA_ADD14
MEM_MA_ADD15

3

Reserved

T23

W 26
W 23
Y26

MA_CLK_H5
MA_CLK_L5
MA_CLK_H1
MA_CLK_L1
MA_CLK_H7
MA_CLK_L7
MA_CLK_H4
MA_CLK_L4

6,7 MEM_MA_ADD[0..15]

R68
*0_4

2K/F_4
CPU_VTT_SENSE 37

MB0_ODT0
MB0_ODT1
MB1_ODT0

C154
0.1U/10V_4

C133
1000P/50V_4

6
6
6
6

MEM_MB_ADD[0..15]

MEM_MB_ADD0
MEM_MB_ADD1
MEM_MB_ADD2
MEM_MB_ADD3
MEM_MB_ADD4
MEM_MB_ADD5
MEM_MB_ADD6
MEM_MB_ADD7
MEM_MB_ADD8
MEM_MB_ADD9
MEM_MB_ADD10
MEM_MB_ADD11
MEM_MB_ADD12
MEM_MB_ADD13
MEM_MB_ADD14
MEM_MB_ADD15

6,7

SOCKET_638_PIN

2

6 MEM_MB_DM[0..7]

Place close to socket

+0.9VSMVTT

C23
4.7U/6.3V_6

C198
4.7U/6.3V_6

C22
4.7U/6.3V_6

C119
4.7U/6.3V_6

C167
0.22U/6.3V_4

C201
0.22U/6.3V_4

C115
0.22U/6.3V_4

C136
0.22U/6.3V_4

+0.9VSMVTT

C204
C155
1000P/50V_4 1000P/50V_4

C117
1000P/50V_4

C142
1000P/50V_4

C140
180P/50V_4

C147
180P/50V_4

04

U24C

R67

MEMVREF

E

Processor Memory Interface

+0.9VSMVREF 6,37

750 mA

P22
R22
A17
A18
AF18
AF17
R26
R25

MEM_MA_CLK1_P
MEM_MA_CLK1_N
MEM_MA_CLK7_P
MEM_MA_CLK7_N

6 MEM_MB_DATA[0..63]

+1.8VSUS

W 10
AC10
AB10
AA10
A10

N19
N20
E16
F16
Y16
AA16
P19
P20

6
6
6
6

D

+0.9VSMVTT

U24B

D10
C10
B10
AD10
R374
R373

C

C208
180P/50V_4

C116
180P/50V_4

Close to CPU within 1500 mils

6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6

MEM_MB_DQS0_P
MEM_MB_DQS0_N
MEM_MB_DQS1_P
MEM_MB_DQS1_N
MEM_MB_DQS2_P
MEM_MB_DQS2_N
MEM_MB_DQS3_P
MEM_MB_DQS3_N
MEM_MB_DQS4_P
MEM_MB_DQS4_N
MEM_MB_DQS5_P
MEM_MB_DQS5_N
MEM_MB_DQS6_P
MEM_MB_DQS6_N
MEM_MB_DQS7_P
MEM_MB_DQS7_N

MEM:DATA
MEM_MB_DATA0
MEM_MB_DATA1
MEM_MB_DATA2
MEM_MB_DATA3
MEM_MB_DATA4
MEM_MB_DATA5
MEM_MB_DATA6
MEM_MB_DATA7
MEM_MB_DATA8
MEM_MB_DATA9
MEM_MB_DATA10
MEM_MB_DATA11
MEM_MB_DATA12
MEM_MB_DATA13
MEM_MB_DATA14
MEM_MB_DATA15
MEM_MB_DATA16
MEM_MB_DATA17
MEM_MB_DATA18
MEM_MB_DATA19
MEM_MB_DATA20
MEM_MB_DATA21
MEM_MB_DATA22
MEM_MB_DATA23
MEM_MB_DATA24
MEM_MB_DATA25
MEM_MB_DATA26
MEM_MB_DATA27
MEM_MB_DATA28
MEM_MB_DATA29
MEM_MB_DATA30
MEM_MB_DATA31
MEM_MB_DATA32
MEM_MB_DATA33
MEM_MB_DATA34
MEM_MB_DATA35
MEM_MB_DATA36
MEM_MB_DATA37
MEM_MB_DATA38
MEM_MB_DATA39
MEM_MB_DATA40
MEM_MB_DATA41
MEM_MB_DATA42
MEM_MB_DATA43
MEM_MB_DATA44
MEM_MB_DATA45
MEM_MB_DATA46
MEM_MB_DATA47
MEM_MB_DATA48
MEM_MB_DATA49
MEM_MB_DATA50
MEM_MB_DATA51
MEM_MB_DATA52
MEM_MB_DATA53
MEM_MB_DATA54
MEM_MB_DATA55
MEM_MB_DATA56
MEM_MB_DATA57
MEM_MB_DATA58
MEM_MB_DATA59
MEM_MB_DATA60
MEM_MB_DATA61
MEM_MB_DATA62
MEM_MB_DATA63

C11
A11
A14
B14
G11
E11
D12
A13
A15
A16
A19
A20
C14
D14
C18
D18
D20
A21
D24
C25
B20
C20
B24
C24
E23
E24
G25
G26
C26
D26
G23
G24
AA24
AA23
AD24
AE24
AA26
AA25
AD26
AE25
AC22
AD22
AE20
AF20
AF24
AF23
AC20
AD20
AD18
AE18
AC14
AD14
AF19
AC18
AF16
AF15
AF13
AC12
AB11
Y11
AE14
AF14
AF11
AD11

MB_DATA0
MB_DATA1
MB_DATA2
MB_DATA3
MB_DATA4
MB_DATA5
MB_DATA6
MB_DATA7
MB_DATA8
MB_DATA9
MB_DATA10
MB_DATA11
MB_DATA12
MB_DATA13
MB_DATA14
MB_DATA15
MB_DATA16
MB_DATA17
MB_DATA18
MB_DATA19
MB_DATA20
MB_DATA21
MB_DATA22
MB_DATA23
MB_DATA24
MB_DATA25
MB_DATA26
MB_DATA27
MB_DATA28
MB_DATA29
MB_DATA30
MB_DATA31
MB_DATA32
MB_DATA33
MB_DATA34
MB_DATA35
MB_DATA36
MB_DATA37
MB_DATA38
MB_DATA39
MB_DATA40
MB_DATA41
MB_DATA42
MB_DATA43
MB_DATA44
MB_DATA45
MB_DATA46
MB_DATA47
MB_DATA48
MB_DATA49
MB_DATA50
MB_DATA51
MB_DATA52
MB_DATA53
MB_DATA54
MB_DATA55
MB_DATA56
MB_DATA57
MB_DATA58
MB_DATA59
MB_DATA60
MB_DATA61
MB_DATA62
MB_DATA63

MEM_MB_DM0
MEM_MB_DM1
MEM_MB_DM2
MEM_MB_DM3
MEM_MB_DM4
MEM_MB_DM5
MEM_MB_DM6
MEM_MB_DM7

A12
B16
A22
E25
AB26
AE22
AC16
AD12

MB_DM0
MB_DM1
MB_DM2
MB_DM3
MB_DM4
MB_DM5
MB_DM6
MB_DM7

C12
B12
D16
C16
A24
A23
F26
E26
AC25
AC26
AF21
AF22
AE16
AD16
AF12
AE12

MB_DQS_H0
MB_DQS_L0
MB_DQS_H1
MB_DQS_L1
MB_DQS_H2
MB_DQS_L2
MB_DQS_H3
MB_DQS_L3
MB_DQS_H4
MB_DQS_L4
MB_DQS_H5
MB_DQS_L5
MB_DQS_H6
MB_DQS_L6
MB_DQS_H7
MB_DQS_L7

MA_DATA0
MA_DATA1
MA_DATA2
MA_DATA3
MA_DATA4
MA_DATA5
MA_DATA6
MA_DATA7
MA_DATA8
MA_DATA9
MA_DATA10
MA_DATA11
MA_DATA12
MA_DATA13
MA_DATA14
MA_DATA15
MA_DATA16
MA_DATA17
MA_DATA18
MA_DATA19
MA_DATA20
MA_DATA21
MA_DATA22
MA_DATA23
MA_DATA24
MA_DATA25
MA_DATA26
MA_DATA27
MA_DATA28
MA_DATA29
MA_DATA30
MA_DATA31
MA_DATA32
MA_DATA33
MA_DATA34
MA_DATA35
MA_DATA36
MA_DATA37
MA_DATA38
MA_DATA39
MA_DATA40
MA_DATA41
MA_DATA42
MA_DATA43
MA_DATA44
MA_DATA45
MA_DATA46
MA_DATA47
MA_DATA48
MA_DATA49
MA_DATA50
MA_DATA51
MA_DATA52
MA_DATA53
MA_DATA54
MA_DATA55
MA_DATA56
MA_DATA57
MA_DATA58
MA_DATA59
MA_DATA60
MA_DATA61
MA_DATA62
MA_DATA63

G12
F12
H14
G14
H11
H12
C13
E13
H15
E15
E17
H17
E14
F14
C17
G17
G18
C19
D22
E20
E18
F18
B22
C23
F20
F22
H24
J19
E21
E22
H20
H22
Y24
AB24
AB22
AA21
W 22
W 21
Y22
AA22
Y20
AA20
AA18
AB18
AB21
AD21
AD19
Y18
AD17
W 16
W 14
Y14
Y17
AB17
AB15
AD15
AB13
AD13
Y12
W 11
AB14
AA14
AB12
AA12

MA_DM0
MA_DM1
MA_DM2
MA_DM3
MA_DM4
MA_DM5
MA_DM6
MA_DM7

E12
C15
E19
F24
AC24
Y19
AB16
Y13

MA_DQS_H0
MA_DQS_L0
MA_DQS_H1
MA_DQS_L1
MA_DQS_H2
MA_DQS_L2
MA_DQS_H3
MA_DQS_L3
MA_DQS_H4
MA_DQS_L4
MA_DQS_H5
MA_DQS_L5
MA_DQS_H6
MA_DQS_L6
MA_DQS_H7
MA_DQS_L7

G13
H13
G16
G15
C22
C21
G22
G21
AD23
AC23
AB19
AB20
Y15
W 15
W 12
W 13

MEM_MA_DATA0
MEM_MA_DATA1
MEM_MA_DATA2
MEM_MA_DATA3
MEM_MA_DATA4
MEM_MA_DATA5
MEM_MA_DATA6
MEM_MA_DATA7
MEM_MA_DATA8
MEM_MA_DATA9
MEM_MA_DATA10
MEM_MA_DATA11
MEM_MA_DATA12
MEM_MA_DATA13
MEM_MA_DATA14
MEM_MA_DATA15
MEM_MA_DATA16
MEM_MA_DATA17
MEM_MA_DATA18
MEM_MA_DATA19
MEM_MA_DATA20
MEM_MA_DATA21
MEM_MA_DATA22
MEM_MA_DATA23
MEM_MA_DATA24
MEM_MA_DATA25
MEM_MA_DATA26
MEM_MA_DATA27
MEM_MA_DATA28
MEM_MA_DATA29
MEM_MA_DATA30
MEM_MA_DATA31
MEM_MA_DATA32
MEM_MA_DATA33
MEM_MA_DATA34
MEM_MA_DATA35
MEM_MA_DATA36
MEM_MA_DATA37
MEM_MA_DATA38
MEM_MA_DATA39
MEM_MA_DATA40
MEM_MA_DATA41
MEM_MA_DATA42
MEM_MA_DATA43
MEM_MA_DATA44
MEM_MA_DATA45
MEM_MA_DATA46
MEM_MA_DATA47
MEM_MA_DATA48
MEM_MA_DATA49
MEM_MA_DATA50
MEM_MA_DATA51
MEM_MA_DATA52
MEM_MA_DATA53
MEM_MA_DATA54
MEM_MA_DATA55
MEM_MA_DATA56
MEM_MA_DATA57
MEM_MA_DATA58
MEM_MA_DATA59
MEM_MA_DATA60
MEM_MA_DATA61
MEM_MA_DATA62
MEM_MA_DATA63
MEM_MA_DM0
MEM_MA_DM1
MEM_MA_DM2
MEM_MA_DM3
MEM_MA_DM4
MEM_MA_DM5
MEM_MA_DM6
MEM_MA_DM7

MEM_MA_DATA[0..63]

6

4

3

MEM_MA_DM[0..7]

6
2

MEM_MA_DQS0_P
MEM_MA_DQS0_N
MEM_MA_DQS1_P
MEM_MA_DQS1_N
MEM_MA_DQS2_P
MEM_MA_DQS2_N
MEM_MA_DQS3_P
MEM_MA_DQS3_N
MEM_MA_DQS4_P
MEM_MA_DQS4_N
MEM_MA_DQS5_P
MEM_MA_DQS5_N
MEM_MA_DQS6_P
MEM_MA_DQS6_N
MEM_MA_DQS7_P
MEM_MA_DQS7_N

6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6

MEM_MA_CLK7_P
MEM_MB_CLK7_P

SOCKET_638_PIN
C636
1.5P/50V_4

C640
1.5P/50V_4

1

1

PLACE CLOSE TO PROCESSOR
WITHIN 1.5 INCH

MEM_MB_CLK7_N

MEM_MA_CLK7_N
MEM_MA_CLK1_P

MEM_MB_CLK1_P
C293
1.5P/50V_4

C291
1.5P/50V_4

PROJECT : OP8
Quanta Computer Inc.

MEM_MA_CLK1_N
MEM_MB_CLK1_N
Size
Custom
NB5/RD2

Document Number

Date: Friday, March 20, 2009
A

B

C

D

Rev
1A

S1G2 DDRII MEMORY I/F 2/3
Sheet
E

4

of

42

5

4

3

2

1

05

U24F
U24E

+VCORE0

D

+CPUVDDNB

+1.8VSUS

VDD0_1
VDD0_2
VDD0_3
VDD0_4
VDD0_5
VDD0_6
VDD0_7
VDD0_8
VDD0_9
VDD0_10
VDD0_11
VDD0_12
VDD0_13
VDD0_14
VDD0_15
VDD0_16
VDD0_17
VDD0_18
VDD0_19
VDD0_20
VDD0_21
VDD0_22
VDD0_23

K16
M16
P16
T16
V16

VDDNB_1
VDDNB_2
VDDNB_3
VDDNB_4
VDDNB_5

H25
J17
K18
K21
K23
K25
L17
M18
M21
M23
M25
N17

VDDIO1
VDDIO2
VDDIO3
VDDIO4
VDDIO5
VDDIO6
VDDIO7
VDDIO8
VDDIO9
VDDIO10
VDDIO11
VDDIO12

2A

C

+VCORE1

G4
H2
J9
J11
J13
J15
K6
K10
K12
K14
L4
L7
L9
L11
L13
L15
M2
M6
M8
M10
N7
N9
N11

3A

AA4
AA11
AA13
AA15
AA17
AA19
AB2
AB7
AB9
AB23
AB25
AC11
AC13
AC15
AC17
AC19
AC21
AD6
AD8
AD25
AE11
AE13
AE15
AE17
AE19
AE21
AE23
B4
B6
B8
B9
B11
B13
B15
B17
B19
B21
B23
B25
D6
D8
D9
D11
D13
D15
D17
D19
D21
D23
D25
E4
F2
F11
F13
F15
F17
F19
F21
F23
F25
H7
H9
H21
H23
J4

VDD1_1
VDD1_2
VDD1_3
VDD1_4
VDD1_5
VDD1_6
VDD1_7
VDD1_8
VDD1_9
VDD1_10
VDD1_11
VDD1_12
VDD1_13
VDD1_14
VDD1_15
VDD1_16
VDD1_17
VDD1_18
VDD1_19
VDD1_20
VDD1_21
VDD1_22
VDD1_23
VDD1_24
VDD1_25
VDD1_26

P8
P10
R4
R7
R9
R11
T2
T6
T8
T10
T12
T14
U7
U9
U11
U13
U15
V6
V8
V10
V12
V14
W4
Y2
AC4
AD2

VDDIO27
VDDIO26
VDDIO25
VDDIO24
VDDIO23
VDDIO22
VDDIO21
VDDIO20
VDDIO19
VDDIO18
VDDIO17
VDDIO16
VDDIO15
VDDIO14
VDDIO13

Y25
V25
V23
V21
V18
U17
T25
T23
T21
T18
R17
P25
P23
P21
P18

+1.8VSUS

SOCKET_638_PIN
+1.8VSUS

3 CNTR_VREF
R157
390_4

R158
1K/F_4

2

R156
390_4

Q23
1

3

*BSS138_NL/SOT23
18,32

MBDATA2

MBDATA2

CPU_SIC
Q24
1

3

*BSS138_NL/SOT23
B

CPU_SIC

3

SMBALERT#

CPU_SID

CPU_SID

3

Q22
1

3

VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98
VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129

J6
J8
J10
J12
J14
J16
J18
K2
K7
K9
K11
K13
K15
K17
L6
L8
L10
L12
L14
L16
L18
M7
M9
AC6
M17
N4
N8
N10
N16
N18
P2
P7
P9
P11
P17
R8
R10
R16
R18
T7
T9
T11
T13
T15
T17
U4
U6
U8
U10
U12
U14
U16
U18
V2
V7
V9
V11
V13
V15
V17
W6
Y21
Y23
N6

+VCORE0

BOTTOM SIDE DECOUPLING

C244
22U/6.3V_8

C262
22U/6.3V_8

C261
22U/6.3V_8

C260
22U/6.3V_8

C241
0.22U/6.3V_4

C242
0.01U/16V_4

C255
180P/50V_4
D

+VCORE1

C181
22U/6.3V_8

C220
22U/6.3V_8

C221
22U/6.3V_8

+CPUVDDNB

C218
22U/6.3V_8

C620
0.22U/6.3V_4

C180
C619
0.01U/16V_4 180P/50V_4

C185
0.01U/16V_4

+1.8VSUS

C215
22U/6.3V_8

C184
C237
22U/6.3V_8 22U/6.3V_8

C193
22U/6.3V_8

C240
22U/6.3V_8

C263
C191
0.22U/6.3V_4 0.22U/6.3V_4

C668
180P/50V_4

C719
180P/50V_4

C

DECOUPLING BETWEEN PROCESSOR AND DIMMs
PLACE CLOSE TO PROCESSOR AS POSSIBLE
+1.8VSUS

C669
4.7U/6.3V_6

C722
4.7U/6.3V_6

C720
4.7U/6.3V_6

C667
4.7U/6.3V_6

C73
0.22U/6.3V_4

C194
0.22U/6.3V_4

+1.8VSUS

C107
C700
C670
C721
0.22U/6.3V_4 0.22U/6.3V_4 0.01U/16V_4 0.01U/16V_4

C708
180P/50V_4

SOCKET_638_PIN

2

MBCLK2

MBCLK2

2

18,32

VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65

B

CPU_ALERT

CPU_ALERT 3

PROCESSOR POWER AND GROUND

*BSS138_NL/SOT23

+3V

+3V
+VCORE0

R162

10K/F_4

R142
10K/F_4

*0_4

SYS_SHDN#

reserve for
power shutdown
( if can )

10K/F_4

7

SDA

DXP

2

6

ALERT#

DXN

3

OVERT#

GND

5

4

13 PM_THERM#

VCC

H_THRMDA 3
C325
1000P/50V_4
H_THRMDC

3

2

+3VPCU

+1.8V

EC2

0.01U/16V_4

+3VPCU

EC10

0.01U/16V_4

+5V

EC1

*0.01U/16V_4

EC14

*0.01U/16V_4

EC13

*0.01U/16V_4

EC12

*0.01U/16V_4

2

PQ56

3920_RST# 32,40

ECPWROK

1

10K/F_4

*2N7002E-G

+VGA_CORE

ECPWROK 16,32

4

0.01U/16V_4

C31

0.01U/16V_4

+1.8VSUS

EC8

0.01U/16V_4

+5V

+5V

EC5

0.01U/16V_4

+3VPCU

+3V

+1.8V

For fix HyperTransport nets
across plane splits

+3VS5

+3V

TEMP_FAIL 18

EC11

EC9

EC6

PROJECT : OP8
Quanta Computer Inc.

EC3

ADD VGA TEMP_ FAIL function
M92 is active Hi

Size
Custom
*0.1U/10V_4

3

A

+1.8V

*0.1U/10V_4

*0.1U/10V_4

*0.1U/10V_4

NB5/RD2

Document Number

2

Rev
1A

S1G2 PWR & GND 3/3

Date: Friday, March 20, 2009
5

0.01U/16V_4

C35

+3V
+3VS5

2

SMBALERT#

C39

+3V

*10K/F_4

1

Q43
*MMBT3904
3

+3V

CH501H-40PT

R459

1

0.01U/16V_4

0.01U/16V_4

D25

MMBT3904
2

R165

*10K/F_4

CPU_THERMTRIP_L#

3 CPU_THERMTRIP_L#

3920_RST#

3

R450

EC4

+VCORE1
C37

*CH500H

*0_4/S

SMBALERT#

G786P8

+1.8VSUS

+1.8V

34,40

Q26

MSOP

A

R161

3

MBDATA2

SCLK

1

1

18,32

+3VPCU

D26

U6

8

MBCLK2

0.01U/16V_4

2

C355
0.1U/10V_4

18,32

SYS_SHDN#

R140

EC7

1

R141

+1.8VSUS

Sheet
1

5

of

42

5

4

3

2

13
31
51
70
131
148
169
188

DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7

4
4
4
4
4
4
4
4

MEM_MA_DQS0_N
MEM_MA_DQS1_N
MEM_MA_DQS2_N
MEM_MA_DQS3_N
MEM_MA_DQS4_N
MEM_MA_DQS5_N
MEM_MA_DQS6_N
MEM_MA_DQS7_N

11
29
49
68
129
146
167
186

DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7

30
32
164
166

CK0
CK0
CK1
CK1

MEM_MA_CLK1_P
MEM_MA_CLK1_N
MEM_MA_CLK7_P
MEM_MA_CLK7_N

79
80

4,7 MEM_MA_CKE0
4,7 MEM_MA_CKE1
MEM_MA_RAS#
MEM_MA_CAS#
MEM_MA_WE#
MEM_MA0_CS#0
MEM_MA0_CS#1

108
113
109
110
115

4,7 MEM_MA0_ODT0
4,7 MEM_MA0_ODT1

114
119

4,7
4,7
4,7
4,7
4,7

B

2,7,13,33 PDAT_SMB
2,7,13,33 PCLK_SMB

DIM1_SA0
DIM1_SA1

198
200

PDAT_SMB
PCLK_SMB

195
197
199

+3V

C622
0.1U/10V_4

+0.9VSMVREF_DIMM

C323
1000P/50V_4

2
3
8
9
12
15
18
21
24
27
28
33
34
39
40
41
42
47
48
53
54

RAS
CAS
WE
S0
S1
ODT0
ODT1
SA0
SA1
SDA
SCL
VDDspd

A

NC1
NC2
NC3
NC4
NC/TEST

VSS0
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20

MEMHOT_SODIMM#_1
MEM_MA_RESET#1
MEM_MA_NC5

R88

*0_4/S

VSS56
VSS55
VSS54
VSS53
VSS52
VSS51
VSS50
VSS49
VSS48
VSS47
VSS46
VSS45
VSS44
VSS43
VSS42
VSS41
VSS40
VSS39
VSS38
VSS37
VSS36
VSS35
VSS34

196
193
190
187
184
183
178
177
172
171
168
165
162
161
156
155
150
149
145
144
139
138
133

81
82
87
88
95
96
103
104
111
112
117
118
107
106
85

BA0
BA1
BA2

MEM_MB_DM0
MEM_MB_DM1
MEM_MB_DM2
MEM_MB_DM3
MEM_MB_DM4
MEM_MB_DM5
MEM_MB_DM6
MEM_MB_DM7

10
26
52
67
130
147
170
185

DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7

MEM_MB_DQS0_P
MEM_MB_DQS1_P
MEM_MB_DQS2_P
MEM_MB_DQS3_P
MEM_MB_DQS4_P
MEM_MB_DQS5_P
MEM_MB_DQS6_P
MEM_MB_DQS7_P

13
31
51
70
131
148
169
188

DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7

4
4
4
4
4
4
4
4

MEM_MB_DQS0_N
MEM_MB_DQS1_N
MEM_MB_DQS2_N
MEM_MB_DQS3_N
MEM_MB_DQS4_N
MEM_MB_DQS5_N
MEM_MB_DQS6_N
MEM_MB_DQS7_N

11
29
49
68
129
146
167
186

DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7

4
4
4
4

MEM_MB_CLK1_P
MEM_MB_CLK1_N
MEM_MB_CLK7_P
MEM_MB_CLK7_N

30
32
164
166

CK0
CK0
CK1
CK1

4,7 MEM_MB_CKE0
4,7 MEM_MB_CKE1

79
80

4,7 MEM_MB_RAS#
4,7 MEM_MB_CAS#
4,7 MEM_MB_WE#
4,7 MEM_MB0_CS#0
4,7 MEM_MB0_CS#1

108
113
109
110
115

4,7 MEM_MB0_ODT0
4,7 MEM_MB0_ODT1
MEMHOT_SODIMM# 7

114
119

T68

DIM2_SA0
DIM2_SA1

198
200

T63

PDAT_SMB
PCLK_SMB

195
197
199

C26
0.1U/10V_4

+0.9VSMVREF_DIMM

C321
0.1U/10V_4

+1.8VSUS

R130
2K/F_4

+0.9VSMVREF_DIMM

4,37 +0.9VSMVREF

R131

*0_4

+0.9VSMVREF_DIMM

R119
2K/F_4

Only for reserved

C318
1000P/50V_4

1
2
o3
8
9
12
15
18
21
24
27
28
33
34
39
40
41
42
47
48
53
54

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63

CKE0
CKE1
RAS
CAS
WE
S0
S1
ODT0
ODT1
SA0
SA1
SDA
SCL
VDDspd
VREF
VSS0
VSS1
oVSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20

MEM_MB_DATA[0..63] 4

CN18

VDD0
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
VDD10
VDD11

50
69
83
120
163

MEM_MB_BANK0
MEM_MB_BANK1
MEM_MB_BANK2

4
4
4
4
4
4
4
4

+3V

VREF

201
202

C324
0.1U/10V_4

1

CKE0
CKE1

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15

SO-DIMM
(REVERSE)

MEM_MA_DQS0_P
MEM_MA_DQS1_P
MEM_MA_DQS2_P
MEM_MA_DQS3_P
MEM_MA_DQS4_P
MEM_MA_DQS5_P
MEM_MA_DQS6_P
MEM_MA_DQS7_P

4 MEM_MB_DM[0..7]

102
101
100
99
98
97
94
92
93
91
105
90
89
116
86
84

NC1
NC2
NC3
NC4
NC/TEST

VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33

4
4
4
4
4
4
4
4

4,7 MEM_MB_BANK[0..2]

MEM_MB_ADD0
MEM_MB_ADD1
MEM_MB_ADD2
MEM_MB_ADD3
MEM_MB_ADD4
MEM_MB_ADD5
MEM_MB_ADD6
MEM_MB_ADD7
MEM_MB_ADD8
MEM_MB_ADD9
MEM_MB_ADD10
MEM_MB_ADD11
MEM_MB_ADD12
MEM_MB_ADD13
MEM_MB_ADD14
MEM_MB_ADD15

GND
GND

4
4
4
4

DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7

GND
GND

C

10
26
52
67
130
147
170
185

MEM_MA_DATA0
MEM_MA_DATA1
MEM_MA_DATA2
MEM_MA_DATA3
MEM_MA_DATA4
MEM_MA_DATA5
MEM_MA_DATA6
MEM_MA_DATA7
MEM_MA_DATA8
MEM_MA_DATA9
MEM_MA_DATA10
MEM_MA_DATA11
MEM_MA_DATA12
MEM_MA_DATA13
MEM_MA_DATA14
MEM_MA_DATA15
MEM_MA_DATA16
MEM_MA_DATA17
MEM_MA_DATA18
MEM_MA_DATA19
MEM_MA_DATA20
MEM_MA_DATA21
MEM_MA_DATA22
MEM_MA_DATA23
MEM_MA_DATA24
MEM_MA_DATA25
MEM_MA_DATA26
MEM_MA_DATA27
MEM_MA_DATA28
MEM_MA_DATA29
MEM_MA_DATA30
MEM_MA_DATA31
MEM_MA_DATA36
MEM_MA_DATA37
MEM_MA_DATA35
MEM_MA_DATA39
MEM_MA_DATA38
MEM_MA_DATA32
MEM_MA_DATA33
MEM_MA_DATA34
MEM_MA_DATA40
MEM_MA_DATA41
MEM_MA_DATA46
MEM_MA_DATA47
MEM_MA_DATA44
MEM_MA_DATA45
MEM_MA_DATA42
MEM_MA_DATA43
MEM_MA_DATA52
MEM_MA_DATA49
MEM_MA_DATA54
MEM_MA_DATA55
MEM_MA_DATA53
MEM_MA_DATA48
MEM_MA_DATA51
MEM_MA_DATA50
MEM_MA_DATA61
MEM_MA_DATA60
MEM_MA_DATA63
MEM_MA_DATA62
MEM_MA_DATA56
MEM_MA_DATA57
MEM_MA_DATA58
MEM_MA_DATA59

59
60
65
66
71
72
77
78
121
122
127
128
132

MEM_MA_DM0
MEM_MA_DM1
MEM_MA_DM2
MEM_MA_DM3
MEM_MA_DM4
MEM_MA_DM5
MEM_MA_DM6
MEM_MA_DM7

5
7
17
19
4
6
14
16
23
25
35
37
20
22
36
38
43
45
55
57
44
46
56
58
61
63
73
75
62
64
74
76
123
125
135
137
124
126
134
136
141
143
151
153
140
142
152
154
157
159
173
175
158
160
174
176
179
181
189
191
180
182
192
194

4,7 MEM_MB_ADD[0..15]

201
202

BA0
BA1
BA2

SO-DIMM
(Normal)

4 MEM_MA_DM[0..7]

MEM_MA_BANK0 107
MEM_MA_BANK1 106
MEM_MA_BANK2 85

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63

VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33

4,7 MEM_MA_BANK[0..2]

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15

59
60
65
66
71
72
77
78
121
122
127
128
132

D

102
101
100
99
98
97
94
92
93
91
105
90
89
116
86
84

MEM_MA_DATA[0..63] 4

CN17

VDD0
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
VDD10
VDD11

4,7 MEM_MA_ADD[0..15]
MEM_MA_ADD0
MEM_MA_ADD1
MEM_MA_ADD2
MEM_MA_ADD3
MEM_MA_ADD4
MEM_MA_ADD5
MEM_MA_ADD6
MEM_MA_ADD7
MEM_MA_ADD8
MEM_MA_ADD9
MEM_MA_ADD10
MEM_MA_ADD11
MEM_MA_ADD12
MEM_MA_ADD13
MEM_MA_ADD14
MEM_MA_ADD15

06

+1.8VSUS
81
82
87
88
95
96
103
104
111
112
117
118

+1.8VSUS

1

VSS56
VSS55
VSS54
VSS53
VSS52
VSS51
VSS50
VSS49
VSS48
VSS47
VSS46
VSS45
VSS44
VSS43
VSS42
VSS41
VSS40
VSS39
VSS38
VSS37
VSS36
VSS35
VSS34

5
7
17
19
4
6
14
16
23
25
35
37
20
22
36
38
43
45
55
57
44
46
56
58
61
63
73
75
62
64
74
76
123
125
135
137
124
126
134
136
141
143
151
153
140
142
152
154
157
159
173
175
158
160
174
176
179
181
189
191
180
182
192
194

MEM_MB_DATA4
MEM_MB_DATA5
MEM_MB_DATA2
MEM_MB_DATA3
MEM_MB_DATA0
MEM_MB_DATA1
MEM_MB_DATA6
MEM_MB_DATA7
MEM_MB_DATA13
MEM_MB_DATA12
MEM_MB_DATA11
MEM_MB_DATA10
MEM_MB_DATA8
MEM_MB_DATA9
MEM_MB_DATA14
MEM_MB_DATA15
MEM_MB_DATA16
MEM_MB_DATA17
MEM_MB_DATA18
MEM_MB_DATA19
MEM_MB_DATA20
MEM_MB_DATA21
MEM_MB_DATA22
MEM_MB_DATA23
MEM_MB_DATA24
MEM_MB_DATA25
MEM_MB_DATA26
MEM_MB_DATA27
MEM_MB_DATA28
MEM_MB_DATA29
MEM_MB_DATA30
MEM_MB_DATA31
MEM_MB_DATA37
MEM_MB_DATA36
MEM_MB_DATA34
MEM_MB_DATA35
MEM_MB_DATA33
MEM_MB_DATA32
MEM_MB_DATA38
MEM_MB_DATA39
MEM_MB_DATA40
MEM_MB_DATA45
MEM_MB_DATA47
MEM_MB_DATA46
MEM_MB_DATA44
MEM_MB_DATA41
MEM_MB_DATA43
MEM_MB_DATA42
MEM_MB_DATA52
MEM_MB_DATA53
MEM_MB_DATA50
MEM_MB_DATA51
MEM_MB_DATA48
MEM_MB_DATA49
MEM_MB_DATA54
MEM_MB_DATA55
MEM_MB_DATA56
MEM_MB_DATA60
MEM_MB_DATA58
MEM_MB_DATA59
MEM_MB_DATA61
MEM_MB_DATA57
MEM_MB_DATA62
MEM_MB_DATA63

50
69
83
120
163

MEMHOT_SODIMM#_2 R82
MEM_MB_RESET#2
T69
MEM_MB_NC5

D

C

*0_4/S

MEMHOT_SODIMM#

B

T62

196
193
190
187
184
183
178
177
172
171
168
165
162
161
156
155
150
149
145
144
139
138
133

DDR SO-DIMM SOCKET 1.8V
A

H=9.2

DDR SO-DIMM SOCKET 1.8V

H=5.2
DIM2_SA0
DIM2_SA1
R22
R20

10K/F_4
10K/F_4

DIM1_SA0
DIM1_SA1

R19
R21

10K/F_4
10K/F_4

PROJECT : OP8
Quanta Computer Inc.

+3V

SMbus address A2
Size
Custom

SMbus address A0
NB5/RD2

Document Number

5

4

3

2

Rev
1A

DDR2 SODIMMS: A/B CHANNEL

Date: Friday, March 20, 2009

Sheet
1

6

of

42

5

4

3

2

MEM_MA_ADD[0..15]

4,6 MEM_MA_ADD[0..15]

MEM_MB_BANK[0..2]

4,6 MEM_MB_BANK[0..2]

+0.9VSMVTT
MEM_MA_CKE0
MEM_MA_BANK2
MEM_MA_ADD12
MEM_MA_ADD9
MEM_MA_ADD8
MEM_MA_ADD5
MEM_MA_ADD3
MEM_MA_ADD1
MEM_MA_ADD10
MEM_MA_BANK0
MEM_MA_WE#
MEM_MA_CAS#
MEM_MA0_ODT1
MEM_MA0_CS#1
MEM_MA_ADD15
MEM_MA_CKE1

4,6 MEM_MA_CKE0
D

4,6
4,6
4,6
4,6

MEM_MA_WE#
MEM_MA_CAS#
MEM_MA0_ODT1
MEM_MA0_CS#1

4,6 MEM_MA_CKE1

4,6 MEM_MA0_CS#0
4,6 MEM_MA_RAS#

RP36

3
1
3
1
1
3
1
3
3
1
3
1
3
1
3
1

MEM_MA_ADD7 RP30
MEM_MA_ADD14
MEM_MA_ADD6 RP27
MEM_MA_ADD11

4
2
4
2

3 47_4P2R_4
1
3 47_4P2R_4
1

MEM_MA_ADD2
MEM_MA_ADD4

4
2

3 47_4P2R_4
1

C69

0.1U/10V_4

MEM_MA_BANK1 RP20
MEM_MA_ADD0

2
4

1 47_4P2R_4
3

C74

0.1U/10V_4

MEM_MA0_CS#0 RP14
MEM_MA_RAS#

4
2

3 47_4P2R_4
1

RP26
RP24
RP19
RP16
RP10
RP35

RP22

MEM_MA_ADD13 RP12
MEM_MA0_ODT0

C

4,6 MEM_MA0_ODT0

+0.9VSMVTT

47_4P2R_4

4
2
4
2
2
4
2
4
4
2
4
2
4
2
4
2

RP32

C132

0.1U/10V_4

C192

0.1U/10V_4

4,6 MEM_MB_CKE0
+1.8VSUS

47_4P2R_4
47_4P2R_4
C178

0.1U/10V_4

C70

0.1U/10V_4

C169

0.1U/10V_4

C66

0.1U/10V_4

+1.8VSUS

47_4P2R_4
47_4P2R_4

+1.8VSUS

47_4P2R_4
47_4P2R_4
C93

0.1U/10V_4

C213

0.1U/10V_4

C98

0.1U/10V_4

+1.8VSUS

47_4P2R_4

3 47_4P2R_4
1

4
2

07

MEM_MB_ADD[0..15]

4,6 MEM_MB_ADD[0..15]

MEM_MA_BANK[0..2]

4,6 MEM_MA_BANK[0..2]

1

C68

0.1U/10V_4

C158

0.1U/10V_4

C212

0.1U/10V_4

C87

0.1U/10V_4

C214

4,6
4,6
4,6
4,6
4,6

MEM_MB_WE#
MEM_MB_CAS#
MEM_MB0_ODT1
MEM_MB0_CS#1
MEM_MB_CKE1

+1.8VSUS

RP33

MEM_MB_ADD7
MEM_MB_ADD14

RP31

RP29
RP25
RP23
RP17
RP15
RP9
RP34

47_4P2R_4

4
2
2
4
4
2
4
2
4
2
4
2
4
2
2
4

3
1
1
3
3
1
3
1
3
1
3
1
3
1
1
3

4
2

3 47_4P2R_4
1

0.1U/10V_4

C159

0.1U/10V_4

C67

0.1U/10V_4

C85

0.1U/10V_4

C63

0.1U/10V_4

47_4P2R_4

+1.8VSUS
D

+1.8VSUS

47_4P2R_4
47_4P2R_4

+1.8VSUS

47_4P2R_4
C148

0.1U/10V_4

C62

0.1U/10V_4

C101

0.1U/10V_4

C206

0.1U/10V_4

C129

0.1U/10V_4

C207

0.1U/10V_4

C81

0.1U/10V_4

C205

0.1U/10V_4

47_4P2R_4

4
2

3 47_4P2R_4
1

MEM_MB_ADD2
MEM_MB_ADD4

RP21

4
2

3 47_4P2R_4
1

MEM_MB_BANK1
MEM_MB_ADD0

RP18

4
2

3 47_4P2R_4
1

4,6 MEM_MB0_CS#0
4,6 MEM_MB_RAS#

MEM_MB0_CS#0
MEM_MB_RAS#

RP13

4
2

3 47_4P2R_4
1

4,6 MEM_MB0_ODT0

MEM_MB0_ODT0
MEM_MB_ADD13

RP11

2
4

1 47_4P2R_4
3

+1.8VSUS

0.1U/10V_4

C197
47_4P2R_4

RP28

+1.8VSUS

C106
47_4P2R_4

MEM_MB_ADD6
MEM_MB_ADD11
+1.8VSUS

0.1U/10V_4

MEM_MB_CKE0
MEM_MB_BANK2
MEM_MB_ADD12
MEM_MB_ADD9
MEM_MB_ADD8
MEM_MB_ADD5
MEM_MB_ADD3
MEM_MB_ADD1
MEM_MB_ADD10
MEM_MB_BANK0
MEM_MB_WE#
MEM_MB_CAS#
MEM_MB0_ODT1
MEM_MB0_CS#1
MEM_MB_CKE1
MEM_MB_ADD15

C135

0.1U/10V_4

C71

0.1U/10V_4

+1.8VSUS

+1.8VSUS

+1.8VSUS

+1.8VSUS

+1.8VSUS
C

+1.8VSUS

C79
0.1U/10V_4

C177
0.1U/10V_4

C150
0.1U/10V_4

C714
0.1U/10V_4

C137
0.1U/10V_4

C75
0.1U/10V_4

PLACE CLOSE TO SOCKET( PER EMI/EMC)

B

B

+3VS5

+3V

R362
*10K/F_4
R363
*10K/F_4

3

CPU_MEMHOT# 3,13

Close DDR2 socket
+3V

U2

PDAT_SMB
PCLK_SMB

1
2

SDA
SCL

8

O.S

3

GND

C27

3

R361

+VS

0.1U/10V_4

MEMHOT_SODIMM#

*33_4

2
Q35
*2N7002E-G

2
Q36
*2N7002E-G

4

1

2,6,13,33 PDAT_SMB
2,6,13,33 PCLK_SMB

A0
A1
A2

1

+3V

7
6
5

*DS75U+T&R

A

+3V

R360

Address:92h

10K/F_4 MEMHOT_SODIMM#

A

MEMHOT_SODIMM# 6

PROJECT : OP8
Quanta Computer Inc.
Size
Custom
NB5/RD2

Document Number

Date: Friday, March 20, 2009
5

4

3

2

Rev
1A

DDR2 SODIMMS TERMINATIONS
Sheet
1

7

of

42

5

4

3

2

1

U25A

D

C

R430

Y25
Y24
V22
V23
V25
V24
U24
U25
T25
T24
P22
P23
P25
P24
N24
N25

HT_RXCAD0P
HT_RXCAD0N
HT_RXCAD1P
HT_RXCAD1N
HT_RXCAD2P
HT_RXCAD2N
HT_RXCAD3P
HT_RXCAD3N
HT_RXCAD4P
HT_RXCAD4N
HT_RXCAD5P
HT_RXCAD5N
HT_RXCAD6P
HT_RXCAD6N
HT_RXCAD7P
HT_RXCAD7N

PART 1 OF 6

HYPER TRANSPORT CPU I/F

HT_CPU_NB_CAD_H0
HT_CPU_NB_CAD_L0
HT_CPU_NB_CAD_H1
HT_CPU_NB_CAD_L1
HT_CPU_NB_CAD_H2
HT_CPU_NB_CAD_L2
HT_CPU_NB_CAD_H3
HT_CPU_NB_CAD_L3
HT_CPU_NB_CAD_H4
HT_CPU_NB_CAD_L4
HT_CPU_NB_CAD_H5
HT_CPU_NB_CAD_L5
HT_CPU_NB_CAD_H6
HT_CPU_NB_CAD_L6
HT_CPU_NB_CAD_H7
HT_CPU_NB_CAD_L7

HT_TXCAD0P
HT_TXCAD0N
HT_TXCAD1P
HT_TXCAD1N
HT_TXCAD2P
HT_TXCAD2N
HT_TXCAD3P
HT_TXCAD3N
HT_TXCAD4P
HT_TXCAD4N
HT_TXCAD5P
HT_TXCAD5N
HT_TXCAD6P
HT_TXCAD6N
HT_TXCAD7P
HT_TXCAD7N

D24
D25
E24
E25
F24
F25
F23
F22
H23
H22
J25
J24
K24
K25
K23
K22

HT_NB_CPU_CAD_H0
HT_NB_CPU_CAD_L0
HT_NB_CPU_CAD_H1
HT_NB_CPU_CAD_L1
HT_NB_CPU_CAD_H2
HT_NB_CPU_CAD_L2
HT_NB_CPU_CAD_H3
HT_NB_CPU_CAD_L3
HT_NB_CPU_CAD_H4
HT_NB_CPU_CAD_L4
HT_NB_CPU_CAD_H5
HT_NB_CPU_CAD_L5
HT_NB_CPU_CAD_H6
HT_NB_CPU_CAD_L6
HT_NB_CPU_CAD_H7
HT_NB_CPU_CAD_L7

HT_TXCAD8P
HT_TXCAD8N
HT_TXCAD9P
HT_TXCAD9N
HT_TXCAD10P
HT_TXCAD10N
HT_TXCAD11P
HT_TXCAD11N
HT_TXCAD12P
HT_TXCAD12N
HT_TXCAD13P
HT_TXCAD13N
HT_TXCAD14P
HT_TXCAD14N
HT_TXCAD15P
HT_TXCAD15N

F21
G21
G20
H21
J20
J21
J18
K17
L19
J19
M19
L18
M21
P21
P18
M18

HT_NB_CPU_CAD_H8
HT_NB_CPU_CAD_L8
HT_NB_CPU_CAD_H9
HT_NB_CPU_CAD_L9
HT_NB_CPU_CAD_H10
HT_NB_CPU_CAD_L10
HT_NB_CPU_CAD_H11
HT_NB_CPU_CAD_L11
HT_NB_CPU_CAD_H12
HT_NB_CPU_CAD_L12
HT_NB_CPU_CAD_H13
HT_NB_CPU_CAD_L13
HT_NB_CPU_CAD_H14
HT_NB_CPU_CAD_L14
HT_NB_CPU_CAD_H15
HT_NB_CPU_CAD_L15

HT_TXCLK0P
HT_TXCLK0N
HT_TXCLK1P
HT_TXCLK1N

H24
H25
L21
L20

HT_NB_CPU_CLK_H0
HT_NB_CPU_CLK_L0
HT_NB_CPU_CLK_H1
HT_NB_CPU_CLK_L1

HT_CPU_NB_CAD_H8
HT_CPU_NB_CAD_L8
HT_CPU_NB_CAD_H9
HT_CPU_NB_CAD_L9
HT_CPU_NB_CAD_H10
HT_CPU_NB_CAD_L10
HT_CPU_NB_CAD_H11
HT_CPU_NB_CAD_L11
HT_CPU_NB_CAD_H12
HT_CPU_NB_CAD_L12
HT_CPU_NB_CAD_H13
HT_CPU_NB_CAD_L13
HT_CPU_NB_CAD_H14
HT_CPU_NB_CAD_L14
HT_CPU_NB_CAD_H15
HT_CPU_NB_CAD_L15

AC24
AC25
AB25
AB24
AA24
AA25
Y22
Y23
W 21
W 20
V21
V20
U20
U21
U19
U18

HT_CPU_NB_CLK_H0
HT_CPU_NB_CLK_L0
HT_CPU_NB_CLK_H1
HT_CPU_NB_CLK_L1

T22
T23
AB23
AA22

HT_RXCLK0P
HT_RXCLK0N
HT_RXCLK1P
HT_RXCLK1N

HT_CPU_NB_CTL_H0
HT_CPU_NB_CTL_L0
HT_CPU_NB_CTL_H1
HT_CPU_NB_CTL_L1

M22
M23
R21
R20

HT_RXCTL0P
HT_RXCTL0N
HT_RXCTL1P
HT_RXCTL1N

HT_TXCTL0P
HT_TXCTL0N
HT_TXCTL1P
HT_TXCTL1N

M24
M25
P19
R18

HT_NB_CPU_CTL_H0
HT_NB_CPU_CTL_L0
HT_NB_CPU_CTL_H1
HT_NB_CPU_CTL_L1

C23
A24

HT_RXCALP
HT_RXCALN

HT_TXCALP
HT_TXCALN

B24
B25

HT_TXCALP R434
HT_TXCALN

1.21K/F_4

HT_RXCALP
HT_RXCALN

HT_RXCAD8P
HT_RXCAD8N
HT_RXCAD9P
HT_RXCAD9N
HT_RXCAD10P
HT_RXCAD10N
HT_RXCAD11P
HT_RXCAD11N
HT_RXCAD12P
HT_RXCAD12N
HT_RXCAD13P
HT_RXCAD13N
HT_RXCAD14P
HT_RXCAD14N
HT_RXCAD15P
HT_RXCAD15N

HT_CPU_NB_CAD_H[15..0]
HT_CPU_NB_CAD_L[15..0]

HT_CPU_NB_CAD_H[15..0]

3

HT_CPU_NB_CAD_L[15..0]

3

HT_CPU_NB_CLK_H[1..0]

3

HT_CPU_NB_CLK_L[1..0]

3

HT_CPU_NB_CLK_H[1..0]
HT_CPU_NB_CLK_L[1..0]
HT_CPU_NB_CTL_H[1..0]
HT_CPU_NB_CTL_L[1..0]

HT_CPU_NB_CTL_H[1..0]

3

HT_CPU_NB_CTL_L[1..0]

3
D

HT_NB_CPU_CAD_H[15..0]
HT_NB_CPU_CAD_L[15..0]

HT_NB_CPU_CAD_H[15..0]

3

HT_NB_CPU_CAD_L[15..0]

3

HT_NB_CPU_CLK_H[1..0]

HT_NB_CPU_CLK_H[1..0]

3

HT_NB_CPU_CLK_L[1..0]

3

HT_NB_CPU_CLK_L[1..0]
HT_NB_CPU_CTL_H[1..0]
HT_NB_CPU_CTL_L[1..0]

HT_NB_CPU_CTL_H[1..0]

3

HT_NB_CPU_CTL_L[1..0]

3

RS880

signals

08

RX880
RES CHIP 1.21K 1/16W +-1%(0402)
P/N : CS21212FB18

HT_TXCALP
HT_TXCALN

R430
301 ohm 1%

R430
1.21k ohm 1%

R434
301 ohm 1%

R434
1.21k ohm 1%

RES CHIP 301 1/16W +-1%(0402)
P/N : CS13012FB14

HT_RXCALP
HT_RXCALN

C

1.21K/F_4

RS880
U19

L2
L3

BA0
BA1

SPM_A12
SPM_A11
SPM_A10
SPM_A9
SPM_A8
SPM_A7
SPM_A6
SPM_A5
SPM_A4
SPM_A3
SPM_A2
SPM_A1
SPM_A0

R2
P7
M2
P3
P8
P2
N7
N3
N8
N2
M7
M3
M8

A12
A11
A10/AP
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0

K8
J8

CK
CK

K2

CKE

SPM_CLKN
SPM_CLKP

*100_4

Within 200mils

SPM_CKE

SPM_CS#

L8

CS

SPM_WE#

K3

WE

SPM_RAS#

K7

RAS

SPM_CAS#

L7

SPM_DM0
SPM_DM1

F3
B3

CAS
LDM
UDM

DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0

B9
B1
D9
D1
D3
D7
C2
C8
F9
F1
H9
H1
H3
H7
G2
G8

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10

A9
C1
C3
C7
C9
E9
G1
G3
G7
G9

VDD1
VDD2
VDD3
VDD4
VDD5

A1
E1
J9
M9
R1

VDDL
VSSDL

SPM_ODT

K9

ODT

SPM_DQS0P
SPM_DQS0N

F7
E8

LDQS
LDQS

J1
J7

R41
*1K/F_4

SPM_DQS1P
SPM_DQS1N
SPM_VREF

A

C57
*0.1U/10V_4

R34
*1K/F_4

SPM_BA2
SPM_A13

SI add A13 for side port function

B7
A8

UDQS
UDQS

J2

VREF

A2
E2
L1
R3
R7
R8

NC#A2
NC#E2
NC#L1
NC#R3
NC#R7
NC#R8

+1.8V

L61
*BLM18PG181SN1D(180,1.5A)_6
MEM_VDDQ_VDDL

C675
*1U/10V_4

VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9
VSSQ10

A7
B2
B8
D2
D8
E7
F2
F8
H2
H8

VSS1
VSS2
VSS3
VSS4
VSS5

A3
E3
J3
N1
P9

40mils wdith or more

U25D

+1.8V_MEM_VDDQ

+1.8V_MEM_VDDQ

C65
*0.1U/10V_4

This block is for UMA RS880 only , RX880 can
remove all component

SPM_DQ15
SPM_DQ14
SPM_DQ9
SPM_DQ12
SPM_DQ8
SPM_DQ10
SPM_DQ13
SPM_DQ11
SPM_DQ5
SPM_DQ3
SPM_DQ4
SPM_DQ1
SPM_DQ0
SPM_DQ7
SPM_DQ2
SPM_DQ6

AB12
AE16
V11
AE15
AA12
AB16
AB14
AD14
AD13
AD15
AC16
AE13
AC14
Y14

MEM_A0(NC)
MEM_A1(NC)
MEM_A2(NC)
MEM_A3(NC)
MEM_A4(NC)
MEM_A5(NC)
MEM_A6(NC)
MEM_A7(NC)
MEM_A8(NC)
MEM_A9(NC)
MEM_A10(NC)
MEM_A11(NC)
MEM_A12(NC)
MEM_A13(NC)

SPM_BA0
SPM_BA1
SPM_BA2

AD16
AE17
AD17

MEM_BA0(NC)
MEM_BA1(NC)
MEM_BA2(NC)

SPM_RAS#
SPM_CAS#
SPM_WE#
SPM_CS#
SPM_CKE
SPM_ODT

W 12
Y12
AD18
AB13
AB18
V14

MEM_RASb(NC)
MEM_CASb(NC)
MEM_W Eb(NC)
MEM_CSb(NC)
MEM_CKE(NC)
MEM_ODT(NC)

SPM_CLKP
SPM_CLKN

V15
W 14

MEM_CKP(NC)
MEM_CKN(NC)

R400
R397

*40.2/F_4 SPM_COMPP
AE12
*40.2/F_4 SPM_COMPN
AD12

+1.8V_MEM_VDDQ

MEM_COMPP(NC)
MEM_COMPN(NC)

+1.8V_MEM_VDDQ
R385

PAR 4 OF 6

SPM_A0
SPM_A1
SPM_A2
SPM_A3
SPM_A4
SPM_A5
SPM_A6
SPM_A7
SPM_A8
SPM_A9
SPM_A10
SPM_A11
SPM_A12
SPM_A13

SBD_MEM/DVO_I/F

R24

B

SPM_BA0
SPM_BA1

MEM_DQ0/DVO_VSYNC(NC)
MEM_DQ1/DVO_HSYNC(NC)
MEM_DQ2/DVO_DE(NC)
MEM_DQ3/DVO_D0(NC)
MEM_DQ4(NC)
MEM_DQ5/DVO_D1(NC)
MEM_DQ6/DVO_D2(NC)
MEM_DQ7/DVO_D4(NC)
MEM_DQ8/DVO_D3(NC)
MEM_DQ9/DVO_D5(NC)
MEM_DQ10/DVO_D6(NC)
MEM_DQ11/DVO_D7(NC)
MEM_DQ12(NC)
MEM_DQ13/DVO_D9(NC)
MEM_DQ14/DVO_D10(NC)
MEM_DQ15/DVO_D11(NC)

AA18
AA20
AA19
Y19
V17
AA17
AA15
Y15
AC20
AD19
AE22
AC18
AB20
AD22
AC22
AD21

SPM_DQ0
SPM_DQ1
SPM_DQ2
SPM_DQ3
SPM_DQ4
SPM_DQ5
SPM_DQ6
SPM_DQ7
SPM_DQ8
SPM_DQ9
SPM_DQ10
SPM_DQ11
SPM_DQ12
SPM_DQ13
SPM_DQ14
SPM_DQ15

MEM_DQS0P/DVO_IDCKP(NC)
MEM_DQS0N/DVO_IDCKN(NC)
MEM_DQS1P(NC)
MEM_DQS1N(NC)

Y17
W 18
AD20
AE21

SPM_DQS0P
SPM_DQS0N
SPM_DQS1P
SPM_DQS1N

MEM_DM0(NC)
MEM_DM1/DVO_D8(NC)

W 17
AE19

SPM_DM0
SPM_DM1

IOPLLVDD18(NC)
IOPLLVDD(NC)

AE23
AE24

IOPLLVSS(NC)

AD23

MEM_VREF(NC)

C38
*1U/10V_4

C646
*10U/6.3V_8

C43
*10U/6.3V_8

C47
*0.1U/10V_4

C44
*0.1U/10V_4

C42
*1U/10V_4

B

IOPLLVDD18 - memory PLL
not applicable to RX780
SI stage add L71 , L72
*BLM18PG181SN1D(180,1.5A)_6
*BLM18PG181SN1D(180,1.5A)_6
C680

AE18 SPM_VREF1

L71
L72

+1.8V
+1.1V

C681
*2.2U/6.3V_6

*2.2U/6.3V_6

IOPLLVDD- memory PLL
not applicable to RX780

RS880
R394

*1K/F_4

R393

*1K/F_4

C695

*0.1U/10V_4

C694

*0.1U/10V_4

A

+1.8V_MEM_VDDQ

PROJECT : OP8
Quanta Computer Inc.

*HYB18T512161B2F-25

Size
Custom
NB5/RD2

Document Number

4

3

2

Rev
1A

RS740/RS780-HT LINK I/F 1/5

Date: Friday, March 20, 2009
5

*0_6

Sheet
1

8

of

42

5

4

3

2

U25B

D

AE3
AD4
PCIE_RXP1
AE2
PCIE_RXN1
AD3
PCIE_RXP2_LAN AD1
PCIE_RXN2_LAN AD2
V5
W6
U5
U6
U8
U7

33 PCIE_RXP1
33 PCIE_RXN1
30 PCIE_RXP2_LAN
30 PCIE_RXN2_LAN

C

12
12
12
12
12
12
12
12

D4
C4
A3
B3
C2
C1
E5
F5
G5
G6
H5
H6
J6
J5
J7
J8
L5
L6
M8
L8
P7
M7
P5
M5
R8
P8
R6
R5
P4
P3
T4
T3

AA8
Y8
AA7
Y7
AA5
AA6
W5
Y5

PCIE_SB_NB_RX0P
PCIE_SB_NB_RX0N
PCIE_SB_NB_RX1P
PCIE_SB_NB_RX1N
PCIE_SB_NB_RX2P
PCIE_SB_NB_RX2N
PCIE_SB_NB_RX3P
PCIE_SB_NB_RX3N

GFX_RX0P
GFX_RX0N
GFX_RX1P
GFX_RX1N
GFX_RX2P
GFX_RX2N
GFX_RX3P
GFX_RX3N
GFX_RX4P
GFX_RX4N
GFX_RX5P
GFX_RX5N
GFX_RX6P
GFX_RX6N
GFX_RX7P
GFX_RX7N
GFX_RX8P
GFX_RX8N
GFX_RX9P
GFX_RX9N
GFX_RX10P
GFX_RX10N
GFX_RX11P
GFX_RX11N
GFX_RX12P
GFX_RX12N
GFX_RX13P
GFX_RX13N
GFX_RX14P
GFX_RX14N
GFX_RX15P
GFX_RX15N
GPP_RX0P
GPP_RX0N
GPP_RX1P
GPP_RX1N
GPP_RX2P
GPP_RX2N
GPP_RX3P
GPP_RX3N
GPP_RX4P
GPP_RX4N
GPP_RX5P
GPP_RX5N
SB_RX0P
SB_RX0N
SB_RX1P
SB_RX1N
SB_RX2P
SB_RX2N
SB_RX3P
SB_RX3N

C_PEG_TX15
C_PEG_TX#15
C_PEG_TX14
C_PEG_TX#14
C_PEG_TX13
C_PEG_TX#13
C_PEG_TX12
C_PEG_TX#12
C_PEG_TX11
C_PEG_TX#11
C_PEG_TX10
C_PEG_TX#10
C_PEG_TX9
C_PEG_TX#9
C_PEG_TX8
C_PEG_TX#8
C_PEG_TX7
C_PEG_TX#7
C_PEG_TX6
C_PEG_TX#6
C_PEG_TX5
C_PEG_TX#5
C_PEG_TX4
C_PEG_TX#4
C_PEG_TX3
C_PEG_TX#3
C_PEG_TX2
C_PEG_TX#2
C_PEG_TX1
C_PEG_TX#1
C_PEG_TX0
C_PEG_TX#0

C332
C333
C339
C338
C336
C337
C335
C334
C735
C734
C729
C730
C727
C724
C726
C725
C723
C718
C716
C717
C710
C712
C713
C715
C707
C709
C706
C705
C703
C704
C699
C701

PCIE_TXP1_C
PCIE_TXN1_C
PCIE_TXP2_C
PCIE_TXN2_C

C88
C89
C679
C696

GFX_TX0P
GFX_TX0N
GFX_TX1P
GFX_TX1N
GFX_TX2P
GFX_TX2N
GFX_TX3P
GFX_TX3N
GFX_TX4P
GFX_TX4N
GFX_TX5P
GFX_TX5N
GFX_TX6P
GFX_TX6N
GFX_TX7P
GFX_TX7N
GFX_TX8P
GFX_TX8N
GFX_TX9P
GFX_TX9N
GFX_TX10P
GFX_TX10N
GFX_TX11P
GFX_TX11N
GFX_TX12P
GFX_TX12N
GFX_TX13P
GFX_TX13N
GFX_TX14P
GFX_TX14N
GFX_TX15P
GFX_TX15N

A5
B5
A4
B4
C3
B2
D1
D2
E2
E1
F4
F3
F1
F2
H4
H3
H1
H2
J2
J1
K4
K3
K1
K2
M4
M3
M1
M2
N2
N1
P1
P2

GPP_TX0P
GPP_TX0N
GPP_TX1P
GPP_TX1N
GPP_TX2P
GPP_TX2N
GPP_TX3P
GPP_TX3N
GPP_TX4P
GPP_TX4N
GPP_TX5P
GPP_TX5N

AC1
AC2
AB4
AB3
AA2
AA1
Y1
Y2
Y4
Y3
V1
V2

SB_TX0P
SB_TX0N
SB_TX1P
SB_TX1N
SB_TX2P
SB_TX2N
SB_TX3P
SB_TX3N

AD7
AE7
AE6
AD6
AB6
AC6
AD5
AE5

A_TX0P_C
A_TX0N_C
A_TX1P_C
A_TX1N_C
A_TX2P_C
A_TX2N_C
A_TX3P_C
A_TX3N_C

PCE_CALRP(PCE_BCALRP)
PCE_CALRN(PCE_BCALRN)

AC8
AB8

NB_PCIECALRP
NB_PCIECALRN

PART 2 OF 6

PCIE I/F GFX

PEG_RX15
PEG_RX#15
PEG_RX14
PEG_RX#14
PEG_RX13
PEG_RX#13
PEG_RX12
PEG_RX#12
PEG_RX11
PEG_RX#11
PEG_RX10
PEG_RX#10
PEG_RX9
PEG_RX#9
PEG_RX8
PEG_RX#8
PEG_RX7
PEG_RX#7
PEG_RX6
PEG_RX#6
PEG_RX5
PEG_RX#5
PEG_RX4
PEG_RX#4
PEG_RX3
PEG_RX#3
PEG_RX2
PEG_RX#2
PEG_RX1
PEG_RX#1
PEG_RX0
PEG_RX#0

PCIE I/F GPP

PCIE I/F SB

17 PEG_RX#[15:0]

PEG_TX15
PEG_TX#15
PEG_TX14
PEG_TX#14
PEG_TX13
PEG_TX#13
PEG_TX12
PEG_TX#12
PEG_TX11
PEG_TX#11
PEG_TX10
PEG_TX#10
PEG_TX9
PEG_TX#9
PEG_TX8
PEG_TX#8
PEG_TX7
PEG_TX#7
PEG_TX6
PEG_TX#6
PEG_TX5
PEG_TX#5
PEG_TX4
PEG_TX#4
PEG_TX3
PEG_TX#3
PEG_TX2
PEG_TX#2
PEG_TX1
PEG_TX#1
PEG_TX0
PEG_TX#0

0.1U/10V_4
0.1U/10V_4
0.1U/10V_4
0.1U/10V_4
0.1U/10V_4
0.1U/10V_4
0.1U/10V_4
0.1U/10V_4
0.1U/10V_4
0.1U/10V_4
0.1U/10V_4
0.1U/10V_4
0.1U/10V_4
0.1U/10V_4
0.1U/10V_4
0.1U/10V_4
0.1U/10V_4
0.1U/10V_4
0.1U/10V_4
0.1U/10V_4
0.1U/10V_4
0.1U/10V_4
0.1U/10V_4
0.1U/10V_4
0.1U/10V_4
0.1U/10V_4
0.1U/10V_4
0.1U/10V_4
0.1U/10V_4
0.1U/10V_4
0.1U/10V_4
0.1U/10V_4

0.1U/10V_4
0.1U/10V_4
0.1U/10V_4
0.1U/10V_4

17 PEG_RX[15:0]

1

PEG_RX#[15:0]

PEG_TX#[15:0]

PEG_RX[15:0]

PEG_TX[15:0]

9

PEG_TX#[15:0] 17
PEG_TX[15:0] 17

Close to North Bridge

C_PEG_TX15
C_PEG_TX#15
C_PEG_TX14
C_PEG_TX#14
C_PEG_TX13
C_PEG_TX#13
C_PEG_TX12
C_PEG_TX#12

D

C_PEG_TX15 25
C_PEG_TX#15 25
C_PEG_TX14 25
C_PEG_TX#14 25
C_PEG_TX13 25
C_PEG_TX#13 25
C_PEG_TX12 25
C_PEG_TX#12 25

To HDMI CONN

PCIE_TXP1 33
PCIE_TXN1 33
PCIE_TXP2_LAN 30
PCIE_TXN2_LAN 30

TO WLAN
TO PCIE-LAN
C

C686
C687
C685
C684
C90
C91
C688
C689

0.1U/10V_4
0.1U/10V_4
0.1U/10V_4
0.1U/10V_4
0.1U/10V_4
0.1U/10V_4
0.1U/10V_4
0.1U/10V_4
R390
R389

PCIE_NB_SB_TX0P
PCIE_NB_SB_TX0N
PCIE_NB_SB_TX1P
PCIE_NB_SB_TX1N
PCIE_NB_SB_TX2P
PCIE_NB_SB_TX2N
PCIE_NB_SB_TX3P
PCIE_NB_SB_TX3N

1.27K/F_4
2K/F_4

12
12
12
12
12
12
12
12

+1.1V

RS880

RS880 Display Port Support (muxed on GFX)
GFX_TX0,TX1,TX2 and TX3
DP0
AUX0 and HPD0
B

B

GFX_TX4,TX5,TX6 and TX7
DP1
AUX1 and HPD1

A

A

PROJECT : OP8
Quanta Computer Inc.
Size
Custom
NB5/RD2

Document Number

5

4

3

2

Rev
1A

RS740/RS780-PCIE I/F 2/5

Date: Friday, March 20, 2009

Sheet
1

9

of

42

5

4

3

2

1

10

U25C

+1.8V_AVDDQ_NB

R91 for UMA use 140 ohm
for DIS
use 150 ohm

140ohm CS11402FB19
150ohm CS11502FB21

18,24

CRT_G

18,24

CRT_B

18,19,24 HSYNC_COM
18,19,24 VSYNC_COM
18,24 DDCDATA
18,24 DDCCLK

CRT_R_1

HSYNC_INT
VSYNC_INT
DDCDATA_INT
DDCCLK_INT

A11
B11
E8
F8

DAC_HSYNC(PWM_GPIO4)
DAC_VSYNC(PWM_GPIO6)
DAC_SDA(PCE_TCALRN)
DAC_SCL(PCE_RCALRN)

R102

*715/F_6

DAC_RSET_NB

G14

DAC_RSET(PWM_GPIO1)

+1.1V_PLLVDD
+1.8V_PLLVDD18

A12
D14
B12

PLLVDD(NC)
PLLVDD18(NC)
PLLVSS(NC)

H17

VDDA18HTPLL

CRT_B_1

2 NBHT_REFCLKP
2 NBHT_REFCLKN

RS780 R94

RS780

EXT_NB_OSC

2 NBGFX_CLKP
2 NBGFX_CLKN

4.7K_4

T8
T4
C

2 SBLINK_CLKP
2 SBLINK_CLKN
18,23 EDIDDATA
18,23 EDIDCLK
25 HDMI_DDC_DATA
25 HDMI_DDC_CLK

+1.8V_VDDA18PCIEPLL

D7
E7

VDDA18PCIEPLL1
VDDA18PCIEPLL2

NB_RST#_IN
NB_PWRGD_IN
NB_LDT_STOP#
NB_ALLOW_LDTSTOP

D8
A10
C10
C12

SYSRESETb
POWERGOOD
LDTSTOPb
ALLOW_LDTSTOP

NBHT_REFCLKP
NBHT_REFCLKN

C25
C24

HT_REFCLKP
HT_REFCLKN

NB_REFCLK_N

E11
F11

REFCLK_P/OSCIN(OSCIN)
REFCLK_N(PWM_GPIO3)

T78
T77
R14

*0_4/S

B18
A18
A17
B17
D20
D21
D18
D19

LB_DATAP0
LB_DATAN0
LB_DATAP1
LB_DATAN1
LB_DATAP2
LB_DATAN2
LB_DATAP3
LB_DATAN3

TXCLK_LP(DBG_GPIO1)
TXCLK_LN(DBG_GPIO3)
TXCLK_UP(PCIE_RESET_GPIO4)
TXCLK_UN(PCIE_RESET_GPIO1)

B16
A16
D16
D17

LA_CLK
LA_CLK#
LB_CLK
LB_CLK#

23
23
23
23
23
23

LB_DATAP0
LB_DATAN0
LB_DATAP1
LB_DATAN1
LB_DATAP2
LB_DATAN2

23
23
23
23
23
23
D

T80
T76
LA_CLK
LA_CLK#
LB_CLK
LB_CLK#

VDDLTP18(NC)
VSSLTP18(NC)

A13
B13

+1.8V_VDDLTP18_NB

VDDLT18_1(NC)
VDDLT18_2(NC)
VDDLT33_1(NC)
VDDLT33_2(NC)

A15
B15
A14
B14

+1.8V_VDDLT_18_NB

VSSLT1(VSS)
VSSLT2(VSS)
VSSLT3(VSS)
VSSLT4(VSS)
VSSLT5(VSS)
VSSLT6(VSS)
VSSLT7(VSS)

C14
D15
C16
C18
C20
E20
C22

I

GFX_REFCLKP
GFX_REFCLKN

I/O

NBGPP_CLKP
NBGPP_CLKN

U1
U2

GPP_REFCLKP
GPP_REFCLKN

I/O

SBLINK_CLKP
SBLINK_CLKN

V4
V3

GPPSB_REFCLKP(SB_REFCLKP)
GPPSB_REFCLKN(SB_REFCLKN)

NB_I2C_DATA
NB_I2C_CLK

A9
B9
B8
A8
B7
A7

I2C_DATA
I2C_CLK
DDC_DATA/AUX0N(NC)
DDC_CLK/AUX0P(NC)
AUX1P(NC)
AUX1N(NC)

R124
R103
R101

E9
F7
G12

LVDS_DIGON(PCE_TCALRP)
LVDS_BLON(PCE_RCALRP)
LVDS_ENA_BL(PWM_GPIO2)

23
23
23
23

Change from AMD request

RS880 only

T2
T1

*0_4
*0_4
*0_4

DISP_ON
DPST_PWM
LVDS_BLON

DISP_ON 19,23
DPST_PWM 19,23
LVDS_BLON 18,23

SI Remove for AMD request
C

STRP_DATA

RS780_AUX_CAL

T81

TXOUT_U0P(NC)
TXOUT_U0N(NC)
TXOUT_U1P(PCIE_RESET_GPIO3)
TXOUT_U1N(PCIE_RESET_GPIO2)
TXOUT_U2P(NC)
TXOUT_U2N(NC)
TXOUT_U3P(PCIE_RESET_GPIO5)
TXOUT_U3N(NC)

LA_DATAP0
LA_DATAN0
LA_DATAP1
LA_DATAN1
LA_DATAP2
LA_DATAN2
T75
T79

I

NBGFX_CLKP
NBGFX_CLKN

RS740_DFT_GPIO1

35 DYN_PWR_EN

RED(DFT_GPIO0)
REDb(NC)
GREEN(DFT_GPIO1)
GREENb(NC)
BLUE(DFT_GPIO3)
BLUEb(NC)

*0_4
*0_4
*0_4
*0_4

12 NB_PLTRST#
16 NB_PWRGD_IN

R108
4.7K_4

G18
G17
E18
F18
E19
F19

R120
R106
R104
R105

+1.8V_VDDA18HTPLL

+1.1V

C_Pr(DFT_GPIO5)
Y(DFT_GPIO2)
COMP_Pb(DFT_GPIO4)

*0_4
*140/F_4
*0_4
*150/F_4
*0_4
*150/F_4

Only for UMA

2

E17
F17
F15

R58
R91
R49
R92
R46
R93

CRT_G_1

A22
B22
A21
B21
B20
A20
A19
B19

PLL PWR
LVTM

CRT_R

TXOUT_L0P(NC)
TXOUT_L0N(NC)
TXOUT_L1P(NC)
TXOUT_L1N(NC)
TXOUT_L2P(NC)
TXOUT_L2N(DBG_GPIO0)
TXOUT_L3P(NC)
TXOUT_L3N(DBG_GPIO2)

PART 3 OF 6

PM

D

18,24

AVDD1(NC)
AVDD2(NC)
AVDDDI(NC)
AVSSDI(NC)
AVDDQ(NC)
AVSSQ(NC)

CRT/TVOUT

F12
E12
F14
G15
H15
H14

+1.8V_AVDDDI_NB

LA_DATAP0
LA_DATAN0
LA_DATAP1
LA_DATAN1
LA_DATAP2
LA_DATAN2
LA_DATAP3
LA_DATAN3

CLOCKs

+3V_AVDD_NB

B10

STRP_DATA

G11

RSVD

C8

MIS.

R438
*0_4/S

TMDS_HPD(NC)
HPD(NC)

D9
D10

TMDS_HPD0
TMDS_HPD1

TVCLKIN(PWM_GPIO5)

D12

SUS_STAT#_NB

THERMALDIODE_P
THERMALDIODE_N

AE8
AD8

TMDS_HPD

18,25

T74
R117

*0_4/S

SUS_STAT# 13

D13 TEST_EN

TESTMODE

R441
1.8K_4

AUX_CAL(NC)

RS880

*BLM18PG181SN1D(180,1.5A)_6

RX780 -->NC / RS780 --- ADD
+3V

L28
*BLM18PG181SN1D(180,1.5A)_6

AVDD-DAC Analog
not applicable to RX780

+3V_AVDD_NB

+1.1V_PLLVDD

+1.1V

L65
C762
0_6

C278
0_6

+1.8V

PLLVDD - Graphics PLL
not applicable to
RX780

*BLM18PG181SN1D(180,1.5A)_6
+1.8V_VDDLTP18_NB
L66
C761
0_6

+1.8V
B

Enables Debug Bus acess
through memory T/O pads and GPIO.
0 : Enable RS780 , Default
1 : Disable RS780
(RS780 use VSYNC#)

RS780
VSYNC_INT

R107

3K_4

+1.8V
+1.8V_PLLVDD18

R84

*0_6

+1.8V_AVDDDI_NB

3K_4

R121

*3K_4

L68

0_4

C769
0_6

*BLM18PG181SN1D(180,1.5A)_6
+1.8V_AVDDQ_NB

PLLVDD18 - Graphics PLL
not applicable to RX780

RS780
R122

C275
0_6

+1.8V_VDDLT_18_NB

AVDDI-DAC Digital
not applicable to RX780

C271

HSYNC_INT

B

*BLM21PG221SN1D(220,100M,2A)_8
L26
*BLM18PG181SN1D(180,1.5A)_6

+3V

C316
10U/6.3V_8

Indicates if memory Side port
is available or not
0: available RS780 , Default
1: Not available RS780
( RS780 use HSYNC#)

VDDLTP18 - LVDS or DVI/HDMI PLL
not applicable to RX780

VDDLT18 - LVDS or
DVI/HDMI digital
not applicable to
*0.1U/10V_4 RX780

C758

AVDDQ-DAC Bandgap Reference
not applicable to RX780

L27
C279
0_6

+3V

+1.8V

VDDA18PCIEPLL -PCIE PLL

For extrnal EEPROM Debug only

RS780/RX780
STRP_DATA

R447

L25

20mils width
+1.8V_VDDA18PCIEPLL

BLM18PG181SN1D(180,1.5A)_6

2K/F_4

C282
2.2U/6.3V_6

MV change:

3,12 CPU_LDT_STOP#

R154

*0_4/S

NB_LDT_STOP#
SI Remove for AMD request

VDDA18HTPLL -HT LINK PLL

A

L24

A

20mils width
+1.8V_VDDA18HTPLL

BLM18PG181SN1D(180,1.5A)_6
C288
2.2U/6.3V_6
3 CPU_LDT_REQ#

R159

0_4

PROJECT : OP8
Quanta Computer Inc.

NB_ALLOW_LDTSTOP

Size
Custom

12 ALLOW_LDTSTOP
NB5/RD2

Document Number

5

4

3

2

Rev
1A

RS740/RS780-SYSTEM I/F 3/5

Date: Friday, March 20, 2009

Sheet
1

10

of

42

PART 6/6

VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34

+1.1V 2A for RS880M
0.6A

VDDHTRX - HT
LINK RX I/O for
RX780/RS780

0.45A

+1.1V_VDDHT

0.5A

L13
*0_8/S

C693
4.7U/6.3V_6

C224
0.1U/10V_4

C265
0.1U/10V_4

C770
4.7U/6.3V_6

C272
0.1U/10V_4

C763
0.1U/10V_4

L64
*0_8/S

C238
0.1U/10V_4

+1.1V_VDDHTRX

+1.2V 2A for RS780M+SB700
C80
4.7U/6.3V_6

B

C152
0.1U/10V_4

C139
0.1U/10V_4

C759
0.1U/10V_4

+1.2V_VDDHTTX
C195
0.1U/10V_4

C151
0.1U/10V_4

+1.8V 1A for RS780M+SB700
+1.8V

11

PIN NAME

RX780

RS780

PIN NAME

RX780

VDDHT

+1.1V

+1.1V

IOPLLVDD

NC

+1.1V

VDDHTRX

+1.1V

+1.1V

AVDD

NC

+3.3V

RS780

VDDHTTX

+1.2V

+1.2V

AVDDDI

NC

+1.8V

VDDA18PCIE

+1.8V

+1.8V

AVDDQ

NC

+1.8V

VDDG18

+1.8V

+1.8V

PLLVDD

NC

+1.1V

VDD18_MEM

NC

+1.8V

PLLVDD18

NC

+1.8V

VDDPCIE

+1.1V

+1.1V

VDDA18PCIEPLL

+1.8V

+1.8V

VDDC

+1.1V

VDD_MEM

NC

+1.8V/1.5V

+1.1V

VDDA18HTPLL

+1.8V

+1.8V

VDDLTP18

NC

+1.8V

VDDG33

NC

IOPLLVDD18

NC

+3.3V

VDDLT18

NC

+1.8V

+1.8V

VDDLT33

NC

NC

D

600mA

L17

+1.8V_VDDA18PCIE

BLM21PG221SN1D(220,100M,2A)_8
C141
4.7U/6.3V_6

VDDA18PCIE PCIE TX stage
I/O for
RX780/RS780

VDD18 - RS780 I/O
transform

+1.8V

C126
4.7U/6.3V_6

R110

C209
0.1U/10V_4

*0_6/S

C166
0.1U/10V_4

R395

*0_6/S

VDD18_MEM For UMA RS780 only
Not applicable to RX780
memory I/O transform

C257
0.1U/10V_4

C188
0.1U/10V_4

0.005A
C267
1U/10V_4

+1.8V

VDDPCIE - PCIE-E Main power

U25E

L58
*0_8/S

VDDHTTX - HT
LINK TX I/O for
RX780/RS780
+1.2V

1

+1.1V

0.005A
C692
1U/10V_4

+1.8V_VDDG18_NB
+1.8V_VDD18_MEM

J17
K16
L16
M16
P16
R16
T16

VDDHT_1
VDDHT_2
VDDHT_3
VDDHT_4
VDDHT_5
VDDHT_6
VDDHT_7

H18
G19
F20
E21
D22
B23
A23

VDDHTRX_1
VDDHTRX_2
VDDHTRX_3
VDDHTRX_4
VDDHTRX_5
VDDHTRX_6
VDDHTRX_7

AE25
AD24
AC23
AB22
AA21
Y20
W 19
V18
U17
T17
R17
P17
M17
J10
P10
K10
M10
L10
W9
H9
T10
R10
Y9
AA9
AB9
AD9
AE9
U10
F9
G9
AE11
AD11

PART 5/6

VDDHTTX_1
VDDHTTX_2
VDDHTTX_3
VDDHTTX_4
VDDHTTX_5
VDDHTTX_6
VDDHTTX_7
VDDHTTX_8
VDDHTTX_9
VDDHTTX_10
VDDHTTX_11
VDDHTTX_12
VDDHTTX_13

POWER

VDDHT - HT
LINK digital
I/O for
RX780/RS780

C

L12
M14
N13
P12
P15
R11
R14
T12
U14
U11
U15
V12
W11
W15
AC12
AA14
Y18
AB11
AB15
AB17
AB19
AE20
AB21
K11

A25
D23
E22
G22
G24
G25
H19
J22
L17
L22
L24
L25
M20
N22
P20
R19
R22
R24
R25
H20
U22
V19
W22
W24
W25
Y21
AD25

VSSAHT1
VSSAHT2
VSSAHT3
VSSAHT4
VSSAHT5
VSSAHT6
VSSAHT7
VSSAHT8
VSSAHT9
VSSAHT10
VSSAHT11
VSSAHT12
VSSAHT13
VSSAHT14
VSSAHT15
VSSAHT16
VSSAHT17
VSSAHT18
VSSAHT19
VSSAHT20
VSSAHT21
VSSAHT22
VSSAHT23
VSSAHT24
VSSAHT25
VSSAHT26
VSSAHT27

GROUND

D

2

RX780/RS780 POWER DIFFERENCE TABLE

VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10

VSSAPCIE1
VSSAPCIE2
VSSAPCIE3
VSSAPCIE4
VSSAPCIE5
VSSAPCIE6
VSSAPCIE7
VSSAPCIE8
VSSAPCIE9
VSSAPCIE10
VSSAPCIE11
VSSAPCIE12
VSSAPCIE13
VSSAPCIE14
VSSAPCIE15
VSSAPCIE16
VSSAPCIE17
VSSAPCIE18
VSSAPCIE19
VSSAPCIE20
VSSAPCIE21
VSSAPCIE22
VSSAPCIE23
VSSAPCIE24
VSSAPCIE25
VSSAPCIE26
VSSAPCIE27
VSSAPCIE28
VSSAPCIE29
VSSAPCIE30
VSSAPCIE31
VSSAPCIE32
VSSAPCIE33
VSSAPCIE34
VSSAPCIE35
VSSAPCIE36
VSSAPCIE37
VSSAPCIE38
VSSAPCIE39
VSSAPCIE40

U25F

3

AE14
D11
G8
E14
E15
J15
J12
K14
M11
L15

4

A2
B1
D3
D5
E4
G1
G2
G4
H7
J4
R7
L1
L2
L4
L7
M6
N4
P6
R1
R2
R4
V7
U4
V8
V6
W1
W2
W4
W7
W8
Y6
AA4
AB5
AB1
AB7
AC3
AC4
AE1
AE4
AB2

5

VDDA18PCIE_1
VDDA18PCIE_2
VDDA18PCIE_3
VDDA18PCIE_4
VDDA18PCIE_5
VDDA18PCIE_6
VDDA18PCIE_7
VDDA18PCIE_8
VDDA18PCIE_9
VDDA18PCIE_10
VDDA18PCIE_11
VDDA18PCIE_12
VDDA18PCIE_13
VDDA18PCIE_14
VDDA18PCIE_15

VDDPCIE_1
VDDPCIE_2
VDDPCIE_3
VDDPCIE_4
VDDPCIE_5
VDDPCIE_6
VDDPCIE_7
VDDPCIE_8
VDDPCIE_9
VDDPCIE_10
VDDPCIE_11
VDDPCIE_12
VDDPCIE_13
VDDPCIE_14
VDDPCIE_15
VDDPCIE_16
VDDPCIE_17
VDDC_1
VDDC_2
VDDC_3
VDDC_4
VDDC_5
VDDC_6
VDDC_7
VDDC_8
VDDC_9
VDDC_10
VDDC_11
VDDC_12
VDDC_13
VDDC_14
VDDC_15
VDDC_16
VDDC_17
VDDC_18
VDDC_19
VDDC_20
VDDC_21
VDDC_22
VDD_MEM1(NC)
VDD_MEM2(NC)
VDD_MEM3(NC)
VDD_MEM4(NC)
VDD_MEM5(NC)
VDD_MEM6(NC)

VDDG18_1(VDD18_1)
VDDG18_2(VDD18_2)
VDD18_MEM1(NC)
VDD18_MEM2(NC)

VDDG33_1(NC)
VDDG33_2(NC)

RS880

A6
B6
C6
D6
E6
F6
G7
H8
J9
K9
M9
L9
P9
R9
T9
V9
U9
K12
J14
U16
J11
K15
M12
L14
L11
M13
M15
N12
N14
P11
P13
P14
R12
R15
T11
T15
U12
T14
J16

0.7A

+1.1V_VDD_PCIE
C226
0.1U/10V_4

C277
0.1U/10V_4

C268
1U/10V_4

C273
1U/10V_4

R99

*0_8/S

C

+1.1V

C281
4.7U/6.3V_6

VDDC - Core Logic power

7A

+1.1V_DYN
C203
0.1U/10V_4

C250
0.1U/10V_4

C252
0.1U/10V_4

C258
0.1U/10V_4

C29
10U/6.3V_8

B

C239
0.1U/10V_4

C232
0.1U/10V_4

C202
0.1U/10V_4

C30
10U/6.3V_8

VDD_MEM For UMA RS780 only
Not applicable to RX780
memory I/O transform

BLM21PG221SN1D(220,100M,2A)_8

AE10
AA11
Y11
AD10
AB10
AC10

+1.8V_VDD_MEM

H11
H12

+3V_VDDG33

C149
0.1U/10V_4

C276
0.1U/10V_4

1.8V(0.15A)

C128
0.1U/10V_4

C127
1U/10V_4

C168
1U/10V_4
RS780
*0_6/S

R111
C274
0.1U/10V_4

L18

+1.8V

C138
10U/6.3V_8

3.3V(0.03A)
+3V

VDD33 - 3.3V I/O
Not applicable to RX780

A

A

PROJECT : OP8
Quanta Computer Inc.
Size
Custom
NB5/RD2

Document Number

Date: Friday, March 20, 2009
5

4

3

2

Rev
1A

RS740/RS780-POWER5/5
Sheet
1

11

of

42

5

9
9
9
9
9
9
9
9

0.1U/10V_4
0.1U/10V_4
0.1U/10V_4
0.1U/10V_4
0.1U/10V_4
0.1U/10V_4
0.1U/10V_4
0.1U/10V_4

L37

A_RX0P_C
A_RX0N_C
A_RX1P_C
A_RX1N_C
A_RX2P_C
A_RX2N_C
A_RX3P_C
A_RX3N_C

PCIE_NB_SB_TX0P
PCIE_NB_SB_TX0N
PCIE_NB_SB_TX1P
PCIE_NB_SB_TX1N
PCIE_NB_SB_TX2P
PCIE_NB_SB_TX2N
PCIE_NB_SB_TX3P
PCIE_NB_SB_TX3N

PCIE_NB_SB_TX0P
PCIE_NB_SB_TX0N
PCIE_NB_SB_TX1P
PCIE_NB_SB_TX1N
PCIE_NB_SB_TX2P
PCIE_NB_SB_TX2N
PCIE_NB_SB_TX3P
PCIE_NB_SB_TX3N
R476
R477

+1.2V_PCIE_VDDR
+1.2V

C807
C806
C800
C799
C809
C808
C802
C801

PCIE_SB_NB_RX0P
PCIE_SB_NB_RX0N
PCIE_SB_NB_RX1P
PCIE_SB_NB_RX1N
PCIE_SB_NB_RX2P
PCIE_SB_NB_RX2N
PCIE_SB_NB_RX3P
PCIE_SB_NB_RX3N

U31A
A_RST#_SB

562/F_4
2.05K/F_4

BLM18PG181SN1D(180,1.5A)_6

PCIE_CALRP_SB
PCIE_CALRN_SB
+1.2V_PCIE_PVDD

40mA

PCIE_PVDD-- PCIE PLL POWER

C439
10U/6.3V_8

N2

SB710
A_RST#

V23
V22
V24
V25
U25
U24
T23
T22

PCIE_TX0P
PCIE_TX0N
PCIE_TX1P
PCIE_TX1N
PCIE_TX2P
PCIE_TX2N
PCIE_TX3P
PCIE_TX3N

U22
U21
U19
V19
R20
R21
R18
R17

PCIE_RX0P
PCIE_RX0N
PCIE_RX1P
PCIE_RX1N
PCIE_RX2P
PCIE_RX2N
PCIE_RX3P
PCIE_RX3N

T25
T24

PCIE_CALRP
PCIE_CALRN

P24

PCIE_PVDD

P25

PCIE_PVSS

C467
1U/10V_4

Part 1 of 5

NB_HT_CLKP
NB_HT_CLKN

RTC_X2

P17
M18

CPU_HT_CLKP
CPU_HT_CLKN

32.768KHZ
20M_6

M23
M22

SLT_GFX_CLKP
SLT_GFX_CLKN

C569
18P/50V_4

C579
18P/50V_4

Change for SB710 chip

FOR A14 chip

B

EXT_SB_OSC
T125

T35

RTC_X1

RTC_X2

+3VS5
10 ALLOW_LDTSTOP
3 CPU_PROCHOT#
3
CPU_PWRGD
3,10 CPU_LDT_STOP#
3,10 CPU_LDT_RST#

A

R201

J19
J18

GPP_CLK0P
GPP_CLK0N

L20
L19

GPP_CLK1P
GPP_CLK1N

M19
M20

GPP_CLK2P
GPP_CLK2N

N22
P22

GPP_CLK3P
GPP_CLK3N

L18

25M_48M_66M_OSC

J21

25M_X1

J20

A3

B3

25M_X2

X1

X2

10K/F_4
ALLOW_LDTSTOP
CPU_PROCHOT#
CPU_PWRGD
CPU_LDT_STOP#
CPU_LDT_RST#

F23
F24
F22
G25
G24

ALLOW _LDTSTP
PROCHOT#
LDT_PG
LDT_STP#
LDT_RST#

PCIRST#

N1

PCIRST#_L

T53
T111
PCI_CLK_TPM 16
PCI_CLK3 16
PCI_CLK4 16
PCI_CLK5 16

R486

33_4

INTE#/GPIO33
INTF#/GPIO34
INTG#/GPIO35
INTH#/GPIO36

AD3
AC4
AE2
AE3

INTE#
INTF#
INTG#
INTH#

LPCCLK0
LPCCLK1
LAD0
LAD1
LAD2
LAD3
LFRAME#
LDRQ0#
LDRQ1#/GNT5#/GPIO68
BMREQ#/REQ5#/GPIO65
SERIRQ

G22
E22
H24
H23
J25
J24
H25
H22
AB8
AD7
V15

LPC_CLK0
LPC_CLK1
LAD0
LAD1
LAD2
LAD3
LFRAME#
LDRQ0#_SB
LDRQ1#_SB
SB_GPIO65
SERIRQ

C3
C2
B2

RTC_CLK
INTRUDER_ALERT#
+AVBAT

RTCCLK
INTRUDER_ALERT#
VBAT

PCIRST#

PCIRST# 32

+3V
PE_GPIO1

R313

8.2K_4

R328

*8.2K_4

SB_GPIO65

R284

*100K/F_4

R297

10K/F_4

+3V

C

AD23
AD24
AD25
AD26
AD27
AD28

AD23
AD24
AD25
AD26
AD27
AD28

16
16
16
16
16
16
D29
RB500V-40

+AVBAT

All the PCI bus has
build-in Pull-UP/Down
resistors

+3VPCU

20MIL R510

499/F_4

+3VRTC_1

R512

20MIL

10_4 +3VRTC

20MIL

D28
RB500V-40

C834
1U/10V_4
SERR#

SERR#

R285

RF_OFF#

20MIL

Change from
0ohm to 1K
for safty
issue

32

*0_4/S

33

R508
1K/F_4

T45

20MIL

B

PE_GPIO1
R482
R480

CLKRUN#_R

*0_4/S
*0_4/S

LCD_BK
23
CLKRUN# 32

BT1

T42

BAT_CONN

T114
T55
T112
T59
R236
R202

LPC_CLK0 16
LPC_CLK1 16

22_4
10_4

PCLK_LPC_DEBUG
32,33
32,33
32,33
32,33
32,33

SERIRQ

32

for EMI
suggestion

C420
5.6P/50V_6

C464
22P/50V_4

T28
T39
T51

20MIL

33

PCLK_LPC_KB3920 32

LAD0
LAD1
LAD2
LAD3
LFRAME#

RTC_CLK 16

R493

*1M/F_4

+AVBAT

+AVBAT

SB710

IC CTRL(528P) SB710 A14(218-0660017)
P/N : AJ066000T01

D

G3
*SHORT_ PAD1

C826
0.1U/10V_4

INTRUDER_ALERT# Left not connected (Southbridge
has 50-kohm internal pull-up to VBAT).

A

2

R321

RTC

1

100MHZ

PCI_CLK_TPM
PCI_CLK3
PCI_CLK4
PCI_CLK5

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
CBE0#
CBE1#
CBE2#
CBE3#
FRAME#
DEVSEL#
IRDY#
TRDY#
PAR
STOP#
PERR#
SERR#
REQ0#
REQ1#
REQ2#
REQ3#/GPIO70
REQ4#/GPIO71
GNT0#
GNT1#
GNT2#
GNT3#/GPIO72
GNT4#/GPIO73
CLKRUN#
LOCK#

PCI INTERFACE

NB_DISP_CLKP
NB_DISP_CLKN

CPU

4

2

K23
K22
M24
M25

2

R305
*20M_6

PCIE_RCLKP/NB_LNK_CLKP
PCIE_RCLKN/NB_LNK_CLKN

CLOCK GENERATOR

Y5

3

N25
N24

LPC

SBSRC_CLKP
SBSRC_CLKN

SBSRC_CLKP
SBSRC_CLKN

RTC XTAL

2
2

P4
P3
P1
P2
T4
T3

U2
P7
V4
T1
V3
U1
V1
V2
T2
W1
T9
R6
R7
R5
U8
U5
Y7
W8
V9
Y8
AA8
Y4
Y3
Y2
AA2
AB4
AA1
AB3
AB2
AC1
AC2
AD1
W2
U7
AA7
Y1
AA6
W5
AA5
Y5
U6
W6
W4
V7
AC3
AD4
AB7
AE6
AB6
AD2
AE4
AD5
AC6
AE5
AD6
V5

C

RTC_X1

PCICLK0
PCICLK1
PCICLK2
PCICLK3
PCICLK4
PCICLK5/GPIO41

2+VCCRTC_2

33_4

+BAT 1

33_4

R505

12

1

R225

33 MINI_PLTRST#

1

2

30 LAN_PLTRST#

2

1

33_4
33_4

PCI CLKS

R223
R224

3

PCI EXPRESS INTERFACE

PLACE THESE
PCIE AC
COUPLING CAPS
CLOSE TO U600

10 NB_PLTRST#
17 PCIE_RST#

9
9
9
9
9
9
9
9

To RS780

D

4

PROJECT : OP8
Quanta Computer Inc.
Size
Custom
NB5/RD2

Document Number

Date: Friday, March 20, 2009
5

4

3

2

Rev
1A

SB700-PCIE/PCI/CPU/LPC 1/4
Sheet
1

12

of

42

5

+3VS5

4

3

2

1

13

NC only ,Can't be install

R319

*2.2K_4

SB_TEST0

R180

*2.2K_4

SB_TEST1

R296

*2.2K_4

SB_TEST2

U31D

2.2K_4

32
32
32
32

PDAT_SMB

Change for test point for Debug

GATEA20
RCIN#
SCI#
KBSMI#
mode T56
T124

30,33 PCIE_WAKE#

R198
R181

32
SWI#
3 CPU_THERMTRIP#
16 WD_PWRGD
C840
100P/50V_4

SCL1/SDATA1 is 3V/S5 tolerance
AMD datasheet define it
2.2K_4 SB_SMBCLK1
2.2K_4 SB_SMBDATA1

T29
T106
30,32 LAN_DISABLE#

remove pull hi
( chip internal
have pull hi )

C

2.2K_4
2.2K_4

*0_4

ACZ_SPKR
PCLK_SMB
PDAT_SMB
SB_SMBCLK1
SB_SMBDATA1

27,28 ACZ_SPKR
2,6,7,33 PCLK_SMB
2,6,7,33 PDAT_SMB
T33
T37

SB_SCLK2
SB_SDATA2

PM_BATLOW#
SES_INT
GEVENT7#

32 PM_BATLOW#
T34
T50

+3V

R290

3K_4

3,7 CPU_MEMHOT#
5 PM_THERM#
+3VS5

+3VS5
2.2K_4

DNBSWON#

R483
R339
R336
R275
R506

To Azalia
ACZ_SDOUT

R487

33_4

ACZ_SDOUT_AUDIO
C830

*10K/F_4
*10K/F_4
*10K/F_4
*10K/F_4

27
16

*10P/50V_4

ACZ_RST#

CPU_MEMHOT#
SMBALERT#_1
R264
*0_4
R276
10K/F_4
SB_JTAG_TDO
SB_JTAG_TCK
SB_JTAG_TDI
SB_JTAG_RST#
*10K/F_4
ACZ_BCLK
ACZ_SDOUT
ACZ_SDIN0
ACZ_SDIN1
ACZ_SDIN2_R
ACZ_SDIN3_R
ACZ_SYNC
ACZ_RST#

R303

33_4

ACZ_SYNC_AUDIO
C562

ACZ_BCLK

R489

33_4

R317

33_4

27

27

27

Remove short pad

Modified for EMI suggestion

To Modem Board
33_4

ACZ_SDOUT_AUDIO_MDC
C831

M1
M2
J7
J8
L8
M3
L6
M4
L5

AZ_BITCLK
AZ_SDOUT
AZ_SDIN0/GPIO42
AZ_SDIN1/GPIO43
AZ_SDIN2/GPIO44
AZ_SDIN3/GPIO46
AZ_SYNC
AZ_RST#
AZ_DOCK_RST#/GPM8#

10P/50V_4

ACZ_SDIN0

R488

USB_OC6#/IR_TX1/GEVENT6#
USB_OC5#/IR_TX0/GPM5#
USB_OC4#/IR_RX0/GPM4#
USB_OC3#/IR_RX1/GPM3#
USB_OC2#/GPM2#
USB_OC1#/GPM1#
USB_OC0#/GPM0#

27

ACZ_RST#_AUDIO

ACZ_SDIN0

ACZ_SDOUT

F7
E8

USB_FDS12P
USB_FSD12N

USB_HSD11P
USB_HSD11N

H11
J10

USB_HSD10P
USB_HSD10N

E11
F11

USBP10+
USBP10-

33
33

WLAN Min-Card

USB_HSD9P
USB_HSD9N

A11
B11

USBP9+
USBP9-

29
29

BLUETOOTH

USB_HSD8P
USB_HSD8N

C10
D10

USBP8+
USBP8-

29
29

USB Connector

USB_HSD7P
USB_HSD7N

G11
H12

USB_HSD6P
USB_HSD6N

E12
E14

USB_HSD5P
USB_HSD5N

C12
D12

USB_HSD4P
USB_HSD4N

B12
A12

USB_HSD3P
USB_HSD3N

USB MISC

USB_FSD12P
USB_FSD12N

SATA_IS0#/GPIO10
CLK_REQ3#/SATA_IS1#/GPIO6
SMARTVOLT/SATA_IS2#/GPIO4
CLK_REQ0#/SATA_IS3#/GPIO0
CLK_REQ1#/SATA_IS4#/FANOUT3/GPIO39
CLK_REQ2#/SATA_IS5#/FANIN3/GPIO40
SPKR/GPIO2
SCL0/GPOC0#
SDA0/GPOC1#
SCL1/GPOC2#
SDA1/GPOC3#
DDC1_SCL/GPIO9
DDC1_SDA/GPIO8
LLB#/GPIO66
SHUTDOW N#/GPIO5
DDR3_RST#/GEVENT7#

*10P/50V_4

BIT_CLK_AUDIO
C832

ACZ_RST#

E6
E7

H19
H20
H21
F25

IMC_GPIO0
IMC_GPIO1
SPI_CS2#/IMC_GPIO2
IDE_RST#/F_RST#/IMC_GPO3

D22
E24
E25
D23

IMC_GPIO4
IMC_GPIO5
IMC_GPIO6
IMC_GPIO7

28

CLK_48M_USB 2
R263

CLK_48M_USB

11.8K/F_6

for EMI

RSMRST#

B9
B8
A8
A9
E5
F8
E4

HD audio
interface is
3.3S5 voltage

B

ACZ_SYNC

AE18
AD18
AA19
W 17
V17
W 20
W 21
AA18
W 18
K1
K2
AA20
Y18
C1
Y19
G5

USB_FSD13P
USB_FSD13N

USB_FSD13P
USB_FSD13N

SUS_STAT#

Change from AMD request
R288

SATA_IS1
LAN_DISABLE#_SB
SB_NWD_CLK_REQ#

T36

SCL2/SDATA2 is 3V/S5 tolerance
AMD datasheet define it
R204
R205

R230

D3

USB_RCOMP_SB

INTEGRATED uC

+3VS5

RSMRST#

RSMRST#

CLK_48M_USB

G8

USB OC

R492
R494

32

INTEGRATED uC

+3VS5

0_4
SWI#_L
*0_4/S SB_THERMTRIP#
WD_PWRGD

C8

USB_RCOMP

USB 1.1

2.2K_4 PCLK_SMB

R241

USBCLK/14M_25M_48M_OSC

D

C516
*2.2P/50V_4

T54
T57
T38
T40

Si Change USB port reference Raven 2.0 design

USBP5+
USBP5-

29
29

G12
G14

USBP3+
USBP3-

26
26

USB

USB_HSD2P
USB_HSD2N

H14
H15

USBP2+
USBP2-

23
23

Carama USB

USB_HSD1P
USB_HSD1N

A13
B13

USBP1+
USBP1-

29
29

E-SATA and USB Connector

USB_HSD0P
USB_HSD0N

B14
A14

IMC_GPIO8
IMC_GPIO9
IMC_PW M0/IMC_GPIO10
SCL2/IMC_GPIO11
SDA2/IMC_GPIO12
SCL3_LV/IMC_GPIO13
SDA3_LV/IMC_GPIO14
IMC_PW M1/IMC_GPIO15
IMC_PW M2/IMC_GPO16
IMC_PW M3/IMC_GPO17

A18
B18
F21
D21
F19
E20
E21
E19
D19
E18

IMC_GPIO18
IMC_GPIO19
IMC_GPIO20
IMC_GPIO21
IMC_GPIO22
IMC_GPIO23
IMC_GPIO24
IMC_GPIO25

G20
G21
D25
D24
C25
C24
B25
C23

IMC_GPIO26
IMC_GPIO27
IMC_GPIO28
IMC_GPIO29
IMC_GPIO30
IMC_GPIO31
IMC_GPIO32
IMC_GPIO33
IMC_GPIO34
IMC_GPIO35
IMC_GPIO36
IMC_GPIO37
IMC_GPIO38
IMC_GPIO39
IMC_GPIO40
IMC_GPIO41

B24
B23
A23
C22
A22
B22
B21
A21
D20
C20
A20
B20
B19
A19
D18
C18

USB 2.0

R238

PCI_PME#/GEVENT4#
RI#/EXTEVNT0#
SLP_S2/GPM9#
SLP_S3#
SLP_S5#
PW R_BTN#
PW R_GOOD
SUS_STAT#
TEST2
TEST1
TEST0
GA20IN/GEVENT0#
KBRST#/GEVENT1#
LPC_PME#/GEVENT3#
LPC_SMI#/EXTEVNT1#
S3_STATE/GEVENT5#
SYS_RESET#/GPM7#
W AKE#/GEVENT8#
BLINK/GPM6#
SMBALERT#/THRMTRIP#/GEVENT2#
NB_PW RGD

GPIO

Clock gen/Robson/TV
tuner
/DDR2/DDR2
thermal/Accelerometer

is 3V tolerance
AMD datasheet define it

E1
E2
H7
F5
G1
H2
H1
K3
H5
H4
H3
Y15
W 15
K4
K24
F1
J2
H6
F2
J6
W 14

ACPI / WAKE UP EVENTS

+3V SCL0/SDATA0

RI#
SLP_S2
SUSB#
SUSC#
DNBSWON#
SB_PWRGD_IN
SUS_STAT#
SB_TEST2
SB_TEST1
SB_TEST0
GATEA20
RCIN#
SCI#
KBSMI#
GEVENT5#
SYS_RST#

T113
T43
32
SUSB#
32
SUSC#
32
DNBSWON#
16 SB_PWRGD_IN
10
SUS_STAT#

Part 4 of 5

SB710

HD AUDIO

D

Check BIOS for no connetcor pin for the power

USB Connector
C

SB_SCLK2
SB_SDATA2
SB_SCLK3
5158_RST_R#
SB_GPIO16
SB_GPIO17

card reader

T32
5158_RST_R# 26
SB_GPIO16 16
SB_GPIO17 16

SPI/LPC define

B

*10P/50V_4
SB710

ACZ_SYNC

R320

33_4

ACZ_BCLK

R490

33_4

ACZ_RST#

R312

33_4

ACZ_SYNC_AUDIO_MDC
C580

28

+3VSUS

*10P/50V_4

BIT_CLK_AUDIO_MDC
C833

ACZ_SDIN1

28

10P/50V_4

SB JTAG

ACZ_RST#_AUDIO_MDC

ACZ_SDIN1

C393
10P/50V_4

CN11

A

28

1
2
3
4
5
6
7
8

A

SB_JTAG_TCK
SB_JTAG_TDO
SB_JTAG_TDI
SB_TEST1

PROJECT : OP8
Quanta Computer Inc.

SB_JTAG_RST#

*S/W JTAG DEBUG

28

Size
Custom
NB5/RD2

Remove short pad
5

Document Number

Date: Friday, March 20, 2009
4

3

2

Rev
1A

SB700-ACPI/GPIO/USB 2/4
Sheet
1

13

of

42

5

4

E-SATA

SATA_TXP0_C
SATA_TXN0_C

AD9
AE9

SATA_TX0P
SATA_TX0N

C554
C553

0.01U/16V_4
0.01U/16V_4

SATA_RXN0_C
SATA_RXP0_C

AB10
AC10

SATA_RX0N
SATA_RX0P

C533
C529

0.01U/16V_4
0.01U/16V_4

SATA_TXP1_C
SATA_TXN1_C

AE10
AD10

SATA_TX1P
SATA_TX1N

C515
C521

0.01U/16V_4
0.01U/16V_4

SATA_RXN1_C
SATA_RXP1_C

AD11
AE11

SATA_RX1N
SATA_RX1P

29
29

SATA_RXN0
SATA_RXP0

29
29

SATA_TXP1
SATA_TXN1

29
29

SATA_RXN1
SATA_RXP1

29
29

SATA_TXP2
SATA_TXN2

AB12
AC12

SATA_TX2P
SATA_TX2N

29
29

SATA_RXN2
SATA_RXP2

AE12
AD12

SATA_RX2N
SATA_RX2P

AD13
AE13

SATA_TX3P
SATA_TX3N

AB14
AC14

SATA_RX3N
SATA_RX3P

AE14
AD14

SATA_TX4P
SATA_TX4N

AD15
AE15

SATA_RX4N
SATA_RX4P

AB16
AC16

SATA_TX5P
SATA_TX5N

AE16
AD16

R361
R256

1K/F_4

SATA_RBIAS_PN
SATA_X1

PLACE SATA_CAL
RES VERY CLOSE
TO BALL OF SB700

NOTE:

SATA_X2

PLVDD_SATA-SATA PLL
POWER

R361 IS 1K 1% FOR 25MHz
XTAL, 4.99K 1% FOR 100MHz
INTERNAL CLOCK

+3V

R257

SATA_CAL

Y12

SATA_X1

AA12

SB_SATA_LED#

SATA_RX5N
SATA_RX5P

V12

W 11

+3V_XTLVDD_SATA

AA11

PLLVDD_SATA

W 12

XTLVDD_SATA

C501

2

SATA_X1
Y4

IDE_D0/GPIO15
IDE_D1/GPIO16
IDE_D2/GPIO17
IDE_D3/GPIO18
IDE_D4/GPIO19
IDE_D5/GPIO20
IDE_D6/GPIO21
IDE_D7/GPIO22
IDE_D8/GPIO23
IDE_D9/GPIO24
IDE_D10/GPIO25
IDE_D11/GPIO26
IDE_D12/GPIO27
IDE_D13/GPIO28
IDE_D14/GPIO29
IDE_D15/GPIO30

AD24
AD23
AE22
AC22
AD21
AE20
AB20
AD19
AE19
AC20
AD20
AE21
AB22
AD22
AE23
AC23

T92
T96
T93
T94
T101
T98
T97
T105
T102
T104
T103
T100
T30
T99
T27
T95

SPI_DI/GPIO12
SPI_DO/GPIO11
SPI_CLK/GPIO47
SPI_HOLD#/GPIO31
SPI_CS#/GPIO32

G6
D2
D1
F4
F3

LAN_RST#/GPIO13
ROM_RST#/GPIO14

U15
J1

R246
10M_6

IF THERE IS NO IDE, TEST
POINTS FOR DEBUG BUS
IS MANDATORY
SIDE_PORT_ID1

*0_4/S

Samsung

0

1

Qimonda

1

0

Hynix

1

1

no supprot side port

T115

+3VS5

T41
T48
T47

+3VS5

R287

SB_FANTACH0
SB_FANTACH1
PORT_80_PWR_DWN

TEMP_COMM
TEMPIN0/GPIO61
TEMPIN1/GPIO62
TEMPIN2/GPIO63
TEMPIN3/TALERT#/GPIO64

C6
B6
A6
A5
B5

TEMP_COMM
TEMPIN0
TEMPIN1
MB_THRMDA_SB

VIN0/GPIO53
VIN1/GPIO54
VIN2/GPIO55
VIN3/GPIO56
VIN4/GPIO57
VIN5/GPIO58
VIN6/GPIO59
VIN7/GPIO60

A4
B4
C4
D4
D5
D6
A7
B7

AVDD

F6

AVSS

G7

SIDE_PORT_ID0

R527

*10K/F_4

10K/F_4

SIDE_PORT_ID1

R294

*10K/F_4

T52
T46
T49

R267

*0_4/S
+3VS5

T108
T107
T109
T110

R286
SIDE_PORT_ID0
SIDE_PORT_ID1
BOARD_ID0
BOARD_ID1
BOARD_ID2
BOARD_ID3

10K/F_4

*0_4

BT_COMBO_EN# 33

R272

*10K/F_4

BOARD_ID0

R271

10K/F_4

R261

10K/F_4

BOARD_ID1

R251

*10K/F_4

R277

*10K/F_4

BOARD_ID2

R265

10K/F_4

R278

*10K/F_4

BOARD_ID3

R266

10K/F_4

+3VS5

SB710

+3V

5mA

+3V_VDD_HWM
C566
*0.1U/10V_4

L47

B

*0_6/S

C561
*2.2U/6.3V_6

AVDD--H/W monitor
Analog power
ID3

ID1

ID0

0

ID2
0

0

0

OP8 UMA

0

0

0

1

OP9 UMA

0

0

1

0

OP8 Dis

0

0

1

1

OP9 Dis

0

1

0

0

0

1

0

1

0

1

1

0

0

1

1

1

Add for design

C500
0.1U/10V_4

+1.2V

( 1.2V @ 60mA)

+1.2V_PLLVDD_SATA

77mA

5

L42

2

SB_SATA_LED#

BLM21PG221SN1D(220,100M,2A)_8
C495
1U/10V_4

4

SATA_LED#

0

BT_OFF# 29

27P/50V_4

1

C520
0.1U/10V_4

C510
22U/6.3V_8

C509
22U/6.3V_8

3

27

0

R526

P5
P8
R8

B

U12
TC7SH08FU

SIDE_PORT_ID0

C

R258
ROM_RST#

FANIN0/GPIO50
FANIN1/GPIO51
FANIN2/GPIO52

SATA_X2

D

T44
T116
T118
T58
T117

SB_FANOUT0
SB_FANOUT1

1

25MHZ
C487

T86
T84
T31
T87
T82
T85
T88
T90
T89
T91
T83

M8
M5
M7

SATA_ACT#/GPIO67

XTLVDD_SATA-- SATA
crystal power

27P/50V_4

AA24
AA25
Y22
AB23
Y23
AB24
AD25
AC25
AC24
Y25
Y24

FANOUT0/GPIO3
FANOUT1/GPIO48
FANOUT2/GPIO49

10K/F_4

+1.2V_PLLVDD_SATA

IDE_IORDY
IDE_IRQ
IDE_A0
IDE_A1
IDE_A2
IDE_DACK#
IDE_DRQ
IDE_IOR#
IDE_IOW #
IDE_CS1#
IDE_CS3#

SATA_X2

HW MONITOR

C

Part 2 of 5

ATA 66/100/133

SATA ODD

SATA_TXP0
SATA_TXN0

1

14
SB710

0.01U/16V_4
0.01U/16V_4

SPI ROM

D

29
29

2

U31B

C540
C539

SERIAL ATA

SATA1

PLACE SATA AC COUPLING
CAPS CLOSE TO SB600

SATA PWR

SATA PORT 0,1,2,3
can support AHCI
mode

3

1mA

+3V

( 3.3V @ 1.2mA)

+3V_XTLVDD_SATA

L41
BLM18PG181SN1D(180,1.5A)_6
C504
1U/10V_4
A

A

Place near
ball

PROJECT : OP8
Quanta Computer Inc.
Size
Custom
NB5/RD2

Document Number

Date: Friday, March 20, 2009
5

4

3

2

Rev
1A

SB700-ACPI/GPIO/USB 2/4
Sheet
1

14

of

42

5

4

3

2

1

PLACE ALL THE DECOUPLING CAPS ON
THIS SHEET CLOSE TO SB AS POSSIBLE.

15

VDD-- S/B CORE power
+1.2V_VCC_SB_R

1
2

1
2

1

1

*0_6/S

+1.2V

1

1

C433
*2.2U/6.3V_6

2

1

1
*0.1U/50V_6

*0_6/S

2

2

C563
C461
0.1U/10V_4 2.2U/6.3V_6

2

C455
0.1U/10V_4

1

1

1

1

+3VS5
Change to 0603
C448
10U/6.3V_8

AMD : Change from 1u to 0.1u

S5_1.2V--1.2V standby power
S5_1.2V_1
S5_1.2V_2

USB_PHY_1.2V_1
USB_PHY_1.2V_2

0.22A

G2
G4

A10
B10

+1.2V_S5

0.2A

C827
1U/10V_4

C825
1U/10V_4

+1.2V_USB_PHY_R
AMD : Change from 1u to 0.1u

+3V_AVDD_USB

1

A15
B15
C14
D8
D9
D11
D13
D14
D15
E15
F12
F14
G9
H9
H17
J9
J11
J12
J14
J15
K10
K12
K14
K15

AVSS_USB_1
AVSS_USB_2
AVSS_USB_3
AVSS_USB_4
AVSS_USB_5
AVSS_USB_6
AVSS_USB_7
AVSS_USB_8
AVSS_USB_9
AVSS_USB_10
AVSS_USB_11
AVSS_USB_12
AVSS_USB_13
AVSS_USB_14
AVSS_USB_15
AVSS_USB_16
AVSS_USB_17
AVSS_USB_18
AVSS_USB_19
AVSS_USB_20
AVSS_USB_21
AVSS_USB_22
AVSS_USB_23
AVSS_USB_24

+5V_VREF

AE7
J16

+3V_AVDDCK

7mA

AVDDCK_1.2V

K17

+1.2V_AVDDCK

44mA

R479

AVDDC

E9

+3V_AVDDC

2 1K/F_4

1
1
D27

1

V5_VREF
AVDDCK_3.3V

C823
1U/10V_4

2

+5V

H18
J17
J22
K25
M16
M17
M21
P16

+3V

CH501H-40PT

16mA

F9

PCIE_CK_VSS_1
PCIE_CK_VSS_2
PCIE_CK_VSS_3
PCIE_CK_VSS_4
PCIE_CK_VSS_5
PCIE_CK_VSS_6
PCIE_CK_VSS_7
PCIE_CK_VSS_8
AVSSC

SB710

PCIE_CK_VSS_9
PCIE_CK_VSS_10
PCIE_CK_VSS_11
PCIE_CK_VSS_12
PCIE_CK_VSS_13
PCIE_CK_VSS_14
PCIE_CK_VSS_15
PCIE_CK_VSS_16
PCIE_CK_VSS_17
PCIE_CK_VSS_18
PCIE_CK_VSS_19
PCIE_CK_VSS_20
PCIE_CK_VSS_21
AVSSCK

Part 5 of 5

A2
A25
B1
D7
F20
G19
H8
K9
K11
K16
L4
L7
L10
L11
L12
L14
L16
M6
M10
M11
M13
M15
N4
N12
N14
P6
P9
P10
P11
P13
P15
R1
R2
R4
R9
R10
R12
R14
T11
T12
T14
U4
U14
V6
Y21
AB1
AB19
AB25
AE1
AE24

D

C

P23
R16
R19
T17
U18
U20
V18
V20
V21
W 19
W 22
W 24
W 25

B

L17

SB710

C502
0.1U/10V_4

+3VS5

+3V_AVDDC

+1.2V_USB_PHY_R

1

C505
0.1U/10V_4

1
C496
10U/6.3V_8

2

1
C499
10U/6.3V_8

2

C508
0.1U/10V_4

2

C507
0.1U/10V_4

AVDDC--USB Analog PLL power

USB_PHY_1.2V--USB Phy
digital power

1

*0_6/S

1

R262

L44
BLM18PG181SN1D(180,1.5A)_6

2

+1.2V_S5

2

C478
0.1U/10V_4

2

1
C476
0.1U/10V_4

2

1
C477
0.1U/10V_4

2

1
2

1
C811
1U/10V_4

2

1
C503
1U/10V_4

2

+1.2V

A

+1.2V_AVDDCK

1
C480
2.2U/6.3V_6

L43
BLM18PG181SN1D(180,1.5A)_6

A

+3V_AVDDCK

AVDDCK_3.3--Analog
system PLL power

2

2

L39
BLM18PG181SN1D(180,1.5A)_6

+3V

AVDDCK_1.2--USB Phy
digital power

1

C482
1U/10V_4

2

1

B

4mA

2

C483
0.1U/10V_4

AVDDTX_0
AVDDTX_1
AVDDTX_2
AVDDTX_3
AVDDTX_4
AVDDTX_5
AVDDRX_0
AVDDRX_1
AVDDRX_2
AVDDRX_3
AVDDRX_4
AVDDRX_5

PLL

A16
B16
C16
D16
D17
E17
F15
F17
F18
G15
G17
G18

1
C814
0.1U/10V_4

2

1
C484
10U/6.3V_8

2

1

1
2

C493
10U/6.3V_8

AVSS_SATA_1
AVSS_SATA_2
AVSS_SATA_3
AVSS_SATA_4
AVSS_SATA_5
AVSS_SATA_6
AVSS_SATA_7
AVSS_SATA_8
AVSS_SATA_9
AVSS_SATA_10
AVSS_SATA_11
AVSS_SATA_12
AVSS_SATA_13
AVSS_SATA_14
AVSS_SATA_15
AVSS_SATA_16
AVSS_SATA_17
AVSS_SATA_18
AVSS_SATA_19
AVSS_SATA_20

V5_VREF--PCI 5V TOLERANCE

0.2A

L40

BLM18PG181SN1D(180,1.5A)_6

2

+3VS5

AVDDTX--USB Phy
Analog I/O power

USB I/O

For support USB
wakeup-->3V_S5

T10
U10
U11
U12
V11
V14
W9
Y9
Y11
Y14
Y17
AA9
AB9
AB11
AB13
AB15
AB17
AC8
AD8
AE8

GROUND

R239

1

C813
1U/10V_4

AVDD_SATA_1
AVDD_SATA_4
AVDD_SATA_2
AVDD_SATA_3
AVDD_SATA_5
AVDD_SATA_6
AVDD_SATA_7

S5_3.3V_1
S5_3.3V_2
S5_3.3V_3
S5_3.3V_4
S5_3.3V_5
S5_3.3V_6
S5_3.3V_7

VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50

S5_3.3--3.3v standby power

0.01A

A17
A24
B17
J4
J5
L1
L2

2

C817
1U/10V_4

C427

*0.1U/50V_6

1

1

1
C818
0.1U/10V_4

2

2

C812
0.1U/10V_4

AA14
AB18
AA15
AA17
AC18
AD17
AE17

SATA I/O

0.2A

2

1

1
C816
22U/6.3V_8

2

2

BLM18PG181SN1D(180,1.5A)_6

1

+1.2V

L38

C445

*2.2U/6.3V_6

2

+1.2V_AVDD_SATA

AVDD_SATA--SATA phy power

C474

2

AMD : Change from 1u to 0.1u

L70

286mA

L21
L22
L24
L25

+3VALW_R

3.3V_S5 I/O

0.1U/10V_4 0.1U/10V_4

PCIE_VDDR_1
PCIE_VDDR_2
PCIE_VDDR_3
PCIE_VDDR_4
PCIE_VDDR_5
PCIE_VDDR_6
PCIE_VDDR_7

CORE S5

C437

2

C447

P18
P19
P20
P21
R22
R24
R25

A-LINK I/O

1

1
C473
1U/10V_4

2

C438
1U/10V_4

2

2

C466
1U/10V_4

CKVDD_1.2V-- Internal
clock Generator I/O
power
AMD : Change from inductance to short pad

AMD : Remove Cap for internal clock

844mA

1

1

1
C431
10U/6.3V_8

2

2

C

1

BLM18PG181SN1D(180,1.5A)_6

SB710
C408
10U/6.3V_8

POWER

+1.2V_PCIE_VDDR

PCIE_VDDR--PCIE I/O power
L69

C497
1U/10V_4

U31E

+1.2V

AMD : Change from 1u to 0.1u

2

*0.1U/10V_4

CKVDD_1.2V_1
CKVDD_1.2V_2
CKVDD_1.2V_3
CKVDD_1.2V_4

CLKGEN I/O

C443

IDE/FLSH I/O

1

2

VDD33_18_1
VDD33_18_2
VDD33_18_3
VDD33_18_4

2

1

Y20
AA21
AA22
AE25

AMD : Change from 1u to 0.1u
AMD : Remove Cap for IDE mode

+1.2V

C498
C513
C506
0.1U/10V_4 0.1U/10V_4 1U/10V_4

+1.2V_CKVDD

0.45A

C465
C442
C460
*1U/10V_4
*0.1U/10V_4*0.1U/10V_4

2

1
C441
*10U/6.3V_8

2

1
SI Remove R219 from AMD request

1

VDD33_18--3.3V IDE I/O power
1.8V flash memory I/O power

1 *0_8/S

2

R216 2

+3V

+VDD33_18

R179
1 *0_8/S

2

2

AMD : Change from 1u to 0.1u

1.8V : FLASH MEMORY MODE(DEFAULT)
3.3V: IDE MODE

L15
M12
M14
N13
P12
P14
R11
R15
T16

2

0.1U/10V_4 0.1U/10V_4 0.1U/10V_4

VDD_1
VDD_2
VDD_3
VDD_4
VDD_5
VDD_6
VDD_7
VDD_8
VDD_9

2

2

C565

2

C528

2

C517

Part 3 of 5

1

1

1
C556
1U/10V_4

1

1
C564
1U/10V_4

2

1
C551
1U/10V_4

2

C537
10U/6.3V_8

2

2

D

1

1

1
2

100U/6.3V_3528

VDDQ_1
VDDQ_2
VDDQ_3
VDDQ_4
VDDQ_5
VDDQ_6
VDDQ_7
VDDQ_8
VDDQ_9
VDDQ_10
VDDQ_11
VDDQ_12

604mA

2

L9
M9
T15
U9
U16
U17
V8
W7
Y6
AA4
AB5
AB21

+3V
C571

SB710
CORE S0

0.8A

PCI/GPIO I/O

VDDQ--3.3V I/O power

2

U31C

PROJECT : OP8
Quanta Computer Inc.

C486
2.2U/6.3V_6
Size
Custom
NB5/RD2

Document Number

Date: Friday, March 20, 2009
5

4

3

2

Rev
1A

SB700-PWR/DECOUPLING 4/4
Sheet
1

15

of

42

5

4

3

2

1

16

OVERLAP COMMON PADS WHERE
POSSIBLE FOR DUAL-OP RESISTORS.
It must ready
refore RSMRST#
+3V

+3VS5
1

+3V

D

REQUIRED STRAPS

+3VS5

D

12

2

2

LPC_CLK0

PCI_CLK5

12

12

RTC_CLK

LPC_CLK1

13

GPIO16

ACZ_RST#

R214
*2.2K_4

R242
2.2K_4

GPIO17

PCI_CLK_TPM
C

BOOTFAIL
TIMER
ENABLED

PULL
HIGH

R304
10K/F_4

TYPE

GPIO16

GPIO17

FWH

L : 2.2K
pull down

L : 2.2K
pull down

LPC

NC

L : 2.2K
pull down

SPI

L : 2.2K
pull down

NC

NC

NC

2

R203
10K/F_4
2

R221
10K/F_4
2

R502
*10K/F_4

1

1

1
R499
*10K/F_4

2

2

2

R503
10K/F_4

2

R504
10K/F_4

1

1

1

1

2

12

SB_GPIO17
SB_GPIO16
1

PCI_CLK4

PCI_CLK3

13
13

2

12
12

intermal have pull
Hi 10K , confirm AMD
ward this pull Hi
not need

1

12 PCI_CLK_TPM

R337
*10K/F_4

2

R501
10K/F_4

2

R500
10K/F_4

1

1

1

R211
2.2K_4

PCI_CLK3

PCI_CLK4

PCI_CLK5

LPC_CLK0

LPC_CLK1

RTC_CLK

USE
DEBUG
STRAPS

RESERVED

RESERVED

IMC
ENABLED

CLKGEN
ENABLED

INTERNAL
RTC

AZ_RST#
ENABLE PCI
ROM BOOT

DEFAULT

PULL
LOW

BOOTFAIL
TIMER
DISABLED

IGNORE
DEBUG
STRAPS

IMC
DISABLED

CLKGEN
DISABLED

DEFAULT

DEFAULT

DEFAULT

DEFAULT

EXT. RTC
(PD on X1,
apply
32KHz to
RTC_CLK)

DISABLE PCI
ROM BOOT

RSVD

C

DEFAULT

NB_PWRGD_IN:
RS780/RX780 = 1.8V; RS740 = 3.3V
Do NOT share it with SB_PWRGD when use Internal Clk Gen
(Need SB PLL initialize firstly)

DEBUG STRAPS
SB700 HAS 15K INTERNAL PU FOR PCI_AD[28:23]
+3VS5

R292

10K/F_4

R281

SB_PWRGD_IN

*0_4/S

C555
*2.2U/6.3V_6
AD28
AD27
AD26
AD25
AD24
AD23

NB/SB POWER GOOD CIRCUIT

+1.8V
+1.8V

B

U13

36 VRM_PWRGD

1

1

1

1

1

1
1

B

12
12
12
12
12
12

SB_PWRGD_IN 13

2

2
3

R498
*2.2K_4

Use 2.2K PD.

C519

5

*0.1U/10V_4

RX780,RS780

A
GND

R269
300_4

Y

R274

4

NB_PWRGD_IN

*33_4

NB_PWRGD_IN

10

*NL17SZ17DFT2G
SOT-353

1

5,32 ECPWROK

2

R485
*2.2K_4
2

R491
*2.2K_4
2

R497
*2.2K_4
2

R484
*2.2K_4
2

2

R496
*2.2K_4

3

NC VCC

D17
BAT54A

SI remove R260

WD_PWRGD 13

PCI_AD28
PULL
HIGH

PULL
LOW
A

PCI_AD27

PCI_AD26

PCI_AD25

PCI_AD24

PCI_AD23

USE
LONG
RESET

USE PCI
PLL

USE ACPI
BCLK

USE IDE
PLL

USE DEFAULT
PCIE STRAPS

RESERVED

DEFAULT

DEFAULT

DEFAULT

DEFAULT

DEFAULT

USE
SHORT
RESET

BYPASS
PCI PLL

BYPASS
ACPI
BCLK

BYPASS IDE
PLL

USE EEPROM
PCIE STRAPS

AL17SZ17000

IC(5P) NL17SZ17DFT2G(SOT-353)

SOT-353

ALUC1G17000

IC OTHER(5P) SN74AUC1G17DBVR(SOT23-5)

SOT23-5

A

PROJECT : OP8
Quanta Computer Inc.
Size
Custom
NB5/RD2

Document Number

5

4

3

2

Rev
1A

SB700-STRAPS

Date: Friday, March 20, 2009

Sheet
1

16

of

42

5

4

3

2

POWER
+PCIE_VDDR=1.2V
+VDD_MEM1.8V=1.8V
+VGA_CORE=0.9~1.2V

U22A

1

17

U22G
DP E/F POWER
+1.8V_DPE_VDD18

DP A/B POWER

AG15
AG16

DPE_VDD18#1
DPE_VDD18#2

NC_DPA_VDD18#1
NC_DPA_VDD18#2

AE11
AF11

+1.8V

AG20
AG21

DPE_VDD10#1
DPE_VDD10#2

DPA_VDD10#1
DPA_VDD10#2

AF6
AF7

+1.1V_DPB_VDD10

AG14
AH14
AM14
AM16
AM18

DPE_VSSR#1
DPE_VSSR#2
DPE_VSSR#3
DPE_VSSR#4
DPE_VSSR#5

DPA_VSSR#1
DPA_VSSR#2
DPA_VSSR#3
DPA_VSSR#4
DPA_VSSR#5

AE1
AE3
AG1
AG6
AH5

AF16
AG17

DPF_VDD18#1
DPF_VDD18#2

NC_DPB_VDD18#1
NC_DPB_VDD18#2

AF22
AG22

DPF_VDD10#1
DPF_VDD10#2

DPB_VDD10#1
DPB_VDD10#2

2.5GT/s bit rate
9
9

PEG_TX0
PEG_TX#0

9
9

PEG_TX1
PEG_TX#1

9
9

PEG_TX2
PEG_TX#2

9
9

PEG_TX3
PEG_TX#3

9
9

PEG_TX4
PEG_TX#4

9
9

PEG_TX5
PEG_TX#5

9
9

PEG_TX6
PEG_TX#6

9
9

PEG_TX7
PEG_TX#7

9
9

PEG_TX8
PEG_TX#8

PEG_TX0
PEG_TX#0

AF30
AE31

PCIE_RX0P
PCIE_RX0N

PCIE_TX0P
PCIE_TX0N

AH30
AG31

C_PEG_RXP0
C_PEG_RXN0

C92
C84

0.1U/10V_4
0.1U/10V_4

PEG_TX1
PEG_TX#1

AE29
AD28

PCIE_RX1P
PCIE_RX1N

PCIE_TX1P
PCIE_TX1N

AG29
AF28

C_PEG_RXP1
C_PEG_RXN1

C94
C99

0.1U/10V_4
0.1U/10V_4

PEG_TX2
PEG_TX#2

AD30
AC31

PCIE_RX2P
PCIE_RX2N

PCIE_TX2P
PCIE_TX2N

AF27
AF26

C_PEG_RXP2
C_PEG_RXN2

C100
C112

0.1U/10V_4
0.1U/10V_4

PEG_TX3
PEG_TX#3

AC29
AB28

PCIE_RX3P
PCIE_RX3N

PCIE_TX3P
PCIE_TX3N

AD27
AD26

C_PEG_RXP3
C_PEG_RXN3

C83
C82

0.1U/10V_4
0.1U/10V_4

PEG_TX4
PEG_TX#4

AB30
AA31

PCIE_RX4P
PCIE_RX4N

PCIE_TX4P
PCIE_TX4N

AC25
AB25

C_PEG_RXP4
C_PEG_RXN4

C134
C146

0.1U/10V_4
0.1U/10V_4

PEG_RX0 9
PEG_RX#0 9

+1.1V_DPE_VDD10

D

D

9
9

PEG_TX9
PEG_TX#9

9
9

PEG_TX10
PEG_TX#10

9
9

PEG_TX11
PEG_TX#11

9
9

PEG_TX12
PEG_TX#12

9
9

PEG_TX13
PEG_TX#13

PCI EXPRESS INTERFACE

C

PEG_TX5
PEG_TX#5

AA29
Y28

PCIE_RX5P
PCIE_RX5N

PCIE_TX5P
PCIE_TX5N

Y23
Y24

C_PEG_RXP5
C_PEG_RXN5

C120
C131

0.1U/10V_4
0.1U/10V_4

PEG_TX6
PEG_TX#6

Y30
W 31

PCIE_RX6P
PCIE_RX6N

PCIE_TX6P
PCIE_TX6N

AB27
AB26

C_PEG_RXP6
C_PEG_RXN6

C153
C156

0.1U/10V_4
0.1U/10V_4

PEG_TX7
PEG_TX#7

W 29
V28

PCIE_RX7P
PCIE_RX7N

PCIE_TX7P
PCIE_TX7N

Y27
Y26

C_PEG_RXP7
C_PEG_RXN7

C164
C171

0.1U/10V_4
0.1U/10V_4

PEG_TX8
PEG_TX#8

V30
U31

PCIE_RX8P
PCIE_RX8N

PCIE_TX8P
PCIE_TX8N

W 24
W 23

C_PEG_RXP8
C_PEG_RXN8

C187
C199

0.1U/10V_4
0.1U/10V_4

PEG_TX9
PEG_TX#9

U29
T28

PCIE_RX9P
PCIE_RX9N

PCIE_TX9P
PCIE_TX9N

V27
U26

C_PEG_RXP9
C_PEG_RXN9

C183
C172

0.1U/10V_4
0.1U/10V_4

PEG_TX10
PEG_TX#10

T30
R31

PCIE_RX10P
PCIE_RX10N

PCIE_TX10P
PCIE_TX10N

U24
U23

C_PEG_RXP10
C_PEG_RXN10

C210
C223

0.1U/10V_4
0.1U/10V_4

PEG_TX11
PEG_TX#11

R29
P28

PCIE_RX11P
PCIE_RX11N

PCIE_TX11P
PCIE_TX11N

T26
T27

C_PEG_RXP11
C_PEG_RXN11

C225
C234

0.1U/10V_4
0.1U/10V_4

PEG_TX12
PEG_TX#12

P30
N31

PCIE_RX12P
PCIE_RX12N

PCIE_TX12P
PCIE_TX12N

T24
T23

C_PEG_RXP12
C_PEG_RXN12

C236
C246

0.1U/10V_4
0.1U/10V_4

PEG_TX13
PEG_TX#13

N29
M28

PCIE_RX13P
PCIE_RX13N

PCIE_TX13P
PCIE_TX13N

P27
P26

C_PEG_RXP13
C_PEG_RXN13

C249
C253

0.1U/10V_4
0.1U/10V_4

PEG_RX1 9
PEG_RX#1 9
PEG_RX2 9
PEG_RX#2 9
PEG_RX3 9
PEG_RX#3 9
PEG_RX4 9
PEG_RX#4 9

1.1V(S100,D200mA)
+1.8V_DPE_VDD18

B

PEG_TX14
PEG_TX#14

9
9

PEG_TX15
PEG_TX#15

PEG_TX14
PEG_TX#14
PEG_TX15
PEG_TX#15

M30
L31
L29
K30

PCIE_RX14P
PCIE_RX14N

PCIE_TX14P
PCIE_TX14N

P24
P23

PCIE_RX15P
PCIE_RX15N

PCIE_TX15P
PCIE_TX15N

M27
N26

C_PEG_RXP14
C_PEG_RXN14
C_PEG_RXP15
C_PEG_RXN15

C269
C270
C256
C264

AK30
AK32

PEG_RX6 9
PEG_RX#6 9
PEG_RX7 9
PEG_RX#7 9

R51

12

10K/F_4

1

2 R533

L9
N9
N10
AL27

PCIE_RST#

PEG_RX10 9
PEG_RX#10 9

150/F_4

AF23
AG23
AM20
AM22
AM24

DPF_VSSR#1
DPF_VSSR#2
DPF_VSSR#3
DPF_VSSR#4
DPF_VSSR#5

DPB_VSSR#1
DPB_VSSR#2
DPB_VSSR#3
DPB_VSSR#4
DPB_VSSR#5

AF10
AG9
AH8
AM6
AM8

AF17

DPEF_CALR

DPAB_CALR

AE10

DPA_PVDD
DPA_PVSS

AG8
AG7

+1.8V_DPA_PVDD

DPB_PVDD
DPB_PVSS

AG10
AG11

+1.8V_DPA_PVDD

+1.8V_DPE_PVDD

+1.8V_DPE_PVDD AG18
AF19

+1.8V_DPE_PVDD

+1.8V_DPE_PVDD AG19
AF20

DPE_PVDD
DPE_PVSS

DP PLL POWER

NC_DPF_PVDD
NC_DPF_PVSS

R63

1000P/50V_4

150/F_4

+1.8V_DPA_PVDD

+1.8V_DPA_PVDD

PEG_RX12 9
PEG_RX#12 9
PEG_RX13 9
PEG_RX#13 9

+1.1V_DPE_VDD10

0.1U/10V_4
0.1U/10V_4

PEG_RX14 9
PEG_RX#14 9

0.1U/10V_4
0.1U/10V_4

PEG_RX15 9
PEG_RX#15 9

+1.8V_DPA_PVDD

1.1V(S100,D200mA)
L51

+1.1V

C658

BLM18PG181SN1D(180,1.5A)_6
C648
10U/6.3V_8

C114

C104

0.1U/10V_4

1000P/50V_4

+1.8V_DPA_PVDD
C663

0.1U/10V_4

1000P/50V_4

L54

1.8V(40mA)
+1.8V

BLM18PG181SN1D(180,1.5A)_6
C649
10U/6.3V_8
B

+1.8V_DPE_PVDD

C54

NC#1
NC#2
NC_PW RGOOD

PCIE_CALRP
PCIE_CALRN

+1.8V_DPE_PVDD
C53

0.1U/10V_4

Y22

M72_PCIE_CALRP

R72

1.27K/F_4

AA22

M72_PCIE_CALRN

R71

2K/F_4

L10

1000P/50V_4

+1.8V

+1.1V_PCIE_VDDC

PERSTB

1.8V -(300mA)

C111

100MHz (+/-300ppm) input frequency,
0-0.7V single-ended swing

0.1U/10V_4

VGA Core

BPP

VGA Core

VDDC

+1.8V

PCIE_VDDR

+1.8V

PCIE_PVDD

+1.8V

VDDR1

SI remove DPB power source

1.8V(20mA)

BLM18PG181SN1D(180,1.5A)_6
C52
10U/6.3V_8

+1.8V_DPE_VDD18

L12

+1.8V

C56
C103
1U/10V_4

10U/6.3V_8

BLM18PG181SN1D(180,1.5A)_6

A

PROJECT : OP8
Quanta Computer Inc.

VDDR3
20ms

Size
Custom

20ms

NB5/RD2

Document Number

4

3

2

Rev
1A

M7X/M8X_PCIE_Interface

Date: Friday, March 20, 2009
5

C118

M92-S2

PEG_RX11 9
PEG_RX#11 9

PCIE_REFCLKP
PCIE_REFCLKN

3.3V_Delay

BLM18PG181SN1D(180,1.5A)_6
L59
+1.1V

C698
10U/6.3V_8

PEG_RX9 9
PEG_RX#9 9

M92-S2

A

C677

C

PEG_RX8 9
PEG_RX#8 9

CALIBRATION

SI Add

AF8
AF9

0.1U/10V_4

PEG_RX5 9
PEG_RX#5 9

CLOCK
EXT_GFX_CLKP
EXT_GFX_CLKN

2 EXT_GFX_CLKP
2 EXT_GFX_CLKN

+1.8V

+1.1V_DPB_VDD10
+1.1V_DPE_VDD10

+1.1V_DPE_VDD10
9
9

AE13
AF13

Sheet
1

17

of

42

5

4

3

2

1

U22B

M93-S3/M92-S2
R414

10K/F_4

AE9
L9
N9
AE8

GPIO22

GPIO22(ROMCS#)
PD without external VBIOS ROM

AD7
AC8
AC7
AB9
AB8
AB7
AB4

D

+VDDR4

MEM_ID[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111

Vendor

Type

Memory ID
R401
R406
R402
R405

Vendor P/N

Hynix
64*16-500MHZ
Samsung (E die)
64*16-500MHZ
Qimonda (Infineon) 64*16-500MHZ

Y8
Y7
*10K/F_4
*10K/F_4
*10K/F_4
*10K/F_4

TXCAP_DPA3P
TXCAM_DPA3N

DVCNTL_0/ DVPDATA_18
DVCNTL_1 / NC
DVCNTL_2 / NC
DVDATA_12 / DVPDATA_16

TX1P_DPA1P
TX1M_DPA1N

DVDATA_9 / DVPDATA_12
DVDATA_8 / DVPDATA_14
DVDATA_7 / DVPCNTL_0
DVDATA_6 / DVPDATA_8
DVDATA_5 / DVPDATA_6
DVDATA_4 DVPDATA_4
DVDATA_3 / DVPDATA_19

TX2P_DPA0P
TX2M_DPA0N
TXCBP_DPB3P
TXCBM_DPB3N

DVDATA_1 / DVPDATA_2
DVDATA_0 / DVPDATA_0

AC5
AC10
AB2
AD9

H5P51G63EFR-20L
K4N1G164QE-HC20
TBD
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved

TX3P_DPB2P
TX3M_DPB2N

DPB

DVO

MEM_ID3
MEM_ID2
MEM_ID1
MEM_ID0

TX0P_DPA2P
TX0M_DPA2N

DPA

TX4P_DPB1P
TX4M_DPB1N

DPC_VDD18#2/DVPDAT23
DVDATA_10 / DVPDATA_22
DVDATA_2 / DVPDATA_21
DVDATA_11 / DVPDATA_20

TX5P_DPB0P
TX5M_DPB0N

AF2
AF4

1.8V(70mA)

C674

AK5
AM3

TXC_HDMI_L+
TXC_HDMI_L-

AK6
AM5

TX0_HDMI_L+
TX0_HDMI_L-

AJ7
AH6

TX1_HDMI_L+
TX1_HDMI_L-

AK8
AL7

TX2_HDMI_L+
TX2_HDMI_L-

AA5
AA6

AA1

1U/10V_4

TXC_HDMI_L+ 25
TXC_HDMI_L- 25

D

TX0_HDMI_L+ 25
TX0_HDMI_L- 25

+1.8V_A2VDD_Q

1.8V(70mA)

TX1_HDMI_L+ 25
TX1_HDMI_L- 25

L52

+1.8V_A2VDD_Q

TX2_HDMI_L+ 25
TX2_HDMI_L- 25

C650

+1.8V

BLM18PG181SN1D(180,1.5A)_6
C651
10U/6.3V_8

C124
1U/10V_4

M92-S2/M93-S3
DVPDATA_3/TXCCP_DPC3P
DVPCNTL_2/TXCCM_DPC3N

DPC_VDD18#1/DVPDAT10

DVPDATA_7 / TX0P_DPC2P
DVPDATA_1 / TX0M_DPC2N

DPC_VDD10#1/DVPDAT15
DPC_VDD10#2/DVPDAT17

DVPCNTL_MV1 / TX1P_DPC1P
DVPDATA_9 / TX1M_DPC1N
U1
W1

+1.8V

BLM18PG181SN1D(180,1.5A)_6
C659
10U/6.3V_8

C673

0.1U/10V_4

AK3
AK1

0.1U/10V_4

DPC_PVDD / DVPDATA_11

L57

+1.8V_AVDD_Q

AH3
AH1

M93-S3/M92-S2
W6
AC6

18

+1.8V_AVDD_Q

AG3
AG5

DPC_VSSR#1 / DVPCLK
DPC_VSSR#2 / DVPDAT5

DVPDATA_13 / TX2P_DPC0P
DVPCNTL_1 / TX2M_DPC0N
VDDR4 / DPCD_CALR

V4
U5
W3
V2

+VDDD1

1.8V(45mA VDD1DI)
Y4
W5
AA3
Y2

C632

+VDDR4
R69

AA12

L49

+VDDD1

M92-S2: Use 0R to VDDR4

0_4

0.1U/10V_4

+1.8V

BLM18PG181SN1D(180,1.5A)_6
C641
10U/6.3V_8

C654
1U/10V_4

DPC_VSSR#5/ DVPCNTL_MV0

DPC

PWRCNTL1 PWRCNTL0 V-CORE

+VDDD2

0

M

1

1

M

R1
R3

10,23 EDIDCLK
10,23 EDIDDATA

1.0V

1

T9
T7
19 GPIO5

0.9V

R59

10,23 LVDS_BLON
19 GPIO8
19 GPIO9
T70

L
H

0
1

19 GPIO11
19 GPIO12
19 GPIO13

BBP

BBEN

T3

38 GFX_CORE_CNTRL0
2 OSC_SPREAD

V-CORE
+1.8V

T6
5 TEMP_FAIL
38 GFX_CORE_CNTRL1
20
BBEN
19 GPIO22

SI Add GND from

+3V_DELAY

*10K/F_4

R60

+3V_DELAY

10K/F_4

R52

SI Add GND from Check list

GPIO_23_CLKREQb

5.11K/F_4

TESTEN

T120

LVDS_BLON
19

R417

U6
U10
T10
U8
U7
T9
T8
0_4
EXT_LVDS_BLON
T7
GPIO8
P10
GPIO9
P4
GPIO10
P2
GPIO11
N6
GPIO12
N5
GPIO13
N3
HDMI_HP2
Y9
GFX_CORE_CNTRL0
N1
OSC_SPREAD
M4
VGA_ALERT
R6
HPD3
W10
TEMP_FAIL
M2
GFX_CORE_CNTRL1
P8
BBEN
P7
GPIO22
N8
GPIO_23_CLKREQb
N7
T11
R11
Check list

T11
T10
T71
T72
T73

Need check again
B

SCL
SDA

GENERICC

GENERICC
150 OHM

10,25 TMDS_HPD
*100K/F_4

R65

TMDS_HPD

L6
L5
L3
L1
K4
AF24
AB13
W8
W9
W7
AD10
AC14

GPIO_0
GPIO_1
GPIO_2
GPIO_3_SMBDATA
GPIO_4_SMBCLK
GPIO_5_AC_BATT
GPIO_6
GPIO_7_BLON
GPIO_8_ROMSO
GPIO_9_ROMSI
GPIO_10_ROMSCK
GPIO_11
GPIO_12
GPIO_13
GPIO_14_HPD2
GPIO_15_PWRCNTL_0
GPIO_16_SSIN
GPIO_17_THERMAL_INT
GPIO_18_HPD3
GPIO_19_CTF
GPIO_20_PWRCNTL_1
GPIO_21_BB_EN
GPIO_22_ROMCSB
GPIO_23_CLKREQB
GPIO_29
GPIO_30
JTAG_TRSTB
JTAG_TDI
JTAG_TCK
JTAG_TMS
JTAG_TDO
TESTEN

R
RB
G
GB
B
BB

DAC1

HSYNC
VSYNC
RSET
AVDD
AVSSQ
VDD1DI
VSS1DI
R2 / NC
R2B / NC
G2 / NC
G2B / NC
B2 / NC
B2B / NC

BLM18PG181SN1D(180,1.5A)_6

1.8V(120mADPLL_PVDD)

C58

GENERICA
GENERICB
GENERICC
GENERICD
GENERICE_HPD4

C / NC
Y / NC
COMP / NC
H2SYNC
V2SYNC
VDD2DI / NC
VSS2DI / NC

HPD1

AL25
AJ25

L_CRT_G

AH24
AG25

L_CRT_B

L_CRT_R

R380
R56

150/F_4
0_4

L_CRT_G

R379
R47

150/F_4
0_4

R378
R44

150/F_4
0_4

L_CRT_B

AH26
AJ27
AD22
AG24
AE22
AE23
AD23

CRT_R

10,24

CRT_G

10,24

CRT_B

10,24

HSYNC_COM
VSYNC_COM
R61

C113
0.1U/10V_4

249/F_4

+0.6V_M92_VREFG

AC16

A2VDDQ / NC
VREFG

0.1U/10V_4

R2SET / NC

10,19,24
10,19,24

+1.8V_AVDD_Q
C672
+VDDD1

+1.8V_AVDD_Q

0.1U/10V_4

+VDDD1

C628
0.1U/10V_4

AM12
AK12

C657

*22P/50V_4

AL11
AJ11

CL=20PF

AK10
AL9

C110
0.1U/10V_4

PLL/CLOCK

BLM18PG181SN1D(180,1.5A)_6
L8
C51
1U/10V_4

C123
0.1U/10V_4

2

EVGA-XTALI

AF14
AE14

+1.1V_DPLL_VDDC

AD14

EVGA-XTALI
EVGA-XTALO

AM28
AK28

DPLL_PVDD
DPLL_PVSS

DDC1CLK
DDC1DATA
AUX1P
AUX1N

DPLL_VDDC

DDC2CLK
DDC2DATA

XTALIN
XTALOUT

AUX2P
AUX2N
DDCCLK_AUX5P
DDCDATA_AUX5N

BLM18PG181SN1D(180,1.5A)_6
+1.8V
A

1.8V(20mA TSVDD)

VGATHRM+
VGATHRM-

L11
C55
10U/6.3V_8

R388
*10M_6

C656

For Int Clk 27Mhz

EVGA-XTALO

AH12
AM10
AJ9
AL13
AJ13

DAC2_VSY
DAC2_HSY

DAC2_VSY
DAC2_HSY

19
19

B

+VDDD2

+VDDD2

AD19
AC19

C49

Thermal Sensor

AE20
AE17

781-1_3V

+3V_DELAY
+1.8V_A2VDD_Q

+1.8V_A2VDD_Q

C162
0.1U/10V_4

MBCLK2

AE19
5,32

AG13

R50

715/F_4

MBDATA2
+3V_DELAY

C61
1U/10V_4

T4
T2

DPLUS
DMINUS

DDCCLK_AUX3P
DDCDATA_AUX3N

C143
+1.8V_TSVDD

0.1U/10V_4

R5
AD17
AC17

THERMAL

DDC6CLK
DDC6DATA

TS_FDO
TSVDD
TSVSS

NC#1
NC#2

AE6
AE5

HDMI_SCL
HDMI_SDA

R39

U3
5,32

DDC/AUX

1U/10V_4

C59
10U/6.3V_8

EVGA-XTALI

Y7
*27MHZ

R55

*0_4/S

R54

*0_4/S
R53

10K/F_4

MB_CLK2

8

MB_DATA2

7

VGA_ALERT

6
5

+1.8V_DPLL_PVDD

1.1V(300mA DPLL_VDDC)

C

1U/10V_4

499/F_4

L53
C652
10U/6.3V_8

+1.8V

BLM18PG181SN1D(180,1.5A)_6
C46
10U/6.3V_8

C48

0.1U/10V_4

A2VDD / NC

C644

+1.1V

L_CRT_R

*22P/50V_4

DAC2

A2VSSQ

+1.8V

AM26
AK26

M92-S2/M93-S3

+1.8V
1.8V+R6043(249R)=1.8V/3=0.6V
R33
499/F_4
R66

L9

+VDDD2

I2C

GENERAL PURPOSE I/O
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5

19 GPIO0
19 GPIO1
19 GPIO2

1.0V

0

1

L

1.8V(45mA VDD1DI)

1.1V

1

C

0

2

0

H

SMCLK
SMDATA

DXP

-ALT

DXN

GND

-OVT

VGATHRM+

2

C78
2200P/50V_4

3

G781-1P8@EV

25
25

-VGATHRM
R42

+3V_DELAY

10K/F_4

T67
T2

AC11
AC13
AD13
AD11
AE16
AD16
AC1
AC3

DDCCLK
10,24
DDCDATA 10,24

AD20
AC20

A

AB22
AC22

T121
T122

SI Add from AMD check list

PROJECT : OP8
Quanta Computer Inc.
Size
Custom
NB5/RD2

Document Number

3

2

Rev
1A

M7X/M8X_Main

Date: Friday, March 20, 2009
4

w/s 10 / 10

VGATHRM-

4

M92-S2

5

+3V_DELAY

0.1U/10V_4

1

I2C ADDRESS: 9AH
AD2
AD4

200/F_6

C64

VCC

1

Sheet

18

of

42

5

4

3

2

1

19

U22E
U22F
R40

D

C

B

AA27
AB24
AB32
AC24
AC26
AC27
AD25
AD32
AE27
AF32
AG27
AH32
K28
K32
L27
M32
N25
N27
P25
P32
R27
T25
T32
U25
U27
V32
W 25
W 26
W 27
Y25
Y32

M6
N11
N12
N13
N16
N18
N21
P6
P9
R12
R15
R17
R20
T13
T16
T18
T21
T6
U15
U17
U20
U3
U9
V13
V16
V18
V6
Y10
Y15
Y17
Y20
Y6

PCIE_VSS#1
PCIE_VSS#2
PCIE_VSS#3
PCIE_VSS#4
PCIE_VSS#5
PCIE_VSS#6
PCIE_VSS#7
PCIE_VSS#8
PCIE_VSS#9
PCIE_VSS#10
PCIE_VSS#11
PCIE_VSS#12
PCIE_VSS#13
PCIE_VSS#14
PCIE_VSS#15
PCIE_VSS#16
PCIE_VSS#17
PCIE_VSS#18
PCIE_VSS#19
PCIE_VSS#20
PCIE_VSS#21
PCIE_VSS#22
PCIE_VSS#23
PCIE_VSS#24
PCIE_VSS#25
PCIE_VSS#26
PCIE_VSS#27
PCIE_VSS#28
PCIE_VSS#29
PCIE_VSS#30
PCIE_VSS#31

GND#56
GND#57
GND#58
GND#59
GND#60
GND#61
GND#62
GND#63
GND#64
GND#65
GND#66
GND#67
GND#68
GND#69
GND#70
GND#71
GND#72
GND#73
GND#74
GND#75
GND#76
GND#77
GND#78
GND#79
GND#80
GND#81
GND#82
GND#83
GND#84
GND#85
GND#86
GND#87

GND

GND#1
GND#2
GND#3
GND#4
GND#5
GND#6
GND#7
GND#8
GND#9
GND#10
GND#11
GND#12
GND#13
GND#14
GND#15
GND#16
GND#17
GND#18
GND#19
GND#20
GND#21
GND#22
GND#23
GND#24
GND#25
GND#26
GND#27
GND#28
GND#29
GND#30
GND#31
GND#32
GND#33
GND#34
GND#35
GND#36
GND#37
GND#38
GND#39
GND#40
GND#41
GND#42
GND#43
GND#44
GND#45
GND#46
GND#47
GND#48
GND#49
GND#50
GND#51
GND#52
GND#53
GND#54
GND#55

A3
A30
AA13
AA16
AB10
AB15
AB6
AC9
AD6
AD8
AE7
AG12
AH10
AH28
B10
B12
B14
B16
B18
B20
B22
B24
B26
B6
B8
C1
C32
E28
F10
F12
F14
F16
F18
F2
F20
F22
F24
F26
F6
F8
G10
G27
G31
G8
H14
H17
H2
H20
H6
J27
J31
K11
K2
K22
K6

LVDS CONTROL

VARY_BL
DIGON

0_4
0_4

AB11
AB12

Strap Name

TXCLK_UP_DPF3P
TXCLK_UN_DPF3N

EXT_TXUCLKOUT+ 23
EXT_TXUCLKOUT- 23

TXOUT_U0P_DPF2P
TXOUT_U0N_DPF2N

AL21
AK20

EXT_TXUOUT0+ 23
EXT_TXUOUT0- 23

TXOUT_U1P_DPF1P
TXOUT_U1N_DPF1N

AH22
AJ21

EXT_TXUOUT1+ 23
EXT_TXUOUT1- 23

TXOUT_U2P_DPF0P
TXOUT_U2N_DPF0N

AL23
AK22

EXT_TXUOUT2+ 23
EXT_TXUOUT2- 23

TXOUT_U3P
TXOUT_U3N

AK24
AJ23

TXCLK_LP_DPE3P
TXCLK_LN_DPE3N

AL15
AK14

EXT_TXLCLKOUT+ 23
EXT_TXLCLKOUT- 23

TXOUT_L0P_DPE2P
TXOUT_L0N_DPE2N

AH16
AJ15

EXT_TXLOUT0+ 23
EXT_TXLOUT0- 23

TXOUT_L1P_DPE1P
TXOUT_L1N_DPE1N

AL17
AK16

EXT_TXLOUT1+ 23
EXT_TXLOUT1- 23

TXOUT_L2P_DPE0P
TXOUT_L2N_DPE0N

AH18
AJ17

EXT_TXLOUT2+ 23
EXT_TXLOUT2- 23

TXOUT_L3P
TXOUT_L3N

AL19
AK18

Default Value

Pin Straps description
Transmitter Power Savings Enable

GPIO0

1

0: 50% Tx output swing for mobile mode
1: full Tx output swing (Default setting for Desktop)

PCI Express Transmitter De-emphasis Enable

TX_DEEMPH_EN

GPIO1

BIF_GEN2_EN

GPIO2

D

1

0: Tx de-emphasis disabled for mobile mode
1: Tx de-emphasis enabled (Default setting for Desktop)

0 = Advertises the PCI-E device as 2.5 GT/s capable at power-on.
1 = Advertises the PCI-E device as 5.0 GT/s capable at power-on.

0

5.0 GT/s capability will be controlled by software.
Enable CLKREQ# Power Management

STRAP_BIF_CLK_PM_EN

GPIO8

BIOS_ROM_EN

GPIO22

AUDIO[0]

VSYNC

AUD(1)

HSYNC

0

0 - CLKREQ# power management capability is disabled
1 - CLKREQ# power management capability is enabled

Enable external BIOS ROM device
0 - Disable external BIOS ROM device
external BIOS ROM device

0

1 - Enable

LVTMDP

1
HSYNC - HDMI_EN
HDMI connector presence. 0 ?No HDMI connector is present on PCB 1
- HDMI connector is present on the PCB HDMI

VIP_DEVICE_STRAP_DIS

DAC2_VSY

1

If VIP_DEVICE_STRAP_EN is set to ?? then this pin
is used to sense whether a VIP slave device is connected to the
VIP Host interface. If VIP_DEVICE_STRAP_EN is set to ?? then
this pin is not used as a strap at all (i.e. its value during
reset is unimportant), and it can be used as a regular GPIO

C

0

M92-S2

+3V_DELAY

18

GPIO0

GPIO0

R416

10K/F_4

18

GPIO1

GPIO1

R411

10K/F_4

GPIO2

R410

*10K/F_4

GPIO8

R413

*10K/F_4

R386

10K/F_4

R387

10K/F_4

R409

*10K/F_4

R367

10K/F_4

18

M92-S2

DPST_PWM 10,23
DISP_ON 10,23

AH20
AJ19

GPIO2
GPIO8

10,18,24 HSYNC_COM

A32
AM1
AM32

R37
R43

TX_PWRS_ENB

18

VSS_MECH#1
VSS_MECH#2
VSS_MECH#3

10K/F_4

10,18,24 VSYNC_COM
18 GENERICC
18

DAC2_VSY

18

DAC2_HSY

18

GPIO22

18

GPIO5

R368

10K/F_4

GPIO22

R415

*10K/F_4

GPIO5

R412

10K/F_4

+3V_DELAY

18

GPIO9

18

GPIO13

18

GPIO12

18

GPIO11

GPIO9

R423

*10K/F_4

GPIO13

R424

10K/F_4

GPIO12

R422

*10K/F_4

GPIO11

R419

*10K/F_4

SMS_EN_HARD

CCBYPASS

0

DAC2_HSY

0

GENERICC

Memory Aperture size
GPIO9

GPIO13 GPIO12 GPIO11

BIOSROM

ROMIDCFG2 ROMIDCFG1 ROMIDCFG0

128M
256M
64M
32M
512M
1G
2G
4G

0
0
0
0
0
0
0
0

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

B

0
1
0
1
0
1
0
1

It is a shared pin strap with CONFIG[2:0] if BIOS_ROM_EN is set to 0.
A

A

PROJECT : OP8
Quanta Computer Inc.
Size
Custom
NB5/RD2

Document Number

Date: Friday, March 20, 2009
5

4

3

2

Rev
1A

M7X/M8X_GND / LVDS/ Straps
Sheet
1

19

of

42

5

4

3

2

VDD_CT -- Level
translation between
core and I/O,
excluding memory
receivers.1.8 V ± 5%

1

20

PCIE_VDDR--PCI-E I/O power. 1.8 V ± 5%
U22D

+1.8V_PCIE_VDDR

MEM I/O
PCIE

1.8V(2.2A VDDR1+VDDRHA)
H13
H16
H19
J10
J23
J24
J9
K10
K23
K24
K9
L11
L12
L13
L20
L21
L22

VDDR1#1
VDDR1#2
VDDR1#3
VDDR1#4
VDDR1#5
VDDR1#6
VDDR1#7
VDDR1#8
VDDR1#9
VDDR1#10
VDDR1#11
VDDR1#12
VDDR1#13
VDDR1#14
VDDR1#15
VDDR1#16
VDDR1#17

AA20
AA21
AB20
AB21

VDD_CT#1
VDD_CT#2
VDD_CT#3
VDD_CT#4

+1.8V
C109
C247
1U/10V_4

D

C380
10U/6.3V_8

C251
1U/10V_4

C748
1U/10V_4

C368

C635

10U/6.3V_8

C233
1U/10V_4

C280

10U/6.3V_8

C245
1U/10V_4

+1.8V

C254
1U/10V_4

C243
1U/10V_4

C102
0.1U/10V_4 1U/10V_4

C285
0.1U/10V_4

10U/6.3V_8

+1.8V_VDD_CT

1.8V(136mA VDD_CT)
L14

C248
1U/10V_4

BLM18PG181SN1D(180,1.5A)_6

LEVEL
TRANSLATION

C145
C163

Gated 3.3V
10U/6.3V_8
60mA by +3V_DELAY
VDDC

AO3409

1000P/50V_4
0.1U/10V_4
+3V_DELAY

3
C633

M93-S3/M92-S2
C130

C157
1U/10V_4 1U/10V_4

2

R31
100K/F_4

AA17
AA18
AB17
AB18

0.1U/10V_4

1.8V(170mA VDDR5)
C

L16

+1.8V

BLM18PG181SN1D(180,1.5A)_6
+VDDR4

C97
10U/6.3V_8

3

C170
1U/10V_4 1U/10V_4

0.1U/10V_4

AA11
Y11
V11
U11

C165

BLM18PG181SN1D(180,1.5A)_6
CH501H-40PT L-F
2

C179

L62

+1.8V
D3
1

V12
Y12
U12

+VDDR5
C105

C702
10U/6.3V_8

1.8V(170mA VDDR4)

Q8
2N7002E

C711
1U/10V_4

CORE

VDDR3#1
VDDR3#2
VDDR3#3
VDDR3#4

I/O

VDDR4#1 / VDDR5
VDDR4#2
VDDR4#3 / VDDR5

POWER

1

+3V

VDD_R3 --IO power for
3.3 V pins (e.g.
GPIO’s). 3.3 V ± 5%

PCIE_VDDC#1
PCIE_VDDC#2
PCIE_VDDC#3
PCIE_VDDC#4
PCIE_VDDC#5
PCIE_VDDC#6
PCIE_VDDC#7
PCIE_VDDC#8
PCIE_VDDC#9
PCIE_VDDC#10
PCIE_VDDC#11
PCIE_VDDC#12

+1.8V_VDD_CT
C72

Q7

PCIE_VDDR#1
PCIE_VDDR#2
PCIE_VDDR#3
PCIE_VDDR#4
PCIE_VDDR#5
PCIE_VDDR#6
PCIE_VDDR#7
PCIE_VDDR#8

NC#1 / VDDR4
DVCLK / VDDR4
NC#3 / VDDR5
NC#4 / VDDR5

0.1U/10V_4
MEM CLK

27,32,35,38,39,40

R23

MAINON

68.1K_4

L22

+1.8V

2

VDDRH_1

BLM18PG181SN1D(180,1.5A)_6

L17

VDDRHA

L16

VSSRHA

C229
C227
10U/6.3V_8

0.1U/10V_4

1

1.8V(68mA PCIE_PVDD)
+1.8V

C45

L56

C665
10U/6.3V_8

0.1U/10V_4

+PCIE_PVDD

AM30

+VGA_CORE

L8

NC_MPV18
NC_SPV18

+VGA_CORE_SPV10

H8

B

SPV10

C266

J7

SPVSS

0.95V~1.1V(35mA SPV10)

L63

BLM18PG181SN1D(180,1.5A)_6

C732
10U/6.3V_8

VDD_R4 -- Power for DVPDATA_[23:12] - external
TMDS or GPIO; corresponds to
DVOA_MSB_VMODE register bit; '1' - 3.3 V(default);
'0' - 1.8 V; 1.8 V ± 5% or 3.3 V ± 5%

VDDC#20
VDDC#21
VDDC#22
VDDC#23
VDDC#19

Y13
Y16
Y18
Y21
V21

M11
M12
C231
C222
1U/10V_4

C691
1U/10V_4

C144
1U/10V_4

+1.8V

BLM18PG181SN1D(180,1.5A)_6
C678
10U/6.3V_8

C683
1U/10V_4

D

1.1V(2.0A)

+1.1V_PCIE_VDDC

L50
BLM21PG221SN1D(220,100M,2A)_8
C627

C196
1U/10V_4

C174
1U/10V_4

C182
1U/10V_4

C219
1U/10V_4

10U/6.3V_8

+VGA_CORE
VDDC+VDDCI
0.95~1.1V(15A peak )( Ripple < 87.2mV)
C639

C638

1U/10V_4

1U/10V_4

C161

C176

C643

1U/10V_4

1U/10V_4

1U/10V_4

C173

C175

C186

C626

1U/10V_4

1U/10V_4

1U/10V_4

1U/10V_4

VDDC--Dedicated core
power, provides power
to the internal
logic. 0.9 V - 1.2 V
(± 5%)

C33
C637
1U/10V_4

C211
1U/10V_4

PCIE_VDDC--PCI-E
Digital Power
Supply (Either 1.0
V or 1.1 V) 1.0 V
-5% to 1.1 V +5%

10U/6.3V_8

C625
C190
1U/10V_4

C

10U/6.3V_8

C624
10U/6.3V_8

+BIF_VDDC

SI Add from AMD check list
0.95V~1.1V(2A VDDCI)
M13
M15
M16
M17
M18
M20
M21
N20

+VDDCI L21
BLM21PG221SN1D(220,100M,2A)_8
C200

C217
C228
1U/10V_4

C216
1U/10V_4

C230
1U/10V_4

+VGA_CORE

VDDCI--Isolated (clean)
0.1U/10V_4 10U/6.3V_8 core power for the l/O
logic. Voltage level
should match that of
VDDC. POWER Same as VDDC

BBP -- Connect to VBBP back bias regulator / generator.
If back bias is not used, connect directly to VDDC.

B

Back Bias Enabled:
(GPIO_21_BB_EN = 3.3 V):
1.5 V or 1.8 V

BBP#1
BBP#2

Back Bias Disabled:
(GPIO_21_BB_EN = 0 V):
VDDC

0.1U/10V_4
M92-S2
+VBBP
+1.1V_PCIE_VDDC

*BLM18PG181SN1D(180,1.5A)_6

+1.8V_PCIE_VDDR

+1.8V or +1.1V @ 1A MAX
Q13
2N7002E

VDDRH_1 & VDDRH_2 --Dedicated power
pins for memory clock pads for each
channel. Should have the same
voltage level as VDDR1.

C121
C160
1U/10V_4

+1.8V

+VGA_CORE

C642

C690
0.1U/10V_4 1U/10V_4

10U/6.3V_8

C634

C32

10U/6.3V_8

C34

10U/6.3V_8

10U/6.3V_8

Q12
ME2303T1
1

3

2

1

2

3

R64
1

100K/F_4
2
+5V

SI Add from AMD check list

3

A

A

+VGA_CORE
HCB1608KF-181T15_6
L73

18

+VGA_CORE

L23

+VGA_CORE

Q11
2N7002E

2

BBEN

+BIF_VDDC

PROJECT : OP8
Quanta Computer Inc.

C845
1U/6.3V_4

1

C844
10U/6.3V_8

Size
Custom
NB5/RD2

Document Number

4

3

2

Rev
1A

M7X/M8X_Power_and_NC

Date: Friday, March 20, 2009
5

1.8V(500mA)

+1.1V

BACK BIAS

1.5/1.8V 120mA

C682
1U/10V_4

+1.1V_PCIE_VDDC

0.1U/10V_4

+VBBP

VDD_R5 -- Power for DVP control pins
(DVPCNTL_[0-2] and DVPCLK) and
DVPDATA_[11:0] - external TMDS or GPIO;
corresponds to DVOA_LSB_VMODE register bit;
'1' - 3.3 V(default); '0' - 1.8 V;
1.8 V
± 5% or 3.3 V ± 5%

PCIE_PVDD

H7

VDDC#1
VDDC#2
VDDC#3
VDDC#4
VDDC#5
VDDC#6
VDDC#7
VDDC#8
VDDC#9
VDDC#10
VDDC#11
VDDC#12
VDDC#13
VDDC#14
VDDC#15
VDDC#16
VDDC#17
VDDC#18

VDDCI#1
VDDCI#2
VDDCI#3
VDDCI#4
VDDCI#5
VDDCI#6
VDDCI#7
VDDCI#8

C664
0.1U/10V_4

0.1U/10V_4

L23
L24
L25
L26
M22
N22
N23
N24
R22
T22
U22
V22
AA15
N15
N17
R13
R16
R18
R21
T12
T15
T17
T20
U13
U16
U18
U21
V15
V17
V20

L60

C125

ISOLATED
CORE I/O

PLL

BLM18PG181SN1D(180,1.5A)_6

+1.8V_PCIE_VDDR

AB23
AC23
AD24
AE24
AE25
AE26
AF25
AG26

Sheet
1

20

of

42

5

4

3

2

1

21

U22C

ODTA0
ODTA1

22
22

RASA0#
RASA1#

RASA0#
RASA1#

22
22

CASA0#
CASA1#

CASA0#
CASA1#

22
22

WEA0#
WEA1#

WEA0#
WEA1#

22

CSA0#_0

CSA0#_0

22

CSA1#_0

CSA1#_0

22
22

CKEA0
CKEA1

CKEA0
CKEA1

22
22

CLKA0
CLKA0#

CLKA0
CLKA0#

22
22

CLKA1
CLKA1#

22

CLKA1
CLKA1#
QSA#[7..0]

QSA#[7..0]

22

QSA[7..0]

22

DQMA#[7..0]

22

MDA[63..0]

22

MAA[12..0]

22
22
22

A_BA0
A_BA1
A_BA2

QSA[7..0]
DQMA#[7..0]
MDA[63..0]
MAA[12..0]

C

A_BA0
A_BA1
A_BA2

support 1Gbit
VRAM ( 64M X 16 )

+1.8V

R76
100/F_4
MVREFD
+1.8V
B

C235
0.1U/10V_4

K27
J29
H30
H32
G29
F28
F32
F30
C30
F27
A28
C28
E27
G26
D26
F25
A25
C25
E25
D24
E23
F23
D22
F21
E21
D20
F19
A19
D18
F17
A17
C17
E17
D16
F15
A15
D14
F13
A13
C13
E11
A11
C11
F11
A9
C9
F9
D8
E7
A7
C7
F7
A5
E5
C3
E1
G7
G6
G1
G3
J6
J1
J3
J5

DQA_0
DQA_1
DQA_2
DQA_3
DQA_4
DQA_5
DQA_6
DQA_7
DQA_8
DQA_9
DQA_10
DQA_11
DQA_12
DQA_13
DQA_14
DQA_15
DQA_16
DQA_17
DQA_18
DQA_19
DQA_20
DQA_21
DQA_22
DQA_23
DQA_24
DQA_25
DQA_26
DQA_27
DQA_28
DQA_29
DQA_30
DQA_31
DQA_32
DQA_33
DQA_34
DQA_35
DQA_36
DQA_37
DQA_38
DQA_39
DQA_40
DQA_41
DQA_42
DQA_43
DQA_44
DQA_45
DQA_46
DQA_47
DQA_48
DQA_49
DQA_50
DQA_51
DQA_52
DQA_53
DQA_54
DQA_55
DQA_56
DQA_57
DQA_58
DQA_59
DQA_60
DQA_61
DQA_62
DQA_63

K26
J26
+1.8V

R77
100/F_4
R90
100/F_4

R78
R75
C259
0.1U/10V_4

4.7K_4
4.7K_4

K17
J20
H23
G23
G24
H24
J19
K19
J14
K14
J11
J13
H11
G11
J16
L15

DQMA_0
DQMA_1
DQMA_2
DQMA_3
DQMA_4
DQMA_5
DQMA_6
DQMA_7

E32
E30
A21
C21
E13
D12
E3
F4

RDQSA_0
RDQSA_1
RDQSA_2
RDQSA_3
RDQSA_4
RDQSA_5
RDQSA_6
RDQSA_7

H28
C27
A23
E19
E15
D10
D6
G5

QSA0
QSA1
QSA2
QSA3
QSA4
QSA5
QSA6
QSA7

W DQSA_0
W DQSA_1
W DQSA_2
W DQSA_3
W DQSA_4
W DQSA_5
W DQSA_6
W DQSA_7

H27
A27
C23
C19
C15
E9
C5
H4

QSA#0
QSA#1
QSA#2
QSA#3
QSA#4
QSA#5
QSA#6
QSA#7

ODTA0
ODTA1

L18
K16

CLKA0
CLKA0B

H26
H25

CLKA0
CLKA0#

CLKA1
CLKA1B

G9
H9

CLKA1
CLKA1#

RASA0B
RASA1B

G22
G17

RASA0#
RASA1#

CASA0B
CASA1B

G19
G16

CASA0#
CASA1#

CSA0B_0
CSA0B_1

H22
J22

CSA0#_0

CSA1B_0
CSA1B_1

G13
K13

CSA1#_0

MVREFDA
MVREFSA

CKEA0
CKEA1

K20
J17

CKEA0
CKEA1
WEA0#
WEA1#

R80
R426

*243/F_4
*243/F_4

J25
K7

NC_MEM_CALRN0
NC_MEM_CALRN1

W EA0B
W EA1B

G25
H10

R81
R79

243/F_4
*243/F_4

J8
K25

MEM_CALRP1
NC_MEM_CALRP0

AB16
G14
G20

L10

RSVD#1
RSVD#2
RSVD#3

DRAM_RST

K8
L7

CLKTESTA
CLKTESTB

MVREFS
C846
C847

0_4
0_4

MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
MAA12
A_BA2
A_BA0
A_BA1

MAA_0
MAA_1
MAA_2
MAA_3
MAA_4
MAA_5
MAA_6
MAA_7
MAA_8
MAA_9
MAA_10
MAA_11
MAA_12
MAA_13/BA2
MAA_14/BA0
MAA_15/BA1

MEMORY INTERFACE

D

MDA0
MDA1
MDA2
MDA3
MDA4
MDA5
MDA6
MDA7
MDA8
MDA9
MDA10
MDA11
MDA12
MDA13
MDA14
MDA15
MDA16
MDA17
MDA18
MDA19
MDA20
MDA21
MDA22
MDA23
MDA24
MDA25
MDA26
MDA27
MDA28
MDA29
MDA30
MDA31
MDA32
MDA33
MDA34
MDA35
MDA36
MDA37
MDA38
MDA39
MDA40
MDA41
MDA42
MDA43
MDA44
MDA45
MDA46
MDA47
MDA48
MDA49
MDA50
MDA51
MDA52
MDA53
MDA54
MDA55
MDA56
MDA57
MDA58
MDA59
MDA60
MDA61
MDA62
MDA63

ODTA0
ODTA1

22
22

D

DQMA#0
DQMA#1
DQMA#2
DQMA#3
DQMA#4
DQMA#5
DQMA#6
DQMA#7

C

ODTA0
ODTA1

B

T123

SI Add GND from Check list

R89
100/F_4
M92-S2

SI Add GND from Check list
Change MEMTEST to 240 1%
ohm to GND , AMD update

A

A

PROJECT : OP8
Quanta Computer Inc.
Size
Custom
NB5/RD2

Document Number

Date: Friday, March 20, 2009
5

4

3

2

Rev
1A

M7X/M8X/MEM_Interface
Sheet
1

21

of

42

5

4

DDR2 BGA
MEMORY

U5

D

A_BA0
A_BA1

L2
L3

MAA12
MAA11
MAA10
MAA9
MAA8
MAA7
MAA6
MAA5
MAA4
MAA3
MAA2
MAA1
MAA0

R2
P7
M2
P3
P8
P2
N7
N3
N8
N2
M7
M3
M8

CLKA0#
CLKA0

K8
J8

CKEA0

K2

CSA0#_0

L8

WEA0#

K3

RASA0#

K7

CASA0#

L7

DQMA#2
DQMA#1

BA0
BA1
A12
A11
A10/AP
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
CK
CK

K9

QSA2
QSA#2

F7
E8

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10

CKE

CS
WE
RAS

VDD1
VDD2
VDD3
VDD4
VDD5

CAS

F3
B3

ODTA0

DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0

LDM
UDM

VDDL
VSSDL

B9
B1
D9
D1
D3
D7
C2
C8
F9
F1
H9
H1
H3
H7
G2
G8

MDA9
MDA13
MDA10
MDA15
MDA14
MDA8
MDA12
MDA11
MDA17
MDA22
MDA16
MDA21
MDA23
MDA18
MDA20
MDA19

A9
C1
C3
C7
C9
E9
G1
G3
G7
G9

3

2

L2
L3

MAA12
MAA11
MAA10
MAA9
MAA8
MAA7
MAA6
MAA5
MAA4
MAA3
MAA2
MAA1
MAA0

R2
P7
M2
P3
P8
P2
N7
N3
N8
N2
M7
M3
M8

CLKA0#
CLKA0

K8
J8

CKEA0

K2

BA0
BA1

A1
E1
J9
M9
R1
J1
J7

CSA0#_0

L8

WEA0#

K3

RASA0#

K7

CASA0#

L7

DQMA#3
DQMA#0

F3
B3

CK
CK
CKE

CS
WE

K9

QSA3
QSA#3

F7
E8

QSA1
QSA#1

R97
4.99K/F_4
(SSTL-1.8) VREF = .5*VDDQ

M_VREF1

C283

C

A_BA2

R96
4.99K/F_4

0.1U/10V_4

Support 1Gbit
VRAM ( 64M X 16 )

VREF

A2
E2
L1
R3
R7
R8

+1.8V

VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9
VSSQ10

UDQS
UDQS

J2

QSA0
QSA#0

B7
A8

M_VREF2

J2

NC#A2
NC#E2
BA2
NC#R3
A15
A13

VSS1
VSS2
VSS3
VSS4
VSS5

A7
B2
B8
D2
D8
E7
F2
F8
H2
H8

+1.8V

R464
4.99K/F_4
(SSTL-1.8) VREF = .5*VDDQ

A3
E3
J3
N1
P9

CAS
LDM
UDM

VDDL
VSSDL

C367

C343
10U/6.3V_8

R462
4.99K/F_4

A_BA2
0.1U/10V_4

Support 1Gbit
VRAM ( 64M X 16 )

+1.8V

C371

C775

C771

C375

C374

1U/10V_4

1U/10V_4

1U/10V_4

1U/10V_4

1U/10V_4

C359
0.1U/10V_4

C378

C377

0.1U/10V_4

0.1U/10V_4

C743

LDQS
LDQS

UDQS
UDQS
VREF

L2
L3

MAA12
MAA11
MAA10
MAA9
MAA8
MAA7
MAA6
MAA5
MAA4
MAA3
MAA2
MAA1
MAA0

R2
P7
M2
P3
P8
P2
N7
N3
N8
N2
M7
M3
M8

CLKA1#
CLKA1

K8
J8

CKEA1

K2

VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9
VSSQ10

NC#A2
NC#E2
BA2
NC#R3
A15
A13

QSA[7..0]

21

QSA#[7..0]

A9
C1
C3
C7
C9
E9
G1
G3
G7
G9

21

MDA[63..0]

21

MAA[12..0]

21
21
21

A_BA0
A_BA1
A_BA2

QSA[7..0]
QSA#[7..0]
DQMA#[7..0]
MDA[63..0]
MAA[12..0]

A_BA0
A_BA1
A_BA2

D

+1.8V

A1
E1
J9
M9
R1

21

CLKA0

21

CLKA0#

CLKA0
CLKA0#
R149
56.2/F_4

R150
56.2/F_4

J1
J7
C773
C382

VSS1
VSS2
VSS3
VSS4
VSS5

470P/50V_4

A7
B2
B8
D2
D8
E7
F2
F8
H2
H8
A3
E3
J3
N1
P9

ODTA0

21

RASA0#

RASA0#

21

CASA0#

CASA0#

21

WEA0#

WEA0#

21

CSA0#_0

CSA0#_0

21

CKEA0

CKEA0

DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0

A12
A11
A10/AP
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0

B9
B1
D9
D1
D3
D7
C2
C8
F9
F1
H9
H1
H3
H7
G2
G8

C

C362

0.1U/10V_4

C750

C381

10U/6.3V_8

10U/6.3V_8

C373

C328

C331

C342

C742

1U/10V_4

1U/10V_4

1U/10V_4

1U/10V_4

1U/10V_4

C365

C341

C329

C322

C379

0.01U/16V_4
0.1U/10V_4

0.1U/10V_4

0.1U/10V_4

0.1U/10V_4

0.01U/16V_4

U4

BA0
BA1

ODTA0

21

HYB18T512161B2F-20

U26
A_BA0
A_BA1

21

21 DQMA#[7..0]

ODT

A2
E2
L1
R3
R7
R8

C779

HYB18T512161B2F-20

10U/6.3V_8

VDD1
VDD2
VDD3
VDD4
VDD5

MDA6
MDA0
MDA7
MDA1
MDA2
MDA5
MDA3
MDA4
MDA28
MDA25
MDA30
MDA27
MDA26
MDA29
MDA24
MDA31

B9
B1
D9
D1
D3
D7
C2
C8
F9
F1
H9
H1
H3
H7
G2
G8

0.1U/10V_4

LDQS
LDQS

B7
A8

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10

RAS

C372
ODTA0

DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0

A12
A11
A10/AP
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0

+1.8V

ODT

22

U27
A_BA0
A_BA1

0.1U/10V_4
+1.8V

1

MDA60
MDA59
MDA61
MDA58
MDA56
MDA62
MDA57
MDA63
MDA52
MDA50
MDA53
MDA49
MDA48
MDA54
MDA51
MDA55

A_BA0
A_BA1

L2
L3

MAA12
MAA11
MAA10
MAA9
MAA8
MAA7
MAA6
MAA5
MAA4
MAA3
MAA2
MAA1
MAA0

R2
P7
M2
P3
P8
P2
N7
N3
N8
N2
M7
M3
M8

CLKA1#
CLKA1

K8
J8

BA0
BA1

DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0

A12
A11
A10/AP
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0

B9
B1
D9
D1
D3
D7
C2
C8
F9
F1
H9
H1
H3
H7
G2
G8

MDA43
MDA47
MDA41
MDA46
MDA44
MDA42
MDA45
MDA40
MDA35
MDA37
MDA33
MDA38
MDA36
MDA32
MDA39
MDA34

21

CLKA1

21

CLKA1#

ODTA1

21

ODTA1

21

RASA1#

RASA1#

21

CASA1#

CASA1#

21

WEA1#

WEA1#

21

CSA1#_0

CSA1#_0

21

CKEA1

CKEA1

CLKA1
CLKA1#
R471
56.2/F_4

R470
56.2/F_4

B

B

CSA1#_0

L8

WEA1#

K3

RASA1#

K7

CASA1#

L7

DQMA#6
DQMA#7

F3
B3

ODTA1

K9

QSA6
QSA#6

F7
E8

QSA7
QSA#7

B7
A8

CK
CK

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10

CKE

CS
WE
RAS

VDD1
VDD2
VDD3
VDD4
VDD5

CAS
LDM
UDM

VDDL
VSSDL

A9
C1
C3
C7
C9
E9
G1
G3
G7
G9

CKEA1

CK
CK

K2

CKE

+1.8V

A1
E1
J9
M9
R1

CSA1#_0

L8

WEA1#

K3

RASA1#

K7

CASA1#

L7

DQMA#4
DQMA#5

F3
B3

CS
WE
RAS

ODTA1

ODT

VDD1
VDD2
VDD3
VDD4
VDD5

CAS
LDM
UDM

J1
J7
C290

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10

VDDL
VSSDL

K9

A9
C1
C3
C7
C9
E9
G1
G3
G7
G9

C786
470P/50V_4
+1.8V

A1
E1
J9
M9
R1
J1
J7
C376

ODT

0.1U/10V_4
+1.8V

R428
4.99K/F_4
M_VREF3

J2

(SSTL-1.8) VREF = .5*VDDQ

C744
A_BA2

R429
A

4.99K/F_4

0.1U/10V_4

Support 1Gbit
VRAM ( 64M X 16 )

A2
E2
L1
R3
R7
R8

LDQS
LDQS

VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9
VSSQ10

UDQS
UDQS
VREF
NC#A2
NC#E2
BA2
NC#R3
A15
A13

VSS1
VSS2
VSS3
VSS4
VSS5

0.1U/10V_4
+1.8V

A7
B2
B8
D2
D8
E7
F2
F8
H2
H8

R147

QSA4
QSA#4

F7
E8

QSA5
QSA#5

B7
A8

LDQS
LDQS

UDQS
UDQS

4.99K/F_4
M_VREF4

J2

VREF

(SSTL-1.8) VREF = .5*VDDQ

C364

A3
E3
J3
N1
P9

A_BA2

R148
4.99K/F_4

0.1U/10V_4

Support 1Gbit
VRAM ( 64M X 16 )

HYB18T512161B2F-20

VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9
VSSQ10

A2
E2
L1
R3
R7
R8

NC#A2
NC#E2
BA2
NC#R3
A15
A13

VSS1
VSS2
VSS3
VSS4
VSS5

A7
B2
B8
D2
D8
E7
F2
F8
H2
H8
A3
E3
J3
N1
P9

A

HYB18T512161B2F-20

+1.8V

DDR2 BGA MEMORY

+1.8V

C358

C289

10U/6.3V_8

10U/6.3V_8

C315

C741

C740

C739

1U/10V_4

1U/10V_4

1U/10V_4

1U/10V_4

C366
0.1U/10V_4

C749
0.1U/10V_4

C189

C369

0.1U/10V_4

0.1U/10V_4

C311
0.01U/16V_4

C361

C345

10U/6.3V_8

10U/6.3V_8

C284

C784

C783

C787

C785

1U/10V_4

1U/10V_4

1U/10V_4

1U/10V_4

1U/10V_4

C354
0.1U/10V_4

C344

C370

0.1U/10V_4

0.1U/10V_4

C317
0.1U/10V_4

PROJECT : OP8
Quanta Computer Inc.

C314
0.01U/16V_4
Size
C
NB5/RD2

Document Number

5

4

3

2

Rev
1A

M92/VRAM_A0,A1

Date: Friday, March 20, 2009
1

Sheet

22

of

42

4

5

6

7

1. If LCD connector near GPU, then place these series Resistors near GPU
2. If LCD connector near N/B, then place these series Resistors near N/B

+12VALW

3
1
3
1
3
1
1
3

4
2
4
2
4
2
2
4

*0_4P2R_4 TXUCLKOUT+
TXUCLKOUT*0_4P2R_4 TXUOUT0+
TXUOUT0*0_4P2R_4 TXUOUT1+
TXUOUT1*0_4P2R_4 TXUOUT2TXUOUT2+

R1

*4.7K_4

EDIDCLK

R2

*4.7K_4

EDIDDATA

R6
330K_6
+5VSUS

RP49 3
1
RP50 3
1
RP51 3
1
RP52 1
3

4
2
4
2
4
2
2
4

0_4P2R_4

19 EXT_TXUCLKOUT19 EXT_TXUCLKOUT+
19 EXT_TXUOUT0+
19 EXT_TXUOUT019 EXT_TXUOUT119 EXT_TXUOUT1+
19 EXT_TXUOUT219 EXT_TXUOUT2+

EXT_TXUCLKOUTEXT_TXUCLKOUT+
EXT_TXUOUT0+
EXT_TXUOUT0EXT_TXUOUT1EXT_TXUOUT1+
EXT_TXUOUT2EXT_TXUOUT2+

RP53 3
1
RP54 1
3
RP55 3
1
RP56 3
1

4
2
2
4
4
2
4
2

0_4P2R_4

0_4P2R_4
0_4P2R_4
0_4P2R_4

0_4P2R_4
0_4P2R_4
0_4P2R_4

3

1

22_8

2

1

Q2
2N7002E

R10
2.2K_4

TXLCLKOUTTXLCLKOUT+
TXLOUT0TXLOUT0+
TXLOUT1TXLOUT1+
TXLOUT2+
TXLOUT2-

+3V_DELAY

R420

4.7K_4

EDIDCLK

R418

4.7K_4

EDIDDATA

A

R3

C11
0.1U/10V_4

LCDDISCHG

LCDON#

Q3
2N7002E

2

1

EXT_TXLCLKOUTEXT_TXLCLKOUT+
EXT_TXLOUT0EXT_TXLOUT0+
EXT_TXLOUT1EXT_TXLOUT1+
EXT_TXLOUT2+
EXT_TXLOUT2-

+3VLCD

2

OPTION SIGNAL FROM M92 to LVDS for discrete
19 EXT_TXLCLKOUT19 EXT_TXLCLKOUT+
19 EXT_TXLOUT019 EXT_TXLOUT0+
19 EXT_TXLOUT119 EXT_TXLOUT1+
19 EXT_TXLOUT2+
19 EXT_TXLOUT2-

N-MOS,5.8A
Q1
AO3404

1

RP8

2
Q4
PDTC144EU

3

RP7

23

2

100K/F_4

10,19 DISP_ON

B

LCDONG

R7
RP6

AO3404 ID
current
5.8A

1

RP5

+3V

2

LB_CLK
LB_CLK#
LB_DATAP0
LB_DATAN0
LB_DATAP1
LB_DATAN1
LB_DATAN2
LB_DATAP2

RP4

*0_4P2R_4 TXLCLKOUT+
TXLCLKOUT*0_4P2R_4 TXLOUT0+
TXLOUT0*0_4P2R_4 TXLOUT1+
TXLOUT1*0_4P2R_4 TXLOUT2+
TXLOUT2-

C10
0.1U/10V_4

3

LB_CLK
LB_CLK#
LB_DATAP0
LB_DATAN0
LB_DATAP1
LB_DATAN1
LB_DATAN2
LB_DATAP2

RP3

4
2
4
2
4
2
4
2

2

10
10
10
10
10
10
10
10

RP2

3
1
3
1
3
1
3
1

1

RP1

1

LA_CLK
LA_CLK#
LA_DATAP0
LA_DATAN0
LA_DATAP1
LA_DATAN1
LA_DATAP2
LA_DATAN2

1

A

LA_CLK
LA_CLK#
LA_DATAP0
LA_DATAN0
LA_DATAP1
LA_DATAN1
LA_DATAP2
LA_DATAN2

+3V

2

OPTION SIGNAL FROM NB to LVDS for UMA
10
10
10
10
10
10
10
10

8

TXUCLKOUTTXUCLKOUT+
TXUOUT0+
TXUOUT0TXUOUT1TXUOUT1+
TXUOUT2TXUOUT2+

+3VLCD_CON

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40

+3V
L2
PBY201209T-4A_8

+3VLCD

C6
C2
C3

10,18 EDIDCLK
10,18 EDIDDATA

+3VLCD_CON
10U/6.3V_8
*0.1U/10V_4
0.01U/16V_4

C4
1000P/50V_4

TXLOUT0TXLOUT0+
TXLOUT1TXLOUT1+

+1.8V

C849

0.1U/10V_4

+VGA_CORE

+1.8V

C854

0.1U/10V_4

+VGA_CORE

TXLOUT2TXLOUT2+
TXLCLKOUTTXLCLKOUT+
D1
2

PN_BLON

SI Add for EMI
+3VPCU
LVDS_BLON

10,18 LVDS_BLON

R12

CH501H-40PT
BLONCON
1

R13

R11

LCD_BK

LCD_BK

LID_EC#

2

TXUOUT0TXUOUT0+

100K/F_4

TXUOUT1TXUOUT1+

LID_EC#

31,32

HWPG

32,34,35,37,38

TXUOUT2TXUOUT2+

3
1

3
12

2

13
USBP2+
13
USBP2+3.9V-CAMARA

Del R21 and Pull hi R259 to
+3VS5, no-stuff Q5, add D7
to HWPG on PV

1

*PDTC144EU

TXUCLKOUTTXUCLKOUT+

*WCM-2012-900T(400mA)

D2
BAT54A

Q5

C

22P/50V_4

33K_6

1K/F_4
PN_BLON

C16

L1 4
1

USBP2+
USBP2-

3
2

VADJ1
BLONCON

+VIN_BLIGHT
C14
.01U/16V_4

C15
*4.7U/6.3V_6

+3.9V-CAMARA

G_0

3

B

G_1

G_2

G_3

G_4
C

G_5

2

3

1

CN1
GS12401-1011-9F

+5V
U1

+3V

3
C842
1
2

PWM_VADJ

5

U33

C17

4
PWM_VADJ

+VIN_BLIGHT

4

1

R1

SHDN

1U/10V_4

2
R524

1K_4

2
C9

FBM2125 HM330-T(4A,0.015)_8

C843
R9
*215K/F_4

4.7U/6.3V_6

C13
0.1U/50V_6

C1
0.01U/50V_4

C5
0.1U/50V_6

C12
*10U/25V_12

C7
0.1U/50V_6

C8

GND

SET

5

AT5231H-3.9KER

TC7SH08FU
*4.7U/6.3V_6

0.01U/50V_4

R2

D

R5

L3

VADJ1

1
3

32

DPST_PWM

VOUT

+VIN

0.047U/10V
10,19 DPST_PWM

VIN

R8
*100K/F_4

D

*0_4

PROJECT : OP8
Quanta Computer Inc.
Size
Custom

SI add U33,R524,C842 for Vari bright function
NB5/RD2

Document Number

Date: Friday, March 20, 2009
1

2

3

4

5

6

7

Rev
1A

LCD CONN
Sheet

23
8

of

42

5

4

3

CRT PORT

D

2

+5V

1

FUSE1A6V_POLY

CRT_R

L20

BLM18BA470SN1(47,300MA)_6

CRT_R1

CRT_G

L19

BLM18BA470SN1(47,300MA)_6

CRT_G1

CRT_B

L15

BLM18BA470SN1(47,300MA)_6

CRT_B1

R57

R48

R45

24

40 MIL

+5VCRT

16

R57 for UAM use 140 ohm
for DIS use 150 ohm (AMD)

40 mils

C122

C95

1

C661
0.1U/10V_4

+5VCRT
F1

2

C77

C76

C86

6
1
7
2
8
3
9
4
10
5

C108

+3V

11

D8

12

2

15
D7

150/F_4

150/F_4 150/F_4

5.6P/50V_6

5.6P/50V_6

5.6P/50V_6

5.6P/50V_6

5.6P/50V_6

5.6P/50V_6

0.1U/10V_4

17

R32

*0_4/S

CRTDDCCLK2

PR_VSYNC

R38

33_4

CRTVSYNC

PR_HSYNC

R391

33_4

CRTHSYNC

R398

*0_4/S

CRTDDCDAT2

2

+5V

*BAV99W

1

4

2
C50

AHCT1G125DCH

C60

C666

C697
D5

*470P/50V_4

1

5
U21

*47P/50V_4

*47P/50V_4

*47P/50V_4

*BAV99W
C

1
2

4

D21

+3V

R377
R375

4.7K_4

+3V

*BAV99W

1

CRTHSYNC

3

*4.7K_4

2

+3V_DELAY

2
DDCCLK

DDCCLK

1

3
D22
Q37
2N7002E

+3V_DELAY
+3V

10,18 DDCDATA

R382
R381
DDCDATA

4.7K_4

DDCCLK2

1

DDCDAT2

2

*BAV99W

*4.7K_4

1

DDCDAT2

3

+3V

2

follow AMD
reference
schematic change
for reduce
leakage to VDDR310,18
BUS

CRTVSYNC

3

AHCT1G125DCH

2

10,18,19 HSYNC_COM

DDCCLK2

3

2

C

CRT_B1

3

U20
10,18,19 VSYNC_COM

*BAV99W

1

D4

1

5

C655

2
D6

+5V

CRT_G1

3
CRT CONN
CN16

close conn
within 600mils

CRT_R
CRT_G
CRT_B

CRT_R
CRT_G
CRT_B

*BAV99W

1

EMI

10,18
10,18
10,18

CRT_R1

3

14

D

*BAV99W

1

13

3
Q40
2N7002E
R27
6.81K_4

R399
6.81K_4

B

B

+5VCRT

+5VCRT

2

CH501H-40PT

1

+5V_CRT2

D20

A

A

PROJECT : OP8
Quanta Computer Inc.
Size
Custom
NB5/RD2

Document Number

Rev
1A

CRT

Date: Friday, March 20, 2009
5

4

3

2

Sheet
1

24

of

42

5

4

3

2

1

26

HDMI HPD SENSE
+3V

+3V_DELAYUMA

use +3V for the detect pin
Dis use +3V_DELAY for the detect pin

R513
*0_4

R514
0_4
Q45
MMBT3904-7-F

3

R118

D

2

From RS780M

9 C_PEG_TX#15
9 C_PEG_TX15
9 C_PEG_TX#14
9 C_PEG_TX14
9 C_PEG_TX#13
9 C_PEG_TX13
9 C_PEG_TX#12
9 C_PEG_TX12

for Layout
concern
,placement close
north bridge

for Layout
concern
,placement close
HDMI conn

C_PEG_TX#15 C347
C_PEG_TX15 C346

*0.1U/10V_4 TX2_HDMI-L
*0.1U/10V_4 TX2_HDMI+L

C_PEG_TX#14 C352
C_PEG_TX14 C353

*0.1U/10V_4 TX1_HDMI-L
*0.1U/10V_4 TX1_HDMI+L

C_PEG_TX#13 C351
C_PEG_TX13 C350

*0.1U/10V_4 TX0_HDMI-L
*0.1U/10V_4 TX0_HDMI+L

C_PEG_TX#12 C348
C_PEG_TX12 C349

*0.1U/10V_4 TXC_HDMI-L
*0.1U/10V_4 TXC_HDMI+L

RP41
TX2_HDMI+L 3
TX2_HDMI-L
1
RP40
TX1_HDMI-L 3
TX1_HDMI+L 1
RP39
TX0_HDMI+L 3
TX0_HDMI-L
1
RP38
TXC_HDMI-L 3
TXC_HDMI+L 1

HDMI_DET_R

1

UMA/DISCRETE select for HDMI

SI Change to 200K for detect pin

D

HDMI_DET
200K/F_4

10,18 TMDS_HPD

R127
200K/F_4

R466
10K/F_4

4 *0_4P2R_4 TX2_HDMI+
TX2_HDMI2
4 *0_4P2R_4 TX1_HDMITX1_HDMI+
2
4 *0_4P2R_4 TX0_HDMI+
TX0_HDMI2
4 *0_4P2R_4 TXC_HDMITXC_HDMI+
2

UMA AND DISCRETE HDMI I2C SELECT
Close to HDMI Connector
*0_4P2R_4

From M92-S2
18 TX1_HDMI_L18 TX1_HDMI_L+
18 TX0_HDMI_L18 TX0_HDMI_L+
18 TXC_HDMI_L18 TXC_HDMI_L+

C789
C788

0.1U/10V_4
0.1U/10V_4

TX2_HDMITX2_HDMI+

TX1_HDMI_LTX1_HDMI_L+

C781
C782

0.1U/10V_4
0.1U/10V_4

TX1_HDMITX1_HDMI+

TX0_HDMI_LTX0_HDMI_L+

C780
C778

0.1U/10V_4
0.1U/10V_4

TX0_HDMITX0_HDMI+

TXC_HDMI_LTXC_HDMI_L+

C774
C777

0.1U/10V_4
0.1U/10V_4

TXC_HDMITXC_HDMI+

for Layout
concern
,placement close
HDMI conn

+3V_DELAY

R442

1
B

499/F_4

TX2_HDMI+

R473

499/F_4

TX2_HDMI-

R469

499/F_4

TX1_HDMI+

+5V
R403
4.7K_4

R468

499/F_4

TX1_HDMI-

R465

499/F_4

TX0_HDMI+

R467

499/F_4

TX0_HDMI-

R461

499/F_4

TXC_HDMI+

R460

499/F_4

TXC_HDMI-

2
100K/F_4

Q59, Q60 Change
2N7002 to
FDV301N for AMD
on PV

C

R407
*4.7K_4

3HDMI_SCLK

1

HDMI_SCL
+3V_DELAY

UMA RS780M
朝 715 ohm CS17152FB17

+3V

HDMI_SDATA
HDMI_SCLK

+3V

DIS

+5V
R408
*4.7K_4

R404
4.7K_4

SI Change for DIS HDMI

Q41
2N7002E

2

3
1

Q44
2N7002E
2

R472

4
2

UMA

Discrete DDC4 is 5V
tolerance , the MOSFET
level shifter no need
UMA DDC is 3V
tolerance,the MOSFET
level shifter is need
18

+5V

RP57 3
1

10 HDMI_DDC_DATA
10 HDMI_DDC_CLK

2

C

18 TX2_HDMI_L18 TX2_HDMI_L+

TX2_HDMI_LTX2_HDMI_L+

DIS M92-S
朝 499 ohm CS14992FB24

18

1

HDMI_SDA

Close to HDMI Connector

3

HDMI_SDATA

Q42
2N7002E
B

HDMI PORT
+5V_HDMVCC

+5V_HDMVCC

TX2_HDMITX1_HDMI+

2

2

TX2_HDMI+

TX1_HDMITX0_HDMI+
TX0_HDMITXC_HDMI+

1

CH501H-40PT

D24
CH501H-40PT

1

D23

TXC_HDMIR446
2K_4
HDMI_SCLK

R454
2K_4
HDMI_SDATA

HDMI_SCLK
HDMI_SDATA

L29 1
L30 1

2 *0_6/S
2 *0_6/S

HDMISCL
HDMISDA
+5V_HDMVCC

+5V

A

FUSE1A6V_POLY
2
1
F2
C772

*0.1U/10V_4

CN21

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19

SHELL1
D2+SHELL3
D2 Shield
D2D1+
D1 Shield
D1D0+
D0 Shield
D0CK+
CK Shield
CKCE Remote
NC
DDC CLK
DDC DATA
GND
+5V
HP DET
SHELL4
SHELL2

20
22

23
21
A

HDMI CONN

HDMI_DET

PROJECT : OP8
Quanta Computer Inc.
Size
Custom
NB5/RD2

Document Number

Rev
1A

HDMI

Date: Friday, March 20, 2009
5

4

3

2

Sheet
1

25

of

42

8

7

6

5

SI remove R350

CLK_48M_CR

3

R250

100K/F_4

2

13
14
15
16
17
18
19
20
21
22
23
24

XD_CD#
SP2
SD_CD#
SP4
R323

6.19K/F_4

RREF

2

4
5

13 USBP313 USBP3+

1

CF_CD#
GPIO0
CF_D10
CF_D9
CF_D2
CF_D8/SM_CD#
CF_D1/XD_CD#
CF_D0/SM_WPM#/SD_WP
CF_A0/SD_CD#
CF_DMACK#
CF_A1/XD_D4
CF_DMARQ
RREF

XD_CLE/CF_D3
XD_CE#/CF_D11
XD_ALE/CF_D4

43
42
41

SP19
SP18
SP17

SD_DAT2/XD_RE#/CF_D12
SD_DAT3/XD_WE#/CF_D5
XD_RDY/CF_D13
SD_DAT4/XD_WP#/CF_D6

40
39
38
37

SP16
SP15
SP14
SP13

SD_CMD
SD_DAT5/XD_D0/CF_D14
SD_CLK/XD_D1/MS_CLK/CF_D7
SD_DAT6/XD_D7/MS_D3/CF_D15
CF_CS0#
MS_INS#/CF_IORD#
SD_DAT7/XD_D2/MS_D2/CF_IOWR#
SD_DAT0/XD_D6/MS_D0/CF_RST#
SD_DAT1/XD_D3/MS_D1/CF_IORDY
XD_D5/MS_BS/CF_A2

36
35
34
31
30
29
28
27
26
25

SD_CMD_R
SP12
SP11
SP10

DM
DP

AV_PLL_IN

XTLO
VREG_OUT
5V_IN
A3V3_ IN
D3V3_ IN

1

Y6
XTLI

47

*5.6P/50V_4

For 5158

R254

*0_4/S

Note:
SD/MMC

MS

SP7
SP6
SP8
SP16
SP5
SP15
SP11

XD

SP1
SP2
SP3
SP4
SP5
SP6
SP7
SP8
SP9
SP10
SP11
SP12
SP13
SP14
SP15
SP16
SP17
SP18
SP19

For 5158E

AL005158B10 -->RTS5158E
AL005158B00 -->RTS5158

MS_CD#
SP8
SP7
SP6
SP5

XD_CD#
SD_WP
SD_CD#
SD_DAT1
MS_BS
MS_D1
MS_D0
MS_D2
MS_INS#
MS_D3
MS_SCLK

SD_DAT0
SD_DAT7
SD_DAT6
SD_CLK
SD_DAT5
SD_DAT4
SD_DAT3
SD_DAT2

XD_D4
XD_D5
XD_D3
XD_D6
XD_D2

R280
R268
R252
R343
R259
R342
R314
R523
R255
R507
R345
R253
R291
R353
R322
R354
R344
R331

SP2
SP13
SP19
SP4
SP10
SP14
SP12
SP17
SP18
SD_CMD_R

XD_D7
XD_D1
XD_D0
XD_WP#
XD_R/B#
XD_WE#
XD_RE#
XD_ALE
XD_CE#
XD_CLE

MS-D0_SD-D0_XD-D6
MS-D1_XD-D3_SD_D1
MS-D2_XD-D2
XD-RE#_SD-D2
MS-BS_XD-D5
SD-D3_XD-WE
SD-CLK
MS-CLK
SD-WP
XD-WP#
XD-CLE
XD-D4
MS-D3_XD-D7
XD-RB#
XD-D0
XD-ALE
XD-CE#
SD-CMD

*0_4/S
*0_4/S
*0_4/S
*0_4/S
*0_4/S
*0_4/S
*0_4/S
*0_4/S
*0_4/S
*0_4/S
*0_4/S
*0_4/S
*0_4/S
*0_4/S
*0_4/S
*0_4/S
*0_4/S
*0_4/S

25
D

1
C581
0.1U/10V_4

C530

XTLI

10
8
3
33

SP11

VREG

R300
+3VSUS_RTS
C558
0.1U/10V_4

0.1U/10V_4

C552
0.1U/10V_4

1 *0_8/S

2

Can not more than 30p

C572
*27P/50V_4

+3VSUS

C557
4.7U/6.3V_6

C568

BG612000717
D3V3_OUT
MODE_SEL

45

11

+3VSUS

0.1U/10V_4

MODE_SEL

C574

C514
4.7U/6.3V_6

C585
*47P/50V_4

A3V3_OUT

For 5158

CARD_3V3_OUT
AG33
AG_PLL
DGND2
DGND1

RST#

C518

6
46
32
12

C532

C534

5158_RST_R#

1

5158_RST_R# 13

RB501V-40

C526

0.1U/10V_4
1U/10V_4

0.1U/10V_4

0.1U/10V_4

0.1U/10V_4

0.1U/10V_4
Add diode for 5158E cardreader driver lost issue

1

1

1

1
1

1
1
1

1

1
1

1
1

1

1

1

1

B

H6
*H-C197D87P2

1

1
1

1
1

1
1

1

1

H25
*H-C315D118P2

H29
*h-c354d118p2

H7
*H-C197D87P2
H26
*H-O236X197D158X118P2

H8
*H-C67D67N

H5
*H-C55D55N

1

H27
*H-TC236BC118D118P2

H14
*h-tshebc315d118p2

H12
*H-TO10X13BC8D8P2

H20
*H-TO9X14BC8D3P2

H22
*H-C315D276P2

H9
*H-TE3-8X9-13BC8P2

H28
*h-c354d118p2

+VIN

H31
*h-c354d118p2

SD-CMD
SD-D3_XD-WE

H30
*h-tc354bs354d118p2

SD-CLK

H11
*H-O79X118D79X118

C851
0.1U/50V_6

PAD1
*SPAD-RE100X200NP

XD-RE#_SD-D2
SD_DAT1
MS-D0_SD-D0_XD-D6

H24
*H-TC315BC394D118P2

SD_CD#

H4
*H-C315D118P2

H19
*H-TC8BE8X7_5D3P2

SD-WP

1

1

1

1

1

1

1

1

H17
*H-C217D181P2

H13
*H-C217D181P2

H18
*H-C217D181P2

H16
*h-c307d181p2

H15
*H-C236D181P2

H10
*H-C236D181P2

TAI-SOL 144-2300001900

H45
*h-c91d91n

C850
0.1U/50V_6

1

Battery Hole
MS-CLK
MS-D3_XD-D7
MS_CD#
MS-D2_XD-D2
MS-D0_SD-D0_XD-D6

H44
*h-c118d118n

42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23

H3
*H-C315D118P2

+VIN

43

H21
*H-C315D118P2

GND
SD-WP
SD-GND1
SD-CD#
SD-GND2
SD-D2
SD-D1
SD-D0
SD-GND
SD-CLK
SD_VCC
SD-GND3
SD-CMD
SD-D3
MS-GND2
MS-VCC
MS-SCLK
MS-P-D3
MS-INS
MS-P-D2
MS-SDIO

H43
*spad-c157np

XD-GND1
XD-CD#
XD-R/B
XD-RE
XD-CE
XD-CLE
XD-ALE
XD-WE
XD-WP
XD-GND2
XD-D0
XD-D1
XD-D2
XD-D3
XD-D4
XD-D5
XD-D6
XD-D7
XD-VCC
MS-GND1
MS-BS
MS-D1

H40
*spad-op89-2

1
2
3
4
5
6
7
8
9
10
XD-D0
11
SP11
12
MS-D2_XD-D2
13
MS-D1_XD-D3_SD_D1 14
XD-D4
15
MS-BS_XD-D5
16
MS-D0_SD-D0_XD-D6 17
MS-D3_XD-D7
18
19
20
MS-BS_XD-D5
21
MS-D1_XD-D3_SD_D1 22
XD_CD#
XD-RB#
XD-RE#_SD-D2
XD-CE#
XD-CLE
XD-ALE
SD-D3_XD-WE
XD-WP#

H2
*H-TC236BC118D118P2

CN24

H37
*spad-re142x339np

R509
*10K/F_4
B

H23
*H-TE8X9BC8D3P2

H42
*spad-c157np

C852
0.1U/50V_6

H1
*h-tr472bc315d118p2

H39
*spad-c134np

H41
*spad-c157np

H36
*spad-c157np

H38
*spad-c157np

+3VCARD

H35
*spad-c157np

+VIN

+3VCARD

H34
*spad-re63x213np

4 IN1 CARD READER
XD,SD,MS/MSP

1

RTS5159

1U/10V_4

+3VCARD

2

C573

C538

1

If SD_DAT1 connect to
SP4 , MOD_SEL need to
let it to N.C

5158_RST# 44
C591

C

D19
5158_RST#

+3VCARD

1

100K/F_4

+3VCARD

+3VSUS

9

1

R326

7

1

C

1

R325
10K/04

SP4

SD_DAT1

1U/10V_4
48

*12MHz

R327
*270K_4
C609

*0_4

CLK_48M_CR

*5.6P/50V_4

2

C610

R273

U14

31 CARD_LED#

D

SP6

1

+3VSUS

for langth trace

1

2 CLK_48M_CR

+3VSUS

4

For 5158

For 5158E

+1.8V
C286
0.1U/10V_4

A

A

+3VCARD

1

1

1

1

1

1

1

H50
*SPAD-RE59X315NP-2

H49
*SPAD-RE59X315NP-1

CLOSE CONN

H48
*SPAD-RE98X298NP-2

C824
0.1U/10V_4

H47
*SPAD-RE98X298NP-1

C810
0.1U/10V_4

H46
*H-R103X67D103X67N

C829
0.1U/10V_4

H51
*h-tc315bc127d87p2

R481
150K/F_4

H52
*h-tc315bc127d87p2

+3VCARD
C828
2.2U/6.3V_6

VGA Hole

Add for EMI request

CPU Hole

PROJECT : OP8
Quanta Computer Inc.
Size
Custom
NB5/RD2

Document Number

7

6

5

4

3

2

Rev
1A

RTS5158 & CR SOCKET &HOLE

Date: Friday, March 20, 2009
8

+Vcore0

Sheet

26
1

of

42

A

B

C

D

L48

C527
10U/6.3V_8

+4.75VAVDD
C604
.1U/10V_4

C542
.1U/10V_4

10U/6.3V_8
C586

1

+3V_DVDD
C541
.1U/10V_4

C602
1U/6.3V_4

C584
4.7U/6.3V_6

C578

5

Vout

4

BYP

2

GND

1U/6.3V_4
C544

C583
.1U/10V_4

C535
.1U/10V_4

C603
*.1U/10V_4

10U/6.3V_8

27

+5V
+5V

U15

+3V
C543

2 *0_8

1

+4.75VAVDD

Close to Pin6

2

+3V_DVDD

E

AGND

1U/6.3V_4
AGND

Vin

1

EN

3

C550
.1U/10V_4

+5V
C548

TPS793475

C547
*.1U/10V_4

1U/6.3V_4

C536
10U/6.3V_8

C549
.047U/25V_4

AGND

3475_EN

R282

*10K/F_4

R283

10K/F_4

MAINON

20,32,35,38,39,40

+5V

R279

22_4

ACZ_SDIN0_ADC

28
29

17

EARPO_L

C804

PORTA_R

27

EARPO_R

C803

GPIO 7 / SPDIF OUT1
DMIC0 / GPIO1

+

1

AVDD

26

PORTB_L
PORTB_R
VREFOUT-B

100UF_16V

EARP_L

100UF_16V

EARP_R

30

32
31

EAPD#

SPDIF0
EAPD/GPIO0/SPDIF OUT 0 or 1

PCBEEP/Mono

DVSS

13
14
20

MIC1_L1
MIC1_R1
VREFOUT_B_L

C577
C587
R329
R318
C599

AGND

AGND

SENSE_A

15
16
21

HP-L
HP-R
INT_MIC_L1
INT_MIC_R1
VREFOUT_C_L

C592
C600
R346
C601

C613

28
28TO

9
C560

.1U/10V_4

TO Audio Jack MIC

AGND

Internal Speakers

AGND

C559
R293
R289

R306
23
SENSE_B

AGND

.1U/10V_4
10K/F_4
47K_4

+4.75VAVDD

2.49K/F_4

R308
R307
C570
R341

39.2K/F_4
20K/F_4
1000P/50V_4
100K/F_4

C606

1000P/50V_4

ACZ_SPKR 13,28

SA_A#
SA_B#

EARP_L
EARP_R
SA_A#
SA_B#
EXT_MIC_L

C522
*180P/50V_4

EXT_MIC_R
C523
MBATLED0_R
SATA_LED_R

*180P/50V_4
C524
C525
*180P/50V_4 *180P/50V_4

2 *1000P/50V_4

1

1
2

CN12

CN27

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

AGND

TO Internal Mic

CN4
88266-020L

From EMI request

+3VPCU
+3VPCU

32

MBATLED0#

1

3

MBATLED0_R

Q30
DDTC114TUA
+3V

31,32 PWR_LED#

1

3

PWR_LED_R

Q32
DDTC114TUA

HEADER 15_11

*HEADER 15_11
14

SATA_LED#

1

3
Q31
DDTC114TUA

AGND

Co-layout

SATA_LED_R

+ 1

PROJECT : OP8
Quanta Computer Inc.

2 -

Single Color ,Right angle
LTW-110TLA
Size
Custom

TO Headphone jack

NB5/RD2

Document Number

B

C

D

Rev
1A

Azalia 92HD75B2X5

Date: Friday, March 20, 2009
A

1

AGND

C841
1000P/50V_4

TO AUDIO/B CON.

AGND
AGND

*0_6

3
AGND

AGND

for EMI

*0_6

R295

2

+5V

*0_6

R340

2

PWR_LED_R

*0_6

R311

AGND

2

0.1U/10V_4

*0_6

R299

+4.75VAVDD

1U/6.3V_4

AGND

C531

*0_6

R315

C605

AGND

+5VPCU

*0_6

R301

C567

SA_A# -->EXT Ear Phone
SA_B# -->EXT MIC

AGND

INT_MIC_R
10U/6.3V_8

R351
INT_MIC_R

2.2U/6.3V_6
2.2U/6.3V_6
2.2K_4
1U/6.3V_4

SENSE_A

10

Audio JACK: Normal Open
SA_A# -->EXT HP
SA_B# -->EXT MIC
Sense_B -->INT MIC

EXT_MIC_L
EXT_MIC_R

2.2U/6.3V_6
2.2U/6.3V_6
4.7K_4
4.7K_4
1U/6.3V_4

11
12

19
22

SENSE_B

24
25

VREF_FLT
CAP2_AU

DAP
33

IDT 92HD75B2X5

VREFFILT
CAP2

*5.11K/F_4

Reserve for EAPD#

1

PORTE_L
PORTE_R

AVSS

R298

PORTC_L
PORTC_R
VREFOUT-C

18

+3V_DVDD

DMIC_CLK

PORT-D_L
PORT-D_R

Analog

C545
*27P/50V_4

FOR EMI

28

Digital

C546
*27P/50V_4

AGND SHIELD TO Headphone jack
AGND SHIELD

ACZ_SDIN0_ADC

4

BIT_CLK_AUDIO

SDO
BITCLK
SDI_CODEC
SYNC
RESET#

AGND SHIELD
PORTA_L

+

2
3
5
7
8

DVDD_LV

13 ACZ_SDOUT_AUDIO
13 BIT_CLK_AUDIO
13
ACZ_SDIN0
13 ACZ_SYNC_AUDIO
13 ACZ_RST#_AUDIO

DVDD_CORE

6

AGND
U16

Sheet
E

27

of

42

1

2

3

4

5

6

7

8

AUDIO AMPLIFIER
+5VAMP
U17

L_SPK+

L_SPK-1

L7

FBMA-11-160808-601A10T

L_SPK-

SI-2 modified -C19
for EMI
*470P/50V_4
suggestion

AGND

INT. SPEAKER

A

Vrms = Vpp / 2 √2
Power =

C20
*470P/50V_4

(Vrms) 2/ R

QT8 speaker -- 3.2ohm / 2W

R309
+3V

100K/F_4

+5VAMP

90K

AUDIO_G0

0

1

10dB

70K

AUDIO_G1

1

0

15.6dB

45K

1

1

21.6dB

25K

+5V
R302

2

R332
R310

1K/F_4

*1K/F_4

VOLMUTE#

2

27

EAPD#

1

1

1

3

C590
10U/6.3V_8

C596
0.1U/10V_4

C589
0.1U/10V_4

C595
0.047U/25V_4

D18
BAT54A

*0_6

R522

*0_6

R352

*0_6

R355

*0_6

AGND

AGND

B

*0_6

R521

499K/F_4

1

R324

32

R520

*0_6/S

1

6dB

2

0

2

0

1

*100K/F_4

RIN

FBMA-11-160808-601A10T

2

R334

AV

AGND

1

GAIN1

AGND

2

GAIN0

AGND

L5

2

6017A2 Gain Table

4
3
2
1

C18
*470P/50V_4

L_SPK+2

100P/50V_4

AGND

100P/50V_4

TPA6017A2/FAN7031/LM4874

100P/50V_4

GAIN0
GAIN1

12
21
1
11
13
20

C597

BYPASS

2
3

28

CN2

INT SPEAKER CONN

100P/50V_4

+5VAMP

10

NC
EPAD
GND1
GND2
GND3
GND4

R_SPK-

19
C582

AMP_BYPASS

AUDIO_G0
AUDIO_G1

SHUTDOW N

R_SPK+

FBMA-11-160808-601A10T

DC impedance 0.35ohm

C598

1 0.47U/10V_6

LIN+
RIN+

FBMA-11-160808-601A10T

L6

C21

C575

C608 2

AGND

9
7

L4

R_SPK-3

*470P/50V_4

2

PC_BEEP

LINRIN-

4
8

1

A

5
17

LOUT+
LOUT-

2

C_SPKR_L
C_SPKR_R

1 .047U/16V_6
1 .047U/16V_6

1

C593 2
C588 2

2

HP-L
HP-R

HP_L_C
HP_R_C

18
14

1

27
27

0_4
0_4

ROUT+
ROUT-

2

Change to 0.047u
R333
R330

PVDD1
PVDD2
VDD

1

6
15
16

R_SPK+4

R386, R310 change
to SHORT-1A on PV

AGND

B

+5V

PC-BEEP

G955 /FON
signal have
internal
pull Hi to
VIN , R420
maybe can
remove

CPU FAN
+5VAMP
C594 *.1U/16V/04

+3V

AGND

C611

U18
*NC7SZ86

TO AMP

*0.1UF/06

*1K/04
R349
*1K/04

32

20 mil

C612
.047U/16V_6

C607
.047U/16V_6

C767

U23

2
1
4

FAN1ON

FAN1SIG

FANPWR = 1.6*VSET

VIN

VO
GND
/FON GND
GND
VSET GND

3
5
6
7
8

+5VFAN1

G995

CN20
+5VFAN1
C768

AGND

1
2
3

1
2
3
FAN CONN

AGND
*0_4

2.2U/6.3V_6

Change to 0.047u

1

0.1U/10V_4
C

AMP_GND

H32
MBZR1005014

H33
MBZR1005014

Modem CONN

1

R347

C

10K/F_4
FAN_SMBALERT#

32

PC_BEEP

1

3

TO CODE

R348

2

4

1

2
2

1

32

R421

R435
4.7K_6

5
KEY_BEEP

13,27 ACZ_SPKR

C731 1U/10V_4

+3V

MDC
CN26
13 ACZ_SDOUT_AUDIO_MDC
13 ACZ_SYNC_AUDIO_MDC
13 ACZ_SDIN1

1
3
5
7
9
11

ACZ_SDOUT_AUDIO_MDC
ACZ_SYNC_AUDIO_MDC
AC_SDIN1_MDC
R316
33_4
C576

*10P/50V_4

GND
REV
A_SDO
REV
GND
VCC
A_SYNC
GND
A_SDI
GND
A_RST# A_BCLK

C836
0.1U/10V_4

2
4
6
8
10
12

R511

*0_4/S

C835
1000P/50V_4

BIT_CLK_AUDIO_MDC

13

MDC CONN

For EMI

13 ACZ_RST#_AUDIO_MDC

D

C838
2.2U/6.3V_6

C837
*10P/50V_4

D

PROJECT : OP8
Quanta Computer Inc.
Size
Custom
NB5/RD2

Document Number

Date: Friday, March 20, 2009
1

2

3

4

5

6

7

Rev
1A

AMP_TPA6017/MDC1.5/CPU FAN
Sheet

28
8

of

42

5

4

BLUETOOTH

+3VPCU

3

2

+5VSUS

Q34
ME2303T1

2

C793
1U/10V_4

14

USB0PWR

8
7
6
5

C805
C797
*470P/50V_4

+

C798
0.1U/10V_4

G545B2PU8
(TPS2061D)

C614
0.1U/10V_4

Q33
PDTC144EU

2

BT_OFF#

OUT3
OUT2
OUT1
OC

3

3

D

VIN1
VIN2
EN
GND

100UF_16V

2
3
4
1

24mil

C616
10U/6.3V_8

CN13
BLUE TOOTH CONN
87213-0600-6P-L

C618
0.1U/10V_4
Check the GMT for the chip

BTCON_P1
BLUELED
USBP9USBP9+

6
5
4
3
2
1

D

AL000545017
IC(8P)G545B2P8U(MSOP-8) - 1.5A
AL000545000
IC OTHER(8P) G545A2P8U(MSOP-8) - 2A

1

BTV

29

80 mils (Iout=2A)

U29

1

R357
4.7K_4

1

LEFT SIDE USBX1 and E-SATA/USB COMBO

+3VSUS

T119
BLUELED 31,32,33
USBP913
USBP9+
13

USBP1+
USBP1-

1

1

2

2

C402
*Clamp-Diode_6

BTV

C395
*Clamp-Diode_6

SATA CD-ROM
C389
0.1U/10V_4

C

CN25

14
14

SATA_RXN1
SATA_RXP1
R478
1

1K/F_4
2

+5V

GND1
TXP
TXN
GND2
RXN
RXP
GND3

8
9
10
11
12
13

DP
+5V
+5V
MD
GND
GND

C

USB & ESATA

14
16

CN22

14
16
13
13

S7
P1

USBP1USBP1+

*WCM-2012-900T(400mA)
4
3
1
2
L36

15
17
P6
SATA ODD

USB0PWR
USBP1USBP1+

15
17

C418
*47P/50V_4

SATA_TXP1
SATA_TXN1

C796
*470P/50V_4

S1

C419
*47P/50V_4

14
14

1
2
3
4
5
6
7

14
14

SATA_TXP2
SATA_TXN2

14
14

SATA_RXN2
SATA_RXP2

1
2
3
4

C413
C414

0.01U/16V_4
0.01U/16V_4

SATA_TXP2_C
SATA_TXN2_C

C394
C392

0.01U/16V_4
0.01U/16V_4

SATA_RXN2_C
SATA_RXP2_C

5
6
7
8
9
10
11

GND
A+
AGND
BB+
GND

Shield

14

Shield

15

Shield

12

Shield

13

USB_ESATA_COMBO

Close to ESATA
CON from AMD
recommend

120 mils

USB Vcc
DD+
GND

+5V

B

C815
10U/6.3V_8

C821
0.1U/10V_4

C819
0.1U/10V_4

C822
0.1U/10V_4

C820
0.1U/10V_4

+5VSUS

CN23

SATA HDD

B

RIGHT SIDE USBX2
+3V_HDD1

A

GND1
TXP
TXN
GND2
RXN
RXP
GND3

1
2
3
4
5
6
7

3.3V
3.3V
3.3V
GND
GND
GND
5V
5V
5V
GND
RSVD
GND
12V
12V
12V

8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

SATA_RXN0 14
SATA_RXP0 14

C459
*10U/6.3V_8

+3V_HDD1

C444
*.1U/10V_4

13
13

USBP8+
USBP8-

13
13

USBP5+
USBP5-

+3V_HDD1

+3V

PCB footprint
BL123-10R-10P-L-QT6

+3V: 2 A(4 Pin)
Gnd : (5 Pin)

R240

C36
0.1U/10V_4

CN6
DUAL USB CONN

+5V: 2 A(4 Pin)
+5V_HDD1

+5VSUS

1
2
3
4
5
6
7
8
9
10

SATA_TXP0 14
SATA_TXN0 14

+5V_HDD1

*0_8

A

+5V_HDD1

R170

+5V

*0_8/S

C410
10U/6.3V_8

C415
4.7U/6.3V_6

C417
0.1U/10V_4

C407
10U/6.3V_8

PROJECT : OP8
Quanta Computer Inc.

LD2722F-SRLL6

Size
Custom
NB5/RD2

Document Number

Date: Friday, March 20, 2009
5

4

3

2

Rev
1A

BT/USBX3/ESATA/SATA ODD/HDD
Sheet
1

29

of

42

5

4

3

2

1

30

+3V_LAN
+DVDD12

+CTRL12DVDD

R237

*0_6/S

+EVDD12

Power trace Layout 寬 寬 > 30mil
+3VLANVCC

Power trace Layout 寬 寬 > 30mil
C397
.1U/10V_4

D

C457
.1U/10V_4

C409
.1U/10V_4

C469
C458
.1U/10V_4

C421
*.1U/10V_4

LANVCC
1.2W
364mA

C426
1U/10V_4

4.7U/6.3V_6

C436
.1U/10V_4

C463
.1U/10V_4

C462
.1U/10V_4
D

CLOSE to Pin 29,37
LAN-AGND

CLOSE to Pin 10, 13, 30, 36

+3V_A_LAN

close to pin 19

C398
.1U/10V_4
+CTRL12DVDD

XTAL2

C403
C472

10U/6.3V_8
.1U/10V_4

CLOSE to Pin 1

XTAL1

1
C429

2
Y3
25MHZ

2.49K/F_4 LANRSET

C416

33P/50V_4

10U/6.3V_8
.1U/10V_4

1
2
3
4
5
6
7
8
9
10
11
12

MDI1+
MDI1-

R199

48
47
46
45
44
43
42
41
40
39
38
37

R232

AVDD33
MDIP0
MDIN0
NC/FB12
MDIP1
MDIN1
RTL8103EL
GND1
NC/MDIP2
NC/MDIN2
DVDD12/AVDD12
NC/MDIP3
NC/MDIN3

DVDD12B
LED1/EESK
LED2/EEDI
LED3/EEDO
EECS
GND3
DVDD12A
VDD33A
ISOLATEB
PERSTB
LANW AKEB
CLKREQB

ISOLATEB

36
35
34
33
32
31
30
29
28
27
26
25

EESK_LED100#
EEDI_LED10#
EEDO
EECS

ISOLATEB
LAN_REST_R#
PCIE_WAKE#

+DVDD12

2
1
D16
*RB501V-40

R220
15K/F_4

+DVDD12
+3V_LAN
R235

*0_4

LAN_DISABLE#

13,32

if ISOLATEB pin
pull-low,the LAN
chip will not drive
it's PCI-E outputs
( excluding
PCIE_WAKE# pin )

CS
SK
DI
DO

2

VCC
DC
ORG
GND

8
7
6
5

C

C422
.1U/10V_4

+3V_LAN

Check the EEPROM for LAN

+3V_LAN

R210

*0_6/S

R209

*0_6/S

0.1U/10V_4
LAN-AGND

13
14
15
16
17
18
19
20
21
22
23
24

U32

DB modified to short-pad

2

12 LAN_PLTRST#

4

LAN_REST_R#

1
TC7SH08FU

PCIE_RXN2_LAN_L
PCIE_RXP2_LAN_L
PCIE_LAN_CLKP
PCIE_LAN_CLKN

1
2
3
4

*M93C46-WMN6TP
R196 1
3.6K_4

LAN_REST# 32
PCIE_WAKE# 13,33

LAN-AGND

9 PCIE_TXP2_LAN
9 PCIE_TXN2_LAN
2 PCIE_LAN_CLKP
2 PCIE_LAN_CLKN

+3V_LAN

U10
EECS
EESK_LED100#
EEDI_LED10#
EEDO

C839

+DVDD12

B

1K/F_4

100/F_4

R233
*1K/F_4

DVDD12
GND2
HSIP
HSIN
REFCLK_P
REFCLK_N
EVDD12
HSOP
HSON
EGND
NC/SMCLK
NC/SMDATA

+DVDD12

+3V

+3V_LAN

VCTRL12A/SROUT12
GND4
RSET
VCTR12DVDDSR
NC/VDDSR
NC/ENSWREG
CKTAL2
CKTAL1
NC/AVDD33
NC/LV_PLL
LED0
VDD33B

C

MDI0+
MDI0-

LAN_YLED#

Delete R261 and add D38 as current loss issue

U9

+3V_A_LAN

33P/50V_4

5

+CTRL12A
C400
C401

C471
C470

.1U/10V_4
.1U/10V_4

3

R177

C435
*.1U/10V_4

PCIE_RXN2_LAN 9
PCIE_RXP2_LAN 9

B

FOR EMI

+EVDD12

C764

.1U/10V_4

RJ45
CN19

+3V_LAN

R433

*0_6/S

LAN_GLED
LAN_GLED#

12
11

Add for EMI request
R534

*75/F_4
LAN_MX1-

LAN_Transformer
C853
*1000P/3KV_1808

U28
MDI0+

1

MDI0-

3

C794
.01U/16V_4

RD-

RX+

16

LAN_MX0+

CT

15

LAN_MCT0
LAN_MX0-

V_DAC_1

2

CT

RX-

14

MDI1+

6

TD+

TX-

9

LAN_MX1-

MDI1-

8

TD-

CMT

10

LAN_MCT1

TX+

11

LAN_MX1+

V_DAC_2

A

RD+

C795
.01U/16V_4

7

CT

LAN_MX1+
LAN_MX0LAN_MX0+

Bios need change
C792
LAN_MCT0_1
0.01U/100V_0603

C791
LAN_MCT0_2
0.01U/100V_0603

R475

R474

8
4
7
3
6
2
5
1

RX1RX1+
RX0TX1TX1+
RX0+
TX0TX0+

75/F_4

EEDI_LED10#

R515

*0_6

EESK_LED100#

R516

0_6

+3V_LAN

R425

*0_6/S

LAN_YLED
LAN_YLED#

10
9

13

LED_YEL_P
LED_YEL_N

RJ45_CONN
LAN_GLED#

C790
1000P/3KV_1808
LAN_YLED#

Fixed RJ45 Pin define (0829)

FOR EMI

Link

LAN_YLED#
C760

C728

*.01U/16V_4

*.01U/16V_4

PROJECT : OP8
Quanta Computer Inc.
Size
Custom

Document Number

3

2

Rev
1A

RTL8102EL/RJ45

Date: Friday, March 20, 2009
4

14

GND

.1U/10V_4

NB5/RD2
5

GND1

75/F_4

C733

NS681684

LED_GRE_P
LED_GRE_N

Sheet
1

30

of

42

A

5

4

3

NBSWON1#

C736

1

1

+PWLEDVCC

C738

2

0.1U/10V_4

D

+3VPCU

MY5
MY6
MY3
MY7

C297
C755
C309
C756

220P/50V_4
220P/50V_4
220P/50V_4
220P/50V_4

MY1
MY2
MY4
MY0

C287
C751
C312
C300

220P/50V_4
220P/50V_4
220P/50V_4
220P/50V_4

MX7
MX0
MX5
MX1

C303
C296
C301
C295

220P/50V_4
220P/50V_4
220P/50V_4
220P/50V_4

31

MY8
MY9
MY10
MY11

C310
C305
C752
C307

220P/50V_4
220P/50V_4
220P/50V_4
220P/50V_4

MX4
MX6
MX3
MX2

C304
C302
C298
C299

220P/50V_4
220P/50V_4
220P/50V_4
220P/50V_4

MY12
MY13
MY14
MY15

C754
C308
C753
C306

220P/50V_4
220P/50V_4
220P/50V_4
220P/50V_4

2

0.1U/10V_4

1

POWER BUTTON CONNECT

G2
*SHORT_ PAD1

C330
0.1U/10V_4

2

D

1. +3VPCU(LIDSWITCH PWR)

C737 0.1U/10V_4

2. PWR_LED#
3. GND

KEYBOARD PULL-UP

CN8

4. NumLED
1
2
3
4
5
6
7
8
9
10

PWR_LED_R#

+5VPCU

NUMLED_R#
2 39_6 +PWLEDVCC
WLSLED_ON_R#
WLSLED_OFF_R#
RF_SW#

R4271

23,32
LID_EC#
32
NBSWON1#

5. +5VPCU (PWRLED PWR)

RP37

10
9
8
7
6

MY15
MY11
MY13
MY3

6. WLSLED_ON#
7. WLSLED_OFF#

10K_10P8R

+3VPCU

9. LIDSWITCH

MY0
MY5
MY4
MY8

1
2
3
4
5

8. RF_SW#

CN7
DUAL USB CONN

MX1
MX7
MX6
MY9
MX4
MX5
MY0
MX2
MX3
MY5
MY1
MX0
MY2
MY4
MY7
MY8
MY6
MY3
MY12
MY13
MY14
MY11
MY10
MY15
MY16
MY17

RP58

10.POWERON#

10
9
8
7
6

MY9
MY1
MY2
MY7

+3V
+3VPCU

MY10
MY14
MY12
MY6

1
2
3
4
5
10K_10P8R

2

C

27,32 PWR_LED#

R530
10K/04

1

3

PWR_LED_R#

32

R432
R431

RF_SW#
32

Q17
DDTC114TUA

MY[0..17]

MY[0..17]

32

8.2K_4 MY16
8.2K_4 MY17

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26

C

MX[0..7]

MX[0..7]

GB1RF260-1253-8F
+3V

2

Change from 144 to 114 chip for leakage current
+3V

26

CARD_LED#

1

3

CARD_LED1_L

R356
CARD_LED1 1

2

2

3P WHITE LED
LED5
1

360/F_6
2
+5V

朝朝 LED1

2P WHITE
2CAP_LED

1

Q29
DDTC114TUA

32

2N7002E
Q14

+5V

1

CAPSLED#

CAP_LED_L

3

朝朝 LED2

R25

1

*2P WHITE
2CAP_LED

1

360/F_6
2
+5V

FOR 16"

Del R167

FOR 17.3"

Q6
DDTC114TUA
Dual Color ,Right angle

B

1

B

WLSLED_ON_R#
+3V

+3V

2

+3VPCU

3

2

R126
10K/F_4

DDTC114TUA

朝朝 (Amber) LED3

Q28
R518
10K/04

32

TP_LED1#

TP_LED1#

1

3

TP_LED1_R

32

TP_LED2#

TP_LED2#

1

3

TP_LED2_R

3

R517
10K/04
RB501V-40 D30

Q27
RF_LINK_R#

RF_LINK_R#

RF_LINK#

3

1

2
DDTC114TUA
Q16

1

Q15
2N7002E

R519

DDTC114TUA

+3V

Close LED1

TPLD3
TPLD4

R155
1
R160
1

FOR 16"

510_6
2
+5V
360/F_6
2
+5V

Amber

4

2

3

1

LED4

4

2 +

3

1 +

Anode

TPLD3

White

FOR 17.3"

TPLD4
*LED 4P WHITE/AMBER

2
C363

Q19
DDTC114TUA

2

29,32,33 BLUELED

TPLD3

Close LED5

3

0_4

*AVL5CS

C615

1

32,33

2

(White) LED 4P WHITE/AMBER
2

RF_LINK_1#

WLSLED_OFF_R#

2
3

32

1

4

CARD_LED1_L

CARD_LED1
*AVL5CS

C360
TP_LED1_R

TPLD4

1

*AVLC5S

A

C385

Close LED3

+3V

*AVLC5S
CAP_LED
*AVLC5S

DDTC114TUA
C41
CAP_LED_L

C356
*.1U/10V_4

Q18
32 NUMLED#

1

3

A

TPLD3

C40

2

NUMLED#

C383
CAP_LED
*AVLC5S

TP_LED2_R

PROJECT : OP8
Quanta Computer Inc.

TPLD4
*AVLC5S

NUMLED_R#

Close LED4

Close LED2

Size
Custom
NB5/RD2

Document Number

Date: Friday, March 20, 2009
5

4

3

2

Rev
1A

LED/KEYBOARD/SW_BOARD
Sheet
1

31

of

42

5

4

3

+3VPCU

12

MY0
MY1
MY2
MY3
MY4
MY5
MY6
MY7
MY8
MY9
MY10
MY11
MY12
MY13
MY14
MY15
MY16
MY17

39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
81
82

KSO0/GPIO20
KSO1/GPIO21
KSO2/GPIO22
KSO3/GPIO23
KSO4/GPIO24
KSO5/GPIO25
KSO6/GPIO26
KSO7/GPIO27
KSO8/GPIO28
KSO9/GPIO29
KSO10/GPIO2A
KSO11/GPIO2B
KSO12/GPIO2C
KSO13/GPIO2D
KSO14/GPIO2E
KSO15/GPIO2F
KSO16/GPIO48
KSO17/GPIO49

SLPBTN#
10K/F_4
ACIN
TPCLK
TPDATA

83
84
85
86
87
88

PSCLK1/GPIO4A
PSDAT1/GPIO4B
PSCLK2/GPIO4C
PSDAT2/GPIO4D
PSCLK3/GPIO4E
PSDAT3/GPIO4F

119
120
128
89
76
109
110
112
114
115
116
117
118

RD
WR
SELMEM/SPICS
SELIO/GPIO50
AD5/GPI43
D0/GPXD0
D1/GPXD1
D2/GPXD2
D3/GPXD3
D4/GPXD4
D5/GPXD5
D6/GPXD6
D7/GPXD7

97
98
99
100
101
102
103
104
105
106
107
108

A0/GPXA0
A1/GPXA1
A2/GPXA2
A3/GPXA3
A4/GPXA4
A5/GPXA5
A6/GPXA6
A7/GPXA7
A8/GPXA8
A9/GPXA9
A10/GPXA10
A11/GPXA11

BIOS_RD#
BIOS_WR#
BIOS_CS#
R200
*0_4/S

SERR#

RF_LINK#
BLUELED

31,33 RF_LINK#
T26
R226

B

*4.7K_4

BIOS_A0
SUSON
MAINON
LAN_POWER
S5_ON
VR2.5_ON

37,39
SUSON
20,27,35,38,39,40 MAINON
39 LAN_POWER
38,39
S5_ON
37
VR2.5_ON
13,30 LAN_DISABLE#
31
RF_LINK_1#
27
MBATLED0#
31
31

MBATLED0#
TP_LED1#
TP_LED2#

TP_LED1#
TP_LED2#

+5VSUS

3

PM_BATLOW1#

D13

TEMP_MBAT
AD_TYPE
AD_AIR
SYS_I

DA0/GPO3C
DA1/GPO3D
DA2/GPO3E
DA3/GPO3F

68
70
71
72

CC-SET

PW M1/GPIOF
PW M2/GPIO10

21
23

PWM_VADJ
KEY_BEEP (1KHz)

PWM_VADJ 23
KEY_BEEP 28

FANPW M1/GPIO12
FANPW M2/GPIO13
FANFB1/GPIO14
FANFB2/GPIO15

26
27
28
29

EC_ACLIM
FAN1SIG

CV-SET
40
EC_ACLIM 40
FAN1SIG 28

SCL1/GPIO44
SDA1/GPIO45
SCL2/GPIO46
SDA2/GPIO47

77
78
79
80

MBCLK
MBDATA
MBCLK2
MBDATA2

TEMP_MBAT 40

FAN1ON
D/C#

AD_AIR
SYS_I

40
40

CC-SET

40

FAN1ON
D/C#

28
40

MBCLK
MBDATA
MBCLK2
MBDATA2

GPIO4

6

SUSB#

GPIO7
GPIO8

14
15

HWPG
PM_BATLOW1#

GPIOA
GPIOB
GPIOC
GPIOD
GPIO11
GPIO16
GPIO17
GPIO18

16
17
18
19
25
30
31
32

SUSC#
RF_SW#

GPIO19
GPIO1A

34
36

NBSWON1#

+5V

TPCLK
TPDATA

VRON
NUMLED#

73
74
75
90
91
92
93
95
121
126
127

XCLKO

123

CRY2

XCLKI

122

CRY1

GND1
GND2
GND3
GND4
GND5
AGND

11
24
35
94
113
69

V18R

13

HWPG

23,34,35,37,38

SUSC#
RF_SW#

13
31

TP_L

RB500V-40

SWI#1

D10

D12

RB500V-40

2 *CH501H-40PT L-F

1

FOR 16"
TOUCH PAD ON/OFF
SW1
3
4
6

TP_R

FOR 16"

SW4
1K/F_4 TP_R_CONN 3
4
6

3
4
6

MY7

1
2
5

1
2
5

MX4

C617
0.1U/10V_4
TMG-533-S-V-TR

*TOUCH PAD EN SW

DB modified

TOUCH PAD L/R

B

LID_EC#
C453

23,31

Project Model GPIO42
OPX 16"
Low
OPX 17.3"
High

22P/50V_4
Y2
32.768KHZ

OP_FAN_SEL

R531

*10K/F_4

R532

10K/F_4
+3VPCU

GPIO42 control fan table
BLUELED

29,31,33 BLUELED
C454

+3VPCU

R227

100K/F_4

22P/50V_4
+3V

C512
0.1U/10V_4

R195

*10K/F_4

HWPG

R184

10K/F_4

NBSWON1#

U30
+3VPCU

BIOS_CS#
SPI_CLK
BIOS_WR#
BIOS_RD#

R183
R172
R175
R208
R166
R206

SCI#

13

PM_BATLOW# 13

D9
1SS355

DNBSWON# 13

KBSMI#

13

SWI#

13

10K/F_4
4.7K_4
4.7K_4
*8.2K_4
*8.2K_4
*8.2K_4

SLPBTN#
MBCLK
MBDATA
PM_BATLOW#
CLKRUN#
SERIRQ

+3VPCU

Change D12, D16 to RB500
for current loss

100/F_4

AD_ID

SB internal pull Hi
10k to 3v_s5

R163

47K_4

CE#
SCK
SI
SO

VDD

8

HOLD#

7

3

W P#

VSS

4

4

A

C386
2

PROJECT : OP8
Quanta Computer Inc.

3920_RST# 5,40
0.1U/10V_4
1

0.1U/10V_4

Size
Custom
NB5/RD2

3

10K/F_4
SPI_7P

EON AKE3GZP0Q00

3920_RST#

+3VPCU

10K/F_4 SPI_3P

R248

1
6
5
2

SST AKE5GFK0Z09 1M byte
WINBOND AKE3GFP0N08 SPI
BIOS
PME AKE3GZP0500

40

R167
24.3K/F_4

R228

33_4

MX25L8005

SB internal pull Hi 10k
to 3v_s5
R168

R229

Document Number

2

Rev
1A

KB3926/ROM/TP

Date: Friday, March 20, 2009
5

MX4

TOUCH PAD ON/OFF
FOR 17.3"
SW2

TMG-533-S-V-TR

R358

C

1
2
5

TMG-533-S-V-TR

1
2
5

C357
0.1U/10V_4

CAPSLED# 31
PWR_LED# 27,31
ECPWROK 5,16
RSMRST# 13
VOLMUTE# 28

C387
KBSMI#1

CN9
TOUCH PAD CONN

SW3
1K/F_4 TP_L_CONN 3
4
6

R145

12
11
10
9
8
7
6
5
4
3
2
1

TP_L
TP_R

MY7

TOUCH PAD L/R

D

PCB footprint
BL121-12R-12P-L-QT6

CN10
*BL123-04R-TAND

T24

2

D14

C319
*10P/50V_4

TOUCH PAD L/R FOR 17" only

SUSB#

AD_TYPE
DNBSWON#1

0.1U/10V_4

TPCLK-1
TPDATA-1
TP_LED1#
TP_LED2#

4
3
2
1

VGA thermal
system thermal

VRON
35,36
NUMLED# 31

OP_FAN_SEL
DNBSWON#1
CAPSLED#
PWR_LED#
ECPWROK
RSMRST#
VOLMUTE#
SPI_CLK
LID_EC#

0.1U/10V_4

C746

BLM18BA470SN1(47,300MA)_6
BLM18BA470SN1(47,300MA)_6

TP_L_CONN
TP_R_CONN

Battery charge/discharge
Cap button

40
40
5,18
5,18

reserved for H/W CIR
GPIO40
GPIO41
AD4/GPI42
GPIO52
GPIO53
GPIO54
GPIO55
GPIO56
GPIO57
GPIO58
GPIO59

C747

C320

NBSWON1# 31
LAN_REST# 30
EC_DEBUG1 33

SWI#1
KBSMI#1

L33
L31

*10P/50V_4

KB3926

2 CH501H-40PT

1

32

1U/10V_4

1

A

TPDATA

+5VSUS

63
64
65
66

C475
4.7U/6.3V_6

2 CH501H-40PT

1

TPCLK

4.7K_4

TOUCH PAD CONNECTOR

+3VPCU

D11

4.7K_4

R135

close conn

For KB3926 C version

SCI1#

R134

C390

25 mils

AD0/GPI38
AD1/GPI39
AD2/GPI3A
AD3/GPI3B

2
1

C451
0.1U/10V_4

Vin

+3VPCU_EC

Modify from RF LED control

124

GND

KSI0/GPIO30
KSI1/GPIO31
KSI2/GPIO32
KSI3/GPIO33
KSI4/GPIO34
KSI5/GPIO35
KSI6/GPIO36
KSI7/GPIO37

Vout

2

55
56
57
58
59
60
61
62

1

2

ACIN

MX0
MX1
MX2
MX3
MX4
MX5
MX6
MX7

L34
BLM18BA470SN1(47,300MA)_6

1

+3VPCU
40

R194

SCI/GPIOE
GA20/GPIO0
KBRST/GPIO1
ECRST

4.7U/6.3V_6
0.1U/10V_4
0.1U/10V_4
0.1U/10V_4
0.1U/10V_4
0.1U/10V_4
0.1U/10V_4
4.7U/6.3V_6

2

C

MY0
MY1
MY2
MY3
MY4
MY5
MY6
MY7
MY8
MY9
MY10
MY11
MY12
MY13
MY14
MY15
MY16
MY17

20
1
2
37

C388
C425
C432
C450
C452
C449
C384
C391

9
22
33
96
111
125
67

1

31
31
31
31
31
31
31
31
31
31
31
31
31
31
31
31
31
31

MX0
MX1
MX2
MX3
MX4
MX5
MX6
MX7

SCI1#
GATEA20
RCIN#
3920_RST#

VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
AVCC

3

31
31
31
31
31
31
31
31

+5VPCU

2

GATEA20
RCIN#

SERIRQ
LFRAME
LAD0
LAD1
LAD2
LAD3
PCICLK
PCIRST/GPIO5
CLKRUN

4

13
13

3
4
10
8
7
5
12
13
38

1

D

SERIRQ
LFRAME#
LAD0
LAD1
LAD2
LAD3
PCLK_LPC_KB3920
R197
*0_4/S
CLKRUN#

+3VPCU_EC

1

U7
*GMT_G910T21U

U8
12
SERIRQ
12,33 LFRAME#
12,33
LAD0
12,33
LAD1
12,33
LAD2
12,33
LAD3
12 PCLK_LPC_KB3920
12
PCIRST#
12
CLKRUN#

+3VPCU

2

Sheet
1

32

of

42

A

B

C

D

E

33

Mini PCI-E Card 1 WLAN
+3VSUS
+1.5V
R366

*10K/F_4

2

+3V

C630
0.01U/16V_4

C629
0.1U/10V_4

C24
10U/6.3V_8

+1.5V

D

32

9
9
9
9

R359

*0_6

EC_DEBUG1

PCIE_TXP1
PCIE_TXN1
PCIE_RXP1
PCIE_RXN1

12 PCLK_LPC_DEBUG

PCIE_TXP1
PCIE_TXN1
PCIE_RXP1
PCIE_RXN1
PCLK_LPC_DEBUG
MINI_PLTRST#
PCIE_MINI1_CLKP
PCIE_MINI1_CLKN

2 PCIE_MINI1_CLKP
2 PCIE_MINI1_CLKN
T60

CLK_MINI_OE#

14 BT_COMBO_EN#
T61

MINICAR_PME#

51
49
47
45
43
41
39
37
35
33
31
29
27
25
23
21
19
17
15
13
11
9
7
5
3
1

C

3

13,30 PCIE_WAKE#

CN15
+5V

Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
GND
PETp0
PETn0
GND
GND
PERp0
PERn0
GND
Reserved
Reserved
GND
REFCLK+
REFCLKGND
CLKREQ#
BT_CHCLK
BT_DATA
W AKE#

+3.3V
GND
+1.5V
LED_W PAN#
LED_W LAN#
LED_W W AN#
GND
USB_D+
USB_DGND
SMB_DATA
SMB_CLK
+1.5V
GND
+3.3Vaux
PERST#
W _DISABLE#
GND

52
50
48
46
44
42
40
38
36
34
32
30
28
26
24
22
20
18

Reserved
Reserved
Reserved
Reserved
Reserved
+1.5V
GND
+3.3V

16
14
12
10
8
6
4
2

MINI_BLED
RF_LINK#

R15

*0_4

R16

10K/F_4

R17
R18

*0_4/S
*0_4/S

D

MINICAR_PME#

+3V

BLUELED 29,31,32
RF_LINK# 31,32
+3V
USBP10+
USBP10-

DAT_SMB
CLK_SMB

1
Q38
*PDTC144EU

MINI_PLTRST#

13
13

C488
0.1U/10V_4

MINI_PLTRST# 12
RF_OFF# 12
LAD0
LAD1
LAD2
LAD3
LFRAME#

C631
10U/6.3V_8

PDAT_SMB 2,6,7,13
PCLK_SMB 2,6,7,13

LAD0
LAD1
LAD2
LAD3
LFRAME#

12,32
12,32
12,32
12,32
12,32

INTEL WLAN
CARD PIN 20
W_DISABLE#
have
internal
pull-up 110k
ohm

+3V

C621
0.1U/10V_4

C25
1U/10V_4
C

MINI PCIE H=4.0

BT_DATA,BT_CHCLK,CLKREQ#
internal pull-DOWN 100k
ohm

R365
*10K/F_4

PCLK_LPC_DEBUG

R364

*0_4

C623

*27PF/50V_4

for EMI request

B

B

A

A

PROJECT : OP8
Quanta Computer Inc.
Size
Custom
NB5/RD2

Document Number

Rev
1A

Mini CARD

Date: Friday, March 20, 2009
A

B

C

D

Sheet
E

33

of

42

5

4

3

+3V

2

1

2,3,5,6,7,10,11,12,13,14,15,16,20,23,24,25,27,28,29,30,31,32,33,35,39

34

DC/DC +3VPCU/+ 5VPCU/ +12VALW
TON: 5V / 3.3V
GND = 400 / 500KHz
REF = 400 / 300KHz
VCC = 200 / 300KHz

+5VPCU 27,31,32,35,36,37,38
+3VPCU 5,12,23,27,29,31,32,36,37,38,40
+VIN

+3VSUS 13,26,29,33,35,37,39

D

D

DB modify

+3VS5 5,7,12,13,14,15,16,39
+5VAL

1

PC108
1U/10VC_4

PC110
0.1U/10VC_4

1

*1U/10VC_4
6236AGND

8
7
6
5
4
3
2
1
PD14
1

PR135

1

3
2
1

2

1
2

2
1

1

5
6
7
8

2
1

39

PC106
*0.1U/10VC_4

4

MAIND

PQ31
SI4800BDY

6236AGND

0.1U/50VB_6

6236AGND

2

PR140
0_4
PGOOD2

PR142
0_4

+3V

HW PG

1

*SHORT-1A

3
2
1

PC102
1U/10VC_4

HW PG

1

PR134
0_6

6236AGND

3

+3V
6.76A

23,32,35,37,38

B

PC100
PD13
CHN217PT
2

S0-S1

6236AGND
+3VPCU

0.1U/50VB_6

+12V_ALW P

5

6

PC98
2.2U/50VB_8 SI2

7

PR141
0_4

PR150
100K_4

8

2

+12VALW

+3VS5

PQ29
AP4228

1

Please use +15VALW to
prevent voltage
rating issue

+3VPCU

PR146
*0_4

Rds(on) 15m ohm

3V_DL

PR210

3

2

PC99
0.1U/50VB_6

+12VALW is +15V power level

PQ54
AO4712

2
1_6

PC101

B

+

6236AGND

CHN217PT

I_lim*MOSFET(RDSON)=V_ILIM(mV)/10
V_ILIM(mV)=5uA*R_ILIM

PR147
0_4
PC195
2200P/50VA_6

3
2
1

3V_DH

BST1
DL1
VDD
SECFB
AGND
PGND
DL2
BST2

PAD
33

1

+5VAL
6236AGND

6236AGND

1
2
3
8
7
6
5

2
2
1

1
2
3

5VBST1

1

PR136 1_6
1
2

PR211
2.2_6

4

3VBST2R

Rds(on) 15m ohm

3VBST2

PR145
0_4

PC105
0.1U/50VB_6

PQ51
AO4712

5VBST1R

Rb

PC169
2200P/50VA_6

2

1
2

5V_DL

4

2

C

PGOOD2

PC104

PR144
*0_4

5V_DH
5V_LX

PU7
RT8206

PR148
309K/F_4
1

32
31
30
29
28
27
26
25

REFIN2
ILIM2
OUT2
SKIP
PGOOD2
ON2
DH2
LX2

+3VPCU

PL13
2.5uH/7.5A_10

3V_LX
PC198
0.1U/10VC_4

Ra

6236FB1
2
HW PG
6237ON1

PR143 1
309K/F_4

BYP
OUT1
FB1
ILIM1
PGOOD1
ON1
DH1
LX1

PQ55
AO4496

PR149
0_4

REFIN2

0.1U/50VB_6

PC192
0.1U/10VC_4

PC190
330U/6.3V_ESR25_6X5.8

+

PR203
2.2_6

9
10
11
12
13
14
15
16

6236AGND

PC199
330U/6.3V_ESR25_6X5.8

+5VPCU
PL12
2.5uH/7.5A_10

6236AGND

Rb around 49.9k

+5VPCU

PQ48
AO4496

17
18
19
20
21
22
23
24

Vout=0.7(Ra+Rb)/Rb

C

LDOREFIN
LDO
IN
RTC
ONLDO
VCC
TON
REF

6236AGND

+3VPCU
C/C:8A
P/C:10A

6236AGND

4
PC107
*0.1U/10VC_4

3.3 Volt +/- 5%

4

2

8
7
6
5

Place these CAPs
close to FETs

REF

PC109

*47_6

5
6
7
8

6237VIN
PC111
0.1U/50VB_6

PC166
2200P/50VB_4

PC165
0.1U/50VB_6

PC92
10U/25VD_1206

Place these CAPs
close to FETs

6237ONLDO

PR151
150K/F_4

*0_4
PR154

1

5
6
7
8

+

2

+5VPCU
C/C:8A
P/C:10A

2

PC194
10U/25VD_1206

PR152
1K_4

PC112
4.7U/6.3VC_6

PD15
UDZS5.6BTE-17
1
2

+3VLANVCC 30,39

5 Volt +/- 5%

+5V_VCC1
PR153

+VIN

5,15,20,23,24,25,27,28,29,31,32,33,35,38,39

PC197
0.1U/50VB_6

+5V

PC196
2200P/50VB_4

+5VSUS 23,29,32,39

+5VAL

0.5A

PR137

2

5,40 SYS_SHDN#

6237ON2

1

+3VSUS
1.84A

PQ53
SI4800BDY

3
2
1

For EMI-SI

+5V
4.31A

39

SUSD

PQ16
SI4800BDY

4

39

4.5A

For EMI-SI

DB modify

+5VSUS

S0-S1
39
+5V

PC97
0.1U/10VC_4

5,15,20,23,24,25,27,28,29,31,32,33,35,38,39

SUSD

39

LAN_ON

4

A

PQ25
AO3404

2

+LANVCC
0.27A

PROJECT : OP8
Quanta Computer Inc.

+3VLANVCC

+5VSUS 23,29,32,39

1

PC193
0.1U/10VC_4

S5_OND

+3VPCU

S0-S3

+5V

SUSD

3

MAIND4

3
2
1

MAIND

+3VSUS 13,26,29,33,35,37,39

5
6
7
8

5
6
7
8
39

S0-S3

+3VSUS

+3VSUS

5,7,12,13,14,15,16,39 +3VS5

+5VSUS
A

3

+3VS5

+5VPCU

2

S0-S5
+5VPCU

1

0_4

+3VLANVCC

30,39

Size
Custom
NB5/RD2

Document Number

Date: Friday, March 20, 2009
5

4

3

2

Rev
1A

+5V/+3V(ISL6237)
Sheet
1

34

of

42

5

4

3

2

1

35

+1.1V & +1.2V
PD2
CH501H-40PT L-F
2

13
ILIM

10

ILIM

DL

8

FB

3
RTDL

PQ52
SI3456

PQ36
AO4712
PR46
10K/F_4

RDSon=15m-ohm

PU10

23,32,34,37,38 HWPG
RTPG

9338EN

3

PGD

4

EN

+5V

PR208
0_4

1
PC186
*.1U/10V/04

DRV

6

G9338 ADJ

5

VCC

GND

PR207
47/F_4

PC184
10U/4VD_8

PC187
0.033U/25VB_6

PR66
0_6

9338ADJ

+1.1V
PR205
127/F_6

2

R1

R1

PR63
6.81K/F_4

PR54
5.11K/F_6
3

RTLFB

PR91

PC179
10U/4VD_8

+3V

PC175
10U/4VD_8

Vo=0.75(R1+R2)/R2
2
PQ5
2N7002E-G

PR92
10K/F_4

PC61
0.1U/10VC_4

R2

PR41
10K/F_4

A

1

1.1

+1.1V 7.0A
+1.1V_DYN

S0-S1

2K_4

1.0

+1.1V_DYN

B

4

PR206
100/F_4

10 DYN_PWR_EN
A

+1.1V_DYN 11
PC177
10U/4VD_8

PC170
0.1U/10VC_4

R2

Low

+1.2V 2,3,11,12,14,15

PC40
22P/50VA_4

PR90
*10K/F_4

High

+1.1V 8,9,10,11,17,18,20,39

Keep R2 higher than 10Kohm

PQ49
ME4856

Vout1= 0.5 * ( 1 + R1/R2 )

DYN_PWR_EN

R_ILIM=I_LIMIT*Rsense/20uA

RTLDRI
PC32
22P/50VA_4

PC35
*22P/50VA_4

PC189
.1U/10V/04

+1.2V

3
2
1

PR209
*0_4

PC22
*100P/50VA_4

5
6
7
8

9338DRV 3

B

C

R2

4
PC182
.1U/10V/04

PC181
.1U/10V/04

PC167
390U/2.5V_6X5.8ESR10

Vo=0.75(R1+R2)/R2

6
5
2
1
PC180
10U/4VD_8

+

PC154
2200P/50VA_6

3
2
1

R1

PC3
*100P/50VA_4

+1.1V

+1.2V

PR199
2.2_6

4

0_4

S0-S1

1.5uH/13A_10

2

10.7K/F_4

6.49K/F_6

RTPG

PL7

1

PR28

RTFB

LDRI

LFB

LEN

VOUT
1

7

6

RTLEN

PR48

+1.2V

PR37

DB modify

S0-S1

PQ37
AO4496

2

BST

RTLX

4

1

9
VDDP

RT8204

PAD

reserved for pwr seq -- andrew

3.82A

11

EN/DEM

14

*0_4

LX

PU1

+1.2V
12A (4.3A+7.0A)

PC178
0.1U/10VC_4

PC2
*100P/50VA_4

PR5

17

DH

3
2
1

LPGD

PC5
0.1U/50VB_6
RTDH

5
6
7
8

PGD

5

RTEN 15

20,27,32,38,39,40 MAINON

C

2

4

0_4
0_4

VDD

RTPG
RTLPPG
PR1

VRON

TON

2.2_6

12

D

PC133
*10U/25VD_1206

RTTON 16
PR49

23,32,34,37,38 HWPG

BST

1U/10VC_4

PR47
47K_4

PR4

PC139
10U/25VD_1206

8204VDD
PR9
604K_4

DB modify

PC130
0.1U/50VB_6

PC17

PC131
2200P/50VB_4

+3VSUS

Frequency=Vout/(VIN*TON)

32,36

PC11
1U/10VC_4

PR23
10_6

+VIN

Ton=3.85p*R_TON*VOUT/(VIN-0.5)

+VIN
RTBST

1

5
6
7
8

+5VPCU
D

PROJECT : OP8
Quanta Computer Inc.

PR31 for UMA only
Size
B
NB5/RD2

Document Number

Date: Friday, March 20, 2009
5

4

3

2

Rev
1A

+1.2V & +1.1V(RT8204)
Sheet
1

35

of

42

D

E

+CPUVDDNB

1
47/F_4

PR99
10_6
PR95
22.1K/F_4

2

1

4

CPU_SVC

PR58
1

0_4
2

5

PR50
1

0_4
2

6

PR51

SVC

PGND_0

34 UGATE_0
33

PHASE_0

ENABLE

LGATE_0

32
31

LGATE_0

9
10

PVCC

ISL6265HRTZ-T

LGATE_1

VDIFF_0

PGND_1

FB_0

PHASE_1

30
29

4.7U/6.3VC_6

LGATE_1

28
4
27

+VCORE1

UGATE_1

26

UGATE_1
PR42

0.22U/25VB_6

2
3
2
1
2

2
0_4

1

0_4

Parallel

2
PC23
0.1U/50VB_6

PR30
18.2K/F_4
ISP_1
3.92K/F_4
ISN_1
+VCORE0

+VCORE1

2

2

PR185

1
2

PC7

PR7
*255/F_4
10_4

Location
PR19
PR185

PR3

PR138

*54.9K/F_4

4

Value

Part Number

NC
1K/F_4

+VCORE0 5,26

PR139

PC12,PR17,PC4,PC7,
PR3,PR24,PC6,PR7

NC
0.001_2512

CS+001AGM13

PROJECT : OP8
Quanta Computer Inc.

NC
Size
C
NB5/RD2

Document Number

C

D

E

F

G

Rev
1A

CPU_CORE(ISL6265)

Date: Friday, March 20, 2009
B

4

+VCORE1 5

CS21002FB24

+CPUVDDNB5

PR204

A

1

For Tigris
PC4
*180P/50VA_4

3 CPU_VDD1_RUN_FB_H

+VCORE1

1

Reserve for uni-plane

PR24

*1K/F_4

3 CPU_VDD1_RUN_FB_L

PC6
*4700P/25VB_4

PR19
*0_4

*1200P/50VB_6

1K/F_4

Reserve for uni-plane

*10_4

2

0.001_2512

+1.8VSUS

Close to
CPU socket

3

PR204

10_4

PR139

PC88

PR29

PR17

PR181

*6.81K/F_4

3 CPU_VDD0_RUN_FB_L

PR18

3 CPU_VDD0_RUN_FB_H

1

1

1

2
1

0_4

PQ43
AON6718L

PC155
2200P/50VA_6

ISN_0

10_4

PC12

*1000P/50VB_4

+VCORE0

PC129
0.1U/50VB_6

PR20

PR183
18.2K/F_4

PR21

PR182

ISP_0
3.92K/F_4

4

PR201
2.2_8

4

PR184

Close to
CPU
socket

PC87
2

3

1

ISN_1

1_6

24

23

ISP_1

VW_1

COMP_1

22

21

20

FB_1

VDIFF_1
19

VSEN_1
18

RTN_1

RTN_0

17

16

ISN_0

15

14

ISP_0

PL9
0.36uH/25A_11
1

330U/2V_ESR9_7

13

PC38

25

330U/2V_ESR9_7

PC18
1000P/50VB_4

3

BOOT_1
VSEN_0

VW_0

6.81K/F_4

PC19
180P/50VA_4

PQ40
AON6428L
3
2
1

COMP_0

36A

PHASE_1

PR31
12

1

1

5

11
1200P/50VB_6

1
+VIN

2

PC16
PR33
54.9K/F_4

ISN_0

PC42

RBIAS
OCSET

2

ISP_0

+5VPCU

Pin 49 is GND Pin
8

PQ42
AON6718L

PC140
10U/25VD/1206

PC28
4700P/25VB_4

4

PC30
10U/25VD/1206

PR187
10K/F_4

0.22U/25VB_6

2

PHASE_0

4

PR202
2.2_8

PC142
0.1U/50VB_6

107K/F_4

DB modify

1

3
2
1

38

37
UGATE_NB

39

PHASE_NB

40
PGND_NB

OCSET_NB

LGATE_NB

41

42

43
VSEN_NB

RTN_NB

44

45
COMP_NB

FB_NB

FSET_NB

46

47
VCC

VIN

UGATE_0

SVD

180P/50VA_4
7

PR36
255/F_4
PR39
1K/F_4

PC49

35 BOOT_0

PC138
2200P/50VB_4

6265AGND

PC141
PR186

PWROK

3

36 BOOT_NB

1

0_4
2

2

2

1
49

3
PR65
1

10K_4

BOOT_0

1_6

CPU_SVID
CPU_SVD

32,35 VRON

BOOT_NB

+VCORE0

1

2

3

0_4
2

PGOOD

3
2
1

3

OFS/VFIXEN

PR76
2

PC161
2200P/50VA_6

1

3 CPU_PWRGD_SVID_REG

1

PL8
0.36uH/25A_11

PR191
1_6

*10K_4

2

36A

PC85
330U/2V_ESR9_7

PR70

2

PR96

PU3

PC86
330U/2V_ESR9_7

0_4
1

16 VRM_PWRGD

6265AGND

PR83
2

GND

1

PQ39
AON6428L

PC145
0.1U/50VB_6

2
PR84
*0_4

+3VPCU
PR85
10K_4

4
UGATE_NB

6265AGND

1

+3VPCU

2

2
PR94
0_4

48

+5VPCU

PHASE_NB

PC137
10U/25VD/1206

0.8

PC27
10U/25VD/1206

1

LGATE_NB
PR195
16.2K/F_4

PC143
0.1U/50VB_6

1

Pre DB modify

PC147
2200P/50VB_4

PC53
0.01U/50VB_4
*short
6265AGND

PR82

1.0

0_4

0

PC148

1

PR189

PR192
44.2K/F_6

1.2

PR81
0_4

PC146

1.4

1

33P/10VB_4

0

0

+VIN

6265AGND

1200P/50VB_6

0

1

1

PR100
10_6

LGATE_NB

FDS6900AS

2

+VIN

2

Output

1

SVD

PC52
1U/10VC_4

S2 4

PC51

SVC

1000P/50VB_4

+5VPCU

VFIXEN VID Codes

G2 3

5

5

X

6265AGND

5V

6

5

X

PR197

PL10
3.3UH/11A_10

5

V

2

X

X

D1 2

PC176
0.1U/10VC_4

1

V

3 CPU_VDDNB_RUN_FB_L

3.3V

7 S1/D2

PC151
10U/25VD_1206

+

47/F_4

D1 1
PC159
0.1U/50VB_6

3 CPU_VDDNB_RUN_FB_H

VFIXEN

36

+VIN

G1

8

PC153
2200P/50VB_4

OFS

PC183
390U/2.5V_ESR10_6X5.8

PR198

1.2V

H

PQ46
UGATE_NB

ISL6265 Pin1

G

1

4A

F

2

C

1

B

2

A

Sheet
H

36

of

43

A

B

C

D

E

37

+2.5V 3
+1.8VSUS 3,4,5,6,7,36,38

+1.8VSUS
+VIN
4

4

PC144
10U/25VD_1206

PR34

1
11

S5ON

10

S3ON

S3

+1.8VSUS

1

23

PR32
0_4

PR16
VDDIO_FB_H

3

51116_V5FILT

Rb

VTTSNS
COMP
NC
NC

PR22
619K/F_4

fix model change to adjust model
+VIN

PGND
PAD

PC47
1U/10VC_4

2

+0.9VSMVTT 4,7
VTTSNS

PR52
*0_4/S

18
PR53
*0_4

25

2

MODE

+1.8VSUS

5
6
7
8

PC119
0.1U/10VC_4

PC115
0.1U/10VC_4

+3VPCU

SHDN

3

VIN

VOUT

PC116
1U/10VC_4

2

2

GND

4

39

R1
SET

S0~S3

Mode

Discharge Mode

V5IN

No discharge

VDDQ

Tracking discharge

Gnd

Non-tracking discharge

2

V_TRIP(mV)=R_TRIP(Kohm)*10(uA)

1.8V_OND

PQ19
ME4856

4

+
PR156
100K/F_4

PC113
4.7U/6.3VC_6

5SET

3
2
1

VR2.5_ON

4

+1.8VSUS

+2.5V

1

32

1

CPU_VTT_SENSE

+0.9VSMVT
2.25A

S0~S1

SI power
PU8

PR157
10K_4

32,39

PR38

PC33
0.033U/25VB_6

Close to CPU

SUSON

3

+0.9VSMVTT
PC62
10U/4VD_8

PC67
10U/4VD_8

24

*SHORT-1A

3

+2.5V
0.25A

PR15
0_4
PR11
0_4

PR2

4,6 +0.9VSMVREF
VDDIO_FB_L

23,32,34,35,38

0_4
PR35
0_6

PR13
10K/F_4
PR12

VTT

GND

51116_V5FILT

4

VDDQSET

5

7
12

1

MODE

3

6

VTTGND
VDDQSNS

CS_GND

8

COMP

*0_4

S5

HW PG

DRVL

VTTREF

AON6718L

PR27
*14.3K/F_4

13

2

19

9

*0_4

PGOOD

RT8207

17

PC10
*100P/50VA_4

LL

PQ41

1
2
3

PR14
14.3K/F_4

1.8_DL

4

PC160
2200P/50VA_6

Ra

PR190
10K_4
8.45K/F_6

DRVH

5

1

20

16 CS

PC9
*100P/50VA_4

PC152
0.1U/10VC_4

2

1.8V_LX

PR43

CS

VLDOIN
PR200
2.2_6

390U/2.5V_6X5.8ESR10

21

+3VSUS

PC8
*100P/50VA_4

1.5uH/10A_10
PC158

1.8V_DH

1
2
3

PL6
+1.8VSUS

PC15
1U/10VC_4

14

2.2_6

PQ38
AON6428L

+1.8VSUS

+

VBST

V5FILT

VBST 22
0.1U/50VB_6

Rb value from 100K to 300K ohm

15

1

PR71

V5IN

PC46

PU2

4

S0~S3

3

10_6

DB modify

5

PC45
2200P/50VB_4

PC26
2.2U/6.3VC_6

2

51116_V5FILT

PC43
0.1U/50VB_6

Ra=(Vout-0.75)/0.75*Rb

I_lim(Valley)=10uA*R_ILIM/RDS_ON
For OCP set.

+5VPCU

2

PC37
*10U/25VD_1206

+1.8VSUS
23.65A

+

PC174
100U/25V_6.3X7.7

PC163
100U/25V_6.3X7.7

PC103
0.1U/10VC_4

PC191
0.1U/10VC_4

PC114
0.1U/10VC_4

+

+1.8V
G913C

I_OCP=V_trip/Rds_on+I_Ripple/2

+1.8V
10.4A

VDDQSET

S0~S1

GND

Vout=1.25(1+R1/R2)

R2

PR155
100K/F_4

+1.8V

V5IN

3,5,8,10,11,15,16,17,18,20,21,22,26,39

PC117
0.1U/10VC_4

FB

VDDQ(V)

VTTREF and Vtt

2.5

V_ vddqsns/2

1.8

V _vddqsns/2

adjustable

Note
DDR
DDR2

V_VDDQSNS/2

1.5V
Source Exif Data: 
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Modify Date                     : 2014:05:01 11:06+03:00
Create Date                     : 2009:03:20 15:07:56+08:00
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Metadata Date                   : 2014:05:01 11:06+03:00
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Format                          : application/pdf
Title                           : Quanta OP8 - Schematics. www.s-manuals.com.
Creator                         : 
Description                     : 
Subject                         : Quanta OP8 - Schematics. www.s-manuals.com.
Page Count                      : 41
Keywords                        : Quanta, OP8, -, Schematics., www.s-manuals.com.
Warning                         : [Minor] Ignored duplicate Info dictionary

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