Quanta U82 Schematics. Www.s Manuals.com. R1a Schematics

User Manual: Motherboard Quanta U82 Discrete Ultra/Slim - Schematics. Free.

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5

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352-(&78
4XDQWD&RPSXWHU,QF

W'Ϯϭ
Size
Custom

Document Number

5

4

3

2

Rev
1A

ůŽĐŬŝĂŐƌĂŵ

Date: Monday, May 06, 2013

Sheet
1

1 of

40

5

4

3

2

<20>
<20>
<20>
<20>
<20>
<20>
<20>
<20>

IN_D2#
IN_D1#
IN_D0#
IN_CLK#
IN_D2
IN_D1
IN_D0
IN_CLK

C54
B58
B55
A57
C55
C58
A55
B57

TP89

DDI1_TXN0
DDI1_TXN1
DDI1_TXN2
DDI1_TXN3
DDI1_TXP0
DDI1_TXP1
DDI1_TXP2
DDI1_TXP3

TP91
<27>

EC_PECI

D61

CATERR#

K61

EC_PECI

N62

PROC_DETECT#
CATERR#
PECI

+1.35VSUS

D

<19>

<19>

INT_eDP_AUXP
INT_eDP_AUXN
INT_eDP_TXP0

INT_eDP_TXN0

B45
A45

INT_eDP_TXP0

B46
B47
C46
B49

INT_eDP_TXN0

C

C45
A47
C47
A49

EDP_AUXP
EDP_AUXN
eDP_TXP0
eDP_TXP1
eDP_TXP2
eDP_TXP3

eDP_TXN0
eDP_TXN1
eDP_TXN2
eDP_TXN3

*HSW_ULT_DDR3L

+VCCIOA_OUT

R109

56.2/F_4

PROCHOT#

K63

PROCHOT#

DDR3

R415

H_PROCHOT#

THERMAL

INT_eDP_AUXP
INT_eDP_AUXN

EDP_RCOMP
EDP_DISP_UTIL

<27,32>

SM_DRAMRST#
SM_RCOMP0
SM_RCOMP1
SM_RCOMP2
SM_PG_CNTL1

PRDY#
PREQ#
R397
TP86

10K/F_4
PROCPWRGD

C61

PROCPW RGD

24.9/F_4 eDP_RCOMP

eDP_COMPIO and ICOMPO signals should be shorted
near balls and routed with typical impedance <25 mohms

PROC_TCK
PROC_TMS
PROC_TRST#

JTAG & BPM

<19>
<19>

EDP_DISP_UTIL

eDP

<6>

D20
A43

SI modify to short pad

PWR MANAGEMENT

eDP_COMPIO and ICOMPO signals should be shorted
near balls and routed with typical impedance <25 mohms
eDP_RCOMP
EDP_DISP_UTIL

D

R183
470_4

DDI2_TXN0
DDI2_TXN1
DDI2_TXN2
DDI2_TXN3
DDI2_TXP0
DDI2_TXP1
DDI2_TXP2
DDI2_TXP3

PCI EXPRESS* - GRAPHICS

C51
C53
C49
A53
C50
B54
B50
B53



U19B
PROC_DETECT#

MISC

U19A
DPB_LANE0_N
DPB_LANE1_N
DPB_LANE2_N
DPB_LANE3_N
DPB_LANE0_P
DPB_LANE1_P
DPB_LANE2_P
DPB_LANE3_P

1

PROC_TDI
PROC_TDO

AV15

SM_DRAMRST#

R184

*0_4/S

AU60
AV60
AU61

SM_RCOMP_0
SM_RCOMP_1
SM_RCOMP_2

R527
R528
R526

200/F_4
121/F_4
100/F_4

AV61

DDR3_DRAMRST#

DDR_PG_CNTL

J62
K62
E60
E61
E59

XDP_TCK0
XDP_TMS_CPU
XDP_TRST#_CPU

F63
F62

XDP_TDI_CPU
XDP_TDO_CPU

<12,13>

<13>

TP21
XDP_PRDY#_CPU
<11>
XDP_PREQ#_CPU
<11>
TP25
XDP_TCK0
<11>
XDP_TMS_CPU
<11>
XDP_TRST#_CPU
<7,11>
XDP_TDI_CPU
XDP_TDO_CPU

<11>
<11>

C

BPM#0
BPM#1
BPM#2
BPM#3
BPM#4
BPM#5
BPM#6
BPM#7

J60
H60
H61
H62
K59
H63
K60
J61

BPM#2
BPM#3
BPM#4
BPM#5
BPM#6
BPM#7

XDP_BPM0
XDP_BPM1
TP90
TP17
TP24
TP20
TP28
TP22

<11>
<11>

*HSW_ULT_DDR3L

Processor pull-up (CPU)
H_PROCHOT#

R419

62_4

+V1.05S_VCCST

+V1.05S_VCCST

DEL or not?
B

XDP_TDO_CPU

R411

51_4

XDP_TMS_CPU

R410

*51_4

XDP_TDI_CPU

R412

*51_4

XDP_TRST#_CPU

R539

*51_4

XDP_TCK0

R101

51_4

B

A

A

352-(&78
4XDQWD&RPSXWHU,QF
Size
Custom

Document Number

5

4

3

2

Rev
1A

h>dϭͬϵ;ĞWͬ/Ϳ

Date: Friday, April 26, 2013

Sheet
1

2 of

40

5

4

3

2

1



<12>
M_A_DQ[63:0]
<13>
M_B_DQ[63:0]
<12>
M_A_DQSN[7:0]
<12>
M_A_DQSP[7:0]
<13>
M_B_DQSN[7:0]
<13>
M_B_DQSP[7:0]

Haswell ULT Processor (DDR3L)
D

D

U19D

C

B

<12>
<12>
<12>
<12>
<12>
<12>

AH63
AH62
AK63
AK62
AH61
AH60
AK61
AK60
AM63
AM62
AP63
AP62
AM61
AM60
AP61
AP60
AP58
AR58
AM57
AK57
AL58
AK58
AR57
AN57
AP55
AR55
AM54
AK54
AL55
AK55
AR54
AN54
AY58
AW58
AY56
AW56
AV58
AU58
AV56
AU56
AY54
AW54
AY52
AW52
AV54
AU54
AV52
AU52
AK40
AK42
AM43
AM45
AK45
AK43
AM40
AM42
AM46
AK46
AM49
AK49
AM48
AK48
AM51
AK51
AU35
AV35
AY41

M_A_BS#0
M_A_BS#1
M_A_BS#2

AU34
AY34
AW34

M_A_CAS#
M_A_RAS#
M_A_WE#

SA_DQ0
SA_DQ1
SA_DQ2
SA_DQ3
SA_DQ4
SA_DQ5
SA_DQ6
SA_DQ7
SA_DQ8
SA_DQ9
SA_DQ10
SA_DQ11
SA_DQ12
SA_DQ13
SA_DQ14
SA_DQ15
SA_DQ16
SA_DQ17
SA_DQ18
SA_DQ19
SA_DQ20
SA_DQ21
SA_DQ22
SA_DQ23
SA_DQ24
SA_DQ25
SA_DQ26
SA_DQ27
SA_DQ28
SA_DQ29
SA_DQ30
SA_DQ31
SA_DQ32
SA_DQ33
SA_DQ34
SA_DQ35
SA_DQ36
SA_DQ37
SA_DQ38
SA_DQ39
SA_DQ40
SA_DQ41
SA_DQ42
SA_DQ43
SA_DQ44
SA_DQ45
SA_DQ46
SA_DQ47
SA_DQ48
SA_DQ49
SA_DQ50
SA_DQ51
SA_DQ52
SA_DQ53
SA_DQ54
SA_DQ55
SA_DQ56
SA_DQ57
SA_DQ58
SA_DQ59
SA_DQ60
SA_DQ61
SA_DQ62
SA_DQ63
SA_BA0
SA_BA1
SA_BA2
SA_CAS#
SA_RAS#
SA_WE#

SA_CLK0
SA_CLK#0
SA_CKE0

SA_CLK1
SA_CLK#1
SA_CKE1

SA_CKE2

SA_CKE3

SA_CS#0
SA_CS#1

SA_ODT0

SA_DQSN0
SA_DQSN1
SA_DQSN2
SA_DQSN3
SA_DQSN4
SA_DQSN5
SA_DQSN6
SA_DQSN7

SA_DQSP0
SA_DQSP1
SA_DQSP2
SA_DQSP3
SA_DQSP4
SA_DQSP5
SA_DQSP6
SA_DQSP7

SA_MA0
SA_MA1
SA_MA2
SA_MA3
SA_MA4
SA_MA5
SA_MA6
SA_MA7
SA_MA8
SA_MA9
SA_MA10
SA_MA11
SA_MA12
SA_MA13
SA_MA14
SA_MA15
SM_VREF_CA
SM_VREF_DQ0
SM_VREF_DQ1

*HSW_ULT_DDR3L

AV37
AU37
AU43

AY36
AW36
AW43

M_A_CLKP0
M_A_CLKN0
M_A_CKE0

<12>
<12>
<12>

M_A_CLKP1
M_A_CLKN1
M_A_CKE1

<12>
<12>
<12>

AY42

AY43

AP33
AR32

M_A_CS#0
M_A_CS#1

<12>
<12>

TP61

DDR SYSTEM MEMORY A

M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_B_DQ0
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ7
M_B_DQ8
M_B_DQ9
M_B_DQ10
M_B_DQ11
M_B_DQ12
M_B_DQ13
M_B_DQ14
M_B_DQ15
M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
M_B_DQ16
M_B_DQ17
M_B_DQ18
M_B_DQ19
M_B_DQ20
M_B_DQ21
M_B_DQ22
M_B_DQ23
M_B_DQ24
M_B_DQ25
M_B_DQ26
M_B_DQ27
M_B_DQ28
M_B_DQ29
M_B_DQ30
M_B_DQ31

AP32

AJ61
AN62
AM58
AM55
AV57
AV53
AL43
AL48

M_A_DQSN0
M_A_DQSN1
M_B_DQSN0
M_B_DQSN1
M_A_DQSN2
M_A_DQSN3
M_B_DQSN2
M_B_DQSN3

AJ62
AN61
AN58
AN55
AW57
AW53
AL42
AL49

M_A_DQSP0
M_A_DQSP1
M_B_DQSP0
M_B_DQSP1
M_A_DQSP2
M_A_DQSP3
M_B_DQSP2
M_B_DQSP3

AU36
AY37
AR38
AP36
AU39
AR36
AV40
AW39
AY39
AU40
AP35
AW41
AU41
AR35
AV42
AU42

M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_A15

M_A_A[15:0]

<13>
<13>
<13>

<12>

<13>
<13>
<13>

AP49 SM_VREF
AR51 SMDDR_VREF_DQ0_M3
AP51 SMDDR_VREF_DQ1_M3

ϮϬŵŝůƐǁŝĚƚŚ

SM_VREF
<12>
SMDDR_VREF_DQ0_M3
SMDDR_VREF_DQ1_M3

AY31
AW31
AY29
AW29
AV31
AU31
AV29
AU29
AY27
AW27
AY25
AW25
AV27
AU27
AV25
AU25
AM29
AK29
AL28
AK28
AR29
AN29
AR28
AP28
AN26
AR26
AR25
AP25
AK26
AM26
AK25
AL25
AY23
AW23
AY21
AW21
AV23
AU23
AV21
AU21
AY19
AW19
AY17
AW17
AV19
AU19
AV17
AU17
AR21
AR22
AL21
AM22
AN22
AP21
AK21
AK22
AN20
AR20
AK18
AL18
AK20
AM20
AR18
AP18
AL35
AM36
AU49

M_B_BS#0
M_B_BS#1
M_B_BS#2

AM33
AM35
AK35

M_B_CAS#
M_B_RAS#
M_B_WE#

SB_DQ0
SB_DQ1
SB_DQ2
SB_DQ3
SB_DQ4
SB_DQ5
SB_DQ6
SB_DQ7
SB_DQ8
SB_DQ9
SB_DQ10
SB_DQ11
SB_DQ12
SB_DQ13
SB_DQ14
SB_DQ15
SB_DQ16
SB_DQ17
SB_DQ18
SB_DQ19
SB_DQ20
SB_DQ21
SB_DQ22
SB_DQ23
SB_DQ24
SB_DQ25
SB_DQ26
SB_DQ27
SB_DQ28
SB_DQ29
SB_DQ30
SB_DQ31
SB_DQ32
SB_DQ33
SB_DQ34
SB_DQ35
SB_DQ36
SB_DQ37
SB_DQ38
SB_DQ39
SB_DQ40
SB_DQ41
SB_DQ42
SB_DQ43
SB_DQ44
SB_DQ45
SB_DQ46
SB_DQ47
SB_DQ48
SB_DQ49
SB_DQ50
SB_DQ51
SB_DQ52
SB_DQ53
SB_DQ54
SB_DQ55
SB_DQ56
SB_DQ57
SB_DQ58
SB_DQ59
SB_DQ60
SB_DQ61
SB_DQ62
SB_DQ63
SB_BA0
SB_BA1
SB_BA2
SB_CAS#
SB_RAS#
SB_WE#

SB_CLK0
SB_CLK#0
SB_CKE0

SB_CLK1
SB_CLK#1
SB_CKE1

SB_CKE2

SB_CKE3

SB_CS#0
SB_CS#1

AN38
AM38
AY49

AL38
AK38
AU50

M_B_CLKP0
M_B_CLKN0
M_B_CKE0

<13>
<13>
<13>

M_B_CLKP1
M_B_CLKN1
M_B_CKE1

<13>
<13>
<13>

M_B_CS#0
M_B_CS#1

<13>
<13>

AW49

AV50

AM32
AK32

C

TP59

SB_ODT0

DDR SYSTEM MEMORY B

M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_B_DQ32
M_B_DQ33
M_B_DQ34
M_B_DQ35
M_B_DQ36
M_B_DQ37
M_B_DQ38
M_B_DQ39
M_B_DQ40
M_B_DQ41
M_B_DQ42
M_B_DQ43
M_B_DQ44
M_B_DQ45
M_B_DQ46
M_B_DQ47
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63
M_B_DQ48
M_B_DQ49
M_B_DQ50
M_B_DQ51
M_B_DQ52
M_B_DQ53
M_B_DQ54
M_B_DQ55
M_B_DQ56
M_B_DQ57
M_B_DQ58
M_B_DQ59
M_B_DQ60
M_B_DQ61
M_B_DQ62
M_B_DQ63

U19C

SB_DQSN0
SB_DQSN1
SB_DQSN2
SB_DQSN3
SB_DQSN4
SB_DQSN5
SB_DQSN6
SB_DQSN7

SB_DQSP0
SB_DQSP1
SB_DQSP2
SB_DQSP3
SB_DQSP4
SB_DQSP5
SB_DQSP6
SB_DQSP7

SB_MA0
SB_MA1
SB_MA2
SB_MA3
SB_MA4
SB_MA5
SB_MA6
SB_MA7
SB_MA8
SB_MA9
SB_MA10
SB_MA11
SB_MA12
SB_MA13
SB_MA14
SB_MA15

AL32

AW30
AV26
AN28
AN25
AW22
AV18
AN21
AN18

M_A_DQSN4
M_A_DQSN5
M_B_DQSN4
M_B_DQSN5
M_A_DQSN6
M_A_DQSN7
M_B_DQSN6
M_B_DQSN7

AV30
AW26
AM28
AM25
AV22
AW18
AM21
AM18

M_A_DQSP4
M_A_DQSP5
M_B_DQSP4
M_B_DQSP5
M_A_DQSP6
M_A_DQSP7
M_B_DQSP6
M_B_DQSP7

AP40
AR40
AP42
AR42
AR45
AP45
AW46
AY46
AY47
AU46
AK36
AV47
AU47
AK33
AR46
AP46

M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
M_B_A14
M_B_A15

M_B_A[15:0]

B

<13>

^Dd

<12>
<13>

*HSW_ULT_DDR3L

A

A

352-(&78
4XDQWD&RPSXWHU,QF
Size
Custom

Document Number

4

3

2

Rev
1A

h>dϮͬϵ;Zϯ/ͬ&Ϳ

Date: Monday, May 06, 2013
5

1

Sheet

3 of

40

4

C201
22U/6.3V_8

D

C234
22U/6.3V_8

C223
22U/6.3V_8

C212
22U/6.3V_8

C236
22U/6.3V_8

C

C245
22U/6.3V_8

C178
22U/6.3V_8

C199
22U/6.3V_8

C214
22U/6.3V_8

C237
22U/6.3V_8

C213
22U/6.3V_8

C187
22U/6.3V_8

C179
22U/6.3V_8

C486
C467
*22U/6.3VS_8 *22U/6.3VS_8

C222
22U/6.3V_8

C471
22U/6.3V_8

C235
22U/6.3V_8

C466
22U/6.3V_8

C475
22U/6.3V_8

C492
22U/6.3V_8

C200
22U/6.3V_8

C211
22U/6.3V_8

C198
22U/6.3V_8

C182
22U/6.3V_8

C468
C502
*22U/6.3VS_8 *22U/6.3VS_8

F59

B

C561
10U/6.3V_6

C559
10U/6.3V_6

C550
2.2U/6.3V_4

C554
2.2U/6.3V_4

+1.05V

VSS
VSS
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD

C562
10U/6.3V_6

C556
10U/6.3V_6

C563
10U/6.3V_6

Direct tie to CPU VCC/VSS-Ball
C552
2.2U/6.3V_4

D63
P62
T59
AD60
AD59
AA59
AE60
AC59
AG58
U59
V59

C551
2.2U/6.3V_4

R458

AC60
AC62
AC63
AA63
AA60
Y62
Y61
Y60
V62
V61
V60
U60
T63
T62
T61
T60
AA62
AA61
U63
U62

R448
49.9/F_4 CFG_RCOMP V63

+VCCIO_OUT

A5

*0_8

E1
D1
J20
H18

C516
4.7U/6.3V_6
R385 TD_IREF
8.2K/F_4

B12
AV63
AU63

TP108
TP104

CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17
CFG18
CFG19

RSVD_TP
RSVD_TP
RSVD_TP
RSVD
RSVD
RSVD
PROC_OPI_RCOMP

CFG_RCOMP
RSVD

RSVD
RSVD

VSS
VSS

RSVD
RSVD
RSVD
RSVD

RSVD

TD_IREF

RSVD

A51
B51

TP80
TP83

L60

TP27

N60
W23
Y22
AY15 PROC_OPI_RCOMP

AV62
D58

D

R523
49.9/F_4

P22
N21

P20
R20

RSVD_TP
RSVD_TP

VCCIO_OUT
VCCIOA_OUT

A59

Layout note: need routing
together and ALERT need
between CLK and DATA.

+VCCIO_OUT

E20

R431
75/F_4

C63
C62
B43

TP88
TP87

SVID ALERT

RSVD_TP
RSVD_TP
RSVD
*HSW_ULT_DDR3L

+VCCIOA_OUT

H_CPU_SVIDALRT#

R422

43_4

VR_SVID_ALERT#

<32>
C

C518

VIDALERT#
VIDSCLK
VIDSOUT
PWR_DEBUG#

L62
N63
L63

H_CPU_SVIDALRT#
VR_SVID_CLK
H_CPU_SVIDDAT

H59

PWR_DEBUG

*0.1U/10V_4

PWR_DEBUG

<11>

For 65 degree, 1.8v limit, (SW)

VR_SVID_CLK

VR_SVID_CLK

TP14

VR_EN
VR_READY

F60
C59

H_VR_ENABLE_MCP
IMVP_PWRGD_R
R398

VCCST
VCCST
VCCST

AC22
AE22
AE23

10K_4

IO Thrm Protect

+3VPCU

SVID CLK

SI modifyR105
D1
2

+V1.05S_VCCST

IMVP_PWRGD_R

*0_4/S

IMVP_PWRGD

<32>

<32>

R78
16.5K/F_4

+V1.05S_VCCST

THRM_MOINTOR

Place PU resistor
close to VR

<27>
<6,32>

R414
130/F_4

*RB501V-40
1
H_CPU_SVIDDAT R421

SVID DATA

*0_4/S

VR_SVID_DATA

B59 H_VCCST_PWRGD_R

R399

3.3K/F_4

For 75 degree, 1.2v limit, (HW)

H_VCCST_PWRGD

*0_4/S

THRM_MOINTOR1

SI modify to short pad
SI modify to short pad
RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP

P60
P61
N59
N61

VSS_SENSE

R408

100/F_4 +VCC_CORE

R413

100/F_4

E63
E62

VCC_SENSE

<32>

VSS_SENSE

<32>

<11,27,29,30,31>

HWPG

D14 1

2 RB501V-40

H_VCCST_PWRGD

<11>

+1.05V

C508
*10P/50V_4

AW14
AY14

B

R504
100K_4 NTC

+V1.05S_VCCST
R459

RSVD
RSVD

<27>

C135
0.1U/10V_4

THER_CPU
R402
10K_4

ϭϬϬͲцϭйƉƵůůͲƵƉƚŽsŶĞĂƌƉƌŽĐĞƐƐŽƌ͘
VCC_SENSE

R509
*0_4/S

+V1.05S_VCCST

TP44
TP40
TP32
TP38

<27>

C145
0.1U/10V_4

R76
<32>

VCC

RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD



U19E
CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17
CFG18
CFG19

TP53
TP51
TP63
TP96
TP58
TP48
TP54
TP41
TP35
TP34
TP49
TP43
TP36
TP31
TP30
TP42
TP16
TP15
TP37
TP39

+V1.05S_VCCST

VCCST_PWRGD
L59
J58
N58
AC58
AB23
AD23
AA23
AE59
AT2
AU44
AV44
D15
F22
H22
J21
N23
R23
T23
U10
AL1
AM11
AP7
AU10
AU15

C560
10U/6.3V_6

CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17
CFG18
CFG19

CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17
CFG18
CFG19

1

C221
22U/6.3V_8

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

<11>
<11>
<11>
<11>
<11>
<11>
<11>
<11>
<11>
<11>
<11>
<11>
<11>
<11>
<11>
<11>
<11>
<11>
<11>
<11>

1

C224
22U/6.3V_8

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

AH26
AJ31
AJ33
AJ37
AN33
AP43
AR48
AY35
AY40
AY44
AY50

1

CFG0-19 need Reserve TP

Close to CPU
C36
C40
C44
C48
C52
C56
E23
E25
E27
E29
E31
E33
E35
E37
E39
E41
E43
E45
E47
E49
E51
E53
E55
E57
F24
F28
F32
F36
F40
F44
F48
F52
F56
G23
G25
G27
G29
G31
G33
G35
G37
G39
G41
G43
G45
G47
G49
G51
G53
G55
G57
H23
J23
K23
K57
L22
M23
M57
P57
U57
W57
AB57
AD57
AG57
C24
C28
C32

HSW ULT POWER

C469
22U/6.3V_8

2

1.4A
+1.35VSUS

2

32A
+VCC_CORE

3

POWER

2

U19F

RESERVED

5

SI modify to short pad

*0_8/S
C514

C513

*1U/6.3V_4

*22U/6.3V_8

TP111
TP110
+V1.05S_VCCST

*HSW_ULT_DDR3L
R401
150/F_4
PWR_DEBUG

Processor Strapping
A

The CFG signals have a default value of '1' if not terminated on the board.

1

+VCCIOA_OUT
+VCCIO_OUT
+1.5V

CFG3
(Physcial Debug Enable)
DFX Privacy
CFG4
(DP Presence Strap)

<2>
<6>

R400
*10K_4

0
Enable: Set DFX Enable in DFX interface MSR

CFG3

R452

*1K_4

Disable; No physical DP attached to eDP

Enable; An ext DP device is connected to eDP

CFG4

R143

1K_4

352-(&78
4XDQWD&RPSXWHU,QF

<10,21,24,26,30>
Size
Custom

+1.35VSUS
<2,12,13,24,31>
+1.05V
<7,10,11,26,27,30,33,35>
+VCC_CORE
<32>
5

A

Circuit

Disable:

Document Number

4

3

2

Rev
1A

ϬϰͲͲh>dϯͬϵ;WKtZͲϭͿ

Date: Friday, April 26, 2013
1

Sheet

4 of

40

5

4

3

2

1



U19I
U19H
U19G

D

C

A11
A14
A18
A24
A28
A32
A36
A40
A44
A48
A52
A56
AA1
AA58
AB10
AB20
AB22
AB7
AC61
AD21
AD3
AD63
AE10
AE5
AE58
AF11
AF12
AF14
AF15
AF17
AF18
AG1
AG11
AG21
AG23
AG60
AG61
AG62
AG63
AH17
AH19
AH20
AH22
AH24
AH28
AH30
AH32
AH34
AH36
AH38
AH40
AH42
AH44
AH49
AH51
AH53
AH55
AH57
AJ13
AJ14
AJ23
AJ25
AJ27
AJ29

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSS

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

AJ35
AJ39
AJ41
AJ43
AJ45
AJ47
AJ50
AJ52
AJ54
AJ56
AJ58
AJ60
AJ63
AK23
AK3
AK52
AL10
AL13
AL17
AL20
AL22
AL23
AL26
AL29
AL31
AL33
AL36
AL39
AL40
AL45
AL46
AL51
AL52
AL54
AL57
AL60
AL61
AM1
AM17
AM23
AM31
AM52
AN17
AN23
AN31
AN32
AN35
AN36
AN39
AN40
AN42
AN43
AN45
AN46
AN48
AN49
AN51
AN52
AN60
AN63
AN7
AP10
AP17
AP20

AP22
AP23
AP26
AP29
AP3
AP31
AP38
AP39
AP48
AP52
AP54
AP57
AR11
AR15
AR17
AR23
AR31
AR33
AR39
AR43
AR49
AR5
AR52
AT13
AT35
AT37
AT40
AT42
AT43
AT46
AT49
AT61
AT62
AT63
AU1
AU16
AU18
AU20
AU22
AU24
AU26
AU28
AU30
AU33
AU51
AU53
AU55
AU57
AU59
AV14
AV16
AV20
AV24
AV28
AV33
AV34
AV36
AV39
AV41
AV43
AV46
AV49
AV51
AV55

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

*HSW_ULT_DDR3L

VSS

^Dd

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

AV59
AV8
AW 16
AW 24
AW 33
AW 35
AW 37
AW 4
AW 40
AW 42
AW 44
AW 47
AW 50
AW 51
AW 59
AW 60
AY11
AY16
AY18
AY22
AY24
AY26
AY30
AY33
AY4
AY51
AY53
AY57
AY59
AY6
B20
B24
B26
B28
B32
B36
B4
B40
B44
B48
B52
B56
B60
C11
C14
C18
C20
C25
C27
C38
C39
C57
D12
D14
D18
D2
D21
D23
D25
D26
D27
D29
D30
D31

D33
D34
D35
D37
D38
D39
D41
D42
D43
D45
D46
D47
D49
D5
D50
D51
D53
D54
D55
D57
D59
D62
D8
E11
E17
F20
F26
F30
F34
F38
F42
F46
F50
F54
F58
F61
G18
G22
G3
G5
G6
G8
H13

TP109

TP78

DC_TEST_AY2_AW2
DC_TEST_AY3_AW3
TEST_AY60
DC_TEST_AY61_AW61
DC_TEST_AY62_AW62
TEST_B2
DC_TEST_A3_B3
DC_TEST_A61_B61
DC_TEST_B62_B63
DC_TEST_C1_C2

AY2
AY3
AY60
AY61
AY62
B2
B3
B61
B62
B63
C1
C2

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSS

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

DAISY_CHAIN_NTCF_AY2
DAISY_CHAIN_NTCF_A3
DAISY_CHAIN_NTCF_AY3
DAISY_CHAIN_NTCF_A4
DAISY_CHAIN_NTCF_AY60
DAISY_CHAIN_NTCF_A60
DAISY_CHAIN_NTCF_AY61
DAISY_CHAIN_NTCF_A61
DAISY_CHAIN_NTCF_AY62
DAISY_CHAIN_NTCF_A62
DAISY_CHAIN_NTCF_B2
DAISY_CHAIN_NTCF_AV1
DAISY_CHAIN_NTCF_B3
DAISY_CHAIN_NTCF_AW 1
DAISY_CHAIN_NTCF_B61
DAISY_CHAIN_NTCF_AW 2
DAISY_CHAIN_NTCF_B62
DAISY_CHAIN_NTCF_AW 3
DAISY_CHAIN_NTCF_B63 DAISY_CHAIN_NTCF_AW 61
DAISY_CHAIN_NTCF_C1
DAISY_CHAIN_NTCF_AW 62
DAISY_CHAIN_NTCF_C2
DAISY_CHAIN_NTCF_AW 63

H17
H57
J10
J22
J59
J63
K1
K12
L13
L15
L17
L18
L20
L58
L61
L7
M22
N10
N3
P59
P63
R10
R22
R8
T1
T58
U20
U22
U61
U9
V10
V3
V7
W 20
W 22
Y10
Y59
Y63
V58
AH46
V23
AH16

D

C

A3
DC_TEST_A3_B3
A4
TEST_A4
A60 TEST_A60
A61 DC_TEST_A61_B61
A62 TEST_A62
AV1 TEST_AV1
AW 1 TEST_AW1
AW 2 DC_TEST_AY2_AW2
AW 3 DC_TEST_AY3_AW3
AW 61DC_TEST_AY61_AW61
AW 62DC_TEST_AY62_AW62
AW 63TEST_AW63

TP79
TP85
TP84
TP102
TP105

TP107

*HSW_ULT_DDR3L
B

B

*HSW_ULT_DDR3L

A

A

352-(&78
4XDQWD&RPSXWHU,QF
Size
Custom

Document Number

5

4

3

2

Rev
1A

h>dϰͬϵ;Z^s͕'EͿ

Date: Monday, May 06, 2013

Sheet
1

5 of

40

5

4

3

2

1

Ϭϲ

Lynx Point-LP Platform Controller Hub (LVDS,DDI)

PCH_LVDS_BLON

PCH_LVDS_BLON

A9

<19>

PCH_DISP_ON

PCH_DISP_ON

C6

<19>

PCH_DPST_PWM

PCH_DPST_PWM

B8

<2>

R379

EDP_DISP_UTIL

EDP_BKLEN
EDP_VDDEN
EDP_BKLCTL

D

*0_4

DDPB_CTRLCLK
DDPB_CTRLDATA

Need Check!

DDPB_AUXN
DDPB_AUXP
DDPB_HPD

B9
C9

SDVO_CLK
SDVO_DATA

C5
B5
C8

HDMI_HPD_CON

SDVO_CLK
SDVO_DATA

<20>
<20>

HDMI_HPD_CON

INT. HDMI

EDP

D

<19>

SIDEBAND

U19M

<20>

U19L
R480

*0_4

DSWVRMEN

SUSACK#

System Power Management

for DS3
SI modify to short pad
<27>

SUSACK#_EC

R472

<11>

SYS_RESET#

<27>

SUSACK#

AC3

SYS_RESET#

C531
<11>

AK2

*0_4/S SUSACK#

SYS_RESET#

*0.1U/10V_4

AG2

SYS_PWROK
EC_PWROK

EC_PWROK

AY7

EC_PWROK

AB5

SYS_PW ROK
PCH_PW ROK

C

AG7

PLTRST#

for DS3
<27>

<27>

R479

*0_4/S

SUSWARN#

AV4

R164

*0_4/S

DNBSWON#_R

AL7

R138

*0_4/S

AC_PRESENT_R

AJ8

PM_BATLOW#

AN4

PCH_SLP_S0_N

AF3

PCH_SLP_WLAN_N

AM5

RSMRST#

DPW ROK
W AKE#
CLKRUN#/ GPIO32
SUS_STAT# / GPIO61 (SUS)

AW 7 DSWVRMEN

Ra

AV5

DPWROK

R543
R542

<7>

For DS3

-->Ra

SINon-DS3
modify to -->Rb
short pad
*0_4/S DPWROK_EC
RSMRST#
*0_4

DPWROK_EC

<27>

Rb
AJ5

PCIE_WAKE#

V5

CLKRUN#

AG4

SUS_STAT#

AE6

PCH_SUSCLK_L R116

PCIE_WAKE#
CLKRUN#

<22,23,26,27>
<24,27>

DDPC_CTRLCLK
DDPC_CTRLDATA
DDPC_AUXN
DDPC_AUXP
DDPC_HPD

B6
A6
A8

TP50
C

SUSCLK / GPIO62 (SUS)
SLP_S5# / GPIO63 ( DSW )
SLP_S4#

SUSW ARN#/SUSPW RDNACK/GPIO30(SUS) SLP_S3#

*0_4/S

PCH_SUSCLK

<27>

TP26

AP5

SLP_S5#

AJ6
AT4

<11>

SUSC#

<11,27>

DNBSWON#

PW RBTN#

SLP_A#

AL5

SUSB#

<11,27>

SLP_A#

for DS3

<11>

EDP_HPD
<27>

D9
D11

TP55

SI modify to short pad
<11,27>

PLTRST#

AW 6

RSMRST#

RSMRST#

SUSWARN#_EC

APW ROK

DSW VRMEN

DISPLAY

SUSWARN#

AC_PRESENT_EC

ACPRESENT / GPIO31(DSW )

SLP_SUS#

AP4

SLP_SUS#

AJ7

SLP_LAN#

R142

*0_4/S

SLP_SUS#_EC

SLP_SUS#_EC

D6

INT_eDP_HPD_Q

<27>

SI modify to short pad

<11,27>

PCH_SLP_S0_N

BATLOW # / GPIO72(DSW )
SLP_S0#

SLP_LAN#

TP69

SLP_W LAN#/ GPIO29(DSW )

TP62

*HSW_ULT_DDR3L

*HSW_ULT_DDR3L

B

B

PCH Pull-high/low(CLG)

PLTRST#(CLG)

System PWR_OK(CLG)

<7,8,9,10,11,12,13,14,15,16,17,19,20,21,22,23,24,25,26,27,32,33,34>
<9,10,11,24,26,29,30,33,35>

+3VS5
PM_BATLOW#

R156

10K_4

PCIE_WAKE#

R131

1K_4
R453

+3V
+3VS5

Check Q2010 Rise/Fall time less than 100ns

PLTRST#

PLTRST#

100K_4

<11,14,22,23,24,26,27>

Change to 1k for LAN wake from OBFF state issue
+3VS5

Reserve EDP_HPD opposites circuit!

C522

+3V_DEEP_SUS
10K_4
10K_4

for DS3

SI modify to short pad
R449

*0.1U/10V_4

+VCCIO_OUT

5

SUSACK#
R471
SUSWARN#
R478
Check SUSWARN# need PU?

*0_4/S

2

+3VS5
INT_eDP_HPD_Q

*2N7002

1

3

INT_eDP_HPD

SYS_PWROK

DG V0.7 -> 10K
SCH V0.7 -> 1K

A

R497

*1K_4

1
U17
*TC7SH08FU

*0_4/S

CLKRUN#

R121

8.2K/F_4

SYS_RESET#

R119

10K_4

R123

*1K_4

R541

10K_4

RSMRST#
DPWROK_EC

R544

+5V

R430
10K_4

2

ULT_EDP_HPD

A

<19,20>
R447

R442
*100K_4

<4,32>

EC_PWROK

SI modify to short pad

R500
*100K_4

Q36
*2N7002

1

R481

2

SYS_PWROK

IMVP_PWRGD

4

3

+3V

R468
*10K/F_4
Q33

3

PWRBTN# internally PU in PCH to 3.3V_DSW
DNBSWON#_R
R163
*10K_4
AC_PRESENT_R
R137
*10K_4

R501
100K_4
RTD2132R Vender request PD 100kohm

*0_4/S

352-(&78
4XDQWD&RPSXWHU,QF

SI modify to short pad
Size
Custom

100K_4

Document Number

5

4

3

2

Rev
1A

h>dϱͬϵ;WŽǁĞƌDĂŶŐĞƌͿ

Date: Friday, April 26, 2013

Sheet
1

6 of

40

5

4

3

2

Lynx Point-LP Platform Controller Hub
(HDA,JTAG,SATA)

1

RTC Clock 32.768KHz

Ϭϳ

SI modify to short pad

U19J

1M_4

RTC_RST#

AU7

SRTC_RST#

AV6

SM_INTRUDER# AU6
PCH_INVRMEN AV7

RTCX2
RTCRST#

LAD0
LAD1
LAD2
LAD3

AV12

LFRAME#

<24,26,27>
<24,26,27>
<24,26,27>
<24,26,27>

LFRAME#

R476

*0_4

<24,26,27>

SRTCRST#
INTRUDER#
INTVRMEN

R473

*51_4

JTAGX_PCH

R469

51_4

JTAG_TMS_PCH

R460

51_4

JTAG_TDI_PCH

R487

51_4

JTAG_TDO_PCH

R477

C530

*18P/50V_4

C534

*18P/50V_4

*0_4/S

CLKGEN_RTC_X1

<26>

RTC_X1

2
1

AY5

AU14
AW 12
AY12
AW 11

LAD0
LAD1
LAD2
LAD3

Y4
*32.768KHZ

R483
*10M_4
D

3
4

R521

+3V_RTC

RTC_X2

RTCX1

R494

+1.05VS5

LPC

D

RTC_RST#

AW 5

RTC

<11>

RTC_X1

+1.05V

RTC_X2

JTAG_TCK_PCH

*51_4

Close to Chipset

AY10

ACZ_SDIN0

AU12
ACZ_SDOUT

AU11
AW 10
AV10
AY8

C

<2,11>

XDP_TRST#_CPU

<11>

JTAG_TCK_PCH

<11>

JTAG_TDI_PCH

<11>

JTAG_TDO_PCH

<11>

JTAG_TMS_PCH

<11>

JTAGX_PCH

XDP_TRST#_CPU

AU62

JTAG_TCK_PCH

AE62

JTAG_TDI_PCH

AD61

JTAG_TDO_PCH

AE61

JTAG_TMS_PCH

AD62
AL11
AC4
AE63
AV2

JTAGX_PCH
TP70

PCH_SPI1_CLKAA3
PCH_SPI_CS0# Y7

Y4
AC2
PCH_SPI1_SI AA2
PCH_SPI1_SO AA4
PCH_SPI_IO2 Y6
PCH_SPI_IO3 AF1
B

PCH Strap Table
Pin Name

HDA_SDIN0/ I2S0_RXD
HDA_SDIN1/ I2S1_RXD
HDA_SDO/ I2S0_TXD

SATA_RN2/ PERN6_L1
SATA_RP2/ PERP6_L1
SATA_TN2/ PETN6_L1
SATA_TP2/ PETP6_L1

J8
H8
A17
B17

SATA_RXN1
SATA_RXP1
SATA_TXN1
SATA_TXP1

J6
H6
B14
C15

SATA_RXN2
SATA_RXP2
SATA_TXN2
SATA_TXP2

<24>
<24>
<24>
<24>

SATA_RXN2
SATA_RXP2
SATA_TXN2
SATA_TXP2

<23>
<23>
<23>
<23>

SATA0GP/ GPIO34

PCH_TCK

SATA1GP/ GPIO35

PCH_TDI

SATA2GP/ GPIO36

PCH_TDO

SATA3GP/ GPIO37

JTAGX
RSVD

R341
RTC_RST#
20K/F_4

ODD (SATA3 6.0Gb/s)

V1

ACC_LED#

U1

SIO_EXT_SMI#

V6

PCI_SERR#

TP95

<21>

PCI_SERR#
TP93
TP101

R346
*1K_4

R347
20K/F_4

+3VPCU

SRTC_RST#
+3V_RTC_1
D9
*BAT54C

SATA_IREF

R362

R391

RTC_RST#

+3V
ACC_LED#
SIO_EXT_SMI#
PCI_SERR#
SATA3GP

+V1.05S_ASATA3PLL

DG recommended that SATA AC coupling capacitors should be
close to the connector (<100 mils) for optimal signal quality.

<21>
<21>

ACZ_SYNC_AUDIO

R533

33_4

ACZ_SYNC

ACZ_RST#_AUDIO

R535

33_4

ACZ_RST#

ACZ_SDOUT_AUDIO

R530

33_4

ACZ_SDOUT

R532

33_4

ACZ_BCLK

<21>

10K_4

BIT_CLK_AUDIO

R454
R106
R420
R474

10K_4
10K_4
10K_4
10K_4

+3V
SATA_LED#

C553
*10P/50V_4

<21>

L11
K10

RSVD
RSVD

*0_6 SRTC_RST#

R345

GPIO Pull UP

HDA Bus(CLG)
3.01K/F_4

U3

SATALED#

SPI_MOSI

C

Uninstall for Green-CLK

*0_6/S
R450

SPI_CS1#
SPI_CS2#

C463
1U/6.3V_4

*1U/6.3V_4

<27>

<21>

SATA_IREF

C464

<27>

SI modify to short pad

SPI_CS0#

SPI_IO2
SPI_IO3

ACC_LED#
SIO_EXT_SMI#

C12 SATA_RCOMP

A12

C462
1U/6.3V_4

RTC Power trace width 20mils.

TP97

AC1 SATA3GP

SATA_RCOMP

SPI_CLK

SPI_MISO

+3V_RTC

CN18
BAT_CONN

PCH_TRST#

PCH_TMS
RSVD
RSVD

30mils

RTC Circuitry(RTC)
mSATA (SATA4 6Gb/s)

+3V_RTC_0

+3V_DEEP_SUS

*1K_4 ACZ_SYNC

R181

*HSW_ULT_DDR3L
B

Sampled

Configuration

PWROK

0 = Default (weak pull-down 20K)
1 = Setting to No-Reboot mode

SDIO_D0 /GPIO66

Top-Block Swap

PWROK

INTVRMEN

Integrated 1.05V VRM enable

ALWAYS

Should be always pull-up

HDA_SDO /I2S0_TXD

Flash Descriptor Security
Only for Interposer

PWROK

0 = Default (weak pull-down 20K)
1 = Can be Overridden

GSPI0_MOSI /GPIO86

Boot BIOS Selection

PWROK

GNT0#

TLS Confidentiality

Deep Sx Well
On-Die Voltage
Regulator Enable

DSWVRMEN

SATA_RXN1
SATA_RXP1
SATA_TXN1
SATA_TXP1

no stuff If use green Clock
HDD0 (SATA3 6.0Gb/s)

+3V_RTC_0

0 = "top-block swap" mode
1 = Default (weak pull-up 20K)

A

<24>
<24>
<24>
<24>

I2S1_SCLK

No reboot mode setting

GPIO15

SATA_RXN0
SATA_RXP0
SATA_TXN0
SATA_TXP0

F5
E5
C17
D17

SATA_RN3/ PERN6_L0
HDA_DOCK_EN# / I2S1_TXD
SATA_RP3/ PERP6_L0
SATA_TN3/ PETN6_L0
HDA_DOCK_RST/ I2S1_SFRM SATA_TP3/ PETP6_L0

Strap description

SPKR

SATA_RN1/ PERN6_L2
SATA_RP1/ PERP6_L2
SATA_TN1/ PETN6_L2
SATA_TP1/ PETP6_L2

HDA_RST#/ I2S_MCLK

SATA_RXN0
SATA_RXP0
SATA_TXN0
SATA_TXP0

1

AU8

J5
H5
B15
A15

2

ACZ_RST#

HDA_SYNC/ I2S0_SFRM

SATA

AV11

AUDIO

ACZ_SYNC

SATA_RN0/ PERN6_L3
SATA_RP0/ PERP6_L3
SATA_TN0/ PETN6_L3
SATA_TP0/ PETP6_L3

HDA_BCLK / I2S0_SCLK

JTAG

AW 8

SPI

<21>

ACZ_BCLK

PWROK

ALWAYS

1
0

Circuit
+3V

R455

*1K_4

R376
R375

*1K_4
*1K_4

+3V_RTC

<27>

R519

330K_4

SPKR

SPKR

<9>

GPIO66_ULT
PCH_INVRMEN

R182

GPIO33_EC

1K_4

ACZ_SDOUT

LPC
SPI(Default)

Should be always pull-up

Size

P/N

MXIC

8MB

AKE3EZN0Z00 (MX25L6473EM2I-10G)

Winbond

8MB

AKE3EFP0N07 (W25Q64FVSSIQ)

GigaDevice

8MB

AKE3EGN0Q01 (GD25B64BSIGR)

Socket

Boot Location

0 = ME Crypto Transport Layer Security
cipher suite with no confidentiality(Default)
1 = Intel ME Crypto TLS cipher suite with
confidentiality

<9>

Vender

PCH SPI ROM(CLG)

DFHS08FS023

TP12
TP19
TP66-71 need place to TOP TP11
TP10
TP13
TP18

PCH_SPI_CS0#_R
PCH_SPI1_CLK_R
PCH_SPI1_SI_R
PCH_SPI1_SO_R
BIOS_WP#
HOLD#

PCH_SPI_CS0# R386
PCH_SPI1_CLK R441
PCH_SPI1_SI R436
PCH_SPI1_SO R387
+3V_DEEP_SUS

R125

*1K_4

GPIO15_ULT

<9>

SI modify to short pad

R520

330K_4

DSWVRMEN

PCH_SPI_CS0#_R
PCH_SPI1_CLK_R
PCH_SPI1_SI_R
PCH_SPI1_SO_R

CE#
SCK
SI
SO

VDD
HOLD#

W P#

VSS

8

+3VSPI

15/F_4 BIOS_WP#

R451

3.3K/F_4

R440

15/F_4

7HOLD#
4

GD25B64BSIGR
AKE3EGN0Q01

<6>
1U/10V_4 +3VSPI R389 3.3K/F_4
PCH_SPI_IO2
R388

1
6
5
2
3

R457/R453/R450/R451/R546/R548 close to U15 pin

C620

*0_4/S

U15
15/F_4
15/F_4
15/F_4
15/F_4

C521
22P/50V_4
+3V_RTC

R438

+3V_DEEP_SUS

C520
0.1U/10V_4
A

SI modify
PCH_SPI_IO3

+3V
+5V
<27>
<27>
<27>
<27>

PCH_SPI_CS0#_R
PCH_SPI1_CLK_R
PCH_SPI1_SI_R
PCH_SPI1_SO_R

PCH_SPI_CS0#_R
PCH_SPI1_CLK_R
PCH_SPI1_SI_R
PCH_SPI1_SO_R

<6,8,9,10,11,12,13,14,15,16,17,19,20,21,22,23,24,25,26,27,32,33,34>
<6,20,21,23,24,25,26,33>

+1.05V
<4,10,11,26,27,30,33,35>
+3VS5
<6,9,10,11,24,26,29,30,33,35>
+3VPCU
<4,21,24,25,26,27,28,29>
+3V_RTC
<10,26>
+V1.05S_ASATA3PLL
<10>

352-(&78
4XDQWD&RPSXWHU,QF
Size
Custom

Document Number

5

4

3

2

Rev
1A

h>dϲͬϵ;^dͬ,Ϳ

Date: Friday, April 26, 2013

Sheet
1

7 of

40

5

4

10K_4
10K_4
10K_4
10K_4
10K_4
*100K_4

ĂƌĚƌĞĂĚĞƌ

+3V_DEEP_SUS
SMBALERT#
USB_OC1#
USB_OC2#
USB_OC3#
USB_OC4#

R498
R171
R172
R173
R484

for DS3

10K_4
10K_4
10K_4
10K_4
10K_4

WLAN

CL_CLK
CL_DATA
CL_RST#

<23>
<23>
<23>
<23>

PCIE_RXN2_CARD
PCIE_RXP2_CARD
PCIE_TXN2_CARD
PCIE_TXP2_CARD

C192
C193

<26>
<26>
<26>
<26>

PCIE_RXN3_WLAN
PCIE_RXP3_WLAN
PCIE_TXN3_WLAN
PCIE_TXP3_WLAN

C494
C493

AF2
AD2

<22>
<22>
<22>
<22>

LAN

AF4

USB2.0(M/B-1)

(USBP0)

USB2.0/USB3.0 COMBO 1st

G20
H20
C33
B34

USB30_RX1USB30_RX1+
USB30_TX1USB30_TX1+

USB2N0
USB2P0
USB2N1
USB2P1
USB2N2
USB2P2
USB2N3
USB2P3
USB2N4
USB2P4
USB2N5
USB2P5
USB2N6
USB2P6
USB2N7
USB2P7

h^ϯ͘Ϭ
<25>
<25>
<25>
<25>

C

E18
F18
B33
A33

USB30_RX2USB30_RX2+
USB30_TX2USB30_TX2+

USB3RN2
USB3RP2
USB3TN2
USB3TP2

AN8
AM8
AR7
AT7
AR8
AP8
AR10
AT10
AM15
AL15
AM13
AN13
AP11
AN11
AR13
AP13

USBP0USBP0+
USBP1USBP1+
USBP2USBP2+

<25>
<25>
<21>
<21>
<20>
<20>

Camera (USBP2)

<14>
<14>
<14>
<14>
<14>
<14>
<14>

PEG_RXN2
PEG_RXP2
PEG_TXN2
PEG_TXP2

<14>
<14>
<14>
<14>

PEG_RXN3
PEG_RXP3
PEG_TXN3
PEG_TXP3

USBP7USBP7+

U6
P4
N4
N2

0.22U/10V_4
0.22U/10V_4

0.22U/10V_4
0.22U/10V_4

0.22U/10V_4
0.22U/10V_4

0.22U/10V_4
0.22U/10V_4
R98
R99

<23>
<23>

SI modify

<23>

L1
L3

GPIO52_ULT
*0_4/S DGPU_PWR_EN_R

PEG_TXN0_C
PEG_TXP0_C

PEG_TXN1_C
PEG_TXP1_C

F8
E8
B23
A23

PEG_TXN2_C
PEG_TXP2_C

H10
G10
B21
C21

PEG_TXN3_C
PEG_TXP3_C

E6
F6
B22
A21

*0_4/S
PCIE_IREF B27
3.01K/F_4 PCIE_RCOMP A27
E15
E13
C43
C42

PCIE_CLKREQ_CR#

DGPU_HOLD_RST# R5
L4
GPIO53_ULT
U7
GPIO55_ULT

GPIO51
GPIO53
GPIO55

USB

DGPU_HOLD_RST#

PCI_PME#

TP46

AD4

<26>
<26>
<26>

USBRBIAS#
USBRBIAS
RSVD
RSVD

PME#

B

LAN

TIE TRACES TOGETHER
CLOSE TO PINS WITH LENGTH
TO RESISTOR

OC0# / GPIO40(SUS)
OC1# / GPIO41(SUS)
OC2# / GPIO42(SUS)
OC3# / GPIO43(SUS)

AJ10
AJ11

<22>

USB_BIAS R140
22.6/F_4

VGA

CLK_PCIE_LANN
CLK_PCIE_LANP
PCIE_CLKREQ_LAN#

<14>
<14>

<14>

AN10
AM10
AL3
AT1
AH2
AV3

CLK_PCIE_WLANN
CLK_PCIE_WLANP
PCIE_CLKREQ_WLAN#

<22>
<22>

G11
F11
C29
B30

F10
E10
C23
C22

<26>
<26>

CLK_PCIE_CRN
CLK_PCIE_CRP

WLAN

GPIO52
GPIO54

F15
G15
B31
A31

F13
PCIE_RXN4_LAN
G13
PCIE_RXP4_LAN
PCIE_TXN4_LAN_C B29
PCIE_TXP4_LAN_C A29

0.1U/10V_4
0.1U/10V_4

Cardreader
PIRQA#/ GPIO77
PIRQB#/ GPIO78
PIRQC#/ GPIO79
PIRQD#/ GPIO80

PCI

<14>

C185
C186

modify

0.1U/10V_4 PCIE_TXN3_WLAN_C
0.1U/10V_4 PCIE_TXP3_WLAN_C

Touch Screen

SI modify to short pad
R417

C190
C191

0.1U/10V_4 PCIE_TXN2_CARD_C
0.1U/10V_4 PCIE_TXP2_CARD_C

PCIE_CLKREQ0#
GPIO77_ULT
TS_INTB#
PIRQC#
PIRQD#

DGPU_PWR_EN

C188
C189

SI
<25>
<25>
<10>
+V1.05S_AUSB3PLL
<26>
<26> WLAN

20111130 Modify USB3.0 for HM70

<15,34,35>

C183
C184

PEG_RXN1
PEG_RXP1
PEG_TXN1
PEG_TXP1

USB2.0(M/B-2) (USBP5)
USBP5USBP5+
USBP6USBP6+

C496
C495

PEG_RXN0
PEG_RXP0
PEG_TXN0
PEG_TXP0

<14>
(USBP1)

USB2.0/USB3.0 COMBO 2nd
USB3RN1
USB3RP1
USB3TN1
USB3TP1

PCIE_RXN4_LAN
PCIE_RXP4_LAN
PCIE_TXN4_LAN
PCIE_TXP4_LAN

<14>
<14>
<14>
<14>

USB2.0 Small board
<25>
<25>
<25>
<25>

Ϭϴ

U19K
G17
F17
C30
C31

CLK_VGA_N
CLK_VGA_P

PCIE_CLKREQ_VGA#

U2

CLK_PCIE_CRN
CLK_PCIE_CRP

B41
A41

PCIE_CLKREQ_CR#

Y5

CLK_PCIE_WLANN
CLK_PCIE_WLANP

C41
B42

PCIE_CLKREQ_WLAN# AD1
CLK_PCIE_LANN
CLK_PCIE_LANP
PCIE_CLKREQ_LAN#
CLK_VGA_N
CLK_VGA_P
PCIE_CLKREQ_VGA#

B38
C37
N1
A39
B39
U5
B37
A37

USB_OC1#
USB_OC2#
USB_OC3#
USB_OC4#

TP65
TP66
TP64
TP100

PCIE_CLKREQ5#

SI modify

T2

PERN1 / USB3RN3
PERP1 / USB3RP3
PETN1 / USB3TN3
PETP1 / USB3TP3

SMBALERT# / GPIO11(SUS)

PERN2/ USB3RN4
PERP2/ USB3RP4
PETN2/ USB3TN4
PETP2/ USB3TP4

SMBCLK
SMBDATA
SML0ALERT# / GPIO60(SUS)

PERN3
PERP3
PETN3
PETP3
PERN4
PERP4
PETN4
PETP4
PERN5_L0
PERP5_L0
PETN5_L0
PETP5_L0

SML0CLK
SML0DATA
SML1ALERT# / PCHHOT# / GPIO73(SUS)
SML1CLK / GPIO75(SUS)
SML1DATA / GPIO74(SUS)

AN2

SMBALERT#

AP2

SMB_PCH_CLK

AH1

SMB_PCH_DAT

AL2

SML0ALERT#

AN1

SMB_ME0_CLK

D

AK1

SMB_ME0_DAT

AU4

SML1ALERT#

AU3

SMB_ME1_CLK

AH3

SMB_ME1_DAT

TP68

SI modify to short pad
R369

PCH_XTAL24_IN

*0_4/S

<26>

TP82

C501 *12P/50V_4

PERN5_L1
PERP5_L1
PETN5_L1
PETP5_L1

1
2

R403
R418
R416
R111
R104
R102

U19N

XTAL24_IN
XTAL24_OUT

A25
B25

XTAL24_IN
XTAL24_OUT

R392
*1M_4

*24MHZ +-30PPM
Y3
3
4

GPIO77_ULT
GPIO52_ULT
GPIO53_ULT
GPIO55_ULT
DGPU_HOLD_RST#
DGPU_HOLD_RST#

1

SMBUS

10K_4
10K_4
10K_4

C- Link

D

*10K_4

R432
R103
R423

PCI-E*

+3V
R428

TS_INTB#
PIRQC#
PIRQD#

2

PERN5_L2
PERP5_L2
PETN5_L2
PETP5_L2

C500 *12P/50V_4

CLKOUT_ITPXDP#
CLKOUT_ITPXDP_P
PERN5_L3
PERP5_L3
PETN5_L3
PETP5_L3

B35
A35

CK_XDP_N_R
RP1 2
CK_XDP_P_R *0_4P2R_4 4

CLKOUT_LPC_0
CLKOUT_LPC_1

PCIE_IREF
PCIE_RCOMP
RSVD
RSVD

AN15
AP15

CLK_PCI_EC_R
CLK_PCI_LPC_R

TP81

1
3

CK_XDP_N
CK_XDP_P

EC34

RP1 install for XDP

<11>
<11>

18P/50V_4

R525 22_4

CLK_24M_KBC
<27>
CLK_24M_DEBUG
<26>

R524 22_4

C

EMI(near PCH)
EC33

18P/50V_4
CLK_PCI_TPM

R5103 22_4

CLKOUT_PCIE0N
CLKOUT_PCIE0P

<24>

EMI(near PCH)
EC44

PCIECLKRQ0# / GPIO18

*18P/50V_4

R384
CLKOUT_PCIE_N1
CLKOUT_PCIE_P1
PCIECLKRQ1# / GPIO19
CLKOUT_PCIE_N2
CLKOUT_PCIE_P2
PCIECLKRQ2# / GPIO20
CLKOUT_PCIE_N3
CLKOUT_PCI_P3
PCIECLKRQ3# / GPIO21
CLKOUT_PCIE_N4
CLKOUT_PCIE_P4

DIFFCLK_BIASREF

CLOCK SIGNALS

PCI/USBOC# Pull-up(CLG)
DGPU_PWR_EN

3

Lynx Point-LP Platform Controller Hub
(HDA,JTAG,SATA)

+V1.05S_AXCK_LCPLL

<10>

3.01K/F_4

RSVD
RSVD
TESTLOW_C35
TESTLOW_C34

PCIECLKRQ4# / GPIO22
TESTLOW_AK8

CLKOUT_PCIE_N5
CLKOUT_PCIE_P5

C26 XCLK_BIASREF

TESTLOW_AL8

K21
M21
C35

R380

10K/F_4

C34

R381

10K/F_4

AK8

R531

10K/F_4

AL8

R141

10K/F_4
B

PCIECLKRQ5# / GPIO23

*HSW_ULT_DDR3L

*HSW_ULT_DDR3L

SMBus/Pull-up(CLG)

CLK_REQ/Strap Pin(CLG)

+3V

SMBus/Pull-up(CLG)

+3V
PCIE_CLKREQ0#
PCIE_CLKREQ5#
PCIE_CLKREQ_WLAN#
PCIE_CLKREQ_LAN#
PCIE_CLKREQ_CR#
PCIE_CLKREQ_VGA#

Q34
5
<13,19,27>

4

MBCLK2

3

SMB_ME1_CLK

R443
R115
R482
R425
R445
R114

10K_4
10K_4
10K_4
10K_4
10K_4
10K_4

for DS3

2
<13,19,27>

1

MBDATA2

+3V_DEEP_SUS

6

*2N7002DW
+3V

A

Q35
+3V
<11,12,13,19,24>

+3V
<11,12,13,19,24>

R495

SMB_RUN_CLK

5

4.7K_4
4

SMB_RUN_DAT
R461

3

2.2K_4
2.2K_4

SMB_PCH_CLK
SMB_PCH_DAT

R168
R493

2.2K_4
2.2K_4

SMB_ME0_CLK
SMB_ME0_DAT

R178
R485

2.2K_4
2.2K_4

SMB_ME1_CLK
SMB_ME1_DAT

R179
R492

10K_4
1K_4

SML1ALERT#
SML0ALERT#

1

6

A

SMB_PCH_DAT

352-(&78
4XDQWD&RPSXWHU,QF

2

4.7K_4

SMB_PCH_CLK

<6,7,9,10,11,12,13,14,15,16,17,19,20,21,22,23,24,25,26,27,32,33,34>
+3V
<6,7,9,10,11>
+3V_DEEP_SUS

2N7002DW
5

R499
R486

SMB_ME1_DAT

4

3

2

Size
Custom

Document Number

Rev
1A

h>dϳͬϵ;W/ͬh^ͬ><Ϳ

Date: Friday, April 26, 2013
1

Sheet

8 of

40

5

4

ͽΪΟΩ͑΁ΠΚΟΥ͞ͽ΁͑΁ΝΒΥΗΠΣΞ͑ʹΠΟΥΣΠΝΝΖΣ͑͹ΦΓ
͙͹͵Ͳ͝ͻ΅Ͳ͸͝΄Ͳ΅Ͳ͚ Haswell (GPIO)

3

2

SI modify to short pad

U19O
TP67
BT_OFF

AM3

RF_OFF

AM2

TP57
TP52

for DS3

R175

+3V_DEEP_SUS

10K_4

LAN_DISABLE#

AM7

GPIO13_ULT

AT3

GPIO14_ULT
TP103
<7>

SI modify

Reserve
<23>

<16,27,36>

AD6

GPIO15_ULT

*0_4 ODD_PRSNT#_R Y1
TP92
T3

R631

ZERO_ODD_DP#
DGPU_PWROK

GPIO24_ULT

AD5

GPIO25_ULT

AM4

GPIO26_ULT

AN3
AN5

GPIO27_ULT

TP5038

GPIO28_ULT

L2

DEVSLP1

DEVSLP1

AD7
P2

DEVSLP0
<24>

AH4

N5

DEVSLP2
GPIO44_ULT

AK4

BOARD_ID4

AG5

ACCEL_INTA#

AG3

BOARD_ID5

AB6

TP for DG
C

TP29

<26>

<26>

ACCEL_INTA#

U4

BT_COMBO_EN#

BT_COMBO_EN#

TP99

GPIO49_ULT

Y3

GPIO50_ULT

P3

BOARD_ID0

AG6

BOARD_ID1

AP1

BOARD_ID2
BOARD_ID3

TP106

MPHY_PWREN

MPHY_PWREN

AT5
C4

GPIO70_ULT
<33>

AL4

TP94

GPIO76_ULT

R456

*0_4/S

Y2
P1

THRMTRIP#

<21>

ACZ_SPKR

RCIN#/ GPIO82

LAN_PHY_PW R_CTRL / GPIO12(DSW )
GPIO13(SUS)
GPIO14(SUS)
GPIO15(SUS)

SERIRQ

PCH_OPI_RCOMP
RSVD

GPIO16

RSVD

<27>

SDIO_D2
SDIO_D1
SDIO_CMD
SDIO_CLK

GSPI1_MOSI
GSPI0_MISO
GSPI1_MISO
UART0_TXD

V4
T4

AW 15

Ϭϵ

I2C0_SCL
I2C1_SCL
I2C0_SDA
SDIO_D3

10K_10P8R_6
+3V
+3V

EC_RCIN#

EC_RCIN#

SERIRQ

R113

10K_4

R522
49.9/F_4

PCH_OPI_RCOMP

+3V
SERIRQ

<27>
<24,27>

RP5
UART0_RXD
UART1_CTS
GSPI0_CS
GSPI1_CS

AF20

10
9
8
7
6

1
2
3
4
5

UART1_RST
UART0_RTS
UART0_CTS
UART1_TXD

D

10K_10P8R_6
+3V

AB21

GPIO Pull-up/Pull-down(CLG)

GPIO25(DSW )

GSPI0_CS/ GPIO83

GPIO26(SUS)
GPIO27(DSW )

GSPI0_CLK/ GPIO84
GSPI0_MISO/ GPIO85

GPIO28(SUS)

GSPI0_MOSI/ GPIO86

DEVSLP0/ GPIO33
GSPI1_CS/ GPIO87
DEVSLP1/ GPIO38
GSPI1_CLK/ GPIO88
DEVSLP2/ GPIO39
GSPI1_MISO/ GPIO89
GPIO44(SUS)
GSPI1_MOSI/ GPIO90

R6

GSPI0_CS

L6

GSPI0_CLK

N6

GSPI0_MISO

L8

GPIO86_ULT

R7

GSPI1_CS

L5

GSPI1_CLK

N7

GSPI1_MISO

K2

GSPI1_MOSI

J1

UART0_RXD

K3

UART0_TXD

J2

UART0_RTS

+3V_DEEP_SUS

SIO_EXT_SCI#
BT_OFF
RF_OFF
GPIO13_ULT
GPIO14_ULT

R174
R177
R139
R176
R489

10K_4
10K_4
10K_4
10K_4
10K_4

GPIO24_ULT
GPIO26_ULT
GPIO28_ULT
GPIO44_ULT
ACCEL_INTA#

R488
R180
R126
R491
R490

10K_4
10K_4
10K_4
10K_4
10K_4

TP33

+3V

GPIO45(SUS)
GPIO46(SUS)

UART0_RXD/ GPIO91

GPIO47(SUS)
GPIO48
GPIO49
GPIO50
GPIO56(SUS)

UART0_TXD/ GPIO92
UART0_RTS/ GPIO93
UART0_CTS/ GPIO94
UART1_RXD/ GPIO0
UART1_TXD/ GPIO1

GPIO57(SUS)
UART1_RST/ GPIO2
GPIO58(SUS)
UART1_CTS/ GPIO3

G1

UART0_CTS

K4

UART1_RXD

G2

UART1_TXD

J3

UART1_RST

J4

UART1_CTS

F2

I2C0_SDA

F3

I2C0_SCL

G4

I2C1_SDA

F1

I2C1_SCL

SI modify

GPIO12 LAN_DISABLE#
SUS -->Check list
+3V -->Datasheet

C

GPIO49_ULT
GPIO50_ULT
ODD_PRSNT#_R
DGPU_PWROK
DEVSLP0
DEVSLP1
DEVSLP2
BT_COMBO_EN#
GPIO70_ULT
EC_RCIN#

R475
R433
R470
R424
R407
R429
R396
R112
R383
R444

10K_4
10K_4
10K_4
10K_4
10K_4
10K_4
10K_4
10K_4
10K_4
10K_4

GPIO76_ULT
MPHY_PWREN
MPHY_PWREN

R434
R465
R464

10K_4
100K_4
*10K_4

GPIO59(SUS)
SDIO_POW ER_EN/ GPIO70

I2C0_SDA/ GPIO4

HSIOPC/ GPIO71

I2C0_SCL/ GPIO5
I2C1_SDA/ GPIO6

BMBUSY# / GPIO76
SPKR/ GPIO81
SDIO_CLK/ GPIO64

<7>

PM_THRMTRIP#

GPIO24 (SUS)

SDIO_CMD/ GPIO65

B

*0_4/S

1
2
3
4
5

1
2
3
4
5

GPIO17

I2C1_SCL/ GPIO7
V2

R405

10
9
8
7
6

10
9
8
7
6

10K_10P8R_6

GPIO10(SUS)

SI modify to short pad
SPKR

D60 PCH_THRMTRIP#

UART1_RXD
I2C1_SDA
GSPI0_CLK
GSPI1_CLK

GPIO9(SUS)

CPU/MISC

D

BT_OFF
RF_OFF

GPIO8(SUS)

GPIO

<26>
<26>

AU2

SIO_EXT_SCI#

SIO_EXT_SCI#

SERIAL IO

<27>

1

RP6
RP7

SPKR

SDIO_D0/ GPIO66
SDIO_D1/ GPIO67
SDIO_D2/ GPIO68
SDIO_D3/ GPIO69

E3

SDIO_CLK

F4

SDIO_CMD

+3VS5
GPIO25_ULT
GPIO27_ULT
LAN_DISABLE#

R134
R161
R136

10K_4
10K_4
10K_4

Close to EC
B

+V1.05S_VCCST

D3
GPIO66_ULT

E4

SDIO_D1

C3

SDIO_D2

E2

SDIO_D3

<7>
PM_THRMTRIP#

R135

1K_4

*HSW_ULT_DDR3L

Model
U83 DIS-14
U83 UMA-15

BOARD_ID5
UMA: 0
DIS: 1

BOARD_ID4
14": 0
15": 1

BOARD_ID3

BOARD_ID2

BOARD_ID1

BOARD_ID0

R132

10K_4

BOARD_ID0

R133

*10K_4

1

0

0

0

0

0

R158

10K_4

BOARD_ID1

R159

*10K_4

0

1

0

0

0

0

R155

10K_4

BOARD_ID2

R154

*10K_4

0

0

0

0

0

0

R160

10K_4

BOARD_ID3

R167

*10K_4

0

0

0

0

0

0

R463

10K_4

BOARD_ID4

R466

*10K_4

A

Rb

0

0

0

0

0

0

0

0

0

0

0

0

R128

*10K_4

BOARD_ID5

Ra R127

+3V_DEEP_SUS

DIS

UMA

Stuff

Ra

Rb

NC

Rb

Ra

A

<6,7,8,10,11,12,13,14,15,16,17,19,20,21,22,23,24,25,26,27,32,33,34>
<6,10,11,24,26,29,30,33,35>

10K_4

352-(&78
4XDQWD&RPSXWHU,QF
Size
Custom

Document Number

4

3

2

Rev
1A

h>dϴͬϵ;'W/KͬD/^Ϳ

Date: Friday, April 26, 2013
5

+3V
+3VS5

Sheet
1

9 of

40

5

4

+1.05V

POWER

VCC1_05=1.741A +V1.05S_CORE_PCH
1U/6.3V_4

C248

1U/6.3V_4

C241

10U/6.3VS_6
D

C5612
TP56

VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05

+V3.3A_DSW_PRTCSUS

VCCSUS3_3

CORE

ϭϬ

C258

VCCRTC

AG10

1U/6.3V_4
+3V_RTC

VCCRTC < 1mA
C564

1U/6.3V_4

C565

0.1U/10V_4

*0.47U/6.3V_4

DCPRTC
AG19
+PCH_VCCDSW AG20

Place close to
Pin AG19 and AG20
SI modify

+V1.05M_ASW
C244

1U/6.3V_4

C528

DCPSUSBYP
DCPSUSBYP

SPI

VCCSPI

AE7 +VCCRTCEXT C233

0.1U/10V_4

Y8VCCSPI=18mA C227

*0.1U/10V_4

C247

AE9
AF9
AG8

VCCASW
VCCASW
VCCASW

*22U/6.3VS_8

VCCASW=658mA

+V1.05M_FHV0
+V1.05M_FHV1

AG14
AG13

+V1.05A_SUS_PCH

AD10
AD8

VCCCLK
VCCCLK
VCCASW
VCCASW

VCCACLKPLL

+1.05V_MODPHY

L26

2.2uH/500mA_6

J18
K19

R117

*0_4/S

L25

2.2uH/500mA_6

+V1.05S_ASATA3PLL

0.1U/10V_4

20mil
+V1.05S_AUSB3PLL

47U/6.3VS_8

C216

47U/6.3VS_8

+3V_DEEP_SUS
+V1.05DX_MODPHY_PCH

R118
*0_4
2.2uH/500mA_6
+V1.05S_AXCK_DCB L4
C209
1U/6.3V_4
C217

D

20mil

SI modify to short pad
+V3.3M_PSPI

+1.05V
+1.05V

1

+3V_DEEP_SUS

AH11

RTC

+3VS5

C249
1U/6.3V_4

2

U19P

J11
H11
H15
AE8
AF22

C204

3

Lynx Point-LP Platform Controller Hub
(HDA,JTAG,SATA)(POWER)

+3V
+1.05V

A20

ICC

DcpSus1=109mA

TP47

+V1.05DX_MODPHY_PCH

C206 1U/6.3V_4

VCCHSIO=1.838A

C197 1U/6.3V_4

C225

VCCHSIO
VCCHSIO
VCCHSIO

VCCCLK

J17

C488

N8
P9

2.2uH/500mA_6
1U/6.3V_4

VCC1_05 VCCMPHY
VCC1_05

VCCCLK
VCCCLK

*1U/6.3V_4

R21
T21

C202

R110

*0_6/S

+V1.05S_SSCFF
+V1.05S_AUSB3PLL

B18

VCCUSB3PLL

RSVD

C489 22U/6.3VS_8

RSVD

C484 22U/6.3VS_8

VCCSATA3PLL=42mA
+V1.05S_ASATA3PLL

C504

1U/6.3V_4

C498

22U/6.3VS_8

B11

VCCACLKPLL=31mA

RSVD
VCCSATA3PLL
VCCSUS3_3
VCCSUS3_3

K18

C210

+1.05V VCCCLK=200mA

SI modify

1U/6.3V_4
R122

*0_6/S

C

C499 1U/6.3V_4

+1.05V

47U/6.3VS_8

C483 47U/6.3VS_8
+V1.05S_SSCF100

C208 *1U/6.3V_4
+V1.05S_AIDLE

+1.05V

K9
L10
M9

+V1.05S_AXCK_LCPLL L27
C503

DCPSUS1
DCPSUS1

+1.05V

C

1U/6.3V_4

M20
V21
AE20 +V3.3A_PSUS
AE21

for DS3

+V3.3A_PSUS
+3VS5

+3V_DEEP_SUS

C490 22U/6.3VS_8
TP23

SI Change to 22uF for Intel recommend
DcpSus3=10mA
+V1.05A_VCCUSB3SUS

USB3

J13

VCCTS1_5=3mA

THERMAL SENSOR

DCPSUS3

R462

VCCTS1_5

J15

+V1.5S_ATS

+1.5V

+V3.3S_PTS

VCC3_3
VCC3_3

HDA

VCCHDA=11mA
+V3.3DX_1.5DX_ADO

+V3.3DX_1.5DX_PAZSUS_PCH
C243

AH14

C203

VCCHDA

AH13

U18

RSVD
VCCAPLL
VCCAPLL

Y20
AA21
W 21

2.2uH PN CV-2205JZ00 SI modify
L5
*0_6/S
+1.05V

VCCAPLL=57mA

C229
+V1.05S_APLLOPI

+V1.05A_USB2SUS

<27>

1U/6.3V_4

SLP_SUS_ON

R426

+3V_DEEP_SUS

C242

+V3.3A_PSUS

22U/6.3VS_8

VCCDSW3_3=114mA+3.3V_A_DSW_P
+3VS5

C250

AC9
AA9

AH10

VCCSUS3_3
VCCSUS3_3

VCCSDIO
VCCSDIO

U8
T9

OUT

IN

GND

1
2
C526
0.1U/10V_4

ON/OFF

C517
*10P/50V_4

B

VCCSDIO=17mA
+V3.3S_1.8S_SDIO_PCH

SUS OSCILLATOR

C218

DCPSUS4

IN

IC(5P) G5243AT11U

C231 *47U/6.3VS_8
C232 *47U/6.3VS_8

GPIO/ LCC

3

*0_4/S

SERIAL IO

DCPSUS2

4

SI modify to short pad

to short pad

B

VCCSUS3_3=63mA

1U/6.3V_4

0.1U/10V_4

5

1U/6.3V_4

DcpSus2=25mA

C524
R446
100K_4

+3V

VCC3_3=41mA

OPI

VRM
TP60

K14
K16

*0_6

AB8 +V1.05A_AOSCSUS

+3V
1U/6.3V_4

DcpSus4=1mA

TP45

VCCDSW 3_3

*1U/6.3V_4

C239

1U/6.3V_4

C246

1U/6.3V_4

USB2
+V3.3S_PCORE

+3V
C205

22U/6.3VS_8

V8
W9

VCC3_3
VCC3_3

RSVD
VCC1_05
VCC1_05

^Dd

AC20
AG16 +V1.05S_DUSB
AG17

+1.05V

*HSW_ULT_DDR3L
+V3.3DX_1.5DX_ADO

A

R129

*0_4/S

R5105

*0_4

SI modify to short pad
+1.5V
+3V

A

352-(&78
4XDQWD&RPSXWHU,QF

<6,7,8,9,11,12,13,14,15,16,17,19,20,21,22,23,24,25,26,27,32,33,34>
+3V
<8>
+V1.05S_AUSB3PLL
+5V
<7>
+V1.05S_ASATA3PLL
<8>
+V1.05S_AXCK_LCPLL
<4,7,11,26,27,30,33,35>
+1.05V
<7,26>
+3V_RTC
<6,9,11,24,26,29,30,33,35>
+3VS5
<2,4,12,13,24,31>
+1.35VSUS
<13,21,24,25,29,31,32,33,34,36>
+5VS5
<6,20,21,23,24,25,26,33>

Size
Custom

Document Number

5

4

3

2

Rev
1A

h>dϵͬϵ;WKtZͲϮͿ

Date: Monday, May 06, 2013

Sheet
1

10of

40

5

4

3

2

1

ϭϭ

CN6
<2>
<2>

D

<4>
<4>

CFG0
CFG1

<4>
<4>

CFG2
CFG3

<2>
<2>

<4>

H_VCCST_PW RGD

H_VCCST_PW RGD

31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60

XDP_PREQ#_CPU
XDP_PRDY#_CPU
R496
CFG1
CFG2
CFG3
OBSFN_B0
OBSFN_B1

XDP_BPM0
XDP_BPM1
<4>
<4>

CFG4
CFG5

<4>
<4>

CFG6
CFG7

R406

1K_4

CFG4
CFG5
CFG6
CFG7

1K_4

VCCST_PW RGD_XDP
DNBSW ON#

+1.05V
C228

0.1U/10V_4

<4>

<8,12,13,19,24>
<8,12,13,19,24>
<2>

PW R_DEBUG

H_SYS_PW ROK_XDP

SMB_RUN_DAT
SMB_RUN_CLK

XDP_TCK1
XDP_TCK0

XDP_TCK0

31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60

30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

OBSFN_C0
OBSFN_C1

CFG17
CFG16

CFG8
CFG9

CFG8
CFG9

CFG10
CFG11

CFG10
CFG11

<4>
<4>

OBSFN_D0
OBSFN_D1

CFG19
CFG18

<4>
<4>

CFG12
CFG13

CFG12
CFG13

<4>
<4>

CFG14
CFG15

CFG14
CFG15

<4>
<4>

<4>
<4>
<4>
<4>

CK_XDP_P
CK_XDP_N

D

+1.05V

<8>
<8>

XDP_RST
XDP_DBRESET_N

C238

0.1U/10V_4

XDP_TDO
XDP_TRST#
XDP_TDI
XDP_TMS
R100

1K_4

CFG3

*SEC_BSH-030-01-L-D-A-TR

C

C

XDP_DBRESET_N

R120

1K_4

H_SYS_PW ROK_XDP

+3V

R170

C215
0.1U/10V_4

*1K_4

+3V_DEEP_SUS

C255
0.1U/10V_4

+3V

C566
0.1U/10V_4
U22

14

APS

B

+3V_DEEP_SUS

<4,27,29,30,31>

+3VS5

XDP_TDI_R

SI modify to short pad
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18

R145

*0_4/S

SUSB#

<6,11,27>

R146
R147
R148

*0_4/S
*0_4/S
*0_4/S

SLP_S5#
SUSC#
SLP_A#

<6>
<6,27>
<6>

R157

*0_4/S

+3V_DEEP_SUS

R144

*0_4

+3VS5

2A

*0_4/S

RTC_RST#

R150

*0_4/S

DNBSW ON#

R151

*0_4/S

SYS_RESET#

R152

*0_4

PCH_SLP_S0_N

R153

*0_4/S

SUSB#

2B

3A

<2>

6

XDP_TDI_CPU

<2>

3B

8

XDP_TMS_CPU

<2>

3OE

12

4A

13
R149

XDP_TDO_CPU

2OE

10
XDP_TRST#

3

B

5

9

XDP_TMS

1B

1OE

4

CN8

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18

1A

1

HW PG

SI modify to short pad

VCC

2

XDP_TDO

4B

4OE
DPAD

<7>

GND

<6,27>

11

XDP_TRST#_CPU

<2,7>

15
7

*SN74CBTLV3126RGYR
<6>

SI modify to short pad
<6,27>
XDP_TDI
<6,11,27>

+V1.05S_VCCST

*ACES_88511-180N

SI modify to short pad
<7>

JTAGX_PCH

<7>

JTAG_TMS_PCH

A

<7>
<7>

JTAG_TDI_PCH
JTAG_TDO_PCH
XDP_TDI_R

<7>

R513

JTAG_TCK_PCH

*0_4

R515

*0_4/S

R511

*51_4

XDP_TDI_R

R510

*0_4

XDP_TDO

R505

*0_4/S

XDP_TCK0

R538

*0_4/S

XDP_TMS

R516

*0_4/S

XDP_TDI

R512

*0_4/S

XDP_TDO

R506

*0_4

XDP_TCK0

R502

*0_4/S

XDP_TCK1

SI modify to short pad
<6>

<6,14,22,23,24,26,27>

SYS_PW ROK

PLTRST#

R166

*0_4/S

H_SYS_PW ROK_XDP

R124

1K_4

XDP_RST

A

352-(&78
4XDQWD&RPSXWHU,QF
ULT

Size

Document Number

Rev
1A

HSW XDP & APS
Friday, AprilDate:
26, 2013
5

4

3

2

11
Sheet
1

of
40

4

D

<3>
<3>
<3>
<3>
<3>
<3>
<3>
<3>
<3>
<3>
<3>
<3>
<3>
<3>
10K/F_4
10K/F_4

R207
R208

<8,11,13,19,24>
<8,11,13,19,24>

M_A_BS#0
M_A_BS#1
M_A_BS#2
M_A_CS#0
M_A_CS#1
M_A_CLKP0
M_A_CLKN0
M_A_CLKP1
M_A_CLKN1
M_A_CKE0
M_A_CKE1
M_A_CAS#
M_A_RAS#
M_A_WE#

SMB_RUN_CLK
SMB_RUN_DAT
<13>
<13>

M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_A15

98
97
96
95
92
91
90
86
89
85
107
84
83
119
80
78

DIMM0_SA0
DIMM0_SA1
SMB_RUN_CLK
SMB_RUN_DAT

109
108
79
114
121
101
103
102
104
73
74
115
110
113
197
201
202
200
116
120

M_A_ODT0
M_A_ODT1

11
28
46
63
136
153
170
187

C

<3>

<3>

M_A_DQ[63:0]

JDIM2A

M_A_A[15:0]

M_A_DQSP[7:0]

M_A_DQSP0
M_A_DQSP1
M_A_DQSP2
M_A_DQSP3
M_A_DQSP4
M_A_DQSP5
M_A_DQSP6
M_A_DQSP7
M_A_DQSN0
M_A_DQSN1
M_A_DQSN2
M_A_DQSN3
M_A_DQSN4
M_A_DQSN5
M_A_DQSN6
M_A_DQSN7

M_A_DQSN[7:0]

WhƌĂĐŬĞƚ

12
29
47
64
137
154
171
188
10
27
45
62
135
152
169
186

5
DQ0 7
DQ1 15
DQ2 17
DQ3 4
DQ4 6
DQ5 16
DQ6 18
DQ7 21
DQ8 23
DQ9 33
DQ10 35
DQ11 22
DQ12 24
DQ13 34
DQ14 36
DQ15 39
DQ16 41
BA0
DQ17 51
BA1
DQ18 53
BA2
DQ19 40
S0#
DQ20 42
S1#
DQ21 50
CK0
DQ22 52
CK0#
DQ23 57
CK1
DQ24 59
CK1#
DQ25 67
CKE0
DQ26 69
CKE1
DQ27 56
CAS#
DQ28 58
RAS#
DQ29 68
W E#
DQ30 70
SA0
DQ31 129
SA1
DQ32 131
SCL
DQ33 141
SDA
DQ34 143
DQ35 130
ODT0
DQ36 132
ODT1
DQ37 140
DQ38 142
DM0
DQ39 147
DM1
DQ40 149
DM2
DQ41 157
DM3
DQ42 159
DM4
DQ43 146
DM5
DQ44 148
DM6
DQ45 158
DM7
DQ46 160
DQ47 163
DQS0
DQ48 165
DQS1
DQ49 175
DQS2
DQ50 177
DQS3
DQ51 164
DQS4
DQ52 166
DQS5
DQ53 174
DQS6
DQ54 176
DQS7
DQ55 181
DQS#0
DQ56 183
DQS#1
DQ57 191
DQS#2
DQ58 193
DQS#3
DQ59 180
DQS#4
DQ60 182
DQS#5
DQ61 192
DQS#6
DQ62 194
DQS#7
DQ63
EZIW
DDR3-DIMM0_H=4.0_STD
ddr-ddrsk-20401-tp4b-204p-ldv
DGMK4000326
IC SOCKET DDR3 SODIMM(204P,H4.0,STD)
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC#
A13
A14
A15

PC2100 DDR3 SDRAM SO-DIMM
(204P)

<3>

3

M_A_DQ5
M_A_DQ4
M_A_DQ6
M_A_DQ2
M_A_DQ1
M_A_DQ0
M_A_DQ7
M_A_DQ3
M_A_DQ13
M_A_DQ12
M_A_DQ14
M_A_DQ15
M_A_DQ9
M_A_DQ8
M_A_DQ11
M_A_DQ10
M_A_DQ21
M_A_DQ20
M_A_DQ19
M_A_DQ23
M_A_DQ17
M_A_DQ16
M_A_DQ18
M_A_DQ22
M_A_DQ24
M_A_DQ25
M_A_DQ31
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ26
M_A_DQ36
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ32
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ42
M_A_DQ40
M_A_DQ41
M_A_DQ47
M_A_DQ43
M_A_DQ49
M_A_DQ52
M_A_DQ50
M_A_DQ51
M_A_DQ55
M_A_DQ48
M_A_DQ54
M_A_DQ53
M_A_DQ59
M_A_DQ56
M_A_DQ63
M_A_DQ58
M_A_DQ57
M_A_DQ60
M_A_DQ62
M_A_DQ61

2

<3>

1

JDIM2B

75
76
81
82
87
88
93
94
99
100
105
106
111
112
117
118
123
124

+3V
<2,13>

<13>
PM_EXTTS#0
DDR3_DRAMRST#

SI modify to short pad
SMDDR_VREF_DQ0_M1 R204
<12,13>

*0_6/S

+SMDDR_VREF_DIMM

VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
VDD10
VDD11
VDD12
VDD13
VDD14
VDD15
VDD16
VDD17
VDD18

199

+3V

R198

ϭϮ

+1.35VSUS

2.48A

VDDSPD

77
122
125

10K/F_4

NC1
NC2
NCTEST

198
30

PM_EXTTS#0

EVENT#
RESET#

C320
*0.1U/10V_4
1
+SMDDR_VREF_DQ0
+SMDDR_VREF_DIMM 126

VREF_DQ
VREF_CA

2
3
8
9
13
14
19
20
25
26
31
32
37
38
43

VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15

PC2100 DDR3 SDRAM SO-DIMM
(204P)

5

VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52

44
48
49
54
55
60
61
65
66
71
72
127
128
133
134
138
139
144
145
150
151
155
156
161
162
167
168
172
173
178
179
184
185
189
190
195
196

D

C

VTT1
VTT2
GND
GND

203
204

+0.75V_DDR_VTT

205
206

DDR3-DIMM0_H=4.0_STD
ddr-ddrsk-20401-tp4b-204p-ldv
DGMK4000326
IC SOCKET DDR3 SODIMM(204P,H4.0,STD)

<6,7,8,9,10,11,13,14,15,16,17,19,20,21,22,23,24,25,26,27,32,33,34>

+3V

<2,4,13,24,31>
+1.35VSUS
<13,31>
+0.75V_DDR_VTT
<12,13>
+SMDDR_VREF_DIMM

B

B

Place these Caps near So-Dimm0.
1uF/10uF 4pcs on each side of connector

+VA

C324

1U/6.3V_4

C333

1U/6.3V_4

C330

1U/6.3V_4

C328

1U/6.3V_4

+1.35VSUS

SI add for EMI

*120P/50V_4

EC14

*120P/50V_4

EC6

*120P/50V_4

EC15

*120P/50V_4

EC7

*120P/50V_4

EC16

*120P/50V_4

EC35

120P/50V_4

EC4

*0.1U/10V_4

EC10

*120P/50V_4

EC13

*0.1U/10V_4

EC8

*120P/50V_4

EC43

*0.1U/10V_4

EC9

*120P/50V_4

EC42

*0.1U/10V_4

C325

1U/6.3V_4

C318

1U/6.3V_4

C311

1U/6.3V_4

C322

1U/6.3V_4

SMDDR_VREF_DQ0_M3

DDR_VTTREF

C313

1U/6.3V_4

C312

1U/6.3V_4

C310

1U/6.3V_4

C309

1U/6.3V_4

C329

10U/6.3V_6

C319

R200

*0_6
R202
1.8K/F_4

SMDDR_VREF_DQ0_M3 R203

R205

SMDDR_VREF_DQ0_M1

2/F_6

10U/6.3V_6

+1.35VSUS
C317
0.022U/25V_4

R201
1.8K/F_4

24.9/F_4

C327

10U/6.3V_6

C326

10U/6.3V_6

R215
1.8K/F_4

DDR_VTTREF
+SMDDR_VREF_DIMM
C335

*0.1U/10V_4

C332

*2.2U/6.3V_6

<3>

+SMDDR_VREF_DQ0

A

+0.75V_DDR_VTT

<3>

DDR_VTTREF

SM_VREF

2

EC45
2200P/50V_4

EC5

<13,31>

R214

*0_6

R217

2/F_6

+SMDDR_VREF_DIMM

R213
1.8K/F_4

1

+1.35VSUS

1

For EMI RESERVE

VREF DQ0 M1 Solution

+0.75V_DDR_VTT

2

+1.35VSUS

+1.35VSUS

C347
0.022U/25V_4

R220

A

C307

*0.1U/10V_4

C316

*2.2U/6.3V_6

24.9/F_4

352-(&78
4XDQWD&RPSXWHU,QF

EC12

*120P/50V_4

C314

10U/6.3V_6

EC11

*120P/50V_4

C315

10U/6.3V_6

C340

10U/6.3V_6

C323

10U/6.3V_6

C302

0.1U/10V_4

C343

10U/6.3V_6

C308

2.2U/6.3V_6

+3V

Size
Custom

Document Number

5

4

3

2

Rev
1A

Zϯ/DDϬͲ^d;ϰ͘Ϭ,Ϳ

Date: Friday, April 26, 2013

Sheet
1

12of

40

5

4

3

2

M_B_DQ[63:0]

1

ϭϯ

<3>
+1.35VSUS

<8,11,12,19,24>
<8,11,12,19,24>

DIMM1_SA0
DIMM1_SA1

SMB_RUN_CLK
SMB_RUN_DAT
M_B_ODT0
M_B_ODT1

116
120
11
28
46
63
136
153
170
187

C

<3>

<3>

M_B_DQSP[7:0]

M_B_DQSP2
M_B_DQSP0
M_B_DQSP1
M_B_DQSP3
M_B_DQSP4
M_B_DQSP5
M_B_DQSP6
M_B_DQSP7
M_B_DQSN2
M_B_DQSN0
M_B_DQSN1
M_B_DQSN3
M_B_DQSN4
M_B_DQSN5
M_B_DQSN6
M_B_DQSN7

M_B_DQSN[7:0]

12
29
47
64
137
154
171
188
10
27
45
62
135
152
169
186

BA0
BA1
BA2
S0#
S1#
CK0
CK0#
CK1
CK1#
CKE0
CKE1
CAS#
RAS#
W E#
SA0
SA1
SCL
SDA
ODT0
ODT1
DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7
DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS#0
DQS#1
DQS#2
DQS#3
DQS#4
DQS#5
DQS#6
DQS#7

VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
VDD10
VDD11
VDD12
VDD13
VDD14
VDD15
VDD16
VDD17
VDD18

199

+3V

VDDSPD

77
122
125

<2,12>

SI modify to short pad

PM_EXTTS#0

<12>
PM_EXTTS#0
DDR3_DRAMRST#
C321

SMDDR_VREF_DQ1_M1 R199

*0_6/S

<12>

*0.1U/10V_4
+SMDDR_VREF_DQ1

+SMDDR_VREF_DIMM

NC1
NC2
NCTEST

198
30

EVENT#
RESET#

1
126

VREF_DQ
VREF_CA

2
3
8
9
13
14
19
20
25
26
31
32
37
38
43

VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15

U3
<8,19,27>
<8,19,27>

MBCLK2
MBDATA2

+3V

MBCLK2

8

2N7002
Q3

MBDATA2

7

PM_EXTTS#0

6

R185

*10K/F_4

4

VCC

SDA

DXP

ALERT#

DXN

OVERT#

GND

+3V

2

3

2

Q5
DTC144EUA

2

1

R209

66.5/F_4

R210

66.5/F_4

R195

66.5/F_4

R194

66.5/F_4

M_A_ODT0

<12>

M_A_ODT1

<12>

+0.75V_DDR_VTT

+1.35VSUS
C303

1U/6.3V_4

M_B_ODT0

C306

1U/6.3V_4

M_B_ODT1

C341

1U/6.3V_4

C293

DDR_VTT_PG_CTRL

1

2

C336
0.1U/10V_4

1

3

R216

*0_4

51216S3

<31>

Q4
2N7002K
A

DDR_PG_CNTL

DDR_PG_CNTL

<2>

R219
*2M/F_4

<2,4,12,24,31>
+1.35VSUS
<12,31>
+0.75V_DDR_VTT
<6,7,8,9,10,11,12,14,15,16,17,19,20,21,22,23,24,25,26,27,32,33,34>
5

4

DDR3 Thermal Sensor

DDR_THERMDA

3
2

C272
*2200P/50V_4

5

Q2
*METR3904-G

C304

1U/6.3V_4

C301

1U/6.3V_4

C300

1U/6.3V_4

C305

1U/6.3V_4

C299

1U/6.3V_4

C287
C292

10U/6.3V_6
10U/6.3V_6

C284
C283

10U/6.3V_6
10U/6.3V_6

C286
C285

10U/6.3V_6
10U/6.3V_6

C291
C294

10U/6.3V_6
10U/6.3V_6

B

DĂŝŶ͗>ϬϬϭϰϭϮϬϬϯ

DϭϰϭϮͲϭͲ>ͲdZ;ϵϴŚͿ

ϮŶĚ͗>ϬϬϬϰϯϭϬϭϰ

dDWϰϯϭ'

DDR_VTTREF

DDR_VTTREF

R192

*0_6

SMDDR_VREF_DQ1_M1

SMDDR_VREF_DQ1_M3

R191

2/F_6

R188
1.8K/F_4

+SMDDR_VREF_DQ1
C296

*0.1U/10V_4

C298

*2.2U/6.3V_6

<3>

SMDDR_VREF_DQ1_M3

1

3

*0.01U/16V_4

1

DDR_THERMDC

1uF/10uF 4pcs on each side of connector

R218
220K_4

205
206

GND
GND

C271

SCLK

Place these Caps near So-Dimm1.
+1.35VSUS

C

+0.75V_DDR_VTT

Local Thermal Sensor

+5VPCU
+5VS5

D

203
204

VTT1
VTT2

*EMC1412-1-ACZL-TR
Need Check PN(EOD)

R212
100K_4

44
48
49
54
55
60
61
65
66
71
72
127
128
133
134
138
139
144
145
150
151
155
156
161
162
167
168
172
173
178
179
184
185
189
190
195
196

VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52

DDR3-DIMM1_H=4.0_RVS
ddr-ddrrk-20401-tp4b-204p-ruv
DGMK4000263
IC SOCKET DDR3 SODIMM (204P, H4.0, RVS)

DDR3-DIMM1_H=4.0_RVS
ddr-ddrrk-20401-tp4b-204p-ruv
DGMK4000263
IC SOCKET DDR3 SODIMM (204P, H4.0, RVS)

B

75
76
81
82
87
88
93
94
99
100
105
106
111
112
117
118
123
124

2.48A

3

10K/F_4
10K/F_4

109
108
79
114
121
101
103
102
104
73
74
115
110
113
197
201
202
200

JDIM1B

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63

M_B_DQ22
M_B_DQ23
M_B_DQ21
M_B_DQ18
M_B_DQ16
M_B_DQ17
M_B_DQ20
M_B_DQ19
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ7
M_B_DQ2
M_B_DQ3
M_B_DQ1
M_B_DQ0
M_B_DQ9
M_B_DQ8
M_B_DQ11
M_B_DQ10
M_B_DQ12
M_B_DQ13
M_B_DQ15
M_B_DQ14
M_B_DQ26
M_B_DQ27
M_B_DQ29
M_B_DQ28
M_B_DQ30
M_B_DQ31
M_B_DQ24
M_B_DQ25
M_B_DQ32
M_B_DQ33
M_B_DQ38
M_B_DQ34
M_B_DQ36
M_B_DQ37
M_B_DQ35
M_B_DQ39
M_B_DQ40
M_B_DQ43
M_B_DQ47
M_B_DQ46
M_B_DQ41
M_B_DQ42
M_B_DQ44
M_B_DQ45
M_B_DQ52
M_B_DQ51
M_B_DQ54
M_B_DQ48
M_B_DQ49
M_B_DQ55
M_B_DQ50
M_B_DQ53
M_B_DQ63
M_B_DQ62
M_B_DQ59
M_B_DQ60
M_B_DQ56
M_B_DQ57
M_B_DQ61
M_B_DQ58

1

+3V

R189
R190

M_B_BS#0
M_B_BS#1
M_B_BS#2
M_B_CS#0
M_B_CS#1
M_B_CLKP0
M_B_CLKN0
M_B_CLKP1
M_B_CLKN1
M_B_CKE0
M_B_CKE1
M_B_CAS#
M_B_RAS#
M_B_WE#

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC#
A13
A14
A15

5
7
15
17
4
6
16
18
21
23
33
35
22
24
34
36
39
41
51
53
40
42
50
52
57
59
67
69
56
58
68
70
129
131
141
143
130
132
140
142
147
149
157
159
146
148
158
160
163
165
175
177
164
166
174
176
181
183
191
193
180
182
192
194

R193
C281

0.1U/10V_4

C282

2.2U/6.3V_6

24.9/F_4

2

D

<3>
<3>
<3>
<3>
<3>
<3>
<3>
<3>
<3>
<3>
<3>
<3>
<3>
<3>

98
97
96
95
92
91
90
86
89
85
107
84
83
119
80
78

M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
M_B_A14
M_B_A15

PC2100 DDR3 SDRAM SO-DIMM
(204P)

JDIM1A

M_B_A[15:0]

PC2100 DDR3 SDRAM SO-DIMM
(204P)

<3>

C290
0.022U/25V_4
A

352-(&78
4XDQWD&RPSXWHU,QF
Size
Custom

+3V

Document Number

3

2

Rev
1A

Zϯ/DDϭͲZs^;ϰ͘Ϭ,Ϳ

Date: Friday, April 26, 2013

Sheet
1

13of

40

1

2

+1.05V_GFX

3

22U/6.3VS_6
22U/6.3VS_6
10U/6.3VS_6
10U/6.3VS_6
4.7U/6.3V_6

Under GPU

C8089
C8079

1U/6.3V_4
1U/6.3V_4

C8122 0.1U/10V_4
C8120 4.7U/6.3V_6
C81304.7U/6.3V_6

Near GPU

AA10
AA12
AA13
AA16
AA18
AA19
AA20
AA21
AB22
AC23
AD24
AE25
AF26
AF27

AA8
AA9
AB8

F2

VGPU_CORE_SENSE

PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ

*200/F_4

D

F1

R8335 PEX_TSTCLK AF22
PEX_TSTCLK# AE22
CX300T30001 Change to 0ohm

C8068
C8069

0.1U/10V_4

C8097

PEX_PLLVDD

VDD_SENSE

GND_SENSE

PEX_TSTCLK_OUT
PEX_TSTCLK_OUT

AA14
AA15

PEX_PLLVDD
PEX_PLLVDD

Under GPU

PEX_PLLVDD = 130mA
10K/F_4

R8346 TESTMODE

10K/F_4

PEX_REFCLK
PEX_REFCLK

AE8
AD8

AD9

R8333 PEX_TERMP AF25

PEX_TX0
PEX_TX0

AC9 PEG_RXP0_C C8167
AB9 PEG_RXN0_C C8168

PEX_RX0
PEX_RX0

AG6
AG7

PEX_TX1
PEX_TX1

AB10 PEG_RXP1_C C8155
AC10 PEG_RXN1_C C8156

PEX_RX1
PEX_RX1

AF7
AE7

PEX_TX2
PEX_TX2

AD11 PEG_RXP2_C C8154
AC11 PEG_RXN2_C C8153

PEX_RX2
PEX_RX2

AE9
AF9

PEX_TX3
PEX_TX3

AC12 PEG_RXP3_C C8170
AB12 PEG_RXN3_C C8169

PEX_RX3
PEX_RX3

AG9
AG10

PEX_TX4
PEX_TX4

AB13
AC13
AF10
AE10

PEX_TX5
PEX_TX5

AD14
AC14

PEX_RX5
PEX_RX5

AE12
AF12

PEX_TX6
PEX_TX6

AC15
AB15

PEX_RX6
PEX_RX6

AG12
AG13

PEX_TX7
PEX_TX7

AB16
AC16

PEX_RX7
PEX_RX7

AF13
AE13

NC
NC

PEX_TX8
PEX_TX8

AD17
AC17

NC
NC

PEX_RX8
PEX_RX8

AE15
AF15

NC
NC

PEX_TX9
PEX_TX9

AC18
AB18

PEX_RX9
PEX_RX9

AG15
AG16

NC
NC

PEX_TX10
PEX_TX10

AB19
AC19

NC
NC

PEX_RX10
PEX_RX10

AF16
AE16

NC
NC

PEX_TX11
PEX_TX11

AD20
AC20

NC
NC

PEX_RX11
PEX_RX11

AE18
AF18

NC
NC

PEX_TX12
PEX_TX12

AC21
AB21

NC
NC

PEX_RX12
PEX_RX12

AG18
AG19

NC
NC

PEX_TX13
PEX_TX13

AD23
AE23

NC
NC

PEX_RX13
PEX_RX13

NC
NC

PEX_TX14
PEX_TX14

AF24
AE24

NC
NC

PEX_RX14
PEX_RX14

AE21
AF21

NC
NC

PEX_TX15
PEX_TX15

AG24
AG25

PEX_RX15
PEX_RX15

AG21
AG22

NC
NC

TESTMODE

GF117

2

<17>

CLK_VGA_P
CLK_VGA_N

<8>
<8>

C8105
C8518
C8088
C8512
C8118
C8112
C8113
C8081
C8519
C8514
C8517
C8523
C8100
C8107
C8087

+3V_GFX

0.22U/10V_4
0.22U/10V_4

PEG_RXP0
PEG_RXN0

<8>
<8>

PEG_TXP0
PEG_TXN0
0.22U/10V_4
0.22U/10V_4

<8>
<8>

PEG_RXP1
PEG_RXN1

<8>
<8>

PEG_TXP1
PEG_TXN1
0.22U/10V_4
0.22U/10V_4

<8>
<8>

PEG_TXP2
PEG_TXN2
0.22U/10V_4
0.22U/10V_4

2
1
C8096
330u_2.5V_3528

<8>
<8>

PEG_RXP2
PEG_RXN2

K10
K12
K14
K16
K18
L11
L13
L15
L17
M10
M12
M14
M16
M18
N11
N13
N15
N17
P10
P12
P14
P16
P18
R11
R13
R15
R17
T10
T12
T14
T16
T18
U11
U13
U15
U17
V10
V12
V14
V16
V18

0.1U/10V_4
0.1U/10V_4
0.1U/10V_4
0.1U/10V_4
4.7U/6.3V_6
4.7U/6.3V_6
4.7U/6.3V_6
4.7U/6.3V_6
4.7U/6.3V_6
4.7U/6.3V_6
4.7U/6.3V_6
4.7U/6.3V_6
4.7U/6.3V_6
4.7U/6.3V_6
4.7U/6.3V_6

<8>
<8>

PEG_RXP3
PEG_RXN3

<8>
<8>

PEG_TXP3
PEG_TXN3

<8>
<8>

C8085
C8529

22U/6.3VS_6
47U/6.3VS_8

C8099
C8114
C8515
C8516
C8084

4.7U/6.3V_6
4.7U/6.3V_6
4.7U/6.3V_6
4.7U/6.3V_6
4.7U/6.3V_6

Near GPU

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

A

14/14 XVDD/VDD33

NC
NC
NC

VDD33
VDD33
VDD33
VDD33

F11

3V3AUX_NC

V5
V6

FERMI_RSVD1_NC
FERMI_RSVD2_NC

G10
G12
G8
G9

+3V_GFX

Near GPU

C8115
1
C8101

C8132
C8131
C8126

4.7U/6.3V_6
2 1U/10V_6

0.1U/10V_4
0.1U/10V_4
0.1U/10V_4

CONFIGURABLE
POWER CHANNELS

Under GPU

* nc on substrate

G1
G2
G3
G4
G5
G6
G7

XPWR_G1
XPWR_G2
XPWR_G3
XPWR_G4
XPWR_G5
XPWR_G6
XPWR_G7

V1
V2

XPWR_V1
XPWR_V2

W1
W2
W3
W4

bga595-nvidia-n13p-gv2-s-a2

B

XPWR_W1
XPWR_W2
XPWR_W3
XPWR_W4
bga595-nvidia-n13p-gv2-s-a2

COMMON

COMMON

sϯϯ
нϯ͘ϯsͺ'&y

U8014
MC74VHC1G08DFT2G
<6,11,22,23,24,26,27>
<8>

C8528
0.1U/10V_4

Power up
sequence

ƚхϬ
C

ƚхϬ

&sY
нϭ͘ϱsͺ'&y

2

PLTRST#

4

PEGX_RST#

Wyͺs
нϭ͘Ϭϱsͺ'&y

1

DGPU_HOLD_RST#

Ess
нsͺ'&yͺKZ

R8388
100K/F_4

ƚхϬ
ƚхсϬ

/&W;&Ϳͺ/Ks
нϭ͘Ϭϱsͺ'&y

+3V_GFX

R8361
4.7K_4
CLKREQ_C1

PCIE_CLKREQ_VGA#

PEX_CLKREQ#

2

Q8028
DTC144EUA
D

2

Q8029
DTC144EUA

Power down
sequence
<8>

352-(&78
4XDQWD&RPSXWHU,QF

GF119

Size
Custom

COMMON

3

VDD33 = 56mA

U8011C

AD10
AD7
B19

PEX_TERMP
bga595-nvidia-n13p-gv2-s-a2

1

PEGX_RST#

+3V

AF19
AE19

NC
NC

2.49K/F_4

R8360

PEX_SVDD_3V3

0_6
4.7U/6.3V_6
1U/6.3V_4

AC6 PEX_CLKREQ#

PEX_RX4
PEX_RX4

PEX_PLL_HVDD
PEX_PLL_HVDD

C

VSS_GPU_SENSE

PEX_CLKREQ

U8011E
11/14 NVVDD

PEX_PLL_HVDD +
PEX_SVDD_3V3 = 143mA
+3V_GFX

100/F_4

+

Near GPU

*0.1U/10V_4

R8391

PEX_RST

5

C8117
C8094
C8121
C8109
C8090

C8521

AC7 VGA_RST#

Under GPU
PEX_IOVDD
PEX_IOVDD
PEX_IOVDD
PEX_IOVDD
PEX_IOVDD
PEX_IOVDD

3

+1.05V_GFX

Near GPU

ϭϰ

+VGACORE

NVDD = 32.22 ~ 26.66 A

3

1U/6.3V_4
1U/6.3V_4

AB6

PEX_WAKE

AA22
AB23
AC24
AD25
AE26
AE27

PEX_IOVDD + PEX_IOVDDQ = 1.042A

+1.05V_GFX

8

1/14 PCI_EXPRESS

Under GPU

R8051

7

1

22U/6.3VS_6
22U/6.3VS_6
10U/6.3VS_6
10U/6.3VS_6
4.7U/6.3V_6

3

A

<34>

6

1

C8110
C8111

<34>

5

U8011A

Near GPU

C8102
C8128
C8135
C8106
C8070

B

4

Document Number

4

5

6

7

Rev
2A

N14M-GS (PCIE I/F) /NVDD

Date: Friday, April 26, 2013

Sheet

14
8

of

40

1

2

3

4

5

6

7

8

ϭϱ

U8011B

A

10K/F_4 PS_FB_CLAMP F3
R8380

0_4

FBA_ODT_L

FBA_CMD2

R8007

10K/F_4

FBA_ODT_H

FBA_CMD18

R8001

10K/F_4

FBA_RST#

FBA_CMD5

R8002

10K/F_4

FBA_CKE_L

FBA_CMD3

R8012

10K/F_4

FBA_CKE_H

FBA_CMD19

R8000

10K/F_4

TP8064

FBA_CMD1

<18>

FBA_CMD0

TP8000

<18>
<18>
<18>
<18>
<18>
<18>
<18>
<18>
<18>
<18>
<18>
<18>
<18>
<18>
<18>
FBA_CMD17

FBA_CMD2
FBA_CMD3
FBA_CMD4
FBA_CMD5
FBA_CMD6
FBA_CMD7
FBA_CMD8
FBA_CMD9
FBA_CMD10
FBA_CMD11
FBA_CMD12
FBA_CMD13
FBA_CMD14
FBA_CMD15
FBA_CMD16

TP8065

<18>
<18>
<18>
<18>
<18>
<18>
<18>
<18>
<18>
<18>
<18>
<18>
<18>
FBA_CMD31

FBA_CMD18
FBA_CMD19
FBA_CMD20
FBA_CMD21
FBA_CMD22
FBA_CMD23
FBA_CMD24
FBA_CMD25
FBA_CMD26
FBA_CMD27
FBA_CMD28
FBA_CMD29
FBA_CMD30

B

NC

GF119

FB_CLAMP

C27
C26
E24
F24
D27
D26
F25
F26
F23
G22
G23
G24
F27
G25
G27
G26
M24
M23
K24
K23
M27
M26
M25
K26
K22
J23
J25
J24
K27
K25
J27
J26

GF117

FBA_CMD0
FBA_CMD1
FBA_CMD2
FBA_CMD3
FBA_CMD4
FBA_CMD5
FBA_CMD6
FBA_CMD7
FBA_CMD8
FBA_CMD9
FBA_CMD10
FBA_CMD11
FBA_CMD12
FBA_CMD13
FBA_CMD14
FBA_CMD15
FBA_CMD16
FBA_CMD17
FBA_CMD18
FBA_CMD19
FBA_CMD20
FBA_CMD21
FBA_CMD22
FBA_CMD23
FBA_CMD24
FBA_CMD25
FBA_CMD26
FBA_CMD27
FBA_CMD28
FBA_CMD29
FBA_CMD30
FBA_CMD31

VMA_CLK0
VMA_CLK0#
VMA_CLK1
VMA_CLK1#

E18 VMA_DQ0
F18 VMA_DQ1
E16 VMA_DQ2
F17 VMA_DQ3
D20 VMA_DQ4
D21 VMA_DQ5
F20 VMA_DQ6
E21 VMA_DQ7
E15 VMA_DQ8
D15 VMA_DQ9
F15 VMA_DQ10
F13 VMA_DQ11
C13 VMA_DQ12
B13 VMA_DQ13
E13 VMA_DQ14
D13 VMA_DQ15
B15 VMA_DQ16
C16 VMA_DQ17
A13 VMA_DQ18
A15 VMA_DQ19
B18 VMA_DQ20
A18 VMA_DQ21
A19 VMA_DQ22
C19 VMA_DQ23
B24 VMA_DQ24
C23 VMA_DQ25
A25 VMA_DQ26
A24 VMA_DQ27
A21 VMA_DQ28
B21 VMA_DQ29
C20 VMA_DQ30
C21 VMA_DQ31
R22 VMA_DQ32
R24 VMA_DQ33
T22 VMA_DQ34
R23 VMA_DQ35
N25 VMA_DQ36
N26 VMA_DQ37
N23 VMA_DQ38
N24 VMA_DQ39
V23 VMA_DQ40
V22 VMA_DQ41
T23 VMA_DQ42
U22 VMA_DQ43
Y24 VMA_DQ44
AA24 VMA_DQ45
Y22 VMA_DQ46
AA23 VMA_DQ47
AD27 VMA_DQ48
AB25 VMA_DQ49
AD26 VMA_DQ50
AC25 VMA_DQ51
AA27 VMA_DQ52
AA26 VMA_DQ53
W 26 VMA_DQ54
Y25 VMA_DQ55
R26 VMA_DQ56
T25 VMA_DQ57
N27 VMA_DQ58
R27 VMA_DQ59
V26 VMA_DQ60
V27 VMA_DQ61
W 27 VMA_DQ62
W 25 VMA_DQ63

VMA_DQ[63:0]

<18>

FBVDDQ + FBVDD = 3.116A

U8011F
13/14 GND

+1.5V_GFX

FBA_DQM0
FBA_DQM1
FBA_DQM2
FBA_DQM3
FBA_DQM4
FBA_DQM5
FBA_DQM6
FBA_DQM7

D19
D14
C17
C22
P24
W 24
AA25
U25

0.1U/10V_4
0.1U/10V_4

1
C8076
1
C8051
C8077
C8086
C8480

21U/10V_6
21U/10V_6
4.7U/6.3V_6
10U/6.3V_6
22U/6.3VS_6

B26
C25
E23
E26
F14
F21
G13
G14
G15
G16
G18
G19
G20
G21
H24
H26
J21
K21
L22
L24
L26
M21
N21
R21
T21
V21
W 21

FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ

FB_CAL_PD_VDDQ

VMA_DM0
VMA_DM1
VMA_DM2
VMA_DM3
VMA_DM4
VMA_DM5
VMA_DM6
VMA_DM7

F22
J22

FBA_DEBUG0
FBA_DEBUG1

D24
D25
N22
M22

FBA_CLK0
FBA_CLK0
FBA_CLK1
FBA_CLK1

FBA_DQS_WP0
FBA_DQS_WP1
FBA_DQS_WP2
FBA_DQS_WP3
FBA_DQS_WP4
FBA_DQS_WP5
FBA_DQS_WP6
FBA_DQS_WP7

E19 VMA_WDQS0
C15 VMA_WDQS1
B16 VMA_WDQS2
B22 VMA_WDQS3
R25 VMA_WDQS4
W 23 VMA_WDQS5
AB26 VMA_WDQS6
T26 VMA_WDQS7

D18
C18
D17
D16
T24
U24
V24
V25

FBA_WCK01
FBA_WCK01
FBA_WCK23
FBA_WCK23
FBA_WCK45
FBA_WCK45
FBA_WCK67
FBA_WCK67

FBA_DQS_RN0
FBA_DQS_RN1
FBA_DQS_RN2
FBA_DQS_RN3
FBA_DQS_RN4
FBA_DQS_RN5
FBA_DQS_RN6
FBA_DQS_RN7

F19
C14
A16
A22
P25
W 22
AB27
T27

A2
AB17
AB20
AB24
AC2
AC22
AC26
AC5
AC8
AD12
AD13
A26
AD15
AD16
AD18
AD19
AD21
AD22
AE11
AE14
AE17
AE20
AB11
AF1
AF11
AF14
AF17
AF20
AF23
AF5
AF8
AG2
AG26
AB14
B1
B11
B14
B17
B20
B23
B27
B5
B8
E11
E14
E17
E2
E20
E22
E25
E5
E8
H2
H23
H25
H5
K11
K13
K15
K17
L10
L12
L14
L16
L18
L2
L23
L25
L5
M11

U8011D
12/14 FBVDDQ

C8474
C8074

FB_CAL_PU_GND

C

<18>
<18>
<18>
<18>

VMA_DQ[63:0]

VMA_DM[7:0]

<18>

FB_CALTERM_GND

D22 FB_CAL_PD_VDDQ

R8046

40.2/F_4

C24 FB_CAL_PU_GND

R8050

42.2/F_4

B25

R8047

51.1/F_4

FB_CAL_TERM_GND

+1.5V_GFX

bga595-nvidia-n13p-gv2-s-a2
COMMON

VMA_WDQS[7:0]

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

M13
M15
M17
N10
N12
N14
N16
N18
P11
P13
P15
P17
P2
P23
P26
P5
R10
R12
R14
R16
R18
T11
T13
T15
T17
U10
U12
U14
U16
U18
U2
U23
U26
U5
V11
V13
V15
V17
Y2
Y23
Y26
Y5

GND
GND

AA7
AB7

A

B

C

<18>
bga595-nvidia-n13p-gv2-s-a2 COMMON

For support GC6
+3V

Change Default setting from DGPU_PWR_EN for tuning sequence

VMA_RDQS0
VMA_RDQS1
VMA_RDQS2
VMA_RDQS3
VMA_RDQS4
VMA_RDQS5
VMA_RDQS6
VMA_RDQS7

VMA_RDQS[7:0]

<18>
<8,34,35>
<34,35>

DGPU_PWR_EN
DGPU_VC_EN
<17,27>

R8402

U8013
NL17SZ32DFT2G

C8522
0.1U/10V_4

2

*0_4

4

DGPU_FB_EN

1

FB_CLAMP

<36>

3

FB_PLLAVDD = 55mA

PV shortpad
R8401
*0_4/S

5

R8379
FB_CLAMP

2/14 FBA
FBA_D0
FBA_D1
FBA_D2
FBA_D3
FBA_D4
FBA_D5
FBA_D6
FBA_D7
FBA_D8
FBA_D9
FBA_D10
FBA_D11
FBA_D12
FBA_D13
FBA_D14
FBA_D15
FBA_D16
FBA_D17
FBA_D18
FBA_D19
FBA_D20
FBA_D21
FBA_D22
FBA_D23
FBA_D24
FBA_D25
FBA_D26
FBA_D27
FBA_D28
FBA_D29
FBA_D30
FBA_D31
FBA_D32
FBA_D33
FBA_D34
FBA_D35
FBA_D36
FBA_D37
FBA_D38
FBA_D39
FBA_D40
FBA_D41
FBA_D42
FBA_D43
FBA_D44
FBA_D45
FBA_D46
FBA_D47
FBA_D48
FBA_D49
FBA_D50
FBA_D51
FBA_D52
FBA_D53
FBA_D54
FBA_D55
FBA_D56
FBA_D57
FBA_D58
FBA_D59
FBA_D60
FBA_D61
FBA_D62
FBA_D63

L8010

+1.05V_GFX

PBY160808T-300Y-N
C8071
C8075
C8091
C8082

D

+FB_PLLAVDD

22U/6.3VS_6
0.1U/10V_4
0.1U/10V_4
0.1U/10V_4

F16

FB_PLLAVDD

P22

FB_PLLAVDD

H22

FB_DLLAVDD

<27>

FB_PLLAVDD

FB_CLAMP1

R8381

*0_4

R8390
100K/F_4

GF119

D

GF117

Need Check footprint & PN!

FB_DLLAVDD = 15mA
FB_VREF_PROBE

^Dd
bga595-nvidia-n13p-gv2-s-a2

352-(&78
4XDQWD&RPSXWHU,QF

D23

COMMON

Size
Custom

Document Number

1

2

3

4

5

6

7

Rev
2A

N14M-GS (MEMORY/GND)

Date: Monday, May 06, 2013

Sheet

15
8

of

40

1

2

3

4

U8011G

GF119

GF117

7

8

NC

ϭϲ

V7

IFPAB_PLLVDD

NC

W7

IFPAB_PLLVDD

GF119

NC

GF117

NC
NC

IFPA_TXD0
IFPA_TXD0

Y3
Y4

J7

IFPEF_PLLVDD

NC

NC
NC

IFPA_TXD1
IFPA_TXD1

AA2
AA3

K7

IFPEF_PLLVDD

NC

NC
NC

IFPA_TXD2
IFPA_TXD2

AA1
AB1

K6

NC
NC

IFPA_TXD3
IFPA_TXD3

AA5
AA4

NC
NC

IFPB_TXC
IFPB_TXC

AB4
AB5

NC
NC

IFPB_TXD4
IFPB_TXD4

AB2
AB3

IFPEF_RSET

NC

IFPA_IOVDD

NC

Y6

IFPB_IOVDD

NC

DVI-SL/HDMI

NC
NC

I2CY_SDA
I2CY_SCL

I2CY_SDA
I2CY_SCL

NC
NC

TXC
TXC

TXC
TXC

NC
NC

TXD0
TXD0

TXD0
TXD0

NC
NC

TXD1
TXD1

TXD1
TXD1

NC
NC

TXD2
TXD2

TXD2
TXD2

NC

NC
NC

IFPB_TXD5
IFPB_TXD5

AD2
AD3

NC
NC

IFPB_TXD6
IFPB_TXD6

AD1
AE1

NC
NC

IFPB_TXD7
IFPB_TXD7

AD5
AD4

GF119

GPIO14

NC

bga595-nvidia-n13p-gv2-s-a2

DP
IFPE_AUX
IFPE_AUX

J3
J2

IFPE_L3
IFPE_L3

J1
K1

IFPE_L2
IFPE_L2

K3
K2

IFPE_L1
IFPE_L1

M3
M2

IFPE_L0
IFPE_L0

M1
N1

+3V_GFX

3/14 DACA

GPIO18

HPD_E

HPD_E

A

U8011K

GF119

W5

DACA_VDD

AE2

DACA_VREF

AF2

DACA_RSET

GF117
NC

GF117
NC
NC

GF119
I2CA_SCL
I2CA_SDA

NC
NC

DACA_HSYNC
DACA_VSYNC

AE3
AE4

NC

DACA_RED

AG3

NC

DACA_GREEN

AF4

NC

DACA_BLUE

H6

IFPE_IOVDD

NC

J6

IFPF_IOVDD

NC

AF3

B7 I2CA_SCL R8386
A7 I2CA_SDA R8383

2.2K_4
2.2K_4

TSEN_VREF
NC

C2

GF117
GF119
GF117

B

IFPAB

DVI-DL

IFPE

GF117

W6

GF119

GF117

AC4
AC3

IFPA_TXC
IFPA_TXC

NC
NC

GF119

IFPAB_RSET

A

6

7/14 IFPEF
GF119

GF117

AA6

5

U8011J

4/14 IFPAB

IFPF

B3

COMMON

DVI-SL/HDMI

DVI-DL

DP
IFPF_AUX
IFPF_AUX

H4
H3

TXC
TXC

IFPF_L3
IFPF_L3

J5
J4

NC
NC

I2CZ_SDA
I2CZ_SCL

NC
NC
NC
NC

TXD3
TXD3

TXD0
TXD0

IFPF_L2
IFPF_L2

K5
K4

NC
NC

TXD4
TXD4

TXD1
TXD1

IFPF_L1
IFPF_L1

L4
L3

NC
NC

TXD5
TXD5

TXD2
TXD2

IFPF_L0
IFPF_L0

M5
M4

bga595-nvidia-n13p-gv2-s-a2

COMMON

B

U8011H
5/14 IFPC

IFPC

NC

GF117

IFPC_RSET

NC

GF117

M7
N7

IFPC_PLLVDD
IFPC_PLLVDD

NC
NC

NC
NC

I2CW_SDA
I2CW_SCL

IFPC_AUX
IFPC_AUX

N5
N4

NC
NC

TXC
TXC

IFPC_L3
IFPC_L3

N3
N2

NC
NC

TXD0
TXD0

IFPC_L2
IFPC_L2

R3
R2

NC
NC

TXD1
TXD1

IFPC_L1
IFPC_L1

R1
T1

TXD2
TXD2

IFPC_L0
IFPC_L0

T3
T2

DVI/HDMI

NC
NC

C

IFPC_IOVDD

NC

F7

DP

GPIO15

NC

bga595-nvidia-n13p-gv2-s-a2

COMMON

PLLVDD = 38mA
+1.05V_GFX

L8012

PBY160808T-300Y-N
C8125 0.1U/10V_4
C8161 22U/6.3VS_6

NV_PLLVDD

U8011M

SP_PLLVDD = 17mA
+1.05V_GFX

C3

L8013

C8508

9/14 XTAL_PLL

HCB1608KF-181T15
C8123
0.1U/10V_4
C8124 0.1U/10V_4
C8172 4.7U/6.3V_6
C8159 22U/6.3VS_6

C

SP_PLLVDD

L6
M6

PLLVDD
SP_PLLVDD

N6

VID_PLLVDD

27M_XTAL_IN_R
27M_XTAL_OUT

bga595-nvidia-n13p-gv2-s-a2

COMMON

GF119
NC

VID_PLLVDD = 41mA

*18P/50V_4

Y8002
*27MHZ +-10PPM

1
2

P6

GPIO19

HPD_F

GF119

4
3

GF119

T6

C8509

GF117

*18P/50V_4

U8011I

R8054

6/14 IFPD

<26>
DVI/HDMI

T7

IFPD_PLLVDD

NC

R7

IFPD_PLLVDD

NC

IFPD

I2CX_SDA
I2CX_SCL

0_4

27M_XTAL_IN_R

C11

XTALSSIN

XTALOUTBUFF

DP

XTALIN

XTALOUT

bga595-nvidia-n13p-gv2-s-a2

IFPD_AUX
IFPD_AUX

P4
P3

NC

R8053

10K/F_4

GF119

27M_XTAL_OUT

TXC
TXC

IFPD_L3
IFPD_L3

R5
R4

NC
NC

TXD0
TXD0

IFPD_L2
IFPD_L2

T5
T4

DGPU_PGOK-1

NC
NC

TXD1
TXD1

IFPD_L1
IFPD_L1

U4
U3

NC
NC

TXD2
TXD2

IFPD_L0
IFPD_L0

V4
V3

+3V

+1.05V_GFX

R8070

4.7K_4

DGPU_POK4 2

NC

GPIO17

C8157
*1000P/50V_4

D4

+1.5V_GFX

R8404

4.7K_4

GF117

Q8035
METR3904-G

DGPU_POK2 2

C8536
*1000P/50V_4

bga595-nvidia-n13p-gv2-s-a2

R8403
*4.7K_4
R8071
4.7K_4

DGPU_PWROK

<9,27,36>
D

2
Q8034
METR3904-G

Q8033
DTC144EUA

R8405
100K/F_4

352-(&78
4XDQWD&RPSXWHU,QF

1

IFPD_IOVDD

B10

+3V_GFX
NC
NC

C8158
1000P/50V_4

1

R6

C10 BXTALOUT

COMMON

3

D

NC
NC

CLK_27M_XTAL_IN

R8367

3

NC

GF119

GF117

3

IFPD_RSET

10K/F_4 XTAL_SSIN A10

GF117

1

GF119

U6

Size
Custom

COMMON

Document Number

1

2

3

4

5

6

7

Rev
2A

N14M-GS (DISPLAY)

Date: Friday, April 26, 2013

Sheet

16
8

of

40

1

2

3

4

5

6

7

8

+3V_GFX

ϭϳ

+3V_GFX

U8011L

Default: HYNIX

10/14 MISC2

VMON_IN0
VMON_IN1

DEL VID pin for NVD request

A

B12 ROM_SI
A12 ROM_SO
C12 ROM_SCLK

ROM_SI
ROM_SO
ROM_SCLK

D1
D2
E4
E3
D3

STRAP0
STRAP1
STRAP2
STRAP3
STRAP4

C1

STRAP5_NC

GF119

40.2K/F_4 F6

R8072
*30.1K/F_4

R8074
*10K/F_4

R8073
*10K/F_4

4.99k
10k
15k
20k
24.9k
30.1k
34.8k
45.3k

R8076
*10K/F_4

STRAP0
STRAP1
STRAP2
STRAP3
STRAP4

R8362
15K/F_4

CS24992FB26
CS31002FB26
CS31502FB24
CS32002FB29
CS32492FB16
CS33012FB18
CS33482FB22
CS34532FB18
A

R8364
*20K/F_4

R8357
*15K/F_4

R8067
*24.9K/F_4

R8066
45.3K/F_4

R8064

R8065
4.99K/F_4

R8063
45.3K/F_4

15K/F_4

NC

MULTISTRAP_REF0_GND

D11
D10 NV_PWG R8055

PGOOD

GF119

EϭϯWͲ'sϮEs,tKKdsŽůƚĂŐĞсϬ͘ϴϳϱs
s/сϭϭϬϬϭϬ

R8075
45.3K/F_4

ROM_SI
ROM_SO
ROM_SCLK

GF117

BUFRST

R8068

TP8002

R8356
4.99K/F_4

2

STRAP0
STRAP1
STRAP2
STRAP3
STRAP4

D12 ROM_CS

ROM_CS

R8365
4.99K/F_4

R8363
*10K/F_4

1

E10
F10

TP8004
TP8007

10K/F_4

GF117

F4

MULTISTRAP_REF1_GND

NC

F5

MULTISTRAP_REF2_GND

NC

E9

CEC

+3V_GFX

bga595-nvidia-n13p-gv2-s-a2

+3V

+3V

+3V_GFX

+3V_GFX

COMMON

R8082
10K/F_4

R8389
10K/F_4

R8334
10K/F_4

GPU_GPIO0_R

FB_CLAMP_TGL_REQ#_EC

R8353
10K/F_4

3

<27>

3

U8011N

R8336
10K/F_4

FB_CLAMP_TGL_REQ#_EC

8/14 MISC1

DGPU_EDIDCLK
DGPU_EDIDDATA

GF119
I2CB_SCL
I2CB_SDA

C9
C8

N12E_SCL
N12E_SDA

R8373
R8374

2.2K_4
2.2K_4

2

+3V_GFX

E12

THERMDN

GF117

TP8001

THERM+ F12

THERMDP

NC
NC

AE5
AD6
AE6
AF6
AG4

R8376
R8378

2.2K_4
2.2K_4

GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GF117
NC
NC
NC

bga595-nvidia-n13p-gv2-s-a2

2

C6
B2
D6
C7
F9
A3
A4
B6
A6
F8
C5
E7
D7
B4

GPU_GPIO0 R8077

0_4

GPU_GPIO0_R

RAMCFG
[3:0]
0000
0000
0110
0111

FB_CLAMP_TGL_REQ#
VGA_OVT#
ALERT
PWR_LEVEL 2
PSI
D8009

1
RB500V-40

GPU_VID
<34>
DGPU_PROCHOT_EC#
PSI
<34>

<27,34>

GF119
GPIO16
GPIO20
GPIO21

D5 GPU_GPIO16
E6
C4

TP8005

2
1

3

DGPU_OVT#

<27>

Q8031
*2N7002K

R8060

10K/F_4

PSI

R8382

10K/F_4

VGA_OVT#

R8385

10K/F_4

ALERT

R8083

10K/F_4

JTAG_TRST#

R8366

10K/F_4

FB_CLAMP

2

<15,27>

2N7002K
Q8030

FB_CLAMP_TGL_REQ#

2N7002K
Q8027

DESCRIPTION

Vendor

DDR3 128Mx16x4, 64bit, 2Gb,900MHz
DDR3 128Mx16x4, 64bit, 2Gb,900MHz
DDR3 128Mx16x4, 64bit, 2Gb,900MHz

...
Micron
HYNIX
SAMSUNG

Vendor P/N

QCI P/N

MT41J128M16JT-107G:K
H5TQ2G63DFR-11C
K4W2G1646E-BC11

AKD5MGSTL06
AKD5MGWTW16
AKD5MGGT520

AKD5MGSTL08
AKD5MGWTW13
AKD5MGGT522

GPIO ASSIGNMENTS
GPIO
0
1
2
3
4
5
6
7
8
9
10
11
12
13

+3V_GFX
PWR_LEVEL

B

VRAM Configuration Table

COMMON

PEGX_RST#

VGA_OVT#

2N7002K
Q8025

+3V_GFX

1

JTAG_TCK
JTAG_TMS
JTAG_TDI
JTAG_TDO
JTAG_TRST

C

<14>

2

2N7002K
Q8032

3

A9
B9

<27>
<27>

3

I2CC_SCL
I2CC_SDA

GPUT_CLK
GPUT_DATA

1

THERM-

JTAG_TCK
JTAG_TMS
JTAG_TDI
JTAG_TDO
JTAG_TRST#

GPUT_CLK
GPUT_DATA

1

TP8003

TP8069
TP8068
TP8067
TP8066

D9
D8

1

B

I2CS_SCL
I2CS_SDA

I/O

PIN

IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
I/O
I/O
OUT
OUT
IN
OUT

FB_CLAMP_MON
MEM_VDD_CTL
LCD_BL_PWM
LCD_VCC
LCD_BLEN
Reserved
FB_CLAMP_TGL_REQ
3D VISION
OVERT
ALERT
MEM VREF_CTL
PWR_VID
PWR_LEVEL
PSI

USAGE

C

FB Clamp monitor
Memory VDD VID
Panel Backlight PWM
PANEL POWER ENABLE
PANEL BACKLIGHT ENABLE
-Active low FB Clamp toggle request
3D VISION LEFT/RIGHT signal
ACTIVE LOW THERMAL OVER TEMP
ACTIVE LOW THERMAL ALERT
MEMMORY VREF CONTROL
GPU CORE_VDD PWM Control signal
AC Power detect or power supply overdraw input
Phase Shedding

D

D

352-(&78
4XDQWD&RPSXWHU,QF
Size
Custom

Document Number

1

2

3

4

5

6

7

Rev
2A

N14M-GS (GPIO/STRAPS)

Date: Friday, April 26, 2013

Sheet

17
8

of

40

5

4

3

2

CHANNEL A: 256MB/512MB DDR3

QBC

VRAM8001

D

C

<15>
<15>
<15>
<15>
<15>
<15>
<15>
<15>
<15>
<15>
<15>
<15>
<15>
<15>
<15>
<15>

FBA_CMD9
FBA_CMD11
FBA_CMD8
FBA_CMD25
FBA_CMD10
FBA_CMD24
FBA_CMD22
FBA_CMD7
FBA_CMD21
FBA_CMD6
FBA_CMD29
FBA_CMD23
FBA_CMD28
FBA_CMD20
FBA_CMD4
FBA_CMD14

<15>
<15>
<15>

FBA_CMD12
FBA_CMD27
FBA_CMD26

<15>
<15>
<15>

VMA_CLK0
VMA_CLK0#
FBA_CMD3

<15>
<15>
<15>
<15>
<15>

FBA_CMD2
FBA_CMD0
FBA_CMD30
FBA_CMD15
FBA_CMD13

<15>

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7
M2
N8
M3

J7
K7
K9
K1
L2
J3
K3
L3
VMA_WDQS1
VMA_RDQS1

F3
G3

VMA_DM1
VMA_DM0

E7
D3

VMA_WDQS0
VMA_RDQS0

C7
B7

T2

FBA_CMD5
VMA_ZQ1

Should be 240
Ohms +-1%

M8
H1

L8

VREFCA
VREFDQ
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC
A13
A14
A15
BA0
BA1
BA2

CK
CK
CKE
ODT
CS
RAS
CAS
WE
DQSL
DQSL
DML
DMU
DQSU
DQSU

RESET
ZQ

R8022
243/F_4

J1
L1
J9
L9

B

NC#J1
NC#L1
NC#J9
NC#L9

VRAM8003

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

VDD#B2
VDD#D9
VDD#G7
VDD#K2
VDD#K8
VDD#N1
VDD#N9
VDD#R1
VDD#R9
VDDQ#A1
VDDQ#A8
VDDQ#C1
VDDQ#C9
VDDQ#D2
VDDQ#E9
VDDQ#F1
VDDQ#H2
VDDQ#H9
VSS#A9
VSS#B3
VSS#E1
VSS#G8
VSS#J2
VSS#J8
VSS#M1
VSS#M9
VSS#P1
VSS#P9
VSS#T1
VSS#T9
VSSQ#B1
VSSQ#B9
VSSQ#D1
VSSQ#D8
VSSQ#E2
VSSQ#E8
VSSQ#F9
VSSQ#G1
VSSQ#G9

E3
F7
F2
F8
H3
H8
G2
H7

VMA_DQ11
VMA_DQ9
VMA_DQ14
VMA_DQ8
VMA_DQ12
VMA_DQ10
VMA_DQ15
VMA_DQ13

D7
C3
C8
C2
A7
A2
B8
A3

VMA_DQ5
VMA_DQ1
VMA_DQ6
VMA_DQ2
VMA_DQ4
VMA_DQ3
VMA_DQ7
VMA_DQ0

VREFC_VMA1
VREFD_VMA1

M8
H1

FBA_CMD9
FBA_CMD11
FBA_CMD8
FBA_CMD25
FBA_CMD10
FBA_CMD24
FBA_CMD22
FBA_CMD7
FBA_CMD21
FBA_CMD6
FBA_CMD29
FBA_CMD23
FBA_CMD28
FBA_CMD20
FBA_CMD4
FBA_CMD14

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

FBA_CMD12
FBA_CMD27
FBA_CMD26

M2
N8
M3

VMA_CLK0
VMA_CLK0#
FBA_CMD3

J7
K7
K9

A1
A8
C1
C9
D2
E9
F1
H2
H9

FBA_CMD2
FBA_CMD0
FBA_CMD30
FBA_CMD15
FBA_CMD13

K1
L2
J3
K3
L3

VMA_WDQS3
VMA_RDQS3

F3
G3

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

VMA_DM3
VMA_DM2

E7
D3

VMA_WDQS2
VMA_RDQS2

C7
B7

FBA_CMD5

T2

B2
D9
G7
K2
K8
N1
N9
R1
R9

+1.5V_GFX

L8

VMA_ZQ2

B1
B9
D1
D8
E2
E8
F9
G1
G9

ϭϴ

TOP B/S

SAM 256Mx16, PN烉
烉AKD5PZDT501---AKD5PZDT500
SAM 128Mx16, PN烉
烉AKD5MGGT535---AKD5MGGT534

<15>
VMA_DQ[63..0]
<15>
VMA_DM[7..0]
<15>
VMA_WDQS[7..0]
<15>
VMA_RDQS[7..0]

VREFC_VMA1
VREFD_VMA1

1

HYU 256Mx16, PN烉
烉AKD5PGWTW08---AKD5PGWTW07
HYU 128Mx16, PN烉
烉AKD5MZDTW03---AKD5MZDTW02

Should be 240
Ohms +-1%

96-BALL
SDRAM DDR3
VRAM _DDR3_HYNIX_256MX16

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC
A13
A14
A15
BA0
BA1
BA2

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

VDD#B2
VDD#D9
VDD#G7
VDD#K2
VDD#K8
VDD#N1
VDD#N9
VDD#R1
VDD#R9

CK
CK
CKE
ODT
CS
RAS
CAS
WE

VDDQ#A1
VDDQ#A8
VDDQ#C1
VDDQ#C9
VDDQ#D2
VDDQ#E9
VDDQ#F1
VDDQ#H2
VDDQ#H9

DQSL
DQSL
DML
DMU
DQSU
DQSU

RESET
ZQ

R8028
243/F_4

J1
L1
J9
L9

VRAM8000

VREFCA
VREFDQ

NC#J1
NC#L1
NC#J9
NC#L9

VSS#A9
VSS#B3
VSS#E1
VSS#G8
VSS#J2
VSS#J8
VSS#M1
VSS#M9
VSS#P1
VSS#P9
VSS#T1
VSS#T9
VSSQ#B1
VSSQ#B9
VSSQ#D1
VSSQ#D8
VSSQ#E2
VSSQ#E8
VSSQ#F9
VSSQ#G1
VSSQ#G9

E3
F7
F2
F8
H3
H8
G2
H7

VMA_DQ25
VMA_DQ28
VMA_DQ27
VMA_DQ29
VMA_DQ26
VMA_DQ31
VMA_DQ24
VMA_DQ30

D7
C3
C8
C2
A7
A2
B8
A3

VMA_DQ16
VMA_DQ23
VMA_DQ18
VMA_DQ21
VMA_DQ19
VMA_DQ22
VMA_DQ17
VMA_DQ20

B2
D9
G7
K2
K8
N1
N9
R1
R9

VREFC_VMA3
VREFD_VMA3

M8
H1

FBA_CMD9
FBA_CMD11
FBA_CMD8
FBA_CMD25
FBA_CMD10
FBA_CMD24
FBA_CMD22
FBA_CMD7
FBA_CMD21
FBA_CMD6
FBA_CMD29
FBA_CMD23
FBA_CMD28
FBA_CMD20
FBA_CMD4
FBA_CMD14

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

FBA_CMD12
FBA_CMD27
FBA_CMD26

M2
N8
M3

J7
K7
K9

<15>
VMA_CLK1
<15>
VMA_CLK1#
FBA_CMD19
+1.5V_GFX <15>

A1
A8
C1
C9
D2
E9
F1
H2
H9

<15>
<15>

FBA_CMD18
FBA_CMD16

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

FBA_CMD30
FBA_CMD15
FBA_CMD13

K1
L2
J3
K3
L3

VMA_WDQS5
VMA_RDQS5

F3
G3

VMA_DM5
VMA_DM4

E7
D3

VMA_WDQS4
VMA_RDQS4

C7
B7

FBA_CMD5

T2
L8

VMA_ZQ3

B1
B9
D1
D8
E2
E8
F9
G1
G9

Should be 240
Ohms +-1%

96-BALL
SDRAM DDR3
VRAM _DDR3_HYNIX_256MX16

+1.5V_GFX

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC
A13
A14
A15

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

BA0
BA1
BA2

VDD#B2
VDD#D9
VDD#G7
VDD#K2
VDD#K8
VDD#N1
VDD#N9
VDD#R1
VDD#R9

CK
CK
CKE
ODT
CS
RAS
CAS
WE
DQSL
DQSL

VDDQ#A1
VDDQ#A8
VDDQ#C1
VDDQ#C9
VDDQ#D2
VDDQ#E9
VDDQ#F1
VDDQ#H2
VDDQ#H9

DML
DMU

VSS#A9
VSS#B3
VSS#E1
VSS#G8
VSS#J2
VSS#J8
VSS#M1
VSS#M9
VSS#P1
VSS#P9
VSS#T1
VSS#T9

DQSU
DQSU

RESET
ZQ

R8019
243/F_4

J1
L1
J9
L9

VRAM8002

VREFCA
VREFDQ

NC#J1
NC#L1
NC#J9
NC#L9

VSSQ#B1
VSSQ#B9
VSSQ#D1
VSSQ#D8
VSSQ#E2
VSSQ#E8
VSSQ#F9
VSSQ#G1
VSSQ#G9

E3
F7
F2
F8
H3
H8
G2
H7

VMA_DQ40
VMA_DQ45
VMA_DQ42
VMA_DQ46
VMA_DQ43
VMA_DQ47
VMA_DQ41
VMA_DQ44

D7
C3
C8
C2
A7
A2
B8
A3

VMA_DQ34
VMA_DQ36
VMA_DQ32
VMA_DQ38
VMA_DQ33
VMA_DQ37
VMA_DQ35
VMA_DQ39

VREFC_VMA3
VREFD_VMA3

M8
H1

FBA_CMD9
FBA_CMD11
FBA_CMD8
FBA_CMD25
FBA_CMD10
FBA_CMD24
FBA_CMD22
FBA_CMD7
FBA_CMD21
FBA_CMD6
FBA_CMD29
FBA_CMD23
FBA_CMD28
FBA_CMD20
FBA_CMD4
FBA_CMD14

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

FBA_CMD12
FBA_CMD27
FBA_CMD26

M2
N8
M3

VMA_CLK1
VMA_CLK1#
FBA_CMD19

J7
K7
K9

A1
A8
C1
C9
D2
E9
F1
H2
H9

FBA_CMD18
FBA_CMD16
FBA_CMD30
FBA_CMD15
FBA_CMD13

K1
L2
J3
K3
L3

VMA_WDQS7
VMA_RDQS7

F3
G3

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

VMA_DM7
VMA_DM6

E7
D3

VMA_WDQS6
VMA_RDQS6

C7
B7

FBA_CMD5

T2

B2
D9
G7
K2
K8
N1
N9
R1
R9

+1.5V_GFX

VMA_ZQ4

B1
B9
D1
D8
E2
E8
F9
G1
G9

Should be 240
Ohms +-1%

L8

VREFCA
VREFDQ

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC
A13
A14
A15

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

BA0
BA1
BA2

VDD#B2
VDD#D9
VDD#G7
VDD#K2
VDD#K8
VDD#N1
VDD#N9
VDD#R1
VDD#R9

CK
CK
CKE
ODT
CS
RAS
CAS
WE

VDDQ#A1
VDDQ#A8
VDDQ#C1
VDDQ#C9
VDDQ#D2
VDDQ#E9
VDDQ#F1
VDDQ#H2
VDDQ#H9

DQSL
DQSL
DML
DMU

VSS#A9
VSS#B3
VSS#E1
VSS#G8
VSS#J2
VSS#J8
VSS#M1
VSS#M9
VSS#P1
VSS#P9
VSS#T1
VSS#T9

DQSU
DQSU

RESET
ZQ

VSSQ#B1
VSSQ#B9
VSSQ#D1
VSSQ#D8
VSSQ#E2
VSSQ#E8
VSSQ#F9
VSSQ#G1
VSSQ#G9

R8326
243/F_4

J1
L1
J9
L9

96-BALL
SDRAM DDR3
VRAM _DDR3_HYNIX_256MX16

NC#J1
NC#L1
NC#J9
NC#L9

E3
F7
F2
F8
H3
H8
G2
H7

VMA_DQ62
VMA_DQ59
VMA_DQ60
VMA_DQ56
VMA_DQ61
VMA_DQ58
VMA_DQ63
VMA_DQ57

D7
C3
C8
C2
A7
A2
B8
A3

VMA_DQ54
VMA_DQ48
VMA_DQ55
VMA_DQ51
VMA_DQ53
VMA_DQ50
VMA_DQ52
VMA_DQ49

B2
D9
G7
K2
K8
N1
N9
R1
R9

D

+1.5V_GFX

A1
A8
C1
C9
D2
E9
F1
H2
H9

C

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
B1
B9
D1
D8
E2
E8
F9
G1
G9

B

96-BALL
SDRAM DDR3
VRAM _DDR3_HYNIX_256MX16

+1.5V_GFX

+1.5V_GFX

+1.5V_GFX

VMA_CLK0
R8329
1.33K/F_4
R8027
160/F_4

R8036
1.33K/F_4

VREFC_VMA1

R8003
1.33K/F_4

VMA_CLK1

VREFD_VMA1

R8041
1.33K/F_4

VREFC_VMA3

VREFD_VMA3

R8031
160/F_4

VMA_CLK0#
R8327
1.33K/F_4

C8475
0.1U/10V_4

R8035
1.33K/F_4

C8044
0.1U/10V_4

R8005
1.33K/F_4

C8028
0.1U/10V_4

R8038
1.33K/F_4

C8046
0.1U/10V_4

VMA_CLK1#

+1.5V_GFX
+1.5V_GFX
A

+1.5V_GFX
+1.5V_GFX
C8052
C8010
C8482
C8485

1U/6.3V_4
1U/6.3V_4
1U/6.3V_4
1U/6.3V_4

C8468
C8479
C8049
C8462
C8476
C8030

10U/6.3V_6
1U/6.3V_4
1U/6.3V_4
1U/6.3V_4
1U/6.3V_4
1U/6.3V_4

+1.5V_GFX

A

C8007

10U/6.3V_6

C8009

10U/6.3V_6

C8478
C8020
C8486

1U/6.3V_4
1U/6.3V_4
1U/6.3V_4

C8466

10U/6.3V_6

C8467

10U/6.3V_6

0.1U/10V_4
0.1U/10V_4
0.1U/10V_4

10U/6.3V_6

1U/6.3V_4
1U/6.3V_4
1U/6.3V_4
1U/6.3V_4

C8471
C8487
C8465

C8008

C8464
C8473
C8011
C8043

C8031
C8470
C8056

0.1U/10V_4
0.1U/10V_4
0.1U/10V_4

C8463
C8027

0.1U/10V_4
0.1U/10V_4

352-(&78
4XDQWD&RPSXWHU,QF
Size
Custom

Document Number

5

4

3

2

Rev
2A

DGPU Memory (DDR3)

Date: Friday, April 26, 2013

Sheet
1

18

of

40

5

4

3

2

1

ϭϵ

ůŽƐĞƚŽ>s^KEE
<2>

INT_eDP_TXP0

<2>

INT_eDP_TXN0

R252

D

INT_eDP_AUXN

<2>

INT_eDP_AUXP
R254

C20

0.1U/10V_4

LANE0P

INT_eDP_TXN0

C26

0.1U/10V_4

LANE0N

*1M/F_4

<2>

+3V

INT_eDP_TXP0

R2

*0_4

eDP_TXP0

R4

*0_4

eDP_TXN0

dŽ>s^ŽŶǀĞƌƚĞƌ

&ƌŽŵ>s^ŽŶǀĞƌƚĞƌ

dŽĞW

INT_eDP_AUXN

C28

0.1U/10V_4 eDP_AUXN_2132

INT_eDP_AUXP

C31

0.1U/10V_4 eDP_AUXP_2132

&ƌŽŵWh

eDP_AUXN

R9

*0_4

eDP_AUXP

0_4

R249

0_4

eDP_TXP0

C10

*0.1U/10V_4

eDP_TXN0

C9

*0.1U/10V_4

PCH_LA_DATAP0

<20>

PCH_LA_DATAN0

<20>

D

&ƌŽŵ>s^ŽŶǀĞƌƚĞƌ
*0_4

R248

PCH_LA_DATAN0_R

dŽ>s^ŽŶǀĞƌƚĞƌ

*1M/F_4
R6

PCH_LA_DATAP0_R

PCH_EDIDDATA_R

R251

0_4

PCH_EDIDCLK_R

R253

0_4

eDP_AUXN

C8

*0.1U/10V_4

eDP_AUXP

C7

*0.1U/10V_4

dŽĞW
&ƌŽŵWh

&ŽƌWKŶůLJ͗ƐƚƵĨĨZĞƐŝƐƚŽƌ
&Žƌ>s^ŽŶůLJƐƚƵĨĨĂƉ

PCH_EDIDDATA

<20>

PCH_EDIDCLK

<20>
<6>
<6>
<6,19>

&ŽƌĞW͕ĐůŽƐĞƚŽhϳ
PCH_LVDS_BLON
PCH_DISP_ON
PCH_DPST_PWM

PCH_LVDS_BLON
PCH_DISP_ON
PCH_DPST_PWM

R241
R247
R245

2132_LVDS_BLON
2132_DISP_ON
2132_DPST_PWM

*0_4
*0_4
*0_4

2132_LVDS_BLON
<19,20>
2132_DISP_ON
<19,20>
2132_DPST_PWM
<19,20>

PCH_EDIDDATA_R

ůŽƐĞWŝŶϯ

+1.2V_2132

PCH_EDIDCLK_R
C24

L22

SCA_SDA

+3V

SCA_SCL
<6,20>

ULT_EDP_HPD

ULT_EDP_HPD

+3.3V_2132_A

TI160808U600

0.1U/10V_4

C377
10U/6.3V_6

DPRX_HPD

C33
0.1U/10V_4

C375
0.1U/10V_4

C

PCH_LA_DATAP0_R

25
TXO0+

27

26

VCCK

TXO0-

28

29
SPI_SI/SCLK/MIICSCL

SPI_CK/SDIO/MIICSDA

31

30
SPI_SO/SCSB/MIICSDA

33

32
HPD

BL_EN

PWMIN

PWMOUT

Panel_VCC

16

RTD2132R-CG

PVCC

15

DP_REXT

TXOC+

14

DP_V12

SWR_VDD

8

12K/F_4

SWR_LX

R17
C376
0.1U/10V_4

13

+1.2V_2132

TXO2TXO2+
TXOC-

12

7

TXO1TXO1+

RTD2132R

LANE0N

+3.3V_2132

TI160808U600
C374
10U/6.3V_6

LANE0P

SWR_VCCK

6

DP_GND

11

5

LANE0N

DP_V33

SPI_CEB/IRQB/MIICSCL

LANE0P

AUX-CH_P

CIICSDA1

4

AUX-CH_N

10

3

+3.3V_2132_A

GND

2

CIICSCL1

1

eDP_AUXP_2132

9

eDP_AUXN_2132

24
23
22
21
20

PCH_LA_DATAN1

<20>

PCH_LA_DATAP1

<20>

PCH_LA_DATAN2

<20>

PCH_LA_DATAP2

<20>

PCH_LA_CLK#

19

PCH_LA_CLK

C367
0.1U/10V_4

SCA_SCL pull high => EEPROM mode
SCA_SDA pull low = > EEPROM Free mode

<20>
<20>

18

C373
0.1U/10V_4

+3.3V_2132

17

C372
0.1U/10V_4

ĚĚƌĞƐƐсϬdžϴ

/Ed

RTD2132R

C

L21
+3V

U7

Note:
entire trace of +3.3V_2132_A should
be wider than 80-mil

PCH_LA_DATAN0_R

R256 1K/F_4

2132_LVDS_BLON

H=1mm(max)

+3V

<19,20>

B

B

+3V

R13

R1
R7

+1.2V_2132

Note:

PCH_DPST_PWM
100K/F_4

PCH_DPST_PWM
2132_DISP_ON
2132_DPST_PWM

C378
R8
10U/6.3V_6

*0_8

<19,20>
<19,20>

SCA_SDA
SCA_SCL

R25
R20

*0_4
*0_4

PCH_EDIDDATA
PCH_EDIDCLK

R28
R23

*0_4
*0_4

SCA_SDA_R
SCA_SCL_R

Note:
+3.3V_2132

ůŽƐĞWŝŶϭϮфϮϬϬŵŝů
C369
0.1U/10V_4

<6,19>

*4.7K_4 CSDA1
L20
4.7UH/850mA/TLPC3010C-4R7M

+1.2V_2132

ϲϬϭϰͬϲϬϭϱ
ĐůŽƐĞфϮϬϬŵŝů

*4.7K_4 CSCL1

C23
22U/6.3V_8

U8

VCC
SDA
SCL
GND

WP
A2
A1
A0

C379
*0.1U/10V_4

7
3
2
1

Close to Pin8

*SGT-M24C64-WMN6TP

entire trace of Panel VCC should
be wider than 80-mil

C32
0.1U/10V_4

8
5
6
4

Note:
LDO mode change to 0ohm and 10u

Pin11/Pin12 +1.2V_2132 entire trace of
should be wider than 80-mil

ϲϬϭϲͬϲϬϭϳ
ĐůŽƐĞфϮϬϬŵŝů

ZdϮϭϯϮ^схZϮϱ͕ZϮϬ
ZdϮϭϯϮZсхZϮϴ͕ZϮϯ

entire trace of +TRAVIS3.3V should
be wider than 80-mil

ůŽƐĞWŝŶϭϯ
CSCL1

*0_4

R15

MODE_CFG0(PIN30)
SMB_RUN_CLK

<8,11,12,13,24>
+3V

*0_4/S
A

R16

MBCLK2

R26

<8,13,27>

SI modify to short pad
CSDA1

*0_4

R12

*0_4/S

R11

R24

4.7K_4

SCA_SCL

*4.7K_4

SCA_SDA

R21
SMB_RUN_DAT

R29

0
MODE_CFG1(PIN31)

<8,11,12,13,24>

1

0

X

EP MODE

1

ROM ONLY MODE

EEPROM MODE

A

*4.7K_4 4.7K_4
MBDATA2

<8,13,27>

352-(&78
4XDQWD&RPSXWHU,QF

Reserve

Change Default setting to EC

EE PROM
EC OPTION
5

4

Size
Custom

R15,R12
R16,R11

Document Number

3

2

Rev
1A

LVDS converter RTD2132R

Date: Friday, April 26, 2013

Sheet
1

19

of

40

5

4

ϴϬŵŝůĞƚƌĂĐĞ
R250
C365
4.7U/6.3V_6

C22

5

*1U/6.3V_4

4
<19>

3

2132_DISP_ON

CN1
<19>

+LCDVCC

1K/F_4

2132_DPST_PWM

PCH_DPST_PWM_R

R226
R225
100K/F_4

IN

OUT

IN

GND

ON/OFF

1

L19
*TI160808U600

2

^Dd

C364

*10U/6.3V_6

C362

*0.01U/16V_4

C359

0.1U/10V_4

+3VLCD_CON

C349
22P/50V_4

+3V
C368

ͺD/
<21>
<21>
R227

100K/F_4

C350

<19>

Can't change to short
R235
0_4

EMU_LID

FCM1608KF-301T02 DIGITAL_D1_R
FCM1608KF-301T02 DIGITAL_CLK_R

L13
L11

DIGITAL_D1
DIGITAL_CLK

C13
C4
C6
C3

22P/50V_4

D3

<19>
<19>

PCH_LA_DATAN0
PCH_LA_DATAP0

<19>
<19>

PCH_LA_DATAN1
PCH_LA_DATAP1

<19>
*0_4 EDP_HPD_R<19>

PCH_LA_DATAN2
PCH_LA_DATAP2

&ŽƌWKŶůLJ͗^ƚƵĨĨZĚ
&Žƌ>s^KŶůLJ͗^ƚƵĨĨZĐ
ZĐ 0_4
R230

*IC(5P) G5243AT11U

<6,19>

R233

ULT_EDP_HPD

ZĚ

DIGITAL_D1
DIGITAL_CLK
DIGITAL_D1_R
DIGITAL_CLK_R

*33P/50V_4
*33P/50V_4
100P/50V_4
100P/50V_4

<19>
<19>

30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

PCH_DPST_PWM_R
BLON_CON
PCH_EDIDCLK
PCH_EDIDDATA

1000P/50V_4

R3
100K/F_4

<27>

PCH_LA_DATAN0
PCH_LA_DATAP0
PCH_LA_DATAN1
PCH_LA_DATAP1
PCH_LA_DATAN2
PCH_LA_DATAP2

PCH_LA_CLK#
PCH_LA_CLK
USBP2-_C
USBP2+_C

BLON_CON

RB500V-40

DIGITAL_D1_R
DIGITAL_CLK_R
R237

2132_LVDS_BLON

1K/F_4

+3V

+3V
<19>

R242
100K/F_4

<19>

PCH_EDIDDATA

R229 4.7K/_4

PCH_EDIDCLK

R228 4.7K/_4
R255 *100K_4

Ra
Rb

C352

0.01U/16V_4

C357

*4.7U/6.3V_6

C351

1000P/50V_4

+VIN_BLIGHT

R238

*1K_4

2132_DPST_PWM

R246

*1K_4

L9
<8>
<8>

USBP2USBP2+

L12

2
3

1
4

+VIN

USBP2-_C
USBP2+_C

<6>

D/^ŽůƵƚŝŽŶ

+3V

Q32

4

3

<6>

HDMI_SDA_R 1

SDVO_DATA
+3V

R82

121/F_4

C_TX2_HDMI-

C_TX1_HDMI+

R93

121/F_4

C_TX1_HDMI-

C_TX0_HDMI+

R96

121/F_4

C_TX0_HDMI-

C_TXC_HDMI+

R352

121/F_4

C_TXC_HDMI-

HDMI_SCLK

2
B

R390

2.2K_4

+VIN_BLIGHT

C2
C360
0.1U/50V_6

CN16

C_TX2_HDMI+

5
HDMI_SCL_R

SDVO_CLK

6

<2>

IN_D2

<2>
<2>

IN_D2#
IN_D1

<2>
<2>

IN_D1#
IN_D0

<2>
<2>

HDMI_SDATA
C_IN_CLK
C_IN_CLK#

2N7002DW

ůŽƐĞƚŽ,D/ĐŽŶŶĞĐƚŽƌ

R351
R354

<2>

C_TXC_HDMI+
C_TXC_HDMI-

*0_4/S
*0_4/S

+5V_HDMIC

IN_D0#
IN_CLK
IN_CLK#
D13 2
2
D12

IN_D2

C167

0.1U/10V_4

C_TX2_HDMI+

IN_D2#
IN_D1

C169
C176

0.1U/10V_4
0.1U/10V_4

C_TX2_HDMIC_TX1_HDMI+

IN_D1#
IN_D0

C177
C180

0.1U/10V_4
0.1U/10V_4

C_TX1_HDMIC_TX0_HDMI+

IN_D0#
IN_CLK

C181
C465

0.1U/10V_4
0.1U/10V_4

C_IN_CLK

C_TX0_HDMIC_TXC_HDMI+

IN_CLK#
C470
RB500V-40
1
5V_HSMBCK
1
5V_HSMBDT
RB500V-40

0.1U/10V_4

C_IN_CLK#

C_TXC_HDMI-

R395
R394

SI del choke and chage 0ohm

2.2K_4
2.2K_4

C506
C509

HDMI_SCLK
HDMI_SDATA

*10P/50V_4
*10P/50V_4

HDMI_HPD

L28

HDMI_DET_C

*0_6/S

SI modify

Q31
2N7002K

1

2

R378 1

470/F_4
470/F_4

C_TX2_HDMI+
C_TX2_HDMI-

R92
R94

470/F_4
470/F_4

C_TX1_HDMI+
C_TX1_HDMI-

R95
R97

470/F_4
470/F_4

C_TX0_HDMI+
C_TX0_HDMI-

R349
R357

470/F_4
470/F_4

HDMI_HPD_CON

HDMI_HPD_CON

21

C491

1

SI modify
3

40 mils

HDMI_HPD

+5V
R374
20K/F_4

2 100K/F_4
Change to 470 for EMI

C505

B

220P/50V_4

Q30
2N7002

C_IN_CLK
C_IN_CLK#

0.1U/10V_4

A

ůŽƐĞƚŽYϯϭ

+5V_HDMIC

F1
2

FUSE1A6V_POLY
1
+5V_HDMIC

C507

0.1U/10V_4

Document Number

2

Rev
1A

>ͬ,D/ͬĂŵĞƌĂͬͲD/

Date: Monday, May 06, 2013
3

A

+VIN

352-(&78
4XDQWD&RPSXWHU,QF
Size
Custom

for EMI request
4

+5V_HDMIC

VC3
SSM14 spec is 40V 1A
*TVM0G5R5M220R
<6,7,8,9,10,11,12,13,14,15,16,17,19,21,22,23,24,25,26,27,32,33,34>
+3V
<4,7,21,24,25,26,27,28,29>
+3VPCU
<6,21,23,24,25,26,33>
+5V
<24,28,29,30,31,32,33,34,35,36>
+VIN
<23,28,33,35>
+12VALW
<13,21,24,25,29,31,32,33,34,36>
+5VS5

C485
*0.01U/16V_4

5

0.01U/25V_4

VC2
*TVM0G5R5M220R

R363
1M_4

<6>

0.1U/50V_6

C1

HDMI CONN

2

3

+3V

R81
R83

*4.7U/25V_8

C348

20

SHELL1
D2+
D2 Shield
D2D1+
D1 Shield
D1D0+
D0 Shield
D0CK+
CK Shield
CKCE Remote
NC
DDC CLK
DDC DATA
GND
+5V
HP DET
SHELL2

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19

+5V_HDMIC
+3V

DGPU_CL_HDMIP

C

*0_8/S

SI modify

,D/^DƵƐ/ƐŽůĂƚŝŽŶ
2.2K_4

33

SI del 0ohm

For LVDS stuff Ra=4.7k,Rb=4.7k,Rc un-stuff
For eDP reserve Ra=100k,Rc=100k,Rb un-stuff

MCM2012B900GBE

R393

34

lvds-lvd-a30sfyg-30p-r
FOX DFWF30MR007 EOD
+VIN_BLIGHT

h^DZ

Only for eDP reserve

+3V

35

DFWF30MR004

+3V

2132_LVDS_BLON

D

LVDS CONN

Rc

C

HDMI Conn.

ϮϬ

*0_8/S

SI modify to short pad

U6

D

1

32

+3V

2

31

LVDS Conn.

3

+3VLCD_CON

Sheet
1

20of

40

A

B

C

D

+5V_AVDD

C592
10U/6.3VS_6

C593
0.1U/10V_4

+1.5V_AVDD

DIGITAL_D1

R547

<20>

DIGITAL_CLK

R548

10P/50V_4
*0_4/S
100/F_4

1

SI modify to short pad
DMIC0

2

DMIC_CLK_R

3

DVDD

GPIO1 / DMIC-CLK

10P/50V_4

ACZ_SDOUT_AUDIO
R549

0_4

ACZ_SDOUT_AUDIO

5

HD_BCLK

6

10U/6.3VS_6

Close to PIN7
R550

C939

RESETB
PCBEEP
CPVEE

36

2.2U/6.3V_6

0.1U/10V_4

C589

10U/6.3VS_6

C582

0.1U/10V_4

C587

1

R545

Vset=1.242V

HPOUT_L

AGND SHIELD

33

HPOUT_R

AGND SHIELD

10U/6.3VS_6

C583

^ƉĞĂŬĞƌϰŽŚŵ͗ϰϬŵŝůƐ
L_SPK+
L_SPKR_SPKR_SPK+

MUTE_LED_CNTL

18
17

MIC_R1
MIC_L1

29

VREFOUT_C

C629
C608

R5108
*2.2U/6.3V_6
2.2U/6.3V_6

*0_4/S

MUTE_LED_CNTL_M

SPDIF-OUT/GPIO2

JDREF

SenseB

SenseA

C604
0.1U/10V_4
AMP_BEEP_L

AMP_BEEP

20K/F_4

AGND

2
1

VOLMUTE#
D2

2
RB500V-40

C337
*1U/6.3V_4
AGND

2.2K_4

1

AMP_BEEP_R2

R552
10K_4

39.2K/F_4

SENSE_A

2

R546

22K/F_4

C585

4.7U/6.3V_6

ACZ_SPKR

AGND

AGND
EC17

EXT_MIC_L
C342
C339
C338

AGND

AGND

R222
1K/F_4

SI modify
SENSE_A

*1000P/50V_4
*1000P/50V_4
*1000P/50V_4

HPOUT_L
HPOUT_R

C590
C586

*1000P/50V_4
10U/6.3V_8

EXT_MIC_L

AGND
R5107

*0_4/S
<25,27>

SENSE_R

USBPW_ON#
+5VS5
+3VPCU
+3V

R223
10K_4

<24>

SI del 0ohm
EC38

*33P/50V_4

ACZ_SDOUT_AUDIO EC19

*10P/50V_4

ACZ_SYNC_AUDIO EC20

*10P/50V_4

BIT_CLK_AUDIO

*33P/50V_4

EXT_MIC_L

EC39

<8>
<8>

USBP1USBP1+

MCM2012B900GBE
4
3
1
2

DEEP_PWRLED#
<7>
SATA_LED#
<7>
ACC_LED#
USBP1-_C
USBP1+_C

L8

<9>

2N7002
Q6

USB 2.0 AND AUDIO COMBO JACK

ACZ_SDIN0
R211

VREFOUT_C

100K/F_4

Close to codec

PD#
<27>

USBPW_ON#

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18 CN9
19 Audio CONN
20

1000P/50V_4

EC18

1000P/50V_4

EC37

1000P/50V_4

EC40

1000P/50V_4

AGND

Close to CODEC
R206

*0_8/S

AGND

352-(&78
4XDQWD&RPSXWHU,QF
Size
Custom

Document Number

C

D

Rev
1A

Azalia ALC 3227

Date: Friday, April 26, 2013
B

1000P/50V_4

EC36

ƉůĂĐĞƚŽŶĞĂƌhϮϰŽƌƵŶĚĞƌhϮϰ

C591
0.1U/25V_4

FOR EMI
A

C353

C606
0.1U/10V_4

check value
R551

Check layout
mount location

AGND

1

C354

EXT_MIC_L

R556 1K/F_4

R221
*2.2K_4

ACZ_RST#_AUDIO

C355

1000P/50V_4
1000P/50V_4
1000P/50V_4
1000P/50V_4

PD#

Q7
*MMBT3904-7-F
3

C356

ALC3227 x QFN48

R554

Close to Pin 46

+3V_DVDD

INT SPEAKER CONN
L_SPK+_R
1
L_SPK-_R
2
R_SPK-_R
3
R_SPK+_R
4
CN2

TI160808U600
TI160808U600
TI160808U600
TI160808U600

<25>

C607
0.01U/25V_4

Close to Pin 41

+1.5V

L17
L16
L15
L14

R553
10K_4

COMBO_GPI

Q7
BA039040000
BA039040020

10K_4 +5V

Close to Speaker

AGND

ĨŽƌŝŶƚĞů,^th>d

C578
1U/6.3V_4

AGND SHIELD

SENSE_A_1 R555
+5V_DVDD

C577
0.047U/10V_4

1

HCB1608KF-181T15_6

C579
0.1U/10V_4

3

AGND

+5V_DVDD

L35

+5V

15

+5V_DVDD

EN

16

MONO-OUT

13

49

NC

R_SPK+

MIC2-VREFO

48

SPK-R+

PDB

SPK-RPVDD2

72,QWHUQDO6SHDNHUV

SPK-L-

45

47

44

PVDD1

L_SPKR_SPK-

46

43

41

Close to Pin 34,35,36

L_SPK+

GND

*TPS793475DBVR
HPA01091DBVR

+5V_AVDD

SPK-L+

C331

1

SI modify

MIC2-R (PORTF)
MIC2-L (PORTF)

4.7U/6.3V_6

Vin

BYP

Close to PIN28

32

31
30

CPVDD

42

Vout

0.1U/10V_4

20
19

MIC1-VREFO-L
MIC1-VREFO-R

+3V_DVDD

+3V_DVDD

C603

22
21

LINE1-L (PORTC)
LINE1-R (PORTC)

CBP

CAP+

1

LINE2-L
LINE2-R

CBN

37

2
C580
*1U/6.3V_4

AGND

24
23

MIC1-R (PORTB)
MIC1-L (PORTB)

35
CAP-

10U/6.3VS_6
10U/6.3VS_6

C346
*0.1U/10V_4

AGND

28

VREF

HPOUT-L (PORT I)

SYNC

34

C334
2.2U/6.3V_6

C598
C595

C345
*2.2U/6.3V_6

DVDD-IO

12

2.2U/6.3V_6

4

AGND

27
39

LDO1-CAP
LDO2-CAP

14

C597

*0.1U/10V_4
AMP_BEEP

U23

5

HPOUT-R (PORT I)

11

ACZ_RST#_AUDIO

+5V_AVDD

Close to PIN40

25
38

AVSS1
AVSS2

C600

SDATA-IN

10

ACZ_SYNC_AUDIO

AGND

LDO3-CAP

Digital

<7>

BCLK

9

+3V_DVDD-IO

ACZ_SYNC_AUDIO

SDATA-OUT

8

HD_SDIN0

33_4

DVSS

7

C599

26
40

AVDD1
AVDD2

GPIO0/ DMIC-DATA

4

<7>

+1.5V

3

<20>

ACZ_SDIN0

+3V

HCB1608KF-181T15_6
C588
10U/6.3VS_6

Analog

C594

C596

<7>

*HCB1608KF-181T15_6

L37

+5V

72'LJLWDO0,&

BIT_CLK_AUDIO

C581 need check!

AGND
L5015

C601
C602
0.1U/10V_4 10U/6.3VS_6

U24

<7>

21

+5V
+3V
+1.5V

Close to PIN26

L5014
*HCB1608KF-181T15_6

+3V

2

+3V_DVDD-IO

L36
HCB1608KF-181T15_6

+1.5V

C584
1U/6.3V_4

<7>

HCB1608KF-181T15_6
C605
0.1U/10V_4

C609
10U/6.3VS_6

E

+5V
<6,20,23,24,25,26,33>
<6,7,8,9,10,11,12,13,14,15,16,17,19,20,22,23,24,25,26,27,32,33,34>
<10,24,26,30>
*AZ2015-01H
C581

>40mils trace

Close to PIN1
+3V_DVDD
L38
HCB1608KF-181T15_6

+3V

L40

Sheet
E

21

of

40

5

4

3

2

1



For EMI 0 ~ 22 ohm
+1.05V_LAN
LAN_XTAL1

R42
*10/F_4

+3V
XTAL1
R39

2.49K/F_4

if ISOLATEB pin
pull-low,the LAN
chip will not drive
it's PCI-E outputs
( excluding
PCIE_WAKE# pin )

TP113

LANRSET
LAN_AMBLED#

XTAL2 R43

<26>

+3V_LAN

R19
1K_4

TP112

3
4

XTAL2

ISOLATEB

TP114

2

1
2

LAN_XTAL25_IN

RSET
VDD10
XTAL2
XTAL1
LED0

Y1
D

*0_4/S

SI modify to short pad
LAN_WLED#

D

R18

*25MHZ +-10PPM

33

Power trace Layout ⮔ ⹎ > 60mil
4.7UH,+-20%,650MA_1210
L23

>60mil
+1.05V_LAN_REGOUT

R259

close to each VDD10 pin-- 3, 8, 22, 30

>60mil

+1.05V_LAN

1
2
3
4
5
6
7
8

MDI0+
MDI0VDD10
MDI1+
MDI1-

Place Cc,Cd,Ce,Cf
+1.05V_LAN

*0_8
+1.05V_LAN

Đ

C46
0.1U/10V_4

4.7U/6.3V_6

Ě

C54
0.1U/10V_4

Ğ

C390
0.1U/10V_4

C42
0.1U/10V_4

Close to Choke L23
SWR mode need stuff C622 & Cz

Ĩ
C37
0.1U/10V_4

VDD10

Ő
C36
1U/6.3V_4

C621
0.1U/10V_4
RTL8176EH-CG

Place Cg & C621 close to each VDD10 pin22

C

REGOUT(NC)
VDDREG(VDD33)
DVDD10(NC)
AKEB
RTL8176EH LANW
ISOLATEB
PERSTB
HSON
HSOP
MDIP3(NC)
MDIN3(NC)
AVDD33(NC)
CLKREQB
HSIP
HSIN
REFCLK_P
REFCLK_N

nj

C622

MDIP0
MDIN0
AVDD10(NC)
MDIP1
MDIN1
MDIP2(NC)
MDIN2(NC)
AVDD10

24
23
22
21
20
19
18
17

+1.05V_LAN_REGOUT
DVDDL
VDD10
PCIE_WAKE#
ISOLATEB
3
/PCIE_RXN4_LAN_L
7PCIE_RXP4_LAN_L
5
6
7


+1.05V_LAN_REGOUT
+3V_LAN
+1.05V_LAN
PCIE_WAKE#
C41
C38

C

R22

MDI1+_1

1

MDI1-_1

3

75/F_4

R30

LAN_MCTG1

2

MDI0+_1

6

MDI0-_1

8

75/F_4

LAN_MCTG0

7

TD+

TX+

TD-

CMT

CT

TX-

RD+

RX-

RD-

CT

CT

RX+

16

MDI1+

15

TRA_V_DAC

14

MDI1-

9

MDI0-

+3V_LAN
<8>

*0_4/S

CLK_PCIE_LANN
CLK_PCIE_LANP
PCIE_TXN4_LAN
PCIE_TXP4_LAN

CLK_PCIE_LANN
CLK_PCIE_LANP
PCIE_TXN4_LAN
PCIE_TXP4_LAN

10

TRA_V_DAC

11

MDI0+

LAN conn
TWD Type

C52
0.01U/25V_4

Kd͗d^dϭϮϴϰZ>&Ϭ>ϱ>EϬϬ

RJ45
(White)

CN13

LAN_WLED
LAN_WLED#

+3V_LAN

MDI1-_1
MDI1+_1
MDI0-_1
MDI0+_1

+3VLANVCC
C45

0.1U/10V_4

0.1U/10V_4

Ă

9
10
8
7
6
5
4
3
2
1

Stuff Ca and Cb only, close to each VDD33 pin-- 11, 32

C34

<8>
<8>
<8>
<8>

SI modify to short pad

NS681684

C366
10P/3KV_1808

PCIE_CLKREQ_LAN# R10

PCIE_CLKREQ_LAN#

LAN_CLKRQ

*RTL8166EH Cg & C621 close pin30
U9

B

<6,23,26,27>

PLTRST#
<6,11,14,23,24,26,27>
PCIE_RXN4_LAN
<8>
PCIE_RXP4_LAN
<8>

0.1U/10V_4
0.1U/10V_4

9
10
11
12
13
14
15
16

Trace<30 mil
Width > 60 mil

GND

WůĞĂƐĞĂĚĚϵ'Es/Ɛ
ĐŽŶŶĞĐƚŝŽŶǁŝƚŚƚŚĞƌŵĂůW

Switch Mode:Stuff L23 For RTL 8176
LDO
Mode:Stuff R259 For RTL8166

1

U1

SI modify

AVDD33
RSET
AVDD10
CKXTAL2
CKXTAL1
LED0
LED1/GPO
LED2(LED1)

C59
*10P/50V_4

32
31
30
29
28
27
26
25

15K/F_4
C56
*10P/50V_4

LED_AMB_P A1
LED_AMB_N A2

*0_6/S

GND1
GND

ď

LAN_AMBLED 11
LAN_AMBLED# 12

(Amber)
C40
68P/50V_4

B

R234

RX1RX1+
RX0TX1TX1+
RX0+
TX0TX0+

14
13
R266

LED_GRE_P B1
LED_GRE_N B2

*0_6/S
RJ45_CONN

Place Cc and Cd close to each VDD33 pin-- 23
C380
4.7U/6.3V_6

C53

C398

+3VLANVCC

0.1U/10V_4

R277

1000P/50V_4

330_4
LAN_AMBLED

Đ

A

Ě

A

Remove For Not Using SWR mode

LAN_WLED

+3VLANVCC
R279

C399
<6,7,8,9,10,11,12,13,14,15,16,17,19,20,21,23,24,25,26,27,32,33,34>
<26,33>

352-(&78
4XDQWD&RPSXWHU,QF

330_4
1000P/50V_4

+3V
+3VLANVCC

Size
Custom

Document Number

Date: Friday, April 26, 2013

5

4

3

2

Rev
1A

LAN RTL8176EH/RJ45
Sheet

1

22

of

40

5

4

3

2

Reserve for EMI

PCIE_CLKREQ_CR#

PCIE_CLKREQ_CR#

*0_4/S PCIE_CLKREQ_CR#_R

R301

R303

SI modify to short pad
D

*0_4/S

<8>
<8>

Zdiff = 100 ohm
<8>
<8>
<8>
<8>

CLK_PCIE_CRP
CLK_PCIE_CRN
PCIE_RXP2_CARD
PCIE_RXN2_CARD

C443
C446

1
2
3
4
5
6
7
8

PLTRST#
PCIE_CLKREQ_CR#_R
PCIE_TXP2_CARD
PCIE_TXN2_CARD
CLK_PCIE_CRP
CLK_PCIE_CRN
PCIE_RXP2_CARD_C
PCIE_RXN2_CARD_C

PLTRST#

PCIE_TXP2_CARD
PCIE_TXN2_CARD
0.1U/10V_4
0.1U/10V_4

WůĞĂƐĞĂĚĚϵ'Es/Ɛ
ĐŽŶŶĞĐƚŝŽŶǁŝƚŚƚŚĞƌŵĂůW

PERST#
CLKREQ#
HSIP
HSIN
REFCLKP
REFCLKN
HSOP
HSON

33

*5.6P/16V_4
*5.6P/16V_4
*5.6P/16V_4
*5.6P/16V_4

SD_D1
SD_D0
SD_CLK
SD_CMD
SD_D3
SD_D2

MS_D1
MS_D0
MS_D2
MS_D3
MS_CLK

SP7

SD_WP

MS_BS

23

SI modify to short pad

C428

*0_6/S

+3V

Share Pin

0.1U/10V_4

C424
4.7U/6.3V_6

WAKE#
MS_INS#
SD_CD#
SP7
GPIO
3V3aux
NC
NC

U11

<6,11,14,22,24,26,27>

EC31
EC32
EC29
EC30

SP1
SP2
SP3
SP4
SP5
SP6

D

SD / MMC

32
31
30
29
28
27
26
25

R300

PCIE_WAKE#

+3V

R299

RTS5237
RREF
AV12
3V3_IN
CARD_3V3
NC
DV12S
SP1
SP2

<6,22,26,27>

10K_4

SD_CD#
SD_WP
RTS5237_GPIO
RTS5237_3Vaux

<8>

SD_D0
SD_D1
SD_D2
SD_D3

1

24
23
22
21
20
19
18
17

Close to chip pin
SD_D2_R
SD_D3_R
SD_CMD_R
DV33_18
SD_CLK_R

0_4 SD_D2
0_4 SD_D3
0_4 SD_CMD

R309
R312
R313

33_4 SD_CLK

R317

1U/10V_4
C442

C441
5.6P/16V_4

SI modify

CARD READER

RTS5237

9
10
11
12
13
14
15
16

GND

NC
NC
NC
SP6
SP5
SP4
DV33_18
SP3

RTS5237_AV12

R330

RTS5237_DV12S

*0_4/S

0.1U/10V_4

C453

4.7U/6.3V_6

C454

0_4
0_4

SD_D0
SD_D1

CLOSE CONN
C457

C450

Close to chip pin

+3VCARD

SD_CLK
SD_D0
SD_D1
SD_WP

C459

C449

C458

0.1U/10V_4

4.7U/6.3V_6

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

SD_D2
SD_D3
SD_CMD
SD_CD#

+3VCARD

0.1U/10V_4

SI modify to short pad

RTS5237_AV12

RTS5237_RREF
1
2
C451 *100P/50V_4

R322 6.2K/F_4

SD_D0_R
R318
SD_D1_R R321

*0.1U/10V_4

ZϳϬϬϵŶĞĞĚĐŽůƐĞƚŽŚŝƉ

RTS5237_DV12S

CN15
C

10U/6.3V_8

CARDREADER CONN

+3V
R5106
C460

R3X Type

0.1U/10V_4

+3VCARD

SATA ODD
CONNECTOR

B

15

17
15

SATA_RXN2
SATA_RXP2

<7>
<7>

ZERO_ODD_DP#
ZERO_ODD_DA#

+5V_ODD

*0_4/S

20
19
ODD_EJECT#

SI modify to short pad
+5V

P6
14 SATA ODD
R564

R824
10K_4

<9>

R40

+5V_ODD

3

2
1

+5V_ODD

2

*0_8

SI change footprint
120 mils
+5V_ODD

<27>

20
19

1

CN24

18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

SI modify to short pad

ZERO_ODD_DA#
<27>

ZERO_ODD_DP#

R574

ZERO_PWR_ODD

*0_4/S

High : ODD power down
Low : ODD power on

+5V_ODD

2

R823
22_8

Q43
2N7002

2

C765
0.01U/25V_4
C767
0.01U/25V_4
2 1K_4
R822 1

Q44
AO3404

1

SATA_RXN14_C
SATA_RXP14_C
ZERO_ODD_DP#

<7>
<7>

C913
0.027U/25V_6

3

17

5
6
8
9
10
11
1
4
7
12
13

SATA_TXP2
SATA_TXN2

2
SATA_RXP15_C
SATA_RXN15_C

C912
C910

*0.01U/25V_4
*0.01U/25V_4

SATA_TXN15_C
SATA_TXP15_C

C909
C911

*0.01U/25V_4
*0.01U/25V_4

SATA_RXP2
SATA_RXN2

Q47
2N7002

SATA_TXN2
SATA_TXP2

1

S7
P1

RXN
RXP
DP
+5V
+5V
MD
GND1
GND2
GND3
GND
GND

New Type

+3V

0.01U/25V_4
0.01U/25V_4

1

16

C766
C764

2

14

SATA_TXP14_C
SATA_TXN14_C

3

16

2
3

C914
0.1U/10V_4

R821
330K_6

1

14

TXP
TXN

15'' SATA ODD

Bypass CAP close conn

CN26
S1

+5V

+12VALW

14'' SATA ODD

A

0_8

SI modify

C452

10U/6.3V_8

B

C

DAT2
DAT3
CMD
C/D
VSS1
VDD
CLK
VSS2
DAT0
DAT1
W /P
GND
GND
GND
GND

A

*15 SATA ODD
C903
10U/6.3V_8

C905
0.1U/10V_4

C901
0.1U/10V_4

C902
0.1U/10V_4

352-(&78
4XDQWD&RPSXWHU,QF

C904
0.1U/10V_4

SI change pin define/PN
& footprint
Size
Custom

Document Number

5

4

3

2

Rev
1A

CR RTS5237 & CR SOCKET

Date: Friday, May 03, 2013

Sheet
1

23

of

40

A

B

C

D

WŝŶϭ͗нϯsWh;>/^t/d,WtZͿ
WŝŶϮ͗WKtZ>
WŝŶϯ͗>/^t/d,
WŝŶϰ͗'E
WŝŶϱ͗'E
WŝŶϲ͗WKtZKEη

+3VPCU
Q1A
R356
10K/F_4

0.1U/10V_4

<8,11,12,13,19>

SMB_RUN_CLK

CN4
<21>

NBSWON1#

C57

2

3

<27>
<8,11,12,13,19>

Q29
DDTC144EUA-7-F

POWER BTN CONN
DFFC06FR062
88513-0601-6p-l-smt

C51

SMB_RUN_DAT

C474
0.1U/10V_4

6

10P/50V_4

C256

BLM18BA470SN1D
BLM18BA470SN1D
10P/50V_4

L7
L6

TPDATA

6
5
4
3
2
1

TPCLK-1
TPDATA-1
TP_SMB_DATA
TP_SMB_CLK

TP_SMB_DATA

4

CN7
C194

*10P/50V_4

C195

*10P/50V_4

C219

0.1U/10V_4

2N7002KDW

+3VSUS

&E

Bypass CAP close conn

Mini PCI-E Card 2- Full size
mSATA

SATA_TXP0_C C253
SATA_TXN0_C C254
SATA_RXN0_C C251
SATA_RXP0_C C252

0.01U/16V_4
0.01U/16V_4
0.01U/16V_4
0.01U/16V_4

SATA_TXP0
SATA_TXN0

<7>
<7>

SATA_RXN0
SATA_RXP0

<7>
<7>

C274

10U/6.3VS_6

C278

0.1U/10V_4

<9>

R559

DEVSLP1

*0_4
+3V

FAN1

<27>
+3V

FAN1_PWM

<27>
+3V

15
2
3
46

FAN1SIG
R186

5
3

6

+1.5V

FAN Connect

4.7K_4

CN21

51
49
47
45
43
41
39
37
35
33
31
29
27
25
23
21
19
17

+5V
月役EC

+5V
C536

*10U/6.3V_8

C539

*10U/6.3VS_6

C542

4.7U/6.3V_6

FAN1_PWM C277

*220P/50V_4

C543

0.1U/10V_4

FAN1SIG

*220P/50V_4

WůĂĐĞĂƉĐůŽƐĞƚŽ
ĐŽŶŶǁŝƚŚŝŶϭϬϬŵŝůƐ

19
C276

<7>
<7>

+5V: 2 A(4 Pin)

SATA HDD(1ST)

+3V: 2 A(4 Pin)

DFHS13FS019
sata-ah534-00-13p-r

<7>
<7>

Gnd : (5 Pin)

SATA_TXP1
SATA_TXN1
SATA_RXN1
SATA_RXP1

C270
C269

0.01U/16V_4
0.01U/16V_4

SATA_TXP1_C
SATA_TXN1_C

C273
C275

0.01U/16V_4
0.01U/16V_4

SATA_RXN1_C
SATA_RXP1_C

+3V

dWD;ϭ͘ϮͿ

TPM_XIN
TPM_XOUT

,сϮ͘ϱϰŵŵ

2

R581

C265

4.7U/6.3V_6

C573

0.1U/10V_4

C575

0.1U/10V_4

C576

0.1U/10V_4

C266

*4.7U/6.3V_6

Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
GND
PETp0
PETn0
GND
GND
PERp0
PERn0
GND
Reserved
Reserved

15
13
11
9
7
5
3
1

CLK_PCI_TPM

,сϰ͘Ϭ

GND
REFCLK+
REFCLKGND
CLKREQ#
BT_CHCLK
BT_DATA
W AKE#
MINI PCIE H4

*10M_4
C570

4.7U/6.3V_6

+3.3V
GND
+1.5V
LED_W PAN#
LED_W LAN#
LED_W W AN#
GND
USB_D+
USB_DGND
SMB_DATA
SMB_CLK
+1.5V
GND
+3.3Vaux
PERST#
W _DISABLE#
GND

GND

1

Main HDD

1

88513-0601-6p-l-smt
DFFC06FR062

C257

25 mils

+5V

3

+3VSUS
<27>

R108 4.7K_4

Q1B

^d,ŽŶŶĞĐƚŽƌ;ĂďůĞƚLJƉĞͿ

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19

TPCLK

*220P/50V_4

*220P/50V_4

CN25

<27>

GND

C391
*220P/50V_4

PWR_LED#

TPCLK
TPDATA

TP_SMB_CLK
R107 4.7K_4

+3V

2 PWR_LED#

1

<27>

LID_EC#

4.7K_4
4.7K_4

Reserved
Reserved
Reserved
Reserved
Reserved
+1.5V
GND
+3.3V

52
50
48
46
44
42
40
38
36
34
32
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2

2

53

<27>

DEEP_PWRLED#

DEEP_PWRLED#

1
2
3
4
5
6

DEEP_PWRLED#

3

ƵĂů

R169
R165

+3VSUS

5

+3VPCU
4

4

2N7002KDW

54

C43

Ϯϰ

E

dŽƵĐŚWĂĚŽŶŶĞĐƚŽƌ

WŽǁĞƌŽƚƚŽŶŽŶŶĞĐƚŽƌ

DFHS52FR108

R582
*33_4
Y6

1
2

$GGUHVV
+,*+

%$''
(+)

C827
*12p

4
3
C826
*12p

*32.768KHZ

C828
*10P/50V_4

+3VS5

GHIDXOW

)25(0,
C822
*0.1U/10V_4

+3V

+VIN
+VIN
+VIN
+VIN
+VIN
+VIN
+VIN
+VIN
+VIN
+VIN
+VIN
+VIN

C361
C264
C610
C611
C612
C613
C615
C614
C616
C618
C617
C619

*0.1U/25V_4
*0.1U/25V_4
*0.1U/25V_4
*0.1U/25V_4
*0.1U/25V_4
*0.1U/25V_4
*0.1U/25V_4
*0.1U/25V_4
*0.1U/25V_4
*0.1U/25V_4
*0.1U/25V_4
*0.1U/25V_4

U41
<7,26,27>
<7,26,27>
<7,26,27>
<7,26,27>

LAD0
LAD1
LAD2
LAD3

LAD0
LAD1
LAD2
LAD3

<8>
<7,26,27>
1

R584
R585
R586
R587

*0_4
*0_4
*0_4
*0_4

CLK_PCI_TPM

LFRAME#
R588
LFRAME#
<6,11,14,22,23,26,27>
PLTRST#
<9,27>

+3V
<6,27>

*0_4

SERIRQ
R577

CLKRUN#

LAD0_T
LAD1_T
LAD2_T
LAD3_T
CLK_PCI_TPM
LFRAME#_T
PLTRST#
LPCPD#_TPM
SERIRQ
*4.7K/F_4
CLKRUN#

26
23
20
17
21
22
16
28
27
9
15
1
3
12

LAD0
LAD1
LAD2
LAD3
LCLK

VDD
VDD
VDD
VSB
GND
GND
GND
GND

LFRAME#
LRESET#
LPCPD#
SERIRQ
TEST/BADD
CLKRUN#
NC
NC
NC

GPIO
GPIO2
PP
TESTI

XTALI/32K IN
XTALO

10
19
24
5

+3V
C823
*0.1U/10V_4

4
11
18
25

C824
*0.1U/10V_4

C825
*0.1U/10V_4

+3V

R579
*4.7K/F_4
R578
*4.7K/F_4

6
2

TPM_PP
LPCPD#_TPM

7
8

TPM_PP

13
14

TPM_XIN
TPM_XOUT

+VIN
+VIN
+VIN
+VIN
+VIN
+VIN
+VIN
+VIN
+VIN
+VIN
+VIN
+VIN
+VIN
+VIN

C29
C69
C196
C240
C259
C5
C11
C39
C371
C370
C447
C395
C261
C268

0.1U/25V_4
0.1U/25V_4
0.1U/25V_4
0.1U/25V_4
0.1U/25V_4
0.1U/25V_4
0.1U/25V_4
0.1U/25V_4
0.1U/25V_4
0.1U/25V_4
0.1U/25V_4
0.1U/25V_4
0.1U/25V_4
0.1U/25V_4

+PRWSRC
+PRWSRC
+PRWSRC
+PRWSRC

C19
C12
C44
C110

0.1U/25V_4
0.1U/25V_4
0.1U/25V_4
0.1U/25V_4

BATT+
BATT+
BATT+
BATT+

C17
C15
C18
C16

*0.1U/25V_4
*0.1U/25V_4
*150P/50V_4
*150P/50V_4
C571
0.01U/16V_4

+1.35VSUS

C625
C624
C626

*0.1U/25V_4
*0.1U/25V_4
*0.1U/25V_4

+5VS5

C632
C633

*0.1U/25V_4
*0.1U/25V_4

B

C

D

C409
C408

+PRWSRC
+PRWSRC

C572
*4.7U/6.3V_6

*0.1U/25V_4
*0.1U/25V_4

1

352-(&78
4XDQWD&RPSXWHU,QF
Size
Custom

Document Number

Rev
1A

,ͬŵ^dͬ&Eͬ>

Date: Friday, April 26, 2013
A

C574
*0.1U/10V_4

<6,7,8,9,10,11,12,13,14,15,16,17,19,20,21,22,23,25,26,27,32,33,34>
+3V
<6,20,21,23,25,26,33>
+5V
<4,7,21,25,26,27,28,29>
+3VPCU
<28>
BATT+
<23,28,33,35>
+12VALW

R580
*0_4

*SLB9635TT1.2-FW3.17

+1.5V

Sheet
E

24of

40

3

MUTE_LED_CNTL_R1

2

MUTE_LED_CNTL_M

Q21
2N7002K
R348
10K/F_4

1

SI modify

<27>

MX1
MX7
MX6
MY9
MX4
MX5
MY0
MX2
MX3
MY5
MY1
MX0
MY2
MY4
MY7
MY8
MY6
MY3
MY12
MY13
MY14
MY11
MY10
MY15
MY16
MY17

1 200/F_6 CAPSLED#_R
R64 2
1MUTE_LED_CNTL_R
MUTE_LED_CNTL_R1 R67 2
WIRELESS_ON_R
200/F_6
WIRELESS_OFF_R
LED_PW
+3V

CAPSLED#

32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

.(<%2$5'38//83
+3VPCU

10
9
8
7
6

MY13
MY12
MY3
MY6

RP3

1
2
3
4
5

10
9
8
7
6

MY1
MY5
MY0
MY9

RP2

MY14
MY11
MY10
MY15

1
2
3
4
5

MY2
MY4
MY7
MY8

*10P8R-8.2K

+3VPCU

MY8
MY9
MY10
MY11

C114
C63
C137
C136

*220P/50V_4
*220P/50V_4
*220P/50V_4
*220P/50V_4

MY1
MY2
MY4
MY0

C89
C100
C102
C71

*220P/50V_4
*220P/50V_4
*220P/50V_4
*220P/50V_4

MX4
MX6
MX3
MX2

C64
C62
C80
C73

*220P/50V_4
*220P/50V_4
*220P/50V_4
*220P/50V_4

MX7
MX0
MX5
MX1

C61
C93
C68
C60

*220P/50V_4
*220P/50V_4
*220P/50V_4
*220P/50V_4

MY12
MY13
MY14
MY15
MY16
MY17

C132
C133
C134
C139
C141
C143

*220P/50V_4
*220P/50V_4
*220P/50V_4
*220P/50V_4
*220P/50V_4
*220P/50V_4

1

+5V

R359
1K/F_4

1 *200/F_6

R364 2

1 *200/F_6

WIRELESS_ON_R

WIRELESS_OFF_R

Q24
DDTC144EUA-7-F
<27>

D

Q26
DDTC144EUA-7-F

2

WIRELESS_ON

Ϯϱ

+5V

R350
1K/F_4

R355 2

*10P8R-8.2K

+3VPCU

*220P/50V_4
*220P/50V_4
*220P/50V_4
*220P/50V_4

3

MX[0..7]

MX[0..7]

3
<21>
D

KB CONN

MY[0..17]

MY[0..17]

<27>

C83
C124
C128
C106

3

<27>

2

MY5
MY6
MY3
MY7

<27>

2

WIRELESS_OFF

1

4

1

5

KEYBOARD Con.

*8.2K_4 MY16
*8.2K_4 MY17

R77
R79

CN5
50698-03201-001-32p-l
DFFC32FR039

R6X Type

C

C

Hole

1

2

*Clamp-Diode
USBP0+_C

C546

1

2

<8>
<8>

*Clamp-Diode

C557
C567

USB30_TX1USB30_TX1+

0.1U/10V_4 USB3_1- 1
0.1U/10V_4 USB3_1+ 4

2
3

L34

USB30_TX1-_C
USB30_TX1+_C

*DLP11SN900HL2L

1

2

*Clamp-Diode
USB30_RX1-_C C541

1

2

USB3_1USB3_1+

R529
R537

0_4
0_4

USB30_TX1-_C
USB30_TX1+_C

USB3_2USB3_2+

1
H33
*H-TC279BC216D141P2

H34
*H-TC279BC216D141P2

H10
*H-TC279BC216D141P2

Nut PN:MBFF4001010
1

SI del 0ohm
USB30_TX1+_C C568

SI modify

SI add

1

1
4

USB30_RX1USB30_RX1+

H29
h-tc256bc236d145p2

1

<8>
<8>
USB30_TX1-_C C555

VBUS
DD+
GND
SSRXSSRX+
GND
SSTXSSTX+

1
2
3
4

*Clamp-Diode

1
2
3
4
5
6
7
8
9

FAN nut
H27
h-tc256bc236d145p2

1

2

1
2
3
4
5
6
7
8
9

H30
*INTEL-BKT-SHARK-ULT

H38
*spad-re197x394np

1

1

+5V_USBP0
USBP0-_C
USBP0+_C
*DLP11SN900HL2L
2
USB30_RX1-_C
3
USB30_RX1+_C

DLP11SN900HL2L
3
2
L32

H37
*spad-re197x394np

1

C549

L33
4
1

USBP0USBP0+

1A

CN20
USB3.0 CONN

H36
H39
*h-tc197bc102d102pt
*h-tsbc102d102pt

1

USBP0-_C

<8>
<8>

USB 3.0

*AVLC5S_4
1000P/50V_4

1

VC4
C529

13
12
11
10

USB 2.0/3.0 Combo

0.1U/10V_4
470P/50V_4

13
12
11
10

C533
C537

*Clamp-Diode
R457
R467

0_4
0_4

USB30_TX2-_C
USB30_TX2+_C

USB30_RX1- R507
USB30_RX1+ R508

0_4
0_4

USB30_RX1-_C
USB30_RX1+_C

USB30_RX2- R404
USB30_RX2+ R409

0_4
0_4

USB30_RX2-_C
USB30_RX2+_C

DFHS09FR122

B

B

usb-2ub4029-200201f-9p

*Clamp-Diode
C515

1

2

*Clamp-Diode

<8>
<8>

USB30_RX2USB30_RX2+

<8>
<8>

USB30_TX2USB30_TX2+

+5V_USBP0
USBP5-_C
USBP5+_C
*DLP11SN900HL2L
2
USB30_RX2-_C
3
USB30_RX2+_C

DLP11SN900HL2L
3
2
L29 1
4

C226 0.1U/10V_4
C230 0.1U/10V_4

USB3_2- 1
USB3_2+ 4

2
3

L31

1

2

1A

USB30_TX2-_C
USB30_TX2+_C

1
2
3
4
5
6
7
8
9

VBUS
DD+
GND
SSRXSSRX+
GND
SSTXSSTX+

*DLP11SN900HL2L

*Clamp-Diode
USB30_RX2-_C C510

1

2

2

usb-2ub4029-200201f-9p

150 mils (Iout=3.7A)

*Clamp-Diode

+5VS5

U20

A

<21,27>

2
3
4
1

USBPW_ON#
VC5
*AVLC5S_4

C538
1U/6.3V_4

VIN1
VIN2
EN
GND

OUT3
OUT2
OUT1
OC

8
7
6
5

+5V_USBP0
C525
1
+5V_USBP0

H17
*h-tsbc394d118p2

1
2

1

1

H18
*H-C394D118P2

Mini-PCIe & mSATA nut

H15
*H-C394D118P2

H28
*h-c236d102p2

SI delete

H19
*H-C394D118P2

H24
*H-C393D354P2

SI modify

H22
*O-U6X-2

Nut PN:MBZR7001010

220U/6.3V_6X4.5
2
+

1

SI modify

SI modify

*Clamp-Diode

DFHS09FR122
USB30_RX2+_C C512

1

CN17
USB3.0 CONN

1
2
3
4
5
6
7
8
9

1

USB 3.0

13
12
11
10

USB30_TX2+_C C527

Active Low

SI modify

+5VS5
+3VPCU

Size
Custom

Document Number

3

2

Rev
1A

h^ϯ͘Ϭͬ<

Date: Monday, May 06, 2013
4

A

352-(&78
4XDQWD&RPSXWHU,QF

UP7534BRA8-20

<13,21,24,29,31,32,33,34,36>
<4,7,21,24,26,27,28,29>

5

H16
*O-U83M-1

1

USBP5+_C

USBP5USBP5+

*AVLC5S_4
1000P/50V_4

H25
*H-TC236BC314D102P2

1

<8>
<8>

L30
4
1

0.1U/10V_4
470P/50V_4

VC1
C262

H14
*H-TC157BC236D118P2

1

*Clamp-Diode

C532
C535

1

2

2

*Clamp-Diode

1

1

1

2

1

USB30_TX2-_C C523

C519

1

1

USBP5-_C

C544

H20
*H-C394D118P2

13
12
11
10

USB30_RX1+_C

H13
*H-C394D118P2

Sheet
1

25of

40

A

B

C

D

+1.5V

E

Ϯϲ

+3V_WLAN_P

+3V_WLAN_P
+3VPCU

+3VS5
+3V_WLAN_P

+1.5V
+1.5V
+1.5V
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
PETp0
PETn0
PERp0
PERn0
REFCLK+
REFCLKCLKREQ#
BT_CHCLK
BT_DATA
W AKE#
Reserved
Reserved
GND
GND
GND
GND
GND

C438
0.1U/10V_4

C415
10U/6.3VS_6
R324
10K_4

ƉŚ

+3.3V
+3.3V
+3.3Vaux
Reserved
Reserved
LED_W LAN#
LED_W PAN#
LED_W W AN#
USB_D+
USB_DSMB_DATA
SMB_CLK
PERST#
W _DISABLE#
Reserved
Reserved
Reserved
Reserved
Reserved
GND
GND
GND
GND
GND
GND
GND

52
2
24
41
39
44
46
42
38
36
32
30
22
20
16
14
12
10
8
50
40
34
26
18
4
9

C444
*0.022U/25V_4

Q18
ME2303T1

WLAN_LED#

R293

4.7K_4 +3V_WLAN_P

R294

*0_4/S

RF_LINK#

<27>

SI modify to short pad
USBP6+
USBP6PLTRST#
PLTRST#
INT_RF_OFF#
LAD0
LAD1
LAD2
LAD3
LFRAME#

R560

DŝŶŝĂƌĚ
t>Eͬd;KƉƚŝŽŶͿ

<8>
<8>
<6,11,14,22,23,24,27>

2

200K_4

R316
C8538

<27>

2N7002E

R296
LAD0
<7,24,27>
LAD1
<7,24,27>
LAD2
<7,24,27>
LAD3
<7,24,27>
LFRAME#
<7,24,27>

10K_4

*0.022U/25V_4

C439

SI modify

*0.1U/10V_4

+3V_WLAN_P

Q40
2N7002E

3

&ŽƌD/^ƵŐŐĞƐƚŝŽŶ

1

CLK_24M_DEBUG
R63
RF_OFF

Accelerometer Sensor

<6,22,23,27>

2

3

3

PCIE_WAKE#

Q17

SI modify to short pad
*0_6/S

+3V_WLAN_P

+3V_WLAN_P

R308

+G_SEN_PW

C77
0.1U/10V_4

U2
HP3DC2TR

1
14

C107
0.1U/10V_4

Vdd_IO
VDD

NC
NC

1
ACCEL_INTA#_R
RB500V-40
TP6

ACCEL_INTA#

R69
<27>
<27>

C55
*22P/50V_4

7
6
4

*0_4/S
MBDATA3
MBCLK3

MBDATA3
MBCLK3

8

+G_SEN_PW

+G_SEN_PW

MBDATA3

C98

*33P/50V_4

MBCLK3

C111

*33P/50V_4

R73
R72

+G_SEN_PW

11
9

4.7K_4
4.7K_4

SDO
SDA
SCL

GND
GND

10
13
15
16

*0_6/S

+3V

R817

*0_6

+5V

1
MINICAR_PME#
DDTC144EUA-7-F

'ƌĞĞŶ><ŝƌĐƵŝƚƌLJ

5
12

ϮϬŵŝůƐǁŝĚƚŚ;ŵŝŶͿ

CS

+3VPCU

2

нϯsͺZdͺϬ͕нϯsͺZdͺZ͕нϯsͺZd͘͘
+3VLANVCC

<22>
LAN_XTAL25_IN
<8>
PCH_XTAL24_IN
<7>
CLKGEN_RTC_X1
<16>
CLK_27M_XTAL_IN

MBDATA3
MBCLK3

R561
R562

0_4
0_4

+3VLANVCC
+1.05V

USBP7+_C
USBP7-_C

+3V_GFX

SI modify to short pad

R816

3
Q19

EC_PCIE_WAKE#

+3V_RTC_0

AL003DC2A00

USBP7+
USBP7-

Touch screen

RESERVED
RESERVED
RESERVED
RESERVED

INT1
INT2

10K/F_4

2
3
<27>

2

1
MINICAR_PME#
*DDTC144EUA-7-F

2

R46

2
D5

*33P/50V_4

+3V_WLAN_P

^ƵƉƉŽƌƚtĂŬĞ&ƵŶĐƚŝŽŶ;ZĞƐĞƌǀĞͿ

ACCEL_INTA#

EC3
*0_4

<9>

3

ACCEL_INTA#

4

+3V

+3V_AOCS

2

EC_AOCS#

D/E/ZͲϭϭϬϬϮϭͲϱϮϭϯϭͲϱϮWͲZhs

<9>

*0_8

24mil

Q20

56
55
54
53

MINI PCIE H=4.0
DFHS52FR108

C417
0.1U/10V_4

3

,сϰ͘Ϭ

CN14

6
28
48
2N7002E
51
R297
*0_6 INT_BT_OFF#
+5V
4
49
47
45
R295
*0_4
<27>
EC_DEBUG
19
<8>
CLK_24M_DEBUG
PLTRST# 17
33
<8>
PCIE_TXP3_WLAN
31
<8>
PCIE_TXN3_WLAN
25
<8>
PCIE_RXP3_WLAN
23
<8>
PCIE_RXN3_WLAN
13
<8>
CLK_PCIE_WLANP
11
<8>
CLK_PCIE_WLANN
REQ_WLAN# 7
R284
*0_4/S
<8>
PCIE_CLKREQ_WLAN#
5
R283
*0_4
<9>
BT_COMBO_EN#
3
SI modify to short pad
1
MINICAR_PME#
43
37
35
29
27
21
15

C418
0.1U/10V_4

3

3

C420
10U/6.3VS_6

1

+3V_WLAN_P

C416
0.1U/10V_4

1

1
Q39

+1.5V

C419
0.01U/16V_4

2

R292
10K_4

HOLE
HOLE
PAD
PAD

BT_OFF

2

<9>

R534
R518

33_4
33_4

R536

22_4

C569

0.1U/10V_4

C548

0.1U/10V_4

C434

0.1U/10V_4

6
5
9
CLK_27M_XTAL_IN_R12
LAN_XTAL25_IN_R
PCH_XTAL24_IN_R

8
3
11
GEN_XTAL25_OUT 16
1
GEN_XTAL25_IN

U21

25M
24M
32Khz
27Mhz/NC

+V3.3A
VDD
VBAT

15
2
10

C547

0.1U/10V_4

+3V_RTC_R R540
C267

VDD_RTC_OUT
VDDIO_25M
VDDIO_24M
GND
VDDIO_27/NC
GND
GND
XTAL_OUT
GND
XTAL_IN

360/F_4
22U/6.3VS_8

14

+3V_RTC

7
13
4
17

C558
2.2U/6.3V_6

SLG3NB3354VTR
+VCC_TS
C545

12P/50V_4

C260

0.1U/10V_4

+3VLANVCC

C58

*10P/50V_4

LAN_XTAL25_IN

UMA

AL003355000

C487

*10P/50V_4

PCH_XTAL24_IN

DIS

AL003354001

C263

*10P/50V_4

CLK_27M_XTAL_IN

P/N

R536

C434

GEN_XTAL25_IN
0_6

2
1

R236
U5

27>

C358
*1U/10V_4

5

IN

4
TS_ON

TS_ON

OUT

IN

3

GND

1

+VCC_TS

CN22
L42
*MCM2012B900GBE
2
1
3
4

2

ON/OFF

<8>
<8>

USBP7USBP7+

*IC(5P) G5243AT11U
R244
Close to CN22
*100K/F_4

EC41
*100P/50V_4

SI modify to short pad

25MHZ +-10PPM

USBP7-_C
USBP7+_C
TS_INTB#

C623
0.1U/10V_4

1
2
3
4
5
6

C540

GEN_XTAL25_OUT

15P/50V_4

<24,28>
+PRWSRC
<6,7,8,9,10,11,12,13,14,15,16,17,19,20,21,22,23,24,25,27,32,33,34>
+3V
<6,20,21,23,24,25,33>
+5V
<4,7,21,24,25,27,28,29>
+3VPCU

Touch screen
R558

*0_4/S

Install Install

352-(&78
4XDQWD&RPSXWHU,QF
Size
Custom

Document Number

B

C

D

Rev
1A

t>Eͬ'Ͳ^ĞŶƐŽƌͬ'Ͳ><ͬd^

Date: Friday, May 03, 2013
A

N/A

Y5
C363
*1U/10V_4

4
3

1

N/A

Sheet
E

26of

40

1

1

2

3

4

5

6

7

8

Ϯϳ

3920_RST#
+3VPCU

For GPU thermal
For Gsensor
For Touch-Pad

MX0
MX1
MX2
MX3
MX4
MX5
MX6
MX7

<25>
<25>
<25>
<25>
<25>
<25>
<25>
<25>
<25>
<25>
<25>
<25>
<25>
<25>
<25>
<25>
<25>
<25>

MY0
MY1
MY2
MY3
MY4
MY5
MY6
MY7
MY8
MY9
MY10
MY11
MY12
MY13
MY14
MY15
MY16
MY17

<17>
GPUT_CLK
<17>
GPUT_DATA
<26>
MBCLK3
<26>
MBDATA3
<24>
TPCLK
<24>
TPDATA

MX0
MX1
MX2
MX3
MX4
MX5
MX6
MX7

55
56
57
58
59
60
61
62

MY0
MY1
MY2
MY3
MY4
MY5
MY6
MY7
MY8
MY9
MY10
MY11
MY12
MY13
MY14
MY15
MY16
MY17

39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
81
82

GPUT_CLK
GPUT_DATA

83
84
85
86
87
88

TPCLK
TPDATA
BIOS_RD#
BIOS_WR#
BIOS_CS#
ACIN

<28,33>
ACIN
SI Modify <7>
PCI_SERR#

EC_GPXD1

<6>
SUSWARN#_EC
<26>
RF_LINK#
<6>
SLP_SUS#_EC
<7>
GPIO33_EC
<6>
DPWROK_EC

C

D8

RB500V-40
EC_PECI_R

<21,25>
USBPW_ON#
<31,33>
SUSON
<30,31,33>
MAINON
<10>
SLP_SUS_ON
<29>
S5_ON
SI modify
*0_4/S R326
<4>
THRM_MOINTOR1
*0_4 R323
<27,28>
SYS_I

USBPW_ON#
SUSON
MAINON

THRM_ALERT_HW#1
<23>

ODD_EJECT#
<28>
MBATLED0#
<28>
AC_LED_ON#
<25>
WIRELESS_ON
<25>
WIRELESS_OFF

119
120
128
89
76
109
110
112
114
115
116
117
118
97
98
99
100
101
102
103
104
105
106
107
108

KSI0/GPIO30
KSI1/GPIO31
KSI2/GPIO32
KSI3/GPIO33
KSI4/GPIO34
KSI5/GPIO35
KSI6/GPIO36
KSI7/GPIO37
KSO0/GPIO20
KSO1/GPIO21
KSO2/GPIO22
KSO3/GPIO23
KSO4/GPIO24
KSO5/GPIO25
KSO6/GPIO26
KSO7/GPIO27
KSO8/GPIO28
KSO9/GPIO29
KSO10/GPIO2A
KSO11/GPIO2B
KSO12/GPIO2C
KSO13/GPIO2D
KSO14/GPIO2E
KSO15/GPIO2F
KSO16/GPIO48
KSO17/GPIO49
PSCLK1/GPIO4A
PSDAT1/GPIO4B
PSCLK2/GPIO4C
PSDAT2/GPIO4D
PSCLK3/GPIO4E
PSDAT3/GPIO4F
RD/GPIO5B
W R/GPIO5C
SPICS/GPIO5A
SELIO/GPIO50
AD5/GPIO43
D0/GPXD0
D1/GPXD1
D2/GPXD2
D3/GPXD3
D4/GPXD4
D5/GPXD5
D6/GPXD6
D7/GPXD7
A0/GPXA0
A1/GPXA1
A2/GPXA2
A3/GPXA3
A4/GPXA4
A5/GPXA5
A6/GPXA6
A7/GPXA7
A8/GPXA8
A9/GPXA9
A10/GPXA10
A11/GPXA11

V18R

1

2

124

SCI/GPIOE
GA20/GPIO0
KBRST/GPIO1
ECRST

C429
0.1U/10V_4

C412
4.7U/6.3V_6

3

L24
BLM18BA470SN1D

1 EC_PWROK
RB500V-40

adapter Type check

+3V

R353

10K/F_4

+3VPCU

+3VPCU

1

THRM_ALERT_HW#1

+3VPCU_EC
0.1U/10V_4

AD_TYPE R327

DA0/GPO3C
DA1/GPO3D
DA2/GPO3E
DA3/GPO3F
PW M1/GPIOF
PW M2/GPIO10
FANPW M1/GPIO12
FANPW M2/GPIO13
FANFB1/GPIO14
FANFB2/GPIO15
SCL1/GPIO44
SDA1/GPIO45
SCL2/GPIO46
SDA2/GPIO47

63
64
65
66

TEMP_MBAT
AD_TYPE
AD_AIR
SYS_I

68
70
71
72

TEMP_MBAT
AD_AIR
SYS_I

21
23
26
27
28
29

FAN1_PWM

77
78
79
80

MBCLK
MBDATA
MBCLK2
MBDATA2

6

SUSB#

14
15

HWPG
H_PROCHOT#_EC

16
17
18
19
25
30
31
32

SUSC#

SIO_EXT_SMI#

34
36

VRON
DGPU_PROCHOT#

3

DGPU_OVT#

<17>

R325

100/F_4

DGPU_PWROK
R382

Q27

<17>

4.7K_4

AD_ID

<28>

R342
12.1K/F_4

C455
100P/50V_4

<9,16,36>

+1.05V

*0_4

IMVP_PWRGD_R

C497

3

C456
0.1U/10V_4

R567

FAN1_PWM
<24>
FB_CLAMP_TGL_REQ#_EC
FAN1SIG
<24>
TS_ON
<26>

FAN1SIG

1

Q25
*2N7002

FB_CLAMP
<15,17>
ZERO_PWR_ODD
<23>

ZERO_PWR_ODD

10K_4

<28>

<28>
<27,28>

LAN_POWER
<33>
DGPU_PROCHOT_EC#
<17,34>
BATSHIP
<28>
PCIE_WAKE#
<6,22,23,26>

BATSHIP
PCH_PCIE_WAKE#

A

Open Drain need pu high

4.7U/6.3V_6

AD0/GPI38
AD1/GPI39
AD2/GPI3A
AD3/GPI3B

Change to 1SS355 as Current loss
D10
1SS355

C421

2

C482

4.7K_4

2
D11

2

EC_RCIN#

9
22
33
96
111
125
67

R377

<4>

220P/50V_4

1

PM_THRMTRIP#

<9>

METR3904-G

MBCLK
<28>
MBDATA
<28>
MBCLK2
<8,13,19>
MBDATA2
<8,13,19>

for Battery charge/charge
for DDR Thermal IC
H_PROCHOT#

H_PROCHOT#

<2,32>

3

B

SIO_EXT_SCI#
R287

<25>
<25>
<25>
<25>
<25>
<25>
<25>
<25>

20
1
2
37

SIO_EXT_SCI#
*0_4 SLP_S0#_EC
RCIN#
3920_RST#

VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
AVCC

Q28
METR3904-G
2 OVT_DETC

GPIO4
GPIO7
GPIO8
GPIOA
GPIOB
GPIOC
GPIOD
GPIO11
GPIO16
GPIO17
GPIO18
GPIO19
GPIO1A

SUSB#
HWPG

GPIO5E
GPIO5D

2

H_PROCHOT#_EC

<4,11,29,30,31>

NBSWON1#
R291

*0_4/S

VRON
<32>
DGPU_PROCHOT#

73
74
75
90
91
92
93
95
121
126
127

EC_PCIE_WAKE#
THRM_CPU
GPIO42_EC
DNBSWON#
CAPSLED#
PWR_LED#
EC_PWROK
RSMRST#
VOLMUTE#
BIOS_SPI_CLK
LID_EC#

123

CRY2

122

CRY1

*10K/F_4

EC_PCIE_WAKE#
THRM_MOINTOR

LID_EC#
C432

NBSWON1#
MBCLK
MBDATA
EC_PCIE_WAKE#
LID_EC#

10K/F_4
4.7K_4
4.7K_4
10K/F_4
47K/F_4

Reserve for ENE Hold time issue

<26>
<4>

DNBSWON#
<6,11>
CAPSLED#
<25>
PWR_LED#
<24>
EC_PWROK
<6>
RSMRST#
<6>
VOLMUTE#
<21>

R307

R290
R371
R370
R361
R285

+3VPCU

<34>

SI Add Pin36 to DGPU_PROCHOT# for DB error

C405
*47P/50V_4

Q13
2N7002K

R289
SUSC#
<6,11>
SUSACK#_EC
<6>
EC_AOCS#
<26>
NBSWON1#
<24>
EMU_LID
<20>
EC_DEBUG
<26>
FB_CLAMP1
<15>
SIO_EXT_SMI#
<7>

TP116

AD6/CIR_RX/GPIO40
AD7/GPIO41
AD4/GPIO42
GPIO52
GPIO53
GPIO54
GPIO55
GPIO56
GPIO57
GPIO58
GPIO59

B

<6,11>

1

<9>
PCH_SLP_S0_N
<9>

<6,11>

CLKRUN#

SERIRQ
LFRAME
LAD0
LAD1
LAD2
LAD3
PCICLK
PCIRST/GPIO5
CLKRUN

+3VPCU

2

A

3
4
10
8
7
5
12
13
38

SERIRQ
LFRAME#
LAD0
LAD1
LAD2
LAD3

<9,24>
SERIRQ
<7,24,26>
LFRAME#
<7,24,26>
LAD0
<7,24,26>
LAD1
<7,24,26>
LAD2
<7,24,26>
LAD3
<8>
CLK_24M_KBC
<6,11,14,22,23,24,26>
PLTRST#
<6,24>
CLKRUN#

+3VPCU_EC

500mA

0.1U/10V_4
0.1U/10V_4
0.1U/10V_4
0.1U/10V_4
0.1U/10V_4
0.1U/10V_4
0.1U/10V_4
0.1U/10V_4
0.1U/10V_4

1

C431
C414
C445
C473
C411
C448
C472
C422
C423

U12

+3V

<24>

R319
R366
R365

*10K_4
4.7K_4
4.7K_4

GPIO33_EC
GPUT_CLK
GPUT_DATA

R373
R368
R367

4.7K_4
4.7K_4
4.7K_4

DGPU_PROCHOT_EC#
MBCLK2
MBDATA2

GND1
GND2
GND3
GND4
GND5
AGND

AC_PRESENT_EC

HWPG

<6>

C413

*10P/50V_4

MBCLK

C481

*10P/50V_4

MBDATA

C480

*10P/50V_4

GPUT_CLK

C477

*10P/50V_4

GPUT_DATA

C476

*10P/50V_4

BIOS_CS#
BIOS_SPI_CLK
BIOS_WR#
BIOS_RD#

+3VPCU

R306

47K/F_4

C433

Close to BIOS
R286
15/F_4
R298
15/F_4
R310
15/F_4
R314
15/F_4

PCH_SPI_CS0#_R
PCH_SPI1_CLK_R
PCH_SPI1_SI_R
PCH_SPI1_SO_R

<7>
<7>
<7>
<7>

0.1U/10V_4

*0_6/S
C410

KB9010QF C4

*10P/50V_4

C478

C

0.1U/10V_4

3920_RST#

R818

C479

MBDATA2

*22P/50V_4

*0_4/S

SI modify to short pad
11
24
35
94
113
69

MBCLK2

*10P/50V_4

R288

*10_4

DGPU Thermal protect

CLK_24M_KBC

SI modify to short pad

Need Change New PN
CRY2

R281

*0_4

PCH_SUSCLK

+3VPCU

2

R282
*100K_4

C630
0.1U/10V_4

R372

GPIO42_EC

R360

*10K_4

UMA Low ==>( 65W)
<2>

FOR SG/DIS
DGPU_PWROK

10K_4

DIS Hi ==> ( 90W )

1

1

C631
0.1U/10V_4

1

2

THRM_MOINTOR1

D

Adapter select for EC

<6>

2

THRM_MOINTOR

R320

*0_4/S

EC_PECI

R315

43_4

H_PECI (50ohm)
Route on microstrip only
Spacing >18 mils
Trace Length: 0.4~6.125 iches

EC_GPXD1

<4,7,10,11,26,30,33,35>
<6,7,8,9,10,11,12,13,14,15,16,17,19,20,21,22,23,24,25,26,32,33,34>
<4,7,21,24,25,26,28,29>

D

DEL Temp Fail 0314
EC_PECI_R

352-(&78
4XDQWD&RPSXWHU,QF

+1.05V
+3V
+3VPCU

Size
Custom

Document Number

1

2

3

4

5

6

7

Rev
1A

;<ϵϬϭϬY&ϰͿ

Date: Friday, April 26, 2013

Sheet

27
8

of

40

3

2

1

CN10
*PMPCRF-08MLBK2ZZ4H0
1
2 1
3 2
SMD
4 3
SMC
4

BATT+
+PRWSRC

4

BQACDRV

<27>

<27,33>

ACIN

5

BTST

PU2

ACPRES

PR57

BQVCC

20

22_8
PC50
0.47U/25V_6

PR66
75K/F_4

MBDATA

AD_AIR

MBCLK

PR43
*0_4/S
PR41

BQDATA

8

BQCLK

9

*0_4/S

PC134
0.1U/10V_4

VCC

SDA
SCL

6

Place this cap
close to EC

BATDRV

PR42
17
BQB_2

PD2
BQB_1

0_6

19

BQPHASE

15

BQLODRV

2

4

PDZ5.6B

1

1

PC5
*100P/50V_4

2

PDZ5.6B

REGN6V

RB501V-40

PC39
0.047U/25V_4

EC28

EC27

EC25

EC26

Place this cap
close to EC

1

C

+BATCHG

PR50
RC1206-R020
F3_2X1_65-2_8
PL4
BQLR
4.7uH/5.5A(EM-47AM05V08)

PQ8
NTTFS4C25N

14
21
22
23
24
25

2

PR5
*2.2_6
PR51
*0_2/S

4
PC37

13 BQSRP

PR40

0.1U/25V_4
0_4/P

12 BQSRN

PR36

0_4/P

PR49
*0_2/S

PC11
*2200P/50V_4

PC53

PC47

PC6

PC7

PD7
SX34
CSOP
CSON

PC36

11 BQBATDRV

B

PC35
0.1U/25V_4

BQIOUT

PR60
12.4K/F_4

SRP
SRN
IOUT

PR45

1N4448WS-7-F

GND
GND
GND
GND
GND
GND

7

2

LODRV

BQ24738

100K/F_4

ILIM

1

+VAD

10

+VA

PD6

ACDET

+VA_AIR

4

BQHIDRV

3
2
1

16

ACDRV

PHASE
ACIN

PQ12
NTTFS4C25N

18

1

REGN6V
100K/F_4

PC4

8
7
6
5

0.1U/25V_4

BQACN

CMSRC

HIDRV

PR58

PQ15
DRC5144

PC10

0.1U/25V_4

MBATLED0#

1U/16V_4

PC8

<27>

PC123

8
7
6
5

+5VPCU

PC38

3
2
1

3

BQCMSRC

PC9

TEMP_MBAT

1K/F_4
PC2

0.1U/25V_4

3

PR73

SYS_I
PC138

<27>

+BATCHG

PR69
470_8

<27>

PQ7
2N7002K

BATSHIP

2

1

1

PR72
1M_4

PR44
10/F_4
PC40

Place this cap
close to EC

2

1M_4
+3VPCU
<4,7,21,24,25,26,27,29>
+5VPCU
<13,29>
BATT+
<24>
+PRWSRC
<24>

PR37

+3VPCU

MIN. BATV=7.2V
+PRWSRC

PR38

0.01U/50V_4

PC49

100P/50V_4

3

PR53
88.7K/F_4

*0.1U/50V_6

PR54
69.8K/F_4

ACDET=13V

100K/F_4

430K/F_4

*100K/F_4

PR52
+VAD

3

2

1

2

PR14
2.43K/F_6

PC14

1

0.1U/25V_4 0.1U/25V_4

PC52

REGN

3

1

ACN

PQ17 1

3
1M_4
2N7002K

PC54

ACP

2

+12VALW

PC51

BQACP

2

REGN6V
PQ23
DRC5144

PR17

S

D

*1U/25V_4

PC64

2

+VA

PD4

*100P/50V_4

1K_6

<27>

*10U/25V_8

PR12

0.1U/25V_4

1

PR56
4.02K/F4

PR4
PD3

1000P/50V_4

MMDT2907A

PR55
2K/F_4

PR48
*0_2/S

*10U/25V_8

IDEA_G

Q2

6

PR46
*0_2/S

14"

PR3
200K_4

MBCLK

*10U/25V_8

2

PD9
P4SMAJ20A

1M_4

2200P/50V_4

220K_4

PR16
1M_4

PR15

4.7U/25V_8

+5VPCU

3

MBATLED0#
PQ16
DRC5144

PR2
330_4

MBDATA

<27>

2

5

PR13

AC_LED_ON#

<27>

*10U/25V_8

3

PR19

PR20
220K_4

2

1

*0.1U/25V_4

PQ22

4

2.43K/F_6

PC13

<27>

PR1
330_4

CSIN

3

1

CN11
PMPCRA-08MLBK2ZZ4H4
D
1
2 1
3 2
SMD
4 3
SMC
4
5
6 5
B_TEMP_MBAT
+3VPCU
7 6
10
8 7 10 9
8 9

PC1

2

Place this ZVS close to
Far-Far away +VIN

CSIP

1

3
PQ18
2N7002K

+VAD

Q1

1M_4

2

PR18

PC48
2200P/50V_4

10
9

10U/25V_8

BATDIS_G

PC3

+VIN

Ϯϴ

BATT+

80/5A

1

PQ21
DRC5144

+12VALW

3
2
1

BATDIS_ID_DOD
2K/F_4

PR47
RC1206-R010
1

15"

80/5A
PL1

5
6
7 10
8 9

10U/25V_8

PC99
*2200P/50V_4

2

To PWR LED

*0.1U/25V_4

BQBATDRV

PC102

AC_LED_ON#

B

5

PL2

0.1U/25V_4

PC97

0.1U/25V_4

DC-IN CONN

C

*1U/25V_4

P4SMAJ20A

PQ27
QM3016D
4
3

*1U/25V_4

*1U/25V_4

+VAD

2

+BATCHG

PQ2
TPCA8064-H

EC23

0.1U/25V_4

PC16

0.1U/25V_4

7

3
4

1

EC22

PR39

PC15

LED2 GND
GND
LED1

1
2
3

EC24

G

80/5A

GND

PD8

5
6
7
8

80/5A
PL6

EC21

1

1
2

0.1U/25V_4

AD_ID

PQ19
EMB20P03V

PL5

4

5

+VA

CN12

VDD
VDD

Place this ZVS close to
Diode away +VIN

<27>

+VA_AC

0.022U/50V_6

AD_ID

D

8

5
6
7
8

B_TEMP_MBAT

DC_JACK
90W

6

Do Not add test pad on BATDIS_G signal

0.1U/25V_4

EC2
1000P/50V_4

0.01U/25V_4

4

0.01U/25V_4

5

PQ13
2N7002K
A

3

A

+VA_AIR

PR59

2

PQ9
METR3904-G

1M_4

1

352-(&78
4XDQWD&RPSXWHU,QF

PR311
1M_4
Size
Custom

Document Number

5

4

3

2

Rev
1A

ŚĂƌŐĞƌ;YϮϰϳϯϴͿ

Date: Friday, April 26, 2013

Sheet
1

28

of

40

5

4

3

2

1

DC/DC +3VS5/+5VS5

29

D

D

+VIN

+VIN_5VS5

Place these CAPs
close to FETs

PL20
*0_8/S

Place these CAPs
close to FETs

Rds(on) 14m ohm

PR185

0_4/P

PGOOD 23

PGOOD

HWPG

4.7U/6.3V_6

8
7
6
5

3
LGATE2
OUT2
FB2

0.1U/25V_4

11

3V_PHASE2

12

3V_LGATE2

2
+3.3V_ALWP

PR166
*2.2_6

7

PR180
*0_2/S

4

3V_FB2

+
PC184

PQ51
MDV1595SURH

PC194

PR179

PR193
80.6K/F_4

PL18
2.2uH/8A(EM-22AM05V04)

5

1

PJP4
*POWER_JP/S

3
2
1

2.2_6

PC206

1

PHASE2

PR184

8
7
6
5

17

LGATE1
VOUT1
FB1

REF

VREG5

4.7U/6.3V_6

8
VREG3

16
PHASE1

4

3V_UGATE2

Rds(on) 14m ohm

*0_2/S

0.1U/10V_4

<4,11,27,30,31>

10K_4

PU9
RT8223P

10
9

3
2
1

+3VS5

BOOT2

1

PC202

PR186

PQ49
MDV1595SURH

UGATE2

BOOT1

C

+3VS5

PQ52
NTTFS4C25N

4

*2200P/50V_4

5V_FB1

4

PR192
15.4K/F_4

24
2

TONSEL

SKIPSEL
GND
GND

5
6
7
8

PR170
*2.2_6

1
2
3

0.1U/10V_4

5V_LGATE1 19

UGATE1

ENC

5V_PHASE120
2.2uH/8A(EM-22AM05V04)

*2200P/50V_4

1
220U/6.3V_6X4.5
2

22

2.2_6

+5V_ALWP

PR191
10K/F_4

5V_BST1

PC214

+3.3 Volt +/- 5%
Countinue current:4A
Peak current:6A
OCP minimum:7.5A

PR187
*0_2/S

14
25
15

0.1U/25V_4

5V_UGATE121
PR183

EN0

18

1
2
3

1

PC205

13

ENTRIP2

4

PL17

8205EN

VIN

PR182
*330K/F_4

PJP3
*POWER_JP/S

PC182

PC210

+5VPCU

PC217
1U/6.3V_4

6

2

PQ50
NTTFS4C25N

ENTRIP1

5
6
7
8

PR181
*665K/F_4

0.1U/25V_4

PC200

+5VS5

+

PC216

PC209

C

PC183

+2VREF

PC215

PR190
6.8K/F_4

PC203
220U/6.3V_6X4.5

0.1U/25V_4

+5 Volt +/- 5%
Countinue current:4A
Peak current:6A
OCP minimum:7.5A

+3VPCU

PC218

0.1U/25V_4

2200P/50V_4

+5VPCU

2

4.7U/25V_8

+VIN

PC197

*0_2/S

+VIN
PL19
*0_8/S

PR173
10_8

PR150

+VIN_3VS5

4.7U/25V_8

PC211

4.7U/25V_8

PC208

2200P/50V_4

PC207

0.1U/25V_4

PC204
4.7U/25V_8

0.1U/25V_4

PC213

PR188
90.9K/F_4

B

B

PR189
10K/F_4
PR178

0_4/P

S5_ON

S5_ON

<27>

PC201
*1000P/50V_4

A

A

352-(&78
4XDQWD&RPSXWHU,QF
Size
Custom

Document Number

5

4

3

2

Rev
1A

3/5VPCU(RT8223P)

Date: Friday, April 26, 2013

Sheet
1

29

of

40

5

4

3

2

1

30
D

D

+VIN_1.05V
PU5

<4,11,27,29,31>

HWPG

HWPG

PR307

BST
PGOOD
SW
SW
SW
SW

NB671PGPCH

*0_4/S

PC116

PC118

PC115

PC120

+1.05V

2

PC114

+1.05V_S2

PC287
NB671BSTPCH_S

PR303
10 NB671BSTPCH
0_6

PL13

0.1U/25V_4

8 NB671SW
9
15
16

PJP2
*POWER_JP/S

1

2

NC

PR305
*0_4

4

14

1uH/11A(EM-10AM05V06)
PR101
*2.2_6

1

PGND

0.1U/25V_4

5

NC

*0_8/S
2200P/50V_4

AGND
3

+VIN
PL11

1

4.7U/25V_8

VIN

4.7U/25V_8

NC

0.1U/25V_4

6

+1.05V Volt +/- 5%
Countinue current:4A
Peak current:7.7A
OCP minimum:9A

FB

C

PR302
16.2K/F_4

NB671

*0.1U/25V_4

PC163

12K/F_4

PC292

B

PR304

12 NB671FBPCH

PC167

*22U/6.3V_8

EN

PC166

*22U/6.3V_8

13

0_4/P

PC164

*22U/6.3V_8

MAINON PR306

NB671VOUTPCH

PC165

22U/6.3V_8

MAINON

7

PC149

22U/6.3V_8

<27,30,31,33>

VOUT

PC148

22U/6.3V_8

PC124
*2200P/50V_4

1U/6.3V_4

C

PC154

0.1U/10V_4

PC291

2

PR122
*0_2/S

VCC

*330U/2.5V_6X4.5ESR12

+

11

+1.5V +/- 5%
Countinue current:1.3A
Peak current:1.5A
OCP current:2A

PR153
*0_6/S
+3VS5

4

4.7U/6.3V_6

PC181

B

+1.5V

0_4/P

5

MAINON PR159

0_4/P

1

VIN

PU8
PR161

HWPG

PG

LX

3

PL16
8008LX1.5V
2.2uH/1.3A_2520
PR145

GND

*0_2/S

6

0.1U/10V_4

PC189
AWP8824CTI

2

R1
8008VFB1.5V

PR163

PC177

PC178
0.1U/10V_4

EN

10U/6.3V_6

MAINON

FB

<27,30,31,33>

+VIN
<20,24,28,29,31,32,33,34,35,36>
+3VS5
<6,9,10,11,24,26,29,33,35>
+5VS5
<13,21,24,25,29,31,32,33,34,36>
+5VPCU
<13,28,29>

15K/F_4

R2

PR164
10K/F_4

VO=(0.6(R1+R2)/R2)
A

A

352-(&78
4XDQWD&RPSXWHU,QF
Size
Custom

Document Number

5

4

3

2

Rev
1A

+1.05V (NB671)/1.5V

Date: Friday, April 26, 2013

Sheet
1

30

of

40

1

2

3

4

5

31
A

A

+1.35VSUS

+VIN_DDR

( VTT/2A )

5

DDR_VTTREF

MAINON

PR32

<4,11,27,29,30>

DRVL

51216S3 17

SUSON
HWPG

0.1U/25V_4

2
PJP5
*POWER_JP/S

+1.35VSUS_S

PL21
0.82uH/13A(EM-82BM05V04)

0.1U/25V_4

13 51216SW

51216SW

SUSON PR29

0_4/P

16
51216S5

HWPG

0_4/P

20
51216PG

PR35

PGND

51216TRIP 18

47K/F_4

12

+5VS5

VDDQSNS
S5

1U/6.3V_4

10

B

9

PQ54
MDV1595SURH

51216VDDQSNS

PC221
*2200P/50V_4

6

TRIP

PC32
0.1U/10V_4

MODE
REFIN

+
PR194
*0_2/S

4

+1.8VREF

PGOOD

8

Rds(on) 14m ohm

PC220

PC219

PR34
10K/F_4

51216REFIN

V5IN
APW8819QAI

PC29

PR195
*2.2_6

S3

VREF
PR30

120K/F_4
PR33
51216MODE19

11 51216DRVL

1

PC33
0.22U/10V_4

0_4/P

<27,33>

2.2_6

+1.35VSUS

2

MAINON

SW

PR28

PQ53
NTTFS4C25N

0.1U/10V_4

<27,30,33>

PC226
*0.1U/10V_4

51216S3

VTTREF

4
PC28
51216VBST_S

330U/2.5V_6X4.5ESR12

<13>

15 51216VBST

PC25

8
7
6
5

*100/F_4

VBST
GND

PC224

3
2
1

<12,13>

GND

PC223

1

21
PR197

14 51216DRVH

PC26

2200P/50V_4

VTTGND

PC27

4.7U/25V_8

*10U/6.3V_6

DRVH
7

2

4.7U/25V_8

VLDOIN

VTTSNS

0.1U/25V_4

4

VTT

8
7
6
5

1

PC225

3
2
1

3
PC34
10U/6.3V_6

B

+1.35V +/- 5%
Countinue current:6A
Peak current:10A
OCP minimum:12A

*0_8/S
PU1

( 3mA )

+VIN
PL22

+1.35VSUS

+0.75V_DDR_VTT

PC31
0.01U/25V_4

+0.675V_DDR_VTT

<2,4,12,13,24>

PR31
31.6K/F_4

C

C

D

D

352-(&78
4XDQWD&RPSXWHU,QF
Size
Custom

Document Number

1

2

3

4

Rev
1A

Zϯ;WtϴϴϭϵͿ

Date: Friday, April 26, 2013

Sheet
5

31

of

40

4

3

2

1



1

Place close
to inductor

PC187

PR158

D

2

TH05-3L104FR

1

2

PC212
*15U/25V

+
PC41
*15U/25V

2

+
PC42
100U/25V

2

1

1

1

+
PC43
100U/25V

0.1U/25V_4

2200P/50V_4

PC222

C

PL15
81101_PH
0.36uH

PQ37
RJK03S3DPA

PC132
PR116
*2.2_6

1K/F_4

PC140
*2200P/50V_4

PC176
0.01U/50V_4

PC151

+VIN_VCC_CORE

PR128

*0_2/S

PR127

*0_2/S

*22U/6.3V_8

+VIN_VCC_CORE

PC117

*22U/6.3V_8

VR_RDY

SCLK

ALERT#

SDIO

PR138

PC113

+VCC_CORE

9

81101VRMP

PC125
*4.7U/25V_8

81101_LG

PC122

5

12

6

81101_PH 0.22U/25V_6

7

81101_BST

1

PC168

8
10

2

11

PC119

4.7U/25V_8

81101_HG_G

4.7U/25V_8

1_6

VRMP

VR_RDY

+

0.01U/25V_4

7

6

PR140

8

*0_4

8.25K/F_4

100K/F_4

15
PVCC

IMAX
SCLK

ALERT#

PC169

81101_HG

0.1U/25V_4

1000P/50V_4

PR147

CSREFPC179

16

CSSUM

18

17
CSREF

CSSUM

CSCOMP

19

1

1U/6.3V_4

TSENSE

*0_8/S

PR26

10/F_4 CSREF
SWN

81101_PH

9

Icc_Max=32A
I_TDC=14A
I_Dynamic=27A
V_Operate=1.6V~1.8V
DC_LL=2m
AC_LL=7m
AC_LL_VOS=9.4m
VBOOT=1.7V

2

0_4/P

B

5

PQ1
*RJK03S3DPA

6

8

*10K/F_4

7

PR137

+3V

S2

0_4/P

PR142

IMVP_PWRGD

S2

PR146

VR_SVID_CLK
IMVP_PWRGD

D1

0_4/P

S2

0_4/P

PR149

D1

PR151

G2

VR_SVID_DATA
VR_SVID_ALERT#

1

81101_HG_G

D1

SDIO
ALERT#
SCLK

PR156

0_4/P

<4>
<4,6>

0_4/P

+VIN

69.8K/F_4

S1/D2

PC190
0.1U/10V_4

13
9

PR143

G1

PR141
54.9/F_4

LG

VBOOT

*75/F_4

H_PROCHOT#

H_PROCHOT#

<4>
<4>

SW

PR154

<2,27>
B

VSP

14

S2

PR155

+V1.05S_VCCST

+V1.05S_VCCST

POP for DIS

S2

H_VR_ENABLE_MCP

BST

GND

1.75V

S2

<4>

PR160

VRON

PGND

VSN

VCC

90.9K

Place close
to MOSFET

G2

<27>

PR144
*75/F_4

29

PC192

PR27
*0_4/S

PU7
NCP81101MNTXG

SDIO

28

2.2_6

HG

5

81101VCC

PR171

+5VS5

1.7V

PR119

PL12

TSENSE

DIFFOUT

1.65V

69.8K

PR136

+VIN_VCC_CORE

FB

4

27

49.9K

D1

26

81101VSP

0V

D1

81101VSN

0_4/P

30.1K

S1/D2

25

PC195
1000P/50V_4
PR174

PR148
130/F_4

81101DIFFOUT

COMP

VR_HOT#

24

+5VS5

VBOOT

3

23

81101FB
0_4/P

PC170
2.2U/6.3V_6

V_boot

D1

VSS_SENSE
VCC_SENSE

PR172

Boot Voltage Table

R_boot

G1

<4>
<4>

0_4/P

CSCOMP

IOUT
81101COM
*2200P/50V_4
PR175

ROSC

ENABLE

81101ROSC 22

PC193
C

1

15.4K/F_4

22.6K/F_4
PR167
18.7K/F_4

Rb

0_4

81101ILIMPR165

PR176

81101IOUT PR162

PR177
6.04K/F_4

20

Ra

*1500P/50V_4

21

1K/F_4

ILIM

10P/50V_4
PC199

PR169

PC191

2

330P/50V_4

SWN

64.9K/F_6

VR_HOT#

PC196

D

PR139
0_4/P

PR152

470P/50V_4

PC198

PR168
49.9/F_4

TSENSE

165K/F_4

1500P/50V_4

POP Rb and
no POP Ra
for nex
version.

PR131
220K_6 NTC

2

PR157
75K/F_4

*680P/50V_4
PC188

2

5

81101_LG

PC133

PC135

PC139

PC129

PC152

PC153

*22U/6.3V_8

*22U/6.3V_8

*22U/6.3V_8

*22U/6.3V_8

*22U/6.3V_8

*22U/6.3V_8

+VCC_CORE

A

A

352-(&78
4XDQWD&RPSXWHU,QF
Size
Custom

Document Number

5

4

3

2

Rev
1A

CPU Core (NCP81101)ULT

Date:Friday, April 26, 2013

Sheet
1

32

of

40

5

4

3

2

1

ϯϯ
+VAD

PR118
22_6
D

D

<27>

LAN_POWER

1U/35V_6

16
DCAP

PC142

CP

VOUT

18 G5934CP

PC143
ACIN

<27,28>

0.47U/25V_6
PR121
*0_4

D_CAP

1

CN

VIN

19 G5934CN

20 G5934VIN

PC145
0.1U/25V_4

17 G5934VOUT

PC144
0.1U/25V_4
2
1

ON1

PG

ON2

VSENSE

15

G5934PG

14

G5934VSENSE

+VAD

PR123
*750K/F_4
<27,30,31>

2

MAINON

MAINON

+12VALW

PU6
G5934RZ1U
<27,31>

PR125

SUSON

3

0_4/P

ON3

REG

PR126
*100K/F_4

13

PC150
1U/16V_4
4

MAINON

ON4
DISC3

+3VSUS

0_4/P

+5V

21

PC159
0.1U/10V_4

4

MAIND

$
PC156
2200P/50V_4
PR133
0_4/P

PC171
*10U/6.3V_6

*10U/6.3V_6

PC158

C

+5VS5

GND

DRIVER2
10

DRIVER1

DISC4

0_4/P

G5934DISC2 PR135

3
2
1

1
2
3

G5934DISC3 PR134

6

PQ47
NTTFS4C25N

for +1.05V_MODPHY timing(64us)
PC155
0.1U/10V_4

7

8
7
6
5
MAIND3.3V

PC162
0.022U/25V_4

+3V

DISC2

G5934DISC4

4

$

9

PQ45
NTTFS4C25N

12

PC172
0.1U/10V_4

8

5
6
7
8

DISC1

DRIVER3

+3VLANVCC

+3VS5

5
G5934DISC1

0_4/P

11

PR129

DRIVER4

C

+3V

+5V

PC175
0.1U/10V_4

+12VALW

+1.05V

+1.05V_MODPHY

+3VLANVCC
<9>

3

3

2

PR106
1M_4

2

$
+1.05V_MODPHY
PL14

*10U/6.3V_6

PC185
0.1U/10V_4

PQ35
BSS138W

1

PC186

+1.05V

*80/5A
PC141
0.1U/10V_4

PC160
*10U/6.3V_6

0.1U/10V_4

PC157

MPHY_PWREN

PC137
0.01U/25V_4

PC180
2200P/50V_4

PQ41
2N7002K

1

PC161
2200P/50V_4

2
3

LAN_ON

PQ34
*2N7002K

1

1
2
5
6

PQ46
EMB32N03K

$

3

SUSD

4

6
5
2
1
3

4

+3VSUS

0.1U/10V_4

$

PC173
0.1U/10V_4

PC23
0.1U/10V_4

4

1.05VMOD_OND

PR105
1M_4

PQ48
EMB32N03K

PC174

B

PR113
PQ42
1M_4 LQ3E070BNFU7TB

PR117
*22_8

1.05VMOD_ONG

PC147

PC24
0.1U/10V_4

+3VS5

*10U/6.3V_6

MAIND
+3VS5

8
7
6
5

+VIN

3
2
1

B

for +1.05V_MODPHY timing (64us)
<6,7,8,9,10,11,12,13,14,15,16,17,19,20,21,22,23,24,25,26,27,32,34>
+3V
<6,20,21,23,24,25,26>
+5V
<20,24,28,29,30,31,32,34,35,36>
+VIN
<6,9,10,11,24,26,29,30,35>
+3VS5
<13,21,24,25,29,31,32,34,36>
+5VS5
<23,28,35>
+12VALW
<22,26>
+3VLANVCC
<12,13,31>
+0.75V_DDR_VTT

A

A

352-(&78
4XDQWD&RPSXWHU,QF
Size
Custom

Document Number

5

4

3

2

Rev
1A

ŝƐͲĐŚĂƌŐĞ/;^>'ϱϱϰϰϴͿ

Date: Friday, April 26, 2013

Sheet
1

33

of

40

5

4

3

2

1

ϯϰ

VGA Core
PU3

RT8813A

+VIN_VGACORE

+VIN

D

D

PL3

5

D
TON

BOOT1

1

G
S

8813BOOT1
0.22U/25V_6
8813PHASE1

D

10K/F_4

16

PGOOD

LGATE1

23

4

8813LGAT1

RB501V-40
<8,15,35>

DGPU_PWR_EN

PR65

4

S

PQ20
TPCA8A10-H
PR77
16.2K/F_4

2
8813EN

3

47K/F_4

EN

VCC/ISEN1

PQ3
*TPCA8064-H

D

G

PC45

PC58

PL8

15

8813ISEN1

PR87

10K_4/P

PR75
*2.2_6

G
S

PQ14
*TPCA8A10-H

1
2
3

PD5

1

PC44

1
2
3

+3V

PC46

S

5
PR86

DGPU_VC_EN

PC61

0.36uH

1U/25V_6

<15,35>

PC56

G

5

PHASE1

24

4
8813UGATE1_1
PQ4
TPCA8064-H

1
2
3

8813TON 9

499K/F_4

PC66

4

PC65

PR78

PR76
1_6

1
2
3

+VIN_VGACORE

PC55

D

2

1_6
PC68
2.2U/10V_6

1

*0_8/S

5

*0_6/S

8813UGATE1_1

0.1U/25V_4

PR67

2200P/50V_4

8813UGATE1

0.1U/25V_4

2

*4.7U/25V_8

UGATE1

4.7U/25V_8

PVCC

4.7U/25V_8

8813PVCC 21

4.7U/25V_8

PR83
+5VS5

PC62
*2200P/50V_4

+5VS5

PC79
PC59
*2200P/50V_4

+VIN_VGACORE

PSI

D
VID

4

G
S

PC71

PQ26
TPCA8A10-H

REFADJ
PR196

PR64
2K/F_4

TALERT/ISEN2

14

*0_4/P

8813ISEN2
PR198

8813REFIN7

DGPU_PROCHOT_EC#
PR88
30K/F_4

0_4/P

PQ25
*TPCA8A10-H

<17,27>

PC104
*2200P/50V_4

+3V

DGPU_PROCHOT#

<27>

1

1

1

+

+

PC91

PC110

PC112

2

2

S

+
PC111

2

PC101

REFIN

B

PR68
18K/F_4

S

+

+

G

*330U/2.5V_6X4.5ESR12

PC57
2700P/50V_4

4

330U/2.5V_6X4.5ESR12

8813REFADJ 6

20K/F_4

G

PR99
*2.2_6

1
2
3

PR63

LGATE2

4

8813LGAT2

D

2

0.36uH

D
20

2&3PLQLPXP$
+VGACORE

VREF

PC60
0.1U/10V_4

1
2
3

PR74
20K/F_4

3HDNFXUUHQW$

330U/2.5V_6X4.5ESR12

PHASE2

&RXQWLQXHFXUUHQW$

PC87

PL10

5

8813VREF 8

PQ24
*TPCA8064-H

PC86

1

0.22U/25V_6
8813PHASE2

PQ28
TPCA8064-H

PC92

2

19

8813VREF

S

PC84

1

8813BOOT2

G

PC90

*330u_2V_7343

18

1
2
3

BOOT2

4
8813UGATE2_1

1
2
3

GPU_VID

5

<17>

PC83

D

2200P/50V_4

5

0.1U/25V_4

4

8813VID

*4.7U/25V_8

8813PSI

0_4/P

4.7U/25V_8

0_4/P

PR62

C

8813UGATE2_1

1_6

4.7U/25V_8

PR61

8813UGATE2

5

PSI

17

4.7U/25V_8

UGATE2
<17>

13*9

0.22U/10V_4
PR85

330U/2.5V_6X4.5ESR12

for VGA sequence

5

C

VSNS

PC63
*0.01U/16V_4

11

PR84

8813VOUT1
PC70
56P/50V_4

RGND

PR70
0_4/P

10

B

+VGACORE
*0_6/S
PC69
*100P/50V_4

8813RGN
PC67

PR81

PR82

100/F_4
VGPU_CORE_SENSE

0_4/P

VSS_GPU_SENSE

<14>
<14>

PR80
100/F_4

56P/50V_4
PC72

SS

12

8813SS

22

PR79
8813PWM3
0_4/P

56P/50V_4

GND/PW M3
PR89
8813VREF
PR71

1

324/F_4

2

PR90
0_4/P

8813ISEN3 13

TSNS/ISEN3

GND

25

10K/F_4 NTC
100P/50V_4

PC80

A

A

352-(&78
4XDQWD&RPSXWHU,QF
Size
Custom
Date:
5

4

3

2

Document Number

Rev
1A

+VGACORE (RT8813A)
Friday, April 26, 2013
1

Sheet

34

of

40

1

2

3

4

5

6

7

8

ϯϱ
A

A

+12VALW
+3V_GFX

+VGACORE

+3VS5

+VIN

3

3

3

PQ59
2N7002K

PQ62
2N7002K

$

+3V_GFX

for VGA sequence

PC325
*10U/6.3V_6

PC337
0.1U/10V_4

1

1

PR290
1M_4

2

1

PR291
DGPU_PWR_EN

PC343
180P/50V_4

2

3

2

PQ60
2N7002K

PC346
0.1U/10V_4

3

3VGFX_OND

2

<8,15,34,35>

PQ61
EMB32N03K

1
2
5
6

PR130
1M_4

PR296
22_8

4

PR299
22_8
PR295
1M_4

PC293
*1U/16V_4

PQ63
LTC044

1

0_4/P
3VGFX_ONG

B

B

+12VALW

+VIN

PQ38
MDU1512RH

PR109
1M_4

PR23
22_8

D

PQ31
LTC044

1
2
3
1

1

PQ33
2N7002K

PC22
*10U/6.3V_6

PC20
0.047U/25V_4

$

+1.05V_GFX

for VGA sequence
PR24
1M_4

PQ32
2N7002K

1

*0_4/P

2

S

2

3

PR22

DGPU_VC_EN

2

<15,34>

110K/F_4

1

C

DGPU_PWR_EN

PC136
0.1U/10V_4

G

PC127
1000P/50V_4

2

PR21
<8,15,34,35>

4

3

3

1.05VGFX_OND
PR25
1M_4

5

+1.05V

+1.05V_GFX

PC21
0.1U/10V_4

C

D

D

352-(&78
4XDQWD&RPSXWHU,QF
Size
Custom

Document Number

1

2

3

4

5

6

7

Rev

1.05V_VGA/3V_VGA

Date:Friday, April 26, 2013

1A

Sheet

35
8

of

40

5

4

3

2

1

36
+VIN_1.5VGA
PR241

PC78

4.7U/25V_8

4.7U/25V_8

2200P/50V_4

0.1U/25V_4

+1.5V_GFX

2

PC252
PR229
RT8238BST_1_1.1V
RT8238BST1.1V

2

RT8238LX1.1V

1

RT8238DL1.1V

1

PL9

0.1U/25V_4

1uH/11A(EM-10AM05V06)

1

PR98
*2.2_6

*100P/50V_4

RDSon=13m ohm

PR239

PC74

PC73
*22U/6.3V_8

PC98
*2200P/50V_4

PC250

PC85

*22U/6.3V_8

Vo=0.5(R1+R2)/R2

PQ66
MDV1595SURH

PC106

330U/2.5V_6X4.5ESR12

+
PR100
*0_2/S

4

2

LGATE

0_4/P

PJP1
*POWER_JP/S

+1.5VGFX_S2

0.1U/10V_4

PR308

+5VS5

PC82

0.1U/25V_4

RT8238TON1.1V

11

8
7
6
5

RT8238VCC1.1V

PHASE

12

0.47U/6.3V_4
C

RT8238DH1.1V

4

2_6

EN
PAD

3

FB

13

PC249

PC81

3
2
1

UGATE

RT8238FB1.1V 6

8
RT8238EN1.1V

PC89

4

9
RT8238HWPG_S2A1.1V
RT8228A
PGOOD

0_4/P

MODE

PR96
DGPU_FB_EN PR231
30K/F_4

GND

DGPU_PWROK

DGPU_FB_EN

PC88

PU12

BOOST

7

<9,16,27>
<15>

CS

PQ65
NTTFS4C25N

D

8
7
6
5

10
RT8238ILIM1.1V

+1.5V Volt +/- 5%
Countinue current:6A
Peak current:8A
OCP minimum:12A

*0_8/S

360K/F_4

TON

PR310
127K/F_4

5

1U/6.3V_4

PC251

VCC

10_6

+VIN
PL7

PR309

+5VS5

3
2
1

D

C

20K/F_4
PR240
10K/F_4

+1.5V_GFX
B

B

+VIN

3

PR115
*22_8
PR120
*1M_4

3

2

*0.47U/6.3V_4

PC146

2
PQ40
*DRC5144

1

PR114
*1M_4

PQ39
*2N7002K

1

RT8238EN1.1V

A

A

352-(&78
4XDQWD&RPSXWHU,QF
Size
Custom

Document Number

5

4

3

2

Rev
1A

нϭ͘ϱsͺs';ZdϴϮϮϴͿ

Date: Friday, April 26, 2013

Sheet
1

36

of

40

1

2

3

4

5

6

7

Power control pin

SATA Master

USB2.0/USB3.0 COMBO 1st

USBPW_ON#(from EC)

SATA0

HDD

N/A

USB2.0/USB3.0 COMBO 2nd

USBPW_ON#(from EC)

SATA1

mSATA

N/A

SATA2

NC

N/A

USB3.0

Port Assignment

PORT1

Port Assignment

8

Power control pin

A

A

PORT2
PORT3

NC

N/A

PORT4

NC

N/A

SATA3/PCIE

PCIE
Port Assignment

PORT0

USB2.0/USB3.0 COMBO 1st

USBPW_ON#(from EC)

PORT1

USB2.0/USB3.0 COMBO 2nd

USBPW_ON#(from EC)

B

PORT2

Camera

N/A

PORT3

NC

N/A

PORT4

NC

N/A

PORT6

Left side USB daughter B

Control pin

PCIE 5_L0

PEG0

PCIE 5_L1

PEG1

PCIE 5_L2

PEG2

PCIE 5_L3

PEG3

PCIE 1

NC

PCIE 2

NC

PCIE 3

WLAN

PCIE 4

LAN

B

N/A

WLAN
Touch Screen 15" used

Port Assignment

USBPW_ON#(from EC)

C

PORT7

N/A

Power control pin

USB2.0

PORT5

Card reader

C

TS_ON(from EC)

D

D

352-(&78
4XDQWD&RPSXWHU,QF
Size

Document Number

Date: Friday, April 26, 2013
1

2

3

4

5

6

7

Rev
1A
Sheet

37
8

of

40

1

2

3

4

5

+3V_DEEP_SUS

2.2K

6

+3VSUS

2.2K

AP2 SMB_PCH_CLK

2.2K

+3VSUS
2N7002KDW

AH1 SMB_PCH_DAT

7

+3V

2.2K

8

+3V

*4.7K

*4.7K 4.7K

4.7K

TP_SMB_CLK

1

TP_SMB_DATA

2

Touch Pad

2N7002KDW
A

A

+3VSUS

Haswell
ULT

+3V
TP_SMB_CLK

2N7002DW

53

TP_SMB_DATA 51

+3V_DEEP_SUS

XDP

2N7002DW

+3V
2.2K

DDR3L DIMM

2.2K

+3V
AU3 SMB_ME1_CLK

*2N7002DW

AH3 SMB_ME1_DAT

0ȍ

*0ȍ

MBCLK2

CSCL1 9

MBDATA2

CSDA1 10

*2N7002DW

*0ȍ

+3V

RTD2132R-CG

0ȍ

+3V

B

B

8

CPU heat pipe local thermal sensor (*G781-1P8)

7

4.7K

4.7K

79

MBCLK2

8

80

MBDATA2

7

DDR thermal sensor (*EMC1412-1-ACZL-TR)

+3VPCU
330
330
4.7K
77

MBCLK

78

MBDATA

4.7K

*short

+3V

SMC

4

SMD

3

BQCLK

9

BQDATA

8

Battery

Charger

*short

C

C

EC
KB9010QF

4.7K

4.7K

83 GPUT_CLK

D9

84 GPUT_DATA

D8

GPU internal thermal sensor (I2C)

+G_SEN_PW

4.7K

4.7K

85 MBCLK3

4

86 MBDATA3

G-sensor (AL003DC2A00)

6

+3VSUS

4.7K

D

4.7K

BLM18BA470SN1D

87 TPCLK

TPCLK-1

88 TPDATA

D

5

TPDATA-1 4

Touch Pad

BLM18BA470SN1D

352-(&78
4XDQWD&RPSXWHU,QF
Size

Document Number

Rev
1A

SMBUS
Friday, AprilDate:
26, 2013
1

2

3

4

5

6

7

Sheet

38
8

of

40

5

4

3

2

1

(+VAD)

Adapter

+PRWSRC
D

D

(+VIN)

Battery

Discharger IC
MAINON

SUSON

VRON

DGPU_PWR_EN

DGPU_FB_EN

SLG55448VTR
AOS
+3VPCU

AOZ1237

Richtek
RT8223P

ANC

ONS

Richtek

APW8819QAI

NCP81101MNTWG

RT8813A

AOS

+1.05V

+1.35VSUS

+VCC_CORE

+VGACORE

MAINON

SUSON

MAINON

AOZ1237

+5VPCU
S5_ON

LAN_POWER

+12VALW

Driver 1

Driver 2

Driver 3

Driver 4

(+3VS5)

(+5VS5)

(+3VS5)

(+3VS5)

+1.5V_GFX

DGPU_VC_EN

+3VLANVCC

C

+3VS5

+5VS5

+5V

+3VSUS

+3V

C

MOS
MDU1512RH

MAINON

DGPU_PWR_EN

USBPW_ON#

SGY

MOS

Power SW

SY8002ABC

EMB32N03K

G547N2P81U

+3V_GFX

+5V_USBP0

+1.5V

+1.05V_GFX

B

B

A

A

352-(&78
4XDQWD&RPSXWHU,QF
Size

Document Number

Rev
1A

Power Block Diagram
Date:
5

4

3

2

Friday, April 26, 2013
1

Sheet

39

of

40

5

+3VS5

4

+3VLANVCC

+3VS5

3

2

+3V

17

2

LAN_POWER

S5 PWR
MOS SW

10

3
MAINON

PWR
BTN

11

+VIN

1

+3VPCU

16

S5 PWR
MOS SW

1

+PWR_SRC

+VIN
+3VS5
+5VS5

3V/5V
VR

+5VPUC

CHARGER

Battery

HWPG
D

+5VS5

+5V

17

D

+3VS5

+3V_GFX

19

S5 PWR
MOS SW

MAINON

S5 PWR
MOS SW

11

DGPU_PWR_EN

3

LATCH
(NBSWON1#)

13

22
15
+3VSUS

+3VS5

S5 PWR
MOS SW

SUS_ON

+1.05V

+1.05V_GFX

9

SUS_ON

9

MAINON

11

VRON

12

LAN_POWER

S0 PWR
MOS SW

4

S5_ON

6

DNBSWON#

5
VCCDSW3_3

10

DGPU_VC_EN

14

EC

PWRBTN#
SLP_S4#

SUSC#

7
8
13

DGPU_PWR_EN

25

DGPU_PWROK

SUSB#

SLP_S3#
GPIO54
GPIO17

PCH

25

C

C

27

DGPU_PWROK

+VIN

+1.5V_GFX

PG
+VIN

GPIO55
HWPG

+VIN

PLTRST#
SYS_PWROK

0ȍ

26

PCH_PWROK
*TC7SH08FU

23

APWROK

IMVP_PWRGD
EC_PWROK

15

9

HWPG

+1.05V
MAINON

1.05V
VR

PLTRST#

EC_PWROK

25

SUS_ON

PG

GPIO7

14

DGPU_PWROK

+1.35VSUS

1.35V
VR

D1/GPXD1

21

DGPU_VC_EN

1.5V
VR

B

17
11

CPU
PG

+3VS5

HWPG

+1.5V
MAINON

LDO

+VIN

20

18

+VGACORE

+VCC_CORE

11

+3V
VR

HWPG

A

IMVP
VR

14
EN

PG

+VIN

17

PG

24

DGPU_VC_EN

DGPU_PWR_EN

EN

B

23

PG

IMVP_PWRGD
A

VRON

13

12

352-(&78
4XDQWD&RPSXWHU,QF
Size
Date:
5

4

3

2

Document Number

POWER UP Sheet
SEQUENCE
of
40
40

Friday, April 26, 2013

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