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R07DS0201EJ0100 Rev.1.00 Page 1 of 15

Jan 25, 2011

Preliminary Datasheet

R2J20656ANP

Integrated Driver - MOS FET (DrMOS)

Description

The R2J20656ANP multi-chip module incorporates a high-side MOS FET, low-side MOS FET, and MOS-FET driver

in a single QFN package. The on and off timing of the power MOS FET is optimized by the built-in driver, making this

device suitable for large-current buck converters. The chip also incorporates a high-side bootstrap switch, eliminating

the need for an external SBD for this purpose.

Features

 Compliant with Intel 6  6 DrMOS Specification.

 Built-in power MOS FET suitable for Notebook, Desktop, Server application.

 Low-side MOS FET with built-in SBD for lower loss and reduced ringing.

 Built-in driver circuit which matches the power MOS FET

 Built-in tri-state input function which can support a number of PWM controllers

 High-frequency operation (above 1 MHz) possible

 VIN operating-voltage range: 27 Vmax

 Large average output current (Max.35 A)

 Achieve low power dissipation

 Controllable driver: Remote on/off

 Zero current detection for a diode emulation operation

 Double thermal protection: Thermal Warning & Thermal Shutdown

 Built-in bootstrapping Switch

 Small package: QFN40 (6 mm  6 mm  0.95 mm)

 Pb-free/Halogen-Free

Outline

Integrated Driver-MOS FET (DrMOS)

QFN40 package 6 mm × 6 mm

(Bottom view)

Low-side MOS Pad

High-side

MOS Pad

Driver

Pad

110

30 21

31 20

VINGHBOOTVCIN

DISBL#

ZCD_EN#

CGND VDRV GL PGND

THWN

PWM

MOS FET Driver VSWH

R07DS0201EJ0100

Rev.1.00

Jan 25, 2011

R2J20656ANP Preliminary

R07DS0201EJ0100 Rev.1.00 Page 2 of 15

Jan 25, 2011

Block Diagram

BOOT GH

GLCGND

VDRV

2 μA

CGND

Driver Chip

High Side

MOS FET

Low Side

MOS FET

VDRV

160 k

VCIN

20 k

35 k

VSWH

PGND

VIN

DISBL#

ZCD_EN#

PWM

Level Shifter

VCIN

UVL

VCIN

Input Logic

(TTL Level)

(3 state in)

THWN THDN

THWN

CGND

Overlap

Protection.

& Logic

Boot

Zero

Current

Det.

Notes: 1. Truth table for the DISBL# pin 2. Truth table for the ZCD_EN# pin

DISBL# Input Driver Chip Status

"L" Shutdown (GL, GH = "L")

"Open" Shutdown (GL, GH = "L")

"H" Enable (GL, GH = "Active")

ZCD_EN# Input Driver Chip Status

"L" "Diode Emulation Mode"

"Open" "Continuous Conduction

Mode"

"H" "Continuous Conduction

Mode"

3. Output signal from the UVL block 4. Output signal from the THWN block

"H"

"L"

UVL output

Logic Level VCIN

VHVL

For active

For shutdown

"H"

"L"

Thermal Warning

Logic Level

(°C)

TwarnHTwarnL

Thermal

Warning

Normal

operating

5. Truth table for the THDN block

Driver IC Temp. Driver Chip Status

< 150°C Enable (GL, GH = "Active")

> 150°C Shutdown (GL, GH = "L")

(latch-off)

R2J20656ANP Preliminary

R07DS0201EJ0100 Rev.1.00 Page 3 of 15

Jan 25, 2011

Pin Arrangement

(Top view)

VSWH

VIN PWM

DISBL#

THWN

CGND

VSWH

VIN

VSWH

PGND

PGND VSWH

VIN CGND

21 22 23 24 25 26 27 28 29 30

10987654321

PGND

VSWH

VIN

VSWH

CGND

BOOT

VDRV

VCIN

ZCD_EN#

Note: All die-pads (three pads in total) should be soldered to PCB.

Pin Description

Pin Name Pin No. Description Remarks

ZCD_EN# 1 Zero current detection enable When asserted "L" signal, zero crossing

detection is enabled

VCIN 2 Control input voltage (+5 V input) Driver Vcc input

VDRV 3 Gate supply voltage (+5 V input) 5 V gate drive

BOOT 4 Bootstrap voltage pin To be supplied +5 V through internal switch

CGND 5, 37, Pad Control signal ground Should be connected to PGND externally

GH 6 High-side gate signal Pin for monitor

VIN 8 to 14, Pad Input voltage

VSWH 7, 15, 29 to 35, Pad Phase output/Switch output

PGND 16 to 28 Power ground

GL 36 Low-side gate signal Pin for monitor

THWN 38 Thermal warning Thermal warning when over 115°C

DISBL# 39 Signal disable Disabled when DISBL# is "L".

This Pin is pulled low when internal IC over the

thermal shutdown level, 150°C.

PWM 40 PWM drive logic input 5 V logic input

R2J20656ANP Preliminary

R07DS0201EJ0100 Rev.1.00 Page 4 of 15

Jan 25, 2011

Absolute Maximum Ratings

(Ta = 25°C)

Item Symbol Rating Units Note

Pt(25) 25 Power dissipation

Pt(110) 8

W 1

Average output current Iout 35 A

VIN(DC) –0.3 to +27 2 Input voltage

VIN(AC) 30

2, 4

Supply voltage & Drive voltage VCIN & VDRV –0.3 to +6 V 2

VSWH(DC) 27 2 Switch node voltage

VSWH(AC) 30

2, 4

VBOOT(DC) 32 2 BOOT voltage

VBOOT(AC) 36

2, 4

I/O voltage Vpwm, Vdisble,

Vlsdbl, Vthwn

–0.3 to VCIN + 0.3 V 2, 5

THWN/THDN current Ithwn, Ithdn 0 to 1.0 mA

Operating junction temperature Tj-opr –40 to +150 °C

Storage temperature Tstg –55 to +150 °C

Notes: 1. Pt(25) represents a PCB temperature of 25°C, and Pt(110) represents 110C.

2. Rated voltages are relative to voltages on the CGND and PGND pins.

3. For rated current, (+) indicates inflow.

4. The specification values indicated "AC" are limited within 10 ns.

5. VCIN + 0.3 V < 6 V

0 25 50 75 100 125 150 175

PCB Temperature (°C)

Safe Operating Area

Average Output Current (A)

VOUT = 1.3 V

VIN = 12 V

VCIN = 5 V

L = 0.45 μH

Fsw = 1 MHz

R2J20656ANP Preliminary

R07DS0201EJ0100 Rev.1.00 Page 5 of 15

Jan 25, 2011

Recommended Operating Condition

Item Symbol Rating Units Note

Input voltage VIN 4.5 to 22 V

Supply voltage & Drive voltage VCIN & VDRV 4.5 to 5.5 V

Electrical Characteristics

(Ta = 25°C, VCIN = 5 V, VDRV = 5 V, VSWH = 0 V, unless otherwise specified)

Item Symbol Min Typ Max Units Test Conditions

VCIN start threshold VH 4.1 4.3 4.5 V

VCIN shutdown threshold VL 3.6 3.8 4.0 V

UVLO hysteresis dUVL — 0.5 — V VH – VL

VCIN operating current ICIN — 49 — mA

fPWM = 1 MHz,

Ton_pwm = 120 ns

Supply

VCIN disable current ICIN-DISBL — — 150 A DISBL# = 0 V,

PWM = ZCD_EN# = Open

PWM input high level VH-PWM 4.0 — — V 5.0 V PWM interface

PWM input low level VL-PWM — — 0.8 V

PWM input resistance RIN-PWM 6.5 12.5 25 k PWM = 1 V

PWM input tri-state range VIN-tri 1.5 — 3.2 V 5.0 V PWM interface

PWM

input

Shutdown hold-off time tHOLD-OFF *1— 150 — ns

Enable level VENBL 2.0 — — V

Disable level VDISBL — — 0.8 V

Input current IDISBL — 2.0 5.0 A DISBL# = 1 V

DISBL#

input

THDN on resistance RTHDN *1 0.2 0.5 1.0 k DISBL# = 0.2 V

ZCD disable level Vzcddisbl 2.0 — — V

ZCD enable level Vzcden — — 0.8 V

ZCD_EN#

Input current Izcden –52 –25 –12 A ZCD_EN# = 1 V

Warning temperature TTHWN *1 100 115 130 °C Driver IC temperature

Temperature hysteresis THYS *1 — 15 — °C

THWN on resistance RTHWN *1 0.2 0.5 1.0 k THWN = 0.2 V

Thermal

warning

THWN leakage current ILEAK — — 1.0 A THWN = 5 V

Thermal

shutdown

Shutdown temperature Tstdn *1 130 150 — °C Driver IC temperature

Note: 1. Reference values for design. Not 100% tested in production.

R2J20656ANP Preliminary

R07DS0201EJ0100 Rev.1.00 Page 6 of 15

Jan 25, 2011

Typical Application

VCIN

CGND GL

VIN

BOOT

4.5 to 22 V

+5 V

+1.3 V

GHVDRV

R2J20656

ANP

PGND

THWN

DISBL#

ZCD_EN#

PWM1

PWM

VSWH

VCIN

CGND GL

VIN

BOOT GHVDRV

R2J20656

ANP

PGND

THWN

DISBL#

ZCD_EN#

PWM2

PWM

VSWH

VCIN

CGND GL

VIN

BOOT GHVDRV

R2J20656

ANP

PGND

THWN

DISBL#

ZCD_EN#

PWM

VSWH

VCIN

CGND GL

VIN

BOOT GHVDRV

PWM

Control

Circuit

R2J20656

ANP

PGND

THWN

DISBL#

ZCD_EN#

PWM

VSWH

PWM3

PWM4

Power GND Signal GND

R2J20656ANP Preliminary

R07DS0201EJ0100 Rev.1.00 Page 7 of 15

Jan 25, 2011

Pin Connection

+5 V

0.1 μF

0.45 μH

VIN

(4.5 to 22 V)

PGND

Power GND Signal GND

R2J20656ANP

CGND

PAD

21 22 23 24 25 26 27 28 29 30

10 9 8 7654321

PWM

DISBL#

THWN

CGND

VSWH

VIN

VSWH GL

PGND

VSWH

VIN

VSWH

CGND

BOOT

VDRV

VCIN

ZCD_EN#

ZCD_EN#able Signal INPUT

VIN

PAD

PGND

1.0 μF

CGND

10 μF × 4

+5 V

Thermal Shutdown

PWM INPUT

VSWH

PAD

10 kΩ

+5 V

10 kΩ

Vout

Thermal Warning

0 to 10 Ω

R2J20656ANP Preliminary

R07DS0201EJ0100 Rev.1.00 Page 8 of 15

Jan 25, 2011

Test Circuit

VCIN

VIN

VSWH

BOOT

R2J20656ANP

PGND

Vcont

Vinput

CGND

DISBL#

VDRV

ZCD_EN#

PWM

5 V pulse

Note: PIN = IIN × VIN + ICIN × VCIN

POUT = IO × VO

Efficiency = POUT / PIN

PLOSS(DrMOS) = PIN – POUT

Ta = 27°C

Average Output Voltage

VCIN

VIN

ICIN

IIN

Electric

load

Averaging

circuit

R2J20656ANP Preliminary

R07DS0201EJ0100 Rev.1.00 Page 9 of 15

Jan 25, 2011

Typical Data

Power Loss vs. Output Current

Output Current (A)

Output Voltage (V)

Power Loss (W)

Normalized Power Loss

@ VIN = 12 V

Input Voltage (V)

Power Loss vs. Input Voltage

Power Loss vs. Switching Frequency

Normalized Power Loss

@ VOUT = 1.3 V

Switching Frequency (kHz)

Normalized Power Loss

@ f

PWM

= 600 kHz

Power Loss vs. Output Voltage

0 5 10 15 20 25 30 35 4 6 8 10 2012 14 2216 18

0.8

0.9

1.0

1.1

1.2

1.4

1.6

1.3

1.5

1.7

0.8

0.9

1.0

1.1

1.2

1.3

1.5

1.7

1.4

1.6

0.8

0.9

1.0

1.1

1.2

1.3

1.5

1.7

1.4

1.6

0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0 4.4 250 500 750 1000 1250

VIN = 12 V

VCIN = VDRV = 5 V

VOUT = 1.3 V

PWM

= 600 kHz

L = 0.45 μH

VIN = 12 V

VCIN = VDRV = 5 V

PWM

= 600 kHz

L = 0.45 μH

IOUT = 25 A

VIN = 12 V

VCIN = VDRV = 5 V

VOUT = 1.3 V

L = 0.45 μH

IOUT = 25 A

VCIN = VDRV = 5 V

VOUT = 1.3 V

PWM

= 600 kHz

L = 0.45 μH

IOUT = 25 A

R2J20656ANP Preliminary

R07DS0201EJ0100 Rev.1.00 Page 10 of 15

Jan 25, 2011

Power Loss vs. Output Inductance

Output Inductance (μH)

Normalized Power Loss

@ L = 0.45 μH

Normalized Power Loss

@ VCIN = VDRV = 5 V

Power Loss vs. VCIN

0.10.20.30.40.50.60.70.80.91.0

VCIN = VDRV (V)

4.5 5.0 5.5 6.0

VIN = 12 V

VCIN = VDRV = 5 V

VOUT = 1.3 V

PWM

= 600 kHz

IOUT = 25 A

VIN = 12 V

VCIN = VDRV = 5 V

VOUT = 1.3 V

L = 0.45 μH

IOUT = 0 A

Switching Frequency (kHz)

Average ICIN vs. Switching Frequency

Average ICIN (mA)

250 500 750 1000 1250

0.8

0.9

1.0

1.1

1.2

1.3

1.5

1.7

1.4

1.6

0.8

0.9

1.0

1.1

1.2

1.3

1.5

1.7

1.4

1.6

VIN = 12 V

VOUT = 1.3 V

PWM

= 600 kHz

L = 0.45 μH

IOUT = 25 A

R2J20656ANP Preliminary

R07DS0201EJ0100 Rev.1.00 Page 11 of 15

Jan 25, 2011

Description of Operation

The DrMOS multi-chip module incorporates a high-side MOS FET, low-side MOS FET, and MOS-FET driver in a

single QFN package. Since the parasitic inductance between each chip is extremely small, the module is highly suitable

for use in buck converters to be operated at high frequencies. The control timing between the high-side MOS FET, low-

side MOS FET, and driver is optimized so that high efficiency can be obtained at low output-voltage.

VCIN & DISBL#

The VCIN pin is connected to the UVL (under-voltage lockout) module, so that the driver is disabled as long as VCIN

is 4.3 V or less. On cancellation of UVL, the driver remains enabled until the UVL input is driven to 3.8 V or less. The

signal on pin DISBL# also enables or disables the circuit.

Voltages from –0.3 V to VCIN can be applied to the DISBL# pin, so on/off control by a logic IC or the use of a resistor,

etc., to pull the DISBL# line up to VCIN are both possible.

VCIN DISBL# Driver State

L  Disable (GL, GH = L)

H L Disable (GL, GH = L)

H H Active

H Open Disable (GL, GH = L)

The pulled-down MOS FET, which is turned on when internal IC temperature becomes over thermal shutdown level, is

connected to the DISBL# pin. The detailed function is described in THDN section.

PWM & ZCD_EN#

The PWM pin is the signal input pin for the driver chip. The input-voltage range is –0.3 V to (VCIN + 0.3 V). When the

PWM input is high, the gate of the high-side MOS FET (GH) is high and the gate of the low-side MOS FET (GL) is

low.

PWM GH GL

L L H

H H L

The ZCD_EN# pin is the Zero Current Detection Operation Enable pin for "Diode Emulation Mode (DEM)" when

ZCD_EN# is low. This function improves light load efficiency by preventing negative inductor current from output

capacitor. Driver IC monitors inductor current and when inductor current crosses zero, driver IC turn off Low side MOS

FET automatically.

Figure 1.1 shows the Typical high side and low side gate switching and Inductor current (IL) during Continuous

Conduction Mode (CCM), and figure 1.2 shows DEM when asserting Zero Current Detection Enable signal.

ZCD_EN# pin is internally pulled up to VCIN with 160 k resistor. When Zero current detection function is not used,

keep this pin open or pulled up to VCIN.

CCM Operation (ZCD_EN# = "H" or Open mode)

PWM

Figure 1.1 Typical Signals during CCM

R2J20656ANP Preliminary

R07DS0201EJ0100 Rev.1.00 Page 12 of 15

Jan 25, 2011

DEM Operation (ZCD_EN# = "L" in Light load condition)

PWM

0 A

Figure 1.2 Typical Signals during DEM

The PWM input is TTL level and has hysteresis. When the signal route from the control IC is high impedance, the tri-

state function turns off the high- and low-side MOS FETs. This function operates when the PWM input signal stays in

the input hysteresis window for 150 ns (typ.). After the tri-state mode has been entered and GH and GL have become

low, a PWM input voltage of 4.0 V or more is required to make the circuit return to normal operation.

3.2 V

1.5 V

3.2 V

1.5 V

150 ns (t

HOLD-OFF

)

150 ns (t

HOLD-OFF

)

150 ns (t

HOLD-OFF

)

150 ns (t

HOLD-OFF

)

PWM

Figure 2 PWM Shutdown-Hold Time Signal

R2J20656ANP Preliminary

R07DS0201EJ0100 Rev.1.00 Page 13 of 15

Jan 25, 2011

The equivalent circuit for the PWM-pin input is shown in the next figure. M1 is in the ON state during normal

operation; after the PWM input signal has stayed in the hysteresis window for 150 ns (typ.) and the tri-state detection

signal has been driven high, the transistor M1 is turned off.

When VCIN is powered up, M1 is started in the OFF state regardless of PWM Low or Open state. After PWM is

asserted high signal, M1 becomes ON and shifts to normal operation.

VCIN

14.5 k

To internal control

Tri-state

detection signal

12.5 k

Input

Logic

PWM Pin

Figure 3 Equivalent Circuit for the PWM-pin Input

THWN & THDN

This device has two level thermal detection, one is thermal warning and the other is thermal shutdown function.

This Thermal Warning feature is the indication of the high temperature status.

THWN is an open drain logic output signal and need to connect a pull-up resistor (ex.51 k) to THWN for Systems

with the thermal warning implementation.

When the chip temperature of the internal driver IC becomes over 115°C, Thermal warning function operates.

This signal is only indication for the system controller and does not disable DrMOS operation.

When thermal warning function is not used, keep this pin open.

(°C)

115100

Thermal

warning

Normal

operating

THWN output

Logic Level

"L"

"H"

Figure 4 THWN Trigger Temperature

R2J20656ANP Preliminary

R07DS0201EJ0100 Rev.1.00 Page 14 of 15

Jan 25, 2011

THDN is an internal thermal shutdown signal when driver IC becomes over 150°C.

This function makes High Side MOS FET and Low Side MOS FET turn off for the device protection from abnormal

high temperature situation and at the same time DISBL# pin is pulled low internally to give notice to the system

controller. Once thermal shutdown function operates, driver IC keeps DISBL# pin pulled low until VCIN becomes

under UVL level (3.8 V).

Figure 5 shows the example of two types of DISBL# connection with the system controller signal.

Driver IC Temp. Driver Chip Status

< 150°C Enable (GL, GH = "Active")

> 150°C Shutdown (GL, GH = "L")

Figure 5.1 THDN Signal to the System Controller Figure 5.2 ON/OFF Signal from the System Controlle

2 μA

10 k

5 V

DISBL#

Thermal

Shutdown

Detection

To Internal

Logic

To shutdown signal

2 μA

DISBL#

Thermal

Shutdown

Detection

To Internal

Logic

ON/OFF signal

10 k

MOS FET

The MOS FETs incorporated in R2J20656ANP are highly suitable for synchronous-rectification buck conversion. For

the high-side MOS FET, the drain is connected to the VIN pin and the source is connected to the VSWH pin. For the

low-side MOS FET, the drain is connected to the VSWH pin and the source is connected to the PGND pin.

R2J20656ANP Preliminary

R07DS0201EJ0100 Rev.1.00 Page 15 of 15

Jan 25, 2011

Package Dimensions

Dimension in Millimeters

Reference

Symbol

P-HVQFN40-p-0606-0.50 ——PVQN0040KE-A

MASS[Typ.]RENESAS CodeJEITA Package Code Previous Code

5.95 6.00 6.05

Min Nom Max

0.87 0.89 0.91

— — 0.20

0.865 0.91 0.95

0.005 0.02 0.04

0.17 0.22 0.27

0.16 0.20 0.24

— 0.50 —

0.40 0.50 0.60

— — 0.05

— — 0.05y

— — 0.20

6.15 6.20 6.25HD

6.15 6.20 6.25

— 0.75 —

— 0.75 —ZE

0.06 0.10 0.14

0.17 0.20 0.23

0.17 0.22 0.27

HE/2 E /2

t S AB

bx S AB

f S AB

X 4

2-A section

HD/2 D /2

4-C0.50

20°

4-(0.139)

1.95

1pin

C0.3

INDEX

0.2

0.7

2.2

2.05

0.2

2.2

0.2

2.2

2.05

CAV No.

Die No.

y1 S

0.69

Ordering Information

Part Name Quantity Shipping Container

R2J20656ANP#G0 2500 pcs Taping Reel

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Renesas Electronics America Inc.

2880 Scott Boulevard Santa Clara, CA 95050-2554, U.S.A.

Tel: +1-408-588-6000, Fax: +1-408-588-6130

Renesas Electronics Canada Limited

1101 Nicholson Road, Newmarket, Ontario L3Y 9C3, Canada

Tel: +1-905-898-5441, Fax: +1-905-898-3220

Renesas Electronics Europe Limited

Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K

Tel: +44-1628-585-100, Fax: +44-1628-585-900

Renesas Electronics Europe GmbH

Arcadiastrasse 10, 40472 Düsseldorf, Germany

Tel: +49-211-65030, Fax: +49-211-6503-1327

Renesas Electronics (China) Co., Ltd.

7th Floor, Quantum Plaza, No.27 ZhiChunLu Haidian District, Beijing 100083, P.R.China

Tel: +86-10-8235-1155, Fax: +86-10-8235-7679

Renesas Electronics (Shanghai) Co., Ltd.

Unit 204, 205, AZIA Center, No.1233 Lujiazui Ring Rd., Pudong District, Shanghai 200120, China

Tel: +86-21-5877-1818, Fax: +86-21-6887-7858 / -7898

Renesas Electronics Hong Kong Limited

Unit 1601-1613, 16/F., Tower 2, Grand Century Place, 193 Prince Edward Road West, Mongkok, Kowloon, Hong Kong

Tel: +852-2886-9318, Fax: +852 2886-9022/9044

Renesas Electronics Taiwan Co., Ltd.

7F, No. 363 Fu Shing North Road Taipei, Taiwan

Tel: +886-2-8175-9600, Fax: +886 2-8175-9670

Renesas Electronics Singapore Pte. Ltd.

1 harbourFront Avenue, #06-10, keppel Bay Tower, Singapore 098632

Tel: +65-6213-0200, Fax: +65-6278-8001

Renesas Electronics Malaysia Sdn.Bhd.

Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No. 18, Jln Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia

Tel: +60-3-7955-9390, Fax: +60-3-7955-9510

Renesas Electronics Korea Co., Ltd.

11F., Samik Lavied' or Bldg., 720-2 Yeoksam-Dong, Kangnam-Ku, Seoul 135-080, Korea

Tel: +82-2-558-3737, Fax: +82-2-558-5141

SALES OFFICES

Colophon 1.0

www.s-manuals.com

R2J20656ANP Datasheet. Www.s Manuals.com. R1.0 Renesas

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