R7735 Datasheet. Www.s Manuals.com. Richtek

User Manual: Datasheets R7735, R7735AGE, R7735AGN, R7735GGE, R7735GGN, R7735HGE, R7735HGN, R7735LGE, R7735LGN, R7735RGE, R7735RGN.

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R7735
High Performance Enhanced Quadruple Mode PWM
Flyback Controller
General Description

Features

R7735 series is the successor of R7732/3 and fully
compatible with most of SOT-23-6 / DIP-8 product so far
in the market. It has enhanced quadruple mode PWM
controller and owns excellent green power performance,
especially under light load and no load conditions. It
focuses on "easy to design" in different applications and
it will save both design effort and external components.

Besides the general features shown in the Features
section, R7735 covers wide protection options, such as
internal Over Load Protection (OLP) and Over Voltage
Protection (OVP) to eliminate the external protection
circuits. Moreover, it also features Secondary Rectifier
Short Protection (SRSP) and CS pin open protection. This
protection will make the PSU design for reliability and
safety easier.

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R7735 is designed for power supply such as NB adaptor
which is a very cost effective and compact design. The
precise external OVP and Over Temperature Protection
(OTP) can be implemented by very simple circuit. The
start-up resistors can also be replaced by bleeding
resistors to save power loss and component count.

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Application

(B)* (* : See Version Table)

Package Type
E : SOT-23-6
N : DIP-8 (R7735G Only)

Switching AC/DC Adaptor
DVD Open Frame Power Supply
Set-Top Box (STB)
ATX Standby Power
TV/Monitor Standby Power
PC Peripherals

Lead Plating System
G : Green (Halogen Free and Pb Free)

NB Adaptor

R7735 Version (Refer to Version Table)

Marking Information

Ordering Information
R7735

Note :
Richtek products are :
`

No Load Input Power Under 100mW
Accurate Over Load Protection
UVLO 9V/14V
Soft Start Function
Current Mode Control
Built-in Slope Compensation
Internal Leading Edge Blanking
PWM Quadruple Mode for Green-Mode
Excellent Green Power Performance
Cycle-by-Cycle Current Limit
Internal Over Voltage Protection
Secondary Rectifier Short Protection
Opto-Coupler Short Protection
Feedback Open-Loop Protection
CS Pin Open Protection
Built-in Jittering Frequency
Built-in PRO Pin for External Arbitrary OVP/OTP
Soft Driving for EMI Noise
High Noise Immunity
RoHS Compliant and Halogen Free

RoHS compliant and compatible with the current

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For marking information, contact our sales representative
directly or through a Richtek distributor located in your
area.

requirements of IPC/JEDEC J-STD-020.
`

Suitable for use in SnPb or Pb-free soldering processes.

R7735-03

September 2012

is a registered trademark of Richtek Technology Corporation.

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1

R7735
Pin Configurations
(TOP VIEW)
GND COMP NC

PRO

GATE VDD CS
8
6

GND COMP PRO

GATE VDD

SOT-23-6

DIP-8

R7735 Version Table
Version

R7735G

R7735R

R7735L

R7735A

R7735H

Frequency

65kHz

100kHz

OLP Delay Time

56ms

28ms

36ms

Internal OVP(27V)

Auto Recovery

Latch

Auto Recovery

OLP & SRSP

Auto Recovery

Latch

Auto Recovery

PRO Pin High

Latch

Auto Recovery

Latch

Auto Recovery

PRO Pin Low

Auto Recovery

Latch

* : VSRSP_TH : Secondary Rectifier Short Protection (SRSP) triggered threshold.
R7735XGE : VSRSP_TH = 1.7V, X = G/R/L/A
R7735HGE(B) : VSRSP_TH = 2.6V

Typical Application Circuit
Vo+
+

AC Mains
(90V to 265V)

Vo-

#
PRO

VDD

GATE

R7735
COMP

CS
GND

NTC

# : See Application Information
Copyright © 2012 Richtek Technology Corporation. All rights reserved.

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is a registered trademark of Richtek Technology Corporation.

R7735-03

September 2012

R7735
Functional Pin Description
Pin No.

Pin Name

Pin Function

SOT-23-6

DIP-8

GND

Ground.

COMP

Voltage Feedback. By connecting an opto-coupler to close control loop
and achieve the regulation.

PRO

For External Arbitrary OVP or OTP.

Primary Current Sense.

VDD

Power Supply.

GATE

Gate Drive Output to Drive the External MOSFET.

3, 6

No Internal Connection.

Function Block Diagram

IBIAS

VL_TH

VDD

Auto
Recovery

Latch

OVP

PRO
+

VSRSP_TH

VH_TH

Secondary Rectifier Short
- & CS Open Protection
+

POR
Shutdown
Logic

UVLO
+

Brownout
Sensing

Counter

COMP Open
Sensing

9V/14V

Bias &
Bandgap

OLP

Oscillator

Constant
Power

Dmax
Soft Driver

S
COMP

Slope
Ramp

+
PWM
Comparator

GATE

VCOMP
Quadruple Mode

LEB

27V

VBURL
VBURH
VDD
GND

R7735-03

September 2012

is a registered trademark of Richtek Technology Corporation.

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3

R7735
Absolute Maximum Ratings
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(Note 1)

Supply Input Voltage, VDD ----------------------------------------------------------------------------------------------GATE Pin --------------------------------------------------------------------------------------------------------------------PRO, COMP, CS Pin -----------------------------------------------------------------------------------------------------IDD -----------------------------------------------------------------------------------------------------------------------------Power Dissipation, PD @ TA = 25°C
SOT-23-6 -------------------------------------------------------------------------------------------------------------------DIP-8 -------------------------------------------------------------------------------------------------------------------------Package Thermal Resistance (Note 2)
SOT-23-6, θJA --------------------------------------------------------------------------------------------------------------DIP-8, θJA -------------------------------------------------------------------------------------------------------------------Junction Temperature -----------------------------------------------------------------------------------------------------Lead Temperature (Soldering, 10 sec.) -------------------------------------------------------------------------------Storage Temperature Range --------------------------------------------------------------------------------------------ESD Susceptibility (Note 3)
HBM (Human Body Model) ----------------------------------------------------------------------------------------------MM (Machine Model) ------------------------------------------------------------------------------------------------------

Recommended Operating Conditions
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−0.3V to 30V
−0.3V to 16.5V
−0.3V to 6.5V
10mA
0.400W
0.714W
250°C/W
140°C/W
150°C
260°C
−65°C to 150°C
3kV
250V

(Note 4)

Supply Input Voltage, VDD ----------------------------------------------------------------------------------------------- 12V to 25V
Junction Temperature Range --------------------------------------------------------------------------------------------- −40°C to 125°C
Ambient Temperature Range --------------------------------------------------------------------------------------------- −40°C to 85°C

Electrical Characteristics
(VDD = 15V, TA = 25°C, unless otherwise specified)

Parameter

Symbol

Test Conditions

Min

Typ

Max

Unit

VDD Over Voltage Protection Level VOVP

VDD Zener Clamp

On Threshold Voltage

VTH_ON

Off Threshold Voltage

VTH_OFF

8.5

9.5

VDD Holdup Mode Entry Point

VDD_LOW

VCOMP < 1.6V

9.5

10.5

VDD Holdup Mode Ending Point

VDD_HIGH

VCOMP < 1.6V

10.5

Latch-off Voltage

VLH

4.5

5.5

6.5

Latched Reset Voltage

VLH_RST

Start-up Current

IDD_ST

VDD = VTH_ON – 0.2V,
TA= −40ºC to 100ºC (Note 5)

μA

Operating Supply Current

IDD_OP

VDD = 15V, VCOMP = 2.5V,
GATE pin open

0.55

0.9

1.6

Latch-off Operating Current

IDD_LH

TA= −40ºC to 100ºC (Note 5)

μA

VDD Section

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is a registered trademark of Richtek Technology Corporation.

R7735-03

September 2012

R7735
Parameter

Symbol

Test Conditions

Min

Typ

Max

R7735G/R/L/A

R7735H

100

108

R7735G/R/L/A

R7735H

Unit

Oscillator Section
Normal PWM Frequency

fOSC

kHz

Frequency Reduction Mode
Minimum Frequency

fFR_MIN

Maximum Duty Cycle

DCYMAX

PWM Frequency Jitter Range

Δf

±6

PWM Frequency Jitter Period

TJIT

For 65kHz

Frequency Variation Versus
VDD Deviation

fDV

VDD = 12V to 25V

Frequency Variation Versus
Temperature Deviation

fDT

TA = −30°C to 105°C
(Note 5)

5.5

5.75

R7735G/R/L

R7735A

R7735H

0.15

0.29

0.45

2.85

3.15

R7735G/R/L/A

2.75

2.9

3.05

R7735H

2.65

2.8

2.95

kHz

COMP Input Section
Open-Loop Voltage
COMP Open-Loop Protection
Delay Time

VCOMP_OP COMP pin Open
TOLP

Short Circuit Current

IZERO

Frequency Reduction Mode Entry
Voltage

VFR_ET

Frequency Reduction Mode
Ending Voltage

VFR_ED

VCOMP = 0V

Current Sense Section
Initial Peak Current Limitation
Offset

VCS_TH

0.68

0.7

0.72

Maximum Clamping Current Limit

VCS(MAX)

1.05

1.1

1.15

Leading Edge Blanking Time

tLEB

(Note 6)

150

250

350

Internal Propagation Delay Time

tPD

(Note 6)

100

Minimum On Time

tON(MIN)

250

350

450

GATE Section
Rising Time

VDD = 15V, CL= 1nF

125

140

Falling Time

VDD = 15V, CL= 1nF

GATE Output Clamping Voltage

VCLAMP

VDD = 25V

12.1

15.9

PRO Interface Section
Pull Low Threshold

VL_TH

0.47

0.5

0.53

Pull High Threshold

VH_TH

3.5

3.8

4.1

Internal Bias Current

IBIAS

100

110

μA

Pull High Sinking Current

ISINK

0.7

1.4

(Note 7)

R7735-03

September 2012

is a registered trademark of Richtek Technology Corporation.

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R7735
Note 1. Stresses beyond those listed “Absolute Maximum Ratings” may cause permanent damage to the device. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may affect
device reliability.
Note 2. θJA is measured at TA = 25°C on a low effective thermal conductivity single-layer test board per JEDEC 51-3.
Note 3. Devices are ESD sensitive. Handling precaution is recommended.
Note 4. The device is not guaranteed to function outside its operating conditions.
Note 5. Guaranteed by design.
Note 6. Leading edge blanking time and internal propagation delay time are guaranteed by design.
Note 7. The sourcing current of PRO pin must be limited below 5mA. Otherwise it may cause permanent damage to the
device.

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is a registered trademark of Richtek Technology Corporation.

R7735-03

September 2012

R7735
Typical Operating Characteristics
IDD_ST vs. Temperature

IDD_ST vs. VDD
6

5
4

I DD_ST (µA)

3
2

4
1
0

2
0

-50

-25

R7735G/R/L/A

f OSC (kHz)

100

125

100

125

100

125

R7735G/R/L/A

60
10

-50

-25

VDD (V)

Temperature (°C)

fOSC vs. VDD
104

fOSC vs. Temperature
104

R7735H

102

f OSC (kHz)

102

f OSC (kHz)

fOSC vs. Temperature

fOSC vs. VDD

100

96
10

VDD (V)
Copyright © 2012 Richtek Technology Corporation. All rights reserved.

R7735-03

Temperature (°C)

VDD (V)

September 2012

-50

-25

Temperature (°C)
is a registered trademark of Richtek Technology Corporation.

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R7735
VTH_OFF vs. Temperature
10.0

9.5

VTH_OFF (V)

VTH_ON (V)

VTH_ON vs. Temperature
16

9.0

8.5

8.0

-50

-25

100

125

-50

-25

100

125

100

125

100

125

IDD_OP vs. Temperature

fFR_MIN vs. Temperature
30

1.05

0.95

VDD = 15V,
VCOMP = 2.5V,
GATE Pin Open

I DD_OP (mA)

f FR_MIN (kHz)

Temperature (°C)

0.85

0.75

0.65

10
-50

-25

100

-50

125

-25

Temperature (°C)

VOVP vs. Temperature

VCOMP_OP vs. Temperature
6.0

5.8

VOVP(V)

VCOMP_OP (V)

5.6

5.4

5.2
-50

-25

100

Temperature (°C)
Copyright © 2012 Richtek Technology Corporation. All rights reserved.

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125

-50

-25

Temperature (°C)
is a registered trademark of Richtek Technology Corporation.

R7735-03

September 2012

R7735
TOLP vs. Temperature

TOLP vs. Temperature
70

R7735G/R/L

TOLP (ms)

R7735A

50
-50

-25

100

-50

125

-25

R7735H

125

100

125

100

125

0.75

VCS_TH (V)

TOLP (ms)

100

0.80

0.70

0.65

0.60
-50

-25

100

125

-50

-25

Temperature (°C)

IBIAS vs. Temperature

IDD_LH vs. Temperature
10

110

100

I BIAS (µA)

I DD_LH (µA)

VCS_TH vs. Temperature

TOLP vs. Temperature

2
-50

-25

100

Temperature (°C)
Copyright © 2012 Richtek Technology Corporation. All rights reserved.

R7735-03

Temperature (°C)

September 2012

125

-50

-25

Temperature (°C)
is a registered trademark of Richtek Technology Corporation.

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9

R7735
VL_TH vs. Temperature
0.60

0.55

VL_TH (V)

VH_TH (V)

VH_TH vs. Temperature
6

0.50

0.45

0.40

-50

-25

100

125

-50

-25

Temperature (°C)

100

125

100

125

100

125

TF vs. Temperature

140

130

TF (ns)

TR (ns)

TR vs. Temperature

120

110

100
-50

-25

100

-50

125

-25

Temperature (°C)

DCYMAX vs. Temperature

VCLAMP vs. Temperature
18

DCYMAX (%)

VCLAMP (V)

Temperature (°C)

70
-50

-25

100

Temperature (°C)
Copyright © 2012 Richtek Technology Corporation. All rights reserved.

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10

125

-50

-25

Temperature (°C)
is a registered trademark of Richtek Technology Corporation.

R7735-03

September 2012

R7735
Application Information
PWM Quadruple Mode
R7735 has enhanced quadruple mode PWM controller and
owns excellent green power performance, especially under
light load and no load conditions. Please refer Figure 1 for
details.
#

: To enhance light load efficiency, the feedback resistor
loss is reduced. Due to small feedback resistor current,
shunt regulator selection and minimum regulation current
design must be careful to make sure it's able to regulate
under low cathode current.

This frequency reduction mode function reduces power
consumption under light-load and no-load conditions, and
easily meets even the strictest regulations.
Frequency

fOSC

fFR_MIN

PWM Mode
For most of load, the circuit will run at traditional PWM
current mode.

VFR_ED

VFR_ET

VCOMP

Figure 2. PWM Frequency vs. COMP Voltage

Frequency Reduction Mode

Burst Mode

he frequency reduction mode function provides linear
switching frequency reduction according to load
conditions, as shown in Figure 2. When the feedback
voltage of COMP pin is lower than VFR_ET, the switching
frequency starts to decrease. When the power supply is
at light-load and the feedback voltage of COMP pin lower
than VFR_ED, the switching frequency is clamped at fFR_MIN.

During light load, switching loss will dominate the power
efficiency calculation. This mode is to cut switching loss.
As shown in Figure 1, when the output load gets light,
feedback signal drops and touches VBURL. PWM signal
will be blanked and system ceases to switch. After VOUT
drops and feedback signal goes back to VBURH, switching
will be resumed.

Normal
Operation

Frequency
Reduction Mode

Burst
Mode

VDD
Holdup Mode

Load

VDD

VDD_HIGH
VDD_LOW

VCOMP
VBURH
VBURL

GATE

Figure 1. PWM Quadruple Mode
Copyright © 2012 Richtek Technology Corporation. All rights reserved.

R7735-03

September 2012

is a registered trademark of Richtek Technology Corporation.

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R7735
VDD Holdup Mode

Start-up Circuit

Under light load or load transient moment, feedback signal
will drop and touch VBURL. Then PWM signal will be
blanked and system ceases to switch. VDD could drop
down to turn off threshold voltage. To avoid this, when VDD
drops to a setting threshold, 10V, the hysteresis
comparator will bypass PWM and burst mode loop and
forces switching at a very low level to supply energy to
VDD pin. VDD holdup mode was also improved to hold up
VDD by less switching cycles. This mode is very useful in
reducing start-up resistor loss while still get start-up time
in spec. It's not likely for VDD to touch UVLO turn off
threshold during any light load condition. This will also
makes bias winding design and transient design easier.

To minimize power loss, it's recommended that the startup current is from bleeding resistor. It's not only good for
power saving but also could reset latch mode protection
quickly. Figure 3 shows IDD_Avg vs. RBleeding curve. User
can apply this curve to design the adequate bleeding
resistor.

Furthermore, VDD holdup mode is only designed to prevent
VDD from touching turn off threshold voltage under light
load or load transient moment. Relative to burst mode,
switching loss will increase on the system at VDD holdup
mode, so it is highly recommended that the system should
avoid operating at this mode during light load or no load
condition, normally.

Gate Driver
A totem pole gate driver is fine tuned to meet both EMI
and efficiency requirement in low power application. An
internal pull low circuit is activated after pretty low VDD to
prevent external MOSFET from accidentally turning on
during UVLO.
Oscillator
To guarantee precise frequency, it's trimmed to 5%
tolerance. It also generates slope compensation saw-tooth,
75% maximum duty cycle pulse and overload protection
slope. It can typically operate at built-in 65kHz center
frequency and features frequency jittering function. Its
jittering depth is 6% with about 4ms envelope frequency
at 65kHz.

IDD_Avg vs. RBleeding Curve
30
28
26

RBleeding

I DD_Avg (μA)

24
22

IDD_Avg

RBleeding

20
18

90Vac
85Vac
80Vac

16
14

VDD

12
10
2.0

2.2

2.4

2.6

2.8

3.0

3.2

3.4

3.6

3.8

4.0

RBleeding Curve (MΩ)

Figure 3. IDD_Avg vs. RBleeding Curve

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R7735-03

September 2012

R7735
Tight Current Limit Tolerance
IBIAS

Deglitch
30µs

Auto
Recovery

Deglitch
50µs

Latch

PRO
+

VH_TH

PRO Pin Application

VL_TH

Since R7735 is the successor of R7732/3, its current limit
setting is completely the same as R7732/3. Generally,
the saw current limit applied to low cost Flyback controller
because of simple design. However, saw current limit is
hard to test in mass production. Therefore, it's generally
"guaranteed by design". The variation of process and
package will make its tolerance wider. It will lead to 20%
to 30% variation when doing OLP test at certain line
voltage. This will cause yield loss in power supply mass
production. Through well foundry control, design and test
/ trim mode in final test, R7735 current limit tolerance is
tight enough to make design easier.

VPRO
Auto Recovery / Latch
VH_TH
Normal Operating
VL_TH

Auto Recovery / Latch

Figure 4. PRO Pin Diagram

R7735 features a PRO pin, as shown in Figure 4, and it
can be applied for external arbitrary OVP or OTP (ex :

VDD

Figure 5 to Figure 8).
If the voltage of PRO pin is greater than pull-low threshold
VL_TH, the controller is enabled and switching will occur. If
the voltage of PRO pin falls below pull-low threshold or
rises to pull-high threshold VH_TH, the controller will be
shut down and cease to switch after deglitch delay.
PRO pin is built in 1.5V internally, so leave PRO pin open
if you don't need this function. If designer needs to apply
a bypass capacitor on PRO pin, it should not be more
than 1nF. The internal bias current of PRO pin is 100μA
(typ.). R7735 has internal OVP. For arbitrary OVP or OTP
applications which behave as auto recovery or latch, it
can get these by PRO pin. For PRO pin pulling high
function applications, the voltage of PRO pin must rise
above VH_TH (The supply current of PRO pin must be
greater than 1.4mA and be limited below 5mA.). When IC
enters latch mode, the IC maximum operating current is
8μA (100°C), and it will be release until VDD is fallen to
VTH_OFF.
PRO pin is guaranteed that below: If the voltage of PRO
pin reaches 4.1V or falls below 0.47V, the system will be
protected.

R7735-03

September 2012

PRO
(Option)

VDD OVP : VDD > VR + VZ + 3.8V
Figure 5. For VDD OVP Only

PRO

(Option)
NTC

Figure 6. For OTP Only

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R7735
VDD

PRO

Long time cycle-by-cycle current limit will lead to system
thermal stress. To further protect system, system will
be shut down after 56ms (R7735A: 28ms; R7735H:
36ms).

(Option)

Through our proprietary prolong turn off period during
hiccup(R7735A: latch), the power loss and thermal
during OLP will be averaged to an acceptable level over
the ON/OFF cycle of the IC. This will last until fault is
removed.

Figure 7. For VDD OVP
PRO

Vo+

During initial power on, especially at high line, current
spike is kind of unlimited by current limit. Therefore,
besides cycle-by-cycle current limiting, R7735 still
provides soft start function. It effectively suppresses the
stat-up current spike. The typical soft start duration is
about 40 clock cycles. This will provide more reliable
operation and possibility to use smaller current rating power
MOSFET.

Cycle-by-Cycle Current Limit
This is a basic but very useful function and it can be
implemented easily in current mode controller.

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Over Voltage Protection
Output voltage can be roughly sensed by VDD pin. If
the sensed voltage reaches 27V threshold, system will
be shut down and hiccup after 20μs deglitch delay for
R7735G/R/H or latch after 70μs deglitch delay for
R7735L/A. This will last until fault is removed.

Feedback Open and Opto-Coupler Short
This will trigger OVP or OLP. It depends on which one
occurs first.

Protection
R7735 provide fruitful protection functions that intend to
protect system from being damaged. All the protection
functions can be listed as below:

CS Pin Open Protection
When CS pin is opened, the system will be shut down
after couples of cycle. It could pass CS pin open test
easier.

Figure 8. For VOUT OVP
Soft-Start

Brownout Protection
During heavy load, this will trigger 56ms(R7735A: 28ms;
R7735H: 36ms) protection and shut down the system.
If it is in light load condition, system will be shut down
after VDD is running low and triggers UVLO.

(Option)

Over Load Protection

Secondary Rectifier Short Protection
As shown in Figure 9. The current spike during
secondary rectifier short test is extremely high because
of the saturated main transformer. Meanwhile, the
transformer acts like a leakage inductance. During high
line, the current in power MOSFET is sometimes too
high to wait for OLP delay time. To offer better and easier
protection design, R7735 shut down the controller after
couples of cycles before fuse is blown up.

is a registered trademark of Richtek Technology Corporation.

R7735-03

September 2012

R7735
Thermal Considerations

Secondary Rectifier Short
Zoom In

R7735G/R/L/H

VDD
VCOMP

For continuous operation, do not exceed absolute
maximum junction temperature. The maximum power
dissipation depends on the thermal resistance of the IC
package, PCB layout, rate of surrounding airflow, and
difference between junction and ambient temperature. The
maximum power dissipation can be calculated by the
following formula :
PD(MAX) = (TJ(MAX) − TA) / θJA

VCS

Figure 9. Secondary Rectifier Short Protection

Negative Voltage Spike on Each Pin
Negative voltage (< -0.3V) on each pin will cause substrate
injection. It leads to controller damage or circuit false
trigger. Generally, it happens at CS pin due to negative
spike because of improper layout or inductive current
sense resistor. Therefore, it is highly recommended to
add a R-C filter to avoid CS pin damage, as shown in
Figure 10. Proper layout and careful circuit design should
be done to guarantee yield rate in mass production.

For recommended operating condition specifications, the
maximum junction temperature is 125°C. The junction to
ambient thermal resistance, θJA, is layout dependent. For
SOT-23-6 packages, the thermal resistance, θJA, is 250°C/
W on a standard JEDEC 51-3 single-layer thermal test
board. For DIP-8 packages, the thermal resistance, θJA,
is 140°C/W on a standard JEDEC 51-3 single-layer thermal
test board. The maximum power dissipation at TA = 25°C
can be calculated by the following formula :
PD(MAX) = (125°C − 25°C) / (250°C/W) = 0.400W for
SOT-23-6 package
PD(MAX) = (125°C − 25°C) / (140°C/W) = 0.714W for
DIP-8 package

AC Mains
(90V to 265V)

The maximum power dissipation depends on the operating
ambient temperature for fixed T J(MAX) and thermal
resistance, θJA. The derating curves in Figure 11 allow
the designer to see the effect of rising ambient temperature
on the maximum power dissipation.
3 PRO
2

NTC

where TJ(MAX) is the maximum junction temperature, TA is
the ambient temperature, and θJA is the junction to ambient
thermal resistance.

5
VDD

GATE

R7735
COMP

GND
1
R-C Filter

Figure 10. R-C Filter on CS Pin

R7735-03

September 2012

is a registered trademark of Richtek Technology Corporation.

www.richtek.com
15

R7735
Maximum Power Dissipation (W)

0.8
0.7

DIP-8

0.6
`

0.5
0.4

SOT-23-6

0.3

The path(2) from RCD snubber circuit to MOSFET is
also a high switching loop, too. Keep it as small as
possible.

` It is good for reducing noise, output ripple and EMI issue

0.2
0.1
0.0
0

100

125

Ambient Temperature (°C)

Figure 11.Derating Curve of Maximum Power Dissipation

to separate ground traces of bulk capacitor(a),
MOSFET(b), auxiliary winding(c) and IC control circuit
(d). Finally, connect them together on bulk capacitor
ground(a). The areas of these ground traces should be
kept large.
` Placing bypass capacitor for abating noise on IC is highly

recommended. The bypass capacitor should be placed
as close to controller as possible.

Layout Consideration
A proper PCB layout can abate unknown noise interference
and EMI issue in the switching power supply. Please refer
to the guidelines when you want to design PCB layout for
switching power supply:
`

to decrease noise coupling and kept a space to other
low voltage traces, such as IC control circuit paths,
especially.

Single-Layer PCB

The current path (1) from bulk capacitor, transformer,
MOSFET, Rcs return to bulk capacitor is a huge high
frequency current loop. It must be as short as possible

` In order to minimize reflected trace inductance and EMI,

it is minimized the area of the loop connecting the
secondary winding, the output diode, and the output
filter capacitor. In addition, apply sufficient copper area
at the anode and cathode terminal of the diode for
heatsinking. Apply a larger area at the quiet cathode
terminal. A large anode area can increase high-frequency
radiated EMI.

CBULK

AC Mains
(90V to 265V)

(2)
(a)

3 PRO
2
NTC

5
VDD

CBULK Ground (a)

GATE

R7735
COMP

Trace
IC
Ground (d)

Trace
Auxiliary
Ground (c)

Trace
MOSFET
Ground (b)

GND
1
(d)

(b)

Figure 12. PCB Layout Guide

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16

is a registered trademark of Richtek Technology Corporation.

R7735-03

September 2012

R7735
Outline Dimension
H
D
L
C

b
A
A1
e

Symbol

Dimensions In Millimeters

Dimensions In Inches

Min

Max

Min

Max

0.889

1.295

0.031

0.051

0.000

0.152

0.000

0.006

1.397

1.803

0.055

0.071

0.250

0.560

0.010

0.022

2.591

2.997

0.102

0.118

2.692

3.099

0.106

0.122

0.838

1.041

0.033

0.041

0.080

0.254

0.003

0.010

0.300

0.610

0.012

0.024

SOT-23-6 Surface Mount Package

R7735-03

September 2012

is a registered trademark of Richtek Technology Corporation.

www.richtek.com
17

R7735

Dimensions In Millimeters

Dimensions In Inches

Symbol
Min

Max

Min

Max

3.700

4.320

0.146

0.170

0.381

0.710

0.015

0.028

3.200

3.600

0.126

0.142

0.360

0.560

0.014

0.022

1.143

1.778

0.045

0.070

9.050

9.550

0.356

0.376

6.200

6.600

0.244

0.260

7.620

8.255

0.300

0.325

e
L

2.540
3.000

0.100
3.600

0.118

0.142

8-Lead DIP Plastic Package

Richtek Technology Corporation
5F, No. 20, Taiyuen Street, Chupei City
Hsinchu, Taiwan, R.O.C.
Tel: (8863)5526789
Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should
obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot
assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be
accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries.

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R7735-03

September 2012

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