RT8856 Datasheet. Www.s Manuals.com. R04 Richtek
User Manual: Datasheets RT8856, RT8856GQW.
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® RT8856 Multi-Phase PWM Controller for CPU Core Power Supply General Description Features The RT8856 is a single/dual phase PWM controller with two integrated MOSFET drivers. Moreover, it is compliant with Intel IMVP6.5 Voltage Regulator Specification to fulfill its mobile CPU Vcore power supply requirements. The RT8856 adopts NAVPTM (Native AVP) which is Richtek's 1/2 Phase PWM Controller with 2 Integrated MOSFET Drivers proprietary topology derived from finite DC gain compensator peak current mode, making it an easy setting PWM controller that meets all Intel AVP (Active Voltage Positioning) mobile CPU requirements. IMVP6.5 Compatible Power Management States (DPSRLVR, PSI, Extended Deeper Sleep Mode) NAVP (Native AVP) Topology 7-bit DAC 0.8% DAC Accuracy Fixed VBOOT (1.1V) Differential Remote Voltage Sensing Programmable Output Transition Slew Rate Control Accurate Current and Thermal Balance System Thermal Compensation AVP Ringing Free Mode at Light Load Conditions Fast Transient Response Power Good Clock Enable Output Thermal Throttling Current Monitor Output Switching Frequency up to 1MHz Per Phase OVP, UVP, NVP, OCP, OTP, UVLO 40-Lead WQFN Package RoHS Compliant and Halogen Free The output voltage of the RT8856 is set by 7-bit VID code. The built-in high accuracy DAC converts the VID code ranging from 0V to 1.5V with 12.5mV per step. The system accuracy of the controller can reach 1.5%. The part supports VID on-the-fly and mode change on-the-fly functions that are fully compliant with IMVP6.5 specification. It operates in single phase, dual phase and RFM. It can reach up to 90% efficiency in different modes according to different loading conditions. The droop load line can be easily programmed by setting the DC gain of the error amplifier. With proper compensation, the load transient can achieve optimized AVP performance. This chip controls soft-start and output transition slew rate via a capacitor. It supports both DCR and sense resistor current sensing. The current mode NAVPTM topology with high accuracy current sensing amplifier well balances the RT8856's channel currents. The RT8856 provides power good, clock enabling and thermal throttling output signals for IMVP6.5 specification. It also features complete fault protection functions including over voltage, under voltage, negative voltage, over current, thermal shutdown, and under voltage lockout. Ordering Information RT8856 Package Type QW : WQFN-40L 6X6 (W-Type) (Exposed Pad-Option 1) Lead Plating System G : Green (Halogen Free and Pb Free) Note : Richtek products are : The RT8856 is available in a WQFN-40L 6x6 small foot print package. RoHS compliant and compatible with the current requirements of IPC/JEDEC J-STD-020. Suitable for use in SnPb or Pb-free soldering processes. Applications IMVP6.5 Core Supply Multi-phase CPU Core Supply AVP Step-Down Converter Notebook/ Desktop Computer/ Servers Copyright © 2014 Richtek Technology Corporation. All rights reserved. DS8856-04 August 2014 is a registered trademark of Richtek Technology Corporation. www.richtek.com 1 RT8856 Pin Configurations Marking Information ISEN2_N BOOT2 OCSET ISEN2 TON PGOOD CLKEN VCC YMDNN : Date Code VRTT NTC (TOP VIEW) RT8856GQW : Product Number RT8856 GQW YMDNN 40 39 38 37 36 35 34 33 32 31 DPRSLPVR VRON FS CM CMSET VID6 VID5 VID4 VID3 VID2 1 30 2 29 3 28 27 4 5 26 GND 6 25 24 7 8 23 41 22 9 21 10 UGATE2 PHASE2 PGND2 LGATE2 PVCC LGATE1 PGND1 PHASE1 UGATE1 BOOT1 ISEN1 ISEN1_N RGND SOFT FB VSEN PSI COMP VID0 VID1 11 12 13 14 15 16 17 18 19 20 WQFN-40L 6x6 Typical Application Circuit VIN 7V to 24V 5V R1 38 VCC C3 VID2 VID3 VID4 R7 R8 Vccp 6 VID6 13 PSI DPRSLPVR 1 VRON 2 R11 40 PWRGD 39 CLKEN C12 R18 R15 C14 R20 R21 R22 PSI DPRSLPVR VRON R24 C18 3 R25 UGATE2 30 29 LGATE2 27 PGND2 28 COMP FS TON 37 R5 D1 R6 C6 C5 C9 R9 C8 Q3 L2 R10 VOUT Q4 R12 C7 VIN 7V to 21V R13 D2 R14 C10 C11 C9 R16 R17 VIN C13 33 ISEN2 32 ISEN2_N SOFT 18 RGND 17 NTC 35 OCSET 34 GND 41 (Exposed pad) Copyright © 2014 Richtek Technology Corporation. All rights reserved. www.richtek.com 2 31 CLKEN NTC1 CPU VCC SENSE BOOT2 PHASE2 C15 14 Q2 R4 24 PGOOD 15 FB R23 L1 R3 19 ISEN1 ISEN1_N 20 VID6 5 CMSET 16 VSEN CPU VSS SENSE VOUT PGND1 C4 Q1 LGATE1 25 36 VRTT 4 CM VRTT CM C2 R2 PHASE1 23 7 VID5 VID5 26 BOOT1 21 UGATE1 22 VID0 11 VID1 10 VID2 9 VID3 8 VID4 VID1 3.3V PVCC 12 VID0 C1 RT8856 VCC R19 C16 C17 CPU VSS SENSE R26 R29 R27 R28 VCC NTC2 is a registered trademark of Richtek Technology Corporation. DS8856-04 August 2014 RT8856 Table 1. IMVP6.5 VID code table VID6 VID5 VID4 VID3 VID2 VID1 VID0 Output VID6 VID5 VID4 VID3 VID2 VID1 VID0 Output 0 0 0 0 0 0 0 1.5000V 0 1 0 0 0 0 1 1.0875V 0 0 0 0 0 0 1 1.4875V 0 1 0 0 0 1 0 1.0750V 0 0 0 0 0 1 0 1.4750V 0 1 0 0 0 1 1 1.0625V 0 0 0 0 0 1 1 1.4625V 0 1 0 0 1 0 0 1.0500V 0 0 0 0 1 0 0 1.4500V 0 1 0 0 1 0 1 1.0375V 0 0 0 0 1 0 1 1.4375V 0 1 0 0 1 1 0 1.0250V 0 0 0 0 1 1 0 1.4250V 0 1 0 0 1 1 1 1.0125V 0 0 0 0 1 1 1 1.4125V 0 1 0 1 0 0 0 1.0000V 0 0 0 1 0 0 0 1.4000V 0 1 0 1 0 0 1 0.9875V 0 0 0 1 0 0 1 1.3875V 0 1 0 1 0 1 0 0.9750V 0 0 0 1 0 1 0 1.3750V 0 1 0 1 0 1 1 0.9625V 0 0 0 1 0 1 1 1.3625V 0 1 0 1 1 0 0 0.9500V 0 0 0 1 1 0 0 1.3500V 0 1 0 1 1 0 1 0.9375V 0 0 0 1 1 0 1 1.3375V 0 1 0 1 1 1 0 0.9250V 0 0 0 1 1 1 0 1.3250V 0 1 0 1 1 1 1 0.9125V 0 0 0 1 1 1 1 1.3125V 0 1 1 0 0 0 0 0.9000V 0 0 1 0 0 0 0 1.3000V 0 1 1 0 0 0 1 0.8875V 0 0 1 0 0 0 1 1.2875V 0 1 1 0 0 1 0 0.8750V 0 0 1 0 0 1 0 1.2750V 0 1 1 0 0 1 1 0.8625V 0 0 1 0 0 1 1 1.2625V 0 1 1 0 1 0 0 0.8500V 0 0 1 0 1 0 0 1.2500V 0 1 1 0 1 0 1 0.8375V 0 0 1 0 1 0 1 1.2375V 0 1 1 0 1 1 0 0.8250V 0 0 1 0 1 1 0 1.2250V 0 1 1 0 1 1 1 0.8125V 0 0 1 0 1 1 1 1.2125V 0 1 1 1 0 0 0 0.8000V 0 0 1 1 0 0 0 1.2000V 0 1 1 1 0 0 1 0.7875V 0 0 1 1 0 0 1 1.1875V 0 1 1 1 0 1 0 0.7750V 0 0 1 1 0 1 0 1.1750V 0 1 1 1 0 1 1 0.7625V 0 0 1 1 0 1 1 1.1625V 0 1 1 1 1 0 0 0.7500V 0 0 1 1 1 0 0 1.1500V 0 1 1 1 1 0 1 0.7375V 0 0 1 1 1 0 1 1.1375V 0 1 1 1 1 1 0 0.7250V 0 0 1 1 1 1 0 1.1250V 0 1 1 1 1 1 1 0.7125V 0 0 1 1 1 1 1 1.1125V 1 0 0 0 0 0 0 0.7000V 0 1 0 0 0 0 0 1.1000V 1 0 0 0 0 0 1 0.6875V Copyright © 2014 Richtek Technology Corporation. All rights reserved. DS8856-04 August 2014 is a registered trademark of Richtek Technology Corporation. www.richtek.com 3 RT8856 VID6 VID5 VID4 VID3 VID2 VID1 VID0 Output VID6 VID5 VID4 VID3 VID2 VID1 VID0 Output 1 0 0 0 0 1 0 0.6750V 1 1 0 0 0 0 1 0.2875V 1 0 0 0 0 1 1 0.6625V 1 1 0 0 0 1 0 0.2750V 1 0 0 0 1 0 0 0.6500V 1 1 0 0 0 1 1 0.2625V 1 0 0 0 1 0 1 0.6375V 1 1 0 0 1 0 0 0.2500V 1 0 0 0 1 1 0 0.6250V 1 1 0 0 1 0 1 0.2375V 1 0 0 0 1 1 1 0.6125V 1 1 0 0 1 1 0 0.2250V 1 0 0 1 0 0 0 0.6000V 1 1 0 0 1 1 1 0.2125V 1 0 0 1 0 0 1 0.5875V 1 1 0 1 0 0 0 0.2000V 1 0 0 1 0 1 0 0.5750V 1 1 0 1 0 0 1 0.1875V 1 0 0 1 0 1 1 0.5625V 1 1 0 1 0 1 0 0.1750V 1 0 0 1 1 0 0 0.5500V 1 1 0 1 0 1 1 0.1625V 1 0 0 1 1 0 1 0.5375V 1 1 0 1 1 0 0 0.1500V 1 0 0 1 1 1 0 0.5250V 1 1 0 1 1 0 1 0.1375V 1 0 0 1 1 1 1 0.5125V 1 1 0 1 1 1 0 0.1250V 1 0 1 0 0 0 0 0.5000V 1 1 0 1 1 1 1 0.1125V 1 0 1 0 0 0 1 0.4875V 1 1 1 0 0 0 0 0.1000V 1 0 1 0 0 1 0 0.4750V 1 1 1 0 0 0 1 0.0875V 1 0 1 0 0 1 1 0.4625V 1 1 1 0 0 1 0 0.0750V 1 0 1 0 1 0 0 0.4500V 1 1 1 0 0 1 1 0.0625V 1 0 1 0 1 0 1 0.4375V 1 1 1 0 1 0 0 0.0500V 1 0 1 0 1 1 0 0.4250V 1 1 1 0 1 0 1 0.0375V 1 0 1 0 1 1 1 0.4125V 1 1 1 0 1 1 0 0.0250V 1 0 1 1 0 0 0 0.4000V 1 1 1 0 1 1 1 0.0125V 1 0 1 1 0 0 1 0.3875V 1 1 1 1 0 0 0 0.0000V 1 0 1 1 0 1 0 0.3750V 1 1 1 1 0 0 1 0.0000V 1 0 1 1 0 1 1 0.3625V 1 1 1 1 0 1 0 0.0000V 1 0 1 1 1 0 0 0.3500V 1 1 1 1 0 1 1 0.0000V 1 0 1 1 1 0 1 0.3375V 1 1 1 1 1 0 0 0.0000V 1 0 1 1 1 1 0 0.3250V 1 1 1 1 1 0 1 0.0000V 1 0 1 1 1 1 1 0.3125V 1 1 1 1 1 1 0 0.0000V 1 1 0 0 0 0 0 0.3000V 1 1 1 1 1 1 1 0.0000V Copyright © 2014 Richtek Technology Corporation. All rights reserved. www.richtek.com 4 is a registered trademark of Richtek Technology Corporation. DS8856-04 August 2014 RT8856 Functional Pin Description Pin No. Pin Name 1 DPRSLPVR 2 VRON Voltage Regulator Enabler. 3 FS Frequency Setting. Connect this pin with a resistor to ground to set the operating frequency. 4 CM Current Monitor Output. This pin outputs a voltage proportional to the output current. 5 CMSET Pin Function Deeper Sleep Mode Signal. Together with PSI, the combination of these two pins indicates the power management states. Current Monitor Output Gain Externally Setting. Connect this pin with one resistor to VSEN while CM pin is connected to ground with another resistor. The current monitor output gain can be set by the ratio of these two resistors. 6 to 12 VID[6:0] Voltage ID. DAC voltage identification inputs for IMVP6.5. The logic threshold is 30% of VCCP as the maximum value for low state and 70% of VCCP as the minimum value for the high state. VCCP is 1.05V. Power Status Indicator II. Together with DPRSLPVR, the combination of these two 13 PSI 14 COMP Compensation. This pin is the output node of the error amplifier. 15 FB Feedback. This is the negative input node of the error amplifier. 16 VSEN 17 RGND pins indicates the power management states. Positive Voltage Sensing Pin. This pin is the positive node of the differential voltage sensing. Return Ground. This pin is the negative node of the differential remote voltage sensing. Soft-Start. This pin provides soft-start function and slew rate control. The capacitance of the slew rate control capacitor is restricted to be larger than 10nF. 18 SOFT The feedback voltage of the converter follows the ramping voltage on the SOFT pin during soft-start and other voltage transitions according to different modes of operation and VID change. 19 ISEN1 Positive Input of Phase1 Current Sense. 20 ISEN1_N Negative Input of Phase1 Current Sense. Bootstrap Power Pin of Phase1. This pin powers the high side MOSFET drivers. 21 BOOT1 Connect this pin to the junction of the bootstrap capacitor with the cathode of the bootstrap diode. Connect the anode of the bootstrap diode to the PVCC pin. 22 UGATE1 Upper Gate Drive of Phase1. This pin drives the gate of the high side MOSFETs. 23 PHASE1 24 PGND1 25 LGATE1 Lower Gate Drive of Phase1. This pin drives the gate of the low side MOSFETs. 26 PVCC Driver Power. 27 LGATE2 Lower Gate Drive of Phase2. This pin drives the gate of the low side MOSFETs. 28 PGND2 Driver Ground of Phase2. 29 PHASE2 Return Node of Phase2 High Side Driver. Connect this pin to high side MOSFET sources together with the low side MOSFET drains and the inductor. Return Node of Phase1 High Side Driver. Connect this pin to high side MOSFET sources together with the low side MOSFET drains and the inductor. Driver Ground of Phase1. Copyright © 2014 Richtek Technology Corporation. All rights reserved. DS8856-04 August 2014 is a registered trademark of Richtek Technology Corporation. www.richtek.com 5 RT8856 Pin No. 30 Pin Name UGATE2 Pin Function Upper Gate Drive of Phase2. This pin drives the gate of the high side MOSFETs. Bootstrap Power Pin of Phase2. This pin powers the high side MOSFET drivers. 31 BOOT2 Connect this pin to the junction of the bootstrap capacitor with the cathode of the bootstrap diode. Connect the anode of the bootstrap diode to the PVCC pin. 32 ISEN2_N 33 ISEN2 Negative Input of Phase2 Current Sense. Positive input of Phase2 Current Sense. Over Current Protection Setting. Connect a resistive voltage divider from VCC to 34 OCSET ground and connect the joint of the voltage divider to the OCSET pin. The voltage, VOCSET, determines the over current threshold, ILIM. Thermal Detection Input for VRTT Circuit. Connect this pin with a resistive 35 NTC voltage divider from VCC using NTC on the top to set the thermal management threshold level. 36 VRTT 37 TON 38 VCC 39 CLKEN 40 PGOOD 41 (Exposed Pad) Voltage Regulator Thermal Throttling. This open-drain output pin indicates the temperature exceeding the preset level when it is pulled low. Connect this pin to VIN with one resistor. This resistor value sets the ripple size in ringing free mode. Chip Power. Inverted Clock Enable. This open-drain pin is an output indicating the start of the GND PLL locking of the clock chip. Power Good Indicator. Ground. The exposed pad must be soldered to a large PCB and connected to GND for maximum power dissipation. Copyright © 2014 Richtek Technology Corporation. All rights reserved. www.richtek.com 6 is a registered trademark of Richtek Technology Corporation. DS8856-04 August 2014 Copyright © 2014 Richtek Technology Corporation. All rights reserved. DS8856-04 August 2014 VSEN COMP - - + - + - + PGOOD ERROR AMP UVP Trip Point + SOFT START MUX OVP Trip Point NVP Trip Point CLKEN FB DAC 1.2V - + VRTT SOFT RGND VID0 VID1 VID2 VID3 VID4 VID5 VID6 GND VCC NTC VCC Offset Cancellation + - + - PSI Mode Selection DPRSLPVR OTP Power On Reset & Central Logic VRON + OCP Setting OCSET - + - + CM PWMCP PWMCP Ringing Free Mode FB TON ONE_PHASE 1/2 Driver Logic Control OSC FS + 20 - + 20 - CM CMSET ISEN2_N ISEN2 ISEN1 ISEN1_N PGND2 LGATE2 PHASE2 UGATE2 PGND1 BOOT2 PHASE1 PVCC LGATE1 UGATE1 BOOT1 RT8856 Function Block Diagram is a registered trademark of Richtek Technology Corporation. www.richtek.com 7 RT8856 Absolute Maximum Ratings (Note 1) VCC to GND ------------------------------------------------------------------------------------------------ −0.3V to 6.5V RGND, PGNDx to GND ---------------------------------------------------------------------------------- −0.3V to 0.3V VIDx to GND ------------------------------------------------------------------------------------------------ −0.3V to (VCC + 0.3V) PSI, VRON to GND --------------------------------------------------------------------------------------- −0.3V to (VCC + 0.3V) PGOOD, CLKEN, VRTT to GND ----------------------------------------------------------------------- −0.3V to (VCC + 0.3V) VSEN, FB, COMP, SOFT, FS, OCSET, CM, CMSET, NTC to GND --------------------------- −0.3V to (VCC + 0.3V) ISENx, ISEN1_N, ISEN2_N to GND ----------------------------------------------------------------- −0.3V to (VCC + 0.3V) PVCC to PGNDx ------------------------------------------------------------------------------------------ −0.3V to 6.5V LGATEx to PGNDx --------------------------------------------------------------------------------------- −0.3V to (PVCC + 0.3V) PHASEx to PGNDx -------------------------------------------------------------------------------------- −3V to 28V BOOTx to PHASEx --------------------------------------------------------------------------------------- −0.3V to 6.5V UGATEx to PHASEx ------------------------------------------------------------------------------------- −0.3V to (BOOTx − PHASEx) PGOOD ------------------------------------------------------------------------------------------------------ −0.3V to (VCC + 0.3V) Power Dissipation, PD @ TA = 25°C WQFN−40L 6x6 -------------------------------------------------------------------------------------------- 2.941W Package Thermal Resistance (Note 2) WQFN-40L 6x6, θJA --------------------------------------------------------------------------------------- 34°C/W WQFN-40L 6x6, θJC -------------------------------------------------------------------------------------- 6°C/W Junction Temperature ------------------------------------------------------------------------------------- 150°C Lead Temperature (Soldering, 10 sec.) --------------------------------------------------------------- 260°C Storage Temperature Range ---------------------------------------------------------------------------- −65°C to 150°C ESD Susceptibility (Note 3) HBM (Human Body Mode) ------------------------------------------------------------------------------ 2kV MM (Machine Mode) -------------------------------------------------------------------------------------- 200V Recommended Operating Conditions (Note 4) Supply Voltage, VCC -------------------------------------------------------------------------------------- 4.5V to 5.5V Battery Voltage, VIN -------------------------------------------------------------------------------------- 7V to 24V Junction Temperature Range ---------------------------------------------------------------------------- −40°C to 125°C Ambient Temperature Range ---------------------------------------------------------------------------- −40°C to 85°C Electrical Characteristics (VCC = 5V, TA = 25°C, unless otherwise specified) Parameter Symbol Test Conditions Min Typ Max Unit Supply Input Supply Current I VCC + IPVCC RFS = 33k, VVRON = 3.3V, Not Switching -- -- 10 mA Shutdown Current I CC + IPVCC VVRON = 0V -- -- 5 A Soft-Start/Slew Rate Control (based on 10nF CSS) Soft-Start / Soft-Shutdown I SS1 VSOFT = 1.5V 16 20 24 A Deeper Sleep Exit/VID Change Slew Current VSOFT = 1.5V 80 100 120 A I SS2 Copyright © 2014 Richtek Technology Corporation. All rights reserved. www.richtek.com 8 is a registered trademark of Richtek Technology Corporation. DS8856-04 August 2014 RT8856 Parameter Symbol Test Conditions Min Typ Max Unit RFS = 33k, VDAC > 1.05 270 300 330 kHz RFS = 5k to 50k 20 -- 20 % Frequency Range Per phase 200 -- 1000 kHz Maximum Duty Cycle Per phase -- 50 -- % VFS RFS = 33k, VDAC > 1.05 1 1.05 1.1 V VFB VDAC = 0.7500 1.5000 (No Load, Active Mode ) VDAC = 0.5000 0.7500 0.8 0 0.8 %VID 7.5 0 7.5 mV 1.089 1.1 1.111 V RL = 47k 70 80 -- dB CLOAD = 5pF CLOAD = 10pF (Gain = 4, RF = 47k, VOUT = 0.5V 3V) RL = 47k -- 10 -- MHz -- 5 -- V/s 0.5 -- 3.6 V -- 250 -- A Oscillator Frequency Frequency f OSC Variation FS pin Output Voltage Reference and DAC DC Accuracy Boot Voltage VBOOT Error Amplifier DC Gain Gain-Bandwidth Product GBW Slew Rate SR Output Voltage Range VCOMP MAX Source/Sink Current IOUTEA VCOMP = 2V Current Sense Amplifier Input Offset Voltage VOSCS 1 -- 1 mV Impedance at Neg. Input RISENx_N 1 -- -- M Impedance at Pos. Input RISENx 1 -- -- M DC Gain AI -- 10 -- V/V Input Range VISENx_IN 50 -- 100 mV RFM TON Setting TON Pin Output Voltage VTON RTON = 80k, VTON = VDAC = 0.75V 5 0 5 % DEM ON-Time Setting tON IRTON = 80A -- 350 -- ns RTON Current Range IRTON 25 -- 280 A 4.1 4.3 4.5 V -- 200 -- mV Protection Under Voltage Lockout Threshold Under Voltage Lockout Threshold Hysteresis Absolute Over Voltage Protection Threshold Relative Over Voltage Protection Threshold VUVLO Falling edge VUVLO VOVABS (With respect to 1.5V, ±50mV) 1.45 1.5 1.55 V VOV (With respect to VVID, ±50mV) 150 200 250 mV 350 300 250 mV 100 -- -- mV Under Voltage Protection Threshold VUV Negative Voltage Protection Threshold VNV Measured at VSEN with respect to unloaded output voltage (UOV) (for 0.8 < UOV < 1.5) Measured at VSEN with respect to GND Copyright © 2014 Richtek Technology Corporation. All rights reserved. DS8856-04 August 2014 is a registered trademark of Richtek Technology Corporation. www.richtek.com 9 RT8856 Parameter Symbol Test Conditions Min Typ Max Unit Current Limit Threshold Voltage (Average) VILIM (VISENx VISENx_N) / N, VOCSET = 0.625V, VILIMT(nom) = 25mV 23 25 27 mV Current Limit Threshold Voltage (per phase) VILIM_PH VILIMITPH / VILIMIT -- 150 -- % Thermal Shutdown Threshold TSD -- 160 -- °C Thermal Shutdown Hysteresis TSD -- 10 -- °C Logic Inputs VRON Input Threshold Voltage Logic-High VIH With respect to 3.3V, 70% 2.31 -- -- Logic-Low With respect to 3.3V, 30% -- -- 0.99 1 -- 1 With respect to 1.1V, 70% 0.77 -- -- With respect to 1.1V, 30% -- -- 0.33 1 -- 1 A -- 1 -- V VIL Leakage Current of VRON DAC (VID0 VID6), Logic-High VIH PSI and DPRSLPVR Input Threshold Voltage Logic-Low VIL Leakage Current of DAC (VID0 VID6), PSI and DPRSLPVR V A V Power Good PGOOD Threshold VTH_PGOOD PGOOD Low Voltage VPGOOD I PGOOD = 4mA -- -- 0.4 V PGOOD Delay tPGOOD CLKEN Low to PGOOD High 3 -- 20 ms VCLKEN I CLKEN = 4mA -- -- 0.4 V Thermal Throttling Threshold VOT Measure at NTC with respect to VCC -- 80 -- %VDD Thermal Throttling Threshold Hysteresis VOT_HY At VCC = 5V -- 100 -- mV VRTT Output Voltage VVRTT I VRTT = 40mA -- -- 0.4 V 0.855 0.9 0.945 V -- -- 1.15 V Clock Enable CLKEN Low Voltage Thermal Throttling Current Monitor Current Monitor Maximum Output Voltage in Operating Range VDAC = 1V, VRCMSET = 90mV, RCM = 50k, RCMSET = 10k Current Monitor Maximum Output Voltage Gate Driver UGATE Driver Source RUGATEsr VBOOTx VPHASEx = 5V VBOOTx VUGATEx = 1V -- 0.7 -- UGATE Driver Sink RUGATEsk VUGATE = 1V -- 0.6 -- LGATE Driver Source RLGATEsr VPVCC = 5V, VPVCC VLGATE = 1V -- 0.7 -- LGATE Driver Sink RLGATEsk VLGATE = 1V -- 0.3 -- UGATE Driver Source/Sink Current IUGATE VBOOT VPHASE = 5V VUGATE = 2.5V -- 3 -- A LGATE Driver Source Current ILGATEsr VLGATE = 2.5V -- 3 -- A Copyright © 2014 Richtek Technology Corporation. All rights reserved. www.richtek.com 10 is a registered trademark of Richtek Technology Corporation. DS8856-04 August 2014 RT8856 Parameter LGATE Driver Sink Current Internal Boost Charging Switch On-Resistance Symbol Test Conditions Min Typ Max Unit ILGATEsk VLGATE = 2.5V -- 5 -- A RBOOT PVCC to BOOTx -- 30 -- Note 1. Stresses listed as the above “Absolute Maximum Ratings” may cause permanent damage to the device. These are for stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. Note 2. θJA is measured in natural convection at TA = 25°C on a high effective thermal conductivity four-layer test board of JEDEC 51-7 thermal measurement standard. The measured case position of θJC is on the exposed pad of the package. Note 3. Devices are ESD sensitive. Handling precaution is recommended. Note 4. The device is not guaranteed to function outside its operating conditions. Copyright © 2014 Richtek Technology Corporation. All rights reserved. DS8856-04 August 2014 is a registered trademark of Richtek Technology Corporation. www.richtek.com 11 RT8856 Typical Operating Characteristics CCM Efficiency vs. Load Current CCM Efficiency vs. Load Current 100 100 90 90 VIN = 8V VIN = 12V VIN = 19V 70 VIN = 8V VIN = 12V VIN = 19V 80 Efficiency (%) Efficiency (%) 80 60 50 40 30 20 70 60 50 40 30 20 VID = 1.15V, RFS = 33 kΩ, DPRSLPVR = GND, PSI = High 10 VID = 0.9375V, RFS = 33 kΩ, DPRSLPVR = GND, PSI = High 10 0 0 0 10 20 30 40 50 0 10 20 Load Current (A) 30 40 50 Load Current (A) DEM Efficiency vs. Load Current CCM VCC_SENSE vs. Load Current 1.16 95 90 1.14 VCC_SENSE (V) Efficiency (%) 85 VIN = 8V VIN = 12V VIN = 19V 80 75 70 65 1.12 VIN = 8V VIN = 12V VIN = 19V 1.1 1.08 60 1.06 VID = 0.85V, RFS = 33 kΩ, DPRSLPVR = GND, PSI = High 55 VID = 1.15V, RFS = 33 kΩ, DPRSLPVR = GND, PSI = High 1.04 50 0 0.5 1 1.5 2 2.5 0 3 10 Load Current (A) 20 30 40 50 Load Current (A) CCM VCC_SENSE vs. Load Current VCM vs. Load Current 1.1 0.96 1.0 0.9 0.8 0.92 VCM (mV) VCC_SENSE (V) 0.94 VIN = 8V VIN = 12V VIN = 19V 0.90 0.88 0.7 0.6 VIN = 8V VIN = 12V VIN = 19V 0.5 0.4 0.3 0.2 0.86 VID = 0.9375V, RFS = 33 kΩ, DPRSLPVR = GND, PSI = High 0.0 0.84 0 10 20 30 40 Load Current (A) Copyright © 2014 Richtek Technology Corporation. All rights reserved. www.richtek.com 12 VID = 0.9375V, RFS = 33 kΩ, DPRSLPVR = GND, PSI = High 0.1 50 0 10 20 30 40 50 Load Current (A) is a registered trademark of Richtek Technology Corporation. DS8856-04 August 2014 RT8856 Power On from VRON Power Off from VRON VIN = 12V, VID = 0.9375V VIN = 12V, VID = 0.9375V VCC SENSE (500mV/Div) PGOOD (1V/Div) VCC SENSE (500mV/Div) PGOOD (1V/Div) VRON (5V/Div) UGATE (20V/Div) VRON (5V/Div) UGATE (2V/Div) DPRSLPVR = GND, PSI = High, No Load DPRSLPVR = GND, PSI = High, No Load Time (1ms/Div) Time (1ms/Div) CCM VID Change Up CCM VID Change Down VIN = 12V, VID change from 0.85V to 0.9375V VIN = 12V, VID change from 0.9375V to 0.85V VCC SENSE (100mV/Div) VCC SENSE (100mV/Div) UGATE1 (20V/Div) UGATE1 (20V/Div) LGATE1 (1V/Div) VID0 (2V/Div) LGATE1 (5V/Div) VID0 (2V/Div) DPRSLPVR = GND, PSI = High, No Load DPRSLPVR = GND, PSI = High, No Load Time (20μs/Div) Time (20μs/Div) RFM VID Change Down CCM Load Transient Response VIN = 12V, VID change 0.9375V to 0.85V, DPRSLPVR = High, No Load VCC SENSE (100mV/Div) VIN = 12V, VID = 0.95V, ILOAD = 12A to 51A, DPRSLPVR = GND, PSI = High VCC SENSE (50mV/Div) UGATE1 (20V/Div) UGATE1 (20V/Div) LGATE1 (5V/Div) VID0 (2V/Div) LGATE1 (5V/Div) Time (40μs/Div) Copyright © 2014 Richtek Technology Corporation. All rights reserved. DS8856-04 August 2014 Time (4μs/Div) is a registered trademark of Richtek Technology Corporation. www.richtek.com 13 RT8856 CCM Load Transient Response Over Current Protection VIN = 12V, VID = 0.95V, ILOAD = 51A to 12A, VCC SENSE (50mV/Div) VCC SENSE (500mV/Div) PGOOD (1V/Div) UGATE1 (20V/Div) LGATE1 (5V/Div) DPRSLPVR = GND, PSI = High I LOAD (50A/Div) LGATE1 (10V/Div) Time (4μs/Div) Time (10μs/Div) Over Voltage Protection Under Voltage Protection VCC SENSE (1V/Div) VCC SENSE (1V/Div) PGOOD (2V/Div) UGATE1 (20V/Div) PGOOD (2V/Div) UGATE1 (20V/Div) LGATE1 (5V/Div) VIN = 12V, VID = 0.9375V, DPRSLPVR = GND Time (10μs/Div) Copyright © 2014 Richtek Technology Corporation. All rights reserved. www.richtek.com 14 VIN = 12V, VID = 0.9375V, DPRSLPVR = GND LGATE1 (5V/Div) VIN = 12V, VID = 0.9375V, DPRSLPVR = GND Time (10μs/Div) is a registered trademark of Richtek Technology Corporation. DS8856-04 August 2014 RT8856 Application Information The RT8856 is a 1/2-phase DC/DC controller and includes embedded gate drivers for reduced system cost and board area. The number of phases is not only user selectable, but also dynamically changeable based on Intel's IMVP6.5 control signals to optimize efficiency. Phase currents are continuously sensed for loop control, droop tuning, and over current protection. The internal 7-bit VID DAC and a low offset differential amplifier allow the controller to maintain high voltage regulating accuracy to meet Intel's IMVP6.5 specification. Design Tool To reduce the efforts and errors caused by manual calculations, a user friendly design tool is now available on request. This design tool calculates all necessary design parameters by entering user's requirements. Please contact Richtek's representatives for details. Phase Selection and Operation Modes The maximum number of operating phase is programmable by setting ISEN2_N. After the initial turn-on of the RT8856, an internal comparator checks the voltage at the ISEN2_N pin. To set the RT8856 as a pure single phase PWM controller, connect ISEN2_N to a voltage higher than (VCC - 1V) at power on. The controller will then disable phase 2 (hold UGATE2 and LGATE2 low) and operate as a single phase PWM controller. The RT8856 also works in conjunction with Intel's IIMVP6.5 control signals, such as PSI and DPRSLPVR. Table 2 shows the control signal truth table for operation modes of the RT8856. For high current demand, the controller will operate with both phases active. These two phase gate signals are interleaved. This achieves minimal output voltage ripple and best transient performance. For reduced current demand, only one phase is active. For 1-phase operation, the power stage can minimize switching losses and maintain transient response capability. At lowest current levels, the controller enters single phase Table 2. Control signal truth table for operation modes DPRSLPVR 0 0 PSI 1 0 1 1 1 0 Operation mode Multi-phase CCM Single-phase CCM S Single-phase RFM, slow C4E Single-phase RFM, slow C4E Differential Remote Sense Setting The RT8856 includes differential, remote sense inputs to eliminate the effects of voltage drops along the PC board traces, CPU internal power routes and socket contacts. The CPU contains on-die sense pin voltages, VCC_SENSE and VSS_SENSE. VSS_SENSE is connected to RGND pin. The VCC_SENSE is connected to FB pin with a resistor to build the negative input path of the error amplifier. Connect VSEN to VCC_SENSE for CLKEN, PGOOD, OVP, and UVP sense. The 7-bit VID DAC and the precision voltage reference are referred to RGND for accurate remote sensing. Current Sense Setting The RT8856 continuously sense the output current of each phase. Therefore, the controller can be less noise sensitive and get more accurate current sharing between phases. Low offset amplifiers are used for loop control and current limit. The internal current sense amplifier gain (AI) is fixed to be 10. The ISENx and ISENx_N denote the positive and negative input of the current sense amplifier of each phase, respectively. Users can either use a current-sense resistor or the inductor's DCR for current sensing. Using inductor's DCR allows higher efficiency as shown in Figure 1. If L R C X X DCR (1) then the current sense performance will be optimum. For example, choosing L = 0.36μH with 1mΩ DCR and CX = 100nF, yields RX : RX 0.36H 3.6k 1.0m 100nF (2) Ringing-Free Mode (RFM) to achieve highest efficiency. Copyright © 2014 Richtek Technology Corporation. All rights reserved. DS8856-04 August 2014 is a registered trademark of Richtek Technology Corporation. www.richtek.com 15 RT8856 V OUT L DCR PHASEx CX RX + VX - ISENx ISENx_N C BYPASS Figure 1. Lossless Inductor Sensing Since the inductance tolerances are normally observed to be 20%, the resistor, RX, has to be tuned on board by examining the transient voltage. If the output voltage transient has an initial dip below the minimum load line requirement with a slow recovery, RX is chosen too small. Vice versa, with a resistance too large, the output voltage transient has only a small initial dip and the recovery is too fast, thus causing a ring-back. Using current sense resistor in series with the inductor can have better accuracy, but the efficiency is a trade-off. Considering the equivalent inductance (LESL) of the current sense resistor, an RC filter is recommended. The RC filter calculation method is similar to the above-mentioned inductor DCR sensing method . Loop Control Similar to the peak current mode control with finite compensator gain, the HS_FET on-time is determined by both the internal clock and the PWM comparator which compares the EA output with the output of current sense amplifier. When load current increases, VCS increases, the steady state COMP voltage also increases and makes the VOUT decrease, hence achieving AVP. A near-DC offset (VOFS) is added to the output EA to cancel the inherent output offset of finite-gain peak current mode controller. In RFM, HS_FET is turned on with constant TON when VCS is lower than VCOMP2. Once the HS_FET is turned off, LS_FET is turned on automatically. By Ringing-Free Technique, the LS_FET allows only partial of negative current when the inductor free-wheeling current reaches negative. The switching frequency will be proportionately reduced, thus the conduction and switching losses will be greatly reduced. Droop Setting (with Temperature Compensation) It's very easy to achieve Active Voltage Positioning (AVP) by properly setting the error amplifier gain with respect to the native droop characteristics. The target is to have Equation (3) VOUT = VSOFT − ILOAD x RDROOP (3) TM The RT8856 adopts Richtek's proprietary NAVP topology. NAVPTM is based on the finite-gain peak current mode PWM topology. The output voltage, VOUT, will decrease with increasing output load current. The control loop consists of PWM modulator with power stage, current sense amplifier and error amplifier as shown in Figure 2. VIN RT8856 S Clock UGATEx PWM Logic R HS_FET RX LGATEx L VOUT CX RC LS_FET + CMP COMP2 VCS AI + - + - EA + VDAC VOFS V OUT A V2 > A V1 C2 R2 C1 R1 VCC_SENSE FB A V2 SOFT RGND A V1 CSOFT VSS_SENSE Figure 2. Simplified Schematic for Droop and Remote Sense in CCM Copyright © 2014 Richtek Technology Corporation. All rights reserved. www.richtek.com 16 where AI is the internal current sense amplifier gain. RSENSE is the current sense resistor. If there is no external sense resistor, it is the DCR of the inductor. RDROOP is the resistive slope value of the converter output and is the desired static output impedance, e.g. −1.9mΩ or −3mΩ for IMVP6.5 specification. Increasing AV can make load line more shallow as shown in Figure 3. C ISENx ISENx_N COMP then solving the switching condition VCOMP2 = VCS in Figure 2 yields the desired error amplifier gain as A RSENSE (4) A V R2 I R1 RDROOP 0 Load Current Figure 3. Error Amplifier Gain (AV) Influence on VOUT Accuracy is a registered trademark of Richtek Technology Corporation. DS8856-04 August 2014 RT8856 Since the DCR of inductor is highly temperature dependent, it affects the output accuracy at hot conditions. Temperature compensation is recommended for the lossless inductor DCR current sense method. Figure 4 shows a simple but effective way of compensating the temperature variations of the sense resistor using an NTC thermistor placed in the feedback path. C2 RT8856 R2 COMP C1 R1b FB + - EA + VDAC R1a VCC_SENSE NTC CSOFT 10nF RGND 25 x (R1b + R1a // RNTC, 25) where AV, 25 is the error amplifier gain at room temperature and can be obtained from Equation (4). R1b can be obtained by substituting Equation (9) to (5), R1b RSENSE, HOT (R1a // RNTC, HOT ) (R1a // RNTC, HOT ) RSENSE, COLD (5) From Equation (4), Av can be obtained at any temperature (T) as shown below : R2 R1a // RNTC, T R1b (6) The standard formula for the resistance of NTC thermistor as a function of temperature compensation is given by : 1 1 298 T+273 (7) where R25 is the thermistor's nominal resistance at room temperature, β (beta) is the thermistor's material constant in Kelvins, and T is the thermistor's actual temperature in Celsius. To calculate DCR value at different temperature, use the equation below : DCRT = DCR25 x [1 + 0.00393 x (T − 25)] Copyright © 2014 Richtek Technology Corporation. All rights reserved. DS8856-04 August 2014 (10) VSS_SENSE A V, HOT RSENSE, HOT A V, COLD RSENSE, COLD (9) RSENSE, HOT 1 R SENSE, COLD Usually, R1a is set to equal RNTC (25°C). R1b is selected to linearize the NTC's temperature characteristic. For a given NTC, design is to get R1b and R2 and then C1 and C2. According to Equation (4), to compensate the temperature variations of the sense resistor, the error amplifier gain (AV) should have the same temperature coefficient with RSENSE. Hence, RNTC, T R25 e R2 = AV, SOFT Figure 4. Loop Setting with Temperature Compensation A V, T where the 0.00393 is the temperature coefficient of the copper. For a given NTC thermistor, solving Equation (6) at room temperature (25°C) yields Loop Compensation Optimized compensation of the RT8856 allows for best possible load step response of the regulator's output. A type-II compensator with one pole and one zero is adequate for a proper compensation. Figure 4 shows the compensation circuit. Prior design procedure shows how to select the resistive feedback components for the error amplifier gain. Next, the C1 and C2 must be calculated for the compensation. The target is to achieve constant resistive output impedance over the widest possible frequency range. The pole frequency of the compensator must be set to compensate the output capacitor ESR zero : 1 2 C RC fP (11) where C is the capacitance of output capacitor, and RC is the ESR of output capacitor. C2 can be calculated as follows : C2 C RC R2 (12) The zero of compensator has to be placed at half of the switching frequency to filter the switching related noise. such that, C1 1 (13) R1b R1a // RNTC, 25 fSW (8) is a registered trademark of Richtek Technology Corporation. www.richtek.com 17 RT8856 Frequency Setting Power Up Sequence High frequency operation optimizes the application for smaller component size, but trads off efficiency due to higher switching losses. This may be acceptable in ultraportable devices where the load currents are lower and the controller is powered from a lower voltage supply. Low frequency operation offers the best overall efficiency at the expense of component size and board space. With the controller's VCC voltage above the POR threshold (typ. 4.3V), the power-up sequence begins when VRON exceeds the 3.3V logic high threshold. Approximately 20μs later, SOFT and VCORE starts ramping up to boot voltage (1.1V) with maximum phases. The slew rate during power-up is 20μA/CSOFT. The RT8856 pulls CLKEN low after VVSEN rises above 1V for 73μs. Right after CLKEN goes low, SOFT and VCORE starts ramping to first DAC value. After CLKEN goes low for approximate 4.7ms, PGOOD is asserted HIGH. DPRSLPVR and PSI are valid right after PGOOD is asserted. UVP is masked as long as VSOFT is less than 1V. Connect a resistor (RFS) between FS and ground to set the switching frequency (fSW) per phase : RFS (k ) 300(kHz) 33(k ) fSW (kHz) (14) A resistor of 5kΩ to 50kΩ corresponds to switching frequency of 1MHz to 200kHz, respectively. VCC 4.3V 4.1V POR VRON Soft-Start and Mode Change Slew Rates VID The RT8856 uses 2 slew rates for various modes of operation. These two slew rates are internally determined by commanding one of two bi-directional current sources on to the SOFT pin (ISS). The 7-bit VID DAC and the precision voltage reference are referred to RGND for accurate remote sensing. Hence, connect a capacitor (CSOFT) from SOFT pin to RGND for controlling the slew rate as shown in Figure 4. The capacitance of capacitor is restricted to be larger than 10nF. The voltage on SOFT pin (VSOFT) is higher than the reference voltage of the error amplifier at about 0.9V. The first current of typically 20μA is used to charge or discharge the CSOFT during soft-start, soft-shutdown. The second current of typically 100μA is used during other voltage transitions, including VID change and transitions between operation modes. The IMVP6.5 specification specifies the critical timing associated with regulating the output voltage. The symbol, SLEWRATE, as given in the IMVP6.5 specification will determine the choice of the SOFT capacitor, CSOFT, by the following equation : CSOFT (nF) ISS (A) SLEWRATE(mV / s) Copyright © 2014 Richtek Technology Corporation. All rights reserved. www.richtek.com 18 (15) XX 1V 1.1V VCORE PWM x x Valid 0.2V DPRSLPVR/PSI Defined Hi-Z MAX Phases MAX Phases Pull Low DPRSLPVR XX Valid XX PSI XX Valid XX CLKEN PGOOD 73µs typ. 4.7ms typ. Figure 5. Timing Diagram for Power-Up and Power-Down Power Down When VRON goes low, the RT8856 enters low-power shutdown mode. PGOOD is pulled low immediately and VSOFT ramps down with slew rate of 20μA/CSOFT. VVSEN also ramps down following VSOFT with maximum phases. After VVSEN falls below 200mV, the RT8856 turns off both high side and low side MOSFETs. A discharging resistor at VSEN will be enabled and the analog part will be turned off. Deeper Sleep Mode Transitions After DPRSLPVR goes high, the RT8856 immediately disables phase 2 (UGATE2 and LGATE2 forced low) and enters 1-phase deeper sleep mode operation. If the VIDs are set to a lower voltage setting, the output drops at a rate determined by the load and the output capacitance. The internal target VSOFT still ramps as before, and UVP, OCP and OVP are masked for 73μs. is a registered trademark of Richtek Technology Corporation. DS8856-04 August 2014 RT8856 The RT8856 provides 2 slew rates for deeper sleep mode entry/ exit. For standard deeper sleep exit, the RT8856 immediately activates all enabled phases and ramps the output voltage to the DAC code provided by the processor at the slew rate of 100μA/CSOFT. The RT8856 remains in 1-phase ringing free mode and ramps the output voltage to the DAC code provided by the processor at the slew rate of 20μA/CSOFT. temperature compensation is recommended to protect under all conditions. Figure 7 shows a typical OCP setting with temperature compensation. V CC RT8856 R OC1a NTC R OC1b OCSET Current Limit Setting R OC2 The RT8856 compares a programmable current limit set point to the voltage from the current sense amplifier output for Over Current Protection (OCP). The voltage applied to OCSET pin defines the desired current limit threshold, ILIM : VOCSET = 25 x ILIM x RSENSE (16) Connect a resistive voltage divider from VCC to GND, with the joint of the voltage divider connected to OCSET pin as shown in Figure 6. For a given ROC2, VCC ROC1 ROC2 1 V OCSET RT8856 (17) V CC Figure 7. OCP Setting with Temperature Compensation Usually, select R OC1a equal to thermistor's nominal resistance at room temperature. Ideally, VOCSET should have same temperature coefficient as RSENSE (Inductor DCR) : VOCSET, HOT RSENSE, HOT (18) VOCSET, COLD RSENSE, COLD According to the basic circuit calculation, VOCSET can be obtained at any temperature : ROC2 (19) VOCSET, T ROC1a // RNTC, T ROC1b ROC2 R OC1 Re-write Equation (18) from (19), and get VOCSET at room temperature R OC2 ROC1a // RNTC, COLD ROC1b ROC2 RSENSE, HOT ROC1a // RNTC, HOT ROC1b ROC2 RSENSE, COLD OCSET Figure 6. OCP Setting Without Temperature Compensation (20) VOCSET, 25 ROC2 ROC1a // RNTC, 25 ROC1b ROC2 (21) The OCP works in two stages : Stage 1 : Average inductor current exceeds the current limit threshold, ILIM, defined by VOCSET, but remains smaller than 150% of ILIM If the over current condition remains valid for 16 cycles, the OCP latches and the system shuts down. Stage 2 : Any inductor current exceeds 150% of ILIM then OCP latches instantaneously. Latched OCP forces driver high impedance with UGATEx = 0 and LGATEx = 0. After latched OCP happens, VVSEN will be monitored. When VVSEN falls below 200mV, a discharging resistor at VSEN will be enabled. Solving Equation (20) and (21) yields ROC1b and ROC2 ROC2 REQU, HOT REQU, COLD (1 ) REQU, 25 VCC (1 ) VOCSET, 25 ROC1b ( 1) ROC2 REQU, HOT REQU, COLD (1 ) DS8856-04 August 2014 (23) where RSENSE, HOT DCR25 [1 0.00393 (THOT 25)] RSENSE, COLD DCR25 [1 0.00393 (TCOLD 25)] (24) If inductor DCR is used as current sense component, then Copyright © 2014 Richtek Technology Corporation. All rights reserved. (22) is a registered trademark of Richtek Technology Corporation. www.richtek.com 19 RT8856 REQU, T = R1a // RNTC, T (25) Over Temperature Protection (OTP) ROC2 = 2.437kΩ, ROC1b = 7.113kΩ Over Temperature Protection prevents the VR from damage. OTP is considered to be the final protection stage against overheating of the VR. The thermal throttling VRTT should be set to assert prior to OTP to manage the VR power. When this measure is insufficient to keep the die temperature of the controller below the OTP threshold, OTP will be asserted and latched. The die temperature of the controller is monitored internally by a temperature sensor. As a result of OTP triggering, a soft shutdown will be launched and VVSEN will be monitored. When VVSEN is less than 200mV, the driver remains in high impedance state and the discharging resistor at VSEN pin will be enabled. A reset can be executed by cycling VCC or VRON. Over Voltage Protection (OVP) Thermal Throttling Control The OVP circuit is triggered under two conditions : Intel IMVP6.5 technology supports thermal throttling of the processor to prevent catastrophic thermal damage. The RT8856 includes a thermal monitoring circuit to detect an exceeded user defined temperature on a VR point. The thermal monitoring circuit senses the voltage change across the NTC pin. Figure 8 shows the principle of setting the temperature threshold. Connect an external resistive voltage divider between Vcc and GND. This divider uses a Negative Temperature Coefficient (NTC) thermistor and a resistor. The joint of the voltage divider is connected to the NTC pin in order to generate a voltage that is proportional to the temperature. The RT8856 pulls VRTT low if the voltage on the NTC pin is greater than 0.8 x VCC. The internal VRTT comparator has a hysteresis of 100mV to prevent high frequency VRTT oscillation when the temperature is near the setting point. The minimum assertion/de-assertion time for VRTT toggling is 1.5ms. For example, the following design parameters are given : DCR =1mΩ, VCC = 5V, IL, Ripple = 5A ROC1a = RNTC, 25 = 10kΩ, βNTC = 2400 For −20°C to 100°C operation range, to set OCP trip current ITRIP = 57A when operating with maximum phases : ILIM 57A 5A 33.5A 2 VOCSET, 25 25 33.5A 1m 0.8375V RNTC, −20 =41.89kΩ, RNTC, 100 = 1.98kΩ RSENSE, −20 =0.82 mΩ, RSENSE, 100 =1.29mΩ Condition 1 : When VVSEN exceeds 1.55V. Condition 2 : When VVSEN exceeds VDAC by 200mV. If either condition is valid, the RT8856 latches the LGATEx =1 and UGATEx = 0 as crowbar to the output voltage of VR. Turning on all LS_FETs can lead to very large reverse inductor current and potentially result in negative output voltage of VR. To prevent damage of the CPU by negative voltage, the RT8856 turns off all LS_FETs when VVSEN has fallen below −100mV. Under Voltage Protection (UVP) If VVSEN is less than VDAC by 300mV or more, a UVP fault is latched and the RT8856 turns off both upper side and lower side MOSFETs. VVSEN is monitored after UVP is valid. When VVSEN falls below 200mV, a discharging resistor at VSEN will be enabled. RT8856 Negative Voltage Protection (NVP) During shutdown or protection state, when VVSEN is lower than −100mV, the controller will force LGATEx = 0 and UGATEx = 0 for preventing negative voltage. Once VVSEN recovers to be more than 0mV, NVP will be suspended and LGATEx = 1 will be enabled again. VRTT V CC R OC1b + CMP - NTC R OC2 0.8 x V CC Figure 8. Thermal Throttling Setting Principle Copyright © 2014 Richtek Technology Corporation. All rights reserved. www.richtek.com 20 is a registered trademark of Richtek Technology Corporation. DS8856-04 August 2014 RT8856 Users can use the same NTC thermistor for both thermal throttling and current limit setting as shown in Figure 9. Just divide the ROC1b into RTTa and RTTb, and write the VNTC equation at thermal throttling temperature TT°C : RTTa + RTTb = ROC1b (26) ROC2 RTTb VCC ROC2 ROC1b ROC1a // RNTC, TTC 0.8 VCC (27) Solving (26) and (27) for RTTa and RTTb as : RTTb = 4 x (ROC1a // RNTC, TT°C )−ROC2 (28) RTTa = ROC1b − RTTb (29) RT8856 VRTT V CC Inductor Selection The switching frequency and ripple current determine the inductor value as follows : LMIN N VOUT(MIN) (1 DMIN ) fSW IRipple (31) where N is the total number of phases. DMIN is the minimum duty at highest input voltage VIN. Higher inductance yields in less ripple current and hence in higher efficiency. The flaw is the slower transient response of the power stage to load transients. This might increase the need for more output capacitors driving the cost up. Find a low loss inductor having the lowest possible DC resistance that fits in the allotted dimensions. The core must be large enough not to saturate at the peak inductor current. Output Capacitor Selection R OC1a NTC R OC1b + CMP - NTC R OC2 0.8 x V CC Figure 9. Using single NTC Thermistor for Thermal Throttling and Current Limit Setting Current Monitor The current monitor allows the system to accurately monitor the CPU's current dissipation and quickly predict whether the system is about to overheat before the significantly slower temperature sensor signals an over temperature alert. The voltage output of CM pin is proportional to the output current. This pin is connected to ground with one resistor while CMSET pin is connected to VVSEN with another resistor. By choosing the appropriate ratio of these two resistors, current monitor gain can be set and VCM will be 1V with maximum output current. Maximum value of VCM is clamped at 1.15V. VCM ILOAD RDROOP 2 R RCM CMSET Copyright © 2014 Richtek Technology Corporation. All rights reserved. DS8856-04 August 2014 (30) Output capacitors are used to obtain high bandwidth for the output voltage beyond the bandwidth of the converter itself. Usually, the CPU manufacturer recommends a capacitor configuration. Two different kinds of output capacitors can be found, bulk capacitors closely located to the inductors and ceramic output capacitors in close proximity to the load. The latter ones are for mid frequency decoupling with especially small ESR and ESL values while the bulk capacitors have to provide enough stored energy to overcome the low frequency bandwidth gap between the regulator and the CPU. Thermal Considerations For continuous operation, do not exceed absolute maximum junction temperature. The maximum power dissipation depends on the thermal resistance of the IC package, PCB layout, rate of surrounding airflow, and difference between junction and ambient temperature. The maximum power dissipation can be calculated by the following formula : PD(MAX) = (TJ(MAX) − TA) / θJA where TJ(MAX) is the maximum junction temperature, TA is the ambient temperature, and θJA is the junction to ambient thermal resistance. is a registered trademark of Richtek Technology Corporation. www.richtek.com 21 RT8856 For recommended operating condition specifications of RT8856, the maximum junction temperature is 125°C and TA is the ambient temperature. The junction to ambient thermal resistance, θ JA , is layout dependent. For WQFN-40L 6x6 packages, the thermal resistance, θJA, is 34°C/W on a standard JEDEC 51-7 four-layer thermal test board. The maximum power dissipation at TA = 25°C can be calculated by the following formula : PD(MAX) = (125°C − 25°C) / (34°C/W) = 2.941W for WQFN-40L 6x6 package The maximum power dissipation depends on the operating ambient temperature for fixed T J(MAX) and thermal resistance, θJA. For RT8856 package, the derating curve in Figure 10 allows the designer to see the effect of rising ambient temperature on the maximum power dissipation. Layout Considerations Careful PC board layout is critical to achieve low switching losses and clean, stable operation. The switching power stage requires particular attention. If possible, mount all of the power components on the top side of the board with their ground terminals flush against one another. Follow these guidelines for optimum PC board layout : Keep the high current paths short, especially at the ground terminals. Keep the power traces and load connections short. This is essential for high efficiency. Connect slew rate control capacitor at SOFT pin to RGND. When trade offs in trace lengths must be made, it's preferable to allow the inductor charging path to be made longer than the discharging path. Place the current sense component close to the controller. ISENx and ISENx_N connections for current limit and voltage positioning must be made using Kelvin sense connections to guarantee the current sense accuracy. PCB trace from the sense nodes should be paralleled back to controller. Route high speed switching nodes away from sensitive analog areas (SOFT, COMP, FB, VSEN, ISENx, ISENx_N, CM, CMSET, etc...) Maximum Power Dissipation (W)1 3.2 Four Layers PCB 2.8 2.4 2.0 1.6 1.2 0.8 0.4 0.0 0 25 50 75 100 125 Ambient Temperature (°C) Figure 10. Derating Curves for RT8856 Packages Copyright © 2014 Richtek Technology Corporation. All rights reserved. www.richtek.com 22 is a registered trademark of Richtek Technology Corporation. DS8856-04 August 2014 RT8856 Outline Dimension 1 1 2 2 DETAIL A Pin #1 ID and Tie Bar Mark Options Note : The configuration of the Pin #1 identifier is optional, but must be located within the zone indicated. Symbol Dimensions In Millimeters Dimensions In Inches Min. Max. Min. Max. A 0.700 0.800 0.028 0.031 A1 0.000 0.050 0.000 0.002 A3 0.175 0.250 0.007 0.010 b 0.180 0.300 0.007 0.012 D 5.950 6.050 0.234 0.238 Option1 4.000 4.750 0.157 0.187 Option2 3.470 3.570 0.137 0.141 5.950 6.050 0.234 0.238 Option1 4.000 4.750 0.157 0.187 Option2 2.570 2.670 0.101 0.105 D2 E E2 e L 0.500 0.350 0.020 0.450 0.014 0.018 W-Type 40L QFN 6x6 Package Copyright © 2014 Richtek Technology Corporation. All rights reserved. DS8856-04 August 2014 is a registered trademark of Richtek Technology Corporation. www.richtek.com 23 RT8856 Richtek Technology Corporation 14F, No. 8, Tai Yuen 1st Street, Chupei City Hsinchu, Taiwan, R.O.C. Tel: (8863)5526789 Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries. www.richtek.com 24 DS8856-04 August 2014 www.s-manuals.com
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