RT9913A, RT9913B Datasheet. Www.s Manuals.com. Richtek

User Manual: Marking of electronic components, SMD Codes B0, B0*, B0**, B0-**, B0-***, B0=***. Datasheets ELM9710NBA, RT9011-FSPJ6, RT9011-JPPQV, RT9011-PMPQWC, RT9013-31PU5, RT9013A-28GY, RT9014A-PPPQV, RT9913BPQV, SST5460.

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Preliminary

RT9913A/B

Integrated Multi-Channel DC-DC Converter for
TFT LCD Panels
General Description

Features

The RT9913A/B includes a high-performance boost
regulator, one linear-regulator controller for VGL, one low
dropout linear regulator, a gate pulse modulator (GPM), a
voltage detector and a VCOM Buffer (Unity- gain OPA) for

2.5V to 5.5V Input Supply Voltage

640kHz/1.2MHz (A/B version) Current-Mode Step-Up
Boost Regulator
Fast Transient Response to Pulsed Load
High Accuracy Output Voltage (±2%)
Built-In 16V, 2.0A, 0.2Ω
Ω N-Channel MOSFET
High Efficiency Up to 90%
Programmable Soft-Start
Programmable Over-Current Protection
Linear-Regulator Controller for VGL
Low Drop-Out Voltage Linear Regulator
Adjustable Output Voltage (2.5V to 3.3V)
350mA Maximum Output Current
On-Chip GPM Controller with Adjustable Falling
Time
Flicker Compensator
Power-On Sequence Control
Low Voltage Detector
Programmable Detecting Voltage and Delay Time
Unity-Gain Operation Amplifier for VCOM Buffer
Over-Temperature Protection
Thin 24-Lead VQFN Package
RoHS Compliant and 100% Lead (Pb)-Free

active-matrix thin-film transistor (TFT) liquid-crystal displays
(LCDs).
The boost converter provides the regulated supply voltage
for the panel source driver ICs. With integrated 16V
N-Channel 0.2Ω MOSFET it allows the use of ultra-small
inductors and ceramic capacitors and provides fast transient
response to pulsed loads. The VGL linear-regulator
controller provides regulated TFT Gate-Off . The low-dropout
linear regulator (LDO) using an internal PMOS as the pass
device can supply up to 350mA current is suitable for the
supply voltage to the T-CON ASIC. And the GPM is
controlled by frame signals from timing controller to
modulate the Gate-On voltage. Voltage detector monitors
the supply voltage to issue a reset signal while the
detected voltage is too low. The VCOM Buffer (Unity-gain)
high-performance operation amplifier) can drive the LCD
backplane (VCOM) and features high short-circuit current
(140mA), fast slew rate (12V/μs), wide bandwidth (12MHz)
and rail-to-rail input and output.

Ordering Information
RT9913A/B
Package Type
QV : VQFN-24L 4x4 (V-Type)

z
z

z
z
z
z

Marking Information
For marking information, contact our sales representative
directly or through a RichTek distributor located in your
area, otherwise visit our website for detail.

Operating Temperature Range
P : Pb Free with Commercial Standard
Switching Frequency
A : 640kHz
B : 1.2MHz
Note :
RichTek Pb-free products are :
`RoHS compliant and compatible with the current requirements of IPC/JEDEC J-STD-020.
`Suitable for use in SnPb or Pb-free soldering processes.
`100% matte tin (Sn) plating.

DS9913A/B-00 February 2006

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1

RT9913A/B

Preliminary

Pin Configurations
OPAI

OPAO

AVDD

PGND

(TOP VIEW)

VFLK

VGH

VIN

VGHM

COMP

VREF

LDOI

FBN

LDOO

AGND

ADJ

DRVN

VDIV

RESET

GND

VQFN-24L 4x4

Typical Application Circuit
D4
BAT54S

Q1
MMBT3904

VGL
-6V

C11
0.1uF
VIN
3.3V

C13
C12
0.1uF

0.22uF

C1
10uF
R9
240k

R8
6.8k

RSET

Chip Enable

17
VIN

VLDO
VDIN
R6
65k
R7
110k

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2

COMP

RESET
VAVDD

R3
56k

RT9913
VREF

VGH 2
VGHM 3

C10
0.1uF
VFLK

RE 4
1

VAVDD
8.5V

FB 20

FBN

CCOMP

C14
0.22uF

D1 SS12

RGH
30k

R1
330k

DRVN

C4
27nF
5

C8
0.1uF

C7
0.1uF

D2
BAT54S
LX 18

15 SS
R10
50k

L1
4.7uH

19 EN
7

C6
0.1uF
D3 BAT54S

C5
0.1uF

OPAO

VFLK

R14
100k

C2
4.7uF x 3

R2
56k
C3
1nF

VGHM
C15 25V
1.5nF

R11
1.2k

VAVDD

VCOM_OUT
VCOM_IN

9 RESET

OPAI
14
LDOI
LDOO

22 AVDD
10 VDIV

ADJ

AGND

PGND

C16
1uF

13
R4
56k

12
R5
56k

VIN
3.3V

R12
56k
R13
56k

VLDO
2.5V
C9
1uF

DS9913A/B-00 February 2006

Preliminary

RT9913A/B

Functional Pin Description
Pin Number Pin Name Pin Function
1

VFLK

VFLK is produced by timing controller for charging or discharging VGHM.

VGH

Switch input for charge VGHM

VGHM

VGHM is the supply voltage for the gate driver ICs.

Switch input for discharge VGHM

VREF

Internal Reference Bypass Terminal. Connect a 0.22uF ceramic capacitor from the VREF
to analog ground (AGND). The source capability is 100uA.
Negative Linear-Regulator Feedback Input. Connect FBN to the center of a resistive

FBN

voltage-divider between the negative output voltage VGL and the VREF to set the
negative linear-regulator output voltage. Place the resistive voltage-divider close to the
pin.
Negative Linear-Regulator Base Drive. Open drain of an internal PMOS. Connect DRVN

DRVN

Pin for external capacitor setting the delay time for voltage detector reset delay time.

RESET

Voltage Detector open-drain Output for Reset.

VDIV

AGND

to the base of the external linear-regulator NPN pass transistor.

Voltage Detector Divider Input. Connect VDIV to the center of a resistive voltage-divider
between the detected voltage input (VDIN) and analog ground (AGND).
Analog Ground.
Low-Dropout Linear Regulator (LDO) Feedback Input. ADJ regulates to 1.24V nominal.
Connect ADJ to the center of a resistive voltage-divider between the LDO output voltage

ADJ

LDOO

Voltage Output of the LDO.

LDOI

Voltage Input of the LDO.

Soft-Start Control Pin. Connect a soft-start capacitor (CSS) to this pin. The soft-start
capacitor is charged with a constant current 4uA.

COMP

Compensation Error Amplifier Pin. Connect a compensation network to ground.

VIN

Switching pin. Drain of the internal power NMOS for the main step-up regulator.

Active-High Enable Control Input and OCP level setting.

LDOO and the analog ground (AGND) the LDO output voltage. Place the resistive
voltage-divider close to the pin.

Supply Input. The supply voltage powers all the control circuits including the boost
converter, negative linear-regulator, gate pulse regulator and voltage detector.

Main Boost Regulator Feedback Input. FB regulates to 1.24V nominal. Connect FB to the
20

center of a resistive voltage-divider between the main output AVDD and the analog
ground (AGND) the boost regulator output voltage. Place the resistive voltage-divider
close to the pin.

PGND

Power Ground. PGND is the source of the power NMOS.

AVDD

VDD for Source Driver Power. It also supplies OP power and GPM level shift voltage.

OPAO

Unit-Gain OPA Output Pin.

OPAI

Unit-Gain OPA Input Pin.

Exposed Pad GND

Exposed pad should be soldered to PCB board and connected to GND.

DS9913A/B-00 February 2006

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3

RT9913A/B

Preliminary

Function Block Diagram
SS EN VIN
VIN
LX

VDIV

Voltage
Detector

PGND

Boost
Regulator

RESET

COMP

LDOI
LDOO
ADJ

VIN

LDO

VGHM
RE
GPM

AVDD
VGH
VFLK

1.24V
Voltage
Reference

VREF
FBN

AGND

OPAO
OPAI

+
-

DRVN

Boost Regulator Block Diagram

VIN
4uA
SoftStart
Protection

COMP
FB

1.24V

Oscillator

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4

Error
Amplifier

Slope
Compensation

Summing
Comparator
+
-

Clock

Control
and
Driver
Logic

PGND

Current
Sense

DS9913A/B-00 February 2006

RT9913A/B

Preliminary
Absolute Maximum Ratings
z
z
z
z
z
z
z
z
z
z
z

z
z
z
z

(Note 1)

Supply Input Voltage, VIN ----------------------------------------------------------------------------------VGH-AVDD, VGHM-AVDD ---------------------------------------------------------------------------------LX ---------------------------------------------------------------------------------------------------------------VGH, VGHM RE ---------------------------------------------------------------------------------------------AVDD -----------------------------------------------------------------------------------------------------------OPAI, OPAO --------------------------------------------------------------------------------------------------DRVN -----------------------------------------------------------------------------------------------------------VFLK, VREF, FBN, CD, RESET_, VDIV, SS, COMP, EN, FB -----------------------------------LDOI ------------------------------------------------------------------------------------------------------------ADJ, LDOO ---------------------------------------------------------------------------------------------------Power Dissipation, PD @ TA = 25°C
VQFN-24L 4x4 -----------------------------------------------------------------------------------------------Package Thermal Resistance (Note 4)
VQFN-24L 4x4, θJA ------------------------------------------------------------------------------------------Lead Temperature (Soldering, 10 sec.) -----------------------------------------------------------------Storage Temperature Range ------------------------------------------------------------------------------Junction Temperature ---------------------------------------------------------------------------------------ESD Susceptibility (Note 2)
HBM (Human Body Mode) --------------------------------------------------------------------------------MM (Machine Mode) -----------------------------------------------------------------------------------------

Recommended Operating Conditions
z
z

−0.3V to 7V
18V
−0.3V to 16V
−0.3V to 30V
−0.3V to 16V
−0.3V to (AVDD + 0.3V)
(VIN − 16V) to (VIN + 0.3V)
−0.3V to (VIN + 0.3V)
−0.3V to 7V
−0.3V to (LDOI + 0.3V)
1.786W
56°C/W
260°C
−65°C to 150°C
150°C
2kV
200V

(Note 3)

Ambient Temperature Range ------------------------------------------------------------------------------Junction Temperature Range -------------------------------------------------------------------------------

−40°C to 85°C
−40°C to 125°C

Electrical Characteristics
(VIN = 3.3V, VOUT = 8.5V, TA = 25°C, unless otherwise specification)

Parameter

Symbol

Test Condition

Min

Typ

Max

Units

2.5

5.5

VIN rising

1.8

2.0

2.2

Hysteresis

0.05

0.1

0.15

VFB = 1.3V, LX no switching

0.15

0.4

VFB = 1.1V, LX switching

3.5

VIN = 3.3V

μA

Logic-High Voltage VIH

1.5

Logic-Low Voltage VIL

0.8

RT9913 A

640

kHz

RT9913 B

0.9

1.2

1.4

MHz

System Supply
Input Supply Voltage

VIN

VIN Under Voltage Lockout Threshold VUVLO
VIN Quiescent Current

Shut Down Current

IIN

EN Threshold

Main Boost Regulator
Operation Frequency
Maximum Duty Cycle

FOSC

To be continued
DS9913A/B-00 February 2006

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5

RT9913A/B
Parameter

Preliminary
Min

Typ

Max

Units

No load, TA = 25°C

1.22

1.24

1.26

FB Input Bias Current

VFB = 1.5V

-40

+40

Transconductance of Error Amplifier Gm

ICOMP = 5μA

160

μA/V

700

V/V

0.1

0.15

%/V

−1

200

500

mΩ

0.5

A/V

Feedback Voltage

Voltage Gain of Error Amplifier

Symbol
VFB

Feedback Voltage Line Regulation

VIN = 2.5V to 5.5V
VIN = 3.3V,

Output Voltage Load Regulation
LX ON-Resistance

Test Condition

ILOAD = 20 to 200mA
RLX(ON)

Current Sense Transresistance
Soft-Start Charge Current

ISS

μA

Thermal Shutdown Temperature

TSD

170

°C

Thermal Shutdown Hysteresis

ΔTSD

°C

Current Limit

ILIM

VREF source current capability

IREF

100

1000

μA

FBN Regulation Voltage

VFBN

−20

−30

−5

2.5

5.5

200

300

500

Gate-Off Regulation Controller

VDRVN = −10V,

FBN Effective Load Regulation Error

IDRVN = 50uA to 1mA

FBN Line Regulation Error

IDRVN = 0.1mA, 2.5V 1V

Low Drop-Out Linear Regulator (LDO)
Input Voltage

VLDOI

Dropout Voltage

VDROP

Feedback Voltage

VADJ

1.22

1.24

1.26

Current Limit

ILIM

350

500

650

Quiescent Current

ILDO

100

μA

0.1

0.3

%/V

0.2

0.5

VIN = 3.3V, IOUT = 350mA

VIN = 2.8V to 5.5V,

Line Regulation

IOUT = 100mA, VLDO = 2.5V

Load Regulation

IOUT = 1mA to 300mA

Gate Pulse Modulator
VFLK Input High Voltage

VIH_FLK

1.5

VFLK Input Low Voltage

VIL FLK

0.6

Power-On-Delay Time (Note 5)

TVGHM

Refer to VFB > 1V

To be continued
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6

DS9913A/B-00 February 2006

RT9913A/B

Preliminary
Parameter

Symbol

Test Condition

Min

Typ

Max

Units

Gate Pulse Modulator
VGH Switch On-Resistance

RP1

RE Switch On-Resistance

RN2

1.6

1.1

−2%

80k

120k

160k

AVDD

0.5

0.9

−15

IOUT = 100μA

AVDD-20

AVDD-5

IOUT = 75mA

AVDD-1.5 AVDD-1.3

Voltage Detector
Minimum Operating Voltage
Detecting voltage adjustment

VDIV

Detecting voltage accuracy
Adjustable delay time-constant

tD = k(Ω)*C10(F)

VCOM Buffer
Supply Voltage Range

VSUP

Supply Current

IOP

Input Offset Voltage

VOS

Input Bias Current

IBIAS

Output Voltage Swing High

VOH

Output Voltage Swing Low

VOL

Short-Circuit Current

VCOM = AVDD/2, TA = 25°C

IOUT = −100μA

IOUT = −75mA

1.5

1.8

Source

100

140

180

Sink

100

140

180

To AVDD/2

-3dB Bandwidth

F3db

MHz

Gain Bandwidth Product

GBW

MHz

Slew Rate

V/μs

Note 1. Stresses listed as the above “Absolute Maximum Ratings” may cause permanent damage to the device. These are for
stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may remain possibility to affect device reliability.
Note 2. Devices are ESD sensitive. Handling precaution recommended.
Note 3. The device is not guaranteed to function outside its operating conditions.
Note 4. θJA is measured in the natural convection at T A = 25°C on a low effective thermal conductivity test board of
JEDEC 51-3 thermal measurement standard.
Note 5. It is guaranteed by design.

DS9913A/B-00 February 2006

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7

RT9913A/B

Preliminary

Typical Application Circuit
Boost Output Voltage vs. Output Current

Boost Efficiency vs. Output Current
8.62

95
90

Efficiency (%)

VIN = 3.3V
VIN = 3.0V
VIN = 2.7V

80
75
70
65
60

Output Voltage (V)

8.6

8.58
8.56
8.54

VIN = 2.7V
VIN = 3.0V
VIN = 3.3V

8.52
8.5

VAVDD = 8.5V, f = 1.2MHz

VAVDD = 8.5V, f = 1.2MHz
8.48

50
0

100 120 140 160 180 200

Boost Efficiency vs. Output Current

100 120 140 160 180 200

Boost Output Voltage vs. Output Current
12.04

VIN = 3.3V

VIN = 3.0V

80
75
70
65
60

Output Voltage (V)

Efficiency(%)

Output Current (mA)

11.96
11.92
11.88

VIN = 3.0V

11.84

VIN = 3.3V
11.8

VAVDD = 12V, f = 1.2MHz

VAVDD = 12V, f = 1.2MHz
11.76

50
0

100 120 140 160 180 200

Output Current (mA)

Boost Output Voltage vs. Output Current

Boost Efficiency vs. Output Current
8.6

8.4

84
82
80
78

VIN = 3V, f = 1.2MHz
C1 = 6.9μF, C2 = 30μF

VAVDD = 8.5V

8.2

Output Voltage (V)

VAVDD = 7V
= 7.5V
= 8V
= 8.5V

Efficiency (%)

VAVDD = 8V

7.8
7.6
7.4

VAVDD = 7.5V

7.2
7

VAVDD = 7V
VIN = 3V, f = 1.2MHz, C1 = 6.9μF, C2 = 30μF

6.8
6.6

76
0

100 120 140 160 180 200

Output Current (mA)

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8

100 120 140 160 180 200

Output Current (mA)

DS9913A/B-00 February 2006

RT9913A/B

Preliminary

Boost Regulator Load
Transient Response

Boost Feedback vs. Temperature
1.255
1.250

VAVDD
ac coupled
(500mV/Div)

Boost Feedback (V)

1.245
1.240
1.235
1.230

I LOAD
(100mA/Div)

1.225
1.220
1.215

IL
(500mA/Div)

1.210

ILOAD = 10mA to 200mA

1.205
-40 -30 -20 -10 0

10 20 30 40 50 60 70 80 90

Time (200μs/Div)

Temperature (°C)

Boost Regulator Soft-Start

Boost Regulator Stability

ILOAD = 200mA

VAVDD
(5V/Div)

VLX
(5V/Div)

VIN
(5V/Div)

VAVDD ripple
ac coupled
(50mV/Div)

EN
(2V/Div)
I IN
(500mA/Div)

IL
(200mA/Div)

ILOAD = 10mA, f = 1.2MHz

Time (2.5ms/Div)

Time (400ns/Div)

VGL Regulator Load Regulation

Boost Regulator Stability
-5.75
-5.77

VGL Voltage (V)

VLX
(5V/Div)
VAVDD ripple
ac coupled
(50mV/Div)
IL
(200mA/Div)

f = 1.2MHz
ILOAD = 100mA

-5.79
-5.81
-5.83
-5.85
-5.87

Time (400ns/Div)

DS9913A/B-00 February 2006

100

Load Current (mA)

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9

RT9913A/B

Preliminary

VGL Regulator Line Regulation

VGL Output Voltage (V)

-5.75

Power On Sequence

IGL = 50mA

VAVDD
(5V/Div)

-5.77

-5.79

VGH
(10V/Div)

-5.81

VGHM
(10V/Div)
VGL
(5V/Div)

-5.83

-5.85
-14

-13

-12

-11

-10

-9

-8

-7

Time (25ms/Div)

Input Voltage(V)

Power Off Sequence
with GPM Function

Power Off Sequence

VAVDD

(5V/Div)

VAVDD

(5V/Div)

VGH

(5V/Div)

VGL

(5V/Div)
VGL
VGHM

(10V/Div)
VGH

(10V/Div)
(10V/Div)

FLK = 50kHz/50%

FLK = VIN

Time (2.5ms/Div)

Time (25ms/Div)

VGHM

VFLK
(1V/Div)

VGHM
(10V/Div)

R11 = 670Ω, C15 = 1.5nF

Time (10μs/Div)

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10

VGHM

(10V/Div)

R11 = 1.2kΩ, C15 = 680pF

Time (10μs/Div)

DS9913A/B-00 February 2006

RT9913A/B

Preliminary

VGHM

LDO Load Transient

VLDOO
ac coupled
(50mV/Div)
VFLK
(1V/Div)
I LDOO
(200mA/Div)

VGHM
(10V/Div)

ILDOO = 10mA to 350mA

R11 = 1.2kΩ, C15 = 2.2nF

Time (10μs/Div)

Time (100μs/Div)

LDO Load Regulation

LDO Line Transient
2.59

LDO Output Voltage (V)

VLDOO
ac coupled
(100mV/Div)

VLDOI 4
(1V/Div) 3

2.585

2.58

2.575

VLDOO = 2.5V, VLDOI = 3V to 4V, ILDOO = 50mA

VLDOO = 2.5V, VLDOI = 3.3V
2.57
0

Time (100μs/Div)

100

150

200

250

300

350

LDO Loading Current (mA)

LDO Dropout Voltage

LDO OCP

500

Dropout Voltage (mV)

450

85°C

400

25°C

350
300

I LDO
(200mA/Div)

-40°C

250
200
150
100

VLDO
(1V/Div)

IOUT = 100mA to 600mA

0
0

0.05

0.1

0.15

0.2

0.25

Load Current (A)

DS9913A/B-00 February 2006

0.3

0.35

0.4

Time (100μs/Div)

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11

RT9913A/B

Preliminary

OPA Large-Signal Step Response

VOPAI
(1V/Div)

OPA Small-Signal Step Response

VOPAI
(100mV/Div)

VOPAO
(100mV/Div)

VOPAO
(1V/Div)

Time (1μs/Div)

Time (500ns/Div)

OPA Rail-to-Rail Input/Output

OPA Slew Rate

VOPAI
(5V/Div)

VOPAI

VOPAO
(5V/Div)

(2V/Div)

Time (400μs/Div)

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12

VOPAO

Time (1μs/Div)

DS9913A/B-00 February 2006

RT9913A/B

Preliminary
Application Information
The RT9913 contains a high performance boost regulator
to generate voltage for output voltage, gate-on driver and
negative voltage regulated by linear regulator controller
for gate-off driver. It also includes of a high-current rail-torail operation amplifier, a gate pulse modulator (GPM), a
programmable timing control voltage detector, and a low
dropout linear regulator. The following content contains
the detailed description and the information of component
selection.

Boost Regulator
The boost regulator is a high efficiency current-mode PWM
architecture with 1.2MHz or 640kHz operation frequency.
It performs fast transient responses to generate gate driver
supplies for TFT LCD display. The high operation frequency
allows smaller components used to minimize the
thickness of LCD panel. To regulate the output voltage is
to set resistive voltage-divider sensing at FB pin. The error
amplifier varies the COMP voltage by sensing FB pin to
regulate the output voltage. For better stability, the slope
compensation signal summed with the current-sense
signal will be compared with the COMP voltage to
determine the current trip point and duty cycle.
Soft-Start
The RT9913 provides soft-start function to minimize the
inrush current. When EN pin is connected to high, an
internal constant current charges an external capacitor.
The rising voltage rate on COMP pin is limited during the
charging period and the inductor peak current also limited
at the same time. In the meanwhile, the frequency
increases slowly at the beginning. When the EN pin is
connected to GND, the external capacitor will be
discharged for next soft start time.
The soft-start function is implemented by the external
capacitor with a 4μA constant current charging to the softstart capacitor. Therefore, the capacitor should be large
enough for output voltage regulation. Typical value for softstart capacitor range is 27nF. The available soft start
capacitor range is from 10nF to 200nF.

DS9913A/B-00 February 2006

Inductor Selection & Maximum output current
capability
The minimum inductance value, peak current rating and
series resistance are factors to consider when selecting
the inductor. These factors influence the converter's
efficiency, maximum output load capability, transientresponse time and output voltage ripple. Physical size
and cost are also important factors to be considered. The
maximum output current, input voltage, output voltage and
switching frequency determine the inductor value. Very
high inductance values minimize the current ripple and
therefore reduce the peak current, which decreases core
losses in the inductor and I2R losses in the entire power
path. However, large inductor values also require more
energy storage and more turns of wire, which increase
physical size and can increase I2R losses in the inductor.
Low inductance values decrease the physical size but
increase the current ripple and peak current.
Finding the best inductor involves choosing the best
compromise between circuit efficiency, inductor size and
cost.
Choose an available inductor value from an appropriate
inductor family. Calculate the maximum DC input current
at the minimum input voltage VIN(MIN) using the following
equation.

IIN(DC, MAX) =

IAVDD(MAX) × VAVDD
VIN(MIN) × η(MIN)

The expected efficiency at that operating point (ηMIN) can
be taken from an appropriate curve in the Typical Operating
Characteristics. Calculate the ripple current at that
operating point and the peak current required for the
inductor :
IRIPPLE =

VIN(MIN) × (VAVDD − VIN(MIN) )
L ×V AVDD ×fOSC

IRIPPLE
2
The inductor's saturation current rating and the LX overcurrent protection (IOCP) should exceed IPEAK and the
inductor DC current rating should exceed IIN(DC,MAX). For
good efficiency, choosing an inductor with less than 0.1Ω
series resistance is suggested.
IPEAK = IIN(DC, MAX) +

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13

RT9913A/B

Preliminary

Diode Selection

Over Current Protection

To achieve high efficiency, Schottky diode is the
recommended diode for lower forward drop voltage and
faster switching time. The output diode rating should be
large enough for maximum output voltage, average power
dissipation and the pulsating diode peak current.

The RT9913 main boost converter has over-current
protection to limit peak inductor current. It prevents large
current damaging the inductor and diode. During the
ON-time, once the inductor current exceeds the current
limit, the internal LX switch turns off immediately and
shortens the duty cycle. Therefore, the output voltage
drops if the over-current condition occurs. Actual current
limit is always larger than nominal value because of the
internal circuit delay. Current limit is also affected by the
input voltage, duty cycle, and inductor value. The following
figure shows the different over-current settings and the
corresponding RSET resistance while OCP function works
and VAVDD falls to 90%.
OCP Current vs. RSET

For lower output voltage ripple, low-ESR ceramic capacitor
is recommended. The output voltage ripple consists of
two components: one is the pulsating output ripple current
flowing through the ESR, and the other is the capacitive
ripple caused by charging and discharging.

VRIPPLE = VRIPPLE_ESR + VRIPPLE_C
≅ IPEAK × RESR +

IPEAK ⎛ VAVDD − VIN ⎞
⎜
⎟
COUT ⎝ VAVDD × f ⎠

Input Capacitor Selection
For better input bypassing, low-ESR ceramic capacitor is
recommended for better performance. A 10μF input
capacitor is sufficient and it is flexible to reduce the value
for a lower output power requirement.

2.2
2
1.8

OCP Current (A)

Output Capacitor Selection

1.6
1.4
1.2
1

Output Voltage

0.8

The regulated output voltage is the following formula :

0.6

VOUT = 1.24V × ⎛⎜1 + R1 ⎞⎟
⎝ R2 ⎠

The recommended value for R2 should be up to 100kΩ
without some sacrificing. To place the resistor-divider as
close as possible to the chip can reduce noise sensitivity.
Loop Compensation
The voltage feedback loop can be compensated with an
external compensation network consisted of R3, C3 and
CCOMP (As Figure 1). Choose R3 to set high frequency
integrator gain for fast transient response and C3 to set
the integrator zero to maintain loop stability.

100

150

200

250

300

RSET (kΩ)

Figure 1. OCP settings versus RSET @ VEN = 2.5V
Over Temperature Protection
The RT9913 main boost converter has thermal protection
function to prevent the excessive power dissipation from
overheating. When the junction temperature exceeds
170°C, it will shut down the device. Once the device cools
down by approximately 20°C, it will start to operate
normally. For continuous operation, do not operate over
the maximum junction temperature rating around 150°C.

Place CCOMP between COMP and GND to add an additional
high-frequecncy pole. The value is between 10pF and
47pF. For typical application VIN = 3.3V , VOUT = 8.5V
,COUT = 4.7μF x 3 , L = 4.7μH, the recommened value
for compensation is as below:
R3 = 56kΩ , C3 = 1nF , Ccomp=NC
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14

DS9913A/B-00 February 2006

RT9913A/B

Preliminary
Gate-Low Linear Regulator Controller
The gate-low linear regulator controller is to provide the
TFT-LCD gate off voltage. One stage charge pump can
provide a negative voltage. Using the gate-low regulator
after the produced negative voltage can regulate the
exceeded voltage. With a 6.8kΩ base to emitter resistor
it can drive an extra NPN pass transistor and at least 4mA
source current. VGL can be regulated by the voltage-divider
resistor and 0.22μF ceramic output capacitor. The output
load current (ILOAD) can be decided by the current gain
(β), drive current (IDRVN), base-to-emitter forward voltage
drop (VBE) and base-to-emitter resistor (R8) as the following
equation :
ILOAD

V
= β (IDRVN - BE )
R8
VGL Regulation Circuit
VREF

1.24V

R10
FBN

C14

PWM

DRVN

VGL
ZD1

VIN

VAVDD

VIN
LX
Boost
Regulator
FB
RT9913A/B

Figure 3

GPM
The GPM function is controlled by frame signals from
timing controller to modulate the Gate-On voltage (VGHM).
According to the different loading capacitor (C16), the
falling slope of the Gate-On voltage is programmable by
an external resistor (R11) .The VGL lags 32ms (typ.) behind
AVDD and the VGHM lags 64ms (typ.) behind AVDD while
power on.

R8
C11

VGL
C13

C12

VGHM

VGH
P1

Figure 2
The VGL regulator controls the intermediate charge-pump
stage and regulates the final charge-pump's output voltage
as the following equation :
VGL = −VREF (R9/R10)
Zener Diode for the Negative Regulator
Instead of the gate-low linear regulator controller,
bypassing a zener diode(ZD1) after the charge-pump satge
can also stable the negative voltage. However, for better
efficiency, using the gate-low linear regulator controller is
recommended.

VFLK

PGOOD
Pos-edge
64ms delay

PGOOD
Delay

Gate
Driver IC

C15

RE
R11

Gate Pulse Modulator

Figure 4
The GPM operation sequence is shown in Figure 5.
PGOOD is the logic signal detecting the feedback voltage
(V FB). If V FB is below 1V, PGOOD becomes low ;
otherwise, PGOOD is high while VFB is above 1V. When
PGOOD is high lasting more than 64ms, PGOOD Delay
signal is built and then VGHM is controled by VFLK signal.

VGL = −(VAVDD− VD)
VD : forward voltage drop of the charge pump diode

DS9913A/B-00 February 2006

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15

RT9913A/B

Preliminary
Charge Pumps

VIN

The charge pump stages can be achieved by the flying
capacitors and the Schottky diodes. According to the
application circuit, the positive and negative charge-pump
output voltages can be determined by the following
equations :

AVDD
VGH
PGOOD
PGOOD Delay

VGH = 3VAVDD − 2VD

VFLK
64ms
VGHM

VGH
adjustable falling slope

Figure 5
GPM for Power Sequence
The GPM function also achieves the power-on sequence
control. The GPM internal delay time (64ms) can be used
for VGH built-up delay. The application circuit is shown in
Figure 6 connecting input voltage to VFLK and bypassing
a 1uF to VGHM .VGH will lag 64ms after VAVDD built.

VGH

VGHM

GPM
VFLK

VIN

1uF

VD : the forward voltage drop of the charge pump diodes
The flying capacitor requires the voltage rating larger than
16V and 0.1uF ceramic capacitors are enough for the lowcurrent applications (10mA) . Besides, Schottky diodes
with a current rating should equal to or greater than two
times the average charge-pump input current. Note that
the voltage difference between VGH (VGHM) and AVDD
should not exceed 18V.

Operational Amplifier
The operational amplifier to drive the LCD backplane VCOM.
The operational amplifier features +/- 140mA output shortcircuit current, 12V/μs slew rate, and 12MHz bandwidth.
An internal short-circuit protection circuit is implemented
to protect the device from output short circuit. The
operational amplifier limits the short circuit current while
the output is directly shorted.

LDO

RT9913A/B

The low-dropout linear regulator (LDO) can supply up to
350mA current while input voltage is 3.3V. It uses an
internal PMOS as the pass device. The output current
limitation is 500mA. It is suitable for the supply voltage
for the T-CON ASIC.

VIN
AVDD
VGH
VGL

LDOI

32ms
VGHM
64ms

Figure 6

Current
Limit
LDOO
R4
ADJ
R5
AGND

Figure 7

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16

DS9913A/B-00 February 2006

Preliminary

RT9913A/B

Voltage Detector

Layout Guideline

The voltage detector monitors the VDIN voltage to generate
a reset signal while VDIN is lower than the detecting level.
The detecting level is decided by an external resistor divider.

For high frequency switching power supplies, the PCB
layout is important to get good regulation, high efficiency
and stability. The following descriptions are the guidelines
for better PCB layout.

VDET = VREF2 (1+R6/R7) = 1.1V x (1+R6/R7)

VHYS = 50mV (1+R6/R7)
The delay time is programmable by an external capacitor
(C10) as equation. For example, setting C10 = 100nF can
generate 12ms delay for reset signal.

tD = 120k x C10
VIN

VDIN
R6
R7

VLDO

RESET
VDIV
VREF2 = 1.1V

R14

Delay
Circuit

+
-

C10

VDI
VDET+VHYS Release Voltage

VHYS

VDET Detecting Voltage

Min Operating Voltage
GND
RESET
z

GND

For good regulation place the power components as
close as possible. The traces should be wide and short
especially for the high-current output loop.
The current limit setting resistor RSET must be near the
EN pin, The trace must be shorter and avoid the trace
near any switching nodes.
The feedback voltage-divider resistors must be near the
feedback pin. The divider center trace must be shorter
and avoid the trace near any switching nodes.
The compensation circuit should be kept away from
the power loops and be shielded with a ground trace to
prevent any noise coupling.
Minimize the size of the Lx node and keep it wide and
shorter. Keep the Lx node away from the FB and analog
ground.
The power ground (PGND) consists input and output
capacitor grounds, the components' ground of charge
pump and GPM. The PGND should be wide and short
connected to a ground plane.
The analog ground (AGND) consists the grounds of
compensation, soft-stat capacitor, FB divider, and OP
divider. The AGND should be separated from PGND and
connected to the ground of the input capacitor.
The exposed pad of the chip should be connected to
ground plane for thermal consideration.

Figure 8

DS9913A/B-00 February 2006

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17

RT9913A/B

Preliminary

Outline Dimension
D2

SEE DETAIL A
L
1

1
2

DETAIL A
Pin #1 ID and Tie Bar Mark Options

A
A3
A1

Symbol

1
2

Note : The configuration of the Pin #1 identifier is optional,
but must be located within the zone indicated.

Dimensions In Millimeters
Min

Dimensions In Inches

Max

Min

Max

0.800

1.000

0.031

0.039

0.000

0.050

0.000

0.002

0.175

0.250

0.007

0.010

0.180

0.300

0.007

0.012

3.950

4.050

0.156

0.159

2.300

2.750

0.091

0.108

3.950

4.050

0.156

0.159

2.300

2.750

0.091

0.108

e
L

0.500
0.350

0.020
0.450

0.014

0.018

V-Type 24L QFN 4x4 Package

RICHTEK TECHNOLOGY CORP.

Headquarter

Taipei Office (Marketing)

5F, No. 20, Taiyuen Street, Chupei City

8F-1, No. 137, Lane 235, Paochiao Road, Hsintien City

Hsinchu, Taiwan, R.O.C.

Taipei County, Taiwan, R.O.C.

Tel: (8863)5526789 Fax: (8863)5526611

Tel: (8862)89191466 Fax: (8862)89191465
Email: marketing@richtek.com

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18

DS9913A/B-00 February 2006

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