SF1530 Datasheet. Www.s manuals.com. Sifirst

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SF1530

FEATURES

◆ Proprietary “Zero OCP/OPP Recovery Gap”

Control

◆ Built-in Soft Start Function

◆ All Pins Floating Protection

◆ Very Low Startup Current

◆ High Voltage CMOS Process with Excellent

ESD Protection

◆ Frequency Reduction and Burst Mode Control

for Energy Saving

◆ Current Mode Control

◆ Built-in Frequency Shuffling

◆ Programmable Switching Frequency

◆ Built-in Synchronous Slope Compensation

◆ Cycle-by-Cycle Current Limiting

◆ Built-in Leading Edge Blanking (LEB)

◆ Constant Power Limiting

◆ Audio Noise Free Operation

◆ VDD OVP & Clamp

◆ VDD Under Voltage Lockout (UVLO)

APPLICATIONS

Offline AC/DC Flyback Converter for

◆ AC/DC Adaptors

◆ Open-frame SMPS

◆ Set-Top Box Power Supplies

◆ ATX Standby Power

GENERAL DESCRIPTION

SF1530 is a high performance, low cost, highly

integrated current mode PWM controller for offline

flyback converter applications.

PWM switching frequency with shuffling is externally

programmable, which can reduce conduction EMI

emission of a power supply. When the output power

demands decrease, the IC automatically decreases

switching frequency for high power conversion

efficiency. When the current set-point falls below a

given value, e.g. the output power demand

diminishes, the IC enters into burst mode and

provides excellent efficiency without audio noise.

The IC can achieve “Zero OCP/OPP Recovery Gap”

using SiFirst’s proprietary control algorithm.

Meanwhile, the OCP/OPP variation versus universal

line input is compensated.

The IC has built-in synchronized slope compensation

to prevent sub-harmonic oscillation at high PWM duty

output. The IC also has built-in soft start function to

soften the stress on the MOSFET during power on

period.

SF1530 integrates functions and protections of Under

Voltage Lockout (UVLO), VCC Over Voltage

Protection (OVP), Cycle-by-cycle Current Limiting

(OCP), All Pins Floating Protection, Over Load

Protection (OLP), RT Pin Short-to-GND Protection,

Gate Clamping, VCC Clamping, Leading Edge

Blanking (LEB).

SF1530 is available in SOT23-6, SOP-8 and DIP-8

packages.

TYPICAL APPLICATION

AC IN

RT

VDD

2

GATE

GND FB

SF1530

DC Out

CS

31

5 46

TL431

High Performance Current Mode PWM Controller

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SF1530

Pin Configuration

GND

FB

1

2

3

6

5

4

RT

GATE

VDD

CS

SOT23-6

GATE

VDD

1

2

3

NC

GND

FB

NC

DIP8

4

8

7

6

5CS RT

Ordering Information

Part Number Top Mark Package Tape & Reel

SF1530LGT .30YWW SOT26 Green Yes

SF1530DP SF1530DP DIP8 RoHS

Marking Information

YWW: Year&Week code

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SF1530

Block Diagram

CS

FB

GND

Slope

compensation

Burst Mode

Control

43ms Delay

OCP

Soft start

CS floating

protection

RT short/floating

protection

POR

Trimmed Voltage &

Current Reference

GATE

Soft Gate

Driver

VDD

9V/14V

27.5V

VDD OVP

33V

RT

Oscillator with

Frequency Shuffling

Internal

blocks

R

S

Q

LEB

Frequency

Reduction Control

5.3V

3.7V

OLP

Zero OCP Recovery

Gap Control

Pin Description

Pin Num Pin Name I/O Description

1 GND P Ground

2 FB I Voltage feedback pin. The loop regulation is achieved by connecting a

photo-coupler to this pin. PWM duty cycle is determined by this pin voltage

and the current sense signal at Pin 3.

3 RT I Set the switching frequency by connecting a resistor between RT and

GND. This pin has floating/short-to-GND protection.

4 CS I Current sense input pin.

5 VDD P IC power supply pin.

6 GATE O Totem-pole gate driver output to drive the external MOSFET.

Absolute Maximum Ratings (Note 1)

Parameter Value Unit

VDD DC Supply Voltage 33 V

VCC DC Clamp Current 10 mA

GATE pin 20 V

FB, RT, CS voltage range -0.3 to 7 V

Package Thermal Resistance (SOT-26) 250 oC/W

Package Thermal Resistance (DIP-8) 90 oC/W

Package Thermal Resistance (SOP-8) 150 oC/W

Maximum Junction Temperature 150 oC

Operating Temperature Range -40 to 85 oC

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SF1530

Storage Temperature Range -65 to 150 oC

Lead Temperature (Soldering, 10sec.) 260 oC

ESD Capability, HBM (Human Body Model) 3 kV

ESD Capability, MM (Machine Model) 250 V

Recommended Operation Conditions (Note 2)

Parameter Value Unit

Supply Voltage, VDD 11 to 25 V

Operating Frequency 50 to 130 kHz

Operating Ambient Temperature -40 to 85 oC

ELECTRICAL CHARACTERISTICS

(TA = 25OC, RT=100K ohm, VDD=18V, if not otherwise noted)

Symbol Parameter Test Conditions Min Typ Max Unit

Supply Voltage Section (VDD Pin)

UVLO(ON) VDD Under Voltage

Lockout Exit (Startup)

13 14 15 V

UVLO(OFF) VDD Under Voltage

Lockout Enter

8 9 10 V

I_Startup VDD Start up Current VDD =12.5V, Measure

current into VDD

5 20 uA

I_VDD_Op Operation Current VFB=3V,CL=1nF 2.5 3.5 mA

VDD_OVP VDD Over Voltage

Protection trigger

25 27.5 30 V

VDD_Clamp VDD Zener Clamp

Voltage

I(VDD ) = 15 mA 33 V

T_Softstart Soft Start Time 3 mSec

Feedback Input Section(FB Pin)

VFB_Open FB Open Voltage 5.3

V

IFB_Short FB short circuit

current

Short FB pin to GND,

measure current

1.1 mA

AVCS PWM Input Gain ΔVFB /ΔVcs 2.0 V/V

VFB_min_duty FB under voltage gate

clock is off.

1.0 V

VTH_PL Power Limiting FB

Threshold Voltage

3.7 V

TD_PL Power limiting

Debounce Time

Note 3 43 mSec

ZFB_IN Input Impedance 5 Kohm

Current Sense Input Section (CS Pin)

Vth_OC_min Internal current

limiting threshold

Zero duty cycle 0.70 0.75 0.80 V

T_blanking SENSE Input Leading

Edge Blanking Time

250 nSec

TD_OC Over Current

Detection and Control

Delay

CL=1nF at GATE, 70 nSec

Oscillator Section (RT Pin)

FOSC Normal Oscillation

Frequency

60 65 70 KHZ

RT_range Operating RT Range 50 100 150 Kohm

V_RT_open RT open voltage 2.0 V

∆F(shuffle)/Fosc Frequency shuffling

range

Note 4 -4 4 %

∆f_Temp Frequency

Temperature Stability

-20oC to 100 oC (Note 4) 5 %

∆f_VDD Frequency Voltage VDD = 12-25V, 5 %

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SF1530

Stability

Duty_max Maximum Duty cycle 75 80 85 %

F_BM Burst Mode Base

Frequency

22 KHZ

Gate Drive Output (GATE Pin)

VOL Output Low Level Io = 20 mA (sink) 1 V

VOH Output High Level Io = 20 mA (source) 7.5 V

VG_Clamp Output Clamp Voltage

Level

VDD=24V 17.5 V

T_r Output Rising Time CL = 1nF 200 nSec

T_f Output Falling Time CL = 1nF 60 nSec

Note 1. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to

the device. These are stress ratings only, and functional operation of the device at these or any other

conditions beyond those indicated in the operational sections of the specifications is not implied.

Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Note 2. The device is not guaranteed to function outside its operating conditions.

Note 3. The OLP debounce time is proportional to the period of switching cycle.

Note 4. Guaranteed by design.

CHARACTERIZATION PLOTS

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SF1530

OPERATION DESCRIPTION

SF1530 is a high performance, low cost, highly

integrated current mode PWM controller for offline

flyback converter applications. The built-in

advanced energy saving with high level protection

features improves the SMPS reliability and

performance without increasing the system cost.

◆ UVLO and Startup Operation

Fig.1 shows a typical startup circuitn. Before the IC

begins switching operation, it consumes only

startup current (typically 5uA) and current supplied

through the startup resistor Rst charges the VDD

hold-up capacitor Cdd. When VDD reaches UVLO

turn-on voltage of 14V(typical), SF1530 begins

switching and the IC current consumed increased

to 2mA (typical). The hold-up capacitor Cdd

continues to supply VDD before the energy can be

delivered from auxiliary winding Na. During this

process, VDD must not drop below UVLO turn-off

voltage (typical 9V). The selection of Rst and Cdd

should be a trade off between the power loss and

startup time.

AC IN

VDD

GATE

2FB

GND

CS

SF1530

RT

3

1

5

4

6

Cbulk Rst

Cdd

Np

Na

Fig.1

◆ Low Operating Current

The operating current in SF1530 is as small as

1.3mA (typical). The small operating current results

in higher efficiency and reduces the VDD hold-up

capacitance requirement.

◆ Soft Start

SF1530 features an internal 3ms (typical) soft start

that slowly increases the threshold of cycle-by-

cycle current limiting comparator during startup

sequence. It helps to prevent transformer saturation

and reduce the stress on the secondary diode

during startup. Every restart attempt is followed by

a soft start activation.

◆ “Zero OCP/OPP Recovery Gap” Control

The definition of OCP or OPP recovery gap of a

power adaptor is illustrated in Fig.2. At T0,

assuming an adaptor is at full loading mode. If the

loading keeps increasing, then the system will

output maximum power P_opp, which will trigger

OPP protection at the same time. After the OPP

protection is triggered, usually the system will enter

into the auto-recovery mode, in burst manner. If the

system power demand decreases below

P_recovery, then system will enter into normal

mode again, as shown in Fig.2. The difference

between P_opp and P_recovery is defined as “OPP

Recovery Gap”, which can cause system startup

failure especially in 90VAC full load startup.

Fig.2

SF1530 can achieve “Zero OCP/OPP Recovery

Gap” in the whole universal AC input range using

SiFirst’s proprietary control algorithm.

◆ Synchronous Slope Compensation

InSF1530, the synchronous slope compensation

circuit is integrated by adding voltage ramp onto the

current sense input voltage for PWM generation.

This greatly improves the close loop stability at

CCM and prevents the sub-harmonic oscillation

and thus reduces the output ripple voltage.

◆ Oscillator with Frequency Shuffling

Connecting a resistor from RT pin to GND

according to the equation below to program the

normal switching frequency:

()

)RT(K

6500

KHzFOSC Ω

=

It can typically operate between 50kHz to 130kHz.

To improve system EMI performance, SF1530

operates the system with ±4% frequency shuffling

around setting frequency.

◆ Leading Edge Blanking (LEB)

Each time the power MOSFET is switched on, a

turn-on spike occurs across the sensing resistor.

The spike is caused by primary side capacitance

and secondary side rectifier reverse recovery. To

avoid premature termination of the switching pulse,

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SF1530

an internal leading edge blanking circuit is built in.

During this blanking period (350ns, typical), the

PWM comparator is disabled and cannot switch off

the gate driver. Thus, external RC filter with a small

time constant is enough for current sensing.

◆ Frequency Reduction for Green Mode

Operation

When the loading is light, the IC will automatically

reduce the PWM switching frequency to achieve

high efficiency. In the whole frequency reduction

process, there is no audio noise generated.

VFB

PWM Frequency

(RT=100kΩ)

65kHz

0

Burst

mode

22kHz

Frequency

Reduction mode

Normal

mode

Fig.3

◆ Burst Mode Control

When the loading is very small, the system enters

into burst mode. When VFB drops below Vskip,

SF1530 will stop switching and output voltage

starts to drop, which causes the VFB to rise. Once

VFB rises above Vskip, switching resumes. Burst

mode control alternately enables and disables

switching, thereby reducing switching loss in

standby mode.

Fig.4

◆ Auto Recovery Mode Protection

As shown in Fig.5, once a fault condition is

detected, switching will stop. This will cause VDD to

fall because no power is delivered form the

auxiliary winding. When VDD falls to UVLO(off)

(typical 9V), the protection is reset and the

operating current reduces to the startup current,

which causes VDD to rise, as shown in Fig.4.

However, if the fault still exists, the system will

experience the above mentioned process. If the

fault has gone, the system resumes normal

operation. In this manner, the auto restart can

alternatively enable and disable the switching until

the fault condition is disappeared.

Fig.5

◆ VDD OVP(Over Voltage Protection)

VDD OVP (Over Voltage Protection) is

implemented in SF1530 and it is a protection of

auto-recovery mode.

◆ Over Load Protection (OLP)

When over load occurs, a fault is detected. If this

fault is present for more than 43ms (typical), the

protection will be triggered, the IC will experience

an auto-recovery mode protection as mentioned

above. The 43mS delay time is to prevent the false

trigger from the power-on and turn-off transient

◆ All Pins Floating Protection and RT Pin

Short-to-GND Protection

In SF1530, if pin floating situation or RT pin short-

to-GND occurs, the protection is triggered

immediately and the system will experience the

process of auto-recovery mode protection.

◆ Soft Gate Drive

SF1530 has a fast totem-pole gate driver with

300mA capability. Cross conduction has been

avoided to minimize heat dissipation, increase

efficiency, and enhance reliability. An internal 17V

clamp is added for MOSFET gate protection at

higher than expected VDD input. A soft driving

waveform is implemented to minimize EMI.

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SF1530

PACKAGE MECHANICAL DATA

Symbol Dimensions In Millimeters Dimensions In Inches

Min Max Min Max

A 1.000 1.300 0.039 0.051

A1 0.000 0.150 0.000 0.006

A2 1.000 1.200 0.039 0.047

b 0.300 0.500 0.012 0.020

c 0.100 0.200 0.004 0.008

D 2.800 3.020 0.110 0.119

E 1.500 1.700 0.059 0.067

E1 2.600 3.000 0.102 0.118

e 0.950 (BSC) 0.037 (BSC)

e1 1.800 2.000 0.071 0.079

L 0.300 0.600 0.012 0.024

θ 0º 8º 0º 8º

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SF1530

Symbol Dimensions In Millimeters Dimensions In Inches

Min Max Min Max

A 3.710 5.334 0.146 0.210

A1 0.381 0.015

A2 3.175 3.600 0.125 0.142

B 0.350 0.650 0.014 0.026

B1 1.524 (BSC) 0.06 (BSC)

C 0.200 0.360 0.008 0.014

D 9.000 10.160 0.354 0.400

E 6.200 6.600 0.244 0.260

E1 7.320 7.920 0.288 0.312

e 2.540 (BSC) 0.1 (BSC)

L 2.921 3.810 0.115 0.150

E2 8.200 9.525 0.323 0.375

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SF1530

Symbol Dimensions In Millimeters Dimensions In Inches

Min Max Min Max

A 1.350 1.750 0.053 0.069

A1 0.050 0.250 0.002 0.010

A2 1.250 1.650 0.049 0.065

b 0.310 0.510 0.012 0.020

c 0.170 0.250 0.006 0.010

D 4.700 5.150 0.185 0.203

E 3.800 4.000 0.150 0.157

E1 5.800 6.200 0.228 0.244

e 1.270 (BSC) 0.05 (BSC)

L 0.400 1.270 0.016 0.050

θ 0º 8º 0º 8º

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SF1530

IMPORTANT NOTICE

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improvements and other changes to its products and services at any time and to discontinue any product or

service without notice. Customers should obtain the latest relevant information before placing orders and should

verify that such information is current and complete.

SiFirst warrants performance of its hardware products to the specifications applicable at the time of sale in

accordance with SiFirst’s standard warranty. Testing and other quality control techniques are used to the extent

SiFirst deems necessary to support this warranty. Except where mandated by government requirements,

testing of all parameters of each product is not necessarily performed.

SiFirst assumes no liability for application assistance or customer product design. Customers are responsible

for their products and applications using SiFirst’s components. To minimize the risks associated with customer

products and applications, customers should provide adequate design and operating safeguards.

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