SF1530 Datasheet. Www.s Manuals.com. Sifirst

User Manual: Marking of electronic components, SMD Codes 30, 30***, 3003, 301, 305, 305*, 3055L, 3064, 3064B, 30A, 30T, 30Y. Datasheets 1.5SMC30AT3, AT-30511, AT-30533, BCR320U, BZV49-C30, FDC6301N, FDC6305N, FDV301N, FDV305N, NCP3064BDR2G, NCP3064DR2G, NTF3055L108, SF1530LGT, TK71530AS, ZD30-AE3, ZD30-CL2, ZXGD3006E6TA.

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SF1530
High Performance Current Mode PWM Controller
FEATURES

GENERAL DESCRIPTION

◆ Proprietary “Zero OCP/OPP Recovery Gap”
Control
◆ Built-in Soft Start Function
◆ All Pins Floating Protection
◆ Very Low Startup Current
◆ High Voltage CMOS Process with Excellent
ESD Protection
◆ Frequency Reduction and Burst Mode Control
for Energy Saving
◆ Current Mode Control
◆ Built-in Frequency Shuffling
◆ Programmable Switching Frequency
◆ Built-in Synchronous Slope Compensation
◆ Cycle-by-Cycle Current Limiting
◆ Built-in Leading Edge Blanking (LEB)
◆ Constant Power Limiting
◆ Audio Noise Free Operation
◆ VDD OVP & Clamp
◆ VDD Under Voltage Lockout (UVLO)

SF1530 is a high performance, low cost, highly
integrated current mode PWM controller for offline
flyback converter applications.
PWM switching frequency with shuffling is externally
programmable, which can reduce conduction EMI
emission of a power supply. When the output power
demands decrease, the IC automatically decreases
switching frequency for high power conversion
efficiency. When the current set-point falls below a
given value, e.g. the output power demand
diminishes, the IC enters into burst mode and
provides excellent efficiency without audio noise.
The IC can achieve “Zero OCP/OPP Recovery Gap”
using SiFirst’s proprietary control algorithm.
Meanwhile, the OCP/OPP variation versus universal
line input is compensated.
The IC has built-in synchronized slope compensation
to prevent sub-harmonic oscillation at high PWM duty
output. The IC also has built-in soft start function to
soften the stress on the MOSFET during power on
period.
SF1530 integrates functions and protections of Under
Voltage Lockout (UVLO), VCC Over Voltage
Protection (OVP), Cycle-by-cycle Current Limiting
(OCP), All Pins Floating Protection, Over Load
Protection (OLP), RT Pin Short-to-GND Protection,
Gate Clamping, VCC Clamping, Leading Edge
Blanking (LEB).
SF1530 is available in SOT23-6, SOP-8 and DIP-8
packages.

APPLICATIONS
Offline AC/DC Flyback Converter for
◆ AC/DC Adaptors
◆ Open-frame SMPS
◆ Set-Top Box Power Supplies
◆ ATX Standby Power

TYPICAL APPLICATION

DC Out

AC IN
6

GATE

VDD

SF1530
GND

3
TL431

©SiFirst Technology

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-1-

SF1530_DS_V1.0

SF1530
Pin Configuration
GND

GATE

SOT23-6
FB

2
3

5
4

GND

GATE

VDD

NC
CS

DIP8

VDD
CS

Ordering Information
Part Number

Top Mark

SF1530LGT
SF1530DP

.30YWW
SF1530DP

Package
SOT26
DIP8

Tape & Reel
Green
RoHS

Yes

Marking Information

YWW: Year&Week code

©SiFirst Technology

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-2-

SF1530_DS_V1.0

SF1530
Block Diagram
Oscillator with
Frequency Shuffling

Soft Gate
Driver

GATE

Zero OCP Recovery
Gap Control
Frequency
Reduction Control
RT short/floating
protection
CS floating
protection
LEB

Trimmed Voltage &
Current Reference

Internal
blocks

CS
OCP

VDD

Soft start

POR

5.3V
9V/14V

Slope
compensation
FB
VDD OVP
Burst Mode
Control

27.5V

33V

GND

OLP

43ms Delay

3.7V

Pin Description
Pin Num

I/O

Description

1
2

Pin Name
GND
FB

P
I

4
5
6

CS
VDD
GATE

I
P
O

Ground
Voltage feedback pin. The loop regulation is achieved by connecting a
photo-coupler to this pin. PWM duty cycle is determined by this pin voltage
and the current sense signal at Pin 3.
Set the switching frequency by connecting a resistor between RT and
GND. This pin has floating/short-to-GND protection.
Current sense input pin.
IC power supply pin.
Totem-pole gate driver output to drive the external MOSFET.

Absolute Maximum Ratings (Note 1)
Parameter
VDD DC Supply Voltage
VCC DC Clamp Current
GATE pin
FB, RT, CS voltage range
Package Thermal Resistance (SOT-26)
Package Thermal Resistance (DIP-8)
Package Thermal Resistance (SOP-8)
Maximum Junction Temperature
Operating Temperature Range

©SiFirst Technology

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-3-

Value

Unit

33
10
20
-0.3 to 7
250
90
150
150
-40 to 85

V
mA
V
V
o
C/W
o
C/W
o
C/W
o
C
o
C

SF1530_DS_V1.0

SF1530
Storage Temperature Range
Lead Temperature (Soldering, 10sec.)
ESD Capability, HBM (Human Body Model)
ESD Capability, MM (Machine Model)

-65 to 150
260
3
250

C
C
kV
V

Value

Unit

11 to 25
50 to 130
-40 to 85

V
kHz
o
C

Recommended Operation Conditions (Note 2)
Parameter
Supply Voltage, VDD
Operating Frequency
Operating Ambient Temperature

ELECTRICAL CHARACTERISTICS
(TA = 25OC, RT=100K ohm, VDD=18V, if not otherwise noted)

Symbol
Parameter
Supply Voltage Section (VDD Pin)
UVLO(ON)
UVLO(OFF)
I_Startup
I_VDD_Op
VDD_OVP
VDD_Clamp
T_Softstart

VDD Under Voltage
Lockout Exit (Startup)
VDD Under Voltage
Lockout Enter
VDD Start up Current
Operation Current
VDD Over Voltage
Protection trigger
VDD Zener Clamp
Voltage
Soft Start Time

Test Conditions

Min

Typ

Max

Unit

2.5
27.5

3.5
30

mA
V

VDD =12.5V, Measure
current into VDD
VFB=3V,CL=1nF
25
I(VDD ) = 15 mA

mSec

5.3

1.1

2.0
1.0

V/V
V

3.7

mSec

Kohm

Feedback Input Section(FB Pin)
VFB_Open

FB Open Voltage

IFB_Short

FB short circuit
current
PWM Input Gain
FB under voltage gate
clock is off.
Power Limiting FB
Threshold Voltage
Power limiting
Debounce Time
Input Impedance

AVCS
VFB_min_duty
VTH_PL
TD_PL
ZFB_IN

Short FB pin to GND,
measure current
ΔVFB /ΔVcs

Note 3

Current Sense Input Section (CS Pin)
Vth_OC_min
T_blanking
TD_OC

Internal current
limiting threshold
SENSE Input Leading
Edge Blanking Time
Over Current
Detection and Control
Delay

Zero duty cycle

0.70

CL=1nF at GATE,

0.75

0.80

250

nSec

Oscillator Section (RT Pin)
FOSC
RT_range
V_RT_open
∆F(shuffle)/Fosc
∆f_Temp
∆f_VDD

©SiFirst Technology

Normal Oscillation
Frequency
Operating RT Range
RT open voltage
Frequency shuffling
range
Frequency
Temperature Stability
Frequency Voltage

Note 4

KHZ

100
2.0

150

Kohm
V
%

-4

-20oC to 100 oC (Note 4)

VDD = 12-25V,

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SF1530_DS_V1.0

SF1530
Duty_max
F_BM

Stability
Maximum Duty cycle
Burst Mode Base
Frequency

80
22

%
KHZ

1
17.5

V
V
V

200
60

nSec
nSec

Gate Drive Output (GATE Pin)
VOL
VOH
VG_Clamp
T_r
T_f

Output Low Level
Output High Level
Output Clamp Voltage
Level
Output Rising Time
Output Falling Time

Io = 20 mA (sink)
Io = 20 mA (source)
VDD=24V
CL = 1nF
CL = 1nF

7.5

Note 1. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to
the device. These are stress ratings only, and functional operation of the device at these or any other
conditions beyond those indicated in the operational sections of the specifications is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Note 2. The device is not guaranteed to function outside its operating conditions.
Note 3. The OLP debounce time is proportional to the period of switching cycle.
Note 4. Guaranteed by design.

CHARACTERIZATION PLOTS

©SiFirst Technology

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-5-

SF1530_DS_V1.0

SF1530
OPERATION DESCRIPTION
SF1530 is a high performance, low cost, highly
integrated current mode PWM controller for offline
flyback converter applications. The built-in
advanced energy saving with high level protection
features improves the SMPS reliability and
performance without increasing the system cost.

◆ UVLO and Startup Operation
Fig.1 shows a typical startup circuitn. Before the IC
begins switching operation, it consumes only
startup current (typically 5uA) and current supplied
through the startup resistor Rst charges the VDD
hold-up capacitor Cdd. When VDD reaches UVLO
turn-on voltage of 14V(typical), SF1530 begins
switching and the IC current consumed increased
to 2mA (typical). The hold-up capacitor Cdd
continues to supply VDD before the energy can be
delivered from auxiliary winding Na. During this
process, VDD must not drop below UVLO turn-off
voltage (typical 9V). The selection of Rst and Cdd
should be a trade off between the power loss and
startup time.

◆ “Zero OCP/OPP Recovery Gap” Control
The definition of OCP or OPP recovery gap of a
power adaptor is illustrated in Fig.2.
At T0,
assuming an adaptor is at full loading mode. If the
loading keeps increasing, then the system will
output maximum power P_opp, which will trigger
OPP protection at the same time. After the OPP
protection is triggered, usually the system will enter
into the auto-recovery mode, in burst manner. If the
system
power
demand
decreases
below
P_recovery, then system will enter into normal
mode again, as shown in Fig.2. The difference
between P_opp and P_recovery is defined as “OPP
Recovery Gap”, which can cause system startup
failure especially in 90VAC full load startup.

AC IN
Np
Cbulk

Rst

Fig.2
Cdd

SF1530
1 GND

GATE

2 FB

VDD

3 RT

SF1530 can achieve “Zero OCP/OPP Recovery
Gap” in the whole universal AC input range using
SiFirst’s proprietary control algorithm.

◆ Synchronous Slope Compensation
InSF1530, the synchronous slope compensation
circuit is integrated by adding voltage ramp onto the
current sense input voltage for PWM generation.
This greatly improves the close loop stability at
CCM and prevents the sub-harmonic oscillation
and thus reduces the output ripple voltage.

Fig.1

◆ Oscillator with Frequency Shuffling

◆ Low Operating Current
The operating current in SF1530 is as small as
1.3mA (typical). The small operating current results
in higher efficiency and reduces the VDD hold-up
capacitance requirement.

◆ Soft Start
SF1530 features an internal 3ms (typical) soft start
that slowly increases the threshold of cycle-bycycle current limiting comparator during startup
sequence. It helps to prevent transformer saturation
and reduce the stress on the secondary diode
during startup. Every restart attempt is followed by
a soft start activation.

Connecting a resistor from RT pin to GND
according to the equation below to program the
normal switching frequency:

FOSC (KHz ) =

6500
RT(KΩ)

It can typically operate between 50kHz to 130kHz.
To improve system EMI performance, SF1530
operates the system with ±4% frequency shuffling
around setting frequency.

◆ Leading Edge Blanking (LEB)
Each time the power MOSFET is switched on, a
turn-on spike occurs across the sensing resistor.
The spike is caused by primary side capacitance
and secondary side rectifier reverse recovery. To
avoid premature termination of the switching pulse,

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-6-

SF1530_DS_V1.0

SF1530
an internal leading edge blanking circuit is built in.
During this blanking period (350ns, typical), the
PWM comparator is disabled and cannot switch off
the gate driver. Thus, external RC filter with a small
time constant is enough for current sensing.

◆ Frequency Reduction for Green Mode
Operation
When the loading is light, the IC will automatically
reduce the PWM switching frequency to achieve
high efficiency. In the whole frequency reduction
process, there is no audio noise generated.
PWM Frequency
(RT=100kΩ)

◆ Auto Recovery Mode Protection
As shown in Fig.5, once a fault condition is
detected, switching will stop. This will cause VDD to
fall because no power is delivered form the
auxiliary winding. When VDD falls to UVLO(off)
(typical 9V), the protection is reset and the
operating current reduces to the startup current,
which causes VDD to rise, as shown in Fig.4.
However, if the fault still exists, the system will
experience the above mentioned process. If the
fault has gone, the system resumes normal
operation. In this manner, the auto restart can
alternatively enable and disable the switching until
the fault condition is disappeared.

65kHz

22kHz

VFB
0
Burst
mode

Frequency
Reduction mode

Normal
mode

Fig.3

Fig.5

◆ Burst Mode Control
When the loading is very small, the system enters
into burst mode. When VFB drops below Vskip,
SF1530 will stop switching and output voltage
starts to drop, which causes the VFB to rise. Once
VFB rises above Vskip, switching resumes. Burst
mode control alternately enables and disables
switching, thereby reducing switching loss in
standby mode.

◆ VDD OVP(Over Voltage Protection)
VDD OVP (Over Voltage Protection) is
implemented in SF1530 and it is a protection of
auto-recovery mode.

◆ Over Load Protection (OLP)
When over load occurs, a fault is detected. If this
fault is present for more than 43ms (typical), the
protection will be triggered, the IC will experience
an auto-recovery mode protection as mentioned
above. The 43mS delay time is to prevent the false
trigger from the power-on and turn-off transient

◆ All Pins Floating Protection and RT Pin
Short-to-GND Protection
In SF1530, if pin floating situation or RT pin shortto-GND occurs, the protection is triggered
immediately and the system will experience the
process of auto-recovery mode protection.

◆ Soft Gate Drive
SF1530 has a fast totem-pole gate driver with
300mA capability. Cross conduction has been
avoided to minimize heat dissipation, increase
efficiency, and enhance reliability. An internal 17V
clamp is added for MOSFET gate protection at
higher than expected VDD input. A soft driving
waveform is implemented to minimize EMI.
Fig.4

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-7-

SF1530_DS_V1.0

SF1530
PACKAGE MECHANICAL DATA

Symbol
A
A1
A2
b
c
D
E
E1
e
e1
L
θ

Dimensions In Millimeters
Min
Max
1.000
1.300
0.000
0.150
1.000
1.200
0.300
0.500
0.100
0.200
2.800
3.020
1.500
1.700
2.600
3.000
0.950 (BSC)
1.800
2.000
0.300
0.600
0º
8º

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-8-

Dimensions In Inches
Min
Max
0.039
0.051
0.000
0.006
0.039
0.047
0.012
0.020
0.004
0.008
0.110
0.119
0.059
0.067
0.102
0.118
0.037 (BSC)
0.071
0.079
0.012
0.024
0º
8º

SF1530_DS_V1.0

SF1530

Symbol
A
A1
A2
B
B1
C
D
E
E1
e
L
E2

Dimensions In Millimeters
Min
Max
3.710
5.334
0.381
3.175
3.600
0.350
0.650
1.524 (BSC)
0.200
0.360
9.000
10.160
6.200
6.600
7.320
7.920
2.540 (BSC)
2.921
3.810
8.200
9.525

Dimensions In Inches
Min
Max
0.146
0.210
0.015
0.125
0.142
0.014
0.026
0.06 (BSC)
0.008
0.014
0.354
0.400
0.244
0.260
0.288
0.312
0.1 (BSC)
0.115
0.150
0.323
0.375

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-9-

SF1530_DS_V1.0

SF1530

Symbol
A
A1
A2
b
c
D
E
E1
e
L
θ

Dimensions In Millimeters
Min
Max
1.350
1.750
0.050
0.250
1.250
1.650
0.310
0.510
0.170
0.250
4.700
5.150
3.800
4.000
5.800
6.200
1.270 (BSC)
0.400
1.270
0º
8º

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Dimensions In Inches
Min
Max
0.053
0.069
0.002
0.010
0.049
0.065
0.012
0.020
0.006
0.010
0.185
0.203
0.150
0.157
0.228
0.244
0.05 (BSC)
0.016
0.050
0º
8º

SF1530_DS_V1.0

SF1530
IMPORTANT NOTICE
SiFirst Technology Nanhai, Ltd (SiFirst) reserves the right to make corrections, modifications, enhancements,
improvements and other changes to its products and services at any time and to discontinue any product or
service without notice. Customers should obtain the latest relevant information before placing orders and should
verify that such information is current and complete.
SiFirst warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with SiFirst’s standard warranty. Testing and other quality control techniques are used to the extent
SiFirst deems necessary to support this warranty. Except where mandated by government requirements,
testing of all parameters of each product is not necessarily performed.
SiFirst assumes no liability for application assistance or customer product design. Customers are responsible
for their products and applications using SiFirst’s components. To minimize the risks associated with customer
products and applications, customers should provide adequate design and operating safeguards.
Reproduction of SiFirst’s information in SiFirst’s data books or data sheets is permissible only if reproduction is
without alteration and is accompanied by all associated warranties, conditions, limitations, and notices.
Reproduction of this information with alteration is an unfair and deceptive business practice. SiFirst is not
responsible or liable for such altered documentation. Information of third parties may be subject to additional
restrictions.
Resale of SiFirst’s products or services with statements different from or beyond the parameters stated by
SiFirst for that product or service voids all express and any implied warranties for the associated SiFirst’s
product or service and is an unfair and deceptive business practice. SiFirst is not responsible or liable for any
such statements.
SiFirst’s products are neither designed nor intended for use in military applications. SiFirst will not be held liable
for any damages or claims resulting from the use of its products in military applications.
SiFirst’s products are not designed to be used as components in devices intended to support or sustain human
life. SiFirst will not be held liable for any damages or claims resulting from the use of its products in medical
applications.

For the latest updates, please visit our website: www.sifirsttech.com

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SF1530_DS_V1.0

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