TLV320AIC3256 Application Reference (Rev. A) Slau306a Guide
User Manual:
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- 1 TLV320AIC3256 Overview
- 2 TLV320AIC3256 Application
- 2.1 Terminal Descriptions
- 2.2 Analog Audio I/O
- 2.3 ADC
- 2.3.1 ADC Signal Routing
- 2.3.2 ADC Gain Setting
- 2.3.3 ADC Decimation Filtering and Signal Processing Overview
- 2.3.3.1 Signal Processing Blocks – Details
- 2.3.3.1.1 First-Order IIR, AGC, Filter A
- 2.3.3.1.2 5 Biquads, First-Order IIR, AGC, Filter A
- 2.3.3.1.3 25 Tap FIR, First-Order IIR, AGC, Filter A
- 2.3.3.1.4 First-Order IIR, AGC, Filter B
- 2.3.3.1.5 3 Biquads, First-Order IIR, AGC, Filter B
- 2.3.3.1.6 20 Tap FIR, First-Order IIR, AGC, Filter B
- 2.3.3.1.7 First-Order IIR, AGC, Filter C
- 2.3.3.1.8 5 Biquads, First-Order IIR, AGC, Filter C
- 2.3.3.1.9 25 Tap FIR, First-Order IIR, AGC, Filter C
- 2.3.3.1.10 User Programmable Filters
- 2.3.3.1.11 Decimation Filter
- 2.3.3.1.12 ADC Data Interface
- 2.3.3.2 ADC Special Functions
- 2.3.3.3 ADC Setup
- 2.3.3.1 Signal Processing Blocks – Details
- 2.4 DAC
- 2.4.1 Processing Blocks – Details
- 2.4.1.1 3 Biquads, Interpolation Filter A
- 2.4.1.2 6 Biquads, 1st order IIR, DRC, Interpolation Filter A or B
- 2.4.1.3 6 Biquads, 1st order IIR, Interpolation Filter A or B
- 2.4.1.4 IIR, Interpolation Filter B or C
- 2.4.1.5 4 Biquads, DRC, Interpolation Filter B
- 2.4.1.6 4 Biquads, Interpolation Filter B
- 2.4.1.7 4 Biquads, 1st order IIR, DRC, Interpolation Filter C
- 2.4.1.8 4 Biquads, 1st order IIR, Interpolation Filter C
- 2.4.1.9 2 Biquads, 3D, Interpolation Filter A
- 2.4.1.10 5 Biquads, DRC, 3D, Interpolation Filter A
- 2.4.1.11 5 Biquads, DRC, 3D, Beep Generator, Interpolation Filter A
- 2.4.2 User Programmable Filters
- 2.4.3 Interpolation Filters
- 2.4.4 DAC Gain Setting
- 2.4.5 DAC Special Functions
- 2.4.6 DAC Setup
- 2.4.1 Processing Blocks – Details
- 2.5 PowerTune
- 2.5.0.1 PowerTune Modes
- 2.5.0.2 ADC Power Consumption
- 2.5.0.2.1 ADC, Stereo, 48kHz, Highest Performance, DVdd = 1.8V, AVdd = 1.8V
- 2.5.0.2.2 ADC, Stereo, 48kHz, DVdd = 1.8V, AVdd = 1.8V
- 2.5.0.2.3 ADC, Stereo, 48kHz, Lowest Power Consumption
- 2.5.0.2.4 ADC, Mono, 48kHz, Highest Performance, DVdd = 1.8V, AVdd = 1.8V
- 2.5.0.2.5 ADC, Mono, 48kHz, DVdd = 1.8V, AVdd = 1.8V
- 2.5.0.2.6 ADC, Mono, 48 kHz, Lowest Power Consumption,
- 2.5.0.2.7 ADC, Stereo, 8kHz, Highest Performance, DVdd = 1.8V, AVdd = 1.8V
- 2.5.0.2.8 ADC, Stereo, 8kHz, DVdd = 1.8V, AVdd = 1.8V
- 2.5.0.2.9 ADC, Stereo, 8kHz, Lowest Power Consumption,
- 2.5.0.2.10 ADC, Mono, 8kHz, Highest Performance, DVdd = 1.8V, AVdd = 1.8V
- 2.5.0.2.11 ADC, Mono, 8kHz, DVdd = 1.8V, AVdd = 1.8V
- 2.5.0.2.12 ADC, Mono, 8kHz, Lowest Power Consumption
- 2.5.0.2.13 ADC, Stereo, 192kHz, Highest Performance, DVdd = 1.8V, AVdd = 1.8V
- 2.5.0.2.14 ADC, Stereo, 192kHz, Lowest Power Consumption
- 2.5.0.3 DAC Power Consumption
- 2.5.0.3.1 DAC, Stereo, 48kHz, Highest Performance, DVdd = 1.8V, AVdd = 1.8V
- 2.5.0.3.2 DAC, Stereo, 48kHz, Lowest Power Consumption
- 2.5.0.3.3 DAC, Mono, 48kHz, Highest Performance, DVdd = 1.8V, AVdd = 1.8V
- 2.5.0.3.4 DAC, Mono, 48kHz, Lowest Power Consumption
- 2.5.0.3.5 DAC, Stereo, 8kHz, Highest Performance, DVdd = 1.8V, AVdd = 1.8V
- 2.5.0.3.6 DAC, Stereo, 8kHz, Lowest Power Consumption
- 2.5.0.3.7 DAC, Mono, 8kHz, Highest Performance, DVdd = 1.8V, AVdd = 1.8V
- 2.5.0.3.8 DAC, Mono, 8kHz, Lowest Power Consumption
- 2.5.0.3.9 DAC, Stereo, 192kHz, DVdd = 1.8V, AVdd = 1.8V
- 2.5.0.3.10 DAC, Stereo, 192kHz, Lowest Power Consumption
- 2.6 Audio Digital I/O Interface
- 2.7 Clock Generation and PLL
- 2.8 Control Interfaces
- 2.9 Power Supply
- 2.10 Reference Voltage
- 2.11 Device Special Functions
- 2.12 miniDSP
- 3 Device Initialization
- 4 Example Setups
- 5 Register Map
- 5.1 Register Map Summary
- 5.2 Page 0 Registers
- 5.2.1 Page 0 / Register 0: Page Select Register - 0x00 / 0x00
- 5.2.2 Page 0 / Register 1: Software Reset Register - 0x00 / 0x01
- 5.2.3 Page 0 / Register 2: Reserved Register - 0x00 / 0x02
- 5.2.4 Page 0 / Register 3: Reserved Register - 0x00 / 0x03
- 5.2.5 Page 0 / Register 4: Clock Setting Register 1, Multiplexers - 0x00 / 0x04
- 5.2.6 Page 0 / Register 5: Clock Setting Register 2, PLL P&R Values - 0x00 / 0x05
- 5.2.7 Page 0 / Register 6: Clock Setting Register 3, PLL J Values - 0x00 / 0x06
- 5.2.8 Page 0 / Register 7: Clock Setting Register 4, PLL D Values (MSB) - 0x00 / 0x07
- 5.2.9 Page 0 / Register 8: Clock Setting Register 5, PLL D Values (LSB) - 0x00 / 0x08
- 5.2.10 Page 0 / Register 9-10: Reserved Register - 0x00 / 0x09-0x0A
- 5.2.11 Page 0 / Register 11: Clock Setting Register 6, NDAC Values - 0x00 / 0x0B
- 5.2.12 Page 0 / Register 12: Clock Setting Register 7, MDAC Values - 0x00 / 0x0C
- 5.2.13 Page 0 / Register 13: DAC OSR Setting Register 1, MSB Value - 0x00 / 0x0D
- 5.2.14 Page 0 / Register 14: DAC OSR Setting Register 2, LSB Value - 0x00 / 0x0E
- 5.2.15 Page 0 / Register 15: miniDSP_D Instruction Control Register 1 - 0x00 / 0x0F
- 5.2.16 Page 0 / Register 16: miniDSP_D Instruction Control Register 2 - 0x00 / 0x10
- 5.2.17 Page 0 / Register 17: miniDSP_D Interpolation Factor Setting Register - 0x00 / 0x11
- 5.2.18 Page 0 / Register 18: Clock Setting Register 8, NADC Values - 0x00 / 0x12
- 5.2.19 Page 0 / Register 19: Clock Setting Register 9, MADC Values - 0x00 / 0x13
- 5.2.20 Page 0 / Register 20: ADC Oversampling (AOSR) Register - 0x00 / 0x14
- 5.2.21 Page 0 / Register 21: miniDSP_A Instruction Control Register 1 - 0x00 / 0x15
- 5.2.22 Page 0 / Register 22: miniDSP_A Instruction Control Register 2 - 0x00 / 0x16
- 5.2.23 Page 0 / Register 23: miniDSP_A Decimation Factor Setting Register - 0x00 / 0x17
- 5.2.24 Page 0 / Register 24: Reserved Register - 0x00 / 0x18
- 5.2.25 Page 0 / Register 25: Clock Setting Register 10, Multiplexers - 0x00 / 0x19
- 5.2.26 Page 0 / Register 26: Clock Setting Register 11, CLKOUT M divider value - 0x00 / 0x1A
- 5.2.27 Page 0 / Register 27: Audio Interface Setting Register 1 - 0x00 / 0x1B
- 5.2.28 Page 0 / Register 28: Audio Interface Setting Register 2, Data offset setting - 0x00 / 0x1C
- 5.2.29 Page 0 / Register 29: Audio Interface Setting Register 3 - 0x00 / 0x1D
- 5.2.30 Page 0 / Register 30: Clock Setting Register 12, BCLK N Divider - 0x00 / 0x1E
- 5.2.31 Page 0 / Register 31: Audio Interface Setting Register 4, Secondary Audio Interface - 0x00 / 0x1F
- 5.2.32 Page 0 / Register 32: Audio Interface Setting Register 5 - 0x00 / 0x20
- 5.2.33 Page 0 / Register 33: Audio Interface Setting Register 6 - 0x00 / 0x21
- 5.2.34 Page 0 / Register 34: Digital Interface Misc. Setting Register - 0x00 / 0x22
- 5.2.35 Page 0 / Register 35: Reserved Register - 0x00 / 0x23
- 5.2.36 Page 0 / Register 36: ADC Flag Register - 0x00 / 0x24
- 5.2.37 Page 0 / Register 37: DAC Flag Register 1 - 0x00 / 0x25
- 5.2.38 Page 0 / Register 38: DAC Flag Register 2 - 0x00 / 0x26
- 5.2.39 Page 0 / Register 39-41: Reserved Register - 0x00 / 0x27-0x29
- 5.2.40 Page 0 / Register 42: Sticky Flag Register 1 - 0x00 / 0x2A
- 5.2.41 Page 0 / Register 43: Interrupt Flag Register 1 - 0x00 / 0x2B
- 5.2.42 Page 0 / Register 44: Sticky Flag Register 2 - 0x00 / 0x2C
- 5.2.43 Page 0 / Register 45: Sticky Flag Register 3 - 0x00 / 0x2D
- 5.2.44 Page 0 / Register 46: Interrupt Flag Register 2 - 0x00 / 0x2E
- 5.2.45 Page 0 / Register 47: Interrupt Flag Register 3 - 0x00 / 0x2F
- 5.2.46 Page 0 / Register 48: INT1 Interrupt Control Register - 0x00 / 0x30
- 5.2.47 Page 0 / Register 49: INT2 Interrupt Control Register - 0x00 / 0x31
- 5.2.48 Page 0 / Register 50-51: Reserved Register - 0x00 / 0x32-0x33
- 5.2.49 Page 0 / Register 52: GPIOorMFP5 Control Register - 0x00 / 0x34
- 5.2.50 Page 0 / Register 53: DOUT or MFP2 Function Control Register - 0x00 / 0x35
- 5.2.51 Page 0 / Register 54: DIN or MFP1 Function Control Register - 0x00 / 0x36
- 5.2.52 Page 0 / Register 55: MISO or MFP4 Function Control Register - 0x00 / 0x37
- 5.2.53 Page 0 / Register 56: SCLK or MFP3 Function Control Register - 0x00 / 0x38
- 5.2.54 Page 0 / Register 57-59: Reserved Registers - 0x00 / 0x39-0x3B
- 5.2.55 Page 0 / Register 60: DAC Signal Processing Block Control Register - 0x00 / 0x3C
- 5.2.56 Page 0 / Register 61: ADC Signal Processing Block Control Register - 0x00 / 0x3D
- 5.2.57 Page 0 / Register 62: miniDSP_A and miniDSP_D Configuration Register - 0x00 / 0x3E
- 5.2.58 Page 0 / Register 63: DAC Channel Setup Register 1 - 0x00 / 0x3F
- 5.2.59 Page 0 / Register 64: DAC Channel Setup Register 2 - 0x00 / 0x40
- 5.2.60 Page 0 / Register 65: Left DAC Channel Digital Volume Control Register - 0x00 / 0x41
- 5.2.61 Page 0 / Register 66: Right DAC Channel Digital Volume Control Register - 0x00 / 0x42
- 5.2.62 Page 0 / Register 67: Headset Detection Configuration Register - 0x00 / 0x43
- 5.2.63 Page 0 / Register 68: DRC Control Register 1 - 0x00 / 0x44
- 5.2.64 Page 0 / Register 69: DRC Control Register 2 - 0x00 / 0x45
- 5.2.65 Page 0 / Register 70: DRC Control Register 3 - 0x00 / 0x46
- 5.2.66 Page 0 / Register 71: Beep Generator Register 1 - 0x00 / 0x47
- 5.2.67 Page 0 / Register 72: Beep Generator Register 2 - 0x00 / 0x48
- 5.2.68 Page 0 / Register 73: Beep Generator Register 3 - 0x00 / 0x49
- 5.2.69 Page 0 / Register 74: Beep Generator Register 4 - 0x00 / 0x4A
- 5.2.70 Page 0 / Register 75: Beep Generator Register 5 - 0x00 / 0x4B
- 5.2.71 Page 0 / Register 76: Beep Generator Register 6 - 0x00 / 0x4C
- 5.2.72 Page 0 / Register 77: Beep Generator Register 7 - 0x00 / 0x4D
- 5.2.73 Page 0 / Register 78: Beep Generator Register 8 - 0x00 / 0x4E
- 5.2.74 Page 0 / Register 79: Beep Generator Register 9 - 0x00 / 0x4F
- 5.2.75 Page 0 / Register 80: Reserved Register - 0x00 / 0x50
- 5.2.76 Page 0 / Register 81: ADC Channel Setup Register - 0x00 / 0x51
- 5.2.77 Page 0 / Register 82: ADC Fine Gain Adjust Register - 0x00 / 0x52
- 5.2.78 Page 0 / Register 83: Left ADC Channel Volume Control Register - 0x00 / 0x53
- 5.2.79 Page 0 / Register 84: Right ADC Channel Volume Control Register - 0x00 / 0x54
- 5.2.80 Page 0 / Register 85: ADC Phase Adjust Register - 0x00 / 0x55
- 5.2.81 Page 0 / Register 86: Left Channel AGC Control Register 1 - 0x00 / 0x56
- 5.2.82 Page 0 / Register 87: Left Channel AGC Control Register 2 - 0x00 / 0x57
- 5.2.83 Page 0 / Register 88: Left Channel AGC Control Register 3 - 0x00 / 0x58
- 5.2.84 Page 0 / Register 89: Left Channel AGC Control Register 4 - 0x00 / 0x59
- 5.2.85 Page 0 / Register 90: Left Channel AGC Control Register 5 - 0x00 / 0x5A
- 5.2.86 Page 0 / Register 91: Left Channel AGC Control Register 6 - 0x00 / 0x5B
- 5.2.87 Page 0 / Register 92: Left Channel AGC Control Register 7 - 0x00 / 0x5C
- 5.2.88 Page 0 / Register 93: Left Channel AGC Control Register 8 - 0x00 / 0x5D
- 5.2.89 Page 0 / Register 94: Right Channel AGC Control Register 1 - 0x00 / 0x5E
- 5.2.90 Page 0 / Register 95: Right Channel AGC Control Register 2 - 0x00 / 0x5F
- 5.2.91 Page 0 / Register 96: Right Channel AGC Control Register 3 - 0x00 / 0x60
- 5.2.92 Page 0 / Register 97: Right Channel AGC Control Register 4 - 0x00 / 0x61
- 5.2.93 Page 0 / Register 98: Right Channel AGC Control Register 5 - 0x00 / 0x62
- 5.2.94 Page 0 / Register 99: Right Channel AGC Control Register 6 - 0x00 / 0x63
- 5.2.95 Page 0 / Register 100: Right Channel AGC Control Register 7 - 0x00 / 0x64
- 5.2.96 Page 0 / Register 101: Right Channel AGC Control Register 8 - 0x00 / 0x65
- 5.2.97 Page 0 / Register 102: DC Measurement Register 1 - 0x00 / 0x66
- 5.2.98 Page 0 / Register 103: DC Measurement Register 2 - 0x00 / 0x67
- 5.2.99 Page 0 / Register 104: Left Channel DC Measurement Output Register 1 - 0x00 / 0x68
- 5.2.100 Page 0 / Register 105: Left Channel DC Measurement Output Register 2 - 0x00 / 0x69
- 5.2.101 Page 0 / Register 106: Left Channel DC Measurement Output Register 3 - 0x00 / 0x6A
- 5.2.102 Page 0 / Register 107: Right Channel DC Measurement Output Register 1 - 0x00 / 0x6B
- 5.2.103 Page 0 / Register 108: Right Channel DC Measurement Output Register 2 - 0x00 / 0x6C
- 5.2.104 Page 0 / Register 109: Right Channel DC Measurement Output Register 3 - 0x00 / 0x6D
- 5.2.105 Page 0 / Register 110-127: Reserved Register - 0x00 / 0x6E-0x7F
- 5.3 Page 1 Registers
- 5.3.1 Page 1 / Register 0: Page Select Register - 0x01 / 0x00
- 5.3.2 Page 1 / Register 1: Power Configuration Register 1 - 0x01 / 0x01
- 5.3.3 Page 1 / Register 2: Power Configuration Register 2 - 0x01 / 0x02
- 5.3.4 Page 1 / Register 3: Playback Configuration Register 1 - 0x01 / 0x03
- 5.3.5 Page 1 / Register 4: Playback Configuration Register 2 - 0x01 / 0x04
- 5.3.6 Page 1 / Register 5-8: Reserved Register - 0x01 / 0x05-0x08
- 5.3.7 Page 1 / Register 9: Output Driver Power Control Register - 0x01 / 0x09
- 5.3.8 Page 1 / Register 10: Common Mode Control Register - 0x01 / 0x0A
- 5.3.9 Page 1 / Register 11: Over Current Protection Configuration Register - 0x01 / 0x0B
- 5.3.10 Page 1 / Register 12: HPL Routing Selection Register - 0x01 / 0x0C
- 5.3.11 Page 1 / Register 13: HPR Routing Selection Register - 0x01 / 0x0D
- 5.3.12 Page 1 / Register 14: LOL Routing Selection Register - 0x01 / 0x0E
- 5.3.13 Page 1 / Register 15: LOR Routing Selection Register - 0x01 / 0x0F
- 5.3.14 Page 1 / Register 16: HPL Driver Gain Setting Register - 0x01 / 0x10
- 5.3.15 Page 1 / Register 17: HPR Driver Gain Setting Register - 0x01 / 0x11
- 5.3.16 Page 1 / Register 18: LOL Driver Gain Setting Register - 0x01 / 0x12
- 5.3.17 Page 1 / Register 19: LOR Driver Gain Setting Register - 0x01 / 0x13
- 5.3.18 Page 1 / Register 20: Headphone Driver Startup Control Register - 0x01 / 0x14
- 5.3.19 Page 1 / Register 21: Reserved Register - 0x01 / 0x15
- 5.3.20 Page 1 / Register 22: IN1L to HPL Volume Control Register - 0x01 / 0x16
- 5.3.21 Page 1 / Register 23: IN1R to HPR Volume Control Register - 0x01 / 0x17
- 5.3.22 Page 1 / Register 24: Mixer Amplifier Left Volume Control Register - 0x01 / 0x18
- 5.3.23 Page 1 / Register 25: Mixer Amplifier Right Volume Control Register - 0x01 / 0x19
- 5.3.24 Page 1 / Register 26-50: Reserved Register - 0x01 / 0x1A-0x32
- 5.3.25 Page 1 / Register 51: MICBIAS Configuration Register - 0x01 / 0x33
- 5.3.26 Page 1 / Register 52: Left MICPGA Positive Terminal Input Routing Configuration Register - 0x01 / 0x34
- 5.3.27 Page 1 / Register 53: Reserved Register - 0x01 / 0x35
- 5.3.28 Page 1 / Register 54: Left MICPGA Negative Terminal Input Routing Configuration Register - 0x01 / 0x36
- 5.3.29 Page 1 / Register 55: Right MICPGA Positive Terminal Input Routing Configuration Register - 0x01 / 0x37
- 5.3.30 Page 1 / Register 56: Reserved Register - 0x01 / 0x38
- 5.3.31 Page 1 / Register 57: Right MICPGA Negative Terminal Input Routing Configuration Register - 0x01 / 0x39
- 5.3.32 Page 1 / Register 58: Floating Input Configuration Register - 0x01 / 0x3A
- 5.3.33 Page 1 / Register 59: Left MICPGA Volume Control Register - 0x01 / 0x3B
- 5.3.34 Page 1 / Register 60: Right MICPGA Volume Control Register - 0x01 / 0x3C
- 5.3.35 Page 1 / Register 61: ADC Power Tune Configuration Register - 0x01 / 0x3D
- 5.3.36 Page 1 / Register 62: ADC Analog Volume Control Flag Register - 0x01 / 0x3E
- 5.3.37 Page 1 / Register 63: DAC Analog Gain Control Flag Register - 0x01 / 0x3F
- 5.3.38 Page 1 / Register 64-70: Reserved Register - 0x01 / 0x40-0x46
- 5.3.39 Page 1 / Register 71: Analog Input Quick Charging Configuration Register - 0x01 / 0x47
- 5.3.40 Page 1 / Register 72-122: Reserved Register - 0x01 / 0x48-0x7A
- 5.3.41 Page 1 / Register 123: Reference Power-up Configuration Register - 0x01 / 0x7B
- 5.3.42 Page 1 / Register 124: Charge Pump Control Register - 0x01 / 0x7C
- 5.3.43 Page 1 / Register 125: Headphone Driver Configuration Register - 0x01 / 0x7D
- 5.3.44 Page 1 / Register 126-127: Reserved Register - 0x01 / 0x7E-0x7F
- 5.4 Page 8 Registers
- 5.5 Page 9-16 Registers
- 5.6 Page 26-34 Registers
- 5.7 Page 44 Registers
- 5.8 Page 45-52 Registers
- 5.9 Page 62-70 Registers
- 5.10 Page 80-114 Registers
- 5.11 Page 152-186 Registers
- 5.12 ADC Coefficients A+B
- 5.13 ADC Defaults
- 5.14 DAC Coefficients A+B
- 5.15 DAC Defaults
- 5.16 ADC miniDSP Instructions
- 5.17 DAC miniDSP Instructions