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S71161-06-000 2/02 504

The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.

Intel is a registered trademark of Intel Corporation.

These specifications are subject to change without notice.

Advance Information

FEATURES:

• Firmware Hub for Intel 8xx Chipsets

• 2 Mbit, 3 Mbit, 4 Mbit, or 8 Mbit SuperFlash

memory array for code/data storage

– SST49LF002A: 256K x8 (2 Mbit)

– SST49LF003A: 384K x8 (3 Mbit)

– SST49LF004A: 512K x8 (4 Mbit)

– SST49LF008A: 1024K x8 (8 Mbit)

• Flexible Erase Capability

– Uniform 4 KByte Sectors

– Uniform 16 KByte overlay blocks for

SST49LF002A

– Uniform 64 KByte overlay blocks for

SST49LF003A/004A/008A

– Top Boot Block protection

- 16 KByte for SST49LF002A

- 64 KByte for SST49LF003A/004A/008A

– Chip-Erase for PP Mode Only

• Single 3.0-3.6V Read and Write Operations

• Superior Reliability

– Endurance:100,000 Cycles (typical)

– Greater than 100 years Data Retention

• Low Power Consumption

– Active Read Current: 6 mA (typical)

– Standby Current: 10 µA (typical)

• Fast Sector-Erase/Byte-Program Operation

– Sector-Erase Time: 18 ms (typical)

– Block-Erase Time: 18 ms (typical)

– Chip-Erase Time: 70 ms (typical)

– Byte-Program Time: 14 µs (typical)

– Chip Rewrite Time:

SST49LF002A: 4 seconds (typical)

SST49LF003A: 6 seconds (typical)

SST49LF004A: 8 seconds (typical)

SST49LF008A: 15 seconds (typical)

– Single-pulse Program or Erase

– Internal timing generation

• Two Operational Modes

– Firmware Hub Interface (FWH) Mode for

in-system operation

– Parallel Programming (PP) Mode for fast

production programming

• Firmware Hub Hardware Interface Mode

– 5-signal communication interface supporting

byte Read and Write

– 33 MHz clock frequency operation

– WP# and TBL# pins provide hardware write

protect for entire chip and/or top Boot Block

– Block Locking Register for all blocks

– Standard SDP Command Set

– Data# Polling and Toggle Bit for End-of-Write

detection

– 5 GPI pins for system design flexibility

– 4 ID pins for multi-chip selection

• Parallel Programming (PP) Mode

– 11-pin multiplexed address and

8-pin data I/O interface

– Supports fast In-System or PROM programming

for manufacturing

• CMOS and PCI I/O Compatibility

• Packages Available

– 32-lead PLCC

– 32-lead TSOP (8mm x 14mm)

PRODUCT DESCRIPTION

The SST49LF00xA flash memory devices are designed

to be read-compatible with the Intel 82802 Firmware Hub

(FWH) device for PC-BIOS application. It provides pro-

tection for the storage and update of code and data in

addition to adding system design flexibility through five

general purpose inputs. Two interface modes are sup-

ported by the SST49LF00xA: Firmware Hub (FWH)

Interface Mode for In-System programming and Parallel

Programming (PP) Mode for fast factory programming of

PC-BIOS applications.

The SST49LF00xA flash memory devices are manufac-

tured with SST’s proprietary, high performance Super-

Flash Technology. The split-gate cell design and thick

oxide tunneling injector attain better reliability and manu-

facturability compared with alternate approaches. The

SST49LF00xA devices significantly improve performance

and reliability, while lowering power consumption. The

SST49LF00xA devices write (Program or Erase) with a

single 3.0-3.6V power supply. It uses less energy during

Erase and Program than alternative flash memory tech-

nologies. The total energy consumed is a function of the

applied voltage, current and time of application. Since for

2 Mbit / 3 Mbit / 4 Mbit / 8 Mbit Firmware Hub

SST49LF002A / SST49LF003A / SST49LF004A / SST49LF008A

SST49LF002A / 003A / 004A / 008A2Mb / 3Mb / 4Mb / 8Mb Firmware Hub for Intel 8xx Chipsets

Advance Information

2 Mbit / 3 Mbit / 4 Mbit / 8 Mbit Firmware Hub

SST49LF002A / SST49LF003A / SST49LF004A / SST49LF008A

any given voltage range, the SuperFlash technology uses

less current to program and has a shorter Erase time, the

total energy consumed during any Erase or Program oper-

ation is less than alternative flash memory technologies.

The SST49LF00xA products provide a maximum Byte-

Program time of 20 µsec. The entire memory can be

erased and programmed byte-by-byte typically in 15 sec-

onds for an 8-Mbit device, when using status detection

features such as Toggle Bit or Data# Polling to indicate the

completion of Program operation. The SuperFlash tech-

nology provides fixed Erase and Program time, indepen-

dent of the number of Erase/Program cycles that have

performed. Therefore the system software or hardware

does not have to be calibrated or correlated to the cumu-

lated number of Erase/Program cycles as is necessary

with alternative flash memory technologies, whose Erase

and Program time increase with accumulated Erase/Pro-

gram cycles.

To protect against inadvertent write, the SST49LF00xA

devices employ hardware and software data (SDP) protec-

tion schemes. It is offered with typical endurance of

100,000 cycles. Data retention is rated at greater than 100

years.

To meet high density, surface mount requirements, the

SST49LF00xA device is offered in 32-lead TSOP and 32-

lead PLCC packages. See Figures 7 and 8 for pin assign-

ments and Table 8 for pin descriptions.

Mode Selection and Description

The SST49LF00xA flash memory devices can operate in

two distinct interface modes: the Firmware Hub Interface

(FWH) mode and the Parallel Programming (PP) mode.

The IC (Interface Configuration pin) is used to set the

interface mode selection. If the IC pin is set to logic High,

the device is in PP mode; while if the IC pin is set Low,

the device is in the FWH mode. The IC selection pin must

be configured prior to device operation. The IC pin is

internally pulled down if the pin is not connected. In FWH

mode, the device is configured to interface with its host

using Intel’s Firmware Hub proprietary protocol. Commu-

nication between Host and the SST49LF00xA occurs via

the 4-bit I/O communication signals, FWH [3:0] and the

FWH4. In PP mode, the device is programmed via an 11-

bit address and an 8-bit data I/O parallel signals. The

address inputs are multiplexed in row and column

selected by control signal R/C# pin. The column

addresses are mapped to the higher internal addresses,

and the row addresses are mapped to the lower internal

addresses. See the Device Memory Maps in Figures 3

through 6 for address assignments.

FIRMWARE HUB (FWH) MODE

Device Operation

The FWH mode uses a 5-signal communication interface,

FWH[3:0] and FWH4, to control operations of the

SST49LF00xA. Operations such as Memory Read and

Memory Write uses Intel FWH propriety protocol. JEDEC

Standard SDP (Software Data Protection) Byte-Program,

Sector-Erase and Block-Erase command sequences are

incorporated into the FWH memory cycles. Chip-Erase is

only available in PP Mode.

The device enters standby mode when FWH4 is high and

no internal operation is in progress. The device is in ready

mode when FWH4 is low and no activity is on the FWH bus.

Firmware Hub Interface Cycles

Addresses and data are transferred to and from the

SST49LF00xA by a series of “fields,” where each field con-

tains 4 bits of data. ST49LF00xA supports only single-byte

read and writes, and all fields are one clock cycle in length.

Field sequences and contents are strictly defined for Read

and Write operations. Addresses in this section refer to

addresses as seen from the SST49LF00xA’s “point of

view,” some calculation will be required to translate these to

the actual locations in the memory map (and vice versa) if

multiple memory device is used on the bus. Tables 1 and 2

list the field sequences for Read and Write cycles.

Advance Information

2 Mbit / 3 Mbit / 4 Mbit / 8 Mbit Firmware Hub

SST49LF002A / SST49LF003A / SST49LF004A / SST49LF008A

FIGURE 1: SINGLE-BYTE READ WAVEFORMS

TABLE 1: FWH READ CYCLE

Clock

Cycle

Field

Name

Field Contents

FWH[3:0]1

FWH[3:0]

Direction Comments

1 START 1101 IN FWH4 must be active (low) for the part to respond. Only the

last start field (before FWH4 transitioning high) should be

recognized. The START field contents indicate a FWH

memory Read cycle.

2 IDSEL 0000 to 1111 IN Indicates which FWH device should respond. If the to IDSEL (ID

select) field matches the value ID[3:0], then that particular device

will respond to the whole bus cycle.

3-9 IMADDR YYYY IN These seven clock cycles make up the 28-bit memory

address. YYYY is one nibble of the entire address.

Addresses are transferred most-significant nibble first.

10 IMSIZE 0000 (1 byte) IN A field of this size indicates how many bytes will be or trans-

ferred during multi-byte operations. The SST49LF00xA will

only support single-byte operation. IMSIZE=0000b

11 TAR0 1111 IN

then Float

In this clock cycle, the master (Intel ICH) has driven the bus

then float to all ‘1’s and then floats the bus, prior to the next

clock cycle. This is the first part of the bus “turnaround

cycle.”

12 TAR1 1111 (float) Float

then OUT

The SST49LF00xA takes control of the bus during this

cycle. During the next clock cycle, it will be driving “sync

data.”

13 RSYNC 0000 (READY) OUT During this clock cycle, the FWH will generate a “ready-

sync” (RSYNC) indicating that the least-significant nibble of

the least-significant byte will be available during the next

clock cycle.

14 DATA YYYY OUT YYYY is the least-significant nibble of the least-significant

data byte.

15 DATA YYYY OUT YYYY is the most-significant nibble of the least-significant

data byte.

16 TAR0 1111 OUT

then Float

In this clock cycle, the SST49LF00xA has driven the bus to

all ones and then floats the bus prior to the next clock cycle.

This is the first part of the bus “turnaround cycle.”

17 TAR1 1111 (float) Float then

The master (Intel ICH) resumes control of the bus during

this cycle.

T1.3 504

1. Field contents are valid on the rising edge of the present clock cycle.

CLK

FWH4

FWH[3:0]

504 ILL F59.1

STR TAR RSYNCIMSIMADDRIDS DATA TAR

Advance Information

2 Mbit / 3 Mbit / 4 Mbit / 8 Mbit Firmware Hub

SST49LF002A / SST49LF003A / SST49LF004A / SST49LF008A

FIGURE 2: WRITE WAVEFORMS

TABLE 2: FWH WRITE CYCLE

Clock

Cycle

Field

Name

Field Contents

FWH[3:0]1

FWH[3:0]

Direction Comments

1 START 1110 IN FWH4 must be active (low) for the part to respond.

Only the last start field (before FWH4 transitioning

high) should be recognized. The START field contents

indicate a FWH memory Read cycle.

2 IDSEL 0000 to 1111 IN Indicates which SST49LF00xA device should

respond. If the IDSEL (ID select) field matches the

value ID[3:0], then that particular device will respond

to the whole bus cycle.

3-9 IMADDR YYYY IN These seven clock cycles make up the 28-bit memory

address. YYYY is one nibble of the entire address.

Addresses are transferred most-significant nibble first.

10 IMSIZE 0000 (1 byte) IN This size field indicates how many bytes will be

transferred during multi-byte operations. The FWH

only supports single-byte writes. IMSIZE=0000b

11 DATA YYYY IN This field is the least-significant nibble of the data byte.

This data is either the data to be programmed into the

flash memory or any valid flash command.

12 DATA YYYY IN This field is the most-significant nibble of the data byte.

13 TAR0 1111 IN then Float In this clock cycle, the master (Intel ICH) has driven the

then float bus to all ‘1’s and then floats the bus prior to

the next clock cycle. This is the first part of the bus

“turnaround cycle.”

14 TAR1 1111 (float) Float then OUT The SST49LF00xA takes control of the bus during this

cycle. During the next clock cycle it will be driving the

“sync” data.

15 RSYNC 0000 OUT The SST49LF00xA outputs the values 0000, indicat-

ing that it has received data or a flash command.

16 TAR0 1111 OUT then Float In this clock cycle, the SST49LF00xA has driven the

bus to all then float ‘1’s and then floats the bus prior to

the next clock cycle. This is the first part of the bus

“turnaround cycle.”

17 TAR1 1111 (float) Float then IN The master (Intel ICH) resumes control of the bus during

this cycle.

T2.4 504

1. Field contents are valid on the rising edge of the present clock cycle.

CLK

FWH4

FWH[3:0]

504 ILL F60.1

STR DATA TARTAR

RSYNC

IMSIMADDRIDS

Advance Information

2 Mbit / 3 Mbit / 4 Mbit / 8 Mbit Firmware Hub

SST49LF002A / SST49LF003A / SST49LF004A / SST49LF008A

Abort Mechanism

If FWH4 is driven low for one or more clock cycles during a

FWH cycle, the cycle will be terminated and the device will

wait for the ABORT command. The host may drive the

FWH[3:0] with ‘1111b’ (ABORT command) to return the

device to Ready mode. If abort occurs during a Write oper-

ation, the data may be incorrectly altered.

Response To Invalid Fields

During FWH operations, the FWH will not explicitly indicate

that it has received invalid field sequences. The response

to specific invalid fields or sequences is as follows:

Address out of range: The FWH address sequence is

7 fields long (28 bits), but only the last five address fields

(20 bits) will be decoded by SST49LF00xA.

Address A22 has the special function of directing reads and

writes to the flash core (A22=1) or to the register space

(A22=0).

The SST49LF003A features are equivalent to the

SST49LF004A with 128 KByte less memory. For the

SST49LF003A, operations beyond the 3-Mbit boundary

(below 20000H) are not valid (see Device Memory Map).

Invalid IMSIZE field: If the FWH receives an invalid size

field during a Read or Write operation, the device will reset

and no operation will be attempted. The SST49LF00xA will

not generate any kind of response in this situation. Invalid-

size fields for a Read/Write cycle are anything but 0000b.

Device Memory Hardware Write Protection

The Top Boot Lock (TBL#) and Write Protect (WP#) pins

are provided for hardware write protection of device

memory in the SST49LF00xA. The TBL# pin is used to

write protect 16 boot sectors (64 KByte) at the highest

flash memory address range for the SST49LF003A/

004A/008A and 4 boot sectors (16 KByte) for

SST49LF002A. WP# pin write protects the remaining

sectors in the flash memory.

An active low signal at the TBL# pin prevents Program and

Erase operations of the top boot sectors. When TBL# pin is

held high, write protection of the top boot sectors is then

determined by the Boot Block Locking register. The WP#

pin serves the same function for the remaining sectors of

the device memory. The TBL# and WP# pins write protec-

tion functions operate independently of one another.

Both TBL# and WP# pins must be set to their required

protection states prior to starting a Program or Erase

operation. A logic level change occurring at the TBL# or

WP# pin during a Program or Erase operation could

cause unpredictable results. TBL# and WP# pins cannot

be left unconnected.

TBL# is internally ORed with the top Boot Block Locking

ware write protected regardless of the state of the Write-

Lock bit for the Boot Block Locking register. Clearing the

Write-Protect bit in the register when TBL# is low will have

no functional effect, even though the register may indicate

that the block is no longer locked.

WP# is internally ORed with the Block Locking register.

When WP# is low, the blocks are hardware write pro-

tected regardless of the state of the Write-Lock bit for the

corresponding Block Locking registers. Clearing the

Write-Protect bit in any register when WP# is low will have

no functional effect, even though the register may indicate

that the block is no longer locked.

Reset

A VIL on INIT# or RST# pin initiates a device reset. INIT#

and RST# pins have the same function internally. It is

required to drive INIT# or RST# pins low during a system

reset to ensure proper CPU initialization.

During a Read operation, driving INIT# or RST# pins low

deselects the device and places the output drivers,

FWH[3:0], in a high-impedance state. The reset signal

must be held low for a minimal duration of time TRSTP. A

reset latency will occur if a reset procedure is performed

during a Program or Erase operation. See Table 18, Reset

Timing Parameters for more information. A device reset

during an active Program or Erase will abort the operation

and memory contents may become invalid due to data

being altered or corrupted from an incomplete Erase or

Program operation.

Advance Information

2 Mbit / 3 Mbit / 4 Mbit / 8 Mbit Firmware Hub

SST49LF002A / SST49LF003A / SST49LF004A / SST49LF008A

Write Operation Status Detection

The SST49LF00xA device provides two software means to

detect the completion of a Write (Program or Erase) cycle,

in order to optimize the system Write cycle time. The soft-

ware detection includes two status bits: Data# Polling

(DQ7) and Toggle Bit (DQ6). The End-of-Write detection

mode is incorporated into the FWH Read cycle. The actual

completion of the nonvolatile write is asynchronous with the

system; therefore, either a Data# Polling or Toggle Bit read

may be simultaneous with the completion of the Write

cycle. If this occurs, the system may possibly get an errone-

ous result, i.e., valid data may appear to conflict with either

DQ7 or DQ6. In order to prevent spurious rejection, if an

erroneous result occurs, the software routine should

include a loop to read the accessed location an additional

two (2) times. If both reads are valid, then the device has

completed the Write cycle, otherwise the rejection is valid.

Data# Polling (DQ7)

When the SST49LF00xA device is in the internal Program

operation, any attempt to read DQ7 will produce the com-

plement of the true data. Once the Program operation is

completed, DQ7 will produce true data. Note that even

though DQ7 may have valid data immediately following the

completion of an internal Write operation, the remaining

data outputs may still be invalid: valid data on the entire

data bus will appear in subsequent successive Read

cycles after an interval of 1 µs. During internal Erase opera-

tion, any attempt to read DQ7 will produce a ‘0’. Once the

internal Erase operation is completed, DQ7 will produce a

‘1’. Proper status will not be given using Data# Polling if the

address is in the invalid range.

Toggle Bit (DQ6)

During the internal Program or Erase operation, any con-

secutive attempts to read DQ6 will produce alternating

‘0’s and ‘1’s, i.e., toggling between 0 and 1. When the

internal Program or Erase operation is completed, the

toggling will stop.

Multiple Device Selection

The four ID pins, ID[3:0], allow multiple devices to be

attached to the same bus by using different ID strapping in

a system. When the SST49LF00xA is used as a boot

device, ID[3:0] must be strapped as 0000, all subsequent

devices should use a sequential up-count strapping (i.e.

0001, 0010, 0011, etc.). The SST49LF00xA will compare

the strapping values, if there is a mismatch, the device will

ignore the remainder of the cycle and go into standby

mode. For further information regarding FWH device map-

ping and paging, please refer to the Intel 82801(ICH) I/O

Controller Hub documentation. Since there is no ID support

in PP Mode, to program multiple devices a stand-alone

PROM programmer is recommended.

REGISTERS

There are three types of registers available on the

SST49LF00xA, the General Purpose Inputs Register,

Block Locking Registers, and the JEDEC ID Registers.

These registers appear at their respective address location

in the 4 GByte system memory map. Unused register loca-

tions will read as 00H. Any attempt to read or write any reg-

ister during an internal Write operation will be ignored.

General Purpose Inputs Register

The GPI_REG (General Purpose Inputs Register) passes

the state of FGPI[4:0] pins at power-up on the

SST49LF00xA. It is recommended that the FGPI[4:0] pins

are in the desired state before FWH4 is brought low for the

beginning of the bus cycle, and remain in that state until the

end of the cycle. There is no default value since this is a

pass-through register. The GPI register for the boot device

appears at FFBC0100H in the 4 GByte system memory

map, and will appear elsewhere if the device is not the boot

device. Register is not available for read when the device is

in Erase/Program operation. See Table 3 for the GPI_REG

bits and function.

TABLE 3: GENERAL PURPOSE INPUTS REGISTER

Bit Function

Pin #

32-PLCC 32-TSOP

7:5 Reserved - -

4 FGPI[4]

Reads status of general

purpose input pin

30 6

3 FGPI[3]

Reads status of general

purpose input pin

311

2 FGPI[2]

Reads status of general

purpose input pin

412

1 FGPI[1]

Reads status of general

purpose input pin

513

0 FGPI[0]

Reads status of general

purpose input pin

614

T3.2 504

Advance Information

2 Mbit / 3 Mbit / 4 Mbit / 8 Mbit Firmware Hub

SST49LF002A / SST49LF003A / SST49LF004A / SST49LF008A

Block Locking Registers

SST49LF00xA provides software controlled lock protection through a set of Block Locking registers. The Block

Locking Registers are read/write registers and it is accessible through standard addressable memory locations

specified in Table 4 and Table 5. Unused register locations will read as 00H.

TABLE 4: BLOCK LOCKING REGISTERS FOR SST49LF002A1

1. Default value at power up is 01H

Protected Memory

Address Package

Memory Map

T_BLOCK_LK 16K 3FFFFH - 3C000H FFBF8002H

T_MINUS01_LK 16K

16K

3BFFFH - 38000H

37FFFH - 34000H

33FFFH - 30000H

FFBF0002H

T_MINUS02_LK 16K

16K

2FFFFH - 2C000H

2BFFFH - 28000H

FFBE8002H

T_MINUS03_LK 16K

16K

27FFFH - 24000H

23FFFH - 20000H

FFBE0002H

T_MINUS04_LK 16K

16K

1FFFFH - 1C000H

1BFFFH - 18000H

FFBD8002H

T_MINUS05_LK 16K

16K

17FFFH - 14000H

13FFFH - 10000H

FFBD0002H

T_MINUS06_LK 16K

16K

0FFFFH - 0C000H

0BFFFH - 08000H

FFBC8002H

T_MINUS07_LK 16K

16K

07FFFH - 04000H

03FFFH - 00000H

FFBC0002H

T4.1 504

TABLE 5: BLOCK LOCKING REGISTERS FOR SST49LF003A/004A/008A1

1. Default value at power up is 01H

Block

Size

Protected Memory Address Range Memory Map

T_BLOCK_LK 64K 07FFFFH - 070000H 07FFFFH - 070000H 0FFFFFH - 0F0000H FFBF0002H

T_MINUS01_LK 64K 06FFFFH - 060000H 06FFFFH - 060000H 0EFFFFH - 0E0000H FFBE0002H

T_MINUS02_LK 64K 05FFFFH - 050000H 05FFFFH - 050000H 0DFFFFH - 0D0000H FFBD0002H

T_MINUS03_LK 64K 04FFFFH - 040000H 04FFFFH - 040000H 0CFFFFH - 0C0000H FFBC0002H

T_MINUS04_LK 64K 03FFFFH - 030000H 03FFFFH - 030000H 0BFFFFH - 0B0000H FFBB0002H

T_MINUS05_LK 64K 02FFFFH - 020000H 02FFFFH - 020000H 0AFFFFH - 0A0000H FFBA0002H

T_MINUS06_LK 64K 01FFFFH - 010000H 09FFFFH - 090000H FFB90002H

T_MINUS07_LK 64K 00FFFFH - 000000H 08FFFFH - 080000H FFB80002H

T_MINUS08_LK 64K 07FFFFH - 070000H FFB70002H

T_MINUS09_LK 64K 06FFFFH - 060000H FFB60002H

T_MINUS10_LK 64K 05FFFFH - 050000H FFB50002H

T_MINUS11_LK 64K 04FFFFH - 040000H FFB40002H

T_MINUS12_LK 64K 03FFFFH - 030000H FFB30002H

T_MINUS13_LK 64K 02FFFFH - 020000H FFB20002H

T_MINUS14_LK 64K 01FFFFH -010000H FFB10002H

T_MINUS15_LK 64K 00FFFFH - 000000H FFB00002H

T5.2 504

Advance Information

2 Mbit / 3 Mbit / 4 Mbit / 8 Mbit Firmware Hub

SST49LF002A / SST49LF003A / SST49LF004A / SST49LF008A

Write Lock

The Write-Lock bit, bit 0, controls the lock state described in

Table 6. The default Write status of all blocks after power-

up is write locked. When bit 0 of the Block Locking register

is set, Program and Erase operations for the corresponding

block are prevented. Clearing the Write-Lock bit will unpro-

tect the block. The Write-Lock bit must be cleared prior to

starting a Program or Erase operation since it is sampled at

the beginning of the operation.

The Write-Lock bit functions in conjunction with the hard-

ware Write Lock pin TBL# for the top Boot Block. When

TBL# is low, it overrides the software locking scheme. The

top Boot Block Locking register does not indicate the state

of the TBL# pin.

The Write-Lock bit functions in conjunction with the hard-

ware WP# pin for blocks 0 to 6. When WP# is low, it over-

rides the software locking scheme. The Block Locking

Lock Down

The Lock-Down bit, bit 1, controls the Block Locking regis-

ter as described in Table 6. When in the FWH interface

mode, the default Lock Down status of all blocks upon

power-up is not locked down. Once the Lock-Down bit is

set, any future attempted changes to that Block Locking

upon a device reset with RST# or INIT# or power down.

Current Lock Down status of a particular block can be

determined by reading the corresponding Lock-Down bit.

Once a block’s Lock-Down bit is set, the Write-Lock bits for

that block can no longer be modified, and the block is

locked down in its current state of write accessibility.

JEDEC ID Registers

The JEDEC ID registers for the boot device appear at

FFBC0000H and FFBC0001H in the 4 GByte system

memory map, and will appear elsewhere if the device is not

the boot device. Register is not available for read when the

device is in Erase/Program operation. Unused register

location will read as 00H. Refer to the relevant application

note for details. See Table 7 for the device ID code.

PARALLEL PROGRAMMING MODE

Device Operation

Commands are used to initiate the memory operation func-

tions of the device. The data portion of the software com-

mand sequence is latched on the rising edge of WE#.

During the software command sequence the row address

is latched on the falling edge of R/C# and the column

address is latched on the rising edge of R/C#.

Read

The Read operation of the SST49LF00xA device is con-

trolled by OE#. OE# is the output control and is used to

gate data from the output pins. Refer to the Read cycle

timing diagram, Figure 14, for further details.

Reset

A VIL on RST# pin initiates a device reset.

Byte-Program Operation

The SST49LF00xA device is programmed on a byte-by-

byte basis. Before programming, one must ensure that the

sector, in which the byte which is being programmed exists,

is fully erased. The Byte-Program operation is initiated by

executing a four-byte command load sequence for Soft-

ware Data Protection with address (BA) and data in the last

byte sequence. During the Byte-Program operation, the

row address (A10-A0) is latched on the falling edge of R/C#

and the column Address (A21-A11) is latched on the rising

edge of R/C#. The data bus is latched in the rising edge of

WE#. The Program operation, once initiated, will be com-

pleted, within 20 µs. See Figure 15 for Program operation

timing diagram, Figure 18 for timing waveforms, and Figure

26 for its flowchart. During the Program operation, the only

valid reads are Data# Polling and Toggle Bit. During the

internal Program operation, the host is free to perform addi-

tional tasks. Any commands written during the internal Pro-

gram operation will be ignored.

TABLE 6: BLOCK LOCKING REGISTER BITS

Reserved Bit [7..2] Lock-Down Bit [1] Write-Lock Bit [0] Lock Status

000000 0 0 Full Access

000000 0 1 Write Locked (Default State at Power-Up)

000000 1 0 Locked Open (Full Access Locked Down)

000000 1 1 Write Locked Down

T6.3 504

Advance Information

2 Mbit / 3 Mbit / 4 Mbit / 8 Mbit Firmware Hub

SST49LF002A / SST49LF003A / SST49LF004A / SST49LF008A

Sector-Erase Operation

The Sector-Erase operation allows the system to erase

the device on a sector-by-sector basis. The sector archi-

tecture is based on uniform sector size of 4 KByte. The

Sector-Erase operation is initiated by executing a six-byte

command load sequence for Software Data Protection

with Sector-Erase command (30H) and sector address

(SA) in the last bus cycle. The internal Erase operation

begins after the sixth WE# pulse. The End-of-Erase can

be determined using either Data# Polling or Toggle Bit

methods. See Figure 19 for Sector-Erase timing wave-

forms. Any commands written during the Sector-Erase

operation will be ignored.

Block-Erase Operation

The Block-Erase Operation allows the system to erase the

device in 64 KByte uniform block size for the

SST49LF003A/SST49LF004A/SST49LF008A and 16

KByte uniform block size for the SST49LF002A. The Block-

Erase operation is initiated by executing a six-byte com-

mand load sequence for Software Data Protection with

Block-Erase command (50H) and block address. The inter-

nal Block-Erase operation begins after the sixth WE#

pulse. The End-of-Erase can be determined using either

Data# Polling or Toggle Bit methods. See Figure 20 for tim-

ing waveforms. Any commands written during the Block-

Erase operation will be ignored.

Chip-Erase

The SST49LF00xA device provides a Chip-Erase opera-

tion only in PP Mode, which allows the user to erase the

entire memory array to the ‘1’s state. This is useful when

the entire device must be quickly erased.

The Chip-Erase operation is initiated by executing a six- byte

Software Data Protection command sequence with Chip-

Erase command (10H) with address 5555H in the last byte

sequence. The internal Erase operation begins with the ris-

ing edge of the sixth WE#. During the internal Erase opera-

tion, the only valid read is Toggle Bit or Data# Polling. See

Table 10 for the command sequence, Figure 21 for timing

diagram, and Figure 29 for the flowchart. Any commands

written during the Chip-Erase operation will be ignored.

Write Operation Status Detection

The SST49LF00xA device provides two software means

to detect the completion of a Write (Program or Erase)

cycle, in order to optimize the system Write cycle time. The

software detection includes two status bits: Data# Polling

(DQ7) and Toggle Bit (DQ6). The End-of-Write detection

mode is enabled after the rising edge of WE# which ini-

tiates the internal Program or Erase operation.

The actual completion of the nonvolatile write is asynchro-

nous with the system; therefore, either a Data# Polling or Tog-

gle Bit read may be simultaneous with the completion of the

Write cycle. If this occurs, the system may possibly get an

erroneous result, i.e., valid data may appear to conflict with

either DQ7 or DQ6. In order to prevent spurious rejection, if an

erroneous result occurs, the software routine should include a

loop to read the accessed location an additional two (2) times.

If both reads are valid, then the device has completed the

Write cycle, otherwise the rejection is valid.

Data# Polling (DQ7)

When the SST49LF00xA device is in the internal Program

operation, any attempt to read DQ7 will produce the com-

plement of the true data. Once the Program operation is

completed, DQ7 will produce true data. Note that even

though DQ7 may have valid data immediately following the

completion of an internal Write operation, the remaining

data outputs may still be invalid: valid data on the entire data

bus will appear in subsequent successive Read cycles after

an interval of 1 µs. During internal Erase operation, any

attempt to read DQ7 will produce a ‘0’. Once the internal

Erase operation is completed, DQ7 will produce a ‘1’. The

Data# Polling is valid after the rising edge of fourth WE#

pulse for Program operation. For Sector- or Chip-Erase, the

Data# Polling is valid after the rising edge of sixth WE#

pulse. See Figure 16 for Data# Polling timing diagram and

Figure 27 for a flowchart. Proper status will not be given

using Data# Polling if the address is in the invalid range.

Toggle Bit (DQ6)

During the internal Program or Erase operation, any con-

secutive attempts to read DQ6 will produce alternating

‘0’s and ‘1’s, i.e., toggling between 0 and 1. When the

internal Program or Erase operation is completed, the

toggling will stop. The device is then ready for the next

operation. The Toggle Bit is valid after the rising edge of

fourth WE# pulse for Program operation. For Sector-,

Block- or Chip-Erase, the Toggle Bit is valid after the ris-

ing edge of sixth WE# pulse. See Figure 17 for Toggle Bit

timing diagram and Figure 27 for a flowchart.

Advance Information

2 Mbit / 3 Mbit / 4 Mbit / 8 Mbit Firmware Hub

SST49LF002A / SST49LF003A / SST49LF004A / SST49LF008A

Data Protection

The SST49LF00xA device provides both hardware and

software features to protect nonvolatile data from inadvert-

ent writes.

Hardware Data Protection

Noise/Glitch Protection: A WE# pulse of less than 5 ns will

not initiate a Write cycle.

VDD Power Up/Down Detection: The Write operation is

inhibited when VDD is less than 1.5V.

Write Inhibit Mode: Forcing OE# low, WE# high will inhibit

the Write operation. This prevents inadvertent writes during

power-up or power-down.

Software Data Protection (SDP)

The SST49LF00xA provides the JEDEC approved Soft-

ware Data Protection scheme for all data alteration opera-

tion, i.e., Program and Erase. Any Program operation

requires the inclusion of a series of three-byte sequences.

The three-byte load sequence is used to initiate the Pro-

gram operation, providing optimal protection from inadvert-

ent Write operations, e.g., during the system power-up or

power-down. Any Erase operation requires the inclusion of

a six-byte load sequence. The SST49LF00xA device is

shipped with the Software Data Protection permanently

enabled. See Table 10 for the specific software command

codes. During SDP command sequence, invalid com-

mands will abort the device to Read mode, within TRC.

Electrical Specifications

The AC and DC specifications for the FWH Interface sig-

nals (FWH[3:0], CLK, FWH4, and RST#) as defined in

Section 4.2.2 of the PCI Local Bus Specification, Rev. 2.1.

Refer to Table 11 for the DC voltage and current specifica-

tions. Refer to the tables on pages 19 through 23 for the AC

timing specifications for Clock, Read/Write, and Reset

operations.

Product Identification

The product identification mode identifies the device as the

SST49LF00xA and manufacturer as SST.

Design Considerations

SST recommends a high frequency 0.1 µF ceramic capacitor

to be placed as close as possible between VDD and VSS less

than 1 cm away from the VDD pin of the device. Additionally, a

low frequency 4.7 µF electrolytic capacitor from VDD to VSS

should be placed within 1 cm of the VDD pin. If you use a

socket for programming purposes add an additional 1-10 µF

next to each socket.

The RST# pin must remain stable at VIH for the entire dura-

tion of an Erase operation. WP# must remain stable at VIH for

the entire duration of the Erase and Program operations for

non-Boot Block sectors. To write data to the top Boot Block

sectors, the TBL# pin must also remain stable at VIH for the

entire duration of the Erase and Program operations.

TABLE 7: PRODUCT IDENTIFICATION

Byte Data

JEDEC ID

Address

Location

Manufacturer’s ID 0000H BFH FFBC0000H

Device ID

SST49LF002A 0001H 57H FFBC0001H

SST49LF003A 0001H 1BH FFBC0001H

SST49LF004A 0001H 60H FFBC0001H

SST49LF008A 0001H 5AH FFBC0001H

T7.5 504

Advance Information

2 Mbit / 3 Mbit / 4 Mbit / 8 Mbit Firmware Hub

SST49LF002A / SST49LF003A / SST49LF004A / SST49LF008A

BOOT-CONFIGURATION SYSTEM MEMORY MAP

Range for

Additional FWH Devices

FFC00000H

FFF00000H

SST49LF004A

(4 Mbit)

SST49LF008A

(8 Mbit)

FFF80000H

FFFA0000H

FFFC0000H

FFFFFFFFH

SST49LF002A

(2 Mbit)

SST49LF003A

(3 Mbit)

System Memory

(Top 4 MByte)

504 ILL B1A.3

504 ILL B1.2

Y-Decoder

I/O Buffers and Data Latches

Address Buffers & Latches

X-Decoder SuperFlash

Memory

Control Logic

CLK

RST#

FGPI[4:0]

Programmer

Interface

WP#

TBL#

INIT#

ID[3:0]

FWH4

R/C#

OE#

WE#

A[10:0]

DQ[7:0]

FWH[3:0]

FWH

Interface

FUNCTIONAL BLOCK DIAGRAM

Advance Information

2 Mbit / 3 Mbit / 4 Mbit / 8 Mbit Firmware Hub

SST49LF002A / SST49LF003A / SST49LF004A / SST49LF008A

FIGURE 3: DEVICE MEMORY MAP FOR SST49LF002A

3FFFFH

3C000H

3BFFFH

38000H

37FFFH

34000H

33FFFH

30000H

2FFFFH

2C000H

2BFFFH

28000H

27FFFH

24000H

23FFFH

20000H

1FFFFH

1C000H

1BFFFH

18000H

17FFFH

14000H

13FFFH

10000H

0FFFFH

0C000H

0BFFFH

08000H

07FFFH

04000H

03FFFH

300000

02FFFH

02000H

01FFFH

01000H

00FFFH

00000H

Block 7

Block 8

Block 6

Block 5

Block 4

Block 3

Block 2

Block 1

Block 15

Block 14

Block 13

Block 12

Block 11

Block 10

Block 9

Block 0

(16 KByte)

504 ILL F52.7

WP# for

Block 0~14

TBL#

4 KByte Sector 1

4 KByte Sector 2

4 KByte Sector 3

4 KByte Sector 0

Boot Block

Advance Information

2 Mbit / 3 Mbit / 4 Mbit / 8 Mbit Firmware Hub

SST49LF002A / SST49LF003A / SST49LF004A / SST49LF008A

FIGURE 4: DEVICE MEMORY MAP FOR SST49LF003A

FIGURE 5: DEVICE MEMORY MAP FOR SST49LF004A

7FFFFH

70000H

6FFFFH

60000H

5FFFFH

50000H

4FFFFH

40000H

3FFFFH

30000H

2F000H

22000H

21000H

20000H

1FFFFH

10000H

0FFFFH

00000H

Block 7

Block 6

Block 5

Block 4

Block 3

Block 2

*Block 1

4 KByte Sector 33

4 KByte Sector 34

4 KByte Sector 32

Invalid Range

4 KByte Sector 47

*Block 0

504 ILL F56.1

(64 KByte)

Boot Block

* operations to shaded area are not valid.

WP# for

Block 2~6

TBL#

7FFFFH

70000H

6FFFFH

60000H

5FFFFH

50000H

4FFFFH

40000H

3FFFFH

30000H

2FFFFH

20000H

1FFFFH

10000H

0F000H

02000H

01000H

00000H

4 KByte Sector 1

4 KByte Sector 2

4 KByte Sector 0

Block 7

Block 6

Block 5

Block 4

Block 3

Block 2

Block 1

Block 0

504 ILL F45.5

(64 KByte)

Boot Block

WP# for

Block 0~6

TBL#

Advance Information

2 Mbit / 3 Mbit / 4 Mbit / 8 Mbit Firmware Hub

SST49LF002A / SST49LF003A / SST49LF004A / SST49LF008A

FIGURE 6: DEVICE MEMORY MAP FOR SST49LF008A

0FFFFFH

0F0000H

0EFFFFH

0E0000H

0DFFFFH

0D0000H

0CFFFFH

0C0000H

0BFFFFH

0B0000H

0AFFFFH

0A0000H

09FFFFH

090000H

08FFFFH

080000H

07FFFFH

070000H

06FFFFH

060000H

05FFFFH

050000H

04FFFFH

040000H

03FFFFH

030000H

02FFFFH

020000H

01FFFFH

010000H

00FFFFH

Block 7

Block 8

Block 6

Block 5

Block 4

Block 3

Block 2

Block 1

Block 15

Block 14

Block 13

Block 12

Block 11

Block 10

Block 9

Block 0

(64 KByte)

504 ILL F57.0

WP# for

Block 0~14

TBL#

4 KByte Sector 1

4 KByte Sector 2

4 KByte Sector 15

4 KByte Sector 0

Boot Block

002000H

001000H

000000H

Advance Information

2 Mbit / 3 Mbit / 4 Mbit / 8 Mbit Firmware Hub

SST49LF002A / SST49LF003A / SST49LF004A / SST49LF008A

FIGURE 7: PIN ASSIGNMENTS FOR 32-LEAD TSOP (8MM X 14MM)

FIGURE 8: PIN ASSIGNMENTS FOR 32-LEAD PLCC

VSS (VSS)

IC (IC)

A10 (FGPI4)

R/C# (CLK)

VDD (VDD)

RST# (RST#)

A9 (FGPI3)

A8 (FGPI2)

A7 (FGPI1)

A6 (FGPI0)

A5 (WP#)

A4 (TBL#)

OE# (INIT#)

WE# (FWH4)

VDD (VDD)

DQ7 (RES)

DQ6 (RES)

DQ5 (RES)

DQ4 (RES)

DQ3 (FWH3)

VSS (VSS)

DQ2 (FWH2)

DQ1 (FWH1)

DQ0 (FWH0)

A0 (ID0)

A1 (ID1)

A2 (ID2)

A3 (ID3)

504 ILL F01.4

Standard Pinout

Top View

Die Up

( ) Designates FWH Mode

A7(FGPI1)

A6 (FGPI0)

A5 (WP#)

A4 (TBL#)

A3 (ID3)

A2 (ID2)

A1 (ID1)

A0 (ID0)

DQ0 (FWH0)

IC (IC)

VSS (VSS)

VDD (VDD)

OE# (INIT#)

WE# (FWH4)

DQ7 (RES)

4 3 2 1 32 31 30

A8 (FGPI2)

A9 (FGPI3)

RST# (RST#)

VDD (VDD)

R/C# (CLK)

A10 (FGPI4)

32-lead PLCC

Top View

504 ILL F02.3

14 15 16 17 18 19 20

DQ1 (FWH1)

DQ2 (FWH2)

VSS (VSS)

DQ3 (FWH3)

DQ4 (RES)

DQ5 (RES)

DQ6 (RES)

( ) Designates FWH Mode

Advance Information

2 Mbit / 3 Mbit / 4 Mbit / 8 Mbit Firmware Hub

SST49LF002A / SST49LF003A / SST49LF004A / SST49LF008A

TABLE 8: PIN DESCRIPTION

Symbol Pin Name Type1

Interface

FunctionsPP FWH

A10-A0Address I X Inputs for low-order addresses during Read and Write operations.

Addresses are internally latched during a Write cycle. For the pro-

gramming interface, these addresses are latched by R/C# and share

the same pins as the high-order address inputs.

DQ7-DQ0Data I/O X To output data during Read cycles and receive input data during

Write cycles. Data is internally latched during a Write cycle. The out-

puts are in tri-state when OE# is high.

OE# Output Enable I X To gate the data output buffers

WE# Write Enable I X To control the Write operations

IC Interface

Configuration Pin

I X X This pin determines which interface is operational. When held high,

programmer mode is enabled and when held low, FWH mode is

enabled. This pin must be setup at power-up or before return from

reset and not change during device operation. This pin is internally

pulled- down with a resistor between 20-100 KΩ.

INIT# Initialize I X This is the second reset pin for in-system use. This pin is internally

combined with the RST# pin; If this pin or RST# pin is driven low,

identical operation is exhibited.

ID[3:0] Identification Inputs I X These four pins are part of the mechanism that allows multiple parts

to be attached to the same bus. The strapping of these pins is used

to identify the component.The boot device must have ID[3:0]=0000

and it is recommended that all subsequent devices should use

sequential up-count strapping. These pins are internally pulled-down

with a resistor between 20-100 KΩ.

FGPI[4:0] General Purpose Inputs I X These individual inputs can be used for additional board flexibility.

The state of these pins can be read through GPI_REG register.

These inputs should be at their desired state before the start of the

PCI clock cycle during which the read is attempted, and should

remain in place until the end of the Read cycle. Unused GPI pins

must not be floated.

TBL# Top Block Lock I X When low, prevents programming to the Boot Block sectors at top of

memory. When TBL# is high it disables hardware write protection for

the top block sectors. This pin cannot be left unconnected.

FWH[3:0] FWH I/Os I/O X I/O Communications

CLK Clock I X To provide a clock input to the control unit

FWH4 FWH Input I X Input Communications

RST# Reset I X X To reset the operation of the device

WP# Write Protect I X When low, prevents programming to all but the highest addressable

blocks. When WP# is high it disables hardware write protection for

these blocks. This pin cannot be left unconnected.

R/C# Row/Column Select I X Select For the Programming interface, this pin determines whether

the address pins are pointing to the row addresses, or to the column

addresses.

RES Reserved X These pins must be left unconnected.

VDD Power Supply PWR X X To provide power supply (3.0-3.6V)

VSS Ground PWR X X Circuit ground (OV reference) All VSS pins must be grounded.

NC No Connection I X X Unconnected pins

T8.4 504

1. I = Input, O = Output

Advance Information

2 Mbit / 3 Mbit / 4 Mbit / 8 Mbit Firmware Hub

SST49LF002A / SST49LF003A / SST49LF004A / SST49LF008A

TABLE 9: OPERATION MODES SELECTION (PP MODE)

Mode RST# OE# WE# DQ Address

Read VIH VIL VIH DOUT AIN

Program VIH VIH VIL DIN AIN

Erase VIH VIH VIL X1Sector or Block address,

XXH for Chip-Erase

Reset VIL XXHigh Z X

Write Inhibit VIH VIL XHigh Z/D

OUT X

VIH High Z/DOUT X

Product Identification VIH VIL VIH Manufacturer’s ID (BFH)

Device ID2

A18-A1=VIL, A0=VIL

A18-A1=VIL, A0=VIH

T9.5 504

1. X can be VIL or VIH, but no other value.

2. Device ID 57H for SST49LF002A, 1BH for SST49LF003A, 60H for SST49LF004A, and 5AH for SST49LF008A

TABLE 10: SOFTWARE COMMAND SEQUENCE

Command Sequence

1st1

Write Cycle

1. FWH Mode uses consecutive Write cycles to complete a command sequence; PP Mode uses consecutive bus cycles to complete a

command sequence.

2nd1

Write Cycle

3rd1

Write Cycle

4th1

Write Cycle

5th1

Write Cycle

6th1

Write Cycle

Addr2

2. Address format A14-A0 (Hex), Addresses A21-A15 can be VIL or VIH, but no other value, for the Command sequence in PP Mode.

Data Addr2Data Addr2Data Addr2Data Addr2Data Addr2Data

Byte-Program 5555H AAH 2AAAH 55H 5555H A0H BA3

3. BA = Program Byte address

Data

Sector-Erase 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H SAX4

4. SAX for Sector-Erase Address

30H

Block-Erase 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H BAX5

5. BAX for Block-Erase Address

50H

Chip-Erase6

6. Chip-Erase is supported in PP Mode only

5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H 5555H 10H

Software ID Entry7,8

7. SST Manufacturer’s ID = BFH, is read with A0=0,

With A17-A1 = 0; 49LF002A Device ID = 57H, is read with A0 = 1.

With A18-A1 = 0; 49LF003A Device ID = 1BH, is read with A0 = 1.

With A18-A1 = 0; 49LF004A Device ID = 60H, is read with A0 = 1.

With A19-A1 = 0; 49LF008A Device ID = 5AH, is read with A0 = 1.

8. The device does not remain in Software Product ID mode if powered down.

5555H AAH 2AAAH 55H 5555H 90H

Software ID Exit9

9. Both Software ID Exit operations are equivalent

XXH F0H

Software ID Exit95555H AAH 2AAAH 55H 5555H F0H

T10.5 504

Advance Information

2 Mbit / 3 Mbit / 4 Mbit / 8 Mbit Firmware Hub

SST49LF002A / SST49LF003A / SST49LF004A / SST49LF008A

Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum

Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation

of the device at these conditions or conditions greater than those defined in the operational sections of this data

sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.)

Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C

D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDD+0.5V

Transient Voltage (<20 ns) on Any Pin to Ground Potential1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.0V to VDD+2.0V

Package Power Dissipation Capability (Ta=25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W

Surface Mount Lead Soldering Temperature (3 Seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240°C

Output Short Circuit Current2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA

1. Do not violate processor or chipset limitations on the INIT# pin.

2. Outputs shorted for no more than one second. No more than one output shorted at a time. This note applies to non-PCI outputs.

OPERATING RANGE

Range Ambient Temp VDD

Commercial 0°C to +85°C 3.0-3.6V

AC CONDITIONS OF TEST1

1. FWH interface signals use PCI load test conditions

Input Rise/Fall Time . . . . . . . . . . . . . . . 3 ns

Output Load . . . . . . . . . . . . . . . . . . . . . CL = 30 pF

See Figures 24 and 25

TABLE 11: DC OPERATING CHARACTERISTICS (ALL INTERFACES)

Symbol Parameter

Limits

Test Conditions1

1. Test conditions apply to PP mode.

Min Max Units

IDD Active VDD Current Address input=VIL/VIH, at F=1/TRC Min,

VDD=VDD Max (PP Mode)

Read 12 mA OE#=VIH, WE#=VIH

Write2

2. IDD active while Erase or Program is in progress.

24 mA OE#=VIH, VDD=VDD Max (PP Mode)

ISB Standby VDD Current

(FWH Interface)

100 µA FWH4=0.9VDD, f=33 MHz VDD=VDD Max, All

other inputs ≥ 0.9 VDD or ≤ 0.1 VDD

IRY3

3. The device is in Ready Mode when no activity is on the FWH bus.

Ready Mode VDD Current

(FWH Interface)

10 mA FWH4=VIL, f=33 MHz VDD=VDD Max

All other inputs ≥ 0.9 VDD or ≤ 0.1 VDD

IIInput Current for IC,

ID [3:0] pins

200 µA VIN=GND to VDD

, VDD=VDD Max

ILI Input Leakage Current 1 µA VIN=GND to VDD

, VDD=VDD Max

ILO Output Leakage Current 1 µA VOUT=GND to VDD, VDD=VDD Max

VIHI4

4. Do not violate processor or chipset specification regarding INIT# voltage.

INIT# Input High Voltage 1.0 VDD+0.5 V VDD=VDD Max

VILI4INIT# Input Low Voltage -0.5 0.4 V VDD=VDD Min

VIL Input Low Voltage -0.5 0.3 VDD VV

DD=VDD Min

VIH Input High Voltage 0.5 VDD VDD+0.5 V VDD=VDD Max

VOL Output Low Voltage 0.1 VDD VI

OL=1500µA, VDD=VDD Min

VOH Output High Voltage 0.9 VDD VI

OH=-500 µA, VDD=VDD Min

T11.9 504

Advance Information

2 Mbit / 3 Mbit / 4 Mbit / 8 Mbit Firmware Hub

SST49LF002A / SST49LF003A / SST49LF004A / SST49LF008A

FIGURE 9: CLK WAVEFORM

TABLE 12: RECOMMENDED SYSTEM POWER-UP TIMINGS

Symbol Parameter Minimum Units

TPU-READ1Power-up to Read Operation 100 µs

TPU-WRITE1Power-up to Write Operation 100 µs

T12.2 504

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter

TABLE 13: PIN IMPEDANCE (VDD=3.3V, Ta=25 °C, f=1 Mhz, other pins open)

Parameter Description Test Condition Maximum

CI/O1

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

I/O Pin Capacitance VI/O = 0V 12 pF

CIN1Input Capacitance VIN = 0V 12 pF

LPIN2

2. Refer to PCI spec.

Pin Inductance 20 nH

T13.4 504

TABLE 14: RELIABILITY CHARACTERISTICS

Symbol Parameter Minimum Specification Units Test Method

NEND1

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

Endurance 10,000 Cycles JEDEC Standard A117

TDR1Data Retention 100 Years JEDEC Standard A103

ILTH 1Latch Up 100 + IDD mA JEDEC Standard 78

T14.3 504

TABLE 15: CLOCK TIMING PARAMETERS

Symbol Parameter Min Max Units

TCYC CLK Cycle Time 30 ns

THIGH CLK High Time 11 ns

TLOW CLK Low Time 11 ns

- CLK Slew Rate (peak-to-peak) 1 4 V/ns

- RST# or INIT# Slew Rate 50 mV/ns

T15.1 504

504 ILL F27.0

0.4 VDD p-to-p

(minimum)

Tcyc

Thigh

Tlow

0.4 VDD

0.3 VDD

0.6 VDD

0.2 VDD

0.5 VDD

Advance Information

2 Mbit / 3 Mbit / 4 Mbit / 8 Mbit Firmware Hub

SST49LF002A / SST49LF003A / SST49LF004A / SST49LF008A

AC CHARACTERISTICS (FWH MODE)

TABLE 16: READ/WRITE CYCLE TIMING PARAMETERS (FWH MODE), VDD =3.0-3.6V

Symbol Parameter Min Max Units

TCYC Clock Cycle Time 30 ns

TSU Data Set Up Time to Clock Rising 7 ns

TDH Clock Rising to Data Hold Time 0 ns

TVAL1

1. Minimum and maximum times have different loads. See PCI spec.

Clock Rising to Data Valid 2 11 ns

TBP Byte Programming Time 20 µs

TSE Sector-Erase Time 25 ms

TBE Block-Erase Time 25 ms

TSCE Chip-Erase Time 100 ms

TON Clock Rising to Active (Float to Active Delay) 2 ns

TOFF Clock Rising to Inactive (Active to Float Delay) 28 ns

T16.3 504

TABLE 17: AC INPUT/OUTPUT SPECIFICATIONS (FWH MODE)

Symbol Parameter Min Max Units Conditions

IOH(AC) Switching Current High -12 VDD

-17.1(VDD-VOUT)

Equation C1

1. See PCI spec.

0 < VOUT ≤ 0.3VDD

0.3VDD < VOUT < 0.9VDD

0.7VDD < VOUT <VDD

(Test Point) -32 VDD mA VOUT=0.7VDD

IOL(AC) Switching Current Low 16 VDD

26.7 VOUT

Equation D1mA

VDD >VOUT ≥0.6VDD

0.6VDD > VOUT > 0.1VDD

0.18VDD > VOUT > 0

(Test Point) 38 VDD mA VOUT=0.18VDD

ICL Low Clamp Current -25+(VIN+1)/0.015 mA -3 < VIN ≤ -1

ICH High Clamp Current 25+(VIN-VDD-1)/0.015 mA VDD+4 > VIN ≤ VDD+1

slewr2

2. PCI specification output load is used.

Output Rise Slew Rate 1 4 V/ns 0.2VDD-0.6VDD load

slewf2Output Fall Slew Rate 1 4 V/ns 0.6VDD-0.2VDD load

T17.3 504

TABLE 18: RESET TIMING PARAMETERS, VDD =3.0-3.6V (FWH MODE)

Symbol Parameter Min Max Units

TPRST VDD stable to Reset Low 1 ms

TKRST Clock Stable to Reset Low 100 µs

TRSTP RST# Pulse Width 100 ns

TRSTF RST# Low to Output Float 48 ns

TRST1

1. There will be a latency of TRSTE if a reset procedure is performed during a Program or Erase operation.

RST# High to FWH4 Low 1 µs

TRSTE RST# Low to reset during Sector-/Block-Erase or Program 10 µs

T18.5 504

Advance Information

2 Mbit / 3 Mbit / 4 Mbit / 8 Mbit Firmware Hub

SST49LF002A / SST49LF003A / SST49LF004A / SST49LF008A

FIGURE 10: RESET TIMING DIAGRAM

FIGURE 11: OUTPUT TIMING PARAMETERS

CLK

VDD

RST#/INIT#

FWH4

FWH[3:0]

504 ILL F51.1

TPRST

TKRST

TRSTP

TRSTF

TRSTE Sector-/Block-Erase

or Program operation

aborted

TRST

TVAL

VTEST

VTL

VTH

TOFF

TON

504 ILL F49.1

CLK

FWH [3:0]

(Valid Output Data)

FWH [3:0]

(Float Output Data)

Advance Information

2 Mbit / 3 Mbit / 4 Mbit / 8 Mbit Firmware Hub

SST49LF002A / SST49LF003A / SST49LF004A / SST49LF008A

FIGURE 12: INPUT TIMING PARAMETERS

TABLE 19: INTERFACE MEASUREMENT CONDITION PARAMETERS

Symbol Value Units

VTH1

1. The input test environment is done with 0.1 VDD of overdrive over VIH and VIL. Timing parameters must be met with no more

overdrive than this. VMAX specified the maximum peak-to-peak waveform allowed for measuring input timing. Production testing

may use different voltage values, but must correlate results back to these parameters.

0.6 VDD V

VTL10.2 VDD V

VTEST 0.4 VDD V

VMAX10.4 VDD V

Input Signal Edge Rate 1 V/ns

T19.3 504

TSU

TDH

Inputs

Valid

504 ILL F50.1

CLK

FWH [3:0]

(Valid Input Data)

VTEST

VTL

VMAX

VTH

Advance Information

2 Mbit / 3 Mbit / 4 Mbit / 8 Mbit Firmware Hub

SST49LF002A / SST49LF003A / SST49LF004A / SST49LF008A

AC CHARACTERISTICS (PP MODE)

TABLE 20: READ CYCLE TIMING PARAMETERS VDD =3.0-3.6V (PP MODE)

Symbol Parameter Min Max Units

TRC Read Cycle Time 270 ns

TRST RST# High to Row Address Setup 1 µs

TAS R/C# Address Set-up Time 45 ns

TAH R/C# Address Hold Time 45 ns

TAA Address Access Time 120 ns

TOE Output Enable Access Time 60 ns

TOLZ OE# Low to Active Output 0 ns

TOHZ OE# High to High-Z Output 35 ns

TOH Output Hold from Address Change 0 ns

T20.2 504

TABLE 21: PROGRAM/ERASE CYCLE TIMING PARAMETERS VDD =3.0-3.6V (PP MODE)

Symbol Parameter Min Max Units

TRST RST# High to Row Address Setup 1 µs

TAS R/C# Address Setup Time 50 ns

TAH R/C# Address Hold Time 50 ns

TCWH R/C# to Write Enable High Time 50 ns

TOES OE# High Setup Time 20 ns

TOEH OE# High Hold Time 20 ns

TOEP OE# to Data# Polling Delay 40 ns

TOET OE# to Toggle Bit Delay 40 ns

TWP WE# Pulse Width 100 ns

TWPH WE# Pulse Width High 100 ns

TDS Data Setup Time 50 ns

TDH Data Hold Time 5 ns

TIDA Software ID Access and Exit Time 150 ns

TBP Byte Programming Time 20 µs

TSE Sector-Erase Time 25 ms

TBE Block-Erase Time 25 ms

TSCE Chip-Erase Time 100 ms

T21.2 504

TABLE 22: RESET TIMING PARAMETERS, VDD =3.0-3.6V (PP MODE)

Symbol Parameter Min Max Units

TPRST VDD stable to Reset Low 1 ms

TRSTP RST# Pulse Width 100 ns

TRSTF RST# Low to Output Float 48 ns

TRST1

1. There will be a reset latency of TRSTE or TRSTC if a reset procedure is performed during a Program or Erase operation.

RST# High to Row Address Setup 1 µs

TRSTE RST# Low to reset during Sector-/Block-Erase or Program 10 µs

TRSTC RST# Low to reset during Chip-Erase 50 µs

T22.1 504

Advance Information

2 Mbit / 3 Mbit / 4 Mbit / 8 Mbit Firmware Hub

SST49LF002A / SST49LF003A / SST49LF004A / SST49LF008A

FIGURE 13: RESET TIMING DIAGRAM

FIGURE 14: READ CYCLE TIMING DIAGRAM (PP MODE)

VDD

RST#

Addresses

R/C#

DQ7-0

504 ILL F58.0

TPRST

TRSTP

TRSTF

TRSTE

Row Address

Sector-/Block-Erase

or Program operation

aborted

TRST

TRSTC Chip-Erase

aborted

504 ILL F28.2

Column Address

Data Valid High-Z

Row AddressColumn AddressRow Address

RST#

Addresses

R/C#

VIH

High-Z

TRST TRC

TAS TAH TAH

TAA

TOE

TOLZ

TOHZ

TOH

TAS

WE#

OE#

DQ7-0

TRSTP

Advance Information

2 Mbit / 3 Mbit / 4 Mbit / 8 Mbit Firmware Hub

SST49LF002A / SST49LF003A / SST49LF004A / SST49LF008A

FIGURE 15: WRITE CYCLE TIMING DIAGRAM (PP MODE)

FIGURE 16: DATA# POLLING TIMING DIAGRAM (PP MODE)

504 ILL F29.2

Column AddressRow Address

Data Valid

RST#

Addresses

R/C#

TRST

TAS TAH

TCWH

TWP TWPH

TOEH

TDH

TDS

TAH

TAS

WE#

OE#

DQ7-0

TOES

TRSTP

504 ILL F54.2

Addresses

R/C#

TOEP

Row Column

WE#

OE#

DQ7D#D D# D

Advance Information

2 Mbit / 3 Mbit / 4 Mbit / 8 Mbit Firmware Hub

SST49LF002A / SST49LF003A / SST49LF004A / SST49LF008A

FIGURE 17: TOGGLE BIT TIMING DIAGRAM (PP MODE)

FIGURE 18: BYTE-PROGRAM TIMING DIAGRAM (PP MODE)

504 ILL F55.0

Addresses

R/C#

TOET

Row Column

WE#

OE#

DQ6D D

504 ILL F53.0

TWP

TWPH

TBP

Four-Byte Code for Byte-Program

5555 2AAA 5555 BA

SB0

BA = Byte-Program Address

SB1 SB2 SB3 Internal Program Starts

WE#

Addresses

R/C#

OE#

Data55AA A0

DQ7-0

Advance Information

2 Mbit / 3 Mbit / 4 Mbit / 8 Mbit Firmware Hub

SST49LF002A / SST49LF003A / SST49LF004A / SST49LF008A

FIGURE 19: SECTOR-ERASE TIMING DIAGRAM (PP MODE)

FIGURE 20: BLOCK-ERASE TIMING DIAGRAM (PP MODE)

504 ILL F32.1

TWP

TWPH

TSE

Six-Byte code for

Sector-Erase Operation

5555 2AAA 5555 5555 2AAA SAx

SB0

SAx = Sector Address

SB1 SB2 SB3 SB4 SB5 Internal Erasure Starts

WE#

Addresses

R/C#

OE#

55AA55AA 80 30

DQ7-0

504 ILL F48.1

TWP

TWPH

TBE

Six-Byte code for

Block-Erase Operation

5555 2AAA 5555 5555 2AAA BAx

SB0

BAx = Block Address

SB1 SB2 SB3 SB4 SB5 Internal Erasure Starts

WE#

Addresses

R/C#

OE#

55AA55AA 80 50

DQ7-0

Advance Information

2 Mbit / 3 Mbit / 4 Mbit / 8 Mbit Firmware Hub

SST49LF002A / SST49LF003A / SST49LF004A / SST49LF008A

FIGURE 21: CHIP-ERASE TIMING DIAGRAM (PP MODE)

FIGURE 22: SOFTWARE ID ENTRY AND READ (PP MODE)

504 ILL F33.1

TWP

TWPH

TSCE

Six-Byte code for Chip-Erase Operation

5555 2AAA 5555 5555 2AAA 5555

SB0 SB1 SB2 SB3 SB4 SB5 Internal Erasure Starts

WE#

Addresses

R/C#

OE#

55AA55AA 80 10

DQ7-0

504 ILL F34.5

Addresses

TIDA

DQ7-0

WE#

SW0

Device ID = 57H for SST49LF002A, 1BH for SST49LF003A,

60H for SST49LF004A, 5AH for SST49LF008A

SW1 SW2

5555 2AAA 5555 0000 0001

OE#

R/C#

Three-byte sequence for

Software ID Entry

TWP

TWPH

TAA

Device ID

55AA 90

Advance Information

2 Mbit / 3 Mbit / 4 Mbit / 8 Mbit Firmware Hub

SST49LF002A / SST49LF003A / SST49LF004A / SST49LF008A

FIGURE 23: SOFTWARE ID EXIT AND RESET (PP MODE)

FIGURE 24: AC INPUT/OUTPUT REFERENCE WAVEFORMS (PP MODE)

FIGURE 25: A TEST LOAD EXAMPLE (PP MODE)

504 ILL F35.2

Addresses

DQ7-0

TIDA

TWP

TWPH

WE#

SW0 SW1 SW2

5555 2AAA 5555

Three-Byte Sequence for

Software ID Exit and Reset

OE#

R/C#

AA 55 F0

504 ILL F06.1

REFERENCE POINTS OUTPUTINPUT VIT

VIHT

VILT

VOT

AC test inputs are driven at VIHT (0.9 VDD) for a logic “1” and VILT (0.1 VDD) for a logic “0”. Measurement reference points

for inputs and outputs are VIT (0.5 VDD) and VOT (0.5 VDD). Input rise and fall times (10% ↔ 90%) are <5 ns.

Note: VIT - VINPUT Te st

VOT - VOUTPUT Te s t

VIHT - VINPUT HIGH Test

VILT - VINPUT LOW Test

504 ILL F07.0

TO TESTER

TO DUT

Advance Information

2 Mbit / 3 Mbit / 4 Mbit / 8 Mbit Firmware Hub

SST49LF002A / SST49LF003A / SST49LF004A / SST49LF008A

FIGURE 26: BYTE-PROGRAM ALGORITHM

504 ILL F36.1

Start

Write data: AAH

Address: 5555H

Write data: 55H

Address: 2AAAH

Write data: A0H

Address: 5555H

Load Byte

Address/Byte

Data

Wait for end of

Program (TBP,

Data# Polling

bit, or Toggle bit

operation)

Program

Completed

Advance Information

2 Mbit / 3 Mbit / 4 Mbit / 8 Mbit Firmware Hub

SST49LF002A / SST49LF003A / SST49LF004A / SST49LF008A

FIGURE 27: WAIT OPTIONS

504 ILL F37.0

Wait TBP,

TSCE, TBE

or TSE

Byte-

Program/Erase

Initiated

Internal Timer Toggle Bit

Ye s

Program/Erase

Completed

Does DQ6

match?

Read same

byte

Data# Polling

Program/Erase

Completed

Program/Erase

Completed

Read byte

Is DQ7 =

true data?

Read DQ7

Byte-

Program/Erase

Initiated

Byte-

Program/Erase

Initiated

Advance Information

2 Mbit / 3 Mbit / 4 Mbit / 8 Mbit Firmware Hub

SST49LF002A / SST49LF003A / SST49LF004A / SST49LF008A

FIGURE 28: SOFTWARE PRODUCT COMMAND FLOWCHARTS

504 ILL F38.1

Write data: AAH

Address: 5555H

Software Product ID Entry

Command Sequence

Write data: 55H

Address: 2AAAH

Write data: 90H

Address: 5555H

Wait TIDA

Read Software ID

Write data: AAH

Address: 5555H

Software Product ID Exit &

Reset Command Sequence

Write data: 55H

Address: 2AAAH

Write data: F0H

Address: 5555H

Write data: F0H

Address: XXH

Return to normal

operation

Wait TIDA

Return to normal

operation

Advance Information

2 Mbit / 3 Mbit / 4 Mbit / 8 Mbit Firmware Hub

SST49LF002A / SST49LF003A / SST49LF004A / SST49LF008A

FIGURE 29: ERASE COMMAND SEQUENCE

504 ILL F39.1

Write data: AAH

Address: 5555H

Chip-Erase

Command Sequence

Write data: 55H

Address: 2AAAH

Write data: 80H

Address: 5555H

Write data: 55H

Address: 2AAAH

Write data: 10H

Address: 5555H

Write data: AAH

Address: 5555H

Wait Options

Chip erased

to FFH

Write data: AAH

Address: 5555H

Sector-Erase

Command Sequence

Write data: 55H

Address: 2AAAH

Write data: 80H

Address: 5555H

Write data: 55H

Address: 2AAAH

Write data: 30H

Address: SAX

Write data: AAH

Address: 5555H

Wait Options

Sector erased

to FFH

Write data: AAH

Address: 5555H

Block-Erase

Command Sequence

Write data: 55H

Address: 2AAAH

Write data: 80H

Address: 5555H

Write data: 55H

Address: 2AAAH

Write data: 50H

Address: BAX

Write data: AAH

Address: 5555H

Wait Options

Block erased

to FFH

Advance Information

2 Mbit / 3 Mbit / 4 Mbit / 8 Mbit Firmware Hub

SST49LF002A / SST49LF003A / SST49LF004A / SST49LF008A

PRODUCT ORDERING INFORMATION

Valid combinations for SST49LF002A

SST49LF002A-33-4C-WH SST49LF002A-33-4C-NH

Valid combinations for SST49LF003A

SST49LF003A-33-4C-WH SST49LF003A-33-4C-NH

Valid combinations for SST49LF004A

SST49LF004A-33-4C-WH SST49LF004A-33-4C-NH

Valid combinations for SST49LF008A

SST49LF008A-33-4C-WH SST49LF008A-33-4C-NH

Note: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales

representative to confirm availability of valid combinations and to determine availability of new combinations.

Device Speed Suffix1 Suffix2

SST49LF00xA-XXX -XX-XX

Package Modifier

H = 32 leads

Package Type

N = PLCC

W = TSOP (type 1, die up, 8mm x 14mm)

Operating Temperature

C = Commercial = 0°C to +85°C

Minimum Endurance

4 = 10,000 cycles

Serial Access Clock Frequency

33 = 33 MHz

Version

Device Density

008 = 8 Mbit

004 = 4 Mbit

003 = 3 Mbit

002 = 2 Mbit

Voltage Range

L = 3.0-3.6V

Advance Information

2 Mbit / 3 Mbit / 4 Mbit / 8 Mbit Firmware Hub

SST49LF002A / SST49LF003A / SST49LF004A / SST49LF008A

PACKAGING DIAGRAMS

32-LEAD PLASTIC LEAD CHIP CARRIER (PLCC)

SST PACKAGE CODE: NH

.040

.030

.021

.013

.530

.490

.095

.075

.140

.125

.032

.026

.032

.026

.029

.023

.453

.447

.553

.547

.595

.585

.495

.485 .112

.106

.042

.048

.042

.015 Min.

TOP VIEW SIDE VIEW BOTTOM VIEW

1232

.400

BSC

32-plcc-NH-3

Note: 1. Complies with JEDEC publication 95 MS-016 AE dimensions, although some dimensions may be more stringent.

2. All linear dimensions are in inches (max/min).

3. Dimensions do not include mold flash. Maximum allowable mold flash is .008 inches.

4. Coplanarity: 4 mils.

.050

BSC

.050

BSC

Optional

Pin #1

Identifier .020 R.

MAX. R.

x 30˚

Advance Information

2 Mbit / 3 Mbit / 4 Mbit / 8 Mbit Firmware Hub

SST49LF002A / SST49LF003A / SST49LF004A / SST49LF008A

32-LEAD THIN SMALL OUTLINE PACKAGE (TSOP) 8MM X 14MM

SST PACKAGE CODE: WH

32-tsop-WH-7

Note: 1. Complies with JEDEC publication 95 MO-142 BA dimensions,

although some dimensions may be more stringent.

2. All linear dimensions are in millimeters (max/min).

3. Coplanarity: 0.1 mm

4. Maximum allowable mold flash is 0.15 mm at the package ends, and 0.25 mm between leads.

1.20

max.

1mm

Pin # 1 Identifier

12.50

12.30

14.20

13.80

0.70

0.50

8.10

7.90 0.27

0.17

0.50

BSC

1.05

0.95

0.15

0.05

0.70

0.50

0˚- 5˚

DETAIL

Silicon Storage Technology, Inc. • 1171 Sonora Court • Sunnyvale, CA 94086 • Telephone 408-735-9110 • Fax 408-735-9036

www.SuperFlash.com or www.sst.com

www.s-manuals.com

SST49LF002A, SST49LF003A, SST49LF004A, SST49LF008A Datasheet. Www.s Manuals.com. 20020521 Sst

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