STM32F446xx Advanced ARM® Based 32 Bit MCUs Stm32f446re Ref Manual
User Manual:
Open the PDF directly: View PDF
Page Count: 1327 [warning: Documents this large are best viewed by clicking the View PDF Link!]
- 1 Documentation conventions
- 2 Memory and bus architecture
- 3 Embedded Flash memory interface
- 3.1 Introduction
- 3.2 Main features
- 3.3 Embedded Flash memory
- 3.4 Read interface
- 3.5 Erase and program operations
- 3.6 Option bytes
- 3.7 One-time programmable bytes
- 3.8 Flash interface registers
- 4 CRC calculation unit
- 5 Power controller (PWR)
- 5.1 Power supplies
- 5.2 Power supply supervisor
- 5.3 Low-power modes
- 5.4 Power control registers
- 5.5 PWR register map
- 6 Reset and clock control (RCC)
- 6.1 Reset
- 6.2 Clocks
- 6.3 RCC registers
- 6.3.1 RCC clock control register (RCC_CR)
- 6.3.2 RCC PLL configuration register (RCC_PLLCFGR)
- 6.3.3 RCC clock configuration register (RCC_CFGR)
- 6.3.4 RCC clock interrupt register (RCC_CIR)
- 6.3.5 RCC AHB1 peripheral reset register (RCC_AHB1RSTR)
- 6.3.6 RCC AHB2 peripheral reset register (RCC_AHB2RSTR)
- 6.3.7 RCC AHB3 peripheral reset register (RCC_AHB3RSTR)
- 6.3.8 RCC APB1 peripheral reset register (RCC_APB1RSTR)
- 6.3.9 RCC APB2 peripheral reset register (RCC_APB2RSTR)
- 6.3.10 RCC AHB1 peripheral clock enable register (RCC_AHB1ENR)
- 6.3.11 RCC AHB2 peripheral clock enable register (RCC_AHB2ENR)
- 6.3.12 RCC AHB3 peripheral clock enable register (RCC_AHB3ENR)
- 6.3.13 RCC APB1 peripheral clock enable register (RCC_APB1ENR)
- 6.3.14 RCC APB2 peripheral clock enable register (RCC_APB2ENR)
- 6.3.15 RCC AHB1 peripheral clock enable in low power mode register (RCC_AHB1LPENR)
- 6.3.16 RCC AHB2 peripheral clock enable in low power mode register (RCC_AHB2LPENR)
- 6.3.17 RCC AHB3 peripheral clock enable in low power mode register (RCC_AHB3LPENR)
- 6.3.18 RCC APB1 peripheral clock enable in low power mode register (RCC_APB1LPENR)
- 6.3.19 RCC APB2 peripheral clock enabled in low power mode register (RCC_APB2LPENR)
- 6.3.20 RCC Backup domain control register (RCC_BDCR)
- 6.3.21 RCC clock control & status register (RCC_CSR)
- 6.3.22 RCC spread spectrum clock generation register (RCC_SSCGR)
- 6.3.23 RCC PLLI2S configuration register (RCC_PLLI2SCFGR)
- 6.3.24 RCC PLL configuration register (RCC_PLLSAICFGR)
- 6.3.25 RCC Dedicated Clock Configuration Register (RCC_DCKCFGR)
- 6.3.26 RCC clocks gated enable register (CKGATENR)
- 6.3.27 RCC dedicated clocks configuration register 2 (DCKCFGR2)
- 6.3.28 RCC register map
- 7 General-purpose I/Os (GPIO)
- 7.1 GPIO introduction
- 7.2 GPIO main features
- 7.3 GPIO functional description
- Figure 17. Basic structure of a 5 V tolerant I/O port bit
- Table 22. Port bit configuration table
- 7.3.1 General-purpose I/O (GPIO)
- 7.3.2 I/O pin multiplexer and mapping
- 7.3.3 I/O port control registers
- 7.3.4 I/O port data registers
- 7.3.5 I/O data bitwise handling
- 7.3.6 GPIO locking mechanism
- 7.3.7 I/O alternate function input/output
- 7.3.8 External interrupt/wakeup lines
- 7.3.9 Input configuration
- 7.3.10 Output configuration
- 7.3.11 Alternate function configuration
- 7.3.12 Analog configuration
- 7.3.13 Using the OSC32_IN/OSC32_OUT pins as GPIO PC14/PC15 port pins
- 7.3.14 Using the OSC_IN/OSC_OUT pins as GPIO PH0/PH1 port pins
- 7.3.15 Selection of RTC additional_AF1 and RTC_AF2 alternate functions
- 7.4 GPIO registers
- 7.4.1 GPIO port mode register (GPIOx_MODER) (x = A..H)
- 7.4.2 GPIO port output type register (GPIOx_OTYPER) (x = A..H)
- 7.4.3 GPIO port output speed register (GPIOx_OSPEEDR) (x = A..H)
- 7.4.4 GPIO port pull-up/pull-down register (GPIOx_PUPDR) (x = A..H)
- 7.4.5 GPIO port input data register (GPIOx_IDR) (x = A..H)
- 7.4.6 GPIO port output data register (GPIOx_ODR) (x = A..H)
- 7.4.7 GPIO port bit set/reset register (GPIOx_BSRR) (x = A..H)
- 7.4.8 GPIO port configuration lock register (GPIOx_LCKR) (x = A..H)
- 7.4.9 GPIO alternate function low register (GPIOx_AFRL) (x = A..H)
- 7.4.10 GPIO alternate function high register (GPIOx_AFRH) (x = A..H)
- 7.4.11 GPIO register map
- 8 System configuration controller (SYSCFG)
- 8.1 I/O compensation cell
- 8.2 SYSCFG registers
- 8.2.1 SYSCFG memory remap register (SYSCFG_MEMRMP)
- 8.2.2 SYSCFG peripheral mode configuration register (SYSCFG_PMC)
- 8.2.3 SYSCFG external interrupt configuration register 1 (SYSCFG_EXTICR1)
- 8.2.4 SYSCFG external interrupt configuration register 2 (SYSCFG_EXTICR2)
- 8.2.5 SYSCFG external interrupt configuration register 3 (SYSCFG_EXTICR3)
- 8.2.6 SYSCFG external interrupt configuration register 4 (SYSCFG_EXTICR4)
- 8.2.7 Compensation cell control register (SYSCFG_CMPCR)
- 8.2.8 SYSCFG configuration register (SYSCFG_CFGR)
- 8.2.9 SYSCFG register maps
- 9 Direct memory access controller (DMA)
- 9.1 DMA introduction
- 9.2 DMA main features
- 9.3 DMA functional description
- 9.3.1 DMA block diagram
- 9.3.2 DMA overview
- 9.3.3 DMA transactions
- 9.3.4 Channel selection
- 9.3.5 Arbiter
- 9.3.6 DMA streams
- 9.3.7 Source, destination and transfer modes
- 9.3.8 Pointer incrementation
- 9.3.9 Circular mode
- 9.3.10 Double buffer mode
- 9.3.11 Programmable data width, packing/unpacking, endianness
- 9.3.12 Single and burst transfers
- 9.3.13 FIFO
- 9.3.14 DMA transfer completion
- 9.3.15 DMA transfer suspension
- 9.3.16 Flow controller
- 9.3.17 Summary of the possible DMA configurations
- 9.3.18 Stream configuration procedure
- 9.3.19 Error management
- 9.4 DMA interrupts
- 9.5 DMA registers
- 9.5.1 DMA low interrupt status register (DMA_LISR)
- 9.5.2 DMA high interrupt status register (DMA_HISR)
- 9.5.3 DMA low interrupt flag clear register (DMA_LIFCR)
- 9.5.4 DMA high interrupt flag clear register (DMA_HIFCR)
- 9.5.5 DMA stream x configuration register (DMA_SxCR) (x = 0..7)
- 9.5.6 DMA stream x number of data register (DMA_SxNDTR) (x = 0..7)
- 9.5.7 DMA stream x peripheral address register (DMA_SxPAR) (x = 0..7)
- 9.5.8 DMA stream x memory 0 address register (DMA_SxM0AR) (x = 0..7)
- 9.5.9 DMA stream x memory 1 address register (DMA_SxM1AR) (x = 0..7)
- 9.5.10 DMA stream x FIFO control register (DMA_SxFCR) (x = 0..7)
- 9.5.11 DMA register map
- 10 Interrupts and events
- 10.1 Nested vectored interrupt controller (NVIC)
- 10.2 External interrupt/event controller (EXTI)
- 10.3 EXTI registers
- 11 Flexible memory controller (FMC)
- 11.1 FMC main features
- 11.2 Block diagram
- 11.3 AHB interface
- 11.4 External device address mapping
- 11.5 NOR Flash/PSRAM controller
- Table 48. Programmable NOR/PSRAM access parameters
- 11.5.1 External memory interface signals
- 11.5.2 Supported memories and transactions
- 11.5.3 General timing rules
- 11.5.4 NOR Flash/PSRAM controller asynchronous transactions
- Figure 33. Mode1 read access waveforms
- Figure 34. Mode1 write access waveforms
- Table 54. FMC_BCRx bit fields
- Table 55. FMC_BTRx bit fields
- Figure 35. ModeA read access waveforms
- Figure 36. ModeA write access waveforms
- Table 56. FMC_BCRx bit fields
- Table 57. FMC_BTRx bit fields
- Table 58. FMC_BWTRx bit fields
- Figure 37. Mode2 and mode B read access waveforms
- Figure 38. Mode2 write access waveforms
- Figure 39. ModeB write access waveforms
- Table 59. FMC_BCRx bit fields
- Table 60. FMC_BTRx bit fields
- Table 61. FMC_BWTRx bit fields
- Figure 40. ModeC read access waveforms
- Figure 41. ModeC write access waveforms
- Table 62. FMC_BCRx bit fields
- Table 63. FMC_BTRx bit fields
- Table 64. FMC_BWTRx bit fields
- Figure 42. ModeD read access waveforms
- Figure 43. ModeD write access waveforms
- Table 65. FMC_BCRx bit fields
- Table 66. FMC_BTRx bit fields
- Table 67. FMC_BWTRx bit fields
- Figure 44. Muxed read access waveforms
- Figure 45. Muxed write access waveforms
- Table 68. FMC_BCRx bit fields
- Table 69. FMC_BTRx bit fields
- Figure 46. Asynchronous wait during a read access waveforms
- Figure 47. Asynchronous wait during a write access waveforms
- 11.5.5 Synchronous transactions
- 11.5.6 NOR/PSRAM controller registers
- 11.6 NAND Flash controller
- Table 74. Programmable NAND Flash access parameters
- 11.6.1 External memory interface signals
- 11.6.2 NAND Flash supported memories and transactions
- 11.6.3 Timing diagrams for NAND Flash memory
- 11.6.4 NAND Flash operations
- 11.6.5 NAND Flash prewait functionality
- 11.6.6 Computation of the error correction code (ECC) in NAND Flash memory
- 11.6.7 NAND Flashcontroller registers
- 11.7 SDRAM controller
- 11.8 FMC register map
- 12 Quad-SPI interface (QUADSPI)
- 12.1 Introduction
- 12.2 QUADSPI main features
- 12.3 QUADSPI functional description
- 12.3.1 QUADSPI block diagram
- 12.3.2 QUADSPI pins
- 12.3.3 QUADSPI Command sequence
- 12.3.4 QUADSPI signal interface protocol modes
- 12.3.5 QUADSPI indirect mode
- 12.3.6 QUADSPI status flag polling mode
- 12.3.7 QUADSPI memory-mapped mode
- 12.3.8 QUADSPI Flash memory configuration
- 12.3.9 QUADSPI delayed data sampling
- 12.3.10 QUADSPI configuration
- 12.3.11 QUADSPI usage
- 12.3.12 Sending the instruction only once
- 12.3.13 QUADSPI error management
- 12.3.14 QUADSPI busy bit and abort functionality
- 12.3.15 nCS behavior
- 12.4 QUADSPI interrupts
- 12.5 QUADSPI registers
- 12.5.1 QUADSPI control register (QUADSPI_CR)
- 12.5.2 QUADSPI device configuration register (QUADSPI_DCR)
- 12.5.3 QUADSPI status register (QUADSPI_SR)
- 12.5.4 QUADSPI flag clear register (QUADSPI_FCR)
- 12.5.5 QUADSPI data length register (QUADSPI_DLR)
- 12.5.6 QUADSPI communication configuration register (QUADSPI_CCR)
- 12.5.7 QUADSPI address register (QUADSPI_AR)
- 12.5.8 QUADSPI alternate bytes registers (QUADSPI_ABR)
- 12.5.9 QUADSPI data register (QUADSPI_DR)
- 12.5.10 QUADSPI polling status mask register (QUADSPI _PSMKR)
- 12.5.11 QUADSPI polling status match register (QUADSPI _PSMAR)
- 12.5.12 QUADSPI polling interval register (QUADSPI _PIR)
- 12.5.13 QUADSPI low-power timeout register (QUADSPI_LPTR)
- 12.5.14 QUADSPI register map
- 13 Analog-to-digital converter (ADC)
- 13.1 ADC introduction
- 13.2 ADC main features
- 13.3 ADC functional description
- Figure 68. Single ADC block diagram
- Table 84. ADC pins
- 13.3.1 ADC on-off control
- 13.3.2 ADC1/2 and ADC3 connectivity
- 13.3.3 ADC clock
- 13.3.4 Channel selection
- 13.3.5 Single conversion mode
- 13.3.6 Continuous conversion mode
- 13.3.7 Timing diagram
- 13.3.8 Analog watchdog
- 13.3.9 Scan mode
- 13.3.10 Injected channel management
- 13.3.11 Discontinuous mode
- 13.4 Data alignment
- 13.5 Channel-wise programmable sampling time
- 13.6 Conversion on external trigger and trigger polarity
- 13.7 Fast conversion mode
- 13.8 Data management
- 13.9 Multi ADC mode
- 13.10 Temperature sensor
- 13.11 Battery charge monitoring
- 13.12 ADC interrupts
- 13.13 ADC registers
- 13.13.1 ADC status register (ADC_SR)
- 13.13.2 ADC control register 1 (ADC_CR1)
- 13.13.3 ADC control register 2 (ADC_CR2)
- 13.13.4 ADC sample time register 1 (ADC_SMPR1)
- 13.13.5 ADC sample time register 2 (ADC_SMPR2)
- 13.13.6 ADC injected channel data offset register x (ADC_JOFRx) (x=1..4)
- 13.13.7 ADC watchdog higher threshold register (ADC_HTR)
- 13.13.8 ADC watchdog lower threshold register (ADC_LTR)
- 13.13.9 ADC regular sequence register 1 (ADC_SQR1)
- 13.13.10 ADC regular sequence register 2 (ADC_SQR2)
- 13.13.11 ADC regular sequence register 3 (ADC_SQR3)
- 13.13.12 ADC injected sequence register (ADC_JSQR)
- 13.13.13 ADC injected data register x (ADC_JDRx) (x= 1..4)
- 13.13.14 ADC regular data register (ADC_DR)
- 13.13.15 ADC Common status register (ADC_CSR)
- 13.13.16 ADC common control register (ADC_CCR)
- 13.13.17 ADC common regular data register for dual and triple modes (ADC_CDR)
- 13.13.18 ADC register map
- 14 Digital-to-analog converter (DAC)
- 14.1 DAC introduction
- 14.2 DAC main features
- 14.3 DAC functional description
- 14.4 Dual DAC channel conversion
- 14.4.1 Independent trigger without wave generation
- 14.4.2 Independent trigger with single LFSR generation
- 14.4.3 Independent trigger with different LFSR generation
- 14.4.4 Independent trigger with single triangle generation
- 14.4.5 Independent trigger with different triangle generation
- 14.4.6 Simultaneous software start
- 14.4.7 Simultaneous trigger without wave generation
- 14.4.8 Simultaneous trigger with single LFSR generation
- 14.4.9 Simultaneous trigger with different LFSR generation
- 14.4.10 Simultaneous trigger with single triangle generation
- 14.4.11 Simultaneous trigger with different triangle generation
- 14.5 DAC registers
- 14.5.1 DAC control register (DAC_CR)
- 14.5.2 DAC software trigger register (DAC_SWTRIGR)
- 14.5.3 DAC channel1 12-bit right-aligned data holding register (DAC_DHR12R1)
- 14.5.4 DAC channel1 12-bit left aligned data holding register (DAC_DHR12L1)
- 14.5.5 DAC channel1 8-bit right aligned data holding register (DAC_DHR8R1)
- 14.5.6 DAC channel2 12-bit right aligned data holding register (DAC_DHR12R2)
- 14.5.7 DAC channel2 12-bit left aligned data holding register (DAC_DHR12L2)
- 14.5.8 DAC channel2 8-bit right-aligned data holding register (DAC_DHR8R2)
- 14.5.9 Dual DAC 12-bit right-aligned data holding register (DAC_DHR12RD)
- 14.5.10 DUAL DAC 12-bit left aligned data holding register (DAC_DHR12LD)
- 14.5.11 DUAL DAC 8-bit right aligned data holding register (DAC_DHR8RD)
- 14.5.12 DAC channel1 data output register (DAC_DOR1)
- 14.5.13 DAC channel2 data output register (DAC_DOR2)
- 14.5.14 DAC status register (DAC_SR)
- 14.5.15 DAC register map
- 15 Digital camera interface (DCMI)
- 15.1 DCMI introduction
- 15.2 DCMI main features
- 15.3 DCMI clocks
- 15.4 DCMI functional overview
- 15.4.1 DCMI block diagram
- 15.4.2 DMA interface
- 15.4.3 DCMI physical interface
- Table 96. DCMI external signals
- Figure 102. DCMI signal waveforms
- Table 97. Positioning of captured data bytes in 32-bit words (8-bit width)
- Table 98. Positioning of captured data bytes in 32-bit words (10-bit width)
- Table 99. Positioning of captured data bytes in 32-bit words (12-bit width)
- Table 100. Positioning of captured data bytes in 32-bit words (14-bit width)
- 15.4.4 Synchronization
- 15.4.5 Capture modes
- 15.4.6 Crop feature
- 15.4.7 JPEG format
- 15.4.8 FIFO
- 15.5 Data format description
- 15.6 DCMI interrupts
- 15.7 DCMI register description
- 15.7.1 DCMI control register (DCMI_CR)
- 15.7.2 DCMI status register (DCMI_SR)
- 15.7.3 DCMI raw interrupt status register (DCMI_RIS)
- 15.7.4 DCMI interrupt enable register (DCMI_IER)
- 15.7.5 DCMI masked interrupt status register (DCMI_MIS)
- 15.7.6 DCMI interrupt clear register (DCMI_ICR)
- 15.7.7 DCMI embedded synchronization code register (DCMI_ESCR)
- 15.7.8 DCMI embedded synchronization unmask register (DCMI_ESUR)
- 15.7.9 DCMI crop window start (DCMI_CWSTRT)
- 15.7.10 DCMI crop window size (DCMI_CWSIZE)
- 15.7.11 DCMI data register (DCMI_DR)
- 15.7.12 DCMI register map
- 16 Advanced-control timers (TIM1&TIM8)
- 16.1 TIM1&TIM8 introduction
- 16.2 TIM1&TIM8 main features
- 16.3 TIM1&TIM8 functional description
- 16.3.1 Time-base unit
- 16.3.2 Counter modes
- Figure 112. Counter timing diagram, internal clock divided by 1
- Figure 113. Counter timing diagram, internal clock divided by 2
- Figure 114. Counter timing diagram, internal clock divided by 4
- Figure 115. Counter timing diagram, internal clock divided by N
- Figure 116. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded)
- Figure 117. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded)
- Figure 118. Counter timing diagram, internal clock divided by 1
- Figure 119. Counter timing diagram, internal clock divided by 2
- Figure 120. Counter timing diagram, internal clock divided by 4
- Figure 121. Counter timing diagram, internal clock divided by N
- Figure 122. Counter timing diagram, update event when repetition counter is not used
- Figure 123. Counter timing diagram, internal clock divided by 1, TIMx_ARR = 0x6
- Figure 124. Counter timing diagram, internal clock divided by 2
- Figure 125. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36
- Figure 126. Counter timing diagram, internal clock divided by N
- Figure 127. Counter timing diagram, update event with ARPE=1 (counter underflow)
- Figure 128. Counter timing diagram, update event with ARPE=1 (counter overflow)
- 16.3.3 Repetition counter
- 16.3.4 Clock selection
- 16.3.5 Capture/compare channels
- 16.3.6 Input capture mode
- 16.3.7 PWM input mode
- 16.3.8 Forced output mode
- 16.3.9 Output compare mode
- 16.3.10 PWM mode
- 16.3.11 Complementary outputs and dead-time insertion
- 16.3.12 Using the break function
- 16.3.13 Clearing the OCxREF signal on an external event
- 16.3.14 6-step PWM generation
- 16.3.15 One-pulse mode
- 16.3.16 Encoder interface mode
- 16.3.17 Timer input XOR function
- 16.3.18 Interfacing with Hall sensors
- 16.3.19 TIMx and external trigger synchronization
- 16.3.20 Timer synchronization
- 16.3.21 Debug mode
- 16.4 TIM1&TIM8 registers
- 16.4.1 TIM1&TIM8 control register 1 (TIMx_CR1)
- 16.4.2 TIM1&TIM8 control register 2 (TIMx_CR2)
- 16.4.3 TIM1&TIM8 slave mode control register (TIMx_SMCR)
- 16.4.4 TIM1&TIM8 DMA/interrupt enable register (TIMx_DIER)
- 16.4.5 TIM1&TIM8 status register (TIMx_SR)
- 16.4.6 TIM1&TIM8 event generation register (TIMx_EGR)
- 16.4.7 TIM1&TIM8 capture/compare mode register 1 (TIMx_CCMR1)
- 16.4.8 TIM1&TIM8 capture/compare mode register 2 (TIMx_CCMR2)
- 16.4.9 TIM1&TIM8 capture/compare enable register (TIMx_CCER)
- 16.4.10 TIM1&TIM8 counter (TIMx_CNT)
- 16.4.11 TIM1&TIM8 prescaler (TIMx_PSC)
- 16.4.12 TIM1&TIM8 auto-reload register (TIMx_ARR)
- 16.4.13 TIM1&TIM8 repetition counter register (TIMx_RCR)
- 16.4.14 TIM1&TIM8 capture/compare register 1 (TIMx_CCR1)
- 16.4.15 TIM1&TIM8 capture/compare register 2 (TIMx_CCR2)
- 16.4.16 TIM1&TIM8 capture/compare register 3 (TIMx_CCR3)
- 16.4.17 TIM1&TIM8 capture/compare register 4 (TIMx_CCR4)
- 16.4.18 TIM1&TIM8 break and dead-time register (TIMx_BDTR)
- 16.4.19 TIM1&TIM8 DMA control register (TIMx_DCR)
- 16.4.20 TIM1&TIM8 DMA address for full transfer (TIMx_DMAR)
- 16.4.21 TIM1&TIM8 register map
- 17 General-purpose timers (TIM2 to TIM5)
- 17.1 TIM2 to TIM5 introduction
- 17.2 TIM2 to TIM5 main features
- 17.3 TIM2 to TIM5 functional description
- 17.3.1 Time-base unit
- 17.3.2 Counter modes
- Figure 160. Counter timing diagram, internal clock divided by 1
- Figure 161. Counter timing diagram, internal clock divided by 2
- Figure 162. Counter timing diagram, internal clock divided by 4
- Figure 163. Counter timing diagram, internal clock divided by N
- Figure 164. Counter timing diagram, Update event when ARPE=0 (TIMx_ARR not preloaded)
- Figure 165. Counter timing diagram, Update event when ARPE=1 (TIMx_ARR preloaded)
- Figure 166. Counter timing diagram, internal clock divided by 1
- Figure 167. Counter timing diagram, internal clock divided by 2
- Figure 168. Counter timing diagram, internal clock divided by 4
- Figure 169. Counter timing diagram, internal clock divided by N
- Figure 170. Counter timing diagram, Update event
- Figure 171. Counter timing diagram, internal clock divided by 1, TIMx_ARR=0x6
- Figure 172. Counter timing diagram, internal clock divided by 2
- Figure 173. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36
- Figure 174. Counter timing diagram, internal clock divided by N
- Figure 175. Counter timing diagram, Update event with ARPE=1 (counter underflow)
- Figure 176. Counter timing diagram, Update event with ARPE=1 (counter overflow)
- 17.3.3 Clock selection
- 17.3.4 Capture/compare channels
- 17.3.5 Input capture mode
- 17.3.6 PWM input mode
- 17.3.7 Forced output mode
- 17.3.8 Output compare mode
- 17.3.9 PWM mode
- 17.3.10 One-pulse mode
- 17.3.11 Clearing the OCxREF signal on an external event
- 17.3.12 Encoder interface mode
- 17.3.13 Timer input XOR function
- 17.3.14 Timers and external trigger synchronization
- 17.3.15 Timer synchronization
- Figure 197. Master/Slave timer example
- Figure 198. Gating timer 2 with OC1REF of timer 1
- Figure 199. Gating timer 2 with Enable of timer 1
- Figure 200. Triggering timer 2 with update of timer 1
- Figure 201. Triggering timer 2 with Enable of timer 1
- Figure 202. Triggering timer 1 and 2 with timer 1 TI1 input
- 17.3.16 Debug mode
- 17.4 TIM2 to TIM5 registers
- 17.4.1 TIMx control register 1 (TIMx_CR1)
- 17.4.2 TIMx control register 2 (TIMx_CR2)
- 17.4.3 TIMx slave mode control register (TIMx_SMCR)
- 17.4.4 TIMx DMA/Interrupt enable register (TIMx_DIER)
- 17.4.5 TIMx status register (TIMx_SR)
- 17.4.6 TIMx event generation register (TIMx_EGR)
- 17.4.7 TIMx capture/compare mode register 1 (TIMx_CCMR1)
- 17.4.8 TIMx capture/compare mode register 2 (TIMx_CCMR2)
- 17.4.9 TIMx capture/compare enable register (TIMx_CCER)
- 17.4.10 TIMx counter (TIMx_CNT)
- 17.4.11 TIMx prescaler (TIMx_PSC)
- 17.4.12 TIMx auto-reload register (TIMx_ARR)
- 17.4.13 TIMx capture/compare register 1 (TIMx_CCR1)
- 17.4.14 TIMx capture/compare register 2 (TIMx_CCR2)
- 17.4.15 TIMx capture/compare register 3 (TIMx_CCR3)
- 17.4.16 TIMx capture/compare register 4 (TIMx_CCR4)
- 17.4.17 TIMx DMA control register (TIMx_DCR)
- 17.4.18 TIMx DMA address for full transfer (TIMx_DMAR)
- 17.4.19 TIM2 option register (TIM2_OR)
- 17.4.20 TIM5 option register (TIM5_OR)
- 17.4.21 TIMx register map
- 18 General-purpose timers (TIM9 to TIM14)
- 18.1 TIM9 to TIM14 introduction
- 18.2 TIM9 to TIM14 main features
- 18.3 TIM9 to TIM14 functional description
- 18.3.1 Time-base unit
- 18.3.2 Counter modes
- Figure 207. Counter timing diagram, internal clock divided by 1
- Figure 208. Counter timing diagram, internal clock divided by 2
- Figure 209. Counter timing diagram, internal clock divided by 4
- Figure 210. Counter timing diagram, internal clock divided by N
- Figure 211. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded)
- Figure 212. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded)
- 18.3.3 Clock selection
- 18.3.4 Capture/compare channels
- 18.3.5 Input capture mode
- 18.3.6 PWM input mode (only for TIM9/12)
- 18.3.7 Forced output mode
- 18.3.8 Output compare mode
- 18.3.9 PWM mode
- 18.3.10 One-pulse mode
- 18.3.11 TIM9/12 external trigger synchronization
- 18.3.12 Timer synchronization (TIM9/12)
- 18.3.13 Debug mode
- 18.4 TIM9 and TIM12 registers
- 18.4.1 TIM9/12 control register 1 (TIMx_CR1)
- 18.4.2 TIM9/12 slave mode control register (TIMx_SMCR)
- 18.4.3 TIM9/12 Interrupt enable register (TIMx_DIER)
- 18.4.4 TIM9/12 status register (TIMx_SR)
- 18.4.5 TIM9/12 event generation register (TIMx_EGR)
- 18.4.6 TIM9/12 capture/compare mode register 1 (TIMx_CCMR1)
- 18.4.7 TIM9/12 capture/compare enable register (TIMx_CCER)
- 18.4.8 TIM9/12 counter (TIMx_CNT)
- 18.4.9 TIM9/12 prescaler (TIMx_PSC)
- 18.4.10 TIM9/12 auto-reload register (TIMx_ARR)
- 18.4.11 TIM9/12 capture/compare register 1 (TIMx_CCR1)
- 18.4.12 TIM9/12 capture/compare register 2 (TIMx_CCR2)
- 18.4.13 TIM9/12 register map
- 18.5 TIM10/11/13/14 registers
- 18.5.1 TIM10/11/13/14 control register 1 (TIMx_CR1)
- 18.5.2 TIM10/11/13/14 Interrupt enable register (TIMx_DIER)
- 18.5.3 TIM10/11/13/14 status register (TIMx_SR)
- 18.5.4 TIM10/11/13/14 event generation register (TIMx_EGR)
- 18.5.5 TIM10/11/13/14 capture/compare mode register 1 (TIMx_CCMR1)
- 18.5.6 TIM10/11/13/14 capture/compare enable register (TIMx_CCER)
- 18.5.7 TIM10/11/13/14 counter (TIMx_CNT)
- 18.5.8 TIM10/11/13/14 prescaler (TIMx_PSC)
- 18.5.9 TIM10/11/13/14 auto-reload register (TIMx_ARR)
- 18.5.10 TIM10/11/13/14 capture/compare register 1 (TIMx_CCR1)
- 18.5.11 TIM11 option register 1 (TIM11_OR)
- 18.5.12 TIM10/11/13/14 register map
- 19 Basic timers (TIM6&TIM7)
- 19.1 TIM6&TIM7 introduction
- 19.2 TIM6&TIM7 main features
- 19.3 TIM6&TIM7 functional description
- 19.3.1 Time-base unit
- 19.3.2 Counting mode
- Figure 229. Counter timing diagram, internal clock divided by 1
- Figure 230. Counter timing diagram, internal clock divided by 2
- Figure 231. Counter timing diagram, internal clock divided by 4
- Figure 232. Counter timing diagram, internal clock divided by N
- Figure 233. Counter timing diagram, update event when ARPE = 0 (TIMx_ARR not preloaded)
- Figure 234. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded)
- 19.3.3 Clock source
- 19.3.4 Debug mode
- 19.4 TIM6&TIM7 registers
- 19.4.1 TIM6&TIM7 control register 1 (TIMx_CR1)
- 19.4.2 TIM6&TIM7 control register 2 (TIMx_CR2)
- 19.4.3 TIM6&TIM7 DMA/Interrupt enable register (TIMx_DIER)
- 19.4.4 TIM6&TIM7 status register (TIMx_SR)
- 19.4.5 TIM6&TIM7 event generation register (TIMx_EGR)
- 19.4.6 TIM6&TIM7 counter (TIMx_CNT)
- 19.4.7 TIM6&TIM7 prescaler (TIMx_PSC)
- 19.4.8 TIM6&TIM7 auto-reload register (TIMx_ARR)
- 19.4.9 TIM6&TIM7 register map
- 20 Independent watchdog (IWDG)
- 21 Window watchdog (WWDG)
- 22 Real-time clock (RTC)
- 22.1 Introduction
- 22.2 RTC main features
- 22.3 RTC functional description
- 22.3.1 Clock and prescalers
- 22.3.2 Real-time clock and calendar
- 22.3.3 Programmable alarms
- 22.3.4 Periodic auto-wakeup
- 22.3.5 RTC initialization and configuration
- 22.3.6 Reading the calendar
- 22.3.7 Resetting the RTC
- 22.3.8 RTC synchronization
- 22.3.9 RTC reference clock detection
- 22.3.10 RTC coarse digital calibration
- 22.3.11 RTC smooth digital calibration
- 22.3.12 Timestamp function
- 22.3.13 Tamper detection
- 22.3.14 Calibration clock output
- 22.3.15 Alarm output
- 22.4 RTC and low power modes
- 22.5 RTC interrupts
- 22.6 RTC registers
- 22.6.1 RTC time register (RTC_TR)
- 22.6.2 RTC date register (RTC_DR)
- 22.6.3 RTC control register (RTC_CR)
- 22.6.4 RTC initialization and status register (RTC_ISR)
- 22.6.5 RTC prescaler register (RTC_PRER)
- 22.6.6 RTC wakeup timer register (RTC_WUTR)
- 22.6.7 RTC calibration register (RTC_CALIBR)
- 22.6.8 RTC alarm A register (RTC_ALRMAR)
- 22.6.9 RTC alarm B register (RTC_ALRMBR)
- 22.6.10 RTC write protection register (RTC_WPR)
- 22.6.11 RTC sub second register (RTC_SSR)
- 22.6.12 RTC shift control register (RTC_SHIFTR)
- 22.6.13 RTC time stamp time register (RTC_TSTR)
- 22.6.14 RTC time stamp date register (RTC_TSDR)
- 22.6.15 RTC timestamp sub second register (RTC_TSSSR)
- 22.6.16 RTC calibration register (RTC_CALR)
- 22.6.17 RTC tamper and alternate function configuration register (RTC_TAFCR)
- 22.6.18 RTC alarm A sub second register (RTC_ALRMASSR)
- 22.6.19 RTC alarm B sub second register (RTC_ALRMBSSR)
- 22.6.20 RTC backup registers (RTC_BKPxR)
- 22.6.21 RTC register map
- 23 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface
- 23.1 Introduction
- 23.2 FMPI2C main features
- 23.3 FMPI2C implementation
- 23.4 FMPI2C functional description
- 23.4.1 FMPI2C block diagram
- 23.4.2 FMPI2C clock requirements
- 23.4.3 Mode selection
- 23.4.4 FMPI2C initialization
- 23.4.5 Software reset
- 23.4.6 Data transfer
- 23.4.7 FMPI2C slave mode
- Figure 246. Slave initialization flowchart
- Figure 247. Transfer sequence flowchart for FMPI2C slave transmitter, NOSTRETCH=0
- Figure 248. Transfer sequence flowchart for FMPI2C slave transmitter, NOSTRETCH=1
- Figure 249. Transfer bus diagrams for FMPI2C slave transmitter
- Figure 250. Transfer sequence flowchart for slave receiver with NOSTRETCH=0
- Figure 251. Transfer sequence flowchart for slave receiver with NOSTRETCH=1
- Figure 252. Transfer bus diagrams for FMPI2C slave receiver
- 23.4.8 FMPI2C master mode
- Figure 253. Master clock generation
- Table 130. I2C-SMBUS specification clock timings
- Figure 254. Master initialization flowchart
- Figure 255. 10-bit address read access with HEAD10R=0
- Figure 256. 10-bit address read access with HEAD10R=1
- Figure 257. Transfer sequence flowchart for FMPI2C master transmitter for N≤255 bytes
- Figure 258. Transfer sequence flowchart for FMPI2C master transmitter for N>255 bytes
- Figure 259. Transfer bus diagrams for FMPI2C master transmitter
- Figure 260. Transfer sequence flowchart for FMPI2C master receiver for N≤255 bytes
- Figure 261. Transfer sequence flowchart for FMPI2C master receiver for N >255 bytes
- Figure 262. Transfer bus diagrams for FMPI2C master receiver
- 23.4.9 FMPI2C_TIMINGR register configuration examples
- 23.4.10 SMBus specific features
- 23.4.11 SMBus initialization
- 23.4.12 SMBus: FMPI2C_TIMEOUTR register configuration examples
- 23.4.13 SMBus slave mode
- Figure 264. Transfer sequence flowchart for SMBus slave transmitter N bytes + PEC
- Figure 265. Transfer bus diagrams for SMBus slave transmitter (SBC=1)
- Figure 266. Transfer sequence flowchart for SMBus slave receiver N Bytes + PEC
- Figure 267. Bus transfer diagrams for SMBus slave receiver (SBC=1)
- Figure 268. Bus transfer diagrams for SMBus master transmitter
- Figure 269. Bus transfer diagrams for SMBus master receiver
- 23.4.14 Error conditions
- 23.4.15 DMA requests
- 23.4.16 Debug mode
- 23.5 FMPI2C low-power modes
- 23.6 FMPI2C interrupts
- 23.7 FMPI2C registers
- 23.7.1 Control register 1 (FMPI2C_CR1)
- 23.7.2 Control register 2 (FMPI2C_CR2)
- 23.7.3 Own address 1 register (FMPI2C_OAR1)
- 23.7.4 Own address 2 register (FMPI2C_OAR2)
- 23.7.5 Timing register (FMPI2C_TIMINGR)
- 23.7.6 Timeout register (FMPI2C_TIMEOUTR)
- 23.7.7 Interrupt and status register (FMPI2C_ISR)
- 23.7.8 Interrupt clear register (FMPI2C_ICR)
- 23.7.9 PEC register (FMPI2C_PECR)
- 23.7.10 Receive data register (FMPI2C_RXDR)
- 23.7.11 Transmit data register (FMPI2C_TXDR)
- 23.7.12 FMPI2C register map
- 24 Inter-integrated circuit (I2C) interface
- 24.1 I2C introduction
- 24.2 I2C main features
- 24.3 I2C functional description
- 24.4 I2C interrupts
- 24.5 I2C debug mode
- 24.6 I2C registers
- 24.6.1 I2C Control register 1 (I2C_CR1)
- 24.6.2 I2C Control register 2 (I2C_CR2)
- 24.6.3 I2C Own address register 1 (I2C_OAR1)
- 24.6.4 I2C Own address register 2 (I2C_OAR2)
- 24.6.5 I2C Data register (I2C_DR)
- 24.6.6 I2C Status register 1 (I2C_SR1)
- 24.6.7 I2C Status register 2 (I2C_SR2)
- 24.6.8 I2C Clock control register (I2C_CCR)
- 24.6.9 I2C TRISE register (I2C_TRISE)
- 24.6.10 I2C FLTR register (I2C_FLTR)
- 24.6.11 I2C register map
- 25 Universal synchronous asynchronous receiver transmitter (USART)
- 25.1 USART introduction
- 25.2 USART main features
- 25.3 USART implementation
- 25.4 USART functional description
- Figure 278. USART block diagram
- 25.4.1 USART character description
- 25.4.2 Transmitter
- 25.4.3 Receiver
- 25.4.4 Fractional baud rate generation
- Table 145. Error calculation for programmed baud rates at fPCLK = 8 MHz or fPCLK = 12 MHz, oversampling by 16
- Table 146. Error calculation for programmed baud rates at fPCLK = 8 MHz or fPCLK = 12 MHz, oversampling by 8
- Table 147. Error calculation for programmed baud rates at fPCLK = 16 MHz or fPCLK = 24 MHz, oversampling by 16
- Table 148. Error calculation for programmed baud rates at fPCLK = 16 MHz or fPCLK = 24 MHz, oversampling by 8
- Table 149. Error calculation for programmed baud rates at fPCLK = 8 MHz or fPCLK = 16 MHz, oversampling by 16
- Table 150. Error calculation for programmed baud rates at fPCLK = 8 MHz or fPCLK = 16 MHz, oversampling by 8
- Table 151. Error calculation for programmed baud rates at fPCLK = 30 MHz or fPCLK = 60 MHz, oversampling by 16
- Table 152. Error calculation for programmed baud rates at fPCLK = 30 MHz or fPCLK = 60 MHz, oversampling by 8
- Table 153. Error calculation for programmed baud rates at fPCLK = 42 MHz or fPCLK = 84 Hz, oversampling by 16
- Table 154. Error calculation for programmed baud rates at fPCLK = 42 MHz or fPCLK = 84 MHz, oversampling by 8
- 25.4.5 USART receiver tolerance to clock deviation
- 25.4.6 Multiprocessor communication
- 25.4.7 Parity control
- 25.4.8 LIN (local interconnection network) mode
- 25.4.9 USART synchronous mode
- 25.4.10 Single-wire half-duplex communication
- 25.4.11 Smartcard
- 25.4.12 IrDA SIR ENDEC block
- 25.4.13 Continuous communication using DMA
- 25.4.14 Hardware flow control
- 25.5 USART interrupts
- 25.6 USART registers
- 26 Serial peripheral interface/ inter-IC sound (SPI/I2S)
- 26.1 Introduction
- 26.2 SPI/I2S implementation
- 26.3 SPI functional description
- 26.3.1 General description
- 26.3.2 Communications between one master and one slave
- 26.3.3 Standard multi-slave communication
- 26.3.4 Multi-master communication
- 26.3.5 Slave select (NSS) pin management
- 26.3.6 Communication formats
- 26.3.7 SPI configuration
- 26.3.8 Procedure for enabling SPI
- 26.3.9 Data transmission and reception procedures
- 26.3.10 Procedure for disabling the SPI
- 26.3.11 Communication using DMA (direct memory addressing)
- 26.3.12 SPI status flags
- 26.3.13 SPI error flags
- 26.4 SPI special features
- 26.5 SPI interrupts
- 26.6 I2S functional description
- 26.6.1 I2S general description
- 26.6.2 I2S full-duplex
- 26.6.3 Supported audio protocols
- Figure 318. I2S Philips protocol waveforms (16/32-bit full accuracy, CPOL = 0)
- Figure 319. I2S Philips standard waveforms (24-bit frame with CPOL = 0)
- Figure 320. Transmitting 0x8EAA33
- Figure 321. Receiving 0x8EAA33
- Figure 322. I2S Philips standard (16-bit extended to 32-bit packet frame with CPOL = 0)
- Figure 323. Example of 16-bit data frame extended to 32-bit channel frame
- Figure 324. MSB Justified 16-bit or 32-bit full-accuracy length with CPOL = 0
- Figure 325. MSB justified 24-bit frame length with CPOL = 0
- Figure 326. MSB justified 16-bit extended to 32-bit packet frame with CPOL = 0
- Figure 327. LSB justified 16-bit or 32-bit full-accuracy with CPOL = 0
- Figure 328. LSB justified 24-bit frame length with CPOL = 0
- Figure 329. Operations required to transmit 0x3478AE
- Figure 330. Operations required to receive 0x3478AE
- Figure 331. LSB justified 16-bit extended to 32-bit packet frame with CPOL = 0
- Figure 332. Example of 16-bit data frame extended to 32-bit channel frame
- Figure 333. PCM standard waveforms (16-bit)
- Figure 334. PCM standard waveforms (16-bit extended to 32-bit packet frame)
- 26.6.4 Clock generator
- 26.6.5 I2S master mode
- 26.6.6 I2S slave mode
- 26.6.7 I2S status flags
- 26.6.8 I2S error flags
- 26.6.9 I2S interrupts
- 26.6.10 DMA features
- 26.7 SPI and I2S registers
- 26.7.1 SPI control register 1 (SPI_CR1) (not used in I2S mode)
- 26.7.2 SPI control register 2 (SPI_CR2)
- 26.7.3 SPI status register (SPI_SR)
- 26.7.4 SPI data register (SPI_DR)
- 26.7.5 SPI CRC polynomial register (SPI_CRCPR) (not used in I2S mode)
- 26.7.6 SPI RX CRC register (SPI_RXCRCR) (not used in I2S mode)
- 26.7.7 SPI TX CRC register (SPI_TXCRCR) (not used in I2S mode)
- 26.7.8 SPI_I2S configuration register (SPI_I2SCFGR)
- 26.7.9 SPI_I2S prescaler register (SPI_I2SPR)
- 26.7.10 SPI register map
- 27 SPDIF receiver interface (SPDIFRX)
- 27.1 SPDIFRX interface introduction
- 27.2 SPDIFRX main features
- 27.3 SPDIFRX functional description
- Figure 337. SPDIFRX block diagram
- 27.3.1 S/PDIF protocol (IEC-60958)
- 27.3.2 SPDIFRX decoder (SPDIFRX_DC)
- 27.3.3 SPDIFRX tolerance to clock deviation
- 27.3.4 SPDIFRX synchronization
- 27.3.5 SPDIFRX handling
- 27.3.6 Data reception management
- 27.3.7 Dedicated control flow
- 27.3.8 Reception errors
- 27.3.9 Clocking strategy
- 27.3.10 Symbol clock generation
- 27.3.11 DMA Interface
- 27.3.12 Interrupt Generation
- 27.3.13 Register protection
- 27.4 Programming procedures
- 27.5 SPDIFRX interface registers
- 27.5.1 Control register (SPDIFRX_CR)
- 27.5.2 Interrupt mask register (SPDIFRX_IMR)
- 27.5.3 Status register (SPDIFRX_SR)
- 27.5.4 Interrupt flag clear register (SPDIFRX_IFCR)
- 27.5.5 Data input register (SPDIFRX_DR)
- 27.5.6 Data input register (SPDIFRX_DR)
- 27.5.7 Data input register (SPDIFRX_DR)
- 27.5.8 Channel status register (SPDIFRX_CSR)
- 27.5.9 Debug Information register (SPDIFRX_DIR)
- 27.5.10 SPDIFRX version register (SPDIFRX_VERR)
- 27.5.11 SPDIFRX identification register (SPDIFRX_IDR)
- 27.5.12 SPDIFRX size identification register (SPDIFRX_SIDR)
- 27.5.13 SPDIFRX interface register map
- 28 Serial audio interface (SAI)
- 28.1 Introduction
- 28.2 SAI main features
- 28.3 SAI functional description
- 28.3.1 SAI block diagram
- 28.3.2 SAI pins and internal signals
- 28.3.3 Main SAI modes
- 28.3.4 SAI synchronization mode
- 28.3.5 Audio data size
- 28.3.6 Frame synchronization
- 28.3.7 Slot configuration
- 28.3.8 SAI clock generator
- 28.3.9 Internal FIFOs
- 28.3.10 AC’97 link controller
- 28.3.11 SPDIF output
- 28.3.12 Specific features
- 28.3.13 Error flags
- 28.3.14 Disabling the SAI
- 28.3.15 SAI DMA interface
- 28.4 SAI interrupts
- 28.5 SAI registers
- 28.5.1 Global configuration register (SAI_GCR)
- 28.5.2 Configuration register 1 (SAI_ACR1 / SAI_BCR1)
- 28.5.3 Configuration register 2 (SAI_ACR2 / SAI_BCR2)
- 28.5.4 Frame configuration register (SAI_AFRCR / SAI_BFRCR)
- 28.5.5 Slot register (SAI_ASLOTR / SAI_BSLOTR)
- 28.5.6 Interrupt mask register 2 (SAI_AIM / SAI_BIM)
- 28.5.7 Status register (SAI_ASR / SAI_BSR)
- 28.5.8 Clear flag register (SAI_ACLRFR / SAI_BCLRFR)
- 28.5.9 Data register (SAI_ADR / SAI_BDR)
- 28.5.10 SAI register map
- 29 Secure digital input/output interface (SDIO)
- 29.1 SDIO main features
- 29.2 SDIO bus topology
- 29.3 SDIO functional description
- Figure 374. SDIO block diagram
- Table 178. SDIO I/O definitions
- 29.3.1 SDIO adapter
- Figure 375. SDIO adapter
- Figure 376. Control unit
- Figure 377. SDIO_CK clock dephasing (BYPASS = 0)
- Figure 378. SDIO adapter command path
- Figure 379. Command path state machine (SDIO)
- Figure 380. SDIO command transfer
- Table 179. Command format
- Table 180. Short response format
- Table 181. Long response format
- Table 182. Command path status flags
- Figure 381. Data path
- Figure 382. Data path state machine (DPSM)
- Table 183. Data token format
- Table 184. DPSM flags
- Table 185. Transmit FIFO status flags
- Table 186. Receive FIFO status flags
- 29.3.2 SDIO APB2 interface
- 29.4 Card functional description
- 29.4.1 Card identification mode
- 29.4.2 Card reset
- 29.4.3 Operating voltage range validation
- 29.4.4 Card identification process
- 29.4.5 Block write
- 29.4.6 Block read
- 29.4.7 Stream access, stream write and stream read (MultiMediaCard only)
- 29.4.8 Erase: group erase and sector erase
- 29.4.9 Wide bus selection or deselection
- 29.4.10 Protection management
- 29.4.11 Card status register
- 29.4.12 SD status register
- 29.4.13 SD I/O mode
- 29.4.14 Commands and responses
- 29.5 Response formats
- 29.6 SDIO I/O card-specific operations
- 29.7 HW flow control
- 29.8 SDIO registers
- 29.8.1 SDIO power control register (SDIO_POWER)
- 29.8.2 SDIO clock control register (SDIO_CLKCR)
- 29.8.3 SDIO argument register (SDIO_ARG)
- 29.8.4 SDIO command register (SDIO_CMD)
- 29.8.5 SDIO command response register (SDIO_RESPCMD)
- 29.8.6 SDIO response 1..4 register (SDIO_RESPx)
- 29.8.7 SDIO data timer register (SDIO_DTIMER)
- 29.8.8 SDIO data length register (SDIO_DLEN)
- 29.8.9 SDIO data control register (SDIO_DCTRL)
- 29.8.10 SDIO data counter register (SDIO_DCOUNT)
- 29.8.11 SDIO status register (SDIO_STA)
- 29.8.12 SDIO interrupt clear register (SDIO_ICR)
- 29.8.13 SDIO mask register (SDIO_MASK)
- 29.8.14 SDIO FIFO counter register (SDIO_FIFOCNT)
- 29.8.15 SDIO data FIFO register (SDIO_FIFO)
- 29.8.16 SDIO register map
- 30 Controller area network (bxCAN)
- 30.1 Introduction
- 30.2 bxCAN main features
- 30.3 bxCAN general description
- 30.4 bxCAN operating modes
- 30.5 Test mode
- 30.6 Behavior in debug mode
- 30.7 bxCAN functional description
- 30.8 bxCAN interrupts
- 30.9 CAN registers
- 31 USB on-the-go full-speed/high-speed (OTG_FS/OTG_HS)
- 31.1 Introduction
- 31.2 USB_OTG main features
- 31.3 USB_OTG Implementation
- 31.4 USB OTG functional description
- 31.5 OTG dual role device (DRD)
- 31.6 USB peripheral
- 31.7 USB host
- 31.8 SOF trigger
- 31.9 Power options
- 31.10 Dynamic update of the OTG_HFIR register
- 31.11 USB data FIFOs
- 31.12 OTG_FS system performance
- 31.13 OTG_FS/OTG_HS interrupts
- 31.14 OTG_FS/OTG_HS control and status registers
- 31.15 OTG_FS/OTG_HS registers
- 31.15.1 OTG control and status register (OTG_GOTGCTL)
- 31.15.2 OTG interrupt register (OTG_GOTGINT)
- 31.15.3 OTG AHB configuration register (OTG_GAHBCFG)
- 31.15.4 OTG USB configuration register (OTG_GUSBCFG)
- 31.15.5 OTG reset register (OTG_GRSTCTL)
- 31.15.6 OTG core interrupt register (OTG_GINTSTS)
- 31.15.7 OTG interrupt mask register (OTG_GINTMSK)
- 31.15.8 OTG_FS Receive status debug read/OTG status read and pop registers (OTG_GRXSTSR/OTG_GRXSTSP)
- 31.15.9 OTG Receive FIFO size register (OTG_GRXFSIZ)
- 31.15.10 OTG Host non-periodic transmit FIFO size register (OTG_HNPTXFSIZ)/Endpoint 0 Transmit FIFO size (OTG_DIEPTXF0)
- 31.15.11 OTG non-periodic transmit FIFO/queue status register (OTG_HNPTXSTS)
- 31.15.12 OTG I2C access register (OTG_GI2CCTL)
- 31.15.13 OTG general core configuration register (OTG_GCCFG)
- 31.15.14 OTG core ID register (OTG_CID)
- 31.15.15 OTG core LPM configuration register (OTG_GLPMCFG)
- 31.15.16 OTG Host periodic transmit FIFO size register (OTG_HPTXFSIZ)
- 31.15.17 OTG device IN endpoint transmit FIFO size register (OTG_DIEPTXFx) (x = 1..5[FS] /8[HS], where x is the FIFO_number)
- 31.15.18 Host-mode registers
- 31.15.19 OTG Host configuration register (OTG_HCFG)
- 31.15.20 OTG Host frame interval register (OTG_HFIR)
- 31.15.21 OTG Host frame number/frame time remaining register (OTG_HFNUM)
- 31.15.22 OTG_Host periodic transmit FIFO/queue status register (OTG_HPTXSTS)
- 31.15.23 OTG Host all channels interrupt register (OTG_HAINT)
- 31.15.24 OTG Host all channels interrupt mask register (OTG_HAINTMSK)
- 31.15.25 OTG Host port control and status register (OTG_HPRT)
- 31.15.26 OTG Host channel-x characteristics register (OTG_HCCHARx) (x = 0..15[HS] / 11[FS], where x = Channel_number)
- 31.15.27 OTG Host channel-x split control register (OTG_HCSPLTx) (x = 0..15, where x = Channel_number)
- 31.15.28 OTG Host channel-x interrupt register (OTG_HCINTx) (x = 0..15[HS] / 11[FS], where x = Channel_number)
- 31.15.29 OTG Host channel-x interrupt mask register (OTG_HCINTMSKx) (x = 0..15[HS] / 11[FS], where x = Channel_number)
- 31.15.30 OTG Host channel-x transfer size register (OTG_HCTSIZx) (x = 0..15[HS] / 11[FS], where x = Channel_number)
- 31.15.31 OTG Host channel-x DMA address register (OTG_HCDMAx) (x = 0..15, where x = Channel_number)
- 31.15.32 Device-mode registers
- 31.15.33 OTG device configuration register (OTG_DCFG)
- 31.15.34 OTG device control register (OTG_DCTL)
- 31.15.35 OTG device status register (OTG_DSTS)
- 31.15.36 OTG device IN endpoint common interrupt mask register (OTG_DIEPMSK)
- 31.15.37 OTG device OUT endpoint common interrupt mask register (OTG_DOEPMSK)
- 31.15.38 OTG device all endpoints interrupt register (OTG_DAINT)
- 31.15.39 OTG all endpoints interrupt mask register (OTG_DAINTMSK)
- 31.15.40 OTG device VBUS discharge time register (OTG_DVBUSDIS)
- 31.15.41 OTG device VBUS pulsing time register (OTG_DVBUSPULSE)
- 31.15.42 OTG Device threshold control register (OTG_DTHRCTL)
- 31.15.43 OTG device each endpoint interrupt register (OTG_DEACHINT)
- 31.15.44 OTG device IN endpoint FIFO empty interrupt mask register (OTG_DIEPEMPMSK)
- 31.15.45 OTG device each endpoint interrupt register mask (OTG_DEACHINTMSK)
- 31.15.46 OTG device control IN endpoint 0 control register (OTG_DIEPCTL0)
- 31.15.47 OTG device endpoint-x control register (OTG_DIEPCTLx) (x = 1..5[FS] / 0..8[HS], where x = Endpoint_number)
- 31.15.48 OTG device control OUT endpoint 0 control register (OTG_DOEPCTL0)
- 31.15.49 OTG device endpoint-x control register (OTG_DOEPCTLx) (x = 1..5[FS] /8[HS], where x = Endpoint_number)
- 31.15.50 OTG device endpoint-x interrupt register (OTG_DIEPINTx) (x = 0..5[FS] /8[HS], where x = Endpoint_number)
- 31.15.51 OTG device endpoint-x interrupt register (OTG_DOEPINTx) (x = 0..5[FS] /8[HS], where x = Endpoint_number)
- 31.15.52 OTG device IN endpoint 0 transfer size register (OTG_DIEPTSIZ0)
- 31.15.53 OTG Device channel-x DMA address register (OTG_DIEPDMAx) (x = 0..15, where x= Channel_number)
- 31.15.54 OTG Device channel-x DMA address register (OTG_DOEPDMAx) (x = 0..15, where x= Channel_number)
- 31.15.55 OTG device OUT endpoint 0 transfer size register (OTG_DOEPTSIZ0)
- 31.15.56 OTG device IN endpoint-x transfer size register (OTG_DIEPTSIZx) (x = 1..5[FS] /8[HS], where x= Endpoint_number)
- 31.15.57 OTG device IN endpoint transmit FIFO status register (OTG_DTXFSTSx) (x = 0..5[FS] /8[HS], where x = Endpoint_number)
- 31.15.58 OTG device OUT endpoint-x transfer size register (OTG_DOEPTSIZx) (x = 1..5[FS] /8[HS], where x = Endpoint_number)
- 31.15.59 OTG power and clock gating control register (OTG_PCGCCTL)
- 31.15.60 OTG_FS/OTG_HS register map
- 31.16 OTG_FS/OTG_HS programming model
- 31.16.1 Core initialization
- 31.16.2 Host initialization
- 31.16.3 Device initialization
- 31.16.4 DMA mode
- 31.16.5 Host programming model
- Figure 409. Transmit FIFO write task
- Figure 410. Receive FIFO read task
- Figure 411. Normal bulk/control OUT/SETUP
- Figure 412. Bulk/control IN transactions
- Figure 413. Normal interrupt OUT
- Figure 414. Normal interrupt IN
- Figure 415. Isochronous OUT transactions
- Figure 416. Isochronous IN transactions
- Figure 417. Normal bulk/control OUT/SETUP transactions - DMA
- Figure 418. Normal bulk/control IN transaction - DMA
- Figure 419. Normal interrupt OUT transactions - DMA mode
- Figure 420. Normal interrupt IN transactions - DMA mode
- Figure 421. Normal isochronous OUT transaction - DMA mode
- Figure 422. Normal isochronous IN transactions - DMA mode
- 31.16.6 Device programming model
- 31.16.7 Worst case response time
- 31.16.8 OTG programming model
- 32 HDMI-CEC controller (HDMI-CEC)
- 32.1 Introduction
- 32.2 HDMI-CEC controller main features
- 32.3 HDMI-CEC functional description
- 32.4 Arbitration
- 32.5 Error handling
- 32.6 HDMI-CEC interrupts
- 32.7 HDMI-CEC registers
- 33 Debug support (DBG)
- 33.1 Overview
- 33.2 Reference ARM® documentation
- 33.3 SWJ debug port (serial wire and JTAG)
- 33.4 Pinout and debug port pins
- 33.5 STM32F446xx JTAG TAP connection
- 33.6 ID codes and locking mechanism
- 33.7 JTAG debug port
- 33.8 SW debug port
- 33.9 AHB-AP (AHB access port) - valid for both JTAG-DP and SW-DP
- 33.10 Core debug
- 33.11 Capability of the debugger host to connect under system reset
- 33.12 FPB (Flash patch breakpoint)
- 33.13 DWT (data watchpoint trigger)
- 33.14 ITM (instrumentation trace macrocell)
- 33.15 ETM (Embedded trace macrocell)
- 33.16 MCU debug component (DBGMCU)
- 33.17 TPIU (trace port interface unit)
- 33.17.1 Introduction
- 33.17.2 TRACE pin assignment
- 33.17.3 TPUI formatter
- 33.17.4 TPUI frame synchronization packets
- 33.17.5 Transmission of the synchronization frame packet
- 33.17.6 Synchronous mode
- 33.17.7 Asynchronous mode
- 33.17.8 TRACECLKIN connection in STM32F446xx
- 33.17.9 TPIU registers
- 33.17.10 Example of configuration
- 33.18 DBG register map
- 34 Device electronic signature
- 35 Revision history