STM32F410 Advanced ARM® Based 32 Bit MCUs Stm32f4 Reference Manual
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- 1 Documentation conventions
- 2 System and memory overview
- 3 Embedded Flash memory interface
- 3.1 Introduction
- 3.2 Main features
- 3.3 Embedded Flash memory
- 3.4 Read interface
- 3.5 Erase and program operations
- 3.6 Option bytes
- 3.7 One-time programmable bytes
- 3.8 Flash interface registers
- 4 Power controller (PWR)
- 4.1 Power supplies
- 4.2 Power supply supervisor
- 4.3 Low-power modes
- Entering low-power mode
- Exiting low-power mode
- Table 14. Low-power mode summary
- 4.3.1 Optimizing PLL VCO frequency
- 4.3.2 Slowing down system clocks
- 4.3.3 Peripheral clock gating
- 4.3.4 Flash memory in low-power mode for code execution from RAM
- 4.3.5 Sleep mode
- 4.3.6 Batch acquisition mode
- 4.3.7 Stop mode
- 4.3.8 Standby mode
- 4.3.9 Programming the RTC alternate functions to wake up the device from the Stop and Standby modes
- 4.4 Power control registers
- 4.5 PWR register map
- 5 Reset and clock control (RCC)
- 5.1 Reset
- 5.2 Clocks
- 5.3 RCC registers
- 5.3.1 RCC clock control register (RCC_CR)
- 5.3.2 RCC PLL configuration register (RCC_PLLCFGR)
- 5.3.3 RCC clock configuration register (RCC_CFGR)
- 5.3.4 RCC clock interrupt register (RCC_CIR)
- 5.3.5 RCC AHB1 peripheral reset register (RCC_AHB1RSTR)
- 5.3.6 RCC APB1 peripheral reset register for (RCC_APB1RSTR)
- 5.3.7 RCC APB2 peripheral reset register (RCC_APB2RSTR)
- 5.3.8 RCC AHB1 peripheral clock enable register (RCC_AHB1ENR)
- 5.3.9 RCC APB1 peripheral clock enable register (RCC_APB1ENR)
- 5.3.10 RCC APB2 peripheral clock enable register (RCC_APB2ENR)
- 5.3.11 RCC AHB1 peripheral clock enable in low power mode register (RCC_AHB1LPENR)
- 5.3.12 RCC APB1 peripheral clock enable in low power mode register (RCC_APB1LPENR)
- 5.3.13 RCC APB2 peripheral clock enabled in low power mode register (RCC_APB2LPENR)
- 5.3.14 RCC Backup domain control register (RCC_BDCR)
- 5.3.15 RCC clock control & status register (RCC_CSR)
- 5.3.16 RCC spread spectrum clock generation register (RCC_SSCGR)
- 5.3.17 RCC Dedicated Clocks Configuration Register (RCC_DCKCFGR)
- 5.3.18 RCC dedicated Clocks Configuration Register 2 (RCC_DCKCFGR2)
- 5.3.19 RCC register map
- 6 General-purpose I/Os (GPIO)
- 6.1 GPIO introduction
- 6.2 GPIO main features
- 6.3 GPIO functional description
- Table 24. Port bit configuration table (continued)
- 6.3.1 General-purpose I/O (GPIO)
- 6.3.2 I/O pin multiplexer and mapping
- 6.3.3 I/O port control registers
- 6.3.4 I/O port data registers
- 6.3.5 I/O data bitwise handling
- 6.3.6 GPIO locking mechanism
- 6.3.7 I/O alternate function input/output
- 6.3.8 External interrupt/wakeup lines
- 6.3.9 Input configuration
- 6.3.10 Output configuration
- 6.3.11 Alternate function configuration
- 6.3.12 Analog configuration
- 6.3.13 Using the OSC32_IN/OSC32_OUT pins as GPIO PC14/PC15 port pins
- 6.3.14 Using the OSC_IN/OSC_OUT pins as GPIO PH0/PH1 port pins
- 6.3.15 Selection of RTC additional functions
- 6.4 GPIO registers
- 6.4.1 GPIO port mode register (GPIOx_MODER) (x = A..C and H)
- 6.4.2 GPIO port output type register (GPIOx_OTYPER) (x = A..C and H)
- 6.4.3 GPIO port output speed register (GPIOx_OSPEEDR) (x = A..C and H)
- 6.4.4 GPIO port pull-up/pull-down register (GPIOx_PUPDR) (x = A..C and H)
- 6.4.5 GPIO port input data register (GPIOx_IDR) (x = A..C and H)
- 6.4.6 GPIO port output data register (GPIOx_ODR) (x = A..C and H)
- 6.4.7 GPIO port bit set/reset register (GPIOx_BSRR) (x = A..C and H)
- 6.4.8 GPIO port configuration lock register (GPIOx_LCKR) (x = A..C and H)
- 6.4.9 GPIO alternate function low register (GPIOx_AFRL) (x = A..C and H)
- 6.4.10 GPIO alternate function high register (GPIOx_AFRH) (x = A..C and H)
- 6.4.11 GPIO register map
- 7 System configuration controller (SYSCFG)
- 7.1 I/O compensation cell
- 7.2 SYSCFG registers
- 7.2.1 SYSCFG memory remap register (SYSCFG_MEMRMP)
- 7.2.2 SYSCFG peripheral mode configuration register (SYSCFG_PMC)
- 7.2.3 SYSCFG external interrupt configuration register 1 (SYSCFG_EXTICR1)
- 7.2.4 SYSCFG external interrupt configuration register 2 (SYSCFG_EXTICR2)
- 7.2.5 SYSCFG external interrupt configuration register 3 (SYSCFG_EXTICR3)
- 7.2.6 SYSCFG external interrupt configuration register 4 (SYSCFG_EXTICR4)
- 7.2.7 SYSCFG configuration register 2 (SYSCFG_CFGR2)
- 7.2.8 Compensation cell control register (SYSCFG_CMPCR)
- 7.2.9 Compensation cell control register (SYSCFG_CFGR)
- 7.2.10 SYSCFG register map
- 8 Direct memory access controller (DMA)
- 8.1 DMA introduction
- 8.2 DMA main features
- 8.3 DMA functional description
- 8.3.1 General description
- 8.3.2 DMA transactions
- 8.3.3 Channel selection
- 8.3.4 Arbiter
- 8.3.5 DMA streams
- 8.3.6 Source, destination and transfer modes
- 8.3.7 Pointer incrementation
- 8.3.8 Circular mode
- 8.3.9 Double buffer mode
- 8.3.10 Programmable data width, packing/unpacking, endianness
- 8.3.11 Single and burst transfers
- 8.3.12 FIFO
- 8.3.13 DMA transfer completion
- 8.3.14 DMA transfer suspension
- 8.3.15 Flow controller
- 8.3.16 Summary of the possible DMA configurations
- 8.3.17 Stream configuration procedure
- 8.3.18 Error management
- 8.4 DMA interrupts
- 8.5 DMA registers
- 8.5.1 DMA low interrupt status register (DMA_LISR)
- 8.5.2 DMA high interrupt status register (DMA_HISR)
- 8.5.3 DMA low interrupt flag clear register (DMA_LIFCR)
- 8.5.4 DMA high interrupt flag clear register (DMA_HIFCR)
- 8.5.5 DMA stream x configuration register (DMA_SxCR) (x = 0..7)
- 8.5.6 DMA stream x number of data register (DMA_SxNDTR) (x = 0..7)
- 8.5.7 DMA stream x peripheral address register (DMA_SxPAR) (x = 0..7)
- 8.5.8 DMA stream x memory 0 address register (DMA_SxM0AR) (x = 0..7)
- 8.5.9 DMA stream x memory 1 address register (DMA_SxM1AR) (x = 0..7)
- 8.5.10 DMA stream x FIFO control register (DMA_SxFCR) (x = 0..7)
- 8.5.11 DMA register map
- 9 Interrupts and events
- 9.1 Nested vectored interrupt controller (NVIC)
- 9.2 External interrupt/event controller (EXTI)
- 9.3 EXTI registers
- 10 CRC calculation unit
- 11 Analog-to-digital converter (ADC)
- 11.1 ADC introduction
- 11.2 ADC main features
- 11.3 ADC functional description
- 11.4 Data alignment
- 11.5 Channel-wise programmable sampling time
- 11.6 Conversion on external trigger and trigger polarity
- 11.7 Fast conversion mode
- 11.8 Data management
- 11.9 Temperature sensor
- 11.10 Battery charge monitoring
- 11.11 ADC interrupts
- 11.12 ADC registers
- 11.12.1 ADC status register (ADC_SR)
- 11.12.2 ADC control register 1 (ADC_CR1)
- 11.12.3 ADC control register 2 (ADC_CR2)
- 11.12.4 ADC sample time register 1 (ADC_SMPR1)
- 11.12.5 ADC sample time register 2 (ADC_SMPR2)
- 11.12.6 ADC injected channel data offset register x (ADC_JOFRx) (x=1..4)
- 11.12.7 ADC watchdog higher threshold register (ADC_HTR)
- 11.12.8 ADC watchdog lower threshold register (ADC_LTR)
- 11.12.9 ADC regular sequence register 1 (ADC_SQR1)
- 11.12.10 ADC regular sequence register 2 (ADC_SQR2)
- 11.12.11 ADC regular sequence register 3 (ADC_SQR3)
- 11.12.12 ADC injected sequence register (ADC_JSQR)
- 11.12.13 ADC injected data register x (ADC_JDRx) (x= 1..4)
- 11.12.14 ADC regular data register (ADC_DR)
- 11.12.15 ADC Common status register (ADC_CSR)
- 11.12.16 ADC common control register (ADC_CCR)
- 11.12.17 ADC register map
- 12 Digital-to-analog converter (DAC)
- 12.1 Introduction
- 12.2 DAC main features
- 12.3 DAC output buffer enable
- 12.4 DAC channel enable
- 12.5 Single mode functional description
- 12.6 Noise generation
- 12.7 Triangle-wave generation
- 12.8 DMA request
- 12.9 DAC registers
- 12.9.1 DAC control register (DAC_CR)
- 12.9.2 DAC software trigger register (DAC_SWTRIGR)
- 12.9.3 DAC channel1 12-bit right-aligned data holding register (DAC_DHR12R1)
- 12.9.4 DAC channel1 12-bit left-aligned data holding register (DAC_DHR12L1)
- 12.9.5 DAC channel1 8-bit right-aligned data holding register (DAC_DHR8R1)
- 12.9.6 DAC channel1 data output register (DAC_DOR1)
- 12.9.7 DAC status register (DAC_SR)
- 12.9.8 DAC register map
- 13 Random number generator (RNG)
- 14 Advanced-control timers (TIM1)
- 14.1 TIM1 introduction
- 14.2 TIM1 main features
- 14.3 TIM1 functional description
- 14.3.1 Time-base unit
- 14.3.2 Counter modes
- 14.3.3 Repetition counter
- 14.3.4 Clock selection
- 14.3.5 Capture/compare channels
- 14.3.6 Input capture mode
- 14.3.7 PWM input mode
- 14.3.8 Forced output mode
- 14.3.9 Output compare mode
- 14.3.10 PWM mode
- 14.3.11 Complementary outputs and dead-time insertion
- 14.3.12 Using the break function
- 14.3.13 Clearing the OCxREF signal on an external event
- 14.3.14 6-step PWM generation
- 14.3.15 One-pulse mode
- 14.3.16 Encoder interface mode
- 14.3.17 Timer input XOR function
- 14.3.18 Interfacing with Hall sensors
- 14.3.19 TIMx and external trigger synchronization
- 14.3.20 Debug mode
- 14.4 TIM1 registers
- 14.4.1 TIM1 control register 1 (TIMx_CR1)
- 14.4.2 TIM1 control register 2 (TIMx_CR2)
- 14.4.3 TIM1 slave mode control register (TIMx_SMCR)
- 14.4.4 TIM1 DMA/interrupt enable register (TIMx_DIER)
- 14.4.5 TIM1 status register (TIMx_SR)
- 14.4.6 TIM1 event generation register (TIMx_EGR)
- 14.4.7 TIM1 capture/compare mode register 1 (TIMx_CCMR1)
- 14.4.8 TIM1 capture/compare mode register 2 (TIMx_CCMR2)
- 14.4.9 TIM1 capture/compare enable register (TIMx_CCER)
- 14.4.10 TIM1 counter (TIMx_CNT)
- 14.4.11 TIM1 prescaler (TIMx_PSC)
- 14.4.12 TIM1 auto-reload register (TIMx_ARR)
- 14.4.13 TIM1 repetition counter register (TIMx_RCR)
- 14.4.14 TIM1 capture/compare register 1 (TIMx_CCR1)
- 14.4.15 TIM1 capture/compare register 2 (TIMx_CCR2)
- 14.4.16 TIM1 capture/compare register 3 (TIMx_CCR3)
- 14.4.17 TIM1 capture/compare register 4 (TIMx_CCR4)
- 14.4.18 TIM1 break and dead-time register (TIMx_BDTR)
- 14.4.19 TIM1 DMA control register (TIMx_DCR)
- 14.4.20 TIM1 DMA address for full transfer (TIMx_DMAR)
- 14.4.21 TIM1 register map
- 15 General-purpose timers (TIM5)
- 15.1 TIM5 introduction
- 15.2 TIM5 main features
- 15.3 TIM5 functional description
- 15.3.1 Time-base unit
- 15.3.2 Counter modes
- 15.3.3 Clock selection
- 15.3.4 Capture/compare channels
- 15.3.5 Input capture mode
- 15.3.6 PWM input mode
- 15.3.7 Forced output mode
- 15.3.8 Output compare mode
- 15.3.9 PWM mode
- 15.3.10 One-pulse mode
- 15.3.11 Encoder interface mode
- 15.3.12 Timer input XOR function
- 15.3.13 Timers and external trigger synchronization
- 15.3.14 Debug mode
- 15.4 TIM5 registers
- 15.4.1 TIMx control register 1 (TIMx_CR1)
- 15.4.2 TIMx control register 2 (TIMx_CR2)
- 15.4.3 TIMx slave mode control register (TIMx_SMCR)
- 15.4.4 TIMx DMA/Interrupt enable register (TIMx_DIER)
- 15.4.5 TIMx status register (TIMx_SR)
- 15.4.6 TIMx event generation register (TIMx_EGR)
- 15.4.7 TIMx capture/compare mode register 1 (TIMx_CCMR1)
- 15.4.8 TIMx capture/compare mode register 2 (TIMx_CCMR2)
- 15.4.9 TIMx capture/compare enable register (TIMx_CCER)
- 15.4.10 TIMx counter (TIMx_CNT)
- 15.4.11 TIMx prescaler (TIMx_PSC)
- 15.4.12 TIMx auto-reload register (TIMx_ARR)
- 15.4.13 TIMx capture/compare register 1 (TIMx_CCR1)
- 15.4.14 TIMx capture/compare register 2 (TIMx_CCR2)
- 15.4.15 TIMx capture/compare register 3 (TIMx_CCR3)
- 15.4.16 TIMx capture/compare register 4 (TIMx_CCR4)
- 15.4.17 TIMx DMA control register (TIMx_DCR)
- 15.4.18 TIMx DMA address for full transfer (TIMx_DMAR)
- 15.4.19 TIM5 option register (TIM5_OR)
- 15.4.20 TIMx register map
- 16 General-purpose timers (TIM9 and TIM11)
- 16.1 TIM9 and TIM11 introduction
- 16.2 TIM9 and TIM11 main features
- 16.3 TIM9 and TIM11 functional description
- 16.3.1 Time-base unit
- 16.3.2 Counter modes
- 16.3.3 Clock selection
- 16.3.4 Capture/compare channels
- 16.3.5 Input capture mode
- 16.3.6 PWM input mode (only for TIM9)
- 16.3.7 Forced output mode
- 16.3.8 Output compare mode
- 16.3.9 PWM mode
- 16.3.10 One-pulse mode
- 16.3.11 TIM9 external trigger synchronization
- 16.3.12 Debug mode
- 16.4 TIM9 registers
- 16.4.1 TIM9 control register 1 (TIMx_CR1)
- 16.4.2 TIM9 slave mode control register (TIMx_SMCR)
- 16.4.3 TIM9 Interrupt enable register (TIMx_DIER)
- 16.4.4 TIM9 status register (TIMx_SR)
- 16.4.5 TIM9 event generation register (TIMx_EGR)
- 16.4.6 TIM9 capture/compare mode register 1 (TIMx_CCMR1)
- 16.4.7 TIM9 capture/compare enable register (TIMx_CCER)
- 16.4.8 TIM9 counter (TIMx_CNT)
- 16.4.9 TIM9 prescaler (TIMx_PSC)
- 16.4.10 TIM9 auto-reload register (TIMx_ARR)
- 16.4.11 TIM9 capture/compare register 1 (TIMx_CCR1)
- 16.4.12 TIM9 capture/compare register 2 (TIMx_CCR2)
- 16.4.13 TIM9 register map
- 16.5 TIM11 registers
- 16.5.1 TIM11 control register 1 (TIMx_CR1)
- 16.5.2 TIM11 Interrupt enable register (TIMx_DIER)
- 16.5.3 TIM11 status register (TIMx_SR)
- 16.5.4 TIM11 event generation register (TIMx_EGR)
- 16.5.5 TIM11 capture/compare mode register 1 (TIMx_CCMR1)
- 16.5.6 TIM11 capture/compare enable register (TIMx_CCER)
- 16.5.7 TIM11 counter (TIMx_CNT)
- 16.5.8 TIM11 prescaler (TIMx_PSC)
- 16.5.9 TIM11 auto-reload register (TIMx_ARR)
- 16.5.10 TIM11 capture/compare register 1 (TIMx_CCR1)
- 16.5.11 TIM11 option register 1 (TIM11_OR)
- 16.5.12 TIM11 register map
- 17 Basic timers (TIM6)
- 17.1 Introduction
- 17.2 TIM6 main features
- 17.3 TIM6 functional description
- 17.4 TIM6 registers
- 17.4.1 TIM6 control register 1 (TIMx_CR1)
- 17.4.2 TIM6 control register 2 (TIMx_CR2)
- 17.4.3 TIM6 DMA/Interrupt enable register (TIMx_DIER)
- 17.4.4 TIM6 status register (TIMx_SR)
- 17.4.5 TIM6 event generation register (TIMx_EGR)
- 17.4.6 TIM6 counter (TIMx_CNT)
- 17.4.7 TIM6 prescaler (TIMx_PSC)
- 17.4.8 TIM6 auto-reload register (TIMx_ARR)
- 17.4.9 TIM6 register map
- 18 Low-power timer (LPTIM)
- 18.1 Introduction
- 18.2 LPTIM main features
- 18.3 LPTIM implementation
- 18.4 LPTIM functional description
- 18.4.1 LPTIM block diagram
- 18.4.2 LP Timer input1 multiplexing
- 18.4.3 LPTIM reset and clocks
- 18.4.4 Glitch filter
- 18.4.5 Prescaler
- 18.4.6 Trigger multiplexer
- 18.4.7 Operating mode
- 18.4.8 Timeout function
- 18.4.9 Waveform generation
- 18.4.10 Register update
- 18.4.11 Counter mode
- 18.4.12 Timer enable
- 18.4.13 Encoder mode
- 18.5 LPTIM interrupts
- 18.6 LPTIM registers
- 18.6.1 LPTIM interrupt and status register (LPTIMx_ISR)
- 18.6.2 LPTIM interrupt clear register (LPTIMx_ICR)
- 18.6.3 LPTIM interrupt enable register (LPTIMx_IER)
- 18.6.4 LPTIM configuration register (LPTIMx_CFGR)
- 18.6.5 LPTIM control register (LPTIMx_CR)
- 18.6.6 LPTIM compare register (LPTIMx_CMP)
- 18.6.7 LPTIM autoreload register (LPTIMx_ARR)
- 18.6.8 LPTIM counter register (LPTIMx_CNT)
- 18.6.9 LPTIM1 option register (LPTIM1_OR)
- 18.6.10 LPTIM register map
- 19 Window watchdog (WWDG)
- 20 Independent watchdog (IWDG)
- 21 Real-time clock (RTC)
- 21.1 Introduction
- 21.2 RTC main features
- 21.3 RTC functional description
- 21.3.1 Clock and prescalers
- 21.3.2 Real-time clock and calendar
- 21.3.3 Programmable alarms
- 21.3.4 Periodic auto-wakeup
- 21.3.5 RTC initialization and configuration
- 21.3.6 Reading the calendar
- 21.3.7 Resetting the RTC
- 21.3.8 RTC synchronization
- 21.3.9 RTC reference clock detection
- 21.3.10 RTC coarse digital calibration
- 21.3.11 RTC smooth digital calibration
- 21.3.12 Timestamp function
- 21.3.13 Tamper detection
- 21.3.14 Calibration clock output
- 21.3.15 Alarm output
- 21.4 RTC and low power modes
- 21.5 RTC interrupts
- 21.6 RTC registers
- 21.6.1 RTC time register (RTC_TR)
- 21.6.2 RTC date register (RTC_DR)
- 21.6.3 RTC control register (RTC_CR)
- 21.6.4 RTC initialization and status register (RTC_ISR)
- 21.6.5 RTC prescaler register (RTC_PRER)
- 21.6.6 RTC wakeup timer register (RTC_WUTR)
- 21.6.7 RTC calibration register (RTC_CALIBR)
- 21.6.8 RTC alarm A register (RTC_ALRMAR)
- 21.6.9 RTC alarm B register (RTC_ALRMBR)
- 21.6.10 RTC write protection register (RTC_WPR)
- 21.6.11 RTC sub second register (RTC_SSR)
- 21.6.12 RTC shift control register (RTC_SHIFTR)
- 21.6.13 RTC time stamp time register (RTC_TSTR)
- 21.6.14 RTC time stamp date register (RTC_TSDR)
- 21.6.15 RTC timestamp sub second register (RTC_TSSSR)
- 21.6.16 RTC calibration register (RTC_CALR)
- 21.6.17 RTC tamper and alternate function configuration register (RTC_TAFCR)
- 21.6.18 RTC alarm A sub second register (RTC_ALRMASSR)
- 21.6.19 RTC alarm B sub second register (RTC_ALRMBSSR)
- 21.6.20 RTC backup registers (RTC_BKPxR)
- 21.6.21 RTC register map
- 22 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface
- 22.1 Introduction
- 22.2 FMPI2C main features
- 22.3 FMPI2C implementation
- 22.4 FMPI2C functional description
- 22.4.1 FMPI2C block diagram
- 22.4.2 FMPI2C clock requirements
- 22.4.3 Mode selection
- 22.4.4 FMPI2C initialization
- 22.4.5 Software reset
- 22.4.6 Data transfer
- 22.4.7 FMPI2C slave mode
- 22.4.8 FMPI2C master mode
- 22.4.9 FMPI2C_TIMINGR register configuration examples
- 22.4.10 SMBus specific features
- 22.4.11 SMBus initialization
- 22.4.12 SMBus: FMPI2C_TIMEOUTR register configuration examples
- 22.4.13 SMBus slave mode
- 22.4.14 Error conditions
- 22.4.15 DMA requests
- 22.4.16 Debug mode
- 22.5 FMPI2C low-power modes
- 22.6 FMPI2C interrupts
- 22.7 FMPI2C registers
- 22.7.1 Control register 1 (FMPI2C_CR1)
- 22.7.2 Control register 2 (FMPI2C_CR2)
- 22.7.3 Own address 1 register (FMPI2C_OAR1)
- 22.7.4 Own address 2 register (FMPI2C_OAR2)
- 22.7.5 Timing register (FMPI2C_TIMINGR)
- 22.7.6 Timeout register (FMPI2C_TIMEOUTR)
- 22.7.7 Interrupt and status register (FMPI2C_ISR)
- 22.7.8 Interrupt clear register (FMPI2C_ICR)
- 22.7.9 PEC register (FMPI2C_PECR)
- 22.7.10 Receive data register (FMPI2C_RXDR)
- 22.7.11 Transmit data register (FMPI2C_TXDR)
- 22.7.12 FMPI2C register map
- 23 Inter-integrated circuit (I2C) interface
- 23.1 I2C introduction
- 23.2 I2C main features
- 23.3 I2C functional description
- 23.4 I2C interrupts
- 23.5 I2C debug mode
- 23.6 I2C registers
- 23.6.1 I2C Control register 1 (I2C_CR1)
- 23.6.2 I2C Control register 2 (I2C_CR2)
- 23.6.3 I2C Own address register 1 (I2C_OAR1)
- 23.6.4 I2C Own address register 2 (I2C_OAR2)
- 23.6.5 I2C Data register (I2C_DR)
- 23.6.6 I2C Status register 1 (I2C_SR1)
- 23.6.7 I2C Status register 2 (I2C_SR2)
- 23.6.8 I2C Clock control register (I2C_CCR)
- 23.6.9 I2C TRISE register (I2C_TRISE)
- 23.6.10 I2C FLTR register (I2C_FLTR)
- 23.6.11 I2C register map
- 24 Universal synchronous asynchronous receiver transmitter (USART)
- 24.1 USART introduction
- 24.2 USART main features
- 24.3 USART implementation
- 24.4 USART functional description
- 24.4.1 USART character description
- 24.4.2 Transmitter
- 24.4.3 Receiver
- 24.4.4 Fractional baud rate generation
- How to derive USARTDIV from USART_BRR register values when OVER8=0
- How to derive USARTDIV from USART_BRR register values when OVER8=1
- Table 98. Error calculation for programmed baud rates at fPCLK = 8 MHz or fPCLK = 12 MHz, oversampling by 16
- Table 99. Error calculation for programmed baud rates at fPCLK = 8 MHz or fPCLK = 12 MHz, oversampling by 8 (continued)
- Table 100. Error calculation for programmed baud rates at fPCLK = 16 MHz or fPCLK = 24 MHz, oversampling by 16
- Table 101. Error calculation for programmed baud rates at fPCLK = 16 MHz or fPCLK = 24 MHz, oversampling by 8
- Table 102. Error calculation for programmed baud rates at fPCLK = 8 MHz or fPCLK = 16 MHz, oversampling by 16 (continued)
- Table 103. Error calculation for programmed baud rates at fPCLK = 8 MHz or fPCLK = 16 MHz, oversampling by 8
- Table 104. Error calculation for programmed baud rates at fPCLK = 30 MHz or fPCLK = 60 MHz, oversampling by 16
- Table 105. Error calculation for programmed baud rates at fPCLK = 30 MHz or fPCLK = 60 MHz, oversampling by 8 (continued)
- Table 106. Error calculation for programmed baud rates at fPCLK = 42 MHz or fPCLK = 84 Hz, oversampling by 16 (continued)
- Table 107. Error calculation for programmed baud rates at fPCLK = 42 MHz or fPCLK = 84 MHz, oversampling by 8 (continued)
- 24.4.5 USART receiver tolerance to clock deviation
- 24.4.6 Multiprocessor communication
- 24.4.7 Parity control
- 24.4.8 LIN (local interconnection network) mode
- 24.4.9 USART synchronous mode
- 24.4.10 Single-wire half-duplex communication
- 24.4.11 Smartcard
- 24.4.12 IrDA SIR ENDEC block
- 24.4.13 Continuous communication using DMA
- 24.4.14 Hardware flow control
- 24.5 USART interrupts
- 24.6 USART registers
- 25 Serial peripheral interface/ inter-IC sound (SPI/I2S)
- 25.1 Introduction
- 25.2 SPI/I2S implementation
- 25.3 SPI functional description
- 25.3.1 General description
- 25.3.2 Communications between one master and one slave
- 25.3.3 Standard multi-slave communication
- 25.3.4 Multi-master communication
- 25.3.5 Slave select (NSS) pin management
- 25.3.6 Communication formats
- 25.3.7 SPI configuration
- 25.3.8 Procedure for enabling SPI
- 25.3.9 Data transmission and reception procedures
- 25.3.10 Procedure for disabling the SPI
- 25.3.11 Communication using DMA (direct memory addressing)
- 25.3.12 SPI status flags
- 25.3.13 SPI error flags
- 25.4 SPI special features
- 25.5 SPI interrupts
- 25.6 I2S functional description
- 25.7 SPI and I2S registers
- 25.7.1 SPI control register 1 (SPI_CR1) (not used in I2S mode)
- 25.7.2 SPI control register 2 (SPI_CR2)
- 25.7.3 SPI status register (SPI_SR)
- 25.7.4 SPI data register (SPI_DR)
- 25.7.5 SPI CRC polynomial register (SPI_CRCPR) (not used in I2S mode)
- 25.7.6 SPI RX CRC register (SPI_RXCRCR) (not used in I2S mode)
- 25.7.7 SPI TX CRC register (SPI_TXCRCR) (not used in I2S mode)
- 25.7.8 SPI_I2S configuration register (SPI_I2SCFGR)
- 25.7.9 SPI_I2S prescaler register (SPI_I2SPR)
- 25.7.10 SPI register map
- 26 Debug support (DBG)
- 26.1 Overview
- 26.2 Reference ARM® documentation
- 26.3 SWJ debug port (serial wire and JTAG)
- 26.4 Pinout and debug port pins
- 26.5 JTAG TAP connection
- 26.6 ID codes and locking mechanism
- 26.7 JTAG debug port
- 26.8 SW debug port
- 26.9 AHB-AP (AHB access port) - valid for both JTAG-DP and SW-DP
- 26.10 Core debug
- 26.11 Capability of the debugger host to connect under system reset
- 26.12 FPB (Flash patch breakpoint)
- 26.13 DWT (data watchpoint trigger)
- 26.14 ITM (instrumentation trace macrocell)
- 26.15 ETM (Embedded trace macrocell)
- 26.16 MCU debug component (DBGMCU)
- 26.17 TPIU (trace port interface unit)
- 26.17.1 Introduction
- 26.17.2 TRACE pin assignment
- 26.17.3 TPUI formatter
- 26.17.4 TPUI frame synchronization packets
- 26.17.5 Transmission of the synchronization frame packet
- 26.17.6 Synchronous mode
- 26.17.7 Asynchronous mode
- 26.17.8 TRACECLKIN connection
- 26.17.9 TPIU registers
- 26.17.10 Example of configuration
- 26.18 DBG register map
- 27 Device electronic signature
- 28 Revision history