Ultra Low Power STM32L0x2 Advanced Arm® Based 32 Bit MCUs Stm32l072 Manual
User Manual:
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- 1 Documentation conventions
- 2 System and memory overview
- 3 Flash program memory and data EEPROM (FLASH)
- 3.1 Introduction
- 3.2 NVM main features
- 3.3 NVM functional description
- 3.4 Memory protection
- 3.5 NVM interrupts
- 3.6 Memory interface management
- 3.7 Flash register description
- 3.7.1 Access control register (FLASH_ACR)
- 3.7.2 Program and erase control register (FLASH_PECR)
- 3.7.3 Power-down key register (FLASH_PDKEYR)
- 3.7.4 PECR unlock key register (FLASH_PEKEYR)
- 3.7.5 Program and erase key register (FLASH_PRGKEYR)
- 3.7.6 Option bytes unlock key register (FLASH_OPTKEYR)
- 3.7.7 Status register (FLASH_SR)
- 3.7.8 Option bytes register (FLASH_OPTR)
- 3.7.9 Write protection register 1 (FLASH_WRPROT1)
- 3.7.10 Write protection register 2 (FLASH_WRPROT2)
- 3.7.11 Flash register map
- 3.8 Option bytes
- 4 Cyclic redundancy check calculation unit (CRC)
- 5 Firewall (FW)
- 5.1 Introduction
- 5.2 Firewall main features
- 5.3 Firewall functional description
- 5.4 Firewall registers
- 5.4.1 Code segment start address (FW_CSSA)
- 5.4.2 Code segment length (FW_CSL)
- 5.4.3 Non-volatile data segment start address (FW_NVDSSA)
- 5.4.4 Non-volatile data segment length (FW_NVDSL)
- 5.4.5 Volatile data segment start address (FW_VDSSA)
- 5.4.6 Volatile data segment length (FW_VDSL)
- 5.4.7 Configuration register (FW_CR)
- 5.4.8 Firewall register map
- 6 Power control (PWR)
- 6.1 Power supplies
- 6.1.1 Independent A/D and DAC converter supply and reference voltage
- 6.1.2 RTC and RTC backup registers
- 6.1.3 Voltage regulator
- 6.1.4 Dynamic voltage scaling management
- 6.1.5 Dynamic voltage scaling configuration
- 6.1.6 Voltage regulator and clock management when VDD drops below 1.71 V
- 6.1.7 Voltage regulator and clock management when modifying the VCORE range
- 6.1.8 Voltage range and limitations when VDD ranges from 1.71 V to 2.0 V
- 6.2 Power supply supervisor
- 6.3 Low-power modes
- 6.3.1 Behavior of clocks in low-power modes
- 6.3.2 Slowing down system clocks
- 6.3.3 Peripheral clock gating
- 6.3.4 Low-power run mode (LP run)
- 6.3.5 Entering low-power mode
- 6.3.6 Exiting low-power mode
- 6.3.7 Sleep mode
- 6.3.8 Low-power sleep mode (LP sleep)
- 6.3.9 Stop mode
- 6.3.10 Standby mode
- 6.3.11 Waking up the device from Stop and Standby modes using the RTC and comparators
- 6.4 Power control registers
- 6.1 Power supplies
- 7 Reset and clock control (RCC)
- 7.1 Reset
- 7.2 Clocks
- 7.2.1 HSE clock
- 7.2.2 HSI16 clock
- 7.2.3 MSI clock
- 7.2.4 HSI48 clock
- 7.2.5 PLL
- 7.2.6 LSE clock
- 7.2.7 LSI clock
- 7.2.8 System clock (SYSCLK) selection
- 7.2.9 System clock source frequency versus voltage range
- 7.2.10 HSE clock security system (CSS)
- 7.2.11 LSE Clock Security System
- 7.2.12 RTC clock
- 7.2.13 Watchdog clock
- 7.2.14 Clock-out capability
- 7.2.15 Internal/external clock measurement using TIM21
- 7.2.16 Clock-independent system clock sources for TIM2/TIM21/TIM22
- 7.3 RCC registers
- 7.3.1 Clock control register (RCC_CR)
- 7.3.2 Internal clock sources calibration register (RCC_ICSCR)
- 7.3.3 Clock recovery RC register (RCC_CRRCR)
- 7.3.4 Clock configuration register (RCC_CFGR)
- 7.3.5 Clock interrupt enable register (RCC_CIER)
- 7.3.6 Clock interrupt flag register (RCC_CIFR)
- 7.3.7 Clock interrupt clear register (RCC_CICR)
- 7.3.8 GPIO reset register (RCC_IOPRSTR)
- 7.3.9 AHB peripheral reset register (RCC_AHBRSTR)
- 7.3.10 APB2 peripheral reset register (RCC_APB2RSTR)
- 7.3.11 APB1 peripheral reset register (RCC_APB1RSTR)
- 7.3.12 GPIO clock enable register (RCC_IOPENR)
- 7.3.13 AHB peripheral clock enable register (RCC_AHBENR)
- 7.3.14 APB2 peripheral clock enable register (RCC_APB2ENR)
- 7.3.15 APB1 peripheral clock enable register (RCC_APB1ENR)
- 7.3.16 GPIO clock enable in Sleep mode register (RCC_IOPSMENR)
- 7.3.17 AHB peripheral clock enable in Sleep mode register (RCC_AHBSMENR)
- 7.3.18 APB2 peripheral clock enable in Sleep mode register (RCC_APB2SMENR)
- 7.3.19 APB1 peripheral clock enable in Sleep mode register (RCC_APB1SMENR)
- 7.3.20 Clock configuration register (RCC_CCIPR)
- 7.3.21 Control/status register (RCC_CSR)
- 7.3.22 RCC register map
- 8 Clock recovery system (CRS)
- 9 General-purpose I/Os (GPIO)
- 9.1 Introduction
- 9.2 GPIO main features
- 9.3 GPIO functional description
- 9.3.1 General-purpose I/O (GPIO)
- 9.3.2 I/O pin alternate function multiplexer and mapping
- 9.3.3 I/O port control registers
- 9.3.4 I/O port data registers
- 9.3.5 I/O data bitwise handling
- 9.3.6 GPIO locking mechanism
- 9.3.7 I/O alternate function input/output
- 9.3.8 External interrupt/wakeup lines
- 9.3.9 Input configuration
- 9.3.10 Output configuration
- 9.3.11 Alternate function configuration
- 9.3.12 Analog configuration
- 9.3.13 Using the HSE or LSE oscillator pins as GPIOs
- 9.3.14 Using the GPIO pins in the RTC supply domain
- 9.4 GPIO registers
- 9.4.1 GPIO port mode register (GPIOx_MODER) (x =A..E and H)
- 9.4.2 GPIO port output type register (GPIOx_OTYPER) (x = A..E and H)
- 9.4.3 GPIO port output speed register (GPIOx_OSPEEDR) (x = A..E and H)
- 9.4.4 GPIO port pull-up/pull-down register (GPIOx_PUPDR) (x = A..E and H)
- 9.4.5 GPIO port input data register (GPIOx_IDR) (x = A..E and H)
- 9.4.6 GPIO port output data register (GPIOx_ODR) (x = A..E and H)
- 9.4.7 GPIO port bit set/reset register (GPIOx_BSRR) (x = A..E and H)
- 9.4.8 GPIO port configuration lock register (GPIOx_LCKR) (x = A..E and H)
- 9.4.9 GPIO alternate function low register (GPIOx_AFRL) (x = A..E and H)
- 9.4.10 GPIO alternate function high register (GPIOx_AFRH) (x = A..E and H)
- 9.4.11 GPIO port bit reset register (GPIOx_BRR) (x = A..E and H)
- 9.4.12 GPIO register map
- 10 System configuration controller (SYSCFG)
- 10.1 Introduction
- 10.2 SYSCFG registers
- 10.2.1 SYSCFG memory remap register (SYSCFG_CFGR1)
- 10.2.2 SYSCFG peripheral mode configuration register (SYSCFG_CFGR2)
- 10.2.3 Reference control and status register (SYSCFG_CFGR3)
- 10.2.4 SYSCFG external interrupt configuration register 1 (SYSCFG_EXTICR1)
- 10.2.5 SYSCFG external interrupt configuration register 2 (SYSCFG_EXTICR2)
- 10.2.6 SYSCFG external interrupt configuration register 3 (SYSCFG_EXTICR3)
- 10.2.7 SYSCFG external interrupt configuration register 4 (SYSCFG_EXTICR4)
- 10.2.8 SYSCFG register map
- 11 Direct memory access controller (DMA)
- 11.1 Introduction
- 11.2 DMA main features
- 11.3 DMA functional description
- 11.4 DMA registers
- 11.4.1 DMA interrupt status register (DMA_ISR)
- 11.4.2 DMA interrupt flag clear register (DMA_IFCR)
- 11.4.3 DMA channel x configuration register (DMA_CCRx) (x = 1..7 , where x = channel number)
- 11.4.4 DMA channel x number of data register (DMA_CNDTRx) (x = 1..7, where x = channel number)
- 11.4.5 DMA channel x peripheral address register (DMA_CPARx) (x = 1..7, where x = channel number)
- 11.4.6 DMA channel x memory address register (DMA_CMARx) (x = 1..7, where x = channel number)
- 11.4.7 DMA channel selection register (DMA_CSELR)
- 11.4.8 DMA register map
- 12 Nested vectored interrupt controller (NVIC)
- 13 Extended interrupt and event controller (EXTI)
- 13.1 Introduction
- 13.2 EXTI main features
- 13.3 EXTI functional description
- 13.4 EXTI interrupt/event line mapping
- 13.5 EXTI registers
- 13.5.1 EXTI interrupt mask register (EXTI_IMR)
- 13.5.2 EXTI event mask register (EXTI_EMR)
- 13.5.3 EXTI rising edge trigger selection register (EXTI_RTSR)
- 13.5.4 Falling edge trigger selection register (EXTI_FTSR)
- 13.5.5 EXTI software interrupt event register (EXTI_SWIER)
- 13.5.6 EXTI pending register (EXTI_PR)
- 13.5.7 EXTI register map
- 14 Analog-to-digital converter (ADC)
- 14.1 Introduction
- 14.2 ADC main features
- 14.3 ADC functional description
- 14.3.1 ADC pins and internal signals
- 14.3.2 ADC voltage regulator (ADVREGEN)
- 14.3.3 Calibration (ADCAL)
- 14.3.4 ADC on-off control (ADEN, ADDIS, ADRDY)
- 14.3.5 ADC clock (CKMODE, PRESC[3:0], LFMEN)
- 14.3.6 Configuring the ADC
- 14.3.7 Channel selection (CHSEL, SCANDIR)
- 14.3.8 Programmable sampling time (SMP)
- 14.3.9 Single conversion mode (CONT=0)
- 14.3.10 Continuous conversion mode (CONT=1)
- 14.3.11 Starting conversions (ADSTART)
- 14.3.12 Timings
- 14.3.13 Stopping an ongoing conversion (ADSTP)
- 14.4 Conversion on external trigger and trigger polarity (EXTSEL, EXTEN)
- 14.5 Data management
- 14.6 Low-power features
- 14.7 Analog window watchdog (AWDEN, AWDSGL, AWDCH, ADC_TR, AWD)
- 14.8 Oversampler
- 14.9 Temperature sensor and internal reference voltage
- 14.10 ADC interrupts
- 14.11 ADC registers
- 14.11.1 ADC interrupt and status register (ADC_ISR)
- 14.11.2 ADC interrupt enable register (ADC_IER)
- 14.11.3 ADC control register (ADC_CR)
- 14.11.4 ADC configuration register 1 (ADC_CFGR1)
- 14.11.5 ADC configuration register 2 (ADC_CFGR2)
- 14.11.6 ADC sampling time register (ADC_SMPR)
- 14.11.7 ADC watchdog threshold register (ADC_TR)
- 14.11.8 ADC channel selection register (ADC_CHSELR)
- 14.11.9 ADC data register (ADC_DR)
- 14.11.10 ADC Calibration factor (ADC_CALFACT)
- 14.11.11 ADC common configuration register (ADC_CCR)
- 14.11.12 ADC register map
- 15 Digital-to-analog converter (DAC)
- 15.1 Introduction
- 15.2 DAC1 main features
- 15.3 DAC output buffer enable
- 15.4 DAC channel enable
- 15.5 Single mode functional description
- 15.6 Dual-mode functional description
- 15.7 Noise generation
- 15.8 Triangle-wave generation
- 15.9 DMA request
- 15.10 DAC registers
- 15.10.1 DAC control register (DAC_CR)
- 15.10.2 DAC software trigger register (DAC_SWTRIGR)
- 15.10.3 DAC channel1 12-bit right-aligned data holding register (DAC_DHR12R1)
- 15.10.4 DAC channel1 12-bit left-aligned data holding register (DAC_DHR12L1)
- 15.10.5 DAC channel1 8-bit right-aligned data holding register (DAC_DHR8R1)
- 15.10.6 DAC channel2 12-bit right-aligned data holding register (DAC_DHR12R2)
- 15.10.7 DAC channel2 12-bit left-aligned data holding register (DAC_DHR12L2)
- 15.10.8 DAC channel2 8-bit right-aligned data holding register (DAC_DHR8R2)
- 15.10.9 Dual DAC 12-bit right-aligned data holding register (DAC_DHR12RD)
- 15.10.10 Dual DAC 12-bit left-aligned data holding register (DAC_DHR12LD)
- 15.10.11 Dual DAC 8-bit right-aligned data holding register (DAC_DHR8RD)
- 15.10.12 DAC channel1 data output register (DAC_DOR1)
- 15.10.13 DAC channel2 data output register (DAC_DOR2)
- 15.10.14 DAC status register (DAC_SR)
- 15.10.15 DAC register map
- 16 Comparator (COMP)
- 17 Touch sensing controller (TSC)
- 17.1 Introduction
- 17.2 TSC main features
- 17.3 TSC functional description
- 17.3.1 TSC block diagram
- 17.3.2 Surface charge transfer acquisition overview
- 17.3.3 Reset and clocks
- 17.3.4 Charge transfer acquisition sequence
- 17.3.5 Spread spectrum feature
- 17.3.6 Max count error
- 17.3.7 Sampling capacitor I/O and channel I/O mode selection
- 17.3.8 Acquisition mode
- 17.3.9 I/O hysteresis and analog switch control
- 17.4 TSC low-power modes
- 17.5 TSC interrupts
- 17.6 TSC registers
- 17.6.1 TSC control register (TSC_CR)
- 17.6.2 TSC interrupt enable register (TSC_IER)
- 17.6.3 TSC interrupt clear register (TSC_ICR)
- 17.6.4 TSC interrupt status register (TSC_ISR)
- 17.6.5 TSC I/O hysteresis control register (TSC_IOHCR)
- 17.6.6 TSC I/O analog switch control register (TSC_IOASCR)
- 17.6.7 TSC I/O sampling control register (TSC_IOSCR)
- 17.6.8 TSC I/O channel control register (TSC_IOCCR)
- 17.6.9 TSC I/O group control status register (TSC_IOGCSR)
- 17.6.10 TSC I/O group x counter register (TSC_IOGxCR) (x = 1..8)
- 17.6.11 TSC register map
- 18 AES hardware accelerator (AES)
- 18.1 Introduction
- 18.2 AES main features
- 18.3 AES implementation
- 18.4 AES functional description
- 18.4.1 AES block diagram
- 18.4.2 AES internal signals
- 18.4.3 AES cryptographic core
- 18.4.4 AES procedure to perform a cipher operation
- 18.4.5 AES decryption key preparation
- 18.4.6 AES ciphertext stealing and data padding
- 18.4.7 AES task suspend and resume
- 18.4.8 AES basic chaining modes (ECB, CBC)
- 18.4.9 AES counter (CTR) mode
- 18.4.10 AES data registers and data swapping
- 18.4.11 AES key registers
- 18.4.12 AES initialization vector registers
- 18.4.13 AES DMA interface
- 18.4.14 AES error management
- 18.5 AES interrupts
- 18.6 AES processing latency
- 18.7 AES registers
- 18.7.1 AES control register (AES_CR)
- 18.7.2 AES status register (AES_SR)
- 18.7.3 AES data input register (AES_DINR)
- 18.7.4 AES data output register (AES_DOUTR)
- 18.7.5 AES key register 0 (AES_KEYR0)
- 18.7.6 AES key register 1 (AES_KEYR1)
- 18.7.7 AES key register 2 (AES_KEYR2)
- 18.7.8 AES key register 3 (AES_KEYR3)
- 18.7.9 AES initialization vector register 0 (AES_IVR0)
- 18.7.10 AES initialization vector register 1 (AES_IVR1)
- 18.7.11 AES initialization vector register 2 (AES_IVR2)
- 18.7.12 AES initialization vector register 3 (AES_IVR3)
- 18.7.13 AES register map
- 19 True random number generator (RNG)
- 20 General-purpose timers (TIM2/TIM3)
- 20.1 TIM2/TIM3 introduction
- 20.2 TIM2/TIM3 main features
- 20.3 TIM2/TIM3 functional description
- 20.3.1 Time-base unit
- 20.3.2 Counter modes
- 20.3.3 Clock selection
- 20.3.4 Capture/compare channels
- 20.3.5 Input capture mode
- 20.3.6 PWM input mode
- 20.3.7 Forced output mode
- 20.3.8 Output compare mode
- 20.3.9 PWM mode
- 20.3.10 One-pulse mode
- 20.3.11 Clearing the OCxREF signal on an external event
- 20.3.12 Encoder interface mode
- 20.3.13 Timer input XOR function
- 20.3.14 Timers and external trigger synchronization
- 20.3.15 Timer synchronization
- 20.3.16 Debug mode
- 20.4 TIM2/TIM3 registers
- 20.4.1 TIMx control register 1 (TIMx_CR1)
- 20.4.2 TIMx control register 2 (TIMx_CR2)
- 20.4.3 TIMx slave mode control register (TIMx_SMCR)
- 20.4.4 TIMx DMA/Interrupt enable register (TIMx_DIER)
- 20.4.5 TIMx status register (TIMx_SR)
- 20.4.6 TIMx event generation register (TIMx_EGR)
- 20.4.7 TIMx capture/compare mode register 1 (TIMx_CCMR1)
- 20.4.8 TIMx capture/compare mode register 2 (TIMx_CCMR2)
- 20.4.9 TIMx capture/compare enable register (TIMx_CCER)
- 20.4.10 TIMx counter (TIMx_CNT)
- 20.4.11 TIMx prescaler (TIMx_PSC)
- 20.4.12 TIMx auto-reload register (TIMx_ARR)
- 20.4.13 TIMx capture/compare register 1 (TIMx_CCR1)
- 20.4.14 TIMx capture/compare register 2 (TIMx_CCR2)
- 20.4.15 TIMx capture/compare register 3 (TIMx_CCR3)
- 20.4.16 TIMx capture/compare register 4 (TIMx_CCR4)
- 20.4.17 TIMx DMA control register (TIMx_DCR)
- 20.4.18 TIMx DMA address for full transfer (TIMx_DMAR)
- 20.4.19 TIM2 option register (TIM2_OR)
- 20.4.20 TIM3 option register (TIM3_OR)
- 20.5 TIMx register map
- 21 General-purpose timers (TIM21/22)
- 21.1 Introduction
- 21.2 TIM21/22 main features
- 21.3 TIM21/22 functional description
- 21.3.1 Timebase unit
- 21.3.2 Counter modes
- 21.3.3 Clock selection
- 21.3.4 Capture/compare channels
- 21.3.5 Input capture mode
- 21.3.6 PWM input mode
- 21.3.7 Forced output mode
- 21.3.8 Output compare mode
- 21.3.9 PWM mode
- 21.3.10 Clearing the OCxREF signal on an external event
- 21.3.11 One-pulse mode
- 21.3.12 Encoder interface mode
- 21.3.13 TIM21/22 external trigger synchronization
- 21.3.14 Timer synchronization (TIM21/22)
- 21.3.15 Debug mode
- 21.4 TIM21/22 registers
- 21.4.1 TIM21/22 control register 1 (TIMx_CR1)
- 21.4.2 TIM21/22 control register 2 (TIMx_CR2)
- 21.4.3 TIM21/22 slave mode control register (TIMx_SMCR)
- 21.4.4 TIM21/22 Interrupt enable register (TIMx_DIER)
- 21.4.5 TIM21/22 status register (TIMx_SR)
- 21.4.6 TIM21/22 event generation register (TIMx_EGR)
- 21.4.7 TIM21/22 capture/compare mode register 1 (TIMx_CCMR1)
- 21.4.8 TIM21/22 capture/compare enable register (TIMx_CCER)
- 21.4.9 TIM21/22 counter (TIMx_CNT)
- 21.4.10 TIM21/22 prescaler (TIMx_PSC)
- 21.4.11 TIM21/22 auto-reload register (TIMx_ARR)
- 21.4.12 TIM21/22 capture/compare register 1 (TIMx_CCR1)
- 21.4.13 TIM21/22 capture/compare register 2 (TIMx_CCR2)
- 21.4.14 TIM21 option register (TIM21_OR)
- 21.4.15 TIM22 option register (TIM22_OR)
- 21.4.16 TIM21/22 register map
- 22 Basic timers (TIM6/7)
- 22.1 Introduction
- 22.2 TIM6/7 main features
- 22.3 TIM6/7 functional description
- 22.4 TIM6/7 registers
- 22.4.1 TIM6/7 control register 1 (TIMx_CR1)
- 22.4.2 TIM6/7 control register 2 (TIMx_CR2)
- 22.4.3 TIM6/7 DMA/Interrupt enable register (TIMx_DIER)
- 22.4.4 TIM6/7 status register (TIMx_SR)
- 22.4.5 TIM6/7 event generation register (TIMx_EGR)
- 22.4.6 TIM6/7 counter (TIMx_CNT)
- 22.4.7 TIM6/7 prescaler (TIMx_PSC)
- 22.4.8 TIM6/7 auto-reload register (TIMx_ARR)
- 22.4.9 TIM6/7 register map
- 23 Low-power timer (LPTIM)
- 23.1 Introduction
- 23.2 LPTIM main features
- 23.3 LPTIM implementation
- 23.4 LPTIM functional description
- 23.5 LPTIM interrupts
- 23.6 LPTIM registers
- 23.6.1 LPTIM interrupt and status register (LPTIM_ISR)
- 23.6.2 LPTIM interrupt clear register (LPTIM_ICR)
- 23.6.3 LPTIM interrupt enable register (LPTIM_IER)
- 23.6.4 LPTIM configuration register (LPTIM_CFGR)
- 23.6.5 LPTIM control register (LPTIM_CR)
- 23.6.6 LPTIM compare register (LPTIM_CMP)
- 23.6.7 LPTIM autoreload register (LPTIM_ARR)
- 23.6.8 LPTIM counter register (LPTIM_CNT)
- 23.6.9 LPTIM register map
- 24 Independent watchdog (IWDG)
- 25 System window watchdog (WWDG)
- 26 Real-time clock (RTC)
- 26.1 Introduction
- 26.2 RTC main features
- 26.3 RTC implementation
- 26.4 RTC functional description
- 26.4.1 RTC block diagram
- 26.4.2 GPIOs controlled by the RTC
- 26.4.3 Clock and prescalers
- 26.4.4 Real-time clock and calendar
- 26.4.5 Programmable alarms
- 26.4.6 Periodic auto-wakeup
- 26.4.7 RTC initialization and configuration
- 26.4.8 Reading the calendar
- 26.4.9 Resetting the RTC
- 26.4.10 RTC synchronization
- 26.4.11 RTC reference clock detection
- 26.4.12 RTC smooth digital calibration
- 26.4.13 Time-stamp function
- 26.4.14 Tamper detection
- 26.4.15 Calibration clock output
- 26.4.16 Alarm output
- 26.5 RTC low-power modes
- 26.6 RTC interrupts
- 26.7 RTC registers
- 26.7.1 RTC time register (RTC_TR)
- 26.7.2 RTC date register (RTC_DR)
- 26.7.3 RTC control register (RTC_CR)
- 26.7.4 RTC initialization and status register (RTC_ISR)
- 26.7.5 RTC prescaler register (RTC_PRER)
- 26.7.6 RTC wakeup timer register (RTC_WUTR)
- 26.7.7 RTC alarm A register (RTC_ALRMAR)
- 26.7.8 RTC alarm B register (RTC_ALRMBR)
- 26.7.9 RTC write protection register (RTC_WPR)
- 26.7.10 RTC sub second register (RTC_SSR)
- 26.7.11 RTC shift control register (RTC_SHIFTR)
- 26.7.12 RTC timestamp time register (RTC_TSTR)
- 26.7.13 RTC timestamp date register (RTC_TSDR)
- 26.7.14 RTC time-stamp sub second register (RTC_TSSSR)
- 26.7.15 RTC calibration register (RTC_CALR)
- 26.7.16 RTC tamper configuration register (RTC_TAMPCR)
- 26.7.17 RTC alarm A sub second register (RTC_ALRMASSR)
- 26.7.18 RTC alarm B sub second register (RTC_ALRMBSSR)
- 26.7.19 RTC option register (RTC_OR)
- 26.7.20 RTC backup registers (RTC_BKPxR)
- 26.7.21 RTC register map
- 27 Inter-integrated circuit (I2C) interface
- 27.1 Introduction
- 27.2 I2C main features
- 27.3 I2C implementation
- 27.4 I2C functional description
- 27.4.1 I2C1/3 block diagram
- 27.4.2 I2C2 block diagram
- 27.4.3 I2C clock requirements
- 27.4.4 Mode selection
- 27.4.5 I2C initialization
- 27.4.6 Software reset
- 27.4.7 Data transfer
- 27.4.8 I2C slave mode
- 27.4.9 I2C master mode
- 27.4.10 I2C_TIMINGR register configuration examples
- 27.4.11 SMBus specific features
- 27.4.12 SMBus initialization
- 27.4.13 SMBus: I2C_TIMEOUTR register configuration examples
- 27.4.14 SMBus slave mode
- 27.4.15 Wakeup from Stop mode on address match
- 27.4.16 Error conditions
- 27.4.17 DMA requests
- 27.4.18 Debug mode
- 27.5 I2C low-power modes
- 27.6 I2C interrupts
- 27.7 I2C registers
- 27.7.1 Control register 1 (I2C_CR1)
- 27.7.2 Control register 2 (I2C_CR2)
- 27.7.3 Own address 1 register (I2C_OAR1)
- 27.7.4 Own address 2 register (I2C_OAR2)
- 27.7.5 Timing register (I2C_TIMINGR)
- 27.7.6 Timeout register (I2C_TIMEOUTR)
- 27.7.7 Interrupt and status register (I2C_ISR)
- 27.7.8 Interrupt clear register (I2C_ICR)
- 27.7.9 PEC register (I2C_PECR)
- 27.7.10 Receive data register (I2C_RXDR)
- 27.7.11 Transmit data register (I2C_TXDR)
- 27.7.12 I2C register map
- 28 Universal synchronous asynchronous receiver transmitter (USART)
- 28.1 Introduction
- 28.2 USART main features
- 28.3 USART extended features
- 28.4 USART implementation
- 28.5 USART functional description
- 28.5.1 USART character description
- 28.5.2 USART transmitter
- 28.5.3 USART receiver
- 28.5.4 USART baud rate generation
- 28.5.5 Tolerance of the USART receiver to clock deviation
- 28.5.6 USART auto baud rate detection
- 28.5.7 Multiprocessor communication using USART
- 28.5.8 Modbus communication using USART
- 28.5.9 USART parity control
- 28.5.10 USART LIN (local interconnection network) mode
- 28.5.11 USART synchronous mode
- 28.5.12 USART Single-wire Half-duplex communication
- 28.5.13 USART Smartcard mode
- 28.5.14 USART IrDA SIR ENDEC block
- 28.5.15 USART continuous communication in DMA mode
- 28.5.16 RS232 hardware flow control and RS485 driver enable using USART
- 28.5.17 Wakeup from Stop mode using USART
- 28.6 USART low-power modes
- 28.7 USART interrupts
- 28.8 USART registers
- 28.8.1 Control register 1 (USART_CR1)
- 28.8.2 Control register 2 (USART_CR2)
- 28.8.3 Control register 3 (USART_CR3)
- 28.8.4 Baud rate register (USART_BRR)
- 28.8.5 Guard time and prescaler register (USART_GTPR)
- 28.8.6 Receiver timeout register (USART_RTOR)
- 28.8.7 Request register (USART_RQR)
- 28.8.8 Interrupt and status register (USART_ISR)
- 28.8.9 Interrupt flag clear register (USART_ICR)
- 28.8.10 Receive data register (USART_RDR)
- 28.8.11 Transmit data register (USART_TDR)
- 28.8.12 USART register map
- 29 Low-power universal asynchronous receiver transmitter (LPUART)
- 29.1 Introduction
- 29.2 LPUART main features
- 29.3 LPUART implementation
- 29.4 LPUART functional description
- 29.4.1 LPUART character description
- 29.4.2 LPUART transmitter
- 29.4.3 LPUART receiver
- 29.4.4 LPUART baud rate generation
- 29.4.5 Tolerance of the LPUART receiver to clock deviation
- 29.4.6 Multiprocessor communication using LPUART
- 29.4.7 LPUART parity control
- 29.4.8 Single-wire Half-duplex communication using LPUART
- 29.4.9 Continuous communication in DMA mode using LPUART
- 29.4.10 RS232 Hardware flow control and RS485 Driver Enable using LPUART
- 29.4.11 Wakeup from Stop mode using LPUART
- 29.5 LPUART low-power mode
- 29.6 LPUART interrupts
- 29.7 LPUART registers
- 29.7.1 Control register 1 (LPUART_CR1)
- 29.7.2 Control register 2 (LPUART_CR2)
- 29.7.3 Control register 3 (LPUART_CR3)
- 29.7.4 Baud rate register (LPUART_BRR)
- 29.7.5 Request register (LPUART_RQR)
- 29.7.6 Interrupt & status register (LPUART_ISR)
- 29.7.7 Interrupt flag clear register (LPUART_ICR)
- 29.7.8 Receive data register (LPUART_RDR)
- 29.7.9 Transmit data register (LPUART_TDR)
- 29.7.10 LPUART register map
- 30 Serial peripheral interface/ inter-IC sound (SPI/I2S)
- 30.1 Introduction
- 30.2 SPI/I2S implementation
- 30.3 SPI functional description
- 30.3.1 General description
- 30.3.2 Communications between one master and one slave
- 30.3.3 Standard multi-slave communication
- 30.3.4 Multi-master communication
- 30.3.5 Slave select (NSS) pin management
- 30.3.6 Communication formats
- 30.3.7 SPI configuration
- 30.3.8 Procedure for enabling SPI
- 30.3.9 Data transmission and reception procedures
- 30.3.10 Procedure for disabling the SPI
- 30.3.11 Communication using DMA (direct memory addressing)
- 30.3.12 SPI status flags
- 30.3.13 SPI error flags
- 30.4 SPI special features
- 30.5 SPI interrupts
- 30.6 I2S functional description
- 30.7 SPI and I2S registers
- 30.7.1 SPI control register 1 (SPI_CR1) (not used in I2S mode)
- 30.7.2 SPI control register 2 (SPI_CR2)
- 30.7.3 SPI status register (SPI_SR)
- 30.7.4 SPI data register (SPI_DR)
- 30.7.5 SPI CRC polynomial register (SPI_CRCPR) (not used in I2S mode)
- 30.7.6 SPI RX CRC register (SPI_RXCRCR) (not used in I2S mode)
- 30.7.7 SPI TX CRC register (SPI_TXCRCR) (not used in I2S mode)
- 30.7.8 SPI_I2S configuration register (SPI_I2SCFGR)
- 30.7.9 SPI_I2S prescaler register (SPI_I2SPR)
- 30.7.10 SPI register map
- 31 Universal serial bus full-speed device interface (USB)
- 32 Debug support (DBG)
- 33 Device electronic signature
- Appendix A Code examples
- A.1 Introduction
- A.2 NVM/RCC Operation code example
- A.3 NVM Operation code example
- A.3.1 Unlocking the data EEPROM and FLASH_PECR register code example
- A.3.2 Locking data EEPROM and FLASH_PECR register code example
- A.3.3 Unlocking the NVM program memory code example
- A.3.4 Unlocking the option bytes area code example
- A.3.5 Write to data EEPROM code example
- A.3.6 Erase to data EEPROM code example
- A.3.7 Program Option byte code example
- A.3.8 Erase Option byte code example
- A.3.9 Program a single word to Flash program memory code example
- A.3.10 Program half-page to Flash program memory code example
- A.3.11 Erase a page in Flash program memory code example
- A.3.12 Mass erase code example
- A.4 Clock Controller
- A.5 GPIOs
- A.6 DMA
- A.7 Interrupts and event
- A.8 ADC
- A.8.1 Calibration code example
- A.8.2 ADC enable sequence code example
- A.8.3 ADC disable sequence code example
- A.8.4 ADC clock selection code example
- A.8.5 Single conversion sequence code example - Software trigger
- A.8.6 Continuous conversion sequence code example - Software trigger
- A.8.7 Single conversion sequence code example - Hardware trigger
- A.8.8 Continuous conversion sequence code example - Hardware trigger
- A.8.9 DMA one shot mode sequence code example
- A.8.10 DMA circular mode sequence code example
- A.8.11 Wait mode sequence code example
- A.8.12 Auto off and no wait mode sequence code example
- A.8.13 Auto off and wait mode sequence code example
- A.8.14 Analog watchdog code example
- A.8.15 Oversampling code example
- A.8.16 Temperature configuration code example
- A.8.17 Temperature computation code example
- A.9 DAC
- A.10 TSC code example
- A.11 Timers
- A.11.1 Upcounter on TI2 rising edge code example
- A.11.2 Up counter on each 2 ETR rising edges code example
- A.11.3 Input capture configuration code example
- A.11.4 Input capture data management code example
- A.11.5 PWM input configuration code example
- A.11.6 PWM input with DMA configuration code example
- A.11.7 Output compare configuration code example
- A.11.8 Edge-aligned PWM configuration example
- A.11.9 Center-aligned PWM configuration example
- A.11.10 ETR configuration to clear OCxREF code example
- A.11.11 Encoder interface code example
- A.11.12 Reset mode code example
- A.11.13 Gated mode code example
- A.11.14 Trigger mode code example
- A.11.15 External clock mode 2 + trigger mode code example
- A.11.16 One-Pulse mode code example
- A.11.17 Timer prescaling another timer code example
- A.11.18 Timer enabling another timer code example
- A.11.19 Master and slave synchronization code example
- A.11.20 Two timers synchronized by an external trigger code example
- A.11.21 DMA burst feature code example
- A.12 Low-power timer (LPTIM)
- A.13 IWDG code example
- A.14 WWDG code example
- A.15 RTC code example
- A.15.1 RTC calendar configuration code example
- A.15.2 RTC alarm configuration code example
- A.15.3 RTC WUT configuration code example
- A.15.4 RTC read calendar code example
- A.15.5 RTC calibration code example
- A.15.6 RTC tamper and time stamp configuration code example
- A.15.7 RTC tamper and time stamp code example
- A.15.8 RTC clock output code example
- A.16 I2C code example
- A.16.1 I2C configured in slave mode code example
- A.16.2 I2C slave transmitter code example
- A.16.3 I2C slave receiver code example
- A.16.4 I2C configured in master mode to receive code example
- A.16.5 I2C configured in master mode to transmit code example
- A.16.6 I2C master transmitter code example
- A.16.7 I2C master receiver code example
- A.16.8 I2C configured in master mode to transmit with DMA code example
- A.16.9 I2C configured in slave mode to receive with DMA code example
- A.17 USART code example
- A.17.1 USART transmitter configuration code example
- A.17.2 USART transmit byte code example
- A.17.3 USART transfer complete code example
- A.17.4 USART receiver configuration code example
- A.17.5 USART receive byte code example
- A.17.6 USART LIN mode code example
- A.17.7 USART synchronous mode code example
- A.17.8 USART single-wire half-duplex code example
- A.17.9 USART smartcard mode code example
- A.17.10 USART IrDA mode code example
- A.17.11 USART DMA code example
- A.17.12 USART hardware flow control code example
- A.18 LPUART code example
- A.19 SPI code example
- A.20 DBG code example
- Revision history