STM32L4x6 Advanced ARM® Based 32 Bit MCUs Stm32l476xx Reference Manual
STM32L476%20-%20Reference%20Manual
STM32L4x6%20-%20Reference%20Manual
User Manual:
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- 1 Documentation conventions
- 2 System and memory overview
- 3 Embedded Flash memory (FLASH)
- 3.1 Introduction
- 3.2 FLASH main features
- 3.3 FLASH functional description
- 3.3.1 Flash memory organization
- 3.3.2 Error code correction (ECC)
- 3.3.3 Read access latency
- 3.3.4 Adaptive real-time memory accelerator (ART Accelerator™)
- 3.3.5 Flash program and erase operations
- 3.3.6 Flash main memory erase sequences
- 3.3.7 Flash main memory programming sequences
- 3.3.8 Read-while-write (RWW)
- 3.4 FLASH option bytes
- 3.4.1 Option bytes description
- Table 9. Option byte format
- Table 10. Option byte organization
- User and read protection option bytes
- Bank 1 PCROP Start address option bytes
- Bank 1 PCROP End address option bytes
- Bank 1 WRP Area A address option bytes
- Bank 1 WRP Area B address option bytes
- Bank 2 PCROP Start address option bytes
- Bank 2 PCROP End address option bytes
- Bank 2 WRP Area A address option bytes
- Bank 2 WRP Area B address option bytes
- 3.4.2 Option bytes programming
- 3.4.1 Option bytes description
- 3.5 FLASH memory protection
- 3.6 FLASH interrupts
- 3.7 FLASH registers
- 3.7.1 Flash access control register (FLASH_ACR)
- 3.7.2 Flash Power-down key register (FLASH_PDKEYR)
- 3.7.3 Flash key register (FLASH_KEYR)
- 3.7.4 Flash option key register (FLASH_OPTKEYR)
- 3.7.5 Flash status register (FLASH_SR)
- 3.7.6 Flash control register (FLASH_CR)
- 3.7.7 Flash ECC register (FLASH_ECCR)
- 3.7.8 Flash option register (FLASH_OPTR)
- 3.7.9 Flash Bank 1 PCROP Start address register (FLASH_PCROP1SR)
- 3.7.10 Flash Bank 1 PCROP End address register (FLASH_PCROP1ER)
- 3.7.11 Flash Bank 1 WRP area A address register (FLASH_WRP1AR)
- 3.7.12 Flash Bank 1 WRP area B address register (FLASH_WRP1BR)
- 3.7.13 Flash Bank 2 PCROP Start address register (FLASH_PCROP2SR)
- 3.7.14 Flash Bank 2 PCROP End address register (FLASH_PCROP2ER)
- 3.7.15 Flash Bank 2 WRP area A address register (FLASH_WRP2AR)
- 3.7.16 Flash Bank 2 WRP area B address register (FLASH_WRP2BR)
- 3.7.17 FLASH register map
- 4 Firewall (FW)
- 4.1 Introduction
- 4.2 Firewall main features
- 4.3 Firewall functional description
- 4.4 Firewall registers
- 4.4.1 Code segment start address (FW_CSSA)
- 4.4.2 Code segment length (FW_CSL)
- 4.4.3 Non-volatile data segment start address (FW_NVDSSA)
- 4.4.4 Non-volatile data segment length (FW_NVDSL)
- 4.4.5 Volatile data segment start address (FW_VDSSA)
- 4.4.6 Volatile data segment length (FW_VDSL)
- 4.4.7 Configuration register (FW_CR)
- 4.4.8 Firewall register map
- 5 Power control (PWR)
- 5.1 Power supplies
- 5.2 Power supply supervisor
- 5.3 Low-power modes
- Table 19. Low-power mode summary
- Table 20. Functionalities depending on the working mode
- Debug mode
- 5.3.1 Run mode
- 5.3.2 Low-power run mode (LP run)
- 5.3.3 Low power modes
- 5.3.4 Sleep mode
- 5.3.5 Low-power sleep mode (LP sleep)
- 5.3.6 Stop 0 mode
- 5.3.7 Stop 1 mode
- 5.3.8 Stop 2 mode
- 5.3.9 Standby mode
- 5.3.10 Shutdown mode
- 5.3.11 Auto-wakeup from low-power mode
- 5.4 PWR registers
- 5.4.1 Power control register 1 (PWR_CR1)
- 5.4.2 Power control register 2 (PWR_CR2)
- 5.4.3 Power control register 3 (PWR_CR3)
- 5.4.4 Power control register 4 (PWR_CR4)
- 5.4.5 Power status register 1 (PWR_SR1)
- 5.4.6 Power status register 2 (PWR_SR2)
- 5.4.7 Power status clear register (PWR_SCR)
- 5.4.8 Power Port A pull-up control register (PWR_PUCRA)
- 5.4.9 Power Port A pull-down control register (PWR_PDCRA)
- 5.4.10 Power Port B pull-up control register (PWR_PUCRB)
- 5.4.11 Power Port B pull-down control register (PWR_PDCRB)
- 5.4.12 Power Port C pull-up control register (PWR_PUCRC)
- 5.4.13 Power Port C pull-down control register (PWR_PDCRC)
- 5.4.14 Power Port D pull-up control register (PWR_PUCRD)
- 5.4.15 Power Port D pull-down control register (PWR_PDCRD)
- 5.4.16 Power Port E pull-up control register (PWR_PUCRE)
- 5.4.17 Power Port E pull-down control register (PWR_PDCRE)
- 5.4.18 Power Port F pull-up control register (PWR_PUCRF)
- 5.4.19 Power Port F pull-down control register (PWR_PDCRF)
- 5.4.20 Power Port G pull-up control register (PWR_PUCRG)
- 5.4.21 Power Port G pull-down control register (PWR_PDCRG)
- 5.4.22 Power Port H pull-up control register (PWR_PUCRH)
- 5.4.23 Power Port H pull-down control register (PWR_PDCRH)
- 5.4.24 PWR register map and reset value table
- 6 Reset and clock control (RCC)
- 6.1 Reset
- 6.2 Clocks
- 6.2.1 HSE clock
- 6.2.2 HSI16 clock
- 6.2.3 MSI clock
- 6.2.4 PLL
- 6.2.5 LSE clock
- 6.2.6 LSI clock
- 6.2.7 System clock (SYSCLK) selection
- 6.2.8 Clock source frequency versus voltage scaling
- 6.2.9 Clock security system (CSS)
- 6.2.10 Clock security system on LSE
- 6.2.11 ADC clock
- 6.2.12 RTC clock
- 6.2.13 Timer clock
- 6.2.14 Watchdog clock
- 6.2.15 Clock-out capability
- 6.2.16 Internal/external clock measurement with TIM15/TIM16/TIM17
- 6.2.17 Peripheral clock enable register (RCC_AHBxENR, RCC_APBxENRy)
- 6.3 Low-power modes
- 6.4 RCC registers
- 6.4.1 Clock control register (RCC_CR)
- 6.4.2 Internal clock sources calibration register (RCC_ICSCR)
- 6.4.3 Clock configuration register (RCC_CFGR)
- 6.4.4 PLL configuration register (RCC_PLLCFGR)
- 6.4.5 PLLSAI1 configuration register (RCC_PLLSAI1CFGR)
- 6.4.6 PLLSAI2 configuration register (RCC_PLLSAI2CFGR)
- 6.4.7 Clock interrupt enable register (RCC_CIER)
- 6.4.8 Clock interrupt flag register (RCC_CIFR)
- 6.4.9 Clock interrupt clear register (RCC_CICR)
- 6.4.10 AHB1 peripheral reset register (RCC_AHB1RSTR)
- 6.4.11 AHB2 peripheral reset register (RCC_AHB2RSTR)
- 6.4.12 AHB3 peripheral reset register (RCC_AHB3RSTR)
- 6.4.13 APB1 peripheral reset register 1 (RCC_APB1RSTR1)
- 6.4.14 APB1 peripheral reset register 2 (RCC_APB1RSTR2)
- 6.4.15 APB2 peripheral reset register (RCC_APB2RSTR)
- 6.4.16 AHB1 peripheral clock enable register (RCC_AHB1ENR)
- 6.4.17 AHB2 peripheral clock enable register (RCC_AHB2ENR)
- 6.4.18 AHB3 peripheral clock enable register(RCC_AHB3ENR)
- 6.4.19 APB1 peripheral clock enable register 1 (RCC_APB1ENR1)
- 6.4.20 APB1 peripheral clock enable register 2 (RCC_APB1ENR2)
- 6.4.21 APB2 peripheral clock enable register (RCC_APB2ENR)
- 6.4.22 AHB1 peripheral clocks enable in Sleep and Stop modes register (RCC_AHB1SMENR)
- 6.4.23 AHB2 peripheral clocks enable in Sleep and Stop modes register (RCC_AHB2SMENR)
- 6.4.24 AHB3 peripheral clocks enable in Sleep and Stop modes register (RCC_AHB3SMENR)
- 6.4.25 APB1 peripheral clocks enable in Sleep and Stop modes register 1 (RCC_APB1SMENR1)
- 6.4.26 APB1 peripheral clocks enable in Sleep and Stop modes register 2 (RCC_APB1SMENR2)
- 6.4.27 APB2 peripheral clocks enable in Sleep and Stop modes register (RCC_APB2SMENR)
- 6.4.28 Peripherals independent clock configuration register (RCC_CCIPR)
- 6.4.29 Backup domain control register (RCC_BDCR)
- 6.4.30 Control/status register (RCC_CSR)
- 6.4.31 RCC register map
- 7 General-purpose I/Os (GPIO)
- 7.1 Introduction
- 7.2 GPIO main features
- 7.3 GPIO functional description
- Table 32. Port bit configuration table
- 7.3.1 General-purpose I/O (GPIO)
- 7.3.2 I/O pin alternate function multiplexer and mapping
- 7.3.3 I/O port control registers
- 7.3.4 I/O port data registers
- 7.3.5 I/O data bitwise handling
- 7.3.6 GPIO locking mechanism
- 7.3.7 I/O alternate function input/output
- 7.3.8 External interrupt/wakeup lines
- 7.3.9 Input configuration
- 7.3.10 Output configuration
- 7.3.11 Alternate function configuration
- 7.3.12 Analog configuration
- 7.3.13 Using the HSE or LSE oscillator pins as GPIOs
- 7.3.14 Using the GPIO pins in the RTC supply domain
- 7.4 GPIO registers
- 7.4.1 GPIO port mode register (GPIOx_MODER) (x =A..H)
- 7.4.2 GPIO port output type register (GPIOx_OTYPER) (x = A..H)
- 7.4.3 GPIO port output speed register (GPIOx_OSPEEDR) (x = A..H)
- 7.4.4 GPIO port pull-up/pull-down register (GPIOx_PUPDR) (x = A..H)
- 7.4.5 GPIO port input data register (GPIOx_IDR) (x = A..H)
- 7.4.6 GPIO port output data register (GPIOx_ODR) (x = A..H)
- 7.4.7 GPIO port bit set/reset register (GPIOx_BSRR) (x = A..H)
- 7.4.8 GPIO port configuration lock register (GPIOx_LCKR) (x = A..H)
- 7.4.9 GPIO alternate function low register (GPIOx_AFRL) (x = A..H)
- 7.4.10 GPIO alternate function high register (GPIOx_AFRH) (x = A..H)
- 7.4.11 GPIO port bit reset register (GPIOx_BRR) (x =A..H)
- 7.4.12 GPIO port analog switch control register (GPIOx_ASCR)(x = A..H)
- 7.4.13 GPIO register map
- 8 System configuration controller (SYSCFG)
- 8.1 SYSCFG main features
- 8.2 SYSCFG registers
- 8.2.1 SYSCFG memory remap register (SYSCFG_MEMRMP)
- 8.2.2 SYSCFG configuration register 1 (SYSCFG_CFGR1)
- 8.2.3 SYSCFG external interrupt configuration register 1 (SYSCFG_EXTICR1)
- 8.2.4 SYSCFG external interrupt configuration register 2 (SYSCFG_EXTICR2)
- 8.2.5 SYSCFG external interrupt configuration register 3 (SYSCFG_EXTICR3)
- 8.2.6 SYSCFG external interrupt configuration register 4 (SYSCFG_EXTICR4)
- 8.2.7 SYSCFG SRAM2 control and status register (SYSCFG_SCSR)
- 8.2.8 SYSCFG configuration register 2 (SYSCFG_CFGR2)
- 8.2.9 SYSCFG SRAM2 write protection register (SYSCFG_SWPR)
- 8.2.10 SYSCFG SRAM2 key register (SYSCFG_SKR)
- 8.2.11 SYSCFG register map
- 9 Peripherals interconnect matrix
- 9.1 Introduction
- 9.2 Connection summary
- 9.3 Interconnection details
- 9.3.1 From timer (TIM1/TIM2/TIM3/TIM4/TIM5/TIM8/TIM15/TIM16/TIM17) to timer (TIM1/TIM2/TIM3/TIM4/TIM5/TIM8/TIM15)
- 9.3.2 From timer (TIM1/TIM2/TIM3/TIM4/TIM6/TIM8/TIM15) and EXTI to ADC (ADC1/ADC2/ADC3)
- 9.3.3 From ADC (ADC1/ADC2/ADC3) to timer (TIM1/TIM8)
- 9.3.4 From timer (TIM2/TIM4/TIM5/TIM6/TIM7/TIM8) and EXTI to DAC (DAC1/DAC2)
- 9.3.5 From timer (TIM1/TIM3/TIM4/TIM6/TIM7/TIM8/TIM16) and EXTI to DFSDM
- 9.3.6 From DFSDM to timer (TIM1/TIM8/TIM15/TIM16/TIM17)
- 9.3.7 From HSE, LSE, LSI, MSI, MCO, RTC to timer (TIM2/TIM15/TIM16/TIM17)
- 9.3.8 From RTC, COMP1, COMP2 to low-power timer (LPTIM1/LPTIM2)
- 9.3.9 From timer (TIM1/TIM2/TIM3/TIM8/TIM15) to comparators (COMP1/COMP2)
- 9.3.10 From ADC (ADC1) to ADC (ADC2)
- 9.3.11 From USB to timer (TIM2)
- 9.3.12 From internal analog source to ADC (ADC1/ADC2/ADC3) and OPAMP (OPAMP1/OPAM2)
- 9.3.13 From comparators (COMP1/COMP2) to timers (TIM1/TIM2/TIM3/TIM8/TIM15/TIM16/TIM17)
- 9.3.14 From system errors to timers (TIM1/TIM8/TIM15/TIM16/TIM17)
- 9.3.15 From timers (TIM16/TIM17) to IRTIM
- 10 Direct memory access controller (DMA)
- 10.1 Introduction
- 10.2 DMA main features
- 10.3 DMA implementation
- 10.4 DMA functional description
- 10.5 DMA registers
- 10.5.1 DMA interrupt status register (DMA_ISR)
- 10.5.2 DMA interrupt flag clear register (DMA_IFCR)
- 10.5.3 DMA channel x configuration register (DMA_CCRx) (x = 1..7 , where x = channel number)
- 10.5.4 DMA channel x number of data register (DMA_CNDTRx) (x = 1..7, where x = channel number)
- 10.5.5 DMA channel x peripheral address register (DMA_CPARx) (x = 1..7, where x = channel number)
- 10.5.6 DMA channel x memory address register (DMA_CMARx) (x = 1..7, where x = channel number)
- 10.5.7 DMA1 channel selection register (DMA1_CSELR)
- 10.5.8 DMA2 channel selection register (DMA2_CSELR)
- 10.5.9 DMA register map
- 11 Nested vectored interrupt controller (NVIC)
- 12 Extended interrupts and events controller (EXTI)
- 12.1 Introduction
- 12.2 EXTI main features
- 12.3 EXTI functional description
- 12.4 EXTI interrupt/event line mapping
- 12.5 EXTI registers
- 12.5.1 Interrupt mask register 1 (EXTI_IMR1)
- 12.5.2 Event mask register 1 (EXTI_EMR1)
- 12.5.3 Rising trigger selection register 1 (EXTI_RTSR1)
- 12.5.4 Falling trigger selection register 1 (EXTI_FTSR1)
- 12.5.5 Software interrupt event register 1 (EXTI_SWIER1)
- 12.5.6 Pending register 1 (EXTI_PR1)
- 12.5.7 Interrupt mask register 2 (EXTI_IMR2)
- 12.5.8 Event mask register 2 (EXTI_EMR2)
- 12.5.9 Rising trigger selection register 2 (EXTI_RTSR2)
- 12.5.10 Falling trigger selection register 2 (EXTI_FTSR2)
- 12.5.11 Software interrupt event register 2 (EXTI_SWIER2)
- 12.5.12 Pending register 2 (EXTI_PR2)
- 12.5.13 EXTI register map
- 13 Cyclic redundancy check calculation unit (CRC)
- 14 Flexible static memory controller (FSMC)
- 14.1 FMC main features
- 14.2 Block diagram
- 14.3 AHB interface
- 14.4 External device address mapping
- 14.5 NOR Flash/PSRAM controller
- Table 50. Programmable NOR/PSRAM access parameters
- 14.5.1 External memory interface signals
- NOR Flash memory, non-multiplexed I/Os
- Table 51. Non-multiplexed I/O NOR Flash memory
- NOR Flash memory, 16-bit multiplexed I/Os
- Table 52. 16-bit multiplexed I/O NOR Flash memory
- PSRAM/SRAM, non-multiplexed I/Os
- Table 53. Non-multiplexed I/Os PSRAM/SRAM
- PSRAM, 16-bit multiplexed I/Os
- Table 54. 16-Bit multiplexed I/O PSRAM
- 14.5.2 Supported memories and transactions
- 14.5.3 General timing rules
- 14.5.4 NOR Flash/PSRAM controller asynchronous transactions
- Asynchronous static memories (NOR Flash, PSRAM, SRAM)
- Mode 1 - SRAM/PSRAM (CRAM)
- Table 56. FMC_BCRx bit fields
- Table 57. FMC_BTRx bit fields
- Mode A - SRAM/PSRAM (CRAM) OE toggling
- Table 58. FMC_BCRx bit fields
- Table 59. FMC_BTRx bit fields
- Table 60. FMC_BWTRx bit fields
- Mode 2/B - NOR Flash
- Table 61. FMC_BCRx bit fields
- Table 62. FMC_BTRx bit fields
- Table 63. FMC_BWTRx bit fields
- Mode C - NOR Flash - OE toggling
- Table 64. FMC_BCRx bit fields
- Table 65. FMC_BTRx bit fields
- Table 66. FMC_BWTRx bit fields
- Mode D - asynchronous access with extended address
- Table 67. FMC_BCRx bit fields
- Table 68. FMC_BTRx bit fields
- Table 69. FMC_BWTRx bit fields
- Muxed mode - multiplexed asynchronous access to NOR Flash memory
- Table 70. FMC_BCRx bit fields
- Table 71. FMC_BTRx bit fields
- WAIT management in asynchronous accesses
- 14.5.5 Synchronous transactions
- 14.5.6 NOR/PSRAM controller registers
- 14.6 NAND Flash controller
- Table 76. Programmable NAND Flash access parameters
- 14.6.1 External memory interface signals
- 14.6.2 NAND Flash supported memories and transactions
- 14.6.3 Timing diagrams for NAND Flash memory
- 14.6.4 NAND Flash operations
- 14.6.5 NAND Flash prewait functionality
- 14.6.6 Computation of the error correction code (ECC) in NAND Flash memory
- 14.6.7 NAND Flashcontroller registers
- 14.7 FMC register map
- 15 Quad-SPI interface (QUADSPI)
- 15.1 Introduction
- 15.2 QUADSPI main features
- 15.3 QUADSPI functional description
- 15.3.1 QUADSPI block diagram
- 15.3.2 QUADSPI Command sequence
- 15.3.3 QUADSPI signal interface protocol modes
- 15.3.4 QUADSPI indirect mode
- 15.3.5 QUADSPI status flag polling mode
- 15.3.6 QUADSPI memory-mapped mode
- 15.3.7 QUADSPI Flash memory configuration
- 15.3.8 QUADSPI delayed data sampling
- 15.3.9 QUADSPI configuration
- 15.3.10 QUADSPI usage
- 15.3.11 Sending the instruction only once
- 15.3.12 QUADSPI error management
- 15.3.13 QUADSPI busy bit and abort functionality
- 15.3.14 nCS behavior
- 15.4 QUADSPI interrupts
- 15.5 QUADSPI registers
- 15.5.1 QUADSPI control register (QUADSPI_CR)
- 15.5.2 QUADSPI device configuration register (QUADSPI_DCR)
- 15.5.3 QUADSPI status register (QUADSPI_SR)
- 15.5.4 QUADSPI flag clear register (QUADSPI_FCR)
- 15.5.5 QUADSPI data length register (QUADSPI_DLR)
- 15.5.6 QUADSPI communication configuration register (QUADSPI_CCR)
- 15.5.7 QUADSPI address register (QUADSPI_AR)
- 15.5.8 QUADSPI alternate bytes registers (QUADSPI_ABR)
- 15.5.9 QUADSPI data register (QUADSPI_DR)
- 15.5.10 QUADSPI polling status mask register (QUADSPI _PSMKR)
- 15.5.11 QUADSPI polling status match register (QUADSPI _PSMAR)
- 15.5.12 QUADSPI polling interval register (QUADSPI _PIR)
- 15.5.13 QUADSPI low-power timeout register (QUADSPI_LPTR)
- 15.5.14 QUADSPI register map
- 16 Analog-to-digital converters (ADC)
- 16.1 Introduction
- 16.2 ADC main features
- 16.3 ADC functional description
- 16.3.1 ADC block diagram
- 16.3.2 Pins and internal signals
- 16.3.3 Clocks
- 16.3.4 ADC1/2/3 connectivity
- 16.3.5 Slave AHB interface
- 16.3.6 ADC Deep-Power-Down Mode (DEEPPWD) & ADC Voltage Regulator (ADVREGEN)
- 16.3.7 Single-ended and differential input channels
- 16.3.8 Calibration (ADCAL, ADCALDIF, ADCx_CALFACT)
- 16.3.9 ADC on-off control (ADEN, ADDIS, ADRDY)
- 16.3.10 Constraints when writing the ADC control bits
- 16.3.11 Channel selection (SQRx, JSQRx)
- 16.3.12 Channel-wise programmable sampling time (SMPR1, SMPR2)
- 16.3.13 Single conversion mode (CONT=0)
- 16.3.14 Continuous conversion mode (CONT=1)
- 16.3.15 Starting conversions (ADSTART, JADSTART)
- 16.3.16 Timing
- 16.3.17 Stopping an ongoing conversion (ADSTP, JADSTP)
- 16.3.18 Conversion on external trigger and trigger polarity (EXTSEL, EXTEN, JEXTSEL, JEXTEN)
- 16.3.19 Injected channel management
- 16.3.20 Discontinuous mode (DISCEN, DISCNUM, JDISCEN)
- 16.3.21 Queue of context for injected conversions
- 16.3.22 Programmable resolution (RES) - fast conversion mode
- 16.3.23 End of conversion, end of sampling phase (EOC, JEOC, EOSMP)
- 16.3.24 End of conversion sequence (EOS, JEOS)
- 16.3.25 Timing diagrams example (single/continuous modes, hardware/software triggers)
- 16.3.26 Data management
- Data register, data alignment and offset (ADCx_DR, OFFSETy, OFFSETy_CH, ALIGN)
- Data and alignment
- Offset
- Table 91. Offset computation versus data resolution
- ADC overrun (OVR, OVRMOD)
- Managing a sequence of conversion without using the DMA
- Managing conversions without using the DMA and without overrun
- Managing conversions using the DMA
- DMA one shot mode (DMACFG=0)
- DMA circular mode (DMACFG=1)
- 16.3.27 Dynamic low-power features
- 16.3.28 Analog window watchdog (AWD1EN, JAWD1EN, AWD1SGL, AWD1CH, AWD2CH, AWD3CH, AWD_HTx, AWD_LTx, AWDx)
- 16.3.29 Oversampler
- Table 95. Maximum output results versus N and M (gray cells indicate truncation)
- Single ADC operating modes support when oversampling
- Analog watchdog
- Triggered mode
- Injected and regular sequencer management when oversampling
- Oversampling regular channels only
- Oversampling Injected channels only
- Oversampling regular and Injected channels
- Triggered regular oversampling with injected conversions
- Autoinjected mode
- Dual ADC modes support when oversampling
- Combined modes summary
- Table 96. Oversampler operating modes summary
- 16.3.30 Dual ADC modes
- Injected simultaneous mode
- Regular simultaneous mode with independent injected
- Interleaved mode with independent injected
- Alternate trigger mode
- Combined regular/injected simultaneous mode
- Combined regular simultaneous + alternate trigger mode
- Combined injected simultaneous plus interleaved
- DMA requests in dual ADC mode
- Overrun detection
- DMA one shot mode/ DMA circular mode when MDMA mode is selected
- Stopping the conversions in dual ADC modes
- 16.3.31 Temperature sensor
- 16.3.32 VBAT supply monitoring
- 16.3.33 Monitoring the internal voltage reference
- 16.4 ADC interrupts
- 16.5 ADC registers (for each ADC)
- 16.5.1 ADC interrupt and status register (ADCx_ISR)
- 16.5.2 ADC interrupt enable register (ADCx_IER)
- 16.5.3 ADC control register (ADCx_CR)
- 16.5.4 ADC configuration register (ADCx_CFGR)
- 16.5.5 ADC configuration register 2 (ADCx_CFGR2)
- 16.5.6 ADC sample time register 1 (ADCx_SMPR1)
- 16.5.7 ADC sample time register 2 (ADCx_SMPR2)
- 16.5.8 ADC watchdog threshold register 1 (ADCx_TR1)
- 16.5.9 ADC watchdog threshold register 2 (ADCx_TR2)
- 16.5.10 ADC watchdog threshold register 3 (ADCx_TR3)
- 16.5.11 ADC regular sequence register 1 (ADCx_SQR1)
- 16.5.12 ADC regular sequence register 2 (ADCx_SQR2)
- 16.5.13 ADC regular sequence register 3 (ADCx_SQR3)
- 16.5.14 ADC regular sequence register 4 (ADCx_SQR4)
- 16.5.15 ADC regular Data Register (ADCx_DR)
- 16.5.16 ADC injected sequence register (ADCx_JSQR)
- 16.5.17 ADC offset register (ADCx_OFRy) (y=1..4)
- 16.5.18 ADC injected data register (ADCx_JDRy, y= 1..4)
- 16.5.19 ADC Analog Watchdog 2 Configuration Register (ADCx_AWD2CR)
- 16.5.20 ADC Analog Watchdog 3 Configuration Register (ADCx_AWD3CR)
- 16.5.21 ADC Differential Mode Selection Register (ADCx_DIFSEL)
- 16.5.22 ADC Calibration Factors (ADCx_CALFACT)
- 16.6 ADC common registers
- 17 Digital-to-analog converter (DAC)
- 17.1 Introduction
- 17.2 DAC main features
- 17.3 DAC functional description
- 17.3.1 DAC block diagram
- 17.3.2 DAC channel enable
- 17.3.3 DAC data format
- 17.3.4 DAC conversion
- 17.3.5 DAC output voltage
- 17.3.6 DAC trigger selection
- 17.3.7 DMA request
- 17.3.8 Noise generation
- 17.3.9 Triangle-wave generation
- 17.3.10 DAC channel modes
- 17.3.11 DAC channel buffer calibration
- 17.3.12 Dual DAC channel conversion
- Independent trigger without wave generation
- Independent trigger with single LFSR generation
- Independent trigger with different LFSR generation
- Independent trigger with single triangle generation
- Independent trigger with different triangle generation
- Simultaneous software start
- Simultaneous trigger without wave generation
- Simultaneous trigger with single LFSR generation
- Simultaneous trigger with different LFSR generation
- Simultaneous trigger with single triangle generation
- 17.3.13 Simultaneous trigger with different triangle generation
- 17.4 DAC low power modes
- 17.5 DAC registers
- 17.5.1 DAC control register (DAC_CR)
- 17.5.2 DAC software trigger register (DAC_SWTRGR)
- 17.5.3 DAC channel1 12-bit right-aligned data holding register (DAC_DHR12R1)
- 17.5.4 DAC channel1 12-bit left aligned data holding register (DAC_DHR12L1)
- 17.5.5 DAC channel1 8-bit right aligned data holding register (DAC_DHR8R1)
- 17.5.6 DAC channel2 12-bit right aligned data holding register (DAC_DHR12R2)
- 17.5.7 DAC channel2 12-bit left aligned data holding register (DAC_DHR12L2)
- 17.5.8 DAC channel2 8-bit right-aligned data holding register (DAC_DHR8R2)
- 17.5.9 Dual DAC 12-bit right-aligned data holding register (DAC_DHR12RD)
- 17.5.10 DUAL DAC 12-bit left aligned data holding register (DAC_DHR12LD)
- 17.5.11 DUAL DAC 8-bit right aligned data holding register (DAC_DHR8RD)
- 17.5.12 DAC channel1 data output register (DAC_DOR1)
- 17.5.13 DAC channel2 data output register (DAC_DOR2)
- 17.5.14 DAC status register (DAC_SR)
- 17.5.15 DAC calibration control register (DAC_CCR)
- 17.5.16 DAC mode control register (DAC_MCR)
- 17.5.17 DAC Sample and Hold sample time register 1 (DAC_SHSR1)
- 17.5.18 DAC Sample and Hold sample time register 2 (DAC_SHSR2)
- 17.5.19 DAC Sample and Hold hold time register (DAC_SHHR)
- 17.5.20 DAC Sample and Hold refresh time register (DAC_SHRR)
- 17.5.21 DAC register map
- 18 Voltage reference buffer (VREFBUF)
- 19 Comparator (COMP)
- 19.1 Introduction
- 19.2 COMP main features
- 19.3 COMP functional description
- 19.4 COMP low-power modes
- 19.5 COMP interrupts
- 19.6 COMP registers
- 20 Operational amplifiers (OPAMP)
- 20.1 Introduction
- 20.2 OPAMP main features
- 20.3 OPAMP functional description
- 20.4 OPAMP low-power modes
- 20.5 OPAMP registers
- 20.5.1 OPAMP1 control/status register (OPAMP1_CSR)
- 20.5.2 OPAMP1 offset trimming register in normal mode (OPAMP1_OTR)
- 20.5.3 OPAMP1 offset trimming register in low-power mode (OPAMP1_LPOTR)
- 20.5.4 OPAMP2 control/status register (OPAMP2_CSR)
- 20.5.5 OPAMP2 offset trimming register in normal mode (OPAMP2_OTR)
- 20.5.6 OPAMP2 offset trimming register in low-power mode (OPAMP2_LPOTR)
- 20.5.7 OPAMP register map
- 21 Digital filter for sigma delta modulators (DFSDM)
- 21.1 Introduction
- 21.2 DFSDM main features
- 21.3 DFSDM functional description
- 21.3.1 DFSDM block diagram
- 21.3.2 DFSDM pins and internal signals
- 21.3.3 DFSDM reset and clocks
- 21.3.4 Serial channel transceivers
- 21.3.5 Configuring the input serial interface
- 21.3.6 Parallel data inputs
- 21.3.7 Channel selection
- 21.3.8 Digital filter configuration
- 21.3.9 Integrator unit
- 21.3.10 Analog watchdog
- 21.3.11 Short-circuit detector
- 21.3.12 Extremes detector
- 21.3.13 Data unit block
- 21.3.14 Signed data format
- 21.3.15 Launching conversions
- 21.3.16 Continuous and fast continuous modes
- 21.3.17 Request precedence
- 21.3.18 Power optimization in run mode
- 21.4 DFSDM interrupts
- 21.5 DFSDM DMA transfer
- 21.6 DFSDM channel y registers (y=0..7)
- 21.6.1 DFSDM channel configuration y register (DFSDM_CHCFGyR1) (y=0..7)
- 21.6.2 DFSDM channel configuration y register (DFSDM_CHCFGyR2) (y=0..7)
- 21.6.3 DFSDM analog watchdog and short-circuit detector register (DFSDM_AWSCDyR) (y=0..7)
- 21.6.4 DFSDM channel watchdog filter data register (DFSDM_CHWDATyR) (y=0..7)
- 21.6.5 DFSDM channel data input register (DFSDM_CHDATINyR) (y=0..7)
- 21.7 DFSDMx module registers (x=0..3)
- 21.7.1 DFSDM control register 1 (DFSDMx_CR1)
- 21.7.2 DFSDM control register 2 (DFSDMx_CR2)
- 21.7.3 DFSDM interrupt and status register (DFSDMx_ISR)
- 21.7.4 DFSDM interrupt flag clear register (DFSDMx_ICR)
- 21.7.5 DFSDM injected channel group selection register (DFSDMx_JCHGR)
- 21.7.6 DFSDM filter control register (DFSDMx_FCR)
- 21.7.7 DFSDM data register for injected group (DFSDMx_JDATAR)
- 21.7.8 DFSDM data register for the regular channel (DFSDMx_RDATAR)
- 21.7.9 DFSDM analog watchdog high threshold register (DFSDMx_AWHTR)
- 21.7.10 DFSDM analog watchdog low threshold register (DFSDMx_AWLTR)
- 21.7.11 DFSDM analog watchdog status register (DFSDMx_AWSR)
- 21.7.12 DFSDM analog watchdog clear flag register (DFSDMx_AWCFR)
- 21.7.13 DFSDM Extremes detector maximum register (DFSDMx_EXMAX)
- 21.7.14 DFSDM Extremes detector minimum register (DFSDMx_EXMIN)
- 21.7.15 DFSDM conversion timer register (DFSDMx_CNVTIMR)
- 21.8 DFSDM register map
- 22 Liquid crystal display controller (LCD)
- 22.1 Introduction
- 22.2 LCD main features
- 22.3 LCD functional description
- 22.4 LCD low-power modes
- 22.5 LCD interrupts
- 22.6 LCD registers
- 23 Touch sensing controller (TSC)
- 23.1 Introduction
- 23.2 TSC main features
- 23.3 TSC functional description
- 23.3.1 TSC block diagram
- 23.3.2 Surface charge transfer acquisition overview
- 23.3.3 Reset and clocks
- 23.3.4 Charge transfer acquisition sequence
- 23.3.5 Spread spectrum feature
- 23.3.6 Max count error
- 23.3.7 Sampling capacitor I/O and channel I/O mode selection
- 23.3.8 Acquisition mode
- 23.3.9 I/O hysteresis and analog switch control
- 23.4 TSC low-power modes
- 23.5 TSC interrupts
- 23.6 TSC registers
- 23.6.1 TSC control register (TSC_CR)
- 23.6.2 TSC interrupt enable register (TSC_IER)
- 23.6.3 TSC interrupt clear register (TSC_ICR)
- 23.6.4 TSC interrupt status register (TSC_ISR)
- 23.6.5 TSC I/O hysteresis control register (TSC_IOHCR)
- 23.6.6 TSC I/O analog switch control register (TSC_IOASCR)
- 23.6.7 TSC I/O sampling control register (TSC_IOSCR)
- 23.6.8 TSC I/O channel control register (TSC_IOCCRTSC_IOCCR)
- 23.6.9 TSC I/O group control status register (TSC_IOGCSR)
- 23.6.10 TSC I/O group x counter register (TSC_IOGxCR) (x = 1..8)
- 23.6.11 TSC register map
- 24 Random number generator (RNG)
- 25 Advanced encryption standard hardware accelerator (AES)
- 25.1 Introduction
- 25.2 AES main features
- 25.3 AES functional description
- 25.4 Encryption and derivation keys
- 25.5 AES chaining algorithms
- 25.6 Galois counter mode (GCM)
- 25.7 AES cipher message authentication code mode (CMAC)
- 25.8 Data type
- 25.9 Operating modes
- 25.10 AES DMA interface
- 25.11 Error flags
- 25.12 Processing time
- 25.13 AES interrupts
- 25.14 AES registers
- 25.14.1 AES control register (AES_CR)
- 25.14.2 AES status register (AES_SR)
- 25.14.3 AES data input register (AES_DINR)
- 25.14.4 AES data output register (AES_DOUTR)
- 25.14.5 AES key register 0 (AES_KEYR0) (LSB: key [31:0])
- 25.14.6 AES key register 1 (AES_KEYR1) (key[63:32])
- 25.14.7 AES key register 2 (AES_KEYR2) (key [95:64])
- 25.14.8 AES key register 3 (AES_KEYR3) (MSB: key[127:96])
- 25.14.9 AES initialization vector register 0 (AES_IVR0) (LSB: IVR[31:0])
- 25.14.10 AES initialization vector register 1 (AES_IVR1) (IVR[63:32])
- 25.14.11 AES initialization vector register 2 (AES_IVR2) (IVR[95:64])
- 25.14.12 AES initialization vector register 3 (AES_IVR3) (MSB: IVR[127:96])
- 25.14.13 AES key register 4 (AES_KEYR4) (key[159:128])
- 25.14.14 AES key register 5 (AES_KEYR5) (key[191:160])
- 25.14.15 AES key register 6 (AES_KEYR6) (key[223:192])
- 25.14.16 AES key register 7 (AES_KEYR7) (MSB: key[255:224])
- 25.14.17 AES Suspend registers (AES_SUSPxR) (x = 0..7)
- 25.14.18 AES register map
- 26 Advanced-control timers (TIM1/TIM8)
- 26.1 TIM1/TIM8 introduction
- 26.2 TIM1/TIM8 main features
- 26.3 TIM1/TIM8 functional description
- 26.3.1 Time-base unit
- 26.3.2 Counter modes
- 26.3.3 Repetition counter
- 26.3.4 External trigger input
- 26.3.5 Clock selection
- 26.3.6 Capture/compare channels
- 26.3.7 Input capture mode
- 26.3.8 PWM input mode
- 26.3.9 Forced output mode
- 26.3.10 Output compare mode
- 26.3.11 PWM mode
- 26.3.12 Asymmetric PWM mode
- 26.3.13 Combined PWM mode
- 26.3.14 Combined 3-phase PWM mode
- 26.3.15 Complementary outputs and dead-time insertion
- 26.3.16 Using the break function
- 26.3.17 Bidirectional break inputs
- 26.3.18 Clearing the OCxREF signal on an external event
- 26.3.19 6-step PWM generation
- 26.3.20 One-pulse mode
- 26.3.21 Retriggerable one pulse mode (OPM)
- 26.3.22 Encoder interface mode
- 26.3.23 UIF bit remapping
- 26.3.24 Timer input XOR function
- 26.3.25 Interfacing with Hall sensors
- 26.3.26 Timer synchronization
- 26.3.27 ADC synchronization
- 26.3.28 DMA burst mode
- 26.3.29 Debug mode
- 26.4 TIM1/TIM8 registers
- 26.4.1 TIM1/TIM8 control register 1 (TIMx_CR1)
- 26.4.2 TIM1/TIM8 control register 2 (TIMx_CR2)
- 26.4.3 TIM1/TIM8 slave mode control register (TIMx_SMCR)
- 26.4.4 TIM1/TIM8 DMA/interrupt enable register (TIMx_DIER)
- 26.4.5 TIM1/TIM8 status register (TIMx_SR)
- 26.4.6 TIM1/TIM8 event generation register (TIMx_EGR)
- 26.4.7 TIM1/TIM8 capture/compare mode register 1 (TIMx_CCMR1)
- 26.4.8 TIM1/TIM8 capture/compare mode register 2 (TIMx_CCMR2)
- 26.4.9 TIM1/TIM8 capture/compare enable register (TIMx_CCER)
- 26.4.10 TIM1/TIM8 counter (TIMx_CNT)
- 26.4.11 TIM1/TIM8 prescaler (TIMx_PSC)
- 26.4.12 TIM1/TIM8 auto-reload register (TIMx_ARR)
- 26.4.13 TIM1/TIM8 repetition counter register (TIMx_RCR)
- 26.4.14 TIM1/TIM8 capture/compare register 1 (TIMx_CCR1)
- 26.4.15 TIM1/TIM8 capture/compare register 2 (TIMx_CCR2)
- 26.4.16 TIM1/TIM8 capture/compare register 3 (TIMx_CCR3)
- 26.4.17 TIM1/TIM8 capture/compare register 4 (TIMx_CCR4)
- 26.4.18 TIM1/TIM8 break and dead-time register (TIMx_BDTR)
- 26.4.19 TIM1/TIM8 DMA control register (TIMx_DCR)
- 26.4.20 TIM1/TIM8 DMA address for full transfer (TIMx_DMAR)
- 26.4.21 TIM1 option register 1 (TIM1_OR1)
- 26.4.22 TIM8 option register 1 (TIM8_OR1)
- 26.4.23 TIM1/TIM8 capture/compare mode register 3 (TIMx_CCMR3)
- 26.4.24 TIM1/TIM8 capture/compare register 5 (TIMx_CCR5)
- 26.4.25 TIM1/TIM8 capture/compare register 6 (TIMx_CCR6)
- 26.4.26 TIM1 option register 2 (TIM1_OR2)
- 26.4.27 TIM1 option register 3 (TIM1_OR3)
- 26.4.28 TIM8 option register 2 (TIM8_OR2)
- 26.4.29 TIM8 option register 3 (TIM8_OR3)
- 26.4.30 TIM1 register map
- 26.4.31 TIM8 register map
- 27 General-purpose timers (TIM2/TIM3/TIM4/TIM5)
- 27.1 TIM2/TIM3/TIM4/TIM5 introduction
- 27.2 TIM2/TIM3/TIM4/TIM5 main features
- 27.3 TIM2/TIM3/TIM4/TIM5 functional description
- 27.3.1 Time-base unit
- 27.3.2 Counter modes
- 27.3.3 Clock selection
- 27.3.4 Capture/compare channels
- 27.3.5 Input capture mode
- 27.3.6 PWM input mode
- 27.3.7 Forced output mode
- 27.3.8 Output compare mode
- 27.3.9 PWM mode
- 27.3.10 Asymmetric PWM mode
- 27.3.11 Combined PWM mode
- 27.3.12 Clearing the OCxREF signal on an external event
- 27.3.13 One-pulse mode
- 27.3.14 Retriggerable one pulse mode (OPM)
- 27.3.15 Encoder interface mode
- 27.3.16 UIF bit remapping
- 27.3.17 Timer input XOR function
- 27.3.18 Timers and external trigger synchronization
- 27.3.19 Timer synchronization
- 27.3.20 DMA burst mode
- 27.3.21 Debug mode
- 27.4 TIM2/TIM3/TIM4/TIM5 registers
- 27.4.1 TIMx control register 1 (TIMx_CR1)
- 27.4.2 TIMx control register 2 (TIMx_CR2)
- 27.4.3 TIMx slave mode control register (TIMx_SMCR)
- 27.4.4 TIMx DMA/Interrupt enable register (TIMx_DIER)
- 27.4.5 TIMx status register (TIMx_SR)
- 27.4.6 TIMx event generation register (TIMx_EGR)
- 27.4.7 TIMx capture/compare mode register 1 (TIMx_CCMR1)
- 27.4.8 TIMx capture/compare mode register 2 (TIMx_CCMR2)
- 27.4.9 TIMx capture/compare enable register (TIMx_CCER)
- 27.4.10 TIMx counter (TIMx_CNT)
- 27.4.11 TIMx prescaler (TIMx_PSC)
- 27.4.12 TIMx auto-reload register (TIMx_ARR)
- 27.4.13 TIMx capture/compare register 1 (TIMx_CCR1)
- 27.4.14 TIMx capture/compare register 2 (TIMx_CCR2)
- 27.4.15 TIMx capture/compare register 3 (TIMx_CCR3)
- 27.4.16 TIMx capture/compare register 4 (TIMx_CCR4)
- 27.4.17 TIMx DMA control register (TIMx_DCR)
- 27.4.18 TIMx DMA address for full transfer (TIMx_DMAR)
- 27.4.19 TIM2 option register 1 (TIM2_OR1)
- 27.4.20 TIM3 option register 1 (TIM3_OR1)
- 27.4.21 TIM2 option register 2 (TIM2_OR2)
- 27.4.22 TIM3 option register 2 (TIM3_OR2)
- 27.4.23 TIMx register map
- 28 General-purpose timers (TIM15/16/17)
- 28.1 TIM15/16/17 introduction
- 28.2 TIM15 main features
- 28.3 TIM16 and TIM17 main features
- 28.4 TIM15/16/17 functional description
- 28.4.1 Time-base unit
- 28.4.2 Counter modes
- 28.4.3 Repetition counter
- 28.4.4 Clock selection
- 28.4.5 Capture/compare channels
- 28.4.6 Input capture mode
- 28.4.7 PWM input mode (only for TIM15)
- 28.4.8 Forced output mode
- 28.4.9 Output compare mode
- 28.4.10 PWM mode
- 28.4.11 Combined PWM mode (TIM15 only)
- 28.4.12 Complementary outputs and dead-time insertion
- 28.4.13 Using the break function
- 28.4.14 One-pulse mode
- 28.4.15 UIF bit remapping
- 28.4.16 Timer input XOR function (TIM15 only)
- 28.4.17 External trigger synchronization (TIM15 only)
- 28.4.18 Slave mode: Combined reset + trigger mode
- 28.4.19 DMA burst mode
- 28.4.20 Debug mode
- 28.5 TIM15 registers
- 28.5.1 TIM15 control register 1 (TIM15_CR1)
- 28.5.2 TIM15 control register 2 (TIM15_CR2)
- 28.5.3 TIM15 slave mode control register (TIM15_SMCR)
- 28.5.4 TIM15 DMA/interrupt enable register (TIM15_DIER)
- 28.5.5 TIM15 status register (TIM15_SR)
- 28.5.6 TIM15 event generation register (TIM15_EGR)
- 28.5.7 TIM15 capture/compare mode register 1 (TIM15_CCMR1)
- 28.5.8 TIM15 capture/compare enable register (TIM15_CCER)
- 28.5.9 TIM15 counter (TIM15_CNT)
- 28.5.10 TIM15 prescaler (TIM15_PSC)
- 28.5.11 TIM15 auto-reload register (TIM15_ARR)
- 28.5.12 TIM15 repetition counter register (TIM15_RCR)
- 28.5.13 TIM15 capture/compare register 1 (TIM15_CCR1)
- 28.5.14 TIM15 capture/compare register 2 (TIM15_CCR2)
- 28.5.15 TIM15 break and dead-time register (TIM15_BDTR)
- 28.5.16 TIM15 DMA control register (TIM15_DCR)
- 28.5.17 TIM15 DMA address for full transfer (TIM15_DMAR)
- 28.5.18 TIM15 option register 1 (TIM15_OR1)
- 28.5.19 TIM15 option register 2 (TIM15_OR2)
- 28.5.20 TIM15 register map
- 28.6 TIM16&TIM17 registers
- 28.6.1 TIM16&TIM17 control register 1 (TIMx_CR1)
- 28.6.2 TIM16&TIM17 control register 2 (TIMx_CR2)
- 28.6.3 TIM16&TIM17 DMA/interrupt enable register (TIMx_DIER)
- 28.6.4 TIM16&TIM17 status register (TIMx_SR)
- 28.6.5 TIM16&TIM17 event generation register (TIMx_EGR)
- 28.6.6 TIM16&TIM17 capture/compare mode register 1 (TIMx_CCMR1)
- 28.6.7 TIM16&TIM17 capture/compare enable register (TIMx_CCER)
- 28.6.8 TIM16&TIM17 counter (TIMx_CNT)
- 28.6.9 TIM16&TIM17 prescaler (TIMx_PSC)
- 28.6.10 TIM16&TIM17 auto-reload register (TIMx_ARR)
- 28.6.11 TIM16&TIM17 repetition counter register (TIMx_RCR)
- 28.6.12 TIM16&TIM17 capture/compare register 1 (TIMx_CCR1)
- 28.6.13 TIM16&TIM17 break and dead-time register (TIMx_BDTR)
- 28.6.14 TIM16&TIM17 DMA control register (TIMx_DCR)
- 28.6.15 TIM16&TIM17 DMA address for full transfer (TIMx_DMAR)
- 28.6.16 TIM16 option register 1 (TIM16_OR1)
- 28.6.17 TIM16 option register 2 (TIM16_OR2)
- 28.6.18 TIM17 option register 1 (TIM17_OR1)
- 28.6.19 TIM17 option register 2 (TIM17_OR2)
- 28.6.20 TIM16&TIM17 register map
- 29 Basic timers (TIM6/TIM7)
- 29.1 TIM6/TIM7 introduction
- 29.2 TIM6/TIM7 main features
- 29.3 TIM6/TIM7 functional description
- 29.4 TIM6/TIM7 registers
- 29.4.1 TIM6/TIM7 control register 1 (TIMx_CR1)
- 29.4.2 TIM6/TIM7 control register 2 (TIMx_CR2)
- 29.4.3 TIM6/TIM7 DMA/Interrupt enable register (TIMx_DIER)
- 29.4.4 TIM6/TIM7 status register (TIMx_SR)
- 29.4.5 TIM6/TIM7 event generation register (TIMx_EGR)
- 29.4.6 TIM6/TIM7 counter (TIMx_CNT)
- 29.4.7 TIM6/TIM7 prescaler (TIMx_PSC)
- 29.4.8 TIM6/TIM7 auto-reload register (TIMx_ARR)
- 29.4.9 TIM6/TIM7 register map
- 30 Low-power timer (LPTIM)
- 30.1 Introduction
- 30.2 LPTIM main features
- 30.3 LPTIM implementation
- 30.4 LPTIM functional description
- 30.5 LPTIM low power modes
- 30.6 LPTIM interrupts
- 30.7 LPTIM registers
- 30.7.1 LPTIM interrupt and status register (LPTIMx_ISR)
- 30.7.2 LPTIM interrupt clear register (LPTIMx_ICR)
- 30.7.3 LPTIM interrupt enable register (LPTIMx_IER)
- 30.7.4 LPTIM configuration register (LPTIMx_CFGR)
- 30.7.5 LPTIM control register (LPTIMx_CR)
- 30.7.6 LPTIM compare register (LPTIMx_CMP)
- 30.7.7 LPTIM autoreload register (LPTIMx_ARR)
- 30.7.8 LPTIM counter register (LPTIMx_CNT)
- 30.7.9 LPTIM1 option register (LPTIM1_OR)
- 30.7.10 LPTIM2 option register (LPTIM2_OR)
- 30.7.11 LPTIM register map
- 31 Infrared interface (IRTIM)
- 32 Independent watchdog (IWDG)
- 33 System window watchdog (WWDG)
- 34 Real-time clock (RTC)
- 34.1 Introduction
- 34.2 RTC main features
- 34.3 RTC functional description
- 34.3.1 RTC block diagram
- 34.3.2 GPIOs controlled by the RTC
- 34.3.3 Clock and prescalers
- 34.3.4 Real-time clock and calendar
- 34.3.5 Programmable alarms
- 34.3.6 Periodic auto-wakeup
- 34.3.7 RTC initialization and configuration
- 34.3.8 Reading the calendar
- 34.3.9 Resetting the RTC
- 34.3.10 RTC synchronization
- 34.3.11 RTC reference clock detection
- 34.3.12 RTC smooth digital calibration
- 34.3.13 Time-stamp function
- 34.3.14 Tamper detection
- 34.3.15 Calibration clock output
- 34.3.16 Alarm output
- 34.4 RTC low-power modes
- 34.5 RTC interrupts
- 34.6 RTC registers
- 34.6.1 RTC time register (RTC_TR)
- 34.6.2 RTC date register (RTC_DR)
- 34.6.3 RTC control register (RTC_CR)
- 34.6.4 RTC initialization and status register (RTC_ISR)
- 34.6.5 RTC prescaler register (RTC_PRER)
- 34.6.6 RTC wakeup timer register (RTC_WUTR)
- 34.6.7 RTC alarm A register (RTC_ALRMAR)
- 34.6.8 RTC alarm B register (RTC_ALRMBR)
- 34.6.9 RTC write protection register (RTC_WPR)
- 34.6.10 RTC sub second register (RTC_SSR)
- 34.6.11 RTC shift control register (RTC_SHIFTR)
- 34.6.12 RTC timestamp time register (RTC_TSTR)
- 34.6.13 RTC timestamp date register (RTC_TSDR)
- 34.6.14 RTC time-stamp sub second register (RTC_TSSSR)
- 34.6.15 RTC calibration register (RTC_CALR)
- 34.6.16 RTC tamper configuration register (RTC_TAMPCR)
- 34.6.17 RTC alarm A sub second register (RTC_ALRMASSR)
- 34.6.18 RTC alarm B sub second register (RTC_ALRMBSSR)
- 34.6.19 RTC option register (RTC_OR)
- 34.6.20 RTC backup registers (RTC_BKPxR)
- 34.6.21 RTC register map
- 35 Inter-integrated circuit (I2C) interface
- 35.1 Introduction
- 35.2 I2C main features
- 35.3 I2C implementation
- 35.4 I2C functional description
- 35.4.1 I2C block diagram
- 35.4.2 I2C clock requirements
- 35.4.3 Mode selection
- 35.4.4 I2C initialization
- 35.4.5 Software reset
- 35.4.6 Data transfer
- 35.4.7 I2C slave mode
- 35.4.8 I2C master mode
- 35.4.9 I2C_TIMINGR register configuration examples
- 35.4.10 SMBus specific features
- 35.4.11 SMBus initialization
- 35.4.12 SMBus: I2C_TIMEOUTR register configuration examples
- 35.4.13 SMBus slave mode
- 35.4.14 Wakeup from Stop mode on address match
- 35.4.15 Error conditions
- 35.4.16 DMA requests
- 35.4.17 Debug mode
- 35.5 I2C low-power modes
- 35.6 I2C interrupts
- 35.7 I2C registers
- 35.7.1 Control register 1 (I2C_CR1)
- 35.7.2 Control register 2 (I2C_CR2)
- 35.7.3 Own address 1 register (I2C_OAR1)
- 35.7.4 Own address 2 register (I2C_OAR2)
- 35.7.5 Timing register (I2C_TIMINGR)
- 35.7.6 Timeout register (I2C_TIMEOUTR)
- 35.7.7 Interrupt and status register (I2C_ISR)
- 35.7.8 Interrupt clear register (I2C_ICR)
- 35.7.9 PEC register (I2C_PECR)
- 35.7.10 Receive data register (I2C_RXDR)
- 35.7.11 Transmit data register (I2C_TXDR)
- 35.7.12 I2C register map
- 36 Universal synchronous asynchronous receiver transmitter (USART)
- 36.1 Introduction
- 36.2 USART main features
- 36.3 USART extended features
- 36.4 USART implementation
- 36.5 USART functional description
- 36.5.1 USART character description
- 36.5.2 USART transmitter
- 36.5.3 USART receiver
- 36.5.4 USART baud rate generation
- 36.5.5 Tolerance of the USART receiver to clock deviation
- 36.5.6 USART auto baud rate detection
- 36.5.7 Multiprocessor communication using USART
- 36.5.8 Modbus communication using USART
- 36.5.9 USART parity control
- 36.5.10 USART LIN (local interconnection network) mode
- 36.5.11 USART synchronous mode
- 36.5.12 USART single-wire half-duplex communication
- 36.5.13 USART smartcard mode
- 36.5.14 USART IrDA SIR ENDEC block
- 36.5.15 USART continuous communication in DMA mode
- 36.5.16 RS232 hardware flow control and RS485 driver enable using USART
- 36.5.17 Wakeup from Stop mode using USART
- 36.6 USART low-power modes
- 36.7 USART interrupts
- 36.8 USART registers
- 36.8.1 Control register 1 (USARTx_CR1)
- 36.8.2 Control register 2 (USARTx_CR2)
- 36.8.3 Control register 3 (USARTx_CR3)
- 36.8.4 Baud rate register (USARTx_BRR)
- 36.8.5 Guard time and prescaler register (USARTx_GTPR)
- 36.8.6 Receiver timeout register (USARTx_RTOR)
- 36.8.7 Request register (USARTx_RQR)
- 36.8.8 Interrupt and status register (USARTx_ISR)
- 36.8.9 Interrupt flag clear register (USARTx_ICR)
- 36.8.10 Receive data register (USARTx_RDR)
- 36.8.11 Transmit data register (USARTx_TDR)
- 36.8.12 USART register map
- 37 Low-power universal asynchronous receiver transmitter (LPUART)
- 37.1 Introduction
- 37.2 LPUART main features
- 37.3 LPUART implementation
- 37.4 LPUART functional description
- 37.4.1 LPUART character description
- 37.4.2 LPUART transmitter
- 37.4.3 LPUART receiver
- 37.4.4 LPUART baud rate generation
- 37.4.5 Multiprocessor communication using LPUART
- 37.4.6 LPUART parity control
- 37.4.7 Single-wire half-duplex communication using LPUART
- 37.4.8 Continuous communication in DMA mode using LPUART
- 37.4.9 RS232 Hardware flow control and RS485 Driver Enable using LPUART
- 37.4.10 Wakeup from Stop mode using LPUART
- 37.5 LPUART low-power mode
- 37.6 LPUART interrupts
- 37.7 LPUART registers
- 37.7.1 Control register 1 (LPUART_CR1)
- 37.7.2 Control register 2 (LPUART_CR2)
- 37.7.3 Control register 3 (LPUART_CR3)
- 37.7.4 Baud rate register (LPUART_BRR)
- 37.7.5 Request register (LPUART_RQR)
- 37.7.6 Interrupt & status register (LPUART_ISR)
- 37.7.7 Interrupt flag clear register (LPUART_ICR)
- 37.7.8 Receive data register (LPUART_RDR)
- 37.7.9 Transmit data register (LPUART_TDR)
- 37.7.10 LPUART register map
- 38 Serial peripheral interface (SPI)
- 38.1 Introduction
- 38.2 SPI main features
- 38.3 SPI implementation
- 38.4 SPI functional description
- 38.4.1 General description
- 38.4.2 Communications between one master and one slave
- 38.4.3 Standard multi-slave communication
- 38.4.4 Multi-master communication
- 38.4.5 Slave select (NSS) pin management
- 38.4.6 Communication formats
- 38.4.7 Configuration of SPI
- 38.4.8 Procedure for enabling SPI
- 38.4.9 Data transmission and reception procedures
- 38.4.10 SPI status flags
- 38.4.11 SPI error flags
- 38.4.12 NSS pulse mode
- 38.4.13 TI mode
- 38.4.14 CRC calculation
- 38.5 SPI interrupts
- 38.6 SPI registers
- 38.6.1 SPI control register 1 (SPIx_CR1)
- 38.6.2 SPI control register 2 (SPIx_CR2)
- 38.6.3 SPI status register (SPIx_SR)
- 38.6.4 SPI data register (SPIx_DR)
- 38.6.5 SPI CRC polynomial register (SPIx_CRCPR)
- 38.6.6 SPI Rx CRC register (SPIx_RXCRCR)
- 38.6.7 SPI Tx CRC register (SPIx_TXCRCR)
- 38.6.8 SPI register map
- 39 Serial audio interface (SAI)
- 39.1 Introduction
- 39.2 SAI main features
- 39.3 SAI functional description
- 39.3.1 SAI block diagram
- 39.3.2 Main SAI modes
- 39.3.3 SAI synchronization mode
- 39.3.4 Audio data size
- 39.3.5 Frame synchronization
- 39.3.6 Slot configuration
- 39.3.7 SAI clock generator
- 39.3.8 Internal FIFOs
- 39.3.9 AC’97 link controller
- 39.3.10 SPDIF output
- 39.3.11 Specific features
- 39.3.12 Error flags
- 39.3.13 Disabling the SAI
- 39.3.14 SAI DMA interface
- 39.4 SAI interrupts
- 39.5 SAI registers
- 39.5.1 Global configuration register (SAI_GCR)
- 39.5.2 Configuration register 1 (SAI_ACR1 / SAI_BCR1)
- 39.5.3 Configuration register 2 (SAI_ACR2 / SAI_BCR2)
- 39.5.4 Frame configuration register (SAI_AFRCR / SAI_BFRCR)
- 39.5.5 Slot register (SAI_ASLOTR / SAI_BSLOTR)
- 39.5.6 Interrupt mask register 2 (SAI_AIM / SAI_BIM)
- 39.5.7 Status register (SAI_ASR / SAI_BSR)
- 39.5.8 Clear flag register (SAI_ACLRFR / SAI_BCLRFR)
- 39.5.9 Data register (SAI_ADR / SAI_BDR)
- 39.5.10 SAI register map
- 40 Single Wire Protocol Master Interface (SWPMI)
- 40.1 Introduction
- 40.2 SWPMI main features
- 40.3 SWPMI functional description
- 40.4 SWPMI low-power modes
- 40.5 SWPMI interrupts
- 40.6 SWPMI registers
- 40.6.1 SWPMI Configuration/Control register (SWPMI_CR)
- 40.6.2 SWPMI Bitrate register (SWPMI_BRR)
- 40.6.3 SWPMI Interrupt and Status register (SWPMI_ISR)
- 40.6.4 SWPMI Interrupt Flag Clear register (SWPMI_ICR)
- 40.6.5 SWPMI Interrupt Enable register (SMPMI_IER)
- 40.6.6 SWPMI Receive Frame Length register (SWPMI_RFL)
- 40.6.7 SWPMI Transmit data register (SWPMI_TDR)
- 40.6.8 SWPMI Receive data register (SWPMI_RDR)
- 40.6.9 SWPMI Option register (SWPMI_OR)
- 40.6.10 SWPMI register map and reset value table
- 41 SD/SDIO/MMC card host interface (SDMMC)
- 41.1 SDMMC main features
- 41.2 SDMMC bus topology
- 41.3 SDMMC functional description
- Table 219. SDMMC I/O definitions
- 41.3.1 SDMMC adapter
- Adapter register block
- Control unit
- Command path
- Table 220. Command format
- Table 221. Short response format
- Table 222. Long response format
- Table 223. Command path status flags
- Data path
- Table 224. Data token format
- DPSM Flags
- Table 225. DPSM flags
- Data FIFO
- Table 226. Transmit FIFO status flags
- Table 227. Receive FIFO status flags
- 41.3.2 SDMMC APB2 interface
- 41.4 Card functional description
- 41.4.1 Card identification mode
- 41.4.2 Card reset
- 41.4.3 Operating voltage range validation
- 41.4.4 Card identification process
- 41.4.5 Block write
- 41.4.6 Block read
- 41.4.7 Stream access, stream write and stream read (MultiMediaCard only)
- 41.4.8 Erase: group erase and sector erase
- 41.4.9 Wide bus selection or deselection
- 41.4.10 Protection management
- 41.4.11 Card status register
- 41.4.12 SD status register
- Table 229. SD status
- SIZE_OF_PROTECTED_AREA
- SPEED_CLASS
- Table 230. Speed class code field
- PERFORMANCE_MOVE
- Table 231. Performance move field
- AU_SIZE
- Table 232. AU_SIZE field
- Table 233. Maximum AU size
- ERASE_SIZE
- Table 234. Erase size field
- ERASE_TIMEOUT
- Table 235. Erase timeout field
- ERASE_OFFSET
- Table 236. Erase offset field
- 41.4.13 SD I/O mode
- 41.4.14 Commands and responses
- Application-specific and general commands
- Command types
- Command formats
- Commands for the MultiMediaCard/SD module
- Table 237. Block-oriented write commands
- Table 238. Block-oriented write protection commands
- Table 239. Erase commands
- Table 240. I/O mode commands
- Table 241. Lock card
- Table 242. Application-specific commands
- 41.5 Response formats
- 41.6 SDIO I/O card-specific operations
- 41.7 HW flow control
- 41.8 SDMMC registers
- 41.8.1 SDMMC power control register (SDMMC_POWER)
- 41.8.2 SDMMC clock control register (SDMMC_CLKCR)
- 41.8.3 SDMMC argument register (SDMMC_ARG)
- 41.8.4 SDMMC command register (SDMMC_CMD)
- 41.8.5 SDMMC command response register (SDMMC_RESPCMD)
- 41.8.6 SDMMC response 1..4 register (SDMMC_RESPx)
- 41.8.7 SDMMC data timer register (SDMMC_DTIMER)
- 41.8.8 SDMMC data length register (SDMMC_DLEN)
- 41.8.9 SDMMC data control register (SDMMC_DCTRL)
- 41.8.10 SDMMC data counter register (SDMMC_DCOUNT)
- 41.8.11 SDMMC status register (SDMMC_STA)
- 41.8.12 SDMMC interrupt clear register (SDMMC_ICR)
- 41.8.13 SDMMC mask register (SDMMC_MASK)
- 41.8.14 SDMMC FIFO counter register (SDMMC_FIFOCNT)
- 41.8.15 SDMMC data FIFO register (SDMMC_FIFO)
- 41.8.16 SDMMC register map
- 42 Controller area network (bxCAN)
- 42.1 Introduction
- 42.2 bxCAN main features
- 42.3 bxCAN general description
- 42.4 bxCAN operating modes
- 42.5 Test mode
- 42.6 Behavior in Debug mode
- 42.7 bxCAN functional description
- 42.8 bxCAN interrupts
- 42.9 CAN registers
- 42.9.1 Register access protection
- 42.9.2 CAN control and status registers
- 42.9.3 CAN mailbox registers
- CAN TX mailbox identifier register (CAN_TIxR) (x = 0..2)
- CAN mailbox data length control and time stamp register (CAN_TDTxR) (x = 0..2)
- CAN mailbox data low register (CAN_TDLxR) (x = 0..2)
- CAN mailbox data high register (CAN_TDHxR) (x = 0..2)
- CAN receive FIFO mailbox identifier register (CAN_RIxR) (x = 0..1)
- CAN receive FIFO mailbox data length control and time stamp register (CAN_RDTxR) (x = 0..1)
- CAN receive FIFO mailbox data low register (CAN_RDLxR) (x = 0..1)
- CAN receive FIFO mailbox data high register (CAN_RDHxR) (x = 0..1)
- 42.9.4 CAN filter registers
- 42.9.5 bxCAN register map
- 43 USB on-the-go full-speed (OTG_FS)
- 43.1 Introduction
- 43.2 USB_OTG main features
- 43.3 USB_OTG Implementation
- 43.4 USB OTG functional description
- 43.5 OTG dual role device (DRD)
- 43.6 USB peripheral
- 43.7 USB host
- 43.8 SOF trigger
- 43.9 Power options
- 43.10 Dynamic update of the OTG_HFIR register
- 43.11 USB data FIFOs
- 43.12 OTG_FS system performance
- 43.13 OTG_FS interrupts
- 43.14 OTG_FS control and status registers
- 43.14.1 CSR memory map
- Global CSR map
- Table 256. Core global control and status registers (CSRs)
- Host-mode CSR map
- Table 257. Host-mode control and status registers (CSRs)
- Device-mode CSR map
- Table 258. Device-mode control and status registers
- Data FIFO (DFIFO) access register map
- Table 259. Data FIFO (DFIFO) access register map
- Power and clock gating CSR map
- Table 260. Power and clock gating control and status registers
- 43.14.1 CSR memory map
- 43.15 OTG_FS registers
- 43.15.1 OTG control and status register (OTG_GOTGCTL)
- 43.15.2 OTG interrupt register (OTG_GOTGINT)
- 43.15.3 OTG AHB configuration register (OTG_GAHBCFG)
- 43.15.4 OTG USB configuration register (OTG_GUSBCFG)
- 43.15.5 OTG reset register (OTG_GRSTCTL)
- 43.15.6 OTG core interrupt register (OTG_GINTSTS)
- 43.15.7 OTG interrupt mask register (OTG_GINTMSK)
- 43.15.8 OTG_FS Receive status debug read/OTG status read and pop registers (OTG_GRXSTSR/OTG_GRXSTSP)
- 43.15.9 OTG Receive FIFO size register (OTG_GRXFSIZ)
- 43.15.10 OTG Host non-periodic transmit FIFO size register (OTG_HNPTXFSIZ)/Endpoint 0 Transmit FIFO size (OTG_DIEPTXF0)
- 43.15.11 OTG non-periodic transmit FIFO/queue status register (OTG_HNPTXSTS)
- 43.15.12 OTG general core configuration register (OTG_GCCFG)
- 43.15.13 OTG core ID register (OTG_CID)
- 43.15.14 OTG core LPM configuration register (OTG_GLPMCFG)
- 43.15.15 OTG power down register (OTG_GPWRDN)
- 43.15.16 OTG ADP timer, control and status register (OTG_GADPCTL)
- 43.15.17 OTG Host periodic transmit FIFO size register (OTG_HPTXFSIZ)
- 43.15.18 OTG device IN endpoint transmit FIFO size register (OTG_DIEPTXFx) (x = 1..5 , where x is the FIFO_number)
- 43.15.19 Host-mode registers
- 43.15.20 OTG Host configuration register (OTG_HCFG)
- 43.15.21 OTG Host frame interval register (OTG_HFIR)
- 43.15.22 OTG Host frame number/frame time remaining register (OTG_HFNUM)
- 43.15.23 OTG_Host periodic transmit FIFO/queue status register (OTG_HPTXSTS)
- 43.15.24 OTG Host all channels interrupt register (OTG_HAINT)
- 43.15.25 OTG Host all channels interrupt mask register (OTG_HAINTMSK)
- 43.15.26 OTG Host port control and status register (OTG_HPRT)
- 43.15.27 OTG Host channel-x characteristics register (OTG_HCCHARx) (x = 0..11, where x = Channel_number)
- 43.15.28 OTG Host channel-x interrupt register (OTG_HCINTx) (x = 0..11, where x = Channel_number)
- 43.15.29 OTG Host channel-x interrupt mask register (OTG_HCINTMSKx) (x = 0..11, where x = Channel_number)
- 43.15.30 OTG Host channel-x transfer size register (OTG_HCTSIZx) (x = 0..11, where x = Channel_number)
- 43.15.31 Device-mode registers
- 43.15.32 OTG device configuration register (OTG_DCFG)
- 43.15.33 OTG device control register (OTG_DCTL)
- 43.15.34 OTG device status register (OTG_DSTS)
- 43.15.35 OTG device IN endpoint common interrupt mask register (OTG_DIEPMSK)
- 43.15.36 OTG device OUT endpoint common interrupt mask register (OTG_DOEPMSK)
- 43.15.37 OTG device all endpoints interrupt register (OTG_DAINT)
- 43.15.38 OTG all endpoints interrupt mask register (OTG_DAINTMSK)
- 43.15.39 OTG device VBUS discharge time register (OTG_DVBUSDIS)
- 43.15.40 OTG device VBUS pulsing time register (OTG_DVBUSPULSE)
- 43.15.41 OTG device IN endpoint FIFO empty interrupt mask register (OTG_DIEPEMPMSK)
- 43.15.42 OTG device control IN endpoint 0 control register (OTG_DIEPCTL0)
- 43.15.43 OTG device endpoint-x control register (OTG_DIEPCTLx) (x = 1..5 , where x = Endpoint_number)
- 43.15.44 OTG device control OUT endpoint 0 control register (OTG_DOEPCTL0)
- 43.15.45 OTG device endpoint-x control register (OTG_DOEPCTLx) (x = 1..5 , where x = Endpoint_number)
- 43.15.46 OTG device endpoint-x interrupt register (OTG_DIEPINTx) (x = 0..5 , where x = Endpoint_number)
- 43.15.47 OTG device endpoint-x interrupt register (OTG_DOEPINTx) (x = 0..5 , where x = Endpoint_number)
- 43.15.48 OTG device IN endpoint 0 transfer size register (OTG_DIEPTSIZ0)
- 43.15.49 OTG device OUT endpoint 0 transfer size register (OTG_DOEPTSIZ0)
- 43.15.50 OTG device IN endpoint-x transfer size register (OTG_DIEPTSIZx) (x = 1..5 , where x= Endpoint_number)
- 43.15.51 OTG device IN endpoint transmit FIFO status register (OTG_DTXFSTSx) (x = 0..5 , where x = Endpoint_number)
- 43.15.52 OTG device OUT endpoint-x transfer size register (OTG_DOEPTSIZx) (x = 1..5 , where x = Endpoint_number)
- 43.15.53 OTG power and clock gating control register (OTG_PCGCCTL)
- 43.15.54 OTG_FS register map
- 43.16 OTG_FS programming model
- 44 Debug support (DBG)
- 44.1 Overview
- 44.2 Reference ARM® documentation
- 44.3 SWJ debug port (serial wire and JTAG)
- 44.4 Pinout and debug port pins
- 44.5 STM32L4x6 JTAG TAP connection
- 44.6 ID codes and locking mechanism
- 44.7 JTAG debug port
- 44.8 SW debug port
- 44.9 AHB-AP (AHB access port) - valid for both JTAG-DP and SW-DP
- 44.10 Core debug
- 44.11 Capability of the debugger host to connect under system reset
- 44.12 FPB (Flash patch breakpoint)
- 44.13 DWT (data watchpoint trigger)
- 44.14 ITM (instrumentation trace macrocell)
- 44.15 ETM (Embedded trace macrocell)
- 44.16 MCU debug component (DBGMCU)
- 44.16.1 Debug support for low-power modes
- 44.16.2 Debug support for timers, RTC, watchdog, bxCAN and I2C
- 44.16.3 Debug MCU configuration register (DBGMCU_CR)
- 44.16.4 Debug MCU APB1 freeze register1(DBGMCU_APB1FZR1)
- 44.16.5 Debug MCU APB1 freeze register 2 (DBGMCU_APB1FZR2)
- 44.16.6 Debug MCU APB2 freeze register (DBGMCU_APB2FZR)
- 44.17 TPIU (trace port interface unit)
- 44.17.1 Introduction
- 44.17.2 TRACE pin assignment
- 44.17.3 TPUI formatter
- 44.17.4 TPUI frame synchronization packets
- 44.17.5 Transmission of the synchronization frame packet
- 44.17.6 Synchronous mode
- 44.17.7 Asynchronous mode
- 44.17.8 TRACECLKIN connection inside the STM32L4x6
- 44.17.9 TPIU registers
- 44.17.10 Example of configuration
- 44.18 DBG register map
- 45 Device electronic signature
- 46 Revision history