Systemverilog For Verification A Guide To Learning The Bench Language Features
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- 001Download PDF (417.5 KB)front-matter
- 002Download PDF (859.0 KB)fulltext
- Chapter 1: Verification Guidelines
- 1.1 The Verification Process
- 1.2 The Verification Methodology Manual
- 1.3 Basic Testbench Functionality
- 1.4 Directed Testing
- 1.5 Methodology Basics
- 1.6 Constrained-Random Stimulus
- 1.7 What Should You Randomize?
- 1.8 Functional Coverage
- 1.9 Testbench Components
- 1.10 Layered Testbench
- 1.11 Building a Layered Testbench
- 1.12 Simulation Environment Phases
- 1.13 Maximum Code Reuse
- 1.14 Testbench Performance
- 1.15 Conclusion
- 1.16 Exercises
- Chapter 1: Verification Guidelines
- 003Download PDF (1.2 MB)fulltext
- Chapter 2: Data Types
- 2.1 Built-In Data Types
- 2.2 Fixed-Size Arrays
- 2.2.1 Declaring and initializing fixed-size arrays
- 2.2.2 The Array Literal
- 2.2.3 Basic array operations — for and foreach
- 2.2.4 Basic array operations – copy and compare
- 2.2.5 Bit and Array Subscripts, Together at last
- 2.2.6 Packed arrays
- 2.2.7 Packed Array Examples
- 2.2.8 Choosing between packed and unpacked arrays
- 2.3 Dynamic Arrays
- 2.4 Queues
- 2.5 Associative Arrays
- 2.6 Array Methods
- 2.7 Choosing a Storage Type
- 2.8 Creating New Types with typedef
- 2.9 Creating User-Defined Structures
- 2.10 Packages
- 2.11 Type Conversion
- 2.12 Streaming operators
- 2.13 Enumerated Types
- 2.14 Constants
- 2.15 Strings
- 2.16 Expression Width
- 2.17 Conclusion
- 2.18 Exercises
- Chapter 2: Data Types
- 004Download PDF (526.4 KB)fulltext
- 005Download PDF (1.2 MB)fulltext
- Chapter 4: Connecting the Testbench and Design
- 4.1 Separating the Testbench and Design
- 4.2 The Interface Construct
- 4.2.1 Using an interface to simplify connections
- 4.2.2 Connecting interfaces and ports
- 4.2.3 Grouping signals in an interface using modports
- 4.2.4 Using modports with a bus design
- 4.2.5 Creating an interface monitor
- 4.2.6 Interface trade-offs
- 4.2.7 More information and examples
- 4.2.8 Logic vs. wire in an interface
- 4.3 Stimulus Timing
- 4.4 Interface Driving and Sampling
- 4.5 Program Block Considerations
- 4.6 Connecting It All Together
- 4.7 Top-Level Scope
- 4.8 Program–Module Interactions
- 4.9 SystemVerilog Assertions
- 4.10 The Four-Port ATM Router
- 4.11 The Ref Port Direction
- 4.12 Conclusion
- 4.13 Exercises
- Chapter 4: Connecting the Testbench and Design
- 006Download PDF (1.2 MB)fulltext
- Chapter 5: Basic OOP
- 5.1 Introduction
- 5.2 Think of Nouns, not Verbs
- 5.3 Your First Class
- 5.4 Where to Define a Class
- 5.5 OOP Terminology
- 5.6 Creating New Objects
- 5.7 Object Deallocation
- 5.8 Using Objects
- 5.9 Class Methods
- 5.10 Defining Methods Outside of the Class
- 5.11 Static Variables vs. Global Variables
- 5.12 Scoping Rules
- 5.13 Using One Class Inside Another
- 5.14 Understanding Dynamic Objects
- 5.15 Copying Objects
- 5.16 Public vs. Local
- 5.17 Straying Off Course
- 5.18 Building a Testbench
- 5.19 Conclusion
- 5.20 Exercises
- Chapter 5: Basic OOP
- 007Download PDF (1.5 MB)fulltext
- Chapter 6: Randomization
- 6.1 Introduction
- 6.2 What to Randomize
- 6.3 Randomization in SystemVerilog
- 6.4 Constraint Details
- 6.5 Solution Probabilities
- 6.6 Controlling Multiple Constraint Blocks
- 6.7 Valid Constraints
- 6.8 In-line Constraints
- 6.9 The pre_randomize and post_randomize Functions
- 6.10 Random Number Functions
- 6.11 Constraints Tips and Techniques
- 6.11.1 Constraints with Variables
- 6.11.2 Using Nonrandom Values
- 6.11.3 Checking Values Using Constraints
- 6.11.4 Randomizing Individual Variables
- 6.11.5 Turn Constraints Off and On
- 6.11.6 Specifying a Constraint in a Test Using In-Line Constraints
- 6.11.7 Specifying a Constraint in a Test with External Constraints
- 6.11.8 Extending a Class
- 6.12 Common Randomization Problems
- 6.13 Iterative and Array Constraints
- 6.14 Atomic Stimulus Generation vs. Scenario Generation
- 6.15 Random Control
- 6.16 Random Number Generators
- 6.17 Random Device Configuration
- 6.18 Conclusion
- 6.19 Exercises
- Chapter 6: Randomization
- 008Download PDF (1.4 MB)fulltext
- Chapter 7: Threads and Interprocess Communication
- 7.1 Working with Threads
- 7.2 Disabling Threads
- 7.3 Interprocess Communication
- 7.4 Events
- 7.5 Semaphores
- 7.6 Mailboxes
- 7.6.1 Mailbox in a Testbench
- 7.6.2 Bounded Mailboxes
- 7.6.3 Unsynchronized Threads Communicating with a Mailbox
- 7.6.4 Synchronized Threads Using a Bounded Mailbox and a Peek
- 7.6.5 Synchronized Threads Using a Mailbox and Event
- 7.6.6 Synchronized Threads Using Two Mailboxes
- 7.6.7 Other Synchronization Techniques
- 7.7 Building a Testbench with Threads and IPC
- 7.8 Conclusion
- 7.9 Exercises
- Chapter 7: Threads and Interprocess Communication
- 009Download PDF (1.5 MB)fulltext
- Chapter 8: Advanced OOP and Testbench Guidelines
- 8.1 Introduction to Inheritance
- 8.2 Blueprint Pattern
- 8.3 Downcasting and Virtual Methods
- 8.4 Composition, Inheritance, and Alternatives
- 8.5 Copying an Object
- 8.6 Abstract Classes and Pure Virtual Methods
- 8.7 Callbacks
- 8.8 Parameterized Classes
- 8.9 Static and Singleton Classes
- 8.10 Creating a Test Registry
- 8.11 Conclusion
- 8.12 Exercises
- Chapter 8: Advanced OOP and Testbench Guidelines
- 010Download PDF (986.5 KB)fulltext
- Chapter 9: Functional Coverage
- 9.1 Gathering Coverage Data
- 9.2 Coverage Types
- 9.3 Functional Coverage Strategies
- 9.4 Simple Functional Coverage Example
- 9.5 Anatomy of a Cover Group
- 9.6 Triggering a Cover Group
- 9.7 Data Sampling
- 9.7.1 Individual Bins and Total Coverage
- 9.7.2 Creating Bins Automatically
- 9.7.3 Limiting the Number of Automatic Bins Created
- 9.7.4 Sampling Expressions
- 9.7.5 User-Defined Bins Find a Bug
- 9.7.6 Naming the Cover Point Bins
- 9.7.7 Conditional Coverage
- 9.7.8 Creating Bins for Enumerated Types
- 9.7.9 Transition Coverage
- 9.7.10 Wildcard States and Transitions
- 9.7.11 Ignoring Values
- 9.7.12 Illegal Bins
- 9.7.13 State Machine Coverage
- 9.8 Cross Coverage
- 9.9 Generic Cover Groups
- 9.10 Coverage Options
- 9.11 Analyzing Coverage Data
- 9.12 Measuring Coverage Statistics During Simulation
- 9.13 Conclusion
- 9.14 Exercises
- Chapter 9: Functional Coverage
- 011Download PDF (824.0 KB)fulltext
- 012Download PDF (1.2 MB)fulltext
- 013Download PDF (917.4 KB)fulltext
- Chapter 12: Interfacing with C/C++
- 014Download PDF (94.5 KB)back-matter