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TPS51640A, TPS59640, TPS59641
SLUSAQ2 – JANUARY 2012
www.ti.com
Dual-Channel (3-Phase CPU/1-Phase GPU) SVID, D-CAP+™ Step-Down Controller for
IMVP-7 VCORE with Two Integrated Drivers
FEATURES
1
•
•
•
•
•
2
•
•
•
•
•
•
•
•
•
•
•
•
Intel IMVP-7 Serial VID (SVID) Compliant
Supports CPU and GPU Outputs
CPU Channel 1, 2, or 3 Phase
Single-Phase GPU Channel
Full IMVP-7 Mobile Feature Set Including
Digital Current Monitor
8-Bit DAC with 0.250-V to 1.52-V Output Range
Optimized Efficiency at Light and Heavy Loads
VCORE Overshoot Reduction (OSR)
VCORE Undershoot Reduction (USR)
Accurate, Adjustable Voltage Positioning
8 Independent Frequency Selections per
Channel (CPU/GPU)
Patent Pending AutoBalance™ Phase
Balancing
Selectable 8-Level Current Limit
3-V to 28-V Conversion Voltage Range
Two Integrated Fast FET Drivers w/Integrated
Boost FET
Internal Driver Bypass Mode for Use with
DrMOS Devices
Small 6 × 6 , 48-Pin, QFN, PowerPAD™
Package
DESCRIPTION
The TPS51640A, TPS59640 and TPS59641 are
dual-channel, fully SVID compliant IMVP-7 step-down
controllers with two integrated gate drivers. Advanced
control features such as D-CAP™+ architecture with
overlapping pulse support (undershoot reduction,
USR) and overshoot reduction (OSR) provide fast
transient response, lowest output capacitance and
high efficiency. All of these controllers also support
single-phase operation for light loads. The full
compliment of IMVP-7 I/O is integrated into the
controllers including dual PGOOD signals, ALERT
and VR_HOT. Adjustable control of VCORE slew rate
and voltage positioning round out the IMVP-7
features. In addition, the controllers' CPU channel
includes two high-current FET gate drivers to drive
high-side and low-side N-channel FETs with
exceptionally high speed and low switching loss. The
TPS51601 or TPS51601A driver is used for the third
phase of the CPU and the GPU channel.
The BOOT voltage (VBOOT) on the TPS51640A and
TPS59640 is 0 V. The TPS59641 is specifically
designed for a VBOOT level of 1.1 V.
These controllers are packaged in a space saving,
thermally enhanced 48-pin QFN. The TPS51640A is
rated to operate from –10°C to 105°C. The
TPS59640 and TPS59641 are rated to operate
from –40°C to 105°C.
APPLICATIONS
•
IMVP-7 VCORE Applications for Adapter,
Battery, NVDC or 3 V/5 V/12 V rails
SIMPLIFIED APPLICATION
3-phase CPU
Controller
Processor
IMVP-7
SVID Interface
Internal
FET Driver
TPS51601
FET Driver
CPU Power Stage
VCC_CPU
TPS51601
FET Driver
GPU Power Stage
VCC_GFX
Internal
FET Driver
1-phase GPU
Controller
TPS51640
UDG-11062
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
D-CAP+, PowerPAD, D-CAP are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2012, Texas Instruments Incorporated
TPS51640A, TPS59640, TPS59641
SLUSAQ2 – JANUARY 2012
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION (1) (2)
TA
VBOOT
(V)
PACKAGE
–10°C to 105°C
ORDERABLE
NUMBER
0
Plastic Quad Flat
Pack (QFN)
(1)
(2)
(3)
MINIMUM
QUANTITY
TPS51640ARSLT
250
2500
TPS59640RSLR
–40°C to 105°C
TRANSPORT
MEDIA
TPS51640ARSLR
TPS59640RSLT
0
1.1
PINS
48
Tape-and-reel
TPS59641RSLT (3)
TPS59641RSLTR
ECO PLAN
250
Green (RoHS and
no Sb/Br)
2500
250
(3)
2500
For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
Product preview. Not currently available.
ABSOLUTE MAXIMUM RATINGS (1) (2)
over operating free-air temperature range (unless otherwise noted)
MIN
Input voltage
Output voltage
Electrotatic discharge
TYP MAX UNIT
VBAT
–0.3
CSW1, CSW2
–6.0
32
CDH1 to CSW1; CDH2 to CSW2; CBST1 to CSW1; CBST2 to CSW2
–0.3
6.0
CTHERM, CCOMP, CF-IMAX, GF-IMAX, GCOMP, GTHERM,
V5DRV, V5
–0.3
6.0
COCP-I, CCSP1, CCSP2, CCSP3, CCSN1, CCSN2, CCSN3, CVFB,
CGFB, V3R3, VR_ON, VCLK, VDIO, SLEWA, GGFB, GVFB, GCSN,
GCSP, GOCP-I,
–0.3
3.6
PGND
–0.3
0.3
VREF
–0.3
1.8
CPGOOD, ALERT, VR_HOT, GPGOOD, CIMON, GIMON
–0.3
3.6
CPWM3, CSKIP, GPWM, GSKIP, CDL1, CDL2
–0.3
6.0
32
V
V
V
(HBM) QSS 009-105 (JESD22-A114A)
1.5
kV
(CDM) QSS 009-147 (JESD22-C101B.01)
500
V
Operating junction temperature, TJ
-40
125
°C
Storage temperature, Tstg
-55
150
°C
(1)
(2)
2
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to the network ground terminal unless otherwise noted.
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Copyright © 2012, Texas Instruments Incorporated
TPS51640A, TPS59640, TPS59641
SLUSAQ2 – JANUARY 2012
www.ti.com
THERMAL INFORMATION
TPS51640A
TPS59640
TPS59641
THERMAL METRIC (1)
UNITS
RSL
48 PINS
θJA
Junction-to-ambient thermal resistance
31.7
θJCtop
Junction-to-case (top) thermal resistance
19.8
θJB
Junction-to-board thermal resistance
7.1
ψJT
Junction-to-top characterization parameter
0.3
ψJB
Junction-to-board characterization parameter
7.1
θJCbot
Junction-to-case (bottom) thermal resistance
2.1
(1)
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
RECOMMENDED OPERATING CONDITIONS
MIN
Input voltage
Output voltage
TYP
MAX
VBAT
–0.1
28
CSW1, CSW2
–3.0
30
CDH1 to CSW1; CDH2 to CSW2; CBST1 to CSW1; CBST2 to
CSW2
–0.1
5.5
V5DRV, V5
4.5
5.5
V3R3
3.1
3.5
–0.1
2.5
CTHERM, GTHERM
0.1
3.6
CF-IMAX, GF-IMAX, COCP-I, GOCP-I
0.1
1.7
CCSP1, CCSP2, CCSP3, CCSN1, CCSN2, CCSN3, CVFB, CGFB,
GGFB, GVFB, GCSN, GCSP,
–0.1
1.7
VR_ON, VCLK, VDIO, SLEWA,
–0.1
3.5
PGND
–0.1
0.1
VREF
–0.1
1.72
CIMON, GIMON
–0.1
VVREF
CPGOOD, ALERT, VR_HOT, GPGOOD,
–0.1
VV3R3
CCOMP, GCOMP
–0.1
VV5
TPS51460A
–10
105
TPS59640,TPS59641
–40
105
CPWM3, CSKIP, GPWM, GSKIP, CDL1, CDL2,
Operating free air temperature, TA
Copyright © 2012, Texas Instruments Incorporated
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UNIT
V
V
°C
3
TPS51640A, TPS59640, TPS59641
SLUSAQ2 – JANUARY 2012
www.ti.com
ELECTRICAL CHARACTERISTICS
over recommended free-air temperature range, VV5 = VV5DRV = 5.0 V; VV3R3 = 3.3 V; VxGFB = VPGND = VGND, VxVFB = VCORE
(Unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
9.0
UNIT
SUPPLY: CURRENTS, UVLO AND POWER-ON RESET
IV5-4
V5 supply current CPU: 3-phase IV5+ IV5DRV , VVDAC < VxVFB < (VVDAC + 100 mV),
active GPU: 1-phase active
VR_ON = ‘HI’
6.0
IV5-3
V5 supply current CPU: 2-phase IV5+ IV5DRV, VVDAC < VxVFB < (VVDAC + 100 mV),
active GPU: 1-phase active
VR_ON = ‘HI’, VCCSP3=3.3 V
5.5
mA
IV5-2
V5 supply current CPU: 1-phase IV5+ IV5DRV, VVDAC < VxVFB < (VVDAC + 100 mV),
active GPU: 1-phase active
VR_ON = ‘HI’, VCCSP3 = VCCSP2= 3.3 V
4.9
mA
IV5-PS3
IV5+ IV5DRV, VVDAC < VxVFB < (VVDAC + 100 mV),
V5 supply current CPU: 3-phase
VR_ON = ‘HI’, SetPS = PS3
active GPU: 1-phase active
(Note: 3-phase CPU goes to 1-phase in PS3)
5.1
mA
IV5STBY
V5DRV standby current
VR_ON = ‘LO’, IV5 + IV5DRV
10
20
µA
VUVLOH
V5 UVLO 'OK' Threshold
Ramp up, VR_ON=’HI’,
4.25
4.4
4.5
V
VUVLOL
V5 UVLO fault threshold
Ramp down, VR_ON = ’HI’,
3.95
4.2
4.3
V
IV3R3
V3R3 supply current
SVID bus idle, VR_ON = ‘HI’
0.5
1.0
mA
IV3R3SBY
V3R3 standby current
VR_ON = ‘LO’
10
µA
V3UVLOH
V3R3 UVLO 'OK' threshold
Ramp up, VR_ON=’HI’,
2.5
2.9
3.0
V
V3UVLOL
V3R3 UVLO fault threshold
Ramp down, VR_ON = ’HI’,
2.4
2.7
2.8
V
mA
REFERENCES: DAC, VREF, VBOOT AND DRVL DISCHARGE FOR BOTH CPU AND GPU
VBOOT
Boot voltage
VVIDSTP
TPS59640
TPS51640A
0
TPS59641
1.1
VID step size
5
0.25 ≤ VxVFB ≤ 0.995V,
IxPU_CORE = 0 A, 0°C ≤ TA ≤ 85°C
VDAC1
xVFB tolerance no load active
0.25 ≤ VxVFB ≤ 0.995V,
IxPU_CORE = 0 A,
–40°C ≤ TA ≤ 105°C
1.000V ≤ VxVFB ≤ 1.520 V,
IxPU_CORE = 0 A, 0°C ≤ TA ≤ 85°C
VDAC4
xVFB tolerance above 1 V VID
V
1.000V ≤ VxVFB ≤ 1.520 V,
IxPU_CORE = 0 A,
–40°C ≤ TA ≤ 105°C
mV
TPS51640A
–5
5
TPS59640
TPS59641
–6
8.3
TPS51640A
–0.5%
0.5%
TPS59640
TPS59641
–0.65%
1.0%
mV
VVREF
VREF Output
4.5 V ≤ VV5 ≤ 5.5 V, IVREF= 0 A
VVREFSRC
VREF output source
0 µA ≤ IVREF ≤ 500 µA
VVREFSNK
VREF output sink
–500 µA ≤ IVREF ≤ 0 µA
0.1
4
mV
VDLDQ
DRVL discharge threshold
Soft-stop transistor turns on at this point.
200
300
mV
20
40
µA
–4
1.70
V
–0.1
mV
VOLTAGE SENSE: xVFB AND xGFB FOR BOTH CPU AND GPU
IxVFB
xVFB input bias current
VxVFB=2 V, VxGFB=0 V
IxGFB
xGFB input bias current
VxVFB=2 V, VxGFB=0 V
AGAINGND
xGFB/GND gain
-40
-20
µA
1
V/V
35
mV
CURRENT MONITOR
VCiMONLK
Zero level current output
Σ∆CS = 0 mV, AIMON = 12 × (1+1.27)
VCIMONLO
Low level current output
Σ∆CS = 15.6 mV, AIMON = 12 × (1+1.27)
425
mV
VCIMONMID
Mid level current output
Σ∆CS = 31.1 mV, AIMON = 12 × (1+1.27)
850
mV
VCIMONHI
High level current output
Σ∆CS = 62.3 mV, AIMON = 12 × (1+1.27)
1700
mV
0
mV
ZERO-CROSSING
VZx
4
Inductor zero crossing threshold
voltage
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Copyright © 2012, Texas Instruments Incorporated
TPS51640A, TPS59640, TPS59641
SLUSAQ2 – JANUARY 2012
www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
over recommended free-air temperature range, VV5 = VV5DRV = 5.0 V; VV3R3 = 3.3 V; VxGFB = VPGND = VGND, VxVFB = VCORE
(Unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
CURRENT SENSE: OVERCURRENT, ZERO CROSSING, VOLTAGE POSITIONING AND PHASE BALANCING
RxOCP-I = 20 kΩ
RxOCP-I = 24 kΩ
RxOCP-I = 30 kΩ
RxOCP-I = 39 kΩ
VOCPP
OCP voltage (valley current
limit)
RxOCP-I = 56 kΩ
RxOCP-I = 75 kΩ
RxOCP-I = 100 kΩ
RxOCP-I = 150 kΩ
TPS51640A
5.1
7.0
9.7
TPS59640
TPS59641
4.6
7.0
9.7
TPS51640A
8.1
10.0
12.6
TPS59640
TPS59641
7.6
10.0
13.1
TPS51640A
12.1
14.0
16.7
TPS59640
TPS59641
11.6
14.0
17.2
TPS51640A
17.1
19.0
21.7
TPS59640
TPS59641
16.6
19.0
22.2
TPS51640A
23.1
25.0
27.9
TPS59640
TPS59641
22.6
25.0
28.4
TPS51640A
29.7
32.0
35.0
TPS59640
TPS59641
29.2
32.0
35.5
TPS51640A
37.9
40.0
43.3
TPS59640
TPS59641
37.4
40.0
43.8
TPS51640A
46.8
49.0
52.6
TPS59640
TPS59641
46.2
49.0
53.1
VIMAX_MIN = 133 mV, value of xIMAX,
VIMAX = VREF × IMAX / 255
20
VIMAX
IMAX values both channels
ICS
CS pin input bias current
CSPx and CSNx
IxVFBDQ
xVFB input bias current,
discharge
End of soft-stop, xVFB = 100mV
GM-DROOP
Droop amplifier
transconductance
xVFB = 1 V
IBAL_TOL
Internal current share tolerance
(VCSP1 – VCSN1) = (VCSP2 – VCSN2) =
(VCSP3 – VCSN3) = VOCPP_MIN
ACSINT
Internal current sense gain
Gain from CSPx – CSNx to PWM comparator
VIMAX_MAX = 653mV, value of xIMAX
Copyright © 2012, Texas Instruments Incorporated
mV
A
98
A
–1.0
0.2
1.0
µA
90
125
180
µA
TPS51640A
486
497
518
TPS59640
TPS59641
480
497
518
–3%
11.65
µS
+3%
12.00
12.30
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V/V
5
TPS51640A, TPS59640, TPS59641
SLUSAQ2 – JANUARY 2012
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ELECTRICAL CHARACTERISTICS (continued)
over recommended free-air temperature range, VV5 = VV5DRV = 5.0 V; VV3R3 = 3.3 V; VxGFB = VPGND = VGND, VxVFB = VCORE
(Unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
TIMERS: SLEW RATE, ISLEW, ADDR, ON-TIME AND I/O TIMING
tSTARTUP1
Start-up time
VBOOT > 0 V, SLEWRATE = 12 mV/µs, no faults,
time from VR_ON until the controller responds to
SVID commands
SLSTRTSTP
xVFB slew soft-start / soft-stop
SLEWRATE = 12mV/µs, VR_ON goes ‘HI’,
VR_ON goes ‘LO = ‘Soft-stop’
1.25
1.50
1.75
VSLEWA ≤ 0.30V (Also disables SVID CLK timer)
10.0
12.0
14.5
3.5
4.0
5.0
5
VSLEWA = 0.4 V
VSLEWA = 0.6 V
0.75 V ≤ VSLEWA ≤ 0.85 V
SLSET
Slew rate setting
7.5
8.5
9.5
10.0
12.0
14.5
VSLEWA = 1.0 V
16
VSLEWA = 1.2 V
20
VSLEWA = 1.4 V
23
VSLEWA = 1.6 V
26
VSLEWA ≥ 2.50 V
26
ms
mV/µs
mV/µs
tPGDDGLTO
xPGOOD deglitch time
Time from xVFB out of +220 mV VDAC boundary
to xPGOOD low.
5
100
µs
tPGDDGLTU
xPGOOD deglitch time
Time from xVFB out of –315 mV VDAC boundary
to xPGOOD low.
150
500
µs
TPS51640A
270
327
375
TPS59640
TPS59641
265
327
380
TPS51640A
225
272
320
TPS59640
TPS59641
220
272
325
TPS51640A
185
235
280
TPS59640
TPS59641
180
235
285
TPS51640A
160
207
252
TPS59640
TPS59641
155
207
262
TPS51640A
140
185
231
TPS59640
TPS59641
134
185
241
TPS51640A
120
167
212
TPS59640
TPS59641
115
167
217
RCF=100 kΩ, VBAT=12 V, VDAC=1.1 V (550 kHz)
109
152
198
RCF=150 kΩ, VBAT=12 V, VDAC=1.1 V (600 kHz)
105
140
177
RCF=20 kΩ, VBAT=12 V, VDAC=1.1 V
(250 kHz)
RCF=24 kΩ, VBAT=12 V, VDAC=1.1 V
(300 kHz)
RCF=30 kΩ, VBAT=12 V, VDAC=1.1 V
(350 kHz)
tTON_CPU
CPU on-time
RCF=39 kΩ, VBAT=12 V, VDAC=1.1 V
(400 kHz)
RCF=56 kΩ, VBAT=12 V, VDAC=1.1 V
(450 kHz)
RCF=75 kΩ, VBAT=12 V, VDAC=1.1 V
(500 kHz)
6
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ns
Copyright © 2012, Texas Instruments Incorporated
TPS51640A, TPS59640, TPS59641
SLUSAQ2 – JANUARY 2012
www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
over recommended free-air temperature range, VV5 = VV5DRV = 5.0 V; VV3R3 = 3.3 V; VxGFB = VPGND = VGND, VxVFB = VCORE
(Unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
TPS51640A
315
347
388
TPS59640
TPS59641
310
347
393
TPS51640A
251
287
330
TPS59640
TPS59641
246
287
335
TPS51640A
215
245
287
TPS59640
TPS59641
210
245
292
TPS51640A
180
216
252
TPS59640
TPS59641
175
216
257
TPS51640A
160
190
223
TPS59640
TPS59641
155
190
228
RGF=75 kΩ, VBAT=12 V, VDAC=1.1 V (550 kHz)
145
171
210
RGF=100 kΩ, VBAT=12 V, VDAC=1.1 V (605 kHz)
120
156
205
RGF=150 kΩ, VBAT=12 V, VDAC=1.1 V (660 kHz)
100
150
201
150
200
ns
2
µs
100
ns
TIMERS: SLEW RATE, ISLEW, ADDR, ON-TIME AND I/O TIMING (Continued)
RGF=20 kΩ, VBAT=12 V, VDAC=1.1 V
(275 kHz)
RGF=24 kΩ, VBAT=12 V, VDAC=1.1V
(330 kHz)
RGF=30 kΩ, VBAT=12 V, VDAC=1.1 V
(385 kHz)
tTON_GPU
GPU on-time
RGF=39 kΩ,VBAT=12 V, VDAC=1.1 V
(440 kHz)
RGF=56 kΩ, VBAT=12 V, VDAC=1.1 V
(495 kHz)
tMIN
Controller minimum off time
Fixed value
(1)
tVCCVID
VID change to xVFB change
tVRONPGD
VR_ON low to xPGOOD low
tPGDVCC
xPGOOD low to xVFB change (1)
tVRTDGLT
VR_HOT# deglitch time
RSFTSTP
Soft-stop transistor resistance
ACK of SetVID-x command to start of voltage
ramp
20
Connect to CVFB, GVFB
550
50
ns
100
ns
0.2
0.7
ms
770
1100
Ω
PROTECTION: OVP, UVP PGOOD, VR_HOT, ‘FAULTS OFF’ AND INTERNAL THERMAL SHUTDOWN
VOVPH
Fixed OVP voltage threshold
voltage
VCSN1 or VGCSN > VOVPH for 1 µs, DRVL → ON
1.68
1.72
1.77
V
VPGDH
xPGOOD high threshold
Measured at the xVFB pin wrt/VID code,
device latches OFF
190
220
245
mV
VPGDL
xPGOOD low threshold
Measured at the xVFB pin wrt/VID code,
device latches OFF
–348
–315
–280
mV
bit0 of xTHERM register = high
757
783
808
bit1 of xTHERM register also is high
651
680
707
bit2 of xTHERM register also is high
611
638
663
bit3 of xTHERM register also is high
570
598
623
bit4 of xTHERM register also is high
531
559
583
bit5 of xTHERM register also is high
496
523
548
bit6 of xTHERM register also is high,
ALERT goes low
461
488
513
bit7 of XTHERM register also is high,
VR_HOT goes low
428
455
481
CDLx goes low, CDHx goes low
373
410
425
VTHERM
IMVP-7 thermal bit voltage
definition
ITHRM
THERM current
Leakage current
THINT
Internal controller thermal
Shutdown (1)
Latch off controller
THHYS
Controller thermal SD
hysteresis (1)
Cooling required before converter can be reset
(1)
–5
5
mV
µA
155
°C
20
°C
Specified by design. Not production tested.
Copyright © 2012, Texas Instruments Incorporated
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TPS51640A, TPS59640, TPS59641
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ELECTRICAL CHARACTERISTICS (continued)
over recommended free-air temperature range, VV5 = VV5DRV = 5.0 V; VV3R3 = 3.3 V; VxGFB = VPGND = VGND, VxVFB = VCORE
(Unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
4
8
13
36
50
0.2
2
µA
0.45
V
LOGIC (VCLK, VDIO, ALERT, VR_HOT, VR_ON) INTERFACE PINS: I/O VOLTAGE AND CURRENT
VDIO, ALERT, VR_HOT, pull-down resistance at
0.31 V
RRSVIDL
Open drain pull down resistance
RRPGDL
Open drain pull down resistance xPGOOD pull-down resistance at 0.31 V
IVRTTLK
Open drain leakage current
VIL
Input logic low
VIH
Input logic high
VHYST
Hysteresis voltage
VVR_ONL
VR_ON logic low
VVR_ONH
VR_ON logic high
IVR_ONH
I/O 3.3 V leakage
VR_HOT, xPGOOD, Hi-Z leakage,
apply 3.3-V in off state
VCLK, VDIO
-2
0.65
(1)
V
0.05
V
0.3
V
25.0
µA
0.8
Leakage current , VVR_ON = 1.1 V
Ω
V
10
OVERSHOOT AND UNDERSHOOT REDUCTION (OSR/USR) THRESHOLD SETTING
VOSR
OSR voltage set
VUSR
USR voltage set
RxSKIP = 20 kΩ
106
RxSKIP = 24 kΩ
156
RxSKIP = 30 kΩ
207
RxSKIP = 39 kΩ
257
RxSKIP = 56 kΩ
308
RxSKIP = 75 kΩ
409
RxSKIP = 100 kΩ
510
RxSKIP = 150 kΩ
610
RxSKIP = 20 kΩ
40
RxSKIP = 24 kΩ
60
RxSKIP = 30 kΩ
75
RxSKIP = 39 kΩ
115
RxSKIP = 56 kΩ
153
RxSKIP = 75 kΩ
190
RxSKIP = 100 kΩ
230
RxSKIP ≥ 150 kΩ = OFF
VOSR_OFF
OSR OFF setting
VxSKIP at start up
VOSRHYS
OSR/USR voltage hysteresis (2)
All settings
(2)
8
mV
mV
–
100
300
mV
20%
Specified by design. Not production tested.
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ELECTRICAL CHARACTERISTICS (continued)
over recommended free-air temperature range, VV5 = VV5DRV = 5.0 V; VV3R3 = 3.3 V; VxGFB = VPGND = VGND, VxVFB = VCORE
(Unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
(VCBSTx – VCSWx) = 5 V, ‘HI’ state,
(VVBST – VVDRVH) = 0.25 V
1.2
2.5
(VCBSTx – VCSWx) = 5 V, ‘LO’ state,
(VDRVH – VLL) = 0.25 V
0.8
2.5
VCDHx = 2.5 V, (VCBSTx – VCSWx) = 5 V, Source
2.2
VCDHx = 2.5 V, (VCBSTx – VCSWx) = 5 V, Sink
2.2
UNIT
DRIVERS: HIGH-SIDE, LOW-SIDE, CROSS CONDUCTION PREVENTION AND BOOST RECTIFIER
RDRVH
IDRVH
tDRVH
DRVH ON resistance
DRVH sink/source current (3)
DRVH transition time
RDRVL
DRVL ON resistance
IDRVL
DRVL sink/source current (3)
Ω
CDHx 10% to 90% or 90% to 10%, CCDHx = 3 nF
A
A
15
40
ns
ns
15
40
‘HI’ State, (VV5DRV – VVDRVL) = 0.25 V
0.9
2
‘LO’ State, (VVDRVL – VPGND)= 0.2 V
0.4
1
VCDLx = 2.5 V, Source
2.7
VCDLx = 2.5 V, Sink
A
6
A
VCDLx 90% to 10%, CCDLx = 3 nF
15
40
VCDLx 10% to 90%, CCDLx = 3 nF
15
40
tDRVL
DRVL transition time
tNONOVLP
Driver non overlap time
RDS(on)
BST on-resistance
(VV5DRV – VVBST), IF = 5 mA
IBSTLK
BST switch leakage current
VVBST = 34 V, VCSWx=28 V
Ω
ns
VCSWx falls to 1 V to VCDLx rises to 1 V
13
25
CDLx falls to 1 V to CDHx rises to 1 V
13
25
5
10
20
Ω
0.1
1
µA
0.7
V
ns
PWM and SKIP OUTPUT: I/O Voltage and Current
VPWML
xPWMy output low level
VPWMH
xPWMy output high level
VSKIPL
SKIP output low level
VSKIPH
xSKIP output high level
VPW(leak)
xPWM leakage
(3)
4.2
V
0.7
V
0.1
µA
4.2
Tri-state, V = 5 V
V
Specified by design. Not production tested.
Copyright © 2012, Texas Instruments Incorporated
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DEVICE INFORMATION
V5
CDH1
CBST1
CSW1
CDL1
V5DRV
PGND
CDL2
CSW2
CBST2
CDH2
VBAT
48
47
46
45
44
43
42
41
40
39
38
37
RSL PACKAGE
48 PINS
(TOP VIEW)
CPWM3
CTHERM
1
36
COCP-I
2
35 CSKIP
CIMON
3
34
GPWM
CCSP1
4
33
GSKIP
CCSN1
5
32
GTHERM
CCSN2
6
31
GOCP-I
CCSP2
7
30
GIMON
CCSP3
8
29
GCSP
CCSN3
9
28
GCSN
CCOMP
10
27
GCOMP
CVFB 11
26
GVFB
CGFB
25
GGFB
TPS51640A
TPS59640
TPS59641
22
23
24
GPGOOD
GF-IMAX
18
VCLK
SLEWA
17
CPGOOD
VR_HOT 21
16
VR_ON
20
15
V3R3
VDIO
14
VREF
ALERT 19
13
CF-IMAX
12
PIN FUNCTIONS
PIN
I/O
DESCRIPTION
NAME
NO.
ALERT
19
O
SVID interrupt line, open drain. Route between VCLK and VDIO to prevent cross-talk.
CBST1
46
I
Top N-channel FET bootstrap voltage input for CPU phase 1.
CBST2
39
I
Top N-channel bootstrap voltage input for CPU phase 2.
CCSN1
5
CCSN2
6
I
Negative current sense inputs for the CPU converter. Connect to the most negative node of current sense
resistor or inductor DCR sense network. CCSN1 has a secondary OVP comparator.
O
Output of GM error amplifier for the CPU converter. A resistor to VREF sets the droop gain.
I
Positive current sense inputs for the CPU converter. Connect to the most positive node of current sense resistor
or inductor DCR sense network. Tie CCSP3, 2 or 1 (in that order) to V3R3 to disable the phase. Tie CCSP1 to
V3R3 to run the GPU converter only.
CCSN3
9
CCOMP
10
CCSP1
4
CCSP2
7
CCSP3
8
CDH1
47
O
Top N-channel FET gate drive output for CPU phase 1.
CDH2
38
O
Top N-channel FET gate drive output for CPU phase 2.
CDL1
44
O
Synchronous N-channel FET gate drive output for CPU phase 1.
CDL2
41
O
Synchronous N-channel FET gate drive output for CPU phase 2.
10
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PIN
NAME
NO.
I/O
DESCRIPTION
CF-IMAX
13
I
Voltage divider to VREF. A resistor to GND sets the operating frequency of the CPU converter. The voltage level
sets the maximum operating current of the CPU converter. The IMAX value is an 8-bit A/D where VIMAX = VREF ×
IMAX / 255. Both are latched at start-up.
CGFB
12
I
Voltage sense return tied for the CPU converter. Tie to GND with a 10-Ω resistor to close feedback when the
microprocessor is not in the socket.
CIMON
3
O
Analog current monitor output for the CPU converter. VCIMON = ΣVCS × ACS × (1 + RCIMON/RCOCP). Connect a
220-nF capacitor to GND for stability.
COCP-I
2
I
Resistor to GND (RCOCP) selects 1 of 8 OCP levels (per phase, latched at start-up) of the CPU converter. Also,
voltage divider to CIMON. Resistor ratio sets the IMON gain (see CIMON pin description).
CPGOOD
17
O
IMVP-7_PWRGD output for the CPU converter. Open-drain.
CSW1
45
I/O Top N-channel FET gate drive return for CPU phase 1.
CSW2
40
I/O Top N-channel FET gate drive return for CPU phase 2.
CPWM3
36
O
PWM control for the external driver, 5V logic level.
CSKIP
35
O
Skip mode control of the external driver for the CPU converter. A logic HI = FCCM, LO = SKIP. R to GND selects
1 of 8 OSR/USR levels. 0.1 V < VCSKIP < 0.3 V at start-up turns OSR off.
CTHERM
1
I/O
Thermal sensor connection for the CPU converter. A resistor connected to VREF forms a divider with an NTC
thermistor connected to GND.
CVFB
11
I
Voltage sense line tied directly to VCORE of the CPU converter. Tie to VCORE with a 10-Ω resistor to close
feedback when µP is not in the socket. The soft-stop transistor is on this pin
GCSN
28
I
Negative current sense input for the GPU converter. Connect to the most negative node of current sense resistor
or inductor DCR sense network. GCSN has a secondary OVP comparator and includes the soft-stop pull-down
transistor.
GCSP
29
I
Positive current sense input for the GPU converter. Connect to the most positive node of current sense resistor
or inductor DCR sense network. Tie to V3R3 to disable the GPU converter.
GCOMP
27
O
Output of gM error amplifier for the GPU converter. A resistor to VREF sets the droop gain.
GGFB
25
I
Voltage sense return tied for the GPU converter. Tie to GND with a 10-Ω resistor to close feedback when the
microprocessor is not in the socket.
24
I
Voltage divider to VREF. R to GND sets the operating frequency of the GPU converter. The voltage level sets
the maximum operating current of the GPU converter. The IMAX value is an 8-bit A/D where VIMAX = VREF ×
IMAX / 255. Both are latched at start-up.
30
O
Analog current monitor output for the GPU converter. VGIMON = VISENSE × (1 + RGIMON/RGOCP). Connect a
220-nF capacitor to GND for stability.
31
I
Voltage divider to GIMON. Resistor ratio sets the IMON gain (see GIMON pin). Resistor to GND (RGOCP) selects
1 of 8 OCP levels (per phase, latched at start-up) of the GPU converter.
GPGOOD
23
O
IMVP-7_PWRGD output for the GPU converter. Open-drain.
GPWM
34
O
PWM control for the external driver, 5-V logic level.
33
O
Skip mode control of the external driver for the GPU converter, 5-V logic level. Logic HI = FCCM, LO = SKIP. R
to GND selects 1 of 8 OSR/USR levels. 0.1 V < VGSKIP< 0.3 V at start-up turns OSR off.
32
I/O Thermal sensor input for the GPU converter. A resistor connected to VREF forms a divider with an NTC
thermistor connected to GND.
GF-IMAX
GIMON
GOCP-I
GSKIP
GTHERM
GVFB
PGND
SLEWA
V5
V5DRV
V3R3
VBAT
26
I
Voltage sense line tied directly to VGFX of the GPU converter. Tie to VGFX with a 10-Ω resistor to close feedback
when the microprocessor is not in the socket. The soft-stop transistor is on this pin
42
–
Synchronous N-channel FET gate drive return.
22
I
The voltage at start-up sets 1 of 7 slew rates for both converters. The SLOW rate is SLEWRATE/4. Soft-start
and soft-stop rates are SLEWRATE/8. This value is latched at start-up. Tie to GND to disable SCLK timer.
48
I
5-V power input for analog circuits; connect through resistor to 5-V plane and bypass to GND with ≥1 µF ceramic
capacitor
43
I
Power input for the gate drivers; connected with an external resistor to V5F; decouple with a ≥2.2 µF ceramic
capacitor.
15
I
3.3-V power input; bypass to GND with ≥1 µF ceramic cap.
37
I
Provides VBAT information to the on-time circuits for both converters. A 10-kΩ series resistor protects the
adjacent pins from inadvertent shorts due to solder bridges or mis-probing during test.
I
SVID clock. 1-V logic level.
VCLK
18
VDIO
20
I/O SVID digital I/O line. 1-V logic level.
VREF
14
O
1.7-V, 500-µA reference. Bypass to GND with a 0.22-µF ceramic capacitor.
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PIN
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I/O
DESCRIPTION
NAME
NO.
VR_ON
16
I
IMVP-7 VR enable; 1V I/O level; 100-ns de-bounce. Regulator enters controlled soft-stop when brought low.
21
O
IMVP-7 thermal flag open drain output – active low. Typically pulled up to 1-V logic level through 56 Ω. Fall time
< 100 ns. 1-ms de-glitch using consecutive 1-ms samples.
GND
–
Thermal pad and analog circuit reference; tie to a quiet area in the system ground plane with multiple vias.
VR_HOT
PAD
12
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TYPICAL CHARACTERISTICS
3-Phase Configuration, 94-A CPU
0.700
VVID = 1.05 V
0.650
1.00
Specified Maximum
0.95
0.90
Output Voltage (V)
Output Voltage (V)
VVID = 0.6 V
0.675
1.05
0.625
Specified Maximum
0.600
0.575
0.550
0.85
VIN = 9 V
VIN = 20 V
Nominal
Specified Minimum
VIN = 9 V
VIN = 20 V
Nominal
0.525
0.80
Specified Minimum
0.500
0
10
20
30
40 50 60
70
Output Current (A)
80
90
100
0
Figure 1. Output Voltage vs. Load Current in PS0
2
4
6
8
10 12
14
Output Current (A)
16
18
20
Figure 2. Output Voltage vs. Load Current in PS1
95
VVID = 0.6 V
90
85
85
Efficiency (%)
Efficiency (%)
VVID = 1.05 V
90
80
75
70
VIN = 9 V
VIN = 20 V
65
0
10
20
30
40 50 60
70
Output Current (A)
80
90
100
Figure 3. Efficiency vs. Load Current in PS0
80
75
70
VIN = 9 V
VIN = 20 V
65
0
2
4
6
8
10 12
14
Output Current (A)
16
18
20
Figure 4. Efficiency vs. Load Current in PS1
400
RCF = 24 kW
350
Frequency (Hz)
300
250
200
150
PS0, VVID = 1.05 V, VIN = 20 V
PS0, VVID = 1.05 V, VIN = 9 V
PS1, VVID = 1.05 V, VIN = 20 V
PS1, VVID = 1.05 V, VIN = 9 V
100
50
0
0
10
20
30
40 50 60
70
Output Current (A)
80
90
100
Figure 5. Frequency vs Load-Current (PS0 and PS1)
Copyright © 2012, Texas Instruments Incorporated
Figure 6. Switching Ripple in PS0, VIN = 20 V
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TYPICAL CHARACTERISTICS
3-Phase Configuration, 94-A CPU (continued)
14
Figure 7. Start-Up and PGOOD
(TPS51640A and TPS59640 Only)
Figure 8. Soft-Stop
Figure 9. Load Transient, VIN = 9 V, Load step = 66 A
Figure 10. Load Transient, VIN = 20 V, Load step = 66 A
Figure 11. Load Insertion, VIN = 9 V, Load step = 66 A
Figure 12. Load Release, VIN = 20 V, Load step = 66 A
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Figure 13. Dynamic VID: SetVID-Slow/SetVID-Slow
Figure 14. Dynamic VID: SetVID-Fast/SetVID-Fast
Figure 15. SetVID-Decay/SetVID-Fast
Figure 16. PS Change PS0 to PS1 Toggle
180
30
135
20
90
10
45
0
−10
−20
0
3−Phase CPU
VOUT = 1.05 V
IOUT ~ 20 A
−45
−90
−30
−40
−50
100
−135
Gain
Phase
−180
1000
10000
Frequency (Hz)
100000
Figure 17. CPU Bode Plot
Copyright © 2012, Texas Instruments Incorporated
−225
1000000
80
0.0045
0.004
Magnitude
Target
Phase
CPU
3-Phase
60
0.0035
40
0.003
20
0.0025
0
0.002
-20
0.0015
-40
0.001
-60
0.0005
100
1k
10 k
Frequency (Hz)
100 k
ZOUTPhase (°)
225
40
ZOUTMagnitude (W)
50
Phase (°)
Magnitude (dB)
TYPICAL CHARACTERISTICS
3-Phase Configuration, 94-A CPU (continued)
-80
1M
Figure 18. Output Impedance
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TYPICAL CHARACTERISTICS
2-Phase Configuration, 53-A CPU
1.10
95
VVID = 1.05 V
VVID = 1.05 V
1.05
90
85
0.95
0.90
Specified Minimum
0.85
0
10
80
75
70
VIN = 9 V
VIN = 20 V
Nominal
0.80
16
Efficiency (%)
Output Voltage (V)
Specified Maximum
1.00
VIN = 9 V
VIN = 20 V
65
20
30
40
Output Current (A)
50
60
0
5
10
15
20 25 30 35
Output Current (A)
40
45
50
55
Figure 19. Output Voltage Vs. Load Current in PS0
Figure 20. Efficiency Vs. Load Current in PS0
Figure 21. Switching Ripple in PS0 (Persistence),
VIN = 9 V
Figure 22. Switching Ripple in PS0 (Persistence),
VIN = 20 V
Figure 23. Switching Ripple in PS0, VIN = 9 V
Figure 24. Switching Ripple in PS0, VIN = 20 V
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TYPICAL CHARACTERISTICS
2-Phase Configuration, 53-A CPU (continued)
Figure 25. Load Transient, VIN = 9 V, Load Step = 43 A
Figure 26. Load Transient, VIN = 20 V, Load Step = 43 A
Figure 27. Load Insertion, VIN = 9 V, Load Step = 43 A,
OSR/USR Setting 150 kΩ)
Figure 28. Load Release, VIN = 20 V, Load Step = 43 A,
OSR/USR Setting 150 kΩ)
Figure 29. Load Insertion, VIN = 9 V, Load Step = 43 A,
OSR/USR Setting 39 kΩ (Reduced Output Capacitance)
Figure 30. Load Release,VIN = 20 V, Load Step = 43 A,
OSR/USR Setting 39 kΩ (Reduced Output Capacitance)
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TYPICAL CHARACTERISTICS
2-Phase Configuration, 53-A CPU (continued)
Figure 31. Dynamic VID: SetVID-Slow/SetVID-Slow
Figure 32. Dynamic VID: SetVID-Fast/SetVID-Fast
Figure 33. Dynamic VID: SetVID-Decay/SetVID-Fast,
ILOAD = 2 A
Figure 34. Dynamic VID: SetVID-Decay/SetVID-Fast,
ILOAD = 0.5 A
80
ZOUTMagnitude (W)
0.004
18
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CPU
2-Phase
60
0.0035
40
0.003
20
0.0025
0
0.002
-20
0.0015
-40
0.001
-60
0.0005
100
Figure 35. PS Change PS0 to PS1 Toggle
Magnitude
Target
Phase
1k
10 k
Frequency (Hz)
100 k
ZOUTPhase (°)
0.0045
-80
1M
Figure 36. Output Impedance
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TYPICAL CHARACTERISTICS
1-Phase Configuration, 33-A GPU
1.250
0.650
VVID = 0.6 V
VVID = 1.23 V
1.225
0.625
1.200
Output Voltage (V)
Output Voltage (V)
Specified Maximum
1.175
1.150
1.125
Specified Minimum
0.600
Specified Maximum
0.575
0.550
1.100
VIN = 9 V
VIN = 20 V
Nominal
1.075
1.050
0.500
0
5
10
15
20
Output Current (A)
25
30
35
0
Figure 37. Output Voltage Vs. Load Current in PS0
2
4
Specified Minimum
6
8
10 12
14
Output Current (A)
16
18
20
Figure 38. Output Voltage Vs. Load Current in PS1
95
95
VVID = 1.23 V
VVID = 0.6 V
90
90
85
Efficiency (%)
Efficiency (%)
VIN = 9 V
VIN = 20 V
Nominal
0.525
85
80
80
75
70
65
75
VIN = 9 V
VIN = 20 V
VIN = 9 V
VIN = 20 V
60
55
70
0
5
10
15
20
Output Current (A)
25
30
35
Figure 39. Efficiency Vs. Load Current in PS0
0
2
4
6
8
10 12
14
Output Current (A)
16
18
20
Figure 40. Efficiency Vs. Load Current in PS1
400
350
Frequency (Hz)
300
250
200
150
PS0, VVID = 1.23 V, VIN = 20 V
PS0, VVID = 1.23 V, VIN = 9 V
PS1, VVID = 0.06 V, VIN = 20 V
PS1, VVID = 0.06 V, VIN = 9 V
100
50
RGF = 30 kW
0
0
5
10
15
20
25
30
35
Output Current (A)
Figure 41. Frequency Vs. Load Current
Copyright © 2012, Texas Instruments Incorporated
Figure 42. Switching Ripple in PS0
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TYPICAL CHARACTERISTICS
1-Phase Configuration, 33-A GPU (continued)
20
Figure 43. Start-Up and PGOOD
(TPS51640A and TPS59640 Only)
Figure 44. Soft-Stop
Figure 45. Load Transient, VIN = 9 V, Load Step = 20 A
Figure 46. Load Transient, VIN = 20 V, Load Step = 20 A
Figure 47. Load Insertion, VIN = 9V, Load Step = 20 A
Figure 48. Load Release, VIN = 20 V, Load Step = 20 A
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TYPICAL CHARACTERISTICS
1-Phase Configuration, 33-A GPU (continued)
Figure 51. Dynamic VID: SetVID-Decay/SetVID-Fast,
ILOAD = 0.5 A
Figure 52. Dynamic VID: SetVID-Decay/SetVID-Fast,
ILOAD = 2 A
50
225
40
180
30
135
20
90
10
45
0
−10
−20
0
GPU
VOUT = 1.05 V
IOUT ~ 10 A
−45
−90
−30
−40
−50
100
Phase (°)
Figure 50. Dynamic VID: SetVID-Fast/SetVID-Fast
Magnitude (dB)
Figure 49. Dynamic VID: SetVID-Slow/SetVID-Slow
−135
Gain
Phase
1000
−180
10000
Frequency (Hz)
100000
−225
1000000
Figure 53. Bode Plot
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TYPICAL CHARACTERISTICS (TPS59641 ONLY)
Figure 54. Startup to VBOOT Voltage and ALERT
Figure 55. Startup to VBOOT Voltage and CPGOOD,
GPGOOD
FUNCTIONAL BLOCK DIAGRAM
CCOMP
GND
V3R3
V5
10
Pad
15
48
43 V5DRV
CPWM1
CPWM2
CPWM3
Ramp
Comparator
46 CBST1
On-Time
1
CF-IMAX
+
CVFB 11
A
Gm
CCSP1
4
Acs
CCSN1
5
CCSP2
6
7
CCSP3
8
44 CDL1
CLK2
Phase
Manager
On-Time
2
CLK3
42 PGND
39 CBST2
OSR/USR
+
Current
Sharing
Circuitry
+
?
IS3
9
VREF 14
VR_ON 16
CPGOOD 17
40 CSW2
41 CDL2
COCP
CPx
CVD
ISUM
IS1
IS2
IS3
DAC0
and
DAC1
38 CDH2
Smart
Driver
ISHARE
+
+
On-Time
3
OSR
IS2
+
Acs
CCSN3
IS1
CLK
USR
Acs
CCSN2
+
+
Error
Amplifier
Integrator
DAC0
+
45 CSW1
CLK1
+
CGFB 12
47 CDH1
Smart
Driver
GOCP
GPx
GVD
1GFx
CPU
Logic Protection
and Status Circuitry
36 CPWM3
GPU
Logic Protection
and Status Circuitry
35 CSKIP
33 GSKIP
DAC0
GPWM
DAC1
Ramp
Comparator
VBAT
VCLK 18
+
ALERT 19
SVID
Interface
VDIO 20
GVD
A
Error
Amplifier
Integrator
Gm
+
CLK
On-Time
34 GPWM
GF-IMAX
DAC1
VR_HOT 21
+
+
+
GPGOOD 23
Acs
22
3
30
1
32
2
31
13
24
26
25
29
28
27
22
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GCOMP
GCSN
GCSP
GGFB
GVFB
CF-IMAX
GF-IMAX
GOCP-I
COCP-I
GTHERM
GIMON
CTHERM
CIMON
SLEWA
UDG-11271
Copyright © 2012, Texas Instruments Incorporated
Copyright © 2012, Texas Instruments Incorporated
GIMON
VREF
3R3V
VREF
VREF
VREF
VR_ON
GOCP-I
VREF
GPGOOD
VR_HOT
VDIO
ALERT
VCLK
CPGOOD
VREF
CCSN3
GSCN
CPU_VSNS
GFX_VSNS
CPU_GSNS
GFX_GSNS
VREF
COCP-I
GPWM
GSKIP
CSKIP
VREF
VCCIO
1
1
+
CCSP2
CCSN2
SVID:CLK
To CPU SVID
VCC_CORE
GFX: GT2
I_cc_max = 33A
I_TDC = 21.5A
I_DYNAMIC = 20.2A
Min. Over Current Limit= 37A
Loadline = 3.9mohm
Frequency setting= 385kHz
2
2
CCSN1
CCSP1
Note:
VR_HOT, CPGOOD and GPGOOD are open drain outputs
.
If used, they would need pull-up resistors.
CPU: QC
I_CC_max = 94A
I_TDC = 52A
I_DYN_max = 66A
Min. Over Current Limit= 112A
Loadline = 1.9mohm
Frequency setting= 300kHz
VDIO
VBAT
VIN
SVID:DATA
VCCIO
V5DRV
V5DRV
SVID:ALERT
V5
VREF
V5
VIN
ALERT
VCLK
VREF
CPWM3
COCP-I
CIMON
www.ti.com
TPS51640A, TPS59640, TPS59641
SLUSAQ2 – JANUARY 2012
APPLICATION INFORMATION
Figure 56. Application for 3-Phase CPU, 1-Phase GPU with Inductor DCR Current Sense (Controller with
2 internal drivers, 1st and 2nd Phase CPU Power)
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23
CIMON
CCSP1
CCSN2
GOCP-I
CCSN1
CCSP2
GIMON
CCSP3
GSCP
TPS51640A, TPS59640, TPS59641
SLUSAQ2 – JANUARY 2012
www.ti.com
GCSP
VIN
GCSN
1
GSKIP
GPWM
2
VGFX_CORE
V5
+
Figure 57. Application for 3-Phase CPU, 1-Phase GPU with Inductor DCR Current Sense continued
(External driver, 3rd Phase CPU Power)
GCSP
VIN
GCSN
1
CSKIP
CPWM3
2
VCC_CORE
V5
+
Figure 58. Application for 3-Phase CPU, 1-Phase GPU with Inductor DCR Current Sense continued
(External driver, GPU Power)
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Copyright © 2012, Texas Instruments Incorporated
VREF
3R3V
VREF
VREF
VR_ON
VR_HOT
VDIO
ALERT
VCLK
CPGOOD
VREF
3R3V
CC SN2
VREF
C CSP2
3R3V
2
2
SVID:ALERT
SVID:DATA
To CPU SVID
+
CCSP2
CCSN2
CCSN1
CCSP1
VCC_CORE
GFX: External. GPU Not used
Note:
VR_HOT and CPGOOD are open drain outputs.
If used, they would need pull- up resistors.
1
1
CPU: SV
I_CC_max = 53A
I_TDC = 36A
I_DYN_max = 43A
Min. Over Current Limit = 65A
Loadline = 1.9mohm
Frequency setting = 300kHz
VDIO
VCCIO
Note:
R19 = 39k (OSR/USR)
if 3x470uF bulk is used
VREF
VIN
SVID:CLK
V5DRV
ALERT
VBAT
V5DRV
V5
VCCIO
V5
VREF
VIN
VCLK
COCP-I
CIMON
www.ti.com
TPS51640A, TPS59640, TPS59641
SLUSAQ2 – JANUARY 2012
Figure 59. Application for Inductor DCR Current Sense Application Diagram for 2-Phase CPU and GPU
Disabled
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COCP-I
C IMON
C CSP1
CC SN1
CPU_VSNS
CPU_GSNS
TPS51640A, TPS59640, TPS59641
SLUSAQ2 – JANUARY 2012
www.ti.com
Table 1. Key External Component Recommendations
FUNCTION
MANUFACTURER
COMPONENT NUMBER
High-side MOSFET
Texas Instruments
CSD17302Q5A
Low-side MOSFET
Texas Instruments
CSD17303Q5
Powerblock MOSFET
Texas Instruments
CSD87350Q5D
Panasonic
ETQP4LR36AFC
NEC-Tokin
MPCH1040LR36,
MPCG1040LR36
TOKO
FDUE1040J-H-R36,
FCUL1040xxR36
ALPS
GLMDR3601A
Panasonic
EEFLXOD471R4
Sanyo
2TPLF470M4E
KEMET
T528Z477M2R5AT
Murata
GRM21BR60J106KE19L
Murata
GRM21BR60J226ME39L
Panasonic
ECJ2FB0J106K
Panasonic
ECJ2FB0J226K
Murata
NCP15WF104F03RC,
NCP18WF104F03RC
Panasonic
ERTJ1VS104F, ERTJ0ES104F
Vishay
WSK0612L7500FEA
Stackpole
CSSK0612FTL750
Inductors
Bulk Output Capacitors
Ceramic Output Capacitors
NTC Thermistors
Sense Resistors
DETAILED DESCRIPTION
Functional Overview
The TPS51640A, TPS59640, and TPS59641 are a DCAP+™ mode adaptive on-time controllers.
The output voltage is set using a DAC that outputs a reference in accordance with the 8-bit VID code defined in
Intel IMVP-7 PWM Specification document. In adaptive on-time converters, the controller varies the on-time as a
function of input and output voltage to maintain a nearly constant frequency during steady-state conditions. In
conventional voltage-mode constant on-time converters, each cycle begins when the output voltage crosses to a
fixed reference level. However, in these devices, the cycle begins when the current feedback reaches an error
voltage level which corresponds to the amplified difference between the DAC voltage and the feedback output
voltage. In the case of two-phase or three-phase operation, the current feedback from all the phases is summed
up at the output of the internal current-sense amplifiers.
This approach has two advantages:
• The amplifier DC gain sets an accurate linear load-line; this is required for CPU core applications.
• The error voltage input to the PWM comparator is filtered to improve the noise performance.
In addition, the difference of the DAC-to-output voltage and the current feedback goes through an integrator to
give a more or less linear load-line even at light loads where the inductor current is in discontinuous conduction
mode (DCM).
In a steady-state condition, the phases of the TPS51640A, TPS59640, and TPS59641 switch 180°
phase-displacement for two-phase mode and 120° phase-displacement for three-phase mode. The phase
displacement is maintained both by the architecture (which does not allow both high-side gate drives to be on in
any condition except transients) and the current ripple (which forces the pulses to be spaced equally). The
controller forces current sharing adjusting the on-time of each phase. Current balancing requires no user
intervention, compensation, or extra components.
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User Selections
After the 5-V and the 3.3-V power are applied to the controller, the controller must be enabled by the VR_ON
signal going high to the VCCIO logic level. At this time, the following information is latched and cannot be
changed anytime during operation. The ELECTRICAL CHARACTERISTICS table defines the values of each of
the selections.
• Operating Frequency. The resistor from CF-IMAX pin to GND sets the frequency of the CPU channel. The
resistor from GF-IMAX to GND sets the frequency of the GPU channel. See the ELECTRICAL
CHARACTERISTICS table for the resistor settings corresponding to each frequency selection. It is to be
noted that the operating frequency is a quasi-fixed frequency in the sense that the ON time is fixed based on
the input voltage (at the VBAT pin) and output voltage (set by VID). The OFF time varies based on various
factors such as load and power-stage components.
• Maximum Current Limit (ICC(max)) Information. The ICC(max) information of the CPU, which can be set by the
voltage on the CF-IMAX pin. The ICC(max) information of the GPU channel, which can be set by the voltage on
the GF-IMAX pin.
• Overcurrent Protection (OCP) Level. The resistor from COCP-I to GND sets the OCP level of the CPU
channel. The resistor from GOCP-I to GND sets the OCP level of the GPU channel.
• Current Monitor (IMON) Gain and Voltage. The resistor from CIMON to COCP-I sets the CIMON gain and
the CIMON voltage for the CPU channel. The resistor from GIMON to GOCP-I sets the GIMON gain and the
GIMON voltage for the GPU channel.
• Overshoot Reduction (OSR) and Undershoot Reduction (USR) Levels. The resistor from the CSKIP pin
to GND sets the OSR and USR for the CPU channel. The resistor from the GSKIP pin to GND sets the OSR
and USR level for GPU channel. The OSR can be disabled for CPU and/or GPU by setting a voltage of
approximately 200 mV on the corresponding xSKIP pin. This is accomplished by connecting a resistor from
VREF to the xSKIP pin.
• Slew Rate. The SetVID-Fast slew rate is set by the voltage on the SLEWA pin. The rate is the same for both
the CPU and GPU channels. The SetVID-Slow is ¼ of the SetVID-Fast rate.
Table 2. Key Selections Summary (1)
SELECTION
RESISTANCE (kΩ)
FREQUENCY
OCP
OSR / USR
20
Lowest
Lowest
Least overshoot,
least undershoot
Rising
Rising
Rising
Highest
Highest
Maximum overshoot,
maximum undershoot
24
30
39
56
75
100
150
(1)
See ELECTRICAL CHARACTERISTICS table for complete settings and values.
Table 3. Active Channels and Phases
CPU
(Active Phases)
GPU
(Active Phases)
CCSP1
CCSN1
CCSP2
CCSN2
CCSP3
CCSN3
GCSP
CGSN
3
CS
CS
CS
CS
CS
CS
n/a
n/a
2
CS
CS
CS
CS
3.3 V
GND
n/a
n/a
1
CS
CS
3.3 V
GND
GND
GND
n/a
n/a
OFF
3.3 V
GND
GND
GND
GND
GND
n/a
n/a
1
n/a
n/a
n/a
n/a
n/a
n/a
CS
CS
OFF
n/a
n/a
n/a
n/a
n/a
n/a
3.3 V
GND
Copyright © 2012, Texas Instruments Incorporated
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PWM Operation
Referring to the FUNCTIONAL BLOCK DIAGRAM and Figure 60, in continuous conduction mode, the converter
operates as shown in Figure 60.
VCORE
ISUM
VCOMP
SW_CLK
Phase 1
Phase 2
Phase 3
Time
UDG-11031
Figure 60. D-CAP+ Mode Basic Waveforms
Starting with the condition that the hig-side FETs are off and the low-side FETs are on, the summed current
feedback (ISUM) is higher than the error amplifier output (VCOMP). ISUM falls until it reaches the VCOMP level, which
contains a component of the output ripple voltage. The PWM comparator senses where the two waveform values
cross and triggers the on-time generator. This generates the internal SW_CLK. Each SW_CLK corresponds to
one switching ON pulse for one phase.
During single-phase operation, every SW_CLK generates a switching pulse on the same phase. Also, ISUM
voltage corresponds to just a single-phase inductor current.
During multi-phase operation, the SW_CLK is distributed to each of the phases in a cycle. Using the summed
inductor current and then cyclically distributing the ON-pulses to each phase automatically yields the required
interleaving of 360/N, where N is the number of phases.
Current Sensing
The TPS51640A, TPS59640 and TPS59641 provide independent channels of current feedback for every phase.
This increases the system accuracy and reduces the dependence of circuit performance on layout compared to
an externally summed architecture. The current sensing topology can be Inductor DCR Sensing, which yields the
best efficiency, or Resistor Current Sensing, which provides the most accuracy across wide temperature range.
DCR sensing can be optimized by using a NTC thermistor to reduce the variation of current sense with
temperature.
The pins CCSP1, CCSN1, CCSP2, CCSN2 and CCSP3, CCSN3 are used for the three phases of the CPU
channel. The pins GCSP and GCSN are used for the single-phase GPU channel.
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Setting the Load-line (DROOP)
VVID
Slope of Loadline RLL
VDROOP
VDROOP = RLL x ICC
ICC
UDG-11032
Figure 61. Load Line
VDROOP = RLL ´ ICC =
RCS(eff ) ´ A CS ´ ICC
RDROOP ´ GM
where
•
•
•
•
•
ACS is the gain of the current sense amplifier
RCS(eff) is the effective current sense resistance, whether a sense resistor or inductor DCR is used
ICC is the load current
RDROOP is the value of resistor from the DROOP pin to VREF
GM is the gain of the droop amplifier
(1)
Load Transients
When there is a sudden load increase, the output voltage immediately drops. This is reflected as a rising voltage
on the COMP pin. This forces the PWM pulses to come in sooner and more frequent which causes the inductor
current to rapidly increase. As the inductor current reaches the new load current, a steady-state operating
condition is reached and the PWM switching resumes the steady-state frequency.
When there is a sudden load release, the output voltage rises. This is reflected as a falling voltage on the COMP
pin. This delays the PWM pulses until the inductor current reaches the new load current level. At that point,
switching resumes and steady-state switching continues.
For simplicity, neither Figure 62, nor Figure 63 show the ripple on the Output VCORE nor the COMP waveform.
Copyright © 2012, Texas Instruments Incorporated
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LOAD
LOAD
VCORE
VCORE
ISUM
COMP
ISUM
COMP
SW_CLK
SW_CLK
Phase 1
Phase 1
Phase 2
Phase 2
Phase 3
Phase 3
Time
UDG-11034
UDG-11033
Figure 62. Operating Waveforms During Load
Transient
Figure 63. needs a title
Overshoot Reduction (OSR)
In low duty-cycle synchronous buck converters, an overshoot condition results from the output inductor having a
too little voltage (VCORE) with which to respond to a transient load release.
In Figure 64, a single phase converter is shown for simplicity. In an ideal converter, with typical input voltage of
12 V and 1.2-V output, the inductor has 10.8 V (12 V – 1.2 V) to respond to a transient load increase, but only
1.2 V with which to respond once the load releases.
12 V
+
–
10.8 V
L
1.2 V
–
1.2 V
+
C
UDG-11035
Figure 64. Synchronous Converter
When the overshoot reduction feature is enabled, the output voltage increases beyond a value that corresponds
to a voltage difference between the ISUM voltage and the COMP voltage, exceeding the specified OSR voltage
specified in the ELECTRICAL CHARACTERISTICS. At that instant, the low-side drivers are turned OFF. When
the low-side driver is turned OFF, the energy in the inductor is partially dissipated by the body diodes. As the
overshoot reduces, the low-side drivers are turned ON again.
Figure 65 shows the overshoot without OSR. Figure 66 shows the overshoot with OSR. The overshoot reduces
by approximately 23 mV. This shows that reduced output capacitance can be used while continuing to meet the
specification. Note the low-side driver turning OFF briefly during the overshoot.
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Figure 65. 43-A Load Transient Release Without
OSR Enabled.
SLUSAQ2 – JANUARY 2012
Figure 66. 43-A Load Transient Release With OSR
Enabled
Undershoot Reduction (USR)
When the transient load increase becomes quite large, it becomes difficult to meet the energy demanded by the
load especially at lower input voltages. Then it is necessary to quickly increase the energy tin the inductors
during the transient load increase. This is achieved in these devices by enabling pulse overlapping. In order to
maintain the interleaving of the multi-phase configuration and yet be able to have pulse-overlapping during
load-insertion, the undershoot reduction (USR) mode is entered only when necessary. This mode is entered
when the difference between COMP voltage and ISUM voltage exceeds the USR voltage level specified in the
ELECTRICAL CHARACTERISTICS table.
Figure 67 shows the performance with undershoot reduction. Figure 68 shows the performance without
undershoot reduction and that it is possible to eliminate undershoot by enabling the undershoot reduction. This
allows reduced output capacitance to be used and still meet the specification.
When the transient condition is over, the interleaving of the phases is resumed. For Figure 67, note the
overlapping pulses for Phase 1 and Phase 2 with USR enabled.
Figure 67. Performance for a 43-A Load Transient
Release Without USR Enabled
Figure 68. Performance for a 43-A Load Transient
Release With USR Enabled
A single-phase GPU operates in a similar way, but instead of pulse-overlap in multi-phase CPU, there is pulse
stretching to provide the needs of the transient load increase when USR is enabled.
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AutoBalance™ Current Sharing
The basic mechanism for current sharing is to sense the average phase current, then adjust the pulse width of
each phase to equalize the current in each phase. (See Figure 69.)
The PWM comparator (not shown) starts a pulse when the feedback voltage meets the reference. The VBAT
voltage charges Ct(ON) through Rt(ON). The pulse is terminated when the voltage at Ct(ON) matches the t(ON)
reference, normally the DAC voltage (VDAC).
The circuit operates in the following fashion, using Figure 69 as the block diagram. First assume that the 5-µs
averaged value of I1 = I2 = I3. In this case, the PWM modulator terminates at VDAC, and the normal pulse width
is delivered to the system. If instead, I1 > IAVG, then an offset is subtracted from VDAC, and the pulse width for
Phase 1 is shortened, reducing the current in Phase 1 to compensate. If I1 < IAVG, then a longer pulse is
produced, again compensating on a pulse-by-pulse basis.
VBAT 37
VDAC
CCSP1
CCSN1
4
+
Current
Amplifier
5
K x (I1-IAVG)
5 ms
Filter
RT(on)
+
PWM1
+
CT(on)
IAVG
RT(on)
VDAC
CCSP2
CCSN2
7
+
Current
Amplifier
6
K x (I2-IAVG)
5 ms
Filter
+
PWM2
+
CT(on)
IAVG
Averaging
Circuit
IAVG
RT(on)
VDAC
CCSP3
CCSN3
8
9
+
Current
Amplifier
5 ms
Filter
K x (I3-IAVG)
+
+
IAVG
PWM3
CT(on)
UDG-11036
Figure 69. Schematic Representation of AutoBalance Current Sharing
Dynamic VID and Power-State Changes
In
•
•
•
IMVP-7, there are 3 basic types of VID changes:
SetVID-Fast
SetVID-Slow
SetVID-Decay
SetVID-Fast change and a SetVID-Slow change automatically puts the power state in PS0. A SetVID-Decay
change automatically puts the power state in PS2.
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The CPU operates in the maximum phase mode when it is in PS0. This means when the CPU channel of the
controller is configured as 3-phase, all 3 phases are active in PS0. When configured in 2-phase mode, the two
phases are active in PS0. But in PS1, PS2 and PS3, the operation is in single-phase mode. Additionally, the
CPU channel in PS0 mode operates in forced continuous conduction mode (FCCM). But in PS1, PS2 and PS3,
the CPU channel operates in diode emulation (DE) mode for additional power savings and higher efficiency.
The single-phase GPU section always operates in diode emulation (DE) mode in all PS states.
The slew rate for a SetVID-Fast is the slew rate set at the SLEWA pin. This slew rate is defined in the
ELECTRICAL CHARACTERISTICS table. The SetVID-Slow is ¼ of the SetVID-Fast slew rate. On a
SetVID-Decay the output voltage decays by the rate of the load current or 1/8 of the slew rate whichever is
slower.
Additionally, on a SetVID-Fast change for a VID-up transition, the gain of the gM amplifier is increased to speed
up the response of the output voltage to meet the Intel timing requirement. So, it is possible to observe an
overshoot at the output voltage on a VID-up transition. This overshoot is allowed by the Intel specification.
XXX
Table 4. VID (continued)
Table 4. VID
VID
7
VID
6
VID
5
VID
4
VID
3
VID
2
VID
1
VID
0
HEX
0
0
0
0
0
0
0
0
00
0.000
0
0
0
0
0
0
0
1
01
0.250
0
0
0
0
0
0
1
0
02
0.255
0
0
0
0
0
0
1
1
03
0.260
0
0
0
0
0
1
0
0
04
0.265
0
0
0
0
0
1
0
1
05
0.270
0
0
0
0
0
1
1
0
06
0.275
0
0
0
0
0
1
1
1
07
0.280
0
0
0
0
1
0
0
0
08
0.285
0
0
0
0
1
0
0
1
09
0.290
0
0
0
0
1
0
1
0
0A
0.295
0
0
0
0
1
0
1
1
0B
0.300
0
0
0
0
1
1
0
0
0C
0.305
0
0
0
0
1
1
0
1
0D
0.310
0
0
0
0
1
1
1
0
0E
0.315
0
0
0
0
1
1
1
1
0F
0.320
0
0
0
1
0
0
0
0
10
0.325
0
0
0
1
0
0
0
1
11
0.330
0
0
0
1
0
0
1
0
12
0.335
0
0
0
1
0
0
1
1
13
0.340
0
0
0
1
0
1
0
0
14
0.345
0
0
0
1
0
1
0
1
15
0.350
0
0
0
1
0
1
1
0
16
0.355
0
0
0
1
0
1
1
1
17
0.360
0
0
0
1
1
0
0
0
18
0.365
0
0
0
1
1
0
0
1
19
0.370
0
0
0
1
1
0
1
0
1A
0.375
0
0
0
1
1
0
1
1
1B
0.380
0
0
0
1
1
1
0
0
1C
0.385
0
0
0
1
1
1
0
1
1D
0.390
0
0
0
1
1
1
1
0
1E
0.395
0
0
0
1
1
1
1
1
1F
0.400
Copyright © 2012, Texas Instruments Incorporated
VDAC
0
0
1
0
0
0
0
0
20
0.405
0
0
1
0
0
0
0
1
21
0.410
0
0
1
0
0
0
1
0
22
0.415
0
0
1
0
0
0
1
1
23
0.420
0
0
1
0
0
1
0
0
24
0.425
0
0
1
0
0
1
0
1
25
0.430
0
0
1
0
0
1
1
0
26
0.435
0
0
1
0
0
1
1
1
27
0.440
0
0
1
0
1
0
0
0
28
0.445
0
0
1
0
1
0
0
1
29
0.450
0
0
1
0
1
0
1
0
2A
0.455
0
0
1
0
1
0
1
1
2B
0.460
0
0
1
0
1
1
0
0
2C
0.465
0
0
1
0
1
1
0
1
2D
0.470
0
0
1
0
1
1
1
0
2E
0.475
0
0
1
0
1
1
1
1
2F
0.480
0
0
1
1
0
0
0
0
30
0.485
0
0
1
1
0
0
0
1
31
0.490
0
0
1
1
0
0
1
0
32
0.495
0
0
1
1
0
0
1
1
33
0.500
0
0
1
1
0
1
0
0
34
0.505
0
0
1
1
0
1
0
1
35
0.510
0
0
1
1
0
1
1
0
36
0.515
0
0
1
1
0
1
1
1
37
0.520
0
0
1
1
1
0
0
0
38
0.525
0
0
1
1
1
0
0
1
39
0.530
0
0
1
1
1
0
1
0
3A
0.535
0
0
1
1
1
0
1
1
3B
0.540
0
0
1
1
1
1
0
0
3C
0.545
0
0
1
1
1
1
0
1
3D
0.550
0
0
1
1
1
1
1
0
3E
0.555
0
0
1
1
1
1
1
1
3F
0.560
0
1
0
0
0
0
0
0
40
0.565
0
1
0
0
0
0
0
1
41
0.570
0
1
0
0
0
0
1
0
42
0.575
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33
TPS51640A, TPS59640, TPS59641
SLUSAQ2 – JANUARY 2012
www.ti.com
Table 4. VID (continued)
34
Table 4. VID (continued)
0
1
0
0
0
0
1
1
43
0.580
0
1
1
1
0
0
1
1
73
0.820
0
1
0
0
0
1
0
0
44
0.585
0
1
1
1
0
1
0
0
74
0.825
0
1
0
0
0
1
0
1
45
0.590
0
1
1
1
0
1
0
1
75
0.830
0
1
0
0
0
1
1
0
46
0.595
0
1
1
1
0
1
1
0
76
0.835
0
1
0
0
0
1
1
1
47
0.600
0
1
1
1
0
1
1
1
77
0.840
0
1
0
0
1
0
0
0
48
0.605
0
1
1
1
1
0
0
0
78
0.845
0
1
0
0
1
0
0
1
49
0.610
0
1
1
1
1
0
0
1
79
0.850
0
1
0
0
1
0
1
0
4A
0.615
0
1
1
1
1
0
1
0
7A
0.855
0
1
0
0
1
0
1
1
4B
0.620
0
1
1
1
1
0
1
1
7B
0.860
0
1
0
0
1
1
0
0
4C
0.625
0
1
1
1
1
1
0
0
7C
0.865
0
1
0
0
1
1
0
1
4D
0.630
0
1
1
1
1
1
0
1
7D
0.870
0
1
0
0
1
1
1
0
4E
0.635
0
1
1
1
1
1
1
0
7E
0.875
0
1
0
0
1
1
1
1
4F
0.640
0
1
1
1
1
1
1
1
7F
0.880
0
1
0
1
0
0
0
0
50
0.645
1
0
0
0
0
0
0
0
80
0.885
0
1
0
1
0
0
0
1
51
0.650
1
0
0
0
0
0
0
1
81
0.890
0
1
0
1
0
0
1
0
52
0.655
1
0
0
0
0
0
1
0
82
0.895
0
1
0
1
0
0
1
1
53
0.660
1
0
0
0
0
0
1
1
83
0.900
0
1
0
1
0
1
0
0
54
0.665
1
0
0
0
0
1
0
0
84
0.905
0
1
0
1
0
1
0
1
55
0.670
1
0
0
0
0
1
0
1
85
0.910
0
1
0
1
0
1
1
0
56
0.675
1
0
0
0
0
1
1
0
86
0.915
0
1
0
1
0
1
1
1
57
0.680
1
0
0
0
0
1
1
1
87
0.920
0
1
0
1
1
0
0
0
58
0.685
1
0
0
0
1
0
0
0
88
0.925
0
1
0
1
1
0
0
1
59
0.690
1
0
0
0
1
0
0
1
89
0.930
0
1
0
1
1
0
1
0
5A
0.695
1
0
0
0
1
0
1
0
8A
0.935
0
1
0
1
1
0
1
1
5B
0.700
1
0
0
0
1
0
1
1
8B
0.940
0
1
0
1
1
1
0
0
5C
0.705
1
0
0
0
1
1
0
0
8C
0.945
0
1
0
1
1
1
0
1
5D
0.710
1
0
0
0
1
1
0
1
8D
0.950
0
1
0
1
1
1
1
0
5E
0.715
1
0
0
0
1
1
1
0
8E
0.955
0
1
0
1
1
1
1
1
5F
0.720
1
0
0
0
1
1
1
1
8F
0.960
0
1
1
0
0
0
0
0
60
0.725
1
0
0
1
0
0
0
0
90
0.965
0
1
1
0
0
0
0
1
61
0.730
1
0
0
1
0
0
0
1
91
0.970
0
1
1
0
0
0
1
0
62
0.735
1
0
0
1
0
0
1
0
92
0.975
0
1
1
0
0
0
1
1
63
0.740
1
0
0
1
0
0
1
1
93
0.980
0
1
1
0
0
1
0
0
64
0.745
1
0
0
1
0
1
0
0
94
0.985
0
1
1
0
0
1
0
1
65
0.750
1
0
0
1
0
1
0
1
95
0.990
0
1
1
0
0
1
1
0
66
0.755
1
0
0
1
0
1
1
0
96
0.995
0
1
1
0
0
1
1
1
67
0.760
1
0
0
1
0
1
1
1
97
1.000
0
1
1
0
1
0
0
0
68
0.765
1
0
0
1
1
0
0
0
98
1.005
0
1
1
0
1
0
0
1
69
0.770
1
0
0
1
1
0
0
1
99
1.010
0
1
1
0
1
0
1
0
6A
0.775
1
0
0
1
1
0
1
0
9A
1.015
0
1
1
0
1
0
1
1
6B
0.780
1
0
0
1
1
0
1
1
9B
1.020
0
1
1
0
1
1
0
0
6C
0.785
1
0
0
1
1
1
0
0
9C
1.025
0
1
1
0
1
1
0
1
6D
0.790
1
0
0
1
1
1
0
1
9D
1.030
0
1
1
0
1
1
1
0
6E
0.795
1
0
0
1
1
1
1
0
9E
1.035
0
1
1
0
1
1
1
1
6F
0.800
1
0
0
1
1
1
1
1
9F
1.040
0
1
1
1
0
0
0
0
70
0.805
1
0
1
0
0
0
0
0
A0
1.045
0
1
1
1
0
0
0
1
71
0.810
1
0
1
0
0
0
0
1
A1
1.050
0
1
1
1
0
0
1
0
72
0.815
1
0
1
0
0
0
1
0
A2
1.055
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TPS51640A, TPS59640, TPS59641
SLUSAQ2 – JANUARY 2012
www.ti.com
Table 4. VID (continued)
Table 4. VID (continued)
1
0
1
0
0
0
1
1
A3
1.060
1
1
0
1
0
0
1
1
D3
1.300
1
0
1
0
0
1
0
0
A4
1.065
1
1
0
1
0
1
0
0
D4
1.305
1
0
1
0
0
1
0
1
A5
1.070
1
1
0
1
0
1
0
1
D5
1.310
1
0
1
0
0
1
1
0
A6
1.075
1
1
0
1
0
1
1
0
D6
1.315
1
0
1
0
0
1
1
1
A7
1.080
1
1
0
1
0
1
1
1
D7
1.320
1
0
1
0
1
0
0
0
A8
1.085
1
1
0
1
1
0
0
0
D8
1.325
1
0
1
0
1
0
0
1
A9
1.090
1
1
0
1
1
0
0
1
D9
1.330
1
0
1
0
1
0
1
0
AA
1.095
1
1
0
1
1
0
1
0
DA
1.335
1
0
1
0
1
0
1
1
AB
1.100
1
1
0
1
1
0
1
1
DB
1.340
1
0
1
0
1
1
0
0
AC
1.105
1
1
0
1
1
1
0
0
DC
1.345
1
0
1
0
1
1
0
1
AD
1.110
1
1
0
1
1
1
0
1
DD
1.350
1
0
1
0
1
1
1
0
AE
1.115
1
1
0
1
1
1
1
0
DE
1.355
1
0
1
0
1
1
1
1
AF
1.120
1
1
0
1
1
1
1
1
DF
1.360
1
0
1
1
0
0
0
0
B0
1.125
1
1
1
0
0
0
0
0
E0
1.365
1
0
1
1
0
0
0
1
B1
1.130
1
1
1
0
0
0
0
1
E1
1.370
1
0
1
1
0
0
1
0
B2
1.135
1
1
1
0
0
0
1
0
E2
1.375
1
0
1
1
0
0
1
1
B3
1.140
1
1
1
0
0
0
1
1
E3
1.380
1
0
1
1
0
1
0
0
B4
1.145
1
1
1
0
0
1
0
0
E4
1.385
1
0
1
1
0
1
0
1
B5
1.150
1
1
1
0
0
1
0
1
E5
1.390
1
0
1
1
0
1
1
0
B6
1.155
1
1
1
0
0
1
1
0
E6
1.395
1
0
1
1
0
1
1
1
B7
1.160
1
1
1
0
0
1
1
1
E7
1.400
1
0
1
1
1
0
0
0
B8
1.165
1
1
1
0
1
0
0
0
E8
1.405
1
0
1
1
1
0
0
1
B9
1.170
1
1
1
0
1
0
0
1
E9
1.410
1
0
1
1
1
0
1
0
BA
1.175
1
1
1
0
1
0
1
0
EA
1.415
1
0
1
1
1
0
1
1
BB
1.180
1
1
1
0
1
0
1
1
EB
1.420
1
0
1
1
1
1
0
0
BC
1.185
1
1
1
0
1
1
0
0
EC
1.425
1
0
1
1
1
1
0
1
BD
1.190
1
1
1
0
1
1
0
1
ED
1.430
1
0
1
1
1
1
1
0
BE
1.195
1
1
1
0
1
1
1
0
EE
1.435
1
0
1
1
1
1
1
1
BF
1.200
1
1
1
0
1
1
1
1
EF
1.440
1
0
0
0
0
0
0
C0
1.205
1
1
1
1
0
0
0
0
F0
1.445
1
1
0
0
0
0
0
1
C1
1.210
1
1
1
1
0
0
0
1
F1
1.450
1
1
0
0
0
0
1
0
C2
1.215
1
1
1
1
0
0
1
0
F2
1.455
1
1
0
0
0
0
1
1
C3
1.220
1
1
1
1
0
0
1
1
F3
1.460
1
1
0
0
0
1
0
0
C4
1.225
1
1
1
1
0
1
0
0
F4
1.465
1
1
0
0
0
1
0
1
C5
1.230
1
1
1
1
0
1
0
1
F5
1.470
1
1
0
0
0
1
1
0
C6
1.235
1
1
1
1
0
1
1
0
F6
1.475
1
1
0
0
0
1
1
1
C7
1.240
1
1
1
1
0
1
1
1
F7
1.480
1
1
0
0
1
0
0
0
C8
1.245
1
1
1
1
1
0
0
0
F8
1.485
1
1
0
0
1
0
0
1
C9
1.250
1
1
1
1
1
0
0
1
F9
1.490
1
1
0
0
1
0
1
0
CA
1.255
1
1
1
1
1
0
1
0
FA
1.495
1
1
0
0
1
0
1
1
CB
1.260
1
1
1
1
1
0
1
1
FB
1.500
1
1
0
0
1
1
0
0
CC
1.265
1
1
1
1
1
1
0
0
FC
1.505
1
1
0
0
1
1
0
1
CD
1.270
1
1
1
1
1
1
0
1
FD
1.510
1
1
0
0
1
1
1
0
CE
1.275
1
1
1
1
1
1
1
0
FE
1.515
1
1
0
0
1
1
1
1
CF
1.280
1
1
1
1
1
1
1
1
FF
1.520
1
1
0
1
0
0
0
0
D0
1.285
1
1
0
1
0
0
0
1
D1
1.290
1
1
0
1
0
0
1
0
D2
1.295
Copyright © 2012, Texas Instruments Incorporated
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35
TPS51640A, TPS59640, TPS59641
SLUSAQ2 – JANUARY 2012
www.ti.com
Gate Driver
The TPS51640A, TPS59640, and TPS59641 incorporate two internal strong, high-performance gate drives with
adaptive cross-conduction protection. These drivers are for two phases in the CPU channel. The third phase of
the CPU and the single-phase GPU channel require external drivers.
The internal driver in these devices uses the state of the CDLx and CSWx pins to be sure the high-side or
low-side FET is OFF before turning the other ON. Fast logic and high drive currents (up to 8-A typical) quickly
charge and discharge FET gates to minimize dead-time to increase efficiency. The high-side gate driver also
includes an integrated boost FET instead of merely a diode to increase the effective drive voltage for higher
efficiency. A zero-crossing detection logic, which detects the switch-node voltage before turning OFF the low-side
FET, is used to minimize losses during DCM operation.
Input Under Voltage Protection (5V and 3.3V)
The TPS51640A, TPS59640, and TPS59641 continuously monitor the voltage on the V5DRV, V5 and V3R3 pin
to be sure the value is high enough to bias the device properly and provide sufficient gate drive potential to
maintain high efficiency. The converter starts with approximately 4.4-V and has a nominal 200 mV of hysteresis.
The input (VBAT) does not have a UVLO function, so the circuit operates with power inputs as low as
approximately 3 x VCORE.
Power Good (CPGOOD and GPGOOD)
These devices have two open-drain power good pins that follow the requirements for IMVP-7. CPGOOD is used
for the CPU channel output voltage and GPGOOD is used for the GPU channel output voltage. Both of these
signals are active high. The upper and the lower limits for the output voltage for xPGOOD active are:
• Upper: VDAC +220 mV
• Lower : VDAC –315 mV
xPGOOD goes inactive (low) as soon as the VR_ON pin is pulled low or an undervoltage condition on V5 or
V3R3 is detected. The xPGOOD signals are masked during DAC transitions to prevent false triggering during
voltage slewing.
Output Under Voltage Protection
Output undervoltage protection works in conjunction with the current protection described below. If VCORE drops
below the low PGOOD threshold, then the drivers are turned OFF until VR_ON is cycled.
Overcurrent Protection
The TPS51640A, TPS59640, and TPS59641 use a valley current limiting scheme, so the ripple current must be
considered. The DC current value at OCP is the OCP limit value plus half of the ripple current. Current limiting
occurs on a phase-by-phase and pulse-by-pulse basis. If the voltage between xCSPx and xCSNx is above the
OCP value, the converter delays the next ON pulse until it drops below the OCP limit. For inductor current
sensing circuits, the voltage between xCSPx and xCSNx is the inductor DCR value multiplied by the resistor
divider which is part of the NTC compensation network. As a result, a wide range of OCP values can be obtained
by changing the resistor divider value. In general, use the highest OCP setting possible with the least attenuation
in the resistor divider to provide as much signal to the device as possible. This provides the best performance for
all parameters related to current feedback.
In OCP mode, the voltage drops until the UVP limit is reached. Then, the converter sets the xPGOOD to inactive,
and the drivers are turned OFF. The converter remains in this state until the device is reset by the VR_ON.
Overvoltage Protection
An OVP condition is detected when VCORE is more than 220 mV greater than VDAC. In this case, the converter
sets xPGOOD inactive, and turns ON the drive for the Low-side FET. The converter remains in this state until the
device is reset by cycling VR_ON. However, because of the dynamic nature of IMVP-7 systems, the +220 mV
OVP threshold is blanked much of the time. In order to provide protection to the processor 100% of the time,
there is a second OVP level fixed at 1.7 V which is always active. If the fixed OVP condition is detected, the
PGOOD are forced inactive and the low-side FETs are tuned ON. The converter remains in this state until
VR_ON is cycled.
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Over Temperature Protection
Two types of thermal protection are provided in these devices:
• VR_HOT
• Thermal Shutdown
VR_HOT
The VR_HOT signal is an Intel-defined open-drain signal that is used to protect the VCORE power chain. To use
VR_HOT, place an NTC thermistor at the hottest area of the CPU channel and connect it from CTHERM pin to
GND. Similarly for GPU channel, place the NTC thermistor at the hottest area and connect it from GTHERM to
GND. Also, connect a resistor from VREF to GTHERM and CTHERM. As the temperature increases, the
xTHERM voltage drops below the THERM threshold, VR_HOT is activated. A small capacitor may be connected
to the xTHERM pins for high frequency noise filtering.
lists the thermal zone register bits based on the xTHERM pin voltage.
Table 5. Thermal Zone Register Bits
OUTPUT IS
SHUTDOWN
VR_HOT
ASSERTED
b7
b6
b5
b4
b3
b2
b1
b0
410 mV
455 mV
458 mV
523 mV
559 mV
598 mV
638 mV
680 mV
783 mV
SVID ALERT ASSERTED
xTHERM THRESHOLD VOLTAGE FOR THE TEMPERATURE
ZONE REGISTER BITS TO BE ASSERTED.
Thermal Shutdown
When the xTHERM pin voltage continues to drop even after VR_HOT is asserted, the drivers turn OFF and the
output is shutdown. These devices also have an internal temperature sensor. When the temperature reaches a
nominal 155°C, the device shuts down until the temperature cools approximately 20°C. Then, the circuit can be
re-started by cycling VR_ON.
Current Monitor, IMON
The TPS51640A, TPS59640, and TPS59641 includes a current monitor (IMON) function each for CPU channel
and GPU channel. The current monitor puts out an analog voltage proportional to the output current on the
xIMON pins.
The current monitor function is tied with the OCP selection resistors. The RCOCP and RGOCP are resistors to GND
from COCP-I and GOCP-I respectively to select the OCP levels. RCIMON is the resistor from CIMON to COCP-I to
set the CIMON gain. Similarly, RGIMON is the resistor from GIMON to GOCP-I to set the GIMON gain.
The calculation for the CIMON voltage is shown in Equation 2. The calculation for the GIMON voltages is shown
in Equation 3.
æ R
ö
VCIMON = A CS ´ ç 1 + CIMON ÷ ´
VCCSn
RCOCP ø
è
(2)
å
æ R
ö
VGIMON = A CS ´ ç 1 + GIMON ÷ ´ VGCS
RGOCP ø
è
where
•
•
•
ACS is given in the ELECTRICAL CHARACTERISTICS table
Σ VCCS is the sum of the DC voltages at the inputs to the CPU channel current sense amplifiers
VGCS is the DC voltage at the GPU channel current sense amplifier
(3)
For the current monitor function to be stable, connect a 220-nF capacitor from CIMON and GIMON to GND.
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Setting the Maximum Processor Current (ICC(max))
The TPS51640 controller allows the user to set the maximum processor current with the multi-function pins
CF-IMAX and GF-IMAX. The voltage on the CF-IMAX and GF-IMAX at start-up sets the maximum processor
current (ICC(max)) for CPU and GPU respectively.
The RCF and RGF are resistors to GND from CF-IMAX and GF-IMAX respectively to select the frequency setting.
RCIMAX is the resistor from VREF to CF-IMAX and RGIMAX is the resistor from VREF to GF-IMAX.
Equation 4 describes the setting the ICC(max) for the CPU channel and Equation 5 describes the setting the
ICC(max) for the GPU channel.
æ
ö
RCF
ICC(max )CPU = 255 ´ ç
÷
è RCF + RCIMAX ø
(4)
æ
ö
RGF
ICC(max )GPU = 255 ´ ç
÷
R
+
è GF RGIMAX ø
(5)
Internal Driver Bypass Mode
The controller can be configured to operate in internal driver bypass mode for use with DrMOS type devices and
driver-integrated PowerBlock devices. Consider the following items when designing for operation in this mode.
• Tie CSW2, CSW1 to V5DRV.
• CDL1 becomes the PWM input to the Phase 1 DrMOS device (or external driver)
• CDL2 becomes the PWM input to the Phase 2 DrMOS device (or external driver)
• CSKIP pin becomes the input to the SKIP/FCCM pin of the DrMOS device (or external driver)
• The Phase-2 and Phase-3 DrMOS device (or the external driver) must be configured in FCCM mode.
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DESIGN STEPS
The design procedure using the TPS51640A, TPS59640, and TPS59641 is very simple . An excel-based
component value calculation tool is available. Contact your local TI representative to get a copy of the
spreadsheet.
The procedure is explained here below with the following design example:
CPU VCORE SPECIFICATIONS
GFX VCORE SPECIFICATIONS
No. of phases
3
1
Input Voltage Range
9 V to 20 V
9 V to 20 V
VHFM
0.9 V
1.23 V
ICC(max)
94 A
33 A
IDYN-MAX
66 A
20 A
ICC-TDC
52
21.5
Load-line
1.9 mV/A
3.9 mV/A
Fast Slew Rate (minimum)
10 mV/µs
10 mV/µs
Step One: Select Switching Frequency.
The CPU channel switching frequency is selected by a resistor from CF-IMAX to GND (RCF) and GPU channel
switching frequency is selected by a resistor from GF-IMAX to GND (RGF). The frequency is an approximate
frequency and is expected to vary based on load and input voltage.
SELECTION RESISTANCE (kΩ)
CPU CHANNEL FREQUENCY
(kHz)
GPU CHANNEL FREQUENCY
(kHz)
20
250
275
24
300
330
30
350
385
39
400
440
56
450
495
75
500
550
100
550
605
150
600
660
For this design, the switching frequency for CPU channel is chosen to be 300 kHz and GPU channel is chosen to
be 385 kHz. Therefore,
RCF = 24 kΩ and RGF = 30 kΩ
Step Two: Set ICC(max)
The ICC(max) is set by the voltage on CF-IMAX for CPU channel and GF-IMAX for GPU channel. This is set by the
resistors from VREF to CF-IMAX (RCMAX) and from VREF to GF-IMAX (RGMAX)
From Equation 4 and Equation 5,
RCMAX = 42.2 kΩ and RGMAX = 200 kΩ.
Step Three: Set the Slew Rate
The slew rate is set by the voltage setting on SLEWA pin. For a minimum 10 mV/ms slew rate, the voltage on the
SLEWA pin must be: 0.8 V. This is set by a resistor divider on SLEWA pin from VREF. The low-side resistor is
chosen to be 150 kΩ and the high-side resistor is calculated as 169 kΩ.
Step Four: Determine inductor value and choose inductor.
Smaller values of inductor have better transient performance but higher ripple and lower efficiency. Higher values
have the opposite characteristics. It is common practice to limit the ripple current to 20% to 40% of the maximum
current per phase. In this case, we use 30%:
94 A
IP-P =
´ 0.3 = 9.4 A
3
(6)
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L=
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V ´ dT
IP-P
(7)
In this equation,
V = VIN-MAX – VHFM = 19. 1V; dT = VHFM / (F x VIN-MAX) = 150 ns; Ipp = 9.4A. So, calculating, L = 0.304 µH.
An inductance value of 0.36 µH is chosen as this is a commonly used inductor for VCORE application. The
inductor must not saturate during peak loading conditions.
æ ICC(max ) I
ö
ISAT = ç
+ P-P ÷ ´ 1.2 = 43.2 A
ç NPHASE
2 ÷
è
ø
(8)
The factor of 1.2 allows for current sensing and current limiting tolerances; the factor of 1.25 is the Intel 25%
momentary OCP requirement.
The chosen inductor should have the following characteristics:
• An inductance to current curve ratio equal to 1 (or as close possible). Inductor DCR sensing is based on the
idea L/DCR is approximately a constant through the current range of interest.
• Either high saturation or soft saturation.
• Low DCR for improved efficiency, but at least 0.7 mΩ for proper signal levels.
• DCR tolerance as low as possible for load-line accuracy.
For this application, a 0.36-µH, 0.825-mΩ inductor is chosen. Because the per phase current for GPU is same as
CPU, the same inductor for GPU channel is chosen.
Step Five: Determine current sensing method.
The TPS51640A, TPS59640, and TPS59641 support both resistor sensing and inductor DCR sensing. Inductor
DCR sensing is chosen. For resistor sensing, substitute the resistor value (0.75 mΩ recommended for a 3-phase
94-A application) for RCS in the subsequent equations and skip Step Four.
Step Six: Design the thermal compensation network and selection of OCP.
In most designs, NTC thermistors are used to compensate thermal variations in the resistance of the inductor
winding. This winding is generally copper, and so has a resistance coefficient of 3900 PPM/°C. NTC thermistors,
on the other hand, have very non-linear characteristics and need two or three resistors to linearize them over the
range of interest. The typical DCR circuit is shown in Figure 70.
L
RSEQU
RDCR
RNTC
I
RSERIES
RPAR
CSENSE
CSP
CSN
UDG-11039
Figure 70. Typical DCR Sensing Circuit
In this circuit, the voltage across the CSENSE exactly equals the voltage across RDCR when Equation 9 is true.
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L
RDCR
= CSENSE ´ REQ
where
•
REQ =
REQ is the series/parallel combination of RSEQU, RNTC, RSERIES and RPAR
(9)
RP _ N
RSEQU + RP _ N
RP _ N =
(10)
RPAR ´ (RNTC + RSERIES )
RPAR + RNTC + RSERIES
(11)
CSENSE should be a capacitor type which is stable over temperature. Use X7R or better dielectric (C0G
preferred).
Since calculating these values by hand is difficult, TI has a spreadsheet using the Excel Solver function available
to calculate them. Contact a local TI representative to get a copy of the spreadsheet.
In
•
•
•
•
•
this design, the following values are input to the spreadsheet:
L = 0.36 µH
RDCR = 0.825 mΩ
Load Line, RIMVP = -1.9 mΩ
Minimum overcurrent limit = 112 A
Thermistor R25 = 100 kΩ and "B" value = 4250 kΩ
The spreadsheet then calculates the OCP (overcurrent protection) setting and the values of RSEQU, RSERIES,
RPAR, and CSENSE. In this case, the OCP setting is the resistor value selection of 56 kΩ from COCP-I to GND and
GOCP-I to GND. The nearest standard component values are:
• RSEQU = 17.8 kΩ;
• RSERIES = 28.7 kΩ;
• RPAR = 162 kΩ
• CSENSE =33 nF
Note the effective divider ratio for the inductor DCR. The effective current sense resistance (RCS(eff)) is shown in
Equation 12.
RP _ N
RCS(eff ) = RDCR ´
RSEQU + RP _ N
where
•
RP_N is the series/parallel combination of RNTC, RSERIES and RPAR.
RGDROOP =
RCS(eff ) ´ A CS
RLL ´ GM
=
(12)
0.66mW ´ 12
= 4.12kW
3.9mW ´ 0.497mS
(13)
RCS(eff) is 0.66 mΩ.
Step Seven: Set current monitor (IMON) setting resistor.
After the OCP selection resistor is selected in Step 6, the IMON is set by the resistor from CIMON to COCP-I
(RCIMON) and GIMON to GOCP-I (RGIMON). Based on Equation 2 and Equation 3,
RCIMON = 71.5 kΩ and RGIMON = 309 kΩ
Step Eight: Set the load line.
The load-line for CPU channel is set by the resistor, RCDROOP from CCOMP to VREF. The load-line for GPU
channel is set by the resistor, RGDROOP from the GCOMP pin to VREF. Using the Equation 1, the droop setting
resistors are calculated in Equation 14 and Equation 15.
RCS(eff ) ´ A CS
0.66mW ´ 12
=
= 8.45kW
RCDROOP =
RLL ´ GM
1.9mW ´ 0.497mS
(14)
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RGDROOP =
www.ti.com
RCS(eff ) ´ A CS
RLL ´ GM
=
0.66mW ´ 12
= 4.12kW
3.9mW ´ 0.497mS
(15)
Step Nine: Programming the CTHERM and GTHERM pins.
The CTHERM and GTHERM pins should be set so that the resistor divider voltage would be greater than 458
mV at normal operation. For VR_HOT to be asserted, the xTHERM pin voltage should fall below 458 mV. The
NTC resistor from xTHERM to GND is chosen as 100 kΩ with a B of 4250K. With this, for a VR_HOT assertion
temperature of 105°C, the resistor from xTHERM to VREF can be calculated as 15.4 kΩ.
Step Ten: Determine the output capacitor configuration.
For the output capacitor, the Intel Power Delivery guideline gives the output capacitor recommendations. Using
these devices, it is possible to meet the load transient with lower capacitance by using the OSR and USR
feature. Eight settings are available and this selection has to be tuned based on transient measurement.
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PCB LAYOUT GUIDELINE
SCHEMATIC REVIEW
Because the voltage and current feedback signals are fully differential it is a good idea to double check their
polarity.
1. CCSP1/CCSN1
2. CCSP2/CCSN2
3. CCSP2/CCSN2
4. GCSP/GCSN
5. VCCSENSE to CVFB/VSSSENSE to CGFB (for CPU)
6. VCCGTSENSE to GVFB/VSSGTSENSE to GGFB (for GPU)
Also, note the order of the current sense inputs on Pin 4 to Pin 9 as the second phase has a reverse order.
CAUTION
Separate noisy driver interface lines from sensitive analog interface lines: (This is the
MOST CRITICAL LAYOUT RULE)
37 VBAT
38 CDH2
39 CBST2
40 CSW2
41 CDL2
42 PGND
43 V5DRV
44 CDL1
45 CSW1
46 CBST1
47 CDH1
48 V5
The TPS51640A, TPS59640, and TPS59641 make this as easy as possible. The pin-out arrangement for
TPS51640A is shown in Figure 71. The driver outputs clearly separated from the sensitive analog and digital
circuitry. The driver has a separate PGND and this should be directly connected to the decoupling capacitor that
connects from V5DRV to PGND. The thermal pad of the package is the analog ground for these devices and
should NOT be connected directly to PGND (Pin 42).
CTHERM 1
36 CPWM3
COCP-I 2
35 CSKIP
CIMON 3
34 GPWM
CCSP1 4
33 GSKIP
CCSN1 5
32 GTHERM
CCSN2
6
CCSP2
7
GND
31 GOCP-I
30 GIMON
CCSP3 8
29 GCSP
CCSN3 9
28 GCSN
CCOMP 10
27 GCOMP
Drivers
14
15
16
17
18
19
20
21
22
23
24
V3R3
VR_ON
CPGOOD
VCLK
ALERT
VDIO
VR_HOT
SLEWA
GPGOOD
GF-IMAX
25 GGFB
VREF
CGFB 12
13
26 GVFB
CF-IMAX
CVFB 11
Analog
Digital
Power
Figure 71. TPS51640A Pin-out Arranged by Pin Function
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Given the physical layout of most systems, the current feedback (xCSPx, xCSNx) may have to pass near the
power chain. Clean current feedback is required for good load-line, current sharing, and current limiting
performance of these devices, so please take the following precautions:
• Make a Kelvin connection to the pads of the resistor or inductor used for current sensing. See Figure 72 for a
layout example.
• Run the current feedback signals as a differential pair to the device.
• Run the lines in a quiet layer. Isolate them from noisy signals by a voltage or ground plane.
• Put the compensation capacitor for DCR sensing (CSENSE) as close to the CS pins as possible.
• Place any noise filtering capacitors directly underneath these devices and connect to the CS pins with the
shortest trace length possible.
Noisy
Quiet
Inductor
Outline
LLx
VCORE
CSNx
CSPx
RSEQ
Thermistor
RSERIES
UDG-11038
Figure 72. Make Kelvin Connections to the Inductor for DCR Sensing
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Minimize High-Current Loops
Figure 73 shows the primary current loops in each phase, numbered in order of importance.
The most important loop to minimize the area of is Loop 1, the path from the input capacitor through the high and
low side FETs, and back to the capacitor through ground.
Loop 2 is from the inductor through the output capacitor, ground and Q2. The layout of the low side gate drive
(Loops 3a and 3b) is important. The guidelines for gate drive layout are:
• Make the low-side gate drive as short as possible (1 inch or less preferred).
• Make the DRVL width to length ratio of 1:10, wider (1:5) if possible.
• If changing layers is necessary, use at least two vias.
VBAT
CB
CIN
1
Q1
4b
DRVH
L
4a
VCORE
LL
2
CD
3b
Q2
COUT
DRVL
3a
PGND
UDG-11040
Figure 73. Major Current Loops to Minimize
Power Chain Symmetry
The TPS51640A, TPS59640, and TPS59641 do not require special care in the layout of the power chain
components. This is because independent isolated current feedback is provided. If it is possible to lay out the
phases in a symmetrical manner, then please do so. The rule is: the current feedback from each phase needs to
be clean of noise and have the same effective current sense resistance.
Place analog components as close to the device as possible.
Place components close to the device in the following order.
1. CS pin noise filtering components
2. xCOMP pin compensation components
3. Decoupling capacitors for VREF, V3R3, V5
4. xTHERM filter capacitor
5. xIMON capacitor, resistors
6. xF-IMAX resistors
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Grounding Recommendations
These devices have separate analog and power grounds, and a thermal pad. The normal procedure for
connecting these is:
• The thermal pad is the analog ground.
• DO NOT connect the thermal pad to Pin 42 directly as Pin 42 is the PGND which is the Gate driver
Ground.
• Pin 42 (PGND) must be connected directly to the gate driver decoupling capacitor ground terminal.
• Tie the thermal pad (analog ground pin) to a ground island with at least 4 small vias or one large via.
• All the analog components can connect to this analog ground island.
• The analog ground can be connected to any quiet spot on the system ground. A quiet area is defined as a
area where no power supply switching currents are likely to flow. This applies to both the VCORE regulator and
other regulators. Use a single point connection from analog ground to the system ground
• Make sure the low-side FET source connection and the decoupling capacitors have plenty of vias.
Decoupling Recommendations
•
•
•
Decouple V5IN to PGND with at least a 2.2 µF ceramic capacitor.
Decouple V5 and V3R3 with 1 µF to AGND with leads as short as possible,
VREF to AGND with 0.33 µF, with short leads also
Conductor Widths
•
•
•
•
46
Follow Intel guidelines with respect to the voltage feedback and logic interface connection requirements.
Maximize the widths of power, ground and drive signal connections.
For conductors in the power path, be sure there is adequate trace width for the amount of current flowing
through the traces.
Make sure there are sufficient vias for connections between layers. A good guideline is to use a minimum of 1
via per ampere of current.
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PACKAGE OPTION ADDENDUM
www.ti.com
13-Jun-2012
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package
Drawing
Pins
Package Qty
Eco Plan
(2)
Lead/
Ball Finish
MSL Peak Temp
(3)
TPS51640ARSLR
ACTIVE
VQFN
RSL
48
2500
Green (RoHS
& no Sb/Br)
CU NIPDAUAGLevel-2-260C-1 YEAR
TPS51640ARSLT
ACTIVE
VQFN
RSL
48
250
Green (RoHS
& no Sb/Br)
CU NIPDAUAGLevel-2-260C-1 YEAR
TPS59640RSLR
ACTIVE
VQFN
RSL
48
2500
Green (RoHS
& no Sb/Br)
CU NIPDAUAGLevel-2-260C-1 YEAR
TPS59640RSLT
ACTIVE
VQFN
RSL
48
250
Green (RoHS
& no Sb/Br)
CU NIPDAUAGLevel-2-260C-1 YEAR
TPS59641RSLR
ACTIVE
VQFN
RSL
48
2500
Green (RoHS
& no Sb/Br)
CU NIPDAUAGLevel-2-260C-1 YEAR
TPS59641RSLT
ACTIVE
VQFN
RSL
48
250
Green (RoHS
& no Sb/Br)
CU NIPDAUAGLevel-2-260C-1 YEAR
Samples
(Requires Login)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
13-Jun-2012
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
TPS51640ARSLR
VQFN
RSL
48
TPS51640ARSLT
VQFN
RSL
TPS59640RSLR
VQFN
RSL
TPS59640RSLT
VQFN
TPS59641RSLR
TPS59641RSLT
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
2500
330.0
16.4
6.3
6.3
1.5
12.0
16.0
Q2
48
250
180.0
16.4
6.3
6.3
1.5
12.0
16.0
Q2
48
2500
330.0
16.4
6.3
6.3
1.5
12.0
16.0
Q2
RSL
48
250
180.0
16.4
6.3
6.3
1.5
12.0
16.0
Q2
VQFN
RSL
48
2500
330.0
16.4
6.3
6.3
1.5
12.0
16.0
Q2
VQFN
RSL
48
250
180.0
16.4
6.3
6.3
1.5
12.0
16.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPS51640ARSLR
VQFN
RSL
48
2500
367.0
367.0
38.0
TPS51640ARSLT
VQFN
RSL
48
250
210.0
185.0
35.0
TPS59640RSLR
VQFN
RSL
48
2500
367.0
367.0
38.0
TPS59640RSLT
VQFN
RSL
48
250
210.0
185.0
35.0
TPS59641RSLR
VQFN
RSL
48
2500
367.0
367.0
38.0
TPS59641RSLT
VQFN
RSL
48
250
210.0
185.0
35.0
Pack Materials-Page 2
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