U PD372_Floppy_Disk_Controller_Addendum_Apr77 PD372 Floppy Disk Controller Addendum Apr77
User Manual: uPD372_Floppy_Disk_Controller_Addendum_Apr77
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~EC IlcrOcOlputers, Inc. }LPD372 ADDENDUM TO FLOPPY DISK CONTROLLER USERS' MANUAL FOR MINIFLOPPyTM APPLICATIONS TM - Shugart Associates Five Militia Drive/Lexington, Massachusetts 02173 Telephone (617) 862-6410 Telex 92-3434 TABLE OF CONTENTS INTRODUCTION 2 MINIFLOPPY INTERFACE SIGNALS 3 RECORDING FORMAT 6 DATA CONDITIONER 9 SAMPLE CONTROLLER DESIGN 11 Hardware 11 Software 13 1 INTRODUCTION The discussion and design shown in this Addendum is dedicated to the MinifloppyTM Diskette Storage Drive. This drive is somewhat different, both electrically and mechanically, from the standard floppy disk drives found throughout the industry. The Minifloppy is smaller, less expensive, and is based upon the same floppy disk drive technology as the standard floppy. However, its data transfer rate is half as fast and its total data storage capacity is approximately one-third. This design uses a single uPD372 Floppy Disk Controller to control a pair of Minifloppies. The interface to the floppies has been configured so as to allow overlap-seeks to be programmed. If only a single drive is used or if overlap-seeks are not required, then two or three logic Ie's may be removed from this design. The controller's architecture remains the same as in the standard floppy design shown in the uPD372 Users' Manual. Before proceeding into the design of this controller, the uPD372 Users' Manual should be read. All the basic concepts and characteristics of the uPD372 are explained in this document, and it will be assumed that the reader is familiar with them. For clarity in this document the uPD372 Users' Manual will be referred to as Users' Manual and this document referred to as the Addendum. TM -- Shugart Associates 2 MINIFLOPPY INTERFACE SIGNALS There are several signals which have been deleted in the Minifloppy as well as several new signals. These are summarized below: Deleted Signals (Used only on Standard Floppy) New Signals Head Load Index/Sector write Fault Drive Select I write Fault Reset Drive Select 2 Low Current Drive Select 3 Sector Motor ON Index Ready The Head Load signal has been deleted in the Minifloppy. The head is loaded concurrently with the Motor ON signal. write Fault and Write Fault Reset which were tests of the Floppy's status prior to attempting to write a diskette, have both been eliminated. Many standard floppies (IBM compatible) have a Low Current signal which allows the write current in the recording head to be decreased on tracks 44-76 -- this signal has been eliminated. If a hard sector recording format is used, the standard floppies provided separate signal outputs for both Sector and Index. The Minifloppy requires that the user separate these signals (this is usually done with a one-shot circuit). The READY command in the standard floppy indicated to the controller that a diskette had been inserted, the door was closed, and that the diskette was spinning; this signal has also been eliminated. Three separate device select lines are provided on the Minifloppy and the appropriate one is selected by the use of hardware straps in the drive. This allows a maximum of three drives to be selected without additional decoding hardware. The Minifloppy uses a dc motor for rotating the diskette, a separate signal called MOTOR ON is used for turning the motor on. In order to increase the longevity of the motor, software has been incorporated in the controller so that two seconds after the last program instruction, the motor is shut off. The following figure shows a typical interface connection between the controller and the Minifloppy. 3 FLAT RIBBON OR TWISTED PAIR MAX 10 FEET MINI FLOPPY CONTROLLER Jl 7- 7 9 8 II 10 13 12 15 14 17 16 19 18 21 2C 23 22 25 2A 27 2':: 29 28 3'" INDEX/SECTOR 8 9~ DRIVE SELECT 1 10 11~ DRIVE SELECT 2 12 13~ DRIVE SELECT 3 14 15~ MOTOR ON 16 17~ DIRECTION SELECT 18 19-· STEP 20 21-~ WRITE DATA 22 23_ WRITE GATE 24 25_ TRACK 00 26 27_ WR ITE PROTECT 28 29 ----4 READ DATA 30 'W J2 POWER SUPPLY ...L - '" +5 VDC X +5 RETURN ;:: +12 VDC I +12 RETURN 4 3 ----4 1 2 ----4 -- ITI77 ACGND ~ - nfn b FRAME GND TWISTED 'PAIR Figure 1 -- Controller/Minifloppy Interface From the detail schematic (Figure 6) it can be seen that the functions of the following signals corning out of the uPD372 have been changed to execute the new commands. Standard Floppy Command 372 Pin Number Minifloppy Command (WFR) write Fault Reset 23 Motor ON (Device #1) (LCT) Low Current 22 MQtor ON (Device #2) 4 The functional performance of these signals is changed in software and requires no change to the uPD372 hardware. The uPD372 has two pairs of device select lines, an A pair and a B pair. In this application these lines have been configured to control Qnly two Minifloppies. The A pair (UA0 and UAl) are used as follows: UA0 - Select Read/Write Electronics in Drive #1 UAI - Select Read/Write Electronics in Drive #2 The B pair (UB0 and UBI) are used as follows: UB0 - Select Motion Control Electronics in Drive #1 UBI - Select Motion Control Electronics in Drive #2 Software constraints have been incorporated so that: • Only one Drive may be Reading or Writing at a time. • Only one Drive may be Stepping IN or OUT at a time. However, it is possible to Read or Write on one Drive while stepping on the other. This is done by selecting UA0 • UBI or UAI • UB0. When two Minifloppies are used, connector Jl on the controller should be connected to Drive #1 and J2 to Drive #2, (Radial busing to the Drives). This should be done in order to keep the hardware decoding on IC's U50, U5l, U53 and U17 the same as the software listing. 5 RECORDING FORMAT The software listing shown at the end of this Addendum and the discussion which follows is for a Soft Sectored format. However, if the user wishes to use Hard Sectoring, he may do so by simply changing the software (the uPD372 is not a limiting factor to hard sectoring). Soft Sectoring has 35 Tracks per diskette and 18 Sectors per Track. All 35 Tracks are formatted in exactly the same manner and follow the standard IBM format fairly closely. Figure 3 shows the recording format which will be used in this Minifloppy Addendum. Data which is recorded on the diskette is done so by using frequency encoding. This technique requires that each data bit recorded on the diskette has an associated clock bit recorded with it. Data which is written or read back from the diskette has the form shown in Figure 2. CDC' --1l n~ CDC __~n~_________n~__~n rL-- I I I I I I ~4111~ t~M I I I 1~14_- I 8U1 --~~ t800.. I l I .........- BIT CELL----.... ' . - - liT CELL-----t.......t - - - liT CELL---NO. 1 NO. I NO. I FIGURE 2 FREQUENCY ENCODED DATA The encoded bit pattern shown in Figure 2 is binary 101. Refer to Figures 7 and 8 (Page 27) of the Users' Manual and note that the bit cell times shown are exactly 1/2 as long as those shown in this Addendum. Flip-flop U58(A) has been added in series with the Write Clock Signal on the uPD372 (pin 13) in order to divide the clock rate in half, making it compatible with the Minifloppy requirements. Three special identification marks (Address Marks), are used in the Minifloppy, (four Address Marks are used in the Standard Floppy) . MINIFLOPPY ADDRESS MARKS ID Address Mark Data Address Mark Deleted Data Address Mark When the Deleted Data Address Mark is written at the beginning of a data field, then the entire contents of the data field will be ignored. Figure 4 shows the recording format for these special codes. 6 200ms --------------------------------------------------~~. Ie I I INOE~ I I I ,, SECTOR 01 \ \ \ , \ \ I , I \ \ \ \ \ ; , SECTOR 03 SECTOR 02 SECTOR 17 --- --- ----- --- ---- -- -- ----- -i N ~~ ~I d •~ ~ c i SECTOR 18 ' .... ......... , >, ~tOS InEI ",," . I I N a..--' .•I I . ~ i ---- __ --- --- -, i ~ \ SECTOR 01 l IIIIYTES DATA I I I I.-- INOIl .»---iMM......- I I I I I I I t - - I.al.. ... I I -0.. 'IELI.....~.....- - - - - - - - DATA FIELD - - - - - - - - - I I ..lIoIe..._- POST DATA , ..... UP I 1 I 10 RECORD ----...... ..O.UtIII ... J J IIP.____et I I 0.641 . . _ ...... 11-_ _ _ _ _ _ _ _ _ _ _ '.SlMI - - - - - - - - - -............- - - 1.144. I • I I I I ~~~--------------------------------------- 10.~.. -----------------------------------------~ FIGURE 3 MI N I FLOPPY RECORDING FORMAT ID ADDRESS M"RK 8YTE BINARY ~:"IESENTATION CLOCK8ITS HEXADECIMAL QATA 81TS :~~RESENT ATlON CLOCK BITS 10 ADDRESS MARK DATA AODflE SSMARK 8YTE BINARY REPRESENTATION Of HEXADECIMAL CLOCK 81TS OATA81TS ~~PRESENTATION CLOCK 81TS DATA ADDRESS MARK BINARY REPRESENTATION 'Of: HExADECIMAL :~RESENTATION DELETED OATA ADDRESS MARK 7 FIGURE 4 ADDRESS MARKS 8 DATA CONDITIONER The uPD372 contains the electronic circuitry for separating the Data and Clock pulses out of the Read Data signal. However, the uPD372 does require some external circuitry so that its internal registers which are clocked on the trailing ed~e of 02 will be presented the proper data. The external circuitry for accomplishing this is called a "Data Conditioner". The floppy disk's Read Signal is asynchronous with the microprocessors' clocks. The Data Conditioner function is to stretch the narrow Read Signal pulses from the floppy so that they will overlap the microprocessor's clock interval, allowing them to be strobed into the uPD372. The Data Conditioner required for the Minifloppy is much simpler than that required for the Standard floppies. The reason being that the bit cell time is twice as long, namely 8us vs. 4us; thereby eliminating the need for double buffering of the data. The conditions and requirements mentioned on Pages 26, 27 and 28 of the Users' Manual are still applicable. Figure 5 shows the schematic and timing diagram for a Minifloppy Data Conditioner. The Read Data signal corning from the Minifloppy consists of a string of pulses representing flux reversals on the diskette. U55A is a retriggerable one-shot which times out after 5.8us, detecting the absence of either a data or clock pulse in the Read Data. The Q output of U55A is used as the Read Data input to the uPD372 (RD). The "AND" gate (7408) and the associated RC network on one of its inputs, detects negative going transitions at the output of the RD one-shot. The pulses at point'A indicate missing clock or data information during each data cell. These pulses are "OR'd" with the Read Data (7432) producing a pulse stream which contains two pulses per data cell, point B. U55B converts this pulse stream into pulses whose widths are uniform (750ns wide), which may then be sent to the Read Clock input of the uPD372 (RCK). It should be noted that two (2) RCK pulses are always generated per data cell, even when clock or data pulses are missing. The 02 clock pulses (which drive both the microprocessor and uPD372) occur at a 500ns rat~, thereby, dictating that the RCK pulses should be 750ns wide for an optimum sampling rate of once per 02 pulse. Once a positive transition of RCK is sensed by 02, the following 02 pulse, clocks the logic level of RD into the uPD372's internal shift register. When the user implements either this or his own Data Conditioner circuit, it is important that he follow the timing constraints outlined in this section of the manual. 9 +5V +5V 220.n. UPl RCK 0 74123 750n. :tIOOn. READ DATA------~----~~~_;C:::::::::::::::::~ ________________________________ RD ~ CELL DATA - - - . , I IC READ DATA --1l I I I I I RD --.J : I I I I I RCK .. I I 0 0 J I I I I I I I I I I D n I I I I I J I I I I IC n n D n J r1 0 n I, I, MISSING CLOCK PULSES ,.,J D n ,I I, n I I I I I LJ -.: I I . - 5.8us I I I I I I I I I I I I I I I I I n I I I I I I I I "'750ns I I I I C I n LJ LJ I: II II II II II II II I I I I I I I I I d --' 14-~ lOOn. II II I n II II II II II "--Il n II II II II n FIGURE 5 MINI-FLOPPY DATA CONDITIONER n II fLJl "--Il n ~ rl SAMPLE CONTROLLER DESIGN Hardware A Controller design is shown in Figure 6. The Controller is architectured in exactly the same manner as shown in the Users' Manual (reference Pages 31-39). The connections to the Minifloppies are done through connectors Jl and J2 on the right-hand side of the schematic. This design handles only two drives. However, four drives could be accommodated by simply decoding the UA0 and UAI as well as the UB0 and UBI lines into two sets of four lines. The figure below shows how this may be achieved. t-------A1 UAe UAl -------1 2 TO 4 LINE DECODER ....- - - - - - A 2 t------ A3 READ/WRITE SELECT LINES .....- - - - - A 4 1 - - - - - - - - 11 U•• 2 TO 4 1 - - - - - - - - 82 Ul1 LINE DECODER 1 - - - - - - - - 83 MOTION CONTROL SELECT LI NES 1--------14 Figure 7 -- Multiple Drive Decoding The program for this Controller is contained in a single lK x 8 bit electrically erasable PROM (Part Number uPD458). However, once the user is confident of his program, a custom·ROM (uPD2308) could be made, reducing the parts' costs. The ROM contains the Drives' Reading, Writing, Formatting and Disk Handling Routines. 11 U50 74368 17 INT UP3 DB7 37 DB6 36 DB5 35 DB4 34 DB3 33 DB2 DB5 DB4 OB3 17 19 DB2 DB7 DB6 DB5 DB4 DB3 082 OBI DB0 DB7 DB6 DB5 DB4 DB3 082 OBI DB0 A9 A8 A7 A6 A5 A4 A3 A2 At A0 U2 A9 A8 A7 A6 A5 NOTES ta2 2 lA 4 H-A9~--------------------------~ 2A 6 H-A8~--------------------------~~ 3A 10 H-A7~--------------------------~LI 12 4A H-A6.---------------------------~~ 5A H-AIO.---------------------------~~ IS C-HLDA----------~~~ r- DB5 A3 A2 Al A0 PROM uPD2308 ROM 74365 U5 DB6 A4 uPD458 r----.. DB7 } U3 DB4 A7 7 A6·6 A5 5 A4 21 A3 I A2 2 Al 3 4 A0 VCC 22 A7 A6 A5 A4 A3 A2 Al A0 DB3 DB2 U4 OBI DB0 A7 A6 A5 A4 A3 A2 Al A0 G2 74125~ OBI uPD2101AL-4 uPD2101AL-4 lK BYTES RAM 256 BYTES RAM "'" G2 ~ 2 H-A5.---------------------------~~ lA 4 2A H-A4l---------------------------~~ 6 10 12 14 --ct= H-A3.-----------------------------~ 3A H-A2~--------------------------~~ 4A H-AI.---------------------------~ 5A H-A0.---------------------------~ ~ ~ - o t!) a w a a::o-.j STEP U'(I 20 TRACK 00 9 7 ~ 6 4 ~ 5 U7 -26 ~ 2 TRACK 00 26 STEP 20 ~ MOTOR ON ~7 DIRECTION 7416 DIRECTION ~7 MOTOR ON 16 - 18 I 7416 18 16 Jl 2200 330 0 r!L UPI4 ~UPI3 UP4....!. UP5 2 UP6 -2. UI5 r!L UPI2 r!L UPII rll- UPIO flL UP9 UP7.2 UPS.....§. RES. NETWORK SPRAGUE NO.916CI3IXSTR PULL UP SOURCES CHIP LIST PART NO. QTY 1 uP0372D 2 uPD21OIAL-4 1 uP02308 1 2 RS0-RSI MUST BE STABLE FROM 150 .. BEFORE TO IOns AFTER THE TRAILING EDGE OF 01.1SEE uPD372 SPECIFICATIONSI flF U32 SYNCRONIZES RS0,RSI CHANGES WITH THE LEADING EDGE OF 02. UNLESS OTHERWISE SPECIFIED ALL RESISTORS 114W,!5% 1 1 7416 1 7430 2 4 7432 7474 2 74123 3 74125 74157 4 uPB8216 1 uPB8224 uPB8238 1 35 FIGURE 6-uPD372D DUAL MINI-FLOPPY DISC CONTROLLER 3-22-71 12 74365 uP080S0A 2 3 C-INTA 7400 7404 7408 1 6. 12 24 WRITE PROTECT 1 10 UP3...l. tl 220n. ~ WRITE DATA UP2...1. Pf - WRITE GATE UPI-L 15K • 511< 8 30 +5V y 5V~ ~ 28 INDEX/SECTOR UPI4 A ~7 ~16 22 U5374368 15 II 9 24 WRITE PROTECT 9 Ui 7 ~J II ~33 " 5 ~A 9 U26B 74123 250., :50 .. UP3 "" 3 ~ 6 RO~ UP2 NOTES 1. THE HOST PROCESSOR AND CONTROLLER PROCESSOR ARE BOTH uPD8080A'S. HOST PROCESSOR SIGNALS ARE PREFiXED WITH H-. CONTROLLER PROCESSOR SIGNALS ARE PREFIXED WITH C-. 2. THE HOST HAS DIRECT MEMORY ACCESS INTC THE CONTROLLER-NOT VICE VERSA. 3. HOST ADDRESS SIGNALS DO NOT REACH THE. CONTROLLER MEMOR IES UNTIL C-HLDA IS GRANTED DURING A HOST ACCESS. THE HOST IS THEN IN A TW STATE. ONE SHOT U26A KEEPS THE H-READY LINE LOW (TO MAINTAIN ADDRESS AND DATA PATHS) FOR AT LEAST THE 450n5 MEMORY ACCESS TIME. 4. H-WR IS ALREADY PRESENT DURING A WRITE CYCLE WHEN THE HOST ADDRESS SIGNALS REACH THE CONTROLLER MEMORIES (HOST IS IN A TW STATE AT C-HLDAI. THIS DELAY CIRCUIT KEEPS THE CONTROLLER RAM R/W SIGNAL HIGH FOR THE REQUIRED TAW TIME. SEE uPD210lAL SPECIFICATION. S. THIS CIRCUIT JAMS AN "FB" (HEX) CODE (ENABLE INTERRUPT) ONTO THE DATA BUS DURING C-INTA. 2Y 5 WFR +5V rO 74365 SID U58A 7474 UP2 R Q U55 74123 UPl ~'I~~'! G2 U12 U~12 10 GATt: WRITE DATA U'{3 USI 74368 RESET 01 +5V ~12S ~ 10 W/R C RQ UP2 U23 74125 ~ wRlf~ OS U~2 )C UZ8A 7474 ~ 9 ';;04 ~WCK 15 01 02 23 24 READY WAIT C-HOLDOC-HLDA pJfI U~2 )C 20K L_....__..~.,:;r-I uPB8216 I 41 42 RQ DB3 13 DB2~10~--------------------------------------------------~ D81~£-6--------------------------------------------~rt DB0 3 ~----------------------------------------------~_r~ OlEN ,.,. :J740~ '--.l--C-IIO R UIO 3 2 U~2 uPB8216 r.!L 6 SOS 26 LCT T 02{TTLl 6 021TTLI L-li~X~T.~AL~2~~S~Y~St~B~7------------------------------------~~~!.____.J I L ___ ..J ! RrnN l H-DB4. = SYSRST U7 ~ ?8 +12V Q 01 RESET 02 013 H-DB7~1------------------------__.~ 003 i ~ H-DB6 II 012 ~D02 H-DB5 i ~ 011 l ~ DOl i U27B 7474 Q RDYIN 7~ - U32B 7474 UP2 NOTE 6 01 02 13 HOLD SVSRST 9 6 + 12V -':<"1 5V 8 + -"- GND I I DSQ uPB8224 UPI \t RESET )C U27A 7474 Q R ~ C-HOLO DSQ ~ /;!!3 R Q _=:J740~~ C-INTA )C UB0 3 7 RS2 RS1 ~1. 7 13 C 13 4 UI4 uPD372 UAI ~ ~ U32A UP2 7474 NOTE 6 C-lNTA C-1I0 W 2~0:Pf ~g~~50nsl UP1 C-HLDA I 6.8K U26A 74123 -5V R II C-J10 W C-I/O R H-AI3 t---------i U22 7404 U21 H-A12.:;;Of:::!404 7430}b-~H.:..-..!.(E::::O~0::..:0::..-..::E:..:.7.:..FF:...;1:...._______f_--__f----...., H-Al1~ ....ll ~ U25 74125 ~ 6A H-AI41------~ GNO ~ DEVICE SELECT! II 5 : 5.1K WD -t>o-n 8 DB0 22- 4 74125 " ' - - H-AI5 t---------, H-0Ie~ ~ U25 AO iHYNC~~~ 4A 5A Q2 (TTL) I u w lOX ~ +5V ~ Gi rn Al UI7 741~ H-READY r:
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