Vivado Design Suite: AXI Reference Guide (UG1037) Ug1037
ug1037-vivado-axi-reference-guide
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- Vivado Design Suite: AXI Reference Guide
- Revision History
- Table of Contents
- Ch. 1: Introducing AXI for Vivado
- Ch. 2: AXI Support in Xilinx Tools and IP
- Ch. 3: Samples of Vivado AXI IP and Xilinx Processors
- Overview
- AXI Infrastructure IP Cores
- Xilinx AXI SmartConnect and AXI Interconnect IP
- AXI SmartConnect IP
- AXI4-Stream Interconnect Core IP
- AXI Virtual FIFO Controller
- The AXI4-Stream interconnect can also perform local FIFO buffering, clock conversion, and width conversion to adapt the interface of the stream endpoints to the data path of the virtual FIFO controller and the AXI memory controller
- DataMover
- AXI4 DMA
- Simulating IP
- Using Debug and IP
- Zynq UltraScale+ MPSoC Processor Device
- Zynq-7000 All Programmable SoC Processor IP
- MicroBlaze Processor
- Ch. 4: AXI Feature Adoption in Xilinx Devices
- Ch. 5: Migrating to Xilinx AXI Protocols
- Ch. 6: AXI System Optimization: Tips and Hints
- Introduction
- AXI System Optimization
- AXI4-based Vivado Multi-Ported Memory Controller: AXI4 System Optimization Example
- Common Pitfalls Leading to AXI Systems of Poor Quality Results
- Optimizing AXI on Zynq-7000 AP SoC Processors
- Ch. 7: AXI4-Stream IP Interoperability: Tips and Hints
- Appx. A: AXI Adoption Summary
- Appx. B: AXI Terminology
- Appx. C: Additional Resources and Legal Notices