Spartan 6 FPGA Configuration User Guide (UG380) Ug380 Spartan6
User Manual:
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- Spartan-6 FPGA Configuration
- Revision History
- Table of Contents
- About This Guide
- Ch. 1: Configuration Overview
- Overview
- Design Considerations
- FPGA Configuration Data Source
- Master Modes
- Slave Modes
- JTAG Connection
- The Basic Configuration Solution
- The Low-Cost Priority Solution
- The High-Speed Priority Option
- Conforming to PCI Link Activation Requirements
- Single and Multiple Configuration Images
- MultiBoot /Safe Update
- Required I/O Voltages
- Nonvolatile Data Storage
- FPGA Density Migration
- Production Lifetime
- Protecting the FPGA Bitstream against Unauthorized Duplication
- Loading Multiple FPGAs with the Same Configuration Bitstream
- Configuration Factors
- Ch. 2: Configuration Interface Basics
- Ch. 3: Boundary-Scan and JTAG Configuration
- Ch. 4: User Primitives
- Ch. 5: Configuration Details
- Configuration Pins
- Configuration Data File Formats
- Bitstream Overview
- Generating PROM Files
- Configuration Sequence
- Bitstream Encryption
- eFUSE
- Configuration Memory Frames
- Configuration Packets
- Packet Types
- Configuration Registers
- CRC Register
- FAR_MAJ Register
- FAR_MIN Register
- FDRI Register
- FDRO Register
- MASK Register
- EYE_MASK Register
- LOUT Register
- CBC_REG Register
- IDCODE Register
- CSBO Register
- Command Register (CMD)
- Control Register 0 (CTL)
- Status Register (STAT)
- Configuration Options Register (COR1 and COR2)
- Suspend Register (PWRDN_REG)
- Frame Length Register
- Multi-Frame Write Register
- Configuration Watchdog Timer Register
- HC_OPT_REG Register
- GENERAL Registers 1, 2, 3, 4, and 5
- MODE Register
- CCLK_FREQ Register
- PU_GWE Register
- PU_GTS Register
- Boot History Status Register (BOOTSTS)
- SEU_OPT Register
- Bitstream Composition
- Default Initial Configuration Process
- Spartan-6 FPGA Unique Device Identifier (Device DNA)
- Bitstream Compression
- Ch. 6: Readback and Configuration Verification
- Preparing a Design for Readback
- Readback Command Sequences
- Verifying Readback Data
- Ch. 7: Reconfiguration and MultiBoot
- Ch. 8: Readback CRC
- Ch. 9: Advanced Configuration Interfaces
- Ch. 10: Advanced JTAG Configurations