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User Manual: Datasheets uP6305, uP6305AFA9, uP6305AQDD, uP6305ASU8.

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uP6305

Preliminary

1MHz, 2.0A, High-Eefficiency
Synchronous-Rectified Buck Converter
Features

General Description
The uP6305 is a high efficiency synchronous-rectified buck
converter with internal power switches. Fixed 1MHz PWM
operation allows possible smallest output ripple and
external component size. With high conversion efficiency
and small package, the uP6305 is ideally suitable for
portable devices and USB/PCIE-based interface cards
where PCB area is especially concerned.
With internal low RDS(ON) switches, the uP6305 is capable
of delivering 2.0A output current over a wide input voltage
range from 2.5V to 5.5V. The output voltage is adjustable
from 0.6V to VIN by a voltage divider. Other features include
internal soft-start, chip enable, overvoltage, under-voltage,
over-temperature and over-current protections. The uP6305
is available in a space-saving WQFN3x3-16L,
WLCSP1.5x1.5-9B or PSOP-8L packages.

Ordering Information

Battery-Powered Portable Devices
MP3 Players
Digital Still Cameras

2.5V to 5.5V Input Voltage Range

Guaranteed 2.0A Output Current
+/- 1.5%)
Accurate Reference: 0.6V (+

Up to 95% Conversion Efficiency

Integrated Low RDS(ON) Upper and Lower
Ω and 75mΩ
Ω
MOSFET Switches: 85mΩ

Current Mode PWM Operation

100% Maximum Duty Cycle for Lowest Dropout

No Schottky Diode Required

Over-Temperature and Over-Current Protection

RoHS Compliant and 100% Lead (Pb)-Free

Adjustable Output from 0.6V to VIN

Low Quiescent Current

Fixed Frequency: 1MHz
Internal Soft-Start
Over-Voltage and Under-Voltage Protection
WQFN3x3-16L, WLCSP1.5x1.5-9B or PSOP-8L
Packages

Applications

Wireless and DSL Modems
Personal Information Appliances

802.11 WLAN Power Supplies

FPGA/ASIC Power Supplies

Dynamically Adjustable Power Supply for
CDMA/WCSMA Power Amplifiers

USB-Based xDSL Modems and Other Network
Interface Cards

Point-of-Load Regulation

Order Number

Package Type

uP6305AQDD

WQFN3x3-16L

uP6305AFA9

WLCSP1.5x1.5-9B

uP6305ASU8

PSOP-8L

Remark

Note: uPI products are compatible with the current IPC/
JEDEC J-STD-020 requirement. They are halogen-free,
RoHS compliant and 100% matte tin (Sn) plating that are
suitable for use in SnPb or Pb-free soldering processes.

VCC

LX 13
LX 15

PGND

LX 15

POK

EN
NC

AGND

VIN

AGND

B
FB

GND

POK

GND

PGND

VIN

GND

VIN

3
PGND

2
PGND

NC 16

PGND

10 VIN

11 VIN

12 VIN

Pin Configuration

1
2
3
WLCSP1.5x1.5-9B

PSOP - 8

WQFN3x3-16L

uPI Semiconductor Corp., http://www.upi-semi.com
Rev. P00, File Name: uP6305-DS-P0002

uP6305

Preliminary

Typical Application Circuit
LX

VIN
R3
VCC
EN
C3

PGND

uP6305AQDD

VIN

VOUT
R2

POK
Option
FB
R1

AGND

Functional Pin Description
Pin Name Pin Function
PGND
FB
AGND

Pow er Ground. Connect to the output and input capacitors return.
Feedback Input. This pin is the inverting input of the error amplifier. FB senses the switcher output through
an external resistor divider network.
Signal Ground. Connect the return of all small signal componenets to this pin.

Not Internally Connected.

Chip Enable (Active High). Logic low shuts down the converter.

VC C

B ias Supply. Suppli es power for the i nternal ci rcui try. C onnect to i nput power vi a low pass fi lter wi th
decoupling to AGND. This pin is internally connected to VIN for uP6305BFAP.

VIN

Pow er Supply Input. Input voltage that supplies current to the output voltage and powers the internal
control circuit. Bypass the input voltage with a minimum 10uF X5R or X7R ceramic capacitor.

Internal Sw itches Output. Connect these pins to the output inductor.

POK

Pow er OK Indication (uP6305AQDD Only). This pin is set high impedance after soft start end and no
fault occurs.

Exposed Pow er Ground. The exposed pad should be well soldered to PCB with multiple vias to ground plane
P ad
for optimal thermal performance.

uPI Semiconductor Corp., http://www.upi-semi.com
Rev. P00, File Name: uP6305-DS-P0002

uP6305

Preliminary

Functional Block Diagram
VCC

EN
POK

OSC &
Shutdown
Control
Over/Under
Voltage
Protection

VIN

Current
Sense

Slope
Comp.

Current Limit
Detector

Control Logic

0.6V
VREF

AGND

uPI Semiconductor Corp., http://www.upi-semi.com
Rev. P00, File Name: uP6305-DS-P0002

Driver

PGND

uP6305

Preliminary

Functional Description
The uP6305 is a high efficiency synchronous-rectified buck
converter with internal power switches. Fixed 1.0MHz PWM
operation allows possible smallest output ripple and
external component size. With high conversion efficiency
and small package, the uP6305 is ideally suitable for
portable devices and USB/PCIE-based interface cards
where PCB area is especially concerned.

where output capacitor is about 22uF.

EN
(2V/Div)
V OUT
(0.5V/Div)

With internal low RDS(ON) switches, the uP6305 is capable
of delivering 2.0A output current over a wide input voltage
range from 2.5V to 5.5V. The output voltage is adjustable
from 0.6V to VIN by a voltage divider. Other features include
internal soft-start, chip enable, overvoltage, under-voltage,
over-temperature and over-current protections. The uP6305
is available in a space-saving WQFN3x3-16L,
WLCSP1.5x1.5-9B or PSOP-8L packages.

ILX
(500mA/Div)

Time (100us/Div)

Input Supply Voltages, VIN & VCC
The uP6305 features seperate power supply and ground
pins for power stages and control circuit, isolating the
control circuit from noise associated with the power
MOSFET switching.
The VIN pins provide current to the power stage. The supply
voltage range is from 2.5V to 5.5V. The uP6305 draws
pulsed current with sharp edges from VIN each time the
upper switch turns on, resulting in voltage ripples and spikes
at supply input. A minimum 10uF ceramic capacitor with
shortest PCB trace is highly recommended for bypassing
the supply input.
The VCC pin provides currents for the internal control circuit.
A power on reset (POR) continuously monitors the input
supply voltage. The POR level is typically 2.3V at VCC rising.
Use low pass filter R3 and C3 as shown in the Typical
Application Circuit to filter the input noise associated with
the power switching.
Chip Enable/Disable and Soft Start
The uP6305 features an EN pin for enable/disable control
of the output voltage. Pulling the EN pin lower than 0.4V
shuts down the uP6305 and reduces its quiescent current
lower than 1uA. In the shutdown mode, both upper and
lower switches are turned off.
Pulling EN pin higher than 1.5V enables the uP6305 and
initiates the softstart cycle once the VCC POR is granted.
The inductor current is limited to fractions of its rated value
during the softstart cycle. Figure 1 illustrates the softstart
behavior of the uP6305. The inductor current ramps up
stairwisely with 250mA increments and 60us duration each
step. Note that the output capacitor is large to illustrate
the whole softstart behavior. The output voltage may ramp
up to its target level in 2 or 3 steps in real applications

uPI Semiconductor Corp., http://www.upi-semi.com
Rev. P00, File Name: uP6305-DS-P0002

Figure 1. Softstart of uP6305.
The uP6305 asserts end of soft start and set the current
limit to its normal level when the soft start duration expires.
After soft start end, the POK pin is set high impedance if
no fault occurs.
PWM Operation
The uP6305 adopts slope-compensated, current mode
PWM control capable of achieving 100% duty cycle. During
normal operation, the uP6305 operates at PWM mode to
regulate output voltage by transferring the power to the
output voltage cycle by cycle at a constant 1.0MHz
frequency. The uP6305 turns on the upper switch at each
rising edge of the internal oscillator allowing the inductor
current to ramp up linearly. The switch remains on until
either the current-limit is tripped or the PWM comparator
turns off the switch for regulating output voltage. The upper
switch current is sensed, slope compensated and
compared with the error amplifier output COMP to determine
the adequate duty cycle. The VOUT pin senses output
feedback voltage from an external resistive divider.
When the load current increases, it causes a slight
decrease in the feedback voltage relative to the 0.6V
reference, which in turn, causes the error amplifier output
voltage to increase until the average inductor current
matches the new load current.
Low Dropout Mode
The uP6305 increases duty cycle to maintain output voltage
within its regulation as the supply input drops gradually in
the battery-powered applications. The uP6305 operates with
100% duty cycle and enters low dropout mode as the supply
input approaches the output voltage. This maximizes the
battery life.

uP6305

Preliminary

Functional Description
Output Voltage Setting and Feedback Network

Undervoltage Protection

The output voltage can be set from VREF to VIN by a voltage
divider as:

Undervoltage Protection is triggered if the FB voltage is
lower than 0.15V and shuts down uP6305. The undervoltage
protection is latch-off type and can only be reset by POR
of VCC or toggling the EN pin.

VOUT =

R1 + R2
× VREF
R1

The internal VREF is 0.6V with 1.5% accuracy. In real
applications, a 22pF feedforward ceramic capacitor is
recommended in parallel with R2 for better transient
response.
Current Limit Function
The uP6305 continuously monitors the inductor current for
current limit by sensing the voltage drop across the upper
switch when it turns on. When the inductor current is higher
than current limit threshold (3.0A typical), the current limit
function activates and forces the upper switch turning off to
limit inductor current cycle by cycle. If the load continuously
demands more current than what uP6305 could provide,
uP6305 can not regulate the output voltage. Eventually
under voltage protection will be triggered and shuts down
the uP6305 if VOUT is too low.

uPI Semiconductor Corp., http://www.upi-semi.com
Rev. P00, File Name: uP6305-DS-P0002

Overvoltage Protection
Overvoltage protection (OVP) is triggered if the FB voltage
is higher than 0.8V and forces the uP6305 to continuous
PWM mode that allows the inductor current to be negative.
The voltage control loop will continuously turn on the lower
switch to sink charges from the output capacitor to lower
the output voltage. The lower switch turns off only the sinking
current is higher than it current limit level, typical 2.0A.
The uP6305 resumes normal operation if the OVP is
removed.
Over Temperature Protection (OTP)
The OTP is triggered and shuts down the uP6305 if the
junction temperature is higher than 150OC. The OTP is a
non-latch type protection. The uP6305 automatically
initiates another soft start cycle if the junction temperature
drops below 130OC.

uP6305

Preliminary

Absolute Maximum Rating
Supply Input Voltage, VIN, VCC(Note 1) --------------------------------------------------------------------------------------------- -0.3V to +6V
LX Pin Voltage
DC -------------------------------------------------------------------------------------------------------------------- -0.3V to +(VIN +0.3V)
<50ns -------------------------------------------------------------------------------------------------------------------- -5V to +(VIN +5V)
Other Pins --------------------------------------------------------------------------------------------------------------------------- -0.3V to (VCC + 0.3V
Storage Temperature Range ---------------------------------------------------------------------------------------------------- -65OC to +150OC
Junction Temperature ------------------------------------------------------------------------------------------------------------------------------------ 150OC
Lead Temperature (Soldering, 10 sec) ------------------------------------------------------------------------------------------------------------ 260OC
ESD Rating (Note 2)
HBM (Human Body Mode) --------------------------------------------------------------------------------------------------------------------- 2kV
MM (Machine Mode) ----------------------------------------------------------------------------------------------------------------------------- 200V

Thermal Information
Package Thermal Resistance (Note 3)
WQFN3x3-16L θJA ------------------------------------------------------------------------------------------------------------------------- 68°C/W
WQFN3x3-16L θJC ----------------------------------------------------------------------------------------------------------------------- 6°C/W
WLCSP1.5x1.5-9B θJA ----------------------------------------------------------------------------------------------------------------- 160°C/W
PSOP-8L θJA ------------------------------------------------------------------------------------------------------------------------- 50°C/W
PSOP-8L θJC ----------------------------------------------------------------------------------------------------------------------- 5°C/W
Power Dissipation, PD @ TA = 25°C
DFN3x3 -16 ----------------------------------------------------------------------------------------------------------------------------------------- 1.47W
WLCSP1.5x1.5-9B ------------------------------------------------------------------------------------------------------------------------------ 0.625W
PSOP-8L ----------------------------------------------------------------------------------------------------------------------------------------- 2.0W

Recommended Operation Conditions
Operating Junction Temperature Range (Note 4) ------------------------------------------------------------------------ -40OC to +125OC
Operating Ambient Temperature Range -------------------------------------------------------------------------------------- -40OC to +85OC
Supply Input Voltage, VIN -------------------------------------------------------------------------------------------------------- +2.5V to +5.5V

Electrical Characteristics
(VCC = VIN = 5V, TA = 25 C, unless otherwise specified)
O

Parameter

Symbol

Test Conditions

Min

Typ

Max

Units

2.5

5.5

VCC Rising, VEN = VCC

2.5

VCC Falling, VEN = VCC

2.2

VFB = 0.8V, IOUT = 0mA

3.4

0.01

Supply Current
Supply Voltage Range

VIN

Under Voltage Lockout

VUVLO

VIN = VCC

Quiescent Current

Shutdown Current

ISHDN

V E N = 0V

V FB

IOUT = 0mA

0.59

0.60

0.61

Output Voltage Accuracy

∆VOUT

IOUT = 0mA

-1.5

+1.5

Output Voltage Line Regulation

∆VOUT

VIN = 2.5V to 5.5V

0.04

0.4

%/V

Output Voltage Load Regulation

∆VOUT

IOUT = 0A ~ 2A

0.5

%/A

Reference
Reference Voltage

uPI Semiconductor Corp., http://www.upi-semi.com
Rev. P00, File Name: uP6305-DS-P0002

uP6305

Preliminary

Electrical Characteristics
Parameter

Symbol

Test Conditions

Min

Typ

Max

Units

0.8

1.0

1.2

MHz

Oscillator
Switching Frequency Range

fOSC

Maximum Duty Cycle

VIN = VOUT ; VFB = 0.55V

100

RDS(ON) of Upper Switch

RP_FET

VIN = 3.6V, ILX = 100mA

mΩ

RDS(ON) of Lower Switch

RN_FET

VIN = 3.6V, ILX = -100mA

mΩ

0.4

1.5

Pow er Sw itches

Logic Input
EN Logic Low Threshold

VIL

VIN = 2.5V to 5.5V, Shutdown

EN Logic High Threshold

VIH

VIN = 2.5V to 5.5V, Enable

Logic High Leakage Current

IPOK

VPOK = VCC = 5V

Logic Low Voltage

VPOK

IPOK = 1mA

0.2

FB Under Voltage Protection

∆FB_UVP FB Falling

%VREF

FB Over Voltage Protection

∆FB_OVP FB Rising

b y d e si g n

150

∆TSHDN by design

Pow er OK Output

Protection

Thermal Shutdwon Temperature
Thermal Shutdown Hysteresis

TSHDN

130 %VREF
C
C

Note 1. Stresses listed as the above “Absolute Maximum Ratings” may cause permanent damage to the device.
These are for stress ratings. Functional operation of the device at these or any other conditions beyond those
indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may remain possibility to affect device reliability.
Note 2. Devices are ESD sensitive. Handling precaution recommended.
Note 3. θJA is measured in the natural convection at TA = 25°C on a low effective thermal conductivity test board of
JEDEC 51-3 thermal measurement standard.
Note 4. The device is not guaranteed to function outside its operating conditions.

uPI Semiconductor Corp., http://www.upi-semi.com
Rev. P00, File Name: uP6305-DS-P0002

uP6305

Preliminary

Typical Operation Characteristics
Turn On Waveforms

Turn On Waveforms

LX (10V/Div)

LX (10V/Div)
EN
(5V/Div)

EN
(5V/Div)

VOUT
(500mV/Div)

IOUT
(1A/Div)

100us/Div
VIN = 3.3V, VOUT = 1.2V, RLOAD = 0.6Ω

100us/Div
VIN = 5V, VOUT = 1.2V, RLOAD = 0.6Ω

Turn Off Waveforms

LX (10V/Div)

VOUT
(500mV/Div)

EN
(5V/Div)

IOUT
(1A/Div)

VOUT
(500mV/Div)

EN
(2V/Div)

IOUT
(1A/Div)

4us/Div
VIN = 3.3V, VOUT = 1.2V, RLOAD = 0.6Ω

4us/Div
VIN = 5V, VOUT = 1.2V, RLOAD = 0.6Ω

Switching

LX
(2V/Div)

ILX
(500mA/Div)

400ns/Div
VIN = 3.3V, VOUT = 1.2V, IOUT = 1A

uPI Semiconductor Corp., http://www.upi-semi.com
Rev. P00, File Name: uP6305-DS-P0002

ILX
(500mA/Div)

400ns/Div
VIN = 5V, VOUT = 1.2V, IOUT = 1A

uP6305

Preliminary

Typical Operation Characteristics
Steady State Waveforms

Steady State Waveforms

VOUT
(10mV/Div)

IOUT
(500mA/Div)

400ns/Div
VIN = 3.3V, VOUT = 1.2V, IOUT = 1A

400ns/Div
VIN = 5V, VOUT = 1.2V, IOUT = 1A

Steady State Waveforms

VOUT
(10mV/Div)

IOUT (1A/Div)

400ns/Div
VIN = 3.3V, VOUT = 1.2V, IOUT = 2A

400ns/Div
VIN = 5V, VOUT = 1.2V, IOUT = 2A

Load Transient Response

VOUT
(50mV/Div)

IOUT (1A/Div)

20us/Div
IOUT = 0A to 1A, VIN = 3.3V, VOUT = 1.2V

uPI Semiconductor Corp., http://www.upi-semi.com
Rev. P00, File Name: uP6305-DS-P0002

20us/Div
IOUT = 0A to 2A, VIN = 3.3V, VOUT = 1.2V

uP6305

Preliminary

Typical Operation Characteristics
Load Transient Response

Load Transient Response

VOUT
(50mV/Div)

IOUT (1A/Div)

20us/Div
IOUT = 0.5A to 1.5A, VIN = 3.3V, VOUT = 1.2V

20us/Div
IOUT = 1A to 2A, VIN = 3.3V, VOUT = 1.2V

Load Transient Response

VOUT
(50mV/Div)

IOUT (1A/Div)
IOUT (1A/Div)

20us/Div
IOUT = 0A to 1A, VIN = 5V, VOUT = 1.2V

20us/Div
IOUT = 0A to 2A, VIN = 5V, VOUT = 1.2V

Load Transient Response

VOUT
(50mV/Div)

IOUT (1A/Div)

20us/Div
IOUT = 0.5 to 1.5A, VIN = 5V, VOUT = 1.2V

20us/Div
IOUT = 1A to 2A, VIN = 5V, VOUT = 1.2V

uPI Semiconductor Corp., http://www.upi-semi.com
Rev. P00, File Name: uP6305-DS-P0002

uP6305

Preliminary

Typical Operation Characteristics
Quiescent Current vs. VIN

FREQ vs. VIN

1.3

1.2

FREQ (MHz)

Quiescent Current (mA)

1.1

1.0

0.9

0.8
2.5

3.0

3.5

4.0

4.5

5.0

5.5

2.5

3.0

3.5

Input Voltage (V)

4.5

5.0

5.5

5.0

5.5

FB vs. VIN

0.620

1.8

0.615
1.6

0.610
0.605

1.4

FB (V)

Enable/Disable Threshold Voltage (V)

Enable/Disable Threshold Voltage vs. VIN

Enable
1.2

0.600
0.595
0.590

Disable

1.0

0.585
0.8

0.580
2.5

3.0

3.5

4.0

4.5

5.0

5.5

2.5

3.0

Input Voltage (V)

3.5

4.0

4.5

Input Voltage (V)

Efficiency vs. Output Current

100

Efficiency (%)

4.0

Input Voltage (V)

60
50
40

100

1000

10000

Output Current (mA)
VIN = 3.3V, VOUT = 1.2V, L = 3.3uH, CIN = COUT = 22uF

uPI Semiconductor Corp., http://www.upi-semi.com
Rev. P00, File Name: uP6305-DS-P0002

100

1000

10000

Output Current (mA)
VIN = 5V, VOUT = 1.2V, L = 3.3uH, CIN = COUT = 22uF

uP6305

Preliminary

Typical Operation Characteristics
OCP

FREQ vs. Temperature
1200

3.2
3.0

1100

2.6

FREQ (kHz)

Output Current (A)

2.8

2.4
2.2
2.0

1000
900
800

1.8

700

1.6
1.4

600
2.5

3.0

3.5

4.0

4.5

5.0

5.5

-40

Input Voltage (V)
VIN = 3.3V, VOUT = 1.2V, CIN = COUT = 22uF

100 120 140

VIN = 5V, VOUT = 1.2V, L = 3.3uH, CIN = COUT = 22uF, No Load

Input Current vs. Temperature
6

1.21

Input Current (mA)

Output Voltage (V)

Temperature (OC)

VOUT vs. Temperature

1.22

-20

1.20
1.19
1.18
1.17

4
3
2
1

1.16
1.15

0
-40

-20

100 120 140

-40

-20

100 120 140

Temperature (OC)

VIN = 5V, VOUT = 1.2V, L = 3.3uH, CIN = COUT = 22uF, No Load

uPI Semiconductor Corp., http://www.upi-semi.com
Rev. P00, File Name: uP6305-DS-P0002

uP6305

Preliminary

Application Information
Output Inductor Selection
Output inductor selection is usually based the
considerations of inductance, rated current value, size
requirements and DC resistance (DCR).
The inductance is chosen based on the desired ripple
current. Large value inductors result in lower ripple currents
and small value inductors result in higher ripple currents.
Higher VIN or VOUT also increases the ripple current as shown
in the equation below. A reasonable starting point for setting
ripple current is ∆IL = 600mA (30% of 2A).
∆IL =

fOSC

V
1
× VOUT × (1 − OUT )
× L OUT
VIN

For most applications, the value of the inductor will fall in
the range of 1uH to 10uH.
Maximum current ratings of the inductor are generally
specified in two methods: permissible DC current and
saturation current. Permissible DC current is the allowable
DC current that causes 40OC temperature raise. The
saturation current is the allowable current that causes 10%
inductance loss. Make sure that the inductor will not
saturate over the operation conditions including temperature
range, input voltage range, and maximum output current. If
possible, choose an inductor with rated current higher than
3A so that it will not saturate even under current limit
condition.
The size requirements refer to the area and height
requirement for a particular design. For better efficiency,
choose a low DC resistance inductor. DCR is usually
inversely proportional to size.
Different core materials and shapes will change the size/
current and price/current relationship of an inductor. Toroid
or shielded pot cores in ferrite or permalloy materials are
small and don’t radiate much energy, but generally cost
more than powdered iron core inductors with similar electrical
characteristics. The choice of which style inductor to use
often depends on the price vs. size requirements and any
radiated field/EMI requirements.
Input Capacitor Selection
The uP6305 draws pulsed current with sharp edges from
the input capacitor resulting in ripple and noise at the input
supply voltage. A minimum 10uF X5R or X7R ceramic
capacitor is highly recommended to filter the pulsed current.
The input capacitor should be placed as near the device as
possible to avoid the stray inductance along the connection
trace. Y5V dielectrics, aside from losing most of their

uPI Semiconductor Corp., http://www.upi-semi.com
Rev. P00, File Name: uP6305-DS-P0002

capacitance over temperature, they also become resistive
at high frequencies. This reduces their ability to filter out
high frequency noise.
The capacitor with low ESR (equivalent series resistance)
provides the small drop voltage to stabilize the input voltage
during the transient loading. For input capacitor selection,
the ceramic capacitors larger than 1uF is recommend. The
capacitor must conform to the RMS current requirement.
The maximum RMS ripple current is calculated as:
IIN(RMS) = IOUT(MAX) ×

VOUT × ( VIN − VOUT )
VIN

This formula has a maximum at VIN = 2xVOUT, where IIN(RMS)
= IOUT(MAX)/2. This simple worst-case condition is commonly
used for design because even significant deviations do not
offer much relief. Note that the capacitor manufacturer’s
ripple current ratings are often based on 2000 hours of life.
This makes it advisable to further derate the capacitor, or
choose a capacitor rated at a higher temperature than
required. Always consult the manufacturer if there is any
question.
Output Capacitor Selection
The uP6305 is specifically design to operate with minimum
10uF X5R or X7R ceramic capacitor. The value can be
increased to improve load/line transient performance. Y5V
dielectrics, aside from losing most of their capacitance over
temperature, they also become resistive at high
frequencies. This reduces their ability to filter out high
frequency noise.
The ESR of the output capacitor determines the output
ripple voltage and the initial voltage drop following a high
slew rate load transient edge. The output ripple voltage
can be calculated as:
∆VOUT = ∆IC × (ESR +

1
)
8 × fOSC × COUT

where fOSC = operating frequency, COUT = output capacitance
and ∆IC = ∆IL = ripple current in the inductor.
The ceramic capacitor with low ESR value provides the low
output ripple and low size profile. Connect a 22uF ceramic
capacitor at output terminal for good performance and place
the input and output capacitors as close as possible to the
device.
Using Ceramic Capacitors
Higher value, lower cost ceramic capacitors are now
available in smaller case sizes. Their high ripple current,
high voltage rating and low ESR make them ideal for
switching regulator applications. Because the uP6305
13

uP6305

Preliminary

Application Information
control loop does not depend on the output capacitor’s ESR
for stable operation, ceramic capacitors can be used to
achieve very low output ripple and small circuit size.
However, care must be taken when these capacitors are
used at the input and the output. When a ceramic capacitor
is used at the input and the power is supplied by a wall
adapter through long wires, a load step at the output can
induce ringing at the input, VIN. At best, this ringing can
couple to the output and be mistaken as loop instability. At
worst, a sudden inrush of current through the long wires
can potentially cause a voltage spike at VIN, large enough
to damage the part.
When choosing the input and output ceramic capacitors,
choose the X5R or X7R dielectric formulations. These
dielectrics have the best temperature and voltage
characteristics of all the ceramics for a given value and
size.
Thermal Considerations
In most applications the uP6305 does not dissipate much
heat due to its high efficiency. However, overtemperature
protection is implemented in case of applications where
the uP6305 is operating at high ambient temperature. If
the junction temperature reaches approximately 150OC, the
OTP turns both power switches and let the LX node become
high impedance. The uP6305 restores to normal operation
if the junction temperature drops to 130OC.
It is helpful to analysis the power dissipation of uP6305 for
avoding the uP6305 from exceeding the maximum junction
temperature. In typical applications, the conduction loss
dominates the total power loss in uP6305. The conduction
loss has its maximum at high duty-ratio, low input voltage,
and high ambient temperatures.

COUT, which generates a feedback error signal. The regulator
loop then acts to return VOUT to its steady state value.
During this recovery time VOUT can be monitored for
overshoot or ringing that would indicate a stability problem.
PCB Layout Considerations
High switching frequencies and relatively large peak
currents make the PCB layout a very important part of
switching mode power supply design. Good design
minimizes excessive EMI on the feedback paths and voltage
gradients in the ground plane, both of which can result in
instability or regulation errors. Follow the PCB layout
guidelines for optimal performance of uP6305.
1. For the main current paths, keep their traces short,
direct and wide.
2. Put the input/output capacitors as close as possible to
the device pins.
3. LX node is with high frequency voltage swing and should
be kept small area. Keep analog components away from
LX node to prevent stray capacitive noise pick-up.
4. Connect feedback network behind the output capacitors.
Place the feedback components near the uP6305 and
keep the loop area small. .
5. A ground plane is preferred, but if not available, keep
the signal and power grounds sepregated with small
signal components returning to the GND pin at one point.
They should not share the high current path of CIN or
COUT.
6. Flood all unused areas on all layers with copper.
Flooding with copper will reduce the temperature rise
of power components. These copper areas should be
connected to VIN or GND.

Consider the uP6305 in dropout mode operation at an input
voltage of 2.5V, a load current of 1.5A and an ambient
temperature of 75OC. The on-resistance of the upper swith
is about 100mΩ at this condition. Therefore the power
dissipation PD is:
2
PD = IOUT
× RDS( ON) = 225mW

This results in 50 x 0.225 = 12OC temperature raise at
junction. The juction temperature is 82OC and is lower
than it maximum rating 125OC.
Checking Transient Response
The regulator loop response can be checked by looking at
the load transient response. Switching regulators take
several cycles to respond to a step in load current. When
a load step occurs, VOUT immediately shifts by an amount
equal to (∆IOUT x ESR), where ESR is the effective series
resistance of COUT. ∆IOUT also begins to discharge or charge
uPI Semiconductor Corp., http://www.upi-semi.com
Rev. P00, File Name: uP6305-DS-P0002

uP6305

Preliminary

Package Information
WQFN3x3-16L Package
0.35 - 0.45

1.45 - 1.80

1.45-1.80

2.90 - 3.10
2.90 - 3.10

0.18 - 0.30

Bottom View - Exposed Pad

Pin 1 mark

0.80 MAX

3.45 - 3.55

1.45 -1.80

0.20 BSC

2.05 - 2.15

0.00 - 0.05

0.18 - 0.30

Recommended Solder Pad Pitch and Dimensions

Note
1.Package Outline Unit Description:
BSC: Basic. Represents theoretical exact dimension or dimension target
MIN: Minimum dimension specified.
MAX: Maximum dimension specified.
REF: Reference. Represents dimension for reference use only. This value is not a device specification.
TYP. Typical. Provided as a general value. This value is not a device specification.
2.Dimensions in Millimeters.
3.Drawing not to scale.
4.These dimensions no not include mold flash or protrusions. Mold flash or protrusions shell not exceed 0.15mm.

uPI Semiconductor Corp., http://www.upi-semi.com
Rev. P00, File Name: uP6305-DS-P0002

uP6305

Preliminary

Package Information
WLCSP1.5x1.5-9B Package
0.50 - 0.70
1.40 - 1.50

0.30 - 0.34R

0.05 - 0.13

1.40 - 1.50

0.50 BSC

3
2
1

BUMP A1 Center

0.21 - 0.27

A
0.50 BSC

0.25 - 0.28R

0.50 BSC

Recommended Solder Pad Layout

uPI Semiconductor Corp., http://www.upi-semi.com
Rev. P00, File Name: uP6305-DS-P0002

uP6305

Preliminary

Package Information
PSOP-8L Package
0.70 ± 0. 10

4.80 - 5.00

1.27 ± 0.10
1.50 ± 0. 10

1.80 - 2.30

2.20 ± 0. 10
1.80 - 2.30

3.80 - 4.00

5.80 - 6.20

4.00 ± 0. 10

2.20 ± 0. 10

5.50 ± 0.10

7.00 ± 0.10

1.27 BSC

0.32 - 0.52

Recommended Solder Pad Layout
1.45 - 1.60
0.18 - 0.25

1.75 MAX
0.05 - 0.25

0.40 - 0.90

3.81 BSC

uPI Semiconductor Corp., http://www.upi-semi.com
Rev. P00, File Name: uP6305-DS-P0002

www.s-manuals.com

Source Exif Data:

File Type                       : PDF
File Type Extension             : pdf
MIME Type                       : application/pdf
PDF Version                     : 1.6
Linearized                      : No
XMP Toolkit                     : Adobe XMP Core 4.0-c316 44.253921, Sun Oct 01 2006 17:14:39
Producer                        : Acrobat Distiller 5.0.5 (Windows)
Create Date                     : 2009:10:28 17:50:44+08:00
Modify Date                     : 2015:11:08 09:47:18+02:00
Metadata Date                   : 2015:11:08 09:47:18+02:00
Creator Tool                    : Adobe PageMaker 7.0
Format                          : application/pdf
Creator                         : 
Title                           : uP6305 - Datasheet. www.s-manuals.com.
Description                     : 
Subject                         : uP6305 - Datasheet. www.s-manuals.com.
Document ID                     : uuid:f0b1cf82-9e7b-4ff6-bf9d-c3b4befb6b66
Instance ID                     : uuid:2aa9ac92-264b-4a29-bacb-9fa5eb204129
Page Count                      : 18
Keywords                        : uP6305, -, Datasheet., www.s-manuals.com.

EXIF Metadata provided by EXIF.tools

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