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User Manual: Motherboard Wistron Cathedral Peak II - Schematics. Free.

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5

4

3

2

1

Cathedral Peak II Block Diagram

Project code: 91.4K801.001
PCB P/N
: 48.4K801.0SB
REVISION
: 08219-SB
SYSTEM DC/DC

CLK GEN.

D

ICS 9LPRS365BKLFT (71.09365.A03)
RTM 875N-606-LFT (71.00875.C03)
3

35

TPS51125

Mobile CPU

PCB STACKUP

THERMAL EMC2102

Penryn 479

21

D

INPUTS

OUTPUTS

TOP
5V_S5

HOST BUS

DDR2 DIMM1
667/800 MHz

667/800/1067MHz@1.05V

GND

3D3V_S5

SYSTEM DC/DC

BOTTOM

INPUTS
DCBATOUT

1D8V_S3

LVDS, CRT I/F

RT9026

6,7,8,9,10,11

INT.MIC

AZALIA

ALC268

C-Link0

DDR_VREF_S3

RT9018A

6 PCIe ports

PCIex1

PCI/PCI BRIDGE

28

MIC In

4 SATA

PCIex1

12 USB 2.0/1.1 ports

LAN

TXFM

CFXCORE DC/DC
ISL6263
INPUTS
27
DCBATOUT

Kedron a/b/g/n

27

Matrix Storage Technology(DO)

INPUTS

BIOS
Winbond
W25X16
16M Bits

KBC
ENE3310
30

17,18,19,20

MODEM
MDC Card

USB

23

Blue Tooth
23
(USB)

Camera
(USB) 14

Touch
Pad 30

LPC
31

DEBUG
CONN.31

USB
3 Port

22
A

0.35~1.5V

CHARGER

Launch
Buttom
16

BQ24745
INPUTS

INT.
KB 30

39
OUTPUTS
BT+

USB
23

CardReader
Realtek
RTS5158E
24

DCBATOUT

MS/MS Pro/xD
/MMC/SD
5 in 1

24

A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

SATA
Title

Launch Board
LED Board

BLOCK DIAGRAM
16

Size
A3

Document Number

Date: Friday, June 20, 2008
5

VCC_CORE_S0

DCBATOUT

HDD SATA

22

34

OUTPUTS

DCBATOUT

SATA

ODD SATA

0.7~1.25V

B

29

Line Out
(NO SPDIF)

VGFXCORE

ISL6266A

LPC BUS

Active Managemnet Technology(DO)

INT.SPKR

OUTPUTS

CPU DC/DC

Serial Peripheral I/F

APA205729

38

Mini Card

LPC I/F

OP AMP

26

PWR SW
TPS2231

New card

PCIex1

High Definition Audio

1D5V_S0

RJ45

26

25

27

ETHERNET (10/100/1000MbE)

36

1D8V_S3

Giga LAN
88E8071

ACPI 2.0

29

C

1D8V_S3

ICH9M

Codec

36
DDR_VREF_S0

X4 DMI
400MHz

RJ11

OUTPUTS
1D05V_S0

INTEGRATED GRAHPICS

667/800MHz

37

TPS51124

14

DDR Memory I/F

16

B

LCD

AGTL+ CPU I/F

13

29

S

15

Cantiga

DDR2 DIMM2
C

CRT

S

667/800MHz

12

667/800 MHz

DCBATOUT

VCC

4, 5

4

3

2

Rev

SB

Cathedral Peak II
Sheet
1

1

of

43

A

B

C

ICH9M Functional Strap Definitions
ICH9 EDS 642879 Rev.1.5

4

D

ICH9M Integrated Pull-up
and Pull-down Resistors

page 92

Signal

Usage/When Sampled

HDA_SDOUT

XOR Chain Entrance/
PCIE Port Config1 bit1,
Rising Edge of PWROK

Allows entrance to XOR Chain testing when TP3
pulled low.When TP3 not pulled low at rising edge
of PWROK,sets bit1 of RPC.PC(Config Registers:
offset 224h). This signal has weak internal pull-down

CL_CLK[1:0]

PULL-UP 20K

CL_DATA[1:0]

PULL-UP 20K

HDA_SYNC

PCIE config1 bit0,
Rising Edge of PWROK.

This signal has a weak internal pull-down.
Sets bit0 of RPC.PC(Config Registers:Offset 224h)

CL_RST0#

PULL-UP 20K

GNT2#/
GPIO53

PCIE config2 bit2,
Rising Edge of PWROK.

DPRSLPVR/GPIO16

PULL-DOWN 20K

GPIO20

Reserved

This signal has a weak internal pull-up.
Sets bit2 of RPC.PC2(Config Registers:Offset 0224h)
This signal should not be pulled high.

GNT1#/
GPIO51

ESI Strap (Server Only)
Rising Edge of PWROK

GNT3#/
GPIO55

GNT0#:
SPI_CS1#/
GPIO58

SPI_MOSI

3
GPIO49

SATALED#
SPKR

TP3

GPIO33/
HDA_DOCK
_EN#

Top-Block
Swap Override.
Rising Edge of PWROK.

Boot BIOS Destination
Selection 0:1.
Rising Edge of PWROK.
Integrated TPM Enable,
Rising Edge of CLPWROK

Comment

ICH9 EDS 642879

SIGNAL

ESI compatible mode is for server platforms only.
This signal should not be pulled low for desttop
and mobile.
Sampled low:Top-Block Swap mode(inverts A16 for
all cycles targeting FWH BIOS space).
Note: Software will not be able to clear the
Top-Swap bit until the system is rebooted
without GNT3# being pulled down.

ENERGY_DETECT

PULL-UP 20K
PULL-DOWN 20K

HDA_DOCK_EN#/GPIO33

PULL-UP 20K

HDA_RST#

PULL-DOWN 20K

HDA_SDIN[3:0]

PULL-DOWN 20K

HDA_SDOUT

PULL-DOWN 20K

Configuration
000 = FSB1067
011 = FSB667
010 = FSB800
others = Reserved

4

Reserved

CFG5

DMI x2 Select

CFG6

iTPM Host
Interface

0 = DMI x2
1 = DMI x4 (Default)
0= The iTPM Host Interface is enabled(Note2)
1=The iTPM Host Interface is disalbed(default)
0 = Transport Layer Security (TLS) cipher
suite with no confidentiality
1 = TLS cipher suite with
confidentiality (default)

PCIE Graphics Lane

0 = Reverse Lanes,15->0,14->1 ect..
1= Normal operation(Default):Lane
Numbered in order

PCIE Loopback enable

0 = Enable (Note 3)
1= Disabled (default)

GNT[3:0]#/GPIO[55,53,51]

PULL-UP 20K

GPIO[20]

PULL-DOWN 20K

GPIO[49]

PULL-UP 20K

LDA[3:0]#/FHW[3:0]#

PULL-UP 20K

LAN_RXD[2:0]

PULL-UP 20K

LDRQ[0]

PULL-UP 20K

LDRQ[1]/GPIO23

PULL-UP 20K

PME#

PULL-UP 20K

PWRBTN#

PULL-UP 20K

SATALED#

PULL-UP 15K

No Reboot.
Rising Edge of PWROK.

If sampled high, the system is strapped to the
"No Reboot" mode(ICH9 will disable the TCO Timer
system reboot feature). The status is readable
via the NO REBOOT bit.

SPI_CS1#/GPIO58/CLGPIO6

PULL-UP 20K

SPI_MOSI

PULL-DOWN 20K

SPI_MISO

PULL-UP 20K

This signal should not be pull low unless using
XOR Chain testing.

SPKR

PULL-DOWN 20K

TACH_[3:0]

PULL-UP 20K

TP[3]

PULL-UP 20K

USB[11:0][P,N]

PULL-DOWN 15K

Sampled low:the Flash Descriptor Security will be
overridden. If high,the security measures will be
in effect.This should only be enabled in manufacturing
environments using an external pull-up resister.

CFG[4:3]
CFG8
CFG[15:14]
CFG[18:17]

Strap Description
FSB Frequency
Select

The pull-up or pull-down active when configured for nativeCFG9
GLAN_DOCK# functionality and determined by LAN controller

Signal has weak internal pull-up. Sets bit 27
of MPC.LR(Device 28:Function 0:Offset D8)

Flash Descriptor
Security Override Strap
Rising Edge of PWROK

CFG[2:0]

0.5

Intel Management
engine Crypto strap

PCI Express Lane
Reversal. Rising Edge
of PWROK.

XOR Chain Entrance.
Rising Edge of PWROK.

Pin Name

PULL-DOWN 20K

GLAN_DOCK#

DMI Termination Voltage, The signal is required to be low for desktop
Rising Edge of PWROK.
applications and required to be high for
mobile applications.

page 218

CFG7

HDA_SYNC

Controllable via Boot BIOS Destination bit
(Config Registers:Offset 3410h:bit 11:10).
GNT0# is MSB, 01-SPI, 10-PCI, 11-LPC.
Sample low: the Integrated TPM will be disabled.
Sample high: the MCH TPM enable strap is sampled
low and the TPM Disable bit is clear, the
Integrated TPM will be enable.

Montevina Platform Design guide 22339

Rev.1.5

Resistor Type/Value

HDA_BIT_CLK

E

Cantiga chipset and ICH9M I/O controller
Hub strapping configuration

CFG10
CFG[13:12]

CFG16

CFG19

00
10
01
11

XOR/ALL

=
=
=
=

Reserve
XOR mode Enabled
ALLZ mode Enabled (Note 3)
Disabled (default)

FSB Dynamic ODT

0 = Dynamic ODT Disabled
1 = Dynamic ODT Enabled (Default)

DMI Lane Reversal

0 = Normal operation(Default):
Lane Numbered in Order

3

1 = Reverse Lanes
DMI x4 mode[MCH -> ICH]:(3->0,2->1,1->2and0->3)
DMI x2 mode[MCH -> ICH]:(3->0,2->1)

CFG20

Digital Display Port
(SDVO/DP/iHDMI)
Concurrent with PCIe

0 = Only Digital Display Port
or PCIE is operational (Default)
1 =Digital display Port and PCIe are
operting simulataneously via the PEG port
0 =No SDVO Card Present (Default)

SDVO_CTRLDATA

SDVO Present
1 = SDVO Card Present
0 = LFP Disabled (Default)

L_DDC_DATA

Local Flat Panel
(LFP) Present

1= LFP Card Present; PCIE disabled

NOTE:
1. All strap signals are sampled with respect to the leading edge of
the (G)MCH Power OK (PWROK) signal.
2. iTPM can be disabled by a 'Soft-Strap' option in the
Flash-decriptor section of the Firmware. This 'Soft-Strap' is
activated only after enabling iTPM via CFG6.
Only one of the CFG10/CFG/12/CFG13 straps can be enabled at any time.

2

2

SMBus
EMC2102

USB Table
USB

PCIE Routing

1

LANE1

LAN MARVELL 88E8071

LANE2

MiniCard WLAN

LANE3

NC

LANE4

NC

LANE5

NewCard

LANE6

NC

Pair

KBC
BAT_SCL

Device

0

USB1

1

NC

2

USB2

Thermal

BATTERY

3

NC

4

USB3

5

Bluetooth

6

NC

7

MINIC1

Wistron Corporation

8

WEBCAM

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

9

NEW1

10

Card Reader

11

NC

1

ICH9M

Title

SMBC_ICH

9LPRS365BKLFT
DDR

Reference
Size
A3

Document Number

Date: Friday, June 20, 2008

Rev

SB

Cathedral Peak II
Sheet

2

of

43

A

B

C

D

E

3D3V_S0

3D3V_S0

2

4

2

24
18

GEN_XTAL_OUT_R

4,7

C176
SC33P50V2JN-3GP

1 10MR2J-L-GP
GEN_XTAL_OUT

1
0R0402-PAD

3
2

RN51

4 SRN33J-5-GP-U
3

1
2

CLK48_5158E
CLK48_ICH

2
R156

CPU_SEL0

3

1

CLK48 17

4
16
9
46
62
23

2

1
2

1
2

1

CPUT0
CPUC0

61
60

CLK_CPU_BCLK_1
CLK_CPU_BCLK_1#

R160 1
R166 1

2 0R0402-PAD
2 0R0402-PAD

CLK_CPU_BCLK 4
CLK_CPU_BCLK# 4

CPU

CPUT1_F
CPUC1_F

58
57

CLK_MCH_BCLK_1
CLK_MCH_BCLK_1#

R167 1
R169 1

2 0R0402-PAD
2 0R0402-PAD

CLK_MCH_BCLK 6
CLK_MCH_BCLK# 6

NB

CPUT2_ITP/SRCT8
CPUC2_ITP/SRCC8

54
53

CLK_PCIE_LAN_R
CLK_PCIE_LAN#_R

R173 1
R176 1

2 0R0402-PAD
2 0R0402-PAD

CLK_PCIE_LAN 25
CLK_PCIE_LAN# 25

LAN

SRCT7/CR#_F
SRCC7/CR#_E

51
50

CLK_PCIE_NEW_R
CLK_PCIE_NEW#_R

R182 1
R181 1

2 0R0402-PAD
2 0R0402-PAD

CLK_PCIE_NEW 27
CLK_PCIE_NEW# 27

New Card

SRCT6
SRCC6

48
47

CLK_PCIE_ICH_1
CLK_PCIE_ICH_1#

R195 1
R194 1

2 0R0402-PAD
2 0R0402-PAD

CLK_PCIE_ICH 18
CLK_PCIE_ICH# 18

SB DMI

SRCT10
SRCC10

41
42

SRCT11/CR#_H
SRCC11/CR#_G

40
39

SRCT9
SRCC9

37
38

SRCT4
SRCC4

34
35

CLK_PCIE_MINI_1
CLK_PCIE_MINI_1#

R192 1
R193 1

2 0R0402-PAD
2 0R0402-PAD

CLK_PCIE_MINI1 27
CLK_PCIE_MINI1# 27

MINI1

SRCT3/CR#_C
SRCC3/CR#_D

31
32

CLK_MCH_3GPLL_1
CLK_MCH_3GPLL_1#

R180 1
R184 1

2 0R0402-PAD
2 0R0402-PAD

CLK_MCH_3GPLL 7
CLK_MCH_3GPLL# 7

NB CLK

SRCT2/SATAT
SRCC2/SATAC

28
29

CLK_PCIE_SATA_1
CLK_PCIE_SATA_1#

R174 1
R177 1

2 0R0402-PAD
2 0R0402-PAD

CLK_PCIE_SATA 17
CLK_PCIE_SATA# 17

SB SATA

27MHZ_NONSS/SRCT1/SE1
27MHZ_SS/SRCC1/SE2

24
25

DREFSSCLK_1
DREFSSCLK#_1

R168 1
R171 1

2 0R0402-PAD
2 0R0402-PAD

DREFSSCLK 7
DREFSSCLK# 7

SRCT0/DOTT_96
SRCC0/DOTC_96

20
21

DREFCLK_1
DREFCLK#_1

R158 1
R161 1

2 0R0402-PAD
2 0R0402-PAD

DREFCLK 7
DREFCLK# 7

X1
X2

USB_48MHZ/FSLA

2K2R2J-2-GP

18 PM_STPPCI#
18 PM_STPCPU#

45
44

12,13,20 SMBC_ICH
12,13,20 SMBD_ICH

7
6

PCI_STOP#
CPU_STOP#

3D3V_S0
CPU_SEL2

8
7
6
5

3D3V_S0

2
R155

RN59
SRN10KJ-6-GP
7

DY

18 CLK_PWRGD
1
10KR2J-3-GP
R150 1
DY 2
475R2F-L1-GP

CLK_MCH_OE#

PCLKCLK2
CPU_SEL2_R
PCLKCLK4
PCLKCLK5

30
18

PCLK_KBC
PCLK_ICH

RN17 1
2

PCLKCLK4
PCLKCLK5

4
3

63

CK_PWRGD/PD#

8
10
11
12
13
14

PCI0/CR#_A
PCI1/CR#_B
PCI2/TME
PCI3
PCI4/27_SELECT
PCI_F5/ITP_EN

SRN33J-5-GP-U
4,7

CPU_SEL1

CPU_SEL2_R

64
5

FSLB/TEST_MODE
REF0/FSLC/TEST_SEL

4
3

PCLKCLK3

55

NC#55

RN70
SRN33J-5-GP-U

DY

ICS9LPRS365BKLFT-GP

ICS9LPRS365BKLFT setting table
PIN NAME
DESCRIPTION

71.09365.A03

PCI0/CR#_A

Byte 5, bit 7
0 = PCI0 enabled (default)
1= CR#_A enabled. Byte 5, bit 6 controls whether CR#_A controls SRC0 or SRC2 pair
Byte 5, bit 6
0 = CR#_A controls SRC0 pair (default),
1= CR#_A controls SRC2 pair

PCI1/CR#_B

Byte 5, bit 5
0 = PCI1 enabled (default)
1= CR#_B enabled. Byte 5, bit 6 controls whether CR#_B controls SRC1 or SRC4 pair
Byte 5, bit 4
0 = CR#_B controls SRC1 pair (default)
1= CR#_B controls SRC4 pair

PCI2/TME

0 = Overclocking of CPU and SRC Allowed
1 = Overclocking of CPU and SRC NOT allowed

PCI3

3.3V PCI clock output

PCI4/27M_SEL

0 = Pin24 as SRC-1, Pin25 as SRC-1#, Pin20 as DOT96, Pin21 as DOT96#
1 = Pin24 as 27MHz, Pin25 as 27MHz_SS, Pin20 as SRC-0, Pin21 as SRC-0#

PCI_F5/ITP_EN

0 =SRC8/SRC8#
1 = ITP/ITP#

SRCT3/CR#_C

Byte 5, bit 3
0 = SRC3 enabled (default)
1= CR#_C enabled. Byte 5, bit 2 controls whether CR#_C controls SRC0 or SRC2 pair
Byte 5, bit 2
0 = CR#_C controls SRC0 pair (default),
1= CR#_C controls SRC2 pair

GND
GNDSRC
GNDSRC
GNDSRC
GNDCPU
GND

1
2

CLK_ICH14
PCLK_FWH

22
30
36
49
59
26

18
31

GND48
GNDPCI
GNDREF

DY

EC59
SC5P50V2CN-2GP

18
15
1

EC56
SC5P50V2CN-2GP

2

1

PCLK_FWH

GND

SB

1

PCLKCLK0
PCLKCLK1
PCLKCLK2
PCLKCLK3

SCLK
SDATA

NB CLK
NB CLK
(96 MHz)

SEL2 SEL1 SEL0
FSC FSB FSA
PIN NAME

DESCRIPTION

SRCC3/CR#_D

Byte 5, bit 1
0 = SRC3 enabled (default)
1= CR#_D enabled. Byte 5, bit 0 controls whether CR#_D controls SRC1 or SRC4 pair
Byte 5, bit 0
0 = CR#_D controls SRC1 pair (default)
1= CR#_D controls SRC4 pair

SRCC7/CR#_E

Byte 6, bit 7
0 = SRC7# enabled (default)
1= CR#_F controls SRC6

SRCT7/CR#_F

Byte 6, bit 6
0 = SRC7 enabled (default)
1= CR#_F controls SRC8

SRCC11/CR#_G

Byte 6, bit 5
0 = SRC11# enabled (default)
1= CR#_G controls SRC9

SRCT11/CR#_H

Byte 6, bit 4
0 = SRC11 enabled (default)
1= CR#_H controls SRC10

1
0
0
0
0

0
0
1
1
0

1
1
1
0
0

CPU

FSB

100M
133M
166M
200M
266M

X
533M
667M
800M
1066M
1

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size

Clock Generator
Document Number

Date: Friday, June 20, 2008
B

2

2nd:
71.00875.C03
RTM875N-606-LFT QFN 64P

Rev

Cathedral Peak II
A

3

65

1
2
3
4

TPAD30 TP158

PCLK_KBC

1

19
27
43
52
33
56
VDD96_IO
VDDPLL3_IO
VDDSRC_IO
VDDSRC_IO
VDDSRC_IO
VDDCPU_IO

DY

EC55
SC5P50V2CN-2GP

DY

VDDREF
VDD48
VDDPCI
VDDSRC
VDDCPU
VDDPLL3

R154 2

2
X3
R153
X-14D31818M-44GP

1
2
1

2

3D3V_48MPWR_S0

CL=20pF±0.2pF

82.30005.951

2

2

1
2

1
2

1
2

1
2

2

2
1

1
2

EC137
SC5P50V2CN-2GP

DY

C177
SC33P50V2JN-3GP
GEN_XTAL_IN
1
2

1

SCD1U16V2ZY-2GP

3D3V_CLKPLL_S0

U19

SB

2

C184

DY

CLK_ICH14
CLK48_ICH
EC57
SC5P50V2CN-2GP

DY

4,7

1 R157
2
0R0603-PAD
C234
SCD1U16V2ZY-2GP

PCLK_ICH

C198
SCD1U16V2ZY-2GP

3D3V_CLKGEN_S0

C453
SCD1U16V2ZY-2GP

DY

C214
SCD1U16V2ZY-2GP

DY

C195
SC4D7U10V5ZY-3GP

2

1

1

1

1

3D3V_CLKGEN_S0
C246
SCD1U16V2ZY-2GP

2

1

1 R197
2
0R0603-PAD
C462
SCD1U16V2ZY-2GP

DY

C231
SCD1U16V2ZY-2GP

2

C465
SCD1U16V2ZY-2GP

2

C459
SCD1U16V2ZY-2GP

DY

C235
SC4D7U10V5ZY-3GP

DY

C463
SCD1U16V2ZY-2GP

2

EC58
SCD1U16V2ZY-2GP

4

C183
SC1U16V3ZY-GP

SC4D7U6D3V3KX-GP

DY

3D3V_CLKPLL_S0

1

C190

2

1

3D3V_48MPWR_S0

1

1 R146
2
0R0603-PAD

1

3D3V_S0

C

D

Sheet
E

3

SB
of

43

A

6

B

C

D

E

H_A#[35..3]

H_A#[35..3]

H_DINV#[3..0]
U33A 1 OF 4

TP93

M4
N5
T2
V3
B2
C3
D2
D22
D3
F6

RSVD_CPU_11

B1

AD4
AD3
AD1
AC4
AC2
AC1
AC5
AA6
AB3
AB5
AB6
C20

2

CONTROL

THERMTRIP#

BCLK0
BCLK1

H_DSTBN#0
H_DSTBP#0
H_DINV#0

E22
F24
E26
G22
F23
G25
E25
E23
K24
G24
J24
J23
H22
F26
K22
H23
J26
H26
H25

D0#
D1#
D2#
D3#
D4#
D5#
D6#
D7#
D8#
D9#
D10#
D11#
D12#
D13#
D14#
D15#
DSTBN0#
DSTBP0#
DINV0#

H_DSTBN#1
H_DSTBP#1
H_DINV#1

H_D#16 N22
H_D#17 K25
H_D#18 P26
H_D#19 R23
H_D#20 L23
H_D#21 M24
H_D#22 L22
H_D#23 M23
H_D#24 P25
H_D#25 P23
H_D#26 P22
H_D#27 T24
H_D#28 R24
H_D#29 L25
H_D#30 T25
H_D#31 N25
L26
M26
N24

D16#
D17#
D18#
D19#
D20#
D21#
D22#
D23#
D24#
D25#
D26#
D27#
D28#
D29#
D30#
D31#
DSTBN1#
DSTBP1#
DINV1#

H_TRDY# 6
H_HIT#
H_HITM#
XDP_BPM#0
XDP_BPM#1
XDP_BPM#2
XDP_BPM#3
XDP_BPM#4
XDP_BPM#5
XDP_TCK
XDP_TDI
XDP_TDO
XDP_TMS
XDP_TRST#
XDP_DBRESET#

TP27
TP25
TP28
TP41
TP30
TP37
TP29
TP39
TP40
TP44
TP34
TP91

H_THERMDA

6
6
TPAD30
TPAD30
TPAD30
TPAD30
TPAD30
TPAD30
TPAD30
TPAD30
TPAD30
TPAD30
TPAD30
TPAD30

DY
H_THERMDC

C136
SC2200P50V2KX-2GP

1D05V_S0
6
6
6

R123
68R2-GP

DY

CPU_PROCHOT#

D21
A24
B25

1
R124

H_THERMDA 21
H_THERMDC 21

C7

2

CPU_PROCHOT#_R

34

0R2J-2-GP

PM_THRMTRIP-A# 7,17,32

A22
A21

CLK_CPU_BCLK 3
CLK_CPU_BCLK# 3

1D05V_S0

PM_THRMTRIP#
should connect to
ICH9 and MCH
without T-ing
( No stub)

6
6
6

R263
1KR2F-3-GP
Layout Note:
"CPU_GTLREF0"
0.5" max length.
R266
2KR2F-3-GP

CPU_GTLREF0

TP21
TP150

AD26
TEST1
C23
TEST2
D25
RSVD_CPU_12 C24
TEST4
AF26
RSVD_CPU_13 AF1
RSVD_CPU_14 A26

DY C352

KEY_NC

CPU_SEL0
CPU_SEL1
CPU_SEL2

B22
B23
C21

62.10079.001

2nd: 62.10053.401

TPAD30 TP86
TPAD30
TPAD30

3,7
3,7
3,7

1D05V_S0

GTLREF
TEST1
TEST2
TEST3
TEST4
TEST5
TEST6

DATA GRP2

BPM0#
BPM1#
BPM2#
BPM3#
PRDY#
PREQ#
TCK
TDI
TDO
TMS
TRST#
DBR#

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15

DATA GRP3

G6
E4

BGA479-SKT6-GPU6

MISC

BSEL0
BSEL1
BSEL2

D32#
D33#
D34#
D35#
D36#
D37#
D38#
D39#
D40#
D41#
D42#
D43#
D44#
D45#
D46#
D47#
DSTBN2#
DSTBP2#
DINV2#

Y22
AB24
V24
V26
V23
T22
U25
U23
Y25
W22
Y23
W24
W25
AA23
AA24
AB25
Y26
AA26
U22

H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47

D48#
D49#
D50#
D51#
D52#
D53#
D54#
D55#
D56#
D57#
D58#
D59#
D60#
D61#
D62#
D63#
DSTBN3#
DSTBP3#
DINV3#

AE24
AD24
AA21
AB22
AB21
AC26
AD20
AE22
AF23
AC25
AE21
AD21
AC22
AD23
AF22
AC23
AE25
AF24
AC20

H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

COMP0
COMP1
COMP2
COMP3

R26
U26
AA1
Y1

DPRSTP#
DPSLP#
DPWR#
PWRGOOD
SLP#
PSI#

E5
B5
D24
D6
D7
AE6

1

2 54D9R2F-L1-GP

XDP_TDI

R101 1

2 54D9R2F-L1-GP

XDP_BPM#5

R97

2 54D9R2F-L1-GP

1

H_CPURST#

R116 1

XDP_TCK

R94

XDP_TRST#

R96

1
1

DY

3

H_DSTBN#2 6
H_DSTBP#2 6
H_DINV#2 6

H_DSTBN#3 6
H_DSTBP#3 6
H_DINV#3 6
COMP0
COMP1
COMP2
COMP3

R105
R104
R98
R99

1
1
1
1

2
2
2
2

27D4R2F-L1-GP
54D9R2F-L1-GP
27D4R2F-L1-GP
54D9R2F-L1-GP

2

H_DPRSTP# 7,17,34
H_DPSLP# 17
H_DPWR# 6
H_PWRGD 17,32,41
H_CPUSLP# 6
PSI#
34

BGA479-SKT6-GPU6

62.10079.001
Layout Note:
Comp0, 2 connect with Zo=27.4 ohm, make
trace length shorter than 0.5" .
Comp1, 3 connect with Zo=55 ohm, make
trace length shorter than 0.5" .

Follow Demo Circuit
R102 1

4

6

U33B 2 OF 4
6

1

HIT#
HITM#

H_LOCK# 6
H_CPURST# 6,41
H_RS#[2..0]

H_RS#0
H_RS#1
H_RS#2

2

C1
F3
F4
G3
G2

HCLK

XDP_TMS

H_D#[63..0]

1
H4

PROCHOT#
THRMDA
THRMDC

RSVD#M4
RSVD#N5
RSVD#T2
RSVD#V3
RSVD#B2
RSVD#C3
RSVD#D2
RSVD#D22
RSVD#D3
RSVD#F6

6

17

1

RSVD_CPU_1
RSVD_CPU_2
RSVD_CPU_3
RSVD_CPU_4
RSVD_CPU_5
RSVD_CPU_6
RSVD_CPU_7
RSVD_CPU_8
RSVD_CPU_9
RSVD_CPU_10

6

H_DSTBP#[3..0]

TP95 TPAD30

H_INIT#

SC1KP50V2KX-1GP

TPAD30

TP52
TP49
TP48
TP47
TP89
TP92
TP87
TP90
TP88
TP72

LOCK#
RESET#
RS0#
RS1#
RS2#
TRDY#

H_BREQ#0 6
H_IERR#

2

2

TPAD30
TPAD30
TPAD30
TPAD30
TPAD30
TPAD30
TPAD30
TPAD30
TPAD30
TPAD30

F1
D20
B3

2

STPCLK#
LINT0
LINT1
SMI#

BR0#
IERR#
INIT#

2

17
17
17
17

6

H_DSTBN#[3..0]

Place testpoint on
H_IERR# with a GND
0.1" away

R125
56R2J-4-GP

1

H_STPCLK#
H_INTR
H_NMI
H_SMI#

D5
C6
B4
A3

DEFER#
DRDY#
DBSY#

1

A20M#
FERR#
IGNNE#

H_D#[63..0]

THERMAL

ICH

17
17
17

H_DEFER# 6
H_DRDY# 6
H_DBSY# 6

H_DSTBP#[3..0]

1D05V_S0

1

H_A20M#
H_FERR#
H_IGNNE#

A6
A5
C4

Side Band
Non GTL

A17#
A18#
A19#
A20#
A21#
A22#
A23#
A24#
A25#
A26#
A27#
A28#
A29#
A30#
A31#
A32#
A33#
A34#
A35#
ADSTB1#

H5
F21
E1

6
6
6

DATA GRP1

H_ADSTB#1

Y2
U5
R3
W6
U4
Y5
U1
R4
T5
T3
W2
W5
Y4
U2
V4
W3
AA4
AB2
AA3
V1

3

6

REQ0#
REQ1#
REQ2#
REQ3#
REQ4#

ADDR GROUP 1

H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35

H_ADS#
H_BNR#
H_BPRI#

DATA GRP0

H_REQ#0 K3
H_REQ#1 H2
H_REQ#2 K2
H_REQ#3 J3
H_REQ#4 L1

H1
E2
G5

2

H_ADSTB#0
H_REQ#[4..0]

ADS#
BNR#
BPRI#

XDP/ITP SIGNALS

6
6

A3#
A4#
A5#
A6#
A7#
A8#
A9#
A10#
A11#
A12#
A13#
A14#
A15#
A16#
ADSTB0#

RESERVED

4

J4
L5
L4
K5
M3
N2
J1
N3
P5
P2
L2
P4
P1
R1
M1

ADDR GROUP 0

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16

H_DINV#[3..0]

H_DSTBN#[3..0]

TP57 TPAD30

1
R118

DY

2 TEST1
1KR2J-1-GP

2 51R2F-2-GP

1
R295

DY

2

2 54D9R2F-L1-GP

2
C351

Net "TEST4" as short as possible,
make sure "TEST4" routing is
reference to GND and away other
noisy signals

TEST2
1KR2J-1-GP

TEST4
1
SCD1U10V2KX-4GP

DY

2 54D9R2F-L1-GP

1

3D3V_S0

All place within 2" to CPU
XDP_DBRESET# R121 1

DY

Wistron Corporation

2 1KR2J-1-GP

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

1D05V_S0
Title
XDP_TDO

R100 1

DY

2 54D9R2F-L1-GP

CPU (1 of 2)
Size

Document Number

Rev

SB

Cathedral Peak II
Date: Friday, June 20, 2008
A

B

C

D

Sheet
E

4

of

43

A

B

C

VCC_CORE

U33D

VCC_CORE

1
4

1

1

1

1

A4
A8
A11
A14
A16
A19
A23
AF2
B6
B8
B11
B13
B16
B19
B21
B24
C5
C8
C11
C14
C16
C19
C2
C22
C25
D1
D4
D8
D11
D13
D16
D19
D23
D26
E3
E6
E8
E11
E14
E16
E19
E21
E24
F5
F8
F11
F13
F16
F19
F2
F22
F25
G4
G1
G23
G26
H3
H6
H21
H24
J2
J5
J22
J25
K1
K4
K23
K26
L3
L6
L21
L24
M2
M5
M22
M25
N1
N4
N23
N26
P3

TC9
ST900U2D5VM-1-GP
TP22
TPAD30

NEC

2
3

DY
2

DY
2

DY
2

DY

2

1
2

1
2

1

C89
SCD1U10V2KX-4GP

2

1

C130
SCD1U10V2KX-4GP

2

C124
SCD1U10V2KX-4GP

DY

C90
SCD1U10V2KX-4GP

DY

C88
SCD1U10V2KX-4GP

DY

C122
SCD1U10V2KX-4GP

DY

C120
SCD1U10V2KX-4GP

77.E9071.011

1

C105

DY
2

1

C103

DY
2

1

C71

DY
2

1
2

1
2

1
2

1
2

1
2

1

C106

DY

SC10U6D3V5MX-3GP

2

1

C94

DY

SC10U6D3V5MX-3GP

2

1

C70

SC10U6D3V5MX-3GP

DY

SC10U6D3V5MX-3GP

2

1

C374

SC10U6D3V5MX-3GP

DY

SC10U6D3V5MX-3GP

2

C381

SC10U6D3V5MX-3GP

CAP

DY

SC10U6D3V5MX-3GP

CAP

C375
SC10U6D3V5MX-3GP

CAP

C380
SC10U6D3V5MX-3GP

CAP

C93
SC10U6D3V5MX-3GP

CAP

C135
SC10U6D3V5MX-3GP

CAP

C102

2

C123

1

1

VCC_CORE

SC10U6D3V5MX-3GP

1D05V_S0
G5

1
2

R77
100R2F-L1-GP-U

1
2

2

1

C99

C433

2

1

C98

2

1
2

1
2

1
2

1
2

1
2

1
2

1
2

1
2

1

1

DY

C427

DY

C95

DY

SC4D7U6D3V3KX-GP

VCC_CORE

C421

C112

SC4D7U6D3V3KX-GP

34

C110

SCD1U10V2KX-4GP

H_VID[6..0]

C108

SCD1U10V2KX-4GP

L11

1

C101

SCD1U10V2KX-4GP

AE7

1D5V_S0
1D5V_VCCA_S0

H_VID0
H_VID1
H_VID2
H_VID3
H_VID4
H_VID5
H_VID6

C104

SCD1U10V2KX-4GP

VSSSENSE

layout note: "1D5V_VCCA_S0"
as short as possible

SCD1U10V2KX-4GP

AF7

DY

1D05V_S0

C100

SCD1U10V2KX-4GP

VCCSENSE

GAP-CLOSE-PWR-2U
C114

SCD1U10V2KX-4GP

VID0
VID1
VID2
VID3
VID4
VID5
VID6

AD6
AF5
AE5
AF4
AE3
AF3
AE2

2

SC10U6D3V5MX-3GP

B26
C26

1

SCD01U16V2KX-3GP

VCCA
VCCA

VCCP_1D05

SCD1U10V2KX-4GP

VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP

G21
V6
J6
K6
M6
J21
K21
M21
N21
N6
R21
R6
T21
T6
V21
W21

2

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

C86

SC10U6D3V5MX-3GP

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

AB20
AB7
AC7
AC9
AC12
AC13
AC15
AC17
AC18
AD7
AD9
AD10
AD12
AD14
AD15
AD17
AD18
AE9
AE10
AE12
AE13
AE15
AE17
AE18
AE20
AF9
AF10
AF12
AF14
AF15
AF17
AF18
AF20

SCD1U10V2KX-4GP

PBY160808T-121Y-GP

68.00206.021

VCC_SENSE 34
VSS_SENSE 34

1

A7
A9
A10
A12
A13
A15
A17
A18
A20
B7
B9
B10
B12
B14
B15
B17
B18
B20
C9
C10
C12
C13
C15
C17
C18
D9
D10
D12
D14
D15
D17
D18
E7
E9
E10
E12
E13
E15
E17
E18
E20
F7
F9
F10
F12
F14
F15
F17
F18
F20
AA7
AA9
AA10
AA12
AA13
AA15
AA17
AA18
AA20
AB9
AC10
AB10
AB12
AB14
AB15
AB17
AB18

SCD1U10V2KX-4GP

2

U33C 3 OF 4

2

4

3

VCC_CORE

E

VCC_CORE

2

VCC_CORE

D

BGA479-SKT6-GPU6

Layout Note:
R88
100R2F-L1-GP-U

VCCSENSE and VSSSENSE lines
should be of equal length.

2

62.10079.001

Layout Note:
Provide a test point (with
no stub) to connect a
differential probe
between VCCSENSE and
VSSSENSE at the location
where the two 54.9ohm
resistors terminate the
55 ohm transmission line.

4 OF 4

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

P6
P21
P24
R2
R5
R22
R25
T1
T4
T23
T26
U3
U6
U21
U24
V2
V5
V22
V25
W1
W4
W23
W26
Y3
Y6
Y21
Y24
AA2
AA5
AA8
AA11
AA14
AA16
AA19
AA22
AA25
AB1
AB4
AB8
AB11
AB13
AB16
AB19
AB23
AB26
AC3
AC6
AC8
AC11
AC14
AC16
AC19
AC21
AC24
AD2
AD5
AD8
AD11
AD13
AD16
AD19
AD22
AD25
AE1
AE4
AE8
AE11
AE14
AE16
AE19
AE23
AE26
A2
AF6
AF8
AF11
AF13
AF16
AF19
AF21
A25
AF25

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

4

3

2

TPAD30
TP24

TPAD30
TP26
TP94
TPAD30

TP151
TPAD30
TP23
TPAD30

BGA479-SKT6-GPU6

62.10079.001

1

1

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

CPU (2 of 2)
Size

Document Number

Rev

SB

Cathedral Peak II
Date: Friday, June 20, 2008
A

B

C

D

Sheet
E

5

of

43

5

4

3

2

1

1 OF 10

U35A

H_A#[35..3]
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

1D05V_S0

H_SWING routing Trace width and
Spacing use 10 / 20 mil

1

D

H_D#[63..0]

H_D#[63..0]

R317
221R2F-2-GP

2

H_SWING Resistors and
Capacitors close MCH
500 mil ( MAX )

R316
100R2F-L1-GP-U

2

2

C450
SCD1U10V2KX-4GP

1

1

H_SWING

C

H_RCOMP routing Trace width and
Spacing use 10 / 20 mil
1
R312

2
24D9R2F-L-GP

H_RCOMP

Place them near to the chip ( < 0.5")

B

F2
G8
F8
E6
G2
H6
H2
F6
D4
H3
M9
M11
J1
J2
N12
J6
P2
L2
R2
N9
L6
M5
J3
N2
R1
N5
N6
P13
N8
L7
N10
M3
Y3
AD14
Y6
Y10
Y12
Y14
Y7
W2
AA8
Y9
AA13
AA9
AA11
AD11
AD10
AD13
AE12
AE9
AA2
AD8
AA3
AD3
AD7
AE14
AF3
AC1
AE3
AC3
AE11
AE8
AG2
AD6

H_D#_0
H_D#_1
H_D#_2
H_D#_3
H_D#_4
H_D#_5
H_D#_6
H_D#_7
H_D#_8
H_D#_9
H_D#_10
H_D#_11
H_D#_12
H_D#_13
H_D#_14
H_D#_15
H_D#_16
H_D#_17
H_D#_18
H_D#_19
H_D#_20
H_D#_21
H_D#_22
H_D#_23
H_D#_24
H_D#_25
H_D#_26
H_D#_27
H_D#_28
H_D#_29
H_D#_30
H_D#_31
H_D#_32
H_D#_33
H_D#_34
H_D#_35
H_D#_36
H_D#_37
H_D#_38
H_D#_39
H_D#_40
H_D#_41
H_D#_42
H_D#_43
H_D#_44
H_D#_45
H_D#_46
H_D#_47
H_D#_48
H_D#_49
H_D#_50
H_D#_51
H_D#_52
H_D#_53
H_D#_54
H_D#_55
H_D#_56
H_D#_57
H_D#_58
H_D#_59
H_D#_60
H_D#_61
H_D#_62
H_D#_63

HOST

4

2
1

R322
1KR2F-3-GP

4,41 H_CPURST#
4
H_CPUSLP#

C455
SCD1U16V2ZY-2GP

H_ADS#
H_ADSTB#_0
H_ADSTB#_1
H_BNR#
H_BPRI#
H_BREQ#
H_DEFER#
H_DBSY#
HPLL_CLK
HPLL_CLK#
H_DPWR#
H_DRDY#
H_HIT#
H_HITM#
H_LOCK#
H_TRDY#

H12
B16
G17
A9
F11
G12
E9
B10
AH7
AH6
J11
F9
H9
E12
H11
C9

H_DINV#_0
H_DINV#_1
H_DINV#_2
H_DINV#_3

J8
L3
Y13
Y1

H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3

H_DSTBN#_0
H_DSTBN#_1
H_DSTBN#_2
H_DSTBN#_3

L10
M7
AA5
AE6

H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3

H_DSTBP#_0
H_DSTBP#_1
H_DSTBP#_2
H_DSTBP#_3

L9
M8
AA6
AE5

H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3

H_SWING
H_RCOMP

H_REQ#_0
H_REQ#_1
H_REQ#_2
H_REQ#_3
H_REQ#_4

B15
K13
F13
B13
B14

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

H_CPURST#
H_CPUSLP#

H_RS#_0
H_RS#_1
H_RS#_2

B6
F12
C8

H_RS#0
H_RS#1
H_RS#2

H_AVREF
H_DVREF

H_A#[35..3]

4

D

H_ADS# 4
H_ADSTB#0 4
H_ADSTB#1 4
H_BNR# 4
H_BPRI# 4
H_BREQ#0 4
H_DEFER# 4
H_DBSY# 4
CLK_MCH_BCLK 3
CLK_MCH_BCLK# 3
H_DPWR# 4
H_DRDY# 4
H_HIT# 4
H_HITM# 4
H_LOCK# 4
H_TRDY# 4

H_DSTBN#[3..0]

H_DSTBP#[3..0]

C

H_DINV#[3..0]

4

H_DSTBN#[3..0]

4

H_DSTBP#[3..0]

4

H_REQ#[4..0]

H_RS#[2..0]

B

4

4

CANTIGA-GM-GP-U-NF

2

R318
2KR2F-3-GP

C12
E11
A11
B11

1

1

H_AVREF

C5
E3

A14
C15
F16
H13
C18
M16
J13
P16
R16
N17
M13
E17
P17
F17
G20
B19
J16
E20
H16
J20
L17
A17
B17
L16
C21
J17
H20
B18
K17
B20
F21
K21
L20

H_DINV#[3..0]

1D05V_S0
H_SWING
H_RCOMP

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35

H_A#_3
H_A#_4
H_A#_5
H_A#_6
H_A#_7
H_A#_8
H_A#_9
H_A#_10
H_A#_11
H_A#_12
H_A#_13
H_A#_14
H_A#_15
H_A#_16
H_A#_17
H_A#_18
H_A#_19
H_A#_20
H_A#_21
H_A#_22
H_A#_23
H_A#_24
H_A#_25
H_A#_26
H_A#_27
H_A#_28
H_A#_29
H_A#_30
H_A#_31
H_A#_32
H_A#_33
H_A#_34
H_A#_35

2

71.CNTIG.00U

A

A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size

Cantiga (1 of 6)

Document Number

Rev

SB

Cathedral Peak II
Date: Friday, June 20, 2008
5

4

3

2

Sheet
1

6

of

43

5

4

3

2

1

2 OF 10

U35B

1

BA17
AY16
AV16
AR13

M_CS0#
M_CS1#
M_CS2#
M_CS3#

13
13
12
12

SA_ODT_0
SA_ODT_1
SB_ODT_0
SB_ODT_1

BD17
AY17
BF15
AY13

M_ODT0
M_ODT1
M_ODT2
M_ODT3

13
13
12
12

SM_RCOMP
SM_RCOMP#

BG22
BH21

M_RCOMPP
M_RCOMPN

SM_RCOMP_VOH
SM_RCOMP_VOL

BF28
BH28

SM_RCOMP_VOH
SM_RCOMP_VOL

SM_VREF
SM_PWROK
SM_REXT
SM_DRAMRST#

AV42
AR36
BF17
BC36

SM_REXT
1R328
TP_SM_DRAMRST#

DPLL_REF_CLK
DPLL_REF_CLK#
DPLL_REF_SSCLK
DPLL_REF_SSCLK#

B38
A38
E41
F41

PEG_CLK
PEG_CLK#

F43
E43

M_RCOMPP

DY

2 4K02R2F-GP CFG20

CFG16
CFG19
CFG20

DY

2 2K21R2F-GP CFG5

R186 1

DY

2 2K21R2F-GP CFG6

R188 1

DY

2 2K21R2F-GP CFG7

18
PM_SYNC#
4,17,34 H_DPRSTP#

2 2K21R2F-GP CFG9

DY

2 2K21R2F-GP CFG10

R190 1

DY

2 2K21R2F-GP CFG12

R185 1

DY

2 2K21R2F-GP CFG13

18,25,27,30,31

PLT_RST1#

2
R353
R140

1
0R0402-PAD
1
2
300R2F-GP

B

2 2K21R2F-GP CFG16

3D3V_S0

RN32
PM_EXTTS#0
PM_EXTTS#1

4
3

1
2
SRN10KJ-5-GP

BG48
BF48
BD48
BC48
BH47
BG47
BE47
BH46
BF46
BG45
BH44
BH43
BH6
BH5
BG4
BH3
BF3
BH2
BG2
BE2
BG1
BF1
BD1
BC1
F1
A47

NC#BG48
NC#BF48
NC#BD48
NC#BC48
NC#BH47
NC#BG47
NC#BE47
NC#BH46
NC#BF46
NC#BG45
NC#BH44
NC#BH43
NC#BH6
NC#BH5
NC#BG4
NC#BH3
NC#BF3
NC#BH2
NC#BG2
NC#BE2
NC#BG1
NC#BF1
NC#BD1
NC#BC1
NC#F1
NC#A47

DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3

DMI_RXP_0
DMI_RXP_1
DMI_RXP_2
DMI_RXP_3

AE40
AE38
AE48
AH40

DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3

DMI_TXN_0
DMI_TXN_1
DMI_TXN_2
DMI_TXN_3

AE35
AE43
AE46
AH42

DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3

DMI_TXP_0
DMI_TXP_1
DMI_TXP_2
DMI_TXP_3

AD35
AE44
AF46
AH43

DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3

DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3

GFX_VR_EN

C34

LVDSA_DATA#_0
LVDSA_DATA#_1
LVDSA_DATA#_2
LVDSA_DATA#_3

14 GMCH_TXAOUT0+
14 GMCH_TXAOUT1+
14 GMCH_TXAOUT2+

H48
D45
F40
B40

LVDSA_DATA_0
LVDSA_DATA_1
LVDSA_DATA_2
LVDSA_DATA_3

14 GMCH_TXBOUT014 GMCH_TXBOUT114 GMCH_TXBOUT2-

A41
H38
G37
J37

LVDSB_DATA#_0
LVDSB_DATA#_1
LVDSB_DATA#_2
LVDSB_DATA#_3

14 GMCH_TXBOUT0+
14 GMCH_TXBOUT1+
14 GMCH_TXBOUT2+

B42
G38
F37
K37

LVDSB_DATA_0
LVDSB_DATA_1
LVDSB_DATA_2
LVDSB_DATA_3

F25
H25
K25

TVA_DAC
TVB_DAC
TVC_DAC

H24

TV_RTN

C31
E32

TV_DCONSEL_0
TV_DCONSEL_1

GMCH_BLUE

E28

CRT_BLUE

GMCH_GREEN

G28

CRT_GREEN

TVA_DAC
TVB_DAC
TVC_DAC

18
18
18
18

DMI_TXP0 18
DMI_TXP1 18
DMI_TXP2 18
DMI_TXP3 18
DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3

15

18
18
18
18

GMCH_BLUE

15 GMCH_GREEN
15

DMI_RXP0 18
DMI_RXP1 18
DMI_RXP2 18
DMI_RXP3 18

GMCH_RED

GMCH_RED

15 GMCH_DDCCLK
15 GMCH_DDCDATA
15 GMCH_HSYNC
15 GMCH_VSYNC
38

GMCH_DDCCLK
GMCH_DDCDATA
GMCH_HS
3
4
GMCH_VS

2
1

J28

CRT_RED

G29

CRT_IRTN

H32
J32
J29
E29
L29

CRT_DDC_CLK
CRT_DDC_DATA
CRT_HSYNC
CRT_TVO_IREF
CRT_VSYNC

RN71
SRN33J-5-GP-U
CRT_IREF
1
2
R347
1K02R2F-1-GP

GFX_VID0
GFX_VID1
GFX_VID2
GFX_VID3
GFX_VID4

H44
J46
L44
L40
N41
P48
N44
T43
U43
Y43
Y48
Y36
AA43
AD37
AC47
AD39

PEG_RX_0
PEG_RX_1
PEG_RX_2
PEG_RX_3
PEG_RX_4
PEG_RX_5
PEG_RX_6
PEG_RX_7
PEG_RX_8
PEG_RX_9
PEG_RX_10
PEG_RX_11
PEG_RX_12
PEG_RX_13
PEG_RX_14
PEG_RX_15

H43
J44
L43
L41
N40
P47
N43
T42
U42
Y42
W47
Y37
AA42
AD36
AC48
AD40

PEG_TX#_0
PEG_TX#_1
PEG_TX#_2
PEG_TX#_3
PEG_TX#_4
PEG_TX#_5
PEG_TX#_6
PEG_TX#_7
PEG_TX#_8
PEG_TX#_9
PEG_TX#_10
PEG_TX#_11
PEG_TX#_12
PEG_TX#_13
PEG_TX#_14
PEG_TX#_15

J41
M46
M47
M40
M42
R48
N38
T40
U37
U40
Y40
AA46
AA37
AA40
AD43
AC46

PEG_TX_0
PEG_TX_1
PEG_TX_2
PEG_TX_3
PEG_TX_4
PEG_TX_5
PEG_TX_6
PEG_TX_7
PEG_TX_8
PEG_TX_9
PEG_TX_10
PEG_TX_11
PEG_TX_12
PEG_TX_13
PEG_TX_14
PEG_TX_15

J42
L46
M48
M39
M43
R47
N37
T39
U36
U39
Y39
Y46
AA36
AA39
AD42
AD46

1
49D9R2F-GP

Close to GMCH as 500 mils.

D

C

CANTIGA-GM-GP-U-NF

71.CNTIG.00U
FOR Cantiga: 1.02k_1% ohm
Teenah: 1.3k ohm

GFXVR_EN

GFXVR_EN 38

CRT_IREF routing Trace
width use 20 mil

1D05V_S0

CL_CLK
CL_DATA
CL_PWROK
CL_RST#
CL_VREF

AH37
AH36
AN36 CLPWROK_MCH 2 R352
1
0R0402-PAD
AJ35
AH34 MCH_CLVREF

CL_CLK0 18
CL_DATA0 18
PWROK
18,32
CL_RST#0
18

C270

NC

DY

PM_SYNC#
PM_DPRSTP#
PM_EXT_TS#_0
PM_EXT_TS#_1
PWROK
RSTIN#
THERMTRIP#
DPRSLPVR

2
499R2F-2-GP
TP120
TPAD30

DREFCLK 3
DREFCLK# 3
DREFSSCLK 3
DREFSSCLK# 3
CLK_MCH_3GPLL 3
CLK_MCH_3GPLL# 3

AE41
AE37
AE47
AH39

B33
B32
G33
F33
E33

H47
E46
G40
A40

GMCH_TXACLKGMCH_TXACLK+
GMCH_TXBCLKGMCH_TXBCLK+

C487

DDPC_CTRLCLK
DDPC_CTRLDATA
SDVO_CTRLCLK
SDVO_CTRLDATA
CLKREQ#
ICH_SYNC#

N28
M28
G36
E36
K36
H36

TSATN#

B12

HDA_BCLK
HDA_RST#
HDA_SDI
HDA_SDO
HDA_SYNC

B28
B30
B29
C29
A28

SCD1U10V2KX-4GP

4,17,32 PM_THRMTRIP-A#
18,34 PM_DPRSLPVR
R189 1

DY

2

C165
SC100P50V2JN-3GP

R29
B7
N33
P32
AT40
AT11
T20
R32

PM

18,21,34 VGATE_PWRGD
18,32 PWROK

DY

R336 1

R332 1

R354 0R2J-2-GP
1
DY 2

PM_SYNC#
H_DPRSTP#
PM_EXTTS#0
PM_EXTTS#1
PWROK_GD
RSTIN#
PM_THRMTRIP-A#
PM_DPRSLPVR

DDR_VREF_S3

GFX_VID[4..0]

1

R345 1

DREFCLK
DREFCLK#
DREFSSCLK
DREFSSCLK#

DMI_RXN_0
DMI_RXN_1
DMI_RXN_2
DMI_RXN_3

GFX_VID_0
GFX_VID_1
GFX_VID_2
GFX_VID_3
GFX_VID_4

14 GMCH_TXAOUT014 GMCH_TXAOUT114 GMCH_TXAOUT2-

14
14
14
14

R355
1KR2F-3-GP

RN72

1

R208 1

ME

DY

2 4K02R2F-GP CFG19

MISC

R207 1

L_VDD_EN
LVDS_IBG
LVDS_VBG
LVDS_VREFH
LVDS_VREFL
LVDSA_CLK#
LVDSA_CLK
LVDSB_CLK#
LVDSB_CLK

PEG_RX#_0
PEG_RX#_1
PEG_RX#_2
PEG_RX#_3
PEG_RX#_4
PEG_RX#_5
PEG_RX#_6
PEG_RX#_7
PEG_RX#_8
PEG_RX#_9
PEG_RX#_10
PEG_RX#_11
PEG_RX#_12
PEG_RX#_13
PEG_RX#_14
PEG_RX#_15

VGA

CFG12
CFG13

CFG

CFG9
CFG10

3D3V_S0

CFG_0
CFG_1
CFG_2
CFG_3
CFG_4
CFG_5
CFG_6
CFG_7
CFG_8
CFG_9
CFG_10
CFG_11
CFG_12
CFG_13
CFG_14
CFG_15
CFG_16
CFG_17
CFG_18
CFG_19
CFG_20

M29
C44
B43
E37
E38
C41
C40
B37
A37

TPAD30 TP121

PEG_COMPI
PEG_COMPO

PEG_CMP 2

2

CFG5
CFG6
CFG7

T25
R25
P25
P20
P24
C25
N24
M24
E21
C23
C24
N21
P21
T21
R20
M20
L21
H21
P29
R28
T28

GRAPHICS VID

CPU_SEL0
CPU_SEL1
CPU_SEL2

TP115 TPAD30

CLK_MCH_OE# 3
MCH_ICH_SYNC# 18
MCH_TSATN#

TP110 TPAD30

GMCH_RED
R356
511R2F-2-GP

GMCH_BLUE
GMCH_GREEN

1
2
3
4

8
7
6
5
B

SRN150F-1-GP

FOR Cantiga:500 ohm
Teenah: 392 ohm

RN62

HDA

2

C

3,4
3,4
3,4

DMI

1
R330
80D6R2F-L-GP

GMCH_LCDVDD_ON
LIBG
L_LVBG

14 GMCH_LCDVDD_ON

TV

M_RCOMPN

L_CTRL_DATA
L_DDC_CLK
L_DDC_DATA

GRAPHICS

SA_CS#_0
SA_CS#_1
SB_CS#_0
SB_CS#_1

CLK

2

R331
80D6R2F-L-GP

13
13
12
12

SCD1U10V2KX-4GP

1D8V_S3

M_CKE0
M_CKE1
M_CKE2
M_CKE3

M33
K33
J33

T37
T36

PCI-EXPRESS

layout take note

BC28
AY28
AY36
BB36

LCTLB_DATA
CLK_DDC_EDID
DAT_DDC_EDID

14 CLK_DDC_EDID
14 DAT_DDC_EDID

1

RESERVED#BG23
RESERVED#BF23
RESERVED#BH18
RESERVED#BF18

SA_CKE_0
SA_CKE_1
SB_CKE_0
SB_CKE_1

L_BKLT_CTRL
L_BKLT_EN
L_CTRL_CLK

TPAD30 TP119
TPAD30 TP118

13
13
12
12

2

1

2

BG23
BF23
BH18
BF18

M_CLK_DDR#0
M_CLK_DDR#1
M_CLK_DDR#2
M_CLK_DDR#3

R214

L32
G32
M32

1

2

RESERVED#AY21

2

1

1

AY21

C470
C472
SCD01U16V2KX-3GP SC2D2U6D3V3MX-1-GP

AR24
AR21
AU24
AV20

L_BKLTCTL
GMCH_BL_ON
LCTLA_CLK

14 L_BKLTCTL
30 GMCH_BL_ON

LVDS

SM_RCOMP_VOL
R334
1KR2F-3-GP

SA_CK#_0
SA_CK#_1
SB_CK#_0
SB_CK#_1

M_CLK_DDR0 13
M_CLK_DDR1 13
M_CLK_DDR2 12
M_CLK_DDR3 12

1

RESERVED#B31
RESERVED#B2
RESERVED#M1

AP24
AT21
AV24
AU20

2

2

B31
B2
M1

SA_CK_0
SA_CK_1
SB_CK_0
SB_CK_1

2

1

C475
SCD01U16V2KX-3GP SC2D2U6D3V3MX-1-GP

2

2

R338
3K01R2F-3-GP

C477

RSVD

D

1

1

SM_RCOMP_VOH

DDR CLK/ CONTROL/COMPENSATION

1
2

R339
1KR2F-3-GP

RESERVED#M36
RESERVED#N36
RESERVED#R33
RESERVED#T33
RESERVED#AH9
RESERVED#AH10
RESERVED#AH12
RESERVED#AH13
RESERVED#K12
RESERVED#AL34
RESERVED#AK34
RESERVED#AN35
RESERVED#AM35
RESERVED#T24

1D05V_S0

3 OF 10

U35C

M36
N36
R33
T33
AH9
AH10
AH12
AH13
K12
AL34
AK34
AN35
AM35
T24

1D8V_S3

CANTIGA-GM-GP-U-NF

TVA_DAC
TVB_DAC
TVC_DAC

1
2
3
4

8
7
6
5

SRN75J-1-GP
RN63
GMCH_LCDVDD_ON
GMCH_BL_ON
GFXVR_EN

1
2
3
4

8
7
6
5

1D05V_S0

3D3V_S0

1

71.CNTIG.00U

MCH_TSATN#

LIBG

SRN100KJ-8-GP-U
R216
1
2
2K37R2F-GP

RN33
LCTLB_DATA
LCTLA_CLK
CLK_MCH_OE#

2

R324
56R2J-4-GP

5
6
7
8

4
3
2
1
SRN10KJ-6-GP

Pin Name

Strap Description

Configuration

A

A

CFG20

Digital DisplayPort
(SDVO/DP/HDMI)
Concurrent with
PCIE

Low = Only digital DisplayPort
(SDVO/DP/HDMI) or
PCIE is operational (default)

Wistron Corporation

High = Digital DisplayPort
(SDVO/DP/HDMI) and
PCIE are operating simultaneously via the PEG port

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

Cantiga (2 of 6)
Size

Document Number

Rev

Cathedral Peak II
Date:
5

4

3

2

Sheet

Friday, June 20, 2008
1

7

SB
of

43

4

B

SA_RAS#
SA_CAS#
SA_WE#

BB20
BD20
AY20

M_A_RAS# 13
M_A_CAS# 13
M_A_WE# 13

SA_DM_0
SA_DM_1
SA_DM_2
SA_DM_3
SA_DM_4
SA_DM_5
SA_DM_6
SA_DM_7

AM37
AT41
AY41
AU39
BB12
AY6
AT7
AJ5

M_A_DM0
M_A_DM1
M_A_DM2
M_A_DM3
M_A_DM4
M_A_DM5
M_A_DM6
M_A_DM7

SA_DQS_0
SA_DQS_1
SA_DQS_2
SA_DQS_3
SA_DQS_4
SA_DQS_5
SA_DQS_6
SA_DQS_7
SA_DQS#_0
SA_DQS#_1
SA_DQS#_2
SA_DQS#_3
SA_DQS#_4
SA_DQS#_5
SA_DQS#_6
SA_DQS#_7

AJ44
AT44
BA43
BC37
AW12
BC8
AU8
AM7
AJ43
AT43
BA44
BD37
AY12
BD8
AU9
AM8

M_A_DQS0
M_A_DQS1
M_A_DQS2
M_A_DQS3
M_A_DQS4
M_A_DQS5
M_A_DQS6
M_A_DQS7
M_A_DQS#0
M_A_DQS#1
M_A_DQS#2
M_A_DQS#3
M_A_DQS#4
M_A_DQS#5
M_A_DQS#6
M_A_DQS#7

SA_MA_0
SA_MA_1
SA_MA_2
SA_MA_3
SA_MA_4
SA_MA_5
SA_MA_6
SA_MA_7
SA_MA_8
SA_MA_9
SA_MA_10
SA_MA_11
SA_MA_12
SA_MA_13
SA_MA_14

BA21
BC24
BG24
BH24
BG25
BA24
BD24
BG27
BF25
AW24
BC21
BG26
BH26
BH17
AY25

M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14

M_A_DQS[7..0]

M_A_DQS#[7..0]

M_A_A[14..0]

M_A_DM[7..0] 13

M_A_DQS[7..0] 13

M_A_DQS#[7..0] 13

M_A_A[14..0] 13

M_B_DQ[63..0]
M_B_DQ0
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ7
M_B_DQ8
M_B_DQ9
M_B_DQ10
M_B_DQ11
M_B_DQ12
M_B_DQ13
M_B_DQ14
M_B_DQ15
M_B_DQ16
M_B_DQ17
M_B_DQ18
M_B_DQ19
M_B_DQ20
M_B_DQ21
M_B_DQ22
M_B_DQ23
M_B_DQ24
M_B_DQ25
M_B_DQ26
M_B_DQ27
M_B_DQ28
M_B_DQ29
M_B_DQ30
M_B_DQ31
M_B_DQ32
M_B_DQ33
M_B_DQ34
M_B_DQ35
M_B_DQ36
M_B_DQ37
M_B_DQ38
M_B_DQ39
M_B_DQ40
M_B_DQ41
M_B_DQ42
M_B_DQ43
M_B_DQ44
M_B_DQ45
M_B_DQ46
M_B_DQ47
M_B_DQ48
M_B_DQ49
M_B_DQ50
M_B_DQ51
M_B_DQ52
M_B_DQ53
M_B_DQ54
M_B_DQ55
M_B_DQ56
M_B_DQ57
M_B_DQ58
M_B_DQ59
M_B_DQ60
M_B_DQ61
M_B_DQ62
M_B_DQ63

AK47
AH46
AP47
AP46
AJ46
AJ48
AM48
AP48
AU47
AU46
BA48
AY48
AT47
AR47
BA47
BC47
BC46
BC44
BG43
BF43
BE45
BC41
BF40
BF41
BG38
BF38
BH35
BG35
BH40
BG39
BG34
BH34
BH14
BG12
BH11
BG8
BH12
BF11
BF8
BG7
BC5
BC6
AY3
AY1
BF6
BF5
BA1
BD3
AV2
AU3
AR3
AN2
AY2
AV1
AP3
AR1
AL1
AL2
AJ1
AH1
AM2
AM3
AH3
AJ3

5 OF 10

SB_DQ_0
SB_DQ_1
SB_DQ_2
SB_DQ_3
SB_DQ_4
SB_DQ_5
SB_DQ_6
SB_DQ_7
SB_DQ_8
SB_DQ_9
SB_DQ_10
SB_DQ_11
SB_DQ_12
SB_DQ_13
SB_DQ_14
SB_DQ_15
SB_DQ_16
SB_DQ_17
SB_DQ_18
SB_DQ_19
SB_DQ_20
SB_DQ_21
SB_DQ_22
SB_DQ_23
SB_DQ_24
SB_DQ_25
SB_DQ_26
SB_DQ_27
SB_DQ_28
SB_DQ_29
SB_DQ_30
SB_DQ_31
SB_DQ_32
SB_DQ_33
SB_DQ_34
SB_DQ_35
SB_DQ_36
SB_DQ_37
SB_DQ_38
SB_DQ_39
SB_DQ_40
SB_DQ_41
SB_DQ_42
SB_DQ_43
SB_DQ_44
SB_DQ_45
SB_DQ_46
SB_DQ_47
SB_DQ_48
SB_DQ_49
SB_DQ_50
SB_DQ_51
SB_DQ_52
SB_DQ_53
SB_DQ_54
SB_DQ_55
SB_DQ_56
SB_DQ_57
SB_DQ_58
SB_DQ_59
SB_DQ_60
SB_DQ_61
SB_DQ_62
SB_DQ_63

SB_BS_0
SB_BS_1
SB_BS_2

BC16
BB17
BB33

SB_RAS#
SB_CAS#
SB_WE#

AU17
BG16
BF14

M_B_BS#0 12
M_B_BS#1 12
M_B_BS#2 12
M_B_RAS# 12
M_B_CAS# 12
M_B_WE# 12
D

M_B_DM[7..0]

B

M_A_BS#0 13
M_A_BS#1 13
M_A_BS#2 13

MEMORY

BD21
BG18
AT25

SYSTEM

A

1

U35E
12 M_B_DQ[63..0]

SA_BS_0
SA_BS_1
SA_BS_2

M_A_DM[7..0]

MEMORY

SA_DQ_0
SA_DQ_1
SA_DQ_2
SA_DQ_3
SA_DQ_4
SA_DQ_5
SA_DQ_6
SA_DQ_7
SA_DQ_8
SA_DQ_9
SA_DQ_10
SA_DQ_11
SA_DQ_12
SA_DQ_13
SA_DQ_14
SA_DQ_15
SA_DQ_16
SA_DQ_17
SA_DQ_18
SA_DQ_19
SA_DQ_20
SA_DQ_21
SA_DQ_22
SA_DQ_23
SA_DQ_24
SA_DQ_25
SA_DQ_26
SA_DQ_27
SA_DQ_28
SA_DQ_29
SA_DQ_30
SA_DQ_31
SA_DQ_32
SA_DQ_33
SA_DQ_34
SA_DQ_35
SA_DQ_36
SA_DQ_37
SA_DQ_38
SA_DQ_39
SA_DQ_40
SA_DQ_41
SA_DQ_42
SA_DQ_43
SA_DQ_44
SA_DQ_45
SA_DQ_46
SA_DQ_47
SA_DQ_48
SA_DQ_49
SA_DQ_50
SA_DQ_51
SA_DQ_52
SA_DQ_53
SA_DQ_54
SA_DQ_55
SA_DQ_56
SA_DQ_57
SA_DQ_58
SA_DQ_59
SA_DQ_60
SA_DQ_61
SA_DQ_62
SA_DQ_63

SYSTEM

C

AJ38
AJ41
AN38
AM38
AJ36
AJ40
AM44
AM42
AN43
AN44
AU40
AT38
AN41
AN39
AU44
AU42
AV39
AY44
BA40
BD43
AV41
AY43
BB41
BC40
AY37
BD38
AV37
AT36
AY38
BB38
AV36
AW36
BD13
AU11
BC11
BA12
AU13
AV13
BD12
BC12
BB9
BA9
AU10
AV9
BA11
BD9
AY8
BA6
AV5
AV7
AT9
AN8
AU5
AU6
AT5
AN10
AM11
AM5
AJ9
AJ8
AN12
AM13
AJ11
AJ12

DDR

D

M_A_DQ[63..0]
M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63

2

4 OF 10

U35D
13 M_A_DQ[63..0]

3

DDR

5

CANTIGA-GM-GP-U-NF

CANTIGA-GM-GP-U-NF

71.CNTIG.00U

71.CNTIG.00U

SB_DM_0
SB_DM_1
SB_DM_2
SB_DM_3
SB_DM_4
SB_DM_5
SB_DM_6
SB_DM_7

AM47
AY47
BD40
BF35
BG11
BA3
AP1
AK2

M_B_DM0
M_B_DM1
M_B_DM2
M_B_DM3
M_B_DM4
M_B_DM5
M_B_DM6
M_B_DM7

SB_DQS_0
SB_DQS_1
SB_DQS_2
SB_DQS_3
SB_DQS_4
SB_DQS_5
SB_DQS_6
SB_DQS_7
SB_DQS#_0
SB_DQS#_1
SB_DQS#_2
SB_DQS#_3
SB_DQS#_4
SB_DQS#_5
SB_DQS#_6
SB_DQS#_7

AL47
AV48
BG41
BG37
BH9
BB2
AU1
AN6
AL46
AV47
BH41
BH37
BG9
BC2
AT2
AN5

M_B_DQS0
M_B_DQS1
M_B_DQS2
M_B_DQS3
M_B_DQS4
M_B_DQS5
M_B_DQS6
M_B_DQS7
M_B_DQS#0
M_B_DQS#1
M_B_DQS#2
M_B_DQS#3
M_B_DQS#4
M_B_DQS#5
M_B_DQS#6
M_B_DQS#7

SB_MA_0
SB_MA_1
SB_MA_2
SB_MA_3
SB_MA_4
SB_MA_5
SB_MA_6
SB_MA_7
SB_MA_8
SB_MA_9
SB_MA_10
SB_MA_11
SB_MA_12
SB_MA_13
SB_MA_14

AV17
BA25
BC25
AU25
AW25
BB28
AU28
AW28
AT33
BD33
BB16
AW33
AY33
BH15
AU33

M_B_DM[7..0] 12

M_B_DQS[7..0]

M_B_DQS[7..0] 12

M_B_DQS#[7..0]

M_B_DQS#[7..0] 12

M_B_A[14..0]

C

M_B_A[14..0] 12

M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
M_B_A14

B

A

A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

Cantiga (3 of 6)
Size

Document Number

Rev

SB

Cathedral Peak II
Date: Friday, June 20, 2008
5

4

3

2

Sheet
1

8

of

43

5

4

1

C434

DY

Coupling CAP

AE33
AC33
AA33
Y33
W33
V33
U33
AH28
AF28
AC28
AA28
AJ26
AG26
AE26
AC26
AH25
AG25
AF25
AG24
AJ23
AH23
AF23

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

T32

VCC

G11

1

2

VCC_GMCH_35

D

VCC CORE

2

2
1

C438

2

1
2

DY

SCD1U10V2KX-4GP

Coupling CAP

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

POWER

1

1

1
2

1
2

1
2
1
2

1
2

1
2

1
2

1
2

1

1
2

2

2

1

1
2

Coupling CAP 370 mils from the Edge

SC10U6D3V5MX-3GP

GAP-CLOSE-PWR

Place CAP where
LVDS and DDR2 taps

1

DY

C259

2

C258

2

2

2

1

1

1

1
2

2

2

C255
SC10U6D3V5MX-3GP

2

TC19

DY

SE330U2D5VDM-LGP

SCD1U10V2KX-4GP

Place on the Edge

AM32
AL32
AK32
AJ32
AH32
AG32
AE32
AC32
AA32
Y32
W32
U32
AM30
AL30
AK30
AH30
AG30
AF30
AE30
AC30
AB30
AA30
Y30
W30
V30
U30
AL29
AK29
AJ29
AH29
AG29
AE29
AC29
AA29
Y29
W29
V29
AL28
AK28
AL26
AK26
AK25
AK24
AK23

VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF

C

CANTIGA-GM-GP-U-NF

1

1
2

C491

C492

2

1

C488

2

1

C468

SC1U10V3KX-3GP

2

C178

SC1U10V3KX-3GP

2

C164

SCD47U16V3ZY-3GP

2

C464

SCD22U10V2KX-1GP
2
1

1

1

71.CNTIG.00U

SCD22U10V2KX-1GP

VCC SM LF

VCC GFX

C252

DY

SC10U6D3V5MX-3GP

C266

AV44 SM_LF1_GMCH
BA37 SM_LF2_GMCH
AM40 SM_LF3_GMCH
AV21 SM_LF4_GMCH
AY5 SM_LF5_GMCH
AM10 SM_LF6_GMCH
BB13 SM_LF7_GMCH
SCD1U10V2KX-4GP

CANTIGA-GM-GP-U-NF

C253

SC10U6D3V5MX-3GP

C254

DY

1

1

1

1D8V_S3

VCC_SM_LF
VCC_SM_LF
VCC_SM_LF
VCC_SM_LF
VCC_SM_LF
VCC_SM_LF
VCC_SM_LF

1D05V_S0

VCC NCTF

VCC GFX NCTF

C236
SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SC1U10V3ZY-6GP

SCD1U10V2KX-4GP

SC10U6D3V5MX-3GP

VCC SM

C248

DY

SCD1U10V2KX-4GP

C233

DY

C436

SCD1U10V2KX-4GP

C249

C435

SC10U6D3V5MX-3GP

C157

DY

DY

C141

SC10U6D3V5MX-3GP

C244

C142

AG34
AC34
AB34
AA34
Y34
V34
U34
AM33
AK33
AJ33
AG33
AF33

FOR VCC SM

VCC_AXG_SENSE
VSS_AXG_SENSE

71.CNTIG.00U

C225

Place on the Edge

SCD1U10V2KX-4GP

AJ14
AH14

38 VCC_AXG_SENSE
38 VSS_AXG_SENSE

DY

SC10U6D3V5MX-3GP

C

DY

SC10U6D3V5MX-3GP

VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG

C167

TC18

SCD1U10V2KX-4GP

Y26
AE25
AB25
AA25
AE24
AC24
AA24
Y24
AE23
AC23
AB23
AA23
AJ21
AG21
AE21
AC21
AA21
Y21
AH20
AF20
AE20
AC20
AB20
AA20
T17
T16
AM15
AL15
AE15
AJ15
AH15
AG15
AF15
AB15
AA15
Y15
V15
U15
AN14
AM14
U14
T14

VCC_GFXCORE

DY

VCC_GFXCORE

SE220U2D5VDM-3GP

6 OF 10

U35F

C437

SC10U6D3V5MX-3GP

VCC_SM/NC
VCC_SM/NC
VCC_SM/NC
VCC_SM/NC
VCC_SM/NC
VCC_SM/NC
VCC_SM/NC

1D05V_S0

SCD1U10V2KX-4GP

BA36
BB24
BD16
BB21
AW16
AW13
AT13

VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF

SC10U6D3V5MX-3GP

VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM

W28
V28
W26
V26
W25
V25
W24
V24
W23
V23
AM21
AL21
AK21
W21
V21
U21
AM20
AK20
W20
U20
AM19
AL19
AK19
AJ19
AH19
AG19
AF19
AE19
AB19
AA19
Y19
W19
V19
U19
AM17
AK17
AH17
AG17
AF17
AE17
AC17
AB17
Y17
W17
V17
AM16
AL16
AK16
AJ16
AH16
AG16
AF16
AE16
AC16
AB16
AA16
Y16
W16
V16
U16

SC10U6D3V5MX-3GP

D

AP33
AN33
BH32
BG32
BF32
BD32
BC32
BB32
BA32
AY32
AW32
AV32
AU32
AT32
AR32
AP32
AN32
BH31
BG31
BF31
BG30
BH29
BG29
BF29
BD29
BC29
BB29
BA29
AY29
AW29
AV29
AU29
AT29
AR29
AP29

POWER

U35G

667MTS 2400mA
800MTS 3000mA

B

2

VCC_GFXCORE

7 OF 10
1D8V_S3

3

B

place near Cantiga

A

A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size

Cantiga (4 of 6)

Document Number

Rev

SB

Cathedral Peak II
Date: Friday, June 20, 2008
5

4

3

2

Sheet
1

9

of

43

5

1D05V_S0

VCCA_SM_CK
VCCA_SM_CK
VCCA_SM_CK
VCCA_SM_CK
VCCA_SM_CK
VCCA_SM_CK_NCTF
VCCA_SM_CK_NCTF
VCCA_SM_CK_NCTF
VCCA_SM_CK_NCTF
VCCA_SM_CK_NCTF
VCCA_SM_CK_NCTF
VCCA_SM_CK_NCTF
VCCA_SM_CK_NCTF

1
2

1
2

VCC_PEG
VCC_PEG
VCC_PEG
VCC_PEG
VCC_PEG

V48
U48
V47
U47
U46

VCC_DMI
VCC_DMI
VCC_DMI
VCC_DMI

AH48
AF48
AH47
AG47

2
1

1

1

C276
SC1KP50V2KX-1GP

4

B

C275
SC1U10V3KX-3GP

A8
L1
AB2

C185
C445
SCD47U6D3V2KX-GP

1

1

2

2

C202
1

C274
SC10U6D3V5MX-3GP

2

1
2

1
2

C251

C440
SC10U6D3V5MX-3GP

DY
1D05V_S0

1

C263

DY

1

1

VTTLF1
VTTLF2
VTTLF3

2

1
2

VTTLF
VTTLF
VTTLF

C439

C441
SC10U6D3V5MX-3GP

2

VCCD_LVDS
VCCD_LVDS

456mA

C262

2

VCCD_PEG_PLL

C447

DY

2

VCCD_HPLL

1782mA

2

1

SCD1U10V2KX-4GP

2

1D8V_S3

1

3D3V_HV_S0

106mA

2

R217
1
2
0R0603-PAD

A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

Cantiga (5 of 6)
Size

Document Number

Rev

SB

Cathedral Peak II
Date: Friday, June 20, 2008

5

1

1
2

1
2

1
2

AXF
A CK

SM CK

VCC_HV
VCC_HV
VCC_HV

VTTLF

VCCD_QDAC

LVDS

1
2

1
2

K47
C35
B35
A35

DMI

2
1
2
1

VCC_TX_LVDS

1

C222
SC10U6D3V5MX-3GP

119mA

SC10U6D3V5MX-3GP

2

VCCD_TVDAC

1D8V_SUS_DLVDS
C271

1D8V_SUS_SM_CK_RC

1D05V_S0

71.CNTIG.00U

1
2
0R0603-PAD

2

1D8V_TXLVDS_S3

CANTIGA-GM-GP-U-NF
R212

60.3mA

M38
L37

R179
1
2
0R0603-PAD

1R2F-GP

SC22U6D3V5MX-2GP

C483
SCD1U10V2KX-4GP

BF21
BH20
BG20
BF20

SCD1U10V2KX-4GP

1D8V_S3

L28
AF1

1D05V_RUN_PEGPLL AA47

C186

C239
SCD1U10V2KX-4GP

M25

1D8V_S3

2

VCC_HDA

VCC_SM_CK
VCC_SM_CK
VCC_SM_CK
VCC_SM_CK

R183
1
C230
SCD1U10V2KX-4GP

SCD47U6D3V2KX-GP

A

C480

C

124mA

SCD47U6D3V2KX-GP

180ohm 100MHz

2
1
0R0402-PAD

DY

SC22U6D3V5MX-2GP

1D5VRUN_QDAC

SCD1U10V2KX-4GP

68.00206.041

2

R349
10R2F-L-GP

C460
SC10U6D3V5MX-3GP

2

A32

50mA

157.2mA

1D5VRUN_QDAC

2
PBY160808T-181Y-GP

C467

B22
B21
A21

HV

VCCA_TV_DAC
VCCA_TV_DAC

VCC_AXF
VCC_AXF
VCC_AXF

PEG

B24
A24

D TV/CRT

C469
SCD01U16V2KX-3GP

1D05V_SUS_MCH_PLL2

L2

1

2

POWER

TV

79mA

1

C471

2

1
2

DY

1D5VRUN_TVDAC
C242
SCD1U10V2KX-4GP

3D3V_HV_S0
R350

1D05V_HV_S0 1

1D05V_S0

SC4D7U6D3V3KX-GP

R196
1
2
0R0603-PAD

3D3V_S0

2
BAT54-7-F-GP
3

1

1
2

2

DY

3D3VTVDAC

C484
SCD1U10V2KX-4GP

35mA

D22

1D8V_SUS_SM_CK

1D5VRUN_TVDAC

1D5V_S0

CRT

AP28
AN28
AP25
AN25
AN24
AM28
AM26
AM25
AL25
AM24
AL24
AM23
AL23

D

2

1
2

1
2

1

VCCA_SM
VCCA_SM
VCCA_SM
VCCA_SM
VCCA_SM
VCCA_SM
VCCA_SM
VCCA_SM
VCCA_SM

C175
SCD1U10V2KX-4GP

322mA

HDA

L14
1
2
0R0603-PAD

50mA
1

68.00217.521

220ohm 100MHz

1

1
2

3D3V_S0_DAC

1D05V_RUN_PEGPLL

2
FCM1608CF-221T02-GP

AR20
AP20
AN20
AR17
AP17
AN17
AT16
AR16
AP16

C187

2

1

1

1
1
2
2

2

1

1
2
1
2

M_VCCA_MPLL

1

2
1
2

DY

139.2mA

2

1
1

C227

VCCA_PEG_PLL

1

C260

1D05V_S0

C241
SCD1U10V2KX-4GP

L15

B

C245

SCD1U10V2KX-4GP

1D05V_S0

DY

C446
SCD1U10V2KX-4GP

VCCA_PEG_BG

C256

1D05V_SM_CK
C237

SC2D2U6D3V3MX-1-GP

DY

C442

SC10U6D3V5MX-3GP

120ohm 100MHz

AD48

VSSA_LVDS

26mA

1
2
R203
0R0603-PAD

C444
SCD1U10V2KX-4GP

SC10U6D3V5MX-3GP

68.00217.161

2

1
2

1
2

1

C443

120ohm 100MHz
L12
1
2
FCM1608KF-1-GP

1D05V_S0

M_VCCA_HPLL
SC4D7U6D3V3KX-GP

68.00217.161

24mA

VCCA_LVDS

C261

SC1U10V3KX-3GP

L13
1
2
FCM1608KF-1-GP

C219

SC1U10V3KX-3GP

1D05V_SUS_MCH_PLL2

J48

1D05V_RUN_PEGPLL AA48
1D05V_SM

C224

DY

VCCA_MPLL

C482
SCD1U10V2KX-4GP

720mA
C171

AE1

13.2mA
J47
VCCA_PEG_BG

1D05V_S0

1
2
R191
0R0603-PAD

VCCA_HPLL

1D8V_TXLVDS_S3

SC1U10V3KX-3GP

2

DY

AD1

M_VCCA_MPLL

R351
0R0402-PAD
1

M_VCCA_DPLLB
C485
SCD1U10V2KX-4GP

VCCA_DPLLB

M_VCCA_HPLL

DY

SC4D7U6D3V3KX-GP

R310
0R0603-PAD

2

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

1D05V_S0

65mA
1

C489

C277
SC1KP50V2KX-1GP

DY

VCCA_DPLLA

L48

C257

SCD1U10V2KX-4GP

SC10U6D3V5MX-3GP

R357
1
2
0R0603-PAD

C486
SCD1U10V2KX-4GP
1D5V_S0

2

C490

F47

M_VCCA_DPLLB

U13
T13
U12
T12
U11
T11
U10
T10
U9
T9
U8
T8
U7
T7
U6
T6
U5
T5
V3
U3
V2
U2
T2
V1
U1

2

1D8V_TXLVDS_S3

M_VCCA_DPLLA

1
2
0R0603-PAD

C

1

65mA

R358

M_VCCA_DPLLA

VTT

2

C474
SCD1U10V2KX-4GP

PLL

1

1D05V_S0

VCCA_DAC_BG
VSSA_DAC_BG

A LVDS

5mA

1
2
R342
0R0603-PAD

M_VCCA_DAC_BG A25
B25

VCCA_CRT_DAC
VCCA_CRT_DAC

VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT

A PEG

2

3D3V_S0_DAC

B27
A26

A SM

1

1
2

1
2

1
2
D

C479
SCD1U10V2KX-4GP

SCD47U6D3V2KX-GP

DY

C478

SC4D7U6D3V3KX-GP

EC153
SC1U16V3ZY-GP

RT9198-33PBR-GP
EC154
74.09198.G7F
SC1U16V3ZY-GP

C476
SC22U16V0KX-1GP

SC2D2U6D3V3MX-1-GP

4

852mA

8 OF 10

U35H

SC4D7U6D3V3KX-GP

5

NC#4

3D3V_CRTDAC_S0

SC4D7U6D3V3KX-GP

VOUT

73mA

1
2
R346
0R0603-PAD

SCD01U16V2KX-3GP

VIN
GND
EN/EN#

1

3D3V_S0_DAC

3D3V_S0_DAC

U36

1
2
3

2

1

Imax = 300 mA

3

2

5V_S0

4

3

2

Sheet
1

10

of

43

5

4

3

2

10 OF 10

U35J

B

A

VSS

AM36
AE36
P36
L36
J36
F36
B36
AH35
AA35
Y35
U35
T35
BF34
AM34
AJ34
AF34
AE34
W34
B34
A34
BG33
BC33
BA33
AV33
AR33
AL33
AH33
AB33
P33
L33
H33
N32
K32
F32
C32
A31
AN29
T29
N29
K29
H29
F29
A29
BG28
BD28
BA28
AV28
AT28
AR28
AJ28
AG28
AE28
AB28
Y28
P28
K28
H28
F28
C28
BF26
AH26
AF26
AB26
AA26
C26
B26
BH25
BD25
BB25
AV25
AR25
AJ25
AC25
Y25
N25
L25
J25
G25
E25
BF24
AD12
AY24
AT24
AJ24
AH24
AF24
AB24
R24
L24
K24
J24
G24
F24
E24
BH23
AG23
Y23
B23
A23
AJ6

BA16

VSS

AU16
AN16
N16
K16
G16
E16
BG15
AC15
W15
A15
BG14
AA14
C14
BG13
BC13
BA13

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

AN13
AJ13
AE13
N13
L13
G13
E13
BF12
AV12
AT12
AM12
AA12
J12
A12
BD11
BB11
AY11
AN11
AH11

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

Y11
N11
G11
C11
BG10
AV10
AT10
AJ10
AE10
AA10
M10
BF9
BC9
AN9
AM9
AD9
G9
B9
BH8
BB8
AV8
AT8

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSS

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

AH8
Y8
L8
E8
B8
AY7
AU7
AN7
AJ7
AE7
AA7
N7
J7
BG6
BD6
AV6
AT6
AM6
M6
C6
BA5
AH5
AD5
Y5
L5
J5
H5
F5
BE4

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

BC3
AV3
AL3
R3
P3
F3
BA2
AW2
AU2
AR2
AP2
AJ2
AH2
AF2
AE2
AD2
AC2
Y2
M2
K2
AM1
AA1
P1
H1

VSS
VSS
VSS
VSS

U24
U28
U25
U29

VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF

AF32
AB32
V32
AJ30
AM29
AF29
AB29
U26
U23
AL20
V20
AC19
AL17
AJ17
AA17
U17

NCTF_VSS_SCB#BH48
NCTF_VSS_SCB#BH1
NCTF_VSS_SCB#A48
NCTF_VSS_SCB#C1
NCTF_VSS_SCB#A3

BH48
BH1
A48
C1
A3

VSS NCTF

C

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

NC

D

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

NCTF TEST PIN:
A3,C1,A48,BH1,BH48

AU48
AR48
AL48
BB47
AW47
AN47
AJ47
AF47
AD47
AB47
Y47
T47
N47
L47
G47
BD46
BA46
AY46
AV46
AR46
AM46
V46
R46
P46
H46
F46
BF44
AH44
AD44
AA44
Y44
U44
T44
M44
F44
BC43
AV43
AU43
AM43
J43
C43
BG42
AY42
AT42
AN42
AJ42
AE42
N42
L42
BD41
AU41
AM41
AH41
AD41
AA41
Y41
U41
T41
M41
G41
B41
BG40
BB40
AV40
AN40
H40
E40
AT39
AM39
AJ39
AE39
N39
L39
B39
BH38
BC38
BA38
AU38
AH38
AD38
AA38
Y38
U38
T38
J38
F38
C38
BF37
BB37
AW37
AT37
AN37
AJ37
H37
C37
BG36
BD36
AK15
AU36

BG21
L12
AW21
AU21
AP21
AN21
AH21
AF21
AB21
R21
M21
J21
G21
BC20
BA20
AW20
AT20
AJ20
AG20
Y20
N20
K20
F20
C20
A20
BG19
A18
BG17
BC17
AW17
AT17
R17
M17
H17
C17

VSS SCB

9 OF 10

U35I

1

NC#E1
NC#D2
NC#C3
NC#B4
NC#A5
NC#A6
NC#A43
NC#A44
NC#B45
NC#C46
NC#D47
NC#B47
NC#A46
NC#F48
NC#E48
NC#C48
NC#B48

D

C

B

TP163
TP155
TP164
TP156
TP157

TPAD30
TPAD30
TPAD30
TPAD30
TPAD30

E1
D2
C3
B4
A5
A6
A43
A44
B45
C46
D47
B47
A46
F48
E48
C48
B48

A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

CANTIGA-GM-GP-U-NF

CANTIGA-GM-GP-U-NF

71.CNTIG.00U

71.CNTIG.00U

Cantiga (6 of 6)
Size

Document Number

Rev

SB

Cathedral Peak II
Date: Friday, June 20, 2008
5

4

3

2

Sheet
1

11

of

43

A

B

C

D

E

DM1

SRN56J-5-GP

Decoupling Capacitor
Put decap near power(0.9V)
and pull-up resistor

DDR_VREF_S3

VREF
VSS

202

GND

GND

201

MH1

MH1

MH2

MH2

1
2

2

2

SCD1U16V2ZY-2GP

DY

8 M_B_DQS#[7..0]

C172

SCD1U16V2ZY-2GP

2

1

1

1

1

C220

SCD1U16V2ZY-2GP

2

C160

SCD1U16V2ZY-2GP

DY

C217

SCD1U16V2ZY-2GP

2

C221

SCD1U16V2ZY-2GP

2

C197

SCD1U16V2ZY-2GP

2

C215

SCD1U16V2ZY-2GP

DY

1

1

1

C196

SCD1U16V2ZY-2GP

2

C166

SCD1U16V2ZY-2GP

2

C180

SCD1U16V2ZY-2GP

2

1

1

1

2

C205

8 M_B_DQS[7..0]

DDR_VREF_S3_1

1
2

2

DY

M_ODT2
M_ODT3

C280
SCD1U16V2ZY-2GP

C281
SC4D7U6D3V3KX-GP

1

7
7

3
8
9
12
15
18
21
24
27
28
33
34
39
40
41
42
47
48
53
54
59
60
65
66
71
72
77
78
121
122
127
128
132
133
138
139
144
145
149
150
155
156
161
162
165
168
171
172
177
178
183
184
187
190
193
196

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

1D8V_S3

Place these Caps near DM1

1D8V_S3

C449

C203

DY

C451

DY

C461

DY

C174

C456

C199

DY

1

M_B_BS#0
M_B_CAS#
M_CS3#
M_CS2#

3

C158

2

1
2
3
4

DY

1

RN12

8
7
6
5

81
82
87
88
95
96
103
104
111
112
117
118

C117
SCD1U16V2ZY-2GP

2

OTD0
OTD1

1
2

SRN56J-5-GP

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

1

2

1

114
119

M_B_A14
M_B_A11
M_B_A7
M_B_A6

2
R114
10KR2J-3-GP

C452

2

1
2
3
4

DDRB_SA0

1

DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7

RN27

3

198
200
50
69
83
120
163

2

13
31
51
70
131
148
169
188

SRN56J-5-GP

8
7
6
5

SA0
SA1
NC#50
NC#69
NC#83
NC#120
NC#163/TEST

3D3V_S0

1

M_B_DQS0
M_B_DQS1
M_B_DQS2
M_B_DQS3
M_B_DQS4
M_B_DQS5
M_B_DQS6
M_B_DQS7

M_B_BS#1
M_B_A2
M_B_A0
M_B_A4

SMBD_ICH 3,13,20
SMBC_ICH 3,13,20

2

1
2
3
4

199

1

DQS0#
DQS1#
DQS2#
DQS3#
DQS4#
DQS5#
DQS6#
DQS7#

RN22

195
197

SC2D2U6D3V3MX-1-GP

11
29
49
68
129
146
167
186

SRN56J-5-GP

8
7
6
5

SDA
SCL
VDDSPD

M_CLK_DDR3 7
M_CLK_DDR#3 7
M_B_DM[7..0] 8

M_B_DM0
M_B_DM1
M_B_DM2
M_B_DM3
M_B_DM4
M_B_DM5
M_B_DM6
M_B_DM7

SCD1U16V2ZY-2GP

M_B_DQS#0
M_B_DQS#1
M_B_DQS#2
M_B_DQS#3
M_B_DQS#4
M_B_DQS#5
M_B_DQS#6
M_B_DQS#7

M_B_A13
M_ODT2
M_ODT3
M_B_RAS#

10
26
52
67
130
147
170
185

SC2D2U6D3V3MX-1-GP

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63

8 M_B_DQ[63..0]

DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7

2

8
7
6
5

SRN56J-5-GP
RN15
1
2
3
4

M_CLK_DDR2 7
M_CLK_DDR#2 7

164
166

SCD1U16V2ZY-2GP

BA0
BA1

5
7
17
19
4
6
14
16
23
25
35
37
20
22
36
38
43
45
55
57
44
46
56
58
61
63
73
75
62
64
74
76
123
125
135
137
124
126
134
136
141
143
151
153
140
142
152
154
157
159
173
175
158
160
174
176
179
181
189
191
180
182
192
194

M_B_DQ0
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ7
M_B_DQ8
M_B_DQ9
M_B_DQ10
M_B_DQ11
M_B_DQ12
M_B_DQ13
M_B_DQ14
M_B_DQ15
M_B_DQ16
M_B_DQ17
M_B_DQ18
M_B_DQ19
M_B_DQ20
M_B_DQ21
M_B_DQ22
M_B_DQ23
M_B_DQ24
M_B_DQ25
M_B_DQ26
M_B_DQ27
M_B_DQ28
M_B_DQ29
M_B_DQ30
M_B_DQ31
M_B_DQ32
M_B_DQ33
M_B_DQ34
M_B_DQ35
M_B_DQ36
M_B_DQ37
M_B_DQ38
M_B_DQ39
M_B_DQ40
M_B_DQ41
M_B_DQ42
M_B_DQ43
M_B_DQ44
M_B_DQ45
M_B_DQ46
M_B_DQ47
M_B_DQ48
M_B_DQ49
M_B_DQ50
M_B_DQ51
M_B_DQ52
M_B_DQ53
M_B_DQ54
M_B_DQ55
M_B_DQ56
M_B_DQ57
M_B_DQ58
M_B_DQ59
M_B_DQ60
M_B_DQ61
M_B_DQ62
M_B_DQ63

30
32

CK1
CK1#

SC2D2U6D3V3MX-1-GP

107
106

CK0
CK0#

4

1

SRN56J-5-GP
RN18
1 M_B_A3
2 M_B_A1
3 M_B_A10
4 M_B_WE#

M_CKE2 7
M_CKE3 7

2

8
7
6
5

TPAD30 TP111

79
80

1

SRN56J-5-GP
RN31
1 M_CKE3
2 M_B_A12
3 M_B_BS#2
4 M_CKE2

M_CS2# 7
M_CS3# 7

CKE0
CKE1

2

8
7
6
5

110
115

1

M_B_A8
M_B_A9
M_B_A5

M_B_RAS# 8
M_B_WE# 8
M_B_CAS# 8

CS0#
CS1#

2

1
2
3
4

108
109
113

SCD1U16V2ZY-2GP

M_B_BS#0
M_B_BS#1

Put decap near power(0.9V) and pull-up resistor

RN25

8
7
6
5

RAS#
WE#
CAS#

SC2D2U6D3V3MX-1-GP

8
8

4

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15
A16/BA2

SCD1U16V2ZY-2GP

M_B_BS#2

PARALLEL TERMINATION

DDR_VREF_S3

SC2D2U6D3V3MX-1-GP

8

102
101
100
99
98
97
94
92
93
91
105
90
89
116
86
84
85

1

M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
M_B_A14
M_B_A15

2

M_B_A[14..0]

REVERSE TYPE

8

DDR2-200P-23-GP-U1

62.10017.A71

High 9.2mm
2nd: 62.10017.B51
1

1

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

DDR2 Socket 0 (DM1)
Size

Document Number

Rev

SB

Cathedral Peak II
Date:
A

B

C

D

Sheet

Friday, June 20, 2008
E

12

of

43

B

C

DM2

M_ODT1
M_CS1#

RN24

1
2
3
4

M_A_A9
M_A_A14
M_A_A5
M_A_A3

SRN56J-5-GP
RN28

3

8
7
6
5

1
2
3
4

M_A_A6
M_A_A7
M_A_A11
M_CKE1

SRN56J-5-GP
RN19

8
7
6
5

1
2
3
4

M_A_BS#0
M_A_A1
M_A_A10
M_A_WE#

SRN56J-5-GP

Decoupling Capacitor

1

1
2

C173

C170

2

1

DY

2

2

2

2

1

1

1

1
2

C201

M_A_DQS0
M_A_DQS1
M_A_DQS2
M_A_DQS3
M_A_DQS4
M_A_DQS5
M_A_DQS6
M_A_DQS7

13
31
51
70
131
148
169
188

DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7

114
119

ODT0
ODT1

1
2

1

M_ODT0
M_ODT1

C279

202

SCD1U16V2ZY-2GP

2

1

7
7

2

/DQS0
/DQS1
/DQS2
/DQS3
/DQS4
/DQS5
/DQS6
/DQS7

VREF
VSS
GND

GND

201

Place these Caps near DM2

1D8V_S3

C200

DY

C454

C458

C457

DY

C169

2

C448

DY

C193

C179

DY

C216
SCD1U16V2ZY-2GP

DDR_VREF_S3_1

DY

11
29
49
68
129
146
167
186

3
8
9
12
15
18
21
24
27
28
33
34
39
40
41
42
47
48
53
54
59
60
65
66
71
72
77
78
121
122
127
128
132
133
138
139
144
145
149
150
155
156
161
162
165
168
171
172
177
178
183
184
187
190
193
196

1D8V_S3

SCD1U16V2ZY-2GP

8 M_A_DQS[7..0]

C278
SC4D7U6D3V3KX-GP

M_A_DQS#0
M_A_DQS#1
M_A_DQS#2
M_A_DQS#3
M_A_DQS#4
M_A_DQS#5
M_A_DQS#6
M_A_DQS#7

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

3

SCD1U16V2ZY-2GP

8 M_A_DQS#[7..0]

81
82
87
88
95
96
103
104
111
112
117
118

DY

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

2

C192

SCD1U16V2ZY-2GP

DY

SCD1U16V2ZY-2GP

2

C223

SCD1U16V2ZY-2GP

DY

SCD1U16V2ZY-2GP

2

1

1

1

1

C218
SCD1U16V2ZY-2GP

DY

SCD1U16V2ZY-2GP

2

C209

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

DY

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

C115
SCD1U16V2ZY-2GP

SC2D2U6D3V3MX-1-GP

C181

198
200
50
69
83
120
163

3D3V_S0

SC2D2U6D3V3MX-1-GP

C207

SA0
SA1
NC#50
NC#69
NC#83
NC#120
NC#163/TEST

SMBD_ICH 3,12,20
SMBC_ICH 3,12,20

SC2D2U6D3V3MX-1-GP

C189

199

SC2D2U6D3V3MX-1-GP

C191

2

Put decap near power(0.9V)
and pull-up resistor

195
197

SC2D2U6D3V3MX-1-GP

DDR_VREF_S3

SDA
SCL
VDDSPD

M_CLK_DDR1 7
M_CLK_DDR#1 7
M_A_DM[7..0] 8

1

M_A_CAS#

SRN56J-5-GP

8
7
6
5

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63

M_A_DM0
M_A_DM1
M_A_DM2
M_A_DM3
M_A_DM4
M_A_DM5
M_A_DM6
M_A_DM7

2

RN13

1
2
3
4

BA0
BA1

5
7
17
19
4
6
14
16
23
25
35
37
20
22
36
38
43
45
55
57
44
46
56
58
61
63
73
75
62
64
74
76
123
125
135
137
124
126
134
136
141
143
151
153
140
142
152
154
157
159
173
175
158
160
174
176
179
181
189
191
180
182
192
194

10
26
52
67
130
147
170
185

1

8 M_A_DQ[63..0]

SRN56J-5-GP

8
7
6
5

107
106
M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63

DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7

2

M_A_BS#0
M_A_BS#1

164
166

1

8
8

M_CLK_DDR0 7
M_CLK_DDR#0 7

CK1
/CK1

2

M_A_BS#1
M_A_A0
M_A_A2
M_A_A4

M_CKE0 7
M_CKE1 7

30
32

1

1
2
3
4

M_A_BS#2

79
80

CK0
/CK0

2

RN23

8
7
6
5

8

CKE0
CKE1

4

1

TPAD30 TP112

SRN56J-5-GP

M_CS0# 7
M_CS1# 7

2

M_A_A13
M_ODT0
M_CS0#
M_A_RAS#

110
115

1

1
2
3
4

/CS0
/CS1

2

8
7
6
5

M_A_RAS# 8
M_A_WE# 8
M_A_CAS# 8

1

RN16

108
109
113

2

SRN56J-5-GP

/RAS
/WE
/CAS

1

1
2
3
4

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15
A16/BA2

2

8
7
6
5

M_A_A12
M_CKE0
M_A_BS#2
M_A_A8

102
101
100
99
98
97
94
92
93
91
105
90
89
116
86
84
85

1

M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_A15

2

M_A_A[14..0]

Put decap near power(0.9V) and pull-up resistor

RN29

E

1

8

4

2

PARALLEL TERMINATION

DDR_VREF_S3

D

REVERSE TYPE

A

SKT-SODIMM20022U2GP

62.10017.691

High 5.2mm
2nd: 62.10017.911

1

1

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

DDR2 Socket 1 (DM2)
Size

Document Number

Rev

Cathedral Peak II
Date:
A

B

C

D

Sheet

Friday, June 20, 2008
E

13

SB
of

43

LCD/INVERTER/CCD CONN

Inverter Pin

BRIGHTNESS_CN
2BLON_OUT_1

33R2J-2-GP
DCBATOUT
F2

1
2

C307

PWR_INVERTER

2

1

POLYSW-1D1A24V-GP

69.50007.A31

ACES-CONN40A-2GP

EC86
SCD1U50V3ZY-GP

SC10U25V6KX-1GP

DY

2nd: 20.F1048.040
3nd: 20.F1084.040

DY

2

BRIGHTNESS_CN

R241
1
0R2J-2-GP

R242 1
2
0R0402-PAD

BRIGHTNESS 30

1

BLON_OUT 16,30

2

1
2
4
3

SRN2K2J-1-GP

GND

Cover Up Switch
3D3V_AUX_S5

CCD Pin
Pin

Symbol

1

CCD_PWR

2

USB-

3

USB+

4

GND

5

GND

3

R253
10KR2J-3-GP

DY

U4

OUT

2

VDD

1

LID_CLOSE#

LID_CLOSE# 30

GND
EC93
SCD1U16V2ZY-2GP

ME268-002-GP

DY

74.00268.07B

C305

74.00268.A7B
74.00268.C7B

SC100P50V2JN-3GP

SC100P50V2JN-3GP

DY
RN1

GND

6

L_BKLTCTL 7

BLON_OUT
C306

BLON

5

EC92
SCD1U16V2ZY-2GP

20.F0993.040

3D3V_S0

Brightness

4

1

1
2

1

GMCH_TXBCLK+ 7
GMCH_TXBCLK- 7
GMCH_TXBOUT2+ 7
GMCH_TXBOUT2- 7
GMCH_TXBOUT1+ 7
GMCH_TXBOUT1- 7
GMCH_TXBOUT0+ 7
GMCH_TXBOUT0- 7
GMCH_TXACLK+ 7
GMCH_TXACLK- 7
GMCH_TXAOUT2+ 7
GMCH_TXAOUT2- 7
GMCH_TXAOUT1+ 7
GMCH_TXAOUT1- 7
GMCH_TXAOUT0+ 7
GMCH_TXAOUT0- 7

3

2

BLON_OUT

GMCH_TXBCLK+
GMCH_TXBCLKGMCH_TXBOUT2+
GMCH_TXBOUT2GMCH_TXBOUT1+
GMCH_TXBOUT1GMCH_TXBOUT0+
GMCH_TXBOUT0GMCH_TXACLK+
GMCH_TXACLKGMCH_TXAOUT2+
GMCH_TXAOUT2GMCH_TXAOUT1+
GMCH_TXAOUT1GMCH_TXAOUT0+
GMCH_TXAOUT0-

Vin

1

CCD_PWR
R457
1

DY

C5

SC10U10V5ZY-1GP

Vin

2

1

3D3V_S0

3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39

C3
DY SCD1U25V3ZY-1GP
SCD1U25V3ZY-1GP

2

4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42

C4

Symbol

1

2

USBPP8_R

CLK_DDC_EDID
DAT_DDC_EDID

7 CLK_DDC_EDID
7 DAT_DDC_EDID

1
2

R7
2
1
0R0402-PAD

USBPP8

1

18

2

41
2

USBPN8_R

Pin

2

LCD1

1

R6
2
1
0R0402-PAD

USBPN8

2

18

1

LCDVDD

DY

CLK_DDC_EDID
DAT_DDC_EDID
3D3V_S0
LCDVDD
U1

Layout 40 mil

1

9
8
7
6
5
1

GND
IN#8
IN#7
IN#6
IN#5

G5281RC1U-GP

74.05281.093

2

1
2

IN#1
OUT
EN
GND

C2
SCD1U16V2ZY-2GP

SC4D7U6D3V3MX-2GP

DY

DY

2

C6

1

GMCH_LCDVDD_ON

7 GMCH_LCDVDD_ON

1
2
3
4

C7
SC4D7U6D3V3MX-2GP

F3

2

3D3V_S0

FUSE-1D1A6V-8GP

69.41101.021
F4

1
2

C309
SC4D7U10V5ZY-3GP

2

1

CCD_PWR

1
C308
SCD1U16V2ZY-2GP

DY

2

3D3V_S0

FUSE-4A32V-6-GP

69.44001.041

Wistron Corporation

Consumption stock

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

LCD CONN
Size

Document Number

Rev

SB

Cathedral Peak II
Date: Friday, June 20, 2008

Sheet

14

of

43

A

B

Layout Note:
Place these resistors
close to the CRT-out
connector

D

E

Hsync & Vsync level shift
5V_S0

Ferrite bead impedance: 10 ohm@100MHz
L7

1

GMCH_RED

CRT_R

2
FCB1608CF-GP

1

7

C

68.00230.021
2

L6

C314
SCD1U16V2ZY-2GP

4

4

68.00230.021
L4

D20

3

7

CRT_VSYNC1

U32B
TSAHCT125PW-GP

7

1

C341

CRT_HSYNC1

3
U32A
TSAHCT125PW-GP

6

DY

C342

2

1

2

CRT_R 3

DY

SC18P50V2JN-1-GP

5V_S0

Layout Note:
* Must be a ground return path between this ground and the ground on
the VGA connector.
Pi-filter & 150 Ohm pull-down resistors should be as close as to CRT
CONN. RGB will hit 75 Ohm first, pi-filter, then CRT CONN.

4

14
5

7 GMCH_VSYNC

2

1
2

1
2

2

1

1
2

2

2

8
7
6
5

2

7 GMCH_HSYNC

C321

SC18P50V2JN-1-GP

1
2
3
4

C326

SC6D8P50V2DN-GP

68.00230.021

C336

SC6D8P50V2DN-GP

DY

CRT_B

2
FCB1608CF-GP

SC6D8P50V2DN-GP

DY

EC96

SC3P50V2CN-1-GP

DY

EC106
SC3P50V2CN-1-GP

SC3P50V2CN-1-GP

RN73
SRN150F-1-GP

EC109

1

1

GMCH_BLUE

1

7

1

CRT_G

2
FCB1608CF-GP

14

1

7 GMCH_GREEN

DY
1

BAV99PT-GP-U
3

D18

2

CRT_G 3

DY
1
BAV99PT-GP-U
D17

2

CRT_B 3

DY
1

BAV99PT-GP-U

DDC_CLK & DATA level shift

5V_S0

7
12
8
13
9
14
10
15

CRT_B

3
4

CRT_IN#_R

5

5V_CRT_S0

DAT_DDC1_5
CRT_HSYNC1
CRT_VSYNC1

C315
CLK_DDC1_5
SCD01U16V2KX-3GP

17
VIDEO-15-42-GP-U

3

6
11

2

D2
BAS16PT-GP

F1

1

5V_CRT_DDC

2

FUSE-1D1A6V-4GP-U

RN41
SRN2K2J-1-GP

RN2
SRN10KJ-6-GP

69.50007.691
Q15

1
2
3
4

1

CRT_G

2

5V_CRT_S0

3
4

CRT_R

3D3V_S0

6
1
7
2
8
3
9
4
10
5

8
7
6
5

CRT1

16

2
1

2

2

3D3V_S0

1

CRT I/F & CONNECTOR

4

3

5

2

6

1

CRT_IN#_R
DAT_DDC1_5

20.20378.015
7 GMCH_DDCDATA
CRT_VSYNC1

7 GMCH_DDCCLK

CLK_DDC1_5
DAT_DDC1_5
C317
C19
SC100P50V2JN-3GP

2N7002DW-1-GP

CLK_DDC1_5
1

1

1

C323

CRT_DEC#

2

CRT_IN#_R

2

470R2J-2-GP

1

30

C578
SC220P50V2JN-3GP

Wistron Corporation

D16

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

2
1

R254
1

DY

5V_S0

DY

2

2

2

DY

SC100P50V2JN-3GP

2

1

1

CRT_HSYNC1

SC18P50V2JN-1-GP

SC18P50V2JN-1-GP

1

2

C316

C313
SC100P50V2JN-3GP

3

DY

Title

BAV99PT-GP-U
1

DY

Size

CRT Connector

Document Number

Rev

SB

Cathedral Peak II
Date: Friday, June 20, 2008
A

B

C

D

Sheet
E

15

of

43

5

4

3

2

1

Q31
PWRLED#_DB

C

E
R2
PDTC143ZU-GP-U

Q30
D

30

STDBY_LED#_BD

C

R1

B

STDBY_LED

Power Button

3D3V_S5
LED5

84.00143.E1K

R451
1
2
56R2J-4-GP
R450
1
2
56R2J-4-GP

FRONT_PWRLED#_R 3

1
SW1

STDBY_LED#_R

4

2

1

R8
KBC_PWRBTN#_1

3

R2
PDTC143ZU-GP-U

5

LED-GY-14-GP

83.00195.I70

2

EC5
SC1KP50V2KX-1GP

4

R1

LED6
R449
1
2
56R2J-4-GP
R448
1
2
56R2J-4-GP

CHARGE_LED#

C

R1

3

1

CHARGE_LED#_R

4

2

E
R2
PDTC143ZU-GP-U

PWRLED#_DB

83.00195.I70
STDBY_LED#_BD

R458
1
2
56R2J-4-GP
R465
1
2
56R2J-4-GP

FRONT_PWRLED#_PB

3

1

STDBY_LED#_PB

4

2

R34

LED-GY-14-GP
WLAN_LED#

1
2
33R2J-2-GP

2

1

3D3V_S5
LED3

LED-GY-14-GP

WLAN_LED#_1

GND

IN

83.00195.I70
C

D

Q4
CHDTA143ZUPT-GP

SB

DC_BATFULL#_R

84.00143.E1K

C

BLON_OUT 14,30

2nd: 62.40009.671

Q28

27 WLAN_LED#_MC

KBC_PWRBTN#

4
3

SRN10KJ-5-GP

3D3V_AUX_S5

84.00143.E1K

B

RN74

1
2

62.40009.681

DC_BATFULL#

E
R2
PDTC143ZU-GP-U

30 CHARGE_LED

3D3V_AUX_S5

DY

SW-TACT-122-GP
Q29

B

KBC_PWRBTN# 30

470R2J-2-GP

2

84.00143.E1K

30 DC_BATFULL

KBC_PWRBTN#

2

D

E

C

1

1

R1

B

30 FRONT_PWRLED

R2

84.00143.J11

Q5
2N7002-11-GP

R1

G

3

S

30 WLAN_TEST_LED
OUT
Q18

30

B

BT_LED

BT_LED#

C

R1

E

R2
PDTC143ZU-GP-U

84.00143.E1K

E Power Button
SW2
B

1

R462
E-BUTTON#_CN_1 1

3

4
2

2

E-BUTTON#

E-BUTTON# 30

B

EC13
SC1KP50V2KX-1GP

DY

SW-TACT-122-GP

2

470R2J-2-GP

1

5

62.40009.681

3D3V_S0
C116 SC1U16V3ZY-GP
1
2

DY

2nd: 62.40009.671

LAUNCHCN1
16

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

A

WLAN_LED#
EC11
BT_LED#
EC182
Volume_Up#
EC141
BT_BTN#
EC142
WIRELESS_BTN#
EC143
Volume_Down#
EC144
MEDIA_LED#
EC123
CAP_LED#
EC122
NUM_LED#
EC121
INT_MIC
EC149

EC22 SCD1U16V2ZY-2GP
1
2
EC180 SCD1U16V2ZY-2GP
1
2
5V_S0

DY

EC181
SCD1U16V2ZY-2GP
1
2

DY
WLAN_LED#
BT_LED#
Volume_Up#
BT_BTN#
WIRELESS_BTN#
Volume_Down#
MEDIA_LED#
CAP_LED#
NUM_LED#
INT_MIC

Volume_Up# 30
BT_BTN# 30
WIRELESS_BTN# 30
Volume_Down# 30
MEDIA_LED# 17
CAP_LED# 30
NUM_LED# 30
INT_MIC 28

3D3V_S0
5V_S0
WLAN_LED#
BT_LED#
Volume_Up#
BT_BTN#
WIRELESS_BTN#
Volume_Down#
MEDIA_LED#
CAP_LED#
NUM_LED#
INT_MIC

DY
1

2

DY
1

2

DY
1

2

DY
1

2

DY
1

2

DY
1

2

DY
1

2

DY
1

2

DY
1

2

DY
1

2

SC220P50V2JN-3GP
SC220P50V2JN-3GP
SC220P50V2JN-3GP
SC220P50V2JN-3GP
SC220P50V2JN-3GP

1
1
1
1
1
1
1
1
1
1
1
1

SC220P50V2JN-3GP

AFTE30-GP
AFTE30-GP
AFTE30-GP
AFTE30-GP
AFTE30-GP
AFTE30-GP
AFTE30-GP
AFTE30-GP
AFTE30-GP
AFTE30-GP
AFTE30-GP
AFTE30-GP

SC220P50V2JN-3GP
SC220P50V2JN-3GP
SC220P50V2JN-3GP
A

SC220P50V2JN-3GP

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

EMI
Title

17
Size

POWER /LAUNCH/LED BOARD

Document Number

5

Rev

SB

Cathedral Peak II

ACES-CON15-GP

20.K0228.015

TP58
TP189
TP190
TP191
TP192
TP193
TP194
TP195
TP53
TP54
TP55
TP178

Date: Friday, June 20, 2008

2nd: 20.K0185.015
4

3

2

Sheet
1

16

of

43

5

4

3

C91
1

2

1

RTC_X1

2

D9

MLX-CON3-6-GP-U

2

1

C354
SC1U16V3ZY-GP
TPAD30

20.F0700.003

RTCX1
RTCX2

RTC_RST#
SRTC_RST#
INTRUDER#

A25
F20
C22

RTCRST#
SRTCRST#
INTRUDER#

INTVRMEN
LAN100_SLP

B22
A22

INTVRMEN
LAN100_SLP

TP143

E25

GLAN_CLK

LAN_RSTYNC

C13

LAN_RSTSYNC

F14
G13
D14

2nd: 20.F0735.003
GLAN_COMP place within 500 mil of ICH9M

C

1D5V_S0
GLAN_DOCK#

18 GLAN_DOCK#
ACZ_SYNC

R453
1
2
R452
RN9

1

23 ACZ_BTCLK_MDC
28
ACZ_BITCLK

2

EC161
SC10P50V2JN-4GP

DY

1
2
3
4

23,28 ACZ_SYNC
23,28 ACZ_RST#
23,28 ACZ_SDATAOUT

1R284

2 22R2J-2-GP
1
0R0402-PAD

2 GLAN_COMP
24D9R2F-L-GP
ACZ_BIT_CLK_R

ACZ_SYNC_R
ACZ_RST#_R
ACZ_SDATAOUT_R

8
7
6
5

28 ACZ_SDATAIN0
23 ACZ_SDATAIN1

SRN33J-7-GP
3D3V_S0

ACZ_SDATAOUT_R
TPAD30
16

B

MEDIA_LED#

22
22
22
22

ODD

HDA_DOCK_EN#
2
8K2R2J-3-GP

D13
D12
E13

LAN_TXD0
LAN_TXD1
LAN_TXD2

B10

GLAN_DOCK#/GPIO56

B28
B27

GLAN_COMPI
GLAN_COMPO

AF6
AH4

HDA_BIT_CLK
HDA_SYNC

AE7

HDA_RST#

AF4
AG4
AH3
AE5

HDA_SDIN0
HDA_SDIN1
HDA_SDIN2
HDA_SDIN3

AG5

HDA_SDOUT

AG7
AE8

HDA_DOCK_EN#/GPIO33
HDA_DOCK_RST#/GPIO34

AG8

SATALED#
SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP

SATA_RXN0
SATA_RXP0
SATA_TXN0
SATA_TXP0

C146
C145
C147
C148

1
1
1
1

2
2
2
2

SCD01U50V2KX-1GP
SCD01U50V2KX-1GP
SCD01U50V2KX-1GP
SCD01U50V2KX-1GP

SATA_RXN0_C
SATA_RXP0_C
SATA_TXN0_C
SATA_TXP0_C

AJ16
AH16
AF17
AG17

SATA_RXN1
SATA_RXP1
SATA_TXN1
SATA_TXP1

C149
C150
C144
C143

1
1
1
1

2
2
2
2

SCD01U50V2KX-1GP
SCD01U50V2KX-1GP
SCD01U50V2KX-1GP
SCD01U50V2KX-1GP

SATA_RXN1_C
SATA_RXP1_C
SATA_TXN1_C
SATA_TXP1_C

AH13
AJ13
AG14
AF14

R299

1
2
10KR2J-3-GP

DY

1
R302

HDA_DOCK_RST#

MEDIA_LED#

22
22
22
22

HDD
3D3V_S0

TP148

LAN_RXD0
LAN_RXD1
LAN_RXD2

SATA1RXN
SATA1RXP
SATA1TXN
SATA1TXP

ICH9M-GP-NF

FWH0/LAD0
FWH1/LAD1
FWH2/LAD2
FWH3/LAD3

K5
K4
L6
K2

FWH4/LFRAME#

K3

LDRQ0#
LDRQ1#/GPIO23

J3
J1

A20GATE
A20M#

N7
AJ27

DPRSTP#
DPSLP#

AJ25
AE23

FERR#

AJ26

1

LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3

TP146 TPAD30
TP50 TPAD30
KA20GATE 30
H_A20M# 4

H_DPRSTP#

H_DPRSTP# 4,7,34
H_DPSLP# 4
RN8
H_THERMTRIP_R

AD22

H_PWRGD 4,32,41
4
H_IGNNE# 4

INIT#
INTR
RCIN#

AE22
AG25
L3

H_INIT# 4
H_INTR 4
KBRCIN# 30

NMI
SMI#

AF23
AF24
AH27

PECI

AG27

SATA4RXN
SATA4RXP
SATA4TXN
SATA4TXP

AH11
AJ11
AG12
AF12

SATA5RXN
SATA5RXP
SATA5TXN
SATA5TXP

AH9
AJ9
AE10
AF10

SATA_CLKN
SATA_CLKP

AH18
AJ18

SATARBIAS#
SATARBIAS

AJ7
AH7

1D05V_S0

H_FERR#_R

AF25

AG26

H_DPSLP#

LPC_LFRAME# 30,31
LDRQ0#
3D3V_LDRQ1_S0

IGNNE#

STPCLK#

R297
56R2J-4-GP

DY

CPUPWRGD

THRMTRIP#

30,31

2

C23
C24

RTC_X2

LPC_LAD[0..3]

H_FERR#

1
2
3
4

8
7
6
5

H_FERR#_R
C

SRN56J-5-GP

H_NMI 4
H_SMI# 4

R296
200R2F-L-GP
1 DY
2

H_PWRGD

1D05V_S0

H_STPCLK# 4
H_THERMTRIP_R
ICH_TP8

1

2

PM_THRMTRIP-A# 4,7,32

DY R300

TP96 TPAD30

54D9R2F-L1-GP

Layout note: R373 needs to placed
within 2" of ICH9, R379 must be
placed within 2" of R373 w/o stub

CLK_PCIE_SATA# 3
CLK_PCIE_SATA 3
SATARBIAS

B

2
1
R301
24D9R2F-L-GP
1D05V_S0

Place within 500 mils of
ICH9 ball

3D3V_S0

2
1

2
1MR2J-1-GP

1

1

C73
SC1U16V3ZY-GP

2

4

R282

2

DY C353
SCD1U16V2ZY-2GP

3
4

SC12P50V2JN-3GP

1

1

2
3

2
1

LPC_LAD[0..3]

1 OF 6

U16A

2

RTC
LPC

RN75
SRN20KJ-GP-U

2

RTC_BAT

1D05V_S0
C92
1

LAN / GLAN
CPU

83.R0304.B81

R265
1
2
1KR2J-1-GP

D

IHDA

CH715FPT-GP

5
1

C74
SC1U16V3ZY-GP

SATA

1

2

1

3

R95
10MR2J-L-GP

82.30001.691

2

RTC_BAT_R

RTC1

X2

X-32D768KHZ-38GPU
RTC_AUX_S5

2

D

4

3D3V_AUX_S5

1

3

SC12P50V2JN-3GP

71.ICH9M.00U
RN14
SRN10KJ-5-GP

3
4

RTC_AUX_S5

1

1

RTC_AUX_S5

R90
330KR2F-L-GP

H_INIT#_G
R93
330KR2F-L-GP

2

DY

2

INTVRMEN

High=Enable

B
Q13

Low=Disable

H_INIT#

1

LAN100_SLP

R91
0R2J-2-GP

DY

R92
0R2J-2-GP

E

FWH_INIT#

C

FWH_INIT#

integrated VccLan1_05VccCL1_05

LAN100_SLP

High=Enable

31

MMBT3904-3-GP

Low=Disable

2

1

2

integrated VccSus1_05,VccSus1_5,VccCL1_5
INTVRMEN

A

A

DY

ACZ_BTCLK_MDC 1
EC187
ACZ_BITCLK

Wistron Corporation

2
SC22P50V2JN-4GP

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

DY
1
EC188

2
SC22P50V2JN-4GP

Title

EMI

Size

Document Number

ICH9-M (1 of 4)

Rev

SB

Cathedral Peak II
Date: Friday, June 20, 2008
5

4

3

2

Sheet
1

17

of

43

5

4

3

2

1

3 OF 6

U16C
2 OF 6

2
INT_PIRQD#
PCI_IRDY#
PCI_TRDY#
ECSCI#_1

28
ACZ_SPKR
7 MCH_ICH_SYNC#
TPAD30

INT_SERIRQ
PCI_DEVSEL#
PCI_STOP#
PCI_FRAME#

1

F22
C19

CL_VREF0
CL_VREF1

C25
A19

CL_RST0#
CL_RST1#

F21
D18

GPIO24/MEM_LED
GPIO10/SUS_PWR_ACK
GPIO14/AC_PRESENT
GPIO9/WOL_EN

A16
C18
C11
C20

TXN5
TXP5

G29
G28
H27
H26

PERN4
PERP4
PETN4
PETP4

E29
E28
F27
F26

PERN5
PERP5
PETN5
PETP5

C29
C28
D27
D26

PERN6/GLAN_RXN
PERP6/GLAN_RXP
PETN6/GLAN_TXN
PETP6/GLAN_TXP

D23
D24
F23

N4
N5
N6
P6
M1
N2
M4
M3
N3
N1
P5
P3

USB_RBIAS_PN AG2
AG1

V27
V26
U29
U28

DMI_RXN0
DMI_RXP0
DMI_TXN0
DMI_TXP0

7
7
7
7

DMI1RXN
DMI1RXP
DMI1TXN
DMI1TXP

Y27
Y26
W29
W28

DMI_RXN1
DMI_RXP1
DMI_TXN1
DMI_TXP1

7
7
7
7

DMI2RXN
DMI2RXP
DMI2TXN
DMI2TXP

AB27
AB26
AA29
AA28

DMI_RXN2
DMI_RXP2
DMI_TXN2
DMI_TXP2

7
7
7
7

DMI3RXN
DMI3RXP
DMI3TXN
DMI3TXP

DMI_CLKN
DMI_CLKP

DMI_ZCOMP
DMI_IRCOMP

USBP0N
USBP0P
USBP1N
USBP1P
SPI_CLK
USBP2N
SPI_CS0#
USBP2P
SPI_CS1#/GPIO58/CLGPIO6 USBP3N
USBP3P
SPI_MOSI
USBP4N
SPI_MISO
USBP4P
USBP5N
OC0#/GPIO59
USBP5P
OC1#/GPIO40
USBP6N
OC2#/GPIO41
USBP6P
OC3#/GPIO42
USBP7N
OC4#/GPIO43
USBP7P
OC5#/GPIO29
USBP8N
OC6#/GPIO30
USBP8P
OC7#/GPIO31
USBP9N
OC8#/GPIO44
USBP9P
OC9#/GPIO45
USBP10N
OC10#/GPIO46
USBP10P
OC11#/GPIO47
USBP11N
USBP11P
USBRBIAS
USBRBIAS#

USB

22D6R2F-L1-GP

RSMRST#_SB

CLK_PWRGD 3

AD27
AD26
AC29
AC28

DMI_RXN3
DMI_RXP3
DMI_TXN3
DMI_TXP3

T26
T25

CLK_PCIE_ICH# 3
CLK_PCIE_ICH 3

AF29
AF28

DMI_IRCOMP_R

AC5
AC4
AD3
AD2
AC1
AC2
AA5
AA4
AB2
AB3
AA1
AA2
W5
W4
Y3
Y2
W1
W2
V2
V3
U5
U4
U1
U2

7
7
7
7

USBPN0 23
USBPP0 23

RN64
1
2

4
3

TP31 TPAD30

R281
3K24R2F-GP

CL_CLK0 7
CL_DATA0 7
CL_VREF0_ICH
CL_VREF1_ICH
CL_RST#0

3D3V_S5

7

GPIO24
GPIO10
GPIO14
GPIO9

TP32

TPAD30

DY

USB_OC#2
USB_OC#7
PM_RI#
PCIE_WAKE#

USB_OC#5
SMB_LINK_ALERT#
GPIO10
SMB_ALERT#

3D3V_S5

1D5V_S0

1
2

3D3V_S5

10
9
8
7
6

4
3

1
2
3
4
B

SRN10KJ-6-GP

PCB_VER0
PCB_VER1
2
10KR2J-3-GP

R133

Device

0

USB1

1

NC

USBPN4
USBPP4
USBPN5
USBPP5

2

USB2

3

NC

BOOT BIOS Strap

4

USB3

PCI_GNT#0

5

Bluetooth

6

NC

7

MINIC1

8

WEBCAM

SB_GPIO13
GPIO14

1
2

R144

R145

DY

PlanarID
(1,0)
SA: 0,0
SB: 0,1
SC: 1,0
SD: 1,1

3D3V_S5
R74
1

2
0R2J-2-GP

D7

R73
10KR2J-3-GP
RSMRST#_SB

1
2

DY

R273
100KR2J-1-GP

3

SPI_CS#1

4
3

SRN10KJ-5-GP

30 RSMRST#_KBC

BAT54-7-F-GP

BOOT BIOS Location

USBPN7 27
USBPP7 27
USBPN8 14
USBPP8 14
USBPN9 27
USBPP9 27
USBPN10 24
USBPP10 24

9

0
1
1

PCI_GNT#3

CardReader

11

NC

SPI
PCI
LPC(Default)

A

low = A16 swap override enable
high = default

PCI_GNT#0

NEW1

10

1
0
1

A16 swap override strap

SPI_CS#1
PCI_GNT#3
GNT0 and SPI_CS#1
have a weak internal pull up

1
R286
1
R287
1
R285

1KR2J-1-GP
2

DY

1KR2J-1-GP
2

DY

1KR2J-1-GP
2

DY

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size

Document Number

ICH9-M (2 of 4)

Date: Friday, June 20, 2008
3

Rev

SB

Cathedral Peak II

71.ICH9M.00U
4

8
7
6
5

RN45

R134

DY
R288
1

3D3V_S5
USB_OC#4
DBRESET#
USB_OC#3
USB_OC#6

3D3V_S0

R298
24D9R2F-L-GP

PWROK

USB_OC#8
USB_OC#9
USB_OC#10
USB_OC#11

SRN10KJ-L3-GP

SRN10KJ-5-GP

USB

DY

RN47

1
2
3
4
5

RN49

Pair

3D3V_S5

RP1

3D3V_S0

C

R283
453R2F-1-GP

R274
453R2F-1-GP

SRN10KJ-L3-GP

SRN10KJ-5-GP

SDATAOUT1
SB_GPIO1

C365

R275
3K24R2F-GP

TP139 TPAD30

2
10
9
8
7
6

GLAN_DOCK# 17

USBPN2 23
USBPP2 23

23
23
23
23

1
2
3
4
5

3D3V_S5

GLAN_DOCK#
GPIO57

3D3V_S0

7,32
1

PWROK

DY

USB_OC#1
PM_BATLOW#_R
ECSWI#
USB_OC#0

3D3V_S5

ICH9M-GP-NF

5

PM_PWRBTN# 30,41

D21
3
BAS16PT-GP
2

2

SATA
GPIO

SMB

Clocks

CL_DATA0
CL_DATA1

10KR2J-3-GP

2

1

B16 PM_SLP_M#
F24
B19

10KR2J-3-GP

1
1

USB_OC#0
USB_OC#1
USB_OC#2
USB_OC#3
USB_OC#4
USB_OC#5
USB_OC#6
USB_OC#7
USB_OC#8
USB_OC#9
USB_OC#10
USB_OC#11
R130

R6

CL_CLK0
CL_CLK1

10KR2J-3-GP

USB_OC#4

CLPWROK

PM_DPRSLPVR 7,34

2

PERN3
PERP3
PETN3
PETP3

D25
E23

23

R5

1

J29
J28
K27
K26

SPI_CS#1

A

D22

CK_PWRGD

2

1
1

NEW CARD

USB_OC#0

PWRBTN#_ICH

RP2

10KR2J-3-GP

C372 SCD1U10V2KX-5GP 2
C379 SCD1U10V2KX-5GP 2

23

R3
D20

1

C391 SCD1U10V2KX-5GP 2
C395 SCD1U10V2KX-5GP 2

MINICARD1

PCIE_RXN5
PCIE_RXP5
PCIE_TXN5
PCIE_TXP5

PWRBTN#
LAN_RST#
RSMRST#

2

PERN2
PERP2
PETN2
PETP2

B

27
27
27
27

PM_BATLOW#_R

SLP_M#

2

TXN2
TXP2

L29
L28
M27
M26

DMI0RXN
DMI0RXP
DMI0TXN
DMI0TXP

1

PERN1
PERP1
PETN1
PETP1

LAN

PCIE_RXN2
PCIE_RXP2
PCIE_TXN2
PCIE_TXP2

B13

BATLOW#

7,32
R289 1
DY 2
100KR2J-1-GP

71.ICH9M.00U

2

N29
N28
P27
P26

PCI-Express

1
1

TXN1
TXP1

Direct Media Interface

C399 SCD1U10V2KX-5GP 2
C403 SCD1U10V2KX-5GP 2

SPI

27
27
27
27

PWROK
PM_DPRSLPVR

C360

No Reboot Strap
SPKR
LOW = Defaule
High=No Reboot

4 OF 6

U16D
PCIE_RXN1
PCIE_RXP1
PCIE_TXN1
PCIE_TXP1

SPKR
MCH_SYNC#
TP3
PWM0
PWM1
PWM2

G20
M2

ICH9M-GP-NF

SRN8K2J-2-GP-U

25
25
25
25

TP138

GPIO49 should be pulled down to
GND only when using Teenah. When
using Cantiga, this ball should
be left as No Connect.

SRN8K2J-2-GP-U

3D3V_S0

M7
AJ24
B21
AH20
AJ20
AJ21

ICH_TP3

TACH1/GPIO1
TACH2/GPIO6
TACH3/GPIO7
GPIO8
LAN_PHY_PWR_CTRL/GPIO12
ENERGY_DETECT/GPIO13
TACH0/GPIO17
GPIO18
GPIO20
SCLOCK/GPIO22
GPIO27
GPIO28
SATACLKREQ#/GPIO35
SLOAD/GPIO38
SDATAOUT0/GPIO39
SDATAOUT1/GPIO48
GPIO49
GPIO57/CLGPIO5

1

10
9
8
7
6

3D3V_S0

10
9
8
7
6

SST

PWROK
DPRSLPVR/GPIO16

D

TP141 TPAD30

1

1

3D3V_S0

1
2
3
4
5

A20

AG19
AH21
AG21
30
ECSCI#_1
A21
30
ECSWI#
GPIO12
C12
TPAD30 TP140
SB_GPIO13
C21
PSW_CLR# AE18
GPIO18
K1
TPAD30 TP51
GPIO20
AF8
TPAD30 TP149
CLK_SEL_0
AJ22
A9
SEL
R306
D19
1KR2J-1-GP
L1
PCB_VER0 AE19
PCB_VER1 AG22
SDATAOUT1 AF21
GPIO49
AH24
GPIO57
TPAD30 TP152
A8

2

3D3V_S0

PCI_REQ#3
INT_PIRQF#
INT_PIRQG#
PCI_SERR#

ICH_TP7

WAKE#
SERIRQ
THRM#
VRMPWRGD

SB_GPIO1

S4_STATE#

SCD1U10V2KX-4GP

PM_CLKRUN#

1
2
3
4
5

RP4

INT_PIRQH#
PCI_REQ#0
INT_PIRQC#
INT_PIRQB#

SRN8K2J-2-GP-U
RP3
PCI_REQ#2
PCI_REQ#1

2

GAP-OPEN

2

DY 0R2J-2-GP

C10

2

ICS

R136
1KR2J-1-GP

R305
1KR2J-1-GP

CLKRUN#

D21

CLK_SEL_1

2

G10

1R89

ICS+RTL

STP_PCI#
STP_CPU#

1

R135
1KR2J-1-GP

S4_STATE#/GPIO26

SMBALERT#/GPIO11

PM_SLP_S3# 27,30,32,36,37,38
PM_SLP_S4# 27,30,36,37
TP144 TPAD30

1

RTL+SEL

2

PCLK_ICH 3

R141
10KR2J-3-GP

1

1
PLT_RST1# 7,25,27,30,31

2

1
0R2J-2-GP

SLPS5#

2

7,21,34 VGATE_PWRGD

C16
E16
G17

SRN10KJ-6-GP

PM_SUS_CLK 21

2

3D3V_S0

1

2

E20
M5
AJ23

25,27 PCIE_WAKE#
30 INT_SERIRQ
21
THRM#

SLP_S3#
SLP_S4#
SLP_S5#

PMSYNC#/GPIO0

1

3D3V_S0

10
9
8
7
6

L4

SUSCLK

1

C357
SC100P50V2JN-3GP

DY

INT_PIRQE#
INT_PIRQF#
INT_PIRQG#
INT_PIRQH#

3D3V_S0

A14
E19

PM_STPPCI#
PM_STPCPU#
30 PM_CLKRUN#

R271

H4
K6
F2
G2

3
3

CLK_ICH14 3
CLK48_ICH 3

1

TP142 TPAD30
PCI_DEVSEL#
PCI_PERR#
PCI_LOCK#
PCI_SERR#
PCI_STOP#
PCI_TRDY#
PCI_FRAME#

(0, 1)
(1, 1)
(1, 0)

H1
AF3
P1

4
3
2
1

2

C14 PLT_RST#_R
D4
R2

ICS
Realtek
Seligo

PCI_IRDY#
PCI_PAR

SUS_STAT#/LPCPD#
SYS_RESET#

RN11
5
6
7
8

1

PLTRST#
PCICLK
PME#

M6

PM_SYNC#

CLK14
CLK48

SATA0GP
SATA1GP
GPIO36
GPIO37

2

D3
E3
R1
C6
E4
C2
J4
A4
F5
D7

TP147

RI#

AH23
AF19
AE21
AD20

SCD1U10V2KX-4GP

1
2
3
4
5

R4
G19

SMB_ALERT# A17

71.ICH9M.00U
PCI_PERR#
INT_PIRQE#
PCI_LOCK#
INT_PIRQA#

F19

SATA0GP/GPIO21
SATA1GP/GPIO19
SATA4GP/GPIO36
SATA5GP/GPIO37

1

IRDY#
PAR
PCIRST#
DEVSEL#
PERR#
PLOCK#
SERR#
STOP#
TRDY#
FRAME#

7

(GPIO6,GPIO22)

TP56 TPAD30

RP5

PM_RI#
PM_SUS_STAT#
DBRESET#

SMBCLK
SMBDATA
LINKALERT#/GPIO60/CLGPIO4
SMLINK0
SMLINK1

SYS GPIO
Power MGT

TPAD30

ICH9M-GP-NF
C

G16
A13
SMB_LINK_ALERT# E17
SMLINK0 C17
SMLINK1 B18

SRN10KJ-5-GP

D8
B4
D6
A5

PIRQE#/GPIO2
PIRQF#/GPIO3
PIRQG#/GPIO4
PIRQH#/GPIO5

3
4

PCI_REQ#3
PCI_GNT#3

ICH_PME#

PIRQA#
PIRQB#
PIRQC#
PIRQD#

2
1

3D3V_S5

PCI_REQ#2

C/BE0#
C/BE1#
C/BE2#
C/BE3#

Interrupt I/F

RN4

MISC
GPIO
Controller Link

20,27 SMB_CLK
20,27 SMB_DATA

PCI_REQ#0
PCI_GNT#0
PCI_REQ#1

1

J5
E1
J6
C4

F1
G4
B6
A7
F13
F12
E6
F6

1

INT_PIRQA#
INT_PIRQB#
INT_PIRQC#
INT_PIRQD#

REQ0#
GNT0#
REQ1#/GPIO50
GNT1#/GPIO51
REQ2#/GPIO52
GNT2#/GPIO53
REQ3#/GPIO54
GNT3#/GPIO55

PCI

2

D

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31

2

D11
C8
D9
E12
E9
C9
E10
B7
C7
C5
G11
F8
F11
E7
A3
D2
F10
D5
D10
B3
F7
C3
F3
F4
C1
G7
H7
D1
G5
H6
G1
H3

1

U16B

2

Sheet
1

18

of

43

4

1

1

2

2

VCCUSBPLL
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A

A10
A11

VCCLAN1_05
VCCLAN1_05

A12
B12

VCCLAN3_3
VCCLAN3_3

A27

VCCGLANPLL

D28
D29
E26
E27

VCCGLAN1_5
VCCGLAN1_5
VCCGLAN1_5
VCCGLAN1_5

1
2

DY
2

C368
SC4D7U6D3V3KX-GP

1

A26
3D3V_S0
C383
SCD1U10V2KX-4GP

1mA

1

1
2

1
2

1

1

C401
SC4D7U6D3V3MX-2GP

2

1
2

1

1D05V_S0

2mA

1D05V_S0

1

1

1

2

2

2

2

2

1

1
2

1
2

2

1

1

C392

DY

C393
SC4D7U6D3V3KX-GP

C

1
2

1

1

2

1
2

2

2
C366

DY

C410

VCCCL1_05

G22 VccSus1_05[3]

VCCCL1_5

G23 VccSus1_5[3]

VCCCL3_3
VCCCL3_3

A24
B24

2
C369

C404

1

T1
T2
T3
T4
T5
T6
U6
U7
V6
V7
W6
W7
Y6
Y7
T7

3D3V_S5

C371
SCD1U10V2KX-4GP

2

VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3

3D3V_S5

C432
SCD1U10V2KX-4GP

1D5V_S5

VCCSUS3_3=212mA

TP145 TPAD28

B

3D3V_S5

1

AF1

11mA

C402
SCD1U10V2KX-4GP

2

VCCSUS3_3

C385
SCD1U10V2KX-4GP

1

A18
D16
D17
E22

3D3V_S0

SCD1U10V2KX-4GP
1D5V_S5

2

VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3

11mA
C431
SCD1U10V2KX-4GP

2

1

F18

1

1

AD8

VCCSUS1_5

C387

DY

2

VCCSUS1_5

1

2

C425
SCD1U10V2KX-4GP

C406

2

1
2

C426
SCD1U10V2KX-4GP

2

1

1
2

1
2

1D5V_S0

68.1R220.10D

DY

C376

1

VCCPSUS

D

3D3V_S0

DY

1

AJ5
AA7
AB6
AB7
AC6
AC7

C377

DY
3D3V_S0

C386
SCD1U10V2KX-4GP

2

1
2

1

1
2

VCC1_5_A
VCC1_5_A
VCC1_5_A

2

VCCSUS1_05
VCCSUS1_05

AC8 VccSus1_05
F17

2

1
2

1
2

2

2

2

DY

80mA

VCC1_5_A
VCC1_5_A

AC12
AC13
AC14

VCCPUSB

1

1

1
1
2

2

2

1D5V_S0

C394
SC10U6D3V5MX-3GP

VCC1_5_A

G10
G9

1
2

AJ4
AJ3

C370

SCD1U10V2KX-4GP

1
C362
SCD1U10V2KX-4GP
2

VCC1_5_A
VCC1_5_A

AC21

1

VCCHDA
VCCSUSHDA

DY

C373

SCD1U10V2KX-4GP

23mA

AC18
AC19

C378

SCD1U10V2KX-4GP

1D5V_S0

VccLan1D05
SCD1U10V2KX-4GP

VCC1_5_A

23mA

C411

C415
SC4D7U6D3V3KX-GP

DY

3D3V_S0

SCD1U10V2KX-4GP

DY

C363

AC9

DY

C382

2
IND-1D2UH-10-GP

48mA

1 R294
2
0R0603-PAD

VCC3_3=308mA 3D3V_S0

2

2

CORE
VCCP_CORE

1

1
2

B9
F9
G3
G6
J2
J7
K7

L10

DY

19mA in S0;73mA in S3/S4/S5

A

GLAN POWER

SCD1U10V2KX-4GP

A

DY

VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A

USB CORE

19mA in S0;78mA in S3/S4/S5

SCD1U10V2KX-4GP

3D3V_S0

C416
SCD1U10V2KX-4GP

AC11
AD11
AE11
AF11
AG10
AG11
AH10
AJ10

ATX

C429

VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A

ARX

DY

DY

USBPLL=11mA

C418
SCD1U10V2KX-4GP

C384

C428
SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

1D5V_S0

AC16
AD15
AD16
AE15
AF15
AG15
AH15
AJ15

C388
SC1U16V3ZY-GP

C420

1

VCCSATAPLL

PCI

2
1

C408
SC1U16V3ZY-GP

2

1

C419
SC4D7U6D3V3MX-2GP

C134
SCD1U16V2ZY-2GP

B

C364
SCD1U10V2KX-4GP

AJ19

VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3

2

1.34A

AD19
AF20
AG24
AC20

1

1
2
1
2

1
2

1

1

1
2

2

2

1

1
2
1

2
1
1
2
2
1

1D5V_S0

AC10

VCC3_3
VCC3_3
VCC3_3
VCC3_3

C367

SCD1U10V2KX-4GP

V5REF_S5

R122
100R2J-2-GP

VCC3_3

C430
SCD1U10V2KX-4GP

C414

SCD1U10V2KX-4GP

D13
CH751H-40PT

2mA

AJ6

C413

SCD1U10V2KX-4GP

5V_S5

VCC3_3

C398

C400
SCD01U16V2KX-3GP

SCD1U10V2KX-4GP

3D3V_S5

AG29

C409

1

SCD1U10V2KX-4GP

Layout Note:
Place near ICH9

VCC3_3

C396

SCD1U10V2KX-4GP

C151

AB23
AC23

C407

1D5V_DMIPLL_ICH_S0

W23 1D05V_DMI_ICH_S0
Y23

V_CPU_IO
V_CPU_IO

1D05V_S0

SCD1U10V2KX-4GP

C152
SC10U6D3V5MX-3GP

VCCDMI
VCCDMI

C405

SC10U6D3V5MX-3GP

68.1R220.10D

R29

1.63A
Layout Note:Place near ICH9M

SCD1U10V2KX-4GP

2
IND-1D2UH-10-GP

R276
100R2J-2-GP

C361
SCD1U16V2ZY-2GP

1D5V_APLL_S0

L1

SC1U16V3ZY-GP

V5REF_S0
C

1

VCCDMIPLL

VCCA3GP

D10
CH751H-40PT

2mA

1D5V_S0

VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B

A15
B15
C15
D15
E15
F15
L11
L12
L14
L16
L17
L18
M11
M18
P11
P18
T11
T18
U11
U18
V11
V12
V14
V16
V17
V18

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SC4D7U6D3V3MX-2GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

47mA
5V_S0

V5REF_SUS

AA24
AA25
AB24
AB25
AC24
AC25
AD24
AD25
AE25
AE26
AE27
AE28
AE29
F25
G25
H24
H25
J24
J25
K24
K25
L23
L24
L25
M24
M25
N23
N24
N25
P24
P25
R24
R25
R26
R27
T24
T27
T28
T29
U24
U25
V24
V25
U23
W24
W25
K23
Y24
Y25

VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05

SCD1U10V2KX-4GP

C423

*Within a given well, 5VREF needs to be up before the
corresponding 3.3V rail

3D3V_S0

V5REF

SCD1U10V2KX-4GP

C417

AE1

VCCRTC

SCD1U10V2KX-4GP

C412

DY

1

SCD1U10V2KX-4GP

C390

DY

A6

SCD1U10V2KX-4GP

C422

DY

V5REF_S5

A23

SCD1U10V2KX-4GP

C389

V5REF_S0

2

6 OF 6

SCD1U10V2KX-4GP

646mA

D

C359
SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

1D5V_S0

6uA in G3

2

C358

3

U16F

RTC_AUX_S5

2

5

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

VCCGLAN3_3

Title

ICH9-M (3 of 4)

ICH9M-GP-NF

Size

71.ICH9M.00U

Document Number

Rev

SB

Cathedral Peak II
Date: Friday, June 20, 2008
5

4

3

2

Sheet
1

19

of

43

A

B

2

1

E

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

H5
J23
J26
J27
AC22
K28
K29
L13
L15
L2
L26
L27
L5
L7
M12
M13
M14
M15
M16
M17
M23
M28
M29
N11
N12
N13
N14
N15
N16
N17
N18
N26
N27
P12
P13
P14
P15
P16
P17
P2
P23
P28
P29
P4
P7
R11
R12
R13
R14
R15
R16
R17
R18
R28
T12
T13
T14
T15
T16
T17
T23
B26
U12
U13
U14
U15
U16
U17
AD23
U26
U27
U3
V1
V13
V15
V23
V28
V29
V4
V5
W26
W27
W3
Y1
Y28
Y29
Y4
Y5
AG28
AH6
AF2
B25

NCTF_VSS#A1
NCTF_VSS#A2
NCTF_VSS#B1
NCTF_VSS#A29
NCTF_VSS#A28
NCTF_VSS#B29
NCTF_VSS#AJ1
NCTF_VSS#AJ2
NCTF_VSS#AH1
NCTF_VSS#AJ28
NCTF_VSS#AJ29
NCTF_VSS#AH29

A1
A2
B1
A29
A28
B29
AJ1
AJ2
AH1
AJ28
AJ29
AH29

4

3

3D3V_S5

3D3V_S0

8
7
6
5

3

D

RN43
SRN2K2J-2-GP

1
2
3
4

4

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

NCTF TEST PIN:
A1,A2,B1,A28,A29,B29
AH1,AJ1,AJ2,AH29,AJ28,AJ29

AA26
AA27
AA3
AA6
AB1
AA23
AB28
AB29
AB4
AB5
AC17
AC26
AC27
AC3
AD1
AD10
AD12
AD13
AD14
AD17
AD18
AD21
AD28
AD29
AD4
AD5
AD6
AD7
AD9
AE12
AE13
AE14
AE16
AE17
AE2
AE20
AE24
AE3
AE4
AE6
AE9
AF13
AF16
AF18
AF22
AH26
AF26
AF27
AF5
AF7
AF9
AG13
AG16
AG18
AG20
AG23
AG3
AG6
AG9
AH12
AH14
AH17
AH19
AH2
AH22
AH25
AH28
AH5
AH8
AJ12
AJ14
AJ17
AJ8
B11
B14
B17
B2
B20
B23
B5
B8
C26
C27
E11
E14
E18
E2
E21
E24
E5
E8
F16
F28
F29
G12
G14
G18
G21
G24
G26
G27
G8
H2
H23
H28
H29

C

5 OF 6

U16E

5V_S0

Q6
18,27

SMB_CLK

3

4

2

5

1

6 2N7002DW-1-GP

SMBC_ICH 3,12,13
2

18,27 SMB_DATA
SMBD_ICH 3,12,13

SMBUS

TP33
TP35
TP46
TP43
TP38
TP45
TP98
TP101
TP99
TP102
TP100
TP97

TPAD30
TPAD30
TPAD30
TPAD30
TPAD30
TPAD30
TPAD30
TPAD30
TPAD30
TPAD30
TPAD30
TPAD30

1

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

ICH9-M (4 of 4)
Size

ICH9M-GP-NF

71.ICH9M.00U

Document Number

A

Rev

SB

Cathedral Peak II
Date: Friday, June 20, 2008
B

C

D

Sheet
E

20

of

43

5V_S0

D11
SSM14PT-GP-U

RN7

1
2

5V_S0

4
3

EMC2102_FAN_TACH_1
EMC2102_FAN_TACH

A

5
3
2

83.1R004.E8M

SRN10KJ-5-GP
EMC2102_FAN_DRIVE

1

1

1
C332
SC22U6D3V5MX-2GP

2

C109
SCD1U16V2ZY-2GP

2

C107
SC4D7U10V5ZY-3GP

FAN1
EMC2102_FAN_TACH_1

K

*Layout* 15 mil

K

3D3V_S0

4

D19
SSM14PT-GP-U

MLX-CON3-10-GP-U

20.F1000.003

83.1R004.E8M

2nd: 20.F0714.003
3nd: 20.D0246.103

A
R115

H_THERMDA

22

23
SMCLK

SMDATA

25

24
VDD_5Vb

CLK_32K

EMC2102_DP2

5

DP2

CLK_SEL

17

EMC2102_DN3

6

DN3

RESET#

16

EMC2102_DP3

7

DP3

NC#15

15

GND = Internal Oscillator Selected
+3.3V = External 32.768kHz Clock Selected
EMC2102_PWROK 32

POWER_OK#

THERMTRIP#

THRM# 18

3D3V_S0
RN6
EMC2102_CLK_SEL 5
THRM#
6
7
8

R291
EMC2102_FAN_mode

3D3V_S0

SRN10KJ-6-GP

C397

2

VGATE_PWRGD
PURE_HW_SHUTDOWN#

S

R106
240KR3-GP

2N7002-11-GP

RN65

CLK_32K

5
6
7
8

3D3V_AUX_S5

2

CLK_32K_R

C111

3D3V_S0

1

D

R108
10R2F-L-GP
1
2

4
3
2
1

PURE_HW_SHUTDOWN#
RSMRST#
EMC2102_FAN_mode

R290
10KR2F-2-GP

TRIP_SET Pin Voltage
V_DEGREE
=(((Degree-75)/21)
R110
3KR2F-GP

T8 90 degree

84.27002.N31
2

SRN10KJ-6-GP

3D3V_AUX_S5

2

32K suspend clock output

D12

7,18,34 VGATE_PWRGD

S

Wistron Corporation

RSMRST# 30,32

Q11

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

D

RSMRST#

1

(dummy, KBC already delay)
C113 DY
SCD1U16V2ZY-2GP

Title

2

PURE_HW_SHUTDOWN#

BAT54-7-F-GP

83.R2003.F81
3

DY
1

PM_SUS_CLK

G

18

G

Q10

V_DEGREE

1

RUN_POWER_ON

SCD1U16V2ZY-2GP

GND = Fan is OFF
OPEN = Fan is at 60% full-scale
+3.3V = Fan is at 75% full-scale

SCD1U16V2ZY-2GP

1

10KR2J-3-GP

1

DY

1

4
3
2
1

2

3.HW T8 sensor

TP188

EMC2102_CLK_SEL

EMC2102_SHDN

1

3D3V_S0

2

TP187

AFTE30-GP

74.02102.A73

10KR2J-3-GP

C372 must be near EMC2102

AFTE30-GP

1

1

DY

1

EMC2102_FAN_DRIVE

R107 1
2
0R2J-2-GP DY

R113

2

EMC2102_FAN_TACH_1

14

13

12

NC#8
EMC2102-DZK-GP

SYS_SHDN#

EMC2102

8

GND = Channel 1
OPEN = Channel 3
+3.3V = Disabled

C121
SC470P50V3JN-2GP

26

ALERT#

18

2
1

DY

C83
SC470P50V3JN-2GP

C

84.03904.L06

B

FANb

19

CLK_IN

Layout notice : Both DN3 and DP3 routing
10 mil trace width and 10 mil spacing

E
Q7
MMBT3904-3-GP

FANa

ALERT#

DN2

C125
SC470P50V3JN-2GP

C375 must be near Q8

20

DP1

C373 must be near EMC2102

2.System Sensor, Put between CPU and NB.

21

GND

4

TRIP_SET

C140
SC470P50V3JN-2GP

NC#21

3

FAN_MODE

2

DY

C

84.03904.L06

B

1

E
Q12
MMBT3904-3-GP

DN1

11

Layout notice : Both DN2 and DP2 routing
10 mil trace width and 10 mil spacing

VDD_3V

2

EMC2102_DN2

1.For CPU Sensor

C374 must be near Q7

1

10

2

Layout notice :
Both H_THERMDA and THERMDC routing
10 mil trace width and 10 mil spacing

SHDN_SEL

1

H_THERMDC
C119
SC470P50V3JN-2GP

4

TACH

1

SCD1U16V2KX-3GP

4

28

U15

GND

C118

VDD_5Va

2

29

49D9R2F-GP

27

EMC2102_VDD_3D3

2

9

1

SMBC_Therm 30
SMBD_Therm 30

2

3D3V_S0

2N7002-11-GP

Size

Thermal/Fan Controllor

Document Number

84.27002.N31

Rev

SB

Cathedral Peak II
Date: Friday, June 20, 2008

Sheet

21

of

43

5

4

3

2

SATA ODD Connector

1

SATA Connector

D

D

ODD1

5V_S0

+5V
+5V

DP
MD

P1
P4

ODD_DP
ODD_MD

TP161 TPAD30

1
2

R199
10KR2J-3-GP

DY

TC23

16
17
18
19
20
21
22
NP2
24

C

SATA_RXP0 17
SATA_RXN0 17

C499
SCD1U16V2ZY-2GP

62.10065.541

5V_S0

SC10U10V5ZY-1GP

2

SKT-SATA7P+6P-39-GP
TC10
SC10U10V5ZY-1GP

SCD1U16V2ZY-2GP

C229

2

1

1

P3
P2

2
3
4
5
6
7
8
9
10
11
12
13
14
15

K

A+
A-

D23
SSM24PT-GP

A

S2
S3

23
NP1
1

1

17 SATA_TXP1
17 SATA_TXN1

GND
GND
GND
GND
GND
GND
GND

2

B+
B-

SATA1

9
8
P6
P5
S7
S4
S1

1

S6
S5

2

17 SATA_RXP1
17 SATA_RXN1

SATA_TXN0 17
SATA_TXP0 17

C

SKT-SATA22P-27-GP

62.10065.471

B

B

A

A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size

HDD & CDROM

Document Number

Rev

Cathedral Peak II
Date: Friday, June 20, 2008
5

4

3

2

Sheet
1

22

SB
of

43

5

4

3

2

1

5V_USB1_S0

USB1
USB1

5V_USB1_S0
U34

2

TC15

G545A2P8U-GP

74.00545.A79

2nd: 22.10218.T51
3nd: 22.10218.P01

2nd source 74.09711.079
18

5V_USB1_S0

USB_OC#0

1

USB2
USB2

D

EC124
SCD1U16V2ZY-2GP

2

2
3
4

5V_USB2_S0

6

5V_S5
U57

5V_USB2_S0

SKT-USB-198-GP

1

2

RT9711BPF-GP

C

5V_USB2_S0

DY
2

74.09711.079

USB3

USB_OC#4 18

30 USB_PWR_EN#

EC14
SCD1U16V2ZY-2GP

USB3

5

R464
0R0402-PAD
2
1
2
1

DY

EC183

1

TC28

DY
2

1
USB_OC#4

1

60mil

8
7
6
5

2

VOUT
VOUT
VOUT
FLG#

EC184
SC1000P50V3JN-GP

USB_PWR_EN#

GND
VIN
VIN
EN/EN#

SCD1U16V2ZY-2GP

C45
SC4D7U10V3KX-GP

2nd: 22.10218.T51
3nd: 22.10218.P01

1
2
3
4

ST100U6D3VBM-5GP

1

22.10218.W51

USBPN4
USBPP4

EC115

DY

1
USB_2USB_2+

R293
0R0402-PAD

18
18

EC114

DY

DY

5

R292
0R0402-PAD
2
1
2
1

USBPN2
USBPP2

TC14

2

18
18

DY

1

1

2

GND

1

OC#
EN/EN#

2

5
4

100 mil
SC1000P50V3JN-GP

USB_PWR_EN#

8
7
6

SCD1U16V2ZY-2GP

22.10218.W51

OUT#8
OUT#7
OUT#6

ST150U6D3VDM-18GP

SKT-USB-198-GP

IN#3
IN#2

ST150U6D3VBM-2-GP

C424
SC4D7U10V3KX-GP

D

3
2

1

6

2

2
3
4

R279
0R0402-PAD

1

USB_0USB_0+

5V_S5

2

USBPN0
USBPP0

1

1

18
18

5V_USB1_S0

5

R278
0R0402-PAD
2
1
2
1

C

1
USB_4USB_4+

R463
0R0402-PAD

2nd source 74.00545.A79

2
3
4
6
SKT-USB-198-GP

22.10218.W51

BLUETOOTH MODULE

MDC 1.5 CONN

1.5A / High Active Voltage 2V

B

1

2

B

MDC1

BLUETOOTH_EN 30

17,28
ACZ_SYNC
17 ACZ_SDATAIN1

R398
0R0402-PAD

C542
SC22P50V2JN-4GP

BLUE1

20.F0917.012
C531
SC100P50V2JN-3GP

DY

2nd: 20.F0604.012

6

A

4
3
2

USB_5USB_5+

1

3D3V_BT_S0

USBPN5
USBPP5

3D3V_S5
3D3V_S5

ACZ_BTCLK_MDC 17

TYCO-CONN12A-2-GP-U1

2

2

DY

4
6
8
10
12
17
18

18
18

C296

1
R222
100KR2J-1-GP

EC21 put near
BLUE1 / all
USB put one
choke near
connector by
EMI request

2

17,28 ACZ_RST#

R232
0R0402-PAD
2
1

3
5
ACZ_SYNC_A
7
ACZ_SDATAIN1_A
9
11
1ACZ_RST#_MDC
NP2
16

SC4D7U10V5ZY-3GP

2nd:74.05240.A7F
(G5240B1T1U-GP)

1

2

RT9711-APBG-GP

74.09711.A7F

1
2
3
4

1

4

15
14
2

C295
DUMMY-C2

2

1

5

1

EC80 DY
SCD1U16V2ZY-2GP

VOUT
VIN
GND
NC#3 EN/EN#

13
NP1
1

RN76
SRN39J-GP
8
7
6
5

2

1
2
3

ACZ_SDATAOUT

1

3D3V_BT_S0

17,28 ACZ_SDATAOUT

C573
SC4D7U10V5ZY-3GP
2
DY

2

3D3V_S0

U26

1

3D3V_BT_S0

1

C297
SC4D7U10V5ZY-3GP

13
14
15

2

11

12

16
17
18

A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

5
USB_51
USB_5+ 1
3D3V_BT_S0 1

ETY-CON4-21-GP-U

20.F0984.004

2nd: 20.D0197.104
3nd: 20.F0689.004

2

1

R233
0R0402-PAD

AFTE30-GP
AFTE30-GP
AFTE30-GP

TP134
TP136
TP133

Title

USB/BLUETOOTH/MDC
Size

Document Number

Rev

Cathedral Peak II
Date: Friday, June 20, 2008

5

4

3

2

Sheet
1

23

SB
of

43

5

3D3V_S0

4

3D3V_D_S0

3

2

1

3D3V_A_S0

R428
0R0603-PAD
1
2

XD_CD#
SD_WP
SD_CD#
XD_D4
XD_D5/MS_BS
SD_DAT1/XD_D3/MS_D1_1
SD_DAT0/XD_D6/MS_D0
SD_DAT7/XD_D2/MS_D2
MS_INS#
SD_DAT6/XD_D7/MS_D3
SD_CLK/XD_D1/MS_CLK
SD_DAT5/XD_D0
SD_DAT4/XD_WP#
XD_R/B#
SD_DAT3/XD_WE#
SD_DAT2/XD_RE#
XD_ALE
XD_CE#
XD_CLE

SD_DAT1/XD_D3/MS_D1_1
R418
0R0603-PAD
1
2

D

2

CARD_3D3V_S0
C539
SC1U10V3KX-3GP

R400
0R2J-2-GP
1 SD_DAT1/XD_D3/MS_D1
DY

XD_D4

2

1

R410
0R0402-PAD
D

1

DY

2

3D3V_D_S0

2

6K19R2F-GP

RREF

D3V3
D3V3

45
36
14
2
44

MODE_SEL
SD_CMD
GPIO0
RREF
RST#
DP
DM
5
4

DY VCC

8
7
6
5

1

DU
ORG
GND

C565
SCD1U16V2ZY-2GP

DY

1
C527
SCD1U16V2ZY-2GP

6
12
32
46

C

-4

DY C516

RTS5158E-GR-GP

71.05158.A0G

SC5D6P50V2CN-1GP
1

12M_XI

R416
0R0402-PAD
2
1

2

3D3V_D_S0

3

2

DY

DY
1

DY

2

2
R396
2
R395

R388
270KR2F-GP

2

1

2

EEDO
EEDI

USBPN10

EESK
EECS

USBPP10

18

1 USB_10+
0R0402-PAD
1USB_100R0402-PAD

12M_XI
12M_XO

18

2

DY

S
C
D
Q

M93C46-WMN6TP-GP

1
1
2

DY

R387
10KR2J-3-GP

XDAL_CTR

1

C511
SC47P50V2JN-3GP

2

GND
GND
GND
GND

1
2
3
4

3D3V_A_S0

DY

RST#

MODE_SEL
R386
100KR2J-1-GP

C510
SC1U10V3KX-3GP

30
7
3

2

1

LED-W-23-GP

3D3V_D_S0

EECS
EESK
EEDO
EEDI

EEDO
EEDI

MODE_SEL
SD_CMD

K VBUS_LED
R394
1

33
11

15
18

68R2-GP

C

LED7
ADY

VBUS_R

NC#30
NC#7
NC#3

3V3_IN

EESK
EECS

2

VREG

17
16

DY

24
22

AV_PLL

XTLI
XTLO

DY

C529
SCD1U16V2ZY-2GP

2

2
C548
SCD1U16V2ZY-2GP

1

8

3D3V_D_S0

C534
SCD1U16V2ZY-2GP

1

2
1

2

1

3V_VBUS_S0

R429

1

10

U52

MS_D5
MS_D4

XTAL_CTR

VREG

3D3V_S0

RST#

1

CARD_3V3

47
48

AV_PLL

R423
0R0603-PAD
1
2
C554
SC4D7U6D3V5KX-3GP

9

13

2

VREG

C524
SCD1U16V2ZY-2GP

1

1

R409
0R0603-PAD
1
2

2

2

C544
SC1U10V3KX-3GP

3D3V_S0

SP1
SP2
SP3
SP4
SP5
SP6
SP7
SP8
SP9
SP10
SP11
SP12
SP13
SP14
SP15
SP16
SP17
SP18
SP19

19
20
21
23
25
26
27
28
29
31
34
35
37
38
39
40
41
42
43

U43

X4
XTAL-12MHZ-11GP

82.30006.191

1

12M_XO

C515
SC5D6P50V2CN-1GP

R393
0R0402-PAD
2
1

CLK48_5158E

12M_XO

B

B

5 IN1 CARD-READER (SD/MMC/MS/MS PRO/XD)
CARD1

1
2

2

C519
SC4D7U10V5ZY-3GP

1

CARD_3D3V_S0

33
23
14

XD_VCC
SD_VCC
MS_VCC

XD_R/B#
SD_DAT2/XD_RE#
XD_CE#
XD_CLE
XD_ALE
SD_DAT3/XD_WE#
SD_DAT4/XD_WP#
XD_CD#

1
2
3
4
5
6
7
34

XD_R/B
XD_RE
XD_CE
XD_CLE
XD_ALE
XD_WE
XD_WP
XD_CD_SW

SD_DAT5/XD_D0
SD_CLK/XD_D1/MS_CLK
SD_DAT7/XD_D2/MS_D2
SD_DAT1/XD_D3/MS_D1_1
XD_D4
XD_D5/MS_BS
SD_DAT0/XD_D6/MS_D0
SD_DAT6/XD_D7/MS_D3

8
9
26
27
28
30
31
32

XD_D0
XD_D1
XD_D2
XD_D3
XD_D4
XD_D5
XD_D6
XD_D7

CARD_3D3V_S0

C505
SCD1U16V2ZY-2GP

DY

Pin27 change to
SD_DAT1/XD_D3/MS_D1_1
for XD fail
A

NP1
NP2

NP1
NP2

SD_DAT0
SD_DAT1
SD_DAT2
SD_DAT3

25
29
10
11

SD_DAT0/XD_D6/MS_D0
SD_DAT1/XD_D3/MS_D1
SD_DAT2/XD_RE#
SD_DAT3/XD_WE#

SD_WP_SW
SD_CD_SW
SD_CMD
SD_CLK

35
36
12
24

SD_WP
SD_CD#
SD_CMD
SD_CLK/XD_D1/MS_CLK

MS_DATA0
MS_DATA1
MS_DATA2
MS_DATA3

19
20
18
16

SD_DAT0/XD_D6/MS_D0
SD_DAT1/XD_D3/MS_D1_1
SD_DAT7/XD_D2/MS_D2
SD_DAT6/XD_D7/MS_D3

MS_SCLK
MS_INS
MS_BS

15
17
21

SD_CLK/XD_D1/MS_CLK
MS_INS#
XD_D5/MS_BS

GROUND
GROUND
4IN1_GND
4IN1_GND

37
38
13
22

A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

CARDBUS38P-GP-U

20.I0079.001

CARDREADER- RTS5158E
Size

2nd: 20.I0081.001
3rd: 20.I0067.001

Document Number

Date: Friday, June 20, 2008
5

4

Rev

Cathedral Peak II
3

2

Sheet

24
1

SB
of

43

5

4

3

2

1

3D3V_LAN_S5

8Kbit

R66
1 0R0603-PAD
2

3D3V_S0

3D3V_LAN_S5

LANPWR

2 R49
1
4K7R2J-2-GP

VPD_DATA
VPD_CLK

1D8V_LAN_S5

RN3
SRN4K7J-10-GP

U13

1
2
3
4

1D8V_LAN_S5

A0
A1
A2
GND

VCC
WP
SCL
SDA

8
7
6
5

8
7
6
5

2
0R2J-2-GP

1
2
3
4

3D3V_LAN_S5

DY
R61

LAN_CLKREQ#

1

3D3V_LAN_S5

VPD_CLK
VPD_DATA
LANLOM

D

D

AT24C08BN-SH-T-GP

NC#52

18 PCIE_TXN1

53

18 PCIE_TXP1

54

3 CLK_PCIE_LAN
3 CLK_PCIE_LAN#

33

35

34

37

36

38

40

39

41

43

42

44

23

59

LED_ACT#

AVDD

22

60

LED_LINK10/100#

MDIN1

21

MDI1-

26

61

VDDO_TTL

MDIP1

20

MDI1+

26

62

LED_LINK1000#

63

LED_DUPLEX#

64

SMCLK

65

GND

AVDD

19

MDIN0

18

MDI0-

26

MDIP0

17

MDI0+

26

C

RSET
16

15

14

13

12

11

9

10

8

7

1

XTALI

24

AVDD

XTALO

RESERVED#24

VDD

VDD

SMALERT#

58

VAUX_AVLBL

57

SWITCH_VCC

25

LOM_DISABLE#

RESERVED#25

SWITCH_VAUX

REFCLKN

AVDDH/3_3V

26

56

VDD

MDI2+

WAKE#

26

88E8071-B0-GP

71.88071.A03

2

1D2V_LAN_S5

C356
SC4D7U6D3V3KX-GP
SCD1U10V2KX-4GP
7,18,27,30,31 PLT_RST1#

B

4
2

CTRL12
CTRL18
PLT_RST1#_LAN

R55

1
100R2J-2-GP
C44
SC100P50V2JN-3GP

R36
1
2
4K99R2F-L-GP

LANLOM

C
C

2

1D2V_LAN_S5

2

LANRSET

1

2

2

E

1

Q8
DCP69A-13-GP

B

DY

3

C72

1

1

R79
4K7R2J-2-GP
CTRL12

46

26

MDIP2

Main source:72.24C08.J01
2nd source:72.24C08.I01

3D3V_LAN_S5_2

1

3D3V_LAN_S5

45

MDI2-

REFCLKP

PLACE PNP TO CHIP ACAP
CTRL12 PIN TRACE IS 25MIL
R270
1
2
0R0603-PAD

47

27

55

PERST#/TSTPT

SC1KP50V2KX-1GP

28

6

DY

26

AVDD

5

C59

MDI3+

MDIN2

CTRL18

LAN_LED_10/100/1G
2
0R2J-2-GP

26

RX_P

4

DY
R70

MDI3-

RX_N

CTRL12

1

26 10M/100M/1G_LED#

31

29

3

26 LAN_ACT_LED#
C

MDIN3

30

VDD

SMB_ALERT#_LAN

32

MDIP3

VDDO_TTL

10KR2J-3-GP
R71
DY
1
2

NC#32

RESERVED#29

2

3D3V_S5

Pull up for AT24C08 another pull low

VDD

NC#51

52

SPI_DI

51

SPI_DO

TX_N

SPI_CS

50

SPI_CLK

PCIE_RXN1_LAN

VPD_CLK

1

VDD

SCD1U10V2KX-5GP 2

VDDO_TTL

C56

VPD_DATA

18 PCIE_RXN1

CLKREQ#

TX_P

VDD

49

SMDATA

PCIE_RXP1_LAN

VDDO_TTL

1

TESTMODE

SCD1U10V2KX-5GP 2

VDD

C55

VMAIN_AVLBL

U8
18 PCIE_RXP1

48

72.24C08.J01

B

1

DY

C75
SC10U6D3V5KX-1GP

18,27 PCIE_WAKE#

R41
1
2
10MR2J-L-GP

LANX1
LANX2

1

1
2

1

1
Q9
DCP69A-13-GP

3D3V_LAN_S5

3

C30
SC12P50V2JN-3GP

C23
SC15P50V2JN-2-GP

1D8V_LAN_S5

1D2V_LAN_S5

DY
4
2

84.00069.A1B
1

1
2

1D8V_LAN_S5

2

CTRL18

C77
SC10U6D3V5KX-1GP

A

SB

R80
4K7R2J-2-GP

2

2

DY

1

1
2

1
2

SC4D7U6D3V3KX-GP

DY

C67

B

C64
SCD1U10V2KX-4GP

2

SC10U6D3V5KX-2GP

SC10U6D3V5KX-2GP

2

C76

C
C

C53
SCD1U10V2KX-4GP

DY

3D3V_LAN_S5
R68
1
2
0R0603-PAD
1
1
C60

2 LANX1

XTAL-25MHZ-67GP

PLACE PNP TO CHIP ACAP
CTRL25 PIN TRACE IS 25MIL

E

3D3V_S5

82.30020.571

X1
LANX2 1

2

2

2

C68
SCD1U10V2KX-4GP

1

84.00069.A1B

C69
SCD1U10V2KX-4GP

1
C345
1
C338
1
C337
1
C340
1
C335

2
SC1KP50V2KX-1GP
2
DY SC1KP50V2KX-1GP
2
SC1U6D3V2KX-GP
2
SC1U6D3V2KX-GP
2
SC1U6D3V2KX-GP

1
2
C330
SCD1U10V2KX-4GP
1
2
C327
SCD1U10V2KX-4GP
1
2
C328
SC1KP50V2KX-1GP
1
2
C57 DY
SC1KP50V2KX-1GP
1
2
C329
SC1U6D3V2KX-GP
1
2
C347
SC1U6D3V2KX-GP

1
C343
1
C333
1
C25
1
C339DY
1
C35
1
C346
1
C344
1
C334

2
SC1U6D3V2KX-GP
2
SC1U6D3V2KX-GP
2
SC1KP50V2KX-1GP
2
SC1KP50V2KX-1GP
2
SC1U6D3V2KX-GP
2
SC1KP50V2KX-1GP
2
SC1U6D3V2KX-GP
2
SC1KP50V2KX-1GP

A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

88E8071
Size
A3

Document Number

Date: Friday, June 20, 2008
5

4

3

2

Rev

SB

Cathedral Peak II
Sheet
1

25

of

43

A

B

C

D

E

LAN Connector

4

1.route on bottom as differential pairs.
2.Tx+/Tx- are pairs. Rx+/Rx- are pairs.
3.No vias, No 90 degree bends.
4.pairs must be equal lengths.
5.6mil trace width,12mil separation.
6.36mil between pairs and any other trace.
7.Must not cross ground moat,except
RJ-45 moat.

LAN_ACT_LED#
10M/100M/1G_LED#

4

DY

SB

DY

C311
C310
SC1KP50V2KX-1GP SC1KP50V2KX-1GP

XF1
25

MDI0+

2

23

RJ45_1

25

MDI0-

3
1

22
24

RJ45_2
MCT1

25

MDI1+

4
5

21
20

MCT2
RJ45_3

1D8V_LAN_S5

1

DY

LAN Connector
RJ1
25 10M/100M/1G_LED#

C10
SCD1U10V2KX-4GP

2

C9
SCD1U10V2KX-4GP

2

1

R31
1
2 V_DAC
0R0603-PAD

14
9
10
11
1

CONN_PWR
RJ45_1

25

MDI1-

6

19

RJ45_6

25

MDI2+

8

17

RJ45_4

RJ45_2
RJ45_3
RJ45_4
RJ45_5
RJ45_6
RJ45_7
RJ45_8
CONN_PWR2

3

25 LAN_ACT_LED#
25

1

MDI3+

9
7

16
18

RJ45_5
MCT3

10
11

15
14

MCT4
RJ45_7

3

RJ45-92-GP

22.10245.E91

DY

C12
SCD1U10V2KX-4GP

2

C11
SCD1U10V2KX-4GP

2

1

25

MDI2-

9:GREEN
13:Orange

2
3
4
5
6
7
8
12
13
15

LAN Link: Green(9), behavior is the
same for 10/100/1000 bits
25

12

MDI3-

13

RJ45_8

LAN Data: Yellow(13), when LAN is
transfering data.

XFORM-275-GP

68.89240.30A

DOC_TIP,DOC_RING,TIP,RING:
W/S : 10/100 @ Surface layers
10/20 @ Inner layers
2

2

CONN_PWR2
470R2J-2-GP
CONN_PWR
470R2J-2-GP

EC87

DY

8
7
6
5

MCT1
MCT2
MCT3
MCT4

DY

1
2
3
4

RN40
SRN75J-1-GP

SC100P50V2JN-3GP

SC100P50V2JN-3GP

1

EC90

1

2

2

1
R243
1
R252

3D3V_LAN_S5

2

2

MCT_R

1

1

2

1

C312
SC1KP2KV8KX-GP

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

LAN CONN
Size
A3

Document Number

Date: Friday, June 20, 2008
A

B

C

D

Rev

SB

Cathedral Peak II
Sheet
E

26

of

43

A

B

NEWCARD Connector

C

NEW2

D

E

Mini Card Connector(WLAN)

1

2

CARDBUS-SKT107-GP

21.H0168.001
1D5V_S0

2nd: 21.H0182.001

3D3V_MINI

4

4

NEW1

TP12

MINI_WAKE#

3 CLK_PCIE_MINI1#
3 CLK_PCIE_MINI1

17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
NP2
54

E51_RxD
E51_TxD

18 PCIE_RXN2
18 PCIE_RXP2
18 PCIE_TXN2
18 PCIE_TXP2
3D3V_MINI

5V_S5

3D3V_S5

R454 0R2J-2-GP
1
2

3D3V_S5

R455 0R2J-2-GP
1
DY 2

NC#16
NC#14
NC#13
NC#5
NC#4
16
14
13
5
4

1

C96

DY

C27

2

1

C87

1

1

1

C97

2

2

2

1

DY

2

C576
SCD1U16V2ZY-2GP

C283

3D3V_NEW_LAN_S5

1

1

1

1

C282
SC1U10V3ZY-6GP

2

2

2

1

1

C493

SCD1U16V2ZY-2GP

C496
SC1U10V3ZY-6GP

1D5V_NEW_S0

C513
SCD1U16V2ZY-2GP

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

NEW CARD/MINI CARD
Size

Document Number

B

Rev

Cathedral Peak II
Date: Friday, June 20, 2008

A

3D3V_MINI

Place them Near to Connector

2

1

3D3V_S0

3D3V_S5

SCD1U16V2ZY-2GP

TPS2231RGP-GP-U

74.02231.073

SCD1U16V2ZY-2GP

2

TC8

ST330U6D3VDM-17GP

1D5V_S0

SC1U6D3V2KX-GP

3D3V_S0
3D3V_NEW_S0
1D5V_S0
1D5V_NEW_S0
3D3V_S5
3D3V_NEW_LAN_S5

SCD1U16V2ZY-2GP

2
3
12
11
17
15

3

WLAN_LED#_MC 16
TPAD28 TP42

Place near MINIC1
3D3V_S0

3D3V_NEW_S0

C509
SCD1U16V2ZY-2GP

1

3D3V_S0
3D3V_NEW_S0

3D3V_S0

1

LED_WPAN#

TPAD28 TP36

2

C502
SC100P50V2JN-3GP

3.3VIN
3.3VOUT
1.5VIN
1.5VOUT
AUXIN
AUXOUT

SMB_CLK 18,20
SMB_DATA 18,20

SRN33J-5-GP-U
USBPN7 18
USBPP7 18

1

2

20
8
9
10
6

1

GND

1D5V_S0
1D5V_NEW_S0

Place them Near to Chip

4
3

LED_WWAN#

PLT_RST1# 7,18,25,30,31

SC1U6D3V2KX-GP

7

STBY#
RCLKEN
OC#
THERMAL_PAD

R369
1
100R2J-2-GP

2

2

RN5

SRN100KJ-6-GP

2

WIRELESS_EN 30
PLT_RST1# 7,18,25,30,31

2

R85
300R2F-GP

62.10043.461

DY

PLT_RST1#_NEWCARD

1
18
19
21

1

DY

3
4

SHDN#
PERST#
CPUSB#
CPPE#
SYSRST#
PM_SLP_S3#

PLT_RST1#_WLAN

SMB_CLK_WLAN 1
SMB_DATA_WLAN2

DY 2
10KR2J-3-GP

SKT-MINI52P-13-GP

RN54

18,30,32,36,37,38

18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

R78

1

C80
SC100P50V2JN-3GP

1

30
30

CPUTSB# 2
CPPE#
1

U38

4
6
8
10
12
14
16

DY

20.F1336.026

18,30,36,37 PM_SLP_S4#

2

3
5
7
9
11
13
15

FCI-CON26-7-GP

TPS2231_PERST#

53
NP1
1

2

TPAD30

2

3

3D3V_MINI
MINIC1

NP2
26
25
18 PCIE_TXP5
24
18 PCIE_TXN5
23
22
18 PCIE_RXP5
21
18 PCIE_RXN5
20
19
3 CLK_PCIE_NEW
3D3V_NEW_S0
18
3 CLK_PCIE_NEW#
CPPE#
17
TP127
NEW_PIN16
16
15
14
3D3V_NEW_LAN_S5
TPS2231_PERST#
13
12
PCIE_WAKE#_NEW
1DY
2
11
18,25 PCIE_WAKE#
R219 0R2J-2-GP
10
1D5V_NEW_S0
RN34
9
SMB_DATA_NEW 8
1
4
DY
18,20 SMB_DATA
SMB_CLK_NEW
2
3
7
18,20 SMB_CLK
SRN33J-5-GP-U
CONN_TP1 6
TP123
CONN_TP2 5
TP122
CPUTSB#
4
3
18 USBPP9
2
18 USBPN9
1
NP1

C

D

Sheet
E

27

SB
of

43

5

4

3

2

1

5V_S0

4.75V / 300mA
U21

1
2
3

EN
GND
VIN

NC#5

5

VOUT

4

5VA_S0
D

1

D

1

RT9198-4GPBG-GP

"VAUX" Pull high to enable standby mode
AMP_BEEP_1
2
SCD47U16V3ZY-3GP

2

SPKR_SB_1

RESET#
BCLK

R340

SC4D7U10V3KX-GP
SC4D7U10V3KX-GP
SC1U16V3ZY-GP
SC1U16V3ZY-GP

2
2
1
1

2 SEL_MIC
1KR2F-3-GP
1
1
2
2

C232
C238
C226
C228

MIC1-L_PORT-B
MIC1-R_PORT-B
IMT_MIC1-L
IMT_MIC1-R

29
31

LINE1-VREFO
GPIO1

21
22
16
17

MIC1-L_PORT-B
MIC1-R_PORT-B
MIC2-L_PORT-F
MIC2-R_PORT-F

32
28
30

MIC1-VREFO-R
MIC1-VREFO-L
MIC2-VREFO

34
13

5
8

AC97_DATIN
1
R163

2
39R2J-L-GP

ACZ_SDATAOUT 17,23
ACZ_SDATAIN0 17

SPDIFO
EAPD
NC#45
DMIC-CLK

45
46

HP-OUT-L_PORT-A
HP-OUT-R_PORT-A

39
41

FRONTL 29
FRONTR 29

LINE-OUT-L_PORT-D
LINE-OUT-R_PORT-D

35
36

SOUNDL 29
SOUNDR 29

AMP_SHUTDOWN# 29,30

ALC_EAPD

D14
BAW56-7-F-GP

DY

R187
0R0402-PAD

2ND = 83.00056.G11
R170

1

2 3D3V_S0

DY

10KR2J-3-GP

B

CD-L
CD-R
CD-G

DMIC-12/GPIO0
DMIC-34/GPIO3

ALC268-GR-GP

18
20
19

2
3

VREF

JDREF
MONO-OUT
40
37

71.00268.00G
2

JDREF

1
1
C269
SCD47U16V3ZY-3GP

R165
10KR2F-2-GP

MONO-OUT
TP116
TPAD30

DY

R198
20KR2F-L-GP

2

2

1
2

C268
SC10U10V5ZY-1GP

MIC_JD# 29

Sense resistors need close codec

Change to 71.00268.A0G

VREF

DY

R175
1
2
20KR2F-L-GP

29 ALC268_EAPD

27

AVSS1
AVSS2
DVSS
DVSS
26
42
4
7

2

C577
SC4D7U10V5ZY-3GP

1

2

C264
SC4D7U10V5ZY-3GP

1

C265
SC4D7U10V5ZY-3GP

1

SRN2K2J-2-GP

2

B

MIC1V_R
MIC1V_L
MIC2-VREFO

8
7
6
5

C

48
47

ALC268

LINEOUT_JD# 29

ALC268_SENSE

SC22P50V2JN-4GP

SDATA-OUT
SDATA-IN

RN46

1
2
3
4

R178
1
2
39K2R2F-L-GP

C211
1
2DY

SENSE_B
SENSE_A

44
43
NC#44
NC#43

12
11
10
6
33

LINE1-L_PORT-C
LINE1-R_PORT-C
NC#14
NC#15

ACZ_RST# 17,23

ACZ_SYNC 17,23
ACZ_BITCLK 17

2 R164
1
0R0402-PAD
1
2
C212
DY
SC22P50V2JN-4GP

1

23
24
14
15

PCBEEP
RESET#
SYNC
BCLK
NC#33

1
9
25
38
DVDD
DVDD-IO
AVDD1
AVDD2

U20

29 AUD_MICIN_L
29 AUD_MICIN_R
16
INT_MIC

2

1

C204
SC100P50V2JN-3GP

C

1

1

1
1
2

2

1
2

C210 SC100P50V2JN-3GP
2
R162
2
1
100R2J-2-GP

1

R159
10KR2J-3-GP

SCD47U16V3ZY-3GP

C240
SCD1U10V2KX-4GP

1

C194
1

SRN47KJ-1-GP

2
SCD47U16V3ZY-3GP

C206
DY
SC10U10V5ZY-1GP

2

ACZ_SPKR

2AUDIP_PC_BEEP

SC1U10V3KX-3GP

3

18

C188
1

C208
1

AUDIO_BEEP

C247
SC10U10V5ZY-1GP

2

KBC_BEEP

5
6
7
8

C213
SCD1U10V2KX-4GP

1

30

4
3
KBC_BEEP_1 2
1

2

DY

RN21

1

C182
1

2

AMP_BEEP

C267
SC10U10V5ZY-1GP

5VA_S0

3D3V_S0
29

2

74.09198.A7F
74.09091.F3F
G9091-475T12U-GP

2

C272
SC1U10V3KX-3GP

A

A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
A3

Azalia codec ALC268
Document Number

Date: Friday, June 20, 2008
5

4

3

2

Rev

SB

Cathedral Peak II
Sheet
1

28

of

43

A

B

1

5V_S0

R127
12KR2F-L-GP
INL_A

1

SET

6DB

4

R143

2

C139
SC1U10V3KX-3GP

1

AMP_SHUTDOWN# 28,30

SPK_EN#
SET
BIAS
HP_EN

1
2
R142
0R0402-PAD

DY

ALC268_EAPD 28
5V_S0

SPKR_R+
SPKR_R-

R147
10KR2J-3-GP
5V_S0
3D3V_S0

SPKR_L+1
SPKR_R+1

SPK_EN#

APA2057ARI-TRL-GP

C153
SC1U10V3KX-3GP

G

2

74.02057.01G

DY

1

DY

2

1

1

2

EC145

DY

2nd: 20.F0984.002

DY

2

5V_S0

22.10133.B01

SPKR_L_A1
SPKR_R_A1

2

U55
SD05C-1-GP

1
B

-1
LINEOUT_JD#

C

SPKR_L+1

DY

1

1

C473
R329
SC680P50V2KX-2GP
DY

1

Wistron Corporation
R335
1KR2J-1-GP

DY

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

2

DY

4
3
SRN51J-GP

2

1
2

C466

1

2
1

DY

22.10133.B21

1
2

SPKR_L_A1
EC152

SPKR_R+1

RN68

2

PHONE-JK235-GP-U2

LINEOUT_JD# 28

SPKR_R_A1

1KR2J-1-GP

TP117
TP114
TP113
TP109
TP160
TP159

NP2
NP1
5
4
3
6
2
1

SC680P50V2KX-2GP

AFTE30-GP
AFTE30-GP
AFTE30-GP
AFTE30-GP
AFTE30-GP
AFTE30-GP

U56 DY
SD05C-1-GP

DY

SC1KP50V2KX-1GP

1
1
1
1
1
1

D27
1SS400PT

DY

2nd: 22.10251.491
3nd: 22.10147.131

LOUT1

LINEOUT_JD#
SPKR_R_A1
SPKR_L_A1
MIC_JD#
AUD_MICIN_R
AUD_MICIN_L

For ESD

5V_S0

D28
1SS400PT

DY

PHONE-JK233-GP-U3

LINE OUT

2nd: 22.10251.511
3nd: 22.10147.151

A

EC140

20.D0197.102

2

1
2

1
2

1
2

DY

R326

ACES-CON2-1-GP-U2

EC4
SC100P50V2JN-3GP

TP1
TP2
TP3
TP4

EC3

SC100P50V2JN-3GP

AFTE30-GP
AFTE30-GP
AFTE30-GP
AFTE30-GP

DY
SC100P50V2JN-3GP

SC100P50V2JN-3GP

1
1
1
1

EC2

AUD_MIC_L

DY 10KR2J-3-GP

SHIELDING

DY

SPKR_LSPKR_L+
SPKR_RSPKR_R+

R321
10KR2J-3-GP

2
4
EC1

1

SRN1KJ-7-GP

SC1KP50V2KX-1GP

SPKR_L-

28 AUD_MICIN_L

AUD_MIC_R

3
4

SC1KP50V2KX-1GP

3
1

SPKR_L+

RN66

2
1
1

INTSPK_L

MIC_JD#

28 AUD_MICIN_R

1

20.D0197.102

2

28
ACES-CON2-1-GP-U2

remove to LED Board

NP2
NP1
5
4
3
6
2
1

SC1KP50V2KX-1GP

2
4

2

MICIN1

1

1

2
DY

2

SPKR_R-

AMP_SHUTDOWN# 28,30

Analog Int. Mic

MIC IN

EC60

INTSPK_R

3
1

SHIELDING

Internal Speaker
SPKR_R+

3

Q14
2N7002-11-GP

1

2

C162
SCD1U16V2ZY-2GP

1

1

C163
SCD1U16V2ZY-2GP

2

SPKR_L+
SPKR_L-

BIAS

2

2

2

GND
BEEP
AMP_EN#
SET
BIAS
HP_EN
PGND
ROUT+
ROUTPVDD
HVDD
HP_L
HP_R
HVSS
CVSS

VDD
GND
INR_A
INR_H
INL_A
INL_H
PGND
LOUT+
LOUTPVDD
CVDD
CP+
CGND
CP-

AMP_BEEP 28

DY

29
28
27
26
25
24
23
22
21
20
19
18
17
16
15

DY 0R2J-2-GP

HP_EN

1

C168
SC2D2U6D3V3MX-1-GP

3

1
2
3
4
5
6
7
8
9
10
11
12
13
14

INR_A
INR_H
INL_A
INL_H

R139
0R2J-2-GP
2
1

U18

5V_S0

1

1

1
INL_H

2

1

1

2

2

D

1

FRONTL

C161
SC1U10V3KX-3GP

S

28

R126
40K2R2F-GP

C137

2

C129
SC3D3U10V5KX-2GP

R138
20KR2F-L-GP

INR_H

2

1

1

2

2

1

1

FRONTR

C138

SC10U6D3V5MX-3GP

28

R128
40K2R2F-GP

SCD1U16V2ZY-2GP

C128
SC3D3U10V5KX-2GP

2

2

3D3V_S0

1

2

R137
13KR2F-GP

2

1

SOUNDL

INR_A

1

2

28

Layout Note：
C218,C219,C220 near U110

SB

1

2

C133
SC1U10V3KX-3GP
4

5V_S0

R129
1K5R2F-2-GP

2

2

E

2

1

SOUNDR

D

AUDIO OP AMPLIFIER

SB
C132
SC1U10V3KX-3GP
28

C

AUDIO AMP AND JACK
Size

Document Number

Rev

SB

Cathedral Peak II
Date: Friday, June 20, 2008
D

Sheet
E

29

of

43

A

D24
17

KBRCIN#

17

KA20GATE

18

ECSCI#_1

6

1

KBRCIN#_KBC

5

2

KA20GATE_KBC

4

3

ECSCI#_KBC

SPI_WP#

28

KBC_BEEP

TP172
TP171

FOR KBC DEBUG

PWM0
PWM1
FANPWM1
FANPWM2
FANFB1
FANFB2

1

2

39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
81
82
55
56
57
58
59
60
61
62

KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSO16
KSO17
KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7

87
88
85
86
83
84

PSCLK3
PSDAT3
PSCLK2
PSDAT2
PSCLK1
PSDAT1

KCOL2
KCOL0
KCOL1
KCOL2
KCOL3
KCOL4
KCOL5
KCOL6
KCOL7
KCOL8
KCOL9
KCOL10
KCOL11
KCOL12
KCOL13
KCOL14
KCOL15
KCOL16
KCOL17
KROW0
KROW1
KROW2
KROW3
KROW4
KROW5
KROW6
KROW7

0R2J-2-GP
R359

DY
ECRST#

3D3V_AUX_S5

3D3V_S0

4
3
2
1

RSMRST#_R
KA20GATE
KBRCIN#

KCOL3

1
E

B

2

5
6
7
8

C494
SC1U6D3V2KX-GP

C

RSMRST#

2
0R2J-2-GP

Q19
MMBT3906-3-GP

RN53
21,32

1

DY:

ISP Mode disable
KCOL15
KROW0
E51_RxD
E51_TxD

TP125
TP130
TP166
TP167
TP165
TP169

SRN10KJ-6-GP

3D3V_AUX_S5

KCOL8
KCOL9
KCOL10
KCOL11

TP129
TP124
TP126
TP128

3

TPCLK
TPDATA

1

KBC_GPIO0C

18,27,32,36,37,38

PM_SLP_S3#

PM_SLP_S3#

16 KBC_PWRBTN#
18,27,36,37 PM_SLP_S4#
40
7
14

3D3V_AUX_S5

BAT_IN#
GMCH_BL_ON
BRIGHTNESS

KBC_PWRBTN#
PM_SLP_S4#
BAT_IN#
KBC_GPIO0C
GMCH_BL_ON
BRIGHTNESS

RN56

1
2

GPIO4
GPIO7
GPIO8

17
18
19
25
34

LID_CLOSE#
BAT_IN#

4
3

6
14
15

SRN100KJ-6-GP

16
STDBY_LED
27 WIRELESS_EN
23 BLUETOOTH_EN
31
SPICLK
39
CHG_ON#
14
18

LID_CLOSE#
ECSWI#

STDBY_LED
WIRELESS_EN
BLUETOOTH_EN
SPICLK
CHG_ON#
LID_CLOSE#
ECSWI#

77
78
80
79

GPO3C
GPO3D
GPO3E
GPO3F
AD0
AD1
AD2
AD3

68
70
71
72
63
64
65
66

CCD_ON
USB_PWR_EN#
KBC_GPIO3E
CHG_BCTL1
AD_IA

97
98
99
100
101
102
103
104
105
106
107
108

FLASH_SEL
TP176
WIRELESS_BTN#
WIRELESS_BTN# 16
BT_BTN#
BT_BTN# 16
AMP_SHUTDOWN#
AMP_SHUTDOWN# 28,29
PM_PWRBTN#
PM_PWRBTN# 18,41
S5_ENABLE_KBC
RSMRST#_KBC
RSMRST#_KBC 18
AD_OFF
AD_OFF 40
WLAN_TEST_LED
WLAN_TEST_LED 16
BT_LED
BT_LED
16
DC_BATFULL
DC_BATFULL 16
GPXIOA11
TP177

1

USB_PWR_EN#
TP170
TP173
AD_IA

1

23
RN30

1
2
3
4

39
3D3V_S0

8
7
6
5

WIRELESS_BTN#
BT_BTN#

SRN10KJ-6-GP

R461
S5_ENABLE_KBC

1

2

S5_ENABLE

S5_ENABLE 32,35,41

2K2R2J-2-GP

GPXIOD0
GPXIOD1
GPXIOD2
GPXIOD3
GPXIOD4
GPXIOD5
GPXIOD6
GPXIOD7

109
110
112
114
115
116
117
118

Volume_Up#
Volume_Up# 16
Volume_Down#
Volume_Down# 16
BLON_OUT
BLON_OUT 14,16
SYS_PWR_ACK
TP132
E-BUTTON#
E-BUTTON# 16
KBC_THERMALTRIP#
KBC_THERMALTRIP# 32
KBC_GPXD6
TP131
CRT_DEC#
CRT_DEC# 15

SPICS#
WR#
RD#
GPIO50
AD5
GPIO52

128
120
119
89
76
90

AC_IN#
KBC_MATRIX0#
CHARGE_LED

SPICS#
SPIDO
SPIDI
AC_IN#

E51_TxD
E51_RxD

GPIO19

36
91
93

NUM_LED#
CAP_LED#
FRONT_PWRLED

XCLKI
XCLKO

122
123

KBC_XI
KBC_XO

V18R

124

E51_TxD
E51_RxD

AD_OFF

R3
1
2
1KR2J-1-GP

S5_ENABLE_KBC

R397
1
2
10KR2J-3-GP

3D3V_AUX_S5
R380

DY

2

1

3D3V_S0

10KR2J-3-GP

27
27

KBC_THERMALTRIP#
E-BUTTON#
Volume_Down#
Volume_Up#

DY

SRN10KJ-6-GP

C545
SC100P50V2JN-3GP

DY

C546
SC100P50V2JN-3GP

5V_AUX_S5
E51_RxD

TP174

R364
1
2
10KR2J-3-GP

C537
SC27P50V2JN-2-GP

KBC_XI

KB3310QF-GP

1
2
3
4

16

C543
2 SC3D3U10V5KX-2GP

1

RN57

8
7
6
5

3D3V_AUX_S5

16

NUM_LED# 16
CAP_LED# 16
FRONT_PWRLED

SEL_CP
KBC_GPIO40

74
73

GPIO41
GPIO40

31
31
31
39

CHARGE_LED

30
31

GPIO0A
GPIO18

SMBC_Therm 21
SMBD_Therm 21

TP168

GPIO16
GPIO17

16
32

BAT_SCL
BAT_SDA

BAT_SCL 39,40
BAT_SDA 39,40

GPIO1A
GPIO53
GPIO55

AD4
GPIO54
GPIO56
GPIO57
SPICLK
GPIO59

4

2
R375
0R0603-PAD

SMBD_Therm
SMBC_Therm

GPIO0B
GPIO0C
GPIO0D
GPIO11

75
92
95
121
126
127

RN55
SRN4K7J-12-GP

SCD1U16V2ZY-2GP

3

R381
1KR2J-1-GP

SCL1
SDA1
SDA2
SCL2

GPXIOA0
GPXIOA1
GPXIOA2
GPXIOA3
GPXIOA4
GPXIOA5
GPXIOA6
GPXIOA7
GPXIOA8
GPXIOA9
GPXIOA10
GPXIOA11

SB
2

113
94

AGND

8
7
6
5

21
23
26
27
28
29

GND
GND

2

KBC_BEEP
CHG_I_PWM
KBC_GPIO12
SPI_WP_R#
KBC_GPIO15

R360

DY

ECRST#
KBRST#
SCI#
GA20
PCIRST#

PLT_RST1#_1

2 R392
1
0R0402-PAD

PLT_RST1#

37
2
20
1
13

C498
1
2

AVCC

3D3V_S0

1

31

7,18,25,27,31

SPI_WP_R#

2 R376
1
0R0402-PAD

ECRST#
KBRCIN#_KBC
ECSCI#_KBC
KA20GATE_KBC

22
33
125
111
96
9
67
69
11
24
35

1

1

C514
SC100P50V2JN-3GP

3D3V_AUX_S5

C528
C535
C533
SCD1U16V2ZY-2GP
SC10U10V5ZY-1GP
SCD1U16V2ZY-2GP
L16
BLM11P600S

VCC
VCC
VCC
VCC
VCC
VCC
AVCC
AGND
GND
GND
GND

2

DY

10KR2J-3-GP

2

DY 1

2

SERIRQ
LFRAME#
PCICLK
CLKRUN#
LAD0
LAD1
LAD2
LAD3

2

5V_S5
R372
KBC_GPIO15

3
4
12
38
10
8
7
5

1
2
3
4

SC4D7P50V2CN-1GP

4

INT_SERIRQ
LPC_LFRAME#
PCLK_KBC
PM_CLKRUN#
LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3

2

18 INT_SERIRQ
17,31 LPC_LFRAME#
3
PCLK_KBC
18
PM_CLKRUN#

2

1

17,31 LPC_LAD[0..3]

PCLK_KBC

1

2

2

1

U39

CH731UPT-GP

DY C520

1

3D3V_AUX_S5

1

2
2

4

71.03310.00G

3

2

X5
X-32D768KHZ-38GPU

change to 71.03310.A0G

SB
SEL_CP

2

1

82.30001.691

R379
1

2

1KR2J-1-GP
KBC_XO

1

2nd: 20.K0317.026

C538
SC22P50V2JN-4GP

Internal KeyBoard Connector

AFTE30-GP
AFTE30-GP
AFTE30-GP
AFTE30-GP

TP77
TP61
TP76
TP60

1
1
1
1

KCOL4
KCOL3
KCOL2
KCOL1

EC27
EC26
EC25
EC24

1
DY
1
DY
1
DY
1
DY

2SC220P50V2JN-3GP
2SC220P50V2JN-3GP
2SC220P50V2JN-3GP
2SC220P50V2JN-3GP

1

1
2
RN52
SRN10KJ-5-GP

2

2

DY

TPAD1

14
TP_DATA
TP_CLK

RN50
AFTE30-GP

TP67

1KCOL17 EC40 1DY

2SC220P50V2JN-3GP

AFTE30-GP

TP73

1KCOL0 EC23 1DY

2SC220P50V2JN-3GP

AFTE30-GP
AFTE30-GP
AFTE30-GP
AFTE30-GP

TP74
TP71
TP85
TP70

1
1
1
1

KROW0 EC41
KROW7 EC48
KROW6 EC47
KROW5 EC46

1
DY
1
DY
1
DY
1
DY

2SC220P50V2JN-3GP
2SC220P50V2JN-3GP
2SC220P50V2JN-3GP
2SC220P50V2JN-3GP

TPDATA
TPCLK

1
2

4
3

TP_DATA
TP_CLK
TP_LEFT
TP_RIGHT

DY

TP_RIGHT

1

12

T/P

EC132

4
3

KROW0
KROW1
KROW2
KROW3
KROW4
KROW5
KROW6
KROW7

2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26

1

KCOL1
KCOL2
KCOL3
KCOL4
KCOL5
KCOL6
KCOL7
KCOL8
KCOL9
KCOL10
KCOL11
KCOL12
KCOL13
KCOL14
KCOL15
KCOL16
KCOL17

KCOL0

SCD1U10V2KX-4GP

5V_S0

TP_DATA
TP_CLK

DY

SRN33J-5-GP-U
TP_LEFT

EC131

EC130

12
11
10
9
8
7
6
5
4
3
2

DY

1

EC135

2

2SC220P50V2JN-3GP
2SC220P50V2JN-3GP
2SC220P50V2JN-3GP
2SC220P50V2JN-3GP

DY

EC134

1

1
DY
1
DY
1
DY
1
DY

2

EC31
EC30
EC29
EC28

1

KCOL8
KCOL7
KCOL6
KCOL5

2

1
1
1
1

EC129
KB1

1

TP80
TP62
TP75
TP59

5V_S0

2

AFTE30-GP
AFTE30-GP
AFTE30-GP
AFTE30-GP

TOUCH PAD

1

2SC220P50V2JN-3GP
2SC220P50V2JN-3GP
2SC220P50V2JN-3GP
2SC220P50V2JN-3GP

DY

SC220P50V2JN-3GP

1
DY
1
DY
1
DY
1
DY

SC220P50V2JN-3GP

EC39
EC38
EC37
EC36

SC100P50V2JN-3GP

KCOL16
KCOL15
KCOL14
KCOL13

SC100P50V2JN-3GP

1
1
1
1

SCD1U10V2KX-4GP

TP84
TP66
TP82
TP65

1

28

27

EMI Bypass cap.

AFTE30-GP
AFTE30-GP
AFTE30-GP
AFTE30-GP

1

20.K0204.026
ACES-CON26-GP-U

CP Pull Low

2

1

13

Internal KeyBoard CONN
25

AFTE30-GP
AFTE30-GP
AFTE30-GP
AFTE30-GP

TP79
TP69
TP78
TP68

1
1
1
1

KROW4 EC45
KROW3 EC44
KROW2 EC43
KROW1 EC42

1
........

CHECK KB SPEC. AND PIN DEFINE

1
DY
1
DY
1
DY
1
DY

2SC220P50V2JN-3GP
2SC220P50V2JN-3GP
2SC220P50V2JN-3GP
2SC220P50V2JN-3GP

LEFT1

2

ACES-CON12-4-GP-U

RIGHT1
TP_LEFT
4

2

TP_RIGHT
4

2nd: 20.K0359.012
5

AFTE30-GP
AFTE30-GP
AFTE30-GP
AFTE30-GP

TP83
TP64
TP81
TP63

1
1
1
1

KCOL12
KCOL11
KCOL10
KCOL9

1
EC35
EC34
EC33
EC32

1
DY
1
DY
1
DY
1
DY

2SC220P50V2JN-3GP
2SC220P50V2JN-3GP
2SC220P50V2JN-3GP
2SC220P50V2JN-3GP

20.K0228.012

5

3

1

SW-TACT-122-GP

1
1
1
1
1

AFTE30-GP
AFTE30-GP
AFTE30-GP
AFTE30-GP
AFTE30-GP

TP108
TP104
TP107
TP103
TP106

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

3
SW-TACT-122-GP

62.40009.681

5V_S0
TP_DATA
TP_CLK
TP_RIGHT
TP_LEFT

Title

62.40009.681

2nd: 62.40009.671
A

KBC ENE3926

Size
A2

Document Number

Date:

Friday, June 20, 2008

Rev

SB

Cathedral Peak II
Sheet

30

of

43

A

B

C

D

E

3D3V_AUX_S5
ERN1

5
6
7
8

SPICLK_ROM 1
SPIDO_ROM 2
SPIDI_ROM
3
4

RN58

3D3V_AUX_S5

SRN10KJ-6-GP

4

8
7
6
5

SPICLK 30
SPIDO
30
SPIDI

ER2
0R0603-PAD

SPIDI_ROM
SPI_WP#

CS#
DO
WP#
GND

8
7
6
5

VCC
HOLD#
CLK
DIO

3D3V_AUX_S5_SPI_ROM
SPI_HOLD#
SPICLK_ROM
SPIDO_ROM

SC4D7P50V2CN-1GP

16M Bits
SPI FLASH ROM
3

MXIC: 72.25165.A01
WinBond: 72.25X16.001

2

EC167

2

1

W25X16VSSIG-GP

72.25X16.001

2

EC160
SC4D7P50V2CN-1GP

1

1

SPI_WP#

1
2
3
4

1

U50
SPICS#

30

EC159
SC4D7P50V2CN-1GP

2

4
3
2
1

2

SRN150F-1-GP

SPI_HOLD#

30

30

1

4

EC166
SC4D7P50V2CN-1GP

3

TOP VIEW

2

A15

(B1)

A14

(B2)

17,30 LPC_LAD[0..3]

LPC_LAD[0..3]

GOLDEN FINGER FOR DEBUG BOARD

....

....

5V_S0

A2

(B14)

A1

(B15)

2

5V_S0
U27

7,18,25,27,30 PLT_RST1#
17,30 LPC_LFRAME#
PCLK_FWH

PCLK_FWH

1

3

R444 DY
100R2J-2-GP

17

2

1

2

(BOTTOM VIEW)

PLT_RST1#
LPC_LFRAME#

PCLKFWH
C575 DY
SC10P50V2JN-4GP

FWH_INIT#

FWH_INIT#
LPC_LAD3
LPC_LAD2
LPC_LAD1
LPC_LAD0
EXT_FWH#
3D3V_S0

A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15

A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15

B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15

B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15

PLT_RST1#
LPC_LFRAME#
PCLK_FWH
FWH_INIT#
LPC_LAD3
LPC_LAD2
LPC_LAD1
LPC_LAD0
EXT_FWH#

TP135 TPAD28

3D3V_S0

FOX-GF30

ZZ.GF030.XXX
1

PCLK_FWH

2

1

1

EC171
SC5P50V2CN-2GP

DY

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size

BIOS/GOLDEN FINGER
Document Number

Rev

SB

Cathedral Peak II
Date: Friday, June 20, 2008
A

B

C

D

Sheet
E

31

of

43

Aux Power

3D3V_AUX_S5

Run Power
5V_AUX_S5

I min = 300 mA

3D3V_AUX_S5

5V_S5

5V_S0

DY U40

330KR2J-L1-GP

DY

R445
100KR2J-1-GP

Z_12V_D4

2

3D3V_runpwr 2

K

C572

R438

D26
PDZ9D1B-GP

3D3V_S0

3D3V_S5

83.9R103.C3F
1
2
3
4

U53
S
S
S
G

D
D
D
D

8
7
6
5

AO4468-GP

84.04468.037

Q32
Z_12V_D3

DY

D

2

DY

Z_12V_G3

2

2

A

R430
100R5J-3-GP

AO4468-GP

1

1
R439

2

R442
1

8
7
6
5

D

10KR2J-3-GP

1

R383
0R0402-PAD
2
1

D
D
D
D

84.04468.037
S

330KR2J-L1-GP

C508
SCD1U10V2KX-4GP

SCD1U25V3KX-GP

2

3D3V_S0

2

1
2
3
4

2

RUN_POWER_ON

1

DY

Z_12V

SCD22U25V3KX-GP

5V_AUX_S5

R435
1

G

74.09198.G7F

Q26
NDS0610-NL-GP

DCBATOUT
C522

10KR2J-3-GP

3D3V_AUX_S5_EN

RT9198-33PBR-GP

DY

C273
1

1

4
1

5

NC#4

2

VOUT

1

2

C517

VIN
GND
EN/EN#

SC1U16V3ZY-GP

SC1U16V3ZY-GP

Q27
2N7002-11-GP

Z_12V_D3

3

5

2

6

1

S

G

4

2N7002DW-1-GP
R103
EMC2102_PWROK 2

DY

84.27002.D3F
1

PWROK

PM_SLP_S3# 18,27,30,36,37,38

0R2J-2-GP

3D3V_S5
SCD1U16V2KX-3GP
C579
1

U14

B

2

A

5

Y

4

DY
PWROK 7,18

GND
74LVC1G08GW-1-GP

1

1D05V_S0

1D05V_S0

R426
2K2R2J-2-GP

2

2

DY
R425
56R2J-4-GP

1

C561
1

PM_THRMTRIP-A# 4,7,17

B

DY

DY
R440
4,17,41 H_PWRGD

2H_PWRGD#

1
1KR2J-1-GP

C574
SCD1U16V2ZY-2GP

2
D25
BAS16PT-GP
30,35,41 S5_ENABLE

E

E

3

VCC

2

B

3

C

PM_SLP_S3#

1

1

21 EMC2102_PWROK
18,27,30,36,37,38

EMC2102_PWROK

C

2
SCD1U16V2ZY-2GP

KBC_THERMALTRIP# 30

Q25

Q24
MMBT2222A-3-GP

MMBT3904-3-GP

2

DY

1

1
2
3

U22
S
S
S
G

RSMRST# 21,30

1

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size

RUN POWER and 3D3V_AUX_S5
Document Number

Rev

SB

Cathedral Peak II
Date: Friday, June 20, 2008

Sheet

32

of

43

5

4

3

CPU_CORE
ISL6266A
VID0
D

VID1
VID2
VID3
VID4
VID5
VID6

Output Signal

VID Setting
VID0(I / 3.3V)

2

PGOOD

Output Power

Input Power
DCBATOUT_51125

VGATE_PWRGD

1D5V_S0
1D8V_S3

5V_S5 (6A)

5V(O)

VIN

VID2(I / 3.3V)

Input Signal

S5_ENABLE

VID3(I / 3.3V)
VID4(I / 3.3V)

VCC_CORE_PWR(O)

3D3V(O)

EN0

Output Power
VCC_CORE(Imax=38A) ALW_PWRGD_3V_5V

PM_SLP_S3#

3D3V_S5 (6A)

RT9026

PGOOD

3D3V(O)

3D3V_AUX_S5

5V_S5

EN (I / 3.3V)

VID0

VID0(I / 3.3V)

0D9V_S3_1

VTTREF

S5

VID1(I / 3.3V)

VID2

VID2(I / 3.3V)

VID3

RGND(I / Vcore)

S3

C

VID1

VSEN(I / Vcore)

CPUCORE_ON

PGOOD

0D9V_S3 (1A)

VTT

VLDOIN

PM_SLP_S4#

Output Signal

VID Setting

0D9V_S0

VIN

1D8V_S3

GFX_CORE
ISL6263A

VID6(I / 3.3V)

CPUCORE_ON

PGOOD

EN

5V_AUX_S5

5V(O)

Output Signal

VID5(I / 3.3V)

Voltage Sense

VSS_SENSE

1D5V_S0 (2.5A)

1D5V(O)

D

C

VCC_SENSE

VIN

VID1(I / 3.3V)

Input Signal
CPUCORE_ON

1

RT9018A

TPS51125
5V/3D3V

VID3(I / 3.3V)

VID4

VID4(I / 3.3V)

Input Power
DCBATOUT_6266A
5V_S0
3D3V_S0

VDD

DCBATOUT

VCC(I)

B

PM_SLP_S3#

DCBATOUT_51124

PM_SLP_S4#
PM_SLP_S3#
A

VDD
VCC
Input Signal

VCC_AXG_SENSE

Output Power
1D8V (O)

1D05V(O)

1D8V_S3 (10A)

VSS_AXG_SENSE

Input Signal
CHG_ON#

Input Signal
VR_ON

24750_CELLS

Output Signal
AC_IN#

ACGOOD#

CHGEN#

B

AD_IA

SRSET

CELLS

Voltage Sense
VSEN(I / Vcore)

Input Power

RGND(I / Vcore)

AD+

ACN

EN1

Input Signal
AD_OFF

BT+

VOUT (O)

Output Signal
(O)

(I)

Output Power
VOUT (O)

Adapter

1D05V_S0 (15A)

EN2

Charger BQ24745

VCC_GFXCORE(5.5A)

GFXVR_EN

TPS51124
1D8V/1D05V
5V_S5

VGFXCORE (O)

VIN

VCC(I)

Input Power

Output Power

Input Power

5V_S0

VCC(I)

DCBATOUT

AD_IN#

Wistron Corporation
CPUCORE_ON

Output Signal

Input Power

PGOOD1

AD_JK

PGOOD2

5V_AUX_S5

VCC(I)

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Output Power
VCC(O)

Title

AD+

Power Sequence Logic
Size
B

VCC(I)

Document Number

Date: Friday, June 20, 2008
5

4

3

2

Rev

Cathedral Peak II
Sheet
1

33

of

SB
43

A

2
1

C29

1

26266A_VO

SCD22U10V2KX-1GP

2

1

2

1

1

1

1

1

2

2

2

1

2
1

C322
SCD1U50V3KX-GP

DY

L9
6266A_PHASE2

VCC_CORE

B

1
2
IND-D36UH-9-GP

one phase

5
6
7
8

one phase

TC6

2

2

CAP

G3
GAP-CLOSE

1

4
3
2
1

2
10R2F-L-GP
C40
SC1U25V0KX-GP

U28
BSC057N03MSG-GP

5V_S0
R50
1

4
3
2
1

BSC057N03MSG-GP

2

U7

one phase

5
6
7
8

5V_S0

TC4

CAP

G39
GAP-CLOSE

6266A_LGATE2
R64
1

2
0R0402-PAD

C42
SCD01U25V2KX-3GP

6266A_VSUM
6266A_ISEN2

6266A_ISEN1

Single Phase
R47=1.2K, R63=5.6K,R460=0R
C33=47p, C49=0.033u, C52=0.1u

R62
1
R56
1
R45
1
R42
1

one phase
2 3K65R2F-1-GP

6266A_ISEN2_P2_VCORE

2 10KR2F-2-GP

one phase
one phase
1R2F-GP

2

6266A_ISEN1_P2_VCORE
A

2 10KR2F-2-GP

one phase

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

ISL6266A_CPU_CORE

DY=U7,U28,U29,L9,R62,R56,R42,
R45,R37,R39,R48,C20
4

C14

DY

Cyntec 10*10*4
DCR=1.05+-5%mohm, Irating=30A
Isat=60A

6266A_UGATE2

R460

C319

DY

1

C31

4
3
2
1

6266A_ISEN1

one phase

5
6
7
8

2

C36

Size
A3

Document Number

Date: Friday, June 20, 2008
5

2

2
2

2

2008/05/06
U29
BSC120N03MS-G-GP

1 DY
2
0R2J-2-GP

1

1
1

one phase

1
2
1

5
6
7
8

R37
6266A_BOOT2 1
26266A_BOOT2_R
2D2R2J-GP

R260
NTC-10K-9-GP

2

2

DCBATOUT_6266A

SB

one phase

2

25

6266A_ISEN2_P1_VCORE

1

NC#25

2 10KR2F-2-GP

2

26

2 1R2F-GP

1 R48

1

BOOT2

one phase

1 R46

2

UGATE2

6266A_UGATE2

ISEN1

ISEN2

28
27

6266A_ISEN2
C20
SCD22U25V3KX-GP

24

6266A_ISEN2
23

VDD

GND

22
6266A_VDD

21

PHASE2

1
1

1

SCD022U25V3JX-U-GP
2

6266A_VSUM_R_VO

4
3
2
1

4
3
2
1

VID1

VID2

VID3

VID4

VID5
VSUM

VIN
6266A_VIN 20

VO

DFB
6266A_DFB 17

18
1
6266A_VO
6266A_VSUM 19
2
2

2
1
2

6266A_VO
6266A_PHASE2

2

1
2
1

2 10KR2F-2-GP

one phase

SE330U2VDM-L-GP

2

1 R39

SE330U2VDM-L-GP

1

6266A_ISEN1

SC2D2U16V3KX-GP

S
S
S
G

2

2

1

29

1

6266A_VO

one phase

one phase

1

1
PGND2

R69
2K61R2F-1-GP

R63
11KR2F-L-GP

BSC057N03MSG-GP

5
6
7
8
6266A_LGATE2

6266A_ISEN1_P1_VCORE

D
D
D
D

C49

2

4
3
2
1

6266A_D0

37

2

6266A_D1

38

2

6266A_D2

39

2

6266A_D3

40

2

6266A_D4

41

2

6266A_D5

42

2

6266A_D6

2

6266A_VR_ON 2

44

43
VID6

VR_ON

VID0

5V_S0

30

S
S
S
G

SCD01U25V2KX-3GP

6266A_VO

5
6
7
8

H_VID0

H_VID1

H_VID2

H_VID3

H_VID4

H_VID5

H_VID6

0R0402-PAD

1
R17

R18 1
0R0402-PAD
R19
1
0R0402-PAD
R20
1
0R0402-PAD
R21
1
0R0402-PAD
R22
1
0R0402-PAD
R23
1
0R0402-PAD
R24
1
0R0402-PAD
R25
1
0R0402-PAD

31

C39

SCD33U10V3KX-3GP

one phase

2 3K65R2F-1-GP

20080605

A

C52
SCD22U50V3ZY-1GP

1 R67

SCD22U10V2KX-1GP

R53

10R3F-GP

C47

2
1
R58
0R0402-PAD

6266A_VSUM

SC180P50V2JN-1GP

R57
0R0402-PAD
2
1

VSS_SENSE

PVCC

1

G4
GAP-CLOSE

C

6266A_VSUM
C18

LGATE2

DCBATOUT_6266A

C43

C34
SC330P50V2KX-3GP
5

499R2F-2-GP

1
R16

6266A_DPRSLPVR2

DPRSTP#

POWER SB

20080605
one phase

C41
SC330P50V2KX-3GP

VCC_SENSE

6266A_ LGATE1

TC3

CAP

6266A_ LGATE1
C17
SCD22U25V3KX-GP

2

D
D
D
D

1K74R2F-GP
1
2

1

DY

5

R59

R47

2
R459
1KR2J-1-GP

32

D

VCC_CORE

TC16

CAP

SC10U25V6KX-1GP

6266A_SOFT

2
1KR2F-3-GP

33

G40
GAP-CLOSE

SC10U25V6KX-1GP

74.06266.073

DROOP

FB2
RTN

6266A_FB2 12

6266A_RTN 15

FB

16
16266A_DROOP

COMP

6266A_FB 11

VDIFF

VW

1KR2F-3-GP

R60
1

DPRSLPVR

OCSET

6266A_VDIFF
B

PGND1
LGATE1

NTC

R52
1KR2F-3-GP
ISL6266AHRZ-GP

C46
2 6266A_FB2_R 1
2
100R2F-L1-GP-U
SC2200P50V2KX-2GP

6266A_DPRSTP# 2

6266A_3V3

6266A_PHASE1

SOFT

Vcc_core
Iomax=38A

TC2

CAP

SC10U25V6KX-1GP

2
SC270P50V2KX-1GP

48

34

S
S
S
G

R65
1

2 6266A_COMP_R
97K6R2F-GP

C32
1

PHASE1

VR_TT#

U31

D
D
D
D

R54
1

2
10K5R2F-GP

PMON

1

one phase

1
R44
2
SC100P50V2JN-3GP

35

6266A_COMP
10

2

C33
1

36

UGATE1

6266A_VDIFF
13

POWER SA

3V3

49
GND

2
1
2

6266A_NTC
1 R259
26266A_NTC_R1 R35
2
6
NTC-470K-1-GP
4K02R2F-GP
C26
C21
6266A_SOFT
1
2
7
SCD015U50V3KX-GP
1
2
SCD01U25V2KX-3GP
6266A_VO 1
26266A_OCSET
8
R38
12KR3F-GP
C28 1
6266A_VW 9
2 SC1000P50V3JN-GP

BOOT1

PSI#

RBIAS

DY

SE330U2VDM-L-GP

4 CPU_PROCHOT#_R

C331
SCD1U50V3KX-GP

SE330U2VDM-L-GP

2

DY

SE330U2VDM-L-GP

R28
6266A_PMON_R 1
R30
SCD1U25V3KX-GP
1
R32

C

C16
1

POWER SB
R29
6266A_BOOT1 1
2
6266A_BOOT1_R
2D2R2J-GP
1
6266A_UGATE1

PGOOD

16266A_PSI# 2
0R0402-PAD
2 6266A_PMON
3
4K99R2F-L-GP
26266A_RBIAS4
147KR2F-GP
5

U11
BSC057N03MSG-GP

Id=19.5A
Qg=21.5~33nC,
Rdson=5.5~6.7mohm

S
S
S
G

1
2

PSI#

DY

C38

D
D
D
D

4

C37

L8
1
2
IND-D36UH-9-GP

6266A_PHASE1

S
S
S
G

R27
1K91R2F-1-GP

C15

Cyntec 10*10*4
DCR=1.05+-5%mohm, Irating=30A
Isat=60A

6266A_UGATE1

U5

7,18,21 VGATE_PWRGD

R33
68R2-GP

U30
BSC120N03MS-G-GP

D
D
D
D

1

3D3V_S0

45

2

SCD1U10V2KX-4GP

46

1

DY

SB

1D05V_S0

1 0R2J-2-GP

2
C13

GAP-CLOSE-PWR

R456
R456
2

GM45

GAP-CLOSE-PWR

1

GAP-CLOSE-PWR
G29
1
2

47

2
1

TC1
SE100U25VM-L1-GP

2

GAP-CLOSE-PWR
G30
1
2

5

SC10U25V6KX-1GP

GAP-CLOSE-PWR
G36
1
2

H_VID[6..0]

SC10U25V6KX-1GP

GAP-CLOSE-PWR
G31
1
2

R26
10R3F-GP

SC10U25V6KX-1GP

DY

36,37,38

S
S
S
G

D

GAP-CLOSE-PWR
G37
1
2

TC13
ST15U25VDM-1-GP

CPUCORE_ON

2

SB

2008/05/06
D
D
D
D

GAP-CLOSE-PWR
G38
1
2

CLK_EN#

1
1

2

3D3V_S0

1

G32

1

DCBATOUT_6266A

PM_DPRSLPVR 7,18

VSEN

G35

1

4,7,17 H_DPRSTP#

DCBATOUT_6266A

6266A_VSEN
14

DCBATOUT

2

1

DCBATOUT_6266A

3

2

DCBATOUT

4

2

5

3

2

Rev

SB

Cathedral Peak II
Sheet
1

34

of

43

5

4

3

2

1

POWER SA

1

GAP-CLOSE-PWR
G26
1
2

GAP-CLOSE-PWR
G95
1
2

GAP-CLOSE-PWR
G25
1
2

GAP-CLOSE-PWR
G97
1
2

GAP-CLOSE-PWR

GAP-CLOSE-PWR

3
4

4

3

5

5

2

1

6

6

1

51125_ENTIP1

51125_ENTIP2
C495

R361
110KR3F-GP

GAP-CLOSE-PWR
G15
1
2

DY

GAP-CLOSE-PWR
G18
1
2
GAP-CLOSE-PWR
G17
1
2
GAP-CLOSE-PWR

DCBATOUT_51125

DCBATOUT_51125

SB

ENTRIP2

PGOOD

23

51125_PGOOD

ENTRIP1

1

51125_ENTIP1

VREF

GND

15

4

TONSEL

GND

25

14

SKIPSEL

VCLK

18

2

2

51125_VREF

2

1
DY
0R2J-2-GP
C506
SC10U10V5KX-2GP

R390
A

1
DY
0R2J-2-GP

5
6
7
8
D
D
D
D

1
2

1

G
S
S
S

VREG5

DY

1 2
1
1

2

3D3V_AUX_S5

2

1

TC11

B

R370
30KR2F-GP

DY

R363
20KR2F-L-GP

DY

Close to VFB Pin (pin2)

C512
SC10U10V5KX-2GP
A

R389

Close to VFB Pin (pin5)

C481

51125_FB1_R

R377
100KR2J-1-GP

GAP-CLOSE-PWR-3-GP

DY

2

D
D
D
D

C500
SC18P50V2JN-1-GP

3D3V_S5
5V_AUX_S5

2

R362
3D3V_AUX_S5

R373
0R2J-2-GP

TPAD28

17

VREG3
2

15V_AUX_S5_51125

1

GAP-CLOSE-PWR-3-GP

S

Id=7.7A
Qg=8.5~13nC
Rdson=16.5~21mohm

51125_VCLK

G78

2

R365
0R0402-PAD
2
1

G77

3D3V_AUX_S5_5_51125 8

74.51125.073
3D3V_AUX_S5

1

TPS51125RGER-GP

G

G74

1

1

51125_TONSEL

EN0

3

51125_SKIPSEL

2
1

51125_VREF

2 51125_EN 13
820KR2F-GP
51125_ENTIP2 6

VFB2

2

1
2

51125_FB1

4
3
2
1

1

VFB1

2

VO2

2

1
1 2

51125_FB2_R
C501
DYSC18P50V2JN-1-GP

C497

5

2

1
2
3
4

1
2
1

Id=7.7A
Qg=8.5~13nC
Rdson=16.5~21mohm

7

51125_FB2

ST220U6D3VDM-15GP

2

24

IND-3D3UH-57GP

D
SCD1U10V2KX-4GP

R366
10KR2F-2-GP

VO1

51125_VO1

5V_PWR

2

GAP-CLOSE-PWR-3-GP

51125_VREF

51125_VO2

SI4812BDY-T1-E3-GP

R374
0R2J-2-GP

G

SCD22U6D3V2KX-1GP

R371
6K65R2F-GP

1
R384

G
S
S
S

SI4812BDY-T1-E3-GP

S

DY

51125_DRVL1
U25

D
D
D
D

GAP-CLOSE-PWR-3-GP

ST220U6D3VDM-20GP

SCD1U10V2KX-4GP

G75

19

8
7
6
5

1

U49

LL1
DRVL1

Iomax=5A

L3

1

1

DRVL2

51125_LL1

2

12

51125_DRVH1

20

1

LL2

51125_DRVL2

D

21

Cyntec 7*7*3
DCR=30mohm, Irating=6A
Isat=13.5A

S

2

11

G

1

51125_LL2

VBST1
DRVH1

2

2

DRVH2

1

2

10

51125_VBST1

GL40

1

VBST2

51125_DRVH2

22

5
6
7
8

9

SI4800BDY-T1

C507
SCD1U25V3KX-GP

DY

G
S
S
S

51125_VBST2

D

U24

C

4
3
2
1

C293
1

SCD1U25V3KX-GP

L20

2

1

2

1
2

VIN
1
2
3
4

G

2

1
2
IND-3D3UH-57GP

2

U37

Id=7A
Qg=8.7~13nC
Rdson=23~30mohm

G
S
S
S

S

3D3V_PWR

TC12

16

8
7
6
5

2

1
2

2

1

Id=7A
Qg=8.7~13nC
Rdson=23~30mohm

C532
SCD01U50V2KX-1GP

U48
SI4800BDY-T1

C292
SC10U25V6KX-1GP

D

C294
SC10U25V6KX-1GP

DY

GL40

D
D
D
D

Iomax=5A

DY

C521
SCD01U50V2KX-1GP

C523
SC10U25V6KX-1GP

DY

SC10U25V6KX-1GP

SCD01U50V2KX-1GP

Cyntec 7*7*3
DCR=30mohm, Irating=6A
Isat=13.5A

C526

C518
SC10U25V6KX-1GP

C290

C

1

DCBATOUT_51125

B

C291

R221
100KR3F-GP

D

GAP-CLOSE-PWR
G13
1
2

51125_ENTIP1
2N7002DW-1-GP

2N7002DW-1-GP

DY

GAP-CLOSE-PWR
G16
1
2

S5_ENABLE 30,32,41

1

GAP-CLOSE-PWR
G91
1
2

4

2

2

GAP-CLOSE-PWR
G81
1
2

3

1

GAP-CLOSE-PWR
G101
1
2

51125_ENTIP2
30,32,41 S5_ENABLE

2

GAP-CLOSE-PWR
G14
1
2

Q21

RN60
SRN100KJ-6-GP

2

GAP-CLOSE-PWR
G83
1
2

Q20

2
1

GAP-CLOSE-PWR
G93
1
2

1

GAP-CLOSE-PWR
G28
1
2

TC27
ST15U25VDM-1-GP

C570

5V_S5
G12

1

2

2

DY

5V_PWR

5V_AUX_S5

2

GAP-CLOSE-PWR
G99
1
2

SC18P50V2JN-1-GP

GM45

1

GAP-CLOSE-PWR
G27
1
2

2

TC25
SE68U25VM-3-GP

3D3V_S5
G98

SC18P50V2JN-1-GP

2

1

SB

3D3V_PWR

1

D

DCBATOUT_51125
G79
1
2

2

DCBATOUT

Wistron Corporation

1
0R2J-2-GP

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

R391

2

DY

Title

1
0R2J-2-GP

DCDC 5V/3D3V (TPS51125)
Size
A3

Document Number

Date: Friday, June 20, 2008
5

4

3

2

Rev

SB

Cathedral Peak II
Sheet
1

35

of

43

5

4

3

2

1

1D5V_S0
Iomax=2.5A
D

D

1D8V_S3
5V_S5
G7

1

1
1

C127
SC10U10V5ZY-1GP

C131
SC1U16V3ZY-GP

2

2

C126
SC10U10V5ZY-1GP

2

1

DY

1

1

GAP-CLOSE-PWR
G8
2

1

GAP-CLOSE-PWR
G6
2

Vo(cal.)=1.5024V
1D5V_LDO
R117
2
15912_EN_U111
0R0402-PAD

1

1
R119
2K2R2J-2-GP

R131
20K5R2F-GP

R120
2
1
0R0402-PAD

34,37,38 CPUCORE_ON

GAP-CLOSE-PWR

1

DY

C155

C

2

74.09018.A3D

2

C

C156

2

2

2

5912_FB_U111

U17
RT9018A-25PSP-GP

1

C154

R132
18KR2J-GP

2

5
6
7
8

1D5V_S0

SC10U10V5ZY-1GP

NC#5
VOUT
ADJ
GND

SC10U10V5ZY-1GP

3D3V_S0

VDD
VIN
EN
PGOOD

SC100P50V2JN-3GP

4
3
2
1

1

9

PM_SLP_S3#

1

PM_SLP_S3#

GND

18,27,30,32,37,38

2
GAP-CLOSE-PWR
G9
2

5912_POK_U111

Vo=0.8*(1+(R1/R2))

B

B

2

G19

1

74.09026.079

11

RT9026PFP-GP

2

2
C285
SC10U10V5ZY-1GP

1

GAP-CLOSE-PWR

1

C284
SC1U10V2ZY-GP

GAP-CLOSE-PWR
G21
1
2

1
2
3
4
5

2

VIN
VDDQSNS
S5
VLDOIN
GND
VTT
S3
PGND
VTTREF VTTSNS
GND

9026_S3

2

10
9
8
7
6

9026_S5

1

DDR_VREF_S3_1

R220
2
1
0R0402-PAD
R218
2
1
0R0402-PAD

2

GAP-CLOSE-PWR
G20
1
2

U23

18,27,30,37 PM_SLP_S4#

DDR_VREF_S3

DDR_VREF_PWR

C288
SCD1U10V2KX-4GP

1

1

C289
SC10U10V5ZY-1GP

2

C287
SC1U10V3ZY-6GP

Iomax=1A
OCP>2A

1D8V_S3

1

5V_S5

C286
SC10U10V5ZY-1GP

A

A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
A3

Document Number

Date: Friday, June 20, 2008
5

4

3

2

1D5V & 0D9V

Rev

SB

Cathedral Peak II
Sheet
1

36

of

43

5

4

3

2

1

1D8V_PWR

1

G94

D

2
C553
SC10U25V6KX-1GP

GL40

D
D
D
D
U45
SI4800BDY-T1

2
1

G
S
S
S

4
3
2
1

1

2

GND

OPEN

V5FILT

240k/CH1
300k/CH2

300k/CH1
360k/CH2

360k/CH1
420k/CH2

1
G
S
S
S

GAP-CLOSE-PWR
G69
1
2
GAP-CLOSE-PWR
G67
1
2

1
1

DY

1
2

C503

B

GAP-CLOSE-PWR
G65
1
2

TC21

GAP-CLOSE-PWR
G63
1
2
GAP-CLOSE-PWR
G46
1
2
GAP-CLOSE-PWR
G60
1
2

1D05V Iomax=10.5A
OCP>20A

2

51124_V5FILT

R236
30KR2F-GP

4
3
2
1

Id=7.7A
Qg=8.5~13nC
Rdson=16.5~21mohm

C303

1

1
2

2

D
D
D
D

DY

51124_VFB2
U46
SI4812BDY-T1-E3-GP

SCD1U16V2KX-3GP

TONSEL

R237
10K7R2F-GP

2

GAP-CLOSE-PWR
G70
1
2

1D05V_PWR

L19

5
6
7
8

2
R238
0R2J-2-GP

1

2
10KR2J-3-GP

51124_VBST2

1

C567
1

DY

2

1

2
1
G
S
S
S

Cyntec 10*10*4
DCR=4.2mohm, Irating=16A
Isat=33A
1
2
IND-D56UH-12-GP

DY R234

C550

SC10U25V6KX-1GPDY

1

2

5
6
7
8
D
D
D
D
U47
SI4800BDY-T1

1

ST330U2D5VDM-9GP

2

1

2

2

24
7

VO1
VO2

1

1
2

C563
C556
SC10U25V6KX-1GP

GL40

Id=7A
Qg=8.7~13nC
Rdson=23~30mohm

1D05V_S0
G71

SCD1U10V2KX-4GP

51124_VBST1

SCD1U16V2KX-3GP
51124_LL2

C

GAP-CLOSE-PWR
G59
1
2

1D05V_PWR

SC18P50V2JN-1-GP

2

GAP-CLOSE-PWR
G48
1
2

GAP-CLOSE-PWR

TPS51124RGER-GPU1

51124_TONSEL

51124_LL1

GAP-CLOSE-PWR
G51
1
2

1D8V Iomax=10A
OCP>15A

Id=7.7A
Qg=8.5~13nC
Rdson=16.5~21mohm

51124_DRVH2
51124_LL2
51124_DRVL2

10
11
12

74.51124.073

R424
20KR3F-GP

C571
1

GAP-CLOSE-PWR
G53
1
2

SB
DRVH2
LL2
DRVL2

51124_TRIP1
51124_TRIP2

R420
17K8R3F-1-GP

B

DY

GAP-CLOSE-PWR
G50
1
2

TC22

DCBATOUT_51124

17
14

BC1
SCD47U6D3V2KX-GP

2

51124_DRVH1
51124_LL1
51124_DRVL1

21
20
19

R235
21K5R3F-GP

4
3
2
1

GND
GND
PGND2
PGND1

PGOOD1
PGOOD2

EN1
EN2

3
25
13
18

TONSEL

23
8

DRVH1
LL1
DRVL1

4

51124_EN1
51124_EN2

VBST1
VBST2

V5FILT
V5IN

R441
2
1
0R0402-PAD

DY1

2
5
VFB1
VFB2

15
16

TRIP1
TRIP2

51124_V5FILT

C582
SC1000P50V3JN-GP

GAP-CLOSE-PWR
G54
1
2

SCD1U50V3KX-GP

PM_SLP_S3#

U44
SI4812BDY-T1-E3-GP

1
R447
0R2J-2-GP

22
9

BC2
SCD47U6D3V2KX-GP

2

18,27,30,32,36,38

SC1U10V3KX-3GPU54

1
6

1

DY1

51124_VFB1

2

C559

2

R443
2
1
0R0402-PAD

2

D
D
D
D
51124RGER_PG1
51124RGER_PG2

1
18,27,30,36 PM_SLP_S4#

1D05V_PWR
1D8V_PWR
51124_VFB2
51124_VFB1

2

C

2

1

R230
3D3R3J-L-GP

GAP-CLOSE-PWR
G56
1
2

SE330U2D5VDM-LGP

DY

C504
SCD1U10V2KX-4GP

R239
30KR2F-GP

C304

2

1
2
IND-1D5UH-34-GP

C581
SC1000P50V3JN-GP

2

G
S
S
S

34,36,38

DY

SC18P50V2JN-1-GP

2

5V_S5

GAP-CLOSE-PWR
G55
1
2

1D8V_PWR

L18

1

CPUCORE_ON

1

GAP-CLOSE-PWR

Id=7A
Qg=8.7~13nC
Rdson=23~30mohm

2008/06/16

R446
0R2J-2-GP
2
1

4
3
2
1

SB

5
6
7
8

GAP-CLOSE-PWR
G96
1
2

Cyntec 10*10*4
DCR=4.2mohm, Irating=16A
Isat=33A

1

GAP-CLOSE-PWR
G92
1
2

C549

DY

1

1

5
6
7
8

C560
SC10U25V6KX-1GP

SCD1U50V3KX-GP

GAP-CLOSE-PWR
G88
1
2

C557
SC4D7U10V5KX-1GP

GAP-CLOSE-PWR
G58
1
2

SB

GM45

2

1

DCBATOUT_51124

TC30
SE68U25VM-3-GP

2

TC26
ST15U25VDM-3-GP

GAP-CLOSE-PWR
G57
1
2

I/P cap: 10U 25V K1206 X5R/ 78.10622.52L
SB

2

1

DY

2

D

GAP-CLOSE-PWR
G89
1
2

2

GAP-CLOSE-PWR
G49
1
2

Vtrip(mV)=Rtrip(Kohm)*10(uA)
Iocp=(Vtrip/Rdson)+((1/(2*L*f))*((Vin-Vout)*Vout)/Vin))

2

GAP-CLOSE-PWR
G90
1
2

2

1

1D8V_S3
G52

DCBATOUT_51124

1

DCBATOUT

GAP-CLOSE-PWR
G61
1
2
GAP-CLOSE-PWR
G72
1
2
GAP-CLOSE-PWR

A

A

Wistron Corporation

Vout=0.758V*(R1+R2)/R2 --> PWM mode
Vout=0.764V*(R1+R2)/R2 --> Skip Mode

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

TPS51124_1D8V_1D05V
Size
A3

Document Number

Date: Friday, June 20, 2008
5

4

3

2

Rev

SB

Cathedral Peak II
Sheet
1

37

of

43

5

4

3

POWER_MONITOR
G62
1

7

2

G64
1
R415
6236A_VID4
R413
6236A_VID3
R411
6236A_VID2
R408
6236A_VID1
R404
6236A_VID0

R421
1

PM_SLP_S3#

2
0R2J-2-GP

DY
R224
1

DY

2
0R2J-2-GP

2
2
2
2

1D05V_S0

G66
1

GAP-CLOSE-PWR
G87
1
2

0R3-0-U-GP
2

NO GFX

GAP-CLOSE-PWR
G85
1
2

2
10KR2F-2-GP

GFX

19

6236A_PHASE

UGATE

18

6236A_UGATE

BOOT

17

6236A_BOOT
1
2
R401
3D3R3J-L-GP

2
1

1
2

1

2

C525
SCD1U50V3KX-GP

C

GAP-CLOSE-PWR
G44
1
2

Cyntec 7*7*3
DCR=8mohm, Irating=13A
Isat=24A

GFX CORE
Iomax=8.7A
OCP>15A

GAP-CLOSE-PWR
G42
1
2

VGFXCORE

GFX

GAP-CLOSE-PWR

1

GFX

G76
GAP-CLOSE-PWR
2

G73
GAP-CLOSE-PWR
2

Id=7.7A
Qg=8.5~13nC
Rdson=16.5~21mohm
G
S
S
S

2

GFX 10R2F-L-GP

GAP-CLOSE-PWR
G41
1
2

5
6
7
8
U41
SI4812BDY-T1-E3-GP

GFX

1

POWER SB

4
3
2
1
R405
1

GAP-CLOSE-PWR
G43
1
2

2

C540
SCD22U16V3KX-2-GP

2

GAP-CLOSE-PWR
G45
1
2

GFX

1
2
COIL-D82UH-2-GP

1

VCC_GFXCORE
G47
1

D
D
D
D

VDD
16

VSS
15

VIN
14

VSUM
13

2

Id=7A
Qg=8.7~13nC
Rdson=23~30mohm

C536

L17

GFX

R223
1

GFX

GFX

2
10R2F-L-GP

5V_S0

DCBATOUT
B

2

C298
SCD01U25V2KX-3GP

2
0R0402-PAD

1

1

R229
1

2

GFX

1

1
2

GFX

SC2D2U10V3KX-1GP

C530

GFX

1

1

G102 GAP-CLOSE-PWR
1
2

C562

D
D
D
D

5
6
7
8

PHASE

G
S
S
S

20

6236A_LGATE

4
3
2
1

PGND

1

22
21

GFX

GFX

2

25

VID3

VID2
PVCC

SC1U16V3KX-2GP

R422

GFX
SC330P50V2KX-3GP

9 VCC_AXG_SENSE

C299

2

1
2

GFX

C541

C547
1
2

2K55R2F-GP

GFX

SC1KP50V2JN-2GP

C300
SC1KP50V2JN-2GP
B

23

74.06263.073

C564
SC1KP50V2JN-2GP
2

5V_S0

6236A_VDD

6236A_RTN

1

26

6236A_AF_EN

6236A_PMON
27
VID4

28
PMON

29
VR_ON

30

32

9

GFX

SC560P50V2KX-2GP

R26 for Intel GPU/With Load line
R27 for ATI GPU/Without Load
line

VID0

ISL6263ACRZ-T-GP

6236A_VIN

1

6236A_VSEN
2

31

6236A_GOOD
VSEN

VO

VDIFF

8

24

6236A_BOOT_R

7

12

FB

6236A_VDIFF

4K99R2F-L-GP

PGOOD

33

6

C568

6236A_FB_R

GFX R436

FDE

GND_T
COMP

6236A_FB

2
2

5

SC180P50V2JN-1GP

GFX 2K21R3F-L-GP
1

1 R437
2
6K98R3F-GP

GFX

VW

VID1

VGFXCORE

DY
DCBATOUT_6263A

U42
SI4800BDY-T1

LGATE

OCSET

6236A_VSUM

GFX

6236A_COMP

DFB

374KR3-GP
R432
1

GFX

2GFX

3

6236A_VW 4

2
SC1KP50V2JN-2GP

11

GFX
C302
1

6236A_COMP_R

SOFT

6236A_DFB

2

2

6263A_VCC_PRM

GFX

SC68P-GP
R231
1

6236A_SOFT

2

6236A_OCSET

C566 1
2

C569 1

GFX SCD01U50V2KX-1GP

RTN

C301
1

RBIAS

6236A_DROOP 10

6263A_VCC_PRM

1

DROOP

R227
GFX
9K1R3F-1-GP
1
2

6236A_RBIAS

R403
0R0402-PAD
2
1

SC10U25V6KX-1GP

C

SB
GFX

SC10U25V6KX-1GP

U51
R434 GFX
150KR2F-L-GP
1
2

AF_EN

2
0R2J-2-GP

6236A_VR_ON

GFX

R433
1 DY

34,36,37 CPUCORE_ON

GAP-CLOSE-PWR

R431
1
2
1K91R2F-1-GP

3D3V_S0

SB
GM45

TC24
SE68U25VM-3-GP

GAP-CLOSE-PWR
G84
1
2

R225
1

3D3V_S0

D

GAP-CLOSE-PWR
G80
1
2

VCC_GFXCORE

0R3-0-U-GP
2

NO GFX
G68
1

2

GAP-CLOSE-PWR
G82
1
2

0R3-0-U-GP
2

NO GFX

0R0402-PAD
GFX_VID4
1
0R0402-PAD
GFX_VID3
1
0R0402-PAD
GFX_VID2
1
0R0402-PAD
GFX_VID1
1
0R0402-PAD
GFX_VID0
1

2

DCBATOUT
G86

1

NO GFX

GFX

PL on P.7

18,27,30,32,36,37

0R3-0-U-GP
2

1

1

R427
2
1
0R0402-PAD

GFXVR_EN

DCBATOUT_6263A
GFX_VID[4..0]

R417
10KR2J-3-GP

2

2

SCD01U50V2KX-1GP

7

1

GFX

C555
1

D

2

TC20
SE330U2VDM-L-GP

GFX

R419
1KR3F-GP

C552
1

GFX

Panasonic
ERT-J1VR103J

R378
1

2

NTC-10K-9-GP

6236A_VSUM_R

2
4K53R2F-1-GP

R407
1

GFX

1

1
G23
GAP-OPEN-PWR

SCD033U25V3KX-GP

G22
GAP-OPEN-PWR
2

DY

2

7K68R2F-GP

2

R414
1

2

DY

SCD033U25V3KX-GP

GFX

GFX

R226
10R3F-GP

R412
1

2

GFX

2

1

1
R228
10R3F-GP
2

C558
SCD1U25V3KX-GP

C551
1

GFX

2

G100 GAP-CLOSE-PWR
1
2

1

9 VSS_AXG_SENSE

2

GFX

2
3K57R2F-GP

GFX

VSS_AXG_SENSE_OUTCAP
VCC_AXG_SENSE_OUTCAP

A

A

Cathedral Peak II

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

ISL6263A_GFX CORE
Size
C
Date:
5

4

3

2

Document Number

Rev

SB

Cathedral Peak II
Friday, June 20, 2008

Sheet
1

38

of

43

5

4

3

2

1

DCBATOUT
EC108
SCD1U50V3KX-GP

1

U3

2

NEAR

AD+

DY

1
2
3
4

DCBATOUT

R12
100KR2J-1-GP

2

1

1

1
GAP-CLOSE-PWR

2

2

1

POWER SB

D8

K
BQ24745_BST
BQ24745_VDDP

C48
1

A

2

CH520S-30PT-GP SC1U10V3KX-3GP

G
S
S
S

SI4800BDY-T1

4
3
2
1

1
SCD1U50V3KX-GP

2BQ24745_FBO
4K7R2J-2-GP

C82
SC1U10V3KX-3GP

FBO
EAI
EAO
VREF
CE
GND

NC#16

16

VFB

15

BQ24745RHDR-GP

BATT_SENSE

BATT_SENSE 40

C318

1

C325

2

1

C324

2

1

C22

2

1

C24

2

1

G33

B

MAX8731A_CSIP
MAX8731A_CSIN

1

6
BQ24745_EAI
5
BQ24745_EAO
4
BQ24745_VREF
3
BQ24745_CHG_ON 7
12

74.24745.073

C51
SCD1U25V2ZY-1GP

2

1
2
C78
SC56P50V2JN-2GP

C50

2

VICM

GND

C84
R86
SC2200P50V2KX-2GP
7K5R2F-1-GP
2
1BQ24745_EAO_RC2
1

2

C65
SC220P50V2KX-3GP

18
17

29

1

1

R82
1

1

2 BQ24745_FBO_RC
R87
1
2
200KR2F-L-GP

2

C85

B

8

CSOP
CSON

G34

SCD1U50V3KX-GP

SC150P50V2JN-3GP

1

U10

GAP-CLOSE-PWR

CHG_AGND
BQ24745_IINP

NC#14

2

D01R2512F-4-GP

D
D
D
D

24745_LOW_G

BT+_R

2
IND-5D6UH-32-GP

SC10U25V6KX-1GP

19

1

SC10U25V6KX-1GP

PGND

C62
SCD1U50V3KX-GP

SC10U25V6KX-1GP

20

BQ24745_LX1

R256
1

SC10U25V6KX-1GP

LGATE

BT+
L5

2

2

23

SDA

1

GAP-CLOSE-PWR

R76
1
2
0R0402-PAD

1

1

SB

SI4800BDY-T1

24745_HIGH_G

SCL

CHG_AGND
CHG_AGND

C

DY

ACOK

PHASE

14

DY

C58
SCD1U25V2ZY-1GP

2

24

BQ24745_CSSN
TP137

2

UGATE

2

25
21

5
6
7
8

BOOT
VDDP

D
D
D
D

VDDSMB

2

1

1

27
26

ACIN

C349

2

9

CSSN
ICOUT

U9

C61

1

30,40 BAT_SDA

28

C350

2

10

SCD1U25V3KX-GP

1

1

C63
SC1U10V3KX-3GP
30,40 BAT_SCL

CSSP

2

AC_OK

2

1
2

R75
1
2BQ24745_ACOK 13
0R0402-PAD

C66
SCD1U50V3KX-GP

2

4
3
2
1

2
11

3D3V_AUX_S5

DCIN

1

GL40

BQ24745_ACIN

22

1

CHG_AGND

ICREF

1

4

5

2

U12

2

SC10U25V6KX-1GP

2

SCD1U50V3KX-GP
CHG_AGND

BQ24745_DCIN

C81
SCD01U50V2KX-1GP

1 BQ24745_CSSP

SC10U25V6KX-1GP

AC_OK
C

DCBATOUT

C580
C79
2

SC10U25V6KX-1GP

SC1U25V5KX-1GP

6

C54

R267
309KR3F-GP

1

R43
470KR2J-2-GP

2

1

1

A
2

K

GAP-CLOSE-PWR

G2

3

2

1

2

2
1

G1

AD+

AD_IA

D

C320
SCD1U25V2ZY-1GP

D6
1SS4000GPT-GP

Q3
2N7002DW-1-GP

30

8
7
6
5

P2003EVG-GP
AD+

DC_IN_D

R84
49K9R2F-L-GP

D
D
D
D

SB

20080605

R11
49K9R2F-L-GP
AD+_G_1

S
S
S
G

1
2
3
4

AD+

D01R2512F-4-GP
AD+_G_2

R10
10KR2F-2-GP

BT+
U6

R13
1

AD+_TO_SYS

2

P2003EVG-GP

G
S
S
S

S
S
S
G

5
6
7
8

D

D
D
D
D

1

8
7
6
5

R83
1
2
0R0402-PAD

CHG_AGND
CHG_AGND
CHG_AGND

BQ24745_VREF
RN61

3D3V_AUX_S5

1
2
3
4

8
7
6
5

AC_OK
CHG_ON#
AC_IN#
BQ24745_CHG_ON

Q16

A

SRN100KJ-8-GP-U

BQ24745_CHG_ON

3

4

AC_OK

2

5

1

6

Cathedral Peak II
CHG_ON#

CHG_ON#

AC_IN#

1

2

C355
SCD1U10V2KX-4GP

1

DY

30

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

AC_IN# to KBC
Title

2

2N7002DW-1-GP

AC_IN#

C348
SC1U10V3KX-3GP

A

30

BQ24745 Charger
Size
A3

Document Number

Date: Friday, June 20, 2008
5

4

3

2

Rev

SB

Cathedral Peak II
Sheet
1

39

of

43

A

B

AD_JK_IN

DC1

D

E

Adaptor in to generate DCBATOUT

AD+

2

7

AD+_2

D1

1

Q2
R2
B

E
C
R15
100KR2J-1-GP

Q1

30

TP6
TP5

B

C

R1

E
R2
PDTC124EU-1-GP

AD_OFF

2

AFTE30-GP
AFTE30-GP

1
1

4

C8
SC1U50V5ZY-1-GP

PDTA124EU-1-GP
AD_JK_IN
AD_JK_IN

8
7
6
5

1

AD_OFF#_JK

R1

2nd: 20.F1170.005

D
D
D
D

P2003EVG-GP
1

R14
200KR2F-L-GP

U2
S
S
S
G

2

2

P6SBMJ24APT-GP

2

1

C1
SCD1U50V3ZY-GP

A

20.F1002.005

1

6
ACES-CON5-7-GP-U1

1
2
3
4

K

2
1

DY

1

AD_JK

D30
S10P40PT-GP-U
3

EC6
SCD1U50V3KX-GP

5
4
3
2
4

C

3

3

BATTERY CONNECTOR

BATA_SDA_1
BATA_SCL_1
BAT_IN#_1
BT+
BT+

D3
BAV99PT-GP-U

D4
BAV99PT-GP-U

DY

DY

2

1

2

1

2

1

3D3V_AUX_S5

D5
BAV99PT-GP-U

1
1
1
1
1

AFTE30-GP
AFTE30-GP
AFTE30-GP
AFTE30-GP
AFTE30-GP

TP11
TP10
TP9
TP8
TP7

BAT1

DY
9
8
7
6
5
4
3
2
1

3

3

2

3

2

RN42
1
2
3
4

30,39 BAT_SDA
30,39 BAT_SCL

BATA_SDA_1
BATA_SCL_1
BAT_IN#_1

2

EC102

1

EC98

DY

2

1

1
2

1
2

2

K
A

SB

1

EC101

DY

SC10P50V2JN-4GP

EC103
SCD1U50V3ZY-GP

SC1000P50V3JN-GP

EC104
SCD1U50V3ZY-GP
D29
MMPZ5232BPT-GP

SC1000P50V3JN-GP

-1

SC10P50V2JN-4GP

1

EC99

DY

2

BAT_IN#

1

SRN33J-7-GP

BT+
30

8
7
6
5

GND
GND
GND
GND
DAT
CLK
BAT_IN
BT+2
BT+1
ALP-CON7-9-GP

20.81094.007

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

39 BATT_SENSE

R257
1
2
0R0402-PAD

Title

AD/BATT CONN

Size

Document Number

Rev

SB

Cathedral Peak II
Date: Friday, June 20, 2008
A

B

C

D

Sheet

40

of
E

43

1

5

4

1

1

1

1

1

1

1

1

1

1

1

11
U32D

7

U32C

7

H22
HOLE

1

12

1

1
8

1

13

14

9

2

H2
H3
H4
H5
H6
H7
H8
H10
H11
H12
H13
H14
H15
PAD-1P-3-GP PAD-1P-3-GP PAD-1P-3-GP PAD-1P-3-GP PAD-1P-3-GP PAD-1P-3-GP PAD-1P-3-GP PAD-1P-3-GP PAD-1P-3-GP PAD-1P-3-GP PAD-1P-3-GP PAD-1P-3-GP PAD-1P-3-GP

5V_S0

10

14

5V_S0

3

TSAHCT125PW-GP

TSAHCT125PW-GP

SB
D

D

1

GM45

EC111

DY

1

EC100

DY

2

DY

1

1

EC91

2

DY

2

1

EC88

DY

2

EC117

DY

2

1

EC112

DY

2

1

EC71

2

1
2

1
2

1

1
2

DY

EC116
SCD1U25V2ZY-1GP

2

EC69

DY

SCD1U25V2ZY-1GP

2

1

1

EC53

SCD1U25V2ZY-1GP

DY

SCD1U25V2ZY-1GP

2

1

EC50

DY

SCD1U25V2ZY-1GP

2

EC20

SCD1U25V2ZY-1GP

DY

SCD1U25V2ZY-1GP

2

1

1

EC119

3D3V_LAN_S5

1

2

1

1
2

2

2

1

1

TC34

SCD1U25V2ZY-1GP

C

DY

EC176

1

EC174

DY

2

2

DY

1

EC173

2

1

1

EC138

2

1

DY

2

1

EC156

2

1
2

1
2

1
2

1
2

1

EC95

DY

2

2

1

EC105

DY

2

1
2

1
2

EC125

1

1
2

1
2

1

1
2
1
2

1

1
2

DY

EC70

EC179

EC97
SCD1U25V2ZY-1GP

2

1

EC67

SCD1U25V2ZY-1GP

DY

DY

SB

SCD1U25V2ZY-1GP

2

1

EC139

SCD1U25V2ZY-1GP

DY

SCD1U25V2ZY-1GP

2

1

EC83

DY

SCD1U25V2ZY-1GP

2

1

EC81

SCD1U25V2ZY-1GP

DY

SCD1U25V2ZY-1GP

2

EC85
SCD1U25V2ZY-1GP

SCD1U25V2ZY-1GP

DY

EC165

SCD1U25V2ZY-1GP

EC82

DY

DY

SCD1U25V2ZY-1GP

EC72
SCD1U25V2ZY-1GP

SCD1U25V2ZY-1GP

DY

EC136

SCD1U25V2ZY-1GP

EC66

DY

DY

SCD1U25V2ZY-1GP

EC49

EC147

DY

SCD1U25V2ZY-1GP

2

1

EC62

DY

SCD1U25V2ZY-1GP

2

1

EC77

SCD1U25V2ZY-1GP

DY

SCD1U25V2ZY-1GP

2

1

EC65

SCD1U25V2ZY-1GP

DY

SCD1U25V2ZY-1GP

2

1

EC118

DY

SCD1U25V2ZY-1GP

2

1

EC73

SCD1U25V2ZY-1GP

DY

SCD1U25V2ZY-1GP

2

B

BOTTOM
GND12
SPRING-7

GND14
SPRING-12-GP-U

34.49U26.001

34.49U26.001

34.41Y19.001

DY

DY

DY

DY

DY

DY

DY

1

GND11
SPRING-7

34.39S07.001

1

GND10
SPRING-23-GP

34.41Y19.001

1

GND8
SPRING-12-GP-U

34.49U26.001

1

GND7
SPRING-7

34.43G01.002

1

GND4
SPRING-48-GP

34.41Y19.001

1

GND3
SPRING-12-GP-U

34.4B542.001

1

GND2
SPRING-36-GP

1

1

GM45

SCD1U25V2ZY-1GP

EC61

SCD1U25V2ZY-1GP

DY

SCD1U25V2ZY-1GP

DY

SCD1U25V2ZY-1GP

2

TC33

SCD1U25V2ZY-1GP

EC74
SCD1U25V2ZY-1GP

1

GM45

SCD1U25V2ZY-1GP

EC163
SCD1U25V2ZY-1GP

SCD1U25V2ZY-1GP

DY

BT+

SCD1U25V2ZY-1GP

2

EC126

SCD1U25V2ZY-1GP

DY

SCD1U25V2ZY-1GP

DY

SCD1U25V2ZY-1GP

EC68

DY

TOP

1

EC54
SCD1U25V2ZY-1GP

EC151
SCD1U25V2ZY-1GP

B

TC32

1D8V_S3

5V_S5

DY

SCD1U25V2ZY-1GP

5V_S0

DY

GM45

1D2V_LAN_S5

EC148

DY

2

1

EC158
SCD1U25V2ZY-1GP

DY

2

1

EC169
SCD1U25V2ZY-1GP

SCD1U25V2ZY-1GP

DY

2

1

EC168

DY

2

1

EC170
SCD1U25V2ZY-1GP

DY

2

1

EC172
SCD1U25V2ZY-1GP

DY

2

1

EC155

DY

2

1

EC150

SCD1U25V2ZY-1GP

DY

SCD1U25V2ZY-1GP

SCD1U25V2ZY-1GP

SCD1U25V2ZY-1GP

2

EC18

DY

2

1

EC9

C

TC31

1D05V_S0

2

1

3D3V_S0

DY

EC133

DY

2

1
2

1

EC192

SE100U25VM-L1-GP

DY

SE100U25VM-L1-GP

2

1

EC191

SE100U25VM-L1-GP

DY

SE100U25VM-L1-GP

2

1

EC190

DCBATOUT

SCD1U25V2ZY-1GP

DY

SCD1U25V2ZY-1GP

2

1

EC7

DY

SCD1U25V2ZY-1GP

2

1

EC10

SCD1U25V2ZY-1GP

DY

SCD1U25V2ZY-1GP

2

EC94

SCD1U25V2ZY-1GP

DY

2

1

EC63

DY

SCD1U25V2ZY-1GP

2

EC75

SCD1U25V2ZY-1GP

DY

SCD1U25V2ZY-1GP

SCD1U25V2ZY-1GP

SCD1U25V2ZY-1GP

2

EC76

DY

1

EC89

2

1

VCC_GFXCORE

1

DCBATOUT

DY

Check test point
SA
H18
HOLE

H19
HOLE

H20
HOLE

H21
HOLE

H1
HOLE

H16
HOLE

SB

-1

34.4G502.001

1

34.4G502.001

1

1

34.42Y01.011

1

34.42Y01.011

1

1

34.42Y01.011

1

34.42Y01.011

34.42Y01.011

MDC

TP179

AFTE30-GP

TP180

3D3V_S5

1

AFTE30-GP

TP181

5V_S5

1

AFTE30-GP

TP182

1

AFTE30-GP

TP183

1

AFTE30-GP

TP184

1

AFTE30-GP

TP185

18,30 PM_PWRBTN#
4,17,32

H_PWRGD

30,32,35 S5_ENABLE
4,6

NB

AFTE30-GP

1

3D3V_AUX_S5

A

CPU

1

3D3V_S0

H17
HOLE

MINIC1

H_CPURST#

AFTE30-GP

1

Test Point放在Dimm Door打開可量測處

TP186

A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size

EMI/Spring/Boss

Document Number

Date: Friday, June 20, 2008
5

4

3

2

Rev

SB

Cathedral Peak II
Sheet
1

41

of

43

5

D

C

4

SA to SB
1.No Power.
change KBC to BO (71.03310.A0G)
2.XD Card function fail
Cut CARD1 pin27. connect to R400 pin2
3.leakage
GFX power VDD connect to S0
4.Gain=8db.1.83W R137=16K.R138=30K
5.Int_MIC voice to small
add VREF C577=4.7U
6.Realtek Audio report
change R327=68 ohm.R333=68 ohm.merge to RN68
7.SIV reset
R140=300,R55=100.C44=100p,R398=0,R369=100.C502=100p,R85=300,R162=100.C210=100p,R392=0,
8.SIV Azalia
DY C542
BITCLK rise and fall time fail RN10 change to R453=22ohm(MDC).R452=0ohm(codec)
9.add MINICard power option for customer ask
R454.R455
10.interfere HDD
C390.C401.C419. change 0603 4.7U
11.power team
R38=12K.R47=2.74K .R361=110K.R221=100K.R237=10.7K .R424=20K.R420=17.8K .R227=10.5K
R48=10K.R29=2.2 .R37=2.2 .R401=3.3 .C49=0.1u.add R456.add C580.D8=83.R0203.08F .
TC11 change to 77.C2271.00L
TC9 change to 77.E9071.001 (power ripple)
add R458=1K.R459=1k.R460
12.Oscillation
C30=15p.C23=15P.C537=27p.C538=22p
13.audio S3.S4 resume bobo sound
R143 DY. R187 0ohm pad
14.AC mode have hight frequency noise
R390 DY.R389 0ohm pad
15.ESD issue
BAT_IN# series 33 ohm
RN42 change to 8p4r
add R457.D27.D28.D29.U55.U56.C578.R457.
16.noise
DY C523.TC25 change to 77.C1561.01L
20.LED brightness
R2.R1.R4.R5.R451.R450.R449.R448=56
EMI
1.EC23 ~~EC48.EC134.EC135.EC167.EC121.EC122.EC123.
2.EC89.EC12.EC8.EC119.EC156.EC173.
3.EC174~~~EC179.
4.GND13.GND14.

B

3

2

1

05/05
Page16: merge LAUNCHCN1 LEDCN1 to LAUNCHCN1 15pins
Page15: change CRT1 from 20.20717.015 to 20.20378.015
Page26: change RJ1 from 22.10277.011 to 22.10245.E91
D

Page23: change BLUE1 from 20.D0197.004 to 20.F0984.004
Page24: change CARD1 from 20.I0081.001 to 20.I0067.001
Page21: change FAN1 from 20.F0714.003 to 20.F1000.003
Page27: change MINIC1 from 20.F1049.052 to 62.10043.331
Page30: change TPAD1 from 20.K0286.012 to 20.K0174.012
Page34: change U29 U30 from 84.07686.037 to 84.12003.A37 and change U7 U11 U28
U31 from 84.04634.037 to 84.57N03.A37
Page16: delete LED1 LED2 R1 R2 R4 R5

C

05/07
Page17: change RTC1 from 62.70001.011 to 20.F0700.003
Page41: delete EC51
Page10: delete C159
Page25: change U13 from 72.24256.R01 to 72.24C08.J01

Merge
1.R313.R314.R315.R319.R320.R149. change to RN59
2.RN6.RN46. change to RN6
3.R341.R343.R344 change to RN46
4.R385 change to 100K merge R382 to RN56
5.RN53.RN56. change to RN53
6.Q20.Q21 change to Q21. Q21.Q23 change to Q21.
7.R367.R368 change to RN60
8.Q16.Q17 change to Q16
9.R262.R264.R268.R277 change to RN61
10.R205.R204.R206 change to RN62
11.RN33.R215 change to RN33
12.R209.R210.R348 change to RN63
13.R280=10K.merge R269 to RN64
14.R109.R112.R111.R290 change to RN65
15.R325.R323 change to RN66
16.R304.R307 change to RN67
17.U14 change to 73.01G08.L04 .add C579
18.R51.R399 vhange to RN69.

05/08
Page30: change KB1 from 20.K0127.026 to 20.K0204.026
B

Page26: delete RN36 RN37 RN38 RN39
Page23: change TC28 from 80.15715.34L to 77.C1071.081
Page26: change TC15 from 80.15715.34L to 80.15715.12L
Page23: delete R244 R245 R246 R247 R248 R249 R250 R251

0 Ohm change to PAD
R427.R403.R415.R413.R411.R408.R404.R146.R197.R157.R153.R353.R352.R358.R357.R310.R196.R346.R342.R351.
R191.R203.L14.R212.R350.R179.R217.R6.R7.R242.R294.R278.R279.R292.R293.R232.R233.R410.R393.
R416.R250.R251.R248.R249.R246.R247.R244.R245.R129.R127.R376.ER2.R383.R28.R16.R19.R20.R21.
R22.R23.R24.R25.R57.R58.R365.R164.

Page24: change CARD1 from 20.0067.001 to 20.I0079.001
05/09
Page41: delete GND13
05/12
Page24: add EC127 EC128 EC185 EC186

A

A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Page35: change TC27 from 77.C1561.01L to
77.C1561.03L

Title
Size

Page40: change BAT1 from 20.80697.007 to
20.80906.007
5

4

3

2

Change List

Document Number

Rev

SB

Cathedral Peak II
Date: Friday, June 20, 2008

Sheet
1

42

of

43

5

4

05/013
Page16: change pin1 pin2 of LED6 from 3D3V_S5 to 3D3V_AUX_S5

3

2

1

06/13
Page37: change R446 R447 from 0ohm pad to 0ohm resistor
Page26: change XF1 from 68.69241.301 to 68.89240.30A

05/014
Page17: add EC187 EC188

06/17
Page39: C320 mount

D

Page16: add EC189 TP189~TP195
Page30: change TPAD1 from 20.K0174.012 to 20.K0228.012

D

Page40: EC104 mount
Page41: EC95 mount

Page41: add EC190~EC195

Page39: change R11 from 10K to 49K9

C

05/015
Page17: change U15 pin13 pin14 from pull high 3D3V_S0 to VGATE_PWRGD

Page34: change C49 from 47nF to 22nF and change R47 from 2.74K to 1.74K

Page17: change Q11 G from 3D3V_S0 to VGATE_PWRGD

Page37: add C581 C582

Page40: change D1 from 83.P4SSM.BAM to 83.P6SBM.AAG

Page41: delete GND6

SB
05/015
Page30: change KBC_GPIO0C from pull-high 3D3V_AUX_S5 with 10K to
pull-low GND with 1K

06/20
Page25: change C30 from 15p to 12p

C

06/06
Page3: change C176 C177 from 78.27034.1FL (27p) to 78.33034.1FL (33p)
Page22: delete D15
Page29: change R127 R129 from 0ohm pad to 12K 1K5 and change R137
R138 from 16K 30K to 13K 20K
Page34: change TC1 from 77.C1561.01L (15u) to 79.10712.L02 (100u) and
C14 C37 C38 C319 dummy
B

B

Page35: change TC25 from 77.C1561.01L (15u) to 79.68612.30L (68u)
and change C292 to dummy
Page37: add TC30 79.68612.30L (68u) and change C553 C563 to dummy
Page38: change C536 to dummy and change TC24 from 77.C1561.01L (15u)
to 79.68612.30L (68u)
Page39: change C61 to dummy
Page41: add TC31 TC32 TC33 TC34 and delete GND9

A

06/09
Page16: add LED3 R458 R465

A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

06/11
Page30: change R379 from 10K to 1K

Title
Size

06/13
Page3: add EC59 DY
5

Change List

Document Number

Rev

SB

Cathedral Peak II
Date: Friday, June 20, 2008
4

3

2

Sheet
1

43

of

43

www.s-manuals.com



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Creator                         : 
Title                           : Wistron Cathedral Peak II - Schematics. www.s-manuals.com.
Subject                         : Wistron Cathedral Peak II - Schematics. www.s-manuals.com.
Document ID                     : uuid:3D7909ED-1A9F-0619-4918-0A0720FB2FF3
Instance ID                     : uuid:78e070e4-77a7-411d-b335-ffa932af479b
Page Count                      : 44
Keywords                        : Wistron, Cathedral, Peak, II, -, Schematics., www.s-manuals.com.

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