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5

4

3

2

1

DQDN15 AMD QUEEN M12
Muxless /UMA Schematics Document

D

D

AMD LIANO APU FS1
AMD GPU Seymour XT
FCH HUDSON M3
PCB 10246-1
2011-05-28
REV : A00

C

C

B

B

DY :None Installed
UMA_PX:UMA and Muxless platform installed
DIS_PX:DIS and Muxless platform installed
PX:Muxless platform installed
FCH_UMA_PX:UMA_PX CRT FCH output
Whistler: For 8 X Vram
DN15: For DN15
DQ15 AMD DIS SAMSUNG TI
A

A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

Cover Page

Size
Document Number
Custom

DQDN15 AMD QUEEN M12

Date:
5

4

3

2

Friday, May 27, 2011

Sheet

1
1

of

Rev

X00
104

5

:
:
:
:

3

91.4IE01.001
48.4IE04.0SA
10246-SB
SB

DDRIII DIMM2
800/1066/1333

DDRIII 1333

AMD
Liano APU

PCIe

PCIe & USB2.0

WLAN
USB3.0 x2

USB3.0 & 2.0 x2

C

MIC IN

DCBATOUT

83, 84, 85, 86, 87

DP1

LCD

9

49

DCBATOUT

FCH
HUDSON-M3

TPS51116RGER
INPUTS
OUTPUTS

Integrated Display DAC
USB2.0 X1

USB 3.0 (4parts)

29

USB 2.0 (10 parts)

DCBATOUT 0D75V_S0

USB2.0

APU VDDR/VDDP
RT8209
INPUTS

INT RTC

CardReader
USB2.0 X4

Realtek
RTS5138

32

LPC Bus

PCIe & USB2.0

OUTPUTS 33

DCBATOUT

1D1V_S5

RT8208B
INPUTS

49
17, 18, 19, 20, 21, 22

46

92

26

OUTPUTS

B

DCBATOUT VGA_CORE_PWR

PCB LAYER
L1:
L2:
L3:
L4:
L5:
L6:

SATA

SATA

63

SATA

USB3.0/2.0

Bluetooth

Touch Panel
63

eSATA
USB3.0
Cbmbo
57

A

RT8209
INPUTS

AMD GPU CORE

Camera Conn

USB2.0 X 1

46

OUTPUTS

AMD FCH CORE Power

SD/SDIO/MMC
MS/MS Pro/xD

(LVDS & Camera Conn.)

DN15 Vostro 64
Fingerprinter

44

DCBATOUT 1D2V_S0

ACPI 1.1
75

TPS51116RGER
INPUTS
OUTPUTS

SATA (6 parts)

HW MONITOR

DN15 Vostro
Express Card

C

DDRIII VTT

CRT

82

USB 1.1 (2 parts)

INT CLK GEN

2CH SPEAKER

44

DCBATOUT 1D5V_S3

Integrated Display DAC

AZALIA

APU_VDD
APU_VDDNB

DDRIII SUS
Reserve GPU CRT for VRAM verification

USB3.0 X 2

Azalia

3D3V_AUX_S5
5V_AUX_S5
5V_S5
3D3V_S5

42, 43
ISL6267HRTZ-T
31
INPUTS
OUTPUTS

Reserve for HDMI v1.4

For FCH CRT Input

USB2.0 X 3

HDD
56

ODD

SPI

56

Top
VCC
Signal
Signal
GND
Bottom

KBC

NUVOTON

27

NPCE795P

Flash ROM
2MB 60

Touch
PAD
69

Int.
KB
69

Thermal

FAN

ENE P2800

G991P11U

28

A

DQ15 AMD DIS SAMSUNG TI

28

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

25

28
25

Title
Size

Block Diagram
Document Number

Custom

Rev

QUEEN AMD Muxless/UMA

Date: Thursday, May 26, 2011
5

4

D

APU Core/NB Power

HDMI 51

TRAVIS
ANX3110

UMI Link 4X4

USB3.0
Redriver x2

41

27

DP0

4, 5, 6, 7, 8

82

B

Seymour-XT
UMA HDMI(Share PCIe x 4)

722-Pin uFCPGA722

CODEC & OP AMP
IDT 92HD87

58

BT+

TPS51123
INPUTS
OUTPUTS 30

AMD Graphic

PCIeX16

(FS1 socket)

PCIeX1

HP1

Muxless (Share PCIe x 8)

DCBATOUT

SYSTEM DC/DC

90, 91

DDRIII 1333

40

OUTPUTS
28,29

AD+

VRAM
64Mx16bx4 (512MB)

DDRIII DIMM1
800/1066/1333

I/O Board Connector

Realtek RTL8105E

BQ24745
INPUTS

DQDN15 QUEEN AMD M12 UMA/Muxless DIS 15'

15

LAN Controller

1

CHARGER

14

RJ45
CONN

2

CRT Board
Connector

D

Project code
Part Number
PCB P/N
Revision

4

3

2

Sheet
1

2

of

X00
104

5

4

3

2

1

D

D

Strapping

No Fusion Config, Strap Not needed, but reserve

REQUIRED SYSTEM STRAPS
EC_PWM2
PCH GPO199

PULL
HIGH

LPC ROM

PULL
LOW

SPI ROM

PCI_CLK1

RTC_CLK

CLK_PCI_LPC

PCI_CLK4

LPC_CLK0

Allow
PCIE GEN2

S5_PLUS Mode
DISABLE

USE
DEBUG STRAPS

non_Fusion
CLOCK mode

ENABLE EC

IGNORE
DEBUG STRAPS

Fusion
CLOCK mode

DISABLE EC

DEFAULT

C

Force
PCIE GEN1

DEFAULT

DEFAULT

DEFAULT

USB Table

DEFAULT

B

USB Debug Port / CRT USB 2.0

1

Mini Card (WLAN)

2

Fingerprint

3

WWAN

4

Bluetooth

5

Touch Panel

6

eSATA/USB Charger

7

CCD Camera

8

New Card

9

CardReader
USB 3.0 port 1

11

USB 3.0 port 2

12

USB 3.0 port 3

13

USB 3.0 port 4

CLKGEN
DISABLED

C

(Use External)

APU

Device

0

10

DEFAULT

PCIe Routing

USB
Pair

CLKGEN
ENABLED
(Use Internal)

DEFAULT

S5_PLUS Mode
ENABLE

LPC_CLK1

LANE0

LAN

LANE1

WWAN

LANE2

WLAN

LANE3

CardReader

B

FCH
LANE0
LANE1

Express Card

LANE2
LANE3

DQ15 AMD DIS SAMSUNG TI

A

A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

5

4

3

2

Table of Content

Size
A3

Document Number

Date:

Thursday, May 26, 2011

Rev

QUEEN AMD Muxless/UMA
Sheet
1

3

of

X00
104

5

4

3

APU1F

C

AC5
AC6
AC8
AC9
AB7
AB8
AA5
AA6

82 PCIE_RXP0
82 PCIE_RXN0

LAN
WWAN

82 PCIE_RXP2
82 PCIE_RXN2

WLAN

17
17
17
17
17
17
17
17

AF8
AF7
AE6
AE5
AE9
AE8
AD8
AD7

UMI_FCH_APU_RX0P
UMI_FCH_APU_RX0N
UMI_FCH_APU_RX1P
UMI_FCH_APU_RX1N
UMI_FCH_APU_RX2P
UMI_FCH_APU_RX2N
UMI_FCH_APU_RX3P
UMI_FCH_APU_RX3N
1 R402

2196R2F-GP P_ZVDDP

K5

P_UMI_RXP0
P_UMI_RXN0
P_UMI_RXP1
P_UMI_RXN1
P_UMI_RXP2
P_UMI_RXN2
P_UMI_RXP3
P_UMI_RXN3
P_ZVDDP

SAINE

P_GFX_TXP0
P_GFX_TXN0
P_GFX_TXP1
P_GFX_TXN1
P_GFX_TXP2
P_GFX_TXN2
P_GFX_TXP3
P_GFX_TXN3
P_GFX_TXP4
P_GFX_TXN4
P_GFX_TXP5
P_GFX_TXN5
P_GFX_TXP6
P_GFX_TXN6
P_GFX_TXP7
P_GFX_TXN7
P_GFX_TXP8
P_GFX_TXN8
P_GFX_TXP9
P_GFX_TXN9
P_GFX_TXP10
P_GFX_TXN10
P_GFX_TXP11
P_GFX_TXN11
P_GFX_TXP12
P_GFX_TXN12
P_GFX_TXP13
P_GFX_TXN13
P_GFX_TXP14
P_GFX_TXN14
P_GFX_TXP15
P_GFX_TXN15
P_GPP_TXP0
P_GPP_TXN0
P_GPP_TXP1
P_GPP_TXN1
P_GPP_TXP2
P_GPP_TXN2
P_GPP_TXP3
P_GPP_TXN3
P_UMI_TXP0
P_UMI_TXN0
P_UMI_TXP1
P_UMI_TXN1
P_UMI_TXP2
P_UMI_TXN2
P_UMI_TXP3
P_UMI_TXN3
P_ZVSS

AA2
AA3
Y2
Y1
Y4
Y5
W2
W3
V2
V1
V4
V5
U2
U3
T2
T1
T4
T5
R2
R3
P2
P1
P4
P5
N2
N3
M2
M1
M4
M5
L2
L3

APU_HDMI_DATA2 51
APU_HDMI_DATA2# 51
APU_HDMI_DATA1 51
APU_HDMI_DATA1# 51
APU_HDMI_DATA0 51
APU_HDMI_DATA0# 51
APU_HDMI_CLK 51
APU_HDMI_CLK# 51

GTXP8
GTXN8
GTXP9
GTXN9
GTXP10
GTXN10
GTXP11
GTXN11
GTXP12
GTXN12
GTXP13
GTXN13
GTXP14
GTXN14
GTXP15
GTXN15

DIS_PX
DIS_PX
DIS_PX
DIS_PX
DIS_PX
DIS_PX
DIS_PX
DIS_PX
DIS_PX
DIS_PX
DIS_PX
DIS_PX
DIS_PX
DIS_PX
DIS_PX
DIS_PX

C417
C418
C419
C420
C421
C422
C423
C424
C425
C426
C427
C428
C429
C430
C431
C432

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2

SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP

PEG_TXP8
PEG_TXN8
PEG_TXP9
PEG_TXN9
PEG_TXP10
PEG_TXN10
PEG_TXP11
PEG_TXN11
PEG_TXP12
PEG_TXN12
PEG_TXP13
PEG_TXN13
PEG_TXP14
PEG_TXN14
PEG_TXP15
PEG_TXN15

PEG_TXP[8..15]
PEG_TXN[8..15]

PEG_RXP[8..15]
PEG_RXN[8..15]

PCIE_TXP0_C
PCIE_TXN0_C

C441 1
C442 1

2 SCD1U16V2KX-3GP
2 SCD1U16V2KX-3GP

PCIE_TXP0
PCIE_TXN0

82
82

PCIE_TXP2_C
PCIE_TXN2_C

C457 1
C460 1

2 SCD1U16V2KX-3GP
2 SCD1U16V2KX-3GP

PCIE_TXP2
PCIE_TXN2

82
82

AF1
AF2
AF5
AF4
AE3
AE2
AD1
AD2

UMI_TX0P_C
UMI_TX0N_C
UMI_TX1P_C
UMI_TX1N_C
UMI_TX2P_C
UMI_TX2N_C
UMI_TX3P_C
UMI_TX3N_C

C445
C446
C447
C448
C449
C450
C451
C452

2
2
2
2
2
2
2
2

K4

P_ZVSS

SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP

PEG_TXP[8..15]

83

PEG_TXN[8..15]

83

PEG_RXP[8..15]

83

PEG_RXN[8..15]

83

C

AD4
AD5
AC2
AC3
AB2
AB1
AB4
AB5

1
1
1
1
1
1
1
1

D

LAN
WWAN

UMI_APU_FCH_TX0P
UMI_APU_FCH_TX0N
UMI_APU_FCH_TX1P
UMI_APU_FCH_TX1N
UMI_APU_FCH_TX2P
UMI_APU_FCH_TX2N
UMI_APU_FCH_TX3P
UMI_APU_FCH_TX3N

WLAN

17
17
17
17
17
17
17
17

1

1D2V_S0

P_GPP_RXP0
P_GPP_RXN0
P_GPP_RXP1
P_GPP_RXN1
P_GPP_RXP2
P_GPP_RXN2
P_GPP_RXP3
P_GPP_RXN3

GRAPHICS

PEG_RXP8
PEG_RXN8
PEG_RXP9
PEG_RXN9
PEG_RXP10
PEG_RXN10
PEG_RXP11
PEG_RXN11
PEG_RXP12
PEG_RXN12
PEG_RXP13
PEG_RXN13
PEG_RXP14
PEG_RXN14
PEG_RXP15
PEG_RXN15

GPP

D

1

6 OF 6
PCI EXPRESS

P_GFX_RXP0
P_GFX_RXN0
P_GFX_RXP1
P_GFX_RXN1
P_GFX_RXP2
P_GFX_RXN2
P_GFX_RXP3
P_GFX_RXN3
P_GFX_RXP4
P_GFX_RXN4
P_GFX_RXP5
P_GFX_RXN5
P_GFX_RXP6
P_GFX_RXN6
P_GFX_RXP7
P_GFX_RXN7
P_GFX_RXP8
P_GFX_RXN8
P_GFX_RXP9
P_GFX_RXN9
P_GFX_RXP10
P_GFX_RXN10
P_GFX_RXP11
P_GFX_RXN11
P_GFX_RXP12
P_GFX_RXN12
P_GFX_RXP13
P_GFX_RXN13
P_GFX_RXP14
P_GFX_RXN14
P_GFX_RXP15
P_GFX_RXN15

UMI-LINK

AA8
AA9
Y7
Y8
W5
W6
W8
W9
V7
V8
U5
U6
U8
U9
T7
T8
R5
R6
R8
R9
P7
P8
N5
N6
N8
N9
M7
M8
L5
L6
L8
L9

2

SAINE

2

R401
196R2F-GP

B

B

DQ15 AMD DIS SAMSUNG TI

A

A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

5

4

3

2

Size
A3

Document Number

Date:

Thursday, May 26, 2011

APU_PCIE(1/5)

Rev

QUEEN AMD Muxless/UMAX00
Sheet
1

4

of

104

5

4

APU1A

C

14 M_A_BS0
14 M_A_BS1
14 M_A_BS2

U24
U21
L23

14
14
14
14
14
14
14
14

M_A_DM0
M_A_DM1
M_A_DM2
M_A_DM3
M_A_DM4
M_A_DM5
M_A_DM6
M_A_DM7

E14
J17
E21
F25
AD27
AC23
AD19
AC15

14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14

M_A_DQS0
M_A_DQS#0
M_A_DQS1
M_A_DQS#1
M_A_DQS2
M_A_DQS#2
M_A_DQS3
M_A_DQS#3
M_A_DQS4
M_A_DQS#4
M_A_DQS5
M_A_DQS#5
M_A_DQS6
M_A_DQS#6
M_A_DQS7
M_A_DQS#7

G14
H14
G18
H18
J21
H21
E27
E26
AE26
AD26
AB22
AA22
AB18
AA18
AA14
AA15
T21
T22
R23
R24

14 M_A_DIM0_CLK_DDR0
14 M_A_DIM0_CLK_DDR#0
14 M_A_DIM0_CLK_DDR1
14 M_A_DIM0_CLK_DDR#1
14 M_A_DIM0_CKE0
14 M_A_DIM0_CKE1

H28
H27

14 M_A_DIM0_ODT0
14 M_A_DIM0_ODT1

Y25
AA27

14 M_A_DIM0_CS#0
14 M_A_DIM0_CS#1

V22
AA26

B

V21
W24
W23

14 M_A_RAS#
14 M_A_CAS#
14 M_A_WE#
14 M_A_RST#

M_A_EVENT#

H25
T24

M_VREF_DQ_APU

W20

1 R501
2
39R2F-GP

1D5V_S3

M_ZVDDIO

W21

2

1

1 OF 6
APU1B

MEMORY CHANNEL
A

MA_ADD0
MA_ADD1
MA_ADD2
MA_ADD3
MA_ADD4
MA_ADD5
MA_ADD6
MA_ADD7
MA_ADD8
MA_ADD9
MA_ADD10
MA_ADD11
MA_ADD12
MA_ADD13
MA_ADD14
MA_ADD15

MA_DATA0
MA_DATA1
MA_DATA2
MA_DATA3
MA_DATA4
MA_DATA5
MA_DATA6
MA_DATA7
MA_DATA8
MA_DATA9
MA_DATA10
MA_DATA11
MA_DATA12
MA_DATA13
MA_DATA14
MA_DATA15

MA_BANK0
MA_BANK1
MA_BANK2

MA_DATA16
MA_DATA17
MA_DATA18
MA_DATA19
MA_DATA20
MA_DATA21
MA_DATA22
MA_DATA23

MA_DM0
MA_DM1
MA_DM2
MA_DM3
MA_DM4
MA_DM5
MA_DM6
MA_DM7

MA_DATA24
MA_DATA25
MA_DATA26
MA_DATA27
MA_DATA28
MA_DATA29
MA_DATA30
MA_DATA31

MA_DQS_H0
MA_DQS_L0
MA_DQS_H1
MA_DQS_L1
MA_DQS_H2
MA_DQS_L2
MA_DQS_H3
MA_DQS_L3
MA_DQS_H4
MA_DQS_L4
MA_DQS_H5
MA_DQS_L5
MA_DQS_H6
MA_DQS_L6
MA_DQS_H7
MA_DQS_L7

MA_DATA32
MA_DATA33
MA_DATA34
MA_DATA35
MA_DATA36
MA_DATA37
MA_DATA38
MA_DATA39
MA_DATA40
MA_DATA41
MA_DATA42
MA_DATA43
MA_DATA44
MA_DATA45
MA_DATA46
MA_DATA47

MA_CLK_H0
MA_CLK_L0
MA_CLK_H1
MA_CLK_L1
MA_CKE0
MA_CKE1

MA_DATA48
MA_DATA49
MA_DATA50
MA_DATA51
MA_DATA52
MA_DATA53
MA_DATA54
MA_DATA55

MA_ODT0
MA_ODT1
MA_CS#0
MA_CS#1
MA_RAS#
MA_CAS#
MA_WE#

MA_DATA56
MA_DATA57
MA_DATA58
MA_DATA59
MA_DATA60
MA_DATA61
MA_DATA62
MA_DATA63

MA_RESET#
MA_EVENT#
M_VREF
M_ZVDDIO

E13
J13
H15
J15
H13
F13
F15
E15

M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7

14
14
14
14
14
14
14
14

H17
F17
E19
J19
G16
H16
H19
F19

M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15

14
14
14
14
14
14
14
14

H20
F21
J23
H23
G20
E20
G22
H22

M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23

14
14
14
14
14
14
14
14

G24
E25
G27
G26
F23
H24
E28
F27

M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31

14
14
14
14
14
14
14
14

AB28
AC27
AD25
AA24
AE28
AD28
AB26
AC25

M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39

14
14
14
14
14
14
14
14

Y23
AA23
Y21
AA20
AB24
AD24
AA21
AC21

M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47

14
14
14
14
14
14
14
14

AA19
AC19
AC17
AA17
AB20
Y19
AD18
AD17

M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55

14
14
14
14
14
14
14
14

AA16
Y15
AA13
AC13
Y17
AB16
AB14
Y13

M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63

14
14
14
14
14
14
14
14

2 OF 6
MEMORY CHANNEL B

M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
M_B_A14
M_B_A15

T27
P24
P25
N27
N26
M28
M27
M24
M25
L26
U26
L27
K27
W26
K25
K24

15 M_B_BS0
15 M_B_BS1
15 M_B_BS2

U27
T28
K28

15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15

15
15
15
15
15
15
15
15

M_B_DM0
M_B_DM1
M_B_DM2
M_B_DM3
M_B_DM4
M_B_DM5
M_B_DM6
M_B_DM7

D14
A18
A22
C25
AF25
AG22
AH18
AD14

15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15

M_B_DQS0
M_B_DQS#0
M_B_DQS1
M_B_DQS#1
M_B_DQS2
M_B_DQS#2
M_B_DQS3
M_B_DQS#3
M_B_DQS4
M_B_DQS#4
M_B_DQS5
M_B_DQS#5
M_B_DQS6
M_B_DQS#6
M_B_DQS7
M_B_DQS#7

C15
B15
E18
D18
E22
D22
B26
A26
AG24
AG25
AG21
AF21
AG17
AG18
AH14
AG14
R26
R27
P27
P28

15 M_B_DIM0_CLK_DDR0
15 M_B_DIM0_CLK_DDR#0
15 M_B_DIM0_CLK_DDR1
15 M_B_DIM0_CLK_DDR#1
15 M_B_DIM0_CKE0
15 M_B_DIM0_CKE1

J26
J27

15 M_B_DIM0_ODT0
15 M_B_DIM0_ODT1

W27
Y28

15 M_B_DIM0_CS#0
15 M_B_DIM0_CS#1

V25
Y27

15 M_B_RAS#
15 M_B_CAS#
15 M_B_WE#

V24
V27
V28

15 M_B_RST#

M_B_EVENT#

J25
T25

MB_ADD0
MB_ADD1
MB_ADD2
MB_ADD3
MB_ADD4
MB_ADD5
MB_ADD6
MB_ADD7
MB_ADD8
MB_ADD9
MB_ADD10
MB_ADD11
MB_ADD12
MB_ADD13
MB_ADD14
MB_ADD15
MB_BANK0
MB_BANK1
MB_BANK2
MB_DM0
MB_DM1
MB_DM2
MB_DM3
MB_DM4
MB_DM5
MB_DM6
MB_DM7
MB_DQS_H0
MB_DQS_L0
MB_DQS_H1
MB_DQS_L1
MB_DQS_H2
MB_DQS_L2
MB_DQS_H3
MB_DQS_L3
MB_DQS_H4
MB_DQS_L4
MB_DQS_H5
MB_DQS_L5
MB_DQS_H6
MB_DQS_L6
MB_DQS_H7
MB_DQS_L7
MB_CLK_H0
MB_CLK_L0
MB_CLK_H1
MB_CLK_L1
MB_CKE0
MB_CKE1
MB_ODT0
MB_ODT1
MB_CS#0
MB_CS#1
MB_RAS#
MB_CAS#
MB_WE#
MB_RESET#
MB_EVENT#

SAINE

U20
R20
R21
P22
P21
N24
N23
N20
N21
M21
U23
M22
L24
AA25
L21
L20

SAINE

D

M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_A15

14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14

3

MB_DATA0
MB_DATA1
MB_DATA2
MB_DATA3
MB_DATA4
MB_DATA5
MB_DATA6
MB_DATA7
MB_DATA8
MB_DATA9
MB_DATA10
MB_DATA11
MB_DATA12
MB_DATA13
MB_DATA14
MB_DATA15
MB_DATA16
MB_DATA17
MB_DATA18
MB_DATA19
MB_DATA20
MB_DATA21
MB_DATA22
MB_DATA23
MB_DATA24
MB_DATA25
MB_DATA26
MB_DATA27
MB_DATA28
MB_DATA29
MB_DATA30
MB_DATA31
MB_DATA32
MB_DATA33
MB_DATA34
MB_DATA35
MB_DATA36
MB_DATA37
MB_DATA38
MB_DATA39
MB_DATA40
MB_DATA41
MB_DATA42
MB_DATA43
MB_DATA44
MB_DATA45
MB_DATA46
MB_DATA47
MB_DATA48
MB_DATA49
MB_DATA50
MB_DATA51
MB_DATA52
MB_DATA53
MB_DATA54
MB_DATA55
MB_DATA56
MB_DATA57
MB_DATA58
MB_DATA59
MB_DATA60
MB_DATA61
MB_DATA62
MB_DATA63

A14
B14
D16
E16
B13
C13
B16
A16

M_B_DQ0
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ7

15
15
15
15
15
15
15
15

C17
B18
B20
A20
E17
B17
B19
C19

M_B_DQ8
M_B_DQ9
M_B_DQ10
M_B_DQ11
M_B_DQ12
M_B_DQ13
M_B_DQ14
M_B_DQ15

15
15
15
15
15
15
15
15

C21
B22
C23
A24
D20
B21
E23
B23

M_B_DQ16
M_B_DQ17
M_B_DQ18
M_B_DQ19
M_B_DQ20
M_B_DQ21
M_B_DQ22
M_B_DQ23

15
15
15
15
15
15
15
15

E24
B25
B27
D28
B24
D24
D26
C27

M_B_DQ24
M_B_DQ25
M_B_DQ26
M_B_DQ27
M_B_DQ28
M_B_DQ29
M_B_DQ30
M_B_DQ31

15
15
15
15
15
15
15
15

AG26
AH26
AF23
AG23
AG27
AF27
AH24
AE24

M_B_DQ32
M_B_DQ33
M_B_DQ34
M_B_DQ35
M_B_DQ36
M_B_DQ37
M_B_DQ38
M_B_DQ39

15
15
15
15
15
15
15
15

AE22
AH22
AE20
AH20
AD23
AD22
AD21
AD20

M_B_DQ40
M_B_DQ41
M_B_DQ42
M_B_DQ43
M_B_DQ44
M_B_DQ45
M_B_DQ46
M_B_DQ47

15
15
15
15
15
15
15
15

AF19
AE18
AE16
AH16
AG20
AG19
AF17
AD16

M_B_DQ48
M_B_DQ49
M_B_DQ50
M_B_DQ51
M_B_DQ52
M_B_DQ53
M_B_DQ54
M_B_DQ55

15
15
15
15
15
15
15
15

AG15
AD15
AG13
AD13
AG16
AF15
AE14
AF13

M_B_DQ56
M_B_DQ57
M_B_DQ58
M_B_DQ59
M_B_DQ60
M_B_DQ61
M_B_DQ62
M_B_DQ63

15
15
15
15
15
15
15
15

D

C

B

SAINE
SAINE

APU_VREF_DQ
DDR_VREF_S3
1D5V_S3
RN501
C502
SC1KP50V2KX-1GP

2

C501
SCD1U10V2KX-5GP

1

M_VREF_DQ_APU
1

R502 2
Do Not Stuff

2

1

4
3

1
2

M_A_EVENT#
M_B_EVENT#
DQ15 AMD DIS SAMSUNG TI

SRN1KJ-7-GP

A

A

Wistron Corporation

LAYOUT: place them close to APU

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

1207: Change To 4 Pin Array Resistor
Title

AMD Confirm: PU Needed even if not used

5

4

3

2

Size
A3

Document Number

Date:

Thursday, May 26, 2011

APU_DDR(2/5)

Rev

QUEEN AMD Muxless/UMA
Sheet
1

5

of

X00
104

5

4

3

2

1

RN610

Boot Voltage

SVD

0

0

1.1

1.1

0

1

1.0

1.2

1

0

0.9

1.1

1

1

0.8

0.9

(VCC/GND)

DP_AUX0N
DP_AUX0P

Boot Voltage

SVC

(open)

4
3

0112: Change To 2 Single 1.8K 0402 for
layout routing.

1
2
SRN1K8J-GP
RN611

DP_AUX1N
DP_AUX1P

4
3

1
2
SRN1K8J-GP

APU1C

3 OF 6

1008: De-Pop R602, Follow Checklist

ANALOG/DISPLAY/MISC

DP1_TX0P
DP1_TX0N

K2
K1

2 SCD1U16V2KX-3GP
2 SCD1U16V2KX-3GP

DP1_TX1P
DP1_TX1N

J3
J2

19 DP1_TX2P_R
19 DP1_TX2N_R

FCH_UMA_PX C622 1
FCH_UMA_PX C623 1

2 SCD1U16V2KX-3GP
2 SCD1U16V2KX-3GP

DP1_TX2P
DP1_TX2N

H2
H1

19 DP1_TX3P_R
19 DP1_TX3N_R

FCH_UMA_PX C624 1
FCH_UMA_PX C625 1

2 SCD1U16V2KX-3GP
2 SCD1U16V2KX-3GP

DP1_TX3P
DP1_TX3N

G2
G3
AH7
AH6
AH4
AH3

2

17 DISP_CLKP
17 DISP_CLKN
EC601

18
18
71
17
17,36,71

RN606
1
2

SCLK3
SDATA3
APU_RST_L_BUF
APU_RST#
H_CPUPWRGD

1 R631
DY

1D5V_S0
4
3

1 R629
1 R630

71
71
71
71
71
71
71

APU_RST#
H_CPUPWRGD

RN603
RN608

DY

AF10
AE10

C12
A12
A11
D12
B12
B11
C11
E8
K21
AC11

RN605

DY

APU_RST#_R
APU_PWRGD_R

APU_TDI
APU_TDO
APU_TCK
APU_TMS
APU_TRST#
APU_DBRDY
APU_DBREQ#

APU_TDI
APU_TDO
APU_TCK
APU_TMS
APU_TRST#
APU_DBRDY
APU_DBREQ#

1 R648

42 APU_VDDNB_RUN_FB_L

42 APU_VDDNB_RUN_FB_H

APU_SVD_R
APU_SVC_R

1
2

2 Do Not Stuff

1 R649
2 Do Not Stuff
Do Not Stuff TP620

42 APU_VDD_RUN_FB_L

4
3

AH11
AG11

1
2

Do Not Stuff
1D5V_S0

1

APU_RUN_FB_L
APU_VDDP_FB_H

Do Not Stuff

TP622

1

APU_VDDIO_SUS_FB_H

Do Not Stuff

TP623

1

APU_VDDR_FB_H

42 APU_VDD_RUN_FB_H

Do Not Stuff

1D5V_S3

APU_SIC
APU_SID

AD10
APU_THERMTRIP#_VDDIO AG12
APU_ALERT#
AH12

1D5V_S3
4
3

2 Do Not Stuff
2 Do Not Stuff

1 R632DY2 Do Not Stuff

0111: Dummy APU-> FCH Prochot function

SRN300J-3-GP
1
2

DY

2 Do Not Stuff

H_CPUPWRGD

17 APU_PROCHOT#_VDDIO
27,40 H_PROCHOT#

Do Not Stuff
4
3

B9
C8
A9
B10
C9
A10

SAINE

DP1_TXP0
DP1_TXN0

DP3_AUXP
DP3_AUXN

DP1_TXP1
DP1_TXN1

DP4_AUXP
DP4_AUXN

DP1_TXP2
DP1_TXN2

DP5_AUXP
DP5_AUXN
DP0_HPD
DP1_HPD
DP2_HPD
DP3_HPD
DP4_HPD
DP5_HPD

DP1_TXP3
DP1_TXN3
CLKIN_H
CLKIN_L

DP_BLON
DP_DIGON
DP_VARY_BL

DISP_CLKIN_H
DISP_CLKIN_L

DP_AUX_ZVSS
SVC
SVD

TEST6
TEST9
TEST10
TEST12
TEST14
TEST15
TEST16
TEST17
TEST18
TEST19
TEST20
TEST21
TEST22
TEST23
TEST24
TEST25_H
TEST25_L
TEST28_H
TEST28_L
TEST30_H
TEST30_L
TEST31
TEST32_H
TEST32_L
TEST35

SIC
SID
RESET#
PWROK
PROCHOT#
THERMTRIP#
ALERT#
TDI
TDO
TCK
TMS
TRST#
DBRDY
DBREQ#
RSVD#E8
RSVD#K21
RSVD#AC11
VSS_SENSE
VDDP_SENSE
VDDNB_SENSE
VDDIO_SENSE
VDD_SENSE
VDDR_SENSE

FS1R1
DMAACTIVE#
THERMDA
THERMDC

DP_AUX1P
DP_AUX1N

C603 1
C601 1

UMA_PX
UMA_PX
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP

2
2

2 SCD1U16V2KX-3GP
2 SCD1U16V2KX-3GP

LVDS_CHP_TRAVIS
LVDS_CHN_TRAVIS

1 C626
1 C627

DP1_AUXP_R 19
DP1_AUXN_R 19

VGA

PCH_HDMI_CLK_R 51
PCH_HDMI_DATA_R 51

HDMI

FCH_UMA_PX
FCH_UMA_PX

J5
J6

9
9

LVDS

APU_TEST25_H_BYPASSCLK_H

1 R611

2 510R2J-1-GP

M_TEST

1 R608

2 39R2F-GP

APU_TEST9_ANALOGIN

R602
1DY

2 Do Not Stuff

APU_TEST18_PLLTEST1

1 R605

2 1KR2J-1-GP

APU_TEST24_SCANCLK1
APU_TEST21_SCANEN

4
3

D

H4
H5
RN612

G5
G6

1
2

F4
F5

SRN1KJ-7-GP
DP0_HPD
DP1_HPD

D7
E7
J7
H7
G7
F7

DP2_HPD

C6
C5
C7

APU_BLPWM_R

D8

DP_AUX_ZVSS 1 R623

FCH_UMA_PX

1 R621

RN609

51

APU_TEST19_PLLTEST0
APU_TEST22_SCANSHIFTEN
APU_TEST20_SCANCLK2
APU_TEST12_SCANSHIFTEND

DY

R671
1
Do Not Stuff

APU_TEST9_ANALOGIN

2

1D2V_S0

DY
R672

APU_TEST12_SCANSHIFTEND
APU_TEST14_BP0
APU_TEST15_BP1
APU_TEST16_BP2
APU_TEST17_BP3
APU_TEST18_PLLTEST1
APU_TEST19_PLLTEST0
APU_TEST20_SCANCLK2
APU_TEST21_SCANEN
APU_TEST22_SCANSHIFTEN

1
2
3
4
SRN1KJ-4-GP

3D3V_S0

APU_BLPWM

2 Do Not Stuff

2 150R2F-1-GP
LVDS_CHN_TRAVIS

AA10
G10
H10
H12
D9
E9
G9
H9
H11
G11
F12
E11
D11
F10
G12
AH10
AH9
K7
K8
AA12
AB12
K22
AB11
AA11
D10

8
7
6
5

LVDS_CHP_TRAVIS

Do Not Stuff1

APU_TEST25_L_BYPASSCLK_L

1 R613

ALLOW_STOP

1 R614

2 510R2J-1-GP

2

1D5V_S0

TP611 Do Not Stuff
TP610 Do Not Stuff
TP612 Do Not Stuff
TP613 Do Not Stuff
APU_TEST18_PLLTEST1 71
APU_TEST19_PLLTEST0 71

2 Do Not Stuff
DY
1D5V_S3

1 R643

2 1KR2J-1-GP

1 R615

2 Do Not Stuff
DY

3D3V_AUX_S5

APU_TEST24_SCANCLK1
APU_TEST25_H_BYPASSCLK_H
APU_TEST25_L_BYPASSCLK_L

C

FS1R1

1D5V_S3
ANATSTIN_H
ANATSTIN_L
M_TEST
ANATSTOUT_H
ANATSTOUT_L
TEST35

TP601 Do Not Stuff
TP617 Do Not Stuff

[AMD FAE Frank]: This is electrical key.
Do not allow power to turn on if this pin is still "L."
FS1 package is open pin, in the furtur, FS1r2 will have this pin tied to VSS.
If the wrong processor is plugged the socket, this is more of a problem on desktop platforms
(CPUs changing)

TP618 Do Not Stuff
TP619 Do Not Stuff

FS1R1

Y11
AB10

FS1R1
36
ALLOW_STOP 17

R612
300R2J-4-GP
TEST35

AE12
AD12

DY R617

Do Not Stuff

PU for internal
PD for customer

SAINE

2

1

B8
A8

42 APU_SVC_R
42 APU_SVD_R

Do Not Stuff

DY

DP0_TXP3
DP0_TXN3

DP_AUX0P
DP_AUX0N

E5
E6

1

2 SCD1U16V2KX-3GP
2 SCD1U16V2KX-3GP

FCH_UMA_PX C620 1
FCH_UMA_PX C621 1

DP2_AUXP
DP2_AUXN

D4
D5

2

FCH_UMA_PX C618 1
FCH_UMA_PX C619 1

19 DP1_TX1P_R
19 DP1_TX1N_R

DP1_AUXP
DP1_AUXN

1

19 DP1_TX0P_R
19 DP1_TX0N_R

DP0_AUXP
DP0_AUXN

DP0_TXP2
DP0_TXN2
DISPLAY PORT 0

C2
C3

DP0_TXP1
DP0_TXN1

DISPLAY PORT MISC.

DP0_TX3P
DP0_TX3N

DP0_TXP0
DP0_TXN0

DISPLAY PORT 1

1
1

Do Not Stuff TP604
Do Not Stuff TP605

F2
F1

CLK

D2
D1

SER.

E3
E2

DP0_TX2P
DP0_TX2N

CTRL

DP0_TX1P
DP0_TX1N

1
1

17 APU_CLKP
17 APU_CLKN

APU_RST_L_BUF

C

DP0_TX0P
DP0_TX0N

2 SCD1U16V2KX-3GP
2 SCD1U16V2KX-3GP

TEST

0109: EMI Reserve, Place Near R631

2 SCD1U16V2KX-3GP
2 SCD1U16V2KX-3GP

UMA_PX C607 1
UMA_PX C604 1

JTAG

DP Input To FCH

UMA_PX C602 1
UMA_PX C606 1

Do Not Stuff TP602
Do Not Stuff TP603

RSVD

9 LVDS_L1P_TRAVIS
9 LVDS_L1N_TRAVIS

SENSE

9 LVDS_L0P_TRAVIS
9 LVDS_L0N_TRAVIS

Travis LVDS Panel
D

RN607
1
2
3D3V_S0
1D5V_S3

1 R637

19 DP_HPD1_R
1

1
1D5V_S3

APU_THERMTRIP#_VDDIO

E

RN604
APU_TRST#
APU_TCK
APU_TMS
APU_TDI

E

DYC

PCH_TEMP_ALERT# 19,27

Q603
Do Not Stuff

H_THERMTRIP# 18,36,85

APU_PROCHOT#_VDDIO

C
Q602
MMBT3904-4-GP

Do Not Stuff
2ND = 84.03904.P11
3rd = 84.03904.L06

84.T3904.C11
2ND = 84.03904.P11
3rd = 84.03904.L06

84.T3904.C11
2ND = 84.03904.P11
3rd = 84.03904.L06

1

1
APU_PROCHOT#_VDDIO_R

42

1 R641

DP_HPD0_C

2150KR2J-L1-GP DP_HPD0_C_B

R646
100KR2J-1-GP

1

APU_SIC

DP0_HPD
R642
10KR2J-3-GP

1

DY

0714: Move From Page 9

C629
Do Not Stuff

1

2

C628
Do Not Stuff

2

2 1KR2J-1-GP APU_PROCHOT#_VDDIO

DY

DY

1D5V_S3
3D3V_S0_TRAVIS

R667
Do Not Stuff

D

G
SML1_CLK

H_CPUPWRGD

84.00138.H31
SML1_DATA

27,85

2

3
Q611
Do Not Stuff

1 R633

H_CPUPWRGD_E

1

A

DQ15 AMD DIS SAMSUNG TI

42
APU_BLPWM

2 Do Not Stuff

S

1011: Reserve Level Shift.

DY
2

101227

2

APU_BLPWM_Q1

1

DY

DY

B

Do Not Stuff
2ND = 84.03904.P11

R652
10KR2J-3-GP

D

27,85
APU_SID

S

Q607
BSS138-8-GP

E

C

APU_BLPWM_TRAVIS

Wistron Corporation

9

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Q608
MMBT3904-4-GP

1

84.00138.H31
2

G

APU_SIC

1D5V_S3

R650
10KR2J-3-GP

R657

UMA_PX

R668
Do Not Stuff
2

Q606
BSS138-8-GP

2

1D5V_S3

1

1

3D3V_S5

1

0105: APU SMBUS Timing Issue, Change From BJT To Mos
3D3V_S5

A

R656
2K2R2J-2-GP

3D3V_S0

4K7R2J-2-GP

H_CPUPWRGD_B

2

2

1008: Change R616 From 300 Ohm To 1K, AMD Checklist Update

2

1D5V_S0
1

1D5V_S3
1 R616

84.T3904.C11
2ND = 84.03904.P11

Q605 3rd = 84.03904.L06
MMBT3904-4-GP

B

1

9

APU_DBREQ#

B

1D5V_S3

1207 Modify: Add Level Shift, Page
42 Regulator Has 3D3V_S0 Pull High

CPU exceeds to 125

2300R2J-4-GP

DP1_HPD
R640
10KR2J-3-GP
2

E

℃

SRN1KJ-4-GP
1 R634

APU_ALERT#

C
Q601
MMBT3904-4-GP

Q604 3rd = 84.03904.L06
MMBT3904-4-GP

B

2

1
2
3
4

APU_SID

8
7
6
5

84.T3904.C11
2ND = 84.03904.P11

C
R638
10KR2J-3-GP

2150KR2J-L1-GP DP_HPD1_C_B

R644
DY Do Not Stuff

C

1008: FCH No Internal PU, POP R638

1 R639

2

3D3V_S5

2

SRN1KJ-4-GP

BAPU_PROCHOT#_VDDIO_Q

APU_ALERT#
APU_THERMTRIP#_VDDIO
APU_SIC
APU_SID

APU_ALERT#_Q 2

1
2
3
4

B

RN601
8
7
6
5

DP_HPD1_C

R636

DY Do Not Stuff

1

S3 Power
1D5V_S3
B

1D5V_S3

2

1

PCH_TEMP_ALERT#

2

210KR2J-3-GP

BAPU_THERMTRIP#_VDDIO_Q

1 R651

DP_HPD1_C

2 Do Not Stuff

FCH_UMA_PX

R653
10KR2J-3-GP

1D5V_S3

R635
10KR2J-3-GP

E

SRN1K8J-GP

3D3V_S5

E

4
3

R655
Do Not Stuff

84.T3904.C11
2ND = 84.03904.P11

Title

3rd = 84.03904.L06

Size
Document Number
Custom

APU_COntrol&Debug(3/5)
Rev

QUEEN AMD Muxless/UMA

Date: Thursday, May 26, 2011
5

4

3

2

Sheet
1

6

of

X00
104

4

1
2

1
2

1

1
2

2

1
2

1
2

VDDA
VDDA

DY

1

1

C746

180pF Cap for EMI requirment

DY

1

1

C742
Do Not Stuff

C741
Do Not Stuff

DY
2

DY
2

1

C743

VDDP:

C745

2

C747

2

1

C748

2

1

1

C749

2

C750

2

1
2

1
2

A5
A6
B5
B6

C751

C744

2

1

4.7uF X4

2

1

1
2

2

1
2

1

1
2

2
1

1
2

2

1
2
1
2

1
2
1
2

10uF X2
0.22uF X6

Decoupling between processor and DIMMs
across VDDIO and VSS Split

10uF X3
0.22uF X4

B

180pF Cap for EMI requirment

1D2V_S0

1
2

1
2

1

1
2

2

1
2

1

1
2

2

C752
SC1KP50V2KX-1GP

1

C753
SC1KP50V2KX-1GP

2

C754
SC1KP50V2KX-1GP

1

C755
SC1KP50V2KX-1GP

1

C756
SC4D7U6D3V3KX-GP

2

C757
SC4D7U6D3V3KX-GP

2

C758
SC4D7U6D3V3KX-GP

1

C759
SC4D7U6D3V3KX-GP

2

C760

DY

Do Not Stuff

1

C761

DY

Do Not Stuff

2

C762

DY

Do Not Stuff

1

C763

DY

Do Not Stuff

2

C764
SCD22U10V2KX-1GP

1

C765
SCD22U10V2KX-1GP

2

C766
SCD22U10V2KX-1GP

1

C767
SCD22U10V2KX-1GP

1

1

DY

C731

Do Not Stuff

2

DY

C732

3.5A for VDDP(35W/45W)

2

1
2
1
2

1

1
2

2
1

1
2

C733

Do Not Stuff

1

C734

SCD22U10V2KX-1GP

1

C735

SCD22U10V2KX-1GP

2

1D5V_S3

4A for VDDIO(35W CPU)
4.6A for VDDIO(45W CPU)

SAINE

SC3300P50V2KX-1GP

SCD22U10V2KX-1GP

SC4D7U6D3V3KX-GP

2

0111: Change C744, C743 From 22uF to 0.22 uF

VDDIO:

SCD22U10V2KX-1GP

2

1
2
1

SAINE

1
2

1

1
2

2

1
2

SC10U6D3V5KX-1GP

1
1
2
1

1

C

SCD22U10V2KX-1GP

2

D

180pF Cap for EMI requirment

SC4D7U6D3V3KX-GP

2

10nF X3
180pF Cap for EMI requirment

Do Not Stuff

1

0.22uF X2

10nF X4

Do Not Stuff

2

10uF X7

1D5V_S3

SCD22U10V2KX-1GP

C738

DY

0.22UF X2

Do Not Stuff

C739

VDDR
VDDR
VDDR
VDDR

C709

18A for VDDNB(35W CPU)
22A for VDDNB(45W CPU)

C720

DY

SC10U6D3V5KX-1GP

AE11
AF11
C740

VDDR
VDDR
VDDR
VDDR

C710

1D2V_S0

A3
A4
B3
B4

SC10U6D3V5KX-1GP

AG6
AG7
AG8
AG9

2D5V_S0

DY

C736

C721

SCD22U10V2KX-1GP

0.75A for VDDA(35W/45W)

VDDP_B
VDDP_B
VDDP_B
VDDP_B

C737

SCD22U10V2KX-1GP

B

VDDP_A
VDDP_A
VDDP_A
VDDP_A

R22
R25
R28
T20
T23
T26
U22
U25
U28
V20
V23
V26
W22
W25
W28
Y24
Y26
AA28

C722

SCD22U10V2KX-1GP

Do Not Stuff

DY

VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO

C723

SC10U6D3V5KX-1GP

1D2V_S0

AG2
AG3
AG4
AG5

C724

VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO

C711

10UF X4

K11
K12
K13
K14
K16
K17
K18
L18

Do Not Stuff

1D2V_S0

C725
SC4D7U6D3V3KX-GP

Do Not Stuff

SCD22U10V2KX-1GP

DY

G28
H26
J28
K20
K23
K26
L22
L25
L28
M20
M23
M26
N22
N25
N28
P20
P23
P26

VDDNB
VDDNB
VDDNB
VDDNB
VDDNB
VDDNB
VDDNB
VDDNB

C712

VDDNB:

SC22U6D3V5MX-2GP

C726

DY

VDDNB
VDDNB
VDDNB
VDDNB
VDDNB
VDDNB
VDDNB
VDDNB

C713

APU_VDDNB

SC22U6D3V5MX-2GP

C727

DY

C715

Do Not Stuff

DY

C716

Do Not Stuff

C728
SCD22U10V2KX-1GP

SCD22U10V2KX-1GP

Do Not Stuff

DY

C729

C717

Do Not Stuff

C730

SC22U6D3V5MX-2GP

1D5V_S3

C718

SC22U6D3V5MX-2GP

C719

2

C

J9
J10
J11
J12
J14
J16
K9
K10

36A for VDD(35W CPU)
45A for VDD(45W CPU)
C714

Do Not Stuff

APU_VDDNB

1

VDD:

APU_VDD
T6
T10
T18
U1
U11
U19
V3
V6
V10
V18
W1
W11
W13
W15
W17
W19
Y3
Y6
Y10
Y12
Y14
Y16
Y18
Y20
AA1
AB3
AB6
AC1
AD3
AD6
AE1

SCD01U16V2KX-3GP

DY

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

SCD22U10V2KX-1GP

1

C701

2

4 OF 6

SC10U6D3V5KX-1GP

2

C702

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

SC10U6D3V5KX-1GP

2

C703

C1
D3
D6
E1
F3
F6
F8
G1
H3
H6
H8
J1
K3
K6
L1
L11
L19
M3
M6
M10
M18
N1
N11
N19
P3
P6
P10
P18
R1
R11
R19
T3

SC10U6D3V5KX-1GP

Do Not Stuff

C704

Do Not Stuff

DY

C705

SCD01U16V2KX-3GP

2

C706

SCD01U16V2KX-3GP

1

C707

SCD22U10V2KX-1GP

2

C708

SC10U6D3V5KX-1GP

D

APU1D

SC10U6D3V5KX-1GP

1

APU_VDD

3

2

5

VDDR:
3A for VDDR(35W)
3.5A for VDDR(45W)

A

A

DQ15 AMD DIS SAMSUNG TI

4.7uF X4

Wistron Corporation

0.22uF X4

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

1nF X4
180pF Cap for EMI requirment

Title

APU_Power(4/5)

Size
Document Number
Custom

QUEEN AMD Muxless/UMA

Date:
5

4

3

Thursday, May 26, 2011

Sheet
2

7

of

Rev

X00
104
1

5

4

3

2

1

D

D

C

B

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

5 OF 6

SAINE

APU1E
A7
A13
A15
A17
A19
A21
A23
A25
B7
C4
C10
C14
C16
C18
C20
C22
C24
C26
C28
D13
D15
D17
D19
D21
D23
D25
D27
E4
E10
E12
F9
F11
F14
F16
F18
F20
F22
F24
F26
F28
G4
G8
G13
G15
G17
G19
G21
G23
G25
J4
J8
J18
J20
J22
J24
K19
L4
L7
L10
M9
M11
M19
N4
N7
N10
N18
P9
P11
P19
R4
R7
R10
R18
T9

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

T11
T19
U4
U7
U10
U18
V9
V11
V19
W4
W7
W10
W12
W14
W16
W18
Y9
Y22
AA4
AA7
AB9
AB13
AB15
AB17
AB19
AB21
AB23
AB25
AB27
AC4
AC7
AC10
AC12
AC14
AC16
AC18
AC20
AC22
AC24
AC26
AC28
AD9
AD11
AE4
AE7
AE13
AE15
AE17
AE19
AE21
AE23
AE25
AE27
AF3
AF6
AF9
AF12
AF14
AF16
AF18
AF20
AF22
AF24
AF26
AF28
AG10
AH5
AH8
AH13
AH15
AH17
AH19
AH21
AH23
AH25

C

B

SAINE

DQ15 AMD DIS SAMSUNG TI

A

A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

5

4

3

2

Size
A3

Document Number

Date:

Thursday, May 26, 2011

APU_VSS(5/5)

Rev

QUEEN AMD Muxless/UMAX00
Sheet
1

8

of

104

5

4

3

2

1

1207: Use PLT_RST# to replace
3D3V_S0_TRAVIS for APU_PCIE_RST#_R.
1D2V_TRAVIS

2 Do Not Stuff

APU_PCIE_RST#_R

DVDD33 DVDD12 AVDD33

UMA_PX

1

R922 1
Do Not Stuff

UMA_PX

DY
1

1231:Reserve 10K, Vendor Suggest

DY
L_BKLT_EN

1

2

1

1
2

2

1

SC2D2U10V3KX-1GP

1

2

SCD1U10V2KX-5GP

1

2

2

Do Not Stuff

1

1

2

2

1

SC2D2U10V3KX-1GP

2

Do Not Stuff

2

1

1
2

Do Not Stuff

C922
Do Not Stuff

C

C925

DY

DY

C927

UMA_PX
UMA_PX
UMA_PX

1
2

12KR2F-L-GP

1

UMA_PX
C912
SC100P50V2JN-3GP

UMA_PX

2

UMA_PX

C926

C928

1

C924

C923

2

ANX3100_CLK_SEL
R904

0512 David

150mA

2

SCD01U16V2KX-3GP

2

Do Not Stuff

1
1

R926
100KR2J-1-GP

1 R927

2

2
1

2
5
62

1

AVSS
AVSS
AVSS

L903
UMA_PX

HCB2012KF-221T30-GP

68.00216.161
2ND = 68.00206.121

3D3V_S0_TRAVIS

UMA_PX 10KR2J-3-GP

UMA_PX

AVDD33

SCD01U16V2KX-3GP

R917
Do Not Stuff
GND_TRVS

DY
UMA_PX

220 ohm 3A

2

1231: Change To 10K PU

DY

3D3V_S0_TRAVIS

C919

C918

2

Do Not Stuff

2

DYDo Not Stuff

DY

C917

1

UMA_PX

2

C916

2

R915
10KR2J-3-GP

UMA_PX

C915

2

2
R914

AVDD12

9
32
46
59

8
25
33
39
63
AVDD33
AVDD33
AVDD33
AVDD33
AVDD33

13
53

2
SCD1U10V2KX-5GP

UMA_PX

1

1
1 R906

C920

2

DYDo Not Stuff
C

C901
Do Not Stuff

LVDS_DDC_DATA_R
49
LVDS_DDC_CLK_R
49
L_BKLT_CTRL 49
L_BKLT_EN 27
LVDS_VDD_EN 49

1

1

DDC_DATA
DDC_CLK
VARY_BL
BL_EN
DIGON

2 Do Not Stuff
2 Do Not Stuff

SC2D2U10V3KX-1GP

UMA_PX

16
17
18

GND

3D3V_S0

LVDS_CHN_TRAVIS

DVDD12
DVDD12
DVDD12
DVDD12

DVDD33
DVDD33

DPRX_HPD

ANX3110-GP

1R907
1R908

1

58

UMA_PX

2

2LVDS_HPD_TRAVIS

Do Not Stuff

LVDS_DDC_DATA_X
LVDS_DDC_CLK_X

68.00216.161
2ND = 68.00206.121
DY

Do Not Stuff

UMA_PX 1R905

0112: Vendor Suggestion To Add PU For AUXP, PL for AUXN

50
49
47
15
14

HCB2012KF-221T30-GP

LVDSA_CLK 49
LVDSA_CLK# 49
LVDSA_DATA2 49
LVDSA_DATA2# 49
LVDSA_DATA1 49
LVDSA_DATA1# 49
LVDSA_DATA0 49
LVDSA_DATA0# 49

2

DP_HPD0_C

UMA_PX

DPRX_L0_P
DPRX_L0_N
DPRX_L1_P
DPRX_L1_N

SCD01U16V2KX-3GP

6

AUX_CH_N
AUX_CH_P

Do Not Stuff

3
4
6
7

AVDD12

400mA

2UMA_PX

1

60
61

UMA_PX

DY

L901

1

1

LVDS_CHN_TRAVIS_C
LVDS_CHP_TRAVIS_C

6 LVDS_L0P_TRAVIS
6 LVDS_L0N_TRAVIS
6 LVDS_L1P_TRAVIS
6 LVDS_L1N_TRAVIS

D

220 ohm 3A
No Need

2

2SCD1U16V2KX-3GP
2SCD1U16V2KX-3GP

UMA_PX

C911

C904

UMA_PX UMA_PX

1D2V_TRAVIS

29
28
27
26
24
23
22
21
20
19

1

C921 1
C932 1

LVDS_L3_P
LVDS_L3_N
LVDS_CLKL_P
LVDS_CLKL_N
LVDS_L2_P
LVDS_L2_N
LVDS_l1_P
LVDS_l1_N
LVDS_L0_P
LVDS_L0_N

CPU_VARY_BL

C910

DY

1

UMA_PX
6 LVDS_CHN_TRAVIS
6 LVDS_CHP_TRAVIS

TDO
TDI
TMS
TCK

C903

UMA_PX

DY

if use single channel,
have to use L Group

C909

2

48

6 APU_BLPWM_TRAVIS

LVDS_U3_P
LVDS_U3_N
LVDS_CLKU_P
LVDS_CLKU_N
LVDS_U2_P
LVDS_U2_N
LVDS_U1_P
LVDS_U1_N
LVDS_U0_P
LVDS_U0_N

OSC_IN
OSC_OUT

1

0105: Vendor Suggestion To Add Pair of Cap In Near Travis Also

POR#
RESET#

CLK_SEL
TEST_EN
R_BIAS

54
55
57
56

CFG_SDA
CFG_SCL

DAC_TDO
DAC_TDI
DAC_TMS
DAC_TCK

1
1
1
1

C908

10
11
64

31
30

17 TRAVIS_REFCLKN
17 TRAVIS_REFCLKP
Do Not Stuff TP902
Do Not Stuff TP904
Do Not Stuff TP903
Do Not Stuff TP901

45
44
43
42
41
40
38
37
36
35

ANX3100_CLK_SEL
DAC_TST_EN
R_BIAS

34
12

52
51

UMA_PX
1231: New Spec Changed Pin 30 To IN and Connect P,
From Vendor Feedback. Mail Confirm

POR#
APU_PCIE_RST#_R

GPIO_0
GPIO_1
GPIO_2

1
2

2 C905

C907

SCD01U16V2KX-3GP

SCD1U10V2KX-5GP

C906
Do Not Stuff

Do Not Stuff

DY

UMA_PX

1

GND_TRVS

U902
R902
1MR2J-L2-GP

SCD1U10V2KX-5GP

3D3V_S0_TRAVIS

TRAVIS Rev 1.01 sugget
to stuff 1M-ohm

D

1 R903

400mA

2

C902
SCD1U10V2KX-5GP

2

DY
Do Not Stuff

65

1

0628: Change Tolerence to 5 %

LVDS_CHP_TRAVIS

DVDD12

AVDD12

R923

2

2

1 R901

Do Not Stuff

PLT_RST#

3D3V_S0_TRAVIS

SCD1U10V2KX-5GP

UMA_PX
17,71,82,83

3D3V_S0_TRAVIS

Vendor Confirm: C912 100p
R921 1

DVDD33

UMA_PX

150mA

2

B

0504 -Sabine David
Annie and Rosa team soluton co-layout

0321

MOS spec VGS:20V

1
R924

1D2V_TRAVIS

R916

1

2
1

2

MOS spec VGS:20V

1

Rosa:RUN_Enable 15V
Annie:RUN Enable 9V

1

2

Do Not Stuff

DY

C933
Do Not Stuff

A

1

2

DY

DY

Do Not Stuff

TRAVIS_3D3V

DY

Do Not Stuff

1
2

DY

D

G

G
1
2

2

1 R918

For ANX3100 ALSO
3D3V_S0

D

DY

Q903_D

C936
Do Not Stuff

B

2

U905
Do Not Stuff

Do Not Stuff

TRAVIS_1D2V

DY

UMA_PX

Do Not Stuff

1D2V_S0

S

R919
Do Not Stuff

A

1

U901
Do Not Stuff

S

15V_S5

C931

UMA_PX

0321

3D3V_S0_TRAVIS

0714: Add to Avoid System Run Power Being Pull Low

C930

2
Do Not Stuff

R925

Rosa:RUN_Enable 15V
Annie:RUN Enable 9V

C929
Do Not Stuff

SCD1U10V2KX-5GP

DY

SC2D2U10V3KX-1GP

1

2

Do Not Stuff

DY
2

Q903

G

18 TRAVIS_EN#

C935
Do Not Stuff

DY

DQ15 AMD DIS SAMSUNG TI

1

D
R920
Do Not Stuff

Wistron Corporation

S
Do Not Stuff

2

DY

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Reserved for tuning sequence of 3.3V and 1.2V

Do Not Stuff

Title

TRAVIS ANX3100

2ND = 84.2N702.031

5

4

3

2

Size
A2

Document Number

Date:

Friday, May 27, 2011

Rev

QUEEN AMD Muxless/UMA X00
Sheet
1

9

of

104

5

4

3

2

1

D

D

C

C

B

B

A

A

DQ15 AMD DIS SAMSUNG TI

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

5

4

3

2

Reserved

Size
A2

Document Number

Date:

Thursday, May 26, 2011

Rev

QUEEN AMD Muxless/UMA X00
Sheet

10

of

104

1

5

4

3

2

1

D

D

C

C

B

B

DQ15 AMD DIS SAMSUNG TI

A

A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

5

4

3

2

Size
A3

Document Number

Date:

Thursday, May 26, 2011

Reserved

Rev

QUEEN AMD Muxless/UMAX00
Sheet
1

11

of

104

5

4

3

2

1

D

D

C

C

B

B

DQ15 AMD DIS SAMSUNG TI

A

A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

5

4

3

2

Size
A3

Document Number

Date:

Thursday, May 26, 2011

Reserved

Rev

QUEEN AMD Muxless/UMAX00
Sheet
1

12

of

104

5

4

3

2

1

D

D

C

C

B

B

DQ15 AMD DIS SAMSUNG TI

A

A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

5

4

3

2

Size
A3

Document Number

Date:

Thursday, May 26, 2011

Reserved

Rev

QUEEN AMD Muxless/UMAX00
Sheet
1

13

of

104

5

4

3

2

1

SSID = MEMORY
0117: Brazo S3 Issue, Sabine Reserve Only

DM1

VTT1
VTT2

1

1

1

2

2
1

1

C1402

DYDo Not Stuff

1D5V_S3
RN1401

75
76
81
82
87
88
93
94
99
100
105
106
111
112
117
118
123
124

SA0_DIM0

PCH_SMBDATA
PCH_SMBCLK

2
1

3
4

SMB_DATA 18,75
SMB_CLK 18,75

SA1_DIM0

C

1

1

SRN0J-6-GP

2
3
8
9
13
14
19
20
25
26
31
32
37
38
43
44
48
49
54
55
60
61
65
66
71
72
127
128
133
134
138
139
144
145
150
151
155
156
161
162
167
168
172
173
178
179
184
185
189
190
195
196
205
206

R1402
Do Not Stuff

PCH_SMBDATA
PCH_SMBCLK

C1423 1
C1424 1

DY2

Do Not Stuff
2 Do Not Stuff

DY

2

2

R1401
Do Not Stuff

B

SODIMM A DECOUPLING Layout Note: Place these Caps near SO-DIMMA.
1D5V_S3

0112: Change TC1401 330uF 6mΩ To 220uF 15 mΩ"DY" same as DV14 Brazo

C1415

C1416

C1409

DY

1

C1408

C1410

DY
2

DY

1

1

C1407

DY

2

1

C1406

2

1

C1405

2

DY

2

1

1

C1404

2

2

2

C1403

DY

1

C1414

1

TC1401

DY

M_A_RST#
C1425
Do Not Stuff

C1401
SCD1U10V2KX-5GP

2

77
122
125

2

RESET#

SA0_DIM0
SA1_DIM0

197
201

1

VREF_CA
VREF_DQ

199

C1417
SCD1U10V2KX-5GP

203
204

ODT0
ODT1

1213 Modify: Remove Dimm Thermal Function

3D3V_S0

198

SCD1U10V2KX-5GP

0D75V_S0

30

DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7

PCH_SMBDATA 15,79,82
PCH_SMBCLK 15,79,82

Intel HR DM tied to GND
AMD still following previous design

SCD1U10V2KX-5GP

5 M_A_RST#

126
1

DQS0#
DQS1#
DQS2#
DQS3#
DQS4#
DQS5#
DQS6#
DQS7#

200
202

5
5
5
5
5
5
5
5

SCD1U10V2KX-5GP

Intel HR channel A & B RST tied toghter
AMD have to separate channel A & B

116
120

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

M_A_DM0
M_A_DM1
M_A_DM2
M_A_DM3
M_A_DM4
M_A_DM5
M_A_DM6
M_A_DM7

Do Not Stuff

DDR_VREF_S3

VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
VDD10
VDD11
VDD12
VDD13
VDD14
VDD15
VDD16
VDD17
VDD18

5
5

11
28
46
63
136
153
170
187

Do Not Stuff

5 M_A_DIM0_ODT0
5 M_A_DIM0_ODT1

NC#1
NC#2
NC#/TEST

M_A_DIM0_CLK_DDR1
M_A_DIM0_CLK_DDR#1

DY

Do Not Stuff

12
29
47
64
137
154
171
188

SA0
SA1

102
104

DY

Do Not Stuff

M_A_DQS0
M_A_DQS1
M_A_DQS2
M_A_DQS3
M_A_DQS4
M_A_DQS5
M_A_DQS6
M_A_DQS7

VDDSPD

5
5

SC10U6D3V5KX-1GP

5
5
5
5
5
5
5
5

SDA
SCL
EVENT#

5
5

M_A_DIM0_CLK_DDR0
M_A_DIM0_CLK_DDR#0

Do Not Stuff

10
27
45
62
135
152
169
186

DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7

M_A_DIM0_CKE0
M_A_DIM0_CKE1

101
103

R1404
Do Not Stuff

SC10U6D3V5KX-1GP

M_A_DQS#0
M_A_DQS#1
M_A_DQS#2
M_A_DQS#3
M_A_DQS#4
M_A_DQS#5
M_A_DQS#6
M_A_DQS#7

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63

73
74

D

R1403
Do Not Stuff

Do Not Stuff

5
5
5
5
5
5
5
5

CK1
CK1#

BA0
BA1

5
5

2

B

CK0
CK0#

M_A_DIM0_CS#0
M_A_DIM0_CS#1

Do Not Stuff

Place these caps close to VTT1 and VTT2.

CKE0
CKE1

114
121

5
5
5

1

1

C1422

DYDo Not Stuff
2

1

C1421
SC1U6D3V2KX-GP

2

1

C1420

DYDo Not Stuff
2

C1419
SC1U6D3V2KX-GP

CS0#
CS1#

M_A_DIM0_CKE0
M_A_DIM0_CKE1
M_A_RAS#
M_A_WE#
M_A_CAS#

2

2
2

1

0D75V_S0

5
7
15
17
4
6
16
18
21
23
33
35
22
24
34
36
39
41
51
53
40
42
50
52
57
59
67
69
56
58
68
70
129
131
141
143
130
132
140
142
147
149
157
159
146
148
158
160
163
165
175
177
164
166
174
176
181
183
191
193
180
182
192
194

RAS#
W E#
CAS#

NP1
NP2
110
113
115

1

C1418

DYDo Not Stuff

109
108

M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63

NP1
NP2

1

1

0D75V_S0

5 M_A_BS0
5 M_A_BS1
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15
A16/BA2

2

1

C

98
97
96
95
92
91
90
86
89
85
107
84
83
119
80
78
79

2

DY

C1413
SCD1U10V2KX-5GP

2

1

C1412
Do Not Stuff

2

C1411
SCD1U10V2KX-5GP

2

1

DDR_VREF_S3

M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_A15
5 M_A_BS2

2

5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5

D

DDR3-204P-43-GP

H =4mm

2

DY

0914: DIMM1 Change To 62.10017.N71
0628: Reserve Cap

A

A

DQ15 AMD DIS SAMSUNG TI

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

DDR3-SODIMM1
Size

Document Number

Date:

Thursday, May 26, 2011

Rev

QUEEN AMD Muxless/UMA
5

4

3

2

Sheet
1

14

of

X00
104

5

D

4

3

2

1

SSID = MEMORY

D

0117: Brazo S3 Issue, Sabine Reserve Only

SO-DIMMB is placed farther from
the Processor than SO-DIMMA

M_B_DIM0_CKE0
M_B_DIM0_CKE1

5 M_B_DIM0_ODT0
5 M_B_DIM0_ODT1
DDR_VREF_S3

1

M_B_RST#
A

C1522
Do Not Stuff

Intel HR channel A & B RST tied toghter
AMD have to separate channel A & B

DY

5 M_B_RST#

2

0D75V_S0

116
120
126
1
30
203
204

1

198

DQS0#
DQS1#
DQS2#
DQS3#
DQS4#
DQS5#
DQS6#
DQS7#
DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
ODT0
ODT1
VREF_CA
VREF_DQ
RESET#
VTT1
VTT2

1
R1501
10KR2J-3-GP
C

SA0_DIM1

199

77
122
125

C1501
SCD1U10V2KX-5GP

SA1_DIM1
C1502
Do Not Stuff

1

SA0_DIM1
SA1_DIM1

DY

R1502
Do Not Stuff

75
76
81
82
87
88
93
94
99
100
105
106
111
112
117
118
123
124

2

1D5V_S3

Intel HR B channel address is 01
AMD B channel address is 10

SODIMM B DECOUPLING

Layout Note: Place these Caps near SO-DIMMB.

C1513

C1509

1

1

C1508

C1510

DY
2

DY

2

1

1

C1507

2

1

C1506

2

C1505

2

1
2

2

C1504

1

C1512

1

C1511

DY

2

C1503

DY

1

1D5V_S3

2
3
8
9
13
14
19
20
25
26
31
32
37
38
43
44
48
49
54
55
60
61
65
66
71
72
127
128
133
134
138
139
144
145
150
151
155
156
161
162
167
168
172
173
178
179
184
185
189
190
195
196
205
206

2

197
201

1

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

3D3V_S0

2

VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
VDD10
VDD11
VDD12
VDD13
VDD14
VDD15
VDD16
VDD17
VDD18

2

2
SA0
SA1
NC#1
NC#2
NC#/TEST

Intel HR DM tied to GND
AMD still following previous design

PCH_SMBDATA 14,79,82
PCH_SMBCLK 14,79,82
3D3V_S0

1

EVENT#
VDDSPD

200
202

5
5
5
5
5
5
5
5

2

SDA
SCL

M_B_DM0
M_B_DM1
M_B_DM2
M_B_DM3
M_B_DM4
M_B_DM5
M_B_DM6
M_B_DM7

2

M_B_DIM0_CLK_DDR1
5
M_B_DIM0_CLK_DDR#1
5

1

DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7

1

1
2

1
2

1
2

1
2

12
29
47
64
137
154
171
188

M_B_DIM0_CLK_DDR0
5
M_B_DIM0_CLK_DDR#0
5

102
104
11
28
46
63
136
153
170
187

Do Not Stuff

M_B_DQS0
M_B_DQS1
M_B_DQS2
M_B_DQS3
M_B_DQS4
M_B_DQS5
M_B_DQS6
M_B_DQS7

CK1
CK1#

SC10U6D3V5KX-1GP

5
5
5
5
5
5
5
5

CK0
CK0#

B

C1514
SCD1U10V2KX-5GP

10
27
45
62
135
152
169
186

101
103

DY

SCD1U10V2KX-5GP

M_B_DQS#0
M_B_DQS#1
M_B_DQS#2
M_B_DQS#3
M_B_DQS#4
M_B_DQS#5
M_B_DQS#6
M_B_DQS#7

5
5

SCD1U10V2KX-5GP

5
5
5
5
5
5
5
5

M_B_DIM0_CKE0
M_B_DIM0_CKE1

SCD1U10V2KX-5GP

Place these caps close to VTT1 and VTT2.

73
74

R1504
Do Not Stuff

DY

Do Not Stuff

C1521
SC1U6D3V2KX-GP

5
5

5
5
5

SC10U6D3V5KX-1GP

C1520

DYDo Not Stuff

M_B_DIM0_CS#0
M_B_DIM0_CS#1

SC10U6D3V5KX-1GP

C1519
SC1U6D3V2KX-GP

M_B_RAS#
M_B_WE#
M_B_CAS#

114
121

SC10U6D3V5KX-1GP

C1518

DYDo Not Stuff

CKE0
CKE1

BA0
BA1
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63

R1503
Do Not Stuff

110
113
115

Do Not Stuff

0D75V_S0

M_B_DQ0
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ7
M_B_DQ8
M_B_DQ9
M_B_DQ10
M_B_DQ11
M_B_DQ12
M_B_DQ13
M_B_DQ14
M_B_DQ15
M_B_DQ16
M_B_DQ17
M_B_DQ18
M_B_DQ19
M_B_DQ20
M_B_DQ21
M_B_DQ22
M_B_DQ23
M_B_DQ24
M_B_DQ25
M_B_DQ26
M_B_DQ27
M_B_DQ28
M_B_DQ29
M_B_DQ30
M_B_DQ31
M_B_DQ32
M_B_DQ33
M_B_DQ34
M_B_DQ35
M_B_DQ36
M_B_DQ37
M_B_DQ38
M_B_DQ39
M_B_DQ40
M_B_DQ41
M_B_DQ42
M_B_DQ43
M_B_DQ44
M_B_DQ45
M_B_DQ46
M_B_DQ47
M_B_DQ48
M_B_DQ49
M_B_DQ50
M_B_DQ51
M_B_DQ52
M_B_DQ53
M_B_DQ54
M_B_DQ55
M_B_DQ56
M_B_DQ57
M_B_DQ58
M_B_DQ59
M_B_DQ60
M_B_DQ61
M_B_DQ62
M_B_DQ63

CS0#
CS1#

Do Not Stuff

B

5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5

5
7
15
17
4
6
16
18
21
23
33
35
22
24
34
36
39
41
51
53
40
42
50
52
57
59
67
69
56
58
68
70
129
131
141
143
130
132
140
142
147
149
157
159
146
148
158
160
163
165
175
177
164
166
174
176
181
183
191
193
180
182
192
194

RAS#
W E#
CAS#

NP1
NP2

2

2

DY

C1517
SCD1U10V2KX-5GP

109
108

NP1
NP2

1

C1516
Do Not Stuff

5 M_B_BS0
5 M_B_BS1

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15
A16/BA2

2

1

1

2

C1515
SCD1U10V2KX-5GP

2

1

DDR_VREF_S3

98
97
96
95
92
91
90
86
89
85
107
84
83
119
80
78
79

2

C

M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
M_B_A14
M_B_A15
5 M_B_BS2

1

DM2
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5

A

DQ15 AMD DIS SAMSUNG TI

DDR3-204P-44-GP

H = 8mm

0628: Reserve Cap

Wistron Corporation

0914: DIMM2 Change To 62.10017.N91

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

DDR3-SODIMM2
Size

Document Number

Date:

Thursday, May 26, 2011

Rev

QUEEN AMD Muxless/UMA
5

4

3

2

Sheet
1

15

of

X00
104

5

4

3

2

1

D

D

C

C

B

B

DQ15 AMD DIS SAMSUNG TI

A

A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

5

4

3

2

Size
A3

Document Number

Date:

Thursday, May 26, 2011

Reserved

Rev

QUEEN AMD Muxless/UMA
Sheet
1

16

of

X00
104

4

Ext. Clock_Gen
6 DISP_CLKP
6 DISP_CLKN
9 TRAVIS_REFCLKP
9 TRAVIS_REFCLKN
6 APU_CLKP
6 APU_CLKN
83 CLK_PCIE_VGA
83 CLK_PCIE_VGA#

New Card

75 CLK_PCIE_NEW
75 CLK_PCIE_NEW#

WLAN

82 CLK_PCIE_WLAN
82 CLK_PCIE_WLAN#

Do Not Stuff
Do Not Stuff

1 R1718
1 R1719

2
2

FCHDISP_CLKP_R
FCHDISP_CLKN_R

R26
T26

Do Not Stuff
Do Not Stuff

1 R1720
1 R1721

2
2

FCHTRVS_CLKP_R
FCHTRVS_CLKN_R

H33
H31

Do Not Stuff
Do Not Stuff

1 R1736
1 R1737

2
2

FCHAPU_CLKP_R
FCHAPU_CLKN_R

T24
T23

Do Not Stuff
Do Not Stuff

1 R1738
1 R1739

2
2

FCHGFX_CLKP_R
FCHGFX_CLKN_R

J30
K29

2
2

NEW_CLK_R
NEW_CLK#_R

H27
H28

Do Not Stuff
Do Not Stuff

R1744 1
R1745 1

Do Not Stuff
Do Not Stuff

DN15
DN15

1 R1740
1 R1741

CLK_MINI1_R
CLK_MINI1#_R

2
2

J27
K26
F33
F31

WWAN

B

Do Not Stuff
Do Not Stuff

82 CLK_PCIE_LAN
82 CLK_PCIE_LAN#

LAN
GPP CLK port

Device

CLKREQ#

0
1
2
3
4
5
6
7
8

New Card
WLAN
WWAN
LAN
X
X
X
X
X

0
1
2
3

1 R1742
1 R1743

LAN_CLK_R
LAN_CLK#_R

2
2

E33
E31
M23
M24
M27
M26
N25
N26
R23
R24

If LAN support Wake on S5,
do not use clock from FCH,
have to use X'tal

Use 48Mhz CLK For 5138
1 R1711

222R2J-2-GP

48M_OSC

J26

PCIE_RCLKP
PCIE_RCLKN
DISP_CLKP
DISP_CLKN
DISP2_CLKP
DISP2_CLKN
APU_CLKP
APU_CLKN
SLT_GFX_CLKP
SLT_GFX_CLKN
GPP_CLK0P
GPP_CLK0N

INTE#/GPIO32
INTF#/GPIO33
INTG#/GPIO34
INTH#/GPIO35

GPP_CLK1P
GPP_CLK1N

GPP_CLK3P
GPP_CLK3N
GPP_CLK4P
GPP_CLK4N
GPP_CLK5P
GPP_CLK5N
GPP_CLK6P
GPP_CLK6N
GPP_CLK7P
GPP_CLK7N
GPP_CLK8P
GPP_CLK8N

DMA_ACTIVE#
PROCHOT#
APU_PG
LDT_STP#
APU_RST#

C31

25M_X2

C33

25M_X1

32K_X2

1

1

1
2
1

PE_PWRGD

Do Not Stuff

1 R1728

PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
DGPU_PWROK

2

BACO

21
21
21
21
21
86,92,93

KBC

0719: EMI Request

Folloiwng Intel HR netname

1 R1716

PCIE_RST#_C

0916: Add 1D5V_VGA_PWOK Connect To FCH,
AMD BACO Document Update
1207: Change DGPU_PWROK To 1D5V_VGA_PWOK
3D3V_S0

0105: Follow DV GPIO
RTC_SENSE
KB_LED_BL_DET

60
69

25M_X1

1

X1701

3D3V_S0

R1724
Do Not Stuff

LPCCLK0_R

1 R1726

LPC_AD0_R
LPC_AD1_R
LPC_AD2_R
LPC_AD3_R
LPC_FRAME#_R

1
1
1
1
1

DY

DY

APU_STOP# 1 R1702

27

PM_CLKRUN#:
HDD_FALL_INT1

No PU Res needed, integrated Resistor PU10K
0719: ADD, Confirm SW

79

1019: Add KB_LED_BL_DET FCH GPIO.

DY2

Do Not Stuff
LPC_CLK0 21,27
LPC_CLK1 21
LPC_AD0 27,71
LPC_AD1 27,71
LPC_AD2 27,71
LPC_AD3 27,71
LPC_FRAME# 27,71

33R2J-2-GP
33R2J-2-GP
33R2J-2-GP
33R2J-2-GP
33R2J-2-GP

INT_SERIRQ

B

There is integrated pull-up.

32K_X1

G4

32K_X2

H7
F1
F3
E6

INTRUDER_ALERT#

1

2 Do Not Stuff
TP1701
RTC_AUX_S5

PCH_SUSCLK_KBC
RTC_CLK 21

32K_X1

1

32K_X2
PCH_SUSCLK_KBC
1

4

DY EC1703
Do Not Stuff

82.30020.D41

25M_X2

2

Document Number
Size
Custom

SC15P50V2JN-2-GP

Reserved

4

A

Rev

QUEEN AMD Muxless/UMA

Date:
5

1
2
C1703
SC18P50V2JN-1-GP
DQ15 AMD DIS SAMSUNG TI

Title

0719: EMI Request
1

X-32D768KHZ-67-GP

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

1122 Modify:
Change X1701 to 82.30020.D41 from 82.30020.851
from Sourcer Dick updated.

3
XTAL-25MHZ-155-GP C1705

X1702

Wistron Corporation

2

1

2

1
2
C1702
SC18P50V2JN-1-GP

R1703
20MR3-GP

27

C1706
SCD1U16V2KX-3GP

2
R1701
1MR2J-1-GP

DY

3D3V_S0

0906: Change X1702 From 82.3001.661 To 82.3001.A81
Base on Sourcer Suggestion

6

6

R1706
1

2 Do Not Stuff

27

APU_RST#

SC15P50V2JN-2-GP
1

1 R1705

INT_SERIRQ

ALLOW_STOP 6
APU_PROCHOT#_VDDIO
H_CPUPWRGD
6,36,71

APU_STOP#

G2

1D5V_S0

PE_GPIO0: VGA_RESET
PE_GPIO1: VGA_PowerEnable

83
92,93

0304: Reserve 0 Ohm For EA Fail

INT_SERIRQ

2 Do Not Stuff
DY

Muxless support

222R2J-2-GP
2
2
2
2
2

C

69 KB_LED_BL_DET

DN15

R1729
R1730
R1731
R1732
R1734

9,71,82,83

56

1 R1727 2
Do Not Stuff

B25
D25
D27
C28
A26
A29
A31
B27
AE27
AE19

PLT_RST#

C1715
SC150P50V2KX-GP

R1725
Do Not Stuff

PM_CLKRUN#
INTE#

2

2 33R2J-2-GP

LDT_STP# connection is just for chipset automation purpose.
It is an automatic test for AMD validation team only

PE_GPIO0
PE_GPIO1
SATA_ODD_DA#

71.HUDM2.M01

C1704

A

2

2
2

2

CLK_PCI_LPC

1

S5_CORE_EN
RTCCLK
INTRUDER_ALERT#
VDDBT_RTC_G

For SW Jin define

2

25M_X2

S5 PLUS

0719: EMI Request

For SW Jin define

DY EC1702
Do Not Stuff

2

25M_X1

D

Debug Strap

AF18
AE18
AC16
AD18

G25
E28
E26
G26
F26

DY

EC1704

DY

14M_25M_48M_OSC
32K_X1

DY EC1701
Do Not Stuff

GSENSOR_DET
dGPU_PRSNT#

C1701 1
LPCCLK0
LPCCLK1
LAD0
LAD1
LAD2
LAD3
LFRAME#
LDRQ0#
LDRQ1#/CLK_REQ6#/GPIO49
SERIRQ/GPIO48

R1735
Do Not Stuff

PX

DGPU_PWROK

GPP_CLK2P
GPP_CLK2N

1

32 CLK_PCH_48M

N27
R27

CLK_CALRN

R1722
10KR2J-3-GP

3

F27
G30
G28

0109: EMI Reserve, Place Near R1728

2

CLK_CALRN

AJ3
AL5
AG4
AL6
AH3
AJ5
AL1
AN5
AN6
AJ1
AL8
AL3
AM7
AJ6
AK7
AN8
AG9
AM11
AJ10
AL12
AK11
AN12
AG12
AE12
AC12
AE13
AF13
AH13
AH14
AD15
AC15
AE16
AN3
AJ8
AN10
AD12
AG10
AK9
AL10
AF10
AE10
AH1
AM9
AH8
AG15
AG13
AF15
AM17
AD16
AD13
AD21
AK17
AD19
AH9

1

2 2KR2F-3-GP

CLOCK GENERATOR

1 R1710

DN15
GSENSOR_DET

1

GPP_RX0P
GPP_RX0N
GPP_RX1P
GPP_RX1N
GPP_RX2P
GPP_RX2N
GPP_RX3P
GPP_RX3N

C

1D1V_CKVDD_S0

R1733
Do Not Stuff

DIS_UMA

4

AA27
AA26
W27
V27
V26
W26
W24
W23

75 PCIE_RXP5
75 PCIE_RXN5

GPP_TX0P
GPP_TX0N
GPP_TX1P
GPP_TX1N
GPP_TX2P
GPP_TX2N
GPP_TX3P
GPP_TX3N

R1723
Do Not Stuff
dGPU_PRSNT#

TP1702

2

1214: Add DN15 Express Card

AD0/GPIO0
AD1/GPIO1
AD2/GPIO2
AD3/GPIO3
AD4/GPIO4
AD5/GPIO5
AD6/GPIO6
AD7/GPIO7
AD8/GPIO8
AD9/GPIO9
AD10/GPIO10
AD11/GPIO11
AD12/GPIO12
AD13/GPIO13
AD14/GPIO14
AD15/GPIO15
AD16/GPIO16
AD17/GPIO17
AD18/GPIO18
AD19/GPIO19
AD20/GPIO20
AD21/GPIO21
AD22/GPIO22
AD23/GPIO23
AD24/GPIO24
AD25/GPIO25
AD26/GPIO26
AD27/GPIO27
AD28/GPIO28
AD29/GPIO29
AD30/GPIO30
AD31/GPIO31
CBE0#
CBE1#
CBE2#
CBE3#
FRAME#
DEVSEL#
IRDY#
TRDY#
PAR
STOP#
PERR#
SERR#
REQ0#
REQ1#/GPIO40
REQ2#/CLK_REQ8#/GPIO41
REQ3#/CLK_REQ5#/GPIO42
GNT0#
GNT1#/GPO44
GNT2#/SD_LED/GPO45
GNT3#/CLK_REQ7#/GPIO46
CLKRUN#
LOCK#

UMI_RX0P
UMI_RX0N
UMI_RX1P
UMI_RX1N
UMI_RX2P
UMI_RX2N
UMI_RX3P
UMI_RX3N
PCIE_CALRP
PCIE_CALRN

2 22R2J-2-GP
2 Do Not Stuff

1

2

V33
V31
W30
W32
AB26
AB27
AA24
AA23

PCIE_TXP5_C
PCIE_TXN5_C

1 R1714
1 R1715

1

2 Do Not Stuff
DN15
2 Do Not Stuff
DN15

AF29
AF31

PCI_RST#

3D3V_S0

2

C1719 1
C1720 1

75 PCIE_TXP5
75 PCIE_TXN5

APU_PCIE_CALRP
APU_PCIE_CALRN

AB5

TP59 Do Not Stuff
PCI_CLK1
21
TP60 Do Not Stuff
CLK_PCI_LPC 21,71
PCI_CLK4
21

1

2 590R2F-GP
2 2KR2F-3-GP

PCIRST#

2 Do Not Stuff

2

1 R1708
1 R1709

UMI_TX0P
UMI_TX0N
UMI_TX1P
UMI_TX1N
UMI_TX2P
UMI_TX2N
UMI_TX3P
UMI_TX3N

1 R1712

1

AB33
AB31
AB28
AB29
Y33
Y31
Y28
Y29

UMI_APU_FCH_TX0P
UMI_APU_FCH_TX0N
UMI_APU_FCH_TX1P
UMI_APU_FCH_TX1N
UMI_APU_FCH_TX2P
UMI_APU_FCH_TX2N
UMI_APU_FCH_TX3P
UMI_APU_FCH_TX3N
1D1V_PCIE_S0

1

3D3V_S0

Do Not Stuff

AE30
AE32
AD33
AD31
AD28
AD29
AC30
AC32

PCI_CLK0_R
PCI_CLK1_R
PCI_CLK2_R
PCI_CLK3_R
PCI_CLK4_R

1

A_RX0P_C
A_RX0N_C
A_RX1P_C
A_RX1N_C
A_RX2P_C
A_RX2N_C
A_RX3P_C
A_RX3N_C

AF3
AF1
AF5
AG2
AF6

2

SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP

PCICLK0
PCICLK1/GPO36
PCICLK2/GPO37
PCICLK3/GPO38
PCICLK4/14M_OSC/GPO39

PCI CLKS

2
2
2
2
2
2
2
2

PCIE_RST#
A_RST#

LPC

4
4
4
4
4
4
4
4

1
1
1
1
1
1
1
1

AE2
AD5

PCI INTERFACE

D

C1707
C1708
C1709
C1710
C1711
C1712
C1713
C1714

UMI_FCH_APU_RX0P
UMI_FCH_APU_RX0N
UMI_FCH_APU_RX1P
UMI_FCH_APU_RX1N
UMI_FCH_APU_RX2P
UMI_FCH_APU_RX2N
UMI_FCH_APU_RX3P
UMI_FCH_APU_RX3N

2

0628: Change R1712 & R1715 Short Pad
PCIE_RST#_C
A_RST#_R

2 33R2J-2-GP

APU

4
4
4
4
4
4
4
4

1 R1717

A_RST#

PCI EXPRESS INTERFACES

27,36

3

Part 5 of 5

FCH1E
C1716
SC150P50V2KX-GP

2

1

5

3

2

Friday, May 27, 2011

Sheet
1

17

of

X00
104

5

4

0909: Modify
Pop R1843 For UMA Config
Pop R1844 For Muxless Config

3

0109: EMI Reserve, Place Near R1810

2

1

Remove PCIE2_RST, Did Not Use FCH GPP

3D3V_S5
2

FCH_PCIE_RST#
2

R1843
Do Not Stuff

EC1803

1213 Modify: Remove Dimm Thermal Function
1214 Add PCIE2_RST For EXPRESS CARD FCH GPP

RSMRST#_R

0716: From KBC

C1802

2

6,36,85

0719: Change From 2.2K and POP
RN1802
4
3

2 Do Not Stuff

1 R1815

2 10KR2J-3-GP

WD_PWRGD

27 RSMRST#_KBC

1 R1821

2 Do Not Stuff

RSMRST#_R

1 R1829

2 Do Not Stuff

PCIE_CLK_LAN_RQ1#_R

2 Do Not Stuff

CLK_PCIE_NEW_REQ#_R
FCH_GPIO55

2

HDA_SPKR_R

DN15

1 R1846
1 R1842
1 R1841
1 R1840

75 CLK_PCIE_NEW_REQ#
9 TRAVIS_EN#
9 TRAVIS_EN#
29 HDA_SPKR
14,75 SMB_CLK
14,75 SMB_DATA

20

RN1804

2 Do Not Stuff

VGA_PD

DY
2 Do Not Stuff

PCH_WAKE#

DY
1 R1824

2 Do Not Stuff
2 Do Not Stuff

EC_SCI#

CLKREQG#

R1847

2 Do Not Stuff

FFS_INT2_X
EC_SWI#

1 R1830

2 Do Not Stuff

DY

EC18021
EC_SWI#

DY
1 R1835

2 Do Not Stuff

PM_PWRBTN#

CLK_PCIE_WLAN_REQ#_R

2 Do Not Stuff

1 R1822

FFS_INT2_R
27
EC_SWI#
82
USB_OC#5
56
ODD_DA_Q
56 SATA_ODD_PRSNT#
82
USB_OC#2
57
USB_OC#1
57
USB_OC#0

DY
1 R1833

2 Do Not Stuff

0909: Un-Stuff (DY) For Leakage Issue, Follow DQ15 Intel
85 PEG_CLKREQ#
79

1 R1839

2 Do Not Stuff
DY
2 Do Not Stuff
DY
Do Not Stuff

VGA_PD

Do Not Stuff
1 R1845

U2
AG24
AE24
AE26
AF22
AH17
AG18
AF24
AD26
AD25
T7
R7
AG25
AG22
J2
AG26
V8
W8
Y6
V10
AA8
AF25

SCLK1
SDATA1
1 R1834

FCH_TEST2
FCH_TEST1
FCH_TEST0

8
7
6
5

T9
T10
V9
AE22
AG19
R9
C26
T5
U4
K1
V7
R10
AF19

0719: ADD

82 PCIE_CLK_LAN_REQ#

82 CLK_PCIE_WLAN_REQ#

SRN10KJ-5-GP

DY

1 R1832

SCLK1
SDATA1

1
2

C

1
2
3
4

2 Do Not Stuff
2 Do Not Stuff

FCH_TEST0
FCH_TEST1
FCH_TEST2
EC_A20M#_R
EC_KB_RST#_R
EC_SCI#
EC_SMI#_R

H_THERMTRIP#
3D3V_S0

If it work normally, ask BIOS to re-program to GPIO55 to double verify.

3D3V_S5

1 R1814
1 R1813

PM_PWRBTN#_R

27 PCH_WAKE#

DY Do Not Stuff

* Travis_EN#: Base on AMD suggestion, use the GPIO66 same the CRB first.

H_A20GATE
H_RCIN#
EC_SCI#
EC_SMI#

2 Do Not Stuff

DN151

M7
R8
T1
P6
F5
P5
J7
T8

ODD_DA_Q
SATA_ODD_PRSNT#_R

1 R1803
1 R1804

2 33R2J-2-GP
2 33R2J-2-GP

HDA_BITCLK
HDA_SDOUT
HDA_SDIN0

AB3
AB1
AA2
Y5
Y3
Y1
AD6
AE4

0721: Reserve PM_PWRBTN# If KBC Change To OD

1 R1805
1 R1806
1

29 HDA_CODEC_SYNC
29 HDA_CODEC_RST#
1 R1836

2 Do Not Stuff

HDA_SYNC
HDA_RST#

K19
J19
J21

2

DY
1 R1837

2 33R2J-2-GP
2 33R2J-2-GP

2 Do Not Stuff

1 R1838

2 Do Not Stuff

DY

D21
C20
D23
C22

H_RCIN#

F21
E20
F20
A22
E18
A20
J18
H18
G18
B21
K18
D19
A18
C18
B19
B17
A24
D17

SMB_CLK
SMB_DATA

4
3
SRN2K2J-1-GP

Modify Zero Power ODD circuit by
Annie team suggestion.

RN1803
8
7
6
5

DY

HDA_CODEC_RST#

1
2
3
4

USB_FSD0P/GPIO185
USB_FSD0N
USB_HSD13P
USB_HSD13N
USB_HSD12P
USB_HSD12N
USB_HSD11P
USB_HSD11N

RSMRST#

USB_HSD9P
USB_HSD9N

CLK_REQ4#/SATA_IS0#/GPIO64
CLK_REQ3#/SATA_IS1#/GPIO63
SMARTVOLT1/SATA_IS2#/GPIO50
CLK_REQ0#/SATA_IS3#/GPIO60
SATA_IS4#/FANOUT3/GPIO55
SATA_IS5#/FANIN3/GPIO59
SPKR/GPIO66
SCL0/GPIO43
SDA0/GPIO47
SCL1/GPIO227
SDA1/GPIO228
CLK_REQ2#/FANIN4/GPIO62
CLK_REQ1#/FANOUT4/GPIO61
IR_LED#/LLB#/GPIO184
SMARTVOLT2/SHUTDOWN#/GPIO51
DDR3_RST#/GEVENT7#/VGA_PD
GBE_LED0/GPIO183
SPI_HOLD#/GBE_LED1/GEVENT9#
GBE_LED2/GEVENT10#
GBE_STAT0/GEVENT11#
CLK_REQG#/GPIO65/OSCIN/IDLEEXIT#

USB_HSD8P
USB_HSD8N
USB_HSD7P
USB_HSD7N
USB_HSD6P
USB_HSD6N

USB_HSD3P
USB_HSD3N
USB_HSD2P
USB_HSD2N
USB_HSD1P
USB_HSD1N
USB_HSD0P
USB_HSD0N
USBSS_CALRP
USBSS_CALRN
USB_SS_TX3P
USB_SS_TX3N
USB_SS_RX3P
USB_SS_RX3N
USB_SS_TX2P
USB_SS_TX2N
USB_SS_RX2P
USB_SS_RX2N

PS2_DAT/SDA4/GPIO187
PS2_CLK/CEC/SCL4/GPIO188
SPI_CS2#/GBE_STAT2/GPIO166
PS2KB_DAT/GPIO189
PS2KB_CLK/GPIO190
PS2M_DAT/GPIO191
PS2M_CLK/GPIO192

HDA_CODEC_BITCLK
HDA_SDIN0

Do Not Stuff

KSO_0/GPIO209
KSO_1/GPIO210
KSO_2/GPIO211
KSO_3/GPIO212
KSO_4/GPIO213
KSO_5/GPIO214
KSO_6/GPIO215
KSO_7/GPIO216
KSO_8/GPIO217
KSO_9/GPIO218
KSO_10/GPIO219
KSO_11/GPIO220
KSO_12/GPIO221
KSO_13/GPIO222
KSO_14/XDB0/GPIO223
KSO_15/XDB1/GPIO224
KSO_16/XDB2/GPIO225
KSO_17/XDB3/GPIO226

USB_HSD5P
USB_HSD5N
USB_HSD4P
USB_HSD4N

BLINK/USB_OC7#/GEVENT18#
USB_OC6#/IR_TX1/GEVENT6#
USB_OC5#/IR_TX0/GEVENT17#
USB_OC4#/IR_RX0/GEVENT16#
USB_OC3#/AC_PRES/TDO/GEVENT15#
USB_OC2#/TCK/GEVENT14#
USB_OC1#/TDI/GEVENT13#
USB_OC0#/SPI_TPM_CS#/TRST#/GEVENT12#

USB_SS_TX1P
USB_SS_TX1N
USB_SS_RX1P
USB_SS_RX1N
USB_SS_TX0P
USB_SS_TX0N
USB_SS_RX0P
USB_SS_RX0N

There are integrated pull-up.

RN1801
1
2

USB_FSD1P/GPIO186
USB_FSD1N

USB_HSD10P
USB_HSD10N

H_A20GATE

DY

B

USB_RCOMP

EC1801

DY Do Not Stuff

EC_SMI#

TEST0
TEST1/TMS
TEST2
GA20IN/GEVENT0#
KBRST#/GEVENT1#
LPC_PME#/GEVENT3#
LPC_SMI#/GEVENT23#
LPC_PD#/GEVENT5#
SYS_RESET#/GEVENT19#
WAKE#/GEVENT8#
IR_RX1/GEVENT20#
THRMTRIP#/SMBALERT#/GEVENT2#
WD_PWRGD

AZ_BITCLK
AZ_SDOUT
AZ_SDIN0/GPIO167
AZ_SDIN1/GPIO168
AZ_SDIN2/GPIO169
AZ_SDIN3/GPIO170
AZ_SYNC
AZ_RST#

D

USBCLK/14M_25M_48M_OSC

DY2Do Not Stuff

29 HDA_CODEC_BITCLK
29 HDA_CODEC_SDOUT
29 HDA_SDIN0

DY

3D3V_S0

Part 1 of 5

PCIE_RST2#/PCI_PME#/GEVENT4#
RI#/GEVENT22#
SPI_CS3#/GBE_STAT1/GEVENT21#
SLP_S3#
SLP_S5#
PWR_BTN#
PWR_GOOD

USB MISC

AB6
R2
W7
T3
W2
J4
N7

USB 1.1

2 100KR2J-1-GP RSMRST#_KBC
27
27
27
27

1

1 R1809

FCH_PCIE_RST#_R

USB 2.0

1 R1825

1 Do Not Stuff
2

USB 3.0

Confirm with SW, RSMRST# from KBC is push-pull.
It can be drived high by SW.

PM_SLP_S3#
PM_SLP_S5#
PM_PWRBTN#
FCH_PWRGD

FCH1A

DN15

R1810

75 FCH_PCIE_RST#
27,36,44,46,75
27,44,75
27
36

ACPI / WAKE UP EVENTS

1

DIS_PX

GPIO

D

USB OC

DY Do Not Stuff

R1844
10KR2J-3-GP

HD AUDIO

CLKREQG#

1

21

UMA

SCL2/GPIO193
SDA2/GPIO194
SCL3_LV/GPIO195
SDA3_LV/GPIO196
EC_PWM0/EC_TIMER0/GPIO197
EC_PWM1/EC_TIMER1/GPIO198
EC_PWM2/EC_TIMER2/WOL_EN/GPIO199
EC_PWM3/EC_TIMER3/GPIO200
EMBEDDED CTRL

KSI_0/GPIO201
KSI_1/GPIO202
KSI_2/GPIO203
KSI_3/GPIO204
KSI_4/GPIO205
KSI_5/GPIO206
KSI_6/GPIO207
KSI_7/GPIO208

71.HUDM2.M01

G8
B9

USB_RCOMP

1 R1819

2 11K8R2F-GP

H1
H3
H6
H5
H10
G10

USB20_DP3
USB20_DM3

82
82

K10
J12

USB20_DP2
USB20_DM2

82
82

G12
F12

USB20_DP1
USB20_DM1

82
82

K12
K13
B11
D11

USB_PP9 32
USB_PN9 32

E10
F10

USB_PP8 75
USB_PN8 75

C10
A10

USB_PP7 49
USB_PN7 49

1214: Add Express Card For DN15

H9
G9
A8
C8

USB_PP5 49
USB_PN5 49

F8
E8

C

USB_PP4 63
USB_PN4 63

C6
A6
C5
A5

USB_PP2 64
USB_PN2 64

C1
C3

USB_PP1 82
USB_PN1 82

E1
E3

1214: Add FP For DN15

USB_PP0 57
USB_PN0 57

C16 USBSS_CALRP
A16 USBSS_CALRN

1 R1817
1 R1818

A14 USB30_TXDP3_C
C14 USB30_TXDN3_C

C1803 1USB32 SCD1U16V2KX-3GP
C1804 1USB32 SCD1U16V2KX-3GP

2 1KR2F-3-GP
USB3
2 1KR2F-3-GP
USB3

1D1V_VDD_SSUSB_S5
USB30_TXDP3
USB30_TXDN3

C12
A12
D15 USB30_TXDP2_C
B15 USB30_TXDN2_C

C1805 1USB32 SCD1U16V2KX-3GP
C1806 1USB32 SCD1U16V2KX-3GP

E14
F14
F15 USB30_TXDP1_C
G15 USB30_TXDN1_C

C1807 1USB32 SCD1U16V2KX-3GP
C1808 1USB32 SCD1U16V2KX-3GP

H13
G13

62
62

USB30_RXDP3
USB30_RXDN3

62
62

USB30_TXDP2
USB30_TXDN2

62
62

USB30_RXDP2
USB30_RXDN2

62
62

USB30_TXDP1
USB30_TXDN1

62
62

USB30_RXDP1
USB30_RXDN1

62
62
B

J16
H16
J15
K15
H19 SCL2
G19 SDAT2
G22 SCLK3
G21 SDATA3
E22
H22
J22
H21

SCLK3 6
SDATA3 6
EC_PWM2

K21
K22
F22
F24
E24
B23
C24
F18

21

KB_DET# 69

0914: Remove DBC_EN & COLOR_ENGINE

0719: If not used SMBUS or GPIO, PD 10k.

RN1807

Checklist suggestion: Don't stuff for default

SCLK3
SDATA3

4
3

SCL2
SDAT2

1
2

SRN10KJ-5-GP
2
1
RN1805

SRN10KJ-5-GP

0719: Modify

3
4

A

A

3D3V_S5
RN1806
1
2
3
4

DQ15 AMD DIS SAMSUNG TI

USB_OC#1
USB_OC#2
USB_OC#5
USB_OC#0

8
7
6
5

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

SRN100KJ-8-GP-U
Title

Integrated PU is not
supported when the pin is
configured for USB over
current function.

Size

HUDSON-M2(2/6)
Document Number

Rev

QUEEN AMD Muxless/UMA
Date:
5

4

3

2

Friday, May 27, 2011

Sheet
1

18

of

X00
104

5

4

3

2

1

Part 2 of 5

FCH1B

0630: Place Cap Near Connecetor

2SCD01U16V2KX-3GP SATA_TXP2_C
2SCD01U16V2KX-3GP SATA_TXN2_C

C1909 1
C1910 1

SATA_TXP2
SATA_TXN2

AJ22
AH22
AM23
AK23

57 SATA_RXN2_C
57 SATA_RXP2_C

AH24
AJ24
AN24
AL24
AL26
AN26
AJ26
AH26
AN29
AL28
AK27
AM27
AL29
AN31
C

AL31
AL33
AH33
AH31
AJ33
AJ31

1 R1901
1 R1902

1D1V_SATA_S0
68

2 1KR2F-3-GP
2 1KR2F-3-GP

SATA_CALP
SATA_CALN

AF28
AF27
AD22

SATA_LED#

AF21

SATA_TX1P
SATA_TX1N
SATA_RX1N
SATA_RX1P

GBE_COL
GBE_CRS
GBE_MDCK
GBE_MDIO
GBE_RXCLK
GBE_RXD3
GBE_RXD2
GBE_RXD1
GBE_RXD0
GBE_RXCTL/RXDV
GBE_RXERR
GBE_TXCLK
GBE_TXD3
GBE_TXD2
GBE_TXD1
GBE_TXD0
GBE_TXCTL/TXEN
GBE_PHY_PD
GBE_PHY_RST#
GBE_PHY_INTR

SATA_TX2P
SATA_TX2N
SATA_RX2N
SATA_RX2P
SATA_TX3P
SATA_TX3N
SATA_RX3N
SATA_RX3P
SATA_TX4P
SATA_TX4N
SATA_RX4N
SATA_RX4P
SATA_TX5P
SATA_TX5N
SATA_RX5N
SATA_RX5P
NC#AL29
NC#AN31

SPI_DI/GPIO164
SPI_DO/GPIO163
SPI_CLK/GPIO162
SPI_CS1#/GPIO165
ROM_RST#/SPI_WP#/GPIO161
VGA_RED

NC#AL31
NC#AL33

VGA_GREEN

NC#AH33
NC#AH31

VGA_BLUE

NC#AJ33
NC#AJ31

VGA_HSYNC/GPO68
VGA_VSYNC/GPO69

SATA_CALRP
SATA_CALRN

VGA_DDC_SDA/GPO70
VGA_DDC_SCL/GPO71
VGA_DAC_RSET
AUX_VGA_CH_P
AUX_VGA_CH_N

SATA_ACT#/GPIO67

AUXCAL
SATA_X1
ML_VGA_L0P
ML_VGA_L0N
ML_VGA_L1P
ML_VGA_L1N
ML_VGA_L2P
ML_VGA_L2N
ML_VGA_L3P
ML_VGA_L3N

AG21

VGA MAINLINK

[Checklist]:
Integrated Clock Mode, left unconnected
SATA_X2

support ODD Zero power
56 SATA_ODD_PWRGT
Do Not Stuff TP1910

B

ML_VGA_HPD/GPIO229

FCH_PROCHOT#_C

1

AH16
AM15
AJ16
AK15
AN16
AL16

1 R1912

2 Do Not Stuff
DY

K6
K5
K3
M6

HW MONITOR

FANIN0/GPIO56
FANIN1/GPIO57
FANIN2/GPIO58

VIN0/GPIO175
VIN1/GPIO176
VIN2/SDATI_1/GPIO177
VIN3/SDATO_1/GPIO178
VIN4/SLOAD_1/GPIO179
VIN5/SCLK_1/GPIO180
VIN6/GBE_STAT3/GPIO181
VIN7/GBE_LED3/GPIO182

TEMPIN0/GPIO171
TEMPIN1/GPIO172
TEMPIN2/GPIO173
TEMPIN3/TALERT#/GPIO174

NC#AG16
NC#AH10
NC#A28
NC#G27
NC#L4

D

GBE_COL
GBE_CRS
GBE_MDIO

1 R1920

2 10KR2J-3-GP

3D3V_S5

RN1903
8
7
6
5

GBE_RXCLT

1
2
3
4
SRN10KJ-6-GP

GBE_PHY

V6
V5
V3
T6
V1

0916: Remove SPI Signal Connect To FCH
FCH_UMA_PX 1 R1904

2150R2F-1-GP

FCH_UMA_PX 1 R1905

2150R2F-1-GP

FCH_UMA_PX 1 R1906

2150R2F-1-GP

L30

CRT_RED

94

CRT_GREEN

94

CRT_BLUE

94

M28
N30

CRT_HSYNC
CRT_VSYNC

94
94

M33
N32

CRT_DDC_DATA 94
CRT_DDC_CLK 94

L32
M29

K31 HUDSON_DAC_RESET

1 R1907

C

2715R2F-GP

FCH_UMA_PX
V28
V29

DP1_AUXP_R
DP1_AUXN_R

U28 AUXCAL

1 R1913

2100R2F-L1-GP-U

T31
T33
T29
T28
R32
R30
P29
P28
1 R1908
N2
M3
L2
N4
P1
P3
M1
M5
AG16
AH10
A28
G27
L4

2Do Not Stuff

DY

C29

6
6

1D1V_VDDAN_ML_S0
DP1_TX0P_R
6
DP1_TX0N_R 6
DP1_TX1P_R
6
DP1_TX1N_R 6
DP1_TX2P_R
6
DP1_TX2N_R 6
DP1_TX3P_R
6
DP1_TX3N_R 6
3D3V_VDDAN_DAC_S0_R
DP_HPD1_R
6

PSW_CLR#
VRAM_SIZE1
VRAM_SIZE2
MEM_1V5
MEM_1V35
VIN_VDDIO
VIN_VDDR
GPIO182

VDDIO

B

[VRAM_SIZE1:VRAM_SIZE2]
LL=512M / HL=1G / LH=2G
3D3V_S5

MEM_1V5

MEM_1V35

1.5V

H

Don't Care

1.35V

L

H

2G R2214

Do Not Stuff

2

6,27 PCH_TEMP_ALERT#

GPIO171
FCH_USB3.0PORT_EN#
MB_THRMDA_FCH
APU_TALERT#

FANOUT0/GPIO52
FANOUT1/GPIO53
FANOUT2/GPIO54

AC4
AD3
AD9
W10
AB8
AH7
AF7
AE7
AD7
AG8
AD1
AB7
AF9
AG6
AE8
AD8
AB9
AC2
AA7
W9

1

AH20
AJ20

AL14
AN14
AJ12
AH12
AK13
AM13
AH15
AJ14

1G R2216

10KR2J-3-GP

2

57
57

eSATA

AN22
AL22

SD_CLK/SCLK_2/GPIO73
SD_CMD/SLOAD_2/GPIO74
SD_CD#/GPIO75
SD_WP/GPIO76
SD_DATA0/SDATI_2/GPIO77
SD_DATA1/SDATO_2/GPIO78
SD_DATA2/GPIO79
SD_DATA3/GPIO80

SATA_RX0N
SATA_RX0P

1

2SCD01U16V2KX-3GP SATA_TXP1_C
2SCD01U16V2KX-3GP SATA_TXN1_C

C1905 1
C1906 1

SATA_TXP1
SATA_TXN1

56 SATA_RXN1_C
56 SATA_RXP1_C

SATA_TX0P
SATA_TX0N

SD CARD

AL20
AN20

GBE LAN

SATA ODD

AK19
AM19

SPI ROM

56
56

D

2SCD01U16V2KX-3GP SATA_TXP0_C
2SCD01U16V2KX-3GP SATA_TXN0_C

C1901 1
C1902 1

SATA_TXP0
SATA_TXN0

VGA DAC

56
56

56 SATA_RXN0_C
56 SATA_RXP0_C

SERIAL ATA

1st SATA HDD

If not used HWM or GPIO, PD 10k.

R2215

R2217

Do Not Stuff
1G_512M 10KR2J-3-GP
512M_2G

GPIO171
FCH_USB3.0PORT_EN#
GPIO182
VIN_VDDR

2

1
2
3
4

2

RN1901
8
7
6
5

VRAM_SIZE1
VRAM_SIZE2

1

1

71.HUDM2.M01

SRN10KJ-6-GP

For PX use only.
RN1902
8
7
6
5

A

1
2
3
4

VIN_VDDIO
MEM_1V35
MEM_1V5
PSW_CLR#

A

DQ15 AMD DIS SAMSUNG TI

SRN10KJ-6-GP
1 R1914

2 10KR2J-3-GP

MB_THRMDA_FCH

1 R1915

2 10KR2J-3-GP

APU_TALERT#

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

1213 Modify: Remove Dimm Thermal Function
Pop R1914 If function Not used.

Reserved
Size

Document Number

Date:

Thursday, May 26, 2011

Rev

QUEEN AMD Muxless/UMA
5

4

3

2

Sheet
1

19

of

X00
104

5

4

3

2

1

1027 Modify: Errata Add

0111: Change R2019 From 100K to 0 Ohm

2

5V_S0

1207 Modify: Change From 0402 0 Ohm To 0603
1D1V_VDDCR_S0

Part 3 of 5

DY

1D1V_S0

1
VDDAN_11_CLK_B

1
2

VDDAN_11_CLK

2

1

G

33 ohm 3A

1

Q2004
Do Not Stuff

1D1V_S0

ohm 3A

1

1

1D1V_S0

1D2V_S5

2

C2033
SC10U6D3V5KX-1GP

3D3V_S5

1
VDDIO_AZ_S

2

2

12mA

AA4

26mA

1D1V_VPPL_SYS_S5
1D2V_VPPL_SYS_S5

2 Do Not Stuff

DY

3D3V_VDDAN_HWM_S5

VDDIO_AZ

1 R2010

2 Do Not Stuff

1 R2018

2 Do Not Stuff

C2049

3D3V_VDDPL_USB_S5

3D3V_S5

1
2

VDDIO_AZ

L2013

1

1 R2012

2

2 Do Not Stuff

C2061
SCD1U10V2KX-5GP

1

C2060
SC2D2U6D3V3KX-GP

Del reservaton 1D5V_S5

C2059
SC2D2U6D3V3KX-GP

2

1

1

BLM15AG221SS1D-GP

2

1

1

Codec power use3.3V,VDDIO_AZ have to tied to 3.3V
Codec power use1.5V,VDDIO_AZ have to tied to 1.5V
If use 1.5V_S5 power,have to add LDO for it extra
3D3V_USB_S5

68.00084.E21

3D3V_VDDAN_DAC_S0_R
L2018

G

Do Not Stuff

1

1
C2067
SCD1U10V2KX-5GP

USB3

R2016
Do Not Stuff

Non USB3

1

1

2
Do Not Stuff

Do Not Stuff

DY

2

C2078
Do Not Stuff

2

1

C2066
SC2D2U6D3V3KX-GP

USB3

L2020

C2071
SCD1U10V2KX-5GP

L2019
Do Not Stuff
DY
220 ohm 300mA

Do Not Stuff

C2070

DY Do Not Stuff

MOS spec VGS:20V

2

1D1V_S0

1D1V_VDDAN_MLDAC_S0

S

Rosa:RUN_Enable 15V
Annie:RUN Enable 9V

Current Limit=360mA

3.3V CRT LDO

5V_S5

3D3V_VDDAN_DAC_S0_R

Q2003

D

84.2N702.J31

U2002

S
AO3404A-GP

84.03404.B31

1122 Modify:
Add G9091 LDO circuit for CRT DAC power
to avoid monitor noise issue.

NC#4

0111: Remove R2023

5
4

1
2

2

DY

C2081
Do Not Stuff

G9091-330T11U-GP

74.09091.J3F

2nd = 74.09198.G7F
20100621 V1.2

C2080

2

SC1U10V2KX-1GP

C2079

3D3V_S0

1 R2022

VOUT

1

VGA_PD_G

VIN
GND
EN

1

G

2ND = 84.2N702.031

1
2
2 Do Not Stuff U2002_EN 3

2

2N7002K-2-GP

SC1U6D3V2KX-GP

D

1

C2072
SC2D2U6D3V3KX-GP

2

2
VGA_PD_R

1

Do Not Stuff
Do Not Stuff

68.00084.E21

If USB 3.0 wake-up is supported, tie to 3.3V_S5
If no, tie to 3.3V_S0,
If no USB 3.0, tie to GND

1D2V_VPPL_SYS_S5

S

DY

Q2001

1D2V_S5

1

Q2002

D

C2069
SCD1U10V2KX-5GP

B

HW Montior Not implemented
or HW Montior balls used as GPIO
=> Bead not used

2

3D3V_VDDAN_DAC_S0
R2014
100KR2J-1-GP

C2068
SC2D2U6D3V3KX-GP

If support USB 3.0 or LAN wake-up, tie to 1.1V_S5
otherwise, tie to 1.1V_S0

DY

1

1

2
DoDY
Not Stuff

2
BLM15AG221SS1D-GP

220 ohm 300mA

2

C2064
SCD1U10V2KX-5GP

1

C2065
SC2D2U6D3V3KX-GP

3D3V_VDDPL_SSUSB_S5

USB3
L2016
1

2

1

C2058
SCD1U10V2KX-5GP

1

C2057
SC2D2U6D3V3KX-GP

3D3V_S0

1

3D3V_S5

2
BLM15AG221SS1D-GP

2

1

220 ohm 300mA

2

68.00084.E21
2

1

C2063
SCD1U10V2KX-5GP

2

1

C2062
SC2D2U6D3V3KX-GP

2

2 Do Not Stuff

15V_S5

G

1D1V_VPPL_SYS_S5
L2017

2

Do Not Stuff

220 ohm 300mA

2

1D1V_S5

1 L2015

2
BLM15AG221SS1D-GP

1

3D3V_S5

L2012

1

220 ohm 300mA

1

3D3V_VPPL_SYS_S0

B

1

Confrim

DY

HW Montior Not implemented
or HW Montior balls not used GPIO
=> Decoupled cap not used

2

C

If support USB 3.0 or LAN wake-up, pls tie to 3.3V_S5
otherwise, tie to 3.3V_S0

3D3V_VDDAN_HWM_S5
3D3V_S0

2

DY

1 R2013

2

220 ohm 300mA

71.HUDM2.M01

Do Not Stuff

Do Not Stuff

DY

2

1D2V_S5

POWER

L2014

1

C2073
Do Not Stuff

DY

BLM15AG221SS1D-GP
C2043
68.00084.E21
SC2D2U6D3V3KX-GP

2

C2001

2

VDDCR_1D1V

1 R2021

1

70mA

C2042

DYDo Not Stuff

68.00084.E21

3D3V_VDDPL_MLDAC_S0

3D3V_VDDAN_DAC_S0_R

R2015
2K2R2J-2-GP

1

1

1

J24
M8

220 ohm 300mA
3D3V_S0

VGA_PD

DY

0120: Modify to 0402 0 Ohm

If support USB 3.0 wake-up, tie to 1.1V_S5
If no, tie to 1.1V_S0,
If no USB 3.0, tied to GND

18

C2077

220 ohm 300mA

VDDCR_11_SSUSB_S
VDDCR_11_SSUSB_S
VDDCR_11_SSUSB_S
VDDCR_11_SSUSB_S

USB3 USB3

DY

3D3V_S5
VDDXL_3.3V

2

VDDPL_11_SYS_S
VDDAN_33_HW M_S

VDDAN_11_SSUSB_S
VDDAN_11_SSUSB_S
VDDAN_11_SSUSB_S
VDDAN_11_SSUSB_S
VDDAN_11_SSUSB_S

1D2V_SET

Vout=1.0*(1+R1/R2)

1D1V_S5

VDDCR_11_S
VDDCR_11_S

VDDCR_11_USB_S
VDDCR_11_USB_S

4

SET

2

1

1

190mA

5

OUT

R2028
Do Not Stuff

C2036
SC2D2U6D3V3KX-GP

C2056

2

2

2

C2055

1

C2054

2

1

1

C2053

USB3 USB3

2

USB3

2

2

2

1

1

1

1

USB3

C2052
SC1U6D3V2KX-GP

SCD1U10V2KX-5GP

Non USB3 USB3

C2051
SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

C2050
SCD1U10V2KX-5GP

SC10U6D3V5KX-1GP

R2017
Do Not Stuff

SC1U6D3V2KX-GP

USB3

5mA

N20
M20

C2035
SC2D2U6D3V3KX-GP

2

1

1
2

2

2

N17
P17
M17

VDDCR_11_SSUSB_S

L2001 Do Not Stuff

G24

C2034

DYDo Not Stuff

IN
GND DY
SHDN#
Do Not Stuff

2

424mA N16

60mA

2

Do Not Stuff

VDDAN_1.1V_SSUSB_S

N18
L19
M18
V12
V13
Y12
Y13
W 11

1
2
3

C2075

L2009

VDDXL_33_S

VDDAN_11_USB_S
VDDAN_11_USB_S

1

2

T13

282mA P16
M14
N14
P13
P14

VDDIO_33_S
VDDIO_33_S
VDDIO_33_S
VDDIO_33_S
VDDIO_33_S
VDDIO_33_S
VDDIO_33_S
VDDIO_33_S

2

1 R2011

42mA T12

CD1U10V2KX-5GP

CD1U10V2KX-5GP

2

1
2

1

1

1

2

C2046S

2 Do Not Stuff

DY
Do Not Stuff

VDDCR_1.1V_USB
C2047S
C2048

U13

2 Do Not Stuff

SC10U6D3V5KX-1GP

2

1 L2011

1D1V_VDD_SSUSB_S5

2

140mA U12

220 ohm 300mA

1D2V_S5

1 R2001

VDDAN_1.1V_USB

VDDAN_33_USB_S
VDDAN_33_USB_S
VDDAN_33_USB_S
VDDAN_33_USB_S
VDDAN_33_USB_S
VDDAN_33_USB_S
VDDAN_33_USB_S
VDDAN_33_USB_S
VDDAN_33_USB_S
VDDAN_33_USB_S
VDDAN_33_USB_S
VDDAN_33_USB_S

SC1U6D3V2KX-GP

1D1V_S5
C2045
SCD1U10V2KX-5GP

33 ohm 3A

1

H8
J8
K8
K9
M9
M10
N9
N10
M12
N12
M11

C2041
SCD1U10V2KX-5GP

SC1U6D3V2KX-GP

C2044
SC2D2U6D3V3KX-GP

1 R2020

1D1V_S5

C2040
SC10U6D3V5KX-1GP

2

2

1

C

Do Not Stuff

2

C2039
SC10U6D3V5KX-1GP

0120: Modify to 0402 0 Ohm

220 ohm 300mA
1 L2010

1

1D1V_S5

C2038
SC1U6D3V2KX-GP

2

1

1
2

C2037
SC1U6D3V2KX-GP

USB

470mA G7

2

3.3V_S5 I/O

3D3V_S5

USB SS

1

R2027
U2001

1027 Modify: Change All 22uF To 10uF

Do Not Stuff

C2032
SC1U6D3V2KX-GP

1

C2031
SCD1U10V2KX-5GP

2

C2030
SCD1U10V2KX-5GP

1

C2029
SC1U6D3V2KX-GP

1

R2025 Do Not Stuff

3D3V_USB_S5

L2008 Do Not Stuff

2

1207 Modify: Reserve R2029 DY Co-lay

33
1D1V_SATA_S0

1

220 ohm 3A

C2074

DY Do Not Stuff
1

R2029 Do Not Stuff
C2023
SC10U6D3V5KX-1GP

2

2

2

1

C2020
SC1U6D3V2KX-GP

DY

1

3D3V_S5

S

2

R2024 Do Not Stuff

AA21 1337mA
Y20
AB21
AB22
AC22
AC21
AA20
AA18
AB20
AC19

DY

D

2

1D1V_PCIE_S0

AB24 1088mA
Y21
AE25
AD24
AB23
AA22
AF26
AG27

VDDAN_11_CLK

D

1D1V_S0

Do Not Stuff

C2015
SC10U6D3V5KX-1GP

2

1

C2014
SC1U6D3V2KX-GP

2
1

1

C2022
SCD1U10V2KX-5GP

2
1

1
2
1

C2021
SCD1U10V2KX-5GP

C2013
SCD1U10V2KX-5GP

1

1
2

1
2

1
2

1
2
1
2

C2019
SC1U6D3V2KX-GP

C2012
SCD1U10V2KX-5GP

R2019
Do Not Stuff

Do Not Stuff

VDDIO_GBE_S
VDDIO_GBE_S

C2011
SC1U6D3V2KX-GP

2

0120: Modify to 0402 0 Ohm

VDDCR_11_GBE_S
VDDCR_11_GBE_S

33 ohm 3A

1

Do Not Stuff

AA10

VDDAN_11_SATA
VDDAN_11_SATA
VDDAN_11_SATA
VDDAN_11_SATA
VDDAN_11_SATA
VDDAN_11_SATA
VDDAN_11_SATA
VDDAN_11_SATA
VDDAN_11_SATA
VDDAN_11_SATA

C2010
SCD1U10V2KX-5GP

2

AA11

VDDIO_33_GBE_S

C2009
SCD1U10V2KX-5GP

2

63mA AB11

145mAAA9

CORE S0

PCI/GPIO I/O

VDDAN_11_ML
VDDAN_11_ML
VDDAN_11_ML
VDDAN_11_ML

C2008
SC10U6D3V5KX-1GP

R2023 Do Not Stuff

1

2mA AB10

VDDAN_11_PCIE
VDDAN_11_PCIE
VDDAN_11_PCIE
VDDAN_11_PCIE
VDDAN_11_PCIE
VDDAN_11_PCIE
VDDAN_11_PCIE
VDDAN_11_PCIE

VDDPL_11_DAC

2

1D1V_CKVDD_S0

2

Y22
V23

C2028
V24
SCD1U10V2KX-5GP V25

LDO_CAP

C2007
SC1U6D3V2KX-GP

2

2

V21

340mA

1

1

1

C2027
SCD1U10V2KX-5GP

SC4D7U6D3V3KX-GP

2

C2026

C2025
SCD1U10V2KX-5GP

M31

H26
J25
K24
L22
M22
N21
N22
P22

C2006
SC1U6D3V2KX-GP

2

VDDPL_3.3V_SATA

2

LDO_CAP

1

L2006
BLM15AG221SS1D-GP
C2024
SC2D2U6D3V3KX-GP

68.00084.E21

Do Not Stuff
Do Not Stuff

2
DY
2
DY

1

1
2

220 ohm 300mA

1

1 R2006
C2018 1

1D5V_S0

1D1V_VDDAN_MLDAC_S0
1D1V_VDDAN_ML_S0
1D1V_VDDPL_DAC_S0
L2005
Do Not Stuff
1
2 1D1V_VDDAN_MLDAC 1 R2007 2
7mA
PBY160808T-330Y-N-GP
Do Not Stuff
1 R2008 2
226mA

2

1

C2017
SCD1U10V2KX-5GP

1

3D3V_S0

2

BLM15AG221SS1D-GP
C2016
SC2D2U6D3V3KX-GP

68.00084.E21

VDDAN_11_CLK
VDDAN_11_CLK
VDDAN_11_CLK
VDDAN_11_CLK
VDDAN_11_CLK
VDDAN_11_CLK
VDDAN_11_CLK
VDDAN_11_CLK

1

R2003 Do Not Stuff

2

VDDPL_3.3V_PCIE

2

2

1

VDDPL_33_SYS
VDDPL_33_DAC
VDDPL_33_ML
VDDAN_33_DAC
VDDPL_33_SSUSB_S
VDDPL_33_USB_S
VDDPL_33_PCIE
VDDPL_33_SATA

1007mA

1

3D3V_VDDAN_DAC_S0_R
3D3V_VDDPL_SSUSB_S5
3D3V_VDDPL_USB_S5

L2003

50mA H24
20mA V22
12mA U22
30mA T22
11mA L18
14mA D7
11mA AH29
12mAAG28

T14
T17
T20
U16
U18
V14
V17
V20
Y17

2

220 ohm 300mA

2Do Not Stuff VDDPL_33_DAC
2Do Not Stuff VDDPL_33_ML

2

3D3V_S0

1 R2004
1 R2005

CLKGEN I/O

3D3V_VPPL_SYS_S0
3D3V_VDDPL_MLDAC_S0

MAIN LINK

1027 Modify: Change All 22uF To 10uF
D

VDDCR_11
VDDCR_11
VDDCR_11
VDDCR_11
VDDCR_11
VDDCR_11
VDDCR_11
VDDCR_11
VDDCR_11

PCI EXPRESS

2

C2005
SCD1U10V2KX-5GP

VDDIO_33_PCIGP
VDDIO_33_PCIGP
VDDIO_33_PCIGP
VDDIO_33_PCIGP
VDDIO_33_PCIGP
VDDIO_33_PCIGP
VDDIO_33_PCIGP
VDDIO_33_PCIGP
VDDIO_33_PCIGP
VDDIO_33_PCIGP

SERIAL ATA

AB18
AE9
AD10
AG7
AC13
AB12
AB13
AB14
AB16

GBE LAN

1

1

C2004
SCD1U10V2KX-5GP

2

1

C2003
SCD1U10V2KX-5GP

2

C2002
SC10U6D3V5KX-1GP

2

1

102mA AB17

1

FCH1C

2 Do Not Stuff

2

3D3V_FCH_VDDIO_S0
R2002

1

2

3D3V_S0

R2026
10KR2J-3-GP

1

Q2005
18

VGA_PD

G
D

VGA_PD_G

A

A

S
2N7002K-2-GP

84.2N702.J31

2ND = 84.2N702.031
DQ15 AMD DIS SAMSUNG TI

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

HUDSON-M2 Power(4/6)
Document Number
Size
Custom

Rev

QUEEN AMD Muxless/UMA

Date:
5

4

3

2

Sheet

Thursday, May 26, 2011
1

20

of

X00
104

5

4

3

2

1

SSID = S.B
D

D

CRB: PU to 3.3V_AUX_S5
Checklist: PU to 3.3V_S5
Confrim with AMD, follow CRB suggestion

REQUIRED STRAPS
3D3V_S0

3D3V_S5

3D3V_AUX_S5

EC_PWM2

PCI_CLK1

LPC ROM

Allow
PCIE GEN2

DEFAULT

DEFAULT

DEFAULT

SPI ROM

Force
PCIE GEN1

S5_PLUS Mode
ENABLE

R2104

R2105
10KR2J-3-GP
2

2

2

1

1

1
R2103

R2107
10KR2J-3-GP

S5_PLUS Mode
DISABLE

PCI_CLK4

LPC_CLK0

non_Fusion
CLOCK mode

ENABLE EC

IGNORE
DEBUG
STRAPS

Fusion
CLOCK mode

DISABLE EC

DEFAULT

DEFAULT

CLK_PCI_LPC
USE
DEBUG
STRAPS

LPC_CLK1
CLKGEN
ENABLED
(Use Internal)
DEFAULT

PULL
LOW

17 PCI_CLK1
17,71 CLK_PCI_LPC
17 PCI_CLK4

C

PULL
HIGH

RTC_CLK

2

R2101

DYDo Not Stuff DYDo Not Stuff DYDo Not Stuff
2

2

1

1

1

PCH GPO199
R2102
10KR2J-3-GP

Use this pin to determine INT/EXT CLK

REQUIRED SYSTEM STRAPS

CLKGEN
DISABLED

DEFAULT

(Use External)

C

17,27 LPC_CLK0
17 LPC_CLK1

No Fusion Config, Strap Not needed, but reserve

1

1
R2117

R2118

DYDo Not Stuff DYDo Not Stuff
2

1
R2116
10KR2J-3-GP

2

2

2

R2115
10KR2J-3-GP
2

R2114
10KR2J-3-GP

DY Do Not Stuff

2

R2113

1

1

1

18 EC_PWM2
17 RTC_CLK

DEBUG STRAPS
B

B

17
17
17
17
17

PULL
HIGH

1 R2112

1 R2111

1 R2110

1 R2109

1 R2108

PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27

PULL
LOW

2

PCI_AD26

PCI_AD25

PCI_AD24

Disable ILA
AUTORUN

USE FC
PLL

USE DEFAULT
PCIE STRAPS Disable PCI
MEM BOOT

PCI_AD23

(DEFAULT)

(DEFAULT)

(DEFAULT)

(DEFAULT)

(DEFAULT)

BYPASS
PCI PLL

Enable ILA
AUTORUN

BYPASS FC
PLL

USE EEPROM
PCIE STRAPS

Enable PCI
MEM BOOT

2
Do Not Stuff

Do Not Stuff

2

2
Do Not Stuff

Do Not Stuff

Do Not Stuff

2

DYDYDYDYDY

PCI_AD27
USE PCI
PLL

Note: FCH has 15K internal PU FOR PCI_AD[27:23]

DQ15 AMD DIS SAMSUNG TI

A

A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

5

4

3

2

SB820M_STRAPPING_(5/5)

Size
A3

Document Number

Date:

Thursday, May 26, 2011

Rev

QUEEN AMD Muxless/UMA
Sheet
1

21

of

X00
104

5

4

3

FCH1D

D

C

B

N8
K25
H25

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

1

Part 4 of 5

GROUND

A3
A33
B7
B13
D9
D13
E5
E12
E16
E29
F7
F9
F11
F13
F16
F17
F19
F23
F25
F29
G6
G16
G32
H12
H15
H29
J6
J9
J10
J13
J28
J32
K7
K16
K27
K28
L6
L12
L13
L15
L16
L21
M13
M16
M21
M25
N6
N11
N13
N23
N24
P12
P18
P20
P21
P31
P33
R4
R11
R25
R28
T11
T16
T18

2

VSSAN_HWM
VSSXL

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSSPL_DAC
VSSAN_DAC
VSSANQ_DAC
VSSIO_DAC

VSSPL_SYS
EFUSE

T25
T27
U6
U14
U17
U20
U21
U30
U32
V11
V16
V18
W4
W6
W25
W28
Y14
Y16
Y18
AA6
AA12
AA13
AA14
AA16
AA17
AA25
AA28
AA30
AA32
AB25
AC6
AC18
AC28
AD27
AE6
AE15
AE21
AE28
AF8
AF12
AF16
AF33
AG30
AG32
AH5
AH11
AH18
AH19
AH21
AH23
AH25
AH27
AJ18
AJ28
AJ29
AK21
AK25
AL18
AM21
AM25
AN1
AN18
AN28
AN33

D

C

B

T21
L28
K33
N28
R6

71.HUDM2.M01

DQ15 AMD DIS SAMSUNG TI

A

A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

5

4

3

2

Size
A3

Document Number

Date:

Thursday, May 26, 2011

Reserved

Rev

QUEEN AMD Muxless/UMAX00
Sheet
1

22

of

104

5

4

3

2

1

D

D

C

C

B

B

A

A

DQ15 AMD DIS SAMSUNG TI

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

5

4

3

2

Size
A3

Document Number

Date:

Thursday, May 26, 2011

Reserved

Rev

QUEEN AMD Muxless/UMAX00
Sheet
1

23

of

104

5

4

3

2

1

D

D

C

C

B

B

DQ15 AMD DIS SAMSUNG TI

A

A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

5

4

3

2

Size
A3

Document Number

Date:

Thursday, May 26, 2011

Reserved

Rev

QUEEN AMD Muxless/UMAX00
Sheet
1

24

of

104

5

4

3

2

1

D

D

C

C

B

B

A

A

DQ15 AMD DIS SAMSUNG TI

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

5

4

3

2

Size
A3

Document Number

Date:

Thursday, May 26, 2011

Reserved

Rev

QUEEN AMD Muxless/UMAX00
Sheet
1

25

of

104

5

4

3

2

1

D

D

C

C

B

B

DQ15 AMD DIS SAMSUNG TI

A

A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

5

4

3

2

Size
A3

Document Number

Date:

Thursday, May 26, 2011

Reserved

Rev

QUEEN AMD Muxless/UMAX00
Sheet
1

26

of

104

5

4

3

2

0107: Change R2724 & R2726 from 5 % To 1 & Resistor tolerence.

1

0107: Update Model_ID_DET
Table,
DQ15_AMD_UMA
DQ15_AMD_DIS (PX)
DN15_AMD_DIS (PX)

0107: POP C2718, R2739, Change To Voltage Divider
** BOM Control For R2710 Value.
Default R2710 10K = DQ15_UMA

3D3V_AUX_KBC

VOLTAGE

100.0K

20.0K

2.75V

MODEL_ID_DET(GPIO07)

-1

33.0K

2.48V

100.0K

47.0K

2.24V

Reserved

100.0K

64.9K

2.0V

Reserved

100.0K

76.8

1.87V

Reserved

100.0K

100.0K

1.65V

MODEL_ID_DET

C2718
SCD1U10V2KX-5GP

SSID = KBC

R2741
Do Not Stuff

MODELID

R2739
100KR2F-L1-GP
2

2

1

100.0K

R2740
20KR2F-L-GP

MODELID

1

R2726
100KR2F-L1-GP

DY

Do Not Stuff

SC

2

C2717

1

2

PCB_VER_AD

R2710
Do Not Stuff

MODELID

1

SB

EC_AGND
EC_AGND

D

0702 Modify:
Defualt un-stuff R2739(internal PL in KBC)

0628 Modify:
Move R2771 to closed 3D3V_AUX_KBC power
rail base on layout placement.

3D3V_AUX_KBC

2.75V

DQ15_NVIDIA

100.0K

33.0K

2.48V

DN15_UMA

100.0K

47.0K(64.47025.6DL)

2.24V

DN15_ATI

100.0K

64.9K(64.64925.6DL)

2.0V

Reserved

100.0K

76.8K

1.87V

Reserved

100.0K

100.0K

1.65V

DN13_UMA

100.0K

143.0K

1.358V

DN13_ATI

100.0K

174.0K

1.204V

DQ15_Ventura

100.0K

215.0K

1.048V

1

C2703

2

DY Do Not Stuff

PSL_IN2
MODEL_ID_DET

0629 Modify:
Rename TP_LOCK_LED#&BATT_WHITE_LED# 68 BATT_WHITE_LED#

ECSMI#_KBC

69 CAP_LED
36 S5_ENABLE
82 MEDIA_BTN3#
39 BAT_IN#
70 LID_CLOSE#
18 RSMRST#_KBC
18,44,75 PM_SLP_S5#
60 EC_SPI_WP#
82 RCID

PSL_IN1
PSL_OUT
EC_GPIO72

82 WIFI_RF_EN
63,82 BLUETOOTH_EN
36,46 1D1V_S5_PWRGD
68 TP_LOCK_LED#
57 USB_PWR_EN#
85 THERMTRIP_VGA_GATE
0719: ADD 36,46 1D2V_S0_PWRGD
0604 Modify:
RN2704 pull-Low 10K Resistor to DY
on BLUETOOTH_EN.

1

KBC_VCORF
C2712
SC1U25V3KX-1-GP

102

4
VDD

AVCC

EC_AGND

1122 Modify:
Change To X5R Cap

1 R2736
1 R2719
1 R2737
1 R2722

SPI_CS0#_R 60
SPI_CLK_R 60
SPI_SO_R 60
SPI_SI_R 60

PSL_IN2

R2732
100KR2J-1-GP

ECSWI#_KBC

3

2ND = 84.2N702.031

6,40

Q2701
MMBT3906-4-GP

B

28,36 PURE_HW_SHUTDOWN#

D2705
18

PSL Solution

ECSCI#_KBC

3

EC_SWI#

1 R2758 2ECSWI#_KBC
Do Not Stuff

18

EC_SCI#

1 R2759 2ECSCI#_KBC
Do Not Stuff

1

3

R2756
2
Do Not Stuff

EC_GPIO72

BAS16-6-GP

1 R2734

PSL_IN1

BAT_IN#
AC_IN#_KBC

EC_ENABLE#_1

S

D
3D3V_AUX_KBC

84.2N702.J31

2ND = 84.2N702.031
KBC_ON#

2ND = 84.2N702.031

1 R2766 2
Do Not Stuff

SRN100KJ-6-GP

0628 Modify:
Stuff R2712 and Removed R2805.

PSL_OUT

FAN_TACH1

1 R2712

E51_RxD

1 R2708

2 Do Not Stuff
DY

BLUETOOTH_EN

1 R2709

2 Do Not Stuff
DY

3D3V_S0
28

FAN_TACH1

PSL

R2769
Do Not Stuff

0604 Modify:
RN2704 pull-Low 10K Resistor to DY
on BLUETOOTH_EN.

0625 Modify:
Change R2769 dummy column for PSL solution.

0623 Modify:
Change RN2704 to R2708 10K 0402
Resistor on BLUETOOTH_EN.

1

D

3

DN15

USBDET_CON#

MEDIA_BTN1#

Do Not Stuff
2ND = 83.00054.Q81
2

S5_ENABLE
ECRST#

DY

BAT54CPT-GP
USB_DET#

1 R2713

2 10KR2J-3-GP

Q2706

Do Not Stuff

2ND = 84.2N702.031

0628 Modify:
Stuff R2712 and Removed R2805.

KBC_ON#_R

D2706

1
57 USBDET_CON#

S

0928 Modify:
Add Q2706 2N7002 to avoid leakage loop from
3D3V_S5 to 3D3V_AUX_KBC issue when 10mW
latched fail timing.

A

83.R2003.E81
2ND = 83.00054.Q81

3

2

KBC_ON#_R

D2707

PWR_CHG_ACOK

0109: EMI Reserve, Place Near R2768
1MEDIA_BTN2#
82 DATA_RECOVERY#

DQ15 AMD DIS SAMSUNG TI

2

BAT54CPT-GP

EC2701

DY

Wistron Corporation

1

DATA_RECOVERY#3

83.R2003.E81
2ND = 83.00054.Q81
2

KBC_ON#_R

D2708

Do Not Stuff

A

INSTANT_ON#

3D3V_AUX_KBC

G

0109: Follow Intel, Need Confirm DQ/DN Spec

2
0R2J-2-GP
Do Not Stuff

DQ15

0712 Modify:
Add D2706 connect to MEDIA
BUTTON Instant_on#.
0713 Modify:
Add R2772,D2707 for USBCHARGER
DETECT Function.

2 10KR2J-3-GP

PSL_IN1

Do Not Stuff
R2757
1

1
2

DY

0623 Modify:
Change RN2702 to R2712 10K 0402
Resistor on FAN_TACH1.

KBC_ON#_R

10mW

2

2
1

4
3

Do Not Stuff

2N7002K-2-GP

1

1

EC_ENABLE#_1
S5_ENABLE

KBC_ON#

10mW

D

Do Not Stuff

84.02130.031
2ND = 84.03413.A31

S

2
1
SRN100KJ-6-GP
RN2705

D

G

3
4

0630 Modify:
Removed LID_CLOSE#
PH 10K on RN2705.

G

2

DY
C2713

2
1

RN2703

PSL_IN1

10mW

PSL

Do Not Stuff

3
4

PSL_IN1

2
Do Not Stuff

3D3V_AUX_KBC

Do Not Stuff

D

3D3V_AUX_KBC

RN2704

KBC_ON#_R

S

Q2703
DMP2130L-7-GP

G
SRN10KJ-5-GP

B

RN2701
BAT_SDA
BAT_SCL

VBACKUP

Q2705
PSL_OUT

SCD1U10V2KX-5GP
G

3D3V_AUX_KBC

EC_GPIO72

Q2704

C2722
1
2

KBC_ON#_GATE

AC_IN#_KBC 1

0702 Modify:
Rename EC_GPIO70 to PSL_IN1

0702 Modify:
Rename EC_GPIO71 to PSL_OUT

2
1

2 Do Not Stuff

2ECSMI#_KBC
Do Not Stuff

R2763

2 Do Not Stuff

PSL

3D3V_AUX_S5

RN2706

DY

SRN4K7J-8-GP

0909 Modify:
De-Pop C2713 &
Add C2722 Soft Start To Solve Leakage Issue.

3
4

1 R2760

EC_SMI#

EC GPIO standard PH/PL
DY

1 R2767
DY2 Do Not Stuff

KBC_ON#_R

ECSMI#_KBC

2

10mW Solution
3D3V_AUX_KBC

1 R2768

40 PWR_CHG_ACOK

3D3V_AUX_S5

0716: Modify
0111: Pop D2705, DY R2760

1

EC_SMI#

DY

84.T3906.A11
2nd = 84.03906.F11

18

18

40

83.R2003.E81
2ND = 83.00054.Q81

3
4

H_PROCHOT#

RTC_AUX_S5

BAT54CPT-GP

MEDIA_BTN3#
MEDIA_BTN1#

69

83.00016.K11
2ND = 83.00016.F11

84.2N702.J31

1

3D3V_AUX_KBC

2100KR2J-1-GP

2
Do Not Stuff

C2715
Do Not Stuff

2N7002K-2-GP

2ND = 83.00016.F11

2ND = 83.00016.F11

D2703

1 R2776

1

0621 Modify:
Removed R2723

Do Not Stuff

2

PCIE_WAKE#

KROW[0..7]

ECRST#

1
R2733
H_PROCHOT#_EC

D

0714 Modify:
Un-stuff D2701,D2704 and Add R2758,R2759
ohm confirm with NUVOTON and SW.

83.R2003.E81
2ND = 83.00054.Q81

2100KR2J-1-GP

KROW0
KROW1
KROW2
KROW3
KROW4
KROW5
KROW6
KROW7

C

0716: Rename

NPCE795PA0DX-GP-U

S

Do Not Stuff

2100KR2J-1-GP

PECI
VTT

54
55
56
57
58
59
60
61

69

R2705
10KR2J-3-GP

Do Not Stuff

DY

KBC_ON#

BAT54CPT-GP

1 R2774

13
12

KCOL0
KCOL1
KCOL2
KCOL3
KCOL4
KCOL5
KCOL6
KCOL7
KCOL8
KCOL9
KCOL10
KCOL11
KCOL12
KCOL13
KCOL14
KCOL15
KCOL16
USB_DET#

1027 Modify:
Change R2075 PU From 3D3V_AUX_S5 to 3D3V_AUX_KBC

G

2

3

1 R2772

R2773
100KR2J-1-GP

1

EC_SCI#

EC_GPIO72

AC_IN#

KBSIN0
KBSIN1
KBSIN2
KBSIN3
KBSIN4
KBSIN5
KBSIN6
KBSIN7

GPIO55/CLKOUT
GPIO00/EXTCLK

53
52
51
50
49
48
47
43
42
41
40
39
38
37
36
35
34
33

0604 Modify:
Add Pull down 100k ohm at F_SDI for Power consumption concern.

1
PROCHOT_EC

DY

D2702

3

GPIO87/SIN_CR
GPO83/SOUT_CR/TRIST#

30
77
For Intel Only

D2704
18

10mW

VCC_POR#

113
111

KCOL[0..16]

KBSOUT0/JENK#
KBSOUT1/TCK
KBSOUT2/TMS
KBSOUT3/TDI
KBSOUT4/JEN0#
KBSOUT5/TDO
KBSOUT6/RDY#
KBSOUT7
KBSOUT8
KBSOUT9/SDP_VIS#
KBSOUT10/P80_CLK
KBSOUT11/P80_DAT
KBSOUT12/GPIO64
KBSOUT13/GPIO63
KBSOUT14/GPIO62
KBSOUT15/GPIO61/XOR_OUT
GPIO60/KBSOUT16
GPIO57/KBSOUT17

GPIO15/A_PWM
GPIO21/B_PWM
GPIO13/C_PWM
GPIO32/D_PWM
GPIO66/G_PWM
GPIO33/H_PWM
GPIO45/E_PWM
GPIO40/F_PWM

85

29 AMP_MUTE#
17 PCH_SUSCLK_KBC

EC_SPI_DI_C

2

2 330KR2J-L1-GP

ECRST#

82 E51_RxD
82 E51_TxD

2 33R2J-2-GP
2 33R2J-2-GP
2 Do Not Stuff
2 33R2J-2-GP

EC_GPIO47 High Active

Do Not Stuff

MEDIA_BTN2#

0629 Modify:Modify KBC GPIO66 From MEDIA_LED2# To AD_IA_HW
Rename PWRLED#&PWR_BTN_LED#&CHARGE_LED#

49

2 OF 2

GPIO56/TA1
GPIO20/TA2
GPIO14/TB1
GPIO01/TB2

32
118
62
65
81
66
22
16

CHG_AMBER_LED#
KBC_BEEP
MEDIA_LED1#
KB_BL_CTRL
AD_IA_HW
MEDIA_LED3#
MEDIA_LED2#
PWRLED#

2

1

EC_SWI#

0702 Modify:
Rename EC_GPIO6 to PSL_IN2

USB_DET#

68
29
82
69
40
82
82
68

0914: Modify GPIO Pin
Modify KBC GPIO45 From PWR_BTN_LED# To MEDIA_LED2#

LCD_TST_EN

U2701B

2

18

R2761
2 PANEL_BLEN
Do Not Stuff

AC_IN#_KBC

0716: Rename, ADD PCH_WAKE# To FCH
<-- TP

Layout Note:
Connect GND and AGND planes via either
0R resistor or one point layout connection.

D2701

DY1

2

69
69

Q2702

EC_AGND

68 KBC_PWRBTN#

TPDATA
TPCLK

0106 Modify:
Update U2701A, U2701B Symbol

31
117
63
64

28 FAN_TACH1
18 PM_PWRBTN#
75,82 PCIE_WAKE#
18,36,44,46,75 PM_SLP_S3#

<-- Use For Lan Wake Up, Need SW Confirm

0106 Modify:
Update U2701A, U2701B Symbol

EC_AGND

1
DY
Do Not Stuff

1 R2704

49
40
18

0706 Modify:
KBC GPIO13 change to MEDIA_LED1#.
KBC GPIO66 change to MEDIA_LED2#.
KBC GPIO33 change to MEDIA_LED3#.

0107 Modify: Add AD_IA_HW2 GPIO For Charger

Layout Note:
Locate resistors R2719 and R2722 close to the KBC.

1
DY
Do Not Stuff

1

BLON_OUT
AD_IA_HW2
PCH_WAKE#

0702 Modify:
Rename CHARGE_LED# to CHG_AMBER_LED#
Rename DC_BATFULL# to BATT_WHITE_LED#.

E

C2720
USB_IO_CRT_EN#
2
C2721
SYS_THRM
2

6,19

18
18

3D3V_AUX_KBC
1 R2711
Do Not Stuff

Do Not Stuff
2

EC_ENABLE#_1
PROCHOT_EC

EC_SPI_CS#_C
EC_SPI_CLK_C
EC_SPI_DI_C
EC_SPI_DO_C

<-- Rename Netname For AMD
<-- Need To Align With Intel Netname?

BAT_SCL 39,40
<-- BATTERY / CHARGER
BAT_SDA 39,40
SML1_CLK 6,85
<-- CPU -Temp
SML1_DATA 6,85
PM_LAN_ENABLE 82

1

1

C2719
CPU_THRM

MEDIA_BTN1#

2

2

0719 Modify:
Reserved 0.1uF on all of ADC input pins base on
NUVOTON feedback list.(C2717~C2721)

EC2702

AD_IA_HW2

90
92
86
87

F_CS0#
F_SCK
F_SDI/F_SDIO1
F_SDIO/F_SDIO0

RSMRST#_KBC

DY Do Not Stuff

H_A20GATE
H_RCIN#

70
69
67
68
119
120
24
28

GPIO17/SCL1
GPIO22/SDA1
GPIO73/SCL2
GPIO74/SDA2
GPIO23/SCL3
GPIO31/SDA3
GPIO47/SCL4
GPIO53/SDA4

PCH_TEMP_ALERT#

ECSWI#_KBC

27
25
11
10
71
72

GPIO52/PSDAT3/RDY#
GPIO50/PSCLK3/TDO
GPIO27/PSDAT2
GPIO26/PSCLK2
GPIO35/PSDAT1
GPIO37/PSCLK1

18
45
78
89
116
5

NPCE795PA0DX-GP-U

0109: EMI Reserve, Place Near R2768

PANEL_BLEN
ECSCI#_KBC

VCORF

2

0706 Modify:
KBC GPIO7 change to DISCRETE#
KBC GPIO97 change to IMVP_PWRGD.

44

GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO16
GPIO24
GPIO30
GPIO34
GPIO36
GPIO41
GPIO42/TCK
GPIO43/TMS
GPIO44/TDI
GPIO46/TRST#
GPIO51
GPIO70
GPIO71
GPIO72
GPIO75
GPO76/SHBM
GPIO77
GPIO81
GPO82/TEST#
GPO84/XORTR#
GPIO97

A_RST#
17,36
LPC_CLK0
17,21
LPC_FRAME# 17,71
LPC_AD3 17,71
LPC_AD2 17,71
LPC_AD1 17,71
LPC_AD0 17,71
INT_SERIRQ
17
PM_CLKRUN# 17

C

0702 Modify:
Rename EC_GPIO70 to PSL_IN1
Rename EC_GPIO71 to PSL_OUT

EC_SPI_WP#

GPIO94/DA0
GPIO95/DA1
GPIO96/DA2

2Do Not Stuff

1 R2735 2
Do Not Stuff

LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0

2

Rename PM_SLP_S4# To PM_SLP_S5#

79
95
96
108
93
94
114
6
109
14
15
80
17
20
21
23
26
73
74
75
82
83
84
91
110
112
107

C2711 1
DY
PLT_RST#_EC

7
2
3
1
128
127
126
125
8
9
29
124
123
121
122

1

0702 Modify:
Rename EC_GPIO6 to PSL_IN2

101
105
106

MEDIA_BTN2#

57 USBCHARGER_CB0
57,82 USB_IO_CRT_EN#
28 SYS_THRM

GPIO90/AD0
GPIO91/AD1
GPIO92/AD2
GPIO93/AD3

2

97
98
99
100

AGND

Do Not Stuff
PCB_VER_AD

1 OF 2

LRESET#
LCLK
LFRAME#
LAD3
LAD2
LAD1
LAD0
SERIRQ
GPIO11/CLKRUN#
GPIO65/SMI#
ECSCI#/GPIO54
GPIO10/LPCPD#
GPIO67/PWUREQ#
GPIO85/GA20
KBRST#/GPIO86

GND
GND
GND
GND
GND
GND

DY2

VREF

103

1

1

1

1

C2714 1

19
46
76
88
115
VCC
VCC
VCC
VCC
VCC

U2701A

104

28 FAN1_DAC
49 LCD_TST
0107: Modify:
Remove ESATA_PWR_EN# In GPIO2
Add GPIO04 To USB_IO_CRT_EN#

INSTANT_ON#

D

1
2

2

2

CD1U10V2KX-5GP

EC_AGND

82 PSID_EC
28 CPU_THRM

82

3.0V

C2710S

C2D2U10V3KX-1GP

2

1

C2709S

CD1U10V2KX-5GP

2

C2708S

CD1U10V2KX-5GP

o Not Stuff

2

C2707S

CD1U10V2KX-5GP

DY

2

C2706S

EC_AGND

B

C2702
SCD1U10V2KX-5GP

2

2

1

C2705D

CD1U10V2KX-5GP

C2D2U10V3KX-1GP

2

1

C2704S

40 AD_IA

1

20.0K(64.20025.6DL)

3D3V_AUX_KBC_VCC

C2701S

L_BKLT_EN

VOLTAGE

10.0K(64.10025.6DL)

100.0K

VBAT
1

1

1 R2702 2
Do Not Stuff

0716: Vendor Suggestion

9

PULL-HIGH RESISTOR

100.0K

DQ15_ATI

3D3V_S0

R2771
2D2R3-1-U-GP

C

PULL-LOW RESISTOR

DQ15_UMA

2

3.0V

1

10.0K

2

PULL-HIGH RESISTOR

1

100.0K

2

PULL-LOW RESISTOR

SA

1

PCB VERSION A/D(PIN98)

2

1

3D3V_AUX_KBC
R2724
47KR2F-GP

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

KBC Nuvoton NPCE795

Size
Document Number
Custom

QUEEN AMD Muxless/UMA

Date:
5

4

3

2

Thursday, May 26, 2011
1

Sheet

27

of

Rev

X00
104

3

2

3D3V_S0

U2802
R2802
1
R2805
Do Not Stuff

For linear FAN
DY

5V_S0

G991P11U-GP

74.00991.031
2nd = 74.02793.A31
3rd = 74.05606.071

R2829

C2816
DY Do Not Stuff
2

Do Not Stuff
DY
Hysterisis:
10°C for HYST = V CC
2°C for HYST = GND

0819 X01 Modify:
Re-assign FAN1 pin define from Niki suggestion.
Pin1 : VCC;Pin2 : Ground;Pin3 : TACH
0823 X01 Modify:
Change U2802 Main source to 74.00991.031
2nd 74.02793.A31,3rd 74.05606.071
0831 X01 Modify:
Change FAN1 to 20.F0772.003 from 20.F1639.004
base on ME Double updated.

0921:Modify
Add AFTP, Follow DQ15 Intel
AFTP2801

1FAN_TACH1_C

AFTP2802

1FAN_VCC

C2803 C2804

D

SYS_THRM 27
CPU_THRM 27
ADJ

0906: Follow DQ15 Intel, Modify Fan1 Connector, Pin Define Changed
1122: Add 2nd 20.F1841.003 on FAN1 from ME updated connector list.
0105: Update DQ15 AMD Fan1 Connector To 4 Pin P/N 20.F1621.004, AMD Different To Intel

0117 Modify:
Vendor Suggest, But will reserve first only, Place Near KBC is OK

P2800EB0-GP

1.H/W T8 Shutdown

6

27

1 R2807

4
3
2

FAN_TACH1_C

2 Do Not Stuff

3D3V_S0

FAN_VCC

D
1

27,36 PURE_HW_SHUTDOWN#

G

1

2

Do Not Stuff

2

DY R2818

C2811
DY Do Not Stuff

Q2805_G

1 R2810

1
5

2 Do Not Stuff

3D3V_S0

2N7002K-2-GP

EC2801

84.2N702.J31

DY

1

ACES-CON4-17-GP-U

1

CH551H-30PT-GP
2

THERM_SYS_SHDN#

S

2

2ND = 83.BAT54.D81
3rd = 83.BAT54.S81

FAN_VCC

DY C2810
1

EMI/ESD

Q2805

D2802
C2809

83.R5003.C8F
2ND = 83.R5003.H8H

3rd = 83.5R003.08F

20.F1621.004
Do Not Stuff

2

1

C2808

SC4D7U6D3V3KX-GP

R2831
100KR2J-1-GP

DY Do Not Stuff
C

*Layout* 15 mil

2 Do Not Stuff

2

THERM_SYS_SHDN#_OTZ 1 R2806
D2801
Do Not Stuff

20.F1561.004

C

DY
Do Not Stuff
2

2ND = 84.2N702.031
1122 Modify: AddR2806

B

FAN_TACH1

3D3V_AUX_S5

3

1

R2814
470KR2J-2-GP

1

CPU_THRM
R2812
470KR2J-2-GP

2

2

FAN2
SYS_THRM

0906 X01 Modify:
Change U2801,U2803 to 74.02800.A71 from
74.02800.071 from vender updated parts.
Change R2803&R2817 to 107K from 499K,
R2804&R2818 to 226K from 102K base on
updated ADJ Table.

Do Not Stuff
2

TDR
TDL
GND
ADJ

8
7
6
5

1

G709_HYSY

GND
GND
GND
GND

1

G709_VCC

4

FON#
VIN
VO
VSET

2

2
5

1
2
3
4

FAN_VCC

2

VCC
DXP
DXN
OTZ

4
3
2
1

1

1
2

P2800_DXN

2.System Sensor, Put on palm rest

VCC
HYST

1027 Modify: Add Extra T8 Incase P2800 Don't Work Properly
1122 Modify: Add R2829 0 Ohm To GND, DY R2828 Change Power
rail to 3D3V_S0, Change R2805 Power Rail From 3D3V_S0 To 3D3V_DAC_S0,
Change R2801 Resistor Value From 18K to 24.3K.
0115: Use P2800EB0 As Pure Hardware Shutdown, DY R2820, Pop R2806

U2801
5
C2807
6
SC2200P50V2KX-2GP
7
THERM_SYS_SHDN#_OTZ
8

DY

Do Not Stuff

1

1
PMBS3904-1-GP
2

Q2801

2

3

1
2

DY
R2808
Do Not Stuff

C2806
SC470P50V3JN-2GP

SET
GND
OUT#

Do Not Stuff

0105 Modify:
Change P2800 To EB0 Version

P2800_DXP

1
2
3

G709_OUT#

1

2

DYC2805

Layout notice :
Both DXN and DXP routing 10 mil
trace width and 10 mil spacing.

2ND = 84.03904.P11
84.03904.L06

G709_SET

DY

Do Not Stuff
2
1

R2804
DY
Do Not Stuff

2
R2820
Do Not Stuff

FON#
DY Do2 Not Stuff

*Layout* 10 mil

2

1

SCD1U10V2KX-5GP

2

THERM_SYS_SHDN# 1

FAN1_DAC

1

87.1 Degree

ADJ

D

U2804

2

C2802

R2801
Do Not Stuff
1 DY
2

27

1

1

2 Do Not Stuff

1

1 R2813

1
5V_S0

R2828

DYDo Not Stuff

2

R2811
Do Not Stuff

1

DY

1

2

0112: Remove R2811 ADJ 3D3V_AUX_KBC Pull High

3D3V_S0

1

Fan controller P2793

3D3V_S0

RSET = 0.0012T 2 — 0.9308T + 96.147
T=87 ; RSET=24.25ohm

SC4D7U6D3V3KX-GP

4

3D3V_S0

SCD1U10V2KX-5GP

5

1122 Modify:
ADJ&ADJ_VGA power source change to 3D3V_DAC_S0
from 3D3V_S0 to solve T8 shut down issue.
1123 Modify:
Co-lay 3D3V_DAC_S0 & 3D3V_S0 In Case LDO is Not Used

B

1213 Modify: Remove Dimm Thermal Function

0107: Remove VGA P2800, SW Does Not Use

A

A

DQ15 AMD DIS SAMSUNG TI

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

Thermal/Fan Controllor EMC2102

Document Number
Size
Custom

QUEEN AMD Muxless/UMA

Date: Friday, May 27, 2011
5

4

3

2

Sheet
1

28

of

Rev

X00
104

5

4

3

2

1

SSID = AUDIO

ANNIE Audio solution

0913 X01 Modify:
Add R2920,R2921 and reserved EC2901,EC2902 on
AUD_DMIC_CLK &AUD_DMIC_IN0 for EMC suggestion.
0105 Modify:
EMI Request R2920, R2921 Place Near LCD1 Connector.
Move EC2901 EC2902 to P.49 and place after R2920, R2921

、

0105 Modify:
Vendor Suggest To Change R2920 To 33 Ohm

D

D

For EMI

THERMAL_PAD
EAPD
PVDD
PORTD_+R
PORTD_-R
PVSS
PORTD_-L
PORTD_+L
PVDD
AVDD2
VREG/+2_5V

0707 Modify:
updated U2901 part number from data base.

92HD87B1A5NDGXTBX8-GP

AUD_SENSE_A
AUD_SENSE_B

2010/06/30 Change to 92HD87 (71.92H87.A03)

3D3V_S0

1

1
2

2

C2910
SC10U6D3V5MX-3GP

2

1

C2909
SC1U10V2KX-1GP

1

C2906
SC1U10V2KX-1GP

2

2

PUMP_CAPP

CAP+
CAPVAVSS2
PORTB_R
PORTB_L
AVSS2
PORTA_R
PORTA_L
AVDD1

30
29
28
27
26
25
24
23
22
21

CLOSE TO CODEC

C2914
SC2D2U10V3KX-1GP

1

DVDD_LV
DMIC_CLK/GPIO_1
DMIC_0/GPIO_2
SDATA_OUT
BITCLK
SDATA_IN
DVDD
71.92H87.A03
SYNC
RESET#
PCBEEP

2

2
HDA_CODEC_SYNC
HDA_CODEC_RST#
AUD_PC_BEEP

1
2
3
4
5
6
7
8
9
10

1

AUD_VREG

HDA_CODEC_SDOUT
HDA_CODEC_BITCLK
2 HDA_CODEC_SDIN0

1

R2904 Do Not Stuff

AUD_AGND

PUMP_CAPN
AUD_V_B
AUD_HP1_JACK_R
AUD_HP1_JACK_L

R2906
R2905

AUD_EXT_MIC_R
AUD_EXT_MIC_L

2 60D4R2F-GP
2 60D4R2F-GP

1
1

C2922
C2921

2
2

AUD_HP1_JACK_R2
AUD_HP1_JACK_L2
AUD_AGND
MIC_IN_R 82
MIC_IN_L 82

1 SC1U10V3KX-3GP
1 SC1U10V3KX-3GP

82
82

+AVDD

SENSE_A
SENSE_B
PORTF_L
PORTF_R
PORTC_L
PORTC_R
VREFFILT
CAP2
VREFOUT_A
VREFOUT_C

222R2J-2-GP AUD_DMIC_CLK_R
222R2J-2-GP AUD_DMIC_IN0_R

R2903 Do Not Stuff

2

R2902 Do Not Stuff

Put C2921 and C2922 close to codec

C

11
12
13
14
15
16
17
18
19
20

2

2

1

1R2901
33R2J-2-GP

18 HDA_CODEC_SYNC
18 HDA_CODEC_RST#

C2902
SCD1U10V2KX-5GP

1

1

2

C2903
SC1U6D3V2KX-GP

C2904
SCD1U10V2KX-5GP

C

1
1 R2921

2

AUD_AGND

AUD_VREFFLT
AUD_CAP2
AUD_VREFOUT_B

2

1

U2901
C2901
SC10U6D3V5MX-3GP

0625 Modify:
AUD_DMIC_CLK&AUD_DMIC_IN0 connector
to LVDS pin define.
R2920
49 AUD_DMIC_CLK
49 AUD_DMIC_IN0
18 HDA_CODEC_SDOUT
18 HDA_CODEC_BITCLK
18 HDA_SDIN0

Close to codec

1

AUD_AGND

41
40
39
38
37
36
35
34
33
32
31

AUD_DVDDCORE

5V_S0

1

+AVDD

AUD_PC_BEEP

0304 Modify:
EMI Suggest To Pop EC2901, EC2902 22P

+PVDD

+AVDD

C2908
SCD1U10V2KX-5GP

+PVDD

AMP_MUTE#

AMP_MUTE#

AUD_SPK_R+ 58
AUD_SPK_R- 58
AUD_SPK_L- 58
AUD_SPK_L+ 58

C2905
SCD1U10V2KX-5GP

27

EC2902
SC22P50V2JN-4GP

Close to codec

3D3V_S0

5V_S0

AUD_SPK_R+
AUD_SPK_RAUD_SPK_LAUD_SPK_L+

1
2

EC2901
SC22P50V2JN-4GP

2

1

AUD_DMIC_CLK
AUD_DMIC_IN0

AUD_CAP2

1

AUD_VREFFLT
R2908
10KR2J-3-GP

Remove Annie Audio

AUD_V_B

1

1
2

2

AUD_PC_BEEP
Trace width>15 mils

C2907
Do Not Stuff

2

1 SCD1U10V2KX-5GP

SB_SPKR_R

C2913

2

1 SCD1U10V2KX-5GP

KBC_BEEP_R

1

2

1

2

R2910
470KR2J-2-GP

HDA_SPKR

18

KBC_BEEP

27

AUD_AGND

From EC

1

1

AUD_AGND

2

1

AUD_AGND

2

From SB

C2916
SC1U6D3V2KX-GP

C2912

C2915
SC10U6D3V5MX-3GP

AUD_PC_BEEP

DY

2

HDA_CODEC_BITCLK

C2923
SC1U10V2KX-1GP

2

120KR2J-L-GP
R2909

C2918
SC10U6D3V5MX-3GP

1

AUD_VREFOUT_B

C2917
SC4D7U6D3V3KX-GP

2

AUD_VREG

AMP_MUTE#

0707 Modify:
Change R2911,R2914,R2917 change
to 0ohm 0603 from short pad.

AUD_AGND

Close to codec

R2911

1 0R3J-0-U-GP

2
B

B

R2914

1 0R3J-0-U-GP

2

R2917

2

1 0R3J-0-U-GP

Azalia I/F EMI
HDA_CODEC_SDOUT

1

AUD_AGND
R2912
Do Not Stuff
+AVDD

+AVDD

PCH_AZ_CODEC_SDOUT1

1

1
R2915
2K49R2F-GP

AUD_HP1_JD#

82

20KR2F-L-GP

R2916
2K49R2F-GP

C2920
Do Not Stuff

AUD_AGND

MIC IN

R2918
20KR2F-L-GP

C2919
SC1000P50V3JN-GP-U

R2919

2

1

EXT_MIC_JD#

2

2

1

1

AUD_SENSE_B

2

2

0715: Move To MB
AUD_SENSE_A

1

82

AUD_VREFOUT_B

39K2R2F-L-GP

2
1

AUD_AGND

Close to Pin13
A

Close to Pin14

A

RN2901
SRN4K7J-8-GP
DQ15 AMD DIS SAMSUNG TI

3
4

2

DY

2

1

R2913

2

DY

0109: EMI Reserve, Place Near R2918

Wistron Corporation
21F, 88, Sec.1, Hs in Tai Wu Rd., Hs ichih,
Taipei Hs ien 221, Taiwan, R.O.C.

2

AUD_SENSE_B
82

MIC_IN_L

82

MIC_IN_R

Title

Audio Codec 92HD79B1

EC2903

Size
Docum ent Num ber
Cus tom

1

DY Do Not Stuff

Date:

QUEEN AMD Muxless/UMA
29
of
Sheet

Thurs day, May 26, 2011

AUD_AGND
5

4

3

2

1

Rev

X00
104

5

4

3

2

1

AUDIO OP AMPLIFIER
D

D

C

C

B

B

A

A

DQ15 AMD DIS SAMSUNG TI

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

5

4

3

2

Size
A3

Document Number

Date:

Thursday, May 26, 2011

AMP

Rev

QUEEN AMD Muxless/UMAX00
Sheet
1

30

of

104

5

4

3

2

1

D

D

C

C

DG15 M12 In Daughter BD

B

B

DQ15 AMD DIS SAMSUNG TI

A

A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

5

4

3

2

Size
A3

Document Number

Date:

Thursday, May 26, 2011

LOM

Rev

QUEEN AMD Muxless/UMA
Sheet
1

31

of

X00
104

5

4

3

2

1

D

D

SSID = SDIO
48MHz clock input trace of characteristic impedance (Zo) must be 50 ±15%.

3D3V_CARD_S0

0110: Follow Intel to change to 4.7 uF 0603

3D3V_CARD_S0

XD_D7
SP14
SP13
SP12
SP11

18
17
16
15
14
13

SP10
SP8_R 1 R3212 2
Do Not Stuff

SP10

74

SP9
SP8
SP7
SP6

74
74
74
74

SP8

7
8
9
10
11
12

71.05138.003
SP5
SP4
SP3
SP2
SP1
XD_CD#

The maximum range of the PMOS output current
1. xD-Picture Card: 250mA
2. SD/MMC Card: 250mA
3. MS/MSPRO/Duo-HG: 250mA

0719: EMI Request, ADD RC Filter

EC3201
Do Not Stuff

DY
SP5
SP4
SP3
SP2
SP1
XD_CD#

74
74
74
74
74
74

The pin2 / pin3 (DM/DP) of RTS5138 chip trace layout
with differential characteristic impedance (Zdiff) is 90Ω± 10%

B

1 R3211

USB_PP9

2

USB_PP9_R

DY Do Not Stuff
C3209
2

2

1

18

TR3201
FILTER-130-GP

DY

1

POWER TRACE
1.RTS5138: pin 4 (3V3_IN) trace fixed width is 30 mils (minimum).
2.RTS5138: pin 5 (CARD_3V3) trace fixed width is 30 mils (minimum).
3.RTS5138: pin 6 (V18) trace fixed width is 12 mils (minimum).
Keep the trace routing lengths as short as possible.
4.RTS5138: pin 1(RREF) trace fixed width is 12 mils (minimum).
5.RTS5138: pin 1(RREF) trace must far away 48MHz clock trace.
6.De-coupling and Bulk capacitor should place near to RT5138 chip and Combo Socket.
7.It is recommended that use of ferrites bead on power trace.
8.Via size: Pad>=32 mils, Finished hole>=16 mils.

B

SP9
SP8
SP7
SP6

USB_PN9

1 R3210

2

USB_PN9_R

DY Do Not Stuff
1

18

Do Not Stuff

1

C

SP10
GPIO0
SP9
SP8
SP7
SP6

2

2

GND

Close to chip

U3201
RTS5138-GR-GP

1

25

1

2
1

C3204
Do Not Stuff

C3207
SC2D2U6D3V3KX-GP

2

C3202
SC1U10V2KX-1GP

3D3V_CARD_S0

DY

RREF
DM
DP
3V3_IN
CARD_3V3
V18

C3206
SCD1U10V2KX-4GP

3

V18

1
2
3
4
5
6

74
74
74
74
74

4

1 R3201 2
6K2R2F-GP
USB_PN9_R
USB_PP9_R

MAX 0.4A

CLK_IN
XD_D7
SP14
SP13
SP12
SP11

C

C3203
SCD1U10V2KX-4GP

RREF
24
23
22
21
20
19

DY2

Do Not Stuff

XD_CD#
SP1
SP2
SP3
SP4
SP5

C3201
1
3D3V_S0

XD_D7
SP14
SP13
SP12
SP11

2

2

PCH GPIO67(48M) confirm with SW

1

1

17 CLK_PCH_48M

2

DY

0118 Modify:
Change TR3201 To 69.10118.001 due to layout limitation

A

Do Not Stuff

C3208

0103 Modify:
AMD Spec Update To reserve 6.8P Cap If Trace < 10 Inch

DQ15 AMD DIS SAMSUNG TI

A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

5

4

3

2

Size
A3

Document Number

Date:

Friday, May 27, 2011

Reserved

Rev

QUEEN AMD Muxless/UMAX00
Sheet
1

32

of

104

5

4

3

2

1

D

D

C

C

B

B

DQ15 AMD DIS SAMSUNG TI

A

A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

5

4

3

2

Size
A3

Document Number

Date:

Thursday, May 26, 2011

Reserved

Rev

QUEEN AMD Muxless/UMAX00
Sheet
1

33

of

104

5

4

3

2

1

D

D

C

C

B

B

A

A

DQ15 AMD DIS SAMSUNG TI

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

5

4

3

2

Size
A3

Document Number

Date:

Thursday, May 26, 2011

Reserved

Rev

QUEEN AMD Muxless/UMAX00
Sheet
1

34

of

104

A

B

C

D

E

4

4

3

3

2

2

DQ15 AMD DIS SAMSUNG TI

1

1

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

A

B

C

D

Size
A3

Document Number

Date:

Thursday, May 26, 2011

Reserved

Rev

QUEEN AMD Muxless/UMA
Sheet
E

35

of

X00
104

5

4

3

2

1

ROSA Run Power
15V_S5
5V_S5

Rds(on) = 14m ohm
Max. Current 11.6A

5V_S0

D
D
D
D

2

S
S
S
G

1

U3601
5
6
7
8

R3604
100KR2J-1-GP

5V_S0
Peak current: 6.27A

4
3
2
1

2 0R2J-2-GP 5V_RUN_ENABLE

84.04468.037
2nd = 84.08882.037

C3608
Do Not Stuff

2

DY

1 R3606

C3603
SC10U10V5KX-2GP

1122 Modify:
Change From Y5V To X5R

PS_S3CNTRL

2 100KR2J-1-GP

D

2

1
3D3V_AUX_S5

1

AO4468-GP
1 R3605
D

4
3

2

1

3D3V_S5

Rds(on) = 14m ohm
Max. Current 11.6A

3D3V_S0
3D3V_S0

U3602

18,27,44,46,75 PM_SLP_S3#

84.04468.037
2nd = 84.08882.037

1

C3605
Do Not Stuff

0720 Modify:
Reserved EC3601 0.1uF near
C3604 for EMC NEO suggestion.
0120 Modify:
Change From 0603 To 0402

U3611
8 D
7 D
6 D
5 D

S
S
S
G

1
2
3
4

AO4468-GP

C

1

1.1V_RUN_ENABLE

1D1V_S0
Peak current: 4.0A

C3614
SC10U6D3V5KX-1GP
C

84.04468.037
2nd = 84.08882.037

C3615
SCD1U25V2KX-GP

2

2
R3633
49K9R2F-L-GP

1D1V_S0

1

Rds(on) = 14m ohm
Max. Current 11.6A

1D1V_S5

1

C3604
SC10U6D3V5KX-1GP

2

2

DY

2

2 0R2J-2-GP 3.3V_RUN_ENABLE

3D3V_S0

DY

AO4468-GP
1 R3607

RUN_ENABLE

Peak current: 4.76A

1

4
3
2
1

1

D
D
D
D

5
6
7
8

S
S
S
G

S G D

Do Not Stuff
EC3601

84.2N702.A3F
2nd = 84.DM601.03F

2

5

6

D G S
Q3602
2N7002KDW-GP

1027 Modify: Tune Sequence

1D5V_S3

U3606
AO3404A-GP

Rds(on) = 14m ohm
Max. Current 11.6A

Peak current: 0.5A

C3609
SC10U6D3V5KX-1GP

2

G
2 10KR2J-3-GP

1.5V_RUN_ENABLE

C3610
SCD01U50V2KX-1GP

2

1

1 R3630

1D5V_S0

S
1

D

1D5V_S0

0307: Change Material, 84.02222.S11 Locked

Power Sequence
E

H_THERMTRIP# 6,18,85

3D3V_S0

2

R3629

D3605
2

R3629_2

1 R3634

2

DY
R3634_2

1

DY
Do Not Stuff

1 R3628

2 Do Not Stuff

VCORE_EN 42

1
3

2

41

2

27,46 1D1V_S5_PWRGD

3

C3616
DY Do Not Stuff

RUNPWROK_D

1 R3625

2 Do Not Stuff

FCH_PWRGD

DY

1

44 1D5V_S3_PWRGD

PURE_HW_SHUTDOWN#

0110 Modify: Reserve R3631 For Cost Time, C3616 For Tune Timing

confrim Intersil by FAE,don't

2

42 VRM_VDD_PWRGD

27,28

83.00016.K11
2ND = 83.00016.F11

1
R3603

2
1KR2J-1-GP

S5_ENABLE 27

0708: DG Change to 1K

2ND = 83.00056.G11
3RD = 83.00056.K11
D3607

2 Do Not Stuff

D3601

2

BAW56-5-GP

83.00056.Q11

1
DY
Do Not Stuff

1 R3631

1

3V_5V_EN

18

2

Do Not Stuff

2
D3606

48 PWR_2D5V_PGOOD

C

1

BAS16-6-GP

D3604
3VCORE_EN_R

B

2
BAW56-5-GP

2

Do Not Stuff
18,27,44,46,75 PM_SLP_S3#

2
1KR2J-1-GP

0713: Remove R3623, Change R3622 to 1K

83.00056.Q11
2ND = 83.00056.G11
3RD = 83.00056.K11

1

1

DY

1
R3622

A_RST#

MMBT2222A-3-GP
Q3601

B

DY

17,27

R3602
Do Not Stuff

1

3
27,46 1D2V_S0_PWRGD

1 R3626 21D2V_S0_PWRGD_R
Do Not Stuff

1

FS1R1

2

PM_SLP_S3#

H_PWRGD_R

2
DYR3601
Do Not Stuff

C3602

R3624

D3603
18,27,44,46,75

Do Not Stuff
2ND = 83.00056.G11
3RD = 83.00056.K11
6

10KR2J-3-GP

DY
Cost Down Opportunity

1

6,17,71 H_CPUPWRGD

Do Not Stuff
R3627

1

3D3V_S0

2
Do Not Stuff

B

need L/S

3
1
BAW56-5-GP

83.00056.Q11
2ND = 83.00056.G11
3RD = 83.00056.K11

A

A

RUNPWROK_D
1D1V_S5_PWRGD
1D5V_S3_PWRGD

1013 Modify: Remove D3607 Pin 1 VRM_VDD_NB_PWRGD

2

2

0109: EMI Reserve, EC3602 Place Near R3625
0109: EMI Reserve, EC3603 Place Near D3604
0109: EMI Reserve, EC3604 Place Near D3604

DQ15 AMD DIS SAMSUNG TI

Wistron Corporation

DY
1

DY

Do Not Stuff

Do Not Stuff

1

DY

1

Do Not Stuff

2

EC3602 EC3603 EC3604

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

Power On Logic

Size
Document Number
Custom

Rev

QUEEN AMD Muxless/UMA

Date: Thursday, May 26, 2011
5

4

3

2

Sheet
1

36

of

X00
104

5

4

3

2

1

D

D

C

C

B

B

DQ15 AMD DIS SAMSUNG TI

Wistron Corporation

A

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

5

4

3

2

Power Plane Enable

Size
A3

Document Number

Date:

Thursday, May 26, 2011

QUEEN AMD Muxless/UMA
Sheet

1

37

of

Rev

X00
104

A

5

4

3

2

1

D

D

Move To CRT BD
C

C

B

B

A

A

DQ15 AMD DIS SAMSUNG TI

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
Document Number
Custom
Date:
5

4

3

2

DCIN_JACK

Rev

X00
QUEEN AMD Muxless/UMA

Thursday, May 26, 2011

Sheet
1

38

of

104

5

4

3

2

1

SSID = BATT CONN
D

1

2

C3902
SCD1U50V3KX-GP

C3901
SC2200P50V2KX-2GP

2

1

K

BT+

R3902
R3903
R3904

BAT_SCL
BAT_SDA
BAT_IN#

DY

BATT1
10
1

PBAT_SMBCLK1
PBAT_SMBDAT1
PBAT_PRES1#

2 100R2J-2-GP
2 100R2J-2-GP
2 100R2J-2-GP

1
1
1

2
3
4
5
6
7
8
9
11

R3901
1

AFTP3901

1

BAT_ALERT

PD3904

470KR2J-2-GP

EC3901

A

2
1
Do Not Stuff

DY
C

DY

EC3902
2
1
Do Not Stuff

2

3D3V_AUX_KBC

K

27,40
27,40
27

Batt Connecter

A

0916: Change Charger IC, Remove BATT_SENSE

PD3902
Do Not Stuff

D

ALP-CON9-2-GP-U

DY

C

20.81316.009
2nd = 20.81440.009
3rd = 20.81328.009
0720 Modify:
DCBATOUT

1

PBAT_PRES1#
PBAT_SMBDAT1
PBAT_SMBCLK1
BT+

DY
2

1
1
1
1

Do Not Stuff
EC3903

AFTP3902
AFTP3903
AFTP3904
AFTP3905

0719 Modify:
Reserved EC3903 0.1uF near EC3901 for EMC NEO suggestion.

B

B

For actual location, need to be swap all pin

Close to Batt Connector

BAT_SCL
3

3

3

BAT_SDA

BAT_IN#

D3901
BAV99-5-GP-U

3rd = 83.BAV99.D11

83.00099.T11
2nd = 83.00099.K11

2

1

2

1

83.00099.T11
2nd = 83.00099.K11

2

D3903
BAV99-5-GP-U
1

D3902
BAV99-5-GP-U

83.00099.T11
2nd = 83.00099.K11

3rd = 83.BAV99.D11

3rd = 83.BAV99.D11

A

A

DQ15 AMD DIS SAMSUNG TI
3D3V_AUX_KBC

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

5

4

3

2

Size
A3

Document Number

Date:

Thursday, May 26, 2011

BATT CONN

Rev

QUEEN AMD Muxless/UMA
Sheet
1

39

of

X00
104

5

4

3

2

1

SSID = Charger

D

D

DCBATOUT

AD+_TO_SYS

130W

0

1

S

DY

1

2
Do Not Stuff

2

2

Do Not Stuff
PG4006
1

Do Not Stuff
PG4001
1

1

EC4002
Do Not Stuff

1

EC4001
Do Not Stuff

2

2

1

1

3
2
1
27

X00 0415

2

2

1

PC4018
SCD1U25V2KX-GP
2
1
PC4019
SCD1U50V3KX-GP

1

1
2

2

1
2

PG4010
Do Not Stuff
1
2

PWR_CHG_CSOP_1

PWR_CHG_CSON_1

CHG_AGND

DY

X00 0415

27 PWR_CHG_ACOK

D
1

PR4033
Do Not Stuff

DY

PR4036
Do Not Stuff

PQ4006
2N7002A-7-GP
G

AC_IN#
A

DY
S

2

DQ15 AMD DIS SAMSUNG TI

Wistron Corporation

DY

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Do Not Stuff
Title

Do Not Stuff

BQ24707RGRRG4
Size
Document Number
Custom

0120 Modify

Rev

QUEEN AMD Muxless/UMA

Date:
5

2

2
5
6
7
8

2

1
2
1 PC4022
SC220P50V2JN-3GP

B

CHG_AGND
AD_IA

D

1

0

2

0

1

PR4038
Do Not Stuff

0

90W

PR4022
Do Not Stuff
2

CHG_AGND

PR4028
Do Not Stuff

2

2

AD_IA_HW2

65W

1

PWR_CHG_REGN

PR4039
100KR2J-1-GP

PQ4009
G

AD_IA_HW

65MOS
4

DY

1

PC4025
Do Not Stuff
2
1

PR4034
Do Not Stuff

DY

DY

H_PROCHOT#

PU4006
Do Not Stuff

AC_IN#

1

27

2

2

AD+

2
7D5R2F-GP

2

PR4025
Do Not Stuff

2

DY

2 10R2F-L-GP

1

1
1

1
PR4027
100KR2J-1-GP

DY

CHG_AGND

3D3V_AUX_S5

PWR_CHG_REGN

1
PR4012

2

S

3D3V_AUX_S5

PR4019

2

Do Not Stuff

CHG_AGND

EC code only BQ24707

PG4011
2

CHG_AGND

EE need check pull high

CHG_AGND

PG4009
Do Not Stuff
1
2

1

1

PWR_CHG_CMPOUT

G

PWR_CHG_IOUT

7

14

BQ24707ARGRR-GP

IOUT

1 PR4024
Do Not Stuff

S

DY
X00 0415

A

GND

ACOK#

GND

5

2

CHG_AGND

PR4035
Do Not Stuff

DYPR4026
Do Not Stuff

PQ4001
Do Not Stuff

D

27

DY

1

IFAULT#

2
1

2

D

PWR_CHG_REGN

1

1

2

3D3V_AUX_KBC

DY
AD_IA_HW2

1 PWR_CHG_IFAULT
11

PR4018
Do Not Stuff
PR4023
Do Not Stuff

PQ4007
2N7002A-7-GP
G

DY

PWR_CHG_SRN

2

2

PWR_CHG_SRP

1
2
PR4016
D01R2512F-4-GP

3
2
1

1

PWR_CHG_AD_OFF

21

1

2

1

13
12

BT+
BT+_R

2

S
S
S

B

ILIM
SRN

TP4001
Do Not Stuff

PWR_CHG_LODRV

DY
SRP

10

1

IND-5D6UH-48-GP-U1

G

PWR_CHG_ILIM

15

SDA

2
PWR_CHG_LX1
PC4013
Do Not Stuff

5
6
7
8

LODRV

1
Do Not Stuff

PC4020
Do Not Stuff
1

SCL

PR4015
PWR_CHG_PHASE
1
2

PC4021
SCD1U25V2KX-GP
2
1

8

19

PL4001

1

9

PWR_CHG_BAT_SDA
1
Do Not Stuff

Charger Current=1.4~3.6A
DY

PWR_CHG_HIDRV

2

PWR_CHG_BAT_SCL
1
Do Not Stuff

2
PG4008

C

SC10U25V5KX-GP
PC4017

2
PG4007

PR4017
100KR2J-1-GP

PR4037
19K6R2F-GP

2
PG4004
1
1

PHASE

DY

PWR_CHG_REGN

16
18

PC4023
SCD1U25V2KX-GP

2

2

CMPIN

PWR_CHG_CMPIN

PC4011
SCD047U25V2KX-GP

1
ACN
HIDRV

PWR_CHG_CMPIN

X00 0415

2

1
1
2

PWR_CHG_ACN

PWR_CHG_ACP

CMPOUT

DY

65MOS
4

PC4014
Do Not Stuff

3

PU4004
Do Not Stuff

2
PC4007
SC1U25V3KX-1-GP

SC10U25V5KX-GP
PC4016

BAT_SCL
BAT_SDA

Do Not Stuff
PG4005
1

1

2
1

REGN

PR4014
3D3MR2J-GP

PWR_CHG_BTST

1

D
D
D
D

27,39

17

BTST

A

SC10U25V5KX-GP
PC4015

CHG_AGND
27,39

X00 0415

2

ACDET

4

CHG_AGND

PG4002

Do Not Stuff

2
6

PWR_CHG_CMPOUT
PR4013
49K9R2F-L-GP

CHG_AGND

3D3V_AUX_KBC

2

2

1
2

1
2

PWR_CHG_ACDET

1

1
2

CHG_AGND

PR4011
19K1R2F-GP

PC4012
SCD01U50V2KX-1GP

PR4031
1
49K9R2F-L-GP
2

D

27

S

AD_IA_HW

VCC

K

S
S
S

PQ4004
2N7002A-7-GP
G

20

PD4001
SD103AWS-1-GP
PR4009
1
2
Do Not Stuff

G

PWR_CHG_IOUT

PU4005

ACP

1
1
1

2

2
20R5J-GP

PC4024
SCD1U25V3KX-GP

CHG_AGND

SC10U25V5KX-GP
PC4009

1
PR4010

CHG_AGND

CHG_AGND

PWR_CHG_VCC

2

PWR_DCBATOUT_CHG

0106: Update PU4005 Symbol From Database.
PC4004
SCD1U25V3KX-GP

SC10U25V5KX-GP
PC4006

PR4008
20R5J-GP
1

PR4007

316KR2F-GP

2

SC10U25V5KX-GP
PC4008

84.2N702.A3F
2nd = 84.DM601.03F

1

Id= -10A
Qg= -22nC
Rdson=14~13mohm

PR4005
470KR2J-2-GP

0222: Change PC4004, PC4024 From 0603 To 0402 0.1uF

DY

PC4010
SCD47U25V3KX-2GP

2

6

X00 0415

2

DY

D 8
D 7
D 6
D 5

AO4407AL-GP

D
D
D
D

X00 0415

PR4029
54K9R2F-L-GP

PR4006
Do Not Stuff
2
1

2N7002KDW-GP

PWR_CHG_CMPIN

C

AD+

PG4003
Do Not Stuff

1

5

AD+
R4040
120KR2J-L-GP

PU4003
1 S
2 S
3 S
4 G

PC4002
SCD1U25V2KX-GP

PC4003
Do Not Stuff
1

2
1

S

2

4

BT+

1
2
PR4002
D01R2512F-4-GP

1
2

PWR_CHG_ACOK

PR4001
10KR2F-2-GP

D

1

2

2

PWR_CHG_CMPOUT

G

PQ4002
3

AD+_G_1

PR4032
100KR2J-1-GP

AD+_G_2

Id= -10A
Qg= -22nC
Rdson=14~13mohm

DC_IN_D

DY

PQ4005
2N7002A-7-GP

1

1

3D3V_AUX_S5
PWR_CHG_REGN

PR4030
Do Not Stuff

AO4407AL-GP

PR4004
1
2
10KR2J-3-GP

0802 Rename H_PROCHOT#

1
2
3
4

PR4003
100KR2J-1-GP

AD+

EE need pull high and net name

6,27 H_PROCHOT#

PU4002
S
S
S
G

8 D
7 D
6 D
5 D

4

3

2

Friday, May 27, 2011

Sheet
1

40

of

X00
104

5

4

3

2

1

SSID = PWR.Plane.Regulator_3p3v5v

PWR_3D3V_LGATE2

1

2
3

1

1
1

2

1
2

PC4106
SCD1U25V3KX-GP

2

PC4111
SC1U25V3KX-1-GP

1

K

4

1

1
2

PD4101
Do Not Stuff

PQ4101
DMN66D0LDW-7-GP

PC4107
SCD1U25V3KX-GP

3

2

A

DY

Do Not Stuff
PG4106

PR4105

2
1

Do Not Stuff

PWR_5V_ENTRIP1

2

105KR2F-1-GP

1

1

2

Do Not Stuff

DY

2

1

1

1
PG4103

6

2

PC4109
Do Not Stuff

2

Do Not Stuff
PG4105

5V_S5

15V_PWR

2
66K5R2F-GP

DY Do Not Stuff

Do Not Stuff
PG4104

1

PWR_3D3V_ENTRIP2
PR4113

2

5

1

PR4108

PG4102

1

1

15V_S5

10KR2J-3-GP

D

PD4104
BAT54S-7F-GP

2

PWR_3D3V5V_ENTRIP

2

PR4106

2

1

3V_5V_EN

PWR_3D3V_DCBATOUT

PD4102
Do Not Stuff

DY

3

2

1
3

2

1
2

PD4103
BAT54S-7F-GP

0307: Power Team Modify
36
DCBATOUT

PC4103
SCD1U25V3KX-GP

PC4102
SCD1U25V3KX-GP

PC4105
SC1KP50V2KX-1GP

D

DCBATOUT

2

DY

PWR_5V_DCBATOUT

PC4108
Do Not Stuff
PG4107

1

2

Do Not Stuff
PG4108

1

2

C

C

Do Not Stuff
PG4109

1

2

Do Not Stuff
PG4122

1

2

DCBATOUT
PWR_3D3V_DCBATOUT

Design Current = 4.5A
6.3A54A

Cyntec 0.36uH
DCR=1.05mohm
Idc=30A, Isat=60A

1
VCC

2

2
1
40

2

VDDA

1

PG4337
2

PC4239
SC2D2U10V3KX-1GP

Do Not Stuff

DCBATOUT_VCC_CORE1
1

Do Not Stuff
PG4334
1
2

SCD1U50V3KX-GP

PR4233
10R2F-L-GP
PU4201

PWR_VCC_CORE_VCC
PC4238

SC10U25V5KX-GP
PC4247

無無無無

SC10U25V5KX-GP
PC4246

5V_S5

0304 Modify: Change To

D

S
S
S
G

5V_S5

Do Not Stuff

PC4231

65MOS

5V_S5

Do Not Stuff
PG4332
1
2

DCBATOUT

D
D
D
D

PU4202
Do Not Stuff

Do Not Stuff
PG4331
1
2

SC10U25V5KX-GP
PC4229

Do Not Stuff
PG4330
1
2
D

PTC4210
Do Not Stuff

SC10U25V5KX-GP
PC4230

Do Not Stuff
PG4329
1
2

DY

2

1

Do Not Stuff
PG4328
1
2

5
6
7
8

DCBATOUT

1

Rev

QUEEN AMD Muxless/UMA

Friday, May 27, 2011

Sheet
1

42

of

X00
104

5

4

3

2

1

D

D

DCBATOUT_VDDNB

DCBATOUT

PG4301

1

2

Do Not Stuff
PG4302

1

2

Do Not Stuff
PG4303

1

2

Do Not Stuff
PG4304

1

2

Do Not Stuff
PG4305

1

2

DCBATOUT_VDDNB

Do Not Stuff
PG4306

1
2

1

1
2

2

1
2
5
6
7
8

PC4305
SCD1U50V3KX-GP

D
D
D
D

PU4207
SIR462DP-T1-GE3-GP

SC10U25V5KX-GP
PC4304

DY

SC10U25V5KX-GP
PC4303

SC10U25V5KX-GP
PC4302

Do Not Stuff
PC4301

C

1

2

Do Not Stuff

2

1

C

S
S
S
G

Imax=22A
OCP>27A

4
3
2
1

Cyntec 0.36uH
DCR=1.05mohm
Idc=30A, Isat=60A

42 PWR_VCC_CORE_UG1_NB

APU_VDDNB

PL4301

1

42 PWR_VCC_CORE_PH1_NB

2

1

1
2

2

1
2

2
1

2
1
1

Do Not Stuff

2

1
1 PWR_VDDNB_SNU
2

Panasonic 330uF
2V, ESR=9 mohm

PR4303
1K78R2F-GP

2

2

PC4306

5
6
7
8

PTC4304
SE330U2VDM-L-GP

4
3
2
1

PTC4303

DY

Do Not Stuff

5
6
7
8

PTC4302
SE330U2VDM-L-GP

4
3
2
1

PTC4301

DY

Do Not Stuff

PG4308

Do Not Stuff

DY

PR4305
Do Not Stuff
PG4307

S
S
S
G

DY

Do Not Stuff

SIR164DP-T1-GE3-GP

DY
S
S
S
G

Do Not Stuff

PU4303

D
D
D
D

D
D
D
D

PU4302

1

IND-D36UH-9-GP
42 PWR_VCC_CORE_LG1_NB

B

PR4302

Id=26.5A
Qg=40.6~61nC
Rdson=2.6~3.2mohm
42 PWR_VCC_CORE_CSPB1

1

B

2
NTC-10K-27-GP

1

2

2

DY

1

0304: Power Team change from 0603 To 0402

PWR_VCC_CORE_CSNB

42

PR4304
PR4306
2K87R2F-1-GP Do Not Stuff

A

A

DQ15 AMD DIS SAMSUNG TI

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

VDDNB
5

4

3

2

Size
A2

Document Number

Date:

Thursday, May 26, 2011

Rev

QUEEN AMD Muxless/UMA
Sheet
1

43

of

X00
104

5

4

3

2

1

SSID = PWR.Plane.Regulator_1p5v0p75v
DCBATOUT
2

PWR_DCBATOUT_1D5V
PG4401
1

Do Not Stuff
PG4402
2
1

D

D

Do Not Stuff
PG4403
2
1

1D5V_PWR

6

VBST
EN/PSV
VREF

DRVH

1
2

1

1
2

2

1
2

5
6
7
8

2

1
PG4411
Do Not Stuff

2

1
PG4412
Do Not Stuff

2

1
PG4413
Do Not Stuff

2

2

PTC4401

1
PG4414
Do Not Stuff
1
PG4416
Do Not Stuff

2

1
PG4417
Do Not Stuff

2

1
PG4418
Do Not Stuff

2

1
PG4419
Do Not Stuff
1
PG4422
Do Not Stuff

2

1
PG4423
Do Not Stuff

2

1D5V_PWR

4
3
2
1

PL4401

0630 modify

4

GND

1

DY
2

PC4413
Do Not Stuff

2

DDR_VREF_S3
PR4409
1
2
Do Not Stuff

1
2

1

1
2

2

PC4411
SCD1U10V2KX-4GP

1
2

C

2

I/P cap: 10U 25V K0805 X5R/ 78.10622.51L
Inductor: 1.5uH PCMC104T-1R5MH Cyntec 3.8mohm/4.2mohm Isat =33Arms 68.1R510.10J
O/P cap: 560U 2.5V MP2VL560MC5R7 16mOhm 3.5Arms 77.55671.00L
O/P cap: 220U 2V EEFCX0D221R 15mOhm 2.7Arms Panasonic/79.22719.20L
H/S: RJK03B9DPA / 10.9mohm/15.1mOhm@4.5Vgs/ 84.003B9.B37
L/S: RJK03D4DPA / 4.6mohm/5.6mOhm@4.5Vgs/ 84.00034.A37

0D75V_S0
2

PG4420
1

Do Not Stuff
PG4421
2
1

DY

0630 Modify:
ADD PC4604 1uF0603 on PWR_1D5V_VTTIN.

0702 Modify:
Add PR4611 0ohm 0603 pad
on PWR_1D5V_VTTREF.
0D75V_PWR

PC4402

1D5V_PWR

1

TPS51216RUKR-GP

DY

PWR_1D5V_VDDQS

VTTGND

0D75V_PWR

3
1

PC4401
SC1U10V3KX-3GP

VTT
VTTS

TPS51216_PHS_SET

PC4410
SC4D7U6D3V5KX-3GP

2

PR4404
Do Not Stuff

65MOS

PWR_1D5V_VDDQS

4
3
2
1

VTTIN
VTTREF

PC4414
SCD22U6D3V2KX-1GP
21
GND

9
2

PC4417
2
1

VDDQS

Do Not Stuff

PWR_1D5V_VTTREF 5

TRIP

PC4416
2
1
SC10U6D3V5MX-3GP

2

18

7

PWR_1D5V_VTTREF

DY

Do Not Stuff

PG4415
Do Not Stuff

PU4403

10

MODE

2
IND-1D5UH-34-GP
2

11

1

1

DRVL
PGND

TPS51216_DRVL

PC4415
2
1
SCD1U10V2KX-4GP

2

200KR2F-L-GP
1

PR4408
66K5R2F-GP
1

PR4406

54K9R2F-L-GP

PWR_1D5V_TRIP

2

1

PR4405
1

REFIN

PWR_1D5V_SW
1

2

8

PWR_1D5V_MODE 19

13

5
6
7
8

SW
PWR_1D5V_REFIN

2

1

Design Current = 12.9A
18.06A2.5A

3D3V_S0

1

3D3V_S0

R5606
10KR2J-3-GP

1

DY
2

0914 Modify:
Change ODD Part number From 22.10300.421 To 62.10065.E01

R5610
Do Not Stuff

B

1122 Modify:
Change From Y5V To X5R

0109: EMI Request.
ODD_PWR_5V

R5607
SATA_ODD_DA#_C

2

DY

1

SATA_ODD_DA#
2

S

D

G

Do Not Stuff
Q5601
2N7002K-2-GP

D

G

84.2N702.J31

DY
1

Q5602
2N7002K-2-GP

Do Not Stuff
EC5601

ODD_PWRGT#

S

2

DY

SC10U10V5KX-2GP

1

2

ODD_PWR_5V

SC10U10V5KX-2GP

1

1

SATA_RXN1_C 19
SATA_RXP1_C 19

R5611
Do Not Stuff

2

SKT-SATA7P-6P-40-GP-U

C5607 1
C5608 1

1

SATA_RX1-_C
SATA_RX1+_C

P1
P2
P3
P4
P5
P6
NP2
9

B

DY
5V_S0

SATA_TXP1 19
SATA_TXN1 19

2

S2
S3
S4
S5
S6
S7

1

19 SATA_ODD_PWRGT

8
NP1
S1

84.2N702.J31

A

A

DQ15 AMD DIS SAMSUNG TI

DY

2 R5605
SATA_ODD_PWRGT

SATA_ODD_DA#_Q

1
Do Not Stuff
1 R5609 2
Do Not Stuff

SATA_ODD_DA#
ODD_DA_Q

Wistron Corporation

17

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

18
Title

0712

5

4

3

2

Size
A3

Document Number

Date:

Thursday, May 26, 2011

HDD/ODD

Rev

QUEEN AMD Muxless/UMA
Sheet
1

56

of

X00
104

5

4

3

2

1

USB30_VCCA

Do Not Stuff

2

GND
IN
EN1#
EN2#

FLG1
OUT1
OUT2
FLG2

8
7
6
5

USB_OC#0

2

2

2

18

Do Not Stuff

1
2
3
4

1

0706: Sourcer Request To Change To GMT
0906: Add 0hm in USB_PWR_EN# and Remove CEN#/
Consult SW Use Which Enable.

TC5702
ST100U6D3VAM-3-GP

0906: Change TC5702 Part Number,
Follow DQ15 Intel

80.10715.B1L
2nd = xxx

0113: Change To Duel USB PWR Switch & Some Cap.

USB30_VCCB
AP2182SG-13-GP

74.02182.071
18

C5709

1
2

C5710
SC10U10V5KX-2GP

2

USB_OC#1

1

D

2nd = 74.00546.A7D
3rd = 74.02062.079

SCD1U10V2KX-4GP

1

U5703_EN#

2

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

D

C5711

2

C5702

2

C5704

DY
SCD1U10V2KX-4GP

1 R5720

27 USB_PWR_EN#
27,82 USB_IO_CRT_EN#

C5703

Do Not Stuff

U5703

1

R5705

DY
5V_S5

1

1

1

at least 80 mil

0101: Change ESATA1 To 22.10290.271

C

C

Wait For 3.0 Esata COMBO With DETECT PIN
2

Do Not Stuff

USB30_VCCA
ESATA1

1

USB_PP0_C

C5705

2

DY

USB30_VCCA

Do Not Stuff

2

USB_PP0_U

DY

3

1 R5701

4

4

1

2

C5707 1
C5708 1

19 SATA_RXP2_C
19 SATA_RXN2_C

6
7

SATA_RXP2
SATA_RXN2

10
9

USB_PP0_C
USB_PN0_C

USB_PN0_C

3

SCD01U16V2KX-3GP
2
SCD01U16V2KX-3GP
2

SATA_TXP2
SATA_TXN2

DY

VBUS

DT1
DT2

A+
A-

GND
GND
GND
GND
GND
GND
GND
GND

3
2

B+
BD+
D-

12
13

USBDET_CON#

27

4
5
8
11
14
15
16
17

Do Not Stuff
SKT-ESATA-USB-11P-6-GP

C5706

2

Do Not Stuff

2

DY

Do Not Stuff

1

USB_PP0_C
USB_PN0_C

1 R5702

19 SATA_TXP2
19 SATA_TXN2

DY

FILTER-130-GP
TR5701

USB_PN0_U

1

D5706

1

22.10321.W11
2nd = 22.10339.261

0103 Modify:
AMD Spec Update To reserve 6.8P Cap If Trace < 10 Inch

0706: Rename Netname

1

USB30_VCCA

AFTP5716

Do Not Stuff

1
AFTP5717
Do Not Stuff

0112: Change To USB 2.0 ESD Diode X 2

0101: Reserve Common Mode Choke & ESD Diode.

B

B

USB CHARGER
0906: Modify:
Change U5702 soltuion to PI5USB14550
from MAX14566

U5702

GND
S1
Y+
YVDD
A-

11
10
9
8
7
6

PI5USB14550AZEE-GP

A

CB

1 R5721

2

Do Not Stuff

USBCHARGER_CB0
USB_PP0 18
USB_PN0 18

27

5V_S5

2

S0
D+
DGND
A+

C5701

Switch Control Bit:
CB=0 (AM):auto detection charger identification active.
CB=1 (PM):connect DP/DM to TDP/TDM.

1

1
2
3
4
5

SCD1U10V2KX-4GP

USB_PP0_U
USB_PN0_U

S0
0
0
1
1

S1
0
1
0
1

A

DQ15 AMD DIS SAMSUNG TI

Auto

Wistron Corporation

D+/- connects to Y+/-

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

0914: Remove Non Charger Co-lay Resistor.

5

4

Title

3

2

ESATA/USB Charger

Size
A2

Document Number

Date:

Thursday, May 26, 2011

Rev

QUEEN AMD Muxless/UMA
Sheet

1

57

of

X00
104

5

4

3

2

1

SSID = AUDIO
0715 Modify:
Change EC5801~EC5804 to 100p 0402
and default un-stuff.
Add R5801~R5804 between SPK signal and connector
for EMC NEO suggest.

D

D

0914 Modify:
Change SPK1 to 20.F0772.004 from
20.F1647.004 from Double updated.
0921 Modify:
Modify Pin Define Base On DQ15 Intel
1110 X02 Modify:
Add 2nd 20.F1804.004 on SPK1 from
ME updated connector list.

Speaker Connector
ACES-CON4-7-GP-U
6
C

29
29
29

AUD_SPK_LAUD_SPK_L+
AUD_SPK_R-

29

AUD_SPK_R+

R5801 1
R5802 1
R5803 1

2 Do Not Stuff
2 Do Not Stuff
2 Do Not Stuff

AUD_SPK_L-_C
AUD_SPK_L+_C
AUD_SPK_R-_C

4
3
2

R5804 1

2 Do Not Stuff

AUD_SPK_R+_C

1

C

5

Do Not Stuff
Do Not Stuff
Do Not Stuff
Do Not Stuff

1
2

DY

EC5804
Do Not Stuff

1
2

DY

EC5803
Do Not Stuff

1
2

DY

EC5802
Do Not Stuff

1
2

DY

EC5801
Do Not Stuff

SPK1

AFTP5801
AFTP5802
AFTP5803
AFTP5804

20.F0772.004
2nd = 20.F1804.004

1
1
1
1

AUD_SPK_L-_C
AUD_SPK_L+_C
AUD_SPK_R-_C
AUD_SPK_R+_C

0921:Modify
Add AFTP, Follow DQ15 Intel

B

B

A

A

DQ15 AMD DIS SAMSUNG TI

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

5

4

3

2

Size
A3

Document Number

Date:

Thursday, May 26, 2011

Audio Jack

Rev

QUEEN AMD Muxless/UMA
Sheet
1

58

of

X00
104

LAN CONN In Daugthter BD

DQ15 AMD DIS SAMSUNG TI

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
A3

Document Number

Date:

Thursday, May 26, 2011

LAN_CONN

Rev

QUEEN AMD Muxless/UMAX00
Sheet

59

of

104

5

4

3

2

1

SSID = Flash.ROM

SPI FLASH ROM (2M byte) for KBC

R6002
SRN100KJ-6-GP

1

SPI_HOLD_0#

1

2

C6001

2
1

2
Do Not Stuff

D

used

C6002

SCD1U10V2KX-5GP

DY

RN6002

DY

R6007
Do Not Stuff

Reserved 795 use LPC ROM or 791 LPC ROM

2

3
4

1

used

1

Reserved 795 use LPC ROM or 791 LPC ROM

SPI_POWR

R6005
Do Not Stuff

1

SPI_VCC

1

1

DY

R6009
Do Not Stuff

Do Not Stuff

R6008
Do Not Stuff

DY

D

3D3V_AUX_KBC

2

2

2

3D3V_AUX_KBC

2

3D3V_S5

0111: Follow DV14 To Change Power rail to 3D3V_AUX_KBC

3D3V_S5

0111: Follow DV14 To Change Power rail to 3D3V_AUX_KBC

U6001
SPI_VCC

8
7
6
5

R6001
10KR2J-3-GP

EC6003

72.25160.B01
2ND = 72.25Q16.001

C

1

3RD = 72.25016.D01

Reserved 795 use LPC ROM or 791 LPC ROM

used

4TH = 72.02516.A01

1

SPI_CLK_R 27
SPI_SI_R 27

MX25L1606EM2I-12G-GP

DY DY

EC6001
Do Not Stuff

VCC
HOLD#
SCLK
SI/SIO0

1

2

Do Not Stuff

CS#
SO/SIO1
WP#
GND

2

1
2
3
4

SPI_SO
SPI_WP#

2 33R2J-2-GP
1

2

1 R6003
2 R6004

Do Not Stuff

27 SPI_CS0#_R
27 SPI_SO_R
27 EC_SPI_WP#

C

SSID = RBATT
RTC_AUX_S5

3D3V_AUX_S5
U6003
2

2

1

RTC1

RTC_PWR

1 R6006 2
510R2J-1-GP

1
2
NP1
NP2

CH715FPT-GP
1

C6005
SC1U6D3V2KX-GP

B

+RTC_VCC

X01

3

83.R0304.B81
2nd = 83.00040.E81

PWR
GND
NP1
NP2

1

B

BAT-330DG02PSS0301CE-GP-U

AFTP6002

Width=20mils

62.70001.051

2nd = 62.70014.001
3rd = 62.70001.061

2

3D3V_S0

Q6002

DY

R6032
Do Not Stuff

1

G
D

1
1

+RTC_VCC

AFTP6001

R6011
10MR2J-L-GP

RTC_SENSE 17

S

2

2N7002K-2-GP

84.2N702.J31

A

A

DQ15 AMD DIS SAMSUNG TI

0105 Modify:
updated RTC1 symbol and footprint from
data base.
1122 Modify:
Add Q6002, R6010, R6011 for FACTORY RTC detect function.

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

0111: Change RTC Schematic As DV14 Brazo, SW Suggest.

5

4

3

2

Size
A3

Document Number

Date:

Thursday, May 26, 2011

Flash/RTC

Rev

QUEEN AMD Muxless/UMA
Sheet
1

60

of

X00
104

5

4

3

2

1

SSID = USB
D

D

C

C

B

B

DQ15 AMD DIS SAMSUNG TI

Wistron Corporation

A

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size

Document Number

USB Power SW

Rev

QUEEN AMD Muxless/UMA
Date:
5

4

3

Thursday, May 26, 2011
2

Sheet

61

of
1

X00
104

A

5

4

3

2

1222 Modify:
C6222,C6224, C6231, C6234 Change Y5V To X7R

R6225 1PARAD
Do Not Stuff
R6226 1PARAD
Do Not Stuff
R6227 1PARAD
Do Not Stuff
R6230 1DY
2
Do Not Stuff
R6232 1DY
2
Do Not Stuff
R6234 1DY
2
Do Not Stuff

EQ2_A

EN_RXD default value PU 3.3V
(internally pulled high)

2

OS1_A

2

R6228 1DY
Do Not Stuff
R6231 1DY
2
Do Not Stuff

OS2_A
DE1_A

EQ1_A

TI

EQ2_A

EN_RXD_A
CM_A

CM default value PD GND
(internally pulled down)

DE2_A

R6235 1
Do Not Stuff
R6237 1
2
Do Not Stuff

1

1

2
1

2

2

SC1U6D3V2KX-GP

C6224

1
13

D

EQ1_A
EQ2_A

2
17

OS1_A
OS2_A

4
15

DE1_A
DE2_A

3
16

EN_RXD_A
CM_A

5
14

VCC
VCC
EQ1
EQ2

TX1-

23
22

USB_SS_TXDN2_C
USB_SS_TXDP2_C

C6225 1
C6226 1

2 SCD1U16V2KX-3GP
2 SCD1U16V2KX-3GP

USB30_TXDN2_R
USB30_TXDP2_R

TX2-

11
12

USB_SS_RXDN2_C
USB_SS_RXDP2_C

C6227 1
C6228 1

2 SCD1U16V2KX-3GP
2 SCD1U16V2KX-3GP

USB30_RXDN2
USB30_RXDP2

OutTX1+
OutTX2+

OS1
OS2

In

RX1RX1+

DE1
DE2

In

RX2RX2+

8
9

82
82

18
18

To FCH
From FCH

USB30_TXDN2 18
USB30_TXDP2 18

20
19

USB30_RXDN2_R
USB30_RXDP2_R

To Connector

82
82

From Connector

EN_RXD_A

DY

2

TI

SCD01U50V2KX-1GP

1

2
1

2

2

SC1U6D3V2KX-GP

3D3V_S5

EQ1_A

2

R6236 1
4K7R2J-2-GP
R6238 1
2
4K7R2J-2-GP
R6239 1
2
Do Not Stuff
R6240 1
2
Do Not Stuff
R6241 1
2
Do Not Stuff
R6242 1
2
Do Not Stuff

C6219

U6215

2

2

C6223

SCD1U16V2KX-3GP

All pin have a default
setting of NC

3D3V_S5

3D3V_S5

0916: Move From IO Board To Main Board

Place near Pin 1
as closed as possible

C6222

SCD1U16V2KX-3GP

0310: Modify Strap Pin To Improve Re-driver Strength
D

C6221
SCD01U50V2KX-1GP

C6220

1

Place near Pin 13
as closed as possible

1

DY CM_A
1 R6211
Do Not Stuff

DY OS1_A

2

PARAD_REXT_P2

EN_RXD
CM

7
24

NC#7
NC#24

PARAD

DY OS2_A

GND
GND
GND
GND
GND

TX Cap Near FCH, RX Cap Near Connector

6
10
18
21
25

SN65LVPE502CPRGER-GP

DY DE1_A
DY DE2_A

DUMMY NAME CONFIGURATION
TI = TI 502R Need Pop
PARAD_ALL = For Both PARAD I2C Mode & Normal MODE
PARAD_I2C = Parad I2C Mode
TI_PARAD= Both TI & PARAD Normal Mode
Pin5
Pin14
Pin2
Pin17
Pin4
Pin15
Pin3
PIN16
GND6 =
GND18=

EN_RX_A = Parade = DUMMY
CM_A = Parade = Default DUMMY (PU)
EQ1 = Parad B_EQ0 = Default DUMMY (PU)
EQ2 = Parad A_EQ0 = Default DUMMY (PU)
OS1 = Parad B_EQ1 = Default DUMMY (PU)
OS2 = Parad A_EQ1 = Default DUMMY (PU)
DE1 = Parad B_DE0 = Default Pull High
DE2 = Parad A_DE0 = Default Pull High
Parad B_DE1 = Default Pull High
Parad A_DE1 = Default Pull High

Parad I2C Mode:
PIN3 DE1 = Parad I2C_ADDR0 = Default DUMMY (PU)
PIN4 OS1 = Parad I2C_ADDR1 = Default DUMMY (PU)
Parad I2C Mode:
PIN15 OS2 = Parad I2C = SDA_CTL (DATA)
PIN16 DE = Parad I2C = SCL_CTL (CLK)

C

C

OS2_B

R6260 1
4K7R2J-2-GP
R6262 1
2
4K7R2J-2-GP
R6263 1
2
Do Not Stuff
R6264 1
2
Do Not Stuff
R6266 1
2
Do Not Stuff
R6267 1
2
Do Not Stuff

TI

EQ1_B

TI

EQ2_B

DY

OS1_B

DY

OS2_B

DY

DE1_B

DY

DE2_B

2

2

1

C6234

1

2

1

C6233

2

2

1

C6232

1

2

2

C6231

SC1U6D3V2KX-GP

OS1_B

2

Place near Pin 1
as closed as possible

SCD01U50V2KX-1GP

EQ2_B

2

SC1U6D3V2KX-GP

R6250 1PARAD
Do Not Stuff
R6251 1PARAD
Do Not Stuff
R6252 1PARAD
Do Not Stuff
R6255 1DY
Do Not Stuff
R6257 1DY
2
Do Not Stuff
R6258 1DY
2
Do Not Stuff

EQ1_B

2

3D3V_S5

SCD1U16V2KX-3GP

2

C6230
SCD01U50V2KX-1GP

C6229

All pin have a default
setting of NC

SCD1U16V2KX-3GP

3D3V_S5

1

Place near Pin 13
as closed as possible

0310: Modify Strap Pin To Improve Re-driver Strength

U6216
3D3V_S5

EN_RXD default value PU 3.3V
(internally pulled high)

1
13

DE1_B
DE2_B
R6253 1DY
2
Do Not Stuff
R6256 1DY
2
Do Not Stuff

EN_RXD_B
CM_B

CM default value PD GND
(internally pulled down)
2

DY EN_RXD_B

2

R6259 1
Do Not Stuff
R6261 1
Do Not Stuff

DY CM_B

EQ1_B
EQ2_B

2
17

OS1_B
OS2_B

4
15

DE1_B
DE2_B

3
16

EN_RXD_B
CM_B

5
14

1 R6212
Do Not Stuff

2

PARAD_REXT_P3

7
24

PARAD

VCC
VCC
EQ1
EQ2

TX1-

23
22

USB_SS_TXDN3_C
USB_SS_TXDP3_C

C6235 1
C6236 1

2 SCD1U16V2KX-3GP
2 SCD1U16V2KX-3GP

USB30_TXDN3_R
USB30_TXDP3_R

TX2-

11
12

USB_SS_RXDN3_C
USB_SS_RXDP3_C

C6237 1
C6238 1

2 SCD1U16V2KX-3GP
2 SCD1U16V2KX-3GP

USB30_RXDN3
USB30_RXDP3

OutTX1+
OutTX2+

OS1
OS2

In

RX1RX1+

DE1
DE2

In

RX2RX2+

EN_RXD
CM
NC#7
NC#24

GND
GND
GND
GND
GND

82
82

To Connector
To FCH

18
18

From FCH

8
9

USB30_TXDN3 18
USB30_TXDP3 18

20
19

USB30_RXDN3_R
USB30_RXDP3_R

82
82

From Connector

TX Cap Near FCH, RX Cap Near Connector

6
10
18
21
25

SN65LVPE502CPRGER-GP

B

B

DUMMY NAME CONFIGURATION
TI = TI 502R Need Pop
PARAD_ALL = For Both PARAD I2C Mode & Normal MODE
PARAD_I2C = Parad I2C Mode
TI_PARAD= Both TI & PARAD Normal Mode

Pin5
Pin14
Pin2
Pin17
Pin4
Pin15
Pin3
PIN16
GND6 =
GND18=

EN_RX_A = Parade = DUMMY
CM_A = Parade = Default DUMMY (PU)
EQ1 = Parad B_EQ0 = Default DUMMY (PU)
EQ2 = Parad A_EQ0 = Default DUMMY (PU)
OS1 = Parad B_EQ1 = Default DUMMY (PU)
OS2 = Parad A_EQ1 = Default DUMMY (PU)
DE1 = Parad B_DE0 = Default Pull High
DE2 = Parad A_DE0 = Default Pull High
Parad B_DE1 = Default Pull High
Parad A_DE1 = Default Pull High

Parad I2C Mode:
PIN15 OS2 = Parad I2C = SDA_CTL (DATA)
PIN16 DE = Parad I2C = SCL_CTL (CLK)
Parad I2C Mode:
PIN3 DE1 = Parad I2C_ADDR0 = Default DUMMY (PU)
PIN4 OS1 = Parad I2C_ADDR1 = Default DUMMY (PU)

0113: CRT BD Redriver
Place near Pin 13
as closed as possible

Place near Pin 1
as closed as possible

3D3V_S5

All pin have a default
setting of NC
2

EQ1_C

2

EQ2_C

2

R6254 1DY
Do Not Stuff
R6275 1DY
Do Not Stuff
R6274 1DY
Do Not Stuff
R6276 1DY
2
Do Not Stuff
R6278 1DY
2
Do Not Stuff
R6277 1DY
2
Do Not Stuff

OS1_C
OS2_C

3D3V_S5

EN_RXD default value PU 3.3V
(internally pulled high)
R6269 1DY
Do Not Stuff
R6270 1DY
2
Do Not Stuff

2

R6268 1
Do Not Stuff
R6265 1
2
Do Not Stuff

2
R6279 1
Do Not Stuff
R6282 1
Do Not Stuff
R6280 1
Do Not Stuff
R6283 1
2
Do Not Stuff
R6281 1
2
Do Not Stuff
R6284 1
2
Do Not Stuff

EN_RXD_C
CM_C

DE2_C

DY EQ1_C

2

DY EQ2_C

2

DY OS1_C

1

2

18 USB30_TXDN1
18 USB30_TXDP1

1 R6249
1 R6271

2
2

Do Not Stuff
Do Not Stuff

1 R6272
1 R6273

2
2

Do Not Stuff
Do Not Stuff

USB30_TXDN1_R
USB30_TXDP1_R

82
82

1

2

1

C6248

DY DY

18
18

USB30_RXDN1
USB30_RXDP1

USB30_RXDN1_R
USB30_RXDP1_R

82
82

U6217

1
13

EQ1_C
EQ2_C

2
17

OS1_C
OS2_C

4
15

DE1_C

2

2

Do Not Stuff

DY DY

C6243

DY

Do Not Stuff

2

1

C6246

1

2

2

Do Not Stuff

Do Not Stuff

DY

C6247

Do Not Stuff

A

C6245

Do Not Stuff

3D3V_S5

1

CRT BD USB 3.0 Redriver
C6244

DY EN_RXD_C
DY CM_C
1 R6213
Do Not Stuff

DE1_C
DE2_C

3
16

EN_RXD_C
CM_C

5
14

2

PARAD_REXT_P1

DY

DY OS2_C

7
24

VCC
VCC
EQ1
EQ2
OS1
OS2
DE1
DE2

TX1-

23
22

USB_SS_TXDN1_C
USB_SS_TXDP1_C

C6242 1
C6241 1

TX2-

11
12

USB_SS_RXDN1_C
USB_SS_RXDP1_C

C6240 1
C6239 1

RX1-

8
9

OutTX1+
OutTX2+

In RX1+
DY
RX2In RX2+

EN_RXD
CM
NC#7
NC#24

GND
GND
GND
GND
GND

DY

2 Do Not Stuff

DY2
DY

Do Not Stuff

DY2

Do Not Stuff

USB30_TXDN1_X 1
USB30_TXDP1_X 1

R6285
DY

Do Not Stuff
Do Not Stuff

2
2

R6286
DY

2 Do Not Stuff

USB30_RXDN1
USB30_RXDP1

82
82

To Connector
To FCH

18
18

From FCH
USB30_TXDN1 18
USB30_TXDP1 18

R6287

20
19

USB30_TXDN1_R
USB30_TXDP1_R

USB30_RXDN1_X
USB30_RXDP1_X

1
1

DY
DY
R6288

2
2

Do Not Stuff
Do Not Stuff

USB30_RXDN1_R
USB30_RXDP1_R

A

82
82

From Connector

6
10
18
21
25

Do Not Stuff

DY DE1_C
DY DE2_C
DQ15 AMD DIS SAMSUNG TI

Wistron Corporation

CM default value PD GND
(internally pulled down)

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

Eng stuff 20.K0216.024 Pin1 -> left side
PD change to 20.K0276.024 Pin1 -> left side
so do not swap net

USB 3.0
Document Number
Size
Custom
Date:

5

4

3

2

Rev

QUEEN AMD Muxless/UMA X00

Friday, May 27, 2011

Sheet
1

62

of

104

5

4

3

2

1

SSID = User.Interface
D

D

R6303

1

DY

2

Do Not Stuff
Q6301

Bluetooth Module conn.

DY
D

W LAN_W W AN_LED#
BT1

S
AFTP6301

Do Not Stuff

C

1

BLUETOOTH_DET#

1

W LAN_ACT
BDC_ON
BLUETOOTH_EN
BT_LED
BLUETOOTH_GPIO3
BLUETOOTH_GPIO5

3
5
7
9
11
13

15
NP1
2

3D3V_S0

BT_ACT

C

Do Not Stuff

2ND = 84.2N702.031

AFTP6302

1

AFTP6304
AFTP6305
AFTP6307

1
1
1

DY

4
6
8
10
12
14
NP2
16

x01 change tolerant 20091118

USB_PP4
USB_PN4

1

G

C6301
Do Not Stuff

2

BT_LED

1

DY

AFTP6306

Do Not Stuff

Do Not Stuff

DY

1
1
1
1
1
1

W LAN_ACT
BLUETOOTH_EN
BT_ACT
3D3V_S0
USB_PP4
USB_PN4

B

Do Not Stuff

C6303

2

2

Do Not Stuff

DY

R6302
Do Not Stuff

1

EC6301
Do Not Stuff
2
1

DY
2

1
2

DY

R6301
Do Not Stuff

C6302

DY

AFTP6309
AFTP6310
AFTP6308
AFTP6311
AFTP6312
AFTP6313

1

USB_PN4

BT_ACT
BLUETOOTH_EN
W LAN_ACT

1

B

USB_PP4

2nd = 20.F1500.014
68,82 W LAN_W W AN_LED#
18
USB_PP4
18
USB_PN4
82
BT_ACT
27,82 BLUETOOTH_EN
82 W LAN_ACT

0103 Modify:
AMD Spec Update To reserve 6.8P Cap If Trace < 10 Inch
DQ15 AMD DIS SAMSUNG TI

A

0906 Modify:
Dell Peter already confirmed DQ15 and DN15 will not
support Bluetooth BT365, only support combo Wirless+BT.
Please DUMMY Bluetooth connector(BT1) and stand off
(HBT1) and related components.

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
A4

Document Number

Date:
5

4

3

Bluetooth

Rev

QUEEN AMD Muxless/UMA
Thursday, May 26, 2011
2

Sheet

63

of
1

X00
104

A

5

4

3

2

1

Finger Printer Connector

D

D

Finger Printer Connector
FP1

7
1124 X02 Modify:
Add EC6402 0.1uF,EC6403 180pF and stuff EC6401
47pF from RF fine tune result.

R6403 1

DN15

EC6403
Do Not Stuff

EC6402
Do Not Stuff
2
1

DN15

C

8

DN15

Do Not Stuff

Do
Not Stuff
2nd = 20.K0382.006

2 Do Not Stuff
Biometric_USBPN
AFTP42
AFTP43
AFTP44

3

USB_PN2

2

18

DN15
2

2

DN15

2
3
4
5
6

Biometric_USBPN
Biometric_USBPP

1

1

EC6401
Do Not Stuff

3D3V_S0

C

1

DY
DY
DY

1
1
1

3D3V_S0
Biometric_USBPN
Biometric_USBPP

B

B

DY

18

4

1

Do Not Stuff
TR6401

Biometric_USBPP

USB_PP2
R6404 1

DN15

2 Do Not Stuff

DQ15 AMD DIS SAMSUNG TI

Wistron Corporation

A

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
A4

Document Number

Date:
5

4

3

F/P

Rev

QUEEN AMD Muxless/UMAX00
Thursday, May 26, 2011
2

Sheet

64

of
1

104

A

5

4

3

2

1

D

D

WLAN CONN In Daugthter BD

C

C

B

B

A

A

DQ15 AMD DIS SAMSUNG TI

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

5

4

3

2

Size
A3

Document Number

Date:

Thursday, May 26, 2011

WLAN

Rev

QUEEN AMD Muxless/UMAX00
Sheet
1

65

of

104

5

4

3

2

1

D

D

Remove For DG12 M12 SPEC

C

C

B

B

DQ15 AMD DIS SAMSUNG TI

A

A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

5

4

3

2

Size
A3

Document Number

Date:

Thursday, May 26, 2011

WWAN

Rev

QUEEN AMD Muxless/UMAX00
Sheet
1

66

of

104

5

4

3

2

1

D

D

C

C

(Blanking)

B

B

A

A

DQ15 AMD DIS SAMSUNG TI

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

5

4

3

2

Size
A3

Document Number

Date:

Thursday, May 26, 2011

Reserved

Rev

QUEEN AMD Muxless/UMA
Sheet
1

67

of

X00
104

5

4

3

2

1

SSID = User.Interface

0928 Modify:
Rename CHARGER_LED1 to CHARGERLED1.
Rename FPOWER_LED1 to FPOWERLED1.
Rename HDD_LED1 to HDDLED1.
Rename TP_LOCK_LED1 to TPLOCKLED1.
Rename TP_LOCK_LED2 to TPLOCKLED2.
Rename WLAN_LED1 to WLANLED1

D

0928 Modify:
Change R6806,R6808,R6811~R6813,R6801,
R6803,R6815 to 390ohm from 1K to fine tune
all of MB LED for 5mA spec.

FRONT POWER LED

3

E
LED_PWR

R1

1

R6808

1KR2J-1-GP
POWER_SW_LED_C
1KR2J-1-GP

1

2

R6811

3
4
RN6802

1122 Modify:
R6808,R6811 change to 1K from 390ohm
for fine tune POWER BUTTON LED.

5V_S0

5V_S0

0629 Modify Q6806

2 Q6806_B B
15KR2J-1-GP

E
C

PDTA143ET-GP

84.00143.M11

0928 Modify:
Add 2nd source 83.00110.J70 on FPOWERLED1
HDDLED1,WLANLED1 from Sourcer Anya suggestion.

0706 Modify:
Change HDD_LED part number to
83.01221.R70 base on latest EMN and DXF.

3
1A

K2

WLED1

LED-W-27-GP

83.01221.R70
2nd = 83.00110.J70

0105 Modify:
Change Part Reference HDDLED1 To HDLED1

2K

A1

WLAN_LED_A

1
R6815

C

83.01221.R70
2nd = 83.00110.J70

R2

WHITE_LED_BAT

1

1
2

AMBER_LED_BAT

C

BAT_AMBER
2
390R2J-1-GP

1
R6803

TPLED2
TP_LOCK_LED_R

1

C

PDTA143ET-GP

DY

84.00143.M11

2

Need change to LOW actived from KBC GPIO

0706 Modify:
Change TP_LOCK_LED part number to
83.19217.J70 base on latest EMN and DXF.

0117 Modify: Brightness Follow Intel

E

1
EC6803
Do Not Stuff

15KR2J-1-GP

B

R1

0629 Modify
Q6804_B

R2

B

2

2nd = 83.00326.G70

EC6809
Do Not Stuff

NEED confirm with ME actual
HDD_LED part number.

5V_S0
Q6804
R6807
1

0105 Modify:
Change Part Reference CHARGERLED1 To CHLED1

1

DY
2

84.00143.M11

TPLOCK LED
27 TP_LOCK_LED#

AMBER
83.01222.X80

E

PDTA143ET-GP

Need change to LOW actived from KBC GPIO

0716 Modify:
CHARGER_LED part number change
to 83.01222.X80 from 83.19223.D70.

3

LED-OW-8-GP

R2

B

2

WHITE

5V_S5

Q6808

Battery LED1(AMBER_LED)

EC6807
Do Not Stuff

DY

84.00143.M11

WHITE_LED_BAT#
AMBER_LED_BAT#

R1

4
3

SRN15KJ-3-GP

CHLED1

+

RN6801

1
2

BAT_WHITE
2
390R2J-1-GP

1
R6801

ORANGE

PDTA143ET-GP

-

R1

C

C

0105 Modify:
Change Part Reference WLANLED1 To WLED1

E

+

0702 Modify:
Rename CHARGE_LED# to CHG_AMBER_LED#
Rename DC_BATFULL# to BATT_WHITE_LED#.
27 BATT_WHITE_LED#
27 CHG_AMBER_LED#

5V_S5

Q6807

B

Need change to LOW actived from KBC GPIO

DY

WHITE

Battery LED2(WHITE_LED)

0706 Modify:
Change WLAN_LED part number to
83.01221.R70 base on latest EMN and DXF.

NEED confirm with ME actual
HDD_LED part number.

WLAN_LED_R

2
390R2J-1-GP

LED-W-27-GP

1

1

84.00143.M11

2

DY

EC6810
Do Not Stuff

PDTA143ET-GP

HDD_LED_A
2
390R2J-1-GP

1
R6812

2

SATA_LED_R

C

Do Not Stuff
EC6811

E

R1

SATA HDD LED(White)

R6814
1

63,82 WLAN_WWAN_LED#

2nd = 83.00110.J70

HDLED1

R2

B

83.01221.R70

NEED confirm with ME actual
HDD_LED part number.

Q6805
SATA_LED#_C

WLAN_LED

0706 Modify:
WLAN__LED# rename to WLAN_WWAN_LED#.

K2

3

2
1

2 POWER_SW_LED_B

1

DYDo Not Stuff

SRN15KJ-3-GP
PWRLED#
SATA_LED#

1A

2 FPOWER_LED_A
390R2J-1-GP

LED-W-27-GP

2

PDTA143ET-GP

1
R6806

EC6801

R1

C

84.00143.M11
27
19

0105 Modify:
Change Part Reference FPOWERLED1 To FPLED1

FPLED1

R2

B

NEED confirm with ME actual
FPOWER_LED part number.

5V_S5

Q6801

PWRLED#_C

R2

Need change to LOW actived from KBC GPIO

D

R6813

TP_LOCK_LED_A
2
390R2J-1-GP

A

K

DN15
Do Not Stuff
Do Not Stuff
2nd = 83.00190.S7A

0928 Modify:
Add 2nd source 83.00326.G70 on
CHARGERLED1from Sourcer Anya suggestion.
1122 Modify:
Change R6813 to 1K from 390ohm for fine tune LED illumination

B

0105 Modify:
Change Part reference name From TPLOCKLED1/TPLOCKLED2 To TPLED1/TPLED2
TPLED1

A

K

DQ15
LED-Y-57-GP
83.01921.P70
2nd = 83.00190.S7A

1

27 KBC_PWRBTN#

R6802

PWRBT1

2
100R2J-2-GP

PWRBT2

5

1

0914:Modify
CONFIRM PWR_BTN_LED# SPEC.
maybe by can combine with FPOWER_LED.
Then PWR_BTN_LED can reserved for other function.

5

1
KBC_PWRBTN#_C
POWER_SW_LED_C
POWER_SW_LED_B

2
3
4

1
KBC_PWRBTN#_C
POWER_SW_LED_C
POWER_SW_LED_B

DQ15

2
3
4

DN15

2

EC6808
EGA10402V12A0-GP

6

0105 Modify:
EMI Request

A

6

ACES-CON4-10-GP-U

Do Not Stuff

20.K0320.004

Do Not Stuff
A

2nd = 20.K0382.004

0304 Modify:
EMI Request To Pop EC6808 83.MS04A.AA0
0321 Modify:
Change EC6808 Source To 83.10402.0A0

0105 Modify:
Change Part reference name From PWRBTN1/PWRBTN2 To PWRBT1/PWRBT2

DQ15 AMD DIS SAMSUNG TI

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

0921:Modify
Add AFTP, Follow DQ15 Intel
KBC_PWRBTN#_C
POWER_SW_LED_C
POWER_SW_LED_B

5

4

1
1
1

Title

LED Bard/Power Button

AFTP6801
AFTP6802
AFTP6803

3

2

Size
A2

Document Number

Date:

Thursday, May 26, 2011

Rev

QUEEN AMD Muxless/UMA
Sheet
1

68

of

X00
104

5

4

3

2

1

SSID = Touch.Pad
1122 Modify:
Add 2nd 20.K0592.030 on KB1 from ME
updated connector list.

0715 Modify:
Add R6908,R6909 for TPAD1 co-lay power option.
0109 Modify:
Change TP_VDD To 3D3V_S0, Follow Intel

Internal KeyBoard Connector
0630 Modify:
Change KB1 part number to 20.K0565.030
base on ME updated EMN and DXF.

0624 Modify:
Removed TP LOCKED CONTROL combin
with KEYBOARD Function KEY.

TP_VDD

5V_S0
R6909

D

AFTP45

31
1

KB_DET# 18

TouchPad Connector
TP_VDD

DY

D

2

Do Not Stuff
3D3V_S0
R6910 1

2 Do Not Stuff

TP_VDD

27

KCOL[0..16]

27

1

RN6901
SRN10KJ-5-GP

C6901
SCD1U10V2KX-5GP

2

KROW[0..7]

TPAD1
6

27
27

4
3
2

TPCLK
TPDATA

CAP_LED_R

0624 Modify:
Add CAP LED Control circuit(Q6902,R6906,R6907)
and Connect CAP_LED_R control to KB1 pin27 from
KBC GPIO(High active).

CAP_LED_R

C6902
Do Not Stuff

1

1

AFTP46
AFTP47
AFTP48
AFTP49
AFTP50
AFTP51
AFTP52
AFTP53
AFTP54
AFTP55
AFTP56
AFTP57
AFTP58
AFTP59
AFTP60
AFTP61
AFTP62
AFTP63
AFTP64
AFTP65
AFTP66
AFTP68
AFTP67
AFTP69
AFTP70

1

2
1

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

3
4

KROW7
KROW6
KROW4
KROW2
KROW5
KROW1
KROW3
KROW0
KCOL5
KCOL4
KCOL7
KCOL6
KCOL8
KCOL3
KCOL1
KCOL2
KCOL0
KCOL12
KCOL16
KCOL15
KCOL13
KCOL14
KCOL9
KCOL11
KCOL10

1

2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
32

0713 Modify:
Change TPAD1 power source to 3D3V_S0 from
5V_S0 base on DELL latest spec A02.

DY DY
2

1

2

KB1

0630 Modify:
Change TPAD1 part number to 20.K0320.006
base on ME updated EMN&DXF.
0712 Modify:
Change TPAD1 part number to 20.K0320.004
from 20.K0320.006.

C6903
Do Not Stuff

1
AFTP71

ACES-CON4-10-GP-U

20.K0320.004

1
AFTP72

C

JAE-CON30-7-GP

20.K0565.030
2nd = 20.K0592.030

5

AFTP73
AFTP74
AFTP75

0921 Modify:
un-stuff R6907 and stuff R6905,Q6902,R6906
for 5V drive CAP LED.
0109 Modify: CAP_LED Change To Low Active From KBC GPIO
0109 Modify: R6906 Change To 1K

1
1
1

TP_VDD
TPCLK
TPDATA

0707 Modify:
Change TPAD1 pin define to follow
TOUCH PAD DATASHEET.
0713 Modify:
Change TPAD1 pin define to follow
TOUCH PAD DATASHEET.

C

CAP LED CONTROL

Low Active from KBC GPIO.

5V_S5

Q6902
R2

R6905
CAP_LED

2

Q6902_B
B

R1

27

1

E

CAP_LED_R
CAP_LED_Q

C

15KR2J-1-GP

CAP_LED_R
2
1KR2J-1-GP

1
R6906

PDTA143ET-GP

84.00143.M11
1
2
R6907 DYDo Not Stuff

0719: EMI Request
B

B

KB Backlight Connector
CAP_LED_R
5V_S0

+5V_KB_BL

EC6901
Do Not Stuff

DY

Do Not Stuff
2 R6902
Do Not Stuff

1

MAX 260mA1123 X02 Modify:

1

2

DY

2
C6905
Do Not Stuff

2

1

F6901
1

DN15

Add 2nd(20.K0613.004)on KBLIT1
from Karl updated.

KBLIT1

DN15

5
1
R6904

2

2
3
4
6

DN15

Do Not Stuff

Do Not Stuff
1
2nd = 20.K0613.004

AFTP82

D

2

DY

Do Not Stuff

C6906

KB_BL_CTRL#

DN15

KB_LED_DET_C

2

Do Not Stuff
R6903
Do Not Stuff

1

DN15

1

1

17 KB_LED_BL_DET

KB_BL_CTRL

DN15

A

2

R6901
Do Not Stuff

Do
Not Stuff
2nd = 84.03404.C31

S

1

27

G

Q6901
Do Not Stuff

A

+5V_KB_BL
KB_LED_DET_C
KB_BL_CTRL#

DN15

1
1
1

AFTP76
AFTP77
AFTP78

DQ15 AMD DIS SAMSUNG TI

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

Key Board/Touch Pad

Size
Document Number
Custom

QUEEN AMD Muxless/UMA

Date:
5

4

3

2

Thursday, May 26, 2011

Sheet
1

69

of

Rev

X00
104

5

4

3

2

1

SSID = Hall.Sensor
D

D

0906 Modify:
HALL SENSOR move to small board at X01 stage,so
Removed HALLSW1 related circuit and add HALL1
connector.

12

HALL1

NP1

1122 Modify:
Add 2nd 20.F0962.010 on HALL1 from
ME updated connector list.

C

C

13

11

10

1

9
8
7
6

2
3
4
5

16

14

LID_CLOSE# 27
3D3V_S5

15
AFTP83 Do Not Stuff
1 3D3V_S5
1 LID_CLOSE#
AFTP84 Do Not Stuff

NP2

AFTP85
TCN-CONN10C-GP

1
Do Not Stuff

20.F1655.010
2nd = 20.F0962.010

B

B

1110 X02 Modify:
Add 2nd 20.F0962.010 on HALL1 from
ME updated connector list.

DQ15 AMD DIS SAMSUNG TI

Wistron Corporation

A

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

Hall Effect Sensor

Size
A4

Document Number

Date:
5

4

3

Rev

QUEEN AMD Muxless/UMA
Thursday, May 26, 2011
2

Sheet

70

of
1

X00
104

A

5

4

3

2

1

SSID = Debug
D

D

3D3V_S0
DB1

1
2
3
4
5
6
7
8
9
10
11
12

17,27 LPC_AD0
17,27 LPC_AD1
17,27 LPC_AD2
17,27 LPC_AD3
17,27 LPC_FRAME#
9,17,82,83 PLT_RST#
17,21 CLK_PCI_LPC

DY

Do Not Stuff

20.D0183.110
C

C

HDT+ Connectors

1D5V_S3

HDT7101

6

Do Not Stuff 1 R7101
DBRDY3
DBRDY2
DBRDY1

APU_TRST#

B

1
3
5
7
APU_TRST#_R 9
11
13
15
17
19

2
DY

CPU_VDDIO
GND
GND
GND
CPU_TRST#
CPU_DBRDY3
CPU_DBRDY2
CPU_DBRDY1
GND
CPU_VDDIO

DY

CPU_TCK
CPU_TMS
CPU_TDI
CPU_TDO
CPU_PWROK_BUF
CPU_RST#_BUF
CPU_DBRDY0
CPU_DBREQ#
CPU_PLLTEST0
CPU_PLLTEST1

2
4
6
8
10
12
14
16
18
20

DY

1
2
3
4

DY11
DY

R7105
R7106

2 Do Not Stuff
2 Do Not Stuff

B

CRB:placed 0-ohm
checklist:if both SCAN and HDT+ header are implement
placed 15-ohm

Do Not Stuff
RN7101

8
7
6
5

APU_TEST19_PLLTEST0_R
APU_TEST18_PLLTEST1_R

APU_TCK 6
APU_TMS 6
APU_TDI 6
APU_TDO 6
H_CPUPW RGD 6,17,36
APU_RST_L_BUF 6
APU_DBRDY 6
APU_DBREQ# 6
APU_TEST19_PLLTEST0 6
APU_TEST18_PLLTEST1 6

DBRDY1
DBRDY2
DBRDY3

Do Not Stuff

0603

DQ15 AMD DIS SAMSUNG TI

Wistron Corporation

A

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

5

4

3

Size
A4

Document Number

Date:

Thursday, May 26, 2011

Dubug connector

QUEEN AMD Muxless/UMA
2

Sheet

71

of
1

Rev

X00
104

A

5

4

3

2

1

D

D

C

C

(Blanking)

B

B

A

A

DQ15 AMD DIS SAMSUNG TI

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

5

4

3

2

Size
A3

Document Number

Date:

Thursday, May 26, 2011

RESERVED

Rev

QUEEN AMD Muxless/UMA
Sheet
1

72

of

X00
104

5

4

3

2

1

D

D

C

C

B

B

DQ15 AMD DIS SAMSUNG TI

A

A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

5

4

3

2

Size
A3

Document Number

Date:

Thursday, May 26, 2011

Reserved

Rev

QUEEN AMD Muxless/UMAX00
Sheet
1

73

of

104

5

4

3

2

1

SSID = SDIO

1
C7405
2

DY

D

Do Not Stuff

1
2

C7404
SC2D2U6D3V3MX-1-GP

1
2

C7403
SCD01U16V2KX-3GP

1

DY
2

2

DY

Close to CARD1
C7402
Do Not Stuff

1

C7401
Do Not Stuff

3D3V_CARD_S0

D

SD/XD/MS/MMC+ Card Reader
3D3V_CARD_S0

CARD1
P13
P22
18

C

32
32
32
32

SP4
SP3
SP13
SP12

P4
P3
P25
P23

32
32
32
32

SP8
SP6
SP1
SP10

P10
P1
P2
P19

32
32
32

SP14
SP2
SP1

P9
P16
P20

32
32
32
32

SP9
SP12
SP8
SP5

P12
P11
P14
P18

32
32
32
32

SP11
SP9
SP7
SP5

P21
P17
P8
P5

SD_VCC

XD_CD
XD_R/B
XD_RE
XD_CE
XD_CLE
XD_ALE
XD_WE
XD_WP_IN

MS_VCC
XD_VCC
SD_DAT0
SD_DAT1
SD_DAT2
SD_DATA3

XD_D0
XD_D1
XD_D2
XD_D3
XD_D4
XD_D5
XD_D6
XD_D7

SD_CLK
SD_CD
SD_WP
SD_CMD
MS_BS
MS_INS
MS_SCLK

SD_WP_COM/SDIO_GND
SD_CD_COM/SDIO_GND
SD_GND
SD_GND

MS_DATA0
MS_DATA1
MS_DATA2
MS_DATA3

MS_GND
MS_GND
XD_GND
XD_GND

MMC_DATA4
MMC_DATA5
MMC_DATA6
MMC_DATA7

NP1
NP2

1
2
3
4
5
6
7
8

XD_CD#
SP1
SP2
SP3
SP4
SP5
SP6
SP7

32
32
32
32
32
32
32
32

10
11
12
13
14
15
16
17

SP8
SP9
SP10
SP11
SP12
SP13
SP14
XD_D7

32
32
32
32
32
32
32
32

P26
P27
P7
P15
P6
P24
9
19

0906 Modify:
Change CARD1 to 20.I0129.001 from 62.10051.931
from ME double updated latest DXF&EMN on X01.

NP1
NP2

0928 Modify:
Updated CARD1 footprint to R013-P12-HM-1
from data base updated footprint.

CARD-PUSH-46P-1-GP-U

20.I0129.001

1122 Modify:
Add 2nd 20.I0135.001 on CARD1 from
ME updated latest connector list.

2nd = 20.I0135.001
B

PCB Footprint = R013-P12-HM-1

For EMI Reserved

C

B

1

EC7417
Do Not Stuff

DY
2

1

DY
2

2

DY

EC7416
Do Not Stuff

1

EC7415
Do Not Stuff

1

DY
2

2

DY

EC7414
Do Not Stuff

1

EC7413
Do Not Stuff

1

DY
2

2

DY

EC7412
Do Not Stuff

1

EC7411
Do Not Stuff

1

DY
2

2

DY

EC7410
Do Not Stuff

1

EC7409
Do Not Stuff

1

DY
2

2

DY

EC7408
Do Not Stuff

1

EC7407
Do Not Stuff

1

DY
2

2

DY

EC7406
Do Not Stuff

1

EC7405
Do Not Stuff

1

DY
2

1

EC7404
Do Not Stuff

2

DY
2

DY

A

EC7403
Do Not Stuff

1

EC7402
Do Not Stuff

SP1
SP2
SP3
SP4
SP5
SP6
SP7
SP8
SP9
SP10
SP11
SP12
SP13
SP14
XD_D7
XD_CD#

A

DQ15 AMD DIS SAMSUNG TI

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

0913: Schematic Score Card Suggest Cap Less Than 10P

5

4

3

2

CARD Reader CONN

Size
A3

Document Number

Date:

Thursday, May 26, 2011

QUEEN AMD Muxless/UMA
Sheet
1

74

of

Rev

X00
104

5

4

3

2

1

SSID = ExpressCard

D

D

1D5V_S0_CARD Max. 650mA, Average 500mA.
3D3V_S0_CARD Max. 1300mA, Average 1000mA
3D3V_S5_CARDAUX Max. 275mA

SB-25
NEW1
27
1
1122 X02 Modify:
Change TR7501 CM choke to 69.10103.041
and un-stuff R7501,R7502 from EMC Neo Suggestion.
Change R7501,R7502 to 0603 from 0402.
1123 X02 Modify:
SWAP TR7501 pin1&4 and pin2&3 each other
base on Connie swap report.

R7505 1

17

PCIE_TXP5

17

PCIE_TXN5

17
17

PCIE_RXP5
PCIE_RXN5

17 CLK_PCIE_NEW
17 CLK_PCIE_NEW#

C

18 CLK_PCIE_NEW_REQ#
3D3V_S0
18

USB_PP8

R7501
1

2Do Not Stuff

3D3V_S5
27,82 PCIE_WAKE#
1D5V_S0

USB_PP8_R

DY

14,18 SMB_DATA
14,18 SMB_CLK
18,27,44 PM_SLP_S5#
18,27,36,44,46 PM_SLP_S3#
18 FCH_PCIE_RST#

Do Not Stuff
2

1

DN15

3

4

TR7501

2 Do Not Stuff
PCIE_TXP5_CON
PCIE_TXN5_CON
R7506
1
2
Do Not Stuff
PCIE_RXP5_CON
R7508 1 Do Not Stuff
2
PCIE_RXN5_CON
R7507 1 Do Not Stuff
2

2
3
4
5
6
7
CLK_PCIE_NEW_C8
R7503 1
2
CLK_PCIE_NEW#_C 9
R7504 1 Do Not Stuff
2
Do Not Stuff
10
R7509 1
2 CLK_PCIE_NEW_REQ#_CON
11
Do Not Stuff
12
13
14
15
PCIE_WAKE#_CON
R7510 1
Do
Not
Stuff
2
16
17
18
SMB_DATA
19
SMB_CLK
20
PM_SLP_S5#
21
PM_SLP_S3#
22
FCH_PCIE_RST#
23
USB_PP8_R
24
USB_PN8_R
25
26

Do Not Stuff
18

USB_PN8

R7502
1

2Do Not Stuff

C

DN15

28
Do Not Stuff

1214: Modify To RST Due To Use FCH GPP

USB_PN8_R

Do Not Stuff

DY

2nd = 20.K0382.026

For EMI

EC7507

Do Not Stuff

1

1

DY
DY
Do Not Stuff

Do Not Stuff

EC7508

DY
DY
Do Not Stuff

EC7504

1

EC7503

1

EC7506

2

2

2
EC7505

DY
DY
Do Not Stuff
1

Do Not Stuff

1

EC7502

2

EC7501

DY
DY
Do Not Stuff

B

CLK_PCIE_NEW_REQ#
PCIE_WAKE#
2

PCIE_TXP5_CON
PCIE_TXN5_CON
PCIE_RXP5
PCIE_RXN5

2

CLK_PCIE_NEW#_C
CLK_PCIE_NEW_C
2

3D3V_S5
3D3V_S0
1D5V_S0
USB_PN8_R
USB_PP8_R
CLK_PCIE_NEW_REQ#_CON
SMB_CLK
SMB_DATA
PM_SLP_S3#
PM_SLP_S5#
FCH_PCIE_RST#
CLK_PCIE_NEW#_C
CLK_PCIE_NEW_C
PCIE_TXN5_CON
PCIE_TXP5_CON
PCIE_RXN5_CON
PCIE_RXP5_CON
PCIE_WAKE#_CON

1

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

2

AFTP107
AFTP108
AFTP109
AFTP110
AFTP111
AFTP112
AFTP113
AFTP114
AFTP115
AFTP116
AFTP117
AFTP118
AFTP119
AFTP120
AFTP121
AFTP122
AFTP123
AFTP124

1

Do Not Stuff
Do Not Stuff
Do Not Stuff
Do Not Stuff
Do Not Stuff
Do Not Stuff
Do Not Stuff
Do Not Stuff
Do Not Stuff
Do Not Stuff
Do Not Stuff
Do Not Stuff
Do Not Stuff
Do Not Stuff
Do Not Stuff
Do Not Stuff
Do Not Stuff
Do Not Stuff

B

Do Not Stuff

DQ15 AMD DIS SAMSUNG TI
A

A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

5

4

3

2

Size
A3

Document Number

Date:

Thursday, May 26, 2011

Express Card

Rev

QUEEN AMD Muxless/UMA
Sheet
1

75

of

X00
104

5

4

3

2

1

D

D

C

C

(Blanking)

B

B

DQ15 AMD DIS SAMSUNG TI

Wistron Corporation

A

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
A4

Document Number

Date:
5

4

3

Reserved

Rev

QUEEN AMD Muxless/UMAX00
Thursday, May 26, 2011
2

Sheet

76

of
1

104

A

5

4

3

2

1

D

D

C

C

(Blanking)

B

B

DQ15 AMD DIS SAMSUNG TI

A

A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

5

4

3

2

Size
A3

Document Number

Date:

Thursday, May 26, 2011

Reserved

Rev

QUEEN AMD Muxless/UMAX00
Sheet
1

77

of

104

5

4

3

2

1

D

D

C

C

(Blanking)

B

B

DQ15 AMD DIS SAMSUNG TI

Wistron Corporation

A

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
A4

Document Number

Date:
5

4

3

Reserved

Rev

QUEEN AMD Muxless/UMAX00
Thursday, May 26, 2011
2

Sheet

78

of
1

104

A

5

4

3

2

1

SSID = User.Interface
D

D

Free Fall Sensor
Note
- no via, trace, under the sensor (keep out area around 2mm)
- stay away from the screw hole or metal shield soldering joints
- design PCB pad based on our sensor LGA pad size (add 0.1mm)
- solder stencil opening to 90% of the PCB pad size
- mount the sensor near the center of mass of the NB as possible as you can

3D3V_S0

1

DN15

1

C7902
Do Not Stuff
Do Not Stuff

C7901

2

3D3V_S0

3
11

C

R7903
Do Not Stuff

9

DN15

CS

DN15

GND
GND
GND
GND

RESERVED#3
RESERVED#11

2
4
5
10

FALL_INT2

0906: Need Pop R7906 ?
3D3V_S0
1

1

3D3V_S5

Do Not Stuff

5V_S0

Q7901
Do Not Stuff

Do Not Stuff
2nd = 84.DM601.03F

DN15

DY R7907 DY R7904

Do Not Stuff

DY R7906

0901 X01 Modify:
U7901 G-SENSOR MAIN SOURCE change to
ST(74.00351.0B3),2nd change to ADI(74.00345.0BZ)

Do Not Stuff

2

Do Not Stuff Do Not Stuff

2

09/0422
(#1) Just pull +3.3V_RUN ~ Ref. Rothschild
(#2) FAE/ DY is ok, chip internal pull-up resistors
(#3) From spec, Slave ADdress(SAD) is 001110xb
Pull HIGH SAD is 0011101b
Pull GND SAD is 0011100b

1

INT2

SDO

1

7

SDA/SDI/SDO

2

12

17

2

13

HDD_FALL_INT1

1

PCH_SMBDATA
R7901
2 HDD_FALL_SDO
Do Not Stuff

3D3V_S0
HDD_FALL_INT1

2

DY

8

3

1

INT1

6

3D3V_S0

SCL/SPC

5

14

R7902
Do Not Stuff

4

PCH_SMBCLK
C

DY
2

6
VDD

14,15,82 PCH_SMBCLK
14,15,82 PCH_SMBDATA

VDD_IO

U7901

1

1

2

DY

FFS_INT2_R

FFS_INT2
1

56

2
DY R7905
Do Not Stuff

0906: Follow DQ15 Intel to Change Main Source To ST

FFS_INT2_R

18

B

B

Note
(1) Keep all signals are the same trace width. (included VDD, GND).
(2) No VIA under IC bottom.

DQ15 AMD DIS SAMSUNG TI

A

A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

5

4

3

2

Size
A3

Document Number

Date:

Thursday, May 26, 2011

Free Fall Sensor

Rev

QUEEN AMD Muxless/UMAX00
Sheet
1

79

of

104

5

4

3

2

1

D

D

(Blanking)

C

C

B

B

DQ15 AMD DIS SAMSUNG TI

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

A

Title

5

4

3

Size
A

Document Number

Date:

Thursday, May 26, 2011

Reserved

Rev

QUEEN AMD Muxless/UMAX00
2

Sheet

80

of
1

104

A

5

4

3

2

1

D

D

(Blanking)

C

C

B

B

DQ15 AMD DIS SAMSUNG TI

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

A

A

Title

UNUSED PARTS/EMI Capacitors

Size
A4

Document Number

QUEEN AMD Muxless/UMA

Date:
5

4

3

Thursday, May 26, 2011
2

Sheet

81

of
1

Rev

X00
104

5

4

3

2

1

IO Board CONN 80 pin
IOBD1
ACES-CONN80D-1-GP

82
NP1
1

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80

62 USB30_TXDN2_R
62 USB30_TXDP2_R

USB 3.0 (1) Port 3

62 USB30_RXDN2_R
62 USB30_RXDP2_R
17 CLK_PCIE_LAN#
17 CLK_PCIE_LAN

LAN CLK
D

17 CLK_PCIE_WLAN
17 CLK_PCIE_WLAN#

WLAN CLK

4
4

LAN PCIE RX

PCIE_RXN2
PCIE_RXP2

4 PCIE_RXP0
4 PCIE_RXN0

LAN PCIE TX

4 PCIE_TXP0
4 PCIE_TXN0

WLAN SMBUS

27
27
14,15,79
14,15,79
27,63
29
29
29
29
29
29
27
63,68
18
18
27,57
18

E51_RXD
E51_TXD
PCH_SMBDATA
PCH_SMBCLK
BLUETOOTH_EN
MIC_IN_L
EXT_MIC_JD#
MIC_IN_R
AUD_HP1_JACK_L2
AUD_HP1_JD#
AUD_HP1_JACK_R2
WIFI_RF_EN
WLAN_WWAN_LED#
USB_OC#2
USB_OC#5
USB_IO_CRT_EN#
PCIE_CLK_LAN_REQ#

3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
NP2
81

USB30_RXDP3_R
USB30_RXDN3_R

62
62

USB30_TXDP3_R
USB30_TXDN3_R

62
62

USB 3.0 Port 4

USB20_DP2
USB20_DM2

18
18

USB2.0 Port 3

USB20_DP3
USB20_DM3

18
18

USB 2.0 Port 4

D

USB_PP1 18
USB_PN1 18
PCIE_TXP2
PCIE_TXN2

4
4

WLAN USB

CLK_PCIE_WLAN_REQ#
5V_S5

18

WLAN PCIE
3D3V_S0

3D3V_S5
1D5V_S0
PM_LAN_ENABLE 27
PLT_RST#
9,17,71,83
PCIE_WAKE# 27,75
BT_ACT
63
WLAN_ACT 63

20.F1849.080
2nd = 20.F1908.080

C

C

0706 Modify: ADD WLAN_LED, Follow Intel, AMD Dont have
WWAN

CRTBD1

94 CRT_RED_R

CRT RGB

94 CRT_GREEN_R
94 CRT_BLUE_R

CRT SMBUS
CRT H/VSYNC

at least 80 mil

USB30_VCCB

43
2

41
1

4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
46

3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
44

CRT_RED_R
CRT_GREEN_R
CRT_BLUE_R

AD+

AFTP5004
AFTP5005
AFTP5006

1
1
1

5V_CRT_S0_R

5V_CRT_S0

5V_S0
D8201

F8201

1

2

2

1

FUSE-1D1A6V-4GP-U
USB30_TXDP1_R
USB30_TXDN1_R
USB30_RXDP1_R
USB30_RXDN1_R
USB20_DM1
USB20_DP1

USB30_TXDP1_R
USB30_TXDN1_R
USB30_RXDP1_R
USB30_RXDN1_R
USB20_DM1
USB20_DP1

18
18

62
62

69.50007.691

USB 3.0 PORT1

62
62

CH551H-30PT-GP

0906 Modify:
Change Part Number 20.K0422.010 To20.K0320.008
Base On ME Connector List
0914 Modify:
Change R8201~R8203 to 470 ohm from 33ohm
for fine tune MEDIA LED 5mA current.
0928 Modify:
Change R8201~R8203 to 430 ohm from 470 ohm
for fine tune MEDIA LED 5mA current.

USB 2.0 PORT11

45
NP2

B

94 CRT_VSYNC_R
94 CRT_HSYNC_R
94
DDCCLK
94
DDCDATA
5V_CRT_S0_R
3D3V_S0
5V_S5
3D3V_S5
27
PSID_EC
27
RCID

42
NP1

1123 Modify: Change Main Source To 20.F1849.080 & Add 2nd 20.F1908.080 on IOBD1 from
ME updated latest connector list & Modify Pin Define So 4 corner pin are GND.

20.F1121.040
2nd = 20.F0085.040

B

ACES-CONN40D-GP

0914 Modify:
Change BTB Connector To 20.F1121.040
Follow ME Connector List
1228 Modify:
Remove USB 3.0 Signal and Re-arrange Pin-Define For Better Layout Routing

0105:Modify
EMI Neo Suggest To Reserve, Close To Media Buttom Board

1
1
1
1
1
1

5V_S5

2
DY
2Do Not Stuff
DY
2Do Not Stuff
DY
2Do Not Stuff
DY
2Do Not Stuff
DY
2Do Not Stuff
DY
Do Not Stuff

2

MEDIA_LED1#
MEDIA_LED2#
EC8203
MEDIA_LED3#
EC8204
INSTANT_ON#
EC8205
DATA_RECOVERY#EC8206
MEDIA_BTN3#
EC8207
EC8208

DY
1

1118 Modify:
Modify Pin Define

EC8209
Do Not Stuff

MEDIA1

9
1
0902 X01 Modify:
Add F8201,D8201 sync with DQ15-NV.
Rename CRTBD1 pin24 power to 5V_CRT_S0_R.

A

0916 X01 Modify:
Change R8201~R8203 to 430ohm from 100ohm.
Add R8204,R8205,R8208 PH 5V_S5 on
MEDIA_LED1~3# for PWM OD mode.

2
3
4
5
6
7
8

5V_S5

5V_S5
MEDIA1_1
1
MEDIA1_2 R8201
1
MEDIA1_3 R8202
1
R8203

2
21KR2J-1-GP
21KR2J-1-GP
1KR2J-1-GP

Low active
MEDIA_LED1# 27
MEDIA_LED2# 27
MEDIA_LED3# 27
INSTANT_ON# 27
DATA_RECOVERY#
MEDIA_BTN3# 27

MEDIA_LED1#
1
MEDIA_LED2# R8204
1
MEDIA_LED3# R8205
1
R8208

DY
DY
DY

2
2Do Not Stuff
2Do Not Stuff

A

Do Not Stuff

27

0921:Modify
Add AFTP, Follow DQ15 Intel

10
ACES-CON8-19-GP

AFTP8201
AFTP8202
AFTP8203
AFTP8204
AFTP8205
AFTP8206
AFTP8207

20.K0320.008
1122 Modify:
change Media resistor from 430 ohm to 1K on both DQ/DN15
(R8201, R8202, R8203) for Media button LED light spot issue

1
1
1
1
1
1
1

MEDIA1_1
MEDIA1_2
MEDIA1_3
5V_S5
INSTANT_ON#
DATA_RECOVERY#
MEDIA_BTN3#

DQ15 AMD DIS SAMSUNG TI

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

Size
A2
Date:

5

4

3

2

IO Board Connector
Document Number

Rev

QUEEN AMD Muxless/UMA
Sheet

Thursday, April 21, 2011
1

82

of

X00
104

5

4

VGA1A

3

4 PEG_TXP[8..15]

PEG_RXP[8..15]

4

4 PEG_TXN[8..15]

PEG_RXN[8..15]

4

AA38
Y37
Y35
W36
W38
V37

D

V35
U36

T35
R36
R38
P37
P35
N36
PEG_TXP8
PEG_TXN8

C

N38
M37

PEG_TXP9
PEG_TXN9

M35
L36

PEG_TXP10
PEG_TXN10

L38
K37

PEG_TXP11
PEG_TXN11

K35
J36

PEG_TXP12
PEG_TXN12

J38
H37

PEG_TXP13
PEG_TXN13

H35
G36

PEG_TXP14
PEG_TXN14

G38
F37

PEG_TXP15
PEG_TXN15

F35
E37

PCIE_RX0P
PCIE_RX0N

PCIE_TX0P
PCIE_TX0N

PCIE_RX1P
PCIE_RX1N

PCIE_TX1P
PCIE_TX1N

PCIE_RX2P
PCIE_RX2N

PCIE_TX2P
PCIE_TX2N

PCIE_RX3P
PCIE_RX3N

PCIE_TX3P
PCIE_TX3N

PCIE_RX4P
PCIE_RX4N

PCIE_TX4P
PCIE_TX4N

PCI EXPRESS INTERFACE

U38
T37

2

1 OF 8

PCIE_RX5P
PCIE_RX5N
PCIE_RX6P
PCIE_RX6N
PCIE_RX7P
PCIE_RX7N
PCIE_RX8P
PCIE_RX8N
PCIE_RX9P
PCIE_RX9N
PCIE_RX10P
PCIE_RX10N
PCIE_RX11P
PCIE_RX11N
PCIE_RX12P
PCIE_RX12N

PCIE_TX5P
PCIE_TX5N
PCIE_TX6P
PCIE_TX6N
PCIE_TX7P
PCIE_TX7N

Y33
Y32
W33
W32
U33
U32
U30
U29
T33
T32
T30
T29
P33
P32

PCIE_TX9P
PCIE_TX9N
PCIE_TX10P
PCIE_TX10N
PCIE_TX11P
PCIE_TX11N
PCIE_TX12P
PCIE_TX12N

PCIE_RX13P
PCIE_RX13N

PCIE_TX13P
PCIE_TX13N

PCIE_RX14P
PCIE_RX14N

PCIE_TX14P
PCIE_TX14N

PCIE_RX15P
PCIE_RX15N

PCIE_TX15P
PCIE_TX15N

PEG_C_RXP8 C8318
PEG_C_RXN8 C8317

1
2
DIS_PX
1
2
DIS_PX

SCD1U10V2KX-5GP
SCD1U10V2KX-5GP

PEG_C_RXP9 C8320
PEG_C_RXN9 C8319

1
2
DIS_PX
1
2
DIS_PX

SCD1U10V2KX-5GP
SCD1U10V2KX-5GP

PEG_RXP9
PEG_RXN9

L33
L32

PEG_C_RXP10C8321
PEG_C_RXN10C8322

1
2
DIS_PX
1
2
DIS_PX

SCD1U10V2KX-5GP
SCD1U10V2KX-5GP

PEG_RXP10
PEG_RXN10

L30
L29

PEG_C_RXP11C8323
PEG_C_RXN11C8324

1
2
DIS_PX
1
2
DIS_PX

SCD1U10V2KX-5GP
SCD1U10V2KX-5GP

PEG_RXP11
PEG_RXN11

K33
K32

PEG_C_RXP12C8325
PEG_C_RXN12C8326

1
2
DIS_PX
1
2
DIS_PX

SCD1U10V2KX-5GP
SCD1U10V2KX-5GP

PEG_RXP12
PEG_RXN12

J33
J32

PEG_C_RXP13C8328
PEG_C_RXN13C8327

1
2 SCD1U10V2KX-5GP
DIS_PX
1
2 SCD1U10V2KX-5GP
DIS_PX

PEG_RXP13
PEG_RXN13

K30
K29

PEG_C_RXP14C8330
PEG_C_RXN14C8329

1
2
DIS_PX
1
2
DIS_PX

SCD1U10V2KX-5GP
SCD1U10V2KX-5GP

PEG_RXP14
PEG_RXN14

H33
H32

PEG_C_RXP15C8332
PEG_C_RXN15C8331

1
2
DIS_PX
1
2
DIS_PX

SCD1U10V2KX-5GP
SCD1U10V2KX-5GP

ATI_RST#

1

2

AJ21
AK21
PWRGOOD AH16
10KR2F-2-GP
VGA_RST# AA30

2
Do Not Stuff

B

PEG_RXP15
PEG_RXN15

GPIO1

PCIE TRANSMITTER DE-EMPHASIS ENABLED
0:Tx de-emphasis disabled 1:Tx de-emphasis enabled

X

1

BIF_GEN2_EN_A

GPIO2

0:Advertises the PCIe device as 2.5GT/s capable at power on.
1:Advertises the PCIe device as 5.0GT/s capable at power on.

0

1

GPIO5_AC_BATT

GPIO5

optional input allow the system to request a fast
power reduction by setting GPIO5 to low.

?

0

RESERVED

GPIO8

0

0

VGA_DIS

GPIO9

ROMIDCFG[2:0]

GPIO[13:11]

RESERVED

GPIO21

NC#AJ21
NC#AK21
PWRGOOD

PCIE_CALRP
PCIE_CALRN

V2SYNC

Y30

PCIE_CALRP

Y29

PCIE_CALRN

R8316 DIS_PX
1V_VGA_S0
1
2
1K27R2F-L-GP
1
2
R8318 DIS_PX 2KR2F-3-GP

PX4.0

DGPU

H

H

X

0
0 0 1
(256MB)

0

0:Disable external BIOS ROM device
1:Enable external BIOS ROM device

0

X

VIP Device Strap Enable indicates to the software driver that it sense
whether or not a VIP device is connected on the VIP Host interface.

0

X

0
0

0

0

X

1

X

1

AUD[1]

HSYNC

AUD[0]

VSYNC

AUD[1:0]:11-Audio for both DisplayPort and HDMI

C

R8301

1

R8302

1

85 BIF_GEN2_EN_A

R8303

1

DIS_PX
2

DIS_PX
2

DIS_PX
DY

3KR2J-2-GP

2

10KR2J-3-GP

2

Do Not Stuff

2

Do Not Stuff

R8304

1

VGA_DIS

R8305

1

85

CONFIG0

R8306

1

85

CONFIG1

R8307

1

85

CONFIG2

R8308

1

2

Do Not Stuff

R8309

1

DY

2

Do Not Stuff

R8310

1

DY

2

Do Not Stuff

R8311

1

2

Do Not Stuff

2

Do Not Stuff

2

Do Not Stuff

2

Do Not Stuff

2

Do Not Stuff

85 GPIO5_AC_BATT
85 GPIO21_BB_EN

R8312

1

R8313

1

R8314

1

R8315

1

DIS_PX
DY
DY

DY
DY
DY
DY
DY

0716: Modify Dummy Name

3KR2J-2-GP

85

DY

3D3V_VGA_S0

3D3V_VGA_S0

PIN STRAPS

85 TX_DEEMPH_EN

85 BIOS_ROM_EN

H

RESERVED

X

RESERVED

85,94 VGA_CRT_HSYNC

L

X

GENERICC

85 HSYNC_DAC2

PX3.0

BIOS_ROM_EN=1, Config[2:0] defines the ROM type
BIOS_ROM_EN=0, Config[2:0] defines the primary memory aperture size

RSVD

85,94 VGA_CRT_VSYNC

IGPU

0

0

85 VSYNC_DAC2

PE_GPIO0

0:VGA Controller capacity enabled
1:The device won't be recognized as the system's VGA controller

RESERVED

1
2

DY

RESERVED

H2SYNC

DIS_PX

C8333
Do Not Stuff

D

RSVD

85 GPIO8_ROMSO

ROBSON-PRO-M2-GP

DIS_PX

1

TX_DEEMPH_EN

DG DY, CHECK

PCIE_REFCLKP
PCIE_REFCLKN

PERST#

X

85 TX_PWRS_ENB

CALIBRATION

DIS_PX

1
R8317
R8320

PLATFORM
SETTING

Transmitter Power Savings Enable
0: 50% Tx output swing 1: Full Tx output swing

Full Tx output swing. Must be pulled to 3.3 V at reset using ~3-K (5%) resistor.

CLOCK

AB35
AA36

17 CLK_PCIE_VGA
17 CLK_PCIE_VGA#

RECOMMEND

PIN
GPIO0

PEG_RXP8
PEG_RXN8

N30
N29

DESCRIPTION OF DEFAULT SETTINGS

STRAPS
TX_PWRS_ENB

BIOS_ROM_EN GPIO_22_ROMCSB

P30
P29
N33
N32

RECOMMENDED SETTINGS
0= DO NOT INSTALL RESISTOR
1 = INSTALL 3K RESISTOR
X = DESIGN DEPENDANT
NA = NOT APPLICABLE

ALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE GPIOS ARE USED,
THEY MUST NOT CONFLICT DURING RESET

VIP_DEVICE_STRAP_EN

PCIE_TX8P
PCIE_TX8N

1

CONFIGURATION STRAPS

2

10KR2J-3-GP

2

Do Not Stuff

85 JTAG_TMS_VGA

DY

R8325 1

DY

2R8331
84

TESTEN

85 JTAG_TCK_VGA

R8323 1
R8322 1

1 Do Not Stuff

DIS_PX
R8332

1

85 JTAG_TRST#_VGA

2 Do Not Stuff

2
5K1R2F-2-GP

DIS_PX

2 10KR2J-3-GP

DY

2 Do Not Stuff
B

JTAG SIGNAL OPTION - for option2
3D3V_VGA_S0
R8330

1

3D3V_VGA_S0

U8302
1D8V_S0_VGA_PG_R

2
Do Not Stuff

1

93 1D8V_S0_VGA_PG

DY
2

DIS_PX

C8334
Do Not Stuff

1
2
3

B
VCC

A

DIS_PX
Y

U8303

4

GND

17

74LVC1G08GW-1-GP

9,17,71,82

PLT_RST#

1

R8326
2 PLT_RST#_R
Do Not Stuff

Signal

Normal
mode

TESTEN

"1"(PU) "1"(PU)

Debug
mode

pilot run
mode
"0"(PD)

"0"(PD) "1"(PU)

NC

5
U8302_4

1

PE_GPIO0

2

B

5
VCC
ADIS_PX
4
Y
3
GND
74LVC1G08GW-1-GP

73.01G08.L04
2ND = 73.7SZ08.DAH

JTAG_TRST#

ATI_RST#

JTAG_TCK

73.01G08.L04
2ND = 73.7SZ08.DAH

CLK

JTAG_TMS

"1"(PU)

NC

"1"(PU) "1"(PU)

NC

DIS_PX
0113: Remove APU_RST# Level Shift

1008: Add Level Shift For APU_RST# To 3.3V

A

A

DQ15 AMD DIS SAMSUNG TI

0113: Remove APU_RST# Colay

R8328
PLT_RST#

2

PE_GPIO0

2

DY

1

Wistron Corporation

ATI_RST#

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

R8329
Do
Not Stuff

DY

1

ATI_RST#

Title

GPU_PCIE/STRAPPING(1/5)

Do Not Stuff
Size

Document Number

Custom
Date:
5

4

3

2

QUEEN AMD Muxless/UMA

Thursday, May 26, 2011

Sheet
1

83

of

Rev

X00
104

CASA0#
CASA1#
CSA0_0#
CSA0_1#
CSA1_0#
CSA1_1#

MVREFDA
MVREFSA

CKEA0
CKEA1

MEM_CALRN0
MEM_CALRN1
MEM_CALRN2

WEA0#
WEA1#

MEM_CALRP1
MEM_CALRP0
MEM_CALRP2

MAA0_8
MAA1_8

88
88
88
88
89
89
89
89

J21
G19
H27
G27
J14
H14
K23
K19

ODTA0
ODTA1

88
89

CLKA0
CLKA0#

88
88

CLKA1
CLKA1#

89
89

RASA0#
RASA1#

88
89

CASA0#
CASA1#

88
89

K24
K27

CSA0#_0

88

M13
K16

CSA1#_0

89

CKEA0
CKEA1

88
89

WEA0#
WEA1#

88
89

K20
K17

K21
J20
K26
L15
H23
J19

MAA13

CLKTESTA_C

83

C8407
Do Not Stuff
1
2

CLKB1
CLKB1#

TESTEN

RASB0#
RASB1#
CASB0#
CASB1#
CSB0_0#
CSB0_1#
CSB1_0#
CSB1_1#
CKEB0
CKEB1

MVREFDB
MVREFSB

TESTEN
CLKTESTA
CLKTESTB

QSBP_0
QSBP_1
QSBP_2
QSBP_3
QSBP_4
QSBP_5
QSBP_6
QSBP_7

90
90
90
90
91
91
91
91

G7
K1
P1
W4
AC4
AH3
AJ8
AM3

QSBN_0
QSBN_1
QSBN_2
QSBN_3
QSBN_4
QSBN_5
QSBN_6
QSBN_7

90
90
90
90
91
91
91
91

T7
W7

CLKTESTA

1

1

Whistler

DY

DY
2

R8419
Do Not Stuff

1D5V_VGA_S0

2

Modify Dummy Name For Co-lay

90
90

CLKB1
CLKB1#

91
91

RASB0#
RASB1#

90
91

CASB0#
CASB1#

90
91

P10
L10

CSB0#_0

90

AD10
AC10

CSB1#_0

91

CKEB0
CKEB1

90
91

WEB0#
WEB1#

90
91

AD8
AD7

MAB0_8
MAB1_8

DRAM_RST

T10
Y10
W10
AA10

U10
AA11
N10
AB11
T8
W8

MAB13

2

R8418
Do Not Stuff

route 50ohms single-ended/100ohms diff and keep short
Debug only, for clock observation, if not needed, DNI

B

Place all these components very close to GPU (Within
25mm) and keep all component close to each Other

**

This basic topology should be used for DRAM_RST for
DDR3/GDDR3/GDDR5.These Capacitors and Resistor values
are an example only. The Series R and || Cap values
will depend on the DRAM load and will have to be
calculated for different Memory ,DRAM Load and board
to pass Reset Signal Spec.

SCD1U10V2KX-5GP

DDR3/GDDR3 Memory Stuff Option(Mad/Park)

2

MVREFSB

Rb

GDDR3

DDR3

1.8V/1.5V

1.5V

Ra

40.2R

40.2R

40.2R

Rb

100R

100R

100R

1

GDDR5
1.5V

DIS_PXC8405

R8417
100R2F-L1-GP-U

DIS_PX

MVDDQ

2

DIS_PXC8404

R8416
100R2F-L1-GP-U

DIS_PX

R8413
40D2R2F-GP

DIS_PX

SCD1U10V2KX-5GP

2

Rb

1

Whistler C8403
R8415
Rb Do Not Stuff
Do Not Stuff
Whistler
2

2

Do Not Stuff

MVREFDB

2

2

1
2

Whistler C8402
Whistler R8414
Rb Do Not Stuff

Ra

DIS_PX

1

Ra
MVREFSA

VANCOUVER

1

1

1

1
2
1

Whistler
R8409 1
Do Not Stuff

Ra

Whistler
MVREFDA

2

MEM_CALRP2

Ra
Whistler

DIS_PX

1D5V_VGA_S0

R8412
40D2R2F-GP

1

2

DIS_PX
R8407 1
243R2F-2-GP

1D5V_VGA_S0

R8411
Do Not Stuff

2

MEM_CALRP1

1D5V_VGA_S0

R8410
Do Not Stuff

2

2

1D5V_VGA_S0

1

2

MEM_CALRP0

MEM_RST 88,89,90,91

C8401

DIS_PX

*

MEM_CALRN1

Whistler

DIS_PX

R8401
Do Not Stuff

2
51R2J-2-GP

If for Mannhatton,have to change to other value

PLACE MVREF DIVIDERS AND CAPS CLOSE TO ASIC

R8408 1
Do Not Stuff

DY

90,91

R8404
5K1R2F-2-GP

R8405
MEM_CALRN2

1D5V_VGA_S0

CLKTESTB

MEM_CALRN0

2
R8406

C

EC8401

DY

1 R8420 2 DRAM_RST_RC
1
10R2J-2-GP
R8402

ROBSON-PRO-M2-GP

R8403

Whistler

DRAM_RST_RC

DIS_PX

DRAM_RST

AH11

DY

1

1
243R2F-2-GP

0109: EMI Reserve, Place Near C8401
90
91

CLKB0
CLKB0#

DIS_PX

1
Do Not Stuff

90
90
90
90
91
91
91
91

ODTB0
ODTB1

L9
L8

DY
C8406
Do Not Stuff
CLKTESTB_C 1
2

2

CLKB0
CLKB0#

F6
K3
P3
V5
AB5
AH1
AJ9
AM5

DIS_PX

ROBSON-PRO-M2-GP

1
Do Not Stuff

ADBIB0/ODTB0
ADBIB1/ODTB1

WEB0#
WEB1#
AD28
CLKTESTA AK10
CLKTESTB AL10

DIS_PX

B

88,89

MVREFDB
Y12
MVREFSB AA12

DDBIB0_0/QSB_0B/WDQSB_0
DDBIB0_1/QSB_1B/WDQSB_1
DDBIB0_2/QSB_2B/WDQSB_2
DDBIB0_3/QSB_3B/WDQSB_3
DDBIB1_0/QSB_4B/WDQSB_4
DDBIB1_1/QSB_5B/WDQSB_5
DDBIB1_2/QSB_6B/WDQSB_6
DDBIB1_3/QSB_7B/WDQSB_7

DQMB0
DQMB1
DQMB2
DQMB3
DQMB4
DQMB5
DQMB6
DQMB7

2

QSAN_0
QSAN_1
QSAN_2
QSAN_3
QSAN_4
QSAN_5
QSAN_6
QSAN_7

MDB[32..63]

D

1

A34
E30
E26
C20
C16
C12
J11
F8

91

H3
H1
T3
T5
AE4
AF5
AK6
AK5

90,91
90,91
90,91
90,91
90,91
90,91
90,91
90,91
90,91
90,91
90,91
90,91
90,91
90,91
90,91
90,91

Do Not Stuff

RASA0#
RASA1#

88
88
88
88
89
89
89
89

MAB0
MAB1
MAB2
MAB3
MAB4
MAB5
MAB6
MAB7
MAB8
MAB9
MAB10
MAB11
MAB12
B_BA2
B_BA0
B_BA1

1

M12
M27
AH12

CLKA1
CLKA1#

QSAP_0
QSAP_1
QSAP_2
QSAP_3
QSAP_4
QSAP_5
QSAP_6
QSAP_7

WCKB0_0/DQMB_0
WCKB0B_0/DQMB_1
WCKB0_1/DQMB_2
WCKB0B_1/DQMB_3
WCKB1_0/DQMB_4
WCKB1B_0/DQMB_5
WCKB1_1/DQMB_6
WCKB1B_1/DQMB_7
GDDR5/DDR2/GDDR3
EDCB0_0/QSB_0/RDQSB_0
EDCB0_1/QSB_1/RDQSB_1
EDCB0_2/QSB_2/RDQSB_2
EDCB0_3/QSB_3/RDQSB_3
EDCB1_0/QSB_4/RDQSB_4
EDCB1_1/QSB_5/RDQSB_5
EDCB1_2/QSB_6/RDQSB_6
EDCB1_3/QSB_7/RDQSB_7

P8
T9
P9
N7
N8
N9
U9
U8
Y9
W9
AC8
AC9
AA7
AA8
Y8
AA9

2

L27
N12
AG12

MEM_CALRP1
MEM_CALRP0
MEM_CALRP2

CLKA0
CLKA0#

C34
D29
D25
E20
E16
E12
J10
D7

88
88
88
88
89
89
89
89

MAB0_0/MAB_0
MAB0_1/MAB_1
MAB0_2/MAB_2
MAB0_3/MAB_3
MAB0_4/MAB_4
MAB0_5/MAB_5
MAB0_6/MAB_6
MAB0_7/MAB_7
MAB1_0/MAB_8
MAB1_1/MAB_9
MAB1_2/MAB_10
MAB1_3/MAB_11
MAB1_4/MAB_12
MAB1_5/BA2
MAB1_6/BA0
MAB1_7/BA1

2

MEM_CALRN0
MEM_CALRN1
MEM_CALRN2

ADBIA0/ODTA0
ADBIA1/ODTA1

DQMA0
DQMA1
DQMA2
DQMA3
DQMA4
DQMA5
DQMA6
DQMA7

DQB0_0/DQB_0
DQB0_1/DQB_1
DQB0_2/DQB_2
DQB0_3/DQB_3
DQB0_4/DQB_4
DQB0_5/DQB_5
DQB0_6/DQB_6
DQB0_7/DQB_7
DQB0_8/DQB_8
DQB0_9/DQB_9
DQB0_10/DQB_10
DQB0_11/DQB_11
DQB0_12/DQB_12
DQB0_13/DQB_13
DQB0_14/DQB_14
DQB0_15/DQB_15
DQB0_16/DQB_16
DQB0_17/DQB_17
DQB0_18/DQB_18
DQB0_19/DQB_19
DQB0_20/DQB_20
DQB0_21/DQB_21
DQB0_22/DQB_22
DQB0_23/DQB_23
DQB0_24/DQB_24
DQB0_25/DQB_25
DQB0_26/DQB_26
DQB0_27/DQB_27
DQB0_28/DQB_28
DQB0_29/DQB_29
DQB0_30/DQB_30
DQB0_31/DQB_31
DQB1_0/DQB_32
DQB1_1/DQB_33
DQB1_2/DQB_34
DQB1_3/DQB_35
DQB1_4/DQB_36
DQB1_5/DQB_37
DQB1_6/DQB_38
DQB1_7/DQB_39
DQB1_8/DQB_40
DQB1_9/DQB_41
DQB1_10/DQB_42
DQB1_11/DQB_43
DQB1_12/DQB_44
DQB1_13/DQB_45
DQB1_14/DQB_46
DQB1_15/DQB_47
DQB1_16/DQB_48
DQB1_17/DQB_49
DQB1_18/DQB_50
DQB1_19/DQB_51
DQB1_20/DQB_52
DQB1_21/DQB_53
DQB1_22/DQB_54
DQB1_23/DQB_55
DQB1_24/DQB_56
DQB1_25/DQB_57
DQB1_26/DQB_58
DQB1_27/DQB_59
DQB1_28/DQB_60
DQB1_29/DQB_61
DQB1_30/DQB_62
DQB1_31/DQB_63

1

L18
L20

DDBIA0_0/QSA_0B/WDQSA_0
DDBIA0_1/QSA_1B/WDQSA_1
DDBIA0_2/QSA_2B/WDQSA_2
DDBIA0_3/QSA_3B/WDQSA_3
DDBIA1_0/QSA_4B/WDQSA_4
DDBIA1_1/QSA_5B/WDQSA_5
DDBIA1_2/QSA_6B/WDQSA_6
DDBIA1_3/QSA_7B/WDQSA_7

A32
C32
D23
E22
C14
A14
E10
D9

88,89
88,89
88,89
88,89
88,89
88,89
88,89
88,89
88,89
88,89
88,89
88,89
88,89
88,89
88,89
88,89

C5
C3
E3
E1
F1
F3
F5
G4
H5
H6
J4
K6
K5
L4
M6
M1
M3
M5
N4
P6
P5
R4
T6
T1
U4
V6
V1
V3
Y6
Y1
Y3
Y5
AA4
AB6
AB1
AB3
AD6
AD1
AD3
AD5
AF1
AF3
AF6
AG4
AH5
AH6
AJ4
AK3
AF8
AF9
AG8
AG7
AK9
AL7
AM8
AM7
AK1
AL4
AM6
AM1
AN4
AP3
AP1
AP5

SC120P50V2JN-1GP

MVREFDA
MVREFSA

WCKA0_0/DQMA_0
WCKA0_0#/DQMA_1
WCKA0_1/DQMA_2
WCKA0_1#/DQMA_3
WCKA1_0/DQMA_4
WCKA1_0#/DQMA_5
WCKA1_1/DQMA_6
WCKA1_1#/DQMA_7
GDDR5/DDR2/GDDR3
EDCA0_0/QSA_0/RDQSA_0
EDCA0_1/QSA_1/RDQSA_1
EDCA0_2/QSA_2/RDQSA_2
EDCA0_3/QSA_3/RDQSA_3
EDCA1_0/QSA_4/RDQSA_4
EDCA1_1/QSA_5/RDQSA_5
EDCA1_2/QSA_6/RDQSA_6
EDCA1_3/QSA_7/RDQSA_7

MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
MAA12
A_BA2
A_BA0
A_BA1

MDB0
MDB1
MDB2
MDB3
MDB4
MDB5
MDB6
MDB7
MDB8
MDB9
MDB10
MDB11
MDB12
MDB13
MDB14
MDB15
MDB16
MDB17
MDB18
MDB19
MDB20
MDB21
MDB22
MDB23
MDB24
MDB25
MDB26
MDB27
MDB28
MDB29
MDB30
MDB31
MDB32
MDB33
MDB34
MDB35
MDB36
MDB37
MDB38
MDB39
MDB40
MDB41
MDB42
MDB43
MDB44
MDB45
MDB46
MDB47
MDB48
MDB49
MDB50
MDB51
MDB52
MDB53
MDB54
MDB55
MDB56
MDB57
MDB58
MDB59
MDB60
MDB61
MDB62
MDB63

2

C

MAA0_0/MAA_0
MAA0_1/MAA_1
MAA0_2/MAA_2
MAA0_3/MAA_3
MAA0_4/MAA_4
MAA0_5/MAA_5
MAA0_6/MAA_6
MAA0_7/MAA_7
MAA1_0/MAA_8
MAA1_1/MAA_9
MAA1_2/MAA_10
MAA1_3/MAA_11
MAA1_4/MAA_12
MAA1_5/MAA_13_BA2
MAA1_6/MAA_14_BA0
MAA1_7/MAA_A15_BA1

4 OF 8
DDR2
GDDR5/GDDR3
DDR3

VGA1D
DDR2
GDDR3/GDDR5
DDR3

MDB[0..31]

1

1

MDA[32..63]

DQA0_0/DQA_0
DQA0_1/DQA_1
DQA0_2/DQA_2
DQA0_3/DQA_3
DQA0_4/DQA_4
DQA0_5/DQA_5
DQA0_6/DQA_6
DQA0_7/DQA_7
DQA0_8/DQA_8
DQA0_9/DQA_9
DQA0_10/DQA_10
DQA0_11/DQA_11
DQA0_12/DQA_12
DQA0_13/DQA_13
DQA0_14/DQA_14
DQA0_15/DQA_15
DQA0_16/DQA_16
DQA0_17/DQA_17
DQA0_18/DQA_18
DQA0_19/DQA_19
DQA0_20/DQA_20
DQA0_21/DQA_21
DQA0_22/DQA_22
DQA0_23/DQA_23
DQA0_24/DQA_24
DQA0_25/DQA_25
DQA0_26/DQA_26
DQA0_27/DQA_27
DQA0_28/DQA_28
DQA0_29/DQA_29
DQA0_30/DQA_30
DQA0_31/DQA_31
DQA1_0/DQA_32
DQA1_1/DQA_33
DQA1_2/DQA_34
DQA1_3/DQA_35
DQA1_4/DQA_36
DQA1_5/DQA_37
DQA1_6/DQA_38
DQA1_7/DQA_39
DQA1_8/DQA_40
DQA1_9/DQA_41
DQA1_10/DQA_42
DQA1_11/DQA_43
DQA1_12/DQA_44
DQA1_13/DQA_45
DQA1_14/DQA_46
DQA1_15/DQA_47
DQA1_16/DQA_48
DQA1_17/DQA_49
DQA1_18/DQA_50
DQA1_19/DQA_51
DQA1_20/DQA_52
DQA1_21/DQA_53
DQA1_22/DQA_54
DQA1_23/DQA_55
DQA1_24/DQA_56
DQA1_25/DQA_57
DQA1_26/DQA_58
DQA1_27/DQA_59
DQA1_28/DQA_60
DQA1_29/DQA_61
DQA1_30/DQA_62
DQA1_31/DQA_63

90
G24
J23
H24
J24
H26
J26
H21
G21
H19
H20
L13
G16
J16
H16
J17
H17

2

GDDR5

89

C37
C35
A35
E34
G32
D33
F32
E32
D31
F30
C30
A30
F28
C28
A28
E28
D27
F26
C26
A26
F24
C24
A24
E24
C22
A22
F22
D21
A20
F20
D19
E18
C18
A18
F18
D17
A16
F16
D15
E14
F14
D13
F12
A12
D11
F10
A10
C10
G13
H13
J13
H11
G10
G8
K9
K10
G9
A8
C8
E8
A6
C6
E6
A5

GDDR5

D

MDA0
MDA1
MDA2
MDA3
MDA4
MDA5
MDA6
MDA7
MDA8
MDA9
MDA10
MDA11
MDA12
MDA13
MDA14
MDA15
MDA16
MDA17
MDA18
MDA19
MDA20
MDA21
MDA22
MDA23
MDA24
MDA25
MDA26
MDA27
MDA28
MDA29
MDA30
MDA31
MDA32
MDA33
MDA34
MDA35
MDA36
MDA37
MDA38
MDA39
MDA40
MDA41
MDA42
MDA43
MDA44
MDA45
MDA46
MDA47
MDA48
MDA49
MDA50
MDA51
MDA52
MDA53
MDA54
MDA55
MDA56
MDA57
MDA58
MDA59
MDA60
MDA61
MDA62
MDA63

3

3 OF 8
DDR2
GDDR5/GDDR3
DDR3

VGA1C
DDR2
GDDR3/GDDR5
DDR3

MDA[0..31]

MEMORY INTERFACE A

88

4

MEMORY INTERFACE B

5

A

A

Whistler Pop All MEM_CAR
Robson_& Seymour "M2" Only Pop
MEM_CALRN1 & MEM_CALRP1

Whistler Only

Robson_Seymour_Whistler Need Pop
DQ15 AMD DIS SAMSUNG TI

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size

GPU_Memory(2/5)

Document Number

Custom
Date:
5

4

3

2

Rev

X00

QUEEN AMD Muxless/UMA

Thursday, May 26, 2011

Sheet
1

84

of

104

5

4

3

1228: Modify Table

2

1

LVDS Interface

FOR HDMI 1.4

2 OF 8

VGA1B

7 OF 8

VGA1G

Default 1G + Hynix Vram, 0011 72.52G63.A0U
1D8V_VGA_S0

TXCAP_DPA3P
TXCAM_DPA3N

PN

TX0P_DPA2P
TX0M_DPA2N

MUTI GFX

TX1P_DPA1P
TX1M_DPA1N

2

TX4P_DPB1P
TX4M_DPB1N
TX5P_DPB0P
TX5M_DPB0N
TXCCP_DPC3P
TXCCM_DPC3N
TX0P_DPC2P
TX0M_DPC2N
DPC

TX1P_DPC1P
TX1M_DPC1N
TX2P_DPC0P
TX2M_DPC0N
TXCDP_DPD3P
TXCDM_DPD3N

6,18,36 H_THERMTRIP#

TX3P_DPD2P
TX3M_DPD2N
DPD

27 THERMTRIP_VGA_GATE

TX4P_DPD1P
TX4M_DPD1N

I2C

83 GPIO5_AC_BATT

GPIO6_VGA

1
TP8505

Do Not Stuff

83 GPIO8_ROMSO
83
VGA_DIS
83
83
83

CONFIG0
CONFIG1
CONFIG2

VPIO14_VGA

1
92 PWRCNTL_0

TP8506
Do Not Stuff
Do Not Stuff

1

TP8502
Do Not Stuff

1
TP8507

GPIO16_SSIN
GPIO17_VGA
EDP_HPD_DET
THERMTRIP_VGA

92 PWRCNTL_1
83 GPIO21_BB_EN
83 BIOS_ROM_EN

3D3V_VGA_S0

18 PEG_CLKREQ#
83 JTAG_TRST#_VGA

TP8501

2

83 JTAG_TCK_VGA
83 JTAG_TMS_VGA

TP8503
TP8504
TP8508
TP8512
TP8513
TP8509
TP8514
TP8515

R8532

DY1

R8502

2

Do Not Stuff

1

10KR2J-3-GP

XTALOUT

DIS_PX

1 Do Not Stuff

For new version no 27M

1
1
1
1
1
1
1
1

Do Not Stuff
Do Not Stuff
Do Not Stuff
Do Not Stuff
Do Not Stuff
Do Not Stuff
Do Not Stuff
Do Not Stuff

JTAG_TDI_VGA

JTAG_TDO_VGA
GEN_A
GEN_B
GENERICC
GENERICD
GENERICE_HPD4
GENERICF
GENERICG

AH17
AJ17
AK17
AJ13
AH15
AJ16
AK16
AL16
AM16
AM14
AM13
AK14
AG30
AN14
AM17
AL13
AJ14
AK13
AN13
AM23
AN23
AK23
AL24
AM24
AJ19
AK19
AJ20
AK20
AJ24
AH26
AH24

GPIO17_VGA
1D8V_VGA_S0

AK24

51 HDMI_HPD_DET

R
R#

GPIO_0
GPIO_1
GPIO_2
GPIO_3_SMBDATA
GPIO_4_SMBCLK
GPIO_5_AC_BATT
DAC1
GPIO_6
GPIO_7_BLON
GPIO_8_ROMSO
GPIO_9_ROMSI
GPIO_10_ROMSCK
GPIO_11
GPIO_12
GPIO_13
GPIO_14_HPD2
GPIO_15_PWRCNTL_0
GPIO_16_SSIN
GPIO_17_THERMAL_INT
GPIO_18_HPD3
GPIO_19_CTF
GPIO_20_PWRCNTL_1
GPIO_21_BB_EN
GPIO_22_ROMCS#
GPIO_23_CLKREQ#
JTAG_TRST#
JTAG_TDI
JTAG_TCK
JTAG_TMS
JTAG_TDO
GENERICA
GENERICB
GENERICC
GENERICD
GENERICE_HPD4
DAC2
GENERICF
GENERICG

G
G#
B
B#
HSYNC
VSYNC
RSET
AVDD
AVSSQ
VDD1DI
VSS1DI
R2
R2#
G2
G2#
B2
B2#
C
Y
COMP
H2SYNC
V2SYNC

HPD1
VDD2DI
VSS2DI

1

DIS_PX

2

2

AH13

A2VSSQ

AM32
AN32
AN31
XTALIN
XTALOUT

AV33
AU34

1 Do Not Stuff

XO_IN

AW 34
AW 35

0107 Modify:
Removed P2800 Circuit , So does C8523.
Do Not Stuff
TP8519
TP8520
Do Not Stuff

Clock Input Configuraiton -GDDR3/DDR3
a) 27MHz crystal connected to XTALIN or XTALOUT or
b) 27MHz (1.8V) oscillator connected to XTALIN or
c) 27MHz (3.3V) oscillator connected to XO_IN (Park, Madison, and Broadway only)

TP8511

1P2800_VGA_DXP AF29
1P2800_VGA_DXN AG29

1 Do Not Stuff FAN_PWM_C

AK32
AL31

1D8V_VGA_S0
L8504

1

TSVDD

(1.8V@20mA TSVDD)

DIS_PX
2

AT17
AR16

2

XTALIN

1

DIS_PX
SC12P50V2JN-3GP

AU20
AT19

DIS_PX
ROBSON-PRO-M2-GP

AU22
AV21
AT23
AR22

AD39
AD37

VGA_CRT_RED

AE36
AD35

VGA_CRT_GREEN

AF37
AE38

VGA_CRT_BLUE

AC36
AC38
AB34

3

1

AVDD

R8514

83,94
83,94

DPLL_VDDC

AUX1P
AUX1N

XTALIN
XTALOUT

DDC2CLK
DDC2DATA
XO_IN
AUX2P
AUX2N

SS_IN

DDCCLK_AUX3P
DDCDATA_AUX3N
DPLUS
DMINUS

THERMAL

DDCCLK_AUX4P
DDCDATA_AUX4N
DDCCLK_AUX5P
DDCDATA_AUX5N

TS_FDO
DDC6CLK
DDC6DATA

TS_A
TSVDD
TSVSS

DIS_PX

C8501

Do Not Stuff

DDCCLK_AUX7P
DDCDATA_AUX7N

DY

C8503

DY

C

C8504

DY Do Not Stuff
AVSSQ
VDD1DI

1

(1.8V@100mA VDD1DI)

2

R8511 Do Not Stuff

DIS_PX

AVSSQ

C8502

R8506

AC30
AC31

1

DY

2

0112: Dummy Cap

C8506

DY

DY

C8507
Do Not Stuff

Do Not Stuff

AD30
AD31

VDD2DI
AVSSQ

AF30
AF31

1

(1.8V@50mA VDD2DI)
2

R8507 Do Not Stuff

DIS_PX

AC32
AD32
AF32

0112: Remove Cap

AD29
AC29

HSYNC_DAC2
VSYNC_DAC2

VDD2DI

83
83

A2VDDQ

AG31
AG32

1

2

(1.8V@1.5mA A2VDDQ)

R8510 Do Not Stuff
A2VDD

DIS_PX
B

A2VDDQ

AG33
AD33
AF33

A2VDD

AA29

R2SET

DIS_PX
1

R8517

3D3V_VGA_S0

2

715R2F-GP

1

AM26
AN26

2

(3.3V@130mA A2VDD)

R8509 Do Not Stuff

DDC1/DDC2/DDC6 have 5V-tolerant
DDC1CLK
DDC1DATA

AVDD

2

DIS_PX

VDD1DI

AC33
AC34

DIS_PX

VGA_CRT_DDCCLK 94
VGA_CRT_DDCDATA 94

DDC1 channel for CRT

GPU_DDC_CLK_HDMI
51
GPU_DDC_DATA_HDMI
51

FOR HDMI 1.4
DDC2 channel for HDMI

AM27
AL27
AM19
AL19
AN20
AM20

AUXP PD 100K
AUXN PU 100K
Draw on EDP circuit page

AL30
AM30
AL29
AM29
AN21
AM21
AJ30
AJ31

1027 Modify: Use VGA Smbus Instead of use another P2800
3D3V_VGA_S0

AK30
AK29

ROBSON-PRO-M2-GP

DIS_PX

RN8501
SRN4K7J-8-GP

1
2

2

3

SC12P50V2JN-3GP

A

Q8503

2
1

DIS_PX

(1.8V@65mA AVDD)
1

R8512 Do Not Stuff

2

C8525
XTALOUT 1

1D8V_VGA_S0

94

94

499R2F-2-GP

6

SML1_CLK 6,27

DQ15 AMD DIS SAMSUNG TI

5
DIS_PX

Wistron Corporation

4

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

2N7002KDW-GP

84.2N702.A3F
2nd = 84.DM601.03F

82.30034.641
2nd = 82.30034.651
3rd = 82.30034.681

5

94

VGA_CRT_HSYNC
VGA_CRT_VSYNC

DIS_PX

GPU_RSET

AD34
AE34

GPIO_VGA_04_CLK

DIS_PX

XTAL-27MHZ-85-GP

AN36
AP37

TXOUT_L3P
TXOUT_L3N

AT21
AR20

4

2

AP35
AR35

TXOUT_L2P_DPE0P
TXOUT_L2N_DPE0N

1

1

AJ32
AJ33

AR37
AU39

TXOUT_L1P_DPE1P
TXOUT_L1N_DPE1N

1MR2J-1-GP
X8501

C8524

1

DY

C8522
DIS_PXSCD1U10V2KX-5GP

AW 37
AU35

TXOUT_L0P_DPE2P
TXOUT_L0N_DPE2N

AU16
AV15

2

C8520
Do Not Stuff

2

DIS_PXC8521
SC1U6D3V2KX-GP
2

R8524

1

2

68.00084.F81

1

BLM15BD121SS1D-GP

DIS_PX

AP34
AR34

TXCLK_LP_DPE3P
TXCLK_LN_DPE3N

AT15
AR14

3
4

DIS_PXDIS_PX
2

SC1U6D3V2KX-GP

2

TP8516

1

1

1

C8519

C8518

DY

SCD1U10V2KX-5GP

Do Not Stuff

A

R2SET

PLL/CLOCK

BLM18PG471SN1D-GP

C8517

AF35
AG36

LVTMDP

AU14
AV13

DPLL_PVDD
DPLL_PVSS
DDC/AUX

DPLL_VDDC
(1.0V@125mA DPLL_VDDC)
(1.1V@150mA DPLL_VDDC For M96/M92)

2

A2VDDQ
VREFG

DPLL_PVDD

DIS_PX
2

1

R8516
249R2F-GP

DIS_PX

DIS_PX DIS_PX

2

1

C8515

2

2

1V_VGA_S0

1

1

C8516

DY

SCD1U10V2KX-5GP

C8505
Do Not Stuff

C8514

1

2

BLM18PG471SN1D-GP

L8506

GPU_VREFG
SCD1U10V2KX-5GP

1

A2VDD

(1.8V@75mA DPLL_PVDD)

SC1U6D3V2KX-GP

L8501
DIS_PX

D

AG38
AH37

TXOUT_U3P
TXOUT_U3N

AT33
AU32

R8515

DIS_PX499R2F-2-GP

DPLL_PVDD

2

1D8V_VGA_S0

AH35
AJ36

TXOUT_U2P_DPF0P
TXOUT_U2N_DPF0N

AR32
AT31

Do Not Stuff

1

PLACE VREFG DIVIDER AND CAP
CLOSE TO ASIC

B

AV31
AU30

1

AH20
AH18
AN16
GPIO_VGA_03_DATA AH23
GPIO_VGA_04_CLK AJ23

AJ38
AK37

TXOUT_U1P_DPF1P
TXOUT_U1N_DPF1N

SCL
SDA
GENERAL PURPOSE I/O

83 TX_PWRS_ENB
83 TX_DEEMPH_EN
83 BIF_GEN2_EN_A

C

TX5P_DPD0P
TX5M_DPD0N

AR30
AT29

AK35
AL36

1

AK26
AJ26

I2C Bus for LVDS

TXOUT_U0P_DPF2P
TXOUT_U0N_DPF2N

2

0708: Need To Pick GPIO
0708: Add Thermal Shutdown Circuit
0107: SW Will Not Use This Function, DY For Reserve Only

TXCLK_UP_DPF3P
TXCLK_UN_DPF3N

HDMI_DATA2 51
HDMI_DATA2# 51

2

3

2

1

DY

TX3P_DPB2P
TX3M_DPB2N

DPB

HDMI_DATA1 51
HDMI_DATA1# 51

AT27
AR26

1

2

DY

4

5

6
Q8501
Do Not Stuff

TXCBP_DPB3P
TXCBM_DPB3N

AU26
AV25

1

0914: Change R8518 Part Reference To HYNIX
For Hynix + Vram 1G,
Pop R8518, Pop R8519
For Hynix + Vram 512M, Pop R8518, De-pop R8519
For Samsung+Vram1G, De-pop R8518, Pop R8519
For Samsung+Vram512M, De-pop R8518, De-POP R8519

Do Not Stuff

TX2P_DPA0P
TX2M_DPA0N

2

R8508

DVPCNTL_MVP_0
DVPCNTL_MVP_1
DVPCNTL_0
DVPCNTL_1
DVPCNTL_2
DVPCLK
DVPDATA_0
DVPDATA_1
DVPDATA_2
DVPDATA_3
DVPDATA_4
DVPDATA_5
DVPDATA_6
DVPDATA_7
DVPDATA_8
DVPDATA_9
DVPDATA_10
DVPDATA_11
DVPDATA_12
DVPDATA_13
DVPDATA_14
DVPDATA_15
DVPDATA_16
DVPDATA_17
DVPDATA_18
DVPDATA_19
DVPDATA_20
DVPDATA_21
DVPDATA_22
DVPDATA_23

AK27
AJ27

VARY_BL
DIGON

2

1

1

THERMTRIP_VGA

AR8
AU8
AP8
AW 8
AR3
AR1
MEM_ID0 AU1
MEM_ID1 AU3
MEM_ID2 AW 3
MEM_ID3
AP6
AW 5
AU5
AR6
AW 6
AU6
AT7
AV7
AN7
AV9
AT9
AR10
AW 10
AU10
AP10
AV11
AT11
AR12
AW 12
AU12
AP12

HDMI_DATA0 51
HDMI_DATA0# 51

1

R8518

HDMI_CLK 51
HDMI_CLK# 51

AT25
AR24

2

R8519

HYNIX
SAMSUNG_Gdie

LVDS CONTROL

AU24
AV23

Do Not Stuff

2

2
R8522

DY

1

72.41646.Q0U

2

DDR3 SAMSUNG-K4W1G1646G-BC11 (900MHz) 64M*16

R8523

DY

1

0000

THERMTRIP_R

72.42164.D0U

Do Not Stuff

72.51G63.H0U

DDR3 SAMSUNG-K4W2G1646C-HC11(900MHz) 128M*16

10KR2J-3-GP

DDR3 Hynix-H5TQ1G63DFR-11C (900MHz) 64M*16

Do Not Stuff

0011
0010

Do Not Stuff
2nd = 84.DM601.03F

DPA

72.52G63.A0U

1

DDR3 Hynix-H5TQ2G63BFR-11C (900MHz) 128M*16

Do Not Stuff

D

0001

1

Description

2

DVPDATA[3:0]

Do Not Stuff

MEMORY ID Table

Title
SML1_DATA 6,27

GPIO_VGA_03_DATA

4

3

2

GPU_DP/LVDS/CRT/GPIO(3/5)
Size
A2

Document Number

Date:

Thursday, May 26, 2011

Rev

QUEEN AMD Muxless/UMA
Sheet
1

85

of

X00
104

5

4

3

10/8

VGA1E

2

1

5 OF 8
1D8V_VGA_S0

SPV10

PCIE_PVDD
MPV18
MPV18

1

1
2

1

1

2

2

2

2

1

1
2

1

1
2

2

2

2

1

1

1
2

1

1
2

2

1

1
2

DIS_PX

1

1

C8671

C8644
SC1U6D3V2KX-GP

C8672

2

DIS_PX

DY

2

C8670

2

1

1
2

2
1

1

1
SC1U6D3V2KX-GP
2

2

2

2
1
2

DY

DIS_PX

2

1

1

1
2
1
2

1

1
2

2
1

1
2

C8669

C8643

DIS_PX

DIS_PX

Only For PX 3.0 Validation If Need
VGA_CORE
R8608 1
Do Not Stuff

2

DY

1

C

C8695

C8699

DIS_PX DIS_PX

VDDCI and VDDC should have seperate regulators with a merge option on PCB
Vgs(th):0.7~1.5
For Madison and Park, VDDCI and VDDC can share one common regulator low Rds(on)
BIF_VDDC

U8603
AO3400A-GP

G
1
R8610
Do Not Stuff
2

1

1

DIS_PX

DIS_PX

C8663

DG COST DOWN?

2

DIS_PX

C8662

2

1

1

DIS_PX

2

2

1
2

1

1
2

DIS_PX

C8661

DIS_PX

1027 Modify: Change Baco Mos Gate Power Rail
To 5V_S0 & Also Reserve 3D3V_VGA_S0
U8602
AO3418-GP

S
3D3V_VGA_S0
3D3V_S5

1D5V_VGA_PWOK_R

1

1D5V_VGA_S0

DIS_PX

Do Not Stuff

DIS_PX

Do Not Stuff

1

DIS_PX

PX_EN

2

8209A_EN/DEM_VGA1D5V_VGA_PWOK_R

PX_EN# PX_EN##

Do Not Stuff
Non-BACO

2ND = 84.2N702.031

Do Not Stuff
2ND = 84.03904.P11

C8694

1

1

2

Non-BACO= HIGH
BACO = LOW

S
C

Q8604
Do Not Stuff
Q8604_B DY B

84.03418.031

BACO

0

1

1

0

1

1

0

0

1

0

3rd = 84.03904.L06

2

SC1U6D3V2KX-GP
2
1

1
2
SC4D7U6D3V3KX-GP

68.00084.F81
2ND = 68.00217.701

DIS_PX

C8692

SCD1U10V2KX-5GP

2

2

DY

E

R8601 2

84.03418.031

R8606
1KR2J-1-GP

1D5V_VGA_PWOK

DY

1

Do Not Stuff

DIS_PX

PX_EN#

1V_VGA_S0

S

G
D

R8603

MPV18

L8605

DIS_PX

DY

DY
Q8603

DGPU_PWROK

(Park: 1.8V@75mA MPV18)

C8691

R8609
Do Not Stuff
2

DY
Q8603_G

1122 Modify: Change Net from 1D5V_VGA_PWOK_R to DGPU_PWROK

(M97, Broadway and Madison: 1.8V@150mA MPV18)

BLM15BD121SS1D-GP

Do 1
Not Stuff
R8605

Do 2
Not Stuff
R8604

1

DIS_PX

BIF_VDDC_1V
D

5V_S0

3D3V_VGA_S0

1

DIS_PX

U8604
AO3418-GP
D

G

DIS_PX

C8690

2

1
SC1U6D3V2KX-GP
2

1
2

SC4D7U6D3V3KX-GP

68.00084.F81
2ND = 68.00217.701

DIS_PX

C8689

SCD1U10V2KX-5GP

2

BLM15BD121SS1D-GP
C8688
DIS_PX

B

DIS_PX

DIS_PX

1122 Modify: Dummy 1D5V PowerOK Cost Down

(1.8V@75mA SPV18)

1

DIS_PX
84.03400.B37
2nd = 84.03404.C31

R8607
1KR2J-1-GP

DY

VGA_CORE

C8660

SCD1U10V2KX-5GP

DIS_PX

C8659

SC1U6D3V2KX-GP

DIS_PX

C8658

SC1U6D3V2KX-GP

DIS_PX

C8657

SC1U6D3V2KX-GP

DIS_PX

C8656

DIS_PX
84.03400.B37
2nd = 84.03404.C31

1

C8687
SC10U6D3V5KX-1GP

DIS_PX

VGA_CORE

S

5V_S0

BIF_VDDC

ROBSON-PRO-M2-GP
SPV18

1

DIS_PX

U8605
AO3400A-GP
BIF_VDDC_CORE
D

D

2

1

DIS_PX

2

2

2

C8686

2

1

1

1
2

1

1
2

2

C8685

DIS_PX

SC1U6D3V2KX-GP

ISOLATED
CORE I/O

FB_GND

C8684

DIS_PX

PX_EN##
C8655

SC1U6D3V2KX-GP

FB_VDDCI

C8683

DIS_PX

SCD1U10V2KX-5GP

AH29

FB_GND

FB_VDDC

C8682

DIS_PX

SC1U6D3V2KX-GP

AG28

SC1U6D3V2KX-GP

1FB_VDDCI
Do Not Stuff

C8681

2

2

SPVSS

VOLTAGE
SENESE
AF28

TP8602

SPV10

SC1U6D3V2KX-GP

AN10

DIS_PX

SC1U6D3V2KX-GP

1

AN9
C8680

SC1U6D3V2KX-GP

DIS_PX

SC1U6D3V2KX-GP

C8679

FB_VDDC

92

PX_EN# = High, BIF_VDDC = 1V_VGA_S0
PX_EN## = High, BIF_VDDC = VGA_CORE

PX_EN

Mode

BIF_VDDC

0

Normal

VGA_Core

1

BACO

1V_VGA

3D3V_VGA_S0

1D5V_VGA_PWOK
17,92,93

DGPU_PWROK

R8602 1
Do Not Stuff

DY

A

2
U8607
1
2

92,93 8209A_EN/DEM_VGA

3
Q8601
87

B
VCC
A

DY

Y

5
4

Non-BACO= HIGH
BACO = LOW

GND

Do Not Stuff
2ND = 73.7SZ08.DAH

D

Q8602

1D5V_VGA_PWOK_R
PX_EN##

Do Not Stuff

G

PX_EN

DIS_PX

4

3

5

DIS_PX2

6

1

Non-BACO= HIGH
2N7002KDW-GP
BACO = LOW
84.2N702.A3F

PX_EN#

2nd = 84.DM601.03F

S

DQ15 AMD DIS SAMSUNG TI

84.2N702.J31

Wistron Corporation

Non-BACO= LOW
BACO = HIGH

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

2N7002K-2-GP

Document Number
Size
Custom

Rev

QUEEN AMD Muxless/UMA

Date:
4

GPU_POWER(4/5)

1122 Modify: Dummy U8607, R8602 And GATE Cost Down

2ND = 84.2N702.031
5

0603

V

S
3D3V_VGA_S0

AA13
AB13
AC12
AC15
AD13
AD16
M15
M16
M18
M23
N13
N15
N17
N20
N22
R12
R13
R16
T12
T15
V15
Y13

SC1U6D3V2KX-GP

DIS_PX

VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI

SCD1U10V2KX-5GP

C8678

SPV18

B

A

DIS_PX

DY

BIF_VDDC

1

(120mA SPV10)
SCD1U10V2KX-5GP

1 DIS_PX 2
BLM15BD121SS1D-GP

68.00084.F81
2ND = 68.00217.701

92

1

C8649

DIS_PX

55mA in BACO mode

1

AM10

L8603

(For M97, Broadway, Madison and Park SPV10 = 1.0V)

L8604

C8648

DIS_PX

DIS_PX

C8642

VGA_CORE
1V_VGA_S0

SC1U6D3V2KX-GP
2
1

DIS_PX

H7
H8

SPV18

2

1

C8677

SC4D7U6D3V3KX-GP
2
1

DIS_PX

PLL
AB37

MPV18

1

C8676

2

DIS_PX

SC1U6D3V2KX-GP
2
1

C8675

DIS_PX
68.00084.F81
2ND = 68.00217.701

SCD1U10V2KX-5GP

SC4D7U6D3V3KX-GP
2
1

(1.8V@40mA PCIE_PVDD)

1
2
BLM15BD121SS1D-GP

C8647

DIS_PX

DIS_PX

C8641

G

NC_VDDRHB
NC_VSSRHB

PCIE_PVDD

L8602

DIS_PX

C8640

G

NC_VDDRHA
NC_VSSRHA

C8646

2

1
2

V12
U12

C8639

SC10U6D3V3MX-GP

2

SC1U6D3V2KX-GP
2
1

SC1U6D3V2KX-GP
2
1

1

SC1U6D3V2KX-GP
2
1
SC1U6D3V2KX-GP
2
1

1

2

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP
2
1

SC4D7U6D3V3KX-GP
2
1
SC4D7U6D3V3KX-GP
2
1
1
2

M20
M21

1VDDRHB
1VSSRHB

C8645

DY

C8638

DIS_PX

2

1
SC10U6D3V5KX-1GP
2

1VDDRHA
1VSSRHA

DIS_PX

SC4D7U6D3V3KX-GP
2
1

SC1U6D3V2KX-GP
2
1

2

2

SC1U6D3V2KX-GP
2
1

SC1U6D3V2KX-GP
2
1

SC1U6D3V2KX-GP
2
1

SC1U6D3V2KX-GP
2
1

SC1U6D3V2KX-GP
2
1

SC1U6D3V2KX-GP
1
2
1

1
2

1
2

1
2

1

1
2

1
2

1
2

2

SC1U6D3V2KX-GP
2
1

SC1U6D3V2KX-GP
2
1

SC1U6D3V2KX-GP
2
1
1
2
1
SC10U6D3V5KX-1GP
2

Do Not Stuff TP8606
Do Not Stuff TP8607

D

SC10U6D3V5KX-1GP

Do Not Stuff TP8604
Do Not Stuff TP8605

C8637

SC10U6D3V5KX-1GP

DIS_PX

C8634

DIS_PX
DIS_PX

Do Not Stuff

M96 Only

SC4D7U6D3V3KX-GP

C8674

VDDR4
VDDR4
VDDR4
VDDR4

C8664

SC10U6D3V5KX-1GP

AD12
AF11
AF12
AG11

VDDR4
VDDR4
VDDR4
VDDR4

DIS_PX

SC1U6D3V2KX-GP

AF13
AF15
AG13
AG15

DIS_PX

C8602

SC1U6D3V2KX-GP

DIS_PX

DIS_PX

Do Not Stuff

VDDR3
VDDR3
VDDR3
VDDR3

DIS_PX

C8633

Do Not Stuff

DIS_PX

DIS_PX

I/O
AF23
AF24
AG23
AG24

C8668

C8632

SC1U6D3V2KX-GP

C8673

C8667

DIS_PX

DIS_PX

SC1U6D3V2KX-GP

C

C8666

DIS_PX

VDD_CT
VDD_CT
VDD_CT
VDD_CT

1V_VGA_S0

C8631

SC1U6D3V2KX-GP

C8665

DIS_PX

AF26
AF27
AG26
AG27

C8654

DIS_PX

SC1U6D3V2KX-GP

3D3V_VGA_S0

DIS_PX

C8653

DIS_PX

C8630

SC1U6D3V2KX-GP

SCD1U10V2KX-5GP

DIS_PX

68.00084.F81
2ND = 68.00217.701

C8652

POWER

SC1U6D3V2KX-GP

DIS_PX

C8651

SCD1U10V2KX-5GP

DIS_PX

C8650

C8629

SCD1U10V2KX-5GP

LEVEL
TRANSLATION

(1.8V@110mA VDD_CT)
2

BLM15BD121SS1D-GP

C8618
SC4D7U6D3V3KX-GP

DIS_PX DIS_PX

VGA_CORE

AA15
AA17
AA20
AA22
AA24
AA27
AB16
AB18
AB21
AB23
AB26
AB28
AC17
AC20
AC22
AC24
AC27
AD18
AD21
AD23
AD26
AF17
AF20
AF22
AG16
AG18
AG21
AH22
AH27
AH28
M26
N24
N27
R18
R21
R23
R26
T17
T20
T22
T24
T27
U16
U18
U21
U23
U26
V17
V20
V22
V24
V27
Y16
Y18
Y21
Y23
Y26
Y28

Do Not Stuff

VDDC_CT

L8601
1

C8628

SC1U6D3V2KX-GP

1D8V_VGA_S0

C8616

(1.0V@1920mA PCIE_VDDC)

G30
G31
H29
H30
J29
J30
L28
M28
N28
R28
T28
U28

SC1U6D3V2KX-GP

VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC

CORE

DIS_PX

SC1U6D3V2KX-GP

C8697

DIS_PX

C8617

DIS_PX

SC1U6D3V2KX-GP

DG COST DOWN
C8603

DIS_PX

C8615

DIS_PX

SC1U6D3V2KX-GP

DIS_PX

C8619

SC1U6D3V2KX-GP

DIS_PX

PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC

(1.8V@504mA PCIE_VDDR)

SC1U6D3V2KX-GP

DIS_PX

C8627

AA31
AA32
AA33
AA34
V28
W29
W30
Y31

SC1U6D3V2KX-GP

DIS_PX

C8635

PCIE_VDDR
PCIE_VDDR
PCIE_VDDR
PCIE_VDDR
PCIE_VDDR
PCIE_VDDR
PCIE_VDDR
PCIE_VDDR

SC1U6D3V2KX-GP

C8625

DIS_PX

SC1U6D3V2KX-GP

DIS_PX

C8636

DIS_PX

VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1

SC1U6D3V2KX-GP

DIS_PX

C8624

DIS_PX

AC7
AD11
AF7
AG10
AJ7
AK8
AL9
G11
G14
G17
G20
G23
G26
G29
H10
J7
J9
K11
K13
K8
L12
L16
L21
L23
L26
L7
M11
N11
P7
R11
U11
U7
Y11
Y7

C8614

SC1U6D3V2KX-GP

DIS_PX

C8623

DIS_PX

C8613

SC1U6D3V2KX-GP

C8622

PCIE

DIS_PX

C8612

SC1U6D3V2KX-GP

DIS_PX

DIS_PX

C8611

SC1U6D3V2KX-GP

C8696

DIS_PX

C8608

SC1U6D3V2KX-GP

DIS_PX

DIS_PX

C8607

SCD1U10V2KX-5GP

C8698

C8606

SCD1U10V2KX-5GP

DIS_PX

DIS_PX

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SCD1U10V2KX-5GP

C8621

C8605

SCD1U10V2KX-5GP

C8604

DIS_PX

D

MEM I/O

For DDR3/GDDR5, MVDDQ = 1.5V
C8601

2

1D5V_VGA_S0

3

2

Friday, May 27, 2011

Sheet
1

86

of

X00
104

5

4

3

2

1

DNI for M96/M92
1D8V_VGA_S0

DPC_VDD18
1V_VGA_S0

AP20
AP21

B

1

C8710

DPC_VDD10
DPC_VDD10

DPA_VDD10
DPA_VDD10

DPC_VSSR
DPC_VSSR
DPC_VSSR
DPC_VSSR
DPC_VSSR

DPA_VSSR
DPA_VSSR
DPA_VSSR
DPA_VSSR
DPA_VSSR

AN24
AP24
1V_VGA_S0
DPA_VDD10

AN17
AP16
AP17
AW 14
AW 16

C8711

HDMI1.4 HDMI1.4
Do Not Stuff

AN27
AP27
AP28
AW 24
AW 26

DPC_VDD18

L8703

(1.0V@110mA DPA_VDD10)

1

1

C8702

C8703
HDMI1.4 HDMI1.4

DIS_PX
2

BLM15BD121SS1D-GP

C8705
HDMI1.4
Do Not Stuff

2

AP31
AP32

1

AP13
AT13

Remove EDP

2

(1.0V@110mA DPC_VDD10)

D

0112: Change Dummy Name
DPB_VDD18

DPC_VDD18

AP22
AP23

(1.8V@130mA DPB_VDD18)

2

DPA_VDD18
DPA_VDD18

1

2

DIS_PX

1V_VGA_S0
R8710

1

DP A/B POWER

2

2

1

0112: Change Dummy Name

2

1

HDMI1.4
2

C8709

2

2
Do Not Stuff

DIS_PX
Do Not Stuff

1

(1.8V@130mA DPB_VDD18)
Do Not Stuff

1

DPD_VDD18
DPD_VDD18

DPB_VDD18
DPB_VDD18

DPD_VDD10
DPD_VDD10

DPB_VDD10
DPB_VDD10

DPD_VSSR
DPD_VSSR
DPD_VSSR
DPD_VSSR
DPD_VSSR

DPB_VSSR
DPB_VSSR
DPB_VSSR
DPB_VSSR
DPB_VSSR

AP25
AP26
1V_VGA_S0

Do Not Stuff

(1.0V@110mA DPD_VDD10)

AP14
AP15

DIS_PX

(1.0V@110mA DPB_VDD10)

AN33
AP33

0112: Remove Cap
AN19
AP18
AP19
AW 20
AW 22

1D8V_VGA_S0
DPA_PVDD

DP PLL POWER

DPA_PVDD
DPA_PVSS

DPE_VDD10
DPE_VDD10

DPB_PVDD
DPB_PVSS

DPE_VSSR
DPE_VSSR
DPE_VSSR
DPE_VSSR

DPC_PVDD
DPC_PVSS

AU28
AV27

DP mode

AL33
AM33

DPC_VDD10

(1.0V@110mA DPE_VDD10)

0112: Change Bead To 0603 0 Ohm & Remove Cap

DPD_PVDD
DPD_PVSS

DP mode

(1.8V@130mA DPF_VDD18)

LVDS mode

AF34
AG34

DPC_VDD18

DPF_VDD18
DPF_VDD18
DPE_PVDD
DPE_PVSS

AK33
AK34

0507 chaomin

DPF_VDD10
DPF_VDD10
DPF_PVDD
DPF_PVSS

R8708
PX_EN_R

1

2
Do Not Stuff

DIS_PX

PX_EN

86

AF39
AH39
AK39
AL34
AM34

LVDS mode

(1.0V@120mA DPF_VDD10)

DPC_VDD10

DP mode

DIS_PX

L8704

HDMI1.4

1

DIS_PX
2

BLM15BD121SS1D-GP
C8714

HDMI1.4
Do Not Stuff

(1.8V@20mA DPB_PVDD)

AV29
AR28

DPC_PVDD

(1.8V@20mA DPC_PVDD)
AN34
AP39
AR39
AU37

(1.8V@200mA DPF_VDD18)

HDMI1.4

C8713

1

DIS_PX
DP E/F POWER

DPE_VDD18
DPE_VDD18

C8712

1

1

2

150R2F-1-GP

2

AW 28DPAB_CALR1

2

AH34
AJ34

DPAB_CALR

Do Not Stuff

(1.8V@200mA DPE_VDD18)

DPCD_CALR

LVDS mode

(1.0V@120mA DPE_VDD10)

(1.8V@20mA DPA_PVDD)

x01 change tolerant 20091117

R8703

DIS_PX

2DPCD_CALR AW 18
150R2F-1-GP
DPC_VDD18
1

2

LVDS mode

0112: Combine Power

R8701

AN29
AP29
AP30
AW 30
AW 32

Do Not Stuff

DP mode

(1.8V@130mA DPE_VDD18)

1

(1.0V@110mA DPF_VDD10)

DPE/DPF_VDD10 Share Same GRP, Base on Checklist
2DPEF_CALR

AM39

AU18
AV17

DPC_PVDD

1 R8715

2

Do Not Stuff

DIS_PX

C

AV19
AR18

AM37
AN38

AL38
AM35

(1.8V@20mA DPE_PVDD)

(1.8V@20mA DPF_PVDD)

DPF_VSSR
DPF_VSSR
DPF_VSSR
DPF_VSSR
DPF_VSSR

0112: Remove Cap, Bead and 0 Ohm

DPEF_CALR
ROBSON-PRO-M2-GP

DIS_PX
R8705

DP[F:E]_VDD10
(LVDS/DP/TMDS Transmitter Power (Links E, F))
For dual-link TMDS or LVDS, the associated power supply
rails can share the filters/decoupling capacitors.

DIS_PX 150R2F-1-GP
1

Pin AL21 is PX_EN

R8702

R8711

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

A3
A37
AA16
AA18
AA2
AA21
AA23
AA26
AA28
AA6
AB12
AB15
AB17
AB20
AB22
AB24
AB27
AC11
AC13
AC16
AC18
AC2
AC21
AC23
AC26
AC28
AC6
AD15
AD17
AD20
AD22
AD24
AD27
AD9
AE2
AE6
AF10
AF16
AF18
AF21
AG17
AG2
AG20
AG22
AG6
AG9
AH21
AJ10
AJ11
AJ2
AJ28
AJ6
AK11
AK31
AK7
AL11
AL14
AL17
AL2
AL20
AL21
AL23
AL26
AL32
AL6
AL8
AM11
AM31
AM9
AN11
AN2
AN30
AN6
AN8
AP11
AP7
AP9
AR5
B11
B13
B15
B17
B19
B21
B23
B25
B27
B29
B31
B33
B7
B9
C1
C39
E35
E5
F11
F13

10KR2J-3-GP

C

F15
F17
F19
F21
F23
F25
F27
F29
F31
F33
F7
F9
G2
G6
H9
J2
J27
J6
J8
K14
K7
L11
L17
L2
L22
L24
L6
M17
M22
M24
N16
N18
N2
N21
N23
N26
N6
R15
R17
R2
R20
R22
R24
R27
R6
T11
T13
T16
T18
T21
T23
T26
U15
U17
U2
U20
U22
U24
U27
U6
V11
V16
V18
V21
V23
V26
W2
W6
Y15
Y17
Y20
Y22
Y24
Y27
U13
V13

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

2

D

PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS

DP C/D POWER

DPC_VDD18
DPC_VDD18

DPC_VDD10

DPB_VDD18

R8714 Do Not Stuff

AB39
E39
F34
F39
G33
G34
H31
H34
H39
J31
J34
K31
K34
K39
L31
L34
M34
M39
N31
N34
P31
P34
P39
R34
T31
T34
T39
U31
U34
V34
V39
W 31
W 34
Y34
Y39

8 OF 8

VGA1H

Do Not Stuff

C8708

Do Not Stuff

C8707

HDMI1.4 HDMI1.4
Do Not Stuff
2

2

Do Not Stuff
6 OF 8

VGA1F

HDMI1.4

DPA_VDD18

DPA_VDD18)

1
C8706

1

2

DIS_PX

1

L8702
BLM15BD121SS1D-GP
(1.8V@130mA

DG15 just tied to DPB_VDD18 instead

Do Not Stuff

1

DPA_VDD18

B

For M97/M96, DPF_VDD18 can be shared with DPE_VDD18
For M97/M96, DPF_VDD10 can be shared with DPE_VDD10

For dual link DVI using DPA AND DPB, DPA_VDDxx and DPB_VDDxx can be shared respectively
For dual link DVI using DPC AND DPD, DPC_VDDxx and DPD_VDDxx can be shared respectively
For dual link LVDS, DPE_VDDxx and DPF_VDDxx can be shared respectively

VSS_MECH
VSS_MECH
VSS_MECH

A39 VSS_MECH1
AW 1 VSS_MECH2
AW 39VSS_MECH3

Do Not Stuff 1
Do Not Stuff 1
Do Not Stuff 1

TP8701
TP8702
TP8703

ROBSON-PRO-M2-GP

DIS_PX

A

A

DQ15 AMD DIS SAMSUNG TI

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

GPU_DPPWR/GND(5/5)
Size

A2
Date:
5

4

3

2

Document Number

Rev

QUEEN AMD Muxless/UMA
Thursday, May 26, 2011

Sheet
1

87

of

X00
104

5

4

3

2

1D5V_VGA_S0

1

1D5V_VGA_S0
VRAM11

VRAM21

VRAM1_VREF
VRAM2_VREF
1
R8801
84,89
84,89
84,89
84,89
84,89
84,89
84,89
84,89
84,89
84,89
84,89
84,89
84,89
84,89

C

84,89
84,89
84,89

Whistler

VRAM_ZQ1
Do Not Stuff

MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
MAA12
MAA13

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
M7

A_BA0
A_BA1
A_BA2

M2
N8
M3
J7
K7

R8803
Do Not Stuff

B

1

GPU_CLKA0_T

C8802

K9

CKEA0

D3
E7

DQMA2
DQMA0

Whistler

84
84
84

L3
K3
J3

WEA0#
CASA0#
RASA0#

DQSL
DQSL#
ODT

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC#
A13
NC#M7

CS#
RESET#
NC#T7
NC#L9
NC#L1
NC#J9
NC#J1
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

BA0
BA1
BA2
CK
CK#
CKE

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

DMU
DML
WE#
CAS#
RAS#

QSAP_0 84
QSAN_0 84

K1

ODTA0

C8818
Do Not Stuff
2
1
Whistler
C8821

C8816
Do Not Stuff
2
1
Whistler

C8819
Do Not Stuff
2
1
Whistler

QSAP_2 84
QSAN_2 84

2
1
Whistler

C8817
Do Not Stuff
2
1
Whistler

C8820

C7
B7
F3
G3

L2
T2

C8814
Do Not Stuff
2
1
Whistler

MDA20
MDA19
MDA23
MDA18
MDA22
MDA16
MDA21
MDA17

84
C8815
Do Not Stuff
2
1
Whistler

D7
C3
C8
C2
A7
A2
B8
A3

MDA[0..31]

C8822
Do Not Stuff
2
1
Whistler

MDA3
MDA7
MDA1
MDA6
MDA2
MDA4
MDA0
MDA5

K8
K2
N1
R9
B2
D9
G7
R1
N9

2
1
Whistler

DQSU
DQSU#

VREFDQ
VREFCA
ZQ

E3
F7
F2
F8
H3
H8
G2
H7

A8
A1
C1
C9
D2
E9
F1
H9
H2

VRAM2_VREF
VRAM1_VREF
2VRAM_ZQ2
R8802 Whistler Do Not Stuff
1

84

CSA0#_0 84
MEM_RST 84,89,90,91

T7
L9
L1
J9
J1
J8
M1
M9
J2
P9
G8
B3
T1
A9
T9
E1
P1

84,89
84,89
84,89
84,89
84,89
84,89
84,89
84,89
84,89
84,89
84,89
84,89
84,89
84,89

84,89
84,89
84,89
84
84

G1
F9
E8
E2
D8
D1
B9
B1
G9

H1
M8
L8

MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
MAA12
MAA13

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
M7

A_BA0
A_BA1
A_BA2

M2
N8
M3
J7
K7

CLKA0
CLKA0#
84

CKEA0

K9

84
84

DQMA1
DQMA3

D3
E7

84
84
84

L3
K3
J3

WEA0#
CASA0#
RASA0#

Do Not Stuff

2

Do Not Stuff

84

Whistler
84

2

Whistler

84

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

2

R8804
Do Not Stuff

1

CLKA0
CLKA0#
1

84
84

2

H1
M8
L8

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

C8823
Do Not Stuff
2
1
Whistler

C8812
Do Not Stuff
2
1
Whistler
2
1
Whistler

C8810
Do Not Stuff
2
1
Whistler

C8813
Do Not Stuff
2
1
Whistler
C8804

A8
A1
C1
C9
D2
E9
F1
H9
H2

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

Do Not Stuff

C8801

K8
K2
N1
R9
B2
D9
G7
R1
N9

Do Not Stuff

Do Not Stuff

Do Not Stuff

2
1
Whistler

C8811
Do Not Stuff
2
1
Whistler

C8808
Do Not Stuff
2
1
Whistler

C8809
Do Not Stuff
2
1
Whistler

C8806
Do Not Stuff
2
1
Whistler

C8807
Do Not Stuff
2
1
Whistler

D

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

DQSU
DQSU#

VREFDQ
VREFCA
ZQ

DQSL
DQSL#
ODT

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC#
A13
NC#M7
BA0
BA1
BA2
CK
CK#

CS#
RESET#
NC#T7
NC#L9
NC#L1
NC#J9
NC#J1
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

CKE
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

DMU
DML
WE#
CAS#
RAS#

E3
F7
F2
F8
H3
H8
G2
H7

MDA29
MDA24
MDA30
MDA26
MDA28
MDA27
MDA25
MDA31

D7
C3
C8
C2
A7
A2
B8
A3

MDA8
MDA14
MDA9
MDA10
MDA15
MDA12
MDA13
MDA11

MDA[0..31]

84

D

C

C7
B7

QSAP_1 84
QSAN_1 84

F3
G3

QSAP_3 84
QSAN_3 84

K1

ODTA0

L2
T2

CSA0#_0 84
MEM_RST 84,89,90,91

84

T7
L9
L1
J9
J1
J8
M1
M9
J2
P9
G8
B3
T1
A9
T9
E1
P1
G1
F9
E8
E2
D8
D1
B9
B1
G9

B

Do Not Stuff

Whistler

Whistler
1D5V_VGA_S0

1

1

1D5V_VGA_S0

R8808
Do Not Stuff

R8805
Do Not Stuff

Whistler

2

2

Whistler

VRAM2_VREF

Whistler

C8803
Do Not Stuff

Whistler

C8805
Do Not Stuff

2

Whistler

A

DQ15 AMD DIS SAMSUNG TI

2

A

1
R8807
Do Not Stuff

Whistler

2

R8806
Do Not Stuff

2

1

1

1

VRAM1_VREF

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size

A3
Date:
5

4

3

2

GPU-VRAM1,2 (1/4)

Document Number

Rev

QUEEN AMD Muxless/UMA
Thursday, May 26, 2011

Sheet
1

88

of

X00
104

5

4

3

2

1D5V_VGA_S0

1

1D5V_VGA_S0

H1
M8
2VRAM_ZQ3
L8
R8903 Whistler Do Not Stuff
1

C

MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
MAA12
MAA13

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
M7

84,88
84,88
84,88

A_BA0
A_BA1
A_BA2

M2
N8
M3
J7
K7

84
Whistler84

C8903

1

GPU_CLKA1_T

Do Not Stuff

DQMA5
DQMA4

D3
E7

Whistler

84
84
84

WEA1#
CASA1#
RASA1#

L3
K3
J3

DQSU
DQSU#
DQSL
DQSL#
ODT

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC#
A13
NC#M7
BA0
BA1
BA2
CK
CK#

CS#
RESET#
NC#T7
NC#L9
NC#L1
NC#J9
NC#J1
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

CKE
DMU
DML
WE#
CAS#
RAS#

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

C7
B7

QSAP_5 84
QSAN_5 84

F3
G3

QSAP_4 84
QSAN_4 84

K1

ODTA1

L2
T2

C8914
Do Not Stuff
2
1
Whistler

C8915
Do Not Stuff
2
1
Whistler

C8918
Do Not Stuff
2
1
Whistler

C8922
Do Not Stuff
2
1
Whistler

VRAM4_VREF
VRAM3_VREF

K8
K2
N1
R9
B2
D9
G7
R1
N9
A8
A1
C1
C9
D2
E9
F1
H9
H2

H1
M8
2VRAM_ZQ4
L8
R8904 Whistler Do Not Stuff
1

84

CSA1#_0 84
MEM_RST 84,88,90,91

T7
L9
L1
J9
J1
J8
M1
M9
J2
P9
G8
B3
T1
A9
T9
E1
P1

C8923
Do Not Stuff
2
1
Whistler

MDA46
MDA43
MDA45
MDA40
MDA44
MDA41
MDA47
MDA42

84
C8920
Do Not Stuff
2
1
Whistler

D7
C3
C8
C2
A7
A2
B8
A3

MDA[32..63]

C8921
Do Not Stuff
2
1
Whistler

MDA36
MDA38
MDA33
MDA39
MDA32
MDA34
MDA35
MDA37

C8916
Do Not Stuff
2
1
Whistler

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

E3
F7
F2
F8
H3
H8
G2
H7

84
84

84,88
84,88
84,88
84,88
84,88
84,88
84,88
84,88
84,88
84,88
84,88
84,88
84,88
84,88

MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
MAA12
MAA13

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
M7

84,88
84,88
84,88

A_BA0
A_BA1
A_BA2

M2
N8
M3
J7
K7

CLKA1
CLKA1#

G1
F9
E8
E2
D8
D1
B9
B1
G9

84

CKEA1

K9

84
84

DQMA6
DQMA7

D3
E7

84
84
84

WEA1#
CASA1#
RASA1#

L3
K3
J3

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

DQSU
DQSU#

VREFDQ
VREFCA
ZQ

DQSL
DQSL#
ODT

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC#
A13
NC#M7

CS#
RESET#
NC#T7
NC#L9
NC#L1
NC#J9
NC#J1
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

BA0
BA1
BA2
CK
CK#
CKE

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

DMU
DML
WE#
CAS#
RAS#

E3
F7
F2
F8
H3
H8
G2
H7

MDA61
MDA57
MDA63
MDA60
MDA59
MDA56
MDA62
MDA58

D7
C3
C8
C2
A7
A2
B8
A3

MDA50
MDA55
MDA49
MDA52
MDA48
MDA54
MDA51
MDA53

MDA[32..63]

84

D

C7
B7

QSAP_6 84
QSAN_6 84

F3
G3

QSAP_7 84
QSAN_7 84

K1

ODTA1

L2
T2

CSA1#_0 84
MEM_RST 84,88,90,91

84

T7
L9
L1
J9
J1

C

J8
M1
M9
J2
P9
G8
B3
T1
A9
T9
E1
P1
G1
F9
E8
E2
D8
D1
B9
B1
G9
B

2

B

K9

CKEA1

R8908
Do Not Stuff

2

Whistler

84

VREFDQ
VREFCA
ZQ

2

R8907
Do Not Stuff

1

CLKA1
CLKA1#
1

84
84

84,88
84,88
84,88
84,88
84,88
84,88
84,88
84,88
84,88
84,88
84,88
84,88
84,88
84,88

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

VRAM41
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

C8917
Do Not Stuff
2
1
Whistler

A8
A1
C1
C9
D2
E9
F1
H9
H2

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

C8919
Do Not Stuff
2
1
Whistler

C8912
Do Not Stuff
2
1
Whistler
2
1
Whistler

C8913
Do Not Stuff
2
1
Whistler
C8907

C8910
Do Not Stuff
2
1
Whistler
C8905

Do Not Stuff

Do Not Stuff

VRAM3_VREF
VRAM4_VREF

2
1
Whistler

C8911
Do Not Stuff
2
1
Whistler

C8908
Do Not Stuff
2
1
Whistler

C8909
Do Not Stuff
2
1
Whistler

D

C8906
Do Not Stuff
2
1
Whistler

C8902
Do Not Stuff
2
1
Whistler

VRAM31
K8
K2
N1
R9
B2
D9
G7
R1
N9

Do Not Stuff

Do Not Stuff

Whistler

Whistler
1D5V_VGA_S0
1

1D5V_VGA_S0
1

R8905
Do Not Stuff
R8901
Do Not Stuff

2

Whistler

Whistler

2

1

1

C8904
Do Not Stuff

Whistler

2

Whistler

Whistler

2

Whistler

R8906
Do Not Stuff

C8901
Do Not Stuff

2

1
R8902
Do Not Stuff

1

2

VRAM4_VREF
VRAM3_VREF

A

A

DQ15 AMD DIS SAMSUNG TI

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

5

4

3

2

GPU-VRAM3,4 (2/4)

Size
A3

Document Number

Date:

Thursday, May 26, 2011

Rev

QUEEN AMD Muxless/UMA
Sheet
1

89

of

X00
104

5

4

3

2

1D5V_VGA_S0

1

1D5V_VGA_S0

VRAM5_VREF
VRAM6_VREF

C

20090902

2

DIS_PX

VRAM_ZQ5
243R2F-2-GP

H1
M8
L8

84,91
84,91
84,91
84,91
84,91
84,91
84,91
84,91
84,91
84,91
84,91
84,91
84,91
84,91

MAB0
MAB1
MAB2
MAB3
MAB4
MAB5
MAB6
MAB7
MAB8
MAB9
MAB10
MAB11
MAB12
MAB13

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
M7

84,91
84,91
84,91

B_BA0
B_BA1
B_BA2

M2
N8
M3
J7
K7

VRAM61

DQSU
DQSU#

VREFDQ
VREFCA
ZQ

DQSL
DQSL#
ODT

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC#
A13
NC#M7

CS#
RESET#
NC#T7
NC#L9
NC#L1
NC#J9
NC#J1
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

BA0
BA1
BA2

R9007
56R2F-1-GP

84

CKEB0

K9

DIS_PX
84
84

DQMB3
DQMB1

D3
E7

84
84
84

WEB0#
CASB0#
RASB0#

L3
K3
J3

R9008
56R2F-1-GP

CK
CK#

2

2

DIS_PX

CKE
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

DMU
DML

1

GPU_CLKB0_T

DIS_PX

2

C9003
SCD01U16V2KX-3GP

WE#
CAS#
RAS#

C7
B7

QSBP_3 84
QSBN_3 84

F3
G3

QSBP_1 84
QSBN_1 84

K1

ODTB0

L2
T2

K8
K2
N1
R9
B2
D9
G7
R1
N9

C9019
SC1U6D3V2KX-GP
2
1
DIS_PX
C9014
C9020
Do Not Stuff
SCD1U10V2KX-5GP
2
1
2
1
DIS_PX

C9017
SC1U6D3V2KX-GP
2
1
DIS_PX

C9018
SC1U6D3V2KX-GP
2
1
DIS_PX

C9016
SCD1U10V2KX-5GP
2
1
DIS_PX

MDB26
MDB27
MDB30
MDB24
MDB31
MDB25
MDB29
MDB28

84

C9013
SC10U6D3V5KX-1GP
2
1
DIS_PX

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

D7
C3
C8
C2
A7
A2
B8
A3

MDB[0..31]

C9015
SC1U6D3V2KX-GP
2
1
DIS_PX

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

MDB14
MDB13
MDB12
MDB15
MDB11
MDB8
MDB9
MDB10

C9011
SC1U6D3V2KX-GP
2
1
DIS_PX

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

E3
F7
F2
F8
H3
H8
G2
H7

C9012
SC1U6D3V2KX-GP
2
1
DIS_PX

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

1

CLKB0
CLKB0#
1

84
84

C9010
SC1U6D3V2KX-GP
2
1
DIS_PX

C9023
SC1U6D3V2KX-GP
2
1
DIS_PX
1

R9004

A8
A1
C1
C9
D2
E9
F1
H9
H2

C9007
SC10U6D3V5KX-1GP
2
1
DIS_PX

C9022
SC1U6D3V2KX-GP
2
1
DIS_PX

C9005
SC10U6D3V5KX-1GP
2
1
DIS_PX

C9021
SC1U6D3V2KX-GP
2
1
DIS_PX

C9008
SCD1U10V2KX-5GP
2
1
DIS_PX

C9009
SC1U6D3V2KX-GP
2
1
DIS_PX

D

C9006
SCD1U10V2KX-5GP
2
1
DIS_PX

C9002
SC1U6D3V2KX-GP
2
1
DIS_PX

VRAM51
K8
K2
N1
R9
B2
D9
G7
R1
N9

A8
A1
C1
C9
D2
E9
F1
H9
H2

DY

VRAM6_VREF
VRAM5_VREF
1
R9006

2

DIS_PX

VRAM_ZQ6
243R2F-2-GP

84

CSB0#_0 84
MEM_RST 84,88,89,91

T7
L9
L1
J9
J1
J8
M1
M9
J2
P9
G8
B3
T1
A9
T9
E1
P1

84
84

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

84,91
84,91
84,91
84,91
84,91
84,91
84,91
84,91
84,91
84,91
84,91
84,91
84,91
84,91

MAB0
MAB1
MAB2
MAB3
MAB4
MAB5
MAB6
MAB7
MAB8
MAB9
MAB10
MAB11
MAB12
MAB13

84,91
84,91
84,91

B_BA0
B_BA1
B_BA2

M2
N8
M3

84

CKEB0

K9

84
84

DQMB0
DQMB2

D3
E7

84
84
84

WEB0#
CASB0#
RASB0#

L3
K3
J3

DQSU
DQSU#

VREFDQ
VREFCA
ZQ

DQSL
DQSL#
ODT

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC#
A13
NC#M7

CS#
RESET#
NC#T7
NC#L9
NC#L1
NC#J9
NC#J1
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

BA0
BA1
BA2

J7
K7

CLKB0
CLKB0#

G1
F9
E8
E2
D8
D1
B9
B1
G9

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

H1
M8
L8
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
M7

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

CK
CK#
CKE

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

DMU
DML
WE#
CAS#
RAS#

K4W1G1646E-HC12-GP

K4W1G1646E-HC12-GP

DIS_PX

DIS_PX

E3
F7
F2
F8
H3
H8
G2
H7

MDB16
MDB18
MDB20
MDB19
MDB22
MDB17
MDB23
MDB21

D7
C3
C8
C2
A7
A2
B8
A3

MDB1
MDB5
MDB2
MDB4
MDB3
MDB7
MDB0
MDB6

MDB[0..31]

84

D

C7
B7

QSBP_0 84
QSBN_0 84

F3
G3

QSBP_2 84
QSBN_2 84

K1

ODTB0

L2
T2

CSB0#_0 84
MEM_RST 84,88,89,91

84

T7
L9
L1
J9
J1

C

J8
M1
M9
J2
P9
G8
B3
T1
A9
T9
E1
P1
G1
F9
E8
E2
D8
D1
B9
B1
G9

B

B

1

1D5V_VGA_S0

1

1D5V_VGA_S0

R9001
2K1R2F-GP

R9003
2K1R2F-GP
2

DIS_PX

2

DIS_PX

1

DIS_PX

C9004
SCD1U10V2KX-5GP

DIS_PX

2

DIS_PX

2

1

1
R9005
2K1R2F-GP

2

DIS_PX

VRAM6_VREF

C9001
SCD1U10V2KX-5GP

2

1

VRAM5_VREF

R9002
2K1R2F-GP

A

Check R9001 & R9002 Change to 4.99K or no
difference?

Check R9001 & R9002 Change to 4.99K or no
difference?

A

DQ15 AMD DIS SAMSUNG TI

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

GPU-VRAM5,6 (3/4)
5

4

3

2

Size
A3

Document Number

Date:

Thursday, May 26, 2011

Rev

QUEEN AMD Muxless/UMA
Sheet
1

90

of

X00
104

5

4

3

2

1D5V_VGA_S0

1

1D5V_VGA_S0

R9103

C

DIS_PX

MAB0
MAB1
MAB2
MAB3
MAB4
MAB5
MAB6
MAB7
MAB8
MAB9
MAB10
MAB11
MAB12
MAB13

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
M7

84,90
84,90
84,90

B_BA0
B_BA1
B_BA2

M2
N8
M3
J7
K7

DQSU
DQSU#

VREFDQ
VREFCA
ZQ

DQSL
DQSL#
ODT

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC#
A13
NC#M7

CS#
RESET#
NC#T7
NC#L9
NC#L1
NC#J9
NC#J1
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

BA0
BA1
BA2
CK
CK#

1

CLKB1
CLKB1#
R9107
56R2F-1-GP

R9108
56R2F-1-GP
2

K9

CKEB1

DIS_PX
84

2

DIS_PX

84

84

DQMB4
DQMB5

D3
E7

84
84
84

WEB1#
CASB1#
RASB1#

L3
K3
J3

CKE
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

DMU
DML

DIS_PX

WE#
CAS#
RAS#

C7
B7

QSBP_4 84
QSBN_4 84

F3
G3

QSBP_5 84
QSBN_5 84

K1

ODTB1

L2
T2

1

2

R9104

K8
K2
N1
R9
B2
D9
G7
R1
N9

C9123
SCD1U10V2KX-5GP
2
1
DIS_PX

C9122
SC1U6D3V2KX-GP
2
1
DIS_PX

C9121
SC1U6D3V2KX-GP
2
1
DIS_PX

VRAM8_VREF
VRAM7_VREF

DIS_PX

A8
A1
C1
C9
D2
E9
F1
H9
H2

VRAM_ZQ8
243R2F-2-GP

84

CSB1#_0 84
MEM_RST 84,88,89,90

T7
L9
L1
J9
J1
J8
M1
M9
J2
P9
G8
B3
T1
A9
T9
E1
P1

C9120
SC1U6D3V2KX-GP
2
1
DIS_PX

C9119
SCD1U10V2KX-5GP
2
1
DIS_PX

MDB36
MDB35
MDB39
MDB32
MDB37
MDB33
MDB38
MDB34

84
C9118
SC1U6D3V2KX-GP
2
1
DIS_PX

D7
C3
C8
C2
A7
A2
B8
A3

MDB[32..63]

84
84

H1
M8
L8

84,90
84,90
84,90
84,90
84,90
84,90
84,90
84,90
84,90
84,90
84,90
84,90
84,90
84,90

MAB0
MAB1
MAB2
MAB3
MAB4
MAB5
MAB6
MAB7
MAB8
MAB9
MAB10
MAB11
MAB12
MAB13

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
M7

84,90
84,90
84,90

B_BA0
B_BA1
B_BA2

M2
N8
M3
J7
K7

CLKB1
CLKB1#

G1
F9
E8
E2
D8
D1
B9
B1
G9

84

CKEB1

K9

84
84

DQMB7
DQMB6

D3
E7

84
84
84

WEB1#
CASB1#
RASB1#

L3
K3
J3

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

DQSU
DQSU#

VREFDQ
VREFCA
ZQ

DQSL
DQSL#
ODT

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC#
A13
NC#M7

CS#
RESET#
NC#T7
NC#L9
NC#L1
NC#J9
NC#J1
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

BA0
BA1
BA2
CK
CK#
CKE

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

DMU
DML
WE#
CAS#
RAS#

E3
F7
F2
F8
H3
H8
G2
H7

MDB53
MDB51
MDB55
MDB49
MDB54
MDB48
MDB52
MDB50

D7
C3
C8
C2
A7
A2
B8
A3

MDB61
MDB62
MDB58
MDB59
MDB63
MDB56
MDB57
MDB60

MDB[32..63]

84

D

C7
B7

QSBP_7 84
QSBN_7 84

F3
G3

QSBP_6 84
QSBN_6 84

K1

ODTB1

L2
T2

CSB1#_0 84
MEM_RST 84,88,89,90

84

T7
L9
L1
J9
J1

C

J8
M1
M9
J2
P9
G8
B3
T1
A9
T9
E1
P1
G1
F9
E8
E2
D8
D1
B9
B1
G9
B

2

K4W1G1646E-HC12-GP

K4W1G1646E-HC12-GP

DIS_PX

DIS_PX

1

1D5V_VGA_S0

1

1D5V_VGA_S0

R9101
2K1R2F-GP

R9105
2K1R2F-GP
2

DIS_PX

2

DIS_PX

1

1

1

R9106
2K1R2F-GP

DIS_PX

2

DIS_PX

C9104
SCD1U10V2KX-5GP

DIS_PX

2

R9102
2K1R2F-GP

DIS_PX

VRAM8_VREF

C9101
SCD1U10V2KX-5GP

2

1

VRAM7_VREF

2

B

1

GPU_CLKB1_T

C9103
SCD01U16V2KX-3GP

MDB40
MDB43
MDB47
MDB44
MDB41
MDB45
MDB42
MDB46

C9117
SC1U6D3V2KX-GP
2
1
DIS_PX

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

E3
F7
F2
F8
H3
H8
G2
H7

C9116
SC10U6D3V5KX-1GP
2
1
DIS_PX

H1
M8
VRAM_ZQ7
L8
243R2F-2-GP

84,90
84,90
84,90
84,90
84,90
84,90
84,90
84,90
84,90
84,90
84,90
84,90
84,90
84,90

1

84
84

2

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

C9114
SC1U6D3V2KX-GP
2
1
DIS_PX

C9113
SC1U6D3V2KX-GP
2
1
DIS_PX

C9112
SC1U6D3V2KX-GP
2
1
DIS_PX
1

VRAM81

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

C9115
SC10U6D3V5KX-1GP
2
1
DIS_PX

VRAM7_VREF
VRAM8_VREF

A8
A1
C1
C9
D2
E9
F1
H9
H2

C9106
SC10U6D3V5KX-1GP
2
1
DIS_PX

C9105
SC10U6D3V5KX-1GP
2
1
DIS_PX

DY

C9111
SCD1U10V2KX-5GP
2
1
DIS_PX

C9110
Do Not Stuff
2
1

DY

C9109
SC1U6D3V2KX-GP
2
1
DIS_PX

C9108
Do Not Stuff
2
1

D

C9107
SC1U6D3V2KX-GP
2
1
DIS_PX

C9102
SC1U6D3V2KX-GP
2
1
DIS_PX

VRAM71
K8
K2
N1
R9
B2
D9
G7
R1
N9

A

A

DQ15 AMD DIS SAMSUNG TI

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

GPU-VRAM7,8 (4/4)
5

4

3

2

Size
A3

Document Number

Date:

Thursday, May 26, 2011

Rev

QUEEN AMD Muxless/UMA
Sheet
1

91

of

X00
104

5

DCBATOUT

4

3

2

1

PWR_DCBATOUT_VGA_CORE
PG9201

2

1

DIS_PX

Do Not Stuff
PG9202

2

1

DIS_PX

Do Not Stuff
PG9203

2

1

DIS_PX

Do Not Stuff
PG9204

2
D

1

DIS_PX
D

Do Not Stuff
PG9231

2

1

DIS_PX

Do Not Stuff
PG9232

2

1

DIS_PX

Do Not Stuff

PWR_DCBATOUT_VGA_CORE

2
DIS_PX

2
1

1

1
2

2

4
3
2
1
PU9203
Do Not Stuff

PWR_VGA_CORE_VOUT

65BOM

PWR_VGA_CORE_VOUT

1

1

S
S
S
G

DIS_PX

PR9204
10R2F-L-GP

4
3
2
1

RT8208BGQW-GP

DIS_PX

20100520

DIS_PX
1

FB_VDDC

Do Not Stuff

C

Do Not Stuff

2

DIS_PX
1

86

PTC9203

DY

Matsuki cap 390uF
2.5V, ESR=10 mohm
6.3Φ×5.7L

2

PR9213
Do Not Stuff

DY

1

85

1

85

PWRCNTL_1

1

PWRCNTL_0

PTC9202

2

PWR_VGA_CORE_D1
PWR_VGA_CORE_D0

PTC9201

2

PWR_VGA_CORE_FB

1

7
3
14
5
6

PC9215

2

1
1
2

IND-1D5UH-34-GP

2

VOUT

2

DIS_PX

Do Not Stuff

GND

PL9201

1

Do Not Stuff

DIS_PX

G0
FB
G1
D1
D0

VGA_CORE

SCD1U25V3KX-GP

SE390U2D5VM-7GP

17

EM/DEM

PWR_VGA_CORE_UGATE
PWR_VGA_CORE_PHASE
PWR_VGA_CORE_LGATE

SCD1U10V2KX-4GP

15

12
11
8

D
D
D
D

PC9204DIS_PX
SC1U10V2KX-1GP

PGOOD
CS

DIS_PX

PR9205
8209A_EN/DEM_VGA
11K3R3F-2-GP

Iomax=14.9A
19.37A
Source Exif Data: 
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XMP Toolkit                     : Adobe XMP Core 4.0-c316 44.253921, Sun Oct 01 2006 17:14:39
Format                          : application/pdf
Creator                         : 
Title                           : Wistron DQDN15 AMD QUEEN M12 - Schematics. www.s-manuals.com.
Subject                         : Wistron DQDN15 AMD QUEEN M12 - Schematics. www.s-manuals.com.
Create Date                     : 2011:05:27 21:39:54
Creator Tool                    : PScript5.dll Version 5.2.2
Modify Date                     : 2016:02:19 22:54:21+02:00
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Has XFA                         : No
Page Count                      : 104
Keywords                        : Wistron, DQDN15, AMD, QUEEN, M12, -, Schematics., www.s-manuals.com.

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