Wistron SJV50 PU Schematics. Www.s Manuals.com. R 1 Schematics
User Manual: Motherboard Wistron SJV50-PU - Schematics. Free.
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5 4 3 2 1 SJV50-PU Block Diagram DDR2 SODIMM DDR2 SODIMM DDR II 533/667 33 4,5, 6,7 638-Pin uFCPGA638 16,17 HyperTransport CLK GEN. 14.318MHz 16x16 L1: Signal 1 L2: VCC L3: Inner Signal 2 L4: Inner Signal 3 L5: GND L6: Signal 4 Project code: 91.4BX01.001 PCB P/N : 48.4BX04.011 REVISION : 08260-1 G792 Video RAM HDMI INPUT 20 ICS9LPRS480BKLFT OUTPUT DCBATOUT 3 North Bridge AMD RS780M PCIex16 VCC_CORE_S0 LCD 18 GPU ON BOARD M92-M2 CPU I/F LVDS, CRT I/F INTEGRATED GRAHPICS PCI-E x 1 19 LAN 10/100/1000 BCM5764/5784 8,9,10 SYSTEM DC/DC CRT 50, 51, 52, 53, 54, 55, 56 C D CPU V_CORE 64Mbx16x4 55,56 IN DIMM2 AMD Giffin CPU S1G2 (35W) 16,17 OUT DIMM1 D DDR II 533/667 PCB Layer Stackup TXFM RJ45 26 25 INPUT OUTPUT 1D1V_S0 1D2V_S0 1D8V_S3 DCBATOUT 26 C SYSTEM DC/DC 25MHz PCI-E x 4 INPUT Mini Card(1)Half OUTPUT DCBATOUT 802.11a/b/g/n Codec 29 South Bridge AZALIA CX20561 MIC In USB 28 SD/ MMC/ MS MS PRO/ XD 5 in 1 CardReader RTS5159 31 ACPI 1.1 LPC I/F AZALIA AMP G1454 SYSTEM LDO 32 INPUT OUTPUT 1D8V_S3 0D9V_S3 SYSTEM LDO Line Out 29 802.11a/b/g/n 32.768KHz USB 2.0/1.1 ports ETHERNET (10/100/1000Mb) High Definition Audio ATA 66/100 32 Mini Card(2) 25MHz AMD SB700 27 29 B PCI-E x 2 5V_S5 3D3V_S5 PCI/PCI BRIDGE INPUT OUTPUT 3D3V_S5 3D3V_S0 3D3V_S0 1D2V_S5 2D5V_S0 1D5V_S0 B 31 SYSTEM LDO LPC BUS INPUT OUTPUT INT.SPKR 11,12,13,14,15 USB 32.768KHz 30 HDD 21 SATA USB 30 MODEM MDC Card USB x 4 RJ11 5V_AUX_S5 CCD .3M 18 SPI I/F KBC Winbond WPC773L Touch Pad 36 BIOS LPC W25X80-VSS DCBATOUT 3D3V_AUX_S5 DEBUG CONN. 35 35 34 INT. KB 34 Battery Charger INPUTS OUTPUTS AD+ BAT+ DCBATOUT A A USB 4 Port24 MINI USB BlueTooth SJV50 Wistron Incorporated 21F, 88, Hsin Tai Wu Rd Hsichih, Taipei 23 Title CDROM BLOCK DIAGRAM SATA 22 5 4 3 2 Size A3 Document Number Date: Wednesday, February 25, 2009 Rev SJV50-PU -1 Sheet 1 1 of 59 5 4 3 2 1 USB PCIE D PCIE0 PCIE1 PCIE2 Pair LAN MINICARD1 MINICARD2 PCIE3 Device 11 CardReader 10 CCD 9 Mini Card2 8 USB4 7 USB1 6 USB2 5 BlueTooth 4 NC 3 NC 2 NC 1 Mini Card1 0 USB3 D OCP2# OCP1# OCP0# C C B B SJV50 A A Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title USB&PCIE ROUTING Size A3 Document Number 5 4 3 2 Rev -1 SJV50-PU Date: Wednesday, February 25, 2009 Sheet 1 2 of 59 A B 3D3V_S0 C D 3D3V_CLK_VDD 3D3V_S0 2R3J-GP 3000mA.80ohm C400 2 DY SC4D7U6D3V3KX-GP 2 1 3D3V_48MPWR_S0 2 1 1 SCD1U10V2KX-4GP 2 1 C436 2 1 1 C394 SCD1U10V2KX-4GP 2 1 C422 SCD1U10V2KX-4GP 2 1 C438 SCD1U10V2KX-4GP 2 C433 SCD1U10V2KX-4GP SCD1U10V2KX-4GP SC10U10V5ZY-1GP 2 C396 2 C428 SC10U10V5ZY-1GP 4 1 1 1 R164 C432 2 1 2 R175 0R0603-PAD E Due to PLL issue on current clock chip, the SBlink clock need to come from SRC clocks for RS740 and RS780. Future clock chip revision will fix this. C398 SC1U10V2KX-1GP 4 Clock chip has internal serial terminations for differencial pairs, external resistors are reserved for debug purpose. 3D3V_S0 U24 16 17 11 VDDSRC VDDSRC_IO VDDSRC_IO 35 34 VDDSB_SRC VDDSB_SRC_IO 40 4 55 56 63 VDDSATA VDD VDDHTT VDDREF VDD48 PD# 51 PD# SRC6T_LPRS SRC6C_LPRS CLK_27M_SSIN CLK_27M_M92 22 21 20 19 15 14 13 12 9 8 42 41 6 5 11 CLK_PCIE_SB 11 CLK_PCIE_SB# 25 CLK_PCIE_LAN 25 CLK_PCIE_LAN# 9 CLK_NB_GPPSB 9 CLK_NB_GPPSB# 32 CLK_PCIE_MINI1 32 CLK_PCIE_MINI1# 32 CLK_PCIE_MINI2 32 CLK_PCIE_MINI2# TPAD14-GP TPAD14-GP TPAD14-GP TPAD14-GP TP205 TP202 TP196 TP217 1 1 1 1 20090106 SB modify 2 37 36 32 31 54 53 9 CLK_NBHT_CLK 9 CLK_NBHT_CLK# 2 C405 SC33P50V2JN-3GP 1 2 3 ATIG0T_LPRS ATIG0C_LPRS ATIG1T_LPRS ATIG1C_LPRS 30 29 28 27 CLKREQ0# CLKREQ1# CLKREQ2# CLKREQ3# CLKREQ4# 23 45 44 39 38 CPUKG0T_LPRS CPUKG0C_LPRS SRC0T_LPRS SRC0C_LPRS 48MHZ_0 SRC1T_LPRS SRC1C_LPRS SRC2T_LPRS REF0/SEL_HTT66 SRC2C_LPRS REF1/SEL_SATA SRC3T_LPRS REF2/SEL_27 SRC3C_LPRS SRC4T_LPRS SRC4C_LPRS SRC6T/SATAT_LPRS GNDSATA SRC6C/SATAC_LPRS GNDATIG SRC7T_LPRS/27MHZ_SS GND SRC7C_LPRS/27MHZ_NS GNDHTT GNDREF GNDCPU SB_SRC0T_LPRS GND48 SB_SRC0C_LPRS SB_SRC1T_LPRS GNDSRC SB_SRC1C_LPRS GNDSRC 50 49 SB_MEM_CLK 12,16,17 SB_MEM_DAT 12,16,17 CLK_PCIE_PEG 50 CLK_PCIE_PEG# 50 CLK_NB_GFX 9 CLK_NB_GFX# 9 CLKREQ0#1 CLKREQ1#1 CLKREQ2#1 CLKREQ3#1 CLKREQ4#1 TP200 TP206 TP207 TP204 TP203 TPAD14-GP TPAD14-GP TPAD14-GP TPAD14-GP TPAD14-GP 3 CLKREQ# Internal pull high CPU_CLK CPU_CLK# 64 CLK_48 59 58 57 REF0 REF1 REF2 6 6 1R161 22R2J-2-GP 1R162 22R2J-2-GP 2 2 CLK48_USB 12 CLK48_5159E 31 20090107_SB mofify 43 24 7 52 60 46 1 R165 REF0 150R2F-1-GP 75R2F-2-GP 2 2 1 33 CLK_NB_14M 9 GND 65 OSC_14M_NB RS780M 1.1V 158R/90.9R R174 10KR2J-3-GP DY 1 RS740 RX780 RS780 HT_REFCLKP 66M SE(SINGLE END) NC 100M DIFF 100M DIFF 100M DIFF 100M DIFF REFCLK_N 14M SE (3.3V) NC 14M SE (1.8V) NC 14M SE (1.1V) vref GFX_REFCLK 100M DIFF 100M DIFF 100M DIFF(IN/OUT)* GPP_REFCLK NC 100M DIFF NC or 100M DIFF OUTPUT GPPSB_REFCLK 100M DIFF 100M DIFF 100M DIFF HT_REFCLKN REFCLK_P PD# 2 2 NB CLOCK INPUT TABLE 2ND = 71.08628.003 1 -1 090223 1 R166 71.09480.A03 2 C856 NB CLOCKS ICS9LPRS480BKLFT-GP 3D3V_S0 C855 10 18 GNDSB_SRC HTT0T_LPRS/66M HTT0C_LPRS/66M G29 SB_MEM_480_CLK 2 G28 1 SB_MEM_480_DAT2 1 GAP-CLOSE GAP-CLOSE 2 2 VDD_REF 3D3V_48MPWR_S0 SMBCLK SMBDAT CL=20pF±0.2pF GEN_XTAL_OUT 1 VDDCPU VDDCPU_IO 61 62 1 48 47 X1 X2 SC22P50V2JN-4GP VDDATIG VDDATIG_IO SC33P50V2JN-3GP SC22P50V2JN-4GP 26 25 1 0R0603-PAD 1 2 R172 C427 SC1U10V2KX-1GP 3 C414 1 X5 X-14D3181MHZ-GP 1D1V_CLK_VDDIO 3D3V_CLK_VDD 2 1 3D3V_CLK_VDD 2 1 C434 2 1 GEN_XTAL_IN SCD1U10V2KX-4GP SCD1U10V2KX-4GP 2 C437 2 1 1 C395 SCD1U10V2KX-4GP 2 C397 SCD1U10V2KX-4GP 2 C399 SCD1U10V2KX-4GP SC10U10V5ZY-1GP SC10U10V5ZY-1GP DY 82.30005.A11 2ND = 82.30005.881 2 C406 1 C415 2 1 1D1V_CLK_VDDIO 1 1 2 R163 0R3-0-U-GP 2 1 2 R176 0R0603-PAD 1D2V_S0 SB_PWRGD 12,39 R173 0R2J-2-GP 3D3V_S0 * RS780 can be used as clock buffer to output two PCIE referecence clocks By deault, chip will configured as input mode, BIOS can program it to output mode. 2 For SB710 R169 10KR2J-3-GP 1 1 SEL_SATA REF1 2 TPAD14-GPTP197 TPAD14-GP TP197 TPAD14-GP TP199 TPAD14-GPTP199 DY 1 R170 10KR2J-3-GP 1 1 REF0 REF1 REF2 27M SEL_HTT66 REF0 SEL_27 REF2 1 SA_20081106 DY 100 MHz non-spreading differential SRC clock R168 0* 100 MHz spreading differential SRC clock 1 66 MHz 3.3V single ended HTT clock 0* 100 MHz differential HTT clock 1* 27 MHz 3.3V single ended enable 0 100 MHz spreading differential SRC clock REF1 110R2F-GP 2 1 R167 75R2F-2-GP 2 CLK_SB_14M 11 SJV50 1 DY Wistron Corporation 1 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title * default CPU_CLK(200MHz) Size Clock Generator ICS9LPRS480BKLFT Document Number Rev SJV50-PU Date: Wednesday, February 25, 2009 A B C D Sheet E -1 3 of 59 A B C D E Placement note: 10ux1,4.7ux1,0.22ux1,180px1 for each group 4 4 1D2V_S0 1 C619 2 1 2 1 2 1 2 1 2 1 2 1 2 2 C618 SC180P50V2JN-1GP C609 SC180P50V2JN-1GP C608 SCD22U6D3V2KX-1GP 2 C625 SCD22U6D3V2KX-1GP 3 C617 SC4D7U6D3V3KX-GP C616 SC4D7U6D3V3KX-GP SC10U6D3V5KX-1GP SC10U6D3V5KX-1GP 1 Place close to socket 1.5Amp C621 ACPU1A D1 D2 D3 D4 VLDT_A0 VLDT_A1 VLDT_A2 VLDT_A3 HT LINK VLDT_B0 VLDT_B1 VLDT_B2 VLDT_B3 AE2 AE3 AE4 AE5 L0_CADOUT_H0 L0_CADOUT_L0 L0_CADOUT_H1 L0_CADOUT_L1 L0_CADOUT_H2 L0_CADOUT_L2 L0_CADOUT_H3 L0_CADOUT_L3 L0_CADOUT_H4 L0_CADOUT_L4 L0_CADOUT_H5 L0_CADOUT_L5 L0_CADOUT_H6 L0_CADOUT_L6 L0_CADOUT_H7 L0_CADOUT_L7 L0_CADOUT_H8 L0_CADOUT_L8 L0_CADOUT_H9 L0_CADOUT_L9 L0_CADOUT_H10 L0_CADOUT_L10 L0_CADOUT_H11 L0_CADOUT_L11 L0_CADOUT_H12 L0_CADOUT_L12 L0_CADOUT_H13 L0_CADOUT_L13 L0_CADOUT_H14 L0_CADOUT_L14 L0_CADOUT_H15 L0_CADOUT_L15 AD1 AC1 AC2 AC3 AB1 AA1 AA2 AA3 W2 W3 V1 U1 U2 U3 T1 R1 AD4 AD3 AD5 AC5 AB4 AB3 AB5 AA5 Y5 W5 V4 V3 V5 U5 T4 T3 HT_CPU_NB_CAD_H0 HT_CPU_NB_CAD_L0 HT_CPU_NB_CAD_H1 HT_CPU_NB_CAD_L1 HT_CPU_NB_CAD_H2 HT_CPU_NB_CAD_L2 HT_CPU_NB_CAD_H3 HT_CPU_NB_CAD_L3 HT_CPU_NB_CAD_H4 HT_CPU_NB_CAD_L4 HT_CPU_NB_CAD_H5 HT_CPU_NB_CAD_L5 HT_CPU_NB_CAD_H6 HT_CPU_NB_CAD_L6 HT_CPU_NB_CAD_H7 HT_CPU_NB_CAD_L7 HT_CPU_NB_CAD_H8 HT_CPU_NB_CAD_L8 HT_CPU_NB_CAD_H9 HT_CPU_NB_CAD_L9 HT_CPU_NB_CAD_H10 HT_CPU_NB_CAD_L10 HT_CPU_NB_CAD_H11 HT_CPU_NB_CAD_L11 HT_CPU_NB_CAD_H12 HT_CPU_NB_CAD_L12 HT_CPU_NB_CAD_H13 HT_CPU_NB_CAD_L13 HT_CPU_NB_CAD_H14 HT_CPU_NB_CAD_L14 HT_CPU_NB_CAD_H15 HT_CPU_NB_CAD_L15 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 HT_NB_CPU_CAD_H0 HT_NB_CPU_CAD_L0 HT_NB_CPU_CAD_H1 HT_NB_CPU_CAD_L1 HT_NB_CPU_CAD_H2 HT_NB_CPU_CAD_L2 HT_NB_CPU_CAD_H3 HT_NB_CPU_CAD_L3 HT_NB_CPU_CAD_H4 HT_NB_CPU_CAD_L4 HT_NB_CPU_CAD_H5 HT_NB_CPU_CAD_L5 HT_NB_CPU_CAD_H6 HT_NB_CPU_CAD_L6 HT_NB_CPU_CAD_H7 HT_NB_CPU_CAD_L7 HT_NB_CPU_CAD_H8 HT_NB_CPU_CAD_L8 HT_NB_CPU_CAD_H9 HT_NB_CPU_CAD_L9 HT_NB_CPU_CAD_H10 HT_NB_CPU_CAD_L10 HT_NB_CPU_CAD_H11 HT_NB_CPU_CAD_L11 HT_NB_CPU_CAD_H12 HT_NB_CPU_CAD_L12 HT_NB_CPU_CAD_H13 HT_NB_CPU_CAD_L13 HT_NB_CPU_CAD_H14 HT_NB_CPU_CAD_L14 HT_NB_CPU_CAD_H15 HT_NB_CPU_CAD_L15 E3 E2 E1 F1 G3 G2 G1 H1 J1 K1 L3 L2 L1 M1 N3 N2 E5 F5 F3 F4 G5 H5 H3 H4 K3 K4 L5 M5 M3 M4 N5 P5 L0_CADIN_H0 L0_CADIN_L0 L0_CADIN_H1 L0_CADIN_L1 L0_CADIN_H2 L0_CADIN_L2 L0_CADIN_H3 L0_CADIN_L3 L0_CADIN_H4 L0_CADIN_L4 L0_CADIN_H5 L0_CADIN_L5 L0_CADIN_H6 L0_CADIN_L6 L0_CADIN_H7 L0_CADIN_L7 L0_CADIN_H8 L0_CADIN_L8 L0_CADIN_H9 L0_CADIN_L9 L0_CADIN_H10 L0_CADIN_L10 L0_CADIN_H11 L0_CADIN_L11 L0_CADIN_H12 L0_CADIN_L12 L0_CADIN_H13 L0_CADIN_L13 L0_CADIN_H14 L0_CADIN_L14 L0_CADIN_H15 L0_CADIN_L15 8 8 8 8 HT_NB_CPU_CLK_H0 HT_NB_CPU_CLK_L0 HT_NB_CPU_CLK_H1 HT_NB_CPU_CLK_L1 J3 J2 J5 K5 L0_CLKIN_H0 L0_CLKIN_L0 L0_CLKIN_H1 L0_CLKIN_L1 L0_CLKOUT_H0 L0_CLKOUT_L0 L0_CLKOUT_H1 L0_CLKOUT_L1 Y1 W1 Y4 Y3 HT_CPU_NB_CLK_H0 8 HT_CPU_NB_CLK_L0 8 HT_CPU_NB_CLK_H1 8 HT_CPU_NB_CLK_L1 8 8 8 8 8 HT_NB_CPU_CTL_H0 HT_NB_CPU_CTL_L0 HT_NB_CPU_CTL_H1 HT_NB_CPU_CTL_L1 N1 P1 P3 P4 L0_CTLIN_H0 L0_CTLIN_L0 L0_CTLIN_H1 L0_CTLIN_L1 L0_CTLOUT_H0 L0_CTLOUT_L0 L0_CTLOUT_H1 L0_CTLOUT_L1 R2 R3 T5 R5 HT_CPU_NB_CTL_H0 8 HT_CPU_NB_CTL_L0 8 HT_CPU_NB_CTL_H1 8 HT_CPU_NB_CTL_L1 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 3 8 8 8 8 8 8 8 8 8 8 8 8 2 SKT-CPU638P-GP-U2 62.10055.111 2ND = 62.10040.471 SKT-BGA638H176 SJV50 1 1 Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title CPU (1 of 4) Size Document Number Rev -1 SJV50-PU Date: Wednesday, February 25, 2009 A B C D Sheet E 4 of 59 A B C D E ACPU1C MEM:DATA Placement note: 4.7ux2,0.22ux1,180px1 for each group Place near to CPU 1 2 1 C140 2 1 2 1 2 1 2 1 C139 SC180P50V2JN-1GP 2 180P x 2 C149 SC180P50V2JN-1GP 2 1 C150 SCD22U6D3V2KX-1GP DY C128 SCD22U6D3V2KX-1GP 2 0.22u X 2 C135 SC4D7U6D3V3KX-GP C123 SC4D7U6D3V3KX-GP DY SC4D7U6D3V3KX-GP SC4D7U6D3V3KX-GP C122 1 4.7u x 4 4 0D9V_S3 CLOSE TO CPU 1D8V_S3 ACPU1B MA0_CS_L0 MA0_CS_L1 MA1_CS_L0 MA1_CS_L1 17 MEM_MA_CKE0 17 MEM_MA_CKE1 J22 J20 MA_CKE0 MA_CKE1 1 2 TP140 TPAD14-GP RSVD_M2 B18 MB0_ODT0 MB0_ODT1 MB1_ODT0 W26 W23 Y26 MEM_MB0_ODT0 16 MEM_MB0_ODT1 16 MB0_CS_L0 MB0_CS_L1 MB1_CS_L0 V26 W25 U22 MEM_MB0_CS#0 16 MEM_MB0_CS#1 16 MB_CKE0 MB_CKE1 J25 H26 MEM_MB_CKE0 16 MEM_MB_CKE1 16 MEM_MB_CLK0_P MEM_MB_CLK0_N MEM_MB_CLK1_P MEM_MB_CLK1_N 17 17 17 17 MEM_MA_CLK0_P MEM_MA_CLK0_N MEM_MA_CLK1_P MEM_MA_CLK1_N N19 N20 E16 F16 Y16 AA16 P19 P20 MA_CLK_H5 MA_CLK_L5 MA_CLK_H1 MA_CLK_L1 MA_CLK_H7 MA_CLK_L7 MA_CLK_H4 MA_CLK_L4 MB_CLK_H5 MB_CLK_L5 MB_CLK_H1 MB_CLK_L1 MB_CLK_H7 MB_CLK_L7 MB_CLK_H4 MB_CLK_L4 P22 R22 A17 A18 AF18 AF17 R26 R25 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 MEM_MA_ADD0 MEM_MA_ADD1 MEM_MA_ADD2 MEM_MA_ADD3 MEM_MA_ADD4 MEM_MA_ADD5 MEM_MA_ADD6 MEM_MA_ADD7 MEM_MA_ADD8 MEM_MA_ADD9 MEM_MA_ADD10 MEM_MA_ADD11 MEM_MA_ADD12 MEM_MA_ADD13 MEM_MA_ADD14 MEM_MA_ADD15 N21 M20 N22 M19 M22 L20 M24 L21 L19 K22 R21 L22 K20 V24 K24 K19 MA_ADD0 MA_ADD1 MA_ADD2 MA_ADD3 MA_ADD4 MA_ADD5 MA_ADD6 MA_ADD7 MA_ADD8 MA_ADD9 MA_ADD10 MA_ADD11 MA_ADD12 MA_ADD13 MA_ADD14 MA_ADD15 MB_ADD0 MB_ADD1 MB_ADD2 MB_ADD3 MB_ADD4 MB_ADD5 MB_ADD6 MB_ADD7 MB_ADD8 MB_ADD9 MB_ADD10 MB_ADD11 MB_ADD12 MB_ADD13 MB_ADD14 MB_ADD15 P24 N24 P26 N23 N26 L23 N25 L24 M26 K26 T26 L26 L25 W24 J23 J24 MEM_MB_ADD0 16 MEM_MB_ADD1 16 MEM_MB_ADD2 16 MEM_MB_ADD3 16 MEM_MB_ADD4 16 MEM_MB_ADD5 16 MEM_MB_ADD6 16 MEM_MB_ADD7 16 MEM_MB_ADD8 16 MEM_MB_ADD9 16 MEM_MB_ADD10 16 MEM_MB_ADD11 16 MEM_MB_ADD12 16 MEM_MB_ADD13 16 MEM_MB_ADD14 16 MEM_MB_ADD15 16 17 MEM_MA_BANK0 17 MEM_MA_BANK1 17 MEM_MA_BANK2 R20 R23 J21 MA_BANK0 MA_BANK1 MA_BANK2 MB_BANK0 MB_BANK1 MB_BANK2 R24 U26 J26 MEM_MB_BANK0 16 MEM_MB_BANK1 16 MEM_MB_BANK2 16 17 MEM_MA_RAS# 17 MEM_MA_CAS# 17 MEM_MA_WE# R19 T22 T24 MA_RAS_L MA_CAS_L MA_WE_L MB_RAS_L MB_CAS_L MB_WE_L U25 U24 U23 MEM_MB_RAS# 16 MEM_MB_CAS# 16 MEM_MB_WE# 16 RN25 1 2 DY C217 C235 4 3 SRN1KJ-7-GP 1 T20 U19 U20 V20 MEM_RSVD_M2 1 VREF_DDR_CLAW TP115 TPAD14-GP C232 2 17 MEM_MA0_CS#0 17 MEM_MA0_CS#1 W17 1 SCD1U10V2KX-4GP MA0_ODT0 MA0_ODT1 MA1_ODT0 MA1_ODT1 MEMVREF VTT_SENSE SC1KP50V2KX-1GP T19 V22 U21 V19 Y10 SC10U6D3V5MX-3GP RSVD_M1 VTT_SENSE 1 MEM_RSVD_M1 MEMZP MEMZN C208 SCD1U10V2KX-4GP 2 1 AF10 AE10 H16 17 MEM_MA0_ODT0 17 MEM_MA0_ODT1 2 MEMZP MEMZN MEM:CMD/CTRL/CLK VTT5 VTT6 VTT7 VTT8 VTT9 1 1D8V_S3 VTT1 VTT2 VTT3 VTT4 W10 AC10 AB10 AA10 A10 2 3 R315 39D2R2F-L-GP 1 2 1 2 R317 39D2R2F-L-GP TP125 TPAD14-GP D10 C10 B10 AD10 16 16 16 16 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 MEM_MA_DATA0 MEM_MA_DATA1 MEM_MA_DATA2 MEM_MA_DATA3 MEM_MA_DATA4 MEM_MA_DATA5 MEM_MA_DATA6 MEM_MA_DATA7 MEM_MA_DATA8 MEM_MA_DATA9 MEM_MA_DATA10 MEM_MA_DATA11 MEM_MA_DATA12 MEM_MA_DATA13 MEM_MA_DATA14 MEM_MA_DATA15 MEM_MA_DATA16 MEM_MA_DATA17 MEM_MA_DATA18 MEM_MA_DATA19 MEM_MA_DATA20 MEM_MA_DATA21 MEM_MA_DATA22 MEM_MA_DATA23 MEM_MA_DATA24 MEM_MA_DATA25 MEM_MA_DATA26 MEM_MA_DATA27 MEM_MA_DATA28 MEM_MA_DATA29 MEM_MA_DATA30 MEM_MA_DATA31 MEM_MA_DATA32 MEM_MA_DATA33 MEM_MA_DATA34 MEM_MA_DATA35 MEM_MA_DATA36 MEM_MA_DATA37 MEM_MA_DATA38 MEM_MA_DATA39 MEM_MA_DATA40 MEM_MA_DATA41 MEM_MA_DATA42 MEM_MA_DATA43 MEM_MA_DATA44 MEM_MA_DATA45 MEM_MA_DATA46 MEM_MA_DATA47 MEM_MA_DATA48 MEM_MA_DATA49 MEM_MA_DATA50 MEM_MA_DATA51 MEM_MA_DATA52 MEM_MA_DATA53 MEM_MA_DATA54 MEM_MA_DATA55 MEM_MA_DATA56 MEM_MA_DATA57 MEM_MA_DATA58 MEM_MA_DATA59 MEM_MA_DATA60 MEM_MA_DATA61 MEM_MA_DATA62 MEM_MA_DATA63 G12 F12 H14 G14 H11 H12 C13 E13 H15 E15 E17 H17 E14 F14 C17 G17 G18 C19 D22 E20 E18 F18 B22 C23 F20 F22 H24 J19 E21 E22 H20 H22 Y24 AB24 AB22 AA21 W22 W21 Y22 AA22 Y20 AA20 AA18 AB18 AB21 AD21 AD19 Y18 AD17 W16 W14 Y14 Y17 AB17 AB15 AD15 AB13 AD13 Y12 W11 AB14 AA14 AB12 AA12 MA_DATA0 MA_DATA1 MA_DATA2 MA_DATA3 MA_DATA4 MA_DATA5 MA_DATA6 MA_DATA7 MA_DATA8 MA_DATA9 MA_DATA10 MA_DATA11 MA_DATA12 MA_DATA13 MA_DATA14 MA_DATA15 MA_DATA16 MA_DATA17 MA_DATA18 MA_DATA19 MA_DATA20 MA_DATA21 MA_DATA22 MA_DATA23 MA_DATA24 MA_DATA25 MA_DATA26 MA_DATA27 MA_DATA28 MA_DATA29 MA_DATA30 MA_DATA31 MA_DATA32 MA_DATA33 MA_DATA34 MA_DATA35 MA_DATA36 MA_DATA37 MA_DATA38 MA_DATA39 MA_DATA40 MA_DATA41 MA_DATA42 MA_DATA43 MA_DATA44 MA_DATA45 MA_DATA46 MA_DATA47 MA_DATA48 MA_DATA49 MA_DATA50 MA_DATA51 MA_DATA52 MA_DATA53 MA_DATA54 MA_DATA55 MA_DATA56 MA_DATA57 MA_DATA58 MA_DATA59 MA_DATA60 MA_DATA61 MA_DATA62 MA_DATA63 17 17 17 17 17 17 17 17 MEM_MA_DM0 MEM_MA_DM1 MEM_MA_DM2 MEM_MA_DM3 MEM_MA_DM4 MEM_MA_DM5 MEM_MA_DM6 MEM_MA_DM7 E12 C15 E19 F24 AC24 Y19 AB16 Y13 MA_DM0 MA_DM1 MA_DM2 MA_DM3 MA_DM4 MA_DM5 MA_DM6 MA_DM7 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 MEM_MA_DQS0_P MEM_MA_DQS0_N MEM_MA_DQS1_P MEM_MA_DQS1_N MEM_MA_DQS2_P MEM_MA_DQS2_N MEM_MA_DQS3_P MEM_MA_DQS3_N MEM_MA_DQS4_P MEM_MA_DQS4_N MEM_MA_DQS5_P MEM_MA_DQS5_N MEM_MA_DQS6_P MEM_MA_DQS6_N MEM_MA_DQS7_P MEM_MA_DQS7_N G13 H13 G16 G15 C22 C21 G22 G21 AD23 AC23 AB19 AB20 Y15 W15 W12 W13 MA_DQS_H0 MA_DQS_L0 MA_DQS_H1 MA_DQS_L1 MA_DQS_H2 MA_DQS_L2 MA_DQS_H3 MA_DQS_L3 MA_DQS_H4 MA_DQS_L4 MA_DQS_H5 MA_DQS_L5 MA_DQS_H6 MA_DQS_L6 MA_DQS_H7 MA_DQS_L7 MB_DATA0 MB_DATA1 MB_DATA2 MB_DATA3 MB_DATA4 MB_DATA5 MB_DATA6 MB_DATA7 MB_DATA8 MB_DATA9 MB_DATA10 MB_DATA11 MB_DATA12 MB_DATA13 MB_DATA14 MB_DATA15 MB_DATA16 MB_DATA17 MB_DATA18 MB_DATA19 MB_DATA20 MB_DATA21 MB_DATA22 MB_DATA23 MB_DATA24 MB_DATA25 MB_DATA26 MB_DATA27 MB_DATA28 MB_DATA29 MB_DATA30 MB_DATA31 MB_DATA32 MB_DATA33 MB_DATA34 MB_DATA35 MB_DATA36 MB_DATA37 MB_DATA38 MB_DATA39 MB_DATA40 MB_DATA41 MB_DATA42 MB_DATA43 MB_DATA44 MB_DATA45 MB_DATA46 MB_DATA47 MB_DATA48 MB_DATA49 MB_DATA50 MB_DATA51 MB_DATA52 MB_DATA53 MB_DATA54 MB_DATA55 MB_DATA56 MB_DATA57 MB_DATA58 MB_DATA59 MB_DATA60 MB_DATA61 MB_DATA62 MB_DATA63 C11 A11 A14 B14 G11 E11 D12 A13 A15 A16 A19 A20 C14 D14 C18 D18 D20 A21 D24 C25 B20 C20 B24 C24 E23 E24 G25 G26 C26 D26 G23 G24 AA24 AA23 AD24 AE24 AA26 AA25 AD26 AE25 AC22 AD22 AE20 AF20 AF24 AF23 AC20 AD20 AD18 AE18 AC14 AD14 AF19 AC18 AF16 AF15 AF13 AC12 AB11 Y11 AE14 AF14 AF11 AD11 MEM_MB_DATA0 16 MEM_MB_DATA1 16 MEM_MB_DATA2 16 MEM_MB_DATA3 16 MEM_MB_DATA4 16 MEM_MB_DATA5 16 MEM_MB_DATA6 16 MEM_MB_DATA7 16 MEM_MB_DATA8 16 MEM_MB_DATA9 16 MEM_MB_DATA10 16 MEM_MB_DATA11 16 MEM_MB_DATA12 16 MEM_MB_DATA13 16 MEM_MB_DATA14 16 MEM_MB_DATA15 16 MEM_MB_DATA16 16 MEM_MB_DATA17 16 MEM_MB_DATA18 16 MEM_MB_DATA19 16 MEM_MB_DATA20 16 MEM_MB_DATA21 16 MEM_MB_DATA22 16 MEM_MB_DATA23 16 MEM_MB_DATA24 16 MEM_MB_DATA25 16 MEM_MB_DATA26 16 MEM_MB_DATA27 16 MEM_MB_DATA28 16 MEM_MB_DATA29 16 MEM_MB_DATA30 16 MEM_MB_DATA31 16 MEM_MB_DATA32 16 MEM_MB_DATA33 16 MEM_MB_DATA34 16 MEM_MB_DATA35 16 MEM_MB_DATA36 16 MEM_MB_DATA37 16 MEM_MB_DATA38 16 MEM_MB_DATA39 16 MEM_MB_DATA40 16 MEM_MB_DATA41 16 MEM_MB_DATA42 16 MEM_MB_DATA43 16 MEM_MB_DATA44 16 MEM_MB_DATA45 16 MEM_MB_DATA46 16 MEM_MB_DATA47 16 MEM_MB_DATA48 16 MEM_MB_DATA49 16 MEM_MB_DATA50 16 MEM_MB_DATA51 16 MEM_MB_DATA52 16 MEM_MB_DATA53 16 MEM_MB_DATA54 16 MEM_MB_DATA55 16 MEM_MB_DATA56 16 MEM_MB_DATA57 16 MEM_MB_DATA58 16 MEM_MB_DATA59 16 MEM_MB_DATA60 16 MEM_MB_DATA61 16 MEM_MB_DATA62 16 MEM_MB_DATA63 16 MB_DM0 MB_DM1 MB_DM2 MB_DM3 MB_DM4 MB_DM5 MB_DM6 MB_DM7 A12 B16 A22 E25 AB26 AE22 AC16 AD12 MEM_MB_DM0 MEM_MB_DM1 MEM_MB_DM2 MEM_MB_DM3 MEM_MB_DM4 MEM_MB_DM5 MEM_MB_DM6 MEM_MB_DM7 MB_DQS_H0 MB_DQS_L0 MB_DQS_H1 MB_DQS_L1 MB_DQS_H2 MB_DQS_L2 MB_DQS_H3 MB_DQS_L3 MB_DQS_H4 MB_DQS_L4 MB_DQS_H5 MB_DQS_L5 MB_DQS_H6 MB_DQS_L6 MB_DQS_H7 MB_DQS_L7 C12 B12 D16 C16 A24 A23 F26 E26 AC25 AC26 AF21 AF22 AE16 AD16 AF12 AE12 MEM_MB_DQS0_P MEM_MB_DQS0_N MEM_MB_DQS1_P MEM_MB_DQS1_N MEM_MB_DQS2_P MEM_MB_DQS2_N MEM_MB_DQS3_P MEM_MB_DQS3_N MEM_MB_DQS4_P MEM_MB_DQS4_N MEM_MB_DQS5_P MEM_MB_DQS5_N MEM_MB_DQS6_P MEM_MB_DQS6_N MEM_MB_DQS7_P MEM_MB_DQS7_N 4 3 16 16 16 16 16 16 16 16 2 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 SKT-CPU638P-GP-U2 SKT-CPU638P-GP-U2 62.10055.111 62.10055.111 1 2ND = 62.10055.251 2ND = 62.10055.251 1 Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title CPU (2 of 4) Size Document Number Rev -1 SJV50-PU Date: Wednesday, February 25, 2009 A B C D Sheet E 5 of 59 5 4 3 2 1 The Processor has reached a preset maximum operating temperature. 100℃ I=Active HTC O=FAN 8 7 6 5 1D8V_S0 RN52 SRN300J-1-GP 2D5V_S0 2D5V_VDDA_S0 1 1 3 3 1D8V_S3 1 HDT_RST# For HDT DBG R266 390R2J-1-GP 1 2 R283 169R2F-GP 2 2SC3900P50V2KX-2GP SC3900P50V2KX-2GP 1 C6601 C657 LDT_RST#_CPU CPU_CLK CPU_CLK# TP97 TP220 TP221 AF4 AF5 AE6 SIC SID ALERT_L R6 P6 HT_REF0 HT_REF1 41 CPU_VDD0_RUN_FB_H 41 CPU_VDD0_RUN_FB_L F6 E6 41 CPU_VDD1_RUN_FB_H 41 CPU_VDD1_RUN_FB_L 1 300R2J-4-GP 2 300R2J-4-GP 2 R61 1 2 1 R64 300R2J-4-GP R66 41 CPU_PWRGD_SVID_REG THERMTRIP_L PROCHOT_L MEMHOT_L AF6 AC7 AA8 Y6 AB6 VDD1_FB_H VDD1_FB_L VDDNB_FB_H VDDNB_FB_L H6 G6 G10 AA9 AC9 AD9 AF9 DBRDY TMS TCK TRST_L TDI CPU_TEST23 AD7 TEST23 CPU_TEST18 H10 G9 TEST18 TEST19 CPU_TEST25_H CPU_TEST25_L E9 E8 TEST25_H TEST25_L CPU_TEST21 CPU_TEST20 CPU_TEST24 CPU_TEST22 CPU_TEST12 CPU_TEST27 AB8 AF7 AE7 AE8 AC8 AF8 TEST21 TEST20 TEST24 TEST22 TEST12 TEST27 CPU_TEST9 C2 AA6 TEST9 TEST6 LDT_PWROK RSVD1 RSVD2 RSVD3 RSVD4 RSVD5 DBREQ_L TDO 41 41 CPU_DBREQ# THERMTRIP# PROCHOT#_SB 11 CPU_MEMHOT# H_THERMDC 33 H_THERMDA 33 1DY 2 C116 SC100P50V2JN-3GP CPU_VDDIO_SUS_FB_H 1 TP116 CPU_VDDIO_SUS_FB_L TP113 1 CPU_VDDNB_RUN_FB_H CPU_VDDNB_RUN_FB_L C LAYOUT: Route FBCLKOUT_H/L differentially impedance 80 41 41 E10 CPU_DBREQ# AE9 CPU_TDO TEST28_H TEST28_L J7 H8 TEST17 TEST16 TEST15 TEST14 D7 E7 F7 C7 TEST7 TEST10 C3 K8 TEST8 C4 TEST29_H TEST29_L C9 C8 RSVD10 RSVD9 RSVD8 RSVD7 RSVD6 CPU_SVC CPU_SVD internal pull high 300 ohm W9 Y9 1 R54 2 0R0402-PAD 8 7 6 5 A6 A4 VDDIO_FB_H VDDIO_FB_L A3 A5 B3 B5 C1 1 2 R308 0R2J-2-GP SVC SVD VDD0_FB_H VDD0_FB_L 1 1 1 RN17 SRN300J-1-GP M11 W18 W7 W8 1 TP112 TP110 TP108 RN54 SRN1KJ-7-GP KEY1 KEY2 THERMDC THERMDA CPU_DBRDY CPU_TMS CPU_TCK CPU_TRST# CPU_TDI 1 2 300R2J-4-GP 2 1 300R2J-4-GP 2 1 300R2J-4-GP B R74 1 CPU_SIC 1 CPU_SID 1CPU_ALERT# CPU_HTREF0 2 2 44D2R2F-GP CPU_HTREF1 44D2R2F-GP TP118 R57 CLKIN_H CLKIN_L RESET_L PWROK LDTSTOP_L LDTREQ_L 1 R2471 R248 2 R277 A9 A8 LDT_PWROK LDT_STP#_CPU CPU_LDT_REQ#_CPU 1D2V_S0 CPU_SIC C VDDA1 VDDA2 B7 A7 F10 C6 1 2 R273 0R0402-PAD 1D8V_S3 CLKCPU_IN CLKCPU#_IN ACPU1D F8 F9 1 2 3 4 Cloce To CPU 1D8V_S3 1D8V_S0 3 4 2 2 1 2 2 SA_20081127 C665 2 1 -1 090213 C669 SCD22U6D3V2KX-1GP 9,11 ALLOW_LDTSTOP C666 SC10U10V5ZY-1GP 11 CPU_LDT_STOP# C667 SC3300P50V2KX-1GP 11,58 CPU_PWRGD 1 R301 2 0R0603-PAD 2 LDT_RST#_CPU 9,58 33R2J-2-GP LDT_PWROK 2 0R0402-PAD 2 LDT_STP#_CPU 9 0R0402-PAD CPU_LDT_REQ#_CPU 2 0R0402-PAD SC4D7U6D3V3KX-GP 1 R242 1 R243 1 R244 1 R241 11 CPU_LDT_RST# 1 D 1 2 3 4 D LYAOUT:ROUTE VDDA TRACE APPROX. 50mils WIDE(USE 2X25 mil TRACES TO EXIT BALL FIELD) AND 500 mils LONG. IF 0 ohm IS NOT GOOD ENOUGH, TRY 68.00082.491 CPU_TEST17 1 TP106 CPU_TEST14 1 TP107 CPU_TEST29H CPU_TEST29L 1 1 TP114 TP109 B H18 H19 AA7 D5 C5 HDT Connectors SKT-CPU638P-GP-U2 62.10055.111 HDT1 2ND = 62.10040.471 20081126 1 CPU_DBREQ# CPU_DBRDY CPU_TCK CPU_TMS CPU_TDI CPU_TRST# CPU_TDO 1 LDT_PWROK R275 2K2R2J-2-GP 1D8V_S3 2 C640 1 2 1D8V_SUS_Q2 SCD1U16V2ZY-2GP Q20 E C MMBT3904-4-GP 3 5 7 9 11 13 15 17 19 21 23 THERMTRIP# CPU exceeds to 125℃ 4 6 8 10 12 14 16 18 20 22 24 26 SMC-CONN26A-FP HDT_RST# B A 2 DY RSMRST# 33,34,39 SJV50 SA_20081030 A Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. 84.T3904.C11 2ND = 84.03904.L06 Title Size Document Number CPU (3 of 4) SJV50-PU Date: Wednesday, February 25, 2009 5 4 3 2 Sheet 1 Rev -1 6 of 59 4 VCC_CORE_S0_1 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 2 1 SC4D7U6D3V3KX-GP SC4D7U6D3V3KX-GP 1 SC4D7U6D3V3KX-GP 1 SCD22U6D3V2KX-1GP 1 SCD22U6D3V2KX-1GP B 2 2 2 2ND = 62.10040.471 SC10U6D3V5KX-1GP SC10U6D3V5KX-1GP SC180P50V2JN-1GP Wistron Corporation SKT-CPU638P-GP-U2 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. 62.10055.111 A Title CPU (4 of 4) Size Document Number Rev -1 SJV50-PU Date: Wednesday, February 25, 2009 5 C C300 C302 2 1 1 2 1 2 1 2 1 2 1 2 1 2 1 1 2 2 2 1 2 to the CPU EC44 SC10U6D3V5MX-3GP SC10U6D3V5MX-3GP 62.10055.111 C199 C268 C297 C258 C301 SCD22U6D3V2KX-1GP SKT-CPU638P-GP-U2 C306 C305 SC10U6D3V5MX-3GP C228 C202 SCD01U50V2KX-1GP VDDIO1 VDDIO2 VDDIO3 VDDIO4 VDDIO5 VDDIO6 VDDIO7 VDDIO8 VDDIO9 VDDIO10 VDDIO11 VDDIO12 Y25 V25 V23 V21 V18 U17 T25 T23 T21 T18 R17 P25 P23 P21 P18 2A for VDDIO 1D8V_S3 Place near to CPU SC180P50V2JN-1GP 200812021D8V_S3 H25 J17 K18 K21 K23 K25 L17 M18 M21 M23 M25 N17 VDDIO27 VDDIO26 VDDIO25 VDDIO24 VDDIO23 VDDIO22 VDDIO21 VDDIO20 VDDIO19 VDDIO18 VDDIO17 VDDIO16 VDDIO15 VDDIO14 VDDIO13 D C148 C114 C167 C121 C166 C642 C643 SC10U6D3V5MX-3GP C189 VDDNB_1 VDDNB_2 VDDNB_3 VDDNB_4 VDDNB_5 P8 P10 R4 R7 R9 R11 T2 T6 T8 T10 T12 T14 U7 U9 U11 U13 U15 V6 V8 V10 V12 V14 W4 Y2 AC4 AD2 SCD22U6D3V2KX-1GP SC180P50V2JN-1GP C188 SC10U6D3V5KX-1GP SC10U6D3V5KX-1GP SC10U6D3V5KX-1GP C726 K16 M16 P16 T16 V16 VDD1_1 VDD1_2 VDD1_3 VDD1_4 VDD1_5 VDD1_6 VDD1_7 VDD1_8 VDD1_9 VDD1_10 VDD1_11 VDD1_12 VDD1_13 VDD1_14 VDD1_15 VDD1_16 VDD1_17 VDD1_18 VDD1_19 VDD1_20 VDD1_21 VDD1_22 VDD1_23 VDD1_24 VDD1_25 VDD1_26 SCD01U50V2KX-1GP SCD01U50V2KX-1GP 4A for VDDNB VDD0_1 VDD0_2 VDD0_3 VDD0_4 VDD0_5 VDD0_6 VDD0_7 VDD0_8 VDD0_9 VDD0_10 VDD0_11 VDD0_12 VDD0_13 VDD0_14 VDD0_15 VDD0_16 VDD0_17 VDD0_18 VDD0_19 VDD0_20 VDD0_21 VDD0_22 VDD0_23 SC180P50V2JN-1GP SCD22U6D3V2KX-1GP VDDNB SC10U6D3V5MX-3GP SC10U6D3V5MX-3GP SC10U6D3V5MX-3GP SC47P50V2JN-3GP 1 2 1 C474 C393 C110 C118 C162 C183 C145 C165 C120 G4 H2 J9 J11 J13 J15 K6 K10 K12 K14 L4 L7 L9 L11 L13 L15 M2 M6 M8 M10 N7 N9 N11 2 -1 090219 SC10U6D3V5MX-3GP A 1 ACPU1E SC10P50V2JN-4GP B J6 J8 J10 J12 J14 J16 J18 K2 K7 K9 K11 K13 K15 K17 L6 L8 L10 L12 L14 L16 L18 M7 M9 AC6 M17 N4 N8 N10 N16 N18 P2 P7 P9 P11 P17 R8 R10 R16 R18 T7 T9 T11 T13 T15 T17 U4 U6 U8 U10 U12 U14 U16 U18 V2 V7 V9 V11 V13 V15 V17 W6 Y21 Y23 N6 SC10P50V2JN-4GP C VSS66 VSS67 VSS68 VSS69 VSS70 VSS71 VSS72 VSS73 VSS74 VSS75 VSS76 VSS77 VSS78 VSS79 VSS80 VSS81 VSS82 VSS83 VSS84 VSS85 VSS86 VSS87 VSS88 VSS89 VSS90 VSS91 VSS92 VSS93 VSS94 VSS95 VSS96 VSS97 VSS98 VSS99 VSS100 VSS101 VSS102 VSS103 VSS104 VSS105 VSS106 VSS107 VSS108 VSS109 VSS110 VSS111 VSS112 VSS113 VSS114 VSS115 VSS116 VSS117 VSS118 VSS119 VSS120 VSS121 VSS122 VSS123 VSS124 VSS125 VSS126 VSS127 VSS128 VSS129 EC47 near SC47P50V2JN-3GP 1 2 D VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59 VSS60 VSS61 VSS62 VSS63 VSS64 VSS65 2 36A for VDD0&VDD1 VCC_CORE_S0_0 ACPU1F AA4 AA11 AA13 AA15 AA17 AA19 AB2 AB7 AB9 AB23 AB25 AC11 AC13 AC15 AC17 AC19 AC21 AD6 AD8 AD25 AE11 AE13 AE15 AE17 AE19 AE21 AE23 B4 B6 B8 B9 B11 B13 B15 B17 B19 B21 B23 B25 D6 D8 D9 D11 D13 D15 D17 D19 D21 D23 D25 E4 F2 F11 F13 F15 F17 F19 F21 F23 F25 H7 H9 H21 H23 J4 3 1 5 4 3 2 Sheet 7 of 1 59 5 4 3 2 1 ANB1A C HT_TXCAD0P HT_TXCAD0N HT_TXCAD1P HT_TXCAD1N HT_TXCAD2P HT_TXCAD2N HT_TXCAD3P HT_TXCAD3N HT_TXCAD4P HT_TXCAD4N HT_TXCAD5P HT_TXCAD5N HT_TXCAD6P HT_TXCAD6N HT_TXCAD7P HT_TXCAD7N D24 D25 E24 E25 F24 F25 F23 F22 H23 H22 J25 J24 K24 K25 K23 K22 HT_NB_CPU_CAD_H0 HT_NB_CPU_CAD_L0 HT_NB_CPU_CAD_H1 HT_NB_CPU_CAD_L1 HT_NB_CPU_CAD_H2 HT_NB_CPU_CAD_L2 HT_NB_CPU_CAD_H3 HT_NB_CPU_CAD_L3 HT_NB_CPU_CAD_H4 HT_NB_CPU_CAD_L4 HT_NB_CPU_CAD_H5 HT_NB_CPU_CAD_L5 HT_NB_CPU_CAD_H6 HT_NB_CPU_CAD_L6 HT_NB_CPU_CAD_H7 HT_NB_CPU_CAD_L7 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 HT_TXCAD8P HT_TXCAD8N HT_TXCAD9P HT_TXCAD9N HT_TXCAD10P HT_TXCAD10N HT_TXCAD11P HT_TXCAD11N HT_TXCAD12P HT_TXCAD12N HT_TXCAD13P HT_TXCAD13N HT_TXCAD14P HT_TXCAD14N HT_TXCAD15P HT_TXCAD15N F21 G21 G20 H21 J20 J21 J18 K17 L19 J19 M19 L18 M21 P21 P18 M18 HT_NB_CPU_CAD_H8 HT_NB_CPU_CAD_L8 HT_NB_CPU_CAD_H9 HT_NB_CPU_CAD_L9 HT_NB_CPU_CAD_H10 HT_NB_CPU_CAD_L10 HT_NB_CPU_CAD_H11 HT_NB_CPU_CAD_L11 HT_NB_CPU_CAD_H12 HT_NB_CPU_CAD_L12 HT_NB_CPU_CAD_H13 HT_NB_CPU_CAD_L13 HT_NB_CPU_CAD_H14 HT_NB_CPU_CAD_L14 HT_NB_CPU_CAD_H15 HT_NB_CPU_CAD_L15 4 4 4 4 HT_TXCLK0P HT_TXCLK0N HT_TXCLK1P HT_TXCLK1N H24 H25 L21 L20 HT_NB_CPU_CLK_H0 4 HT_NB_CPU_CLK_L0 4 HT_NB_CPU_CLK_H1 4 HT_NB_CPU_CLK_L1 4 HT_RXCTL0P HT_RXCTL0N HT_RXCTL1P HT_RXCTL1N HT_TXCTL0P HT_TXCTL0N HT_TXCTL1P HT_TXCTL1N M24 M25 P19 R18 HT_NB_CPU_CTL_H0 4 HT_NB_CPU_CTL_L0 4 HT_NB_CPU_CTL_H1 4 HT_NB_CPU_CTL_L1 4 HT_RXCALP HT_RXCALN HT_TXCALP HT_TXCALN B24 B25 GFX_TX0P GFX_TX0N GFX_TX1P GFX_TX1N GFX_TX2P GFX_TX2N GFX_TX3P GFX_TX3N GFX_TX4P GFX_TX4N GFX_TX5P GFX_TX5N GFX_TX6P GFX_TX6N GFX_TX7P GFX_TX7N GFX_TX8P GFX_TX8N GFX_TX9P GFX_TX9N GFX_TX10P GFX_TX10N GFX_TX11P GFX_TX11N GFX_TX12P GFX_TX12N GFX_TX13P GFX_TX13N GFX_TX14P GFX_TX14N GFX_TX15P GFX_TX15N A5 B5 A4 B4 C3 B2 D1 D2 E2 E1 F4 F3 F1 F2 H4 H3 H1 H2 J2 J1 K4 K3 K1 K2 M4 M3 M1 M2 N2 N1 P1 P2 GPP_TX0P GPP_TX0N GPP_TX1P GPP_TX1N GPP_TX2P GPP_TX2N GPP_TX3P GPP_TX3N GPP_TX4P GPP_TX4N GPP_TX5P GPP_TX5N AC1 AC2 AB4 AB3 AA2 AA1 Y1 Y2 Y4 Y3 V1 V2 SB_TX0P SB_TX0N SB_TX1P SB_TX1N SB_TX2P SB_TX2N SB_TX3P SB_TX3N AD7 AE7 AE6 AD6 AB6 AC6 AD5 AE5 PCE_CALRP PCE_CALRN AC8 AB8 HT_CPU_NB_CAD_H0 HT_CPU_NB_CAD_L0 HT_CPU_NB_CAD_H1 HT_CPU_NB_CAD_L1 HT_CPU_NB_CAD_H2 HT_CPU_NB_CAD_L2 HT_CPU_NB_CAD_H3 HT_CPU_NB_CAD_L3 HT_CPU_NB_CAD_H4 HT_CPU_NB_CAD_L4 HT_CPU_NB_CAD_H5 HT_CPU_NB_CAD_L5 HT_CPU_NB_CAD_H6 HT_CPU_NB_CAD_L6 HT_CPU_NB_CAD_H7 HT_CPU_NB_CAD_L7 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 HT_CPU_NB_CAD_H8 HT_CPU_NB_CAD_L8 HT_CPU_NB_CAD_H9 HT_CPU_NB_CAD_L9 HT_CPU_NB_CAD_H10 HT_CPU_NB_CAD_L10 HT_CPU_NB_CAD_H11 HT_CPU_NB_CAD_L11 HT_CPU_NB_CAD_H12 HT_CPU_NB_CAD_L12 HT_CPU_NB_CAD_H13 HT_CPU_NB_CAD_L13 HT_CPU_NB_CAD_H14 HT_CPU_NB_CAD_L14 HT_CPU_NB_CAD_H15 HT_CPU_NB_CAD_L15 AC24 AC25 AB25 AB24 AA24 AA25 Y22 Y23 W21 W20 V21 V20 U20 U21 U19 U18 HT_RXCAD8P HT_RXCAD8N HT_RXCAD9P HT_RXCAD9N HT_RXCAD10P HT_RXCAD10N HT_RXCAD11P HT_RXCAD11N HT_RXCAD12P HT_RXCAD12N HT_RXCAD13P HT_RXCAD13N HT_RXCAD14P HT_RXCAD14N HT_RXCAD15P HT_RXCAD15N 4 4 4 4 HT_CPU_NB_CLK_H0 HT_CPU_NB_CLK_L0 HT_CPU_NB_CLK_H1 HT_CPU_NB_CLK_L1 T22 T23 AB23 AA22 HT_RXCLK0P HT_RXCLK0N HT_RXCLK1P HT_RXCLK1N 4 4 4 4 HT_CPU_NB_CTL_H0 HT_CPU_NB_CTL_L0 HT_CPU_NB_CTL_H1 HT_CPU_NB_CTL_L1 M22 M23 R21 R20 C23 A24 2 R236 301R2F-GP 1 HT_RXCALP HT_RXCALN Place < 100mils from pin C23 and A24 HT_RXCAD0P HT_RXCAD0N HT_RXCAD1P HT_RXCAD1N HT_RXCAD2P HT_RXCAD2N HT_RXCAD3P HT_RXCAD3N HT_RXCAD4P HT_RXCAD4N HT_RXCAD5P HT_RXCAD5N HT_RXCAD6P HT_RXCAD6N HT_RXCAD7P HT_RXCAD7N PART 1 OF 6 HYPER TRANSPORT CPU I/F D Y25 Y24 V22 V23 V25 V24 U24 U25 T25 T24 P22 P23 P25 P24 N24 N25 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 HT_TXCALP HT_TXCALN D 4 4 4 4 4 4 4 4 4 4 4 4 GTXP0 GTXN0 GTXP1 GTXN1 GTXP2 GTXN2 GTXP3 GTXN3 C645 C646 C647 C648 C649 C650 C651 C652 1 2 HDMI_SL 1 2 HDMI_SL 1 2 HDMI_SL 1 2 HDMI_SL 1 2 HDMI_SL 1 2 HDMI_SL 1 2 HDMI_SL 1 2 HDMI_SL SCD1U10V2KX-4GP SCD1U10V2KX-4GP SCD1U10V2KX-4GP SCD1U10V2KX-4GP SCD1U10V2KX-4GP SCD1U10V2KX-4GP SCD1U10V2KX-4GP SCD1U10V2KX-4GP TMDS_A_TX2+ TMDS_A_TX2TMDS_A_TX1+ TMDS_A_TX1TMDS_A_TX0+ TMDS_A_TX0TMDS_A_TXC+ TMDS_A_TXC- 20,51 20,51 20,51 20,51 20,51 20,51 20,51 20,51 RS780M Display Port Support(muxed on GFX) DP0 GFX_TX0,TX1,TX2,TX3,AUX0,HPD0 DP1 GFX_TX4,TX5,TX6,TX7,AUX1,HPD1 C 2 R235 301R2F-GP 1 Place < 100mils from pin B25 and B24 RS780M-GP-U2 Placement: close RS780 ANB1B 50 PEG_RXP[15..0] B 25 25 32 32 32 32 LAN MINICARD1 MINICARD2 TP44 TP36 A A-LINK 11 11 11 11 11 11 11 11 PEG_RXP0 PEG_RXN0 PEG_RXP1 PEG_RXN1 PEG_RXP2 PEG_RXN2 PEG_RXP3 PEG_RXN3 PEG_RXP4 PEG_RXN4 PEG_RXP5 PEG_RXN5 PEG_RXP6 PEG_RXN6 PEG_RXP7 PEG_RXN7 PEG_RXP8 PEG_RXN8 PEG_RXP9 PEG_RXN9 PEG_RXP10 PEG_RXN10 PEG_RXP11 PEG_RXN11 PEG_RXP12 PEG_RXN12 PEG_RXP13 PEG_RXN13 PEG_RXP14 PEG_RXN14 PEG_RXP15 PEG_RXN15 D4 C4 A3 B3 C2 C1 E5 F5 G5 G6 H5 H6 J6 J5 J7 J8 L5 L6 M8 L8 P7 M7 P5 M5 R8 P8 R6 R5 P4 P3 T4 T3 GFX_RX0P GFX_RX0N GFX_RX1P GFX_RX1N GFX_RX2P GFX_RX2N GFX_RX3P GFX_RX3N GFX_RX4P GFX_RX4N GFX_RX5P GFX_RX5N GFX_RX6P GFX_RX6N GFX_RX7P GFX_RX7N GFX_RX8P GFX_RX8N GFX_RX9P GFX_RX9N GFX_RX10P GFX_RX10N GFX_RX11P GFX_RX11N GFX_RX12P GFX_RX12N GFX_RX13P GFX_RX13N GFX_RX14P GFX_RX14N GFX_RX15P GFX_RX15N GPP_RX5P GPP_RX5N AE3 AD4 AE2 AD3 AD1 AD2 V5 W6 U5 U6 U8 U7 GPP_RX0P GPP_RX0N GPP_RX1P GPP_RX1N GPP_RX2P GPP_RX2N GPP_RX3P GPP_RX3N GPP_RX4P GPP_RX4N GPP_RX5P GPP_RX5N AA8 Y8 AA7 Y7 AA5 AA6 W5 Y5 SB_RX0P SB_RX0N SB_RX1P SB_RX1N SB_RX2P SB_RX2N SB_RX3P SB_RX3N PCIE_RXP1 PCIE_RXN1 PCIE_RXP2 PCIE_RXN2 PCIE_RXP3 PCIE_RXN3 1 1 ALINK_NBRX_SBTX_P0 ALINK_NBRX_SBTX_N0 ALINK_NBRX_SBTX_P1 ALINK_NBRX_SBTX_N1 ALINK_NBRX_SBTX_P2 ALINK_NBRX_SBTX_N2 ALINK_NBRX_SBTX_P3 ALINK_NBRX_SBTX_N3 PART 2 OF 6 PCIE I/F GFX 50 PEG_RXN[15..0] PCIE I/F GPP PCIE I/F SB GTXP0 GTXN0 GTXP1 GTXN1 GTXP2 GTXN2 GTXP3 GTXN3 GTXP4 GTXN4 GTXP5 GTXN5 GTXP6 GTXN6 GTXP7 GTXN7 GTXP8 GTXN8 GTXP9 GTXN9 GTXP10 GTXN10 GTXP11 GTXN11 GTXP12 GTXN12 GTXP13 GTXN13 GTXP14 GTXN14 GTXP15 GTXN15 1 DIS 1 DIS 1 DIS 1 DIS 1 DIS 1 DIS 1 DIS 1 DIS 1 DIS 1 DIS 1 DIS 1 DIS 1 DIS 1 DIS 1 DIS 1 DIS 1 DIS 1 DIS 1 DIS 1 DIS 1 DIS 1 DIS 1 DIS 1 DIS 1 DIS 1 DIS 1 DIS 1 DIS 1 DIS 1 DIS 1 DIS 1 DIS TXP1 TXN1 TXP2 TXN2 TXP3 TXN3 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 C630 C631 C632 C633 C634 C635 C636 C637 C521 C520 C505 C504 C519 C518 C503 C502 C517 C516 C501 C500 C515 C514 C499 C498 C513 C512 C497 C496 C510 C511 C495 C494 C525 C524 C527 C526 C522 C523 1 1 1 1 1 1 SCD1U10V2KX-4GP SCD1U10V2KX-4GP SCD1U10V2KX-4GP SCD1U10V2KX-4GP SCD1U10V2KX-4GP SCD1U10V2KX-4GP SCD1U10V2KX-4GP SCD1U10V2KX-4GP SCD1U10V2KX-4GP SCD1U10V2KX-4GP SCD1U10V2KX-4GP SCD1U10V2KX-4GP SCD1U10V2KX-4GP SCD1U10V2KX-4GP SCD1U10V2KX-4GP SCD1U10V2KX-4GP SCD1U10V2KX-4GP SCD1U10V2KX-4GP SCD1U10V2KX-4GP SCD1U10V2KX-4GP SCD1U10V2KX-4GP SCD1U10V2KX-4GP SCD1U10V2KX-4GP SCD1U10V2KX-4GP SCD1U10V2KX-4GP SCD1U10V2KX-4GP SCD1U10V2KX-4GP SCD1U10V2KX-4GP SCD1U10V2KX-4GP SCD1U10V2KX-4GP SCD1U10V2KX-4GP SCD1U10V2KX-4GP 2 2 2 2 2 2 1 1 PCE_PCAL PCE_NCAL C557 C551 C548 C549 C538 C545 C536 C537 1 R207 1 R25 1 1 1 1 1 1 1 1 PEG_TXP[15..0] 50 PEG_TXN[15..0] 50 B SCD1U10V2KX-4GP SCD1U10V2KX-4GP SCD1U10V2KX-4GP SCD1U10V2KX-4GP SCD1U10V2KX-4GP SCD1U10V2KX-4GP GPP_TX5P GPP_TX5N ALINK_NBTX_SBRX_P0 ALINK_NBTX_SBRX_N0 ALINK_NBTX_SBRX_P1 ALINK_NBTX_SBRX_N1 ALINK_NBTX_SBRX_P2 ALINK_NBTX_SBRX_N2 ALINK_NBTX_SBRX_P3 ALINK_NBTX_SBRX_N3 PEG_TXP0 PEG_TXN0 PEG_TXP1 PEG_TXN1 PEG_TXP2 PEG_TXN2 PEG_TXP3 PEG_TXN3 PEG_TXP4 PEG_TXN4 PEG_TXP5 PEG_TXN5 PEG_TXP6 PEG_TXN6 PEG_TXP7 PEG_TXN7 PEG_TXP8 PEG_TXN8 PEG_TXP9 PEG_TXN9 PEG_TXP10 PEG_TXN10 PEG_TXP11 PEG_TXN11 PEG_TXP12 PEG_TXN12 PEG_TXP13 PEG_TXN13 PEG_TXP14 PEG_TXN14 PEG_TXP15 PEG_TXN15 2 2 2 2 2 2 2 2 PCIE_TXP1 PCIE_TXN1 PCIE_TXP2 PCIE_TXN2 PCIE_TXP3 PCIE_TXN3 25 25 32 32 32 32 LAN MINICARD1 MINICARD2 TP28 TP29 SCD1U10V2KX-4GP SCD1U10V2KX-4GP SCD1U10V2KX-4GP SCD1U10V2KX-4GP SCD1U10V2KX-4GP SCD1U10V2KX-4GP SCD1U10V2KX-4GP SCD1U10V2KX-4GP 2 2 1K27R2F-L-GP 2KR2F-3-GP ALINK_NBTX_C_SBRX_P0 ALINK_NBTX_C_SBRX_N0 ALINK_NBTX_C_SBRX_P1 ALINK_NBTX_C_SBRX_N1 ALINK_NBTX_C_SBRX_P2 ALINK_NBTX_C_SBRX_N2 ALINK_NBTX_C_SBRX_P3 ALINK_NBTX_C_SBRX_N3 11 11 11 11 11 11 11 11 A Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title RS780 (1 of 3) 1D1V_S0 Size RS780M-GP-U2 Place < 100mils from pin AC8 and AB8 Document Number Rev 5 4 3 -1 SJV50-PU Date: Wednesday, February 25, 2009 2 Sheet 1 8 of 59 5 4 3 2 3D3V_S0 STRAP_DEBUG_BUS_GPIO_ENABLEb C38 SC1U10V2KX-1GP 8 7 6 5 220ohm 200mA 1 1 SYSREST# 3D3V_S0_AVDD C49 SCD1U10V2KX-4GP RN49 SRN3K3J-1-GP 2 PLT_RST1# 2 0R2J-2-GP 2 0R0402-PAD 1 11 3D3V_S0 L7 1 2 FCM1608CF-221T02-GP DY 1 R14 1 R11 2 6,58 LDT_RST#_CPU 1 * Enables the Test Debug Bus using GPIO.(PIN: RS780M--> VSYNC#) 1 :Disable 0 : Enable RS780: Enables Side port memory ( RS780 use HSYNC#) *1 1 2 3 4 2 C12 SC330P50V2KX-3GP 1D8V_S0 :Disable 0 : Enable GMCH_HSYNC 1D8V_S0 L12 1 2 FCM1608CF-221T02-GP RED REDb GREEN GREENb BLUE BLUEb 19 GMCH_GREEN 19 GMCH_BLUE A11 B11 F8 E8 DAC_HSYNC DAC_VSYNC DAC_SCL DAC_SDA G14 DAC_RSET A12 D14 B12 PLLVDD PLLVDD18 PLLVSS VDDA18HTPLL H17 VDDA18HTPLL VDDA18PCIEPLL D7 E7 VDDA18PCIEPLL1 VDDA18PCIEPLL2 D8 A10 C10 C12 SYSRESET# POWERGOOD LDTSTOP# ALLOW_LDTSTOP 3 CLK_NBHT_CLK 3 CLK_NBHT_CLK# C25 C24 HT_REFCLKP HT_REFCLKN CLK_NB_14M E11 F11 REFCLK_P/OSCIN REFCLK_N R41 1 140R2F-GP 2 R43 1 150R2F-1-GP 2 R42 1 150R2F-1-GP 2 Close to NB ball 19 GMCH_HSYNC 19 GMCH_VSYNC 19 NB_CRT_CLK 19 NB_CRT_DAT C 1D1V_S0 1 R34 2DAC_RSET 715R2F-GP L2 1 2 FCM1608CF-221T02-GP C553 SC1U10V2KX-1GP 1D8V_S0 1 1D8V_S0_PLVDD18 C554 SCD1U10V2KX-4GP 2 220ohm 200mA 2 1 1D1V_S0_PLLVDD L13 1 2R3J-GP C63 SC22U6D3V5MX-2GP SCD1U10V2KX-4GP C78 12,39 NB_PWRGD 1D1V_S0 RN2 ENABLE External CLK GEN 1 2 3 4 3 NB_LDT_STOP# NB_ALLOW_LDTSTOP SRN1KJ-7-GP 1 C85 SCD1U10V2KX-4GP 1D8V_S0 U1 U2 GPP_REFCLKP GPP_REFCLKN V4 V3 GPPSB_REFCLKP GPPSB_REFCLKN NB_DVI_CLK NB_DVI_DATA B9 A9 B8 A8 B7 A7 I2C_CLK I2C_DATA DDC_CLK0/AUX0P DDC_DATA0/AUX0N DDC_DATA0/AUX0N DDC_CLK0/AUX0P DDC_CLK1/AUX1P DDC_DATA1/AUX1N STRP_DATA B10 1CLK_NBGPP_CLK 1CLK_NBGPP_CLK# C17 SCD1U10V2KX-4GP TP38 TP39 1 1 GPIO MODE G11 2 1 STRP_DATA 0 VCC_NB 1.0V 1.1V *1 1 RS780_AUX_CAL 2 GMCH_TXBOUT0+ GMCH_TXBOUT0GMCH_TXBOUT1+ GMCH_TXBOUT1GMCH_TXBOUT2+ GMCH_TXBOUT2- 18 18 18 18 18 18 TXCLK_LP TXCLK_LN TXCLK_UP TXCLK_UN B16 A16 D16 D17 VDDLTP18 VSSLTP18 A13 B13 VDDLT18_1 VDDLT18_2 VDDLT33_1 VDDLT33_2 A15 B15 A14 B14 VSSLT1 VSSLT2 VSSLT3 VSSLT4 VSSLT5 VSSLT6 VSSLT7 C14 D15 C16 C18 C20 E20 C22 LVDS_DIGON LVDS_BLON LVDS_ENA_BL GMCH_TXACLK+ GMCH_TXACLKGMCH_TXBCLK+ GMCH_TXBCLK- 18 18 18 18 L8 1 2 FCM1608CF-221T02-GP C42 SCD1U10V2KX-4GP 1D8V_S0_VDDLP18 C560 SC1U10V2KX-1GP 1D8V_S0_VDDLT18 C567 SC4D7U6D3V3KX-GP E9 GMCH_BL_ON F7 G12 LVDS_ENA_BL C 1D8V_S0 L10 1 2 PBY201209T-221Y-N-GP C571 SCD1U10V2KX-4GP 1 RN1 2 1 GMCH_LCDVDD_ON GMCH_BL_ON 34 18 TP52 3 4 B SRN4K7J-8-GP R27 MIS. TMDS_HPD HPD D9 D10 NB_DVI_HPD 1 SUS_STAT# D12 SUS_STAT# 2 THERMALDIODE_P THERMALDIODE_N STRP_DATA RESERVED TESTMODE AE8 AD8 1 DY 2 100KR2J-1-GP HDMI_NB_HPD TP48 1 R29 10KR2J-3-GP 20 3D3V_S0 D13 TESTMODE_NB C8 R192 150R2F-1-GP AUX_CAL R31 1K8R2F-GP RS780M-GP-U2 2 2 C18 SC1U10V2KX-1GP 1 L1 220ohm 200mA GFX_REFCLKP GFX_REFCLKN 3 CLK_NB_GPPSB 3 CLK_NB_GPPSB# 18 NB_LCD_CLK 18 NB_LCD_DAT 20 HDMI_NB_DAT 20 HDMI_NB_CLK 1 2 VDDA18PCIEPLL FCM1608CF-221T02-GP T2 T1 B18 A18 A17 B17 D20 D21 D18 D19 1 C62 SC1U10V2KX-1GP TP215 TP216 2 220ohm 200mA NB_REFCLK_N 3 CLK_NB_GFX 3 CLK_NB_GFX# VDDA18HTPLL 1 1D8V_S0 L15 1 2 FCM1608CF-221T02-GP 2 B SYSREST# 2 63.2R003.15L 1 2 2 2 C97 SC22U6D3V5MX-2GP 1 1 TXOUT_U0P TXOUT_U0N TXOUT_U1P TXOUT_U1N TXOUT_U2P TXOUT_U2N TXOUT_U3P TXOUT_U3N 1 G18 G17 E18 F18 E19 F19 18 18 18 18 18 18 1 GMCH_RED GMCH_TXAOUT0+ GMCH_TXAOUT0GMCH_TXAOUT1+ GMCH_TXAOUT1GMCH_TXAOUT2+ GMCH_TXAOUT2- 2 19 A22 B22 A21 B21 B20 A20 A19 B19 1 C_Pr Y COMP_Pb TXOUT_L0P TXOUT_L0N TXOUT_L1P TXOUT_L1N TXOUT_L2P TXOUT_L2N TXOUT_L3P TXOUT_L3N 2 E17 F17 F15 1D8V_S0_AVDDQ PART 3 OF 6 2 AVDD1 AVDD2 AVDDDI AVSSDI AVDDQ AVSSQ 1 F12 E12 F14 G15 H15 H14 2 1 C46 SCD1U10V2KX-4GP 2 C68 SC1U10V2KX-1GP 2 1 ANB1C 220ohm 200mA CRT/TVOUT 2 NB_ALLOW_LDTSTOP 0R0402-PAD SUS_STAT# Selects Loading of STRAPS From EEPROM the loading of EEPROM straps and use Hardware Default Values *10 :: Bypass I2C Master can load strap values from EEPROM if connected, or use default values if not connected PLL PWR LVTM 1 R24 D GMCH_VSYNC C91 SCD1U10V2KX-4GP CLOCKs PM 6,11 ALLOW_LDTSTOP C86 SC1U10V2KX-1GP 1 NB_LDT_STOP# 2 0R0402-PAD 1 6 LDT_STP#_CPU 1 R19 2 D 1D8V_S0_AVDDDI 2 R47 2 1 0R0603-PAD 3D3V_S0 20090106_SB modify 1 1 1D8V_S0 TC12 ST100U6D3VBM-5GP R201 2K2R2J-2-GP 77.C1071.081 DY 1 R459 DY 2 2 A STRP_DATA 2 UMA 34,51 BLON_IN 1 R458 51 BRIGHTNESS_AMD 1 R460 2 A LVDS_ENA_BL 0R2J-2-GP Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. GMCH_BL_ON 0R2J-2-GP Title DY 2 RS780 (2 of 3) 0R2J-2-GP Size Rev -1 SJV50-PU Near NB 5 Document Number Date: Wednesday, February 25, 2009 4 3 2 Sheet 1 9 of 59 5 4 3 2 1 ANB1F AE12 AD12 SBD_MEM/DVO_I/F MEM_CKP MEM_CKN Y17 W18 AD20 AE21 MEM_DM0 MEM_DM1/DVO_D8 W17 AE19 IOPLLVDD18 IOPLLVDD AE23 AE24 IOPLLVSS AD23 MEM_VREF AE18 MEM_COMPP MEM_COMPN 1 2 1 2 1 2 1 C67 2 1 1 2 1 2 1 2 1 2 2 1 2 1 1 2 1 2 C37 1 C36 1 R30 2 0R0603-PAD VSSAHT1 VSSAHT2 VSSAHT3 VSSAHT4 VSSAHT5 VSSAHT6 VSSAHT7 VSSAHT8 VSSAHT9 VSSAHT10 VSSAHT11 VSSAHT12 VSSAHT13 VSSAHT14 VSSAHT15 VSSAHT16 VSSAHT17 VSSAHT18 VSSAHT19 VSSAHT20 VSSAHT21 VSSAHT22 VSSAHT23 VSSAHT24 VSSAHT25 VSSAHT26 VSSAHT27 L12 M14 N13 P12 P15 R11 R14 T12 U14 U11 U15 V12 W11 W15 AC12 AA14 Y18 AB11 AB15 AB17 AB19 AE20 AB21 K11 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 PART 6/6 VSSAPCIE1 VSSAPCIE2 VSSAPCIE3 VSSAPCIE4 VSSAPCIE5 VSSAPCIE6 VSSAPCIE7 VSSAPCIE8 VSSAPCIE9 VSSAPCIE10 VSSAPCIE11 VSSAPCIE12 VSSAPCIE13 VSSAPCIE14 VSSAPCIE15 VSSAPCIE16 VSSAPCIE17 VSSAPCIE18 VSSAPCIE19 VSSAPCIE20 VSSAPCIE21 VSSAPCIE22 VSSAPCIE23 VSSAPCIE24 VSSAPCIE25 VSSAPCIE26 VSSAPCIE27 VSSAPCIE28 VSSAPCIE29 VSSAPCIE30 VSSAPCIE31 VSSAPCIE32 VSSAPCIE33 VSSAPCIE34 VSSAPCIE35 VSSAPCIE36 VSSAPCIE37 VSSAPCIE38 VSSAPCIE39 VSSAPCIE40 VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 A2 B1 D3 D5 E4 G1 G2 G4 H7 J4 R7 L1 L2 L4 L7 M6 N4 P6 R1 R2 R4 V7 U4 V8 V6 W1 W2 W4 W7 W8 Y6 AA4 AB5 AB1 AB7 AC3 AC4 AE1 AE4 AB2 D C AE14 D11 G8 E14 E15 J15 J12 K14 M11 L15 RS780M-GP-U2 C35 2 1 2 V15 W14 MEM_DQS0P/DVO_IDCKP MEM_DQS0N/DVO_IDCKN MEM_DQS1P MEM_DQS1N C27 1 R210 2 0R0603-PAD +3.3V_RUN_VDD33 1 POWER 1 2 1 1 2 2 1 2 1 1 2 2 1 2 1 MEM_RAS# MEM_CAS# MEM_WE# MEM_CS# MEM_CKE MEM_ODT C19 3D3V_S0 2 1 2 1 2 1 2 1 2 1 2 2 W12 Y12 AD18 AB13 AB18 V14 2 1 2 1 2 1 2 1 2 1 2 1 2 2 MEM_BA0 MEM_BA1 MEM_BA2 C28 SC10U6D3V5KX-1GP AD16 AE17 AD17 MEM_DQ0/DVO_VSYNC MEM_DQ1/DVO_HSYNC MEM_DQ2/DVO_DE MEM_DQ3/DVO_D0 MEM_DQ4 MEM_DQ5/DVO_D1 MEM_DQ6/DVO_D2 MEM_DQ7/DVO_D4 MEM_DQ8/DVO_D3 MEM_DQ9/DVO_D5 MEM_DQ10/DVO_D6 MEM_DQ11/DVO_D7 MEM_DQ12 MEM_DQ13/DVO_D9 MEM_DQ14/DVO_D10 MEM_DQ15/DVO_D11 C26 SC10U6D3V5KX-1GP A MEM_A0 MEM_A1 MEM_A2 MEM_A3 MEM_A4 MEM_A5 MEM_A6 MEM_A7 MEM_A8 MEM_A9 MEM_A10 MEM_A11 MEM_A12 MEM_A13 AA18 AA20 AA19 Y19 V17 AA17 AA15 Y15 AC20 AD19 AE22 AC18 AB20 AD22 AC22 AD21 C51 SCD1U10V2KX-4GP PAR 4 OF 6 AB12 AE16 V11 AE15 AA12 AB16 AB14 AD14 AD13 AD15 AC16 AE13 AC14 Y14 C39 VDD_MEM AE10 AA11 Y11 AD10 AB10 AC10 RS780M-GP-U2 ANB1D B 1D1V_S0 RS780M: 1V ~ 1.1V, check PWR team SCD1U10V2KX-4GP C568 SC1U10V2KX-1GP +NB_VCORE Per check list (Rev 0.02) SCD1U10V2KX-4GP VDD33_1 VDD33_2 C577 7A per ANT Rev1.1, Page3 K12 J14 U16 J11 K15 M12 L14 L11 M13 M15 N12 N14 P11 P13 P14 R12 R15 T11 T15 U12 T14 J16 H11 H12 C57 SC4D7U6D3V3KX-GP VDD18_1 VDD18_2 VDD18_MEM1 VDD18_MEM2 C56 SCD1U10V2KX-4GP F9 G9 AE11 AD11 +1.8V_RUN_VDD18_MEM VDD_MEM1 VDD_MEM2 VDD_MEM3 VDD_MEM4 VDD_MEM5 VDD_MEM6 C59 SC1U10V2KX-1GP C24 VDDA18PCIE_1 VDDA18PCIE_2 VDDA18PCIE_3 VDDA18PCIE_4 VDDA18PCIE_5 VDDA18PCIE_6 VDDA18PCIE_7 VDDA18PCIE_8 VDDA18PCIE_9 VDDA18PCIE_10 VDDA18PCIE_11 VDDA18PCIE_12 VDDA18PCIE_13 VDDA18PCIE_14 VDDA18PCIE_15 VDDC_1 VDDC_2 VDDC_3 VDDC_4 VDDC_5 VDDC_6 VDDC_7 VDDC_8 VDDC_9 VDDC_10 VDDC_11 VDDC_12 VDDC_13 VDDC_14 VDDC_15 VDDC_16 VDDC_17 VDDC_18 VDDC_19 VDDC_20 VDDC_21 VDDC_22 C58 SCD1U10V2KX-4GP 1 300mil Width A6 B6 C6 D6 E6 F6 G7 H8 J9 K9 M9 L9 P9 R9 T9 V9 U9 SC1U10V2KX-1GP J10 P10 K10 M10 L10 W9 H9 T10 R10 Y9 AA9 AB9 AD9 AE9 U10 VDDHTTX_1 VDDHTTX_2 VDDHTTX_3 VDDHTTX_4 VDDHTTX_5 VDDHTTX_6 VDDHTTX_7 VDDHTTX_8 VDDHTTX_9 VDDHTTX_10 VDDHTTX_11 VDDHTTX_12 VDDHTTX_13 VDDPCIE_1 VDDPCIE_2 VDDPCIE_3 VDDPCIE_4 VDDPCIE_5 VDDPCIE_6 VDDPCIE_7 VDDPCIE_8 VDDPCIE_9 VDDPCIE_10 VDDPCIE_11 VDDPCIE_12 VDDPCIE_13 VDDPCIE_14 VDDPCIE_15 VDDPCIE_16 VDDPCIE_17 SCD1U10V2KX-4GP SCD1U10V2KX-4GP SCD1U10V2KX-4GP 1 R214 2 0R0603-PAD VDDHTRX_1 VDDHTRX_2 VDDHTRX_3 VDDHTRX_4 VDDHTRX_5 VDDHTRX_6 VDDHTRX_7 PART 5/6 SCD1U10V2KX-4GP SCD1U10V2KX-4GP C61 +1.8V_RUN_VDDA18PCIE C29 C20 C25 SCD1U10V2KX-4GP C30 +1.2V_RUN_VDDHTTX C598 C79 SCD1U10V2KX-4GP C34 SC1U10V2KX-1GP C31 SCD1U10V2KX-4GP 1D8V_S0 SC4D7U6D3V3KX-GP 220 ohm @ 100MHz,2A 80mil Width SC4D7U6D3V3KX-GP 1 2 PBY201209T-221Y-N-GP SCD1U10V2KX-4GP C88 L3 C SCD1U10V2KX-4GP 1D8V_S0 SC4D7U6D3V3KX-GP 220 ohm @ 100MHz,2A C599 H18 G19 F20 E21 D22 B23 A23 AE25 AD24 AC23 AB22 AA21 Y20 W19 V18 U17 T17 R17 P17 M17 L44 1 2 PBY201209T-221Y-N-GP VDDHT_1 VDDHT_2 VDDHT_3 VDDHT_4 VDDHT_5 VDDHT_6 VDDHT_7 SCD1U10V2KX-4GP SCD1U10V2KX-4GP C594 SCD1U10V2KX-4GP 1D2V_S0 SCD1U10V2KX-4GP SC4D7U6D3V3KX-GP 220 ohm @ 100MHz,2A +1.1V_RUN_VDDHTRX C81 C89 C72 J17 K16 L16 M16 P16 R16 T16 SCD1U10V2KX-4GP 0.45A per ANT Rev1.1, Page3 L45 1 2 PBY201209T-221Y-N-GP 1D1V_S0 ANB1E SCD1U10V2KX-4GP 1D1V_S0 +1.1V_RUN_VDDHT C54 C52 SCD1U10V2KX-4GP C587 C55 SCD1U10V2KX-4GP D SCD1U10V2KX-4GP 220 ohm @ 100MHz,2A SC4D7U6D3V3KX-GP L43 1 2 PBY201209T-221Y-N-GP A25 D23 E22 G22 G24 G25 H19 J22 L17 L22 L24 L25 M20 N22 P20 R19 R22 R24 R25 H20 U22 V19 W22 W24 W25 Y21 AD25 GROUND 0.6A per ANT Rev1.1, Page3 1D1V_S0 B MEM_COMP_P and MEM_COMP_N trace width >=10mils and 10mils spacing from other Signals in X,Y,Z directions 1D8V_S0 1 R226 2 0R0402-PAD +1.8V_IOPLLVDD18 1D1V_S0 1 R230 2 0R0402-PAD +1.1V_IOPLLVDD A Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. RS780M-GP-U2 Title RS780 (3 of 3) Size Document Number Rev -1 SJV50-PU Date: Wednesday, February 25, 2009 5 4 3 2 Sheet 1 10 of 59 5 4 ALINK_NBTX_C_SBRX_P0 ALINK_NBTX_C_SBRX_N0 ALINK_NBTX_C_SBRX_P1 ALINK_NBTX_C_SBRX_N1 ALINK_NBTX_C_SBRX_P2 ALINK_NBTX_C_SBRX_N2 ALINK_NBTX_C_SBRX_P3 ALINK_NBTX_C_SBRX_N3 R144 R146 L36 Part 1 of 5 PCIE_TX0P PCIE_TX0N PCIE_TX1P PCIE_TX1N PCIE_TX2P PCIE_TX2N PCIE_TX3P PCIE_TX3N U22 U21 U19 V19 R20 R21 R18 R17 PCIE_RX0P PCIE_RX0N PCIE_RX1P PCIE_RX1N PCIE_RX2P PCIE_RX2N PCIE_RX3P PCIE_RX3N T25 T24 PCIE_CALRP PCIE_CALRN P24 PCIE_PVDD P25 PCIE_PVSS PCIE_RCLKP/NB_LNK_CLKP PCIE_RCLKN/NB_LNK_CLKN K23 K22 NB_DISP_CLKP NB_DISP_CLKN M24 M25 NB_HT_CLKP NB_HT_CLKN P17 M18 CPU_HT_CLKP CPU_HT_CLKN M23 M22 SLT_GFX_CLKP SLT_GFX_CLKN 12 11 13 PLT_RST1# TSLVC08APW-1-GP 7 9 PLT_RST1#_B 25,31,32,34,35,50,58 73.07408.L16 2ND = 73.07408.02B SA_20081106 DY B R345 C385 SC10P50V2JN-4GP 2 1 3 CLK_SB_14M 2 0R2J-2-GP 1 25M_X1 J19 J18 GPP_CLK0P GPP_CLK0N L20 L19 GPP_CLK1P GPP_CLK1N M19 M20 GPP_CLK2P GPP_CLK2N N22 P22 GPP_CLK3P GPP_CLK3N L18 25M_48M_66M_OSC 32K_X1 1 4 3 J21 X4 X-32D768KHZ-34GPU TP243 R153 10MR2J-L-GP 82.30001.661 125M_X2 J20 25M_X1 AD3 AC4 AE2 AE3 LPCCLK0 LPCCLK1 LAD0 LAD1 LAD2 LAD3 LFRAME# LDRQ0# LDRQ1#/GNT5#/GPIO68 BMREQ#/REQ5#/GPIO65 SERIRQ G22 E22 H24 H23 J25 J24 H25 H22 AB8 AD7 V15 25M_X2 F23 F24 F22 G25 G24 1 1 TP237 TP238 PCI_CLK2 15 PCI_CLK3 15 CLK_PCI4 15 CLK_PCI_LOM 15 ALLOW_LDTSTP PROCHOT# LDT_PG LDT_STP# LDT_RST# RTCCLK INTRUDER_ALERT# VBAT LPC PCIRST#_SB SB700-1-GP-U1 71.SB700.M02 TP172 1 PCI_AD23 PCI_AD24 PCI_AD25 PCI_AD26 PCI_AD27 PCI_AD28 PCI_AD29 PCI_AD30 15 15 15 15 15 15 15 15 C Delete test pad B PM_CLKRUN# 34 INT_PIRQE# INT_PIRQF# INT_PIRQG# INT_PIRQH# TP160 TP229 TP161 TP159 1 1 1 1 -1 090219 C3 C2 B2 LPCCLK0_R R357 1 LPCCLK1_R R358 1 2 22R2J-2-GP PCLK_FWH 15,35,58 2 22R2J-2-GP PCLK_KBC 15,34 2SC10P50V2JN-4GP DY EC511 LPC_LAD0 34,35,58 2SC10P50V2JN-4GP DY EC501 LPC_LAD1 34,35,58 LPC_LAD2 34,35,58 LPC_LAD3 34,35,58 LPC_LDRQ0# TP245 LPC_LFRAME# 34,35,58 1 LPC_LDRQ1# TP233 1 PCI_REQ#5 1 2 3D3V_S0 R331 10KR2J-3-GP INT_SERIRQ 34 RTC_CLK 15,33 INTRUDER# 1 RTC_AUX_S5_R C763 SCD1U16V2ZY-2GP A X2 PCI_CLK0 PCI_CLK1 SC1U10V2KX-1GP 6,9 ALLOW_LDTSTOP 6 PROCHOT#_SB 6,58 CPU_PWRGD 6 CPU_LDT_STOP# 6 CPU_LDT_RST# B3 RTC 32K_X2 CPU 1 C384 SC10P50V2JN-4GP X1 RTC XTAL 2 1 2 2 2nd = 82.30001.B21 A3 N1 INTE#/GPIO33 INTF#/GPIO34 INTG#/GPIO35 INTH#/GPIO36 PCI INTERFACE N25 N24 CLOCK GENERATOR 14 U6D PCIRST# U2 P7 V4 T1 V3 U1 V1 V2 T2 W1 T9 R6 R7 R5 U8 U5 Y7 W8 V9 Y8 AA8 Y4 Y3 Y2 AA2 AB4 AA1 AB3 AB2 AC1 AC2 AD1 W2 U7 AA7 Y1 AA6 W5 AA5 Y5 U6 W6 W4 V7 AC3 AD4 AB7 AE6 AB6 AD2 AE4 AD5 AC6 AE5 AD6 V5 C 3 CLK_PCIE_SB 3 CLK_PCIE_SB# P4 P3 P1 P2 T4 T3 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 CBE0# CBE1# CBE2# CBE3# FRAME# DEVSEL# IRDY# TRDY# PAR STOP# PERR# SERR# REQ0# REQ1# REQ2# REQ3#/GPIO70 REQ4#/GPIO71 GNT0# GNT1# GNT2# GNT3#/GPIO72 GNT4#/GPIO73 CLKRUN# LOCK# Place R <100mils form pins T25,T24 3D3V_S5 PCICLK0 PCICLK1 PCICLK2 PCICLK3 PCICLK4 PCICLK5/GPIO41 D 1 C720 2 1 SC1U10V2KX-1GP SC1U10V2KX-1GP C719 2 1 2 PBY201209T-221Y-N-GP 220 ohm 2A PCIE_CALRP 2 562R2F-GP 2 2K05R2F-GP PCIE_CALRN 1 1 20mil Width SB700 A_RST# V23 V22 V24 V25 U25 U24 T23 T22 RTC_AUX_S5 RTC1 1 2 NP1 NP2 TP183 1 2 R361 1KR2J-1-GP PWR GND NP1 NP2 BAT-CON2-1-GP-U 62.70001.011 1 PCIE_VDDR 1 C762 A 2 +1.2V_RUN_PCIE_PVDD 8 8 8 8 8 8 8 8 SCD1U10V2KX-4GP SCD1U10V2KX-4GP SCD1U10V2KX-4GP SCD1U10V2KX-4GP SCD1U10V2KX-4GP SCD1U10V2KX-4GP SCD1U10V2KX-4GP SCD1U10V2KX-4GP ALINK_NBRX_C_SBTX_P0 ALINK_NBRX_C_SBTX_N0 ALINK_NBRX_C_SBTX_P1 ALINK_NBRX_C_SBTX_N1 ALINK_NBRX_C_SBTX_P2 ALINK_NBRX_C_SBTX_N2 ALINK_NBRX_C_SBTX_P3 ALINK_NBRX_C_SBTX_N3 1 1D2V_S0 C703 C701 C291 C296 C311 C304 C709 C705 2 2 2 2 2 2 2 2 N2 2 D ALINK_NBRX_SBTX_P0 ALINK_NBRX_SBTX_N0 ALINK_NBRX_SBTX_P1 ALINK_NBRX_SBTX_N1 ALINK_NBRX_SBTX_P2 ALINK_NBRX_SBTX_N2 ALINK_NBRX_SBTX_P3 ALINK_NBRX_SBTX_N3 1 1 1 1 1 1 1 1 2 ASB1A NB_RST# PCI CLKS 8 8 8 8 8 8 8 8 33R2J-2-GP R339 2 1 PLT_RST1# PCI EXPRESS INTERFACE 9 3 Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title SB700 (1 of 5) Size Document Number Rev -1 SJV50-PU Date: Wednesday, February 25, 2009 5 4 3 2 Sheet 1 11 of 59 5 4 3 2 1 3D3V_S0 ASB1D 1 3D3V_S0 PM_SUS_STAT# SB_TEST2 SB_TEST1 SB_TEST0 D NB_PWRGD 2 1 R353 2 1 R329 2 1KR2J-1-GP ECSMI#_KBC 34 34 34 10KR2J-3-GP FP_ID ECSMI#_KBC TP177 GEVENT5# 1 TP175 SYS_RST# 1 10KR2J-3-GP 25 PCIE_WAKE# 34 EC_TMR 3D3V_S5 2 DY 2 DY 2 DY 2 DY 2 2K2R2F-GP SB_TEST1 D3 FP_ID GPIO6 GPIO4 HDMI AE18 AD18 AA19 W17 V17 W20 W21 AA18 W18 K1 K2 AA20 Y18 C1 Y19 G5 ICH_PME# 1 1 10KR2J-3-GP PCIE_WAKE# 10KR2J-3-GP SMB_ALERT# 27 10KR2J-3-GP SB_MEM_CLK SB_MEM_DAT SB_ASF_CLK SB_ASF_DAT PM_SLP_S5# ECSCI#_SB ECSWI#_SB PM_SLP_S3# 1 2 3 4 ACZ_SPKR TP232 TP234 TP182 TP235 TP248 SRN10KJ-6-GP 34 ECSWI#_SB Close to SB700 1 2 R462 33R2J-2-GP 1 2 R346 33R2J-2-GP 1 2 R342 33R2J-2-GP 30 ACZ_BITCLK_MDC 27 ACZ_BITCLK 27,30 ACZ_SDATAOUT 27 ACZ_SDATAIN0 30 ACZ_SDATAIN1 TP190 TP194 24,58 USB_OC#3 TP250 TP193 24 1 2 R333 1 33R2J-2-GP 2 R338 33R2J-2-GP DDC1_SCL DDC1_SDA SATA_DET# GPIO5 GEVENT7# 1USB_OC#5 1USB_OC#4 1 1 USB_OC#0 ACZ_BTCLK_R ACZ_SDATAOUT_R TP240 TP239 27,30 ACZ_SYNC 27,30 ACZ_RST# B 1 1 1 1 1 TP241 1ACZ_SDIN2 1ACZ_SDIN3 ACZ_SYNC_R ACZ_RST#_R GPM8# 1 B9 B8 A8 A9 E5 F8 E4 USB_OC6#/IR_TX1/GEVENT6# USB_OC5#/IR_TX0/GPM5# USB_OC4#/IR_RX0/GPM4# USB_OC3#/IR_RX1/GPM3# USB_OC2#/GPM2# USB_OC1#/GPM1# USB_OC0#/GPM0# M1 M2 J7 J8 L8 M3 L6 M4 L5 AZ_BITCLK AZ_SDOUT AZ_SDIN0/GPIO42 AZ_SDIN1/GPIO43 AZ_SDIN2/GPIO44 AZ_SDIN3/GPIO46 AZ_SYNC AZ_RST# AZ_DOCK_RST#/GPM8# 2 1 2 2 1 1 2 1 DY DY DY DY DY SC12P50V2JN-3GP SC12P50V2JN-3GP SC12P50V2JN-3GP SC12P50V2JN-3GP SC12P50V2JN-3GP 1 2 EC122 EC49 EC48 EC83 EC84 ACZ_RST#_R 15 TO STRAPS H19 H20 H21 F25 IMC_GPIO0 IMC_GPIO1 SPI_CS2#/IMC_GPIO2 IDE_RST#/F_RST#/IMC_GPO3 D22 E24 E25 D23 IMC_GPIO4 IMC_GPIO5 IMC_GPIO6 IMC_GPIO7 3 2CLK48_USB_R2 1 DY2 C767 SC10P50V2JN-4GP Place these close SB700 E6 E7 USB_FSD12P USB_FSD12N F7 E8 USB_HSD11P USB_HSD11N H11 J10 USBPP11 31 USBPN11 31 USB_HSD10P USB_HSD10N E11 F11 USBPP10 18 USBPN10 18 USB_HSD9P USB_HSD9N A11 B11 USBPP9 32 USBPN9 32 Pair USB_HSD8P USB_HSD8N C10 D10 USBPP8 24 USBPN8 24 11 USB_HSD7P USB_HSD7N G11 H12 USBPP7 24,58 USBPN7 24,58 USB_HSD6P USB_HSD6N E12 E14 USBPP6 24 USBPN6 24 USB_HSD5P USB_HSD5N C12 D12 USB_HSD4P USB_HSD4N B12 A12 USB_HSD3P USB_HSD3N G12 G14 USB_HSD2P USB_HSD2N H14 H15 USB_HSD1P USB_HSD1N A13 B13 USBPP1 32 USBPN1 32 USB_HSD0P USB_HSD0N B14 A14 USBPP0 24 USBPN0 24 IMC_GPIO8 IMC_GPIO9 IMC_PWM0/IMC_GPIO10 SCL2/IMC_GPIO11 SDA2/IMC_GPIO12 SCL3_LV/IMC_GPIO13 SDA3_LV/IMC_GPIO14 IMC_PWM1/IMC_GPIO15 IMC_PWM2/IMC_GPO16 IMC_PWM3/IMC_GPO17 A18 B18 F21 D21 F19 E20 E21 E19 D19 E18 IMC_GPIO18 IMC_GPIO19 IMC_GPIO20 IMC_GPIO21 IMC_GPIO22 IMC_GPIO23 IMC_GPIO24 IMC_GPIO25 G20 G21 D25 D24 C25 C24 B25 C23 IMC_GPIO26 IMC_GPIO27 IMC_GPIO28 IMC_GPIO29 IMC_GPIO30 IMC_GPIO31 IMC_GPIO32 IMC_GPIO33 IMC_GPIO34 IMC_GPIO35 IMC_GPIO36 IMC_GPIO37 IMC_GPIO38 IMC_GPIO39 IMC_GPIO40 IMC_GPIO41 B24 B23 A23 C22 A22 B22 B21 A21 D20 C20 A20 B20 B19 A19 D18 C18 RSMRST# SATA_IS0#/GPIO10 CLK_REQ3#/SATA_IS1#/GPIO6 SMARTVOLT/SATA_IS2#/GPIO4 CLK_REQ0#/SATA_IS3#/GPIO0 CLK_REQ1#/SATA_IS4#/FANOUT3/GPIO39 CLK_REQ2#/SATA_IS5#/FANIN3/GPIO40 SPKR/GPIO2 SCL0/GPOC0# SDA0/GPOC1# SCL1/GPOC2# SDA1/GPOC3# DDC1_SCL/GPIO9 DDC1_SDA/GPIO8 LLB#/GPIO66 SHUTDOWN#/GPIO5 DDR3_RST#/GEVENT7# 1 DY R364 10KR2J-3-GP USB_FSD13P USB_FSD13N SB_TEST0 TP228 TP230 CLK48_USB 2 1% 2K2R2F-GP RN65 8 7 6 5 RSMRST#_KBC 2K2R2F-GP USB_PCOMP1 R355 11K8R2F-GP USB 2.0 DY SB_TEST2 CLK48_USB G8 GPIO 2 C8 USB_RCOMP INTEGRATED uC 1 R148 1 R350 1 R341 DY SMB_ALERT# NB_PWRGD_R INTEGRATED uC 1 R351 1 R349 1 R348 C KA20GATE KBRCIN# ECSCI#_SB USBCLK/14M_25M_48M_OSC USB OC 1 HD AUDIO R20 Part 4 of 5 SB700 PCI_PME#/GEVENT4# RI#/EXTEVNT0# SLP_S2/GPM9# SLP_S3# SLP_S5# PWR_BTN# PWR_GOOD SUS_STAT# TEST2 TEST1 TEST0 GA20IN/GEVENT0# KBRST#/GEVENT1# LPC_PME#/GEVENT3# LPC_SMI#/EXTEVNT1# S3_STATE/GEVENT5# SYS_RESET#/GPM7# WAKE#/GEVENT8# BLINK/GPM6# SMBALERT#/THRMTRIP#/GEVENT2# NB_PWRGD D Place R near pin14. Route it with 10mils Trace width and 25mils spacing to any signals in X, Y, Z directions. USB USBPP5 23,58 USBPN5 23,58 SB_GPO16 SB_GPO17 Device CardReader 10 CCD 9 Mini Card2 8 USB4 7 USB3 6 USB2 5 BlueTooth OCP2# OCP1# C 4 NC 3 NC 2 NC 1 Mini Card1 0 USB1 OCP0# 15 15 Strap Pin / define to use LPC or SPI ROM B 3D3V_S5 3D3V_S0 5 6 7 8 33,34,39,47,48 PM_SLP_S3# 34,44,46 PM_SLP_S5# 34,58 PM_PWRBTN# 3,39 SB_PWRGD E1 E2 H7 F5 G1 H2 H1 K3 H5 H4 H3 Y15 W15 K4 K24 F1 J2 H6 F2 J6 W14 USB MISC 1D8V_S0 1ICH_PME# 1 RI# 1 S2# USB 1.1 1 R330 DY TP179 TP178 TP244 ACPI / WAKE UP EVENTS 2 0R2J-2-GP NB_PWRGD R347 4K7R2F-GP 2 9,39 NB_PWRGD_R RN63 SRN2K2J-2-GP 4 3 2 1 20090114 SB SB_ASF_CLK SB_ASF_DAT 3,16,17 SB_MEM_CLK 3,16,17 SB_MEM_DAT SB700-1-GP-U1 71.SB700.M02 3D3V_S5 SJV50 1 R362 10KR2J-3-GP R328 10KR2J-3-GP 2 DY 2 A 1 HDMI A 34 RSMRST#_KBC Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. RSMRST#_KBC Title Size Document Number SB700 (2 of 5) SJV50-PU Date: Wednesday, February 25, 2009 5 4 3 2 Sheet 1 Rev -1 12 of 59 4 3 D 2 ASB1B SATA_TX0P SATA_TX0N AB10 AC10 SATA_RX0N SATA_RX0P 22 22 SATA_TXP1 SATA_TXN1 AE10 AD10 SATA_TX1P SATA_TX1N 22 22 SATA_RXN1 SATA_RXP1 AD11 AE11 SATA_RX1N SATA_RX1P AB12 AC12 SATA_TX2P SATA_TX2N AE12 AD12 SATA_RX2N SATA_RX2P AD13 AE13 SATA_TX3P SATA_TX3N AB14 AC14 SATA_RX3N SATA_RX3P AE14 AD14 SATA_TX4P SATA_TX4N AD15 AE15 SATA_RX4N SATA_RX4P AB16 AC16 SATA_TX5P SATA_TX5N AE16 AD16 SATA_RX5N SATA_RX5P C Very Close to SB700 SATA_X2 PLLVDD_SATA AA11 PLLVDD_SATA W12 XTLVDD_SATA 1 2 C711 SCD1U10V2KX-4GP C710 SC1U10V2KX-1GP 2 1 20mil Width 1 R332 2 0R0603-PAD SATA_ACT#/GPIO67 Close to SB700 3D3V_S0 B XTLVDD_SATA SPI_DI/GPIO12 SPI_DO/GPIO11 SPI_CLK/GPIO47 SPI_HOLD#/GPIO31 SPI_CS#/GPIO32 G6 D2 D1 F4 F3 LAN_RST#/GPIO13 ROM_RST#/GPIO14 U15 J1 FANOUT0/GPIO3 FANOUT1/GPIO48 FANOUT2/GPIO49 M8 M5 M7 FANIN0/GPIO50 FANIN1/GPIO51 FANIN2/GPIO52 P5 P8 R8 TEMP_COMM TEMPIN0/GPIO61 TEMPIN1/GPIO62 TEMPIN2/GPIO63 TEMPIN3/TALERT#/GPIO64 C6 B6 A6 A5 B5 VIN0/GPIO53 VIN1/GPIO54 VIN2/GPIO55 VIN3/GPIO56 VIN4/GPIO57 VIN5/GPIO58 VIN6/GPIO59 VIN7/GPIO60 A4 B4 C4 D4 D5 D6 A7 B7 C706 SC1U10V2KX-1GP AVDD F6 AVSS G7 C SB_SPI_MISO SPI_MOSI_R ICH_SPICLK SB_SPI_HOLD ICH_SPICS0# LAN_RST# 1 ROM_RST# 1 TP247 TP181 TP180 TP246 TP249 1 1 1 1 1 TP236 TP176 3D3V_S0 20081201 RN66 SRN10KJ-5-GP PSW_CLR# 58 ALERT#_SB 33 PSW_CLR# B AVDD_HWM 2 1 20mil Width 1 R335 2 0R0603-PAD AD24 AD23 AE22 AC22 AD21 AE20 AB20 AD19 AE19 AC20 AD20 AE21 AB22 AD22 AE23 AC23 1 2 W11 IDE_D0/GPIO15 IDE_D1/GPIO16 IDE_D2/GPIO17 IDE_D3/GPIO18 IDE_D4/GPIO19 IDE_D5/GPIO20 IDE_D6/GPIO21 IDE_D7/GPIO22 IDE_D8/GPIO23 IDE_D9/GPIO24 IDE_D10/GPIO25 IDE_D11/GPIO26 IDE_D12/GPIO27 IDE_D13/GPIO28 IDE_D14/GPIO29 IDE_D15/GPIO30 4 3 C245 SC15P50V2JN-2-GP 1D2V_S0 SATA_X1 SATA_X2AA12 2 300R2J-4-GP MEDIA_LED# AA24 AA25 Y22 AB23 Y23 AB24 AD25 AC25 AC24 Y25 Y24 Close to SB700 R359 SC2D2U6D3V3KX-GP R360 DY Layout connect to Cap then GND 1 3D3V_S0 SCD1U10V2KX-4GP SB700-1-GP-U1 71.SB700.M02 3D3V_S5 1 R363 2 0R0603-PAD 1 1 R135 SATA_CAL Y12 D 2 SATA_X2_R V12 SATA_X1 IDE_IORDY IDE_IRQ IDE_A0 IDE_A1 IDE_A2 IDE_DACK# IDE_DRQ IDE_IOR# IDE_IOW# IDE_CS1# IDE_CS3# 1 1 SATA_CAL HW MONITOR 1 R134 10MR2J-L-GP 2 2 R336 1KR2F-3-GP 1 2 2 X3 XTAL-25MHZ-102-GP 82.30020.851 2ND = 82.30020.791 1 C244 SC15P50V2JN-2-GP 2 1 Part 2 of 5 ATA 66/100/133 AD9 AE9 SATA_RXN0 SATA_RXP0 SPI ROM SATA_TXP0 SATA_TXN0 21 21 SERIAL ATA SATA ODD 21 21 SATA PWR SATA HDD 1 Delete Test Pad SB700 2 5 2 R337 10KR2J-3-GP 38 MEDIA_LED# MEDIA_LED# A A SJV50 Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. SA_20081030 Title Size Document Number SB700 (3 of 5) SJV50-PU Date: Wednesday, February 25, 2009 5 4 3 2 Sheet 1 Rev -1 13 of 59 5 4 3 2 1 ASB1C SB700-1-GP-U1 71.SB700.M02 1 1 2 2 1 2 1 1 1 2 2 CLKGEN I/O AVSS_SATA_1 AVSS_SATA_2 AVSS_SATA_3 AVSS_SATA_4 AVSS_SATA_5 AVSS_SATA_6 AVSS_SATA_7 AVSS_SATA_8 AVSS_SATA_9 AVSS_SATA_10 AVSS_SATA_11 AVSS_SATA_12 AVSS_SATA_13 AVSS_SATA_14 AVSS_SATA_15 AVSS_SATA_16 AVSS_SATA_17 AVSS_SATA_18 AVSS_SATA_19 AVSS_SATA_20 A15 B15 C14 D8 D9 D11 D13 D14 D15 E15 F12 F14 G9 H9 H17 J9 J11 J12 J14 J15 K10 K12 K14 K15 AVSS_USB_1 AVSS_USB_2 AVSS_USB_3 AVSS_USB_4 AVSS_USB_5 AVSS_USB_6 AVSS_USB_7 AVSS_USB_8 AVSS_USB_9 AVSS_USB_10 AVSS_USB_11 AVSS_USB_12 AVSS_USB_13 AVSS_USB_14 AVSS_USB_15 AVSS_USB_16 AVSS_USB_17 AVSS_USB_18 AVSS_USB_19 AVSS_USB_20 AVSS_USB_21 AVSS_USB_22 AVSS_USB_23 AVSS_USB_24 2 1 C386 C373 2 1 1 2 2 1 C764 5V_S0 V5_VREF AE7 V5_VREF AVDDCK_3.3V J16 AVDDCK_3D3V K17 AVDDK_1D2V 1 C765 68.00206.121 1 C255 2 1 2 PBY201209T-221Y-N-GP 1 C752 2 3D3V_S5 L37 3D3V_AVDDC 2 E9 1 AVDDC 2 AVDDCK_1.2V 2 C251 1 H18 J17 J22 K25 M16 M17 M21 P16 1KR2J-1-GP 3D3V_S0 RB751V-40-2-GP K A D3 83.R2004.B8F 2ND = 83.R0304.A8F F9 PCIE_CK_VSS_1 PCIE_CK_VSS_2 PCIE_CK_VSS_3 PCIE_CK_VSS_4 PCIE_CK_VSS_5 PCIE_CK_VSS_6 PCIE_CK_VSS_7 PCIE_CK_VSS_8 GROUND 1 2 1 1 2 2 2 1 3.3V_S5 I/O PLL AVDDTX_0 AVDDTX_1 AVDDTX_2 AVDDTX_3 AVDDTX_4 AVDDTX_5 AVDDRX_0 AVDDRX_1 AVDDRX_2 AVDDRX_3 AVDDRX_4 AVDDRX_5 USB I/O 1 A16 B16 C16 D16 D17 E17 F15 F17 F18 G15 G17 G18 SC1U10V2KX-1GP 2 1 C755 A10 B10 SCD1U10V2KX-4GP 2 1 C754 SCD1U10V2KX-4GP 2 1 C741 SCD1U10V2KX-4GP 2 1 C751 SC1U10V2KX-1GP 2 1 50mil Width C739 T10 U10 U11 U12 V11 V14 W9 Y9 Y11 Y14 Y17 AA9 AB9 AB11 AB13 AB15 AB17 AC8 AD8 AE8 R128 AVDD_USB SC1U10V2KX-1GP SC10U10V5ZY-1GP SC10U10V5ZY-1GP 2 C383 2 CORE S0 PCI/GPIO I/O SATA I/O 1 2 CORE S5 1 2 1 2 1 1 2 1 2 1D2V_S5 SC1U10V2KX-1GP C387 C757 SCD1U10V2KX-4GP B C728 SC10U10V5ZY-1GP 2 1 2 1 2 1 50mil Width Use Plane Shape for +3.3V_AVDD_USB 1 2 PBY201209T-221Y-N-GP DY C729 SC10U10V5ZY-1GP 2 IDE/FLSH I/O 1 2 1 2 1 2 1 2 1 2 1 2 1 2 S5_1.2V_1 S5_1.2V_2 G2 G4 C760 SCD1U10V2KX-4GP AVDD_SATA_1 AVDD_SATA_4 AVDD_SATA_2 AVDD_SATA_3 AVDD_SATA_5 AVDD_SATA_6 AVDD_SATA_7 A17 A24 B17 J4 J5 L1 L2 SC1U10V2KX-1GP AA14 AB18 AA15 AA17 AC18 AD17 AE17 S5_3.3V_1 S5_3.3V_2 S5_3.3V_3 S5_3.3V_4 S5_3.3V_5 S5_3.3V_6 S5_3.3V_7 USB_PHY_1.2V_1 USB_PHY_1.2V_2 3D3V_S5 L38 C370 SC4D7U6D3V3KX-GP C699 SCD1U10V2KX-4GP SCD1U10V2KX-4GP SC1U10V2KX-1GP SC10U6D3V5KX-1GP SC10U6D3V5KX-1GP SCD1U16V2ZY-2GP PCIE_VDDR_1 PCIE_VDDR_2 PCIE_VDDR_3 PCIE_VDDR_4 PCIE_VDDR_5 PCIE_VDDR_6 PCIE_VDDR_7 SCD1U10V2KX-4GP C700 VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8 VSS_9 VSS_10 VSS_11 VSS_12 VSS_13 VSS_14 VSS_15 VSS_16 VSS_17 VSS_18 VSS_19 VSS_20 VSS_21 VSS_22 VSS_23 VSS_24 VSS_25 VSS_26 VSS_27 VSS_28 VSS_29 VSS_30 VSS_31 VSS_32 VSS_33 VSS_34 VSS_35 VSS_36 VSS_37 VSS_38 VSS_39 VSS_40 VSS_41 VSS_42 VSS_43 VSS_44 VSS_45 VSS_46 VSS_47 VSS_48 VSS_49 VSS_50 3D3V_S5 P18 P19 P20 P21 R22 R24 R25 SCD1U10V2KX-4GP C712 1D2V_S0 1 R147 2 0R0402-PAD DY SC1U10V2KX-1GP C241 POWER AVDD_SATA 50mil Width C218 C724 SCD1U10V2KX-4GP DY L28 1 2 PBY201209T-221Y-N-GP EC85 C722 SCD1U10V2KX-4GP 1D2V_S0 SC1U10V2KX-1GP SC4D7U6D3V3KX-GP C C721 C369 DY Part 5 of 5 C375 SC2D2U6D3V3KX-GP 50mil Width C334 C718 SC2D2U6D3V3KX-GP PCIE_VDDR 220 ohm 2A L21 L22 L24 L25 C731 CKVDD 1D2V_S0 L33 1 2 PBY201209T-221Y-N-GP CKVDD_1.2V_1 CKVDD_1.2V_2 CKVDD_1.2V_3 CKVDD_1.2V_4 SB700 C730 SC10U10V5ZY-1GP VDD33_18_1 VDD33_18_2 VDD33_18_3 VDD33_18_4 ASB1E SCD1U10V2KX-4GP SC1U10V2KX-1GP SC4D7U6D3V3KX-GP SC10U10V5ZY-1GP Y20 AA21 AA22 AE25 L15 M12 M14 N13 P12 P14 R11 R15 T16 SC1U10V2KX-1GP C732 SCD1U10V2KX-4GP C714 C702 SCD1U10V2KX-4GP C708 SCD1U10V2KX-4GP C279 C717 VDD_1 VDD_2 VDD_3 VDD_4 VDD_5 VDD_6 VDD_7 VDD_8 VDD_9 Part 3 of 5 SC1U10V2KX-1GP 3D3V_S0 D 1D2V_S0 SB700 VDDQ_1 VDDQ_2 VDDQ_3 VDDQ_4 VDDQ_5 VDDQ_6 VDDQ_7 VDDQ_8 VDDQ_9 VDDQ_10 VDDQ_11 VDDQ_12 A-LINK I/O 3D3V_S0 L9 M9 T15 U9 U16 U17 V8 W7 Y6 AA4 AB5 AB21 PCIE_CK_VSS_9 PCIE_CK_VSS_10 PCIE_CK_VSS_11 PCIE_CK_VSS_12 PCIE_CK_VSS_13 PCIE_CK_VSS_14 PCIE_CK_VSS_15 PCIE_CK_VSS_16 PCIE_CK_VSS_17 PCIE_CK_VSS_18 PCIE_CK_VSS_19 PCIE_CK_VSS_20 PCIE_CK_VSS_21 AVSSC AVSSCK A2 A25 B1 D7 F20 G19 H8 K9 K11 K16 L4 L7 L10 L11 L12 L14 L16 M6 M10 M11 M13 M15 N4 N12 N14 P6 P9 P10 P11 P13 P15 R1 R2 R4 R9 R10 R12 R14 T11 T12 T14 U4 U14 V6 Y21 AB1 AB19 AB25 AE1 AE24 D C P23 R16 R19 T17 U18 U20 V18 V20 V21 W19 W22 W24 W25 B L17 SB700-1-GP-U1 71.SB700.M02 20mil Width 1 C737 SC1U10V2KX-1GP 2 C736 SCD1U10V2KX-4GP 3D3V_S0 2 R354 1 0R0603-PAD 2 1 AVDDCK_3D3V 1D2V_S0 2 C733 SC1U10V2KX-1GP 1 C727 SCD1U10V2KX-4GP A 20mil Width R344 2 1 0R0603-PAD A 2 1 AVDDK_1D2V Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title SB700 (4 of 5) Size Document Number Rev -1 SJV50-PU Date: Wednesday, February 25, 2009 5 4 3 2 Sheet 1 14 of 59 A B Delete DY Parts C D E REQUIRED STRAPS REQUIRED SYSTEM STRAPS 4 4 3D3V_S5 TP170 1 TP171 PCI_CLK2 11 PCI_CLK3 11 CLK_PCI4 11 CLK_PCI_LOM 11 PCLK_FWH 11,35,58 PCLK_KBC 11,34 RTC_CLK 11,33 ACZ_RST#_R 12 SB_GPO17 12 1 TP186 1 1 R340 1 2 2 4 3 RN62 SRN10KJ-5-GP 10KR2J-3-GP 4 3 4 3 RN61 SRN10KJ-5-GP 2 PCI_CLK2 PULL HIGH WatchDOG (NB_PWRGD) ENABLED PCI_CLK3 CLK_PCI_LOM CLK_PCI4 USE DEBUG STRAPS PCLK_FWH IMC ENABLED CLKGEN ENABLED (Use Internal) RESERVED PULL LOW PCLK_KBC WatchDog (NB_PWRGD) DISABLED IGNORE DEBUG STRAPS IMC DISABLED DEFAULT DEFAULT DEFAULT CLKGEN DISABLED (Use External) DEFAULT RTCCLK INTERNAL RTC AZ_RST# ENABLE PCI ROM BOOT DEFAULT EXT. RTC (PD on X1, apply 32KHz to RTC_CLK) 3 RN29 SRN2K2J-1-GP 1 2 1 2 3 SB_GPO16 DEBUG STRAPS 12 TP169 TP168 TP231 TP166 TP164 TP165 TP163 TP162 PCI_AD28 PCI_AD27 PCI_AD26 SB_GPO17 , SB_GPO16 ROM TYPE: PULL HIGH H, H = Reserved DEFAULT H, L = SPI ROM DISABLE PCI ROM BOOT L, H = LPC ROM DEFAULT L, L = FWH ROM 1 1 1 1 1 1 1 1 PULL LOW USE LONG RESET (DEFAULT) USE SHORT RESET PCI_AD23 PCI_AD24 PCI_AD25 PCI_AD26 PCI_AD27 PCI_AD28 PCI_AD29 PCI_AD30 11 11 11 11 11 11 11 11 PCI_AD25 PCI_AD24 USE PCI PLL USE ACPI BCLK USE IDE PLL USE DEFAULT PCIE STRAPS Reserved PCI_AD23 (DEFAULT) (DEFAULT) (DEFAULT) (DEFAULT) (DEFAULT) BYPASS PCI PLL BYPASS ACPI BCLK BYPASS IDE PLL USE EEPROM PCIE STRAPS Reserved PCI_AD30 PCI_AD29 2 Reserved Note: SB700 has 15K internal PU FOR PCI_AD[30:23] NOTE: SB700 HAS INTERNAL 15K PULL UP RESISTOR FOR RTCCLK 1 1 Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title SB700 (5 of 5) Size Document Number Rev -1 SJV50-PU Date: Wednesday, February 25, 2009 A B C D Sheet E 15 of 59 A B C D E DDR2 SOCKET_2 (9.2mm) PARALLEL TERMINATION Put decap near power(0.9V) and pull-up resistor 4 4 0D9V_S3 DM2 MEM_MB_CLK1_P 5 MEM_MB_CLK1_N 5 DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7 10 26 52 67 130 147 170 185 MEM_MB_DM0 MEM_MB_DM1 MEM_MB_DM2 MEM_MB_DM3 MEM_MB_DM4 MEM_MB_DM5 MEM_MB_DM6 MEM_MB_DM7 SDA SCL 195 197 VDDSPD 199 1D8V_S3 1 1 PLACE CLOSE TO PROCESSOR WITHIN 1.5 INCH MEM_MB0_ODT1 5 MEM_MB0_CS#1 5 MEM_MB_CAS# 5 MEM_MB_WE# 5 SRN47J-4-GP RN38 8 7 6 5 MEM_MB_BANK2 5 MEM_MB_CKE0 5 MEM_MB_ADD15 5 MEM_MB_CKE1 5 1 2 3 4 SRN47J-4-GP RN44 8 7 6 5 MEM_MB_BANK1 MEM_MB0_CS#0 MEM_MB0_ODT0 MEM_MB_ADD13 1 2 3 4 SRN47J-4-GP RN39 8 7 6 5 MEM_MB_ADD5 5 MEM_MB_ADD8 5 MEM_MB_ADD12 5 MEM_MB_ADD9 5 1 2 3 4 SRN47J-4-GP RN40 8 7 6 5 MEM_MB_BANK0 5 MEM_MB_ADD10 5 MEM_MB_ADD1 5 MEM_MB_ADD3 5 1 2 3 4 SRN47J-4-GP RN42 8 7 6 5 MEM_MB_ADD14 5 MEM_MB_ADD11 5 MEM_MB_ADD7 5 MEM_MB_ADD6 5 1 2 3 4 SRN47J-4-GP RN43 8 7 6 5 MEM_MB_ADD2 5 MEM_MB_ADD4 5 MEM_MB_ADD0 5 MEM_MB_RAS# 5 2 2 DY MEM_MB_CLK0_P 5 5 5 5 3 1 SRN47J-4-GP 2 C203 SC1D5P50V2CN-1GP MEM_MB_CLK0_N Do not share the Term resistor between the DDR addess and Control Signals. MEM_MB_CLK1_P C197 SC1D5P50V2CN-1GP MEM_MB_CLK1_N Decoupling Capacitor Put decap near power(0.9V) and pull-up resistor 1 2 1 2 1 2 1 2 1 2 2 C423 SC10P50V2JN-4GP 1 C401 2 1 C478 2 1 C404 2 1 2 1 C473 2 Layout Note: Place one cap close to every 2 pullup resistors terminated to 0D9V_S3 SCD1U16V2ZY-2GP 2 1 C462 SC1KP50V2KX-1GP C472 SCD1U16V2ZY-2GP 2 C424 SC1KP50V2KX-1GP 1 C460 Place these Caps near DM2 C475 SCD1U16V2ZY-2GP 2 C452 SCD1U16V2ZY-2GP C476 C461 SCD1U16V2ZY-2GP 1D8V_S3 1 C450 2 1 0D9V_S3 Place these Caps near PARALLEL TERMINATION 1D8V_S3 1 C464 2 1 C410 2 1 2 1 C413 2 1 2 1 2 1 C443 C407 SCD1U16V2ZY-2GP 2 1 C447 SCD1U16V2ZY-2GP 2 C463 SCD1U16V2ZY-2GP 2 C468 SCD1U16V2ZY-2GP DDR2-200P-23-GP-U1 62.10017.A71 62.10017.B51 C466 SCD1U16V2ZY-2GP 2 1 0D9V_S3 SCD1U16V2ZY-2GP Place C2.2uF and 0.1uF < 500mils from DDR connector C457 SCD1U16V2ZY-2GP 3 8 9 12 15 18 21 24 27 28 33 34 39 40 41 42 47 48 53 54 59 60 65 66 71 72 77 78 121 122 127 128 132 133 138 139 144 145 149 150 155 156 161 162 165 168 171 172 177 178 183 184 187 190 193 196 2 10KR2J-3-GP (A1) 8 7 6 5 1 2 3 4 C454 SCD1U10V2KX-4GP SC2D2U6D3V3KX-GP 81 82 87 88 95 96 103 104 111 112 117 118 1 R177 SC2D2U6D3V3KX-GP VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD DIMM2_SA0 3D3V_S0 SCD1U16V2ZY-2GP 50 69 83 120 163 SB_MEM_DAT 3,12,17 SB_MEM_CLK 3,12,17 SC2D2U6D3V3KX-GP 198 200 5 5 5 5 5 5 5 5 SCD1U16V2ZY-2GP SA0 SA1 NC#50 NC#69 NC#83 NC#120 NC#163/TEST MH2 1 2 1 164 166 SC2D2U6D3V3KX-GP 1 CK1 CK1# 201 OTD0 OTD1 2 MEM_MB_CLK0_P 5 MEM_MB_CLK0_N 5 MH2 114 119 1 30 32 GND DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 2 CK0 CK0# MH1 13 31 51 70 131 148 169 188 SCD1U10V2KX-4GP 1 MEM_MB_CKE0 5 MEM_MB_CKE1 5 GND MEM_MB_DQS0_P MEM_MB_DQS1_P MEM_MB_DQS2_P MEM_MB_DQS3_P MEM_MB_DQS4_P MEM_MB_DQS5_P MEM_MB_DQS6_P MEM_MB_DQS7_P C449 MEM_MB0_CS#0 5 MEM_MB0_CS#1 5 MH1 5 5 5 5 5 5 5 5 C455 110 115 79 80 VREF VSS DQS0# DQS1# DQS2# DQS3# DQS4# DQS5# DQS6# DQS7# C458 CS0# CS1# 202 11 29 49 68 129 146 167 186 1 2 3 4 CKE0 CKE1 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS MEM_MB_DQS0_N MEM_MB_DQS1_N MEM_MB_DQS2_N MEM_MB_DQS3_N MEM_MB_DQS4_N MEM_MB_DQS5_N MEM_MB_DQS6_N MEM_MB_DQS7_N SC2D2U6D3V3KX-GP SC10U6D3V5MX-3GP DY DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 5 5 5 5 5 5 5 5 5 MEM_MB0_ODT0 5 MEM_MB0_ODT1 VREF_DDR_MEM 5 7 17 19 4 6 14 16 23 25 35 37 20 22 36 38 43 45 55 57 44 46 56 58 61 63 73 75 62 64 74 76 123 125 135 137 124 126 134 136 141 143 151 153 140 142 152 154 157 159 173 175 158 160 174 176 179 181 189 191 180 182 192 194 MEM_MB_RAS# 5 MEM_MB_WE# 5 MEM_MB_CAS# 5 SCD1U16V2ZY-2GP 2 BA0 BA1 108 109 113 SCD1U16V2ZY-2GP 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 3 MEM_MB_DATA0 MEM_MB_DATA1 MEM_MB_DATA2 MEM_MB_DATA3 MEM_MB_DATA4 MEM_MB_DATA5 MEM_MB_DATA6 MEM_MB_DATA7 MEM_MB_DATA8 MEM_MB_DATA9 MEM_MB_DATA10 MEM_MB_DATA11 MEM_MB_DATA12 MEM_MB_DATA13 MEM_MB_DATA14 MEM_MB_DATA15 MEM_MB_DATA16 MEM_MB_DATA17 MEM_MB_DATA18 MEM_MB_DATA19 MEM_MB_DATA20 MEM_MB_DATA21 MEM_MB_DATA22 MEM_MB_DATA23 MEM_MB_DATA24 MEM_MB_DATA25 MEM_MB_DATA26 MEM_MB_DATA27 MEM_MB_DATA28 MEM_MB_DATA29 MEM_MB_DATA30 MEM_MB_DATA31 MEM_MB_DATA32 MEM_MB_DATA33 MEM_MB_DATA34 MEM_MB_DATA35 MEM_MB_DATA36 MEM_MB_DATA37 MEM_MB_DATA38 MEM_MB_DATA39 MEM_MB_DATA40 MEM_MB_DATA41 MEM_MB_DATA42 MEM_MB_DATA43 MEM_MB_DATA44 MEM_MB_DATA45 MEM_MB_DATA46 MEM_MB_DATA47 MEM_MB_DATA48 MEM_MB_DATA49 MEM_MB_DATA50 MEM_MB_DATA51 MEM_MB_DATA52 MEM_MB_DATA53 MEM_MB_DATA54 MEM_MB_DATA55 MEM_MB_DATA56 MEM_MB_DATA57 MEM_MB_DATA58 MEM_MB_DATA59 MEM_MB_DATA60 MEM_MB_DATA61 MEM_MB_DATA62 MEM_MB_DATA63 107 106 RAS# WE# CAS# SC2D2U6D3V3KX-GP 5 5 5 5 5 5 5 5 5 5 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15 A16/BA2 1 5 MEM_MB_BANK2 5 MEM_MB_BANK0 5 MEM_MB_BANK1 102 101 100 99 98 97 94 92 93 91 105 90 89 116 86 84 85 2 5 5 5 5 5 5 MEM_MB_ADD0 MEM_MB_ADD1 MEM_MB_ADD2 MEM_MB_ADD3 MEM_MB_ADD4 MEM_MB_ADD5 MEM_MB_ADD6 MEM_MB_ADD7 MEM_MB_ADD8 MEM_MB_ADD9 MEM_MB_ADD10 MEM_MB_ADD11 MEM_MB_ADD12 MEM_MB_ADD13 MEM_MB_ADD14 MEM_MB_ADD15 REVERSE TYPE 5 5 5 5 5 5 5 5 5 5 RN41 1 9.2 mm Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size Date: A B C D Document Number DDR2 Socket_2 SJV50-PU Wednesday, February 25, 2009 Sheet E Rev -1 16 of 59 A B C D E DDR2 SOCKET_1 (5.2mm) DM1 CKE0 CKE1 79 80 MEM_MA_CKE0 5 MEM_MA_CKE1 5 CK0 /CK0 30 32 MEM_MA_CLK0_P 5 MEM_MA_CLK0_N 5 CK1 /CK1 164 166 MEM_MA_CLK1_P 5 MEM_MA_CLK1_N 5 DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7 10 26 52 67 130 147 170 185 MEM_MA_DM0 MEM_MA_DM1 MEM_MA_DM2 MEM_MA_DM3 MEM_MA_DM4 MEM_MA_DM5 MEM_MA_DM6 MEM_MA_DM7 SDA SCL 195 197 1 1 MEM_MA_ADD10 5 MEM_MA_BANK0 5 MEM_MA_ADD3 5 MEM_MA_ADD1 5 2 2 SRN47J-4-GP RN31 8 7 6 5 1 SRN47J-4-GP RN32 8 7 6 5 MEM_MA0_CS#1 5 MEM_MA0_ODT1 5 MEM_MA_CAS# 5 MEM_MA_WE# 5 3 Decoupling Capacitor Put decap near power(0.9V) and pull-up resistor 1 C451 2 1 C421 2 1 C445 2 C446 2 2 1 C420 2 1 1 C459 2 1 0D9V_S3 C453 Place these Caps near DM2 2 1 1 C477 C402 C403 2 1 C444 2 1 C809 2 C810 1 C808 2 C811 1 1D8V_S3 Layout Note: Place one cap close to every 2 pullup resistors terminated to 0D9V_S3 SKT-SODIMM20022U2GP 2 62.10017.691 2ND = 62.10017.911 5.2mm Place these Caps near PARALLEL TERMINATION 1D8V_S3 1 2 1 2 1 C456 SCD1U16V2ZY-2GP 2 1 C411 SCD1U16V2ZY-2GP 2 1 C412 SCD1U16V2ZY-2GP 2 1 C448 SCD1U16V2ZY-2GP 2 1 C469 SCD1U16V2ZY-2GP 2 1 C467 SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP 2 C465 C418 1 C417 2 1 2 2 SRN1KJ-7-GP 1 C419 SC1KP50V2KX-1GP 4 3 SCD1U10V2KX-4GP SCD1U10V2KX-4GP RN30 1 VREF_DDR_MEM 1 1 2 C409 SCD1U16V2ZY-2GP 1D8V_S3 SCD1U16V2ZY-2GP DDR_VREF C408 1 0D9V_S3 Place C2.2uF and 0.1uF < 500mils from DDR connector 2 1 2 1 2 3 4 MEM_MA_CLK1_N 2 GND MEM_MA_ADD14 5 MEM_MA_ADD11 5 MEM_MA_ADD7 5 MEM_MA_ADD6 5 Do not share the Term resistor between the DDR addess and Control Signals. C186 SC1D5P50V2CN-1GP 1 GND SRN47J-4-GP RN35 8 7 6 5 SRN47J-4-GP 2 VREF VSS 202 C426 1 2 3 4 MEM_MA_CLK1_P 1 1 2 C429 MEM_MA_CLK0_N 2 ODT0 ODT1 SC1D5P50V2CN-1GP 1 114 119 MEM_MA_ADD5 5 MEM_MA_ADD8 5 MEM_MA_ADD9 5 MEM_MA_ADD12 5 1 2 3 4 C198 2 DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 SRN47J-4-GP RN34 8 7 6 5 MEM_MA_CLK0_P SCD1U16V2ZY-2GP 13 31 51 70 131 148 169 188 PLACE CLOSE TO PROCESSOR WITHIN 1.5 INCH SC2D2U6D3V3KX-GP MEM_MA_DQS0_P MEM_MA_DQS1_P MEM_MA_DQS2_P MEM_MA_DQS3_P MEM_MA_DQS4_P MEM_MA_DQS5_P MEM_MA_DQS6_P MEM_MA_DQS7_P 1D8V_S3 SC2D2U6D3V3KX-GP 5 5 5 5 5 5 5 5 1 2 3 4 (A0) SC2D2U6D3V3KX-GP /DQS0 /DQS1 /DQS2 /DQS3 /DQS4 /DQS5 /DQS6 /DQS7 MEM_MA0_CS#0 5 MEM_MA_RAS# 5 MEM_MA_ADD13 5 MEM_MA0_ODT0 5 SC10P50V2JN-4GP 201 11 29 49 68 129 146 167 186 SRN47J-4-GP RN37 8 7 6 5 SC180P50V2JN-1GP 3 8 9 12 15 18 21 24 27 28 33 34 39 40 41 42 47 48 53 54 59 60 65 66 71 72 77 78 121 122 127 128 132 133 138 139 144 145 149 150 155 156 161 162 165 168 171 172 177 178 183 184 187 190 193 196 1 2 3 4 4 SC1KP50V2KX-1GP 81 82 87 88 95 96 103 104 111 112 117 118 DY C416 SCD1U10V2KX-4GP MEM_MA_ADD0 5 MEM_MA_ADD2 5 MEM_MA_ADD4 5 MEM_MA_BANK1 5 SC1KP50V2KX-1GP VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD C425 SC2D2U6D3V3KX-GP SRN47J-4-GP RN36 8 7 6 5 SC180P50V2JN-1GP 50 69 83 120 163 3D3V_S0 1 2 3 4 SCD01U50V2KX-1GP NC#50 NC#69 NC#83 NC#120 NC#163/TEST SB_MEM_DAT 3,12,16 SB_MEM_CLK 3,12,16 MEM_MA_BANK2 5 MEM_MA_ADD15 5 MEM_MA_CKE0 5 MEM_MA_CKE1 5 SCD1U16V2ZY-2GP 198 200 5 5 5 5 5 5 5 5 8 7 6 5 SCD01U50V2KX-1GP 199 SA0 SA1 RN33 1 2 3 4 SCD1U16V2ZY-2GP VDDSPD Put decap near power(0.9V) and pull-up resistor 0D9V_S3 SC2D2U6D3V3KX-GP 1 MEM_MA0_CS#0 5 MEM_MA0_CS#1 5 MEM_MA_DQS0_N MEM_MA_DQS1_N MEM_MA_DQS2_N MEM_MA_DQS3_N MEM_MA_DQS4_N MEM_MA_DQS5_N MEM_MA_DQS6_N MEM_MA_DQS7_N SCD1U10V2KX-4GP SC2D2U6D3V3KX-GP SC10U6D3V5MX-3GP 2 110 115 5 5 5 5 5 5 5 5 VREF_DDR_MEM DY DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 MEM_MA_RAS# 5 MEM_MA_WE# 5 MEM_MA_CAS# 5 /CS0 /CS1 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS 5 MEM_MA0_ODT0 5 MEM_MA0_ODT1 C430 BA0 BA1 5 7 17 19 4 6 14 16 23 25 35 37 20 22 36 38 43 45 55 57 44 46 56 58 61 63 73 75 62 64 74 76 123 125 135 137 124 126 134 136 141 143 151 153 140 142 152 154 157 159 173 175 158 160 174 176 179 181 189 191 180 182 192 194 108 109 113 SCD1U16V2ZY-2GP 2 107 106 PARALLEL TERMINATION /RAS /WE /CAS REVERSE TYPE 3 MEM_MA_DATA0 MEM_MA_DATA1 MEM_MA_DATA2 MEM_MA_DATA3 MEM_MA_DATA4 MEM_MA_DATA5 MEM_MA_DATA6 MEM_MA_DATA7 MEM_MA_DATA8 MEM_MA_DATA9 MEM_MA_DATA10 MEM_MA_DATA11 MEM_MA_DATA12 MEM_MA_DATA13 MEM_MA_DATA14 MEM_MA_DATA15 MEM_MA_DATA16 MEM_MA_DATA17 MEM_MA_DATA18 MEM_MA_DATA19 MEM_MA_DATA20 MEM_MA_DATA21 MEM_MA_DATA22 MEM_MA_DATA23 MEM_MA_DATA24 MEM_MA_DATA25 MEM_MA_DATA26 MEM_MA_DATA27 MEM_MA_DATA28 MEM_MA_DATA29 MEM_MA_DATA30 MEM_MA_DATA31 MEM_MA_DATA32 MEM_MA_DATA33 MEM_MA_DATA34 MEM_MA_DATA35 MEM_MA_DATA36 MEM_MA_DATA37 MEM_MA_DATA38 MEM_MA_DATA39 MEM_MA_DATA40 MEM_MA_DATA41 MEM_MA_DATA42 MEM_MA_DATA43 MEM_MA_DATA44 MEM_MA_DATA45 MEM_MA_DATA46 MEM_MA_DATA47 MEM_MA_DATA48 MEM_MA_DATA49 MEM_MA_DATA50 MEM_MA_DATA51 MEM_MA_DATA52 MEM_MA_DATA53 MEM_MA_DATA54 MEM_MA_DATA55 MEM_MA_DATA56 MEM_MA_DATA57 MEM_MA_DATA58 MEM_MA_DATA59 MEM_MA_DATA60 MEM_MA_DATA61 MEM_MA_DATA62 MEM_MA_DATA63 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15 A16/BA2 2 5 MEM_MA_BANK2 5 MEM_MA_BANK0 5 MEM_MA_BANK1 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 102 101 100 99 98 97 94 92 93 91 105 90 89 116 86 84 85 1 4 MEM_MA_ADD0 MEM_MA_ADD1 MEM_MA_ADD2 MEM_MA_ADD3 MEM_MA_ADD4 MEM_MA_ADD5 MEM_MA_ADD6 MEM_MA_ADD7 MEM_MA_ADD8 MEM_MA_ADD9 MEM_MA_ADD10 MEM_MA_ADD11 MEM_MA_ADD12 MEM_MA_ADD13 MEM_MA_ADD14 MEM_MA_ADD15 2 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. LAYOUT: Locate close to DIMM Title DDR2 Socket_1 Size Document Number Rev -1 SJV50-PU Date: Wednesday, February 25, 2009 A B C D Sheet E 17 of 59 LCD/CCD CONN RN3 LCD_TXACLK+ LCD_TXACLKLCD_TXBCLK+ LCD_TXBCLK- 1 2 3 4 8 7 6 5 GMCH_TXACLK+ GMCH_TXACLKGMCH_TXBCLK+ GMCH_TXBCLK- 9 9 9 9 UMASRN0J-7-GP RN9 LCDVDD LCD_TXAOUT1+ LCD_TXAOUT1LCD_TXAOUT0+ LCD_TXAOUT0- C4 LCD1 34 DBC_EN 3D3V_S0 M92_LCD_CLK M92_LCD_DAT BRIGHTNESS_CN BLON_OUT_R DCBATOUT F2 DCBATOUT_LCD1 1 2 POLYSW-1D1A24V-GP C489 SC10U25V6KX-1GP 2 69.50007.A31 2nd = 69.50007.A41 1 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 42 20081231 Add for KBC 1 2 41 40 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 LCD_TXBCLK+ LCD_TXBCLKLCD_TXBOUT2+ LCD_TXBOUT2LCD_TXBOUT1+ LCD_TXBOUT1LCD_TXBOUT0+ LCD_TXBOUT0LCD_TXACLK+ LCD_TXACLKLCD_TXAOUT2+ LCD_TXAOUT2LCD_TXAOUT1+ LCD_TXAOUT1LCD_TXAOUT0+ LCD_TXAOUT0- SC10U25V6KX-1GP 1 20081231 change LCD conn. 1 2 3 4 8 7 6 5 GMCH_TXAOUT1+ GMCH_TXAOUT1GMCH_TXAOUT0+ GMCH_TXAOUT0- 9 9 9 9 GMCH_TXAOUT2+ GMCH_TXAOUT2GMCH_TXBOUT2+ GMCH_TXBOUT2- 9 9 9 9 GMCH_TXBOUT1+ GMCH_TXBOUT1GMCH_TXBOUT0GMCH_TXBOUT0+ 9 9 9 9 UMASRN0J-7-GP RN7 LCD_TXAOUT2+ LCD_TXAOUT2LCD_TXBOUT2+ LCD_TXBOUT2- 1 2 3 4 8 7 6 5 UMASRN0J-7-GP RN5 LCD_TXBOUT1+ LCD_TXBOUT1LCD_TXBOUT0LCD_TXBOUT0+ 1 2 3 4 8 7 6 5 SRN0J-7-GP UMA RN4 LCD_TXBCLKLCD_TXBCLK+ LCD_TXACLKLCD_TXACLK+ 1 2 3 4 8 7 6 5 LVDS_M92_TXBCLKLVDS_M92_TXBCLK+ LVDS_M92_TXACLKLVDS_M92_TXACLK+ 51 51 51 51 DIS SRN0J-7-GP ACES-CONN40C-4-GP RN10 LCD_TXAOUT0LCD_TXAOUT0+ LCD_TXAOUT1LCD_TXAOUT1+ 20.F1296.040 1 2 3 4 8 7 6 5 LVDS_M92_TXAOUT0LVDS_M92_TXAOUT0+ LVDS_M92_TXAOUT1LVDS_M92_TXAOUT1+ 51 51 51 51 LVDS_M92_TXBOUT2LVDS_M92_TXBOUT2+ LVDS_M92_TXAOUT2LVDS_M92_TXAOUT2+ 51 51 51 51 LVDS_M92_TXBOUT0+ LVDS_M92_TXBOUT0LVDS_M92_TXBOUT1LVDS_M92_TXBOUT1+ 51 51 51 51 DIS SRN0J-7-GP RN8 LCD_TXBOUT2LCD_TXBOUT2+ LCD_TXAOUT2LCD_TXAOUT2+ 1 2 3 4 8 7 6 5 DIS SRN0J-7-GP RN6 LCD_TXBOUT0+ LCD_TXBOUT0LCD_TXBOUT1LCD_TXBOUT1+ 1 2 3 4 8 7 6 5 SRN0J-7-GP 1 USBPP10_R 1 VDDR3 27,58 INT_MIC1 1 3D3V_S0 3D3V_S0 1 2 AMIC1 3 1 2 4 EC11 2nd = 69.50007.981 2 EC73 DY SC22P50V2JN-4GP 2 EC72 DY SC22P50V2JN-4GP 12 12 ACES-CON2-3-GP-U RN19 SRN2K2J-1-GP DIS M92_LCD_CLK M92_LCD_DAT 51 M92_LCD_CLK 51 M92_LCD_DAT RN16 CCD_PWR -1 090213 6 1 2 3 4 5 7 2 1 9 NB_LCD_CLK 9 NB_LCD_DAT CCD1 R188 2 0R0402-PAD 1 USBPN10_R 2 1 USBPP10_R R189 0R0402-PAD USBPN10 USBPP10 20.F0825.002 2ND = 20.F1396.002 RN20 SRN2K2J-1-GP UMA 4 3 FUSE-1A6V-2-GP 69.50007.721 2 1 USBPN10_R 2 MLVG0402220NV05BP-GP-U 2 1 C11 SCD1U16V2ZY-2GP SC4D7U10V5ZY-3GP 2 C493 1 4 3 -1 090223 F3 CCD_PWR 1 2 DIS CCD_PWR CCD_PWR USBPN10_R USBPN10_R 58 USBPP10_R USBPP10_R 58 3 4 SRN0J-10-GP-U UMA 58 FOX-CON5-3-GP-U1 20.F0411.005 Layout 40 mil 2ND = 20.F1396.005 3D3V_S0 LCDVDD U1 51 LCDVDD_ON RN45 SC4D7U6D3V3KX-GP DY 2 1 2 C492 DY 4 3 SRN33J-5-GP-U BRIGHTNESS 34 BLON_OUT 34 SJV50 1 C490 SC100P50V2JN-3GP G5285T11U-GP 74.05285.07F C491 Wistron Corporation R469 100KR2J-1-GP 2 4 1 2 1 IN#4 BRIGHTNESS_CN BLON_OUT_R 2 5 SC100P50V2JN-3GP C1 SC4D7U6D3V3KX-GP DY SCD1U16V2ZY-2GP UMA IN#5 1 C2 EN GND OUT 1 1 2 3 2 R1 0R2J-2-GP 1 1 2 2 9 GMCH_LCDVDD_ON -1 090219 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size LED & LCD CONN / CCD Document Number Rev -1 SJV50-PU Date: Wednesday, February 25, 2009 Sheet 18 of 59 A B C D E RN12 GMCH_RED 9 GMCH_GREEN 9 GMCH_BLUE 9 CRT1 DY CRT_VSYNC1 C108 CLK_DDC1_5 DY 2 SC18P50V2JN-1-GP 20081230 Modify C43 13 14 15 CRT_G CRT_B 5V_CRT_S0 SCD01U16V2KX-3GP VIDEO-15-58-GP-U SC18P50V2JN-1-GP 20.20431.015 SC100P50V2JN-3GP 3D3V_S0 ED8 R32 2 C98 SCD1U16V2ZY-2GP DY 6 C101 SC18P50V2JN-1-GP SC18P50V2JN-1-GP DY 1 C100 2 1 SRN0J-10-GP-U 5 5V_S0 3 3 CRT_HSYNC1_R U7A TSAHCT125PW-GP 73.74125.L13 2 1 3 4 5V_CRT_S0 CRT_HSYNC1 CRT_VSYNC1 F1 1 FUSE-1D1A6V-4GP-U SRN33J-5-GP-U 3D3V_S0 2 69.50007.691 2ND = 69.50007.771 3D3V_S0 RN13 SRN2K2J-1-GP 2ND = 73.74125.L12 CRT_VSYNC1_R 3RD = 73.74125.01B U7B TSAHCT125PW-GP 73.74125.L13 2ND = 73.74125.L12 3RD = 73.74125.01B D10 CH551H-30PT-GP 2 3D3V_S0 RN50 SRN10KJ-6-GP 4 3 14 3 4 2 9 GMCH_HSYNC 9 GMCH_VSYNC 2 1 BAV99-5-GP DIS 51 M92_CRT_CLK 51 M92_CRT_DAT 1 2 3 4 2 SRN0J-10-GP-U UMA RN23 1 SC100P50V2JN-3GP 1 2 HSYNC_1 VSYNC_1 7 3 4 4 2 1 DY 3 C33 RN15 7 51,54 M92_HSYNC 51,54 M92_VSYNC CRT_DEC_R 83.R5003.C8F RN56 DIS 1 470R2J-2-GP 1 14 2 2 3 1 1 CRT_DEC# 2 1 5V_S0 34 4 C53 17 DY 2 1 1 2 2 2 2 2 1 1 1 1 2 2ND = 68.00230.021 SC100P50V2JN-3GP C69 SC12P50V2JN-3GP 150R2F-1-GP DY C82 SC12P50V2JN-3GP 150R2F-1-GP DY C93 68.00119.081 SC12P50V2JN-3GP 150R2F-1-GP DY DY CRT_B 1 2 SBK160808T-100Y-N-GP C70 SC3P50V2CN-1-GP R44 C83 SC3P50V2CN-1-GP R46 SC3P50V2CN-1-GP R49 1 CRT_B_1 C94 1 DIS CRT_BLUE 2 L9 C107 1 2ND = 68.00230.021 CRT_HSYNC1 CRT_R 7 2 8 3 9 4 10 5 12 C95 1 68.00119.081 SRN0J-7-GP 51 DAT_DDC1_5 CRT_G 1 2 SBK160808T-100Y-N-GP 1 CRT_G_1 2 CRT_GREEN L14 1 51 8 7 6 5 6 1 11 2ND = 68.00230.021 2 4 68.00119.081 1 2 3 4 CRT_R 1 2 SBK160808T-100Y-N-GP RN11 1 CRT_R_1 UMA CRT_RED 2 51 16 L16 SRN0J-7-GP 8 7 6 5 8 7 6 5 2 1 2 3 4 Q15 RN53 2 1 3 4 DAT_DDC1_5_Q SRN0J-10-GP-U UMA RN51 9 NB_CRT_CLK 9 NB_CRT_DAT 2 2 1 3 4 CRT_DEC# 4 3 5 2 6 1 DAT_DDC1_5 2N7002DW-1-GP CLK_DDC1_5_Q CLK_DDC1_5 2 SRN0J-10-GP-U 1 1 Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size CRT/TV Connector Document Number SJV50-PU Date: Wednesday, February 25, 2009 A B C D Sheet E Rev -1 19 of 59 5 4 3 2 1 HDMI1 HDMI_SL TMDS_A_TX2+ C661 1 HDMI_SL TMDS_A_TX2- C662 1 HDMI_TX0+ 2SCD1U16V2KX-3GP HDMI_TX0- 2SCD1U16V2KX-3GP HDMI_TX1+ 2SCD1U16V2KX-3GP HDMI_TX1- 2SCD1U16V2KX-3GP HDMI_TX2+ 2SCD1U16V2KX-3GP HDMI_TX2- 20 HDMI_TX2+ HDMI_TX1HDMI_TX0+ HDMI_TX0HDMI_TXC+ 5V_S0 TP120 TPAD14-GP RN14 2 1 3 4 5V_S0 1 2 R286 4K7R2J-2-GP 2 R289 2 4K7R2J-2-GP 3D3V_S0 SA_20081103 HDMI_SL 2 11 15 21 26 33 40 46 Non-Level shift & DIS mount RN55,U40 U40 3D3V_S0 23 22 HDMI_TX2HDMI_TX2+ 8,51 TMDS_A_TX18,51 TMDS_A_TX1+ 41 42 IN_D2IN_D2+ OUT_D2OUT_D2+ 20 19 HDMI_TX1HDMI_TX1+ 8,51 TMDS_A_TX08,51 TMDS_A_TX0+ 44 45 IN_D3IN_D3+ OUT_D3OUT_D3+ 17 16 HDMI_TX0HDMI_TX0+ 47 48 IN_D4IN_D4+ OUT_D4OUT_D4+ 14 13 HDMI_TXCHDMI_TXC+ 2 OUT_D1OUT_D1+ Recommended Equalization: [PC1,PC0]=01, 4dB PC0 PC1 3 4 DY REXT_HDMI 3D3V_S0 UMA_HDMI PS8101_OE# DDC_EN_PS8101 2 1 6 10 25 32 PC0 PC1 REXT RT_EN# OE# DDC_EN 2 UMA_HDMI 71.P8101.003 1A 2A 1OE 2OE VCC 8 3 6 1B 2B GND 4 DDC_OE 1 7 TSCBTD3305CPWR-GP 73.03305.A0B 2ND = 73.53305.A0B HDMI_SL B 8 9 7 PS8101_HPD 30 29 28 HDMI_A_HPD_CN TDMS_A_DAT TDMS_A_CLK HDMI_NB_DAT 9 HDMI_NB_CLK 9 1 2 R265 1KR2J-1-GP HDMI_NB_HPD 9 UMA_HDMI 1 R53 10KR2J-3-GP 2 HDMI_M92_HPD 51 DIS R52 100KR2J-1-GP DIS UMA_HDMI 2 R303 20KR2J-L2-GP 5V_S0 2 5 UMA_HDMI 1 1 PS8101-GP R267 499R2F-2-GP HPD_SINK SDA_SINK SCL_SINK RN18 SRN1K5J-GP GND GND GND GND GND GND GND GND GND GND GND R302 4K7R2J-2-GP 3D3V_S0 SDA SCL HPD TDMS_A_CLK TDMS_A_DAT 1 1 4K7R2J-2-GP 1 UMA_HDMI 51 HDMI_M92_CLK 51 HDMI_M92_DAT 1 5 12 18 24 27 31 36 37 43 49 UMA_HDMI 4K7R2J-2-GP C RN55 SRN2K2J-2-GP PS8101_VDD35 1 PS8101_VDD34 1 2 1 SCD1U10V2KX-4GP SCD1U10V2KX-4GP 2 1 2 1 SCD1U10V2KX-4GP 2 1 SCD1U10V2KX-4GP 1 1 2 2 1 2 1 1 1 1 2 2 2 VCC VCC VCC VCC VCC VCC VCC VCC S 1 22.10296.061 2ND = 22.10296.011 IN_D1IN_D1+ 3D3V_S0 SA_20081107 23 38 39 R269 2 R268 2 BAV99PT-GP-U 21 8,51 TMDS_A_TX28,51 TMDS_A_TX2+ 8,51 TMDS_A_TXC8,51 TMDS_A_TXC+ B 1 D16 DY DY D 2 1 C629 U10 R62 100KR2J-1-GP DY 3 SA_20081104 84.27002.W31 2ND = 84.2N702.E31 HDMI_SL HDMI_SL 2 HDMI_A_HPD_CN SCD1U16V2KX-3GP C115 3D3V_S0 Q17 2N7002-11-GP G D 5V_S0 SKT-HDMI19P-25-GP UMA_HDMI 2 C670 UMA_HDMI UMA_HDMI UMA_HDMI 499R2F-2-GP R272 HDMI_SL 499R2F-2-GP R274 HDMI_SL 499R2F-2-GP R279 HDMI_SL 499R2F-2-GP R280 HDMI_SL 499R2F-2-GP R284 HDMI_SL 499R2F-2-GP HDMI_SL R287 HDMI_SL 499R2F-2-GP R304 R299 HDMI_SL 499R2F-2-GP TMDS_R C641 5V_S0_HDMICN HDMI_A_HPD_CN DY 3D3V_S0 Non-Level shift change to 715 ohm 5V_S0 L18 1 2 FCM1608CF-221T02-GP EC39 SC220P50V2JN-3GP SC220P50V2JN-3GP 2 1 1 EC38 DY 2 66.15236.04L C654 HDMI_TXCHDMI_A_CEC 1 TDMS_A_CLK TDMS_A_DAT SRN1K5J-GP C 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 HDMI_TX2HDMI_TX1+ HDMI_SL Non-Level shift & DIS mount 0.1uF 1 8 7 6 5 HDMI_SL TMDS_A_TX1- C658 1 D 2SCD1U16V2KX-3GP 22 1 2 3 4 HDMI_SL TMDS_A_TX1+ C656 1 HDMI_TXC- 4 3 HDMI_SL TMDS_A_TX0- C653 1 HDMI_TXC+ 2SCD1U16V2KX-3GP 1 2 HDMI_SL TMDS_A_TX0+ C644 1 2SCD1U16V2KX-3GP 35 34 HDMI_SL TMDS_A_TXC- C639 1 NC#35 NC#34 TMDS_A_TXC+ C638 1 20090114_SB HDMI_SL D 2 SA_20081104 PS8101_OE# HDMI_A_HPD_CN RN71 HDMI_NB_DAT HDMI_NB_CLK 84.27002.W31 2ND = 84.27002.N31 G S 2 1 3 4 HDMI_M92_DAT HDMI_M92_CLK SJV50 A SRN0J-10-GP-U UMA_HDMI HDMI_SL 2 HDMI_NB_HPD R238 10KR2J-3-GP HDMI_SL 1 R297 Wistron Corporation HDMI_A_HPD_CN 2 5K1R2J-4-GP Non-Level shift mount RN71,R297,R238 1 A Q16 2N7002-11-GP 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size A3 -1 090224 HDMI CONNECTOR Document Number Rev SJV50-PU Date: Wednesday, February 25, 2009 5 4 3 2 Sheet 1 -1 20 of 59 SATA HDD Connector SATA1 13 13 SATA_TXP0 SATA_TXN0 C1431 C1441 SCD01U50V2KX-1GP 2 SCD01U50V2KX-1GP 2 13 13 SATA_RXN0 SATA_RXP0 C1411 C1421 SCD01U50V2KX-1GP 2 SCD01U50V2KX-1GP 2 24 NP2 22 SATA_TXP0_C 21 SATA_TXN0_C 20 19 SATA_RXN0_C 18 SATA_RXP0_C 17 16 5V_S0 A 1 1 EC78 2 SC10U10V5ZY-1GP 2 SSM24PT-GP DY DY-RF C620 SC47P50V2JN-3GP TC14 SCD1U25V3ZY-1GP D12 2 1 K PWR TRACE 100mil 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 NP1 23 ALP-CON22-GP-U1 20.F0754.022 ED2 SATA_RXP0_C SATA_RXN0_C SATA_TXP0_C SATA_TXN0_C 2ND = 62.10065.151 DY 3 ED1 2 SA_20081112 DY 3 2 SJV50 Wistron Corporation 5V_S0 4 1 5V_S0 4 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. 1 PRTR5V0U2X-GP PRTR5V0U2X-GP 83.5V0U2.0A3 83.5V0U2.0A3 Title Size HDD Document Number Rev -1 SJV50-PU Date: Wednesday, February 25, 2009 Sheet 21 of 59 5 4 3 2 1 SATA ODD Connector D D P2 P3 +5V +5V 13 13 SATA_TXN1 SATA_TXP1 C4391 C4401 2SCD01U50V2KX-1GP 2SCD01U50V2KX-1GP SATA_TXN1_C S3 SATA_TXP1_C S2 AA+ 13 13 SATA_RXN1 SATA_RXP1 C4411 C4421 2SCD01U50V2KX-1GP 2SCD01U50V2KX-1GP SATA_RXN1_C S5 SATA_RXP1_C S6 BB+ MD DP P4 P1 GND GND GND GND GND GND GND S1 S4 S7 P5 P6 8 9 SKT-SATA7P+6P-30-GP-U 62.10065.441 2ND = 62.10065.541 ODD_MD ODD_DP TP198 TP201 1 1 TPAD14-GP TPAD14-GP C 2 2 2 2 1 ODD1 R171 10KR2J-3-GP 1 A EC58 SC47P50V2JN-3GP C DY-RF TC6 SC10U10V5ZY-1GP SSM24PT-GP DY C431 SCD1U16V2ZY-2GP D6 1 1 K 5V_S0 DY ED3 3 DY SATA_RXP1_C SATA_TXP1_C SATA_RXN1_C B SATA_TXN1_C B ED4 2 3 DY SA_20081112 2 SJV50 Wistron Corporation A 5V_S0 4 1 4 5V_S0 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. 1 Title PRTR5V0U2X-GP PRTR5V0U2X-GP 83.5V0U2.0A3 83.5V0U2.0A3 Size ODD Document Number Rev -1 SJV50-PU Date: Wednesday, February 25, 2009 5 4 3 2 Sheet 22 of 1 59 A 5 4 3 2 1 D D BLUETOOTH MODULE 3D3V_BT_S0 3D3V_S0 U25 3D3V_BT_S0 EC66 DY SCD1U16V2ZY-2GP OUT GND NC#3 IN 5 EN 4 1 DY C486 SC4D7U10V5ZY-3GP 2 C BLUETOOTH_EN 34 G5240B1T1U-GP 2 1 C 1 2 3 74.05240.A7F 2ND = 74.09711.A7F EC34 put near BT1 all USB put one choke near connector by EMI request USB_5+ 58 USB_5- USB_5- 58 BT1 5 1 2 3 4 6 ETY-CON4-21-GP-U B USB_5+ 3D3V_BT_S0 58 USB_5+ USB_5- R184 1 0R0402-PAD 2 1 2 R185 0R0402-PAD USBPP5 12,58 USBPN5 12,58 -1 090213 B 20.F0984.004 2ND = 20.D0197.104 SJV50 Wistron Corporation A 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title BLUETOOTH Size Document Number SJV50-PU Sheet Wednesday, February 25, 2009 Date: 5 4 3 2 Rev -1 23 of 1 59 A Size：W:5.8 * H:6.3 桶狀。 5V_USB1_S5 5V_USB1_S5 1 1 SCD1U16V2ZY-2GP DY EC86 SC1000P50V3JN-GP-U 2ND = 77.92271.021 3RD = 79.22710.E0L 5V_USB1_S5 USB_OC#0 12 USB1 1 2 3 4 5 6 7 8 USBPN6 USBPP6 1 EC81 1 EC82 SCD1U25V2ZY-1GP 12 12 SCD1U25V2ZY-1GP 3RD = 74.08015.07G DY EC80 2 2 1 74.09715.079 2ND = 74.00547.A79 2 1 2 1 34,58 USB_PWR_EN# DY EC94 RT9715DGF-GP SCD1U16V2ZY-2GP 2 EC97 SC47P50V2JN-3GP DY-RF SC47P50V2JN-3GP C777 SC4D7U10V3KX-GP VOUT VOUT VOUT FLG# 2 TC20 SE220U6D3VM-7GP 79.22710.6AL EC95 GND VIN VIN EN# 8 7 6 5 2 1 DY-RF U42 1 2 3 4 1 100 mil 5V_S5 2 DY 2 DY VBUS DD+ GND SHELL#5 SHELL#6 SHELL#7 SHELL#8 SKT-USB-172-GP 22.10218.T31 2ND = 22.10254.031 3RD = 22.10254.041 5V_USB1_S5 20081231 change conn. USB3 USBCN1 14 13 12 11 10 9 8 7 6 5 4 3 2 34,58 USB_PWR_EN# 2 DY 1 C776 2 EC96 SC1U16V3ZY-GP SCD1U16V2ZY-2GP 1 5V_S5 EC90 EC87 DY 1 USBPN8 USBPP8 DY 2 12 12 1 USBPN7 USBPP7 USBPN0 USBPP0 2 12,58 12,58 12 12 SCD1U25V2ZY-1GP USB_OC#3 SCD1U25V2ZY-1GP 16 12,58 1 2 3 4 5 6 7 8 VBUS DD+ GND SHELL#5 SHELL#6 SHELL#7 SHELL#8 SKT-USB-172-GP 22.10218.T31 2ND = 22.10254.031 3RD = 22.10254.041 1 15 ACES-CON14-8-GP 20.F0866.014 PD UMA Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size USB Connector Document Number SJV50-PU Date: Wednesday, February 25, 2009 Sheet Rev -1 24 of 59 5 4 3 2 1 D 3D3V_LAN_S5 DC#38 DC#52 DC#68 36 BIASVDD_G 2 L17 0R3-0-U-GP 1 1 LAN_AVDDH XTALVDD_G XTALVDDH 23 AVDDH AVDDH 48 42 AVDDL_G 39 45 51 AVDDL AVDDL AVDDL GPHY_PLLVDD 35 GPHY_PLLVDDL TRD3_N TRD3_P 49 50 MDI3MDI3+ 26 26 TRD2_N TRD2_P 47 46 MDI2MDI2+ 26 26 TRD1_N TRD1_P 43 44 MDI1MDI1+ 26 26 TRD0_N TRD0_P 41 40 MDI0MDI0+ 26 26 LINKLED# SPD100LED# SPD1000LED# TRAFFICLED# 2 1 67 66 C597 DY LAN_AVDDH C603 Place PLLVDD/AVDDL CKT as close to chip as possible C 3D3V_AUX_S5 1 C 2 38 52 68 6 56 61 15 19 BIASVDDH VDDC_IO VDDC_IO VDDC VDDC VDDC VDDC 2 2 C592 SCD1U10V2KX-4GP 1 1 5 55 13 20 34 60 SCD1U10V2KX-4GP DY VDDIO VDDIO VDDIO VDDIO VDDIO VDDC_IO_12 1 2 SCD1U10V2KX-4GP L11 0R3-0-U-GP 2 1 BIASVDD_G 2 TP77 1 2 1 U5 1D2V_LAN_S5 C622 SCD1U10V2KX-4GP SCD1U10V2KX-4GP 2 C66 DY 2 2 1 1 TP76 1 SCD1U10V2KX-4GP C578 SCD1U10V2KX-4GP SCD1U10V2KX-4GP 2 TP64 1 LAN_VDC3 SCD1U10V2KX-4GP 1 SCD1U10V2KX-4GP C87 1 LAN_VDC2 C570 SCD1U10V2KX-4GP C84 2 C579 SCD1U10V2KX-4GP 2 C611 SC4D7U10V5ZY-3GP 2 C627 LAN_VDC1 C60 3D3V_LAN_S5 3D3V_S5 R234 0R0603-PAD 1 2 1 1 1 1D2V_LAN_S5 L6 0R3-0-U-GP 2 1XTALVDD_G 1 1 DY 2 1 2 1 C604 SCD1U10V2KX-4GP 2 C80 SCD1U10V2KX-4GP SCD1U10V2KX-4GP D C601 2 C605 SC4D7U10V5ZY-3GP 1 3D3V_LAN_S5 ENERGY_DET 3D3V_LAN_S5 10M/100M/1G_LED# 26 1 LAN_ACT_LED# 26 U39 59 3D3V_LAN_S5 3 2ND = 71.05784.M03 C564 1 1 2 GND 69 71.05764.M01 16 L5 0R3-0-U-GP 1 PCIE_SDSVDD 1 1 C44 SCD1U10V2KX-4GP BCM5764MKMLG-GP SUPER_IDDQ SC10U10V5ZY-1GP 20081204 2 2 Q8 1D2V_LAN_S5 BCP69-GP 84.00069.B1B 2ND = 84.DCP69.01B 3RD = 84.00069.A1B 2 C40 C45 C584 B C50 C576 SCD1U10V2KX-4GP 1 CLKREQ# C580 C591 SC4D7U10V5ZY-3GP LAN_1D2Q C628 2 2 R48 0R0603-PAD 2 REGCTL12 SCD1U10V2KX-4GP 14 SC4D7U10V5ZY-3GP REGCTL12 1 2 R233 1K24R2F-GP L4 0R3-0-U-GP 1 PCIE_PLLVDD 1 2 2 C607 1 1 1 2 1 C71 1 18 2 RDAC 17 SCD1U10V2KX-4GP 37 VDDC_IO REGOUT12_IO 2 XTALO XTALI 1 SMB_CLK SMB_DATA 22 21 2 R457 1 LAN_CLKREQ# 11 1KR2J-1-GP L42 0R3-0-U-GP 1 GPHY_PLLVDD VDDC_IO_12 1 2 1 1RDAC 2 2 C600 SCD1U10V2KX-4GP 2ND = 82.30020.791 C48 SC15P50V2JN-2-GP 82.30020.851 R466 4K7R2J-2-GP SC4D7U10V5ZY-3GP 2 2LAN_XO 200R2J-L1-GP R253 4K7R2J-2-GP 20090107 SB modify VAUX_PRSNT VMAIN_PRSNT LOW_PWR XTAL-25MHZ-102-GP C47 SC15P50V2JN-2-GP 1 1 R36 2 R252 4K7R2J-2-GP C612 2 ENERGY_DET AVDDL_G SCLK SI SO CS# 1 65 63 64 62 1 2 R258 1VAUX_PRESENT54 VMAINPRSNT 53 1KR2J-1-GP LOW_PWR 3 2 R240 1 0R2J-2-GPDY LAN_SMB_CLK 58 R256 0R2J-2-GP 1 DY 2 LAN_SMB_DATA 57 1 DY 2 R257 0R2J-2-GP LAN_XO_R X1 1 2LAN_XI 1D2V_LAN_S5 L46 0R3-0-U-GP 2 1 ENERGY_DET 34 2 R259 1 1KR2J-1-GP KBC_THERM_CLK KBC_THERM_DAT 72.24C02.R01 SCD1U10V2KX-4GP 32,33,34,38,51,58 3D3V_LAN_S5 AT24C02BN-SH-T-GP SC4D7U10V5ZY-3GP 20081218_SB rename 32,33,34,38,51,58 LOW_PWR R51 10KR2J-3-GP 1 2 2 SCLK/EECLK SI SO/EEDATA CS# 3D3V_S0 34 EE_WP SCLK SO 2ND = 72.24C02.M01 3D3V_LAN_S5 B 8 7 6 5 1 TP67 TP69 TP73 VCC WP SCL SDA 2 UART_MODE 1 EE_WP 1 GPIO_0 1 2 2 9 7 4 A0 A1 A2 GND SCD1U10V2KX-4GP 3 CLK_PCIE_LAN 3 CLK_PCIE_LAN# PCIE_TXD_P PCIE_TXD_N PCIE_RXD_P PCIE_RXD_N WAKE# PERST# PCIE_REFCLK_P PCIE_REFCLK_N UART_MODE GPIO_1/SERIAL_DI GPIO_0/SERIAL_DO 1 2 3 4 SC4D7U10V5ZY-3GP SC150P50V2JN-3GP C595 LAN_RST 26 25 31 32 12 10 29 28 TP68 10KR2J-3-GP DY R255 2 12 PCIE_WAKE# PCIE_RXDP PCIE_RXDN 1 1 PLT_RST1#_B 1 C64 1 C65 GPIO_2 SCD1U10V2KX-4GP 2 R232 1 0R2J-2-GP 1 11,31,32,34,35,50,58 SCD1U10V2KX-4GP 2 SCD1U10V2KX-4GP 2 PCIE_RXP1 PCIE_RXN1 PCIE_TXP1 PCIE_TXN1 8 2 8 8 8 8 GPIO_2 C77 SCD1U10V2KX-4GP 2 1 PCIE_VDDL PCIE_VDDL 2 33 24 10KR2J-3-GP DY R254 EEPROM 1 PCIE_PLLVDDL PCIE_PLLVDDL 2 PCIE_SDSVDD 30 27 2 PCIE_PLLVDD R66 change to Bead for Transmitter Distortion A A SJV50 Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title BCM 5764 Size A2 Date: 5 4 3 2 Document Number Rev SJV50-PU Wednesday, February 25, 2009 1 -1 Sheet 25 of 59 A B C D E LAN Connector RN47 3D3V_LAN_S5 3D3V_LAN_S5 1 2 4 3 CONN_PWR_2 CONN_PWR_1 SRN220J-1-GP 25 10M/100M/1G_LED# 4 10M/100M/1G_LED# EC17 1 DY 2 SC1KP50V2KX-1GP CONN_PWR_2 EC74 1 DY 2 SCD1U10V2KX-4GP CONN_PWR_1 EC75 1 DY 2 SCD1U10V2KX-4GP LAN_ACT_LED# EC9 DY 2 SC1KP50V2KX-1GP 1 RJ45 -1 090217 9 CONN_PWR_2 RJ45_1 RJ45_2 RJ45_3 RJ45_4 RJ45_5 RJ45_6 RJ45_7 RJ45_8 CONN_PWR_1 25 LAN_ACT_LED# A1 A2 A3 A2(+),A1(-):GREEN 4 A2(+),A3(-):ORANGE 1 2 3 4 5 6 7 8 B1 B2 B1(+),B2(-):YELLOW 10 RJ45-130-GP-U1 GIGA Lan Transformer 22.10277.041 XF1 XRF_TDC_1 25 MDI0+ 2 23 25 MDI0- 3 1 22 24 25 MDI1+ 4 5 21 20 25 MDI1- 6 19 25 MDI2+ 8 17 25 MDI2- 9 7 16 18 25 MDI3+ 10 11 15 14 25 MDI3- 12 13 XRF_TDC_2 3 DY 1 1 DY SCD01U16V2KX-3GP SCD01U16V2KX-3GP 2 C76 2 C75 XRF_TDC_3 XRF_TDC_4 2 2 C73 SCD01U16V2KX-3GP 1.route on bottom as differential pairs. 2.Tx+/Tx- are pairs. Rx+/Rx- are pairs. 3.No vias, No 90 degree bends. 4.pairs must be equal lengths. 5.6mil trace width,12mil separation. 6.36mil between pairs and any other trace. 7.Must not cross ground moat,except RJ-45 moat. C74 SCD01U16V2KX-3GP 2 DY 1 1 DY RJ45_1 RJ45_2 MCT1 MCT2 3 RJ45_3 RJ45_6 RJ45_4 RJ45_5 MCT3 MCT4 RJ45_7 RJ45_8 2 XFORM-275-GP 68.89240.30A 2ND = 68.IH601.301 4 3 2 1 MCT4 MCT3 MCT2 MCT1 RN48 SRN75J-1-GP SJV50 1 RJ45 PIN TD+ --> TX+ RJ45-1 TD- --> TX- RJ45-2 RD+ --> RX+ RJ45-3 RD- --> RX- RJ45-6 5 6 7 8 10/100 LAN Transformer C14 LAN_TERMINAL 1 1 Wistron Corporation 2 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. SC1KP2KV8KX-GP Title LAN Connector Size A3 Document Number Rev A B C D -1 SJV50-PU Date: Wednesday, February 25, 2009 Sheet E 26 of 59 A B C D E 5V_S0 RN69 AUDIO_BEEP 4 3 C821 1 2 MICBIASC PORTC_L 20K PORTC_R 18 16 17 PORTD_L 39.2K PORTD_R 27 28 29 R470 100KR2J-1-GP AUDIP_PC_BEEP 12 SPDIF AUD_GPIO2 AUD_GPIO1 28 EAPD# PC_BEEP 48 S/PDIF C804 2 C803 2 1 SC2D2U10V3KX-1GP 1 SC2D2U10V3KX-1GP MICBIASB MIC1-L_PORT-B C813 2 MIC1-R_PORT-B C806 2 1 SC2D2U10V3KX-1GP 1 SC2D2U10V3KX-1GP 45 46 47 GPIO2 GPIO1 EAPD#/GPIO0 1 2 DMIC_CLOCK DMIC_1/2 14 15 MONO STEREO_L STEREO_R 29 30 31 13 VREF 24 FLY_P FLY_N 39 37 VREF_LO VREF_HI RESERVED#32 RESERVED#33 22 23 32 33 CX_SENSE DY C798 Populate Omit Omit -12dB Populate Omit -18dB Omit Populate 25 38 7 41 49 1 1 1 2 2 2 R381 5K1R2F-2-GP 1 CX_SENSE Default gain is -6dB without populating the 10K-ohms pull-down resistors going to GPIO1 and GPIO2. C802 C795 1 AUD_GPIO1 2 Populate -6dB 1 1 DY R383 0dB 2 C800 2 AVSS AVSS DVSS DVSS GND AUD_GPIO2 2 R388 10KR2J-3-GP 3 3VA_S0 10K GPIO RESISTORS R388 29 29 -1 090219 AUD_AVREF C797 1 2SC1U10V3KX-3GP SC1U10V3KX-3GP R383 10KR2J-3-GP GAIN AUD_MICIN_L AUD_MICIN_R SOUNDL 28 SOUNDR 28 PC BEEP GAIN CONTROL -1 090219 2 C807 SC10U10V5ZY-1GP R467 0R2J-2-GP 2 SENSEA DY INT_MIC1 18,58 20090113_SB SC1U10V3KX-3GP CX20561-15Z-GP R386 4K7R2F-GP 1 2 1 PORTB_L 10K PORTB_R CX20561 2 R384 4K7R2F-GP 1 2 FRONTL 29 FRONTR 29 MIC_L MIC_R SC1U10V3KX-3GP SRN1KJ-7-GP 1 2 AVDD AVDD AVEE 19 20 21 C799 SC10U10V5ZY-1GP 2 1 1 2 DIB_P DIB_N MICBIASB MIC_L MIC_R 74.09091.J3F 2ND = 74.09198.G7F R385 1KR2J-1-GP 1 1 2 43 42 PORTA_L 5.11K PORTA_R 4 G9091-330T11U-GP SCD1U10V2KX-4GP KBC_BEEP ACZ_SPKR 1 BIT_CLK SYNC SDATA_IN SDATA_OUT 4 3VA_S0 1 34 12 2 RESET# 6 10 8 5 5 NC#4 C794 SC10U10V5ZY-1GP 2 1 2 3 SCD1U25V2ZY-1GP DY 12,30 ACZ_SYNC 12 ACZ_SDATAIN0 EC10612,30 ACZ_SDATAOUT 11 VOUT 1 1 R402 2ACZ_BITCLK_1 0R0402-PAD 1 2 R403 33R2J-2-GP 34 35 VIN GND EN 2 ACZ_RST# 26 40 36 9 4 3 44 VDD_IO DVDD_1_8 DVDD_3_3 DVDD 12,30 2 1 1 2 -1 090219 C790 SC1U10V3KX-3GP 300mA SCD1U10V2KX-4GP U50 C789 SC10U10V5ZY-1GP DY C815 SCD1U10V2KX-4GP 12 ACZ_BITCLK 1 1 2 1 SCD1U10V2KX-4GP 2 SC10U10V5ZY-1GP 2 AUD_AVEE C782 SCD1U10V2KX-4GP 2 C780 DVDD_IO -1 090213 1 2 3 C820 SC10U10V5ZY-1GP SCD1U10V2KX-4GP SC10U10V5ZY-1GP 1 R407 2 0R0603-PAD 3D3V_S0 C819 C801 2 1 1 DY C818 U47 3VA_S0 1 R392 2 0R0603-PAD 4 3VA_S0 VDD_20561 1 -1 090213 2 3D3V_S0 2 R400 5K1R2F-2-GP 1 2 LINEOUT_JD# 29 MIC_JD# 29 R380 20KR2F-L-GP 1 1 SJV50 Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size Date: A B C D AZALIA CODEC - CX20561 Document Number Rev SJV50-PU Sheet Wednesday, February 25, 2009 E -1 27 of 59 5 4 3 2 1 AUDIO OP AMPLIFIER 1 3D3V_S0 R390 10KR2J-3-GP D 1 2 2 C32 SC1U16V3ZY-GP SC4D7U10V5ZY-3GP 1 BYPASS C10 R_LINE_IN RIN+ L_LINE_IN LIN+ 1 2 C13 SC4D7U10V5ZY-3GP 2 U4 2 11 VCC VCC BYPASS SHUTDOWN# 5 14 7 8 15 16 RINRIN+ LINLIN+ LVO1 LVO2 RVO1 RVO2 1 4 12 9 VSS VSS 3 10 GND 17 C 6 13 NC#6 NC#13 1454_SHUTDOWN SPKR_LSPKR_L+ SPKR_RSPKR_R+ D 2 5VA_OP_S0 SPKR_LSPKR_L+ SPKR_RSPKR_R+ 2 29 29 29 29 DY R387 1 0R2J-2-GP AMP_SHUTDOWN# 34 R391 1 0R2J-2-GP EAPD# 27 -1 090219 C G1454LR41U-GP 74.01454.A13 -1 090220 27 SOUNDR R15 1 2L_LINE_IN_1 1 2 C792 18KR2F-GP SCD47U16V3KX-1GP R16 1 2R_LINE_IN_11 2 C791 18KR2F-GP SCD47U16V3KX-1GP R21 1 2RIN+_1 1 2 20KR2F-L-GP C21 SCD47U16V3KX-1GP R17 1 2LIN+_1 1 2 C22 20KR2F-L-GP SCD47U16V3KX-1GP L_LINE_IN R_LINE_IN RIN+ L_LINE_IN R12 1 2 52K3R2F-L-GP SPKR_L- LIN+ R13 1 2 52K3R2F-L-GP SPKR_L+ R_LINE_IN R26 1 2 52K3R2F-L-GP SPKR_R- RIN+ R22 1 2 52K3R2F-L-GP SPKR_R+ 5V_S0 5VA_OP_S0 B G5 1 2 GAP-CLOSE-PWR LIN+ 1 SOUNDL 2 B 27 C9 SC4D7U10V5ZY-3GP PD UMA Wistron Corporation A 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title AUDIO AMP (G1454) Size Document Number Rev -1 SJV50-PU Date: Wednesday, February 25, 2009 5 4 3 2 Sheet 28 of 1 59 A 5 4 3 2 1 MIC IN MICIN1 L57 L58 1 PHONE-JK326-GP-U 22.10133.F61 MLVS0603M04-1-GP 1 2 MLVS0603M04-1-GP SRN1KJ-7-GP 4 3 DY 1 PHONE-JK336-GP 22.10133.G91 IN NC#3 GND OUT 3 2 1 G5240B2T1U-GP-U DY 74.05240.B7F 2ND = 74.09711.07F R379 2 DY 1 0R2J-2-GP 5V_SPDIF_S0 C 1 C783 EN# 5 DY C781 SCD1U16V2ZY-2GP L60 ERN1 3 2 SCD1U16V2ZY-2GP L59 5V_S0 4 2 LOUT_L+1 2 R472 5K1R2J-4-GP 1 1 FRONTL U44 TX LINEOUT_JD# 2 27 1 C FRONTR LED 5 4 LOUT_R+1 2 27 R471 5K1R2J-4-GP 1 2 SPDIF LOUT1 A B DRIVE IC C 1 5V_SPDIF_S0 2 -1 090219 27 D 2 2 R398 100R2J-2-GP 5 4 3 2 1 7 MIC_JD# 1 1 2 10KR2J-3-GP LINE OUT R389 27 2 1 DY 10KR2J-3-GP DY R401 AUD_MIC_R AUD_MIC_L MLVS0603M04-1-GP 27 AUD_MICIN_R 27 AUD_MICIN_L R393 100R2J-2-GP 1 2 1 2 MLVS0603M04-1-GP D 27 LINEOUT_JD# Internal Speaker B B -1 090216 SPKR1 5 SPKR_L- 2 ER1 2 2ER2 2ER3 ER4 EC7 1 EC6 DY DY SC1KP50V2KX-1GP SC1KP50V2KX-1GP SC1KP50V2KX-1GP SC1KP50V2KX-1GP 2 EC5 DY 1 1 EC4 DY 2 SPKR_L+ SPKR_RSPKR_R+ 2 SPKR_L+ SPKR_RSPKR_R+ 1 SPKR_L- 28 28 28 2 28 SPKR_L-_R 1 0R0402-PAD SPKR_L+_R 1 0R0402-PAD SPKR_R-_R 1 0R0402-PAD SPKR_R+_R 1 0R0402-PAD 1 2 3 4 6 ETY-CON4-21-GP-U 20.F0984.004 2ND = 20.D0197.104 use Varistor for ESD solution SJV50 A SPKR_L-_R SPKR_L+_R SPKR_R-_R SPKR_R+_R A 58 58 58 58 Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size Document Number Audio Jack SJV50-PU Date: Wednesday, February 25, 2009 5 4 3 2 Sheet 1 Rev -1 29 of 59 5 4 3 2 1 D D MDC 1.5 CONN MDC1 1 2 1 C471 SC22P50V2JN-4GP SC22P50V2JN-4GP 2 DY C470 2ND = 20.F0604.012 DY R180 1 DY EC63 ACZ_BITCLK_MDC 12 -1 090219 SCD1U25V2ZY-1GP 20.F0917.012 C483 1 R463 2 0R0402-PAD 100KR2J-1-GP TYCO-CONN12A-2-GP-U1 20090108_SB DY C ACZ_BITCLK_MDC_R SC4D7U10V5ZY-3GP 1 R179 470R2J-2-GP 3D3V_S5 2 2 12,27 ACZ_RST# 4 6 8 10 12 17 18 1 1 2 R178 39R2J-L-GP 12 ACZ_SDATAIN1 3 5 7 ACSDATAIN1_A 9 ACZ_RST#_MDC11 NP2 16 2 C ACZ_SYNC 15 14 2 2 12,27 13 NP1 1 1 12,27 ACZ_SDATAOUT B B SJV50 Wistron Corporation A 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title USB Connector Size Document Number SJV50-PU Sheet Wednesday, February 25, 2009 Date: 5 4 3 2 Rev -1 30 of 1 59 A 5 3 2 1 3D3V_D_S0 XD_CD# SD_WP SD_CD# SD_DAT1/XD_D4 XD_D5/MS_BS XD_D3/MS_D1 SD_DAT0/XD_D6/MS_D0 SD_DAT7/XD_D2/MS_D2 MS_INS# SD_DAT6/XD_D7/MS_D3 SD_CLK/XD_D1/MS_CLK SD_DAT5/XD_D0 SD_DAT4/XD_WP# XD_R/B# SD_DAT3/XD_WE# SD_DAT2/XD_RE# XD_ALE XD_CE# XD_CLE 1 R409 2 0R0603-PAD -1 090213 CARD_3D3V_S0 2 D C805 SC1U10V3KX-3GP U55 RTS5159-GR-GP 19 20 21 23 25 26 27 28 29 31 34 35 37 38 39 40 41 42 43 R435 0R3-0-U-GP 1 MODE_SEL SD_CMD K VBUS_LED R424 LED-W-23-GP 1 2 RREF 6K19R2F-GP RST# 1 R432 2 0R0603-PAD LED1 ADY 3D3V_D_S0 VREG 8 3V3_IN 33 11 D3V3 D3V3 45 36 14 2 44 MODE_SEL SD_CMD GPIO0 RREF RST# 5 4 -1 090213 24 22 NC#30 NC#7 NC#3 30 7 3 GND GND GND GND 6 12 32 46 EEDO EEDI C C825 SCD1U16V2ZY-2GP 10 DP DM 1 R394 2 VBUS_R 68R2F-GP DY 3D3V_S0 2 3D3V_D_S0 C824 SCD1U16V2ZY-2GP DY 2 C834 SCD1U16V2ZY-2GP 1 2 2 C833 SC4D7U6D3V5KX-3GP 1 1 3V_VBUS_S0 MS_D5 MS_D4 C 71.05159.00G R443 100KR2J-1-GP USBPN11 2 R419 1 0R0402-PAD 2 R422 1 0R0402-PAD DY USB_11+ USB_11- -1 090213 C849 SC1U10V3KX-3GP 3D3V_D_S0 2 470R2J-2-GP USBPP11 12 2 1RST# 2 PLT_RST1#_B 1 R440 25,32,34,35,50,58 12 12M_XO DY 20090108_SB XDAL_CTR 1 15 18 VREG 2 R410 1 0R0603-PAD 3D3V_S0 EESK EECS AV_PLL 17 16 CARD_3V3 1 XTLO XTLI -1 090213 9 AV_PLL XTAL_CTR 2 R431 1 0R0402-PAD 47 48 2 VREG C844 SCD1U16V2ZY-2GP 1 1 C826 SC1U10V3KX-3GP 2 2 DY SP1 SP2 SP3 SP4 SP5 SP6 SP7 SP8 SP9 SP10 SP11 SP12 SP13 SP14 SP15 SP16 SP17 SP18 SP19 2 C845 SC47P50V2JN-3GP D 1 1 1 MODE_SEL 13 3D3V_S0 4 2 R395 1 0R0402-PAD -1 090213 3 2 R160 1 12M_XO 0R0402-PAD CLK48_5159E -1 090213 CARD_3D3V_S0 1 1 2 C835 SC4D7U10V5ZY-3GP 2 4 IN1 CARD-READER (SD/MMC/MS/XD) B B C828 SCD1U16V2ZY-2GP CARD1 23 14 33 SD_VCC MS_VCC XD_VCC SD_DAT5/XD_D0_1 SD_CLK/XD_D1/MS_CLK SD_DAT7/XD_D2/MS_D2_1 XD_D3/MS_D1_1 SD_DAT1/XD_D4_1 XD_D5/MS_BS_1 SD_DAT0/XD_D6/MS_D0_1 SD_DAT6/XD_D7/MS_D3_1 8 9 26 27 28 30 31 32 XD_D0 XD_D1 XD_D2 XD_D3 XD_D4 XD_D5 XD_D6 XD_D7 XD_R/B# SD_DAT2/XD_RE#_1 XD_CE# XD_CLE XD_ALE SD_DAT3/XD_WE#_1 SD_DAT4/XD_WP#_1 XD_CD# 1 2 3 4 5 6 7 34 XD_R/B XD_RE XD_CE XD_CLE XD_ALE XD_WE XD_WP XD_CD_SW CARD_3D3V_S0 SD_DAT5/XD_D0 1 R423 2 0R0402-PAD XD_D3/MS_D1 1 R399 2 0R0402-PAD -1 090213 SD_DAT4/XD_WP# 1 R425 2 0R0402-PAD SD_DAT0 SD_DAT1 SD_DAT2 SD_DAT3 25 29 10 11 SD_DAT0/XD_D6/MS_D0_1 SD_DAT1/XD_D4_1 SD_DAT2/XD_RE#_1 SD_DAT3/XD_WE#_1 2 2 2 2 R405 R382 R438 R429 0R0402-PAD 1 0R0402-PAD 1 0R0402-PAD 1 0R0402-PAD 1 SD_CMD SD_CLK SD_CD_SW SD_WP_SW 12 24 36 35 SD_CMD_1 SD_CLK/XD_D1/MS_CLK SD_CD# SD_WP 2 R418 0R0402-PAD 1 MS_DATA0 MS_DATA1 MS_DATA2 MS_DATA3 19 20 18 16 SD_DAT0/XD_D6/MS_D0_1 XD_D3/MS_D1_1 SD_DAT7/XD_D2/MS_D2_1 SD_DAT6/XD_D7/MS_D3_1 MS_BS MS_INS MS_SCLK 21 17 15 XD_D5/MS_BS_1 MS_INS# SD_CLK/XD_D1/MS_CLK 4IN1_GND 4IN1_GND 13 22 GROUND GROUND 38 37 SD_DAT0/XD_D6/MS_D0 SD_DAT1/XD_D4 SD_DAT2/XD_RE# SD_DAT3/XD_WE# SD_CMD -1 090213 2 R406 0R0402-PAD 1 2 R408 0R0402-PAD 1 SD_DAT7/XD_D2/MS_D2 SD_DAT6/XD_D7/MS_D3 2 R396 0R0402-PAD 1 XD_D5/MS_BS SJV50 A A SD_DAT0/XD_D6/MS_D0 SD_DAT1/XD_D4 SD_DAT2/XD_RE# SD_DAT3/XD_WE# SD_WP SD_CD# SD_CMD SD_CLK/XD_D1/MS_CLK NP2 NP1 DY EC105 DY EC103 DY EC112 DY EC111 DY EC101 DY EC102 DY EC108 DY EC104 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 SCD1U25V2ZY-1GP SCD1U25V2ZY-1GP SCD1U25V2ZY-1GP SCD1U25V2ZY-1GP SCD1U25V2ZY-1GP SCD1U25V2ZY-1GP SCD1U25V2ZY-1GP SCD1U25V2ZY-1GP NP2 NP1 Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. CARD-PUSH-36P-GP-U2 20.I0043.001 Title CARDREADER- RTS5158E Size Document Number Rev SJV50-PU Date: Wednesday, February 25, 2009 5 4 3 2 -1 Sheet 31 1 of 59 A B C D E Mini Card Connector Half Card 4 4 1D5V_S0 3D3V_S0_MINI 3D3V_S0_MINI 1D5V_S0 MINI1 53 NP1 1 3 CLK_PCIE_MINI1# 3 CLK_PCIE_MINI1 34 34 2 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 NP2 54 E51_RxD E51_TxD 8 PCIE_RXN2 8 PCIE_RXP2 8 PCIE_TXN2 8 PCIE_TXP2 3 3D3V_S0_MINI 5V_S5 4 6 8 10 12 14 16 DY 3D3V_S0_MINI MINI2 TPAD14-GP C582 DY SC100P50V2JN-3GP 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 PLC_RST#_WLAN1 2 R228 10KR2J-3-GP WIRELESS_EN 34 PLT_RST1#_B 11,25,31,34,35,50,58 1 0R2J-2-GP 20081218_SB rename 1 R227 1 R231 34 34 E51_RxD E51_TxD 8 PCIE_RXN3 8 PCIE_RXP3 KBC_THERM_CLK 25,33,34,38,51,58 KBC_THERM_DAT 25,33,34,38,51,58 8 PCIE_TXN3 8 PCIE_TXP3 USBPN1 12 USBPP1 12 LED_WWAN#1 3D3V_S0_MINI TP70 TPAD14-GP 1 1 MINI_WAKE2# 53 NP1 1 2 3 5 7 9 11 13 15 4 6 8 10 12 14 16 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 NP2 54 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 R224 1DY 10KR2J-3-GP 2 DY 2 1 DY -1 090213 UMI_CLK1 2 DY UMI_DATA1 0R2J-2-GP 2 0R2J-2-GP DY TP74 3 CLK_PCIE_MINI2# 3 CLK_PCIE_MINI2 R216 2 1 MINI_WAKE1# 1 TPAD14-GP TP33 TPAD14-GPTP33 3D3V_S0_MINI WLAN_LED# 38 5V_S5 SKT-MINI52P-13-GP SKT-MINI52P-13-GP 62.10043.461 62.10043.461 20090108_SB PLC_RST#_WLAN2 UMI_CLK2 2 DY UMI_DATA2 0R2J-2-GP 2 0R2J-2-GP DY WIRELESS_EN 34 2 1 PLT_RST1#_B 11,25,31,34,35,50,58 R220 470R2J-2-GP 1 2 C583DY SC100P50V2JN-3GP 1 KBC_THERM_CLK 25,33,34,38,51,58 R212 1 KBC_THERM_DAT 25,33,34,38,51,58 R208 20081218_SB rename USBPN9 12 USBPP9 12 LED_WWAN#2 WLAN_LED# 3 TP219 TPAD14-GP TP218 TPAD14-GP 1 1 20081219_SB rename 1 3D3V_S0 R250 0R0603-PAD 1D5V_S0 2 1 1 1 2 2 2 1 2 1 2 1 1 2 2 SCD1U16V2ZY-2GP -1 090213 SC1U16V3ZY-GP DY C586DY C593 DY C16 SC10U6D3V5MX-3GP 2 C590 SCD1U16V2ZY-2GP 2 1 1 1 C569 SC1U16V3ZY-GP DY C547 SC10U6D3V5MX-3GP 2 1 C90 SCD1U16V2ZY-2GP SC1U16V3ZY-GP SC10U6D3V5MX-3GP DY TC13 DY C574DY C15 ST220U6D3VDM-15GP 2 C596 SC1U16V3ZY-GP SC10U6D3V5MX-3GP DY C535 2 1 3D3V_S0_MINI 2 2 SJV50 1 1 Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title MINI CARD Size Document Number Rev SJV50-PU Date: Wednesday, February 25, 2009 A B C D Sheet E -1 32 of 59 5 4 3 2 1 FAN1_VCC *Layout* 15 mil 1 FAN1_VCC FAN1_FG1 C615 SC2200P50V2KX-2GP D14 BAS16-6-GP 83.00016.K11 R261 10KR2J-3-GP 2ND = 83.00016.F11 3RD = 83.00016.H11 FAN1_VCC FAN1 2 2 FAN1_VCC 58 FAN1_FG1 58 1 2 3 1 C613 SC10U10V5ZY-1GP 1 2 2 1 5V_S0 DY C614 SCD1U16V2ZY-2GP 5 D FAN1_FG1 D 3 2 1 4 V_DEGREE 8 10 12 G792_DXN2 G792_DXN3 74.00792.A79 G67 1 2 G792SFUF-GP GAP-CLOSE R263 71K5R2F-1-GP 39 S0_PWR_GOOD DXP1:108 Degree DXP2:H/W Setting DXP3:88 Degree C103 C606 C134B Q9 SC470P50V3JN-2GP MMBT3904-4-GP G15 2.System Sensor, Put between CPU and NB. H_THERMDA 6 Place near chip as close as possible C104 SC2200P50V2KX-2GP H_THERMDC 6 1.For CPU Sensor U6C 8 C 3.T8 Sensor 32K suspend clock output 9 12,34,39,47,48 PM_SLP_S3# Q11 B C435 MMBT3904-4-GP SC470P50V3JN-2GP SC2200P50V2KX-2GP SC2200P50V2KX-2GP 2 14 3D3V_S5 C SGND1 SGND2 SGND3 1 5 17 1 C DGND DGND C ALERT# THERM# THERM_SET RESET# 2 ALERT#_SB RSMRST# 84.T3904.C11 2ND = 84.03904.P11 E 2 13 84.T3904.C11 2ND = 84.03904.P11 G792_DXP2 G792_DXP3 1 15 13 3 2 KBC_THERM_DAT 25,32,34,38,51,58 KBC_THERM_CLK 25,32,34,38,51,58 2 DXP1 DXP2 DXP3 1 4 14 16 18 19 2 7 9 11 FAN1 FG1 CLK SDA SCL NC#19 1 VCC DVCC 2 2 C92 SCD1U16V2ZY-2GP C610 C96 DY DY SCD1U16V2ZY-2GP R264 SC4D7U10V5ZY-3GP 30K1R3F-GP 2 6 20 1 1 1 1 1 2 C623 SC1U10V3ZY-6GP GAP-CLOSE 2 5V_G792_S0 2 200R2F-L-GP 1 R260 E U8 *Layout* 30 mil 1 SCD1U25V2ZY-1GP 2 DY 5V_S0 5V_S0 20.F1000.003 2ND = 20.F0714.003 1 EC31 MLX-CON3-10-GP-U C624 SC1000P50V3JN-GP-U 2 G792_32K V_DEGREE =(((Degree-72)*0.02)+0.34)*VCC *Layout* 15 mil 1 Setting T8 as 90 Degree R50 10R2J-2-GP 32KHZ 1 2 G792_32K 10 7 11,15 RTC_CLK TSLVC08APW-1-GP 73.07408.L16 2ND = 73.07408.L15 3RD = 73.07408.02B -1 090223 5V_AUX_S5 B B RSMRST# 6,34,39 SB_THSET 1 1 DY 2 18KR2F-GP RSMRST# 1 2 3 SET GND DY OUT# 1 2 C388 SCD01U16V2KX-3GP DY DY VCC 5 HYST 4 R155 0R2J-2-GP SB_TH_HYST 2 C99 R154 150R2J-L1-GP-U 5V_AUX_S5 2 2 1 2 U22 R156 DY 2 3 1 HW thermal shut down tempature setting 95 degree . Put Near SB. D2 DY BAT54PT-GP SCD1U16V2ZY-2GP R158 10KR2J-3-GP 1 EC123 2 3D3V_AUX_S5 1 1 5V_AUX_S5 1 SCD1U16V2ZY-2GP G709T1UF-GP 74.00709.A7F DY R157 0R2J-2-GP 2 OUT#: Hi active / mount R1110 Low active / mount R1108 PD UMA A A Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title G792 Size A3 Document Number Rev Date: Wednesday, February 25, 2009 5 4 3 2 -1 SJV50-PU Sheet 1 33 of 59 A 1 2 3 4 3D3V_S0 1 C111 SCD1U16V2ZY-2GP 2 1 1 2 2 1 C113 3D3V_AUX_S5 -1 090213 KBC_THERM_CLK KBC_THERM_DAT C195 DY 2 1 1 2 2 C673 RN21 KBC_BAT_CLK KBC_BAT_DAT 4 C252 SC10U10V5ZY-1GP SCD1U16V2ZY-2GP C685 SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP SRN4K7J-10-GP 8 7 6 5 3D3V_AUX_S5 DY SCD1U16V2ZY-2GP C256 SC10U10V5ZY-1GP 2 3D3V_S0 CHECK WITH SW 3D3V_S0 1 3D3V_AUX_S5 colse to Pin VDD 4 1 68 67 69 70 GPIO74/SDA2 GPIO73/SCL2 GPIO22/SDA1 GPIO17/SCL1 81 GPIO66/G_PWM SMB 2 4 3 ECSWI#_KBC 23 18 32 38 84 83 82 91 BLUETOOTH_EN DBC_EN WIRELESS_EN WLAN_TEST_LED SP GPIO77 GPIO76/SHBM GPIO75 GPIO81 SPI GPIO SDM03MT40A-7-F-GP 83.R3004.A8E 2ND = 83.R2002.B8E 32 32 E51_TxD 111 E51_RxD 113 112 E51_TxD E51_RxD DC_BATFULL 38 DC_BATFULL RN28 43,58 S5_ENABLE E51_TxD DBC_EN MODEL_ID0 GPIO16 GPIO34 GPIO36 SER/IR 44 1 1 32KX2 GPIO55/CLKOUT 28 AMP_SHUTDOWN# CRT_DEC# 19 38 ALL_LED_OFF# 12,58 PM_PWRBTN# TPAD14-GP TP224 27 12 18 PM_SLP_S3# 12,33,39,47,48 KBC_PWRBTN# 37 AC_IN# 42 LID_CLOSE# 37 1 CHG_ON# KBC_BEEP EC_TMR BRIGHTNESS 63 117 31 32 118 62 GPIO14/TB1 GPIO20/TA2 GPIO56/TA1 GPIO15/A_PWM GPIO21/B_PWM GPIO13/C_PWM 25 ENERGY_DET MODEL_ID0 TP158 1 TPAD14-GP FRONT_PWRLED 38 STDBY_LED 38 CAP_LED 38 AD_OFF 49 RSMRST#_KBC 12 PM_SLP_S5# 12,44,46 CHARGE_LED 38 13 12 11 10 71 72 36 36 35 35 35 MODEL_ID1 TP227 1 TPAD14-GP SPI_WP# 135 TP226 BLON_OUT 18 TPAD14-GP TP_LOCK_LED UMA_DISCRETE# 35 SPIDI SPIDO SPICS# SPICLK DY LOW_PWR 25 BT_LED 38 USB_PWR_EN# TPDATA TPCLK GPIO12/PSDAT3 GPIO25/PSCLK3 GPIO27/PSDAT2 GPIO26/PSCLK2 GPIO35/PSDAT1 GPIO37/PSCLK1 86 87 90 92 2 R112 1 0R0402-PAD F_SDI F_SDO F_CS0# F_SCK 53 52 51 50 49 48 47 43 42 41 40 39 38 37 36 35 34 33 KCOL1 KCOL2 KCOL3 KCOL4 KCOL5 KCOL6 KCOL7 KCOL8 KCOL9 KCOL10 KCOL11 KCOL12 KCOL13 KCOL14 KCOL15 KCOL16 KCOL17 KCOL18 KBSIN0 KBSIN1 KBSIN2 KBSIN3 KBSIN4 KBSIN5 KBSIN6 KBSIN7 54 55 56 57 58 59 60 61 KROW1 KROW2 KROW3 KROW4 KROW5 KROW6 KROW7 KROW8 VCC_POR# 85 ECRST# KBC PS/2 FIU C212 SC4D7P50V2CN-1GP GND GND GND GND GND GND 5 18 45 78 89 116 UMA_DISCRETE# 1 R140 10KR2J-3-GP Q10 B RSMRST# 3D3V_S0 MMBT3906-4-GP 84.T3906.A11 R278 10KR2J-3-GP RN27 8 7 6 5 C132 2ND = 84.03906.H11 WIRELESS_BTN# TP_LOCK_BTN# KA20GATE KBRCIN# SRN10KJ-6-GP 20.K0320.026 5V_S0 2 5V_S5 1 1 PCB_VER0 PCB_VER1 3 2 1 R137 10KR2J-3-GP USB_PWR_EN# R285 10KR2J-3-GP DY AMP_SHUTDOWN# KROW1 KROW2 KROW3 KROW4 KROW5 KROW6 KROW7 KROW8 2 2 DY KB1 ACES-CON26-6GP-U PlanarID SA: 0,0 SB: 0,1 -1: 1,0 -1M:1,1 27 1 1 2 R141 10KR2J-3-GP 58 58 58 58 58 58 58 58 ECRST# LID_CLOSE# LOW_PWR 6,33,39 2 1 2 3 4 R139 10KR2J-3-GP KROW1 KROW2 KROW3 KROW4 KROW5 KROW6 KROW7 KROW8 20090105 SB modify 4 3 2 1 SRN10KJ-6-GP 71.00773.00G 3D3V_AUX_S5 R142 10KR2J-3-GP 2 DY 2 5 6 7 8 WPCE773LA0DG-GP DIS 2 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 58 71.00773.00G 24,58 GMCH_BL_ON 9 BLON_IN 9,51 KCOL1 KCOL2 KCOL3 KCOL4 KCOL5 KCOL6 KCOL7 KCOL8 KCOL9 KCOL10 KCOL11 KCOL12 KCOL13 KCOL14 KCOL15 KCOL16 KCOL17 KCOL18 WPCE773LA0DG-GP 3D3V_AUX_S5 103 R309 0R2J-2-GP 1 2 UMA 20081124 add 64 95 93 94 119 6 109 120 65 66 16 17 20 21 22 23 24 25 26 27 28 73 74 75 110 PCB_VER0 PCB_VER1 VCORF C112 SCD1U16V2ZY-2GP 2 1 BLON_IN 100KR2J-1-GP R311 79 30 KBSOUT0/JENK# KBSOUT1/TCK KBSOUT2/TMS KBSOUT3/TDI KBSOUT4/JEN0# KBSOUT5/TDO KBSOUT6/RDY# KBSOUT7 KBSOUT8 KBSOUT9 KBSOUT10 KBSOUT11 KBSOUT12/GPIO64 KBSOUT13/GPIO63 KBSOUT14/GPIO62 KBSOUT15/GPIO61/XOR_OUT GPIO60/KBSOUT16 GPIO57/KBSOUT17 SC1U10V3KX-3GP S5_ENABLE 32KX1/32KCLKIN RN26 VCORF SRN10KJ-6-GP AGND 8 7 6 5 1 1 2 3 4 GPO83/SOUT_CR/BADDR1 GPIO87/SIN_CR GPO84/BADDR0 114 14 15 77 28 5 NUM_LED GPIO01/TB2 GPIO03 GPIO06 GPIO07 GPIO23 GPIO24 GPIO30 GPIO31 GPIO32/D_PWM GPIO33/H_PWM GPIO40/F_PWM GPIO42/TCK GPIO43/TMS GPIO44/TDI GPIO45/E_PWM GPIO46/TRST# GPIO47 GPIO50/TDO GPIO51 GPIO52/RDY# GPIO53 GPIO70 GPIO71 GPIO72 GPO82/TRIS# KBC_XO 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 ECSWI#_SB 38 101 105 106 107 KCOL2 KCOL3 KCOL4 KCOL5 KCOL6 KCOL7 KCOL8 KCOL9 KCOL10 KCOL11 KCOL12 KCOL13 KCOL14 KCOL15 KCOL16 KCOL17 KCOL18 12 ECSCI#_SB GPI94 GPI95 GPI96 GPI97 1 12 ECSCI#_KBC 2 19 46 76 88 115 D/A D17 1 KBC_XI 20081201 3 6 2 10MR2J-L-GP 2 OF 2 U13B 2nd = 82.30001.B21 1 R73 TP151 TPAD14-GP 1 10KR2J-3-GP DY 82.30001.661 1 BATTERY-----> KBC_THERM_DAT KBC_THERM_CLK 42,49 KBC_BAT_DAT 42,49 KBC_BAT_CLK TP156 TPAD14-GP TP154 TPAD14-GP TP152 TPAD14-GP 1 2 R59 R76 2 25,32,33,38,51,58 THERMAL-----> 25,32,33,38,51,58 MEDIA_INT 38,58 S0_PWR_GOOD_TP 1 X-32D768KHZ-34GPU E BLON_IN 1 1 1 4 C 9,51 TP_LOCK_BTN# WIRELESS_BTN# 1D1V_PWRGD_TP 42 2 2PCLK_KBC_RC DY AD_IA KCOL1 1 104 97 98 99 100 108 96 C119 SC7P50V2DN-2GP 1 C687 LPC VREF GPI90/AD0 GPI91/AD1 GPI92/AD2 GPI93/AD3 GPIO05 GPIO04 2 1 1 SC4D7P50V2CN-1GP A/D X2 3 2 R322 0R2J-2-GP DY GPIO10/LPCPD# LRESET# LCLK LFRAME# LAD0 LAD1 LAD2 LAD3 SERIRQ GPIO11/CLKRUN# KBRST# GA20 ECSCI#/GPIO54 GPIO65/SMI# GPIO67/PWUREQ# 33KR2J-3-GP 2 1KBC_XO_R 2 2 11,35,58 LPC_LFRAME# 11,35,58 LPC_LAD0 11,35,58 LPC_LAD1 11,35,58 LPC_LAD2 11,35,58 LPC_LAD3 11 INT_SERIRQ 11 PM_CLKRUN# 12 KBRCIN# 12 KA20GATE VDD GPIO41 124 7 2 3 126 127 128 1 125 8 122 121 ECSCI#_KBC 29 9 ECSWI#_KBC 123 11,15 PCLK_KBC C147 SC7P50V2DN-2GP U13A VCC VCC VCC VCC VCC 1 OF 2 102 BAT_IN# AVCC 49 DY 2 SC100P50V2JN-3GP 80 C678 2 PLT_RST1#_1 2 R313 0R2J-2-GP 4 1 PLT_RST1#_B 1 11,25,31,32,35,50,58 C270 SCD1U16V2ZY-2GP 2 C272 SC1U16V3ZY-GP 1 1 R138 2 0R0402-PAD Internal KeyBoard CONN 1 26 ........ 1 1 CHECK KB SPEC. AND PIN DEFINEWistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size A2 Date: A KBC WPC8768L Document Number Rev -1 SJV50-PU Wednesday, February 25, 2009 Sheet 34 of 59 3D3V_AUX_S5 5 6 7 8 SPI FLASH ROM RN24 SRN10KJ-6-GP SPI_HOLD# 4 3 2 1 16M Bits SPI_HOLD# 2 SPIDO DY EC43 SPICLK 34 DY DY EC41 EC42 SC4D7P50V2CN-1GP SC4D7P50V2CN-1GP 72.25X16.A01 2nd = 72.25165.A01 1 R103 0R2J-2-GP 2 1 34 R105 0R2J-2-GP W25X16AVSSIG-GP 2 2 SPI_WP# 8 7 6 5 SC4D7P50V2CN-1GP SC4D7P50V2CN-1GP EMI REQUEST 34 VCC HOLD# CLK DIO 1 1 R86 DY EC40 0R2J-2-GP CS# DO WP# GND 2 1 2 3 4 SPI_WP# 1 1 2 SPICS# SPICS# 2 SPIDI 3D3V_AUX_S5 U14 1 34 34 20081208 Connector FOR DEBUG BOARD 20081219 3D3V_S0 GF1 DY 1 2 3 4 5 6 7 8 9 10 11 12 LPC_LAD0 LPC_LAD1 LPC_LAD2 LPC_LAD3 LPC_LFRAME# PLT_RST1#_B PCLK_FWH LPC_LAD0 11,34,58 LPC_LAD1 11,34,58 LPC_LAD2 11,34,58 LPC_LAD3 11,34,58 LPC_LFRAME# 11,34,58 PLT_RST1#_B 11,25,31,32,34,50,58 PCLK_FWH 11,15,58 MLX-CON10-7-GP SJV50 20.D0183.110 Boot Device must have ID[3:0] = 0000 Has internal pull-down resistors All may be left floated FPET7 Elec. P3-46 Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title BIOS Size A4 Document Number Rev -1 SJV50-PU Date: Wednesday, February 25, 2009 Sheet 35 of 59 5 4 D 3 2 1 D TOUCH PAD 5V_S0 5V_S0 EC53 2 2 1 ACES-CON12-9-GP DY EC89 DY SC100P50V2JN-3GP 14 EC88 SC100P50V2JN-3GP DY SC100P50V2JN-3GP 37,58 TP_LEFT EC52 SC100P50V2JN-3GP 37,58 TP_RIGHT 1 SRN33J-5-GP-U 2 3 4 5 6 7 8 9 10 11 12 1 TP_DATA TP_CLK 3 4 C 2 2 1 TP_DATA TP_CLK TP_LEFT TP_RIGHT TP_DATA TP_CLK 1 TPDATA TPCLK 58 58 1 2 34 34 TPCN1 13 1 2 4 3 RN64 EC92 SCD1U10V2KX-4GP C SCD1U10V2KX-4GP RN67 SRN10KJ-5-GP DY 2 EC91 1 2 1 DY DY 20.K0315.012 2ND = 20.K0370.012 B B 1 12 T/P SJV50 Wistron Corporation A 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title TouchPad Size Document Number SJV50-PU Sheet Wednesday, February 25, 2009 Date: 5 4 3 2 Rev -1 36 1 of 59 A A B C D Power Button Board 4 KBC_PWRBTN#_R E Cover Up Switch KBC_PWRBTN#_R 58 4 3D3V_AUX_S5 1 3D3V_AUX_S5 R7 10KR2J-3-GP 1 VDD 1 EC2 SCD1U16V2ZY-2GP ME268-002-GP 1 20.F0825.002 2ND = 20.F1396.002 LID_CLOSE# 34 DY GND C7 SCD1U16V2ZY-2GP 2 ACES-CON2-3-GP-U 3 LID_CLOSE# 2 2 R8 470R2J-2-GP OUT KBC_PWRBTN# 34 1 G1 GAP-OPEN 2 4 2 1 KBC_PWRBTN#_R 2 LID1 2 74.00268.07B EC109 SCD1U16V2ZY-2GP DY 3 1 3 2 PWRCN1 3 1 RIGHT LEFT TP_RIGHT 36,58 TP_LEFT 36,58 RIGHT1 2 4 SW-TACT-5P-1-GP 62.40009.A61 2 2 DY 5 1 2 5 3 1 EC114 SCD1U16V2ZY-2GP DY LEFT1 2 1 EC65 SCD1U16V2ZY-2GP 2 1 3 4 SW-TACT-5P-1-GP 62.40009.A61 SJV50 Wistron Corporation 1 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Switchs Size Document Number Rev SJV50-PU Date: Wednesday, February 25, 2009 A B C D Sheet -1 37 of E 59 1 5 4 3 5V_S5 3 PWR_LED1 Q31 DC_BATFULL# -1 090223 3 EC118 R2 DTC143ZUB-GP 84.00143.G1K 2ND = 84.00143.D1K 3RD = 84.00143.E1K Q4 1 CAP_LED CAP_LED# 3 R1 1 R39 2 82R2J-1-GP 20081204_SWAP 2 1 2 1 R37 NUM_LED#_MMB 58 2 120R2J-2-GP MEDIA_LED#_MMB MEDIA_LED#_MMB 58 5V_S0 C EC25 SCD1U10V2KX-4GP SC220P50V2JN-3GP MEDIA_LED#_R 3 NUM_LED#_MMB EC22 Q6 R1 1 20.K0384.016 SCD1U25V2ZY-1GP -1 090223 DY SC220P50V2JN-3GP 2 82R2J-1-GP 2ND = 84.00143.D1K 3RD = 84.00143.E1K 34 ALL_LED_OFF# 18 CAP_LED#_MMB 58 EC23 DY 2 R2 DTC143ZUB-GP 84.00143.G1K BT_LED#_MMB SC220P50V2JN-3GP 1 R38 WLAN_LED#_MMB CAP_LED#_MMB NUM_LED#_MMB MEDIA_LED#_MMB SC220P50V2JN-3GP NUM_LED# 3 KBC_THERM_CLK 25,32,33,34,51,58 KBC_THERM_DAT 25,32,33,34,51,58 MEDIA_INT 34,58 SC220P50V2JN-3GP 1 CAP_LED#_MMB 20081218_SB rename 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 KYO-CON16-GP Q3 NUM_LED 83.19226.C70 2ND = 83.00195.M70 SCD1U25V2ZY-1GP 2ND = 84.00143.D1K 3RD = 84.00143.E1K 34 4 LED-RB-4-GP DY 2 R2 DTC143ZUB-GP 84.00143.G1K R1 1 EC119 EC19 SCD1U10V2KX-4GP 1 2 34 17 3 DY 1 C 2 BLUE SCD1U25V2ZY-1GP 2 SCD1U25V2ZY-1GP 1 DC_BATFULL#_R 2 1K82R2F-1-GP DY 1 R453 Q30 RED CHARGE_LED#_R 2 1KR2J-1-GP 1 R454 1 2ND = 84.00143.D1K 3RD = 84.00143.E1K R1 MMB1 5V_AUX_S5 CHARGER_LED1 CHARGE_LED# 2 R1 D 3D3V_S0 DY 3 2 R2 DTC143ZUB-GP 84.00143.G1K 34 DC_BATFULL 83.19226.C70 2ND = 83.00195.M70 CHARGER LED 1 1 34 CHARGE_LED 3 LED-RB-4-GP EC30 1 2 2ND = 84.00143.D1K 3RD = 84.00143.E1K 2 -1 090223 2 R2 DTC143ZUB-GP 84.00143.G1K 2 STDBY_LED 2 EC121 SCD1U25V2ZY-1GP 34 SCD1U25V2ZY-1GP D R1 RED DY EC21 1 2 STDBY_LED#_R 2 1KR2J-1-GP DY EC120 4 EC26 1 2 1 R455 3 1 EC27 1 2 STDBY_LED# Q32 BLUE EC28 1 2 FRONT_PWRLED#_R 2 1K82R2F-1-GP 1 1 R456 1 FRONT_PWRLED# 1 2ND = 84.00143.D1K 3RD = 84.00143.E1K 2 R2 DTC143ZUB-GP 84.00143.G1K 2 R1 2 1 1 1 1 34 FRONT_PWRLED 2 POWER LED Q33 DY DY DY DY DY 2 R2 DTC143ZUB-GP 84.00143.G1K B B 2ND = 84.00143.D1K 3RD = 84.00143.E1K 13 MEDIA_LED# Q7 BT_LED# 3 R1 1 R35 BT_LED#_MMB 2 300R2J-4-GP 1 -1 090213 DY WLAN_LED#_R2 4 3 RN70 SRN10KJ-5-GP 1 2 R45 33R2F-3-GP 1 R40 DY 2 100R2J-2-GP WLAN_LED#_MMB 58 DY Q34 R2 DY R1 2 R2 DTC143ZUB-GP 84.00143.G1K B DY E C D 1 WLAN_LED#_R R1 34 ALL_LED_OFF# 3 DDTA114YCA-7-F-GP . 84.00114.M11 G SJV50 A Wistron Corporation Q13 2N7002E-1-GP 84.2N702.D31 . . . . 2ND = 84.00143.D1K 3RD = 84.00143.E1K 32 DY 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title S Q5 A EC24 SCD1U25V2ZY-1GP WLAN_LED#_R1 1 2 3D3V_S0 EC20 2 2ND = 84.00143.D1K 3RD = 84.00143.E1K SCD1U25V2ZY-1GP R2 DTC143ZUB-GP 84.00143.G1K DY BT_LED#_MMB 58 DY 2 1 1 BT_LED 2 34 LED on Front Panel WLAN_LED# Size Document Number Rev Date: Wednesday, February 25, 2009 5 4 -1 SJV50-PU 34 WLAN_TEST_LED 3 2 Sheet 1 38 of 59 Run Power 5V_S5 5V_S0 DY C846 1 Q28 NDS0610-NL-GP 1 G 2 1 1 3D3V_RUNPWR 2 R449 100KR2J-1-GP R433 2 2 Z_12V_D4 D20 PDZ9D1B-GP D D D D 8 7 6 5 3D3V_S0 3D3V_S5 1 2 3 4 U60 S S S G AO4468-GP 1D8V_S3 1D8V_S0 Z_12V_D3 Q27 Q29 2N7002-11-GP D DY 330KR2J-L1-GP C840 330KR2J-L1-GP DY Z_12V_G3 2 AO4468-GP SCD22U25V3KX-GP R428 10KR2J-3-GP R426 100R5J-3-GP 8 7 6 5 K 10KR2J-3-GP R448 1 D D D D D A S SCD1U25V3KX-GP RUN_POWER_ON 1 3D3V_S0 2 Z_12V 2 R447 1 1 DCBATOUT 1 2 3 4 2 U59 S S S G Z_12V_D3 3 5 2 6 1 1 2 3 4 R365 1 2 1D8V_S0_ON 1MR2F-GP S 1 G 4 D D D D 8 7 6 5 AO4468-GP C766 SC22P50V2JN-4GP 20081128 2 2N7002DW-1-GP U41 S S S G PM_SLP_S3# 12,33,34,47,48 1 3D3V_AUX_S5 R159 10KR2J-3-GP 2 3 DY 2 1 12,33,34,47,48 PM_SLP_S3# D4 BAT54-7-F-GP VCORE_EN 41,45 2nd = 83.BAT54.D81 3 1 D13 2D5V_S0_PG 1 SC1U10V2KX-1GP 1 C602 2 2 100KR2J-1-GP R239 2 100KR2J-1-GP R237 2 Follow OLAN 3D3V_S0 1 2D5V_S0 BAW56-5-GP 1 3V/5V_POK (dummy, KBC already delay) R246 1 DY 2 0R2J-2-GP DY R245 1 2 44 1D8V_S3_PWRGD C390 DY SCD1U16V2ZY-2GP 2 43 RSMRST# 6,33,34 83.00056.Q11 2ND = 83.00056.K11 0R2J-2-GP P/H @ 1D8V_S3 PAGE R251 41 1 VRM_PWRGD DY 2 1D1V_PWRGD 45 0R2J-2-GP 20080114 SB 3D3V_S5 1D8V_S0 D 3D3V_S5 G S D5 BAS16-1-GP NB_PWRGD 9,12 14 U37A 12,33,34,47,48 PM_SLP_S3# 3 2 45 1D1V_PWRGD 7 D15 33 S0_PWR_GOOD TSLVC08APW-1-GP 2 3 RUNPWROK_D 73.07408.L16 2ND = 73.07408.02B 1 2N7002E-1-GP 84.2N702.D31 1 2ND = 84.2N702.I31 SB_PWRGD 3,12 SA_20081030 2 2 10KR2J-3-GP . R249 . . . . 1 Q35 3 43 3V/5V_EN 1 RSMRST# 6,33,34 SJV50 83.00016.B11 2ND = 83.00016.K11 Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title RUN POWER and AUX POWER BAW56-5-GP 83.00056.Q11 2ND = 83.00056.K11 Size Document Number Rev -1 SJV50-PU Date: Wednesday, February 25, 2009 Sheet 39 of 59 5 4 3 2 TI TPS51125 3D3V/5V CPU_CORE ISL6264 VID Setting VID0 D VID0(I / 3.3V) VID1 1D5V_S0 Input Signal Output Signal VROK() MAX8760_VRM 51120_EN2 VID1(I / 3.3V) VID2 51120_EN1 VID2(I / 3.3V) VID3 VID3(I / 3.3V) VID4 VID4(I / 3.3V) VID5 1 3D3V_S0 Output Signal FOR 3.3V INPUT FOR 5.0V D Pull High (3D3V) 1D2V_S5 3D3V_S5 INPUT VCC_CORE_S0(Imax=35A) OUT 1D2V_S5 G9091 DCBATOUT_51120 VID5(I / 3.3V) 1D5V_S0 G957 PGOUT(OD / 5V) Output Power VCC_CORE_PWR(O) OUT VIN 2D5V_S0 5V_AUX_S5 Input Signal VCORE_EN COREFB COREFB# 3D3V_S0 INPUT OUT 2D5V_S0 3D3V_AUX_S5 DCBATOUT_51120 Voltage Sense C Output Power Input Power EN (I / 3.3V) G9091 VIN 5V(O) VSEN(I / Vcore) 5V_S5 (5.4A) 0D9V_S3 REG5V_IN(I / 5V) C RGND(I / Vcore) 3D3V(O) 3D3V_S5 (4A) 5V_S5 INPUT OUT 0D9V_S3 Input Power DCBATOUT 5V_S0 RT9026 VCC(I) VCC(I) 3D3V_S0 Adapter VCC(I) Input Signal AD_OFF Charger_MAX8731 Output Signal (O) (I) AD_IN CHARGE_OFF BT_TH Input Power AD_JK B TI TPS51124 1.8V / 1.2V Input Signal PM_SLP_S5# 5V_S5 VCC(I) VCC(I) VCC(I) AD+ BAT+SENSE BT_SCL_5 BT_SDA_5 Output Signal PGOOD(OD / 3.3V) Input Power A VCC(O) VCC(I) FLASH_GPIO1 S5 S3 DCBATOUT 5V_AUX_S5 Output Power FLASH_GPIO2 1D8V_S3_PG AC_IN AD+ Output Power VCC(O) VCC(O) Input Signal Output Signal THM (I / 3.3V) BATT (I / 3.3V) AD_IN LDO (O / 5.4V) CLS (I / 3.3V) CHARGE_LED# XTAL2/PB4 (O/5V) XTAL1/PB3 (O/5V) B BL2# SCL (IO / 5V) SDA (IO / 5V) Output Power DCBATOUT VCC (O) RESET#/PB5 (I/5V) PB0/MOSI/AIN0 BT+ VCC (O) PB0/MOSI/AIN0 Input Power DCIN (I) 1.8V_S3 1.2V_S0 SJV50 A Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Power Block Diagram Size A3 Document Number Rev SJV50-PU Date: Wednesday, February 25, 2009 5 4 3 2 -1 Sheet 1 40 of 59 5 DCBATOUT_6265_1 DCBATOUT 1 2 1 2 4 3 2 1 4 3 2 1 ISP0 C170 1 2 1 2 249R2F-GP SC4700P50V2KX-1GP 1 R99 2 1KR2F-3-GP 1 2 C138 SC1KP50V2KX-1GP SC180P50V2JN-1GP R85 1 2 54K9R2F-L-GP C161 1 2 R78 C127 1 2 1 2 249R2F-GP SC4700P50V2KX-1GP 2 6K81R2F-1-GP SC180P50V2JN-1GP 1 R79 2 1KR2F-3-GP 1 2 54K9R2F-L-GP 1 2 1 1 C117 1 2 1 R80 1 1 2 2 G S S S 4 3 2 1 5 6 7 8 1 2 1 G S S S 4 3 2 1 1 2 1 TC1 TC2 2 1 2 1 R68 2 DY 2 1 DY 10R2F-L-GP NTC-10K-9-GP ISP1_R TC15 2 1 2 1 2 1 5 6 7 8 4 3 2 1 2 SCD1U16V2KX-3GP ISN1 2 G17 2 SC1KP50V2KX-1GP C125 SC1KP50V2KX-1GP 2 1 2 5 6 7 8 D D D D 1 SC180P50V2JN-1GP R71 R77 1 C136 1 2 ISP1 C176 1 2 1 C129 SC180P50V2JN-1GP 1 DY 2 1 4 3 2 1 5 6 7 8 4 3 2 1 S S S G S S S G R82 1 C151 2 4K02R2F-GP R81 R100 2 2 2 2 2 1 SE330U2VDM-L-GP Parts close to PWM IC SE330U2VDM-L-GP Close to CPU socket 6265_FB1_C VCC_CORE_S0_1 Design Current: 12.6A Peak current: 18A OCP_min:24A VCC_CORE_S0_1 L48 1 2 IND-D36UH-9-GP R84 16K2R2F-GP LGATE1 C154 SC180P50V2JN-1GP 1 2 DY ESR=15mohm B SE330U2VDM-L-GP D D D D U11 AOL1712-GP D D D D BOOT1 1 2 C172 SCD22U10V3KX-2GP U12 AOL1712-GP Parallel TC17 DY 79.22719.20L 2ND = 80.2271V.A9L 2 1 1 1 6 CPU_VDD1_RUN_FB_L 6 CPU_VDD1_RUN_FB_H 6265_FB0_C C723 LGATE_NB 68.R3610.20C 2ND = 68.R3610.20A UGATE1 PHASE1 R58 10R2F-L-GP 68.4R710.20D 2ND = 68.4R71C.10A DY 2 6 CPU_VDD0_RUN_FB_H 6 CPU_VDD0_RUN_FB_L R55 10R2J-2-GP VDDNB L55 2 IND-4D7UH-88-GP C109 SCD1U25V3KX-GP S S S G 2 C105 SC10U25V6KX-1GP R75 C106 SC10U25V6KX-1GP 1 C102 U9 AOL1426-GP DY 0R2J-2-GP R60 10R2J-2-GP 1 84.04800.D37 2ND = 84.08884.037 ISN1 ISP1 SC10U25V6KX-1GP 1 U20 SI4800BDY-T1 D D D D R56 10R2J-2-GP PHASE_NB 2 DY VDDNB: Design Current: 2.1A Peak current: 3A OCP_min:5A SCD22U10V3KX-2GP DCBATOUT_6265_2 6265_VDIFF1 6265_FB1 6265_COMP1 6265_VW1 ISP0 ISN0 VCC_CORE_S0_0 VCC_CORE_S0_1 UGATE_NB BOOT_NB 1 C381 C184 2 74.06265.A73 1D8V_S3 Close to CPU socket PHASE1 UGATE1 BOOT1 13 14 15 16 17 18 19 20 21 22 23 24 ISL6265HRTZ-T-1-GP GNDA_VCORE B LGATE1 5 6 7 8 GAP-CLOSE-PWR-3-GP 2ND = 84.08884.037 5V_S0 LGATE0 C365 SE220U2VDM-8GP 2 U19 SI4800BDY-T1 84.04800.D37 C C367 SCD1U10V2KX-4GP G18 1 BOOT_NB BOOT0 UGATE0 PHASE0 ISP0 ISN0 VSEN0 RTN0 RTN1 VSEN1 VDIFF1 FB1 COMP1 VW1 ISP1 ISN1 GNDA_VCORE BOOT_NB BOOT0 UGATE0 PHASE0 PGND0 LGATE0 PVCC LGATE1 PGND1 PHASE1 UGATE1 BOOT1 U15 DCBATOUT_6265_3 1 GND VIN VCC FB_NB COMP_NB FSET_NB VSEN_NB RTN_NB OCSET_NB PGND_NB LGATE_NB PHASE_NB UGATE_NB 2 2 1 2 R101 23K7R2F-GP OFS/VFIXEN PGOOD PWROK SVD SVC ENABLE RBIAS OCSET VDIFF0 FB0 COMP0 VW0 GAP-CLOSE-PWR-3-GP 6 C368 SC2D2U6D3V3KX-GP 6265_SVD 6265_SVC 6265_ENABLE 6265_RBIAS 6265_OCSET 6265_VDIFF0 6265_FB0 6265_COMP0 6265_VW0 R109 1 0R0402-PAD 2 R104 1 0R0402-PAD 2 R107 1 0R0402-PAD 2 1 2 R102 93K1R2F-L-GP 79.33719.L01 79.33719.L01 2ND = 77.C3371.051 2ND = 77.C3371.051 1 R131 10R2F-L-GP 36 35 34 33 32 31 30 29 28 27 26 25 79.33719.L01 2ND = 77.C3371.051 SCD1U25V3KX-GP 39 VRM_PWRGD 6 CPU_PWRGD_SVID_REG 6 CPU_SVD 6 CPU_SVC 39,45 VCORE_EN 1 2 3 4 5 6 7 8 9 10 11 12 CPU_VDDNB_RUN_FB_L R236 close to L13 TC3 SC10U25V6KX-1GP GNDA_VCORE R118 2 1 0R0402-PAD ISP0_R ISN0 2 G16 TC16 SC10U25V6KX-1GP R122DY 0R2J-2-GP R110 10KR2F-2-GP CPU_VDDNB_RUN_FB_L_R 49 48 47 46 45 44 43 42 41 40 39 38 37 GNDA_VCORE LGATE0 UGATE_NB 1 1 1 2 2 2 0R2J-2-GP 6265_OFS/VFIXEN LGATE_NB PHASE_NB 1 2 C126 SCD1U16V2KX-3GP R67 R70 1 2 DY 2 1 DY 10R2F-L-GP NTC-10K-9-GP 2 1 2 GNDA_VCORE 6265_VIN 6265_VCC 6265_FB_NB 6265_COMP_NB 6265_FSET_NB 6265_VSEN_NB DY R117 3D3V_S0 C 2 6265_OCSET_NB C225 SCD1U25V3KX-GP 1 1 1 R125 2R3J-GP PHASE_NB S S S G R123 0R0603-PAD R106DY 10KR2F-2-GP GAP-CLOSE-PWR 3D3V_S0 1 R115 2 11K3R2F-2-GP S S S G 5V_S0 GAP-CLOSE-PWR G24 1 2 1 DCBATOUT_6265_1 GAP-CLOSE-PWR G25 1 2 TC4 2 1 1 1 R72 2 4K02R2F-GP D D D D 2 2 4 3 2 1 6 SE330U2VDM-L-GP CPU_VDDNB_RUN_FB_H Parts close to PWM IC SE330U2VDM-L-GP R1191 0R0402-PAD 2 U17 AOL1712-GP VCC_CORE_S0_0 SE330U2VDM-L-GP GNDA_VCORE 2 VCC_CORE_S0_0 Design Current: 12.6A Peak current: 18A OCP_min:24A L52 1 2 IND-D36UH-9-GP R69 16K2R2F-GP D D D D G26 BOOT0 1 2 C196 SCD22U10V3KX-2GP U16 AOL1712-GP R130 10R2F-L-GP GNDA_VCORE DCBATOUT_6265_3 DY D 2ND = 68.R3610.20A 68.R3610.20C UGATE0 PHASE0 D D D D DCBATOUT C289 2 1 R120 2 22KR2F-GP C223 SC1U10V2KX-1GP 2 SC1KP50V2KX-1GP VDDNB 2 SCD1U10V2KX-4GP 5 6 7 8 1 2R3J-GP 1 C222 1 5 6 7 8 2 C285 SC10U25V6KX-1GP R124 1 C286 SC10U25V6KX-1GP 1 R121 26265_FB_NB_R 1 44K2R2F-1-GP C233 5V_S0 GAP-CLOSE-PWR U18 AOL1426-GP C234 SC180P50V2JN-1GP 1 2 S S S G GAP-CLOSE-PWR 2 SC33P50V2JN-3GP 1 C216 GAP-CLOSE-PWR G14 1 2 20081203 D D D D GAP-CLOSE-PWR G23 1 2 C287 GAP-CLOSE-PWR G13 1 2 SC10U25V6KX-1GP 79.68612.30L 2nd = 79.68612.L01 GAP-CLOSE-PWR G22 1 2 DCBATOUT_6265_1 5 6 7 8 GAP-CLOSE-PWR G21 1 2 GAP-CLOSE-PWR G11 1 2 TC18 SE68U25VM-3-GP GAP-CLOSE-PWR G12 1 2 2 1 GAP-CLOSE-PWR G20 1 2 2 2 1 2 2 G10 2 1 1 SCD1U25V3KX-GP D TC29 SE100U25VM-L1-GP 1 DY 2 DCBATOUT_6265_2 G19 1 3 1 DCBATOUT 4 79.33719.L01 2ND = 77.C3371.051 R235 close 79.33719.L01 to L12 2ND = 77.C3371.051 79.33719.L01 2ND = 77.C3371.051 1 GAP-CLOSE-PWR-3-GP 2 6K81R2F-1-GP A A 6265_FB0_R 1 C156 6265_FB1_R 1 C124 2 SC1KP50V2KX-1GP 2 SC180P50V2JN-1GP SJV50 Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size Custom Date: 5 4 3 2 CPU Vcore (ISL6265HR) Document Number Rev -1 SJV50-PU Wednesday, February 25, 2009 Sheet 1 41 of 59 5 4 3 2 1 AD+ AD+_TO_SYS BT+ DY 20090108_SB_Wayne C581 SCD1U25V2ZY-1GP 1 DY 2 1 2 C559 SC1U10V3KX-3GP 1 2 C563 SCD015U25V2KX-GP 1 C573 SCD01U50V2ZY-1GP 2 DY ISL88731AHRZ-T-GP 74.88731.B73 NC#16 16 VFB 15 C508 SC10U25V6KX-1GP 1 84.04800.D37 2ND = 84.08884.037 C566 SCD22U50V3ZY-1GP ISL88731_CSIP VCOMP NC#5 ICOMP VREF NC#7 GND 1 C528 1 C530 C529 B R215 GND 6 5 4 3 7 12 29 ISL88731_CCV 2 10KR2F-2-GP ISL88731_CCS C575 SCD01U50V2KX-1GP 2 1ISL88731_CCV1 10KR2J-3-GP DY 2 R221 SCD01U16V2KX-3GP 2 1 C588 B 1 ISL88731_CSIN R217 1 U29 SI4800BDY-T1 D01R2512F-4-GP C507 SC10U25V6KX-1GP 2 1 2 5 6 7 8 D D D D ICM 10R2F-L-GP G S S S 1 8 2 4 3 2 1 1 2 R223 1KR2F-3-GP AD_IA 1 2 34 R211 ISL88731_CSIP_R 1 2 G46 GAP-CLOSE-PWR-2U 5 6 7 8 D D D D 68.1001B.10R 2ND = 68.1001B.10S 2 1 17 1 C506 SC10U25V6KX-1GP 2 1 CSON R187 1 2 IND-10UH-117-GP 2 ISL88731_IINP BT+ L40 ISL88731_LX 1 CHG_AGND 18 SA_20081104 2008/11/04 C509 SC10U25V6KX-1GP 19 CSOP NC#14 C 2 PGND 14 2 ISL88731_DLO 2 20 SDA 2 1 LGATE SCL 9 34,49 KBC_BAT_DAT C556 1 2 SC1U10V3KX-4GP 1 2 C544 SCD1U50V3KX-GP 1 ISL88731_LX BAT54PT-GP 2 23 1 C531 G4 GAP-CLOSE-PWR-2U PHASE 84.04800.D37 2ND = 84.08884.037 DY ACOK 10 34,49 KBC_BAT_CLK D8 U27 SI4800BDY-T1 1 ISL88731_DHI 3 CHG_AGND 2 24 13 R195 4D7R3F-L-GP 2 G S S S 1 UGATE ISL88731_ACOK CHG_AGND CHG_AGND 2 25 21 27 26 1 1 BOOT VDDP CSSN VCC VDDSMB 1 C585 SCD1U10V2KX-4GP CSSP 2008/11/04CHG_AGND ISL88731_CSSN_R ISL88731_VCC R196 0R3-0-U-GP ISL88731_BST 1 2ISL88731_BST1 ISL88731_LDO 11 5V_S5 2 1 2 2 C555 SCD01U50V2KX-1GP R204 49K9R2F-L-GP ACIN SA_20081114 CHRG_IN C543 SC1U10V3KX-3GP 2 2 1 C DCIN 2 D SCD1U25V3KX-GP ISL88731_ACIN 28 C542 SC10U25V6KX-1GP U33 22 2 SCD047U25V3KX-GP SC10U25V6KX-1GP R205 215KR3F-1-GP NC#1 2 1 SC1U25V5KX-1GP C540 1 84.04433.A37 2ND = 84.04407.F37 R10 470KR2J-2-GP SC10U25V6KX-1GP 2008/10/20 CHG_AGND ISL88731_CSSP C565 CH521S-30PT-GP-U C8 4 3 2 1 1 SCD1U25V3KX-GP 1 2 2 2 1 K SCD1U25V3KX-GP ISL88731_ACOK D9 A G47 GAP-CLOSE-PWR-2U 2 1 2 R194 10R2J-2-GP C541 2 R197 10R2J-2-GP R229 1 10KR2F-2-GP G45 GAP-CLOSE-PWR-2U 2 1 2 1 4 5 6 2 1 3 2 Q12 2N7002EDW-GP 8 7 6 5 AO4433-GP G48 GAP-CLOSE-PWR-2U 2 1 100KR2J-1-GP 1 10KR2J-3-GP 2 G55 GAP-CLOSE-PWR-2U 1 D D D D SCD1U25V3KX-GP 2 2 R2 1 U26 S S S G 1 2 3 4 AD+ D01R2512F-4-GP R3 84.04433.A37 AD+_G_1 2ND = 84.04407.F37 1 2 GAP-CLOSE-PWR-2U G3 1 2 R4 1 AO4433-GP D DCBATOUT 1 2 3 4 1ISL88731_CSSN 1 U3 S S S G D D D D G9 GAP-CLOSE-PWR-2U 8 7 6 5 PBATT_SENSE_R 1 2 BATT_SENSE 49 0R3-0-U-GP 2008/11/04 20081008 1 2 G56 GAP-CLOSE-PWR-2U CHG_AGND ISL88731_LDO 2008/10/24 1 3D3V_AUX_S5 2 2 R222 10KR2F-2-GP R218 10KR2J-3-GP AC_IN# R219 Q14 2N7002-11-GP G 1 S 1 A 1 D 34 2 ISL88731_ACOK SJV50 A 0R2J-2-GP Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. 2 R225 15K8R3F-GP Title ISL88731A Charger Size A3 Document Number Rev 5 4 3 2 -1 SJV50-PU Date: Wednesday, February 25, 2009 Sheet 1 42 of 59 4 DCBATOUT_51125 G36 2 5V_AUX_S5 3V/5V_EN 39 2 3 4 3 4 84.27002.B3F 51125_ENTIP1 GAP-CLOSE-PWR G113 1 2 1 C487 1 DY 2N7002SPT R441 GAP-CLOSE-PWR G31 1 2 D GAP-CLOSE-PWR G112 1 2 DY C488 2N7002SPT 84.27002.B3F GAP-CLOSE-PWR G114 1 2 GAP-CLOSE-PWR G108 1 2 2 DY 3V/5V_EN 2 2 R434 39 2 DY C847 1 1 5 1 51125_ENTIP2 2 1 2 1 R65 249KR2F-GP 6 2 SC18P50V2JN-1-GP GAP-CLOSE-PWR G33 1 2 1 5 115KR2F-GP DCBATOUT_51125_3V G35 1 2 6 2 SC18P50V2JN-1-GP 1 DCBATOUT_51125 DCBATOUT C848 1 2 GAP-CLOSE-PWR G111 1 2 Q25 SCD1U25V3ZY-1GP DY 124KR2F-GP 2 3V/5V_EN SCD1U25V3ZY-1GP 79.10712.L02 2ND = 79.10112.3JL 3RD = 79.10712.6JL 39 -1 090206 GAP-CLOSE-PWR 5V_S5 G110 1 R439 10KR2J-3-GP R444 10KR2J-3-GP Q26 GAP-CLOSE-PWR G30 1 2 TC22 SE100U25VM-L1-GP 5V_AUX_S5 5V_PWR GAP-CLOSE-PWR G32 1 2 D 1 1 1 2 R436 2KR2F-3-GP 34,58 S5_ENABLE GAP-CLOSE-PWR G34 1 2 2 1 2 1 DCBATOUT 3 2 5 GAP-CLOSE-PWR G115 1 2 51125_EN GAP-CLOSE-PWR GAP-CLOSE-PWR DCBATOUT_51125 DCBATOUT_51125 51125_DRVL1 68.3R310.20A 2ND = 68.3R31A.10E 1 51125_ENTIP1 GND 4 TONSEL GND 25 1 18 R427 100KR2J-1-GP DY Close to VFB Pin (pin5) 3D3V_AUX_S5 2 R415 1 0R2J-2-GP TP209 1 1 5V_AUX_S5 G37 1 4 3 2 1 DY C852 SC18P50V2JN-1-GP GAP-CLOSE-PWR-3-GP R446 30K9R2F-GP GAP-CLOSE-PWR G103 1 2 GAP-CLOSE-PWR G105 1 2 GAP-CLOSE-PWR G106 1 2 GAP-CLOSE-PWR G107 1 2 20081203 GAP-CLOSE-PWR change to poscap 51125_FB1_R 1 R450 20KR2F-L-GP -1 090213 Close to VFB Pin (pin2) 51125_PGOOD C832 2 1 R430 0R2J-2-GP 3V/5V_POK 39 SJV50 A Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. R181 2 DY Title 1 TPS51125 5V/3D3V 0R2J-2-GP Size A3 Document Number Rev SJV50-PU Date: Wednesday, February 25, 2009 5 4 B DY S5_ENABLE 34,58 2 2008/10/17 R452 0R2J-2-GP R468 100KR2J-1-GP DY SC10U10V5KX-2GP 2 R416 1 0R2J-2-GP SC10U10V5KX-2GP 51125_VREF A 2 C843 51125_VCLK Id=7.7A Qg=8.5~13nC Rdson=16.5~21mohm TC27 2 R451 1 0R2J-2-GP 2 5V_AUX_S5_51125 17 3D3V_AUX_S5 GAP-CLOSE-PWR 1 1 0R2J-2-GP 2 DY R183 3D3V_AUX_S5_5_51125 8 51125_VREF 2 2 1 2 1 G38 S 1 2 TPS51125RGER-GP 74.51125.073 VCLK VREG5 SKIPSEL VREG3 14 51125_SKIPSEL 1 G S S S VREF 15 2 51125_TONSEL G 3D3V_S5 3 DY 1 ENTRIP1 ENTRIP2 84.04812.A37 2ND = 84.08878.037 TC28 2 51125_PGOOD 1 23 C836 2 PGOOD G116 1 51125_FB1 D D D D 2 DY U56 SI4812BDY-T1-E3-GP 2 1 VFB1 2 1 1 2 VFB2 D 2 5 6 7 8 8 7 6 5 1 2 3 4 1 1 2 5 3D3V_AUX_S5 2 R442 10KR2F-2-GP 51125_VO1 SE220U6D3VM-7GP 51125_FB2_R C851 DYSC18P50V2JN-1-GP C850 24 2ND = 77.92271.021 Id=7.7A R437 Qg=8.5~13nC 0R2J-2-GP Rdson=16.5~21mohm DY VO1 2 GAP-CLOSE-PWR G99 1 2 GAP-CLOSE-PWR G101 1 2 ST220U6D3VDM-20GP 51125_VREF VO2 EN0 1 19 7 2 51125_EN 13 820KR2F-GP 51125_ENTIP2 6 1 DRVL1 2ND = 77.C2271.00L G SCD22U6D3V2KX-1GP R445 6K65R2F-GP 1 R182 2 2 5 6 7 8 1 2 IND-3D3UH-57GP SCD1U10V2KX-4GP 51125_FB2 84.04812.A37 2ND = 84.08878.037 S D D D D G S S S 51125_LL1 GAP-CLOSE-PWR-3-GP 2008/10/17 U57 SI4812BDY-T1-E3-GP 2 1 1 51125_DRVH1 20 1 DRVL2 51125_VO2 G S S S 2 1 2 2 2 21 LL1 2 12 D D D D G109 GAP-CLOSE-PWR-3-GP 2ND = 77.92271.021 DRVH1 L61 1 Cyntec 7*7*3 DCR=30mohm, Irating=6A 5V_PWR Isat=13.5A 1 51125_DRVL2 S 3D3V_S5 G97 2 LL2 G 1 DRVH2 11 3D3V_PWR Iomax=6A OCP>9A 2 10 C 51125_VBST1 VBST1 51125_LL2 68.3R310.20AD 2ND = 68.3R31A.10E TC26 SE220U6D3VM-7GP ST220U6D3VDM-20GP SCD1U10V2KX-4GP B TC25 SCD1U25V3KX-GP C839 1 2 C822 22 VBST2 51125_DRVH2 D U51 SI4800BDY-T1 C480 4 3 2 1 51125_VBST2 9 SCD1U25V3KX-GP L62 1 1 C838 2 2 VIN C842 1 1 2 IND-3D3UH-57GP DY 16 8 7 6 5 1 2 3 4 2 1 2 1 1 2 DY 84.04800.D37 2ND = 84.08884.037 G S S S G Isat=13.5A DY U58 84.04800.D37 2ND = 84.08884.037 Id=7A Qg=8.7~13nC Rdson=23~30mohm SCD1U50V3KX-GP D D D D U52 SI4800BDY-T1 Id=7A Qg=8.7~13nC Rdson=23~30mohm C479 C484 SCD1U50V3KX-GP SC10U25V6KX-1GP D Iomax=6A Cyntec 7*7*3 DCR=30mohm, Irating=6A OCP>9A S 3D3V_PWR C485 DY SC10U25V6KX-1GP DY SC10U25V6KX-1GP 2 C482 C481 SC10U25V6KX-1GP C823 SCD1U50V3KX-GP SC2D2U10V3KX-1GP C 1 DCBATOUT_51125_3V 3 2 Sheet 1 -1 43 of 59 5 4 DCBATOUT 3 2 DCBATOUT_51117_1D8V 1 DCBATOUT_51117_1D8V G86 2 1 EN_PSV TON TRIP 3 6 7 8 15 1D8V_PWR 1 2 2 1 4 3 2 1 2 1 2 1 1 GAP-CLOSE-PWR G102 1 2 GAP-CLOSE-PWR G100 1 2 GAP-CLOSE-PWR G94 1 2 GAP-CLOSE-PWR G95 1 2 GAP-CLOSE-PWR G104 1 2 Id=5A Qg=8.7~13nC, Rdson=23~30mohm 3D3V_S5 TPS51117RGYR-GP C GAP-CLOSE-PWR R404 10KR2J-3-GP 2 74.51117.073 2 R397 16KR2F-GP 2008/10/17 2 VOUT PGOOD GND PGND GND 1 12 VFB VBST R421 47KR2F-GP 2 5 6 7 8 1 2 1 1 1 2 2 1 2 1 2 1 1 R413 2 1D8V_RUN ON 0R2J-2-GP 51117_TON 1 R414 2 2 249KR2F-GP 51117_TRIP1 11 LL 51117_LL TC23 2ND = 77.93971.02L 20081128 51117_DRVH 51117_DRVL DRVH DRVL TC24 SE390U2D5VM-2GP 5 14 13 9 V5FILT V5DRV 51117_1D8V_VFB S DY ST220U2D5VDM-13GP R420 63K4R2F-2-GP C837 DY DY SCD1U10V2KX-4GP 4 10 2ND = 83.R5003.H8H 3RD = 83.5R003.08F 12,34,46 PM_SLP_S5# G U54 51117_1D8V_VFB 51117_VBST C U49 SI4172DY-T1-GE3-GP C841 SCD1U16V2KX-3GP S S S G C830 SC1U10V2KX-1GP D19 CH551H-30PT-GP 83.R5003.C8F C831 1 68.1R510.10J 2ND = 68.1R51A.10G SC18P50V2JN-1-GP 2 51117_V5FILT GAP-CLOSE-PWR G98 1 2 Vo(cal)=1.8046V 2 IND-1D5UH-34-GP D D D D 5V_S5 1D8V_PWR L63 D GAP-CLOSE-PWR G96 1 2 Iomax=6A OCP>9A 1 R417 300R3F-GP D GAP-CLOSE-PWR G92 1 2 S 5V_S5 C812 SC1U10V2KX-1GP 1 1 2 D D D D 5 6 7 8 Id=5A Qg=8.7~13nC, G Rdson=23~30mohm 2 GAP-CLOSE-PWR G90 1 2 4 3 2 1 GAP-CLOSE-PWR 1D8V_S3 G87 1 G S S S 84.04800.D37 D 1D8V_PWR C796 SCD1U50V3KX-GP U48 SI4800BDY-T1 C788 SC10U25V6KX-1GP D GAP-CLOSE-PWR G84 1 2 C793 SC10U25V6KX-1GP GAP-CLOSE-PWR G85 1 2 2 1 1D8V_S3_PWRGD 39 20090108_SB Wayne B B SJV50 A A Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title TPS51124_1D8V/1D2V Size A3 Document Number Rev SJV50-PU Date: Wednesday, February 25, 2009 5 4 3 2 Sheet 1 -1 44 of 59 5 4 2 DCBATOUT_51124 G6 SA_20081112 2 1D1V_PWR GAP-CLOSE-PWR G7 1 2 1 2 2 S 1 5 6 7 8 G 4 3 2 1 1 S S S G GAP-CLOSE-PWR G41 1 2 GAP-CLOSE-PWR G43 1 2 Iomax=8A G49 2 1 1 2 1 2 2 1 GAP-CLOSE-PWR G54 1 2 C 24 7 TP47 TPAD14-GP Change 4.7u 1 R213 30KR2F-GP 1 1 TC10 2 4 3 2 1 GAP-CLOSE-PWR G63 1 2 TC11 2 2 2 DY 51124_VFB2 84.04812.A37 2ND = 84.08878.037 SCD1U16V2KX-3GP 1 1 R33 17K8R2F-GP 5 6 7 8 2 U31 SI4812BDY-T1-E3-GP 1 2 10KR2J-3-GP 51124_VBST2 1 C41 1 R209 0R2J-2-GP S S S G 2 DY GAP-CLOSE-PWR G62 1 2 SE390U2D5VM-2GP 51124_LL2 DY R202 DY C572 1D2V_PWR 2ND = 77.93971.02L 51124_VBST1 SCD1U16V2KX-3GP 51124_V5FILT A TONSEL OPEN V5FILT 240k/CH1 300k/CH2 300k/CH1 360k/CH2 360k/CH1 420k/CH2 B GAP-CLOSE-PWR G64 1 2 GAP-CLOSE-PWR G65 1 2 GAP-CLOSE-PWR G66 1 2 SA_20081117 GND 2 GAP-CLOSE-PWR G61 1 2 1D2V Iomax=5A OCP>10A ST220U2D5VDM-13GP C23 1 1 GAP-CLOSE-PWR G60 1 2 SCD1U10V2KX-4GP 68.1R510.10K 2ND = 68.1R510.10Y D D D D 2 2 2 L41 1 2 IND-1D5UH-23-GP 20090108_SB Wayne 51124_LL1 C561 2 1 5 6 7 8 84.04800.D37 2ND = 84.08884.037 C562 2 1 2 2 R203 10K5R2F-GP 1D2V_S0 G59 1 51124_TRIP1 51124_TRIP2 R193 11KR2F-L-GP U34 SI4800BDY-T1 TPS51124RGER-GPU1 74.51124.073 S S S G B 1D2V_PWR C558 51124_TONSEL 1 DY DRVH2 LL2 DRVL2 51124_DRVH2 51124_LL2 51124_DRVL2 10 11 12 1 17 14 BC1 SCD47U6D3V2KX-GP SA_20081112 4 3 2 1 GND GND PGND2 PGND1 PGOOD1 PGOOD2 3 25 13 18 51124_DRVH1 51124_LL1 51124_DRVL1 21 20 19 DCBATOUT_51124 TONSEL EN1 EN2 4 23 8 VBST1 VBST2 51124_EN1 51124_EN2 DRVH1 LL1 DRVL1 SCD1U25V3KX-GP V5FILT V5IN SC10U25V6KX-1GP 15 16 SC10U25V6KX-1GP 51124_V5FILT VO1 VO2 VFB1 VFB2 DY D D D D 1 1 6 U32 GAP-CLOSE-PWR G53 1 2 Close to VFB Pin (pin5) 1D1V_PWRGD 39 1D2V_PWRGD 2 5 2 BC2 SC1U10V2KX-1GP 1 1KR2J-1-GP 2 2 2 1 1 1 C550 SC1U10V2KX-1GP 22 9 2 S GAP-CLOSE-PWR G52 1 2 SA_20081117 1D1V_PWRGD TRIP1 TRIP2 1 2 SC180P50V2JN-1GP R191 2 VCORE_EN C546 1 R206 39K2R2F-L-GP TC7 GAP-CLOSE-PWR 1D2V_PWR 1D1V_PWR 51124_VFB2 51124_VFB1 2 100KR2J-1-GP G DY TC8 2 R199 1 39,41 VCORE_EN R200 2R3J-GP 2 SC4D7U6D3V3KX-GP C DY 1 10KR2J-3-GP 10KR2J-3-GP C539 51124_VFB1 R190 DY C552 2 5 6 7 8 R198 R28 18KR2F-GP S S S G 1 5V_S5 68.1R01A.20B 2ND = 68.1R10A.10S SCD1U10V2KX-4GP 3D3V_S0 GAP-CLOSE-PWR U30 SI4172DY-T1-GE3-GP SE390U2D5VM-2GP 3D3V_S0 2ND = 77.93971.02L D 2 0R2J-2-GP GAP-CLOSE-PWR G44 1 2 ST220U2D5VDM-13GP 1 R18 D D D D GAP-CLOSE-PWR G51 1 2 1D1V_PWR Vo(cal)=1.1060V L39 1 2 COIL-1UH-34-GP-U 1 Vtrip(mV)=Rtrip(Kohm)*10(uA) Iocp=(Vtrip/Rdson)+((1/(2*L*f))*((Vin-Vout)*Vout)/Vin)) 2 4 3 2 1 1 GAP-CLOSE-PWR G50 1 2 D GAP-CLOSE-PWR G42 1 2 DCBATOUT_51124_1 1 2 84.04800.D37 2ND = 84.08884.037 C533 SC10U25V6KX-1GP SI4800BDY-T1 TC9 SE68U25VM-3-GP C532 SC10U25V6KX-1GP D D D D U28 GAP-CLOSE-PWR 2 GAP-CLOSE-PWR G40 1 2 C534 SCD1U25V3KX-GP D D 39,41 G39 1 GAP-CLOSE-PWR G8 1 2 79.68612.30L 2nd = 79.68612.L01 DCBATOUT 1D1V_S0 DCBATOUT_51124_1 1 1 20081203 1 2 DCBATOUT 3 GAP-CLOSE-PWR SJV50 A Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Vout=0.758V*(R1+R2)/R2 --> PWM mode Vout=0.764V*(R1+R2)/R2 --> Skip Mode Title Size A3 TPS51124_1D1V_1D2V Document Number 5 4 3 2 Rev -1 SJV50-PU Date: Wednesday, February 25, 2009 Sheet 1 45 of 59 4 11 1 2 C817 NC#4 4 1 VOUT D C761 SC1U10V2KX-1GP 2 C735 SC2D2U10V3KX-1GP G9091-120T11U-GP 74.09091.K3F Place near to SB600 GAP-CLOSE-PWR G91 1 2 1 C816 VIN GND EN 1D2V_S5 5 1 1 RT9026PFP-GP 74.09026.079 2ND = 74.02997.A79 3RD = 74.51110.B79 SC10U6D3V3MX-GP C827 SCD1U10V2KX-4GP 2 GAP-CLOSE-PWR G89 1 2 1 2 3 4 5 SC10U6D3V3MX-GP DDR_VREF_S3 G88 2 VIN VDDQSNS S5 VLDOIN GND VTT S3 PGND VTTREF VTTSNS GND 10 9 8 7 6 1 2 3 0D9V_S3 1 1 51100_S5 1 R412 0R2J-2-GP 2 151100_S3 R411 0R2J-2-GP 2 12,34,44 PM_SLP_S5# U21 OCP>3A DDR_VREF_PWR 2 U53 3D3V_S5 C814 2 2 D 1 1D8V_S3 SC10U6D3V3MX-GP C829 SC10U10V5KX-2GP 2 1D2V_S5 Iomax=0.2A 0D9V_S3 Iomax=1.4A 1 5V_S5 3 2 5 GAP-CLOSE-PWR G93 1 2 GAP-CLOSE-PWR C C 1D5V_S0 Iomax=1A G957 2D5V_S0 Iomax=200mA 1D5V_S0_LDO OCP>430mA 1 3D3V_S0 U23 1D5V_S0 G58 1 C589 2D5V_S0 2 GAP-CLOSE-PWR-3-GP G57 1 2 2 SC10U6D3V5KX-1GP VOUT 5 NC#4 4 G9091-250T11U-GP 2 C392 SC2D2U10V3KX-1GP C389 SC1U10V2KX-1GP GAP-CLOSE-PWR-3-GP VOUT GND VIN 74.09091.T3F 2ND = 74.09198.D7F 3D3V_S0 3 2 1 B 1 2 B U36 1 VIN GND EN 1 1 2 3 G957T65UF-GP 2 74.95765.03C C391 SC1U10V3KX-3GP For MINI Card power SW A A Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title 2D5V/1D5V0D9V Size A3 Document Number Rev 5 4 3 2 -1 SJV50-PU Date: Wednesday, February 25, 2009 Sheet 1 46 of 59 5 4 DCBATOUT 3 2 1 DCBATOUT_8202_VGA G83 2 GAP-CLOSE-PWR G82 1 2 5V_S5 2 1 1 1 4 3 2 1 1 2 1 1 2 2 1 1 1 DIS DIS RT8202_DL_VGA 2 GAP-CLOSE-PWR G75 1 2 GAP-CLOSE-PWR G74 1 2 GAP-CLOSE-PWR G70 1 2 GAP-CLOSE-PWR G77 1 2 DY 2 DIS 2 84.00840.037 2ND:84.07672.037 2 1 5 6 7 8 RT8202_LX_VGA 1 RT8202_OC_VGA_L 1 2 RT8202_FB_VGA 6K2R2F-GP VGA_CORE_PWR DIS GND GND PGND DIS 10 3 VOUT 7 RT8202APQW-GP OC FB 17 6 1 NC#5 NC#14 VGA_CORE G73 SE330U2VDM-L-GP SCD1U25V3ZY-1GP 5 14 VGA_CORE_PWR C775 SE330U2VDM-L-GP DY S S S G 2 C768 EN/DEM DIS U45 SIR840DP-GP DIS Iomax=13A, OCP>20A VGA_CORE_PWR L56 IND-D56UH-12-GP 1 2 RT8202_LX_VGA DIS C784 TC5 DIS 20081201 15 RT8202_DH_VGA SCD1U25V3KX-GP DIS TC19 C 2 10KR2J-3-GP R367 RT8202_BST_VGA_L 1 2 RT8202_DH_VGA 1R2F-GP RT8202_LX_VGA DIS RT8202_DL_VGA R373 SCD1U10V2KX-4GP 1 12,33,34,39,48 PM_SLP_S3# RT8202_EN_VGA 13 12 11 8 D D D D R366 BOOT UGATE PHASE LGATE 2 2 9 VDDP 2 VDD TON PGOOD DIS DIS 4 3 2 1 1 2 2 1 2 RT8202_PGOOD_VGA DIS 16 4 C769 1 2RT8202_LX_VGA DIS C786 SCD1U50V3KX-GP U43 84.00474.037 2ND:84.08672.A37 C787 SC10U25V6KX-1GP C779 SC100P50V2JN-3GP DIS 1 0R0402-PAD-1-GP C778 SC1U10V3ZY-6GP C785 S S S G DIS U46 SIR474DP-T1-GE3-GP SC10U25V6KX-1GP C770 SC1KP50V2KX-1GP DIS CH521S-30-GP-U1 5V_S5 SC10U25V6KX-1GP RT8202_TON_VGA DIS 5 6 7 8 2 D18 C773 SC1U10V3ZY-6GP D D D D 1 DIS R377 2 DCBATOUT_8202_VGA 5V_S5 RT8202_BST_VGA R378 10KR2F-2-GP DIS R376 10R2F-L-GP RT8202_VDD_VGA GAP-CLOSE-PWR DCBATOUT_8202_VGA 3D3V_S0 1 R372 2 1MR2F-GP 20090108_SB D 1 DIS GAP-CLOSE-PWR G80 1 2 1 2 GAP-CLOSE-PWR G81 1 2 TC21 SE100U25VM-L1-GP 1 D 2 1 C GAP-CLOSE-PWR G71 1 2 GAP-CLOSE-PWR G78 1 2 GAP-CLOSE-PWR G79 1 2 RT8202_FB_VGA GAP-CLOSE-PWR G72 1 2 Vout=0.75*(1+Rh/Rl) GAP-CLOSE-PWR R375 12KR2F-L-GP R370 30KR2F-GP 1 B 20081125 DY NV_VID0_R 2 NV_VID1_R 2 DY D D 2 DIS Q22 2N7002-11-GP Q23 2N7002-11-GP DY R369 NV_VID1 1 2 DIS 2 S R368 NV_VID0 G PWRCNTL_1 51 1 G 1 DIS 2 PWRCNTL_0 51 1 84.27002.W31 2ND = 84.27002.Y31 B DIS DY R374 43KR2F-GP R371 36K5R2F-GP 10KR2J-3-GP C771 SCD1U10V2KX-4GP DY 84.27002.W31 2ND = 84.27002.Y31 2 2 1 RT8202_FB_VGA DIS 1 DIS 2 C774 SC47P50V2JN-3GP S 1 1 GAP-CLOSE-PWR G76 1 2 10KR2J-3-GP C772 SCD1U10V2KX-4GP DIS SJV50 A A Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size RT8202A_VGA CORE Document Number Rev -1 SJV50-PU Date: Wednesday, February 25, 2009 5 4 3 2 Sheet 1 47 of 59 5 4 3 2 1 D D C Q18 SI2301BDS-T1-GP 3D3V_S0 D G 1 S R271 100KR2J-1-GP DIS D 2 VDDR3_G DIS DIS R281 G 1 S Q19 VDDR3_GG 1 2 DIS 2N7002E-1-GP B C VDDR3 2 PM_SLP_S3# 12,33,34,39,47 B 68K1R2F-1-GP C655 SCD22U10V3KX-2GP DIS SJV50 Wistron Corporation A 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title VDDR3 Size A4 Document Number Rev Date: Wednesday, February 25, 2009 5 4 3 -1 SJV50-PU 2 Sheet 48 of 1 59 A A B C D E Adaptor in to generate DCBATOUT DCIN1 AD+ GND 6 5 4 1 2 3 NP1 4 K D1 P6SMBJ20A-GP R1 1 2 3 DTA124EUB-GP 84.00124.T1K 2 R5 100KR2J-1-GP 3 1 2 R2 DTC124EUB-GP 84.00124.S1K R9 1KR2J-1-GP 2ND = 84.00124.M1K 3RD = 84.00124.H1K 3 2 3 C6 SCD1U50V3ZY-GP 2 1 AD_OFF R1 ID = -10A/70deg Rds(ON) = 24mohm 84.04433.A37 SO-8 2ND = 84.04407.F37 C5 SCD47U50V5KX-1GP 2ND = 84.00124.N1K 3RD = 84.00124.K1K Q2 Layout Trace 200mil 8 7 6 5 1 R2 2 Q1 1 R6 200KR2F-L-GP EC3 SCD1U50V3ZY-GP D D D D AO4433-GP 1 83.P6SMB.AAG AD+_2 U2 S S S G 2 2 DY 1 22.10037.F11 C3 SCD1U50V3ZY-GP 2 DC-JACK131-GP 34 1 2 3 4 1 Layout Trace 200mil AD+_JK A AD+_JK 58 1 AD+_JK 4 2 1 2 3 4 34 BAT_IN# 34,42 KBC_BAT_CLK 34,42 KBC_BAT_DAT 2 ED5 BAV99-5-GP ED6 BAV99-5-GP DY DY DY 3 RN46 SRN27J-GP 8 7 6 5 1 2 1 ED7 BAV99-5-GP 3 R186 470KR2F-GP BATTERY CONNECTOR 3 1 3D3V_AUX_S5 2 1 3D3V_AUX_S5 BAT1 1 2 3 4 5 6 7 8 9 KBC_BAT_DAT_1 KBC_BAT_CLK_1 BAT_IN#_1 BT+ 1 1 2 2 2 2 2 TYCO-CON7-19-GP EC68 SC100P50V2JN-3GP EC69 G2 2 DY SC100P50V2JN-3GP 42 BATT_SENSE EC70 SC1000P50V3JN-GP-U EC16 SC1000P50V3JN-GP-U EC14 DY 1 DY 1 1 1 DY SCD1U50V3ZY-GP A DY EC15 SCD1U50V3ZY-GP 2ND = 83.5R603.D3F DY 2 K Layout Trace 320mil D7 MM3Z5V6T1G-GP 83.5R603.E3F 2 2 GND GND DAT CLK BAT_IN BT+2 BT+1 GND GND 20.81159.007 20090108 SB modify 1 GAP-CLOSE-PWR KBC_BAT_CLK_1 KBC_BAT_DAT_1 BAT_IN#_1 KBC_BAT_CLK_1 58 KBC_BAT_DAT_1 58 BAT_IN#_1 58 SJV50 1 1 Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title AD/BATT CONN Size A3 Document Number Rev A B C D -1 SJV50-PU Date: Wednesday, February 25, 2009 Sheet E 49 of 59 5 4 3 2 1 1 OF 8 AVGA1A D D PEG_TXP0 PEG_TXN0 PEG_TXP1 PEG_TXN1 PEG_TXP2 PEG_TXN2 PEG_TXP3 PEG_TXN3 AA38 Y37 PCIE_RX0P PCIE_RX0N PCIE_TX0P PCIE_TX0N Y33 Y32 M92_PCIE_RXP0 M92_PCIE_RXN0 Y35 W36 PCIE_RX1P PCIE_RX1N PCIE_TX1P PCIE_TX1N W33 W32 M92_PCIE_RXP1 M92_PCIE_RXN1 W38 V37 PCIE_RX2P PCIE_RX2N PCIE_TX2P PCIE_TX2N U33 U32 M92_PCIE_RXP2 M92_PCIE_RXN2 V35 U36 PCIE_RX3P PCIE_RX3N U38 T37 PCIE_RX4P PCIE_RX4N PEG_TXP5 PEG_TXN5 T35 R36 PCIE_RX5P PCIE_RX5N PEG_TXP6 PEG_TXN6 R38 P37 PCIE_RX6P PCIE_RX6N PEG_TXP7 PEG_TXN7 P35 N36 PCIE_RX7P PCIE_RX7N N38 M37 PCIE_RX8P PCIE_RX8N M35 L36 PCIE_RX9P PCIE_RX9N L38 K37 PCIE_RX10P PCIE_RX10N K35 J36 PCIE_RX11P PCIE_RX11N J38 H37 PCIE_RX12P PCIE_RX12N H35 G36 PCIE_RX13P PCIE_RX13N G38 F37 PCIE_RX14P PCIE_RX14N C PEG_TXP8 PEG_TXN8 PEG_TXP9 PEG_TXN9 PEG_TXP10 PEG_TXN10 PEG_TXP11 PEG_TXN11 PEG_TXP12 PEG_TXN12 B PEG_TXP13 PEG_TXN13 PEG_TXP14 PEG_TXN14 PEG_TXP15 PEG_TXN15 F35 E37 PCIE_RX15P PCIE_RX15N PCI EXPRESS INTERFACE PEG_TXP4 PEG_TXN4 PCIE_TX3P PCIE_TX3N DIS U30 U29 SCD1U16V2KX-3GP 1 2 C259 1 2 PEG_RXP0 PEG_RXN0 2 C262 1 2 PEG_RXP1 PEG_RXN1 2 C278 1 2 PEG_RXP2 PEG_RXN2 DIS SCD1U16V2KX-3GP SCD1U16V2KX-3GP 1 DIS SCD1U16V2KX-3GP SCD1U16V2KX-3GP 1 DIS SCD1U16V2KX-3GP M92_PCIE_RXP3 M92_PCIE_RXN3 DIS C267 DIS C269 SCD1U16V2KX-3GP 1 2 C283 1 2 DIS SCD1U16V2KX-3GP DIS C277 PCIE_TX4P PCIE_TX4N T33 T32 M92_PCIE_RXP4 M92_PCIE_RXN4 SCD1U16V2KX-3GP 1 2 C292 1 2 DIS SCD1U16V2KX-3GP DIS C288 PCIE_TX5P PCIE_TX5N T30 T29 M92_PCIE_RXP5 M92_PCIE_RXN5 SCD1U16V2KX-3GP 1 PCIE_TX6P PCIE_TX6N P33 P32 M92_PCIE_RXP6 M92_PCIE_RXN6 SCD1U16V2KX-3GP 1 PCIE_TX7P PCIE_TX7N P30 P29 M92_PCIE_RXP7 M92_PCIE_RXN7 SCD1U16V2KX-3GP 1 PCIE_TX8P PCIE_TX8N N33 N32 M92_PCIE_RXP8 M92_PCIE_RXN8 PCIE_TX9P PCIE_TX9N N30 N29 M92_PCIE_RXP9 M92_PCIE_RXN9 PCIE_TX10P PCIE_TX10N L33 L32 M92_PCIE_RXP10 M92_PCIE_RXN10 PCIE_TX11P PCIE_TX11N L30 L29 M92_PCIE_RXP11 M92_PCIE_RXN11 PCIE_TX12P PCIE_TX12N K33 K32 M92_PCIE_RXP12 M92_PCIE_RXN12 PCIE_TX13P PCIE_TX13N J33 J32 M92_PCIE_RXP13 M92_PCIE_RXN13 PCIE_TX14P PCIE_TX14N K30 K29 M92_PCIE_RXP14 M92_PCIE_RXN14 PCIE_TX15P PCIE_TX15N H33 H32 M92_PCIE_RXP15 M92_PCIE_RXN15 PCIE_CALRP Y30 M92_PCIE_CALRP PCIE_CALRN Y29 M92_PCIE_CALRN 2 C299 1 DIS SCD1U16V2KX-3GP 2 2 C303 1 2 SCD1U16V2KX-3GP DIS C310 SCD1U16V2KX-3GP 1 PEG_RXP8 PEG_RXN8 2 C330 1 2 PEG_RXP9 PEG_RXN9 2 C318 1 2 PEG_RXP10 PEG_RXN10 2 C347 1 2 PEG_RXP11 PEG_RXN11 2 C327 1 2 PEG_RXP12 PEG_RXN12 2 C354 1 2 PEG_RXP13 PEG_RXN13 2 C362 1 2 PEG_RXP14 PEG_RXN14 2 C360 1 2 PEG_RXP15 PEG_RXN15 DIS SCD1U16V2KX-3GP SCD1U16V2KX-3GP 1 DIS SCD1U16V2KX-3GP SCD1U16V2KX-3GP 1 DIS SCD1U16V2KX-3GP SCD1U16V2KX-3GP 1 DIS SCD1U16V2KX-3GP SCD1U16V2KX-3GP 1 DIS SCD1U16V2KX-3GP SCD1U16V2KX-3GP 1 C PEG_RXP6 PEG_RXN6 2 DIS SCD1U16V2KX-3GP 1 PEG_RXP5 PEG_RXN5 2 C316 1 SCD1U16V2KX-3GP DIS SCD1U16V2KX-3GP PEG_TXN[15..0] PEG_RXP4 PEG_RXN4 PEG_RXP7 PEG_RXN7 DIS PEG_TXP[15..0] 8 PEG_TXP[15..0] 8 PEG_TXN[15..0] 2 SCD1U16V2KX-3GP SCD1U16V2KX-3GP 1 PEG_RXP3 PEG_RXN3 2 C320 1 DIS PEG_RXN[15..0] 8 PEG_RXN[15..0] DIS C293 DIS SCD1U16V2KX-3GP PEG_RXP[15..0] 8 PEG_RXP[15..0] DIS C273 DIS C314 DIS C321 DIS C340 DIS C309 DIS C355 DIS C335 B DIS C345 DIS C366 DIS C364 CLOCK 3 CLK_PCIE_PEG 3 CLK_PCIE_PEG# AB35 AA36 PCIE_REFCLKP PCIE_REFCLKN AJ21 AK21 AH16 NC#AJ21 NC#AK21 NC_PWRGOOD R136 CALIBRATION PLT_RST1#_B 1 2 PLT_RST1#_M92 R356 470R2J-2-GP AA30 DIS 1 R143 DIS 11,25,31,32,34,35,58 1 1K27R2F-L-GP 1D1V_S0 2 2 DIS 2KR2F-3-GP PERST# M92-M2-GP 20090108_SB SJV50 A A Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title M92 (1/7)_PCIE Size A3 Document Number Rev SJV50-PU Date: Wednesday, February 25, 2009 5 4 3 2 Sheet 1 -1 50 of 59 5 4 20090106_SB modify 2 2 DPD HYNIX-SAMSUNG I2C PH at LCD conn. TP128 TP138 TP131 TP132 TP149 TP141 TP139 TP134 TP142 TP136 TP146 2 DIS 1D8V_S0 AK24 TX5P_DPB0P TX5M_DPB0N AT33 AU32 AU14 AV13 TX0P_DPC2P TX0M_DPC2N AT15 AR14 TX1P_DPC1P TX1M_DPC1N AU16 AV15 TX2P_DPC0P TX2M_DPC0N AT17 AR16 TXCDP_DPD3P TXCDM_DPD3N AU20 AT19 TX3P_DPD2P TX3M_DPD2N AT21 AR20 TX4P_DPD1P TX4M_DPD1N AU22 AV21 TX5P_DPD0P TX5M_DPD0N AT23 AR22 R R# AD39 AD37 R325 1 G G# AE36 AD35 R321 1 B B# AF37 AE38 R319 1 HSYNC VSYNC AC36 AC38 DIS DIS C204 SCD1U16V2KX-3GP AN31 DPLL_VDDC AV33 AU34 XTALIN XTALOUT 2 GPU_DPLUS GPU_DMINUS AF29 AG29 DPLUS DMINUS AK32 AJ32 AJ33 TS_FDO TSVDD TSVSS For Thermal sensor DIS TP133 1 2 TXCLK_LP_DPE3P TXCLK_LN_DPE3N AP34 AR34 LVDS_M92_TXACLK+ 18 LVDS_M92_TXACLK- 18 TXOUT_L0P_DPE2P TXOUT_L0N_DPE2N AW37 AU35 LVDS_M92_TXAOUT0+ 18 LVDS_M92_TXAOUT0- 18 TXOUT_L1P_DPE1P TXOUT_L1N_DPE1N AR37 AU39 LVDS_M92_TXAOUT1+ 18 LVDS_M92_TXAOUT1- 18 TXOUT_L2P_DPE0P TXOUT_L2N_DPE0N AP35 AR35 LVDS_M92_TXAOUT2+ 18 LVDS_M92_TXAOUT2- 18 TXOUT_L3P TXOUT_L3N AN36 AP37 R129 M92_RSET 1 499R2F-2-GP AVSSQ DIS 2 DAC1_AVDD VDD1DI VSS1DI AC33 AC34 DAC1_VDD1DI R2 R2# AC30 AC31 1VGA_TS_VDD THERMAL AVSSQ DIS G2 G2# AD30 AD31 B2 B2# AF30 AF31 C Y COMP AC32 AD32 AF32 1 4 3 DIS DIS H2SYNC V2SYNC AD29 AC29 VDD2DI VSS2DI AG31 AG32 DAC2_VDD2DI 1 R133 2 0R0402-PAD 1D8V_S0 DAC2_A2VDD 1 R113 2 0R0402-PAD VDDR3 1D8V_S0 DIS DIS L29 1 2 BLM15BD121SN1D-GP DIS 1 R126 2 0R0402-PAD AVSSQ B A2VDD AG33 A2VDDQ AD33 A2VSSQ AF33 VDDR3 -1 090219 R127 AA29 M92_R2SET 1 2 DIS SA_20081104 AUX1P AUX1N AM27 AL27 DDC2CLK DDC2DATA AM19 AL19 AUX2P AUX2N AN20 AM20 DDCCLK_AUX3P DDCDATA_AUX3N AL30 AM30 DDCCLK_AUX4P DDCDATA_AUX4N AL29 AM29 DDCCLK_AUX5P DDCDATA_AUX5N AN21 AM21 M92_CRT_CLK 19 M92_CRT_DAT 19 2 DDC1CLK DDC1DATA AM26 AN26 DDC6CLK DDC6DATA AJ30 AJ31 NC_DDCCLK_AUX7P NC_DDCDATA_AUX7N AK30 AK29 SA_20081104 25,32,33,34,38,58 25,32,33,34,38,58 HDMI_M92_CLK 20 HDMI_M92_DAT 20 KBC_THERM_CLK KBC_THERM_DAT G68 1GAP-CLOSE 2 1 2 GAP-CLOSE G69 KBC_THERM_G781_CLK 8 KBC_THERM_G781_DAT 7 G781_ALERT# 6 5 DIS SMBCLK VCC SMBDATA DXP ALERT# DXN GND THERM# 1 2 3 4 GPU_DPLUS GPU_DMINUS GPU_THERM# DIS DIS G781P8F-GP VDDR3 R262 2K2R2F-GP R270 2K2R2F-GP DIS Q21 MMBT3904-4-GP DIS B DIS C230 HDMI_M92_HPD 20 VDDR3 HPD1_M92 A R276 10KR2J-3-GP SJV50 Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. DIS Title M92 (2/7)_ IO Size A2 Document Number Rev SJV50-PU Date: Wednesday, February 25, 2009 5 C626 SCD1U16V2KX-3GP U38 SA_20081030 2 2 DIS 1 2 BLM15BD121SN1D-GP -1 090219 C130 SC10U6D3V5KX-1GP 1 C146 SCD1U16V2KX-3GP 1 DIS L30 DAC1_VDD1DI 2 TSVDD 2 1 1 DIS 2 DIS M92_HSYNC 19,54 M92_VSYNC 19,54 C242 SC10U6D3V5KX-1GP DIS AD34 AE34 1D8V_S0 2 CRT_BLUE 19 2 150R2F-1-GP M92-M2-GP DIS 2 L21 1 AF35 AG36 CRT_GREEN 19 2 150R2F-1-GP DIS BLM15BD121SN1D-GP LVDS_M92_TXBOUT2+ 18 LVDS_M92_TXBOUT2- 18 TXOUT_U3P TXOUT_U3N 2 DPLL_PVDD DPLL_PVSS DIS 1MR2F-GP R461 2 AM32 AN32 20090106_SB add 1D8V_S0 LVDS_M92_TXBOUT1+ 18 LVDS_M92_TXBOUT1- 18 AG38 AH37 C DIS X6 XTAL-27MHZ-74-GP C137 SC1U10V3KX-3GP A C854 1 1 3 4 XTALIN XTALOUT 1 2 AH35 AJ36 TXOUT_U2P_DPF0P TXOUT_U2N_DPF0N RN22 SRN10KJ-5-GP SC2200P50V2KX-2GP SC27P50V2JN-2-GP DPLL_VDDC DIS 82.30034.611 2ND = 82.30034.421 TXOUT_U1P_DPF1P TXOUT_U1N_DPF1N D DIS 1 DDC/AUX PLL/CLOCK C853 1 LVDS_M92_TXBOUT0+ 18 LVDS_M92_TXBOUT0- 18 715R2F-GP Depending on OSC used select voltage divider resist values R25 R70 to ensure XTALIN voltage level of 1.8V 2 LVDS_M92_TXBCLK+ 18 LVDS_M92_TXBCLK- 18 AJ38 AK37 DAC1_AVDD DIS AB34 R2SET DPLL_PVDD SC27P50V2JN-2-GP AK35 AL36 CRT_RED 19 2 150R2F-1-GP DIS 2 2 DIS TXCLK_UP_DPF3P TXCLK_UN_DPF3N M92-M2-GP RSET VREFG 1 1 R111 249R2F-GP AH13 DIS AVDD AVSSQ HPD1 = 0.6V) VGA_VREFG BLON_IN 9,34 LCDVDD_ON 18 TXOUT_U0P_DPF2P TXOUT_U0N_DPF2N C220 SC1U6D3V2KX-GP GPIO_0 GPIO_1 GPIO_2 GPIO_3_SMBDATA GPIO_4_SMBCLK GPIO_5_AC_BATT DAC1 GPIO_6 GPIO_7_BLON GPIO_8_ROMSO GPIO_9_ROMSI GPIO_10_ROMSCK GPIO_11 GPIO_12 GPIO_13 GPIO_14_HPD2 GPIO_15_PWRCNTL_0 GPIO_16_SSIN GPIO_17_THERMAL_INT GPIO_18_HPD3 GPIO_19_CTF GPIO_20_PWRCNTL_1 GPIO_21_BB_EN GPIO_22_ROMCSB GPIO_23_CLKREQB JTAG_TRSTB JTAG_TDI JTAG_TCK JTAG_TMS JTAG_TDO GENERICA GENERICB GENERICC GENERICD GENERICE_HPD4 DAC2 GENERICF GENERICG 2 VDDR4,5(1.8V) / 3 BRIGHTNESS_AMD 9 R465 LVTMDP DIS VREFG VOLTAGE DIVIDER IS (VREFG = R464 1 2 R114 499R2F-2-GP SA_20081104 TXCCP_DPC3P TXCCM_DPC3N 1 DIS C 1 HPD1_M92 TMDS_A_TX2+ 8,20 TMDS_A_TX2- 8,20 DY 2 1 R290 1KR2J-1-GP 1 Back Bias (body bias) which minimizes power consumption in battery modes. PD = Disable PU = Enable B 1 TP222 SA_20081104 DIS 2 0R2J-2-GP 1 TP127 PWRCNTL_1 R295 1 2 10KR2J-3-GP 54 GPIO_VGA_22 AR32 AT31 TMDS_A_TX1+ 8,20 TMDS_A_TX1- 8,20 4 SRN0J-10-GP-U 3 0R2J-2-GP 1 47 TX4P_DPB1P TX4M_DPB1N 4 SRN0J-10-GP-U 3 M92_VARY_BL 2 TP126 DY SA_20081103 1 1 AV31 AU30 DIS 1 2 1 PWRCNTL_0 1 TP143 AR30 AT29 TX3P_DPB2P TX3M_DPB2N 1 2 RN57 2 TP129 47 TXCBP_DPB3P TXCBM_DPB3N RN58 AK27 AJ27 C243 SC10U6D3V5KX-1GP 1 1 TP147 54 GPIO_VGA_11 54 GPIO_VGA_12 54 GPIO_VGA_13 TX2P_DPAP0 TX2M_DPAN0 TMDS_A_TX0+ 8,20 TMDS_A_TX0- 8,20 1 1 TP137 2 0R2J-2-GP 54 GPIO_VGA_08 54 GPIO_VGA_09 DY 1 TX1P_DPAP1 TX1M_DPAN1 AT27 AR26 4 SRN0J-10-GP-U 3 2 R94 BLON_IN 2 9,34 AH20 AH18 AN16 AH23 AJ23 AH17 GPIO_VGA_06 AJ17 GPIO_VGA_07_BLON AK17 AJ13 AH15 GPIO_VGA_10 AJ16 AK16 AL16 AM16 GPIO_VGA_14 AM14 AM13 CLK_27M_SSIN_M92 AK14 THERMAL_INT AG30 GPIO_VGA_18 AN14 VGA_CTF AM17 AL13 VGA_BB_EN AJ14 AK13 VGA_CLKREQ AN13 JTAG_TRSTB AM23 JTAG_TDI AN23 1 1 JTAG_TCK AK23 1 JTAG_TMS AL24 1 JTAG_TDD AM24 AJ19 1 GENERICA AK19 1 GENERICB 1 GENERICC AJ20 1 GENERICD AK20 AJ24 1 GENERICE_HPD4 AH26 1 GENERICF 1 GENERICG AH24 GPIO_VGA_03 GPIO_VGA_04 AU26 AV25 TX2P_DPA0P TX2M_DPA0N DIS VARY_BL DIGON C261 SC1U6D3V2KX-GP DIS 1 1 TX1P_DPA1P TX1M_DPA1N 1 2 LVDS CONTROL 1 1 TP148 TP144 54 GPIO_VGA_05 RN59 TMDS_A_TXC+ 8,20 TMDS_A_TXC- 8,20 2 54 GPIO_VGA_00 54 GPIO_VGA_01 54 GPIO_VGA_02 R63 10KR2J-3-GP TX0P_DPAP2 TX0M_DPAN2 4 SRN0J-10-GP-U 3 SCL SDA GENERAL PURPOSE I/O 3D3V_S0 AT25 AR24 DIS C221 SCD1U16V2KX-3GP AK26 AJ26 18 M92_LCD_CLK 18 M92_LCD_DAT C TX0P_DPA2P TX0M_DPA2N 1 2 1 1 1 1 SAMSUNG HYNIX-SAMSUNG RN60 E 2 R316 DPC TXCAP_DPAP3 TXCAM_DPAN3 1 2 2 1 MEM_ID0 MEM_ID1 MEM_ID2 MEM_ID3 DPB AU24 AV23 2 PLL DVPCNTL_MVP_0 DVPCNTL_MVP_1 DVPCNTL_0 DVPCNTL_1 DVPCNTL_2 DVPCLK DVPDATA_0 DVPDATA_1 DVPDATA_2 DVPDATA_3 DVPDATA_4 DVPDATA_5 DVPDATA_6 DVPDATA_7 DVPDATA_8 DVPDATA_9 DVPDATA_10 DVPDATA_11 DVPDATA_12 DVPDATA_13 DVPDATA_14 DVPDATA_15 DVPDATA_16 DVPDATA_17 DVPDATA_18 DVPDATA_19 DVPDATA_20 DVPDATA_21 DVPDATA_22 DVPDATA_23 TXCAP_DPA3P TXCAM_DPA3N C260 SCD1U16V2KX-3GP 1 DIS 2 SCD1U16V2KX-3GP C160 1 2 1 2 SC10U6D3V5KX-1GP C133 DIS VRAM 10KR2J-3-GP 10KR2J-3-GP 2 R314 10KR2J-3-GP 10KR2J-3-GP 2 R310 VRAM 1 1 1 SAMSUNG HYNIX 1 DPA AR8 AU8 AP8 AW8 AR3 AR1 AU1 AU3 AW3 AP6 AW5 AU5 AR6 AW6 AU6 AT7 AV7 AN7 AV9 AT9 AR10 AW10 AU10 AP10 AV11 AT11 AR12 AW12 AU12 AP12 R318 10KR2J-3-GP 10KR2J-3-GP 2 R312 10KR2J-3-GP 10KR2J-3-GP 2 R307 HYNIX MUTI GFX SA_20081103 DVPDATA [3:0] 0100 64Mx16 Hynix 1000 64Mx16 Samsung 1100 64Mx16 Qimonda 1D8V_S0 R306 SC1U10V2KX-1GP DIS C153 7 OF 8 AVGA1G 2 DIS BLM15BD121SN1D-GP R305 2 OF 8 AVGA1B DIS DPLL_VDDC 1 1D1V_S0 1 1 SCD1U16V2KX-3GP C159 1 1 2 C152 DIS 2 SC1U10V2KX-1GP DIS L19 D 2 2 DIS BLM15BD121SN1D-GP SC10U6D3V5KX-1GP C131 1 1D8V_S0 3 DPLL_PVDD L20 4 3 2 1 Sheet -1 51 of 59 3 2 1D8V_S0 2 PLL PCIE_PVDD H7 H8 PCIE-PLL 40mA L53 AB37 1 SCD1U16V2KX-3GP C696 2 1 DIS SC1U6D3V2KX-GP C697 DIS 2 2 SC10U6D3V5KX-1GP DIS C698 1 1 2 BLM15BD121SN1D-GP AM10 SPV10 L47 NC_MPV18#1 NC_MPV18#2 NC_SPV18 AN9 SPV10 AN10 SPVSS AA13 Y13 BBP BBP DIS Core-PLL 120mA ISOLATED CORE I/O DIS 1 1 1 2 2 1 1 C359 SC10U6D3V5KX-1GP 2 1 2 2 C328 SC1U6D3V2KX-GP 1 C307 SC1U6D3V2KX-GP 1 C323 SC1U6D3V2KX-GP 2 2 1 C313 SC1U6D3V2KX-GP 1 C348 SC1U6D3V2KX-GP 2 DIS DIS C257 SC1U6D3V2KX-GP DIS C271 SC1U6D3V2KX-GP 2 1 DIS C284 SC1U6D3V2KX-GP 2 1 DIS C266 SC1U6D3V2KX-GP 2 1 DIS C280 SC1U6D3V2KX-GP 2 1 DIS C298 SC1U6D3V2KX-GP 2 1 DIS C227 SC1U6D3V2KX-GP 2 1 C226 SC1U6D3V2KX-GP 2 1 C312 SC1U6D3V2KX-GP 2 1 C238 SC1U6D3V2KX-GP 2 1 C247 SC1U6D3V2KX-GP 2 1 C246 SC1U6D3V2KX-GP 2 1 C214 SC1U6D3V2KX-GP 2 1 1 2 DIS C748 SC1U6D3V2KX-GP C750 SC1U6D3V2KX-GP 2 1 1 DIS DIS C744 SC10U6D3V5KX-1GP 1 DIS C759 SC10U6D3V5KX-1GP DIS 2 C749 SC1U6D3V2KX-GP 2 1 C747 SC1U6D3V2KX-GP 2 1 1 DIS DIS 2 DIS DIS 2 DIS C753 SC10U6D3V5KX-1GP DIS C746 SC1U6D3V2KX-GP 2 1 DIS C745 SC1U6D3V2KX-GP 2 1 DIS 1 DIS C319 SC1U6D3V2KX-GP 2 1 DIS C263 SC1U6D3V2KX-GP 2 1 DIS C219 SC1U6D3V2KX-GP 2 1 DIS C274 SC1U6D3V2KX-GP 2 1 DIS C224 SC1U6D3V2KX-GP 2 1 DIS C209 SC1U6D3V2KX-GP 2 1 C248 SC1U6D3V2KX-GP 2 1 M15 N13 R12 T12 C250 SC1U6D3V2KX-GP 2 1 VDDCI VDDCI VDDCI VDDCI DIS B VGA_CORE 2A DIS M92-M2-GP DIS 2 SC10U6D3V5KX-1GP C155 SCD1U16V2KX-3GP C187 2 1 1 DIS 2 2 DIS SC1U6D3V2KX-GP C181 1 SC1U6D3V2KX-GP C180 1 2 BLM15BD121SN1D-GP DIS DIS BACK BIAS VGA_CORE VGA_CORE PCIE_PVDD DIS C 2 1D8V_S0 B DIS C742 SC10U6D3V5KX-1GP VDDRHB VSSRHB DIS 2 V12 U12 1D1V_S0 DIS DIS DIS C756 SC10U6D3V5KX-1GP VDDRHB DIS DIS 1 VDDRHA VSSRHA DIS 2 M20 M21 1 VDDRHA DIS C265 SC1U6D3V2KX-GP DIS 1 2 BLM15BD121SN1D-GP C372 SC1U6D3V2KX-GP DIS 2 L31 DIS 1 MEM CLK 1D8V_S0 DIS 1 C324 SC1U6D3V2KX-GP DIS DIS 2 VDDR4 VDDR4 VDDR4 VDDR4 DIS C282 SC1U6D3V2KX-GP AD12 AF11 AF12 AG11 DIS D VGA_CORE 1 VDDR5 VDDR5 VDDR5 VDDR5 AA15 AA17 AA20 AA22 AA24 AA27 AB13 AB16 AB18 AB21 AB23 AB26 AB28 AC12 AC15 AC17 AC20 AC22 AC24 AC27 AD13 AD16 AD18 AD21 AD23 AD26 AF17 AF20 AF22 AG16 AG18 AG21 AH22 M16 M18 M23 M26 N15 N17 N20 N22 N24 N27 R13 R16 R18 R21 R23 R26 T15 T17 T20 T22 T24 T27 U16 U18 U21 U23 U26 V15 V17 V20 V22 V24 V27 Y16 Y18 Y21 Y23 Y26 Y28 AH27 AH28 2 AF13 AF15 AG13 AG15 VRAM-CLK L32 1 2 BLM15BD121SN1D-GP 1 2 VDDR3 VDDR3 VDDR3 VDDR3 VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC DIS C281 SC1U6D3V2KX-GP 1 2 1 1D8V_S0 AF23 AF24 AG23 AG24 I/O DIS DIS VDD_CT VDD_CT VDD_CT VDD_CT DIS PCIE_Core 1920mA C264 SC1U6D3V2KX-GP 2 1 1 DIS 2 2 DIS AF26 AF27 AG26 AG27 DIS C361 SC10U6D3V5KX-1GP G30 G31 H29 H30 J29 J30 L28 M28 N28 R28 T28 U28 C350 SC1U6D3V2KX-GP PCIE_VDDC PCIE_VDDC PCIE_VDDC PCIE_VDDC PCIE_VDDC PCIE_VDDC PCIE_VDDC PCIE_VDDC PCIE_VDDC PCIE_VDDC PCIE_VDDC PCIE_VDDC LEVEL TRANSLATION C200 SC1U6D3V2KX-GP 1 C215 SC1U6D3V2KX-GP 1 DIS 2 2 C211 SC1U6D3V2KX-GP 1 C236 SC1U6D3V2KX-GP 1 2 DIS DIS C275 SC1U6D3V2KX-GP C276 SC1U6D3V2KX-GP DIS 2 DIS 2 AA31 AA32 AA33 AA34 V28 W29 W30 Y31 CORE DIS DIS PCIE_VDDR PCIE_VDDR PCIE_VDDR PCIE_VDDR PCIE_VDDR PCIE_VDDR PCIE_VDDR PCIE_VDDR 1 1 C338 SC1U6D3V2KX-GP 2 1 C342 SC1U6D3V2KX-GP 2 1 DIS 2 2 2 2 DIS DIS C332 SC1U6D3V2KX-GP 1 C339 SC1U6D3V2KX-GP 1 C336 SC1U6D3V2KX-GP 1 2 1 DIS 2 C237 SC1U6D3V2KX-GP 1 C325 SC1U6D3V2KX-GP 2 1 C326 SC1U6D3V2KX-GP 2 2 1 2 C229 SC1U6D3V2KX-GP 1 C343 SC1U6D3V2KX-GP 1 C333 SC1U6D3V2KX-GP 2 2 1 2 C239 SC1U6D3V2KX-GP 1 C346 SC1U6D3V2KX-GP 1 C322 SC1U6D3V2KX-GP 2 1 C315 SC1U6D3V2KX-GP 1 2 1 C317 SC1U6D3V2KX-GP 1 2 DIS DIS C691 SC10U6D3V5KX-1GP 1 2 2 C692 SC1U6D3V2KX-GP 1 C693 SC1U6D3V2KX-GP DIS 1 1 C295 SC1U6D3V2KX-GP 1 DIS DIS DIS VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 POWER SC10U6D3V5KX-1GP C194 1D8V_S0 2 DIS DIS 10ux1, 1ux3 DIS C308 SC1U6D3V2KX-GP DIS VDD_CT DIS DIS DIS DIS DIS DIS AC7 AD11 AF7 AG10 AJ7 AK8 AL9 G11 G14 G17 G20 G23 G26 G29 H10 J7 J9 K11 K13 K8 L12 L16 L21 L23 L26 L7 M11 N11 P7 R11 U11 U7 Y11 Y7 10ux1, 1ux4 110mA L34 1 2 BLM15BD121SN1D-GP VDDR3 C337 2 SC10U6D3V5KX-1GP 1D8V_S0 DIS DIS 1 2 DIS C C352 SC1U6D3V2KX-GP DIS C329 SC1U6D3V2KX-GP 2 DIS C253 SC1U6D3V2KX-GP 1 C353 SC1U6D3V2KX-GP PCIE 2 MEM I/O 2 10ux1, 1ux20 VRAM-IO C349 SC1U6D3V2KX-GP 5 OF 8 AVGA1E 1D8V_S0 SCD1U16V2KX-3GP C351 2 1 PCIE_IO 500mA D 1 C290 SC1U6D3V2KX-GP 2 1 4 C294 SC1U6D3V2KX-GP 2 1 5 A A SJV50 Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title M92 (3/7)_Power Size A2 Date: 5 4 3 2 Document Number Rev SJV50-PU Wednesday, February 25, 2009 1 Sheet -1 52 of 59 5 4 3 2 1 6 OF 8 AVGA1F AB39 E39 F34 F39 G33 G34 H31 H34 H39 J31 J34 K31 K34 K39 L31 L34 M34 M39 N31 N34 P31 P34 P39 R34 T31 T34 T39 U31 U34 V34 V39 W31 W34 Y34 Y39 D 8 OF 8 AVGA1H DP C/D POWER DP A/B POWER AP20 AP21 NC_DPC_VDD18#1 NC_DPC_VDD18#2 NC_DPA_VDD18#1 NC_DPA_VDD18#2 AN24 AP24 AP13 AT13 DPC_VDD10 DPC_VDD10 DPA_VDD10 DPA_VDD10 AP31 AP32 AN17 AP16 AP17 AW14 AW16 DPC_VSSR DPC_VSSR DPC_VSSR DPC_VSSR DPC_VSSR DPA_VSSR DPA_VSSR DPA_VSSR DPA_VSSR DPA_VSSR AN27 AP27 AP28 AW24 AW26 AP22 AP23 NC_DPD_VDD18#1 NC_DPD_VDD18#2 NC_DPB_VDD18#1 NC_DPB_VDD18#2 AP25 AP26 AP14 AP15 DPD_VDD10 DPD_VDD10 DPB_VDD10 DPB_VDD10 AN33 AP33 AN19 AP18 AP19 AW20 AW22 DPD_VSSR DPD_VSSR DPD_VSSR DPD_VSSR DPD_VSSR DPB_VSSR DPB_VSSR DPB_VSSR DPB_VSSR DPB_VSSR AN29 AP29 AP30 AW30 AW32 1 2 C163 SC4D7U6D3V3KX-GP 1 DIS 1 -1 090219 2 2 DIS 150R2F-1-GP DPC_PVDD DPD_PVDD DPD_PVSS AV19 AR18 DPD_PVDD DPE_PVDD DPE_PVSS AM37 AN38 DPE_PVDD NC_DPF_PVDD NC_DPF_PVSS AL38 AM35 DIS DIS DPF_VDD10 DPF_VDD10 AF39 AH39 AK39 AL34 AM34 DPF_VSSR DPF_VSSR DPF_VSSR DPF_VSSR DPF_VSSR AM39 DPEF_CALR L50 DIS DPEF_CALR DIS 2 2 R108 1 150R2F-1-GP -1 090219 DIS 1 DIS 1D8V_S0 2 R282 1 0R0402-PAD M92-M2-GP DIS 1 AK33 AK34 DIS 2 DPF_VDD10 C682 SC4D7U6D3V3KX-GP DPF_VDD18 DPF_VDD18 -1 090219 DIS 1 AF34 AG34 1D8V_S0 2 R288 1 0R0402-PAD C679 SC1U6D3V2KX-GP DPF_VDD18 1 AU18 AV17 2 DPC_PVDD DPC_PVSS SC1U6D3V2KX-GP C178 DPE_VSSR DPE_VSSR DPE_VSSR DPE_VSSR DPE_VSSR -1 090219 DIS 1 AN34 AP39 AR39 AU37 AW35 2 R83 1 0R0402-PAD 2 DPB_PVDD 1D8V_S0 SC1U6D3V2KX-GP C668 AV29 AR28 DIS 1 DPB_PVDD DPB_PVSS DIS SC1U6D3V2KX-GP C659 DPE_VDD10 DPE_VDD10 2 AL33 AM33 DIS DIS 1 2 BLM15BD121SN1D-GP 2 DPE_VDD10 DP E/F POWER DPE_VDD18 DPE_VDD18 1 DPA_PVDD AH34 AJ34 2 AU28 AV27 DIS DPE_VDD18 C164 SC4D7U6D3V3KX-GP DP PLL POWER DPA_PVDD DPA_PVSS DIS 1D8V_S0 L22 1 DPAB_CALR 2 AW28 C177 SC1U6D3V2KX-GP DPAB_CALR 1 DPCD_CALR C185 SCD1U16V2KX-3GP DPCD_CALR AW18 2 1 R300 C680 SCD1U16V2KX-3GP DIS SCD1U16V2KX-3GP SCD1U16V2KX-3GP SCD1U16V2KX-3GP SCD1U16V2KX-3GP C193 C207 C169 C675 2 1 2 1 2 1 2 1 1 2 1 2 1 DIS 2 1 SC1U6D3V2KX-GP C676 2 1 2 1 2 SC1U6D3V2KX-GP C168 DIS DIS 1 DIS B DIS DIS 2 1 2 BLM15BD121SN1D-GP DIS SC1U6D3V2KX-GP C206 L25 1 DIS 2 L27 1 2 BLM15BD121SN1D-GP DIS SC1U6D3V2KX-GP C192 L24 DIS 1D1V_S0 1 DIS 1 2 BLM15BD121SN1D-GP 1D8V_S0 R293 150R2F-1-GP SC4D7U6D3V3KX-GPSC4D7U6D3V3KX-GPSC4D7U6D3V3KX-GPSC4D7U6D3V3KX-GP C190 C205 C171 C677 1D1V_S0 DIS 2 R91 1 0R0402-PAD DIS 2 DIS DPB_VDD10 DIS L49 1 2 BLM15BD121SN1D-GP SC1U6D3V2KX-GP C182 1 DPD_VDD10 2 -1 090219 1D8V_S0 1 2 BLM18PG300SN-GP 1D1V_S0 2 R292 1 0R0402-PAD SC1U6D3V2KX-GP C664 1D1V_S0 C 1D1V_S0 L23 DIS 2 DIS C175 SC1U6D3V2KX-GP 1 200mA 2 1 DIS DPA_VDD10 C179 SCD1U16V2KX-3GP -1 090219 DPC_VDD10 2 R291 2 0R0402-PAD 1 SC1U6D3V2KX-GP C663 1D1V_S0 PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS 1D8V_S0 1 2 BLM15BD121SN1D-GP DIS F15 F17 F19 F21 F23 F25 F27 F29 F31 F33 F7 F9 G2 G6 H9 J2 J27 J6 J8 K14 K7 L11 L17 L2 L22 L24 L6 M17 M22 M24 N16 N18 N2 N21 N23 N26 N6 R15 R17 R2 R20 R22 R24 R27 R6 T11 T13 T16 T18 T21 T23 T26 U15 U17 U2 U20 U22 U24 U27 U6 V11 V16 V18 V21 V23 V26 W2 W6 Y15 Y17 Y20 Y22 Y24 Y27 U13 V13 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND DIS GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND VSS_MECH VSS_MECH VSS_MECH A3 A37 AA16 AA18 AA2 AA21 AA23 AA26 AA28 AA6 AB12 AB15 AB17 AB20 AB22 AB24 AB27 AC11 AC13 AC16 AC18 AC2 AC21 AC23 AC26 AC28 AC6 AD15 AD17 AD20 AD22 AD24 AD27 AD9 AE2 AE6 AF10 AF16 AF18 AF21 AG17 AG2 AG20 AG22 AG6 AG9 AH21 AH29 AJ10 AJ11 AJ2 AJ28 AJ6 AK11 AK31 AK7 AL11 AL14 AL17 AL2 AL20 AL21 AL23 AL26 AL32 AL6 AL8 AM11 AM31 AM9 AN11 AN2 AN30 AN6 AN8 AP11 AP7 AP9 AR5 AW34 B11 B13 B15 B17 B19 B21 B23 B25 B27 B29 B31 B33 B7 B9 C1 C39 E35 E5 F11 F13 D C B A39 VCC_MECH_A39 VCC_MECH_AW1 AW1 AW39 VCC_MECH_AW39 1 1 1 TP242TPAD14-GP TP122TPAD14-GP TP123TPAD14-GP M92-M2-GP A A SJV50 Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title M92 (4/7)_DP POWER_GND Size A2 Date: 5 4 3 2 Document Number Rev SJV50-PU Sheet Wednesday, February 25, 2009 1 -1 53 of 59 5 4 3 ALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE GPIOS ARE USED, THEY MUST NOT CONFLICT DURING RESET H2SYNC, 4 OF 8 AVGA1D VDDR3 MAB[12..0] 55,56 C MDB0 MDB1 MDB2 MDB3 MDB4 MDB5 MDB6 MDB7 MDB8 MDB9 MDB10 MDB11 MDB12 MDB13 MDB14 MDB15 MDB16 MDB17 MDB18 MDB19 MDB20 MDB21 MDB22 MDB23 MDB24 MDB25 MDB26 MDB27 MDB28 MDB29 MDB30 MDB31 MDB32 MDB33 MDB34 MDB35 MDB36 MDB37 MDB38 MDB39 MDB40 MDB41 MDB42 MDB43 MDB44 MDB45 MDB46 MDB47 MDB48 MDB49 MDB50 MDB51 MDB52 MDB53 MDB54 MDB55 MDB56 MDB57 MDB58 MDB59 MDB60 MDB61 MDB62 MDB63 ( 0.5 * VDDR1 ) ( for SSTL-1.8/SSTL-2/DDR2 ) ( 0.7 * VDDR1 ) ( for GDDR3/GDDR4 ) DIVIDER RESISTORS DDR2 DDR3 MVREF TO 1.8V 100R 40.2R MVREF TO GND 100R 100R 1 1D8V_S0 R152 100R2F-L1-GP-U 2 1 MVREFDB MVREFSB TESTEN 1 2 DIS Y12 AA12 DQB_0 DQB_1 DQB_2 DQB_3 DQB_4 DQB_5 DQB_6 DQB_7 DQB_8 DQB_9 DQB_10 DQB_11 DQB_12 DQB_13 DQB_14 DQB_15 DQB_16 DQB_17 DQB_18 DQB_19 DQB_20 DQB_21 DQB_22 DQB_23 DQB_24 DQB_25 DQB_26 DQB_27 DQB_28 DQB_29 DQB_30 DQB_31 DQB_32 DQB_33 DQB_34 DQB_35 DQB_36 DQB_37 DQB_38 DQB_39 DQB_40 DQB_41 DQB_42 DQB_43 DQB_44 DQB_45 DQB_46 DQB_47 DQB_48 DQB_49 DQB_50 DQB_51 DQB_52 DQB_53 DQB_54 DQB_55 DQB_56 DQB_57 DQB_58 DQB_59 DQB_60 DQB_61 DQB_62 DQB_63 P8 T9 P9 N7 N8 N9 U9 U8 Y9 W9 AC8 AC9 AA7 AA8 Y8 AA9 DQMB_0 DQMB_1 DQMB_2 DQMB_3 DQMB_4 DQMB_5 DQMB_6 DQMB_7 H3 H1 T3 T5 AE4 AF5 AK6 AK5 DQMB#0 DQMB#1 DQMB#2 DQMB#3 DQMB#4 DQMB#5 DQMB#6 DQMB#7 QSB_0/RDQSB_0 QSB_1/RDQSB_1 QSB_2/RDQSB_2 QSB_3/RDQSB_3 QSB_4/RDQSB_4 QSB_5/RDQSB_5 QSB_6/RDQSB_6 QSB_7/RDQSB_7 F6 K3 P3 V5 AB5 AH1 AJ9 AM5 RDQSB0 RDQSB1 RDQSB2 RDQSB3 RDQSB4 RDQSB5 RDQSB6 RDQSB7 QSB_0B/WDQSB_0 QSB_1B/WDQSB_1 QSB_2B/WDQSB_2 QSB_3B/WDQSB_3 QSB_4B/WDQSB_4 QSB_5B/WDQSB_5 QSB_6B/WDQSB_6 QSB_7B/WDQSB_7 G7 K1 P1 W4 AC4 AH3 AJ8 AM3 WDQSB0 WDQSB1 WDQSB2 WDQSB3 WDQSB4 WDQSB5 WDQSB6 WDQSB7 TESTEN AK10 AL10 CLKTESTA CLKTESTB BA2 BA0 BA1 BA2 BA0 BA1 ODTB0 ODTB1 T7 W7 ODTB0 ODTB1 CLKB0 CLKB0# L9 L8 CLKB0 CLKB0# CLKB1 CLKB1# AD8 AD7 CLKB1 CLKB1# RASB0# RASB1# T10 Y10 RASB0# RASB1# CASB0# CASB1# W10 AA10 CASB0# CASB1# CSB0_0# CSB0_1# P10 L10 CSB0#_0 CSB1_0# CSB1_1# AD10 AC10 CSB1#_0 DIS MVREFDB MVREFSB AD28 MAB0 MAB1 MAB2 MAB3 MAB4 MAB5 MAB6 MAB7 MAB8 MAB9 MAB10 MAB11 MAB12 MAB_0 MAB_1 MAB_2 MAB_3 MAB_4 MAB_5 MAB_6 MAB_7 MAB_8 MAB_9 MAB_10 MAB_11 MAB_12 MAB_13/BA2 MAB_14/BA0 MAB_15/BA1 55,56 55,56 55,56 DQMB#0 DQMB#1 DQMB#2 DQMB#3 DQMB#4 DQMB#5 DQMB#6 DQMB#7 55 55 55 55 56 56 56 56 RDQSB0 RDQSB1 RDQSB2 RDQSB3 RDQSB4 RDQSB5 RDQSB6 RDQSB7 55 55 55 55 56 56 56 56 WDQSB0 WDQSB1 WDQSB2 WDQSB3 WDQSB4 WDQSB5 WDQSB6 WDQSB7 55 55 55 55 56 56 56 56 ODTB0 ODTB1 55 56 CLKB0 CLKB0# 55 55 CLKB1 CLKB1# 56 56 RASB0# RASB1# 55 56 CASB0# CASB1# 55 56 CSB0#_0 55 CSB1#_0 56 51 GPIO_VGA_00 51 GPIO_VGA_01 DIS1 R95 DIS1 R93 2 10KR2J-3-GP 2 10KR2J-3-GP 51 GPIO_VGA_05 DIS1 R92 2 10KR2J-3-GP 51 GPIO_VGA_08 DY 1 R96 2 10KR2J-3-GP 51 GPIO_VGA_11 DIS1 R89 2 10KR2J-3-GP 51 GPIO_VGA_22 DY 1 R87 2 10KR2J-3-GP 19,51 M92_HSYNC 19,51 M92_VSYNC DIS1 R326 DIS1 R327 2 10KR2J-3-GP 2 10KR2J-3-GP 51 GPIO_VGA_02 DIS1 R90 2 10KR2J-3-GP 51 GPIO_VGA_13 DY 1 R98 2 10KR2J-3-GP 51 GPIO_VGA_12 DY 1 R97 2 10KR2J-3-GP DIS GPIO_28_TDO , If BIOS_ROM_EN (GPIO22) = 0 DY 1 R88 If BIOS_ROM_EN (GPIO22) = 1 V 128MB 256MB 64MB 32MB 512MB 1GB 2GB 4GB STRAPS x000 x001 x010 x x x x x PIN Part Number GPIO[13,12,11] ST Microelectronics Chingis (formerly PMC) M25P05A M25P10A M25P20 M25P40 M25P80 0100 0101 0101 0101 0101 Pm25LV512A Pm25LV010A 0100 0101 RECOMMENDED SETTINGS 0= DO NOT INSTALL RESISTOR 1 = INSTALL 10K RESISTOR X = DESIGN DEPENDANT NA = NOT APPLICABLE DESCRIPTION PCIE FULL TX OUTPUT SWING 2 10KR2J-3-GP GPIO1 Transmitter De-emphasis Enable 0= Tx de-emphasis disabled 1= Tx de-emphasis enabled (Internal PD) TX_DEEMPH_EN HDMI must only be enabled on systems that are legally entitled. It is the responsibility of the system designer to ensure that the system is entitled to support this feature. GPIO0 Tansmitter Power Savings Enable 0= 50% Tx output swing 1= Full Tx output swing (Internal PD) C 1 1 PCIE GNE2 ENABLED 0 = Advertises the PCI-E device as 2.5GT/s 1 = Advertises the PCI-E device as 5GT/s BIF_GEN2_EN_A GPIO2 AC_BATT GPIO5 AC (Performance mode) = 3.3 V Battery saving mode = 0.0 V ROMSO GPIO8 Serial ROM Output from ROM 1 BIF_CLK_PM_EN 0 VGA ENABLED CKEB0 CKEB1 U10 AA11 CKEB0 CKEB1 WEB0# WEB1# N10 AB11 WEB0# WEB1# CKEB0 CKEB1 55 56 WEB0# WEB1# 55 56 ROMSI GPIO9 0 Serial ROM Input to ROM SERIAL ROM TYPE OR MEMORY APERTURE SIZE SELECT ROMIDCFG[3:0] GPIO[13,12,11] (Internal PD) DRAM_RST GPIO21_BB_EN Size of the primary GPIO[13,12,11] Manufacturer memory apertures TX_PWRS_ENB 51 GPIO_VGA_09 D GENERICC PULLUP PADS ARE NOT REQUIRED FOR THESE STRAPS BUT IF THESE GPIOS ARE USED, THEY MUST NOT CONFLICT DURING RESET SA_20081105 if BIOS_ROM_EN=1,then Config[3:0] defines the ROM type if BIOS_ROM_EN=0,then Config[3:0] defines the primary memory apeture size X X X B AH11 PWRCNTL_[1,0] 1 1 DIS 2 R296 4K7R2F-GP DIS 2 R294 4K7R2F-GP 1 CLKTESTA CLKTESTB R132 2 2 1 2 1 DIS 1KR2J-1-GP 2 R149 100R2F-L1-GP-U SCD1U16V2KX-3GP C380 C 380 DIS DIS SCD01U50V2KX-1GP C378 B 2 1 1 R151 100R2F-L1-GP-U 2 DIS DIS DIS SCD1U16V2KX-3GP C379 C 379 R150 100R2F-L1-GP-U SCD01U50V2KX-1GP C377 1D8V_S0 1 2 DIS C5 C3 E3 E1 F1 F3 F5 G4 H5 H6 J4 K6 K5 L4 M6 M1 M3 M5 N4 P6 P5 R4 T6 T1 U4 V6 V1 V3 Y6 Y1 Y3 Y5 AA4 AB6 AB1 AB3 AD6 AD1 AD3 AD5 AF1 AF3 AF6 AG4 AH5 AH6 AJ4 AK3 AF8 AF9 AG8 AG7 AK9 AL7 AM8 AM7 AK1 AL4 AM6 AM1 AN4 AP3 AP1 AP5 MEMORY INTERFACE B MDB[63..0] 55,56 MDB[63..0] 1 AMD RESERVED CONFIGURATION STRAPS SA_20081104 M92-M2 uses memory group B only D 2 M92-M2-GP BB_EN STRAPS GPIO PIN DVPDATA(23:20) (Internal PD) GPIO[15,20] Power control signals to control the core voltage regulator GPIO21 Back Bias (body bias) which minimizes power consumption in battery modes. 0V = Disable 3D3V = Enable DESCRIPTION Initialization Behavior: This signal is input during reset (no reference clock is required). After reset, the default state is output low (0 V). The signals above can be left unconnected if not used. AUD[1] AUD[0] VGA_HSYNC VGA_VSYNC (Internal PD) CCBYPASS 0 AUD[1:0] 00:No audio function 01:Audio for DisplayPort and HDMI ( if adapter is detected) 10:Audio for DisplayPort only 11:Audio for both DisplayPort and HDMI 1 0 GENERICC A A SJV50 Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title M92 (5/7)_Memory_Straps Size A2 Date: 5 4 3 2 Document Number Rev SJV50-PU Wednesday, February 25, 2009 Sheet 1 -1 54 of 59 5 4 3 2 1 VGARAM1 DQMB#1 DQMB#2 F3 B3 ODTB0 ODTB0 CAS# LDM UDM VDDL VSSDL K9 1 2 BLM15BD121SN1D-GP VDDL_M1 J1 J7 DIS C716 ODT B7 A8 54,56 BA2 BA2 VREF A2 E2 L1 R3 R7 R8 NC#A2 NC#E2 BA2 NC#R3 NC#R7 NC#R8 VSS VSS VSS VSS VSS A3 E3 J3 N1 P9 1D8V_S0 K4N1G164QQ-HC20-GP 1D8V_S0 54 WEB0# WEB0# K3 WE# RASB0# K7 54 RASB0# 54 CASB0# RAS# CASB0# L7 CAS# 54 54 DQMB#3 DQMB#0 DQMB#3 DQMB#0 F3 B3 LDM UDM 54 ODTB0 ODTB0 K9 ODT R145 DIS DIS 54 54 RDQSB3 WDQSB3 54 54 RDQSB0 WDQSB0 F7 E8 LDQS LDQS# RDQSB0 WDQSB0 B7 A8 UDQS UDQS# J2 VREF A2 E2 L1 R3 R7 R8 54,56 NC#A2 NC#E2 BA2 NC#R3 NC#R7 NC#R8 BA2 BA2 1 C713 DIS 2 1 DIS 2 1 2 1 2 1 2 1 2 1 2 1 2 1 1 2 2 2 1 1 2 VSS VSS VSS VSS VSS A3 E3 J3 N1 P9 DIS C382 DIS C758 DIS C376 DIS SC10U6D3V5KX-1GP 1 C341 SC10U6D3V5KX-1GP DIS C707 SC10U6D3V5KX-1GP DIS C704 SC1U6D3V2KX-GP DIS C738 SC1U6D3V2KX-GP DIS C740 SC1U6D3V2KX-GP 2 A7 B2 B8 D2 D8 E7 F2 F8 H2 H8 2 1 2 BLM15BD121SN1D-GP VDDL_M2 DIS J1 J7 VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ C734 SCD47U6D3V2KX-GP DIS 72.41164.D0U SC1U6D3V2KX-GP DIS C357 SC1U6D3V2KX-GP DIS C725 SC1U6D3V2KX-GP 1 C 1 DIS L35 B SC10U6D3V5KX-1GP C363 SC1U6D3V2KX-GP 2 CLKB0_R 2ND = 72.51G63.A0U SC1U6D3V2KX-GP DIS SC1U6D3V2KX-GP SC1U6D3V2KX-GP SCD1U16V2KX-3GP SCD1U16V2KX-3GP SCD1U16V2KX-3GP SCD1U16V2KX-3GP DIS C358 1D8V_S0 DIS K4N1G164QQ-HC20-GP DIS C743 VDDL VSSDL RDQSB3 WDQSB3 VRAM_VREF1 DIS C331 SAMSUNG 72.41164.D0U 2ND = 72.51G63.A0U HYNIX DIS C356 DIS C374 DIS C371 DIS C157 VDD VDD VDD VDD VDD A1 E1 J9 M9 R1 1 CS# R343 DIS R352 2 L8 CLKB0 1 CSB0#_0 R334 SCD1U16V2KX-3GP DIS J2 A7 B2 B8 D2 D8 E7 F2 F8 H2 H8 4K99R2F-L-GP B C715 SCD1U16V2KX-3GP 2 1 VRAM_VREF1 UDQS UDQS# VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ CKE CLKB0# SC1U6D3V2KX-GP 1 RDQSB2 WDQSB2 RDQSB2 WDQSB2 LDQS LDQS# 4K99R2F-L-GP 54 54 F7 E8 CSB0#_0 DIS 1 RDQSB1 WDQSB1 RDQSB1 WDQSB1 54 L54 SC1U6D3V2KX-GP 54 54 K2 A9 C1 C3 C7 C9 E9 G1 G3 G7 G9 MDB[63..0] 54,56 MDB[63..0] 2 A1 E1 J9 M9 R1 CKEB0 1D8V_S0 VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ MAB[12..0] 1 L7 VDD VDD VDD VDD VDD CK# CK 54,56 2 RAS# K8 J8 D MAB[12..0] 1 K7 CKEB0 CLKB0# CLKB0 MDB5 MDB2 MDB7 MDB0 MDB1 MDB4 MDB3 MDB6 MDB30 MDB25 MDB31 MDB24 MDB28 MDB29 MDB27 MDB26 C344 2 WE# RASB0# CS# 54 A12 A11 A10/AP A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 B9 B1 D9 D1 D3 D7 C2 C8 F9 F1 H9 H1 H3 H7 G2 G8 1 K3 CLKB0# CLKB0 R2 P7 M2 P3 P8 P2 N7 N3 N8 N2 M7 M3 M8 DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 2 L8 WEB0# 54 54 MAB12 MAB11 MAB10 MAB9 MAB8 MAB7 MAB6 MAB5 MAB4 MAB3 MAB2 MAB1 MAB0 BA0 BA1 1 CSB0#_0 A9 C1 C3 C7 C9 E9 G1 G3 G7 G9 L2 L3 2 CKE CASB0# DQMB#1 DQMB#2 54 K2 VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ BA0 BA1 1 54 54 CK# CK BA0 BA1 2 CASB0# K8 J8 VGARAM2 54,56 54,56 2 54 CLKB0# CLKB0 MDB20 MDB21 MDB18 MDB22 MDB23 MDB17 MDB19 MDB16 MDB8 MDB14 MDB9 MDB13 MDB15 MDB11 MDB12 MDB10 1 RASB0# A12 A11 A10/AP A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 B9 B1 D9 D1 D3 D7 C2 C8 F9 F1 H9 H1 H3 H7 G2 G8 2 WEB0# 54 R2 P7 M2 P3 P8 P2 N7 N3 N8 N2 M7 M3 M8 CKEB0 CSB0#_0 54 MAB12 MAB11 MAB10 MAB9 MAB8 MAB7 MAB6 MAB5 MAB4 MAB3 MAB2 MAB1 MAB0 DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 1 CKEB0 BA0 BA1 2 54 L2 L3 56R2F-1-GP CLKB0# CLKB0 BA0 BA1 56R2F-1-GP 54 54 54 C BA0 BA1 2 54,56 54,56 D DIS SJV50 A A Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title M92 (6/7)_VRAM_B0 Size A3 Document Number Rev SJV50-PU Date: Wednesday, February 25, 2009 5 4 3 2 Sheet 1 -1 55 of 59 5 4 3 2 1 VGARAM4 WEB1# 54 RASB1# 54 CASB1# 54 54 54 ODTB1 54 54 RDQSB4 WDQSB4 WEB1# K3 WE# RASB1# K7 RAS# CASB1# L7 CAS# DQMB#4 DQMB#6 DQMB#4 DQMB#6 F3 B3 VDD VDD VDD VDD VDD A1 E1 J9 M9 R1 LDM UDM ODTB1 K9 ODT RDQSB4 WDQSB4 F7 E8 LDQS LDQS# DIS VDDL VSSDL 1 2 BLM15BD121SN1D-GP VDDL_M3 DIS C684 B7 A8 54,55 BA2 BA2 VREF A2 E2 L1 R3 R7 R8 NC#A2 NC#E2 BA2 NC#R3 NC#R7 NC#R8 A3 E3 J3 N1 P9 CSB1#_0 54 WEB1# 54 RASB1# 54 CASB1# 54 54 DQMB#7 DQMB#5 K4N1G164QQ-HC20-GP CSB1#_0 L8 CS# WEB1# K3 WE# RASB1# K7 RAS# CASB1# L7 CAS# DQMB#7 DQMB#5 F3 B3 LDM UDM ODTB1 ODTB1 K9 DIS R116 54 54 RDQSB7 WDQSB7 54 54 RDQSB5 WDQSB5 DIS RDQSB7 WDQSB7 F7 E8 LDQS LDQS# RDQSB5 WDQSB5 B7 A8 UDQS UDQS# J2 VREF A2 E2 L1 R3 R7 R8 NC#A2 NC#E2 BA2 NC#R3 NC#R7 NC#R8 VRAM_VREF2 C689 72.41164.D0U 54,55 BA2 BA2 DIS 1 DIS 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 1 2 2 2 2 1 1 1 2 C213 A7 B2 B8 D2 D8 E7 F2 F8 H2 H8 VSS VSS VSS VSS VSS A3 E3 J3 N1 P9 R320 DIS C CLKB1_R 1 DIS DIS C688 SCD47U6D3V2KX-GP 2 B C191 DIS C173 DIS C674 DIS SC10U6D3V5KX-1GP 1 1 2 BLM15BD121SN1D-GP VDDL_M4 DIS J1 J7 VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ R324 DIS L26 SC10U6D3V5KX-1GP DIS C201 SC1U6D3V2KX-GP DIS C671 SC1U6D3V2KX-GP DIS C240 SC1U6D3V2KX-GP DIS C158 SC1U6D3V2KX-GP DIS C210 SC1U6D3V2KX-GP 2 VDDL VSSDL SC10U6D3V5KX-1GP C683 SC1U6D3V2KX-GP DIS SC1U6D3V2KX-GP DIS C695 SC10U6D3V5KX-1GP C254 SC1U6D3V2KX-GP DIS A1 E1 J9 M9 R1 CLKB1 2ND = 72.51G63.A0U C249 SC1U6D3V2KX-GP SC1U6D3V2KX-GP SCD1U16V2KX-3GP SCD1U16V2KX-3GP SCD1U16V2KX-3GP SCD1U16V2KX-3GP DIS VDD VDD VDD VDD VDD CLKB1# 1D8V_S0 72.41164.D0U 1D8V_S0 C686 DIS A9 C1 C3 C7 C9 E9 G1 G3 G7 G9 K4N1G164QQ-HC20-GP 2ND = 72.51G63.A0U DIS C690 DIS C681 DIS C672 DIS C694 ODT 2 1 VSS VSS VSS VSS VSS CKE R323 SCD1U16V2KX-3GP DIS J2 K2 VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ SC1U6D3V2KX-GP 1D8V_S0 4K99R2F-L-GP B C231 SCD1U16V2KX-3GP 2 1 VRAM_VREF2 UDQS UDQS# 54 54 1 RDQSB6 WDQSB6 RDQSB6 WDQSB6 CKEB1 DIS 4K99R2F-L-GP 54 54 CKEB1 L51 SC1U6D3V2KX-GP A7 B2 B8 D2 D8 E7 F2 F8 H2 H8 54 1D8V_S0 J1 J7 VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ CK# CK 1 CS# K8 J8 2 54 L8 CLKB1# CLKB1 56R2F-1-GP C CSB1#_0 CLKB1# CLKB1 MDB[63..0] 54,55 MDB[63..0] 56R2F-1-GP 54 CSB1#_0 54 54 MAB[12..0] 1 CKE 54,55 2 K2 D MAB[12..0] 1 CKEB1 A9 C1 C3 C7 C9 E9 G1 G3 G7 G9 A12 A11 A10/AP A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 MDB47 MDB41 MDB44 MDB43 MDB40 MDB46 MDB42 MDB45 MDB62 MDB59 MDB63 MDB56 MDB60 MDB58 MDB57 MDB61 2 54 VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ R2 P7 M2 P3 P8 P2 N7 N3 N8 N2 M7 M3 M8 B9 B1 D9 D1 D3 D7 C2 C8 F9 F1 H9 H1 H3 H7 G2 G8 1 CK# CK MAB12 MAB11 MAB10 MAB9 MAB8 MAB7 MAB6 MAB5 MAB4 MAB3 MAB2 MAB1 MAB0 DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 C174 2 K8 J8 CKEB1 BA0 BA1 1 CLKB1# CLKB1 L2 L3 2 CLKB1# CLKB1 BA0 BA1 BA0 BA1 1 54 54 VGARAM3 54,55 54,55 2 A12 A11 A10/AP A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 MDB49 MDB55 MDB50 MDB54 MDB53 MDB51 MDB52 MDB48 MDB34 MDB38 MDB32 MDB36 MDB39 MDB33 MDB37 MDB35 1 R2 P7 M2 P3 P8 P2 N7 N3 N8 N2 M7 M3 M8 B9 B1 D9 D1 D3 D7 C2 C8 F9 F1 H9 H1 H3 H7 G2 G8 2 MAB12 MAB11 MAB10 MAB9 MAB8 MAB7 MAB6 MAB5 MAB4 MAB3 MAB2 MAB1 MAB0 DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 2 BA0 BA1 D 1 L2 L3 2 BA0 BA1 1 BA0 BA1 2 54,55 54,55 DIS SJV50 A A Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title M92 (7/7)_VRAM_B1 Size A3 Document Number Rev SJV50-PU Date: Wednesday, February 25, 2009 5 4 3 2 Sheet 1 -1 56 of 59 4 1D1V_S0 DY 3 DY DY DY DY 2 Type-I 2 H14 HOLE276R142 EC113 SCD1U10V2KX-4GP 1 H16 HOLE276R142 Type-I 1 34.42Y01.031 1 Type-I 34.4H551.001 2 SPR2 DY 34.4H551.001 Size Date: 1 SPR1 1 H17 HOLE276R142 1 2ND = 73.74125.L12 3RD = 73.74125.01B 34.42Y01.031 1 34.4B804.001 7 12 2 Type-I 1 DY 2 H13 HOLE276R142 34.42Y01.031 U7C TSAHCT125PW-GP 73.74125.L13 EC10 SCD1U10V2KX-4GP 1 DY 2 H15 HOLE276R110 2 5V_S0 DY 2 7 13 14 10 14 5V_S0 EC107 SCD1U10V2KX-4GP 1 DY 2 1 34.4B804.001 8 EC76 SCD1U10V2KX-4GP 1 DY DY EC71 SCD1U10V2KX-4GP 1 DCBATOUT 2 Type-I 1 34.42Y01.031 H12 HOLE276R142 EC37 SCD1U10V2KX-4GP 1 2 Type-M 2 2 EC8 SCD1U25V3KX-GP 1 -1_0205 EC45 SCD1U10V2KX-4GP 1 DY 2 DY EC1 SCD1U25V3KX-GP 1 1 9 EC35 SCD1U10V2KX-4GP 1 DY 2 1 34.42Y01.031 H8 HOLE236R142 EC77 SCD1U10V2KX-4GP 1 DY 2 34.42Y01.031 1 34.42Y01.031 1 D EC54 SCD1U10V2KX-4GP 1 DY DY EC116 SCD1U10V2KX-4GP 1 2 EC59 SCD1U25V3KX-GP 1 Type-I EC62 SCD1U25V3KX-GP 1 2 EC60 SCD1U25V3KX-GP 1 1 H11 HOLE276R142 2 2 EC57 SCD1U25V3KX-GP 1 34.42Y01.031 Type-M EC79 SCD1U10V2KX-4GP 1 DY DY 2 2 1 H7 HOLE236R142 EC55 SCD1U10V2KX-4GP 1 DY 2 2 -1 090223_EMI EC99 SCD1U10V2KX-4GP 1 DY DY EC93 SCD1U25V3KX-GP 1 1 GND10 2 2 1 GND5 EC36 SCD1U10V2KX-4GP 1 5V_S5 2 EC46 SCD1U25V3KX-GP 1 2 DY EC61 SCD1U10V2KX-4GP 1 DY 2 EC12 SCD1U25V3KX-GP 1 DY EC64 SCD1U10V2KX-4GP 1 DY 2 2 DY EC110 SCD1U10V2KX-4GP 1 DY EC29 SCD1U25V3KX-GP 1 DY 2 1 GND4 EC117 SCD1U10V2KX-4GP 1 2 EC13 SCD1U25V3KX-GP 1 EC18 SCD1U25V3KX-GP 1 1 GND9 EC67 SCD1U10V2KX-4GP 1 DY 2 2 GND3 EC100 SCD1U10V2KX-4GP 1 DY 2 2 DY EC33 SCD1U25V3KX-GP 1 GND8 -1 SPRING-71-GP 2 SB 3 SPRING-71-GP 5 4 SPRING-71-GP DY EC115 SCD1U10V2KX-4GP 1 1 GND2 HOLE355X355R111-S1-GP HOLET276B315X315R91-S DY 1 SA HOLE355X355R111-S1-GP HOLE355X355R111-S1-GP 2 GND7 HOLE355X355R111-S1-GP HOLE355X355R111-S1-GP EC34 SCD1U25V3KX-GP 1 GND6 2 1 GND1 EC56 SCD1U10V2KX-4GP 1 1 HOLE355X355R111-S1-GP DY EC98 SCD1U25V3KX-GP 1 HOLE315X315R91-S1-GP A HOLE355X355R111-S1-GP HOLE355X355R111-S1-GP C EC32 SCD1U10V2KX-4GP 1 5 2 1 5V_S0 11 U7D TSAHCT125PW-GP 73.74125.L13 2ND = 73.74125.L12 3RD = 73.74125.01B D -1_0217 H20 HOLE276R110 DY SPR3 C DY 34.4H551.001 20081203 20081202 -1 090223_EMI B B 3D3V_S0 SJV50 A Wistron Corporation Title 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Document Number EMI/Spring/Boss SJV50-PU Sheet Wednesday, February 25, 2009 1 57 Rev of 59 -1 5 4 BT Conn. Test Point USB_5- 1 23 USB_5+ 1 23 3D3V_BT_S0 1 23 USBCN1 Conn. Test Point AFTE14P-GP TP214 1 12,24 USB_OC#3 1 AFTE14P-GP TP212 AFTE14P-GP TP210 1 1 1 12,23 USBPN5 12,23 USBPP5 AFTE14P-GP TP43 D 1 1 1 12,24 USBPN7 12,24 USBPP7 1 1 AD+, BAT Conn. Test Point 1 24,34 USB_PWR_EN# 49 1 1 AD+_JK 1 1 1 1 1 1 1 49 KBC_BAT_CLK_1 49 KBC_BAT_DAT_1 49 BAT_IN#_1 BT+ 1 1 AFTE14P-GP TP6 AFTE14P-GP TP5 TP7 TP9 TP8 TP15 TP12 AFTE14P-GP TP19 AFTE14P-GP TP21 1 1 1 1 5V_S5 5V_S5 5V_S5 5V_S5 AFTE14P-GP TP22 AFTE14P-GP TP17 AFTE14P-GP AFTE14P-GP AFTE14P-GP AFTE14P-GP AFTE14P-GP 3 2 Check test point AFTE14P-GP TP20 AFTE14P-GP TP24 1 3D3V_AUX_S5 AFTE14P-GP TP213 AFTE14P-GP TP211 3D3V_S5 1 3D3V_S0 1 5V_S5 1 AFTE14P-GP TP25 AFTE14P-GP TP30 AFTE14P-GP TP31 AFTE14P-GP TP16 1 AFTE14P-GP TP34 12,34 PM_PWRBTN# AFTE14P-GP AFTE14P-GP AFTE14P-GP AFTE14P-GP 6,9 LDT_RST#_CPU 1 6,11 CPU_PWRGD 1 TP41 TP40 TP46 TP45 1 34,43 S5_ENABLE 1 1 AFTE14P-GP TP11 AFTE14P-GP TP225 33 33 1 1 1 FAN1_VCC FAN1_FG1 1 18,27 INT_MIC1 1 AFTE14P-GP TP94 AFTE14P-GP TP92 AFTE14P-GP TP63 1 1 13 AFTE14P-GP TP10 PSW_CLR# 2 36 36 1 1 TP_DATA TP_CLK 1 1 B 1 1 36,37 TP_RIGHT 36,37 TP_LEFT 18 18 18 AFTE14P-GP TP189 AFTE14P-GP TP187 1 1 AFTE14P-GP TP184 KCOL1 KCOL2 KCOL3 KCOL4 KCOL5 KCOL6 KCOL7 KCOL8 KCOL9 KCOL10 KCOL11 KCOL12 KCOL13 KCOL14 KCOL15 KCOL16 KCOL17 KCOL18 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 34 34 34 34 34 34 34 34 KROW1 KROW2 KROW3 KROW4 KROW5 KROW6 KROW7 KROW8 1 1 1 1 1 1 1 1 A 1 AFTE14P-GP TP37 AFTE14P-GP TP191 AFTE14P-GP TP124 20081201 C 3D3V_S0 1 1 1 1 1 1 1 11,15,35 PCLK_FWH 1 1 1 1 AFTE14P-GP TP155 AFTE14P-GP AFTE14P-GP AFTE14P-GP AFTE14P-GP AFTE14P-GP AFTE14P-GP TP153 TP150 TP145 TP135 TP130 TP62 AFTE14P-GP TP119 AFTE14P-GP TP117 AFTE14P-GP TP111 AFTE14P-GP TP121 AFTE14P-GP TP27 AFTE14P-GP TP18 AFTE14P-GP TP14 AFTE14P-GP TP26 AFTE14P-GP TP23 AFTE14P-GP TP185 B AFTE14P-GP TP173 AFTE14P-GP TP174 MMB Conn. Test Point 3D3V_S0 KB Conn. Test Point 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 1 1 1 CCD_PWR USBPN10_R USBPP10_R AFTE14P-GP TP167 1 11,34,35 LPC_LAD0 11,34,35 LPC_LAD1 11,34,35 LPC_LAD2 11,34,35 LPC_LAD3 11,34,35 LPC_LFRAME# 11,25,31,32,34,35,50 PLT_RST1#_B CCD Conn. Test Point AFTE14P-GP TP192 AFTE14P-GP TP188 AFTE14P-GP TP195 AFTE14P-GP TP13 TouchPad Conn. Test Point 5V_S0 D AFTE14P-GP TP157 Test Point放在Dimm Door打開可量測處 AMic Conn. Test Point FAN Conn. Test Point AFTE14P-GP TP208 G27 GAP-OPEN C AFTE14P-GP TP71 AFTE14P-GP TP61 PowerButton Conn. Test Point 37 KBC_PWRBTN#_R 1 25,32,33,34,38,51 25,32,33,34,38,51 AFTE14P-GP AFTE14P-GP AFTE14P-GP AFTE14P-GP AFTE14P-GP AFTE14P-GP AFTE14P-GP AFTE14P-GP AFTE14P-GP AFTE14P-GP AFTE14P-GP AFTE14P-GP AFTE14P-GP AFTE14P-GP AFTE14P-GP AFTE14P-GP AFTE14P-GP AFTE14P-GP TP75 TP83 TP101 TP78 TP91 TP104 TP82 TP99 TP89 TP103 TP79 TP98 TP84 TP102 TP90 TP100 TP105 TP81 AFTE14P-GP AFTE14P-GP AFTE14P-GP AFTE14P-GP AFTE14P-GP AFTE14P-GP AFTE14P-GP AFTE14P-GP TP93 TP80 TP85 TP95 TP86 TP88 TP96 TP87 AFTE14P-GP TP50 1 1 1 1 KBC_THERM_CLK KBC_THERM_DAT 1 1 1 34,38 MEDIA_INT 38 38 38 38 WLAN_LED#_MMB CAP_LED#_MMB NUM_LED#_MMB MEDIA_LED#_MMB 3D3V_S0 38 BT_LED#_MMB 1 1 1 1 1 1 1 1 AFTE14P-GP TP51 AFTE14P-GP TP49 AFTE14P-GP TP65 AFTE14P-GP TP66 AFTE14P-GP TP53 AFTE14P-GP TP32 AFTE14P-GP TP58 AFTE14P-GP AFTE14P-GP AFTE14P-GP AFTE14P-GP AFTE14P-GP AFTE14P-GP TP57 TP59 TP56 TP55 TP60 TP54 AFTE14P-GP TP35 AFTE14P-GP TP42 SJV50 A Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. SPKR Conn. Test Point 29 29 29 29 1 1 1 1 SPKR_L-_R SPKR_L+_R SPKR_R-_R SPKR_R+_R Title AFTE14P-GP AFTE14P-GP AFTE14P-GP AFTE14P-GP TP3 TP1 TP2 TP4 Size Document Number Test point SJV50-PU Date: Wednesday, February 25, 2009 5 4 3 2 Sheet 1 Rev -1 58 of 59 5 4 3 2 1 D D C C B B SJV50 A A Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size Document Number Change List SJV50-PU Date: Wednesday, February 25, 2009 5 4 3 2 Sheet 1 Rev -1 59 of 59 www.s-manuals.com
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