Zynq UltraScale+ MPSoC Product Tables And Selection Guide Ultrascale Plus
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© Copyright 2016–2017 Xilinx . Zynq® UltraScale+™ MPSoCs CG Devices Devices Devices Application Processor EV EG Dual-core ARM® Cortex™-A53 MPCore™ up to 1.3GHz Quad-core ARM Cortex-A53 MPCore up to 1.5GHz Quad-core ARM Cortex-A53 MPCore up to 1.5GHz Dual-core ARM Cortex-R5 MPCore up to 533MHz Dual-core ARM Cortex-R5 MPCore up to 600MHz Dual-core ARM Cortex-R5 MPCore up to 600MHz Mali™-400 MP2 Mali™-400 MP2 Real-Time Processor Graphics Processor Video Codec Programmable Logic H.264 / H.265 103K–600K System Logic Cells • • • • 103K–1143K System Logic Cells Sensor Processing & Fusion Motor Control Low-cost Ultrasound Traffic Engineering • • • • • • • • • Applications Page 2 Flight Navigation Missile & Munitions Military Construction Secure Solutions Networking Cloud Computing Security Data Center Machine Vision Medical Endoscopy © Copyright 2016–2017 Xilinx . 192K–504K System Logic Cells • • • • • • • • • Situational Awareness Surveillance/Reconnaissance Smart Vision Image Manipulation Graphic Overlay Human Machine Interface Automotive ADAS Video Processing Interactive Display Zynq® UltraScale+™ MPSoCs: CG Block Diagram Processing System Memory Application Processing Unit NEON™ ARM® Cortex™-A53 32KB I-Cache w/Parity 32KB D-Cache w/ECC Floating Point Unit Memory Management Unit Embedded Trace Macrocell 1 2 GIC-400 SCU CCI/SMMU ARM Cortex™-R5 128KB TCM w/ECC Vector Floating Point Unit Memory Protection Unit 32KB I-Cache w/ECC 32KB D-Cache w/ECC GIC DisplayPort v1.2a DDR4/3/3L, LPDDR4/3 32/64-Bit w/ ECC Multichannel DMA 256KB OCM with ECC Timers, WDT, Resets, Clocking & Debug 1 2 USB 3.0 SATA 3.1 1MB L2 w/ECC Real-Time Processing Unit High-Speed Connectivity System Functions Platform Management Unit Configuration and Security Unit System Management Config AES Decryption, Authentication, Secure Boot Power Management Functional Safety PCIe® 1.0 / 2.0 PS-GTR General Connectivity GigE USB 2.0 CAN UART SPI Voltage/Temp Monitor Quad SPI NOR NAND TrustZone SD/eMMC Programmable Logic System Monitor Storage & Signal Processing Page 3 Block RAM General-Purpose I/O High-Speed Connectivity UltraRAM High-Performance HP I/O GTH DSP High-Density HD I/O PCIe Gen4 © Copyright 2016–2017 Xilinx . Processing System (PS) Zynq® UltraScale+™ MPSoCs: CG Devices Application Processor Unit Real-Time Processor Unit External Memory Connectivity Integrated Block Functionality Device Name(1) Processor Core Memory w/ECC Processor Core Memory w/ECC Dynamic Memory Interface Static Memory Interfaces High-Speed Connectivity General Connectivity Power Management Security AMS - System Monitor PS to PL Interface Programmable Logic (PL) Programmable Functionality Memory Clocking Integrated IP Transceivers Speed Grades System Logic Cells (K) CLB Flip-Flops (K) CLB LUTs (K) Max. Distributed RAM (Mb) Total Block RAM (Mb) UltraRAM (Mb) Clock Management Tiles (CMTs) DSP Slices PCI Express® Gen 3x16 / Gen4x8 150G Interlaken 100G Ethernet MAC/PCS w/RS-FEC AMS - System Monitor GTH 16.3Gb/s Transceivers GTY 32.75Gb/s Transceivers Extended(2) Industrial ZU2CG ZU3CG ZU4CG ZU5CG ZU6CG ZU7CG ZU9CG Dual-core ARM® Cortex™-A53 MPCore™ up to 1.3GHz L1 Cache 32KB I / D per core, L2 Cache 1MB, on-chip Memory 256KB Dual-core ARM Cortex-R5 MPCore up to 533MHz L1 Cache 32KB I / D per core, Tightly Coupled Memory 128KB per core x32/x64: DDR4, LPDDR4, DDR3, DDR3L, LPDDR3 with ECC NAND, 2x Quad-SPI PCIe® Gen2 x4, 2x USB3.0, SATA 3.1, DisplayPort, 4x Tri-mode Gigabit Ethernet 2xUSB 2.0, 2x SD/SDIO, 2x UART, 2x CAN 2.0B, 2x I2C, 2x SPI, 4x 32b GPIO Full / Low / PL / Battery Power Domains RSA, AES, and SHA 10-bit, 1MSPS – Temperature and Voltage Monitor 12 x 32/64/128b AXI Ports 103 154 192 256 469 504 600 94 141 176 234 429 461 548 47 71 88 117 215 230 274 1.2 1.8 2.6 3.5 6.9 6.2 8.8 5.3 7.6 4.5 5.1 25.1 11.0 32.1 13.5 18.0 27.0 3 3 4 4 4 8 4 240 360 728 1,248 1,973 1,728 2,520 2 2 2 1 1 1 1 1 1 1 16 16 24 24 24 -1 -2 -2L -1 -1L -2 Notes: 1. For full part number details, see the Ordering Information section in DS891, Zynq UltraScale+ MPSoC Overview. 2.-2LE (Tj = 0°C to 110°C). For more details, see the Ordering Information section in DS891, Zynq UltraScale+ MPSoC Overview. Page 4 © Copyright 2016–2017 Xilinx . Zynq® UltraScale+™ MPSoCs: EG Block Diagram Processing System Memory Application Processing Unit NEON™ ARM® Cortex™-A53 32KB I-Cache w/Parity 32KB D-Cache w/ECC GIC-400 DDR4/3/3L, LPDDR4/3 32/64-Bit w/ECC Floating Point Unit Memory Management Unit SCU Embedded Trace Macrocell CCI/SMMU 1 2 3 1MB L2 w/ECC Real-Time Processing Unit ARM Cortex™-R5 128KB TCM w/ECC Vector Floating Point Unit Memory Protection Unit 32KB I-Cache w/ECC 32KB D-Cache w/ECC 1 2 Page 5 1 2 DisplayPort v1.2a USB 3.0 SATA 3.1 4 256KB OCM with ECC Memory Management Unit PCIe® 1.0 / 2.0 64KB L2 Cache PS-GTR Platform Management Unit Configuration and Security Unit System Functions System Management Config AES Decryption, Authentication, Secure Boot Multichannel DMA Voltage/Temp Monitor Timers, WDT, Resets, Clocking & Debug Power Management Block RAM General-Purpose I/O UltraRAM High-Performance HP I/O DSP High-Density HD I/O Interlaken GTH GTY 100G EMAC PCIe Gen4 © Copyright 2016–2017 Xilinx . GigE USB 2.0 CAN UART Quad SPI NOR NAND SD/eMMC High-Speed Connectivity System Monitor General Connectivity SPI TrustZone Programmable Logic Storage & Signal Processing PixelPixel Processor Processor Geometry Processor Functional Safety GIC High-Speed Connectivity Graphics Processing Unit ARM Mali™-400 MP2 Processing System (PS) Zynq® UltraScale+™ MPSoCs: EG Devices Application Processor Unit Real-Time Processor Unit Graphic & Video Acceleration External Memory Connectivity Integrated Block Functionality PS to PL Interface Programmable Logic (PL) Programmable Functionality Memory Clocking Integrated IP Transceivers Speed Grades Device Name(1) ZU2EG ZU3EG ZU4EG ZU5EG ZU6EG ZU7EG ZU9EG ZU11EG ZU15EG ZU17EG Processor Core Quad-core ARM® Cortex™-A53 MPCore™ up to 1.5GHz Memory w/ECC L1 Cache 32KB I / D per core, L2 Cache 1MB, on-chip Memory 256KB Processor Core Dual-core ARM Cortex-R5 MPCore™ up to 600MHz Memory w/ECC L1 Cache 32KB I / D per core, Tightly Coupled Memory 128KB per core Graphics Processing Unit Mali™-400 MP2 up to 667MHz Memory L2 Cache 64KB Dynamic Memory Interface x32/x64: DDR4, LPDDR4, DDR3, DDR3L, LPDDR3 with ECC Static Memory Interfaces NAND, 2x Quad-SPI High-Speed Connectivity PCIe® Gen2 x4, 2x USB3.0, SATA 3.1, DisplayPort, 4x Tri-mode Gigabit Ethernet General Connectivity 2xUSB 2.0, 2x SD/SDIO, 2x UART, 2x CAN 2.0B, 2x I2C, 2x SPI, 4x 32b GPIO Power Management Full / Low / PL / Battery Power Domains RSA, AES, and SHA Security AMS - System Monitor 10-bit, 1MSPS – Temperature and Voltage Monitor 12 x 32/64/128b AXI Ports System Logic Cells (K) 103 154 192 256 469 504 600 653 747 926 CLB Flip-Flops (K) 94 141 176 234 429 461 548 597 682 847 CLB LUTs (K) 47 71 88 117 215 230 274 299 341 423 Max. Distributed RAM (Mb) 1.2 1.8 2.6 3.5 6.9 6.2 8.8 9.1 11.3 8.0 Total Block RAM (Mb) 5.3 7.6 4.5 5.1 25.1 11.0 32.1 21.1 26.2 28.0 UltraRAM (Mb) 13.5 18.0 27.0 22.5 31.5 28.7 Clock Management Tiles (CMTs) 3 3 4 4 4 8 4 8 4 11 DSP Slices 240 360 728 1,248 1,973 1,728 2,520 2,928 3,528 1,590 PCI Express® Gen 3x16 / Gen4x8 2 2 2 4 4 150G Interlaken 1 2 100G Ethernet MAC/PCS w/RS-FEC 2 2 AMS - System Monitor 1 1 1 1 1 1 1 1 1 1 GTH 16.3Gb/s Transceivers 16 16 24 24 24 32 24 44 GTY 32.75Gb/s Transceivers 16 28 (2) Extended -1 -2 -2L -1 -2 -2L -3 -1 -2 -2L -3 Industrial -1 -1L -2 Notes: 1. For full part number details, see the Ordering Information section in DS891, Zynq UltraScale+ MPSoC Overview. 2.-2LE (Tj = 0°C to 110°C). For more details, see the Ordering Information section in DS891, Zynq UltraScale+ MPSoC Overview. Page 6 © Copyright 2016–2017 Xilinx . ZU19EG 1,143 1,045 523 9.8 34.6 36.0 11 1,968 5 4 4 1 44 28 Zynq® UltraScale+™ MPSoCs: EV Block Diagram Processing System Application Processing Unit NEON™ ARM® Cortex™-A53 32KB I-Cache w/Parity 32KB D-Cache w/ECC GIC-400 DDR4/3/3L, LPDDR4/3 32/64 bit w/ECC Floating Point Unit Memory Management Unit SCU Embedded Trace Macrocell CCI/SMMU 1 2 3 128KB TCM w/ECC Vector Floating Point Unit Memory Protection Unit 32KB I-Cache w/ECC 32KB D-Cache w/ECC 1 2 DisplayPort v1.2a 1 2 USB 3.0 SATA 3.1 256KB OCM with ECC Memory Management Unit PCIe® 1.0 / 2.0 64KB L2 Cache PS-GTR Platform Management Unit Configuration and Security Unit System Functions System Management Config AES Decryption, Authentication, Secure Boot Multichannel DMA Voltage/Temp Monitor Timers, WDT, Resets, Clocking & Debug Power Management Functional Safety GIC Pixel Pixel Processor Processor Geometry Processor 1MB L2 w/ECC Real-Time Processing Unit ARM Cortex™-R5 4 High-Speed Connectivity Graphics Processing Unit ARM Mali™-400 MP2 Memory General Connectivity GigE USB 2.0 CAN UART SPI TrustZone Quad SPI NOR NAND SD/eMMC Programmable Logic System Monitor Storage & Signal Processing Page 7 Block RAM General-Purpose I/O High-Speed Connectivity UltraRAM High-Performance HP I/O GTH DSP High-Density HD I/O PCIe Gen4 © Copyright 2016–2017 Xilinx . Video Codec H.265/H.264 Processing System (PS) Zynq® UltraScale+™ MPSoCs: EV Devices Application Processor Unit Real-Time Processor Unit Graphic & Video Acceleration External Memory Connectivity Integrated Block Functionality Device Name(1) Processor Core Memory w/ECC Processor Core Memory w/ECC Graphics Processing Unit Memory Dynamic Memory Interface Static Memory Interfaces High-Speed Connectivity General Connectivity Power Management Security AMS - System Monitor PS to PL Interface Programmable Logic (PL) Programmable Functionality Memory Clocking Integrated IP Transceivers Speed Grades System Logic Cells (K) CLB Flip-Flops (K) CLB LUTs (K) Max. Distributed RAM (Mb) Total Block RAM (Mb) UltraRAM (Mb) Clock Management Tiles (CMTs) DSP Slices Video Codec Unit (VCU) PCI Express® Gen 3x16 / Gen4x8 150G Interlaken 100G Ethernet MAC/PCS w/RS-FEC AMS - System Monitor GTH 16.3Gb/s Transceivers GTY 32.75Gb/s Transceivers Extended(2) Industrial ZU4EV ZU5EV ZU7EV Quad-core ARM® Cortex™-A53 MPCore™ up to 1.5GHz L1 Cache 32KB I / D per core, L2 Cache 1MB, on-chip Memory 256KB Dual-core ARM Cortex-R5 MPCore™ up to 600MHz L1 Cache 32KB I / D per core, Tightly Coupled Memory 128KB per core Mali™-400 MP2 up to 667MHz L2 Cache 64KB x32/x64: DDR4, LPDDR4, DDR3, DDR3L, LPDDR3 with ECC NAND, 2x Quad-SPI PCIe® Gen2 x4, 2x USB3.0, SATA 3.1, DisplayPort, 4x Tri-mode Gigabit Ethernet 2xUSB 2.0, 2x SD/SDIO, 2x UART, 2x CAN 2.0B, 2x I2C, 2x SPI, 4x 32b GPIO Full / Low / PL / Battery Power Domains RSA, AES, and SHA 10-bit, 1MSPS – Temperature and Voltage Monitor 12 x 32/64/128b AXI Ports 192 256 504 176 234 461 88 117 230 2.6 3.5 6.2 4.5 5.1 11.0 13.5 18.0 27.0 4 4 8 728 1,248 1,728 1 1 1 2 2 2 1 1 1 16 16 24 -1 -2 -2L -3 -1 -1L -2 Notes: 1. For full part number details, see the Ordering Information section in DS891, Zynq UltraScale+ MPSoC Overview. 2.-2LE (Tj = 0°C to 110°C). For more details, see the Ordering Information section in DS891, Zynq UltraScale+ MPSoC Overview. Page 8 © Copyright 2016–2017 Xilinx . Zynq® UltraScale+™ MPSoCs PS I/Os(1), 3.3V High-Density (HD) I/O, 1.8V High-Performance (HP) I/Os PS-GTR 6Gb/s, GTH 16.3Gb/s, GTY 32.75Gb/s Pkg Dimensions Footprint(2,3) (mm) ZU2 ZU3 ZU4 ZU5 ZU6 ZU7 ZU9 ZU11 ZU15 ZU17 ZU19 A484(4) 19x19 170, 24, 58 4, 0, 0 170, 24, 58 4, 0, 0 A625(4) 21x21 170, 24, 156 4, 0, 0 170, 24, 156 4, 0, 0 C784(4,5) 23x23 214, 96, 156 4, 0, 0 214, 96, 156 4, 0, 0 B900 31x31 C900 31x31 214, 48, 156 4, 16, 0 214, 48, 156 4, 16, 0 214, 48, 156 4, 16, 0 B1156 35x35 214, 120, 208 4, 24, 0 214, 120, 208 4, 24, 0 214, 120, 208 4, 24, 0 C1156 35x35 B1517 40x40 F1517 40x40 C1760 42.5x42.5 D1760 42.5x42.5 214, 48, 260 214, 48, 260 4, 44, 28 4, 44, 28 E1924 45x45 214, 96, 572 214, 96, 572 4, 44, 0 4, 44, 0 214, 96, 156 214, 96, 156 4, 4, 0 4, 4, 0 214, 48, 156 214, 48, 156 4, 16, 0 4, 16, 0 214, 48, 156 4, 16, 0 214, 48, 312 4, 20, 0 214, 72, 416 4, 16, 0 214, 48, 416 4, 24, 0 © Copyright 2016–2017 Xilinx . 214, 72, 572 214, 72, 572 4, 16, 0 4, 16, 0 214, 48, 416 4, 32, 0 214, 96, 416 4, 32, 16 Notes: 1. PS I/O is a combination of PS MIO and PS DDRIO. 2. Packages with the same last letter and number sequence, e.g., A484, are footprint compatible with all other UltraScale devices with the same sequence. 3. For full part number details, see the Ordering Information section in DS891, Zynq UltraScale+ MPSoC Overview. 4. These packages are only offered in 0.8mm ballpitch. All other packages are offered in 1.0mm ball pitch. 5. GTH transceivers in the C784 package support data rates up to 12.5Gb/s. Page 9 214, 48, 312 4, 20, 0 214, 96, 416 214, 96, 416 4, 32, 16 4, 32, 16 Important: Verify all data in this document with the device data sheets found at www.xilinx.com Zynq® UltraScale+™ MPSoC Device Migration Table The Zynq UltraScale+ family provides footprint compatibility to enable users to migrate designs from one device to another. Any two packages with the same footprint identifier code (last letter and number sequence) are footprint compatible. Zynq® UltraScale+™ CG Devices Pkg EG Devices EV Devices mm ZU2CG ZU3CG ZU4CG ZU5CG ZU6CG ZU7CG ZU9CG ZU2EG ZU3EG ZU4EG ZU5EG ZU6EG ZU7EG ZU9EG ZU11EG ZU15EG ZU17EG ZU19EG ZU4EV ZU5EV ZU7EV A484 19 X X X X A625 21 X X X X C784 23 X X X X B900 31 C900 31 X X x X X B1156 35 X X x X X C1156 35 B1517 40 F1517 40 C1760 42.5 D1760 E1924 X X X X x X X X X X X x x X X X x x X X X X X 42.5 X X 45 X X Page 10 © Copyright 2016–2017 Xilinx . X X X X X Zynq® UltraScale+™ MPSoC Speed Grades Industrial Extended(2) Speed Grade ZU2 CG EG ZU3 CG EG ZU4 CG EG EV Device Name(1) ZU6 ZU7 CG EG CG EG EV ZU5 CG EG EV ZU11 EG ZU15 EG ZU17 EG ZU19 EG -1 -2 -2L -3 – – – – – – – – – -1 -1L -2 Notes: 1. For full part number details, see the Ordering Information section in DS891, Zynq UltraScale+ MPSoC Overview. 2.-2LE (Tj = 0°C to 110°C). For more details, see the Ordering Information section in DS891, Zynq UltraScale+ MPSoC Overview. :: available – :: not offered Page 11 ZU9 CG EG © Copyright 2016–2017 Xilinx . Zynq® UltraScale+™ MPSoC Ordering Information Footprint XC ZU # E Xilinx Commercial Zynq UltraScale + Value Index G -1 Processor Engine Type Speed Grade System G: General Purpose -1: Slowest Identifier V: Video -L1: Low Power C: Dual APU -2: Mid Dual RPU -L2: Low Power E: Quad APU -3: Fastest Dual RPU Single GPU F F V A # E F: Flip-chip F: Lid V: RoHS 6/6 w/ 1.0mm B: Lidless Ball Pitch S: Flip-chip w/ 0.8mm Ball Pitch Package Designator Package Pin Count Temperature Grade (E, I) E = Extended (Tj = 0°C to +100°C) I = Industrial (Tj = –40°C to +100°C) Note: -L2E (Tj = 0°C to +110°C). Refer to DS891, Zynq UltraScale+ MPSoC Overview for additional information. Important: Verify all data in this document with the device data sheets found at www.xilinx.com Page 12 © Copyright 2016–2017 Xilinx . Memory Zynq® UltraScale+™ MPSoCs include block RAM and UltraRAM (high density, dual-port, synchronous memory block), which increase performance, device utilization, and power efficiency. These new features are designed to provide highly efficient solutions for applications that require heterogeneous processing. Total Memory (Mb) ZU2 ZU5 7.6 4.5 13.5 5.1 18.0 ZU6 ZU7 25.1 11.0 27.0 ZU9 ZU11 ZU15 ZU17 ZU19 UltraRAM 5.3 ZU3 ZU4 Block RAM 32.1 21.1 22.5 26.2 31.5 28.0 28.7 34.6 36.0 Important: Verify all data in this document with the device data sheets found at www.xilinx.com Page 13 © Copyright 2016–2017 Xilinx . Transceiver Count and Bandwidth UltraScale™ architecture serial transceivers include the proven on-chip circuits required to provide optimal signal integrity in real world environments, at data rates up to 6.0Gb/s (PS-GTR), 16.3Gb/s (GTH), and 32.75Gb/s (GTY). Total Transceiver Count and Bandwidth PS-GTR GTH GTY PS-GTR = 6.0Gb/s GTH = 16.3Gb/s GTY = 32.75Gb/s ZU2 4 24.0Gb/s ZU3 4 24.0Gb/s ZU4 4 16 224Gb/s ZU5 4 16 224Gb/s ZU6 4 24 415.2Gb/s ZU7 4 24 415.2Gb/s ZU9 4 24 415.2Gb/s ZU11 4 ZU15 4 ZU17 4 44 28 1658.2Gb/s ZU19 4 44 28 1658.2Gb/s 32 24 16 1069.6Gb/s 415.2Gb/s Important: Verify all data in this document with the device data sheets found at www.xilinx.com Page 14 © Copyright 2016–2017 Xilinx . I/O Count The I/Os are classified as PS I/O, high-density (HD) I/O, and high-performance (HP) I/O. The PS I/Os are composed of multi-use I/O (MIO) and DDR I/O, which support 1.8V to 3.3V standards. The HD I/Os are reduced-feature I/Os, providing voltage support from 1.2V to 3.3V. The HP I/Os are optimized for highest performance operation, from 1.0V to 1.8V. PS I/O I/O Counts ZU2 HD I/O HP I/O ZU3 214 214 96 96 156 156 ZU4 214 96 156 ZU5 214 96 156 ZU6 ZU7 214 214 ZU9 214 ZU11 214 ZU15 214 ZU17 214 96 572 ZU19 214 96 572 120 208 48 416 120 208 96 416 120 208 Notes: 1. The PS I/O count is composed of 78 I/Os, which are used to communicate to external components, referred to as multi-use I/O (MIO) and an additional 136 I/Os, which are used to communicate to DDRs, referred to as DDR I/O. Important: Verify all data in this document with the device data sheets found at www.xilinx.com Page 15 © Copyright 2016–2017 Xilinx . References DS890, UltraScale™ Architecture and Product Overview DS891, Zynq® UltraScale+™ MPSoC Overview DS925, Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics UG1075, Zynq UltraScale+ MPSoC Packaging and Pinouts UG1085, Zynq UltraScale+ MPSoC Technical Reference Manual UG1087, Zynq UltraScale+ MPSoC Register Reference UG1137, Zynq UltraScale+ MPSoC: Software Developers Guide UG1169, Zynq UltraScale+ MPSoC QEMU: User Guide UG1186, Zynq UltraScale+ MPSoC OpenAMP: Getting Started Guide UG571, UltraScale Architecture SelectIO™ Resources User Guide UG572, UltraScale Architecture Clocking Resources User Guide UG573, UltraScale Architecture Memory Resources User Guide UG574, UltraScale Architecture Configurable Logic Block User Guide UG576, UltraScale Architecture GTH Transceivers User Guide UG578, UltraScale Architecture GTY Transceivers User Guide UG579, UltraScale Architecture DSP Slice User Guide UG580, UltraScale Architecture System Monitor User Guide UG583, UltraScale Architecture PCB and Pin Planning User Guide PG150, LogiCORE™ IP UltraScale Architecture-Based FPGAs Memory Interface Solutions PG182, UltraScale FPGAs Transceivers Wizard Product Guide Page 16 Important: Verify all data in this document with the device data sheets found at www.xilinx.com XMP104 (v2.3) © Copyright 2016–2017 Xilinx .
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