Emerson Atca 9305 Users Manual Preliminary User’s Manual, #10009109 00

2015-01-05
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User’s Manual
from Emerson Network Power ™
Embedded Computing

ATCA-9305: ATCA® Blade with Dual Cavium Processors

April 2009

The information in this manual has been checked and is believed to be accurate and reliable.
HOWEVER, NO RESPONSIBILITY IS ASSUMED BY EMERSON NETWORK POWER, EMBEDDED
COMPUTING FOR ITS USE OR FOR ANY INACCURACIES. Specifications are subject to change
without notice. EMERSON DOES NOT ASSUME ANY LIABILITY ARISING OUT OF USE OR
OTHER APPLICATION OF ANY PRODUCT, CIRCUIT, OR PROGRAM DESCRIBED HEREIN. This
document does not convey any license under Emerson patents or the rights of others.
Emerson. Consider It Solved is a trademark, and Business-Critical Continuity, Emerson Network Power, and the Emerson Network Power logo are trademarks and service marks of
Emerson Network Power, Embedded Computing, Inc.
© 2009 Emerson Network Power, Embedded Computing, Inc.
Revision Level:

Principal Changes:

Date:

10009109-00

Original release

January 2009

10009109-01

Added “GR-1089-CORE Standard” on page -i
Updated “Product Certification” on page 1-4

April 2009

Copyright © 2009 Emerson Network Power, Embedded Computing, Inc. All rights reserved.

Regulatory Agency Warnings & Notices

The Emerson ATCA-9305 meets the requirements set forth by the Federal Communications
Commission (FCC) in Title 47 of the Code of Federal Regulations. The following information
is provided as required by this agency.
This device complies with part 15 of the FCC Rules. Operation is subject to the following two
conditions: (1) This device may not cause harmful interference, and (2) this device must
accept any interference received, including interference that may cause undesired operation.

FCC RULES AND REGULATIONS — PART 15
This equipment has been tested and found to comply with the limits for a Class A digital
device, pursuant to part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference when the equipment is operated in a commercial environment. This equipment generates, uses and can radiate radio frequency energy
and, if not installed and used in accordance with the instructions, may cause harmful interference to radio communications. Operation of this equipment in a residential area is likely
to cause harmful interference, in which case the user will be required to correct the interference at his own expense.
Caution: Making changes or modifications to the ATCA-9305 hardware without the explicit consent
of Emerson Network Power could invalidate the user’s authority to operate this equipment.
!

EMC COMPLIANCE
The electromagnetic compatibility (EMC) tests used an ATCA-9305 model that includes a
front panel assembly from Emerson Network Power.
Caution: For applications where the ATCA-9305 is provided without a front panel, or where the front
panel has been removed, your system chassis/enclosure must provide the required
!
electromagnetic interference (EMI) shielding to maintain EMC compliance.

GR-1089-CORE STANDARD
Caution: WARNING: The intra-building port(s) of the equipment or subassembly is suitable for
connection to intrabuilding or unexposed wiring or cabling only. The intra-building port(s)
!
of the equipment or subassembly MUST NOT be metallically connected to interfaces that
connect to the OSP or its wiring. These interfaces are designed for use as intra-building
interfaces only (Type 2 or Type 4 ports as described in GR-1089-CORE, Issue 4) and require
isolation from the exposed OSP cabling. The addition of Primary Protectors is not sufficient
protection in order to connect these interfaces metallically to OSP wiring.

10009109-01

ATCA-9305 User’s Manual

i

Regulatory Agency Warnings & Notices

(continued)

EC Declaration of Conformity
According to EN 45014:1998

Manufacturer’s Name:

Emerson Network Power
Embedded Computing

Manufacturer’s Address:

8310 Excelsior Drive
Madison, Wisconsin 53717

Declares that the following product, in accordance with the requirements of 2004/108/EEC, EMC
Directive and 1999/5/EC, RTTE Directive and their amending directives,
Product:

ATCA Blade

Model Name/Number:

ATCA-9305/10009986-xx

has been designed and manufactured to the following specifications:
EN55022:1998 Information Technology Equipment, Radio disturbance characteristics, Limits and
methods of measurement
EN55024:1998 Information Technology Equipment, Immunity characteristics, Limits and methods
of measurement
EN300386 V.1.3.2:2003-5 Electromagnetic compatibility and radio spectrum matters (ERM);
Telecommunication network equipment; EMC requirements
As manufacturer we hereby declare that the product named above has been designed to comply
with the relevant sections of the above referenced specifications. This product complies with the
essential health and safety requirements of the EMC Directive and RTTE Directive. We have an internal production control system that ensures compliance between the manufactured products and
the technical documentation.

Bill Fleury
Compliance Engineer

Issue date: April 7, 2009

ii

ATCA-9305 User’s Manual

10009109-01

Regulatory Agency Warnings & Notices

10009109-01

(continued)

ATCA-9305 User’s Manual

iii

Regulatory Agency Warnings & Notices

iv

ATCA-9305 User’s Manual

10009109-01

(continued)

Contents

1 Overview
Components and Features . . . . . . . . . . . 1-1
Functional Overview . . . . . . . . . . . . . . . . 1-3
Additional Information . . . . . . . . . . . . . . 1-4
Product Certification . . . . . . . . . . . . . 1-4
RoHS Compliance. . . . . . . . . . . . . . . . 1-5
Terminology and Notation . . . . . . . . 1-6
Technical References. . . . . . . . . . . . . 1-6

2 Setup
Electrostatic Discharge . . . . . . . . . . . . . . 2-1
ATCA-9305 Circuit Board . . . . . . . . . . . . 2-1
Connectors . . . . . . . . . . . . . . . . . . . . . 2-7
Configuration Header . . . . . . . . . . . . 2-8
ATCA-9305 Setup . . . . . . . . . . . . . . . . . . . 2-8
Power Requirements . . . . . . . . . . . . . 2-9
Environmental Considerations . . . . 2-9
Hot Swap . . . . . . . . . . . . . . . . . . . . . .2-10

Insert a board: . . . . . . . . . 2-11
Remove a board: . . . . . . . 2-11

Troubleshooting . . . . . . . . . . . . . . . . . . . 2-11
Technical Support . . . . . . . . . . . . . .2-11
Product Repair . . . . . . . . . . . . . . . . .2-12
Comments and Suggestions . . . . .2-13

3 Cavium Processor Complex
Cavium CN5860 Processor . . . . . . . . . . . 3-1
Cavium Memory Map . . . . . . . . . . . . 3-2
PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
CN5860 Boot Over PCI . . . . . . . . . . . 3-3
Cavium Reset . . . . . . . . . . . . . . . . . . . 3-4
Cavium Ethernet. . . . . . . . . . . . . . . . . . . . 3-5
Cavium Monitor . . . . . . . . . . . . . . . . . . . . 3-6
Start-up Display . . . . . . . . . . . . . . . . . 3-6
Power-up/Reset Sequence . . . . . . . . 3-6
Diagnostic Tests During Power-up and
Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7
POST Diagnostic Results . . . . . . 3-7
Cavium Environment Variables . . . . 3-8
Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
DDR2 SDRAM . . . . . . . . . . . . . . . . . . . 3-9
RLDRAM . . . . . . . . . . . . . . . . . . . . . . . . 3-9
I2C EEPROM. . . . . . . . . . . . . . . . . . . . . 3-9
Flash, 512 KB x 8 . . . . . . . . . . . . . . . .3-10
Flash, 4 MB x 16 . . . . . . . . . . . . . . . .3-10

10009109-01

StratixGX Interconnect . . . . . . . . . . . . . 3-10
PLD Registers . . . . . . . . . . . . . . . . . . 3-10
Data Registers . . . . . . . . . . . . . 3-10
Address Registers . . . . . . . . . . 3-12
Control Register. . . . . . . . . . . . 3-12
Version Register. . . . . . . . . . . . 3-13
Scratch Register . . . . . . . . . . . . 3-13
Headers and Connectors. . . . . . . . . . . . 3-14
COP/JTAG Headers . . . . . . . . . . . . . 3-14
Console Serial Ports (optional) . . . 3-15

4 Management Complex
MPC8548 Processor. . . . . . . . . . . . . . . . . .4-2
MPC8548 Memory Map . . . . . . . . . . 4-2
Chip Selects . . . . . . . . . . . . . . . . . . . . 4-5
Reset Diagram . . . . . . . . . . . . . . . . . . 4-6
Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-7
SDRAM. . . . . . . . . . . . . . . . . . . . . . . . . 4-7
Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7
512 KB x 8 (optional). . . . . . . . . 4-7
4M x 16 . . . . . . . . . . . . . . . . . . . . 4-7
1 GB x 16 . . . . . . . . . . . . . . . . . . . 4-8
64 MB x 16. . . . . . . . . . . . . . . . . . 4-8
PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-8
PCI Express . . . . . . . . . . . . . . . . . . . . . 4-8
I2C Interface . . . . . . . . . . . . . . . . . . . . . . . .4-9
Management Processor Header and Serial
Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-9
JTAG/COP Interface (optional) . . . . 4-9
Serial Debug Port. . . . . . . . . . . . . . . 4-10

5 Management Processor
CPLD
MPC8548 PLD Register Summary . . . . . .5-1
Product ID . . . . . . . . . . . . . . . . . . . . . . 5-2
Hardware Version . . . . . . . . . . . . . . . 5-2
PLD Version. . . . . . . . . . . . . . . . . . . . . 5-3
PLL Reset Configuration . . . . . . . . . . 5-3
Hardware Configuration 0 . . . . . . . . 5-3
Jumper Settings . . . . . . . . . . . . . . . . . 5-4
LED . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4
Reset Event . . . . . . . . . . . . . . . . . . . . . 5-5
Reset Command 1. . . . . . . . . . . . . . . 5-5
Reset Command 2. . . . . . . . . . . . . . . 5-6
Reset Command 3. . . . . . . . . . . . . . . 5-6

ATCA-9305 User’s Manual

v

Contents

(continued)

Reset Command 4 . . . . . . . . . . . . . . . 5-7
Reset Command 5 . . . . . . . . . . . . . . . 5-7
Reset Command Sticky #1 . . . . . . . . 5-7
Reset Command Sticky #2 . . . . . . . . 5-8
Boot Device Redirection . . . . . . . . . . 5-8
Miscellaneous Control. . . . . . . . . . . . 5-9
Low Frequency Timer 1 and 2 . . . . . 5-9
RTM GPIO State . . . . . . . . . . . . . . . .5-10
RTM GPIO Control . . . . . . . . . . . . . .5-10
RTM Status . . . . . . . . . . . . . . . . . . . .5-10
Cavium 1 C_MUL Clock Divisor Control
5-11
Cavium 2 C_MUL Clock Divisor Control
5-11
JTAG . . . . . . . . . . . . . . . . . . . . . . . . . .5-12
Cavium GPIO Control . . . . . . . . . . .5-12
Cavium GPIO Data Out . . . . . . . . . .5-13
Cavium GPIO Data In . . . . . . . . . . . .5-13
IPMP/IPMC GPIO Control . . . . . . . .5-14
LPC Bus Control . . . . . . . . . . . . . . . .5-14
LPC Data. . . . . . . . . . . . . . . . . . . . . . .5-14
Serial IRQ Interrupt 1 . . . . . . . . . . .5-15
Serial IRQ Interrupt 2 . . . . . . . . . . .5-15

6 Ethernet Interface
Broadcom BCM56802 Switch . . . . . . . . .6-1
Ethernet Switching. . . . . . . . . . . . . . . . . . .6-1
Ethernet Transceivers . . . . . . . . . . . . 6-2
Ethernet Switch Ports . . . . . . . . . . . . 6-2
VLAN Setup . . . . . . . . . . . . . . . . . . . . . 6-3
MPC8548 Management Processor Ethernet
Address. . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-3
Front Panel Ethernet Ports . . . . . . . . 6-4

7 System Management
IPMC Overview . . . . . . . . . . . . . . . . . . . . . .7-1
IPMI Messaging . . . . . . . . . . . . . . . . . . . . . .7-2
IPMI Completion Codes . . . . . . . . . . 7-4
IPMB Protocol . . . . . . . . . . . . . . . . . . . . . . .7-5
SIPL Protocol . . . . . . . . . . . . . . . . . . . . . . . .7-6
Message Bridging . . . . . . . . . . . . . . . . . . . .7-7
Standard Commands. . . . . . . . . . . . . . . . .7-9
OEM Boot Options . . . . . . . . . . . . . . . . . 7-11
IPMC Watchdog Timer Commands. . . 7-12
Watchdog Timer Actions . . . . . . . .7-12

vi

ATCA-9305 User’s Manual

10009109-01

Watchdog Timer Use Field and
Expiration Flags . . . . . . . . . . . . . . . . 7-12
Using the Timer Use Field and
Expiration Flags . . . . . . . . . . . . 7-13
Watchdog Timer Event Logging . . 7-13
Monitor Support for Watchdog
Timer . . . . . . . . . . . . . . . . . . . . . 7-13
Reset Watchdog Timer Command7-14
Set Watchdog Timer Command. . 7-14
Get Watchdog Timer Command . 7-16
FRU LEDs . . . . . . . . . . . . . . . . . . . . . . . . . 7-18
Get FRU LED Properties Command7-19
Get LED Color Capabilities Command .
7-19
Set FRU LED State Command . . . . 7-21
Get FRU LED State Command . . . . 7-22
Vendor Commands . . . . . . . . . . . . . . . . 7-24
Get Status . . . . . . . . . . . . . . . . . . . . . 7-25
Get Serial Interface Properties . . . 7-27
Set Serial Interface Properties . . . . 7-28
Get Debug Level . . . . . . . . . . . . . . . 7-29
Set Debug Level . . . . . . . . . . . . . . . . 7-29
Get Hardware Address . . . . . . . . . . 7-30
Set Hardware Address . . . . . . . . . . 7-30
Get Handle Switch. . . . . . . . . . . . . . 7-31
Set Handle Switch . . . . . . . . . . . . . . 7-31
Get Payload Communication Time-Out
7-32
Set Payload Communication Time-Out
7-32
Enable Payload Control . . . . . . . . . 7-32
Disable Payload Control . . . . . . . . . 7-33
Reset IPMC . . . . . . . . . . . . . . . . . . . . 7-33
Hang IPMC . . . . . . . . . . . . . . . . . . . . 7-33
Bused Resource . . . . . . . . . . . . . . . . 7-34
Bused Resource Status . . . . . . . . . . 7-34
Graceful Reset . . . . . . . . . . . . . . . . . 7-35
Diagnostic Interrupt Results . . . . . 7-36
Get Payload Shutdown Time-Out. 7-36
Set Payload Shutdown Time-Out . 7-37
Set Local FRU LED State . . . . . . . . . 7-38
Get Local FRU LED State . . . . . . . . . 7-39
Update Discrete Sensor . . . . . . . . . 7-40
Update Threshold Sensor. . . . . . . . 7-40
Boot Device Redirection (BDR) . . . . . . 7-41
Message Listeners . . . . . . . . . . . . . . . . . 7-43
Add Message Listener. . . . . . . . . . . 7-44
Remove Message Listener . . . . . . . 7-44

Contents

(continued)

Get Message Listener List . . . . . . . .7-45
System Firmware Progress Sensor . . . 7-45
Entities and Entity Associations . . . . . . 7-46
Sensors and Sensor Data Records . . . . 7-48
FRU Inventory . . . . . . . . . . . . . . . . . . . . . 7-50
E-Keying . . . . . . . . . . . . . . . . . . . . . . . . . . 7-51
Base Point-to-Point Connectivity .7-52
HPM.1 Firmware Upgrade. . . . . . . . . . . 7-52
HPM.1 Reliable Field Upgrade
Procedure . . . . . . . . . . . . . . . . . . . . .7-53
IPMC Headers . . . . . . . . . . . . . . . . . . . . . 7-53

8 Back Panel Connectors
Zone 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-1
Zone 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-2
Zone 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-3

9 Management Processor
Monitor
Command-Line Features. . . . . . . . . . . . . .9-1
Basic Operation. . . . . . . . . . . . . . . . . . . . . .9-3
Power-up/Reset Sequence . . . . . . . . 9-3
POST Diagnostic Results . . . . . . . . . . 9-4
Monitor SDRAM Usage . . . . . . . . . . . 9-5
Monitor Recovery and Updates . . . . . . . .9-5
Recovering the Monitor . . . . . . . . . . 9-6
Resetting Environment Variables . . 9-6
Updating the Monitor via TFTP . . . . 9-6
Monitor Command Reference . . . . . . . . .9-7
Command Syntax. . . . . . . . . . . . . . . . 9-7
Command Help . . . . . . . . . . . . . . . . . 9-8
Typographic Conventions . . . . . . . . 9-8
Boot Commands. . . . . . . . . . . . . . . . . . . . .9-8
bootd . . . . . . . . . . . . . . . . . . . . . . . . . . 9-8
bootelf . . . . . . . . . . . . . . . . . . . . . . . . . 9-8
bootm . . . . . . . . . . . . . . . . . . . . . . . . . 9-8
bootp . . . . . . . . . . . . . . . . . . . . . . . . . . 9-8
bootv . . . . . . . . . . . . . . . . . . . . . . . . . . 9-9
bootvx . . . . . . . . . . . . . . . . . . . . . . . . . 9-9
dhcp . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-9
rarpboot. . . . . . . . . . . . . . . . . . . . . . .9-10
tftpboot . . . . . . . . . . . . . . . . . . . . . . .9-10
File Load Commands . . . . . . . . . . . . . . . 9-11
loadb . . . . . . . . . . . . . . . . . . . . . . . . .9-11
loads . . . . . . . . . . . . . . . . . . . . . . . . . .9-11
Memory Commands . . . . . . . . . . . . . . . 9-11

10009109-01

cmp . . . . . . . . . . . . . . . . . . . . . . . . . . 9-12
cp . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-12
find . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-12
md . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-12
mm. . . . . . . . . . . . . . . . . . . . . . . . . . . 9-13
nm . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-13
mw . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-13
Flash Commands . . . . . . . . . . . . . . . . . . 9-14
cp . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-14
erase . . . . . . . . . . . . . . . . . . . . . . . . . 9-14
flinfo. . . . . . . . . . . . . . . . . . . . . . . . . . 9-14
protect. . . . . . . . . . . . . . . . . . . . . . . . 9-15
EEPROM/I2C Commands . . . . . . . . . . . 9-15
eeprom . . . . . . . . . . . . . . . . . . . . . . . 9-15
icrc32 . . . . . . . . . . . . . . . . . . . . . . . . . 9-16
iloop . . . . . . . . . . . . . . . . . . . . . . . . . . 9-16
imd . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-16
imm . . . . . . . . . . . . . . . . . . . . . . . . . . 9-16
imw . . . . . . . . . . . . . . . . . . . . . . . . . . 9-16
inm . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-16
iprobe . . . . . . . . . . . . . . . . . . . . . . . . 9-17
IPMC Commands . . . . . . . . . . . . . . . . . . 9-17
bootdev. . . . . . . . . . . . . . . . . . . . . . . 9-17
fru . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-17
fruinit . . . . . . . . . . . . . . . . . . . . . . . . . 9-18
fruled . . . . . . . . . . . . . . . . . . . . . . . . . 9-18
ipmchpmfw . . . . . . . . . . . . . . . . . . . 9-18
sensor . . . . . . . . . . . . . . . . . . . . . . . . 9-18
Environment Parameter Commands . 9-19
printenv. . . . . . . . . . . . . . . . . . . . . . . 9-19
saveenv . . . . . . . . . . . . . . . . . . . . . . . 9-19
setenv . . . . . . . . . . . . . . . . . . . . . . . . 9-19
Test Commands . . . . . . . . . . . . . . . . . . . 9-20
diags. . . . . . . . . . . . . . . . . . . . . . . . . . 9-20
mtest . . . . . . . . . . . . . . . . . . . . . . . . . 9-20
um . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-20
Other Commands. . . . . . . . . . . . . . . . . . 9-20
autoscr. . . . . . . . . . . . . . . . . . . . . . . . 9-20
base . . . . . . . . . . . . . . . . . . . . . . . . . . 9-20
bdinfo . . . . . . . . . . . . . . . . . . . . . . . . 9-21
coninfo . . . . . . . . . . . . . . . . . . . . . . . 9-21
crc32 . . . . . . . . . . . . . . . . . . . . . . . . . 9-21
date . . . . . . . . . . . . . . . . . . . . . . . . . . 9-21
echo . . . . . . . . . . . . . . . . . . . . . . . . . . 9-21
enumpci . . . . . . . . . . . . . . . . . . . . . . 9-21
go . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-21
help . . . . . . . . . . . . . . . . . . . . . . . . . . 9-22

ATCA-9305 User’s Manual

vii

Contents

(continued)

iminfo . . . . . . . . . . . . . . . . . . . . . . . . .9-22
isdram . . . . . . . . . . . . . . . . . . . . . . . .9-22
loop. . . . . . . . . . . . . . . . . . . . . . . . . . .9-22
memmap . . . . . . . . . . . . . . . . . . . . . .9-22
moninit . . . . . . . . . . . . . . . . . . . . . . .9-22
pci . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-23
phy . . . . . . . . . . . . . . . . . . . . . . . . . . .9-23
ping. . . . . . . . . . . . . . . . . . . . . . . . . . .9-24
reset . . . . . . . . . . . . . . . . . . . . . . . . . .9-24
run. . . . . . . . . . . . . . . . . . . . . . . . . . . .9-24
script. . . . . . . . . . . . . . . . . . . . . . . . . .9-24
showmac . . . . . . . . . . . . . . . . . . . . . .9-24
showpci . . . . . . . . . . . . . . . . . . . . . . .9-24

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sleep. . . . . . . . . . . . . . . . . . . . . . . . . . 9-25
switch_reg . . . . . . . . . . . . . . . . . . . . 9-25
version . . . . . . . . . . . . . . . . . . . . . . . . 9-25
vlan. . . . . . . . . . . . . . . . . . . . . . . . . . . 9-25
MPC8548 Environment Variables . . . . 9-26
Troubleshooting. . . . . . . . . . . . . . . . . . . 9-28
Download Formats. . . . . . . . . . . . . . . . . 9-28
Binary. . . . . . . . . . . . . . . . . . . . . . . . . 9-29
Motorola S-Record . . . . . . . . . . . . . 9-29

10 Acronyms

Figures

Figure 1-1:

General System Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3

Figure 2-1:

ATCA-9305 Front Panel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2

Figure 2-2:

Component Map, Top (Rev. 01) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3

Figure 2-3:

Component Map, Bottom (Rev. 01). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4

Figure 2-4:

LED, Fuse and Switch Locations, Top . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5

Figure 2-5:

LED and Switch Locations, Bottom. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6

Figure 2-6:

Configuration Header, J9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8

Figure 2-7:

Air Flow Graph . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10

Figure 2-8:

Serial Number and Product ID on Top Side. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12

Figure 3-1:

Cavium Processor Complex Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1

Figure 3-2:

CN5860 Reset Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4

Figure 3-3:

Example Cavium CN5860 Monitor Start-up Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6

Figure 3-4:

Power-up/Reset CN5860 Boot Sequence Flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7

Figure 4-1:

MPC8548 Management Processor Complex Block Diagram. . . . . . . . . . . . . . . . . . . . . 4-1

Figure 4-2:

MPC8548 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3

Figure 4-3:

MPC8548 Reset Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6

Figure 6-1:

Ethernet Switching Interface Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2

Figure 7-1:

IPMC Connections Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2

Figure 7-2:

Extension Command Request Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-7

Figure 7-3:

Extension Command Response Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-7

Figure 7-4:

Boot Device Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-42

Figure 7-5:

Boot Redirection Control Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-42

Figure 7-6:

IPMB Entity Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-47

Figure 8-1:

Zone 1 Connector, P10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1

Figure 8-2:

Zone 2 and 3 Connectors; J23, J30-J31 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2

Figure 8-3:

Zone 3 Connector, J33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4

Figure 9-1:

Example MPC8548 Monitor Start-up Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2

Figure 9-2:

Power-up/Reset Sequence Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4

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Tables

Table 1-1:

Regulatory Agency Compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4

Table 1-2:

Technical References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6

Table 2-1:

Circuit Board Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1

Table 2-2:

Typical Power Requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9

Table 2-3:

Environmental Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9

Table 3-1:

CN5860 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1

Table 3-2:

Cavium Address Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2

Table 3-3:

Ethernet Port Address. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5

Table 3-4:

POST Diagnostic Results–Bit Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8

Table 3-5:

Standard Cavium Environment Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8

Table 3-6:

Cavium NVRAM Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10

Table 3-7:

CN5860 Processor COP/JTAG Headers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14

Table 3-8:

CN5860 Processor Debug Headers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15

Table 4-1:

MPC8548 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2

Table 4-2:

MPC8548 Address Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3

Table 4-3:

Device Chip Selects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5

Table 4-4:

PCI Device Interrupts and ID Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8

Table 4-5:

I2C Device Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9

Table 4-6:

MPC8548 NVRAM Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9

Table 4-7:

Serial Debug Connector, P2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9

Table 4-8:

Serial Debug Connector, P7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10

Table 5-1:

PLD Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1

Table 5-2:

Low Frequency Timer Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10

Table 6-1:

Ethernet Switch Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2

Table 6-2:

VLAN Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3

Table 6-3:

Ethernet Port Address. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4

Table 6-4:

Front Panel Ethernet Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4

Table 7-1:

Network Function Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3

Table 7-2:

Completion Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4

Table 7-3:

Format for IPMI Request Message . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5

Table 7-4:

Format for IPMI Response Message . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-6

Table 7-5:

IPMC IPMI Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-9

Table 7-6:

Emerson Boot Option Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-11

Table 7-7:

IPMC Watchdog Timer Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-12

Table 7-8:

Reset Watchdog Timer Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-14

Table 7-9:

Set Watchdog Timer Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-15

Table 7-10:

Get Watchdog Timer Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-16

Table 7-11:

FRU LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-18

Table 7-12:

Get FRU LED Properties Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-19

Table 7-13:

Get LED Color Capabilities Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-19

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Table 7-14:

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Set FRU LED State Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-21

Table 7-15:

Get FRU LED State Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-22

Table 7-16:

Vendor Command Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-24

Table 7-17:

Get Status Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-25

Table 7-18:

Get Serial Interface Properties Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-27

Table 7-19:

Set Serial Interface Properties Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-28

Table 7-20:

Get Debug Level Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-29

Table 7-21:

Set Debug Level Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-29

Table 7-22:

Get Hardware Address Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-30

Table 7-23:

Set Hardware Address Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-30

Table 7-24:

Get Handle Switch Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-31

Table 7-25:

Set Handle Switch Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-31

Table 7-26:

Get Payload Communication Time-Out Command . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-32

Table 7-27:

Set Payload Communication Time-Out Command . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-32

Table 7-28:

Enable Payload Control Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-32

Table 7-29:

Disable Payload Control Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-33

Table 7-30:

Reset IPMC Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-33

Table 7-31:

Hang IPMC Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-33

Table 7-32:

Bused Resource Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-34

Table 7-33:

Bused Resource Status Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-35

Table 7-34:

Graceful Reset Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-36

Table 7-35:

Diagnostic Interrupt Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-36

Table 7-36:

Get Payload Shutdown Time-Out Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-37

Table 7-37:

Set Payload Shutdown Time-Out Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-37

Table 7-38:

Set Local FRU LED State Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-38

Table 7-39:

Get Local FRU LED State Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-39

Table 7-40:

Update Discrete Sensor Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-40

Table 7-41:

Update Threshold Sensor Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-40

Table 7-42:

Add Message Listener Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-44

Table 7-43:

Remove Message Listener Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-44

Table 7-44:

Get Message Listener List Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-45

Table 7-45:

Update System Firmware Progress Sensor Command . . . . . . . . . . . . . . . . . . . . . . . . . 7-46

Table 7-46:

IPMI Threshold Sensors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-48

Table 7-47:

IPMI Discrete Sensors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-48

Table 7-48:

Event Message Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-49

Table 7-49:

FRU Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-50

Table 7-50:

Link Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-52

Table 7-51:

IPMP CPLD JP1 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-53

Table 7-52:

IPMP EIA-232 P4 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-53

Table 8-1:

Zone 1 Connector, P10 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1

Table 8-2:

Zone 2 Connector, J23 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3

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Table 8-3:

Zone 3 Connector, J30 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3

Table 8-4:

Zone 3 Connector, J31 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4

Table 8-5:

Zone 3 Connector, J33 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4

Table 9-1:

Debug LED Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2

Table 9-2:

POST Diagnostic Results–Bit Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-5

Table 9-3:

Monitor Address per Flash Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-6

Table 9-4:

Static IP Ethernet Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-9

Table 9-5:

DHCP Ethernet Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-10

Table 9-6:

Standard Environment Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-26

Table 9-7:

Optional Environment Variables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-28

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Register 3-1:

Data 31:24 (0x0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10

Register 3-2:

Data 23:16 (0x1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11

Register 3-3:

Data 15:8 (0x2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11

Register 3-4:

Data 7:0 (0x3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11

Register 3-5:

Address 9:8 (0x4). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12

Register 3-6:

Address 7:0 (0x5). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12

Register 3-7:

Control (0x6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12

Register 3-8:

Version (0x7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13

Register 3-9:

Scratch (0x8-0x3F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13

Register 5-1:

Product ID (0x00) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2

Register 5-2:

Hardware Version (0x04) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2

Register 5-3:

PLD Version (0x08) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3

Register 5-4:

PLL Reset Configuration (0x0C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3

Register 5-5:

Hardware Configuration 0 (0x10). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4

Register 5-6:

Jumper Settings (0x18). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4

Register 5-7:

LED (0x1C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5

Register 5-8:

Reset Event (0x20) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5

Register 5-9:

Reset Command 1 (0x24) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6

Register 5-10: Reset Command 2 (0x28) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6
Register 5-11: Reset Command 3 (0x2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6
Register 5-12: Reset Command 4 (0x30) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7
Register 5-13: Reset Command 5 (0x34) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7
Register 5-14: Reset Command Sticky #1 (0x38) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8
Register 5-15: Reset Command Sticky #2 (0x3C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8
Register 5-16: Boot Device Redirection (0x50) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9
Register 5-17: Miscellaneous Control (0x54) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9
Register 5-18: RTM GPIO State (0x60). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10
Register 5-19: RTM GPIO Control (0x64). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10
Register 5-20: RTM Control (0x68). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11
Register 5-21: Cavium 1 C_MULL Clock Divisor Control (0x70) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11
Register 5-22: Cavium 2 C_MULL Clock Divisor Control (0x74) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12
Register 5-23: JTAG (0x78). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12
Register 5-24: Cavium GPIO Control (0x80) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12
Register 5-25: Cavium GPIO Data Out (0x84) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13
Register 5-26: Cavium GPIO Data In (0x88) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13
Register 5-27: IPMP/IPMC GPIO Control (0x8C). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-14
Register 5-28: LPC Bus (0xD0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-14
Register 5-29: LPC Data (0xD4). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15
Register 5-30: Serial IRQ Interrupts 1 (0xD8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15
Register 5-31: Serial IRQ Interrupts 2 (0xDC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15

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Section 1

Overview

The ATCA-9305 is an Advanced Telecom Computing Architecture (AdvancedTCA®, ATCA®)
blade based on dual Cavium OCTEON™ CN5860 processors and the Freescale™ Semiconductor MPC8548 management processor. This blade is targeted at security and packet-processing applications in the wireless and transport market segments. These markets include
data-plane packet-processor, security co-processor, video compression, and pattern matching.
The ATCA-9305 complies with the SCOPE recommended profile for central office ATCA systems, PICMG® 3.0 ATCA mechanical specifications, E-keying, and Hot Swap.

COMPONENTS AND FEATURES
The following is a brief summary of the ATCA-9305 hardware components and features:
Cavium Processor : The Cavium CN5860 processor is a highly programmable, high-performance 16-core architecture operating up to 800 MHz.
Management Processor:
The Freescale PowerQUICC™ III MPC8548 processor is a 32-bit enhanced e500 core operating at 1 GHz.
Ethernet Switch: The Broadcom® BCM56802 is a sixteen-port, 10 GbE switch which interconnects the processors using SPI to XAUI™ bridges. The functionality includes both 10-Gbps XAUI and 1Gbps SGMII PHY interfaces.
Stratix™ GX Bridge: There are two packet routing Altera® SPI-4.2 high-speed interconnect to XAUI bridges per
CN5860 processor.
Ethernet: 10/100/1000BASE-T Ethernet ports are accessible via the front panel RJ45 connectors and
through the base channel on the back panel. The 10 GbE ports route to the back panel
through the fabric and RTM connectors.
Serial Port: The front panel serial port (MGT CSL) connects to the MPC8548 management processor.
System Management: This product supports an Intelligent Platform Management Controller (IPMC) based on a
proprietary BMR-H8S-AMCc® reference design from Pigeon Point Systems. The IPMC has
an inter-integrated circuit (I2C) controller to support an Intelligent Management Platform
Bus (IPMB) that routes to the AdvancedTCA connector. The IPMB allows for features such as
remote shutdown, remote reset, payload voltage monitoring, temperature monitoring,
and access to Field Replaceable Unit (FRU) data.
PCI/PCIe: The PCI bus allows for read/write memory access between the MPC8548 processor, Ethernet switch, and Cavium processors. The four lane PCI Express® (PCIe) routes between the
MPC8548 and the optional RTM.

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Overview:

Components and Features

Real-time Clock: The STMicroelectronics M41T00S RTC provides counters for seconds, minutes, hours, day,
date, month, years, and century. The M41T00S serial interface supports I2C bus and has a
super-cap backup capable of maintaining the clock for a minimum of two hours.
Software: The Cavium CN5860 processor provides a GNU compiler that implements the MIPS64 Rel 2
instruction set in addition to the specialized instructions and a Linux® Board Specific Package (BSP) including the IP-stack optimization. The CN5860 also provides libraries that take
advantage of the chip’s hardware acceleration for certain security protocols.
RTM (optional): This blade supports a custom Rear Transition Module (RTM) with the following I/O:
• Either two or six 10GbE connections
• One x4 PCI Express port from the MPC8548
• Connections for an MMC to control Hot Swap
• MPC8548 console port
For more detailed information, see the ATCA-9305 Rear Transition Module User’s Manual.

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ATCA-9305 User’s Manual

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Overview:

Functional Overview

FUNCTIONAL OVERVIEW
The following block diagram provides a functional overview for the ATCA-9305:
Figure 1-1: General System Block Diagram
Console

RJ45

RJ45

Mag

Mag

Socketed
ROM
512KB
x8

KSL
CPLD

Console
(ENG use only)

Latched Adrs

BCM5461S BCM5461S

NAND
Flash
1GB
x 16

Adrs/Data
COP/JTAG
MPC8548
Management
Processor

P1 DDR
SDRAM

COP/
JTAG

NOR
Flash
512Mb or
64MB x 16

PQ DDR2
SDRAM

I2C
EEPROM

(ENG use only)

NOR
Flash
4M
x 16

A/D

I2C
EEPROM

Console

PCIe x4

COP/
JTAG

RTC

P2 DDR2
SDRAM

BCM5461S

I2C
I2C
EEPROM
RLDRAM
64MB
RLDRAM
64MB
RLDRAM
64MB
RLDRAM
64MB

D1_DDR2 Serial 0 PCI
Bus
I2C
IDSEL11

Cavium
SPI-0
Octeon
CN5860
Processor 1
SPI-1
Local Bus
Addr/Data
Serial 1

Socketed
ROM
512K
x8

NOR
Flash
4M
x8

PCI Bus
Serial CFG
EEPROM

3
SGMII

Stratix II GX
#1

6 XAUI

Stratix II GX
#2

5 XAUI

4
SGMII

PCI Serial 0 D1_DDR2
Bus
I2C
IDSEL12

PCI Bus
IDSEL13
XAUI 13

BCM56802
XAUI 10 Gb
Switch
SGMII
2

SGMII
1

XAUI 14
To RTM
XAUI
XAUI
8 7 11-12 15 -18

SPI-0

Stratix II GX
#4

SPI-1
Local Bus
Addr/Data

1

2
Base

P10

10G - 2 PORTS

Mag

3 2 1 0 3 2 1 0
FC2
FC1
10G Fabric
J23

10009109-01

RLDRAM
64MB
RLDRAM
64MB

Socketed
ROM
512K
x8

10G - 4 PORTS
Mag

I2C
EEPROM

Serial 1

BCM5482
IPMB

Cavium
Octeon
CN5860
Processor 2

Stratix II GX
#3

I2C

NOR
Flash
4M
x8

RLDRAM
64MB
RLDRAM
64MB

RTM RST
12V Hot Swap
RTM Console
PQ I2C

J30

J31

J33

ATCA-9305 User’s Manual

1-3

Overview:

Additional Information

ADDITIONAL INFORMATION
This section lists the ATCA-9305 hardware’s regulatory certifications and briefly discusses
the terminology and notation conventions used in this manual. It also lists general technical
references.
Mean time between failures (MTBF) has been calculated at 439,924 hours using the Telcordia SR-332, Issue 1 (Reliability Prediction for Electronic Equipment), method 2 at 30° C.

Product Certification
The ATCA-9305 hardware has been tested to comply with various safety, immunity, and
emissions requirements as specified by the Federal Communications Commission (FCC),
Underwriters Laboratories (UL), and others. The following table summarizes this compliance:
Table 1-1: Regulatory Agency Compliance

Type:

Specification:

Safety

IEC60950/EN60950 – Safety of Information Technology Equipment
(Western Europe)
UL60950, CSA C22.2 No. 60950 – Safety of Information Technology
Equipment, including Electrical Business Equipment (BI-National)
GR1089-CORE
Global IEC – CB Scheme Report IEC 60950, all country deviations

Environmental

1-4

ATCA-9305 User’s Manual

NEBS: Telecordia GR-63 –
Section 4.1.1 Transportation and Storage Environmental Criteria;
Section 4.1.2 Operating Temperature and Humidity;
Section 4.1.3 Altitude;
Section 4.1 4 Temperature Margins;
Section 4.4.1 Earthquake Environment;
Section 4.4.4 Office Vibration:
Section 4.4.5 Transportation Vibration

10009109-01

Overview:

Additional Information

(continued)

Type:

Specification:

EMC

FCC Part 15, Class A– Title 47, Code of Federal Regulations, Radio
Frequency Devices
ICES 003, Class A – Radiated and Conducted Emissions, Canada
NEBS: Telecordia GR-1089 level 3 – Emissions and Immunity (circuit pack
level testing only)
EN55022 – Information Technology Equipment, Radio Disturbance
Characteristics, Limits and Methods of Measurement
EN55024 – Information Technology Equipment, Immunity
Characteristics, Limits and Methods of Measurement
ETSI EN300386 – Electromagnetic Compatibility and Radio Spectrum
Matters (ERM), Telecommunication Network Equipment,
Electromagnetic Compatibility (EMC) Requirements
AS/NZS 3548 003, Class A – Standard for radiated and conducted
emissions for Australia and New Zealand

Emerson maintains test reports that provide specific information regarding the methods
and equipment used in compliance testing. Unshielded external I/O cables, loose screws, or
a poorly grounded chassis may adversely affect the ATCA-9305 hardware’s ability to comply
with any of the stated specifications.
The UL web site at ul.com has a list of Emerson’s UL certifications. To find the list, search in
the online certifications directory using Emerson’s UL file number, E190079. There is a list
for products distributed in the United States, as well as a list for products shipped to Canada. To find the ATCA-9305, search in the list for 10009986-xx, where xx changes with each
revision of the printed circuit board.
The Ethernet connection of the equipment or subassembly must be connected with
shielded cables that are grounded at both ends.

RoHS Compliance
The ATCA-9305 is compliant with the European Union’s RoHS (Restriction of use of Hazardous Substances) directive created to limit harm to the environment and human health by
restricting the use of harmful substances in electrical and electronic equipment. Effective
July 1, 2006, RoHS restricts the use of six substances: cadmium (Cd), mercury (Hg), hexavalent chromium (Cr (VI)), polybrominated biphenyls (PBBs), polybrominated diphenyl ethers
(PBDEs) and lead (Pb). Configurations that are RoHS compliant are built with lead-free solder.
To obtain a certificate of conformity (CoC) for the ATCA-9305, send an e-mail to
sales@artesyncp.com or call 1-800-356-9602. Have the part number(s)
(e.g., C000####-##) for your configuration(s) available when contacting Emerson.

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Overview:

Additional Information

Terminology and Notation
Active low signals: An active low signal is indicated with an asterisk * after the signal name.
Byte, word: Throughout this manual byte refers to 8 bits, word refers to 16 bits, and long word refers to
32 bits, double long word refers to 64 bits.
PLD: This manual uses the acronym, PLD, as a generic term for programmable logic device (also
known as FPGA, CPLD, EPLD, etc.).
Radix 2 and 16: Hexadecimal numbers end with a subscript 16. Binary numbers are shown with a
subscript 2.

Technical References
Further information on basic operation and programming of the ATCA-9305 components
can be found in documents listed in Table 1-2.
Table 1-2: Technical References

Device /
Interface:
ATCA

Document: 1
AdvancedTCA® Base Specification
(PICMG® 3.0 Revision 2.0 March 18, 2005)
Engineering Change Notice 3.0-1.0-001
(PICMG® 3.0 R2.0: ECN 3.0-2.0-001 June 15, 2005)
Ethernet/Fibre Channel for AdvancedTCA™ Systems
(PICMG® 3.1 Revision 1.0 January 22, 2003)
http://www.picmg.org

CPU
CN5860
MPC8548

Cavium Networks OCTEON™ Plus CN58XX Hardware Reference Manual
(Cavium Networks, CN58XX-HM-1.2 Sept. 2008)
http:/www.caviumnetworks.com
MPC8548E PowerQUICC™ III Integrated Processor Family Reference Manual
(Freescale™ Semiconductor, Inc. MPC8548ERM Rev.2, 02/2007
http://www.freescale.com

DRAM

576Mb: x9, x18, x36 2.5V VEXT, 1.8C VDD, HSTL, CIO,RLDRAM II Data Sheet
(Micron Technology, Inc. 576Mb_RLDRAM_II_CIO_D1.fm - Rev C 9/07 EN)
http://www.micron.com

EEPROM

Atmel® 2-Wire Serial EEPROM 64K (8192 x 8) Preliminary Data Sheet
(Atmel Corporation, 5174C-SEEPR-6/07)
http://www.atmel.com

Ethernet
BCM5461S
BCM5482

10/100/1000BASE-T Gigabit Ethernet Transceiver Data Sheet
(Broadcom® Corporation, Document 5461S-DS17-R 5/12/08)
10/100/1000BASE-T Gigabit Ethernet Transceiver Data Sheet
(Broadcom® Corporation, Document 5482-DS04-R 10/18/07)
http://www.broadcom.com

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ATCA-9305 User’s Manual

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Overview:

Additional Information

Device /
Interface:
Flash

Document: 1

(continued)

32 Mbit (x8/x16) Concurrent SuperFlash Data Sheet
(Silicon Storage Technology, Inc., S71270-01-000 9/05)
http://www.sst.com
mDOC H3 Embedded Flash Drive (EFD) featuring Embedded TrueFFS® Flash Management
Software Preliminary Data Sheet
(msystems 92-DS-1205-10 Rev. 0.2 June 2006)
http://www.m-systems.com/mobile
StrataFlash® Embedded Memory (P33) Data Sheet
(Intel®, Order Number: 314749-004 November 2007)
http://www.intel.com
4. Serial Configuration Devices (EPCS1, EPCA4, EPCS16, & EPCS64)
(Altera® Corporation CS1014-2.0 April 2007)
http://www.altera.com

IPMI

IPMI — Intelligent Platform Management Interface Specification v2.0
(Intel Hewlett-Packard NEC Dell, Rev. 1.0, Feb. 12, 2004)
IPMI — Intelligent Platform Management Bus Communications Protocol Specification v1.0
(Intel Hewlett-Packard NEC Dell, Rev. 1.0, November 15, 1999)
IPMI — Platform Management FRU Storage Definition v1.0
(Intel Hewlett-Packard NEC Dell, Rev. 1.1, September 27, 1999)
http://www.intel.com/design/servers/ipmi/
Hardware Platform Management IPM Controller Firmware Upgrade Specification v1.0
(PICMG HPM.1 R1.0 May 4, 2007)
http://www.picmg.org

RTC
M41T00S

Serial Access Real-Time Clock Data Sheet
(STMicroelectronics December 2004)

Switch
BCM56802

BCM56800 Series 20-Port 10-Gigabit Ethernet Multilayer Switch Preliminary Data Sheet
(Broadcom® Corporation, Document 56800-DS03-R 12/28/07)
http://www.broadcom.com

1. Frequently, the most current information regarding addenda/errata for specific documents may be
found on the corresponding web site.

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ATCA-9305 User’s Manual

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Section 2

Setup

This chapter describes the physical layout of the boards, the setup process, and how to
check for proper operation once the boards have been installed. This chapter also includes
troubleshooting, service, and warranty information.

ELECTROSTATIC DISCHARGE
Before you begin the setup process, please remember that electrostatic discharge (ESD) can
easily damage the components on the ATCA-9305 hardware. Electronic devices, especially
those with programmable parts, are susceptible to ESD, which can result in operational failure. Unless you ground yourself properly, static charges can accumulate in your body and
cause ESD damage when you touch the board.
Caution: Use proper static protection and handle ATCA-9305 boards only when absolutely
necessary. Always wear a wriststrap to ground your body before touching a board. Keep
!
your body grounded while handling the board. Hold the board by its edges–do not touch
any components or circuits. When the board is not in an enclosure, store it in a staticshielding bag.
To ground yourself, wear a grounding wriststrap. Simply placing the board on top of a staticshielding bag does not provide any protection–place it on a grounded dissipative mat. Do
not place the board on metal or other conductive surfaces.

ATCA-9305 CIRCUIT BOARD
The ATCA-9305 circuit board is an ATCA blade assembly and complies with the PICMG 3.0
ATCA mechanical specification. It uses a 16-layer printed circuit board with the following
dimensions:
Table 2-1: Circuit Board Dimensions

Width:

Depth:

Height:

Weight (typical):

12.687 in.
(322.25 mm)

11.024 in.
(280.01 mm)

< .84 in.
(<21.33 mm)

4.2 lb.
(1.91 kg)1

1. This is the typical weight for the ATCA-9305. Board weight varies slightly per configuration; contact
Technical Support if you require a specific configuration weight.

The following figures show the front panel, component maps, and LED locations for the
ATCA-9305 circuit board.

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Setup:

ATCA-9305 Circuit Board

Figure 2-1: ATCA-9305 Front Panel

MGT ETH
SPD

Red/Amber = Out of Service (OOS)

O
O
S

Green = In Service (2)

2

LINK
ACT
SPD

Amber = User Defined (3)

3

SWITCH
ETH

Management Console

Reset
Blue Hot Swap

LINK
ACT

Ethernet Speed (top LED)
Off = 10 Mbps
Yellow = 100 Mbps
Port 1
Green = 1000Mbps
Port 2 Ethernet Link/Activity (bottom LED)
Off = No Link
On= Link, No Activity
Blink = Link/Activity

MGT CSL

RST
H/S

ATCA-9035

Note: The electromagnetic compatibility (EMC) tests used an ATCA-9305 model that includes a front panel assembly from Emerson Network Power, Embedded Computing.

Caution: For applications where the ATCA-9305 is provided without a front panel, or where the front
panel has been removed, your system chassis/enclosure must provide the required
!
electromagnetic interference (EMI) shielding to maintain CE compliance.

2-2

ATCA-9305 User’s Manual

10009109-01

Setup:

ATCA-9305 Circuit Board

Figure 2-2: Component Map, Top (Rev. 01)
CR4

C21

C22

C19

C20

C17

C16

C15

CR3

C7

U1
C18

C2
R4

R5

R3

C6

C84

C83

C178

U15
CN58x0
Processor 2

R83

C212

R332

R84

R85

R86

R87

C238

C211
C225

C239

CR11

C242

CR12
R1060

C213

C199

C215

C214

J3

C226

C200

R67
R81

C164

L8

C201

C216

J4

J5

J6

C243

C244

C245

R93

R94

R95

C251

C252

C253

C267

C268

C269

C300

C302

C304

C299

C301

C303

C305

R92

R73

R80

C162

C227

C228

C240

C241

C247

C248

C255

C256

C271

C272

C306

C349

R104

C347

C348

R103

C346

C343

U16

C2113

C187

C208

C203

C205

C207

C209

C217

C219

C221

C223

C220

C222

C231

C233

C235

C234

C236

C218

C229

C230

C232

C224

C257

C259

C261

C263

C258

C260

C262

C264

C273

C275

C277

C279

C274

C276

C278

C280

C291

C293

C295

C292

C294

C296

C307

C309

C311

C308

C310

C297

C298

C313

C312

C314

C323

R105

R106
R110

C385

C384
R117

R118

C395

C396

C394

R120

C428

C430

C431

C446

C448

C427

C429

C445

C444

C447

C425

C426

C442

C443

C424

C433

U22
L36

C458

L40

L41
L43
L45

L58

L62

C604

C607

C608

C664

C670

C671

C672

C656

C643

C666

C667

R248

R249

C665

C673

C637

L65

C675

J11 J12 J13 J14
C681

C682

R259

R260

R261

C687

C688

C689

C693

C694

C695

C696

C683

C555

C556

C557

C571

C569

C568

C566

CR49

R252

C680

R254

R253

C678
R255

R1059

R258

C570

C565

U58

R247
C674
R251

CR48

J23
80-pin
Zone 2
ATCA
Connector

U55
12V
Power Supply

C2118

C677

C2106

C684

R262

C690

C691

C2111

C685

C697

R256

C669

CR47

CR46

CR44
R231

R229

C641

C642

C660
R246

C668

C567

C564

C550

C548

C552

C553

C554

C549

C551

C561

C563

C559

C562

U51 U52

R220

C686
C692

R264

C698

U59

U60

R263

C655

C663

C529

C531

R257

C654

C653

C662

C640

C639

C657

C652

C651

C638

C658

C647

C650

C648

C646

C645

U57

C649

C659
R245

C528

R221

+

U56
CN58x0
Processor 1

C527

R226

+

C644

C526

L59

U50
PHY

C599

R217

C603

L63

R214

C598

C610

R213

C591

C597

R238

C634

C633

C500

C501

R210

C590

C609

R1057

C581
R208

C617

CR42

R1056

U48
Microcontroller

C560

C558

L57

L55

L56

L54

L53

L52

L51

U44

R225

R230

U54

C625

C499

L48

L47

L49

R202

R204

R203

R201

R98

U47

CR43

CR41

CR40

CR38

CR39

CR37

CR35

L39

R194

R1049

R222

CR36

C616

C632

L38

L44

R243

R205

U49

C601

C606

L37

L42

L50

R180

JP1

C530
C546

U43

C547

C544

C545

C542

C543

C540

C541

C539

C537

C538

C536

C535

C533

C534

C532

R223

R224

R215

L35

R242

C676

C484

C490

R1050

R219

L64

U34
BCM5680x
Switch

L33

P4

SW1

U39

C635

R250

C471

C485

C488

L34

R241

C661

C470

C469

L32

L46

U46

R212

C636

R244

L23

C459

L22

L21

C456

L20

L16

L14

U30

Y5

R211

C615

C614

L15

R1034

U28

U29

C580

C589

C588

C586

C579

C595

C594

R179

C493
C522

C525

C523

C520

C521

C524

C518

C517

C519

C515

C516

C514

C513

C511

C512

C510

C509

C508

C507

C506

C505

C504

C503

C502

R198

R199

F3

C621

C631

C441

R1036

R1035

R1039

C492

CR34

R216

R237

C630

C629

R236

Polar Key
ATCA Guide

C482

U36 U37 U38

Y7

C578

C577

C576

R207

C574

C573

C572
C592

C593

C600

C436

C483

U32

C494

U40

Y6

C602

C613
C612

C423

C434

C468

C495

U33

R765

R235

C360

L29

R218

C611

C417

C422

C624

C628

C355

C359

C358

R116

C416

C626

R234

C353

C357

L26

Y8

C575

R206

C584

C582
C583

C354

L25

C496

R189

R188

R187

R186

R185

U31

R192

C605

R761

C336

C489

RN12

RN11

R183

C620

C619

C712

C335

C334

C352

CR31

R196

R228

C324

C333

CR21

R200

R227

J31
80-pin
Zone 3
ATCA
Connector
J30
80-pin
Zone 3
ATCA
Connector

CR18

R193

R197

C618

C702

C704

C706

C703

C705

C707

C700

C699

C708

C718

C717

R267

C716

C715

C714

C711

C713

C701

C709

F4

C723

F5

C719

R265

C2149
R266

R757

C186

CR22

R195

CR29

CR28

R176

C487

C486

CR27

R175
R178

CR25

CR23

CR24

U27 Y4

U53
R759

C172

L24

R184

U42
SPI-XAUI
Bridge

R190

R191

P5
P6

R233

C197

C206

C491

R182

R232

C195

C204

CR32

R181

R240

C193

C202

C435

CR16

CR19

CR33

U41
SPI-XAUI
Bridge

C421

CR14

J9

C467

RN10

R177

CR26

C466

R1032
C477

C479

C478

C476

C475

R174

L31

L28

R171

R173

CR30

R172

C473

C472

R170

CR20

C480

L30

R166

Y3

R165

CR17

R168

R169

C481

L27

U23S

C463

CR15

R163

R164

C420

Y9

C2103

U24
KSL
CPLD

RN9

RN8

C455
C462

C474

C419

C596

R1041

C461
C465
C464

R239

C171

C184

C437

C418

R144

R143

R142
R159

R158

R157
C452

C453

C451
C450
C460

R167

C622

C169

C170

C185

L11

U21

RN7

RN6

R156

R154

R155

R152

R150

R151

R149

R153

R147

R148

C432

R140

R139

R138

R136

R134

R133

R135

R132

R137

R130

R131

R129

R126

R127

R128

R125

R124

C439

C438

L13

L12

R145

R146

C440

C454

C449

R162

C623

C196

C191

L18

C415

RN5

R160

R161

C627

C194

L19

C414

CR13

U45

C192

R115

C393

L17

C390
C402

C406
C410

C408

C413

C345

C411

C404

R141

L61

C154

C155

C183

C398

R121

C403

C392

Y2

U20

C405

C400

C409

C399

C391

C389

C388
C401

C387

R119

C382

C381
C380

C377

U17

R114

RN4

C383

C412

L60

C140

C182

C370

C375

C379

C378

R111

R112

R123

P7
Mini-B
USB

C139

C152

C153

C168

R107

RN2

C374

C407

C397

R109

RN3

U19
MPC8548
Processor

C386

R108
C373

C376

R113

U18
SO-CDIMM

U35S

C137

C138

C167

C368
C369

C372

U26

C151

C190

C322

C2104

RN1

C365

C338

R101

C366

C364

C367
C332
C350
C356

C331

C342

C341

C371

U25

C150

C180

C351

Y1

C330

R100

C329

C340

C328

R99

C339

C337

C270

C288

C285
C286

C287

C283

C284

C327

C325

C320

C326

C363

C361

C254

C290

C319
R2

C362

L9

C289

R97

C136

C165

C166

C321

R819

C316

C315

C317
C318

R102

L10

C282

C281

C265
R96

C135

C134

C148

C149

C246

C249

C250

C133

C181

C457

R334

CR10

C198

R72
R70

C177

R71

C176

C147

C161

C146

C160

C145

C144

C174

R82

C237

C143

C173

C175

CR45

C188

C158

R460

R91

C159

C163

C157

R462

C210

C141

C142

U13
SPI-XAUI
Bridge

CR9

R90

R89

R66

C130

C131

U14
R88

C129

C132

P2

P3
RJ45

R65

C2110
C128

C156

R79

R39

C105
C104

C125

C124

R64

C123

C122

C121

R63

R62

R61

C120

C2147

R69

R77

C119

C2145

U12

R68

R75

R15

C28

C27
C43

C44

C56
R42

R40

R41

C66

C67

C65

C64

C62

C63

C61

C59

C126
C117
C118

C179

R58

R57

R59

R56

R54
R60

CR6

F2
R78

R46

C85

C106

CR8

R76

M2

R45

R44

C2116

C116

CR7

R74

R43

C75

C115

C114

C113

CR5

C112

U11

J33
24-pin ATCA
Connector

R25

U9

C2119

C92
R52

R55

P1
RJ45

C68
C2108

R51

L7

C103

C96

C95

C94

C97

C109

C110

C111

C108

C98

U8

C54

R53

L5

C90

R50

M1

C69

C102

C81

C89

C87
C88

C80

C86

C101

C79

C78

L6

C100

R1010

C77

L4
R49

R27

C50

C49
C48

C51

C47

C46

C53
R26

R38

C58
C74
C82

R24

R23

R22

C52

R37

C99

R48

C76

C93
C107

U6

C33

U7

C344

R28

C42

L1

R10

R9
C26

R8

C24

C25

R7

R21

C41

R36

C60

C72

C73

L3

C57

C71
R47

C10
C14

R19

R17

R18

C32

R16

C31
R20

R35

U10
SPI-XAUI
Bridge

Polar Key
ATCA Guide

C9

C8
C13

R6

C30

C29

C40

C38

C37

C36

C35

L2

C34

F1

C39

R13

C12

U5

R14

R11

R12

J1

R34

C45

R32

R33

R31

C55

R29

R30

C5

C4
C11

C1

C3

U4

CR2

C2109

U2

U3S

CR1

C2146

R1

C2148
R269

C728

C729

C730
R270

C731

C2120

F6

R273

U62

C742

C737

C738

C736

C735

U61

C741

C740

C745

R272

C734

C733

R271

C2117

C767

R274
C743

R275
R277

C727

C726

C732

C2107

C724

C725

C722

C721

R276

C710

+

R268
C720

C744

C758

C759

C772

C773

C761

C757

L67

C766

C774

C776

C787

U63
C796

C793

CR51

CR53

CR52

C801

CR50

C2105

C783
C791

C789

R295

10009109-01

L66
F7
F8

C777

C790

U65

C797
C800

C2112

C788

C782

U64

C781

C769

C780

R287

R288

C779

C778

R285

R286
R289

C785

C786

R290

C784

L68

R294

R292

R293

R291

C795
C799
C798

J15

F10

C762

C756

C760

C771

R282
C765

C770

C747
C755

C754

C746
C752

C753
C764

R283
R284

C751

R279
R280

C748

R296

C792

+

C763

C768

C750

C749

R278

C775

R281

C794

P10
30-pin
Zone 13
ATCA
Connector

L69
F9

ATCA-9305 User’s Manual

2-3

Setup:

ATCA-9305 Circuit Board

R1007

R1008

C2100

C2098

R1002

R1003

C2097

R1005

C2101

R1004

C2102

J16

R1006

R1009

Figure 2-3: Component Map, Bottom (Rev. 01)

R1001

R1000

R999

R998

C2096

U82

C2099

C2095

U81

C2093

R997

C2094

C2092
C2091

R996

R994

R995

C2090

R981

R980

R982

C2088

R986

R987

R983

R989

R990

R984

R991

R993

R985

R988

R992

C2089
RN39

C2087

RN36

C2049

R961

C1958

R960

C1937

C1929

C1934

C1931

C1940

C1938

C1941

C1927

C1932

C1928

C1935

C1912

C1904

C1907

C1905

C1910

C1908

C1911

C1906

C1888

C1887

C1859

C1902

C1889
C1860

C1903

C1909

C1890
C1862

C1857

C1884

C1943
C1891

C1861

C1930

C1883

C1944
C1914

C1913

C1892

C1864

C1946

C1933

C1936

C1865

C1915

C1939

C1942

C1863

C1950

C1949

C1947

C1917

C1918

C1945

C1916

C1952

C1953

C1921

C1920

C1955

C1948

C1951

C1919

C1924

C1923

C1956

C1957

C1954

R930

C1880

C1882

C1881

C1844

C1886

C1848

C1846

C1885

C1851

C1854

C1850

C1856

C1847

C1853

C1852

C1855

C1849

C1893
C1867

C1845

C1896

R914

C1895

R918

C1894

R920

R916

C1870

R922

C1868

R923

R924

R919

C1871

R925

R926

R969

R966

C2023

C2048
C2026

C2047

C2027

C2031

C2030

C2034

C2035

C2029

C2028

C2033

C2032

C2025

C1986

C1995

C1985

C2001

C1981

C1997

C1983

C1980

C1999

C1991

C1989

C1982

C1993

C1984

C1988

C1987

C1998

C1992

C2000

C1996

C1990

C1994

C1962

C1961

C1960

C1959

C1964

C1966

C1965

C1967

C1969

C1968

C1963

C2006
C1972

C2013

R970

C2024

R1018

R1017
C2058

C2037

C2008
C1973

C2050

C2036

C2038
C2007

C2010
C1974

C2051

C2052

C2004

C2011

C2009

C2012
C1975

C2053

C2055

C2002

C2015

C2054

C2056

C2057

C1970

C2040

C2039

C2017

C2071

C1971

C2044
C2019

C2041

C2045

C2043

C2042

C2021

C2016

C2014

C2020

C2018

C2072

R937

C1926

C1901

C1925

R931

R927

R928

R921

C1879

R917

C1826

C1825

C1824

C1838

C1842

C1823

C1822

R910

R905

R908
R909

C1820

C1821

R904

R902

R903

C1817

C1815

C1816

R886

R885

C1810

R883

R884

R888

R887

R890

R889

R891
R881

R893

R892
R882

R894

R895

R897

R900

R901

R896

R898

R899

C1814

C1811

U80

C1819

C1827

C1828

C1818

C1858

C1829

C1812

C1831
C1830

C1813

C1833
C1832

C1843

C1866

C1835
C1834

R912

C1869

C1837
C1836

R907

C1841

R915

C1872

C1840
C1839

R906

C1875

C1878

R911

C2073

R1037

R938

R932

C1922

R939

R913

R933

C1977

R1047
R944

R940

R936

C1978

R945

R947

R941

R942

C1898

R946

R949

C1897

R948

R950

C1899

R952

C1873

R953

R954

C1874

R955

R956

R935

C2060

C2064

C1976

R934
R957

R958

R943

C2059

C2062

C2063

C2065

C1979

C2046

R963

R962

R959

R972

C2061

C2066

R968

R951

R971
C2074

C2077

C2003

C2068
C2067

C2076

C2078

C1900

R965

R964

C2075
C2079

C1877

RN32

C2080
C2081

C2005

C2082

C1876

RN34

RN33

R973

RN31

CR57

C2069

R974

C2022

R929

C2070

R975

R967

SW2

C2085

R976

C2083

RN37

R978

RN35

Q5

R977

RN38

C2086

C2084

R979

C1809
L100

R880

C1804

R1053

C2192

C1711

R769

R770

R771

R772

R773

RN29

RN30

R742

C1607
C1606

C1658

C1657

C1653

C1655

C1630

C1598

C1596

C1594

C1592

C1597

RN28
RN26

RN27

RN25

C1554

C1521

C1555

C1588
C1590

C1551

C1517

C1516

C1514

C1503

C1502

R675

C1437

C1415

C1416

C1487

C1486

C1469
C1468

C1446
C1432
C1409

C1412
C1413

RN20

C1405

R672

C1403

C1402

C1404

C1467

C1447

C1448

C1433

C1408

C1410

C1411

C1414
C1406

C1485

C1489

C1470
C1450
C1449

C1434

C1418

C1407

R665

C1397

C1398

C1400

C1396

C1399

R642

C1276

C1280

C1277

C1281

C1299

C1288

C1282

C1286

C1283

R609

R608

C1272

R606

C1258
C1259

C1244

C1234

R579

R573

C1218

R503

U70

R388

R542

R636

R635

R634

C1387

C1389

C1359

C1358

R633

R540

R543

R544

R545

R541

C1084

C1162

C1165

C1179

C1161
C1160

C1164

C1163

C1166

C1138

C1141

C1139

C1140
C1118

C1117

C1119

C1116

C1087

C1085

C1089

C1086

C1169

C1168
C1142
C1120
C1090

C1143
C1121
C1092

C1174

C1182

C1183

C1178

C1171

C1172

C1177

C1175

C1180

C1185

C1186

C1153

C1149

C1148

C1146

C1150

C1144

C1152

C1151

C1154

C1147
C1125

C1145

C1128

C1124

C1129

C1123

C1130

C1098

C1122

C1131

C1126

C1132

C1127

C1102

C1108

C1107

C1099

C1093

C1101

C1096

C1105

C1110

C1104

C1189
C1155
C1133

C1111

C1095

C1193

C1190

C1157

C1156

C1135

C1134

C1113

C1056

C1055

C1054

C1053

R1013

R435

C1052

R1014

R425

C1018

C1020
C961
C920

C1019

C1021
C964

C962

C963

C959

C921

C919

C1057

C1058

C922

C1023

C966

C968

C965

C923

C1022

C1061

C1062

C1066

C1060

C1024

C1059

C1064

C1025

C1063

C1065

C1028

C1032

C1030

C1029

C1027

C1026

C1031

C1033

C970

C1034

C974

C972

C988

C982

C980

C978

C976

C990

C986

C1088

C969

C984

C1091

C981

C987

C985

C983

C1069

C1094

C973

C1068

C1097

C1100

C975

C1067

C1103

C979

C1071

C1070
C1035

C1072

C1106

C1109

C1112

C971

R397

C960

C958
C957

C967

R404

R408

C940

R395
C933

C931

C934

C932

C930

C905

C904

C903

C939

C937

C935

C938

C936

C908

C906

C2130
R396

R394

R393

R392

C928

C925

C927

C926

C902

C901

C918

C2160
L106

C941

C910
C898

R390

C899

R389

C900

R391

C907

R1019

C909

C895

R1020

C2131
C896

R386

R464

R463

R436

C977

R413

R403

C989

C2158

L78

C1198

C924

R415

R405

C929

C943

R417

R407

C994

C942

C944

R1038

R414

C1037

R448

R426

R416

C1036

R427

C992

C1000

C945

C946

C1194
C1137

R439

R438

R428

R418

R419

R409

C999

C991

C1004

C947

C1167

C993

C1008

C948
C949

C1170

R1048

R406

R429

R420

L83

C1011

C1173

C2132

C894
R385

R383

L76
C893

R384

C892

R380

R382

C891

R379

R381

R449

C1075

R1030

C2159

C1079

C1081
C1048

C1049

C1046

C1045

C1015

C1014

C1013

C1012
C950

C954

C952

C1002
C1001

C912

C915

R430

C1039

C1040

C1005
C1003

C1176

R447
R450

R440

C1041

C1006
C1007

C913

C914

R387

C1043

C1010

C897

L77

Q1

C1044
C1009

C1181

C996

R451

C1076

C1078

C1077

C2129

R421

C951

R398

C917
Q2

C1080

C1042

C2161

R400

R399

C916

C956

C955

C1016

R410

R401

L79

C1047

R422

C1199

C1184

C1159

R442

R431

C1200

C1188

C995

R443

C953

R411

L105

R423

C911

R424

L80

R432

C1050

C1202

C1191

C1211

R478

R454

R402

R433

C1051

C1201

C1204

C1195

R446

R441
R444

C1082

C1222

R495

R494

C1203

C1206

C1158

R455

C1205

C1208

C1136

R456

R457

C1207

C1187

C1114

R452

R458

R479
C1209

C1192

C1212

R437

U69

R453

R466

R465

C1210

C1196

C1073

R461

R459

R468

R467

C1213

C1074

R469

C1214

C1038

R483

R484

R485

R486

C2184

C2177

R518

R499

R498

R496

C998

R473

R475

R474

R472

R470

R471

C1215
R476

C2188

C1219

R497

R480

R482

C2193

L82

C1115

C1083

R563

R519
R501

R500

C997

R504

R505

R508

R506

R509

R507

R510

R490

R488

R491

R489

R511
R492

R487

R512
R493

R513

R514

R516

C1217

R515

R502

L85

C1216

C1017

R547

R549

C1220
R520

R517

L81

R445

R548

R550

R551

C1223

R521

R525

R526

R529

R530

R528

R527

C1221
L86

Q3

R434

C1329

R571

R572

R575

R576

R574

C1230

R564

U72

R538

R556
R531

R553

R557

R554

R558
R533

R532

R552

R559
R534

R522

R560
R535

C1224

R523

R562

R561

R537

C1231

R1021

C1225

R546

C1227

R580

R566

R565

R536

R578

R587

R577

C1235

R588

R581
C1233
C1226

R481

R412

C1330

R593

R582
C1232

R539

L84

Q4

R625

R626

R594

C1249
C1241

C1243

C1246
C1245

C1247

R599

C1248
C1250

C1242

R555

R567

R624

R607

R600
C1257

C1251

R524

R569

C1237

C1327

R611

C1271

C1274

C1260
C1261

R601

C1236

R583

R568

C1239

R585

R570

C1238

R617

U73

C1273

C1278

C1262
C1263

C1252

R584

C1253

R589

C1254

R590

R591

C1229

R595

R592

R586

C1264

C1265

C1266
C1255

R596

R597

C1228

RN13

C1267

R603

R604

U71
PHY

CR55

U74

C1291

R602
C1268

R605

R598

R1022

CR54

R627

C1342

R615

C1300

C1290

C1292

C1293
C1294

C1279

R1011

C1304

C1295
C1296

C1275

C1269

C1285

C1270

C1301

C1302

C1303

C1306

C1307

C1308

C1284

C1328

C1317
C1318

R1012

C1305

C1310

C1297
C1287

R619

R618

C1321

C1322

C1309

C1311

RN14

C1314

RN15
C1298

C1312

C1381

C1353

U75
NAND
Flash

R637

R628

R620
C1319
R621

C1256

R477

R638

R639

R630

C1240

CR56

R641

R640

C1331

C1320

R616

C1313

R643

R629
C1332

C1335

C1323

R610

C1289

C1197

C1333

RN18
RN16

C1325

C1334

C1324

RN17

C1326
C1316

C1315

C1343

C1344

C1336

C1338

R614

C1345
C1346
C1337

R631

R623

R622

C1382

R612

C1347
C1350

C1352

RN19

C1341

C1354

C1355

C1348

R632

C1339

R613

C1356

R645

R644

C1349

C1383

C890

R361

R359

R360

R363

R362

R364

R365

R367

R366

C887

R369

R368

R373

R370

R372

R371

R375

R374

R343
R341

R340

R336

R335

R328

R327

R326

R331

R330

R329

R342

R346

R349

R348

R344

R345

R347

R351

R350

R353

R352

C2175
C2169

R337

C2183

R338

R333

R356

C884

R355

R376

R357

C885

R354

C888

C883

C2166

C889

C886

C2171

R377

R378
R358
R339
C882

R325

C877

C876

C847

C2163

L108

C834

C831

C835

C830

C843

C846

C861

C863

C860

C862

C867
C851

C2134

R1031

C2162

C879

C858

C857

L107

C878

C873

C875

C872
C854

C840

C871
C856

C855

C841

C842

C866

C868

C850

C836
C837

C833

C839

C852

C849

C869

C848

C2165

R320
R318

C844

C822

C2136

C845

U67

C823

C2133

L70

C829
C828

C827

C825

C824

C826

U66

C821

L71

L73

C838

R322

C2164

L74

C2135
C870

C853

C832

C859

R323

C865

C874

C881

L72

C864

U68
PHY

C880

R324

L75

C820

R321

C2167

C815

C803
R300

R301

R303

R304
R302

C802
R299

R298
R297

2-4

ATCA-9305 User’s Manual

R315

C818

R308
C806
R305

C804

10009109-01

C809

C810

R307

R306
C807

C808

R311

C812

R310

R312

R313

R309

R314

C814

C816

C2182

C811

C2170

C813

C2190

C2189

R316

C817

C819

R317

R319

C805

C1380

C1379

C1368
R652

R646

C1340

C1384

C1385

C1361

R647

C1386

C1360

R653

R648

C1388

C1362

R655

R657

C1363

R654

C1364

R658

R656

C1372

R664

R659

R660

C1366
C1365

R662

C1367

C1392

C1393

C1394

C1375

C1390

C1373

C1374

C1376

C1371

C1370

R668

R669

R666

R661

C1369

R670

C1395
R663
R651

C1377

R649

R650

C1378

U76

R853
C1762

C1763

C1764

C1765

C1766

L98

C1488

R718

C1490

C1471

C1451

C1453

C1435

C1438

C1492
C1491

C1472

C1452
C1455

C1419

C1493

C1495

C1473
R1027

C1454

R1026

C1474

C1456

C1439

C1440

C1417

R673

C1494

C1497
C1498

C1475
C1476
C1457

C1458

C1441

C1401

RN23

C1477
C1478
C1459

RN22

R688

R687

R689

C1442

R690

C1420

StrataFlash

C1767

C1768

C1769

C1513

C1519

C1500

C1501

C1499

C1479
C1462

C1461

RN24

R705

C1480

R706

R709

R707
R693

C1460
R691

C1357

R805

R803

R804

R807

R809

R808

R810

C1549
C1515

R806

R811

C1585

C1586

C1587
C1550

C1552
C1518

C1436

C1505

C1464

R694

C1463

R698

R696

R699

R697

R700

R695

C1651

C1589

C1591
C1593

C1595

C1600

C1556

C1391

U77
PHY

C1351

R854

R857

C1652

C1626

C1599

C1602

C1522

C1496

R710

R712

RN21

R676

R678

L99

C1773

C1772

C1774

C1775

C1771

C1776

C1656

C1627
C1628

C1601

C1603

C1504

R711

R713

R692

R677

C1770

C1777

C1661

C1662

C1604

C1557

C1523

R728

R719

R721
R720
C1481
C1482
R715

R701
R703

L90

R812

R813

R814

R815

R817

R816

C1678

C1654

C1660
C1663

R748

R740

C1605

C1520

R730

C1525

R722

C1524

R708

C1526

R734

R733

R731

C1527

R732

R729

R714

R671

R667

R855

R856
C1791

R859

C1792

R860

R858

C1802

C1733
C1732

C1735
C1734

C1739

C1736

C1740

R1040

C1737

C1744

C1745
C1729

C1731

R785

R786

C1730

R787

R788

C1738

R790

R791

R792

R794

R793

R795

R796

R800

R798

R797

R801

R799

R753

C1610

C1608

R739

C1443

C1562

C1560

C1558

C1559

C1528

C1508

C1571

R749

R741

R743

C2125

C1564

C1565

C1563

C1570

C1535

C1533

C1536

C1507

R723

C1506

R702

L91

C1702

C1680
C1659

C1553

R735

C1423

C1703

C1700

C1681
R760

C1664

R751

R750

C1609

R744

R704

R682

C1704

C1679
C1682

C1683

C1629

C1631

R755

C1667

C1666

C1634

C1611

C1669

C1671

C1633

C1636

C1635

C1612

C1632

C1715

C1689

C1688

C2172

C2156

C1692

C1691

C1668
C1637

C1615

C1614
C1566

C1670

C1640

C1639

C1638

C1616

C1613

C1569

C1567

R752

R745

R736

C1465

C2174
L87

C1705

C1707

C1708

C1684

C1665

R1016

L103

L93

C1425

L88

C1426

L89

R674

C1427

R683

C1428

R684

C1431

C1429

C1430

R685

R686

C1532

C1725
C1721

C1701
C1709

C1686

C1687

R1015

R756

R754

C1534

C1750

C1726
C1722

R783

C1685

R724

R727

R716

C1752

C1751

C1706

L104

C1693

R725

C1424

C2173

C1510

L92

C1511

C1723

C1710

C2191

C1509

C1538
R726

C1512

C2176

C1444

C1724

R779

R774

C2157

C1529
C1530

C1727

R775

C2127

C1561

C1531

R122

R781

L95

C1568

R1046

C1728

R784

R1033

R679

C1540

R737

R680

C1544

R738

C1537

R681

C1545

C2178 C2181

C1572

C1573

C1539

C1422
C1421

C1716
C1694

C1641

C2155
C1617

C1541

C1542

C1581

C1466
C2186

R1029

R762

C2151

R746

C1575

C1543

C1546

C1690

C1713

R763
C1642
C1643

C1578

C1547

C1712
C2128

C1742

C1741

L97

C2150

C1717

C1719
C1720

C2122

C2152

C1697

C2124

C1695

C1698

L102

C1699

C1672

C1674

C1676

C1673

C1675

C1677

C1646

C1650

C1647

C1644

C1648

C1645
C1619

C1618

C1649

C1621

C1620

C1623

C1576

C1622

C1579

C1574

C1580

C2121
C1583

C1584

R776

R764

L94

C1548

C1714
C2126

R777

L101

C1624

R758

R782

C1577

C1582

R1028

C2153

C2179
R780

C1718
C2123

C2168
R766

R747

C1483

C1743

C1753

R821

R822

R823

R824

C1754

R1054

C1746
R789

R767

C1625

R717

C2180

C2154

R818

R820

C1696

R861

C1757

C1759

C1760

C1747

R768

C1801
C1786
C1780

C1781

R1045

R830

R827

R828

R826

R802

L96

C2185

R778

C1778

C1779

C1787
R831

R832

R1052

C1758

R1044

R833

C1782

C1783

R1051

C1748

C2187

C1794

C1795

C1796

R862

R863

R1043
C1790

R834

C1784

R825

C1749

C1793

C1788

R837
C1789

R844

C1785

R1058

R864

R835

C1755

C1756

C1445

R1055

R840

R842

R846
R836

R838
R839

U78

R847

R848

R841

R829

U79

C1761

R865

R849

R843

C1797

R851

R845

C1484

C1806

R878

R1042

R850

C1803

R870

R873

R869

R868

R874

R876

R875

R871

R872

C1798

C1805

C1799

C1800

C1808

C1807

R879
R867

R866

R877
R852

Setup:

ATCA-9305 Circuit Board

CR1

CR4

CR2

CR3

Figure 2-4: LED, Fuse and Switch Locations, Top
CR1 - P2_LED_GPIO12-R
CR2 - P2_LED_GPIO13-R
CR3 - P2_LED_GPIO14-R
CR4 - P2_LED_GPIO15-R

J1
F1

F1 - .75 Amp Fuse
(self resetting)

F2 - .75 Amp Fuse
(self resetting)

MPC8548
CR13 - PQ_GREENLED_R*
CR14 - PQ_CKSTP_OUT_R*
CR16 - PQ_REDLED_R*
Debug
CR18 - DEBUG_LED1_R*
CR19 - DEBUG_LED2_R*
CR21 - DEBUG_LED3_R*
CR22 - DEBUG_LED43_R*
Boot Device
CR31 - FL0_LED_R*
CR32 - FL1_LED_R*
CR33 - SKT_LED_R*

CR13

CR15

Ethernet
CR15 - TSEC2_ACTIVITY

CR14
CR16

J9

CR18
CR19
CR21

CR32

SW1

CR23 - MIP1_LED1_R
CR24 - MIP1_LED2_R
CR25 - MIP1_LED3_R
CR26 - MIP1_LED4_R

SW1 - IPMC Reset

CR44

IPMP State
CR35 - STATE_LED8
CR36 - STATE_LED7
CR37 - STATE_LED6
CR38 - STATE_LED5
CR39 - STATE_LED4
CR40 - STATE_LED3
CR41 - STATE_LED2
CR42 - STATE_LED1
CR43 - STATE_LED0

CR48

CR41

CR42

CR43

CR37

CR36

CR40

CR35

CR38

F3 - .75 Amp Fuse
(self resetting)

CR47

Ethernet
CR44 - BC1_LINKSPD1/2
CR45 - BC1_LINKSPD1/2
CR46 - BC1_ACT*
CR47 - BC2_LINKSPD1/2
CR48 - BC2_LINKSPD1/2
CR49 - BC2_ACT*
CR49

JP1

F3

CR39

CR25

CR31

CR26

CR24

CR23

CR22

CR33

CR45

P2

CR46

F2

+

+

F4
F4 - 1 Amp Fuse
F5 - 1 Amp Fuse
F6 - 10 Amp Fuse
F7 - 8 Amp Fuse
F8 - 10 Amp Fuse
F9 - 8 Amp Fuse
+

CR51

CR50

CR52

F6
F7
F8
F9

CR53

F10

+

J15

CR50 - P1_LED_GPIO12_R1
CR51 - P1_LED_GPIO13_R1
CR52 - P1_LED_GPIO14_R1
CR53 - P1_LED_GPIO15_R1

F5

F10 - .75 Amp Fuse
(self resetting)

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Setup:

ATCA-9305 Circuit Board

Figure 2-5: LED and Switch Locations, Bottom

CR57

J16

Hot Swap
CR57 - BLUE_LED_CONN_K
SW2 - Front Panel Reset

CR54

CR55

CR56

SW2

2-6

Front Panel
CR54 - Red = LED1R_CONN
Amber = LED1A_CONN
CR55 - LED2_CONN
CR56 - LED3_CONN

ATCA-9305 User’s Manual

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Setup:

ATCA-9305 Circuit Board

Connectors
The ATCA-9305 circuit board has various connectors and headers (see the figures beginning
on page 2-3), summarized as follows:
J1: This 14-pin JTAG header is used for debugging CN5860 processor 2. See Table 3-7.
J3-J6: These 240-pin sockets are installed for the CN5860 processor 1 DDR2 SDRAM memory.
J9: This 14-pin configuration header allows selection of boot device, and MPC8548 configuration for the configuration SROM. See Fig. 2-6.
J11-J14: These 240-pin sockets are installed for the CN5860 processor 2 DDR2 SDRAM memory.
J15: This 14-pin JTAG header is used for debugging CN5860 processor 1. See Table 3-7.
J23: The 80-pin Zone 2 connector provides 1 GB and 10 GB Ethernet access to the backplane, see
Table 8-2.
J30-J31: The 80-pin Zone 3 connectors route PCIe and XAUI (10G) to the optional RTM. See Table 8-3
and Table 8-4 for pin assignments.
J33: The 24-pin Zone 3 connector routes the reset, Hot Swap, MPC8548 console, power, and
IPMC I2C to the optional RTM, see Table 8-5.
JP1: This is the 10-pin programming header for the IPMP, CPLD, and SPI 10G (1-4) devices, see
Table 7-51.
P1: This 14-pin RJ45 connector with LEDs routes the Three-speed Ethernet Controller (TSEC1)
between the MPC8548 and the front panel. See Table 6-4 for pin assignments.
P2: This 16-pin JTAG debug header accesses the MPC8548 processor, see Table 4-7.
P3: This 14-pin RJ45 connector with LEDs routes Ethernet (FP1) between the switch and the
front panel, see Table 6-4 for pin assignments.
P4: The 5-pin vertical mini-B USB provides the IPMP EIA-232 console debug, see Table 7-52.
P5, P6: These 5-pin vertical mini-B USBs are the CN5860 console and for factory debug use only.
P7: This 5-pin mini-B USB is the console serial port for the MPC8548 management processor,
see Table 4-8.
P10: The 30-pin Zone 1 connector routes IPMB to the backplane, see Table 8-1.

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Setup:

ATCA-9305 Setup

Configuration Header
There are a total of seven jumper pairs on J9 (pins 11-14 are spare posts). See figure Fig. 2-2
for the jumper location on the ATCA-9305. Also reference the “Jumper Settings (0x18)” register.
Figure 2-6: Configuration Header, J9
13 11 9 7 5 3 1

BT FLASH
PROG
STAND
BOOT
REDIR EN
IG ROM
BT SKT

14 12 10 8 6 4 2

BT SKT: A shunt on pins 1-2 selects the 512 KB socketed ROM as the boot device for the MPC8548.
IG SROM: If the serial ROM configuration jumper is installed (pins 3-4), the ATCA-9305 will not try to
configure (IGNORE_SROM*) from the MPC8548 serial ROM.
REDIR EN: A shunt installed on pins 5-6 disables the boot redirection, see page 7-41 for more information.
BOOT: A shunt on pins 7-8 causes both Cavium CN5860s to boot from their local bus and not boot
over PCI.
STAND: A shunt on pins 9-10, IPMC stand alone mode, allows the board to boot without management control.
PROG: Installing a shunt on pins 11-12 puts the IPMC controller into programming mode. This is
only used in the factory to configure the IPMC.
BT FLASH: If BOOT shunt is installed (booting from local bus), this shunt determines whether the boot
is from local flash or socket. When this BT FLASH shunt is installed, the ATCA-9305 boots
from flash. Otherwise, it boots from the socket.

ATCA-9305 SETUP
You need the following items to set up and check the operation of the Emerson ATCA-9305:
ATCA chassis and power supply
MPC8548 Console cable for EIA-232 port, Emerson part # C0007662-00
Computer terminal
Save the antistatic bag and box for future shipping or storage.

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ATCA-9305 User’s Manual

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Setup:

ATCA-9305 Setup

Power Requirements
The ATCA-9305 circuit board uses —48 volts from the backplane to derive 3.3 volts for the
IPMC and 12 volts for payload power.
Table 2-2: Typical Power Requirements

Configuration:

Power:

1.0 GHz MPC8548 and 800 MHz Cavium processors,
board running at room temperature with all
processors at U-Boot prompt

135 watts

The exact power requirements for the ATCA-9305 circuit board depend upon the specific
configuration of the board, including the CPU frequency and amount of memory installed
on the board. Please contact Emerson Technical Support at 1-800-327-1251 if you have
specific questions regarding the board’s power requirements.

Environmental Considerations
As with any printed circuit board, be sure that air flow to the board is adequate. Chassis constraints and other factors greatly affect the air flow rate. The environmental requirements
are as follows:
Table 2-3: Environmental Requirements

Environment:

Range:

Relative Humidity:

Operating Temperature

0° to +55° Centigrade, ambient
(at board)

Not to exceed 85% (noncondensing)

Storage Temperature

—40° to 85° Centigrade

Not to exceed 95%
(non-condensing)

Altitude

0 to 4,000 meters above sea
level

—

Air Flow

Requires 30 CFM at 55° Centigrade at sea level. Meets thermal
performance requirements of CP-TA ATCA ICD Book 1.1Class B-2

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Setup:

ATCA-9305 Setup

Figure 2-7: Air Flow Graph

Hot Swap
The ATCA-9305 can be Hot Swapped, as defined in the AdvancedTCA specification (see reference in Table 1-2). This section describes how to insert and extract an ATCA-9305 module
in a typical AdvancedTCA system. (These procedures assume the system is using a shelf
manager.)
Note: The ATCA-9305 Rear Transistion Module (RTM) has its own Hot Swap LED and switch, and it can be Hot
Swapped in/out independently of the front board. If the front board is not present, then the RTM will not be
powered. If the front board is Hot Swapped out, the RTM’s blue LED will illuminate. In either case, the RTM can
be safely removed.

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Setup:

Troubleshooting

Insert a board:
1 Insert the ATCA-9305 into an available slot.
2 Push in the front panel handle (tab).
The blue Hot Swap LED on the front panel (see Fig. 2-1) flashes a long blink to indicate that
board insertion is in progress and system management software is activating the slot. Then
the blue LED turns off, indicating the insertion process is complete, and payload power is
present.
Remove a board:
1 Pull out the handle (tab) on the ATCA-9305 front panel one click.
A short blink indicates the board is requesting permission for extraction.
2 Remove the board when the blue LED on the front panel is on (no payload power).
Caution: Do not remove the ATCA-9305 while the blue LED is blinking.
!

TROUBLESHOOTING
In case of difficulty, use the following checklist:
Be sure the ATCA-9305 circuit board is seated firmly in the carrier.
Be sure the system is not overheating.
Check the cables and connectors to be certain they are secure.
Check that your terminal is connected to a console port.

Technical Support
If you need help resolving a problem with your ATCA-9305, visit
http://www.emersonembeddedcomputing.com/ on the internet or send E-mail to support@artesyncp.com. Please have the following information handy:
• ATCA-9305 serial number and product identification (see Fig. 2-8)
• MPC8548 monitor version number (see Fig. 9-1)
• Cavium monitor version number (see Fig. 3-3)
• version and part number of the operating system (if applicable)

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Setup:

Troubleshooting

• whether your board has been customized for options such as a higher processor speed or
additional memory
• license agreements (if applicable)
If you do not have internet access, please call Emerson for further assistance:
(800) 327-1251 or (608) 826-8006 (US)
44-131-475-7070 (UK)
Figure 2-8: Serial Number and Product ID on Top Side

Serial Number

Product ID

Product Repair
If you plan to return the board to Emerson Network Power for service, visit
http://www.emersonembeddedcomputing.com/ on the internet or send E-mail to serviceinfo@artesyncp.com to obtain a Return Merchandise Authorization (RMA) number. We
will ask you to list which items you are returning and the board serial number, plus your purchase order number and billing information if your ATCA-9305 hardware is out of warranty.
Contact our Test and Repair Services Department for any warranty questions. If you return
the board, be sure to enclose it in an antistatic bag, such as the one in which it was originally
shipped. Send it prepaid to:
Emerson Network Power, Embedded Computing
Test and Repair Services Department
8310 Excelsior Drive
Madison, WI 53717
RMA #____________

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ATCA-9305 User’s Manual

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Setup:

Troubleshooting

Please put the RMA number on the outside of the package so we can handle your problem
efficiently. Our service department cannot accept material received without an RMA number.

Comments and Suggestions
We welcome and appreciate your comments on our documentation. We want to know
what you think about our manuals and how we can make them better.
Mail comments to us by filling out the following online form:
http://www.emersonnetworkpowerembeddedcomputing.com/ Contact Us > Online Form
In “Area of Interest” select “Technical Documentation”. Be sure to include the title, part
number, and revision of the manual and tell us how you used it.

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(blank page)

2-14

ATCA-9305 User’s Manual

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Section 3

Cavium Processor Complex

The ATCA-9305 provides two Cavium processor complexes. The major devices on each
complex consist of the Cavium CN5860 processor, two StratixGX bridges, SDRAM,
RLDRAM®, an I2C EEPROM, socketed ROM, Flash, and the PCI bus interface.
Figure 3-1: Cavium Processor Complex Block Diagram

Console

Console

(ENG use only)

P1 DDR
SDRAM

I2C
I2C
EEPROM
RLDRAM
64MB

(ENG use only)

COP/
JTAG

COP/
JTAG

D1_DDR2 Serial 0 PCI
Bus
I2C
IDSEL11

PCI Bus
Serial CFG
EEPROM

SPI-0

Cavium
Octeon
CN5860
Processor 1 SPI-1
Local Bus
Addr/Data

RLDRAM
64MB
RLDRAM
64MB
RLDRAM
64MB

Serial 1

PCI Serial 0 D1_DDR2
Bus
I2C
IDSEL12

PCI Bus
IDSEL13

Stratix II GX
#1

6 XAUI

Stratix II GX
#2

5 XAUI

XAUI 13

Stratix II GX
#3

XAUI 14

Stratix II GX
#4

BCM56802
XAUI 10 Gb
Switch

Socketed
ROM
512K x8

Socketed
ROM
512K x8

NOR
Flash
4M x8

NOR
Flash
4M x8

Cavium Processor Complex 1

P2 DDR2
SDRAM

I2C
I2C
EEPROM

SPI-0

Cavium
Octeon
CN5860
SPI-1 Processor 2

RLDRAM
64MB

Local Bus
Addr/Data

RLDRAM
64MB
RLDRAM
64MB

Serial 1

RLDRAM
64MB

Cavium Processor Complex 2

CAVIUM CN5860 PROCESSOR
The main features of the CN5860 include:
Table 3-1: CN5860 Features

Feature:

Description:

Processor Core

Up to 16 cnMIPS™ cores

Core Speed
Network Services Processor (NSP)

up to 800 MHz, processing up to 30 million packets per second

System Packet Interface

Two SPI-4.2 ports

L2 Cache

2 MB, eight-way set associative

DRAM

144-bit DDR2 DRAM interface

RLDRAM

18-bit RLDRAM, low-latency memory direct access

PCI

64-bit, PCI 2.3 compatible

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Cavium Processor Complex:

PCI

The CN5860 and switch route packets using SPI-4.2 and control information flow using PCI.
The CN5860 has two SPI-4.2 interfaces with each one supporting up to 16 ports. Two highspeed SPI-4.2 Altera (Stratix™ GX) FPGAs function as the SPI-to-XAUI bridge for each processor to switch complex. The PCI interface supports up to four ports, consequently a total
of 36 ports can be supported internally by each CN5860.

Cavium Memory Map
Although the Cavium processors are 64-bit, the ATCA-9305 uses a 49-bit implementation.
Refer to the Cavium Networks OCTEON Plus CN58xx Hardware Reference Manual for more
detailed information on the memory map.
Table 3-2: Cavium Address Summary

Hex Physical
Address:

Register Description:

1,2000,0000,0000

reserved

1,1F00,0000,0000

Cavium Hardware registers

1,1E00,0000,0000

PCI Memory Space (6)

1,1D00,0000,0000

PCI Memory Space (5)

1,1C00,0000,0000

PCI Memory Space (4)

1,1B00,0000,0000

PCI Memory Space (3)

1,1A00,0000,0000

PCI I/O Space

1,1910,0000,0000

reserved

1,1900,0000,0000

PCI Special Space

1,0700,0000,0000

CN58xx Registers

1,0001,0000,0000

reserved

1,0000,0000,0000

Local Boot Bus

0,0004,1000,0000

DDR2 SDRAM, middle block (256-512 MB)

0,0004,0000,0000

reserved

0,0000,2000,0000

DDR2 SDRAM, upper block (512 MB-2 GB)1

0,0000,1000,0000

reserved

0,0000,0000,0000

DDR2 SDRAM, bottom block (256 MB)

1. This depends on how much memory is installed.

PCI
The Cavium is a slave device on the PCI bus. The Cavium U-boot monitor image is provided
by the MPC8548 management processor via PCI. The MPC8548 monitors the Cavium boot
status and has the ability to try alternate boot images if the current one fails.

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Cavium Processor Complex:

PCI

The CN5860 processor is designed such that another PCI device can initialize its memory
interface, copy code over PCI into its local memory space, and then write a boot release register.

CN5860 Boot Over PCI
The PCI bus is configured to run at 66 MHz in 64-bit conventional PCI mode. On power-up,
the CN5860 processor’s 16 internal cores are held in reset. The MPC8548 management processor performs the following steps:
1 Initialize the CN5860 RAM.
2 Copy the CN5860 U-boot to the CN5860 RAM.
3 Copy boot code to the reset vector to jump to the U-boot code in RAM.
4 Release the CN5860 processor cores from reset.
5 Receive return codes from the CN5860 that indicate any boot or POST errors and take the
appropriate action.
The management processor (MPC8548) monitor implements a utility to load non-volatile
memory redundant U-boot images for the CN5860 processors. The utility tags each copy as
primary or secondary.

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Cavium Processor Complex:

PCI

Cavium Reset
Each CN5860 can be reset independently of the other processor without affecting its operation. This task is performed by the MPC8548 management processor.
Figure 3-2: CN5860 Reset Diagram
33MHz
L_PAYLD_EN
3_3V_PWRGD
2_5V_PWRGD
1_8V_PWRGD
1_2V_PWRGD
1_0V_PWRGD
PQ_CORE_PWRGD
P1_CORE_PWRGD
P2_CORE_PWRGD

3_3V_MP

P1_RESET*
P1_PCI_RST*
P1_PWRGD

IPMP
CPLD

P2_RESET*
P2_PCI_RST*

PWRGD_OK

P2_PWRGD

3_3V_MP
3_3V_MP

Hot Swap
Switch

IPMC_PO_RST*

3_3V_MP

Voltage
Monitor
Delay

IPMC_PO_RST*

Voltage
Monitor
Delay

CN5860
Cavium
Processor 2

3_3V
P1_DDR_RST*
POR_RST*

KSL
CPLD

P1 DDR
SDRAM

P2_DDR_RST*

P2 DDR
SDRAM
I2C IO
Port

L_PAYLOAD_RST*

MIP1_RST*

PRIV_I2C_SCL
PRIV_I2C_SDA

MC Reset

Front
Panel
Reset

CN5860
Cavium
Processor 1

MIP2_RST*

E_HANDLE

MIP3_RST*

IPMC
48A_OK

Stratix II GX
XAUI #1

Stratix II GX
XAUI #2
Stratix II GX
XAUI #3

48B_OK
MIP4_RST*

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Stratix II GX
XAUI #4

Cavium Processor Complex:

Cavium Ethernet

CAVIUM ETHERNET
The Ethernet address for your board is a unique identifier on a network. The address consists of 48 bits (MAC [47:0]) divided into two equal parts. The upper 24 bits define a unique
identifier that has been assigned to Emerson Network Power, Embedded Computing by
IEEE. The lower 24 bits are defined by Emerson for identification of each of our products.
The Ethernet address for the ATCA-9305 is a binary number referenced as 12 hexadecimal
digits separated into pairs, with each pair representing eight bits. The address assigned to
the ATCA-9305 has the following form:
00 80 F9 xx yy zz
00 80 F9 is Emerson’s identifier. The last three bytes of the Ethernet address consist of the
port (one byte); 0x99(SPI 1), 0x9A (SPI 2), 0x9B (SPI 3), or 0x9C (SPI 4), followed by the serial
number (two byte hexadecimal). The ATCA-9305 Cavium has been assigned the Ethernet
address range 00:80:F9:99:00:00 to 00:80:F9:9C:FF:FF. The format is shown in Table 3-3.
Table 3-3: Ethernet Port Address

Offset:

MAC:

Description:

Ethernet Identifier (hex):

Byte 5

15:0

LSB of (serial number in hex)

—

MSB of (serial number in hex)

—

Byte 3

23:16

SPI 1
SPI 2
SPI 3
SPI 4

0x99
0x9A
0x9B
0x9C

Byte 2

47:24

Assigned to Emerson by IEEE

0xF9

Byte 4

Byte 1

0x80

Byte 0

0x00

The last two bytes, MAC[15:0], are calculated from the serial number stored in the Cavium
EEPROM. This corresponds to the following formula: n —1000, where n is the unique serial
number assigned to each board. So if an ATCA-9305 serial number is 1032, the calculated
value is 32 (2016), and the default Ethernet port addresses are:
• Cavium 1 SPI 1 MAC address is: 0x00 0x80 0xF9 0x99 0x00 0x20
• Cavium 1 SPI 2 MAC address is: 0x00 0x80 0xF9 0x9A 0x00 0x20
• Cavium 2 SPI 1 MAC address is: 0x00 0x80 0xF9 0x9B 0x00 0x20
• Cavium 2 SPI 2 MAC address is: 0x00 0x80 0xF9 0x9C 0x00 0x20

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Cavium Processor Complex:

Cavium Monitor

CAVIUM MONITOR
The primary function of the monitor software is to transfer control of the hardware to the
user’s application. Secondary responsibilities include:
• low-level initialization of the hardware
• diagnostic tests
• low-level monitor commands/functions to aid in debug

Start-up Display
At power-up or after a reset, the Cavium monitor runs diagnostics and reports the results in
the start-up display, see an example in Fig. 3-3. During the power-up sequence, the monitor
configures the board according to the environment variables (see “MPC8548 Environment
Variables” on page 9-26). If the configuration indicates that autoboot is enabled, the monitor attempts to load the application from the specified device. If the monitor is not configured for autoboot or a failure occurs during power-up, the monitor enters normal
command-line mode. The monitor command prompt in Fig. 3-3 is the result of a successful
hardware boot of the ATCA-9305.
Figure 3-3: Example Cavium CN5860 Monitor Start-up Display
U-Boot 1.1.1 (Jan 16 2009 - 14:26:14)0.9
Hardware initialization

Monitor command prompt

OCTEON CN58XX-NSP revision: 1
Core clock: 750 MHz
DDR clock: 266 MHz (533 Mhz data rate)
DRAM: 4096 MB
Flash: 4 MB
Clearing DRAM........ done
PCI console init succeeded, 1 consoles, 1024 bytes each
Net:
octspi0, octspi1
RLDRAM not present
Octeon BIST Passed
POST i2c PASSED
POST memory PASSED
2 ATCA-9305 (Mon 0.9)=>

Note: There will be either a 1 or 2 in front of the monitor prompt indicating which Cavium processor is prompting.

Power-up/Reset Sequence
The Cavium CN5860 processor follows the boot sequence in Fig. 3-4 before auto-booting
the operating system or application software. At power-up or board reset, the monitor performs hardware initialization, diagnostic routines, autoboot procedures, and if necessary,
invokes the command line. See Table 3-5 for default Cavium environment variables settings.

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Cavium Processor Complex:

Cavium Monitor

Figure 3-4: Power-up/Reset CN5860 Boot Sequence Flowchart
Power-up or Reset

Cavium Hardware
Wait for PCI load of U-boot

U-Boot Monitor
Default Board Initialization

U-Boot Monitor
Execute POST

U-Boot Monitor
Start Autoboot Sequence
(Boot Operating System)

Operating System Boot
Boot OS image
according to
configuration parameters

Diagnostic Tests During Power-up and Reset
The Cavium monitor diagnostic tests can be executed during power-up or invoked from the
monitor’s command prompt. This is accomplished by changing the state of the monitor
configuration parameters that define power-up and reset diagnostics mode. If the powerondiags parameter is set to “on”, the monitor invokes the diagnostic tests after a reset of the
hardware. Results are displayed to the console including whether the test passed or failed.
POST Diagnostic Results
The ATCA-9305 Power-On Self-Test (POST) diagnostic results are stored as a 32-bit value in
memory accessible by the management console at location 0x80080A6C. Each bit indicates
the result of a specific test, so this field can store the results of up to 32 diagnostic tests.
Table 3-4 assigns the bits to specific tests.

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Cavium Processor Complex:

Cavium Monitor

Table 3-4: POST Diagnostic Results–Bit Assignments

Bit:

Diagnostic
Test:

0-1

Reserved

2

DRAM

Verify address and data lines are intact

3

Cavium BIST

-

0

Passed the test

4

I2C

Verify all local I2C devices are connected
to the I2C bus

1

Failure detected

5-31

Reserved

Description:

Value:

Cavium Environment Variables
The following table lists the standard Cavium environment variables:
Table 3-5: Standard Cavium Environment Variables

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ATCA-9305 User’s Manual

Variable:

Default
Value:

baudrate

115200

Console port baud rate
Valid rates: 9600, 14400, 19200, 38400, 57600, 115200

bootcmd

""

Command to execute when auto-booting or executing
the ‘bootd’ command

bootdelay

0

Choose the number of seconds the Monitor counts down
before booting user application code
Valid options: time in seconds, -1 to disable autoboot

bootfile

""

Path to boot file on server (used with TFTP)—set this to
“path/file.bin” to specify filename and location of the file
to load.

ethaddr

undefined

SPI 1 MAC address

eth1addr

undefined

SPI 2 MAC address

ethact

octspi0

Specifies Ethernet port to use

gatewayip

0.0.0.0

Select the network gateway machine IP address

hostname

none

Target hostname

ipaddr

0.0.0.0

Board IP address

loadaddr

0x20000000

Define the address to download user application code
(used with TFTP)

netmask

0.0.0.0

Board sub-network mask

powerondiags

off

Turns POST diagnostics on or off after power-on/reset
Valid options: on, off

rootpath

eng/

Path name of the NFS’ server root file system

serial#

xxxxx

Board serial number

serverip

0.0.0.0

Boot server IP address

stderr

serial

Sets the standard destination for console error reporting
Valid options: serial, pci

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Description:

Cavium Processor Complex:

Memory

Variable:

Default
Value:

stdin

serial

Sets the standard source for console input
Valid options: serial, pci

stdout

serial

Sets the standard destination for console output
Valid options: serial, pci

Description: (continued)

MEMORY
The processor complex supports DDR2 Synchronous DRAM (SDRAM) and Reduced Latency
DRAM (RLDRAM) memory devices.

DDR2 SDRAM
The ATCA-9305 supports up to 16 gigabytes of 144-bit wide DDR2 SDRAM per processor
complex. The SDRAM interface clock speed frequency is 400 MHz. The four low-profile,
dual-inline memory modules (buffered DIMM) are installed in 240-pin very low profile (VLP)
sockets to reduce board density and routing constraints. A 2 KB EEPROM on the DIMM provides the serial presence detection (SPD). On-card SDRAM occupies physical addresses
from 0,0000,0000,000016 to 0,0003,FFFF,FFFF16.
Each processor memory bus is operating in 144-bit mode. Error-correcting Code (ECC) is
performed on the memory bus so that the CN5860 detects all double-bit errors, multi-bit
errors within a nibble, and corrects all single-bit errors.

RLDRAM
Each CN5860 supports 256 MB Common I/O (CIO) RLDRAM operating up to 400 MHz
(depends on the processor speed). The Micron RLDRAM II is organized as 32Mx18x8 internal
banks. The DDR I/O interface transfers two data words per clock cycle. Output data is referenced to the free-running output data clock. Read and write accesses to the RLDRAM are
burst-oriented. RLDRAM is accessed by using Cavium-specific instructions which operate on
MIPS Coprocessor 2.

I2C EEPROM
Each Cavium processor complex has one user EEPROM device for parameter storage located
on the I2C bus, address 0xA8. The I2C bus for each processor is completely independent
from the other CN5860 processor and MPC8548 processor I2C buses. The Atmel two-wire
serial EEPROM on each CN5860 processor I2C interface consists of the Serial Clock (SCL)
input and the Serial Data (SDA) bidirectional lines.

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Cavium Processor Complex:

StratixGX Interconnect

Table 3-6: Cavium NVRAM Memory Map

Address Offset
(hex):

Description:

Window
Size (bytes)

0x1E00-0x1FFF

Monitor parameters

256

0x0000-0x1D36

User defined

79F

Flash, 512 KB x 8
The 512 KB of 32-pin PLCC socketed flash starts at physical address1D46,000016 and is used
for Engineering code. The StrataFlash features high-performance fast asynchronous access
times, low power, and flexible security options.

Flash, 4 MB x 16
The 4 MB soldered NOR flash starts at physical address 1D05,000016. The 32-Mbit device
provides CN5860 code storage and non-volatile memory.

STRATIXGX INTERCONNECT
The Altera StratixGX FPGA provides the high-speed SPI-4.2 interconnect. Each complex has
dual SPI-to-XAUI bridges connected to the XAUI Ethernet switch ports.

PLD Registers
The FPGA bridge is located at address 0x1D030000. Use the following registers to access
the XAUI to SPI bridge configuration registers. See the “Read Example” and “Write Example.”
Data Registers
Register 3-1: Data 31:24 (0x0)

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ATCA-9305 User’s Manual

Bits:

R/W:

Function:

7

R/W

Data 31

6

R/W

Data 30

5

R/W

Data 29

4

R/W

Data 28

3

R/W

Data 27

2

R/W

Data 26

1

R/W

Data 25

0

R/W

Data 24

10009109-01

Cavium Processor Complex:

StratixGX Interconnect

Register 3-2: Data 23:16 (0x1)

Bits:

R/W:

Function:

7

R/W

Data 23

6

R/W

Data 22

5

R/W

Data 21

4

R/W

Data 20

3

R/W

Data 19

2

R/W

Data 18

1

R/W

Data 17

0

R/W

Data 16

Register 3-3: Data 15:8 (0x2)

Bits:

R/W:

Function:

7

R/W

Data 15

6

R/W

Data 14

5

R/W

Data 13

4

R/W

Data 12

3

R/W

Data 11

2

R/W

Data 10

1

R/W

Data 9

0

R/W

Data 8

Register 3-4: Data 7:0 (0x3)

Bits:

R/W:

Function:

7

R/W

Data 7

6

R/W

Data 6

5

R/W

Data 5

4

R/W

Data 4

3

R/W

Data 3

2

R/W

Data 2

1

R/W

Data 1

0

R/W

Data 0

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3-11

Cavium Processor Complex:

StratixGX Interconnect

Address Registers
Register 3-5: Address 9:8 (0x4)

Bits:

R/W:

Function:

7

—

Reserved

6

—

5

—

4

—

3

—

2

—

1

R/W

Address 9

0

R/W

Address 8

Register 3-6: Address 7:0 (0x5)

Bits:

R/W:

Function:

7

R/W

Address 7

6

R/W

Address 6

5

R/W

Address 5

4

R/W

Address 4

3

R/W

Address 3

2

R/W

Address 2

1

R/W

Address 1

0

R/W

Address 0

Control Register
The write only Control register performs two functions:
• Writing a value of 0x01 causes the contents of the Data registers to be written to the
FPGA bridge at the location specified by the Address registers.
• Writing a value of 0x02 causes the contents of the Data registers to be overwritten by the
contents of the FPGA bridge at the location specified by the Address registers.
Note: Writing any other value to the Control register will be ignored.
Register 3-7: Control (0x6)

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ATCA-9305 User’s Manual

Bits:

R/W:

Function:

7

—

Reserved

6

—

5

—

4

—

3

—

2

—

10009109-01

Cavium Processor Complex:

Bits:

R/W:

Function:

1

W

Read

0

W

Write

StratixGX Interconnect

Version Register
This read-only register tracks the PLD versions. The version is hard coded in the PLD and
changes with every released code change. Version starts at 0116.
Register 3-8: Version (0x7)

Bits:

R/W:

Function:

7

R

0x01

6

R

5

R

4

R

3

R

2

R

1

R

0

R

Scratch Register
All registers in this range act as the same register.
Register 3-9: Scratch (0x8-0x3F)

Bits:

R/W:

7

R/W

6

R/W

5

R/W

4

R/W

3

R/W

2

R/W

1

R/W

0

R/W

Function:

Read Example: To read the FPGA bridge SPI_COMMAND register at 0x204, use the following commands.
Set address bits 9:8.
=>write64b 1d030004 02

Set address bits 7:0.
=>write64b 1d030005 04

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ATCA-9305 User’s Manual

3-13

Cavium Processor Complex:

Headers and Connectors

Perform a read.
=>write64b 1d030006 02

Display the results.
=>read64l 1d030000

Write Example: To write to the FPGA bridge MAC_CMD_CFG register at 0x00C, use the following commands.
Set data bits 31:24.
=>write64b 1d030000 a9

Set data bits 23:16.
=>write64b 1d030001 b8

Set data bits 15:8.
=>write64b 1d030002 c7

Set data bits 7:0.
=>write64b 1d030003 d6

Set address bits 9:8.
=>write64b 1d030004 00

Set address bits 7:0.
=>write64b 1d030005 0c

Perform a write.
=>write64b 1d030006 01

HEADERS AND CONNECTORS
COP/JTAG Headers
The CN5860 processor complex uses headers J1 and J15 for debug.
Table 3-7: CN5860 Processor COP/JTAG Headers

3-14

ATCA-9305 User’s Manual

Pin:

J1 (processor 2):

J15 (processor 1):

1

P2_ETRST*

P1_ETRST*

2

ground

ground

3

P2_TDI

P1_TDI

4

ground

ground

10009109-01

Cavium Processor Complex:

Headers and Connectors

Pin:

J1 (processor 2):

J15 (processor 1): (continued)

5

P2_ETDO

P1_ETDO

6

ground

ground

7

P2_TMS

P1_TMS

8

ground

ground

9

P2_TCK

P1_TCK

10

ground

ground

11

P2_EJTAG_RST

P1_EJTAG_RST

12

key (pin not installed)

key (pin not installed)

13

P2_EJTAG_DINT

P1_EJTAG_DINT

14

P2_COP_PWR (3.3V)

P1_COP_PWR (3.3V)

Console Serial Ports (optional)
Connectors P6 (processor P1) and P5 (processor P2) access the CN5860 processors for Engineering debug use only. The supported baud rates for these ports operate at 9600, 14400,
19200, 38400, 57600, and 115200 bps. (The default rate is 115200 bps.)
Table 3-8: CN5860 Processor Debug Headers

Pin:

P6:

P5:

1

no connect

no connect

2

P1_SER1_RXD

P2_SER1_RXD

3

P1_SER1_TXD

P2_SER1_TXD
no connect

4

no connect

5

signal ground

signal ground

6-7

shield

signal ground

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ATCA-9305 User’s Manual

3-15

(blank page)

3-16

ATCA-9305 User’s Manual

10009109-01

Section 4

Management Complex

The ATCA-9305 management complex is comprised of the Freescale MPC8548 processor,
CPLD, SDRAM, flash, I2C EEPROM, Real-time Clock, and PCI bus interface. Board power-up,
booting and monitoring the Cavium processors, PCI bus arbitration, interrupt servicing,
memory persistence functionality, and other board level management tasks are implemented using the MPC8548 processor. The MPC8548 stores the Cavium operating system
and monitor code in its local memory and then uses the boot over PCI functionality to bring
up the Cavium processor complexes. The CPLD registers are described in Chapter 5. See
Chapter 9 for the Management Processor Monitor.
The management complex connects to the Broadcom Ethernet switch via a 1000BASE-T
Ethernet port. This connection uses the TSEC2 interface operating in SGMII mode. See
Chapter 6, “Ethernet Interface.”
Figure 4-1: MPC8548 Management Processor Complex Block Diagram
Console

RJ45

RJ45
Socketed
ROM
512KB
x8

Management Processor Complex
PHY

PHY

KSL
CPLD
Latched Adrs

NOR
Flash
4M
x 16

A/D

NAND
Flash
1GB
x 16

Adrs/Data
COP/JTAG
MPC8548
Management
Processor

I2C
EEPROM
I2C
EEPROM

NOR
Flash
512Mb or
64MB x 16

PQ DDR2
SDRAM

PCIe x4

RTC
PHY
To Cavium
Processor 1

To Cavium
Processor 2
& Ethernet Switch

PCI Bus
3
SGMII

4
SGMII

PCI Bus
IDSEL13

BCM56802
XAUI 10 Gb
Switch

J30

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ATCA-9305 User’s Manual

4-1

Management Complex:

MPC8548 Processor

MPC8548 PROCESSOR
The MPC8548 processor has the following features:
Table 4-1: MPC8548 Features

Feature:

Description:

L1 Cache

32-kilobyte data and instruction caches with parity protection, 32byte line, eight-way set associative

L2 Cache

512 kilobytes, eight-way set associative

CPU Core Speed

1 GHz with a 400 MHz DDR2 bus

DDR2 Memory Controller

64-bit data interface, four banks of memory supported (each up to 4
GB), full ECC support

Dual I2C Controllers

Two-wire interface, master or slave I2C support

Boot Sequencer

Loads configuration data from serial ROM at reset via the I2C interface

Ethernet

Four 10/100/1000 enhanced three-speed controllers (eTSECs), full/half-duplex support, MAC address recognition

Local Bus Controller (LBC)

DDR2 SDRAM memory controller, General Purpose Chip Select
Machine (GPCM), three User-Programmable Machines (UPM), eight
chip selects support eight external slaves

PCI

64-bit, PCI 2.2 compatible

PCI Express

Single x4 PCIe high-speed interconnect, complies with PCI Express™
Base Specification Revision 1.0a

JTAG

Complies with IEEE Std. 1149.1

For more detailed information, reference the Freescale MPC8548E PowerQUICC™ III Integrated Processor Family Reference Manual.

MPC8548 Memory Map
The monitor can boot from either the soldered flash (Bank 1, default) or the socketed PLCC
device. Based on the configuration header (see page 2-8) either the socketed device or soldered flash is mapped to the boot bank at FFF8,000016, see Fig. 4-2. Information on particular portions of the memory map can be found in later sections of this manual, see Table 4-2.

4-2

ATCA-9305 User’s Manual

10009109-01

Management Complex:

MPC8548 Processor

Figure 4-2: MPC8548 Memory Map
Hex Address
Address Range
FFFF,FFFF
FFF0,0000
FFEF,FFFF
FF80,0000
FF7F,FFFF
FF70,0000
FF6F,FFFF
FC88,0000
FC87,FFFF
FC80,0000
FC7F,FFFF
FC48,0000
FC47,FFFF
FC40,0000
FC3F,FFFF
FC11,0000
FC10,FFFF
FC10,0000
FC0F,FFFF
FC00,8000
FC00,7FFF
FC00,0000
FBFF,FFFF
F800,0000
F7FF,FFFF
F600,0000
F5FF,FFFF
F400,0000
F3FF,FFFF
F080,0000
F3FF,FFFF
F3C0,0000
F3BF,FFFF
F380,0000
F0FF,FFFF
F000,0000
EFFF,FFFF
E000,0000
DFFF,FFFF
8000,0000
7FFF,FFFF
0000,0000

Boot Window (512 KB)
Reserved (7.5 MB)
MPC8548 CCSRBAR (1 MB)
Reserved (46 MB)
Socketed Flash, optional (512 KB)
Reserved (3.5 MB)
CPLD Registers (512 KB)
Reserved (2.9 MB)
LPC Interface (64 KB)
Reserved (992 KB)
NAND Flash (32 KB)
Reserved (64 MB)
Soldered Flash Bank 4 (32 MB)
Soldered Flash Bank 3 (32 MB)
Reserved (56 MB)

Serial IRQ Interrupt 2
FC40,00DC
Serial IRQ Interrupt 1
FC40,00D8
LPC Data
FC40,00D4
LPC Bus Control
FC40,00D0
IPMP/IPMC GPIO Control
FC40,008C
Cavium GPIO Data Input
FC40,0088
Cavium GPIO Data Output
FC40,0084
Cavium GPIO Control
FC40,0080
Altera JTAG Software Control
FC40,0078
Cavium 2 Clock Divisor Control
FC40,0074
Cavium 1 Clock Divisor Control
FC40,0070
RTM Control
FC40,0068
RTM GPIO Control
FC40,0064
RTM GPIO State
FC40,0060
Miscellaneous Control
FC40,0054
Boot Device Redirection
FC40,0050
Scratch #1
FC40,0040
Reset Command Sticky #2
FC40,003C
Reset Command Sticky #1
FC40,0038
Reset Command #5
FC40,0034
Reset Command #4
FC40,0030
Reset Command #3
FC40,002C
Reset Command #2
FC40,0028
Reset Command #1
FC40,0024
Reset Event
FC40,0020
LED
FC40,001C
Jumper Setting
FC40,0018
reserved
FC40,0014
Hardware Configuration 0
FC40,0010
PLL Configuration
FC40,000C
PLD Version
FC40,0008
Hardware Version
FC40,0004
Product ID
FC40,0000

Soldered Flash Bank 2 (4 MB)
Soldered Flash Bank 1 (4 MB)
PCI Express I/O (16 MB)
PCI Express (256 MB)
PCI (1.5 GB)
SDRAM DDR2 (2 GB)

Table 4-2: MPC8548 Address Summary

Hex Physical
Address:

Access
Mode:

Register Description:

See
Page:
—

FFF8,0000

R/W

Boot window (512 KB)

FF80.0000

—

reserved (7.5 MB)

FF70,0000

R/W

MPC8548 CCSRBAR (1MB)

FC88,0000

—

reserved (46 MB)

10009109-01

—

ATCA-9305 User’s Manual

4-3

Management Complex:

Hex Physical
Address:

Access
Mode:

ATCA-9305 User’s Manual

Register Description: (continued)

See
Page:
4-7

FC80,0000

R/W

Socketed flash, optional (512 KB)

FC48,0000

—

reserved (3.5 MB)

FC40,00DC0

R/W

Serial IRQ Interrupt 2

5-15

FC40,00D8

R/W

Serial IRQ Interrupt 1

5-15

FC40,00D4

R/W

LPC Data

5-15

FC40,00D0

R/W

Low Pin Count (LPC) Bus Control

5-14

FC40,008C

R/W

IPMP/IPMC GPIO Control

5-14

FC40,0088

R/W

Cavium GPIO Data Input

5-13

FC40,0084

R/W

Cavium GPIO Data Output

5-13

FC40,0080

R/W

Cavium GPIO Control

5-12

FC40,0078

R/W

Altera JTAG Chain Software Control

5-12

FC40,0074

R/W

Cavium 2 C_MUL Clock Divisor Control

5-11
5-11

FC40,0070

R/W

Cavium 1 C_MUL Clock Divisor Control

FC40,0068

R/W

RTM Control

5-10

FC40,0064

R/W

RTM GPIO Control

5-10

FC40,0060

R/W

RTM GPIO State

5-10

FC40,0054

R/W

Miscellaneous Control (SIO, I2C, Test Clock)

5-9

FC40,0050

R/W

Boot Device Redirection

5-8

FC40,0040

R/W

Scratch #1

—

FC40,003C

R/W

Reset Command Sticky #2

5-8

FC40,0038

R/W

Reset Command Sticky #1

5-7

FC40,0034

W

Reset Command #5

5-7

FC40,0030

W

Reset Command #4

5-7

FC40,002C

W

Reset Command #3

5-6

FC40,0028

W

Reset Command #2

5-6

FC40,0024

W

Reset Command #1

5-5

FC40,0020

R/W

Reset Event

5-5

FC40,001C

R/W

LED

5-4

FC40,0018

R/W

Jumper Setting

5-4

FC40,0014

—

reserved

—

FC40,0010

R/W

Hardware Configuration 0

5-3

FC40,000C

R/W

PLL Configuration

5-3

FC40,0008

R/W

PLD Version

5-3

FC40,0004

R/W

Hardware Version

5-2

FC40,0000

R/W

Product ID (CPLD 512 KB)

5-2

FC11,0000

4-4

MPC8548 Processor

reserved (2.9 MB)

FC10,0000

R/W

LPC Interface (64 KB)

FC00,8000

—

reserved (992 KB)

FC00,0000

R/W

NAND flash (32 KB)

10009109-01

4-5
4-8

Management Complex:

MPC8548 Processor

Hex Physical
Address:

Access
Mode:

Register Description: (continued)

See
Page:

F800,0000

—

reserved (64 MB)

F600,0000

R/W

Soldered flash bank 4 (32 MB)

4-7

F400,0000

R/W

Soldered flash bank 3 (32 MB)

4-7

F080,0000

—

reserved (56 MB)

F3C0,0000

R/W

Soldered flash bank 2 (4 MB)

F380,0000

R/W

Soldered flash bank 1 (4 MB)

4-7

F000,0000

R/W

PCI Express I/O space (16 MB)

4-8

4-7

E000,0000

R/W

PCI Express (256 MB)

4-8

8000,0000

R/W

PCI (1.5 GB)

4-8

0000,0000

R/W

SDRAM DDR2 (2 GB)

4-7

Chip Selects
The MPC8548 memory controller functions as a chip select (CS) generator to access onboard memory devices. In order to select one device over another, the following chip
selects have been established.
Table 4-3: Device Chip Selects

Pin:

Signal:

0

Boot bank 1

1

Soldered flash boot bank 1 (default)

2

Soldered flash boot bank 2

3

Socketed flash (optional)

4

KSL CPLD registers

5

NAND flash

6

Soldered NOR flash boot banks 3 and 4

7

LPC interface
1. Boot bank can be either socketed flash, flash 1, or flash 2;
depending on the jumper setting (see Fig. 2-6).

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ATCA-9305 User’s Manual

4-5

Management Complex:

MPC8548 Processor

Reset Diagram
Figure 4-3: MPC8548 Reset Diagram
33MHz
L_PAYLD_EN
3_3V_PWRGD
2_5V_PWRGD
1_8V_PWRGD
1_2V_PWRGD
1_0V_PWRGD
PQ_CORE_PWRGD*
P1_CORE_PWRGD*
P2_CORE_PWRGD*

3_3V_MP
PQ_HRESET*
PQ_SRESET*
PQ_TRST*

IPMP
CPLD

RESET_INDICATION*

Reset to IPMC

I2C1
I2C2

PWRGD_OK

3_3V_MP

Front
Panel
Reset

3_3V_MP
IPMC Reset

Voltage
Monitor
Delay

PRIV_I2C_SDA

IPMC_PO_RST*

NOR
Flash
4M
x 16

NAND_RST*

NAND
Flash
1GB
x 16

BOOT_REDIR
BOOT_SEL0
BOOT_SEL1

NAND_WARM_RST*

PQ_DDR_RST*

PQ DDR2
SODIMM
Module

TSEC1_RST*

Ethernet Port
BCM5461S

TSEC2_RST*

Ethernet Port
BCM5461S

FP1_RST*

Ethernet Port
BCM5461S

BC_RST*

Ethernet Port
BCM5482

L_PAYLOAD_RST*
PRIV_I2C_SCL

Hot Swap
Switch

POR_RST*

KSL
CPLD

I2C IO
Port
3_3V_MP

FLASH_RST*

3_3V

IPMC_PO_RST*

Voltage
Monitor
Delay

MPC8548
Management
Processor

E_HANDLE

IPMC
48A_OK
48B_OK

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ATCA-9305 User’s Manual

10009109-01

Management Complex:

Memory

MEMORY
The memory devices in the management complex consist of:
• 1 GB DDR2 SDRAM
• 512 KB socketed flash
• 8 MB soldered NOR flash (two redundant banks of 4 MB each)
• 1 GB soldered NAND flash
• 512 Mb or 64 MB soldered NOR flash

SDRAM
This is a specialized, socketed, 200-pin, small outline, clocked, dual in- line, memory module (SO-CDIMM). It provides Error-correcting Code (ECC) on the SDRAM memory bus operating at 200 MHz. The MPC8548 detects all double-bit errors, multi-bit errors within a
nibble and corrects all single-bit errors.
The 128M X 72 DDR2 SDRAM is a high-density, un-buffered SO-CDIMM. This module consists of nine 128x8-bit with eight banks DDR2 SDRAMs, a zero delay phase-lock loop (PLL)
clock, and a 2 KB serial presence detect (SPD) EEPROM. The SDRAM starts at physical
address 0000,000016.

Flash
There are several flash devices on the local bus interfacing the CPLD and MPC8548 processor. The four soldered flash banks are labeled 1 through 4:
• Banks 1 and 2 are the MPC8548 U-boot banks (see “4M x 16”). These boot banks are
used in the boot redirection scheme, see “Boot Device Redirection (BDR).”
• Banks 3 and 4 are physically one device, but appear in the software as two banks of 32
MB (see “64 MB x 16”). These are for general purpose storage.
512 KB x 8 (optional)
The 512 KB of 32-pin PLCC socketed flash starts at physical address FC80,000016 and is used
for Engineering code. The StrataFlash (P33) features high-performance fast asynchronous
access times, low power, and flexible security options.
4M x 16
The two 4 MB soldered flash devices are used for MPC8548 boot code. This redundant bank
configuration allows booting from either bank in case of corruption in one bank. See “Boot
Device Redirection (BDR)” on page 7-41. The SST NOR flash devices are organized as 4Mx8

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ATCA-9305 User’s Manual

4-7

Management Complex:

PCI

in a dual-bank architecture for concurrent read/write operation with hardware and software
data protection schemes. These devices start at physical addresses F000,000016 (boot bank
1) and F040,000016 (boot bank 2).
1 GB x 16
The ATCA-9305 uses 1 GB of M-Systems DiskOnChip (mDOC H3) NAND flash starting at
physical address FC00,000016 for non-volatile RAM storage and True Flash File System
(TFFS). This memory incorporates an embedded flash controller and memory, and includes
hardware protection and security-enabling features, an enhanced programmable boot
block enabling eXecution In Place (XIP) functionality using 16-bit access, user-controlled
One Time Programmable (OTP) partitions, and 6-bit Error Detection Code/Error Correction
Code (EDC/ECC).
64 MB x 16
The 64 MB soldered NOR flash starts at physical address F400,000016 (bank 3). The 64-Mbit
P33 device provides CN5860 code storage and non-volatile memory.

PCI
The MPC8548 performs all the functions of a PCI host and monarch, and handles all arbitration and enumeration functions. PCI starts at physical address 8000,000016.
The PCI bus connects to both Cavium processors, the MPC8548 processor and the Broadcom Ethernet switch, see Table 4-4. All of the devices on the PCI bus can operate at 66 MHz
and perform 64-bit transactions in conventional PCI mode except for the Broadcom switch.
The switch has a 32-bit PCI bus.
The MPC8548 stores the Cavium CN5860 operating system and monitor code in local
memory and then uses the boot over PCI functionality to bring up the CN5860 processor
complexes.
Table 4-4: PCI Device Interrupts and ID Assignments

PCI Device:

Interrupt:

IDSEL:

Cavium processor 1

IRQ6

PCI_AD11

Cavium processor 2

IRQ5

PCI_AD12

Ethernet switch

IRQ4

PCI_AD13

MPC8548

—

PCI_AD14

PCI Express
The four lane PCIe routes between the MPC8548 and the optional rear transition module
(zone 3 connector). PCIe starts at physical address E000,000016.

4-8

ATCA-9305 User’s Manual

10009109-01

Management Complex:

I2C Interface

I2C INTERFACE
The I2C interface consists of the MPC8548 initialization EEPROM, user (storage) NVRAM,
SO-CDIMM, and the Real-time Clock (RTC). The two Atmel two-wire serial EEPROMs on the
I2C interface consist of the Serial Clock (SCL) input and the Serial Data (SDA) bidirectional
lines.
Table 4-5: I2C Device Addresses

I2C Device:

Address:

MPC8548 Initialization (EEPROM-2)

0xA0

User NVRAM (EEPROM-1)

0xA2

DDR2 SDRAM (SO-CDIMM)

0xA4

M41T00 RTC

0xD0

The two EEPROMs store non-volatile information such as board, monitor, and operating system configurations as well as customer specific items.
Table 4-6: MPC8548 NVRAM Memory Map

EEPROM:

Address Offset
(hex):

Window
Size (bytes)

Description:

EEPROM-1
0xA2
(write
protected)

0x1FF0-0x1FFF

Boot verify secondary area (monitor)

16

0x1FE0-0x1FEF

Boot verify primary area (monitor)

16

EEPROM-2
0xA0
(write
protected)

0x0900-0x1FFF

Emerson reserved area

5887

0x0800-0x08FF

Miscellaneous

256

0x1EE0-0x1FDF

Operating system parameters (monitor)

256

0x0000-x1EDF

User defined

7903

0x07F0-0x07FF

Power-on Self-test (POST)

16

0x0000-0x07EF

User defined

2032

Note: Both EEPROMs are write-protected.

MANAGEMENT PROCESSOR HEADER AND SERIAL PORT
JTAG/COP Interface (optional)
The management complex uses header P2 for debug purposes.
Table 4-7: Serial Debug Connector, P2

Pin:

Signal:

Description:

1

PQ_TDO

Test Data Output is the serial data output as well as test and
programming data.

2

no connect

—

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ATCA-9305 User’s Manual

4-9

Management Complex:

Management Processor Header and Serial

Pin:

Signal:

Description: (continued)

3

PQ_TDI

Test Data Input is the serial input pin for instructions as well as test and
programming data.

4

DEBUG_TRST*

Test Reset input signal resets the test access port.

5

no connect

—

6

PQ_JTAG_PWR

3.3 volt power

7

PQ_TCK_R

Test Clock Input is the clock input to the boundary scan test (BST)
circuitry.

8

no connect

—

9

PQ_TMS

Test Mode Select input pin provides the control signal to determine
the transitions of the TAP controller state machine.

10

no connect

—

11

DEBUG_SRESET*

Soft Reset input signal indicates that the MPC8548 must initiate a
System Reset interrupt.

12

ground

—

13

DEBUG_HRESET*

Hard Reset input signal indicates that a complete Power-on Reset must
be initiated by the MPC8548.

14

no connect

—

15

PQ_CKSTP_OUT*

Checkstop Out indicates the MPC8548 has detected a checkstop
condition and has ceased operation.

16

ground

—

Serial Debug Port
The console port for the management processor is accessible via the front panel mini-B USB
connector P7. The supported baud rates for these ports operate at 9600, 14400, 19200,
38400, 57600, and 115200 bps.
Table 4-8: Serial Debug Connector, P7

Pin:

4-10

ATCA-9305 User’s Manual

Signal:

1

no connect

2

PQ_CONSOLE_RX_C

3

PQ_CONSOLE_TX_C

4

no connect

5

signal ground

6

chassis ground

7

chassis ground

10009109-01

Section 5

Management Processor CPLD

The ATCA-9305 uses a Programmable Logic Device (PLD) to provide control logic for the
local bus. The PLD implements various registers for reset, hardware, and LPC bus communication between the processors.

MPC8548 PLD REGISTER SUMMARY
The PLD registers start at address FC40,000016. As a rule, registers retain their values
through all resets except for power-on and front panel reset. Table 5-1 lists the 8-bit PLD registers followed by the register bit descriptions.
Table 5-1: PLD Register Summary

Address
Offset (hex):

Mnemonic:

Register Name:

See Page:

0x00

PIDR

Product ID

5-2

0x04

HVR

Hardware Version

5-2

0x08

PVR

PLD Version

5-3

0x0C

PLLCR

PLL Configuration

5-3

0x10

HCR00

Hardware Configuration 0

5-4

0x18

JSR

Jumper Setting

5-4

0x1C

LEDR

LED

5-5

0x20

RER

Reset Event

5-5

0x24

RCR1

Reset Command #1

5-6

0x28

RCR2

Reset Command #2

5-6

0x2C

RCR3

Reset Command #3

5-6

0x30

RCR4

Reset Command #4

5-7

0x34

RCR5

Reset Command #5

5-7

0x38

RCRS1

Reset Command Sticky #1

5-8

0x3C

RCRS2

Reset Command Sticky #2

5-8

0x40

SCR1

Scratch #11

—

0x50

BDRR

Boot Device Redirection

5-9

0x54

MISC

Miscellaneous Control (SIO, I2C, Test Clock)

5-9

0x58

LFTR1

Low Frequency Timer 1

5-9

0x5C

LFTR2

Low Frequency Timer 2

5-9

0x60

RGSR

RTM GPIO State

5-10

0x64

RGCR

RTM GPIO Control

5-10

0x68

RTMCR

RTM Control

5-11

0x70

CMUL1

Cavium 1 C_MUL Clock Divisor Control

5-11

0x74

CMUL2

Cavium 2 C_MUL Clock Divisor Control

5-12

0x78

JTAG

Altera JTAG Chain Software Control

5-12

0x80

CGCR

Cavium GPIO Control

5-12

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ATCA-9305 User’s Manual

5-1

Management Processor CPLD:

MPC8548 PLD Register

Address
Offset (hex):

Mnemonic:

Register Name:

0x84

CGDO

Cavium GPIO Data Out

0x88

CGDI

Cavium GPIO Data In

5-13

0x8C

IGCR

IPMP/IPMC GPIO Control

5-14

0xD0

LPC1

Low Pin Count (LPC) Bus Control

5-14

0xD4

LPCD

LPC Data

5-15

0xD8

SIRQI1

Serial IRQ Interrupt 1 [15:8]

5-15

0xDC

SIRQI2

Serial IRQ Interrupt 2 [7:0]

5-15

(continued)

See Page:
5-13

1. Scratch 1 (0x40) is a read/write register for storage only.

Product ID
This read-only register identifies the board as ATCA-9305, and is used for PLD coding.
Register 5-1: Product ID (0x00)

Bits:

Function:

Description:

7

CAVF1

Cavium Frequency 1

6

CAVF0

Cavium Frequency 0

5

0

Product ID

4

0

3

0

2

0

1

HC1

Hardware Configuration 1

0

HC0

Hardware Configuration 0

Hardware Version
This read-only register tracks hardware revisions.
Register 5-2: Hardware Version (0x04)

5-2

ATCA-9305 User’s Manual

Bits:

Function:

7

0

6

0

5

0

4

0

3

HVN (3)

2

HVN (2)

1

HVN (1)

0

HVN (0)

Description:

Hardware Version Number is hard coded in the PLD and changes
with every major PCB artwork version.
Version starts at 0016.

10009109-01

Management Processor CPLD:

MPC8548 PLD Register

PLD Version
This read-only register tracks PLD revisions.
Register 5-3: PLD Version (0x08)

Bits:

Function:

Description:

7

0

6

0

This is hard coded in the PLD and changes with every released code
change. Version starts at 0016.

5

0

4

0

3

0

2

0

1

0

0

0

PLL Reset Configuration
Write to this register to reconfigure the SYSCLK to CCB clock ratio and the CCB to CORE
clock ratio using valid values from the MPC8548E PowerQUICC™ III Integrated Processor Family
Reference Manual. The changes take affect when the processor is reset (for example, the
software hard reset command or watchdog timer expires). Default values are restored
when the board is power-cycled, front panel reset is pressed, or receives a PCI reset that was
not the result of the MPC8548 software initiating a PCI RSTOUT command.
Register 5-4: PLL Reset Configuration (0x0C)

Bits:

Function:

7

reserved

Description:

6

CCCB2

CCB2 to CORE clock ratio

5

CCCB1

CCB1 to CORE clock ratio

4

CCCB0

CCB0 to CORE clock ratio

3

CCBSYS3

SYSCLOCK3 to CCB clock ratio

2

CCBSYS2

SYSCLOCK2 to CCB clock ratio

1

CCBSYS1

SYSCLOCK1 to CCB clock ratio

0

CCBSYS0

SYSCLOCK0 to CCB clock ratio

Hardware Configuration 0
The read-only HCR0 allows the MPC8548 monitor software to easily determine specific
hardware configurations, such as the processor clock and MPC8548 DDR memory.

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ATCA-9305 User’s Manual

5-3

Management Processor CPLD:

MPC8548 PLD Register

Register 5-5: Hardware Configuration 0 (0x10)

Bits:

Function:

7

0

Description:

6

P33P

P33 (StrataFlash) is Present

5

RST_IND_CLR

Clear the Reset Indication to the IPMC controller

4

CAVF1

Cavium Frequency 1

3

CAVF0

Cavium Frequency 0

2

PQCF1

MPC8548 Core Frequency 1

1

PQCF0

MPC8548 Core Frequency 0

0

PQDDRF

MPC8548 DDR SDRAM Fast

Jumper Settings
These read-only bits may be read by software to determine the current jumper settings. See
the jumper descriptions on page 2-8.
Register 5-6: Jumper Settings (0x18)

Bits:

Function:

7

0

Description:

6

0

5

0

4

SJ

Cavium Boot Flash Jumper
0 Installed, Cavium processors boot from soldered flash
1 Not installed, Cavium processors boot from socket

3

BOOT

Boot PCI Jumper
0 Installed, boot from flash (socket or soldered per bit 4)
1 Not installed, boot over PCI from the MPC8548

2

REDIR

Boot Redirect Jumper
0 Installed, disables boot redirection
1 Not installed, enables boot redirection

1

IG ROM

Ignore SROM
0 Not installed, SROM is used for initialization (default)
1 Installed, disables SROM, uses default values in monitor
code

0

BT SKT

Boot from Socket
0 Not installed, enables MPC8548 to boot from soldered
flash (default)
1 Installed, enables MPC8548 to boot from socketed flash

LED
Writing a one to an LED bit lights that LED. During monitor power-up, the debug LEDs are
used to display the software progress.

5-4

ATCA-9305 User’s Manual

10009109-01

Management Processor CPLD:

MPC8548 PLD Register

Register 5-7: LED (0x1C)

Bits:

Function:

Description:

7

PQRED

MPC8548 red LED
Lit on power-up and turned off when the monitor finishes boot
up and Power-on Self Testing (POST)

6

PQGREEN

MPC8548 green LED

5

SWLEDCLK

Ethernet Switch LED Clock

4

SWLEDDAT

Ethernet Switch LED Data

3

DEBUGLED3

LED CR22

2

DEBUGLED2

LED CR21

1

DEBUGLED1

LED CR19

0

DEBUGLED0

LED CR18

Reset Event
This read-only register contains the bit corresponding to the most recent event which
caused a reset. When power is first applied, the FP_PSH_BUTTN reset event is not latched
into the Reset Event register, this is the Power-on Reset (POR) event. Front panel reset
events which occur after power-up will be latched.
Note: At power-up, the FRST_PWR_UP defaults to 1.
Register 5-8: Reset Event (0x20)

Bits:

Function:

Description:

7

RTMPB

RTM push button

6

SHR

Software Hard Reset Set to 1 when the last reset was caused
by a write to the Reset Command register

5

CPUHRR

CPU Hard Reset Request

4

COPSR

Set to 1 when a COP header or software-issued Soft Reset
(SRESET) has occurred

3

COPHR

Set to 1 when a COP header Hard Reset (HRESET) has occurred

2

PAYR

Set to 1 when a Payload Reset from the IPMC has occurred

1

SBR

Software Board Reset
Set to 1 when the IPMC software issued the board (payload)
reset

0

FPPB

Front Panel Push Button (FP_PSH_BUTTN, POR_RST)

Reset Command 1
The write-only Reset Command 1 register forces one of several types of resets, as shown
below. A reset sequence is first initiated by writing a one to a single valid bit, then the PLD
performs that particular reset, and the bit is automatically cleared.

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ATCA-9305 User’s Manual

5-5

Management Processor CPLD:

MPC8548 PLD Register

Register 5-9: Reset Command 1 (0x24)

Bits:

Function:

Description:

7

WBR

Reset the Whole Board

6

PQCR

Reset the MPC8548 Complex

5

CAV1CR

Reset the Cavium CN5860 1 Complex

4

CAV2CR

Reset the Cavium CN5860 2 Complex

3

SWICR

Reset the switch BCM5680x Complex

2

I2C R

Reset the I2C on the MPC8548

1

RTMR

Reset the (optional) RTM

0

reserved

Reset Command 2
The write-only Reset Command 2 register forces one of several types of MPC8548 resets, as
shown below. A reset sequence is first initiated by writing a one to a single valid bit, then the
PLD performs that particular reset, and the bit is automatically cleared.
Register 5-10: Reset Command 2 (0x28)

Bits:

Function:

Description:

7

PQHR

MPC8548 Hardware Reset

6

PQSR

MPC8548 Software Reset

5

PQDR

MPC8548 DDR SDRAM Reset

4

PQF

MPC8548 Flash reset

3

NANDR

MPC8548 NAND flash Reset

2

NANDWR

MPC8548 NAND flash Warm Reset

1

reserved

0

reserved

Reset Command 3
The write-only Reset Command 3 register forces one of several types of Cavium 1 resets, as
shown below. A reset sequence is first initiated by writing a one to a single valid bit, then the
PLD performs that particular reset, and the bit is automatically cleared.
Register 5-11: Reset Command 3 (0x2C)

5-6

ATCA-9305 User’s Manual

Bits:

Function:

Description:

7

CAV1R

Cavium 1 Reset

6

CAV1PR

Cavium 1 PCI Reset

5

CAV1DR

Cavium 1 DDR SDRAM Reset

4

CAV1F

Cavium 1 4 MB Flash (Cavium local bus) reset

3

CAV1M1

Cavium 1 MIP1 reset

2

CAV1M2

Cavium 1 MIP2 reset

10009109-01

Management Processor CPLD:

Bits:

Function:

1

reserved

0

reserved

MPC8548 PLD Register

Description: (continued)

Reset Command 4
The write-only Reset Command 4 register forces one of several types of Cavium 2 resets, as
shown below. A reset sequence is first initiated by writing a one to a single valid bit, then the
PLD performs that particular reset, and the bit is automatically cleared.
Register 5-12: Reset Command 4 (0x30)

Bits:

Function:

Description:

7

CAV2R

Cavium 2 Reset

6

CAV2PR

Cavium 2 PCI Reset

5

CAV2DR

Cavium 2 DDR SDRAM Reset

4

CAV2F

Cavium 2 4 MB Flash (Cavium local bus) reset

3

CAV2M3

Cavium 2 MIP3 reset

2

CAV2M4

Cavium 2 MIP4 reset

1

reserved

0

reserved

Reset Command 5
The write-only Reset Command 5 register forces one of several types of BCM5680x Ethernet
switch resets, as shown below. A reset sequence is first initiated by writing a one to a single
valid bit, then the PLD performs that particular reset, and the bit is automatically cleared.
Register 5-13: Reset Command 5 (0x34)

Bits:

Function:

Description:

7

SWIR

Switch Reset

6

TSEC1R

TSEC1 Ethernet to front panel PHY Reset

5

TSEC2R

TSEC2 Ethernet to switch PHY Reset

4

FPIR

FPI Ethernet to front panel PHY Reset

3

BCR

Ethernet dual PHY to backplane Base Channel reset

2

reserved

1

reserved

0

reserved

Reset Command Sticky #1
The read/write Reset Command Sticky #1 register forces one of several types of the groupcomplex resets, as shown below. A reset sequence is first initiated by writing a one to one or
more bits, then the PLD performs that particular reset. The bit will persist until cleared.

10009109-01

ATCA-9305 User’s Manual

5-7

Management Processor CPLD:

MPC8548 PLD Register

Note: The board powers down and powers back up when the Cavium processors power is back up (bits 0 or 1 are
cleared).
Register 5-14: Reset Command Sticky #1 (0x38)

Bits:
7
6
5
4
3
2
1
0

Function:

Description:

CAV1C

Cavium 1 Complex reset

CAV2C

Cavium 2 Complex reset

SWIC

Switch Complex reset

CAV1CF

Cavium 1 Complex 4MB Flash reset

CAV2CF

Cavium 2 Complex 4MB Flash reset

NANDF

NAND Flash reset

CAV2RPD

Reset and power down the Cavium 2 core

CAV1RPD

Reset and power down the Cavium 1 core

Reset Command Sticky #2
The read/write Reset Command Sticky #2 register forces one of several types of the PHY
reset command, as shown below. A reset sequence is first initiated by writing a one to one
or more bits, then the PLD performs that particular reset. The bit will persist until cleared.
Register 5-15: Reset Command Sticky #2 (0x3C)

Bits:

Function:

7

TSEC1R

Description:
TSEC1 Ethernet to front panel PHY Reset

6

TSEC2R

TSEC2 Ethernet to switch PHY Reset

5

FPIR

FPI Ethernet from switch to front panel PHY Reset

4

BCR

Ethernet dual PHY to backplane Base Channel Reset

3

MIP1

SPI to XAUI bridge #1 on Cavium 1

2

MIP2

SPI to XAUI bridge #2 on Cavium 1

1

MIP3

SPI to XAUI bridge #3 on Cavium 2

0

MIP4

SPI to XAUI bridge #4 on Cavium 2

Boot Device Redirection
The read/write Boot Device Redirection register (BDRR) allows the user to determine which
of three boot devices the MPC8548 CPU is using as the boot device. Several bits also indicate which device was set as the initial boot device. The Boot Redirected bit is set to a 1
when the current boot device does not match the initial default boot device. This indicates
to the user that the image in the default device was bad, the MPC8548 watch dog timer
expired, and the next device was tried. The boot device redirection order is determined by
IPMC. Reference the “Boot Device Diagram”.

5-8

ATCA-9305 User’s Manual

10009109-01

Management Processor CPLD:

MPC8548 PLD Register

Register 5-16: Boot Device Redirection (0x50)

Bits:

Function:

Description:

7

SELFRS

Self Refresh Started

6

BOOTSEL1

IPMC successful boot indication (BOARD_BOOTED)

5

reserved

4

BSJ

3

NFBS

Nand Flash Busy Signal

2

BDS

Active boot device is socket

1

BDF1

Active boot device is flash 2

0

BDF0

Active boot device is flash 1

Boot from Socket Jumper A shunt on J9 [1:2] selects the
512KB socketed ROM as the boot device, see Fig. 2-6.

Miscellaneous Control

This register includes two bits for manually toggling the MPC8548 I2C bus.
Register 5-17: Miscellaneous Control (0x54)

Bits:

Function:

Description:

7

P33WP

0
1

Write Protect disabled (default until the monitor boots)
Write Protect enabled

6

SROM1WP

0
1

Write Protect disabled
Write Protect enabled (default)

5

SROM0WP

0
1

Write Protect disabled
Write Protect enabled (default)

4

FLASH1WP

0
1

Write Protect disabled (default until the monitor boots)
Write Protect enabled

3

FLASH0WP

0
1

Write Protect disabled (default until the monitor boots)
Write Protect enabled

2

NANDWP

0
1

Write Protect disabled
Write Protect enabled (default)

1

I2CSDA

I2C Data line
0 Drive a 0 onto the I2C SDA line
1 Drive a 1 onto the I2C SDA line

0

I2CSCL

I2C Clock line
0
1

Drive a 0 onto the I2C SCL line
Drive a 1 onto the I2C SCL line

Low Frequency Timer 1 and 2
Registers LFTR1 (0x58) and LFTR2 (0x5C) are timers. They determine how many 50 μs intervals you want before the next interrupt on Cavium GPIO5.
Note: Unless the frequency is set to 0, there is always one 50 μs interval. This is the reason for the register setting
being 1 less than an even hundred, for example 199 rather than 200.

10009109-01

ATCA-9305 User’s Manual

5-9

Management Processor CPLD:

MPC8548 PLD Register

Table 5-2: Low Frequency Timer Settings

Frequency:

Set Register:

0

Off

Never interrupts

1 Hz

19999 (0x4E1F)

These frequencies require the use of both registers

10 Hz

1999 (0x7CF)

100 Hz

199 (0xC7)

1 KHz

19 (0x13)

10 KHz

1

Comments:

This equals two 50 μs time units (default)

RTM GPIO State
This read-only register reads the current state of the GPIO pins.
Register 5-18: RTM GPIO State (0x60)

Bits:

Function:

7

RTM_GPIO 7

6

RTM_GPIO 6

5

RTM_GPIO 5

4

RTM_GPIO 4

3

RTM_GPIO 3

2

RTM_GPIO 2

1

RTM_GPIO 1

0

RTM_GPIO 0

Description:

RTM GPIO Control
This register sets the state of the GPIO pins. These signals are implemented as open collector signals.
Register 5-19: RTM GPIO Control (0x64)

Bits:

Function:

Description:

7

RTM_GPIO 7

6

RTM_GPIO 6

5

RTM_GPIO 5

0 Causes the corresponding bit to be driven to 0
1 Tristates the signal; this will either be read by the RTM as a 1
or can be driven by the RTM to any value

4

RTM_GPIO 4

3

RTM_GPIO 3

2

RTM_GPIO 2

1

RTM_GPIO 1

0

RTM_GPIO 0

RTM Status
The RTM identification (ID) is determined by factory installed configuration resistors.

5-10

ATCA-9305 User’s Manual

10009109-01

Management Processor CPLD:

MPC8548 PLD Register

Register 5-20: RTM Control (0x68)

Bits:

Function:

7

0

Description:

6

0

5

0

4

RTMP

RTM is Present

3

RTMID3

RTM Identification bits 3:0

2

RTMID2

1

RTMID1

0

RTMID0

0000 = Test RTM (factory only)
1000 = 20GbE I/O RTM
1100 = 18GbE and 2x10GbE I/O RTM
1010 = Storage RTM

Cavium 1 C_MUL Clock Divisor Control
Use the C_MUL1 register to reduce the speed of the Cavium CN5860 processor 1 core.
Caution: Do not over-clock the Cavium frequency (bits 6:7 hard strapped).
!

Register 5-21: Cavium 1 C_MULL Clock Divisor Control (0x70)

Bits:

Function:

Description:

7

CAVF

Cavium Frequency resistor set bit (read-only)
00 600
01 750
10 800
11 reserved

5

CMULOE

C_MUL Output Enable

4

P1CMUL4

3

P1CMUL3

2

P1CMUL2

These bits drive directly to the Cavium 1. The core clock speed
is the number multiplied by 50 MHz. For example, the 800 MHz
core is set to 16(0x10).

1

P1CMUL1

0

P1CMUL0

6

Cavium 2 C_MUL Clock Divisor Control
Use the C_MUL2 register to reduce the speed of the Cavium CN5860 processor 2 core.
Caution: Do not over-clock the Cavium frequency (bits 6:7 hard strapped).
!

10009109-01

ATCA-9305 User’s Manual

5-11

Management Processor CPLD:

MPC8548 PLD Register

Register 5-22: Cavium 2 C_MULL Clock Divisor Control (0x74)

Bits:

Function:

Description:

7

CAVF1

Cavium 1 Frequency resistor set bit (read-only, see Register
Map 5-21)

6

CAVF0

Cavium 0 Frequency resistor set bit (read-only)

5

CMULOE

C_MUL Output Enable

4

P1CMUL4

3

P1CMUL3

2

P1CMUL2

These bits drive directly to the Cavium 2. The core clock speed
is the number multiplied by 50 MHz. For example, the 800 MHz
core is set to 16(0x10).

1

P1CMUL1

0

P1CMUL0

JTAG
This register allows for manual reprogramming of the PLDs on the board. Changes to this
register do not take effect until after a full board reset.
Register 5-23: JTAG (0x78)

Bits:

Function:

7

reserved

Description:

6

reserved

5

JTAGOEN

JTAG Output Enable

4

JTAGTCKSEL

JTAG Test Clock Select changes from header to PLD as the TCK
source

3

JTAGTCK

JTAG Test Clock

2

JTAGTMS

JTAG Test Mode Select

1

JTAGTDO

JTAG Test Data Output

0

JTAGTDI

JTAG Test Data Input (read only)

Cavium GPIO Control
Each Cavium processor has three GPIO control bits connected to the PLD. This register
determines whether the PLD is driving or receiving on these lines. Setting a bit to 1 causes
the PLD to drive the corresponding line.
Register 5-24: Cavium GPIO Control (0x80)

5-12

ATCA-9305 User’s Manual

Bits:

Function:

7

reserved

Description:

6

reserved

5

P2GPIO5OE

Processor 2 GPIO5 Output Enable (enabled is the default)
Output enable is set for the TIC timer output to the Cavium

4

P2GPIO4OE

Processor 2 GPIO4 Output Enable
This is an input from the Cavium to reset the MIP4

10009109-01

Management Processor CPLD:

MPC8548 PLD Register

Bits:

Function:

Description: (continued)

3

P2GPIO3OE

Processor 2 GPIO3 Output Enable
This is an input from the Cavium to reset the MIP3

2

P1GPIO5OE

Processor 1 GPIO5 Output Enable (enabled is the default)
Output enable is set for the TIC timer output to the Cavium

1

P1GPIO4OE

Processor 1 GPIO4 Output Enable
This is an input from the Cavium to reset the MIP2

0

P1GPIO3OE

Processor 1 GPIO3 Output Enable
This is an input from the Cavium to reset the MIP1

Cavium GPIO Data Out
This register is the data that will be driven on the GPIO line when the Output enable is set.
Register 5-25: Cavium GPIO Data Out (0x84)

Bits:

Function:

7

reserved

6

reserved

Description:

5

reserved

4

P2GPIO4

Set the value of the Cavium 2 GPIO bit 4

3

P2GPIO3

Set the value of the Cavium 2 GPIO bit 3

2

reserved

1

P1GPIO4

Set the value of the Cavium 1 GPIO bit 4

0

P1GPIO3

Set the value of the Cavium 1 GPIO bit 3

Cavium GPIO Data In
This register reads the value on the GPIO lines connected to each Cavium.
Register 5-26: Cavium GPIO Data In (0x88)

Bits:

Function:

7

reserved

6

reserved

Description:

5

reserved

4

P2GPIO4

Read the value of the Cavium 2 GPIO bit 4

3

P2GPIO3

Read the value of the Cavium 2 GPIO bit 3

2

reserved

1

P1GPIO4

Read the value of the Cavium 1 GPIO bit 4

0

P1GPIO3

Read the value of the Cavium 1 GPIO bit 3

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Management Processor CPLD:

MPC8548 PLD Register

IPMP/IPMC GPIO Control
This register provides access (if required) to signals between the KSL CPLD and the IPMP, as
well as to signals between the KSL CPLD and the IPMC. The lower two bits can request
request the power down of a Cavium core from the sticky reset register.
Register 5-27: IPMP/IPMC GPIO Control (0x8C)

Bits:

Function:

Description:

7

IPMC2KSL4

Input only

6

IPMC2KSL3

5

IPMC2KSL2

4

IPMC2KSL1

3

IPMP2KSL4

Output only

2

IPMP2KSL3

Output only

1

IPMP2KSL2

Power-down signal for Cavium 2 (output)
Assert high to shut down the core. The sticky Cavium reset also
causes this to be asserted.

0

IPMP2KSL1

Power-down signal for Cavium 1 (output)
Assert high to shut down the core. The sticky Cavium reset also
causes this to be asserted.

LPC Bus Control
This is the control register for the 4-bit LPC bus. It allows for communication with the IPMC
controller from the management CPU.
Register 5-28: LPC Bus (0xD0)

Bits:

Function:

7

LPCIE

Description:
LPC Interrupt Enable

6

LPCS

LPC State (internal use only)

2

LPCIOE

LPC I/O Error

1

SYNCE

SYNC Error

0

SYNCT

SYNC Time-out

5
4
3

LPC Data
This is the data register for the 4-bit LPC bus. It allows for communication with the IPMC
controller from the management CPU. This register provides the data to be sent or received,
depending upon the commands given in the control register.

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Management Processor CPLD:

MPC8548 PLD Register

Register 5-29: LPC Data (0xD4)

Bits:

Function:

Description:

7:0

-

LPC Data

Serial IRQ Interrupt 1
This is interrupt register1 for the LPC bus.
Register 5-30: Serial IRQ Interrupts 1 (0xD8)

Bits:

Function:

Description:

7:0

-

Interrupts

Serial IRQ Interrupt 2
This is interrupt register2 for the LPC bus.
Register 5-31: Serial IRQ Interrupts 2 (0xDC)

Bits:

Function:

Description:

7:0

-

Interrupts

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Section 6

Ethernet Interface

The ATCA-9305 supports multiple Ethernet interfaces. This chapter describes the Broadcom
BCM56802 switch, PHYS BCM5482 and BCM5461S, Ethernet address, LEDs and connectors.

BROADCOM BCM56802 SWITCH
The BCM56802 is a 16-port, 10-GbE multi-layer switch based on the StrataXGS® architecture. The switch operates at 66 MHz with a 32-bit PCI bus for processor communication.
SERDES functionality includes 10-Gbps XAUI and 1-Gbps SGMII PHY interfaces.
One 10/100/1000BASE-T Ethernet (SGMII) port is routed to a front panel RJ45 connector
(see Fig. 6-1), one is routed to the MPC8548 management processor TSEC2 port, and two
are routed to the base channel backplane (see Fig. 8-2). Two 10 GbE XAUI ports connect to
the back panel via the fabric channel (see Fig. 8-2).
Two XAUI ports process packets to and from each CN5860 processor. Six 10 GbE XAUI ports
route to the optional rear transition module (RTM). See Table 8-3 and Table 8-4 for pin assignments.
Note: Proprietary information on the Broadcom switch is not available in this user’s manual. Refer to their web site
for available documentation.

ETHERNET SWITCHING
The base interface Ethernet ports are provided by the Broadcom BCM56802 16-port, 10
gigabit (GbE) switch. The SerDes functionality includes 10-Gbps XAUI and 1-Gbps SGMII
PHY interfaces. The integrated SerDes complies with the CX-4 standard and PICMG 3.1
standard. The Fabric interface is compliant with PICMG 3.1 Revision 1.0, specifically link
option 9 (one 10GBASE-BX4). Switch connectivity consists of the following devices:
• Two 10GbE ports to CN5860 processor complex 1
• Two 10GbE ports to CN5860 processor complex 2
• One GbE port to the front panel (RJ45 connector)
• One GbE port to the MPC8548 management processor complex, then out the front
panel (RJ45 connector)
• Two 10 GbE ports to the fabric interface
• Two 1 GbE ports to the base interface
• Two or six 10 GbE ports to the Zone 3 connector (optional RTM)

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Ethernet Interface:

Ethernet Switching

Figure 6-1: Ethernet Switching Interface Diagram
RJ45

RJ45

BCM5461S

BCM5461S

MPC8548
Management
Processor

BCM5461S
3
SGMII

Stratix II GX
#1

6 XAUI

Stratix II GX
#2

5 XAUI

XAUI 13

Stratix II GX
#3

XAUI 14

Stratix II GX
#4

BCM56802
XAUI 10 Gb
Switch Ports

SGMII
2

SGMII
1

XAUI
8 7

XAUI
11-12 15 -18

10G Fabric

To Optional RTM

BCM5482

Base

J23

J30

SPI-0

Cavium
Octeon
CN5860
SPI-1 Processor 2

10G - 4 PORTS

SPI-0

Cavium
Octeon
CN5860
Processor 1 SPI-1

4
SGMII

10G - 2 PORTS

P1 DDR2
SDRAM

J31

Note: The phyiscal port numbering starts at 1, as indicated in the figure. However, the software port numbering
starts at 0. Therefore, to issue a command to a port, you must subtract 1 from the port numbers shown in the
figure.

Ethernet Transceivers
The BCM5461S is a 10/100/1000BASE-T GbE Ethernet transceiver using the SGMII interface.
The BCM5482 consists of two complete 10/100/1000BASE-T GbE transceivers supporting
both voice and data simultaneously.

Ethernet Switch Ports
Table 6-1: Ethernet Switch Ports

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ATCA-9305 User’s Manual

Port:

Interface:

Connection:

1

SGMII 1 GB

PHY to backplane BASE

2

SGMII 1 GB

PHY to backplane BASE

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Ethernet Interface:

MPC8548 Management Processor Ethernet

Port:

Interface:

Connection: (continued)

3

SGMII 1 GB

Switch PHY to front panel RJ45 connector

4

SGMII 1 GB

Management processor PHYs to front panel RJ45 connector

5

XAUI 10 GB

Stratix II GX bridge 2

6

XAUI 10 GB

Stratix II GX bridge 1

7

XAUI 10 GB

Back plane Fabric

8

XAUI 10 GB

Back plane Fabric

9

—

not used

10

—

not used

11

XAUI 10 GB

BCM56802 to J30 to optional RTM

13

XAUI 10 GB

Stratix II GX bridge 3

14

XAUI 10 GB

Stratix II GX bridge 4

15

XAUI 10 GB

BCM56802 to J31 to optional RTM

12

16
17
18

VLAN Setup
The default VLAN configuration is defined in Table 6-2. See page 9-25 for the monitor vlan
command.
Table 6-2: VLAN Configuration

VLAN:

Ports:

1

1, 3, 4

2

6, 7

3

8, 13

4

5, 11

5

12, 14

MPC8548 MANAGEMENT PROCESSOR ETHERNET ADDRESS
The Ethernet address for your board is a unique identifier on a network. The address consists of 48 bits (MAC [47:0]) divided into two equal parts. The upper 24 bits define a unique
identifier that has been assigned to Emerson Network Power, Embedded Computing by
IEEE. The lower 24 bits are defined by Emerson for identification of each of our products.
The Ethernet address for the ATCA-9305 is a binary number referenced as 12 hexadecimal
digits separated into pairs, with each pair representing eight bits. The address assigned to
the ATCA-9305 has the following form:

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Ethernet Interface:

MPC8548 Management Processor Ethernet

00 80 F9 xx yy zz
00 80 F9 is Emerson’s identifier. The last three bytes of the Ethernet address consist of the
port (one byte), 0x97(port 1) or 0x98 (port 2), followed by the serial number (two byte
hexadecimal). The ATCA-9305 has been assigned the Ethernet address range
00:80:F9:97:00:00 to 00:80:F9:98:FF:FF. The format is shown in Table 6-3.
Table 6-3: Ethernet Port Address

Offset:

MAC:

Description:

Ethernet Identifier (hex):

Byte 5

15:0

LSB of (serial number in hex)

—

Byte 4

MSB of (serial number in hex)

—

Byte 3

23:16

Port 1 (TSEC_1)
Port 2 (TSEC_2)

0x97
0x98

Byte 2

47:24

Assigned to Emerson by IEEE

0xF9

Byte 1

0x80

Byte 0

0x00

The last two bytes, MAC[15:0], correspond to the following formula: n —1000, where n is
the unique serial number assigned to each board. So if an ATCA-9305 serial number is 1032,
the calculated value is 32 (2016), and the default Ethernet port addresses are:
• TSEC_1 MAC address is: 0x00 0x80 0xF9 0x97 0x00 0x20
• TSEC_2 MAC address is: 0x00 0x80 0xF9 0x98 0x00 0x20

Front Panel Ethernet Ports
One MPC8548 PHY (TSEC1) routes to front panel RJ45 connector, P1. The BCM56802 switch
PHY (port 3) routes to front panel RJ45 connector, P3. The Ethernet port LEDs (green or yellow) indicate link and activity status, see front panel Fig. 2-1.
Table 6-4: Front Panel Ethernet Ports

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ATCA-9305 User’s Manual

Pin:

P1 Signal:

P3 Signal:

1

TSEC1_TRD0_P

FP1_TRD0_P

2

TSEC1_TRD0_N

FP1_TRD0_N

3

TSEC1_TRD1_P

FP1_TRD1_P

4

TSEC1_TRD2_P

FP1_TRD2_P

5

TSEC1_TRD2_N

FP1_TRD2_N

6

TSE1C_TRD1_N

FP1_TRD1_N

7

TSEC1_TRD3_P

FP1_TRD3_P

8

TSEC1_TRD3_N

FP1_TRD3_N

9

TSEC1_ACTIVITY (green LED 1)

FP1_ACTIVITY (green LED1)

10

2_5V (yellow LED 1)

2_5V (yellow LED 1)

11

TSEC1_LINKSPD1 (green LED 2)

FP1_LINKSPD1 (green LED 2)

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Ethernet Interface:

MPC8548 Management Processor Ethernet

Pin:

P1 Signal:

P3 Signal: (continued)

12

TSEC1_LINKSPD2 (yellow LED 2)

FP1_LINKSPD2 (yellow LED 2)

13

TSEC1_CHSGND

FP1_CHSGND

14

TSEC1_CHSGND

FP1_CHSGND

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Section 7

System Management

The ATCA-9305 provides an intelligent hardware management system, as defined in the
AdvancedTCA Base Specification (PICMG® 3.0). This system implements an Intelligent Platform Management Controller (IPMC) based on the BMR-H8S-AMCc® reference design from
Pigeon Point Systems. It also has an inter-integrated circuit (I2C) controller to support an
Intelligent Platform Management Bus (IPMB) that routes to the ATCA backplane.
The IPMC implements all the standard Intelligent Platform Management Interface (IPMI)
commands and provides hardware interfaces for other system management features such
as Hot Swap control, LED control, power negotiation, and temperature and voltage monitoring. The IPMC also supports an EIA-232 interface for serial communications via the Serial
Interface Protocol Lite (SIPL) IPMI commands.

IPMC OVERVIEW
The basic features for the IPMC implementation include:
• Conformance with AdvancedTCA Base Specification (PICMG® 3.0)
• Geographical addressing according to PICMG® 3.0
• Ability to read and write Field Replaceable Unit (FRU) data
• Ability to reset IPMC from IPMB
• Ability to read inlet and outlet airflow temperature sensors
• Ability to read payload voltage/current levels
• Ability to send event messages to a specified receiver
• All sensors generate assertion and/or de-assertion event messages
• Support for fault tolerant HPM.1 firmware upgrades
• Support for field updates of firmware via IPMB-0 or the payload interface
• Redundant boot bank capability

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System Management:

IPMI Messaging

Figure 7-1: IPMC Connections Block Diagram

UART
& LPC

IPMI MESSAGING
All IPMI messages contain a Network Function Code field, which defines the category for a
particular command. Each category has two codes assigned to it–one for requests and one
for responses. The code for a request has the least significant bit of the field set to zero,
while the code for a response has the least significant bit of the field set to one. Table 7-1 lists
the network function codes (as defined in the IPMI specification) used by the IPMC.

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System Management:

IPMI Messaging

Table 7-1: Network Function Codes

Hex Code
Value(s):

Name:

Type:

Name:

00, 01

Chassis

chassis device
requests/responses

00 = command/request, 01 = response:
common chassis control and status functions

02, 03

Bridge

bridge
requests/responses

02 = request, 03 = response:
message contains data for bridging to the next
bus. Typically, the data is another message,
which also may be a bridging message. This
function is only present on bridge nodes.

04, 05

Sensor/
Event

sensor and event
requests/responses

04 = command/request, 05 = response:
for configuration and transmission of Event
Messages and system Sensors. This function
may be present on any node.

06, 07

App

application
requests/responses

06 = command/request, 07 = response:
message is implementation-specific for a
particular device, as defined by the IPMI
specification

08, 09

Firmware

firmware transfer
requests/responses

08 = command/request, 09 = response:
firmware transfer messages match the format
of application messages, as determined by the
particular device

0A, 0B

Storage

non-volatile
storage
requests/responses

0A = command/request, 0B = response:
may be present on any node that provides
nonvolatile storage and retrieval services

0C-2F

reserved

–

reserved: 30 network functions (15 pairs)

30-3F

OEM

–

30 = command/request, 3F = response:
vendor specific: 16 network functions (8 pairs).
The vendor defines functional semantics for
cmd and data fields. The cmd field must hold the
same value in requests and responses for a
given operation to support IPMI message
handling and transport mechanisms. The
controller’s Manufacturer ID value identifies the
vendor or group.

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System Management:

IPMI Messaging

IPMI Completion Codes
All IPMI response messages contain a hexadecimal Completion Code field that indicates the
status of the operation.
Table 7-2: Completion Codes

Code:

Description:

Generic Completion Codes 00, C0-FF

7-4

ATCA-9305 User’s Manual

00

Command completed normally

C0

Node busy–command could not be processed because command-processing resources
are temporarily unavailable

C1

Invalid command–indicates an unrecognized or unsupported command

C2

Command invalid for given LUN

C3

Time-out while processing command, response unavailable

C4

Out of space–command could not be completed because of a lack of storage space
required to execute the given command operation

C5

Reservation canceled or invalid Reservation ID

C6

Request data truncated

C7

Request data length invalid

C8

Request data field length limit exceeded

C9

Parameter out of range–one or more parameters in the data field of the Request are out
of range. This is different from Invalid data field code (CC) because it indicates that the
erroneous field(s) has a contiguous range of possible values.

CA

Cannot return number of requested data bytes

CB

Requested sensor, data, or record not present

CC

Invalid data field in Request

CD

Command illegal for specified sensor or record type

CE

Command response could not be provided

CF

Cannot execute duplicated request–for devices that cannot return the response returned
for the original instance of the request. These devices should provide separate commands
that allow the completion status of the original request to be determined. An Event
Receiver does not use this completion code, but returns the 00 completion code in the
response to (valid) duplicated requests.

D0

Command response could not be provided, SDR Repository in update mode

D1

Command response could not be provided, device in firmware update mode

D2

Command response could not be provided, Baseboard Management Controller (BMC)
initialization or initialization agent in progress

D3

Destination unavailable–cannot deliver request to selected destination. (This code can be
returned if a request message is targeted to SMS, but receive message queue reception is
disabled for the particular channel.)

D4

Cannot execute command, insufficient privilege level

D5

Cannot execute command, parameter(s) not supported in present state

FF

Unspecified error

10009109-01

System Management:

Code:

IPMB Protocol

(continued)

Description:

Device-Specific (OEM) Codes 01-7E
01-7E

Device specific (OEM) completion codes–command-specific codes (also specific for a
particular device and version). Interpretation of these codes requires prior knowledge of
the device command set.

Command-Specific Codes 80-BE
80-BE

Standard command-specific codes–reserved for command-specific completion codes
(described in this chapter)

IPMB PROTOCOL
The IPMB message protocol is designed to be robust and support many different physical
interfaces. The IPMC supports messages over the IPMB interface. Messages are defined as
either a request or a response, as indicated by the least significant bit in the Network Function Code of the message.
Table 7-3: Format for IPMI Request Message

Byte:

Bits:
7

6

5

4

1
2

3

2

1

0

rsSA
Network Function (netFn)

3

rsLUN

Checksum
rqSA

4
5

rqLUN

rqSeq

6

Command

7:N

Data

N+1

Checksum

• The first byte contains the responder’s Slave Address, rsSA.
• The second byte contains the Network Function Code, netFn, and the responder’s
Logical Unit Number, rsLUN.
• The third byte contains the two’s-complement checksum for the first two bytes.
• The fourth byte contains the requester’s Slave Address, rqSA.
• The fifth byte contains the requester’s Sequence Number, rqSeq, and requester’s Logical
Unit Number, rqLUN. The Sequence number may be used to associate a specific response
to a specific request.
• The sixth byte contains the Command Number.

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System Management:

SIPL Protocol

• The seventh byte and beyond contain parameters for specific commands (if required).
• The final byte is the two’s-complement checksum of all of the message data after the
first checksum.
An IPMI response message (see Table 7-4) is similar to an IPMI request message. The main
difference is that the seventh byte contains the Completion Code, and the eighth byte and
beyond hold data received from the controller (rather than data to send to the controller).
Also, the Slave Address and Logical Unit Number for the requester and responder are
swapped.
Table 7-4: Format for IPMI Response Message

Byte:

Bits:
7

6

5

4

1
2

3

2

1

0

rqSA
Network Function (netFn)

3

rqLUN

Checksum
rsSA

4
5

rsLUN

rsSeq

6

Command

7

Completion Code

8:N

Data

N+1

Checksum

SIPL PROTOCOL
The IPMC supports the Serial Interface Protocol Lite (SIPL) protocol. It supports raw IPMI
messages in SIPL and handles these messages the same way as it handles IPMI messages
from the IPMB-0 bus, except that the replies route to either the payload or serial debug
interface. Messages are entered as case-insensitive hex-ASCII pairs, separated optionally by
a space, as shown in the following examples:
[18 00 22]
[180022]

The IPMC does not, however, support SIPL ASCII text commands, as defined by the IPMI
specification.
The IPMC does support Pigeon Point Systems extension commands, implemented as OEM
IPMI commands. These commands use Network Function Codes 2E/2F (hex), and the message body is transferred similarly to raw IPMI messages, as described previously.
The following figures show an example of an extension command request and response,
respectively.

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ATCA-9305 User’s Manual

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System Management:

Message Bridging

Figure 7-2: Extension Command Request Example

[B8
[B8 00
00 01
01 0A
0A 40
40 00
00 12]
12]

Data
Data
Pigeon Point IANA
IANA
Command Code
Command
rqSeq (00
(001616)) // Bridge
Bridge (0022))
rqSeq
NetFnCode
Code (2E
(2E1616)) // LUN
LUN (00
(0022))
NetFn

Figure 7-3: Extension Command Response Example

[BC 00 01 00 0A 40 00 34]

Data
Pigeon Point IANA
Completion Code
Command Code
rqSeq (0016) / Bridge (002)
NetFn Code (2F16) / LUN (002)

MESSAGE BRIDGING
The Message Bridging facility is responsible for bridging messages between various interfaces of the ATCA-9305 IPMI. The message bridging is implemented via the standard Send
Message command.
The ATCA-9305 IPMC also supports message bridging between the Payload Interface and
IPMB-0, which allows the payload to send custom messages to and receive them from other
shelf entities, such as the shelf manager. Message bridging is implemented using the
Send/Get Message commands and also via LUN 10 of the ATCA-9305 IPMC.

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System Management:

Message Bridging

The following example illustrates how the Send/Get Message and Get Address Info commands can be used by the payload software to get the physical location of the board in the
shelf:
1 The payload software sends the Get Address Info command to the BMR-H8S-AMCc,
requesting address information for FRU device 0. Using the SIPL protocol:
[B0 xx 01 00]

2 The BMR-H8S-AMCc returns its IPMB address in the Get Address Info reply. In this example,
7216 is the IPMB-0 address of the IPMC.
{B4 00 01 00 00 FF 72 FF 00 01 07]

3 The payload software composes a Get Address Info command requesting the responder to
provide its addressing information for FRU device 0. The request is composed in the IPMB
format. The responder address is set to 2016 (for the shelf manager). The requester address
is set to the value obtained in the previous step.
{20 B0 30 72 00 01 00 8D]

4 The payload software forwards the command composed in the previous step to the shelf
manager using the Send Message command. The Send/Get Message in SIPL format is:
[18 xx 34 40 20 B0 30 72 00 01 00 8D]

5 The BMR-H8S-AMCc firmware sends the Get Address Info request to the shelf manager,
waits for a reply to this request, and sends this reply to the payload software in the Send/Get
Message response.
[1C 00 34 00 72 B4 DA 20 00 01 00 00 41 82 FF 00 FF 00 1E]

6 The payload software extracts the Get Address info reply from the Send/Get Message
response and retrieves the physical address of the board from it.
The second message bridging implementation, bridging via LUN 10, allows the payload to
receive responses to requests sent to IPMB-0 via the Send Message command with request
tracking disabled, as well as receive requests from IPMB-0. To provide this functionality, the
ATCA-9305 IPMC places all messages coming to LUN 10 from IPMB-0 in a dedicated Receive
Message Queue, and those messages are processed by the payload instead of the IPMC
firmware. To read messages from the Receive Message Queue, the payload software uses
the standard Get Message command. The payload software is notified about messages
coming to LUN 10 via the Get Status command of the SIPL protocol and the payload notification mechanism, or, if the LPC/KCS-based Payload Interface is used, using the KCS interrupt. The Receive Message Queue of the ATCA-9305 IPMC is limited to 128 bytes, which is
sufficient for storing at least three IPMB messages, but may be not enough for a larger number of messages. Taking this into account, the payload software must read messages from
the queue as fast as possible, caching them on the on-carrier payload side for further han-

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System Management:

Standard Commands

dling, if it is necessary. If the Receive Message Queue is full, the ATCA-9305 IPMC rejects all
requests coming to LUN 10 with the C0h (Node Busy) completion code and discards all
responses coming to this LUN.

STANDARD COMMANDS
The Intelligent Peripheral Management Controller (IPMC) supports standard IPMI commands to query board information and to control the behavior of the board. These commands provide a means to:
• identify the controller
• reset the controller
• return the controller’s self-test results
• read and write the controller’s SROMs
• read the temperature, voltage, and watchdog sensors
• get specific information, such as thresholds, for each sensor
• read and write the Field Replaceable Unit (FRU) data
• reserve and read the Sensor Data Record (SDR) repository
• configure event broadcasts
• bridge an IPMI request to the public IPMB and return the response
Table 7-5 lists the IPMI commands supported by the IPMC along with the hexadecimal values
for each command’s Network Function Code (netFn), Logical Unit Number (LUN), and Command Code (Cmd):
Table 7-5: IPMC IPMI Commands

Command:

netFn:

LUN:

Cmd:

Set System Boot Options

Chassis

01, 01

07

Get System Boot Options

Chassis

01, 01

08

Set Event Receiver

Sensor/Event

04, 05

00

Get Event Receiver

Sensor/Event

04, 05

01

Platform Event (Event Message)

Sensor/Event

04, 05

02

Get Device SDR Information

Sensor/Event

04, 05

20

Get Device SDR

Sensor/Event

04, 05

21

Reserve Device SDR Repository

Sensor/Event

04, 05

22

Get Sensor Reading Factors

Sensor/Event

04, 05

23

Set Sensor Hysteresis

Sensor/Event

04, 05

24

Get Sensor Hysteresis

Sensor/Event

04, 05

25

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System Management:

Command:

Standard Commands

(continued)

Set Sensor Thresholds

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ATCA-9305 User’s Manual

netFn:

LUN:

Cmd:

Sensor/Event

04, 05

26

Get Sensor Thresholds

Sensor/Event

04, 05

27

Set Sensor Event Enable

Sensor/Event

04, 05

28

Get Sensor Event Enable

Sensor/Event

04, 05

29

Rearm Sensor Events

Sensor/Event

04, 05

2A
2B

Get Sensor Event Status

Sensor/Event

04, 05

Get Sensor Reading

Sensor/Event

04, 05

2D

Set Sensor Type

Sensor/Event

04, 05

2E

Get Sensor Type

Sensor/Event

04, 05

2F

Get Device ID

Application

06, 07

01

Broadcast 'Get Device ID'

Application

06, 07

01

Cold Reset

Application

06, 07

02

Warm Reset

Application

06, 07

03

Get Self Test Results

Application

06, 07

04

Get Device GUID

Application

06, 07

08

Reset Watchdog Timer

Application

06, 07

22

Set Watchdog Timer

Application

06, 07

24

Get Watchdog Timer

Application

06, 07

25

Send Message

Application

06, 07

34

Get FRU Inventory Area Info

Storage

0A, 0B

10

Read FRU Data

Storage

0A, 0B

11

Write FRU Data

Storage

0A, 0B

12

Get PICMG Properties

PICMG

2C, 2D

00

Get Address Info

PICMG

2C, 2D

01

FRU Control

PICMG

2C, 2D

04

Get FRU LED Properties

PICMG

2C, 2D

05

Get LED Color Capabilities

PICMG

2C, 2D

06

Set FRU LED State

PICMG

2C, 2D

07

Get FRU LED State

PICMG

2C, 2D

08

Set IPMB State

PICMG

2C, 2D

09

Set FRU Activation Policy

PICMG

2C, 2D

0A

Get FRU Activation Policy

PICMG

2C, 2D

0B

Set FRU Activation

PICMG

2C, 2D

0C

Get Device Locator Record ID

PICMG

2C, 2D

0D

Set Port State

PICMG

2C, 2D

0E

Get Port State

PICMG

2C, 2D

0F

Compute Power Properties

PICMG

2C, 2D

10

Set Power Level

PICMG

2C, 2D

11

10009109-01

System Management:

Command:

OEM Boot Options

(continued)

netFn:

LUN:

Cmd:

Get Power Level

PICMG

2C, 2D

12

Bused Resource
(Release, Query, Force, Bus Free)

PICMG

2C, 2D

17

The IPMC implements many standard IPMI commands. For example, software can use the
watchdog timer commands to monitor the system’s health. Normally, the software resets
the watchdog timer periodically to prevent it from expiring. The IPMI specification allows
for different actions such as reset, power off, and power cycle, to occur if the timer expires.
The watchdog’s ‘timer use’ fields can keep track of which software (Operating System, System Management, etc.) started the timer. Also, the time-out action and ‘timer use’ information can be logged automatically to the System Event Log (SEL) when the time-out
occurs. Refer to the IPMI specification (listed in Table 1-2) for details about each command’s
request and response data. The IPMC also implements ATCA commands, see the ATCA Base
Specification (PICMG 3.0).

OEM BOOT OPTIONS
The Set System Boot Options and Get System Boot Options commands provide a means to
set/retrieve the boot options. The IPMI specification defines a set of standard boot option
parameters. In addition, the specification includes a range of numbers (96-127) for OEM
extensions. Emerson utilizes this area for OEM function extensions, such as boot bank selection and POST configuration. The following table describes these extensions:
Table 7-6: Emerson Boot Option Parameters

Parameter:

#

Parameter Data:

Boot Bank
(non-volatile)

96

data 1 — Set Selector. This is the processor ID for which the
boot option is to be set.
data 2 — Boot Bank Selector. This parameter is used to
indicate the boot bank from which the payload will boot.
00h = Primary (i.e., default) Boot Bank is selected.
01h = Secondary Boot Bank is selected.
02h-FFh = unused

POST Type
(non-volatile)

97

data 1 — Set Selector. This is the processor ID for which the
boot option is to be set.
data 2 — PSOT Type Selector. This parameter is used to
specify the POST type that the payload boot firmware will
execute.
00h = Short POST
01h = Long POST
02h-FFh = unused

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ATCA-9305 User’s Manual

7-11

System Management:

IPMC Watchdog Timer Commands

IPMC WATCHDOG TIMER COMMANDS
The IPMC implements a standardized ‘Watchdog Timer’ that can be used for a number of
system time-out functions by System Management Software (SMS) or by the monitor. Setting a time-out value of zero allows the selected time-out action to occur immediately. This
provides a standardized means for devices on the IPMB to perform emergency recovery
actions.
Table 7-7: IPMC Watchdog Timer Commands

Command:

See Page:

Optional/Mandatory:

Reset Watchdog Timer

7-14

M

Set Watchdog Timer

7-14

M

Get Watchdog Timer

7-16

M

Watchdog Timer Actions
The following actions are available on expiration of the Watchdog Timer:
• System Reset
• System Power Off
The System Reset and System Power Off on time-out selections are mutually exclusive. The
watchdog timer is stopped whenever the system is powered down. A command must be
sent to start the timer after the system powers up.

Watchdog Timer Use Field and Expiration Flags
The watchdog timer provides a ‘timer use’ field that indicates the current use assigned to
the watchdog timer. The watchdog timer provides a corresponding set of ‘timer use expiration’ flags that are used to track the type of time-out(s) that had occurred.
The time-out use expiration flags retain their state across system resets and power cycles, as
long as the IPMC remains powered. The flags are normally cleared solely by the Set Watchdog Timer command; with the exception of the “don’t log” flag, which is cleared after every
system hard reset or timer time-out.
The Timer Use fields indicate:
Monitor FRB-2 Time-out:
A Fault-resilient Booting, level 2 (FRB-2) time-out has occurred. This indicates that the last
system reset or power cycle was due to the system time-out during POST, presumed to be
caused by a failure or hang related to the bootstrap processor.

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ATCA-9305 User’s Manual

10009109-01

System Management:

IPMC Watchdog Timer Commands

Monitor POST Time-out:
In this mode, the time-out occurred while the watchdog timer was being used by the monitor for some purpose other than FRB-2 or OS Load Watchdog.
OS Load Time-out: The last reset or power cycle was caused by the timer being used to ‘watchdog’ the interval
from ‘boot’ to OS up and running. This mode requires system management software, or OS
support. The monitor should clear this flag if it starts this timer during POST.
SMS ‘OS Watchdog’ Time-out:
This indicates that the timer was being used by System Management Software (SMS). During run-time, SMS starts the timer, then periodically resets it to keep it from expiring. This
periodic action serves as a ‘heartbeat’ that indicates that the OS (or at least the SMS task) is
still functioning. If SMS hangs, the timer expires and the IPMC generates a system reset.
When SMS enables the timer, it should make sure the ‘SMS’ bit is set to indicate that the
timer is being used in its ‘OS Watchdog’ role.
OEM: This indicates that the timer was being used for an OEM-specific function.
Using the Timer Use Field and Expiration Flags
The software that sets the Timer Use field is responsible for managing the associated Timer
Use Expiration flag. For example, if System Management Software (SMS) sets the timer use
to “SMS/OS Watchdog,” then that same SMS is responsible for acting on and clearing the
associated Timer Use Expiration flag.
In addition, software should only interpret or manage the expiration flags for watchdog
timer uses that it set. For example, the monitor should not report watchdog timer expirations or clear the expiration flags for non-monitor uses of the timer. This is to allow the software that did set the Timer Use to see that a matching expiration occurred.

Watchdog Timer Event Logging
By default, the IPMC will automatically log the corresponding sensor-specific watchdog sensor event when a timer expiration occurs. A “don’t log” bit is provided to temporarily disable
the automatic logging. The “don’t log” bit is automatically cleared (logging re-enabled)
whenever a timer expiration occurs.
Monitor Support for Watchdog Timer
If a system “Warm Reset” occurs, the watchdog timer may still be running while the monitor executes POST. Therefore, the monitor should take steps to stop or restart the watchdog
timer early in POST. Otherwise, the timer may expire later during POST or after the OS has
booted.

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ATCA-9305 User’s Manual

7-13

System Management:

IPMC Watchdog Timer Commands

Reset Watchdog Timer Command
The Reset Watchdog Timer command is used for starting and restarting the Watchdog
Timer from the initial countdown value that was specified in the Set Watchdog Timer command.
If a pretime-out interrupt has been configured, the Reset Watchdog Timer command will
not restart the timer once the pretime-out interval has been reached. The only way to stop
the timer once it has reached this point is via the Set Watchdog Timer command.
Table 7-8: Reset Watchdog Timer Command

Type:

Byte:

Data Field:

Request Data

—

—

Response Data

1

Completion Code

Set Watchdog Timer Command
The Set Watchdog Timer command is used for initializing and configuring the watchdog
timer. The command is also used for stopping the timer.
If the timer is already running, the Set Watchdog Timer command stops the timer (unless
the “don’t stop” bit is set) and clears the Watchdog pretime-out interrupt flag (see Get Message Flags command in the IPMI specification v1.5). IPMC hard resets, system hard resets,
and the Cold Reset command also stop the timer and clear the flag.
Byte 1: This selects the timer use and configures whether an event will be logged on expiration.
Byte 2: This selects the time-out action and pretime-out interrupt type.
Byte 3: This sets the pretime-out interval. If the interval is set to zero, the pretime-out action occurs
concurrently with the time-out action.
Byte 4: This clears the Timer Use Expiration flags. A bit set in byte 4 of this command clears the corresponding bit in byte 5 of the Get Watchdog Timer command.
Bytes 5 and 6: These hold the least significant and most significant bytes, respectfully, of the countdown
value. The Watchdog Timer decrement is one count/100 ms. The counter expires when the
count reaches zero. If the counter is loaded with zero and the Reset Watchdog command is
issued to start the timer, the associated timer events occur immediately.

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ATCA-9305 User’s Manual

10009109-01

System Management:

IPMC Watchdog Timer Commands

Table 7-9: Set Watchdog Timer Command

Type:

Byte:

Data Field:

Request Data

1

Timer Use
[7] 1b=don’t log
[6] 1b=the don’t stop timer on Set Watchdog Timer command
(new for IPMI v1.5) new parameters take effect
immediately. If timer is already running, countdown value
will get set to given value and countdown will continue
from that point. If timer is already stopped, it will remain
stopped. If the pretime-out interrupt bit is set, it will get
cleared.1
0b=timer stops automatically when Set Watchdog Timer
command is received
[5:3] reserved
[2:0] timer use (logged on expiration when “don’t log” bit = 0b)
000b=reserved
001b=Monitor FRB-2
010b=Monitor/POST
011b=OS Load
100b=SMS/OS
101b=OEM
110b-111b=reserved

2

Timer Actions
[7] reserved
[6:4] pretime-out interrupt (logged on expiration when “don’t
log” bit = 0b)
000b=none
001b=SMI
010b=NMI/Diagnostic Interrupt
011b=Messaging Interrupt (this is the same interrupt as
allocated to the messaging interface)
100b, 111b =reserved
[3] reserved
[2:0] time-out action
000b=no action
001b=Hard Reset
010b=Power Down
011b=Power Cycle
100b, 111b=reserved

3

Pretime-out interval in seconds, ‘1’ based

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ATCA-9305 User’s Manual

7-15

System Management:

IPMC Watchdog Timer Commands

Type:

Byte:

Data Field: (continued)

Request Data
(continued)

4

Timer Use Expiration flags clear
(0b=leave alone, 1b=clear timer use expiration bit)
[7] reserved
[6] reserved
[5] OEM
[4] SMS/OS
[3] OS Load
[2] Monitor/POST
[1] Monitor FRB-2
[0] reserved

5

Initial countdown value, lsbyte (100 ms/count)

6

Initial countdown value, msbyte

1

Completion Code

Response Data

1. Potential race conditions exist with implementation of this option. If the Set Watchdog Timer command is
sent just before a pretime-out interrupt or time-out is set to occur, the time-out could occur before the
command is executed. To avoid this condition, it is recommended that software set this value no closer
than three counts before the pretime-out or time-out value is reached.

Get Watchdog Timer Command
This command retrieves the current settings and present countdown of the watchdog
timer. The Timer Use Expiration flags in byte 5 retain their states across system resets and
system power cycles. With the exception of bit 6 in the Timer Use byte, the Timer Use Expiration flags are cleared using the Set Watchdog Timer command. They may also become
cleared because of a loss of IPMC power, firmware update, or other cause of IPMC hard
reset. Bit 6 of the Timer Use byte is automatically cleared to 0b whenever the timer times
out, is stopped when the system is powered down, enters a sleep state, or is reset.
Table 7-10: Get Watchdog Timer Command

7-16

ATCA-9305 User’s Manual

Type:

Byte:

Data Field:

Request Data

—

—

Response Data

1

Completion Code

10009109-01

System Management:

IPMC Watchdog Timer Commands

Type:

Byte:

Data Field: (continued)

Response Data

2

Timer Use
[7] 1b=don’t log
[6] 1b=timer is started (running)
0b=timer is stopped
[5:3] reserved
[2:0] timer use (logged on expiration if “don’t log” bit = 0)
000b=reserved
001b=Monitor FRB-2
010b=Monitor/POST
011b=OS Load
100b=SMS/OS
101b=OEM
110b, 111b=reserved

3

Timer Actions
[7] reserved
[6:4] pretime-out interrupt
000b=none
001b=SMI
010b=NMI/Diagnostic Interrupt
011b=Messaging Interrupt (this would be the same interrupt
as allocated to the messaging interface)
100b, 111b =reserved
[3] reserved
[2:0] time-out action
000b=no action
001b=Hard Reset
010b=Power Down
011b=Power Cycle
100b, 111b=reserved

4

Pretime-out interval in seconds, ‘1’based

5

Timer Use Expiration flags (1b=timer expired while associated ‘use’
was selected)
[7] reserved
[6] reserved
[5] OEM
[4] SMS/OS
[3] OS Load
[2] Monitor/POST
[1] Monitor FRB-2
[0] reserved

6

Initial countdown value, lsbyte (100 ms/count)

7

Initial countdown, msbyte

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ATCA-9305 User’s Manual

7-17

System Management:

FRU LEDs

Type:

Byte:

Data Field: (continued)

Response Data

8

Present countdown value, lsbyte. The initial countdown value and
present countdown values should match immediately after the
countdown is initialized via a Set Watchdog Timer command and
after a Reset Watchdog Timer has been executed.
Note that internal delays in the IPMC may require software to delay
up to 100 ms before seeing the countdown value change and be
reflected in the Get Watchdog Timer command.

9

Present countdown value, msbyte

FRU LEDS
This section describes the front panel LEDs controlled by the IPMC and documents how to
control each LED with the standard FRU LED commands. Reference the PICMG® 3.0 Revision
2.0 AdvancedTCA® Base Specification for more detailed information.
The ATCA-9305 has four Light-Emitting Diodes (LEDs) on the front panel. See Fig. 2-1 for
their location.
Table 7-11: FRU LEDs

ID
(hex):

Reference
Designator:

Hot
Swap

00

CR57

The blue Hot Swap LED displays four states:
On—the board can be safely extracted
Off—the board is operating and not safe for
extraction,
Long blink—insertion is in progress
Short blink—requesting permission for
extraction

OOS

01

CR54

The Out Of Service programmable LED
controlled by the IPMI controller is either red
(North America) or amber (Europe). When lit,
this LED indicates the ATCA-9305 is in a failed
state.

2

02

CR55

The green LED is user defined, but frequently is
used as an In Service indicator. When used as an
In Service indicator, a lit LED indicates that the
ATCA-9305 is functioning properly.

3

03

CR56

The amber LED is user defined.

LEDs:

7-18

ATCA-9305 User’s Manual

10009109-01

Description:

System Management:

FRU LEDs

Get FRU LED Properties Command
This command allows software to determine which LEDs are under IPMC control.
Table 7-12: Get FRU LED Properties Command

Type:

Byte:

Data Field:

Request Data

1

PICMG Identifier—indicates that this is a PICMG defined group
extension command. Use value 00h.

2

FRU Device ID

Response Data

1

Completion Code

2

PICMG Identifier—indicates that this is a PICMG defined group
extension command. Use value 00h.

3

General Status LED Properties—indicates the FRU’s ability to control
the four general status LEDs. When a bit is set, the FRU can control
the associated LED.
Bits [7:4] reserved, set to 0
Bit [3] LED3
Bit [2] LED2
Bit [1] LED1
Bit [0] Blue LED

4

Application Specific LED Count—is the number of application
specific LEDs under IPMC control.
00h-FBh Number of application-specific LEDs under IPMC
control. If none are present, this field is 00h.
FCh-FFh reserved

Get LED Color Capabilities Command
LED 1 can be either red or amber, this command is used to determine the valid color prior to
issuing a Set FRU LED State command.
Table 7-13: Get LED Color Capabilities Command

Type:

Byte:

Data Field:

Request Data

1

PICMG Identifier—indicates that this is a PICMG defined group
extension command. Use value 00h.

2

FRU Device ID

3

LED ID
FFh reserved

10009109-01

ATCA-9305 User’s Manual

7-19

System Management:

7-20

ATCA-9305 User’s Manual

FRU LEDs

Type:

Byte:

Data Field: (continued)

Response Data

1

Completion Code
CCh If the LED ID contained in the Request data is not present
on the FRU

2

PICMG Identifier—indicates that this is a PICMG defined group
extension command. Use value 00h.

3

LED Color Capabilities—when a bit is set, the LED supports the
color.
Bit [7] reserved, set to 0
Bit [6] LED supports white
Bit [5] LED supports orange
Bit [4] LED supports amber
Bit [3] LED supports green
Bit [2] LED supports red
Bit [1] LED supports blue
Bit [0] reserved, set to 0

4

Default LED Color in Local Control State
Bit [7] reserved, set to 0
Bits [3:0]
0h reserved
1h Blue
2h Red
3h Green
4h Amber
5h Orange
6h White
7h-Fh reserved

5

Default LED Color in Override State
Bit [7] reserved, set to 0
Bits [3:0]
0h reserved
1h Blue
2h Red
3h Green
4h Amber
5h Orange
6h White
7h-Fh reserved

10009109-01

System Management:

FRU LEDs

Set FRU LED State Command
The Set FRU LED State command allows the state of the FRU LEDs to be controlled by the
management system.
Table 7-14: Set FRU LED State Command

Type:

Byte:

Data Field:

Request Data

1

PICMG Identifier—indicates that this is a PICMG defined group
extension command. Use value 00h.

2

FRU Device ID

3

LED ID
00h Blue LED (Hot Swap)
01h LED 1 (OOS)
02h LED 2
03h LED 3
04h-FEh OEM defined LEDs
FFh Lamp Test (all LEDs under management control are
addressed)

4

LED Function
00h LED off override
01h-FAh LED blinking override
FBh Lamp Test state Turn on LED specified in byte 3 for the
duration specified in byte 5, then return to the highest
priority state.
FCh LED state restored to Local Control state
FDh-FEh reserved
FFh LED on override

5

On Duration
LED on-time is measured in tens of milliseconds
Lamp Test time in hundreds of milliseconds if byte 4=FBh, time
value must be less than 128. Other values when Byte 4=FBh are
reserved. Otherwise, this field is ignored and shall be set to 0h.

10009109-01

ATCA-9305 User’s Manual

7-21

System Management:

FRU LEDs

Type:

Byte:

Data Field: (continued)

Request Data

6

Color When Illuminated—sets the override color when LED Function
is 01h-FAh and FFh. This byte sets the Local Control color when LED
Function is FCh. This byte may be ignored during Lamp Test or may
be used to control the color during the lamp test when LED
Function is FBh.
Bits [7:4] reserved, set to 0
Bits [3:0]
0h reserved
1h Use Blue
2h Use Red
3h Use Green
4h Use Amber
5h Use Orange
6h Use White
7h-Dh reserved
Eh Do not change
Fh Use default color

Response Data

1

Completion Code

2

PICMG Identifier—indicates that this is a PICMG defined group
extension command. Use value 00h.

Get FRU LED State Command
The Get FRU LED State command allows the state of the FRU LEDs to be controlled by the
management system.
Table 7-15: Get FRU LED State Command

Type:

Byte:

Data Field:

Request Data

1

PICMG Identifier—indicates that this is a PICMG defined group
extension command. Use value 00h.

2

FRU Device ID

3

LED ID
00h Blue LED (Hot Swap)
01h LED 1 (OOS)
02h LED 2
03h LED 3
04h-FEh OEM defined LEDs
FFh reserved

Response Data

7-22

ATCA-9305 User’s Manual

1

Completion Code

2

PICMG Identifier—indicates that this is a PICMG defined group
extension command. Use value 00h.

10009109-01

System Management:

FRU LEDs

Type:

Byte:

Data Field: (continued)

Response Data

3

LED States
Bits [7:3] reserved, set to 0
Bit [2] 1b if Lamp Test has been enabled
Bit [1] 1b if override state has been enabled
Bit [2] 1b if IPMC has a Local control state

4

Local Control LED Function
00h LED is off (default if Local Control not supported)
01h-FAh LED is blinking Off duration specified by this byte,
on duration specified by byte 5 (in tens of
milliseconds)
FBh-FEh reserved
FFh LED is on

5

On Duration
LED on-time is measured in tens of milliseconds
Lamp Test time in hundreds of milliseconds if byte 4=FBh, time
value must be less than 128. Other values when Byte 4=FBh are
reserved. Otherwise, this field is ignored and shall be set to 0h.

6

Local Control Color
Bits [7:4] reserved, set to 0
Bits [3:0]
0h reserved
1h Blue
2h Red
3h Green
4h Amber
5h Orange
6h White
7h-Fh reserved

7

Override State LED Function—is required if either override state or
Lamp Test is in effect.
00h LED override state is off
01h-FAh LED override state is blinking Off duration is
specified by this byte, on duration specified by
byte 8 (in tens of milliseconds)
FBh-FEh reserved
FFh LED override state is on

8

Override State On Duration—is required if either override state or
Lamp Test is in effect (in tens of milliseconds).

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ATCA-9305 User’s Manual

7-23

System Management:

Type:
Response Data

Vendor Commands

Byte:

Data Field: (continued)

9

Override State Color
Bits [7:4] reserved, set to 0
Bits [3:0]
0h reserved
1h Blue
2h Red
3h Green
4h Amber
5h Orange
6h White
7h-Fh reserved

10

Lamp Test Duration—is optional if Lamp Test is not in effect
(hundreds of milliseconds).

VENDOR COMMANDS
The IPMC supports additional IPMI commands that are specific to Pigeon Point and/or
Emerson. This section provides detailed descriptions of those extension or SIPL commands.
Table 7-16: Vendor Command Summary

7-24

ATCA-9305 User’s Manual

Command:

netFn:

LUN:

Cmd:

Get Status

OEM

2E, 2F

00

Get Serial Interface Properties

OEM

2E, 2F

01

Set Serial Interface Properties

OEM

2E, 2F

02

Get Debug Level

OEM

2E, 2F

03

Set Debug Level

OEM

2E, 2F

04

Get Hardware Address

OEM

2E, 2F

05

Set Hardware Address

OEM

2E, 2F

06

Get Handle Switch

OEM

2E, 2F

07

Set Handle Switch

OEM

2E, 2F

08

Get Payload Communication Time-Out

OEM

2E, 2F

09

Set Payload Communication Time-Out

OEM

2E, 2F

0A

Enable Payload Control

OEM

2E, 2F

0B

Disable Payload Control

OEM

2E, 2F

0C

Reset IPMC

OEM

2E, 2F

0D

Hang IPMC

OEM

2E, 2F

0E

Bused Resource Control

OEM

2E, 2F

0F

Bused Resource Status

OEM

2E, 2F

10

Graceful Reset

OEM

2E, 2F

11

Diagnostic Interrupt Results

OEM

2E, 2F

12

Get Payload Shutdown Time-Out

OEM

2E, 2F

15

Set Payload Shutdown Time-Out

OEM

2E, 2F

16

10009109-01

System Management:

Command:

Vendor Commands

(continued)

Set Local FRU LED State

netFn:

LUN:

Cmd:

OEM

2E, 2F

18

Get Local FRU LED State

OEM

2E, 2F

19

Update Discrete Sensor

OEM

2E, 2F

1A
1B

Update Threshold Sensor

OEM

2E, 2F

Reserved for Message Listeners

OEM

30, 31

10

Add Message Listener

OEM

30, 31

11

Remove Message Listener

OEM

30, 31

12

Get Message Listener List

OEM

30, 31

13

Update Firmware Progress Sensor

OEM

30, 31

F0

Get Status
The IPMC firmware notifies the payload about changes of all status bits except for bits 0-2
by sending an unprintable character (ASCII 07, BELL) over the Payload Interface. The payload is expected to use the Get Status command to identify pending events and other SIPL
commands to provide a response (if necessary). The event notification character is sent in a
synchronous manner, and does not appear in the contents of SIPL messages sent to the payload.
Table 7-17: Get Status Command

Type:

Byte:

Data Field:

Request Data

1:3

PPS IANA Private Enterprise ID, MS Byte first
0x00400A = 16394 (Pigeon Point Systems)

Response Data

1

Completion Code

2:4

PPS IANA Private Enterprise ID, MS Byte first
0x00400A = 16394 (Pigeon Point Systems)

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ATCA-9305 User’s Manual

7-25

System Management:

7-26

ATCA-9305 User’s Manual

Vendor Commands

(continued)

Type:

Byte:

Data Field:

Response Data

5

Bit [7] Graceful Reboot Request
If set to 1, indicates that the payload is requested to initiate the
graceful reboot sequence
Bit [6] Diagnostic Interrupt Request
If set to 1, indicates that a payload diagnostic interrupt request
has arrived
Bit [5] Shutdown Alert
If set to 1, indicates that the payload is going to be shutdown
Bit [4] Reset Alert
If set to 1, indicates that the payload is going to be reset
Bit [3] Sensor Alert
If set to 1, indicates that at least one of the IPMC sensors detects
threshold crossing
Bits [2:1] Mode
The current IPMC modes are defined as:
0 Normal
1 Standalone
2 Manual Standalone
Bit [0] Control
If set to 0, the IPMC control over the payload is disabled

6

Bits [4:7] Metallic Bus 2 Events
These bits indicate pending Metallic Bus 2 requests arrived from
the carrier controller:
0 Metallic Bus 2 Query
1 Metallic Bus 2 Release
2 Metallic Bus 2 Force
3 Metallic Bus 2 Free
Bits [0:3] Metallic Bus 1 Events
These bits indicate pending Metallic Bus 1 requests arrived from
the carrier controller:
0 Metallic Bus 1 Query
1 Metallic Bus 1 Release
2 Metallic Bus 1 Force
3 Metallic Bus 1 Free

10009109-01

System Management:

Vendor Commands

(continued)

Type:

Byte:

Data Field:

Response Data

7

Bits [4:7] Clock Bus 2 Events
These bits indicate pending Clock Bus 2 requests arrived from
the carrier controller:
0 Clock Bus 2 Query
1 Clock Bus 2 Release
2 Clock Bus 2 Force
3 Clock Bus 2 Free
Bits [0:3] Clock Bus 1 Events
These bits indicate pending Clock Bus 1 requests arrived from
the carrier controller:
0 Clock Bus 1 Query
1 Clock Bus 1 Release
2 Clock Bus 1 Force
3 Clock Bus 1 Free

8

Bits [4:7] reserved
Bits [0:3] Clock Bus 3 Events
These bits indicate pending Clock Bus 3 requests arrived from
the carrier controller:
0 Clock Bus 3 Query
1 Clock Bus 3 Release
2 Clock Bus 3 Force
3 Clock Bus 3 Free

Get Serial Interface Properties
The Get Serial Interface Properties command is used to get the properties of a particular
serial interface.
Table 7-18: Get Serial Interface Properties Command

Type:

Byte:

Data Field:

Request Data

1:3

PPS IANA Private Enterprise ID, MS Byte first
0x00400A = 16394 (Pigeon Point Systems)

4

Interface ID
0 Serial Debug Interface
1 Payload Interface

1

Completion Code

2:4

PPS IANA Private Enterprise ID, MS Byte first
0x00400A = 16394 (Pigeon Point Systems)

Response Data

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7-27

System Management:

Vendor Commands

(continued)

Type:

Byte:

Data Field:

Response Data

5

Bit [7] Echo On
If this bit is set, the IPMC enables echo for the given serial
interface
Bits [6:4] reserved
Bits [3:0] Baud Rate ID
The baud rate ID defines the interface baud rate as follows:
0 9600 bps
1 19200 bps
2 38400 bps
3 57600 bps (unsupported)
4 115200 bps (unsupported)

Set Serial Interface Properties
The Set Serial Interface Properties command is used to set the properties of a particular
serial interface.
Table 7-19: Set Serial Interface Properties Command

Type:

Byte:

Data Field:

Request Data

1:3

PPS IANA Private Enterprise ID, MS Byte first
0x00400A = 16394 (Pigeon Point Systems)

4

Interface ID
0 Serial Debug Interface
1 Payload Interface

5

Bit [7] Echo On
If this bit is set, the IPMC enables echo for the given serial
interface
Bits [6:4] reserved
Bits [3:0] Baud Rate ID
The baud rate ID defines the interface baud rate as follows:
0 9600 bps
1 19200 bps
2 38400 bps
3 57600 bps (unsupported)
4 115200 bps (unsupported)

Response Data

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ATCA-9305 User’s Manual

1

Completion Code

2:4

PPS IANA Private Enterprise ID, MS Byte first
0x00400A = 16394 (Pigeon Point Systems)

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System Management:

Vendor Commands

Get Debug Level
The Get Debug Level command gets the current debug level of the IPMC firmware.
Table 7-20: Get Debug Level Command

Type:

Byte:

Data Field:

Request Data

1:3

PPS IANA Private Enterprise ID, MS Byte first
0x00400A = 16394 (Pigeon Point Systems)

Response Data

1

Completion Code

2:4

PPS IANA Private Enterprise ID, MS Byte first
0x00400A = 16394 (Pigeon Point Systems)

5

Bits [7:5] reserved
Bit [4] IPMB Dump Enable
If set to 1, the IPMC provides a trace of IPMB messages that are
arriving to/going from the IPMC via IPMB-0 or IPMB -L
Bit [3] Payload Logging Enable
If set to 1, the IPMC provides a trace of SIPL activity on the
Payload interface onto the Serial Debug interface
Bit [2] Alert Logging Enable
If set to 1, the IPMC outputs important alert messages onto the
Serial Debug interface
Bit [1] Low-level Error Logging Enable
If set to 1, the IPMC outputs low-level error/diagnostic messages
onto the Serial Debug interface
Bit [0] Error Logging Enable
If set to 1, the IPMC outputs error/diagnostic messages onto the
Serial Debug interface

Set Debug Level
The Set Debug Level command sets the current debug level of the IPMC firmware.
Table 7-21: Set Debug Level Command

Type:

Byte:

Data Field:

Request Data

1:3

PPS IANA Private Enterprise ID, MS Byte first
0x00400A = 16394 (Pigeon Point Systems)

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7-29

System Management:

Vendor Commands

(continued)

Type:

Byte:

Data Field:

Request Data

4

Bits [7:5] reserved
Bit [4] IPMB Dump Enable
If set to 1, the IPMC provides a trace of IPMB messages that are
arriving to/going from the IPMC via IPMB-0 or IPMB-L
Bit [3] Payload Logging Enable
If set to 1, the IPMC provides a trace of SIPL activity on the
Payload interface onto the Serial Debug interface
Bit [2] Alert Logging Enable
If set to 1, the IPMC outputs important alert messages onto the
Serial Debug interface
Bit [1] Low-level Error Logging Enable
If set to 1, the IPMC outputs low-level error/diagnostic
messages onto the Serial Debug interface
Bit [0] Error Logging Enable
If set to 1, the IPMC outputs error/diagnostic messages onto the
Serial Debug interface

Response Data

1

Completion Code

2:4

PPS IANA Private Enterprise ID, MS Byte first
0x00400A = 16394 (Pigeon Point Systems)

Get Hardware Address
The Get Hardware Address command reads the hardware address of the IPMC.
Table 7-22: Get Hardware Address Command

Type:

Byte:

Data Field:

Request Data

1:3

PPS IANA Private Enterprise ID, MS Byte first
0x00400A = 16394 (Pigeon Point Systems)

Response Data

1

Completion Code

2:4

PPS IANA Private Enterprise ID, MS Byte first
0x00400A = 16394 (Pigeon Point Systems)

5

Hardware Address

Set Hardware Address
The Set Hardware Address command allows overriding of the hardware address read from
hardware when the IPMC operates in (Manual) Standalone mode.
Table 7-23: Set Hardware Address Command

7-30

ATCA-9305 User’s Manual

Type:

Byte:

Data Field:

Request Data

1:3

PPS IANA Private Enterprise ID, MS Byte first
0x00400A = 16394 (Pigeon Point Systems)

10009109-01

System Management:

Type:

Vendor Commands

(continued)

Byte:

Data Field:

4

Hardware Address
If set to 00, the ability to override the hardware address is
disabled
NOTE: A hardware address change only takes effect after an
IPMC reset. See “Reset IPMC” on page 7-33.

Response Data

1

Completion Code

2:4

PPS IANA Private Enterprise ID, MS Byte first
0x00400A = 16394 (Pigeon Point Systems)

Get Handle Switch
The Get Handle Switch command reads the state of the Hot Swap handle of the IPMC. Overriding of the handle switch state is allowed only if the IPMC operates in (Manual) Standalone
mode.
Table 7-24: Get Handle Switch Command

Type:

Byte:

Data Field:

Request Data

1:3

PPS IANA Private Enterprise ID, MS Byte first
0x00400A = 16394 (Pigeon Point Systems)

Response Data

1

Completion Code

2:4

PPS IANA Private Enterprise ID, MS Byte first
0x00400A = 16394 (Pigeon Point Systems)

5

Handle Switch Status
0x00 The handle switch is open
0x01 The handle switch is closed
0x02 The handle switch state is read from hardware

Set Handle Switch
The Set Handle Switch command sets the state of the Hot Swap handle switch in (Manual)
Standalone mode.
Table 7-25: Set Handle Switch Command

Type:

Byte:

Data Field:

Request Data

1:3

PPS IANA Private Enterprise ID, MS Byte first
0x00400A = 16394 (Pigeon Point Systems)

4

Handle Switch Status
0x00 The handle switch is open
0x01 The handle switch is closed
0x02 The handle switch state is read from hardware

Response Data

1

Completion Code

2:4

PPS IANA Private Enterprise ID, MS Byte first
0x00400A = 16394 (Pigeon Point Systems)

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7-31

System Management:

Vendor Commands

Get Payload Communication Time-Out
The Get Payload Communication Time-Out command reads the payload communication
time-out value.
Table 7-26: Get Payload Communication Time-Out Command

Type:

Byte:

Data Field:

Request Data

1:3

PPS IANA Private Enterprise ID, MS Byte first
0x00400A = 16394 (Pigeon Point Systems)

Response Data

1

Completion Code

2:4

PPS IANA Private Enterprise ID, MS Byte first
0x00400A = 16394 (Pigeon Point Systems)

5

Payload Time-out
Payload communication time-out measured in hundreds of
milliseconds. Thus, the payload communication time-out
may vary from 0.1 to 25.5 seconds.

Set Payload Communication Time-Out
The Set Payload Communication Time-Out command sets the payload communication
time-out value.
Table 7-27: Set Payload Communication Time-Out Command

Type:

Byte:

Data Field:

Request Data

1:3

PPS IANA Private Enterprise ID, MS Byte first
0x00400A = 16394 (Pigeon Point Systems)

4

Payload Time-out
Payload communication time-out measured in hundreds of
milliseconds. Thus, the payload communication time-out
may vary from 0.1 to 25.5 seconds.

Response Data

1

Completion Code

2:4

PPS IANA Private Enterprise ID, MS Byte first
0x00400A = 16394 (Pigeon Point Systems)

Enable Payload Control
The Enable Payload Control command enables payload control from the Serial Debug interface.
Table 7-28: Enable Payload Control Command

Type:

Byte:

Data Field:

Request Data

1:3

PPS IANA Private Enterprise ID, MS Byte first
0x00400A = 16394 (Pigeon Point Systems)

Response Data

7-32

ATCA-9305 User’s Manual

1

Completion Code

2:4

PPS IANA Private Enterprise ID, MS Byte first
0x00400A = 16394 (Pigeon Point Systems)

10009109-01

System Management:

Vendor Commands

Disable Payload Control
The Disable Payload Control command disables payload control from the Serial Debug
interface.
Table 7-29: Disable Payload Control Command

Type:

Byte:

Data Field:

Request Data

1:3

PPS IANA Private Enterprise ID, MS Byte first
0x00400A = 16394 (Pigeon Point Systems)

Response Data

1

Completion Code

2:4

PPS IANA Private Enterprise ID, MS Byte first
0x00400A = 16394 (Pigeon Point Systems)

Reset IPMC
The Reset IPMC command allows the payload to reset the IPMC over the SIPL.
Table 7-30: Reset IPMC Command

Type:

Byte:

Data Field:

Request Data

1:3

PPS IANA Private Enterprise ID, MS Byte first
0x00400A = 16394 (Pigeon Point Systems)

4

Reset Type Code
0x00 Cold IPMC reset to the current mode
0x01 Cold IPMC reset to the Normal mode
0x02 Cold IPMC reset to the Standalone mode
0x03 Cold IPMC reset to the Manual Standalone mode
0x04 Reset the IPMC and enter Upgrade mode

Response Data

1

Completion Code

2:4

PPS IANA Private Enterprise ID, MS Byte first
0x00400A = 16394 (Pigeon Point Systems)

Hang IPMC
The IPMC provides a means to test the watchdog timer support by implementing the Hang
IPMC command, which simulates firmware hanging by entering an endless loop.
Table 7-31: Hang IPMC Command

Type:

Byte:

Data Field:

Request Data

1:3

PPS IANA Private Enterprise ID, MS Byte first
0x00400A = 16394 (Pigeon Point Systems)

Response Data

1

Completion Code

2:4

PPS IANA Private Enterprise ID, MS Byte first
0x00400A = 16394 (Pigeon Point Systems)

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7-33

System Management:

Vendor Commands

Bused Resource
To send a Bused Resource command to the carrier controller, the payload uses the Bused
Resource command of the SIPL.
Table 7-32: Bused Resource Command

Type:

Byte:

Data Field:

Request Data

1:3

PPS IANA Private Enterprise ID, MS Byte first
0x00400A = 16394 (Pigeon Point Systems)

4

Command Types for Carrier Controller to Board
0 Query if board has control of the bus
1 Release requests a board to release control of the bus
2 Force board to release control of bus immediately
3 Bus Free informs board that the bus is available
Command Types for Board to Carrier Controller
0 Request to seize control of the bus
1 Relinquish control of the bus, carrier controller can reassign
control of bus
2 Notify carrier controller that control of the bused resource has
been transferred to this board from another authorized board

5

Response Data

Bused Resource ID
0 Metallic Test Bus pair #1
1 Metallic Test Bus pair #2
2 Synch clock group 1 (CLK1A and CLK1B pairs)
3 Synch clock group 2 (CLK2A and CLK2B pairs)
3 Synch clock group 3 (CLK3A and CLK3B pairs)

1

Completion Code

2:4

PPS IANA Private Enterprise ID, MS Byte first
0x00400A = 16394 (Pigeon Point Systems)

5

Status
0 Ack; carrier controller acknowledges that board has control
1 Error; same as Ack, but carrier controller believes board should
not have been given control of the resource (optional)
2 Deny; carrier controller denies control of resource by the board

Bused Resource Status
If the IPMC receives a Bused Resource command from IPMB-0, it asserts an appropriate
event and notifies the payload which uses the Bused Resource Status command over the
SIPL. When the IPMC receives a Bused Resource Status command, the respective bit in the
IPMC status is cleared.
The payload must issue a Bused Resource Status command before the payload communication time-out time. If the payload does not issue such a command before the payload communication time-out time, the IPMC sends the 0xC3 completion code (Time-Out) in the
appropriate Bused Resource command reply.

7-34

ATCA-9305 User’s Manual

10009109-01

System Management:

Vendor Commands

Table 7-33: Bused Resource Status Command

Type:

Byte:

Data Field:

Request Data

1:3

PPS IANA Private Enterprise ID, MS Byte first
0x00400A = 16394 (Pigeon Point Systems)

4

Command Types for Carrier Controller to Board
0 Query if board has control of the bus
(0=In control, 1= No control)
1 Release request a board to release control of the bus
(0=Ack, 1=Refused, 2=No control)
2 Force board to release control of bus immediately
(0=Ack, 1=No control)
3 Bus Free informs board that the bus is available
(0=Accept, 1=Not needed)
Command Types for Board to Carrier Controller
0 Request to seize control of the bus
(0=Grant, 1=Busy, 2=Defer, 3=Deny)
1 Relinquish control of the bus, carrier controller can reassign
control of bus (0=Ack, 1=Error)
2 Notify carrier controller that control of the bused resource has
been transferred to this board from another authorized board
(0=Ack, 1=Error, 2=Deny)

Response Data

5

Bused Resource ID
0 Metallic Test Bus pair #1
1 Metallic Test Bus pair #2
2 Synch clock group 1 (CLK1A and CLK1B pairs)
3 Synch clock group 2 (CLK2A and CLK2B pairs)
4 Synch clock group 3 (CLK3A and CLK3B pairs)

6

Status
0 Ack; carrier controller acknowledges that board has control
1 Error; same as Ack, but carrier controller believes board should
not have been given control of the resource (optional)
2 Deny; carrier controller denies control of resource by the board

1

Completion Code

2:4

PPS IANA Private Enterprise ID, MS Byte first
0x00400A = 16394 (Pigeon Point Systems)

Graceful Reset
The IPMC supports the Graceful Reboot option of the FRU Control command. On receiving
such a command, the IPMC sets the Graceful Reboot Request bit of the IPMC status, sends a
status update notification to the payload, and waits for the Graceful Reset command from
the payload. If the IPMC receives such a command before the payload communication timeout time, it sends the 0x00 completion code (Success) to the carrier controller. Otherwise
the 0xC3 completion code (Time-Out) is sent.

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ATCA-9305 User’s Manual

7-35

System Management:

Vendor Commands

The IPMC does not reset the payload on receiving the Graceful Reset command or time-out.
If the IPMC participation is necessary, the payload must request the IPMC to perform a payload reset. The Graceful Reset command is also used to notify the IPMC about the completion of the payload shutdown sequence.
Table 7-34: Graceful Reset Command

Type:

Byte:

Data Field:

Request Data

1:3

PPS IANA Private Enterprise ID, MS Byte first
0x00400A = 16394 (Pigeon Point Systems)

Response Data

1

Completion Code

2:4

PPS IANA Private Enterprise ID, MS Byte first
0x00400A = 16394 (Pigeon Point Systems)

Diagnostic Interrupt Results
The IPMC supports the Issue Diagnostic Interrupt feature of the FRU Control command. The
payload is notified about a diagnostic interrupt over the SIPL. The payload is expected to
return diagnostic interrupt results before the payload communication time-out using the
Diagnostic Interrupt Results command of the SIPL.
Table 7-35: Diagnostic Interrupt Command

Type:

Byte:

Data Field:

Request Data

1:3

PPS IANA Private Enterprise ID, MS Byte first
0x00400A = 16394 (Pigeon Point Systems)

4

If the payload responds before the payload communication
time-out, the diagnostic interrupt return code is forwarded to the
carrier controller as the completion code of the FRU Control
command response. Otherwise, the 0xC3 completion code (TimeOut) is returned.

Response Data

1

Completion Code

2:4

PPS IANA Private Enterprise ID, MS Byte first
0x00400A = 16394 (Pigeon Point Systems)

Get Payload Shutdown Time-Out
When the carrier controller commands the IPMC to shut down the payload (i.e. sends the
Set Power Level (0) command), the IPMC notifies the payload by asserting an appropriate
alert and sending an alert notification to the payload. Upon receiving this notification, the
payload software is expected to initiate the payload shutdown sequence. After performing
this sequence, the payload should send the Graceful Reset command to the IPMC over the
Payload interface to notify the IPMC that the payload shutdown is complete.

7-36

ATCA-9305 User’s Manual

10009109-01

System Management:

Vendor Commands

To avoid deadlocks that may occur if the payload software does not respond, the IPMC provides a special time-out for the payload shutdown sequence. If the payload does not send
the Graceful Reset command within a definite period of time, the IPMC assumes that the
payload shutdown sequence is finished, and sends a Module Quiesced Hot Swap event to
the ATCA-9305 controller.
Table 7-36: Get Payload Shutdown Time-Out Command

Type:

Byte:

Data Field:

Request Data

1:3

PPS IANA Private Enterprise ID, MS Byte first
0x00400A = 16394 (Pigeon Point Systems)

Response Data

1

Completion Code

2:4

PPS IANA Private Enterprise ID, MS Byte first
0x00400A = 16394 (Pigeon Point Systems)

5:6

Time-Out measured in hundreds of milliseconds, LSB first

Set Payload Shutdown Time-Out
The Set Payload Shutdown Time-Out command is defined as follows:
Table 7-37: Set Payload Shutdown Time-Out Command

Type:

Byte:

Data Field:

Request Data

1:3

PPS IANA Private Enterprise ID, MS Byte first
0x00400A = 16394 (Pigeon Point Systems)

4:5

Time-Out measured in hundreds of milliseconds, LSB first

Response Data

1

Completion Code

2:4

PPS IANA Private Enterprise ID, MS Byte first
0x00400A = 16394 (Pigeon Point Systems)

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7-37

System Management:

Vendor Commands

Set Local FRU LED State
The Set Local FRU LED State command is used to change the local state of a FRU LED.
Table 7-38: Set Local FRU LED State Command

Type:

Byte:

Data Field:

Request Data

1:3

PPS IANA Private Enterprise ID, MS Byte first
0x00400A = 16394 (Pigeon Point Systems)

4

FRU Device ID

5

LED ID
00h Blue LED (Hot Swap)
01h LED 1 (OOS)
02h LED 2
03h LED 3
04h-FEh OEM defined LEDs
FFh Lamp Test (all LEDs under management control are
addressed)

6

LED Function
00h LED off override
01h-FAh LED blinking override
FBh Lamp Test state Turn on LED specified in byte 3 for the
duration specified in byte 5, then return to the highest
priority state.
FCh LED state restored to Local Control state
FDh-FEh reserved
FFh LED on override

7

On Duration
LED on-time is measured in tens of milliseconds
Lamp Test time in hundreds of milliseconds if byte 4=FBh, time
value must be less than 128. Other values when Byte 4=FBh are
reserved. Otherwise, this field is ignored and shall be set to 0h.

8

Color parameter specifies the color of the LED in the local state for
multi-color LEDs

9

If the off-first flag parameter is 0, the on part of the blink cycle of
the LED precedes the off part of the cycle. Otherwise, the off part
of the blink cycle precedes the on part of the cycle.

Response Data

7-38

ATCA-9305 User’s Manual

1

Completion Code

2:4

PPS IANA Private Enterprise ID, MS Byte first
0x00400A = 16394 (Pigeon Point Systems)

10009109-01

System Management:

Vendor Commands

Get Local FRU LED State
The Get Local FRU LED State command is used to read the local state of a FRU LED.
Table 7-39: Get Local FRU LED State Command

Type:

Byte:

Data Field:

Request Data

1:3

PPS IANA Private Enterprise ID, MS Byte first
0x00400A = 16394 (Pigeon Point Systems)

4

FRU Device ID

5

LED ID
00h Blue LED (Hot Swap)
01h LED 1 (OOS)
02h LED 2
03h LED 3
04h-FEh OEM defined LEDs
FFh reserved (all LEDs under management control are
addressed)

Response Data

1

Completion Code

2:4

PPS IANA Private Enterprise ID, MS Byte first
0x00400A = 16394 (Pigeon Point Systems)

5

Local Control LED Function
00h LED is off (default if Local Control not supported)
01h-FAh LED is blinking Off duration specified by this byte,
on duration specified by byte 5 (in tens of
milliseconds)
FBh-FEh reserved
FFh LED is on

6

Local Control On Duration
LED on-time is measured in tens of milliseconds
Lamp Test time in hundreds of milliseconds if byte 4=FBh, time
value must be less than 128. Other values when Byte 4=FBh are
reserved. Otherwise, this field is ignored and shall be set to 0h.

7

Color parameter specifies the color of the LED in the local state for
multi-color LEDs

8

If the off-first flag parameter is 0, the on part of the blink cycle of
the LED precedes the off part of the cycle. Otherwise, the off part
of the blink cycle precedes the on part of the cycle.

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System Management:

Vendor Commands

Update Discrete Sensor
The Update Discrete Sensor command is used to change the state of a discrete sensor controlled by the payload.
Table 7-40: Update Discrete Sensor Command

Type:

Byte:

Data Field:

Request Data

1:3

PPS IANA Private Enterprise ID, MS Byte first
0x00400A = 16394 (Pigeon Point Systems)

4

Sensor ID identifies the payload-controlled discrete sensor that has
to be updated

5

Update flags
0 0=sensor initialization is complete
1=sensor is in the initial update state
1:2 reserved, set to 0
3 0=globally disable events from the sensor
1=leave the global event enable bit intact
4 0=globally enable events from the sensor
1=leave the global event enable bit intact
5 0=globally disable sensor scanning
1=leave the global scanning enable bit intact
6 0=globally enable sensor scanning
1=leave the global scanning enable bit intact
7 reserved, set to 0

6:7

New status LSB and new status MSB are the least and most
significant bytes of the new sensor state

Response Data

1

Completion Code

2:4

PPS IANA Private Enterprise ID, MS Byte first
0x00400A = 16394 (Pigeon Point Systems)

Update Threshold Sensor
The Update Threshold Sensor command is used to change the state of a threshold sensor
controlled by the payload.
Table 7-41: Update Threshold Sensor Command

7-40

ATCA-9305 User’s Manual

Type:

Byte:

Data Field:

Request Data

1:3

PPS IANA Private Enterprise ID, MS Byte first
0x00400A = 16394 (Pigeon Point Systems)

4

Sensor ID parameter identifies the payload-controlled threshold
sensor that has to be updated

10009109-01

System Management:

Boot Device Redirection (BDR)

(continued)

Type:

Byte:

Data Field:

Request Data

5

Update flags
0 0=sensor initialization is complete
1=sensor is in the initial update state
1:2 reserved, set to 0
3 0=globally disable events from the sensor
1=leave the global event enable bit intact
4 0=globally enable events from the sensor
1=leave the global event enable bit intact
5 0=globally disable sensor scanning
1=leave the global scanning enable bit intact
6 0=globally enable sensor scanning
1=leave the global scanning enable bit intact
7 reserved, set to 0

6

New raw reading of the sensor

Response Data

1

Completion Code

2:4

PPS IANA Private Enterprise ID, MS Byte first
0x00400A = 16394 (Pigeon Point Systems)

BOOT DEVICE REDIRECTION (BDR)
The IPMC enables the ATCA-9305 to recover from monitor corruption by booting from a
redundant copy in another flash device. The mechanism relies on an IPMC software internal
watchdog to expire when corrupted code fails to reset the timer. This watchdog begins
counting down as soon as the payload is power cycled or reset. If the timer expires (approximately 30 seconds), the boot redirection will activate and the board will reset. Following
this automatic reset, IPMC will attempt to boot from the next flash device according to
Fig. 7-4. This sequence will continue until a valid boot image clears the watchdog.
The boot redirection order is configurable via the bootdev command (see page 9-17). If a
shunt is present on J9 [1:2}, the ATCA-9305 boots from socket. When forcing boot from the
socket, use bootdev and reset from the command line to test boot from a flash device. If
shunt is not installed on J9 [1:2], the ATCA-9305 follows the default boot redirection shown
in Fig. 7-4. Also reference the“Boot Device Redirection” register.
Note: The System Management IPMC can override the BDFR and swap the flash banks (from 1 to 2, or 2 to 1).

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7-41

System Management:

Boot Device Redirection (BDR)

Figure 7-4: Boot Device Diagram
512 KB socketed
flash installed on
ATCA-9305?

No

Yes
Yes

Initial boot attempt is from
ATCA-9305 soldered
flash bank 1

No

Jumper J11 [1:2]
shunt installed?

Flash bank 2
fail?

Flash bank 1
fail?
No

No

Yes

Yes
Boot device is 512
KB socketed flash
BDR Watchdog
disabled

Secondary boot
attempt is from ATCA9305 soldered
flash bank 2

Boot from
flash bank 2

Boot from
flash bank 1

Note: The Boot Device Redirection mechanism is disabled when booting from the 512 KB socketed flash.
Figure 7-5: Boot Redirection Control Diagram
Payload Reset
Monitor Booted
Management
Controller

Power Good

Private I2C

Force Boot Socket

I2C Port
Expander

Payload Reset Indication

Boot Select [ ]
Payload Reset Indication Clear

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Payload

System Management:

Message Listeners

Management Controller:
The controller provides a signals to reset the payload.
Payload: This provides signals to the controller indicating when the payload has reset for any reason,
that the payload is powered, and that the payload has finished its monitor booting
sequence. By default, a powered payload enables the watchdog and disables when the payload is not powered.
I2C Port Expander: The I2C port expander provides signals to the payload to define the boot device selection
(boot select [1 and 2]) and to clear the payload reset indication. The I2C port expander communicates with the controller via a private I2C.
Payload Reset: This signal is used by the management controller to reset the payload.
Monitor Booted: This signal indicates to the management controller that a valid monitor image has finished
booting and the watchdog can be disabled.
Power Good: This signal indicates to the management controller that the payload is powered. When payload power is applied, the BMC watchdog will start.
Force Boot Socket: If a shunt is present on J9 [1:2], the controller sets the boot location to socket flash with this
signal.
Payload Reset Indication:
When reset, this signal is held high by the payload until it is cleared by the IPMC using the
payload reset indication clear signal.
Boot Select [ ]: These signals select the boot device.
Payload Reset Indication Clear:
This signal clears the payload reset indication.

MESSAGE LISTENERS
Payload port dynamic control can be implemented via message listeners. The payload can
add itself as a message listener to any message destined for the IPMC target either over
IPMB-0 or the payload serial interface. When the IPMC receives a subscribed message, the
IPMC firmware copies the message into the payload’s LUN-10 Receive Message Queue and
notifies the payload via an unprintable character (ASCII 07, BELL). The payload receives the
message as described in “Message Bridging.” The message listener list is only eight entries
long. The payload can add/remove/get list at any time.
Note: The message listener list is not persistent across IPMC reboots.

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7-43

System Management:

Message Listeners

Add Message Listener
The Add Message Listener command adds a specified Network Function and Command to
the Message Listener List. The command returns completion code (0x00) and IANA. If this
command does not complete successfully (e.g., due to a full list), it returns 0xCD and IANA.
Table 7-42: Add Message Listener Command

Type:

Byte:

Data Field:

Request Data

1:3

Emerson Network Power, Embedded Computing Inc. IANA Private
Enterprise ID
0x0065CD = 26061 (Emerson Network Power, Embedded
Computing Inc.)
LSB Byte first:byte 1 = CD, byte 2 = 65, byte 3 = 00

4

Network function to add

5

Command to add

Response Data

1

Completion Code

2:4

Emerson Network Power, Embedded Computing Inc. IANA Private
Enterprise ID
0x0065CD = 26061 (Emerson Network Power, Embedded
Computing Inc.)
LSB Byte first:byte 2 = CD, byte 3 = 65, byte 4 = 00

Remove Message Listener
The Remove Message Listener command removes a specified Network Function and Command from the Message Listener List. The command returns completion code (0x00) and
IANA. If this command does not complete successfully (e.g., if the Network Function and
Command are not in the list), it returns 0xCD and IANA.
Table 7-43: Remove Message Listener Command

Type:

Byte:

Data Field:

Request Data

1:3

Emerson Network Power, Embedded Computing Inc. IANA Private
Enterprise ID
0x0065CD = 26061 (Emerson Network Power, Embedded
Computing Inc.)
LSB Byte first:byte 1 = CD, byte 2 = 65, byte 3 = 00

4

Network function to remove

5

Command to remove

Response Data

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ATCA-9305 User’s Manual

1

Completion Code

2:4

Emerson Network Power, Embedded Computing Inc. IANA Private
Enterprise ID
0x0065CD = 26061 (Emerson Network Power, Embedded
Computing Inc.)
LSB Byte first:byte 2 = CD, byte 3 = 65, byte 4 = 00

10009109-01

System Management:

System Firmware Progress Sensor

Get Message Listener List
The Get Message Listener List command returns the entire list of subscribed Message Listeners. The command returns completion code (0x00) and IANA.
Table 7-44: Get Message Listener List Command

Type:

Byte:

Data Field:

Request Data

1:3

Emerson Network Power, Embedded Computing Inc. IANA Private
Enterprise ID
0x0065CD = 26061 (Emerson Network Power, Embedded
Computing Inc.)
LSB Byte first:byte 1 = CD, byte 2 = 65, byte 3 = 00

Response Data

1

Completion Code

2:4

Emerson Network Power, Embedded Computing Inc. IANA Private
Enterprise ID
0x0065CD = 26061 (Emerson Network Power, Embedded
Computing Inc.)
LSB Byte first:byte 2 = CD, byte 3 = 65, byte 4 = 00

5

Network function for listener 0

6

Command for listener 0

7

Network function for listener 1

8

Command for listener 1

9

Network function for listener 2

10

Command for listener 2

11

Network function for listener 3

12

Command for listener 3

13

Network function for listener 4

14

Command for listener 4

15

Network function for listener 5

16

Command for listener 5

17

Network function for listener 6

18

Command for listener 6

19

Network function for listener 7

20

Command for listener 7

SYSTEM FIRMWARE PROGRESS SENSOR
The Update System Firmware Progress Sensor command sets the values for the Firmware
Progress Sensor using sensor codes from the IPMI Intelligent Platform Management Interface Specification, specifically (System Firmware Progress” within Table 42-3 in Section 42.2
“Sensor Type Codes and Data.”

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7-45

System Management:

Entities and Entity Associations

The command returns 0xC0 when the IPMC is busy and will retry until the command is successful. If this command returns 0xCC, the sensor ID is invalid. There is only one sensor on
the board, so the sensor ID should always be “0”. When updated, the shelf manager is notified.
Table 7-45: Update System Firmware Progress Sensor Command

Type:

Byte:

Data Field:

Request Data

1:3

Emerson Network Power, Embedded Computing Inc. IANA Private
Enterprise ID
0x0065CD = 26061 (Emerson Network Power, Embedded
Computing Inc.)
LSB Byte first:byte 1 = CD, byte 2 = 65, byte 3 = 00

4

0 (The sensor ID)

Response Data

5

Flags: reserved to 0

6

Offset in specification

7

Event Data 2; content to be added into the second byte of event data
per the IPMI specification

Valid offsets: 0, 1, 2

1

Completion Code

2:4

Emerson Network Power, Embedded Computing Inc. IANA Private
Enterprise ID
0x0065CD = 26061 (Emerson Network Power, Embedded
Computing Inc.)
LSB Byte first:byte 2 = CD, byte 3 = 65, byte 4 = 00

ENTITIES AND ENTITY ASSOCIATIONS
The AdvancedTCA specification (see PICMG Engineering Change Notice 3.0 listed in Table 1-2)
uses Entity IDs and Instances to describe physical components associated with FRUs.
Device-relative Entities are unique to a specific IPMC and are referenced as follows in the
specification:
r(,,,)
Using this terminology, a ATCA-9305 installed in Logical Slot 1 has the following description
in Fig. 7-6.

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System Management:

Entities and Entity Associations

Figure 7-6: IPMB Entity Structure
FRU 0 r(82, 0, A0, 0)
Inflow Temp
Outflow Temp
Hot Swap
IPMB Physical
BMC Watchdog
F/W Progress
SDRAM POST
IIC Bus POST
Flash POST
EthSwitch POST
Version change
Async Pld Rst
Payload Power
r(82, 0, 03, 0) - Cavium 1
Cavium 1 Temp
Cav1 SDRAM POST
Cav1 IIC POST
Cav1 Boot
r(82, 0, 03, 1) - Cavium 2
Cavium 2 Temp
Cav2 SDRAM POST
Cav2 IIC POST
Cav2 Boot
r(82, 0, 14, 0) - Power Module
-48V
-48V Curr
-48V Src A
-48V Src B
+3.3V Mgmt
+12V Payload
+12V Curr
FRU 1 r(82, 0, C0, 1) RTM
RTM Hot Swap

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7-47

System Management:

Sensors and Sensor Data Records

SENSORS AND SENSOR DATA RECORDS
The ATCA-9305 implements a number of sensors as described in the following tables. All
values are hexadecimal.
Table 7-46: IPMI Threshold Sensors

Name:

Sensor
Type:

Event Reading
Type:

Enity
ID:

Entity
Instance:

Event
Gen:

Inflow Temp

Temperature = 01

Threshold = 01

0xA0

0x60

Yes

Outflow Temp

Temperature = 01

Threshold = 01

0xA0

0x60

Yes

Cavium 1 Temp

Temperature = 01

Threshold = 01

0x03

0x60

Yes

Cavium 2 Temp

Temperature = 01

Threshold = 01

0x03

0x61

Yes

-48V

Voltage = 02

Threshold = 01

0x14

0x60

Yes

-48V Curr

Current = 03

Threshold = 01

0x14

0x60

Yes

-48V Src A

Voltage = 02

Threshold = 01

0x14

0x60

Yes

-48V Src B

Voltage = 02

Threshold = 01

0x14

0x60

Yes

+3.3V Mgmt

Voltage = 02

Threshold = 01

0x14

0x60

Yes

+12V Payload

Voltage = 02

Threshold = 01

0x14

0x60

Yes

+12V Curr

Current = 03

Threshold = 01

0x14

0x60

Yes

Name:

Sensor
Type:

Event Reading
Type:

Enity
ID:

Entity
Instance:

Event
Gen:

Hot Swap

Hot Swap = F0

Sensor specific
discrete = 6F

0xA0

0x60

Yes

RTM Hot Swap

Hot Swap = F0

Sensor specific
discrete = 6F

0xC0

0x61

Yes

IPMB Physical

IPMB Link = F1

Sensor specific
discrete = 6F

0xA0

0x60

Yes

BMC Watchdog

Watchdog2 = 23

Sensor specific
discrete = 6F

0xA0

0x60

Yes

F/W Progress

System Firmware
Progress = 0F

Sensor specific
discrete = 6F

0xA0

0x60

Yes

SDRAM POST

Memory = 0C

Sensor specific
discrete = 6F

0xA0

0x60

Yes

IIC Bus POST

Processor = 07

Predictive-failure
Discrete = 04

0xA0

0x60

Yes

Flash POST

Memory = 0C

Sensor specific
discrete = 6F

0xA0

0x60

Yes

EthSwitch POST

Chip Set

Predictive-failure
Discrete = 04

0xA0

0x60

Yes

Cav1 SDRAM
POST

Memory = 0C

Sensor specific
discrete = 6F

0x03

0x60

Yes

Table 7-47: IPMI Discrete Sensors

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System Management:

Sensors and Sensor Data Records

Name:

Sensor
Type:

Event Reading
Type:

Enity
ID:

Entity
Instance:

Event
Gen:

Cav1 IIC POST

Processor = 07

Predictive-failure
Discrete = 04

0x03

0x60

Yes

Cav1 Boot

Processor = 07

Predictive-failure
Discrete = 04

0x03

0x60

Yes

Cav2 SDRAM
POST

Memory = 0C

Sensor specific
discrete = 6F

0x03

0x61

Yes

Cav2 IIC POST

Processor = 07

Predictive-failure
Discrete = 04

0x03

0x61

Yes

Cav2 Boot

Processor = 07

Predictive-failure
Discrete = 04

0x03

0x61

Yes

Version change

Version Change

Sensor specific
discrete = 6F

0xA0

0x60

Yes

Async Pld Rst

Power Supply = 08

Digital Discrete
= 03

0xA0

0x60

Yes

Payload Power

Power Supply = 08

Digital Discrete
= 03

0xA0

0x60

Yes

The IPMC implements a Device Sensor Data Record (SDR) Repository that contains SDRs for
the IPMC, the FRU device, and each sensor. A system management controller may use the
Get Device SDR command to read the repository and dynamically discover the capabilities
of the board. Refer to the IPMI specification (listed in Table 1-2) for more information on
using Sensor Data Records and the Device SDR Repository.
Under certain circumstances, some sensors connected to the IPMC can generate Event Messages for the system management controller. To enable these messages, the system management controller must send a Set Event Receiver command to the IPMC, along with the
address of the Event Receiver. Table 7-48 shows the format of an Event Message:
Table 7-48: Event Message Format

Byte:1

Field:

0

RsSA

Responder’s Slave Address (Address of Event Receiver)

1

NetFn/RsLUN

Net Function Code (0x04) in upper 6 bits; Responder’s LUN in lower 2
bits

2

Chk 1

Checksum #1

3

RqSA

Requester’s Slave Address (Address of our board on IPMB)

4

RqSeq/RqLUN

Request Sequence number in upper 6 bits; Requester’s LUN in lower 2
bits

5

Cmd

Command (Always 0x02 for event message)

6

EvMRev

Event Message Revision (0x04 for IPMI 1.5)

7

Sensor Type

Indicates event class or type of sensor that generated the message

8

Sensor Number

A unique number indicating the sensor that generated the message

Description:

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System Management:

FRU Inventory

Byte:1

Field:

Description:

9

Event Dir/Event
Type

Upper bit indicates direction (0 = Assert, 1= Deassert); Lower 7 bits
indicate type of threshold crossing or state transition

10

Event Data 0

Data for sensor and event type

11

Event Data 1

(Optional) Data for sensor and event type

12

Event Data 2

(Optional) Data for sensor and event type

13

Chk2

Checksum #2

(continued)

1. Each byte has eight bits.

Event-generating sensors with a Threshold Event/Reading Type (0x01) initiate an event message when a sensor reading crosses the defined threshold. The default thresholds for a particular sensor are retrieved by sending the IPMC a Get Sensor Thresholds command. The
system management controller must send the IPMC a Get Sensor Reading command to
retrieve the current sensor reading. Refer to the IPMI specification listed in Table 1-2 for complete details on using these commands.

FRU INVENTORY
The IPMC stores Field Replaceable Unit (FRU) information in its boot memory (SROM). The
data structure contains information such as the product name, part number, serial number,
manufacturing date, and E-keying information. Refer to the IPMI specification for complete
details on the FRU data structure. Table 7-49 lists the general contents of the ATCA-9305’s
FRU information:
Table 7-49: FRU Definition

Item:

Description:

Common Header
Version

Version number of the overall FRU data structure defined by the IPMI
FRU specification

Internal Use Area
Version

Version number of the Internal Use Area data structure defined by
the IPMI FRU specification

Internal Use Size

0x100 bytes are allocated for customer use in this area

Board Information Area
Version

7-50

ATCA-9305 User’s Manual

Version number of the Board Information Area data structure
defined by the IPMI FRU specification

Language Code

0x01 = English

Manufacturing Date/Time

Variable, expressed as the number of minutes since 12:00 AM on
January 1, 1996

Board Manufacturer

“Emerson”

Board Product Name

“ATCA-9305”

10009109-01

System Management:

E-Keying

Item:

Description: (continued)

Board Serial Number

Variable, formatted as “730-XXXX”

Board Part Number

Variable, formatted as “10XXXXXX-YY-Z”

FRU File ID

Variable, for example: “fru-info.inf”

Product Information Area
Version

Version number of the Product Information Area data structure
defined by the IPMI FRU specification

Language Code

0x01 = English

Manufacturer Name

“Emerson”

Product Name

“ATCA-9305”

Product Part/Model Number

Variable, formatted as “10XXXXXX-YY-Z”

Product Version

Not used, same information is provided by the part number

Product Serial Number

Variable, formatted as “730-XXXX”

Asset Tag

Not Used

FRU File ID

Variable, for example: “fru-info.inf”

MultiRecord Area
E-Keying records

See “E-Keying”

Maximum Internal Current

“12.5 Amps”

E-KEYING
This section details the interfaces governed by E-keying and the protocols they support.
Specifically, this includes the interfaces implemented by this product and the E-keying definition that corresponds to each interface.
The IPMC supports E-keying for the ATCA-9305 per PICMG® ATCA 3.0, Revision 2.0 and
PICMG 3.1, Revision 1.0 specifications The E-keying information is stored in the ATCA Pointto-Point Connectivity Record located in the Multi-Record area of the FRU Inventory Information (see page 7-50). The ATCA Point-to-Point Connectivity Record contains a Channel
Descriptor list, where each Link Descriptor details one type of point-to-point protocol supported by the referenced channels.
The ATCA channel descriptors define the ATCA channels implemented on a module. Each
channel has an arbitrary set of up to four ports. Channel descriptors map physical ports to
logical entities known as lanes, see Table 7-50.
Note: Certain Ethernet core switch and fat pipe switch module GbE switch ports are disabled due to lack of e-keying
support in the monitor.

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System Management:

HPM.1 Firmware Upgrade

Base Point-to-Point Connectivity
The ATCA-9305 supports two 10/100/1000BASE-T ports on Base Interface Channels 0 and
1, and two 10 GbE XAUI ports to the Fabric channels. Depending on the board configuration, either two or six 10 GbE XAUI ports route to the optional rear transition module (RTM).
Table 7-50 shows the Point-to-point Connectivity Record Link Descriptors for the ATCA9305.
Note: For actual Point-to-Point connectivity Records for your configuration, query the IPMI controller.
Table 7-50: Link Description

Field:

Value:1

Description:

Link Descriptor

000100000000b

Port 0 Enabled; Base Interface; Channel 1

Link Type

01h

PICMG 3.0 Base Interface 10/100/1000BASE-T

Link Type Extension

000b

Link Grouping ID

00h

Independent Channel

Link Designator

000100000001b

Port 0 Enabled; Base Interface; Channel 2

Link Type

01h

PCIMG 3.0 Base Interface 10/100/1000BASE-T

Link Type Extension

0000b

Link Grouping ID

00h

Link Designator

000110000001b

Port 0 Enabled; Update Channel Interface; Channel 1

Link Type

01h

PICMG 3.1 Ethernet Fabric Interface

Independent Channel

Link Type Extension

0000b

Fixed 1000BASE-BX

Link GroupingID

00h

Independent Channel

1. h = hexadecimal, b = binary

HPM.1 FIRMWARE UPGRADE
The ATCA-9305 IPMC firmware supports a reliable field upgrade procedure compliant with
the HPM.1 specification. The prominent features of the firmware upgrade procedure are:
• The upgrade can be performed either over the payload serial interface or IPMB-0.
• The upgrade procedure is performed while the ATCA-9305 is online and operating
normally.
• The upgrades are reliable. A failure in the download (error or interruption) does not
disturb the ATCA-9305’s ability to continue using the “old” firmware or its ability to
restart the download process.
• The upgrades are reversible. The ATCA-9305 IPMC automatically reverts back to the
previous firmware if there is a problem when first running the new code, and can be
reverted manually using the HPM.1-defined Manual Rollback command.

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System Management:

IPMC Headers

HPM.1 Reliable Field Upgrade Procedure
The HPM.1 upgrade procedure is managed by a utility called the Upgrade Agent. The
Impitool utility is used as an Upgrade Agent for upgrading the ATCA-9305 IPMC firmware.
The Upgrade Agent communicates with the IPMC firmware via the payload serial interface
or IPMC-0, and uses the AdvancedTCA commands that are described in the HPM.1 specification for upgrading the firmware. Updated firmware is packed into an image formatted in
compliance with the HPM.1 specification. That image is used by Upgrade Agent to prepare
and upgrade the IPMC firmware. The HPM.1 upgrade procedure includes the following
steps:
Preparation: This step erases the region in the flash memory where the component image will be written.
Component Upload: This step is designed to upload the component image via IPMB or payload interface and
write it into the flash memory.
Component Activation: This step activates the previously upgraded component. This step can be deferred and performed later.
For more details, refer to the HPM.1 specification listed in Table 1-2.

IPMC HEADERS
This JTAG header (JP1) is available for in-system programming of the CPLD.
Table 7-51: IPMP CPLD JP1 Pin Assignments

Pin:

Signal:

Direction:

Pin:

Signal:

1

CPLD_TCK

out

2

ground

3

CPLD_TDI

in

4

3_3V (fused)

5

CPLD_TMS

out

6

no connect

7

no connect

—

8

no connect

9

CPLD_TDO

out

10

ground

The EIA-232 debug serial port is accessible via the mini-B USB connector P4. Default port
settings are: 115200 baud (optional 9600), 8 data bits, 1 stop bit, no parity, no flow control.
Table 7-52: IPMP EIA-232 P4 Pin Assignments

Pin:

Signal:

Pin:

Signal:

1

no connect

2

IPMP_RS_232_Rx

3

IPMP_RS_232_Tx

4

no connect

5

ground

6

ground

7

ground

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Section 8

Back Panel Connectors

There are multiple connectors on the ATCA-9305, reference Fig. 2-2 for their location. The
back panel connectors, Zones 1 through 3, are described in this chapter. Whether individual
back panel connectors are populated on the ATCA-9305 depends on the specific product
configuration.

ZONE 1
Connector P10 provides the AdvancedTCA Zone 1 power (dual redundant -48 VDC) and system management connections. Four levels of sequential mating provide proper functionality during live insertion or extraction, see Table 8-1.
Figure 8-1: Zone 1 Connector, P10

33

30

28

32

34

25

21

17 13

1

24

20 16

4

27

31

29

26

Table 8-1: Zone 1 Connector, P10 Pin Assignments

Pin:

Signal:

Insertion Sequence:

1

reserved

NA

2

reserved

NA

3

reserved

NA

4

reserved

NA

5

HA0

third

6

HA1

third

7

HA2

third

8

HA3

third

9

HA4

third

10

HA5

third

11

HA6

third

12

HA7 (odd parity bit)

third

13

IPMBA_SCL

third

14

IPMBA_SDA

third

15

IPMBB_SCL

third

16

IPMBB_SDA

third

17

no connect

third

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ATCA-9305 User’s Manual

8-1

Back Panel Connectors:

Zone 2

Pin:

Signal:

Insertion Sequence:

18

no connect

third

19

no connect

third

20

no connect

third

21

no connect

third

22

no connect

third

23

no connect

third

24

no connect

third

25

P10_CHS_GND

first

26

Logic ground

first

27

ENABLE_B

fourth

28

-48RTNA

first

29

-48RTNB

first

30

no connect

first

31

no connect

first

32

ENABLE_ A

fourth

33

-48A

second

34

-48B

third

ZONE 2
Zone 2 (ZD) defines backplane connector J23, which supports the data transport interface.
The Zone 2 connector array supports four interfaces to the AdvancedTCA backplane:
• Base Node Interface (J23) supports two Base channels (10/100/1000 BASE-T)
• Fabric Interface (J23) supports two Fabric channels (10GbE)
Figure 8-2: Zone 2 and 3 Connectors; J23, J30-J31
Row H
Row G
Row F
Row E
Row D
Row C
Row B
Row A

8-2

ATCA-9305 User’s Manual

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6

5

1

10009109-01

Back Panel Connectors:

Zone 3

Table 8-2: Zone 2 Connector, J23 Pin Assignments

Row:

Interface:

1

Fabric
Channel 2

2
3

Fabric
Channel 1

4

AB:

CD:

EF:

GH:

TX2+

TX2-

RX2+

RX2-

TX3+

TX3-

RX3+

TX0+

TX0-

RX0+

RX0-

TX1+

TX1-

RX1+

RX3RX1-

TX2+

TX2-

RX2+

RX2-

TX3+

TX3-

RX3+

RX3-

TX0+

TX0-

RX0+

RX0-

TX1+

TX1-

RX1+

RX1-

5

Base
Channel 1

TRD0+

TRD0-

TRD1+

TRD1-

TRD2+

TRD2-

TRD3+

TRD3-

6

Base
Channel 2

TRD0+

TRD0-

TRD1+

TRD1-

TRD2+

TRD2-

TRD3+

TRD3-

7-10

na

no connect

ZONE 3
These optional Zone 3 type A connectors, J30, J31, and J33, support a Rear Transition Module (RTM). I/O signals are routed through Zone 3 connectors to the RTM to allow servicing
the ATCA-9305 without using cable assemblies. Connectors J30 and J31 use the same ZD
connector as Zone 2. See Fig. 8-3 for the J33 connector.
Table 8-3: Zone 3 Connector, J30 Pin Assignments

A:

B:

C:

D:

E:

F:

G:

H:

1

RTM_10G1
_ RX0_P

RTM_10G1
_ RX0_N

PQ_PCIE_
RXD3_P

PQ_PCIE_
RXD3_N

RTM_10G2
_ RX0_P

RTM_10G2
_ RX0_N

PQ_PCIE_
TXD3_P

PQ_PCIE_
TXD3_N

2

RTM_10G1
_ RX1_P

RTM_10G1
_ RX1_N

PQ_PCIE_
RXD2_P

PQ_PCIE_
RXD2_N

RTM_10G2
_ RX1_P

RTM_10G2
_ RX1_N

PQ_PCIE_
TXD2_P

PQ_PCIE_
TXD2_N

3

RTM_10G1
_ RX2_P

RTM_10G1
_ RX2_N

PQ_PCIE_
RXD1_P

PQ_PCIE_
RXD1_N

RTM_10G2
_ RX2_P

RTM_10G2
_ RX2_N

PQ_PCIE_
TXD1_P

PQ_PCIE_
TXD1_N

4

RTM_10G1
_ RX3_P

RTM_10G1
_ RX3_N

PQ_PCIE_
RXD0_P

PQ_PCIE_
RXD0_N

RTM_10G2
_ RX3_P

RTM_10G2
_ RX3_N

PQ_PCIE_
TXD0_P

PQ_PCIE_
TXD0_N

5

RTM_10G1
_TX0_P

RTM_10G1
_ TX0_P

PCIE_
REFCLKF_P

PCIE_
REFCLKF_N

RTM_10G2
_ TX0_P

RTM_10G2
_ TX0_N

no connect

no connect

6

RTM_10G1
_ TX1_P

RTM_10G1
_ TX1_N

no connect

no connect

RTM_10G2
_ TX1_P

RTM_10G2
_ TX1_N

no connect

no connect

7

RTM_10G1
_ TX2_P

RTM_10G1
_ TX2_N

no connect

no connect

RTM_10G2
_ TX2_P

RTM_10G2
_ TX2_N

no connect

no connect

8

RTM_10G1
_ TX3_P

RTM_10G1
_ TX3_N

no connect

no connect

RTM_10G2
_ TX3_P

RTM_10G2
_ TX3_N

no connect

no connect

9

RTM_ID3

RTM_ID2

no connect

no connect

RTM_
GPIO3

RTM_
GPIO2

RTM_
GPIO7

RTM_
GPIO6

10

RTM_ID1

RTM_ID0

SW_MDC

SW_MDIO

RTM_
GPIO1

RTM_
GPIO0

RTM_
GPIO5

RTM_
GPIO4

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ATCA-9305 User’s Manual

8-3

Back Panel Connectors:

Zone 3

Table 8-4: Zone 3 Connector, J31 Pin Assignments

A:

B:

C:

D:

E:

F:

G:

H:

1

RTM_10G3
_ RX0_P

RTM_10G3
_ RX0_N

RTM_10G5
_ RX0_P

RTM_10G5
_ RX0_N

RTM_10G4
_ RX0_P

RTM_10G4
_ RX0_N

RTM_10G6
_ RX0_P

RTM_10G6
_ RX0_N

2

RTM_10G3
_ RX1_P

RTM_10G3
_ RX1_N

RTM_10G5
_ RX1_P

RTM_10G5
_ RX1_N

RTM_10G4
_ RX1_P

RTM_10G4
_ RX1_N

RTM_10G6
_ RX1_P

RTM_10G6
_ RX1_N

3

RTM_10G3
_ RX2_P

RTM_10G3
_ RX2_N

RTM_10G5
_ RX2_P

RTM_10G5
_ RX2_N

RTM_10G4
_ RX2_P

RTM_10G4
_ RX2_N

RTM_10G6
_ RX2_P

RTM_10G6
_ RX2_N

4

RTM_10G3
_ RX3_P

RTM_10G3
_ RX3_N

RTM_10G5
_ RX3_P

RTM_10G5
_ RX3_N

RTM_10G4
_ RX3_P

RTM_10G4
_ RX3_N

RTM_10G6
_ RX3_P

RTM_10G6
_ RX3_N

5

RTM_10G3
_ TX0_P

RTM_10G3
_ TX0_N

RTM_10G5
_ TX0_P

RTM_10G5
_ TX0_N

RTM_10G4
_ TX0_P

RTM_10G4
_ TX0_N

RTM_10G6
_ TX0_P

RTM_10G6
_ TX0_N

6

RTM_10G3
_ TX1_P

RTM_10G3
_ TX1_N

RTM_10G5
_ TX1_P

RTM_10G5
_ TX1_N

RTM_10G4
_ TX1_P

RTM_10G4
_ TX1_N

RTM_10G6
_ TX1_P

RTM_10G6
_ TX1_N

7

RTM_10G3
_ TX2_P

RTM_10G3
_ TX2_N

RTM_10G5
_ TX2_P

RTM_10G5
_ TX2_N

RTM_10G4
_ TX2_P

RTM_10G4
_ TX2_N

RTM_10G6
_ TX2_P

RTM_10G6
_ TX2_N

8

RTM_10G3
_ TX3_P

RTM_10G3
_TX3_N

RTM_10G5
_ TX3_P

RTM_10G5
_ TX3_N

RTM_10G4
_ TX3_P

RTM_10G4
_ TX3_N

RTM_10G6
_ TX3_P

RTM_10G6
_ TX3_N

9

no connect

no connect

no connect

no connect

no connect

no connect

no connect

no connect

10

no connect

no connect

no connect

no connect

no connect

no connect

no connect

no connect

Figure 8-3: Zone 3 Connector, J33
1

6

D
C
B
A

Table 8-5: Zone 3 Connector, J33 Pin Assignments

8-4

Pin:

A:

B:

C:

D:

1

RTM_ENABLE

RTM_PS1_CONN*

PQ_CONSOLE_RX_M

RTM_PB_RST*

2

RTM_PP_PWRGD

RTM_HS_LED

PQ_CONSOLE_TX_M

RTM_E_HANDLE

3

RTM_MP_PWRGD

IPMB_RTM_SCL_BUFF

no connect

RTM_RST*

4

no connect

IPMB_RTM_SDA_BUFF

3_3V_MP_RTM

3_3V_MP_RTM

5

ground

ground

ground

ground

6

12V_RTM

12V_RTM

12V_RTM

12V_RTM

ATCA-9305 User’s Manual

10009109-01

Section 9

Management Processor Monitor

The ATCA-9305 monitor is based on the Embedded PowerPC Linux Universal Boot (U-Boot)
Project program, available under the GNU General Public License (GPL). For instructions on
how to obtain the source code for this GPL program, please visit http://www.emersonembeddedcomputing.com/post-sales_support/218, send an e-mail to support@artesyncp.com, or call Emerson at (800) 327-1251.
This chapter describes the monitor’s basic features, operation, and configuration
sequences. This chapter also serves as a reference for the monitor commands and functions.

COMMAND-LINE FEATURES
The ATCA-9305 monitor uses a command-line interface with the following features:
Auto-Repeat: After entering a command, you can re-execute it simply by pressing the ENTER or RETURN
key.
Command History: Recall previously entered commands using the up and down arrow keys.
TFTP Boot: You can use the TFTP protocol to load application images via Ethernet into the ATCA-9305’s
memory.
Auto-Boot: You can store specific boot commands in the environment to be executed automatically
after reset.
Flash Programming: You can write application images into flash via the U-Boot command line. The upper 1 MB at
the base of flash and 128 KB of each flash bank is reserved for the monitor and environment
variables (see “MPC8548 Memory Map”). One megabyte is reserved at the second bank of
flash. The moninit command will load both banks of flash (see “moninit” on page 9-22) with
the monitor and default environment variables.
At power-up or after a reset, the monitor runs diagnostics and reports the results in the
start-up display, see Fig. 9-1. During the power-up sequence, the monitor configures the
board according to the environment variables (see “MPC8548 Environment Variables” on
page 9-26). If the configuration indicates that autoboot is enabled, the monitor attempts to
load the application from the specified device. If the monitor is not configured for autoboot
or a failure occurs during power-up, the monitor enters normal command-line mode. Also,
the optional “e-keying” environment variable enables connections at power-up, for debug
purposes only, to the Update Channel and payload ports that go off the ATCA-9305. See
Table 9-7 for more information.
The monitor command prompt in Fig. 9-1 is the result of a successful hardware boot of the
ATCA-9305.

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9-1

Management Processor Monitor:

Command-Line Features

Figure 9-1: Example MPC8548 Monitor Start-up Display
U-Boot 1.1.4 (Jan
Hardware initialization

Monitor command prompt

8 2007 - 16:07:48)1.0

CPU:
8548_E, Version: 2.0, (0x80390020)
Core: E500, Version: 2.0, (0x80210020)
Clock Configuration:
CPU: 999 MHz, CCB: 399 MHz,
DDR: 199 MHz, LBC: 49 MHz
Board: ATCA-9305 ATCA Blade
Emerson Network Power, Embedded Computing Inc.
cPLD Ver: 2
I2C:
ready
Clearing ALL of memory
................
DRAM: 512 MB
Testing Top 1M Area of DRAM........PASSED
Relocating code to RAM
FLASH: [4MB@e0000000][4MB@e1000000]8 MB
L2 cache: enabled
In:
serial
Out:
serial
Err:
serial
Ser#: 1096
Diags Mem:
PASSED
Diags I2C:
PASSED
Diags Flash:
PASSED
BootDev: Socket
I-cache enabled
D-cache enabled (write-through)
L2 cache enabled. (L2CTL: 0xa0000000)
(write-through)
IPMC: v0.1.1
DOC:
Turbo Mode
Net:
eTSEC1, eTSEC2
ATCA-9305 (Mon 1.0)=>

This prompt is also displayed as an indication that the monitor has finished executing a
command or function invoked at the command prompt (except when the command loads
and jumps to a user application). The hardware product name (ATCA-9305), and current
software version number are displayed in the prompt.
Prior to the console port being available, the monitor will display a four-bit hexadecimal
value on LED1 through LED4 to indicate the power-up status (see Table 9-1). See Fig. 2-4 for
the debug LED locations. In the event of a specific initialization error, the LED pattern will be
displayed and the board initialization will halt.
Table 9-1: Debug LED Codes

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ATCA-9305 User’s Manual

LED Code:

Power-up Status:

LED Value:

BOARD_PRE_INIT

start booting, setup BATs done

0x01

SERIAL_INIT

console init done

0x02

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Management Processor Monitor:

Basic Operation

LED Code:

Power-up Status:

LED Value:

CHECKBOARD

get processor and bus speeds done

0x03

SDRAM_INIT

RAM / ECC init done

0x04

AFTER_RELOC

U-Boot relocated to RAM done

0x05

MISC_R

final init including Ethernet done

0x06

GONE_TO_PROMPT

—

0x00

BASIC OPERATION
The monitor performs various configuration tasks upon power-up or reset. This section
describes the monitor operation during initialization of the ATCA-9305 board. The flowchart (see Fig. 9-2) illustrates the power-up and global reset sequence (bold text indicates
environment variables).

Power-up/Reset Sequence
The ATCA-9305 monitor follows the boot sequence in Fig. 9-2 before auto-booting the operating system or application software. At power-up or board reset, the monitor performs
hardware initialization, diagnostic routines, autoboot procedures, free memory initialization, and if necessary, invokes the command line. See Fig. 3-4 for the Cavium CN5860 processor boot sequence. See Table 9-6 for default environment variables settings.

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9-3

Management Processor Monitor:

Basic Operation

Figure 9-2: Power-up/Reset Sequence Flowchart
Power-up or Reset

U-Boot Monitor
Default Board Initialization

U-Boot Monitor
PCI Monarch, Enumerate

U-Boot Monitor
Configure Ethernet Switch
Initialize IPMC
Execute POST

Boot Caviums
Boot Cavium processor
according to
configuration parameters

U-Boot Monitor
Start Autoboot Sequence
(Boot Operating System)

Operating System Boot
Boot OS image
according to
configuration parameters

POST Diagnostic Results
The ATCA-9305 Power-On Self-Test (POST) diagnostic results are stored as a 32-bit value in
I2C NVRAM at the offset 0x07F0-0x07FF. Each bit indicates the result of a specific test,
therefore this field can store the results of up to 32 diagnostic tests. Table 9-2 assigns the bits
to specific tests.

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ATCA-9305 User’s Manual

10009109-01

Management Processor Monitor:

Monitor Recovery and

Table 9-2: POST Diagnostic Results–Bit Assignments

Bit:

Diagnostic Test:

Description:

0

SDRAM

Verify address and data lines are intact

1

Flash

Verify size and initialization of soldered
flash

2

I2C

Verify all local I2C devices are connected
to the I2C bus
Verify PCI communication with switch

3

Ethernet Switch

4

Reserved

5

PCIe Time-out

PCIe enumeration skipped by user

6

DOC Embedded Flash
Drive (EFD)

Verify presence and ability to access
configuration space of DOC

7

Cavium 1 Presence

Verify presence and ability to
communicate via PCI bus with Cavium 1

8

Cavium 2 Presence

Verify presence and ability to
communicate via PCI bus with Cavium 2

9-31

Reserved

Value:

0

Passed the test

1

Failure detected

Monitor SDRAM Usage
Monitor SDRAM usage is typically around 1 MB for monitor code and stack support. Please
note that the monitor stack grows downward from below where the monitor code resides
(in the upper 512 KB). The monitor C stack will typically not grow beyond 512 KB, therefore
the upper 1 MB of SDRAM is reserved for monitor use.
Note: The monitor has the ability to preserve (not overwrite) areas of memory defined by the pram environment
variable.

Caution: Any writes to these areas can cause unpredictable operation of the monitor.
!

MONITOR RECOVERY AND UPDATES
This section describes how to recover and/or update the monitor, given one or more of the
following conditions:
• If there is no console output, the monitor may be corrupted and need recovering (see
the “Recovering the Monitor” section).
• If the monitor still functions, but is not operating properly, then you may need to reset
the environment variables (see the “Resetting Environment Variables” section).
• If you are having Ethernet problems in the monitor, you may need to set the serial
number, since the MAC address is calculated from the serial number variable.

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Management Processor Monitor:

Monitor Recovery and

Recovering the Monitor
1 Make sure that a monitor ROM device is installed in the PLCC socket on the ATCA-9305.
2 Verify there is a shunt on J9, across pins 1 and 2.
3 Issue the following command, where serial_number is the board’s serial number, at the
monitor prompt:
ATCA-9305 (1.0) => moninit serial_number

moninit will also reset environment variables to the default state.
4 To boot from soldered flash, power down the board and remove the shunt from J9, pins 1
and 2.
The monitor always resides in the top 512 KB block of NOR flash (banks 1 and 2) as shown in
Table 9-3.
Table 9-3: Monitor Address per Flash Device

Address Range (hex):

Device:

F3F8,0000-F400,0000

Monitor Location in Flash Bank2 (4 MB)

F3B8,0000-F3C0,0000

Monitor Location in Flash Bank1 (4 MB)

F3B7,0000-F3B7,1000

Environment Variables

F3F7,0000-F3F7,1000

Redundant Environment Variables

Resetting Environment Variables
To restore the monitor’s standard environment variables, execute the following commands
and insert the appropriate data in the italicized fields:
ATCA-9305 (1.0) => moninit serial_number noburn

Note: Press the ‘s’ key on the keyboard during reset to force the default environment variables to be loaded. See
“MPC8548 Environment Variables” for more information.

Optionally, save your settings:
ATCA-9305 (1.0) => saveenv

Updating the Monitor via TFTP
To update the monitor via TFTP, ensure that an appropriate VLAN is set up in the Ethernet
switch (see the ATCA-9305 Quick Start Guide, #10009110-xx) and execute the following
commands, inserting the appropriate data in the italicized fields:
If necessary, edit your network settings:
ATCA-9305
ATCA-9305
ATCA-9305
ATCA-9305

9-6

ATCA-9305 User’s Manual

(1.0)
(1.0)
(1.0)
(1.0)

=>
=>
=>
=>

setenv
setenv
setenv
setenv

ipaddr 192.168.1.100
gatewayip 192.168.1.1
netmask 255.255.255.0
serverip 10.64.16.168

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Management Processor Monitor:

Monitor Command

ATCA-9305 (1.0) => setenv ethport eTSEC1

Optionally, save your settings:
ATCA-9305 (1.0) => saveenv

TFTP the new monitor (binary) image to memory location 0x100000:
ATCA-9305 (1.0) => tftpboot 100000 path_to_file_on_tftp_server

Update the monitor:
ATCA-9305 (1.0) => moninit serial_number 100000

If moninit( ) fails, burn the new monitor to a ROM and follow the recovery steps in the
“Recovering the Monitor” section.

MONITOR COMMAND REFERENCE
This section describes the syntax and typographic conventions for the ATCA-9305 monitor
commands. Subsequent sections in this chapter describe individual commands, which fall
into the following categories: boot, memory, flash, environment variables, test, and other
commands.

Command Syntax
The monitor uses the following basic command syntax:
   

• The command line accepts three different argument formats: string, numeric, and
symbolic. All command arguments must be separated by spaces with the exception of
argument flags, which are described below.
• Monitor commands that expect numeric arguments assume a hexadecimal base.
• All monitor commands are case sensitive.
• Some commands accept flag arguments. A flag argument is a single character that
begins with a period (.). There is no white space between an argument flag and a
command. For example, md.b 80000 is a valid monitor command, while md .b 80000
is not.
• Some commands may be abbreviated by typing only the first few characters that
uniquely identify the command. For example, you can type h instead of help. However,
commands cannot be abbreviated when accessing online help. You must type help and
the full command name.

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Management Processor Monitor:

Boot Commands

Command Help
Access all available monitor commands by pressing the ? key or entering help. Access the
monitor online help for individual commands by typing help . The full command name must be entered to access the online help.

Typographic Conventions
In the following command descriptions, text in Courier shows the command format.
Square brackets [ ] enclose optional arguments, and angled brackets < > enclose required
arguments. Italic type indicates a variable or field that requires input.

BOOT COMMANDS
The boot commands provide facilities for booting application programs and operating systems from various devices.

bootd
Execute the command stored in the bootcmd environment variable.
Definition:

bootd

bootelf
The bootelf command boots from an ELF image in memory, where address is the load
address of the ELF image.
Definition:

bootelf [ address ]

bootm
The bootm command boots an application image stored in memory, passing any entered
arguments to the called application. When booting a Linux kernel, arg can be the address of
an initrd image. If addr is not specified, the environment variable loadaddr is used as the
default.
Definition:

bootm [addr [arg …]]

bootp
The bootp command boots an image via a network connection using the BootP/TFTP protocol. If loadaddress or bootfilename is not specified, the environment variables loadaddr and
bootfile are used as the default.
Definition:

9-8

ATCA-9305 User’s Manual

bootp [loadAddress] [bootfilename]

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Management Processor Monitor:

Boot Commands

To use network download commands (e.g., bootp, bootvx, rarpboot, tftpboot), the environment variables listed in Table 9-4 must be configured. To set a static IP, these environment variables must be specified through the command line interface.
Table 9-4: Static IP Ethernet Configuration

Environment Variable:

Description:

ipaddr

Local IP address for the board

serverip

TFTP/NFS server address

netmask

Net mask

gatewayip

Gateway IP address

ethport

eTSEC1 default

ethaddr1

MAC address

1. Ensure that each MAC address on the network is unique.

bootv
The bootv command checks the checksum on the primary image (in flash) and boots it, if
valid. If it is not valid, it checks the checksum on the secondary image (in flash) and boots it,
if valid. If neither checksum is valid, the command returns back to the monitor prompt.
Definition: Verify bootup.
bootv

Write image to flash and update NVRAM.
bootv  write   

Update NVRAM based on image already in flash.
bootv  update  

Check validity of images in flash.
bootv  check

bootvx
The bootvx command boots VxWorks® from an ELF image, where address is the load
address of the VxWorks ELF image. To use this command, the environment variables listed
in Table 9-4 must be configured.
Definition:

bootvx [ address ]

dhcp
The dhcp command invokes a Dynamic Host Configuration Protocol (DHCP) client to obtain
IP and boot parameters by sending out a DHCP request and waiting for a response from a
server.

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Management Processor Monitor:

Definition:

Boot Commands

dhcp [loadaddress] [bootfilename]

To use the dhcp command, your DHCP server must be configured with the variables designated in Table 9-5.
Table 9-5: DHCP Ethernet Configuration

Environment
Variable:

Description:

ipaddr

Local IP address for the board, configured by DHCP

e.g., 192.168.1.1

serverip

TFTP/NFS server address value must be configured
after the DHCP IP address is acquired2

e.g., 192.168.1.2

netmask

Net mask, obtained by DHCP

—

gatewayip

Gateway IP address, obtained by DHCP

—

ethport

eTSEC1 default

—

ethaddr3

MAC address

00:80:F9:xx:xx:xx

autoload4

Boot image from TFTP server after DHCP acquisition

no

Value1:

1. Values for ethaddr, netdev and autoload are set by the user.
2. The value obtained by the DHCP server may not be applicable to your development application.
3. Ensure that each MAC address on the network is unique.
4. If autoload is not set or configured to “yes,” ensure that the DHCP provides proper information for
autoboot. If proper autoboot information is not provided, an error may occur.

rarpboot
The rarpboot command boots an image via a network connection using the RARP/TFTP
protocol. If loadaddress or bootfilename is not specified, the environment variables loadaddr
and bootfile are used as the default. To use this command, the environment variables listed
in Table 9-4 must be configured.
Definition:

rarpboot [loadaddress] [bootfilename]

tftpboot
The tftpboot command loads an image via a network connection using the TFTP protocol.
The environment variable’s ipaddr and serverip are used as additional parameters to this
command. If loadaddress or bootfilename is not specified, the environment variables loadaddr and bootfile are used as the default. To use this command, the environment variables
listed in Table 9-4 must be configured.
The port used is defined by the ethport environment variable. If all is selected for ethport,
the TFTP process will cycle through each port until a connection is found or all ports have
failed.
Definition:

9-10

ATCA-9305 User’s Manual

tftpboot [loadaddress] [bootfilename]

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Management Processor Monitor:

File Load Commands

FILE LOAD COMMANDS
The file load commands load files over the serial port.

loadb
The loadb command loads a binary file over the serial port. The command takes two
optional parameters:
offset: The address offset parameter allows the file to be stored in a location different than what is
indicated within the binary file by adding the value off to the file’s absolute address.
baudrate: The baudrate parameter allows the file to be loaded at baud instead of the monitor’s console baudrate.
The file is not automatically executed, the loadb command only loads the file into memory.
Definition:

loadb [off] [baud]

loads
The loads command loads an S-Record file over the serial port. The command takes two
optional parameters:
offset: The address offset parameter allows the file to be stored in a location different than what is
indicated within the S-Record file by adding the value off to the file’s absolute address.
baudrate: The baudrate parameter allows the file to be loaded at baud instead of the monitor’s console baudrate.
The file is not automatically executed, the loads command only loads the file into memory.
Definition:

loads [off] [baud]

MEMORY COMMANDS
The memory commands allow you to manipulate specific regions of memory. For some
memory commands, the data size is determined by the following flags:
Definition: The flag .b is for data in 8-bit bytes.
Definition: The flag .w is for data in 16-bit words.
Definition: The flag .l is for data in 32-bit long words.
These flags are optional arguments and describe the objects on which the command operates. If you do not specify a flag, memory commands default to 32-bit long words. Numeric
arguments are in hexadecimal.

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Management Processor Monitor:

Memory Commands

cmp
The cmp command compares count objects between addr1 and addr2. Any differences are
displayed on the console display.
Definition:

cmp [.b, .w, .l] addr1 addr2 count

cp
The cp command copies count objects located at the source address to the target address.
Note: If the target address is located in the range of the flash device, it will program the flash with count objects
from the source address. The cp command does not erase the flash region prior to copying the data. The flash
region must be manually erased using the erase command prior to using the cp command.

Definition:

cp [.b, .w, .l] source target count

Example: In this example, the cp command is used to copy 0x1000, 32-bit values from address
0x100000 to address 0x80000.
=> cp 100000 80000 1000

find
The find command searches from base_addr to top_addr looking for pattern. For the find
command to work properly, the size of pattern must match the size of the object flag. The -a
option searches for the absence of the specified pattern.
Definition:

find [.b, .w, .l] [-a] base_addr top_addr pattern

Example: In this example, the find command is used to search for the 32-bit pattern 0x12345678 in
the address range starting at 0x40000, and ending at 0x80000.
=> find.1 40000 80000 12345678
Searching from 0x00040000 to 0x00080000
Match found: data = 0x12345678 Adrs = 0x00050a6c
=>

md
The command md displays the contents of memory starting at address. The number of
objects displayed can be defined by an optional third argument, # of objects. The memory’s
numerical value and its ASCII equivalent is displayed.
Definition:

md [.b, .w, .l] address [# of objects]

Example: In this example, the md command is used to display thirty-two 16-bit words starting at the
physical address 0x80000.
=> md.w 80000 20
00080000: ffff ffff ffff ffff ffff ffff ffff ffff
00080010: ffff ffff ffff ffff ffff ffff ffff ffff
00080020: ffff ffff ffff ffff ffff ffff ffff ffff

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Memory Commands

00080030: ffff ffff ffff ffff ffff ffff ffff ffff

................

mm
The mm command modifies memory one object at a time. Once started, the command line
prompts for a new value at the starting address. After a new value is entered, pressing
ENTER auto-increments the address to the next location. Pressing ENTER without entering a
new value leaves the original value for that address unchanged. To exit the mm command,
enter a non-valid hexadecimal value (such as x) followed by ENTER.
Definition:

mm [.b, .w, .l] address

Example: In this example, the mm command is used to write random 8-bit data starting at the physical address 0x80000.
=> mm.b 80000
00080000: ff ? 12
00080001: ff ? 23
00080002: ff ? 34
00080003: ff ? 45
00080004: ff ?
00080005: ff ? x
=> md.b 80000 6
00080000: 12 23 34 45 ff ff
=>

.#4E

nm
The nm command modifies a single object repeatedly. Once started, the command line
prompts for a new value at the selected address. After a new value is entered, pressing
ENTER modifies the value in memory and then the new value is displayed. The command
line then prompts for a new value to be written at the same address. Pressing ENTER without entering a new value leaves the original value unchanged. To exit the nm command,
enter a non-valid hexadecimal value (such as x) followed by ENTER.
Definition:

nm [.b, .w, .l] address

mw
The command mw writes value to memory starting at address. The number of objects modified can be defined by an optional fourth argument, count.
Definition:

mw [.b, .w, .l] address value [count]

Example: In this example, the mw command is used to write the value 0xabba three times starting at
the physical address 0x80000.
=> mw.w 80000 abba 3
=> md 80000
00080000: abbaabba abbaffff ffffffff ffffffff
00080010: ffffffff ffffffff ffffffff ffffffff

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00080020:
00080030:
00080040:
00080050:
00080060:
00080070:

ffffffff
ffffffff
ffffffff
ffffffff
ffffffff
ffffffff

ffffffff
ffffffff
ffffffff
ffffffff
ffffffff
ffffffff

ffffffff
ffffffff
ffffffff
ffffffff
ffffffff
ffffffff

Flash Commands

ffffffff
ffffffff
ffffffff
ffffffff
ffffffff
ffffffff

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FLASH COMMANDS
The flash commands affect the StrataFlash devices on the ATCA-9305 circuit board. There
are four flash banks on the ATCA-9305 board (see “Flash” on page 4-7). They can be
accessed by:
• the individual bank (1, 2, 3 or 4), or
• the address, where both banks are regarded as one contiguous address space
The following flash commands access the individual flash bank as flash bank 1. To access the
individual sectors within each flash bank, the sector numbers start at 0 and end at one less
than the total number of sectors in the bank. For a flash bank with 128 sectors, the following flash commands access the individual sectors as 0 through 127.

cp
The cp command can be used to copy data into the flash device. For the cp command syntax, refer to “Memory Commands” on page 9-11.

erase
The erase command erases the specified area of flash memory.
Definition: Erase all of the sectors in the address range from start to end.
erase start end

Erase all of the sectors SF (first sector) to SL (last sector) in flash bank # N.
erase N:SF[-SL]

Erase all of the sectors in flash bank # N.
erase bank N

Erase all of the sectors in all of the flash banks.
erase all

flinfo
The flinfo command prints out the flash device’s manufacturer, part number, size, number
of sectors, and starting address of each sector.

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EEPROM/I2C Commands

Definition: Print information for all flash memory banks.
flinfo

Print information for the flash memory in bank # N.
flinfo N

protect
The protect command enables or disables the flash sector protection for the specified flash
sector. Protection is implemented using software only. The protection mechanism inside
the physical flash part is not being used.
Definition: Protect all of the flash sectors in the address range from start to end.
protect on start end

Protect all of the sectors SF (first sector) to SL (last sector) in flash bank # N.
protect on N:SF[-SL]

Protect all of the sectors in flash bank # N.
protect on bank N

Protect all of the sectors in all of the flash banks.
protect on all

Remove protection on all of the flash sectors in the address range from start to end.
protect off start end

Remove protection on all of the sectors SF (first sector) to SL (last sector) in flash bank # N.
protect off N:SF[-SL]

Remove protection on all of the sectors in flash bank # N.
protect off bank N

Remove protection on all of the sectors in all of the flash banks.
protect off all

EEPROM/I2C COMMANDS
This section describes commands that allow you to read and write memory on the serial
EEPROMs and I2C devices.

eeprom
The eeprom command reads and writes from the EEPROM. For example:
eeprom read 53 100000 1800 100

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EEPROM/I2C Commands

reads 100 bytes from offset 0x1800 in serial EEPROM 0x53 (right-shifted 7-bit address) and
places it in memory at address 0x100000.
Definition: Read/write cnt bytes from devaddr EEPROM at offset off.
eeprom read devaddr addr off cnt
eeprom write devaddr addr off cnt

icrc32
The icrc32 computes a CRC32 checksum.
Definition:

icrc32 chip address[.0, .1, .2] count

iloop
The iloop command reads in an infinite loop on the specified address range.
Definition:

iloop chip address[.0, .1, .2] [# of objects]

imd

The imd command displays the primary I2C bus memory. For example:
imd 53 1800.2 100

displays 100 bytes from offset 0x1800 of I2C device 0x53 (right-shifted 7-bit address). The
.2 at the end of the offset is the length, in bytes, of the offset information sent to the
device. The serial EEPROMs all have two-byte offset lengths. The Real-Time Clock (RTC) has
a one-byte offset length. The temperature sensors have zero-byte offset lengths.
Definition:

imd chip address[.0, .1, .2] [# of objects]

imm

The imm command modifies the primary I2C memory and automatically increments the
address.
Definition:

imm chip address[.0, .1, .2]

imw
The imw command writes (fills) memory.
Definition:

imw chip address[.0, .1, .2] value [count]

inm

The inm command modifies I2C memory, reads it, and keeps the address.
Definition:

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inm chip address[.0, .1, .2]

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IPMC Commands

iprobe

The iprobe command probes to discover valid primary I2C bus chip addresses.
Definition:

iprobe

IPMC COMMANDS
IPMI Baseboard Management Controller (BMC) watchdog is supported and serviced
throughout the monitor boot process. The BMC watchdog is disabled if the monitor goes to
the monitor prompt.

bootdev
The bootdev command gets or sets the initial boot bank. Get prints out the flash bank set as
initial boot device.
Definition:

bootdev get

The IPMC sets the hardware strapping for the initial boot device.
bootdev set 

Where  is either b0 or b1 for the corresponding flash bank, or b3 to boot from socket
and if a shunt is installed on J9 [1:2].

fru
The fru command opens, closes, saves, sets, shows, dumps, and loads fru data to and from
the IPMC.
Definition:

fru  [ arg1 arg2 … ]
command := [ open | close | save | set | show | dump | load | create ]
fru open 
fru close
fru save
fru set 
fru set   
section := [ chassis | board | product ]
fru set chassis  
field := [ type | part | serial ]
fru set board  
field := [ date | maker | name | serial | part | file ]
fru set product  
field := [ maker | name | part | version |serial | asset | file ]
fru show
fru dump 
fru load 

Set data in the internal use area.

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IPMC Commands

fru set internal   

The fru create command loads a default fru image to a blank fru device.
fru create  default 
fru create    

fruinit
The fruinit command initializes the following fru data fields: part number, build date, and
serial number in the board and product sections.
Definition:

fruinit    [ serial number ]

fruled
The fruled command allows the application programmer to get the status of the red out-ofservice LED or to turn the LED on or off when an application fails to load.
Definition:

fruled get      
fruled set     

Example: Turns the red out-of-service LED on.
fruled set 0 1 0xff 0 2

Turns the red out-of-service LED off.
fruled set 0 1 0 0 2

ipmchpmfw
The ipmchpmfw command restores the previous IPMC firmware from the backup IPMC
firmware stored in the controller. The upgrade argument upgrades the IPMC firmware with
the upgrade image held in memory.
Definition:

ipmchpmfw [restore] [upgrade ]

sensor
The sensor command probes, reads, and prints the sensor information from the IPMI.
Definition:

sensor [probe|read|dump]

Sensor probe prints out each sensor number and name.
sensor probe 

Sensor read prints out the sensor reading for sensor.
sensor read 

Sensor dump prints out the raw Sensor Data Record (SDR) information for sensor.
sensor dump 

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Environment Parameter

ENVIRONMENT PARAMETER COMMANDS
The monitor uses on-board, non-volatile memory for the storage of environment parameters. Environment parameters are stored as ASCII strings with the following format.
=

Some environment variables are used for board configuration and identification by the
monitor. The environment parameter commands deal with the reading and writing of these
parameters. Refer to “MPC8548 Environment Variables” on page 9-26 for a list of monitor
environment variables.
Redundant environment parameters allow you to store a “backup” copy of environment
parameters should they ever become corrupt. The redundant environment parameters are
only used if the main parameters are corrupt.
To save environment variables:
1 Use moninit to save default environment variables to both primary and secondary
environment parameters.
2 Use saveenv to save to the primary environment variables.
3 Set the next save to the secondary image.

printenv
The printenv command displays all of the environment variables and their current values to
the display.
Definition: Print the values of all environment variables.
printenv

Print the values of all environment variable (exact match) ‘name’.
printenv name …

saveenv
The saveenv command writes the environment variables to non-volatile memory.
Definition:

saveenv

setenv
The setenv command adds new environment variables, sets the values of existing environment variables, and deletes unwanted environment variables.
Definition: Set the environment variable name to value or adds the new variable name and value to the
environment.

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Test Commands

setenv name value

Removes the environment variable name from the environment.
setenv name

TEST COMMANDS
The commands described in this section perform diagnostic and memory tests.

diags
The diags command runs the Power-on Self-test (POST).
Definition:

diags

mtest
The mtest command performs a simple SDRAM read/write test.
Definition:

mtest [start [end [pattern]]]

um
The um command is a destructive memory test. Press the ‘q’ key to quit this test; the monitor completes running the most recent iteration, and exits to the default prompt after displaying cumulative results for the completed iterations.
Definition:

um [.b, .w, .l] base_addr [top_addr]

OTHER COMMANDS
This section describes all the remaining commands supported by the ATCA-9305 monitor.

autoscr
The autoscr command runs a script, starting at address addr, from memory.
A valid autoscr header must be present.
Definition:

autoscr [addr]

base
The base command prints or sets the address offset for memory commands.
Definition: Displays the address offset for the memory commands.
base

Sets the address offset for the memory commands to off.
base off

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Other Commands

bdinfo
The bdinfo command displays the Board Information Structure.
Definition:

bdinfo

coninfo
The coninfo command displays the information for all available console devices.
Definition:

coninfo

crc32
The crc32 command computes a CRC32 checksum on count bytes starting at address.
Definition:

crc32 address count

date
The date command will set or get the date and time, and reset the RTC device.
Definition: Set the date and time.
date [MMDDhhmm[[CC]YY][.ss]]

Display the date and time.
date

Reset the RTC device.
date reset

echo
The echo command echoes args to console.
Definition:

echo [args..]

enumpci
The enumpci command enumerates the PCI bus (when the hardware is the PCI Root Complex in the system).
Definition:

enumpci

go
The go command runs an application at address addr, passing the optional argument arg to
the called application.
Definition:

go addr [arg…]

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Other Commands

help
The help (or ?) command displays the online help. Without arguments, all commands are
displayed with a short usage message for each. To obtain more detailed information for a
specific command, enter the desired command as an argument.
Definition:

help [command …]

iminfo
The iminfo command displays the header information for an application image that is
loaded into memory at address addr. Verification of the image contents (magic number,
header, and payload checksums) are also performed.
Definition:

iminfo addr [addr …]

isdram
The isdram command displays the SDRAM configuration information (valid chip values
range from 50 to 57).
Definition:

isdram addr

loop
The loop command executes an infinite loop on address range.
Definition:

loop [.b, .w, .l] address number_of_objects

memmap
The memmap command displays the board’s memory map layout.
Definition:

memmap

moninit
The moninit command resets the NVRAM and serial number, and writes the monitor to
flash. The ATCA-9305 must be booted from the boot socket for this command to function in
the default state. The proper region of flash memory will be unlocked and erased prior to
copying the monitor software into it.
The command flags, .1 or .2, force the monitor to be programmed to a single (.1) bank of
flash or dual (.2) banks of flash. If the command flags are not used, then moninit checks for
the number of banks of flash. If there are two banks of flash, then moninit automatically
programs both banks for redundancy. Also, the serial number can be obtained from the fru
data if “fru” is used as a parameter.
Definition: Initialize environment variables and serial number in NVRAM and copy the monitor from the
socket to NOR (soldered) flash.

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Other Commands

moninit[.1, .2] 

Initialize environment variables and serial number in NVRAM but do not update the monitor
in NOR flash.
moninit[.1, .2]  noburn

Initialize environment variables and serial number in NVRAM and copy the monitor from
 into NOR flash.
moninit[.1, .2]  

pci
The pci command enumerates the PCI bus. It displays enumeration information about each
detected device. The pci command allows you to display values for and access the PCI Configuration Space.
Definition: Display a short or long list of PCI devices on the bus specified by bus.
pci [bus] [long]

Show the header of PCI device bus.device.function.
pci header b.d.f

Display the PCI configuration space (CFG).
pci display[.b, .w, .l] b.d.f [address] [# of objects]

Modify, read, and keep the CFG address.
pci next[.b, .w, .l] b.d.f address

Modify, automatically increment the CFG address.
pci modify[.b, .w, .l] b.d.f address

Write to the CFG address.
pci write[.b, .w, .l] b.d.f address value

phy
The phy command reads or writes to the contents of the PHY registers. The values changed
via this command are not persistent and clear after a hard or soft reset. The port options are
all, eTSEC1, eTSEC2, and base1 and base2 via the switch. “R” reads the register contents at
the address specified. “W” writes the address value to the register address specified. “A”
reads the contents of all registers.
Definition:

phy [port] [R|W|A] (address) (value)

Example: The following is an example of a read from register address 0x1a.
phy eTSEC2 r 0x1a

The following is an example of a write to register address 0x1a where 0 is the data to write.

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Other Commands

phy eTSEC2 w 0x1a 0

ping
The ping command sends a ping over Ethernet to check if the host can be reached. The port
used is defined by the ethport environment variable. If all is selected for ethport, the ping
process cycles through each port until a connection is found or all ports have failed.
Definition:

ping host

reset
The reset command performs a hard reset of the CPU by writing to the reset register on the
board. Without any arguments, the ATCA-9305 CPU is reset.
Definition:

reset

run
The run command runs the commands in an environment variable var.
Definition:

run var [ … ]

Use $ for variable substitution; the syntax “$(variable_name)” should be used for variable
expansion.
Example:

=> setenv cons_opts console=tty0 console=ttyS0,\$(baudrate)
=> printenv cons_opts cons_opts=console=tty0 console=ttyS0,$(baudrate)

Use the \ character to escape execution of the $ as seen in the setenv command above. In
this example, the value for baudrate will be inserted when cons_opts is executed.

script
The script command runs a list of monitor commands out of memory. The list is an ASCII
string of commands separated by the ; character and terminated with the ;; characters.
Emerson Atca 9305 Users Manual Preliminary User’s Manual, #10009109 00

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