Emerson Atca 9305 Users Manual Preliminary User’s Manual, #10009109 00

2015-01-05

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ATCA-9305: ATCA® Blade with Dual Cavium Processors
User’s Manual
from Emerson Network Power™
Embedded Computing
April 2009
The information in this manual has been checked and is believed to be accurate and reliable.
HOWEVER, NO RESPONSIBILITY IS ASSUMED BY EMERSON NETWORK POWER, EMBEDDED
COMPUTING FOR ITS USE OR FOR ANY INACCURACIES. Specifications are subject to change
without notice. EMERSON DOES NOT ASSUME ANY LIABILITY ARISING OUT OF USE OR
OTHER APPLICATION OF ANY PRODUCT, CIRCUIT, OR PROGRAM DESCRIBED HEREIN. This
document does not convey any license under Emerson patents or the rights of others.
Emerson. Consider It Solved is a trademark, and Business-Critical Continuity, Emerson Net-
work Power, and the Emerson Network Power logo are trademarks and service marks of
Emerson Network Power, Embedded Computing, Inc.
© 2009 Emerson Network Power, Embedded Computing, Inc.
Copyright © 2009 Emerson Network Power, Embedded Computing, Inc. All rights reserved.
Revision Level: Principal Changes: Date:
10009109-00 Original release January 2009
10009109-01 Added “GR-1089-CORE Standard” on page -i
Updated “Product Certification” on page 1-4
April 2009
10009109-01 ATCA-9305 User’s Manual i
Regulatory Agency Warnings & Notices
The Emerson ATCA-9305 meets the requirements set forth by the Federal Communications
Commission (FCC) in Title 47 of the Code of Federal Regulations. The following information
is provided as required by this agency.
This device complies with part 15 of the FCC Rules. Operation is subject to the following two
conditions: (1) This device may not cause harmful interference, and (2) this device must
accept any interference received, including interference that may cause undesired opera-
tion.
FCC RULES AND REGULATIONS — PART 15
This equipment has been tested and found to comply with the limits for a Class A digital
device, pursuant to part 15 of the FCC Rules. These limits are designed to provide reason-
able protection against harmful interference when the equipment is operated in a commer-
cial environment. This equipment generates, uses and can radiate radio frequency energy
and, if not installed and used in accordance with the instructions, may cause harmful inter-
ference to radio communications. Operation of this equipment in a residential area is likely
to cause harmful interference, in which case the user will be required to correct the interfer-
ence at his own expense.
Caution: Making changes or modifications to the ATCA-9305 hardware without the explicit consent
of Emerson Network Power could invalidate the user’s authority to operate this equipment.
EMC COMPLIANCE
The electromagnetic compatibility (EMC) tests used an ATCA-9305 model that includes a
front panel assembly from Emerson Network Power.
Caution: For applications where the ATCA-9305 is provided without a front panel, or where the front
panel has been removed, your system chassis/enclosure must provide the required
electromagnetic interference (EMI) shielding to maintain EMC compliance.
GR-1089-CORE STANDARD
Caution: WARNING: The intra-building port(s) of the equipment or subassembly is suitable for
connection to intrabuilding or unexposed wiring or cabling only. The intra-building port(s)
of the equipment or subassembly MUST NOT be metallically connected to interfaces that
connect to the OSP or its wiring. These interfaces are designed for use as intra-building
interfaces only (Type 2 or Type 4 ports as described in GR-1089-CORE, Issue 4) and require
isolation from the exposed OSP cabling. The addition of Primary Protectors is not sufficient
protection in order to connect these interfaces metallically to OSP wiring.
!
!
!
Regulatory Agency Warnings & Notices (continued)
ATCA-9305 User’s Manual 10009109-01
ii
EC Declaration of Conformity
According to EN 45014:1998
Manufacturer’s Name: Emerson Network Power
Embedded Computing
Manufacturer’s Address: 8310 Excelsior Drive
Madison, Wisconsin 53717
Declares that the following product, in accordance with the requirements of 2004/108/EEC, EMC
Directive and 1999/5/EC, RTTE Directive and their amending directives,
Product: ATCA Blade
Model Name/Number: ATCA-9305/10009986-xx
has been designed and manufactured to the following specifications:
EN55022:1998 Information Technology Equipment, Radio disturbance characteristics, Limits and
methods of measurement
EN55024:1998 Information Technology Equipment, Immunity characteristics, Limits and methods
of measurement
EN300386 V.1.3.2:2003-5 Electromagnetic compatibility and radio spectrum matters (ERM);
Telecommunication network equipment; EMC requirements
As manufacturer we hereby declare that the product named above has been designed to comply
with the relevant sections of the above referenced specifications. This product complies with the
essential health and safety requirements of the EMC Directive and RTTE Directive. We have an inter-
nal production control system that ensures compliance between the manufactured products and
the technical documentation.
Issue date: April 7, 2009
Bill Fleury
Compliance Engineer
Regulatory Agency Warnings & Notices (continued)
10009109-01 ATCA-9305 User’s Manual iii
Regulatory Agency Warnings & Notices (continued)
ATCA-9305 User’s Manual 10009109-01
iv
10009109-01 ATCA-9305 User’s Manual v
Contents
1Overview
Components and Features . . . . . . . . . . . 1-1
Functional Overview . . . . . . . . . . . . . . . . 1-3
Additional Information . . . . . . . . . . . . . . 1-4
Product Certification . . . . . . . . . . . . . 1-4
RoHS Compliance. . . . . . . . . . . . . . . . 1-5
Terminology and Notation . . . . . . . .1-6
Technical References. . . . . . . . . . . . . 1-6
2Setup
Electrostatic Discharge . . . . . . . . . . . . . . 2-1
ATCA-9305 Circuit Board . . . . . . . . . . . . 2-1
Connectors . . . . . . . . . . . . . . . . . . . . .2-7
Configuration Header . . . . . . . . . . . . 2-8
ATCA-9305 Setup. . . . . . . . . . . . . . . . . . . 2-8
Power Requirements . . . . . . . . . . . . . 2-9
Environmental Considerations . . . . 2-9
Hot Swap . . . . . . . . . . . . . . . . . . . . . .2-10
Insert a board: . . . . . . . . . 2-11
Remove a board: . . . . . . . 2-11
Troubleshooting. . . . . . . . . . . . . . . . . . . 2-11
Technical Support . . . . . . . . . . . . . .2-11
Product Repair . . . . . . . . . . . . . . . . .2-12
Comments and Suggestions . . . . .2-13
3 Cavium Processor Complex
Cavium CN5860 Processor . . . . . . . . . . . 3-1
Cavium Memory Map . . . . . . . . . . . . 3-2
PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
CN5860 Boot Over PCI . . . . . . . . . . . 3-3
Cavium Reset . . . . . . . . . . . . . . . . . . . 3-4
Cavium Ethernet. . . . . . . . . . . . . . . . . . . . 3-5
Cavium Monitor . . . . . . . . . . . . . . . . . . . . 3-6
Start-up Display . . . . . . . . . . . . . . . . . 3-6
Power-up/Reset Sequence . . . . . . . . 3-6
Diagnostic Tests During Power-up and
Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7
POST Diagnostic Results . . . . . . 3-7
Cavium Environment Variables . . . . 3-8
Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
DDR2 SDRAM . . . . . . . . . . . . . . . . . . .3-9
RLDRAM . . . . . . . . . . . . . . . . . . . . . . . . 3-9
I2C EEPROM. . . . . . . . . . . . . . . . . . . . .3-9
Flash, 512 KB x 8. . . . . . . . . . . . . . . .3-10
Flash, 4 MB x 16 . . . . . . . . . . . . . . . .3-10
StratixGX Interconnect . . . . . . . . . . . . . 3-10
PLD Registers . . . . . . . . . . . . . . . . . . 3-10
Data Registers . . . . . . . . . . . . . 3-10
Address Registers . . . . . . . . . . 3-12
Control Register. . . . . . . . . . . . 3-12
Version Register. . . . . . . . . . . . 3-13
Scratch Register. . . . . . . . . . . . 3-13
Headers and Connectors. . . . . . . . . . . . 3-14
COP/JTAG Headers . . . . . . . . . . . . . 3-14
Console Serial Ports (optional) . . . 3-15
4 Management Complex
MPC8548 Processor. . . . . . . . . . . . . . . . . .4-2
MPC8548 Memory Map . . . . . . . . . . 4-2
Chip Selects . . . . . . . . . . . . . . . . . . . . 4-5
Reset Diagram . . . . . . . . . . . . . . . . . . 4-6
Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-7
SDRAM. . . . . . . . . . . . . . . . . . . . . . . . . 4-7
Flash. . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7
512 KB x 8 (optional). . . . . . . . . 4-7
4M x 16 . . . . . . . . . . . . . . . . . . . . 4-7
1 GB x 16 . . . . . . . . . . . . . . . . . . . 4-8
64 MB x 16. . . . . . . . . . . . . . . . . . 4-8
PCI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-8
PCI Express . . . . . . . . . . . . . . . . . . . . . 4-8
I2C Interface . . . . . . . . . . . . . . . . . . . . . . . .4-9
Management Processor Header and Serial
Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-9
JTAG/COP Interface (optional) . . . . 4-9
Serial Debug Port. . . . . . . . . . . . . . . 4-10
5 Management Processor
CPLD
MPC8548 PLD Register Summary . . . . . .5-1
Product ID. . . . . . . . . . . . . . . . . . . . . . 5-2
Hardware Version . . . . . . . . . . . . . . . 5-2
PLD Version. . . . . . . . . . . . . . . . . . . . . 5-3
PLL Reset Configuration . . . . . . . . . . 5-3
Hardware Configuration 0 . . . . . . . . 5-3
Jumper Settings . . . . . . . . . . . . . . . . . 5-4
LED . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4
Reset Event . . . . . . . . . . . . . . . . . . . . . 5-5
Reset Command 1. . . . . . . . . . . . . . . 5-5
Reset Command 2. . . . . . . . . . . . . . . 5-6
Reset Command 3. . . . . . . . . . . . . . . 5-6
Contents (continued)
ATCA-9305 User’s Manual 10009109-01
vi
Reset Command 4 . . . . . . . . . . . . . . . 5-7
Reset Command 5 . . . . . . . . . . . . . . . 5-7
Reset Command Sticky #1 . . . . . . . . 5-7
Reset Command Sticky #2 . . . . . . . . 5-8
Boot Device Redirection . . . . . . . . . . 5-8
Miscellaneous Control. . . . . . . . . . . . 5-9
Low Frequency Timer 1 and 2 . . . . . 5-9
RTM GPIO State . . . . . . . . . . . . . . . .5-10
RTM GPIO Control . . . . . . . . . . . . . .5-10
RTM Status . . . . . . . . . . . . . . . . . . . .5-10
Cavium 1 C_MUL Clock Divisor Control
5-11
Cavium 2 C_MUL Clock Divisor Control
5-11
JTAG . . . . . . . . . . . . . . . . . . . . . . . . . .5-12
Cavium GPIO Control . . . . . . . . . . .5-12
Cavium GPIO Data Out . . . . . . . . . .5-13
Cavium GPIO Data In . . . . . . . . . . . .5-13
IPMP/IPMC GPIO Control . . . . . . . .5-14
LPC Bus Control . . . . . . . . . . . . . . . .5-14
LPC Data. . . . . . . . . . . . . . . . . . . . . . .5-14
Serial IRQ Interrupt 1 . . . . . . . . . . .5-15
Serial IRQ Interrupt 2 . . . . . . . . . . .5-15
6 Ethernet Interface
Broadcom BCM56802 Switch . . . . . . . . .6-1
Ethernet Switching. . . . . . . . . . . . . . . . . . .6-1
Ethernet Transceivers . . . . . . . . . . . . 6-2
Ethernet Switch Ports . . . . . . . . . . . . 6-2
VLAN Setup . . . . . . . . . . . . . . . . . . . . . 6-3
MPC8548 Management Processor Ethernet
Address. . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-3
Front Panel Ethernet Ports . . . . . . . . 6-4
7 System Management
IPMC Overview . . . . . . . . . . . . . . . . . . . . . .7-1
IPMI Messaging. . . . . . . . . . . . . . . . . . . . . .7-2
IPMI Completion Codes . . . . . . . . . . 7-4
IPMB Protocol . . . . . . . . . . . . . . . . . . . . . . .7-5
SIPL Protocol . . . . . . . . . . . . . . . . . . . . . . . .7-6
Message Bridging . . . . . . . . . . . . . . . . . . . .7-7
Standard Commands. . . . . . . . . . . . . . . . .7-9
OEM Boot Options . . . . . . . . . . . . . . . . . 7-11
IPMC Watchdog Timer Commands. . . 7-12
Watchdog Timer Actions . . . . . . . .7-12
Watchdog Timer Use Field and
Expiration Flags . . . . . . . . . . . . . . . . 7-12
Using the Timer Use Field and
Expiration Flags . . . . . . . . . . . . 7-13
Watchdog Timer Event Logging . . 7-13
Monitor Support for Watchdog
Timer . . . . . . . . . . . . . . . . . . . . . 7-13
Reset Watchdog Timer Command7-14
Set Watchdog Timer Command. . 7-14
Get Watchdog Timer Command . 7-16
FRU LEDs . . . . . . . . . . . . . . . . . . . . . . . . . 7-18
Get FRU LED Properties Command7-19
Get LED Color Capabilities Command .
7-19
Set FRU LED State Command . . . . 7-21
Get FRU LED State Command . . . . 7-22
Vendor Commands . . . . . . . . . . . . . . . . 7-24
Get Status . . . . . . . . . . . . . . . . . . . . . 7-25
Get Serial Interface Properties . . . 7-27
Set Serial Interface Properties . . . . 7-28
Get Debug Level . . . . . . . . . . . . . . . 7-29
Set Debug Level . . . . . . . . . . . . . . . . 7-29
Get Hardware Address . . . . . . . . . . 7-30
Set Hardware Address . . . . . . . . . . 7-30
Get Handle Switch. . . . . . . . . . . . . . 7-31
Set Handle Switch . . . . . . . . . . . . . . 7-31
Get Payload Communication Time-Out
7-32
Set Payload Communication Time-Out
7-32
Enable Payload Control . . . . . . . . . 7-32
Disable Payload Control . . . . . . . . . 7-33
Reset IPMC . . . . . . . . . . . . . . . . . . . . 7-33
Hang IPMC . . . . . . . . . . . . . . . . . . . . 7-33
Bused Resource . . . . . . . . . . . . . . . . 7-34
Bused Resource Status . . . . . . . . . . 7-34
Graceful Reset . . . . . . . . . . . . . . . . . 7-35
Diagnostic Interrupt Results . . . . . 7-36
Get Payload Shutdown Time-Out. 7-36
Set Payload Shutdown Time-Out . 7-37
Set Local FRU LED State . . . . . . . . . 7-38
Get Local FRU LED State . . . . . . . . . 7-39
Update Discrete Sensor . . . . . . . . . 7-40
Update Threshold Sensor. . . . . . . . 7-40
Boot Device Redirection (BDR) . . . . . . 7-41
Message Listeners . . . . . . . . . . . . . . . . . 7-43
Add Message Listener. . . . . . . . . . . 7-44
Remove Message Listener . . . . . . . 7-44
Contents (continued)
10009109-01 ATCA-9305 User’s Manual vii
Get Message Listener List . . . . . . . .7-45
System Firmware Progress Sensor . . . 7-45
Entities and Entity Associations . . . . . . 7-46
Sensors and Sensor Data Records . . . . 7-48
FRU Inventory . . . . . . . . . . . . . . . . . . . . . 7-50
E-Keying . . . . . . . . . . . . . . . . . . . . . . . . . . 7-51
Base Point-to-Point Connectivity .7-52
HPM.1 Firmware Upgrade. . . . . . . . . . . 7-52
HPM.1 Reliable Field Upgrade
Procedure . . . . . . . . . . . . . . . . . . . . .7-53
IPMC Headers . . . . . . . . . . . . . . . . . . . . . 7-53
8 Back Panel Connectors
Zone 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-1
Zone 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-2
Zone 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-3
9 Management Processor
Monitor
Command-Line Features. . . . . . . . . . . . . .9-1
Basic Operation. . . . . . . . . . . . . . . . . . . . . .9-3
Power-up/Reset Sequence. . . . . . . . 9-3
POST Diagnostic Results. . . . . . . . . . 9-4
Monitor SDRAM Usage . . . . . . . . . . . 9-5
Monitor Recovery and Updates . . . . . . . .9-5
Recovering the Monitor . . . . . . . . . . 9-6
Resetting Environment Variables . . 9-6
Updating the Monitor via TFTP . . . . 9-6
Monitor Command Reference . . . . . . . . .9-7
Command Syntax. . . . . . . . . . . . . . . . 9-7
Command Help . . . . . . . . . . . . . . . . . 9-8
Typographic Conventions . . . . . . . . 9-8
Boot Commands. . . . . . . . . . . . . . . . . . . . .9-8
bootd . . . . . . . . . . . . . . . . . . . . . . . . . . 9-8
bootelf . . . . . . . . . . . . . . . . . . . . . . . . . 9-8
bootm . . . . . . . . . . . . . . . . . . . . . . . . . 9-8
bootp . . . . . . . . . . . . . . . . . . . . . . . . . . 9-8
bootv . . . . . . . . . . . . . . . . . . . . . . . . . . 9-9
bootvx . . . . . . . . . . . . . . . . . . . . . . . . . 9-9
dhcp . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-9
rarpboot. . . . . . . . . . . . . . . . . . . . . . .9-10
tftpboot . . . . . . . . . . . . . . . . . . . . . . .9-10
File Load Commands . . . . . . . . . . . . . . . 9-11
loadb . . . . . . . . . . . . . . . . . . . . . . . . .9-11
loads . . . . . . . . . . . . . . . . . . . . . . . . . .9-11
Memory Commands . . . . . . . . . . . . . . . 9-11
cmp . . . . . . . . . . . . . . . . . . . . . . . . . . 9-12
cp . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-12
find . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-12
md . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-12
mm. . . . . . . . . . . . . . . . . . . . . . . . . . . 9-13
nm . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-13
mw . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-13
Flash Commands . . . . . . . . . . . . . . . . . . 9-14
cp . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-14
erase . . . . . . . . . . . . . . . . . . . . . . . . . 9-14
flinfo. . . . . . . . . . . . . . . . . . . . . . . . . . 9-14
protect. . . . . . . . . . . . . . . . . . . . . . . . 9-15
EEPROM/I2C Commands . . . . . . . . . . . 9-15
eeprom . . . . . . . . . . . . . . . . . . . . . . . 9-15
icrc32. . . . . . . . . . . . . . . . . . . . . . . . . 9-16
iloop. . . . . . . . . . . . . . . . . . . . . . . . . . 9-16
imd. . . . . . . . . . . . . . . . . . . . . . . . . . . 9-16
imm . . . . . . . . . . . . . . . . . . . . . . . . . . 9-16
imw . . . . . . . . . . . . . . . . . . . . . . . . . . 9-16
inm . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-16
iprobe . . . . . . . . . . . . . . . . . . . . . . . . 9-17
IPMC Commands . . . . . . . . . . . . . . . . . . 9-17
bootdev. . . . . . . . . . . . . . . . . . . . . . . 9-17
fru. . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-17
fruinit . . . . . . . . . . . . . . . . . . . . . . . . . 9-18
fruled . . . . . . . . . . . . . . . . . . . . . . . . . 9-18
ipmchpmfw . . . . . . . . . . . . . . . . . . . 9-18
sensor . . . . . . . . . . . . . . . . . . . . . . . . 9-18
Environment Parameter Commands . 9-19
printenv. . . . . . . . . . . . . . . . . . . . . . . 9-19
saveenv . . . . . . . . . . . . . . . . . . . . . . . 9-19
setenv . . . . . . . . . . . . . . . . . . . . . . . . 9-19
Test Commands . . . . . . . . . . . . . . . . . . . 9-20
diags. . . . . . . . . . . . . . . . . . . . . . . . . . 9-20
mtest . . . . . . . . . . . . . . . . . . . . . . . . . 9-20
um . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-20
Other Commands. . . . . . . . . . . . . . . . . . 9-20
autoscr. . . . . . . . . . . . . . . . . . . . . . . . 9-20
base . . . . . . . . . . . . . . . . . . . . . . . . . . 9-20
bdinfo . . . . . . . . . . . . . . . . . . . . . . . . 9-21
coninfo . . . . . . . . . . . . . . . . . . . . . . . 9-21
crc32 . . . . . . . . . . . . . . . . . . . . . . . . . 9-21
date . . . . . . . . . . . . . . . . . . . . . . . . . . 9-21
echo . . . . . . . . . . . . . . . . . . . . . . . . . . 9-21
enumpci . . . . . . . . . . . . . . . . . . . . . . 9-21
go . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-21
help . . . . . . . . . . . . . . . . . . . . . . . . . . 9-22
Contents (continued)
ATCA-9305 User’s Manual 10009109-01
viii
iminfo. . . . . . . . . . . . . . . . . . . . . . . . .9-22
isdram . . . . . . . . . . . . . . . . . . . . . . . .9-22
loop. . . . . . . . . . . . . . . . . . . . . . . . . . .9-22
memmap. . . . . . . . . . . . . . . . . . . . . .9-22
moninit . . . . . . . . . . . . . . . . . . . . . . .9-22
pci . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-23
phy . . . . . . . . . . . . . . . . . . . . . . . . . . .9-23
ping. . . . . . . . . . . . . . . . . . . . . . . . . . .9-24
reset . . . . . . . . . . . . . . . . . . . . . . . . . .9-24
run. . . . . . . . . . . . . . . . . . . . . . . . . . . .9-24
script. . . . . . . . . . . . . . . . . . . . . . . . . .9-24
showmac . . . . . . . . . . . . . . . . . . . . . .9-24
showpci . . . . . . . . . . . . . . . . . . . . . . .9-24
sleep. . . . . . . . . . . . . . . . . . . . . . . . . . 9-25
switch_reg . . . . . . . . . . . . . . . . . . . . 9-25
version. . . . . . . . . . . . . . . . . . . . . . . . 9-25
vlan. . . . . . . . . . . . . . . . . . . . . . . . . . . 9-25
MPC8548 Environment Variables . . . . 9-26
Troubleshooting. . . . . . . . . . . . . . . . . . . 9-28
Download Formats. . . . . . . . . . . . . . . . . 9-28
Binary. . . . . . . . . . . . . . . . . . . . . . . . . 9-29
Motorola S-Record . . . . . . . . . . . . . 9-29
10Acronyms
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Figures
Figure 1-1: General System Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
Figure 2-1: ATCA-9305 Front Panel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
Figure 2-2: Component Map, Top (Rev. 01) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
Figure 2-3: Component Map, Bottom (Rev. 01). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
Figure 2-4: LED, Fuse and Switch Locations, Top . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
Figure 2-5: LED and Switch Locations, Bottom. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
Figure 2-6: Configuration Header, J9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
Figure 2-7: Air Flow Graph . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
Figure 2-8: Serial Number and Product ID on Top Side. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12
Figure 3-1: Cavium Processor Complex Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
Figure 3-2: CN5860 Reset Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
Figure 3-3: Example Cavium CN5860 Monitor Start-up Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6
Figure 3-4: Power-up/Reset CN5860 Boot Sequence Flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7
Figure 4-1: MPC8548 Management Processor Complex Block Diagram. . . . . . . . . . . . . . . . . . . . . 4-1
Figure 4-2: MPC8548 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3
Figure 4-3: MPC8548 Reset Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6
Figure 6-1: Ethernet Switching Interface Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2
Figure 7-1: IPMC Connections Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2
Figure 7-2: Extension Command Request Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-7
Figure 7-3: Extension Command Response Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-7
Figure 7-4: Boot Device Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-42
Figure 7-5: Boot Redirection Control Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-42
Figure 7-6: IPMB Entity Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-47
Figure 8-1: Zone 1 Connector, P10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1
Figure 8-2: Zone 2 and 3 Connectors; J23, J30-J31 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2
Figure 8-3: Zone 3 Connector, J33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4
Figure 9-1: Example MPC8548 Monitor Start-up Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2
Figure 9-2: Power-up/Reset Sequence Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4
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Tables
Table 1-1: Regulatory Agency Compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
Table 1-2: Technical References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
Table 2-1: Circuit Board Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
Table 2-2: Typical Power Requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
Table 2-3: Environmental Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
Table 3-1: CN5860 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
Table 3-2: Cavium Address Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
Table 3-3: Ethernet Port Address. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5
Table 3-4: POST Diagnostic Results–Bit Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
Table 3-5: Standard Cavium Environment Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
Table 3-6: Cavium NVRAM Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
Table 3-7: CN5860 Processor COP/JTAG Headers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14
Table 3-8: CN5860 Processor Debug Headers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15
Table 4-1: MPC8548 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
Table 4-2: MPC8548 Address Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3
Table 4-3: Device Chip Selects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5
Table 4-4: PCI Device Interrupts and ID Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8
Table 4-5: I2C Device Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9
Table 4-6: MPC8548 NVRAM Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9
Table 4-7: Serial Debug Connector, P2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9
Table 4-8: Serial Debug Connector, P7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10
Table 5-1: PLD Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
Table 5-2: Low Frequency Timer Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10
Table 6-1: Ethernet Switch Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2
Table 6-2: VLAN Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3
Table 6-3: Ethernet Port Address. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4
Table 6-4: Front Panel Ethernet Ports. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4
Table 7-1: Network Function Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3
Table 7-2: Completion Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4
Table 7-3: Format for IPMI Request Message . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5
Table 7-4: Format for IPMI Response Message . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-6
Table 7-5: IPMC IPMI Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-9
Table 7-6: Emerson Boot Option Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-11
Table 7-7: IPMC Watchdog Timer Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-12
Table 7-8: Reset Watchdog Timer Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-14
Table 7-9: Set Watchdog Timer Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-15
Table 7-10: Get Watchdog Timer Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-16
Table 7-11: FRU LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-18
Table 7-12: Get FRU LED Properties Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-19
Table 7-13: Get LED Color Capabilities Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-19
Tables (continued)
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Table 7-14: Set FRU LED State Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-21
Table 7-15: Get FRU LED State Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-22
Table 7-16: Vendor Command Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-24
Table 7-17: Get Status Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-25
Table 7-18: Get Serial Interface Properties Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-27
Table 7-19: Set Serial Interface Properties Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-28
Table 7-20: Get Debug Level Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-29
Table 7-21: Set Debug Level Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-29
Table 7-22: Get Hardware Address Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-30
Table 7-23: Set Hardware Address Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-30
Table 7-24: Get Handle Switch Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-31
Table 7-25: Set Handle Switch Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-31
Table 7-26: Get Payload Communication Time-Out Command . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-32
Table 7-27: Set Payload Communication Time-Out Command . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-32
Table 7-28: Enable Payload Control Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-32
Table 7-29: Disable Payload Control Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-33
Table 7-30: Reset IPMC Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-33
Table 7-31: Hang IPMC Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-33
Table 7-32: Bused Resource Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-34
Table 7-33: Bused Resource Status Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-35
Table 7-34: Graceful Reset Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-36
Table 7-35: Diagnostic Interrupt Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-36
Table 7-36: Get Payload Shutdown Time-Out Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-37
Table 7-37: Set Payload Shutdown Time-Out Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-37
Table 7-38: Set Local FRU LED State Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-38
Table 7-39: Get Local FRU LED State Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-39
Table 7-40: Update Discrete Sensor Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-40
Table 7-41: Update Threshold Sensor Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-40
Table 7-42: Add Message Listener Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-44
Table 7-43: Remove Message Listener Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-44
Table 7-44: Get Message Listener List Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-45
Table 7-45: Update System Firmware Progress Sensor Command. . . . . . . . . . . . . . . . . . . . . . . . . 7-46
Table 7-46: IPMI Threshold Sensors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-48
Table 7-47: IPMI Discrete Sensors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-48
Table 7-48: Event Message Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-49
Table 7-49: FRU Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-50
Table 7-50: Link Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-52
Table 7-51: IPMP CPLD JP1 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-53
Table 7-52: IPMP EIA-232 P4 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-53
Table 8-1: Zone 1 Connector, P10 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1
Table 8-2: Zone 2 Connector, J23 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3
Tables (continued)
10009109-01 ATCA-9305 User’s Manual xiii
Table 8-3: Zone 3 Connector, J30 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3
Table 8-4: Zone 3 Connector, J31 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4
Table 8-5: Zone 3 Connector, J33 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4
Table 9-1: Debug LED Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2
Table 9-2: POST Diagnostic Results–Bit Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-5
Table 9-3: Monitor Address per Flash Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-6
Table 9-4: Static IP Ethernet Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-9
Table 9-5: DHCP Ethernet Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-10
Table 9-6: Standard Environment Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-26
Table 9-7: Optional Environment Variables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-28
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Registers
Register 3-1: Data 31:24 (0x0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
Register 3-2: Data 23:16 (0x1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11
Register 3-3: Data 15:8 (0x2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11
Register 3-4: Data 7:0 (0x3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11
Register 3-5: Address 9:8 (0x4). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12
Register 3-6: Address 7:0 (0x5). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12
Register 3-7: Control (0x6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12
Register 3-8: Version (0x7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13
Register 3-9: Scratch (0x8-0x3F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13
Register 5-1: Product ID (0x00) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
Register 5-2: Hardware Version (0x04) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
Register 5-3: PLD Version (0x08) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3
Register 5-4: PLL Reset Configuration (0x0C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3
Register 5-5: Hardware Configuration 0 (0x10). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4
Register 5-6: Jumper Settings (0x18). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4
Register 5-7: LED (0x1C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5
Register 5-8: Reset Event (0x20) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5
Register 5-9: Reset Command 1 (0x24) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6
Register 5-10: Reset Command 2 (0x28) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6
Register 5-11: Reset Command 3 (0x2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6
Register 5-12: Reset Command 4 (0x30) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7
Register 5-13: Reset Command 5 (0x34) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7
Register 5-14: Reset Command Sticky #1 (0x38) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8
Register 5-15: Reset Command Sticky #2 (0x3C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8
Register 5-16: Boot Device Redirection (0x50) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9
Register 5-17: Miscellaneous Control (0x54) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9
Register 5-18: RTM GPIO State (0x60). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10
Register 5-19: RTM GPIO Control (0x64). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10
Register 5-20: RTM Control (0x68). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11
Register 5-21: Cavium 1 C_MULL Clock Divisor Control (0x70) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11
Register 5-22: Cavium 2 C_MULL Clock Divisor Control (0x74) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12
Register 5-23: JTAG (0x78). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12
Register 5-24: Cavium GPIO Control (0x80) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12
Register 5-25: Cavium GPIO Data Out (0x84) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13
Register 5-26: Cavium GPIO Data In (0x88) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13
Register 5-27: IPMP/IPMC GPIO Control (0x8C). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-14
Register 5-28: LPC Bus (0xD0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-14
Register 5-29: LPC Data (0xD4). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15
Register 5-30: Serial IRQ Interrupts 1 (0xD8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15
Register 5-31: Serial IRQ Interrupts 2 (0xDC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15
ATCA-9305 User’s Manual 10009109-01
ii
(blank page)
10009109-01 ATCA-9305 User’s Manual 1-1
Section 1
Overview
The ATCA-9305 is an Advanced Telecom Computing Architecture (AdvancedTCA®, ATCA®)
blade based on dual Cavium OCTEON™ CN5860 processors and the Freescale™ Semicon-
ductor MPC8548 management processor. This blade is targeted at security and packet-pro-
cessing applications in the wireless and transport market segments. These markets include
data-plane packet-processor, security co-processor, video compression, and pattern match-
ing.
The ATCA-9305 complies with the SCOPE recommended profile for central office ATCA sys-
tems, PICMG® 3.0 ATCA mechanical specifications, E-keying, and Hot Swap.
COMPONENTS AND FEATURES
The following is a brief summary of the ATCA-9305 hardware components and features:
Cavium Processor : The Cavium CN5860 processor is a highly programmable, high-performance 16-core archi-
tecture operating up to 800 MHz.
Management Processor:
The Freescale PowerQUICC™ III MPC8548 processor is a 32-bit enhanced e500 core operat-
ing at 1 GHz.
Ethernet Switch: The Broadcom® BCM56802 is a sixteen-port, 10 GbE switch which interconnects the pro-
cessors using SPI to XAUI™ bridges. The functionality includes both 10-Gbps XAUI and 1-
Gbps SGMII PHY interfaces.
Stratix™ GX Bridge: There are two packet routing Altera® SPI-4.2 high-speed interconnect to XAUI bridges per
CN5860 processor.
Ethernet: 10/100/1000BASE-T Ethernet ports are accessible via the front panel RJ45 connectors and
through the base channel on the back panel. The 10 GbE ports route to the back panel
through the fabric and RTM connectors.
Serial Port: The front panel serial port (MGT CSL) connects to the MPC8548 management processor.
System Management: This product supports an Intelligent Platform Management Controller (IPMC) based on a
proprietary BMR-H8S-AMCc® reference design from Pigeon Point Systems. The IPMC has
an inter-integrated circuit (I2C) controller to support an Intelligent Management Platform
Bus (IPMB) that routes to the AdvancedTCA connector. The IPMB allows for features such as
remote shutdown, remote reset, payload voltage monitoring, temperature monitoring,
and access to Field Replaceable Unit (FRU) data.
PCI/PCIe: The PCI bus allows for read/write memory access between the MPC8548 processor, Ether-
net switch, and Cavium processors. The four lane PCI Express® (PCIe) routes between the
MPC8548 and the optional RTM.
Overview: Components and Features
ATCA-9305 User’s Manual 10009109-01
1-2
Real-time Clock: The STMicroelectronics M41T00S RTC provides counters for seconds, minutes, hours, day,
date, month, years, and century. The M41T00S serial interface supports I2C bus and has a
super-cap backup capable of maintaining the clock for a minimum of two hours.
Software: The Cavium CN5860 processor provides a GNU compiler that implements the MIPS64 Rel 2
instruction set in addition to the specialized instructions and a Linux® Board Specific Pack-
age (BSP) including the IP-stack optimization. The CN5860 also provides libraries that take
advantage of the chip’s hardware acceleration for certain security protocols.
RTM (optional): This blade supports a custom Rear Transition Module (RTM) with the following I/O:
• Either two or six 10GbE connections
• One x4 PCI Express port from the MPC8548
• Connections for an MMC to control Hot Swap
• MPC8548 console port
For more detailed information, see the ATCA-9305 Rear Transition Module User’s Manual.
Overview: Functional Overview
10009109-01 ATCA-9305 User’s Manual 1-3
FUNCTIONAL OVERVIEW
The following block diagram provides a functional overview for the ATCA-9305:
Figure 1-1: General System Block Diagram
Console
(ENG use only)
PCI Bus
10G - 4 PORTS
RJ45 RJ45
BCM5482
1 2
Base
3 2 1 0 3 2 1 0
FC2 FC1
10G Fabric
J23
I2C
EEPROM
COP/
JTAG
NAND
Flash
1GB
x 16
BCM56802
XAUI 10 Gb
Switch
5 XAUI
SGMII
2
SGMII
1
XAUI
8 7
XAUI 13
XAUI 14
3
SGMII
4
SGMII
PCI Bus
IDSEL13
6 XAUI
Mag
KSL
CPLD
Latched Adrs
A/D
IPMB
P10
Console
(ENG use only)
Cavium
Octeon
CN5860
Processor 1
SPI-1
PCI
Bus
IDSEL11
Serial 0D1_DDR2
I2C
Serial 1
SPI-0
Adrs/Data
Console
BCM5461S
Stratix II GX
#2
I2C
EEPROM
RTC
MPC8548
Management
Processor
RLDRAM
64MB
Local Bus
Addr/Data
J31
10G - 2 PORTS
J30
Socketed
ROM
512KB
x 8
COP/
JTAG
To RTM
XAUI
11-12 15 -18
J33
RTM RST
12V Hot Swap
RTM Console
PQ I2C
Serial CFG
EEPROM
RLDRAM
64MB
PQ DDR2
SDRAM
NOR
Flash
4M
x 16
P1 DDR
SDRAM
P2 DDR2
SDRAM
RLDRAM
64MB
RLDRAM
64MB
I2C
EEPROM
RLDRAM
64MB
RLDRAM
64MB
RLDRAM
64MB
RLDRAM
64MB
Stratix II GX
#1
Stratix II GX
#4
BCM5461S BCM5461S
Mag
Mag Mag
I2C
EEPROM
COP/JTAG
PCIe x4
I2CI2C
Stratix II GX
#3
Cavium
Octeon
CN5860
Processor 2
Serial 0
Serial 1
D1_DDR2
I2C
SPI-1
SPI-0
Local Bus
Addr/Data
PCI
Bus
IDSEL12
NOR
Flash
512Mb or
64MB x 16
Socketed
ROM
512K
x 8
NOR
Flash
4M
x 8
Socketed
ROM
512K
x 8
NOR
Flash
4M
x 8
Overview: Additional Information
ATCA-9305 User’s Manual 10009109-01
1-4
ADDITIONAL INFORMATION
This section lists the ATCA-9305 hardware’s regulatory certifications and briefly discusses
the terminology and notation conventions used in this manual. It also lists general technical
references.
Mean time between failures (MTBF) has been calculated at 439,924 hours using the Telcor-
dia SR-332, Issue 1 (Reliability Prediction for Electronic Equipment), method 2 at 30° C.
Product Certification
The ATCA-9305 hardware has been tested to comply with various safety, immunity, and
emissions requirements as specified by the Federal Communications Commission (FCC),
Underwriters Laboratories (UL), and others. The following table summarizes this compli-
ance:
Table 1-1: Regulatory Agency Compliance
Type: Specification:
Safety IEC60950/EN60950 – Safety of Information Technology Equipment
(Western Europe)
UL60950, CSA C22.2 No. 60950 – Safety of Information Technology
Equipment, including Electrical Business Equipment (BI-National)
GR1089-CORE
Global IEC – CB Scheme Report IEC 60950, all country deviations
Environmental NEBS: Telecordia GR-63 –
Section 4.1.1 Transportation and Storage Environmental Criteria;
Section 4.1.2 Operating Temperature and Humidity;
Section 4.1.3 Altitude;
Section 4.1 4 Temperature Margins;
Section 4.4.1 Earthquake Environment;
Section 4.4.4 Office Vibration:
Section 4.4.5 Transportation Vibration
Overview: Additional Information
10009109-01 ATCA-9305 User’s Manual 1-5
Emerson maintains test reports that provide specific information regarding the methods
and equipment used in compliance testing. Unshielded external I/O cables, loose screws, or
a poorly grounded chassis may adversely affect the ATCA-9305 hardware’s ability to comply
with any of the stated specifications.
The UL web site at ul.com has a list of Emerson’s UL certifications. To find the list, search in
the online certifications directory using Emerson’s UL file number, E190079. There is a list
for products distributed in the United States, as well as a list for products shipped to Can-
ada. To find the ATCA-9305, search in the list for 10009986-xx, where xx changes with each
revision of the printed circuit board.
The Ethernet connection of the equipment or subassembly must be connected with
shielded cables that are grounded at both ends.
RoHS Compliance
The ATCA-9305 is compliant with the European Union’s RoHS (Restriction of use of Hazard-
ous Substances) directive created to limit harm to the environment and human health by
restricting the use of harmful substances in electrical and electronic equipment. Effective
July 1, 2006, RoHS restricts the use of six substances: cadmium (Cd), mercury (Hg), hexava-
lent chromium (Cr (VI)), polybrominated biphenyls (PBBs), polybrominated diphenyl ethers
(PBDEs) and lead (Pb). Configurations that are RoHS compliant are built with lead-free sol-
der.
To obtain a certificate of conformity (CoC) for the ATCA-9305, send an e-mail to
sales@artesyncp.com or call 1-800-356-9602. Have the part number(s)
(e.g., C000####-##) for your configuration(s) available when contacting Emerson.
EMC FCC Part 15, Class A– Title 47, Code of Federal Regulations, Radio
Frequency Devices
ICES 003, Class A – Radiated and Conducted Emissions, Canada
NEBS: Telecordia GR-1089 level 3 – Emissions and Immunity (circuit pack
level testing only)
EN55022 – Information Technology Equipment, Radio Disturbance
Characteristics, Limits and Methods of Measurement
EN55024 – Information Technology Equipment, Immunity
Characteristics, Limits and Methods of Measurement
ETSI EN300386 – Electromagnetic Compatibility and Radio Spectrum
Matters (ERM), Telecommunication Network Equipment,
Electromagnetic Compatibility (EMC) Requirements
AS/NZS 3548 003, Class A – Standard for radiated and conducted
emissions for Australia and New Zealand
Type: Specification: (continued)
Overview: Additional Information
ATCA-9305 User’s Manual 10009109-01
1-6
Terminology and Notation
Active low signals: An active low signal is indicated with an asterisk * after the signal name.
Byte, word: Throughout this manual byte refers to 8 bits, word refers to 16 bits, and long word refers to
32 bits, double long word refers to 64 bits.
PLD: This manual uses the acronym, PLD, as a generic term for programmable logic device (also
known as FPGA, CPLD, EPLD, etc.).
Radix 2 and 16: Hexadecimal numbers end with a subscript 16. Binary numbers are shown with a
subscript 2.
Technical References
Further information on basic operation and programming of the ATCA-9305 components
can be found in documents listed in Table 1-2.
Table 1-2: Technical References
Device /
Interface: Document: 1
ATCA AdvancedTCA® Base Specification
(PICMG® 3.0 Revision 2.0 March 18, 2005)
Engineering Change Notice 3.0-1.0-001
(PICMG® 3.0 R2.0: ECN 3.0-2.0-001 June 15, 2005)
Ethernet/Fibre Channel for AdvancedTCA™ Systems
(PICMG® 3.1 Revision 1.0 January 22, 2003)
http://www.picmg.org
CPU
CN5860
MPC8548
Cavium Networks OCTEON™ Plus CN58XX Hardware Reference Manual
(Cavium Networks, CN58XX-HM-1.2 Sept. 2008)
http:/www.caviumnetworks.com
MPC8548E PowerQUICC™ III Integrated Processor Family Reference Manual
(Freescale™ Semiconductor, Inc. MPC8548ERM Rev.2, 02/2007
http://www.freescale.com
DRAM 576Mb: x9, x18, x36 2.5V VEXT, 1.8C VDD, HSTL, CIO,RLDRAM II Data Sheet
(Micron Technology, Inc. 576Mb_RLDRAM_II_CIO_D1.fm - Rev C 9/07 EN)
http://www.micron.com
EEPROM Atmel® 2-Wire Serial EEPROM 64K (8192 x 8) Preliminary Data Sheet
(Atmel Corporation, 5174C-SEEPR-6/07)
http://www.atmel.com
Ethernet
BCM5461S
BCM5482
10/100/1000BASE-T Gigabit Ethernet Transceiver Data Sheet
(Broadcom® Corporation, Document 5461S-DS17-R 5/12/08)
10/100/1000BASE-T Gigabit Ethernet Transceiver Data Sheet
(Broadcom® Corporation, Document 5482-DS04-R 10/18/07)
http://www.broadcom.com
Overview: Additional Information
10009109-01 ATCA-9305 User’s Manual 1-7
Flash 32 Mbit (x8/x16) Concurrent SuperFlash Data Sheet
(Silicon Storage Technology, Inc., S71270-01-000 9/05)
http://www.sst.com
mDOC H3 Embedded Flash Drive (EFD) featuring Embedded TrueFFS® Flash Management
Software Preliminary Data Sheet
(msystems 92-DS-1205-10 Rev. 0.2 June 2006)
http://www.m-systems.com/mobile
StrataFlash® Embedded Memory (P33) Data Sheet
(Intel®, Order Number: 314749-004 November 2007)
http://www.intel.com
4. Serial Configuration Devices (EPCS1, EPCA4, EPCS16, & EPCS64)
(Altera® Corporation CS1014-2.0 April 2007)
http://www.altera.com
IPMI IPMI — Intelligent Platform Management Interface Specification v2.0
(Intel Hewlett-Packard NEC Dell, Rev. 1.0, Feb. 12, 2004)
IPMI — Intelligent Platform Management Bus Communications Protocol Specification v1.0
(Intel Hewlett-Packard NEC Dell, Rev. 1.0, November 15, 1999)
IPMI — Platform Management FRU Storage Definition v1.0
(Intel Hewlett-Packard NEC Dell, Rev. 1.1, September 27, 1999)
http://www.intel.com/design/servers/ipmi/
Hardware Platform Management IPM Controller Firmware Upgrade Specification v1.0
(PICMG HPM.1 R1.0 May 4, 2007)
http://www.picmg.org
RTC
M41T00S
Serial Access Real-Time Clock Data Sheet
(STMicroelectronics December 2004)
Switch
BCM56802
BCM56800 Series 20-Port 10-Gigabit Ethernet Multilayer Switch Preliminary Data Sheet
(Broadcom® Corporation, Document 56800-DS03-R 12/28/07)
http://www.broadcom.com
1. Frequently, the most current information regarding addenda/errata for specific documents may be
found on the corresponding web site.
Device /
Interface: Document: 1 (continued)
ATCA-9305 User’s Manual 10009109-01
1-8
(blank page)
10009109-01 ATCA-9305 User’s Manual 2-1
Section 2
Setup
This chapter describes the physical layout of the boards, the setup process, and how to
check for proper operation once the boards have been installed. This chapter also includes
troubleshooting, service, and warranty information.
ELECTROSTATIC DISCHARGE
Before you begin the setup process, please remember that electrostatic discharge (ESD) can
easily damage the components on the ATCA-9305 hardware. Electronic devices, especially
those with programmable parts, are susceptible to ESD, which can result in operational fail-
ure. Unless you ground yourself properly, static charges can accumulate in your body and
cause ESD damage when you touch the board.
Caution: Use proper static protection and handle ATCA-9305 boards only when absolutely
necessary. Always wear a wriststrap to ground your body before touching a board. Keep
your body grounded while handling the board. Hold the board by its edges–do not touch
any components or circuits. When the board is not in an enclosure, store it in a static-
shielding bag.
To ground yourself, wear a grounding wriststrap. Simply placing the board on top of a static-
shielding bag does not provide any protection–place it on a grounded dissipative mat. Do
not place the board on metal or other conductive surfaces.
ATCA-9305 CIRCUIT BOARD
The ATCA-9305 circuit board is an ATCA blade assembly and complies with the PICMG 3.0
ATCA mechanical specification. It uses a 16-layer printed circuit board with the following
dimensions:
Table 2-1: Circuit Board Dimensions
The following figures show the front panel, component maps, and LED locations for the
ATCA-9305 circuit board.
Width: Depth: Height: Weight (typical):
12.687 in.
(322.25 mm)
11.024 in.
(280.01 mm)
< .84 in.
(<21.33 mm)
4.2 lb.
(1.91 kg)1
1. This is the typical weight for the ATCA-9305. Board weight varies slightly per configuration; contact
Technical Support if you require a specific configuration weight.
!
Setup: ATCA-9305 Circuit Board
ATCA-9305 User’s Manual 10009109-01
2-2
Figure 2-1: ATCA-9305 Front Panel
Note: The electromagnetic compatibility (EMC) tests used an ATCA-9305 model that includes a front panel assem-
bly from Emerson Network Power, Embedded Computing.
Caution: For applications where the ATCA-9305 is provided without a front panel, or where the front
panel has been removed, your system chassis/enclosure must provide the required
electromagnetic interference (EMI) shielding to maintain CE compliance.
ATCA-9035
O
O
S
Blue Hot Swap
2
3
MGT ETH
SWITCH
ETH
SPD
LINK
ACT
SPD
LINK
ACT
MGT CSL
RST
H/S
Reset
Red/Amber = Out of Service (OOS)
Green = In Service (2)
Amber = User Defined (3)
Off = 10 Mbps
Yellow = 100 Mbps
Green = 1000Mbps
Off = No Link
On= Link, No Activity
Blink = Link/Activity
Ethernet Speed (top LED)
Ethernet Link/Activity (bottom LED)
Port 1
Port 2
Management Console
!
Setup: ATCA-9305 Circuit Board
10009109-01 ATCA-9305 User’s Manual 2-3
Figure 2-2: Component Map, Top (Rev. 01)
+
+
+
+
C523
R153
C420
C518
C311
C717
C149
L30
C9
F5
U61
C314
C140
U22
C751
R172
C684
L41
C197
C549
C254
C220
R169
R91
U53
CR7
C54
R187
R146
C740
C508
C491
C544
C644
C592
R199
C2108
U38
C240
C538
C612
R45
C2145
R19
C406
C731
R40
R228
R58
C330
R279
F10
U15
CN58x0
Processor 2
C527
C336
C533
CR11
R57
R223
C1
C607
R102
C5
C176
C264
R136
C710
C466
C526
C200
R21
C561
C259
U7
C69
C67
CR6
L53
C552
C26
C506
CR34
C312
R178
R47
C675
C535
C766
R1034
C764
U19
MPC8548
Processor
C755
R183
C415
R75
Y1
C19
C32
C227
C692
R280
L20
R247
C516
R1
C775
C542
R166
C235
C78
C591
C512
C447
C2147
R6
C315
C96
CR40
R69
R197
C486
R1010
C20
R213
C748
R1039
C680
C713
CR38
RN2
R66
R210
R4
C173
C216
C454
C2106
C520
C693
C307
L67
C712
C395
R181
R161
C763
C58
C345
C485
R292
C519
C419
C588
C767
C219
R103
R118
C777
C732
R757
C727
C632
R236
R132
U43
L32
C459
C458
C726
L14
C218
C111
C550
C298
RN12
C403
C181
R202
U34
BCM5680x
Switch
C500
C536
Y9
C129
R216
U36
C162
R73
C114
C678
C596
C636
C504
C733
C103
C437
R24
CR42
C272
CR53
C559
C555
R111
C445
C595
U39
U33
C52
R49
C152
C75
R157
C325
C556
CR29
C147
C190
C530
R214
C366
C271
RN1
C281
C761
R56
C440
R237
L52
R272
C463
C709
L69
R100
R139
C66
C61
C10
U54
R201
R291
C451
C402
C279
C575
C482
C696
U46
R759
C273
P2
F4
R36
C85
C64
C164
R34
R18
R170
C203
R204
C192
C229
C628
C599
Y6
C753
R460
C139
C746
R16
C741
C799
C60
R254
C301
R83
C377
C45
C677
C418
F1
U32
C155
C416
C424
C72
U5
C722
C238
C2103
R192
C479
C131
C261
C148
J13
L28
C141
C353
F2
CR8
C226
CR52
C56
L43
C788
R44
C79
C332
C385
C540
CR25
C786
C53
R261
C743
R293
C467
C117
L66
C151
C207
C399
C364
C258
U58
C704
C503
C461
C214
U65
U3S
R143
C303
L55
C706
R171
R287
C309
C376
R189
RN10
R8
C365
C110
R35
R165
C615
R89
CR19
C464
C510
C581
CR9
C697
R159
C172
U35S
C391
L44
C369
RN3
C351
C509
R258
R285
C380
R137
C265
C600
C25
C389
C448
L35
C444
C630
SW1
C275
C179
R25
C779
C191
R243
L48
C409
CR12
R276
C30
CR18
C758
U62
R252
R1056
R215
C502
M2
C41
C300 C306
U30
C457
R256
C422
R177
R206
C333
C398
C431
R195
R217
C201
R274
L60
R121
R3
C683
C159
C361
C436
C665
C154
L23
C557
R149
C319
C250
CR21
C183
C560
R286
C168
C410
C230
R92
U2
C495
C2105
R185
C196
R144
C29
R142
L18
C231
L40
C288
R225
C642
CR24
R281
C285
C435
L11
C773
R82
C68
R101
R295
C100
CR3
U37
C707
C471
L25
CR41
F3
L26
U45
C782
C723
R196
R126
C493
C2148
C525
C368
R1060
R120
R107
C80
C425
C474
R235
C295
C158
R7
C289
U12
CR47
R152
R267
R135
U29
C604
C650
C65
R130
R289
C18
L6
C478
C357
C546
C589
R5
C317
R288
C473
C565
C348
C631
R80
R81
C76
L29
C206
C322
C682
C113
C517
C378
C785
U14
R278
R93
C640
R112
C84
R28
C470
C138
R203
C411
C670
C661
C396
L24
R230
J4
R1035
C74
R1057
R94
C6
C638
R52
F9
R253
R53
C742
C676
C578
C481
R227
C247
C354
R95
C105
C244
L39
C702
C532
C548
L49
C125
C268
R156
C515
Y5
R819
R283
C90
C137
R127
C185
R180
R26
C308
L54
C276
C123
C655
R114
C681
J6
R290
C780
C737
C36
L61
R334
CR43
R160
R50
C400
R41
C156
C284
C87
U21
L56
J1
L65
P4
C321
R23
C106
L4
R167
R238
R48
C762
C674
CR50
CR36
R61
L63
R29
R62
U47
C143
C293
C639
C553
C689
CR4
CR20
C157
R255
C584
CR45
C405
C624
C178
R138
R72
R164
C46
C522
C237
C708
C694
RN8
C529
R97
R104
C452
C101
C397
R39
C729
C133
C417
L3
C569
C421
C77
R42
C432
C660
CR33
C12
R218
C2120
U64
C608
C603
C8
C232
C428
C528
R233
C252
C798
L12
L1
L19
C598
R22
C212
R271
L2
R190
C616
CR23
CR32
R221
R88
C633
CR49
C296
C531
C62
C33
C2146
C11
R273
C449
C735
C771
R220
C619
C574
C388
C182
C38
C695
R123
CR31
C223
C718
C543
R260
R1032
R275
CR44
C667
C651
C2117
R27
Y8
C150
C623
R128
C499
C654
R193
C177
C93
CR15
C567
C687
C625
R74
R205
C781
R54
R163
C794
C277
U51
C577
C48
R282
C352
C287
L46
C350
RN11
P5
C404
R140
R222
R176
C267
C234
C282
R259
U23S
JP1
L59
C7
R264
R31
C511
C423
C379
R268
C747
L21
CR14
C104
R55
R194
C714
C57
C622
C174
R134
C160
C13
C699
U20
C22
R207
R85
C4
C725
C443
C666
C617
C262
C657
C765
C89
RN6
C784
C329
U48
Micro-
controller
F8
C613
C524
C302
U9
C690
C394
C769
C2112
R462
R78
C343
R154
C107
C283
C153
R37
L13
RN4
R245
C367
C292
CR37
C175
R232
C2116
C414
C202
C772
C2104
R63
R117
L37
R162
R242
C571
R251
C686
C716
U31
L64
C488
C59
C28
C34
R86
C73
C705
C210
U11
R150
R265
C2109
C462
C95
C446
C241
R1036
R59
C98
C297
C228
R32
R147
C796
C347
C576
U16
C668
C360
R240
C304
C331
C187
R241
R249
C513
U49
C738
C355
C120
CR46
R113
C790
C659
R43
L17
L5
C646
U28
C338
C195
U50
PHY
R105
CR48
C783
R294
Y4
C180
CR51
R70
L10
C340
C645
C356
C31
R1059
C427
C269
C442
CR16
L42
C455
P6
C438
C387
C490
C730
R13
R296
R174
C92
R173
R141
C611
C392
C86
U59
C579
C728
J12
C381
L15
L7
R239
C492
C384
C225
C204
C2107
R284
C169
C205
C165
CR2
C744
C494
C700
C648
R11
C124
C39
R106
C2118
L47
C122
C610
C263
C363
U52
U55
12V
Power Supply
C349
U44
C167
C703
C401
U57
C566
C246
C800
C393
C2149
R246
C521
C691
F7
C233
R17
C255
C545
C602
C118
C787
C290
U40
Y3
C136
C637
C2111
C17
R226
C426
C759
C487
C505
C251
R175
R168
L36
CR35
C199
C573
C475
R270
C551
C593
C408
C242
C664
R51
C16
C15
L62
C328
C647
R277
M1
R129
U17
C161
RN7
C342
R145
C483
C715
C99
C564
C14
C413
L50
C760
C270
C750
C570
J11
C514
C450
R65
R219
C334
C534
C736
C658
C719
C430
C541
C652
R262
C434
R158
C537
R79
C43
C477
R179
R10
C188
C774
R124
U24
KSL
CPLD
C253
C144
C501
C789
C274
C194
C563
C51
C371
C484
C583
C209
C112
C472
C257
C278
C323
C346
R211
C770
C539
R76
C439
R266
C649
C594
R765
C341
C299
R77
R212
R229
R30
C468
R1049
C320
R257
C752
R198
R20
C653
C119
C507
C222
R116
C627
C2
C609
C208
C142
R231
L45
R90
C184
C383
C590
C620
C109
R2
R155
C115
R1050
C373
C465
R71
C768
R15
R263
R125
C370
C49
RN9
C128
R87
C601
CR39
J3
C186
C3
R9
J15
R151
C453
L34
R14
C662
R133
C797
C412
L33
CR30
R200
C81
C94
R269
C778
C362
Y7
R108
L8
C327
R224
C745
U25
C40
C47
C626
C562
J14
C582
C547
C27
C456
R115
C116
CR27
C749
C280
L31
R248
C558
C294
CR22
C171
C671
C698
R332
C249
R131
C580
C132
L58
L51
C236
L38
R84
C318
RN5
C669
C441
C629
C145
C245
R109
C2119
C71
R67
CR10
C50
C193
C305
L9
C135
CR1
C310
C224
C433
C88
C793
C476
C460
R12
L27
R68
C374
F6
J9
C386
U41
SPI-XAUI
Bridge
R98
C429
R110
CR28
L68
L22
C791
C2110
U1
C606
J5
C55
C720 C721
C35
C248
C685
C326
C63
C673
R60
C344
C339
U26
C572
U4
R1041
R46
C163
R244
C217
R99
C243
L16
C42
C496
U27
C390
C734
C121
C792
C213
R119
C656
C102
C634
C211
C635
C256
C605
CR5
R208
C126
L57
R191
C382
R234
C239
C337
C97
C701
C2113
R33
C586
C286
C801
C130
C795
R761
C711
C597
C375
C260
U18
SO-CDIMM
U63
C756
C358
C568
C618
R188
U8
C37
C82
R184
C134
C316
C215
C335
CR13
C672
U6
C489
C469
C554
U60
C688
C663
Y2
C324
C776
R96
C198
R64
C480
C407
C757
C643
C359
R186
R148
C614
C166
CR17
C146
C221
C108
C21
C754
R38
C170
C83
C641
C372
C621
C313
C44
R182
R250
C24
C724
C291
CR26
P3
RJ45
P1
RJ45
P7
Mini-B
USB
U42
SPI-XAUI
Bridge
U13
SPI-XAUI
Bridge
U10
SPI-XAUI
Bridge
J33
24-pin ATCA
Connector
Polar Key
ATCA Guide
Polar Key
ATCA Guide
J31
80-pin
Zone 3
ATCA
Connector
J30
80-pin
Zone 3
ATCA
Connector
J23
80-pin
Zone 2
ATCA
Connector
P10
30-pin
Zone 13
ATCA
Connector
U56
CN58x0
Processor 1
Setup: ATCA-9305 Circuit Board
ATCA-9305 User’s Manual 10009109-01
2-4
Figure 2-3: Component Map, Bottom (Rev. 01)
C1882
C1004
C1877
C1442
C1506
C1330
R999
C1499
C1578
C1703
C1914
R831
C1818
R891
C1923
C1829
C941
C859
C1839
C1718
C1710
R597
R700
R534
L72
R406
C1133
R491
R799
R417
R862
C1465
R837
C1878
C933
C1514
R677
R968
C1676
R352
C1207
C1556
C968
C1991
C1935
R970
CR56
C1395
C1106
R575
C1066
C1902
C1849
C1857
R398
C1934
R349
C1364
L83
R896
R872
C1660
R355
C953
C1418
C817
C1381
C1539
C2153
C1592
C1977
R911
C1015
R725
C1726
R604
U82
R1003
C1011
R1031
C1137
C1480
C1359
C2065
C2027
C1762
R328
R343
R437
C958
R515
C2177
R736
C1738
R693
C1221
C1327
R828
R954
C1639
C1375
R533
C1383
C990
R892
C2124
C1155
C2182
C2064
C1755
C1980
R658
C892
C939
C1570
R974
C1505
C1179
L77
R558
C1652
C1017
C1026
R883
C1002
R822
C2068
C1995
C2150
C1897
R698
C1833
R569
C877
C1419
R329
R552
C1675
C1228
C1979
C1713
C1642
R603
C2016
C1319
R666
C1720
C985
RN13
C1705
C863
R762
C1910
R479
C1256
C1111
C1444
C962
C1999
C1739
C1450
J16
C1235
RN39
C1018
C1764
C1341
C2050
R915
C1146
R749
C1044
C1649
U74
R364
R994
C811
R380
C1317
R550
C1138
C1761
RN38
R441
R924
C998
R510
R752
C1671
C1305
C1982
R925
C1292
C1990
R453
C1286
C1260
RN14
C1681
C2013
R1008
R340
C1293
R574
L108
R412
C1299
R910
C935
C1128C982
R727
C1704
C1429
R630
C1717
R748
C1098
C1000
C833
R746
R416
C1475
C2126
C1664
C1773
R639
C1896
C2001
C1816
R429
C1907
R1045
R1053
C2136
C1975
C2039
C1159
C1525
C1272
R979
C1452
L94
R650
C1091
C1129
R817
C2081
C1614
C1225
U67
C1973
C2121
C1967
C2041
R758
R344
C814
C1890
C1549
R587
C869
C832
C1998
R367
C1760
RN34
C1562
C1079
R369
C1864
R784
C853
C821
C1267
C1722
C1244
C1997
R618
C1670
C1226
C1099
R411
C1842
C1880
C2158
R551
R743
R909
C2045
R415
R652
R508
C2032
C2096
C971
L96
R839
R942
R377
C1115
R882
C2038
R368
C2161
C1417
C1567
R913
C1171
R402
R876
C987
R465
C1782
C1687
C984
C979 C980
R362
C1887
C1770
C906
RN36
R774
R324
RN26
R928
R351
C1518
C1852 C2029
C1264
C2172
C1950
C1428
C1152
C1249
C1961
C947
C1544
R945
R624
C1196
C1844
C1326
R553
L99
R528
C1903
R425
C2031
C1392
R838
C2176
R865
C2191
C916
R767
C864
R714
R395
C1250
R710
C1060
R539
C1607
C1796
C2059
R827
R897
R405
R962
C1609
R981
C1552
C1733
R541
R921
C1097
R350
R730
C842
C1624
C1689
C1046
C1173
C908
C2189
R947
C1020
R554
R493
C1338
R886
C1841
R719
C1407
C876
C1806
R816
C1241
C1163
C1834
C1734
C2071
R506
L89
C1875
C1631
C1613
C1373
C831
C1768
C1645
C1136
R690
R662
R327
C1801
C1458
C1333
C966
C858
R1002
R360
R336
C2192
C1838
R365
C1156
L95
R653
C1711
C1074
C1183
C957
R396
C1672
C1906
C1441
C1583
C1120
R612
C1512
C1478
C2007
R919
R706
R917
C2175
C1965
C1039
U66
C2034
C1231
L76
C1884
C1218
C2051
R887
R733
C1928
R385
R946
C1212
C1731
C888
C1473
C1546
C1101
R582
C1650
C974
C1340
C1424
RN16
C2157
C1105
R431
R691
R637
C1901
R312
R963
R631
R1021
CR55
R716
C1309
C1233
C849
R707
R833
C1823
R1054
L97
C1746
L100
R966
C861
R646
R443
R986
C1189
C1958
C2094
C826
R995
R958
R957
C1379
R912
C1683
RN21
R1000
R1047
C844
R713
C1855
R450
C1970
R563
C981
R734
R530
R881
R763
C1013
C1909
C1513
R526
R613
C2123
R517
C2004
R542
C1802
C2099
R664
C2152
C1534
L75
C1357
R927
C956
C1243
C882
R608
C1536
R803
C1490
C2165
R920
C1690
R339
C1230
C1988
R857
C926
C1065
C1391
C2006
R401
C921
R972
C1931
C1167
R470
C1234
R520
R1051
C1470
C1667
C1142
L105
RN37
R988
C1048
R1009
R498
C1248
C963
C902
C846
C1498
R507
R728
R1037
C1220
L73
R347
R750
C2102
C1873
U77
PHY
C1810
C1725
C1378
C1107
R1015
C1957
R473
C1618
C1635
R656
C1483
C1597
C1135
C1194
R795
C1321
C1794
C1012
C1811
RN31
C840
C2188
C1851
C871
R430
C1742
C1028
R671
C2164
R775
C2040
C2037
C1367
C2000
C1611
R681
C1204
R1020
C1356
C1397
R463
C1242
R754
R801
R726
C1677
C2020
C2028
R848
C927
R456
C1693
C1288
C1987
R579
C881
R702
R499
C837
C1294
C994
C2132
R619
C937
R494
C1641
C1698
C1198
R902
R513
R1027
C1182
C1537
C1402
U81
R807
R871
C866
C855
R858
R898
C824
C1572
C1238
C1543
C1680
C919
C1712
C1398
C1033
C1166
R776
C1468
C1281
C1587
C1140
R467
C1003
C2183
R386
C1685
R830
R516
C815
R856
C2131
C1301
C1714
R930
R929
C1586
U72
C1616
C1320
C1064
R1014
C883
C2003
C1100
C872
R454
C965
C1113
R982
C891
L79
C1420
C928
C1521
C2078
C1691
C2184
RN22
C1948
R751
C2035
C813
C1634
C1924
C1056
R651
C1814
L88
C1659
C2008
R1052
C1832
R938
C1926
L92
R932
R665
R611
C1516
C802
C819
Q2
R842
C820
R832
C1431
R422
C1255
C1445
R320
C1047
C1376
R638
C1257
C1117
R1019
R849
C1859
R1026
RN25
C1318
C1289
C1846
C1062
C1331
C1602
C867
C2088
C1825
C2052
C2011
C1350
R800
C1371
C1937
C1803
R483
R1055
C1312
R404
C1055
C1077
C1905
C2086
C2067
C1195
R562
C1310
R647
R492
R576
C1296
R621
R1004
R724
C1637
C1223
R583
R383
C1188
C901
C1308
R366
R772
C1454
C1992
C1576
C1507
C2181
C2015
R893
C1736
Q1
C1051
C1831
C1034
R789
R469
C1172
R591
C1271
C1384
C1640
C2133
R704
C893
U78
R794
R419
C1658
C810
C936
C1557
C1943
C1848
R1006
C1519
R696
C1275
C1606
C2047
R676
C1346
R371
C1547 C1541
C1304
C1515
C1679
C2005
C1788
C1917
C1174
R547
C1081
C2180
C1130
R847
C1654
C1566
L85
C1430
C943
L106
C946
C2014
C2082
C1052
R524
C2156
R805
C1214
C1657
Q4
R809
C1466
R703
R477
R697
C1464
C1110
R310
C807
C898
C1835
C1895
C1363
C1854
C1735
R685
R674
C1827
R694
C1716
R936
R863
R600
R628
C887 C1147
C1236
R976
C1190
R829
C1463
C1582
C1187
C830
C1287
R602
C1239
C822
C1528
C905
C868
C2044
C2080
C2056
R840
C2017
C1335
R590
R926
C1745
C1024
R804
SW2
C1237
C1962
R888
C1279
R931
R712
R447
C1176
C2021C1956
C969
C852
C1774
C1568
C1414
C1951
C1960
C1192
R303
C1707
C1413
C1881
C952
R427
R824
R899
C1322
R854
R363
R485
C1353
C1409
C2074
C1860
C1254
R705
C1396
C1121
R1058
R381
R1001
C1185
C1994
C1472
C1558
C1112
C1899
C1102
R641
C2174
C1252
C2151 C2155
C851
C1694
C2168
R548
C2018
C1347
C2193
R708
R490
C1314
C1601
C1485
R561
C1328
C2127
C1776
R348
R474
R960
C1933
R810
C1337
CR54
R438
C1648
R392
R1007
C924
R625
R879
C1122
C1203
C1573
C955
C1813
R578
C1840
C1503
C1486
C1551
C1104
R480
C1045
C975
RN29
C1719
R907
C841
C2054
R835
C1766
R667
C1339
C1199
C1290
C2134
R806
R826
C1405
C1554
C1619
R869
C1469
C2160
C1276
C1850
R549
C1010
C839
C1879
C2122
R984
R584
R895
C884
R596
C925
C1282
C970
R546
R796
R884
C1006
C1270
C1565
R678
R877
C1177
C1661
R922
R434
R391
R672
C850
C1588
C1268
C1197
RN28
R717
C954
C1520
C1394
R764
R961
C1972
C2091
C1569
R975
C2128
C1481
R645
R535
C1035
R820
C2079
C1263
C1563
C1824
C1978
C899
R709
R971
C1747
C2089
C950
C1217
R588
R481
C1866
C1767
R299
C1819
R777
RN24
C1453
C1612
C2085
C1432
R457
R466
R991
R346
C918
L80
C816
C911
C1273
C856
L84
R544
C1471
R874
R949
C1737
R798
C1125
C1342
C1298
R846
R556
C917
R684
R305
C2098
C1090
C1870
C1061
C2023
R657
C1311
C2190
R321
C1284
C1080
C967
R711
C1868
C1193
R825
C2073
C1861
C1916
R311
C1219
C1451
C1555
C2154
C2171
C1131
C2125
R593
C2075
R326
R523
R1043
R459
C1261
C1158
R540
L70
C1123
C1334
C1888
R755
C2093
C1674
C2022
C1180
C1561
C1070
C1786
C1448
C1433
R509
C1799
C961
C1032
R384
R880
C1354
R478
L107
R426
C1608
R595
C1345
C1867
C1678
R738
C1446
R335
C1042
C2077
R679
C1759
C1579
C1291
R908
C1913
C1911
C1699
RN17
C1303
L81
R1042
R615
R394
C1157
R864
C1830
R501
R452
R916
C1727
C1511
R572
R318
R495
C2063
R1030
C2042
R1011
C1845
C929
C1030
R620
R841
C1487
C1016
R522
R472
R309
C2055
R525
R940
R502
R851
R867
R890
C1932
Q5
R723
R622
C1765
C2024
R555
C1374
R689
R670
RN27
R649
C894
C2159
R333
C1666
R814
C1036
R786
C835
R388
R918
C1772
C1222
C1779
R471
R464
C978
C1753
C1625
C1181
C1538
C1361
C1966
RN18
C1898
C1927
R323
C1610
C1741
R505
R319
C1621
R387
R537
R769
R636
C1771
C1360
C2057
RN35
C1141
R413
R873
R787
C2097
C1940
R914
C2179
C951
R682
C1900
C2076
R680
R433
C1724
C1088
C1508
R792
C1748
C2169
C923
C1790
R663
C1349
C1093
C1126
C1527
R661
C1372
C1439
C838
C2010
R315
C1580
R660
R753
R409
C1548
C1492
C1143
R487
R756
C1622
C944
C915
C1560
C1939
R731
C1412
C1119
C907
R812
R985
C2166
R436
C1729
R511
R378
R445
C989
C1686
C1945
R570
R967
R567
R389
C1509
R424
C1300
L71
R423
R735
R565
C1863
R688
R770
C1103
C1936
C1069
C1262
C1209
C1368
C1826
RN20
R451
C1584
R923
C1386
R379
R486
C1701
C1791
C1883
C1743
C2163
C1575
C1351
R955
C1323
C1352
C1504
R322
R444
C1662
C1871
C1477
R418
C812
C1986
C1721
C1564
C1605
C2009
C2062
C1401
C1211
C1952
R791
C1891
C1949
R1029
C2092
C903
C1522
R594
C1784
C976
C1800
R860
R996
C1438
R797
C1632
C1078
R993
C1118
R845
C1644
C1307
C1072
R633
R545
R301
C1474
R514
C845
C1491
R739
C1489
C1377
C878
C1533
C992
R737
R400
C1938
R304
C1154
L101
C1603
C1114
C1416
C1355
R821
C1971
C1201
C1400
C1455
C1348
R793
R773
C1449
C1266
C1964
C1684
R1040
R421
C1577
C1479
C1643
C1053
C1380
C1728
C993
C1399
C1175
R721
R815
R950
R519
C2087
R458
R308
C1083
C1259
R488
C1408
C1789
C1435
C2084
R390
C806
C1058
C948
C972
R592
C1812
CR57
C1315
C949
C1014
C1946
R823
C1889
C1751
C1655
R564
C2002
C1912
C1820
C885
C1777
R640
C1094
C1370
R790
C983
R626
C1636
R885
R440
C1482
C1265
R905
C862
R668
C1571
C1007
R669
C1647
C1856
R952
U70
C914
C836
C1031
R644
C1595
R586
R937
C1029
C1095
R1046
C2066
R1016
R399
C1501
C1955
R1048
C2129
C1628
C1688
R589
C1332
R935
C2048
C1922
C1591
C1792
R1044
C1682
R683
R500
R866
Q3
R742
C1313
R435
R875
C2162
R527
R720
R358
C1996
C2072
C1805
C1574
C995
C818
C1216
C1369
R965
R316
R397
R904
R780
C1620
R476
L104
C847
R992
C1633
C1008
C940
C1947
R978
C1665
C1316
C1968
R370
C1757
C2033
C1411
R449
R357
C1109
R375
C897
C2025
R782
C1706
C2069
R374
C1170
C1976
C1918
R853
C1985
R939
R781
R442
C1617
C1023
C1434
R811
R314
R997
R577
C825
L87
C1422
C1941
C1387
R834
C2100
C1019
R948
C1953
R361
R432
C1134
R642
R900
C1744
C1001
C2186
R581
C1150
R969
C1837
C1437
C1754
C1041
R1017
R1022
R306
R695
C1797
C1876
C1224
R580
C1623
R779
C904
C1240
R998
R342
R585
C1793
C1865
R557
R870
L91
C1082
C1295
R1005
C1186
C1885
R722
R338
C1651
C1497
C1599
C1164
R428
R330
L93
R740
C1959
R521
R353
C1071
C1529
R325
C1210
C1510
R635
L102
C1178
R1012
C932
R956
C1165
C930
C1858
C1390
C1280
C912
C1277
R648
R675
R783
C960
R337
C1215
U71
PHY
R808
R1028
C809
R414
R503
C1732
L103
R489
C2043
R482
C1700
C1843
C1590
C1874
C1532
R627
C1410
C1027
C913
C2019
C1153
C1638
R843
R878
C1594
L82
R609
R420
C1343
C1756
C1904
C2173
R571
C1050
R623
R941
R300
C1993
C910
R497
R297
R560
C1798
U75
NAND
Flash
C1500
C1853
C1283
R302
C1067
C1297
C1783
C1306
C1205
C1139
C2058
R410
C1709
C1253
C1054
C1366
C808
C1021
C1989
R659
R687
C988
C805
C1440
R446
C857
C1022
R531
C1530
C895
C1362
C1278
R813
C1769
C1496
C1184
C1073
C1822
C1488
C1092
C973
C1869
C2030
R983
C1494
C1456
C1646
C1038
C1708
C1656
C1037
C2090
C1476
C2036
C1421
C1160
R747
C1229
C1559
R768
R345
R889
C1404
C1085
C1981
C945
RN30
R559
R951
C1447
C1808
C1124
C920
U73
C1930
R943
C1663
C1162
R372
R568
C1059
R844
C2061
C1925
C880
L78
R468
C1785
C1459
C1484
C1329
R903
R836
C1531
C1443
C1775
C2185
R686
R802
L74
C896
R632
C1495
R122
R298
L90
C2170
R861
C1213
R692
R616
R964
C2095
C1523
C2083
R760
C1043
C1535
C1269
R617
C1344
C1715
C1406
C1626
C1669
C1692
R607
C2012
C1817
R354
C1593
R598
C854
C1749
C1892
C1954
C2101
R407
C1427
R317
C1145
C1089
C1202
C1542
C1168
C1365
C1778
R718
C1025
C1750
C1393
R701
R788
C900
C1075
C1227
RN33
R655
C977
C1127
C1467
C1894
C1740
RN23
R331
R643
C1600
C1668
C931
R601
C1063
R536
C890
C1389
C2053
R439
C1921
C2178
R341
R356
R538
C1872
L98
C1086
R818
R980
C873
R376
C1005
C1169
C1232
C1191
R771
C1581
C865
C959
C843
C2130
C1915
R484
C827
R610
C1161
C1781
C1436
C1462
U76
StrataFlash
C1132
C1423
U69
R944
C1920
R518
C1795
R573
C1596
R989
R403
C1942
C1461
R868
C1206
R566
R599
C1553
C1695
U68
PHY
R741
C1862
C1598
C2070
R732
R606
C1919
C1804
R953
C1149
C1415
R901
R729
C1144
C1049
C2135
C1076
C1929
C1246
C1087
U79
C1325
R654
C1893
C1403
C997
C1274
R1018
C1040
C879
C1752
C1148
RN19
C1821
C834
C996
RN15
R455
C938
R852
R894
C1108
C1285
C1604
R977
C1815
C1807
C1245
C804
C1493
C874
C1983
R778
C803
R504
R461
C1702
C886
C1984
R745
R634
R906
C999
R859
C909
R393
C1096
C829
C1385
C1151
C1550
C1526
C860
C1358
R629
C1324
C1787
C1208
U80
R699
C1653
C1758
C875
R382
C1836
C1886
R475
C1723
C1969
R529
C1809
C1847
R785
R959
C2049
C1057
C1627
R1033
R673
R934
C1068
R408
C1425
C1302
C991
R313
C2187
R990
C1258
C1251
R987
C2026
C1517
R973
C848
C1457
R855
C1629
C1697
R359
R543
C1615
R512
C922
R614
C870
C1974
R373
R448
C1763
C1426
C1382
C823
C1696
C1673
C1545
R850
R715
C1388
C889
C986
C1963
C1944
R933
R1013
C1336
C1585
C934
C2167
C964
C1630
C1540
C1589
L86
C942
C1084
C1828
R496
C2046
R744
C1908
C1200
R532
R766
C828
C1116
RN32
C2060
R605
C1502
R1038
C1460
R307
C1247
C1780
C1730
C1524
C1009
Setup: ATCA-9305 Circuit Board
10009109-01 ATCA-9305 User’s Manual 2-5
Figure 2-4: LED, Fuse and Switch Locations, Top
CR1 - P2_LED_GPIO12-R
CR2 - P2_LED_GPIO13-R
CR3 - P2_LED_GPIO14-R
CR4 - P2_LED_GPIO15-R
CR23 - MIP1_LED1_R
CR24 - MIP1_LED2_R
CR25 - MIP1_LED3_R
CR26 - MIP1_LED4_R
CR50 - P1_LED_GPIO12_R1
CR51 - P1_LED_GPIO13_R1
CR52 - P1_LED_GPIO14_R1
CR53 - P1_LED_GPIO15_R1
IPMP State
CR35 - STATE_LED8
CR36 - STATE_LED7
CR37 - STATE_LED6
CR38 - STATE_LED5
CR39 - STATE_LED4
CR40 - STATE_LED3
CR41 - STATE_LED2
CR42 - STATE_LED1
CR43 - STATE_LED0
SW1 - IPMC Reset
F3 - .75 Amp Fuse
(self resetting)
F10 - .75 Amp Fuse
(self resetting)
F2 - .75 Amp Fuse
(self resetting)
F1 - .75 Amp Fuse
(self resetting)
F4 - 1 Amp Fuse
F5 - 1 Amp Fuse
F6 - 10 Amp Fuse
F7 - 8 Amp Fuse
F8 - 10 Amp Fuse
F9 - 8 Amp Fuse
Ethernet
CR15 - TSEC2_ACTIVITY
Ethernet
CR44 - BC1_LINKSPD1/2
CR45 - BC1_LINKSPD1/2
CR46 - BC1_ACT*
CR47 - BC2_LINKSPD1/2
CR48 - BC2_LINKSPD1/2
CR49 - BC2_ACT*
MPC8548
CR13 - PQ_GREENLED_R*
CR14 - PQ_CKSTP_OUT_R*
CR16 - PQ_REDLED_R*
Debug
CR18 - DEBUG_LED1_R*
CR19 - DEBUG_LED2_R*
CR21 - DEBUG_LED3_R*
CR22 - DEBUG_LED43_R*
Boot Device
CR31 - FL0_LED_R*
CR32 - FL1_LED_R*
CR33 - SKT_LED_R*
+
+
+
+
CR49
CR26
JP1
CR19
CR3
CR25
CR50
F4
CR51
F9
CR1
CR18
CR4
CR46
F6
F8
CR15
CR21
CR2
SW1
CR14
CR32
CR45
CR31
CR33
CR23
CR16
F5
CR22
CR52
CR48
CR24
CR47
J9
CR13
CR35
CR38
CR40
CR36
CR39
CR43
CR37
CR42
CR41
CR53
CR44
F7
J1
P2
J15
F10
F1
F2
F3
Setup: ATCA-9305 Circuit Board
ATCA-9305 User’s Manual 10009109-01
2-6
Figure 2-5: LED and Switch Locations, Bottom
J16
Front Panel
CR54 - Red = LED1R_CONN
Amber = LED1A_CONN
CR55 - LED2_CONN
CR56 - LED3_CONN
SW2 - Front Panel Reset
Hot Swap
CR57 - BLUE_LED_CONN_K
CR56 CR57
CR54
SW2
CR55
Setup: ATCA-9305 Circuit Board
10009109-01 ATCA-9305 User’s Manual 2-7
Connectors
The ATCA-9305 circuit board has various connectors and headers (see the figures beginning
on page 2-3), summarized as follows:
J1: This 14-pin JTAG header is used for debugging CN5860 processor 2. See Table 3-7.
J3-J6: These 240-pin sockets are installed for the CN5860 processor 1 DDR2 SDRAM memory.
J9: This 14-pin configuration header allows selection of boot device, and MPC8548 configura-
tion for the configuration SROM. See Fig. 2-6.
J11-J14: These 240-pin sockets are installed for the CN5860 processor 2 DDR2 SDRAM memory.
J15: This 14-pin JTAG header is used for debugging CN5860 processor 1. See Table 3-7.
J23: The 80-pin Zone 2 connector provides 1 GB and 10 GB Ethernet access to the backplane, see
Table 8-2.
J30-J31: The 80-pin Zone 3 connectors route PCIe and XAUI (10G) to the optional RTM. See Table 8-3
and Table 8-4 for pin assignments.
J33: The 24-pin Zone 3 connector routes the reset, Hot Swap, MPC8548 console, power, and
IPMC I2C to the optional RTM, see Table 8-5.
JP1: This is the 10-pin programming header for the IPMP, CPLD, and SPI 10G (1-4) devices, see
Table 7-51.
P1: This 14-pin RJ45 connector with LEDs routes the Three-speed Ethernet Controller (TSEC1)
between the MPC8548 and the front panel. See Table 6-4 for pin assignments.
P2: This 16-pin JTAG debug header accesses the MPC8548 processor, see Table 4-7.
P3: This 14-pin RJ45 connector with LEDs routes Ethernet (FP1) between the switch and the
front panel, see Table 6-4 for pin assignments.
P4: The 5-pin vertical mini-B USB provides the IPMP EIA-232 console debug, see Table 7-52.
P5, P6: These 5-pin vertical mini-B USBs are the CN5860 console and for factory debug use only.
P7: This 5-pin mini-B USB is the console serial port for the MPC8548 management processor,
see Table 4-8.
P10: The 30-pin Zone 1 connector routes IPMB to the backplane, see Table 8-1.
Setup: ATCA-9305 Setup
ATCA-9305 User’s Manual 10009109-01
2-8
Configuration Header
There are a total of seven jumper pairs on J9 (pins 11-14 are spare posts). See figure Fig. 2-2
for the jumper location on the ATCA-9305. Also reference the “Jumper Settings (0x18)” reg-
ister.
Figure 2-6: Configuration Header, J9
BT SKT: A shunt on pins 1-2 selects the 512 KB socketed ROM as the boot device for the MPC8548.
IG SROM: If the serial ROM configuration jumper is installed (pins 3-4), the ATCA-9305 will not try to
configure (IGNORE_SROM*) from the MPC8548 serial ROM.
REDIR EN: A shunt installed on pins 5-6 disables the boot redirection, see page 7-41 for more informa-
tion.
BOOT: A shunt on pins 7-8 causes both Cavium CN5860s to boot from their local bus and not boot
over PCI.
STAND: A shunt on pins 9-10, IPMC stand alone mode, allows the board to boot without manage-
ment control.
PROG: Installing a shunt on pins 11-12 puts the IPMC controller into programming mode. This is
only used in the factory to configure the IPMC.
BT FLASH: If BOOT shunt is installed (booting from local bus), this shunt determines whether the boot
is from local flash or socket. When this BT FLASH shunt is installed, the ATCA-9305 boots
from flash. Otherwise, it boots from the socket.
ATCA-9305 SETUP
You need the following items to set up and check the operation of the Emerson ATCA-9305:
ATCA chassis and power supply
MPC8548 Console cable for EIA-232 port, Emerson part # C0007662-00
Computer terminal
Save the antistatic bag and box for future shipping or storage.
13 11 9 7 5 3 1
14 12 10 8 6 4 2
BT SKT
IG ROM
REDIR EN
BOOT
STAND
PROG
BT FLASH
Setup: ATCA-9305 Setup
10009109-01 ATCA-9305 User’s Manual 2-9
Power Requirements
The ATCA-9305 circuit board uses —48 volts from the backplane to derive 3.3 volts for the
IPMC and 12 volts for payload power.
Table 2-2: Typical Power Requirements
The exact power requirements for the ATCA-9305 circuit board depend upon the specific
configuration of the board, including the CPU frequency and amount of memory installed
on the board. Please contact Emerson Technical Support at 1-800-327-1251 if you have
specific questions regarding the board’s power requirements.
Environmental Considerations
As with any printed circuit board, be sure that air flow to the board is adequate. Chassis con-
straints and other factors greatly affect the air flow rate. The environmental requirements
are as follows:
Table 2-3: Environmental Requirements
Configuration: Power:
1.0 GHz MPC8548 and 800 MHz Cavium processors,
board running at room temperature with all
processors at U-Boot prompt
135 watts
Environment: Range: Relative Humidity:
Operating Temperature 0° to +55° Centigrade, ambient
(at board)
Not to exceed 85% (non-
condensing)
Storage Temperature —40° to 85° Centigrade Not to exceed 95%
(non-condensing)
Altitude 0 to 4,000 meters above sea
level
—
Air Flow Requires 30 CFM at 55° Centigrade at sea level. Meets thermal
performance requirements of CP-TA ATCA ICD Book 1.1Class B-2
Setup: ATCA-9305 Setup
ATCA-9305 User’s Manual 10009109-01
2-10
Figure 2-7: Air Flow Graph
Hot Swap
The ATCA-9305 can be Hot Swapped, as defined in the AdvancedTCA specification (see ref-
erence in Table 1-2). This section describes how to insert and extract an ATCA-9305 module
in a typical AdvancedTCA system. (These procedures assume the system is using a shelf
manager.)
Note: The ATCA-9305 Rear Transistion Module (RTM) has its own Hot Swap LED and switch, and it can be Hot
Swapped in/out independently of the front board. If the front board is not present, then the RTM will not be
powered. If the front board is Hot Swapped out, the RTM’s blue LED will illuminate. In either case, the RTM can
be safely removed.
Setup: Troubleshooting
10009109-01 ATCA-9305 User’s Manual 2-11
Insert a board:
1Insert the ATCA-9305 into an available slot.
2Push in the front panel handle (tab).
The blue Hot Swap LED on the front panel (see Fig. 2-1) flashes a long blink to indicate that
board insertion is in progress and system management software is activating the slot. Then
the blue LED turns off, indicating the insertion process is complete, and payload power is
present.
Remove a board:
1Pull out the handle (tab) on the ATCA-9305 front panel one click.
A short blink indicates the board is requesting permission for extraction.
2Remove the board when the blue LED on the front panel is on (no payload power).
Caution: Do not remove the ATCA-9305 while the blue LED is blinking.
TROUBLESHOOTING
In case of difficulty, use the following checklist:
Be sure the ATCA-9305 circuit board is seated firmly in the carrier.
Be sure the system is not overheating.
Check the cables and connectors to be certain they are secure.
Check that your terminal is connected to a console port.
Technical Support
If you need help resolving a problem with your ATCA-9305, visit
http://www.emersonembeddedcomputing.com/ on the internet or send E-mail to sup-
port@artesyncp.com. Please have the following information handy:
• ATCA-9305 serial number and product identification (see Fig. 2-8)
• MPC8548 monitor version number (see Fig. 9-1)
• Cavium monitor version number (see Fig. 3-3)
• version and part number of the operating system (if applicable)
!
Setup: Troubleshooting
ATCA-9305 User’s Manual 10009109-01
2-12
• whether your board has been customized for options such as a higher processor speed or
additional memory
• license agreements (if applicable)
If you do not have internet access, please call Emerson for further assistance:
(800) 327-1251 or (608) 826-8006 (US)
44-131-475-7070 (UK)
Figure 2-8: Serial Number and Product ID on Top Side
Product Repair
If you plan to return the board to Emerson Network Power for service, visit
http://www.emersonembeddedcomputing.com/ on the internet or send E-mail to servi-
ceinfo@artesyncp.com to obtain a Return Merchandise Authorization (RMA) number. We
will ask you to list which items you are returning and the board serial number, plus your pur-
chase order number and billing information if your ATCA-9305 hardware is out of warranty.
Contact our Test and Repair Services Department for any warranty questions. If you return
the board, be sure to enclose it in an antistatic bag, such as the one in which it was originally
shipped. Send it prepaid to:
Emerson Network Power, Embedded Computing
Test and Repair Services Department
8310 Excelsior Drive
Madison, WI 53717
RMA #____________
Product ID
Serial Number
Setup: Troubleshooting
10009109-01 ATCA-9305 User’s Manual 2-13
Please put the RMA number on the outside of the package so we can handle your problem
efficiently. Our service department cannot accept material received without an RMA num-
ber.
Comments and Suggestions
We welcome and appreciate your comments on our documentation. We want to know
what you think about our manuals and how we can make them better.
Mail comments to us by filling out the following online form:
http://www.emersonnetworkpowerembeddedcomputing.com/ Contact Us > Online Form
In “Area of Interest” select “Technical Documentation”. Be sure to include the title, part
number, and revision of the manual and tell us how you used it.
ATCA-9305 User’s Manual 10009109-01
2-14
(blank page)
10009109-01 ATCA-9305 User’s Manual 3-1
Section 3
Cavium Processor Complex
The ATCA-9305 provides two Cavium processor complexes. The major devices on each
complex consist of the Cavium CN5860 processor, two StratixGX bridges, SDRAM,
RLDRAM®, an I2C EEPROM, socketed ROM, Flash, and the PCI bus interface.
Figure 3-1: Cavium Processor Complex Block Diagram
CAVIUM CN5860 PROCESSOR
The main features of the CN5860 include:
Table 3-1: CN5860 Features
Feature: Description:
Processor Core Up to 16 cnMIPS™ cores
Core Speed
Network Services Processor (NSP)
up to 800 MHz, processing up to 30 million packets per second
System Packet Interface Two SPI-4.2 ports
L2 Cache 2 MB, eight-way set associative
DRAM 144-bit DDR2 DRAM interface
RLDRAM 18-bit RLDRAM, low-latency memory direct access
PCI 64-bit, PCI 2.3 compatible
Cavium Processor Complex: PCI
ATCA-9305 User’s Manual 10009109-01
3-2
The CN5860 and switch route packets using SPI-4.2 and control information flow using PCI.
The CN5860 has two SPI-4.2 interfaces with each one supporting up to 16 ports. Two high-
speed SPI-4.2 Altera (Stratix™ GX) FPGAs function as the SPI-to-XAUI bridge for each pro-
cessor to switch complex. The PCI interface supports up to four ports, consequently a total
of 36 ports can be supported internally by each CN5860.
Cavium Memory Map
Although the Cavium processors are 64-bit, the ATCA-9305 uses a 49-bit implementation.
Refer to the Cavium Networks OCTEON Plus CN58xx Hardware Reference Manual for more
detailed information on the memory map.
Table 3-2: Cavium Address Summary
PCI
The Cavium is a slave device on the PCI bus. The Cavium U-boot monitor image is provided
by the MPC8548 management processor via PCI. The MPC8548 monitors the Cavium boot
status and has the ability to try alternate boot images if the current one fails.
Hex Physical
Address: Register Description:
1,2000,0000,0000 reserved
1,1F00,0000,0000 Cavium Hardware registers
1,1E00,0000,0000 PCI Memory Space (6)
1,1D00,0000,0000 PCI Memory Space (5)
1,1C00,0000,0000 PCI Memory Space (4)
1,1B00,0000,0000 PCI Memory Space (3)
1,1A00,0000,0000 PCI I/O Space
1,1910,0000,0000 reserved
1,1900,0000,0000 PCI Special Space
1,0700,0000,0000 CN58xx Registers
1,0001,0000,0000 reserved
1,0000,0000,0000 Local Boot Bus
0,0004,1000,0000 DDR2 SDRAM, middle block (256-512 MB)
0,0004,0000,0000 reserved
0,0000,2000,0000 DDR2 SDRAM, upper block (512 MB-2 GB)1
1. This depends on how much memory is installed.
0,0000,1000,0000 reserved
0,0000,0000,0000 DDR2 SDRAM, bottom block (256 MB)
Cavium Processor Complex: PCI
10009109-01 ATCA-9305 User’s Manual 3-3
The CN5860 processor is designed such that another PCI device can initialize its memory
interface, copy code over PCI into its local memory space, and then write a boot release reg-
ister.
CN5860 Boot Over PCI
The PCI bus is configured to run at 66 MHz in 64-bit conventional PCI mode. On power-up,
the CN5860 processor’s 16 internal cores are held in reset. The MPC8548 management pro-
cessor performs the following steps:
1Initialize the CN5860 RAM.
2Copy the CN5860 U-boot to the CN5860 RAM.
3Copy boot code to the reset vector to jump to the U-boot code in RAM.
4Release the CN5860 processor cores from reset.
5Receive return codes from the CN5860 that indicate any boot or POST errors and take the
appropriate action.
The management processor (MPC8548) monitor implements a utility to load non-volatile
memory redundant U-boot images for the CN5860 processors. The utility tags each copy as
primary or secondary.
Cavium Processor Complex: PCI
ATCA-9305 User’s Manual 10009109-01
3-4
Cavium Reset
Each CN5860 can be reset independently of the other processor without affecting its opera-
tion. This task is performed by the MPC8548 management processor.
Figure 3-2: CN5860 Reset Diagram
Voltage
Monitor
Delay
IPMC
Stratix II GX
XAUI #2
P1 DDR
SDRAM
Stratix II GX
XAUI #1
Stratix II GX
XAUI #4
Stratix II GX
XAUI #3
KSL
CPLD
P1_RESET*
CN5860
Cavium
Processor 1
P1_PCI_RST*
P1_PWRGD
P1_DDR_RST*
MIP1_RST*
MIP2_RST*
MIP3_RST*
MIP4_RST*
CN5860
Cavium
Processor 2
P2_RESET*
P2_PCI_RST*
P2_PWRGD
P2 DDR
SDRAM
P2_DDR_RST*
IPMP
CPLD
PWRGD_OK
L_PAYLD_EN
3_3V_PWRGD
2_5V_PWRGD
1_8V_PWRGD
1_2V_PWRGD
1_0V_PWRGD
PQ_CORE_PWRGD
P1_CORE_PWRGD
P2_CORE_PWRGD
POR_RST*
48A_OK
48B_OK
E_HANDLE
I2C IO
Port
L_PAYLOAD_RST*
PRIV_I2C_SCL
PRIV_I2C_SDA
IPMC_PO_RST*
3_3V_MP
MC Reset
3_3V_MP
Hot Swap
Switch
3_3V_MP
3_3V_MP
Front
Panel
Reset
3_3V
Voltage
Monitor
Delay
33MHz
IPMC_PO_RST*
Cavium Processor Complex: Cavium Ethernet
10009109-01 ATCA-9305 User’s Manual 3-5
CAVIUM ETHERNET
The Ethernet address for your board is a unique identifier on a network. The address con-
sists of 48 bits (MAC [47:0]) divided into two equal parts. The upper 24 bits define a unique
identifier that has been assigned to Emerson Network Power, Embedded Computing by
IEEE. The lower 24 bits are defined by Emerson for identification of each of our products.
The Ethernet address for the ATCA-9305 is a binary number referenced as 12 hexadecimal
digits separated into pairs, with each pair representing eight bits. The address assigned to
the ATCA-9305 has the following form:
00 80 F9 xx yy zz
00 80 F9 is Emerson’s identifier. The last three bytes of the Ethernet address consist of the
port (one byte); 0x99(SPI 1), 0x9A (SPI 2), 0x9B (SPI 3), or 0x9C (SPI 4), followed by the serial
number (two byte hexadecimal). The ATCA-9305 Cavium has been assigned the Ethernet
address range 00:80:F9:99:00:00 to 00:80:F9:9C:FF:FF. The format is shown in Table 3-3.
Table 3-3: Ethernet Port Address
The last two bytes, MAC[15:0], are calculated from the serial number stored in the Cavium
EEPROM. This corresponds to the following formula: n —1000, where n is the unique serial
number assigned to each board. So if an ATCA-9305 serial number is 1032, the calculated
value is 32 (2016), and the default Ethernet port addresses are:
• Cavium 1 SPI 1 MAC address is: 0x00 0x80 0xF9 0x99 0x00 0x20
• Cavium 1 SPI 2 MAC address is: 0x00 0x80 0xF9 0x9A 0x00 0x20
• Cavium 2 SPI 1 MAC address is: 0x00 0x80 0xF9 0x9B 0x00 0x20
• Cavium 2 SPI 2 MAC address is: 0x00 0x80 0xF9 0x9C 0x00 0x20
Offset: MAC: Description: Ethernet Identifier (hex):
Byte 5 15:0 LSB of (serial number in hex) —
Byte 4 MSB of (serial number in hex) —
Byte 3 23:16 SPI 1
SPI 2
SPI 3
SPI 4
0x99
0x9A
0x9B
0x9C
Byte 2 47:24 Assigned to Emerson by IEEE 0xF9
Byte 1 0x80
Byte 0 0x00
Cavium Processor Complex: Cavium Monitor
ATCA-9305 User’s Manual 10009109-01
3-6
CAVIUM MONITOR
The primary function of the monitor software is to transfer control of the hardware to the
user’s application. Secondary responsibilities include:
• low-level initialization of the hardware
•diagnostic tests
• low-level monitor commands/functions to aid in debug
Start-up Display
At power-up or after a reset, the Cavium monitor runs diagnostics and reports the results in
the start-up display, see an example in Fig. 3-3. During the power-up sequence, the monitor
configures the board according to the environment variables (see “MPC8548 Environment
Variables” on page 9-26). If the configuration indicates that autoboot is enabled, the moni-
tor attempts to load the application from the specified device. If the monitor is not config-
ured for autoboot or a failure occurs during power-up, the monitor enters normal
command-line mode. The monitor command prompt in Fig. 3-3 is the result of a successful
hardware boot of the ATCA-9305.
Figure 3-3: Example Cavium CN5860 Monitor Start-up Display
Note: There will be either a 1 or 2 in front of the monitor prompt indicating which Cavium processor is prompting.
Power-up/Reset Sequence
The Cavium CN5860 processor follows the boot sequence in Fig. 3-4 before auto-booting
the operating system or application software. At power-up or board reset, the monitor per-
forms hardware initialization, diagnostic routines, autoboot procedures, and if necessary,
invokes the command line. See Table 3-5 for default Cavium environment variables settings.
Hardware initialization
Monitor command prompt
U-Boot 1.1.1 (Jan 16 2009 - 14:26:14)0.9
OCTEON CN58XX-NSP revision: 1
Core clock: 750 MHz
DDR clock: 266 MHz (533 Mhz data rate)
DRAM: 4096 MB
Flash: 4 MB
Clearing DRAM........ done
PCI console init succeeded, 1 consoles, 1024 bytes each
Net: octspi0, octspi1
RLDRAM not present
Octeon BIST Passed
POST i2c PASSED
POST memory PASSED
2 ATCA-9305 (Mon 0.9)=>
Cavium Processor Complex: Cavium Monitor
10009109-01 ATCA-9305 User’s Manual 3-7
Figure 3-4: Power-up/Reset CN5860 Boot Sequence Flowchart
Diagnostic Tests During Power-up and Reset
The Cavium monitor diagnostic tests can be executed during power-up or invoked from the
monitor’s command prompt. This is accomplished by changing the state of the monitor
configuration parameters that define power-up and reset diagnostics mode. If the poweron-
diags parameter is set to “on”, the monitor invokes the diagnostic tests after a reset of the
hardware. Results are displayed to the console including whether the test passed or failed.
POST Diagnostic Results
The ATCA-9305 Power-On Self-Test (POST) diagnostic results are stored as a 32-bit value in
memory accessible by the management console at location 0x80080A6C. Each bit indicates
the result of a specific test, so this field can store the results of up to 32 diagnostic tests.
Table 3-4 assigns the bits to specific tests.
Power-up or Reset
Cavium Hardware
Wait for PCI load of U-boot
U-Boot Monitor
Default Board Initialization
U-Boot Monitor
Execute POST
U-Boot Monitor
Start Autoboot Sequence
(Boot Operating System)
Operating System Boot
Boot OS image
according to
configuration parameters
Cavium Processor Complex: Cavium Monitor
ATCA-9305 User’s Manual 10009109-01
3-8
Table 3-4: POST Diagnostic Results–Bit Assignments
Cavium Environment Variables
The following table lists the standard Cavium environment variables:
Table 3-5: Standard Cavium Environment Variables
Bit:
Diagnostic
Test: Description: Value:
0-1 Reserved
0 Passed the test
1 Failure detected
2 DRAM Verify address and data lines are intact
3Cavium BIST-
4I
2C Verify all local I2C devices are connected
to the I2C bus
5-31 Reserved
Variable:
Default
Value: Description:
baudrate 115200 Console port baud rate
Valid rates: 9600, 14400, 19200, 38400, 57600, 115200
bootcmd " " Command to execute when auto-booting or executing
the ‘bootd’ command
bootdelay 0 Choose the number of seconds the Monitor counts down
before booting user application code
Valid options: time in seconds, -1 to disable autoboot
bootfile " " Path to boot file on server (used with TFTP)—set this to
“path/file.bin” to specify filename and location of the file
to load.
ethaddr undefined SPI 1 MAC address
eth1addr undefined SPI 2 MAC address
ethact octspi0 Specifies Ethernet port to use
gatewayip 0.0.0.0 Select the network gateway machine IP address
hostname none Target hostname
ipaddr 0.0.0.0 Board IP address
loadaddr 0x20000000 Define the address to download user application code
(used with TFTP)
netmask 0.0.0.0 Board sub-network mask
powerondiags off Turns POST diagnostics on or off after power-on/reset
Valid options: on, off
rootpath eng/ Path name of the NFS’ server root file system
serial# xxxxx Board serial number
serverip 0.0.0.0 Boot server IP address
stderr serial Sets the standard destination for console error reporting
Valid options: serial, pci
Cavium Processor Complex: Memory
10009109-01 ATCA-9305 User’s Manual 3-9
MEMORY
The processor complex supports DDR2 Synchronous DRAM (SDRAM) and Reduced Latency
DRAM (RLDRAM) memory devices.
DDR2 SDRAM
The ATCA-9305 supports up to 16 gigabytes of 144-bit wide DDR2 SDRAM per processor
complex. The SDRAM interface clock speed frequency is 400 MHz. The four low-profile,
dual-inline memory modules (buffered DIMM) are installed in 240-pin very low profile (VLP)
sockets to reduce board density and routing constraints. A 2 KB EEPROM on the DIMM pro-
vides the serial presence detection (SPD). On-card SDRAM occupies physical addresses
from 0,0000,0000,000016 to 0,0003,FFFF,FFFF16.
Each processor memory bus is operating in 144-bit mode. Error-correcting Code (ECC) is
performed on the memory bus so that the CN5860 detects all double-bit errors, multi-bit
errors within a nibble, and corrects all single-bit errors.
RLDRAM
Each CN5860 supports 256 MB Common I/O (CIO) RLDRAM operating up to 400 MHz
(depends on the processor speed). The Micron RLDRAM II is organized as 32Mx18x8 internal
banks. The DDR I/O interface transfers two data words per clock cycle. Output data is refer-
enced to the free-running output data clock. Read and write accesses to the RLDRAM are
burst-oriented. RLDRAM is accessed by using Cavium-specific instructions which operate on
MIPS Coprocessor 2.
I2C EEPROM
Each Cavium processor complex has one user EEPROM device for parameter storage located
on the I2C bus, address 0xA8. The I2C bus for each processor is completely independent
from the other CN5860 processor and MPC8548 processor I2C buses. The Atmel two-wire
serial EEPROM on each CN5860 processor I2C interface consists of the Serial Clock (SCL)
input and the Serial Data (SDA) bidirectional lines.
stdin serial Sets the standard source for console input
Valid options: serial, pci
stdout serial Sets the standard destination for console output
Valid options: serial, pci
Variable:
Default
Value: Description: (continued)
Cavium Processor Complex: StratixGX Interconnect
ATCA-9305 User’s Manual 10009109-01
3-10
Table 3-6: Cavium NVRAM Memory Map
Flash, 512 KB x 8
The 512 KB of 32-pin PLCC socketed flash starts at physical address1D46,000016 and is used
for Engineering code. The StrataFlash features high-performance fast asynchronous access
times, low power, and flexible security options.
Flash, 4 MB x 16
The 4 MB soldered NOR flash starts at physical address 1D05,000016. The 32-Mbit device
provides CN5860 code storage and non-volatile memory.
STRATIXGX INTERCONNECT
The Altera StratixGX FPGA provides the high-speed SPI-4.2 interconnect. Each complex has
dual SPI-to-XAUI bridges connected to the XAUI Ethernet switch ports.
PLD Registers
The FPGA bridge is located at address 0x1D030000. Use the following registers to access
the XAUI to SPI bridge configuration registers. See the “Read Example” and “Write Exam-
ple.”
Data Registers
Register 3-1: Data 31:24 (0x0)
Address Offset
(hex): Description:
Window
Size (bytes)
0x1E00-0x1FFF Monitor parameters 256
0x0000-0x1D36 User defined 79F
Bits: R/W: Function:
7R/WData 31
6R/WData 30
5R/WData 29
4R/WData 28
3R/WData 27
2R/WData 26
1R/WData 25
0R/WData 24
Cavium Processor Complex: StratixGX Interconnect
10009109-01 ATCA-9305 User’s Manual 3-11
Register 3-2: Data 23:16 (0x1)
Register 3-3: Data 15:8 (0x2)
Register 3-4: Data 7:0 (0x3)
Bits: R/W: Function:
7R/WData 23
6R/WData 22
5R/WData 21
4R/WData 20
3R/WData 19
2R/WData 18
1R/WData 17
0R/WData 16
Bits: R/W: Function:
7R/WData 15
6R/WData 14
5R/WData 13
4R/WData 12
3R/WData 11
2R/WData 10
1R/WData 9
0R/WData 8
Bits: R/W: Function:
7R/WData 7
6R/WData 6
5R/WData 5
4R/WData 4
3R/WData 3
2R/WData 2
1R/WData 1
0R/WData 0
Cavium Processor Complex: StratixGX Interconnect
ATCA-9305 User’s Manual 10009109-01
3-12
Address Registers
Register 3-5: Address 9:8 (0x4)
Register 3-6: Address 7:0 (0x5)
Control Register
The write only Control register performs two functions:
• Writing a value of 0x01 causes the contents of the Data registers to be written to the
FPGA bridge at the location specified by the Address registers.
• Writing a value of 0x02 causes the contents of the Data registers to be overwritten by the
contents of the FPGA bridge at the location specified by the Address registers.
Note: Writing any other value to the Control register will be ignored.
Register 3-7: Control (0x6)
Bits: R/W: Function:
7 — Reserved
6 —
5 —
4 —
3 —
2 —
1R/WAddress 9
0R/WAddress 8
Bits: R/W: Function:
7R/WAddress 7
6R/WAddress 6
5R/WAddress 5
4R/WAddress 4
3R/WAddress 3
2R/WAddress 2
1R/WAddress 1
0R/WAddress 0
Bits: R/W: Function:
7 — Reserved
6 —
5 —
4 —
3 —
2 —
Cavium Processor Complex: StratixGX Interconnect
10009109-01 ATCA-9305 User’s Manual 3-13
Version Register
This read-only register tracks the PLD versions. The version is hard coded in the PLD and
changes with every released code change. Version starts at 0116.
Register 3-8: Version (0x7)
Scratch Register
All registers in this range act as the same register.
Register 3-9: Scratch (0x8-0x3F)
Read Example: To read the FPGA bridge SPI_COMMAND register at 0x204, use the following commands.
Set address bits 9:8.
=>write64b 1d030004 02
Set address bits 7:0.
=>write64b 1d030005 04
1W Read
0W Write
Bits: R/W: Function:
7R 0x01
6R
5R
4R
3R
2R
1R
0R
Bits: R/W: Function:
7R/W
6R/W
5R/W
4R/W
3R/W
2R/W
1R/W
0R/W
Bits: R/W: Function:
Cavium Processor Complex: Headers and Connectors
ATCA-9305 User’s Manual 10009109-01
3-14
Perform a read.
=>write64b 1d030006 02
Display the results.
=>read64l 1d030000
Write Example: To write to the FPGA bridge MAC_CMD_CFG register at 0x00C, use the following com-
mands.
Set data bits 31:24.
=>write64b 1d030000 a9
Set data bits 23:16.
=>write64b 1d030001 b8
Set data bits 15:8.
=>write64b 1d030002 c7
Set data bits 7:0.
=>write64b 1d030003 d6
Set address bits 9:8.
=>write64b 1d030004 00
Set address bits 7:0.
=>write64b 1d030005 0c
Perform a write.
=>write64b 1d030006 01
HEADERS AND CONNECTORS
COP/JTAG Headers
The CN5860 processor complex uses headers J1 and J15 for debug.
Table 3-7: CN5860 Processor COP/JTAG Headers
Pin: J1 (processor 2): J15 (processor 1):
1 P2_ETRST* P1_ETRST*
2 ground ground
3P2_TDI P1_TDI
4 ground ground
Cavium Processor Complex: Headers and Connectors
10009109-01 ATCA-9305 User’s Manual 3-15
Console Serial Ports (optional)
Connectors P6 (processor P1) and P5 (processor P2) access the CN5860 processors for Engi-
neering debug use only. The supported baud rates for these ports operate at 9600, 14400,
19200, 38400, 57600, and 115200 bps. (The default rate is 115200 bps.)
Table 3-8: CN5860 Processor Debug Headers
5P2_ETDO P1_ETDO
6 ground ground
7P2_TMS P1_TMS
8 ground ground
9 P2_TCK P1_TCK
10 ground ground
11 P2_EJTAG_RST P1_EJTAG_RST
12 key (pin not installed) key (pin not installed)
13 P2_EJTAG_DINT P1_EJTAG_DINT
14 P2_COP_PWR (3.3V) P1_COP_PWR (3.3V)
Pin: P6: P5:
1no connect no connect
2 P1_SER1_RXD P2_SER1_RXD
3 P1_SER1_TXD P2_SER1_TXD
4no connect no connect
5 signal ground signal ground
6-7 shield signal ground
Pin: J1 (processor 2): J15 (processor 1): (continued)
ATCA-9305 User’s Manual 10009109-01
3-16
(blank page)
10009109-01 ATCA-9305 User’s Manual 4-1
Section 4
Management Complex
The ATCA-9305 management complex is comprised of the Freescale MPC8548 processor,
CPLD, SDRAM, flash, I2C EEPROM, Real-time Clock, and PCI bus interface. Board power-up,
booting and monitoring the Cavium processors, PCI bus arbitration, interrupt servicing,
memory persistence functionality, and other board level management tasks are imple-
mented using the MPC8548 processor. The MPC8548 stores the Cavium operating system
and monitor code in its local memory and then uses the boot over PCI functionality to bring
up the Cavium processor complexes. The CPLD registers are described in Chapter 5. See
Chapter 9 for the Management Processor Monitor.
The management complex connects to the Broadcom Ethernet switch via a 1000BASE-T
Ethernet port. This connection uses the TSEC2 interface operating in SGMII mode. See
Chapter 6, “Ethernet Interface.”
Figure 4-1: MPC8548 Management Processor Complex Block Diagram
PCI Bus
RJ45 RJ45
NAND
Flash
1GB
x 16
BCM56802
XAUI 10 Gb
Switch
3
SGMII
4
SGMII
PCI Bus
IDSEL13
KSL
CPLD
Latched Adrs
A/D
Adrs/Data
Console
I2C
EEPROM
RTC
MPC8548
Management
Processor
J30
Socketed
ROM
512KB
x 8
PQ DDR2
SDRAM
NOR
Flash
4M
x 16
I2C
EEPROM
COP/JTAG
PCIe x4
NOR
Flash
512Mb or
64MB x 16
To Cavium
Processor 2
& Ethernet Switch
To Cavium
Processor 1
Management Processor Complex
PHY
PHY PHY
Management Complex: MPC8548 Processor
ATCA-9305 User’s Manual 10009109-01
4-2
MPC8548 PROCESSOR
The MPC8548 processor has the following features:
Table 4-1: MPC8548 Features
For more detailed information, reference the Freescale MPC8548E PowerQUICC™ III Inte-
grated Processor Family Reference Manual.
MPC8548 Memory Map
The monitor can boot from either the soldered flash (Bank 1, default) or the socketed PLCC
device. Based on the configuration header (see page 2-8) either the socketed device or sol-
dered flash is mapped to the boot bank at FFF8,000016, see Fig. 4-2. Information on particu-
lar portions of the memory map can be found in later sections of this manual, see Table 4-2.
Feature: Description:
L1 Cache 32-kilobyte data and instruction caches with parity protection, 32-
byte line, eight-way set associative
L2 Cache 512 kilobytes, eight-way set associative
CPU Core Speed 1 GHz with a 400 MHz DDR2 bus
DDR2 Memory Controller 64-bit data interface, four banks of memory supported (each up to 4
GB), full ECC support
Dual I2C Controllers Two-wire interface, master or slave I2C support
Boot Sequencer Loads configuration data from serial ROM at reset via the I2C interface
Ethernet Four 10/100/1000 enhanced three-speed controllers (eTSECs), full-
/half-duplex support, MAC address recognition
Local Bus Controller (LBC) DDR2 SDRAM memory controller, General Purpose Chip Select
Machine (GPCM), three User-Programmable Machines (UPM), eight
chip selects support eight external slaves
PCI 64-bit, PCI 2.2 compatible
PCI Express Single x4 PCIe high-speed interconnect, complies with PCI Express™
Base Specification Revision 1.0a
JTAG Complies with IEEE Std. 1149.1
Management Complex: MPC8548 Processor
10009109-01 ATCA-9305 User’s Manual 4-3
Figure 4-2: MPC8548 Memory Map
Table 4-2: MPC8548 Address Summary
Hex Physical
Address:
Access
Mode: Register Description:
See
Page:
FFF8,0000 R/W Boot window (512 KB) —
FF80.0000 —reserved (7.5 MB)
FF70,0000 R/W MPC8548 CCSRBAR (1MB) —
FC88,0000 —reserved (46 MB)
E000,0000
EFFF,FFFF
F000,0000
SDRAM DDR2 (2 GB)
Soldered Flash Bank 4 (32 MB)
Soldered Flash Bank 3 (32 MB)
PCI (1.5 GB)
Soldered Flash Bank 2 (4 MB)
Reserved (64 MB)
NAND Flash (32 KB)
LPC Interface (64 KB)
Reserved (992 KB)
Reserved (2.9 MB)
CPLD Registers (512 KB)
Reserved (3.5 MB)
Socketed Flash, optional (512 KB)
Reserved (46 MB)
MPC8548 CCSRBAR (1 MB)
Reserved (7.5 MB)
Boot Window (512 KB)
F3C0,0000
F400,0000
F600,0000
F800,0000
FC00,0000
FC00,8000
FC10,0000
FC11,0000
FC40,0000
FC48,0000
FC80,0000
FC88,0000
FF70,0000
FF80,0000
FFF0,0000
F3BF,FFFF
F3FF,FFFF
F5FF,FFFF
F7FF,FFFF
FBFF,FFFF
FC00,7FFF
FC0F,FFFF
FC10,FFFF
FC3F,FFFF
FC47,FFFF
FC7F,FFFF
FC87,FFFF
FF6F,FFFF
FF7F,FFFF
FFEF,FFFF
FFFF,FFFF
Address Range
Reserved (56 MB)
F080,0000
F3FF,FFFF
PCI Express (256 MB)
Soldered Flash Bank 1 (4 MB)
8000,0000
DFFF,FFFF
0000,0000
7FFF,FFFF
Product ID
Hardware Version
PLD Version
PLL Configuration
Hardware Configuration 0
reserved
Jumper Setting
LED
Reset Event
Reset Command #1
Reset Command #2
Reset Command #3
Reset Command #4
Reset Command #5
Reset Command Sticky #1
Reset Command Sticky #2
Scratch #1
Boot Device Redirection
Miscellaneous Control
RTM GPIO State
RTM GPIO Control
RTM Control
Cavium 1 Clock Divisor Control
Cavium 2 Clock Divisor Control
Altera JTAG Software Control
Cavium GPIO Control
LPC Data
IPMP/IPMC GPIO Control
LPC Bus Control
FC40,0000
FC40,0004
FC40,0008
FC40,000C
FC40,0010
FC40,0014
FC40,0018
FC40,001C
FC40,0020
FC40,0024
FC40,0028
FC40,002C
FC40,0030
FC40,0034
FC40,0038
FC40,003C
FC40,0040
FC40,0050
FC40,0054
FC40,0060
FC40,0064
FC40,0068
FC40,0070
FC40,0074
FC40,0078
FC40,0080
FC40,0084
FC40,0088
FC40,008C
FC40,00D0
Hex Address
FC40,00D4
FC40,00D8 Serial IRQ Interrupt 1
Serial IRQ Interrupt 2
Cavium GPIO Data Output
Cavium GPIO Data Input
FC40,00DC
F0FF,FFFF
F380,0000
PCI Express I/O (16 MB)
Management Complex: MPC8548 Processor
ATCA-9305 User’s Manual 10009109-01
4-4
FC80,0000 R/W Socketed flash, optional (512 KB) 4-7
FC48,0000 —reserved (3.5 MB)
FC40,00DC0 R/W Serial IRQ Interrupt 2 5-15
FC40,00D8 R/W Serial IRQ Interrupt 1 5-15
FC40,00D4 R/W LPC Data 5-15
FC40,00D0 R/W Low Pin Count (LPC) Bus Control 5-14
FC40,008C R/W IPMP/IPMC GPIO Control 5-14
FC40,0088 R/W Cavium GPIO Data Input 5-13
FC40,0084 R/W Cavium GPIO Data Output 5-13
FC40,0080 R/W Cavium GPIO Control 5-12
FC40,0078 R/W Altera JTAG Chain Software Control 5-12
FC40,0074 R/W Cavium 2 C_MUL Clock Divisor Control 5-11
FC40,0070 R/W Cavium 1 C_MUL Clock Divisor Control 5-11
FC40,0068 R/W RTM Control 5-10
FC40,0064 R/W RTM GPIO Control 5-10
FC40,0060 R/W RTM GPIO State 5-10
FC40,0054 R/W Miscellaneous Control (SIO, I2C, Test Clock) 5-9
FC40,0050 R/W Boot Device Redirection 5-8
FC40,0040 R/W Scratch #1 —
FC40,003C R/W Reset Command Sticky #2 5-8
FC40,0038 R/W Reset Command Sticky #1 5-7
FC40,0034 W Reset Command #5 5-7
FC40,0030 W Reset Command #4 5-7
FC40,002C W Reset Command #3 5-6
FC40,0028 W Reset Command #2 5-6
FC40,0024 W Reset Command #1 5-5
FC40,0020 R/W Reset Event 5-5
FC40,001C R/W LED 5-4
FC40,0018 R/W Jumper Setting 5-4
FC40,0014 —reserved —
FC40,0010 R/W Hardware Configuration 0 5-3
FC40,000C R/W PLL Configuration 5-3
FC40,0008 R/W PLD Version 5-3
FC40,0004 R/W Hardware Version 5-2
FC40,0000 R/W Product ID (CPLD 512 KB) 5-2
FC11,0000 reserved (2.9 MB)
FC10,0000 R/W LPC Interface (64 KB) 4-5
FC00,8000 —reserved (992 KB)
FC00,0000 R/W NAND flash (32 KB) 4-8
Hex Physical
Address:
Access
Mode: Register Description: (continued)
See
Page:
Management Complex: MPC8548 Processor
10009109-01 ATCA-9305 User’s Manual 4-5
Chip Selects
The MPC8548 memory controller functions as a chip select (CS) generator to access on-
board memory devices. In order to select one device over another, the following chip
selects have been established.
Table 4-3: Device Chip Selects
F800,0000 —reserved (64 MB)
F600,0000 R/W Soldered flash bank 4 (32 MB) 4-7
F400,0000 R/W Soldered flash bank 3 (32 MB) 4-7
F080,0000 —reserved (56 MB)
F3C0,0000 R/W Soldered flash bank 2 (4 MB) 4-7
F380,0000 R/W Soldered flash bank 1 (4 MB) 4-7
F000,0000 R/W PCI Express I/O space (16 MB) 4-8
E000,0000 R/W PCI Express (256 MB) 4-8
8000,0000 R/W PCI (1.5 GB) 4-8
0000,0000 R/W SDRAM DDR2 (2 GB) 4-7
Pin: Signal:
0Boot bank 1
1. Boot bank can be either socketed flash, flash 1, or flash 2;
depending on the jumper setting (see Fig. 2-6).
1 Soldered flash boot bank 1 (default)
2 Soldered flash boot bank 2
3Socketed flash (optional)
4KSL CPLD registers
5NAND flash
6 Soldered NOR flash boot banks 3 and 4
7LPC interface
Hex Physical
Address:
Access
Mode: Register Description: (continued)
See
Page:
Management Complex: MPC8548 Processor
ATCA-9305 User’s Manual 10009109-01
4-6
Reset Diagram
Figure 4-3: MPC8548 Reset Diagram
NAND
Flash
1GB
x 16
PQ_HRESET*
MPC8548MPC8548
ManagementManagement
ProcessorProcessor
PQ DDR2PQ DDR2
SODIMMSODIMM
Module Module
NOR
Flash
4M
x 16
Ethernet Port
BCM5461S
PQ_SRESET*
PQ_TRST*
RESET_INDICATION*
I2C1
I2C2
Reset to IPMC
FLASH_RST*
NAND_RST*
NAND_WARM_RST*
PQ_DDR_RST*
TSEC1_RST*
Ethernet Port
BCM5461S
Ethernet Port
BCM5461S
Ethernet Port
BCM5482
TSEC2_RST*
FP1_RST*
BC_RST*
Voltage
Monitor
Delay
IPMC
KSL
CPLD
IPMP
CPLD
PWRGD_OK
L_PAYLD_EN
3_3V_PWRGD
2_5V_PWRGD
1_8V_PWRGD
1_2V_PWRGD
1_0V_PWRGD
PQ_CORE_PWRGD*
P1_CORE_PWRGD*
P2_CORE_PWRGD*
POR_RST*
48A_OK
48B_OK
E_HANDLE
I2C IO
Port
BOOT_REDIR
BOOT_SEL0
BOOT_SEL1
L_PAYLOAD_RST*
PRIV_I2C_SCL
PRIV_I2C_SDA
IPMC_PO_RST*
3_3V_MP
IPMC Reset
3_3V_MP
Hot Swap
Switch
3_3V_MP
3_3V_MP
Front
Panel
Reset
3_3V
Voltage
Monitor
Delay
33MHz
IPMC_PO_RST*
Management Complex: Memory
10009109-01 ATCA-9305 User’s Manual 4-7
MEMORY
The memory devices in the management complex consist of:
• 1 GB DDR2 SDRAM
• 512 KB socketed flash
• 8 MB soldered NOR flash (two redundant banks of 4 MB each)
• 1 GB soldered NAND flash
• 512 Mb or 64 MB soldered NOR flash
SDRAM
This is a specialized, socketed, 200-pin, small outline, clocked, dual in- line, memory mod-
ule (SO-CDIMM). It provides Error-correcting Code (ECC) on the SDRAM memory bus oper-
ating at 200 MHz. The MPC8548 detects all double-bit errors, multi-bit errors within a
nibble and corrects all single-bit errors.
The 128M X 72 DDR2 SDRAM is a high-density, un-buffered SO-CDIMM. This module con-
sists of nine 128x8-bit with eight banks DDR2 SDRAMs, a zero delay phase-lock loop (PLL)
clock, and a 2 KB serial presence detect (SPD) EEPROM. The SDRAM starts at physical
address 0000,000016.
Flash
There are several flash devices on the local bus interfacing the CPLD and MPC8548 proces-
sor. The four soldered flash banks are labeled 1 through 4:
• Banks 1 and 2 are the MPC8548 U-boot banks (see “4M x 16”). These boot banks are
used in the boot redirection scheme, see “Boot Device Redirection (BDR).”
• Banks 3 and 4 are physically one device, but appear in the software as two banks of 32
MB (see “64 MB x 16”). These are for general purpose storage.
512 KB x 8 (optional)
The 512 KB of 32-pin PLCC socketed flash starts at physical address FC80,000016 and is used
for Engineering code. The StrataFlash (P33) features high-performance fast asynchronous
access times, low power, and flexible security options.
4M x 16
The two 4 MB soldered flash devices are used for MPC8548 boot code. This redundant bank
configuration allows booting from either bank in case of corruption in one bank. See “Boot
Device Redirection (BDR)” on page 7-41. The SST NOR flash devices are organized as 4Mx8
Management Complex: PCI
ATCA-9305 User’s Manual 10009109-01
4-8
in a dual-bank architecture for concurrent read/write operation with hardware and software
data protection schemes. These devices start at physical addresses F000,000016 (boot bank
1) and F040,000016 (boot bank 2).
1 GB x 16
The ATCA-9305 uses 1 GB of M-Systems DiskOnChip (mDOC H3) NAND flash starting at
physical address FC00,000016 for non-volatile RAM storage and True Flash File System
(TFFS). This memory incorporates an embedded flash controller and memory, and includes
hardware protection and security-enabling features, an enhanced programmable boot
block enabling eXecution In Place (XIP) functionality using 16-bit access, user-controlled
One Time Programmable (OTP) partitions, and 6-bit Error Detection Code/Error Correction
Code (EDC/ECC).
64 MB x 16
The 64 MB soldered NOR flash starts at physical address F400,000016 (bank 3). The 64-Mbit
P33 device provides CN5860 code storage and non-volatile memory.
PCI
The MPC8548 performs all the functions of a PCI host and monarch, and handles all arbitra-
tion and enumeration functions. PCI starts at physical address 8000,000016.
The PCI bus connects to both Cavium processors, the MPC8548 processor and the Broad-
com Ethernet switch, see Table 4-4. All of the devices on the PCI bus can operate at 66 MHz
and perform 64-bit transactions in conventional PCI mode except for the Broadcom switch.
The switch has a 32-bit PCI bus.
The MPC8548 stores the Cavium CN5860 operating system and monitor code in local
memory and then uses the boot over PCI functionality to bring up the CN5860 processor
complexes.
Table 4-4: PCI Device Interrupts and ID Assignments
PCI Express
The four lane PCIe routes between the MPC8548 and the optional rear transition module
(zone 3 connector). PCIe starts at physical address E000,000016.
PCI Device: Interrupt: IDSEL:
Cavium processor 1 IRQ6 PCI_AD11
Cavium processor 2 IRQ5 PCI_AD12
Ethernet switch IRQ4 PCI_AD13
MPC8548 — PCI_AD14
Management Complex: I2C Interface
10009109-01 ATCA-9305 User’s Manual 4-9
I2C INTERFACE
The I2C interface consists of the MPC8548 initialization EEPROM, user (storage) NVRAM,
SO-CDIMM, and the Real-time Clock (RTC). The two Atmel two-wire serial EEPROMs on the
I2C interface consist of the Serial Clock (SCL) input and the Serial Data (SDA) bidirectional
lines.
Table 4-5: I2C Device Addresses
The two EEPROMs store non-volatile information such as board, monitor, and operating sys-
tem configurations as well as customer specific items.
Table 4-6: MPC8548 NVRAM Memory Map
Note: Both EEPROMs are write-protected.
MANAGEMENT PROCESSOR HEADER AND SERIAL PORT
JTAG/COP Interface (optional)
The management complex uses header P2 for debug purposes.
Table 4-7: Serial Debug Connector, P2
I2C Device: Address:
MPC8548 Initialization (EEPROM-2) 0xA0
User NVRAM (EEPROM-1) 0xA2
DDR2 SDRAM (SO-CDIMM) 0xA4
M41T00 RTC 0xD0
EEPROM:
Address Offset
(hex): Description:
Window
Size (bytes)
EEPROM-1
0xA2
(write
protected)
0x1FF0-0x1FFF Boot verify secondary area (monitor) 16
0x1FE0-0x1FEF Boot verify primary area (monitor) 16
0x1EE0-0x1FDF Operating system parameters (monitor) 256
0x0000-x1EDF User defined 7903
EEPROM-2
0xA0
(write
protected)
0x0900-0x1FFF Emerson reserved area 5887
0x0800-0x08FF Miscellaneous 256
0x07F0-0x07FF Power-on Self-test (POST) 16
0x0000-0x07EF User defined 2032
Pin: Signal: Description:
1 PQ_TDO Test Data Output is the serial data output as well as test and
programming data.
2no connect —
Management Complex: Management Processor Header and Serial
ATCA-9305 User’s Manual 10009109-01
4-10
Serial Debug Port
The console port for the management processor is accessible via the front panel mini-B USB
connector P7. The supported baud rates for these ports operate at 9600, 14400, 19200,
38400, 57600, and 115200 bps.
Table 4-8: Serial Debug Connector, P7
3 PQ_TDI Test Data Input is the serial input pin for instructions as well as test and
programming data.
4 DEBUG_TRST* Test Reset input signal resets the test access port.
5no connect —
6 PQ_JTAG_PWR 3.3 volt power
7 PQ_TCK_R Test Clock Input is the clock input to the boundary scan test (BST)
circuitry.
8no connect —
9 PQ_TMS Test Mode Select input pin provides the control signal to determine
the transitions of the TAP controller state machine.
10 no connect —
11 DEBUG_SRESET* Soft Reset input signal indicates that the MPC8548 must initiate a
System Reset interrupt.
12 ground —
13 DEBUG_HRESET* Hard Reset input signal indicates that a complete Power-on Reset must
be initiated by the MPC8548.
14 no connect —
15 PQ_CKSTP_OUT* Checkstop Out indicates the MPC8548 has detected a checkstop
condition and has ceased operation.
16 ground —
Pin: Signal:
1no connect
2 PQ_CONSOLE_RX_C
3 PQ_CONSOLE_TX_C
4no connect
5 signal ground
6 chassis ground
7 chassis ground
Pin: Signal: Description: (continued)
10009109-01 ATCA-9305 User’s Manual 5-1
Section 5
Management Processor CPLD
The ATCA-9305 uses a Programmable Logic Device (PLD) to provide control logic for the
local bus. The PLD implements various registers for reset, hardware, and LPC bus communi-
cation between the processors.
MPC8548 PLD REGISTER SUMMARY
The PLD registers start at address FC40,000016. As a rule, registers retain their values
through all resets except for power-on and front panel reset. Table 5-1 lists the 8-bit PLD reg-
isters followed by the register bit descriptions.
Table 5-1: PLD Register Summary
Address
Offset (hex): Mnemonic: Register Name: See Page:
0x00 PIDR Product ID 5-2
0x04 HVR Hardware Version 5-2
0x08 PVR PLD Version 5-3
0x0C PLLCR PLL Configuration 5-3
0x10 HCR00 Hardware Configuration 0 5-4
0x18 JSR Jumper Setting 5-4
0x1C LEDR LED 5-5
0x20 RER Reset Event 5-5
0x24 RCR1 Reset Command #1 5-6
0x28 RCR2 Reset Command #2 5-6
0x2C RCR3 Reset Command #3 5-6
0x30 RCR4 Reset Command #4 5-7
0x34 RCR5 Reset Command #5 5-7
0x38 RCRS1 Reset Command Sticky #1 5-8
0x3C RCRS2 Reset Command Sticky #2 5-8
0x40 SCR1 Scratch #11—
0x50 BDRR Boot Device Redirection 5-9
0x54 MISC Miscellaneous Control (SIO, I2C, Test Clock) 5-9
0x58 LFTR1 Low Frequency Timer 1 5-9
0x5C LFTR2 Low Frequency Timer 2 5-9
0x60 RGSR RTM GPIO State 5-10
0x64 RGCR RTM GPIO Control 5-10
0x68 RTMCR RTM Control 5-11
0x70 CMUL1 Cavium 1 C_MUL Clock Divisor Control 5-11
0x74 CMUL2 Cavium 2 C_MUL Clock Divisor Control 5-12
0x78 JTAG Altera JTAG Chain Software Control 5-12
0x80 CGCR Cavium GPIO Control 5-12
Management Processor CPLD: MPC8548 PLD Register
ATCA-9305 User’s Manual 10009109-01
5-2
Product ID
This read-only register identifies the board as ATCA-9305, and is used for PLD coding.
Register 5-1: Product ID (0x00)
Hardware Version
This read-only register tracks hardware revisions.
Register 5-2: Hardware Version (0x04)
0x84 CGDO Cavium GPIO Data Out 5-13
0x88 CGDI Cavium GPIO Data In 5-13
0x8C IGCR IPMP/IPMC GPIO Control 5-14
0xD0 LPC1 Low Pin Count (LPC) Bus Control 5-14
0xD4 LPCD LPC Data 5-15
0xD8 SIRQI1 Serial IRQ Interrupt 1 [15:8] 5-15
0xDC SIRQI2 Serial IRQ Interrupt 2 [7:0] 5-15
1. Scratch 1 (0x40) is a read/write register for storage only.
Bits: Function: Description:
7 CAVF1 Cavium Frequency 1
6 CAVF0 Cavium Frequency 0
50 Product ID
40
30
20
1 HC1 Hardware Configuration 1
0 HC0 Hardware Configuration 0
Bits: Function: Description:
70
60
50
40
3 HVN (3) Hardware Version Number is hard coded in the PLD and changes
with every major PCB artwork version.
Version starts at 0016.
2HVN (2)
1HVN (1)
0HVN (0)
Address
Offset (hex): Mnemonic: Register Name: (continued) See Page:
Management Processor CPLD: MPC8548 PLD Register
10009109-01 ATCA-9305 User’s Manual 5-3
PLD Version
This read-only register tracks PLD revisions.
Register 5-3: PLD Version (0x08)
PLL Reset Configuration
Write to this register to reconfigure the SYSCLK to CCB clock ratio and the CCB to CORE
clock ratio using valid values from the MPC8548E PowerQUICC™ III Integrated Processor Family
Reference Manual. The changes take affect when the processor is reset (for example, the
software hard reset command or watchdog timer expires). Default values are restored
when the board is power-cycled, front panel reset is pressed, or receives a PCI reset that was
not the result of the MPC8548 software initiating a PCI RSTOUT command.
Register 5-4: PLL Reset Configuration (0x0C)
Hardware Configuration 0
The read-only HCR0 allows the MPC8548 monitor software to easily determine specific
hardware configurations, such as the processor clock and MPC8548 DDR memory.
Bits: Function: Description:
7 0 This is hard coded in the PLD and changes with every released code
change. Version starts at 0016.
60
50
40
30
20
10
00
Bits: Function: Description:
7reserved
6 CCCB2 CCB2 to CORE clock ratio
5 CCCB1 CCB1 to CORE clock ratio
4 CCCB0 CCB0 to CORE clock ratio
3 CCBSYS3 SYSCLOCK3 to CCB clock ratio
2 CCBSYS2 SYSCLOCK2 to CCB clock ratio
1 CCBSYS1 SYSCLOCK1 to CCB clock ratio
0 CCBSYS0 SYSCLOCK0 to CCB clock ratio
Management Processor CPLD: MPC8548 PLD Register
ATCA-9305 User’s Manual 10009109-01
5-4
Register 5-5: Hardware Configuration 0 (0x10)
Jumper Settings
These read-only bits may be read by software to determine the current jumper settings. See
the jumper descriptions on page 2-8.
Register 5-6: Jumper Settings (0x18)
LED
Writing a one to an LED bit lights that LED. During monitor power-up, the debug LEDs are
used to display the software progress.
Bits: Function: Description:
70
6 P33P P33 (StrataFlash) is Present
5 RST_IND_CLR Clear the Reset Indication to the IPMC controller
4 CAVF1 Cavium Frequency 1
3 CAVF0 Cavium Frequency 0
2 PQCF1 MPC8548 Core Frequency 1
1 PQCF0 MPC8548 Core Frequency 0
0 PQDDRF MPC8548 DDR SDRAM Fast
Bits: Function: Description:
70
60
50
4 SJ Cavium Boot Flash Jumper
0 Installed, Cavium processors boot from soldered flash
1 Not installed, Cavium processors boot from socket
3BOOT Boot PCI Jumper
0 Installed, boot from flash (socket or soldered per bit 4)
1 Not installed, boot over PCI from the MPC8548
2 REDIR Boot Redirect Jumper
0 Installed, disables boot redirection
1 Not installed, enables boot redirection
1IG ROM Ignore SROM
0 Not installed, SROM is used for initialization (default)
1 Installed, disables SROM, uses default values in monitor
code
0 BT SKT Boot from Socket
0 Not installed, enables MPC8548 to boot from soldered
flash (default)
1 Installed, enables MPC8548 to boot from socketed flash
Management Processor CPLD: MPC8548 PLD Register
10009109-01 ATCA-9305 User’s Manual 5-5
Register 5-7: LED (0x1C)
Reset Event
This read-only register contains the bit corresponding to the most recent event which
caused a reset. When power is first applied, the FP_PSH_BUTTN reset event is not latched
into the Reset Event register, this is the Power-on Reset (POR) event. Front panel reset
events which occur after power-up will be latched.
Note: At power-up, the FRST_PWR_UP defaults to 1.
Register 5-8: Reset Event (0x20)
Reset Command 1
The write-only Reset Command 1 register forces one of several types of resets, as shown
below. A reset sequence is first initiated by writing a one to a single valid bit, then the PLD
performs that particular reset, and the bit is automatically cleared.
Bits: Function: Description:
7 PQRED MPC8548 red LED
Lit on power-up and turned off when the monitor finishes boot
up and Power-on Self Testing (POST)
6 PQGREEN MPC8548 green LED
5 SWLEDCLK Ethernet Switch LED Clock
4 SWLEDDAT Ethernet Switch LED Data
3 DEBUGLED3 LED CR22
2 DEBUGLED2 LED CR21
1 DEBUGLED1 LED CR19
0 DEBUGLED0 LED CR18
Bits: Function: Description:
7 RTMPB RTM push button
6 SHR Software Hard Reset Set to 1 when the last reset was caused
by a write to the Reset Command register
5 CPUHRR CPU Hard Reset Request
4 COPSR Set to 1 when a COP header or software-issued Soft Reset
(SRESET) has occurred
3 COPHR Set to 1 when a COP header Hard Reset (HRESET) has occurred
2 PAYR Set to 1 when a Payload Reset from the IPMC has occurred
1SBR Software Board Reset
Set to 1 when the IPMC software issued the board (payload)
reset
0 FPPB Front Panel Push Button (FP_PSH_BUTTN, POR_RST)
Management Processor CPLD: MPC8548 PLD Register
ATCA-9305 User’s Manual 10009109-01
5-6
Register 5-9: Reset Command 1 (0x24)
Reset Command 2
The write-only Reset Command 2 register forces one of several types of MPC8548 resets, as
shown below. A reset sequence is first initiated by writing a one to a single valid bit, then the
PLD performs that particular reset, and the bit is automatically cleared.
Register 5-10: Reset Command 2 (0x28)
Reset Command 3
The write-only Reset Command 3 register forces one of several types of Cavium 1 resets, as
shown below. A reset sequence is first initiated by writing a one to a single valid bit, then the
PLD performs that particular reset, and the bit is automatically cleared.
Register 5-11: Reset Command 3 (0x2C)
Bits: Function: Description:
7 WBR Reset the Whole Board
6 PQCR Reset the MPC8548 Complex
5 CAV1CR Reset the Cavium CN5860 1 Complex
4 CAV2CR Reset the Cavium CN5860 2 Complex
3 SWICR Reset the switch BCM5680x Complex
2 I2C R Reset the I2C on the MPC8548
1 RTMR Reset the (optional) RTM
0reserved
Bits: Function: Description:
7 PQHR MPC8548 Hardware Reset
6 PQSR MPC8548 Software Reset
5 PQDR MPC8548 DDR SDRAM Reset
4 PQF MPC8548 Flash reset
3 NANDR MPC8548 NAND flash Reset
2 NANDWR MPC8548 NAND flash Warm Reset
1reserved
0reserved
Bits: Function: Description:
7 CAV1R Cavium 1 Reset
6 CAV1PR Cavium 1 PCI Reset
5 CAV1DR Cavium 1 DDR SDRAM Reset
4 CAV1F Cavium 1 4 MB Flash (Cavium local bus) reset
3 CAV1M1 Cavium 1 MIP1 reset
2 CAV1M2 Cavium 1 MIP2 reset
Management Processor CPLD: MPC8548 PLD Register
10009109-01 ATCA-9305 User’s Manual 5-7
Reset Command 4
The write-only Reset Command 4 register forces one of several types of Cavium 2 resets, as
shown below. A reset sequence is first initiated by writing a one to a single valid bit, then the
PLD performs that particular reset, and the bit is automatically cleared.
Register 5-12: Reset Command 4 (0x30)
Reset Command 5
The write-only Reset Command 5 register forces one of several types of BCM5680x Ethernet
switch resets, as shown below. A reset sequence is first initiated by writing a one to a single
valid bit, then the PLD performs that particular reset, and the bit is automatically cleared.
Register 5-13: Reset Command 5 (0x34)
Reset Command Sticky #1
The read/write Reset Command Sticky #1 register forces one of several types of the group-
complex resets, as shown below. A reset sequence is first initiated by writing a one to one or
more bits, then the PLD performs that particular reset. The bit will persist until cleared.
1reserved
0reserved
Bits: Function: Description:
7 CAV2R Cavium 2 Reset
6 CAV2PR Cavium 2 PCI Reset
5 CAV2DR Cavium 2 DDR SDRAM Reset
4 CAV2F Cavium 2 4 MB Flash (Cavium local bus) reset
3 CAV2M3 Cavium 2 MIP3 reset
2 CAV2M4 Cavium 2 MIP4 reset
1reserved
0reserved
Bits: Function: Description:
7 SWIR Switch Reset
6 TSEC1R TSEC1 Ethernet to front panel PHY Reset
5 TSEC2R TSEC2 Ethernet to switch PHY Reset
4 FPIR FPI Ethernet to front panel PHY Reset
3 BCR Ethernet dual PHY to backplane Base Channel reset
2reserved
1reserved
0reserved
Bits: Function: Description: (continued)
Management Processor CPLD: MPC8548 PLD Register
ATCA-9305 User’s Manual 10009109-01
5-8
Note: The board powers down and powers back up when the Cavium processors power is back up (bits 0 or 1 are
cleared).
Register 5-14: Reset Command Sticky #1 (0x38)
Reset Command Sticky #2
The read/write Reset Command Sticky #2 register forces one of several types of the PHY
reset command, as shown below. A reset sequence is first initiated by writing a one to one
or more bits, then the PLD performs that particular reset. The bit will persist until cleared.
Register 5-15: Reset Command Sticky #2 (0x3C)
Boot Device Redirection
The read/write Boot Device Redirection register (BDRR) allows the user to determine which
of three boot devices the MPC8548 CPU is using as the boot device. Several bits also indi-
cate which device was set as the initial boot device. The Boot Redirected bit is set to a 1
when the current boot device does not match the initial default boot device. This indicates
to the user that the image in the default device was bad, the MPC8548 watch dog timer
expired, and the next device was tried. The boot device redirection order is determined by
IPMC. Reference the “Boot Device Diagram”.
Bits: Function: Description:
7CAV1C Cavium 1 Complex reset
6CAV2C Cavium 2 Complex reset
5SWIC Switch Complex reset
4CAV1CF Cavium 1 Complex 4MB Flash reset
3CAV2CF Cavium 2 Complex 4MB Flash reset
2NANDF NAND Flash reset
1CAV2RPD Reset and power down the Cavium 2 core
0CAV1RPD Reset and power down the Cavium 1 core
Bits: Function: Description:
7 TSEC1R TSEC1 Ethernet to front panel PHY Reset
6 TSEC2R TSEC2 Ethernet to switch PHY Reset
5 FPIR FPI Ethernet from switch to front panel PHY Reset
4 BCR Ethernet dual PHY to backplane Base Channel Reset
3 MIP1 SPI to XAUI bridge #1 on Cavium 1
2 MIP2 SPI to XAUI bridge #2 on Cavium 1
1 MIP3 SPI to XAUI bridge #3 on Cavium 2
0 MIP4 SPI to XAUI bridge #4 on Cavium 2
Management Processor CPLD: MPC8548 PLD Register
10009109-01 ATCA-9305 User’s Manual 5-9
Register 5-16: Boot Device Redirection (0x50)
Miscellaneous Control
This register includes two bits for manually toggling the MPC8548 I2C bus.
Register 5-17: Miscellaneous Control (0x54)
Low Frequency Timer 1 and 2
Registers LFTR1 (0x58) and LFTR2 (0x5C) are timers. They determine how many 50 μs inter-
vals you want before the next interrupt on Cavium GPIO5.
Note: Unless the frequency is set to 0, there is always one 50 μs interval. This is the reason for the register setting
being 1 less than an even hundred, for example 199 rather than 200.
Bits: Function: Description:
7 SELFRS Self Refresh Started
6 BOOTSEL1 IPMC successful boot indication (BOARD_BOOTED)
5reserved
4 BSJ Boot from Socket Jumper A shunt on J9 [1:2] selects the
512KB socketed ROM as the boot device, see Fig. 2-6.
3 NFBS Nand Flash Busy Signal
2BDS Active boot device is socket
1 BDF1 Active boot device is flash 2
0 BDF0 Active boot device is flash 1
Bits: Function: Description:
7 P33WP 0 Write Protect disabled (default until the monitor boots)
1Write Protect enabled
6 SROM1WP 0 Write Protect disabled
1 Write Protect enabled (default)
5 SROM0WP 0 Write Protect disabled
1 Write Protect enabled (default)
4 FLASH1WP 0 Write Protect disabled (default until the monitor boots)
1Write Protect enabled
3 FLASH0WP 0 Write Protect disabled (default until the monitor boots)
1Write Protect enabled
2 NANDWP 0 Write Protect disabled
1 Write Protect enabled (default)
1I2CSDA I
2C Data line
0 Drive a 0 onto the I2C SDA line
1 Drive a 1 onto the I2C SDA line
0I2CSCL I2C Clock line
0Drive a 0 onto the I2C SCL line
1Drive a 1 onto the I2C SCL line
Management Processor CPLD: MPC8548 PLD Register
ATCA-9305 User’s Manual 10009109-01
5-10
Table 5-2: Low Frequency Timer Settings
RTM GPIO State
This read-only register reads the current state of the GPIO pins.
Register 5-18: RTM GPIO State (0x60)
RTM GPIO Control
This register sets the state of the GPIO pins. These signals are implemented as open collec-
tor signals.
Register 5-19: RTM GPIO Control (0x64)
RTM Status
The RTM identification (ID) is determined by factory installed configuration resistors.
Frequency: Set Register: Comments:
0 Off Never interrupts
1 Hz 19999 (0x4E1F) These frequencies require the use of both registers
10 Hz 1999 (0x7CF)
100 Hz 199 (0xC7)
1 KHz 19 (0x13)
10 KHz 1 This equals two 50 μs time units (default)
Bits: Function: Description:
7RTM_GPIO 7
6RTM_GPIO 6
5RTM_GPIO 5
4RTM_GPIO 4
3RTM_GPIO 3
2RTM_GPIO 2
1RTM_GPIO 1
0RTM_GPIO 0
Bits: Function: Description:
7 RTM_GPIO 7 0 Causes the corresponding bit to be driven to 0
1 Tristates the signal; this will either be read by the RTM as a 1
or can be driven by the RTM to any value
6RTM_GPIO 6
5RTM_GPIO 5
4RTM_GPIO 4
3RTM_GPIO 3
2RTM_GPIO 2
1RTM_GPIO 1
0RTM_GPIO 0
Management Processor CPLD: MPC8548 PLD Register
10009109-01 ATCA-9305 User’s Manual 5-11
Register 5-20: RTM Control (0x68)
Cavium 1 C_MUL Clock Divisor Control
Use the C_MUL1 register to reduce the speed of the Cavium CN5860 processor 1 core.
Caution: Do not over-clock the Cavium frequency (bits 6:7 hard strapped).
Register 5-21: Cavium 1 C_MULL Clock Divisor Control (0x70)
Cavium 2 C_MUL Clock Divisor Control
Use the C_MUL2 register to reduce the speed of the Cavium CN5860 processor 2 core.
Caution: Do not over-clock the Cavium frequency (bits 6:7 hard strapped).
Bits: Function: Description:
70
60
50
4 RTMP RTM is Present
3 RTMID3 RTM Identification bits 3:0
0000 = Test RTM (factory only)
1000 = 20GbE I/O RTM
1100 = 18GbE and 2x10GbE I/O RTM
1010 = Storage RTM
2RTMID2
1RTMID1
0RTMID0
Bits: Function: Description:
7 CAVF Cavium Frequency resistor set bit (read-only)
00 600
01 750
10 800
11 reserved
6
5CMULOE C_MUL Output Enable
4 P1CMUL4 These bits drive directly to the Cavium 1. The core clock speed
is the number multiplied by 50 MHz. For example, the 800 MHz
core is set to 16(0x10).
3P1CMUL3
2P1CMUL2
1P1CMUL1
0P1CMUL0
!
!
Management Processor CPLD: MPC8548 PLD Register
ATCA-9305 User’s Manual 10009109-01
5-12
Register 5-22: Cavium 2 C_MULL Clock Divisor Control (0x74)
JTAG
This register allows for manual reprogramming of the PLDs on the board. Changes to this
register do not take effect until after a full board reset.
Register 5-23: JTAG (0x78)
Cavium GPIO Control
Each Cavium processor has three GPIO control bits connected to the PLD. This register
determines whether the PLD is driving or receiving on these lines. Setting a bit to 1 causes
the PLD to drive the corresponding line.
Register 5-24: Cavium GPIO Control (0x80)
Bits: Function: Description:
7 CAVF1 Cavium 1 Frequency resistor set bit (read-only, see Register
Map 5-21)
6 CAVF0 Cavium 0 Frequency resistor set bit (read-only)
5CMULOE C_MUL Output Enable
4 P1CMUL4 These bits drive directly to the Cavium 2. The core clock speed
is the number multiplied by 50 MHz. For example, the 800 MHz
core is set to 16(0x10).
3P1CMUL3
2P1CMUL2
1P1CMUL1
0P1CMUL0
Bits: Function: Description:
7reserved
6reserved
5 JTAGOEN JTAG Output Enable
4 JTAGTCKSEL JTAG Test Clock Select changes from header to PLD as the TCK
source
3JTAGTCK JTAG Test Clock
2 JTAGTMS JTAG Test Mode Select
1JTAGTDO JTAG Test Data Output
0 JTAGTDI JTAG Test Data Input (read only)
Bits: Function: Description:
7reserved
6reserved
5 P2GPIO5OE Processor 2 GPIO5 Output Enable (enabled is the default)
Output enable is set for the TIC timer output to the Cavium
4 P2GPIO4OE Processor 2 GPIO4 Output Enable
This is an input from the Cavium to reset the MIP4
Management Processor CPLD: MPC8548 PLD Register
10009109-01 ATCA-9305 User’s Manual 5-13
Cavium GPIO Data Out
This register is the data that will be driven on the GPIO line when the Output enable is set.
Register 5-25: Cavium GPIO Data Out (0x84)
Cavium GPIO Data In
This register reads the value on the GPIO lines connected to each Cavium.
Register 5-26: Cavium GPIO Data In (0x88)
3 P2GPIO3OE Processor 2 GPIO3 Output Enable
This is an input from the Cavium to reset the MIP3
2 P1GPIO5OE Processor 1 GPIO5 Output Enable (enabled is the default)
Output enable is set for the TIC timer output to the Cavium
1 P1GPIO4OE Processor 1 GPIO4 Output Enable
This is an input from the Cavium to reset the MIP2
0 P1GPIO3OE Processor 1 GPIO3 Output Enable
This is an input from the Cavium to reset the MIP1
Bits: Function: Description:
7reserved
6reserved
5reserved
4 P2GPIO4 Set the value of the Cavium 2 GPIO bit 4
3 P2GPIO3 Set the value of the Cavium 2 GPIO bit 3
2reserved
1 P1GPIO4 Set the value of the Cavium 1 GPIO bit 4
0 P1GPIO3 Set the value of the Cavium 1 GPIO bit 3
Bits: Function: Description:
7reserved
6reserved
5reserved
4 P2GPIO4 Read the value of the Cavium 2 GPIO bit 4
3 P2GPIO3 Read the value of the Cavium 2 GPIO bit 3
2reserved
1 P1GPIO4 Read the value of the Cavium 1 GPIO bit 4
0 P1GPIO3 Read the value of the Cavium 1 GPIO bit 3
Bits: Function: Description: (continued)
Management Processor CPLD: MPC8548 PLD Register
ATCA-9305 User’s Manual 10009109-01
5-14
IPMP/IPMC GPIO Control
This register provides access (if required) to signals between the KSL CPLD and the IPMP, as
well as to signals between the KSL CPLD and the IPMC. The lower two bits can request
request the power down of a Cavium core from the sticky reset register.
Register 5-27: IPMP/IPMC GPIO Control (0x8C)
LPC Bus Control
This is the control register for the 4-bit LPC bus. It allows for communication with the IPMC
controller from the management CPU.
Register 5-28: LPC Bus (0xD0)
LPC Data
This is the data register for the 4-bit LPC bus. It allows for communication with the IPMC
controller from the management CPU. This register provides the data to be sent or received,
depending upon the commands given in the control register.
Bits: Function: Description:
7IPMC2KSL4 Input only
6IPMC2KSL3
5IPMC2KSL2
4IPMC2KSL1
3 IPMP2KSL4 Output only
2 IPMP2KSL3 Output only
1 IPMP2KSL2 Power-down signal for Cavium 2 (output)
Assert high to shut down the core. The sticky Cavium reset also
causes this to be asserted.
0 IPMP2KSL1 Power-down signal for Cavium 1 (output)
Assert high to shut down the core. The sticky Cavium reset also
causes this to be asserted.
Bits: Function: Description:
7 LPCIE LPC Interrupt Enable
6 LPCS LPC State (internal use only)
5
4
3
2 LPCIOE LPC I/O Error
1 SYNCE SYNC Error
0SYNCT SYNC Time-out
Management Processor CPLD: MPC8548 PLD Register
10009109-01 ATCA-9305 User’s Manual 5-15
Register 5-29: LPC Data (0xD4)
Serial IRQ Interrupt 1
This is interrupt register1 for the LPC bus.
Register 5-30: Serial IRQ Interrupts 1 (0xD8)
Serial IRQ Interrupt 2
This is interrupt register2 for the LPC bus.
Register 5-31: Serial IRQ Interrupts 2 (0xDC)
Bits: Function: Description:
7:0 - LPC Data
Bits: Function: Description:
7:0 - Interrupts
Bits: Function: Description:
7:0 - Interrupts
ATCA-9305 User’s Manual 10009109-01
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(blank page)
10009109-01 ATCA-9305 User’s Manual 6-1
Section 6
Ethernet Interface
The ATCA-9305 supports multiple Ethernet interfaces. This chapter describes the Broadcom
BCM56802 switch, PHYS BCM5482 and BCM5461S, Ethernet address, LEDs and connec-
tors.
BROADCOM BCM56802 SWITCH
The BCM56802 is a 16-port, 10-GbE multi-layer switch based on the StrataXGS® architec-
ture. The switch operates at 66 MHz with a 32-bit PCI bus for processor communication.
SERDES functionality includes 10-Gbps XAUI and 1-Gbps SGMII PHY interfaces.
One 10/100/1000BASE-T Ethernet (SGMII) port is routed to a front panel RJ45 connector
(see Fig. 6-1), one is routed to the MPC8548 management processor TSEC2 port, and two
are routed to the base channel backplane (see Fig. 8-2). Two 10 GbE XAUI ports connect to
the back panel via the fabric channel (see Fig. 8-2).
Two XAUI ports process packets to and from each CN5860 processor. Six 10 GbE XAUI ports
route to the optional rear transition module (RTM). See Table 8-3 and Table 8-4 for pin assign-
ments.
Note: Proprietary information on the Broadcom switch is not available in this user’s manual. Refer to their web site
for available documentation.
ETHERNET SWITCHING
The base interface Ethernet ports are provided by the Broadcom BCM56802 16-port, 10
gigabit (GbE) switch. The SerDes functionality includes 10-Gbps XAUI and 1-Gbps SGMII
PHY interfaces. The integrated SerDes complies with the CX-4 standard and PICMG 3.1
standard. The Fabric interface is compliant with PICMG 3.1 Revision 1.0, specifically link
option 9 (one 10GBASE-BX4). Switch connectivity consists of the following devices:
• Two 10GbE ports to CN5860 processor complex 1
• Two 10GbE ports to CN5860 processor complex 2
• One GbE port to the front panel (RJ45 connector)
• One GbE port to the MPC8548 management processor complex, then out the front
panel (RJ45 connector)
• Two 10 GbE ports to the fabric interface
• Two 1 GbE ports to the base interface
• Two or six 10 GbE ports to the Zone 3 connector (optional RTM)
Ethernet Interface: Ethernet Switching
ATCA-9305 User’s Manual 10009109-01
6-2
Figure 6-1: Ethernet Switching Interface Diagram
Note: The phyiscal port numbering starts at 1, as indicated in the figure. However, the software port numbering
starts at 0. Therefore, to issue a command to a port, you must subtract 1 from the port numbers shown in the
figure.
Ethernet Transceivers
The BCM5461S is a 10/100/1000BASE-T GbE Ethernet transceiver using the SGMII interface.
The BCM5482 consists of two complete 10/100/1000BASE-T GbE transceivers supporting
both voice and data simultaneously.
Ethernet Switch Ports
Table 6-1: Ethernet Switch Ports
Port: Interface: Connection:
1 SGMII 1 GB PHY to backplane BASE
2 SGMII 1 GB PHY to backplane BASE
10G - 4 PORTS
RJ45 RJ45
BCM5482
Base 10G Fabric
J23
P1 DDR2
SDRAM
BCM56802
XAUI 10 Gb
Switch Ports
5 XAUI
SGMII
2
SGMII
1
XAUI
8 7
XAUI 13
XAUI 14
3
SGMII
4
SGMII
6 XAUI
Cavium
Octeon
CN5860
Processor 2
SPI-1
SPI-0
Cavium
Octeon
CN5860
Processor 1
SPI-1
SPI-0
BCM5461S
Stratix II GX
#2
MPC8548
Management
Processor
J31
10G - 2 PORTS
J30
XAUI
11-12 15 -18
Stratix II GX
#1
Stratix II GX
#3
Stratix II GX
#4
BCM5461S BCM5461S
To Optional RTM
Ethernet Interface: MPC8548 Management Processor Ethernet
10009109-01 ATCA-9305 User’s Manual 6-3
VLAN Setup
The default VLAN configuration is defined in Table 6-2. See page 9-25 for the monitor vlan
command.
Table 6-2: VLAN Configuration
MPC8548 MANAGEMENT PROCESSOR ETHERNET ADDRESS
The Ethernet address for your board is a unique identifier on a network. The address con-
sists of 48 bits (MAC [47:0]) divided into two equal parts. The upper 24 bits define a unique
identifier that has been assigned to Emerson Network Power, Embedded Computing by
IEEE. The lower 24 bits are defined by Emerson for identification of each of our products.
The Ethernet address for the ATCA-9305 is a binary number referenced as 12 hexadecimal
digits separated into pairs, with each pair representing eight bits. The address assigned to
the ATCA-9305 has the following form:
3 SGMII 1 GB Switch PHY to front panel RJ45 connector
4 SGMII 1 GB Management processor PHYs to front panel RJ45 connector
5 XAUI 10 GB Stratix II GX bridge 2
6 XAUI 10 GB Stratix II GX bridge 1
7 XAUI 10 GB Back plane Fabric
8 XAUI 10 GB Back plane Fabric
9— not used
10 — not used
11 XAUI 10 GB BCM56802 to J30 to optional RTM
12
13 XAUI 10 GB Stratix II GX bridge 3
14 XAUI 10 GB Stratix II GX bridge 4
15 XAUI 10 GB BCM56802 to J31 to optional RTM
16
17
18
VLAN: Ports:
11, 3, 4
26, 7
38, 13
45, 11
512, 14
Port: Interface: Connection: (continued)
Ethernet Interface: MPC8548 Management Processor Ethernet
ATCA-9305 User’s Manual 10009109-01
6-4
00 80 F9 xx yy zz
00 80 F9 is Emerson’s identifier. The last three bytes of the Ethernet address consist of the
port (one byte), 0x97(port 1) or 0x98 (port 2), followed by the serial number (two byte
hexadecimal). The ATCA-9305 has been assigned the Ethernet address range
00:80:F9:97:00:00 to 00:80:F9:98:FF:FF. The format is shown in Table 6-3.
Table 6-3: Ethernet Port Address
The last two bytes, MAC[15:0], correspond to the following formula: n —1000, where n is
the unique serial number assigned to each board. So if an ATCA-9305 serial number is 1032,
the calculated value is 32 (2016), and the default Ethernet port addresses are:
• TSEC_1 MAC address is: 0x00 0x80 0xF9 0x97 0x00 0x20
• TSEC_2 MAC address is: 0x00 0x80 0xF9 0x98 0x00 0x20
Front Panel Ethernet Ports
One MPC8548 PHY (TSEC1) routes to front panel RJ45 connector, P1. The BCM56802 switch
PHY (port 3) routes to front panel RJ45 connector, P3. The Ethernet port LEDs (green or yel-
low) indicate link and activity status, see front panel Fig. 2-1.
Table 6-4: Front Panel Ethernet Ports
Offset: MAC: Description: Ethernet Identifier (hex):
Byte 5 15:0 LSB of (serial number in hex) —
Byte 4 MSB of (serial number in hex) —
Byte 3 23:16 Port 1 (TSEC_1)
Port 2 (TSEC_2)
0x97
0x98
Byte 2 47:24 Assigned to Emerson by IEEE 0xF9
Byte 1 0x80
Byte 0 0x00
Pin: P1 Signal: P3 Signal:
1TSEC1_TRD0_P FP1_TRD0_P
2TSEC1_TRD0_N FP1_TRD0_N
3TSEC1_TRD1_P FP1_TRD1_P
4TSEC1_TRD2_P FP1_TRD2_P
5TSEC1_TRD2_N FP1_TRD2_N
6 TSE1C_TRD1_N FP1_TRD1_N
7TSEC1_TRD3_P FP1_TRD3_P
8TSEC1_TRD3_N FP1_TRD3_N
9 TSEC1_ACTIVITY (green LED 1) FP1_ACTIVITY (green LED1)
10 2_5V (yellow LED 1) 2_5V (yellow LED 1)
11 TSEC1_LINKSPD1 (green LED 2) FP1_LINKSPD1 (green LED 2)
Ethernet Interface: MPC8548 Management Processor Ethernet
10009109-01 ATCA-9305 User’s Manual 6-5
12 TSEC1_LINKSPD2 (yellow LED 2) FP1_LINKSPD2 (yellow LED 2)
13 TSEC1_CHSGND FP1_CHSGND
14 TSEC1_CHSGND FP1_CHSGND
Pin: P1 Signal: P3 Signal: (continued)
ATCA-9305 User’s Manual 10009109-01
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(blank page)
10009109-01 ATCA-9305 User’s Manual 7-1
Section 7
System Management
The ATCA-9305 provides an intelligent hardware management system, as defined in the
AdvancedTCA Base Specification (PICMG® 3.0). This system implements an Intelligent Plat-
form Management Controller (IPMC) based on the BMR-H8S-AMCc® reference design from
Pigeon Point Systems. It also has an inter-integrated circuit (I2C) controller to support an
Intelligent Platform Management Bus (IPMB) that routes to the ATCA backplane.
The IPMC implements all the standard Intelligent Platform Management Interface (IPMI)
commands and provides hardware interfaces for other system management features such
as Hot Swap control, LED control, power negotiation, and temperature and voltage moni-
toring. The IPMC also supports an EIA-232 interface for serial communications via the Serial
Interface Protocol Lite (SIPL) IPMI commands.
IPMC OVERVIEW
The basic features for the IPMC implementation include:
• Conformance with AdvancedTCA Base Specification (PICMG® 3.0)
• Geographical addressing according to PICMG® 3.0
• Ability to read and write Field Replaceable Unit (FRU) data
• Ability to reset IPMC from IPMB
• Ability to read inlet and outlet airflow temperature sensors
• Ability to read payload voltage/current levels
• Ability to send event messages to a specified receiver
• All sensors generate assertion and/or de-assertion event messages
• Support for fault tolerant HPM.1 firmware upgrades
• Support for field updates of firmware via IPMB-0 or the payload interface
• Redundant boot bank capability
System Management: IPMI Messaging
ATCA-9305 User’s Manual 10009109-01
7-2
Figure 7-1: IPMC Connections Block Diagram
IPMI MESSAGING
All IPMI messages contain a Network Function Code field, which defines the category for a
particular command. Each category has two codes assigned to it–one for requests and one
for responses. The code for a request has the least significant bit of the field set to zero,
while the code for a response has the least significant bit of the field set to one. Table 7-1 lists
the network function codes (as defined in the IPMI specification) used by the IPMC.
UART
& LPC
System Management: IPMI Messaging
10009109-01 ATCA-9305 User’s Manual 7-3
Table 7-1: Network Function Codes
Hex Code
Value(s): Name: Type: Name:
00, 01 Chassis chassis device
requests/responses
00 = command/request, 01 = response:
common chassis control and status functions
02, 03 Bridge bridge
requests/responses
02 = request, 03 = response:
message contains data for bridging to the next
bus. Typically, the data is another message,
which also may be a bridging message. This
function is only present on bridge nodes.
04, 05 Sensor/
Event
sensor and event
requests/responses
04 = command/request, 05 = response:
for configuration and transmission of Event
Messages and system Sensors. This function
may be present on any node.
06, 07 App application
requests/responses
06 = command/request, 07 = response:
message is implementation-specific for a
particular device, as defined by the IPMI
specification
08, 09 Firmware firmware transfer
requests/responses
08 = command/request, 09 = response:
firmware transfer messages match the format
of application messages, as determined by the
particular device
0A, 0B Storage non-volatile
storage
requests/responses
0A = command/request, 0B = response:
may be present on any node that provides
nonvolatile storage and retrieval services
0C-2F reserved – reserved: 30 network functions (15 pairs)
30-3F OEM – 30 = command/request, 3F = response:
vendor specific: 16 network functions (8 pairs).
The vendor defines functional semantics for
cmd and data fields. The cmd field must hold the
same value in requests and responses for a
given operation to support IPMI message
handling and transport mechanisms. The
controller’s Manufacturer ID value identifies the
vendor or group.
System Management: IPMI Messaging
ATCA-9305 User’s Manual 10009109-01
7-4
IPMI Completion Codes
All IPMI response messages contain a hexadecimal Completion Code field that indicates the
status of the operation.
Table 7-2: Completion Codes
Code: Description:
Generic Completion Codes 00, C0-FF
00 Command completed normally
C0 Node busy–command could not be processed because command-processing resources
are temporarily unavailable
C1 Invalid command–indicates an unrecognized or unsupported command
C2 Command invalid for given LUN
C3 Time-out while processing command, response unavailable
C4 Out of space–command could not be completed because of a lack of storage space
required to execute the given command operation
C5 Reservation canceled or invalid Reservation ID
C6 Request data truncated
C7 Request data length invalid
C8 Request data field length limit exceeded
C9 Parameter out of range–one or more parameters in the data field of the Request are out
of range. This is different from Invalid data field code (CC) because it indicates that the
erroneous field(s) has a contiguous range of possible values.
CA Cannot return number of requested data bytes
CB Requested sensor, data, or record not present
CC Invalid data field in Request
CD Command illegal for specified sensor or record type
CE Command response could not be provided
CF Cannot execute duplicated request–for devices that cannot return the response returned
for the original instance of the request. These devices should provide separate commands
that allow the completion status of the original request to be determined. An Event
Receiver does not use this completion code, but returns the 00 completion code in the
response to (valid) duplicated requests.
D0 Command response could not be provided, SDR Repository in update mode
D1 Command response could not be provided, device in firmware update mode
D2 Command response could not be provided, Baseboard Management Controller (BMC)
initialization or initialization agent in progress
D3 Destination unavailable–cannot deliver request to selected destination. (This code can be
returned if a request message is targeted to SMS, but receive message queue reception is
disabled for the particular channel.)
D4 Cannot execute command, insufficient privilege level
D5 Cannot execute command, parameter(s) not supported in present state
FF Unspecified error
System Management: IPMB Protocol
10009109-01 ATCA-9305 User’s Manual 7-5
IPMB PROTOCOL
The IPMB message protocol is designed to be robust and support many different physical
interfaces. The IPMC supports messages over the IPMB interface. Messages are defined as
either a request or a response, as indicated by the least significant bit in the Network Func-
tion Code of the message.
Table 7-3: Format for IPMI Request Message
• The first byte contains the responder’s Slave Address, rsSA.
• The second byte contains the Network Function Code, netFn, and the responder’s
Logical Unit Number, rsLUN.
• The third byte contains the two’s-complement checksum for the first two bytes.
• The fourth byte contains the requester’s Slave Address, rqSA.
• The fifth byte contains the requester’s Sequence Number, rqSeq, and requester’s Logical
Unit Number, rqLUN. The Sequence number may be used to associate a specific response
to a specific request.
• The sixth byte contains the Command Number.
Device-Specific (OEM) Codes 01-7E
01-7E Device specific (OEM) completion codes–command-specific codes (also specific for a
particular device and version). Interpretation of these codes requires prior knowledge of
the device command set.
Command-Specific Codes 80-BE
80-BE Standard command-specific codes–reserved for command-specific completion codes
(described in this chapter)
Byte: Bits:
76543210
1rsSA
2 Network Function (netFn) rsLUN
3Checksum
4rqSA
5rqSeq
rqLUN
6Command
7:N Data
N+1 Checksum
Code: Description: (continued)
System Management: SIPL Protocol
ATCA-9305 User’s Manual 10009109-01
7-6
• The seventh byte and beyond contain parameters for specific commands (if required).
• The final byte is the two’s-complement checksum of all of the message data after the
first checksum.
An IPMI response message (see Table 7-4) is similar to an IPMI request message. The main
difference is that the seventh byte contains the Completion Code, and the eighth byte and
beyond hold data received from the controller (rather than data to send to the controller).
Also, the Slave Address and Logical Unit Number for the requester and responder are
swapped.
Table 7-4: Format for IPMI Response Message
SIPL PROTOCOL
The IPMC supports the Serial Interface Protocol Lite (SIPL) protocol. It supports raw IPMI
messages in SIPL and handles these messages the same way as it handles IPMI messages
from the IPMB-0 bus, except that the replies route to either the payload or serial debug
interface. Messages are entered as case-insensitive hex-ASCII pairs, separated optionally by
a space, as shown in the following examples:
[18 00 22]<newline>
[180022]<newline>
The IPMC does not, however, support SIPL ASCII text commands, as defined by the IPMI
specification.
The IPMC does support Pigeon Point Systems extension commands, implemented as OEM
IPMI commands. These commands use Network Function Codes 2E/2F (hex), and the mes-
sage body is transferred similarly to raw IPMI messages, as described previously.
The following figures show an example of an extension command request and response,
respectively.
Byte: Bits:
76543210
1rqSA
2 Network Function (netFn) rqLUN
3Checksum
4rsSA
5rsSeqrsLUN
6Command
7Completion Code
8:N Data
N+1 Checksum
System Management: Message Bridging
10009109-01 ATCA-9305 User’s Manual 7-7
Figure 7-2: Extension Command Request Example
Figure 7-3: Extension Command Response Example
MESSAGE BRIDGING
The Message Bridging facility is responsible for bridging messages between various inter-
faces of the ATCA-9305 IPMI. The message bridging is implemented via the standard Send
Message command.
The ATCA-9305 IPMC also supports message bridging between the Payload Interface and
IPMB-0, which allows the payload to send custom messages to and receive them from other
shelf entities, such as the shelf manager. Message bridging is implemented using the
Send/Get Message commands and also via LUN 10 of the ATCA-9305 IPMC.
[B8 00 01 0A 40 00 12]
Command Code
rqSeq (00
16
) / Bridge (00
2
)
NetFn Code (2E
16
) / LUN (00
2
)
Pigeon Point IANA
Data
[B8 00 01 0A 40 00 12]
Command Code
rqSeq (0016) / Bridge (002)
NetFn Code (2E16) / LUN (002)
Pigeon Point IANA
Data
[BC 00 01 00 0A 40 00 34]
Command Code
rqSeq (0016) / Bridge (002)
NetFn Code (2F16) / LUN (002)
Pigeon Point IANA
Data
Completion Code
System Management: Message Bridging
ATCA-9305 User’s Manual 10009109-01
7-8
The following example illustrates how the Send/Get Message and Get Address Info com-
mands can be used by the payload software to get the physical location of the board in the
shelf:
1The payload software sends the Get Address Info command to the BMR-H8S-AMCc,
requesting address information for FRU device 0. Using the SIPL protocol:
[B0 xx 01 00]
2The BMR-H8S-AMCc returns its IPMB address in the Get Address Info reply. In this example,
7216 is the IPMB-0 address of the IPMC.
{B4 00 01 00 00 FF 72 FF 00 01 07]
3The payload software composes a Get Address Info command requesting the responder to
provide its addressing information for FRU device 0. The request is composed in the IPMB
format. The responder address is set to 2016 (for the shelf manager). The requester address
is set to the value obtained in the previous step.
{20 B0 30 72 00 01 00 8D]
4The payload software forwards the command composed in the previous step to the shelf
manager using the Send Message command. The Send/Get Message in SIPL format is:
[18 xx 34 40 20 B0 30 72 00 01 00 8D]
5The BMR-H8S-AMCc firmware sends the Get Address Info request to the shelf manager,
waits for a reply to this request, and sends this reply to the payload software in the Send/Get
Message response.
[1C 00 34 00 72 B4 DA 20 00 01 00 00 41 82 FF 00 FF 00 1E]
6The payload software extracts the Get Address info reply from the Send/Get Message
response and retrieves the physical address of the board from it.
The second message bridging implementation, bridging via LUN 10, allows the payload to
receive responses to requests sent to IPMB-0 via the Send Message command with request
tracking disabled, as well as receive requests from IPMB-0. To provide this functionality, the
ATCA-9305 IPMC places all messages coming to LUN 10 from IPMB-0 in a dedicated Receive
Message Queue, and those messages are processed by the payload instead of the IPMC
firmware. To read messages from the Receive Message Queue, the payload software uses
the standard Get Message command. The payload software is notified about messages
coming to LUN 10 via the Get Status command of the SIPL protocol and the payload notifi-
cation mechanism, or, if the LPC/KCS-based Payload Interface is used, using the KCS inter-
rupt. The Receive Message Queue of the ATCA-9305 IPMC is limited to 128 bytes, which is
sufficient for storing at least three IPMB messages, but may be not enough for a larger num-
ber of messages. Taking this into account, the payload software must read messages from
the queue as fast as possible, caching them on the on-carrier payload side for further han-
System Management: Standard Commands
10009109-01 ATCA-9305 User’s Manual 7-9
dling, if it is necessary. If the Receive Message Queue is full, the ATCA-9305 IPMC rejects all
requests coming to LUN 10 with the C0h (Node Busy) completion code and discards all
responses coming to this LUN.
STANDARD COMMANDS
The Intelligent Peripheral Management Controller (IPMC) supports standard IPMI com-
mands to query board information and to control the behavior of the board. These com-
mands provide a means to:
• identify the controller
• reset the controller
• return the controller’s self-test results
• read and write the controller’s SROMs
• read the temperature, voltage, and watchdog sensors
• get specific information, such as thresholds, for each sensor
• read and write the Field Replaceable Unit (FRU) data
• reserve and read the Sensor Data Record (SDR) repository
• configure event broadcasts
• bridge an IPMI request to the public IPMB and return the response
Table 7-5 lists the IPMI commands supported by the IPMC along with the hexadecimal values
for each command’s Network Function Code (netFn), Logical Unit Number (LUN), and Com-
mand Code (Cmd):
Table 7-5: IPMC IPMI Commands
Command: netFn: LUN: Cmd:
Set System Boot Options Chassis 01, 01 07
Get System Boot Options Chassis 01, 01 08
Set Event Receiver Sensor/Event 04, 05 00
Get Event Receiver Sensor/Event 04, 05 01
Platform Event (Event Message) Sensor/Event 04, 05 02
Get Device SDR Information Sensor/Event 04, 05 20
Get Device SDR Sensor/Event 04, 05 21
Reserve Device SDR Repository Sensor/Event 04, 05 22
Get Sensor Reading Factors Sensor/Event 04, 05 23
Set Sensor Hysteresis Sensor/Event 04, 05 24
Get Sensor Hysteresis Sensor/Event 04, 05 25
System Management: Standard Commands
ATCA-9305 User’s Manual 10009109-01
7-10
Set Sensor Thresholds Sensor/Event 04, 05 26
Get Sensor Thresholds Sensor/Event 04, 05 27
Set Sensor Event Enable Sensor/Event 04, 05 28
Get Sensor Event Enable Sensor/Event 04, 05 29
Rearm Sensor Events Sensor/Event 04, 05 2A
Get Sensor Event Status Sensor/Event 04, 05 2B
Get Sensor Reading Sensor/Event 04, 05 2D
Set Sensor Type Sensor/Event 04, 05 2E
Get Sensor Type Sensor/Event 04, 05 2F
Get Device ID Application 06, 07 01
Broadcast 'Get Device ID' Application 06, 07 01
Cold Reset Application 06, 07 02
Warm Reset Application 06, 07 03
Get Self Test Results Application 06, 07 04
Get Device GUID Application 06, 07 08
Reset Watchdog Timer Application 06, 07 22
Set Watchdog Timer Application 06, 07 24
Get Watchdog Timer Application 06, 07 25
Send Message Application 06, 07 34
Get FRU Inventory Area Info Storage 0A, 0B 10
Read FRU Data Storage 0A, 0B 11
Write FRU Data Storage 0A, 0B 12
Get PICMG Properties PICMG 2C, 2D 00
Get Address Info PICMG 2C, 2D 01
FRU Control PICMG 2C, 2D 04
Get FRU LED Properties PICMG 2C, 2D 05
Get LED Color Capabilities PICMG 2C, 2D 06
Set FRU LED State PICMG 2C, 2D 07
Get FRU LED State PICMG 2C, 2D 08
Set IPMB State PICMG 2C, 2D 09
Set FRU Activation Policy PICMG 2C, 2D 0A
Get FRU Activation Policy PICMG 2C, 2D 0B
Set FRU Activation PICMG 2C, 2D 0C
Get Device Locator Record ID PICMG 2C, 2D 0D
Set Port State PICMG 2C, 2D 0E
Get Port State PICMG 2C, 2D 0F
Compute Power Properties PICMG 2C, 2D 10
Set Power Level PICMG 2C, 2D 11
Command: (continued) netFn: LUN: Cmd:
System Management: OEM Boot Options
10009109-01 ATCA-9305 User’s Manual 7-11
The IPMC implements many standard IPMI commands. For example, software can use the
watchdog timer commands to monitor the system’s health. Normally, the software resets
the watchdog timer periodically to prevent it from expiring. The IPMI specification allows
for different actions such as reset, power off, and power cycle, to occur if the timer expires.
The watchdog’s ‘timer use’ fields can keep track of which software (Operating System, Sys-
tem Management, etc.) started the timer. Also, the time-out action and ‘timer use’ infor-
mation can be logged automatically to the System Event Log (SEL) when the time-out
occurs. Refer to the IPMI specification (listed in Table 1-2) for details about each command’s
request and response data. The IPMC also implements ATCA commands, see the ATCA Base
Specification (PICMG 3.0).
OEM BOOT OPTIONS
The Set System Boot Options and Get System Boot Options commands provide a means to
set/retrieve the boot options. The IPMI specification defines a set of standard boot option
parameters. In addition, the specification includes a range of numbers (96-127) for OEM
extensions. Emerson utilizes this area for OEM function extensions, such as boot bank selec-
tion and POST configuration. The following table describes these extensions:
Table 7-6: Emerson Boot Option Parameters
Get Power Level PICMG 2C, 2D 12
Bused Resource
(Release, Query, Force, Bus Free)
PICMG 2C, 2D 17
Parameter: # Parameter Data:
Boot Bank
(non-volatile)
96 data 1 — Set Selector. This is the processor ID for which the
boot option is to be set.
data 2 — Boot Bank Selector. This parameter is used to
indicate the boot bank from which the payload will boot.
00h = Primary (i.e., default) Boot Bank is selected.
01h = Secondary Boot Bank is selected.
02h-FFh = unused
POST Type
(non-volatile)
97 data 1 — Set Selector. This is the processor ID for which the
boot option is to be set.
data 2 — PSOT Type Selector. This parameter is used to
specify the POST type that the payload boot firmware will
execute.
00h = Short POST
01h = Long POST
02h-FFh = unused
Command: (continued) netFn: LUN: Cmd:
System Management: IPMC Watchdog Timer Commands
ATCA-9305 User’s Manual 10009109-01
7-12
IPMC WATCHDOG TIMER COMMANDS
The IPMC implements a standardized ‘Watchdog Timer’ that can be used for a number of
system time-out functions by System Management Software (SMS) or by the monitor. Set-
ting a time-out value of zero allows the selected time-out action to occur immediately. This
provides a standardized means for devices on the IPMB to perform emergency recovery
actions.
Table 7-7: IPMC Watchdog Timer Commands
Watchdog Timer Actions
The following actions are available on expiration of the Watchdog Timer:
•System Reset
•System Power Off
The System Reset and System Power Off on time-out selections are mutually exclusive. The
watchdog timer is stopped whenever the system is powered down. A command must be
sent to start the timer after the system powers up.
Watchdog Timer Use Field and Expiration Flags
The watchdog timer provides a ‘timer use’ field that indicates the current use assigned to
the watchdog timer. The watchdog timer provides a corresponding set of ‘timer use expira-
tion’ flags that are used to track the type of time-out(s) that had occurred.
The time-out use expiration flags retain their state across system resets and power cycles, as
long as the IPMC remains powered. The flags are normally cleared solely by the Set Watch-
dog Timer command; with the exception of the “don’t log” flag, which is cleared after every
system hard reset or timer time-out.
The Timer Use fields indicate:
Monitor FRB-2 Time-out:
A Fault-resilient Booting, level 2 (FRB-2) time-out has occurred. This indicates that the last
system reset or power cycle was due to the system time-out during POST, presumed to be
caused by a failure or hang related to the bootstrap processor.
Command: See Page: Optional/Mandatory:
Reset Watchdog Timer 7-14 M
Set Watchdog Timer 7-14 M
Get Watchdog Timer 7-16 M
System Management: IPMC Watchdog Timer Commands
10009109-01 ATCA-9305 User’s Manual 7-13
Monitor POST Time-out:
In this mode, the time-out occurred while the watchdog timer was being used by the moni-
tor for some purpose other than FRB-2 or OS Load Watchdog.
OS Load Time-out: The last reset or power cycle was caused by the timer being used to ‘watchdog’ the interval
from ‘boot’ to OS up and running. This mode requires system management software, or OS
support. The monitor should clear this flag if it starts this timer during POST.
SMS ‘OS Watchdog’ Time-out:
This indicates that the timer was being used by System Management Software (SMS). Dur-
ing run-time, SMS starts the timer, then periodically resets it to keep it from expiring. This
periodic action serves as a ‘heartbeat’ that indicates that the OS (or at least the SMS task) is
still functioning. If SMS hangs, the timer expires and the IPMC generates a system reset.
When SMS enables the timer, it should make sure the ‘SMS’ bit is set to indicate that the
timer is being used in its ‘OS Watchdog’ role.
OEM: This indicates that the timer was being used for an OEM-specific function.
Using the Timer Use Field and Expiration Flags
The software that sets the Timer Use field is responsible for managing the associated Timer
Use Expiration flag. For example, if System Management Software (SMS) sets the timer use
to “SMS/OS Watchdog,” then that same SMS is responsible for acting on and clearing the
associated Timer Use Expiration flag.
In addition, software should only interpret or manage the expiration flags for watchdog
timer uses that it set. For example, the monitor should not report watchdog timer expira-
tions or clear the expiration flags for non-monitor uses of the timer. This is to allow the soft-
ware that did set the Timer Use to see that a matching expiration occurred.
Watchdog Timer Event Logging
By default, the IPMC will automatically log the corresponding sensor-specific watchdog sen-
sor event when a timer expiration occurs. A “don’t log” bit is provided to temporarily disable
the automatic logging. The “don’t log” bit is automatically cleared (logging re-enabled)
whenever a timer expiration occurs.
Monitor Support for Watchdog Timer
If a system “Warm Reset” occurs, the watchdog timer may still be running while the moni-
tor executes POST. Therefore, the monitor should take steps to stop or restart the watchdog
timer early in POST. Otherwise, the timer may expire later during POST or after the OS has
booted.
System Management: IPMC Watchdog Timer Commands
ATCA-9305 User’s Manual 10009109-01
7-14
Reset Watchdog Timer Command
The Reset Watchdog Timer command is used for starting and restarting the Watchdog
Timer from the initial countdown value that was specified in the Set Watchdog Timer com-
mand.
If a pretime-out interrupt has been configured, the Reset Watchdog Timer command will
not restart the timer once the pretime-out interval has been reached. The only way to stop
the timer once it has reached this point is via the Set Watchdog Timer command.
Table 7-8: Reset Watchdog Timer Command
Set Watchdog Timer Command
The Set Watchdog Timer command is used for initializing and configuring the watchdog
timer. The command is also used for stopping the timer.
If the timer is already running, the Set Watchdog Timer command stops the timer (unless
the “don’t stop” bit is set) and clears the Watchdog pretime-out interrupt flag (see Get Mes-
sage Flags command in the IPMI specification v1.5). IPMC hard resets, system hard resets,
and the Cold Reset command also stop the timer and clear the flag.
Byte 1: This selects the timer use and configures whether an event will be logged on expiration.
Byte 2: This selects the time-out action and pretime-out interrupt type.
Byte 3: This sets the pretime-out interval. If the interval is set to zero, the pretime-out action occurs
concurrently with the time-out action.
Byte 4: This clears the Timer Use Expiration flags. A bit set in byte 4 of this command clears the cor-
responding bit in byte 5 of the Get Watchdog Timer command.
Bytes 5 and 6: These hold the least significant and most significant bytes, respectfully, of the countdown
value. The Watchdog Timer decrement is one count/100 ms. The counter expires when the
count reaches zero. If the counter is loaded with zero and the Reset Watchdog command is
issued to start the timer, the associated timer events occur immediately.
Type: Byte: Data Field:
Request Data — —
Response Data 1 Completion Code
System Management: IPMC Watchdog Timer Commands
10009109-01 ATCA-9305 User’s Manual 7-15
Table 7-9: Set Watchdog Timer Command
Type: Byte: Data Field:
Request Data 1 Timer Use
[7] 1b=don’t log
[6] 1b=the don’t stop timer on Set Watchdog Timer command
(new for IPMI v1.5) new parameters take effect
immediately. If timer is already running, countdown value
will get set to given value and countdown will continue
from that point. If timer is already stopped, it will remain
stopped. If the pretime-out interrupt bit is set, it will get
cleared.1
0b=timer stops automatically when Set Watchdog Timer
command is received
[5:3] reserved
[2:0] timer use (logged on expiration when “don’t log” bit = 0b)
000b=reserved
001b=Monitor FRB-2
010b=Monitor/POST
011b=OS Load
100b=SMS/OS
101b=OEM
110b-111b=reserved
2Timer Actions
[7] reserved
[6:4] pretime-out interrupt (logged on expiration when “don’t
log” bit = 0b)
000b=none
001b=SMI
010b=NMI/Diagnostic Interrupt
011b=Messaging Interrupt (this is the same interrupt as
allocated to the messaging interface)
100b, 111b =reserved
[3] reserved
[2:0] time-out action
000b=no action
001b=Hard Reset
010b=Power Down
011b=Power Cycle
100b, 111b=reserved
3 Pretime-out interval in seconds, ‘1’ based
System Management: IPMC Watchdog Timer Commands
ATCA-9305 User’s Manual 10009109-01
7-16
1. Potential race conditions exist with implementation of this option. If the Set Watchdog Timer command is
sent just before a pretime-out interrupt or time-out is set to occur, the time-out could occur before the
command is executed. To avoid this condition, it is recommended that software set this value no closer
than three counts before the pretime-out or time-out value is reached.
Get Watchdog Timer Command
This command retrieves the current settings and present countdown of the watchdog
timer. The Timer Use Expiration flags in byte 5 retain their states across system resets and
system power cycles. With the exception of bit 6 in the Timer Use byte, the Timer Use Expi-
ration flags are cleared using the Set Watchdog Timer command. They may also become
cleared because of a loss of IPMC power, firmware update, or other cause of IPMC hard
reset. Bit 6 of the Timer Use byte is automatically cleared to 0b whenever the timer times
out, is stopped when the system is powered down, enters a sleep state, or is reset.
Table 7-10: Get Watchdog Timer Command
Request Data
(continued)
4 Timer Use Expiration flags clear
(0b=leave alone, 1b=clear timer use expiration bit)
[7] reserved
[6] reserved
[5] OEM
[4] SMS/OS
[3] OS Load
[2] Monitor/POST
[1] Monitor FRB-2
[0] reserved
5 Initial countdown value, lsbyte (100 ms/count)
6 Initial countdown value, msbyte
Response Data 1 Completion Code
Type: Byte: Data Field:
Request Data — —
Response Data 1 Completion Code
Type: Byte: Data Field: (continued)
System Management: IPMC Watchdog Timer Commands
10009109-01 ATCA-9305 User’s Manual 7-17
Response Data2Timer Use
[7] 1b=don’t log
[6] 1b=timer is started (running)
0b=timer is stopped
[5:3] reserved
[2:0] timer use (logged on expiration if “don’t log” bit = 0)
000b=reserved
001b=Monitor FRB-2
010b=Monitor/POST
011b=OS Load
100b=SMS/OS
101b=OEM
110b, 111b=reserved
3Timer Actions
[7] reserved
[6:4] pretime-out interrupt
000b=none
001b=SMI
010b=NMI/Diagnostic Interrupt
011b=Messaging Interrupt (this would be the same interrupt
as allocated to the messaging interface)
100b, 111b =reserved
[3] reserved
[2:0] time-out action
000b=no action
001b=Hard Reset
010b=Power Down
011b=Power Cycle
100b, 111b=reserved
4 Pretime-out interval in seconds, ‘1’based
5 Timer Use Expiration flags (1b=timer expired while associated ‘use’
was selected)
[7] reserved
[6] reserved
[5] OEM
[4] SMS/OS
[3] OS Load
[2] Monitor/POST
[1] Monitor FRB-2
[0] reserved
6 Initial countdown value, lsbyte (100 ms/count)
7 Initial countdown, msbyte
Type: Byte: Data Field: (continued)
System Management: FRU LEDs
ATCA-9305 User’s Manual 10009109-01
7-18
FRU LEDS
This section describes the front panel LEDs controlled by the IPMC and documents how to
control each LED with the standard FRU LED commands. Reference the PICMG® 3.0 Revision
2.0 AdvancedTCA® Base Specification for more detailed information.
The ATCA-9305 has four Light-Emitting Diodes (LEDs) on the front panel. See Fig. 2-1 for
their location.
Table 7-11: FRU LEDs
Response Data 8 Present countdown value, lsbyte. The initial countdown value and
present countdown values should match immediately after the
countdown is initialized via a Set Watchdog Timer command and
after a Reset Watchdog Timer has been executed.
Note that internal delays in the IPMC may require software to delay
up to 100 ms before seeing the countdown value change and be
reflected in the Get Watchdog Timer command.
9 Present countdown value, msbyte
LEDs:
ID
(hex):
Reference
Designator: Description:
Hot
Swap
00 CR57 The blue Hot Swap LED displays four states:
On—the board can be safely extracted
Off—the board is operating and not safe for
extraction,
Long blink—insertion is in progress
Short blink—requesting permission for
extraction
OOS 01 CR54 The Out Of Service programmable LED
controlled by the IPMI controller is either red
(North America) or amber (Europe). When lit,
this LED indicates the ATCA-9305 is in a failed
state.
2 02 CR55 The green LED is user defined, but frequently is
used as an In Service indicator. When used as an
In Service indicator, a lit LED indicates that the
ATCA-9305 is functioning properly.
3 03 CR56 The amber LED is user defined.
Type: Byte: Data Field: (continued)
System Management: FRU LEDs
10009109-01 ATCA-9305 User’s Manual 7-19
Get FRU LED Properties Command
This command allows software to determine which LEDs are under IPMC control.
Table 7-12: Get FRU LED Properties Command
Get LED Color Capabilities Command
LED 1 can be either red or amber, this command is used to determine the valid color prior to
issuing a Set FRU LED State command.
Table 7-13: Get LED Color Capabilities Command
Type: Byte: Data Field:
Request Data 1 PICMG Identifier—indicates that this is a PICMG defined group
extension command. Use value 00h.
2 FRU Device ID
Response Data 1 Completion Code
2 PICMG Identifier—indicates that this is a PICMG defined group
extension command. Use value 00h.
3 General Status LED Properties—indicates the FRU’s ability to control
the four general status LEDs. When a bit is set, the FRU can control
the associated LED.
Bits [7:4] reserved, set to 0
Bit [3] LED3
Bit [2] LED2
Bit [1] LED1
Bit [0] Blue LED
4 Application Specific LED Count—is the number of application
specific LEDs under IPMC control.
00h-FBh Number of application-specific LEDs under IPMC
control. If none are present, this field is 00h.
FCh-FFh reserved
Type: Byte: Data Field:
Request Data 1 PICMG Identifier—indicates that this is a PICMG defined group
extension command. Use value 00h.
2 FRU Device ID
3LED ID
FFh reserved
System Management: FRU LEDs
ATCA-9305 User’s Manual 10009109-01
7-20
Response Data 1 Completion Code
CCh If the LED ID contained in the Request data is not present
on the FRU
2 PICMG Identifier—indicates that this is a PICMG defined group
extension command. Use value 00h.
3 LED Color Capabilities—when a bit is set, the LED supports the
color.
Bit [7] reserved, set to 0
Bit [6] LED supports white
Bit [5] LED supports orange
Bit [4] LED supports amber
Bit [3] LED supports green
Bit [2] LED supports red
Bit [1] LED supports blue
Bit [0] reserved, set to 0
4 Default LED Color in Local Control State
Bit [7] reserved, set to 0
Bits [3:0]
0h reserved
1h Blue
2h Red
3h Green
4h Amber
5h Orange
6h White
7h-Fh reserved
5 Default LED Color in Override State
Bit [7] reserved, set to 0
Bits [3:0]
0h reserved
1h Blue
2h Red
3h Green
4h Amber
5h Orange
6h White
7h-Fh reserved
Type: Byte: Data Field: (continued)
System Management: FRU LEDs
10009109-01 ATCA-9305 User’s Manual 7-21
Set FRU LED State Command
The Set FRU LED State command allows the state of the FRU LEDs to be controlled by the
management system.
Table 7-14: Set FRU LED State Command
Type: Byte: Data Field:
Request Data 1 PICMG Identifier—indicates that this is a PICMG defined group
extension command. Use value 00h.
2 FRU Device ID
3LED ID
00h Blue LED (Hot Swap)
01h LED 1 (OOS)
02h LED 2
03h LED 3
04h-FEh OEM defined LEDs
FFh Lamp Test (all LEDs under management control are
addressed)
4 LED Function
00h LED off override
01h-FAh LED blinking override
FBh Lamp Test state Turn on LED specified in byte 3 for the
duration specified in byte 5, then return to the highest
priority state.
FCh LED state restored to Local Control state
FDh-FEh reserved
FFh LED on override
5On Duration
LED on-time is measured in tens of milliseconds
Lamp Test time in hundreds of milliseconds if byte 4=FBh, time
value must be less than 128. Other values when Byte 4=FBh are
reserved. Otherwise, this field is ignored and shall be set to 0h.
System Management: FRU LEDs
ATCA-9305 User’s Manual 10009109-01
7-22
Get FRU LED State Command
The Get FRU LED State command allows the state of the FRU LEDs to be controlled by the
management system.
Table 7-15: Get FRU LED State Command
Request Data 6 Color When Illuminated—sets the override color when LED Function
is 01h-FAh and FFh. This byte sets the Local Control color when LED
Function is FCh. This byte may be ignored during Lamp Test or may
be used to control the color during the lamp test when LED
Function is FBh.
Bits [7:4] reserved, set to 0
Bits [3:0]
0h reserved
1h Use Blue
2h Use Red
3h Use Green
4h Use Amber
5h Use Orange
6h Use White
7h-Dh reserved
Eh Do not change
Fh Use default color
Response Data 1 Completion Code
2 PICMG Identifier—indicates that this is a PICMG defined group
extension command. Use value 00h.
Type: Byte: Data Field:
Request Data 1 PICMG Identifier—indicates that this is a PICMG defined group
extension command. Use value 00h.
2 FRU Device ID
3LED ID
00h Blue LED (Hot Swap)
01h LED 1 (OOS)
02h LED 2
03h LED 3
04h-FEh OEM defined LEDs
FFh reserved
Response Data 1 Completion Code
2 PICMG Identifier—indicates that this is a PICMG defined group
extension command. Use value 00h.
Type: Byte: Data Field: (continued)
System Management: FRU LEDs
10009109-01 ATCA-9305 User’s Manual 7-23
Response Data 3 LED States
Bits [7:3] reserved, set to 0
Bit [2] 1b if Lamp Test has been enabled
Bit [1] 1b if override state has been enabled
Bit [2] 1b if IPMC has a Local control state
4 Local Control LED Function
00h LED is off (default if Local Control not supported)
01h-FAh LED is blinking Off duration specified by this byte,
on duration specified by byte 5 (in tens of
milliseconds)
FBh-FEh reserved
FFh LED is on
5On Duration
LED on-time is measured in tens of milliseconds
Lamp Test time in hundreds of milliseconds if byte 4=FBh, time
value must be less than 128. Other values when Byte 4=FBh are
reserved. Otherwise, this field is ignored and shall be set to 0h.
6 Local Control Color
Bits [7:4] reserved, set to 0
Bits [3:0]
0h reserved
1h Blue
2h Red
3h Green
4h Amber
5h Orange
6h White
7h-Fh reserved
7 Override State LED Function—is required if either override state or
Lamp Test is in effect.
00h LED override state is off
01h-FAh LED override state is blinking Off duration is
specified by this byte, on duration specified by
byte 8 (in tens of milliseconds)
FBh-FEh reserved
FFh LED override state is on
8 Override State On Duration—is required if either override state or
Lamp Test is in effect (in tens of milliseconds).
Type: Byte: Data Field: (continued)
System Management: Vendor Commands
ATCA-9305 User’s Manual 10009109-01
7-24
VENDOR COMMANDS
The IPMC supports additional IPMI commands that are specific to Pigeon Point and/or
Emerson. This section provides detailed descriptions of those extension or SIPL commands.
Table 7-16: Vendor Command Summary
Response Data 9 Override State Color
Bits [7:4] reserved, set to 0
Bits [3:0]
0h reserved
1h Blue
2h Red
3h Green
4h Amber
5h Orange
6h White
7h-Fh reserved
10 Lamp Test Duration—is optional if Lamp Test is not in effect
(hundreds of milliseconds).
Command: netFn: LUN: Cmd:
Get Status OEM 2E, 2F 00
Get Serial Interface Properties OEM 2E, 2F 01
Set Serial Interface Properties OEM 2E, 2F 02
Get Debug Level OEM 2E, 2F 03
Set Debug Level OEM 2E, 2F 04
Get Hardware Address OEM 2E, 2F 05
Set Hardware Address OEM 2E, 2F 06
Get Handle Switch OEM 2E, 2F 07
Set Handle Switch OEM 2E, 2F 08
Get Payload Communication Time-Out OEM 2E, 2F 09
Set Payload Communication Time-Out OEM 2E, 2F 0A
Enable Payload Control OEM 2E, 2F 0B
Disable Payload Control OEM 2E, 2F 0C
Reset IPMC OEM 2E, 2F 0D
Hang IPMC OEM 2E, 2F 0E
Bused Resource Control OEM 2E, 2F 0F
Bused Resource Status OEM 2E, 2F 10
Graceful Reset OEM 2E, 2F 11
Diagnostic Interrupt Results OEM 2E, 2F 12
Get Payload Shutdown Time-Out OEM 2E, 2F 15
Set Payload Shutdown Time-Out OEM 2E, 2F 16
Type: Byte: Data Field: (continued)
System Management: Vendor Commands
10009109-01 ATCA-9305 User’s Manual 7-25
Get Status
The IPMC firmware notifies the payload about changes of all status bits except for bits 0-2
by sending an unprintable character (ASCII 07, BELL) over the Payload Interface. The pay-
load is expected to use the Get Status command to identify pending events and other SIPL
commands to provide a response (if necessary). The event notification character is sent in a
synchronous manner, and does not appear in the contents of SIPL messages sent to the pay-
load.
Table 7-17: Get Status Command
Set Local FRU LED State OEM 2E, 2F 18
Get Local FRU LED State OEM 2E, 2F 19
Update Discrete Sensor OEM 2E, 2F 1A
Update Threshold Sensor OEM 2E, 2F 1B
Reserved for Message Listeners OEM 30, 31 10
Add Message Listener OEM 30, 31 11
Remove Message Listener OEM 30, 31 12
Get Message Listener List OEM 30, 31 13
Update Firmware Progress Sensor OEM 30, 31 F0
Type: Byte: Data Field:
Request Data 1:3 PPS IANA Private Enterprise ID, MS Byte first
0x00400A = 16394 (Pigeon Point Systems)
Response Data 1 Completion Code
2:4 PPS IANA Private Enterprise ID, MS Byte first
0x00400A = 16394 (Pigeon Point Systems)
Command: (continued) netFn: LUN: Cmd:
System Management: Vendor Commands
ATCA-9305 User’s Manual 10009109-01
7-26
Response Data 5 Bit [7] Graceful Reboot Request
If set to 1, indicates that the payload is requested to initiate the
graceful reboot sequence
Bit [6] Diagnostic Interrupt Request
If set to 1, indicates that a payload diagnostic interrupt request
has arrived
Bit [5] Shutdown Alert
If set to 1, indicates that the payload is going to be shutdown
Bit [4] Reset Alert
If set to 1, indicates that the payload is going to be reset
Bit [3] Sensor Alert
If set to 1, indicates that at least one of the IPMC sensors detects
threshold crossing
Bits [2:1] Mode
The current IPMC modes are defined as:
0Normal
1Standalone
2 Manual Standalone
Bit [0] Control
If set to 0, the IPMC control over the payload is disabled
6 Bits [4:7] Metallic Bus 2 Events
These bits indicate pending Metallic Bus 2 requests arrived from
the carrier controller:
0 Metallic Bus 2 Query
1 Metallic Bus 2 Release
2 Metallic Bus 2 Force
3 Metallic Bus 2 Free
Bits [0:3] Metallic Bus 1 Events
These bits indicate pending Metallic Bus 1 requests arrived from
the carrier controller:
0 Metallic Bus 1 Query
1 Metallic Bus 1 Release
2 Metallic Bus 1 Force
3 Metallic Bus 1 Free
Type: Byte: Data Field: (continued)
System Management: Vendor Commands
10009109-01 ATCA-9305 User’s Manual 7-27
Get Serial Interface Properties
The Get Serial Interface Properties command is used to get the properties of a particular
serial interface.
Table 7-18: Get Serial Interface Properties Command
Response Data 7 Bits [4:7] Clock Bus 2 Events
These bits indicate pending Clock Bus 2 requests arrived from
the carrier controller:
0Clock Bus 2 Query
1 Clock Bus 2 Release
2Clock Bus 2 Force
3Clock Bus 2 Free
Bits [0:3] Clock Bus 1 Events
These bits indicate pending Clock Bus 1 requests arrived from
the carrier controller:
0Clock Bus 1 Query
1 Clock Bus 1 Release
2Clock Bus 1 Force
3Clock Bus 1 Free
8 Bits [4:7] reserved
Bits [0:3] Clock Bus 3 Events
These bits indicate pending Clock Bus 3 requests arrived from
the carrier controller:
0Clock Bus 3 Query
1 Clock Bus 3 Release
2Clock Bus 3 Force
3Clock Bus 3 Free
Type: Byte: Data Field:
Request Data 1:3 PPS IANA Private Enterprise ID, MS Byte first
0x00400A = 16394 (Pigeon Point Systems)
4Interface ID
0Serial Debug Interface
1 Payload Interface
Response Data 1 Completion Code
2:4 PPS IANA Private Enterprise ID, MS Byte first
0x00400A = 16394 (Pigeon Point Systems)
Type: Byte: Data Field: (continued)
System Management: Vendor Commands
ATCA-9305 User’s Manual 10009109-01
7-28
Set Serial Interface Properties
The Set Serial Interface Properties command is used to set the properties of a particular
serial interface.
Table 7-19: Set Serial Interface Properties Command
Response Data 5 Bit [7] Echo On
If this bit is set, the IPMC enables echo for the given serial
interface
Bits [6:4] reserved
Bits [3:0] Baud Rate ID
The baud rate ID defines the interface baud rate as follows:
0 9600 bps
1 19200 bps
2 38400 bps
3 57600 bps (unsupported)
4 115200 bps (unsupported)
Type: Byte: Data Field:
Request Data 1:3 PPS IANA Private Enterprise ID, MS Byte first
0x00400A = 16394 (Pigeon Point Systems)
4Interface ID
0Serial Debug Interface
1 Payload Interface
5 Bit [7] Echo On
If this bit is set, the IPMC enables echo for the given serial
interface
Bits [6:4] reserved
Bits [3:0] Baud Rate ID
The baud rate ID defines the interface baud rate as follows:
0 9600 bps
1 19200 bps
2 38400 bps
3 57600 bps (unsupported)
4 115200 bps (unsupported)
Response Data 1 Completion Code
2:4 PPS IANA Private Enterprise ID, MS Byte first
0x00400A = 16394 (Pigeon Point Systems)
Type: Byte: Data Field: (continued)
System Management: Vendor Commands
10009109-01 ATCA-9305 User’s Manual 7-29
Get Debug Level
The Get Debug Level command gets the current debug level of the IPMC firmware.
Table 7-20: Get Debug Level Command
Set Debug Level
The Set Debug Level command sets the current debug level of the IPMC firmware.
Table 7-21: Set Debug Level Command
Type: Byte: Data Field:
Request Data 1:3 PPS IANA Private Enterprise ID, MS Byte first
0x00400A = 16394 (Pigeon Point Systems)
Response Data 1 Completion Code
2:4 PPS IANA Private Enterprise ID, MS Byte first
0x00400A = 16394 (Pigeon Point Systems)
5 Bits [7:5] reserved
Bit [4] IPMB Dump Enable
If set to 1, the IPMC provides a trace of IPMB messages that are
arriving to/going from the IPMC via IPMB-0 or IPMB -L
Bit [3] Payload Logging Enable
If set to 1, the IPMC provides a trace of SIPL activity on the
Payload interface onto the Serial Debug interface
Bit [2] Alert Logging Enable
If set to 1, the IPMC outputs important alert messages onto the
Serial Debug interface
Bit [1] Low-level Error Logging Enable
If set to 1, the IPMC outputs low-level error/diagnostic messages
onto the Serial Debug interface
Bit [0] Error Logging Enable
If set to 1, the IPMC outputs error/diagnostic messages onto the
Serial Debug interface
Type: Byte: Data Field:
Request Data 1:3 PPS IANA Private Enterprise ID, MS Byte first
0x00400A = 16394 (Pigeon Point Systems)
System Management: Vendor Commands
ATCA-9305 User’s Manual 10009109-01
7-30
Get Hardware Address
The Get Hardware Address command reads the hardware address of the IPMC.
Table 7-22: Get Hardware Address Command
Set Hardware Address
The Set Hardware Address command allows overriding of the hardware address read from
hardware when the IPMC operates in (Manual) Standalone mode.
Table 7-23: Set Hardware Address Command
Request Data 4 Bits [7:5] reserved
Bit [4] IPMB Dump Enable
If set to 1, the IPMC provides a trace of IPMB messages that are
arriving to/going from the IPMC via IPMB-0 or IPMB-L
Bit [3] Payload Logging Enable
If set to 1, the IPMC provides a trace of SIPL activity on the
Payload interface onto the Serial Debug interface
Bit [2] Alert Logging Enable
If set to 1, the IPMC outputs important alert messages onto the
Serial Debug interface
Bit [1] Low-level Error Logging Enable
If set to 1, the IPMC outputs low-level error/diagnostic
messages onto the Serial Debug interface
Bit [0] Error Logging Enable
If set to 1, the IPMC outputs error/diagnostic messages onto the
Serial Debug interface
Response Data 1 Completion Code
2:4 PPS IANA Private Enterprise ID, MS Byte first
0x00400A = 16394 (Pigeon Point Systems)
Type: Byte: Data Field:
Request Data 1:3 PPS IANA Private Enterprise ID, MS Byte first
0x00400A = 16394 (Pigeon Point Systems)
Response Data 1 Completion Code
2:4 PPS IANA Private Enterprise ID, MS Byte first
0x00400A = 16394 (Pigeon Point Systems)
5 Hardware Address
Type: Byte: Data Field:
Request Data 1:3 PPS IANA Private Enterprise ID, MS Byte first
0x00400A = 16394 (Pigeon Point Systems)
Type: Byte: Data Field: (continued)
System Management: Vendor Commands
10009109-01 ATCA-9305 User’s Manual 7-31
Get Handle Switch
The Get Handle Switch command reads the state of the Hot Swap handle of the IPMC. Over-
riding of the handle switch state is allowed only if the IPMC operates in (Manual) Standalone
mode.
Table 7-24: Get Handle Switch Command
Set Handle Switch
The Set Handle Switch command sets the state of the Hot Swap handle switch in (Manual)
Standalone mode.
Table 7-25: Set Handle Switch Command
4 Hardware Address
If set to 00, the ability to override the hardware address is
disabled
NOTE: A hardware address change only takes effect after an
IPMC reset. See “Reset IPMC” on page 7-33.
Response Data 1 Completion Code
2:4 PPS IANA Private Enterprise ID, MS Byte first
0x00400A = 16394 (Pigeon Point Systems)
Type: Byte: Data Field:
Request Data 1:3 PPS IANA Private Enterprise ID, MS Byte first
0x00400A = 16394 (Pigeon Point Systems)
Response Data 1 Completion Code
2:4 PPS IANA Private Enterprise ID, MS Byte first
0x00400A = 16394 (Pigeon Point Systems)
5 Handle Switch Status
0x00 The handle switch is open
0x01 The handle switch is closed
0x02 The handle switch state is read from hardware
Type: Byte: Data Field:
Request Data 1:3 PPS IANA Private Enterprise ID, MS Byte first
0x00400A = 16394 (Pigeon Point Systems)
4 Handle Switch Status
0x00 The handle switch is open
0x01 The handle switch is closed
0x02 The handle switch state is read from hardware
Response Data 1 Completion Code
2:4 PPS IANA Private Enterprise ID, MS Byte first
0x00400A = 16394 (Pigeon Point Systems)
Type: Byte: Data Field: (continued)
System Management: Vendor Commands
ATCA-9305 User’s Manual 10009109-01
7-32
Get Payload Communication Time-Out
The Get Payload Communication Time-Out command reads the payload communication
time-out value.
Table 7-26: Get Payload Communication Time-Out Command
Set Payload Communication Time-Out
The Set Payload Communication Time-Out command sets the payload communication
time-out value.
Table 7-27: Set Payload Communication Time-Out Command
Enable Payload Control
The Enable Payload Control command enables payload control from the Serial Debug inter-
face.
Table 7-28: Enable Payload Control Command
Type: Byte: Data Field:
Request Data 1:3 PPS IANA Private Enterprise ID, MS Byte first
0x00400A = 16394 (Pigeon Point Systems)
Response Data 1 Completion Code
2:4 PPS IANA Private Enterprise ID, MS Byte first
0x00400A = 16394 (Pigeon Point Systems)
5Payload Time-out
Payload communication time-out measured in hundreds of
milliseconds. Thus, the payload communication time-out
may vary from 0.1 to 25.5 seconds.
Type: Byte: Data Field:
Request Data 1:3 PPS IANA Private Enterprise ID, MS Byte first
0x00400A = 16394 (Pigeon Point Systems)
4Payload Time-out
Payload communication time-out measured in hundreds of
milliseconds. Thus, the payload communication time-out
may vary from 0.1 to 25.5 seconds.
Response Data 1 Completion Code
2:4 PPS IANA Private Enterprise ID, MS Byte first
0x00400A = 16394 (Pigeon Point Systems)
Type: Byte: Data Field:
Request Data 1:3 PPS IANA Private Enterprise ID, MS Byte first
0x00400A = 16394 (Pigeon Point Systems)
Response Data 1 Completion Code
2:4 PPS IANA Private Enterprise ID, MS Byte first
0x00400A = 16394 (Pigeon Point Systems)
System Management: Vendor Commands
10009109-01 ATCA-9305 User’s Manual 7-33
Disable Payload Control
The Disable Payload Control command disables payload control from the Serial Debug
interface.
Table 7-29: Disable Payload Control Command
Reset IPMC
The Reset IPMC command allows the payload to reset the IPMC over the SIPL.
Table 7-30: Reset IPMC Command
Hang IPMC
The IPMC provides a means to test the watchdog timer support by implementing the Hang
IPMC command, which simulates firmware hanging by entering an endless loop.
Table 7-31: Hang IPMC Command
Type: Byte: Data Field:
Request Data 1:3 PPS IANA Private Enterprise ID, MS Byte first
0x00400A = 16394 (Pigeon Point Systems)
Response Data 1 Completion Code
2:4 PPS IANA Private Enterprise ID, MS Byte first
0x00400A = 16394 (Pigeon Point Systems)
Type: Byte: Data Field:
Request Data 1:3 PPS IANA Private Enterprise ID, MS Byte first
0x00400A = 16394 (Pigeon Point Systems)
4 Reset Type Code
0x00 Cold IPMC reset to the current mode
0x01 Cold IPMC reset to the Normal mode
0x02 Cold IPMC reset to the Standalone mode
0x03 Cold IPMC reset to the Manual Standalone mode
0x04 Reset the IPMC and enter Upgrade mode
Response Data 1 Completion Code
2:4 PPS IANA Private Enterprise ID, MS Byte first
0x00400A = 16394 (Pigeon Point Systems)
Type: Byte: Data Field:
Request Data 1:3 PPS IANA Private Enterprise ID, MS Byte first
0x00400A = 16394 (Pigeon Point Systems)
Response Data 1 Completion Code
2:4 PPS IANA Private Enterprise ID, MS Byte first
0x00400A = 16394 (Pigeon Point Systems)
System Management: Vendor Commands
ATCA-9305 User’s Manual 10009109-01
7-34
Bused Resource
To send a Bused Resource command to the carrier controller, the payload uses the Bused
Resource command of the SIPL.
Table 7-32: Bused Resource Command
Bused Resource Status
If the IPMC receives a Bused Resource command from IPMB-0, it asserts an appropriate
event and notifies the payload which uses the Bused Resource Status command over the
SIPL. When the IPMC receives a Bused Resource Status command, the respective bit in the
IPMC status is cleared.
The payload must issue a Bused Resource Status command before the payload communica-
tion time-out time. If the payload does not issue such a command before the payload com-
munication time-out time, the IPMC sends the 0xC3 completion code (Time-Out) in the
appropriate Bused Resource command reply.
Type: Byte: Data Field:
Request Data 1:3 PPS IANA Private Enterprise ID, MS Byte first
0x00400A = 16394 (Pigeon Point Systems)
4 Command Types for Carrier Controller to Board
0 Query if board has control of the bus
1 Release requests a board to release control of the bus
2 Force board to release control of bus immediately
3 Bus Free informs board that the bus is available
Command Types for Board to Carrier Controller
0 Request to seize control of the bus
1 Relinquish control of the bus, carrier controller can reassign
control of bus
2 Notify carrier controller that control of the bused resource has
been transferred to this board from another authorized board
5Bused Resource ID
0 Metallic Test Bus pair #1
1 Metallic Test Bus pair #2
2 Synch clock group 1 (CLK1A and CLK1B pairs)
3 Synch clock group 2 (CLK2A and CLK2B pairs)
3 Synch clock group 3 (CLK3A and CLK3B pairs)
Response Data 1 Completion Code
2:4 PPS IANA Private Enterprise ID, MS Byte first
0x00400A = 16394 (Pigeon Point Systems)
5Status
0 Ack; carrier controller acknowledges that board has control
1 Error; same as Ack, but carrier controller believes board should
not have been given control of the resource (optional)
2 Deny; carrier controller denies control of resource by the board
System Management: Vendor Commands
10009109-01 ATCA-9305 User’s Manual 7-35
Table 7-33: Bused Resource Status Command
Graceful Reset
The IPMC supports the Graceful Reboot option of the FRU Control command. On receiving
such a command, the IPMC sets the Graceful Reboot Request bit of the IPMC status, sends a
status update notification to the payload, and waits for the Graceful Reset command from
the payload. If the IPMC receives such a command before the payload communication time-
out time, it sends the 0x00 completion code (Success) to the carrier controller. Otherwise
the 0xC3 completion code (Time-Out) is sent.
Type: Byte: Data Field:
Request Data 1:3 PPS IANA Private Enterprise ID, MS Byte first
0x00400A = 16394 (Pigeon Point Systems)
4 Command Types for Carrier Controller to Board
0 Query if board has control of the bus
(0=In control, 1= No control)
1 Release request a board to release control of the bus
(0=Ack, 1=Refused, 2=No control)
2 Force board to release control of bus immediately
(0=Ack, 1=No control)
3 Bus Free informs board that the bus is available
(0=Accept, 1=Not needed)
Command Types for Board to Carrier Controller
0 Request to seize control of the bus
(0=Grant, 1=Busy, 2=Defer, 3=Deny)
1 Relinquish control of the bus, carrier controller can reassign
control of bus (0=Ack, 1=Error)
2 Notify carrier controller that control of the bused resource has
been transferred to this board from another authorized board
(0=Ack, 1=Error, 2=Deny)
5Bused Resource ID
0 Metallic Test Bus pair #1
1 Metallic Test Bus pair #2
2 Synch clock group 1 (CLK1A and CLK1B pairs)
3 Synch clock group 2 (CLK2A and CLK2B pairs)
4 Synch clock group 3 (CLK3A and CLK3B pairs)
6Status
0 Ack; carrier controller acknowledges that board has control
1 Error; same as Ack, but carrier controller believes board should
not have been given control of the resource (optional)
2 Deny; carrier controller denies control of resource by the board
Response Data 1 Completion Code
2:4 PPS IANA Private Enterprise ID, MS Byte first
0x00400A = 16394 (Pigeon Point Systems)
System Management: Vendor Commands
ATCA-9305 User’s Manual 10009109-01
7-36
The IPMC does not reset the payload on receiving the Graceful Reset command or time-out.
If the IPMC participation is necessary, the payload must request the IPMC to perform a pay-
load reset. The Graceful Reset command is also used to notify the IPMC about the comple-
tion of the payload shutdown sequence.
Table 7-34: Graceful Reset Command
Diagnostic Interrupt Results
The IPMC supports the Issue Diagnostic Interrupt feature of the FRU Control command. The
payload is notified about a diagnostic interrupt over the SIPL. The payload is expected to
return diagnostic interrupt results before the payload communication time-out using the
Diagnostic Interrupt Results command of the SIPL.
Table 7-35: Diagnostic Interrupt Command
Get Payload Shutdown Time-Out
When the carrier controller commands the IPMC to shut down the payload (i.e. sends the
Set Power Level (0) command), the IPMC notifies the payload by asserting an appropriate
alert and sending an alert notification to the payload. Upon receiving this notification, the
payload software is expected to initiate the payload shutdown sequence. After performing
this sequence, the payload should send the Graceful Reset command to the IPMC over the
Payload interface to notify the IPMC that the payload shutdown is complete.
Type: Byte: Data Field:
Request Data 1:3 PPS IANA Private Enterprise ID, MS Byte first
0x00400A = 16394 (Pigeon Point Systems)
Response Data 1 Completion Code
2:4 PPS IANA Private Enterprise ID, MS Byte first
0x00400A = 16394 (Pigeon Point Systems)
Type: Byte: Data Field:
Request Data 1:3 PPS IANA Private Enterprise ID, MS Byte first
0x00400A = 16394 (Pigeon Point Systems)
4 If the payload responds before the payload communication
time-out, the diagnostic interrupt return code is forwarded to the
carrier controller as the completion code of the FRU Control
command response. Otherwise, the 0xC3 completion code (Time-
Out) is returned.
Response Data 1 Completion Code
2:4 PPS IANA Private Enterprise ID, MS Byte first
0x00400A = 16394 (Pigeon Point Systems)
System Management: Vendor Commands
10009109-01 ATCA-9305 User’s Manual 7-37
To avoid deadlocks that may occur if the payload software does not respond, the IPMC pro-
vides a special time-out for the payload shutdown sequence. If the payload does not send
the Graceful Reset command within a definite period of time, the IPMC assumes that the
payload shutdown sequence is finished, and sends a Module Quiesced Hot Swap event to
the ATCA-9305 controller.
Table 7-36: Get Payload Shutdown Time-Out Command
Set Payload Shutdown Time-Out
The Set Payload Shutdown Time-Out command is defined as follows:
Table 7-37: Set Payload Shutdown Time-Out Command
Type: Byte: Data Field:
Request Data 1:3 PPS IANA Private Enterprise ID, MS Byte first
0x00400A = 16394 (Pigeon Point Systems)
Response Data 1 Completion Code
2:4 PPS IANA Private Enterprise ID, MS Byte first
0x00400A = 16394 (Pigeon Point Systems)
5:6 Time-Out measured in hundreds of milliseconds, LSB first
Type: Byte: Data Field:
Request Data 1:3 PPS IANA Private Enterprise ID, MS Byte first
0x00400A = 16394 (Pigeon Point Systems)
4:5 Time-Out measured in hundreds of milliseconds, LSB first
Response Data 1 Completion Code
2:4 PPS IANA Private Enterprise ID, MS Byte first
0x00400A = 16394 (Pigeon Point Systems)
System Management: Vendor Commands
ATCA-9305 User’s Manual 10009109-01
7-38
Set Local FRU LED State
The Set Local FRU LED State command is used to change the local state of a FRU LED.
Table 7-38: Set Local FRU LED State Command
Type: Byte: Data Field:
Request Data 1:3 PPS IANA Private Enterprise ID, MS Byte first
0x00400A = 16394 (Pigeon Point Systems)
4 FRU Device ID
5LED ID
00h Blue LED (Hot Swap)
01h LED 1 (OOS)
02h LED 2
03h LED 3
04h-FEh OEM defined LEDs
FFh Lamp Test (all LEDs under management control are
addressed)
6 LED Function
00h LED off override
01h-FAh LED blinking override
FBh Lamp Test state Turn on LED specified in byte 3 for the
duration specified in byte 5, then return to the highest
priority state.
FCh LED state restored to Local Control state
FDh-FEh reserved
FFh LED on override
7On Duration
LED on-time is measured in tens of milliseconds
Lamp Test time in hundreds of milliseconds if byte 4=FBh, time
value must be less than 128. Other values when Byte 4=FBh are
reserved. Otherwise, this field is ignored and shall be set to 0h.
8 Color parameter specifies the color of the LED in the local state for
multi-color LEDs
9 If the off-first flag parameter is 0, the on part of the blink cycle of
the LED precedes the off part of the cycle. Otherwise, the off part
of the blink cycle precedes the on part of the cycle.
Response Data 1 Completion Code
2:4 PPS IANA Private Enterprise ID, MS Byte first
0x00400A = 16394 (Pigeon Point Systems)
System Management: Vendor Commands
10009109-01 ATCA-9305 User’s Manual 7-39
Get Local FRU LED State
The Get Local FRU LED State command is used to read the local state of a FRU LED.
Table 7-39: Get Local FRU LED State Command
Type: Byte: Data Field:
Request Data 1:3 PPS IANA Private Enterprise ID, MS Byte first
0x00400A = 16394 (Pigeon Point Systems)
4 FRU Device ID
5LED ID
00h Blue LED (Hot Swap)
01h LED 1 (OOS)
02h LED 2
03h LED 3
04h-FEh OEM defined LEDs
FFh reserved (all LEDs under management control are
addressed)
Response Data 1 Completion Code
2:4 PPS IANA Private Enterprise ID, MS Byte first
0x00400A = 16394 (Pigeon Point Systems)
5 Local Control LED Function
00h LED is off (default if Local Control not supported)
01h-FAh LED is blinking Off duration specified by this byte,
on duration specified by byte 5 (in tens of
milliseconds)
FBh-FEh reserved
FFh LED is on
6 Local Control On Duration
LED on-time is measured in tens of milliseconds
Lamp Test time in hundreds of milliseconds if byte 4=FBh, time
value must be less than 128. Other values when Byte 4=FBh are
reserved. Otherwise, this field is ignored and shall be set to 0h.
7 Color parameter specifies the color of the LED in the local state for
multi-color LEDs
8 If the off-first flag parameter is 0, the on part of the blink cycle of
the LED precedes the off part of the cycle. Otherwise, the off part
of the blink cycle precedes the on part of the cycle.
System Management: Vendor Commands
ATCA-9305 User’s Manual 10009109-01
7-40
Update Discrete Sensor
The Update Discrete Sensor command is used to change the state of a discrete sensor con-
trolled by the payload.
Table 7-40: Update Discrete Sensor Command
Update Threshold Sensor
The Update Threshold Sensor command is used to change the state of a threshold sensor
controlled by the payload.
Table 7-41: Update Threshold Sensor Command
Type: Byte: Data Field:
Request Data 1:3 PPS IANA Private Enterprise ID, MS Byte first
0x00400A = 16394 (Pigeon Point Systems)
4 Sensor ID identifies the payload-controlled discrete sensor that has
to be updated
5Update flags
0 0=sensor initialization is complete
1=sensor is in the initial update state
1:2 reserved, set to 0
3 0=globally disable events from the sensor
1=leave the global event enable bit intact
4 0=globally enable events from the sensor
1=leave the global event enable bit intact
5 0=globally disable sensor scanning
1=leave the global scanning enable bit intact
6 0=globally enable sensor scanning
1=leave the global scanning enable bit intact
7 reserved, set to 0
6:7 New status LSB and new status MSB are the least and most
significant bytes of the new sensor state
Response Data 1 Completion Code
2:4 PPS IANA Private Enterprise ID, MS Byte first
0x00400A = 16394 (Pigeon Point Systems)
Type: Byte: Data Field:
Request Data 1:3 PPS IANA Private Enterprise ID, MS Byte first
0x00400A = 16394 (Pigeon Point Systems)
4 Sensor ID parameter identifies the payload-controlled threshold
sensor that has to be updated
System Management: Boot Device Redirection (BDR)
10009109-01 ATCA-9305 User’s Manual 7-41
BOOT DEVICE REDIRECTION (BDR)
The IPMC enables the ATCA-9305 to recover from monitor corruption by booting from a
redundant copy in another flash device. The mechanism relies on an IPMC software internal
watchdog to expire when corrupted code fails to reset the timer. This watchdog begins
counting down as soon as the payload is power cycled or reset. If the timer expires (approxi-
mately 30 seconds), the boot redirection will activate and the board will reset. Following
this automatic reset, IPMC will attempt to boot from the next flash device according to
Fig. 7-4. This sequence will continue until a valid boot image clears the watchdog.
The boot redirection order is configurable via the bootdev command (see page 9-17). If a
shunt is present on J9 [1:2}, the ATCA-9305 boots from socket. When forcing boot from the
socket, use bootdev and reset from the command line to test boot from a flash device. If
shunt is not installed on J9 [1:2], the ATCA-9305 follows the default boot redirection shown
in Fig. 7-4. Also reference the“Boot Device Redirection” register.
Note: The System Management IPMC can override the BDFR and swap the flash banks (from 1 to 2, or 2 to 1).
Request Data 5 Update flags
0 0=sensor initialization is complete
1=sensor is in the initial update state
1:2 reserved, set to 0
3 0=globally disable events from the sensor
1=leave the global event enable bit intact
4 0=globally enable events from the sensor
1=leave the global event enable bit intact
5 0=globally disable sensor scanning
1=leave the global scanning enable bit intact
6 0=globally enable sensor scanning
1=leave the global scanning enable bit intact
7 reserved, set to 0
6 New raw reading of the sensor
Response Data 1 Completion Code
2:4 PPS IANA Private Enterprise ID, MS Byte first
0x00400A = 16394 (Pigeon Point Systems)
Type: Byte: Data Field: (continued)
System Management: Boot Device Redirection (BDR)
ATCA-9305 User’s Manual 10009109-01
7-42
Figure 7-4: Boot Device Diagram
Note: The Boot Device Redirection mechanism is disabled when booting from the 512 KB socketed flash.
Figure 7-5: Boot Redirection Control Diagram
Initial boot attempt is from
ATCA-9305 soldered
flash bank 1
Boot device is 512
KB socketed flash
BDR Watchdog
disabled
512 KB socketed
flash installed on
ATCA-9305?
Yes
No
Jumper J11 [1:2]
shunt installed?
Yes
No
Secondary boot
attempt is from ATCA-
9305 soldered
flash bank 2
Yes
Flash bank 1
fail?
Yes
Flash bank 2
fail?
No
Boot from
flash bank 1
No
Boot from
flash bank 2
Management
Controller
Payload Reset
Force Boot Socket
I2C Port
Expander
Monitor Booted
Power Good
Payload Reset Indication
Private I2C
Boot Select [ ]
Payload Reset Indication Clear
Payload
System Management: Message Listeners
10009109-01 ATCA-9305 User’s Manual 7-43
Management Controller:
The controller provides a signals to reset the payload.
Payload: This provides signals to the controller indicating when the payload has reset for any reason,
that the payload is powered, and that the payload has finished its monitor booting
sequence. By default, a powered payload enables the watchdog and disables when the pay-
load is not powered.
I2C Port Expander: The I2C port expander provides signals to the payload to define the boot device selection
(boot select [1 and 2]) and to clear the payload reset indication. The I2C port expander com-
municates with the controller via a private I2C.
Payload Reset: This signal is used by the management controller to reset the payload.
Monitor Booted: This signal indicates to the management controller that a valid monitor image has finished
booting and the watchdog can be disabled.
Power Good: This signal indicates to the management controller that the payload is powered. When pay-
load power is applied, the BMC watchdog will start.
Force Boot Socket: If a shunt is present on J9 [1:2], the controller sets the boot location to socket flash with this
signal.
Payload Reset Indication:
When reset, this signal is held high by the payload until it is cleared by the IPMC using the
payload reset indication clear signal.
Boot Select [ ]: These signals select the boot device.
Payload Reset Indication Clear:
This signal clears the payload reset indication.
MESSAGE LISTENERS
Payload port dynamic control can be implemented via message listeners. The payload can
add itself as a message listener to any message destined for the IPMC target either over
IPMB-0 or the payload serial interface. When the IPMC receives a subscribed message, the
IPMC firmware copies the message into the payload’s LUN-10 Receive Message Queue and
notifies the payload via an unprintable character (ASCII 07, BELL). The payload receives the
message as described in “Message Bridging.” The message listener list is only eight entries
long. The payload can add/remove/get list at any time.
Note: The message listener list is not persistent across IPMC reboots.
System Management: Message Listeners
ATCA-9305 User’s Manual 10009109-01
7-44
Add Message Listener
The Add Message Listener command adds a specified Network Function and Command to
the Message Listener List. The command returns completion code (0x00) and IANA. If this
command does not complete successfully (e.g., due to a full list), it returns 0xCD and IANA.
Table 7-42: Add Message Listener Command
Remove Message Listener
The Remove Message Listener command removes a specified Network Function and Com-
mand from the Message Listener List. The command returns completion code (0x00) and
IANA. If this command does not complete successfully (e.g., if the Network Function and
Command are not in the list), it returns 0xCD and IANA.
Table 7-43: Remove Message Listener Command
Type: Byte: Data Field:
Request Data 1:3 Emerson Network Power, Embedded Computing Inc. IANA Private
Enterprise ID
0x0065CD = 26061 (Emerson Network Power, Embedded
Computing Inc.)
LSB Byte first:byte 1 = CD, byte 2 = 65, byte 3 = 00
4 Network function to add
5Command to add
Response Data 1 Completion Code
2:4 Emerson Network Power, Embedded Computing Inc. IANA Private
Enterprise ID
0x0065CD = 26061 (Emerson Network Power, Embedded
Computing Inc.)
LSB Byte first:byte 2 = CD, byte 3 = 65, byte 4 = 00
Type: Byte: Data Field:
Request Data 1:3 Emerson Network Power, Embedded Computing Inc. IANA Private
Enterprise ID
0x0065CD = 26061 (Emerson Network Power, Embedded
Computing Inc.)
LSB Byte first:byte 1 = CD, byte 2 = 65, byte 3 = 00
4 Network function to remove
5Command to remove
Response Data 1 Completion Code
2:4 Emerson Network Power, Embedded Computing Inc. IANA Private
Enterprise ID
0x0065CD = 26061 (Emerson Network Power, Embedded
Computing Inc.)
LSB Byte first:byte 2 = CD, byte 3 = 65, byte 4 = 00
System Management: System Firmware Progress Sensor
10009109-01 ATCA-9305 User’s Manual 7-45
Get Message Listener List
The Get Message Listener List command returns the entire list of subscribed Message Lis-
teners. The command returns completion code (0x00) and IANA.
Table 7-44: Get Message Listener List Command
SYSTEM FIRMWARE PROGRESS SENSOR
The Update System Firmware Progress Sensor command sets the values for the Firmware
Progress Sensor using sensor codes from the IPMI Intelligent Platform Management Inter-
face Specification, specifically (System Firmware Progress” within Table 42-3 in Section 42.2
“Sensor Type Codes and Data.”
Type: Byte: Data Field:
Request Data 1:3 Emerson Network Power, Embedded Computing Inc. IANA Private
Enterprise ID
0x0065CD = 26061 (Emerson Network Power, Embedded
Computing Inc.)
LSB Byte first:byte 1 = CD, byte 2 = 65, byte 3 = 00
Response Data 1 Completion Code
2:4 Emerson Network Power, Embedded Computing Inc. IANA Private
Enterprise ID
0x0065CD = 26061 (Emerson Network Power, Embedded
Computing Inc.)
LSB Byte first:byte 2 = CD, byte 3 = 65, byte 4 = 00
5 Network function for listener 0
6 Command for listener 0
7 Network function for listener 1
8 Command for listener 1
9 Network function for listener 2
10 Command for listener 2
11 Network function for listener 3
12 Command for listener 3
13 Network function for listener 4
14 Command for listener 4
15 Network function for listener 5
16 Command for listener 5
17 Network function for listener 6
18 Command for listener 6
19 Network function for listener 7
20 Command for listener 7
System Management: Entities and Entity Associations
ATCA-9305 User’s Manual 10009109-01
7-46
The command returns 0xC0 when the IPMC is busy and will retry until the command is suc-
cessful. If this command returns 0xCC, the sensor ID is invalid. There is only one sensor on
the board, so the sensor ID should always be “0”. When updated, the shelf manager is noti-
fied.
Table 7-45: Update System Firmware Progress Sensor Command
ENTITIES AND ENTITY ASSOCIATIONS
The AdvancedTCA specification (see PICMG Engineering Change Notice 3.0 listed in Table 1-2)
uses Entity IDs and Instances to describe physical components associated with FRUs.
Device-relative Entities are unique to a specific IPMC and are referenced as follows in the
specification:
r(<ipmb>,<lun>,<Entity ID>,<Entity Instance - 60>)
Using this terminology, a ATCA-9305 installed in Logical Slot 1 has the following description
in Fig. 7-6.
Type: Byte: Data Field:
Request Data 1:3 Emerson Network Power, Embedded Computing Inc. IANA Private
Enterprise ID
0x0065CD = 26061 (Emerson Network Power, Embedded
Computing Inc.)
LSB Byte first:byte 1 = CD, byte 2 = 65, byte 3 = 00
40 (The sensor ID)
5Flags: reserved to 0
6 Offset in specification Valid offsets: 0, 1, 2
7 Event Data 2; content to be added into the second byte of event data
per the IPMI specification
Response Data 1 Completion Code
2:4 Emerson Network Power, Embedded Computing Inc. IANA Private
Enterprise ID
0x0065CD = 26061 (Emerson Network Power, Embedded
Computing Inc.)
LSB Byte first:byte 2 = CD, byte 3 = 65, byte 4 = 00
System Management: Entities and Entity Associations
10009109-01 ATCA-9305 User’s Manual 7-47
Figure 7-6: IPMB Entity Structure
FRU 0 r(82, 0, A0, 0)
Inflow Temp
Outflow Temp
Hot Swap
IPMB Physical
BMC Watchdog
F/W Progress
SDRAM POST
IIC Bus POST
Flash POST
EthSwitch POST
Version change
Async Pld Rst
Payload Power
r(82, 0, 03, 0) - Cavium 1
Cavium 1 Temp
Cav1 SDRAM POST
Cav1 IIC POST
Cav1 Boot
r(82, 0, 03, 1) - Cavium 2
Cavium 2 Temp
Cav2 SDRAM POST
Cav2 IIC POST
Cav2 Boot
r(82, 0, 14, 0) - Power Module
-48V
-48V Curr
-48V Src A
-48V Src B
+3.3V Mgmt
+12V Payload
+12V Curr
FRU 1 r(82, 0, C0, 1) RTM
RTM Hot Swap
System Management: Sensors and Sensor Data Records
ATCA-9305 User’s Manual 10009109-01
7-48
SENSORS AND SENSOR DATA RECORDS
The ATCA-9305 implements a number of sensors as described in the following tables. All
values are hexadecimal.
Table 7-46: IPMI Threshold Sensors
Table 7-47: IPMI Discrete Sensors
Name:
Sensor
Type:
Event Reading
Type:
Enity
ID:
Entity
Instance:
Event
Gen:
Inflow Temp Temperature = 01 Threshold = 01 0xA0 0x60 Yes
Outflow Temp Temperature = 01 Threshold = 01 0xA0 0x60 Yes
Cavium 1 Temp Temperature = 01 Threshold = 01 0x03 0x60 Yes
Cavium 2 Temp Temperature = 01 Threshold = 01 0x03 0x61 Yes
-48V Voltage = 02 Threshold = 01 0x14 0x60 Yes
-48V Curr Current = 03 Threshold = 01 0x14 0x60 Yes
-48V Src A Voltage = 02 Threshold = 01 0x14 0x60 Yes
-48V Src B Voltage = 02 Threshold = 01 0x14 0x60 Yes
+3.3V Mgmt Voltage = 02 Threshold = 01 0x14 0x60 Yes
+12V Payload Voltage = 02 Threshold = 01 0x14 0x60 Yes
+12V Curr Current = 03 Threshold = 01 0x14 0x60 Yes
Name:
Sensor
Type:
Event Reading
Type:
Enity
ID:
Entity
Instance:
Event
Gen:
Hot Swap Hot Swap = F0 Sensor specific
discrete = 6F
0xA0 0x60 Yes
RTM Hot Swap Hot Swap = F0 Sensor specific
discrete = 6F
0xC0 0x61 Yes
IPMB Physical IPMB Link = F1 Sensor specific
discrete = 6F
0xA0 0x60 Yes
BMC Watchdog Watchdog2 = 23 Sensor specific
discrete = 6F
0xA0 0x60 Yes
F/W Progress System Firmware
Progress = 0F
Sensor specific
discrete = 6F
0xA0 0x60 Yes
SDRAM POST Memory = 0C Sensor specific
discrete = 6F
0xA0 0x60 Yes
IIC Bus POST Processor = 07 Predictive-failure
Discrete = 04
0xA0 0x60 Yes
Flash POST Memory = 0C Sensor specific
discrete = 6F
0xA0 0x60 Yes
EthSwitch POST Chip Set Predictive-failure
Discrete = 04
0xA0 0x60 Yes
Cav1 SDRAM
POST
Memory = 0C Sensor specific
discrete = 6F
0x03 0x60 Yes
System Management: Sensors and Sensor Data Records
10009109-01 ATCA-9305 User’s Manual 7-49
The IPMC implements a Device Sensor Data Record (SDR) Repository that contains SDRs for
the IPMC, the FRU device, and each sensor. A system management controller may use the
Get Device SDR command to read the repository and dynamically discover the capabilities
of the board. Refer to the IPMI specification (listed in Table 1-2) for more information on
using Sensor Data Records and the Device SDR Repository.
Under certain circumstances, some sensors connected to the IPMC can generate Event Mes-
sages for the system management controller. To enable these messages, the system man-
agement controller must send a Set Event Receiver command to the IPMC, along with the
address of the Event Receiver. Table 7-48 shows the format of an Event Message:
Table 7-48: Event Message Format
Cav1 IIC POST Processor = 07 Predictive-failure
Discrete = 04
0x03 0x60 Yes
Cav1 Boot Processor = 07 Predictive-failure
Discrete = 04
0x03 0x60 Yes
Cav2 SDRAM
POST
Memory = 0C Sensor specific
discrete = 6F
0x03 0x61 Yes
Cav2 IIC POST Processor = 07 Predictive-failure
Discrete = 04
0x03 0x61 Yes
Cav2 Boot Processor = 07 Predictive-failure
Discrete = 04
0x03 0x61 Yes
Version change Version Change Sensor specific
discrete = 6F
0xA0 0x60 Yes
Async Pld Rst Power Supply = 08 Digital Discrete
= 03
0xA0 0x60 Yes
Payload Power Power Supply = 08 Digital Discrete
= 03
0xA0 0x60 Yes
Byte:1Field: Description:
0 RsSA Responder’s Slave Address (Address of Event Receiver)
1 NetFn/RsLUN Net Function Code (0x04) in upper 6 bits; Responder’s LUN in lower 2
bits
2 Chk 1 Checksum #1
3 RqSA Requester’s Slave Address (Address of our board on IPMB)
4 RqSeq/RqLUN Request Sequence number in upper 6 bits; Requester’s LUN in lower 2
bits
5 Cmd Command (Always 0x02 for event message)
6 EvMRev Event Message Revision (0x04 for IPMI 1.5)
7 Sensor Type Indicates event class or type of sensor that generated the message
8 Sensor Number A unique number indicating the sensor that generated the message
Name:
Sensor
Type:
Event Reading
Type:
Enity
ID:
Entity
Instance:
Event
Gen:
System Management: FRU Inventory
ATCA-9305 User’s Manual 10009109-01
7-50
Event-generating sensors with a Threshold Event/Reading Type (0x01) initiate an event mes-
sage when a sensor reading crosses the defined threshold. The default thresholds for a par-
ticular sensor are retrieved by sending the IPMC a Get Sensor Thresholds command. The
system management controller must send the IPMC a Get Sensor Reading command to
retrieve the current sensor reading. Refer to the IPMI specification listed in Table 1-2 for com-
plete details on using these commands.
FRU INVENTORY
The IPMC stores Field Replaceable Unit (FRU) information in its boot memory (SROM). The
data structure contains information such as the product name, part number, serial number,
manufacturing date, and E-keying information. Refer to the IPMI specification for complete
details on the FRU data structure. Table 7-49 lists the general contents of the ATCA-9305’s
FRU information:
Table 7-49: FRU Definition
9Event Dir/Event
Type
Upper bit indicates direction (0 = Assert, 1= Deassert); Lower 7 bits
indicate type of threshold crossing or state transition
10 Event Data 0 Data for sensor and event type
11 Event Data 1 (Optional) Data for sensor and event type
12 Event Data 2 (Optional) Data for sensor and event type
13 Chk2 Checksum #2
1. Each byte has eight bits.
Item: Description:
Common Header
Version Version number of the overall FRU data structure defined by the IPMI
FRU specification
Internal Use Area
Version Version number of the Internal Use Area data structure defined by
the IPMI FRU specification
Internal Use Size 0x100 bytes are allocated for customer use in this area
Board Information Area
Version Version number of the Board Information Area data structure
defined by the IPMI FRU specification
Language Code 0x01 = English
Manufacturing Date/Time Variable, expressed as the number of minutes since 12:00 AM on
January 1, 1996
Board Manufacturer “Emerson”
Board Product Name “ATCA-9305”
Byte:1Field: Description: (continued)
System Management: E-Keying
10009109-01 ATCA-9305 User’s Manual 7-51
E-KEYING
This section details the interfaces governed by E-keying and the protocols they support.
Specifically, this includes the interfaces implemented by this product and the E-keying defi-
nition that corresponds to each interface.
The IPMC supports E-keying for the ATCA-9305 per PICMG® ATCA 3.0, Revision 2.0 and
PICMG 3.1, Revision 1.0 specifications The E-keying information is stored in the ATCA Point-
to-Point Connectivity Record located in the Multi-Record area of the FRU Inventory Informa-
tion (see page 7-50). The ATCA Point-to-Point Connectivity Record contains a Channel
Descriptor list, where each Link Descriptor details one type of point-to-point protocol sup-
ported by the referenced channels.
The ATCA channel descriptors define the ATCA channels implemented on a module. Each
channel has an arbitrary set of up to four ports. Channel descriptors map physical ports to
logical entities known as lanes, see Table 7-50.
Note: Certain Ethernet core switch and fat pipe switch module GbE switch ports are disabled due to lack of e-keying
support in the monitor.
Board Serial Number Variable, formatted as “730-XXXX”
Board Part Number Variable, formatted as “10XXXXXX-YY-Z”
FRU File ID Variable, for example: “fru-info.inf”
Product Information Area
Version Version number of the Product Information Area data structure
defined by the IPMI FRU specification
Language Code 0x01 = English
Manufacturer Name “Emerson”
Product Name “ATCA-9305”
Product Part/Model Number Variable, formatted as “10XXXXXX-YY-Z”
Product Version Not used, same information is provided by the part number
Product Serial Number Variable, formatted as “730-XXXX”
Asset Tag Not Used
FRU File ID Variable, for example: “fru-info.inf”
MultiRecord Area
E-Keying records See “E-Keying”
Maximum Internal Current “12.5 Amps”
Item: Description: (continued)
System Management: HPM.1 Firmware Upgrade
ATCA-9305 User’s Manual 10009109-01
7-52
Base Point-to-Point Connectivity
The ATCA-9305 supports two 10/100/1000BASE-T ports on Base Interface Channels 0 and
1, and two 10 GbE XAUI ports to the Fabric channels. Depending on the board configura-
tion, either two or six 10 GbE XAUI ports route to the optional rear transition module (RTM).
Table 7-50 shows the Point-to-point Connectivity Record Link Descriptors for the ATCA-
9305.
Note: For actual Point-to-Point connectivity Records for your configuration, query the IPMI controller.
Table 7-50: Link Description
HPM.1 FIRMWARE UPGRADE
The ATCA-9305 IPMC firmware supports a reliable field upgrade procedure compliant with
the HPM.1 specification. The prominent features of the firmware upgrade procedure are:
• The upgrade can be performed either over the payload serial interface or IPMB-0.
• The upgrade procedure is performed while the ATCA-9305 is online and operating
normally.
• The upgrades are reliable. A failure in the download (error or interruption) does not
disturb the ATCA-9305’s ability to continue using the “old” firmware or its ability to
restart the download process.
• The upgrades are reversible. The ATCA-9305 IPMC automatically reverts back to the
previous firmware if there is a problem when first running the new code, and can be
reverted manually using the HPM.1-defined Manual Rollback command.
Field: Value:1
1. h = hexadecimal, b = binary
Description:
Link Descriptor 000100000000b Port 0 Enabled; Base Interface; Channel 1
Link Type 01h PICMG 3.0 Base Interface 10/100/1000BASE-T
Link Type Extension 000b
Link Grouping ID 00h Independent Channel
Link Designator 000100000001b Port 0 Enabled; Base Interface; Channel 2
Link Type 01h PCIMG 3.0 Base Interface 10/100/1000BASE-T
Link Type Extension 0000b
Link Grouping ID 00h Independent Channel
Link Designator 000110000001b Port 0 Enabled; Update Channel Interface; Channel 1
Link Type 01h PICMG 3.1 Ethernet Fabric Interface
Link Type Extension 0000b Fixed 1000BASE-BX
Link GroupingID 00h Independent Channel
System Management: IPMC Headers
10009109-01 ATCA-9305 User’s Manual 7-53
HPM.1 Reliable Field Upgrade Procedure
The HPM.1 upgrade procedure is managed by a utility called the Upgrade Agent. The
Impitool utility is used as an Upgrade Agent for upgrading the ATCA-9305 IPMC firmware.
The Upgrade Agent communicates with the IPMC firmware via the payload serial interface
or IPMC-0, and uses the AdvancedTCA commands that are described in the HPM.1 specifica-
tion for upgrading the firmware. Updated firmware is packed into an image formatted in
compliance with the HPM.1 specification. That image is used by Upgrade Agent to prepare
and upgrade the IPMC firmware. The HPM.1 upgrade procedure includes the following
steps:
Preparation: This step erases the region in the flash memory where the component image will be writ-
ten.
Component Upload: This step is designed to upload the component image via IPMB or payload interface and
write it into the flash memory.
Component Activation:This step activates the previously upgraded component. This step can be deferred and per-
formed later.
For more details, refer to the HPM.1 specification listed in Table 1-2.
IPMC HEADERS
This JTAG header (JP1) is available for in-system programming of the CPLD.
Table 7-51: IPMP CPLD JP1 Pin Assignments
The EIA-232 debug serial port is accessible via the mini-B USB connector P4. Default port
settings are: 115200 baud (optional 9600), 8 data bits, 1 stop bit, no parity, no flow control.
Table 7-52: IPMP EIA-232 P4 Pin Assignments
Pin: Signal: Direction: Pin: Signal:
1 CPLD_TCK out 2 ground
3 CPLD_TDI in 4 3_3V (fused)
5CPLD_TMSout 6
no connect
7no connect —8no connect
9 CPLD_TDO out 10 ground
Pin: Signal: Pin: Signal:
1no connect 2 IPMP_RS_232_Rx
3 IPMP_RS_232_Tx 4 no connect
5ground 6ground
7ground
ATCA-9305 User’s Manual 10009109-01
7-54
(blank page)
10009109-01 ATCA-9305 User’s Manual 8-1
Section 8
Back Panel Connectors
There are multiple connectors on the ATCA-9305, reference Fig. 2-2 for their location. The
back panel connectors, Zones 1 through 3, are described in this chapter. Whether individual
back panel connectors are populated on the ATCA-9305 depends on the specific product
configuration.
ZONE 1
Connector P10 provides the AdvancedTCA Zone 1 power (dual redundant -48 VDC) and sys-
tem management connections. Four levels of sequential mating provide proper functional-
ity during live insertion or extraction, see Table 8-1.
Figure 8-1: Zone 1 Connector, P10
Table 8-1: Zone 1 Connector, P10 Pin Assignments
Pin: Signal: Insertion Sequence:
1reserved NA
2reserved NA
3reserved NA
4reserved NA
5HA0 third
6HA1 third
7HA2 third
8HA3 third
9HA4 third
10 HA5 third
11 HA6 third
12 HA7 (odd parity bit) third
13 IPMBA_SCL third
14 IPMBA_SDA third
15 IPMBB_SCL third
16 IPMBB_SDA third
17 no connect third
1131721
252830
27
33
32
34 31 29 26
24 20 16 4
Back Panel Connectors: Zone 2
ATCA-9305 User’s Manual 10009109-01
8-2
ZONE 2
Zone 2 (ZD) defines backplane connector J23, which supports the data transport interface.
The Zone 2 connector array supports four interfaces to the AdvancedTCA backplane:
• Base Node Interface (J23) supports two Base channels (10/100/1000 BASE-T)
• Fabric Interface (J23) supports two Fabric channels (10GbE)
Figure 8-2: Zone 2 and 3 Connectors; J23, J30-J31
18 no connect third
19 no connect third
20 no connect third
21 no connect third
22 no connect third
23 no connect third
24 no connect third
25 P10_CHS_GND first
26 Logic ground first
27 ENABLE_B fourth
28 -48RTNA first
29 -48RTNB first
30 no connect first
31 no connect first
32 ENABLE_ A fourth
33 -48A second
34 -48B third
Pin: Signal: Insertion Sequence:
Row H
Row G
Row F
Row E
Row D
Row C
Row B
Row A
10 6 15
Back Panel Connectors: Zone 3
10009109-01 ATCA-9305 User’s Manual 8-3
Table 8-2: Zone 2 Connector, J23 Pin Assignments
ZONE 3
These optional Zone 3 type A connectors, J30, J31, and J33, support a Rear Transition Mod-
ule (RTM). I/O signals are routed through Zone 3 connectors to the RTM to allow servicing
the ATCA-9305 without using cable assemblies. Connectors J30 and J31 use the same ZD
connector as Zone 2. See Fig. 8-3 for the J33 connector.
Table 8-3: Zone 3 Connector, J30 Pin Assignments
Row: Interface: AB: CD: EF: GH:
1Fabric
Channel 2
TX2+ TX2- RX2+ RX2- TX3+ TX3- RX3+ RX3-
2 TX0+ TX0- RX0+ RX0- TX1+ TX1- RX1+ RX1-
3Fabric
Channel 1
TX2+ TX2- RX2+ RX2- TX3+ TX3- RX3+ RX3-
4 TX0+ TX0- RX0+ RX0- TX1+ TX1- RX1+ RX1-
5Base
Channel 1
TRD0+ TRD0- TRD1+ TRD1- TRD2+ TRD2- TRD3+ TRD3-
6Base
Channel 2
TRD0+ TRD0- TRD1+ TRD1- TRD2+ TRD2- TRD3+ TRD3-
7-10 na no connect
A: B: C: D: E: F: G: H:
1 RTM_10G1
_ RX0_P
RTM_10G1
_ RX0_N
PQ_PCIE_
RXD3_P
PQ_PCIE_
RXD3_N
RTM_10G2
_ RX0_P
RTM_10G2
_ RX0_N
PQ_PCIE_
TXD3_P
PQ_PCIE_
TXD3_N
2 RTM_10G1
_ RX1_P
RTM_10G1
_ RX1_N
PQ_PCIE_
RXD2_P
PQ_PCIE_
RXD2_N
RTM_10G2
_ RX1_P
RTM_10G2
_ RX1_N
PQ_PCIE_
TXD2_P
PQ_PCIE_
TXD2_N
3 RTM_10G1
_ RX2_P
RTM_10G1
_ RX2_N
PQ_PCIE_
RXD1_P
PQ_PCIE_
RXD1_N
RTM_10G2
_ RX2_P
RTM_10G2
_ RX2_N
PQ_PCIE_
TXD1_P
PQ_PCIE_
TXD1_N
4 RTM_10G1
_ RX3_P
RTM_10G1
_ RX3_N
PQ_PCIE_
RXD0_P
PQ_PCIE_
RXD0_N
RTM_10G2
_ RX3_P
RTM_10G2
_ RX3_N
PQ_PCIE_
TXD0_P
PQ_PCIE_
TXD0_N
5 RTM_10G1
_TX0_P
RTM_10G1
_ TX0_P
PCIE_
REFCLKF_P
PCIE_
REFCLKF_N
RTM_10G2
_ TX0_P
RTM_10G2
_ TX0_N
no connect no connect
6 RTM_10G1
_ TX1_P
RTM_10G1
_ TX1_N
no connect no connect RTM_10G2
_ TX1_P
RTM_10G2
_ TX1_N
no connect no connect
7 RTM_10G1
_ TX2_P
RTM_10G1
_ TX2_N
no connect no connect RTM_10G2
_ TX2_P
RTM_10G2
_ TX2_N
no connect no connect
8 RTM_10G1
_ TX3_P
RTM_10G1
_ TX3_N
no connect no connect RTM_10G2
_ TX3_P
RTM_10G2
_ TX3_N
no connect no connect
9RTM_ID3 RTM_ID2 no connect no connect RTM_
GPIO3
RTM_
GPIO2
RTM_
GPIO7
RTM_
GPIO6
10 RTM_ID1 RTM_ID0 SW_MDC SW_MDIO RTM_
GPIO1
RTM_
GPIO0
RTM_
GPIO5
RTM_
GPIO4
Back Panel Connectors: Zone 3
ATCA-9305 User’s Manual 10009109-01
8-4
Table 8-4: Zone 3 Connector, J31 Pin Assignments
Figure 8-3: Zone 3 Connector, J33
Table 8-5: Zone 3 Connector, J33 Pin Assignments
A: B: C: D: E: F: G: H:
1 RTM_10G3
_ RX0_P
RTM_10G3
_ RX0_N
RTM_10G5
_ RX0_P
RTM_10G5
_ RX0_N
RTM_10G4
_ RX0_P
RTM_10G4
_ RX0_N
RTM_10G6
_ RX0_P
RTM_10G6
_ RX0_N
2 RTM_10G3
_ RX1_P
RTM_10G3
_ RX1_N
RTM_10G5
_ RX1_P
RTM_10G5
_ RX1_N
RTM_10G4
_ RX1_P
RTM_10G4
_ RX1_N
RTM_10G6
_ RX1_P
RTM_10G6
_ RX1_N
3 RTM_10G3
_ RX2_P
RTM_10G3
_ RX2_N
RTM_10G5
_ RX2_P
RTM_10G5
_ RX2_N
RTM_10G4
_ RX2_P
RTM_10G4
_ RX2_N
RTM_10G6
_ RX2_P
RTM_10G6
_ RX2_N
4 RTM_10G3
_ RX3_P
RTM_10G3
_ RX3_N
RTM_10G5
_ RX3_P
RTM_10G5
_ RX3_N
RTM_10G4
_ RX3_P
RTM_10G4
_ RX3_N
RTM_10G6
_ RX3_P
RTM_10G6
_ RX3_N
5 RTM_10G3
_ TX0_P
RTM_10G3
_ TX0_N
RTM_10G5
_ TX0_P
RTM_10G5
_ TX0_N
RTM_10G4
_ TX0_P
RTM_10G4
_ TX0_N
RTM_10G6
_ TX0_P
RTM_10G6
_ TX0_N
6 RTM_10G3
_ TX1_P
RTM_10G3
_ TX1_N
RTM_10G5
_ TX1_P
RTM_10G5
_ TX1_N
RTM_10G4
_ TX1_P
RTM_10G4
_ TX1_N
RTM_10G6
_ TX1_P
RTM_10G6
_ TX1_N
7 RTM_10G3
_ TX2_P
RTM_10G3
_ TX2_N
RTM_10G5
_ TX2_P
RTM_10G5
_ TX2_N
RTM_10G4
_ TX2_P
RTM_10G4
_ TX2_N
RTM_10G6
_ TX2_P
RTM_10G6
_ TX2_N
8 RTM_10G3
_ TX3_P
RTM_10G3
_TX3_N
RTM_10G5
_ TX3_P
RTM_10G5
_ TX3_N
RTM_10G4
_ TX3_P
RTM_10G4
_ TX3_N
RTM_10G6
_ TX3_P
RTM_10G6
_ TX3_N
9no connect no connect no connect no connect no connect no connect no connect no connect
10 no connect no connect no connect no connect no connect no connect no connect no connect
Pin: A: B: C: D:
1 RTM_ENABLE RTM_PS1_CONN* PQ_CONSOLE_RX_M RTM_PB_RST*
2 RTM_PP_PWRGD RTM_HS_LED PQ_CONSOLE_TX_M RTM_E_HANDLE
3 RTM_MP_PWRGD IPMB_RTM_SCL_BUFF no connect RTM_RST*
4no connect IPMB_RTM_SDA_BUFF 3_3V_MP_RTM 3_3V_MP_RTM
5 ground ground ground ground
6 12V_RTM 12V_RTM 12V_RTM 12V_RTM
D
C
B
A
16
10009109-01 ATCA-9305 User’s Manual 9-1
Section 9
Management Processor Monitor
The ATCA-9305 monitor is based on the Embedded PowerPC Linux Universal Boot (U-Boot)
Project program, available under the GNU General Public License (GPL). For instructions on
how to obtain the source code for this GPL program, please visit http://www.emersonem-
beddedcomputing.com/post-sales_support/218, send an e-mail to support@arte-
syncp.com, or call Emerson at (800) 327-1251.
This chapter describes the monitor’s basic features, operation, and configuration
sequences. This chapter also serves as a reference for the monitor commands and func-
tions.
COMMAND-LINE FEATURES
The ATCA-9305 monitor uses a command-line interface with the following features:
Auto-Repeat: After entering a command, you can re-execute it simply by pressing the ENTER or RETURN
key.
Command History: Recall previously entered commands using the up and down arrow keys.
TFTP Boot: You can use the TFTP protocol to load application images via Ethernet into the ATCA-9305’s
memory.
Auto-Boot: You can store specific boot commands in the environment to be executed automatically
after reset.
Flash Programming: You can write application images into flash via the U-Boot command line. The upper 1 MB at
the base of flash and 128 KB of each flash bank is reserved for the monitor and environment
variables (see “MPC8548 Memory Map”). One megabyte is reserved at the second bank of
flash. The moninit command will load both banks of flash (see “moninit” on page 9-22) with
the monitor and default environment variables.
At power-up or after a reset, the monitor runs diagnostics and reports the results in the
start-up display, see Fig. 9-1. During the power-up sequence, the monitor configures the
board according to the environment variables (see “MPC8548 Environment Variables” on
page 9-26). If the configuration indicates that autoboot is enabled, the monitor attempts to
load the application from the specified device. If the monitor is not configured for autoboot
or a failure occurs during power-up, the monitor enters normal command-line mode. Also,
the optional “e-keying” environment variable enables connections at power-up, for debug
purposes only, to the Update Channel and payload ports that go off the ATCA-9305. See
Table 9-7 for more information.
The monitor command prompt in Fig. 9-1 is the result of a successful hardware boot of the
ATCA-9305.
Management Processor Monitor: Command-Line Features
ATCA-9305 User’s Manual 10009109-01
9-2
Figure 9-1: Example MPC8548 Monitor Start-up Display
This prompt is also displayed as an indication that the monitor has finished executing a
command or function invoked at the command prompt (except when the command loads
and jumps to a user application). The hardware product name (ATCA-9305), and current
software version number are displayed in the prompt.
Prior to the console port being available, the monitor will display a four-bit hexadecimal
value on LED1 through LED4 to indicate the power-up status (see Table 9-1). See Fig. 2-4 for
the debug LED locations. In the event of a specific initialization error, the LED pattern will be
displayed and the board initialization will halt.
Table 9-1: Debug LED Codes
LED Code: Power-up Status: LED Value:
BOARD_PRE_INIT start booting, setup BATs done 0x01
SERIAL_INIT console init done 0x02
Hardware initialization
Monitor command prompt
U-Boot 1.1.4 (Jan 8 2007 - 16:07:48)1.0
CPU: 8548_E, Version: 2.0, (0x80390020)
Core: E500, Version: 2.0, (0x80210020)
Clock Configuration:
CPU: 999 MHz, CCB: 399 MHz,
DDR: 199 MHz, LBC: 49 MHz
Board: ATCA-9305 ATCA Blade
Emerson Network Power, Embedded Computing Inc.
cPLD Ver: 2
I2C: ready
Clearing ALL of memory
................
DRAM: 512 MB
Testing Top 1M Area of DRAM........PASSED
Relocating code to RAM
FLASH: [4MB@e0000000][4MB@e1000000]8 MB
L2 cache: enabled
In: serial
Out: serial
Err: serial
Ser#: 1096
Diags Mem: PASSED
Diags I2C: PASSED
Diags Flash: PASSED
BootDev: Socket
I-cache enabled
D-cache enabled (write-through)
L2 cache enabled. (L2CTL: 0xa0000000)
(write-through)
IPMC: v0.1.1
DOC: Turbo Mode
Net: eTSEC1, eTSEC2
ATCA-9305 (Mon 1.0)=>
Management Processor Monitor: Basic Operation
10009109-01 ATCA-9305 User’s Manual 9-3
BASIC OPERATION
The monitor performs various configuration tasks upon power-up or reset. This section
describes the monitor operation during initialization of the ATCA-9305 board. The flow-
chart (see Fig. 9-2) illustrates the power-up and global reset sequence (bold text indicates
environment variables).
Power-up/Reset Sequence
The ATCA-9305 monitor follows the boot sequence in Fig. 9-2 before auto-booting the oper-
ating system or application software. At power-up or board reset, the monitor performs
hardware initialization, diagnostic routines, autoboot procedures, free memory initializa-
tion, and if necessary, invokes the command line. See Fig. 3-4 for the Cavium CN5860 pro-
cessor boot sequence. See Table 9-6 for default environment variables settings.
CHECKBOARD get processor and bus speeds done 0x03
SDRAM_INIT RAM / ECC init done 0x04
AFTER_RELOC U-Boot relocated to RAM done 0x05
MISC_R final init including Ethernet done 0x06
GONE_TO_PROMPT — 0x00
LED Code: Power-up Status: LED Value:
Management Processor Monitor: Basic Operation
ATCA-9305 User’s Manual 10009109-01
9-4
Figure 9-2: Power-up/Reset Sequence Flowchart
POST Diagnostic Results
The ATCA-9305 Power-On Self-Test (POST) diagnostic results are stored as a 32-bit value in
I2C NVRAM at the offset 0x07F0-0x07FF. Each bit indicates the result of a specific test,
therefore this field can store the results of up to 32 diagnostic tests. Table 9-2 assigns the bits
to specific tests.
Power-up or Reset
U-Boot Monitor
Default Board Initialization
U-Boot Monitor
PCI Monarch, Enumerate
U-Boot Monitor
Configure Ethernet Switch
Initialize IPMC
Execute POST
U-Boot Monitor
Start Autoboot Sequence
(Boot Operating System)
Operating System Boot
Boot OS image
according to
configuration parameters
Boot Caviums
Boot Cavium processor
according to
configuration parameters
Management Processor Monitor: Monitor Recovery and
10009109-01 ATCA-9305 User’s Manual 9-5
Table 9-2: POST Diagnostic Results–Bit Assignments
Monitor SDRAM Usage
Monitor SDRAM usage is typically around 1 MB for monitor code and stack support. Please
note that the monitor stack grows downward from below where the monitor code resides
(in the upper 512 KB). The monitor C stack will typically not grow beyond 512 KB, therefore
the upper 1 MB of SDRAM is reserved for monitor use.
Note: The monitor has the ability to preserve (not overwrite) areas of memory defined by the pram environment
variable.
Caution: Any writes to these areas can cause unpredictable operation of the monitor.
MONITOR RECOVERY AND UPDATES
This section describes how to recover and/or update the monitor, given one or more of the
following conditions:
• If there is no console output, the monitor may be corrupted and need recovering (see
the “Recovering the Monitor” section).
• If the monitor still functions, but is not operating properly, then you may need to reset
the environment variables (see the “Resetting Environment Variables” section).
• If you are having Ethernet problems in the monitor, you may need to set the serial
number, since the MAC address is calculated from the serial number variable.
Bit: Diagnostic Test: Description: Value:
0 SDRAM Verify address and data lines are intact
0 Passed the test
1 Failure detected
1 Flash Verify size and initialization of soldered
flash
2I
2C Verify all local I2C devices are connected
to the I2C bus
3 Ethernet Switch Verify PCI communication with switch
4Reserved
5 PCIe Time-out PCIe enumeration skipped by user
6 DOC Embedded Flash
Drive (EFD)
Verify presence and ability to access
configuration space of DOC
7 Cavium 1 Presence Verify presence and ability to
communicate via PCI bus with Cavium 1
8 Cavium 2 Presence Verify presence and ability to
communicate via PCI bus with Cavium 2
9-31 Reserved
!
Management Processor Monitor: Monitor Recovery and
ATCA-9305 User’s Manual 10009109-01
9-6
Recovering the Monitor
1Make sure that a monitor ROM device is installed in the PLCC socket on the ATCA-9305.
2Verify there is a shunt on J9, across pins 1 and 2.
3Issue the following command, where serial_number is the board’s serial number, at the
monitor prompt:
ATCA-9305 (1.0) => moninit serial_number
moninit will also reset environment variables to the default state.
4To boot from soldered flash, power down the board and remove the shunt from J9, pins 1
and 2.
The monitor always resides in the top 512 KB block of NOR flash (banks 1 and 2) as shown in
Table 9-3.
Table 9-3: Monitor Address per Flash Device
Resetting Environment Variables
To restore the monitor’s standard environment variables, execute the following commands
and insert the appropriate data in the italicized fields:
ATCA-9305 (1.0) => moninit serial_number noburn
Note: Press the ‘s’ key on the keyboard during reset to force the default environment variables to be loaded. See
“MPC8548 Environment Variables” for more information.
Optionally, save your settings:
ATCA-9305 (1.0) => saveenv
Updating the Monitor via TFTP
To update the monitor via TFTP, ensure that an appropriate VLAN is set up in the Ethernet
switch (see the ATCA-9305 Quick Start Guide, #10009110-xx) and execute the following
commands, inserting the appropriate data in the italicized fields:
If necessary, edit your network settings:
ATCA-9305 (1.0) => setenv ipaddr 192.168.1.100
ATCA-9305 (1.0) => setenv gatewayip 192.168.1.1
ATCA-9305 (1.0) => setenv netmask 255.255.255.0
ATCA-9305 (1.0) => setenv serverip 10.64.16.168
Address Range (hex): Device:
F3F8,0000-F400,0000 Monitor Location in Flash Bank2 (4 MB)
F3B8,0000-F3C0,0000 Monitor Location in Flash Bank1 (4 MB)
F3B7,0000-F3B7,1000 Environment Variables
F3F7,0000-F3F7,1000 Redundant Environment Variables
Management Processor Monitor: Monitor Command
10009109-01 ATCA-9305 User’s Manual 9-7
ATCA-9305 (1.0) => setenv ethport eTSEC1
Optionally, save your settings:
ATCA-9305 (1.0) => saveenv
TFTP the new monitor (binary) image to memory location 0x100000:
ATCA-9305 (1.0) => tftpboot 100000 path_to_file_on_tftp_server
Update the monitor:
ATCA-9305 (1.0) => moninit serial_number 100000
If moninit( ) fails, burn the new monitor to a ROM and follow the recovery steps in the
“Recovering the Monitor” section.
MONITOR COMMAND REFERENCE
This section describes the syntax and typographic conventions for the ATCA-9305 monitor
commands. Subsequent sections in this chapter describe individual commands, which fall
into the following categories: boot, memory, flash, environment variables, test, and other
commands.
Command Syntax
The monitor uses the following basic command syntax:
<Command> <argument 1> <argument 2> <argument 3>
• The command line accepts three different argument formats: string, numeric, and
symbolic. All command arguments must be separated by spaces with the exception of
argument flags, which are described below.
• Monitor commands that expect numeric arguments assume a hexadecimal base.
• All monitor commands are case sensitive.
• Some commands accept flag arguments. A flag argument is a single character that
begins with a period (.). There is no white space between an argument flag and a
command. For example, md.b 80000 is a valid monitor command, while md .b 80000
is not.
• Some commands may be abbreviated by typing only the first few characters that
uniquely identify the command. For example, you can type h instead of help. However,
commands cannot be abbreviated when accessing online help. You must type help and
the full command name.
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Command Help
Access all available monitor commands by pressing the ? key or entering help. Access the
monitor online help for individual commands by typing help <command>. The full com-
mand name must be entered to access the online help.
Typographic Conventions
In the following command descriptions, text in Courier shows the command format.
Square brackets [ ] enclose optional arguments, and angled brackets < > enclose required
arguments. Italic type indicates a variable or field that requires input.
BOOT COMMANDS
The boot commands provide facilities for booting application programs and operating sys-
tems from various devices.
bootd
Execute the command stored in the bootcmd environment variable.
Definition: bootd
bootelf
The bootelf command boots from an ELF image in memory, where address is the load
address of the ELF image.
Definition: bootelf [ address ]
bootm
The bootm command boots an application image stored in memory, passing any entered
arguments to the called application. When booting a Linux kernel, arg can be the address of
an initrd image. If addr is not specified, the environment variable loadaddr is used as the
default.
Definition: bootm [addr [arg …]]
bootp
The bootp command boots an image via a network connection using the BootP/TFTP pro-
tocol. If loadaddress or bootfilename is not specified, the environment variables loadaddr and
bootfile are used as the default.
Definition: bootp [loadAddress] [bootfilename]
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To use network download commands (e.g., bootp, bootvx, rarpboot, tftpboot), the envi-
ronment variables listed in Table 9-4 must be configured. To set a static IP, these environ-
ment variables must be specified through the command line interface.
Table 9-4: Static IP Ethernet Configuration
bootv
The bootv command checks the checksum on the primary image (in flash) and boots it, if
valid. If it is not valid, it checks the checksum on the secondary image (in flash) and boots it,
if valid. If neither checksum is valid, the command returns back to the monitor prompt.
Definition: Verify bootup.
bootv
Write image to flash and update NVRAM.
bootv <primary|secondary> write <source> <dest> <size>
Update NVRAM based on image already in flash.
bootv <primary|secondary> update <source> <size>
Check validity of images in flash.
bootv <primary|secondary> check
bootvx
The bootvx command boots VxWorks® from an ELF image, where address is the load
address of the VxWorks ELF image. To use this command, the environment variables listed
in Table 9-4 must be configured.
Definition: bootvx [ address ]
dhcp
The dhcp command invokes a Dynamic Host Configuration Protocol (DHCP) client to obtain
IP and boot parameters by sending out a DHCP request and waiting for a response from a
server.
Environment Variable: Description:
ipaddr Local IP address for the board
serverip TFTP/NFS server address
netmask Net mask
gatewayip Gateway IP address
ethport eTSEC1 default
ethaddr1
1. Ensure that each MAC address on the network is unique.
MAC address
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Definition: dhcp [loadaddress] [bootfilename]
To use the dhcp command, your DHCP server must be configured with the variables desig-
nated in Table 9-5.
Table 9-5: DHCP Ethernet Configuration
rarpboot
The rarpboot command boots an image via a network connection using the RARP/TFTP
protocol. If loadaddress or bootfilename is not specified, the environment variables loadaddr
and bootfile are used as the default. To use this command, the environment variables listed
in Table 9-4 must be configured.
Definition: rarpboot [loadaddress] [bootfilename]
tftpboot
The tftpboot command loads an image via a network connection using the TFTP protocol.
The environment variable’s ipaddr and serverip are used as additional parameters to this
command. If loadaddress or bootfilename is not specified, the environment variables load-
addr and bootfile are used as the default. To use this command, the environment variables
listed in Table 9-4 must be configured.
The port used is defined by the ethport environment variable. If all is selected for ethport,
the TFTP process will cycle through each port until a connection is found or all ports have
failed.
Definition: tftpboot [loadaddress] [bootfilename]
Environment
Variable: Description: Value1:
1. Values for ethaddr, netdev and autoload are set by the user.
ipaddr Local IP address for the board, configured by DHCP e.g., 192.168.1.1
serverip TFTP/NFS server address value must be configured
after the DHCP IP address is acquired2
2. The value obtained by the DHCP server may not be applicable to your development application.
e.g., 192.168.1.2
netmask Net mask, obtained by DHCP —
gatewayip Gateway IP address, obtained by DHCP —
ethport eTSEC1 default —
ethaddr3
3. Ensure that each MAC address on the network is unique.
MAC address 00:80:F9:xx:xx:xx
autoload4
4. If autoload is not set or configured to “yes,” ensure that the DHCP provides proper information for
autoboot. If proper autoboot information is not provided, an error may occur.
Boot image from TFTP server after DHCP acquisition no
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FILE LOAD COMMANDS
The file load commands load files over the serial port.
loadb
The loadb command loads a binary file over the serial port. The command takes two
optional parameters:
offset: The address offset parameter allows the file to be stored in a location different than what is
indicated within the binary file by adding the value off to the file’s absolute address.
baudrate: The baudrate parameter allows the file to be loaded at baud instead of the monitor’s con-
sole baudrate.
The file is not automatically executed, the loadb command only loads the file into memory.
Definition: loadb [off] [baud]
loads
The loads command loads an S-Record file over the serial port. The command takes two
optional parameters:
offset: The address offset parameter allows the file to be stored in a location different than what is
indicated within the S-Record file by adding the value off to the file’s absolute address.
baudrate: The baudrate parameter allows the file to be loaded at baud instead of the monitor’s con-
sole baudrate.
The file is not automatically executed, the loads command only loads the file into memory.
Definition: loads [off] [baud]
MEMORY COMMANDS
The memory commands allow you to manipulate specific regions of memory. For some
memory commands, the data size is determined by the following flags:
Definition: The flag .b is for data in 8-bit bytes.
Definition: The flag .w is for data in 16-bit words.
Definition: The flag .l is for data in 32-bit long words.
These flags are optional arguments and describe the objects on which the command oper-
ates. If you do not specify a flag, memory commands default to 32-bit long words. Numeric
arguments are in hexadecimal.
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cmp
The cmp command compares count objects between addr1 and addr2. Any differences are
displayed on the console display.
Definition: cmp [.b, .w, .l] addr1 addr2 count
cp
The cp command copies count objects located at the source address to the target address.
Note: If the target address is located in the range of the flash device, it will program the flash with count objects
from the source address. The cp command does not erase the flash region prior to copying the data. The flash
region must be manually erased using the erase command prior to using the cp command.
Definition: cp [.b, .w, .l] source target count
Example: In this example, the cp command is used to copy 0x1000, 32-bit values from address
0x100000 to address 0x80000.
=> cp 100000 80000 1000
find
The find command searches from base_addr to top_addr looking for pattern. For the find
command to work properly, the size of pattern must match the size of the object flag. The -a
option searches for the absence of the specified pattern.
Definition: find [.b, .w, .l] [-a] base_addr top_addr pattern
Example: In this example, the find command is used to search for the 32-bit pattern 0x12345678 in
the address range starting at 0x40000, and ending at 0x80000.
=> find.1 40000 80000 12345678
Searching from 0x00040000 to 0x00080000
Match found: data = 0x12345678 Adrs = 0x00050a6c
=>
md
The command md displays the contents of memory starting at address. The number of
objects displayed can be defined by an optional third argument, # of objects. The memory’s
numerical value and its ASCII equivalent is displayed.
Definition: md [.b, .w, .l] address [# of objects]
Example: In this example, the md command is used to display thirty-two 16-bit words starting at the
physical address 0x80000.
=> md.w 80000 20
00080000: ffff ffff ffff ffff ffff ffff ffff ffff ................
00080010: ffff ffff ffff ffff ffff ffff ffff ffff ................
00080020: ffff ffff ffff ffff ffff ffff ffff ffff ................
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00080030: ffff ffff ffff ffff ffff ffff ffff ffff ................
mm
The mm command modifies memory one object at a time. Once started, the command line
prompts for a new value at the starting address. After a new value is entered, pressing
ENTER auto-increments the address to the next location. Pressing ENTER without entering a
new value leaves the original value for that address unchanged. To exit the mm command,
enter a non-valid hexadecimal value (such as x) followed by ENTER.
Definition: mm [.b, .w, .l] address
Example: In this example, the mm command is used to write random 8-bit data starting at the physi-
cal address 0x80000.
=> mm.b 80000
00080000: ff ? 12
00080001: ff ? 23
00080002: ff ? 34
00080003: ff ? 45
00080004: ff ?
00080005: ff ? x
=> md.b 80000 6
00080000: 12 23 34 45 ff ff .#4E
=>
nm
The nm command modifies a single object repeatedly. Once started, the command line
prompts for a new value at the selected address. After a new value is entered, pressing
ENTER modifies the value in memory and then the new value is displayed. The command
line then prompts for a new value to be written at the same address. Pressing ENTER with-
out entering a new value leaves the original value unchanged. To exit the nm command,
enter a non-valid hexadecimal value (such as x) followed by ENTER.
Definition: nm [.b, .w, .l] address
mw
The command mw writes value to memory starting at address. The number of objects mod-
ified can be defined by an optional fourth argument, count.
Definition: mw [.b, .w, .l] address value [count]
Example: In this example, the mw command is used to write the value 0xabba three times starting at
the physical address 0x80000.
=> mw.w 80000 abba 3
=> md 80000
00080000: abbaabba abbaffff ffffffff ffffffff ................
00080010: ffffffff ffffffff ffffffff ffffffff ................
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00080020: ffffffff ffffffff ffffffff ffffffff ................
00080030: ffffffff ffffffff ffffffff ffffffff ................
00080040: ffffffff ffffffff ffffffff ffffffff ................
00080050: ffffffff ffffffff ffffffff ffffffff ................
00080060: ffffffff ffffffff ffffffff ffffffff ................
00080070: ffffffff ffffffff ffffffff ffffffff ................
FLASH COMMANDS
The flash commands affect the StrataFlash devices on the ATCA-9305 circuit board. There
are four flash banks on the ATCA-9305 board (see “Flash” on page 4-7). They can be
accessed by:
• the individual bank (1, 2, 3 or 4), or
• the address, where both banks are regarded as one contiguous address space
The following flash commands access the individual flash bank as flash bank 1. To access the
individual sectors within each flash bank, the sector numbers start at 0 and end at one less
than the total number of sectors in the bank. For a flash bank with 128 sectors, the follow-
ing flash commands access the individual sectors as 0 through 127.
cp
The cp command can be used to copy data into the flash device. For the cp command syn-
tax, refer to “Memory Commands” on page 9-11.
erase
The erase command erases the specified area of flash memory.
Definition: Erase all of the sectors in the address range from start to end.
erase start end
Erase all of the sectors SF (first sector) to SL (last sector) in flash bank # N.
erase N:SF[-SL]
Erase all of the sectors in flash bank # N.
erase bank N
Erase all of the sectors in all of the flash banks.
erase all
flinfo
The flinfo command prints out the flash device’s manufacturer, part number, size, number
of sectors, and starting address of each sector.
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Definition: Print information for all flash memory banks.
flinfo
Print information for the flash memory in bank # N.
flinfo N
protect
The protect command enables or disables the flash sector protection for the specified flash
sector. Protection is implemented using software only. The protection mechanism inside
the physical flash part is not being used.
Definition: Protect all of the flash sectors in the address range from start to end.
protect on start end
Protect all of the sectors SF (first sector) to SL (last sector) in flash bank # N.
protect on N:SF[-SL]
Protect all of the sectors in flash bank # N.
protect on bank N
Protect all of the sectors in all of the flash banks.
protect on all
Remove protection on all of the flash sectors in the address range from start to end.
protect off start end
Remove protection on all of the sectors SF (first sector) to SL (last sector) in flash bank # N.
protect off N:SF[-SL]
Remove protection on all of the sectors in flash bank # N.
protect off bank N
Remove protection on all of the sectors in all of the flash banks.
protect off all
EEPROM/I2C COMMANDS
This section describes commands that allow you to read and write memory on the serial
EEPROMs and I2C devices.
eeprom
The eeprom command reads and writes from the EEPROM. For example:
eeprom read 53 100000 1800 100
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reads 100 bytes from offset 0x1800 in serial EEPROM 0x53 (right-shifted 7-bit address) and
places it in memory at address 0x100000.
Definition: Read/write cnt bytes from devaddr EEPROM at offset off.
eeprom read devaddr addr off cnt
eeprom write devaddr addr off cnt
icrc32
The icrc32 computes a CRC32 checksum.
Definition: icrc32 chip address[.0, .1, .2] count
iloop
The iloop command reads in an infinite loop on the specified address range.
Definition: iloop chip address[.0, .1, .2] [# of objects]
imd
The imd command displays the primary I2C bus memory. For example:
imd 53 1800.2 100
displays 100 bytes from offset 0x1800 of I2C device 0x53 (right-shifted 7-bit address). The
.2 at the end of the offset is the length, in bytes, of the offset information sent to the
device. The serial EEPROMs all have two-byte offset lengths. The Real-Time Clock (RTC) has
a one-byte offset length. The temperature sensors have zero-byte offset lengths.
Definition: imd chip address[.0, .1, .2] [# of objects]
imm
The imm command modifies the primary I2C memory and automatically increments the
address.
Definition: imm chip address[.0, .1, .2]
imw
The imw command writes (fills) memory.
Definition: imw chip address[.0, .1, .2] value [count]
inm
The inm command modifies I2C memory, reads it, and keeps the address.
Definition: inm chip address[.0, .1, .2]
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iprobe
The iprobe command probes to discover valid primary I2C bus chip addresses.
Definition: iprobe
IPMC COMMANDS
IPMI Baseboard Management Controller (BMC) watchdog is supported and serviced
throughout the monitor boot process. The BMC watchdog is disabled if the monitor goes to
the monitor prompt.
bootdev
The bootdev command gets or sets the initial boot bank. Get prints out the flash bank set as
initial boot device.
Definition: bootdev get
The IPMC sets the hardware strapping for the initial boot device.
bootdev set <bank>
Where <bank> is either b0 or b1 for the corresponding flash bank, or b3 to boot from socket
and if a shunt is installed on J9 [1:2].
fru
The fru command opens, closes, saves, sets, shows, dumps, and loads fru data to and from
the IPMC.
Definition: fru <command> [ arg1 arg2 … ]
command := [ open | close | save | set | show | dump | load | create ]
fru open <id>
fru close
fru save
fru set <section [chassis|board|product]><field><value>
fru set <section> <field> <value>
section := [ chassis | board | product ]
fru set chassis <field> <value>
field := [ type | part | serial ]
fru set board <field> <value>
field := [ date | maker | name | serial | part | file ]
fru set product <field> <value>
field := [ maker | name | part | version |serial | asset | file ]
fru show
fru dump <address>
fru load <address><size>
Set data in the internal use area.
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fru set internal <source addr> <internal use offset> <count>
The fru create command loads a default fru image to a blank fru device.
fru create <id> default <product name>
fru create <id> <address> <size> <product name>
fruinit
The fruinit command initializes the following fru data fields: part number, build date, and
serial number in the board and product sections.
Definition: fruinit <fru id> <part number> <build date> [ serial number ]
fruled
The fruled command allows the application programmer to get the status of the red out-of-
service LED or to turn the LED on or off when an application fails to load.
Definition: fruled get <fru id> <led id> <led state> <led function (on/off)> <on time> <color>
fruled set <fru id> <led id> <led function (on/off)> <on time> <color>
Example: Turns the red out-of-service LED on.
fruled set 0 1 0xff 0 2
Turns the red out-of-service LED off.
fruled set 0 1 0 0 2
ipmchpmfw
The ipmchpmfw command restores the previous IPMC firmware from the backup IPMC
firmware stored in the controller. The upgrade argument upgrades the IPMC firmware with
the upgrade image held in memory.
Definition: ipmchpmfw [restore] [upgrade <source address>]
sensor
The sensor command probes, reads, and prints the sensor information from the IPMI.
Definition: sensor [probe|read|dump]
Sensor probe prints out each sensor number and name.
sensor probe <sensor number>
Sensor read prints out the sensor reading for sensor.
sensor read <sensor number>
Sensor dump prints out the raw Sensor Data Record (SDR) information for sensor.
sensor dump <sensor number>
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ENVIRONMENT PARAMETER COMMANDS
The monitor uses on-board, non-volatile memory for the storage of environment parame-
ters. Environment parameters are stored as ASCII strings with the following format.
<Parameter Name>=<Parameter Value>
Some environment variables are used for board configuration and identification by the
monitor. The environment parameter commands deal with the reading and writing of these
parameters. Refer to “MPC8548 Environment Variables” on page 9-26 for a list of monitor
environment variables.
Redundant environment parameters allow you to store a “backup” copy of environment
parameters should they ever become corrupt. The redundant environment parameters are
only used if the main parameters are corrupt.
To save environment variables:
1Use moninit to save default environment variables to both primary and secondary
environment parameters.
2Use saveenv to save to the primary environment variables.
3Set the next save to the secondary image.
printenv
The printenv command displays all of the environment variables and their current values to
the display.
Definition: Print the values of all environment variables.
printenv
Print the values of all environment variable (exact match) ‘name’.
printenv name …
saveenv
The saveenv command writes the environment variables to non-volatile memory.
Definition: saveenv
setenv
The setenv command adds new environment variables, sets the values of existing environ-
ment variables, and deletes unwanted environment variables.
Definition: Set the environment variable name to value or adds the new variable name and value to the
environment.
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setenv name value
Removes the environment variable name from the environment.
setenv name
TEST COMMANDS
The commands described in this section perform diagnostic and memory tests.
diags
The diags command runs the Power-on Self-test (POST).
Definition: diags
mtest
The mtest command performs a simple SDRAM read/write test.
Definition: mtest [start [end [pattern]]]
um
The um command is a destructive memory test. Press the ‘q’ key to quit this test; the moni-
tor completes running the most recent iteration, and exits to the default prompt after dis-
playing cumulative results for the completed iterations.
Definition: um [.b, .w, .l] base_addr [top_addr]
OTHER COMMANDS
This section describes all the remaining commands supported by the ATCA-9305 monitor.
autoscr
The autoscr command runs a script, starting at address addr, from memory.
A valid autoscr header must be present.
Definition: autoscr [addr]
base
The base command prints or sets the address offset for memory commands.
Definition: Displays the address offset for the memory commands.
base
Sets the address offset for the memory commands to off.
base off
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bdinfo
The bdinfo command displays the Board Information Structure.
Definition: bdinfo
coninfo
The coninfo command displays the information for all available console devices.
Definition: coninfo
crc32
The crc32 command computes a CRC32 checksum on count bytes starting at address.
Definition: crc32 address count
date
The date command will set or get the date and time, and reset the RTC device.
Definition: Set the date and time.
date [MMDDhhmm[[CC]YY][.ss]]
Display the date and time.
date
Reset the RTC device.
date reset
echo
The echo command echoes args to console.
Definition: echo [args..]
enumpci
The enumpci command enumerates the PCI bus (when the hardware is the PCI Root Com-
plex in the system).
Definition: enumpci
go
The go command runs an application at address addr, passing the optional argument arg to
the called application.
Definition: go addr [arg…]
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help
The help (or ?) command displays the online help. Without arguments, all commands are
displayed with a short usage message for each. To obtain more detailed information for a
specific command, enter the desired command as an argument.
Definition: help [command …]
iminfo
The iminfo command displays the header information for an application image that is
loaded into memory at address addr. Verification of the image contents (magic number,
header, and payload checksums) are also performed.
Definition: iminfo addr [addr …]
isdram
The isdram command displays the SDRAM configuration information (valid chip values
range from 50 to 57).
Definition: isdram addr
loop
The loop command executes an infinite loop on address range.
Definition: loop [.b, .w, .l] address number_of_objects
memmap
The memmap command displays the board’s memory map layout.
Definition: memmap
moninit
The moninit command resets the NVRAM and serial number, and writes the monitor to
flash. The ATCA-9305 must be booted from the boot socket for this command to function in
the default state. The proper region of flash memory will be unlocked and erased prior to
copying the monitor software into it.
The command flags, .1 or .2, force the monitor to be programmed to a single (.1) bank of
flash or dual (.2) banks of flash. If the command flags are not used, then moninit checks for
the number of banks of flash. If there are two banks of flash, then moninit automatically
programs both banks for redundancy. Also, the serial number can be obtained from the fru
data if “fru” is used as a parameter.
Definition: Initialize environment variables and serial number in NVRAM and copy the monitor from the
socket to NOR (soldered) flash.
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moninit[.1, .2] <serial# or “fru”>
Initialize environment variables and serial number in NVRAM but do not update the monitor
in NOR flash.
moninit[.1, .2] <serial# or “fru”> noburn
Initialize environment variables and serial number in NVRAM and copy the monitor from
<src_address> into NOR flash.
moninit[.1, .2] <serial# or “fru”> <src_address>
pci
The pci command enumerates the PCI bus. It displays enumeration information about each
detected device. The pci command allows you to display values for and access the PCI Con-
figuration Space.
Definition: Display a short or long list of PCI devices on the bus specified by bus.
pci [bus] [long]
Show the header of PCI device bus.device.function.
pci header b.d.f
Display the PCI configuration space (CFG).
pci display[.b, .w, .l] b.d.f [address] [# of objects]
Modify, read, and keep the CFG address.
pci next[.b, .w, .l] b.d.f address
Modify, automatically increment the CFG address.
pci modify[.b, .w, .l] b.d.f address
Write to the CFG address.
pci write[.b, .w, .l] b.d.f address value
phy
The phy command reads or writes to the contents of the PHY registers. The values changed
via this command are not persistent and clear after a hard or soft reset. The port options are
all, eTSEC1, eTSEC2, and base1 and base2 via the switch. “R” reads the register contents at
the address specified. “W” writes the address value to the register address specified. “A”
reads the contents of all registers.
Definition: phy [port] [R|W|A] (address) (value)
Example: The following is an example of a read from register address 0x1a.
phy eTSEC2 r 0x1a
The following is an example of a write to register address 0x1a where 0 is the data to write.
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phy eTSEC2 w 0x1a 0
ping
The ping command sends a ping over Ethernet to check if the host can be reached. The port
used is defined by the ethport environment variable. If all is selected for ethport, the ping
process cycles through each port until a connection is found or all ports have failed.
Definition: ping host
reset
The reset command performs a hard reset of the CPU by writing to the reset register on the
board. Without any arguments, the ATCA-9305 CPU is reset.
Definition: reset
run
The run command runs the commands in an environment variable var.
Definition: run var [ … ]
Use $ for variable substitution; the syntax “$(variable_name)” should be used for variable
expansion.
Example: => setenv cons_opts console=tty0 console=ttyS0,\$(baudrate)
=> printenv cons_opts cons_opts=console=tty0 console=ttyS0,$(baudrate)
Use the \ character to escape execution of the $ as seen in the setenv command above. In
this example, the value for baudrate will be inserted when cons_opts is executed.
script
The script command runs a list of monitor commands out of memory. The list is an ASCII
string of commands separated by the ; character and terminated with the ;; charac-
ters. <script address> is the starting location of the script.
Note: A script is limited to 1000 characters.
Definition: script <script address>
showmac
The showmac command displays the Processor MAC addresses assigned to each Ethernet
port.
Definition: showmac
showpci
The showpci command scans the PCI bus and lists the base address of the devices.
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Definition: showpci
sleep
The sleep command executes a delay of N seconds.
Definition: Delay execution for N seconds (N is a decimal value).
sleep N
switch_reg
The switch_reg command reads or writes to the Ethernet core switch registers. The values
changed via this command are not persistent and clear after a hard or soft reset. Option val-
ues are as follows: switch (core or fp), port (0 - 25), block (1-7), and sub-block (0-15). “R”
reads the register contents at the address specified. “W” writes the address value to the reg-
ister address specified.
Definition: switch_reg [switch] [port op | block sub-block op [R|W]] (address) (value)
Example: The following is an example of a read of register address 0x1a.
switch_reg core 0 r 0x1a
The following is an example of a write to register address 0x1a where 0 is the data to write.
switch_reg core 0 w 0x1a 0
version
The version command displays the monitor’s current version number.
Definition: version
vlan
The vlan command creates one or more new VLANs using vid as the VLAN identification
(VID) value and deletes one or more existing VLANs whose VLAN ID matches the VLAN ID
value vid. These variables are set using a comma-separated list of port names. This com-
mand sets an untagged port-based VLAN and the VLAN table entry with the port’s default
VID. In this configuration, each port is assigned to one VLAN.
Definition: vlan add <vid1>=portlist1> <vid2>=<portlist2>…
vlan delete <vid1> <vid2>…
vlan show
Example: To create VLAN 1 on the core switch:
vlan add 1=14,15
To delete VLAN 1 on the core switch:
vlan delete 1
Management Processor Monitor: MPC8548 Environment
ATCA-9305 User’s Manual 10009109-01
9-26
MPC8548 ENVIRONMENT VARIABLES
Press the ‘s’ key on the keyboard during reset to force the default monitor environment vari-
ables to be loaded during hardware initialization but before diagnostic testing.
Table 9-6: Standard Environment Variables
Variable:
Default
Value: Description:
baudrate 115200 Console port baud rate
Valid rates: 9600, 14400, 19200, 38400, 57600, 115200
bmc_wd_timeout -1 This sets the time-out in seconds for the BMC watchdog
before booting the OS. If set to -1, then the BMC watchdog
is disabled before booting the OS.
Valid options: -1, 1-65535
bootcmd " " Command to execute when auto-booting or executing the
‘bootd’ command
bootdelay 1 Choose the number of seconds the Monitor counts down
before booting user application code
Valid options: time in seconds, -1 to disable autoboot
bootfile " " Path to boot file on server (used with TFTP)—set this to
“path/file.bin” to specify filename and location of the file to
load.
bootretry -1 Set the number of seconds the Monitor counts down before
booting user application code (used only with autoboot). If
the boot commands fails, it will try again after bootretry
seconds.
Valid options: time in seconds, -1 to disable bootretry
bootstopkey h Press during power-up/reset initialization to terminate the
monitor autoboot sequence and go to the monitor prompt.
clearmem on Select whether to clear unused SDRAM (memory used by
monitor is excluded) on power-up and reset.
Valid options: on, off
dcache on Enables the processor L1 data cache
Valid options: on, off
ecc on Enable ECC initialization—all of memory is cleared during
ECC initialization. Valid options: on, off
ecc_1bit_report off Select the reporting of single bit, correctable ECC errors to
the console (errors of 2 or more bits are always reported)
Valid options: on, off
ethaddr 00:80:F9:
97:00:00-
00:80:F9:
97:FF:FF
ATCA-9305 board Ethernet address for TSEC_1 port, the last
digits are the board serial number in hex.
Management Processor Monitor: MPC8548 Environment
10009109-01 ATCA-9305 User’s Manual 9-27
The monitor supports optional environment variables that enable additional functionality.
The moninit command (see “moninit” on page 9-22) clears all environment variables and
sets the standard environment variables to the default values. All optional environment vari-
ables are removed after moninit. However, it can clear all optional variables.
eth1addr 00:80:F9:
98:00:00-
00:80:F9:
98:FF:FF
ATCA-9305 board Ethernet address for TSEC_2 port, the last
digits are the board serial number in hex.
fru_id undefined Corresponds to ATCA-9305 processing resources
Valid options: Not defined in default configuration—
reported at bootup from the IPMC
gatewayip 0.0.0.0 Select the network gateway machine IP address
hostname EMERSON
_ATCA-
9305
Target hostname
icache on Enables the processor L1 instruction cache
Valid options: on, off
ipaddr 0.0.0.0 Board IP address
l2cache on Enables the L2 cache
Valid options: on, off
loadaddr 0x100000 Define the address to download user application code (used
with TFTP)
model ATCA-
9305
Board model number
ncip undefined Sets the IP address and the destination port, format is
<ip_addr>;<port>
netmask 0.0.0.0 Board sub-network mask
powerondiags on Turns POST diagnostics on or off after power-on/reset
Valid options: on, off
preboot undefined Command to execute immediately before starting the
CONFIG_BOOTDELAY countdown and/or running the auto-
boot command entering the interactive mode
rootpath eng/
emerson/
Path name of the NFS’ server root file system
serial# xxxxx Board serial number
serverip 0.0.0.0 Boot server IP address
tftp_port eTSEC_1 Selects which Ethernet port will be used for tftp
Valid options: eTSEC_1, eTSEC_2
Variable:
Default
Value: Description: (continued)
Management Processor Monitor: Troubleshooting
ATCA-9305 User’s Manual 10009109-01
9-28
Table 9-7: Optional Environment Variables
TROUBLESHOOTING
To bypass the full board initialization sequence, attach a terminal to the console located on
the front of the ATCA-9305. Configure the terminal parameters to be:
9600 bps, no parity, 8 data bits, 1 stop bit
Reset the ATCA-9305 while holding down the ‘s’ key. Pressing the ‘s’ key forces a configura-
tion based on default environment variables.
DOWNLOAD FORMATS
The ATCA-9305 monitor supports binary and Motorola® S-Record download formats, as
described in the following sections.
Variable1:
1. The moninit command does not initialize these variables. Each parameter is only defined if a change
from the default setting is desired and is not defined after initialization of the environment variables.
Description:
app_lock_base Assigns where to start block lock protection at the base of NOR (soldered) flash.
If assigned region does not fall within the NOR flash area, no user/application
locking will occur, except for the monitor block-locking protection.
app_lock_size Size of user NOR (soldered) flash protection area.
bootverifycmd Sets the U-Boot boot command that is used to execute the primary and
secondary application images when using the bootv command. If not defined,
bootv uses the U-Boot go command as the default.
carrier_num This is a slot within a shelf defined by the zone 1 hardware address
corresponding to the logical slot address.
e_keying Determines whether switch ports should be configured.
pci_memsize Sets the amount of SDRAM memory made available on the PCI bus. The
minimum setting is 16 megabytes. If not set, 128 MB of SDRAM are available
over PCI. This parameter takes a hex value.
Valid options: all, size in hex (0x8000000=128 MB)
pram This memory region is at the very top of memory and can be reserved—not to be
cleared on start-up or reset. Default size of the protected memory region is 0.
pram is defined in kilobytes and is a base 10 number. The smallest allowable size
is 4 (4 KB) and the largest recommended size is 32768 (32 MB). pram should be 4
KB aligned, otherwise U-Boot will round pram to the next 4 KB size.
sec_bootargs Sets the boot arguments that are passed into the secondary application images
when using the bootv command. If not defined, bootv will pass the bootargs
configuration parameters into both the primary and secondary application
images.
shelf_addr ATCA chassis shelf address provided by shelf-manager
Not defined in default configuration—reported at bootup from the IPMC
Management Processor Monitor: Download Formats
10009109-01 ATCA-9305 User’s Manual 9-29
Binary
The binary formats (and associated commands) include:
• Executable binary files (go)
•VxWorks and QNX
® ELF (bootm, bootvx, or bootelf)
• Compressed (gzipped) VxWorks and QNX ELF (bootm)
• Linux kernel images (bootm)
• Compressed (gzipped) Linux kernel images (bootm)
Motorola S-Record
S-Record download uses the standard Motorola S-Record format. This includes load
address, section size, and checksum all embedded in an ASCII file.
ATCA-9305 User’s Manual 10009109-01
9-30
(blank page)
10009109-01 ATCA-9305 User’s Manual 10-1
Section 10
Acronyms
AMC Advanced Mezzanine Card
ASCII American Standard Code for Information Interchange
ATCA Advanced Telecom Computing Architecture or AdvancedTCA
BMC Baseboard Management Controller
CIO Common I/O (RLDRAM)
Cmd Command code
CPU Central Processing Unit
CRC Cyclic Redundancy Code
CSA Canadian Standards Association
DDR Double Data Rate
EC European Community
ECC Error-correcting Code
EIA Electronic Industries Alliance
EMC Electromagnetic Compatibility
ESD Electrostatic Discharge
ETSI European Telecommunications Standards Institute
EXP Extreme Processor
FCC Federal Communications Commission
FRU Field Replaceable Unit
GbE Gigabit Ethernet
GNU GNU’s Not Unix
GPL General Public License
I2CInter-integrated Circuit
IEC International Electrotechnical Commission
IPMB Intelligent Platform Management Bus
IPMI Intelligent Platform Management Interface
ISP In-system Programmable
ITP In-target Probe
JTAG Joint Test Action Group
KCS Keyboard Controller Style
LED Light-emitting Diode
LPC Low Pin Count
LUN Logical Unit Number
MAC Medium/media Access Control/controller
NEBS Network Equipment-Building System
netFn Network Function Code
NSP Network Services Processor
Acronyms: (continued)
ATCA-9305 User’s Manual 10009109-01
10-2
OEM Original Equipment Manufacturer
PCI Peripheral Component Interconnect
PCIe PCI Express
PHY Physical Interface
PLD Programmable Logic Device
POST Power-on Self Test
RLDRAM Reduced Latency Dynamic Random Access Memory
RMA Return Merchandise Authorization
SCP Secure Communications Processor
SDR Sensor Data Record
SDRAM Synchronous Dynamic Random Access Memory
SEL System Event Log
SERDES Serializer/deserializer
SIO Separate I/O (RLDRAM)
SO-CDIMM Small-outline Clocked Dual In-line Memory
SPI-4.2 System Packet Interface level 4 phase 2
SROM Serial Read Only Memory
TBD To Be Determined
UART Universal Asynchronous Receiver/transmitter
UL Underwriters Laboratories
USB Universal Serial Bus
VLP Very Low Profile
XAUI 10 Gigabit Attachment Unit Interface
10009109-01 ATCA-9305 User’s Manual i-1
Index
A
air flow rate . . . . . . . . . . . . . . . . . . . 2-9
B
binary download format . . . . . . . .9-29
block diagram
Ethernet switching Interface . . . 6-2
general system . . . . . . . . . . . . . . 1-3
boot commands, monitor . . . . . . . 9-8
boot redirection
control diagram . . . . . . . . . . . .7-42
flow diagram. . . . . . . . . . . . . . .7-42
C
caution statements
front panel EMI . . . . . . . . . . . . . . 2-2
hot swap . . . . . . . . . . . . . . . . . .2-11
over-clocking Cavium. . . . . . . .5-11
static protection . . . . . . . . . . . . . 2-1
writes to monitor area . . . . . . . . 9-5
Cavium complexes
boot over PCI . . . . . . . . . . . . . . . 3-3
CN5860 features. . . . . . . . . . . . . 3-1
console ports . . . . . . . . . . . . . .3-15
COP/JTAG headers . . . . . . . . . .3-14
environment variables . . . . . . . . 3-8
memory . . . . . . . . . . . . . . . . . . . 3-9
memory map . . . . . . . . . . . . . . . 3-2
PLD registers. . . . . . . . . . . . . . .3-10
POST diagnostic results . . . . . . . 3-7
power-up sequence . . . . . . . . . . 3-6
reset diagram . . . . . . . . . . . . . . . 3-4
SPI-4.2 interconnect . . . . . . . . .3-10
start-up display. . . . . . . . . . . . . . 3-6
circuit board dimensions . . . . . . . . 2-1
comments and suggestions . . . . .2-13
compliance . . . . . . . . . . . . . . . . . . . 1-4
component map
bottom . . . . . . . . . . . . . . . . . . . . 2-4
top . . . . . . . . . . . . . . . . . . . . . . . 2-3
connectors
back panel zones 1-3 . . . . . . . . . 8-1
front panel . . . . . . . . . . . . . . . . . 2-2
J23. . . . . . . . . . . . . . . . . . . . . . . . 8-2
J30, J31, J33. . . . . . . . . . . . . . . . . 8-3
overview . . . . . . . . . . . . . . . . . . . 2-7
P10 . . . . . . . . . . . . . . . . . . . . . . . 8-1
contents, table of . . . . . . . . . . . . . . ii-v
E
E-keying . . . . . . . . . . . . . . . . . . . . . 9-1
environment parameter commands,
monitor. . . . . . . . . . . . . . . . . . . . . 9-19
environment variables . . . . . . . . . . 9-6
equipment for setup. . . . . . . . . . . . 2-8
ESD prevention. . . . . . . . . . . . . . . . 2-1
Ethernet
address . . . . . . . . . . . . . . . . 3-5, 6-3
RJ45 connectors . . . . . . . . . . . . . 6-4
F
features
components . . . . . . . . . . . . . . . . 1-1
general . . . . . . . . . . . . . . . . . . . . 1-1
IPMI . . . . . . . . . . . . . . . . . . . . . . 7-1
figures, list of . . . . . . . . . . . . . . . . iii-ix
file load commands, monitor . . . . 9-11
flash
commands, monitor . . . . . . . . 9-14
management devices. . . . . . . . . 4-7
front panel . . . . . . . . . . . . . . . . . . . 2-2
G
glossary of acronyms . . . . . . . . . . 10-1
grounding. . . . . . . . . . . . . . . . . . . . 2-1
H
Hot Swap . . . . . . . . . . . . . . . . . . . 2-10
I
I2C addresses . . . . . . . . . . . . . . . . . 4-9
installation of the board . . . . . . . . . 2-8
IPMI
completion codes. . . . . . . . . . . . 7-4
E-keying information . . . . . . . . 7-51
entity IDs and instances . . . . . . 7-46
event messages . . . . . . . . . . . . 7-49
FRU information . . . . . . . . . . . . 7-50
message bridging. . . . . . . . . . . . 7-7
network function codes . . . . . . . 7-2
request/response messages. . . . 7-5
sensors and data records . . . . . 7-48
SIPL protocol . . . . . . . . . . . . . . . 7-6
standard commands . . . . . . . . . 7-9
vendor commands . . . . . . . . . . 7-24
L
LEDs
Ethernet ports . . . . . . . . . . . . . . 6-4
front panel . . . . . . . . . . . . . . . . . 2-2
FRU/IPMC . . . . . . . . . . . . . . . . . 7-18
IPMI status . . . . . . . . . . . . . 2-5, 2-6
M
management complex
chip select . . . . . . . . . . . . . . . . . 4-5
console port . . . . . . . . . . . . . . . 4-10
I2C interface. . . . . . . . . . . . . . . . 4-9
JTAG/COP interface . . . . . . . . . . 4-9
memory devices. . . . . . . . . . . . . 4-7
memory map . . . . . . . . . . . . . . . 4-2
MPC8548 features . . . . . . . . . . . 4-2
PCI bus . . . . . . . . . . . . . . . . . . . . 4-8
PLD register summary . . . . . . . . 5-1
reset diagram. . . . . . . . . . . . . . . 4-6
mean time between failures (MTBF)1-4
memory
Cavium complex . . . . . . . . . . . . 3-9
commands, monitor . . . . . . . . 9-11
management complex. . . . . . . . 4-7
memory map
Cavium. . . . . . . . . . . . . . . . . . . . 3-2
Cavium NVRAM . . . . . . . . . . . . 3-10
MPC8548 . . . . . . . . . . . . . . . . . . 4-2
MPC8548 NVRAM . . . . . . . . . . . 4-9
monitor
auto-booting . . . . . . . . . . . . . . . 9-1
auto-repeat . . . . . . . . . . . . . . . . 9-1
basic operation . . . . . . . . . . . . . 9-3
boot commands. . . . . . . . . . . . . 9-8
command history. . . . . . . . . . . . 9-1
command reference . . . . . . . . . 9-7
command syntax . . . . . . . . . . . . 9-7
command-line interface . . . . . . 9-1
environment parameter commands
9-19
environment variables . . . 3-8, 9-26
file load commands . . . . . . . . . 9-11
flash commands. . . . . . . . . . . . 9-14
flash programming . . . . . . . . . . 9-1
memory commands. . . . . . . . . 9-11
Motorola S-record . . . . . . . . . . 9-29
other commands . . . . . . . . . . . 9-20
POST diagnostic results . . . . . . . 9-4
power-up/reset sequence . 3-7, 9-4
recovery . . . . . . . . . . . . . . . . . . . 9-5
Index (continued)
ATCA-9305 User’s Manual 10009109-01
i-2
start-up display. . . . . . . . . . 3-6, 9-2
test commands. . . . . . . . . . . . .9-20
TFTP booting . . . . . . . . . . . . . . . 9-1
troubleshooting . . . . . . . . . . . .9-28
typographic conventions . . . . . . 9-8
U-Boot . . . . . . . . . . . . . . . . . . . . 9-1
updates. . . . . . . . . . . . . . . . . . . . 9-6
monitor commands
autoscr . . . . . . . . . . . . . . . . . . .9-20
base . . . . . . . . . . . . . . . . . . . . .9-20
bdinfo . . . . . . . . . . . . . . . . . . . .9-21
bootd . . . . . . . . . . . . . . . . . . . . . 9-8
bootdev . . . . . . . . . . . . . . . . . .9-17
bootelf . . . . . . . . . . . . . . . . . . . . 9-8
bootm. . . . . . . . . . . . . . . . . . . . . 9-8
bootp . . . . . . . . . . . . . . . . . . . . . 9-8
bootv . . . . . . . . . . . . . . . . . . . . . 9-9
bootvx. . . . . . . . . . . . . . . . . . . . . 9-9
cmp. . . . . . . . . . . . . . . . . . . . . .9-12
coninfo . . . . . . . . . . . . . . . . . . .9-21
cp . . . . . . . . . . . . . . . . . 9-12, 9-14
crc32. . . . . . . . . . . . . . . . . . . . .9-21
date . . . . . . . . . . . . . . . . . . . . .9-21
dhcp . . . . . . . . . . . . . . . . . . . . . . 9-9
diags . . . . . . . . . . . . . . . . . . . . .9-20
echo . . . . . . . . . . . . . . . . . . . . .9-21
eeprom . . . . . . . . . . . . . . . . . . .9-15
enumpci . . . . . . . . . . . . . . . . . .9-21
erase . . . . . . . . . . . . . . . . . . . . .9-14
find . . . . . . . . . . . . . . . . . . . . . .9-12
flinfo . . . . . . . . . . . . . . . . . . . . .9-14
fru . . . . . . . . . . . . . . . . . . . . . . .9-17
fruinit . . . . . . . . . . . . . . . . . . . .9-18
fruled . . . . . . . . . . . . . . . . . . . .9-18
go . . . . . . . . . . . . . . . . . . . . . . .9-21
help. . . . . . . . . . . . . . . . . .9-8, 9-22
icrc32 . . . . . . . . . . . . . . . . . . . .9-16
iloop . . . . . . . . . . . . . . . . . . . . .9-16
imd . . . . . . . . . . . . . . . . . . . . . .9-16
iminfo . . . . . . . . . . . . . . . . . . . .9-22
imm . . . . . . . . . . . . . . . . . . . . .9-16
imw. . . . . . . . . . . . . . . . . . . . . .9-16
inm . . . . . . . . . . . . . . . . . . . . . .9-16
ipmchpmfw . . . . . . . . . . . . . . .9-18
iprobe . . . . . . . . . . . . . . . . . . . .9-17
isdram. . . . . . . . . . . . . . . . . . . .9-22
loadb. . . . . . . . . . . . . . . . . . . . .9-11
loads . . . . . . . . . . . . . . . . . . . . .9-11
loop. . . . . . . . . . . . . . . . . . . . . .9-22
md . . . . . . . . . . . . . . . . . . . . . .9-12
memmap . . . . . . . . . . . . . . . . .9-22
mm . . . . . . . . . . . . . . . . . . . . . .9-13
moninit. . . . . . . . . . . . . . . . . . . 9-22
mtest . . . . . . . . . . . . . . . . . . . . 9-20
mw . . . . . . . . . . . . . . . . . . . . . . 9-13
nm . . . . . . . . . . . . . . . . . . . . . . 9-13
pci. . . . . . . . . . . . . . . . . . . . . . . 9-23
phy . . . . . . . . . . . . . . . . . . . . . . 9-23
ping . . . . . . . . . . . . . . . . . . . . . 9-24
printenv . . . . . . . . . . . . . . . . . . 9-19
protect . . . . . . . . . . . . . . . . . . . 9-15
rarpboot . . . . . . . . . . . . . . . . . . 9-10
reset . . . . . . . . . . . . . . . . . . . . . 9-24
run . . . . . . . . . . . . . . . . . . . . . . 9-24
saveenv . . . . . . . . . . . . . . . . . . 9-19
script . . . . . . . . . . . . . . . . . . . . 9-24
sensor. . . . . . . . . . . . . . . . . . . . 9-18
setenv. . . . . . . . . . . . . . . . . . . . 9-19
showmac . . . . . . . . . . . . . . . . . 9-24
showpci . . . . . . . . . . . . . . . . . . 9-24
sleep . . . . . . . . . . . . . . . . . . . . . 9-25
switch_reg . . . . . . . . . . . . . . . . 9-25
tftpboot . . . . . . . . . . . . . . . . . . 9-10
um . . . . . . . . . . . . . . . . . . . . . . 9-20
version . . . . . . . . . . . . . . . . . . . 9-25
vlan. . . . . . . . . . . . . . . . . . . . . . 9-25
N
notation conventions . . . . . . . . . . . 1-6
P
PCI
bus . . . . . . . . . . . . . . . . . . . . . . . 4-8
device interrupts and ID . . . . . . . 4-8
power requirements. . . . . . . . . . . . 2-9
product repair. . . . . . . . . . . . . . . . 2-12
programmable logic device (PLD) . 5-1
R
references and data books . . . . . . . 1-6
registers
Address 9-8 . . . . . . . . . . . . . . . 3-12
Address7-0 . . . . . . . . . . . . . . . . 3-12
CGCR . . . . . . . . . . . . . . . . . . . . 5-12
CGDI . . . . . . . . . . . . . . . . . . . . . 5-13
CGDO . . . . . . . . . . . . . . . . . . . . 5-13
CMUL1 . . . . . . . . . . . . . . . . . . . 5-11
Control . . . . . . . . . . . . . . . . . . . 3-12
Data 15-8 . . . . . . . . . . . . . . . . . 3-11
Data 23-16 . . . . . . . . . . . . . . . . 3-11
Data 31-24 . . . . . . . . . . . . . . . . 3-10
Data 7-0 . . . . . . . . . . . . . . . . . . 3-11
HCR0 . . . . . . . . . . . . . . . . . . . . . 5-3
HVR . . . . . . . . . . . . . . . . . . . . . . 5-2
IGCR . . . . . . . . . . . . . . . . . . . . . 5-14
JSR . . . . . . . . . . . . . . . . . . . . . . . 5-4
LEDR. . . . . . . . . . . . . . . . . . . . . . 5-4
LPC1 . . . . . . . . . . . . . . . . . . . . . 5-14
MISC. . . . . . . . . . . . . . . . . . . . . . 5-9
PIDR . . . . . . . . . . . . . . . . . . . . . . 5-2
PLLC . . . . . . . . . . . . . . . . . . . . . . 5-3
PVR. . . . . . . . . . . . . . . . . . . . . . . 5-3
RCR1 . . . . . . . . . . . . . . . . . . . . . 5-5
RCR2 . . . . . . . . . . . . . . . . . . . . . 5-6
RCR3 . . . . . . . . . . . . . . . . . . . . . 5-6
RCR4 . . . . . . . . . . . . . . . . . . . . . 5-7
RCR5 . . . . . . . . . . . . . . . . . . . . . 5-7
RCRS1. . . . . . . . . . . . . . . . . . . . . 5-7
RCRS2. . . . . . . . . . . . . . . . . . . . . 5-8
RER. . . . . . . . . . . . . . . . . . . . . . . 5-5
RGCR . . . . . . . . . . . . . . . . . . . . 5-10
RGSR . . . . . . . . . . . . . . . . . . . . 5-10
RTMS . . . . . . . . . . . . . . . . . . . . 5-10
Scratch . . . . . . . . . . . . . . . . . . . 3-13
SIRQI1 . . . . . . . . . . . . . . . . . . . 5-15
SIRQI2 . . . . . . . . . . . . . . . . . . . 5-15
Version. . . . . . . . . . . . . . . . . . . 3-13
regulatory certifications. . . . . . . . . 1-4
returning boards . . . . . . . . . . . . . 2-12
RoHS. . . . . . . . . . . . . . . . . . . . . . . . 1-5
S
setup requirements . . . . . . . . . . . . 2-8
specifications
environmental . . . . . . . . . . . . . . 2-9
mechanical. . . . . . . . . . . . . . . . . 2-1
power. . . . . . . . . . . . . . . . . . . . . 2-9
static control . . . . . . . . . . . . . . . . . 2-1
switches
Hot Swap . . . . . . . . . . . . . . . . . . 2-6
reset . . . . . . . . . . . . . . . . . . 2-5, 2-6
T
table of contents . . . . . . . . . . . . . . ii-v
tables, list of . . . . . . . . . . . . . . . . . .iv-xi
technical references. . . . . . . . . . . . 1-6
technical support . . . . . . . . . . . . . 2-11
terminology . . . . . . . . . . . . . . . . . . 1-6
test commands, monitor . . . . . . . 9-20
troubleshooting
general . . . . . . . . . . . . . . . . . . . 2-11
monitor . . . . . . . . . . . . . . . . . . 9-28
Index (continued)
10009109-01 ATCA-9305 User’s Manual i-3
U
UL certifications . . . . . . . . . . . . . . . 1-5
W
watchdog timer . . . . . . . . . . . . . . 7-12
watchdog, BMC . . . . . . . . .9-17, 9-26
Z
zone 1-3 connectors. . . . . . . . . . . . 8-1
ATCA-9305 User’s Manual 10009109-01
i-4
(blank page)
10009109-01 ATCA-9305 User’s Manual
Notes
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