Epson Rtc 4543Sa Users Manual

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MQ252-03

Application

Manual

Real Time Clock Module

RTC-4543SA/SB
Model

Product Number

RTC-4543SA

Q4145435x000200

RTC-4543SB

Q4145436x000200

In pursuit of "Saving" Technology ,Epson electronic device.
Our Lineup of semiconductors, Liquid crystal displays and quartz devices
assists in creating the products of our customers' dreams.
Epson IS energy savings.

NOTICE
• The material is subject to change without notice.
• Any part of this material may not be reproduced or duplicated in any form or any means without the
written permission of Seiko Epson.
• The information, applied circuit, program, using way etc., written in this material is just for reference.
Seiko Epson does not assume any liability for the occurrence of infringing any patent or copyright of third
party. This material does not authorize the licence for any patent or intellectual property rights.
• Any product described in this material may contain technology or the subject relating to strategic
products under the control of the Foreign Exchange and Foreign Trade Law of Japan and may require an
export licence from the Ministry of International Trade and industry or other approval from another
government agency.
• The products (except for some product for automotive applications) listed up on this material are designed
to be used with ordinary electronic equipment (OA equipment, AV equipment, communications equipment,
measuring instruments etc). Seiko Epson does not assume any liability for the case using the products with
the appoication required high reliability or safety extremely (such as aerospace equipment etc).
When intending to use any our product with automotive application and the other application than
ordinary electronic equipments as above, please contact our sales representatives in advance.

RTC - 4543 SA/SB
CONTENTS
1. OVERVIEW ........................................................................................................1
2. BLOCK DIAGRAM ...........................................................................................1
3. PIN CONNECTIONS.......................................................................................2
4. PIN FUNCTIONS..............................................................................................2
5. ELECTRICAL CHARACTERISTICS .........................................................3
5-1. ABSOLUTE MAXIMUM RATINGS ..........................................................................................3
5-2. OPERATING CONDITION .......................................................................................................3
5-3. FREQUENCY CHARACTERISTICS ........................................................................................3
5-4. DC CHARACTERISTICS ........................................................................................................3
5-5. AC CHARACTERISTICS.........................................................................................................4
5-6. TIMING CHARTS .....................................................................................................................5

6. TIMER DATA ORGANIZATION ..................................................................6
7. DESCRIPTION OF OPERATION...............................................................7
7-1.DATA READS ............................................................................................................................7
7-2. DATA WRITES .........................................................................................................................7
7-3. DATA WRITES (DIVIDER RESET).........................................................................................8
7-4. FOUT OUTPUT AND 1 HZ CARRIES ...................................................................................8

8. EXAMPLES OF EXTERNAL CIRCUITS .................................................9
9. EXTERNAL DIMENSIONS ......................................................................... 10
10. LAYOUT OF PACKAGE MARKINGS .................................................. 10
11. REFERENCE DATA ................................................................................... 11
12. APPLICATION NOTES.............................................................................. 12
12-1. NOTES ON HANDLING .......................................................................................................12
12-2. NOTES ON PACKAGING ....................................................................................................12

RTC - 4543 SA/SB
32-kHz Output Serial RTC Module

RTC - 4543 SA/SB
z Built-in crystal permits operation without requiring adjustment
z Built-in time counters (seconds, minutes, hours) and calendar counters (days, days of the week

months, years)
z Operating voltage range: 2.5 V to 5.5 V
z Supply voltage detection voltage: 1.7 ±0.3 V
z Low current consumption: 1.0 µA/2.0 V (Max.)
z Automatic processing for leap years
z Output selectable between 32.768 kHz/1 Hz

1. Overview
This module is a real-time clock with a serial interface and a built-in crystal oscillator. This module
is also equipped with clock and calendar circuits, an automatic leap year compensation function,
and a supply voltage detection function.
In addition, this module has a 32.768 kHz/1 Hz selectable output function for hardware control that
is independent of the RTC circuit.
This module is available in a compact SOP 14-pin package (RTC-4543SA) and a thin SOP 18-pin
package (RTC-4543SB).

2. Block diagram
32.768 kHz

OSC

FOUT
FSEL

CLOCK

DIVIDER

AND

CALENDAR

OUTPUT
CONTROLLER

SHIFT REGISTER

FOE
VOLTAGE

DATA
CLK
WR
CE

I/O

DETECT
CONTROL

CONTROLLER

CIRCUIT

Page - 1

MQ - 252 - 03

RTC - 4543 SA/SB
3. Pin Connections
RTC - 4543SA
1 GND
2 N.C

RTC - 4543SB
14 FOUT

1

3 CE

12 N.C

4 FSEL

11 DATA

5 WR

10 CLK

6 FOE

7

1
2
3
4
5
6
7
8
9

13 N.C

14

9 V DD

8

8 N.C

7 N.C

SOP - 14pin

N.C
N.C
N.C
N.C
FOE
WR
FSEL
CE
GND

1

18

9

10

18 N.C
17 N.C
16 N.C
15 N.C
14 V DD
13 N.C
12 CLK
11 DATA
10 FOUT

SOP - 18pin

4. Pin Functions
Pin No.
Signal
GND

SOP-14pin
(SOP-18pin)

I/O

1
(9)

Connects to negative (-) side (ground) of the power supply.

3
(8)

Input

FSEL

4
(7)

Input

WR

5
(6)

Input

FOE

6
(5)

Input

VDD

9
( 14 )

CLK

10
( 12 )

DATA

11
( 11 )

FOUT

14
( 10 )

N.C.

2,7,8,12,13
( 1,2,3,4,13,
15,16,17,18 )

CE

Function

Chip enable input pin.
When high,the chip is enabled. When low,the DATA pin goes to
high impedance and the CLK,DATA,and WR pins are not able to
accept input.In addition, when low,the TM bit is cleared.
Serect the frequency that is output from the FOUT pin.
High : 1 Hz
Low : 32.768 kHz
DATA pin input/output switching pin.
High : DATA input (when writing the RTC)
Low : DATA output (when reading the RTC)
When high, the frequency selected by the FSEL pin is output from
the FOUT pin.
When low, the FOUT pin goes to high impedance.
Connects to positive (+) side of the power supply.

Input

Serial clock input pin.
Data is gotten at the rising edge during a write, and data is output
at the rising edge during a read.

Bi-directional Input/outout pin that is used for writing and reading data.
Output

Outputs the frequency selected by the FSEL pin. 1 Hz output is
synchronized with the internal one-second signal.
This output is not affected by the CE pin.
Although these pins are not connected internally,they should
always be left open in order to obtain the most stable oscillation
possible.

* Always connect a passthrough capacitor of at least 0.1 µF as close as possible between VDD and GND.

Page - 2

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RTC - 4543 SA/SB
5. Electrical Characteristics
5-1. Absolute Maximum Ratings
Item
Supply voltage
Input voltage
Output voltage
Storage temperature

Symbol
VDD
VI
VO
TSTG

Conditions

-

Min.
-0.3
GND-0.3
GND-0.3
-55

Max.
7.0
VDD+0.3
VDD+0.3
+125

Unit
V
V
V
°C

Ta=+25 °C

Symbol

Conditions

Min.

Max.

Unit

VDD

-

2.5

5.5

V

VCLK
TOPR

-

1.4
-40

5.5
+85

V
°C

Max.

Unit

5 ± 23 *

×10

5-2. Operating Condition
Item
Operating supply
voltage
Data holding voltage
Operating temperature

No condensation

5-3. Frequency Characteristics
Item

Symbol

Frequency tolerance
∆f/fO
Frequency temperature
Top
characteristics
Frequency voltage
f/V
characteristics
Oscillation start time
tSTA
Aging
fa
* Monthly deviation: Approx. 1 min.

Conditions
Ta=+25 °C , VDD=5.0 V
-10to+70 °C

+25 °C ref

-6

+ 10 / - 120

×10

Ta=+25 °C , VDD=2.0 to 5.5 V

±2

×10 /V

Ta=+25 °C , VDD=2.5 V
Ta=+25 °C , VDD=5 V , first year

3
±5

s
-6
×10

-6

-6

5-4. DC Characteristics
Item

Symbol

Current consumption(1)
Current consumption(2)
Current consumption(3)
Current consumption(4)
Current consumption(5)

IDD1
IDD2
IDD3
IDD4
IDD5

Current consumption(6)

IDD6

Input voltage

VIH
VIL

Input off/leak current
Output voltage

Output load condition
( fanout )

Output leak current
Supply voltage detection
voltage

IOFF

Unless specified otherwise: VDD = 5 V ± 10 %, Ta = - 40 to +85 °C
Conditions
Min.
Typ.
Max.
Unit
VDD=5.0 V
VDD=3.0 V
VDD=2.0 V
VDD=5.0 V
VDD=3.0 V

CE=L , FOE=L
FSEL=H
CE=L , FOE=H

FSEL=L
No load on the
VDD=2.0 V
FOUT pin
WR,DATA,CE,CLK,
FOE,FSEL pins
WR,CE,CLK,FOE,FSEL pins
VIN = VDD or GND

3.0
2.0
1.0
10.0
6.5

µA
µA
µA
µA
µA

1.5

4.0

µA

0.2 VDD

V
V

0.5

µA

0.5
0.8

V
V
V
V

0.8 VDD

VOH(1)
VOH(2)
VOL(1)
VOL(2)

VDD=5.0 V
IOH=-1.0 mA
DATA
, FOUT pins
VDD=3.0 V
VDD=5.0 V
IOL= 1.0 mA
VDD=3.0 V DATA , FOUT pins

N / CL

FOUT pin

IOZH
IOZL

VOUT=5.5 V DATA , FOUT pins
VOUT=0 V DATA , FOUT pins

-1.0
-1.0

VDT

-

1.4

Page - 3

1.5
1.0
0.5
4.0
2.5

4.5
2.0

2 LSTTL / 30 pF Max.

1.7

1.0
1.0

µA
µA

2.0

V

MQ - 252 - 03

RTC - 4543 SA/SB
5-5. AC Characteristics
Unless specified otherwise: Ta = - 40 to +85 °C, CL = 50 pF
Unit
Symbol
VDD=3 V ± 10 %
VDD=5 V ± 10 %

Item

Min.

Max.

Min.

Max.

CLK clock cycle
CLK low pulse width

tCLK
tCLKL

0.75
0.375

7800
3900

1.5
0.75

7800
3900

µs
µs

CLK high pulse width

tCLKH

0.375

3900

0.75

3900

µs

CLK setup time

tCLKS

25

CE setup time

tCES

0.375

CE hold time

tCEH

0.375

CE enable time

tCE

Write data setup time

tSD

0.1

0.2

µs

Write data hold time

tHD

0.1

0.1

µs

WR setup time

tWRS

100

100

ns

WR hold time

tWRH

100

100

ns

DATA output delay time

tDATD

0.2

0.4

µs

DATA output floating time

tDZ

0.1

0.2

µs

Clock input rise time

tr1

50

100

ns

Clock input fall time

tf1

50

100

ns

50
3900

0.75

ns
3900

0.9

µs
µs

0.75
0.9

s

FOUT rise time

(CL=30 pF)

tr2

100

200

ns

FOUT fall time

(CL=30 pF)

tf2

100

200

ns

Disable time

(CL=30 pF)

tXZ

100

200

ns

Enable time

(CL=30 pF)

tZX

100

200

ns

60

%

FOUT duty ratio (CL=30 pF)

Duty

40

Wait time

tRCV

0.95

Page - 4

60

40
1.9

µs

MQ - 252 - 03

RTC - 4543 SA/SB
5-6. Timing Charts
( 1 ) Data read
tCE

WR
tWRS

tWRH

CE
t CES

tCLK

tCEH
tRCV

CLK
tCLKS

t CLKH

tCLKL

tr1

tDZ

tf1

DATA
tDATD

( 2 ) Data write
tCE

WR
tWRS

tWRH

CE
tCES

tCEH tRCV

tCLK

CLK
tCLKH
tCLKS

tSD

tCLKL
tr1

tHD

tf1

DATA

( 3 ) FOUT output
tH

tf2
90%

FOUT

50%
10%

tr2
t

tH
× 100
Duty =
t

[%]

( 4 ) Disable/enable
VIH

FOE
VIL

Enable

Disable

tXZ

tZX
High impedance

FOUT

Page - 5

MQ - 252 - 03

RTC - 4543 SA/SB
6. Timer Data Organization
• The counter data is BCD code.
• The timer automatically adjusts for different month lengths and for leap year.
• The time is indicated in 24-hour format.
• Writes and reads are both performed on an LSB-first basis.
MSB

LSB

Second
( 0 to 59 )

FDT

s40

s20

s10

s8

s4

s2

s1

Minutes
( 0 to 59 )

*

mi40

mi20

mi10

mi8

mi4

mi2

mi1

*

*

h20

h10

h8

h4

h2

h1

*

w4

w2

w1

Hour ( 0 to 23 )

Day of the week
( 1 to 7 )
Day ( 1 to 31 )

Month ( 1 to 12 )

Year ( 0 to 99 )

*

*

d20

d10

d8

d4

d2

d1

TM

*

*

mo10

mo8

mo4

mo2

mo1

y80

y40

y20

y10

y8

y4

y2

y1

* bits: Any data may be written to these bits.

• FDT bit: Supply voltage detection bit
• This bit is set to “1” when voltage of 1.7 ±0.3 V or less is detected between VDD and GND.
• The FDT bit is cleared if all of the digits up to the year digits are read.
• Although this bit can be both read and written, normally set this bit to “0”.
V DD

VDET
0.5 s

0.5 s

Detection
pulse
Mode

Read

FDT bit

The supply voltage detection circuit monitors the supply voltage once every 0.5 seconds;
if the supply voltage is lower than the detection voltage value, the FDT bit is set to “1”.

• TM bit: This is a test bit for SEIKO-EPSON’s use.

Page - 6

Always set this bit to “0”.

MQ - 252 - 03

RTC - 4543 SA/SB
7. Description of Operation
7-1.Data reads
1

2

52

53

54

54+n

CLK
CE
WR
DATA

s1

s2

s4

s8 s10 s20 s40 FDT

y8 y10 y20 y40 y80
Year

Sec

Output data does not change

1)
2)
3)

4)

5)
6)
7)

When the WR pin is low and the CE pin is high, the RTC enters data output mode.
At the first rising edge of the CLK signal, the clock and calendar data are loaded into the shift
register and the LSB of the seconds digits is output from the DATA pin.
The remaining seconds, minutes, hour, day of the week, day, month, and year data is shifted out,
in sequence and in synchronization with the rising edge of the CLK signal, so that the data is
output from the DATA pin.
The output data is valid until the rising edge of the 52nd clock pulse; even if more than 52 clock
pulses are input, the output data does not change.
If data is required in less than 52 clock pulses, that part of the data can be gotten by setting the
CE pin low after the necessary number of clock pulses have been output.
Example: If only the data from “seconds” to “day of the week” is needed:
After 28 clock pulses, set the CE pin low in order to get the data from “seconds” to “day of
the week.”
When performing successive data read operations, a wait (tRCV) is necessary after the CE pin
is set low.
Note that if an update operation (a one-second carry) occurs during a data read operation,
the data that is read will have an error of -1 second.
Complete data read operations within tCE (Max.) = 0.9 seconds, as described earlier.

7-2. Data writes
1

2

s1

s2

52

53

54

54+n

CLK
CE
WR
DATA

s4

s8 s10 s20 s40

0

y8 y10 y20 y40 y80

( FDT )

Seconds

1)
2)
3)
4)
5)

6)
7)

Year

When the WR pin is high and the CE pin is high, the RTC enters data input mode.
In this mode, data is input, in succession and in synchronization with the rising edge of the CLK
signal, to the shift register from the DATA pin, starting from the LSB of the seconds digits.
The sub-seconds counter is reset between the falling edge of the first clock pulse and the rising
edge of the second clock pulse. In addition, carries to the seconds counter are prohibited at the
falling edge of the first clock pulse.
After the last data is input to the shift register at the rising edge of the 52nd clock pulse, the
contents of the shift register are transferred to the timer counter.
Note that during a data write operation, 52 bits of data must be input.
• Correct write-access isn't completed when CE terminal turned into low on a state of less
than 52 bits.
• If more than 52 bits of data are input, the 53rd and subsequent bits are ignored.
(The first 52 bits of data are valid.)
Once the CE pin is set low, the prohibition on carries to the seconds counter is lifted.
Complete data write operations within tCE (Max.) = 0.9 seconds, as described earlier.
If a data read operation is to be performed immediately after a data write operation, a wait (tRCV)
is necessary after the CE pin is set low.

* Malfunction will result if illegal data is written.

Therefore, be certain to write legal data.

Page - 7

MQ - 252 - 03

RTC - 4543 SA/SB
7-3. Data writes (Divider Reset)
CE

WR
1

2

52

CLK

N Seconds
DATA

s1 s2

s4

s8 s10 s20 s40

Timer,counter N seconds

y8 y10 y20 y40 y80

0 seconds

N seconds

Divider reset
Pulse
Carry stop
Pulse

After the counter is reset, carries to the seconds digit are halted.After the data write operation,
the prohibition on carries to the seconds counter is lifted by setting the CE pin low.
Complete data write operations within tCE (Max.) = 0.9 seconds, as described earlier.

7-4. FOUT output and 1 Hz carries
CE
WR
tCES

CLK
1.0 s

1Hz

0
-7.8 ms

tCLK

FOUT
15.6 ms

15.6 ms

During a data write operation, because a reset is applied to the Devider counter (from the 128 Hz
level to the 1 Hz level) after the CE pin goes high during the time between the falling edge of the first
clock cycle and the rising edge of the second clock cycle, the length of the first 1 Hz cycle after the
data write operation is 1.0 s

+0 / −7.8ms

+tCES+tCLK. Subsequent cycles are output at 1.0-second intervals.

The 1-Hz signal that is output on FOUT is the internal 1-Hz signal with a 15.6-ms shift applied.

Page - 8

MQ - 252 - 03

RTC - 4543 SA/SB
8. Examples of External Circuits
• Example 1. When used as an RTC + clock source
VDD
Power supply
Switching circuit

VDD

RTC 4543

Power supply
Detection circuit

VDD
CE
WR
DATA

0.1 µF

CLK
FOUT
*1

FSEL

*2

FOE
GND

*1: FOUT output frequency setting (High: 1 Hz; low: 32.768 kHz)
*2: Prohibits FOUT output during back up, reducing current consumption.

• Example 2. When used as a clock source (oscillator)

VDD

RTC-4543
VDD
CE
VDD

VDD

WR
DATA

0.1 µF

CLK
FOUT

∗1

FSEL
FOE
GND

Page - 9

MQ - 252 - 03

RTC - 4543 SA/SB
9. External Dimensions
RTC - 4543 SA ( SOP-14pin )
10.1 ± 0.2

0.35
∗

1.27

5.0

7.4 ± 0.2

0.05
Min.

3.2 ± 0.1

0.15
0 - 10°

1.2

0.6

The cylinder of the crystal oscillator can be seen in this area ( front ),
but it has no affect on the performance of the device.

RTC - 4543 SB ( SOP-18pin )
11.4 ± 0.2

5.4

7.8 ± 0.2

0.15

1.8 2.0
Max.
0.4

1.27

0 Min.
0 - 10

0.12

0.6 ± 0.2

0.1

10. Layout of Package Markings
RTC - 4543 SA

Model

Frequency
torerance

( SOP-14pin )

R4543 B
E 1234A
Manufacturing
Lot

RTC - 4543 SB

Model

Frequency
tolerance

( SOP-18pin )

R4543 B
E 1234A
Manufacturing
Lot

Note :
The markings and their positions as pictured above are only approximations.
These illustrations do not define the details of the style, size, and position of the characters marked on the packages.

Page - 10

MQ - 252 - 03

RTC - 4543 SA/SB
11. Reference Data
(1) Example of Frequency-Temperature Characteristics
θT = +25 °C Typ.

Determining the frequency stability (clock accuracy)

Frequency ∆ fT

α = -0.035 × 10-6/ °C 2 Typ.
1.The frequency-temperature characteristics can be

× 10-6
+10
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150

approximated by the following equation:
∆fT = α(θT-θX)2
∆fT
α( /°C2)
θT(°C)
θX(°C)

: Frequency deviation at any given temperature
: Second-order temperature
((-0.035±0.005)×10-6/°C2)
: Highest temperature(+25 °C±5 °C)
: Any given temperature

2. In order to determine the clock accuracy, add in the
frequency tolerance and the voltage characteristics.

-50 -40 -30 -20 -10

0

+10 +20 +30 +40 +50 +60 +70 +80 +90+100

Temperature [°C]

∆f/f = ∆f/f0 + ∆fT + ∆fv
∆f /f

: Clock accuracy at any given temperature
and voltage (frequency stability)

∆f/f 0
∆f T
∆f v

: Frequency accuracy
: Frequency deviation at any given temperature
: Frequency deviation at any given voltage

3. Determining the daily error
Daily error =∆f/f × 86400 (seconds)
With error of 11.574 × 10-6, the error of the clock is
about one second per day.

(2)Example of Frequency-Voltage

(3)Example of Current Consumption-Voltage

Characteristics

Characteristics
Current consumpiton[ µA ]

Frequency [ ×10-6 ]

Conditions
Conditions
+1.0

No load, Ta=+25 °C

5 V reference Voltage,
Ta=+25 °C

2.0

0.0
2

3

4

5

-1.0
-2.0

1.0
Supply voltage (VDD)[V]

0.0

2.0

3.0

4.0

5.0

Supply voltage (VDD) [V]

Note : This data shows values obtained from a sample lot.

Page - 11

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RTC - 4543 SA/SB
12. Application notes
12-1. Notes on handling
This module uses a C-MOS IC to realize low power consumption. Carefully note the following cautions when
handling.
(1) Static electricity
While this module has built-in circuitry designed to protect it against electrostatic discharge, the chip
could still be damaged by a large discharge of static electricity. Containers used for packing and
transport should be constructed of conductive materials. In addition, only soldering irons, measurement
circuits, and other such devices which do not leak high voltage should be used with this module, which
should also be grounded when such devices are being used.
(2) Noise
If a signal with excessive external noise is applied to the power supply or input pins, the device may
malfunction or "latch up." In order to ensure stable operation, connect a filter capacitor (preferably
ceramic) of greater that 0.1F as close as possible to the power supply pins (between VDD and GNDs).
Also, avoid placing any device that generates high level of electronic noise near this module.
* Do not connect signal lines to the shaded area in the figure shown in Fig. 1 and, if possible, embed
this area in a GND land.
(3) Voltage levels of input pins
When the input pins are at the mid-level, this will cause increased current consumption and a reduced
noise margin, and can impair the functioning of the device. Therefore, try as much as possible to apply
the voltage level close to VDD or GND.
(4) Handling of unused pins
Since the input impedance of the input pins is extremely high, operating the device with these pins in
the open circuit state can lead to unstable voltage level and malfunctions due to noise. Therefore, pullup or pull-down resistors should be provided for all unused input pins.

12-2. Notes on packaging
(1) Soldering heat resistance.
If the temperature within the package exceeds 260, the characteristics of the crystal oscillator will be
degraded and it may be damaged. The reflow conditions within our reflow profile is recommended.
Therefore, always check the mounting temperature and time before mounting this device. Also, check
again if the mounting conditions are later changed.
* See Fig. 2 profile for our evaluation of Soldering heat resistance for reference.
(2) Mounting equipment
While this module can be used with general-purpose mounting equipment, the internal crystal oscillator
may be damaged in some circumstances, depending on the equipment and conditions. Therefore, be
sure to check this. In addition, if the mounting conditions are later changed, the same check should be
performed again.
(3) Ultrasonic cleaning
Depending on the usage conditions, there is a possibility that the crystal oscillator will be damaged by
resonance during ultrasonic cleaning. Since the conditions under which ultrasonic cleaning is carried
out (the type of cleaner, power level, time, state of the inside of the cleaning vessel, etc.) vary widely,
this device is not warranted against damage during ultrasonic cleaning.
(4) Mounting orientation
This device can be damaged if it is mounted in the wrong orientation. Always confirm the orientation of
the device before mounting.
(5) Leakage between pins
Leakage between pins may occur if the power is turned on while the device has condensation or dirt on
it. Make sure the device is dry and clean before supplying power to it.
Fig. 1: Example GND Pattern
RTC - 4543 SA

( SOP-14pin )

Fig. 2: Reference profile for our evaluation of Soldering heat resistance.
Temperature [ °C ]
+260 °C Max.

−1 ∼ −5 °C / s
+1 ∼ +5 °C / s

RTC - 4543 SB

( SOP-18pin )

+1 ∼ +5 °C / s

+170 °C
100 s

+220 °C
35 s

Pre-heating area

Stable Melting area

time [ s ]

Page - 12

MQ - 252 - 03

Application Manual
Distributor

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Gumi Branch Office

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Phone: (82) 2-784-6027 Fax: (82) 2-767-3677
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730-090, Korea
Phone: (82) 54-454-6027 Fax: (82) 54-454-6093

ELECTRONIC DEVICE MARKETING DEPARTMENT
Electronic devices information on WWW server

http://www.epsondevice.com



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