Freescale Semiconductor USBKW24D USB Dongle User Manual MKW22D512V good

Freescale Semiconductor, Inc. USB Dongle MKW22D512V good

Manual

© Freescale Semiconductor, Inc., 2013. All rights reserved.Freescale SemiconductorAdvance InformationThis document contains information on a product under development. Freescale reserves the right to change or discontinue thisproduct without notice.Document Number: MKW22D512VRev. 0.1, 01/2013MKW24D512VPackage InformationPlastic Package 8x8 56-pin LGACase 2234-01MC13242MKW24D512VOrdering InformationDevice Program flash System RAM PackageMKW24D512V (USB)512 K 64 K 8x8 LGAMKW22D512V(USB)512 K 64 K 8x8 LGAMKW21D256V 256 K 32 K 8x8 LGA1 IntroductionThe MKW2xDxxxV devices consists of two separate ICs: a 2.4 GHz transceiver and a microcontroller. The MCU is done in the 90 nm thin film storage (TFS) process, is built from the Kinetis platform and is part of the Kinetis portfolio. The transceiver is built using a 180 nm process.The primary target for the MKW2xDxxxV portfolio is to meet the higher performance requirements of ZigBee Pro and ZigBee IP based applications, especially Smart Energy and Commercial Building Automation. This product is a cost-effective solution that matches or exceeds competitive solutions.The following content describes the MKW2xDxxxV.The MKW2xDxxxV portfolio consist of a system on chip for the IEEE® 802.15.4 standard that incorporates a complete, low power, 2.4 GHz 802.15.4 compliant radio frequency transceiver and a Kinetis family low power, mixed-signal ARM® eCortex™- M4 MCU, with a functional set of MCU peripherals integrated into a single package.MKW24D512VAlso covers MKW22D512V and MKW21D256V1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Transceiver description . . . . . . . . . . . . . . . . . 64 System and power management . . . . . . . . 115 Radio Peripherals . . . . . . . . . . . . . . . . . . . . . 126 MKW2xDxxxV operating modes . . . . . . . . . 157 MKW2xDxxxV electrical characteristics . . 198 MCU Electrical characteristics . . . . . . . . . . 229 Transceiver electrical characteristics . . . . 6610Crystal oscillator reference frequency . . . . 7011Pin assignments . . . . . . . . . . . . . . . . . . . . . . 7112Packaging information . . . . . . . . . . . . . . . . 76
MKW2xDxxxV Product Electrical Specification, Rev. 0.12Freescale Semiconductor 1.1 Ordering information2FeaturesThis section provides a simplified block diagram and highlights MKW2xDxxxV features.2.1 Block diagramFigure 1 shows a simplified block diagram of the MKW2xDxxxV, which is an IEEE®802.15.4 standard compatible transceiver.Figure 1. MKW2xDxxxV simplified block diagramTable 1. Orderable parts detailsDevice Program flash System RAMMKW24D512V (USB) 512 K 64 KMKW22D512V (USB) 512 K 64 KMKW21D256V 256 K 32 K
MKW2xDxxxV Product Electrical Specification, Rev. 0.1Freescale Semiconductor 3 2.2 Radio features• 2.4 GHz frequency band of operation• 250 kbps data rate with O-QPSK modulation in 5.0 MHz channels with direct sequence spread-spectrum (DSSS) encode and decode• Operates on one of 16 selectable channels per IEEE 802.15.4 specification• Programmable output power• Supports 2.36 to 2.4 GHz Medical Band (MBAN) frequencies with same modulation as IEEE 802.15.4• Small RF footprint— Differential input/output port used with external balun— Integrated transmit/receive switch— Supports single ended and diversity antenna options— Low external component count— Supports external PA and LNA• Hardware acceleration for IEEE® 802.15.4 2006 packet processing— Random number generator— Support for dual PAN mode• 32 MHz crystal reference oscillator with on board trim capability to supplement external load capacitors• Programmable frequency clock output (CLK_OUT) • Bit stream mode (BSM) to monitor packet data with synchronization clock• Advanced Security Module with support for AES encryption• GPIO for Antenna Diversity control•Clocks— 32 MHz crystal oscillator— Internal 1 kHz low power oscillator— DC to 32 MHz external square wave input clock2.3 Microcontroller featuresIn addition all MKW2xDxxxV devices contain the below microcontroller features:•Core:— ARM Cortex-M4 Core delivering 1.25 DMIPS/MHz with DSP instructions (floating-point unit available on certain Kinetis families)— 16-channel DMA for peripheral and memory servicing with minimal CPU intervention• Reliability, Safety and Security:— Hardware cyclic redundancy check engine for validating memory contents/communication data and increased system reliability— Independent-clocked COP for protection against code runaway in fail-safe applications
MKW2xDxxxV Product Electrical Specification, Rev. 0.14Freescale Semiconductor — External watchdog monitor— Analog tamper detects (voltage, temperature, and clock)— External tamper detect— 256-bit secure storage (asynchronously erased on tamper detect)• Ultra-low power:— 10 low power operating modes for optimizing peripheral activity and wake-up times for extended battery life.— Low–leakage wake-up unit, low power timer, and low power RTC for additional low power flexibility— Industry-leading fast wake-up times• Memory:— FlexMemory with up to 512 KB FlexNVM and up to 4 KB FlexRAM. FlexNVM can be partitioned to support additional program flash memory (ex. bootloader), data flash (ex. storage for large tables), or EEPROM backup. FlexRAM supports— EEPROM byte-write/byte-erase operations and dictates the maximum EEPROM size.— EEPROM endurance capable of exceeding 10 million cycles— EEPROM erase/write times an order of magnitude faster than traditional EEPROM• Connectivity and Communications:— UART, I2C and DSPI• Mixed-signal analog:— Fast, high precision 16-bit ADC. Powerful signal conditioning, conversion and analysis capability with reduced system cost• Timing and Control:— Powerful FlexTimers which support general purpose, PWM, and motor control functions— Programmable Interrupt Timer for RTOS task scheduler time base or trigger source for ADC conversion and programmable delay block•System:— Wide operating voltage range from 1.8 V to 3.6 V with flash programmable down to 1.8 V with fully functional flash and analog peripherals— Ambient operating temperature ranges from –40°C to 105°CMKW2xDxxxV devices are supported by a market-leading enablement bundle from Freescale and numerous ARM 3rd party ecosystem partners.Common features among the MKW2xDxxxV family:• Operating characteristics— Voltage range 1.8 V – 3.6 V— Flash memory programming down to 1.8 V— Temperature range (TA) –40 to 105°C— Flexible modes of operation
MKW2xDxxxV Product Electrical Specification, Rev. 0.1Freescale Semiconductor 5 • Core features— Next generation 32-bit ARM Cortex-M4 core— Supports DSP instructions— Nested vectored interrupt controller (NVIC)— Asynchronous wake-up interrupt controller (AWIC)— Debug and trace capability– 2-pin serial wire debug (SWD)– IEEE 1149.1 Joint Test Action Group (JTAG)– IEEE 1149.7 compact JTAG (cJTAG)– Trace port interface unit (TPIU)– Flash patch and breakpoint (FPB)– Data watchpoint and trace (DWT)– Instrumentation trace macrocell (ITM)– Enhanced Trace Macrocell (ETM)• System and power management— Software and hardware watchdog with external monitor pin— DMA controller with 16 channels— Low-leakage wake-up unit (LLWU)— Power management controller with 10 different power modes— Non-maskable interrupt (NMI)— 128-bit unique identification (ID) number per chip•Clocks— Multi-purpose clock generator– PLL and FLL operation– Internal reference clocks (32 kHz or 2 MHz)— Three separate crystal oscillators– 3 MHz to 32 MHz crystal oscillator for MCU– 32 kHz to 40 kHz crystal oscillator for MCU or RTC– 32 MHz crystal oscillator for Radio— Internal 1 kHz low power oscillator— DC to 50 MHz external square wave input clock• Memories and Memory Interfaces— FlexMemory consisting of FlexNVM (non-volatile flash memory that can execute program code, store data, or backup EEPROM data) or FlexRAM (RAM memory that can be used as traditional RAM or as high-endurance EEPROM storage, and also accelerates flash programming)— Flash security and protection features— Serial flash programming interface (EzPort)
MKW2xDxxxV Product Electrical Specification, Rev. 0.16Freescale Semiconductor • Security and integrity— Cyclic redundancy check (CRC)— Tamper detect— Hardware encryption— AES128 Hardware encryption• Analog— 16-bit SAR ADC— High-speed Analog comparator (CMP) with 6-bit DAC•Timers— Up to 12 channels; 7 channels support external connections; 5 channels are internal only— Carrier modulator timer (CMT)— Programmable delay block (PDB)— 1x4ch programmable interrupt timer (PIT)— Low-power timer (LPT)• Communications— SPI— I2C with SMBUS support— UART (w/ ISO7816, IrDA and hardware flow control)• Human-machine interface— GPIO with pin interrupt support, DMA request capability, digital glitch filter, and other pin control options3 Transceiver description3.1 Key specificationsMKW2xDxxxV meets or exceeds all IEEE 802.15.4 performance specifications applicable to 2.4 GHz ISM and MBAN (Medical Band Area Network) bands. Key specifications for MKW2xDxxxV are:• ISM band:— RF operating frequency: 2405 MHz to 2480 MHz (center frequency range)— ISM Channel numbering: Fc = 2405 + 5 (k – 11) in MHz, k = 11, 12, …, 26.• MBAN band:— RF operating frequency: 2360 MHz to 2400 MHz (center frequency range)— MBANS channel page 9 is (2360 MHz–2390 MHz band)— Fc = 2363.0 + 1.0 * k in MHz for k = 0......26— MBANS channel page 10 is (2390 MHz–2400 MHz band)— Fc = 2390.0 + 1.0 * k in MHz for k = 0......8• IEEE 802.15.4 Standard 2.4 GHz modulation scheme— Chip rate: 2000 kbps
MKW2xDxxxV Product Electrical Specification, Rev. 0.1Freescale Semiconductor 7 — Data rate: 250 kbps— Symbol rate: 62.5 kbps— Modulation: OQPSK• Receiver sensitivity: –102 dBm, typical (@1% PER for 20 byte payload packet)• Differential bidirectional RF input/output port with integrated transmit/receive switch• Programmable output power from –30 dBm to +10 dBm.3.2 RF interface and usageThe MKW2xDxxxV RF output ports are bidirectional (diplexed between receive/transmit modes) and differential enabling interfaces with numerous off-chip devices such as a balun. When using a balun, this device provides an interface to directly connect between a single-ended antenna with MKW2xDxxxV RF ports. In addition, MKW2xDxxxV provides four output driver ports that can have both drive strength and slew rate configured to control external peripheral devices. These signals designated ANT_A, ANT_B, RX_SWITCH, and TX_SWITCH when enabled are switched via an internal hardware state machine. These ports provide control features for peripheral devices such as:• Antenna diversity modules• External PAs • External LNAs • T/R switched 3.2.1 Clock output featureThe CLK_OUT digital output can be enabled to drive the system clock to the MCU. This provides a highly accurate clock source based on the transceiver reference oscillator. The clock is programmable over a wide range of frequencies divided down from the reference 32 MHz (see Table 3).The CLK_OUT pin will be enabled upon POR. The frequency CLK_OUT will be determined by the state of the GPIO5/BOPT pin. If this pin is low upon POR, then the frequency will be 4 MHz (32 MHz/8). If this pin is high upon POR (upon POR GPIO5 has a pullup resistor) then the frequency will be 32.78689 kHz (32 MHz/976). 3.3 Transceiver functions3.3.1 Receive path The receive path has the functionality to operate in run state or operate in a low power run state (LPRS) that can be considered as a partial power down mode. The radio receiver path is based upon a near zero IF (NZIF) architecture incorporating front end amplification, one(1) mixed signal down conversion to IF that is programmably filtered, demodulated and digitally processed. The RF front end (FE) input port is differential that shares the same off chip matching network with the transmit path.
MKW2xDxxxV Product Electrical Specification, Rev. 0.18Freescale Semiconductor 3.3.2 Transmit path MKW2xDxxxV transmits OQPSK modulation having power and channel selection adjustment per user application. After the channel of operation is determined, coarse and fine tuning is executed within the Frac-N PLL to engage signal lock. After signal lock is established, the modulated buffered signal is then routed to a multi-stage amplifier for transmission. The differential signals at the output of the PA (RFOUTP, RFOUTN) are converted as single ended (SE) signals with off chip components as required. 3.3.3 Clear channel assessment (CCA), energy detection (ED), and link quality indicator (LQI)MKW2xDxxxV supports three clear channel assessment (CCA) modes of operation to include energy detection (ED) and link quality indicator (LQI). Functionality for each of these modes is provided in the sections that follow.3.3.3.1 CCA mode 1CCA mode 1 has two functions: • To estimate the energy in the received baseband signal.This energy is estimated based on receiver signal strength indicator (RSSI).• To determine whether the energy is greater than a threshold. The estimate of the energy can also be used as the Link Quality metric. In CCA Mode 1, MKW2xDxxxV warms up from Idle to Receive mode where RSSI (Receiver Signal Strength Indicator) averaging takes place right after 170µs of receiver warm-up. 3.3.3.2 CCA mode 2 CCA mode 2 detects whether there is any 802.15.4 signal transmitting at the frequency band that an 802.15.4 transmitter intends to transmit. From the definition of CCA mode 2 in the 802.15.4 standard, the requirement is to detect an 802.15.4 complied signal. Whether the detected energy is strong or not is not important for CCA mode 2.3.3.3.3 CCA mode 3CCA mode 3 as defined by 802.15.4 standard is implemented using a logical combination of CCA mode 1 and CCA mode 2. Specifically, CCA mode 3 operates in one of two operating modes: • CCA mode 3 is asserted if both CCA mode 1 and CCA mode 2 are asserted.• CCA mode 3 is asserted if either CCA mode 1 or CCA mode 2 is asserted.This mode setting is available through a programmable register.
MKW2xDxxxV Product Electrical Specification, Rev. 0.1Freescale Semiconductor 9 3.3.3.4 Energy detection (ED) Energy detection (ED) is based on receiver signal strength indicator (RSSI) and correlator output for the 802.15.4 standard. energy detect (ED) is an average value of signal strength. The magnitude from this measurement is calculated from the digital RSSI value that is averaged over an 128 s duration. 3.3.3.5 Link quality indicator (LQI)Link quality indicator (LQI), is based on receiver signal strength indicator (RSSI) or correlator output for the 802.15.4 standard. In this mode, RSSI measurement is done during normal packet reception. LQI computations for MKW2xDxxxV are based on either digital RSSI or correlator peak values. This setting is executed through a register bit where the final LQI value is available 64 s after preamble is detected. If a continuous update of LQI based on RSSI throughout the packet is desired, it can be read in a separate 8-bit register by enabling continuous update in a register bit. 3.3.4 Packet processorThe MKW2xDxxxV packet processor performs sophisticated hardware filtering of the incoming received packet, to determine whether the packet is both PHY- and MAC-compliant, whether the packet is addressed to this device, and if the device is a PAN coordinator, whether a message is pending for the sending device. The packet processor greatly reduces the packet filtering burden on software, allowing software to tend to higher-layer tasks with a lower latency and smaller software footprint.3.3.4.1 Features• Aggressive packet filtering to enable long, uninterrupted MCU sleep periods• Fully compliant with both 2003 and 2006 versions of the 802.15.4 wireless standard• Supports all frame types, including reserved types• Supports all valid 802.15.4 frame lengths• Enables auto-Tx acknowledge frames (no MCU intervention) by parsing of frame control field and sequence number• Supports all source and destination address modes, and also PAN ID compression• Supports broadcast address for PAN ID and short address mode• Supports “promiscuous” mode, to receive all packets regardless of address- and rules-checking• Allows frame type-specific filtering (e.g., reject all but beacon frames)• Supports SLOTTED and non-SLOTTED modes• Includes special filtering rules for PAN coordinator devices• Enables minimum-turnaround Tx-acknowledge frames for data-polling requests by automatically determining message-pending status• Assists MCU in locating pending messages in its indirect queue for data-polling end devices• Makes available to MCU detailed status of frames that fail address- or rules-checking.• Supports Dual PAN mode, allowing the device to exist on 2 PAN’s simultaneously• Supports 2 IEEE addresses for the device
MKW2xDxxxV Product Electrical Specification, Rev. 0.110 Freescale Semiconductor • Supports active promiscuous mode3.3.5 Packet bufferingThe packet buffer is a 128-byte random access memory (RAM) dedicated to the storage of 802.15.4 packet contents for both TX and RX sequences. For TX sequences, software stores the contents of the packet buffer starting with the frame length byte at packet buffer address 0, followed by the packet contents at the subsequent packet buffer addresses. For RX sequences the incoming packet’s frame length is stored in a register, external to the packet buffer. Software will read this register to determine the number of bytes of packet buffer to read. This facilitates DMA transfer through the SPI. For receive packets, an LQI byte is stored at the byte immediately following the last byte of the packet (frame length +1). Usage of the packet buffer for RX and TX sequences is on a time-shared basis; receive packet data will overwrite the contents of the packet buffer. Software can inhibit receive-packet overwriting of the packet buffer contents by setting the PB_PROTECT bit. This will block RX packet overwriting, but will not inhibit TX content loading of the packet buffer via the SPI. 3.3.5.1 Features• 128 byte buffer stores maximum length 802.15.4 packets• Same buffer serves both TX and RX sequences• The entire Packet Buffer can be uploaded or downloaded in a single SPI burst.• Automatic address auto-incrementing for burst accesses• Single-byte access mode supported.• Entire packet buffer can be accessed in hibernate mode• Under-run error interrupt supported3.4 Dual PAN ID In the past, radio transceivers designed for 802.15.4 and ZigBee applications allowed a device to associate to one and only one PAN (Personal Area Network) at any given time. MKW2xDxxxV represents a high-performance SoC that includes hardware support for a device to reside in two networks simultaneously. In optional Dual PAN mode, the device alternates between the two (2) PANs under hardware or software control. Hardware support for Dual PAN operation consists of two (2) sets of PAN and IEEE addresses for the device, two (2) different channels (one for each PAN), a programmable timer to automatically switch PANs (including on-the-fly channel changing) without software intervention. There are control bits to configure and enable Dual PAN mode and read only bits to monitor status in Dual PAN mode. A device can be configured to be a PAN coordinator on either network, both networks, or neither.For the purpose of defining PAN in the content of Dual PAN mode, two (2) sets of network parameters are maintained, PAN0 and PAN1. PAN0 and PAN1 will be used to refer to the two (2) PANs where each parameter set uniquely identifies a PAN for Dual PAN mode. These parameters are described in Table 2.
MKW2xDxxxV Product Electrical Specification, Rev. 0.1Freescale Semiconductor 11 During device initialization if Dual PAN mode is used, software will program both parameter sets to configure the hardware for operation on two (2) networks. 4 System and power managementThe MKW2xDxxxV is a low power device that also supports extensive system control and power management modes to maximize battery life and provide system protection.4.1 Modes of operationThe transceiver modes of operation include:• Idle mode • Doze mode• Low power (LP) / hibernate mode • Reset / powerdown mode• Run mode4.2 Power managementThe MKW2xDxxxV power management is controlled through programming the modes of operation. Different modes allow for different levels of power-down and RUN operation. For the receiver, programmable power modes available are:• Receiver modes of operation:— RX preamble search— RX Preamble search sniff — X FAD Preamble search— RX packet decoding• The RF section of the radio only powered-up as required to do a TX, RX, or CCA/ED operation.Table 2. PAN0 and PAN1 descriptionsPAN0 PAN1Channel0 (PHY_INT0, PHY_FRAC0) Channel1 (PHY_INT1, PHY_FRAC1)MacPANID0 (16-bit register) MacPANID1 (16-bit register)MacShortAddrs0 (16-bit register) MacShortAddrs1 (16-bit register)MacLongAddrs0 (64-bit registers) MacLongAddrs1 (64-bit registers)PANCORDNTR0 (1-bit register) PANCORDNTR1 (1-bit register)
MKW2xDxxxV Product Electrical Specification, Rev. 0.112 Freescale Semiconductor 5 Radio PeripheralsThe MKW2xDxxxV provides a set of I/O pins useful for suppling a system clock to the MCU, controlling external RF modules/circuitry, and GPIO. In addition, there is a special option for streaming the digital packet data for external monitoring (BSM).5.1 Clock output (CLK_OUT)MKW2xDxxxV integrates a programmable clock to source numerous frequencies for connection with various MCUs. Package pin 39 can be used to provide this clock source as required allowing the user to make adjustments per their application requirement. The transceiver CLK_OUT pin is internally connected to the MCU EXTAL pin so that no external connection is needed to drive the MCU clock.Care must be taken that the clock output signal does not “talk” or interfere with the reference oscillator or the radio. Additional functionality this feature supports is:• 3 clock domains (XTAL, SCLK, SDM_CK).• Built in synchronization at all clock domain crossings.• Aggressive clock gating in the XTAL domain to minimize dynamic current consumption based on the power mode selected.• XTAL domain can be completely gated off (hibernate mode) • SPI communication allowed in hibernate• Single-clock domain in scan modeTable 3. CLK_OUT tableThere is an enable and disable bit for CLK_OUT. When disabling, the clock output will optionally continue to run for 128 clock cycles after disablement. There will also be one (1) bit available to adjust the CLK_OUT I/O pad drive strength. 5.2 Bit streaming mode (BSM)Another peripheral option is bit streaming mode that when activated allows all 802.15.4 packet data, received or transmitted, to be serialized and shifted out to external hardware for further processing. A simple development system can be crafted to consume the BSM outputs and generate packet trace data for CLK_OUT_DIV [2:0] CLK_OUT frequency Comments032 MHz116 MHz28 MHz3 4 MHz DEFAULT if GPIO5/BOPT=042 MHz51 MHz6 62.5 kHz7 32.786 kHz DEFAULT if GPIO5/BOPT=1
MKW2xDxxxV Product Electrical Specification, Rev. 0.1Freescale Semiconductor 13 all 802.15.4 traffic appearing on a network within the range of the MKW2xDxxxV device allowing for PAN-level monitoring and debugging.BSM uses a simple synchronous 3-wire interface consisting of BSM_CLK, BSM_DATA, and BSM_FRAME outputs. Packet data is shifted out serially at the 802.15.4 bit rate (250 kHz). Signaling is provided on BSM_FRAME to indicate start-of-packet and end-of-packet and to discriminate between TX and RX packet types. BSM_DATA and BSM_FRAME are synchronous to BSM_CLK. BSM_DATA and BSM_FRAME are shifted out on the falling BSM_CLK and intended to be captured on rising BSM_CLK.A single shift register control bit activates or deactivates BSM. Aside from controlling this bit, BSM requires no software support while the mode is engaged. BSM outputs are multiplexed with GPIO, so that the pins are available for general-purpose use when BSM is disabled. BSM does not interfere with packet processing or transmit data handling in any way, it is merely a monitoring tool. BSM when engaged will not measurably increase current consumption because the hardware (including the external I/O) operates at the 250 kHz rate. 5.3 General-purpose input output (GPIO)MKW2xDxxxV embedded transceiver supports up to 8 GPIO pins where all I/O pins will have the same supply voltage, which depending on the battery can vary from 1.8 V up to 3.6 V. Not all 8 are available on the MKW2xDxxxV. When a die pin is configured as a general-purpose output or for peripheral use, there will be specific settings required per use case. Pin configuration will be executed by software to adjust input/output direction and drive strength, capability. When a die pin is configured as a general-purpose input or for peripheral use, software (see Table 4) can enable a pull-up or pull-down device. Immediately after reset, all pins are configured as high-impedance general-purpose inputs with “internal pull-up or pull-down devices enabled”. Features for these pins include:• Programmable output drive strength• Programmable output slew rate• Hi-Z mode• Programmable as outputs or inputs (default)• Pins shared with BSM mode outputs
MKW2xDxxxV Product Electrical Specification, Rev. 0.114 Freescale Semiconductor 5.3.1 Serial peripheral interface (SPI)MKW2xDxxxV’s SPI interface allows an MCU to communicate with MKW2xDxxxV’s register set and packet buffer. The SPI is a slave-only interface; the MCU must drive R_SSEL_B, R_SCLK and R_MOSI. Write and read access to both direct and indirect registers is supported, and transfer length can be single-byte, or bursts of unlimited length. Write and read access to the Packet buffer can also be single-byte, or a burst mode of unlimited length. The SPI interface is asynchronous to the rest of the IC. No relationship between R_SCLK and MKW2xDxxxV’s internal oscillator is assumed. And no relationship between R_SCLK and the CLK_OUT pin is assumed. All synchronization of the SPI interface to the IC takes place inside the SPI module. SPI synchronization takes place in both directions: SPI-to-IC (register writes), and IC-to-SPI (register reads). The SPI is capable of operation in all power modes, except Reset. Operation in hibernate mode allows most MKW2xDxxxV registers and the complete packet buffer to be accessed in the lowest-power operating state enabling minimal power consumption, especially during the register-initialization phase of the IC. The SPI design features a compact, single-byte control word, reducing SPI access latency to a minimum. Most SPI access types require only a single-byte control word, with the address embedded in the control word. During control word transfer (the first byte of any SPI access), the contents of the IRQSTS1 register (MKW2xDxxxV’s highest-priority status register) are Table 4. Pin configuration summaryPin function configuration Details Tolerance UnitsMin. Typ. Max.I/O buffer full drive mode11For this drive condition, the output voltage will not deviate more than 0.5 V from the rail reference VOH or VOL.Source or sink —10 — mAI/O buffer partial drive mode22For this drive condition, the output voltage will not deviate more than 0.5 V from the rail reference VOH or VOL.Source or sink —2—mAI/O buffer high impedance33Leakage current applies for the full range of possible input voltage conditions.Off state — — 10 nANo slew, full drive Rise and fall time44Rise and fall time values in reference to 20% and 80%246nsNo slew, partial drive Rise and fall time 246nsSlew, full drive Rise and fall time 61224nsSlew, partial drive Rise and fall time 61224nsPropagation delay5, no slew5Propagation Delay measured from/to 50% voltage point.Full drive66Full drive values provided are in reference to a 75 pF load.——11nsPropagation delay, no slew Partial drive77Partial drive values provided are in reference to a 15 pF load.——11nsPropagation delay, slew Full drive — — 50 nsPropagation delay, slew Partial drive — — 50 ns
MKW2xDxxxV Product Electrical Specification, Rev. 0.1Freescale Semiconductor 15 always shifted out, so that the MCU gets access to IRQSTS1, with the minimum possible latency, on every SPI access.5.3.1.1 Features• 4-wire industry standard interface, supported by all MCUs• SPI R_SCLK maximum frequency 16 MHz (for SPI write accesses).• SPI R_SCLK maximum frequency 9 MHz (for SPI read accesses).• Write and read access to all Coconino registers (direct and indirect)• Write and read access to packet buffer• SPI accesses can be single-byte or burst.• Automatic address auto-incrementing for burst accesses• The entire packet buffer can be uploaded or downloaded in a single SPI burst.• Entire packet buffer, and most registers, can be accessed in hibernate mode• Built-in synchronization inside the SPI module to/from the rest of the IC.• R_MISO can be tristated when SPI inactive, enabling multi-slave configurations5.3.2 Antenna diversityTo improve the reliability of RF connectivity to long range applications, the antenna diversity feature is supported without using the MCU through use of four dedicated control pins (package pins 44, 45, 46, and 47) by direct register antenna selection. The digital regulator supplies bias to analog switches that can be programmed to sink and source current or operate in a high impedance mode.Fast antenna diversity (FAD) mode supports this radio feature and, when enabled, will allow the choice of selection between two antennas during the preamble phase. By continually monitoring the received signal, the FAD block will select the first antenna on which the received signal has a correlation factor above a predefined progammable threshold. The FAD accomplishes the antenna selection by sequentially switching between the two antennas testing for the presence of a suitably strong signals/symbols where the first antenna to reach this condition is then selected for the reception of the packet.The first antenna is monitored for a period equal to 1 symbol, ts = 16 s, then antenna monitoring is switched to the second antenna, ta = 8 s. The period ta is required to allow for the external module control circuitry to turn on/off to select the antenna. ts + ta = 24 s that will allow enough time to test both antennas within the first 4 preamble symbols, tfad = 3 x ta + 2 x ts = 56 s, thus tfad < 4 x ts < 64 s. Operationally, FAD will continue to switch between the two antennas until one is found that has a sufficiently strong detected signal. FAD’s operation covers less than four s0 symbols before the antenna that is selected allowing the symbol demodulator to detect at least four s0 symbols before declaring “Preamble Detect”.6 MKW2xDxxxV operating modesThe radio has these 6 operating modes: • Reset / power down• Low power (LP) / hibernate
MKW2xDxxxV Product Electrical Specification, Rev. 0.116 Freescale Semiconductor • Doze (low power with reference oscillator active)• Idle• Receive• TransmitTable 5 lists and describes these modes.The MCU has these radio modes:Table 6. MCU power modesTable 5. Radio mode definitions and transition timesMode Definition Current consumption11Conditions: VBAT and VBAT_2 = 2.7 V, nominal process @ 25CTransition timeto or from idleReset / powerdownAll IC functions off, leakage only. RST asserted. < 30 nA TBDLow power / hibernateCrystal reference oscillator off. (SPI is functional.) < 1 ATBDDoze Crystal reference oscillator on but CLK_OUT output available only if selected.600 A (no clockout)TBDIdle Crystal reference oscillator on with CLK_OUT output available. 700 A (no clockout)TBDReceive Crystal reference oscillator on. Receiver on. 15 mA 22Signal sensitivity = –102 dBmTBDTransmit Crystal reference oscillator on. Transmitter on. 15 mA 33RF output = 0 dBmTBD
MKW2xDxxxV Product Electrical Specification, Rev. 0.1Freescale Semiconductor 17
MKW2xDxxxV Product Electrical Specification, Rev. 0.118 Freescale Semiconductor Table 7 describes alignment of radio and MCU power modes versus current consumption for typical conditions: VBAT / VDD = + 2.7V @ T=25OCTable 7. Power Modes MCU Mode Radio Mode MCU typical current consumption Radio typical current consumptionStop Idle 320 A700 A, typ. (no CLOCKOUT)Stop Doze 320 A600 A, typ. (no CLOCKOUT)VLLS1 Low power / Hibernate 0.6 A<1 A11Value does not include SPI activity. VLLS0 Reset / Powerdown <250 nA <30 nARun2232 MHz operationTransmit 12 mA 15 mARun3332 MHz operationReceive 12 mA 15 mA
MKW2xDxxxV Product Electrical Specification, Rev. 0.1Freescale Semiconductor 19 7 MKW2xDxxxV electrical characteristics7.1 Recommended operating conditions7.2 Thermal handling ratings7.3 Moisture handling ratingsTable 8. Recommended operating conditionsCharacteristic Symbol Min Typ Max UnitPower Supply Voltage (VBATT = VDDINT)VBATT, VDDINT1.8 2.7 3.6 VdcInput Frequency fin 2.360 — 2.480 GHzAmbient Temperature Range TA –40 25 105 CLogic Input Voltage Low VIL 0 — 30% VDDINTVLogic Input Voltage High VIH 70% VDDINT—VDDINT VSPI Clock Rate fSPI — — 16.0 MHzRF Input Power Pmax — — 10 dBmCrystal Reference Oscillator Frequency (40 ppm over operating conditions to meet the 802.15.4 Standard.)fref 32 MHz onlySymbol Description Min. Max. Unit NotsTSTG Storage temperature –55 150 C11Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life.TSDR Solder temperature, lead-free — 260 C22Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices.Symbol Description Min. Max. Unit NotsMSL Moisture sensitivitiy level — 3 — 11Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices.
MKW2xDxxxV Product Electrical Specification, Rev. 0.120 Freescale Semiconductor 7.4 ESD handling ratings7.5 Voltage and current ratingsSymbol Description Min. Max. Unit NotsVHBM Electrostatic discharge voltage, human body model –2000 2000 V 11Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life.VCDM Electrostatic discharge voltage, charged-device model –500 500 V 22Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices.ILAT Latch-up current at ambient temperature of 105C –100 100 mASymbol Description Min. Max. UnitVDD Digital supply voltage –0.3 3.8 VIDD Digital supply current — 155 mAVDIO Digital input voltage (except RESET, EXTAL, and XTAL) –0.3 VVAIO Analog1, RESET, EXTAL, and XTAL input voltage1Analog pins are defined as pins that do not have an associated general purpose I/O port function.–0.3 VDD + 0.3 VIDMaximum current single pin limit (applies to all port pins) –25 25 mAVDDA Analog supply voltage VDD – 0.3 VDD + 0.3 VVUSB_DP USB_DP input voltage –0.3 3.63 VVUSB_DM USB_DM input voltage –0.3 3.63 VVREGIN USB regulator input –0.3 6 VVBAT RTC battery supply voltage –0.3 3.8 V
MKW2xDxxxV Product Electrical Specification, Rev. 0.1Freescale Semiconductor 21 7.5.1 EMC radiated emissions operating behaviors7.5.2 Designing with radiated emissions in mindTo find application notes that provide guidance on designing your system to minimize interference from radiated emissions:1. Go to http://www.freescale.com.2. Perform a keyword search for “EMC design.”7.5.3 Capacitance attributes
MKW2xDxxxV Product Electrical Specification, Rev. 0.122 Freescale Semiconductor 8 MCU Electrical characteristics8.1 Maximum ratingsTable 9. Maximum ratingsRequirement Description Symbol Rating level UnitPower Supply Voltage VBAT, VBAT2 –0.3 to 3.6 VdcDigital Input Voltage Vin –0.3 to (VDDINT + 0.3) VdcRF Input Power Pmax +10 dBmESD11Electrostatic discharge on all device pads meet this requirementHuman Body Model HBM 2000 VdcMachine Model MM 200 VdcCharged Device Model CDM 750 VdcEMC22Electromagnetic compatibility for this product is low stress rating levelPower Electro-Static Discharge / Direct ContactPESDNo damage / latch up to 4000 VdcNo soft failure / reset to 1000Power Electro-Static Discharge / Indirect ContactNo damage / latch up to 6000 VdcNo soft failure / reset to 1000Langer IC / EFT / P201EFT (Electro Magnetic Fast Transient)No damage / latch up to 5VdcNo soft failure / reset to 5Langer IC / EFT / P201No damage / latch up to 300 VdcNo soft failure / reset to 150Junction Temperature TJ+150 CStorage Temperature Range Tstg –65 to +165 CNOTEMaximum ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the limits in the electrical characteristics or recommended operating conditions tables.
MKW2xDxxxV Product Electrical Specification, Rev. 0.1Freescale Semiconductor 23 8.2 General8.2.1 AC electrical characteristicsUnless otherwise specified, propagation delays are measured from the 50% to the 50% point, and rise and fall times are measured at the 20% and 80% points, as shown in the following figure.Figure 2. Input signal measurement referenceAll digital I/O switching characteristics assume:• output pins—have CL=30pF loads,—are configured for fast slew rate (PORTx_PCRn[SRE]=0), and—are configured for high drive strength (PORTx_PCRn[DSE]=1)• input pins— have their passive filter disabled (PORTx_PCRn[PFE]=0)
MKW2xDxxxV Product Electrical Specification, Rev. 0.124 Freescale Semiconductor 8.2.2 Nonswitching electrical specifications8.2.2.1 Voltage and current operating requirements11. All analog pins are internally clamped to VSS and VDD through ESD protection diodes. If VIN is greater than VAIO_MIN (=VSS-0.3V) and VIN is less than VAIO_MAX(=VDD+0.3V) is observed, then there is no need to provide current limiting resistors at the pads. If these limits cannot be observed then a current limiting resistor is required. The negative DC injection current limiting resistor is calculated as R=(VAIO_MIN-VIN)/|IIC|. The positive injection current limiting resistor is calcualted as R=(VIN-VAIO_MAX)/|IIC|. Select the larger of these two calculated resistances.
MKW2xDxxxV Product Electrical Specification, Rev. 0.1Freescale Semiconductor 25 8.3 LVD and POR operating requirements1. Rising thresholds are falling threshold + hysteresis voltage.VBAT power operating requirements
MKW2xDxxxV Product Electrical Specification, Rev. 0.126 Freescale Semiconductor 8.3.1 Voltage and current operating behaviors8.3.2 Power mode transition operating behaviorsAll specifications except tPOR, and VLLSx to RUN recovery times in the following table assume this clock configuration:• CPU and system clocks = 50 MHz• Bus clock = 50 MHz• Flash clock = 25 MHz
MKW2xDxxxV Product Electrical Specification, Rev. 0.1Freescale Semiconductor 27
MKW2xDxxxV Product Electrical Specification, Rev. 0.128 Freescale Semiconductor 8.3.3 Power consumption operating behaviors
MKW2xDxxxV Product Electrical Specification, Rev. 0.1Freescale Semiconductor 29
MKW2xDxxxV Product Electrical Specification, Rev. 0.130 Freescale Semiconductor 8.4 Switching specification8.4.1 Device clock specifications1. The frequency limitations in VLPR mode here override any frequency specification listed in the timing specification for any other module.
MKW2xDxxxV Product Electrical Specification, Rev. 0.1Freescale Semiconductor 31 8.4.2 General switching specificationsThese general purpose specifications apply to all signals configured for GPIO, UART, CMT, and I2C signals.
MKW2xDxxxV Product Electrical Specification, Rev. 0.132 Freescale Semiconductor 8.5 Core modules8.5.1 JTAG electricalsFigure 3. Test clock input timing
MKW2xDxxxV Product Electrical Specification, Rev. 0.1Freescale Semiconductor 33 Figure 4. Boundary scan (JTAG) timingFigure 5. Test access port timing
MKW2xDxxxV Product Electrical Specification, Rev. 0.134 Freescale Semiconductor Figure 6. TRST timing
MKW2xDxxxV Product Electrical Specification, Rev. 0.1Freescale Semiconductor 35 8.6 Clock modules
MKW2xDxxxV Product Electrical Specification, Rev. 0.136 Freescale Semiconductor
MKW2xDxxxV Product Electrical Specification, Rev. 0.1Freescale Semiconductor 37 8.6.1 Oscillator electrical specifications
MKW2xDxxxV Product Electrical Specification, Rev. 0.138 Freescale Semiconductor 8.6.1.1 Oscillator frequency specification
MKW2xDxxxV Product Electrical Specification, Rev. 0.1Freescale Semiconductor 39 8.6.2 32 kHz oscillator electrical characteristics8.6.2.1 32 kHz oscillator DC electrical specifications8.6.2.2 32 kHz oscillator frequency specifications8.7 Memories and memory interfaces8.7.1 Flash electrical specifications8.7.1.1 Flash timing specifications — program and eraseThe following specifications represent the amount of time the internal charge pumps are active and do not include command overhead.
MKW2xDxxxV Product Electrical Specification, Rev. 0.140 Freescale Semiconductor NVM program/erase timing specifications8.7.1.2 Flash timing specifications — commands
MKW2xDxxxV Product Electrical Specification, Rev. 0.1Freescale Semiconductor 41
MKW2xDxxxV Product Electrical Specification, Rev. 0.142 Freescale Semiconductor 8.7.1.3 Flash high voltage current behaviors8.7.1.4 NVM reliability specifications8.7.1.5 Write endurance to FlexRAM for EEPROMWhen the FlexNVM partition code is not set to full data flash, the EEPROM data set size can be set to any of several non-zero values.
MKW2xDxxxV Product Electrical Specification, Rev. 0.1Freescale Semiconductor 43 The bytes not assigned to data flash via the FlexNVM partition code are used by the flash memory module to obtain an effective endurance increase for the EEPROM data. The built-in EEPROM record management system raises the number of program/erase cycles that can be attained prior to device wear-out by cycling the EEPROM data through a larger EEPROM NVM storage space.While different partitions of the FlexNVM are available, the intention is that a single choice for the FlexNVM partition code and EEPROM data set size is used throughout the entire lifetime of a given application. The EEPROM endurance equation and graph shown below assume that only one configuration is ever used.where• Writes_subsystem — minimum number of writes to each FlexRAM location for subsystem (each subsystem can have different endurance)• EEPROM — allocated FlexNVM for each EEPROM subsystem based on DEPART; entered with the Program Partition command• EEESPLIT — FlexRAM split factor for subsystem; entered with the Program Partition command• EEESIZE — allocated FlexRAM based on DEPART; entered with the Program Partition command • Write_efficiency — 0.25 for 8-bit writes to FlexRAM— 0.50 for 16-bit or 32-bit writes to FlexRAM•nnvmcycd — data flash cycling endurance (the following graph assumes 10,000 cycles)Writes_subsystem = EEPROM . 2 Å~ EEESPLIT Å~ EEESIZEEEESPLIT Å~ EEESIZE x Write_efficiency x nnvmcycd
MKW2xDxxxV Product Electrical Specification, Rev. 0.144 Freescale Semiconductor Figure 7. EEPROM backup writes to FlexRAM8.7.2 EzPort switching specifications
MKW2xDxxxV Product Electrical Specification, Rev. 0.1Freescale Semiconductor 45 Figure 8. ExPort timing diagram8.8 Analog8.8.1 ADC electrical specificationsThe 16-bit accuracy specifications are achievable on the differential pins ADCx_DP0, ADCx_DM0.All other ADC channels meet the 13-bit differential/12-bit single-ended accuracy specifications.
MKW2xDxxxV Product Electrical Specification, Rev. 0.146 Freescale Semiconductor
MKW2xDxxxV Product Electrical Specification, Rev. 0.1Freescale Semiconductor 47 Figure 9. ADC input impedance equivalency diagram
MKW2xDxxxV Product Electrical Specification, Rev. 0.148 Freescale Semiconductor 8.8.1.1 16-bit ADC electrical characteristics
MKW2xDxxxV Product Electrical Specification, Rev. 0.1Freescale Semiconductor 49
MKW2xDxxxV Product Electrical Specification, Rev. 0.150 Freescale Semiconductor Figure 10. Typical ENOB vs. ADC_CLK for 16-bit differential modeFigure 11. Typical ENOB vs. ADC_CLK for 16-bit single-ended mode
MKW2xDxxxV Product Electrical Specification, Rev. 0.1Freescale Semiconductor 51 8.8.2 CMP and 6-bit DAC electrical specifications
MKW2xDxxxV Product Electrical Specification, Rev. 0.152 Freescale Semiconductor Figure 12. Typical hysteresis vs. Vin level (VDD=3.3 V, PMODE=0)
MKW2xDxxxV Product Electrical Specification, Rev. 0.1Freescale Semiconductor 53 Figure 13. Typical hysteresis vs. Vin level (VDD=3.3 V, PMODE=1)8.8.3 12-bit DAC electrical characteristics8.8.3.1 12-bit DAC operating requirements8.8.3.2 12-bit DAC operating behaviorsThe following table contains information about the 12-bit DAC on the MCU.
MKW2xDxxxV Product Electrical Specification, Rev. 0.154 Freescale Semiconductor
MKW2xDxxxV Product Electrical Specification, Rev. 0.1Freescale Semiconductor 55 Figure 14. Typical INL error vs. digital code
MKW2xDxxxV Product Electrical Specification, Rev. 0.156 Freescale Semiconductor Figure 15. Offset at half scale vs. temperature8.8.4 Voltage reference electrical specifications8.8.4.1 VREF full-range operating requirements
MKW2xDxxxV Product Electrical Specification, Rev. 0.1Freescale Semiconductor 57 8.8.4.2 VREF full-range operating behaviors8.8.4.3 VREF limited-range operating requirements8.8.4.4 VREF limited-range operating behaviors8.9 Communication interfaces8.9.1 USB electrical specificationsThe USB electricals for the USB On-the-Go module conform to the standards documented by the Universal Serial Bus Implementers Forum. For the most up-to-date standards, visit http://www.usb.org.
MKW2xDxxxV Product Electrical Specification, Rev. 0.158 Freescale Semiconductor 8.9.2 USB DCD electrical specifications8.9.3 VREG electrical specifications
MKW2xDxxxV Product Electrical Specification, Rev. 0.1Freescale Semiconductor 59 8.9.4 DSPI switching specifications (limited voltate range)The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with master and slave operations. Many of the transfer attributes are programmable. The tables below provide DSPI timing characteristics for classic SPI timing modes. Refer to the DSPI chapter of the Reference Manual for information on the modified transfer formats used for communicating with slower peripheral devices.Master modeFigure 16. DSPI classic SPI timing — master mode
MKW2xDxxxV Product Electrical Specification, Rev. 0.160 Freescale Semiconductor Slave modeFigure 17. DSPI classic SPI timing — slave mode8.9.5 DSPI switching specification (full voltage range)The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with master and slave operations. Many of the transfer attributes are programmable. The tables below provides DSPI timing characteristics for classic SPI timing modes. Refer to the DSPI chapter of the Reference Manual for information on the modified transfer formats used for communicating with slower peripheral devices.
MKW2xDxxxV Product Electrical Specification, Rev. 0.1Freescale Semiconductor 61 Master mode DSPI timing (full voltage range)Figure 18. DSPI classic SPI timing — master modeSlave mode DSPI timing (full voltage range)
MKW2xDxxxV Product Electrical Specification, Rev. 0.162 Freescale Semiconductor Figure 19. DSPI classic SPI timing — slave mode8.9.6 Normal Run, Wait and Stop mode performance over the fulloperating voltage rangeThis section provides the operating performance over the full operating voltage for the device in Normal Run, Wait and Stop modes.
MKW2xDxxxV Product Electrical Specification, Rev. 0.1Freescale Semiconductor 63 I2S/SAI master mode timingFigure 20. I2S/SAI timing — master modes
MKW2xDxxxV Product Electrical Specification, Rev. 0.164 Freescale Semiconductor I2S/SAI slave mode timingFigure 21. I2S/SAI timing — slave modes8.9.7 VLPR, VLPW, and VLPS mode performance over the full operating voltage rangeThis section provides the operating performance over the full operating voltage for the device in VLPR, VLPW, and VLPS modes.
MKW2xDxxxV Product Electrical Specification, Rev. 0.1Freescale Semiconductor 65 I2S/SAI master mode timing in VLPR, VLPW, and VLPS modes (full voltage range)Figure 22. I2S/SAI timing — master modesI2S/SAI slave mode timing in VLPR, VLPW, and VLPS modes (full voltage range)
MKW2xDxxxV Product Electrical Specification, Rev. 0.166 Freescale Semiconductor Figure 23. I2S/SAI timing — slave modes9 Transceiver electrical characteristics9.1 DC electrical characteristicsTable 10. DC electrical characteristics (VBATT, VDDINT = 2.7 V, TA=25°C, unless otherwise noted)Characteristic Symbol Min Typ Max UnitPower Supply Current (VBATT + VDDINT)Reset / power down1 Hibernate1Doze (No CLK_OUT)Idle (No CLK_OUT)Transmit mode (0 dBm nominal output power)Receive modeIleakageICCHICCDICCIICCTICCR——————<30<16007001515————1818nAµAµAµAmAmAInput current (VIN = 0 V or VDDINT) (All digital inputs) IIN — — 1µA
MKW2xDxxxV Product Electrical Specification, Rev. 0.1Freescale Semiconductor 67 Input low voltage (all digital inputs) VIL 0 — 30% VDDINTVInput high voltage (all digital inputs) VIH 70% VDDINT—VDDINTVOutput high voltage (IOH = -1 mA) (all digital outputs) VOH 80% VDDINT—VDDINTVOutput low voltage (IOL = 1 mA) (all digital outputs) VOL 0 — 20% VDDINTV1To attain specified low power current, all GPIO and other digital IO must be handled properly.Table 10. DC electrical characteristics (VBATT, VDDINT = 2.7 V, TA=25°C, unless otherwise noted)Characteristic Symbol Min Typ Max Unit
MKW2xDxxxV Product Electrical Specification, Rev. 0.168 Freescale Semiconductor 9.2 AC electrical characteristicsTable 11. Receiver AC electrical characteristics (VBATT, VDDINT=2.7 V, TA=25 °C, fref=32 MHz, unless otherwise noted)Characteristic Symbol Min Typ Max UnitSensitivity for 1% packet error rate (PER) (–40 to +105 °C) SENSper — –99 –97 dBmSensitivity for 1% packet error rate (PER) (+25 °C) SENSper — –102 dBmSaturation (maximum input level) SENSmax — +10 — dBmChannel rejection for dual port mode (1% PER and desired signal –82 dBm)+5 MHz (adjacent channel)–5 MHz (adjacent channel)+10 MHz (alternate channel)–10 MHz (alternate channel)>= 15 MHz—————3834474755—————dBdBdBdBdBFrequency error tolerance — — 200 kHzSymbol rate error tolerance 80 — — ppmTable 12. Transmitter AC electrical characteristics(VBATT, VDDINT=2.7 V, TA=25°C, fref=32 MHz, unless otherwise noted)Characteristic Symbol Min Typ Max UnitPower spectral density1, absolute limit from –40C to +105C1[f-fc] > 3.5 MHz, average spectral power is measured in 100 kHz resolution BW. –30 — — dBmPower Spectral Density2, Relative limit from –40C to +105C2For the relative limit, the reference level is the highest reference power measured within  1 MHz of the carrier frequency–20 — — dBNominal output power Pout –0.5 0 0.5 dBmMaximum output power — 10 — dBmError vector magnitude EVM — 8 13 %Output power control range33Measurement is at the package pin on the output of the Tx/Rx switch. It does not degrade more than 2 dB across temperature and an additional 1 dB across all processes. Power adjustment will span nominally from –30 dBm to +10 dBm in 21 steps @ 2 dBm / step. —40—dBOver the air data rate — 250 — kbps2nd harmonic44Measured with output power set to nominal (0 dBm) and temperature @ 25°C. If trap filter is needed must meet reference board size requirements.—<-50<-40dBm3rd harmonic 4—<-50<-40dBm
MKW2xDxxxV Product Electrical Specification, Rev. 0.1Freescale Semiconductor 69 9.2.1 SPI timing: R_SSEL_B to R_SCLKThe following diagram describes timing constraints that must be guaranteed by the system designer.Figure 24. SPI timing: R_SSEL_B to R_SCLKtCSC (CS-to-SCK delay): 31.25 nstASC (After SCK delay): 31.25 nstDT (Minimum CS idle time): 62.5 nstCKH (Minimum R_SCLK high time): 31.25 ns (for SPI writes); 55.55 ns (for SPI reads)tCKL (Minimum R_SCLK low time): 31.25 ns (for SPI writes); 55.55 ns (for SPI reads)NOTEThe SPI master device deasserts R_SSEL_B only on byte boundaries, and only after guaranteeing the tASC constraint shown above. 9.2.2 SPI timing: R_SCLK to R_MOSI and R_MISOThe following diagram describes timing constraints that must be guaranteed by the system designer. These constraints apply to the Master SPI (R_MOSI), and are guaranteed by the radio SPI (R_MISO). Figure 25. SPI timing: R_SCLK to R_MOSI and R_MISOtDSU (data-to-SCK setup): 10 nstDH (SCK-to-data hold): 10 nsR_SSEL_BR_SCLKtCSCtASCtDTtCKLtCKHR_SCLKtDSUtDHR_MOSIR_MISO
MKW2xDxxxV Product Electrical Specification, Rev. 0.170 Freescale Semiconductor 10 Crystal oscillator reference frequencyThis section provides application specific information regarding crystal oscillator reference design and recommended crystal usage.10.1 Crystal oscillator design considerationsThe IEEE ® 802.15.4 Standard requires that frequency tolerance be kept within ±40 ppm accuracy. This means that a total offset up to 80 ppm between transmitter and receiver will still result in acceptable performance. The MKW2xDxxxV transceiver provides on board crystal trim capacitors to assist in meeting this performance, while the bulk of the crystal load capacitance is external.Table 13. RF port impedanceCharacteristic Symbol Typ UnitRFIN Pins for internal T/R switch configuration, TX mode2.360 GHz2.420 GHz2.480 GHzZinTBDRFIN Pins for internal or external T/R switch configuration, RX mode2.360 GHz2.420 GHz2.480 GHzZinTBDPAO Pins for external T/R switch configuration, TX mode2.360 GHz2.420 GHz2.480 GHzZinTBD
MKW2xDxxxV Product Electrical Specification, Rev. 0.1Freescale Semiconductor 71 10.2 Crystal requirementsThe suggested crystal specification for the MKW2xDxxxV is shown in Table 14. A number of the stated parameters are related to desired package, desired temperature range and use of crystal capacitive load trimming.11 Pin assignmentsTable 14. MKW2xDxxxV crystal specificationsParameter Value Unit ConditionFrequency 32 MHzFrequency tolerance (cut tolerance) 10 ppm at 25°CFrequency stability (temperature) 25 ppm Over desired temperature rangeAging11A wider aging tolerance may be acceptable if application uses trimming at production final test.2 ppm maxEquivalent series resistance 60 maxLoad capacitance 5–9 pFShunt capacitance <2 pF maxMode of oscillation fundamental
MKW2xDxxxV Product Electrical Specification, Rev. 0.172 Freescale Semiconductor
MKW2xDxxxV Product Electrical Specification, Rev. 0.1Freescale Semiconductor 73
MKW2xDxxxV Product Electrical Specification, Rev. 0.174 Freescale Semiconductor
MKW2xDxxxV Product Electrical Specification, Rev. 0.1Freescale Semiconductor 75
MKW2xDxxxV Product Electrical Specification, Rev. 0.176 Freescale Semiconductor 12 Packaging information Figure 26. MKW22/24D512V (USB) Pin Assignment
MKW2xDxxxV Product Electrical Specification, Rev. 0.1Freescale Semiconductor 77 Figure 27. MKW21D256V Pin Assignment

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