Hitachi Travelstar Hds723020Bla642 Users Manual DPＣ SATA OEM SPEC 100

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2015-01-24

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7K200 SATA OEM Specification

Hｉｔａｃｈｉ Global Storage Technologies

Hard Disk Drive Specification

Hitachi Travelstar 7K200
2.5 inch SATA hard disk drive
Models:

HTS722020K9A300

HTS722020K9SA00

HTS722016K9A300

HTS722016K9SA00

HTS722012K9A300

HTS722012K9SA00

HTS722010K9A300

HTS722010K9SA00

HTS722080K9A300

HTS722080K9SA00

Revision 1.0

10 May 2007

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7K200 SATA OEM Specification
Preliminary Edition (Revision 0.1) (31 March 2007)
2nd Preliminary Edition (Revision 0.2) (20 April 2007)
Final Release (Revision 1.0) (10 May 2007)
The following paragraph does not apply to the United Kingdom or any country where such
provisions are inconsistent with local law: HITACHI GLOBAL STORAGE TECHNOLOGIES
PROVIDES THIS PUBLICATION "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
EXPRESS OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Some states do not allow
disclaimer or express or implied warranties in certain transactions, therefore, this statement may
not apply to you.
This publication could include technical inaccuracies or typographical errors. Changes are
periodically made to the information herein; these changes will be incorporated in new editions of
the publication. Hitachi may make improvements or changes in any products or programs described
in this publication at any time.
It is possible that this publication may contain reference to, or information about, Hitachi products
(machines and programs), programming, or services that are not announced in your country. Such
references or information must not be construed to mean that Hitachi intends to announce such
Hitachi products, programming, or services in your country.
Technical information about this product is available by contacting your local Hitachi Global Storage
Technologies representative or on the Internet at http://www.hitachigst.com
Hitachi Global Storage Technologies may have patents or pending patent applications covering
subject matter in this document. The furnishing of this document does not give you any license to
these patents.
©Copyright Hitachi Global Storage Technologies
Note to U.S. Government Users —Documentation related to restricted rights —Use, duplication or
disclosure is subject to restrictions set forth in GSA ADP Schedule Contract with Hitachi Global
Storage Technologies.

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Table of Contents
GENERAL...............................................................................................................................................10
1 INTRODUCTION .....................................................................................................................................10
1.1
Abbreviations...........................................................................................................................10
1.2
References ................................................................................................................................13
1.3
General caution .......................................................................................................................13
1.4
Drive handling precautions ....................................................................................................13
2 OUTLINE OF THE DRIVE.........................................................................................................................14
PART 1 FUNCTIONAL SPECIFICATION ...........................................................................................15
3 FIXED DISK SUBSYSTEM DESCRIPTION ..................................................................................................16
3.1
Control Electronics ..................................................................................................................16
3.2
Head disk assembly data ........................................................................................................16
4 FIXED DISK CHARACTERISTICS ..............................................................................................................17
4.1
Formatted capacity by model number....................................................................................17
4.2
Data sheet ................................................................................................................................18
4.3
Cylinder allocation ..................................................................................................................18
4.4
Performance characteristics ...................................................................................................19
5 DATA INTEGRITY ...................................................................................................................................23
5.1
Data loss on power off .............................................................................................................23
5.2
Write Cache .............................................................................................................................23
5.3
Equipment status ....................................................................................................................23
5.4
WRITE safety...........................................................................................................................23
5.5
Data buffer test........................................................................................................................24
5.6
Error recovery ..........................................................................................................................24
5.7
Automatic reallocation ............................................................................................................24
5.8
ECC ..........................................................................................................................................25
6 SPECIFICATION .....................................................................................................................................26
6.1
Environment ............................................................................................................................26
6.2
DC power requirements ..........................................................................................................28
6.3
Reliability.................................................................................................................................30
6.4
Mechanical specifications........................................................................................................33
6.5
Vibration and shock.................................................................................................................35
6.6
Acoustics...................................................................................................................................37
6.7
Identification labels.................................................................................................................38
6.8
Electromagnetic compatibility................................................................................................38
6.9
Safety........................................................................................................................................39
6.10 Packaging.................................................................................................................................39
6.11 Substance restriction requirements .......................................................................................39
7 ELECTRICAL INTERFACE SPECIFICATIONS ............................................................................................40
7.1
Cabling .....................................................................................................................................40
7.2
Interface connector ..................................................................................................................40
7.3
Signal definitions.....................................................................................................................41
PART 2 INTERFACE SPECIFICATION...............................................................................................43
8 GENERAL ..............................................................................................................................................44
8.1
Introduction .............................................................................................................................44
8.2
Terminology .............................................................................................................................44
9 DEVIATIONS FROM STANDARD ..............................................................................................................45
10 PHYSICAL INTERFACE .........................................................................................................................45
11 REGISTERS ..........................................................................................................................................45
11.1 Register naming convention ...................................................................................................46
11.2 Command register ...................................................................................................................47
11.3 Device Control Register...........................................................................................................47
11.4 Device Register ........................................................................................................................47

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11.5 Error Register ..........................................................................................................................47
11.6 Features Register ....................................................................................................................48
11.7 LBA High Register ..................................................................................................................48
11.8 LBA Low Register....................................................................................................................48
11.9 LBA Mid Register ....................................................................................................................48
11.10 Sector Count Register..........................................................................................................48
11.11 Status Register.....................................................................................................................48
12 GENERAL OPERATION DESCRIPTIONS ................................................................................................50
12.1 Reset Response ........................................................................................................................50
12.1.1

Register Initialization .................................................................................................................... 50

12.3.1
12.3.2
12.3.3

Load/Unload ................................................................................................................................... 52
Emergency unload.......................................................................................................................... 52
Required power-off sequence ......................................................................................................... 52

12.2
12.3

12.4

Diagnostic and Reset considerations......................................................................................51
Power-off considerations .........................................................................................................52

Sector Addressing Mode..........................................................................................................53

12.4.1
12.4.2

Logical CHS Addressing Mode ...................................................................................................... 53
LBA Addressing Mode ................................................................................................................... 53

12.5.1
12.5.2
12.5.3
12.5.4
12.5.5
12.5.6

Power Mode .................................................................................................................................... 54
Power Management Commands.................................................................................................... 54
Standby/Sleep command completion timing................................................................................. 54
Status.............................................................................................................................................. 54
Interface Capability for Power Modes........................................................................................... 54
Initial Power Mode at Power On ................................................................................................... 55

12.5

12.6

Power Management Feature ..................................................................................................53

Advanced Power Management (Adaptive Battery Life Extender 3) Feature......................55

12.6.1
12.6.2
12.6.3
12.6.4

Performance Idle mode .................................................................................................................. 55
Active Idle mode............................................................................................................................. 55
Low Power Idle mode ..................................................................................................................... 55
Transition Time.............................................................................................................................. 56

12.8.1
12.8.2
12.8.3
12.8.4
12.8.5
12.8.6

Attributes ....................................................................................................................................... 56
Attribute values ............................................................................................................................. 56
Attribute thresholds....................................................................................................................... 57
Threshold exceeded condition........................................................................................................ 57
S.M.A.R.T. commands.................................................................................................................... 57
S.M.A.R.T operation with power management modes ................................................................. 57

12.7
12.8

12.9

Interface Power Management Mode (Slumber and Partial).................................................56
S.M.A.R.T. Function................................................................................................................56

Security Mode Feature Set .....................................................................................................57

12.9.1
12.9.2
12.9.3
12.9.4
12.9.5
12.9.6

12.10
12.10.1
12.10.2

12.11
12.12
12.13
12.13.1

12.14
12.15

12.15.1

Security mode................................................................................................................................. 57
Security Level................................................................................................................................. 58
Password......................................................................................................................................... 58
Master Password Revision Code ................................................................................................... 58
Operation example ......................................................................................................................... 58
Command Table ............................................................................................................................. 61

Protected Area Function......................................................................................................63
Example for operation (In LBA mode) ...................................................................................... 64
Set Max security extension commands ..................................................................................... 65

Seek Overlap ........................................................................................................................66
Write Cache Function..........................................................................................................66
Reassign Function................................................................................................................66
Auto Reassign Function............................................................................................................. 67

48-bit Address Feature Set..................................................................................................67
Software Setting Preservation Feature Set .......................................................................68
Preserved software settings....................................................................................................... 68

12.16 Native Command Queuing..................................................................................................69
12.17 SMART Command Transport (SCT)...................................................................................70
13 COMMAND PROTOCOL .........................................................................................................................70
13.1 Data In Commands .................................................................................................................71
13.2 Data Out Commands...............................................................................................................71
13.3 Non-Data Commands ..............................................................................................................72
13.4 DMA Data Transfer Commands.............................................................................................72

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13.5 First-parity DMA Commands .................................................................................................73
14 COMMAND DESCRIPTIONS ..................................................................................................................74
14.1 Check Power Mode (E5h/98h).................................................................................................78
14.2 Device Configuration Overlay (B1h) ......................................................................................79
14.2.1
14.2.2
14.2.3
14.2.4

14.3
14.4
14.5
14.6
14.7
14.8
14.9
14.10
14.11
14.12
14.13
14.14
14.15
14.16

Execute Device Diagnostic (90h) ............................................................................................83
Flush Cache (E7h) ...................................................................................................................84
Flush Cache Ext (EAh)............................................................................................................85
Format Track (50h: Vendor Specific) .....................................................................................86
Format Unit (F7h: Vendor Specific) .......................................................................................87
Identify Device (ECh) ..............................................................................................................88
Idle (E3h/97h) ..........................................................................................................................99
Idle Immediate (E1h/95h) .................................................................................................100
Initialize Device Parameters (91h) ...................................................................................101
Read Buffer (E4h) ..............................................................................................................102
Read DMA(C8h/C9h) .........................................................................................................103
Read DMA Ext (25h)..........................................................................................................104
Read FPDMA Queued (60h)..............................................................................................105
Read Log Ext(2Fh) .............................................................................................................106

14.16.1
14.16.2
14.16.3
14.16.4
14.16.5

14.17
14.18
14.19
14.20
14.21
14.22
14.23
14.24
14.25
14.26
14.27
14.28
14.29
14.30
14.31
14.32
14.33
14.34
14.35
14.36
14.37
14.38
14.39

14.39.1
14.39.2
14.39.3
14.39.4
14.39.5
14.39.6
14.39.7
14.39.8

14.40
14.41
14.42

DEVICE CONFIGURATION RESTORE (subcommand C0h)..................................................... 79
DEVICE CONFIGURATION FREEZE LOCK (subcommand C1h) ............................................ 79
DEVICE CONFIGURATION IDENTIFY (subcommand C2h) .................................................... 80
DEVICE CONFIGURATION SET (subcommand C3h) ............................................................... 80

General purpose Log Directory................................................................................................ 107
Extended comprehensive SMART error log............................................................................ 107
Extended Self-test log sector ................................................................................................... 110
Command Error ....................................................................................................................... 111
Phy Event Counter................................................................................................................... 112

Read Multiple (C4h)...........................................................................................................114
Read Multiple Ext (29h) ....................................................................................................115
Read Native Max Address (F8h).......................................................................................116
Read Native Max Address Ext (27h) ................................................................................117
Read Sector(s) (20h/21h)....................................................................................................118
Read Sector(s) Ext (24h)....................................................................................................119
Read Verify Sector(s) (40h/41h) ........................................................................................120
Read Verify Sector(s) Ext (42h).........................................................................................121
Recalibrate (1xh)................................................................................................................122
Security Disable Password (F6h)......................................................................................123
Security Erase Prepare (F3h) ...........................................................................................124
Security Erase Unit (F4h) .................................................................................................125
Security Freeze Lock (F5h) ...............................................................................................127
Security Set Password (F1h) .............................................................................................128
Security Unlock (F2h)........................................................................................................130
Seek (7xh) ...........................................................................................................................131
Sense Condition (F0h : vendor specific)............................................................................132
Set Features (EFh).............................................................................................................133
Set Max Address (F9h) ......................................................................................................135
Set Max Address Ext (37h)................................................................................................137
Set Multiple (C6h)..............................................................................................................139
Sleep (E6h/99h) ..................................................................................................................140
S.M.A.R.T Function Set (B0h) ..........................................................................................141
S.M.A.R.T. Sub commands ...................................................................................................... 141
Device Attributes Data Structure ........................................................................................... 146
Device Attribute Thresholds Data Structure.......................................................................... 150
S.M.A.R.T. Log Directory......................................................................................................... 151
S.M.A.R.T. error log sector ...................................................................................................... 151
Self-test log data structure ...................................................................................................... 154
Selective self-test log data structure ....................................................................................... 155
Error Reporting ........................................................................................................................ 155

Standby (E2h/96h) .............................................................................................................156
Standby Immediate (E0h/94h) ..........................................................................................157
Write Buffer (E8h) .............................................................................................................158
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14.43 Write DMA (CAh/CBh) ......................................................................................................159
14.44 Write DMA Ext (35h).........................................................................................................160
14.45 Write DMA FUA Ext (3Dh)...............................................................................................161
14.46 Write FPDMA Queued (61h).............................................................................................162
14.47 Write Log Ext (3Fh) ...........................................................................................................163
14.48 Write Multiple (C5h)..........................................................................................................164
14.49 Write Multiple Ext (39h) ...................................................................................................165
14.50 Write Multiple FUA Ext (CEh) .........................................................................................166
14.51 Write Sector(s) (30h/31h)...................................................................................................167
14.52 Write Sector(s) Ext (34h)...................................................................................................168
14.53 Write Uncorrectable Ext (45h)..........................................................................................169
15 TIMINGS ............................................................................................................................................171

List of Figures
Figure 1. Limits of temperature and humidity
Figure 2. Mounting hole locations
Figure 3. Interface connector pin assignments
Figure 4. Parameter descriptions
Figure 5 Initial Setting
Figure 6 Usual Operation
Figure 7 Password Lost
Figure 8 Set Max security mode transition
Figure 9 Seek overlap
Figure 10 Selective self-test test span example

26
33
40
42
59
60
61
65
66
143

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List of Tables
Table 1. Formatted capacity by model number.
Table 2. Data sheet
Table 3. Cylinder allocation
Table 4. Performance characteristics
Table 5. Mechanical positioning performance
Table 6. Full stroke seek time
Table 7. Single track seek time
Table 8. Latency time
Table 9. Drive ready time
Table 10. Operating mode
Table 11. Drive ready time
Table 12. Environmental condition
Table 13. Magnetic flux density limits
Table 14. DC Power requirements
Table 15. Power consumption efficiency
Table 16. Physical dimensions and weight
Table 17. Random vibration PSD profile breakpoints (operating)
Table 18. Swept sine vibration
Table 19. Random Vibration PSD Profile Breakpoints (nonoperating)
Table 20. Operating shock
Table 21. Nonoperating shock
Table 22. Weighted sound power
Table 23. Interface connector pins and I/O signals
Table 24 Register naming convention and correspondence
Table 25 Device Control Register
Table 26 Device Register
Table 27 Error Register
Table 28 Status Register
Table 29 Reset Response Table
Table 30 Default Register Values
Table 31 Diagnostic Codes
Table 32 Reset error register values
Table 33 Device’s behavior by ATA commands
Table 34 Power conditions
Table 35 Command table for device lock operation
Table 36 Command table for device lock operation - continued
Table 37 Set Max Set Password data content
Table 38 Preserved Software Setting
Table 39 SCT Action Code Supported
Table 40 Command set
Table 41 Command Set - continued
Table 42 Command Set (Subcommand)
Table 43 Check Power Mode Command (E5h/98h)
Table 44 Device Configuration Overlay Command (B1h)
Table 45 Device Configuration Overlay Features register values
Table 46 Device Configuration Overlay Data structure
Table 47 DCO error information definition
Table 48 Execute Device Diagnostic Command (90h)
Table 49 Flush Cache Command (E7h)
Table 50 Flush Cache EXT Command (EAh)
Table 51 Format Track Command (50h)
Table 52 Format Unit Command (F7h)
Table 53 Identify Device Command (ECh)
Table 54 Identify device information
Table 55 Identify device information --- Continued --Table 56 Identify device information --- Continued --Table 57 Identify device information --- Continued ---

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35
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41
46
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51
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7K200 SATA OEM Specification
Table 58 Identify device information --- Continued --93
Table 59 Identify device information --- Continued --94
Table 60 Identify device information --- Continued --95
Table 61 Identify device information --- Continued --96
Table 62 Identify device information --- Continued --97
Table 63 Number of cylinders/heads/sectors by models for HTS7220XXK9SA00 / HTS7220XXK9A300
98
Table 64 Idle Command (E3h/97h)
99
Table 65 Idle Immediate Command (E1h/95h)
100
Table 66 Initialize Device Parameters Command (91h)
101
Table 67 Read Buffer Command (E4h)
102
Table 68 Read DMA Command (C8h/C9h)
103
Table 69 Read DMA Ext Command (25h)
104
Table 70 Read FPDMA Queued Command (60h)
105
Table 71 Read Log Ext Command (2Fh)
106
Table 72 Log address definition
106
Table 73 General purpose Log Directory
107
Table 74 Extended comprehensive SMART error Log
108
Table 75 Extended Error log data structure
108
Table 76 Command data structure
109
Table 77 Error data structure
109
Table 78 Extended Self-test log data structure
110
Table 79 Extended Self-test log descriptor entry
111
Table 80 Command Error information
111
Table 81 Phy Event Counter Identifier
112
Table 82 Phy Event Counter information
113
Table 83 Read Multiple Command (C4h)
114
Table 84 Read Multiple Ext Command (29h)
115
Table 85 Read Native Max Address Command (F8h)
116
Table 86 Read Native Max Address Ext Command (29h)
117
Table 87 Read Sector(s) Command (20h/21h)
118
Table 88 Read Sector(s) Ext Command (24h)
119
Table 89 Read Verify Sector(s) Command (40h/41h)
120
Table 90 Read Verify Sector(s) Ext Command (42h)
121
Table 91 Recalibrate Command (1xh)
122
Table 92 Security Disable Password Command (F6h)
123
Table 93 Password Information for Security Disable Password command
123
Table 94 Security Erase Prepare Command (F3h)
124
Table 95 Security Erase Unit Command (F4h)
125
Table 96 Erase Unit Information
125
Table 97 Security Freeze Lock Command (F5h)
127
Table 98 Security Set Password Command (F1h)
128
Table 99 Security Set Password Information
128
Table 100 Security Unlock Command (F2h)
130
Table 101 Security Unlock Information
130
Table 102 Seek Command (7xh)
131
Table 103 Sense Condition Command (F0h)
132
Table 104 Set Features Command (EFh)
133
Table 105 Set Max Address Command (F9h)
135
Table 106 Set Max Address Ext Command (37h)
137
Table 107 Set Multiple Command (C6h)
139
Table 108 Sleep Command (E6h/99h)
140
Table 109 S.M.A.R.T. Function Set Command (B0h)
141
Table 110 Log sector addresses
144
Table 111 Device Attribute Data Structure
146
Table 112 Individual Attribute Data Structure
147
Table 113 Status Flag Definitions
148
Table 114 Device Attribute Thresholds Data Structure
150
Table 115 Individual Threshold Data Structure
151
Table 116 SMART Log Directory
151
Table 117 S.M.A.R.T. error log sector
152
Table 118 Error log data structure
152
Table 119 Command data structure
153

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Table 120 Error data structure
Table 121 Self-test log data structure
Table 122 Selective self-test log data structure
Table 123 S.M.A.R.T. Error Codes
Table 124 Standby Command (E2h/96h)
Table 125 Standby Immediate Command (E0h/94h)
Table 126 Write Buffer Command (E8h)
Table 127 Write DMA Command (CAh/CBh)
Table 128 Write DMA Ext Command (35h)
Table 129 Write DMA FUA Ext Command (3Dh)
Table 130 Write FPDMA Queued Command (61h)
Table 131 Write Log Ext Command
Table 132 Write Multiple Command (C5h)
Table 133 Write Multiple Ext Command (39h)
Table 134 Write Multiple FUA Ext Command (CEh)
Table 135 Write Sector(s) Command (30h/31h)
Table 136 Write Sector(s) Ext Command (34h)
Table 137 Write Uncorrectable Ext Command (45h)
Table 138 Timeout Values

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7K200 SATA OEM Specification

General
1 Introduction
This document describes the specifications of the HITACHI Travelstar 7K200, a 2.5-inch hard disk
drive with Serial ATA interface:
Drive
name

Model Number

Travelstar
7K200-200

HTS722020K9A300

MAX Data
transfer rate
(Gbps)
3.0

HTS722020K9SA00

1.5

HTS722016K9A300

3.0

HTS722016K9SA00

1.5

HTS722012K9A300

3.0

HTS722012K9SA00

1.5

HTS722010K9A300

3.0

HTS722010K9SA00

1.5

HTS722080K9A300

3.0

HTS722080K9SA00

1.5

Travelstar
7K200-160
Travelstar
7K200-120
Travelstar
7K200-100
Travelstar
7K200-80

Capacity
(GB)

Height
(mm)

Rotation
speed (rpm)

200

9.5

7200

160

9.5

7200

120

9.5

7200

100

9.5

7200

9.5

7200

Part 1 of this document beginning on page 16 defines the hardware functional specification. Interface
specification is Part 2 starting from page 44

1.1

Abbreviations

Abbreviation

Meaning

32 KB

32 x 1024 bytes

64 KB

64 x 1024 bytes

“

inch

amp

alternating current

Advanced Technology

ATA

Advanced Technology Attachment

Bels

unit of sound power

BIOS

Basic Input/Output System

°C

degrees Celsius

CSA

Canadian Standards Association

C-UL

Canadian-Underwriters Laboratory

Cyl

cylinder

direct current

DFT

Drive Fitness Test

DMA

Direct Memory Access

ECC

error correction code

EEC

European Economic Community

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7K200 SATA OEM Specification
EMC

electromagnetic compatibility

ERP

Error Recovery Procedure

Esd

electrostatic discharge

FCC

Federal Communications Commission

FRU

field replacement unit

gravity, a unit of force

1 000 000 000 bits

1 000 000 000 bytes

GND

ground

hexadecimal

HDD

hard disk drive

hertz

Input

ILS

integrated lead suspension

imped

impedance

I/O

Input/Output

ISO

International Standards Organization

1,000 bytes

Kbit/mm

1,000 bits per mm

Kbit/sq-mm

1000 bits per square mm

KHz

kilohertz

LBA

logical block addressing

unit of A-weighted sound power

meter

max. or Max.

maximum

1,000,000 bytes

Mbps

1,000,000 Bit per second

Mb/sec

1,000,000 Bit per second

MB/sec

1,000,000 bytes per second

MHz

megahertz

MLC

Machine Level Control

millimeter

millisecond

us,

microsecond

Newton meter

No. or #

number

oct/min

oscillations per minute

Output

Open Drain Programmed Input/Output

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7K200 SATA OEM Specification
PIO
POH

power on hours

Pop.

population

P/N

part number

p-p

peak-to-peak

PSD

power spectral density

RES

radiated electromagnetic susceptibility

RFI

radio frequency interference

relative humidity

% RH

per cent relative humidity

RMS

root mean square

RPM

revolutions per minute

RST

reset

R/W

read/write

sec

second

Sect/Trk

sectors per track

SELV

secondary low voltage

S.M.A.R.T

Self-monitoring, analysis, and reporting technology

Trk.

track

TTL

transistor-transistor logic

Underwriters Laboratory

volt

VDE

Verband Deutscher Electrotechniker

watt

3-state

transistor-transistor tristate logic

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7K200 SATA OEM Specification

1.2

References

Serial ATA International Organization : Serial ATA Revision 2.6

1.3

General caution

Do not apply force to the top cover (See figure below).
Do not cover the breathing hole on the top cover (See figure below).
Do not touch the interface connector pins or the surface of the printed circuit board.
The drive can be damaged by shock or ESD (Electric Static Discharge). Any damages incurred to
the drive after removing it from the shipping package and the ESD protective bag are the
responsibility of the user

1.4

Drive handling precautions

Do not press on the drive cover during handling.

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2 Outline of the drive
・ 2.5-inch, 9.5-mm Height
・ Perpendicular Recording
・ Formatted capacities of 200GB, 160GB,120GB,100GB, and 80GB (512 bytes/sector)
・ SATA Interface conforming to Serial ATA International Organization: Serial ATA Revision
2.6(15-February-2007)
・ Integrated controller
・ No-ID recording format
・ Coding : 199/200
・ Multi zone recording
・ Enhanced ECC
・ 10 bit 40 symbol non Interleaved Read Solomon code
・ Non interleave On-The –Fly correction
・ Included 2 symbol system ECC
・ Segmented Buffer with write cache
・ 16384 KB - Upper 705 KB is used for firmware
・ Fast data transfer rate
・ HTS7220xxK9A300 model : up to 3.0Gbit/s
・ HTS7220xxK9SA00 model : up to 1.5Gbit/s
・ Media data transfer rate (max):
・ 876 Mb/s
・ Average seek time: 10 ms for read
・ Closed-loop actuator servo (Embedded Sector Servo)
・ Rotary voice coil motor actuator
・ Load/Unload mechanism
・ Mechanical latch
・ 0.8 Watts at idle state
・ Power on to ready
・ 4.0 sec (Typical)
・ Operating shock
・ 3430 m/sec2 (350 G)/2ms
・ 1764 m/sec2 (180G)/1ms
・ Nonoperating shock
・ 9800 m/sec2 (1000 G)/1ms
・ Full Data Encryption as optional (HTS7220xxK9SA00 model only)

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Part 1 Functional Specification

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7K200 SATA OEM Specification

3 Fixed disk subsystem description
3.1

Control Electronics

The control electronics works with the following functions:
SATA Interface Protocol
Embedded Sector Servo
No-ID (TM) formatting
Multizone recording
Code: 100/102
・ System ECC
・ Enhanced Adaptive Battery Life Extender
・ Full Data Encryption as optional(HTS7220xxK9SA00 model only)

3.2

Head disk assembly data

The following technologies are used in the drive:
Femto Slider
Perpendicular recording disk and write head
GMR head
Integrated lead suspension (ILS)
Load/unload mechanism
Mechanical latch

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7K200 SATA OEM Specification

4 Fixed disk characteristics
4.1

Formatted capacity by model number

Description
Physical Layout
Bytes per Sector
Sectors per Track
Number of Heads
Number of Disks
Logical Layout
Number of Heads
Number of Sectors/
Track
Number of Cylinders
Number of Sectors
Total Logical Data
Bytes
Description

HTS722020K9A300
HTS722020K9SA00

HTS722016K9A300
HTS722016K9SA00

HTS722012K9A300
HTS722012K9SA00

512
1209 (max)
4
2

512
1092 (max)
4
2

512
1092 (max)
3
2

16
63

16,383
390,721,968
200,049,647,616

16,383
312,581,808
160,041,885,696

16,383
234,441,648
120,034,123,776

HTS722010K9A300
HTS722010K9SA00

HTS722080K9A300
HTS722080K9SA00

Physical Layout
Bytes per Sector
512
Sectors per Track
1209 (max)
Number of Heads
2
Number of Disks
1
Logical Layout
Number of Heads
16
Number of Sectors/
63
Track
Number of Cylinders
16,383
Number of Sectors
195,371,568
Total Logical Data
100,030,242,816
Bytes
Table 1. Formatted capacity by model number.

512
1092 (max)
2
1
16
63
16,383
156,301,488
80,026,361,856

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7K200 SATA OEM Specification

4.2

Data sheet

Rotational Speed (RPM)
Data transfer rates (buffer to/from
media) (Mbps)
Data transfer rates (Gbit/sec)
Recording density (Kbit/mm) (Max)
(KBPI) (Max)
Track density (Ktrack/mm)(Max)
(KTPI)(Max)
Areal density (Gbit/sq-mm.- Max)
(Gbit/sq-inch - Max)
Number of zones
Table 2. Data sheet

4.3

200GB

160GB

120GB

100GB

80GB

7200
876

7200
695

7200
876

7200
695

1.5/3.0

994

903

994

903

164

146

164

146

164
24

132
24

164
24

132
24

Cylinder allocation

Data format is allocated by each head characteristics. Typical format is described below.

Zone
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
Table 3. Cylinder allocation

80GB/p Mid BIP-Mid TPI format
Cylinder
0
5280
10560
13760
18560
23360
26560
28960
34240
39040
43840
48640
53440
55840
61280
65280
69120
72480
78560
80160
85280
88960
92960
96800

5279
10559
13759
18559
23359
26559
28959
34239
39039
43839
48639
53439
55839
61279
65279
69119
72479
78559
80159
85279
88959
92959
96799
102399

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No. of
Sectors/Trk
1209
1209
1196
1170
1144
1131
1118
1092
1053
1040
1014
975
962
939
910
884
858
819
806
780
741
702
663
624

7K200 SATA OEM Specification

4.4

Performance characteristics

Drive performance is characterized by the following parameters:
Command Overhead
Mechanical Positioning
Seek Time
Latency
Data Transfer Speed
Buffering Operation (Look ahead/Write Cache)
Note: All the above parameters contribute to drive performance. There are other parameters which
contribute to the performance of the actual system. This specification defines the essential characteristics
of the drive. This specification does not include the system throughput as this is dependent upon the
system and the application.
The following table gives a typical value for each parameter. The detailed descriptions are found in
section 5.0.
Function
Average Random Seek Time - Read (ms)
Average Random Seek Time - Write (ms)
Rotational Speed (RPM)
Power-on-to-ready (sec)(Typical)
Command overhead (ms)
Disk-buffer data transfer (Mb/s) (max)
Buffer-host data transfer (Gbit/s) (max)
Table 4. Performance characteristics

4.4.1

10
11
7200
4.0
1.0
876
1.5/3.0

Command overhead

Command overhead time is defined as the interval from the time that a drive receives a command to the
time that the actuator starts its motion.

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7K200 SATA OEM Specification

4.4.2

Mechanical positioning

4.4.2.1 Average seek time (including settling)
Command Type
Typical (ms)
Read
10
Write
11
Table 5. Mechanical positioning performance

Max. (ms)
16
17

Typical and Max. are defined throughout the performance specification as follows:
Average of the drive population tested at nominal environmental and voltage conditions.
Maximum value measured on any one drive over the full range of the environmental and
voltage conditions. (See section 6.1, "Environment" on page 26 and section 6.2, "DC power
requirements" on page 28)
The seek time is measured from the start of motion of the actuator to the start of a reliable read or write
operation. A reliable read or write operation implies that error correction/recovery is not employed to
correct arrival problems. The Average Seek Time is measured as the weighted average of all possible
seek combinations.

Typical
Max.

max.

Σ (max. + 1 – n)(Tnin + Tnout)
n=1

Weighted Average = ––––––––––––––––––––––––––––
(max. + 1)(max)
Where: max.

4.4.2.2

= maximum seek length
n = seek length (1-to-max.)
Tnin
= inward measured seek time for an n-track seek
Tnout
= outward measured seek time for an n-track seek

Full stroke seek

Command Type
Read
Write
Table 6. Full stroke seek time

Typical (ms)
18.0
19.0

Max. (ms)
30.0
31.0

Full stroke seek time in milliseconds is the average time of 1000 full stroke seeks.

4.4.2.3

Single track seek time (without command overhead, including
settling)

Command Type
Read
Write
Table 7. Single track seek time

Typical (ms)
1.0
1.2

Maximum (ms)
4.0
4.5

Single track seek is measured as the average of one (1) single track seek from every track in both
directions (inward and outward).

4.4.2.4

Average latency

Rotational Speed
(RPM)
7200
Table 8. Latency time

Time for one revolution
(ms)
8.3

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Average Latency
(ms)
4.2

7K200 SATA OEM Specification

4.4.2.5

Drive ready time

Condition
Power On To Ready
Table 9. Drive ready time

Typical (sec)
4.0

Max. (sec)
9.5

The condition in which the drive is able to perform a media access command
(for example—read, write) immediately.
Power On To Ready This includes the time required for the internal self diagnostics.
Ready

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7K200 SATA OEM Specification

4.4.3

Operating modes

Operating mode

Description
Start up time period from spindle stop or power down.

Spin-Up

Seek operation mode

Seek

Write operation mode

Write

Read operation mode

Read

The device is capable of responding immediately to idle media access requests. All
electronic components remain powered and the full frequency servo remains
operational.
The device is capable of responding immediately to media access requests. Some
circuitry—including servo system and R/W electronics—is in power saving mode.
The head is parked near the mid-diameter the disk without servoing.
Active idle
A device in Active idle mode may take longer to complete the execution of a
command because it must activate that circuitry.
The head is unloaded onto the ramp position. The spindle motor is rotating at full
Low power idle
speed.
The device interface is capable of accepting commands. The spindle motor is
Standby
stopped. All circuitry but the host interface is in power saving mode.
The execution of commands is delayed until the spindle becomes ready.
The device requires a soft reset or a hard reset to be activated. All electronics,
Sleep
including spindle motor and host interface, are shut off.
Table 10. Operating mode
Performance idle

4.4.3.1
From

Mode transition time
To

Standby
Idle
Table 11. Drive ready time

4.4.3.2

Transition
Time (typ)
3.0

Transition Time
(max.)
9.5

Operating mode at power on

The device goes into Idle mode after power on as an initial state.

4.4.3.3

Adaptive power save control

The transient timing from Performance Idle mode to Active Idle mode and Active Idle mode to Low
Power Idle mode is controlled adaptively according to the access pattern of the host system. The
transient timing from Low Power Idle mode to Standby mode is also controlled adaptively, if it is
allowed by Set Features Enable Advanced Power Management subcommand.

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7K200 SATA OEM Specification

5 Data integrity
5.1

Data loss on power off

Data loss will not be caused by a power off during any operation except the write operation.
A power off during a write operation causes the loss of any received or resident data that has not
been written onto the disk media.
A power off during a write operation might make a maximum of one sector of data unreadable. This
state can be recovered by a rewrite operation.

5.2

Write Cache

When the write cache is enabled, the write command may complete before the actual disk write operation
finishes. This means that a power off, even after the write command completion, could cause the loss of
data that the drive has received but not yet written onto the disk.
In order to prevent this data loss, confirm the completion of the actual write operation prior to the power
off by issuing a
Soft reset
COMRESET
Flush Cache command
Standby command
Standby Immediate command
Sleep command
Confirm the command’s completion.

5.3

Equipment status

The equipment status is available to the host system any time the drive is not ready to read, write, or seek.
This status normally exists at the power-on time and will be maintained until the following conditions are
satisfied:
The access recalibration/tuning is complete.
The spindle speed meets the requirements for reliable operation.
The self-check of the drive is complete.
The appropriate error status is made available to the host system if any of the following conditions occur
after the drive has become ready:
The spindle speed lies outside the requirements for reliable operation.
The occurrence of a Write Fault condition.

5.4

WRITE safety

The drive ensures that the data is written into the disk media properly. The following conditions are
monitored during a write operation. When one of these conditions exceeds the criteria, the write operation
is terminated and the automatic retry sequence is invoked.
Head off track
External shock
Low supply voltage
Spindle speed out of tolerance
Head open/short

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7K200 SATA OEM Specification

5.5

Data buffer test

The data buffer is tested at power on reset and when a drive self-test is requested by the host. The test
consists of a write/read '00'x and 'ff'x pattern on all buffers.

5.6

Error recovery

Errors occurring on the drive are handled by the error recovery procedure.
Errors that are uncorrectable after application of the error recovery procedure are reported to the host
system as nonrecoverable errors.

5.7

Automatic reallocation

The sectors that show some errors may be reallocated automatically when specific conditions are met.
The drive does not report any auto reallocation to the host system. The conditions for auto reallocation
are described below.

5.7.1

Nonrecovered write errors

When a write operation cannot be completed after the Error Recovery Procedure (ERP) is fully carried out,
the sectors are reallocated to the spare location. An error is reported to the host system only when the
write cache is disabled and the auto reallocation has failed.

5.7.2

Nonrecoverable read error

When a read operation fails after ERP is fully carried out, a hard error is reported to the host system. This
location is registered internally as a candidate for the reallocation. When a registered location is specified
as a target of a write operation, a sequence of media verification is performed automatically. When the
result of this verification meets the required criteria, this sector is reallocated.

5.7.3

Recovered read errors

When a read operation for a sector fails and is recovered at the specific ERP step, the sector is
reallocated automatically. A media verification sequence may be run prior to the reallocation according to
the predefined conditions.

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7K200 SATA OEM Specification

5.8

ECC

The 10 bit 40 symbol non interleaved ECC processor provides user data verification and correction
capability. The first 6 symbol of ECC are 4 check symbols for user data and the 2 symbol system ECC.
The other 34 symbols are Read Solomon ECC. Hardware logic corrects up to 16 symbols(20 bytes)
errors on-the-fly.
2 symbol System ECC is generated when HDC receives user data from HOST, and can correct up to 1
symbol(10bit) errors on-the-fly when one transfers to HOST.

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7K200 SATA OEM Specification

6 Specification
6.1
6.1.1

Environment
Temperature and humidity

Operating conditions
Temperature
5 to 55°C (See note below)
Relative humidity
8 to 90% noncondensing
Maximum wet bulb temperature
29.4°C noncondensing
Maximum temperature gradient
20°C/hour
Altitude
–300 to 3048 m (10,000 ft)
Nonoperating conditions
Temperature
–40 to 65°C
Relative humidity
5 to 95% noncondensing
Maximum wet bulb temperature
40°C noncondensing
Maximum temperature gradient
20°C/hour
Altitude
–300 to 12,192 m (40,000 ft)
Table 12. Environmental condition
The system is responsible for providing sufficient air movement to maintain surface temperatures below
60°C at the center of top cover and below 63°C at the center of the drive circuit board assembly.
The maximum storage period in the shipping package is one year.

Specification (Environment)
100
41'C/95%

90
31'C/90%

W etBulb 40'C

Relative Humidity (%)

80
70
W etBulb29.4'C

Non Operating

Operating
40
65'C/23%

30
20
55'C/15%

10
0
-45

-35

-25

-15

-5

Temperature (degC)

Figure 1. Limits of temperature and humidity

6.1.2

Corrosion test

The hard disk drive must be functional and show no signs of corrosion after being exposed to a
temperature humidity stress of 50°C/90%RH (relative humidity) for one week followed by a temperature
and humidity drop to 25'C/40%RH in 2 hours.

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7K200 SATA OEM Specification

6.1.3

Radiation noise

The disk drive shall work without degradation of the soft error rate under the following magnetic flux
density limits at the enclosure surface.
Frequency (KHz)
0–60
61–100
101–200
201–400
Table 13. Magnetic flux density limits

6.1.4

Limits (uT RMS)
500
250
100
50

Conductive noise

The disk drive shall work without soft error degradation in the frequency range from DC to 20 Mhz
injected through any two of the mounting screw holes of the drive when an AC current of up to 45 mA
(p-p) is applied through a 50-ohm resistor connected to any two mounting screw holes.

6.1.5

Magnetic fields

The disk drive will withstand radiation and conductive noise within the limits shown below. The test
method is defined in the Noise Susceptibility Test Method specification, P/N 95F3944.

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7K200 SATA OEM Specification

6.2

DC power requirements

Connection to the product should be made in a safety extra low voltage (SELV) circuits. The voltage
specifications are applied at the power connector of the drive.
Item
Nominal supply
Supply voltage
Power supply ripple (0–20
1
MHz)
2
Tolerance
Supply rise time

Requirements
+5 Volt dc
–0.3 Volt to 6.0 Volt
100 mV p-p max.
±5%
1–100 ms

Watts (RMS Typical)
3
Performance Idle average
Active Idle average
Low Power Idle average
4
Read average
Write average
5
Seek average
Standby
Sleep
6
Startup (maximum peak)
Average from power on to
ready

2.0
1.0
0.8
2.3
2.3
2.6
0.25
0.2
5.5
3.8

Table 14. DC Power requirements

Footnotes:
1.

The maximum fixed disk ripple is measured at the 5 volt input of the drive.

The disk drive shall not incur damage for an over voltage condition of +25% (maximum
duration of 20 ms) on the 5 volt nominal supply.

The idle current is specified at an inner track.

The read/write current is specified based on three operations of 63 sector read/write per
100 ms.

The seek average current is specified based on three operations per 100 ms.

The worst case operating current includes motor surge.

“Typical” mean average of the drive population tested at nominal environmental and
voltage conditions.

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7K200 SATA OEM Specification

6.2.1
Capacity

Power consumption efficiency
200GB

160GB

120GB

100GB

80GB

Power Consumption Efficiency
0.0040
(Watts/GB)
Table 15. Power consumption efficiency

0.0050

0.0067

0.0080

0.0100

Note: Power consumption efficiency is calculated as Power Consumption of Low Power Idle Watt/
Capacity (GB).

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7K200 SATA OEM Specification

6.3
6.3.1

Reliability
Data reliability
Probability of not recovering data is 1 in 1013 bits read
ECC implementation

On-the-fly correction performed as a part of read channel function recovers up to 16 symbols of error in 1
sector (1 symbol is 10 bits).

6.3.2

Failure prediction (S.M.A.R.T.)

The drive supports Self-monitoring, analysis and reporting technology (S.M.A.R.T.) function. The details
are described in section 11.8, "S.M.A.R.T. Function" on page 84 and in Section 13.32, "S.M.A.R.T.
Function Set (B0h)" on page 163.

6.3.3

Cable noise interference

To avoid any degradation of performance throughput or error when the interface cable is routed on top or
comes in contact with the HDA assembly, the drive must be grounded electrically to the system frame by
four screws. The common mode noise or voltage level difference between the system frame and power
cable ground or AT interface cable ground should be in the allowable level specified in the power
requirement section.

6.3.4

Service life and usage condition

The drive is designed to be used under the following conditions:
The drive should be operated within specifications of shock, vibration, temperature, humidity, altitude,
and magnetic field.
The drive should be protected from ESD.
The breathing hole in the top cover of the drive should not be covered.
Force should not be applied to the cover of the drive.
The specified power requirements of the drive should be satisfied.
The drive frame should be grounded electrically to the system through four screws.
The drive should be mounted with the recommended screw depth and torque.
The interface physical and electrical requirements of the drive should satisfy ATA-6.
The power-off sequence of the drive should comply with the
sequence.”

6.4.6.2,"Required power-off

Service life of the drive is approximately 5 years or 20,000 power on hours, whichever comes first, under
the following assumptions:
Less than 333 power on hours per month.
Seeking/Writing/Reading operation is less than 20% of power on hours.
This does not represent any warranty or warranty period. Applicable warranty and warranty period are
covered by the purchase agreement.

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7K200 SATA OEM Specification

Preventive maintenance

6.3.5
None.

Load/unload

6.3.6

The product supports a minimum of 600,000 normal load/unloads.
Load/unload is a functional mechanism of the hard disk drive. It is controlled by the drive micro code.
Specifically, unloading of the heads is invoked by the following commands:
Standby
Standby immediate
Sleep
Load/unload is also invoked as one of the idle modes of the drive.
The specified start/stop life of the product assumes that load/unload is operated normally, not in
emergency mode.

6.3.6.1

Emergency unload

When hard disk drive power is interrupted while the heads are still loaded the micro code cannot operate
and the normal 5-volt power is unavailable to unload the heads. In this case, normal unload is not
possible. The heads are unloaded by routing the back EMF of the spinning motor to the voice coil. The
actuator velocity is greater than the normal case and the unload process is inherently less controllable
without a normal seek current profile.
Emergency unload is intended to be invoked in rare situations. Because this operation is inherently
uncontrolled, it is more mechanically stressful than a normal unload.
The drive supports a minimum of 20,000 emergency unloads.

6.3.6.2

Required Power-Off Sequence

The required host system sequence for removing power from the drive is as follows:
Step 1: Issue one of the following commands.
Standby
Standby immediate
Sleep
Note: Do not use the Flush Cache command for the power off sequence because this command
does not invoke Unload.
Step 2: Wait until the Command Complete status is returned.
In a typical case 500 ms are required for the command to finish completion; however, the host system
time out value needs to be 30 seconds considering error recovery time. Refer to section 15.0,
"Time-out values," on page 172.
Step 3: Terminate power to HDD.
This power-down sequence should be followed for entry into any system power-down state, system
suspend state, or system hibernation state. In a robustly designed system, emergency unload is limited
to rare scenarios, such as battery removal during operation.

6.3.6.3

Power switch design considerations

In systems that use the Travelstar 7K200 consideration should be given to the design of the system
power switch.
Hitachi recommends that the switch operate under control of the BIOS, as opposed to being hardwired.
The same recommendation is made for cover-close switches. When a hardwired switch is turned off,

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7K200 SATA OEM Specification
emergency unload occurs, as well as the problems cited in section 5.1, "Data loss by power off" on page
19 and section 5.2, “Write Cache” on page 19.

6.3.6.4

Test considerations

Start/stop testing is classically performed to verify head/disk durability. The heads do not land on the disk,
so this type of test should be viewed as a test of the load/unload function.
Start/Stop testing should be done by commands through the interface, not by power cycling the drive.
Simple power cycling of the drive invokes the emergency unload mechanism and subjects the HDD to
nontypical mechanical stress.
Power cycling testing may be required to test the boot-up function of the system. In this case HItachi
recommends that the power-off portion of the cycle contain the sequence specified in section 6.4.6.2,
"Required Power-Off Sequence” on page 29. If this is not done, the emergency unload function is
invoked and nontypical stress results.

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7K200 SATA OEM Specification

6.4
6.4.1

Mechanical specifications
Physical dimensions and weight

The following figure lists the dimensions for the drive.
Model
Height (mm)
200GB, 160 GB, 120 GB models
9.5±0.2
100GB , 80 GB models
9.5±0.2
Table 16. Physical dimensions and weight

6.4.2

Width (mm)
69.85±0.25
69.85±0.25

Mounting hole locations

The mounting hole locations and size of the drive are shown below.

Figure 2. Mounting hole locations

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Length (mm)
100.2±0.25
100.2±0.25

Weight (gram)
115 Max
110 Max

7K200 SATA OEM Specification

6.4.3

Connector and jumper description

Connector specifications are included in section 7.2, "Interface connector" on page 41.

6.4.4

Mounting orientation

The drive will operate in all axes (six directions) and will stay within the specified error rates when tilted ±5
degrees from these positions.
Performance and error rate will stay within specification limits if the drive is operated in the other
permissible orientations from which it was formatted. Thus a drive formatted in a horizontal orientation will
be able to run vertically and vice versa.
The recommended mounting screw torque is 0.3±0.05 Nm.
The recommended mounting screw depth is 3.0±0.3 mm for bottom and 3.5±0.5 mm for horizontal
mounting.
The user is responsible for using the appropriate screws or equivalent mounting hardware to mount
the drive securely enough to prevent excessive motion or vibration of the drive at seek operation or
spindle rotation.

6.4.5

Load/unload mechanism

The head load/unload mechanism is provided to protect the disk data during shipping, movement, or
storage. Upon power down, a head unload mechanism secures the heads at the unload position. See
section 6.5.4, "Nonoperating shock" on page 36 for additional details.

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7K200 SATA OEM Specification

6.5

Vibration and shock

All vibration and shock measurements in this section are for drives without mounting attachments for
systems. The input level shall be applied to the normal drive mounting points.
Vibration tests and shock tests are to be conducted by mounting the drive to a table using the bottom four
mounting holes.

6.5.1

Operating vibration

The drive will operate without a hard error while being subjected to the following vibration levels.

6.5.1.1 Random vibration
The test consists of 30 minutes of random vibration using the power spectral density (PSD) levels below.
The vibration test level is 6.57 m/sec2 RMS (Root Mean Square) (0.67 G RMS).
Random vibration PSD profile Breakpoint
Hz
m x 10n (m2/sec4)/Hz
5
1.9 x E–3
17
1.1 x E–1
45
1.1 x E–1
48
7.7 x E–1
62
7.7 x E–1
65
9.6 x E–2
150
9.6 x E–2
200
4.8 x E–2
500
4.8 x E–2

Table 17. Random vibration PSD profile breakpoints (operating)

6.5.1.2

Swept sine vibration

Swept sine vibration (zero to peak 5 to
500 to 5 Hz sine wave)
9.8 m/sec2 (1 G) (5-500 Hz)
Table 18. Swept sine vibration

Sweep rate (oct/min)
1.0

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7K200 SATA OEM Specification

Nonoperating vibration

6.5.2

The disk drive withstands the following vibration levels without any loss or permanent damage.

6.5.2.1

Random vibration

The test consists of a random vibration applied in each of three mutually perpendicular axes for a duration
of 15 minutes per axis. The PSD levels for the test simulating the shipping and relocation environment is
shown below.
Hz
2.5
5
40
500
Table 19. Random Vibration PSD Profile Breakpoints (nonoperating)

(m/sec2)/Hz
0.096
2.88
1.73
1.73

Note: Overall RMS level of vibration is 29.50 m/sec2 (3.01 G).

6.5.2.2

Swept sine vibration

49 m/sec2 (5 G) (zero-to-peak), 10 to 500 to 10 Hz sine wave
0.5 oct/min sweep rate
25.4 mm (peak-to-peak) displacement, 5 to 10 to 5 Hz

6.5.3

Operating shock

The hard disk drive meets the criteria in the table below while operating under these conditions:
The shock test consists of 10 shock inputs in each axis and direction for a total of 60.
There must be a minimum delay of 3 seconds between shock pulses.
The disk drive will operate without a hard error while subjected to the following half-sine shock pulse.
Duration of 1 ms
2

1764 m/sec (180 G)
Table 20. Operating shock

Duration of 2 ms
3430 m/sec2 (350 G)

The input level shall be applied to the normal disk drive subsystem mounting points used to secure the
drive in a normal system.

6.5.4

Nonoperating shock

The drive withstands the following half-sine shock pulse without any data loss or permanent damage.
Duration of 1 ms
2

9800 m/sec (1000 G)
Table 21. Nonoperating shock

Duration of 11 ms
1470 m/sec2 (150 G)

The shocks are applied for each direction of the drive for three mutually perpendicular axes, one axis at a
time. Input levels are measured on a base plate where the drive is attached with four screws.

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6.6
6.6.1

Acoustics
Sound power level

The criteria of A-weighted sound power level are described below.
Measurements are to be taken in accordance with ISO 7779. The mean of the sample of 40 drives is to
be less than the typical value. Each drive is to be less than the maximum value. The drives are to meet
this requirement in both board down orientations.
A-weighted Sound Power

Typical (Bels)

Maximum (Bels)

Idle

2.5.

2.8

Operating

2.9

3.4

Idle

2.2

2.5

Operating

2.6

3.1

200GB, 160GB 120GB models

100GB, 80GBmodels

Table 22. Weighted sound power
The background power levels of the acoustic test chamber for each octave band are to be recorded.
Sound power tests are to be conducted with the drive supported by spacers so that the lower surface of
the drive be located 25±3 mm above from the chamber floor. No sound absorbing material shall be used.
The acoustical characteristics of the disk drive are measured under the following conditions:
Mode definitions
Idle mode: Power on, disks spinning, track following, unit ready to receive and respond to control line
commands.
Operating mode: Continuous random cylinder selection and seek operation of the actuator with a
dwell time at each cylinder. The seek rate for the drive can be calculated as shown below.
Ns = 0.4/(Tt + T1)
where:
Ns = average seek rate in seeks/s
Tt = published seek time from one random track to another without including rotational
latency
T1= equivalent time in seconds for the drive to rotate by half a revolution

6.6.2

Discrete tone penalty

Discrete tone penalties are added to the A-weighted sound power (Lw) with the following formula only
when determining compliance.
Lwt(spec) = Lw + 0.1Pt + 0.3 < 4.0 (Bels)
where
Lw = A-weighted sound power level
Pt = Value of desecrate tone penalty = dLt – 6.0(dBA)
dLt = Tone-to-noise ratio taken in accordance with ISO 7779 at each octave band.

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6.7

Identification labels

The following labels are affixed to every drive:
A label which is placed on the top of the head disk assembly containing the statement "Made by
Hitachi" or equivalent, part number, EC number, and FRU number.
A bar code label which is placed on the disk drive based on user request. The location on the disk
drive is to be designated in the drawing provided by the user.
Labels containing the vendor's name, disk drive model number, serial number, place of manufacture,
and UL/CSA logos.
The presence of labels containing jumper information depends on the customer.

6.8

Electromagnetic compatibility

When installed in a suitable enclosure and exercised with a random accessing routine at maximum data
rate, the drive meets the following worldwide electromagnetic compatibility (EMC) requirements:
・ United States Federal Communications Commission (FCC) Rules and Regulations (Class B),
Part 15. RFI Suppression German National Requirements
・ RFI Japan VCCI, Requirements of HITACHI products
・ EU EMC Directive, Technical Requirements and Conformity Assessment Procedures

6.8.1

CE Mark

The product is certified for compliance with EC directive 89/336/EEC. The EC marking for the certification
appears on the drive.

6.8.2

C-Tick Mark

The product complies with the Australian EMC standard "Limits and methods of measurement of radio
disturbance characteristics of information technology equipment, AS/NZS 3548:1995 Class B."

6.8.3

BSMI Mark

The product complies with the Taiwan EMC standard “Limits and methods of measurement of radio
disturbance characteristics of information technology equipment, CNS 13438 Class B.”

6.8.4

MIC Mark

The product complies with the Korea EMC standard. The regulation for certification of information and
communication equipment is based on “Telecommunications Basic Act” and “Radio Waves Act” Korea
EMC requirment are based technically on CISPR22:1993-12 measurement standards and limits. MIC
standards are likewise based on IEC standards.

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6.9
6.9.1

Safety
UL and CSA approval

All models of the Travelstar 7K200 are qualified per UL60950-1:2003

6.9.2

IEC compliance

All models of the Travelstar 7K200 comply with IEC 60950-1:2001.

6.9.3

German Safety Mark

All models of the Travelstar 7K200 are approved by TUV on Test Requirement: EN 60950-1:2001, but the
GS mark has not been obtained.

6.9.4

Flammability

The printed circuit boards used in this product are made of material with a UL recognized
flammability rating of V-1 or better. The flammability rating is marked or etched on the board. All
other parts not considered electrical components are made of material with a UL recognized
flammability rating of V-1 or better except minor mechanical parts.

6.9.5

Secondary circuit protection

This product utilizes printed circuit wiring that must be protected against the possibility of
sustained combustion due to circuit or component failures as defined in C-B 2-4700-034 (Protection
Against Combustion). Adequate secondary over current protection is the responsibility of the using
system.
The user must protect the drive from its electrical short circuit problem. A 10 amp limit is required
for safety purpose.

6.10 Packaging
Drives are packed in ESD protective bags and shipped in appropriate containers.

6.11

Substance restriction requirements

The product complies with the Directive 2002/95/EC of the European Parliament on the restrictions
of the use of the certain hazardous substances in electrical and electronic equipment (RoHS).

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7 Electrical interface specifications
7.1

Cabling

The maximum cable length from the host system to the hard disk drive plus circuit pattern length in the
host system shall not exceed 1 meter.

7.2

Interface connector

The figure below shows the physical pin location.

Figure 3. Interface connector pin assignments
All pins are in a single row, with a 127 mm(.050”) pitch.
The comments on the mating sequence in Table in the section 7.3 apply to the case of back-plane
blind-mate connector only. In this case, the mating sequences are:(1)the ground pins P4 and
P12;(2) the pre-charge power pins and the other ground pins; and (3) the signal pins and the rest
of the power pins.
There are three power pins for each voltage. One pin from each voltage is used for pre-charge in
the backplane blind-mate situation.
If a device uses 3.3V, then all V33 pins must be terminated. Otherwise, it is optional to
terminate any of the V33 pins
If a device uses 5.0V, then all V5 pins must be terminated. Otherwise, it is optional to terminate
any of the V5 pins
If a device uses 12.0V, then all V12 pins must be terminated. Otherwise, it is optional to
terminate any of the V12 pins.

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7.3

Signal definitions

The pin assignments of interface signals are listed as follows:

Signal

No.
S1
S2
S3
S4
S5
S6
S7

GND
A+
AGnd
BB+
Gnd

Plug Connector pin definition
2nd mate
Differential signal A from Phy
2nd mate
Differential signal B from Phy

2nd mate
Key and spacing separate signal and power
segments
P1
V33
3.3V power
P2
V33
3.3V power
P3
V33
3.3V power, pre-charge, 2nd Mate
P4
Gnd
1st mate
P5
Gnd
2nd mate
P6
Gnd
2nd mate
P7
V5
5V power,pre-charge,2nd Mate
P8
V5
5V power
Power
P9
V5
5V power
P10 Gnd
2nd mate
P11 DAS/DSS
Device Activity Signal / Disable Staggered
Spinup1
P12 Gnd
1st mate
P13 V12
12V power,pre-chage,2nd mate
P14 V12
12V power
P15 V12
12V power
Table 23. Interface connector pins and I/O signals

Signal
Gnd
RX+
RXGnd
TXTX+
Gnd

I/O
Input
Input
Output
Output

3.3V
3.3V
3.3V
Gnd
Gnd
Gnd
5V
5V
5V
Gnd
Note 1
Gnd
V12
V12
V12

Note 1;
Pin P11 is used by the drive to provide the host with an activity indication and by the host to
indicate whether staggered spinup should be used.
The signal the drive provides for activity indication is a low-voltage low-current driver.
If pin P11 is asserted low the drive shall disable staggered spin-up and immediately initiate
spin-up. If pin P11 is not connected in the host (floating), the drive shall enable staggered spin-up.

7.3.1

TX+ / TX-

These signal are the outbound high-speed differential signals that are connected to the serial ATA
cable

7.3.2

RX+ / RX-

These signals are the inbound high-speed differential signals that are connected to the serial ATA
cable.
The following standard shall be referenced about signal specifications.
Serial ATA International Organization: Serial ATA Revision 2.6 15-February -2007

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Out of band signaling

7.3.3

Figure 4 shows the timing of COMRESET, COMINIT and COMWAKE.

COMRESET/COMINIT

COMWAKE

PARAMETER
DESCRIPTION

Nominal (ns)

ALINE primitives

106.7

Spacing

320

ALIGN primitives

106.7

Psacing

106.7

Figure 4. Parameter descriptions

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Part 2 Interface Specification

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8 General
8.1

Introduction

This specification describes the host interface of HTS7220XXK9SA00 / HTS7220XXK9A300.
The interface conforms to following Working Document of Information technology with certain
limitations described in the chapter 9 “Deviations from Standard” on Page 45
Serial ATA International Organization : Serial ATA Revision 2.6 dated on 15 February 2007
AT Attachment 8 – ATA/ATAPI Command Set (ATA8-ACS) Revision 3f dated on 11 December 2006
HTS7220XXK9SA00 / HTS7220XXK9A300 support following functions as Vendor Specific Function.
•
•

8.2
Device
Host
INTRQ

Format Unit Function
SENSE CONDITION command

Terminology
Device indicates HTS7220XXK9SA00 / HTS7220XXK9A300
Host indicates the system that the device is attached to.
Interrupt request (Device or Host)

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9 Deviations from Standard
The device conforms to the referenced specifications, with deviations described below.
The interface conforms to the Working Document of Information Technology, AT Attachment 8 –
ATA/ATAPI Command Set (ATA/ATAPI8-ACS) Revision 3f dated 11 Dec. 2006, with deviation as
follows:
S.M.A.R.T. Return Status

Check Power Mode

S.M.A.R.T. RETURN STATUS subcommand does not check advisory attributes.
That is, the device will not report threshold exceeded condition unless pre-failure
attributes exceed their corresponding thresholds. For example, Power-On Hours
Attribute never results in negative reliability status.
Check Power Mode command returns FFh to Sector Count Register when the device
is in Idle mode. This command does not support 80h as the return value.

10 Physical Interface
Physical Interface is described in Functional Specification part.

11 Registers
In Serial ATA, the host adapter contains a set of registers that shadow the contents of the traditional
device registers, referred to as the Shadow Register Block. Shadow Register Block registers are
interface registers used for delivering commands to the device or posting status from the device.
About details, please refer to the Serial ATA Specification.
In the following cases, the host adapter sets the BSY bit in its shadow Status Register and transmits
a FIS to the device containing the new contents.
•
•
•

Command register is written in the Shadow Register Block
Device Control register is written in the Shadow Register Block with a change of state of the
SRST bit
COMRESET is requested

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11.1 Register naming convention
This specification uses the same naming conventions for the Command Block Registers as the
ATA8-ACS standard. However, the register naming convention is different from that uses in the
Serial ATA 2.6 specification. The following table defines the corresponding of the register names
used in this specification with those used in the Serial ATA 2.6 specification.

Serial ATA register
name

Features

Feature current

Features (exp)

Feature previous

Sector count

Sector count current

Sector count HOB=0

Sector count (exp)

Sector count previous

Sector count HOB=1

LBA low

LBA low current

LBA low HOB=0

LBA low (exp)

LBA low previous

LBA low HOB=1

LBA mid

LBA mid current

LBA mid HOB=0

LBA mid (exp)

LBA mid previous

LBA mid HOB=1

LBA high

LBA high current

LBA mid HOB=0

LBA high (exp)

LBA high previous

LBA mid HOB=1

Device

Command

N/A

Control

Device Control

N/A

Status

N/A

Status

Error

N/A

Error

Table 24 Register naming convention and correspondence

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11.2 Command register
This register contains the command code being sent to the device. Command execution begins
immediately after this register is written. The command set is shown in “Table 40 Command set” on
page 74.
All other registers required for the command must be set up before writing the Command Register.

11.3 Device Control Register
Device Control Register
7
6
5
Table 25 Device Control Register
Bit Definitions
SRST (RST)

-IEN

4
-

3
1

2
SRST

1
-IEN

0
0

Software Reset. The device is held reset when RST=1. Setting RST=0 reenables the device.
The host must set RST=1 and wait for at least 5 microseconds before setting RST=0, to
ensure that the device recognizes the reset.
Interrupt Enable. When IEN=0, and the device is selected, device interrupts to the host will
be enabled. When IEN=1, or the device is not selected, device interrupts to the host will be
disabled.

11.4 Device Register
Device Register
7
6
L
Table 26 Device Register

5
-

4
0

3
HS3

2
HS2

1
HS1

0
HS0

This register contains the device and head numbers.
Bit Definitions
L
HS3,HS2,HS1,HS0

Binary encoded address mode select. When L=0, addressing is by CHS mode. When L=1,
addressing is by LBA mode.
The HS3 through HS0 contain bits 24-27 of the LBA. At command completion, these bits
are updated to reflect the current LBA bits 24-27.

11.5 Error Register
Error Register
7
6
CRC
UNC
Table 27 Error Register

5
0

4
IDNF

3
0

2
ABRT

1
TK0NF

0
AMNF

This register contains status from the last command executed by the device, or a diagnostic code.
At the completion of any command except Execute Device Diagnostic, the contents of this register
are valid always even if ERR=0 in the Status Register.
Following a power on, a reset, or completion of an Execute Device Diagnostic command, this register
contains a diagnostic code. See “Table 31 Diagnostic Codes” on Page 51 for the definition.
Bit Definitions
ICRCE (CRC)
UNC

Interface CRC Error. CRC=1 indicates a CRC error has occurred on the data bus during a
Ultra-DMA transfer.
Uncorrectable Data Error. UNC=1 indicates an uncorrectable data error has been
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IDNF (IDN)
ABRT (ABT)
TK0NF (T0N)
AMNF (AMN)

encountered.
ID Not Found. IDN=1 indicates the requested sector’s ID field could not be found.
Aborted Command. ABT=1 indicates the requested command has been aborted due to a
device status error or an invalid parameter in an output register.
Track 0 Not Found. T0N=1 indicates track 0 was not found during a Recalibrate command.
Address Mark Not Found. AMN=1 indicates the data address mark has not been found after
finding the correct ID field for the requested sector.
This bit is obsolete.

11.6 Features Register
This register is command specific. This is used with the Set Features command, S.M.A.R.T. Function
Set command and Format Unit command.

11.7 LBA High Register
This register contains Bits 16-23. At the end of the command, this register is updated to reflect the
current LBA Bits 16-23.
When 48-bit addressing commands are used, the “most recently written” content contains LBA Bits
16-23, and the “previous content” contains Bits 40-47. The 48-bit Address feature set is described in
“12.14 48-bit Address Feature Set”.

11.8 LBA Low Register
This register contains Bits 0-7. At the end of the command, this register is updated to reflect the
current LBA Bits 0-7.
When 48-bit commands are used, the “most recently written” content contains LBA Bits 0-7, and the
“previous content” contains Bits 24-31.

11.9 LBA Mid Register
This register contains Bits 8-15. At the end of the command, this register is updated to reflect the
current LBA Bits 8-15.
When 48-bit addressing commands are used, the “most recently written” content contains LBA Bits
8-15, and the “previous content” contains Bits 32-39.

11.10

Sector Count Register

This register contains the number of sectors of data requested to be transferred on a read or write
operation between the host and the device. If the value in the register is set to 0, a count of 256
sectors (in 28-bit addressing) or 65,536 sectors (in 48-bit addressing) is specified.
If the register is zero at command completion, the command was successful. If not successfully
completed, the register contains the number of sectors which need to be transferred in order to
complete the request.
The contents of the register are defined otherwise on some commands. These definitions are given in
the command descriptions.

11.11

Status Register
Status Register
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7K200 SATA OEM Specification
7
6
BSY
DRDY
Table 28 Status Register

5
DF

4
DSC

3
DRQ

2
CORR

1
IDX

0
ERR

This register contains the device status. The contents of this register are updated whenever an error
occurs and at the completion of each command.
If the host reads this register when an interrupt is pending, it is considered to be the interrupt
acknowledge. Any pending interrupt is cleared whenever this register is read.
If BSY=1, no other bits in the register are valid.
Bit Definitions
BSY

DRDY (RDY)
DF
DSC

DRQ

CORR (COR)
IDX
ERR

Busy. BSY=1 whenever the device is accessing the registers. The host should not read or
write any registers when BSY=1. If the host reads any register when BSY=1, the contents of
the Status Register will be returned.
Device Ready. RDY=1 indicates that the device is capable of responding to a command.
RDY will be set to 0 during power on until the device is ready to accept a command.
Device Fault. DF=1 indicates that the device has detected a write fault condition. DF is set to
0 after the Status Register is read by the host.
Device Seek Complete. DSC=1 indicates that a seek has completed and the device head is
settled over a track. DSC is set to 0 by the device just before a seek begins. When an error
occurs, this bit is not changed until the Status Register is read by the host, at which time the
bit again indicates the current seek complete status.
When the device enters into or is in Standby mode or Sleep mode, this bit is set by device in
spite of not spinning up.
Data Request. DRQ=1 indicates that the device is ready to transfer a word or byte of data
between the host and the device. The host should not write the Command register when
DRQ=1.
Corrected Data. Always 0.
Index. Always 0
ERR=1 indicates that an error occurred during execution of the previous command. The
Error Register should be read to determine the error type. The device sets ERR=0 when the
next command is received from the host.

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12 General Operation Descriptions
12.1 Reset Response
There are three types of reset in ATA as follows:
The device executes a series of electrical circuitry diagnostics, spins up the HDA,
tests speed and other mechanical parametric, and sets default values.
COMRESET is issued in Serial ATA bus.
COMRESET
The device resets the interface circuitry as well as Soft Reset.
SRST bit in the Device Control Register is set, then is reset.
Soft Reset (Software Reset)
The device resets the interface circuitry according to the Set Features requirement.
The actions of each reset are shown in “Table 29 Reset Response Table” on Page 50
Power On Reset (POR)

Aborting Host interface
Aborting Device operation
Initialization of hardware
Internal diagnostic
Starting spindle motor
Initialization of registers (*2)
Reverting programmed parameters to default
- Number of CHS (set by Initialize Device Parameter)
- Multiple mode
- Write cache
- Read look-ahead
- ECC bytes
- Volatile max address
Power mode
Reset Standby timer value

POR

COMRESET

Soft Reset

O
O
(*5)
O
O

o
(*1)
x
x
x
o
(*6)

o
(*1)
x
x
x
o
(*3)

(*5)
o

(*4)
o

(*4)
x

O ---- execute
X ---- not execute

Note.
(*1)
Execute after the data in write cache has been written.
(*2)
Default value on POR is shown in “Table 30 Default Register Values” on Page 51.
(*3)
The Set Features command with Feature register = CCh enables the device to revert these
parameters to the power on defaults.
(*4)
In the case of sleep mode, the device goes to standby mode. In other case, the device does not
change current mode.
(*5)
According to the initial power mode selection.
(*6)
See 12.15 Software Setting Preservation Feature Set.
Table 29 Reset Response Table

12.1.1

After power on, COMRESET, or software reset, the register values are initialized as shown in the following table.

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Default Value
Diagnostic Code
01h
01h
00h
00h
00h
50h
50h

Error
Sector Count
LBA Low
LBA Mid
LBA High
Device
Status
Alternate Status
Table 30 Default Register Values

The meaning of the Error Register diagnostic codes resulting from power on, COMRESET or the
Execute Device Diagnostic command are shown in the following table.

Code
01h
02h
03h
04h
05h
Table 31 Diagnostic Codes

Description
No error Detected
Formatter device error
Sector buffer error
Ecc circuitry error
Controller microprocessor error

12.2 Diagnostic and Reset considerations
The Set Max password, the Set Max security mode and the Set Max unlock counter don’t retain over
a Power On Reset but persist over a COMRESET or Soft Reset.
For each Reset and Execute Device Diagnostic, the Diagnostic is done as follows:
Execute Device Diagnostic
In all the above cases: Power on, COMRESET, Soft reset, and the EXECUTE DEVICE
DIAGNOSTIC command the Error register is shown in the following table.
Device 0 Passed
Error Register
Yes
01h
No
0xh
Where x indicates the appropriate Diagnostic Code for the Power on, COMRESET, Soft reset, or Device
Diagnostic error.
Table 32 Reset error register values

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12.3 Power-off considerations
12.3.1

Load/Unload

Load/Unload is a functional mechanism of the HDD. It is controlled by the drive microcode.
Specifically, unloading of the heads is invoked by the commands:
Command
Standby
Standby immediate
Sleep

Response
UL -> Comp.
UL -> Comp.
UL -> Comp.
“UL”

means “unload”.

“Comp” means “complete”.
Table 33 Device’s behavior by ATA commands
Load/unload is also invoked as one of the idle modes of the drive.
The specified start/stop life of the product assumes that load/unload is operated normally, NOT in
emergency mode.

12.3.2

Emergency unload

When HDD power is interrupted while the heads are still loaded, the microcode cannot operate and
the normal 5V power is unavailable to unload the heads. In this case, normal unload is not possible,
so the heads are unloaded by routing the back-EMF of the spinning motor to the voice coil. The
actuator velocity is greater than the normal case, and the unload process is inherently less
controllable without a normal seek current profile.
Emergency unload is intended to be invoked in rare situations. Because this operation is inherently
uncontrolled, it is more mechanically stressful than a normal unload.
A single emergency unload operation is more stressful than 100 normal unloads. Use of emergency
unload reduces the start/stop life of the HDD at a rate at least 100X faster than that of normal
unload, and may damage the HDD.

12.3.3

Required power-off sequence

Problems can occur on most HDDs when power is removed at an arbitrary time. Examples:
Data loss from the write buffer.
If the drive is writing a sector, a partially-written sector with an incorrect ECC block results. The sector
contents are destroyed and reading that sector results in a hard error.
Heads possibly land in the data zone instead of landing zone, depending on the design of the HDD.
You may then turn off the HDD in the following order:
1. Issue Standby Immediate or sleep command.
2. Wait until COMMAND COMPLETE STATUS is returned. (It may take up to 350 ms in typical case)
3. Terminate power to HDD.
This power-down sequence should be followed for entry into any system power-down state, or system
suspend state, or system hibernation state. In a robustly designed system, emergency unload is
limited to rare scenarios such as battery removal during operation.

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12.4 Sector Addressing Mode
All addressing of data sectors recorded on the device’s media is by a logical sector address. The
logical CHS address for HTS7220XXK9SA00 / HTS7220XXK9A300 is different from the actual
physical CHS location of the data sector on the disk media.
HTS7220XXK9SA00 / HTS7220XXK9A300 support both Logical CHS Addressing Mode and LBA
Addressing Mode as the sector addressing mode.
The host system may select either the currently selected CHS translation addressing or LBA
addressing on a command-by-command basis by using the L bit in the DEVICE register. So a host
system must set the L bit to 1 if the host uses LBA Addressing mode.

12.4.1

Logical CHS Addressing Mode

The logical CHS addressing is made up of three fields: the cylinder number, the head number and
the sector number. Sectors are numbered from 1 to the maximum value allowed by the current CHS
translation mode but can not exceed 255(0FFh). Heads are numbered from 0 to the maximum value
allowed by the current CHS translation mode but can not exceed 15(0Fh). Cylinders are numbered
from 0 to the maximum value allowed by the current CHS translation mode but cannot exceed
65535(0FFFFh).
When the host selects a CHS translation mode using the INITIALIZE DEVICE PARAMETERS
command, the host requests the number of sectors per logical track and the number of heads per
logical cylinder. The device then computes the number of logical cylinders available in requested
mode.
The default CHS translation mode is described in the Identify Device Information. The current CHS
translation mode also is described in the Identify Device Information.

12.4.2

LBA Addressing Mode

Logical sectors on the device shall be linearly mapped with the first LBA addressed sector (sector 0)
being the same sector as the first logical CHS addressed sector ( cylinder 0, head 0, sector 1).
Irrespective of the logical CHS translation mode currently in effect, the LBA address of a given
logical sector does not change. The following is always true:
LBA = ( (cylinder * heads_per_cylinder + heads)
* sectors_per_track ) + sector - 1
where heads_per_cylinder and sectors_per_track are the current translation mode values.
On LBA addressing mode, the LBA value is set to the following register.
Device
<--- LBA bits 27-24
LBA High <--- LBA bits 23-16
LBA Mid <--- LBA bits 15- 8
LBA Low <--- LBA bits 7- 0

12.5 Power Management Feature
The power management feature set permits a host to modify the behavior in a manner which
reduces the power required to operate. The power management feature set provides a set of
commands and a timer that enables a device to implement low power consumption modes.
HTS7220XXK9SA00 / HTS7220XXK9A300 implement the following set of functions.
1.
2.
3.
4.
5.
6.

A Standby timer
Idle command
Idle Immediate command
Sleep command
Standby command
Standby Immediate command
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12.5.1

Power Mode

Sleep Mode
Standby Mode

Idle Mode
Active Mode

12.5.2

The lowest power consumption when the device is powered on occurs in Sleep Mode.
When in sleep mode, the device requires a reset to be activated.
The device interface is capable of accepting commands, but as the media may not
immediately accessible, there is a delay while waiting for the spindle to reach
operating speed.
Refer to the section of Adaptive Battery Life Extender Feature.
The device is in execution of a command or accessing the disk media with read
look-ahead function or write cache function.

Power Management Commands

The Check Power Mode command allows a host to determine if a device is currently in, going to or
leaving standby mode.
The Idle and Idle Immediate commands move a device to idle mode immediately from the active or
standby modes. The idle command also sets the standby timer count and starts the standby timer.
The sleep command moves a device to sleep mode. The device’s interface becomes inactive at the
completion of the sleep command. A reset is required to move a device out of sleep mode. When a
device exits sleep mode it will enter standby mode.
The Standby and Standby Immediate commands move a device to standby mode immediately from
the active or idle modes. The standby command also sets the standby timer count.

12.5.3
1.
2.
3.
4.
5.
6.

Standby/Sleep command completion timing

Confirm the completion of writing cached data in the buffer to media
Unload heads on the ramp
Set DRDY bit and DSC bit in Status Register
Activate the spindle break to stop the spindle motor
Wait until spindle motor is stopped
Perform post process

12.5.4

Status

In the active, idle and standby modes, the device shall have RDY bit of the status register set. If BSY
bit is not set, device shall be ready to accept any command.
In sleep mode, the device’s interface is not active. A host shall not attempt to read the device’s status
or issue commands to the device.

12.5.5

Interface Capability for Power Modes

Each power mode affects the physical interface as defined in the following table:
Mode
Active
Idle
Standby
Sleep
Table 34 Power conditions

BSY
x
0
0
x

RDY
x
1
1
x

Interface active
Yes
Yes
Yes
No

Media
Active
Active
Inactive
Inactive

Ready(RDY) is not a power condition. A device may post ready at the interface even though the
media may not be accessible.

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12.5.6

Initial Power Mode at Power On

After power on the device goes to IDLE mode or STANDBY mode depending on the setting of the
Power Up in Standby Feature set

12.6 Advanced Power Management (Adaptive
Battery Life Extender 3) Feature
This feature provides power saving without performance degradation. The Adaptive Battery Life
Extender 3 (ABLE-3) technology intelligently manages transition among power modes within the
device by monitoring access patterns of the host.
This technology has three idle modes; Performance Idle mode, Active Idle mode, and Low Power Idle
mode.
This feature allows the host to select an advanced power management level. The advanced power
management level is a scale from the lowest power consumption setting of 01h to the maximum
performance level of FEh. Device performance may increase with increasing advanced power
management levels. Device power consumption may increase with increasing advanced power
management levels. The advanced power management levels contain discrete bands, described in the
section of Set Feature command in detail.
This feature set uses the following functions:
A SET FEATURES subcommand to enable Advanced Power Management
A SET FEATURES subcommand to disable Advanced Power Management
The Advanced Power Management feature is independent of the Standby timer setting. If both
Advanced Power Management level and the Standby timer are set, the device will go to the Standby
state when the timer times out or the device’s Advanced Power Management algorithm indicates
that it is time to enter the Standby state.
The IDENTIFY DEVICE response word 83, bit 3 indicates that Advanced Power Management
feature is supported if set. Word 86, bit 3 indicates that Advanced Power Management is enabled if
set.
Word 91, bits 7-0 contain the current Advanced Power Management level if Advanced Power
Management is enabled.

12.6.1

Performance Idle mode

This mode is usually entered immediately after Active mode command processing is complete,
instead of conventional idle mode. In Performance Idle mode, all electronic components remain
powered and full frequency servo remains operational. This provides instantaneous response to the
next command. The duration of this mode is intelligently managed as described below.

12.6.2

Active Idle mode

In this mode, power consumption is 45-55% less than that of Performance Idle mode. Additional
electronics are powered off, and the head is parked near the mid-diameter of the disk without
servoing. Recovery time to Active mode is about 20ms.

12.6.3

Low Power Idle mode

Power consumption is 60%-65% less than that of Performance Idle mode. The heads are unloaded on
the ramp, however the spindle is still rotated at the full speed. Recovery time to Active mode is about
300ms.
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12.6.4

Transition Time

The transition time is dynamically managed by users recent access pattern, instead of fixed times.
The ABLE-3 algorithm monitors the interval between commands instead of the command frequency
of ABLE-2. The algorithm supposes that next command will come with the same command interval
distribution as the previous access pattern. The algorithm calculates the expected average saving
energy and response delay for next command in several transition time case based on this
assumption. And it selects the most effective transition time with the condition that the calculated
response delay is shorter than the value calculated from the specified level by Set Feature Enable
Advanced Power Management command.
The optimal time to enter Active Idle mode is variable depending on the users recent behavior. It is
not possible to achieve the same level of Power savings with a fixed entry time into Active Idle
because every users data and access pattern is different. The optimum entry time changes over time.
The same algorithm works for entering into Low Power Idle mode and Standby mode, which
consumes less power but need more recovery time switching from this mode to Active mode.

12.7 Interface Power Management Mode
(Slumber and Partial)
Interface Power Management Mode is supported by both Device-initiated interface power
management and Host-initiated interface power management. Please refer to the Serial ATA
Specification about Power Management Mode.

12.8 S.M.A.R.T. Function
The intent of Self-monitoring, analysis and reporting technology (S.M.A.R.T) is to protect user data
and prevent unscheduled system downtime that may be caused by predictable degradation and/or
fault of the device. By monitoring and storing critical performance and calibration parameters,
S.M.A.R.T devices employ sophisticated data analysis algorithms to predict the likelihood of
near-term degradation or fault condition. By alerting the host system of a negative reliability status
condition, the host system can warn the user of the impending risk of a data loss and advise the user
of appropriate action.
Since S.M.A.R.T. utilizes the internal device microprocessor and other device resources, there may
be some small overhead associated with its operation. However, special care has been taken in the
design of the S.M.A.R.T. algorithms to minimize the impact to host system performance. Actual
impact of S.M.A.R.T. overhead is dependent on the specific device design and the usage patterns of
the host system. To further ensure minimal impact to the user, S.M.A.R.T. capable devices are
shipped from the device manufacturer’s factory with the S.M.A.R.T. feature disabled. S.M.A.R.T.
capable devices can be enabled by the system OEMs at time of system integration or in the field by
aftermarket products.

12.8.1

Attributes

Attributes are the specific performance or calibration parameters that are used in analyzing the
status of the device. Attributes are selected by the device manufacturer based on that attribute’s
ability to contribute to the prediction of degrading or faulty conditions for that particular device. The
specific set of attributes being used and the identity of these attributes is vendor specific and
proprietary.

12.8.2

Attribute values

Attribute values are used to represent the relative reliability of individual performance or
calibration attributes. Higher attribute values indicate that the analysis algorithms being used by
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the device are predicting a lower probability of a degrading or fault condition existing. Accordingly,
lower attribute values indicate that the analysis algorithms being used by the device are predicting a
higher probability of a degrading or fault condition existing. There is no implied linear reliability
relationship corresponding to the numerical relationship between different attribute values for any
particular attribute.

12.8.3

Attribute thresholds

Each attribute value has a corresponding attribute threshold limit which is used for direct
comparison to the attribute value to indicate the existence of a degrading or faulty condition. The
numerical value of the attribute thresholds are determined by the device manufacturer through
design and reliability testing and analysis. Each attribute threshold represents the lowest limit to
which its corresponding attribute value can be equal while still retaining a positive reliability status.
Attribute thresholds are set at the device manufacturer’s factory and cannot be changed in the field.
The valid range for attribute thresholds is from 1 through 253 decimal.

12.8.4

Threshold exceeded condition

If one or more attribute values are less than or equal to their corresponding attribute thresholds,
then the device reliability status is negative, indicating an impending degrading or faulty condition.

12.8.5

S.M.A.R.T. commands

The S.M.A.R.T. commands provide access to attribute values, attribute thresholds and other logging
and reporting information.

12.8.6

S.M.A.R.T operation with power management modes

The device saves attribute values automatically on every head unload timing except the emergency
unload, even if the attribute auto save feature is not enabled. The head unload is done not only by
Standby, Standby Immediate, or Sleep command, but also by the automatic power saving functions
like ABLE-3 or Standby timer. So basically it is not necessary for a host system to enable the
attribute auto save feature, when it utilizes the power management. If the attribute auto save
feature is enabled, attribute values will be saved after 30minutes passed since the last saving,
besides above condition.

12.9 Security Mode Feature Set
Security Mode Feature Set is a powerful security feature. With a device lock password, a user can
prevent unauthorized access to hard disk device even if the device is removed from the computer.
New commands are supported for this feature as below.
Security Set Password
Security Unlock
Security Erase Prepare
Security Erase Unit
Security Freeze Lock
Security Disable Password

12.9.1

(‘F1’h)
(‘F2’h)
(‘F3’h)
(‘F4’h)
(‘F5’h)
(‘F6’h)

Security mode

Following security modes are provided.
Device Locked mode

Device Unlocked mode

The device disables media access commands after power on. Media access
commands are enabled by either a security unlock command or a security
erase unit command.
The device enables all commands. If a password is not set this mode is
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Device Frozen mode

12.9.2

7K200 SATA OEM Specification
entered after power on, otherwise it is entered by a security unlock or a
security erase unit command.
The device enables all commands except those which can update the device
lock function, set/change password. The device enters this mode via a
Security Freeze Lock command. It cannot quit this mode until power off.

Security Level

Following security levels are provided.
High level security
Maximum level security

12.9.3

When the device lock function is enabled and the User Password is
forgotten the device can be unlocked via a Master Password.
When the device lock function is enabled and the User Password is
forgotten then only the Master Password with a Security Erase Unit
command can unlock the device. Then user data is erased.

Password

This function can have 2 types of passwords as described below.
When the Master Password is set, the device does NOT enable the Device
Lock Function, and the device can NOT be locked with the Master
Password, but the Master Password can be used for unlocking the device
locked.
The User Password should be given or changed by a system user. When the
User Password
User Password is set, the device enables the Device Lock Function, and
then the device is locked on next power on reset. If Software Setting
Preservation is disabled, the device is locked on COMRESET as well.
The system manufacturer/dealer who intends to enable the device lock function for the end users,
must set the master password even if only single level password protection is required. Otherwise, if
the User Password is forgotten then no one can unlock the device which is locked with the User
Password.
Master Password

12.9.4

Master Password Revision Code

This Master Password Revision Code is set by Security Set Password command with the master
password. And this revision code field is returned in the Identify Device command word 92. The valid
revision codes are 0001h to FFFEh. The default value of Master Password Revision Code is FFFEh.
Value 0000h and FFFFh is reserved.

12.9.5

Operation example

12.9.5.1 Master Password setting
The system manufacturer/dealer can set a initial Master Password using the Security Set Password
command, without enabling the Device Lock Function.

12.9.5.2 User Password setting
When a User Password is set, the device will automatically enter lock mode the next time the device
is powered on.

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Figure 5 Initial Setting

12.9.1.2 Operation from POR after User Password is set
When Device Lock Function is enabled, the device rejects media access command until a Security
Unlock command is successfully completed.

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(*1) refer to Table 35 Command table for device lock operation on Page 62 and Table 36 Command table for
device lock operation - continued on Page 63.
Figure 6 Usual Operation

12.9.1.3 User Password Lost
If the User Password is forgotten and High level security is set, the system user can’t access any
data. However the device can be unlocked using the Master Password.
If a system user forgets the User Password and Maximum security level is set, data access is
impossible. However the device can be unlocked using the Security Erase Unit command to unlock
the device and erase all user data with the Master Password.

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Figure 7 Password Lost

12.9.1.4 Attempt limit for SECURITY UNLOCK command
The SECURITY UNLOCK command has an attempt limit. The purpose of this attempt limit is to
prevent that someone attempts to unlock the drive by using various passwords many times.
The device counts the password mismatch. If the password does not match, the device counts it up
without distinguishing the Master password and the User password. If the count reaches 5, EXPIRE
bit(bit 4) of Word 128 in Identify Device information is set, and then SECURITY ERASE UNIT
command and SECURITY UNLOCK command are aborted until a power off. The count and EXPIRE
bit are cleared after a power on reset.

12.9.6

Command Table

This table shows the device’s response to commands when the Security Mode Feature Set (Device
lock function) is enabled.

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Command

Device
Locked
Mode
o
x
o
x
x
o
x
x
x
x
o
o
o
o
o
o
x
x
x
o
x
x
o
o
x
x
x
x
o
x
o
o
x
x
o
o
o
o

Check Power Mode
Device Configuration RESTORE
Device Configuration FREEZE LOCK
Device Configuration IDENTIFY
Device Configuration SET
Execute Device Diagnostic
Flush Cache
Flush Cache Ext
Format Track
Format Unit
Identify Device
Idle
Idle Immediate
Idle Immediate with Unload option
Initialize Device Parameters
Read Buffer
Read DMA
Read DMA Ext
Read FPDMA Queued
Read Log Ext
Read Multiple
Read Multiple Ext
Read Native Max Address
Read Native Max Address Ext
Read Sector(s)
Read Sector(s) Ext
Read Verify Sector(s)
Read Verify Sector(s) Ext
Recalibrate
Security Disable Password
Security Erase Prepare
Security Erase Unit
Security Freeze Lock
Security Set Password
Security Unlock
Seek
Sense Condition
Set Features
Table 35 Command table for device lock operation

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Device
Unlock
Mode
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o

Device
Frozen
Mode
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
x
o
x
o
x
x
o
o
o

7K200 SATA OEM Specification
Command

Set Max Address
Set Max Address Ext
Set Max Freeze Lock
Set Max Lock
Set Max Set Password
Set Max Unlock
Set Multiple Mode
Sleep
S.M.A.R.T. Disable Operations
S.M.A.R.T. Enable/Disable Automatic Offline
S.M.A.R.T. Enable/Disable Attribute Autosave
S.M.A.R.T. Enable Operations
S.M.A.R.T. Execute Off-line Immediate
S.M.A.R.T. Read Attribute Values
S.M.A.R.T. Read Attribute Thresholds
S.M.A.R.T. Read Log Sector
S.M.A.R.T. Write Log Sector
S.M.A.R.T. Return Status
S.M.A.R.T. Save Attribute Values
Standby
Standby Immediate
Write Buffer
Write DMA
Write DMA Ext
Write DMA FUA Ext
Write FPDMA Queued
Write Log Ext
Write Multiple
Write Multiple Ext
Write Multiple FUA Ext
Write Sector(s)
Write Sector(s) Ext
Write Uncorrectable Ext
Table 36 Command table for device lock operation - continued

12.10

Device
Locked
Mode
x
x
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
x
x
x
x
x
x
x
x
x
x
x

Device
Unlock
Mode
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o

Device
Frozen
Mode
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o

Protected Area Function

Protected Area Function is to provide the ‘protected area’ which can not be accessed via conventional
method. This ‘protected area’ is used to contain critical system data such as BIOS or system
management information. The contents of entire system main memory may also be dumped into
‘protected area’ to resume after system power off.
The LBA/CYL changed by following command affects the Identify Device Information.
Two commands are defined for this function.
Read Native Max Address
Set Max Address

(‘F8’h)
(‘F9’h)

Four security extension commands are implemented as sub-functions of the Set Max Address.
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Set Max Set Password
Set Max Lock
Set Max Freeze Lock
Set Max Unlock

12.10.1 Example for operation (In LBA mode)
Assumptions :
For better understanding, the following example uses actual values for LBA, size, etc. Since it is just
an example, these values could be different.
Device characteristics
Capacity (native)
Max LBA (native)
Required size for protected area
Required blocks for protected area
Customer usable device size
Customer usable sector count
LBA range for protected area
Shipping HDDs from HDD manufacturer

:
536,870,912 byte (536MB)
:
1,048,575 (0FFFFFh)
:
8,388,608 byte
:
16,384 (004000h)
:
528,482,304 byte (528MB)
:
1,032,192 (0FC000h)
: 0FC000h to 0FFFFFh

When the HDDs are shipped from HDD manufacturer, the device has been tested to have a
capacity of 536MB,flagging the media defects not to be visible by system.
Preparing HDDs at system manufacturer
Special utility software is required to define the size of protected area and store the data into it.
The sequence is :
Issue Read Native Max Address command to get the real device max of LBA/CYL. Returned value shows
that native device Max LBA is 0FFFFFh regardless to the current setting.
Make entire device be accessible including the protected area by setting device Max LBA as 0FFFFFh via
Set Max Address command. The option could be either nonvolatile or volatile.
Test the sectors for protected area (LBA >= 0FC000h) if required.
Write information data such as BIOS code within the protected area.
Change maximum LBA using Set Max Address command to 0FBFFFh with nonvolatile option.
From this point, the protected area cannot be accessed until next Set Max Address command is issued.
Any BIOSes, device drivers, or application software access the HDD as if that is the 528MB device
because the device acts exactly same as real 528MB device does.

Conventional usage without system software support
Since the HDD works as 528MB device, there is no special care to use this device for normal use.

Advanced usage using protected area
The data in the protected area is accessed by following.
Issue Read Native Max Address command to get the real device max LBA/CYL. Returned value
shows that native device Max LBA is 0FFFFFh regardless of the current setting.
Make entire device be accessible including the protected area by setting device Max LBA as
0FFFFFh via Set Max Address command with volatile option. By using this option, unexpected
power removal or reset will not make the protected area remained accessible.
Read information data from protected area.
Issue POR to inhibit any access to the protected area.

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12.10.2 Set Max security extension commands
The Set Max Set Password command allows the host to define the password to be used during the
current power on cycle. This password is not related to the password used for the Security Mode
Feature set. When the password is set the device is in the Set Max Unlocked mode.
This command requests a transfer of a single sector of data from the host. The table shown below
defines the content of this sector of information. The password is retained by the device until the
next power cycle. When the device accepts this command the device is in Set Max Unlocked mode.
Word
0
1-16
17-255
Table 37 Set Max Set Password data content

Content
Reserved
Password (32 bytes)
Reserved

The Set Max Lock command allows the host to disable the Set Max commands (except Set Max
Unlock and Set Max Freeze Lock) until the next power cycle or the issuance and acceptance of the
Set Max Unlock command. When this command is accepted the device is in the Set Max Locked
mode.
The Set Max Unlock command changes the device from the Set Max Locked mode to the Set Max
Unlocked mode.
This command requests a transfer of a single sector of data from the host. The Table shown above
defines the content of this sector of information. The password supplied in the sector of data
transferred is compared with the stored Set Max password. If the password compare fails, then the
device returns command aborted and decrements the unlock counter. On the acceptance of the Set
Max Lock command, this counter is set to a value of five and is decremented for each password
mismatch when Set Max Unlock is issued and the device is locked. When this counter reaches zero,
then the Set Max Unlock command returns command aborted until a power cycle.
The Set Max Freeze Lock command allows the host to disable the SET Max commands (including Set
Max Unlock) until the next power cycle. When this command is accepted the device is in the Set Max
Frozen mode.
The password, the Set Max security mode and the unlock counter don’t persist over a power cycle but
does persist over a COMRESET or software reset.
Note that If this command is immediately preceded by a Read Native Max Address command
regardless of Feature register value, it shall be interpreted as a Set Max Address command.

Figure 8 Set Max security mode transition
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12.11

Seek Overlap

HTS7220XXK9SA00 / HTS7220XXK9A300 provide accurate seek time measurement method. The
seek command is usually used to measure the device seek time by accumulating execution time for a
number of seek commands. With typical implementation of the seek command, this measurement
must including the device and host command overhead. To eliminate this overhead,
HTS7220XXK9SA00 / HTS7220XXK9A300 overlap the seek command as described below.
The first seek command completes before the actual seek operation is over. Then device can receive
the next seek command from the host but actual seek operation for the next seek command starts
right after the actual seek operation for the first seek command is completed. In other words, the
execution of two seek commands overlaps excluding the actual seek operation.
With this overlap, total elapsed time for a number of seek commands is the total accumulated time
for the actual seek operation plus one pre and post overhead. When the number of seeks is large, just
this one overhead can be ignored.

Figure 9 Seek overlap

12.12

Write Cache Function

Write cache is a performance enhancement whereby the device reports completion of the write
command (Write Sector(s) and Write Multiple) to the host as soon as the device has received all of
the data into its buffer. The device assumes responsibility to write the data subsequently onto the
disk.
While writing data after completed acknowledgment of a write command, soft reset or COMRESET does
not affect its operation. But power off terminates writing operation immediately and unwritten data are to
be lost.
Flush cache, Soft reset, Standby, Standby Immediate and Sleep are executed after the completion of
writing to disk media on enabling write cache function. So the host system can confirm the completion of
write cache operation by issuing flush cache command, Soft reset, Standby command, Standby Immediate
command or Sleep command, and then, by confirming its completion.

12.13

Reassign Function

The reassign Function is used with read commands and write commands. The sectors of data for
reassignment are prepared as the spare data sector. The one entry can register 256 consecutive
sectors maximally.
This reassignment information is registered internally, and the information is available right after
completing the reassign function. Also the information is used on the next power on reset.
If the number of the spare sector reaches 0 sector, the reassign function will be disabled
automatically.
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The spare tracks for reassignment are located at regular intervals from Cylinder 0. As a result of
reassignment, the physical location of logically sequenced sectors will be dispersed.

12.13.1 Auto Reassign Function
The sectors that show some errors may be reallocated automatically when specific conditions are met.
The spare tracks for reallocation are located at regular intervals from Cylinder 0. The conditions for
auto-reallocation are described below.
Non recovered write errors
When a write operation can not be completed after the Error Recovery Procedure(ERP) is fully
carried out, the sector(s) are reallocated to the spare location. An error is reported to the host system
only when the write cache is disabled and the auto reallocation fails.
If the number of available spare sectors reaches 16 sectors, the write cache function will be disabled
automatically.
Non recovered read errors
When a read operation fails after defined ERP is fully carried out, a hard error is reported to the
host system. This location is registered internally as a candidate for the reallocation. When a
registered location is specified as a target of a write operation, a sequence of media verification is
performed automatically. When the result of this verification meets the criteria, this sector is
reallocated.
Recovered read errors
When a read operation for a sector failed once then recovered at the specific ERP step, this sector of
data is reallocated automatically. A media verification sequence may be run prior to the relocation
according to the pre-defined conditions.

12.14

48-bit Address Feature Set

The 48-bit Address feature set allows devices with capacities up to 281,474,976,710,655 sectors. This
allows device capacity up to 144,115,188,075,855,360 bytes. In addition, the number of sectors that
may be transferred by a single command are increased by increasing the allowable sector count to 16
bits.
Commands unique to the 48-bit Address feature set are:
Flush Cache Ext
Read DMA Ext
Read Multiple Ext
Read Native Max Address Ext
Read Sector(s) Ext
Read Verify Sector(s) Ext
Set Max Address Ext
Write DMA Ext
Write Multiple Ext
Write Sector(s) Ext
The 48-bit Address feature set operates in LBA addressing only. Devices also implement commands
using 28-bit addressing, and 28-bit and 48-bit commands may be intermixed.
Support of the 48-bit Address feature set is indicated in the Identify Device response bit 10 word 83.
In addition, the maximum user LBA address accessible by 48-bit addressable commands is contained
in Identify Device response words 100 through 103.
When the 48-bit Address feature set is implemented, the native maximum address is the value
returned by a Read Native Max Address Ext command. If the native maximum address is equal to or
less than 268,435,455, a Read Native Max Address shall return the native maximum address. If the
native maximum address is greater than 268,435,455, a Read Native Max Address shall return a
value of 268,435,455.

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12.15

Software Setting Preservation Feature Set

When a device is enumerated, software will configure the device using Set Features and other
commands. These software settings are often preserved across software reset but not necessarily
across hardware reset. In Parallel ATA, only commanded hardware resets can occur, thus legacy
software only reprograms settings that are cleared for the particular type of reset it has issued. In
Serial ATA, COMRESET is equivalent to hard reset and a non-commanded COMRESET may occur
if there is an asynchronous loss of signal. Since COMRESET is equivalent to hardware reset, in the
case of an asynchronous loss of signal some software settings may be lost without legacy software
knowledge. In order to avoid losing important software settings without legacy driver knowledge,
the software settings preservation ensures that the value of important software settings is
maintained across a COMRESET. Software settings preservation may be enabled or disabled using
Set Features with a subcommand code of 06h. Software settings preservation is enabled by default.

12.15.1 Preserved software settings
If Software setting preservation is enabled, the following settings are preserved across COMRESET.
Otherwise settings are cleared across COMRESET.

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Setting

Contents

Initialize device parameters

Track length
Number of head
Number of cylinder
Capacity

Power Management Feature Set Standby
Timer

Time to fall into standby mode

Security mode state

Security freeze lock
Security unlock

Set max address

Capacity

Set feature

Write Cache Enable/Disable
Set Transfer Mode
Advanced Power Management
Enable/Disable
Read Look-Ahead
Reverting to Defaults

Set multiple mode

Block size

Table 38 Preserved Software Setting

12.16

Native Command Queuing

Native Command Queuing feature (Read / Write FPDMA Queued commands) is supported. Please
refer to the Serial ATA II Specification about Native Command Queuing.
The host shall not issue a legacy ATA command while a native queued command is outstanding.
Upon receiving a legacy ATA command while a native queued command is outstanding, the device
aborts the command and halts command processing of outstanding native queued commands.

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7K200 SATA OEM Specification

12.17

SMART Command Transport (SCT)

SMART Command Transport (SCT) feature set is supported. The SMART Read Log and SMART
Write Log commands or Read Log Ext and Write Log Ext commands are used to issue a command in
this feature sets. Log page E0h is used to issue commands and return status. Log page E1h is
used to transport data. Please refer to the section 8 SCT Command Transport in ATA8-ACS
specification for more detail.
The following Action codes are supported.

Action
code

Description

0002h

Write Same command

0003h

Error Recovery Control command

0004h

Feature Control command

0005h

Feature code
0001h

Write Cache

Feature code
0003h

Time Interval for temperature logging

SCT Data Table command

Table 39 SCT Action Code Supported

13 Command Protocol
The commands are grouped into different classes according to the protocols followed for command
execution. The command classes with their associated protocols are defined below.
Please refer to Serial ATA Revision 2.6 (Section 11. device command layer protocol) about each
protocol.
For all commands, the host must first check if BSY=1, and should proceed no further unless and
until BSY=0. For all commands, the host must also wait for RDY=1 before proceeding.
A device must maintain either BSY=1 or DRQ=1 at all times until the command is completed. The
INTRQ signal is used by the device to signal most, but not all, times when the BSY bit is changed
from 1 to 0 during command execution.
A command shall only be interrupted with a COMRESET or software reset. The result of writing to
the Command register while BSY=1 or DRQ=1 is unpredictable and may result in data corruption. A
command should only be interrupted by a reset at times when the host thinks there may be a
problem, such as a device that is no longer responding.
Interrupts are cleared when the host reads the Status Register, issues a reset, or writes to the
Command Register.
“Table 138 Timeout Values” on Page 171 shows the device timeout values.

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7K200 SATA OEM Specification

13.1 Data In Commands
These commands are:
Device Configuration Identify
Identify Device
Read Buffer
Read Log Ext
Read Multiple
Read Multiple Ext
Read Sector(s)
Read Sector(s) Ext
S.M.A.R.T. Read Attribute Values
S.M.A.R.T. Read Attribute Thresholds
S.M.A.R.T. Read log sector
Execution includes the transfer of one or more 512 byte (>512 bytes on Read Long) sectors of data
from the device to the host.
Note that the status data for a sector of data is available in the Status Register before the sector is
transferred to the host.
If the device detects an invalid parameter, then it will abort the command by setting BSY=0, ERR=1,
ABT=1.
If an error occurs, the device will set BSY=0, ERR=1, and DRQ=1. The device will then store the
error status in the Error Register. The registers will contain the location of the sector in error. The
erroneous location will be reported with CHS mode or LBA mode, the mode is decided by mode select
bit (bit 6) of Device register on issuing the command.

13.2 Data Out Commands
These commands are:
Device Configuration Set
Format Track
Security Disable Password
Security Erase Unit
Security Set Password
Security Unlock
Set Max Set Password
Set Max Unlock
S.M.A.R.T Write Log Sector
Write Buffer
Write Log Ext
Write Multiple
Write Multiple Ext
Write Sector(s)
Write Sector(s) Ext
Execution includes the transfer of one or more 512 byte (>512 bytes on Write Long) sectors of data
from the host to the device.
If the device detects an invalid parameter, then it will abort the command by setting BSY=0, ERR=1,
ABT=1.
If an uncorrectable error occurs, the device will set BSY=0 and ERR=1, store the error status in the
Error Register. The registers will contain the location of the sector in error. The errored location will
be reported with CHS mode or LBA mode. The mode is decided by mode select bit (bit 6) of Device
register on issuing the command.

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7K200 SATA OEM Specification

13.3 Non-Data Commands
These commands are:
Check Power Mode
Device Configuration Freeze Lock
Device Configuration Restore
Execute Device Diagnostic
Flush Cache
Flush Cache Ext
Format Unit
Idle
Idle Immediate
Idle Immediate with Unload option
Initialize Device Parameters
Read Native Max Address
Read Native Max Address Ext
Read Verify Sector(s)
Read Verify Sector(s) Ext
Recalibrate
Security Erase Prepare
Security Freeze Lock
Seek
Sense Condition
Set Features
Set Max Address
Set Max Address Ext
Set Max Lock
Set Max Freeze Lock
Set Multiple Mode
Sleep
S.M.A.R.T. Disable Operations
S.M.A.R.T. Enable/Disable Attribute Autosave
S.M.A.R.T. Enable/Disable Automatic Off-line
S.M.A.R.T. Enable Operations
S.M.A.R.T. Execute Off-line Immediate
S.M.A.R.T. Return Status
S.M.A.R.T. Save Attribute Values
Standby
Standby Immediate
Write Uncorrectable Ext
Execution of these commands involves no data transfer.

13.4 DMA Data Transfer Commands
These commands are:
Read DMA
Read DMA Ext
Write DMA
Write DMA Ext
Initiation of the DMA transfer commands is identical to the Read Sector or Write Sector commands
except that the host initializes the slave-DMA channel prior to issuing the command.
The DMA protocol allows high performance multi-tasking operating systems to eliminate processor
overhead associated with PIO transfers.
Refer Functional Specification part for further details.

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7K200 SATA OEM Specification

13.5 First-parity DMA Commands
These commands are:
Read FPDMA Queued
Write FPDMA Queued
Execution of this class of commands includes command queuing and the transfer of one or more
blocks of data between the device and the host. The protocol is described in the section 11.14
“FPDMA Queued command protocol” of “Serial ATA revision 2.6”.

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14 Command Descriptions
Protocol

Command

Code
(Hex)
E5
98
B1
B1
B1
B1
90
E7
EA
50
F7
EC
E3
97
E1
95
E1
91
E4
C8
C9
25
60
2F
C4
29
F8
27
20
21
24
40
41
42
1x
F6
F3
F4
F5
F1
F2
7x
F0
EF

3
Check Power Mode
3
Check Power Mode*
3
Device Configuration Restore
3
Device Configuration Freeze Lock
1
Device Configuration Identify
2
Device Configuration Set
3
Execute Device Diagnostic
3
Flush Cache
3
Flush Cache Ext
2
Format Track
3+
Format Unit
1
Identify Device
3
Idle
3
Idle*
3
Idle Immediate
3
Idle Immediate*
3
Idle Immediate with Unload optoin
3
Initialize Device Parameters
1
Read Buffer
4
Read DMA
4
Read DMA
4
Read DMA Ext
5
Read FPDMA Queued
1
Read Log Ext
1
Read Multiple
1
Read Multiple Ext
3
Read Native Max Address
3
Read Native Max Address Ext
1
Read Sector(s)
1
Read Sector(s)
1
Read Sector(s) Ext
3
Read Verify Sector(s)
3
Read Verify Sector(s)
3
Read Verify Sector(s) Ext
3
Recalibrate
2
Security Disable Password
3
Security Erase Prepare
2
Security Erase Unit
3
Security Freeze Lock
2
Security Set Password
2
Security Unlock
3
Seek
3
Sense Condition
3
Set Features
Table 40 Command set
Protocol

Command
74/173

Code

7
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
0
0
0
1
0
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
1
1

6
1
0
0
0
0
0
0
1
1
1
1
1
1
0
1
0
1
0
1
1
1
0
1
0
1
0
1
0
0
0
0
1
1
1
0
1
1
1
1
1
1
1
1
1

5
1
0
1
1
1
1
0
1
1
0
1
1
1
0
1
0
1
0
1
0
0
1
1
1
0
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
1

4
0
1
0
0
0
0
1
0
0
1
1
0
0
1
0
1
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0

3
0
1
0
0
0
0
0
0
1
0
0
1
0
0
0
0
0
0
0
1
1
0
0
1
0
1
1
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1

2
1
0
0
0
0
0
0
1
0
0
1
1
0
1
0
1
0
0
1
0
0
1
0
1
1
0
0
1
0
0
1
0
0
0
0
0
1
1
0
0
0
1

1
0
0
0
0
0
0
0
1
1
0
1
0
1
1
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
1
1
1
0
0
0
1
0
1

0
1
0
1
1
1
1
0
1
0
0
1
0
1
1
1
1
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
1
0
0
1
0
1
1
0
0
1

7K200 SATA OEM Specification
3
3
3
3
2
2
3
3
3
3
3
3
3
3
1
1
1
3
3
2
3
3
3
3
2
4
4
4
4
5
2
2
2
2
2
2
2
3

(Hex)
F9
37
F9
F9
F9
F9
C6
E6
99
B0
B0
B0
B0
B0
B0
B0
B0
B0
B0
B0
E2
96
E0
94
E8
CA
CB
35
3D
61
3F
C5
39
CE
30
31
34
45

Set Max Address
Set Max Address Ext
Set Max Freeze Lock
Set Max Lock
Set Max Set Password
Set Max Unlock
Set Multiple Mode
Sleep
Sleep*
S.M.A.R.T. Disable Operations
S.M.A.R.T. Enable/Disable Attribute Auto save
S.M.A.R.T. Enable/Disable Automatic Off-line
S.M.A.R.T. Enable Operations
S.M.A.R.T. Execute Off-line Immediate
S.M.A.R.T. Read Attribute Values
S.M.A.R.T. Read Attribute Thresholds
S.M.A.R.T. Read Log Sector
S.M.A.R.T. Return Status
S.M.A.R.T. Save Attribute Values
S.M.A.R.T. Write Log Sector
Standby
Standby*
Standby Immediate
Standby Immediate*
Write Buffer
Write DMA
Write DMA
Write DMA Ext
Write DMA FUA Ext
Write FPDMA Queued
Write Log Ext
Write Multiple
Write Multiple Ext
Write Multiple FUA Ext
Write Sector(s)
Write Sector(s)
Write Sector(s) Ext
Write Uncorrectable Ext

Protocol :

7
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
0
1
0
0
0
0

6
1
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
1
1
1
0
0
1
0
1
0
1
0
0
0
1

5
1
1
1
1
1
1
0
1
0
1
1
1
1
1
1
1
1
1
1
1
1
0
1
0
1
0
0
1
1
1
1
0
1
0
1
1
1
0

4
1
1
1
1
1
1
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
1
0
1
0
0
0
1
1
0
1
0
1
0
1
1
1
0

1 : PIO data IN command
2 : PIO data OUT command
3 : Non data command
4 : DMA command
5 : First-parity DMA command
+ : Vendor specific command

Table 41 Command Set - continued
Commands marked * are alternate command codes for previously defined commands.
Command (Subcommand)

Command code
(Hex)
75/173

Feature
Register

3
1
0
1
1
1
1
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
1
0
1
0
1
1
0
0
0
0

2
0
1
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
0
1
1
0
1
1
0
1
0
0
1
1

1
0
1
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
1
1
0
0
0
1
0
0
1
0
0
0
0

0
1
1
1
1
1
1
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
1
0
1

7K200 SATA OEM Specification
(Hex)
(S.M.A.R.T Function)
S.M.A.R.T. Read Attribute Values
S.M.A.R.T. Read Attribute Thresholds
S.M.A.R.T. Enable/Disable Attribute Autosave
S.M.A.R.T. Save Attribute Values
S.M.A.R.T. Execute Off-line Immediate
S.M.A.R.T. Read Log Sector
S.M.A.R.T. Write Log Sector
S.M.A.R.T. Enable Operations
S.M.A.R.T. Disable Operations
S.M.A.R.T. Return Status
S.M.A.R.T. Enable/Disable Automatic Off-line
(Set Features)
Enable Write Cache
Set Transfer Mode
Enable Advanced Power Management feature
Enable Power-Up in Standby feature
Power-Up in Standby feature device Spin-Up
Enable use of Serial ATA feature
Enable Automatic Acoustic Management (AAM)
Disable read look-ahead feature
Disable reverting to power on defaults
Disable write cache
Disable Advanced Power Management feature
Disable Power-Up in Standby feature
Disable use of Serial ATA feature
Enable read look-ahead feature
Disable AAM
Enable reverting to power on defaults
(Set Max security extension)
Set Max Set Password
Set Max Lock
Set Max Unlock
Set Max Freeze Lock
(Device Configuration Overlay)
Device Configuration Restore
Device Configuration Freeze Lock
Device Configuration Identify
Device Configuration Set
Table 42 Command Set (Subcommand)

B0
B0
B0
B0
B0
B0
B0
B0
B0
B0
B0

D0
D1
D2
D3
D4
D5
D6
D8
D9
DA
DB

EF
EF
EF
EF
EF
EF
EF
EF
EF
EF
EF
EF
EF
EF
EF
EF

02
03
05
06
07
10
42
55
66
82
85
86
90
AA
C2
CC

F9
F9
F9
F9

01
02
03
04

B1
B1
B1
B1

C0
C1
C2
C3

“Table 40 Command set” on Page 74 shows the commands that are supported by the device. “ Table
42 Command Set (Subcommand)” on Page 76 shows the sub-commands that are supported by each
command or feature.
The following symbols are used in the command descriptions:
Output Registers
Indicates that the bit must be set to 0.
0
Indicates that the bit must be set to 1.
1
Head number. Indicates that the head number part of the Device Register is an output parameter and should
H
be specified.
LBA mode. Indicates the addressing mode. Zero specifies CHS mode and one does LBA addressing mode.
L
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7K200 SATA OEM Specification
Retry. Original meaning is already obsolete, there is no difference between 0 and 1. (Using 0 is
R
recommended for future compatibility.)
Option Bit. Indicates that the Option Bit of the Sector Count Register should be specified. (This bit is used by
B
Set Max ADDRESS command)
Valid. Indicates that the bit is part of an output parameter and should be specified.
V
Indicates that the hex character is not used.
x
Indicates that the bit is not used.
Input Registers
Indicates that the bit is always set to 0.
0
Indicates that the bit is always set to 1.
1
Head number. Indicates that the head number part of the Device Register is an input parameter and will be
H
set by the device.
Valid. Indicates that the bit is part of an input parameter and will be set to 0 or 1 by the device.
V
Not recommendable condition for start up. Indicates that the condition of device is not recommendable for
N
start up.
Indicates that the bit is not part of an input parameter.
The command descriptions show the contents of the Status and Error Registers after the device has
completed processing the command.

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7K200 SATA OEM Specification

14.1 Check Power Mode (E5h/98h)
Command Block Output Registers
Register
7 6
Data
- Feature
- Sector Count
- LBA Low
- LBA Mid
- LBA High
- Device
- Command
1 1

7
6
CRC UNC

5
0

5
1

4
0

3
0

Error Register
4
3
2
1
IDN
0
ABT T0N

2
1

1
0

0
1

0
AM
N
0
0
0
0
0
V
0
0
Table 43 Check Power Mode Command (E5h/98h)

Command Block Input Registers
Register
7
Data
Error
Sector Count
V
LBA Low
LBA Mid
LBA High
Device
Status

7
6
BSY RDY
0

5
DF
0

6 5 4 3 2 1
- - - - - ...See Below...
V V V V V V
- - - - - - - - - - - - - - - - - - - ...See Below...

0
V
-

Status Register
4
3
2
1
0
DSC DRQ COR IDX ERR
-

The Check Power Mode command will report whether the device is spun up and the media is
available for immediate access.
Input Parameters From The Device
The power mode code. The command returns FFh in the Sector Count Register if the spindle
Sector Count
motor is at speed and the device is not in Standby or Sleep mode. Otherwise, the Sector Count
Register will be set to 0.

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7K200 SATA OEM Specification

14.2 Device Configuration Overlay (B1h)
Command Block Output Registers
Register
7 6
Data
- Feature
1 0
Sector Count
- LBA Low
- LBA Mid
- LBA High
- Device
- Command
1 0

7
6
CRC UNC

5
0

5
1
1

4
0
1

3
V
0

2
V
0

1
V
0

0
V
1

Command Block Input Registers
Register
7
Data
Error
Sector Count
V
LBA Low
LBA Mid
V
LBA High
V
Device
Status

Error Register
4
3
2
1
IDN
0
ABT T0N

0
7
6
AM
BSY RDY
N
0
0
0
0
0
V
0
0
V
V
Table 44 Device Configuration Overlay Command (B1h)

6 5 4 3 2 1
- - - - - ...See Below...
V V V V V V
- - - - - V V V V V V
V V V V V V
- - - - - ...See Below...

0
V
V
V
-

Status Register
5
4
3
2
1
0
DF DSC DRQ COR IDX ERR
0

Individual Device Configuration Overlay feature set commands are identified by the value placed in
the Features register. The table below shows these Features register values.
Value
Command
C0h
DEVICE CONFIGURATION RESTORE
C1h
DEVICE CONFIGURATION FREEZE LOCK
C2h
DEVICE CONFIGURATION IDENTIFY
C3h
DEVICE CONFIGURATION SET
other
Reserved
Table 45 Device Configuration Overlay Features register values

14.2.1

DEVICE CONFIGURATION RESTORE (subcommand
C0h)

The DEVICE CONFIGURATION RESTORE command discard any setting previously made by a
DEVICE CONFIGURATION SET command and return the content of the IDENTIFY DEVICE
command response to the original settings as indicated by the data returned from the execution of a
DEVICE CONFIGURATION IDENTIFY command.

14.2.2

DEVICE CONFIGURATION FREEZE LOCK
(subcommand C1h)

The DEVICE CONFIGURATION FREEZE LOCK command prevents accidental modification of the
Device Configuration Overlay settings. After successful execution of a DEVICE CONFIGURATION
FREEZE LOCK command, all DEVICE CONFIGURATION SET, DEVICE CONFIGURATION
FREEZE LOCK, DEVICE CONFIGURATION IDENTIFY, and DEVICE CONFIGURATION
RESTORE commands are aborted by the device. The DEVICE CONFIGURATION FREEZE LOCK
condition shall be cleared by a power-down. The DEVICE CONFIGURATION FREEZE LOCK
condition shall not be cleared by COMRESET or software reset.

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7K200 SATA OEM Specification

14.2.3

DEVICE CONFIGURATION IDENTIFY (subcommand
C2h)

The DEVICE CONFIGURATION IDENTIFY command returns a 512 byte data structure via PIO
data-in transfer. The content of this data structure indicates the selectable commands, modes, and
feature sets that the device is capable of supporting. If a DEVICE CONFIGURATION SET command
has been issued reducing the capabilities, the response to an IDENTIFY DEVICE or IDENTIFY
PACKET DEVICE command will reflect the reduced set of capabilities, while the DEVICE
CONFIGURATION IDENTIFY command will reflect the entire set of selectable capabilities.
The format of the Device Configuration Overlay data structure is shown on next page.

14.2.4

DEVICE CONFIGURATION SET (subcommand C3h)

The DEVICE CONFIGURATION SET command allows a device manufacturer or a personal
computer system manufacturer to reduce the set of optional commands, modes, or feature sets
supported by a device as indicated by a DEVICE CONFIGURATION IDENTIFY command. The
DEVICE CONFIGURATION SET command transfers an overlay that modifies some of the bits set
in words 63, 78, 79, 82, 83, 84, and 88 of the IDENTIFY DEVICE command response. When the bits
in these words are cleared, the device no longer supports the indicated command, mode, or feature
set. If a bit is set in the overlay transmitted by the device that is not set in the overlay received from
a DEVICE CONFIGURATION IDENTIFY command, no action is taken for that bit.
The format of the overlay transmitted by the device is described in the table at next page. The
restrictions on changing these bits are described in the text following that table. If any of the bit
modification restrictions described are violated or any setting is changed with DEVICE
CONFIGURATION SET command, the device shall return command aborted. At that case, error
reason code is returned to sector count register, invalid word location is returned to LBA High
register, and invalid bit location is returned to LBA Mid register. The Definition of error information
is shown on the next page.
ERROR INFORMATION EXAMPLE 1:
After establish a protected area with SET MAX address, if a user attempts to execute DC SET or DC
RESTORE, device abort that command and return error reason code as below.
LBA High
: 03h
= word 3 is invalid
LBA Mid
: 00h
this register is not assigned in this case
Sector count
: 06h
= Protected area is now established
ERROR INFORMATION EXAMPLE 2:
When device is enabled the Security feature set, if user attempts to disable that feature, device abort
that command and return error reason code as below.
LBA High
LBA Mid
Sector count

: 07h
: 08h
: 04h

= word 7 is invalid
= bit 3 is invalid
= now Security feature set is enabled

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7K200 SATA OEM Specification
Word

Content
0002h
Data Structure revision
Multiword DMA modes supported
15-3 Reserved
2 1 = Multiword DMA mode 2 and below are supported
1 1 = Multiword DMA mode 1 and below are supported
0 1 = Multiword DMA mode 0 is supported
2
Ultra DMA modes supported
15-6 Reserved
5 1 = Ultra DMA mode 5 and below are supported
4 1 = Ultra DMA mode 4 and below are supported
3 1 = Ultra DMA mode 3 and below are supported
2 1 = Ultra DMA mode 2 and below are supported
1 1 = Ultra DMA mode 1 and below are supported
0 1 = Ultra DMA mode 0 is supported
3-6
Maximum LBA address
7
Command set/feature set supported
15-9 Reserved
8 1 = 48-bit Addressing feature set supported
7 1 = Host Protected Area feature set supported
6 1 = Automatic acoustic management supported
5 Reserved
4 1 = Power-Up in Standby feature set supported
3 1 = Security feature set supported
2 1 = SMART error log supported
1 1 = SMART self-test supported
0 1 = SMART feature set supported
8
SATA feature
15-5 Reserved
4 1 = Software setting preservation supported
3 Reserved
2 1 = Interface power management supported
1 1 = Non-zero buffer offset in DMA Setup FIS supported
0 1 = Native command queuing supported
9-254
Reserved
255
Integrity word
15-8
Checksum
7-0
Signature (A5h)
Table 46 Device Configuration Overlay Data structure
0
1

Note.
Bits 7:0 of this word contain the value A5h. Bits 15:8 of this word contain the data structure
checksum. The data structure checksum is the two’s complement of the sum of all byte in words 0
through 254 and the byte consisting of bits 7:0 of word 255. Each byte is added with unsigned
arithmetic, and overflow is ignored. The sum of all bytes is zero when the checksum is correct.

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7K200 SATA OEM Specification

LBA High
LBA Mid
LBA Low
Sector count

invalid word location
invalid bit location (bits (7:0))
invalid bit location (bits (15:8))
error reason code & description
01h DCO feature is frozen
02h Device is now Security Locked mode
03h Device’s feature is already modified with DCO
04h User attempt to disable any feature enabled
05h Device is now SET MAX Locked or Frozen mode
06h Protected area is now established
07h DCO is not supported
08h Subcommand code is invalid
FFh other reason
Table 47 DCO error information definition

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7K200 SATA OEM Specification

14.3 Execute Device Diagnostic (90h)
Command Block Output Registers
Register
7 6
Data
- Feature
- Sector Count
- LBA Low
- LBA Mid
- LBA High
- Device
- Command
1 0

7
6
CRC UNC

5
0

4
1

3
0

Error Register
4
3
2
1
IDN
0
ABT T0N

2
0

1
0

0
0

0
AM
N
0
V
V
V
V
V
V
V
Table 48 Execute Device Diagnostic Command (90h)

Command Block Input Registers
Register
7
Data
Error
Sector Count
LBA Low
LBA Mid
LBA High
Device
Status

7
6
BSY RDY
0

6 5 4 3 2 1
- - - - - ...See Below...
- - - - - - - - - - - - - - - - - - - - - - - - - ...See Below...

0
-

Status Register
5
4
3
2
1
0
DF DSC DRQ COR IDX ERR
0

The Execute Device Diagnostic command performs the internal diagnostic tests implemented by the
device. The results of the test are stored in the Error Register.
The normal Error Register bit definitions do not apply to this command. Instead, the register
contains a diagnostic code. See “Table 31 Diagnostic Codes” on Page 51 for the definition.

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7K200 SATA OEM Specification

14.4 Flush Cache (E7h)
Command Block Output Registers
Register
7 6
Data
- Feature
- Sector Count
- LBA Low
- LBA Mid
- LBA High
- Device
- Command
1 1

7
6
CRC UNC

5
0

5
1

4
0

3
0

Error Register
4
3
2
1
IDN
0
ABT T0N

0
0
0
0
0
V
Table 49 Flush Cache Command (E7h)

2
1

1
1

0
1

0
AM
N
0

Command Block Input Registers
Register
7
Data
Error
Sector Count
LBA Low
LBA Mid
LBA High
Device
Status

7
6
BSY RDY
0

5
DF
0

The device returns a status, RDY=1 and DSC=1 (50h), after following sequence.

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0
-

Status Register
4
3
2
1
0
DSC DRQ COR IDX ERR

This command causes the device to complete writing data from its cache.

Data in the write cache buffer is written to disk media.
Return a successfully completion.

6 5 4 3 2 1
- - - - - ...See Below...
- - - - - - - - - - - - - - - - - - - - - - - - - ...See Below...

7K200 SATA OEM Specification

14.5 Flush Cache Ext (EAh)
Command Block Output Registers
Register
7 6 5 4 3 2 1 0
Data Low
- - - - - - - Data High
- - - - - - - Feature
Current
- - - - - - - Previous
- - - - - - - Sector Count Current
- - - - - - - Previous
- - - - - - - LBA Low
Current
- - - - - - - Previous
- - - - - - - LBA Mid
Current
- - - - - - - Previous
- - - - - - - LBA High
Current
- - - - - - - Previous
- - - - - - - Device
- - - - - - - Command
1 1 1 0 1 0 1 0
Error Register
7
6
5
4
3
2
1
0
CRC UNC 0 IDN 0 ABT T0N AMN
0
0
0
0
0
V
0
0
Table 50 Flush Cache EXT Command (EAh)

Command Block Input Registers
Register
7 6 5 4 3 2 1 0
Data Low
- - - - - - - Data High
- - - - - - - Error
...See Below...
Sector Count
LBA Low
LBA Mid
LBA High

HOB=0
HOB=1
HOB=0
HOB=1
HOB=0
HOB=1
HOB=0
HOB=1

Device
Status

- - - - - - - - - - - - - - - - - - - - - - - - - - - ...See Below...

Status Register
7
6
5
4
3
2
BSY RDY DF DSC DRQ COR
0
V
0
V
0

This command causes the device to complete writing data from its cache.
The device returns good status after data in the write cache is written to disk media.

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1
IDX
0

0
ERR
V

7K200 SATA OEM Specification

14.6 Format Track (50h: Vendor Specific)
Command Block Output Registers
Register
7 6
Data
- Feature
- Sector Count
- LBA Low
V V
LBA Mid
V V
LBA High
V V
Device
- L
Command
0 1

7
6
CRC UNC

5
0

5
V
V
V
0

4
V
V
V
1

3
V
V
V
H
0

2
V
V
V
H
0

Error Register
4
3
2
1
IDN
0
ABT T0N

0
0
0
V
0
V
Table 51 Format Track Command (50h)

1
V
V
V
H
0

0
V
V
V
H
0

0
AM
N
0

Command Block Input Registers
Register
7
Data
Error
Sector Count
LBA Low
V
LBA Mid
V
LBA High
V
Device
Status

7
6
BSY RDY
0

5
DF
0

6 5 4 3 2 1
- - - - - ...See Below...
- - - - - V V V V V V
V V V V V V
V V V V V V
- - - H H H
...See Below...

0
V
V
V
H

Status Register
4
3
2
1
0
DSC DRQ COR IDX ERR
V

The Format Track command formats a single logical track on the device. Each good sector of data on
the track will be initialized to zero with write operation. At this time, whether the sector of data is
initialized correctly is not verified with read operation. Any data previously stored on the track will
be lost.
Output Parameters To The Device
In LBA mode, this register specifies LBA address bits 0 - 7 to be formatted. (L=1)
LBA Low
The cylinder number of the track to be formatted. (L=0)
LBA High/Mid
In LBA mode, this register specifies LBA address bits 8 - 15 (Mid), 16 - 23 (High) to be
formatted. (L=1)
The head number of the track to be formatted. (L=0)
H
In LBA mode, this register specifies LBA address bits 24 - 27 to be formatted. (L=1)
Input Parameters From The Device
In LBA mode, this register specifies current LBA address bits 0-7. (L=1)
LBA Low
In LBA mode, this register specifies current LBA address bits 8 - 15 (Mid), 16 - 23 (High)
LBA High/Mid
In LBA mode, this register specifies current LBA address bits 24 - 27. (L=1)
H
In LBA mode, this command formats a single logical track including the specified LBA.

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7K200 SATA OEM Specification

14.7 Format Unit (F7h: Vendor Specific)
Command Block Output Registers
Register
7 6
Data
- Feature
V V
Sector Count
- LBA Low
- LBA Mid
- LBA High
- Device
- Command
1 1

7
8
CRC UNC

9
0

5
V
1

4
V
1

3
V
0

2
V
1

Error Register
10
3
2
1
IDN
0
ABT T0N

0
0
0
V
0
V
Table 52 Format Unit Command (F7h)

1
V
1

0
V
1

0
AM
N
0

Command Block Input Registers
Register
7
Data
Error
Sector Count
LBA Low
LBA Mid
LBA High
Device
Status

7
6
BSY RDY
0

6 5 4 3 2 1
- - - - - ...See Below...
- - - - - - - - - - - - - - - - - - - - - - - - - ...See Below...

0
-

Status Register
5
4
3
2
1
0
DF DSC DRQ COR IDX ERR
0

The Format Unit command initializes all user data sectors after merging reassigned sector location
into the defect information of the device and clearing the reassign information. Both new reassign
information and new defect information are available right after this command completion, and are
also used on next power on reset. Both previous information are erased from the device by this
command.
Note that the Format Unit command initializes from LBA 0 to Native MAX LBA. Host MAX LBA set
by Initialize Drive Parameter or Set MAX ADDRESS command is ignored. So the protected area by
Set MAX ADDRESS commands is also initialized.
The security erase prepare command should be completed immediately prior to the Format Unit
command. If the device receives a Format Unit command without a prior Security Erase Prepare
command the device aborts the Format Unit command.
If Feature register is NOT 11h, the device returns Abort error to the host.
This command does not request to data transfer.
Output Parameters To The Device
Destination code for this command
Feature
11H Merge reassigned location into the defect information
The execution time of this command is shown below.
HTS722020K9SA00 / HTS722020K9A300
HTS722016K9SA00 / HTS722016K9A300
HTS722012K9SA00 / HTS722012K9A300
HTS722010K9SA00 / HTS722010K9A300
HTS722080K9SA00 / HTS722080K9A300

71 min
63 min
48 min
37 min
33 min

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7K200 SATA OEM Specification

14.8 Identify Device (ECh)
Command Block Output Registers
Register
7 6
Data
- Feature
- Sector Count
- LBA Low
- LBA Mid
- LBA High
- Device
- Command
1 1

7
6
CRC UNC

5
0

5
1

4
0

3
1

Error Register
4
3
2
1
IDN
0
ABT T0N

0
0
0
0
0
V
0
Table 53 Identify Device Command (ECh)

2
1

1
0

0
0

0
AM
N
0

Command Block Input Registers
Register
7
Data
Error
Sector Count
LBA Low
LBA Mid
LBA High
Device
Status

7
6
BSY RDY
0

6 5 4 3 2 1
- - - - - ...See Below...
- - - - - - - - - - - - - - - - - - - - - - - - - ...See Below...

0
-

Status Register
5
4
3
2
1
0
DF DSC DRQ COR IDX ERR
0

The Identify Device command requests the device to transfer configuration information to the host.
The device will transfer a sector to the host containing the information in “Table 54 Identify device
information” on Page 88-97.

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7K200 SATA OEM Specification

Word

Description
Drive classification, bit assignments:
15 (=0): 1=ATAPI device, 0=ATA device
*
14 (=0): 1=format speed tolerance gap required
*
13 (=0): 1=track offset option available
*
12 (=0): 1=data strobe offset option available
*
11 (=0): 1=rotational speed tolerance > 0.5%
*
10 (=1): 1=disk transfer rate > 10 Mbps
*
9 (=0): 1=disk transfer rate > 5 Mbps but <= 10 Mbps
*
8 (=0): 1=disk transfer rate <= 5 Mbps
7 (=0): 1=removable cartridge device
6 (=1): 1=fixed device
*
5 (=0): 1=spindle motor control option implemented
*
4 (=1): 1=head switch time > 15 us
*
3 (=1): 1=not MFM encoded
2 (=x): 1=Identify data incomplete
*
1 (=1): 1=hard sectored
0 (=0): Reserved
01
Note.2
Number of cylinders in default translate mode
02
xxxxh
Specific configuration
C837h
SET FEATURES subcommand is not required to spin-up
and IDENTIFY DEVICE response is complete
37C8h
SET FEATURES subcommand is required to spin-up and
IDENTIFY DEVICE response is incomplete
03
Note.2
Number of heads in default translate mode
04-05
0
*
Reserved
06
003FH
Number of sectors per track in default translate mode
07-09
0
Reserved
10-19
XXXX
Serial number in ASCII (0 = not specified)
20
0003H
*
Controller type:
0003: dual ported, multiple sector buffer with look-ahead read
21
Note.2
*
Buffer size in number of sectors
22
00xxH
*
Obsolete
23-26
XXXX
Microcode version in ASCII
27-46
Note.2
Model number in ASCII
47
8010H
Maximum number of sectors that can be transferred per interrupt on Read
and Write Multiple commands
15-8 : (=80h)
7-0 : Maximum number of sectors that can be transferred per
interrupt.
Note.1 The ‘*’ mark in ‘Content’ field indicates the use of those parameters that are vendor specific.
00

Content
045xH

Note.2 See following table “Table 63 Number of cylinders/heads/sectors by models for
HTS7220XXK9SA00 / HTS7220XXK9A300” on Page 98

Table 54 Identify device information

89/173

7K200 SATA OEM Specification

Word

Content
4000H

Description
48
Trusted Computing feature set options
15(=0) Always 0
14(=1) Always 1
13- 1(=0) Reserved
0(=0) 1=Trusted Computing feature set is supported
49
0F00H
Capabilities, bit assignments:
15-14 (=0) Reserved
13 (=0) 0= Standby timer value are vendor specific
12 (=0) Reserved
11 (=1) 1= IORDY Supported
10 (=1) 1= IORDY can be disabled
9 (=1) 1=LBA Supported
8 (=1) 1=DMA Supported
*
7- 0 (=0) Reserved
50
4000H
Capabilities
15 (=0) 0=the contents of word 50 are valid
14 (=1) 1=the contents of word 50 are valid
13- 2 (=0) Reserved
1 (=0) Obsolete
0 (=0) 1=the device has a minimum Standby timer value that is
device specific
51
0200H
* PIO data transfer cycle timing mode
52
0200H
* DMA data transfer cycle timing mode
Refer Word 62 and 63
53
0007H
Validity flag of the word
15- 3(=0) Reserved
2(=1) 1=Word 88 is Valid
1(=1) 1=Word 64-70 are Valid
0(=1) 1=Word 54-58 are Valid
54
xxxxH
Number of current cylinders
55
xxxxH
Number of current heads
56
xxxxH
Number of current sectors per track
57-58
xxxxH
Current capacity in sectors
Word 57 specifies the low word of the capacity
59
0xxxH
Current Multiple setting. bit assignments
15- 9 (=0) Reserved
8 1= Multiple Sector Setting is Valid
7- 0 xxh = Current setting for number of sectors
60-61
Note.2
Total Number of User Addressable Sectors
Word 60 specifies the low word of the number
FFFFFFFh=The 48-bit native max address is greater than 268,435,455
62
0000H
* Reserved
Note.1 The ‘*’ mark in ‘Content’ field indicates the use of those parameters that are vendor specific.
Note.2 See following table “Table 63 Number of cylinders/heads/sectors by models for
HTS7220XXK9SA00 / HTS7220XXK9A300” on Page 98

Table 55 Identify device information --- Continued ---

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7K200 SATA OEM Specification

Word

Content
0x07H

Description
63
Multiword DMA Transfer Capability
15-11(=0) Reserved
10 1=Multiword DMA mode 2 is selected
9 1=Multiword DMA mode 1 is selected
8 1=Multiword DMA mode 0 is selected
7- 3 (=0) Reserved
2 (=1) 1=Multiword DMA mode 2 is supported
1 (=1) 1=Multiword DMA mode 1 is supported
0 (=1) 1=Multiword DMA mode 0 is supported
64
0003H
Flow Control PIO Transfer Modes Supported
15- 8 (=0) Reserved
7- 0 (=3) Advanced PIO Transfer Modes Supported
‘11’ = PIO Mode 3 and 4 Supported
65
0078H
Minimum Multiword DMA Transfer Cycle Time Per Word
15- 0 (=78h) Cycle time in nanoseconds (120ns, 16.6MB/s)
66
0078H
Manufacturer’s Recommended Multiword DMA Transfer Cycle Time
15- 0 (=78h) Cycle time in nanoseconds (120ns, 16.6MB/s)
67
0078H
Minimum PIO Transfer Cycle Time Without Flow Control
15- 0 (=78h) Cycle time in nanoseconds (120ns, 16.6MB/s)
68
0078H
Minimum PIO Transfer Cycle Time With IORDY Flow Control
15- 0 (=78h) Cycle time in nanoseconds (120ns, 16.6MB/s)
69-74
0000H
Reserved
75
001FH
Queue depth
15-5(=0) Reserved
4-0(=1Fh) Maximum queued depth - 1
76
170xH
SATA capabilities
15-13(=0) Reserved
1=Native Command Queuing priority information
12(=1)
supported
1=Unload while NCQ commands outstanding
11(=0)
supported
10(=1) 1=Phy event counters supported
1=Receipt of host-initiated interface power
9(=1)
management requests supported
8(=1) 1=Native Command Queuing supported
7-3(=0) Reserved
**2(=x) 1=SATA Gen-2 speed (3.0Gbps) supported
1(=1) 1=SATA Gen-1 speed (1.5Gbps) supported
0(=0) Reserved
77
0000H
Reserved
Note.1 The ‘*’ mark in ‘Content’ field indicates the use of those parameters that are vendor specific.
Note.2 The ‘**’ mark depends on HTS7220XXK9SA00 or HTS7220XXK9A300.

Table 56 Identify device information --- Continued ---

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7K200 SATA OEM Specification

Word

Description
SATA supported features
15-7(=0) Reserved
6(=1) 1=Software setting preservation supported
5(=0) Reserved
4(=1) 1=In-order data delivery supported
1=Device initiated interface power management
3(=1)
supported
2(=1) 1=DMA Setup Auto-Activate optimization supported
1=Non-zero buffer offset in DMA Setup FIS
1(=1)
supported
0(=0) Reserved
79
00xxH
SATA enabled features
15-7(=0) Reserved
6(=x) 1=Software setting preservation enabled
5(=0) Reserved
4(=x) 1=In-order data delivery enabled
1=Device initiated interface power management
3(=x)
enabled
2(=x) 1=DMA Setup Auto-Activate optimization enabled
1(=x) 1=Non-zero buffer offset in DMA Setup FIS enabled
0(=0) Reserved
80
01FCH
Major version number
ATA-2.3 and ATA/ATAPI-4, 5, 6, 7, 8
81
0042H
Minor version number—ATA8-ACS revision 3f -82
746BH
Command set supported
15 (=0) Reserved
14 (=1) 1=NOP command supported
13 (=1) 1=READ BUFFER command supported
12 (=1) 1=WRITE BUFFER command supported
11 (=0) Reserved
10 (=1) 1=Host Protected Area Feature Set supported
9 (=0) 1=DEVICE RESET command supported
8 (=0) 1=SERVICE interrupt supported
7 (=0) 1=release interrupt supported
6 (=1) 1=look-ahead supported
5 (=1) 1=write cache supported
4 (=0) 1=supports PACKET Command Feature Set
3 (=1) 1=supports Power Management Feature Set
2 (=0) 1=supports Removable Media Feature Set
1 (=1) 1=supports Security Feature Set
0 (=1) 1=supports S.M.A.R.T Feature Set
Note.1 The ‘*’ mark in ‘Content’ field indicates the use of those parameters that are vendor specific.
78

Content
005EH

Table 57 Identify device information --- Continued ---

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7K200 SATA OEM Specification

Word

Content
7F69H

Description
83
Command set supported
15 (=0) Always
14 (=1) Always
13 (=1) 1=FLUSH CACHE EXT command supported
12 (=1) 1=FLUSH CACHE command supported
11 (=1) 1=Device Configuration Overlay command supported
10 (=1) 1=48-bit Address feature set supported
9 (=1) 1=Automatic Acoustic Management supported
8 (=1) 1=SET MAX security extension supported
7 (=0) Reserved
6 (=1) 1=SET FEATURES subcommand required to spin-up
5 (=1) 1=Power-Up In Standby feature set supported
4 (=0) 1=Removable Media Status Notification Feature Set
supported
3 (=1) 1=Advanced Power Management Feature Set
supported
2 (=0) 1=CFA Feature Set supported
1 (=0) 1=READ/WRITE DMA QUEUED supported
0 (=1) Download Microcode Command Supported
84
6163H
Command set/feature supported extension
15 (=0) Always
14 (=1) Always
13 (=1) 1=IDLE IMMEDIATE with UNLOAD FEATURE
supported
12- 9 (=0) Reserved
8 (=1) 1=64-bit World wide name supported
7 (=0) 1=WRITE DMA QUEUED FUA EXT command
supported
6 (=1) 1=WRITE DMA FUA EXT and WRITE MULTIPLE
FUA EXT commands supported
5 (=1) 1=General Purpose Logging feature set supported
4- 2 (=0) Reserved
1 (=1) 1=SMART self-test supported
0 (=1) 1=SMART error logging supported
Note.1 The ‘*’ mark in ‘Content’ field indicates the use of those parameters that are vendor specific.

Table 58 Identify device information --- Continued ---

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7K200 SATA OEM Specification

Word

Content
74xxH

Description
85
Command set/feature enabled
15 (=0) Obsolete
14 (=1) 1=NOP command supported
13 (=1) 1=READ BUFFER command supported
12 (=1) 1=WRITE BUFFER command supported
11 (=0) Reserved
10 (=1) 1=Host Protected Area Feature Set supported
9 (=0) 1=DEVICE RESET command supported
8 (=0) 1=SERVICE interrupt enabled
7 (=0) 1=release interrupt enabled
6 (=x) 1=look-ahead enabled
5 (=x) 1=write cache enabled
4 (=0) 1=supports PACKET Command Feature Set
3 (=1) 1=supports Power Management Feature Set
2 (=0) 1=supports Removable Media Feature Set
1 (=x) 1=Security Feature Set enabled
0 (=x) 1=S.M.A.R.T Feature Set enabled
86
BxxxH
Command set/feature enabled
15 (=1) 1=Words 120:119 are valid
*
14 (=0) Reserved
13 (=1) 1=FLUSH CACHE EXT command supported
12 (=1) 1= FLUSH CACHE command supported
11 (=x) 1=Device Configuration Overlay supported
*
10 (=1) 1= 48-bit Address feature set supported
9 (=x) 1=Automatic Acoustic Management enabled
8 (=x) 1=SET MAX security extension enabled
7 (=0) Reserved
6 (=1) 1=SET FEATURES subcommand required to spin-up
5 (=x) 1=Power-Up In Standby feature set has been enabled
via the SET FEATURES command
4 (=0) 1=Removable Media Status Notification Feature Set
enabled
3 (=x) 1=Advanced Power Management Feature Set enabled
2 (=0) 1=CFA Feature Set supported
1 (=0) 1=READ/WRITE DMA QUEUED command
supported
0 (=1) 1=DOWNLOAD MICROCODE command supported
Note.1 The ‘*’ mark in ‘Content’ field indicates the use of those parameters that are vendor specific.

Table 59 Identify device information --- Continued ---

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7K200 SATA OEM Specification

Word

Content
6163H

Description
87
Command set/feature enabled
15 (=0) Always
14 (=1) Always
13 (=1) 1=IDLE IMMEDIATE with UNLOAD FEATURE
supported
12- 9 (=0) Reserved
8 (=1) 1=64 bit World wide name supported
7 (=0) 1=WRITE DMA QUEUED FUA EXT command
supported
6 (=1) 1=WRITE DMA FUA EXT and WRITE MULTIPLE
FUA EXT command supported
5 (=1) 1=General Purpose Logging feature set supported
4- 2 (=0) Reserved
1 (=1) 1=SMART self-test supported
0 (=1) 1=SMART error logging supported
88
xx7FH
Ultra DMA Transfer mode (mode 6 supported)
15 (=0) Reserved
14 (=x) 1=UltraDMA mode 6 is selected
13 (=x) 1=UltraDMA mode 5 is selected
12 (=x) 1=UltraDMA mode 4 is selected
11 (=x) 1=UltraDMA mode 3 is selected
10 (=x) 1=UltraDMA mode 2 is selected
9 (=x) 1=UltraDMA mode 1 is selected
8 (=x) 1=UltraDMA mode 0 is selected
7 (=0) Reserved
6 (=1) 1=UltraDMA mode 6 is supported
5 (=1) 1=UltraDMA mode 5 is supported
4 (=1) 1=UltraDMA mode 4 is supported
3 (=1) 1=UltraDMA mode 3 is supported
2 (=1) 1=UltraDMA mode 2 is supported
1 (=1) 1=UltraDMA mode 1 is supported
0 (=1) 1=UltraDMA mode 0 is supported
Note.1 The ‘*’ mark in ‘Content’ field indicates the use of those parameters that are vendor specific.

Table 60 Identify device information --- Continued ---

95/173

7K200 SATA OEM Specification

Word

Content
xxxxH

Description
89
Time required for security erase unit completion
Time= value(xxxxh)*2 [minutes]
90
xxxxH
Time required for Enhanced security erase completion
Time= value(xxxxh)*2 [minutes]
91
40xxH
Current Advanced Power Management level
15- 8 (=40h) Reserved
7- 0 (=xxh) Currect Advanced Power Management level set by Set
Features Command (01h to FEh)
92
xxxxH
Current Master Password Revision Codes
93
0000H
Reserved
94
80xxH
Automatic Acoustic Management value
15-8 Vendor’s Recommended Acoustic Management level
7-0 Current Automatic Acoustic Management value
Default value is FEh
95
0000H
Stream Minimum Request Size
96
0000H
Streaming Transfer Time – DMA
97
0000H
Streaming Access Latency – DMA and PIO
98-99
0000H
Streaming Performance Granularity
100-103
Note.2
Maximum user LBA address for 48-bit Address feature set
104
0000H
Streaming Transfer Time - PIO
105-106
0000H
Reserved
107
7AB8H
Inter seek delay time (1.5tt + 2.5tl)
108-111
XXXX
World Wide Name
112-118
0000H
Reserved
119
4004H
Supported Setting
15 (=0) Always
14 (=1) Always
13-5 (=0) Reserved
4 (=0) 1=Segmented feature for Download is supported
3 (=0) 1=Read and Write DMA Ext GPL is supported
2 (=1) 1=WRITE UNCORRECTABLE is supported
1 (=0) 1=Write Read Verify feature set is supported
0 (=0) Reserved
120
4004H
Enabled Setting
15 (=0) Always
14 (=1) Always
13-3 (=0) Reserved
4 (=0) 1=Segmented feature for Download is supported
3 (=0) 1=Read and Write DMA Ext GPL is supported
2 (=1) 1=WRITE UNCORRECTABLE is supported
1 (=0) 1=Write Read Verify feature set is enabled
0 (=0) Reserved
121-126
0000H
Reserved
127
0000H
Removable Media Status Notification feature set
Note.1 The ‘*’ mark in ‘Content’ field indicates the use of those parameters that are vendor specific.

Table 61 Identify device information --- Continued ---

96/173

7K200 SATA OEM Specification

Word
128

Content
0xxxH

Description
Security status. Bit assignments
15-9 (=0) Reserved
8 (=x) Security Level 1= Maximum, 0= High
7-6 (=0) Reserved
5 (=1) 1=Enhanced security erase supported
4 (=x) 1=Security count expired
3 (=x) 1=Security Frozen
2 (=x) 1=Security locked
1 (=x) 1=Security enabled
**0 (=1) 1=Security supported
129
000xH
* Current Set Feature Option. Bit assignments
15-4(=0) Reserved
3(=x) 1=Auto reassign enabled
2(=x) 1=Reverting enabled
1(=x) 1=Read Look-ahead enabled
0(=x) 1=Write Cache enabled
130
xxxxH
* Reserved
131
000xH
* Initial Power Mode Selection. Bit assignments
15-1(=0) Reserved
0(=x) Initial Power Mode 1= Standby, 0= Idle
132-205
xxxxH
* Reserved
206
003DH
SCT Command Transport
15- 6(=0) Reserved
5(=1) 1=SCT Data Tables supported
4(=1) 1=SCT Features Control supported
3(=1) 1=SCT Error Recovery Control supported
2(=1) 1=SCT Write Same supported
1(=0) 1=SCT Long Sector Access supported
0(=1) 1=SCT Command Transport supported
207 - 221
xxxxH
* Reserved
222
100FH
Transport Major Revision Number
15- 12 Transport Type 0=Parallel, 1=Serial, 2-15=Reserved
11- 4(=0) Reserved
3(=1) 1=SATA 2.5
2(=1) 1=SATA II: Extensions
1(=1) 1=SATA 1.0a
0(=1) 1=ATA8-AST
223
0021H
Transport Minor Revision Number – ATA8-AST Revision 0b
224 - 254
xxxxH
* Reserved
255
xxA5H
Integrity word
15-8 (=xxh) Checksum
7-0 (=A5h) Signature
Note.1 The ‘*’ mark in ‘Content’ field indicates the use of those parameters that are vendor specific.
Note.2 See following table “Table 63 Number of cylinders/heads/sectors by models for
HTS7220XXK9SA00 / HTS7220XXK9A300” on Page 98

Table 62 Identify device information --- Continued ---

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7K200 SATA OEM Specification

Model Number in ASCII
Number of cylinders
Number of heads
Buffer size
Total number of user
addressable sectors (word
60-61)
Maximum user LBA
address for 48-bit Address
feature set (word 100-103)
Model Number in ASCII
Number of cylinders
Number of heads
Buffer size
Total number of user
addressable sectors (word
60-61)
Maximum user LBA
address for 48-bit Address
feature set (word 100-103)
Model Number in ASCII
Number of cylinders
Number of heads
Buffer size
Total number of user
addressable sectors (word
60-61)
Maximum user LBA
address for 48-bit Address
feature set (word 100-103)
Model Number in ASCII

Hitachi
HTS722020K9SA00
3FFFh
10h
76C6h
FFFFFFFh

Hitachi
HTS722016K9SA00
3FFFh
10h
76C6h
FFFFFFFh

Hitachi
HTS722012K9SA00
3FFFh
10h
76C6h
DF94BB0h

1749F1B0h

12A19EB0h

DF94BB0h

Hitachi
HTS722010KJ9SA00
3FFFh
10h
76C6h
BA52230h

Hitachi
HTS722080K9SA00
3FFFh
10h
76C6h
950F8B0h

BA52230h

950F8B0h

Hitachi
HTS722020K9A300
3FFFh
10h
76C6h
FFFFFFFh

Hitachi
HTS722016K9A300
3FFFh
10h
76C6h
FFFFFFFh

Hitachi
HTS722012K9A300
3FFFh
10h
76C6h
DF94BB0h

1749F1B0h

12A19EB0h

DF94BB0h

Hitachi
HTS722010KJ9A300
3FFFh
10h
76C6h
BA52230h

Hitachi
HTS722080K9A300
3FFFh
10h
76C6h
950F8B0h

Number of cylinders
Number of heads
Buffer size
Total number of user
addressable sectors (word
60-61)
Maximum user LBA
BA52230h
950F8B0h
address for 48-bit Address
feature set (word 100-103)
Table 63 Number of cylinders/heads/sectors by models for HTS7220XXK9SA00 / HTS7220XXK9A300

98/173

7K200 SATA OEM Specification

14.9 Idle (E3h/97h)
Command Block Output Registers
Register
7 6
Data
- Feature
- Sector Count
V V
LBA Low
- LBA Mid
- LBA High
- Device
- Command
1 1

7
6
CRC UNC

5
0

5
V
1

4
V
0

3
V
0

2
V
0

Error Register
4
3
2
1
IDN
0
ABT T0N

0
0
0
0
0
V
Table 64 Idle Command (E3h/97h)

1
V
1

0
V
1

0
AM
N
0

Command Block Input Registers
Register
7
Data
Error
Sector Count
LBA Low
LBA Mid
LBA High
Device
Status

7
6
BSY RDY
0

6 5 4 3 2 1
- - - - - ...See Below...
- - - - - - - - - - - - - - - - - - - - - - - - - ...See Below...

0
-

Status Register
5
4
3
2
1
0
DF DSC DRQ COR IDX ERR
0

When the power save mode is Standby mode, the Idle command causes the device to enter
performance Idle mode immediately, and set auto power down timeout parameter(standby timer).
And then the timer starts counting down. When the device’s power save mode is already any idle
mode, the device keep that mode.
When the Idle mode is entered, the device is spun up to operating speed. If the device is already
spinning, the spin up sequence is not executed.
During Idle mode the device is spinning and ready to respond to host commands immediately.
Output Parameters To The Device
Timeout Parameter. If zero, the timeout interval(Standby Timer) is
disabled. If other than
Sector Count
zero, the timeout interval is set for (Timeout Parameter x5) seconds.
The device will enter Standby mode automatically if the timeout interval expires with no
device access from the host. The timeout interval will be reinitialized if there is a device
access before the timeout interval expires.

99/173

7K200 SATA OEM Specification

14.10

Idle Immediate (E1h/95h)

Command Block Output Registers
Register
7 6
Data
- Feature
- Sector Count
- LBA Low
- LBA Mid
- LBA High
- Device
- Command
1 1

5
1

4
0

3
0

2
0

1
0

Unload Feature
Command Block Output Registers
Register
7 6
Data
- Feature
0 1
Sector Count
0 0
LBA Low
0 1
LBA Mid
0 1
LBA High
0 1
Device
- Command
1 1

5
0
0
0
0
0
1

4
0
0
0
0
1
D
0

3
0
0
1
1
0
0

2
1
0
1
1
1
0

1
0
0
0
1
0
0

7
6
CRC UNC

5
0

Error Register
4
3
2
1
IDN
0
ABT T0N

0
0
0
0
0
V
0
Table 65 Idle Immediate Command (E1h/95h)

0
AM
N
0

0
1

Command Block Input Registers
Register
7
Data
Error
Sector Count
LBA Low
LBA Mid
LBA High
Device
Status

6 5 4 3 2 1
- - - - - ...See Below...
- - - - - - - - - - - - - - - - - - - - - - - - - ...See Below...

0
-

0
0
0
0
0
1
1

Command Block Input Registers
Register
7
Data
Error
Sector Count
LBA Low
1
LBA Mid
LBA High
Device
Status

6 5 4 3 2 1
- - - - - ...See Below...
- - - - - 1 0 0 0 1 0
- - - - - - - - - - - - - - - ...See Below...

0
-

7
6
BSY RDY
0

0
-

Status Register
5
4
3
2
1
0
DF DSC DRQ COR IDX ERR
0

The Idle Immediate command causes the device to enter performance Idle mode.
The device is spun up to operating speed. If the device is already spinning, the spin up sequence is
not executed.
During Idle mode the device is spinning and ready to respond to host commands immediately.
The Idle Immediate command will not affect the auto power down timeout parameter.
Unload Feature:
The UNLOAD FEATURE of the IDLE IMMEDIATE command allows the host to immediately unload the heads.
The device stops read look-ahead if it is in process. If the device is performing a write operation, the device
suspends writing cached data onto the media as soon as possible. The data in the write cache is retained, and the
device resumes writing the cached data onto the media after receiving a Software Reset, a Hardware Reset, or any
new command except IDLE IMMEDIATE with UNLOAD FEATURE.

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7K200 SATA OEM Specification

14.11

Initialize Device Parameters (91h)

Command Block Output Registers
Register
7 6
Data
- Feature
- Sector Count
V V
LBA Low
- LBA Mid
- LBA High
- Device
- Command
1 0

7
6
CRC UNC

5
0

5
V
0

4
V
1

3
V
H
0

2
V
H
0

Error Register
4
3
2
1
IDN
0
ABT T0N

1
V
H
0

0
V
H
1

0
AM
N
0
0
0
0
0
V
0
0
Table 66 Initialize Device Parameters Command (91h)

Command Block Input Registers
Register
7
Data
Error
Sector Count
LBA Low
LBA Mid
LBA High
Device
Status

7
6
BSY RDY
0

5
DF
0

6 5 4 3 2 1
- - - - - ...See Below...
- - - - - - - - - - - - - - - - - - - - - - - - - ...See Below...

0
-

Status Register
4
3
2
1
0
DSC DRQ COR IDX ERR
-

The Initialize Device Parameters command enables the host to set the number of sectors per track
and the number of heads minus 1, per cylinder. Words 54-58 in Identify Device Information reflects
these parameters.
The parameters remain in effect until the following events:
Another Initialize Device Parameters command is received.
The device is powered off.
Soft reset occurs and the Set Feature option of CCh is set
Output Parameters To The Device
The number of sectors per track. 0 does not mean there are 256 sectors per track, but there is no
Sector Count
sector per track.
The number of heads minus 1 per cylinder. The minimum is 0 and the maximum is 15.
H

101/173

7K200 SATA OEM Specification

14.12

Read Buffer (E4h)

Command Block Output Registers
Register
7 6
Data
- Feature
- Sector Count
- LBA Low
- LBA Mid
- LBA High
- Device
- Command
1 1

7
6
CRC UNC

5
0

5
1

4
0

3
0

Error Register
4
3
2
1
IDN
0
ABT T0N

0
0
0
0
0
V
Table 67 Read Buffer Command (E4h)

2
1

1
0

0
0

0
AM
N
0

Command Block Input Registers
Register
7
Data
Error
Sector Count
LBA Low
LBA Mid
LBA High
Device
Status

7
6
BSY RDY
0

6 5 4 3 2 1
- - - - - ...See Below...
- - - - - - - - - - - - - - - - - - - - - - - - - ...See Below...

0
-

Status Register
5
4
3
2
1
0
DF DSC DRQ COR IDX ERR
0

The Read Buffer command transfers a sector of data from the sector buffer of device to the host.
The sector is transferred through the Data Register 16 bits at a time.
The sector transferred will be from the same part of the buffer written to by the last Write Buffer
command. The contents of the sector may be different if any reads or writes have occurred since the
Write Buffer command was issued.

102/173

7K200 SATA OEM Specification

14.13

Read DMA(C8h/C9h)

Command Block Output Registers
Register
7 6
Data
- Feature
- Sector Count
V V
LBA Low
V V
LBA Mid
V V
LBA High
V V
Device
- L
Command
1 1

7
6
CRC UNC

5
0

5
V
V
V
V
0

4
V
V
V
V
0

3
V
V
V
V
H
1

2
V
V
V
V
H
0

Error Register
4
3
2
1
IDN
0
ABT T0N

V
V
0
V
0
V
0
Table 68 Read DMA Command (C8h/C9h)

1
V
V
V
V
H
0

0
V
V
V
V
H
R

0
AM
N
0

Command Block Input Registers
Register
7
Data
Error
Sector Count
V
LBA Low
V
LBA Mid
V
LBA High
V
Device
Status

7
6
BSY RDY
0

5
DF

6 5 4 3 2 1
- - - - - ...See Below...
V V V V V V
V V V V V V
V V V V V V
V V V V V V
- - - H H H
...See Below...

0
V
V
V
V
H

Status Register
4
3
2
1
0
DSC DRQ COR IDX ERR

The Read DMA command reads one or more sectors of data from disk media, then transfers the data
from the device to the host.
The sectors are transferred through the Data Register 16 bits at a time.
The host initializes a slave-DMA channel prior to issuing the command. The data transfers are
qualified by DMARQ and are performed by the slave-DMA channel. The device issues only one
interrupt per command to indicate that data transfer has terminated and status is available.
If an uncorrectable error occurs, the read will be terminated at the failing sector.
Output Parameters To The Device
The number of continuous sectors to be transferred. If zero is specified, then 256 sectors
Sector Count
will be transferred.
The sector number of the first sector to be transferred. (L=0)
LBA Low
In LBA mode, this register specifies LBA address bits 0 - 7 to be transferred. (L=1)
The cylinder number of the first sector to be transferred. (L=0)
LBA High/Mid
In LBA mode, this register specifies LBA address bits 8 - 15 (Mid) 16 - 23 (High) to be
transferred. (L=1)
The head number of the first sector to be transferred. (L=0)
H
In LBA mode, this register specifies LBA bits 24-27 to be transferred. (L=1)
The retry bit, but this bit is ignored.
R
Input Parameters From The Device
The number of requested sectors not transferred. This will be zero, unless an
Sector Count
unrecoverable error occurs.
The sector number of the last transferred sector. (L=0)
LBA Low
In LBA mode, this register contains current LBA bits 0 - 7. (L=1)
The cylinder number of the last transferred sector. (L=0)
LBA High/Mid
In LBA mode, this register contains current LBA bits 8 - 15 (Mid), 16 - 23 (High).
(L=1)
The
head number of the sector to be transferred. (L=0)
H
In LBA mode, this register contains current LBA bits 24 - 27. (L=1)

103/173

7K200 SATA OEM Specification

14.14

Read DMA Ext (25h)

Command Block Output Registers
Register
7 6
Data Low
- Data High
- Feature
Current
- Previous
- Sector Count Current
V V
Previous
V V
LBA Low
Current
V V
Previous
V V
LBA Mid
Current
V V
Previous
V V
LBA High
Current
V V
Previous
V V
Device
- 1
Command
0 0

5
V
V
V
V
V
V
V
V
1

4
V
V
V
V
V
V
V
V
0

3
V
V
V
V
V
V
V
V
0

2
V
V
V
V
V
V
V
V
1

1
V
V
V
V
V
V
V
V
0

Error Register
7
6
5
4
3
2
1
0
CRC UNC 0 IDN 0 ABT T0N AMN
V
V
0
V
0
V
0
0
Table 69 Read DMA Ext Command (25h)

0
V
V
V
V
V
V
V
V
1

Command Block Input Registers
Register
7 6 5 4 3 2 1 0
Data Low
- - - - - - - Data High
- - - - - - - Error
...See Below...
Sector Count
LBA Low
LBA Mid
LBA High

HOB=0
HOB=1
HOB=0
HOB=1
HOB=0
HOB=1
HOB=0
HOB=1

Device
Status

V
V
V
V
V
V
-

- - - - - - V V V V
V V V V
V V V V
V V V V
V V V V
V V V V
- - - ...See Below...

Status Register
7
6
5
4
3
2
BSY RDY DF DSC DRQ COR
0
V
0
V
0

1
IDX
0

V
V
V
V
V
V
-

0
ERR
V

The Read DMA Ext command reads one or more sectors of data from disk media, then transfers the
data from the device to the host.
The sectors are transferred through the Data Register 16 bits at a time.
The host initializes a slave-DMA channel prior to issuing the command. The data transfers are
qualified by DMARQ and are performed by the slave-DMA channel. The device issues only one
interrupt per command to indicate that data transfer has terminated and status is available.
If an uncorrectable error occurs, the read will be terminated at the failing sector.
Output Parameters To The Device
The number of sectors to be transferred low order, bits (7:0).
Sector Count Current
The number of sectors to be transferred high order, bits (15:8). If 0000h in the Sector
Sector Count Previous
Count register is specified, then 65,536 sectors will be transferred.
LBA (7:0)
LBA Low Current
LBA (31:24)
LBA Low Previous
LBA (15:8)
LBA Mid Current
LBA (39:32)
LBA Mid Previous
LBA (23:16)
LBA High Current
LBA (47:40)
LBA High Previous
Input Parameters From The Device
LBA (7:0) of the address of the first unrecoverable error.
LBA Low (HOB=0)
LBA (31:24)of the address of the first unrecoverable error.
LBA Low (HOB=1)
LBA (15:8)of the address of the first unrecoverable error.
LBA Mid (HOB=0)
LBA (39:32)of the address of the first unrecoverable error.
LBA Mid (HOB=1)
LBA (23:16)of the address of the first unrecoverable error.
LBA High (HOB=0)
LBA (47:40)of the address of the first unrecoverable error.
LBA High (HOB=1)

104/173

7K200 SATA OEM Specification

14.15

Read FPDMA Queued (60h)

Command Block Output Registers
Register
7 6
Data Low
- Data High
- Feature
Current
V V
Previous
V V
Sector Count Current
T T
Previous
P LBA Low
Current
V V
Previous
V V
LBA Mid
Current
V V
Previous
V V
LBA High
Current
V V
Previous
V V
Device
F 1
Command
0 1

5
V
V
T
V
V
V
V
V
V
1

4
V
V
T
V
V
V
V
V
V
0

3
V
V
T
V
V
V
V
V
V
0

2
V
V
V
V
V
V
V
V
0

1
V
V
V
V
V
V
V
V
0

Error Register
7
6
5
4
3
2
1
0
CRC UNC 0 IDN 0 ABT T0N AMN
V
V
0
V
0
V
0
0
Table 70 Read FPDMA Queued Command (60h)

0
V
V
V
V
V
V
V
V
0

Command Block Input Registers
Register
7 6 5 4 3 2 1 0
Data Low
- - - - - - - Data High
- - - - - - - Error
...See Below...
Sector Count
LBA Low
LBA Mid
LBA High
Device
Status

HOB=0
HOB=1
HOB=0
HOB=1
HOB=0
HOB=1
HOB=0
HOB=1

V
V
V
V
V
V
-

- - - - - - V V V V
V V V V
V V V V
V V V V
V V V V
V V V V
- - - ...See Below...

Status Register
7
6
5
4
3
2
BSY RDY DF DSC DRQ COR
0
V
0
V
0

1
IDX
0

V
V
V
V
V
V
-

0
ERR
V

The Read FPDMA Queued command reads one or more sectors of data from disk media, then
transfers the data from the device to the host.
If an uncorrectable error occurs, the read will be terminated at the failing sector.
Output Parameters To The Device
The number of sectors to be transferred low order, bits (7:0)
Feature Current
The number of sectors to be transferred high order, bits (15:8)
Feature Previous
TAG value. It shall be assigned to be different from all other queued commands.
T
The value shall not exceed the maximum queue depth specified by the Word 75 of the
Identify Device information.
LBA (7:0)
LBA Low Current
LBA (31:24)
LBA Low Previous
LBA
(15:8)
LBA Mid Current
LBA
(39:32)
LBA Mid Previous
LBA
(23:16)
LBA High Current
LBA
(47:40)
LBA High Previous
FUA bit. When the FUA bit is set to 1, the requested data is always retrieved from
F
the media regardless of whether the data are held in the sector buffer or not. When
the FUA bit is set to 0, the data may be retrieved from the media or from the cached
data left by previously processed Read or Write commands.
Priority bit. When the Priority bit is set to 1, the device attempts to provide better
P
quality of service for the command than normal priority commands.
Input Parameters From The Device
LBA (7:0) of the address of the first unrecoverable error.
LBA Low (HOB=0)
LBA (31:24)of the address of the first unrecoverable error.
LBA Low (HOB=1)
LBA (15:8)of the address of the first unrecoverable error.
LBA Mid (HOB=0)
LBA (39:32)of the address of the first unrecoverable error.
LBA Mid (HOB=1)
LBA (23:16)of the address of the first unrecoverable error.
LBA High (HOB=0)
LBA (47:40)of the address of the first unrecoverable error.
LBA High (HOB=1)
105/173

7K200 SATA OEM Specification

14.16

Read Log Ext(2Fh)

Command Block Output Registers
Register
7 6
Data Low
- Data High
- Feature
Current
- Previous
- Sector Count Current
V V
Previous
V V
LBA Low
Current
V V
Previous
- LBA Mid
Current
V V
Previous
V V
LBA High
Current
- Previous
- Device
- Command
0 0

5
V
V
V
V
V
1

4
V
V
V
V
V
0

3
V
V
V
V
V
1

2
V
V
V
V
V
1

1
V
V
V
V
V
1

Error Register
7
6
5
4
3
2
1
0
CRC UNC 0 IDN 0 ABT T0N AMN
V
V
0
V
0
V
0
0
Table 71 Read Log Ext Command (2Fh)

0
RV
V
V
V
V
1

Command Block Input Registers
Register
7 6 5 4 3 2 1 0
Data Low
- - - - - - - Data High
- - - - - - - Error
...See Below...
Sector Count
LBA Low
LBA Mid
LBA High
Device
Status

HOB=0
HOB=1
HOB=0
HOB=1
HOB=0
HOB=1
HOB=0
HOB=1

- - - - - - - - - - - - - - - - - - - - - - - - - - - ...See Below...

Status Register
7
6
5
4
3
2
BSY RDY DF DSC DRQ COR
0
V
0
V
0

1
IDX
0

0
ERR
V

This command returns the specified log to the host. The device shall interrupt for each DRQ block
transferred.
Output Parameters To The Device
Phy Event Counter Reset bit. When Log address is 11h (Phy Event Counter) and this
R
bit is set to 1, all Phy Event Counter values are reset to 0 after sending the current
counter valules.
The number of sectors to be read from the specified log low order, bits (7:0). The log
Sector Count Current
transferred by the drive shall start at the sector in the specified log at the specified
offset, regardless of the sector count requested.
The number of sectors to be read from the specified log high orders, bits (15:8).
Sector Count Previous
The log to be returned as described in the following table.
LBA Low Current
The first sector of the log to be read low order, bits (7:0).
LBA Mid Current
The first sector of the log to be read high order, bits (15:8).
LBA Mid Previous

Log
address
00h
03h
07h
10h
11h
80h-9Fh

Content

Feature set

Type

Log directory
Extended
Comprehensive
SMART
error log
Extended SMART self-test log
Command Error

N/A
SMART
error
logging
SMART self-test
Native
Command
Queuing
Phy Event Counter
SMART

Read Only
Read Only

Phy Event Counter
Host vendor specific

Table 72 Log address definition

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Read Only
Read Only
Read Only
Read/Wri
te

7K200 SATA OEM Specification
The Extended SMART self-test log sector shall support 48-bit and 28-bit addressing. All 28-bit
entries contained in the SMART self-test log sector shall also be included in the Comprehensive
SMART self-test log sector with the 48-bit entries.
If the feature set associated with the log specified in the Sector Number register is not supported or
enabled, or if the values in the Sector Count, Sector Number or Cylinder Low registers are invalid,
the device shall return command aborted.

14.16.1 General purpose Log Directory
The following table defines the 512 bytes that make up the General Purpose Log Directory.

Description
General Purpose Logging Version
Number of sectors in the log at log address 01h (7:0)
Number of sectors in the log at log address 01h (15:8)
Number of sectors in the log at log address 02h (7:0)
Number of sectors in the log at log address 02h (15:8)
...
Number of sectors in the log at log address 80h (7:0)
Number of sectors in the log at log address 80h (15:8)
...
Number of sectors in the log at log address FFh (7:0)
Number of sectors in the log at log address FFh (15:8)

Bytes
2
1
1
1
1

Offset
00h
02h
03h
04h
05h

1
1

100h
101h

1
1
512

1FEh
1FFh

Table 73 General purpose Log Directory
The value of the General Purpose Logging Version word shall be 0001h. A value of 0000h indicates
that there is no General Purpose Log Directory.
The logs at log addresses 80-9Fh shall each be defined as 16 sectors long.

14.16.2 Extended comprehensive SMART error log
The following table defines the format of each of the sectors that comprise the Extended
Comprehensive SMART error log. Error log data structure shall not include errors attributed to the
receipt of faulty commands such as command codes not implemented by the device or requests with
invalid parameters or in valid addresses.

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7K200 SATA OEM Specification

Description
SMART error log version
Reserved
Error log index (7:0)
Error log index (15:8)
1st error log data structure
2nd error log data structure
3rd error log data structure
4th error log data structure
Device error count
Reserved
Data structure checksum

Bytes
1
1
1
1
124
124
124
124
2
9
1
512

Offset
00h
01h
02h
03h
04h
80h
FCh
178h
1F4h
1F6h
1FFh

Table 74 Extended comprehensive SMART error Log

14.16.2.1

Error Log version

The value of this version shall be 01h.

14.16.2.2

Error log index

This indicates the error log data structure representing the most recent error. If there have been no
error log entries, it is cleared to 0. Valid values for the error log index are 0 to 4.

14.16.2.3

Extended Error log data structure

An error log data structure shall be presented for each of the last four errors reported by the device.
These error log data structure entries are viewed as a circular buffer. The fifth error shall create an
error log structure that replaces the first error log data structure. The next error after that shall
create an error log data structure that replaces the second error log structure, etc.
Unused error log data structures shall be filled with zeros.
Data format of each error log structure is shown below.

Description
1st command data structure
2nd command data structure
3rd command data structure
4th command data structure
5th command data structure
Error data structure

Bytes
18
18
18
18
18
34
124

Table 75 Extended Error log data structure

108/173

Offset
00h
12h
24h
36h
48h
5Ah

7K200 SATA OEM Specification

Command data structure: Data format of each command data structure is shown below.
Description
Device Control register
Features register (7:0) (see Note)
Features register (15:8)
Sector count register (7:0)
Sector count register (15:8)
Sector number register (7:0)
Sector number register (15:8)
Cylinder Low register (7:0)
Cylinder Low register (15:8)
Cylinder High register (7:0)
Cylinder High register (15:8)
Device register
Command register
Reserved
Timestamp (milliseconds from Power-on)

Bytes
1
1
1
1
1
1
1
1
1
1
1
1
1
1
4
18

Offset
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh

Note: bits (7:0) refer to the most recently written contents of the register. Bits (15:8) refer to the
contents of the register prior to the most recent write to the register.

Table 76 Command data structure

Error data structure: Data format of error data structure is shown below.
Description
Reserved
Error register
Sector count register (7:0) (see Note)
Sector count register (15:8) (see Note)
Sector number register (7:0)
Sector number register (15:8)
Cylinder Low register (7:0)
Cylinder Low register (15:8)
Cylinder High register (7:0)
Cylinder High register (15:8)
Device register
Status register
Extended error data (vendor specific)
State
Life timestamp (hours)

Bytes
1
1
1
1
1
1
1
1
1
1
1
1
19
1
2
34

Offset
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
1Fh
20h

Note: bits (7:0) refer to the contents if the register is read with bit 7 of the Device Control register
cleared to zero. Bits (15:8) refer to the contents if the register is read with bit 7 of the Device Control
register set to one.

Table 77 Error data structure

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7K200 SATA OEM Specification
State shall contain a value indicating the state of the device when the command was issued to the
device or the reset occurred as described below.

Value
x0h
x1h
x2h
x3h
x4h
x5h-xAh
xBh-xFh

State
Unknown
Sleep
Standby
Active/Idle
SMART Off-line or Self-test
Reserved
Vendor specific

Note: The value of x is vendor specific.

14.16.2.4

Device error count

This field shall contain the total number of errors attributable to the device that have been reported
by the device during the life of the device. This count shall not include errors attributed to the
receipt of faulty commands such as commands codes not implemented by the device or requests with
invalid parameters or invalid addresses. If the maximum value for this field is reached the count
shall remain at the maximum value when additional errors are encountered and logged.

14.16.3 Extended Self-test log sector
The following table defines the format of each of the sectors that comprise the Extended SMART
self-test log.
The Extended SMART self-test log sector shall support 48-bit and 28-bit addressing. All 28-bit
entries contained in the SMART self-test log, defined in “Self-test log data structure” shall also be
included in the Extended SMART self-test log with all 48-bit entries.

Description
Self-test log data structure revision number
Reserved
Self-test descriptor index (7:0)
Self-test descriptor index (15:8)
Descriptor entry 1
Descriptor entry 2
...
Descriptor entry 18
Vendor specific
Reserved
Data structure checksum

Bytes
1
1
1
1
26
26

Offset

26
2
11
1
512

00h
01h
02h
03h
04h
1Eh
1D8h
1F2h
1F4h
1FFh

Table 78 Extended Self-test log data structure
These descriptor entries are viewed as a circular buffer. The nineteenth self-test shall create a
descriptor entry that replaces descriptor entry 1. The next self-test after that shall create a
descriptor entry that replaces descriptor entry 2, etc. All unused self-test descriptors shall be filled
with zeros

14.16.3.1

Self-test log data structure revision number

The value of this revision number shall be 01h.

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7K200 SATA OEM Specification

14.16.3.2

Self-test descriptor index

This indicates the most recent self-test descriptor. If there have been no self-tests, this is set to zero.
Valid values for the Self-test descriptor index are 0 to 18.

14.16.3.3

Extended Self-test log descriptor entry

The content of the self-test descriptor entry is shown below.

Description
Self-test number
Self-test execution status
Power-on life timestamp in hours
Self-test failure check point
Failing LBA (7:0)
Failing LBA (15:8)
Failing LBA (23:16)
Failing LBA (31:24)
Failing LBA (39:32)
Failing LBA (47:40)
Vendor specific

Bytes
1
1
2
1
1
1
1
1
1
1
15
26

Offset
00h
01h
02h
04h
05h
06h
07h
08h
09h
0Ah
0Bh

Table 79 Extended Self-test log descriptor entry

14.16.4 Command Error
The following table defines the format of the Command Error data structure.

Byte
7
6
0
NQ
UNL
1
2
3
4
5
6
7
8
9
10
11
12
13
14 – 255
256 – 510
511
Table 80 Command Error information

5
Rsv

2
TAG

Reserved
Status
Error
LBA Low
LBA Mid
LBA High
Device
LBA Low Previous
LBA Mid Previous
LBA High Previous
Reserved
Sector Count
Sector Count Previous
Reserved
Vendor Unique
Data Structure Checksum

The TAG field (Byte 0 bits 4-0) contains the tag number corresponding to a queued command, if the
NQ bit is cleared.
The UNL field (Byte 0 bit 6) indicates whether the error condition was a result of receiving an IDLE
IMMEDIATE command with the Unload Feature. If cleared to zero, the reason for the error was
not due to reception of an IDLE IMMEDIATE command with Unload Feature.
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7K200 SATA OEM Specification
If set to one, LBA Low is set to C4h if the unload is being executed or has completed successfully. It
is set to 4Ch if the unload was not accepted or has failed.
The NQ field (Byte 0 bit 7) indicates whether the error condition was a result of a non-queued or not.
If it is cleared, the error information corresponds to a queued command specified by the tag number
indicated in the TAG field.
The bytes 1 to 13 correspond to the contents of Shadow Register Block when the error was reported.
The Data Structure Checksum (Byte 511) contains the 2’s complement of the sum of the first 511
bytes in the data structure. The sum of all 512 bytes of the data structure will be zero when the
checksum is correct.

14.16.5 Phy Event Counter
Phy Event Counters are a feature to obtain more information about Phy level events that occur on
the interface. The counter values are not retained across power cycles. The counter values are
preserved across COMRESET and software resets.

14.16.5.1

Counter Reset Mechanisms

There are 2 mechanisms by which the host can explicitly cause the Phy counters to be reset. The
first mechanism is to issue a BIST Activate FIS to the drive. The second mechanism uses the Read
Log Ext command. When the drive receives a Read Log Ext command for log page 11h and bit 0 in
Feature register is set to one, the drive returns the current counter values for the command and then
resets all Phy event counter values.

14.16.5.2

Counter Identifiers

Each counter begins with a 16-bit identifier. The following table defines the counter value for each
identifier.
For all counter descriptions, “transmitted” refers to items sent by the drive to the host and “received”
refers to items received by the drive from the host.
Bits 14:12 of the counter identifier convey the number of significant bits that counter uses. All
counter values consumes a multiple of 16-bits. The valid values for bit 14:12 and the corresponding
counter size are:
1h

16-bit counter

32-bit counter

48-bit counter

64-bit counter

Description
Identifier
(Bits 11:0)
000h
No counter value; marks end of counters in the page
001h
Command failed due to ICRC error
009h
Transfer from drive PhyRdy to drive PhyNRdy
00Ah
Signature D2H register FISes sent due to a COMRESET
00Bh
CRC errors within the FIS (received)
00Dh
Non-CRC errors within the FIS (received)
Table 81 Phy Event Counter Identifier

14.16.5.3

Read Log Ext Log Page 11h

The following table defines the format of the Phy Event counter data structure.

112/173

7K200 SATA OEM Specification

Byte
7
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26 - 510
511
Table 82 Phy Event Counter information

00h
00h
00h
00h
Counter 0001h Identifier
Counter 0001h Value
Counter 0009h Identifier
Counter 0009 Value
Counter 000Ah Identifier
Counter 000Ah Value
Counter 000Bh Identifier
Counter 000Bh Value
Counter 000Dh Identifier
Counter 000Dh Value
00h
00h
Reserved ( 00h )
Data Structure Checksum

The Data Structure Checksum (Byte 511) contains the 2’s complement of the sum of the first 511
bytes in the data structure. The sum of all 512 bytes of the data structure will be zero when the
checksum is correct.

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7K200 SATA OEM Specification

14.17

Read Multiple (C4h)

Command Block Output Registers
Register
7 6
Data
- Feature
- Sector Count
V V
LBA Low
V V
LBA Mid
V V
LBA High
V V
Device
- L
Command
1 1

7
6
CRC UNC

5
0

5
V
V
V
V
0

4
V
V
V
V
0

3
V
V
V
V
H
0

2
V
V
V
V
H
1

Error Register
4
3
2
1
IDN
0
ABT T0N

0
V
0
V
0
V
0
Table 83 Read Multiple Command (C4h)

1
V
V
V
V
H
0

0
V
V
V
V
H
0

0
AM
N
0

Command Block Input Registers
Register
7
Data
Error
Sector Count
V
LBA Low
V
LBA Mid
V
LBA High
V
Device
Status

7
6
BSY RDY
0

5
DF
0

6 5 4 3 2 1
- - - - - ...See Below...
V V V V V V
V V V V V V
V V V V V V
V V V V V V
- - - H H H
...See Below...

0
V
V
V
V
H

Status Register
4
3
2
1
0
DSC DRQ COR IDX ERR
V

The Read Multiple command reads one or more sectors of data from disk media, then transfers the
data from the device to the host.
The sectors are transferred through the Data Register 16 bits at a time. Command execution is
identical to the Read Sectors command except that an interrupt is generated for each block (as
defined by the Set Multiple command) instead of for each sector.
Output Parameters To The Device
The number of continuous sectors to be transferred. If zero is specified, then 256 sectors
Sector Count
will be transferred.
The sector number of the first sector to be transferred. (L=0)
LBA Low
In LBA mode, this register contains LBA bits 0 - 7. (L=1)
The cylinder number of the first sector to be transferred. (L=0)
LBA High/Mid
In LBA mode, this register contains LBA bits 8 - 15 (Mid), 16 - 23 (High). (L=1)
The
head number of the first sector to be transferred. (L=0)
H
In LBA mode, this register contains LBA bits 24 - 27. (L=1)
Input Parameters From The Device
The number of requested sectors not transferred. This will be zero, unless an
Sector Count
unrecoverable error occurs.
The sector number of the last transferred sector. (L=0)
LBA Low
In LBA mode, this register contains current LBA bits 0 - 7. (L=1)
The cylinder number of the last transferred sector. (L=0)
LBA High/Mid
In LBA mode, this register contains current LBA bits 8-15 (Mid), 16-23 (High). (L=1)
The head number of the last transferred sector. (L=0)
H
LBA mode, this register contains current LBA bits 24 - 27. (L=1)

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7K200 SATA OEM Specification

14.18

Read Multiple Ext (29h)

5
V
V
V
V
V
V
V
V
1

4
V
V
V
V
V
V
V
V
0

3
V
V
V
V
V
V
V
V
1

2
V
V
V
V
V
V
V
V
0

1
V
V
V
V
V
V
V
V
0

Error Register
7
6
5
4
3
2
1
0
CRC UNC 0 IDN 0 ABT T0N AMN
0
V
0
V
0
V
0
0
Table 84 Read Multiple Ext Command (29h)

0
V
V
V
V
V
V
V
V
1

Command Block Input Registers
Register
7 6 5 4 3 2 1 0
Data Low
- - - - - - - Data High
- - - - - - - Error
...See Below...
Sector Count
LBA Low
LBA Mid
LBA High
Device
Status

HOB=0
HOB=1
HOB=0
HOB=1
HOB=0
HOB=1
HOB=0
HOB=1

V
V
V
V
V
V
-

- - - - - - V V V V
V V V V
V V V V
V V V V
V V V V
V V V V
- - - ...See Below...

Status Register
7
6
5
4
3
2
BSY RDY DF DSC DRQ COR
0
V
0
V
0

1
IDX
0

V
V
V
V
V
V
-

0
ERR
V

Output Parameters To The Device
The number of sectors to be transferred low order, bits (7:0).
Sector Count Current
The number of sectors to be transferred high order, bits (15:8). If 0000h in the Sector
Sector Count Previous
Count register is specified, then 65,536 sectors will be transferred.
LBA (7:0)
LBA Low Current
LBA (31:24)
LBA Low Previous
LBA (15:8)
LBA Mid Current
LBA (39:32)
LBA Mid Previous
LBA (23:16)
LBA High Current
LBA (47:40)
LBA High Previous
Input Parameters From The Device
LBA (7:0) of the address of the first unrecoverable error.
LBA Low (HOB=0)
LBA (31:24)of the address of the first unrecoverable error.
LBA Low (HOB=1)
LBA (15:8)of the address of the first unrecoverable error.
LBA Mid (HOB=0)
LBA (39:32)of the address of the first unrecoverable error.
LBA Mid (HOB=1)
LBA (23:16)of the address of the first unrecoverable error.
LBA High (HOB=0)
LBA (47:40)of the address of the first unrecoverable error.
LBA High (HOB=1)

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7K200 SATA OEM Specification

14.19

Read Native Max Address (F8h)

Block Output Registers Command
Register
7 6
Data
- Feature
- Sector Count
- LBA Low
- LBA Mid
- LBA High
- Device
- L
Command
1 1

7
6
CRC UNC

5
0

5
1

4
1

3
1

Error Register
4
3
2
1
IDN
0
ABT T0N

2
0

1
0

0
0

0
AM
N
0
0
0
0
0
V
0
0
Table 85 Read Native Max Address Command (F8h)

Command Block Input Registers
Register
7
Data
Error
Sector Count
LBA Low
V
LBA Mid
V
LBA High
V
Device
Status

7
6
BSY RDY
0

6 5 4 3 2 1
- - - - - ...See Below...
- - - - - V V V V V V
V V V V V V
V V V V V V
- - - H H H
...See Below...

0
V
V
V
H

Status Register
5
4
3
2
1
0
DF DSC DRQ COR IDX ERR
0

This command returns the native max LBA/CYL of HDD which is not affected by Set Max Address
command.
The 48-bit native max address is greater than 268,435,455, the Read Native Max Address command
return a value of 268,435,455.
Output Parameters To The Device
LBA mode.Indicates the addressing mode.L=0 specifies CHS mode and L=1 does LBA
L
addressing mode.
The device number bit. Indicates that the device number bit of the Device Register
D
should be specified. D=0 selects the master device and D=1 selects the slave device.
Indicates that the bit is not used.
Input Parameters From The Device
In LBA mode, this register contains native max LBA bits 0 - 7. (L=1)
LBA Low
In CHS mode, this register contains native max LBA Low. (L=0)
In LBA mode, this register contains native max LBA bits 8 - 15 (Mid), 16 - 23 (High).
LBA High/Mid
(L=1)
In CHS mode, this register contains native max cylinder number. (L=0)
In LBA mode, this register contains native max LBA bits 24 - 27. (L=1)
H
In CHS mode, this register contains native max head number.(L=0)
Valid. Indicates that the bit is part of an input parameter and will be set to 0 or 1 by the
V
device.
Indicates that the bit is not used.
-

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7K200 SATA OEM Specification

14.20

Read Native Max Address Ext (27h)

Command Block Output Registers
Register
7 6 5 4 3 2 1 0
Data Low
- - - - - - - Data High
- - - - - - - Feature
Current
- - - - - - - Previous
- - - - - - - Sector Count Current
- - - - - - - Previous
- - - - - - - LBA Low
Current
- - - - - - - Previous
- - - - - - - LBA Mid
Current
- - - - - - - Previous
- - - - - - - LBA High
Current
- - - - - - - Previous
- - - - - - - Device
- 1 - - - - - Command
0 0 1 0 0 1 1 1

Command Block Input Registers
Register
7 6 5 4 3 2 1 0
Data Low
- - - - - - - Data High
- - - - - - - Error
...See Below...
Sector Count
LBA Low
LBA Mid
LBA High
Device
Status

HOB=0
HOB=1
HOB=0
HOB=1
HOB=0
HOB=1
HOB=0
HOB=1

V
V
V
V
V
V
-

- - - - - - V V V V
V V V V
V V V V
V V V V
V V V V
V V V V
- - - ...See Below...

Error Register
Status Register
7
6
5
4
3
2
1
0
7
6
5
4
3
2
CRC UNC 0 IDN 0 ABT T0N AMN
BSY RDY DF DSC DRQ COR
0
0
0
0
0
V
0
0
0
V
0
0
Table 86 Read Native Max Address Ext Command (29h)

1
IDX
0

V
V
V
V
V
V
-

0
ERR
V

This command returns the native max LBA of HDD which is not effected by Set Max Address Ext
command.
Input Parameters From The Device
LBA (7:0) of the address of the Native max address.
LBA Low (HOB=0)
LBA (31:24)of the address of the Native max address.
LBA Low (HOB=1)
LBA (15:8)of the address of the Native max address.
LBA Mid (HOB=0)
LBA (39:32)of the address of the Native max address.
LBA Mid (HOB=1)
LBA (23:16)of the address of the first Native max address.
LBA High (HOB=0)
LBA (47:40)of the address of the first Native max address.
LBA High (HOB=1)

117/173

7K200 SATA OEM Specification

14.21

Read Sector(s) (20h/21h)

Command Block Output Registers
Register
7 6
Data
- Feature
- Sector Count
V V
LBA Low
V V
LBA Mid
V V
LBA High
V V
Device
- L
Command
0 0

7
6
CRC UNC

5
0

5
V
V
V
V
1

4
V
V
V
V
0

3
V
V
V
V
H
0

2
V
V
V
V
H
0

Error Register
4
3
2
1
IDN
0
ABT T0N

0
V
0
V
0
V
0
Table 87 Read Sector(s) Command (20h/21h)

1
V
V
V
V
H
0

0
V
V
V
V
H
R

0
AM
N
0

Command Block Input Registers
Register
7
Data
Error
Sector Count
V
LBA Low
V
LBA Mid
V
LBA High
V
Device
Status

7
6
BSY RDY
0

6 5 4 3 2 1
- - - - - ...See Below...
V V V V V V
V V V V V V
V V V V V V
V V V V V V
- - - H H H
...See Below...

0
V
V
V
V
H

Status Register
5
4
3
2
1
0
DF DSC DRQ COR IDX ERR
0

The Read Sector(s) command reads one or more sectors of data from disk media, then transfers the
data from the device to the host.
The sectors are transferred through the Data Register 16 bits at a time.
If an uncorrectable error occurs, the read will be terminated at the failing sector.
Output Parameters To The Device
The number of continuous sectors to be transferred. If zero is specified, then 256 sectors
Sector Count
will be transferred.
The sector number of the first sector to be transferred. (L=0)
LBA Low
In LBA mode, this register contains LBA bits 0 - 7. (L=1)
The cylinder number of the first sector to be transferred. (L=0)
LBA High/Mid
In LBA mode, this register contains LBA bits 8 - 15 (Mid), 16 - 23 (High). (L=1)
The head number of the first sector to be transferred. (L=0)
H
In LBA mode, this register contains LBA bits 24 - 27. (L=1)
The retry bit, but this bit is ignored.
R
Input Parameters From The Device
The number of requested sectors not transferred. This will be zero, unless an
Sector Count
unrecoverable error occurs.
The sector number of the last transferred sector. (L=0)
LBA Low
In LBA mode, this register contains current LBA bits 0 - 7. (L=1)
The cylinder number of the last transferred sector. (L=0)
LBA High/Mid
In LBA mode, this register contains current LBA bits 8 - 15 (Mid), 16 - 23 (High).
(L=1)
The head number of the last transferred sector. (L=0)
H
In LBA mode, this register contains current LBA bits 24 - 27. （L=1）

118/173

7K200 SATA OEM Specification

14.22

Read Sector(s) Ext (24h)

5
V
V
V
V
V
V
V
V
1

4
V
V
V
V
V
V
V
V
0

3
V
V
V
V
V
V
V
V
0

2
V
V
V
V
V
V
V
V
1

1
V
V
V
V
V
V
V
V
0

Error Register
7
6
5
4
3
2
1
0
CRC UNC 0 IDN 0 ABT T0N AMN
0
V
0
V
0
V
0
0
Table 88 Read Sector(s) Ext Command (24h)

0
V
V
V
V
V
V
V
V
0

Command Block Input Registers
Register
7 6 5 4 3 2 1 0
Data Low
- - - - - - - Data High
- - - - - - - Error
...See Below...
Sector Count
LBA Low
LBA Mid
LBA High

HOB=0
HOB=1
HOB=0
HOB=1
HOB=0
HOB=1
HOB=0
HOB=1

Device
Status

V
V
V
V
V
V
-

- - - - - - V V V V
V V V V
V V V V
V V V V
V V V V
V V V V
- - - ...See Below...

Status Register
7
6
5
4
3
2
BSY RDY DF DSC DRQ COR
0
V
0
V
0

1
IDX
0

V
V
V
V
V
V
-

0
ERR
V

The Read Sector(s) Ext command reads from 1 to 65,536 sectors of data from disk media, then
transfers the data from the device to the host.
The sectors are transferred through the Data Register 16 bits at a time.
If an uncorrectable error occurs, the read will be terminated at the failing sector.
Output Parameters To The Device
The number of sectors to be transferred low order, bits (7:0).
Sector Count Current
The number of sectors to be transferred high order, bits (15:8). If 0000h in the Sector
Sector Count Previous
Count register is specified, then 65,536 sectors will be transferred.
LBA (7:0)
LBA Low Current
LBA (31:24)
LBA Low Previous
LBA
(15:8)
LBA Mid Current
LBA (39:32)
LBA Mid Previous
LBA (23:16)
LBA High Current
LBA (47:40)
LBA High Previous
Input Parameters From The Device
LBA (7:0) of the address of the first unrecoverable error.
LBA Low (HOB=0)
LBA (31:24)of the address of the first unrecoverable error.
LBA Low (HOB=1)
LBA (15:8)of the address of the first unrecoverable error.
LBA Mid (HOB=0)
LBA (39:32)of the address of the first unrecoverable error.
LBA Mid (HOB=1)
LBA (23:16)of the address of the first unrecoverable error.
LBA High (HOB=0)
LBA (47:40)of the address of the first unrecoverable error.
LBA High (HOB=1)

119/173

7K200 SATA OEM Specification

14.23

Read Verify Sector(s) (40h/41h)

Command Block Output Registers
Register
7 6
Data
- Feature
- Sector Count
V V
LBA Low
V V
LBA Mid
V V
LBA High
V V
Device
- L
Command
0 0

7
6
CRC UNC

5
0

5
V
V
V
V
1

4
V
V
V
V
0

3
V
V
V
V
H
0

2
V
V
V
V
H
0

Error Register
4
3
2
1
IDN
0
ABT T0N

1
V
V
V
V
H
0

0
V
V
V
V
H
R

0
AM
N
0
V
0
V
0
V
0
0
Table 89 Read Verify Sector(s) Command (40h/41h)

Command Block Input Registers
Register
7
Data
Error
Sector Count
V
LBA Low
V
LBA Mid
V
LBA High
V
Device
Status

7
6
BSY RDY
0

6 5 4 3 2 1
- - - - - ...See Below...
V V V V V V
V V V V V V
V V V V V V
V V V V V V
- - - H H H
...See Below...

0
V
V
V
V
H

Status Register
5
4
3
2
1
0
DF DSC DRQ COR IDX ERR
0

The Read Verify Sector(s) verifies one or more sectors on the device. No data is transferred to the
host.
The difference of Read Sector(s) command and Read Verify Sector(s) command is whether the data is
transferred to the host or not.
If an uncorrectable error occurs, the read verify will be terminated at the failing sector.
Output Parameters To The Device
The number of continuous sectors to be verified. If zero is specified, then 256 sectors
Sector Count
will be verified.
The sector number of the first sector to be transferred. (L=0)
LBA Low
In LBA mode, this register contains LBA bits 0 - 7. (L=1)
The cylinder number of the first sector to be transferred. (L=0)
LBA High/Mid
In LBA mode, this register contains LBA bits 8 - 15 (Mid), 16 - 23 (High). (L=1)
The head number of the first sector to be transferred. (L=0)
H
In LBA mode, this register contains LBA bits 24 - 27. (L=1)
The retry bit, but this bit is ignored.
R
Input Parameters From The Device
The number of requested sectors not verified. This will be zero, unless an unrecoverable
Sector Count
error occurs.
The sector number of the last transferred sector. (L=0)
LBA Low
In LBA mode, this register contains current LBA bits 0 - 7. (L=1)
The cylinder number of the last transferred sector. (L=0)
LBA High/Mid
In LBA mode, this register contains current LBA bits 8 - 15 (Mid), 16 - 23 (High).
(L=1)
The head number of the last transferred sector. (L=0)
H
In LBA mode, this register contains current LBA bits 24 - 27. (L=1)

120/173

7K200 SATA OEM Specification

14.24

Read Verify Sector(s) Ext (42h)

5
V
V
V
V
V
V
V
V
1

4
V
V
V
V
V
V
V
V
0

3
V
V
V
V
V
V
V
V
0

2
V
V
V
V
V
V
V
V
0

1
V
V
V
V
V
V
V
V
1

Error Register
7
6
5
4
3
2
1
0
CRC UNC 0 IDN 0 ABT T0N AMN
0
V
0
V
0
V
0
0
Table 90 Read Verify Sector(s) Ext Command (42h)

0
V
V
V
V
V
V
V
V
0

Command Block Input Registers
Register
7 6 5 4 3 2 1 0
Data Low
- - - - - - - Data High
- - - - - - - Error
...See Below...
Sector Count
LBA Low
LBA Mid
LBA High
Device
Status

HOB=0
HOB=1
HOB=0
HOB=1
HOB=0
HOB=1
HOB=0
HOB=1

V
V
V
V
V
V
-

- - - - - - V V V V
V V V V
V V V V
V V V V
V V V V
V V V V
- - - ...See Below...

Status Register
7
6
5
4
3
2
BSY RDY DF DSC DRQ COR
0
V
0
V
0

1
IDX
0

V
V
V
V
V
V
-

0
ERR
V

The Read Verify Sector(s) Ext verifies one or more sectors on the device. No data is transferred to the
host.
The difference between the Read Sector(s) Ext command and the Read Verify Sector(s) Ext command
is whether the data is transferred to the host or not.
If an uncorrectable error occurs, the Read Verify Sector(s) Ext will be terminated at the failing
sector.
Output Parameters To The Device
The number of sectors to be transferred low order, bits (7:0).
Sector Count Current
The number of sectors to be transferred high order, bits (15:8). If 0000h in the Sector
Sector Count Previous
Count register is specified, then 65,536 sectors will be verified.
LBA (7:0)
LBA Low Current
LBA (31:24)
LBA Low Previous
LBA (15:8)
LBA Mid Current
LBA (39:32)
LBA Mid Previous
LBA (23:16)
LBA High Current
LBA (47:40)
LBA High Previous
Input Parameters From The Device
LBA (7:0) of the address of the first unrecoverable error.
LBA Low (HOB=0)
LBA (31:24)of the address of the first unrecoverable error.
LBA Low (HOB=1)
LBA (15:8)of the address of the first unrecoverable error.
LBA Mid (HOB=0)
LBA (39:32)of the address of the first unrecoverable error.
LBA Mid (HOB=1)
LBA (23:16)of the address of the first unrecoverable error.
LBA High (HOB=0)
LBA (47:40)of the address of the first unrecoverable error.
LBA High (HOB=1)

121/173

7K200 SATA OEM Specification

14.25

Recalibrate (1xh)

Command Block Output Registers
Register
7 6
Data
- Feature
- Sector Count
- LBA Low
- LBA Mid
- LBA High
- Device
- Command
0 0

7
6
CRC UNC

5
0

4
1

3
-

Error Register
4
3
2
1
IDN
0
ABT T0N

0
0
0
0
0
V
Table 91 Recalibrate Command (1xh)

2
-

1
-

0
-

0
AM
N
0

Command Block Input Registers
Register
7
Data
Error
Sector Count
LBA Low
LBA Mid
LBA High
Device
Status

7
6
BSY RDY
0

6 5 4 3 2 1
- - - - - ...See Below...
- - - - - - - - - - - - - - - - - - - - - - - - - ...See Below...

Status Register
5
4
3
2
1
0
DF DSC DRQ COR IDX ERR
0

The Recalibrate command moves the read/write heads from anywhere on the disk to cylinder 0.
If the device cannot reach cylinder 0, T0N (Track 0 Not Found) will be set in the Error Register.

122/173

0
-

7K200 SATA OEM Specification

14.26

Security Disable Password (F6h)

Command Block Output Registers
Register
7 6
Data
- Feature
- Sector Count
- LBA Low
- LBA Mid
- LBA High
- Device
- Command
1 1

7
6
CRC UNC

5
0

5
1

4
1

3
0

Error Register
4
3
2
1
IDN
0
ABT T0N

2
1

1
1

0
0

0
AM
N
0
0
0
0
0
V
0
0
Table 92 Security Disable Password Command (F6h)

Command Block Input Registers
Register
7
Data
Error
Sector Count
LBA Low
LBA Mid
LBA High
Device
Status

7
6
BSY RDY
0

5
DF

6 5 4 3 2 1
- - - - - ...See Below...
- - - - - - - - - - - - - - - - - - - - - - - - - ...See Below...

0
-

Status Register
4
3
2
1
0
DSC DRQ COR IDX ERR

The Security Disable Password command disables the security mode feature ( device lock function).
The Security Disable Password command requests a transfer of a single sector of data from the host
including information specified in the following table. Then the device checks the transferred
password. If the User Password or Master Password matches the given password, the device disables
the security mode feature (device lock function). This command does not change the Master
Password which may be re-activated later by setting User Password. This command should be
executed in device unlock mode.
Word
00

Description
Control word
bit 0
: Identifier (1-Mater, 0-User)
bit 1-15
: Reserved
01-16
Password
(32 bytes)
17-255
Reserved
Table 93 Password Information for Security Disable Password command
The device will compare the password sent from this host with that specified in the control word.
Zero indicates that the device should check the supplied password against the user password
Identifier
stored internally. One indicates that the device should check the given password against the
master password stored internally.

123/173

7K200 SATA OEM Specification

14.27

Security Erase Prepare (F3h)

Command Block Output Registers
Register
7 6
Data
- Feature
- Sector Count
- LBA Low
- LBA Mid
- LBA High
- Device
- Command
1 1

7
6
CRC UNC

5
0

5
1

4
1

3
0

2
0

1
1

0
1

Error Register
4
3
2
1
IDN
0
ABT T0N

0
AM
N
0
0
0
0
0
V
0
0
Table 94 Security Erase Prepare Command (F3h)

Command Block Input Registers
Register
7
Data
Error
Sector Count
LBA Low
LBA Mid
LBA High
Device
Status

7
6
BSY RDY
0

6 5 4 3 2 1
- - - - - ...See Below...
- - - - - - - - - - - - - - - - - - - - - - - - - ...See Below...

0
-

Status Register
5
4
3
2
1
0
DF DSC DRQ COR IDX ERR
0

The Security Erase Prepare Command must be issued immediately before the Security Erase Unit
Command to enable device erasing and unlocking.
The Security Erase Prepare Command must be issued immediately before the Format Unit
Command. This command is to prevent accidental erasure of the device.
This command does not request to transfer data.

124/173

7K200 SATA OEM Specification

14.28

Security Erase Unit (F4h)

Command Block Output Registers
Register
7 6
Data
- Feature
- Sector Count
- LBA Low
- LBA Mid
- LBA High
- Device
- Command
1 1

7
6
CRC UNC

5
0

5
1

4
1

3
0

2
1

Error Register
4
3
2
1
IDN
0
ABT T0N

0
0
0
V
0
V
0
Table 95 Security Erase Unit Command (F4h)

1
0

0
0

0
AM
N
0

Command Block Input Registers
Register
7
Data
Error
Sector Count
LBA Low
LBA Mid
LBA High
Device
Status

7
6
BSY RDY
0

5
DF
0

6 5 4 3 2 1
- - - - - ...See Below...
- - - - - - - - - - - - - - - - - - - - - - - - - ...See Below...

0
-

Status Register
4
3
2
1
0
DSC DRQ COR IDX ERR
V

The Security Erase Unit command initializes all user data sectors, then disables the device lock
function.
Note that the Security Erase Unit command initializes from LBA 0 to Native Max LBA. Host Max
LBA set by Initialize Drive Parameter or Set Max Address command is ignored. So the protected
area by Set Max Address command is also initialized.
This command requests to transfer a single sector data from the host including information specified
in the following table.
If the password does not match then the device rejects the command with an Aborted error.
Word
00

01-16
17-255

Description
Control word
bit 0

Identifier (1-Mater, 0-User)

bit 1

Erase mode (1-Enhanced Erase, 0-Normal Erase)

bit 2-15

Reserved

Password
Reserved

(32 bytes)

Table 96 Erase Unit Information
Zero indicates that the device should check the supplied password against the user password
stored internally. One indicates that the device should check the given password against the
master password stored internally.
The Security Erase Unit command erases all user data and disables the security mode feature (device lock function).
So after completing this command, all user data will be initialized to zero with write operation. At this time, it is not
verified with read operation whether the sector of data is initialized correctly. Also, the defective sector information
and the reassigned sector information for the device are not updated. The security erase prepare command should be
completed immediately prior to the Security Erase Unit command. If the device receives a Security Erase Unit
command without a prior Security Erase Prepare command the device aborts the security erase unit command.
Identifier

125/173

7K200 SATA OEM Specification
This command disables the security mode feature (device lock function), however the master
password is still stored internally within the device and may be re-activated later when a new user
password is set. If you execute this command on disabling the security mode feature (device lock
function), the password sent by the host is NOT compared with the password stored in the device for
both the Master Password and the User Password, and then the device only erases all user data.
The execution time of this command in Normal Erase mode is shown below.
HTS722020K9SA00 / HTS722020K9A300
HTS722016K9SA00 / HTS722016K9A300
HTS722012K9SA00 / HTS722012K9A300
HTS722010K9SA00 / HTS722010K9A300
HTS722080K9SA00 / HTS722080K9A300

71 min
63 min
48 min
37 min
33 min

The execution time of this command in Enhanced Erase mode is shown below.
HTS722020K9SA00 / HTS722020K9A300
HTS722016K9SA00 / HTS722016K9A300
HTS722012K9SA00 / HTS722012K9A300
HTS722010K9SA00 / HTS722010K9A300
HTS722080K9SA00 / HTS722080K9A300

73 min
65 min
50 min
39 min
35 min

In case of the FDE model, the execution time in Enhanced Erase mode is less than 1 minutes.

126/173

7K200 SATA OEM Specification

14.29

Security Freeze Lock (F5h)

Command Block Output Registers
Register
7 6
Data
- Feature
- Sector Count
- LBA Low
- LBA Mid
- LBA High
- Device
- Command
1 1

7
6
CRC UNC

5
0

5
1

4
1

3
0

2
1

Error Register
4
3
2
1
IDN
0
ABT T0N

0
0
0
0
0
V
0
Table 97 Security Freeze Lock Command (F5h)

1
0

0
1

0
AM
N
0

Command Block Input Registers
Register
7
Data
Error
Sector Count
LBA Low
LBA Mid
LBA High
Device
Status

7
6
BSY RDY
0

6 5 4 3 2 1
- - - - - ...See Below...
- - - - - - - - - - - - - - - - - - - - - - - - - ...See Below...

0
-

Status Register
5
4
3
2
1
0
DF DSC DRQ COR IDX ERR
0

The Security Freeze Lock Command allows the device to enter frozen mode immediately.
After this command is completed, the command which updates Security Mode Feature (Device Lock
Function) is rejected.
Frozen mode is quit only by Power off.
The following commands are rejected when the device is in frozen mode. For detail, refer to “Table 35
Command table for device lock operation” on Page62-63.
Security Set Password
Security Unlock
Security Disable Password
Security Erase Unit

127/173

7K200 SATA OEM Specification

14.30

Security Set Password (F1h)

Command Block Output Registers
Register
7 6
Data
- Feature
- Sector Count
- LBA Low
- LBA Mid
- LBA High
- Device
- Command
1 1

7
6
CRC UNC

5
0

5
1

4
1

3
0

2
0

1
0

0
1

Error Register
4
3
2
1
IDN
0
ABT T0N

0
AM
N
0
0
0
0
0
V
0
0
Table 98 Security Set Password Command (F1h)

Command Block Input Registers
Register
7
Data
Error
Sector Count
LBA Low
LBA Mid
LBA High
Device
Status

7
6
BSY RDY
0

6 5 4 3 2 1
- - - - - ...See Below...
- - - - - - - - - - - - - - - - - - - - - - - - - ...See Below...

0
-

Status Register
5
4
3
2
1
0
DF DSC DRQ COR IDX ERR
0

The Security Set Password command enables security mode feature (device lock function), and sets
the master password or the user password.
The security mode feature (device lock function) is enabled by this command, and the device is not
locked immediately. The device is locked after next COMRESET with Software Setting
Preservation disabled or power on reset. When the MASTER password is set by this command, the
master password is registered internally, but the device is NOT locked after next power on reset.
This command requests a transfer of a single sector of data from the host including the information
specified in the following table.
The data transferred controls the function of this command.
Word
00

01-16
17-18

Description
Control word
bit 0

: Identifier (1-Mater, 0-User)

bit 1-7

: Reserved

bit 8

: Security level (1-Maximum, 0-High)

bit 1-15

: Reserved

Password (32 bytes)
Master Password Revision Code
(valid if Word 0 bit 0 = 1)

19-255

Reserved

Table 99 Security Set Password Information
Identifier

Zero indicates that the device should check the supplied password against the user
password stored internally. One indicates that the device should check the given password
against the master password stored internally.
128/173

7K200 SATA OEM Specification
Zero indicates High level, one indicates Maximum level. If the host sets High level and the
Security Level
password is forgotten, then the Master Password can be used to unlock the device. If the
host sets Maximum level and the user password is forgotten, only an Security Erase
Prepare/Security Unit command can unlock the device and all data will be lost.
The text of the password - all 32 bytes are always significant.
Password
The Revision Code field is set with Master password. If Identifier is User, the Revision
Master Password
Code is not set. The Revision Code field is returned in Identify Device word 92. The valid
Revision Code
Revision Codes are 0000h to FFFDh. Default Master Password Revision Code is FFFEh.
FFFFh is reserved.
The setting of the Identifier and Security level bits interact as follows.
Identifier=User / Security level = High
The password supplied with the command will be saved as the new user password. The security
mode feature (lock function) will be enabled from the next power on. The file may then be unlocked
by either the user password or the previously set master password.
Identifier=Master / Security level = High
This combination will set a master password but will NOT enable the security mode feature (lock
function).
Identifier=User / Security level = Maximum
The password supplied with the command will be saved as the new user password. The security
mode feature (lock function) will be enabled from the next power on. The file may then be unlocked
by only the user password. The master password previously set is still stored in the file but may
NOT be used to unlock the device.
Identifier=Master / Security level = Maximum
This combination will set a master password but will NOT enable the security mode feature (lock
function).

129/173

7K200 SATA OEM Specification

14.31

Security Unlock (F2h)

Command Block Output Registers
Register
7 6
Data
- Feature
- Sector Count
- LBA Low
- LBA Mid
- LBA High
- Device
- Command
1 1

7
6
CRC UNC

5
0

5
1

4
1

3
0

Error Register
4
3
2
1
IDN
0
ABT T0N

0
V
0
0
0
V
0
Table 100 Security Unlock Command (F2h)

2
0

1
1

0
0

0
AM
N
0

Command Block Input Registers
Register
7
Data
Error
Sector Count
LBA Low
LBA Mid
LBA High
Device
Status

7
6
BSY RDY
0

5
DF

6 5 4 3 2 1
- - - - - ...See Below...
- - - - - - - - - - - - - - - - - - - - - - - - - ...See Below...

0
-

Status Register
4
3
2
1
0
DSC DRQ COR IDX ERR

This command unlocks the password and causes the device to enter device unlock mode. If
COMRESET with Software Setting Preservation disable or power on reset is done without executing
the Security Disable Password command after this command is completed, the device will be in
device lock mode. The password has not been changed yet.
The Security Unlock command requests to transfer a single sector of data from the host including
information specified in the following table.
If the Identifier bit is set to master and the file is in high security mode then the password supplied
will be compared with the stored master password. If the file is in maximum security mode then the
security unlock will be rejected.
If the Identifier bit is set to user, then the file compares the supplied password with the stored user
password.
If the password compare fails then the device returns an abort error to the host and decrements the
unlock attempt counter. This counter is initially set to 5 and is decremented for each password
mismatch. When this counter reaches zero then all password protected commands are rejected until
a power off.
Word
00

Description
Control word
bit 0

: Identifier (1-Master, 0-User)

bit 1-15

: Reserved

01-16
Password
17-255
Reserved
Table 101 Security Unlock Information

(32 bytes)

Zero indicates that device regards Password as User Password. One indicates that device
regards Password as Master Password.
The user can detect if the attempt to unlock the device has failed due to a mismatched password as this is the only
reason that an abort error will be returned by the file AFTER the password information has been sent to the device.
If an abort error is returned by the device BEFORE the password data has been sent to the file then another
problem exists.

Identifier

130/173

7K200 SATA OEM Specification

14.32

Seek (7xh)

Command Block Output Registers
Register
7 6
Data
- Feature
- Sector Count
- LBA Low
V V
LBA Mid
V V
LBA High
V V
Device
- L
Command
0 1

7
6
CRC UNC

5
0

5
V
V
V
1

4
V
V
V
1

3
V
V
V
H
-

2
V
V
V
H
-

Error Register
4
3
2
1
IDN
0
ABT T0N

0
0
0
V
0
Table 102 Seek Command (7xh)

1
V
V
V
H
-

0
V
V
V
H
-

0
AM
N
0

Command Block Input Registers
Register
7
Data
Error
Sector Count
LBA Low
V
LBA Mid
V
LBA High
V
Device
Status

7
6
BSY RDY
0

6 5 4 3 2 1
- - - - - ...See Below...
- - - - - V V V V V V
V V V V V V
V V V V V V
- - - H H H
...See Below...

0
V
V
V
H

Status Register
5
4
3
2
1
0
DF DSC DRQ COR IDX ERR
0

The Seek command initiates a seek to the designated track and selects the designated head. The device need not
be formatted for a seek to execute properly.
Output Parameters To The Device
In LBA mode, this register specifies LBA address bits 0 - 7 for seek. (L=1)
LBA Low
The cylinder number of the seek.
LBA High/Mid
In LBA mode, this register specifies LBA address bits 8 - 15 (Mid), 16 - 23 (High) for
seek. (L=1)
The head number of the seek.
H
In LBA mode, this register specifies LBA address bits 24 - 27 for seek. (L=1)
Input Parameters From The Device
In LBA mode, this register contains current LBA bits 0 - 7. (L=1)
LBA Low
In LBA mode, this register contains current LBA bits 8 - 15 (Mid), 16 - 23 (High).
LBA High/Mid
(L=1)
In LBA mode, this register contains current LBA bits 24 - 27. (L=1)
H

131/173

7K200 SATA OEM Specification

14.33

Sense Condition (F0h : vendor specific)

Command Block Output Registers
Register
7 6
Data
- Feature
0 0
Sector Count
- LBA Low
- LBA Mid
- LBA High
- Device
- Command
1 1

7
6
CRC UNC

5
0

5
0
1

4
0
1

3
0
0

2
0
0

Error Register
4
3
2
1
IDN
0
ABT T0N

0
0
0
V
0
V
0
Table 103 Sense Condition Command (F0h)

1
0
0

0
1
0

0
AM
N
0

Command Block Input Registers
Register
7
Data
Error
Sector Count
V
LBA Low
LBA Mid
LBA High
Device
Status

7
6
BSY RDY
V

6 5 4 3 2 1
- - - - - ...See Below...
V V V V V V
- - - - - - - - - - - - - - - - - - - - ...See Below...

0
V
N
-

Status Register
5
4
3
2
1
0
DF DSC DRQ COR IDX ERR
V

The Sense Condition command is used to sense temperature in a device.
This command is executable without spinning up even if a device is started with No Spin Up option.
If this command is issued at the temperature out of range which is specified for operating condition,
the error might be returned with IDN bit 1.
Output Parameters To The Device
Feature
Input Parameters From The Device
Sector Count

The Feature register must be set to 01h. All other value are rejected with
setting ABORT bit in status register.
The Sector Count register contains result value.
Value
Description
00h

Temperature is equal to or lower than -20 degC

01h-FEh

Temperature is (Value / 2 - 20) deg C

FFh

Temperature is higher than 107 degC

Not recommendable condition for start up. If over stressed condition is
detected, this bit will be set to one.

132/173

7K200 SATA OEM Specification

14.34

Set Features (EFh)

Command Block Output Registers
Register
7 6
Data
- Feature
V V
Sector Count
LBA Low
- LBA Mid
- LBA High
- Device
- Command
1 1

7
6
CRC UNC

5
0

5 4 3 2
- - - V V V V
Note.1
- - - - - - - - - - - - 1 0 1 1

Error Register
4
3
2
1
IDN
0
ABT T0N

0
0
0
0
0
V
Table 104 Set Features Command (EFh)

1 0
- V V
1

0
AM
N
0

Command Block Input Registers
Register
7
Data
Error
Sector Count
LBA Low
LBA Mid
LBA High
Device
Status

7
6
BSY RDY
0

6 5 4 3 2 1
- - - - - ...See Below...
- - - - - - - - - - - - - - - - - - - - - - - - - ...See Below...

0
-

Status Register
5
4
3
2
1
0
DF DSC DRQ COR IDX ERR
0

The Set Feature command is to establish the following parameters which affect the execution of
certain features as shown in below table.
ABT will be set to 1 in the Error Register if the Feature register contains any undefined values.
After power on reset, the device is set to the following features as default.
Write cache
ECC bytes
Read look-ahead
Reverting to power on defaults
Device-initiated interface power state
transition
Software setting preservation

: Enable
: 4 bytes
: Enable
: Disable
: Disable
: Enable

Output Parameters To The Device
Destination code for this command
Feature
Enable write cache (Note.2)
02H
Set transfer mode based on value in sector count register
03H
Enable Advanced Power Management
05H
Enable Power-Up in Standby feature set
06H
Power-Up in Standby feature set device spin-up
07H
Enable use of Serial ATA feature
10H
Enable Automatic Acoustic Management feature set
42H
Disable read look-ahead feature
55H
Disable reverting to power on defaults
66H
Disable write cache
82H
Disable Advanced Power Management (Note.3)
85H
Disable Power-UP in Standby feature set
86H
Disable use of Serial ATA feature
90H
Enable read look-ahead feature
AAH
Disable Automatic Acoustic Management feature set
C2H
Enable reverting to power on defaults
CCH

133/173

7K200 SATA OEM Specification

Note 1.
When Feature register is 03h (=Set Transfer mode), the Sector Count Register specifies the transfer
mechanism. The upper 5 bits define the type of transfer and the low order 3 bits encode the mode
value.

PIO Default Transfer Mode

bits
(7:3)
00000

bits
(2:0)
000

PIO Default Transfer Mode, Disable IORDY

00000

001

PIO Flow Control Transfer Mode x
00001
nnn
(nnn=000,001,010,011,100)
Multiword DMA mode x
00100
nnn
(nnn=000,001,010)
Ultra DMA mode x
01000
nnn
(nnn=000,001,010,011,100,101)
When Feature register is 05h (=Enable Advanced Power Management), the Sector Count Register specifies the
Advanced Power Management level.
C0h - FEh ...
The deepest Power Saving mode is Active Idle
80h - BFh ...
The deepest Power Saving mode is Low power Idle
01h - 7Fh ...
The deepest Power Saving mode is Standby
00h, FFh ...
Aborted

Note 2.
If the number of auto reassigned sectors reaches the device’s reassignment capacity, the write cache
function will be automatically disabled. Although the device still accepts the Set Features
command (with Feature register = 02h) without error, the write cache function will remain disabled.
For current write cache function status, please refer to the Identify Device Information(129word)
by Identify Device command. Power off must not be done in 5 seconds after write command
completion when write cache is enabled.

Note 3.
When Feature register is 85h (=Disable Advanced Power Management), the deepest Power Saving
mode becomes Active Idle.
Note 4.
When the Feature register is set to 10h or 90h, the value set to the Sector Count register specifies the
specific Serial ATA feature to enable or disable.
When the Feature register is set to 10h or 90h, the value set to the Sector Count register specifies the
specific Serial ATA feature to enable or disable.

Sector count value

Description

01h

Non-zero buffer offset in DMA setup FIS

02h

DMA setup FIS auto-activate optimization

03h

Device-initiated interface power state transitions

04h

Guaranteed in-order data delivery

06h

Software Settings Preservation

134/173

7K200 SATA OEM Specification

14.35

Set Max Address (F9h)

Command Block Output Registers
Register
7 6
Data
- Feature
V V
Sector Count
- LBA Low
V V
LBA Mid
V V
LBA High
V V
Device
- L
Command
1 1

7
6
CRC UNC

5
0

5
V
V
V
V
1

4
V
V
V
V
1

3
V
V
V
V
H
1

2
V
V
V
V
H
0

Error Register
4
3
2
1
IDN
0
ABT T0N

0
0
0
0
0
V
0
Table 105 Set Max Address Command (F9h)

1
V
V
V
V
H
0

0
V
B
V
V
V
H
1

0
AM
N
0

Command Block Input Registers
Register
7
Data
Error
Sector Count
LBA Low
V
LBA Mid
V
LBA High
V
Device
Status

7
6
BSY RDY
0

6 5 4 3 2 1
- - - - - ...See Below...
- - - - - V V V V V V
V V V V V V
V V V V V V
- - - H H H
...See Below...

0
V
V
V
H

Status Register
5
4
3
2
1
0
DF DSC DRQ COR IDX ERR
0

The Set Max Address command overwrites the max LBA/CYL of HDD in a range of actual device
capacities. The device receives this command, all accesses beyond that LBA/CYL are rejected with
setting ABORT bit in status register. Identify device command and Identify device DMA command
returns the LBA/CYL which is set via this command as a default value.
This command implement SET Max security extension commands as subcommands. But regardless
of Feature register value, the case this command is immediately preceded by a Read Native Max
Address command, it is interpreted as a Set Max Address command.
The Read Native Max Address command should be issued and completed immediately prior to
issuing Set Max Address command. Otherwise this command is interpreted as a Set Max security
extension command which is destinated by feature register. If Set Max security mode is in the
Locked or Frozen, the Set Max Address command is aborted.
For more information, see “12.10.2 Set Max security extension commands” on Page 65.
In CHS mode, LBA High, LBA Mid specify the max cylinder number. The Head number of Device
and LBA Low are ignored. The default value(See default CHS in Identify device information) is used
for that.
In LBA mode, the Head number of Device, LBA High, LBA Mid and LBA Low specify the max LBA.
This command sets this LBA as the max LBA of the device.
After a successful command completion, Identify Device response words (61:60) shall reflect the
maximum address set with this command.
If the 48-bit Address feature set is supported, the value placed in Identify Device response words
(103:100) shall be the same as the value placed in words (61:60). However, if the device contains
greater than 268,435,455 sectors, the capacity addressable with 28-bit commands, and the address
requested is 268,435,455, the max address shall be changed to the native maximum address, the
value placed in words (61:60) shall be 268,435,455 and the value placed in words (103:100) shall be
the native maximum address.
If a host protected area has been established by a Set Max Address Ext command, the device shall
return command aborted.
Output Parameters To The Device
Feature

Destination code for this command
SET MAX SET PASSWORD
01h
135/173

LBA Low

LBA High/Mid

L
Input Parameters From The Device
LBA Low
LBA High/Mid

7K200 SATA OEM Specification
SET MAX LOCK
02h
SET MAX UNLOCK
03h
SET MAX FREEZE LOCK
04h
When the Set Max ADDRESS command is executed, this register is
ignored.
Option bit for selection whether nonvolatile or volatile. B=0 is volatile
condition. When B=1, MAX LBA/CYL which is set by Set Max
ADDRESS command is preserved by POR. When B=0, MAX LBA/CYL
which is set by Set Max ADDRESS command will be lost by POR.
in LBA mode, this register contains LBA bits 0 - 7 which is to be
input.(L=1)
In CHS mode, this register is ignored. (L=0)
In LBA mode, this register contains LBA bits 8 - 15 (Mid), 16 - 23 (High)
which is to be set. (L=1)
In CHS mode, this register contains max cylinder number which is to be
set. (L=0)
In LBA mode, this register contains LBA bits 24 - 27 which is to be
input.(L=1)
In CHS mode, this register is ignored. (L=0)
LBA mode.Indicates the addressing mode.L=0 specifies CHS mode and
L=1 does LBA addressing mode.
In LBA mode, this register contains Adjusted max LBA bits 0 - 7.(L=1)
In CHS mode, this register contains max LBA Low(= 63). (L=0)
In LBA mode, this register contains Adjusted max LBA bits 8 - 15 (Mid),
16 - 23 (High). (L=1)
In CHS mode, this register contains max cylinder number which is set.
(L=0)
In LBA mode, this register contains Adjusted max LBA bits 24 - 27. (L=1)
In CHS mode, this register contains max head number(= 15).(L=0)

136/173

7K200 SATA OEM Specification

14.36

Set Max Address Ext (37h)

Command Block Output Registers
Register
7 6
Data Low
- Data High
- Feature
Current
- Previous
- Sector Count Current
- Previous
- LBA Low
Current
V V
Previous
V V
LBA Mid
Current
V V
Previous
V V
LBA High
Current
V V
Previous
V V
Device
- 1
Command
0 0

5
V
V
V
V
V
V
1

4
V
V
V
V
V
V
1

3
V
V
V
V
V
V
0

2
V
V
V
V
V
V
1

1
V
V
V
V
V
V
1

Error Register
7
6
5
4
3
2
1
0
CRC UNC 0 IDN 0 ABT T0N AMN
0
0
0
0
0
V
0
0
Table 106 Set Max Address Ext Command (37h)

0
B
V
V
V
V
V
V
1

Command Block Input Registers
Register
7 6 5 4 3 2 1 0
Data Low
- - - - - - - Data High
- - - - - - - Error
...See Below...
Sector Count
LBA Low
LBA Mid
LBA High
Device
Status

HOB=0
HOB=1
HOB=0
HOB=1
HOB=0
HOB=1
HOB=0
HOB=1

V
V
V
V
V
V
-

- - - - - - V V V V
V V V V
V V V V
V V V V
V V V V
V V V V
- - - ...See Below...

Status Register
7
6
5
4
3
2
BSY RDY DF DSC DRQ COR
0
V
0
0

1
IDX
0

V
V
V
V
V
V
-

0
ERR
V

This command is immediately preceded by a Read Native Max Address Ext command.
This command overwrites the maximum number of Address of HDD in a range of actual device
capacity. Once device receives this command, all accesses beyond that Address are rejected with
setting ABORT bit in status register.
When the address requested is greater than 268,435,455, words (103:100) shall be modified to reflect
the requested value, but words (61:60) shall not modified. When the address requested is equal to or
less than 268,435,455, words (103:100) shall be modified to reflect the requested value, and words
(61:60) shall also be modified.
If this command is not supported, the maximum value to be set exceeds the capacity of the device, a
host protected area has been established by a Set Max Address command, the command is not
immediately preceded by a Read Native Max Address Ext command, or the device is in the Set Max
Locked or Set Max Frozen state, the device shall return command aborted.
The device returns the command aborted for a second non-volatile Set Max Address Ext command
until next power on.
Output Parameters To The Device
B

LBA Low Current
LBA Low Previous
LBA Mid Current
LBA Mid Previous
LBA High Current
LBA High Previous
Input Parameters From The Device
LBA Low (HOB=0)

Option bit for selection whether nonvolatile or volatile. B=0 is volatile
condition. When B=1, Max Address which is set by Set Max Address
Ext command is preserved by POR. When B=0, Max Address which is
set by Set Max Address Ext command will be lost by POR.
Set Max LBA (7:0).
Set Max LBA (31:24).
Set Max LBA (15:8).
Set Max LBA (39:32).
Set Max LBA (23:16).
Set Max LBA (47:40).
Set Max LBA (7:0).
137/173

LBA Low (HOB=1)
LBA Mid (HOB=0)
LBA Mid (HOB=1)
LBA High (HOB=0)
LBA High (HOB=1)

7K200 SATA OEM Specification
Set Max LBA (31:24).
Set Max LBA (15:8).
Set Max LBA (39:32).
Set Max LBA (23:16).
Set Max LBA (47:40).

138/173

7K200 SATA OEM Specification

14.37

Set Multiple (C6h)

Command Block Output Registers
Register
7 6
Data
- Feature
- Sector Count
V V
LBA Low
- LBA Mid
- LBA High
- Device
- Command
1 1

7
6
CRC UNC

5
0

5
V
0

4
V
0

3
V
0

2
V
1

Error Register
4
3
2
1
IDN
0
ABT T0N

0
0
0
0
0
V
Table 107 Set Multiple Command (C6h)

1
V
1

0
V
0

0
AM
N
0

Command Block Input Registers
Register
7
Data
Error
Sector Count
LBA Low
LBA Mid
LBA High
Device
Status

7
6
BSY RDY
0

6 5 4 3 2 1
- - - - - ...See Below...
- - - - - - - - - - - - - - - - - - - - - - - - - ...See Below...

0
-

Status Register
5
4
3
2
1
0
DF DSC DRQ COR IDX ERR
0

The Set Multiple command enables the device to perform Read and Write Multiple commands and
establishes the block size for these commands. The block size is the number of sectors to be
transferred for each interrupt.
The default block size after power up is 0, and Read Multiple and Write Multiple commands are
disabled.
If an invalid block size is specified, an Abort error will be returned to the host, and Read Multiple
and Write Multiple commands will be disabled.
Output Parameters To The Device
The block size to be used for Read Multiple and Write Multiple commands. Valid
Sector Count
block sizes can be selected from 0, 1, 2, 4, 8 or 16. If 0 is specified, then Read Multiple
and Write Multiple commands are disabled.

139/173

7K200 SATA OEM Specification

14.38

Sleep (E6h/99h)

Command Block Output Registers
Register
7 6
Data
- Feature
- Sector Count
- LBA Low
- LBA Mid
- LBA High
- Device
- Command
1 1

7
6
CRC UNC

5
0

5
1

4
0

3
0

Error Register
4
3
2
1
IDN
0
ABT T0N

0
0
0
0
0
V
Table 108 Sleep Command (E6h/99h)

2
1

1
1

0
0

0
AM
N
0

Command Block Input Registers
Register
7
Data
Error
Sector Count
LBA Low
LBA Mid
LBA High
Device
Status

7
6
BSY RDY
0

6 5 4 3 2 1
- - - - - ...See Below...
- - - - - - - - - - - - - - - - - - - - - - - - - ...See Below...

0
-

Status Register
5
4
3
2
1
0
DF DSC DRQ COR IDX ERR
0

This command is the only way to cause the device to enter Sleep Mode.
When this command is issued, the device confirms the completion of the cached write commands.
Then the device is spun down, and the interface becomes inactive. The only way to recover from
Sleep Mode is with a software reset or a COMRESET.
If the device is already spun down, the spin down sequence is not executed.

140/173

7K200 SATA OEM Specification

14.39

S.M.A.R.T Function Set (B0h)

Command Block Output Registers
Register
7 6
Data
- Feature
V V
Sector Count
V V
LBA Low
- LBA Mid
0 1
LBA High
1 1
Device
- Command
1 0

7
6
CRC UNC

5
0

5
V
V
0
0
1

4
V
V
0
0
1

3
V
V
1
0
0

2
V
V
1
0
0

Error Register
4
3
2
1
IDN
0
ABT T0N

1
V
V
1
1
0

0
V
V
1
0
0

0
AM
N
0
0
0
0
0
V
0
0
Table 109 S.M.A.R.T. Function Set Command (B0h)

Command Block Input Registers
Register
7
Data
Error
Sector Count
LBA Low
LBA Mid
LBA High
Device
Status

7
6
BSY RDY
0

5
DF
0

6 5 4 3 2 1
- - - - - ...See Below...
- - - - - - - - - - - - - - - - - - - - - - - - - ...See Below...

0
-

Status Register
4
3
2
1
0
DSC DRQ COR IDX ERR
V

The S.M.A.R.T. Function Set command provides access to Attribute Values, Attribute Thresholds
and other low level subcommands that can be used for logging and reporting purposes and to
accommodate special user needs. The S.M.A.R.T. Function Set command has several separate
subcommands which are selectable via the device’s Features Register when the S.M.A.R.T. Function
Set command is issued by the host.

14.39.1 S.M.A.R.T. Sub commands
In order to select a subcommand the host must write the subcommand code to the device’s Features
Register before issuing the S.M.A.R.T. Function Set command. The subcommands and their
respective codes are listed below.
Code
D0h
D1h
D2h
D3h
D4h
D5h
D6h
D8h
D9h
DAh
DBh

Subcommand
S.M.A.R.T. Read Attribute Values
S.M.A.R.T. Read Attribute Thresholds
S.M.A.R.T. Enable/disable Attribute Autosave
S.M.A.R.T. Save Attribute Values
S.M.A.R.T. Execute Off-line Immediate
S.M.A.R.T. Read Log Sector
S.M.A.R.T. Write Log Sector
S.M.A.R.T. Enable Operations
S.M.A.R.T. Disable Operations
S.M.A.R.T. Return Status
S.M.A.R.T. Enable/Disable Automatic Off-Line

14.39.1.1 S.M.A.R.T. Read Attribute Values (Subcommand D0h)
This subcommand returns the device’s Attribute Values to the host. Upon receipt of the S.M.A.R.T.
Read Attribute Values subcommand from the host, the device saves any updated Attribute Values to
the Attribute Data sectors, and then waits for the host to transfer the 512 bytes of Attribute Value
information from the device.

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14.39.1.2 S.M.A.R.T. Read Attribute Thresholds (Subcommand D1h)
This subcommand returns the device’s Attribute Thresholds to the host. Upon receipt of the
S.M.A.R.T. Read Attribute Thresholds subcommand from the host, the device reads the Attribute
Thresholds from the Attribute Threshold sectors and then waits for the host to transfer the 512
bytes of Attribute Thresholds information from the device.

14.39.1.3 S.M.A.R.T. Enable/Disable Attribute Autosave (Subcommand
D2h)
This subcommand enables and disables the attribute autosave feature of the device. The S.M.A.R.T.
Enable/Disable Attribute Autosave subcommand allows the device to automatically save its updated
Attribute Values to the Attribute Data Sector at the timing of the first transition to Active idle mode
after 30 minutes since the last saving of Attribute Values; this subcommand causes the autosave
feature to be disabled. The state of the Attribute Autosave feature (either enabled or disabled) will
be preserved by the device across power cycle.
A value of 00h written by the host into the device’s Sector Count Register before issuing the
S.M.A.R.T. Enable/Disable Attribute Autosave subcommand will cause this feature to be disabled.
Disabling this feature does not preclude the device from saving Attribute Values to the Attribute
Data sectors during some other normal operation such as during a power-up or power-down.
A value of F1h written by the host into the device’s Sector Count Register before issuing the
S.M.A.R.T. Enable/Disable Attribute Autosave subcommand will cause this feature to be enabled.
Any other non-zero value written by the host into this register before issuing the S.M.A.R.T.
Enable/Disable Attribute Autosave subcommand will not change the current Autosave status but the
device will respond with the error code specified in “Table 123 S.M.A.R.T. Error Codes” on Page 155.
The S.M.A.R.T. Disable Operations subcommand disables the autosave feature along with the
device’s S.M.A.R.T. operations.
Upon the receipt of the subcommand from the host the device enables or disables the Autosave
feature.

14.39.1.4 S.M.A.R.T. Save Attribute Values (Subcommand D3h)
This subcommand causes the device to immediately save any updated Attribute Values to the
device’s Attribute Data sector regardless of the state of the Attribute Autosave feature. Upon receipt
of the S.M.A.R.T. Save Attribute Values subcommand from the host, the device writes any updated
Attribute Values to the Attribute Data sector.

14.39.1.5 S.M.A.R.T. Execute Off-line Immediate (Subcommand D4h)
This subcommand causes the device to immediately initiate the set of activities that collect Attribute
data in an off-line mode (off-line routine) or execute a self-test routine in either captive or off-line
mode.
The LBA Low register shall be set to specify the operation to be executed.
LBA Low
0
1
2
3
4
127
128
129
130
131
132

Operation to be executed
Execute S.M.A.R.T. off-line data collection routine immediately
Execute S.M.A.R.T. Short self-test routine immediately in off-line mode
Execute S.M.A.R.T. Extended self-test routine immediately in off-line mode
Reserved
Execute SMART Selective self-test routine immediately in off-line mode
Abort off-line mode self-test routine
Reserved
Execute S.M.A.R.T. Short self-test routine immediately in captive mode
Execute S.M.A.R.T. Extended self-test routine immediately in captive mode
Reserved
Execute SMART selective self-test routine immediately in captive mode
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Off-line mode: The device executes command completion before executing the specified routine.
During execution of the routine the device will not set BSY nor clear DRDY. If the device is in the
process of performing its routine and is interrupted by a new command from the host, the device will
abort or suspend its routine and service the host within two seconds after receipt of the new
command. After servicing the interrupting command, the device will resume its routine
automatically or not start its routine depending on the interrupting command.
Captive mode: When executing self-test in captive mode, the device sets BSY to one and executes the
specified self-test routine after receipt of the command. At the end of the routine, the device sets the
execution result in the Self-test execution status byte and ATA registers as below and executes
command completion.
Status
Error
LBA Mid
LBA High

Set ERR to one when self-test has failed
Set ABRT to one when self-test has failed
Set to F4h when self-test has failed
Set to 2Ch when self-test has failed

SMART Selective self-test routine
When the value in the LBA Low register is 4 or 132, the Selective self-test routine shall be
performed. This self-test routine shall include the initial tests performed by the Extended self-test
routine plus a selectable read scan. The host shall not write the Selective self-test log while the
execution of a Selective self-test command is in progress.
The user may choose to do read scan only on specific areas of the media. To do this, user shall set the
test spans desired in the Selective self-test log and set the flags in the Feature flags field of the
Selective self-test log to indicate do not perform off-line scan. In this case, the test spans defined
shall be read scanned in their entirety. The Selective self-test log is updated as the self-test proceeds
indicating test progress. When all specified test spans have been completed, the test is terminated
and the appropriate self-test execution status is reported in the S.M.A.R.T. READ DATA response
depending on the occurrence of errors. The following figure shows an example of a Selective selftest
definition with three test spans defined. In this example, the test terminates when all three test
spans have been scanned.

Figure 10 Selective self-test test span example
After the scan of the selected spans described above, a user may wish to have the rest of media read
scanned as an off-line scan. In this case, the user shall set the flag to enable off-line scan in addition
to the other settings. If an error occurs during the scanning of the test spans, the error is reported in
the self-test execution status in the S.M.A.R.T. READ DATA response and the off-line scan is not
executed. When the test spans defined have been scanned, the device shall then set the offline scan
pending and active flags in the Selective self-test log to one, the span under test to a value greater
than five, the self-test execution status in the S.M.A.R.T. READ DATA response to 00h, set a value
of 03h in the off-line data collection status in the S.M.A.R.T. READ DATA response and shall
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proceed to do an off-line read scan through all areas not included in the test spans. This off-line read
scan shall completed as rapidly as possible, no pauses between block reads, and any errors
encountered shall not be reported to the host. Instead error locations may be logged for future
reallocation. If the device is powered-down before the off-line scan is completed, the off-line scan
shall resume when the device is again powered up. From power-up, the resumption of the scan shall
be delayed the time indicated in the Selective self-test pending time field in the Selective self-test
log. During this delay time the pending flag shall be set to one and the active flag shall be set to zero
in the Selective self-test log. Once the time expires, the active flag shall be set to one, and the off-line
scan shall resume. When the entire media has been scanned, the off-line scan shall terminate, both
the pending and active flags shall be cleared to zero, and the off-line data collection status in the
S.M.A.R.T. READ DATA response shall be set to 02h indicating completion.
During execution of the Selective self-test, the self-test executions time byte in the Device S.M.A.R.T.
Data Structure may be updated but the accuracy may not be exact because of the nature of the test
span segments. For this reason, the time to complete off-line testing and the self-test polling times
are not valid. Progress through the test spans is indicated in the selective self-test log.
A COMRESET or software reset shall abort the Selective self-test except when the pending bit is set
to one in the Selective self-test log (see 14.39.7 Selective self-test log data structure). The receipt of a
S.M.A.R.T. EXECUTE OFF-LINE IMMEDIATE command with 0Fh, Abort off-line test routine, in
the LBA Low register shall abort Selective self-test regardless of where the device is in the execution
of the command. If a second self-test is issued while a selective self-test is in progress, the selective
self-test is aborted and the newly requested self-test is executed.

14.39.1.6 S.M.A.R.T. Read Log Sector (Subcommand D5h)
This command returns the specified log sector contents to the host.
The 512 bytes data are returned at a command and the Sector Count value shall be set to one. The
LBA Low shall be set to specify the log sector address.
Log sector address
00h
01h
06h
09h
80h-9Fh
Table 110 Log sector addresses

Content
Log Directory
S.M.A.R.T. Error Log
S.M.A.R.T. Self-test Log
Selective self-test log
Host vendor specific

Type
Read Only
Read Only
Read Only
Read/Write
Read/Write

14.39.1.7 S.M.A.R.T. Write Log Sector (Subcommand D6h)
This command writes 512 bytes data to the specified log sector.
The 512 bytes data are transferred at a command and the Sector Count value shall be set to one. The
LBA Low shall be set to specify the log sector address (Table 110 Log sector addresses). If Read Only
log sector is specified, the device returns ABRT error.

14.39.1.8 S.M.A.R.T. Enable Operations (Subcommand D8h)
This subcommand enables access to all S.M.A.R.T. capabilities within the device. Prior to receipt of a
S.M.A.R.T. Enable Operations subcommand, Attribute Values are neither monitored nor saved by
the device. The state of S.M.A.R.T. (either enabled or disabled) will be preserved by the device across
power cycles. Once enabled, the receipt of subsequent S.M.A.R.T. Enable Operations subcommands
will not affect any of the Attribute Values.
Upon receipt of the S.M.A.R.T. Enable Operations subcommand from the host, the device enables
S.M.A.R.T. capabilities and functions.

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14.39.1.9 S.M.A.R.T. Disable Operations (Subcommand D9h)
This subcommand disables all S.M.A.R.T.capabilities within the device including the device’s
attribute autosave feature. After receipt of this subcommand the device disables all S.M.A.R.T.
operations. Non self-preserved Attribute Values will no longer be monitored. The state of
S.M.A.R.T. (either enabled or disabled) is preserved by the device across power cycles. Note that
this subcommand does not preclude the device’s power mode attribute autosaving.
Upon receipt of the S.M.A.R.T. Disable Operations subcommand from the host, the device disables
S.M.A.R.T. capabilities and functions.
After receipt of the device of the S.M.A.R.T. Disable Operations subcommand from the host, all other
S.M.A.R.T. subcommands—with the exception of S.M.A.R.T. Enable Operations—are disabled, and
invalid and will be aborted by the device (including the S.M.A.R.T. Disable Operations subcommand),
returning the error code as specified in “Table 123 S.M.A.R.T. Error Codes” on Page 155.
Any Attribute Values accumulated and saved to volatile memory prior to receipt of the S.M.A.R.T.
Disable Operations command will be preserved in the device’s Attribute Data Sectors. If the device is
re-enabled, these Attribute Values will be updated, as needed, upon receipt of a S.M.A.R.T. Read
Attribute Values or S.M.A.R.T. Save Attribute Values command.

14.39.1.10 S.M.A.R.T. Return Status (Subcommand DAh)
This command is used to communicate the reliability status of the device to the host’s request. Upon
receipt of the S.M.A.R.T. Return Status subcommand the device asserts BSY, saves any updated
Attribute Values to the reserved sector and compares the updated Attribute Values to the Attribute
Thresholds.
If the device does not detect a Threshold Exceeded Condition, or detects a Threshold Exceeded
Condition but involving attributes are advisory, the device loads 4Fh into the LBA Mid register, C2h
into the LBA High register.
If the device detects a Threshold Exceeded Condition for prefailure attributes, the device loads F4h
into the LBA Mid register, 2Ch into the LBA High register. Advisory attributes never result in
negative reliability condition.

14.39.1.11 S.M.A.R.T. Enable/Disable Automatic Off-Line
(Subcommand DBh)
This subcommand enables and disables the optional feature that cause the device to perform the set
of off-line data collection activities that automatically collect attribute data in an off-line mode and
then save this data to the device’s non-volatile memory. This subcommand may either cause the
device to automatically initiate or resume performance of its off-line data collection activities or
cause the automatic off-line data collection feature to be disabled. This subcommand also enables
and disables the off-line read scanning feature that cause the device to perform the entire read
scanning with defect reallocation as the part of the off-line data collection activities.
The Sector Count register shall be set to specify the feature to be enabled or disabled.
Sector Count
Feature Description
00h
Disable Automatic Off-line
01h
Disable Off-line Read Scanning
F8h
Enable Automatic Off-line
F9h
Enable Off-line Read Scanning
A value of zero written by the host into the device’s Sector Count register before issuing this
subcommand shall cause the automatic off-line data collection feature to be disabled. Disabling this
feature does not preclude the device from saving attribute values to non-volatile memory during
some other normal operation such as during a power-on or power-off sequence or during an error
recovery sequence.
A value of one written by the host into the device’s Sector Count register before issuing this
subcommand shall cause the off-line read scanning feature to be disabled. The Device does not
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perform the off-line read scanning at the off-line data collection activities which is initiated by the
S.M.A.R.T. Execute Off-line Immediate(Subcommand D4h) or automatically if the off-line read
scanning feature is disabled.
A value of F8h written by the host into the device’s Sector Count register before issuing this
subcommand shall cause the automatic Off-line data collection feature to be enabled.
A value of F9 written by the host into the device’s Sector Count register before issuing this
subcommand shall cause the off-line read scanning feature to be enabled. The Device perform the
off-line read scanning at the off-line data collection activities which is initiated by the S.M.A.R.T.
Execute Off-line Immediate(Subcommand D4h) even if the automatic off-line feature is disabled.
Any other non-zero value written by the host into this register before issuing this subcommand is
vender specific and will not change the current Automatic Off-Line Data Collection and Off-line
Read Scanning status, but device may respond with the error code specified in “Table 123 S.M.A.R.T.
Error Codes” on Page 155.

14.39.2 Device Attributes Data Structure
The following defines the 512 bytes that make up the Attribute Value information. This data
structure is accessed by the host in its entirety using the S.M.A.R.T. Read Attribute Values
subcommand. All multi-byte fields shown in these data structures follow the ATA/ATAPI-6
specification for byte ordering, namely that the least significant byte occupies the lowest numbered
byte address location in the field.
Description
Data Structure Revision Number
1st Device Attribute
...
...
30th Device Attribute
Off-line data collection status
Self-test execution status
Total time in seconds to complete off-line data collection activity
Current segment pointer
Off-line data collection capability
S.M.A.R.T. capability
S.M.A.R.T. device error logging capability
Self-test failure check point
Short self-test completion time in minutes
Extended self-test completion time in minutes
Reserved
Vendor specific
Data structure checksum

Bytes

Offset
2
12
..
..
12
1
1
2
1
1
2
1
1
1
1
12
125
1
512

Format
Value
00h
binary
0010h
02h
(*1)
(*2)

15Eh
16Ah
16Bh
16Ch
16Eh
16Fh
170h
172h
173h
174h
175h
176h
182h
1FFh

(*1)
(*1)
(*1)
(*1)
(*1)
(*1)
(*1)
(*1)
(*1)
(*1)
(*1)

(*1)

(*2)
(*2)
(*2)
(*2)
(*2)
1Bh
0003h
01h
(*2)
(*2)
(*2)
(*3)
(*3)
(*2)

(*1) - See following definitions
(*2) - Value varied by actual operating condition
(*3) - Filled with 00h
Table 111 Device Attribute Data Structure

14.39.2.1

Data Structure Revision Number

The Data Structure Revision Number identifies which version of this data structure is implemented
by the device. This revision number will be set to 0005h. This revision number identifies both the
Attribute Value and Attribute Threshold Data structures.

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14.39.2.2

Individual Attribute Data Structure

The following defines the 12 bytes that make up the information for each Attribute entry in the
Device Attribute Data Structure.
Description
Attribute ID Number (01h to FFh)
Status Flags
Bit 0 Pre-Failure/Advisory

Bytes

Offset
1
00h
2
01h

Format
binary
bit flags

03h

binary

1
6
1
12

04h
05h
0Bh

binary
binary
binary

Bit 1 On-line Collection
Bit 2-5 Reserved (may either 0 or 1)
Bit 6-15 Reserved (all 0)
Attribute Value (valid values from 01h to FEh)
00h invalid for attribute value – not to be used
01h minimum value
64h initial value for all attributes prior to any data collection
FDh maximum value
FEh value is not valid
FFh invalid for attribute value - not to be used
Reserved (may not be 0)
Reserved (may not be 0)
Reserved (00h)
Total Bytes
Table 112 Individual Attribute Data Structure

Attribute ID Numbers: Any non-zero value in the Attribute ID Number indicates an active attribute.
The device supports following Attribute ID Numbers. Those marked with (*) indicate that
corresponding Attribute Values can be either collected on-line or off-line.
ID
0
1
2
3
4
5
7
8
9
10
12
191
192
193
194
196
197
198
199

Attribute Name
Indicates that this entry in the data structure is not used
Raw Read Error Rate (*)
Throughput Performance (*)
Spin Up Time
Start/Stop Count
Reallocated Sector Count
Seek Error Rate
Seek Time Performance (*)
Power-On Hours Count
Spin Retry Count
Device Power Cycle Count
G Sense error rate
Power off retract count
Load/Unload cycle count
Device Temperature
Reallocation Event Count
Current Pending Sector Count
Off-Line Scan Uncorrectable Sector Count
Ultra DMA CRC Error Count
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7K200 SATA OEM Specification
Load Retry Count
223
Status Flag Definitions:
Bit
0

Flag Name
Pre-Failure/Advisory bit

Definition
If bit = 0, an Attribute Value less than or equal to its
corresponding Attribute Threshold indicates an Advisory
condition where the usage or age of the device has
exceeded its intended design life period.
If bit = 1, an Attribute Value less than or equal
to its corresponding Attribute Threshold
indicates a Pre-Failure condition where imminent
loss of data is being predicted.

On-Line Collective bit

2-5
Reserved bits
6-15
Reserved bits
Table 113 Status Flag Definitions

If bit = 0, the Attribute Value is updated only during
Off-Line testing.
If bit = 1, the Attribute Value is updated during On-Line
testing or during both On-Line and Off-Line testing.
may either 0 or 1
Always 0

Normalized Values: The device will perform conversion of the raw Attribute Values to transform
them into normalized values, which the host can then compare with the Threshold values. A
Threshold is the excursion limit for a normalized Attribute Value. In normalizing the raw data, the
device will perform any necessary statistical validity checks to ensure that an instantaneous raw
value is not improperly reflected in the normalized Attribute Value (i.e., one read error in the first 10
reads being interpreted as exceeding the read error rate threshold when the subsequent 1 billion
reads all execute without error). The end points for the normalized values for all Attributes will be 1
(01h) at the low end, and 100 (64h) at the high end for the device. For Performance and Error Rate
Attributes, values greater than 100 are also possible, up to a maximum value of 253 (FDh).

14.39.2.3

Off-Line Data Collection Status

The value of this byte defines the current status of the off-line activities of the device. Bit 7 indicates
Automatic Off-Line Data Collection Status.
Bit 7
Automatic Off-Line Data Collection Status
Automatic Off-Line Data Collection is disabled.
0
Automatic Off-Line Data Collection is enabled.
1
Bits 0 thru 6 represents a hexadecimal status value reported by the device.
Value
0
2
4
5
6

Definition
Off-line data collection never started
All segments completed without errors. In this case, current segment pointer equals to total segments
required.
Off-line data collection suspended by interrupting command
Off-line data collecting aborted by interrupting command
Off-line data collection aborted with fatal error

14.39.2.4
Bit
0-3

4-7

Self-test execution status

Definition
Percent Self-test remaining
An approximation of the percent of the self-test routine remaining until completion in ten percent
increments. Valid values are 0 through 9.
Current Self-test execution status
The self-test routine completed without error or has never been run
0
The self-test routine aborted by the host
1
The self-test routine interrupted by the host with a hard or soft reset
2
The device was unable to complete the self-test routine due to a fatal error or unknown test error
3
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4
5
6
7
15

7K200 SATA OEM Specification
The self-test routine completed with unknown element failure
The self-test routine completed with electrical element failure
The self-test routine completed with servo element failure
The self-test routine completed with read element failure
The self-test routine in progress

14.39.2.5

Total Time in Seconds to Complete Off-line Data
Collection Activity

This field tells the host how many seconds the device requires to complete the off-line data collection
activity.

14.39.2.6

Current Segment Pointer

This byte is a counter indicating the next segment to execute as an off-line data collection activity.
Because the number of segments is 1, 01h is always returned in this field.

14.39.2.7
Bit
0

5
6

Off-Line Data Collection Capability

Definition
Execute Off-line Immediate implemented bit
S.M.A.R.T. Execute Off-line Immediate subcommand is not implemented
0
S.M.A.R.T. Execute Off-line Immediate subcommand is implemented
1
Enable/disable Automatic Off-line implemented bit
S.M.A.R.T. Enable/disable Automatic Off-line subcommand is not implemented
0
S.M.A.R.T. Enable/disable Automatic Off-line subcommand is implemented
1
abort/restart off-line by host bit
The device will suspend off-line data collection activity after an interrupting command and resume
0
it after some vendor specific event
The device will abort off-line data collection activity upon receipt of a new command
1
Off-line Read Scanning implemented bit
The device does not support Off-line Read Scanning
0
The device supports Off-line Read Scanning
1
Self-test implemented bit
Self-test routine is not implemented
0
Self-test routine is implemented
1
Reserved (0)
Selective self-test implemented bit
Selective self-test routine is not implemented
0
Selective self-test routine is implemented
1
Reserved (0)

14.39.2.8

S.M.A.R.T. Capability

This word of bit flags describes the S.M.A.R.T. capabilities of the device. The device will return 03h
indicating that the device will save its Attribute Values prior to going into a power saving mode and
supports the S.M.A.R.T. ENABLE/DISABLE ATTRIBUTE AUTOSAVE command.
Bit
0

Definition
Pre-power mode attribute saving capability
If bit = 1, the device will save its Attribute Values prior to going into a power saving
mode (Standby or Sleep mode).

2-15

Attribute autosave capability
If bit = 1, the device supports the S.M.A.R.T. ENABLE/DISABLE ATTRIBUTE AUTOSAVE
command.
Reserved (0)

14.39.2.9
Bit
7-1

Error Logging Capability

Definition
Reserved (0)
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7K200 SATA OEM Specification
0

Error Logging support bit
If bit = 1, the device supports the Error Logging

14.39.2.10

Self-test failure check point

This byte indicates the section of self-test where the device detected a failure.

14.39.2.11

Self-test completion time

These bytes are the minimum time in minutes to complete self-test.

14.39.2.12

Data Structure Checksum

The Data Structure Checksum is the 2’s compliment of the result of a simple 8-bit addition of the
first 511 bytes in the data structure.

14.39.3 Device Attribute Thresholds Data Structure
The following defines the 512 bytes that make up the Attribute Threshold information. This data
structure is accessed by the host in its entirety using the S.M.A.R.T. Read Attribute Thresholds. All
multi-byte fields shown in these data structures follow the ATA/ATAPI-6 specification for byte
ordering, namely that the least significant byte occupies the lowest numbered byte address location
in the field.
The sequence of active Attribute Thresholds will appear in the same order as their corresponding
Attribute Values.
Description
Data Structure Revision Number
1st Attribute Threshold
...
...
30th Attribute Threshold
Reserved
Vendor specific
Data structure checksum

Bytes

Offset
2
12
..
..
12
18
131
1
512

00h
02h

15Eh
16Ah
17Ch
1FFh

Format
binary
(*1)

Value
0010h
(*2)

(*1)

(*2)
(*3)
(*3)
(*2)

(*1) - See following definitions
(*2) - Value varied by actual operating condition
(*3) - Filled with 00h
Table 114 Device Attribute Thresholds Data Structure

14.39.3.1

Data Structure Revision Number

This value is the same as the value used in the Device Attributes Values Data Structure.

14.39.3.2

Individual Thresholds Data Structure

The following defines the 12 bytes that make up the information for each Threshold entry in the
Device Attribute Thresholds Data Structure. Attribute entries in the Individual Threshold Data
Structure is in the same order and correspond to the entries in the Individual Attribute Data
Structure.

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7K200 SATA OEM Specification

Description
Attribute ID Number (01h to FFh)
Attribute Threshold (for comparison with Attribute Values
from 00h to FFh)
00h -

“always passing” threshold value to be
used for code test purposes

01h -

minimum value for normal operation

FDh -

maximum value for normal operation

FEh -

invalid for threshold value

FFh -

“always failing” threshold value to be used
for code test purposes

Bytes

Reserved (00h)
Total Bytes
Table 115 Individual Threshold Data Structure

14.39.3.3

1
1

Offset
00h
01h

Format
binary
binary

10
12

02h

binary

Attribute ID Numbers

Attribute ID Numbers supported by the device are the same as Attribute Values Data Structures.

14.39.3.4

Attribute Threshold

These values are preset at the factory and are not meant to be changeable. However, the host
might use “ S.M.A.R.T. Write Attribute Threshold” subcommand to override these preset values
in the Threshold sectors.

14.39.3.5

Data Structure Checksum

The Data Structure Checksum is the 2’s compliment of the result of a simple 8-bit addition of the
first 511 bytes in the data structure.

14.39.4 S.M.A.R.T. Log Directory
Following table defines the 512 bytes that make up the S.M.A.R.T. Log Directory. The S.M.A.R.T.
Log Directory is on S.M.A.R.T. Log Address zero and is defined as one sector long.
Description
S.M.A.R.T. Logging Version
Number of sectors in the log at log address 1
Reserved
Number of sectors in the log at log address 2
Reserved
…
Number of sectors in the log at log address 255
Reserved

Bytes
2
1
1
1
1
…
1
1
512

Offset
00h
02h
03h
04h
05h
…
1FEh
1FFh

Table 116 SMART Log Directory
The value of the S.M.A.R.T. Logging Version word shall be 01h. The logs at log addresses
80-9Fh are defined as 16 sectors long.

14.39.5 S.M.A.R.T. error log sector
The following defines the 512 bytes that make up the S.M.A.R.T. error log sector. All multi-byte
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fields shown in these data structures follow the ATA/ATAPI-6 specifications for byte ordering.
Description
Bytes Offset
S.M.A.R.T. error log version
1
00h
Error log pointer
1
01h
1st error log data structure
90
02h
2nd error log data structure
90
5Ch
3rd error log data structure
90
B6h
4th error log data structure
90
110h
5th error log data structure
90
16Ah
Device error count
2
1C4h
Reserved
57
1C6h
Data structure checksum
1
1FFh
512
Table 117 S.M.A.R.T. error log sector

14.39.5.1

S.M.A.R.T. error log version

This value is set to 01h.

14.39.5.2

Error log pointer

This points the most recent error log data structure. Only values 1 through 5 are valid.

14.39.5.3

Device error count

This field contains the total number of errors. The value will not roll over.

14.39.5.4

Error log data structure

Data format of each error log structure is shown below.
Description
1st error log data structure
2nd error log data structure
3rd error log data structure
4th error log data structure
5th error log data structure
Error data structure
Table 118 Error log data structure

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Bytes Offset
12
12
12
12
12
30
90

00h
0Ch
18h
24h
30h
3Ch

7K200 SATA OEM Specification

Command data structure: Data format of each command data structure is shown below.
Description
Bytes Offset
Device Control register
1
Features register
1
Sector count register
1
LBA Low register
1
LBA Mid register
1
LBA High register
1
Device register
1
Command register
1
Timestamp(milliseconds from Power On)
4
12
Table 119 Command data structure
Error data structure: Data format of error data structure is shown below.
Description
Reserved
Error register
Sector count register
LBA Low register
LBA Mid register
LBA High register
Device register
Status register
Extended error data (vendor specific)
State
Life timestamp (hours)

Bytes Offset
1
1
1
1
1
1
1
1
19
1
2
30

00h
01h
02h
03h
04h
05h
06h
07h
08h

00h
01h
02h
03h
04h
05h
06h
07h
08h
1Bh
1Ch

Table 120 Error data structure
State field contains a value indicating the device state when command was issued to the device.
Value
State
Unknown
x0h
Sleep
x1h
Standby
x2h
Active/Idle
x3h
S.M.A.R.T. Off-line or Self-test
x4h
Reserved
x5h-xAh
Vendor specific
xBh-xFh
Note: The value of x is vendor specific

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14.39.6 Self-test log data structure
The following defines the 512 bytes that make up the Self-test log sector. All multi-byte fields
shown in these data structures follow the ATA/ATAPI-7 specifications for byte ordering.
Description
Bytes Offset
Data structure revision
2
00h
Self-test number
1
n*18h+02h
Self-test execution status
1
n*18h+03h
Life time power on hours
2
n*18h+04h
Self-test failure check point
1
n*18h+06h
LBA of first failure
4
n*18h+07h
Vendor specific
15
n*18h+0Bh
...
Vendor specific
2
1FAh
Self-test log pointer
1
1FCh
Reserved
2
1FDh
Data structure checksum
1
1FFh
512
Note: n is 0 through 20
Table 121 Self-test log data structure
The data structure contains the descriptor of Self-test that the device has performed. Each
descriptor is 24 bytes long and the self-test data structure is capable to contain up to 21
descriptors.
After 21 descriptors has been recorded, the oldest descriptor will be overwritten with new
descriptor.
Self-test log pointer points the most recent descriptor. When there is no descriptor the value is 0.
When there is descriptor(s) the value is 1 through 21.

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14.39.7 Selective self-test log data structure
The Selective self-test log is a log that may be both written and read by the host. This log allows
the host to select the parameters for the self-test and to monitor the progress of the self-test.
The following table defines the contents of the Selective self-test log which is 512 bytes long. All
multi-byte fields shown in these data structures follow the specifications for byte ordering.
Description
Bytes Offset Read/Write
Data structure revision
2
00h
R/W
Starting LBA for test span 1
8
02h
R/W
Ending LBA for test span 1
8
0Ah
R/W
Starting LBA for test span 2
8
12A
R/W
Ending LBA for test span 2
8
1Ah
R/W
Starting LBA for test span 3
8
22h
R/W
Ending LBA for test span 3
8
2Ah
R/W
Starting LBA for test span 4
8
32h
R/W
Ending LBA for test span 4
8
3Ah
R/W
Starting LBA for test span 5
8
42h
R/W
Ending LBA for test span 5
8
4Ah
R/W
Reserved
256
52h
Reserved
Vendor specific
154
152h
Vendor specific
Current LBA under test
8
1ECh Read
Current span under test
2
1F4h
Read
Feature flags
2
1F6
R/W
Vendor specific
4
1F8h
Vendor specific
Selective self test pending time 2
1FCh R/W
Reserved
1
1FEh Reserved
Data structure checksum
1
1FFh R/W
512
Table 122 Selective self-test log data structure

14.39.8 Error Reporting
The following table shows the values returned in the Status and Error Registers when specific
error conditions are encountered by a device.
Error Condition
Status Register
Error Register
A S.M.A.R.T. FUNCTION SET command was received
51h
04h
by the device without the required key being loaded into
the LBA High and LBA Mid registers.
A S.M.A.R.T. FUNCTION SET command was received
51h
04h
by the device with a subcommand value in the Features
Register that is either invalid or not supported by this
device.
A S.M.A.R.T. FUNCTION SET command subcommand
51h
04h
other than S.M.A.R.T. ENABLE OPERATIONS was
received by the device while the device was in a
“S.M.A.R.T. disabled” state.
The device is unable to read its Attribute Values or
51h
10h or 40h
Attribute Thresholds data structure.
The device is unable to write to its Attribute Values data
51h
10h or 01h
structure.
Table 123 S.M.A.R.T. Error Codes

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7K200 SATA OEM Specification

14.40

Standby (E2h/96h)

Command Block Output Registers
Register
7 6 5 4 3 2
Data
- - - - - Feature
- - - - - Sector Count
V V V V V V
LBA Low
- - - - - LBA Mid
- - - - - LBA High
- - - - - Device
- - - - - Command
1 1 1 0 0 0
Error Register
7
6
5
4
3
2
1
CRC UNC
0
IDN
0
ABT T0N
0
0
0
0
0
V
Table 124 Standby Command (E2h/96h)

1
V
1

0
V
0

0
AM
N
0

Command Block Input Registers
Register
7 6 5 4 3 2 1 0
Data
- - - - - - - Error
...See Below...
Sector Count
- - - - - - - LBA Low
- - - - - - - LBA Mid
- - - - - - - LBA High
- - - - - - - Device
- - - - - - - Status
...See Below...
Status Register
7
6
5
4
3
2
1
0
BSY RDY DF DSC DRQ COR IDX ERR
0

The Standby command causes the device to enter the Standby Mode immediately, and set auto
power down timeout parameter(standby timer).
When this command is issued, the device confirms the completion of the cached write commands.
Then the device is spun down, but the interface remains active.
If the device is already spun down, the spin down sequence is not executed.
During the Standby mode the device will respond to commands, but there is a delay while
waiting for the spindle to reach operating speed.
The timer starts counting down when the device returns to Idle mode.
Output Parameters To The Device
Sector Count
Timeout Parameter. If zero, the timeout interval(Standby Timer) is disabled. If other
than zero, the timeout interval is set for (Timeout Parameter x5) seconds.
When the automatic power down sequence is enabled,
The device will enter Standby mode automatically if the timeout interval expires with
no device access from the host. The timeout interval will be reinitialized if there is a
device access before the timeout interval expires.

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7K200 SATA OEM Specification

14.41

Standby Immediate (E0h/94h)

Command Block Output Registers
Register
7 6
Data
- Feature
- Sector Count
- LBA Low
- LBA Mid
- LBA High
- Device
- Command
1 1

7
6
CRC UNC

5
0

5
1

4
0

3
0

Error Register
4
3
2
1
IDN
0
ABT T0N

2
0

1
0

0
0

0
AM
N
0
0
0
0
0
V
0
0
Table 125 Standby Immediate Command (E0h/94h)

Command Block Input Registers
Register
7
Data
Error
Sector Count
LBA Low
LBA Mid
LBA High
Device
Status

7
6
BSY RDY
0

6 5 4 3 2 1
- - - - - ...See Below...
- - - - - - - - - - - - - - - - - - - - - - - - - ...See Below...

0
-

Status Register
5
4
3
2
1
0
DF DSC DRQ COR IDX ERR
0

The Standby Immediate command causes the device to enter Standby mode immediately.
When this command is issued, the device confirms the completion of the cached write commands.
Then the device is spun down, but the interface remains active.
If the device is already spun down, the spin down sequence is not executed.
During the Standby mode, the device will respond to commands, but there is a delay while
waiting for the spindle to reach operating speed.
The Standby Immediate command will not affect the auto power down timeout parameter.

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7K200 SATA OEM Specification

14.42

Write Buffer (E8h)

Command Block Output Registers
Register
7 6
Data
- Feature
- Sector Count
- LBA Low
- LBA Mid
- LBA High
- Device
- Command
1 1

7
6
CRC UNC

5
0

5
1

4
0

3
1

Error Register
4
3
2
1
IDN
0
ABT T0N

0
0
0
0
0
V
0
Table 126 Write Buffer Command (E8h)

2
0

1
0

0
0

0
AM
N
0

Command Block Input Registers
Register
7
Data
Error
Sector Count
LBA Low
LBA Mid
LBA High
Device
Status

7
6
BSY RDY
0

6 5 4 3 2 1
- - - - - ...See Below...
- - - - - - - - - - - - - - - - - - - - - - - - - ...See Below...

0
-

Status Register
5
4
3
2
1
0
DF DSC DRQ COR IDX ERR
0

The Write Buffer command transfers a sector of data from the host to the sector buffer of the
device. The sectors of data are transferred through the Data Register 16 bits at a time.
The Read Buffer and Write Buffer commands are synchronized such that sequential Write
Buffer and Read Buffer commands access the same 512 byte within the buffer.

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14.43

Write DMA (CAh/CBh)

Command Block Output Registers
Register
7 6
Data
- Feature
- Sector Count
V V
LBA Low
V V
LBA Mid
V V
LBA High
V V
Device
- L
Command
1 1

7
6
CRC UNC

5
0

5
V
V
V
V
0

4
V
V
V
V
0

3
V
V
V
V
H
1

2
V
V
V
V
H
0

Error Register
4
3
2
1
IDN
0
ABT T0N

V
0
0
V
0
V
0
Table 127 Write DMA Command (CAh/CBh)

1
V
V
V
V
H
1

0
V
V
V
V
H
R

0
AM
N
0

Command Block Input Registers
Register
7
Data
Error
Sector Count
V
LBA Low
V
LBA Mid
V
LBA High
V
Device
Status

7
6
BSY RDY
0

5
DF

6 5 4 3 2 1
- - - - - ...See Below...
V V V V V V
V V V V V V
V V V V V V
V V V V V V
- - - H H H
...See Below...

0
V
V
V
V
H

Status Register
4
3
2
1
0
DSC DRQ COR IDX ERR

The Write DMA command transfers one or more sectors of data from the host to the device, then
the data is written to the disk media.
The sectors of data are transferred through the Data Register 16 bits at a time.
The host initializes a slave-DMA channel prior to issuing the command. Data transfers are
qualified by DMARQ and are performed by the slave-DMA channel. The device issues only one
interrupt per command to indicate that data transfer has terminated and status is available.
If an uncorrectable error occurs, the write will be terminated at the failing sector.
Output Parameters To The Device
The number of continuous sectors to be transferred. If zero is specified, then 256 sectors
Sector Count
will be transferred.
The sector number of the first sector to be transferred. (L=0)
LBA Low
In LBA mode, this register contains LBA bits 0 - 7. (L=1)
The cylinder number of the first sector to be transferred. (L=0)
LBA High/Mid
In LBA mode, this register contains LBA bits 8 - 15 (Mid), 16 - 23 (High).
(L=1)
H

The head number of the first sector to be transferred. (L=0)
In LBA mode, this register contains LBA bits 24 - 27. (L=1)
The retry bit, but this bit is ignored.
R
Input Parameters From The Device
Sector Count
The number of requested sectors not transferred. This will be zero, unless
an unrecoverable error occurs.
LBA Low

The sector number of the last transferred sector. (L=0)
In LBA mode, this register contains current LBA bits 0 - 7. (L=1)

LBA High/Mid

The cylinder number of the last transferred sector. (L=0)
In LBA mode, this register contains current LBA bits 8 - 15 (Mid), 16 - 23 (High).
(L=1)
The head number of the last transferred sector. (L=0) In LBA mode, this register
contains current LBA bits 24 - 27. (L=1)

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14.44

Write DMA Ext (35h)

5
V
V
V
V
V
V
V
V
1

4
V
V
V
V
V
V
V
V
1

3
V
V
V
V
V
V
V
V
0

2
V
V
V
V
V
V
V
V
1

1
V
V
V
V
V
V
V
V
0

Error Register
7
6
5
4
3
2
1
0
CRC UNC 0 IDN 0 ABT T0N AMN
V
0
0
V
0
V
0
0
Table 128 Write DMA Ext Command (35h)

0
V
V
V
V
V
V
V
V
1

Command Block Input Registers
Register
7 6 5 4 3 2 1 0
Data Low
- - - - - - - Data High
- - - - - - - Error
...See Below...
Sector Count
LBA Low
LBA Mid
LBA High
Device
Status

HOB=0
HOB=1
HOB=0
HOB=1
HOB=0
HOB=1
HOB=0
HOB=1

V
V
V
V
V
V
-

- - - - - - V V V V
V V V V
V V V V
V V V V
V V V V
V V V V
- - - ...See Below...

Status Register
7
6
5
4
3
2
BSY RDY DF DSC DRQ COR
0
V
0
V
0

1
IDX
0

V
V
V
V
V
V
-

0
ERR
V

The Write DMA Ext command transfers one or more sectors of data from the host to the device,
then the data is written to the disk media.
The sectors of data are transferred through the Data Register 16 bits at a time.
The host initializes a slave-DMA channel prior to issuing the command. Data transfers are
qualified by DMARQ and are performed by the slave-DMA channel. The device issues only one
interrupt per command to indicate that data transfer has terminated and status is available.
If an uncorrectable error occurs, the write will be terminated at the failing sector
Output Parameters To The Device
The number of continuous sectors to be transferred low order, bits (7:0).
Sector Count Current
The number of continuous sectors to be transferred high order bits (15:8). If 0000h in
Sector Count Previous
the Sector Count register is specified, then 65,536 sectors will be transferred.
LBA (7:0).
LBA Low Current
LBA (31:24).
LBA Low Previous
LBA (15:8).
LBA Mid Current
LBA (39:32).
LBA Mid Previous
LBA (23:16).
LBA High Current
LBA (47:40).
LBA High Previous
Input Parameters From The Device
LBA (7:0) of the address of the first unrecoverable error.
LBA Low (HOB=0)
LBA (31:24) of the address of the first unrecoverable error.
LBA Low (HOB=1)
LBA (15:8) of the address of the first unrecoverable error.
LBA Mid (HOB=0)
LBA (39:32) of the address of the first unrecoverable error.
LBA Mid (HOB=1)
LBA (23:16) of the address of the first unrecoverable error.
LBA High (HOB=0)
LBA (47:40) of the address of the first unrecoverable error.
LBA High (HOB=1)

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14.45

Write DMA FUA Ext (3Dh)

5
V
V
V
V
V
V
V
V
1

4
V
V
V
V
V
V
V
V
1

3
V
V
V
V
V
V
V
V
1

2
V
V
V
V
V
V
V
V
1

1
V
V
V
V
V
V
V
V
0

Error Register
7
6
5
4
3
2
1
0
CRC UNC 0 IDN 0 ABT T0N AMN
V
0
0
V
0
V
0
0
Table 129 Write DMA FUA Ext Command (3Dh)

0
V
V
V
V
V
V
V
V
1

Command Block Input Registers
Register
7 6 5 4 3 2 1 0
Data Low
- - - - - - - Data High
- - - - - - - Error
...See Below...
Sector Count
LBA Low
LBA Mid
LBA High
Device
Status

HOB=0
HOB=1
HOB=0
HOB=1
HOB=0
HOB=1
HOB=0
HOB=1

V
V
V
V
V
V
-

- - - - - - V V V V
V V V V
V V V V
V V V V
V V V V
V V V V
- - - ...See Below...

Status Register
7
6
5
4
3
2
BSY RDY DF DSC DRQ COR
0
V
0
V
0

1
IDX
0

V
V
V
V
V
V
-

0
ERR
V

The Write DMA FUA Ext command transfers one or more sectors of data from the host to the
device, then the data is written to the disk media. This command provides the same function
as the Write DMA Ext command except that the transferred data shall be written to the media
before the ending status for this command is reported also when write caching is enabled.
The sectors of data are transferred through the Data Register 16 bits at a time.
The host initializes a slave-DMA channel prior to issuing the command. Data transfers are
qualified by DMARQ and are performed by the slave-DMA channel. The device issues only one
interrupt per command to indicate that data transfer has terminated and status is available.
If an uncorrectable error occurs, the write will be terminated at the failing sector
Output Parameters To The Device
The number of continuous sectors to be transferred low order, bits (7:0).
Sector Count Current
The number of continuous sectors to be transferred high order bits (15:8). If 0000h in
Sector Count Previous
the Sector Count register is specified, then 65,536 sectors will be transferred.
LBA (7:0).
LBA Low Current
LBA (31:24).
LBA Low Previous
LBA (15:8).
LBA Mid Current
LBA (39:32).
LBA Mid Previous
LBA (23:16).
LBA High Current
LBA (47:40).
LBA High Previous
Input Parameters From The Device
LBA (7:0) of the address of the first unrecoverable error.
LBA Low (HOB=0)
LBA (31:24) of the address of the first unrecoverable error.
LBA Low (HOB=1)
LBA (15:8) of the address of the first unrecoverable error.
LBA Mid (HOB=0)
LBA (39:32) of the address of the first unrecoverable error.
LBA Mid (HOB=1)
LBA (23:16) of the address of the first unrecoverable error.
LBA High (HOB=0)
LBA (47:40) of the address of the first unrecoverable error.
LBA High (HOB=1)

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14.46

Write FPDMA Queued (61h)

5
V
V
T
V
V
V
V
V
V
1

4
V
V
T
V
V
V
V
V
V
0

3
V
V
T
V
V
V
V
V
V
0

2
V
V
V
V
V
V
V
V
0

1
V
V
V
V
V
V
V
V
0

Error Register
7
6
5
4
3
2
1
0
CRC UNC 0 IDN 0 ABT T0N AMN
V
0
0
V
0
V
0
0
Table 130 Write FPDMA Queued Command (61h)

0
V
V
V
V
V
V
V
V
1

Command Block Input Registers
Register
7 6 5 4 3 2 1 0
Data Low
- - - - - - - Data High
- - - - - - - Error
...See Below...
Sector Count
LBA Low
LBA Mid
LBA High
Device
Status

HOB=0
HOB=1
HOB=0
HOB=1
HOB=0
HOB=1
HOB=0
HOB=1

V
V
V
V
V
V
-

- - - - - - V V V V
V V V V
V V V V
V V V V
V V V V
V V V V
- - - ...See Below...

Status Register
7
6
5
4
3
2
BSY RDY DF DSC DRQ COR
0
V
0
V
0

1
IDX
0

V
V
V
V
V
V
-

0
ERR
V

The Write FPDMA Queued command transfers one or more sectors of data from the host to the
device, then the data is written to the disk media.
If an uncorrectable error occurs, the write will be terminated at the failing sector
Output Parameters To The Device
The number of sectors to be transferred low order, bit (7:0)
Feature Current
The number of sectors to be transferred high order, bit (15:8)
Feature Previous
TAG value. It shall be assigned to be different from all other queued commands.
T
The value shall not exceed the maximum queue depth specified by the Word 75 of the
Identify Device information.
LBA (7:0).
LBA Low Current
LBA (31:24).
LBA Low Previous
LBA (15:8).
LBA Mid Current
LBA (39:32).
LBA Mid Previous
LBA (23:16).
LBA High Current
LBA (47:40).
LBA High Previous
FUA bit. When the FUA bit is set to 1, the completion status is indicated after the
F
transferred data are written to the media also when Write Cache is enabled. When the
FUA bit is set to 0, the completion status may be indicated before the transferred data
are written to the media successfully when Write Cache is enabled.
Priority bit. When the Priority bit is set to 1, the device attempts to provide better
P
quality of service for the command than normal priority commands.
Input Parameters From The Device
LBA (7:0) of the address of the first unrecoverable error.
LBA Low (HOB=0)
LBA (31:24) of the address of the first unrecoverable error.
LBA Low (HOB=1)
LBA (15:8) of the address of the first unrecoverable error.
LBA Mid (HOB=0)
LBA (39:32) of the address of the first unrecoverable error.
LBA Mid (HOB=1)
LBA (23:16) of the address of the first unrecoverable error.
LBA High (HOB=0)
LBA (47:40) of the address of the first unrecoverable error.
LBA High (HOB=1)
162/173

7K200 SATA OEM Specification

14.47

Write Log Ext (3Fh)

Command Block Output Registers
Register
7 6 5
Data Low
- - Data High
- - Feature
Current
- - Previous
- - Sector Count Current
V V V
Previous
V V V
LBA Low
Current
V V V
Previous
- - LBA Mid
Current
V V V
Previous
V V V
LBA High
Current
- - Previous
- - Device
- - Command
0 0 1
Error Register
7
6
5
4
3
2
CRC UNC 0 IDN 0 ABT
V
V
0
V
0
V
Table 131 Write Log Ext Command

4
V
V
V
V
V
1

3
V
V
V
V
V
1

2
V
V
V
V
V
1

1
V
V
V
V
V
1

1
0
T0N AMN
0
0

0
V
V
V
V
V
1

Command Block Input Registers
Register
7 6 5 4 3 2 1 0
Data Low
- - - - - - - Data High
- - - - - - - Error
...See Below...
Sector Count

HOB=0
HOB=1
HOB=0
HOB=1
HOB=0
HOB=1
HOB=0
HOB=1

- - - - - - LBA Low
- - - - - - LBA Mid
- - - - - - LBA High
- - - - - - Device
- - - Status
...See Below...
Status Register
7
6
5
4
3
2
1
BSY RDY DF DSC DRQ COR IDX
0
V
0
V
0
0

0
ERR
V

This command writes a specified number of 512 byte data sectors to the specific log. The device
shall interrupt for each DRQ block transferred.
Output Parameters To The Device
The number of sectors to be written to the specified log low
Sector Count Current
order, bits (7:0).
The number of sectors to be written to the specified log high
Sector Count Previous
orders, bits (15:8). If the number of sectors is greater than the
number indicated in the Log directory, which is available in Log
number zero, the device shall return command aborted. The log
transferred to the device shall be stored by the device starting at
the first sector in the specified log.
The log to be written as described in Table 110 Log sector
Sector Number Current
addresses definition. If the host attempts to write to a read only
log address, the device shall return command aborted.
The first sector of the log to be written low order, bits (7:0).
Cylinder Low Current
The first sector of the log to be written high order, bits (15:8)
Cylinder Low Previous
If the feature set associated with the log specified in the Sector Number register is not
supported or enabled, or if the values in the Sector Count, Sector Number or Cylinder Low
registers are invalid, the device shall return command aborted. If the host attempts to write to a
read only log address, the device shall return command aborted.

163/173

7K200 SATA OEM Specification

14.48

Write Multiple (C5h)

Command Block Output Registers
Register
7 6
Data
- Feature
- Sector Count
V V
LBA Low
V V
LBA Mid
V V
LBA High
V V
Device
- L

4
V
V
V
V
1 1 0 0

Command

7
6
CRC UNC

5
0

5
V
V
V
V
-

3
V
V
V
V
H

2
V
V
V
V
H

1
V
V
V
V
H

0
V
V
V
V
H

0 1 0 1

Error Register
4
3
2
1
IDN
0
ABT T0N

0
AM
N
0
0
0
V
0
V
0
0
Table 132 Write Multiple Command (C5h)

Command Block Input Registers
Register
7
Data
Error
Sector Count
V
LBA Low
V
LBA Mid
V
LBA High
V
Device
Status

0
V
V
V
V
H

...See Below...

7
6
BSY RDY
0

6 5 4 3 2 1
- - - - - ...See Below...
V V V V V V
V V V V V V
V V V V V V
V V V V V V
- - - H H H

5
DF
V

Status Register
4
3
2
1
0
DSC DRQ COR IDX ERR
V

The Write Multiple command transfers one or more sectors from the host to the device, then the
data is written to the disk media.
Command execution is identical to the Write Sectors command except that an interrupt is
generated for each block (as defined by the Set Multiple command) instead of for each sector.
The sectors are transferred through the Data Register 16 bits at a time.
Output Parameters To The Device
The number of continuous sectors to be transferred. If zero is specified, then 256 sectors
Sector Count
will be transferred.
The sector number of the first sector to be transferred. (L=0)
LBA Low
In LBA mode, this register contains LBA bits 0 - 7. (L=1)
The cylinder number of the first sector to be transferred. (L=0)
LBA High/Mid
In LBA mode, this register contains LBA bits 8 - 15 (Mid), 16 - 23 (High). (L=1)
The head number of the first sector to be transferred. (L=0)
H
In LBA mode, this register contains LBA bits 24 - 27. (L=1)
Input Parameters From The Device
The number of requested sectors not transferred. This will be zero, unless an
Sector Count
unrecoverable error occurs.
The sector number of the last transferred sector. (L=0)
LBA Low
In LBA mode, this register contains current LBA bits 0 - 7. (L=1)
The cylinder number of the last transferred sector. (L=0)
LBA High/Mid
In LBA mode, this register contains current LBA bits 8 - 15 (Mid), 16 - 23 (High).
(L=1)
The head number of the last transferred sector. (L=0)
H
In LBA mode, this register contains current LBA bits 24 - 27. (L=1)

164/173

7K200 SATA OEM Specification

14.49

Write Multiple Ext (39h)

5
V
V
V
V
V
V
V
V
1

4
V
V
V
V
V
V
V
V
1

3
V
V
V
V
V
V
V
V
1

2
V
V
V
V
V
V
V
V
0

1
V
V
V
V
V
V
V
V
0

Error Register
7
6
5
4
3
2
1
0
CRC UNC 0 IDN 0 ABT T0N AMN
0
0
0
V
0
V
0
0
Table 133 Write Multiple Ext Command (39h)

0
V
V
V
V
V
V
V
V
1

Command Block Input Registers
Register
7 6 5 4 3 2 1 0
Data Low
- - - - - - - Data High
- - - - - - - Error
...See Below...
Sector Count
LBA Low
LBA Mid
LBA High
Device
Status

HOB=0
HOB=1
HOB=0
HOB=1
HOB=0
HOB=1
HOB=0
HOB=1

V
V
V
V
V
V
-

- - - - - - V V V V
V V V V
V V V V
V V V V
V V V V
V V V V
- - - ...See Below...

Status Register
7
6
5
4
3
2
BSY RDY DF DSC DRQ COR
0
V
0
V
0

1
IDX
0

V
V
V
V
V
V
-

0
ERR
V

The Write Multiple Ext command transfers one or more sectors from the host to the device, then
the data is written to the disk media.
Command execution is identical to the Write Sector(s) Ext command except that an interrupt is
generated for each block (as defined by the Set Multiple command) instead of for each sector.
The sectors are transferred through the Data Register 16 bits at a time.
Output Parameters To The Device
The number of continuous sectors to be transferred low order, bits (7:0)
Sector Count Current
The number of continuous sectors to be transferred high order, bits (15:8). If 0000h in
Sector Count Previous
the Sector Count register is specified, then 65,536 sectors shall be transferred.
LBA (7:0).
LBA Low Current
LBA (31:24).
LBA Low Previous
LBA (15:8).
LBA Mid Current
LBA (39:32).
LBA Mid Previous
LBA (23:16).
LBA High Current
LBA (47:40).
LBA High Previous
Input Parameters From The Device
LBA (7:0) of the address of the first unrecoverable error.
LBA Low (HOB=0)
LBA (31:24) of the address of the first unrecoverable error.
LBA Low (HOB=1)
LBA (15:8) of the address of the first unrecoverable error.
LBA Mid (HOB=0)
LBA (39:32) of the address of the first unrecoverable error.
LBA Mid (HOB=1)
LBA (23:16) of the address of the first unrecoverable error.
LBA High (HOB=0)
LBA (47:40) of the address of the first unrecoverable error.
LBA High (HOB=1)

165/173

7K200 SATA OEM Specification

14.50

Write Multiple FUA Ext (CEh)

5
V
V
V
V
V
V
V
V
0

4
V
V
V
V
V
V
V
V
0

3
V
V
V
V
V
V
V
V
1

2
V
V
V
V
V
V
V
V
1

1
V
V
V
V
V
V
V
V
1

Error Register
7
6
5
4
3
2
1
0
CRC UNC 0 IDN 0 ABT T0N AMN
0
0
0
V
0
V
0
0
Table 134 Write Multiple FUA Ext Command (CEh)

0
V
V
V
V
V
V
V
V
0

Command Block Input Registers
Register
7 6 5 4 3 2 1 0
Data Low
- - - - - - - Data High
- - - - - - - Error
...See Below...
Sector Count
LBA Low
LBA Mid
LBA High
Device
Status

HOB=0
HOB=1
HOB=0
HOB=1
HOB=0
HOB=1
HOB=0
HOB=1

V
V
V
V
V
V
-

- - - - - - V V V V
V V V V
V V V V
V V V V
V V V V
V V V V
- - - ...See Below...

Status Register
7
6
5
4
3
2
BSY RDY DF DSC DRQ COR
0
V
0
V
0

1
IDX
0

V
V
V
V
V
V
-

0
ERR
V

The Write Multiple FUA Ext command transfers one or more sectors from the host to the device,
then the data is written to the disk media. This command provides the same function as the
Write Multiple Ext command except that the transferred data shall be written to the media
before the ending status for this command is reported also when write caching is enabled.
Output Parameters To The Device
The number of continuous sectors to be transferred low order, bits (7:0)
Sector Count Current
The number of continuous sectors to be transferred high order, bits (15:8). If 0000h in
Sector Count Previous
the Sector Count register is specified, then 65,536 sectors shall be transferred.
LBA (7:0).
LBA Low Current
LBA (31:24).
LBA Low Previous
LBA (15:8).
LBA Mid Current
LBA (39:32).
LBA Mid Previous
LBA (23:16).
LBA High Current
LBA (47:40).
LBA High Previous
Input Parameters From The Device
LBA (7:0) of the address of the first unrecoverable error.
LBA Low (HOB=0)
LBA (31:24) of the address of the first unrecoverable error.
LBA Low (HOB=1)
LBA (15:8) of the address of the first unrecoverable error.
LBA Mid (HOB=0)
LBA (39:32) of the address of the first unrecoverable error.
LBA Mid (HOB=1)
LBA (23:16) of the address of the first unrecoverable error.
LBA High (HOB=0)
LBA (47:40) of the address of the first unrecoverable error.
LBA High (HOB=1)

166/173

7K200 SATA OEM Specification

14.51

Write Sector(s) (30h/31h)

Command Block Output Registers
Register
7 6
Data
- Feature
- Sector Count
V V
LBA Low
V V
LBA Mid
V V
LBA High
V V
Device
- L
Command
0 0

7
6
CRC UNC

5
0

5
V
V
V
V
1

4
V
V
V
V
1

3
V
V
V
V
H
0

2
V
V
V
V
H
0

Error Register
4
3
2
1
IDN
0
ABT T0N

0
0
0
V
0
V
0
Table 135 Write Sector(s) Command (30h/31h)

1
V
V
V
V
H
0

0
V
V
V
V
H
R

0
AM
N
0

Command Block Input Registers
Register
7
Data
Error
Sector Count
V
LBA Low
V
LBA Mid
V
LBA High
V
Device
Status

7
6
BSY RDY
0

6 5 4 3 2 1
- - - - - ...See Below...
V V V V V V
V V V V V V
V V V V V V
V V V V V V
- - - H H H
...See Below...

0
V
V
V
V
H

Status Register
5
4
3
2
1
0
DF DSC DRQ COR IDX ERR
V

The Write Sector(s) command transfers one or more sectors from the host to the device, then the
data is written to the disk media.
The sectors are transferred through the Data Register 16 bits at a time.
If an uncorrectable error occurs, the write will be terminated at the failing sector, when the
auto reassign function is disable.
Output Parameters To The Device
The number of continuous sectors to be transferred. If zero is specified, then 256 sectors
Sector Count
will be transferred.
The sector number of the first sector to be transferred. (L=0)
LBA Low
In LBA mode, this register contains LBA bits 0 - 7. (L=1)
The cylinder number of the first sector to be transferred. (L=0)
LBA High/Mid
In LBA mode, this register contains LBA bits 8 - 15 (Mid), 16 - 23 (High). (L=1)
The head number of the first sector to be transferred. (L=0)
H
In LBA mode, this register contains LBA bits 24 - 27. (L=1)
The retry bit, but this bit is ignored.
R
Input Parameters From The Device
Sector Count
The number of requested sectors not transferred. This will be zero, unless
an unrecoverable error occurs.
LBA Low
LBA High/Mid

The sector number of the last transferred sector. (L=0)
In LBA mode, this register contains current LBA bits 0 - 7. (L=1)
The cylinder number of the last transferred sector. (L=0)
In LBA mode, this register contains current LBA bits 8 - 15 (Mid), 16 - 23 (High).
(L=1)
The head number of the last transferred sector. (L=0)In LBA mode, this register
contains current LBA bits 24 - 27. (L=1)

167/173

7K200 SATA OEM Specification

14.52

Write Sector(s) Ext (34h)

5
V
V
V
V
V
V
V
V
1

4
V
V
V
V
V
V
V
V
1

3
V
V
V
V
V
V
V
V
0

2
V
V
V
V
V
V
V
V
1

1
V
V
V
V
V
V
V
V
0

Error Register
7
6
5
4
3
2
1
0
CRC UNC 0 IDN 0 ABT T0N AMN
0
0
0
V
0
V
0
0
Table 136 Write Sector(s) Ext Command (34h)

0
V
V
V
V
V
V
V
V
0

Command Block Input Registers
Register
7 6 5 4 3 2 1 0
Data Low
- - - - - - - Data High
- - - - - - - Error
...See Below...
Sector Count
LBA Low
LBA Mid
LBA High
Device
Status

HOB=0
HOB=1
HOB=0
HOB=1
HOB=0
HOB=1
HOB=0
HOB=1

V
V
V
V
V
V
-

- - - - - - V V V V
V V V V
V V V V
V V V V
V V V V
V V V V
- - - ...See Below...

Status Register
7
6
5
4
3
2
BSY RDY DF DSC DRQ COR
0
V
0
V
0

1
IDX
0

V
V
V
V
V
V
-

0
ERR
V

The Write Sector(s) Ext command transfers one or more sectors from the host to the device,
then the data is written to the disk media.
The sectors are transferred through the Data Register 16 bits at a time.
If an uncorrectable error occurs, the write will be terminated at the failing sector.
Output Parameters To The Device
The number of continuous sectors to be transferred low order, bits (7:0).
Sector Count Current
The number of continuous sectors to be transferred high order bits (15:8). If 0000h in
Sector Count Previous
the Sector Count register is specified, then 65,536 sectors will be transferred.
LBA (7:0).
LBA Low Current
LBA (31:24).
LBA Low Previous
LBA (15:8).
LBA Mid Current
LBA (39:32).
LBA Mid Previous
LBA (23:16).
LBA High Current
LBA (47:40).
LBA High Previous
Input Parameters From The Device
LBA (7:0) of the address of the first unrecoverable error.
LBA Low (HOB=0)
LBA (31:24) of the address of the first unrecoverable error.
LBA Low (HOB=1)
LBA (15:8) of the address of the first unrecoverable error.
LBA Mid (HOB=0)
LBA (39:32) of the address of the first unrecoverable error.
LBA Mid (HOB=1)
LBA (23:16) of the address of the first unrecoverable error.
LBA High (HOB=0)
LBA (47:40) of the address of the first unrecoverable error.
LBA High (HOB=1)

168/173

7K200 SATA OEM Specification

14.53

Write Uncorrectable Ext (45h)

5
V
V
V
V
V
V
V
V
0

4
V
V
V
V
V
V
V
V
0

3
V
V
V
V
V
V
V
V
0

2
V
V
V
V
V
V
V
V
1

1
V
V
V
V
V
V
V
V
0

Error Register
7
6
5
4
3
2
1
0
CRC UNC 0 IDN 0 ABT T0N AMN
0
0
0
V
0
V
0
0
Table 137 Write Uncorrectable Ext Command (45h)

0
V
V
V
V
V
V
V
V
1

Command Block Input Registers
Register
7 6 5 4 3 2 1 0
Data Low
- - - - - - - Data High
- - - - - - - Error
...See Below...
Sector Count
LBA Low
LBA Mid
LBA High
Device
Status

HOB=0
HOB=1
HOB=0
HOB=1
HOB=0
HOB=1
HOB=0
HOB=1

V
V
V
V
V
V
-

- - - - - - V V V V
V V V V
V V V V
V V V V
V V V V
V V V V
- - - ...See Below...

Status Register
7
6
5
4
3
2
BSY RDY DF DSC DRQ COR
0
V
0
V
0

1
IDX
0

V
V
V
V
V
V
-

0
ERR
V

The Write Uncorrectable Ext command is used to cause the device to report an uncorrectable
error when the target sector is subsequently read.
When the feature field contains a value of 5xh, the Write Uncorrectable Ext command causes
the device to indicate a failure when reads to any of the sectors that are contained in specified
sectors. Theses sectors are referred to as “pseudo uncorrectable” sectors. In this case
whenever a pseudo uncorrectable sector is accessed via a read command, the device performs
normal error recovery and then set the UNC and ERR bits to indicate she sector is bad.
When the feature field contains a value of Axh, the Write Uncorrectable Ext command causes
the device to flag the specified sector as “flagged uncorrectable”. Flagging a logical sector as
uncorrectable causes the device to indicate a failure when reads to specified sectors are
performed. These sectors are referred to as “flagged uncorrectable” sectors. In this case
whenever a “flagged uncorrectable” sector is accessed via a read command, the device sets the
UNC and ERR bits without normal error recovery to indicate the sector is bad.
If the Uncorrectable options are set to A5h or 55h, then sectors that have been made pseudo
uncorrectable are listed as failed in the standard error logs when read back. If the
Uncorrectable options are set to 5Ah or AAh, then the reading of pseudo uncorrectable sectors
are not logged as an error in any standardized error logs.
The pseudo uncorrectable or flagged uncorrectable status of a sector remains through a power
cycle.
If an uncorrectable error occurs, the write will be terminated at the failing sector.
Output Parameters To The Device
Uncorrectable options
Feature Current
55h : Create a pseudo uncorrectable error with logging
5Ah: Create a pseudo uncorrectable error without logging
A5h: Create a flagged error with logging
AAh: Create a flagged error without logging
Other: Reserved (command is aborted)
The number of continuous sectors to be marked low order, bits (7:0).
Sector Count Current
169/173

7K200 SATA OEM Specification
The number of continuous sectors to be marked high order bits (15:8). If 0000h in the
Sector Count Previous
Sector Count register is specified, then 65,536 sectors will be transferred.
LBA (7:0).
LBA Low Current
LBA (31:24).
LBA Low Previous
LBA (15:8).
LBA Mid Current
LBA (39:32).
LBA Mid Previous
LBA (23:16).
LBA High Current
LBA
(47:40).
LBA High Previous
Input Parameters From The Device
LBA (7:0) of the address of the first unrecoverable error.
LBA Low (HOB=0)
LBA (31:24) of the address of the first unrecoverable error.
LBA Low (HOB=1)
LBA
(15:8) of the address of the first unrecoverable error.
LBA Mid (HOB=0)
LBA
(39:32) of the address of the first unrecoverable error.
LBA Mid (HOB=1)
LBA
(23:16) of the address of the first unrecoverable error.
LBA High (HOB=0)
LBA
(47:40) of the address of the first unrecoverable error.
LBA High (HOB=1)

170/173

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15 Timings
The timing of BSY and DRQ in Status Register are shown in the following table.
The other timings are described in Functional Specification part.
FUNCTION
INTERVAL
START
STOP
TIMEOUT
Device Ready
Power On and COMRESET
Status Register
31 sec
Power On and After Power On
BSY=0 and RDY=1
COMRESET
and sends a Register
FIS to the host.
Software
Device Busy
Device Control Register
Status Register
400 ns
Reset
After Software Reset
RST=1 and sends a Register
BSY=1
FIS to the Device.
Device Ready
Device Control Register
Status Register
31 sec
After Software Reset
RST=0 and sends a Register
BSY=0 and RDY=1
FIS to the Device. After
and requests to send a
RST=1 and sends a Register
Register FIS to the host.
FIS to the Device.
COMRESET Device Ready
COMRESET Signal
Status Register
31 sec
After COMRESET
Asserted
BSY=0 and RDY=1
and sends a Register
FIS to the Host.
Data In
Device Busy
Sets proper values in the
Status Register
400 ns
After a Register FIS to issue a registers and sends a Register BSY=1
Command
command
FIS
PIO SETUP FIS for data-in Status Register
Status Register
30 sec
transfer
BSY=1
BSY=0 and DRQ=1
and sends a PIO
SETUP FIS to the host.
Device Busy
A PIO SETUP FIS is
Status Register
10 us
After Data Transfer In
transferred to the host.
BSY=1
Data Out
Device Busy
Sets proper values in the
Status Register
400 ns
Command
After a Register FIS to issue a registers and sends a Register BSY=1
command
FIS
Device Busy
Sends a Data FIS to the device. Status Register
5 us
After Data Transfer Out
BSY=1
30 sec
PIO SETUP FIS for data-out Status Register
Status Register
transfer
BSY=1
BSY=0 and RDY=1
(Note.1)
and sends a PIO
SETUP FIS to the host.
Non-Data
Device Busy
Sets proper values in the
Status Register
400 ns
Command
After a Register FIS to issue a registers and sends a Register BSY=1
command
FIS
A Register FIS to report
Status Register BSY=1
Sets the status of the
30 sec
Command Complete
command to the Status
(Note.2)
Register and sends a
Register FIS to the host
DMA Data
Device Busy
Sets proper values in the
Status Register
400 ns
Transfer
After a Register FIS to issue a registers and sends a Register BSY=1
Command
command
FIS
Table 138 Timeout Values
Command category is referred to “13
Command Protocol” on page 70.
The abbreviations “ns”, “us”, “ms” and “sec” mean nanoseconds, microseconds, milliseconds and
seconds, respectively.
We recommend that the host system executes Soft reset and then retry to issue the command if
the host system timeout would occur for the device.
For SECURITY ERASE UNIT command, the execution time is referred to “14.28 Security
(Note.1)
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(Note.2)

7K200 SATA OEM Specification
Erase Unit (F4h)” on Page 125.
FORMAT UNIT command, the execution time is referred to “14.7 Format Unit (F7h: Vendor
Specific)” on Page 87.

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7K200 SATA OEM Specification

© Copyright Hitachi Global Storage Technologies
Hitachi Global Storage Technologies
5600 Cottle Road
San Jose, CA 95193
Produced in the United States
05/07
All rights reserved Travelstar™ is a trademark of
Hitachi Global Storage Technologies.
Microsoft, Windows XP, and Windows are trademarks
of Microsoft Corporation in the United States, other
countries, or both.
Other product names are trademarks or registered
trademarks of their respective companies.
References in this publication to Hitachi Global
Storage Technologies products, programs or services
do not imply that Hitachi Global Storage Technologies
intends to make these available in all countries in
which Hitachi Global Storage Technologies operates.
Product information is provided for information purposes only and does not constitute a warranty.
Information is true as of the date of publication and is
subject to change. Actual results may vary.
This publication is for general guidance only. Photographs may show design models.
10 May 2007

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