Honeywell ALA-52B2 Radio Altimeter User Manual CMM ALA 52B Radio Altimeter 012 0823 001

Honeywell International Inc. Radio Altimeter CMM ALA 52B Radio Altimeter 012 0823 001

Users Manual

COMPONENT MAINTENANCE MANUALPart No. 066-50007DESCRIPTION AND OPERATION1. Description (TASK 34-42-37-870-801-A01)A. General (Subtask 34-42-37-870-001-A01)(1) This section contains descriptive information covering the ALA-52B Radio Altimeter(ALA-52B). The ALA-52B is shown in Figure 1 (GRAPHIC 34-42-37-99B-802-A01).Figure 1. (Sheet 1 of 1) ALA-52B Radio Altimeter (GRAPHIC 34-42-37-99B-802-A01)EFFECTIVITYALL 34-42-37 Page 110 Oct 2007© Honeywell International Inc. Do not copy without express permission of Honeywell.
COMPONENT MAINTENANCE MANUALPart No. 066-50007(2) The ALA-52B is part of the Honeywell ALA-52B Radio Altimeter System. TheALA-52B is a lightweight, solid-state, digital airborne altimeter designed to provideaccurate, digital height measurements above terrain during aircraft approach, landing,and climb-out phases. It is a low-range altimeter that incorporates two different andindependent microprocessors, one of which performs the primary altitude computationwhile the second independently verifies the computation by comparison.2. Configuration (TASK 34-42-37-870-802-A01)A. Overview (Subtask 34-42-37-870-002-A01)(1) Table 1 lists the features contained in the ALA-52B. Table 2 contains a brief descriptionof each feature.Table 1. ALA-52B ConfigurationsFeaturesHoneywellPart Number066-50007 Basic Unit Fault Memory CMCCompatible MaximumWeight (Lbs/Kg)-1111 XXX8.6/3,9Table 2. ALA-52B FeaturesFeature DescriptionBasic Unit Airborne solid-state radio altimeter that incorporatestwo different and independent microprocessors, oneof which performs the primary altitude computationwhile the second independently verifies thecomputation by comparison. The altitude informationis supplied to the AFCS and height displays on theinstrument panel. The front panel contains LEDsthat indicate the operating status of the unit. Thefront panel also provides a user interface for testand troubleshooting, including a test button and anRS-232C 25-pin “D” connector. The RS-232 frontpanel connector is used for testing the ALA-52Bthrough a front panel adapter.Fault Memory A nonvolatile, single-chip fault memory that allowsthe recording of faults associated with a particularflightleg. Sixty-four flight legs are available with eachflight leg made up of a flightleg information headercontaining a fault record section for recording tenairborne faults and three ground faults. When allflight legs are used, the oldest flight leg is reused.CMC Interface The ALA-52B interfaces fault memory and BITEdata between radio altimeter and line maintenanceCMC for the purpose of extracting maintenanceinformation and initiating tests. Designed to conformwith ARINC 429 interfaces, and ARINC 604.EFFECTIVITYALL 34-42-37 Page 210 Oct 2007© Honeywell International Inc. Do not copy without express permission of Honeywell.
COMPONENT MAINTENANCE MANUALPart No. 066-500073. Leading Particulars (TASK 34-42-37-870-803-A01)A. Unit Specifications (Subtask 34-42-37-870-003-A01)(1) Table 3 lists the leading particulars for the ALA-52B.Table 3. ALA-52B Leading ParticularsCharacteristics DescriptionForm Factor ARINC6003MCUDimensions 14.04 in. (35,66 cm) long by 3.56 in. (9,04 cm) wide by 7.64 in.(19,41 cm) highWeight 8.6lb(3,9Kg)maximumPower Requirements 30W, +28 V dcTemperature:• Operating 5to+158 F(-15to+70 C)•Storage -67to+185 F(-55to+85 C)Cooling ARINC 600 forced airHumidity Zero to 95% relative humidity at 122 F(50 ºC)Altitude 50,000 ft (15,240 m) above mean sea levelWarm-up period Stable operation within 6 secondsFrequency Range 4.235 to 4.365 GHzTransmit Power +26 dBm (nominal at antenna port)Operating Range of Altitudes -20 to 5000 ft (-6,1 to 1524 m)Accuracy ±1.5 ft (0,46 m) or 2%, whichever is greaterData Outputs ARINC 429 range and CMC interfaceAircraft Installation Delays 40, 57, 80 ftPitch Limits ±20ºRoll Limits ±40ºDoppler Error Compensated using dual slope FM rampSelf-Test Automatic in-flight, manual from discrete, ARINC 429, or front panelIntegrity Monitoring Continuous self-monitoring establishes operational status at allaltitudesFault Reporting Conforms to Boeing 777 formatsB. Environmental Certification (Subtask 34-42-37-870-004-A01)(1) The ALA-52B meets the environmental conditions of the RTCA documentnumber DO-160E, Environmental Conditions and Test Procedures for AirlineElectronic/Electrical Equipment and Instruments. Refer to Table 4.EFFECTIVITYALL 34-42-37 Page 310 Oct 2007© Honeywell International Inc. Do not copy without express permission of Honeywell.
COMPONENT MAINTENANCE MANUALPart No. 066-50007Table 4. Environmental Certification Categories of ALA-52BTest CategoryTemperature and Altitude A2/B2In-Flight Loss of Cooling ZTemperature Variation BHumidity AOperational Shocks and Crash Safety BVibration SVibration Curves BExplosion Atmosphere XWaterproofness XFluids Susceptibility XSand and Dust XFungus Resistance XSalt Spray XMagnetic Effect APower Input AVoltage Spike AAudio Frequency Conducted Susceptibility - PowerInputs RInduced Signal Susceptibility ZCRadio Frequency Susceptibility (Radiated andConducted) WEEmission of Radio Frequency Energy MLightning Induced Transient Susceptibility ZZZZZLightning Direct Effects XIcing XElectrostatic Discharge AFire, Flammability CNOTE: Category X = Test not applicable.EFFECTIVITYALL 34-42-37 Page 410 Oct 2007© Honeywell International Inc. Do not copy without express permission of Honeywell.
COMPONENT MAINTENANCE MANUALPart No. 066-500074. Brief Description of Equipment (TASK 34-42-37-870-804-A01)A. Mechanical Description (Subtask 34-42-37-870-005-A01)(1) The ALA-52B is contained in a standard ARINC Characteristic 600, 3-MCU case withside panels. Electrical connection to the aircraft wiring is made through an ARINC600, series number one, multiple-section connector centered vertically.(2) Table 5 lists all modules and assemblies in the unit. Figure 2 (GRAPHIC34-42-37-99B-803-A01) shows the location of the modules and assemblies.Table 5. Module and Assembly DesignationsModule/Board Honeywell PartNumber ReferenceSeries ConnectorsFinal Assembly 700-1796-001 --- W4,W6,W8,W11,W20,W21• Rear Interconnect CCA 722-4667-002 1200 J1001, J1212, J1214, W2,W23Main Processor CCA 722-4703-002 2000 J2001, J2002, J2003, J2005thru J2012Power Supply Module 710-0366-001 --- ---• Input CCA 722-4767-001 3100 P3102, W6, J3108• Output CCA 722-4577-005 3300 J3302, P3310, P3313Front Panel 700-1784-001• LED CCA 722-4692-002 4000 J4001, J4002, J4003, W5, W9Monitor Processor Module 300-90234-0502 6000 J6018, J6043, J6044, J6045RF Assembly727-0026-001 9000 W4, W6, W7, W20, W21• RF Module CCA 722-4656-005 9000 J9039, P9033EFFECTIVITYALL 34-42-37 Page 510 Oct 2007© Honeywell International Inc. Do not copy without express permission of Honeywell.
COMPONENT MAINTENANCE MANUALPart No. 066-50007Blank PageEFFECTIVITYALL 34-42-37 Page 610 Oct 2007© Honeywell International Inc. Do not copy without express permission of Honeywell.
COMPONENT MAINTENANCE MANUALPart No. 066-50007Figure 2. (Sheet 1 of 1) Module and Assembly Location (GRAPHIC 34-42-37-99B-803-A01)EFFECTIVITYALL 34-42-37 Pages 7/810 Oct 2007© Honeywell International Inc. Do not copy without express permission of Honeywell.
COMPONENT MAINTENANCE MANUALPart No. 066-50007B. Electrical Description (Subtask 34-42-37-870-006-A01)(1) Figure 3 (GRAPHIC 34-42-37-99B-804-A01) shows the ALA-52B interconnections inthe aircraft. Antenna cabling is determined by the setting of the AID strap pins in themiddle plug. The round trip delay from the ALA-52B transmitter port to the receiver portis set to the AID value for the return signal that corresponds to a reading of zero feet.(2) The middle plug also contains the ARINC 429 altitude bus outputs that connect to theAFCS, cockpit altitude indicators. Data recording equipment in the form of a flash cardis available for in-flight test, though normally it is not required. For most installations,ARINC 429 bus number 1 is connected to the Flight Management Control Computer,and ARINC 429 bus number 2 is connected to the altitude indicators on the instrumentpanel. ARINC 429 I/O is also provided for interface with the CMC.Figure 3. (Sheet 1 of 1) ALA-52B Block Diagram (GRAPHIC 34-42-37-99B-804-A01)(3) Besides the AID strap pins, system select strap pins are provided to designate theinstalled equipment as unit number 1, 2, or 3. The antenna monitor strap pin enablesantenna monitoring, and the AFCS data program strap pins set the mode of operationof the ARINC 429 altitude buses in case an ALA-52B failure is detected.(4) Discretes from other systems provide test activation, the inhibiting of test, andair/ground indication.(5) An RS-232 port on the ALA-52B front panel (not shown) provides an attachment for ahand-held tester for additional ramp test information, and shop test interface.EFFECTIVITYALL 34-42-37 Page 910 Oct 2007© Honeywell International Inc. Do not copy without express permission of Honeywell.
COMPONENT MAINTENANCE MANUALPart No. 066-500075. Theory of Operation (TASK 34-42-37-870-805-A01)A. Overall Operation (Subtask 34-42-37-870-007-A01)(1) The basic objective of the ALA-52B is to provide accurate height above the groundterrain with a high degree of integrity during the approach, landing, and climbout phases of aircraft operation. This is accomplished by transmitting a frequencymodulated continuous signal to the ground.(2) The frequency modulation is a linear dual slope ramp. During the time required for thetransmitted signal to bounce off the ground and return to the aircraft, the transmittedsignal has changed frequency. When the transmitted signal is mixed with the returnsignal bounced up from the ground, a baseband signal is produced at a frequency thatrepresents the difference between the transmitted and returned signal frequencies.Since this difference frequency is proportional to the delay between the transmittedand received signals, it is also proportional to the altitude of the aircraft.(3) The difference frequency signal is amplified sufficiently and applied to two independentDSPs. The amplifier gain increases with frequency to compensate for attenuation dueto increased range. The DSPs perform FFT and extract the lowest peak frequency.This process is repeated periodically. The results are averaged and verified in themicroprocessors before being supplied to the 429 altitude data buses.(4) The verified digital altitude information is then routed to the peripheral equipmentwhere it is further processed for pilot display, ground proximity warning, and AFCSusage.B. Block Diagram (Subtask 34-42-37-870-008-A01)(1) RF Module(a) The RF module, controlled by the main processor, transmits and receives thealtimeter signal. BITE circuitry is included to both test and continuously monitorthe RF module functions.(b) The process of generating a transmission is driven by a VCO based PLL that iscontrolled by a DDS. The transmitter chain supplies the receiver LO as well asthe required input for the calibration circuitry. The transmitted signal is radiatedfrom the transmit antenna located on the underside of the aircraft.(c) The transmitted signal, after bouncing off the ground below the aircraft, iscollected by the receive antenna.(d) A pair of RF switches are provided to channel the calibrated 300-foot delayelement signal through the receiver during self-test. The self-test operationperforms a full transmitter and receiver check. The self-test operation is activatedmanually by the pilot or automatically when the ALA-52B is acquiring a signal.(e) The received signal is mixed with the part of transmitted signal, producing adifference frequency signal that is amplified and fed to an A/D converter onthe main processor module.EFFECTIVITYALL 34-42-37 Page 1010 Oct 2007© Honeywell International Inc. Do not copy without express permission of Honeywell.
COMPONENT MAINTENANCE MANUALPart No. 066-50007(2) Main Processor Module(a) The main processor module controls the radio altimeter operation, performssignal processing of the difference frequency and test signals, and controls theaircraft interfaces and the data displayed on the front panel.(b) The main processor provides all the control signals to generate an up-down linearramped frequency-modulated carrier wave output, determines the mode ofoperation, and provides all RF control signals. It also processes the differencefrequency signals digitally. The return signal and test signals are converted todigital data streams using an A/D converter. In addition, the main processormodule performs BITE, I/O, flash card interface, and monitor processor moduleinterface functions.(c) The main processor module is divided into three major sections: the DSP section,the 486 CPU microprocessor section, and the I/O section.(d) When replacing the main processor module, refer to the Alignment Procedure,in the TESTING AND FAULT ISOLATION (PGBLK 34-42-37-1000) section andthe SW Data Recording and Loading in the REPAIR (PGBLK 34-42-37-6000)section of this manual.1DSP SectionaThe DSP section is used to process the analog outputs from the RFmodule and to generate some of the control signals to the RF modulefor transmit modulation, automatic gain control, and test signals. Thedifference frequency signal from the RF module is digitized using a12-bit A/D converter. The A/D converter is also used to monitor signalsfrom the BITE test points on the RF module and the power supplyvoltages. The digitized data from the A/D converter is stored in a FIFOmemory device which is accessed by the DSP. The DSP processes thedifference frequency and calibration frequency into altitude information.Data is exchanged with the CPU section through a dual-port RAM,providing maximum throughput of both processors.2CPU SectionaThe CPU section does frame-to-frame processing of the altitude datafrom the DSP section providing the resulting altitude to the I/O section.The microprocessor in the CPU section controls all major functionsof the radio altimeter. Programmable logic devices serve as themicroprocessor controller and provide the interfaces to the memorydevices (boot routine, program, fault, and data), the data recorder/dataloader flash card, and the front panel display driver.3I/O SectionaThe I/O section provides the two ARINC 429 altitude outputs as well asARINC 429 interfaces with other aircraft systems including the CMC. Alldiscrete inputs external to the radio altimeter are processed by the I/Osection. The I/O section also generates the external discrete outputs,which are buffered to prevent damage to the processor circuitry. TheEFFECTIVITYALL 34-42-37 Page 1110 Oct 2007© Honeywell International Inc. Do not copy without express permission of Honeywell.
COMPONENT MAINTENANCE MANUALPart No. 066-50007I/O section also contains an RS-232C production test interface. Thistest interface is also used to update serial number, part number andconfiguration memory as applicable, utilizing a stand-alone PTM toolor integrated PTM tool in the Quantum Line Tester, when the mainprocessor module is replaced.(3) Monitor Processor Module(a) The monitor processor module provides a second signal processing path using aDSP. The DSP processes the received signal and calibration signal supplied indigital form from the Main Processor A/D converter. Also present are a clock, anARINC 429 receiver/selector, and static memory.(b) The primary function of the monitor processor module is to provide the ALA-52Bwith the integrity that permits Category III operations by acting as an independentmonitor for the main processor altitude computations.(4) Power Supply Module(a) The power supply module is a self-contained, high-efficiency, switching powersupply that converts the 28 V dc aircraft power into the required +5 V dc,+12 Vdc, and -12 V dc, operating voltages. A power-down interrupt signal providesadvanced notice of a power loss allowing the processors to temporarily retaintheir status.(5) Rear Interconnect Module(a) The Rear Interconnect module provides interface between the ARINC connector,the main processor, and the power supply modules. Lightning proctection for I/Osignals is provided on the Rear Interconnect.(6) Display Data Module(a) The display data module is mounted behind the front panel and provides aninterface to an operator through LEDs, which are visible from the front of theALA-52B. In addition to the LEDs, the module has a pushbutton switch and aconnector.(b) The connector is used for testing the ALA-52B through a compatible test set ortest panel.(7) Memory Card Interface Connector(a) The ALA-52B ALA transceiver is provided with a connector for a PCMCIA flashcard for programming the unit at the factory or service shop.6. Detailed Theory of Operation (TASK 34-42-37-870-806-A01)A. General (Subtask 34-42-37-870-009-A01)(1) See the appropriate schematic for the ALA-52B Radio Altimeter subassembliesdescribed in this section. All electrical signals are shown in uppercase characters.If the signal does not contain such a suffix, then the signal is generally a dual-statesignal such as a clock or data bus.(2) There are six subassemblies of the ALA-52B Radio Altimeter described in thissection. They are:EFFECTIVITYALL 34-42-37 Page 1210 Oct 2007© Honeywell International Inc. Do not copy without express permission of Honeywell.
COMPONENT MAINTENANCE MANUALPart No. 066-50007• RF module• Main processor module• Monitor processor module• Power supply assembly• Rear interconnect module• Front panel module.B. RF Module (Subtask 34-42-37-870-010-A01)(1) General(a) The RF module transmits and receives FM modulated C-Band signals that areused to determine the altitude above the ground. When the transmitted signal ismixed with the return signal bounced up from the ground, a baseband signal isproduced at a frequency that represents the difference between the transmittedand return signal frequencies. The baseband signal frequency is directlyproportional to the altitude above the ground. This analog baseband signal is theprimary output from the RF Module. A simplified block diagram of the RF circuitryis shown in Figure 4 (GRAPHIC 34-42-37-99B-805-A01)1The transmitted signal, centered at 4.3 gigahertz with a maximum possiblespan of +/-100 megahertz is radiated from the transmit antenna locatedon the underside of the aircraft, and is subsequently (after bouncing offthe ground) collected by the receive antenna. A directional coupler picksoff some of the transmit signal which is mixed with the received signal,producing a difference signal that is amplified, filtered and fed to ananalog-to-digital converter on the Main Processor module.2BITE circuitry is also included to both test and continuously monitor theRF module functions. A portion of the transmit signal is also fed into abulk acoustic wave device that provides a reflected signal calibrated to atime delay equivalent to 300 feet (0.616usec). Cal mixer extracts a signalcorresponding to the difference frequency between transmit and delayelement signals. The difference frequency signal is fed through a multiplexerto the A/D converter on the Main Processor board for calibration andself-test purposes3The PLD receives control signals from the DSP of the Processor Module anddirects them to appropriate circuitry on the RF module. A major function ofthis PLD is to control the DDS which provides a nearly ideal linear frequencysweep as a reference signal to the PLL within the transmitter chain.EFFECTIVITYALL 34-42-37 Page 1310 Oct 2007© Honeywell International Inc. Do not copy without express permission of Honeywell.
COMPONENT MAINTENANCE MANUALPart No. 066-50007Blank PageEFFECTIVITYALL 34-42-37 Page 1410 Oct 2007© Honeywell International Inc. Do not copy without express permission of Honeywell.
COMPONENT MAINTENANCE MANUALPart No. 066-50007Figure 4. (Sheet 1 of 1) RF Module Block Diagram (GRAPHIC 34-42-37-99B-805-A01)EFFECTIVITYALL 34-42-37 Pages 15/1610 Oct 2007© Honeywell International Inc. Do not copy without express permission of Honeywell.
COMPONENT MAINTENANCE MANUALPart No. 066-50007(2) Transmitter Chain(a) The transmitter chain is driven by a VCO based PLL that is controlled by a DDS.The transmitter chain supplies the receiver LO as well as the required input forthe calibration circuitry. The DDS is programmed by the PLD which is controlledby the Processor Module. A second DDS, called the monitor DDS is driven withthe same frequency set-up as the main DDS in order to provide a comparisonreference to the main DDS. The lock-detect signals from the compared DDSsand the PLL are used by the PLD to monitor the failure modes of the DDSs andthe transmitter chain.1Reference OscillatoraThe transistor based oscillator is powered by a 128 megahertz singletone crystal, Y1 and amplified by a X3 multiplier, Q5 to 384 megahertz.The 384 megahertz signal is filtered by a comb-line filter and amplifiedby a gain block, U14 and filtered again before providing the clock signalto the DDSs (U18, U32) and an LO signal to the IF mixer (U24). Two 3decibel splitters are employed to split the signal into three outputs, twowith equal amplitude and phase at 0 dBm and one with 3 dBm. The 0dBm signals are used to reference the DDSs(DDS1-REF, DDS2-REF).3 dBm signal is used as IF_LO signal.2DDSaBoth of the DDSs (U18, U32) are driven by the PLD (U512) to generatea frequency sweep between 82.66 megahertz to 104.88 megahertz(approximate maximum sweep) with the external reference clock 384megahertz. The main DDS (U32) output is feeding the IF mixer as wellas the PLD where it is compared with that from the monitor DDS.bThe linear frequency ramp generator U32 includes an on-chipcomparator. The comparator signals are square waves. The bandwidthis greater than 200 megahertz and has a common-mode input range of1.3 volts to 1.8 volts. This signal helps eliminate phase noise and jitter.cThe linear frequency ramp generator U32 output frequency range is82.66 megahertz to 104.88 megahertz. The DDS frequency sweepoutput (DDS_OUT) on U32-20 and -21 is routed through, transformerT3, a 120 megahertz low pass filter and a 3 decibel coupler tomixer U24. The signal from the ramp generator is mixed with the384 megahertz IF signal so that the linear frequency modulation istranslated up in frequency to 466.66 megahertz to 488.88 megahertz.These frequencies correspond to 4.200 gigahertz and 4.400 gigahertzdivided by 9 in the PLL circuit.3IF Mixer:aThe DDS_OUT signal and the IF_LO signal are routed to IF mixer U24.The output on U24-4 has a frequency range of 466.6 megahertz –488.8 megahertz(upper sideband). The output of U24 is routed throughan amplifier U27 and a 477 megahertz bandpass filter to PFD U33-3.EFFECTIVITYALL 34-42-37 Page 1710 Oct 2007© Honeywell International Inc. Do not copy without express permission of Honeywell.
COMPONENT MAINTENANCE MANUALPart No. 066-500074PLLaThe PLL consists of PFD (U33), loop filter (U28), VCO (G1), digitalattenuator(U20), preamp (U19), power amplifier (U12) and twosuccessive divide by 3 frequency dividers (U21, U25) for a totalfrequency division by 9. The power amplifiers and the digital attenuatorare included in the PLL in order to improve the phase linearity of theoverall transmitter. The loop bandwidth is approximately 1 megahertzwhich is required by the fast sweep and the desired ramp linearity. Anexternal PLL lock detect circuitry which is driven from the PFD U33provides the status of the PLL to the PLD.bThe phase-frequency detector PFD U33 is used in low noise phaselocked loop. It detects the phase/frequency difference between the477 megahertz signal provided by the upconverted DDS signal andthe frequency divided signal derived from the 4.3 gigahertz VCOto generate output pulses that are proportional to the phase andfrequency difference between the two signals. The reference signalis the RF output of U24 from the 477 megahertz bandpass filter(466.6 to 488.9 megahertz) applied to U33-3. The second signal isthe PLL_FDBK_VCO and the compliment PLL_FDBK_NVCO fromfrequency divider U25. The phase-frequency detector U33 uses thephase difference between the two signals to supply frequency up anddown pulses to comparator U28. The output of U28, a dc voltage, isused to tune the VCO G1.5VCOaThe VCO G1 has a range of 4.2 to 4.4 gigahertz. The power outputis a typical 5.0dBm typical from a single supply of +3 .3 V DC. Thecontrol voltage from U28 on G1-22 (VTUNE) increases the outputfrequency of the VCO as the voltage increases. The control voltagerange is 3.5 to 7.0 V dc.6Digital AttenuatoraThe RF output of VCO G1 is routed to digital attenuator U20-2. Digitalattenuator U20 has a range of 2.4 to 8.0 gigahertz, with an insertionloss of less than 3.8 decibel and attenuation accuracy is ± 0.5 decibel.The attenuator can be set between 0 to 31.5 decibels with 0.5 decibelsteps. Six control voltage inputs, switch between 0 and +3 to +5 V dc,are used to select each attenuation state. The digital attenuator U20 iscontrolled by the PLD U512 for dynamic power control that is requiredfor board to board variation and temperature variation.7Driver Amp, Power Amp and Power DetectoraThe RF output of Digital Attenuator U20-2 is connected to driveramplifier U19-3. The driver amplifier U20 provides about 20 decibelsof gain and the PA U12 27 decibels of gain. Both operate with 5 voltsupply and consume about 130 mA and 600 mA respectively. The PAprovides an internal power detector which uses an external temperatureEFFECTIVITYALL 34-42-37 Page 1810 Oct 2007© Honeywell International Inc. Do not copy without express permission of Honeywell.
COMPONENT MAINTENANCE MANUALPart No. 066-50007compensation circuitry. The temperature compensated circuit drivestwo comparators whose output is sent to PLD U512, which in turncontrol the digital attenuator to control the power. The temperaturecompensated detector enables the power to be controlled within +/-1decibel over the operating temperature range. PA U12 is capable ofdeliveringupto29dBmpower.8CouplersaThe RF output of the power amplifier U12 is on U12-12. The output isrouted through three 23-decibel couplers and one 33-decibel coupler.The three 23 decibel coupled signals are used for Receive Mixer LOU12, Cal Mixer LO U11 and for calibration signal generation using BAWdevice U6. 33 decibel coupler is used to sample the output signaland feed back to the PFD U33 through frequency dividers U21 &U25. There exist two more 23 decibel couplers for test signal injectionbefore LNA, U7.bEach directional coupler consists of two microstrip coupled lines with agap dimension of which depends on the coupling requirements. Thecoupling length is quarter wavelength and one port of each directionalcoupler is terminated by 50 ohm shielded resistors (R10, R36, R88,R89, R90, R121). The printed structure of coupler provides 0.25decibel maximum loss.9IsolatoraAn isolator, U17 is placed between the Power Amplifier and theTransmit antenna to minimize reflections from the transmit antennaand associated cables and connectors and improve the VSWR. Thisis a SMT device and provides 20 decibel minimum isolation with 0.5decibel of maximum insertion loss.10Low-Pass FilteraA printed microstrip low pass filter is employed to attenuate theharmonics up to 18 gigahertz. This filter provides 30 decibel and15 decibel for 2nd and 3rd harmonics respectively and a maximuminsertion loss of 0.25 decibel. The return loss of this filter is betterthan 18 decibel. The output of the low-pass filter is routed to transmitantenna connector J1004-1.11DC block and the TransguardsaA high-voltage matched capacitor circuitry and transguard are usedin the transmitter chain to provide protection transmitter amplifier andthe DC antenna monitoring circuit from voltage transients which arecaused by lightning.12RF FPGAaThe FPGA supports a 24 bit serial interface between the DSP andRF module. The DSP uses the DATA_IN and DATA_CLK signals totransfer 24 bit serial data sequences to the FPGA that provide it withEFFECTIVITYALL 34-42-37 Page 1910 Oct 2007© Honeywell International Inc. Do not copy without express permission of Honeywell.
COMPONENT MAINTENANCE MANUALPart No. 066-50007system select information, control the U1 Receive RF switch with theRX_SWT_CTRL signal, control the U3 Calibration RF switch withthe CAL_SWT_CTRL signal and control power to the U7 LNA withthe RF_AGC signal. The FPGA returns received DATA_IN data onthe DATA_OUT line when RDATA_EN is low and the FSYNC signalwhen RDATA_EN is high.bThe FPGA generates the FSYNC and DOWN_UP signals based on thesystem select information provided by the 24 bit serial interface. Thefrequency of the DOWN_UP signal is 145 Hz for system select 1, 150Hz for system select 2 and 155 Hz for system select 3. The FSYNCfrequencies are one-half the DOWN_UP frequencies. Assertion ofthe RAMP_CLR signal cause the FSYNC and DOWN_UP signals tobe held low.cThe FPGA gets ramp rate information by reading ADC U510 using theA2D_CS, A2D_SCLK and A2D_DOUT signals. The ADC input isthe DAC12_0 signal and its voltage is proportional to the ramp raterequired by the DSP.dThe FPGA programs the main DDS U32 using the DDS1_CS,DDS1_SDIO and DDS1_SCLK signals. The DDS1_SDO signalprovides the FPGA readback capability of the DDS internal registers.Signals DDS1_RESET and DDS1_IOSYNC are used to reset the DDS.Similar signals support the monitor DDS U18.eBoth DDS are programmed with identical ramp information based onsystem select and the ramp rate information from the ADC. For systemselect 1 the DDS are programmed such that the lower transmitterfrequency is held constant at 4.235 gigahertz, for system select 2 theupper transmitter frequency is held constant at 4.365 gigahertz andfor system select 3 the transmitter frequency range is held centeredat 4.3 gigahertz.fThe FPGA FUD signal is used to initially program the DDS for a single4.3 gigahertz transmitter frequency. During normal operation the FPGAPS0 signal is then used to program the DDS registers with new ramprate and frequency range data. The PS0 signal also controls the rampfrequency direction of the DDS.gThe FPGA uses the TX_PWR_DET_LO and TX_PWR_DET_HIsignals from comparator U514 to level the transmitter power. TheFPGA periodically adjusts the TX_.5dB_CTRL to TX_16dB_CTRLsignal lines in .5 decibel steps until both TX_PWR_DET_LO andTX_PWR_DET_HI signals are high.hThe FPGA provides limited fault detection reporting to the mainprocessor module via the FAULT_EB and FAULT_EF signals. Via thebite fault multiplexer U4 when the tri-state FAULT_EB signal is pulledlow the LRU will generate an EB fault and similarly polarity changes inFAULT_EF signal will cause the LRU to report an EF fault. Only whenEFFECTIVITYALL 34-42-37 Page 2010 Oct 2007© Honeywell International Inc. Do not copy without express permission of Honeywell.
COMPONENT MAINTENANCE MANUALPart No. 066-50007the RF_AGC signals at FPGA pins 27 and 24 miss-compare will theEF fault be generated. Transmitter leveling faults, miss-compare faultsbetween the two DDS outputs, 384 megahertz clock frequency or20 megahertz clock frequency(G500) accuracy faults, or transmitterPLL loop faults occurring when the PLL_LOCK_DET signal goes lowcause the EB fault to be generated.(3) Receiver Chain(a) The heart of the receiver chain is the double balanced mixer. The signal receivedfrom the Rx Antenna is mixed with a sample of the transmitter signal to produce alow frequency signal that is proportional to the altitude to the ground. An LNAwith bypass switch is employed to adjust the LNA gain between the two states asrequired by the received signal amplitude.1DC block and Receive TransguardsaThe BPF provides the required dc block for the receiver chain while thetransguard provides protection for the antenna monitoring circuit fromvoltage tansients which are caused by lightning.2Bandpass FilteraThe receiver input is from RX antenna connector J1005-1. The receiveRF signal from the antenna is routed through a 4.3 gigahertz bandpassfilter. This printed bandpass filter uses parallel coupled, half-wavelong microstrip resonators, coupled along half of their length with theadjacent resonators. The seven-resonator bandpass filter provides2.5 decibel loss in the bandpass and 50 decibel attenuation for themultilayer spiral parasitic signal at 5.03 gigahertz and overall out ofband attenuation to reject out of band HIRF up to 18 gigahertz.3Receive/Calibration switchesaThe output of the bandpass filter is routed to the LNA through theRF switch U1. The RF switch U1 is a broadband high isolation,non-reflective SPDT. The receiver and calibration switches (U1 andU3) provide the facility to channel the approprate signal through thereceiver chain and are used for the self-test and noise floor test. Theswitches are non-reflective, high isolation switches and provides about50 decibel of isolation at 4.3 gigahertz with 1.5 decibel insertion loss.The high isolation on the PCB is achieved through co-planner waveguide design instead of microstrip.bThe RF switch operates with complementary negative control voltagelogic of -5 to 0 V dc and does not need bias supply. Control signalsare generated by the PLD through CMOS level shifters (U2) sincethe PLD operates with 3.3volts. The switch control voltages are alsobeing monitored by the MUX U4.cThe control of the RF switch is by the control signals on U1-15 and-16. Refer to Table 6 for the U1 control truth table. The RF1 output isnot used and grounded through resistor R5.EFFECTIVITYALL 34-42-37 Page 2110 Oct 2007© Honeywell International Inc. Do not copy without express permission of Honeywell.
COMPONENT MAINTENANCE MANUALPart No. 066-50007Table6. U1ControlTruthTableControl Input Signal Path StateU1-16 (A) U1-15 (B) RFC to RF1 RFC to RF2High Low On OffLow High Off On4Low Noise Amplifier/Step AttenuatoraThe receiver front-end C-Band low noise amplifier, U7 has a typicalnoise figure of 1.8 decibel and provides 12 decibel of gain for lower levelsignals (high altitudes), and 6 decibel attenuation (total loss 18 decibel)for the higher level signals (low altitudes). The amplifier is under thebinary control of the PLD U512. The low noise amplifier insures withminimum noise figure for signals received at high altitudes.5RX MixeraThe receive mixer (U10) is a double balanced mixer with built-in LOamplifier and work with +2 dBm of typical LO signal. This provides8 decibels of conversion loss, 32 decibels LO/RF isolation, and 25decibels LO/IF isolation. In the receive path, the RF signal on U10-8 isfrom the Rx antenna through the RF Switch U1. The LO signal to U10-1is from the 23 decibels coupler on the output of the power amplifierU12-12. The two signals are mixed to provide the IF baseband signal(IF_TO_BB) on U10-5.(4) Cal Signal Chain(a) A directional coupler picks off some of the transmitter signal and feeds it to abulk acoustic wave device that provides a reflected signal calibrated to a timedelay equivalent to 300 feet (0.616usec). Calibration mixer extracts a signal atthe difference frequency between transmit and delay element signals. Theoutput is filtered and amplified and processed by the CPU for calibration andself-test purposes.1Delay-LineaThe 300-foot Bulk acoustic wave SMT delay line U6 with 0.603 to0.616 usec delay consists of a cylindrical rod of quartz crystal forthe propagation of an acoustic wave. This one- port delay line usesonly one transducer for both input and output and therefore we haveincluded a circulator that properly directs the input to the BAW andoutput of the delayed signal to the calibration mixer. The circulatorprevents the transmitter sample signal from directly being applied to thecalibration mixer. The BAW delayed signal incurs 28 to 38 decibels ofinsertion loss at 4.3 gigahertz.2CirculatoraThe circulator, U5 is a counterclockwise SMT device and provides 22decibels minimum isolation at 0.5 decibels maximum insertion loss. AEFFECTIVITYALL 34-42-37 Page 2210 Oct 2007© Honeywell International Inc. Do not copy without express permission of Honeywell.
COMPONENT MAINTENANCE MANUALPart No. 066-50007portion of the transmit signal is supplied to port-1, which in turn feedsthe delay-line at port-2 to produce the delayed signal. The reflectedsignal is extracted from port-3 and fed to the cal mixer.3Calibration MixeraThe device used for calibration mixer U11 is the same as receivemixer U10. In the calibration path, the RF signal on U11-8 is from thecirculator U5 output. The LO signal, CAL_LO_MIX on U11-1 is fromthe 23 decibels coupler on the output of the power amplifier U12-12.The two signals are mixed to supply the IF calibration baseband signal(CAL_TO_BB) on U11-5.(5) IF Sections(a) U506, U507, and U505 are the calibration output amplifier chain. U506 acts as aselectable high-pass filter controlled by HI_PASS1 and HI_PASS2 signals whichcomes from the DSP. In the case of the calibration signal, it allows for increasedhigh pass filtering in the response to the calibration IF. With switch 2 (S2) of U506open, C532 is not part of the circuit and the high pass response is determined byC533. With S2 closed, C532 is then in parallel with C533 and is the dominantfactor in determining the response of the input stage of the filter.(b) The input signal CAL_TO_BB goes through C533, which gives it a high-passresponse. The signal then goes into U507 which is a non-inverting amplifierwithagainof20.(c) The output of U507 goes to C534 which produces a high-pass response. This isalso selectable by HI_PASS2. With switch 4 (S4) of U506 open, R66 is not part ofthe circuit and the response is determined by C534 and R536. With S4 closed,the response is determined by C534 and the parallel combination of R536 andR66 to determine the cutoff frequencies/response. The output goes to U504,which is an inverting amplifier with a gain of 2. This gain can be adjusted usingthe pot R34. Next, the output goes through C512 for high-pass filtering andbecomes CAL_OUT, which goes to the differential amplifiers in the DSP section.(d) The IF input signal IF_TO_BB is ac coupled to transistor Q1, which is a commonemitter amplifier. The output from the collector of Q1 is filtered by C36 (low-pass)and C528 (high-pass) and then it is applied to high-pass amplifier U505. Overall,Q1 and U505 have 30 decibels of gain and low noise. The output of U505 goesthrough R533 and then into a selectable high-pass filters which is determinedby HI_PASS1 and U506. With switch 1 (S1) and U505 open, C45 is not part ofthe circuit and the response is determined by C531 and the input impedanceof U502 which is 100-ohms. With S1 closed, C45 is in parallel with C531 andbecomes the dominant capacitor for the response. The response is essentiallyC45 and 100 ohms. The output of the high-pass filter goes to U502-A, which isa 40 decibels gain voltage controlled amplifier. It is controlled by the IF_AGCwhich comes in on pin 28 of J21. The voltage at pin 16 of U502-A and pin 9of U502-B varies from 0 to 2.5 volts.(e) The gain of U502 can varied from 0 decibel gain to 40 decibels gain. The outputof U502-A goes through a high-pass filter (C505) and then it is routed to the pinEFFECTIVITYALL 34-42-37 Page 2310 Oct 2007© Honeywell International Inc. Do not copy without express permission of Honeywell.
COMPONENT MAINTENANCE MANUALPart No. 066-500077 of U502-B. U502-B is a 0 to 40 decibels voltage controlled amplifier. Its gaingoes from 0 to 40 decibels gain when the input on pin 9 goes from 1.25 to2.5 volts. Overall, from pin 2 of U502-A to pin 11 of U502-B, there is up to 80decibels gain available depends up on the IF_AGC control signal. The output islow-pass filtered through R503 and C503 and goes into the first of two switchedcapacitor filters.(f) U500 and U501 are switched capacitor elliptical filters which have a responseequivalent to an eight-pole elliptical filter. The cutoff is determined by theFILTER_CLK which comes from the DSP section. The cutoff is at 43 KHz. Theoutput of these filters have an uncommitted op-amp with which resistors R1, R2,R3, and capacitors C1 and C2, are a dual, two-pole low-pass filter to reducethe amount of clock noise on the output. The output of U500 is connected toU501, which is essentially the same circuit, to give it a very sharp cut-off toprevent high frequencies going to the DSP. The output at pin 5 of U501 goesthrough high-pass filter C507 to pin 3 of amplifier U503 which has a gain of 15decibels. The output of U503 goes through R22 and is the BASEBAND_OUTwhich goes to the DSP section.(6) BITE MUX(a) The BITE MUX U4 is a CMOS latched 16-bit to 1 analog multiplexer. The BITEMUX has different voltages on its inputs which are monitored by the DSP section.On input 1 (S1) and 2 (S2), 2.5V and 3.3 volts going to the RF section aremonitored. Also, input 2 (S2) provides FAULT_EB signal which can be decoded toa set of RF circuitry failures. Inputs 3 (S3) thru 4 (S8) are the RX_SWT_CNTRLsignal voltage which is monitored. Input 7 (S7) is the FAULT_EF signal voltagewhich is monitored. Input 7 (S6) is the CAL_SWT_CNTRL signal voltage which ismonitored. Input 8 (S8) is the RF_AGC signal voltage which is monitored. Input 9(S9) is the +12_DIG volts which is monitored. Input 10 (S10) is the +5V_RF whichis monitored. Input 11 (S11) is the -12_DIG volts which is monitored. Input 12(S12) is the -5_DIG volts which is monitored. Input 13 (S13) is the TX_ANT_MONwhich is monitored and should look like a short when connected to an antenna.Input 14 (S14) is the RX_ANT_MON which is monitored and should look likea short if its connected. Input 15 (S15) is the RAMP_OFFSET signal voltagewhich is monitored. Input 16 (S16) is the TX_POWER_MON which is monitored.U508-A is a buffer amplifier to buffer the output going to the DSP section.(7) Power Supply Filtering(a) The power supply filtering consists of L507, L501, L505, and L504. RF CCAcontains voltage regulators U13, U16, U22, U23, U29, U30, U34, U509 &U515 linear regulators to generate a clean +1.8V, +2.5V, +3.3V, +5.0V, +10V,and -5V for various RF and Digital ICs. U5 is switching regulator to convert12V to +6V DC with 85 percent efficiency. This device contains internal shortcircuit protection also.EFFECTIVITYALL 34-42-37 Page 2410 Oct 2007© Honeywell International Inc. Do not copy without express permission of Honeywell.
COMPONENT MAINTENANCE MANUALPart No. 066-50007C. Main Processor Module (Subtask 34-42-37-870-011-A01)(1) General(a) See Figure 2004 (GRAPHIC 34-42-37-99B-814-A01) for a schematic diagram onthe Main Processor Module.(b) The main processor module:• Controls the radio altimeter operation• Does signal processing of the difference frequency and test signals• Controls the aircraft interfaces and the data displayed on the front panel.(c) The main processor module is divided into three major sections:• 486 microprocessor section• I/O section• DSP section.(2) 486 Microprocessor Section(a) General1The 486 microprocessor section (CPU section) does frame-to-frameprocessing of the altitude data from the DSP section and supplies thealtitude to the I/O section. Programmable logic devices serve as themicroprocessor controllers and are the interfaces to:• Memory devices (boot routine, program, fault, and data• Data recorder/data loader flash card• Front panel display driver.2The microprocessor U39, in the CPU section, controls all major functions ofthe radio altimeter. Microprocessor U39 is an Intel®486 SX microprocessor,which does not have a math coprocessor. The CLK signal on U39-123is the fundamental timer and the internal operational frequency for themicroprocessor.3Address lines A31 thru A2, together with the byte enables BE0* thru BE3*,define the physical area of memory or I/O space accessed. Address linesA31 thru A4 (2) are used to drive addresses into the microprocessor to docache line validations. Address lines A31 thru A2 are not driven during busor address hold. The byte enable signals BE0* thru BE3* indicate activebytes during read and write cycles.4On the first cycle of a cache fill, the external system assumes that all byteenables are active. Data lines D31 thru D0 are the data lines for themicroprocessor U39. Data lines D0 thru D7 define the least significant byteof the data bus while lines D24 thru D31 define the most significant byte ofthe data bus. Data parity pins DP0 thru DP3 are connected to VCC throughpull-up resistors because the system does not use parity.EFFECTIVITYALL 34-42-37 Page 2510 Oct 2007© Honeywell International Inc. Do not copy without express permission of Honeywell.
COMPONENT MAINTENANCE MANUALPart No. 066-500075A temperature sensor is used for the data log for temperature. It is for BITand is used to log the temperature when a failure happens. This is usedin debug.(b) Microprocessor Control1Programmable logic device U52 and integrated peripheral controller U22are the heart of the Main Processor CCA. The bus controller U52 hasall the logic signals and timing needed to do chip selects and controlmicroprocessor U39. Oscillator Y1 is a 24 megahertz clock, which is dividedby 2. This supplies 12 megahertz to microprocessor U39. The 24 megahertzis used because there are two edges used to control the timing.2The 5-volt monitor and watchdog timer U28 reset gives over and undervoltage protection. It is set for about 5 to 7 percent of the upper 5 volts,which is needed for the microprocessor U39. When the voltage falls below4.75 volts or rises above 5.25 volts, the reset happens and holds themicroprocessor in reset.3Crystal G2, on integrated peripheral controller U22-72, is a 32.768 kilohertzcrystal. It is used to control the real time clock for the software. It alsocontrols timing and tagging information.(c) Microprocessor Memory1Data RAMs U40, U47, U53 and U61 are 128K X 32 CMOS static RAMs.The data RAMs are backed up by +5 Volts for 20 seconds, which decreasespower-up time. The chip select, on pin 22 of each device, is used to makesure there are no inadvertent writes to each RAM. The chip selects are heldhigh to disable the RAM as the power goes down. This makes sure that noexterior writes happen to the RAM.2Flash memories U16, U17, U25, and U26, are used to store the program.These memories are read/write and can be rewritten as long as 12 volts isapplied to the device. The flash memories 12-volt switch circuit consists oftransistor Q6 and the associated components. The flash memories 12-voltswitch is controlled to make sure that no inadvertent writes happen duringoperation. It is a switch needed to turn on the 12 Volts to the flash memory.3Devices U2, U3, U9 and U10 are the byte swapping logic. There are twoindependent buses to accommodate 32-bit and 16/8 bit devices. The FAST32-bit bus only talks with the program/data memories. The SLOW bus talksto all other I/O peripherals. For the 32-bit microprocessor U39 to talk to any8- or 16-bit devices, the 16- and 8-bit memories need external byte swappinglogic to route data to the appropriate data lines. Separate buses distributecapacitance loading and thus lower signal noise.4Devices U4, U11 and U60 are address buffers. Half of U11 is used to bufferother signals for increased drive and to make sure that the signals are cleangoing to other sections of the module. Address buffer U60 is the controlsignals buffer, which is all the signals that go to either the I/O section or theDSP section. The signals are pulled up to make sure that no noise getson the line and inadvertently actuates the signal.EFFECTIVITYALL 34-42-37 Page 2610 Oct 2007© Honeywell International Inc. Do not copy without express permission of Honeywell.
COMPONENT MAINTENANCE MANUALPart No. 066-500075The D flip-flops U42 and U48 are used in the I/O discretes circuit. OnU48, the FLASH_WR_ENABLE discrete is used to switch 12 volts. TheDSP_RESET discrete and RS232_RST discrete are used on two differentperipherals. Another discrete is the LCD_LITE_EN, which turns on thebacklight on a plug-in test display. Device U42 makes up the input discretes,which monitor various inputs from the data card and some of the test buttonsfrom the front panel.6Device U59 is a 32K byte CMOS EEPROM. This is the storage site forconfiguration memory and fault memory recorded during the flight legs.7The BOOT block flash memory U50 is where microprocessor U39 getsthe start-up information and power up. Device U50 is a 128K X 8 flashmemory and a switch. The switch has two settings: SHOP_MODE andNORMAL_MODE. The flash memories are not preprogrammed.• In the SHOP_MODE, the switch lets 12 volts access the BOOT blocksection. This is done so that in flight (even if the 12 volts is inadvertentlyturned on) the BOOT code can not be overridden. It can only be done inthe shop and the unit has to be open.• In the NORMAL_MODE, part of the BOOT code can be overridden butthat is not essential to the unit so memory cannot be lost.8A UART U65 does parallel-to-serial conversion on data characters receivedfrom the microprocessor. The microprocessor can read the complete statusof the UART U65 at any time during the functional operation. When CS0and CS1 are high and CS2 is low, the chip is selected. This enablescommunication between the UART and the microprocessor.9When the interrupt output pin U65-33 goes high when any one of thefollowing interrupt types has an active high condition and is enabled throughthe interupt enable register:• Receiver Line Status• Received Data Available• Transmitter Holding Register Empty• MODEM Status.10The INTR signal is reset low upon the appropriate interrupt service ora master reset operation.11Connector J8 is the 34-pin power supply connector. The +24, +5, +12, and-12 volts have filter capacitors and inductors. The PWRDN_INT* signalon J8-4 is buffered by two Schmitt trigger inverters and a pull-up resistorand capacitor. This is the power supply signal that tells the unit that the200 milliseconds power hold-up is about to go down, and to store all theinformation before all power is lost.12Connector J12 is the in-circuit programmable connector. This connectoris used to program microprocessor U52 and U70, the circuit card PLDs.EFFECTIVITYALL 34-42-37 Page 2710 Oct 2007© Honeywell International Inc. Do not copy without express permission of Honeywell.
COMPONENT MAINTENANCE MANUALPart No. 066-50007Microprocessor U52 and U70 can be reprogrammed as many times asneeded.(3) I/O Section(a) General1The I/O section of the Main Processor Module supplies the necessary signallevel conversion, bipolar to TTL and TTL to bipolar. The I/O section alsodoes the serial to parallel and parallel to serial conversion needed to transferARINC 429 and discrete input/output information between the I/O moduleand the main processor data bus.(b) ARINC 429 Inputs1The ARINC 429 receivers 1 and 2 are in U20. The ARINC 429 receivers3 and 4 are in U27. The ARINC 429 receivers 1, 2, 3 and 4 are dual 429receivers used to convert the bipolar input signals from standard 429 levels(+12 to -12 V dc) to standard TTL levels (0 to +5 V dc) needed for properoperation.2There are four ARINC 429 inputs to ARINC 429 receivers 1 and 2, U20.They are:• FREQ_FUN_SEL INPUT_PORTA_A (J6-41)• FREQ_FUN_SEL INPUT_PORTA_B (J6-42)• FREQ_FUN_SEL INPUT_PORTB_A (J6-49)• FREQ_FUN_SEL INPUT_PORTB_B (J6-50).3The TTL level serial data output from U20-5, -8, -12, -15 dual receiver U20 isapplied to XCVR LSI U49-19, -20, -21, -22. The serial data is shifted intointernal registers and stored as 8-bit parallel bytes. When a valid word isreceived, a processor interrupt IOINT signal is asserted at U49-27.4The microprocessor U39 responds to this interrupt by the addresses SA2and SA3 on U49-6 and -7. Signal IOCS1 on U49-5 is asserted low. TheW/R SA4 signal on U49-2 is asserted high. This selects U49 and the databyte is placed onto the IO_DATA bus (D0-D7) The D0-D7 I/O data bus linesare applied to the lower section of bidirectional 429 data buffer U37, whichinterfaces XCVR LSI U49 to the microprocessor slow data bus.5The ARINC 429 receivers 3 and 4 operate the same as the ARINC 429receivers 1 and 2 and are not described.(c) ARINC 429 Outputs1There are two ARINC transmitters on the Main Processor CCA. ARINC429 transmitter 1 is U66. ARINC 429 transmitter 2 is U67. The outputsof transmitter 1 are CMC_OUTPUT_A and on CMC_OUTPUT _B onJ6-61 and -62. The outputs of transmitter 2 are 429_OUTPUT _#0_A and429_OUTPUT _#0_B on J6-55 and -56. Because 429 signal processing isidentical for both outputs, only transmitter 1, U66, is described.EFFECTIVITYALL 34-42-37 Page 2810 Oct 2007© Honeywell International Inc. Do not copy without express permission of Honeywell.
COMPONENT MAINTENANCE MANUALPart No. 066-500072To transmit, the main processor places a data byte on the I/O data busthrough bidirectional 429 data buffer U37. Bidirectional 429 data buffer U37addresses and selects 429 LSI #1 U49 and asserts WR low. The data bytepresent at the data inputs to U37, is clocked out as a serial TTL level data bitstream from LSI#1 U49-3 and -4. The serial data steam is applied to ARINC429 transmitter U66-6 and -23. Transmitter U66 converts the TTL input to abipolar output at U66-13 and -17. The bipolar output from U66 is routedthrough J6-61 and -62 to the rear interconnect board.3The bipolar output from U66-13 and -17 is also routed through multiplexerU56 and fed back as 429_BITE_INPUT_A and 429_BITE_INPUT_B to 429receiver U27-4 and -6. The signal is converted to TTL levels and appliedto LSI U49-25 and -26.This allows the main processor to read and verifythe transmitted data.(d) Discrete Inputs1The 16 discrete inputs from the rear interconnect module are applied to themain processor module at pins 15 thru 30 of connector J6. Eight of the 16input lines are applied to the inputs of discrete input latch U38 throughdiode networks and resistor divider network R36. The other eight lines areapplied to discrete input latch U38 through diode network and resistordivider network RR27. The outputs from discrete input latch U38 are placeddirectly on the microprocessor slow data bus.2Resistor divider networks R27 and R36 lower the bipolar level signals to TTLlevels. The diode networks supply over-voltage protection for the U38 inputs.(e) Discrete Outputs1Discrete output data is placed on the microprocessor slow data bus andapplied discrete output/429 TX setup latch U69. The data is latched andtransferred to the 1Q and 2Q outputs of U69. The control signals TX1ENand IOCS5 at U69-25 and -48 are asserted. The 1Q outputs of U69 areused as strobe and sync pulses to select 429 transmitters 1 thru 4 onthe I/O control bus.2The 2Q outputs are the discrete data lines, which are applied to powerdriver U32. The 2Q outputs from power driver U32 are unregulated 24-voltsignal levels that are transmitted to the rear interconnect module throughconnector J6.(f) Shut Down Logic1Two discrete are present on the rear connector, but are not connectedinternally. The unit is strapped for interrupt mode. One discrete is strappedhigh the other discrete is strapped low. In the interrupt mode the highand low discrete is applied through a diode network and resistor dividernetwork R27 to the A and B sections of logic gate U68 where it is invertedto produce a high INT_ENABLE signal on I/O control bus. Logic gate U68inverts the high signal back to its original low status before it is latched intodiscrete input latch U38.EFFECTIVITYALL 34-42-37 Page 2910 Oct 2007© Honeywell International Inc. Do not copy without express permission of Honeywell.
COMPONENT MAINTENANCE MANUALPart No. 066-500072The high INT_ENABLE signal on I/O control bus is applied to the C and Dsections of U68. The outputs of U68C and U68D are determined by the stateof the MON1 and MON2 signals at pins 9 and 12. In normal operationalconditions (no failures or errors detected), the MON1 and MON2 lines arelow, and do not affect the operation of 429 transmitters U66 and U67.3If a failure is detected, the monitor processor may assert a high MON1 or ahigh MON2 signal, which produces a low output from U68C or U68D. Theselow outputs are applied to the CLOCK (pin 25) and SYNC (pin 4) inputs of429 TX #1 U66 and 429 TX #2 U67 to shut down the transmitters.(4) DSP Section(a) General1See Figure 5 (GRAPHIC 34-42-37-99B-806-A01) for a block diagram of theDSP section. The DSP section is used to process the analog outputsfrom the RF module. The DSP section also generates some of the controlsignals to the RF module for:• Transmit modulation• Automatic gain control• Test signals.(b) Analog Input Circuits1The baseband signal (DETRX1), which is the output from the RF on the RFcontrol module, goes into differential amplifier U45A. Differential amplifierU45A buffers the output that goes to analog MUX U46-6. Differentialamplifier U45B is another buffer on the same signal, which buffers the signalthat goes to the monitor processor.2Differential amplifier U36A buffers the calibration output signal (DETRX2from the RF control module. It buffers the signal going into analog MUXU46-7. Another differential amplifier is U36B, which buffers the calibrationoutput signal goes to the monitor processor.3Multiplexer U46 is a CMOS latched eight channels-to-one analog multiplexer.It switches between the calibration output signal and the baseband signalor any of the other inputs. In normal operation U46 alternately samplesthe calibration output signal and the baseband signal. The output of U46goes to U57, which is a 12-bit A/D converter. Converter U57 output iscontrolled by the MUX addresses 0 thru 2, which are generated by the DSPI/O controller U70.(c) Analog to Digital Conversion Circuits1See Figure 6 (GRAPHIC 34-42-37-99B-807-A01) for a block diagram of theDSP section. The analog signals from the RF module are digitized in 12-bitA/D converter U57. The A/D converter is also used to monitor signals fromthe BITE test points on the RF module and the power supply voltages. Thedigitized data from the A/D converter is stored in FIFO memory devices U18and U29, which are accessed by the DSP. The output of the FIFOs goesEFFECTIVITYALL 34-42-37 Page 3010 Oct 2007© Honeywell International Inc. Do not copy without express permission of Honeywell.
COMPONENT MAINTENANCE MANUALPart No. 066-50007to the DSP_DATA [31:0] bus where the microprocessor has access tothe contents of the FIFO.2Another mode of operation is byte sampling. The microprocessor determinesthat it wants to look at either the RX_MUX on J10/J2-20 from the RF controlmodule or the bit MUX U43. This allows the microprocessor to monitordifferent voltages. The BIT output has a MUX on the RF control module,which allows the microprocessor to monitor RF test points.3The BIT MUX U43 enables a monitor of the power supply voltages +24,+12, and -12 and also a loop back DAC output (DAC8_0). Inputs DSPBD0,1 and 2 are used to determine which one of the inputs is monitored. TheDSP U15 writes to a latch inside the MUX U43 to select which of the 8inputs it is going to look at.(d) DSP Memory Circuits1The output of the FIFOs U18 and U29 is accessed by U15, which is the DSP.The DSP processes the difference frequency and calibration frequency intoaltitude information2Memory devices U6, U7, U12, and U23 are 32 k X 8 SRAMs, which make upthe program/data memory. These are zero wait state memories that use 15nanosecond RAMs that are 32 k deep. This makes a 32 k by 32-bit RAMarray where the program is stored after boot up.3Dual ported RAM U33 is a where the communications between the DSP andthe main processor takes place. It is 4 k deep by 8-bit wide where by themain processor and DSP can access any location. It is partitioned so theDSP does not access the main processor portion of the RAM. This is whereall the commands from the main processor go to the DSP, and the altitudespectrum data from the DSP goes to the main processor.(e) Data Buffers and Latches1Device U44 is a 16-bit data bus buffer. This is divided into two 8-bitfunctions. The U44 (1A) and U44 (1B) function buffers the lower 8-bits ofthe data bus. On U44 (1B) there is a DSPD0 signal, which is not buffered,that passes through U44 and comes out as DSPBD0, which is buffered.The other function U44 (2A) and U44 (2B) reads the discrete inputs fromthe RF control module. RF1_FIN0 and RF2_FIN0 are functions, which aredefined, on the RF control module.2Latch U35 is a 16-bit latch, which supplies latched outputs to the RF controlmodule. Data outputs DSPBD0 thru DSPBD7 is the buffered data bus andDSPD8 thru DSPD15 is unbuffered data. Outputs DSPL0 thru DSPL15 gothrough 5 megahertz low pass filters U14 and U58. They are then routed tothe two connectors going to the RF control module.(f) Digital to Analog Circuits1DAC U41 is a quad 8-bit device. Output 0 of U41 goes through another filterU30 and is routed to the RF control module on connector J10-28, as IF AGCvoltage. This voltage allows the DSP to control the gain of the receiver IF.EFFECTIVITYALL 34-42-37 Page 3110 Oct 2007© Honeywell International Inc. Do not copy without express permission of Honeywell.
COMPONENT MAINTENANCE MANUALPart No. 066-50007Output 2 goes out on J10-22, which is RAMP_REF. Each D/A converteroutput VOUTA for example, is addressed by setting DSPA0 and DSPA1 to azero and then writes the value on the DSP data bus (the lowest seven bits).Then VOUTB writes a one to A0 and a zero to A1, and then writes the value.2DAC U24 is a quad 12-bit device. The value for the output is written on thedata line D0 thru D11. Each output is accessed by:• A write to an address A0 or A1• Selection of one output• Placement of the value on the data bus outputs.3Digital-to-analog converter U24 is double buffered on the input, so there is aLDAC function (U24-7), which is controlled by the I/O controller U70. Whenthe microprocessor writes to the latch, it goes through an input latch. Whenthe LDAC goes low, the input latch is written to the output. This function isthere so that all the outputs are synchronized. Each of these outputs goesto quad SPST analog switch U19.4Quad SPST analog switch U19 along with U13 make up a quad sample andhold circuit. When the DAC changes voltage, the switch U19 opens and thecapacitors hold the previous value. Once the DAC settles out, U19 closesand samples the output of the DAC. Device U13 is a quad op-amp buffer forthe capacitors. These outputs go to U30, which is a low pass filter. OutputVOUTA from the DAC, after it is sampled, goes to the RF control module andis used for the RAMP_REF on the RF control module.(g) DSP Control1The I/O controller U70 is a high-density in- CPLD. It is programmed by theJTAG inputs, which go to a connector on the main microprocessor.2This I/O controller CPLD U70 has many functions, one is to control whichinput is sampled, like the analog MUX U46 on the input. The main processorgenerates a timer clock, which is DSPCLK1. The DSPCLK1 controls thesample rate of the analog-to-digital converters.3The DSPCLK1 goes into a state machine in the I/O controller U70. TheI/O controller U70 generates the address to be sampled and the samplecommand SAMPLE. This goes to the input signal MUX U46 and to the 12BIT A/D converter U57. The I/O controller U70 generates an A/DSC signal.The A/DSC* goes to the A/D converter which starts the conversion.4The MUX address lines 0 thru 2 determine which input is sampled. TheA/D converter U57 has an end-of-conversion output, which goes high whenthe conversion is over. The I/O controller U70 generates an A/DOE signal,which goes to the FIFOs U18 and U29 where the DSP can read them.5Another function of the I/O controller U70, based on the timer clockDSPCLK1, is to generate a sample command. The sample commandgoes to the analog switch U19, which tells it when to sample the output ofthe 12-bit DAC U22.EFFECTIVITYALL 34-42-37 Page 3210 Oct 2007© Honeywell International Inc. Do not copy without express permission of Honeywell.
COMPONENT MAINTENANCE MANUALPart No. 066-500076Another function is chip select generation, which is _CS0 thru _CS8. Theseare decodes of the address inputs DSPA0 thru DSPA4 and DSPA20 thruDSPA23, to generate DSPCS0 thru DSPCS8. Another function tied to thetimer clock DSPCLK1 is LDAC, which, is the command to load the outputlatch of the 12-bit DAC U24.7Another function of the I/O controller U70 is to generate the serial clockout (SCLKOUT) and serial data out (SDATOUT) signals. The signals goto the RF control module. On the serial port from the DSP the frame isANDed with the clock to generate a gated clock on SCLKOUT. The gatedclock on SCLKOUT signal is routed with SDATOUT through low pass filtersU31 and U64.8The SCLKOUT signal is used to load the ramp generator with the ramp valueto be used in that sweep. It lets the read back of the DATA_OUT_FSYNC.The data is then read back through input that goes into the I/O controllerU70 (SD2IN). It is put onto the RX_CLK, RX_FRAME, and RX_DATA soverification of data sent out was loaded properly into the ramp generator.EFFECTIVITYALL 34-42-37 Page 3310 Oct 2007© Honeywell International Inc. Do not copy without express permission of Honeywell.
COMPONENT MAINTENANCE MANUALPart No. 066-50007Figure 5. (Sheet 1 of 1) DSP Block Diagram (GRAPHIC 34-42-37-99B-806-A01)EFFECTIVITYALL 34-42-37 Page 3410 Oct 2007© Honeywell International Inc. Do not copy without express permission of Honeywell.
COMPONENT MAINTENANCE MANUALPart No. 066-50007Figure 6. (Sheet 1 of 1) Input Filter Module (GRAPHIC 34-42-37-99B-807-A01)EFFECTIVITYALL 34-42-37 Page 3510 Oct 2007© Honeywell International Inc. Do not copy without express permission of Honeywell.
COMPONENT MAINTENANCE MANUALPart No. 066-50007D. Monitor Processor Module (Subtask 34-42-37-870-012-A01)(1) General(a) The main component of the monitor processor module is the MonitorProcessor CCA. See Figure 2003 (GRAPHIC 34-42-37-99B-813-A01) for theschematic diagram of the monitor processor CCA. See Figure 7 (GRAPHIC34-42-37-99B-808-A01) for the overall block diagram of the monitor processorCCA.(b) The Monitor Processor CCA supplies a second signal processor path. It uses aDSP. The DSP processes the received signal and calibration signal, supplied indigital form, from the main processor A/D converter. Also present are a clock, anARINC 429 receiver/selector, and static memory.(c) The Monitor Processor CCA monitors how the main processor module processesthe signals. There are three interfaces between the main processor module andthe Monitor Processor CCA:• Shared memory interface• 429 interface• DSP serial interface.EFFECTIVITYALL 34-42-37 Page 3610 Oct 2007© Honeywell International Inc. Do not copy without express permission of Honeywell.
COMPONENT MAINTENANCE MANUALPart No. 066-50007Figure 7. (Sheet 1 of 1) Monitor Processor Block Diagram (GRAPHIC 34-42-37-99B-808-A01)EFFECTIVITYALL 34-42-37 Page 3710 Oct 2007© Honeywell International Inc. Do not copy without express permission of Honeywell.
COMPONENT MAINTENANCE MANUALPart No. 066-50007(2) Shared Memory Interface(a) The shared memory on the Monitor Processor CCA is the interface to the mainprocessor module. Two hardware semaphores located in the programmable logicdevice U1 supply control of the interface. There is no nonvolatile memory on themonitor processor module.(b) The Monitor Processor CCA gets the program through the shared memoryinterface, which is dual port RAM U1. After power-up the signal MON_RESET(U11-48) is held active. The main processor module loads the monitor program inthe shared memory. Then the main processor takes the monitor out of reset,which causes MON_RESET to go high. The DSP automatically loads its programto the static RAMs U5, U6, U8, and U9.(c) Programmable logic device U11 is a logic device, which is programmedon the module by connector J6043 connector. Figure 8 (GRAPHIC34-42-37-99B-809-A01) is a block diagram of U11.(d) Inside the programmable logic device U11 device are:• Reset logic function• Interrupt timing• Input discrete• Output discrete• Chip select generation for the ARINC 429 and dual port RAM• ARINC 429 interfaces• Data enable and address lines LA2, LA3 and LA4• Watchdog timer logic• Boot ready logic• Shared memory logic.(e) The communications for the shared memory is done with two flip-flopsimplemented in the programmable logic device as shown in Figure 8 (GRAPHIC34-42-37-99B-809-A01). The signal definitions are as follows:1CM_REQ — CP to MON Request• Input pulse from CP• Latched to generate CM_IRQ.2CM_IRQ — CP to MON Interrupt• Active high interrupt to MON, generated from CM_REQ signal from CP• Routed to CP/MON connector to be read by CP before next message issent• Can also be read by MON as Input Discrete Bit DO• Cleared by CM_REL.3CM_REL — Clear CP to MON InterruptEFFECTIVITYALL 34-42-37 Page 3810 Oct 2007© Honeywell International Inc. Do not copy without express permission of Honeywell.
COMPONENT MAINTENANCE MANUALPart No. 066-50007• Any write to Address 60 0000C or reset clears the CP to MON interrupt.4MC_REQ — MON to CP Request• Any write to Address 60 0010 sets MON to CP Interrupt.5MC_IRQ — MON to CP Interrupt• Active high interrupt to CP, sent through CP/MON connector• Read by MON before next message is sent as D1 of Input Discretes• Generated by MC_REQ, cleared by MC_REL.6MC_REL — Clear MON to CP Interrupt• Input pulse from CP/MON connector clears MON to CP Interrupt• Reset also clears the interrupt.(f) Each flip-flop has a request, clear, and a latched output. The latch of thecommunication from main processor to monitor processor has a CM prefix on thesignal (control to monitor). In the other direction, the flip-flop has a MC prefix onthe signal (monitor to main). CM_IRQ and MC_IRQ are the latched outputs.(g) When the main processor requests attention from the monitor processor CCA, itsends a request signal CM_REQ to the input U11-3. The signal is then latchedand becomes CM_IRQ and remains latched until the monitor processor moduleservices the interrupt, and issues a clear signal. Once the latch is cleared,CM_IRQ goes disabled.EFFECTIVITYALL 34-42-37 Page 3910 Oct 2007© Honeywell International Inc. Do not copy without express permission of Honeywell.
COMPONENT MAINTENANCE MANUALPart No. 066-50007Figure 8. (Sheet 1 of 1) U11 Functional Block Diagram (GRAPHIC 34-42-37-99B-809-A01)EFFECTIVITYALL 34-42-37 Page 4010 Oct 2007© Honeywell International Inc. Do not copy without express permission of Honeywell.
COMPONENT MAINTENANCE MANUALPart No. 066-50007(3) 429 Interface(a) The Monitor Processor CCA listens to the 429 transmitters on the main processormodule. There are two modes, interrupt and continuous.1In the interrupt mode if there is something wrong with either module, themonitor processor module automatically shuts off the 429 transmitters onthe main processor module.2In the continuous mode, the monitor processor module will not shut offthe transmitters.(b) The signals that are used to shut off the transmitters are:• XMON_BUS_DIS_#1 (J6018-74)• XMON_BUS_DIS_#2 (J6018-75)• XMON_DATA_ENABLE (J6018-76).(c) In a default, as long as there is power to the monitor processor module thetransmitters are turned off.(d) Device U10 is the ARINC 429 LSI and U12 is the ARINC 429 receiver. ReceiverU12 receives the transmitter signals from the main processor module. LSI U10processes the signals. The programmable logic device does the ARINC 429interrupt timing U11.(e) The transistor Q1 supplies the drive to the monitor data enable discrete and to adefault position, which turns the transmitters on the main processor module off.(4) DSP Serial Interface(a) The DSP serial interface is connector J6045, which is two DSPs thatcommunicate with each other directly. One is on the Monitor Processor CCA,which is U3. The other DSP is on the main processor CCA.(b) The monitor processor module DSP U3 is be reset by:• External reset from the main processor module• 5 volt supply dipping below threshold value• Watchdog timer reset.(c) After monitor DSP U3 is reset by either the 5-volt monitor or the watchdog timer,it stays reset until main processor issues a reset. When WDIS test point isstrapped to ground, both the 5-volt monitor and the watchdog timer are disabled.In addition, BOOT RDY is written to in order to enable the watchdog function.Until then, watchdog cannot cause reset.(d) Device U4 is the supervisor and reset circuit, which has:• Watchdog timer functions• Reset function• Over-voltage monitor function.(e) The output reset signal goes to the programmable logic device U11.EFFECTIVITYALL 34-42-37 Page 4110 Oct 2007© Honeywell International Inc. Do not copy without express permission of Honeywell.
COMPONENT MAINTENANCE MANUALPart No. 066-50007(f) Device U7 is an address decoder, which generates memory chip select. DeviceU13A generates the ready signal for the DSP U3. Connector J6045 is anemulator connection used for development.E. Power Supply Assembly (Subtask 34-42-37-870-013-A01)(1) General(a) The power supply assembly is a self-contained, high-efficiency, switching powersupply that converts the +28 V dc aircraft power into the needed dc operationalvoltages. Three voltages are supplied:•+5Vdc•+12Vdc•-12Vdc.(b) The power supply assembly contains two modules:• Power supply input module• Power supply output module.(c) See Figure 2008 (GRAPHIC 34-42-37-99B-818-A01) for a schematicdiagram of the power supply input module. See Figure 2009 (GRAPHIC34-42-37-99B-819-A01) for a schematic diagram of the power supply outputmodule.(2) Power Supply Input Module(a) See Figure 2008 (GRAPHIC 34-42-37-99B-818-A01) for a schematic diagram ofthe power supply input module. The aircraft + 28 V dc power is applied to theinput module through connector J3108, pins 1 thru 4. The aircraft + 28 V dcvoltage is applied to hot swap controller U1. Hot swap controller U1 is an 8-pinhot swap controller that allows a board to be safely inserted and removed from alive unit. The hot swap controller uses N-channel pass transistor Q1 so that theboard supply voltage can be ramped up at a programmable rate.(b) The voltage on hot swap controller U1-1 is used to supply under-voltage lockout.When the voltage ON pin, U1-1, is pulled below 1.233V an under-voltagecondition is detected. The GATE on U1-6 is pulled low to turn the transistor Q1off. When the ON pin, U1-1, rises above 1.313V low-to-high threshold voltage,the transistor Q1 is turned on again.(c) The voltage on hot swap controller U1-2 (FB) is the power good comparator input.It monitors the output voltage with an external resistive divider R3 and R4. Whenthe voltage on the FB pin is lower than the high-to-low threshold of 1.233V, thePWRGD pin U1-3 is pulled low. This pin is not used on this module.(d) The voltage on hot swap controller pin U1-5 is the timing input. External timingcapacitors, C3, C6, and C13 at this pin programs the maximum time U1 is allowedto remain in current limit. When the part goes into current limit, a 77-microamppull-up current source starts to charge the timing capacitors. When the voltageon the TIMER pin reaches 1.233V, the GATE pin (U1-6) is pulled low. Thepull-up current is turned off and a 3 microamp pull-down current discharges thecapacitors. When the TIMER pin falls below 0.5 Volts, the GATE pin either turnsEFFECTIVITYALL 34-42-37 Page 4210 Oct 2007© Honeywell International Inc. Do not copy without express permission of Honeywell.
COMPONENT MAINTENANCE MANUALPart No. 066-50007on automatically or turns on once the ON pin is pulsed low to reset the internalfault latch. If the ON pin is not cycled low, the GATE pin remains latched off.(e) The voltage on hot swap controller pin U1-6 is the high side gate drive for theN-channel transistor Q1. An internal charge pump guarantees at least 10 volts ofgate drive for supply voltages above 20 volts and 4.5 volts gate drive for supplyvoltages between 10.8 and 20 volts. The rising slope of the voltage at the GATEU1-6 is set by an external capacitor C5 connected from the GATE pin to GND andan internal 10A pull-up current source from the charge pump output.(f) When the current limit is reached, the GATE pin voltage adjusts to maintain aconstant voltage across the sense resistor while the timer capacitor starts tocharge. If the TIMER pin voltage exceeds 1.233V, the GATE pin is pulled low.The GATE pin is pulled to GND when the ON pin is pulled low, the VCC supplyvoltage drops below the 8.3V under-voltage lockout threshold or the TIMER pinrises above 1.233V.(g) The voltage on hot swap controller pin U1-7 is the current limit sense. A senseresistor R8 is placed in the supply path between VCC and SENSE. The currentlimit circuit regulates the voltage across the sense resistor to 47 millivolts if thevoltage on U1-2 is 0.5V or higher. If the voltage on U1-2 drops below 0.5V, thevoltage across the sense resistor decreases linearly and stops at 12 millivoltswhen U1-2 is 0V. To defeat current limit, short the SENSE pin to the VCC pin.(h) The 28 V dc output of the power supply input module is applied to the powersupply output module through connector J3302.(3) Power Supply Output Module(a) See Figure 2009 (GRAPHIC 34-42-37-99B-819-A01) for a schematic diagram ofthe power supply output module. The power supply output module converts the28 V dc from the hot swap controller into the three power supply voltages, +5 Vdc, +12 V dc, and -12 V dc.(b) Each of the power supplies in the power supply output module use a PWMcontroller and two switching transistors to develop each voltage. Table 7 lists thePWMs and the transistors.Table 7. Power Supply ComponentsPower Supply PWM Transistors+5 V dc U2 Q3 and Q4+12 V dc U1 Q1 and Q2-12 V dc U3 Q5 and Q6(c) All three of the supplies operate the same and only the +5 V dc supply isdescribed in this section.(d) The 28 V dc from the hot swap controller is applied to PWM U2-15. The PWMU2 is a high-voltage, wide input (10 to 55 Volts) synchronous, step-downconverter.Table 8 lists the pins of the PWM and the function of each pin.EFFECTIVITYALL 34-42-37 Page 4310 Oct 2007© Honeywell International Inc. Do not copy without express permission of Honeywell.
COMPONENT MAINTENANCE MANUALPart No. 066-50007Table 8. PWM Pin FunctionsPWM Pin FunctionU2-15 (VIN) +28 V dc input voltageU2-2 (RT) Sets the internal oscillator ramp charge current andswitching frequency with resistor R23 and capacitorC36.U2-1 (KFF) Sets the output voltage and the slope of the voltageramp with resistor R25.U2-6 (SD/SS) Soft start programming pinU2-4 (SYNC) Synchronization inputU2-7 (VFB) Inverted input to the error amplifierU2-12 (SW) Used for over-current senseU2-16 (ILIM) Current limit pin, used to set the over-currentthreshold.U2-8 (COMP) Output of the error amplifier, input to the PWMcomparator.U2-10 (LDRV) Gate drive for the N-channel synchronous rectifierQ4. This pin switches from MOSFET Q4 on toground, MOSFET Q4 offU2-14 (HDRV) Floating drive for the high-side P-channel MOSFETQ5. This pin switches from MOSFET Q3 off toMOSFET Q3 on(e) The 28 V dc is converted to an ac voltage by the switching action off transistorsQ3 and Q4. Transistor Q3 is a P-channel MOSFET device. It is turned on and offby the voltage on U2-14 (HDRV). Transistor Q4 is an N-channel MOSFET device.It is turned on and off by the voltage on U2-10 (LDRV).(f) The ac voltage generated by transistors Q3 and Q4 is rectified by diodes D14 andD15. The rectified dc voltage is filtered by L2 and capacitors C30 thru C35.F. Rear Interconnect Module (Subtask 34-42-37-870-014-A01)(1) See Figure 2006 (GRAPHIC 34-42-37-99B-816-A01) for a schematic diagram ofthe rear interconnect module. The rear interconnect module supplies the antennaconnections, power, and signal/data paths between the rear connector of the unit andthe ALA-52B internal circuits.(2) The power supply input lines are straight through connections between rear connectorJ1-BP-9 to pins 1 thru 4 of connector J14.(3) The I/O signal lines are grouped on the schematic diagram into four categories:• ARINC 429 inputs• ARINC 429 outputsEFFECTIVITYALL 34-42-37 Page 4410 Oct 2007© Honeywell International Inc. Do not copy without express permission of Honeywell.
COMPONENT MAINTENANCE MANUALPart No. 066-50007• Discrete inputs• Discrete outputs.(4) Wirewound resistors, 100 ohm, 1 watt, along with TVS devices provide lightningproctection for all ARINC inputs.(5) All ARINC outputs have TVS devices to provide lightning protection. The lightningcurrent limiting is provided by the connected LRUs.G. Front Panel Module (Subtask 34-42-37-870-015-A01)(1) See Figure 2005 (GRAPHIC 34-42-37-99B-815-A01) for a schematic diagram of theLED CCA. The LED CCA is an interface to an operator by the use of three LEDsand a test switch.(2) The LEDs D1, D2, and D3 display either red or green light when turned on. TheLED D1 shows the radio altimeter status. The LED D2 shows the receive antennastatus and D3 shows the transmit antenna status. The test switch S1 is used totest the entire unit operation.(3) A front panel connector is used for a handheld remote device or to program the unit.EFFECTIVITYALL 34-42-37 Page 4510 Oct 2007© Honeywell International Inc. Do not copy without express permission of Honeywell.
COMPONENT MAINTENANCE MANUALPart No. 066-50007Blank PageEFFECTIVITYALL 34-42-37 Page 4610 Oct 2007© Honeywell International Inc. Do not copy without express permission of Honeywell.
COMPONENT MAINTENANCE MANUALPart No. 066-50007TESTING AND FAULT ISOLATION1. Planning Data (TASK 34-42-37-99C-801-A01)A. Reason for the Job (Subtask 34-42-37-99C-001-A01)(1) Use the test procedures in this section to do tests and fault isolate the ALA-52B.(2) The function of the test procedures is to find if there is a failure in the operationof the ALA-52B.B. Job Setup Data (Subtask 34-42-37-99C-002-A01)(1) You can use equivalent alternatives for the special tools, fixtures, equipment, andconsumable materials. The user must find equivalent alternatives.(2) Refer to Table 1001 for the specified special tools, fixtures, and equipment in thissection. If this section refers to online data, refer to that data for the specified specialtools, fixtures, and equipment.Table 1001. Special Tools, Fixtures, and EquipmentNumber Name11730A RF power sensor cable (CAGE 1MY97)300-90273-0504 memory card interface module (CAGE 97896)704-2899-001 ALA-52B ATP cable (CAGE 97896)8074177-0001 ISP programming cable (CAGE 97896)951-0409-00X COMNAV RTS (CAGE 97896)951-0423-001 front panel interface adapter (CAGE 97896)998-3804-5XX ATP software (CAGE 97896)998-3853-503 (or later) Delta software (CAGE 97896)Microsoft Windows 2000 or above (optional source)ALT 52A Altitude simulator (CAGE 97896)CA1267-60 RA power meter cable (CAGE 1UKX3)CA1267-60 RA spectrum analyzer cable (CAGE 1UKX3)E4418B RF power meter (CAGE 1MY97)E9304A RF power sensor (CAGE 1MY97)FSEB30 or FSIQ7 Spectrum analyzer (CAGE 82199)Version 16.x LSC isp VM system software (CAGE 66675)EFFECTIVITYALL 34-42-37 Page 100110 Oct 2007© Honeywell International Inc. Do not copy without express permission of Honeywell.
COMPONENT MAINTENANCE MANUALPart No. 066-50007WARNING: BEFORE YOU USE A MATERIAL, REFER TO THE MANUFACTURERS’MATERIAL SAFETY DATA SHEETS. SOME MATERIALS CAN BEDANGEROUS.CAUTION: DO NOT USE MATERIALS THAT ARE NOT EQUIVALENT TO HONEYWELLSPECIFIED MATERIALS. MATERIALS THAT ARE NOT EQUIVALENTCAN CAUSE DAMAGE TO THE EQUIPMENT AND CAN MAKE THEWARRANTY NOT APPLICABLE.(3) Refer to Table 1002 for the specified consumable materials in this section. If thissection refers to online data, refer to that data for the specified consumable materials.Table 1002. Consumable MaterialsNumber NameNot applicable Not applicable2. Procedure (TASK 34-42-37-810-801-A01)A. Job Setup (Subtask 34-42-37-810-001-A01)WARNING: BEFORE YOU USE A MATERIAL, REFER TO THE MANUFACTURERS’MATERIAL SAFETY DATA SHEETS. SOME MATERIALS CAN BE DANGEROUS.CAUTION: DO NOT USE MATERIALS THAT ARE NOT EQUIVALENT TO HONEYWELLSPECIFIED MATERIALS. MATERIALS THAT ARE NOT EQUIVALENT CANCAUSE DAMAGE TO THE EQUIPMENT AND CAN MAKE THE WARRANTYNOT APPLICABLE.CAUTION: THE ALA-52B CONTAINS ESDS ITEMS. USE INDUSTRY APPROVEDPRECAUTIONS.(1) Obey the precautions.(2) Refer to Table 1003 for a list of test procedures that are included in this section.Table 1003. Test ProceduresProcedure PartNumber Revision Used On Part Number Reference076-1132-001 B066-50007-1111 Figure1001(GRAPHIC34-42-37-99B-810-A01)B. Testing of the ALA-52B (Subtask 34-42-37-810-002-A01)(1) Use Figure 1001 (GRAPHIC 34-42-37-99B-810-A01) to do a test of the ALA-52B, PartNo. 066-50007-1111.C. Job Close-up (Subtask 34-42-37-810-003-A01)(1) Not applicable.EFFECTIVITYALL 34-42-37 Page 100210 Oct 2007© Honeywell International Inc. Do not copy without express permission of Honeywell.
COMPONENT MAINTENANCE MANUALPart No. 066-50007Figure 1001. (Sheet 1 of 12) ALA-52B Test Procedure (GRAPHIC 34-42-37-99B-810-A01)EFFECTIVITYALL 34-42-37 Page 100310 Oct 2007© Honeywell International Inc. Do not copy without express permission of Honeywell.
COMPONENT MAINTENANCE MANUALPart No. 066-50007Figure 1001. (Sheet 2 of 12) ALA-52B Test Procedure (GRAPHIC 34-42-37-99B-810-A01)EFFECTIVITYALL 34-42-37 Page 100410 Oct 2007© Honeywell International Inc. Do not copy without express permission of Honeywell.
COMPONENT MAINTENANCE MANUALPart No. 066-50007Figure 1001. (Sheet 3 of 12) ALA-52B Test Procedure (GRAPHIC 34-42-37-99B-810-A01)EFFECTIVITYALL 34-42-37 Page 100510 Oct 2007© Honeywell International Inc. Do not copy without express permission of Honeywell.
COMPONENT MAINTENANCE MANUALPart No. 066-50007Figure 1001. (Sheet 4 of 12) ALA-52B Test Procedure (GRAPHIC 34-42-37-99B-810-A01)EFFECTIVITYALL 34-42-37 Page 100610 Oct 2007© Honeywell International Inc. Do not copy without express permission of Honeywell.
COMPONENT MAINTENANCE MANUALPart No. 066-50007Figure 1001. (Sheet 5 of 12) ALA-52B Test Procedure (GRAPHIC 34-42-37-99B-810-A01)EFFECTIVITYALL 34-42-37 Page 100710 Oct 2007© Honeywell International Inc. Do not copy without express permission of Honeywell.
COMPONENT MAINTENANCE MANUALPart No. 066-50007Figure 1001. (Sheet 6 of 12) ALA-52B Test Procedure (GRAPHIC 34-42-37-99B-810-A01)EFFECTIVITYALL 34-42-37 Page 100810 Oct 2007© Honeywell International Inc. Do not copy without express permission of Honeywell.
COMPONENT MAINTENANCE MANUALPart No. 066-50007Figure 1001. (Sheet 7 of 12) ALA-52B Test Procedure (GRAPHIC 34-42-37-99B-810-A01)EFFECTIVITYALL 34-42-37 Page 100910 Oct 2007© Honeywell International Inc. Do not copy without express permission of Honeywell.
COMPONENT MAINTENANCE MANUALPart No. 066-50007Figure 1001. (Sheet 8 of 12) ALA-52B Test Procedure (GRAPHIC 34-42-37-99B-810-A01)EFFECTIVITYALL 34-42-37 Page 101010 Oct 2007© Honeywell International Inc. Do not copy without express permission of Honeywell.
COMPONENT MAINTENANCE MANUALPart No. 066-50007Figure 1001. (Sheet 9 of 12) ALA-52B Test Procedure (GRAPHIC 34-42-37-99B-810-A01)EFFECTIVITYALL 34-42-37 Page 101110 Oct 2007© Honeywell International Inc. Do not copy without express permission of Honeywell.
COMPONENT MAINTENANCE MANUALPart No. 066-50007Figure 1001. (Sheet 10 of 12) ALA-52B Test Procedure (GRAPHIC 34-42-37-99B-810-A01)EFFECTIVITYALL 34-42-37 Page 101210 Oct 2007© Honeywell International Inc. Do not copy without express permission of Honeywell.
COMPONENT MAINTENANCE MANUALPart No. 066-50007Figure 1001. (Sheet 11 of 12) ALA-52B Test Procedure (GRAPHIC 34-42-37-99B-810-A01)EFFECTIVITYALL 34-42-37 Page 101310 Oct 2007© Honeywell International Inc. Do not copy without express permission of Honeywell.
COMPONENT MAINTENANCE MANUALPart No. 066-50007Figure 1001. (Sheet 12 of 12) ALA-52B Test Procedure (GRAPHIC 34-42-37-99B-810-A01)EFFECTIVITYALL 34-42-37 Page 101410 Oct 2007© Honeywell International Inc. Do not copy without express permission of Honeywell.

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