IP Mobilenet ECSDT450TX User Manual 8a

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Document Description	8a
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Document Type	User Manual
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Date Submitted	1999-06-07 00:00:00
Date Available	1999-03-24 00:00:00
Creation Date	2001-06-19 08:27:59
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Document Lastmod	2001-06-19 08:28:01
Document Title	8a

Instrument Specialties Company, Inc. — World Compliance Center
EXHIBIT C:
DT450 MX91QB FSK Modem Manual
| "mum-nun IVM'IJIMJNE. IVIIXGd Slgnal IUS
DATA BULLETIN
MX91 QB 4-Level FSK Modem Data Pump
PRELIMINARY INFORMATION
Features Applications
0 4-Level Root Raised Cosine FSK Modulation . Wireless Data Terminals
- Half Duplex, 4800 to 19.2kbps . Two Way Paging Systems
. Increase Channel Bit Hate/Hz . Digital Radio Systems
Wide Area Wireless Data Broadcasts
Point to Point Wireless Data Links
. Full Data Packet Framing
. Impulse and NH2 Signal Modes
- Enhanced Performance in Noisy Conditions
. Error Detection and Error Correction
. Low Power 3.3V/5.0V Operation
RADIO MX91QB
HOST uc
ANALOG TX DATA AND
MODULATOR CONTROL BUS
RF
DISCRIMINATOR
The MX91QB is a low vottage CMOS device containing all of the baseband signal processing and Medium Access Control
(MAC) protocol functions required for a high performance 4-level FSK Wireless Packet Data Modern. tt interfaces with the
modem host uC and the radio modulation/demodulation circuits to deliver reliable two-way transfer of the application data
over a wireless link.
The MX91QE assembles application data received from the host pC, adds iorward error correction (PEG) and error
detection (CRC) information, and interleaves the result for burst-error promotion, After automatically adding symbol and
frame sync codewords. the data packet lS converted into filtered 4-Ievel analog signals for modulating the radio
transmitter.
In receive mode, the MX91QB performs the reverse function using the analog signals from the receiver discriminator.
Alter error correction and removal of the packet overhead, the recovered application data is applied to the host uC. CHC
detected residual uncorrected data errors will be flagged, A readout ol the SNR value during receipt of a packet is also
provided
The MX9198 uses data block sizes and FEC/CFIC suitable for applications where high speed transfer of data over
narrow-band wireless links is required The device is programmable to operate at standard bit rates from a wide range of
XtaI/clock frequencies.
The MXQtQB may be used with a 3.0V to 5.0V power supply and is available in the following package styles:
24-pin SSOP (MX91QBDS), 24-pin SOIC (MX91 QBDW). 24-pin PLCC (MX91 QBLH). and 24-pin PDIP (MX919EP).
SYS EM
APPLICATION
PROCESSING
ANALOG RX
Section
CONTENTS
Page
1 Block Diagram ........ .. .............. ........... . .................................................................................... 6
2 Signal List ................. . ............. ......................... ......................................... . ................. ..
3 External Components ............................................... ..................................
4 General Description ..... ......................................... ........ . ...................................
4.1 Description of Blocks.
4.1 .1 Data Bus Butlers
4.1.2 Address and WW Decode
413 Status and Data Quality Registers...
4.1.4 Command, Mode, and Control Registe
4.1.5 Data Buffer ................
4.1.6 CRC Generator/Checke
4.1.7 FEC Generator/Checker .....
4.1.8 Interleave/Detmeneave Suite
4.1.9 Frame Sync Detect
4.1.10 Rx Input Amp
4.1.11 RRC Low Pass Filter.
4.1.12 Tx Output Bufler ...........
4.1.13 Rx LeveVCiock Extraction
4.1.14 Clock Oscillator and Divider
4.2 Modem - uC Interactio
4.3 Binary to Symbol Translation
.9
.9
.9
.9
.9
.9
.9
4.4 Frame Stmcture ..................................................................................................................................... 13
4.5 The Programmers View.
4.5.1 Data Block Buffer
4.5.2 Command Register ......
4.5.2.1 Command Register 5 AQSC- Acquire Symbol Clock.
4.5.2.2 Command Register 56: AQLEV Acquire Receive Signal Levels
4.5.2.3 Command Register 85: CR
4.5.2.4 Command Register 84: TXIMP - Tx LeveVlmpulse Shape.
4.5.2.5 Command Register BB - Reserved
4.5.2.6 Command Register 82 B1, BO: TASK
4.5.2.7 NULL. No elfec't.
4.5.2.8 SFSH: Search form Frame Sync plus Header Block
4.5.2.9 RHB: Head Header Block" ..
4.5.2.10 RlLB: Read ‘Intennediate' or 'Last‘ Block
4.5.2.11 SFS: Search for Frame Sync ......
4.5.2.12 R48: Read 4 Symbols .......
4.5.2.13 T24S: Transmit 24 Symbols.
4.5.2.14 THB: Transmit Header Block'......
4 5.2.15 TIE: Transmit Intermediate BIocth
4.52.16 TLB: Transmit Last Block
4.52.17 T4S: Transmit 4 Symbols
4.5.2.18 RESET: Stop any current action .................................................................................
4.5.2.19 Task Timing
4.52.20 HRC Filter Delay
4.5.3 Control Hegister....
4.5.3.1 Control Register B7, es: (XDIV - Clock Divt ion Ratio
4.5.3.2 Control Register 85. 84: FSTOL — Frame Sync Tolerance to Inexact Matches
4.5.3.3 Control Register BS, 82: LEVRES - Level Measurement Modes ............
4.5.3.4 Control Register 31, BO: PILBW - Phase-Locked Loop Bandwidth Modes
4.5.4 Mode Register...
4.5.4.1 Mode Register B7: IRQEN- WOOutput Enable ........................................................................ 23
4.5.4.2 Mode Register 86: INVSYM - Invert Symbols...
4.5.4.3 Mode Register as TX/R_x -Tx/Rx Mode...
4.5.4.4 Mode Register 84: RXEYE- Show Rx Eye
4.5.4.5 Mode Register B3: FSAVE - Powersave
4.5.4.5 Mode Register BE, 51. an
45.5 Status Register
4.5.5.1 Status Register B7: IRQ - Interrupt Request .........
4.5.5.2 Status Register BS: BFREE - Data Block Buffer Fre ..
4.5.5.3 Status Register BS: IBEMPTY - interleave Butter Empty ............................................................... 25
4.5.5.4 Status Register B4: DIBOVF - Dre—interleave Buffer Overflow
. 4.5.5.5 Status Register 83: CRCERR - CRC Checksum Error ....... ..
4.5.5.6 Status Register B2, B1, 5.7 ............................................................................................................ 26
4.5.6 Data Quality Register.. ..26
4.6 CRC, PEG. and Interieaving
4.6.1 Cyclic Redundancy Codes.
4.6.1.1 CRC1
4.5.1.2 CRCZ
4.5.1.3 Forward Error Correcuon
4.8.1.4 Interleaving
4.7 Transmitted Symbol Shape.
Application ..................
5.1 Transmit Frame Example.
52 Receive Frame Example.
5.3 Clock Extraction and Level Measurement Systems ........
5.3.1 Supported Types of Systems......_-....
5.3.2 Clock and Level Acquisition Proudures with RF Carrier Detect.
5.3.3 Clock and Level Acquisition Procedure without RF Carrier Detect
5.3.4 Automatic Acquisition Functions
5.4 AC Coupling
5.5 Radio Performance .
5.6 Received Signal Quality Monitor .. .. 39
6 Performance Specification
6.1 Electrical Performance .....
6.1.1 Absolute Maximum Ratings ......................
6.1.2 Operating Limits ......
5.1.3 Operating Characteristics .
6.1.4 Operating Characteristics Notes:
6.1.5 Timing
6.1.6 Typical Bit Error Rate. .
6.2 Packaging
LMX-COM, Inc. Reserves the right to change specifications at any time and without noticej
Figures
Figure Page
_______—_—_———-—-——
lgure 1: Block Diagram ..
Figure 2: Recommended External Components
Figure 3: Typical Modem uC connections
Figure 4: Translation of Binary Data to Filtered 4-Level Symbols in Tx Mod
Figure 5: RRC Filter Frequency Response vs. Bit Rate (including the external RC filler R4/Cs)...
Figure 6: FIRC Filter Frequency Response vs. Symbol Rate (including the external RC filter Fla/C5
Figure 7: Over—Air Signal Format ..................................................................................... , ................................................ 13
Figure 3: Alternative Frame Structures
Figure 9: Transmit Task Overlapping
Figure 10: Receive Task Overlappin
Figure 11: Transmit Task Timing Diagram
Figure 12: Receive Task Timing Diagram
Figure 13: HRS Low Pass Filter Delay
Figure 14: Ideal 'RXEYE' Signal ...... ..
Figure 15: Typical Data Quality Reading vs S/N
Figure 15: Input Signal to FIRC Filter“ in Tx Mode for TXIMP = 0 and 1 ...........
Figure 17: Tx Signal Eye TXIMP = 0
Figure 18: Tx Signal Eye TXIMP =1
Figure 19: Transmit Frame Example Flowchart, Main Program“
‘igure 20: Tx Interrupt Service Routine.
Figure 21: Receive Frame Example Flowchart, Main Program
Figure 22: Rx Interrupt Service routine ..............
Figure 23: Acquisition Sequence Timing ......
Figure 24: Effect of AC Coupling on BEFI (without FEC)
Figure 25: Decay Time AC Coupling
Figure 26: Typical Connections between Radio and MX919
Figure 27: Received Signal Quality Monitor Flowchart ......
Figure 28: pl? Parallel Interface Timings ....................
Figure 29: Typical Bit Error Rate With and Vlfithout FEC
Figure 30: 24-pin SOIC Mechanical Outline: aide/as paflfla. MX9795P‘.
Figure 31: 24-pin SSOF Mechanical Outline: Orde/aspan‘ no, MXQIQBDS.
Figure 32: 24-pin PLCC Mechanical Outline : Orderaspaflna. MXQISHLH.
Figure 33: 24-pin PDIP Mechanical Outline: Dive/aspen no. MX9795P ........................................................................ 46
1 Block Diagram
DATA
STATUS
m Hc’é‘é‘t‘lsJTTEYH
l I * I
D0
D1
DZ COMMAND MODE CONTROL
I D3 REGISTER REGISTER REGISTER
§§ m
ER" 05 DATA
zE 06 4“, BUFFER
03 D7
5.
PEG
gt ENCODER/
DECODEH
55“
A0
M v INTERLEAVE/ FRAME
- ”0 DE-INTERLEAVE SYNCDEI'ECT
VDD
VBIAS
TxS bols HXS bols
RXAMF’
CLOCK
OSCILLATOR
AND
DIV|DE RS
Tx Output Buffer
CLOCK
Figure 1: Block Diagram
2 Signal List
11
input
Pin No. Signal Type Description |
1 W _rouqJUI A ‘wire—OFlable' output lor connection to the host uC's lnten-upt
Request input. When active, this output has a low impedance
pull down to Vss- it has a high impedance when inactive,
2 D7 BUS
5 Pins 2-9 (D7-D0) are S-bit, bidirectional, S-state
6 DB BUS pC interface data lines
Read An active low logic level input used to control the reading
of data lrom the modern into the host pC.
of data into the modern from the host itC.
Write. An active low logic level input used to control the writing ‘|
Negative supply (ground).
13
Chip Select. An active low logic level input to the modem used
to enable a data read or write operation.
19
DOC 1
capacitive coupled to Vss
20 TXOUT output TX signal output from the modem.
14 A0 input Logic level modem register select input
15 A1 input Logic level modem register select input
16 FA]. output Output of the on-chip oscillator.
17 XTAUCLOCK input input to the on—chip oscillator, for an external Xtal circuit or
clock,
18 DOC 2 output Connection to the Fix level measurement circuitry. Should be
output
capacitive coupled to Vss~
Connection to the Fix level measurement circuitry. Should be
21 V5,“ output A bias line for the internal circuitry held at VDD 12. This pin must
be bypassed to Vss by a capacitor mounted close to the device
pins.
22 I RXIN input - Input to the Rx input amplifier.
23 I RXAMPOUT output Oulput of the Rx input amplifier.
24 VDD power Positive supply. Levels and voltages are dependent upon this
supply. This pin should be bypassed to Vss by a capacitor
mounted close to the device pins.
3 External Components
FromeFM
rm
D7 2 Discriminator
UJ D6 3
O ToTxFrequency
E 33 2 20 Modulator
L”
5 D3 6 MX91QB 19
E D2 7 18
51 D1 8 17
6 DO 9 16 c7 06 cs 02
E H5 10 15
6 W“ 11 XTAL/CLOCK
17
(3; 59 0
A0
Recommended External Component Notes:
1.
2,
See Section 4.1.10.
For best resuls. a crystal oscillator design should drive the clock inverter input with signal levels of at least 40% of
VDD, peak to peak Tuning fork crystals generally cannot meet this requirement. To obtain crystal oscillator design
assistance, consult your crystal manufacturer
The values used for C3 and C4 should be suitable for the frequency oi the crystal X1. As a guide, values (including
stray capacitance) of 33pF at 1MHz falling to tspF at 10MHz will generally prove suitable. Crystal frequency
tolerances are discussed in Section 4.5.3.4.
Values CS and CB should be equal to 750,000 I symbol rate, e.g.
Values ca and C7 should be equal to 50,000! symbol rate, e.g.
Symbol Rate
2400 symbols/second
4800 symbols/second
9600 symbols/second
Symbol Rate
2400 symbols/second
4800 symbols/second
9500 symbols/second
4 General Description
4.1 Description of Blocks
1.1.1 Data Bus Buffers
Eight bi-directional 3-state logic level buffers between the modem's internal registers and the host pC's data bus lines.
4.1.2 Address and RM Decode
This block controls the transfer of data bytes between the pic and the modefl's internal registers according to the state of
the Write and Read Enable inputs (WR and RD ), the Chip Select input(CS ), and the Register Address inputs
A0 and At.
The Data Bus Butters, Address, and Fl/W Decode blocks provide a byte»wide parallel uC interface, which can be
memorymapped, as shown in Figure 3.
Address Bus Address Decode
Circuit
- W) pull up
resistor
Figure 3: Typical Modem uc connections
4.1.3 Status and Data Quality Registers
Two, a-bit registers which the pc can read, to determine the status of the modem and received data quality.
4.1.4 Command, Mode, and Control Registers
The values written by the [AC to these B-b‘rt registers control the operation of the modem,
4.1.5 Data Buffer
A 12-byte bul‘ler used to hold rece'we or transmit data to or from the |.tC.
4.1.6 CRC Generator/checker
A circuit which generates (in transmit mode) or checks (in receive mode) the Cyclic Redundancy Checksum bits. which
may be included in the transmitted data blocks so the receive modem can detect transmission errors.
4.1.7 FEC Generator/Checker
In transmit mode, this circuit adds Forward Error Correction bits to the transmitted data, resulting in the conversion of
binary data to 4—level symbols. In receive mode, this circuit translates received 4-Ievel symbols to binary data. using the
FEC |nfonnation to correct a large proportion ol transmission errors.
4.1.8 InterleavelDe—Intierluve Butler
This circuit interleaves data symbols within a block before transmission and de—intedeaves the received data so that the
FEC system is best able to handle short noise bursts or fades.
4.1.9 Frame Sync Detect
This circuit, which is onty active in receive mode. is used to look for the 24-symbol Frame Synchronization pattern that is
transmitted to mark the start of every frame.
4.1.10 Rx input Amp
This amplifier allows the received signal input to the modem to be set to the optimum level by suitable selection of the
external components R1 and H2. The value of R1 should be calculated to give 0.2 x VDD volt5p.p at the RXAMPOUT pin
for a received '.,.+3 +3 -3 -3 ...' sequence,
A capacitor may be placed in series with R1 if ac coupling of the received signal is desired (see Section 5.4), otherwise
the DC level of the received signal should be adjuswd so that the signal at the modem‘s FlXAMPOUT pin is centered
around Vans (van/2),
4.1.11 RRC Low Pass Filler
This filter. which is used in both transmit and receive modes, is a linear-phase lowpass filter with a Fool Raised Cosine’
frequency response defined by:
1-b
H(l)=1 for 0 5 k?
fr, fl <1 m
'27 - 5 2T
1+b
H(f).=0 for 1 > —2T
Where b—OZ T-——1—v
_ ' ' _symbol rate
This frequency response is illustrated in Figure 5 an! Figure 6.
In transmit mode, the 4-level symbols are passed through this filter to eliminate the high frequency components which
would otherwise cause interference into adjacent radio channels. The input applied to the RRC Tx filter may be impulses
or fullawidth symbols depending on the setting of the Command Register TXIMP bit. See Section 4 7
l- ----- '
: input Data :
______ l
Frequency
modulator
Figure 4: Translation of Blmry Data to Filtered 4-Levet Symbols in Tx Mode
In receive mode, the filter is used to reject HF helm and to equalize the received signal to a form suitable for extracting
the 4-level symbols, The equalization charactenst'xs are determined by the setting of the Command Register TXIMP bit
0.1 0,2 0.3 0.4 0.5
Frequency / Bit Rate
Figure 5: HBO Filter Frequency Response vs. Bit Rate (including the external RC filter R4ICS)
o 0.2 0.4 0.5 0.5 1.0
Frequency/ Symbol Rate
Figure 5: RRC Filter Frequency Response vs. Symbol Rate (including the external RC filter R4lc5)
4.1.12 Tx Output Buffer
This is a unity gain amplifier used in the transmit mode to buffer the output of the Tx low pass filter. in receive mode. the
input of this buffer is connected to Val/is, unless the RXEYE bit of the Control Register is ‘1', in which case it is connected
to the received signal. When changing from Rx to Tx mode, the input to this butler will be connected in VBIAS for 8 symbol
times while the RHC filter settles.
Note: The RC low pass filter formed by the external components H4 and Cs between the TXOUT pin and the input to the
radio's frequency modulator forms an imponam part of the transmit signal filtering. These components may form
part of any DC level-shifting and gain adjustment circuitry. The value used for CS should take into account stray
circuit capacitance, and its ground connection should be positioned to give maximum attenuation of high frequency
noise into the modulator.
The signal at the TXOUT pin is centered around sz. it is approximately 0.2 x VDD volts”. for a
continuous ‘+3 +3 -3 -3...' pattem with TXIMP = O. For typical Tx Eye Diagrams refer to Section 4.7. Figure 17 and
Figure 15. For typical Rx Eye Diagrams refer to Section 4.5.4.4, Figure 14.
A capacitor may be placed in series with the input to the frequency modulator ii AC coupling is desired. See Section 5.4.
4.1.13 Rx Level/Clock Extraction
These circuits, which operate only in receive mode, derive a symbol rate clock from the received signal and measure the
received signal amplitude and DC offset. This information is then used to extract the received 4-level symbols and also to
rovide an input to the received Data Quality measuring circuit. The external capacitors CG and C7 form part of the
received signal level measuring circuit.
The capacitors CS and C7 are driven from a very high impedance source so any measurement of the vottages on the
DOC pins must be made via high input impedance (MOS input) voltage followers to avoid disturbance of the level
measurement circuits.
Further details of the level and clock extraction functions are given in Section 5.3.
4.1.14 Clock Oscillator and Dividers
These circuits derive the transmit symbol rate (and the nominal receive symbol rate) by frequency division of a reference
frequency which may be generated by the on-ohip Xtal oscillator or applied from an external source.
Note: if the on-chip Xtal oscillator is to be used, then the external components X1, C3, C4, and R3 are required. if an
external clock source is to be used. then it shomd be connected to the XTALJCLOCK input pin, the XTAL pin
should be left unconnected, and X1 , C3, 04, and H3 should not be installed.
4.2 Modem - pC Interaction
in general, data is transmitted over-air in the form oi messages. or ‘Frames', consisting of a 'Frame Preamble" followed by
one or more formatted data blocks. The Frame Preamble includes a Frame Synchronization pattern designed to allow the
receiving modem to identify the start of a frame. The following data blocks are constructed from the ‘raw‘ data using a
combination of CEO (Cyclic Redundancy Checksum) generation, Forward Error Correction coding, and Interleaving.
Details of the message formats handled by the modem are provided in Section 4.4, Figure 7, and Figure B.
To reduce the processing load on the associated pC. the MX919E modem has been designed to perform as much of the
computationally intensive work involved in Frame formatting and de-fomtatting and (when in receive mode) searching for
and synchronizing onto the Frame Preamble. in normal operation. the modem will only require servicing by the pC once
per received or transmitted block.
”‘herefore, to transmit a block, the controlling uC needs only to load the unformatted 'raw‘ binary data into the modem's
data Block Buffer, then instruct the modem to format and transmit that data. The modem will then calculate and add the
CRC bits as required, encode the result as 4-Ievel symbols (with Fomard Error Correction coding), and interleave the
symbols before transmission.
In receive mode. the modern can be instructed to assemble a block's worth of received symbols, de-interleave the
symbols. translate them to binary, perform Forward Error Correction, and check the resulting CHC before placing the
received binary data into the Data Block Bufler for the pic to read.
The modem can also handle the transmission and reception oi unforrnatted data using the T48. T248. and R43 tasks as
described in Sections 4.3 and 45.2. These tasks are normally used for the transmission of Symbol and Frame
Synchronization sequences. These tasks may also be used for the transmission and reception of special test patterns or
special data formats. In such a case, care should be taken to ensure that the transmitted TXOUT signal contains enough
level and timing infon'nation for the receiving modem‘s level and clock extraction circuits to function correctly.
See Section 5.3.
4.3 Binary to Symbol Translation
Although the over-air signal, and therefore the signals at the modern TXOUT and RXlN pins, consists of A—Ievel symbols,
the raw data passing between the modem and the uC is in binary form. Translation between binary data and the 4-Ievel
symbols is done in one of two ways, depending on the task being performed.
1. Direct way: (simplest form) - converts between 2 binary bits and a single symbol.
Accordingly, 1 byte = 4 symbols = 8 bits. and one byte translates to four symbols for the T45 and R43 tasks and six bytes
translates to twenty-tour symbols for the T248 task described in Section 4 5 2,
MSE LSB
Bits: 7 e 5 4 3 2 1 | o
Symbols: “n— d
sent first sent last
2. PEG way: (more complicated) - essentially translates groups of 3 binary bits to pairs Of 4-Ievel symbols using 3
Forward Error Correcting coding scheme for the block oriented tasks THB, TIB, TLB. RHB, and RILB described in Section
4.5.2,
4.4 Frame Structure
Figure 7 shows how an overvair message frame may be constructed lrom a sequence of: 3 Symbol Sync pattern
(preamble), a Frame Sync pattern, and one or more Header, ‘Intermediate' or 'Last' blocks,
uC binary data stored
in MXSWB data block
memory configured as
header, Nermadate, or
last biodi by W9! 95
task being matted.
FEC Trellis Coding / Decoding
(Error Correction)
Symbolsync: atleast24 vyrrbois oils-iii +3 -3 -3..‘sequenoe
Figure 7: Over-Air Signal Format
The "Header block is self-contained and includes its own checksum (CRC1). it would normally carry information such as
the address of the calling and called parties. the number of following blocks in the frame (if any). and miscellaneous
control information. The number of following blocks (if any) is required to allow the Rx device software to expect the Last
Block and interpret it as a Last Block rather than an Intermediate Block. There is no other indicator to differentiate a Last
Block and an Intermediate Block.
The 'lntzermediate' block(s) contain only data. the checlsum for all of the data in the 'lntermediate‘ and 'Last‘ blocks
(CRCZ) being contained at the end of the 'Last‘ block.
This arrangement, while efficient in terms of data capacity, may not be optimum for poor signal-to-noise conditions, since
a reception error in any one of the ‘lntermediate' or ‘Last‘ blocks would invalidate the whole frame. In such conditions.
increased throughput may be obtained by using the ‘Header' block format for all blocks of the lrame, so blocks that are
received correctly can be identified as such, and do not need to he re-transrnrtted These, and some other possible frame
structures, are shown in FIgure 8.
. , SYMBOL FRAME . ‘ . .
SYNC SYNC HEADER BLOCKS
5 SYMBOL FRAME . . 'LAS‘I“
' ' SYNC SYNC INTERMEDIATE BLOCKS BLOCK _ ,
C SYMBOL FRAME , .
' ' SYNC INTERMEDIATE BLOCKS . .
Figure 3: Alternative Frame Structures
The stnge performs the entire block lonnatting and ole—formatting required to convert data between uC binary form and
Over-Air as shown in Figure 7.
4.5 The Programmer's View
To the programmer, the modem appears as 4 write only B-bit registers, shadowed by 3 read only registers. The individual
registers are selected by the A0 and A1 chip inputs:
Write to Modern Read from Modem
0 Data Butter Data Butter
1 Command Register Status Register
0 Control Register Data Quality Register
1 Mode Register not used A
Note: There is a minimum time allowance between accesses of the modem’s registers, see Section 6.1 ,5.
4.5.1 Data Block Butter
This is a 12-byte read/write butter used to transfer data (as opposed to command, status, mode, data quality or control
information) between the modern and the host pC.
To the uC, the Data Block Buffer appears as a single E-bit register. The modern ensures that sequential uC reads or
writes to the buffer are routed to the correct locations within the buffer.
The “0 should only access this buffer when the Status Register BFREE (Buffer Free) bit is "1‘.
The buffer should only be written to while in Tx mode and read from while in Rx mode. Note that in recere mode, the
modem will function correctly even it the received data is not read from the Data Buffer by the uC.
4.5.2 Command Register
Writing to this register tells the modem to periorrn a specific task as indicated by the TASK bits and modified by the
A080, AOLEV, CBC, and TXIMP bits.
Command Register
AQSC AQLEV CRC TXlMP Reserved
Seth’fl'
When there is no action to periorm, the modern will be in an ‘idle' state. It the modem is in transmit mode. the input to the
Tar FtFtC filter will be connected to VE'AS. in receive mode. the modem will continue to measure the received data quality
and extract symbols from the received signal, supplying them to the de»interleave buffer, otherwise these received
symbols are ignored.
4.5.2.1 Command Register B7: AQSC - Acquire Symbol Clock
'his bit has no effect in transmit mode.
In receive mode, when a byte with the A050 bit set to ‘1' is written to the Command Register, and TASK is not set to
RESET, it initiates an automatic sequence designed to achieve symbol timing synchronization with the received signal as
quickly as possible. This involves setting the Phase Locked Loop of the received bit timing extraction circuits to its widest
bandwidth, then gradually reducing the bandwidth as timing synchronization is achieved, until it reaches the 'normal‘ value
set by the PLLBW bits of the Control Register. ’
Setting this bit to 'O‘ (or changing itfrorn ‘1' to ‘0') has no effect. however; the acquisition sequence will be re-started every
time a byte written to the Command Register has the A080 bit set to ‘1'.
The use of the symbol clock acquisition sequence is described in Section 5.3.
4.5.2.2 Command Register 55: AGLEV - Acquire Receive Signal Levels
This bit has no effect in transmit mode.
in receive mode, when a byte with the AQLEV bit set to '1' is written to the Command Register and TASK is not set to
RESET, it initiates an automatic sequence designed to measure the amplitude and DC offset of the received signal as
rapidly as possible. This sequence involves setting the measurement circuits to respond quickly at first. then gradually
increasing their response time, therefore improving the measurement accuracy. until the ‘norrnal‘ value set by the
LEVRES bits of the Control Register is reached.
Setting this bit to '0' (or changing it from '1‘ to ‘0‘) has no effect, however; the acquisition sequence will be restarted every
time a byte written to the Command Register has the AOLEV bit set to '1'.
The use of the level measurement acquisition sequence (AQLEV) is described in Section 5.3.
4.5.2.3 Command Register BS: cm:
This bit allows the user to select between two different initial states of the CRCt and CRC2 checksum generators. When
this bit is set to ‘0'. the CRC generators are initialized to ‘all ones’ as for CCI'I‘I' X25 CRC calculations. When this bit is
to ‘1', the CRC generators are initialized to ‘ail zeros’. Setting this bit to ‘0’ provides compatibility with the MX91Q, a prior
nember of the MX919 device family. Other systems may set this bit as required. Note: This bit must be set correctly
everygtirne the Command Register is written to,
4.5.2.4 Command Register 54: TXIMP - Tx Level/impulse Shape
This bit allows the user to choose between two transmit symbol waveform shapes as described in Section 4.7. Note: This
bit must be set correctly every time the Command Register is written to.
4.5.2.5 Command Register 33 - Reserved
This bit should always be set to ‘0'.
4.5.2.6 Command Register 52, 51, BO: TASK
Operations such as transmitting or receiving a data block are treated by the modem as ‘tasks‘ and are initiated when the
uc writes a byte to the Command Register with the TASK bits set to anything other than the ‘NULL' code.
The no should not write a task (other than NULL or RESET) to the Command Register or write to or read from the Data
Buffer when the BFREE (Buffer Free) bit of the Status Register is ‘0‘.
Different tasks apply in receive and transmit modes.
When the modem is in transmit mode, all tasks other than NULL or RESET instruct the modem to transmit data from the
Data Buffer, formatting it as required. The pc should therefore wait until the BFREE (Buffer Free) bit of the Satus
Register is ‘1'. before writing the data to the Data Block Buffer, then it should write the desired task to the Command
Register. If more than 1 byte needs to be written to the Data Block Buffer, byte number 0 of the block should be written
first
Once the byte containing the desired ask has been written to the Command Register, the modern will:
Set the BFREE (Buffer Free) bit of the Status Register to 'o‘,
Take the data from the Data Block Buffer as quickly as it can - transferring it to the interleave Buffer for eventual
transmission. This operation will start immediately if the modern is ‘idle' (Le. not transmitting data from a previous
task), otherwise it will be delayed until there is sufficient mom in the lnterleave Buffer.
Once all of the data has been transferred iromme Data Block Buffer, the modem vin'lt set the BFREE and IRO bits ol
the Status Register to '1" (causing the chip m output to go low if the IROEN bit of the Mode Register has been set
to '1') to tell the pic that it may write new data and the next task to the modem
This lets the uC write the next task and its assomated data to the modem while the modem is still transmitting the data
from its prevtous task.
Data from 1110 to Block Butter - Tsk 1 data - Task 2 data
Task from 110 to Command | 1
R ister l
eg V
BFREE B‘t of Status Register
IRQ Bit at Status Register
ETC» Output (IRQEN = '1')
TXOUT Signal tram Task 2
Figure 9: Transmit Task Overlapping
When the modem is in receive mode. the uC shout! wait until the BFREE bit of the Status Register is ‘1', then write the
desired task to the Command Register.
Once the byte containing the desired task has been written to the Command Register, the modem will:
Set the BFREE bit of the Status Register in “0‘.
Wait until enough received symbols are in the Devinterleave Buffer.
Decode them as needed and transfer the restifing binary data to the Data Block Butler
Then the modern will set the BFREE and lRQbits of the Status Register to '1', (causing the m output to 90 low it
the IROEN bit at the Mode Register has been set to ‘1‘) to tell the 11C that it may read from the Data Block Butter and
write the next task to the modem. if more that” byte is contained in the buffer, byte number 0 at the data will be
read out first,
In this way, the uC can read data and write a new tsk to the modern while the received symbols needed for th's new task
are being received and stored in the De-interieave Butter.
RXiN Signal
“To ompm (iRQEN =‘1‘)
IRQ Bit at Status Register
BFHEE El! 01 Status Register
Task from no
to Command Register : Task 1 : Task 2
Data from Block Butter to go - Task 1 data
Figure 1a: Receive Task Overlapping
Detailed timings tor the various tasks are provide it Figure 11 and Figure 12.
MX9198 Modem Tasks:
32 B1 aol ReceiveMode Transmit Mode 5
Search ior FS + Header
Read Header Block THB Transmit Header Block
Read intermediate or Last Block TIB Transmit Intermediate Block
Search for Frame Sync TLB Tmnsmit Last Block
Read 4 symbols T4S Transmit 4 symbols
NULL NULL
Cancel any current action RESET Cancel any current action
Transmit 24 symbols
4.5.2.7 NULL: No effect
This “task' is provided so an AQSC or AQLEV command can be initiated without loading a new task.
4.5.2.8 SFSH: Search for Frame Sync plus Header Block
This task causes the modem to search the received signal for a valid 24-symbol Frame Sync sequence followed by
Header Block which has a correct CRCl checksum.
The task continues until a valid Frame Sync plus Header Block has been found.
The search consists of two stages:
First the modem will attempt to match the incoming symbols against the 24-symbol Frame Synchronization pattern to
within the tolerance defined by the FSTOL bits of the Control Register.
Once a match has been found, the modem will read in the next 66 symbols as it they were a 'Header‘ block, decoding
the symbols and checking the CRCt checksum. If this is incorrect, the modem will resume the search, looking for a
fresh Frame Sync pattern.
if the received CRC1 is correct, the 10 decoded data bytes will be placed into the Data Block Butter. the BFREE and
”RC bits of the Status Register will be set to '1' and the CRCERR bit cleared to '0‘.
Once detecting that the BFREE bit of the Status Register has gone to '1‘. the pit. should read the 10 bytes from the Data
Block Buffer and then write the next task to the modern's Command Register.
4.5.2.9 RHB: Read Header Block
This task causes the modem to read the next 66 symbols as a 'Header Block, decoding them, placing the resulting 10
data bytes and the 2 received cnc1 bytes into the Data Block Buffer. and setting the BFREE and IFlQ bits of the Status
Register to '1'. When the task is complete, it indicates that the ye may read the data from the Data Block Butler and write
the next task to the modem‘s Command Register.
The CRCERR bit at the Status Register will be set to ‘1' or '0‘ depending on the validity of the received CRCl checksurn
bytes,
4.5.2.10 RILB: Road “Intermediate or 'Last' Block
This task causes the modem to read the next 55 symbols as an ‘Intermediate‘ or ‘Last‘ block (the pC should be able to tell
from the 'Header' block how many blocks are in the frame and when to expect the 'Last' block).
In each case, it will decode the 68 symbols and place the resulting 12 bytes into the Data Block Buffer, setting the BFREE
and IRQ bits of the Status Register to '1‘ when the task is complete.
if an 'lntermediate' block is received, then the uC should read out all 12 bytes from the Data Block Butter and ignore the
CRCERR bit ol the Status Register, for a 'Last‘ block the uC need only read the lirst 8 bytes from the Data Block Bufier,
and the CRCERR bit in the Status Register will reflect the validity of the received CRCE checksum.
4.5.2.11 SFS: Search for Frame Sync
This task causes the modem to search the received signal for a 24-symbol sequence which matches the Frame
Synchronization pattern to within the tolerance defined by the FSTOL bits of the Mode Register.
When a match is found the modem will set the BFREE and IRO bits of the Status Register to ‘1‘ to indicate to the pC that it
thould write the next task to the Command Register.
45.2.12 R45: Read 4 Symbols
This task causes the modem to read the next 4 symbols and translate them directly (without die-interleaving or FEC) to an
B»bit byte which is placed into the Data Block But-fer. The BFREE and IRO bits of the Status Register are then set to ‘1' to
“ndicate that the uC may read the data byte from the Data Block Butter and write the next task to the Command Register.
This task is intended for special tests and channel monitoring - perhaps preceded by a SFS task.
Note: It is possible to construct message lormatsl which do not rely on the block lorrnatting oi the THB. TB, and TLB
tasks, This can be accomplished by using TAS or T24S tasks to transmit and F145 to receive the user's data, One should
be aware, that the receive level and timing measurement circuits need to see a reasonably “random“ distribution of all four
possible symbols in the received signal to operate correctly. Accordingly, binary data may benefit irom scrambling before
transmission it it is not reasonably 'random' to start with.
45213 T24S: Transmit 24 Symbols
This task. which is intended to facilitate the transmission of Symbol and Frame Sync patterns as well as special test
sequences, takes 6 bytes oi data from the Data Block Butter and transmits them as 24 4-Ievel symbols without any CR0
or FEC.
Byte 0 of the Data Block Butler is sent first, byte 5 last.
Once the modem has read the data bytes from the Data Block Butter, the BFFtEE and lFtQ bits oi the Status Register will
be set to '1‘, indicating to the uC that it may write the data and command byte tor the next task to the modem.
The tables below show what data needs to be written to the Data Block Butler to transmit the MX919B Symbol and Frame
Sync sequences:
'Symbol Sync' Values written to Data Block Butler
Symbols Binary Hex
11110101 F5
11110101 F5
11110101 F5
11110101 F5
11110101 F5
11110101
‘Frame Sync' Values written to Data Block Butter
00100010
00110111 37
01001001
11110010
Byte 4: 01011011
00011011
4.5.2.14 THE. Transmit Header Block
This task takes 10 bytes of data (Address and Control) tram the Data Block Buffer. calculates and appends the 2-byte
CRC1 checksum, translates the result to 4-level symbols (WITH FEC). inteneaves the symbols, and transmits the result as
a tomatted Header“ Blockt
Once the modern has read the data bytes from the Data Block Buffer, the BFHEE and IFlO bits of the Status Register will
be set to ‘1’.
4.5.2.15 TIE: Tmnsmit Intermediate Block
This task takes 12 bytes of data from the Data Block Butter, updates the A-byte CFtCz checksum for inclusion in the ‘Last‘
block, translates the 12 data bytes to 4-Ievel symbols (with FEC), interteaves the symbols, and transmits the result as a
formatted 'Intermediate' Block.
Once the modem has read the data bytes from the Data Block Butler, the BFFlEE and IRQ bits of the Status Register will
be set to ‘1'.
4.5.2.16 TLB: Transmit Last Block
This task lakes 8 bytes at data lrom the Data Block Buffer, updates and appends the 4-byte CFtCZ checksum‘ translates
the resulting 12 bytes to 4-level symbols (with PEG) interleaves the symbols. and transmits the result as a formatted 'Last‘
“tlock,
Once the modem has read the data bytes from the Data Block Buffer, the BFREE and IRO bits of the Status Register will
be set to '1'.
4.5.2.17 T45: Transmit 4 Symbols
This command is similar to T24S but takes only one byte from the Data Block Buffer. transmitting it as four 4-Ievel
symbols.
4.5.2.18 RESET: Stop any current action
This 'task’ takes effect immediately, and terminates any current action (task, AQSC or AQLEV) the modem may be
performing and sets the BFREE bit of the Status Register to '1', without setting the IRQ bit. It should be used when VDD is
applied. to set the modem into a known state.
Note: Due to delays in the transmit filter, it will take several symbol times for any change to appear at the TXOUT pin.
4.52.19 Task Timing
The following table and figures describe the duration of tasks and timing sequences for Tx and Rx operation.
Task Time
(symbol times)
t1 Modem in idle state. Time from writing first task to appllcation of first Any 1 to 2
transmit bit to Tx HRC filter
ta Time from application of first symbol of the task to the Tx RRC T248 5
filter until BFREE goes to a logic '1' THB/TlB/TLB 16
T48 0
ts Time to transmit all symbols of the task T243 24
THB/Tlel'LB 66
us 4 2
t4 Max time allowed from BFREE going to a logic '1‘ (high) for next T24S ' 16 ‘
task (and data) to be written to modern THB/i'lB/TLB 49
T48 3
t5 Time to receive all symbols of task SFS 24 (minimum)
SFSH 90 (minimum)
RHB/RILB 56
R45 4 l
15 Maximum time between first symbol of task entering the ale—interleave SFS ‘ 21
circuit and the task being written to modern SFSH . 21
RHB/HILB ‘ 49
[445 3
l— . .
t7 Maxrmum time from the last bit of the task entering the de interleave Any 1
circuit to BFHEE going to a logic '1‘ (high)
Data to Data Block Eufler
Task to Command Register | 1
[BEMPTY Bit
BFFlEE Bit
—>l h u-
symbols 10 WHO Fliler I
Modem TX 0mm“ m
Figure 11: Transmit Task Timing Diagram
Modemnxmpm m
Symbols to De-interleave for Task 3
Circuit | ,
| is t5 ' ts
~———>~—n<_>4
Data irom Data Block Butler | 1 1 | E
| 1 | |
Task to Command Register | is | 1 | [5 l E I h I 3 |
N—N u———->i H—N |
l l | s t l i t l
1 -—>1 17 H— | —>1 !7 N— | —->1 17 N—
BFREE an m |
Figure 12: Receive Task Timing Diagram
4.5.2.20 HRC filter Delay
The previous task timing figures are based on the signal at the input to the HRC finer (in transmit mode) or the input to the
ale-interleave buffer (in receive mode). There is an additional delay of about 8 symbol times through to the REC filter in
both transmit and receive modes. as illustrated below:
L—__
Delay from Tx Input Tx Mom to ERG Filter
symbol to TXOUT
response.
Tx Symbol at TXOUT pin / Rx Symbol from FM discriminator
Delay from Rx input
(hem FM disorimumur)
to inierprmd data in
mm“ Me'- RX Symbol to Delnterloave Butler l |
Symbol-times
Figure 13: HRC Low Pass Filter Delay
4.5.3 Control Register
This B-bit writeonly register controls the modem’s symbol rate, the response times of the receive clock extraction, signal
level measurement circuits, and the Frame Sync pattern recognition tolerance to inexact matches.
Control Register
CKDIV FSTOL LEVRES PLLBW
4.5.3.1 Control Register 87, BE: CKDIV - Clock Division Ratio
These bits control a frequency divider driven from the clock signal present at the XTAL pin, therefore determining the
nominal symbol rate, Because each symbol represents two bits. bit rates are 2x the symbol rates. The table below shows
how symbol rates of MOO/480019600 symbols/sec (4800/9600/19200bps) may be obtained from common Xtal
frequencies:
Xml Frequency (MHz)
2.4576 4.9152 9.8304
Symbol Rate (symbols/sec) I Bit Rate (bps)
ewe/19200 _
4800/9600 9600/19200
Division Ratio:
--uenc IS mbol Rate
1024 2400/4600
2400/4800 _
Note: Device operation is not guaranteed below 2400 symbols/sec (4800bps) or above 9600 symbols/sec
(192mm).
4.5.3.2 Control Register 85, B4: FSTOL - Frame Sync Tolerance to Inexact Matches
These two bits have no effect in transmit mode. ln receive mode, they define the maximum number of mismatches
allowed during a search for the Frame Sync pattern:
55 | 84 | Mismatches allowed
Note: A single 'mismatch' is defined as the difference between two adjacent symbol levels, thus it the symbol '+1' were
expected, then received symbol values of ‘+3' and '-1' would count as 1 mismatch, a received symbol value of '-3'
would count as 2 mismatches. A setting of '4 mismatches is recommended for normal use.
4.5.3.3 Control Register 53, 52: LEVRES - Level Measurement Modes
These two bits have no effect in transmit mode. In receive mode they set the 'norrnal' or 'steady state‘ operating mode of
the Rx signal amplitude and DC offset measuring and tracking circuits. These circuits analyze the Rx signal envelope and
charge the DOC1 and D002 capacitors to ‘store‘ signal maximum and minimum references that are used in the data
reception process. This setting is temporarily overridden during the automatic sequencing triggered by an AQLEV
command when level is initially being acquired as described in Section 5.3.
II_
II_
“Lossy Peak Detect
n“ Slow Peak Detect
1 normal use the LEVHES bits should be set to '0 1' (Level Track). The other modes are intended for special purposes,
ror device testing, or are invoked automatically during an AQLEV sequence.
in 'Slow Peak Detect’ modes, the positive and negative excursions of the received signal (after filtering) are measured by
peak rectifiers driving the 0001 and DOCZ capacitors to establish the amplitude of the signal and any DC offset with
regards to VBus. This mode provides good overall performance, particularly when acquiring level information at the start
of a received message, but does not work as well with certain long sequences of repeated data byte values. It is also
susceptible to large amplitude noise spikes. which can be caused by deep fades.
The 'Lossy Peak Detect' mode is similar to 'Slow Peak Detect but the capacitor discharge time constant is much shorter
so this mode is not suitable for non-rial data reception and is only used within part of the automatic AOLEV acquisition
sequence.
In 'Level Track‘ mode the DOC capacitor voltages are slowly adjusted by the MXQtQB in such a way as to minimize the
average errors seen in the received signal, This mode provides the best overall performance, being much more accurate
than 'Slow Peak Detect' when receiving large amplitude noise spikes on long sequences of repeated data byte values. it
does, however, depend on the measured levels and timing being approximately correct. it either of these is significantly
wrong then the correction algorithm used by the 'Level Track' mode can actually drive the voltages on the DOC capacitors
away from their optimum levels. For this reason, the automatic AOLEV acquisition sequence (see Section 5.3) forces the
level measuring circuits into 'Siow Peak Detect‘ mode until a Frame Sync pattern has been found.
4.5.3.4 Control Register Bi, BO: PLLBW - Phase-Locked Loop Bandwidth Modes
These two bits have no effect in transmit mode. In receive mode, they set the 'non-nal‘ or ‘steady state' bandwidth of the
Fix clock extraction Phase Locked Loop circuit. The PLL circuit synchronizes itself with the th Signal to develop a local
clock signal used in the data clock recovery process, This setting will be temporarily overridden during the automatic
sequencing of an AQSC command when Rx clock extraction circuits are initially being trained as described in Section 5.3.
The normal setfing for the PLLBW bits should be 'Medium Bandwidth' when the received symbol rate and the frequency oi
the receian modern's crystal are both within it OOppm of nominal, except at the start of a symbol clock acquisition
sequence (AQSC) when 'Wide Bandwidth‘ should be selected as described in Section 5.3
if the received symbol rate and the crystal frequency are both within t20ppm of nominal then selection oi the ‘Narrow
Bandwidth’ setting will provide better performance especially through fades or noise bursts which may othenuise pull the
PLL away from its optimum timing. In this case however: it is recommended that the PLLBW bits only be set to 'Nanow
Bahdwidth' after the modern has been mnning in 'Medium Bandwidth' mode for about 200 symbol times to ensure
accurate lock has first been achieved.
The 'Hold‘ setting disables the feedback loop of the PLL which continues to run at a rate determined only by the actual
crystal lrequency and the setting of the Control Register CKDIV bits, not the PLL‘s operating frequency immediately prior
to the 'Hold' setting.
4.5.4 Mode Register
The contents of this B-bit write only register control the basic operating modes of the modem:
Mode Register
4.5.4.1 Mode Register B7: inoEN - momma Enable
When this bit is set to ‘1‘, the TFE chip output pin is pulled low (Vss) given the IRQ bitol the Status Register is a '1‘.
4.5.4.2 Mode Register BS: INVSYM - Invert Symbols
This bit controls the polarity of the transmitted and received symbol voltages.
BS Symbol Signal at TXOUT Signal at HXAMPOUT
0 “+3“ Above VB.“ Below Vans
'-3' Below Vans Above ngs
1 '+3’ Below VBMS Above Vans
'-3' Above ngs Below VBlAS
Note: Be must be normalry set to the same value in Tx and Rx devices for successiul operation.
4.5.4.3 Mode Register BS: TX/fi -TxIRx Mode
Setting this bit to '1‘ places the modem into the Transmit mode, clearing it to '0' puts the modem into the Receive mode.
Note' Changing between receive and transmit modes will cancel any current task.
4.5.4.4 Mode Register B4: RXEYE - Show Rx Eye
This bit should normally be set to ‘0'. Setting it to '1‘ when the modem is in receive mode configures the modem for a
special test mode, in which the input of the Tx output buffer is connected to the fix Symbol/Clock extraction circuit at a
point which carries the equalized receive signal. This may be monitored with an oscilloscope (at the TXOUT pin itself). to
assess the quality of the complete radio channel including the Tx and Fix modem filters, the Tx modulator and the Rx IF
fitters, and FM demodulator.
This mode is provided because observation of the direct discriminator output of a root raised cosine Tx filtered signal
(before Fix equalization) is not very recognizable so it is generally not useful.
The resulting eye diagram (for reasonably random data) should ideally be as shown in the following Figure 14. with 4
distinct and equally spaced level crossing points.
Figure 14: ideal 'RXEYE‘ Signal
4.5.4.5 Mode Register 53: PSAVE - Powersave
When this bit is a ‘1', the modem will be in a 'powersave’ mode in which the internal filters, the Rx Symbol and Clock
extraction circuits, and the Tx output buffer will be disabled. The TXOUT pin will be connected to V5.“ through a high
value intemai resistance. The Xtal clock oscillator, Rx input amplifier and the "C interface logic will continue to operate,
Setting the PSAVE bit to '0' restores power to all of the chip circuitry.
Note: The internal filters. and therefore the TXOUT pin in transmit mode, will take approximately 20 symbol-times to settle
alter the PSAVE bit has gone train ‘1‘ lo '0‘.
4.5.4.6 Mode Register 52, Bl, Bo
These bits should be set to ‘DOO'.
4.5.5 Status Register
This register may be read by the 1.1.0 to determine the current state of the modem.
Status Register
mun-nu
l "
EFRE DlBC’VF
IRQ IBEMF’TY CHCERR Resennsd
4.5.5.1 Status Register B7: IRQ - Interrupt Request
This bit is set to ‘1‘by:
The Status Register BFREE bit going from '0' to ‘1‘. unless this is caused by a RESET task or by a change to the
Mode Register TX/R_X or PSAVE bits
or The Status Register lBEMPTY bit going from ‘0‘ to ‘1‘, unless this is caused by a RESET task or by changing the
Mode Register TX/R—x or PSAVE bits.
or The Status Register DlBOVF bit going lrom ‘0' to ‘1'.
The IRQ bit is cleared to '0' immediately after a read of the Status Register.
If the IROEN bit of the Mode Register is '1', then the chip m output will be pulled low (Vss) when the lRQ bit is set to '1'.
and will go high impedance when the Status Register is read.
4.5.5.2 Status Register 56: BFREE - Data Block Butler Free
This bit reflects the availability of the Data Block Buffer and is cleared to '0‘ when a task other than NULL or RESET is
written to the Command Register,
n transmit mode, the BFHEE bit will be set to ‘1' (also setting the Status Register IRO bit to ‘1') by the modem when the
modem is ready for the pic to write new data to the Data Block Butter and the next task to the Command Register.
In receive mode, the BFREE bit is set to ‘1' (also setting the Status Register lRO bit to '1‘) by the modem when it has
completed a task and any data associated with that task has been placed into the Data Block Butter. The uC may then
read that data and write the next task to the Command Register.
The BFREE bit is also set to '1' — but without setting the lRQ bit , by a RESET task or when the Mode Register TXIW or
PSAVE bits are changed.
4.5.5.3 Status Register BS: IBEMPTY - Interleave Buffer Empty
in transmit mode, this bit will be set to '1' - also setting the IRQ bit - when less than two symbols remain in the interleave
Buffer. Any transmit task written to the modem after this bit goes to '1‘ will be too late to avoid a gap in the transmit output
signal.
The bit is also set to ‘1' by a RESET task or by a change of the Mode Register TX/W or F‘SAVE bits, but in these cases
the lRO bit will not be set.
The bit is cleared to '0‘ within one symbol time after a task other than NULL or RESET is written to the Command
Register.
Note: When the modem is in transmit mode and the lnlerleave Buffer is empty, 5 mid~level (halfway between '+1' and ‘-1')
signal will be sent to the RRC filter.
In receive mode this bit will be 'D‘.
4.5.5.4 Status Register B4: DIEOVF- De-lnterleave Butter Overflow
In receive mode this bit will be set to '1' - also setting the lRQ bit - when a RHB, RiLB or R48 task is written to the
Command Register too late to allow continuous reception.
The bit is cleared to ’0‘ immediately after reading the Status Register. by writing a RESET task to the Command Register
>r by changing the TX/RVX or PSAVE bits of the Mode Register.
in transmit mode this bit will be 'D‘.
4.5.5.5 Status Register 83: CRCERR - CRC Checksum Error
In receive mode, this bit will be updated at the end of a SFSH, RHB or RILB task to reflect the result of the receive CRC
check. '0‘ indicates that the CRC was received correctly, '1' indicates an error.
Note: This bit should be ignored when an ‘intermediate' block (which does not have an integral CRC) is received.
The bit is cleared m '0' by a RESET task or by changing the TX/fi, or PSAVE bits of the Mode Reg'ster. in transmit
mode this bit is ’0’.
4.5.5.6 Status Register 32. BI, 80
These bits are reserved for future use.
4.5.5 Data Quality Register
In receive mode, the MX9198 continually measures the ‘quality' oi the received signal, by comparing the actual received
waveform over the previous 64 symbol times against an internally generated 'ideal‘ 4-Ievel FSK baseband signal.
The resuit is placed into bits 3-7 of the Data Quality Register for the |JC to read at any time. his 0-2 being always set to '0'.
Figure 15 shows how the value (0-255) read irom the Data Quality Register varies with received signal~to-noise ratio:
250
200
150
100
5 7 9 11 13 15
S/N dB (noise in 2 x symbol-rate bandwidth)
Figure 15: Typical Data Quality Reading vs SIN
The Data Quality readings are onty valid when the modem has successfully acquired signal level and timing lock for at
least 64 symbol times. It is invalid when an AOSC or AQLEV sequence is being performed or when the LEVRES setting
is ‘Lossy Peak Detect‘. A low reading will be obtained if the FLLBW bits are set to 'W’ide‘ or ii the received signal
waveform is distorted in any significant way.
Section 5.6 describes how monitoring the Data Quality reading can help improve the overall system pen‘on-nance in some
applications,
4.6 CRC, FEC and lnterleaving
4.5.1 Cyclic Redundancy Codes
4.6.1.1 CHC1
This is a sixteen-bit CRC check code contained in bytes 10 and 11 of the Header Block which provides error detection
coverage for the Header Block of a message. It is calculated by the modem Irom the first 80 bits of the Header Block
(Bytes 0 to 9 inclusive) using the generator polynomial:
x16 + x12 + x5 +1
4.6.1.2 CRCZ
This is a thirty-Mobil CRC check code contained in bytes 5 to 11 of the 'Last‘ Block, which provides enor detection
coverage lor the combined Intermediate Blocks and Last Block of a message. It is calculated by the modem from all of
the data and pad bytes in the Intermediate Blocks and in the first 8 bytes of the Last Block using the generator polynomial:
X32¢X25*X23+X22+X16+X12+X‘1+X1O+XE+X7+X5+X4+X2+X1+1
Note: In receive mode the CRCZ checksum circuits are initialized on completion of any task other than NULL or RILB, In
transmit mode the CRC2 checksum circuits are initialized on completion of any task other than NULL, TIE. or TLB.
Command Register bit BS (CRC) allows the user to select between two different forms of the CRCt am CHCZ
checksums. When this bit is set to 'U', the CRC generators are initialized to ‘all ones' for calculations such as
CClTl' X25 CRC. When this bit is set to '1', the CBC generators are initialized to ‘all zeros'.
4.6.1.3 Forward Error Correction
In transmit mode. the MX91 QB uses a Trellis Encoder to translate the 56 bits (12 bytes) of a 'Header‘, 'Intermediate' or
'Last‘ Block into a 65-symbol (132 bits) sequence which includes FEC inionnation.
In receive mode, the MX91QB decodes the received 66 symbols of a block into 96 bits of binary data using a 'Soft
Decision‘ Viterbi algorithm to periorm decoding and error correction.
4.6.1 A lnterleaving
The 66 symbols of a 'Header‘, 'Intermediate' or 'Last' block are interleaved by the modem before transmission to provide
protection against the effects of noise bursts and short fades.
In receive mode, the MX9193 de—interleaves the received symbols prior to decoding.
4.7 Transmitted Symbol Shape
Bit 4 of the Command Register (T XlMP) selects the transmit baseband signal and the receive signal equalization as
follows:
the TXlMP bit is “0', then the transmit baseband signal is generated by feedlng full-symbol-time—width 4-level symbols
into the RRC lowpass filtert The receive signal equalization is optimized for this type of signal. With this setting. the
MX91 BB is compatible with the MX919A devices, another member of the MX919 device family.
it the TXlMP bit is set to ‘1,’ impulses, rather than iull-symbcl-time—width symbuls are fed into the RRC filter when in TX
mode, and the receive signal equalization is suitably adjusted in RX mode.
TXlMP = 0 TXlMP = 1
+3 +3 ~'—L
+1 +1
4 -1
.3 -3
i symbol 1 symbol
time time
Figure 16: Input Signal to REC Filter in Tx Mode tor TXlMP = 0 and 1
Figure 17: T: Signal Eye TXlMP = 0
Figure 18: TX Slgnal Eye TXIMP =1
Note: Setting TXIMP to ‘1' affects the Tx omput signal level as shown in Section 6.1.3 and the table below.
TXIMP = 0 TXIMP =1
Nominal Voltage difference between continuous '+3‘ and 0.157VDD 0.157VDD
continuous '-3' symbol outputs.
1 Nominal Vp.p for continuous ‘+3 +3 -3 -3.' symbol pattem 0.20VDD 0.22VDD
5 Application
5.1 Transmit Frame Example
The operations needed to transmit a single Frame consisting of Symbol and Frame Sync sequences. and one each
Header, Intermediate and Last blocks are provided below:
1.
10.
11.
12.
Ensure that the Control Register has been loaded with a suitable CKDIV value, that the lRQEN and TX/Ft-X bits oi the
Mode Register are '1', the FlXEYE and PSAVE bits are '0‘, and the INVSYM bit is set appropriately.
Read the Status Register to ensure that the BFREE bit is ‘1’, then write 6 Symbol Sync bytes (a preamble) to the
Data Block Butter and a T245 task to the Command Register.
Wait for an interrupt from the modern, read the Status Register; the IRQ and BFREE bits should be ‘1' and the
IBEMPTY bit should be 'D'.
Write 6 byte Frame Sync to the Data Block Butter and a T24S task to the Command Register.
Wait tor an interrupt trom the modem, read the Status Register; the IRO and BFREE bits should be '1‘ and the
IBEMPTY bit should be '0'.
Write to Header Block bytes to the Data Block Buffer and at THE task to the Command Register.
Wait for an interrupt from the modern, read the Status Register; the IRQ and BFREE bits should be '1' and the
IBEMPTY bit should be '0'.
Write 12 Intermediate Block bytes to the Data Block Butter and a TIB task to the Command Register.
Wait for an interrupt from the modem, read the Status Register; the IRO and BFREE bits should be '1‘ and the
IEEMPTY bit should be '0'.
Write a Last Block bytes to the Data Block Buffer and a TLB task to the Command Register.
Wait for an interrupt from the modem, read the Status Register; the mo and BFREE bits should be '1' and the
IBEMPTY bit should be '0'.
Wait for another interrupt from the modem. read the Status Register; the IRO, BFREE and IBEMPTY bits should be
'1‘.
Note: The final symbol of the frame will start to appear approximately 2 symbol times after the Status Register IBEMPTY
bit goes to '1'; a turther 16 symbol times should be allowed for the symbol to pass completely through the RRC
filter.
Figure 19 and Figure 20 illustrate the host uC routines needed to send a single Frame consisting oi Symbol and Frame
Sync patterns. a Header block, and any number of Intermediate blocks and one Last Block. it is assumed that the Tx
Interrupt Service Routine Figure 20 is called when the MXBtQB no output line goes low.
START
Ensure that the Control Register
has been loaded with Set uC variable ‘IBLOCKS'
a suitable CKDIV va|ue to the number of Intermediate blocks
I “mm“
Ensure that the Mode Register
lFlQEN, PSAVE EEHXEYE bns are '0‘, Set pC variable 'STATE' (0 0
the TWRX bit is ‘t',
and the INVSYM bit is set appropriately
Set the Mode Register IHQEN bit to '1'
Write a RESET task to the Command Register
Enable uC‘s MXSIQE Tx Interrupt Service Routine
Plead the Status Register
Write 6 bytes oi Symbol Sync
pattern to the Data Bulier
BFFlEE bit = 1 ? es
Write a 1245 task to the Command Register
Note: during this time the uC may
perform other functions, as the
pC variable ‘STATE' is updated
by the intermpt service routine Yes
Disable uC‘s MXQtsB Tx Interrupt Service Routine
Set the Mode Register IHOEN bit to '0‘
me
Yes
END
with error
Figure 19: Transmit Frame Example Flowchart, Main Program
Notes
1. The RESET command in Figure 19 and the practice of disabling the MX9198‘s m output when not needed are not
essential but can eliminate problems during debugging and if errors occur in operation
a. The CRC and TXIMP bits should be set appropriately every time a byte is written to the Command Register.
Wm 00 “C We STATE on Grin/1D mo mm
and nonaspofxmg ngmfl's armors
o symbol Sym: pallem being bummed
Inad Fume Sync panam a. 7245 ask.
‘1 Fame Sync mam bein lransmmad
load Heads! Blodt bvlesgrdTP-B [ask
2: Humor er Imermmediflle stock bang «maxed.
iced Inlermeanle or us 51m Mes A TlBorTLBtask
a: [351 M being mined
ignore ms item,
4“ Wailing h! at! d "ansmlubn.
filish on Mental mm men/1m on w.
START
(TR‘G ine goes km)
IBEMFTYM: | 7
wme 5 byte Fume Sync
panem lo me on. wear
the" wnte a T24S task [0
ma mm neggw
50! 1.0 “We STATE m 9
wmnondaerm
Yes dahbylesbmflmum
men mnaTHB'ask'n
moammmi Regmer
M512 Imam-Bl”
mammmmm
mmoaflahsklu
WmaaLas‘Bhi
dambyteswmeDmBufer
vmnwriteafljum
ma can-mm flaws!
lwmucwiabh
' ATE
Figure 20: Tx Interrum Service Routine
5.2 Receive Frame Example
The operations needed to receive a single Frame consisting of Symbol and Frame Sync sequences and one each
Header. Intermediate and Last blocks are Shown below:
WP?!“
S”
9.
10.
11.
12.
Ensure that the Control Register has been loaded with suitable CKDIV, FSTOL, LEVHES and FLLBW values, and
that the lRQEN bit or the Mode Register is '1', the TX/R—Y PSAVE, and RXEYE bits are 'O‘r and the INVSYM bit is set
appropriately.
Wait until the received carrier has been present for at least a symbol times (see Section 53)
Head the Status Register to ensure that the BFREE bit is '1'.
Write a byte containing a SFSH task and with the A050 and AQLEV bits set to '1' to the Command Register.
Wait for an interrupt from the modern. read the Status Register: the mo and BFREE bits should be '1' and the
CHCERR and DIBOVF bifi should be '0’.
Check that the CRCERR bit of the Status Register is ‘o‘ and read 10 Header Block bytes from the Data Block Butter.
Write a RILB task to the Command Register.
Wait for an interrupt from the modem, read the Status Register; the IRO and BFREE bits should be '1' and the
DIBOVF bit ‘0'.
Read 12 Intermediate Block bytes from the Data Block Buffet
Write a RILB task to the Command Register.
Wait for an interrupt trorn the modem read the Status Register; the IR!) and BFREE bits should be '1‘ and the
DIBOVF bit 'O'.
Check that the CRCEFIR bit at the Status Register is 'D' and read the 8 Last Block bytes from Data Buffer.
Figure 21 and Figure 22 illustrate the host pC routines needed to receive a single Frame consisting of Symbol and Frame
Sync patterns, a Header Block, any number of intermediate blocks and one Last block it is assumed that the Rx Interrupt
Service Routine Figure 22 is called when the MXQtQB‘s W output goes low.
START
Ensure that the Camel Register
has been loaded with stumble
CKDlV, FSTOL. LEVHES and PLLEW values
Wait until the received carrier ha been present
brat least a symbol time
Set 90 vlrinble ‘STATE' (9 0
Setrhe Mode Flagmer moan him '1'
Enable uC‘s MX‘91QB Rx lnterrupt Service Rm
Wnta a SFSH task to the Command Peseta
with the A030 and AQIEV bite who '1‘
Note: during this timethe uC may
perform other runaims, as the
VC variaHe STATE is updated
by the interrupt service routine
Ensure that the Mode H isle! IHQENv
PSAVE. RXEYE and bits. are ‘(t''
and the lNVSYM bit is set appropriately
__l____
Write a RESET task to the Command Heg‘ster
—l—
Reed the Status Register
BFREE bit - | 7
Figure 21: Receive Frame Example Flowchart, Main Program
Notes
1. The RESET command in Figure 21 and the practice of disabling the MX91QB’s W) cutput when not needed are not
essential but can eliminate problems during debugging and it errors occur in operation.
2 The CR0 and TXIMP bits should be set appropriately every time a byte is written to the Command Register.
Value 0! a: variable ‘STATE‘ an entry to ma wane
and canespommg stn 98‘s actions:
START
(Mummmn)
Read Sums Regvs1er
0 Frame Sync has been vsoomued
and Head“ Hod renewed.
read out data and [and RILE msk
r .In(ermed|ata m has been received.
read omdara and toad RILB task
2 Lasl Nod has been received.
read out dala and finish;
RETURN
(Not st|9s mm
CRCERR bi! = U 7
Read 12 Imemmdale Block Head NJ Header Mock hyles
bmsmmnmm OmmlheDalaBunermen
menwrneaRmBlaitw wrueaRlLBfiadflnlhe
"$07an Regifler Gunman Hegfier
SEE NOTEBELOW
sammue'lmocxs‘
wnyeuunbermlmenneciake
Emsmberemvad
'|ELOCKS' = U 7
Se! MC winds STATE“ lo 2
Figure 22: Rx Interrupt Service routine
Note: This routine assumes that the number of Intermediate blocks in the Frame is contained ‘m‘min the Header Block
Data.
5.3 Clock Extraction and Level Measurement Systems
5.3.1 Supported Types 01 Systems
The MX919B is intended tor use in systems where:
I. The Symbol Sync pattern is transmitted immediately on start-up of the transmitter, before the first Frame Sync pattern
(see Figure 23).
2. Aten'ninal may remain powered up indefinitely, transmitting concatenated Frames with or without intervening Symbol
Sync patterns (each Frame having a Frame Sync pattern and symbol timing being maintained from one Frame to the
next).
3. A receiving modem may be swimhed onto a channel before the distant transmitter has started up. or may be switched
onto a channel where the transmitting station is already sending concatenated Frames
5.3.2 Clock and Level Acquisition Procedures with RF Carrier Detect
When the receiving modem is enabled or switched onto a channel. it needs to establish the received symbol levels, clock
timing, and look for 3 Frame Sync pattern in the incoming signal, This is best done by the following procedure:
1. Ensure that the Control Registers PLLBW bits are set to 'Wrde‘ and the LEVHES bits to 'Track'.
2. Wait until a received carrier has been present for 8 symbol times. This B-symbol delay gives time for the received
signal to propagate through the modern‘s FlFiC filter. An 'FiF received 8 symbol times‘ qualifying function can be
included in a radio's carrier detect circuitry to take this into account.
3. Write a SFS or SFSH task to the Command Register with the A030 and the AOLEV bits set to '1'.
4. When the modern interrupts to signal that it has recognized a Frame Sync pattern (or completed the SFSH task) then
change the PLLBW bits to 'Medium'.
Once the receiving modern has achieved level and symbol timing synchronization with a particular channel - as evidenced
by recognition of a Frame Sync pattern - then subsequent concatenated Frames can be read by simply issuing SFS or
SFSH tasks at appropriate times, keeping the ASOSC and AOLEV bits at zero. and the PLuaw and LEVRES bits at their
current 'Medium' and rI'rack' settings, respectively.
Noise Symbol Sync Frame Sync Rest of Frame
i'o'o‘o'
t n 0 v.
Fix Signal trorn 524031:
FM discrtninator
to Modern
S-Symbol delay determined by external
circuit such as RF comer detect
Set A050 and AQLEV bis
to start Acqulsition sequences
Level Measurement and Clock >
Extraction Circuits
Increasing accuracy and lengthening response times
Figure 23: Acquisition Sequence Timing
5.3.3 clock and Level Acquisition Procedure without RF Carrier Detect
It is also possible to use the modem in a system where there is an indeterminate delay between the RF transmitter turn on
time and the transmission moment of the Symbol Sync pattern, or where a receive carrier detect signal is not available to
the controlling pic, or where the transmitting terminal can send separate unsynchronized Frames. In these cases, each
Frame should be preceded by. a Symbol Sync pattern which should be extended to about 100 symbols and the procedure
provided in Section 5.3.2, used.
5.3.4 Automatic Acquisition Functions
Setting the A050 and AQLEV bits to '1' triggers the modem's automatic Symbol Clock Extraction and Level Measurement
acquisition sequences, which are designed to measure the received symbol timing, amplitude, and DC offset as quickly as
flossible before switching to accurate - but slower - measurement modes These acquisition sequences act very quickly it
triggered at the start of a received Symbol Sync pattern {as shown in Figure 23), but will still function correctly, although
more slowly. it started any time during a normal Frame as when the receiver is switched onto a channel where the
transmitter is operating continuously.
The automatic AOLEV Level Measurement acquisition sequence starts with the level measurement circuits being put into
'Clamp' Mode for one symbol time to quickly set the voltages on the DOC pins to approximately correct levels. The level
measurement circuits are then automatically set to ‘Lossy Peak Detect“ mode for 15 symbol times, then 'Slow Peak
Detect‘ until a received Frame Sync pattern is recognized. after which the automatic sequence ends and the level
measurement circuit mode reverts to the mode set by the LEVRES bits of the Control Register (normally 'Level Track'),
The peak detectors used in both 'Slow' and ‘Lossy Peak Detect modes include additional low pass filtering ol the received
signal which greatly reduces the effect of pattern noise on the reference voltages held on the external DOC capacitors, but
means that pairs of ‘+3' (and '—3') symbols need to be received to establish the correct levels. Two pairs of '+3' and two
pairs of '-3' symbols received after the start of an AQLEV sequence are sufficient to correctly set the levels on the DOC
capacitors.
The automatic AOSC Symbol Clock acquisition sequence sets the PLL to 'Extra Wide Bandwidth' mode for 15 symbol
times (this mode is not one at those which can be selected by the Control Register PLLBW bits) then changes to 'Wide'
bandwidth. After 45 symbol times, the PLL mode will revert to that set by the Control Flegister PLLBW bits.
5.4 AC Coupling
For a practical circuit, ac coupling between the modem's transmit output to the frequency modulator and between the
receivers frequency discriminator and the receive input ol the modem may be desired. There are, however, two issues
which deserve consideration:
1. AC coupling ol the signal degrades the Bit Error Rate performance of the modem. The following graph illustrates the
typical bit error rates at 4800 symbols/sec (9600bps) without FEC tor reasonably random data with differing degrees of AC
coupling:
‘l em
ism
nan
lE-Oil
—rxamocmuu
—o—Tx9tL Rant:
——r.sn‘ mat:
-'->Tx5tk. mm;
l 544
u s m n 12 t: u
SNfilNo-nzommh-Ml
Figure 24: Effect 01 AC Coupling on BER (without FEC)
2. Any ac coupling at the receive lnput Will transform any step in the voltage at the discriminator output to a slowly
decaying pulse which can confuse the modem's level measuring circuits. As illustrated in Figure 25 below, the time for
this step to decay to 37°16 of its original value is 'RC' where:
RC = 2n(3dB cut - off frequency oi the RC network)
which is 32ms. or 153 symbol times at 4800 symbols/sec (9600bps) for a 5Hz network.
swan...”
IoFlCClul'l
1m 7
Damn at
RC Circuit 3736 f I
T : RC ‘
l“—’f
Figure 25: Decay Time - AC Coupling
In general, it is best to DC couple the receiver discriminator to the modem and ensure that any AC coupling to the
transmitters frequency modulator has a -3dB cutoff frequency ol no higher than 5Hz for 4800 symbols/sec (econops).
5.5 Radio Performance
The maximum data rate that can be transmitted over a radio channel using mese modems depends on:
- RF channel spacing.
- Allowable adjacent channel interference.
' Symbol rate.
0 Peer: carrier deviation (modulation index).
0 Tx and Fix reference oscillator accuracy.
- Modulator and demodulator linearity.
- Fleceiver IF filter frequency and phase characteristics.
0 Use of error correction techniques.
0 Acceptable error rate.
As a guide, 4800 symbols/sec (Bfioobps) can be achieved (subject to local regulatory requirements) over a system with
12.5kHz channel spacing if the transmitter frequency deviation is set to 12.5kHz peak for a repetitive“ +3 +3 -3 -3 ‘
pattern and the maximum difference between transmitter and receiver 'oarrier‘ lrequencies is less than 2400Hz.
The modulation scheme employed by these modems is designed to achieve high data throughput by exploiting as much
as possible of the RF channel bandwidth, However, this does place constraints on the performance of the radio.
Particular attention must be paid to:
0 Linearity. frequency, and phase response of the Tx Frequency Modulator. For a 4500 symbols/sec (9600bps) system,
the frequency response should be within =2dB over the range SHz to 5kHz, relative to 2400Hz.
o The bandwidth and phase response of the receiver‘s IF filters.
0 Accuracy ol the TX and Rx reference oscillators. as any difference will shift the received signal towards the skirts of
the IF filter response and cause a DC offset at the discriminator output
Viewing the equalized received signal eye diagram, using the Mode Register RXEYE function, provides a good indication
of the overall FlF transmitter/receiver performance.
Rx FREQUENCY Tx FREQUENCY
D‘SCRIMWATOR MODULATOR
SlGNAL LEVEL
ADJUSTMENT
DC LEVEL
ADJUSTMENT SgCNLAIELVAEPil-D
ADJUSTME NT
Tx
CIRCUITS
MX91SB MODEM
Figure 26: Typical Connections between Radio and mx91ss
5.6 Received Signal Quality Monitor
In applications where the modem has to monitor a long transmission containing a number of concatenated Frames, it is
recommended that the controlling software include a function which regulany checks that the modem is still receiving a
-ood data signal and triggers a re-acquisition and possibly changes to another channel it a problem is encountered. This
strategy has been shown to improve the system's overall performance in situation where fading, large noise bursts, severe
co—channel interference, or loss of the received signal tor long periods are likely to occur.
Such a function can be simply implemented by regularly reading the Data Quality Register, which gives a measure of the
overall quality of the received signal, as well as the current ettectiveness oi the modem's clock extraction and level
measurement systems. Experience has shown that if two consecutive DQ readings are both less than 50 then it s worth
instructing the MX919B to re-acquire the received signal levels and timing once it has been established that the received
carrier level is satisfactory. He—acqu'sition should lollow the procedure given in Section 5.3.
The intervals between Data Quality readings is not critical, but should be a minimum of 64 symbol times except for the first
reading made after triggering the A050 and AOLEV automatic acquisition sequences. which should be delayed tor about
250 symbol times.
A suitable algorithm is shown in Figure 27.
Reset timer.
Set pC variable ‘LAST_DQ‘ to 99
Note: Times are symbol times
Read DO register into
[40 variable 'THlS_DQ'
Copy ‘THlS—DO' to 'LAST DO'.
Reset Timer
figure 27: Received Signal Quality Monitor Flowchart
6 Performance Specification
6.1 Electrical Performance
i.1.1 Absolute Maximum Ratings
Exceeding these maximum ratings can result in damage to the device.
Volmge on any pin to Vss
Current
Any other pin
DW, LH, P Package
Total Allowable Power Dissipation at Tuna = 25°C
Derating above 25°C
Storage Temperature -55
| Operating Temperature -40
08 Package Min. Max.
Max. Units
U nits
Total Allowable Power Dissipation at TAMB = 25°C 550 mW
Derating above 25°C mW/“C above uC
Storage Temperature -55 °C
Operating Temperature -40 as “C
5.1.2 Operating Limits
Correct operation of the device outside these limits is not implied.
6.1.3 Operating Charameristics
For the following conditions unless otherwise specified:
Xial Frequency = 4.9152MHz, Symbol Rate = 4800 symbols/sec,
loise Bandwidth = O to 9600Hz, VDD = 5.0V @ TAMB = 25°C
Notes
DC Parameters
[DD 1
lat: (VDD = 343V) 1
IDD (Powersave Mode) 1
lug (Powersave Mode, VDD = 3.3V) 1
Ac Parameters
Tx Output
TXOUT Impedance 2
Signal Level
TXIMP = o 3 0.9
TXiMP =1 3 0.88 . 2 ,
Output DC Offset with respect to Van 12 4 -0.25 025 V
Fix Input
HXIN Impedance (at 100Hz) 100 M9
RXlN Amp Voltage Gain (inpui = 1mvms at100Hz) “—
Inpm Signal Level 5 1.3 Vp_p
DC Offset with respect to VDD I2 5 0.5 V
XTAL/CLOCK INPUT
‘High' Pulse Width 5 40 -- ns
_n 40 - ns
inpui Impedance (3! 1DDHz) 10.0 - Mn
inverter Gain (inpu1 = 1 vaMs a: 100Hz) 20 - dB
pc interface I
Inpm Logic “1" Levei 7, a 707. l vDD
Input Logic -0" Level 7, e 3031: | vol;
Input Leakage Current (vm = o to VDD) 7, B -5.0 540 | in
input Capacitance 7, B pF
Output Logic '1' Levei (iOH = 120pA) e 92% -- VDU
Oulpui Logic '0" Level (ch = 360pA) 8, Q 8% VB!)
'0f‘l' Slate Leakage Cun'eni (Vour = VDD) m pA
6.1 A Operating Characteristics Notes:
1. Not including any current drawn from the modem pins by external circuitry other than the Xtal oscillator.
2. Small signal impedance.
1. Measured after the external FlC iilter (RA/C5) for a “+3 +3 -3 -....“3 symbol sequence, (Tx output level is proportional
to VDO).
Measured at the TXOUT pin with the modem in the Tx idle mode.
For optimum performance, measured at RXAMPOUT pin. for a "...+3 +3 -3 -.3.' symbol sequence, TXIMP = 0 or 1,
The optimum level and DC offset values are proportional to Van.
6 Timing for an external input to (he XTAUCLOCK pin,
7. W, 723, E, AOand A1 pins.
5. DO - D7 pins,
Sn.“
ITO pin.
.1.5 Timing
tic Parallellntenace'l'imings (ref. Figure Notes Min. Typ. Max. Units
23)
Address valid to §§ low time
Address hold time
fl hold time
a high time “—
fi lo W or Fm Iowtime
clock cycles
fol-tn Read data hold time
m“, Write data hold time
tgsw Write data setup time
‘ tancsr E high to is low time (write) "5
tFlACL Head access time from a low ”5
inARL Head access time from W low "5
tat m low time 7 200 ns
tax E high to 00-07 3-state time | 50 ns
‘WHCSL Whigh to a low time (read) 0 "5 J
tWI. W_Rlow time 200 ns
Timing Notes:
1 Xtal/Clock cycles at the XTAUCLOCK pin,
2. With 30pF max to V55 on Do - D7 pins.
WHITE CYCLE lDATAfO MODEM)
ADDRESS
AO‘Al
hH K—PI
ADDRESS VALID :
I l
VCSH K—H I I
l l
| . l law
H——>l
M | l |
MA
no in D7 (1 me)
READ CYCLE (DATA FROM MODEM)
ADDRESS
A41 A1
ADDRESS VALID ‘
| | | ' '
_ | | |
Li
I7
- l
~——>l'
m w M
DATA
Do to D7 (1 byte)
: m—u imam—N1
l | w
M '
l———n
Figure 28: pc Parallel Interlaoe Timings
6.1.6 Typical Bit Error Rate
15.1
—eenwml rec
“52 - - -BERwithoulFEC
1E-3
BER
15-4
1 ES
156
8 9 10 11 12 13 14 15 16
SIN dB (Noise in 2 x Symbol RateBandwidlh)
Figure 29: Typical Bit Error Rate With and without FEC
Measured under nominal working conditions, LEVFlES bits set to 'Level Track‘ or 'Slow Peak Detect' and PLLBW bits set
to ‘Medium' or ‘Narrow‘ Bandwidth, Command Register TXlMP bit set to ‘0' or '1' (same for Tx and fix devices), with
vseudo-random data.
Signal Voltage
N t : S/N alculates aszolo
o e C g‘°( Voltage Noise
where: Signal Voltage is the measured Vnus of a random 4-Ievel signal.
Noise Voltage is the Vans of a flat Gaussian noise signal having a bandwidth from a few Hz to twice the
symbol rate e.g. to $360on when measuring a 4800 symbol/sec (9600bps) system.
Both signals are measured at the same point in the test circuit.
8.2 Packaging
Package Tolerances
DIM. MIN. TYP. MAX.
A 0,597 (1516) 0 61:1 (15.57)
B 0286 (720) 0.290 (7.59)
C 0.090 (230) 0.105 (2.57)
E 0.390 (9.90) 0.419 (10.04)
H 0.000 (0.00) 0.020 (0.51)
J 0013 (0.00) 0.020 (0.51)
K 0.005 (0.91) 0.040 (1 .17)
|_ 0.015 (0.41) 0.050 (1 27)
p 0.050 (127)
T 0.009 (0.23) 0.0125 (0.32)
W 45°
X 0“ 10’
Y 50 7°
Z 5-
NOTE: Alld'lnemlons h Wmm.) |
Angu we in 601000
Figure 30: 24-pin SOIC Mechanical Outline: Orderaspanno. MXQIEEDW
Package Tolerances
DIM. MIN. TYP MAX.
A 0.313 (5.07) 0.320 01.30)
B 0205 (520) 0213 (539)
C 0.066 (1.57) 0.079 (2.00)
E 0301 (7.55) 0.312 (7.90)
H 0.002 (0.05) 0.000 (0.21)
J 0.010 (025) 0.015 (0.30)
L 0 022 (0.55) 0.057 (0.95)
P 0.026 (0.55)
T 0.005 (0.13) 0.009 (0.22)
X 0° 8‘
Y r 9'
Z 4' 10°
NcTEzAlIdflmnslomhMBflm.)
Andosm‘ndsgess
Figure 31: 24-pin SSOP Mechanlml Outline: Older-0551011170. 50919503
Package Tolerances
DIM. MIN. TYP. MAX.
A 0 3000161) 0409 (10.40)
B 0 3500151) 0.409 (10.40)
C 0.120 (3.25) 0.145 (3.70)
D 0 417 (10.50) 0.435 (11.05)
E 0.417 (10.00) 043501135)
F 0.250 (6.35)
G 0250 (6.35)
H 0.029 (0.55)
J 0.013 (0.45) 0.022 (0.55)
K 0.047 (1.19) 0.040 (122)
P 0.049 (124) 0.051 (1 30)
T 0.006 (0.152) 0.009 (022)
W 30' 45°
Y 5°
NOTE: All d|mensims n amt-as (mm)
Anglesun'ndegm
PIN1
KL
‘I
HT
1- J.
A-_..
Package Tolerances
T (‘F T DIM, MIN. TYP MAX.
‘ I ) ' A 1.200 (30.45) 1270 (32.26)
3 E1 E B 0500 (12.70) 0,555 (14.04)
_L l ‘ C 0.151 (5.54) 0220 (5.59)
1r L E 0.500 (1524) 0.070 (1702)
E1 0590 (14.99) 0.025 (15.00)
T H 0.015 (0.35) 0.045 (1.14)
J 0.015 (0:58) 0.023 (0.50)
J1 0,040 (1.02) 0005055)
__ K 0.055 (1.57) 0.074 (1 00)
TC L 0.121 (3.07) 0.160 (4.05)
. P 0 100 (254)
T 00000120) 0.015 (0313)
1) v .
NOTE: Him n “mu-11111)
Anya-lemmas
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