Intel 324632 003 Intel® 82575EB Gigabit Ethernet Controller Software Developer’s Manual And EEPROM Guide User To The 1225128d 56bb 4f2f Aa25 0479ccaef100
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- Intel® 82575EB Gigabit Ethernet Controller Software Developer’s Manual and EEPROM Guide
- 1.0 Introduction
- 2.0 Architectural Overview
- 3.0 General Initialization and Reset Operation
- 4.0 EEPROM and Flash Interface
- 4.1 EEPROM Device
- 4.2 Flash Interface Operation
- 4.3 Shared EEPROM
- 4.4 Shared FLASH
- 4.5 EEPROM Map
- 4.5.1 Hardware Accessed Words
- 4.5.1.1 Ethernet Address (Words 00h – 02h)
- 4.5.1.2 Initialization Control 1 (Word 0Ah)
- 4.5.1.3 Subsystem ID (Word 0Bh)
- 4.5.1.4 Subsystem Vendor ID (Word 0Ch)
- 4.5.1.5 Device ID (Word 0Dh, 11h)
- 4.5.1.6 Dummy Device ID (Word 1Dh)
- 4.5.1.7 Initialization Control 2 (Word 0Fh)
- 4.5.1.8 Software Defined Pins Control (Word 10h)
- 4.5.1.9 EEPROM Sizing & Protected Fields (Word 12h)
- 4.5.1.10 Initialization Control 3 (Word 14h, 24h)
- 4.5.1.11 NC-SI and PCIe* Completion Timeout Configuration (Word 15h)
- 4.5.1.12 MSI-X Configuration (Word 16h)
- 4.5.1.13 PLL/Lane/PHY Initialization Pointer (Word 17h)
- 4.5.1.14 PCIe* Initialization Configuration 1 (Word 18h)
- 4.5.1.15 PCIe* Initialization Configuration 2 (Word 19h)
- 4.5.1.16 Software Defined Pins Control (Word 20h)
- 4.5.1.17 PCIe* Initialization Configuration 3 (Word 1Ah)
- 4.5.1.18 PCIe* Control (Word 1Bh)
- 4.5.1.19 LED 1, 3 Configuration Defaults (Word 1Ch)
- 4.5.1.20 Device Revision ID (Word 1Eh)
- 4.5.1.21 LED 0, 2 Configuration Defaults (Word 1Fh)
- 4.5.1.22 Functions Control (Word 21h)
- 4.5.1.23 LAN Power Consumption (Word 22h)
- 4.5.1.24 Management Hardware Configuration Control (Word 23h)
- 4.5.1.25 End of RO Area (Word 2Ch
- 4.5.1.26 Start of RO Area (Word 2Dh)
- 4.5.1.27 Watchdog Configuration (Word 2Eh)
- 4.5.1.28 VPD Pointer (Word 2Fh)
- 4.5.1.29 PXE Words (Words 30h:3Eh)
- 4.5.1.29.1 Main Setup Options PCI Function 0 (Word 30h)
- 4.5.1.29.2 Configuration Customization Options PCI Function 0 (Word 31h)
- 4.5.1.29.3 PXE Version (Word 32h)
- 4.5.1.29.4 IBA Capabilities (Word 33h)
- 4.5.1.29.5 Setup Options PCI Function 1 (Word 34h)
- 4.5.1.29.6 Configuration Customization Options PCI Function 1 (Word 35h)
- 4.5.1.29.7 iSCSI Option ROM Version (Word 36h)
- 4.5.1.29.8 Alternate MAC Address Pointer (Word 37h)
- 4.5.1.29.9 Setup Options PCI Function 2 (Word 38h)
- 4.5.1.29.10 Configuration Customization Options PCI Function 2 (Word 39h)
- 4.5.1.29.11 Setup Options PCI Function 3 (Word 3Ah)
- 4.5.1.29.12 Configuration Customization Options PCI Function 3 (Word 3Bh)
- 4.5.1.29.13 iSCSI Boot Configuration Offset (Word 3Dh)
- 4.5.1.29.14 Checksum Word (Word 3Fh)
- 4.5.1 Hardware Accessed Words
- 4.6 Manageability Control Sections
- 4.6.1 Sideband Configuration Structure
- 4.6.1.1 Section Header - (0ffset 0h)
- 4.6.1.2 SMBus Max Fragment Size - (0ffset 01h)
- 4.6.1.3 SMBus Notification Timeout and Flags - (0ffset 02h)
- 4.6.1.4 SMBus Slave Addresses - (0ffset 03h)
- 4.6.1.5 SMBus Fail-Over Register (Low Word) - (0ffset 04h)
- 4.6.1.6 SMBus Fail-Over Register (High Word) - (0ffset 05h)
- 4.6.1.7 NC-SI Configuration (0ffset 06h)
- 4.6.2 Flex TCO Filter Configuration Structure
- 4.6.3 NC-SI Microcode Download Structure
- 4.6.4 NC-SI Configuration Structure
- 4.6.4.1 Section Header - (0ffset 0h)
- 4.6.4.2 Rx Mode Control1 (RR_CTRL[15:0]) (Offset 01h)
- 4.6.4.3 Rx Mode Control2 (RR_CTRL[31:16]) (Offset 02h)
- 4.6.4.4 Tx Mode Control1 (RT_CTRL[15:0]) (Offset 03h)
- 4.6.4.5 Tx Mode Control2 (RT_CTRL[31:16]) (Offset 04h)
- 4.6.4.6 MAC Tx Control Reg1 (TxCntrlReg1 (15:0]) (Offset 05h)
- 4.6.4.7 MAC Tx Control Reg2 (TxCntrlReg1 (31:16]) (Offset 06h)
- 4.6.5 Common Firmware Pointer
- 4.6.6 Pass Through Pointers
- 4.6.7 PT LAN Configuration Structure
- 4.6.7.1 Section Header (Offset 0h)
- 4.6.7.2 LAN0 IPv4 Address 0 LSB, MIPAF0 (Offset 01h)
- 4.6.7.3 LAN0 IPv4 Address 0 LSB, MIPAF0 (Offset 02h)
- 4.6.7.4 LAN0 IPv4 Address 1; MIPAF1 (Offset 03h:04h)
- 4.6.7.5 LAN0 IPv4 Address 2; MIPAF2 (Offset 05h:06h)
- 4.6.7.6 LAN0 IPv4 Address 3; MIPAF3 (Offset 07h:08h)
- 4.6.7.7 LAN0 MAC Address 0 LSB, MMAL0 (Offset 09h)
- 4.6.7.8 LAN0 MAC Address 0 LSB, MMAL0 (Offset 0Ah)
- 4.6.7.9 LAN0 MAC Address 0 MSB, MMAH0 (Offset 0Bh)
- 4.6.7.10 LAN0 MAC Address 1; MMAL/H1 (Offset 0Ch:0Eh)
- 4.6.7.11 LAN0 MAC Address 2; MMAL/H2 (Offset 0Fh:11h)
- 4.6.7.12 LAN0 MAC Address 3; MMAL/H3 (Offset 12h:14h)
- 4.6.7.13 LAN0 UDP Flex Filter Ports 0:15; MFUTP Registers (Offset 15h:24h)
- 4.6.7.14 LAN0 VLAN Filter 0:7; MAVTV Registers (Offset 25h:2Ch)
- 4.6.7.15 LAN0 Manageability Filters Valid; MFVAL LSB (Offset 2Dh)
- 4.6.7.16 LAN0 Manageability Filters Valid; MFVAL MSB (Offset 2Eh)
- 4.6.7.17 LAN0 MAC Value MSB (Offset 2Fh)
- 4.6.7.18 LAN0 MANC Value LSB (Offset 30h)
- 4.6.7.19 LAN0 Receive Enable 1(Offset 31h)
- 4.6.7.20 LAN0 Receive Enable 2 (Offset 32h)
- 4.6.7.21 LAN0 MANC2H Value LSB (Offset 33h)
- 4.6.7.22 LAN0 MANC2H Value MSB (Offset 34h)
- 4.6.7.23 Manageability Decision Filters; MDEF0,1 (Offset 35h)
- 4.6.7.24 Manageability Decision Filters; MDEF0, 2 (Offset 36h)
- 4.6.7.25 Manageability Decision Filters; MDEF1:6, 1:2 (Offset 37h:42h)
- 4.6.7.26 ARP Response IPv4 Address 0 LSB (Offset 43h)
- 4.6.7.27 ARP Response IPv4 Address 0 MSB (Offset 44h)
- 4.6.7.28 LAN0 IPv6 Address 0 LSB; MIPAF (Offset 45h)
- 4.6.7.29 LAN0 IPv6 Address 0 MSB; MIPAF (Offset 46h)
- 4.6.7.30 LAN0 IPv6 Address 0 LSB; MIPAF (Offset 47h)
- 4.6.7.31 LAN0 IPv6 Address 0 MSB; MIPAF (Offset 48h)
- 4.6.7.32 LAN0 IPv6 Address 0 LSB; MIPAF (Offset 49h)
- 4.6.7.33 LAN0 IPv6 Address 0 MSB; MIPAF (Offset 4Ah)
- 4.6.7.34 LAN0 IPv6 Address 0 LSB; MIPAF (Offset 4B)
- 4.6.7.35 LAN0 IPv6 Address 0 MSB; MIPAF (Offset 4Ch)
- 4.6.7.36 LAN0 IPv6 Address 1; MIPAF (Offset 4Dh)
- 4.6.7.37 LAN0 IPv6 Address 2; MIPAF (Offset 55h:5Ch)
- 4.6.1 Sideband Configuration Structure
- 4.7 Software Owned EEPROM Words
- 5.0 Receive and Transmit Description
- 5.1 82575 Data Flows
- 5.2 Receive Data Flow
- 5.3 Receive Functionality
- 5.3.1 Packet Address Filtering
- 5.3.2 Receive Data Storage
- 5.3.3 Legacy Receive Descriptor Format
- 5.3.4 Advanced Receive Descriptors
- 5.3.4.1 Packet Buffer Address
- 5.3.4.2 Header Buffer Address
- 5.3.4.3 Packet Type
- 5.3.4.4 RSS Type
- 5.3.4.5 Split Header
- 5.3.4.6 Packet Checksum
- 5.3.4.7 RSS Hash Value
- 5.3.4.8 Extended Status
- 5.3.4.9 Extended Errors
- 5.3.4.10 Packet Buffer (Number of Bytes Exists in the Host Packet Buffer)
- 5.3.4.11 VLAN Tag Field
- 5.3.5 Receive UDP Fragmentation Checksum
- 5.3.6 Receive Descriptor Fetching
- 5.3.7 Receive Descriptor Write-Back
- 5.3.8 Receive Descriptor Ring Structure
- 5.4 Multiple Receive Queues
- 5.5 Header Splitting and Replication
- 5.6 Packet Transmission
- 5.7 Transmit Descriptor Ring Structure
- 5.8 TCP Segmentation
- 5.9 IP/TCP/UDP Transmit Checksum Offloading
- 5.10 IP/TCP/UDP Transmit Checksum Offloading in Non-Segmentation Mode
- 5.11 Multiple Transmit Queues
- 5.12 Tx Completions Head Write-Back
- 5.13 Interrupts
- 5.13.1 Interrupt Cause Register (ICR)
- 5.13.2 Interrupt Cause Set Register (ICS)
- 5.13.3 Interrupt Mask Set/Read Register (IMS)
- 5.13.4 Interrupt Mask Clear Register (IMC)
- 5.13.5 Interrupt Acknowledge Auto-mask register (IAM)
- 5.13.6 Extended Interrupt Cause Registers (EICR)
- 5.13.7 Extended Interrupt Cause Set Register (EICS)
- 5.13.8 Extended Interrupt Mask Set and Read Register (EIMS)/Extended Interrupt Mask Clear Register (EIMC)
- 5.13.9 Extended Interrupt Auto Clear Enable Register (EIAC)
- 5.13.10 Extended Interrupt Auto Mask Enable Register (EIAM)
- 5.13.11 Interrupt Modes Setting Bits
- 5.14 Interrupt Moderation
- 5.15 Clearing Interrupt Causes
- 5.16 Dynamic Interrupt Moderation
- 5.17 Memory Error Correction and Detection
- 6.0 PCIe* Local Bus Interface
- 6.1 General Functionality
- 6.2 Flow Control
- 6.3 Host Interface
- 6.4 Error Events and Error Reporting
- 6.5 Link Layer
- 6.6 Physical Layer
- 7.0 Power Management
- 7.1 Power States
- 7.2 Auxiliary Power
- 7.3 Form Factor Power Limits
- 7.4 Power Management Interconnects
- 7.5 Wake Up
- 8.0 DCA
- 9.0 Ethernet Interface
- 9.1 Internal MAC/PHY 10/100/1000Base-T Interface
- 9.2 Duplex Operation for Copper PHY Operation
- 9.3 Auto-Negotiation and Link Setup
- 9.4 Loopback Support
- 10.0 802.1q VLAN Support
- 11.0 PHY Functionality and Features
- 11.1 Auto MDIO Register Initialization
- 11.2 Determining Link State
- 11.3 Link Criteria
- 11.4 Link Enhancements
- 11.5 Management Data Interface
- 11.6 Low Power Operation
- 11.7 Power Down via the PHY Register
- 11.8 1000 Mb/s Operation
- 11.9 100 Mb/s Operation
- 11.10 10 Mb/s Operation
- 12.0 Configurable LED Outputs
- 13.0 Dual Port Characteristics
- 14.0 Register Descriptions
- 14.1 Register Conventions
- 14.2 Register Summary
- 14.3 Main Register Descriptions
- 14.3.1 Device Control Register - CTRL (00000h; R/W)
- 14.3.2 Device Status Register - STATUS (00008h; R)
- 14.3.3 EEPROM/Flash Control Register - EEC (00010h; R/W)
- 14.3.4 EEPROM Read Register - EERD (00014h; RW)
- 14.3.5 Extended Device Control Register - CTRL_EXT (00018h, R/W)
- 14.3.6 Flash Access - FLA (0001Ch; R/W)
- 14.3.7 MDI Control Register - MDIC (00020h; R/W)
- 14.3.8 PHY Registers
- 14.3.8.1 PHY Control Register - PCTRL (00d; R/W)
- 14.3.8.2 PHY Status Register - PSTATUS (01d; R)
- 14.3.8.3 PHY Identifier Register 1 (LSB) - PHY ID 1 (02d; R)
- 14.3.8.4 PHY Identifier Register 2 (MSB) - PHY ID 2 (03d; R)
- 14.3.8.5 Auto-Negotiation Advertisement Register - ANA (04d; R/W)
- 14.3.8.6 Auto-Negotiation Base Page Ability Register - (05d; R)
- 14.3.8.7 Auto-Negotiation Expansion Register - ANE (06d; R)
- 14.3.8.8 Auto-Negotiation Next Page Transmit Register - NPT (07d; R/W)
- 14.3.8.9 Auto-Negotiation Next Page Ability Register - LPN (08d; R)
- 14.3.8.10 1000BASE-T/100BASE-T2 Control Register - GCON (09d; R/W)
- 14.3.8.11 1000BASE-T/100BASE-T2 Status Register - GSTATUS (10d; R)
- 14.3.8.12 Extended Status Register - ESTATUS (15d; R)
- 14.3.8.13 Port Configuration Register - PCONF (16d; R/W)
- 14.3.8.14 Port Status 1 Register - PSTAT (17d; RO)
- 14.3.8.15 Port Control Register - PCONT (18d; R/W)
- 14.3.8.16 Link Health Register - LINK (19d; RO)
- 14.3.8.17 1000Base-T FIFO Register - PFIFO (20d; R/W)
- 14.3.8.18 Channel Quality Register - CHAN (21d; RO)
- 14.3.8.19 PHY Power Management - (25d; R/W)
- 14.3.8.20 Special Gigabit Disable Register - (26d; R/W)
- 14.3.8.21 Misc Cntrl Register 1 - (27d; R/W)
- 14.3.8.22 Misc Cntrl Register 2 - (28d; RO)
- 14.3.8.23 Page Select Core Register - (31d; WO)
- 14.3.9 SERDES ANA - SERDESCTL (00024h; R/W)
- 14.3.10 Copper/Fiber Switch Control - CONNSW (00034h; R/W)
- 14.3.11 VLAN Ether Type - VET (00038h; R/W)
- 14.3.12 Fuse Register - UFUSE (5B78h; RO)
- 14.3.13 Flow Control Address Low - FCAL (00028h; R/ W)
- 14.3.14 Flow Control Address High - FCAH (0002Ch; R/ W)
- 14.3.15 Flow Control Type - FCT (00030h; R/W)
- 14.3.16 Flow Control Transmit Timer Value - FCTTV (00170h; R/W)
- 14.3.17 LED Control - LEDCTL (00E00h; RW)
- 14.3.18 Packet Buffer Allocation - PBA (01000h; R/W)
- 14.3.19 Packet Buffer Size - PBS (01008h; R/W)
- 14.3.20 SFP 12C Command - I2CCMD (01028h; R/W)
- 14.3.21 SFP 12C Parameters - I2CPARAMS (0102Ch; R/ W)
- 14.3.22 Flash Opcode - FLASHOP (0103Ch; R/W)
- 14.3.23 EEPROM Diagnostic - EEDIAG (01038h; RO)
- 14.3.24 Manageability EEPROM Control Register - EEMNGCTL (01010h; RO)
- 14.3.25 Manageability EEPROM Read/Write Data - EEMNGDATA (1014h; RO)
- 14.3.26 Manageability Flash Control Register - FLMNGCTL (1018h; R/W)
- 14.3.27 Manageability Flash Read Data - FLMNGDATA (101Ch; R/W)
- 14.3.28 Manageability Flash Read Counter - FLMNGCNT (1020h; R/W)
- 14.3.29 EEPROM Auto Read Bus Control - EEARBC (01024h; R/W)
- 14.3.30 Watchdog Setup - WDSTP (01040h; R/W)
- 14.3.31 Watchdog SW Device Status - WDSWSTS (01044h; R/W)
- 14.3.32 Free Running Timer - FRTIMER (01048h; RWS)
- 14.3.33 TCP Timer - TCPTIMER (0104Ch; R/W)
- 14.3.34 Interrupt Cause Read Register - ICR (000C0H; R)
- 14.3.35 Interrupt Cause Set Register - ICS (000C8h; WO)
- 14.3.36 Interrupt Mask Set/Read Register - IMS (000D0h; R/W)
- 14.3.37 Interrupt Mask Clear Register - IMC (000D8h; W)
- 14.3.38 Interrupt Acknowledge Auto Mask Register - IAM (000E0h; R/W)
- 14.3.39 Extended Interrupt Cause - EICR (01580h; RC/ W1C)
- 14.3.40 Extended Interrupt Cause Set - EICS (01520h; WO)
- 14.3.41 Extended Interrupt Mask Set/Read - EIMS (01524h; RWS)
- 14.3.42 Extended Interrupt Mask Clear - EIMC (01528h; WO)
- 14.3.43 Extended Interrupt Auto Clear - EIAC (0152Ch; R/W)
- 14.3.44 Extended Interrupt Auto Mask Enable - EIAM (01530h; R/W)
- 14.3.45 Interrupt Throttle - EITR (01680h + 4*n [n = 0..9]; R/W)
- 14.3.46 Immediate Interrupt Rx - IMIR (05A80h + 4*n [n = 0..7]; R/W)
- 14.3.47 Immediate Interrupt Rx Extended - IMIREXT (05AA0h + 4*n [n = 0..7]; R/W)
- 14.3.48 Immediate Interrupt Rx VLAN Priority - IMIRVP (05AC0h; R/W)
- 14.3.49 MSI-X Allocation - MSIXBM (01600h + 4*n [n = 0..9]; R/W)
- 14.3.50 Receive Control Register - RCTL (00100h; R/W)
- 14.3.51 Split and Replication Receive Control - SRRCTL (0280Ch + 100*n [n=0..3]; R/W)
- 14.3.52 Packet Split Receive Type - PSRTYPE (05480h + 4*n [n=0..3]; R/W)
- 14.3.53 Flow Control Receive Threshold Low - FCRTL (02160h; R/W)
- 14.3.54 Flow Control Receive Threshold High - FCRTH (02168h; R/W)
- 14.3.55 Flow Control Refresh Threshold Value - FCRTV (02460h; R/W)
- 14.3.56 Receive Descriptor Base Address High - RDBAH (02804h + 100*n [n=0..3]; R/W)
- 14.3.57 Receive Descriptor Length - RDLEN (02808h + 100*n [n=0..3]; R/W)
- 14.3.58 Receive Descriptor Head - RDH (02810h + 100*n [n=0..3]; R/W)
- 14.3.59 Receive Descriptor Tail - RDT (02818h + 100*n [n=0..3]; R/W)
- 14.3.60 Receive Descriptor Control - RXDCTL (02828h + 100*n [n=0..3]; R/W)
- 14.3.61 Receive Checksum Control - RXCSUM (05000h; R/W)
- 14.3.62 Receive Long Packet Maximum Length - RLPML (05004; R/W)
- 14.3.63 Receive Filter Control Register - RFCTL (05008h; R/W)
- 14.3.64 Transmit Control Register - TCTL (00400h; R/ W)
- 14.3.65 Transmit Control Extended - TCTL_EXT (00404;R/W)
- 14.3.66 Transmit IPG Register - TIPG (00410;R/W)
- 14.3.67 DMA Tx Control - DTXCTL (03590h; R/W)
- 14.3.68 Transmit Descriptor Base Address Low - TDBAL (03800h + 100*n [n=0..3]; R/W)
- 14.3.69 Transmit Descriptor Base Address High - TDBAH (03804h + 100*n [n=0..3]; R/W)
- 14.3.70 Transmit Descriptor Length - TDLEN (03808h + 100*n [n=0..3]; R/W)
- 14.3.71 Transmit Descriptor Head - TDH (03810h + 100*n [n=0..3]; R/W)
- 14.3.72 Transmit Descriptor Tail - TDT (03818h + 100*n [n=0..3]; R/W)
- 14.3.73 Transmit Descriptor Control - TXDCTL (03828h + 100*n [n=0..3]; R/W)
- 14.3.74 Tx Descriptor Completion Write-Back Address Low - TDWBAL (03838h + 100*n [n=0..3]; R/ W)
- 14.3.75 Tx Descriptor Completion Write-Back Address High - TDWBAH (0383Ch + 100*n [n=0..3]; R/ W)
- 14.3.76 PCS Configuration 0 - PCS_CFG (04200h; R/W)
- 14.3.77 PCS Link Control - PCS_LCTL (04208h; R/W)
- 14.3.78 PCS Link Status - PCS_LSTS (0420Ch; R/W)
- 14.3.79 AN Advertisement - PCS_ANADV (04218h; R/ W)
- 14.3.80 Link Partner Ability - PCS_LPAB (0421Ch; RO)
- 14.3.81 Next Page Transmit - PCS_NPTX (04220h; RO)
- 14.3.82 Link Partner Ability Next Page - PCS_LPABNP (04224h; RO)
- 14.4 DCA Registers
- 14.5 Filter Registers
- 14.5.1 Multicast Table Array - MTA (05200h + 4*n [n..127]; R/W)
- 14.5.2 Receive Address Low - RAL (05400h + 8*n [n=0..15]; R/W)
- 14.5.3 Receive Address High - RAH (05404h + 8*n [n=0..15]; R/W)
- 14.5.4 VLAN Filter Table Array - VFTA (05600h + 4*n [n=0..127]; R/W)
- 14.5.5 Multiple Receive Queues Command Register - MRQC (05818h; R/W)
- 14.5.6 Redirection Table - RETA (05C00h + 4*n [n=0..31]; R/W)
- 14.5.7 RSS Random Key Register - RSSRK (05C80h + 4*n [n=0..9]; R/W)
- 14.5.8 VMDq Control - VMD_CTRL (0581Ch; R/W)
- 14.5.9 VLAN Filter Queue Array 0 - VFQA0 (0B100h + 4*n [n=0…127]; R/W)
- 14.5.10 VLAN Filter Queue Array 1 - VFQA1 (0B200h + 4*n [n=0…127]; R/W)
- 14.6 Wakeup Registers
- 14.6.1 Wakeup Control Register - WUC (05800h; R/W)
- 14.6.2 Wakeup Filter Control Register - WUFC (05808h; R/W)
- 14.6.3 Wakeup Status Register - WUS (05810h; R/ W1C)
- 14.6.4 IP Address Valid - IPAV (5838h; R/W)
- 14.6.5 IPv4 Address Table - IP4AT (05840h + 8*n [n=0..3]; R/W)
- 14.6.6 IPv6 Address Table - IP6AT (05880h + 4*n[n=0..3]; R/W)
- 14.6.7 Wakeup Packet Length - WUPL (05900h; RC)
- 14.6.8 Wakeup Packet Memory (128 Bytes) - WUPM (05A00h + 4*n [n=0..31]; RC)
- 14.6.9 Flexible Filter Mask Table - FFMT (09000h + 8*n [n=0..127]; R/W)
- 14.6.10 Flexible Filter Value Table - FFVT (09800h + 8*n [n=0..127]; R/W)
- 14.6.11 Flexible Filter Length Table - FFLT (05F00h + 8*n [n=0..3]; R/W)
- 14.7 Manageability Registers
- 14.7.1 Management VLAN TAG Value - MAVTV (5010h +4*n [n=0..7]; R/W)
- 14.7.2 Management Flex UDP/TCP Ports - MFUTP (5030h + 4*n [n=0..7]; R/W)
- 14.7.3 Management Control Register - MANC (05820h; R/W)
- 14.7.4 Manageability Filters Valid - MFVAL (5824h; R/ W)
- 14.7.5 Management Control to Host Register - MANC2H (5860h; R/W)
- 14.7.6 Manageability Decision Filters- MDEF (5890h + 4*n [n=0..7]; R/W)
- 14.7.7 Manageability IP Address Filter - MIPAF (0x58B0-0x58EC; RW)
- 14.7.8 Manageability MAC Address Low - MMAL (5910h + 8*n[n=0..3]; RW)
- 14.7.9 Manageability MAC Address High - MMAH (0x5914 + 8*n[n=0..3]; RW)
- 14.7.10 Flexible TCO Filter Table Registers - FTFT (09400h-097FCh; RW)
- 14.7.11 Legacy Sensor Polling Mask 1...8 Register (F8h:FFh)
- 14.8 PCIe* Registers
- 14.8.1 PCIe* Control - GCR (05B00h; R)
- 14.8.2 Function Tag - FUNCTAG (05B08h; R/W)
- 14.8.3 PCIe* Statistics Control #1 - GSCL_1 (05B10h; R)
- 14.8.4 PCIe* Statistics Control #2 - GSCL_2 (05B14h; R)
- 14.8.5 PCIe* Statistics Control #3 - GSCL_3 (05B18h; R/W)
- 14.8.6 PCIe* Statistics Control #4 - GSCL_4 (05B1Ch; R/W)
- 14.8.7 PCIe* Counter #0 - GSCN_0 (05B20h; R/W)
- 14.8.8 PCIe* Counter #1 - GSCN_1 (05B24h; R/W)
- 14.8.9 PCIe* Counter #2 - GSCN_2 (05B28h; R/W)
- 14.8.10 PCIe* Counter #3 - GSCN_3 (05B2Ch; R/W)
- 14.8.11 Function Active and Power State to MNG - FACTPS (05B30h; R)
- 14.8.12 SerDes/CCM/PCIe* CSR - GIOANACTL0 (05B34h; R/W)
- 14.8.13 SerDes/CCM/PCIe* CSR - GIOANACTL1 (05B38h; R/W)
- 14.8.14 GIOANACTL2 (05B3Ch; R/W)
- 14.8.15 GIOANACTL3 (05B40h; R/W)
- 14.8.16 SerDes/CCM/PCIe* CSR - GIOANACTLALL (05B44h; R/W)
- 14.8.17 SerDes/CCM/PCIe* CSR - CCMCTL (05B48h; R/ W)
- 14.8.18 SerDes/CCM/PCIe* CSR - SCCTL (05B4Ch; R/ W)
- 14.8.19 Software Semaphore - SWSM (05B50h; R/W)
- 14.8.20 Firmware Semaphore - FWSM (05B58h; R/WS)
- 14.8.21 Software-Firmware Synchronization - SW_FW_SYNC (05B5Ch; R/WS)
- 14.8.22 Mirrored Revision ID - MREVID (05B64h; R/W)
- 14.8.23 MSI-X PBA Clear - PBACL (05B68h; R/W1C)
- 14.8.24 DCA Requester ID Information - DCA_ID (05B70h; R/W)
- 14.8.25 DCA Control - DCA_CTRL (05B74h; R/W)
- 14.9 Statistics Registers
- 14.9.1 CRC Error Count - CRCERRS (04000h; RC)
- 14.9.2 Alignment Error Count - ALGNERRC (04004h; RC)
- 14.9.3 Symbol Error Count - SYMERRS (04008h; RC)
- 14.9.4 RX Error Count - RXERRC (0400Ch; RC)
- 14.9.5 Missed Packets Count - MPC (04010h; RC)
- 14.9.6 Single Collision Count - SCC (04014h; RC)
- 14.9.7 Excessive Collisions Count - ECOL (04018h; RC)
- 14.9.8 Multiple Collision Count - MCC (0401Ch; RC)
- 14.9.9 Late Collisions Count - LATECOL (04020h; RC)
- 14.9.10 Collision Count - COLC (04028h; RC)
- 14.9.11 Defer Count - DC (04030h; RC)
- 14.9.12 Transmit with No CRS - TNCRS (04034h; RC)
- 14.9.13 Receive Length Error Count - RLEC (04040h; RC)
- 14.9.14 XON Received Count - XONRXC (04048h; RC)
- 14.9.15 XON Transmitted Count - XONTXC (0404Ch; RC)
- 14.9.16 XOFF Received Count - XOFFRXC (04050h; RC)
- 14.9.17 XOFF Transmitted Count - XOFFTXC (04054h; RC)
- 14.9.18 FC Received Unsupported Count - FCRUC (04058h; RC)
- 14.9.19 Packets Received (64 Bytes) Count - PRC64 (0405Ch; RC)
- 14.9.20 Packets Received (65-127 Bytes) Count - PRC127 (04060h; RC)
- 14.9.21 Packets Received (128-255 Bytes) Count - PRC255 (04064h; RC)
- 14.9.22 Packets Received (256-511 Bytes) Count - PRC511 (04068h; RC)
- 14.9.23 Packets Received (512-1023 Bytes) Count - PRC1023 (0406Ch; RC)
- 14.9.24 Packets Received (1024 to Max Bytes) Count - PRC1522 (04070h; RC)
- 14.9.25 Good Packets Received Count - GPRC (04074h; RC)
- 14.9.26 Broadcast Packets Received Count - BPRC (04078h; RC)
- 14.9.27 Multicast Packets Received Count - MPRC (0407Ch; RC)
- 14.9.28 Good Packets Transmitted Count - GPTC (04080h; RC)
- 14.9.29 Good Octets Received Count - GORCL (04088h; RC)/GORCH (0408Ch; RC)
- 14.9.30 Good Octets Transmitted Count - GOTCL (04090h; RC)/ GOTCH (04094; RC)
- 14.9.31 Receive No Buffers Count - RNBC (040A0h; RC)
- 14.9.32 Receive Undersize Count - RUC (040A4h; RC)
- 14.9.33 Receive Fragment Count - RFC (040A8h; RC)
- 14.9.34 Receive Oversize Count - ROC (040ACh; RC)
- 14.9.35 Receive Jabber Count - RJC (040B0h; R)
- 14.9.36 Management Packets Received Count - MNGPRC (040B4h; RC)
- 14.9.37 Management Packets Dropped Count - MPDC (040B8h; RC)
- 14.9.38 Management Packets Transmitted Count - MNGPTC (040BCh; RC)
- 14.9.39 Total Octets Received - TORL (040C0h; RC) / TORH (040C4h; RC)
- 14.9.40 Total Octets Transmitted - TOTL (040C8h; RC / TOTH (040CCh; RC)
- 14.9.41 Total Packets Received - TPR (040D0h; RC)
- 14.9.42 Total Packets Transmitted - TPT (040D4h; RC)
- 14.9.43 Packets Transmitted (64 Bytes) Count - PTC64 (040D8h; RC)
- 14.9.44 Packets Transmitted (65-127 Bytes) Count - PTC127 (040DCh; RC)
- 14.9.45 Packets Transmitted (128-255 Bytes) Count - PTC255 (040E0h; RC)
- 14.9.46 Packets Transmitted (256-511 Bytes) Count - PTC511 (040E4h; RC)
- 14.9.47 Packets Transmitted (512-1023 Bytes) Count - PTC1023 (040E8h; RC)
- 14.9.48 Packets Transmitted (1024 Bytes or Greater) Count - PTC1522 (040ECh; RC)
- 14.9.49 Multicast Packets Transmitted Count - MPTC (040F0h; RC)
- 14.9.50 Broadcast Packets Transmitted Count - BPTC (040F4h; RC)
- 14.9.51 TCP Segmentation Context Transmitted Count - TSCTC (040F8h; RC)
- 14.9.52 Interrupt Assertion Count - IAC (04100h; RC)
- 14.9.53 Rx Packets to Host Count - RPTHC (04104h; RC)
- 14.9.54 Transmit Queue Empty Count - TXQEC (04118h; RC)
- 14.9.55 Receive Descriptor Minimum Threshold Count - RXDMTC (04120h; RC)
- 14.9.56 Interrupt Cause Receiver Overrun Count - ICRXOC (04124h; RC)
- 14.9.57 SerDes/SGMII Code Violation Packet Count - SCVPC (04228h; R/WS)
- 14.10 Diagnostics Registers
- 14.10.1 Receive Data FIFO Head Register - RDFH (02410h; RO)
- 14.10.2 Receive Data FIFO Tail Register - RDFT (02418h; RO)
- 14.10.3 Receive Data FIFO Head Saved Register - RDFHS (02420h; RO)
- 14.10.4 Receive Data FIFO Tail Saved Register - RDFTS (02428h; RO)
- 14.10.5 Receive Data FIFO Packet Count - RDFPCQ (02430h + 4 *n [n=0..3]; RO)
- 14.10.6 PB Descriptor Read Pointers - PBDESCRP (02454h; RO)
- 14.10.7 Packet Buffer Diagnostic - PBDIAG (02458h; R/ W)
- 14.10.8 Transmit Data FIFO Head Register - TDFH (03410h; RO)
- 14.10.9 Transmit Data FIFO Tail Register - TDFT (03418h; R/WS)
- 14.10.10 Transmit Data FIFO Head Saved Register - TDFHS (03420h; R/WS)
- 14.10.11 Transmit Data FIFO Tail Saved Register - TDFTS (03428h; R/WS)
- 14.10.12 Transmit Data FIFO Packet Count - TDFPC (03430h; RO)
- 14.10.13 Packet Buffer ECC Error Inject - PBEEI (03438h; RO)
- 14.10.14 Tx Descriptor Handler ECC Error Inject - TDHEEI (035F8h; R/W)
- 14.10.15 Rx Descriptor Handler ECC Error Inject - RDHEEI (025F8h; R/W)
- 14.10.16 Packet Buffer Memory - PBM (10000h - 10FFCh; R/W)
- 14.10.17 Packet Buffer Memory Page NPBMPN Register Bit Description
- 14.10.18 Rx Descriptor Handler Memory Page Number - RDHMP (025FCh; R/W)
- 14.10.19 Tx Descriptor Handler Memory Page Number - TDHMP (035FCh; R/W)
- 14.10.20 Packet Buffer ECC Status - PBECCSTS (0245Ch; R/W)
- 14.10.21 Rx Descriptor Handler ECC Status - RDHESTS (02468h; R/W)
- 14.10.22 Tx Descriptor Handler ECC Status - TDHESTS (0246Ch; R/W)
- 14.11 Packet Generator Registers
- 14.11.1 Packet Generator Destination Address Low - PGDAL (04280h; R/W)
- 14.11.2 Packet Generator Destination Address High - PGDAH (04284h; R/W)
- 14.11.3 Packet Generator Source Address Low - PGSAL (04288h; R/W)
- 14.11.4 Packet Generator Source Address High - PGSAH (0428Ch; R/W)
- 14.11.5 Packet Generator Inter Packet Gap - PGIPG (04290h; R/W)
- 14.11.6 Packet Generator Packet Length - PGPL (04294h; R/W)
- 14.11.7 Packet Generator Number of Packets - PGNP (04298h; R/W)
- 14.11.8 Packet Generator StaPGSTS Bit Description
- 14.11.9 Packet Generator ContPGCTL Bit Description
- 14.12 MSI-X Registers
- 14.12.1 MSI-X Table Entry Lower Address - MSIXTADD (00000h - 00090h; R/W)
- 14.12.2 MSI-X Table Entry Upper Address - MSIXTUADD (BAR3: 0004h + n*10h [n=0..9]; RW)
- 14.12.3 MSI-X Table Entry Message - MSIXTMSG (BAR3: 0008h + n*10h [n=0..9]; RW)
- 14.12.4 MSI-X Table Entry Vector Control - MSIXVCTRL (BAR3: 000Ch + n*10h [n=0..9]; RW)
- 14.12.5 MSI-X Pending Bit Array - MSIXPBA Bit Description
- 15.0 Diagnostics and Testability
- 16.0 Statistics