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80960HA/HD/HT 32-Bit High-Performance
Superscalar Processor
Datasheet
Product Features
■
■
■
■
■
■
32-Bit Parallel Architecture
— Load/Store Architecture
— Sixteen 32-Bit Global Registers
— Sixteen 32-Bit Local Registers
— 1.28 Gbyte Internal Bandwidth
(80 MHz)
— On-Chip Register Cache
Processor Core Clock
— 80960HA is 1x Bus Clock
— 80960HD is 2x Bus Clock
— 80960HT is 3x Bus Clock
Binary Compatible with Other 80960
Processors
Issue Up To 150 Million Instructions per
Second
High-Performance On-Chip Storage
— 16 Kbyte Four-Way Set-Associative
Instruction Cache
— 8 Kbyte Four-Way Set-Associative Data
Cache
— 2 Kbyte General Purpose RAM
Separate 128-Bit Internal Paths For
Instructions/Data
■
■
■
■
■
3.3 V Supply Voltage
— 5 V Tolerant Inputs
— TTL Compatible Outputs
Guarded Memory Unit
— Provides Memory Protection
— User/Supervisor Read/Write/Execute
32-Bit Demultiplexed Burst Bus
— Per-Byte Parity Generation/Checking
— Address Pipelining Option
— Fully Programmable Wait State Generator
— Supports 8-, 16- or 32-Bit Bus Widths
— 160 Mbyte/s External Bandwidth
(40 MHz)
High-Speed Interrupt Controller
— Up to 240 External Interrupts
— 31 Fully Programmable Priorities
— Separate, Non-maskable Interrupt Pin
Dual On-Chip 32-Bit Timers
— Auto Reload Capability and One-Shot
— CLKIN Prescaling, divided by 1, 2, 4 or 8
— JTAG Support - IEEE 1149.1 Compliant
Order Number: 272495-008
September 2002
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY
ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN
INTEL’S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS
ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES
RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER
INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The 80960HA/HD/HT 32-Bit High-Performance Superscalar Processor may contain design defects or errors known as errata which may cause the
product to deviate from published specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling
1-800-548-4725 or by visiting Intel’s website at http://www.intel.com.
Copyright © Intel Corporation, 2002
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*Other names and brands may be claimed as the property of others.
2
Datasheet
Contents
Contents
1.0
About This Document ................................................................................................................... 9
2.0
Intel 80960Hx Processor ............................................................................................................... 9
2.1
2.2
2.3
3.0
The i960® Processor Family ...............................................................................................10
Key 80960Hx Features .......................................................................................................10
2.2.1 Execution Architecture ...........................................................................................10
2.2.2 Pipelined, Burst Bus ..............................................................................................10
2.2.3 On-Chip Caches and Data RAM............................................................................11
2.2.4 Priority Interrupt Controller.....................................................................................11
2.2.5 Guarded Memory Unit ...........................................................................................11
2.2.6 Dual Programmable Timers ...................................................................................12
2.2.7 Processor Self Test ...............................................................................................12
Instruction Set Summary ....................................................................................................13
Package Information ...................................................................................................................14
3.1
3.2
3.3
3.4
3.5
3.6
3.7
4.0
Pin Descriptions ..................................................................................................................15
80960Hx Mechanical Data..................................................................................................20
3.2.1 80960Hx PGA Pinout.............................................................................................20
3.2.2 80960Hx PQ4 Pinout .............................................................................................26
Package Thermal Specifications ........................................................................................31
Heat Sink Adhesives...........................................................................................................34
PowerQuad4 Plastic Package ............................................................................................34
Stepping Register Information ............................................................................................34
Sources for Accessories .....................................................................................................36
Electrical Specifications .............................................................................................................37
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
5.0
Absolute Maximum Ratings ................................................................................................37
Operating Conditions ..........................................................................................................37
Recommended Connections ..............................................................................................38
VCC5 Pin Requirements (VDIFF) ........................................................................................38
VCCPLL Pin Requirements ................................................................................................39
DC Specifications ...............................................................................................................40
AC Specifications................................................................................................................42
4.7.1 AC Test Conditions ................................................................................................45
AC Timing Waveforms ........................................................................................................46
Bus Waveforms ...........................................................................................................................54
5.1
5.2
80960Hx Boundary Scan Chain .........................................................................................84
Boundary Scan Description Language Example ................................................................88
Figures
1
2
3
4
5
6
80960Hx Block Diagram ............................................................................................................... 9
80960Hx 168-Pin PGA Pinout—View from Top (Pins Facing Down) .........................................20
80960Hx 168-Pin PGA Pinout—View from Bottom (Pins Facing Up) ........................................21
80960Hx 208-Pin PQ4 Pinout.....................................................................................................26
Measuring 80960Hx PGA Case Temperature ............................................................................31
80960Hx Device Identification Register......................................................................................34
Datasheet
3
Contents
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
4
VCC5 Current-Limiting Resistor ................................................................................................. 38
AC Test Load.............................................................................................................................. 45
CLKIN Waveform........................................................................................................................ 46
Output Delay Waveform ............................................................................................................. 46
Output Delay Waveform ............................................................................................................. 46
Output Float Waveform .............................................................................................................. 47
Input Setup and Hold Waveform ................................................................................................ 47
NMI, XINT7:0 Input Setup and Hold Waveform.......................................................................... 47
Hold Acknowledge Timings ........................................................................................................ 48
Bus Backoff (BOFF) Timings ...................................................................................................... 48
TCK Waveform ........................................................................................................................... 49
Input Setup and Hold Waveforms for TBSIS1 and TBSIH1.......................................................... 49
Output Delay and Output Float for TBSOV1 and TBSOF1 ........................................................ 50
Output Delay and Output Float Waveform for TBSOV2 and TBSOF2 ....................................... 50
Input Setup and Hold Waveform for TBSIS2 and TBSIH2 ......................................................... 50
Rise and Fall Time Derating at 85 °C and Minimum VCC.......................................................... 51
ICC Active (Power Supply) vs. Frequency................................................................................... 51
ICC Active (Thermal) vs. Frequency............................................................................................ 52
Output Delay or Hold vs. Load Capacitance .............................................................................. 52
Output Delay vs. Temperature ................................................................................................... 53
Output Hold Times vs. Temperature .......................................................................................... 53
Output Delay vs. VCC ................................................................................................................ 53
Cold Reset Waveform ................................................................................................................ 54
Warm Reset Waveform .............................................................................................................. 55
Entering ONCE Mode................................................................................................................. 56
Non-Burst, Non-Pipelined Requests without Wait States ........................................................... 57
Non-Burst, Non-Pipelined Read Request with Wait States ........................................................ 58
Non-Burst, Non-Pipelined Write Request with Wait States ........................................................ 59
Burst, Non-Pipelined Read Request without Wait States, 32-Bit Bus ........................................ 60
Burst, Non-Pipelined Read Request with Wait States, 32-Bit Bus ............................................. 61
Burst, Non-Pipelined Write Request without Wait States, 32-Bit Bus ........................................ 62
Burst, Non-Pipelined Write Request with Wait States, 32-Bit Bus ............................................. 63
Burst, Non-Pipelined Read Request with Wait States, 16-Bit Bus ............................................. 64
Burst, Non-Pipelined Read Request with Wait States, 8-Bit Bus ............................................... 65
Non-Burst, Pipelined Read Request without Wait States, 32-Bit Bus ........................................ 66
Non-Burst, Pipelined Read Request with Wait States, 32-Bit Bus ............................................. 67
Burst, Pipelined Read Request without Wait States, 32-Bit Bus ................................................ 68
Burst, Pipelined Read Request with Wait States, 32-Bit Bus ..................................................... 69
Burst, Pipelined Read Request with Wait States, 8-Bit Bus ....................................................... 70
Burst, Pipelined Read Request with Wait States, 16-Bit Bus ..................................................... 71
Using External READY............................................................................................................... 72
Terminating a Burst with BTERM ............................................................................................... 73
BREQ and BSTALL Operation ................................................................................................... 74
BOFF Functional Timing. BOFF occurs during a burst or non-burst data cycle. ........................ 75
HOLD Functional Timing ............................................................................................................ 76
LOCK Delays HOLDA Timing..................................................................................................... 77
FAIL Functional Timing............................................................................................................... 77
A Summary of Aligned and Unaligned Transfers for 32-Bit Regions.......................................... 78
A Summary of Aligned and Unaligned Transfers for 32-Bit Regions (Continued) ...................... 79
A Summary of Aligned and Unaligned Transfers for 16-Bit Bus................................................. 80
Datasheet
Contents
57 A Summary of Aligned and Unaligned Transfers for 8-Bit Bus...................................................81
58 Idle Bus Operation ......................................................................................................................82
59 Bus States ..................................................................................................................................83
Tables
1
2
3
4
5
6
7
8
9
10
11
13
12
15
14
17
18
16
19
20
21
22
23
25
24
26
80960Hx Product Description ....................................................................................................... 9
Fail Codes For BIST (bit 7 = 1) ...................................................................................................12
Remaining Fail Codes (bit 7 = 0) ................................................................................................12
80960Hx Instruction Set .............................................................................................................13
80960HA/HD/HT Package Types and Speeds...........................................................................14
Pin Description Nomenclature ....................................................................................................15
80960Hx Processor Family Pin Descriptions..............................................................................16
80960Hx 168-Pin PGA Pinout—Signal Name Order..................................................................22
80960Hx 168-Pin PGA Pinout—Pin Number Order ...................................................................24
80960Hx PQ4 Pinout—Signal Name Order................................................................................27
80960Hx PQ4 Pinout—Pin Number Order .................................................................................29
80960Hx 168-Pin PGA Package Thermal Characteristics .........................................................32
Maximum TA at Various Airflows in °C (PGA Package Only) .....................................................32
80960Hx 208-Pin PQ4 Package Thermal Characteristics..........................................................33
Maximum TA at Various Airflows in °C (PQ4 Package Only)......................................................33
80960Hx Device ID Model Types ...............................................................................................35
Device ID Version Numbers for Different Steppings...................................................................35
Fields of 80960Hx Device ID ......................................................................................................35
Absolute Maximum Ratings ........................................................................................................37
Operating Conditions ..................................................................................................................37
VDIFF Specification for Dual Power Supply Requirements (3.3 V, 5 V) ......................................39
80960Hx DC Characteristics ......................................................................................................40
80960Hx AC Characteristics.......................................................................................................42
80960Hx Boundary Scan Test Signal Timings ...........................................................................44
AC Characteristics Notes............................................................................................................44
80960Hx Boundary Scan Chain .................................................................................................84
Datasheet
5
Contents
Revision History
Date
Revision
History
Formatted the datasheet in a new template.
In “32-Bit Parallel Architecture” on page 1:
• Removed operating frequency of 16/32 (bus/core) from 80960HD.
• Removed operating frequency of 20/60 (bus/core) from 80960HT.
In Table 5 “80960HA/HD/HT Package Types and Speeds” on page 14:
September 2002
008
• Removed core speed of 32 MHz and bus speed of 16 MHz, and order
number A80960HD32-S-L2GG from the 168L PGA package, 80960HD
device.
• Removed core speed of 60 MHz and bus speed of 20 MHz, and order
number A80960HT60 from the 168L PGA package, 80960HT device.
• Removed core speed of 32 MHz and bus speed of 16 MHz, and order
number FC80960HD32-S-L2GL from the 208L PQFP package,
80960HD device.
• Removed core speed of 60 MHz and bus speed of 20 MHz, and order
number FC80960HT60-S-L2G2 from the 208L PQFP package,
80960HT device.
In “32-Bit Parallel Architecture” on page 1:
• Revised 1.2 Gbyte Internal Bandwidth (75 MHz) to 1.28 Gbyte Internal
Bandwidth (80 MHz).
In Section 3.0, “Package Information” on page 14:
• Added paragraph two and Table 5 “80960HA/HD/HT Package Types
and Speeds” on page 14.
In Table 7 “80960Hx Processor Family Pin Descriptions” on page 16:
• Corrected minor typeset and spacing errors.
• BREQ; Revised description.
• ONCE; last sentence, changed ‘low’ to ‘high’.
• TDI and TMS; removed last sentence stating, “Pull this pin low when
not in use.”
In Figure 2 “80960Hx 168-Pin PGA Pinout—View from Top (Pins Facing
Down)” on page 20:
July 1998
007
• Added insert package marking diagram.
In Figure 4 “80960Hx 208-Pin PQ4 Pinout” on page 26:
• Added insert package marking diagram.
In Table 10 “80960Hx PQ4 Pinout—Signal Name Order” on page 27:
• Corrected TDO (‘O’ was zero) and revised alphabetical ordering.
In Table 11 “80960Hx PQ4 Pinout—Pin Number Order” on page 29:
• Corrected TDO (‘O’ was zero) and revised alphabetical ordering.
In Section 4.1, “Absolute Maximum Ratings” on page 37:
• Revised VCC to VCC5 for Voltage on Other Pins with respect to VSS.
In Section 4.5, “VCCPLL Pin Requirements” on page 39:
• Added section.
In Table 22 “80960Hx DC Characteristics” on page 40:
• Added footnote (1) to ILO notes column for TDO pin.
• Added footnote (10) to CIN, COUT and CI/O pin.
6
Datasheet
Contents
Date
Revision
History
In Table 23 “80960Hx AC Characteristics” on page 42:
• Added overbars where required.
• Modified TDVNH to list separate specifications for 3.3 V and 5 V.
July 1998
(continued)
007
(continued)
• Modified TOV2, TOH2 and TTVEL to reflect specific 80960HA, 80960HD
and 80960HT values.
In Figure 23 “ICC Active (Power Supply) vs. Frequency” on page 51:
• Changed ‘5’ to ‘0’ on the CLKIN Frequency axis.
In Figure 49 “BREQ and BSTALL Operation” on page 74:
• Added figure and following text.
August 1997
Datasheet
006
Fixed several font and format issues.
7
Contents
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8
Datasheet
80960HA/HD/HT
1.0
About This Document
This document describes the parametric performance of Intel’s 80960Hx embedded superscalar
microprocessors. Detailed descriptions for functional topics, other than parametric performance,
are published in the i960® Hx Microprocessor User’s Guide (272484).
In this document, ‘80960Hx’ and ‘i960 Hx processor’ refer to the products described in Table 1.
Throughout this document, information that is specific to each is clearly indicated.
Figure 1. 80960Hx Block Diagram
Guarded Memory Unit
Instruction Prefetch Queue
JTAG Port
Instruction Cache
16 Kbyte, Four-Way Set-Associative
Timers
Interrupt
Port
128-Bit Cache Bus
Programmable
Interrupt Controller
Control
Memory Region Configuration
Address
Bus Controller
Bus Request Queues
Parallel Instruction Scheduler
Data
Data Cache
8 Kbyte, Four-Way Set-Associative
Multiply/Divide Unit
Register-Side
Memory-Side
Machine Bus
Machine Bus
Execution Unit
Data RAM - 2 Kbyte
Register Cache - 5 to 15 sets
Six-Port Register File
64-bit SRC1 Bus
32-bit Base Bus
Address Generation Unit
64-bit SRC2 Bus 128-bit Load Bus
64-bit DST Bus
2.0
128-bit Store Bus
Intel 80960Hx Processor
The Intel 80960Hx processor provides new performance levels while maintaining backward
compatibility (pin1 and software) with the i960 CA/CF processor. This newest member of the
family of i960 32-bit, RISC-style, embedded processors allows customers to create scalable
designs that meet multiple price and performance points. This is accomplished by providing
processors that may run at the bus speed or faster using Intel’s clock multiplying technology
(see Table 1). The 80960Hx core is capable of issuing 150 million instructions per second, using a
sophisticated instruction scheduler that allows the processor to sustain a throughput of two
instructions every core clock, with a peak performance of three instructions per clock. The
80960Hx-series comprises three processors, which differ in the ratio of core clock speed to external
bus speed.
Table 1.
80960Hx Product Description
Product
Core
Voltage
Operating Frequency (bus/core)
80960HA
1x
3.3 V†
25/25, 33/33, 40/40
80960HD
2x
3.3 V†
25/50, 33/66, 40/80
3x
†
80960HT
3.3 V
25/75
† Processor inputs are 5 V tolerant.
1. The 80960Hx is not “drop-in” compatible in an 80960Cx-based system. Customers may design systems that accept either 80960Hx or Cx
processors.
Datasheet
9
80960HA/HD/HT
In addition to expanded clock frequency options, the 80960Hx provides essential enhancements for
an emerging class of high-performance embedded applications. Features include a larger
instruction cache, data cache, and data RAM than any other 80960 processor to date. It also boasts
a 32-bit demultiplexed and pipelined burst bus, fast interrupt mechanism, guarded memory unit,
wait state generator, dual programmable timers, ONCE and IEEE 1149.1-compliant boundary scan
test and debug support, and new instructions.
2.1
The i960® Processor Family
The i960® processor family is a 32-bit RISC architecture created by Intel to serve the needs of
embedded applications. The embedded market includes applications as diverse as industrial
automation, avionics, image processing, graphics and communications.
Because all members of the i960 processor family share a common core architecture, i960
applications are code-compatible. Each new processor in the family adds its own special set of
functions to the core to satisfy the needs of a specific application or range of applications in the
embedded market.
2.2
Key 80960Hx Features
2.2.1
Execution Architecture
Independent instruction paths inside the processor allow the execution of multiple, out-of-sequence
instructions per clock. Register and resource scoreboarding interlocks maintain the logical integrity
of sequential instructions that are being executed in parallel. To sustain execution of multiple
instructions in each clock cycle, the processor decodes multiple instructions in parallel and
simultaneously issues these instructions to parallel processing units. The various processing units
are then able to independently access instruction operands in parallel from a common register set.
Local Register Cache integrated on-chip provides automatic register management on call/return
instructions. Upon a call instruction, the processor allocates a set of local registers for the called
procedure, then stores the registers for the previous procedure in the on-chip register cache. As
additional procedures are called, the cache stores the associated registers such that the most recently
called procedure is the first available by the next return (ret) instruction. The processor may store up
to fifteen register sets, after which the oldest sets are stored (spilled) into external memory.
The 80960Hx supports the 80960 architecturally-defined branch prediction mechanism. This
allows many branches to execute with no pipeline break. With the 80960Hx’s efficient pipeline, a
branch may take as few as zero clocks to execute. The maximum penalty for an incorrect prediction
is two core clocks.
2.2.2
Pipelined, Burst Bus
A 32-bit high performance bus controller interfaces the 80960Hx core to the external memory and
peripherals. The Bus Control Unit features a maximum transfer rate of 160 Mbytes per second (at a
40 MHz external bus clock frequency). A key advantage of this design is its versatility. The user
may independently program the physical and logical attributes of system memory. Physical
attributes include wait state profile, bus width, and parity. Logical attributes include cacheability
and Big or Little Endian byte order. Internally programmable wait states and 16 separately
configurable physical memory regions allow the processor to interface with a variety of memory
10
Datasheet
80960HA/HD/HT
subsystems with minimum system complexity. To reduce the effect of wait states, the bus design is
decoupled from the core. This lets the processor execute instructions while the bus performs
memory accesses independently.
The Bus Controller’s key features include:
•
•
•
•
•
•
•
•
2.2.3
Demultiplexed, Burst Bus to support most efficient DRAM access modes
Address Pipelining to reduce memory cost while maintaining performance
32-, 16- and 8-bit modes to facilitate I/O interfacing
Full internal wait state generation to reduce system cost
Little and Big Endian support
Unaligned Access support implemented in hardware
Three-deep request queue to decouple the bus from the core
Independent physical and logical address space characteristics
On-Chip Caches and Data RAM
As shown in Figure 1, the 80960Hx provides generous on-chip cache and storage features to
decouple CPU execution from the external bus. The processor includes a 16 Kbyte instruction
cache, an 8 Kbyte data cache and 2 Kbytes of Data RAM. The caches are organized as 4-way set
associative. Stores that hit the data cache are written through to memory. The data cache performs
write allocation on cache misses. A fifteen-set stack frame cache allows the processor to rapidly
allocate and deallocate local registers. All of the on-chip RAM sustains a 4-word (128-bit) access
every clock cycle.
2.2.4
Priority Interrupt Controller
The interrupt unit provides the mechanism for the low latency and high throughput interrupt
service essential for embedded applications. A priority interrupt controller provides full
programmability of 240 interrupt sources with a typical interrupt task switch (latency) time of 17
core clocks. The controller supports 31 priority levels. Interrupts are prioritized and signaled within
10 core clocks of the request. When the interrupt has a higher priority than the processor priority,
the context switch to the interrupt routine would typically complete in another seven bus clocks.
External agents post interrupts through the 8-bit external interrupt port. The Interrupt unit also
handles the two internal sources from the Timers. Interrupts may be level- or edge-triggered.
2.2.5
Guarded Memory Unit
The Guarded Memory Unit (GMU) provides memory protection without the address translation
found in Memory Management Units. The GMU contains two memory protection schemes: one
prevents illegal memory accesses, the other detects memory access violations. Both signal a fault
to the processor. The programmable protection modes are: user read, write or execute; and
supervisor read, write or execute.
Datasheet
11
80960HA/HD/HT
2.2.6
Dual Programmable Timers
The processor provides two independent 32-bit timers, with four programmable clock rates. The
user configures the timers through the Timer Unit registers. These registers are memory-mapped
within the 80960Hx, addressable on 32-bit boundaries. The timers have a single-shot mode and
auto-reload capabilities for continuous operation. Each timer has an independent interrupt request
to the processor’s interrupt controller.
2.2.7
Processor Self Test
When a system error is detected, the FAIL pin is asserted, a fail code message is driven onto the
address bus, and the processor stops execution at the point of failure. The only way to resume
normal operation is to perform a RESET operation. Because System Error generation may occur
sometime after the bus confidence test and even after initialization during normal processor
operation, the FAIL pin is HIGH (logic “1”) before the detection of a System Error.
The processor uses only one read bus-transaction to signal the fail code message; the address of the
bus transaction is the fail code itself. The fail code is of the form: 0xfeffffnn; bits 6 to 0 contain a
mask recording the possible failures. Bit 7, when set to 1, indicates that the mask contains failures
from the internal Built-In Self-Test (BIST); when 0, the mask indicates other failures.
Ignore reserved bits 0 and 1. Also ignore bits 5 and 6 when bit 7 is clear (=0).
The mask is shown in Table 2 and Table 3.
Table 2.
Fail Codes For BIST (bit 7 = 1)
Bit
Table 3.
When Set
6
On-chip Data-RAM failure detected by BIST.
5
Internal Microcode ROM failure detected by BIST.
4
Instruction cache failure detected by BIST.
3
Data cache failure detected by BIST.
2
Local-register cache or processor core failure detected by BIST.
1
Reserved. Always zero.
0
Reserved. Always zero.
Remaining Fail Codes (bit 7 = 0)
Bit
6
12
When Set
Reserved. Always one.
5
Reserved. Always one.
4
A data structure within the IMI is not aligned to a word boundary.
3
A System Error during normal operation has occurred.
2
The Bus Confidence test has failed.
1
Reserved. Always zero.
0
Reserved. Always zero.
Datasheet
80960HA/HD/HT
2.3
Instruction Set Summary
Table 4 summarizes the 80960Hx instruction set by logical groupings.
Table 4.
80960Hx Instruction Set
Data Movement
Arithmetic
Logical
Bit / Bit Field / Byte
Add
Subtract
Multiply
And
Divide
Not And
Set Bit
Clear Bit
Remainder
And Not
Load
Modulo
Or
Store
Shift
Exclusive Or
Move
Extended Shift
Not Or
Load Address
Extended Multiply
Or Not
Conditional Select2
Extended Divide
Nor
Not Bit
Alter Bit
Scan For Bit
Span Over Bit
Extract
Add with Carry
Exclusive Nor
Subtract with Carry
Not
Rotate
Nand
Modify
Scan Byte for Equal
Byte Swap2
Conditional Add2
Conditional Subtract2
Comparison
Branch
Call/Return
Fault
Compare
Conditional Compare
Compare and Increment
Compare and Decrement
Compare Byte
2
Compare Short2
Call
Unconditional Branch
Call Extended
Conditional Branch
Call System
Compare and Branch
Return
Conditional Fault
Synchronize Faults
Branch and Link
Test Condition Code
Check Bit
Debug
Processor Mgmt
Atomic
Cache Control
Flush Local Registers
Modify Trace Controls
Modify Arithmetic Controls
Mark
Modify Process Controls
Force Mark
Interrupt Enable/ Disable1, 2
System Control
Atomic Add
Instruction Cache
Control1, 2
Atomic Modify
Data Cache Control1, 2
1
NOTES:
1. 80960Hx extensions to the 80960 core instruction set.
2. 80960Hx extensions to the 80960Cx instruction set.
Datasheet
13
80960HA/HD/HT
3.0
Package Information
This section describes the pins, pinouts and thermal characteristics for the 80960Hx in the 168-pin
ceramic Pin Grid Array (PGA) package, 208-pin PowerQuad2* (PQ4). For complete package
specifications and information, see the Intel Packaging Handbook (Order# 240800).
The 80960HA/HD/HT is offered with eight speeds and two package types (Table 5). Both the
168-pin ceramic Pin Grid Array (PGA) and the 208-pin PowerQuad2* (PQ4) devices are specified
for operation at VCC = 3.3 V ± 0.15 V over a case temperature range of 0 °C to 85 °C.
Table 5.
80960HA/HD/HT Package Types and Speeds
Package/Name
Device
Core Speed
(MHz)
80960HA
168L PGA
80960HD
80960HT
Bus Speed
(MHz)
25
A80960HA25 S L2GX
33
A80960HA33 S L2GY
40
A80960HA40 S L2GZ
50
25
A80960HD50 S L2GH
66
33
A80960HD66 S L2GJ
80
40
A80960HD80 S L2GK
75
25
A80960HT75 S L2GP
80960HA
25
FC80960HA25 S L2GU
33
FC80960HA33 S L2GV
40
208L PQFP
(also known as PQ4)
14
Order #
FC80960HA40 S L2GW
50
25
FC80960HD50 S L2GM
80960HD
66
33
FC80960HD66 S L2GN
80
40
FC80960HD80 S L2LZ
80960HT
75
25
FC80960HT75 S L2GT
Datasheet
80960HA/HD/HT
3.1
Pin Descriptions
This section defines the 80960Hx pins. Table 6 presents the legend for interpreting the pin
descriptions in Table 7. All pins float while the processor is in the ONCE mode, except TDO,
which may be driven active according to normal JTAG specifications.
Table 6.
Pin Description Nomenclature
Symbol
I
Input only pin.
O
Output only pin.
I/O
Pin may be input or output.
-
Datasheet
Description
Pin must be connected as indicated for proper device functionality.
S(E)
Synchronous edge sensitive input. This input must meet the setup and hold times relative to
CLKIN to ensure proper operation of the processor.
S(L)
Synchronous level sensitive input. This input must meet the setup and hold times relative to
CLKIN to ensure proper operation of the processor.
A(E)
Asynchronous edge-sensitive input.
A(L)
Asynchronous level-sensitive input.
H(...)
While the processor bus is in the HOLD state (HOLDA asserted), the pin:
H(1) is driven to VCC
H(0) is driven to VSS
H(Z) floats
H(Q) continues to be a valid output
B(...)
While the processor is in the bus backoff state (BOFF asserted), the pin:
B(1) is driven to VCC
B(0) is driven to VSS
B(Z) floats
B(Q) continues to be a valid output
R(...)
While the processor’s RESET pin is asserted, the pin:
R(1) is driven to VCC
R(0) is driven to VSS
R(Z) floats
R(Q) continues to be a valid output
15
80960HA/HD/HT
Table 7.
80960Hx Processor Family Pin Descriptions (Sheet 1 of 4)
Name
Type
Description
O
A31:2
H(Z)
B(Z)
R(Z)
ADDRESS BUS carries the upper 30 bits of the physical address. A31 is the most
significant address bit and A2 is the least significant. During a bus access, A31:2
identify all external addresses to word (4-byte) boundaries. The byte enable
signals indicate the selected byte in each word. During burst accesses, A3 and
A2 increment to indicate successive addresses.
I/O
D31:0
S(L)
H(Z)
B(Z)
R(Z)
DATA BUS carries 32, 16, or 8-bit data quantities depending on bus width
configuration. The least significant bit of the data is carried on D0 and the most
significant on D31. The lower eight data lines (D7:0) are used when the bus is
configured for 8-bit data. When configured for 16-bit data, D15:0 are used.
DATA PARITY carries parity information for the data bus. Each parity bit is
assigned a group of eight data bus pins as follows:
I/O
DP3:0
S(L)
H(Z)
B(Z)
R(Z)
DP3 generates/checks parity for D31:24
DP2 generates/checks parity for D23:16
DP1 generates/checks parity for D15:8
DP0 generates/checks parity for D7:0
Parity information is generated for a processor write cycle and is checked for a
processor read cycle. Parity checking and polarity are programmable. Parity
generation/checking is only performed for the size of the data accessed.
O
PCHK
H(Q)
B(Q)
R(1)
PARITY CHECK indicates the result of a parity check operation. An asserted
PCHK indicates that the previous bus read access resulted in a parity check error.
BYTE ENABLES select which of the four bytes addressed by A31:2 are active
during a bus access. Byte enable encoding is dependent on the bus width of the
memory region accessed:
O
BE3:0
H(Z)
B(Z)
R(1)
32-bit bus:
BE3 enables D31:24
BE2 enables D23:16
BE1 enables D15:8
BE0 enables D7:0
16-bit bus:
BE3 becomes Byte High Enable (enables D15:8)
BE2 is not used (state is undefined)
BE1 becomes Address Bit 1 (A1)
BE0 becomes Byte Low Enable (enables D7:0)
8-bit bus:
BE3 is not used (state is undefined)
BE2 is not used (state is undefined)
BE1 Address Bit 1 (A1)
BE0 Address Bit 0 (A0)
O
W/R
H(Z)
B(Z)
R(0)
O
D/C
16
H(Z)
B(Z)
R(0)
WRITE/READ is low for read accesses and high for write accesses.
W/R becomes valid during the address phase of a bus cycle and remains valid
until the end of the cycle for non-pipelined accesses. For pipelined accesses, W/
R changes state when the next address is presented.
0= Read
1= Write
DATA/CODE indicates that a bus access is a data access or an instruction
access. D/C has the same timing as W/R.
0 = Code
1 = Data
Datasheet
80960HA/HD/HT
Table 7.
80960Hx Processor Family Pin Descriptions (Sheet 2 of 4)
Name
Type
O
SUP
H(Z)
B(Z)
R(1)
Description
SUPERVISOR ACCESS indicates whether the current bus access originates
from a request issued while in supervisor mode or user mode. SUP may be used
by the memory subsystem to isolate supervisor code and data structures from
non-supervisor access.
0 = Supervisor Mode
1 = User Mode
O
ADS
READY
H(Z)
B(Z)
R(1)
I
S(L)
ADDRESS STROBE indicates a valid address and the start of a new bus access.
ADS is asserted for the first clock of a bus access.
READY, when enabled for a memory region, is asserted by the memory
subsystem to indicate the completion of a data transfer. READY is used to
indicate that read data on the bus is valid, or that a write transfer has completed.
READY works in conjunction with the internal wait state generator to
accommodate various memory speeds. READY is sampled after any
programmed wait states:
During each data cycle of a burst access
During the data cycle of a non-burst access
BTERM
I
S(L)
O
WAIT
H(Z)
B(Z)
R(1)
O
BLAST
H(Z)
B(Z)
R(1)
O
DT/R
H(Z)
B(Z)
R(0)
O
DEN
H(Z)
B(Z)
R(1)
O
LOCK
Datasheet
H(Z)
B(Z)
R(1)
BURST TERMINATE, when enabled for a memory region, is asserted by the
memory subsystem to terminate a burst access in progress. When BTERM is
asserted, the current burst access is terminated and another address cycle
occurs.
WAIT indicates the status of the internal wait-state generator. WAIT is asserted
when the internal wait state generator generates NWAD, NRAD, NWDD and NRDD
wait states. WAIT may be used to derive a write data strobe.
BURST LAST indicates the last transfer in a bus access. BLAST is asserted in
the last data transfer of burst and non-burst accesses after the internal wait-state
generator reaches zero. BLAST remains active as long as wait states are inserted
through the READY pin. BLAST becomes inactive after the final data transfer in a
bus cycle.
DATA TRANSMIT/RECEIVE indicates direction for data transceivers. DT/R is
used with DEN to provide control for data transceivers connected to the data bus.
DT/R is driven low to indicate the processor expects data (a read cycle). DT/R is
driven high when the processor is “transmitting” data (a store cycle). DT/R only
changes state when DEN is high.
0 = Data Receive
1 = Data Transmit
DATA ENABLE indicates data transfer cycles during a bus access. DEN is
asserted at the start of the first data cycle in a bus access and de-asserted at the
end of the last data cycle. DEN remains asserted for an entire bus request, even
when that request spans several bus accesses. For example, a ldq instruction
starting at an unaligned quad word boundary is one bus request spanning at least
two bus accesses. DEN remains asserted throughout all the accesses (including
ADS states) and de-asserts when the Iqd instruction request is satisfied. DEN is
used with DT/R to provide control for data transceivers connected to the data bus.
DEN remains asserted for sequential reads from pipelined memory regions.
BUS LOCK indicates that an atomic read-modify-write operation is in progress.
LOCK may be used by the memory subsystem to prevent external agents from
accessing memory that is currently involved in an atomic operation (e.g., a
semaphore). LOCK is asserted in the first clock of an atomic operation and deasserted when BLAST is deasserted in the last bus cycle.
17
80960HA/HD/HT
Table 7.
80960Hx Processor Family Pin Descriptions (Sheet 3 of 4)
Name
Type
Description
HOLD REQUEST signals that an external agent requests access to the
processor’s address, data, and control buses. When HOLD is asserted, the
processor:
HOLD
I
S(L)
Completes the current bus request.
Asserts HOLDA and floats the address, data, and control buses.
When HOLD is deasserted, the HOLDA pin is deasserted and the processor
reassumes control of the address, data, and control pins.
O
HOLDA
H(1)
B(0)
R(Q)
HOLD ACKNOWLEDGE indicates to an external master that the processor has
relinquished control of the bus. The processor grants HOLD requests and enters
the HOLDA state while the RESET pin is asserted.
HOLDA is never granted while LOCK is asserted.
BUS BACKOFF forces the processor to immediately relinquish control of the bus
on the next clock cycle. When READY/BTERM is enabled and:
BOFF
I
S(L)
When BOFF is asserted, the address, data, and control buses are floated on the
next clock cycle and the current access is aborted.
When BOFF is deasserted, the processor resumes by regenerating the aborted
bus access.
See Figure 16 on page 48 for BOFF timing requirements.
O
BREQ
H(Q)
B(Q)
R(0)
BSTALL
H(Q)
B(Q)
R(0)
O
BUS REQUEST indicates that a bus request is pending in the bus controller.
BREQ does not indicate whether or not the processor is stalled. See BSTALL for
processor stall status. BREQ may be used with BSTALL to indicate to an external
bus arbiter the processor’s bus ownership requirements.
BUS STALL indicates that the processor has stalled pending the result of a
request in the bus controller. When BSTALL is asserted, the processor must
regain bus ownership to continue processing (i.e., it may no longer execute
strictly out of on-chip cache memory).
CYCLE TYPE indicates the type of bus cycle currently being started or processor
state. CT3:0 encoding follows:
O
CT3:0
H(Z)
B(Z)
R(Z)
Cycle Type
ADSCT3:0
Program-initiated access using 8-bit bus
Program-initiated access using 16-bit bus
Program-initiated access using 32-bit bus
Event-initiated access using 8-bit bus
Event-initiated access using 16-bit bus
Event-initiated access using 32-bit bus
Reserved
Reserved for future products
Reserved
00000
00001
00010
00100
00101
00110
00X11
01XXX
1XXXX
EXTERNAL INTERRUPT pins are used to request interrupt service. These pins
may be configured in three modes:
I
XINT7:0
A(E)
A(L)
Dedicated Mode: Each pin is assigned a dedicated interrupt level. Dedicated
inputs may be programmed to be level (low or high) or edge (rising or falling)
sensitive.
Expanded Mode: All eight pins act as a vectored interrupt source. The interrupt
pins are level sensitive in this mode.
Mixed Mode: The XINT7:5 pins act as dedicated sources and the XINT4:0 pins
act as the five most significant bits of a vectored source. The least significant bits
of the vectored source are set to “010” internally.
NMI
18
I
A(E)
NON-MASKABLE INTERRUPT causes a non-maskable interrupt event to occur.
NMI is the highest priority interrupt source. NMI is falling edge triggered.
Datasheet
80960HA/HD/HT
Table 7.
80960Hx Processor Family Pin Descriptions (Sheet 4 of 4)
Name
CLKIN
RESET
STEST
Type
I
I
A(L)
I
S(L)
O
FAIL
H(Q)
B(Q)
R(0)
Description
CLOCK INPUT provides the time base for the 80960Hx. All internal circuitry is
synchronized to CLKIN. All input and output timings are specified relative to
CLKIN.
For the 80960HD, the 2x internal clock is derived by multiplying the CLKIN
frequency by two. For the 80960HT, the 3x internal clock is derived by multiplying
the CLKIN frequency by three.
RESET forces the device into reset. RESET causes all external and internal
signals to return to their reset state (when defined). The rising edge of RESET
starts the processor boot sequence.
SELF TEST, when asserted during the rising edge of RESET, causes the
processor to execute its built in self-test.
FAIL indicates a failure of the processor’s built-in self-test performed during
initialization. FAIL is asserted immediately out of reset and toggles during self-test
to indicate the status of individual tests. When self-test passes, FAIL is deasserted and the processor branches to the user’s initialization code. When selftest fails, the FAIL pin asserts and the processor ceases execution.
ONCE
I
ON-CIRCUIT EMULATION control: the processor samples this pin during reset.
When it is asserted low at the end of reset, the processor enters ONCE mode. In
ONCE mode, the processor stops all clocks and floats all output pins except the
TDO pin. ONCE uses an internal pull-up resistor; see RPU definition in Table 22,
“80960Hx DC Characteristics” on page 40. Pull this pin high when not in use.
TCK
I
TEST CLOCK provides the clocking function for IEEE 1149.1 Boundary Scan
testing.
TDI
I
TEST DATA INPUT is the serial input pin for IEEE 1149.1 Boundary Scan testing.
TDI uses an internal pull-up resistor; see RPU definition in Table 22, “80960Hx DC
Characteristics” on page 40.
TDO
O
TEST DATA OUTPUT is the serial output pin for IEEE 1149.1 Boundary Scan
testing. ONCE does not disable this pin.
I
TEST RESET asynchronously resets the Test Access Port (TAP) controller. TRST
must be held low at least 10,000 clock cycles after power-up. One method is to
provide TRST with a separate power-on-reset circuit. TRST includes an internal
pull-up resistor; see RPU definition in Table 22, “80960Hx DC Characteristics” on
page 40. Pull this pin low when not in use.
TMS
I
TEST MODE SELECT is sampled at the rising edge of TCK. TCK controls the
sequence of TAP controller state changes for IEEE 1149.1 Boundary Scan
testing. TMS uses an internal pull-up resistor; see RPU definition in Table 22,
“80960Hx DC Characteristics” on page 40.
VCC5
I
5 V REFERENCE VOLTAGE input is the reference voltage for the 5 V-tolerant I/O
buffers. Connect this signal to +5 V for use with inputs which exceed 3.3 V. When
all inputs are from 3.3 V components, connect this signal to 3.3 V.
VCCPLL
I
PLL VOLTAGE is the +3.3 VDC analog input for the PLL.
O
VOLTAGE DETECT signal allows external system logic to distinguish between a
5 V 80960Cx processor and the 3.3 V 80960Hx processor. This signal is active
low for a 3.3 V 80960Hx (it is high impedance for 5 V 80960Cx). This pin is
available only on the PGA version.
TRST
VOLDET
0 = 80960Hx
1 = 80960Cx
Datasheet
19
80960HA/HD/HT
3.2
80960Hx Mechanical Data
3.2.1
80960Hx PGA Pinout
Figure 2 depicts the complete 80960Hx PGA pinout as viewed from the top side of the component
(i.e., pins facing down). Figure 3 shows the complete 80960Hx PGA pinout as viewed from the
pin-side of the package (i.e., pins facing up). Table 9 lists the 80960Hx pin names with package
location. See Section 4.3, “Recommended Connections” on page 38 for specifications and
recommended connections.
Figure 2. 80960Hx 168-Pin PGA Pinout—View from Top (Pins Facing Down)
1
2
3
S
R
Q
P
N
M
L
K
J
H
G
F
E
D
C
B
A
D25
D24
D21
D19
D17
D16
D15
D13
D12
D11
D9
D8
D7
D5
D3
BOFF
VSS
D29
D27
D23
D20
D18
VCC
D14
VCC
VCC
D10
VCC
D6
D4
D2
D1
STEST
FAIL
READY
D31
D26
D22
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VCC
D0
NC
ONCE
DP1
DP0
VSS
DP3
DP2
4
HOLDA BTERM D28
5
BE3
HOLD
D30
VCC5
TCK
VOLDET
BE2
ADS
VCC
VCC
TMS
TRST
BE1
VCC
VSS
VSS
VCC
TDI
BLAST
VCC
VSS
VSS
PCHK
TDO
DEN
BE0
VSS
VSS
VCC
NC
W/R
VCC
VSS
DT/R
VCC
VSS
6
7
8
9
10
11
12
13
14
15
16
WAIT BSTALL
i
A80960Hx
2
3
4
5
6
7
8
9
M
© 19xx
VSS VCCPLL
XXXXXXXX SS
10
NC
11
VSS
VCC
CTO
SUP
VSS
VCC
CT1
D/C
BREQ
A30
CLKIN
NC
CT2
LOCK
A29
A28
VCC
NC
CT3
A31
A26
A24
A20
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VCC
NMI
XINT4 XINT0
XINT1
A27
A23
A21
A19
A16
VCC
A13
VCC
VCC
VCC
A7
VCC
A4
A2
XINT6 XINT3
RESET
A25
A22
A18
A17
A15
A14
A12
A11
A10
A9
A8
A6
A5
A3
XINT7 XINT5
XINT2
S
R
Q
P
N
M
L
K
J
H
12
13
14
15
16
17
20
1
17
G
F
E
D
C
B
A
Datasheet
80960HA/HD/HT
Figure 3. 80960Hx 168-Pin PGA Pinout—View from Bottom (Pins Facing Up)
A
B
C
D
E
F
G
H
J
K
L
M
N
P
Q
R
S
VSS
BOFF
D3
D5
D7
D8
D9
D11
D12
D13
D15
D16
D17
D19
D21
D24
D25
FAIL
STEST
D1
D2
D4
D6
VCC
D10
VCC
VCC
D14
VCC
D18
D20
D23
D27
D29
DP0
DP1
ONCE
NC
D0
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VCC
D22
D26
D31
READY
DP2
DP3
VSS
VOLDET
TCK
VCC5
D30
HOLD
BE3
TRST
TMS
VCC
VCC
ADS
BE2
TDI
VCC
VSS
VSS
VCC
BE1
TDO
PCHK
VSS
VSS
VCC
BLAST
NC
VCC
VSS
VSS
BE0
DEN
VCCPLL VSS
VSS
VCC
W/R
VCC
DT/R
1
1
2
2
3
4
5
6
3
4
D28 BTERM HOLDA
5
6
7
7
8
8
9
10
NC
Package Lid
9
10
11
11
CT0
VCC
VSS
VSS
CT1
VCC
VSS
SUP BSTALL WAIT
CT2
NC
CLKIN
A30
BREQ
D/C
CT3
NC
VCC
A28
A29
LOCK
12
12
13
13
14
14
15
15
XINT1
XINT0 XINT4
NMI
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VCC
A20
A24
A26
A31
RESET
XINT3 XINT6
A2
A4
VCC
A7
VCC
VCC
VCC
A13
VCC
A16
A19
A21
A23
A27
XINT2
XINT5 XINT7
A3
A5
A6
A8
A9
A10
A11
A12
A14
A15
A17
A18
A22
A25
D
E
F
G
H
J
K
L
M
N
P
Q
R
S
16
16
17
17
A
Datasheet
B
C
21
80960HA/HD/HT
Table 8.
22
80960Hx 168-Pin PGA Pinout—Signal Name Order (Sheet 1 of 2)
Signal Name
PGA
Pin
Signal Name
PGA
Pin
Signal Name
PGA
Pin
Signal Name
PGA
Pin
A2
D16
ADS
R6
D14
L2
LOCK
S14
A3
D17
BE0
R9
D15
L1
NC
A9
A4
E16
BE1
S7
D16
M1
NC
A10
A5
E17
BE2
S6
D17
N1
NC
B13
A6
F17
BE3
S5
D18
N2
NC
B14
A7
G16
BLAST
S8
D19
P1
NC
D3
A8
G17
BOFF
B1
D20
P2
NMI
D15
A9
H17
BREQ
R13
D21
Q1
ONCE
C3
A10
J17
BSTALL
R12
D22
P3
PCHK
B8
A11
K17
BTERM
R4
D23
Q2
READY
S3
A12
L17
CLKIN
C13
D24
R1
RESET
A16
A13
L16
CT0
A11
D25
S1
STEST
B2
A14
M17
CT1
A12
D26
Q3
SUP
Q12
A15
N17
CT2
A13
D27
R2
TCK
B5
A16
N16
CT3
A14
D28
Q4
TDI
A7
A17
P17
D/C
S13
D29
S2
TDO
A8
A18
Q17
D0
E3
D30
Q5
TMS
B6
A19
P16
D1
C2
D31
R3
TRST
A6
A20
P15
D2
D2
DEN
S9
VCC
B7
A21
Q16
D3
C1
DP0
A3
VCC
B9
A22
R17
D4
E2
DP1
B3
VCC
B11
A23
R16
D5
D1
DP2
A4
VCC
B12
A24
Q15
D6
F2
DP3
B4
VCC
C6
A25
S17
D7
E1
DT/R
S11
VCC
C14
A26
R15
D8
F1
FAIL
A2
VCC
E15
A27
S16
D9
G1
—
—
VCC
F3
A28
Q14
D10
H2
—
—
VCC
F16
A29
R14
D11
H1
—
—
VCC
G2
A30
Q13
D12
J1
HOLD
R5
VCC
H16
A31
S15
D13
K1
HOLDA
S4
VCC
J2
Datasheet
80960HA/HD/HT
Table 8.
Datasheet
80960Hx 168-Pin PGA Pinout—Signal Name Order (Sheet 2 of 2)
Signal Name
PGA
Pin
Signal Name
PGA
Pin
Signal Name
PGA
Pin
Signal Name
PGA
Pin
VCC
J16
VCCPLL
B10
VSS
H3
VSS
Q10
VCC
K2
VOLDET
A5
VSS
H15
VSS
Q11
VCC
K16
VSS
A1
VSS
J3
W/R
S10
VCC
M2
VSS
C4
VSS
J15
WAIT
S12
VCC
M16
VSS
C7
VSS
K3
XINT0
B15
VCC
N3
VSS
C8
VSS
K15
XINT1
A15
VCC
N15
VSS
C9
VSS
L3
XINT2
A17
VCC
Q6
VSS
C10
VSS
L15
XINT3
B16
VCC
R7
VSS
C11
VSS
M3
XINT4
C15
VCC
R8
VSS
C12
VSS
M15
XINT5
B17
VCC
R10
VSS
F15
VSS
Q7
XINT6
C16
VCC
R11
VSS
G3
VSS
Q8
XINT7
C17
VCC5
C5
VSS
G15
VSS
Q9
—
—
23
80960HA/HD/HT
Table 9.
80960Hx 168-Pin PGA Pinout—Pin Number Order (Sheet 1 of 2)
PGA
Pin
24
Signal Name
PGA
Pin
Signal Name
PGA
Pin
Signal Name
PGA
Pin
Signal Name
A1
VSS
B14
NC
E15
VCC
K15
VSS
A2
FAIL
B15
XINT0
E16
A4
K16
VCC
A3
DP0
B16
XINT3
E17
A5
K17
A11
A4
DP2
B17
XINT5
F1
D8
L1
D15
A5
VOLDET
C1
D3
F2
D6
L2
D14
A6
TRST
C2
D1
F3
VCC
L3
VSS
A7
TDI
C3
ONCE
F15
VSS
L15
VSS
A8
TDO
C4
VSS
F16
VCC
L16
A13
A9
NC
C5
VCC5
F17
A6
L17
A12
A10
NC
C6
VCC
G1
D9
M1
D16
A11
CT0
C7
VSS
G2
VCC
M2
VCC
A12
CT1
C8
VSS
G3
VSS
M3
VSS
A13
CT2
C9
VSS
G15
VSS
M15
VSS
A14
CT3
C10
VSS
G16
A7
M16
VCC
A15
XINT1
C11
VSS
G17
A8
M17
A14
A16
RESET
C12
VSS
H1
D11
N1
D17
A17
XINT2
C13
CLKIN
H2
D10
N2
D18
B1
BOFF
C14
VCC
H3
VSS
N3
VCC
B2
STEST
C15
XINT4
H15
VSS
N15
VCC
B3
DP1
C16
XINT6
H16
VCC
N16
A16
B4
DP3
C17
XINT7
H17
A9
N17
A15
B5
TCK
D1
D5
J1
D12
P1
D19
B6
TMS
D2
D2
J2
VCC
P2
D20
B7
VCC
D3
NC
J3
VSS
P3
D22
B8
PCHK
D15
NMI
J15
VSS
P15
A20
B9
VCC
D16
A2
J16
VCC
P16
A19
B10
VCCPLL
D17
A3
J17
A10
P17
A17
B11
VCC
E1
D7
K1
D13
Q1
D21
B12
VCC
E2
D4
K2
VCC
Q2
D23
B13
NC
E3
D0
K3
VSS
Q3
D26
Datasheet
80960HA/HD/HT
Table 9.
80960Hx 168-Pin PGA Pinout—Pin Number Order (Sheet 2 of 2)
PGA
Pin
Datasheet
Signal Name
PGA
Pin
Signal Name
PGA
Pin
Signal Name
PGA
Pin
Signal Name
Q4
D28
Q16
A21
R11
VCC
S6
BE2
Q5
D30
Q17
A18
R12
BSTALL
S7
BE1
Q6
VCC
R1
D24
R13
BREQ
S8
BLAST
Q7
VSS
R2
D27
R14
A29
S9
DEN
Q8
VSS
R3
D31
R15
A26
S10
W/R
Q9
VSS
R4
BTERM
R16
A23
S11
DT/R
Q10
VSS
R5
HOLD
R17
A22
S12
WAIT
Q11
VSS
R6
ADS
S1
D25
S13
D/C
Q12
SUP
R7
VCC
S2
D29
S14
LOCK
Q13
A30
R8
VCC
S3
READY
S15
A31
Q14
A28
R9
BE0
S4
HOLDA
S16
A27
Q15
A24
R10
VCC
S5
BE3
S17
A25
25
80960HA/HD/HT
3.2.2
80960Hx PQ4 Pinout
Figure 4. 80960Hx 208-Pin PQ4 Pinout
PIN 105
A28
A29
A30
A24
A25
A26
A27
VCC
VSS
A4
A5
A6
A7
VCC
VSS
A8
A9
A10
A11
VCC
VSS
A12
A13
A14
A15
VCC
VSS
VSS
VCC
A16
A17
A18
A19
VCC
VSS
A20
A21
A22
A23
VCC
VSS
VCC
VSS
VSS
VSS
VCC
VCC
VSS
A2
A3
VCC
VSS
PIN 156
PIN 104
PIN 157
VSS
VCC
A31
VSS
VCC
VCC
NMI
XINT7
XINT6
XINT5
XINT4
VSS
VCC
XINT3
XINT2
XINT1
XINT0
VSS
VCC
VSS
VCC
BREQ
LOCK
VSS
SUP
D/C
VCC
VSS
VSS
VCC
BSTALL
WAIT
DT/R
W/R
VCC
VSS
RESET
CLKIN
VCC
VCCPLL
VSS
VCC
CT3
CT2
CT1
CT0
VSS
VCC
VSS
VCC
TDO
PCHK
i960
PIN 1
26
BE2
BE3
ADS
VCC
VSS
VCC
VSS
FC80960Hx
HOLDA
VCC
VSS
HOLD
READY
BTERM
VCC
VSS
D31
D30
D29
D28
VCC
VCC
VSS
D27
D26
D25
D24
VSS
XXXXXXXX SS
D21
D22
D23
D20
VCC
VSS
VSS
VCC
D8
D9
D10
D11
V SS
V CC
VSS
VCC
D12
D13
D14
D15
VCC
D16
D17
D18
D19
VSS
VCC
© 19xx
D7
VSS
VCC
M
D4
D5
D6
VCC
D1
BOFF
VCC
D0
FAIL
ONCE
VSS
VSS
VCC
VCC
VSS
VSS
VCC
TDI
TMS
TRST
TCK
VSS
VCC
VCC5
VSS
VCC
VSS
VCC
DP3
DP2
VCC
VSS
DP0
DP1
STEST
D2
D3
VSS
VCC
VSS
i
VSS
PIN 208
DEN
BLAST
BE0
BE1
VCC
VSS
®
PIN 53
PIN 52
Datasheet
80960HA/HD/HT
Table 10. 80960Hx PQ4 Pinout—Signal Name Order (Sheet 1 of 2)
Signal Name
Datasheet
PQ4
Pin
Signal Name
PQ4
Pin
Signal Name
PQ4
Pin
Signal Name
PQ4
Pin
A2
151
BE0
83
D16
39
PCHK
189
A3
150
BE1
82
D17
40
READY
68
A4
147
BE2
79
D18
41
RESET
174
A5
146
BE3
78
D19
42
STEST
208
A6
145
BLAST
84
D20
45
SUP
97
A7
144
BOFF
10
D21
50
TCK
194
A8
141
BREQ
100
D22
51
TDI
191
A9
140
BSTALL
91
D23
52
TDO
188
A10
139
BTERM
67
D24
54
TMS
192
A11
138
CLKIN
175
D25
55
TRST
193
A12
135
CT0
183
D26
56
VCC
1
A13
134
CT1
182
D27
57
VCC
4
A14
133
CT2
181
D28
61
VCC
9
A15
132
CT3
180
D29
62
VCC
11
A16
127
D/C
96
D30
63
VCC
17
A17
126
D0
12
D31
64
VCC
19
A18
125
D1
13
DEN
85
VCC
25
A19
124
D2
14
DP0
206
VCC
31
A20
121
D3
15
DP1
207
VCC
33
A21
120
D4
20
DP2
203
VCC
38
A22
119
D5
21
DP3
202
VCC
44
A23
118
D6
22
DT/R
89
VCC
46
A24
113
D7
23
FAIL
5
VCC
49
A25
112
D8
26
—
—
VCC
59
A26
111
D9
27
—
—
VCC
60
A27
110
D10
28
—
—
VCC
66
A28
107
D11
29
HOLD
69
VCC
71
A29
106
D12
34
HOLDA
72
VCC
74
A30
105
D13
35
LOCK
99
VCC
76
A31
104
D14
36
NMI
159
VCC
81
ADS
77
D15
37
ONCE
6
VCC
87
27
80960HA/HD/HT
Table 10. 80960Hx PQ4 Pinout—Signal Name Order (Sheet 2 of 2)
Signal Name
28
PQ4
Pin
Signal Name
PQ4
Pin
Signal Name
PQ4
Pin
Signal Name
PQ4
Pin
VCC
92
VCC
187
VSS
70
VSS
164
VCC
95
VCC
196
VSS
73
VSS
170
VCC
101
VCC
199
VSS
75
VSS
172
VCC
102
VCC
201
VSS
80
VSS
178
VCC
109
VCC
204
VSS
86
VSS
184
VCC
115
VCC5
197
VSS
93
VSS
186
VCC
117
VCCPLL
177
VSS
94
VSS
190
VCC
123
VSS
2
VSS
98
VSS
195
VCC
128
VSS
3
VSS
103
VSS
198
VCC
131
VSS
7
VSS
108
VSS
200
VCC
137
VSS
8
VSS
114
VSS
205
VCC
143
VSS
16
VSS
116
W/R
88
VCC
149
VSS
18
VSS
122
WAIT
90
VCC
153
VSS
24
VSS
129
XINT0
169
VCC
154
VSS
30
VSS
130
XINT1
168
VCC
158
VSS
32
VSS
136
XINT2
167
VCC
165
VSS
43
VSS
142
XINT3
166
VCC
171
VSS
47
VSS
148
XINT4
163
VCC
173
VSS
48
VSS
152
XINT5
162
VCC
176
VSS
53
VSS
155
XINT6
161
VCC
179
VSS
58
VSS
156
XINT7
160
VCC
185
VSS
65
VSS
157
—
—
Datasheet
80960HA/HD/HT
Table 11. 80960Hx PQ4 Pinout—Pin Number Order (Sheet 1 of 2)
Datasheet
PQ4
Pin
Signal Name
PQ4
Pin
Signal Name
PQ4
Pin
Signal Name
PQ4
Pin
Signal Name
1
VCC
31
VCC
61
D28
91
BSTALL
2
VSS
32
VSS
62
D29
92
VCC
3
VSS
33
VCC
63
D30
93
VSS
4
VCC
34
D12
64
D31
94
VSS
5
FAIL
35
D13
65
VSS
95
VCC
6
ONCE
36
D14
66
VCC
96
D/C
7
VSS
37
D15
67
BTERM
97
SUP
8
VSS
38
VCC
68
READY
98
VSS
9
VCC
39
D16
69
HOLD
99
LOCK
10
BOFF
40
D17
70
VSS
100
BREQ
11
VCC
41
D18
71
VCC
101
VCC
12
D0
42
D19
72
HOLDA
102
VCC
13
D1
43
VSS
73
VSS
103
VSS
14
D2
44
VCC
74
VCC
104
A31
15
D3
45
D20
75
VSS
105
A30
16
VSS
46
VCC
76
VCC
106
A29
17
VCC
47
VSS
77
ADS
107
A28
18
VSS
48
VSS
78
BE3
108
VSS
19
VCC
49
VCC
79
BE2
109
VCC
20
D4
50
D21
80
VSS
110
A27
21
D5
51
D22
81
VCC
111
A26
22
D6
52
D23
82
BE1
112
A25
23
D7
53
VSS
83
BE0
113
A24
24
VSS
54
D24
84
BLAST
114
VSS
25
VCC
55
D25
85
DEN
115
VCC
26
D8
56
D26
86
VSS
116
VSS
27
D9
57
D27
87
VCC
117
VCC
28
D10
58
VSS
88
W/R
118
A23
29
D11
59
VCC
89
DT/R
119
A22
30
VSS
60
VCC
90
WAIT
120
A21
29
80960HA/HD/HT
Table 11. 80960Hx PQ4 Pinout—Pin Number Order (Sheet 2 of 2)
30
PQ4
Pin
Signal Name
PQ4
Pin
Signal Name
PQ4
Pin
Signal Name
PQ4
Pin
121
A20
143
VCC
122
VSS
144
A7
165
VCC
187
VCC
166
XINT3
188
TDO
123
VCC
145
A6
167
XINT2
189
PCHK
Signal Name
124
A19
146
A5
168
XINT1
190
VSS
125
A18
147
A4
169
XINT0
191
TDI
126
A17
148
VSS
170
VSS
192
TMS
127
A16
149
VCC
171
VCC
193
TRST
128
VCC
150
A3
172
VSS
194
TCK
129
VSS
151
A2
173
VCC
195
VSS
130
VSS
152
VSS
174
RESET
196
VCC
131
VCC
153
VCC
175
CLKIN
197
VCC5
132
A15
154
VCC
176
VCC
198
VSS
133
A14
155
VSS
177
VCCPLL
199
VCC
134
A13
156
VSS
178
VSS
200
VSS
135
A12
157
VSS
179
VCC
201
VCC
136
VSS
158
VCC
180
CT3
202
DP3
137
VCC
159
NMI
181
CT2
203
DP2
138
A11
160
XINT7
182
CT1
204
VCC
139
A10
161
XINT6
183
CT0
205
VSS
140
A9
162
XINT5
184
VSS
206
DP0
141
A8
163
XINT4
185
VCC
207
DP1
142
VSS
164
VSS
186
VSS
208
STEST
Datasheet
80960HA/HD/HT
3.3
Package Thermal Specifications
The 80960Hx is specified for operation when TC (case temperature) is within the range of
0 °C to 85 °C. TC may be measured in any environment to determine whether the 80960Hx is
within the specified operating range. Measure the case temperature at the center of the top surface,
opposite the pins. Refer to Figure 5.
TA (ambient temperature) is calculated from θCA (thermal resistance from case to ambient) using
Equation 1:
Equation 1. Calculation of Ambient Temperature (TA)
T A = T C – ( P ⋅ θCA )
Table 12 shows the maximum TA allowable (without exceeding TC) at various airflows and
operating frequencies (fCLKIN).
Note that TA is greatly improved by attaching fins or a heatsink to the package. P (maximum power
consumption) is calculated by using the typical ICC as tabulated in Section 4.6, “DC
Specifications” on page 40 and VCC of 3.3 V.
Figure 5. Measuring 80960Hx PGA Case Temperature
Measure PGA/PQ4 temperature at
center of top surface
Datasheet
31
80960HA/HD/HT
Table 12. Maximum TA at Various Airflows in °C (PGA Package Only)
Airflow-ft/min (m/sec)
Core
1X Bus
Clock
Core
2X Bus
Clock
Core
3X Bus
Clock
fCLKIN
(MHz)
0
(0)
200
(1.01)
400
(2.03)
600
(3.04)
800
(4.06)
1000
(5.07)
TA with
Heatsink†
25
33
40
69
63
59
74
70
67
78
75
73
79
77
75
80
79
77
80
79
77
TA
without
Heatsink
25
33
40
64
56
50
67
62
56
71
67
63
74
70
67
75
72
69
76
74
71
TA with
Heatsink†
16
25
33
40
68
58
49
41
73
66
60
55
77
73
69
65
79
75
71
68
80
77
74
72
80
77
74
72
TA
without
Heatsink
16
25
33
40
62
49
38
27
66
56
46
38
71
62
55
48
73
66
60
55
75
68
63
58
76
71
66
62
TA with
Heatsink†
20
25
53
45
63
58
71
67
73
70
76
73
76
73
TA
without
Heatsink
20
25
43
33
51
42
58
51
63
58
66
61
68
64
† *0.285” high unidirectional heatsink (AI alloy 6061, 50 mil fin width, 150 mil center-to-center fin spacing).
Table 13. 80960Hx 168-Pin PGA Package Thermal Characteristics
Thermal Resistance — °C/Watt
Airflow — ft./min (m/sec)
Parameter
0
(0)
200
(1.01)
400
(2.03)
600
(3.07)
800
(4.06)
1000
(5.07)
θ Junction-to-Case
(Case measured as
shown in Figure 5.)
1.5
1.5
1.5
1.5
1.5
1.5
θ Case-to-Ambient
(No Heatsink)
17
14
11
9
8
7
θ Case-to-Ambient
(With Heatsink)3
13
9
6
5
4
4
θJA
θJC
NOTES:
1. This table applies to 80960Hx PGA plugged into socket or soldered directly to board.
2. θJA = θJC + θCA
3. 0.285” high unidirectional heatsink (AI alloy 6061, 50 mil fin width, 150 mil center-to-center fin spacing).
32
Datasheet
80960HA/HD/HT
Table 14. Maximum TA at Various Airflows in °C (PQ4 Package Only)
Airflow-ft/min (m/sec)
Core
1X Bus
Clock
Core
2X Bus
Clock
Core
3X Bus
Clock
fCLKIN
(MHz)
0
(0)
200
(1.01)
400
(2.03)
600
(3.04)
800
(4.06)
1000
(5.07)
TA with
Heatsink†
25
33
40
71
67
63
76
74
71
79
77
75
79
77
75
80
79
77
80
79
77
TA
without
Heatsink
25
33
40
70
65
61
73
68
65
75
72
69
75
72
69
76
74
71
76
74
71
TA with
Heatsink†
16
25
33
40
71
62
55
48
76
71
66
62
79
75
71
68
79
75
71
68
80
77
74
72
80
77
74
72
TA
without
Heatsink
16
25
33
40
69
60
52
42
72
64
57
51
75
68
63
58
75
68
63
58
76
71
66
62
76
71
66
62
TA with
Heatsink†
20
25
58
51
68
64
73
70
73
70
76
73
76
73
TA
without
Heatsink
20
25
56
48
61
55
66
61
66
61
68
64
68
64
† 0.285” high unidirectional heatsink (AI alloy 6061, 50 mil fin width, 150 mil center-to-center fin spacing).
Table 15. 80960Hx 208-Pin PQ4 Package Thermal Characteristics
Thermal Resistance — °C/Watt
Airflow — ft./min (m/sec)
Parameter
0
(0)
200
(1.01)
400
(2.03)
600
(3.07)
800
(4.06)
1000
(5.07)
θ Junction-to-Case
(Case measured as
shown in Figure 5.)
1
1
1
1
1
1
θ Case-to-Ambient
(No Heatsink)
12
10
8
8
7
7
θ Case-to-Ambient
(With Heatsink)3
11
7
5
5
4
4
θJA
θJC
NOTES:
1. This table applies to 80960Hx PQ4 plugged into socket or soldered directly to board.
2. θJA = θJC + θCA
3. 0.285” high unidirectional heatsink (AI alloy 6061, 50 mil fin width, 150 mil center-to-center fin spacing).
Datasheet
33
80960HA/HD/HT
3.4
Heat Sink Adhesives
Intel recommends silicone-based adhesives to attach heat sinks to the PGA package. There is no
particular recommendation concerning the PQ4 package.
3.5
PowerQuad4 Plastic Package
The 80960Hx family is available in an improved version of the common 208-lead SQFP plastic
package called the PowerQuad4* (PQ4). The PQ4 package dimensions and lead pitch are identical
to the SQFP package and the former PQ2 package, so the PQ4 fits into the same board footprint.
The advantage of the PQ4 package is the superior thermal conductivity that allows the plastic
version of the 80960Hx to operate with the same 0 °C to 85 °C temperature specifications as the
more expensive ceramic PGA package.
The PQ4 package integrates a copper heat sink within the package to dissipate heat effectively. See
Table 14 and Table 15 for more information.
3.6
Stepping Register Information
The memory-mapped register at FF008710H contains the 80960Hx Device ID. The ID is identical
to the ID obtained from a JTAG Query. Figure 6 defines the current 80960Hx Device IDs. The
value for device identification is compliant with the IEEE 1149.1 specification and Intel standards.
Table 16 describes the fields of the device ID.
Figure 6. 80960Hx Device Identification Register
Part Number
Version VCC
1
28
34
Product
Type
0 0 0 1
24
0 0
Gen
0
20
Model
Manufacturer ID
0 1 0
0
16
12
0 0 0 0
8
0 0
1
4
0 0 1
1
1
0
Datasheet
80960HA/HD/HT
Table 16. Fields of 80960Hx Device ID
Field
Value
Definition
Version
See Table 18.
Indicates major stepping changes.
VCC
1 = 3.3 V device
Indicates that a device is 3.3 V.
Product Type
00 0100
(Indicates i960 CPU)
Designates type of product.
Generation Type
0010 = H-series
Indicates the generation (or series) the product belongs to.
Model
See Table 17.
Indicates member within a series and specific model
information.
Manufacturer ID
000 0000 1001
(Indicates Intel)
Manufacturer ID assigned by IEEE.
Table 17. 80960Hx Device ID Model Types
Device
Version
80960HA
80960HD
80960HT
See Table 18.
VCC
Product
Gen.
Model
Manufacturer ID
‘1’
1
000100
0010
00000
00000001001
1
1
000100
0010
00001
00000001001
1
1
000100
0010
00010
00000001001
1
Table 18. Device ID Version Numbers for Different Steppings
Stepping
Version
A0
0000
A1
0001
A2
0001
B0, B2
0010
NOTE: This data sheet applies to the B2 stepping.
Datasheet
35
80960HA/HD/HT
3.7
Sources for Accessories
The following is a list of suggested sources for 80960Hx accessories. This is neither an
endorsement nor a warranty of the performance of any of the listed products and/or companies.
Sockets
• 3M Textool Test and Interconnection Products
6801 River Place Blvd. MS 130-3N-29
Austin, TX 78726-9000
(800) 328-0411 FAX: (800) 932-9373
• Concept Mfg, Inc. (Decoupling Sockets)
400 Walnut St. Suite 609
Redwood City, CA 94063
(415) 365-1162 FAX: (415) 365-1164
Heatsinks/Fins
• Thermalloy, Inc.
2021 West Valley View Lane
Dallas, TX 75234-8993
(972) 243-4321 FAX: (972) 241-4656
• Wakefield Engineering, Inc.
60 Audubon Road
Wakefield, MA 01880
(617) 245-5900 FAX: (617) 246-0874
• Aavid Thermal Technologies, Inc.
One Kool Path
Laconia, NH 03247-0400
(603) 523-3400
36
Datasheet
80960HA/HD/HT
4.0
Electrical Specifications
4.1
Absolute Maximum Ratings
Table 19. Absolute Maximum Ratings
Warning:
4.2
Parameter
Maximum Rating
Storage Temperature
–65 ºC to +150 ºC
Case Temperature Under Bias
–65 ºC to +110 ºC
Supply Voltage with respect to VSS
–0.5 V to + 4.6 V
Voltage on VCC5 with respect to VSS
–0.5 V to + 6.5 V
Voltage on Other Pins with respect to VSS
–0.5 V to VCC5 + 0.5 V
Stressing the device beyond the “Absolute Maximum Ratings” may cause permanent damage.
These are stress ratings only. Operation beyond the “Operating Conditions” is not recommended
and extended exposure beyond the “Operating Conditions” may affect device reliability.
Operating Conditions
Table 20. Operating Conditions
Symbol
Datasheet
Parameter
Min
Max
Units
VCC
Supply Voltage
3.15
3.45
V
VCC5
Input Protection Bias
3.15
5.5
V
fCLKIN 1xcore
Input Clock Frequency - 1x Core (80960HA)
16
40
MHz
fCLKIN 2xcore
Input Clock Frequency - 2x Core (80960HD)
16
40
MHz
fCLKIN 3xcore
Input Clock Frequency - 3x Core (80960HT)
16
25
MHz
TC
Case Temp Under Bias (PGA and PQ4 Packages)
0
85
o
C
37
80960HA/HD/HT
4.3
Recommended Connections
Power and ground connections must be made to multiple VCC and VSS (GND) pins. Every
80960Hx-based circuit board should include power (VCC) and ground (VSS) planes for power
distribution. Every VCC pin must be connected to the power plane; every VSS pin must be
connected to the ground plane. Pins identified as “NC” —no connect pins—must not be connected
in the system.
Liberal decoupling capacitance should be placed near the 80960Hx. The processor may cause
transient power surges when its output buffers transition, particularly when connected to large
capacitive loads.
Low inductance capacitors and interconnects are recommended for best high-frequency electrical
performance. Inductance may be reduced by shortening the board traces between the processor and
decoupling capacitors as much as possible. Capacitors specifically designed for PGA packages
offer the lowest possible inductance.
For reliable operation, always connect unused inputs to an appropriate signal level. In particular,
any unused interrupt (XINT7:0, NMI) input should be connected to VCC through a pull-up resistor,
as should BTERM when not used. Pull-up resistors should be in the range of 20 KΩ for each pin
tied high. When READY or HOLD are not used, the unused input should be connected to ground.
N.C. pins must always remain unconnected.
4.4
VCC5 Pin Requirements (VDIFF)
In mixed-voltage systems that drive 80960Hx processor inputs in excess of 3.3 V, the VCC5 pin
must be connected to the system’s 5 V supply. To limit current flow into the VCC5 pin, there is a
limit to the voltage differential between the VCC5 pin and the other VCC pins. The voltage
differential between the 80960Hx VCC5 pin and its 3.3 V VCC pins should never exceed 2.25 V.
This limit applies to power-up, power-down, and steady-state operation. Table 21 outlines this
requirement.
Meeting this requirement ensures proper operation and ensures that the current draw into the VCC5
pin does not exceed the ICC5 specification.
When the voltage difference requirements cannot be met due to system design limitations, an
alternate solution may be employed. As shown in Figure 7, a minimum of 100 Ω series resistor
may be used to limit the current into the VCC5 pin. This resistor ensures that current drawn by the
VCC5 pin does not exceed the maximum rating for this pin.
Figure 7. VCC5 Current-Limiting Resistor
VCC5 Pin
+5 V (±0.25 V)
100 Ω
(±5%, 0.5 W)
This resistor is not necessary in systems that may ensure the VDIFF specification.
In 3.3 V-only systems and systems that drive 80960Hx pins from 3.3 V logic, connect the VCC5
pin directly to the 3.3 V VCC plane.
38
Datasheet
80960HA/HD/HT
Table 21. VDIFF Specification for Dual Power Supply Requirements (3.3 V, 5 V)
Sym
VDIFF
4.5
Parameter
VCC5-VCC
Difference
Min
Max
Units
Notes
2.25
V
VCC5 input should not exceed VCC by more than 2.25 V during
power-up and power-down, or during steady-state operation.
VCCPLL Pin Requirements
When the voltage on the VCCPLL power supply pin exceeds the VCC pin voltage by 0.5 V at any
time, including the power up and power down sequences, excessive currents may permanently
damage on-chip electrostatic discharge (ESD) protection diodes. The damage may accumulate over
multiple episodes.
Pragmatically, this problem only occurs when the VCCPLL and VCC pins are driven by separate
power supplies or voltage regulators. Applications that use one power supply for VCCPLL and
VCC are not typically at risk. Verify that your application does not allow the VCCPLL voltage to
exceed VCC by 0.5 V.
The VCCPL low-pass filter recommended in the Developer’s Manual does not promote this
problem.
Datasheet
39
80960HA/HD/HT
4.6
D.C.Specifications
Table 22. 80960Hx D.C. Characteristics (Sheet 1 of 2)
Per the conditions described in Section 4.3, “Recommended Connections” on page 38.
Symbol
Parameter
Min
Typ
Max
Units
Notes
VIL
Input Low Voltage
– 0.3
+0.8
V
VIH
Input High Voltage
2.0
VCC5 + 0.3
V
All outputs except FAIL
0.4
0.2
V
IOL = 3 mA
IOL = 100 µA
VOL
Output Low Voltage FAIL pin
0.4
V
IOL = 5 mA
VOH
Output High Voltage
V
V
IOH = –3 mA
IOH = –100 µA
VOL
Output Low Voltage
2.4
VCC – 0.2
Input Leakage Current
ILI
1
µA
0 ≤ VIN ≤ VCC
-110
µA
VIN = 0 V
Non-Test Outputs
1
µA
0.45 ≤ VOUT ≤ VCC
TDO pin
5
µA
0.45 ≤ VOUT ≤ VCC
mA
4, 5
mA
4, 6
mA
7, 8
mA
7
Non-Test Inputs
-1
TDI, TMS, TRST and ONCE
Output Leakage Current
ILO
ICC Active
(Power
Supply)
ICC Active
(Thermal)
ICC Test
(Reset
Mode)
ICC Test
(ONCE
mode)
40
80960HA 25
33
40
579
765
927
80960HD 32
50
66
80
631
985
1300
1578
80960HT 60
75
1165
1455
80960HA 25
33
40
392
518
628
80960HD 32
50
66
80
413
645
851
1034
80960HT 60
75
752
938
80960HA 25
33
40
330
436
528
80960HD 32
50
66
80
382
595
785
955
80960HT 60
75
702
878
25
Datasheet
80960HA/HD/HT
Table 22. 80960Hx D.C. Characteristics (Sheet 2 of 2)
Per the conditions described in Section 4.3, “Recommended Connections” on page 38.
Symbol
ICC5
Current on
the VCC5
Pin
Parameter
Min
Typ
80960HA
80960HD
80960HT
Max
Units
Notes
200
200
200
µA
9
12
12
pF
pF
FC = 1 MHz10
Input Capacitance for:
CIN
PQ4
PGA
COUT
Output Capacitance of each
output pin
12
pF
FC = 1 MHz3, 10
CI/O
I/O Pin Capacitance
12
pF
FC = 1 MHz10
RPU
Internal Pull-Up Resistance
for ONCE, TMS, TDI and
TRST
100
kΩ
30
65
NOTES:
1. ICC Maximum is measured at worst case frequency, VCC, and temperature, with device operating and
outputs loaded to the test conditions described in Section 4.7.1, “AC Test Conditions” on page 45.
2. ICC Typical is not tested.
3. Output Capacitance is the capacitive load of a floating output.
4. Measured with device operating and outputs loaded to the test conditions in Figure 8, “AC Test Load” on
page 45. Input signals rise to VCC and fall to VSS.
5. ICC Active (Power Supply) value is provided for selecting your system’s power supply. It is measured using
one of the worst case instruction mixes with VCC = 3.45 V. This parameter is characterized but not tested.
6. ICC Active (Thermal) value is provided for your system’s thermal management. Typical ICC is measured with
VCC = 3.3 V and temperature = 25°C. This parameter is characterized but not tested.
7. ICC Test (Power modes) refers to the ICC values that are tested when the 80960HA/HD/HT is in Reset mode
or ONCE mode with VCC = 3.45 V.
8. Worst case is VCC = 3.45 V, 0 °C.
9. ICC5 is tested at VCC = 3.0 V, VCC5 = 5.25 V.
10.Pin capacitance is characterized, but not tested.
Datasheet
41
80960HA/HD/HT
4.7
A.C. Specifications
Table 23. 80960Hx A.C. Characteristics (Sheet 1 of 2)
Per conditions in Section 4.2, “Operating Conditions” on page 37 and Section 4.7.1, “AC Test Conditions” on page 45.
Symbol
Parameter
Min
Max
Units
Notes
16
16
16
40
40
25
MHz
MHz
MHz
25
25
40
62.5
62.5
62.5
ns
ns
ns
-250
+250
ps
11
8
ns
11
8
8
8
ns
ns
ns
11
Input Clock1, 7
CLKIN Frequency
TF
80960HA
80960HD
80960HT
CLKIN Period
80960HA
T
80960HD
80960HT
TCS
CLKIN Period Stability
TCH
CLKIN High Time
CLKIN Low Time
TCL
80960HA
80960HD
80960HT
TCR
CLKIN Rise Time
0
4
ns
11
TCF
CLKIN Fall Time
0
4
ns
11
1.5
9.5
ns
T/2 + 1.5
3T/4 + 1.5
5T/6 + 1.5
T/2 + 9.5
3T/4 + 9.5
5T/6 + 9.5
ns
ns
ns
Synchronous Outputs1, 2, 3, 6
TOV1, TOH1
Output Valid Delay and Output Hold for all
outputs except DT/R, BLAST and BREQ for
3.3 V and 5 V inputs and I/Os.
Output Valid Delay and Output Hold for DT/R
80960HA
80960HD
80960HT
TOV2, TOH2
TOV3, TOH3
Output Valid Delay and Output Hold for BLAST
1.5
9
ns
TOV4, TOH4
Output Valid Delay and Output Hold for BREQ
0.5
9
ns
TOV5, TOH5
Output Valid Delay and Output Hold for A3:2
1.5
8.5
TOF
Output Float for all outputs
1.5
9
ns
11
Synchronous Inputs1, 7, 8, 9
Input Setup for all inputs except READY, BTERM,
TIS1
HOLD, and BOFF
TIH1
HOLD, and BOFF
Input Hold for all inputs except READY, BTERM,
2.5
ns
2.5
ns
NOTE: See Table 24, “AC Characteristics Notes” on page 44 for all notes related to AC specifications.
42
Datasheet
80960HA/HD/HT
Table 23. 80960Hx A.C. Characteristics (Sheet 2 of 2)
Per conditions in Section 4.2, “Operating Conditions” on page 37 and Section 4.7.1, “AC Test Conditions” on page 45.
Symbol
TIS2
TIH2
Parameter
Min
Input Setup for READY, BTERM, HOLD, and
BOFF
Input Hold for READY, BTERM, HOLD, and
BOFF
Max
Units
6
ns
2.5
ns
Notes
Relative Output Timings1, 2, 3, 6, 10
TAVSH1
A31:2 Valid to ADS Rising
T–5
T+5
ns
10
TAVSH2
BE3:0, W/R, SUP, D/C Valid to ADS Rising
T–5
T+5
ns
10
TAVEL1
A31:2 Valid to DEN Falling
T–5
T+5
ns
10
TAVEL2
BE3:0, W/R, SUP Valid to DEN Falling
T–5
T+5
ns
10
TNLQV
WAIT Falling to Output Data Valid
-5
5
ns
10
TDVNH
Output Data Valid to WAIT Rising
-5 + N*T
5 + N*T
ns
4, 10
TNLNH
WAIT Falling to WAIT Rising
-4 + N*T
4 + N*T
ns
4, 10
TNHQX
Output Data Hold after WAIT Rising
-5 +
(N+1)*T
5 + (N+1)*T
ns
5, 10
TEHTV
DT/R Hold after DEN High
T/2 – 5
Infinite
ns
10
ns
ns
ns
10
DT/R Valid to DEN Falling
80960HA
80960HD
80960HT
TTVEL
T/2 – 4
T/4 – 4
T/6 – 4
Relative Input Timings1, 7, 10
TIS7
XINT7:0, NMI Input Setup
6
ns
9
TIH7
XINT7:0, NMI Input Hold
2.5
ns
9
TIS8
RESET Input Setup
3
ns
8
TIH8
RESET Input Hold
T/4 + 1
ns
8
NOTE: See Table 24, “AC Characteristics Notes” on page 44 for all notes related to AC specifications.
Datasheet
43
80960HA/HD/HT
Table 24. A.C. Characteristics Notes
NOTES:
1. See Section 4.8, “AC Timing Waveforms” on page 46 for waveforms and definitions.
2. See Figure 25, “Output Delay or Hold vs. Load Capacitance” on page 52 for capacitive derating information
for output delays and hold times.
3. See Figure 22, “Rise and Fall Time Derating at 85 °C and Minimum VCC” on page 51 for capacitive
derating information for rise and fall times.
4. Where N is the number of NRAD, NRDD, NWAD or NWDD wait states that are programmed in the Bus
Controller Region Table. WAIT never goes active when there are no wait states in an access.
5. N = Number of wait states inserted with READY.
6. These specifications are ensured by the processor.
7. These specifications must be met by the system for proper operation of the processor.
8. RESET is an asynchronous input that has no required setup and hold time for proper operation. However,
to ensure the device exits the reset mode synchronized to a particular clock edge, the rising edge of
RESET must meet setup and hold times to the rising edge of the CLKIN.
9. The interrupt pins are synchronized internally by the 80960Hx. They have no required setup or hold times
for proper operation. These pins are sampled by the interrupt controller every clock and must be active for
at least two consecutive CLKIN rising edges when asserting them asynchronously. To ensure recognition at
a particular clock edge, the setup and hold times shown must be met.
10.Relative Output timings are not tested.
11. Not tested.
12.The processor minimizes changes to the bus signals when transitioning from a bus cycle to an idle bus for
the following signals: A31:4, SUP, CT3:0, D/C, LOCK, W/R, BE3:0.
Table 25. 80960Hx Boundary Scan Test Signal Timings
Symbol
TBSF
Parameter
TCK Frequency
Min
Max
Units
0
8
MHz
Infinite
Notes
TBSC
TCK Period
125
TBSCH
TCK High Time
40
ns
Measured at 1.5 V†
TBSCL
TCK Low Time
40
ns
Measured at 1.5 V†
TBSCR
TCK Rise Time
8
ns
0.8 V to 2.0 V†
TBSCF
TCK Fall Time
8
ns
2.0 V to 0.8 V†
TBSIS1
Input Setup to TCK —
TDI, TMS
8
ns
TBSIH1
Input Hold from TCK —
TDI, TMS
10
ns
3
TBSOV1
TDO Valid Delay
TBSOF1
TDO Float Delay
TBSOV2
All Outputs (Non-Test)
Valid Delay
TBSOF2
All Outputs (Non-Test)
Float Delay
TBSIS2
Input Setup to TCK - All
Inputs (Non-Test)
TBSIH2
Input Hold from TCK - All
Inputs (Non-Test)
3
ns
30
ns
36
ns
30
ns
36
ns
8
ns
10
ns
†
Relative to TCK
Relative to TCK†
† Not tested.
44
Datasheet
80960HA/HD/HT
4.7.1
A.C. Test Conditions
A.C. values are derived using the 50 pF load shown in Figure 8. Figure 25, “Output Delay or Hold vs.
Load Capacitance” on page 52, shows how timings vary with load capacitance. Input waveforms
(except for CLKIN) are assumed to have a rise and fall time of ≤ 2 ns from 0.8 V to 2.0 V.
Figure 8. A.C. Test Load
Output Pin
CL
CL = 50 pF for all signals
Datasheet
45
80960HA/HD/HT
4.8
A.C. Timing Waveforms
Figure 9. CLKIN Waveform
TCR
TCF
2.0 V
1.5 V
0.8 V
TCH
TCL
T
Figure 10. Output Delay Waveform
1.5 V
CLKIN
Outputs:
A31:2, D31:0 write only,
DP3:0 write only
PCHK, BE3:0, W/R, D/C,
SUP, ADS, DEN,
LOCK, HOLDA, BREQ, BSTALL,
CT3:0, FAIL, WAIT, BLAST
TOH1
1.5 V
TOV1
Max
Min
1.5 V
1.5 V
Figure 11. Output Delay Waveform
CLKIN
1.5 V
1.5 V
TOV2
TOH2
DT/R
46
1.5 V
Min
Max
1.5 V
Datasheet
80960HA/HD/HT
Figure 12. Output Float Waveform
1.5 V
CLKIN
Outputs:
A31:2, D31:0 write only,
DP3:0 write only
PCHK, BE3:0, W/R, D/C,
SUP, ADS, DEN,
LOCK, HOLDA,
TOF
1.5 V
Max
Min
CT3:0, WAIT, BLAST, DT/R
Figure 13. Input Setup and Hold Waveform
1.5 V
CLKIN
1.5 V
1.5 V
TIH
TIS
Min
Min
Inputs:
READY, HOLD, BTERM,
BOFF, D31:0 on reads,
DP3:0 on reads, RESET
Valid
Figure 14. NMI, XINT7:0 Input Setup and Hold Waveform
A
CLKIN
B
1.5 V
A
1.5 V
TIH
Min
TIS
Min
NMI, XINT7:0
NOTE:
Datasheet
1.5 V
1.5 V
Valid
1.5 V
A and B edges are established by de-assertion of RESET. See Figure 29, “Cold Reset Waveform” on page 54.
47
80960HA/HD/HT
Figure 15. Hold Acknowledge Timings
CLKIN
HOLD
1.5 V
TIH
TIS
Min
Min
1.5 V
TIH
TIS
Min
Min
1.5 V
1.5 V
TOV1
TOH1
HOLDA
1.5 V
1.5 V
TOV1
Max
Min
1.5 V
TOH1
Max
Min
1.5 V
1.5 V
TOV TOH — OUTPUT DELAY - The maximum output delay is referred to as the Output Valid Delay (TOV).
The minimum output delay is referred to as the Output Hold (TOH).
TIS TIH — INPUT SETUP AND HOLD - The input setup and hold requirements specify the sampling window
during which synchronous inputs must be stable for correct processor operation.
Figure 16. Bus Backoff (BOFF) Timings
TIH
BOFF
48
1.5 V
1.5 V
CLKIN
1.5 V
1.5 V
TIS
TIS
TIH
1.5 V
1.5 V
Datasheet
80960HA/HD/HT
Figure 17. TCK Waveform
TBSCR
TBSCF
2.0 V
1.5 V
0.8 V
TBSCH
TBSCL
TBSC
Figure 18. Input Setup and Hold Waveforms for TBSIS1 and TBSIH1
TCLK
1.5 V
1.5 V
TBSIS1
Inputs:
TMS
TDI
Datasheet
1.5 V
1.5 V
TBSIH1
Valid
1.5 V
49
80960HA/HD/HT
Figure 19. Output Delay and Output Float for TBSOV1 and TBSOF1
TCK
1.5 V
1.5 V
TBSOV1
TDO
1.5 V
TBSOF1
Valid
1.5 V
Figure 20. Output Delay and Output Float Waveform for TBSOV2 and TBSOF2
TCK
1.5 V
1.5 V
TBSOV2
Non-Test
Outputs
1.5 V
1.5 V
TBSOF2
Valid
Figure 21. Input Setup and Hold Waveform for TBSIS2 and TBSIH2
TCK
1.5 V
1.5 V
1.5 V
TBSIS2 TBSIH2
Non-Test
Inputs
50
1.5 V
Valid
1.5 V
Datasheet
80960HA/HD/HT
Figure 22. Rise and Fall Time Derating at 85 °C and Minimum VCC
5
Time (ns)
4
3
2.0 to 0.8 V
0.8 to 2.0 V
2
1
50pF
100pF
150pF
CL (pF)
Figure 23. ICC Active (Power Supply) vs. Frequency
ICC Active (Power Supply) (mA)
1800
1600
1400
1200
1000
HA
800
600
HD
400
HT
200
0
0
10
20
30
40
CLKIN Frequency (MHz)
Datasheet
51
80960HA/HD/HT
Figure 24. ICC Active (Thermal) vs. Frequency
1400
ICC Active (Thermal) (mA)
1200
1000
800
HA
600
HD
400
HT
200
10
20
30
40
CLKIN Frequency (MHz)
Output Valid Delays (ns) @ 1.5 V
Figure 25. Output Delay or Hold vs. Load Capacitance
nom + 10
5.5 V Input Signals
3.3 V Input Signals
nom + 5
nom
50
100
150
CL (pF)
52
Datasheet
80960HA/HD/HT
Figure 26. Output Delay vs. Temperature
Output Valid Delays (ns) @ 1.5 V
Processor Case Temperature (°C)
nom - 0.0
0°C
85°C
nom - 0.1
nom - 0.2
nom - 0.3
nom - 0.4
nom - 0.5
Figure 27. Output Hold Times vs. Temperature
Output Hold Times (ns) @ 1.5 V
Processor Case Temperature (°C)
nom + 0.5
0°C
85°C
nom + 0.4
nom + 0.3
nom + 0.2
nom + 0.1
nom + 0
Output Valid or Hold Delays (ns) @ 1.5 V
Figure 28. Output Delay vs. VCC
nom + 0.5
nom + 0.3
nom + 0.1
-nom + 0.1
-nom + 0.3
-nom + 0.5
3.15
3.45
VCC (volts)
Datasheet
53
~
~
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼ ∼
∼
∼
∼
∼
∼ ∼
∼
∼
∼
∼
∼
∼
∼ ∼
∼
∼
∼ ∼
∼
∼
∼ ∼
∼
Valid
Datasheet
CLKIN and VCC Stable to RESET high,
minimum 10,000 CLKIN periods
for PLL stabilization.
NOTE:
Thold
1CLKIN
∼
∼
RESET
∼
∼
Tsetup
1CLKIN
∼
∼ ∼
∼
∼
∼
Invalid
∼
∼
Inputs
∼
∼ ∼
∼
∼
∼ ∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
STEST
∼
∼
D31:0,
DP3:0
∼
∼
W/R, DT/R,
BREQ, FAIL,
BSTALL
RESET high to First Bus Activity,
HA=67, HD=34, HT=23
CLKIN periods
VCC stable: As specified in Table 21, “VDIFF Specification for Dual Power Supply Requirements (3.3 V, 5 V)” on page 39
80960HA/HD/HT
CT3:0, ADS,
LOCK, WAIT,
DEN, BLAST
A31:2, SUP
D/C, BE3:0
B
Bus Waveforms
VCC, VCC5,
ONCE
A
Figure 29. Cold Reset Waveform
CLKIN
B
5.0
54
A
∼
∼
∼
∼ ∼
∼
∼
∼
STEST
∼
∼
Valid
Tsetup
1 CLKIN
Thold
1 CLKIN
∼
∼
Maximum RESET Low to RESET State
16 CLKIN Periods
∼
∼ ∼
∼
∼
∼ ∼
∼
∼
∼
D31:0,
DP3:0
∼
∼
SUP,
A31:2,
D/C, BE3:0
∼
∼
∼
∼
DT/R
RESET
∼
∼
∼
∼
∼
∼
ADS,
LOCK, WAIT,
DEN, BLAST,
W/R, BREQ, FAIL,
BSTALL
Figure 30. Warm Reset Waveform
Datasheet
CLKIN
Minimum RESET Low Time
16 CLKIN Periods
55
80960HA/HD/HT
RESET High to First Bus Activity,
HA=67, HD=34, HT=23
CLKIN Periods
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼ ∼
∼
ONCE mode is entered within 1 CLKIN
period after ONCE becomes low while
RESET is low.
∼
∼ ∼
∼
∼
∼
∼
∼
ONCE
∼
∼ ∼
∼
RESET
∼
∼ ∼
∼
∼
∼
ADS, BE3:0, A31:2,
D31:0, LOCK, WAIT,
BLAST,W/R, D/C, DEN,
DT/R, HOLDA,
BLAST, FAIL, SUP,BREQ,
CT3:0, BSTALL, DP3:0,
PCHK
∼
∼
VCC, VCC5
CLKIN and VCC Stable and RESET low and ONCE low to
RESET high, minimum 10,000 CLKIN Periods.
Datasheet
NOTES:
1. ONCE mode may be entered prior to the rising edge of RESET: ONCE input is not latched until the rising
edge of RESET.
2. The ONCE input may be removed after the processor enters ONCE mode.
Figure 31. Entering ONCE Mode
CLKIN
80960HA/HD/HT
56
CLKIN may neither float nor remain idle.
It must continue to run.
80960HA/HD/HT
Figure 32. Non-Burst, Non-Pipelined Requests without Wait States
PMCON
Function
Bit
Value
External
Ready
Control
Burst
29
28
Disabled Disabled
0
0
PipeLining
Bus
Width
Odd
Parity
24
23-22
OFF
0
X
xx
Parity
Enable
NXDA
NWDD
21
20
19-16
X
x
Enabled
1
0
0000
NWAD
NRDD
NRAD
15-14
12-8
7-6
4-0
0
00
0
00000
0
00
0
00000
NOTE: Bits 31-30, 27-25, 13, and 5 are reserved.
A
D
A
D
A
D
CLKIN
ADS
A31:2, SUP,
D/C, BE3:0,
LOCK, CT3:0
Valid
Valid
Valid
W/R
BLAST
DT/R
DEN
WAIT
D31:0,
DP3:0
In
Out
In
PCHK
Datasheet
57
80960HA/HD/HT
Figure 33. Non-Burst, Non-Pipelined Read Request with Wait States
PMCON
Function
External
Ready
Control
Burst
29
28
Bit
Disabled Disabled
0
0
Value
PipeLining
Bus
Width
Odd
Parity
24
23-22
OFF
0
X
xx
Parity
Enable
NXDA
NWDD
21
20
19-16
X
x
Enabled
1
1
0001
NWAD
NRDD
NRAD
15-14
12-8
7-6
4-0
X
xx
X
xxxxx
X
xx
3
00011
NOTE: Bits 31-30, 27-25, 13, and 5 are reserved.
A
3
2
1
D
1
A
CLKIN
ADS
A31:2, BE3:0
Valid
W/R
BLAST
DT/R
DEN
D/C, SUP,
LOCK, CT3:0
Valid
WAIT
D31:0,
DP3:0
In
PCHK
58
Datasheet
80960HA/HD/HT
Figure 34. Non-Burst, Non-Pipelined Write Request with Wait States
PMCON
Function
Bit
Value
External
Ready
Control
Burst
29
28
Disabled Disabled
0
0
PipeLining
Bus
Width
Odd
Parity
24
23-22
OFF
0
X
xx
Parity
Enable
NXDA
NWDD
NWAD
NRDD
NRAD
21
20
19-16
15-14
12-8
7-6
4-0
X
x
Enabled
1
1
0001
X
xxxxx
3
00011
X
xx
X
xxxxx
NOTE: Bits 31-30, 27-25, 13, and 5 are reserved.
A
3
2
1
D
1
A
CLKIN
ADS
A31:2,
BE3:0
Valid
W/R
BLAST
DT/R
DEN
D/C, SUP,
LOCK, CT3:0
Valid
WAIT
D31:0,
DP3:0
Out
PCHK
Datasheet
59
80960HA/HD/HT
Figure 35. Burst, Non-Pipelined Read Request without Wait States, 32-Bit Bus
PMCON
Function
External
Ready
Control
Burst
29
28
Bit
Value
PipeLining
Disabled Enabled
1
0
Parity
Enable
NXDA
NWDD
NWAD
NRDD
NRAD
21
20
19-16
15-14
12-8
7-6
4-0
X
x
Enabled
1
0
0000
X
xx
X
xxxxx
0
00
0
00000
Bus
Width
Odd
Parity
24
23-22
OFF
0
32-Bit
10
NOTE: Bits 31-30, 27-25, 13, and 5 are reserved.
A
D
D
D
D
A
CLKIN
ADS
A31:4, SUP,
CT3:0,D/C,
BE3:0, LOCK
Valid
W/R
BLAST
DT/R
DEN
A3:2
00
01
10
11
WAIT
D31:0,
DP3:0
In0
In1
In2
In3
PCHK
60
Datasheet
80960HA/HD/HT
Figure 36. Burst, Non-Pipelined Read Request with Wait States, 32-Bit Bus
PMCON
Function
Bit
Value
External
Ready
Control
Burst
PipeLining
Bus
Width
Odd
Parity
Parity
Enable
NXDA
NWDD
NWAD
NRDD
NRAD
29
28
24
23-22
21
20
19-16
15-14
12-8
7-6
4-0
OFF
0
32-Bit
10
X
x
Enabled
1
1
0001
X
xx
X
xxxxx
1
01
2
00010
Disabled Enabled
1
0
NOTE: Bits 31-30, 27-25, 13, and 5 are reserved.
A
2
1
D
1
D
1
D
1
D
1
A
CLKIN
ADS
A31:4, SUP,
CT3:0, D/C,
BE3:0, LOCK
Valid
W/R
BLAST
DT/R
DEN
A3:2
00
01
10
11
WAIT
D31:0,
DP3:0
In0
In1
In2
In3
PCHK
Datasheet
61
80960HA/HD/HT
Figure 37. Burst, Non-Pipelined Write Request without Wait States, 32-Bit Bus
PMCON
External
Function Ready
Control
Bit
Value
29
Burst
PipeLining
Bus
Width
Odd
Parity
Parity
Enable
NXDA
NWDD
NWAD
NRDD
NRAD
28
24
23-22
21
20
19-16
15-14
12-8
7-6
4-0
OFF
0
32-Bit
10
X
x
Enabled
1
0
0000
0
00
0
00000
X
xx
X
xxxxx
Disabled Enabled
1
0
NOTE: Bits 31-30, 27-25, 13, and 5 are reserved.
A
D
D
D
D
A
CLKIN
ADS
A31:4, SUP,
CT3:0, D/C,
BE3:0, LOCK
Valid
W/R
BLAST
DT/R
DEN
A3:2
00
01
10
11
Out1
Out2
Out3
WAIT
D31:0,
DP3:0
Out0
PCHK
62
Datasheet
80960HA/HD/HT
Figure 38. Burst, Non-Pipelined Write Request with Wait States, 32-Bit Bus
PMCON
Function
Bit
External
Ready
Control
Burst
29
28
Disabled Enabled
1
0
Value
PipeLining
Bus
Width
Odd
Parity
24
23-22
OFF
0
32-bit
10
Parity
Enable
NXDA
NWDD
NWAD
NRDD
NRAD
21
20
19-16
15-14
12-8
7-6
4-0
X
x
Enabled
1
1
0001
1
01
2
00010
X
xx
X
xxxxx
NOTE: Bits 31-30, 27-25, 13, and 5 are reserved.
A
2
1
D
1
D
1
D
1
D
1
A
CLKIN
ADS
A31:4, SUP,
CT3:0, D/C,
BE3:0, LOCK
Valid
W/R
BLAST
DT/R
DEN
A3:2
00
01
10
11
WAIT
D31:0,
DP3:0
Out0
Out1
Out2
Out3
PCHK
Datasheet
63
80960HA/HD/HT
Figure 39. Burst, Non-Pipelined Read Request with Wait States, 16-Bit Bus
PMCON
Function
Bit
Value
External
Ready
Control
Burst
29
28
Disabled Enabled
1
0
PipeLining
Parity
Enable
NXDA
NWDD
NWAD
NRDD
NRAD
21
20
19-16
15-14
12-8
7-6
4-0
X
x
Enabled
1
1
0001
X
xx
X
xxxxx
1
01
2
00010
D
1
A
Bus
Width
Odd
Parity
24
23-22
OFF
0
16-Bit
01
NOTE: Bits 31-30, 27-25, 13, and 5 are reserved.
A
2
1
D
1
D
1
D
1
CLKIN
ADS
SUP, CT3:0,
D/C, LOCK,
A31:4, BE3/BHE,
BE0/BLE
Valid
W/R
BLAST
DT/R
DEN
A3:2
A3:2 = 00 or 10
A3:2 = 01 or 11
BE1/A1
WAIT
D31:0,
DP3:0
D15:0
A1=0
D15:0
A1=1
D15:0
A1=0
D15:0
A1=1
PCHK
64
Datasheet
80960HA/HD/HT
Figure 40. Burst, Non-Pipelined Read Request with Wait States, 8-Bit Bus
PMCON
Function
External
Ready
Control
Burst
29
28
Bit
Disabled Enabled
1
0
Value
Parity
Enable
NXDA
NWDD
21
20
19-16
X
x
Enabled
1
1
0001
PipeLining
Bus
Width
Odd
Parity
24
23-22
OFF
0
8-Bit
00
NWAD
NRDD
NRAD
15-14
12-8
7-6
4-0
X
xx
X
xxxxx
1
01
2
00010
NOTE: Bits 31-30, 27-25, 13, and 5 are reserved.
A
2
1
D
1
D
1
D
1
D
1
A
CLKIN
ADS
SUP, CT3:0,
D/C, LOCK,
A31:4
Valid
W/R
BLAST
DT/R
DEN
A3:2
BE1/A1,
BE0/A0
A3:2 = 00, 01, 10 or 11
A1:0 = 00
A1:0 = 01
A1:0 = 10
A1:0 =11
WAIT
D31:0,
DP3:0
D7:0
Byte 0
D7:0
Byte 1
D7:0
Byte 2
D7:0
Byte 3
PCHK
Datasheet
65
80960HA/HD/HT
Figure 41. Non-Burst, Pipelined Read Request without Wait States, 32-Bit Bus
PMCON
External
Function Ready
Control
PipeLining
Burst
Bus
Width
Odd
Parity
Parity
Enable
NXDA
NWDD
NWAD
NRDD
NRAD
Bit
29
28
24
23-22
21
20
19-16
15-14
12-8
7-6
4-0
Value
X
x
Disabled
0
ON
1
32-Bit
10
X
x
Enabled
1
X
xxxx
X
xx
X
xxxxx
X
xx
0
00000
NOTE: Bits 31-30, 27-25, 13, and 5 are reserved.
1
A’
D
A
A’’
D’
A’’’’
D’’’
A’’’
D’’
D’’’’
2
CLKIN
ADS
A31:4, SUP,
CT3:0, D/C,
LOCK
Valid
Valid
Valid
Valid
Valid
Invalid
W/R
A3:2
BE3:0
D31:0,
DP3:0
Invalid
Valid
Valid
IN
D
Valid
Valid
IN
D’
IN
D’’
Valid
IN
D’’’
Invalid
IN
D’’’’
WAIT
BLAST
DT/R
DEN
PCHK
1. Non-pipelined request concludes, pipelined reads begin.
2. Pipelined reads conclude, non-pipelined requests begin.
66
Datasheet
80960HA/HD/HT
Figure 42. Non-Burst, Pipelined Read Request with Wait States, 32-Bit Bus
PMCON
External
Function Ready
Control
Burst
PipeLining
Bus
Width
Odd
Parity
Parity
Enable
NXDA
NWDD
NWAD
NRDD
NRAD
Bit
29
28
24
23-22
21
20
19-16
15-14
12-8
7-6
4-0
Value
X
x
Disabled
0
ON
1
32-Bit
10
X
x
Enabled
1
X
xxxx
X
xx
X
xxxxx
X
xx
1
00001
NOTE: Bits 31-30, 27-25, 13, and 5 are reserved.
1
A
1
A’
D
1
D’
2
CLKIN
ADS
A31:4, SUP,
CT3:0, D/C,
LOCK
Valid
Valid
Invalid
W/R
A3:2
BE3:0
D31:0,
DP3:0
Invalid
Valid
Valid
IN
D
Invalid
IN
D’
WAIT
BLAST
DT/R
DEN
PCHK
1. Non-pipelined request concludes, pipelined reads begin
2. Pipelined reads conclude, non-pipelined requests begin
Datasheet
67
80960HA/HD/HT
Figure 43. Burst, Pipelined Read Request without Wait States, 32-Bit Bus
PMCON
External
Function Ready
Control
Burst
PipeLining
Bus
Width
Odd
Parity
Parity
Enable
NXDA
NWDD
NWAD
NRDD
NRAD
24
23-22
21
20
19-16
15-14
12-8
7-6
4-0
ON
1
32-Bit
10
X
x
Enabled
1
X
xxxx
X
xx
X
xxxxx
0
00
0
00000
Bit
29
28
Value
X
x
Enabled
1
NOTE: Bits 31-30, 27-25, 13, and 5 are reserved.
1 A
D
D
D
A’
D
D’ 2
D’
CLKIN
ADS
A31:4, SUP,
CT3:0, D/C,
BE3:0, LOCK
Valid
InValid
Valid
W/R
A3:2
D31:0,
DP3:0
00
01
IN
D
10
IN
D
11
IN
D
Valid
Valid
IN
D
IN
D
InValid
IN
D
WAIT
BLAST
DT/R
DEN
PCHK
1. Non-pipelined request concludes, pipelined reads begin
2. Pipelined reads conclude, non-pipelined requests begin
68
Datasheet
80960HA/HD/HT
Figure 44. Burst, Pipelined Read Request with Wait States, 32-Bit Bus
PMCON
Function
External
Ready
Control
Burst
PipeLining
Bus
Width
Odd
Parity
Parity
Enable
NXDA
NWDD
NWAD
NRDD
NRAD
Bit
29
28
24
23-22
21
20
19-16
15-14
12-8
7-6
4-0
Value
X
x
Enabled
1
ON
1
32-Bit
10
X
x
Enabled
1
X
xxxx
X
xx
X
xxxxx
1
01
2
00010
NOTE: Bits 31-30, 27-25, 13, and 5 are reserved.
2
1
D
1
D
1
1 A
D
1
A’
D
2
1
D’ 2
CLKIN
ADS
A31:4, SUP,
CT3:0, D/C,
BE3:0, LOCK
Valid
Valid
Invalid
W/R
A3:2
D31:0,
DP3:0
Invalid
00
01
IN
D
10
IN
D
11
IN
D
Valid
IN
D
Invalid
IN
D’
WAIT
BLAST
DT/R
DEN
PCHK
1. Non-pipelined request concludes, pipelined reads begin.
2. Pipelined reads conclude, non-pipelined requests begin.
Datasheet
69
80960HA/HD/HT
Figure 45. Burst, Pipelined Read Request with Wait States, 8-Bit Bus
PMCON
Function
External
Ready
Control
Burst
PipeLining
Bus
Width
Odd
Parity
Parity
Enable
NXDA
NWDD
NWAD
NRDD
NRAD
Bit
29
28
24
23-22
21
20
19-16
15-14
12-8
7-6
4-0
Value
X
x
Enabled
1
ON
1
8-Bit
00
X
x
Enabled
1
X
xxxx
X
xx
X
xxxxx
1
01
2
00010
NOTE: Bits 31-30, 27-25, 13, and 5 are reserved.
2
1
D
1
D
1
D
1 A
1
A’
D
2
1
D’ 2
CLKIN
ADS
A31:4, SUP,
CT3:0, D/C,
LOCK
Valid
Valid
Invalid
W/R
A3:2
BE1/A1,
BE0/A0
D31:0,
DP3:0
Invalid
A3:2 = 00, 01, 10, or 11
A1:0 = 00
Valid
A1:0 = 01
A1:0 = 10
A1:0 = 11
D7:0
Byte 0
D7:0
Byte 1
D7:0
Byte 2
Valid
D7:0
Byte 3
Invalid
Invalid
D7:0
D’
WAIT
BLAST
DT/R
DEN
PCHK
1. Non-pipelined request concludes, pipelined reads begin
2. Pipelined reads conclude, non-pipelined requests begin
70
Datasheet
80960HA/HD/HT
Figure 46. Burst, Pipelined Read Request with Wait States, 16-Bit Bus
PMCON
External
Ready
Control
Burst
PipeLining
Bus
Width
Odd
Parity
Parity
Enable
NXDA
NWDD
NWAD
NRDD
NRAD
Bit
29
28
24
23-22
21
20
19-16
15-14
12-8
7-6
4-0
Value
X
x
Enabled
1
ON
1
16-Bit
01
X
x
Enabled
1
X
xxxx
X
xx
X
xxxxx
1
01
2
00010
Function
NOTE: Bits 31-30, 27-25, 13, and 5 are reserved.
1
A
2
1
D
1
D
1
D
1
A’
D
2
2
1
D’
CLKIN
ADS
A31:4, SUP,
CT3:0, D/C,
BE0/BLC,
BE3/BHE,
LOCK
W/R
A3:2
Valid
Valid
Invalid
A3:2 = 00 or 10
A3:2 = 01 or 11
BE1/A1
D31:0,
DP3:0
Invalid
D15:0
A1=0
D15:0
A1=1
D15:0
A1=0
D15:0
A1=1
Valid
Invalid
Valid
Invalid
D15:0
D’
WAIT
BLAST
DT/R
DEN
PCHK
1. Non-pipelined request concludes, pipelined reads begin
2. Pipelined reads conclude, non-pipelined requests begin
Datasheet
71
80960HA/HD/HT
Figure 47. Using External READY
Quad-Word Read Request
NRAD = 0, NRDD = 0, NXDA = 0
Ready Enabled
A 1
D
D
D
D
A
1
Quad-Word Write Request
NWAD = 1, NWDD = 0, NWDA = 0
Ready Enabled
2
D
1
D
1
D
1
D
CLKIN
ADS
A31:4, SUP,
CT3:0, D/C,
BE3:0, LOCK
Valid
Valid
W/R
BLAST
DT/R
DEN
READY
BTERM
A3:2
00
01
10
11
00
01
10
11
D1
D2
D3
WAIT
D31:0,
DP3:0
D0
D1
D2
D3
D0
PCHK
NOTE: Pipelining must be disabled to use READY.
72
Datasheet
80960HA/HD/HT
Figure 48. Terminating a Burst with BTERM
A
D
Quad-Word Read Request
NRAD = 0, NRDD = 0, NRDA = 0
Ready Enabled
A
D
1
A
D
1
1
D
1
CLKIN
ADS
A31:4, SUP,
CT3:0, D/C,
BE3:0, LOCK
Valid
W/R
BLAST
DT/R
DEN
READY
See Note
BTERM
A3:2
00
01
10
11
WAIT
D31:0,
DP3:0
D0
D1
D2
D3
PCHK
Note: READY adds memory access time to data transfers, whether or not the
bus access is a burst access. BTERM interrupts a bus access, whether or not
the bus access has more data transfers pending. Either the READY signal or
the BTERM signal terminates a bus access when the signal is asserted during
the last (or only) data transfer of the bus access.
Datasheet
73
80960HA/HD/HT
Figure 49. BREQ and BSTALL Operation
CLKIN
ADS
BLAST
BREQ
BSTALL
The processor may stall (BSTALL asserted) even with an empty bus queue (BREQ deasserted).
Depending on the instruction stream and memory wait states, the two signals may be separated by
several CLKIN cycles.
Bus arbitration logic that logically ‘ANDs’ BSTALL and BREQ will not correctly grant the bus to
the processor in all stall cases, potentially degrading processor performance.
Do not logically ‘AND’ BSTALL and BREQ together in arbitration logic. Instead, the simplest bus
arbitration should logically “OR” BSTALL and BREQ to determine the processor’s bus ownership
requirements.
More sophisticated arbitration should recognize the priority nature of these two signals. Using a
traffic light analogy, BREQ is a ‘yellow light’ warning of a possible processor stall and BSTALL is
a ‘red light’ indicating a stall in progress.
74
Datasheet
80960HA/HD/HT
Figure 50. BOFF Functional Timing. BOFF occurs during a burst or non-burst data cycle.
A
BOFF Mode
D
A
CLKIN
ADS
∼
∼
∼
∼
∼
∼
Regenerate ADS
Non-Burst
May Change
DP3:0 & D31:0,
(WRITES)
Valid
Resume Request
∼
∼
∼ ∼
∼ ∼
∼ ∼
∼ ∼
DEN, DT/R
∼
∼
∼ ∼
CT3:0, D/C,
BE3:0, WAIT,
∼
∼
A31:2, SUP,
∼
∼
∼
∼ ∼
∼
∼ ∼
∼ ∼
∼ ∼
Suspend Request
∼
∼
∼
∼
READY
BOFF
∼
∼ ∼
∼ ∼
∼
∼
∼
BLAST
∼
∼
∼ ∼
∼
∼
∼ ∼
∼ ∼
Burst
Valid
PCHK
Begin Request
BOFF may be asserted to suspend request
BOFF may not
be asserted
End Request
BOFF may not
be asserted
Note: READY/BTERM must be enabled; NRAD, NRDD, NWAD, NWDD= 0
Datasheet
75
80960HA/HD/HT
Figure 51. HOLD Functional Timing
Word Read Request
NRAD=1, NXDA=1
Hold State
Word Read
Request
NRAD=0,
NXDA=0
Hold State
CLKIN
ADS
A31:2, SUP,
CT3:0, D/C,
BE3:0, WAIT,
DEN, DT/R
Valid
Valid
BLAST
LOCK
HOLD
HOLDA
76
Datasheet
80960HA/HD/HT
Figure 52. LOCK Delays HOLDA Timing
CLKIN
ADS
W/R
BLAST
LOCK
HOLD
HOLDA
~
~
~
~
Figure 53. FAIL Functional Timing
RESET
(Bus Test)
Pass
Datasheet
~
~
FAIL
~
~
(Internal Self-Test)
Pass
80960HA:
257,517 Cycles
Fail
30 Cycles
113 Cycles
80960HD:
128,761 Cycles
15 Cycles
94 Cycles
80960HT:
85,840 Cycles
10 Cycles
90 Cycles
Fail
77
80960HA/HD/HT
Figure 54. A Summary of Aligned and Unaligned Transfers for 32-Bit Regions
0
4
8
12
16
20
24
Word Offset 0
1
2
3
4
5
6
Byte Offset
Short Request (Aligned)
Short Requests (Unaligned)
Short-Word
Load/Store
Short Request (Aligned)
Byte, Byte Requests
Word Request (Aligned)
Trey, Byte, Requests
Word
Load/Store
Short, Short Requests
Byte, Trey, Requests
One Double-Word Burst (Aligned)
Trey, Byte, Trey, Byte, Requests
Short, Short, Short, Short Requests
Double-Word
Load/Store
Byte, Trey, Byte, Trey, Requests
Word, Word Requests
One Double-Word
Request (Aligned)
NOTES:
1. All requests that are less than a word in size and are cacheable will be promoted to a word to be cached. This causes
adjacent requests to occur for full words to the same address.
78
Datasheet
80960HA/HD/HT
Figure 55. A Summary of Aligned and Unaligned Transfers for 32-Bit Regions (Continued)
0
4
8
12
16
20
24
1
2
3
4
5
6
Byte Offset
Word Offset
0
One Three-Word
Request (Aligned)
Trey, Byte, Trey, Byte,
Trey, Byte Requests
Triple-Word
Load/Store
Short, Short, Short, Short
Short, Short, Short Requests
Byte, Trey, Byte, Trey, Byte, Trey Requests
Word, Word,
Word Requests
Word, Word,
Word Requests
Word,
Word,
Word
Requests
One Four-Word
Request (Aligned)
Trey, Byte, Trey, Byte, Trey, Byte
Trey, Byte Requests
Quad-Word
Load/Store
8 Short Requests
Byte, Trey, Byte, Trey,
Byte, Trey, Byte, Trey, Requests
4 Word
Requests
4 Word
Requests
NOTES:
1. All requests that are less than a word in size and are cacheable will be promoted to a word to be cached. This causes
adjacent requests to occur for full words to the same address.
Datasheet
79
80960HA/HD/HT
Figure 56. A Summary of Aligned and Unaligned Transfers for 16-Bit Bus
Byte Offset 0
4
8
12
16
20
24
Word Offset 0
1
2
3
4
5
6
Short
Short
16-Bit Bus
Byte, Byte
Short
Byte, Byte
Two Short Burst
Byte, Short, Byte
Word
16-Bit Bus
(Short)*2
Byte, Short, Byte
Two Short Burst
Four Short Burst
(Byte, Short, Byte) *2
Double Word
16-Bit Bus
(Short) *4
(Byte, Short, Byte)*2
(Two Short Burst)*2
Four Short Burst
Four Short Burst, Two Short Burst
(Byte, Short, Byte) *3
Triple Word
16-Bit Bus
(Short) *6
(Byte, Short, Byte) *3
(Two Short Burst) *3
(Two Short Burst) *3
(Four Short Burst)*2
(Byte, Short, Byte) *4
Quad Word
16-Bit Bus
(Short) *8
(Byte, Short, Byte) *4
(Two Short Burst)*4
(Two Short Burst) *4
80
Datasheet
80960HA/HD/HT
Figure 57. A Summary of Aligned and Unaligned Transfers for 8-Bit Bus
Byte Offset 0
Word Offset 0
4
8
12
16
20
24
1
2
3
4
5
6
Two Byte Burst
Short
8-Bit Bus
Two Byte Burst
Two Byte Burst
Byte, Byte
Four Byte Burst
Three Byte Burst, Byte
Word
8-Bit Bus
(Two Byte Burst)*2
Byte, Three Byte Burst
Four Byte Burst
(Four Byte Burst) *2
(Three Byte Burst, Byte)*2
Double Word
8-Bit Bus
(Two Byte Burst) *4
(Byte, Three Byte Burst) *2
(Four Byte Burst) *2
(Four Byte Burst) *2
(Four Byte Burst)*3
(Three Byte Burst, Byte)*3
Triple Word
8-Bit Bus
(Two Byte Burst) *6
(Byte, Three Byte Burst) *3
(Four Byte Burst)*3
(Four Byte Burst)*3
(Four Byte Burst)*4
(Three Byte Burst, Byte)*4
Quad Word
16-Bit Bus
(Two Byte Burst) *8
(Byte, Three Byte Burst) *4
(Four Byte Burst)*4
(Four Byte Burst) *4
Datasheet
81
80960HA/HD/HT
Figure 58. Idle Bus Operation
Write Request
NWAD=2, NXDA = 0
Ready Disabled
Idle Bus
(not in Hold Acknowledge state)
Read Request
NRAD=2, NXDA = 0
Ready Disabled
CLKIN
ADS
A31:4, SUP, D/C,
BE3:0, CT3:0
LOCK
Valid
Valid
Valid
Valid
W/R
BLAST
DT/R
DEN
A3:2
Valid
Valid
WAIT
D31:0
Out
In
READY,
BTERM
PCHK
82
Datasheet
80960HA/HD/HT
Figure 59. Bus States
Tb
BOFF
WdCNT > 1
BOFF
BOFF
WdCNT = 1
!BOFF and READY and !BLAST or
!BOFF
!BOFF and BTERM and !BLAST or !BOFF and
!HOLD and BLAST and REQUEST and NXDA = 0
READ and Nrdd > 0 or
WRITE and Nwdd > 0
Ta
Td1
!BOFF and READ and Nrad = 0 or
!BOFF and WRITE and Nwad = 0
!RESET and
!HOLD and
REQUEST
READ and Nrad > 0 or
WRITE and Nwad > 0
Taw2
!BOFF and READ and Nrdd = 0
and !BLAST or !BOFF and
WRITE and Nwdd = 0 and !BLAST or
READY!
!BOFF and
BLAST and
Nxda > 0
WaCNT = 1
Trw4
WaCNT > 1
WxCNT > 1
!BOFF and !HOLD and
BLAST and Nxda = 0
!HOLD and WxCNT=1
and REQUEST
and !REQUEST
To
RESET and
!ONCE
ONCE and
RESET
WxCNT=1 and
HOLD
!HOLD and WxCNT=1
and !REQUEST
HOLD
Ti
HOLD
!HOLD
RESET
Tdw3
Th
!BOFF and
HOLD and BLAST
and Nxda= 0
KEY:
To = ONCE
Ti = IDLE
Th = HOLD
Ta = ADDRESS
Td = DATA
Tb = BOFF’ed
Taw= address to data wait
Tdw= data to data wait
Tdw= data to address wait
REQUEST= One or more
requests in the bus queue.
READ= The current
access is a read.
WRITE= The current
access is a write.
NOTES:
1. When the PMCON for the region has External Ready Control enabled, wait states are inserted as long
as READY and BTERM are de-asserted. When Read Pipelining is enabled, the Ta state of the
subsequent read access is concurrent with the last data cycle of the access. Because External Ready
Control is disabled for Read Pipelining, the address cycle occurs during BLAST.
2. WaCNT is decremented during Taw.
3. WdCNT is decremented during Tdw.
4. WxCNT is decremented during Trw.
Datasheet
83
80960HA/HD/HT
5.1
80960Hx Boundary Scan Chain
Table 26. 80960Hx Boundary Scan Chain (Sheet 1 of 4)
#
Boundary Scan Cell
Cell Type
DP3
Bidirectional
DP2
Bidirectional
DP0
Bidirectional
DP1
Bidirectional
STEST
Input
FAILBAR
Output
Enable for FAILBAR, BSTALL and
BREQ
Control
ONCEBAR
Input
BOFFBAR
Input
D0
Bidirectional
D1
Bidirectional
D2
Bidirectional
D3
Bidirectional
D4
Bidirectional
D5
Bidirectional
D6
Bidirectional
D7
Bidirectional
Enable for DP(3:0) and D(31:0)
Control
D8
Bidirectional
D9
Bidirectional
D10
Bidirectional
D11
Bidirectional
D12
Bidirectional
D13
Bidirectional
D14
Bidirectional
D15
Bidirectional
D16
Bidirectional
D17
Bidirectional
D18
Bidirectional
D19
Bidirectional
D20
Bidirectional
Comment
NOTES:
1. Cell#1 connects to TDO and cell #112 connects to TDI.
2. All outputs are tri-state.
3. In output and bidirectional signals, a logical 1 on the enable signal enables the output. A logical 0
tri-states the output.
84
Datasheet
80960HA/HD/HT
Table 26. 80960Hx Boundary Scan Chain (Sheet 2 of 4)
#
Boundary Scan Cell
Cell Type
D21
Bidirectional
D22
Bidirectional
D23
Bidirectional
D24
Bidirectional
D25
Bidirectional
D26
Bidirectional
D27
Bidirectional
D28
Bidirectional
D29
Bidirectional
D30
Bidirectional
D31
Bidirectional
BTERMBAR
Input
RDYBAR
Input
HOLD
Input
HOLDA
Output
Enable for HOLDA control
Control
ADSBAR
Output
BE3BAR
Output
BE2BAR
Output
BE1BAR
Output
BE0BAR
Output
BLASTBAR
Output
DENBAR
Output
Comment
Appears as READYBAR in BSDL
file.
Appears as BEBAR(3:0) in BSDL
file.
WRRDBAR
Output
DTRBAR
Output
Appears as WRBAR in BSDL file.
Enable for DTRBAR
Control
WAITBAR
Output
BSTALL
Output
DATACODBAR
Output
Appears as DCBAR in BSDL file.
USERSUPBAR
Output
Appears as SUPBAR in BSDL file.
Enable for ADSBAR, BEBAR,
BLASTBAR, DENBAR, WRRDBAR,
WAITBAR, DCBAR, SUPBAR and
LOCKBAR,
Control
NOTES:
1. Cell#1 connects to TDO and cell #112 connects to TDI.
2. All outputs are tri-state.
3. In output and bidirectional signals, a logical 1 on the enable signal enables the output. A logical 0
tri-states the output.
Datasheet
85
80960HA/HD/HT
Table 26. 80960Hx Boundary Scan Chain (Sheet 3 of 4)
#
Boundary Scan Cell
Cell Type
LOCKBAR
Output
BREQ
Output
A31
Output
A30
Output
A29
Output
A28
Output
A27
Output
A26
Output
A25
Output
A24
Output
A23
Output
A22
Output
A21
Output
A20
Output
A19
Output
A18
Output
A17
Output
A16
Output
Enable for A(31:0) and CT(3:0)
Control
A15
Output
A14
Output
A13
Output
A12
Output
A11
Output
A10
Output
A9
Output
A8
Output
A7
Output
A6
Output
A5
Output
A4
Output
A3
Output
A2
Output
NMIBAR
Input
Comment
NOTES:
1. Cell#1 connects to TDO and cell #112 connects to TDI.
2. All outputs are tri-state.
3. In output and bidirectional signals, a logical 1 on the enable signal enables the output. A logical 0
tri-states the output.
86
Datasheet
80960HA/HD/HT
Table 26. 80960Hx Boundary Scan Chain (Sheet 4 of 4)
#
Boundary Scan Cell
Cell Type
XINT7BAR
Input
XINT6BAR
Input
XINT5BAR
Input
XINT4BAR
Input
XINT3BAR
Input
XINT2BAR
Input
XINT1BAR
Input
XINT0BAR
Input
RESETBAR
Input
CLKIN
Input
CT3
Output
CT2
Output
CT1
Output
CT0
Output
PCHK
Output
PCHK enable
Control
Comment
Appears as XINTBAR(7:0) in
BSDL file.
Appears as CT(3:0) in BSDL file.
Appears as PCHKBAR in BSDL
file.
NOTES:
1. Cell#1 connects to TDO and cell #112 connects to TDI.
2. All outputs are tri-state.
3. In output and bidirectional signals, a logical 1 on the enable signal enables the output. A logical 0
tri-states the output.
Datasheet
87
80960HA/HD/HT
5.2
Boundary Scan Description Language Example
The Boundary-Scan Description Language (BSDL) for PGA Package Example, as shown in
Example 1, meets the de-facto standard means of describing essential features of ANSI/IEEE
1149.1-1993 compliant devices.
The Boundary-Scan Description Language (BSDL) for PQ2 Package Example is shown in
Example 2 on page 96.
Example 1. Boundary-Scan Description Language (BSDL) for PGA
Package Example (Sheet 1 of 8)
-- Copyright Intel Corp. 1995
- - ***************************************************************************
- - Intel Corporation makes no warranty for the use of its products and assumes no
responsibility for any errors which may appear in this document nor does it make
a commitment to update the information contained herein.
- - ***************************************************************************
- - Boundary-Scan Description Language (BSDL Version 0.0) is a de-facto standard
means of describing essential features of ANSI/IEEE 1149.1-1990 compliant
devices. This language is under consideration by the IEEE for formal inclusion
within a supplement to the 1149.1-1990 standard. The generation of the supplement
entails an extensive IEEE review and a formal acceptance balloting procedure
which may change the resultant form of the language. Be aware that this process
may extend well into 1993, and at this time the IEEE does not endorse or hold an
opinion on the language.
- - ***************************************************************************
--- i960(R) Processor BSDL Model
88
Datasheet
80960HA/HD/HT
Example 1. Boundary-Scan Description Language (BSDL) for PGA
Package Example (Sheet 2 of 8)
-- Project code HA
-- File **NOT** verified electrically
-- ------------------------------------------------- Rev 0.7
18 Dec
1995
-- Rev 0.6
08 Dec
1994
-- Rev 0.5
21 Nov
1994
-- Rev 0.4
31 Oct
1994
-- Rev 0.3
26 July 1994
-- Rev 0.2
22 June 1994
-- Rev 0.1
16 Mar
1994
-- Rev 0.0
30 Aug
1993
Updated for A-1 stepping.
entity Ha_Processor is
generic(PHYSICAL_PIN_MAP : string:= “PGA”);
port (A
Datasheet
: out
bit_vector(2 to 31);
ADSBAR
: out
bit;
BEBAR
: out
bit_vector(0 to 3);
BLASTBAR
: out
bit;
BOFFBAR
: in
bit;
BREQ
: out
bit;
BSTALL
: out
bit;
BTERMBAR
: in
bit;
CT
: out
bit_vector(0 to 3);
CLKIN
: in
bit;
D
: inout
bit_vector(0 to 31);
DENBAR
: out
bit;
DP
: inout
bit_vector(0 to 3);
DTRBAR
: out
bit;
DCBAR
: out
bit;
FAILBAR
: out
bit;
HOLD
: in
bit;
HOLDA
: out
bit;
LOCKBAR
: out
bit;
NMIBAR
: in
bit;
ONCEBAR
: in
bit;
PCHKBAR
: out
bit;
READYBAR
: in
bit;
RESETBAR
: in
bit;
STEST
: in
bit;
89
80960HA/HD/HT
Example 1. Boundary-Scan Description Language (BSDL) for PGA
Package Example (Sheet 3 of 8)
SUPBAR
: out
bit;
TCK
: in
bit;
TDI
: in
bit;
TDO
: out
bit;
TMS
: in
bit;
TRST
: in
bit;
WAITBAR
: out
bit;
WRBAR
: out
bit;
XINTBAR
: in
bit_vector(0 to 7);
FIVEVREF
: linkage bit;
VCCPLL
: linkage bit;
VOLTDET
: out
VCC1
: linkage bit_vector(0 to 23);
VCC2
: linkage bit_vector(0 to 20);
VSS1
: linkage bit_vector(0 to 25);
VSS2
: linkage bit_vector(0 to 22);
NC
: linkage bit_vector(0 to 4)
bit;
);
use STD_1149_1_1990.all;
use i960ha_a.all;
attribute PIN_MAP of Ha_Processor : entity is PHYSICAL_PIN_MAP;
constant PGA:PIN_MAP_STRING :=
“A
“
K17, L17, L16, M17, N17, N16, P17, Q17, P16,”&
“
P15, Q16, R17, R16, Q15, S17, R15, S16, Q14, ”&
“
90
: (D16, D17, E16, E17, F17, G16, G17, H17, J17,”&
R14, Q13, S15),
“ADSBAR
: R06,”&
“BEBAR
: (R09, S07, S06, S05),”&
“BLASTBAR
: S08,”&
“BOFFBAR
: B01,”&
“BREQ
: R13,”&
“BSTALL
: R12,”&
“BTERMBAR
: R04,”&
“CT
: (A11, A12, A13, A14),”&
“CLKIN
: C13,”&
Datasheet
80960HA/HD/HT
Example 1. Boundary-Scan Description Language (BSDL) for PGA
Package Example (Sheet 4 of 8)
“D
“
G01, H02, H01, J01, K01, L02, L01, M01, N01,”&
“
N02, P01, P02, Q01, P03, Q02, R01, S01, Q03,”&
“
R02, Q04, S02, Q05, R03),”&
“DENBAR
: S09,”&
“DP
: (A03, B03, A04, B04),”&
“DTRBAR
: S11,”&
“DCBAR
: S13,”&
“FAILBAR
: A02,”&
“HOLD
: R05,”&
“HOLDA
: S04,”&
“LOCKBAR
: S14,”&
“NMIBAR
: D15,”&
“ONCEBAR
: C03,”&
“PCHKBAR
: B08,”&
“READYBAR
: S03,”&
“RESETBAR
: A16,”&
“STEST
: B02,”&
“SUPBAR
: Q12,”&
“TCK
: B05,”&
“TDI
: A07,”&
“TDO
: A08,”&
“TMS
: B06,”&
“TRST
: A06,”&
“WAITBAR
: S12,”&
“WRBAR
: S10,”&
“ XINTBAR
: (B15, A15, A17, B16, C15, B17, C16, C17),”&
“FIVEVREF
: C05,”&
“VOLTDET
: A05,”&
“VCCPLL
: B10,”&
“ VCC1
“
“
“ VSS1
“
“
“NC
Datasheet
: (E03, C02, D02, C01, E02, D01, F02, E01, F01,”&
: (M02, K02, J02, G02, N03, F03, C06, B07, B09, B11,”&
B12, C14, E15, F16, H16, J16, K16, M16, N15, Q06,”&
R07, R08, R10, R11),”&
: (G03, H03, J03, K03, L03, M03, C07, C08, C09, C10,”&
C11, C12, Q07, Q08, Q09, Q10, Q11, F15, G15, H15,”&
J15, K15, L15, M15, A01, C04),”&
: (A09, A10, B13, B14, D03)”;
91
80960HA/HD/HT
Example 1. Boundary-Scan Description Language (BSDL) for PGA
Package Example (Sheet 5 of 8)
attribute Tap_Scan_In
of
TDI
: signal is true;
attribute Tap_Scan_Mode
of
TMS
: signal is true;
attribute Tap_Scan_Out
of
TDO
: signal is true;
attribute Tap_Scan_Reset of
TRST
: signal is true;
attribute Tap_Scan_Clock of
TCK
: signal is (66.0e6, BOTH);
attribute Instruction_Length of Ha_Processor: entity is 4;
attribute Instruction_Opcode of Ha_Processor: entity is
“BYPASS
(1111),” &
“EXTEST
(0000),” &
“SAMPLE
(0001),” &
“IDCODE
(0010),” &
“RUBIST
(0111),” &
“CLAMP
(0100),” &
“HIGHZ
(1000),” &
“Reserved
(1011, 1100)”;
attribute Instruction_Capture of Ha_Processor: entity is “0001”;
attribute Instruction_Private of Ha_Processor: entity is “Reserved” ;
attribute Idcode_Register of Ha_Processor: entity is
“0010”
&
--version,
“1000100001000000”
&
--part number
“00000001001”
&
--manufacturers identity
“1”;
--required by the standard
attribute Register_Access of Ha_Processor: entity is
“Runbist[32]
(RUBIST),” &
“Bypass
(CLAMP, HIGHZ)”;
{***************************************************************************}
{
The first cell, cell 0, is closest to TDO
}
{
BC_1:Control, Output3
}
CBSC_1:Bidir
BC_4: Input, Clock
{***************************************************************************}
92
Datasheet
80960HA/HD/HT
Example 1. Boundary-Scan Description Language (BSDL) for PGA
Package Example (Sheet 6 of 8)
attribute Boundary_Cells of Ha_Processor: entity is “BC_4, BC_1, CBSC_1”;
attribute Boundary_Length of Ha_Processor: entity is 112;
attribute Boundary_Register of Ha_Processor: entity is
Datasheet
“0
(CBSC_1,
DP(3),
bidir,
X,
17, 1,
Z),”
&
“1
(CBSC_1,
DP(2),
bidir,
X,
17, 1,
Z),”
&
“2
(CBSC_1,
DP(0),
bidir,
X,
17, 1,
Z),”
&
17, 1,
Z),”
&
Z),”
&
“3
(CBSC_1,
DP(1),
bidir,
X,
“4
(BC_4,
STEST,
input,
X),”
“5
(BC_1,
FAILBAR,
output3, X,
“6
(BC_1,
*,
control, 1),”
&
“7
(BC_4,
ONCEBAR,
input,
X),”
&
“8
(BC_4,
BOFFBAR,
input,
X),”
&
“9
(CBSC_1,
D(0),
bidir,
X,
17,
1,
Z),”
&
“10 (CBSC_1,
D(1),
bidir,
X,
17,
1,
Z),”
&
&
6,
1,
“11 (CBSC_1,
D(2),
bidir,
X,
17,
1,
Z),”
&
“12 (CBSC_1,
D(3),
bidir,
X,
17,
1,
Z),”
&
“13 (CBSC_1,
D(4),
bidir,
X,
17,
1,
Z),”
&
“14 (CBSC_1,
D(5),
bidir,
X,
17,
1,
Z),”
&
“15 (CBSC_1,
D(6),
bidir,
X,
17,
1,
Z),”
&
“16 (CBSC_1,
D(7),
bidir,
X,
17,
1,
Z),”
&
“17 (BC_1,
*,
control, 1),”
“18 (CBSC_1,
D(8),
bidir,
X,
17,
1,
Z),”
&
“19 (CBSC_1,
D(9),
bidir,
X,
17,
1,
Z),”
&
&
“20 (CBSC_1,
D(10),
bidir,
X,
17,
1,
Z),”
&
“21 (CBSC_1,
D(11),
bidir,
X,
17,
1,
Z),”
&
“22 (CBSC_1,
D(12),
bidir,
X,
17,
1,
Z),”
&
“23 (CBSC_1,
D(13),
bidir,
X,
17,
1,
Z),”
&
“24 (CBSC_1,
D(14),
bidir,
X,
17,
1,
Z),”
&
“25 (CBSC_1,
D(15),
bidir,
X,
17,
1,
Z),”
&
“26 (CBSC_1,
D(16),
bidir,
X,
17,
1,
Z),”
&
“27 (CBSC_1,
D(17),
bidir,
X,
17,
1,
Z),”
&
“28 (CBSC_1,
D(18),
bidir,
X,
17,
1,
Z),”
&
“29 (CBSC_1,
D(19),
bidir,
X,
17,
1,
Z),”
&
“30 (CBSC_1,
D(20),
bidir,
X,
17,
1,
Z),”
&
“31 (CBSC_1,
D(21),
bidir,
X,
17,
1,
Z),”
&
“32 (CBSC_1,
D(22),
bidir,
X,
17,
1,
Z),”
&
“33 (CBSC_1,
D(23),
bidir,
X,
17,
1,
Z),”
&
“34 (CBSC_1,
D(24),
bidir,
X,
17, 1,
Z),”
&
93
80960HA/HD/HT
Example 1. Boundary-Scan Description Language (BSDL) for PGA
Package Example (Sheet 7 of 8)
94
“35 (CBSC_1,
D(25),
bidir,
X,
17, 1,
Z),”
&
“36 (CBSC_1,
D(26),
bidir,
X,
17, 1,
Z),”
&
“37 (CBSC_1,
D(27),
bidir,
X,
17, 1,
Z),”
&
“38 (CBSC_1,
D(28),
bidir,
X,
17, 1,
Z),”
&
“39 (CBSC_1,
D(29),
bidir,
X,
17, 1,
Z),”
&
“40 (CBSC_1,
D(30),
bidir,
X,
17, 1,
Z),”
&
“41 (CBSC_1,
D(31),
bidir,
X,
17, 1,
Z),”
&
“42 (BC_4,
BTERMBAR,
input,
X),”
&
“43 (BC_4,
READYBAR,
input,
X),”
&
“44 (BC_4,
HOLD,
input,
X),”
&
“45 (BC_1,
HOLDA,
output3, X,
Z),”
&
“46 (BC_1,
*,
control, 1),”
“47 (BC_1,
ADSBAR,
output3, X,
61, 1,
Z),”
&
“48 (BC_1,
BEBAR(3),
output3, X,
61, 1,
Z),”
&
“49 (BC_1,
BEBAR(2),
output3, X,
61, 1,
Z),”
&
“50 (BC_1,
BEBAR(1),
output3, X,
61, 1,
Z),”
&
“51 (BC_1,
BEBAR(0),
output3, X,
61, 1,
Z),”
&
“52 (BC_1,
BLASTBAR,
output3, X,
61, 1,
Z),”
&
“53 (BC_1,
DENBAR,
output3, X,
61, 1,
Z),”
&
“54 (BC_1,
WRBAR,
output3, X,
61, 1,
Z),”
&
“55 (BC_1,
DTRBAR,
output3, X,
56, 1,
Z),”
&
“56 (BC_1,
*,
control, 1),”
“57 (BC_1,
WAITBAR,
output3, X,
61, 1,
Z),”
&
“58 (BC_1,
BSTALL,
output3, X,
6,
1,
Z),”
&
“59 (BC_1,
DCBAR,
output3, X,
61, 1,
Z),”
&
“60 (BC_1,
SUPBAR,
output3, X,
61, 1,
Z),”
&
“61 (BC_1,
*,
control, 1),”
“62 (BC_1,
LOCKBAR,
output3, X,
61, 1,
Z),”
&
“63 (BC_1,
BREQ,
output3, X,
6,
1,
Z),”
&
“64 (BC_1,
A(31),
output3, X,
80, 1,
Z),”
&
“65 (BC_1,
A(30),
output3, X,
80, 1,
Z),”
&
“66 (BC_1,
A(29),
output3, X,
80, 1,
Z),”
&
“67 (BC_1,
A(28),
output3, X,
80, 1,
Z),”
&
“68 (BC_1,
A(27),
output3, X,
80, 1,
Z),”
&
“69 (BC_1,
A(26),
output3, X,
80, 1,
Z),”
&
“70 (BC_1,
A(25),
output3, X,
80, 1,
Z),”
&
“71 (BC_1,
A(24),
output3, X,
80, 1,
Z),”
&
46, 1,
&
&
&
“72 (BC_1,
A(23),
output3,
X,
80, 1,
Z),”
&
“73 (BC_1,
A(22),
output3,
X,
80, 1,
Z),”
&
Datasheet
80960HA/HD/HT
Example 1. Boundary-Scan Description Language (BSDL) for PGA
Package Example (Sheet 8 of 8)
“74 (BC_1,
A(21),
output3,
X,
80, 1,
Z),”
&
“75 (BC_1,
A(20),
output3,
X,
80, 1,
Z),”
&
“76 (BC_1,
A(19),
output3,
X,
80, 1,
Z),”
&
“77 (BC_1,
A(18),
output3,
X,
80, 1,
Z),”
&
“78 (BC_1,
A(17),
output3,
X,
80, 1,
Z),”
&
“79 (BC_1,
A(16),
output3,
X,
80, 1,
Z),”
&
“80 (BC_1,
*,
control,
1),”
&
“81 (BC_1,
A(15),
output3,
X,
80, 1,
Z),”
&
“82 (BC_1,
A(14),
output3,
X,
80, 1,
Z),”
&
“83 (BC_1,
A(13),
output3,
X,
80, 1,
Z),”
&
“84 (BC_1,
A(12),
output3,
X,
80, 1,
Z),”
&
“85 (BC_1,
A(11),
output3,
X,
80, 1,
Z),”
&
“86 (BC_1,
A(10),
output3,
X,
80, 1,
Z),”
&
“87 (BC_1,
A(9),
output3,
X,
80, 1,
Z),”
&
“88 (BC_1,
A(8),
output3,
X,
80, 1,
Z),”
&
“89 (BC_1,
A(7),
output3,
X,
80, 1,
Z),”
&
“90 (BC_1,
A(6),
output3,
X,
80, 1,
Z),”
&
“91 (BC_1,
A(5),
output3,
X,
80, 1,
Z),”
&
“92 (BC_1,
A(4),
output3,
X,
80, 1,
Z),”
&
“93 (BC_1,
A(3),
output3,
X,
80, 1,
Z),”
&
“94 (BC_1,
A(2),
output3,
X,
80, 1,
Z),”
&
“95 (BC_4,
NMIBAR,
input,
X),”
&
“96 (BC_4,
XINTBAR(7),
input,
X),”
&
“97 (BC_4,
XINTBAR(6),
input,
X),”
&
“98 (BC_4,
XINTBAR(5),
input,
X),”
&
“99 (BC_4,
XINTBAR(4),
input,
X),”
&
“100(BC_4,
XINTBAR(3),
input,
X),”
&
“101(BC_4,
XINTBAR(2),
input,
X),”
&
“102(BC_4,
XINTBAR(1),
input,
X),”
&
“103(BC_4,
XINTBAR(0),
input,
X),”
&
“104(BC_4,
RESETBAR,
input,
X),”
&
“105(BC_4,
CLKIN,
input,
X),”
&
“106(BC_1,
CT(3),
output3,
X,
Z),”
&
“107(BC_1,
CT(2),
output3,
X,
80, 1,
80, 1, Z),”
&
“108(BC_1,
CT(1),
output3,
X,
80, 1, Z),”
&
“109(BC_1,
CT(0),
output3,
X,
80, 1, Z),”
&
“110(BC_1,
PCHKBAR,
output3,
X,
111, 1, Z),”
&
“111(BC_1,
*,
control,
1)”;
end Ha_Processor;
Datasheet
95
80960HA/HD/HT
Example 2. Boundary-Scan Description Language (BSDL) for PQ2
Package Example (Sheet 1 of 8)
-- Copyright Intel Corporation 1995, 1996
-- *****************************************************************************
-- Intel Corporation makes no warranty for the use of its products and assumes no
responsibility for any errors which may appear in this document nor does it make
a commitment to update the information contained herein.
-- *****************************************************************************
-- Boundary-Scan Description Language (BSDL Version 0.0) is a de-facto
-- standard means of describing essential features of ANSI/IEEE 1149.1-1990
compliant devices. This language is under consideration by the IEEE for formal
inclusion within a supplement to the 1149.1-1990 standard. The generation of the
supplement entails an extensive IEEE review and a formal acceptance balloting
procedure which may change the resultant form of the language. Be aware that this
process may extend well into 1993, and at this time the IEEE does not endorse or
hold an opinion on the language.
-- i960(R) Processor BSDL Model
-- Project code HA
-- File **NOT** verified electrically
-- -----------------------------------------------
96
-- Rev 0.8
4 Apr
1996
Changed for PQ2 Package
-- Rev 0.7
18 Dec
1995
Updated for A-1 stepping.
-- Rev 0.6
08 Dec
1994
-- Rev 0.5
21 Nov
1994
-- Rev 0.4
31 Oct
1994
-- Rev 0.3
26 July 1994
-- Rev 0.2
22 June 1994
-- Rev 0.1
16 Mar
1994
-- Rev 0.0
30 Aug
1993
Datasheet
80960HA/HD/HT
Example 2. Boundary-Scan Description Language (BSDL) for PQ2
Package Example (Sheet 2 of 8)
entity Ha_Processor is
generic(PHYSICAL_PIN_MAP : string:= “PQ2”);
port (A
Datasheet
: out
bit_vector(2 to 31);
ADSBAR
: out
bit;
BEBAR
: out
bit_vector(0 to 3);
BLASTBAR
: out
bit;
BOFFBAR
: in
bit;
BREQ
: out
bit;
BSTALL
: out
bit;
BTERMBAR
: in
bit;
CT
: out
bit_vector(0 to 3);
CLKIN
: in
bit;
D
: inout
bit_vector(0 to 31);
DENBAR
: out
bit;
DP
: inout
bit_vector(0 to 3);
DTRBAR
: out
bit;
DCBAR
: out
bit;
FAILBAR
: out
bit;
HOLD
: in
bit;
HOLDA
: out
bit;
LOCKBAR
: out
bit;
NMIBAR
: in
bit;
ONCEBAR
: in
bit;
PCHKBAR
: out
bit;
READYBAR
: in
bit;
RESETBAR
: in
bit;
STEST
: in
bit;
SUPBAR
: out
bit;
TCK
: in
bit;
TDI
: in
bit;
TDO
: out
bit;
TMS
: in
bit;
TRST
: in
bit;
WAITBAR
: out
bit;
WRBAR
: out
bit;
XINTBAR
: in
bit_vector(0 to 7);
FIVEVREF
: linkage bit;
VCCPLL
: linkage bit;
97
80960HA/HD/HT
Example 2. Boundary-Scan Description Language (BSDL) for PQ2
Package Example (Sheet 3 of 8)
VCC1
: linkage bit_vector(0 to 23);
VCC2
: linkage bit_vector(0 to 23);
VSS1
: linkage bit_vector(0 to 23);
VSS2
: linkage bit_vector(0 to 23)
);
use STD_1149_1_1990.all;
use i960ha_a.all;
attribute PIN_MAP of Ha_Processor : entity is PHYSICAL_PIN_MAP;
constant PQ2:PIN_MAP_STRING :=
“A
98
: (151, 150, 147, 146, 145, 144, 141, 140, 139, 138,”&
“
135, 134, 133, 132, 127, 126, 125, 124, 121, 120,”&
“
119, 118, 113, 112, 111, 110, 107, 106, 105, 104),”&
“ADSBAR
: 77,”&
“BEBAR
: (83, 82, 79, 78),”&
“BLASTBAR
: 84,”&
“BOFFBAR
: 10,”&
“BREQ
: 100,”&
“BSTALL
: 91,”&
“BTERMBAR
: 67,”&
“CT
: (183, 182, 181, 180),”&
“CLKIN
: 175,”&
“D
: (12, 13, 14, 15, 20, 21, 22, 23, 26, 27, 28, 29,”&
“
34, 35, 36, 37, 39, 40, 41, 42, 45, 50, 51, 52,”&
“
54, 55, 56, 57, 61, 62, 63, 64),”&
“DENBAR
: 85,”&
“DP
: (206, 207, 203, 202),”&
“DTRBAR
: 89,”&
“DCBAR
: 96,”&
“FAILBAR
: 5,”&
“HOLD
: 69,”&
“HOLDA
: 72,”&
“LOCKBAR
: 99,”&
“NMIBAR
: 159,”&
Datasheet
80960HA/HD/HT
Example 2. Boundary-Scan Description Language (BSDL) for PQ2
Package Example (Sheet 4 of 8)
“ONCEBAR
: 6,”&
“PCHKBAR
: 189,”&
“READYBAR
: 68,”&
“RESETBAR
: 174,”&
“STEST
: 208,”&
“SUPBAR
: 97,”&
“TCK
: 194,”&
“TDI
: 191,”&
“TDO
: 188,”&
“TMS
: 192,”&
“TRST
: 193,”&
“WAITBAR
: 90,”&
“WRBAR
: 88,”&
“XINTBAR
: (169, 168, 167, 166, 163, 162, 161, 160),”&
“FIVEVREF
: 197,”&
“VCCPLL
: 177,”&
“VCC1
: (1, 4, 9, 11, 17, 19, 25, 31, 33, 38, 44, 46,”&
“
“VCC2
“
“
“VSS1
“
“VSS2
49, 59, 60, 66, 71, 74, 76, 81, 87, 92, 95, 101),”&
: (102, 109, 115, 117, 123, 128, 131, 137, 143, 149,”&
153, 154, 158, 165, 171, 173, 176, 179, 185, 187,”&
196, 199, 201, 204),”&
: (2, 3, 7, 8, 16, 18, 24, 30, 32, 43, 47, 48,”&
53, 58, 65, 70, 73, 75, 80, 86, 93, 94, 98, 103),”&
: (108, 114, 116, 122, 129, 130, 136, 142, 148, 152,”&
“
155, 156, 157, 164, 170, 172, 178, 184, 186, 190,”&
“
195, 198, 200, 205)”;
attribute Tap_Scan_In
of
TDI
: signal is true;
attribute Tap_Scan_Mode
of
TMS
: signal is true;
attribute Tap_Scan_Out
of
TDO
: signal is true;
attribute Tap_Scan_Reset of
TRST
: signal is true;
attribute Tap_Scan_Clock of
TCK
: signal is (66.0e6, BOTH);
attribute Instruction_Length of Ha_Processor: entity is 4;
attribute Instruction_Opcode of Ha_Processor: entity is
Datasheet
99
80960HA/HD/HT
Example 2. Boundary-Scan Description Language (BSDL) for PQ2
Package Example (Sheet 5 of 8)
“BYPASS
(1111),” &
“EXTEST
(0000),” &
“SAMPLE
(0001),” &
“IDCODE
(0010),” &
“RUBIST
(0111),” &
“CLAMP
(0100),” &
“HIGHZ
(1000),” &
“Reserved
(1011, 1100)”;
attribute Instruction_Capture of Ha_Processor: entity is “0001”;
attribute Instruction_Private of Ha_Processor: entity is “Reserved” ;
attribute Idcode_Register of Ha_Processor: entity is
“0001” &
version,
“1000100001000000”
“00000001001”&
“1”;
&
part number
manufacturers identity
required by the standard
attribute Register_Access of Ha_Processor: entity is
“Runbist[32]
(RUBIST),” &
“Bypass
(CLAMP, HIGHZ)”;
*******************************************************************************
{
The first cell, cell 0, is closest to TDO
}
{
BC_1:Control, Output3
}
CBSC_1:Bidir
BC_4: Input, Clock
*******************************************************************************
attribute Boundary_Cells of Ha_Processor: entity is “BC_4, BC_1, CBSC_1”;
attribute Boundary_Length of Ha_Processor: entity is 112;
attribute Boundary_Register of Ha_Processor: entity is
100
“0
(CBSC_1,
DP(3),
bidir,
X,
17, 1,
Z),”
&
“1
(CBSC_1,
DP(2),
bidir,
X,
17, 1,
Z),”
&
“2
(CBSC_1,
DP(0),
bidir,
X,
17, 1,
Z),”
&
“3
(CBSC_1,
DP(1),
bidir,
X,
17, 1,
Z),”
&
“4
(BC_4,
STEST,
input,
X),”
“5
(BC_1,
FAILBAR,
output3, X,
Z),”
&
&
6,
1,
Datasheet
80960HA/HD/HT
Example 2. Boundary-Scan Description Language (BSDL) for PQ2
Package Example (Sheet 6 of 8)
Datasheet
“6
(BC_1,
*,
control, 1),”
&
“7
(BC_4,
ONCEBAR,
input,
X),”
&
“8
(BC_4,
BOFFBAR,
input,
X),”
&
“9
(CBSC_1,
D(0),
bidir,
X,
17,
1,
Z),”
&
“10 (CBSC_1,
D(1),
bidir,
X,
17,
1,
Z),”
&
“11 (CBSC_1,
D(2),
bidir,
X,
17,
1,
Z),”
&
“12 (CBSC_1,
D(3),
bidir,
X,
17,
1,
Z),”
&
“13 (CBSC_1,
D(4),
bidir,
X,
17,
1,
Z),”
&
“14 (CBSC_1,
D(5),
bidir,
X,
17,
1,
Z),”
&
“15 (CBSC_1,
D(6),
bidir,
X,
17,
1,
Z),”
&
“16 (CBSC_1,
D(7),
bidir,
X,
17,
1,
Z),”
&
“17 (BC_1,
*,
control, 1),”
&
“18 (CBSC_1,
D(8),
bidir,
X,
17,
1,
Z),”
&
“19 (CBSC_1,
D(9),
bidir,
X,
17,
1,
Z),”
&
“20 (CBSC_1,
D(10),
bidir,
X,
17,
1,
Z),”
&
“21 (CBSC_1,
D(11),
bidir,
X,
17,
1,
Z),”
&
“22 (CBSC_1,
D(12),
bidir,
X,
17,
1,
Z),”
&
“23 (CBSC_1,
D(13),
bidir,
X,
17,
1,
Z),”
&
“24 (CBSC_1,
D(14),
bidir,
X,
17,
1,
Z),”
&
“25 (CBSC_1,
D(15),
bidir,
X,
17,
1,
Z),”
&
“26 (CBSC_1,
D(16),
bidir,
X,
17,
1,
Z),”
&
“27 (CBSC_1,
D(17),
bidir,
X,
17,
1,
Z),”
&
“28 (CBSC_1,
D(18),
bidir,
X,
17,
1,
Z),”
&
“29 (CBSC_1,
D(19),
bidir,
X,
17,
1,
Z),”
&
“30 (CBSC_1,
D(20),
bidir,
X,
17,
1,
Z),”
&
“31 (CBSC_1,
D(21),
bidir,
X,
17,
1,
Z),”
&
“32 (CBSC_1,
D(22),
bidir,
X,
17,
1,
Z),”
&
“33 (CBSC_1,
D(23),
bidir,
X,
17,
1,
Z),”
&
“34 (CBSC_1,
D(24),
bidir,
X,
17,
1,
Z),”
&
“35 (CBSC_1,
D(25),
bidir,
X,
17,
1,
Z),”
&
“36 (CBSC_1,
D(26),
bidir,
X,
17,
1,
Z),”
&
“37 (CBSC_1,
D(27),
bidir,
X,
17,
1,
Z),”
&
“38 (CBSC_1,
D(28),
bidir,
X,
17,
1,
Z),”
&
“39 (CBSC_1,
D(29),
bidir,
X,
17,
1,
Z),”
&
“40 (CBSC_1,
D(30),
bidir,
X,
17,
1,
Z),”
&
101
80960HA/HD/HT
Example 2. Boundary-Scan Description Language (BSDL) for PQ2
Package Example (Sheet 7 of 8)
“41 (CBSC_1,
102
D(31),
bidir,
X,
17, 1,
Z),”
&
Z),”
&
“42 (BC_4,
BTERMBAR,
input,
X),”
&
“43 (BC_4,
READYBAR,
input,
X),”
&
“44 (BC_4,
HOLD,
input,
X),”
“45 (BC_1,
HOLDA,
output3,
X,
“46 (BC_1,
*,
control,
1),”
“47 (BC_1,
ADSBAR,
output3,
X,
61, 1,
Z),”
&
“48 (BC_1,
BEBAR(3),
output3,
X,
61, 1,
Z),”
&
“49 (BC_1,
BEBAR(2),
output3,
X,
61, 1,
Z),”
&
“50 (BC_1,
BEBAR(1),
output3,
X,
61, 1,
Z),”
&
“51 (BC_1,
BEBAR(0),
output3,
X,
61, 1,
Z),”
&
“52 (BC_1,
BLASTBAR,
output3,
X,
61, 1,
Z),”
&
“53 (BC_1,
DENBAR,
output3,
X,
61, 1,
Z),”
&
“54 (BC_1,
WRBAR,
output3,
X,
61, 1,
Z),”
&
“55 (BC_1,
DTRBAR,
output3,
X,
56, 1,
Z),”
&
“56 (BC_1,
*,
control,
1),”
“57 (BC_1,
WAITBAR,
output3,
X,
61, 1,
Z),”
&
“58 (BC_1,
BSTALL,
output3,
X,
6,
1,
Z),”
&
“59 (BC_1,
DCBAR,
output3,
X,
61, 1,
Z),”
&
“60 (BC_1,
SUPBAR,
output3,
X,
61, 1,
Z),”
&
“61 (BC_1,
*,
control,
1),”
“62 (BC_1,
LOCKBAR,
output3,
X,
61, 1,
Z),”
&
“63 (BC_1,
BREQ,
output3,
X,
6,
1,
Z),”
&
“64 (BC_1,
A(31),
output3,
X,
80, 1,
Z),”
&
“65 (BC_1,
A(30),
output3,
X,
80, 1,
Z),”
&
“66 (BC_1,
A(29),
output3,
X,
80, 1,
Z),”
&
“67 (BC_1,
A(28),
output3,
X,
80, 1,
Z),”
&
“68 (BC_1,
A(27),
output3,
X,
80, 1,
Z),”
&
“69 (BC_1,
A(26),
output3,
X,
80, 1,
Z),”
&
“70 (BC_1,
A(25),
output3,
X,
80, 1,
Z),”
&
“71 (BC_1,
A(24),
output3,
X,
80, 1,
Z),”
&
“72 (BC_1,
A(23),
output3,
X,
80, 1,
Z),”
&
“73 (BC_1,
A(22),
output3,
X,
80, 1,
Z),”
&
“74 (BC_1,
A(21),
output3,
X,
80, 1,
Z),”
&
“75 (BC_1,
A(20),
output3,
X,
80, 1,
Z),”
&
&
46, 1,
&
&
&
Datasheet
80960HA/HD/HT
Example 2. Boundary-Scan Description Language (BSDL) for PQ2
Package Example (Sheet 8 of 8)
“76 (BC_1,
A(19),
output3,
X,
80, 1,
Z),”
&
“77 (BC_1,
A(18),
output3,
X,
80, 1,
Z),”
&
“78 (BC_1,
A(17),
output3,
X,
80, 1,
Z),”
&
80, 1,
Z),”
&
Z),”
&
“79 (BC_1,
A(16),
output3,
X,
“80 (BC_1,
*,
control,
1),”
“81 (BC_1,
A(15),
output3,
X,
&
80, 1,
“82 (BC_1,
A(14),
output3,
X,
80, 1,
Z),”
&
“83 (BC_1,
A(13),
output3,
X,
80, 1,
Z),”
&
“84 (BC_1,
A(12),
output3,
X,
80, 1,
Z),”
&
“85 (BC_1,
A(11),
output3,
X,
80, 1,
Z),”
&
“86 (BC_1,
A(10),
output3,
X,
80, 1,
Z),”
&
“87 (BC_1,
A(9),
output3,
X,
80, 1,
Z),”
&
“88 (BC_1,
A(8),
output3,
X,
80, 1,
Z),”
&
“89 (BC_1,
A(7),
output3,
X,
80, 1,
Z),”
&
“90 (BC_1,
A(6),
output3,
X,
80, 1,
Z),”
&
“91 (BC_1,
A(5),
output3,
X,
80, 1,
Z),”
&
“92 (BC_1,
A(4),
output3,
X,
80, 1,
Z),”
&
“93 (BC_1,
A(3),
output3,
X,
80, 1,
Z),”
&
80, 1,
Z),”
&
“94 (BC_1,
A(2),
output3,
X,
“95 (BC_4,
NMIBAR,
input,
X),”
&
“96 (BC_4,
XINTBAR(7),
input,
X),”
&
“97 (BC_4,
XINTBAR(6),
input,
X),”
&
“98 (BC_4,
XINTBAR(5),
input,
X),”
&
“99 (BC_4,
XINTBAR(4),
input,
X),”
&
“100(BC_4,
XINTBAR(3),
input,
X),”
&
“101(BC_4,
XINTBAR(2),
input,
X),”
&
“102(BC_4,
XINTBAR(1),
input,
X),”
&
“103(BC_4,
XINTBAR(0),
input,
X),”
&
“104(BC_4,
RESETBAR,
input,
X),”
&
“105(BC_4,
CLKIN,
input,
X),”
“106(BC_1,
CT(3),
output3,
X,
80, 1,
&
Z),”
&
“107(BC_1,
CT(2),
output3,
X,
80, 1,
Z),”
&
“108(BC_1,
CT(1),
output3,
X,
80, 1,
Z),”
&
“109(BC_1,
CT(0),
output3,
X,
80, 1,
Z),”
&
“110(BC_1,
PCHKBAR,
output3,
X,
111,1,
Z),”
&
“111(BC_1,
*,
control,
1)”;
end Ha_Processor;
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80960HA/HD/HT
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