Intel IXF1104 IXF1104_CSpec_Datasheet_Book User Manual To The 205ea831 77a6 4d70 Bf39 Cb66a5381fb4
User Manual: Intel IXF1104 to the manual
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Page Count: 227 [warning: Documents this large are best viewed by clicking the View PDF Link!]
- 1.0 Introduction
- 2.0 General Description
- 3.0 Ball Assignments and Ball List Tables
- 4.0 Ball Assignments and Signal Descriptions
- 4.1 Naming Conventions
- 4.2 Interface Signal Groups
- 4.3 Signal Description Tables
- Table 3. SPI3 Interface Signal Descriptions (Sheet 1 of 8)
- Table 4. SerDes Interface Signal Descriptions
- Table 5. GMII Interface Signal Descriptions (Sheet 1 of 2)
- Table 6. RGMII Interface Signal Descriptions (Sheet 1 of 2)
- Table 7. CPU Interface Signal Descriptions (Sheet 1 of 2)
- Table 8. Transmit Pause Control Interface Signal Descriptions
- Table 9. Optical Module Interface Signal Descriptions (Sheet 1 of 2)
- Table 10. MDIO Interface Signal Descriptions
- Table 11. LED Interface Signal Descriptions
- Table 12. JTAG Interface Signal Descriptions
- Table 13. System Interface Signal Descriptions
- Table 14. Power Supply Signal Descriptions
- 4.4 Ball Usage Summary
- 4.5 Multiplexed Ball Connections
- 4.6 Ball State During Reset
- 4.7 Power Supply Sequencing
- 4.8 Pull-Up/Pull-Down Ball Guidelines
- 4.9 Analog Power Filtering
- 5.0 Functional Descriptions
- 5.1 Media Access Controller (MAC)
- 5.2 SPI3 Interface
- 5.3 Gigabit Media Independent Interface (GMII)
- 5.4 Reduced Gigabit Media Independent Interface (RGMII)
- 5.5 MDIO Control and Interface
- 5.6 SerDes Interface
- 5.7 Optical Module Interface
- 5.7.1 IXF1104-Supported Optical Module Interface Signals
- 5.7.2 Functional Descriptions
- 5.7.3 I·C Module Configuration Interface
- 5.8 LED Interface
- 5.9 CPU Interface
- 5.10 TAP Interface (JTAG)
- 5.11 Loopback Modes
- 5.12 Clocks
- 6.0 Applications
- 7.0 Electrical Specifications
- Table 39. Absolute Maximum Ratings
- Table 40. Recommended Operating Conditions
- 7.1 DC Specifications
- 7.2 SPI3 AC Timing Specifications
- 7.3 RGMII AC Timing Specification
- 7.4 GMII AC Timing Specification
- 7.5 SerDes AC Timing Specification
- 7.6 MDIO AC Timing Specification
- 7.7 Optical Module and I2C AC Timing Specification
- 7.8 CPU AC Timing Specification
- 7.9 Transmit Pause Control AC Timing Specification
- 7.10 JTAG AC Timing Specification
- 7.11 System AC Timing Specification
- 7.12 LED AC Timing Specification
- 8.0 Register Set
- 8.1 Document Structure
- 8.2 Graphical Representation
- 8.3 Per Port Registers
- 8.4 Register Map
- Table 59. MAC Control Registers ($ Port Index + Offset) (Sheet 1 of 2)
- Table 60. MAC RX Statistics Registers ($ Port Index + Offset) (Sheet 1 of 2)
- Table 61. MAC TX Statistics Registers ($ Port Index + Offset)
- Table 62. PHY Autoscan Registers ($ Port Index + Offset)
- Table 63. Global Status and Configuration Registers ($ 0x500 - 0X50C)
- Table 64. RX FIFO Registers ($ 0x580 - 0x5BF) (Sheet 1 of 2)
- Table 65. TX FIFO Registers ($ 0x600 - 0x63E) (Sheet 1 of 2)
- Table 66. MDIO Registers ($ 0x680 - 0x683)
- Table 67. SPI3 Registers ($ 0x700 - 0x716) (Sheet 1 of 2)
- Table 68. SerDes Registers ($ 0x780 - 0x798)
- Table 69. Optical Module Registers ($ 0x799 - 0x79F)
- 8.4.1 MAC Control Registers
- Table 70. Station Address ($ Port_Index +0x00 - +0x01)
- Table 71. Desired Duplex ($ Port_Index + 0x02)
- Table 72. FD FC Type ($ Port_Index + 0x03)
- Table 73. Collision Distance ($ Port_Index + 0x05)
- Table 74. Collision Threshold ($ Port_Index + 0x06)
- Table 75. FC TX Timer Value ($ Port_Index + 0x07)
- Table 76. FD FC Address ($ Port_Index + 0x08 - + 0x09)
- Table 77. IPG Receive Time 1 ($ Port_Index + 0x0A)
- Table 78. IPG Receive Time 2 ($ Port_Index + 0x0B)
- Table 79. IPG Transmit Time ($ Port_Index + 0x0C)
- Table 80. Pause Threshold ($ Port_Index + 0x0E)
- Table 81. Max Frame Size (Addr: Port_Index + 0x0F)
- Table 82. MAC IF Mode and RGMII Speed ($ Port_Index + 0x10)
- Table 83. Flush TX ($ Port_Index + 0x11)
- Table 84. FC Enable ($ Port_Index + 0x12)
- Table 85. FC Back Pressure Length ($ Port_Index + 0x13)
- Table 86. Short Runts Threshold ($ Port_Index + 0x14)
- Table 87. Discard Unknown Control Frame ($ Port_Index + 0x15)
- Table 88. RX Config Word ($ Port_Index + 0x16) (Sheet 1 of 2)
- Table 89. TX Config Word ($ Port_Index + 0x17) (Sheet 1 of 2)
- Table 90. Diverse Config Write ($ Port_Index + 0x18) (Sheet 1 of 2)
- Table 91. RX Packet Filter Control ($ Port_Index + 0x19) (Sheet 1 of 2)
- Table 92. Port Multicast Address ($ Port_Index +0x1A - +0x1B)
- 8.4.2 MAC RX Statistics Register Overview
- 8.4.3 MAC TX Statistics Register Overview
- 8.4.4 PHY Autoscan Registers
- Table 95. PHY Control ($ Port Index + 0x60) (Sheet 1 of 2)
- Table 96. PHY Status ($ Port Index + 0x61) (Sheet 1 of 2)
- Table 97. PHY Identification 1 ($ Port Index + 0x62)
- Table 98. PHY Identification 2 ($ Port Index + 0x63) (Sheet 1 of 2)
- Table 99. Auto-Negotiation Advertisement ($ Port Index + 0x64) (Sheet 1 of 2)
- Table 100. Auto-Negotiation Link Partner Base Page Ability ($ Port Index + 0x65) (Sheet 1 of 2)
- Table 101. Auto-Negotiation Expansion ($ Port Index + 0x66)
- Table 102. Auto-Negotiation Next Page Transmit ($ Port Index + 0x67)
- 8.4.5 Global Status and Configuration Register Overview
- Table 103. Port Enable ($0x500)
- Table 104. Interface Mode ($0x501)
- Table 105. Link LED Enable ($0x502)
- Table 106. MAC Soft Reset ($0x505)
- Table 107. MDIO Soft Reset ($0x506)
- Table 108. CPU Interface ($0x508)
- Table 109. LED Control ($0x509)
- Table 110. LED Flash Rate ($0x50A)
- Table 111. LED Fault Disable ($0x50B)
- Table 112. JTAG ID ($0x50C)
- 8.4.6 RX FIFO Register Overview
- Table 113. RX FIFO High Watermark Port 0 ($0x580)
- Table 114. RX FIFO High Watermark Port 1 ($0x581)
- Table 115. RX FIFO High Watermark Port 2 ($0x582)
- Table 116. RX FIFO High Watermark Port 3 ($0x583)
- Table 117. RX FIFO Low Watermark Port 0 ($0x58A)
- Table 118. RX FIFO Low Watermark Port 1 ($0x58B)
- Table 119. RX FIFO Low Watermark Port 2 ($0x58C)
- Table 120. RX FIFO Low Watermark Port 3 ($0x58D)
- Table 121. RX FIFO Overflow Frame Drop Counter Ports 0 - 3 ($0x594 - 0x597)
- Table 122. RX FIFO Port Reset ($0x59E)
- Table 123. RX FIFO Errored Frame Drop Enable ($0x59F)
- Table 124. RX FIFO Overflow Event ($0x5A0)
- Table 125. RX FIFO Errored Frame Drop Counter Ports 0 - 3 ($0x5A2 - 0x5A5) (Sheet 1 of 2)
- Table 126. RX FIFO SPI3 Loopback Enable for Ports 0 - 3 ($0x5B2)
- Table 127. RX FIFO Padding and CRC Strip Enable ($0x5B3)
- Table 128. RX FIFO Transfer Threshold Port 0 ($0x5B8)
- Table 129. RX FIFO Transfer Threshold Port 1 ($0x5B9)
- Table 130. RX FIFO Transfer Threshold Port 2 ($0x5BA)
- Table 131. RX FIFO Transfer Threshold Port 3 ($0x5BB)
- 8.4.7 TX FIFO Register Overview
- Table 132. TX FIFO High Watermark Ports 0 - 3 ($0x600 - 0x603)
- Table 133. TX FIFO Low Watermark Register Ports 0 - 3 ($0x60A - 0x60D)
- Table 134. TX FIFO MAC Threshold Register Ports 0 - 3 ($0x614 - 0x617)
- Table 135. TX FIFO Overflow/Underflow/Out of Sequence Event ($0x61E) (Sheet 1 of 2)
- Table 136. Loop RX Data to TX FIFO (Line-Side Loopback) Ports 0 - 3 ($0x61F)
- Table 137. TX FIFO Port Reset ($0x620) (Sheet 1 of 2)
- Table 138. TX FIFO Overflow Frame Drop Counter Ports 0 - 3 ($0x621 - 0x624)
- Table 139. TX FIFO Errored Frame Drop Counter Ports 0 - 3 ($0x625 - 0x629)
- Table 140. TX FIFO Occupancy Counter for Ports 0 - 3 ($0x62D - 0x630)
- Table 141. TX FIFO Port Drop Enable ($0x63D)
- 8.4.8 MDIO Register Overview
- 8.4.9 SPI3 Register Overview
- 8.4.10 SerDes Register Overview
- 8.4.11 Optical Module Register Overview
- 9.0 Mechanical Specifications
- 10.0 Product Ordering Information