Intel Architecture Ia 32 Users Manual Intel® Software Developer’s

2015-02-02

• IA-32 Intel® Architecture Software Developer’s Manual
• Disclaimer
• CONTENTS FOR VOLUME 3A AND 3B
• CHAPTER 1 About This Manual
  • 1.1 IA-32 Processors Covered in this Manual
  • 1.2 Overview of The SYSTEM PROGRAMMING GUIDE
  • 1.3 Notational Conventions
    • 1.3.1 Bit and Byte Order
    • 1.3.2 Reserved Bits and Software Compatibility
    • 1.3.3 Instruction Operands
    • 1.3.4 Hexadecimal and Binary Numbers
    • 1.3.5 Segmented Addressing
    • 1.3.6 Syntax for CPUID, CR, and MSR Values
    • 1.3.7 Exceptions
  • 1.4 Related Literature
• CHAPTER 2 System Architecture Overview
  • 2.1 Overview of the System-Level Architecture
    • 2.1.1 Global and Local Descriptor Tables
      • 2.1.1.1 Global and Local Descriptor Tables in IA-32 Mode
    • 2.1.2 System Segments, Segment Descriptors, and Gates
      • 2.1.2.1 Gates in IA-32e Mode
    • 2.1.3 Task-State Segments and Task Gates
      • 2.1.3.1 Task-State Segments in IA-32e Mode
    • 2.1.4 Interrupt and Exception Handling
      • 2.1.4.1 Interrupt and Exception Handling IA-32e Mode
    • 2.1.5 Memory Management
      • 2.1.5.1 Memory Management in IA-32e Mode
    • 2.1.6 System Registers
      • 2.1.6.1 System Registers in IA-32e Mode
    • 2.1.7 Other System Resources
  • 2.2 Modes of Operation
  • 2.3 System Flags and Fields in the EFLAGS Register
    • 2.3.1 System Flags and Fields in IA-32e Mode
  • 2.4 Memory-Management Registers
    • 2.4.1 Global Descriptor Table Register (GDTR)
    • 2.4.2 Local Descriptor Table Register (LDTR)
    • 2.4.3 IDTR Interrupt Descriptor Table Register
    • 2.4.4 Task Register (TR)
  • 2.5 Control Registers
    • 2.5.1 CPUID Qualification of Control Register Flags
  • 2.6 System Instruction Summary
    • 2.6.1 Loading and Storing System Registers
    • 2.6.2 Verifying of Access Privileges
    • 2.6.3 Loading and Storing Debug Registers
    • 2.6.4 Invalidating Caches and TLBs
    • 2.6.5 Controlling the Processor
    • 2.6.6 Reading Performance-Monitoring and Time-Stamp Counters
      • 2.6.6.1 Reading Counters in 64-Bit Mode
    • 2.6.7 Reading and Writing Model-Specific Registers
      • 2.6.7.1 Reading and Writing Model-Specific Registers in 64-Bit Mode
• CHAPTER 3 Protected-Mode Memory Management
  • 3.1 Memory Management Overview
  • 3.2 Using Segments
    • 3.2.1 Basic Flat Model
    • 3.2.2 Protected Flat Model
    • 3.2.3 Multi-Segment Model
    • 3.2.4 Segmentation in IA-32e Mode
    • 3.2.5 Paging and Segmentation
  • 3.3 Physical Address Space
    • 3.3.1 Physical Address Space for Processors with Intel® EM64T
  • 3.4 Logical and Linear Addresses
    • 3.4.1 Logical Address Translation in IA-32e Mode
    • 3.4.2 Segment Selectors
    • 3.4.3 Segment Registers
    • 3.4.4 Segment Loading Instructions in IA-32e Mode
    • 3.4.5 Segment Descriptors
      • 3.4.5.1 Code- and Data-Segment Descriptor Types
  • 3.5 System Descriptor Types
    • 3.5.1 Segment Descriptor Tables
    • 3.5.2 Segment Descriptor Tables in IA-32e Mode
  • 3.6 Paging (Virtual Memory) Overview
    • 3.6.1 Paging Options
    • 3.6.2 Page Tables and Directories in the Absence of Intel EM64T
  • 3.7 Page Translation using 32-Bit Physical Addressing
    • 3.7.1 Linear Address Translation (4-KByte Pages)
    • 3.7.2 Linear Address Translation (4-MByte Pages)
    • 3.7.3 Mixing 4-KByte and 4-MByte Pages
    • 3.7.4 Memory Aliasing
    • 3.7.5 Base Address of the Page Directory
    • 3.7.6 Page-Directory and Page-Table Entries
    • 3.7.7 Not Present Page-Directory and Page-Table Entries
  • 3.8 36-Bit Physical Addressing Using the PAE Paging Mechanism
    • 3.8.1 Enhanced Legacy PAE Paging
    • 3.8.2 Linear Address Translation With PAE Enabled (4-KByte Pages)
    • 3.8.3 Linear Address Translation With PAE Enabled (2-MByte Pages)
    • 3.8.4 Accessing the Full Extended Physical Address Space With the Extended Page-Table Structure
    • 3.8.5 Page-Directory and Page-Table Entries With Extended Addressing Enabled
  • 3.9 36-Bit Physical Addressing Using the PSE-36 Paging Mechanism
  • 3.10 PAE-Enabled Paging in IA-32e Mode
    • 3.10.1 IA-32e Mode Linear Address Translation (4-KByte Pages)
    • 3.10.2 IA-32e Mode Linear Address Translation (2-MByte Pages)
    • 3.10.3 Enhanced Paging Data Structures
      • 3.10.3.1 Reserved Bit Checking
  • 3.11 Mapping Segments to Pages
  • 3.12 Translation Lookaside Buffers (TLBs)
• CHAPTER 4 Protection
  • 4.1 Enabling and Disabling Segment and Page Protection
  • 4.2 Fields and Flags Used for Segment-Level and Page-Level Protection
    • 4.2.1 Code Segment Descriptor in 64-bit Mode
  • 4.3 Limit Checking
    • 4.3.1 Limit Checking in 64-bit Mode
  • 4.4 Type Checking
    • 4.4.1 Null Segment Selector Checking
      • 4.4.1.1 NULL Segment Checking in 64-bit Mode
  • 4.5 Privilege Levels
  • 4.6 Privilege Level Checking When Accessing Data Segments
    • 4.6.1 Accessing Data in Code Segments
  • 4.7 Privilege Level Checking When Loading the SS Register
  • 4.8 Privilege Level Checking When Transferring Program Control Between Code Segments
    • 4.8.1 Direct Calls or Jumps to Code Segments
      • 4.8.1.1 Accessing Nonconforming Code Segments
      • 4.8.1.2 Accessing Conforming Code Segments
    • 4.8.2 Gate Descriptors
    • 4.8.3 Call Gates
      • 4.8.3.1 IA-32e Mode Call Gates
    • 4.8.4 Accessing a Code Segment Through a Call Gate
    • 4.8.5 Stack Switching
      • 4.8.5.1 Stack Switching in 64-bit Mode
    • 4.8.6 Returning from a Called Procedure
    • 4.8.7 Performing Fast Calls to System Procedures with the SYSENTER and SYSEXIT Instructions
      • 4.8.7.1 SYSENTER and SYSEXIT Instructions in IA-32e Mode
    • 4.8.8 Fast System Calls in 64-bit Mode
  • 4.9 Privileged Instructions
  • 4.10 Pointer Validation
    • 4.10.1 Checking Access Rights (LAR Instruction)
    • 4.10.2 Checking Read/Write Rights (VERR and VERW Instructions)
    • 4.10.3 Checking That the Pointer Offset Is Within Limits (LSL Instruction)
    • 4.10.4 Checking Caller Access Privileges (ARPL Instruction)
    • 4.10.5 Checking Alignment
  • 4.11 Page-Level Protection
    • 4.11.1 Page-Protection Flags
    • 4.11.2 Restricting Addressable Domain
    • 4.11.3 Page Type
    • 4.11.4 Combining Protection of Both Levels of Page Tables
    • 4.11.5 Overrides to Page Protection
  • 4.12 Combining Page and Segment Protection
  • 4.13 Page-Level Protection and Execute-Disable Bit
    • 4.13.1 Detecting and Enabling the Execute-Disable Bit Capability
    • 4.13.2 Execute-Disable Bit Page Protection
    • 4.13.3 Reserved Bit Checking
    • 4.13.4 Exception Handling
• CHAPTER 5 Interrupt and Exception Handling
  • 5.1 Interrupt and Exception Overview
  • 5.2 Exception and Interrupt Vectors
  • 5.3 Sources of Interrupts
    • 5.3.1 External Interrupts
    • 5.3.2 Maskable Hardware Interrupts
    • 5.3.3 Software-Generated Interrupts
  • 5.4 Sources of Exceptions
    • 5.4.1 Program-Error Exceptions
    • 5.4.2 Software-Generated Exceptions
    • 5.4.3 Machine-Check Exceptions
  • 5.5 Exception Classifications
  • 5.6 Program or Task Restart
  • 5.7 NonMaskable Interrupt (NMI)
    • 5.7.1 Handling Multiple NMIs
  • 5.8 Enabling and Disabling Interrupts
    • 5.8.1 Masking Maskable Hardware Interrupts
    • 5.8.2 Masking Instruction Breakpoints
    • 5.8.3 Masking Exceptions and Interrupts When Switching Stacks
  • 5.9 Priority Among Simultaneous Exceptions and Interrupts
  • 5.10 Interrupt Descriptor Table (IDT)
  • 5.11 IDT Descriptors
  • 5.12 Exception and Interrupt Handling
    • 5.12.1 Exception- or Interrupt-Handler Procedures
      • 5.12.1.1 Protection of Exception- and Interrupt-Handler Procedures
      • 5.12.1.2 Flag Usage By Exception- or Interrupt-Handler Procedure
    • 5.12.2 Interrupt Tasks
  • 5.13 Error Code
  • 5.14 Exception and Interrupt Handling in 64-bit Mode
    • 5.14.1 64-Bit Mode IDT
    • 5.14.2 64-Bit Mode Stack Frame
    • 5.14.3 IRET in IA-32e Mode
    • 5.14.4 Stack Switching in IA-32e Mode
    • 5.14.5 Interrupt Stack Table
  • 5.15 Exception and Interrupt Reference
    • Interrupt 0-Divide Error Exception (#DE)
    • Interrupt 1-Debug Exception (#DB)
    • Interrupt 2-NMI Interrupt
    • Interrupt 3-Breakpoint Exception (#BP)
    • Interrupt 4-Overflow Exception (#OF)
    • Interrupt 5-BOUND Range Exceeded Exception (#BR)
    • Interrupt 6-Invalid Opcode Exception (#UD)
    • Interrupt 7-Device Not Available Exception (#NM)
    • Interrupt 8-Double Fault Exception (#DF)
    • Interrupt 9-Coprocessor Segment Overrun
    • Interrupt 10-Invalid TSS Exception (#TS)
    • Interrupt 11-Segment Not Present (#NP)
    • Interrupt 12-Stack Fault Exception (#SS)
    • Interrupt 13-General Protection Exception (#GP)
    • Interrupt 14-Page-Fault Exception (#PF)
    • Interrupt 16-x87 FPU Floating-Point Error (#MF)
    • Interrupt 17-Alignment Check Exception (#AC)
    • Interrupt 18-Machine-Check Exception (#MC)
    • Interrupt 19-SIMD Floating-Point Exception (#XF)
    • Interrupts 32 to 255-User Defined Interrupts
• CHAPTER 6 Task Management
  • 6.1 Task Management Overview
    • 6.1.1 Task Structure
    • 6.1.2 Task State
    • 6.1.3 Executing a Task
  • 6.2 Task Management Data Structures
    • 6.2.1 Task-State Segment (TSS)
    • 6.2.2 TSS Descriptor
    • 6.2.3 TSS Descriptor in 64-bit mode
    • 6.2.4 Task Register
    • 6.2.5 Task-Gate Descriptor
  • 6.3 Task Switching
  • 6.4 Task Linking
    • 6.4.1 Use of Busy Flag To Prevent Recursive Task Switching
    • 6.4.2 Modifying Task Linkages
  • 6.5 Task Address Space
    • 6.5.1 Mapping Tasks to the Linear and Physical Address Spaces
    • 6.5.2 Task Logical Address Space
  • 6.6 16-Bit Task-State Segment (TSS)
  • 6.7 Task Management in 64-bit Mode
• CHAPTER 7 Multiple-Processor Management
  • 7.1 Locked Atomic Operations
    • 7.1.1 Guaranteed Atomic Operations
    • 7.1.2 Bus Locking
      • 7.1.2.1 Automatic Locking
      • 7.1.2.2 Software Controlled Bus Locking
    • 7.1.3 Handling Self- and Cross-Modifying Code
    • 7.1.4 Effects of a LOCK Operation on Internal Processor Caches
  • 7.2 Memory Ordering
    • 7.2.1 Memory Ordering in the Intel® Pentium® and Intel486™ Processors
    • 7.2.2 Memory Ordering Pentium 4, Intel® Xeon®, and P6 Family Processors
    • 7.2.3 Out-of-Order Stores For String Operations in Pentium 4, Intel Xeon, and P6 Family Processors
    • 7.2.4 Strengthening or Weakening the Memory Ordering Model
  • 7.3 Propagation of Page Table and Page Directory Entry Changes to Multiple Processors
  • 7.4 Serializing Instructions
  • 7.5 Multiple-Processor (MP) Initialization
    • 7.5.1 BSP and AP Processors
    • 7.5.2 MP Initialization Protocol Requirements and Restrictions for Intel Xeon Processors
    • 7.5.3 MP Initialization Protocol Algorithm for Intel Xeon Processors
    • 7.5.4 MP Initialization Example
      • 7.5.4.1 Typical BSP Initialization Sequence
      • 7.5.4.2 Typical AP Initialization Sequence
    • 7.5.5 Identifying Logical Processors in an MP System
  • 7.6 Hyper-Threading and Multi-Core Technology
  • 7.7 Detecting Hardware Multi-Threading Support and Topology
    • 7.7.1 Initializing IA-32 Processors Supporting Hyper-Threading Technology
    • 7.7.2 Initializing Dual-Core IA-32 Processors
    • 7.7.3 Executing Multiple Threads on an IA-32 Processor Supporting Hardware Multi-Threading
    • 7.7.4 Handling Interrupts on an IA-32 Processor Supporting Hardware Multi-Threading
  • 7.8 Intel® Hyper-Threading Technology Architecture
    • 7.8.1 State of the Logical Processors
    • 7.8.2 APIC Functionality
    • 7.8.3 Memory Type Range Registers (MTRR)
    • 7.8.4 Page Attribute Table (PAT)
    • 7.8.5 Machine Check Architecture
    • 7.8.6 Debug Registers and Extensions
    • 7.8.7 Performance Monitoring Counters
    • 7.8.8 IA32_MISC_ENABLE MSR
    • 7.8.9 Memory Ordering
    • 7.8.10 Serializing Instructions
    • 7.8.11 MICROCODE UPDATE Resources
    • 7.8.12 Self Modifying Code
    • 7.8.13 Implementation-Specific HT Technology Facilities
      • 7.8.13.1 Processor Caches
      • 7.8.13.2 Processor Translation Lookaside Buffers (TLBs)
      • 7.8.13.3 Thermal Monitor
      • 7.8.13.4 External Signal Compatibility
  • 7.9 Dual-Core Architecture
    • 7.9.1 Logical Processor Support
    • 7.9.2 Memory Type Range Registers (MTRR)
    • 7.9.3 Performance Monitoring Counters
    • 7.9.4 IA32_MISC_ENABLE MSR
    • 7.9.5 MICROCODE UPDATE Resources
  • 7.10 Programming Considerations for Hardware Multi-Threading Capable Processors
    • 7.10.1 Hierarchical Mapping of Shared Resources
    • 7.10.2 Identifying Logical Processors in an MP System
    • 7.10.3 Algorithm for Three-Level Mappings of APIC_ID
    • 7.10.4 Identifying Topological Relationships in a MP System
  • 7.11 Management of Idle and Blocked Conditions
    • 7.11.1 HLT Instruction
    • 7.11.2 PAUSE Instruction
    • 7.11.3 Detecting Support MONITOR/MWAIT Instruction
    • 7.11.4 MONITOR/MWAIT Instruction
    • 7.11.5 Monitor/Mwait Address Range Determination
    • 7.11.6 Required Operating System Support
      • 7.11.6.1 Use the PAUSE Instruction in Spin-Wait Loops
      • 7.11.6.2 Potential Usage of MONITOR/MWAIT in C0 Idle Loops
      • 7.11.6.3 Halt Idle Logical Processors
      • 7.11.6.4 Potential Usage of MONITOR/MWAIT in C1 Idle Loops
      • 7.11.6.5 Guidelines for Scheduling Threads on Logical Processors Sharing Execution Resources
      • 7.11.6.6 Eliminate Execution-Based Timing Loops
      • 7.11.6.7 Place Locks and Semaphores in Aligned, 128-Byte Blocks of Memory
• CHAPTER 8 Advanced Programmable Interrupt Controller (APIC)
  • 8.1 Local and I/O APIC Overview
  • 8.2 System Bus Vs. APIC Bus
  • 8.3 the Intel® 82489DX External APIC, The APIC, and the xAPIC
  • 8.4 Local APIC
    • 8.4.1 The Local APIC Block Diagram
    • 8.4.2 Presence of the Local APIC
    • 8.4.3 Enabling or Disabling the Local APIC
    • 8.4.4 Local APIC Status and Location
    • 8.4.5 Relocating the Local APIC Registers
    • 8.4.6 Local APIC ID
    • 8.4.7 Local APIC State
      • 8.4.7.1 Local APIC State After Power-Up or Reset
      • 8.4.7.2 Local APIC State After It Has Been Software Disabled
      • 8.4.7.3 Local APIC State After an INIT Reset (“Wait-for-SIPI” State)
      • 8.4.7.4 Local APIC State After It Receives an INIT-Deassert IPI
    • 8.4.8 Local APIC Version Register
  • 8.5 Handling Local Interrupts
    • 8.5.1 Local Vector Table
    • 8.5.2 Valid Interrupt Vectors
    • 8.5.3 Error Handling
    • 8.5.4 APIC Timer
    • 8.5.5 Local Interrupt Acceptance
  • 8.6 Issuing Interprocessor Interrupts
    • 8.6.1 Interrupt Command Register (ICR)
    • 8.6.2 Determining IPI Destination
      • 8.6.2.1 Physical Destination Mode
      • 8.6.2.2 Logical Destination Mode
      • 8.6.2.3 Broadcast/Self Delivery Mode
      • 8.6.2.4 Lowest Priority Delivery Mode
    • 8.6.3 IPI Delivery and Acceptance
  • 8.7 System and APIC Bus Arbitration
  • 8.8 Handling Interrupts
    • 8.8.1 Interrupt Handling with the Pentium 4 and Intel Xeon Processors
    • 8.8.2 Interrupt Handling with the P6 Family and Pentium Processors
    • 8.8.3 Interrupt, Task, and Processor Priority
      • 8.8.3.1 Task and Processor Priorities
    • 8.8.4 Interrupt Acceptance for Fixed Interrupts
    • 8.8.5 Signaling Interrupt Servicing Completion
    • 8.8.6 Task Priority in IA-32e Mode
      • 8.8.6.1 Interaction of Task Priorities between CR8 and APIC
  • 8.9 Spurious Interrupt
  • 8.10 APIC Bus Message Passing Mechanism and Protocol (P6 Family, Pentium Processors)
    • 8.10.1 Bus Message Formats
  • 8.11 Message Signalled Interrupts
    • 8.11.1 Message Address Register Format
    • 8.11.2 Message Data Register Format
• CHAPTER 9 Processor Management and Initialization
  • 9.1 Initialization Overview
    • 9.1.1 Processor State After Reset
    • 9.1.2 Processor Built-In Self-Test (BIST)
    • 9.1.3 Model and Stepping Information
    • 9.1.4 First Instruction Executed
  • 9.2 x87 FPU Initialization
    • 9.2.1 Configuring the x87 FPU Environment
    • 9.2.2 Setting the Processor for x87 FPU Software Emulation
  • 9.3 Cache Enabling
  • 9.4 Model-Specific Registers (MSRs)
  • 9.5 Memory Type Range Registers (MTRRs)
  • 9.6 Initializing SSE/SSE2/SSE3 Extensions
  • 9.7 Software Initialization for Real-Address Mode Operation
    • 9.7.1 Real-Address Mode IDT
    • 9.7.2 NMI Interrupt Handling
  • 9.8 Software Initialization for Protected-Mode Operation
    • 9.8.1 Protected-Mode System Data Structures
    • 9.8.2 Initializing Protected-Mode Exceptions and Interrupts
    • 9.8.3 Initializing Paging
    • 9.8.4 Initializing Multitasking
    • 9.8.5 Initializing IA-32e Mode
      • 9.8.5.1 IA-32e Mode System Data Structures
      • 9.8.5.2 IA-32e Mode Interrupts and Exceptions
      • 9.8.5.3 64-bit Mode and Compatibility Mode Operation
      • 9.8.5.4 Switching Out of IA-32e Mode Operation
  • 9.9 Mode Switching
    • 9.9.1 Switching to Protected Mode
    • 9.9.2 Switching Back to Real-Address Mode
  • 9.10 Initialization and Mode Switching Example
    • 9.10.1 Assembler Usage
    • 9.10.2 STARTUP.ASM Listing
    • 9.10.3 MAIN.ASM Source Code
    • 9.10.4 Supporting Files
  • 9.11 Microcode Update Facilities
    • 9.11.1 Microcode Update
    • 9.11.2 Optional Extended Signature Table
    • 9.11.3 Processor Identification
    • 9.11.4 Platform Identification
    • 9.11.5 Microcode Update Checksum
    • 9.11.6 Microcode Update Loader
      • 9.11.6.1 Hard Resets in Update Loading
      • 9.11.6.2 Update in a Multiprocessor System
      • 9.11.6.3 Update in a System Supporting Intel Hyper-Threading Technology
      • 9.11.6.4 Update in a System Supporting Dual-Core Technology
      • 9.11.6.5 Update Loader Enhancements
    • 9.11.7 Update Signature and Verification
      • 9.11.7.1 Determining the Signature
      • 9.11.7.2 Authenticating the Update
    • 9.11.8 Pentium 4, Intel Xeon, and P6 Family Processor Microcode Update Specifications
      • 9.11.8.1 Responsibilities of the BIOS
      • 9.11.8.2 Responsibilities of the Calling Program
      • 9.11.8.3 Microcode Update Functions
      • 9.11.8.4 INT 15H-based Interface
      • 9.11.8.5 Function 00H-Presence Test
      • 9.11.8.6 Function 01H-Write Microcode Update Data
      • 9.11.8.7 Function 02H-Microcode Update Control
      • 9.11.8.8 Function 03H-Read Microcode Update Data
      • 9.11.8.9 Return Codes
• CHAPTER 10 Memory Cache Control
  • 10.1 Internal Caches, TLBs, and Buffers
  • 10.2 Caching Terminology
  • 10.3 Methods of Caching Available
    • 10.3.1 Buffering of Write Combining Memory Locations
    • 10.3.2 Choosing a Memory Type
  • 10.4 Cache Control Protocol
  • 10.5 Cache Control
    • 10.5.1 Cache Control Registers and Bits
    • 10.5.2 Precedence of Cache Controls
      • 10.5.2.1 Selecting Memory Types for Pentium Pro and Pentium II Processors
      • 10.5.2.2 Selecting Memory Types for Pentium 4, Intel Xeon, and Pentium III Processors
      • 10.5.2.3 Writing Values Across Pages with Different Memory Types
    • 10.5.3 Preventing Caching
    • 10.5.4 Disabling and Enabling the L3 Cache
    • 10.5.5 Cache Management Instructions
    • 10.5.6 L1 Data Cache Context Mode
      • 10.5.6.1 Adaptive Mode
      • 10.5.6.2 Shared Mode
  • 10.6 Self-Modifying Code
  • 10.7 Implicit Caching (Pentium 4, Intel Xeon, and P6 Family Processors)
  • 10.8 Explicit Caching
  • 10.9 Invalidating the Translation Lookaside Buffers (TLBs)
  • 10.10 Store Buffer
  • 10.11 Memory Type Range Registers (MTRRs)
    • 10.11.1 MTRR Feature Identification
    • 10.11.2 Setting Memory Ranges with MTRRs
      • 10.11.2.1 IA32_MTRR_DEF_TYPE MSR
      • 10.11.2.2 Fixed Range MTRRs
      • 10.11.2.3 Variable Range MTRRs
    • 10.11.3 Example Base and Mask Calculations
      • 10.11.3.1 Base and Mask Calculations with Intel EM64T
    • 10.11.4 Range Size and Alignment Requirement
      • 10.11.4.1 MTRR Precedences
    • 10.11.5 MTRR Initialization
    • 10.11.6 Remapping Memory Types
    • 10.11.7 MTRR Maintenance Programming Interface
      • 10.11.7.1 MemTypeGet() Function
      • 10.11.7.2 MemTypeSet() Function
    • 10.11.8 MTRR Considerations in MP Systems
    • 10.11.9 Large Page Size Considerations
  • 10.12 Page Attribute Table (PAT)
    • 10.12.1 Detecting Support for the PAT Feature
    • 10.12.2 IA32_CR_PAT MSR
    • 10.12.3 Selecting a Memory Type from the PAT
    • 10.12.4 Programming the PAT
    • 10.12.5 PAT Compatibility with Earlier IA-32 Processors
• CHAPTER 11 Intel® MMX™ Technology System Programming
  • 11.1 Emulation of the MMX Instruction Set
  • 11.2 The MMX State and MMX Register Aliasing
    • 11.2.1 Effect of MMX, x87 FPU, FXSAVE, and FXRSTOR Instructions on the x87 FPU Tag Word
  • 11.3 Saving and Restoring the MMX State and Registers
  • 11.4 Saving MMX State on Task or Context Switches
  • 11.5. EXCEPTIONS That Can Occur When Executing MMX Instructions
    • 11.5.1 Effect of MMX Instructions on Pending x87 Floating-Point Exceptions
  • 11.6 Debugging MMX Code
• CHAPTER 12 SSE, SSE2 and SSE3 System Programming
  • 12.1 Providing Operating System Support for SSE/SSE2/SSE3 Extensions
    • 12.1.1 Adding Support to an Operating System for SSE/SSE2/SSE3 Extensions
    • 12.1.2 Checking for SSE/SSE2/SSE3 Extension Support
    • 12.1.3 Checking for Support for the FXSAVE and FXRSTOR Instructions
    • 12.1.4 Initialization of the SSE/SSE2/SSE3 Extensions
    • 12.1.5 Providing Non-Numeric Exception Handlers for Exceptions Generated by the SSE/SSE2/SSE3 Instructions
    • 12.1.6 Providing an Handler for the SIMD Floating-Point Exception (#XF)
      • 12.1.6.1 Numeric Error flag and IGNNE#
  • 12.2 Emulation of SSE/SSE2/SSE3 Extensions
  • 12.3 Saving and Restoring the SSE/SSE2/SSE3 State
  • 12.4 Saving the SSE/SSE2/SSE3 State on Task or Context Switches
  • 12.5 Designing OS Facilities for AUTOMATICALLY Saving x87 FPU, MMX, and SSE/SSE2/SSE3 state on Task or Context Switches
    • 12.5.1. Using the TS Flag to Control the Saving of the x87 FPU, MMX, SSE, SSE2 and SSE3 State
• CHAPTER 13 Power and Thermal Management
  • 13.1 Enhanced Intel Speedstep® Technology
    • 13.1.1 Software Interface For Initiating Performance State Transitions
  • 13.2 P-State Hardware Coordination
  • 13.3 MWAIT Extensions for Advanced Power Management
  • 13.4 Thermal Monitoring and Protection
    • 13.4.1 Catastrophic Shutdown Detector
    • 13.4.2 Thermal Monitor
      • 13.4.2.1 Thermal Monitor 1
      • 13.4.2.2 Thermal Monitor 2
      • 13.4.2.3 Two Methods for Enabling TM2
      • 13.4.2.4 Performance State Transitions and Thermal Monitoring
      • 13.4.2.5 Thermal Status Information
    • 13.4.3 Software Controlled Clock Modulation
    • 13.4.4 Detection of Thermal Monitor and Software Controlled Clock Modulation Facilities
    • 13.4.5 On Die Digital Thermal Sensors
      • 13.4.5.1 Digital Thermal Sensor Enumeration
      • 13.4.5.2 Reading the Digital Sensor
• CHAPTER 14 Machine-Check Architecture
  • 14.1 Machine-Check Exceptions and Architecture
  • 14.2 Compatibility with Pentium Processor
  • 14.3 Machine-Check MSRs
    • 14.3.1 Machine-Check Global Control MSRs
      • 14.3.1.1 IA32_MCG_CAP MSR (Pentium 4 and Intel Xeon Processors)
      • 14.3.1.2 MCG_CAP MSR (P6 Family Processors)
      • 14.3.1.3 IA32_MCG_STATUS MSR
      • 14.3.1.4 IA32_MCG_CTL MSR
    • 14.3.2 Error-Reporting Register Banks
      • 14.3.2.1 IA32_MCi_CTL MSRs
      • 14.3.2.2 IA32_MCi_STATUS MSRs
      • 14.3.2.3 IA32_MCi_ADDR MSRs
      • 14.3.2.4 IA32_MCi_MISC MSRs
      • 14.3.2.5 IA32_MCG Extended Machine Check State MSRs
    • 14.3.3 Mapping of the Pentium Processor Machine-Check Errors to the Machine-Check Architecture
  • 14.4 Machine-Check Availability
  • 14.5 Machine-Check Initialization
  • 14.6. Interpreting the MCA Error Codes
    • 14.6.1 Simple Error Codes
    • 14.6.2 Compound Error Codes
    • 14.6.3 Machine-Check Error Codes Interpretation
  • 14.7 Guidelines for Writing Machine-Check Software
    • 14.7.1 Machine-Check Exception Handler
    • 14.7.2 Enabling BINIT# Drive and BINIT# Observation
    • 14.7.3 Pentium Processor Machine-Check Exception Handling
    • 14.7.4 Logging Correctable Machine-Check Errors
• CHAPTER 15 8086 Emulation
  • 15.1 Real-Address Mode
    • 15.1.1 Address Translation in Real-Address Mode
    • 15.1.2 Registers Supported in Real-Address Mode
    • 15.1.3 Instructions Supported in Real-Address Mode
    • 15.1.4 Interrupt and Exception Handling
  • 15.2 Virtual-8086 Mode
    • 15.2.1 Enabling Virtual-8086 Mode
    • 15.2.2 Structure of a Virtual-8086 Task
    • 15.2.3 Paging of Virtual-8086 Tasks
    • 15.2.4 Protection within a Virtual-8086 Task
    • 15.2.5 Entering Virtual-8086 Mode
    • 15.2.6 Leaving Virtual-8086 Mode
    • 15.2.7 Sensitive Instructions
    • 15.2.8 Virtual-8086 Mode I/O
      • 15.2.8.1 I/O-Port-Mapped I/O
      • 15.2.8.2 Memory-Mapped I/O
      • 15.2.8.3 Special I/O Buffers
  • 15.3 Interrupt and Exception Handling in Virtual-8086 Mode
    • 15.3.1 Class 1-Hardware Interrupt and Exception Handling in Virtual-8086 Mode
      • 15.3.1.1 Handling an Interrupt or Exception Through a Protected-Mode Trap or Interrupt Gate
      • 15.3.1.2 Handling an Interrupt or Exception With an 8086 Program Interrupt or Exception Handler
      • 15.3.1.3 Handling an Interrupt or Exception Through a Task Gate
    • 15.3.2 Class 2-Maskable Hardware Interrupt Handling in Virtual-8086 Mode Using the Virtual Interrupt Mechanism
    • 15.3.3 Class 3-Software Interrupt Handling in Virtual-8086 Mode
      • 15.3.3.1 Method 1: Software Interrupt Handling
      • 15.3.3.2 Methods 2 and 3: Software Interrupt Handling
      • 15.3.3.3 Method 4: Software Interrupt Handling
      • 15.3.3.4 Method 5: Software Interrupt Handling
      • 15.3.3.5 Method 6: Software Interrupt Handling
  • 15.4 Protected-Mode Virtual Interrupts
• CHAPTER 16 Mixing 16-Bit and 32-Bit Code
  • 16.1 Defining 16-Bit and 32-Bit Program Modules
  • 16.2 Mixing 16-Bit and 32-Bit Operations Within a Code Segment
  • 16.3 Sharing Data Among Mixed-Size Code Segments
  • 16.4 Transferring Control Among Mixed-Size Code Segments
    • 16.4.1 Code-Segment Pointer Size
    • 16.4.2 Stack Management for Control Transfer
      • 16.4.2.1 Controlling the Operand-Size Attribute For a Call
      • 16.4.2.2 Passing Parameters With a Gate
    • 16.4.3 Interrupt Control Transfers
    • 16.4.4 Parameter Translation
    • 16.4.5 Writing Interface Procedures
• CHAPTER 17 IA-32 Architecture Compatibility
  • 17.1. IA-32 Processor Families and Categories
  • 17.2. Reserved Bits
  • 17.3. Enabling New Functions and Modes
  • 17.4. Detecting the Presence of New Features Through Software
  • 17.5. Intel MMX Technology
  • 17.6. Streaming SIMD Extensions (SSE)
  • 17.7. Streaming SIMD Extensions 2 (SSE2)
  • 17.8. Streaming SIMD Extensions 3 (SSE3)
  • 17.9. Hyper-Threading Technology
  • 17.10. Dual-Core Technology
  • 17.11. Specific Features of Dual-Core Processor
  • 17.12. New Instructions In the Pentium and Later IA-32 Processors
    • 17.12.1 Instructions Added Prior to the Pentium Processor
  • 17.13. Obsolete Instructions
  • 17.14. Undefined Opcodes
  • 17.15. New Flags in the EFLAGS Register
    • 17.15.1 Using EFLAGS Flags to Distinguish Between 32-Bit IA-32 Processors
  • 17.16. Stack Operations
    • 17.16.1 PUSH SP
    • 17.16.2 EFLAGS Pushed on the Stack
  • 17.17. x87 FPU
    • 17.17.1 Control Register CR0 Flags
    • 17.17.2 x87 FPU Status Word
      • 17.17.2.1 Condition Code Flags (C0 through C3)
      • 17.17.2.2 Stack Fault Flag
    • 17.17.3 x87 FPU Control Word
    • 17.17.4 x87 FPU Tag Word
    • 17.17.5 Data Types
      • 17.17.5.1 NaNs
      • 17.17.5.2 Pseudo-zero, Pseudo-NaN, Pseudo-infinity, and Unnormal Formats
    • 17.17.6 Floating-Point Exceptions
      • 17.17.6.1 Denormal Operand Exception (#D)
      • 17.17.6.2 Numeric Overflow Exception (#O)
      • 17.17.6.3 Numeric Underflow Exception (#U)
      • 17.17.6.4 Exception Precedence
      • 17.17.6.5 CS and EIP For FPU Exceptions
      • 17.17.6.6 FPU Error Signals
      • 17.17.6.7 Assertion of the FERR# Pin
      • 17.17.6.8 Invalid Operation Exception On Denormals
      • 17.17.6.9 Alignment Check Exceptions (#AC)
      • 17.17.6.10 Segment Not Present Exception During FLDENV
      • 17.17.6.11 Device Not Available Exception (#NM)
      • 17.17.6.12 Coprocessor Segment Overrun Exception
      • 17.17.6.13 General Protection Exception (#GP)
      • 17.17.6.14 Floating-Point Error Exception (#MF)
    • 17.17.7 Changes to Floating-Point Instructions
      • 17.17.7.1 FDIV, FPREM, and FSQRT Instructions
      • 17.17.7.2 FSCALE Instruction
      • 17.17.7.3 FPREM1 Instruction
      • 17.17.7.4 FPREM Instruction
      • 17.17.7.5 FUCOM, FUCOMP, and FUCOMPP Instructions
      • 17.17.7.6 FPTAN Instruction
      • 17.17.7.7 Stack Overflow
      • 17.17.7.8 FSIN, FCOS, and FSINCOS Instructions
      • 17.17.7.9 FPATAN Instruction
      • 17.17.7.10 F2XM1 Instruction
      • 17.17.7.11 FLD Instruction
      • 17.17.7.12 FXTRACT Instruction
      • 17.17.7.13 Load Constant Instructions
      • 17.17.7.14 FSETPM Instruction
      • 17.17.7.15 FXAM Instruction
      • 17.17.7.16 FSAVE and FSTENV Instructions
    • 17.17.8 Transcendental Instructions
    • 17.17.9 Obsolete Instructions
    • 17.17.10 WAIT/FWAIT Prefix Differences
    • 17.17.11 Operands Split Across Segments and/or Pages
    • 17.17.12 FPU Instruction Synchronization
  • 17.18. Serializing Instructions
  • 17.19. FPU and Math Coprocessor Initialization
    • 17.19.1 Intel® 387 and Intel® 287 Math Coprocessor Initialization
    • 17.19.2 Intel486 SX Processor and Intel 487 SX Math Coprocessor Initialization
  • 17.20. Control Registers
  • 17.21. Memory Management Facilities
    • 17.21.1 New Memory Management Control Flags
      • 17.21.1.1 Physical Memory Addressing Extension
      • 17.21.1.2 Global Pages
      • 17.21.1.3 Larger Page Sizes
    • 17.21.2 CD and NW Cache Control Flags
    • 17.21.3 Descriptor Types and Contents
    • 17.21.4 Changes in Segment Descriptor Loads
  • 17.22. Debug Facilities
    • 17.22.1 Differences in Debug Register DR6
    • 17.22.2 Differences in Debug Register DR7
    • 17.22.3 Debug Registers DR4 and DR5
  • 17.23. Recognition of Breakpoints
  • 17.24. Exceptions and/or Exception Conditions
    • 17.24.1 Machine-Check Architecture
    • 17.24.2 Priority OF Exceptions
  • 17.25. Interrupts
    • 17.25.1 Interrupt Propagation Delay
    • 17.25.2 NMI Interrupts
    • 17.25.3 IDT Limit
  • 17.26. Advanced Programmable Interrupt Controller (APIC)
    • 17.26.1 Software Visible Differences Between the Local APIC and the 82489DX
    • 17.26.2 New Features Incorporated in the Local APIC for the P6 Family and Pentium Processors
    • 17.26.3 New Features Incorporated in the Local APIC of the Pentium 4 and Intel Xeon Processors
  • 17.27. Task Switching and TSs
    • 17.27.1 P6 Family and Pentium Processor TSS
    • 17.27.2 TSS Selector Writes
    • 17.27.3 Order of Reads/Writes to the TSS
    • 17.27.4 Using A 16-Bit TSS with 32-Bit Constructs
    • 17.27.5 Differences in I/O Map Base Addresses
  • 17.28. Cache Management
    • 17.28.1 Self-Modifying Code with Cache Enabled
    • 17.28.2 Disabling the L3 Cache
  • 17.29. Paging
    • 17.29.1 Large Pages
    • 17.29.2 PCD and PWT Flags
    • 17.29.3 Enabling and Disabling Paging
  • 17.30. Stack Operations
    • 17.30.1 Selector Pushes and Pops
    • 17.30.2 Error Code Pushes
    • 17.30.3 Fault Handling Effects on the Stack
    • 17.30.4 Interlevel RET/IRET From a 16-Bit Interrupt or Call Gate
  • 17.31. Mixing 16- and 32-Bit Segments
  • 17.32. Segment and Address Wraparound
    • 17.32.1 Segment Wraparound
  • 17.33. Store Buffers and Memory Ordering
  • 17.34. Bus Locking
  • 17.35. Bus Hold
  • 17.36. Model-Specific Extensions to the IA-32
    • 17.36.1 Model-Specific Registers
    • 17.36.2 RDMSR and WRMSR Instructions
    • 17.36.3 Memory Type Range Registers
    • 17.36.4 Machine-Check Exception and Architecture
    • 17.36.5 Performance-Monitoring Counters
  • 17.37. Two Ways to Run Intel 286 Processor Tasks