Intel Computer Accessories 845 Users Manual .

2015-02-02

• Title Page
• Contents
• Revision History
• Introduction
  • Terminology and Notations
  • Reference Documents
  • Intel® 845 Chipset System Architecture
  • Intel® 82845 MCH Overview
    • System Bus Interface
    • System Bus Error Checking
    • System Memory Interface
    • AGP Interface
    • Hub Interface
    • Intel® MCH Clocking
    • System Interrupts
    • Powerdown Flow
• Signal Description
  • System Bus Signals
  • SDR SDRAM Interface Signals
    • AGP Addressing Signals
    • AGP Flow Control Signals
• Register Description
  • Register Terminology
    • Standard PCI Bus Configuration Mechanism
    • Routing Configuration Accesses
  • I/O Mapped Registers
    • CONF_ADDR—Configuration Address Register
    • CONF_DATA—Configuration Data Register
  • Memory-Mapped Register Space
    • DRAMWIDTH—DRAM Width Register
    • DQCMDSTR—Strength Control Register (SDQ and CMD Signal Groups)
    • CKESTR—Strength Control Register (SCKE Signal Group)
    • CSBSTR—Strength Control Register (SCS# Signal Group)
    • CKSTR—Strength Control Register (Clock Signal Group)
    • RCVENSTR—Strength Control Register (RCVENOUT Signal Group)
  • Host-Hub Interface Bridge Device Registers (Device 0)
    • VID—Vendor Identification Register (Device 0)
    • DID—Device Identification Register (Device 0)
    • PCICMD—PCI Command Register (Device 0)
    • PCISTS—PCI Status Register (Device 0)
    • RID—Revision Identification Register (Device 0)
    • SUBC—Sub-Class Code Register (Device 0)
    • BCC—Base Class Code Register (Device 0)
    • MLT—Master Latency Timer Register (Device 0)
    • HDR—Header Type Register (Device 0)
    • APBASE—Aperture Base Configuration Register (Device 0)
    • SVID—Subsystem Vendor Identification (Device 0)
    • SID—Subsystem Identification (Device 0)
    • CAPPTR—Capabilities Pointer (Device 0)
    • AGPM—AGP Miscellaneous Configuration Register (Device 0)
    • DRB[0:7]—DRAM Row Boundary Registers (Device 0)
    • DRA—DRAM Row Attribute Registers (Device 0)
    • DRT—DRAM Timing Register (Device 0)
    • DRC—DRAM Controller Mode Register (Device 0)
    • DERRSYN—DRAM Error Syndrome Register (Device 0)
    • EAP—Error Address Pointer Register (Device 0)
    • PAM[0:6]—Programmable Attribute Map Registers (Device 0)
    • FDHC—Fixed DRAM Hole Control Register (Device 0)
    • SMRAM—System Management RAM Control Register (Device 0)
    • ESMRAMC—Extended System Mgmt RAM Control Register (Device 0)
    • ACAPID—AGP Capability Identifier Register (Device 0)
    • AGPSTAT—AGP Status Register (Device 0)
    • AGPCMD—AGP Command Register (Device 0)
    • AGPCTRL—AGP Control Register (Device 0)
    • APSIZE—Aperture Size (Device 0)
    • ATTBASE—Aperture Translation Table Base Register (Device 0)
    • AMTT—AGP Interface Multi-Transaction Timer Register (Device 0)
    • LPTT—AGP Low Priority Transaction Timer Register (Device 0)
    • TOM—Top of Low Memory Register (Device 0)
    • MCHCFG—MCH Configuration Register (Device 0)
    • ERRSTS—Error Status Register (Device 0)
    • ERRCMD—Error Command Register (Device 0)
    • SMICMD—SMI Command Register (Device 0)
    • SCICMD—SCI Command Register (Device 0)
    • SKPD—Scratchpad Data Register (Device 0)
    • CAPID—Product Specific Capability Identifier Register (Device 0)
  • Bridge Registers (Device 1)
    • VID1—Vendor Identification Register (Device 1)
    • DID1—Device Identification Register (Device 1)
    • PCICMD1—PCI-PCI Command Register (Device 1)
    • PCISTS1—PCI-PCI Status Register (Device 1)
    • RID1—Revision Identification Register (Device 1)
    • SUBC1—Sub-Class Code Register (Device 1)
    • BCC1—Base Class Code Register (Device 1)
    • MLT1—Master Latency Timer Register (Device 1)
    • HDR1—Header Type Register (Device 1)
    • PBUSN1—Primary Bus Number Register (Device 1)
    • SBUSN1—Secondary Bus Number Register (Device 1)
    • SUBUSN1—Subordinate Bus Number Register (Device 1)
    • SMLT1—Secondary Master Latency Timer Register (Device 1)
    • IOBASE1—I/O Base Address Register (Device 1)
    • IOLIMIT1—I/O Limit Address Register (Device 1)
    • SSTS1—Secondary PCI-PCI Status Register (Device 1)
    • MBASE1—Memory Base Address Register (Device 1)
    • MLIMIT1—Memory Limit Address Register (Device 1)
    • PMBASE1—Prefetchable Memory Base Address Register (Device 1)
    • PMLIMIT1—Prefetchable Memory Limit Address Register (Device 1)
    • BCTRL1—PCI-PCI Bridge Control Register (Device 1)
    • ERRCMD1—Error Command Register (Device 1)
    • DWTC—DRAM Write Thermal Management Control Register (Device 1)
    • DRTC—DRAM Read Thermal Management Control Register (Device 1)
• System Address Map
  • Memory Address Ranges
    • VGA and MDA Memory Space
    • PAM Memory Spaces
    • ISA Hole Memory Space
    • TSEG SMM Memory Space
    • IOAPIC Memory Space
    • System Bus Interrupt APIC Memory Space
    • High SMM Memory Space
    • AGP Aperture Space (Device 0 BAR)
    • AGP Memory and Prefetchable Memory
    • Hub Interface Subtractive Decode
  • AGP Memory Address Ranges
    • AGP DRAM Graphics Aperture
  • System Management Mode (SMM) Memory Range
    • SMM Space Definition
    • SMM Space Restrictions
  • I/O Address Space
  • Intel® MCH Decode Rules and Cross-Bridge Address Mapping
    • Hub Interface Decode Rules
    • AGP Interface Decode Rules
• Functional Description
  • System Bus
    • Dynamic Bus Inversion
    • System Bus Interrupt Delivery
    • Upstream Interrupt Messages
  • System Memory Interface
    • Single Data Rate (SDR) SDRAM Interface Overview
    • Memory Organization and Configuration
      • Configuration Mechanism For DIMMs
    • Memory Address Translation and Decoding
    • DRAM Performance Description
      • Data Integrity (ECC)
  • AGP Interface Overview
    • AGP Target Operations
    • AGP Transaction Ordering
    • AGP Signal Levels
    • 4x AGP Protocol
    • Fast Writes
    • AGP FRAME# Transactions on AGP
  • Power and Thermal Management
    • Processor Power State Control
    • Sleep State Control
  • Intel® MCH Clocking
  • Intel® MCH System Reset and Power Sequencing
• Electrical Characteristics
  • Absolute Maximum Ratings
  • Power Characteristics
  • Signal Groups
  • DC Characteristics
• Ballout and Package Information
  • Package Mechanical Information
• Testability
  • XOR Test Mode Initialization
  • XOR Chains