Intel PBA31309 Bluetooth Wireless Adapter User Manual

Intel Mobile Communications Bluetooth Wireless Adapter

User Manual

User’s ManualHardware DescriptionRevision 1.2, 1-Feb-2013eUniStoneBlueMoon™ Universal Platform EmbeddedPBA 31309 Version 1.x Intel Public
The template (FrameMaker) of this document has been formally released by DOC department (IMC-DOC@intel.com).Template data: T_TechDoc.fm, Rev. 2.00, 2012-04-01.User’s Manual Intel Public 2Hardware Description Revision 1.0, 1-Feb-2013legal lines and disclaimersInformation in this document related to the Intel product or, if any, related to its use is provided in connection with Intel products. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. except as provided in agreements concluded individually or Intel’s terms and conditions of sale for such products, Intel assumes no liability whatsoever and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right.Unless otherwise agreed in writing by Intel, the Intel products are not designed nor intended for any application in which the failure of the Intel product could create a situation where personal injury or death may occur.Unless otherwise agreed upon, Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined”. Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. Unless otherwise agreed, the information here is subject to change without notice. Do not finalize a design with this information.Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.Copies of documents which have an order number and are referenced in this document, or other Intel literature, may be obtained by calling 1-800-548-4725, or go to: http://www.intel.com/#/en_US_01.Any software source code reprinted in this document is furnished under a software license and may only be used or copied in accordance with the terms of that license.This document may contain information on products in the design phase of development.Intel product numbers are not a measure of performance. Product numbers differentiate features within each product family, not across different product families.Code Names are only for use by Intel to identify products, platforms, programs, services, etc. (“products”) in development by Intel that have not been made commercially available to the public, i.e., announced, launched or shipped. They are never to be used as “commercial” names for products. Also, they are not intended to function as trademarks.SMARTI, SMARTi & Device, BlueMoon, Comneon, Comneon & Device, M-GOLD, S-GOLD, E-GOLD, A-GOLD, X-GOLD, XMM, X-PMU, XPOSYS are trademarks of Intel Corporation and related companies.Copyright © 2013, Intel Corporation. All rights reserved.*Other names and brands may be claimed as the property of others.
eUniStonePBA 31309User’s Manual Intel Public 3Hardware Description Revision 1.0, 1-Feb-2013Revision HistoryPage or Item Subjects (major changes since previous revision)Revision 1.0, 1-Feb-2013<Revision X.Y>, <yyyy-mm-dd>
eUniStonePBA 31309User’s Manual Intel Public 4Hardware Description Revision 1.0, 1-Feb-20131.0 General Device Overview........................................................................................... 81.1 Features ............................................................................................................ 81.2 Block Diagram .................................................................................................... 91.3 Pin Configuration LGA........................................................................................ 101.4 Pin Description ................................................................................................. 111.5 System Integration ........................................................................................... 131.6 SW Patch in EEPROM ......................................................................................... 142.0 Basic Operating Information ................................................................................... 152.1 Power Supply ................................................................................................... 152.2 Clocking........................................................................................................... 152.3 Low Power Modes.............................................................................................. 152.3.1 Low Power Mode .................................................................................... 152.3.2 Complete Power Down............................................................................ 152.3.3 ON/OFF ................................................................................................ 153.0 eUniStone Interfaces............................................................................................... 163.1 UART Interface ................................................................................................. 163.1.1 UART.................................................................................................... 163.1.1.1 Baud Rates .............................................................................. 163.1.1.2 Detailed UART Behavior............................................................. 173.1.1.3 UARTCTS Response Time........................................................... 183.2 Low Power Control ............................................................................................ 184.0 General Device Capabilities ..................................................................................... 194.1 RF Test Application............................................................................................ 194.2 Firmware ROM Patching ..................................................................................... 194.2.1 Patch Support........................................................................................ 195.0 Bluetooth Capabilities ............................................................................................. 205.1 Supported Features........................................................................................... 205.2 eUniStone Bluetooth Features............................................................................. 205.2.1 Secure Simple Paining ............................................................................ 205.2.2 Role Switch ........................................................................................... 205.2.3 Sniff Mode ............................................................................................ 215.2.4 Sniff Subrating ...................................................................................... 215.2.5 Enhanced Power Control ......................................................................... 215.2.6 Encryption Pause and Resume ................................................................. 216.0 Electrical Characteristics ......................................................................................... 226.1 Absolute Maximum Ratings................................................................................. 226.2 Operating Conditions ......................................................................................... 226.3 DC Characteristics............................................................................................. 236.3.1 Pad Driver and Input Stages.................................................................... 236.3.2 Pull-ups and Pull-downs .......................................................................... 256.3.3 Protection Circuits .................................................................................. 256.3.4 System Power Consumption .................................................................... 266.4 RF Part ............................................................................................................ 266.4.1 Characteristics RF Part............................................................................ 266.4.1.1 Bluetooth Related Specifications ................................................. 267.0 Package Information............................................................................................... 297.1 Package Marking............................................................................................... 297.2 Production Package ........................................................................................... 307.2.1 Pin Mark ............................................................................................... 308.0 Bluetooth Qualification and Regulatory Certification ............................................... 31Contents
eUniStonePBA 31309User’s Manual Intel Public 5Hardware Description Revision 1.0, 1-Feb-20138.1 Reference Design .............................................................................................. 318.2 FCC Class B Digital Devices Regulatory Notice....................................................... 328.3 FCC Wireless Notice........................................................................................... 328.4 FCC Interference Statement ............................................................................... 338.5 FCC Identifier ................................................................................................... 338.6 European R&TTE Declaration of Conformity........................................................... 348.7 Bluetooth Qualified Design ID ............................................................................. 368.8 Industry Canada Certification.............................................................................. 368.9 Label Design of the Host Product......................................................................... 368.10 Regulatory Test House....................................................................................... 369.0 Assembly Guidelines ............................................................................................... 379.1 General Description of the Module ....................................................................... 379.2 Printed Circuit Board Design ............................................................................... 389.3 Solder Paste Printing ......................................................................................... 399.4 Assembly ......................................................................................................... 399.4.1 Component Placement ............................................................................ 399.4.2 Pin Mark ............................................................................................... 399.4.3 Package................................................................................................ 409.5 Soldering Profile................................................................................................ 419.6 Rework........................................................................................................... 429.6.1 Removal Procedure ............................................................................... 429.6.2 Replacement Procedure .......................................................................... 429.6.2.1 Alternative 1: Dispensing Solder................................................. 429.6.2.2 Alternative 2: Printing Solder ..................................................... 439.7 Inspection........................................................................................................ 439.8 Component Salvage .......................................................................................... 449.9 Voids in the Solder Joints ................................................................................... 449.9.1 Expected Void Content and Reliability ....................................................... 449.9.2 Parameters with an Impact on Voiding ...................................................... 45
eUniStonePBA 31309User’s Manual Intel Public 6Hardware Description Revision 1.0, 1-Feb-20131 Simplified Block Diagram of eUniStone ......................................................................... 92 Pin Configuration for eUniStone in Top View (footprint) ................................................. 103 System Architecture Example with eUniStone .............................................................. 134 UART Interface........................................................................................................ 165 UARTCTS Response Time .......................................................................................... 186 Package Marking...................................................................................................... 297 Production Package.................................................................................................. 308 Top View and Bottom View........................................................................................ 309 Reference Design Schematics .................................................................................... 3110 Cutout Drawing ....................................................................................................... 3311 Equipment Label...................................................................................................... 3412 Declaration of Conformity ......................................................................................... 3513 Pad Layout on the Module (top view).......................................................................... 3714 Cutout Drawing ....................................................................................................... 3815 Pin Marking............................................................................................................. 3916 Tape on Reel........................................................................................................... 4017 Eutectic Lead-Solder Profile....................................................................................... 4118 Eutectic Leadfree-Solder Profile ................................................................................. 4119 Solder Printing ........................................................................................................ 4320 X-ray Picture Showing Voids Conforming to IPC-A-610D................................................ 44Figures
eUniStonePBA 31309User’s Manual Intel Public 7Hardware Description Revision 1.0, 1-Feb-20131 Pin Description ....................................................................................................... 112 UART Baud Rates .................................................................................................... 173 Default (non-inverted) behavior of UART signals ......................................................... 174 Absolute Maximum Ratings ...................................................................................... 225 Operating Conditions ............................................................................................... 226 Internal1 (1.5 V) Supplied Pins ................................................................................. 237 Internal2 (2.5 V) Supplied Pins ................................................................................. 238 VDDUART Supplied Pins ........................................................................................... 249 VDD1 Supplied Pins ................................................................................................. 2410 ONOFF PIN ............................................................................................................ 2411 Pull-up and Pull-down Currents ................................................................................. 2512 Max. Load at the Different Supply Voltages ................................................................ 2613 BDR - Transmitter Part ............................................................................................ 2614 BDR -Receiver Part ................................................................................................. 2715 EDR - Transmitter Part ............................................................................................ 2716 EDR -Receiver Part .................................................................................................. 28Tables
eUniStonePBA 31309General Device OverviewUser’s Manual Intel Public 8Hardware Description Revision 1.0, 1-Feb-20131.0 General Device Overview1.1 FeaturesGeneral• Complete Bluetooth 2.1 + EDR solution• Implements a single point-to-point data link to other SPP capable Bluetooth devices• Ultra low power design in 0.13 µm CMOS• Temperature range from -40°C to +85°C• Integrates ARM7TDMI, RAM and patchable ROM• On-module voltage regulators. External supply 2.9 - 4.1 V• On-module EEPROM with configuration data• On-module tuned reference clock• Module can enter low power mode in idle state and during sniff intervalsInterfaces• AT command interface over UART with HW flow control• Default UART baudrate 115200 bit/s• Module configuration reprogrammable for 9600 bit/s up to 3.25 Mbit/s UART baudrate• JTAG for boundary scan in production testRF• Class 2 device up to +4 dBm• Receiver sensitivity typ. -86 dBm• Integrated antenna, balun and ISM band filter• Integrated LNA with excellent blocking and intermodulation performance• Digital demodulation for optimum sensitivity and co-/adjacent channel performance
eUniStonePBA 31309General Device OverviewUser’s Manual Intel Public 9Hardware Description Revision 1.0, 1-Feb-2013Bluetooth• Bluetooth V2.1 + EDR compliant• Secure Simple Pairing• Device A (initiating link) or Device B (accepting link) role supported• Single point-to-point data link, role switch supported• Packet data mode and stream data mode supported• Sniff mode and Sniff Subrating is supported with above capabilities• 5 trusted devices stored in EEPROM• SW version available to configure specific RF certification tests1.2 Block DiagramFigure 1. Simplified Block Diagram of eUniStoneeUnistone_ Block_ Diagram.vsdeUniStonePMB8754BlueMoon UniCellularEEPROMVoltage RegulatorCrystal26 MHzBalun FilterI2CVsupplyGPIOUARTVDD_UARTVDD1
eUniStonePBA 31309General Device OverviewUser’s Manual Intel Public 10Hardware Description Revision 1.0, 1-Feb-20131.3 Pin Configuration LGAFigure 2. Pin Configuration for eUniStone in Top View (footprint)PBA31309_Pinout.vsdF1VSSF2P1.2TDIF3P0.11F4LPMinP0.14F5UARTCTSF6VDDUARTF7UARTTXDF8UARTRTSF9VSS F11VSSF12VSSE1P0.12SDA0E2P013SCL0E3P1.3TDOE4LPMoutP0.0E5P0.1E6UARTRXDE7(NC)E8VSSE9VSSD1P0.10D2P0.8D3P1.1TCKD4P0.3D5P0.2D6(NC)D7VSSD8VSSD9(NC)C1VREGC2P0.9C3JTAG #C4TRST#C5VDD1C6(NC)C7(NC)C8VSSC9VSSB1P1.7B2P1.8B3P1.0TMSB4P1.4RTCKB5ONOFFB6(NC)B7(NC)B8(NC)B9P0.15A2P1.6A3RESET#A4VSUPPLYA6VSUPPLYA7VSSA8P1.5A9VSS A11VSSA12VSSA1VSSTop ViewA5VSUPPLY
eUniStonePBA 31309General Device OverviewUser’s Manual Intel Public 11Hardware Description Revision 1.0, 1-Feb-20131.4 Pin DescriptionThe non-shaded cells indicate pins that will be fixed for the product lifetime. Shaded cells indicate that the pin might be removed/changed in future variants. Pins not listed below shall not be connected.Table 1. Pin DescriptionPin No. Symbol Input / Output Supply Voltage During Reset After Reset FunctionA2 P1.6 I/O/OD Internal1 Z Z Port 1.6A3 RESET# AI Internal1 Input Input Hardware ResetA8 P1.5 I/O/OD Internal1 Input Input Port 1.5B1 P1.7 I/O/OD Internal1 PD/ Input PD/ Input Port 1.7B2 P1.8 I/O/OD Internal1 PD PD Port 1.8B3 P1.0 /TMS I/O/OD Internal2 PU1PU1. Port 1.0 orJTAG interfaceB4 P1.4 /RTCK I/O/OD Internal2 ZZPort 1.4 orJTAG interfaceB5 ONOFF I --Turns off module completelyB9 P0.15 I/O VDDUART PD H Port 0.15C2 P0.9 I/O/OD Internal2 ZZPort 0.9C3 JTAG# IInternal2 PU PU Mode selection Port 1:0: JTAG1: PortC4 TRST# IInternal2 PD PD JTAG interfaceD1 P0.10 I/O/OD Internal2 ZZPort 0.10D2 P0.8 I/O/OD Internal2 PD PD Port 0.8D3 P1.1 /TCK I/O/OD Internal2 PU1. PU1. Port 1.1 orJTAG interfaceD4 P0.3 I/O/OD VDD1 Conf.PD def. Conf.PD def. Port 0.3D5 P0.2 I/O/OD VDD1 Z Z Port 0.2E1 P0.12 / SDA0 I/O/OD Internal2 PU PU I2C data signalE2 P0.13 / SCL0 I/O/OD Internal2 PU PU I2C clock signalE3 P1.3 /TDO I/O/OD Internal2 Z Z Port 1.3 orJTAG interfaceE4 P0.0 LPMout I/O/OD VDD1 PD PD Port 0.0LPM wakeup outputE5 P0.1 I/O/OD VDD1 PD PD Port 0.1E6 P0.5 /UARTRXD I/O/OD VDDUART Z Z Port 0.5 orUART receive dataF2 P1.2 /TDI I/O/OD Internal2 PU1. PU1. Port 1.2 orJTAG interfaceF3 P0.11 I/O/OD Internal2 Z Z Port 0.11F4 P0.14 LPMin I/O VDDUART ZZPort 0.14LPM wakup inputF5 P0.7 /UARTCTS I/O/OD VDDUART Z Z Port 0.7 orUART CTS flow controlF7 P0.4 /UARTTXD I/O/OD VDDUART PU PU Port 0.4 orUART transmit dataF8 P0.6 /UARTRTS I/O/OD VDDUART PU PU Port 0.6 orUART RTS flow controlA4, A5, A6VSUPPLY SI - - Power supplyC1VREG SO --Regulated Power supplyF6 VDDUART SI - - UART interface Power supplyC5 VDD1 SI - - Power supply
eUniStonePBA 31309General Device OverviewUser’s Manual Intel Public 12Hardware Description Revision 1.0, 1-Feb-2013Descriptions of acronyms used in the pin list:A1, A7, A9, A11, A12, C8, C9, D7, D8, E8, E9, F1, F9, F11, F12VSS --GroundB6, B7, B8, C6, C7, D6, D9, E7NC - - - - No connection1. Fixed pull-up/pull-down if JTAG interface is selected, not affected by any chip reset. If JTAG interface is not selected the port is tristate.Table 1. Pin Description (Continued)Pin No. Symbol Input / Output Supply Voltage During Reset After Reset FunctionAcronym DescriptionI InputOOutputOD Output with open drain capabilityZTristatePU Pull-upPD Pull-downA Analog (e.g. AI means analog input)S Supply (e.g. SO means supply output)
eUniStonePBA 31309General Device OverviewUser’s Manual Intel Public 13Hardware Description Revision 1.0, 1-Feb-20131.5 System IntegrationeUniStone is optimized for a low bill of material (BOM) and a small PCB size. Figure 3 shows a typical application example.Figure 3. System Architecture Example with eUniStoneSystem_Architecture.vsdBT BasebandBT StackRFCOMMAPIBT RFOscillatorHOSTI2CBALUNRESETAntennaSPP(Serial Port Profile)AT interfaceUARTcommandButtons,LedsEEPROMVoltageRegulatorVSUPPLYGPIOConfiguration , SW patchLPM
eUniStonePBA 31309General Device OverviewUser’s Manual Intel Public 14Hardware Description Revision 1.0, 1-Feb-2013The UART interface is used for communication between the host and eUniStone. The lines UARTTXD and UARTRXD are used for commands, events and data. The lines UARTRTS and UARTCTS are used for hardware flow control.Low power mode control of eUniStone and the host can be implemented in by using the pins P0.14 and P0.0. P0.14 is used by the host to allow eUniStone to enter low power mode and P0.0 is used by eUniStone to wake-up the host when attention is required. To save current in idle mode, the host could hardware reset the module using the RESET#.Power is supplied to a single VSUPPLY input from which internal regulators can generate all required voltages. The UART and the GPIO’s interfaces have separate supply voltages so that they can comply with host signaling.1.6 SW Patch in EEPROMBugfixes for the SW in ROM are downloaded from the EEPROM. Intel may include new bugfixes in EEPROM during product lifetime..
eUniStonePBA 31309Basic Operating InformationUser’s Manual Intel Public 15Hardware Description Revision 1.0, 1-Feb-20132.0 Basic Operating Information2.1 Power SupplyeUniStone is supplied from a single supply voltage VSUPPLY. This supply voltage must always be present. The Bluetooth chip is supplied from an internally generated 2.5 V supply voltage. This voltage can be accessed from the VREG pin. This voltage shall not be used for supplying other components in the host system but can be used for referencing the host interfaces.The GPIO’s and the UART interface are supplied with dedicated, independent, reference levels via the VDD1 and VDDUART pins. All other digital I/O pins are supplied internally by either 2.5 V (Internal2) or 1.5 V (Internal1). Section 1.4 provides a mapping between pins and supply voltages.The I/O power domains (VDD1 and VDDUART) are completely separated from the other power domains and can stay present also in low power modes.2.2 ClockingeUniStone contains a crystal from which the internal 26 MHz system clock is generated. Also, the low power mode clock of 32.768 kHz is generated internally, which means that no external clock is needed. 2.3 Low Power ModesTo minimize current consumption, eUniStone automatically switches between different low power modes. The major modes are described below.2.3.1 Low Power ModeIn Low Power Mode (LPM) most parts of eUniStone are powered down. This is done automatically in idle mode or if the link is in Sniff mode and the host allows LPM with the pin P0.14.2.3.2 Complete Power DownIf Bluetooth functionality is not needed at all, VSUPPLY should be grounded to minimize power consumption. In this state there is no activity in eUniStone and the Bluetooth state (native clock, etc.) is not updated.2.3.3 ON/OFFeUniStone provides an alternative way to power down using the ONOFF logic input. When the ONOFF is low, the internal regulator on the module is turned OFF. The intention with the signal is to have the possibility to turn off the module without having to turn off the supply voltage. In the OFF state, the module will consume less than 1 mA excluding the interface currents that is mainly set by the external load. If this signal isn’t used then it should be connected to VSUPPLY on the host PCB.
eUniStonePBA 31309eUniStone InterfacesUser’s Manual Intel Public 16Hardware Description Revision 1.0, 1-Feb-20133.0 eUniStone Interfaces3.1 UART InterfaceThe UART interface is the main communication interface between the host and eUniStone. AT commands are described in detail in the AT Commands specification [1].The interface consists of four UART signals and two LPM control signals as shown in Figure 4.Figure 4. UART Interface3.1.1 UARTThe lines UARTTXD and UARTRXD are used for commands, responses and data. The lines UARTRTS and UARTCTS are used for hardware flow control. A separate supply voltage, VDDUART, defines the UART reference levels to fit any system requirements.3.1.1.1 Baud RatesThe UART baud rate can be configured with the BD_DATA parameter UART_Baudrate. The module is programmed for a default baudrate of 115200 baud. Reprogramming of the EEPROM configuration is possible by AT commands at manufacturing time of the end product. The baudrate written to EEPROM will be used each time eUniStone starts or, HW or SW reset is done.The host is also able to change the baudrate temporarily with an AT command. This baudrate is used by eUniStone until a HW or SW reset is done, when it will change back to the baudrate stored in the EEPROM.eUnistone_UART_Interface.vsdUARTTXDUARTRXDUARTRTSUARTCTSWAKEUP_BTWAKEUP_HOSTUARTTXDUARTRXDUARTRTSUARTCTSP0.14 inputP0.0 outputHost eUniStone
eUniStonePBA 31309eUniStone InterfacesUser’s Manual Intel Public 17Hardware Description Revision 1.0, 1-Feb-2013Table 2 shows the UART baudrates supported.3.1.1.2 Detailed UART BehaviorAfter reset the UART interface is configured with one start bit, eight data bits, no parity bit and one stop bit. The least significant bit is transmitted first.The polarity of the UART signals can be changed with the BD_DATA parameter UART_Invert. The default (non-inverted) behavior is shown in Table 3Table 2. UART Baud RatesStandard Baud Rate Module Baud Rate Deviation in %9600 9615 0.1619200 19230 0.1638400 38461 0.1657600 57522 -0.14115200 115044 -0.14230400 230088 -0.14460800 464285 0.76921600 928571 0.761843200 1857142 0.763250000 3250000 0Table 3. Default (non-inverted) behavior of UART signalsSignal Level MeaningUARTTXD / UARTRXD 0 Start bit, ’0’ bit in character.1 Idle level, stop bitUARTRTS / UARTCTS 0 Flow on1Flow stopped
eUniStonePBA 31309eUniStone InterfacesUser’s Manual Intel Public 18Hardware Description Revision 1.0, 1-Feb-20133.1.1.3 UARTCTS Response TimeFigure 5 shows the UARTCTS response time. Assuming non-inverted UART signals, the data flow stops within the “flow off response time” after UARTCTS has been set to high. If UARTCTS goes high during the transmission of a byte (phase 1 in the figure) this byte will be completely transmitted. While UARTCTS is high, no data will be transmitted (phase 2). When UARTCTS goes low again, data transmission will continue (phase 3).The maximum flow off response time is 10 UART bits (including start and stop bits). As an example, if the UART baud rate is 115200 Baud, the maximum flow off response time is 10 x 1/115200 s = 87 µs.Figure 5. UARTCTS Response Time3.2 Low Power ControlPin P0.14 and P0.0 are optional, but strongly recommended to be used. P0.14 is used to allow eUniStone to enter Low Power Mode (LPM). P0.0 is used by eUniStone when in LPM to wake up the host.HCI_UARTCTS_Response_Time.vsdUARTCTSUARTTXDbit0bit1bit2bit3bit4bit5bit6bit7startstopbit0start...phase 1phase 2phase 3flow offresponsetimemax. flow off responsetime
eUniStonePBA 31309General Device CapabilitiesUser’s Manual Intel Public 19Hardware Description Revision 1.0, 1-Feb-20134.0 General Device CapabilitiesThis chapter describes features available in the eUniStone (PBA 31309).Actual feature set and how to access the features can be found in the AT Command document [1]. Release specific performance characteristics, data throughput and current consumption are listed in the SW Release Notes [2].4.1 RF Test ApplicationThe eUniStone module can be programmed over UART with a specific application for RF test purposes, e.g. TX continuous or TX burst mode. This test application is controlled over the UART through Intel specific HCI commands. The commands supported by this test application are described in the document “T8753-2-Intel_Specific_HCI_Commands-7600.pdf”.4.2 Firmware ROM PatchingIn any chip with complex firmware in ROM it is wise to support patching. The risk of project delay is significantly reduced when problems can be solved without hardware changes. Enhancements, adaptations and bug fixes can be handled very late during design-in, even after the chip has been soldered in the final product.The well-proven patch concept used in BlueMoon UniCellular is described below.4.2.1 Patch SupportThe Bluetooth chip contains dedicated hardware that makes it possible to apply patches to the code and data in the firmware ROM. The hardware is capable of replacing up to 32 blocks of 16 bytes each with new content. This area can be filled with any combination of code and data. The firmware patch is stored in EEPROM and automatically loaded after startup. This provides a flexible bugfix solution for the software in ROM.
eUniStonePBA 31309Bluetooth CapabilitiesUser’s Manual Intel Public 20Hardware Description Revision 1.0, 1-Feb-20135.0 Bluetooth Capabilities5.1 Supported Features• Bluetooth V2.1 + EDR compliant• Enhanced Data Rate 2 and 3 Mbit/s symbol rate on the air• Secure Simple Pairing• Device A (initiating link) or Device B (accepting link) role supported• Single point-to-point data link, role switch supported• Packet data mode and stream data mode supported• Link in sniff mode supported. Device enters Low Power Mode in sniff intervals if permitted by the host.• Sniff Subrating• 5 trusted devices stored in EEPROM• Connection to a Bluetooth Tester5.2 eUniStone Bluetooth Features5.2.1 Secure Simple PainingThe device implements Secure Simple Pairing with the following association models according to BT2.1 core specification:• Numeric Comparisoon•Just Works• Passkey EntryAlso pairing with legacy (BT2.0 and older) devices is supported.5.2.2 Role SwitchThe initiating device (devA) starts as Bluetooth master of the link, the accepting device starts as Bluetooth slave of the link. The remote device can request a role change to accomodate with other Bluetooth links. If that happens, the module will send an event to the host. Also if the eUniStone start as slave, (Device B), the other device can change it's own role making eUniStone master. The host controlling eUniStone will be notified with the same event.
eUniStonePBA 31309Bluetooth CapabilitiesUser’s Manual Intel Public 21Hardware Description Revision 1.0, 1-Feb-20135.2.3 Sniff ModeThe local host or the remote device can request sniff mode for the link. During sniff mode, the devices synchronize on sniff instants only. The module will enter low power mode in the sniff intervals, if allowed by the host LPM control signals. Data packets can be exchanged at the sniff instants only, so the data rate is reduced in sniff mode. The module will wake up the host when data is received or other responses need to be transmitted.5.2.4 Sniff SubratingThe local host or the remote device can request Sniff Subrating for the link. When in sniff mode, the device will automatically switch between Sniff Mode and Sniff Subrating Mode making it possible to stay longer in Low Power Mode when there is no data transmitted or received.5.2.5 Enhanced Power ControleUniStone support Enhanced Power Control according to Bluetooth specification 3.0. The Enhanced Power Control is handled automatically to make different modulations modes transmit on optimal levels.5.2.6 Encryption Pause and ResumeEncryption Pause Resume is supported making it possible to change connection link key on an encrypted link, pause the encryption and resume it with the new link key. This is handled automatically by eUniStone to make the link more secure.
eUniStonePBA 31309Electrical CharacteristicsUser’s Manual Intel Public 22Hardware Description Revision 1.0, 1-Feb-20136.0 Electrical Characteristics6.1 Absolute Maximum RatingsNote: Stresses above those listed here are likely to cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Maximum ratings are absolute ratings; exceeding only one of these values may cause irreversible damage to the integrated circuit.Maximum ratings are not operating conditions.6.2 Operating ConditionsTable 4. Absolute Maximum RatingsParameter Symbol Values Unit Note / Test ConditionMin. Typ. Max.Storage temperature -40 – 125 °C –VSUPPLY supply voltage -0.3 – 6.0 V –VDDUART supply voltage -0.9 – 4.0 V –VDD1 supply voltage -0.9 – 4.0 V –VREG -0.3 – 4.0 V VSUPPLY > 4 VVREG -0.3 – VSUPPLY V VSUPPLY < 4 VONOFF -0.3 – VSUPPLY+0.3 VInput voltage range -0.9 – 4.0 V –Output voltage range -0.9 – 4.0 V -9ESD – – 1.0 kV According to MIL-STD883D method 3015.7Table 5. Operating ConditionsParameter Symbol Values Unit Note / Test ConditionMin. Typ. Max.Operating temperature -40 – 85 °C –Main supply voltage (Vsupply) 2.9 – 4.111. At ambient temperatures above 65oC the maximum allowed power dissipation in the module is limited to 200 mWV–VDDUART 1.35 – 3.6 V –VDD1 1.35 – 3.6 V –
eUniStonePBA 31309Electrical CharacteristicsUser’s Manual Intel Public 23Hardware Description Revision 1.0, 1-Feb-20136.3 DC Characteristics6.3.1 Pad Driver and Input StagesFor more information, see Chapter 1.4.Table 6. Internal1 (1.5 V) Supplied PinsParameter Symbol Values Unit Note / Test ConditionMin. Typ. Max.Input low voltage -0.3 – 0.27 V –Input high voltage 1.15 – 3.6 V –Output low voltage – – 0.25 V IOL = 1 mAOutput high voltage 1.1 – – V IOH = -1 mAContinuous Load11. The total continuous load for all Internal1 supplied pins shall not exceed 2 mA at the same time––1mA–Pin Capacitance – – 10 pF –Magnitude Pin Leakage – 0.01 1 µA Input and output drivers disabledTable 7. Internal2 (2.5 V) Supplied PinsParameter Symbol Values Unit Note / Test ConditionMin. Typ. Max.Input low voltage -0.3 – 0.45 V –Input high voltage 1.93 – 2.8 V P0.10Input high voltage 1.93 – 3.6 V Other pinsOutput low voltage – – 0.25 V IOL = 5 mAOutput low voltage – – 0.15 V IOL = 2 mAOutput high voltage 2.0 – – V IOH = -5 mAOutput high voltage 2.1 – – V IOH = -2 mAContinuous Load11. The total continuous load for all Internal2 supplied pins shall not exceed 35 mA at the same time––5mA–Pin Capacitance – – 10 pF –Magnitude Pin Leakage – 0.01 1 µA Input and output drivers disabled
eUniStonePBA 31309Electrical CharacteristicsUser’s Manual Intel Public 24Hardware Description Revision 1.0, 1-Feb-2013Table 8. VDDUART Supplied PinsParameter Symbol Values Unit Note / Test ConditionMin. Typ. Max.Input low voltage -0.3 – 0.2*VDDUART V –Input high voltage 0.7*VDDUART – VDDUART+0.3 V P0.5/UARTRXDInput high voltage 0.7*VDDUART – 3.6 V Other pinsOutput low voltage – – 0.25 V IOL = 5 mAVDDUART = 2.5 VOutput low voltage – – 0.15 V IOL = 2 mAVDDUART = 2.5 VOutput high voltage VDDUART-0.25 –– VIOH=-5mAVDDUART = 2.5 VOutput high voltage VDDUART-0.15 –– VIOH=-2mAVDDUART = 2.5 VContinuous Load11. The total continuous load for all VDDUART supplied pins shall not exceed 35 mA at the same time––5 mA–Pin Capacitance – – 10 pF –Magnitude Pin Leakage – 0.01 1 µA Input and output drivers disabledTable 9. VDD1 Supplied PinsParameter Symbol Values Unit Note / Test ConditionMin. Typ. Max.Input low voltage -0.3 – 0.2*VDD1 V –Input high voltage 0.7*VDD1 – 3.6 V –Output low voltage – – 0.25 V IOL = 5 mAVDD1 = 2.5 VOutput low voltage – – 0.15 V IOL = 2 mAVDD1 = 2.5 VOutput high voltage VDD1-0.25 –– VIOH=-5mAVDD1 = 2.5 VOutput high voltage VDD1-0.15 –– VIOH=-2mAVDD1 = 2.5 VContinuous Load11. The total continuous load for all VDD1 supplied pins shall not exceed 35 mA at the same time––5 mA–Pin Capacitance – – 10 pF –Magnitude Pin Leakage – 0.01 1 µA Input and output drivers disabledTable 10. ONOFF PINParameter Symbol Values Unit Note / Test ConditionMin. Typ. Max.Input low voltage – – 0.7 V –Input high voltage 1.7 – VSUPPLY V –Input current -1 0.01 1 µA ONOFF = 0 V
eUniStonePBA 31309Electrical CharacteristicsUser’s Manual Intel Public 25Hardware Description Revision 1.0, 1-Feb-20136.3.2 Pull-ups and Pull-downs6.3.3 Protection CircuitsAll pins have an inverse protection diode against VSS. P0.10 has an inverse diode against Internal2.P0.5/UARTRXD has an inverse diode against VDDUART.All other pins have no diode against their supply.Table 11. Pull-up and Pull-down CurrentsPin Pull Up Current Pull Down Current Unit ConditionsMin. Typ. Max. Min. Typ. Max.P0.12P0.13 260 740 1300 N/A N/A N/A µA Pull-up current measured with pin voltage = 0 VPull-down current measured with pin voltage = supply voltageMin measured at 125°C with supply = 1.35 VTyp. measured at 27°C with supply = 2.5VMax measured at -40°C with supply = 3.63 VP0.0P0.1P0.2P0.322 130 350 23 150 380 µAP0.4P0.5P0.6P0.7P0.10P0.8P0.9P0.11P0.14P0.154.2 24 68 3.0 20 55 µAP1.0P1.1P1.2P1.3P1.4P1.5P1.6P1.7P1.81.1 6.0 17 0.75 5.0 14 µA
eUniStonePBA 31309Electrical CharacteristicsUser’s Manual Intel Public 26Hardware Description Revision 1.0, 1-Feb-20136.3.4 System Power ConsumptionNote: I/O currents are not included since they depend mainly on external loads. For more details see [2].6.4 RF Part6.4.1 Characteristics RF PartThe characteristics involve the spread of values to be within the specific temperature range. Typical characteristics are the median of the production.All values refers to Intel reference design.6.4.1.1 Bluetooth Related SpecificationsTable 12. Max. Load at the Different Supply VoltagesParameter Symbol Values Unit Note / Test ConditionMin. Typ. Max.Vsupply – – 100 mA Peak currentTable 13. BDR - Transmitter PartParameter Symbol Values Unit Note / Test ConditionMin. Typ. Max.Output power (high gain) 0.5 2.5 4.5 dBm Default settingsOutput power (highest gain) – 4.5 – dBm Maximum settingsPower control step size 4 6 8 dB –Frequency range fL 2400 2401.3 – MHz –Frequency range fH – 2480.7 2483.5 MHz –20 dB bandwidth – 0.930 1 MHz –2nd adjacent channel power – -40 -20 dBm –3rd adjacent channel power – -60 -40 dBm –>3rd adjacent channel power – -64 -40 dBm Max. 2 of 3 exceptions @ 52 MHz offset might be usedAverage modulation deviation for 00001111 sequence 140 156 175 kHz –Minimum modulation deviation for 01010101 sequence 115 145 – kHz –Ratio Deviation 01010101 / Deviation 00001111 0.8 1 – –Initial carrier frequency tolerance |foffset| –– 75 kHz –Carrier frequency drift (one slot) |fdrift| –1025 kHz –Carrier frequency drift (three slots) |fdrift| –1040 kHz –Carrier frequency drift (five slots) |fdrift| –1040 kHz –Carrier frequency driftrate (one slot) |fdriftrate| – 5 20 kHz/50 ms –
eUniStonePBA 31309Electrical CharacteristicsUser’s Manual Intel Public 27Hardware Description Revision 1.0, 1-Feb-2013Carrier frequency driftrate (three slots) |fdriftrate| – 5 20 kHz/50 ms –Carrier frequency driftrate (five slots) |fdriftrate| – 5 20 kHz/50 ms –Table 14. BDR -Receiver PartParameter Symbol Values Unit Note / Test ConditionMin. Typ. Max.Sensitivity – -86 -81 dBm Ideal wanted signalC/I-performance: -4th adjacent channel –-51-40dB –C/I-performance: -3rd adjacent channel (1st adj. of image)–-46-20dB –C/I-performance: -2nd adjacent channel (image) –-35-9 dB –C/I-performance: -1st adjacent channel –-40 dB –C/I-performance: co. channel – 9 11 dB –C/I-performance: +1st adjacent channel –-40 dB –C/I-performance: +2nd adjacent channel –-40-30dB –C/I-performance: +3rd adjacent channel –-50-40dB –Blocking performance 30 MHz - 2 GHz 10 – – dBm Some spurious responses, but according to BT-specificationBlocking performance 2GHz-2.4GHz -27 – – dBm –Blocking performance 2.5 GHz - 3 GHz -27 – – dBm –Blocking performance 3 GHz - 12.75 GHz 10 – – dBm Some spurious responses, but according to BT-specificationIntermodulation performance -39 -34 – dBm Valid for all intermodulation testsMaximum input level -20 – – dBm –Table 15. EDR - Transmitter PartParameter Symbol Values Unit Note / Test ConditionMin. Typ. Max.Output power (high gain) -2.5 – 2 dBmRelative transmit power: PxPSK - PGFSK -4 -0.6 1 dBCarrier frequency stability |ωi| – – 75 kHz –Carrier frequency stability |ωi+ω0| – – 75 kHz –Carrier frequency stability |ω0| – 2 10 kHz –DPSK - RMS DEVM – 10 20 % –8DPSK - RMS DEVM – 10 13 % –DPSK - Peak DEVM – 20 35 % –8DPSK - Peak DEVM – 20 25 % –DPSK - 99% DEVM – – 30 % –8DPSK - 99% DEVM – – 20 % –Differential phase encoding 99 100 – % –Table 13. BDR - Transmitter Part (Continued)Parameter Symbol Values Unit Note / Test ConditionMin. Typ. Max.
eUniStonePBA 31309Electrical CharacteristicsUser’s Manual Intel Public 28Hardware Description Revision 1.0, 1-Feb-20131st adjacent channel power – -40 -26 dBc –2nd adjacent channel power – – -20 dBm Carrier power measured at basic rate3rd adjacent channel power – – -40 dBm Carrier power measured at basic rateTable 16. EDR -Receiver PartParameter Symbol Values Unit Note / Test ConditionMin. Typ. Max.DQPSK-Sensitivity – -88 -83 dBm Ideal wanted signal8DPSK-Sensitivityl – -83 -77 dBm Ideal wanted signalDQPSK - BER Floor Sensitivity – -84 -60 dBm –8DPSK - BER Floor Sensitivity – -79 -60 dBm –DQPSK - C/I-performance:-4th adjacent channel –-53-40dB –DQPSK - C/I-performance:-3rd adjacent channel (1st adj. of image) –-47-20dB –DQPSK - C/I-performance:-2nd adjacent channel (image) –-31-7 dB –DQPSK - C/I-performance:-1st adjacent channel –-70 dB –DQPSK - C/I-performance:co. channel –1113 dB –DQPSK - C/I-performance:+1st adjacent channel –-90 dB –DQPSK - C/I-performance:+2nd adjacent channel –-44-30dB –DQPSK - C/I-performance:+3rd adjacent channel –-50-40dB –8DPSK - C/I-performance:-4th adjacent channel –-48-33dB –8DPSK - C/I-performance:-3rd adjacent channel (1st adj. of image) –-44-13dB –8DPSK - C/I-performance:-2nd adjacent channel (image) –-250 dB –8DPSK - C/I-performance:-1st adjacent channel –-55 dB –8DPSK - C/I-performance:co. channel –1721 dB –8DPSK - C/I-performance:+1st adjacent channel –-55 dB –8DPSK - C/I-performance:+2nd adjacent channel –-36-25dB –8DPSK - C/I-performance:+3rd adjacent channel –-46-33dB –Maximum input level -20 – – dBm –Table 15. EDR - Transmitter Part (Continued)Parameter Symbol Values Unit Note / Test ConditionMin. Typ. Max.
eUniStonePBA 31309Package InformationUser’s Manual Intel Public 29Hardware Description Revision 1.0, 1-Feb-20137.0 Package Information7.1 Package MarkingFigure 6. Package MarkingPackage_Marking.vsdVersionProduct IDFCC ID Machine readable2D bar codeIntel usage only , could be changed without any noticeCase PCBi intelCGYYWW/DFYWW9EXXPD9PBA313309PBA31309 V1.00Date codeYYWWFYWW9EXX- calendar Year (2digits) + calendar week (2digits) of production- lot code starts with F- last digit of assembly year (2013)- assembly week = calendar week + 1- final test ID + assembly site ID- unique lot sequential number 00-09,0A-0Z,10, …, ZZP B A 3 1 3 0 9 V 1 . 0 0G Y Y W W / D F Y W W 9 E X XF C C I D : Q 2 3 3 1 3 0 8Example of markingMarking definition
eUniStonePBA 31309Package InformationUser’s Manual Intel Public 30Hardware Description Revision 1.0, 1-Feb-20137.2 Production PackageFigure 7. Production PackageAll dimensions are in mm.Tolerances on all outer dimensions, height, width and length, are +/- 0.2 mm.7.2.1 Pin MarkPin 1 (A1) is marked on bottom footprint and on the top of the shield on the module according to Figure 8. Diameter of pin 1 mark on the shield is 0.40 mm.Figure 8. Top View and Bottom View121011_ PAN1322_V1.0.vsd1,561,800,6015,608,70To l era nce s: + -0. 2mmi intelGYYWW /D FYWW9EXXPD9PBA31309PBA31309 V1.00Top_and_Bottom_Views.vsdPin 1 marking bottom sideF2F3F4F5F6E1E2E3E4E5E6E7E8E9D1D2D3D4D5D6D7D8C1C2C3C4C5C6C7C8B1B2B3B4B5B6B7B8B9A2A3A4A5A6A7A8 A1F9 F7 F1F8D9C9A9Pin 1 marking top sideA11F12 F11A12
eUniStonePBA 31309Bluetooth Qualification and Regulatory CertificationUser’s Manual Intel Public 31Hardware Description Revision 1.0, 1-Feb-20138.0 Bluetooth Qualification and Regulatory Certification8.1 Reference DesignFigure 9. Reference Design Schematics   !! "!! "# # $#%$#%$#  "$#%$#% ##! $# "# "# & & #& #& ##& &      & $#$# ! $#  # # !!# # $#$#$# $#!$# $# #$# #!$# !$#!  $# $#  '$&() #() #() ()* ()"# ()"# () !() (! #( ( #()" ()# () ()" ()()* #()#) ()#) ()*()*!(()+*(!)+*,&" &#### $---$#$# $# $# """"""$$++**++(((((((!(!(  (  (  (  #./0123)45678//9:9;65.:07:<97( $#
eUniStonePBA 31309Bluetooth Qualification and Regulatory CertificationUser’s Manual Intel Public 32Hardware Description Revision 1.0, 1-Feb-2013PBA 31309 is intended to be installed inside end user equipment. PBA 31309 is Bluetoooth-qualified and also FCC-certified, and conforms to R&TTE (European) requirements and directives with the reference design described in Figure 9.Manufacturers of mobile, fixed or portable devices incorporating this device are advised to clarify any regulatory questions and to have their complete product tested and approved for compliance (FCC or other when applicable).There are no parts in PBA 31309 that can be modified by the user except modifications of the device BD data and loading of SW patches. Any changes or modifications made to this device that are not expressly approved by Intel, may void the user’s authority to operate the equipment.8.2 FCC Class B Digital Devices Regulatory NoticeThis equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to Part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment generates, uses, and can radiate radio frequency energy and, if not installed and used in accordance with the instructions, may cause harmful interference to radio communications. However, there is no guarantee that interference will not occur in a particular installation. If this equipment does cause harmful interference to radio or television reception, which can be determined by turning the equipment off and on, the user is encouraged to try to correct the interference by 1 or more of the following measures:• Reorient or relocate the antenna• Increase the separation between the equipment and receiver• Connect the equipment into an outlet on a circuit different from that to which the receiver is connected• Consult the dealer or an experienced radio or television technician for help8.3 FCC Wireless NoticeThis product emits radio frequency energy, but the radiated output power of this device is far below the FCC radio frequency exposure limits. Nevertheless, the device should be used in such a manner that the potential for human contact with the antenna during normal operation is minimized.To meet the FCC's RF exposure rules and regulations:• The system antenna used for this transmitter must not be co-located or operating in conjunction with any other antenna or transmitter.• The on-board antenna used must not be altered.• Users and installers must be provided with antenna installation instructions and transmitter operating conditions for satisfying RF exposure compliance. See Figure 10.
eUniStonePBA 31309Bluetooth Qualification and Regulatory CertificationUser’s Manual Intel Public 33Hardware Description Revision 1.0, 1-Feb-2013Figure 10. Cutout DrawingManufacturers of mobile, fixed or portable devices incorporating this module are advised to clarify any regulatory questions and to have their complete product tested and approved for FCC compliance.8.4 FCC Interference StatementThis device complies with Part 15 of the FCC Rules. Operation is subject to the following two conditions:1. This device may not cause harmful interference2. This device must accept any interference received, including interference that may cause undesired operation.8.5 FCC IdentifierFCC ID: PD9PBA31309Min. 40mm15.63.008.7Min. 15mmMin. 15mmVisio-Source-PAN1322.vsdRestricted AreaNo copper in any layer5.00Dimensions are in mm.Use a Ground plane in the area surrounding the PBA31309 module wherever possible.If possible place PBA31309in the center of the main PCB.Place PBA31309 at the edge of the main PCB.Top View
eUniStonePBA 31309Bluetooth Qualification and Regulatory CertificationUser’s Manual Intel Public 34Hardware Description Revision 1.0, 1-Feb-20138.6 European R&TTE Declaration of ConformityHereby, Intel declares that the Bluetooth module PBA 31309 is in compliance with the essential requirements and other relevant provisions of Directive 1999/5/EC.As a result of the conformity assessment procedure described in Annex III of the Directive 1999/5/EC, the end-customer equipment should be labelled as follows:Figure 11. Equipment LabeleUniStone in the specified reference design can be used in the following countries:Austria, Belgium, Cyprus, Czech Republic, Denmark, Estonia, Finland, France, Germany, Greece, Hungary, Ireland, Italy, Latvia, Lithuania, Luxembourg, Malta, Poland, Portugal, Slovakia, Slovenia, Spain, Sweden, The Netherlands, the United Kingdom, Switzerland, and Norway.
eUniStonePBA 31309Bluetooth Qualification and Regulatory CertificationUser’s Manual Intel Public 35Hardware Description Revision 1.0, 1-Feb-2013Figure 12. Declaration of ConformityThe product will be compliant to R&TTE Directive 1999/5/EC: EN 60950-1 2006, EN 50371: 2002 Health and Safety of the User EN301 489-1, v1.8.1, EN301 489-17 v2.1.1 Electromagnetic Compatibility EN300 328 v1.8.1 Effective use of spectrum allocated.
eUniStonePBA 31309Bluetooth Qualification and Regulatory CertificationUser’s Manual Intel Public 36Hardware Description Revision 1.0, 1-Feb-20138.7 Bluetooth Qualified Design IDIntel has submitted End Product Listings (EPL) for eUniStone and eBMU in the Qualified Product List of the Bluetooth SIG. These EPLs are referencing the Bluetooth qualification of the SPP-AT application running on the eBMU chip under QD ID t.b.d.Manufacturers of Bluetooth devices incorporating eUniStone or eBMU can reference the same QD ID number.Bluetooth QD ID: B021246 8.9 Label Design of the Host ProductIt is recommended to include the following information on the host product label:Contains transmitter Module FCC ID: PD9PBA313098.10 Regulatory Test HouseThe test house used by Intel in the Bluetooth and Regulatory approvals for the module PBA 31309:AT4wirelessParque Tecnologico de Andaluciac/ Severo Ochoa 2E-29590 - MalagaSPAINTel: (34) 95 261 91 00Fax: (34) 95 261 91 13www.at4wireless.com
eUniStonePBA 31309Assembly GuidelinesUser’s Manual Intel Public 37Hardware Description Revision 1.0, 1-Feb-20139.0 Assembly GuidelinesThe target of this chapter is to provide guidelines for customers to successfully introduce the eUniStone module in production. This includes general description, PCB-design, solder printing process, assembly, soldering process, rework and inspection.9.1 General Description of the ModuleeUniStone is a Land Grid Array (LGA 6x12) module made for surface mounting. The pad diameter is 0.6 mm and the pitch 1.2 mm.All solder joints on the module will reflow during soldering on the mother board. All components and shield will stay in place due to wetting force. Wave soldering is not possible.Surface treatment on the module pads is Nickel (5-8 µm)/Gold (0.04 - 0.10 µm).Figure 13 shows the pad layout on the module, seen from the component side.Figure 13. Pad Layout on the Module (top view)F2 F3 F4 F5E1 E2 E3 E4 E5 E6 E7 E8 E9D1 D2 D3 D4 D5 D6 D7 D8C1 C2 C3 C4 C5 C6 C7 C8B1 B2 B3 B4 B5 B6 B7 B8 B9A2 A3 A4 A5 A6 A7 A8A11.08.70 mm0.65.00. 61. 35 1.351.2F91.2F7F1 F8D9C9A915.6 mmF6 F11A11F1 2A122.4
eUniStonePBA 31309Assembly GuidelinesUser’s Manual Intel Public 38Hardware Description Revision 1.0, 1-Feb-20139.2 Printed Circuit Board DesignThe land pattern on the PCB shall be according to the land pattern on the module, which means that the diameter of the LGA pads on the PCB shall be 0.6 mm. It is recommended that each pad on the PCB shall be surrounded by a solder mask clearance of about 75 µm to avoid overlapping solder mask and pad.Figure 14. Cutout DrawingIn order to preserve the characteristics of the embedded antenna, a cutout must be respected under the antenna through all metal layers of the PCB, as shown in drawing Figure 14.Placing the module inside a metal housing or close to metal parts like fasteners, shielding cages, washers, etc. can significantly affect the antenna characteristics.Min. 40mm15.63.008.7Min. 15mmMin. 15mmVisio-Source-PAN1322.vsdRestricted AreaNo copper in any layer5.00Dimensions are in mm.Use a Ground plane in the area surrounding the PBA31309 module wherever possible.If possible place PBA31309in the center of the main PCB.Place PBA31309 at the edge of the main PCB.Top View
eUniStonePBA 31309Assembly GuidelinesUser’s Manual Intel Public 39Hardware Description Revision 1.0, 1-Feb-20139.3 Solder Paste PrintingThe solder paste deposited on the PCB by stencil printing has to be of eutectic or near eutectic tin leadfree / lead composition. A no-clean solder paste is preferred, since cleaning of the solder joints is difficult because of the small gap between the module and the PCB.Preferred thickness of the solder paste stencil is 100 - 127 µmm (4 - 5 mils). The apertures on the solder paste stencil shall be of the same size as the pads, 0.6 mm.9.4 Assembly9.4.1 Component PlacementIn order to assure a high yield, good placement on the PCB is necessary. As a rule of thumb the tolerable misplacement is 150 µmm. This means that the eUniStone module can be assembled with a variety of placement systems.It is recommended to use a vision system capable of package pad recognition and alignment that evaluates the pad locations on the package (in contrast to outline centring). This eliminates the pad to package edge tolerance.The recommendation is to pick and place the module with a nozzle in the centre of the shield. The nozzle diameter shall not be bigger than 4 mm.9.4.2 Pin MarkPin 1 (A1) is marked on bottom footprint and on the top of the shield on the module according to Figure 15. Diameter of pin 1 mark on the shield is 0.40 mm.Figure 15. Pin Markingi intelGYYWW/DFYWW9EXXFCCID:QG2331308PBA31309 V1.00Top_and_Bottom_Views.vsdPin 1 marking bottom sideF2F3F4F5F6E1E2E3E4E5E6E7E8E9D1D2D3D4D5D6D7D8C1C2C3C4C5C6C7C8B1B2B3B4B5B6B7B8B9A2A3A4A5A6A7A8 A1F9 F7 F1F8D9C9A9Pin 1 marking top sideA11F12 F11A12
eUniStonePBA 31309Assembly GuidelinesUser’s Manual Intel Public 40Hardware Description Revision 1.0, 1-Feb-20139.4.3 PackageeUniStone is packed in tape on reel according to Figure 16.Figure 16. Tape on Reel
eUniStonePBA 31309Assembly GuidelinesUser’s Manual Intel Public 41Hardware Description Revision 1.0, 1-Feb-20139.5 Soldering ProfileGenerally all standard reflow soldering processes (vapour phase, convection, infrared) and typical temperature profiles used for surface mount devices are suitable for the eUniStone module. Wave soldering is not possible.Figure 17 and Figure 18 shows example of a suitable solder reflow profile. One for leaded and one for leadfree solder.Figure 17. Eutectic Lead-Solder ProfileFigure 18. Eutectic Leadfree-Solder ProfileLead_Solder_Profile .vsd Recommended temp. profile for reflow soldering Temp.[°C] Time [s] 235°C max. 220 5°C 200°C150 10°C 90 30s 10 1s 30 +20/-10s LeadFree_Solder_Profile.vsd 25°C 150°C 200°C 217°C 255°C 260°C 60 ~ 120 sec @ 3’C/sec max60 ~ 150 sec30 sec max 6’C/sec max 8 minutes maxTemp.[°C] Time [s] Recommended temp. profile for reflow soldering (J-STD-020C)
eUniStonePBA 31309Assembly GuidelinesUser’s Manual Intel Public 42Hardware Description Revision 1.0, 1-Feb-2013At the reflow process each solder joint has to be exposed to temperatures above solder liquids for a sufficient time to get the optimum solder joint quality, whereas overheating the board with its components has to be avoided. Using infrared ovens without convection special care may be necessary to assure a sufficiently homogeneous temperature profile for all solder joints on the PCB (especially on large, complex boards with different thermal masses of the components). The most recommended types are therefore forced convection or vapour phase reflow. Nitrogen atmosphere can generally improve solder joint quality, but is normally not necessary.The reflow profiles and other reflow parameters are dependent on the used solder paste. The paste manufacturer provides a reflow profile recommendation for this product.Additionally it is important not to overheat the eUniStone module by a too large reflow peak temperature. eUniStone contain several plastic packages and is there by sensitive of the moisture content level at the time of board assembly.Overheating in combination with excessive moisture content could result in package delaminations or cracks (popcorn effect). The heating rate should not exceed 3°C/s and max sloping rate should not exceed 4°C/s.eUniStone shall be handled according to MSL3, which means a floor life of 168 h in 30°C/60% r.h.The eUniStone module can be soldered according to max. J-STD-020C curve, assuming that all other conditions are followed stated in Product Specification, Qualification Report and in Application Note. Restriction is that PBA 31309 can be soldered two times, since one time is already consumed when soldering devices on Module.9.6 Rework9.6.1 Removal Procedure1. Heat the module with an appropriate heating nozzle according to the instruction of the equipment or on a hot plate (about 225°C dependent on the board). Hot plate can only be used if the board is single side assembled. The temperature of the module shall be 200-220°C.2. Use grippers or a pair of tweezers to remove the module. The module has to be gripped on two opposite edges of the module (not on the shield).3. Remove excess solder by using solder sucker, suction soldering irons or solder wick.9.6.2 Replacement ProcedureReplacement can be done in two ways, dependent of how the solder is applied. Solder can be applied either by dispensing on the mother board or by printing the solder paste directly on the module.9.6.2.1 Alternative 1: Dispensing SolderA dispenser with controlled volume must be used to assure the same volume on every pad. The volume on each pad shall be about 0.04 mm3.1. Dispense 0.04 mm3 on each LGA pad2. Pick the module by a nozzle and place in the right position on the board3. Reflow the solder.
eUniStonePBA 31309Assembly GuidelinesUser’s Manual Intel Public 43Hardware Description Revision 1.0, 1-Feb-20139.6.2.2 Alternative 2: Printing SolderTo print solder on the module a fixture must be used. The purpose of the fixture is to get a flat surface and fix the stencil and module for printing. An example of how this fixture can be designed is shown in Figure 19.Figure 19. Solder Printing1. Assemble the fixture to the bottom2. Place the module in the cavity with the LGA pads upwards3. Place the solder paste stencil on the fixture and make sure it fits to the tooling pins and the module4. Apply vacuum to fix the solder paste stencil5. Apply solder paste on the stencil and print by using a blade6. Turn everything (bottom, fixture and stencil) upside down.7. Separate carefully the bottom from the fixture8. Pick the module by a nozzle and place in the right position on the board9. Reflow the solder.9.7 InspectionAutomatic inspection of the solder paste printing before assembly is highly recommended to ensure high yield and good long term reliability.Solder_Printing.vsdVacuum hol esSolder paste stencilCavity of the module Tooling pinsBottomFixture
eUniStonePBA 31309Assembly GuidelinesUser’s Manual Intel Public 44Hardware Description Revision 1.0, 1-Feb-20139.8 Component SalvageIf it is intended to send a defect eUniStone module back to the supplier for failure analysis, please note that during the removal of this component no further defects must be introduced to the device, because this may hinder the failure analysis at the supplier. This includes ESD precautions, not to apply high mechanical force for component removal, and to prevent excess moisture content in the package during salvage (risk of pop corning failures). Therefore if the maximum storage time out of the dry pack (see label on packing material) is exceeded after board assembly, the PCB has to be dried 24h at 125°C before soldering off the defect component, because otherwise too much moisture may have been accumulated.9.9 Voids in the Solder Joints9.9.1 Expected Void Content and ReliabilityThe content of voids is larger on LGA modules than for modules with BGA or leads. At a LGA solder joint the outgassing flux has a longer way to the surface of the solder and it has a relatively small surface to the air.The void content of the eUniStone module conforms to IPC-A-610D (25% or less voiding area/area).Figure 20 shows an example of void-content at a module assembled at production site. Normally you can see the whole spectra of void content variation within the same lot and occasion of assembly.Figure 20. X-ray Picture Showing Voids Conforming to IPC-A-610DVoids_IPC_A_610D.vsd
eUniStonePBA 31309Assembly GuidelinesUser’s Manual Intel Public 45Hardware Description Revision 1.0, 1-Feb-20139.9.2 Parameters with an Impact on VoidingIf the void content has to be reduced following parameters have an impact.Solderability on module and PCBBad solderability is often connected to oxidation and has therefore a major impact on voiding. Flux will get entrapped on oxidized surfaces. In general, Ni/Au pads show fewer voids than HASL and OSP.Solder pasteHigher activity of the flux will remove oxide rapidly and less flux will get entrapped.Voiding increases with increasing solder paste exposure time, since long exposure time will result in more oxidation and moisture pickup.Pad sizeA large soldering pad means that the outgassing flux has a longer way to the surface of the solder, and will thereby create more voids.Solder pasteSmaller powder size and higher metal load means more metal surface to deoxidize and thereby more entrapped flux and voiding. Higher metal load does also mean higher viscosity and more difficult for outgassed flux to remove from the solder.Stencil thicknessA thick solder paste stencil means more surface area to the air and thereby easier for the outgassing flux to leave the solder.Temperature soldering profileToo short preheat time means that the flux does not get enough time to react and flux get entrapped in the solder and create voids.Too long reflow time gives larger voidsToo short reflow time gives a fraction of voids
eUniStonePBA 31309User’s Manual Intel Public 46Hardware Description Revision 1.0, 1-Feb-2013References[1] Intel AT Command Specification (eUniStone_1.00_UM_SD.pdf)[2] Release Notes for SPP AT application SW version 1.1 (eUniStone_1.00_SW_3.1_RN.pdf)
eUniStonePBA 31309User’s Manual Intel Public 47Hardware Description Revision 1.0, 1-Feb-2013TerminologyAACK AcknowledgementACL Asynchronous Connection-oriented (logical transport)AFH Adaptive Frequency HoppingAHS Adaptive Hop SequenceARQ Automatic Repeat reQuestBb bit/bits (e.g. kb/s)B Byte/Bytes (e.g. kB/s)BALUN BALanced UNbalancedBD_ADDR Bluetooth Device AddressBER Bit Error RateBMU BlueMoon UniversalBOM Bill Of MaterialBT BluetoothBW BandwidthCCDCT Clock Drift Compensation TaskCMOS Complementary Metal Oxide SemiconductorCOD Class Of DeviceCODEC COder/DECoderCPU Central Processing UnitCQDDR Channel Quality Driven Data RateCRC Cyclic Redundancy CheckCTS Clear To Send (UART flow control signal)CVSD Continuous Variable Slope Delta (modulation)DDC Direct CurrentDDC Device Data ControlDM Data Medium-Rate (packet type)DMA Direct Memory AccessDH Data High-Rate (packet type)DPSK Differential Phase Shift Keying (modulation)DQPSK Differential Quaternary Phase Shift Keying (modulation)DSP Digital Signal ProcessorDUT Device Under TestEEDR Enhanced Data RateEEPROM Electrically Erasable Programmable Read Only MemoryeSCO Extended Synchronous Connection-Oriented (logical transport)EV Extended Voice (packet type)FFEC Forward Error Correction
eUniStonePBA 31309User’s Manual Intel Public 48Hardware Description Revision 1.0, 1-Feb-2013FHS Frequency Hop Synchronization (packet)FIFO First In First Out (buffer)FM Frequency ModulationFW FirmwareGGFSK Gaussian Frequency Shift Keying (modulation)GPIO General Purpose Input/OutputGSM Global System for Mobile communicationHHCI Host Controller InterfaceHCI+ Intel Specific HCI command setHEC Header Error CheckHV High quality Voice (packet type)HW HardwareII2C Inter-IC Control (bus)I2S Inter-IC Sound (bus)IAC Inquiry Access CodeID IDentifierIEEE Institute of Electrical and Electronics EngineersIF Intermediate FrequencyISM Industrial Scientific & Medical (frequency band)JJTAG Joint Test Action GroupLLAN Local Area NetworkLAP Lower Address PartLM Link ManagerLMP Link Manager ProtocolLNA Low Noise AmplifierLO Local OscillatorLPM Low Power Mode(s)LPO Low Power OscillatorLSB Least Significant Bit/ByteLT_ADDR Logical Transport AddressMMSB Most Significant Bit/ByteMSRS Master-Slave Role SwitchNNC No ConnectionNOP No OPerationNVM Non-Volatile MemoryOOCF Opcode Command FieldOGF Opcode Group FieldPPA Power AmplifierPCB Printed Circuit BoardPCM Pulse Coded ModulationPDU Protocol Data UnitPER Packet Error RatePIN Personal Identification Number
This document has been formally released by DOC department (IMC-DOC@intel.com) on February 16, 2013eUniStonePBA 31309User’s Manual Intel Public 49Hardware Description Revision 1.0, 1-Feb-2013PLC Packet Loss ConcealmentPLL Phase Locked LoopPMU Power Management UnitPOR Power-On ResetPTA Packet Traffic ArbitrationPTT Packet Type TableQQoS Quality Of ServiceRRAM Random Access MemoryRF Radio FrequencyROM Read Only MemoryRSSI Received Signal Strength IndicationRTS Request To Send (UART flow control signal)RX ReceiveRXD Receive Data (UART signal)SSCO Synchronous Connection-Oriented (logical transport)SIG Special Interest Group (Bluetooth SIG)SW SoftwareSYRI Synthesizer Reference InputTTBD To Be DeterminedTCK Test Clock (JTAG signal)TDI Test Data In (JTAG signal)TDO Test Data Out (JTAG signal)TL Transport LayerTMS Test Mode Select (JTAG signal)TX TransmitTXD Transmit Data (UART signal)UUART Universal Asynchronous Receiver & TransmitterULPM Ultra Low Power ModeVVCO Voltage Controlled OscillatorWWLAN Wireless LAN (Local Area Network)

Navigation menu