LG Electronics USA LEO2-A LTE User Equipment User Manual LEO2 Platform Hardware Manual

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Document Description	Users Manual
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Date Submitted	2008-09-23 00:00:00
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Document Title	Microsoft Word - LEO2 Platform Hardware Manual.doc
Document Creator	Microsoft Word - LEO2 Platform Hardware Manual.doc
Document Author:	frank.lee

Updated
File
Title
V1.0
Type
LEO2-A Platform Hardware Manual
Rev.
LEO2 Platform Hardware Manual
2008-09-08
Manual
ABSTRACT
This document is hardware manual for LEO2-A Platform board. Contents of this document are
descriptions of each blocks and usage directions. It is recommended to peruse this manual before
operating LEO2-A Platform
HISTORY
Rev Status
Date
Author
Contents
KEY WORDS
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Mobile Communication Technology Research Lab.
533 Hogye-dong, Dongan-gu, Anyang-shi,
Kyongki-do, KOREA
©Copyright, 2008 By LG Electronics Inc. All rights reserved.
No part of this document may be reproduced in any way, or by any means, without
the express written permission of LG Electronics Inc.
LGE Proprietary
MCTR Lab.
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V1.0
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[Notice]
1. The product described in this manual may be modified without prior notice for reliability,
functionality or design improvement.
2. Information contained in this manual is correct and reliable, but LG shall not be held
responsible for damage due to the use of information, product or circuit or infringement of
property rights or other rights.
3. This manual does not grant users the property rights and other rights of the third party or
LG Electronics Inc.
4. No part of this manual may be transcribed or duplicated without the written permission of
LG Electronics Inc.
5. The appearance of the product shown in this manual may slightly differ from that of the
actual product.
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1.
1.1
1.2
1.3
1.4
2.
2.1
2.2
2.3
2.4
3.
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
4.
4.1
4.2
4.3
5.
6.
Rev.
LEO2 Platform Hardware Manual
V1.0
CONTENTS
Introduction............................................................................................................................... １
Scope ..................................................................................................................................... １
Terminology............................................................................................................................ １
Trademark List ........................................................................................................................ １
Special Mark........................................................................................................................... １
Features and top level diagram ................................................................................................. ２
Features ................................................................................................................................. ２
Photograph of the LEO2-A platform board............................................................................... ２
Top level block diagram .......................................................................................................... ３
Placement map....................................................................................................................... ３
Block description....................................................................................................................... ４
FPGA subsystem .................................................................................................................... ４
ARM subsystem...................................................................................................................... ４
Debugger Interface ................................................................................................................. ５
RF Interface............................................................................................................................ ６
Reference Clock ..................................................................................................................... ７
Reset ...................................................................................................................................... ８
Application interface................................................................................................................ ８
Power Supplies....................................................................................................................... ９
DIP switch, LED and logic probing connector ............................................................................ ９
ARM Processor debugging configuration switch setting........................................................... ９
General purpose LED indication........................................................................................... １０
Logic probing connector....................................................................................................... １１
Description of Smart antenna and beam forming modes if applicable ..................................... １２
Reference ............................................................................................................................ １２3
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FIGURES
Figure 1. Photograph of LEO2-A platform ........................................................................................ ２
Figure 2. Top level block diagram .................................................................................................... ３
Figure 3. Placement map of LEO2-A ............................................................................................. ３
Figure 4. ARM processor Block ..................................................................................................... ４
Figure 5. RF interface on LEO2-A platform board ............................................................................ ６
Figure 6. Block diagram of RF daughter board................................................................................. ６
Figure 7. Block diagram of clock distribution .................................................................................... ７
Figure 8. Block diagram of platform board reset scheme.................................................................. ８
Figure 9. Block diagram of application interface ............................................................................... ８
Figure 10. Block diagram of power supplies..................................................................................... ９
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TABLES
Table 1. ARM processor setting DIP switches............................................................................... １０
Table 2. LED signal mapping........................................................................................................ １１
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1.
Rev.
LEO2 Platform Hardware Manual
V1.0
Introduction
1.1 Scope
This document intends to describe the brief architecture and usage of the LEO2-A Platform
board. LEO2-A Platform board is designed for LTE User Equipment test and verification.
1.2
Terminology
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ADC
AMBA
AHB
DAC
DDR SDRAM
EPI
ETM
JTAG
LNA
UE
UART
SDIO
USB
VGA
ZDB
Analog to Digital Converter
Advanced Microcontroller Bus Architecture
Advanced High-performance Bus
Digital to Analog Converter
Double Data Rate Synchronous Dynamic Random Access Memory
External Perallel Interface
Embedded Trace Macro-cell
Joint Test Action Group
Low Noise Amplifier
User Equipment
Universal Asynchronous Receiver/Transmitter
Secure Digital Input Output
Universal Serial Bus
Variable Gain Amplifier
Zero Delay BufferAMBA
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1.3
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ARM926EJ-S are registered trademarks of ARM Ltd.
Trademark List
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1.4 Special Mark
The following table defines special marks used in this manual.
Mark
Definition
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2.
Rev.
LEO2 Platform Hardware Manual
V1.0
Features and top level diagram
2.1
Features
- ARM926EJ-S (max 333MHz)
- AMBA 2.0 (max 166MHz)
- 7 Virtex4 FX140 FPGA for Modem algorithm
- RF interface (2 Receivers and 1 Transmitter)
- Application interface
- 512Mb DDR SDRAM, 1Gb NAND Flash
- USB 2.0 High speed device
- 100 Ethernet port
- 1 Serial ports (up to 115 K baud)
- JTAG and ETM Debug port
2.2
Photograph of the LEO2-A platform board
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Figure 1. Photograph of LEO2-A platform
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Mechanical size of platform board is 420 (W) x 300 (H) mm
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Top level block diagram
Application Interface
EPI, NAND, USB
SDIO, SPI, DIP SW
96
32 Signals
OPT_DCH1_SYMB0[8]
OPT_DCH1_SYMB1[8]
OPT_DCH1_STB, START, END
RSVD[13]
ls
na
Sig
51 Signals
310 Signals
ls ] ND
na B[8 , E
_N
Sig YM RT ]
54 _S STA [10 YNC
H ,
X S
LC TB _ID E_
CT _S C H AM 2]
CH T L FR D[3
TL C X_ SV
_R R
PT
ls
0[8
na MB [8]
Sig SY B1 EN
32 H0_ SYM RT,
_D C H0 , ST
OP T _D _ST [13]
O CH S
T_
OP
30.72/61.44/122.88MHz
149 Signals
TD0_START
TD0_IMEM_WE, SEL[3]
TD0_IMEM_WADDR[12]
TD0_IMEM_WDATA[64]
TD0_DB_DONE, DEC_DONE
HARQ0_START
HARQ0_PARAM_START
RSVD[64]
PLL
TurboDecoder_CLK
59 Signals
TX_FILTER_OUT[48]
TX_FILTER_IQ_SEL
RSVD[10]
26 Signals
TX_I[12]
TX_Q[12]
RSVD[2]
32 Signals
RF_GPIO[16]
4ch SPI
64bits
mDDR
JTAG
ETM
UART
Ethernet
Serial
Flash
NAND
USB
SDRAM
RF Daughter connector
DA D AT 5
TA AT AC 1 S
C H AC H1 ign
1_ H1 _S als
R T B _SY M B
SV ,
M 0
D[3 ST B1 [8]
2] AR [8]
T,
EN
64bits
mDDR
100 Signals
RSVD[100]
48 Signals
RX0_I[12], RX0_Q[12]
RX1_I[12], RX1_Q[12]
RX_FRAME_SYNC_N
RX_SUB_FRAME_SYNC_N
ENG_EN[5]
ORX_WR, ADDR[10], DATA[32]
MIMO_WR_ADDR[10], DATA[32]
SC_RD_DATA0[32]
SC_RD_DATA1[32]
SC_RD_STB, IDX[2]
SC_RD_EN, ADDR[11]
SC_RD_SYMB_IDX[2]
ORX_OPT[100]
RSVD[64]
DATACH0_SYMB0[8]
DATACH0_SYMB1[8]
DATACH0_STB, START, END
RSVD[32]
32 Signals
RX_FRAME_SYNC_N
OPT_CTLCH_SYMB[8]
OPT_CCH_STB, START, END
OPT_CCH_IDX[10]
RSVD[10]
149 Signals
TD1_START
TD1_IMEM_WE, SEL[3]
TD1_IMEM_WADDR[12]
TD1_IMEM_WDATA[64]
TD1_DB_DONE, DEC_DONE
HARQ1_START
HARQ1_PARAM_START
RSVD[64]
ARM926EJ-S
Figure 2. Top level block diagram
2.4
Placement map
SRCH TP1
SRCH TP0
J10
MIMO TP1
MIMO TP0
J7
TD1 TP1
TD1 TP0
J4
HARQ TP1
HARQ TP0
J1
RF RX
RF TX
J11
TD0 TP1
TD0 TP0
J6
HARQ0 TP1
HARQ0 TP0
J3
TX TP1
TX TP0
ETHERNET
RESET
Figure 3. Placement map of the LEO2-A
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3.
Block description
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3.1 FPGA subsystem
The LEO2-A Platform supports 7 FPGAs (xilinx virtex4 FX140, 1517pin package) for LTE UE
modem algorithm. Functionality of each FPGA is
- TX FPGA : Transmit block, Viterbi decoder, RF board control
- SRCH FPGA : Receiver block
- MISO FPGA : Receiver block and MISO
- HARQ 0/1 FPGA : Hybrid ARQ block
- Turbo Decoder 0/1 FPGA : Decoder block
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Signal connection of FPGAs is
- ARM926 bus signal is connected to commonly all FPGAs, except MISO FPGA.
- 32 common reserved signals are connected commonly.
- 64 test signals of each FPGA are connected to MICTOR probing header.
- 4 GPIO LEDs of each FPGAs
- Detailed signals are described on block diagram.
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FPGA configure bitstream is stored in platform flash. The maximum configuration bitstream size
of virtex4 FX140 is 47,856,896. Bitstream is stored in 2 serial daisy chained memories; capacity is
32Mb and 16Mb. Proper binary image should be fused on each platform memories. Xilinx
Platform cable connection for image fusing are J12 (TX FPGA), J10 (SRCH FPGA), J7 (MISO
FPGA), J3 (HARQ0 FPGA), J4 (HARQ1 FPGA), J6 (Turbo Decoder 0 FPGA) and J1 (Turbo
Decoder1 FPGA), which are placed beside of each FPGAs.
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3.2
ARM subsystem
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Figure 4. ARM processor block
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The ARM processor is used to control the LTE UE modem logic. The processor has
ARM926EJ-S core and peripheral controllers.
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ARM Processor
- ARM926EJ-S core max. 333MHz, 16KB-I/D cache, configurable TMC-I/D size, MMU,
TLB, JTAG and ETM trace module (multiplexed interfaces).
- 32KByte Rom (code customizable) 8KByte common SRAM.
- High performance linked list 8 channels DMA.
- Ethernet MII, management interface
- USB2.0 High speed device
- Ext. memory interface : 16bit DDR1@200MHz
- Flash interface: 8bits NAND and Serial.
- 10 independent Timers with programmable prescaler.
- RTC - WDOG - SYSCTR - MISC internal control registers.
- JTAG (IEEE1149.1) interface.
- Current clock frequency setting : ARM Core 300MHz, Bus 150MHz, SDRAM 150MHz
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Memory
The memory capacity and speed grade, that is on this board, are
- SDRAM : 512Mbits, 16bits data access, DDR @ 150MHz
- NAND Flash : 1Gbits, 8bits parallel, code stored.
- Serial Flash : 64Mbits, boot loader stored.
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External Interface
The LEO2-A Platform supports external interface for diagnostic monitoring and user data
transfer.
- High speed USB2.0
- 100Mbps Ethernet
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Interrupt
9 interrupt inputs are from interrupt handler in Turbo decoder0 FPGA.
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3.3 Debugger Interface
The LEO2-A platform support debugging interface, JTAG and ETM, for ARM926
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ARM926 core
- JTAG : CON12
- ETM9 : CON11
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3.4
RF Interface
Figure 5. RF interface on LEO2-A platform board
Figure 6. Block diagram of RF daughter board
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The LEO2-A Platform supports RF daughter board interface to verify and test LTE UE modem
algorithm. The baseband IQ signals are transmitted and received on FPGAs, Transmit part is on
TX FPGA and Receive part is on SRCH, MISO FPGA. The bit resolution of IQ signal is 12bits.
The sampling frequencies are 122.88MHz for DAC and 61.44MHz for ADC. The transmit signal
and sampling clock are delivered through LVDS, because of it’s over 100MHz data rate.
The RF control signals, GPIO and SPIs, are generated on TX FPGA.
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RF daughter board consist in following blocks
- 2 antenna ports : 1 Tx and 2 Rx
- 14bits TX DAC, 14bits RX ADC
- TX synthesizer, RX synthesizer
- Modulator, Demodulator, VGA,
- Power amp, LNA and passive RF devices
- 3 x 120pin connector
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3.5 Reference Clock
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Figure 7. Block diagram of clock distribution
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The 19.2MHz reference clock for LEO2-A platform board is supplied from TCXO in RF daughter
board. From this ref. clock, all needed clock source for LTE UE modem is synthesized by PLLs.
The PLLs generated clock frequencies 30.72, 61.44, 122.88MHz, and 32KHz.
All PLL output clocks are supplied to FPGAs and other blocks. The clock skews on each FPGA
input pad is very low <1nsec.
There is additional reference clock oscillator on LEO2-A platform board for without RF daughter
board test situations. This clock path selection is controlled by the 7pin on SW6. (‘1’ on-board, ‘0’
RF daughter board oscillator)
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3.6
Reset
Figure 8. Block diagram of platform board reset scheme
The reset CPLD manages whole system reset scheme for ARM, Ethernet transceiver and each
FPGA reset. In the lower left lower corner of the platform board, a manual reset switch is provided.
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3.7 Application interface
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Figure 9. Block diagram of application interface
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The LEO2-A platform supports a interface for external connection to application side. 3 kinds of
interfaces are supported, EPI, SDIO and USB. Application side will be designed as a platform
board
at
next
phase.
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3.8
Power Supplies
Figure 10. Block diagram of power supplies
External power supplied from DC input jack on the platform board. To proper operation,
external AC to DC power supply should be 12V and >5A. All needed power sources of
platform board are supplied from DC-DC converters and LDOs devices.
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4.
DIP switch, LED and logic probing connector
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4.1 ARM Processor debugging configuration switch setting
Two DIP switches (SW3, SW6) are used to ARM processor configurations and platform board
settings. Each control signals are assigned according to Table 1. “Switch on” represents “logic
low”, “switch off” represents “logic high” as other platform boards.
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LEO2-A Platform default DIP switch settings are Table 1.
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Remark: Setting the DIP switch in a wrong way may cause unexpected behavior that can
also damage the board since that all the production tests are intended to run in a different
environment.
SW3
Pin No.
Name
ARM_INT(0)
ARM_INT(1)
ARM_INT(2)
ARM_INT(3)
DIPSW_CPLD(0)
LGE Proprietary
Description
ARM Processor interrupt input
"on" : assert interrupt
"off" : deassert interrupt
Test signal input to reset CPLD
"on" : low signal to CPLD
"off" : high signal to CPLD
９
Default
OFF
OFF
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"off" : high signal to CPLD
V1.0
DIPSW_CPLD(1)
SSP2_SS1
SMI_WE
Pin No.
Name
ARM_TEST(0)
OFF
ARM_TEST(1)
ON
ARM_TEST(2)
ARM processor booting device selection
'on' Boot from USB
'off' Boot NAND flash
OFF
Write enable signal of serial flash
"on" : write protected
"off" : write enabled
OFF
Description
Default
ON
ARM Processor configuration
SW6
ARM_TEST(3)
OFF
ARM_TEST(4)
ON
ARM_TEST(5)
OFF
CLK_SEL
Reference clock selection
'on' Reference clock from RF daughter
'off' on board reference clock
ON
OFF
Table 1. ARM processor setting DIP switches
4.2 General purpose LED indication
There are several LEDs are present on the board. Their meanings are described in Table 4-3.
LED turn on represent signal is high or status is good.
LED1
1.2V power OK
LED2
1.2V power OK
LED3
1.2V power OK
LED4
3.3V power OK
LED5
DC IN OK
LED6
1.0V power OK
LED7
Ethernet duplex
LED8
Ethernet link 1000
LED9
Ethernet link 100
LED10
Ethernet link 10
LED11
Ethernet activity
LED13
2.5V power OK
LED14
All FPGA done
LED15
PLL Lock
LED16
Turbo Dec1 FPGA done
LED17
ARM INT(4)
LED18
TD1 GPIO(0)
LED19
ARM INT(5)
LED20
TD1 GPIO(1)
LED21
ARM INT(6)
LED22
TD1 GPIO(2)
LED23
ARM INT(7)
LED24
TD1 GPIO(3)
LED25
ARM INT(8)
LED26
HARQ1 FPGA Done
LED27
HARQ0 FPGA Done
LED28
HARQ1 GPIO(0)
LED29
HARQ0 GPIO(0)
LED30
HARQ1 GPIO(1)
LED31
HARQ0 GPIO(1)
LED32
1.8V power OK
LED33
HARQ1 GPIO(2)
LED34
HARQ0 GPIO(2)
LED35
HARQ1 GPIO(3)
LED36
HARQ0 GPIO(3)
LED37
MISO FPGA done
LED38
TD0 FPGA Done
LED39
MISO GPIO(0)
LED40
TD0 GPIO(0)
LED41
MISO GPIO(1)
LED42
TD0 GPIO(1)
LED43
MISO GPIO(2)
LED44
TD0 GPIO(2)
LED45
MISO GPIO(3)
LED46
TD0 GPIO(3)
LED47
SRCH FPGA Done
LED48
TX FPGA Done
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LED49
SRCH GPIO(0)
LED50
TX GPIO(0)
LED51
SRCH GPIO(1)
LED52
TX GPIO(1)
LED53
SRCH GPIO(2)
LED54
TX GPIO(2)
LED55
SRCH GPIO(3)
LED56
TX GPIO(3)
LED57
RF power OK
V1.0
Table 2. LED signal mapping
4.3
Logic probing connector
All of the logic analyzer probing headers are MICTOR connector type, agilent E5346A logic
analyzer probing adaptor is needed to signal monitoring. Refer to LEO2-A schematic for detailed
signal mappings.
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Description of Smart antenna and beam forming modes if applicable
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1) SFBC(Space Frequency Block Code) mode : Transmit diversity mode
Easily speaking, SFBC which eNB sends same data through 2 antennas means
Tx diversity.
2) SM(Spatial multiplexing) mode
SM which eNB sends different data through 2 antennas helps high data
Rate.
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Our LTE UE supports upper 2cases functionality.
That is, we support smart antenna and beam forming in wide meaning.
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6. Reference
[1]
Notice
OEM integrators and installers are instructed that the phrase. This device contains
Warning: Exposure to Radio Frequency Radiation The radiated output
power of this device is far below the FCC radio frequency exposure
limits. Nevertheless, the device should be used in such a manner that
the potential for human contact during normal operation is minimized.
In order to avoid the possibility of exceeding the FCC radio
frequency exposure limits, human proximity to the antenna should
not be less than 20cm during normal operation. The gain of the
antenna for 3GPP-Band4(1710~1755MHz) must not exceed -4 dBi.
The antenna(s) used for this transmitter must not be co-located or operating
in conjunction with any other antenna or transmitter.
LGE Proprietary
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MCTR Lab.

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File Type                       : PDF
File Type Extension             : pdf
MIME Type                       : application/pdf
PDF Version                     : 1.4
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