LG Innotek TWFMB001T Wi-Fi Module User Manual Op Desc

LG Innotek Co., Ltd. Wi-Fi Module Users Manual Op Desc

Contents

Users Manual & Op Desc

SPECIFICATIONSPRODUCT NAME : Dual Band 2T2R MIMO Wi-Fi ModuleMODEL NAME : TWFM-B001TThe information contained herein is the exclusive property of LG Innotekand shall not be distributed, reproduced or disclosed in whole or no in partwithout prior written permission of LG Innotek.Designed Checked ApprovedLG Innotek Co., Ltd. S.C.Lee S.C.Lee D.S.OhDOCUMENT No. HC406452010.11.16 2010.11.16 2010.11.17 PAGE 16(00)-0073
S P E C I F I C A T I O NPAGE :DOCUMENT No :REG. DATE : 2010.11.16MODEL NAME : TWFM-B001TREV. DATE : 2010.11.16REV.NO : 1.0HC406451/ 161. FeaturesTWFM-B001T is the small size and low power module for IEEE 802.11a/b/g/n wireless LAN. TWFM-B001T is based on Broadcom BCM43236 solution.IEEE 802.11 a/b/g/n Dual Band WLAN infrastructureSize : 42mm x 29mm x 6mm2.4GHz and 5GHz internal PATwo stream spatial multiplexing up to 300MbpsMonopole ANT (2T2R MIMO)Use on-chip OTP (One-Time Programmable)USB 2.0Supports drivers for Windows Vista, 2000, XP, LinuxSecurity : WPA,WPA2,AES(TKIP) ,IEEE 802.1X • Application: DTV, DVR, HD DVD Player, Blue-ray Disk Player, STB2. Ordering InformationModel DescriptionTWFM-B001T Wi-Fi Module, Dual Band 2T2R MIMO3. Label marking①④①②③①Model No ④Product Lot No. : 1009A2901 TWFM-B001T 1009A2901001EB2B00339 15351616④⑤©2010 LGIT. All rights reserved.②MAC Address BAR Code -10 : Year - 29 : Date③MAC Address No. - 09: Month - 01 : Manufactured⑤PIN Code - Revision No. : A Process
S P E C I F I C A T I O NPAGE :DOCUMENT No :REG. DATE : 2010.11.16MODEL NAME : TWFM-B001TREV. DATE : 2010.11.16REV.NO : 1.0HC406452/ 16RF802.11n MACANTInUSB 2 0ANTBCM432364. Block DiagramRFSwitch+diplexer3.3V 1.2V2.4GHz PA5GHz PA2 x 2Radio802.11nPHY SecurityOTP(2K bits)nternal BusGPIOUSB 2.0 or HSICANTUSB Connector5. Absolute Maximum RatingsMain Clock(20MHz) DC-DC5V< Fig.1 Hardware Block Diagram >Caution : The specifications in Table 1 define levels at which permanent damage to the ParameterMinMaxUnitppgdevice can occur. Function operation is not guaranteed under these conditions. Operating at absolute maximum conditions for extend periods can adversely affect the long-term reliability of the device.ParameterMinMaxUnitStorage Temperature -10 +80 ℃Storage Humidity - 90 %Supply Voltage VDD_5V - 6.0 Vdc< Table 1 Absolute Maximum Ratings >. Other conditions1) Do not use or store modules in the corrosive atmosphere, especially where chloridegas, sulfide gas, acid, alkali, salt or the like are contained. Also, avoid exposure to moisture. 2) Store the modules where the temperature©2010 LGIT. All rights reserved.2) Store the modules where the temperatureand relative humidity do not exceed 5 to 40℃and 20 to 60%.3) Assemble the modules within 6 months.Check the soldering ability in case of 6 months over.
S P E C I F I C A T I O NPAGE :DOCUMENT No :REG. DATE : 2010.11.16MODEL NAME : TWFM-B001TREV. DATE : 2010.11.16REV.NO : 1.0HC406453/ 166. Operating ConditionsParameter Min Typ Max UnitOperating Temperature 0 - +60 ℃Operating Humidity - - 85 %Supply Voltage VDD_5V 4.5 - 5.5 Vdc7. Standard Test ConditionsTh T t f l t i l ifi ti h ll b f d d th f ll i ditiThe Test for electrical specification shall be performed under the following conditionunless otherwise specified.1). Ambient condition. Temperature : 25℃±5℃. Humidity : 65% ±5% R.H. 2) Power supply voltages2). Power supply voltages . 5V (±5%) input power at the Module 3). Current consumption over recommended range of supply voltage and operating conditions is like below. When it’s tested, it must be supplied more than 2 times of maximal current.FCC (Federal Communications Commission)WARNING Thi i t t di fWARNING: This equipment may generate or use radio frequency energy. Changes or modifications to this equipment may cause harmful interference unless the modifications are expressly approved in the instruction manual. The user could lose the authority to operate this equipment if an unauthorized change or modification is made. This device complies with Part 15 of the FCC`s Rules. Operation is subject to the following two Conditions:1. This device may not cause harmful interference, and2. This device must accept ant interference received, including interference that may cause undesirable operation.To satisfy FCC exterior labeling requirements the following text must be placed on the exterior of the end productTo satisfy FCC exterior labeling requirements, the following text must be placed on the exterior of the end product.Contains Transmitter module FCC ID: YZP-TWFMB001TThe antenna must be installed such that 20 cm is maintained between the antenna and users, and the transmitter module may not be co-located with any other transmitter or antenna. End users cannot modify this transmitter device. Any Unauthorized modification could void the user‘s authority to operate this device.©2010 LGIT. All rights reserved.
S P E C I F I C A T I O NPAGE :DOCUMENT No :REG. DATE : 2010.11.16MODEL NAME : TWFM-B001TREV. DATE : 2010.11.16REV.NO : 1.0HC406454/ 168. Electrical SpecificationsCurrent Consumption Min. Typ. Max. UnitTX Mode ( MCS7) - 470 -mAIdle and Associated state-210-1) DC CharacteristicsItems Contents2) RF Characteristics for IEEE802.11b ( 11Mbps mode unless otherwise specified) mAIdle and Associated state210Radio disabled state - 60 -Specification IEEE802.11bMode DSSS/CCKChannel frequency 2400 ~ 2483 MHz Data rate 1,2,5.5,11MbpsTX Characteristics Min. Typ. Max. UnitPower Level 13 15 17 dBmSpectrum Mask1st side lobes - -38 -30 dBr2nd side lobes - -54 -50 dBrModulation Accuracy (EVM) - - 35 %Power On/Off ramp - - 2.0 UsecSpurious Emissions (BW=100kHz)30-1000MHz - - -36 dBm1000-12750MHz - - -30 dBmRX Characteristics Min. Typ. Max. UnitMinimum Input Level Sens. (FER ≤ 8%) -88 -78 dBm©2010 LGIT. All rights reserved.Maximum Input Level (FER ≤ 8%) -10 - - dBm* Normal Condition : 25℃, VDD=5V.
S P E C I F I C A T I O NPAGE :DOCUMENT No :REG. DATE : 2010.11.16MODEL NAME : TWFM-B001TREV. DATE : 2010.11.16REV.NO : 1.0HC406455/ 16Items ContentsSpecificationIEEE802.11g3) RF Characteristics for IEEE802.11g ( 54Mbps mode unless otherwise specified) SpecificationIEEE802.11gMode OFDMChannel frequency 2400 ~ 2483 MHz Data rate 6,9,12,18,24,36,48,54MbpsTX Characteristics Min. Typ. Max. UnitPower Level 13 15 17 dBmSpectrum Masktf /11MH3221dBat fc +/-11MHz--32-21dBrat fc +/-20MHz - -35 -29 dBrat fc ≥ +/- 30MHz - -45 -41 dBrConstellation Error (EVM) - -28 -25 dBSpurious Emissions (BW=100kHz)30-1000MHz - - -36 dBm1000-12750MHz - - -30 dBmRX Characteristics Min. Typ. Max. UnitMinimum Input Level Sens. (PER ≤ 10%) - -73 -65 dBmMaximum Input Level (PER ≤ 10%) -20 - - dBm©2010 LGIT. All rights reserved.* Normal Condition : 25℃, VDD=5V.
S P E C I F I C A T I O NPAGE :DOCUMENT No :REG. DATE : 2010.11.16MODEL NAME : TWFM-B001TREV. DATE : 2010.11.16REV.NO : 1.0HC406456/ 16Items Contents4) RF Characteristics for IEEE802.11a ( 54Mbps mode unless otherwise specified) Specification IEEE802.11aMode OFDMChannel frequency 5150~5250MHz, 5725 ~ 5850 MHzData rate 6,9,12,18,24,36,48,54MbpsTX Characteristics Min. Typ. Max. UnitPower Level 11 13 15 dBmSpectrum MaskSpectrum Maskat fc +/-11MHz - -32 -21 dBrat fc +/-20MHz - -35 -29 dBrat fc ≥ +/- 30MHz - -45 -41 dBrConstellation Error (EVM) - -28 -25 dBSpurious Emissions (BW=100kHz)30-1000MHz - - -36 dBm1000-12750MHz - - -30 dBmRX Characteristics Min. Typ. Max. UnitMinimum Input Level Sens. (PER ≤ 10%) - -73 -65 dBmMaximum Input Level (PER ≤10%)-20--dBm©2010 LGIT. All rights reserved.Maximum Input Level (PER ≤ 10%)-20--dBm* Normal Condition : 25℃, VDD=5V.
S P E C I F I C A T I O NPAGE :DOCUMENT No :REG. DATE : 2010.11.16MODEL NAME : TWFM-B001TREV. DATE : 2010.11.16REV.NO : 1.0HC406457/ 16Items ContentsSpecification IEEE802.11n – 5GHz5) RF Characteristics for IEEE802.11an( MCS7 mode unless otherwise specified) Mode OFDMChannel frequency 5150~5250MHz, 5725 ~ 5850 MHzData rate 6.5,13,19.5,26,39,52,58.5,65MbpsTX CharacteristicsMinTypMaxUnitTX CharacteristicsMin.Typ.Max.UnitPower Level (HT20 / HT40 : MCS7) 11 13 15 dBmSpectrum Maskat fc +/-11MHz - -32 -21 dBrat fc +/-20MHz - -35 -29 dBrat fc ≥ +/- 30MHz - -45 -41 dBrConstellation Error (EVM) - -29 -28 dBSpurious Emissions (BW=100kHz)30-1000MHz - - -36 dBm1000-12750MHz - - -30 dBmRX Characteristics Min. Typ. Max. UnitMinimum Input Level Sens. (HT20,PER ≤ 10%) --70-64dBmMinimum Input Level Sens. (HT40,PER ≤ 10%) --66-62dBm(%)©2010 LGIT. All rights reserved.Maximum Input Level (PER ≤ 10%)-20 - - dBm* Normal Condition : 25℃, VDD=5V.
S P E C I F I C A T I O NPAGE :DOCUMENT No :REG. DATE : 2010.11.16MODEL NAME : TWFM-B001TREV. DATE : 2010.11.16REV.NO : 1.0HC406458/ 16Items Contents6) RF Characteristics for IEEE802.11gn( MCS7 mode unless otherwise specified) Specification IEEE802.11n – 2.4GHzMode OFDMChannel frequency 2400 ~ 2483 MHzData rate 6.5,13,19.5,26,39,52,58.5,65Mbps,, ,,,, , pTX Characteristics Min. Typ. Max. UnitPower Level (HT20/HT40 : MCS7) 13 15 17 dBmSpectrum Maskat fc +/11MHz3221dBrat fc +/-11MHz--32-21dBrat fc +/-20MHz - -35 -29 dBrat fc ≥ +/- 30MHz - - -45 dBrConstellation Error (EVM) - -29 -28 dBS i E i i (BW 100kH )Spurious Emissions (BW=100kHz)30-1000MHz - - -36 dBm1000-12750MHz - - -30 dBmRX Characteristics Min. Typ. Max. UnitMinimum Input Level Sens. (HT20,PER ≤ 10%) --68-64dBmMinimum Input Level Sens. (HT40,PER ≤ 10%) --66-62dBmM i I t L l (PER ≤10%)20dB©2010 LGIT. All rights reserved.Maximum Input Level (PER ≤ 10%)-20--dBm* Normal Condition : 25℃, VDD=5V.
S P E C I F I C A T I O NPAGE :DOCUMENT No :REG. DATE : 2010.11.16MODEL NAME : TWFM-B001TREV. DATE : 2010.11.16REV.NO : 1.0HC406459/ 169. Environment TestsItem Test Conditions Specifications Initial values are measured at standard test condition.Heat LoadTestLeave samples in 60℃±2℃for 96 ±5 hours, and in standard test condition for 30 minutes, then take measurements within 1 hour.- Supply voltage : standard ±5%- Supply voltage cycle : 1.5h on, 0.5h offHumidityLoad TestInitial values are measured at standard test condition.Leave samples in 40℃±5℃, 90 ~ 95% RH for 96 ±5 hours, and in standard test condition for 30 minutes, then take measurements within 1 hour.- Supply voltage : standard + 5%Supply voltage cycle : 1 5h on 0 5h off•TX Power: ±4dB Max• Min Input Level ±4dB M-Supply voltage cycle : 1.5h on, 0.5h offHigh Temperature TestInitial values are measured at standard test condition.Leave samples in 80℃±2℃for 96 ±5 hours, andin standard ambient for 1 hour with standard powerSupply then take measurements within 1 hour.: ±4dB MaxCold TestInitial values are measured at standard test condition.Leave samples in －40℃±2℃for 96 ±5 hours, andin standard ambient for 1 hour with standard powerSupply then take measurements within 1 hourSupply then take measurements within 1 hour.TemperatureShockTake measurements in standard test condition.Temp. : -40℃~ +85℃Duration : 30 min©2010 LGIT. All rights reserved.ShockRamp-up & Ramp-down for 5 minCycle : 200cycle.
S P E C I F I C A T I O NPAGE :DOCUMENT No :REG. DATE : 2010.11.16MODEL NAME : TWFM-B001TREV. DATE : 2010.11.16REV.NO : 1.0HC4064510 / 1610. Pin DescriptionPin No. Pin Name I/O Pin Description1Wake-upOControl signal for wake-up1WakeupOControl signal for wakeup2 GND - GND3 USB_DP I/O USB Communication signal USB_DP4 USB_DN I/O USB Communication signal USB_DN5 VDD I VDD 5V< TOP View > ①⑤TWFM-B001T001EB2B003391009A290115351616Note.. Recommend a Module install sequence for prevent USB device failure1) Supply 5V power 2) Connect to data signal (USB_DP, USB_DN). If remove the module, proceed in reveres sequence©2010 LGIT. All rights reserved.
S P E C I F I C A T I O NPAGE :DOCUMENT No :REG. DATE : 2010.11.16MODEL NAME : TWFM-B001TREV. DATE : 2010.11.16REV.NO : 1.0HC4064511 / 1611. S/WThe module is controlled by wl command. It is intended for those evaluating and/or testing Broadcom’s IC, describes a subset of the commands available in wl, the Broadcom ® WLAN client utility.1) Command SyntaxThe syntax is as follows:wl <adapter> [-h] [-d|u|x] <command> [arguments]where-h this message and command descriptions-d output format signed integer-u output format unsigned integer-x output format hexdecimalThe [h,u] option is only to print help.Other syntax specifics are as follows:• Entries within square brackets, such as [arguments], are optional. In the above example,switches within brackets, such as –h, are typed as shown. The |symbol should not be typed, it represents the word or.• Entries within angle brackets, such as <adapter>, are required and indicate that a value must be inserted in place of the item contained within the angle brackets.•Entries shown outside of either square or angle brackets are to be typed as shownEntries shown outside of either square or angle brackets are to be typed as shown.2) Command List and Version•CMDSSyntax: wl cmdsPurpose: Generates a list of available commands.pParameters:NoneReturns: All commands available to the attached 43XX chip.•VERSyntax: wl verPurpose: Generates a list of available commands.Parameters:None©2010 LGIT. All rights reserved.Parameters:NoneReturns: All commands available to the attached 43XX chip.•Please refer to ‘80211-TI201-R’ technical document of Broadcom to other commands.
12/20/2010 CTJ5MCONFIDENTIAL FOR LG INNOTEK CO LTD Preliminary Data SheetBCM4323643236-DS04-R5300 California Avenue • Irvine, CA 92617 • Phone: 949-926-5000 • Fax: 949-926-5203 December 17, 20102.4 GHz/5 GHz IEEE802.11n MAC/PHY/Radio ChipGENERAL DESCRIPTIONFEATURESThe BCM43236 is a dual-band (2.4 GHz and 5 GHz) IEEE 802.11n-compliant MAC/PHY/Radio complete system-on-a-chip with 2.4 GHz and 5 GHz internal PAs. The device enables the development of USB 2.0- or HSIC-based IEEE 802.11n WLAN client and router subsystem solutions. The BCM43236 is targeted for all WLAN markets that can take advantage of the high throughput and extended range of the Broadcom second-generation MIMO solution. With MIMO, information is sent and received over two or more antennas simultaneously using the same frequency band thus providing greater range and increasing throughput, while maintaining compatibility with legacy IEEE 802.11a/b/g devices. This is accomplished through a combination of enhanced MAC and PHY implementations including spatial multiplexing modes in the transmitter and receiver and advanced digital signal processing techniques to improve receive sensitivity.The BCM43236 architecture with its fully integrated dual-band radio transceiver supports 2 × 2 antennas for Layer 2 throughput of over 200 Mbps. State-of-the-art security is provided by industry standardized system support for WPA™, WPA2™ (IEEE 802.11i), and hardware-accelerated AES encryption/decryption, coupled with TKIP and IEEE 802.1X support. Embedded hardware acceleration enables increased system performance and significant reduction in host-CPU utilization in both client and access point configurations. The BCM43236 also supports Broadcom’s widely accepted and deployed WPS for ease-of-use wireless secured networks.• IEEE 802.11n-compliant• 2.4 GHz and 5 GHz internal PA• Two-stream spatial multiplexing up to 300 Mbps• Uses on-chip OTP (One-Time Programmable) memory instead of SROM for substantial RBOM savings.• Supports MCS 0–15 and MCS 32 modulation and coding rates.• Supports 20 MHz and 40 MHz channels with optional SGI.• Support for STBC in both TX and RX• Greenfield, mixed mode, and legacy modes supported• Full IEEE 802.11a/b/g legacy compatibility with enhanced performance.• Supports one USB 2.0 host port or one 480 MHz HSIC port.• UART and JTAG interface, up to eight GPIOs.• Supports up to 32 MB of serial Flash™ memory.• ARM® Cortex-M3™ CPU core plus 256 KB ROM and 448 KB RAM.• Supports Broadcom’s OneDriver™ software. • Supports WHQL certified drivers for Windows® Vista 32- and 64-bit, Windows® XP, and Windows 2000 operating systems for client applications. • Supports Linux® and VxWorks® for access point and router applications.• Comprehensive wireless network security support that includes WPA, WPA2, and AES encryption/decryption coupled with TKIP and IEEE 802.1X support.• BCM43236 package: 10 mm x 10 mm 88-pin QFNAPPLICATIONS• USB 2.0 dongles• HSIC media modules
12/20/2010 CTJ5MCONFIDENTIAL FOR LG INNOTEK CO LTD Revision HistoryBROADCOM 2.4 GHz/5 GHz 802.11n MAC/PHY/Radio Chip December 17, 2010 • 43236-DS04-R Page 2®BCM43236 Preliminary Data SheetFigure 1: BCM43236 Block Diagram802.11n MAC IEEE 802.11n PHY USB 2.0 Device or HSICOTP (2 Kbits)JTAGGPIOLEDSecurityRF Front End Internal Bus(Switches)2 × 2 Radio2.4-Ghz PA5-Ghz PABCM43236Serial FlashInterfaceFlash Memory
12/20/2010 CTJ5MCONFIDENTIAL FOR LG INNOTEK CO LTD Revision HistoryBROADCOM 2.4 GHz/5 GHz 802.11n MAC/PHY/Radio Chip December 17, 2010 • 43236-DS04-R Page 3®BCM43236 Preliminary Data SheetRevision HistoryRevision Date Change Description43236-DS04-R 12/17/10 Updated:•Table 7: “Current Consumption from 3.3V Supply,” on page 28•Table 8: “Current Consumption from 1.2V Supply,” on page 28•Figure 11: “BCM43236 Mechanical Drawing,” on page 3943236-DS03-R 07/19/10 Updated:• Section 3: “Pin Assignments,” on page 20.• Table 3: “Signal Descriptions,” on page 22.• Table 5: “Absolute Maximum Ratings,” on page 27.• Section 8: “Thermal Information,” on page 38.• Section 10: “Ordering Information,” on page 40.Added:• “HSIC Characteristics” on page 29.43236-DS02-R 07/05/10 Updated:• Figure 8: “BCM43236 88-Pin QFN Package,” on page 19.• Table 2: “Pin Assignments,” on page 20.• Table 3: “Signal Descriptions,” on page 21.43236-DS01-R 04/30/10 Updated:• Table 2: “Pin Assignments,” on page 19.• Figure 7: “BCM43236 88-Pin QFN Package,” on page 18.• Table 3: “Signal Descriptions,” on page 20.• Table 4: “Strapping Options,” on page 24.• Table 5: “Absolute Maximum Ratings,” on page 25.• Table 6: “Recommended Operating Conditions and DC Characteristics,” on page 26.• Table 10: “2.4 GHz Band Receiver RF Specifications,” on page 27.• Table 11: “2.4 GHz Band Transmitter RF Specifications,” on page 29.• Table 13: “5 GHz Band Receiver RF Specifications,” on page 30.• Table 14: “5 GHz Band Transmitter RF Specifications,” on page 31.• Table 19: “88-Pin QFN Thermal Characteristics,” on page 35.• Table 20: “Ordering Information,” on page 37.Added:• Table 7: “Current Consumption from 3.3V Supply,” on page 26.• Table 8: “Current Consumption from 1.2V Supply,” on page 26.43236-DS00-R 10/20/09 Initial release
12/20/2010 CTJ5MCONFIDENTIAL FOR LG INNOTEK CO LTD Broadcom®, the pulse logo, Connecting everything®, and the Connecting everything logo are among the trademarks of Broadcom Corporation and/or its affiliates in the United States, certain other countries and/or the EU. Any other trademarks or trade names mentioned are the property of their respective owners.Any recommendations or changes to this document can be submitted to MCBUMktg@broadcom.com.This data sheet (including, without limitation, the Broadcom component(s) identified herein) is not designed, intended, or certified for use in any military, nuclear, medical, mass transportation, aviation, navigations, pollution control, hazardous substances management, or other high risk application. BROADCOM PROVIDES THIS DATA SHEET "AS-IS", WITHOUT WARRANTY OF ANY KIND. BROADCOM DISCLAIMS ALL WARRANTIES, EXPRESSED AND IMPLIED, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT. Broadcom Corporation5300 California AvenueIrvine, CA 92617© 2010 by Broadcom CorporationAll rights reservedPrinted in the U.S.A.
12/20/2010 CTJ5MCONFIDENTIAL FOR LG INNOTEK CO LTD Table of Contents BCM43236 Preliminary Data SheetBROADCOM 2.4 GHz/5 GHz 802.11n MAC/PHY/Radio Chip December 17, 2010 • 43236-DS04-R Page 5®Table of ContentsSection 1: Introduction...................................................................................................... 9Section 2: Functional Description .................................................................................... 11Global Functions...........................................................................................................................................11Power Management ..............................................................................................................................11Voltage Regulators.................................................................................................................................11Reset ......................................................................................................................................................11GPIO Interface........................................................................................................................................11Bluetooth Coexistence Interface ...........................................................................................................12OTP.........................................................................................................................................................12JTAG Interface........................................................................................................................................12UART Interface.......................................................................................................................................12Serial Flash™ Interface...........................................................................................................................12USB/HSIC Interface ................................................................................................................................13Crystal Oscillator ....................................................................................................................................14IEEE 802.11n MAC Description.....................................................................................................................15IEEE 802.11n PHY Description ......................................................................................................................17Dual-Band Radio Transceiver.......................................................................................................................19Receiver Path .........................................................................................................................................19Transmitter Path ....................................................................................................................................19Calibration..............................................................................................................................................19Section 3: Pin Assignments.............................................................................................. 20BCM43236 88-Pin QFN Assignments ...........................................................................................................20Signals by Pin Number ...........................................................................................................................21Section 4: Signal and Pin Descriptions ............................................................................. 22Package Signal Descriptions.........................................................................................................................22Strapping Options.........................................................................................................................................26Section 5: Electrical Characteristics.................................................................................. 27Absolute Maximum Ratings.........................................................................................................................27Recommended Operating Conditions and DC Characteristics....................................................................28Current Consumption from the 3.3V Supply ...............................................................................................28Current Consumption from the 1.2V Supply ...............................................................................................28
12/20/2010 CTJ5MCONFIDENTIAL FOR LG INNOTEK CO LTD Table of Contents BROADCOM 2.4 GHz/5 GHz 802.11n MAC/PHY/Radio Chip December 17, 2010 • 43236-DS04-R Page 6®BCM43236 Preliminary Data SheetHSIC Characteristics......................................................................................................................................29Section 6: RF Specifications ............................................................................................. 302.4 GHz Band General RF Specifications ......................................................................................................302.4 GHz Band Receiver RF Specifications.....................................................................................................312.4 GHz Band Transmitter RF Specifications................................................................................................322.4 GHz Band Local Oscillator Specifications...............................................................................................325 GHz Band Receiver RF Specifications ........................................................................................................335 GHz Band Transmitter RF Specifications...................................................................................................345 GHz Band Local Oscillator Frequency Generator Specifications ..............................................................34On-Chip Regulator Power Supply Characteristics .......................................................................................35Section 7: Timing Characteristics ..................................................................................... 36Reset and Clock Timing Diagram..................................................................................................................36Serial Flash Timing Diagram .........................................................................................................................37Section 8: Thermal Information....................................................................................... 38Junction Temperature Estimation and PSIJT Versus ThetaJC .......................................................................38Section 9: Package Information ....................................................................................... 39Section 10: Ordering Information .................................................................................... 40
12/20/2010 CTJ5MCONFIDENTIAL FOR LG INNOTEK CO LTD List of Figures BCM43236 Preliminary Data SheetBROADCOM 2.4 GHz/5 GHz 802.11n MAC/PHY/Radio Chip December 17, 2010 • 43236-DS04-R Page 7®List of FiguresFigure 1: BCM43236 Block Diagram ...................................................................................................................2Figure 2: MIMO System Diagram Showing 2 × 2 Antenna Configuration ..........................................................9Figure 3: Functional Block Diagram..................................................................................................................10Figure 4: USB 2.0 Device/HSIC Core Block Diagram .........................................................................................13Figure 5: Recommended Oscillator Configuration ...........................................................................................15Figure 6: Enhanced MAC Block Diagram ..........................................................................................................16Figure 7: PHY Block Diagram ............................................................................................................................18Figure 8: BCM43236 88-Pin QFN Package........................................................................................................20Figure 9: Timing for the Optional External Power-On Reset............................................................................36Figure 10: Serial Flash Timing Diagram (STMicroelectronics-Compatible).......................................................37Figure 11: BCM43236 Mechanical Drawing .....................................................................................................39
12/20/2010 CTJ5MCONFIDENTIAL FOR LG INNOTEK CO LTD List of Tables BCM43236 Preliminary Data SheetBROADCOM 2.4 GHz/5 GHz 802.11n MAC/PHY/Radio Chip December 17, 2010 • 43236-DS04-R Page 8®List of TablesTable 1: Crystal Oscillator Requirements .........................................................................................................14Table 2: Pin Assignments..................................................................................................................................21Table 3: Signal Descriptions..............................................................................................................................22Table 4: Strapping Options...............................................................................................................................26Table 5: Absolute Maximum Ratings................................................................................................................27Table 6: Recommended Operating Conditions and DC Characteristics ...........................................................28Table 7: Current Consumption from 3.3V Supply.............................................................................................28Table 8: Current Consumption from 1.2V Supply.............................................................................................28Table 9: HSIC Characteristics............................................................................................................................29Table 10: 2.4 GHz Band General RF Specifications...........................................................................................30Table 11: 2.4 GHz Band Receiver RF Specifications..........................................................................................31Table 12: 2.4 GHz Band Transmitter RF Specifications.....................................................................................32Table 13: 2.4 GHz Band Local Oscillator Specifications ....................................................................................32Table 14: 5 GHz Band Receiver RF Specifications.............................................................................................33Table 15: 5 GHz Band Transmitter RF Specifications........................................................................................34Table 16: 5 GHz Band Local Oscillator Frequency Generator Specifications....................................................34Table 17: On-Chip Regulator Power Supply Characteristics.............................................................................35Table 18: Ext_por and Clock Timing .................................................................................................................36Table 19: Serial Flash Timing ............................................................................................................................37Table 20: 88-Pin QFN Thermal Characteristics.................................................................................................38Table 21: Ordering Information .......................................................................................................................40
12/20/2010 CTJ5MCONFIDENTIAL FOR LG INNOTEK CO LTD IntroductionBROADCOM 2.4 GHz/5 GHz 802.11n MAC/PHY/Radio Chip December 17, 2010 • 43236-DS04-R Page 9®BCM43236 Preliminary Data SheetSection 1: IntroductionThe BCM43236 is the latest innovative chip from Broadcom® based on IEEE 802.11n. The chip is designed to take current WLAN systems to the next level of higher performance and greater range with Multiple Input Multiple Output (MIMO) technology as shown in Figure 2. The IEEE 802.11n standard more than doubles the spectral efficiency compared to that of current IEEE 802.11a/g WLANs.Figure 2: MIMO System Diagram Showing 2 × 2 Antenna ConfigurationEmploying a native 32-bit bus with Direct Memory Access (DMA) architecture, the BCM43236 offers significant performance improvements in transfer rates, CPU utilization, and flexible support for USB 2.0 devices.Figure 3 on page 10 shows a block diagram of the device.BCM43236 BCM43236 IEEE 802.11n MAC/PHYIEEE 802.11n 2.4-/5-GHz Radio Transceiver with Integrated PAsRF SwitchesHostI/F RF SwitchesIEEE 802.11n MAC/PHYIEEE 802.11n 2.4-/5-GHz Radio Transceiver with Integrated PAsHostI/F
12/20/2010 CTJ5MCONFIDENTIAL FOR LG INNOTEK CO LTD IntroductionBROADCOM 2.4 GHz/5 GHz 802.11n MAC/PHY/Radio Chip December 17, 2010 • 43236-DS04-R Page 10®BCM43236 Preliminary Data SheetFigure 3: Functional Block DiagramBCM43236Internal Bus SystemIEEE802.11nPHY2.4/5 GHz RadioSecurityRFControlUARTJTAGInterfaceUART_RXUART_TXGPIOPLL 20 MHz Ref. ClockSFLASH InterfaceROM(256 KB)ARMCortexM3RAM(448 KB)USB 2.0Deviceor HSICIEEE 802.11nMACGPIO[0:7]antenna switch controls (10)ext_lna_2g controls (4)ext_lna_5g controls (4)pa_2g controls (2)pa_5g controls (2)USB20_DEV_DPLSUSB20_DEV_DMNSHSIC DataHSIC StrobeTRST#TMSTDITCLKTDOtssiln_0tssiln_1lna_p_a_0lna_p_a_1lna_p_g_0lna_p_g_0pa_p_a_0pa_p_a_1pa_p_g_0pa_p_g_1xtal_buf_outxtal_outxtal_insflash_dextif_flash_cs_lsflash_csflash_q
12/20/2010 CTJ5MCONFIDENTIAL FOR LG INNOTEK CO LTD Functional DescriptionBROADCOM 2.4 GHz/5 GHz 802.11n MAC/PHY/Radio Chip December 17, 2010 • 43236-DS04-R Page 11®BCM43236 Preliminary Data SheetSection 2: Functional DescriptionGlobal FunctionsPower Management The BCM43236 has been designed with the stringent power consumption requirements of battery-powered hosts in mind. All areas of the chip design were scrutinized to help reduce power consumption. Silicon processes and cell libraries were chosen to reduce leakage current and supply voltages. Additionally, the BCM43236 includes an advanced Power Management Unit (PMU). The PMU provides significant power savings by putting the BCM43236 into various power management states appropriate to the current environment and activities that are being performed. The power management unit enables and disables internal regulators, switches, and other blocks based on a computation of the required resources and a table that describes the relationship between resources and the time needed to enable and disable them. Power-up sequences are fully programmable. Configurable, free-running counters in the PMU are used to turn on/off individual regulators and power switches. Clock speeds are dynamically changed (or gated altogether) for the current mode. Slower clock speeds are used wherever possible. Voltage RegulatorsThree Low-Dropout (LDO) regulators and a PMU are integrated into the BCM43236. All regulators are programmable via the PMU.ResetResets are generated internally by the BCM43236. An optional external power-on reset circuit can be connected to the active-low Ext_por input pin. A 50 ms low pulse is recommended to guarantee that a sufficiently long reset is applied to all internal circuits, including integrated PHYs. The initialization process loads all pin-configurable modes, resets all internal processes, and puts the device in the idle state. During initialization, the clock source input signal must be active, and the 3.3V power supply to the device must be stable. The external power-on reset overrides the BCM43236 internal reset.GPIO InterfaceThere are eight General-Purpose I/O (GPIO) pins provided on the BCM43236. They are multiplexed with the control signals. These pins can be used to attach to various external devices. Upon power-up and reset, these pins become tristated. Subsequently, they can be programmed to be either input or output pins via the GPIO control register. A programmable internal pull-up/pull-down resistor is included on each GPIO. If a GPIO output enable is not asserted, and the corresponding GPIO signal is not being driven externally, the GPIO state is determined by its programmable resistor.
12/20/2010 CTJ5MCONFIDENTIAL FOR LG INNOTEK CO LTD Global FunctionsBROADCOM 2.4 GHz/5 GHz 802.11n MAC/PHY/Radio Chip December 17, 2010 • 43236-DS04-R Page 12®BCM43236 Preliminary Data SheetBluetooth Coexistence InterfaceA 5-wire handshake interface is provided to enable signalling between the device and an external Bluetooth device host to manage sharing of the wireless medium for optimum performance. The signals provided are:•btcx_tx_conf• btcx_rf_active• btcx_status•btcx_prisel•btcx_freqOTPThe BCM43236 contains an on-chip One-Time-Programmable (OTP) area that can be used for nonvolatile storage of WLAN information such as a MAC address and other hardware-specific parameters. The total area available for programming is 2 Kbits.JTAG InterfaceThe BCM43236 supports the IEEE 1149.1 JTAG boundary-scan standard for testing the device packaging and PCB manufacturing.UART InterfaceOne UART interface is provided that can be attached to RS-232 Data Termination Equipment (DTE) for exchanging and managing data with other serial devices. The UART interface is primarily used for debugging and development. Serial Flash™ InterfaceSerial Flash™ is available regardless of whether USB 2.0 operation is enabled or disabled. The Flash interface is an STMicroelectronics®-compatible 4-pin interface.Note: These five pins are muxed with the JTAG interface.
12/20/2010 CTJ5MCONFIDENTIAL FOR LG INNOTEK CO LTD Global FunctionsBROADCOM 2.4 GHz/5 GHz 802.11n MAC/PHY/Radio Chip December 17, 2010 • 43236-DS04-R Page 13®BCM43236 Preliminary Data SheetUSB/HSIC InterfaceThe BCM43236 USB/HSIC interface can be set to operate as a USB 2.0 port or a High-Speed Inter-Chip (HSIC) port. Features of the interface are:• USB 2.0 protocol engine:– Parallel Interface Engine (PIE) between packet buffers and USB transceiver– Supports up to nine endpoints, including Configurable Control Endpoint 0• Separate endpoint packet buffers with a 512-byte FIFO buffer each• Host-to-device communication for bulk, control, and interrupt transfers• Configuration/status registers• The HSIC port can communicate with an external HSIC host, such as the BCM5357 and BCM5358.The various blocks in the USB 2.0 device/HSIC core are shown in Figure 4. Figure 4: USB 2.0 Device/HSIC Core Block DiagramThe USB 2.0 PHY handles the USB protocol and the serial signaling interface between the host and device. It is primarily responsible for data transmission and recovery. On the transmit side, data is encoded, along with a clock, using the NRZI scheme with bit stuffing to ensure that the receiver detects a transition in the data stream. A SYNC field that precedes each packet enables the receiver to synchronize the data and clock recovery circuits. On the receive side, the serial data is deserialized, unstuffed, and checked for errors. The recovered data and clock are then shifted to the clock domain that is compatible with the internal bus logic.USB 2.0 Deviceor HSICTXFIFOTXFIFOTXFIFOTXFIFOTXFIFOsDMA EnginesRXFIFOEndpoint Management UnitUSB 2.0 Protocol EngineHSIC PHY USB 2.0 PHYData Strobe D+ D-32-bit On-Chip Communication System
12/20/2010 CTJ5MCONFIDENTIAL FOR LG INNOTEK CO LTD Global FunctionsBROADCOM 2.4 GHz/5 GHz 802.11n MAC/PHY/Radio Chip December 17, 2010 • 43236-DS04-R Page 14®BCM43236 Preliminary Data SheetThe endpoint management unit contains the PIE control logic and the endpoint logic. The PIE interfaces between the packet buffers and the USB transceiver. It handles packet identification (PID), USB packets, and transactions.The endpoint logic contains nine uniquely-addressable endpoints. These endpoints are the source or sink of communication flow between the host and the device. Endpoint zero is used as a default control port for both the input and output directions. The USB system software uses this default control method to initialize and configure the device information, and allows USB status and control access. Endpoint zero is always accessible after a device is attached, powered, and reset.Endpoints are supported by 512-byte FIFO buffers, one for each IN endpoint and one shared by all OUT endpoints. Both TX and RX data transfers support a DMA burst of 4, which guarantees low latency and maximum throughput performance. The RX FIFO can never overflow by design. The maximum USB packet size cannot be more than 512 bytes. Finally, the BCM43236 is either configured as a USB 2.0 device or as a PHY-less HSIC by selecting the appropriate strapping option. See Table 4 on page 26 for information on how to select the strapping options.Crystal OscillatorTable 1 lists the requirements for the crystal oscillator.Table 1: Crystal Oscillator Requirements Parameter ValueFrequency 20 MHzMode AT cut, fundamentalLoad capacitance 16 pFESR 50Ω maximumFrequency stability ±10 ppm at 25°C±10 ppm at 0°C to +85°CAging ±3 ppm/year max first year, ±1 ppm thereafterDrive level 300 µW maximumQ-factor 40,000 minimumShunt capacitance < 5 pF
12/20/2010 CTJ5MCONFIDENTIAL FOR LG INNOTEK CO LTD IEEE 802.11n MAC DescriptionBROADCOM 2.4 GHz/5 GHz 802.11n MAC/PHY/Radio Chip December 17, 2010 • 43236-DS04-R Page 15®BCM43236 Preliminary Data SheetFigure 5 shows the recommended oscillator configuration. Figure 5: Recommended Oscillator ConfigurationIEEE 802.11n MAC DescriptionThe IEEE 802.11n MAC features include:• Enhanced MAC for supporting IEEE 802.11n features• Programmable Access Point (AP) or Station (STA) functionality• Programmable Independent Basic Service Set (IBSS) or infrastructure mode• Aggregated MPDU (MAC Protocol Data Unit) support for High-throughput (HT)• Passive scanning• Network Allocation Vector (NAV), Interframe Space (IFS), and Timing Synchronization Function (TSF) functionality• RTS/CTS procedure• Transmission of response frames (ACK/CTS)• Address filtering of receive frames as specified by IBSS rules• Multirate support• Programmable Target Beacon Transmission Time (TBTT), beacon transmission/cancellation and programmable Announcement Traffic Indication Message (ATIM) window• CF conformance: Setting NAV for neighborhood Point Coordination Function (PCF) operation• Security through a variety of encryption schemes including WEP, TKIP, AES, WPA™, WAP2™, and IEEE 802.1X• Power management• Statistics counters for MIB supportThe MAC core supports the transmission and reception of sequences of packets, together with related timing, without any packet-by-packet driver interaction. Time-critical tasks requiring response times of only a few milliseconds are handled in the MAC core. This achieves the required timing on the medium while keeping the host driver easier to write and maintain. Also, incoming packets are buffered in the MAC core, which allows the MAC driver to process them in bursts, enabling high bandwidth performance.1M27 pF27 pF221OCS INOCS OUTNOTE: See Reference Schematics
12/20/2010 CTJ5MCONFIDENTIAL FOR LG INNOTEK CO LTD IEEE 802.11n MAC DescriptionBROADCOM 2.4 GHz/5 GHz 802.11n MAC/PHY/Radio Chip December 17, 2010 • 43236-DS04-R Page 16®BCM43236 Preliminary Data SheetThe MAC driver interacts with the MAC core to prepare queues of packets to transmit and to analyze and forward received packets to upper software layers. The internal blocks of the MAC core are connected to a Programmable State Machine (PSM) through the host interface that connects to the internal bus (see Figure 6). Figure 6: Enhanced MAC Block DiagramThe host interface consists of registers for controlling and monitoring the status of the MAC core and interfacing with the TX/RX FIFOs. For transmit, a total of 128 KB FIFO buffering is available that can be dynamically allocated to six transmit queues plus template space for beacons, ACKs, and probe responses. Whenever the host has a frame to transmit, the host queues the frame into one of the transmit FIFOs with a TX descriptor containing TX control information. The PSM schedules the transmission on the medium depending on the frame type, transmission rules in IEEE 802.11 protocol, and the current medium occupancy scenario. After the transmission is completed, a TX status is returned to the host, informing the host of the result that got transmitted.The MAC contains a single 10 KB RX FIFO. When a frame is received, it is sent to the host along with an RX descriptor that contains additional information about the frame reception conditions.The power management block maintains the information regarding the power management state of the core (and the associated STAs in case of an AP) to help in dynamic decisions by the core regarding frame transmission.The wireless security engine performs the required encryption/decryption on the TX/RX frames. This block supports separate transmit and receive keys with four shared keys and 50 link-specific keys. The link-specific keys are used to establish a secure link between any two STAs, with the required key being shared between only those two STAs, hence excluding all of the other STAs in the same network from deciphering the communication between those two STAs. The wireless security engine supports the following encryption schemes that can be selected on a per-destination basis:• None: The wireless security engine acts as a pass-through• WEP: 40-bit secure key and 24-bit IV as defined in IEEE Std. 802.11-2007• WEP128: 104-bit secure key and 24-bit IV• TKIP: IEEE Std. 802.11-2007• AES: IEEE Std. 802.11-2007Host Interface(Host Registers)TX Status FIFO Six TX FIFOs Template RX FIFO Code MemoryPHY InterfaceData MemoryPower Management Wireless Security Engine Programmable State Machine (PSM)Timing and ControlTX Engine RX Engine
12/20/2010 CTJ5MCONFIDENTIAL FOR LG INNOTEK CO LTD IEEE 802.11n PHY DescriptionBROADCOM 2.4 GHz/5 GHz 802.11n MAC/PHY/Radio Chip December 17, 2010 • 43236-DS04-R Page 17®BCM43236 Preliminary Data SheetThe transmit engine is responsible for the byte flow from the TX FIFO to the PHY interface through the encryption engine and the addition of an FCS (CRC-32) as required by IEEE 802.11-2007. Similarly, the receive engine is responsible for byte flow from the PHY interface to the RX FIFO through the decryption engine and for detection of errors in the RX frame.The timing block performs the TSF, NAV, and IFS functionality as described in IEEE Std. 802.11-2007.The Programmable State Machine (PSM) coordinates the operation of different hardware blocks required for both transmission and reception. The PSM also maintains the statistics counters required for MIB support.IEEE 802.11n PHY DescriptionThe PHY features include:• Programmable data rates from MCS 0–15 in 20 MHz and 40 MHz channels, as specified in IEEE 802.11n.• Support for Short Guard Interval (SGI) and Space-Time Block Coding (STBC)• All scrambling, encoding, forward error correction, and modulation in the transmit direction, and inverse operations in the receive direction• Advanced digital signal processing technology for best-in-class receive sensitivity• Both mixed-mode and optional greenfield preamble of IEEE 802.11n• Both long and optional short preambles of IEEE 802.11b• Resistance to multipath (>250 nanoseconds RMS delay spread) with maximal ratio combining for high throughput and range performance, including improved performance in legacy mode over existing IEEE 802.11a/b/g solutions.• Automatic Gain Control (AGC)• Available per-packet channel quality and signal strength measurementsThe dual PHYs integrated in the BCM43236 provide baseband processing at all mandatory data rates specified in IEEE 802.11n up to 300 Mbps, and the legacy rates specified in IEEE 802.11a/b/g including 1, 2, 5.5, 6, 9, 11, 12, 18, 24, 36, 48, and 54 Mbps. This core acts as an intermediary between the MAC and the dual-band 2.4/5 GHz radio, converting back and forth between packets and baseband waveforms.
12/20/2010 CTJ5MCONFIDENTIAL FOR LG INNOTEK CO LTD IEEE 802.11n PHY DescriptionBROADCOM 2.4 GHz/5 GHz 802.11n MAC/PHY/Radio Chip December 17, 2010 • 43236-DS04-R Page 18®BCM43236 Preliminary Data SheetFigure 7: PHY Block DiagramDescramble and DeframeTiming and Frequency Correction TX FSM RX FSM MAC Interface ADC ADC Rake Receiver and DPSK Demodulation Equalizer and CCK Demodulation DAC DAC TX Filter TX Filter Modulate/Spread Frame and Scramble PHY-to-Radio Interface Sync/AGC PHY Registers MIMO OFDM
12/20/2010 CTJ5MCONFIDENTIAL FOR LG INNOTEK CO LTD Dual-Band Radio TransceiverBROADCOM 2.4 GHz/5 GHz 802.11n MAC/PHY/Radio Chip December 17, 2010 • 43236-DS04-R Page 19®BCM43236 Preliminary Data SheetDual-Band Radio TransceiverIntegrated into the BCM43236 is Broadcom's world-class dual-band radio transceiver that ensures low power consumption and robust communications for low-cost applications operating in the 2.4 GHz and 5 GHz bands. Channel bandwidths of 20 MHz and 40 MHz are supported as specified in IEEE 802.11n. Receiver PathThe BCM43236 has a wide dynamic range, direct conversion receiver. It employs high order on-chip channel filtering to ensure reliable operation in the noisy 2.4 GHz ISM band or the entire 5 GHz U-NII band. The excellent noise figure of the receiver makes an external LNA unnecessary.Transmitter PathBaseband data is modulated and upconverted to the 2.4 GHz ISM band or the 5 GHz U-NII bands, respectively. Linear on-chip Power Amplifiers are included, which are capable of delivering a nominal output power exceeding +15 dBm while meeting the IEEE 802.11a and 802.11g specifications. The TX gain has a 78 dB range with a resolution of 0.25 dB.CalibrationThe BCM43236 features dynamic on-chip calibration, eliminating process variation across components. This enables the device to be used in high-volume applications because calibration routines are not required during manufacturing testing. These calibration routines are performed periodically in the course of normal radio operation.
12/20/2010 CTJ5MCONFIDENTIAL FOR LG INNOTEK CO LTD Pin AssignmentsBROADCOM 2.4 GHz/5 GHz 802.11n MAC/PHY/Radio Chip December 17, 2010 • 43236-DS04-R Page 20®BCM43236 Preliminary Data SheetSection 3: Pin AssignmentsThis sections contains pin assignments and ballout information for the BCM43236 (88-pin) packages.BCM43236 88-Pin QFN AssignmentsFigure 8: BCM43236 88-Pin QFN Package 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67VDDmimophy_core0_ant1_rxmimophy_core0_ant1_txgpio_6gpio_5VDDIOgpio_4gpio_3gpio_2gpio_1gpio_0VDDVDDIO/OTP_VDDUSB_RREFHSIC_STRBHSIC_DATAUSB AVDD 1p2USB_DMNSUSB_DPLSUSB_AVDD3p3USB_MONCDRUSBAVDD2p51 VDDIOBCM43236 10 x 10 QFNVDD 662sflash_cs_l mimophy_core1_ant1_rx 653sflash_q mimophy_core1_ant1_tx 644sflash_c VDDIO 635sflash_d UART_RX 626 mimophy_core0_ant0_tx UART_TX 617 mimophy_core0_ant0_rx VDD 608VDD VDDPLL/RF_AVDD_1p2 599 mimophy_core1_ant0_tx USBLDO_2p5_out 5810 mimophy_core1_ant0_rx LDO_3p3_in 5711 VDDIO VREF 5612 VDD PAREF 5513 gpio_7 PAREF_CTL1 5414 jtag_trst_l PAREF_CTL2 5315 jtag_tdi Ext_por 5216 jtag_tck xtal_buf_out 5117 analog_wlan_iqtest_VDD1p2 i_xtal_VDD2p5/o_xtal_VDD2p5 5018 jtag_tms xtal_in 4919 jtag_tdo xtal_out 4820 analog_wlan_iqtest_qp synth_VDD1p2 4721 analog_wlan_iqtest_qn synth_vco_VDD1p2 4622 analog_wlan_iqtest_in vreg3p3_VDD3p3 45analog_wlan_iqtest_ipGndpa_5g_core1_VDD3p3PA_5g_core1tx_5g_core1_VDD1p2rf_5g_antenna_core1core1_VDD1p2rf_2g_antenna_core1tx_2g_core1_VDD1p2pa_2g_core1_VDD3p3PA_2g_core1pa_5g_core0_VDD3p3PA_5g_core0tx_5g_core0_VDD1p2rf_5g_antenna_core0core0_VDD1p2rf_2g_antenna_core0tx_2g_core0_VDD1p2pa_2g_core0_VDD3p3PA_2g_core0gpiao_GPIO_PADrcal_res_ext_core23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
12/20/2010 CTJ5MCONFIDENTIAL FOR LG INNOTEK CO LTD BROADCOM 2.4 GHz/5 GHz 802.11n MAC/PHY/Radio Chip December 17, 2010 • 43236-DS04-R Page 21®BCM43236 88-Pin QFN AssignmentsBCM43236 Preliminary Data SheetSignals by Pin NumberTable 2: Pin AssignmentsPin Signal Name1 VDDIO2sflash_cs_l3sflash_q4sflash_c5sflash_d6 mimophy_core0_ant0_tx7 mimophy_core0_ant0_rx8VDD9 mimophy_core1_ant0_tx10 mimophy_core1_ant0_rx11 VDDIO12 VDD13 gpio_714 jtag_trst_l15 jtag_tdi16 jtag_tck17 analog_wlan_iqtest_VDD1p218 jtag_tms19 jtag_tdo20 analog_wlan_iqtest_qp21 analog_wlan_iqtest_qn22 analog_wlan_iqtest_in23 analog_wlan_iqtest_ip24 Gnd 25 pa_5g_core1_VDD3p326 PA_5g_core127 tx_5g_core1_VDD1p228 rf_5g_antenna_core129 core1_VDD1p230 rf_2g_antenna_core131 tx_2g_core1_VDD1p232 pa_2g_core1_VDD3p333 PA_2g_core134 pa_5g_core0_VDD3p335 PA_5g_core036 tx_5g_core0_VDD1p237 rf_5g_antenna_core038 core0_VDD1p239 rf_2g_antenna_core040 tx_2g_core0_VDD1p241 pa_2g_core0_VDD3p342 PA_2g_core043 gpiao_GPIO_PAD44 rcal_res_ext_core45 vreg3p3_VDD3p3Pin Signal Name46 synth_vco_VDD1p247 synth_VDD1p248 xtal_out49 xtal_in50 i_xtal_VDD2p5/o_xtal_VDD2p551 xtal_buf_out52 Ext_por53 PAREF_CTL254 PAREF_CTL155 PAREF56 VREF57 LDO_3p3_in58 USBLDO_2p5_out59 VDDPLL/RF_AVDD_1p260 VDD61 UART_TX62 UART_RX63 VDDIO64 mimophy_core1_ant1_tx65 mimophy_core1_ant1_rx66 VDD67 USBAVDD2p5Pin Signal Name68 USB_MONCDR69 USB_AVDD3p370 USB_DPLS71 USB_DMNS72 USB AVDD 1p273 HSIC_DATA74 HSIC_STRB75 USB_RREF76 VDDIO/OTP_VDD77 VDD78 gpio_079 gpio_180 gpio_281 gpio_382 gpio_483 VDDIO84 gpio_585 gpio_686 mimophy_core0_ant1_tx87 mimophy_core0_ant1_rx88 VDDPin Signal Name
12/20/2010 CTJ5MCONFIDENTIAL FOR LG INNOTEK CO LTD Signal and Pin DescriptionsBROADCOM 2.4 GHz/5 GHz 802.11n MAC/PHY/Radio Chip December 17, 2010 • 43236-DS04-R Page 22®BCM43236 Preliminary Data SheetSection 4: Signal and Pin DescriptionsPackage Signal DescriptionsThe signal name, type, and description of each pin in the BCM43236 88-pin QFN package is listed in Table 3. The symbols shown under Type indicate pin directions (I/O = bidirectional, I = input, O = output) and the internal pull-up/pull-down characteristics (PU = weak internal pull-up resistor and PD = weak internal pull-down resistor), if any. See also Table 4 on page 26 for resistor strapping options.Table 3: Signal Descriptions Signal BCM43236 Type DescriptionCrystal Oscillatorxtal_in 49 I XTAL oscillator input. Connect a 20 MHz, 10 ppm crystal between the xtal_in and xtal_out pins.xtal_out 48 O XTAL oscillator outputxtal_buf_out 51 O Buffered XTAL outputSerial Flash Interfacesflash_cs_l 2 O (8 mA-PU) Serial Flash chip selectsflash_q 3 I (8mA-PU) Serial Flash data inputsflash_c 4 O (8 mA-PD) Serial Flash clocksflash_d 5 O (8 mA) Serial Flash data outputUSB Interfaceusb_dmns 71 I/O USB interface port D–usb_dpls 70 I/O USB interface port D+usb_rref 75 O During USB mode, tie this pin in parallel through a 100 pF capacitor and a 4 kΩ resistor to ground. During HSIC mode, tie this pin to a 50Ω resistor to ground.hsic_strb 74 O USB HSIC strobehsic_data 73 I/O USB HSIC datausb_moncdr 68 – For test/diagnostic purposes only.Miscellaneous Signalsrcal_res_ext_core 44 O Reference output, connect to ground via 15k 1% resistor.ext_por 52 I External power-on reset (POR) input. Active low. Allows an optional external power-on reset circuit to be connected. If installed, the external POR will override the internal POR.analog_wlan_iqtest_qp 20 – IQ test pin
12/20/2010 CTJ5MCONFIDENTIAL FOR LG INNOTEK CO LTD Package Signal DescriptionsBROADCOM 2.4 GHz/5 GHz 802.11n MAC/PHY/Radio Chip December 17, 2010 • 43236-DS04-R Page 23®BCM43236 Preliminary Data Sheetanalog_wlan_iqtest_qn 21 – IQ test pinanalog_wlan_iqtest_in 22 – IQ test pinanalog_wlan_iqtest_ip 23 – IQ test pinRF Control Interfacemimophy_core0_ant0_tx 6 O Antenna0 TR Switch controls for core 0. These pins are also used as strapping options, see Table 4 on page 26.mimophy_core0_ant0_rx 7mimophy_core0_ant1_tx 86 O Antenna1 TR Switch controls for core 0. These pins are also used as strapping options, see Table 4 on page 26.mimophy_core0_ant1_rx 87mimophy_core1_ant0_tx 9 O Antenna0 TR Switch controls for core 1. These pins are also used as strapping options, see Table 4.mimophy_core1_ant0_rx 10mimophy_core1_ant1_tx 64 O Antenna1 TR Switch controls for core 1. These pins are also used as strapping options, see Table 4.mimophy_core1_ant1_rx 65RF Signal Interfacerf_5g_antenna_core0 37 I Chain 0 RF receive input, 5 GHz bandrf_5g_antenna_core1 28 I Chain 1 RF receive input, 5 GHz bandrf_2g_antenna_core0 39 I Chain 0 RF receive input, 2.4 GHz bandrf_2g_antenna_core1 30 I Chain 1 RF receive input, 2.4 GHz bandpa_5g_core0 35 O Chain 0 RF transmit output, 5 GHz bandpa_5g_core1 26 O Chain 1 RF transmit output, 5 GHz bandpa_2g_core0 42 O Chain 0 RF transmit output, 2.4 GHz bandpa_2g_core1 33 O Chain 1 RF transmit output, 2.4 GHz bandJTAG Interfacejtag_trst_l 14 I/O JTAG Reset Input. Resets the JTAG Controller. If not used, this pin should be pulled low by a 1 kΩ resistor. This pin is muxed with gpio0.jtag_tck 16 I/O JTAG Test Clock Input. Used to synchronize JTAG control and data transfers. If not used, this pin should be pulled low by a 1 kΩ resistor. This pin is muxed with btcx_rf_active (Bluetooth coexistence output, RF active).jtag_tdi 15 I/O JTAG Test Data Input. Serial data input to the JTAG TAP controller. Sampled on the rising edge of TCK. If not used, it may be left unconnected. This pin is muxed with btcx_tx_conf (Bluetooth coexistence output, WLAN transmit).Table 3: Signal Descriptions (Cont.)Signal BCM43236 Type Description
12/20/2010 CTJ5MCONFIDENTIAL FOR LG INNOTEK CO LTD Package Signal DescriptionsBROADCOM 2.4 GHz/5 GHz 802.11n MAC/PHY/Radio Chip December 17, 2010 • 43236-DS04-R Page 24®BCM43236 Preliminary Data Sheetjtag_tdo 19 I/O JTAG Test Data Output. Serial data output from the JTAG TAP controller. Sampled on the rising edge of TCK. If not used, it may be left unconnected. This pin is muxed with btcx_prisel (Bluetooth coexistence output, antenna select).jtag_tms 18 I/O JTAG Mode Select Input. Single control input to the JTAG TAP controller used to traverse the test logic state machine. Sampled on the rising edge of TCK. If not used, it may be left unconnected. This pin is muxed with btcx_status (Bluetooth coexistence output, status).GPIO Interfacegpio_0 78 I/O (8 mA)General Purpose I/O pin. This pin is tristated on power-up and reset. Subsequently, it becomes an input or an output through software control. A programmable PU or PD resistor is available for each GPIO pin. This pin is muxed with wlan_led (WLAN LED output).gpio_1 79 I/O General Purpose I/O pin. This pin is muxed with mimophy_core0_ant_shd (antenna switch control for the shared [middle] antenna of a 2 of 3 design [core 0]).gpio_2 80 I/O General Purpose I/O pin. This pin is muxed with: • mimophy_core1_ant_shd: antenna switch control for the shared (middle) antenna of a 2 of 3 design (core 1).• btcx_freq: Bluetooth coexistence RF frequencygpio_3 81 I/O General Purpose I/O pin.gpio_4 82 I/O General Purpose I/O pin. This pin is muxed with:• ext_lna_2g_pu_0: 2.4 GHz band core 0 power amplifier control• ext_pa_2g_0: 2.4 GHz band core 0 power amplifier control• CS: SPI selectgpio_5 84 I/O General Purpose I/O pin. This pin is muxed with:• ext_lna_2g_pu_1: 2.4 GHz band core 1 power amplifier control• ext_pa_2g_1: 2.4 GHz band core 1 power amplifier control•SCLK: SPI clock•I2C_SCL: I2C clockTable 3: Signal Descriptions (Cont.)Signal BCM43236 Type Description
12/20/2010 CTJ5MCONFIDENTIAL FOR LG INNOTEK CO LTD Package Signal DescriptionsBROADCOM 2.4 GHz/5 GHz 802.11n MAC/PHY/Radio Chip December 17, 2010 • 43236-DS04-R Page 25®BCM43236 Preliminary Data Sheetgpio_6 85 I/O General Purpose I/O pin. This pin is muxed with:• ext_lna_5g_pu_0: 5 GHz band core 0 power amplifier control• ext_pa_5g_0: 5 GHz band core 0 power amplifier control)• SDI: SPI data inputgpio_7 13 I/O General Purpose I/O pin. This pin is muxed with:• ext_lna_5g_pu_1: 5 GHz band core 1 power amplifier control• ext_pa_5g_1: 5 GHz band core 1 power amplifier control• SDO: SPI data output•I2C_SDA: I2C datagpiao_gpio_pad 43 – No connect; test onlyUART InterfaceUART_RX 62 I/O (4 mA PU) UART receive dataUART_TX 61 I/O (4 mA) UART transmit dataPower and Groundvdd 8, 12, 60, 66, 77, 88PWR 1.2V supply input for the core logic.vddio 1, 11, 63, 83 PWR 3.3V supply input for I/O logic vddio/otp_vdd 76 PWR 3.3V supply input for I/O logic usbavdd2p5 67 PWR USB analog power supplyusbldo_2p5_out 58 PWR USB LDO output; decouple to ground.usb_avdd3p3 69 PWR 3.3V supply input to USB interfaceusbavdd1p2 72 PWR 1.2V supply input to USB interfacesynth_vdd1p2 47 PWR Analog 1.2V supply inputsynth_vco_vdd1p2 46 PWR Analog 1.2V supply inputcore0_vdd1p2 38 PWR Analog 1.2V supply inputcore1_vdd1p2 29 PWR Analog 1.2V supply inputtx_5g_core0_vdd1p2 36 PWR Analog 1.2V supply inputtx_5g_core1_vdd1p2 27 PWR Analog 1.2V supply inputtx_2g_core0_vdd1p2 40 PWR Analog 1.2V supply inputtx_2g_core1_vdd1p2 31 PWR Analog 1.2V supply inputpa_5g_core0_vdd3p3 34 PWR Filtered 3.3V input to internal PApa_5g_core1_vdd3p3 25 PWR Filtered 3.3V input to internal PApa_2g_core0_vdd3p3 41 PWR Filtered 3.3V input to internal PApa_2g_core1_vdd3p3 32 PWR Filtered 3.3V input to internal PAanalog_wlan_iqtest_vdd_1p2 17 PWR 1.2V power supply for IQ test.Table 3: Signal Descriptions (Cont.)Signal BCM43236 Type Description
12/20/2010 CTJ5MCONFIDENTIAL FOR LG INNOTEK CO LTD Strapping OptionsBROADCOM 2.4 GHz/5 GHz 802.11n MAC/PHY/Radio Chip December 17, 2010 • 43236-DS04-R Page 26®BCM43236 Preliminary Data SheetStrapping OptionsThe pins listed in Table 4 are sampled at Power-on Reset (POR) to determine the various operating modes. Sampling occurs within a few milliseconds following internal POR or deassertion of external POR. After POR, each pin assumes the function specified in the signal descriptions table. Each pin has an internal pull-up (PU) or pull-down (PD) resistor that determines the default mode. To change the mode, connect an external PU resistor to VDDIO or a PD resistor to GND; use 10 kΩ or less (refer to the reference board schematics for further details).ldo_3p3_in 57 PWR 3.3V input to RF LDOvddpll/rf_avdd_1p2 59 O XTAL power reference; decouple to ground.vreg3p3_vdd3p3 45 PWR Analog 3.3V supplyi_xtal_vdd2p5/o_xtal_vdd2p5 50 PWR 3.3V supply input for I/O logicvref 56 – VREF; decouple to ground.paref 55 – PA reference; decouple to ground.paref_ctl1 54 – PA reference control 1paref_ctl2 53 – PA reference control 2gnd_slug H GND Groundgnd 24 GND GroundTable 4: Strapping Options Signal Name Mode Default Description mimophy_core0_ant0_tx OTP select PU 0: No OTP1: OTP presentmimophy_core1_ant0_tx SFLASH not presentPD 0: SFLASH not present1: SFLASH presentmimophy_core0_ant0_rx ST SFLASH PD 0: SFLASH type is STMicroelectronics1: SFLASH type is Atmel®mimophy_core0_ant1_tx USB PHY PU 0: HSIC mode1: USB PHY modemimophy_core0_ant1_rx 120 MHz PU 0: Backplane at 96 (98.4) MHz1: Backplane at 120 (123) MHzgpio[7:6] Boot from ROM No pull 00: Remap to RAM; ARM processor to be held at reset.01: Boot from ROM unless the ARM needs to be held at reset.Table 3: Signal Descriptions (Cont.)Signal BCM43236 Type Description
12/20/2010 CTJ5MCONFIDENTIAL FOR LG INNOTEK CO LTD Electrical CharacteristicsBROADCOM 2.4 GHz/5 GHz 802.11n MAC/PHY/Radio Chip December 17, 2010 • 43236-DS04-R Page 27®BCM43236 Preliminary Data SheetSection 5: Electrical CharacteristicsAbsolute Maximum RatingsNote: Values in this data sheet are design goals and are subject to change based on the results of device characterization.Caution! The specifications in Table 5 define levels at which permanent damage to the device can occur. Functional operation is not guaranteed under these conditions. Operation at absolute maximum conditions for extended periods can adversely affect the long-term reliability of the device.Table 5: Absolute Maximum RatingsRating Symbol Minimum Maximum UnitDC supply voltage for core VDDC –0.5 +1.4 VDC supply voltage for I/O VDDO –0.5 +3.8 VVoltage on any input or output pin VIMAX, VIMIN –0.5 +3.8aa. The max voltage requirement is to not exceed VDDO + 0.5V when VDDO < 3.3V.VAmbient Temperature (Operating) TA0+65bb. The temperature above the shield is 65°C for the TJ to be less than 125°C with a Pout of 15 dBm.°COperating Junction Temperature 125°C TJ– 125 °COperating Humidity – – 85 %Storage Temperature TSTG –40 +125 °CStorage Humidity – – 60 %ESD Protection (HBM) VESD – 2000 V
12/20/2010 CTJ5MCONFIDENTIAL FOR LG INNOTEK CO LTD Recommended Operating Conditions and DC CharacteristicsBROADCOM 2.4 GHz/5 GHz 802.11n MAC/PHY/Radio Chip December 17, 2010 • 43236-DS04-R Page 28®BCM43236 Preliminary Data SheetRecommended Operating Conditions and DC CharacteristicsCurrent Consumption from the 3.3V SupplyCurrent Consumption from the 1.2V Supply Table 6: Recommended Operating Conditions and DC CharacteristicsElement SymbolValueUnitMinimum Typical MaximumDC supply voltage for I/O VDDO 2.97 3.3 3.63 VDC supply voltage for core and 1.2V analog VDD12 1.14 1.2 1.26 VInput low voltage (VDDO = 3.3V) VIL ––0.8VInput high voltage (VDDO = 3.3V) VIH 2.0 – – VOutput low voltage VOL ––0.4VOutput high voltage VOH VDDO – 0.4V – – VTable 7: Current Consumption from 3.3V Supply Item Typical Maximum UnitsRadio disabled state 29 48 mAIdle and associated state, PM2 mode 120 148 mAActive state, TX or RX, 40 MHz channel, maximum throughput, PM2 mode462 716 mATable 8: Current Consumption from 1.2V Supply Item Typical Maximum UnitsRadio disabled state 47 68 mAIdle and associated state, PM2 mode 228 296 mAActive state, TX or RX, 40 MHz channel, maximum throughput, PM2 mode510 708 mA
12/20/2010 CTJ5MCONFIDENTIAL FOR LG INNOTEK CO LTD HSIC CharacteristicsBROADCOM 2.4 GHz/5 GHz 802.11n MAC/PHY/Radio Chip December 17, 2010 • 43236-DS04-R Page 29®BCM43236 Preliminary Data SheetHSIC CharacteristicsTable 9: HSIC Characteristics Parameter Symbol Minimum Typical Maximum Unit CommentsHSIC signaling voltage VDD 1.11.21.3V–I/O voltage input low VIL –0.3 – 0.35 × VDD V–I/O Voltage input high VIH 0.65 × VDD –VDD + 0.3 V –I/O voltage output low VOL ––0.25 × VDD V–I/O voltage output high VOH 0.75 × VDD ––V–I/O pad drive strength OD40 – 60 ΩControlled output impedance driverI/O weak keepers IL20 – 70 mA –I/O input impedance ZI100 – – kΩ–Total capacitive loadaa. Total Capacitive Load (CL), includes device Input/Output capacitance, and capacitance of a 50Ω PCB trace with a length of 10 cm.CL3–14pF–Characteristic trace impedanceTI45 50 55 Ω–Circuit board trace length TL––10cm–Circuit board trace propagation skewbb. Maximum propagation delay skew in STROBE or DATA with respect to each other. The trace delay should be matched between STROBE and DATA to ensure that the signal timing is within specification limits at the receiver.TS––15ps–STROBE frequencycc. Jitter and duty cycle are not separately specified parameters: they are incorporated into the values in the table above.FSTROBE 239.988 240 240.012 MHz ± 500 ppmSlew rate (rise and fall) STROBE and DATACTslew 0.60 × VDD 1.0 1.2 V/ns Averaged from 30% ~ 70% pointsReceiver data setup time (with respect to STROBE)cTs300 – – ps Measured at the 50% pointReceiver data hold time (with respect to STROBE)cTb300 – – ps Measured at the 50% point
12/20/2010 CTJ5MCONFIDENTIAL FOR LG INNOTEK CO LTD RF SpecificationsBROADCOM 2.4 GHz/5 GHz 802.11n MAC/PHY/Radio Chip December 17, 2010 • 43236-DS04-R Page 30®BCM43236 Preliminary Data SheetSection 6: RF Specifications2.4 GHz Band General RF SpecificationsNote: Values in this data sheet are design goals and are subject to change based on the results of device characterization.Table 10: 2.4 GHz Band General RF Specifications Item Condition Minimum Typical Maximum UnitaRxTxTurnaroundTime Including switch time – – 2 μs
12/20/2010 CTJ5MCONFIDENTIAL FOR LG INNOTEK CO LTD 2.4 GHz Band Receiver RF SpecificationsBROADCOM 2.4 GHz/5 GHz 802.11n MAC/PHY/Radio Chip December 17, 2010 • 43236-DS04-R Page 31®BCM43236 Preliminary Data Sheet2.4 GHz Band Receiver RF SpecificationsTable 11: 2.4 GHz Band Receiver RF Specifications Characteristic Condition Minimum Typical Maximum UnitCascaded Noise Figure – – 4.5 – dBMaximum Receive Levelaa. When using a suitable external switch.@ 1, 2 Mbps –4 – – dBm@ 5.5, 11 Mbps –10 – – dBm@ 54 Mbps –10 – – dBmInput IP3 Maximum gain – –16 – dBmMinimum gain – –2 – dBmLPF 3 dB Bandwidth – 8 8.5 9 MHzPGA DC Rejection Servo Loop Bandwidth WB mode – 1 – MHzNB mode 120 Hz – 230 kHz –LPF DC Rejection Servo Loop Bandwidth WB mode – 500 – kHzNB mode 120 Hz – 230 kHz –Maximum Receiver Gain – – 88 – dBGain Control Step – – 3 – dB/stepRx Sensitivity(10% PER for 4096 octet PSDU) at WLAN RF port. Defined for default parameters: GF, 800 ns GI, and non-STBC.20 MHz channel spacing for all MCS ratesMCS0 OFDM – –91 – dBmMCS7 OFDM – –74 – dBmMCS8 OFDM – –88.5 – dBmMCS15 OFDM – –69 – dBm40 MHz channel spacing for all MCS ratesMCS0 OFDM – –88 – dBmMCS7 OFDM – –71 – dBmMCS8 OFDM – –85.5 – dBmMCS15 OFDM – –66 – dBm
12/20/2010 CTJ5MCONFIDENTIAL FOR LG INNOTEK CO LTD 2.4 GHz Band Transmitter RF SpecificationsBROADCOM 2.4 GHz/5 GHz 802.11n MAC/PHY/Radio Chip December 17, 2010 • 43236-DS04-R Page 32®BCM43236 Preliminary Data Sheet2.4 GHz Band Transmitter RF Specifications2.4 GHz Band Local Oscillator SpecificationsTable 12: 2.4 GHz Band Transmitter RF Specifications Characteristic Condition Minimum Typical Maximum UnitRF Output Frequency Range – 2400 – 2500 MHzG band 20 MHz BW – – 16 dBm40 MHz BW – – 14.5 dBmCarrier Suppression – 15 – – dBrTX Spectrum mask @ maximum gainfc – 22 MHz < f < fc – 11 MHz – – –30 dBrfc + 11 MHz < f < fc + 22 MHz – – –30 dBrf < fc – 22 MHz; and f > fc + 22 MHz–––50dBrTX Modulation Accuracy (EVM) at maximum gainIEEE 802.11b mode – – 35% –IEEE 802.11g mode – – 5% –Gain Control Step Size – – 0.25 – dB/stepI/Q Baseband Bandwidth IEEE 802.11b mode – 12 – MHzIEEE 802.11g mode – 12 – MHzAmplitude Balanceaa. At a 3 MHz offset from the carrier frequency.DC input –1 – 1 dBPhase BalanceaDC input –1.5 – 1.5 °CBaseband Differential Input VoltageShaped pulse – 0.6 – VppTable 13: 2.4 GHz Band Local Oscillator Specifications Characteristic Condition Minimum Typical Maximum UnitVCO Frequency Range – 2412 – 2484 MHzReference Input Frequency Range – – 20 – MHzClock Frequency Tolerance – – – ±20 ppmReference Spurs – – – –34 dBcLocal Oscillator Phase Noise, single-sided from 1 kHz–300 kHz offset––––86.5dBc/Hz
12/20/2010 CTJ5MCONFIDENTIAL FOR LG INNOTEK CO LTD 5 GHz Band Receiver RF SpecificationsBROADCOM 2.4 GHz/5 GHz 802.11n MAC/PHY/Radio Chip December 17, 2010 • 43236-DS04-R Page 33®BCM43236 Preliminary Data Sheet5 GHz Band Receiver RF SpecificationsTable 14: 5 GHz Band Receiver RF Specificationsa a. With minimum RF gain.Characteristic Condition Minimum Typical Maximum UnitCascaded Noise Figure Maximum RX gain – 4.5 – dBMaximum Receive Levela (5.24 GHz) @ 6 Mbps –10 (TBV) – – dBmMaximum Receive Levela (5.24 GHz) @ 54 Mbps –15 (TBV) – – dBmInput IP3 Maximum LNA gain – –5 – dBmMinimum LNA gain – –4 – dBmLPF 3 dB Bandwidth – – 8.5 – MHzDC Rejection Servo Loop Bandwidth(normal operation)WB mode – 500 – kHzNB mode 120 Hz – 230 kHz –Minimum RX Gain – – 15 – dBMaximum RX Gain – – 92 – dBGain Control Step – – 3 – dB/stepIQ Amplitude Balance – – 0.5 – dBIQ Phase Balance – – 1.5 – °COut-of-Band Blocking Performance without RF Band-Pass Filter (–1 dB desensitization):CW 30 MHz–4300 MHz –10 (TBV) – – dBmCW 4300 MHz–4800 MHz –25 (TBV) – – dBmCW 5900 MHz–6400 MHz –25 (TBV) – – dBmRx Sensitivity(10% PER for 4096 octet PSDU) at WLAN RF port. Defined for default parameters: GF, 800 ns GI, and non-STBC.20 MHz channel spacing for all MCS ratesMCS0 OFDM – –90 – dBmMCS7 OFDM – –74 – dBmMCS8 OFDM – –88.5 – dBmMCS15 OFDM – –69 – dBm40 MHz channel spacing for all MCS ratesMCS0 OFDM – –87 – dBmMCS7 OFDM – –71 – dBmMCS8 OFDM – –86 – dBmMCS15 OFDM – –66 – dBm
12/20/2010 CTJ5MCONFIDENTIAL FOR LG INNOTEK CO LTD 5 GHz Band Transmitter RF SpecificationsBROADCOM 2.4 GHz/5 GHz 802.11n MAC/PHY/Radio Chip December 17, 2010 • 43236-DS04-R Page 34®BCM43236 Preliminary Data Sheet5 GHz Band Transmitter RF Specifications5 GHz Band Local Oscillator Frequency Generator SpecificationsTable 15: 5 GHz Band Transmitter RF Specifications Characteristic Condition Minimum Typical Maximum UnitRF Output Frequency Range – 4920 – 5805 MHzOutput Power (EVM-compliant)20 MHz BW – – 15 dBm40 MHz BW – – 14 dBmCarrier Suppression – – – TBD dBrTX Spectrum mask(chip output power = 11 dBm)f < fc – 11 MHz and f > fc + 11 MHz – – –26 dBcf < fc – 20 MHz and f > fc + 20 MHz – – –35 dBrf < fc – 30 MHz and f > fc + 30 MHz – – –40 dBrTX Modulation Accuracy (EVM) Po = 11 dBm – –25 – dBTX Modulation Accuracy (EVM) Po = 6 dBm – –33 – dBGain Control Step Size – – 2 – dB/stepI/Q Baseband 3 dB Bandwidth – – 12 – MHzAmplitude Balance DC Input –0.5 – 0.5 dBPhase Balance DC Input –1.5 – 1.5 °CBaseband Differential Input Voltage––0.7–VppTX Power Ramp Up 90% of final power – – 2 µsecTX Power Ramp Down 10% of final power – – 2 µsecTable 16: 5 GHz Band Local Oscillator Frequency Generator Specifications Characteristic Condition Minimum Typical Maximum UnitVCO Frequency Range – 4920 – 5805 MHzReference Input Frequency Range – – 20 – MHzClock Frequency Tolerance – – – ±20 ppmReference Spurs – – – –30 dBcLocal Oscillator Integrated Phase Noise (1 kHz–300 kHz)4.920 GHz–5.700 GHz – 0.7 – °C5.725 GHz–5.805 GHz – 1.4 –
12/20/2010 CTJ5MCONFIDENTIAL FOR LG INNOTEK CO LTD On-Chip Regulator Power Supply CharacteristicsBROADCOM 2.4 GHz/5 GHz 802.11n MAC/PHY/Radio Chip December 17, 2010 • 43236-DS04-R Page 35®BCM43236 Preliminary Data SheetOn-Chip Regulator Power Supply CharacteristicsTable 17: On-Chip Regulator Power Supply Characteristics ElementValueUnitMinimum Typical Maximum2.5V–3.1V PA Reference LDO (default: off)Vout: 2.5V to 3.1V when output A, B, C and/or D is enabled.Control Step: 50 mV/stepInput Power Supply 2.97 3.3 3.63 VVout (Note 1) Programmable, 50 mV/step 2.5 2.85 3.1 VAbsolute Accuracy –4 – +4 %Maximum Output Current: A, B, C and D all enabled – – 40 mAMaximum Output Current: any output A, B, C, or D – – 10 mADropout Voltage 150 – – mVStartup Time – – 100 µsSwitching ON Time (either A or G)Note: LDO is already powered.20 30 100 nsSwitching OFF Time (either A or G)Note: LDO is already powered.11.32ns3.3V–1.2V RF LDOInput power supply, Vbat 2.97 3.30 3.63 VVout (Note 1) Programmable, 50 mV/step 1.2 – 3.0 VAbsolute Accuracy –4 – +4 %Dropout Voltage 150 – – mVMaximum Output Current – – 120 mAStartup time with 100 µs VDD Ramp––50µs3.3V–2.5V USB LDOInput power supply 2.97 3.30 3.63 VVout 2.3 2.5 2.65 VAbsolute accuracy –4 – +4 %Dropout voltage 150 – – mVMaximum output current – – 30 mAStart-up time – – 50 µsNote: It is required that the input supply be at least 200 mV higher than the output. More headroom is better for PSRR performance.
12/20/2010 CTJ5MCONFIDENTIAL FOR LG INNOTEK CO LTD Timing CharacteristicsBROADCOM 2.4 GHz/5 GHz 802.11n MAC/PHY/Radio Chip December 17, 2010 • 43236-DS04-R Page 36®BCM43236 Preliminary Data SheetSection 7: Timing CharacteristicsReset and Clock Timing DiagramResets are generated internally by the BCM43236. An optional external Power-On Reset (POR) circuit can be connected to the active-low Ext_por input pin. The BCM43236 is reset automatically as long as the power supplies are turned on in the following sequence. 3.3V first, 2.5V second, and 1.2V last.Figure 9: Timing for the Optional External Power-On ResetTable 18: Ext_por and Clock TimingParameter Description Minimum Typical Maximum Unitst201 OSCIN frequency 19.9995 20.0000 20.0005 MHzt202 OSCIN high time – 20 – nst203 OSCIN low time – 20 – nst204 EXT_POR_L low pulse duration 50 – – mst207 Configuration valid setup to EXT_POR_L rising 50 – – μst208 Configuration valid hold from EXT_POR_L rising 1.7 – 2.8 mst209 EXT_POR_L deassertion to normal switch operation–3–mst210 Reset low hold time after power supplies stabilize50 – – msVccWPLL_CLK25(20 MHz)Ext_porConfigurationStrap Signals Validt201t202t203t204t205t206t207 t208t209t210
12/20/2010 CTJ5MCONFIDENTIAL FOR LG INNOTEK CO LTD Serial Flash Timing DiagramBROADCOM 2.4 GHz/5 GHz 802.11n MAC/PHY/Radio Chip December 17, 2010 • 43236-DS04-R Page 37®BCM43236 Preliminary Data SheetSerial Flash Timing DiagramFigure 10: Serial Flash Timing Diagram (STMicroelectronics-Compatible)Table 19: Serial Flash Timing Parameter Descriptions Minimum Typical Maximum UnitsfSCK Serial flash clock frequency – 12.5 66 MHztWH Serial flash clock high time 9 – – nstWL Serial flash clock low time 9 – – nstR, tFaa. tR and tF are expressed as a slew-rate.Clock rise and fall timesbb. Peak-to-peakTBD – – V/nstCSS Chip select active setup time 5 – – nstCS Chip select deselect time 100 – – nstCSH Chip select hold time 5 – – nstSU Data input setup time 2 – – nstHData input hold time 5 – – nstHO Data output hold time 0 – – nstVClock low to output valid – – 8 nsSFLASH_CS_LSFLASH_CSFLASH_QSFLASH_D High Impedance High ImpedancetCSS tWLtWHtCSHtCStFtHOtVtHtSUVALID ONVALID INtR
12/20/2010 CTJ5MCONFIDENTIAL FOR LG INNOTEK CO LTD Thermal InformationBROADCOM 2.4 GHz/5 GHz 802.11n MAC/PHY/Radio Chip December 17, 2010 • 43236-DS04-R Page 38®BCM43236 Preliminary Data SheetSection 8: Thermal InformationJunction Temperature Estimation and PSIJT Versus ThetaJCPackage thermal characterization parameter Psi-JT (ΨJT) yields a better estimation of actual junction temperature (TJ) versus using the junction-to-case thermal resistance parameter Theta-JC (θJC). The reason for this is θJC assumes that all the power is dissipated through the top surface of the package case. In actual applications, some of the power is dissipated through the bottom and sides of the package. ΨJT takes into account power dissipated through the top, bottom, and sides of the package. The equation for calculating the device junction temperature is as follows: TJ = TT + P ×ΨJTWhere: •TJ = junction temperature at steady-state condition, °C•TT = package case top center temperature at steady-state condition, °C• P = device power dissipation, Watts•ΨJT = package thermal characteristics (no airflow), °C/WPackage thermal characterization measurements: The temperature above the shield is 65°C for the TJ to be less than 125°C with a Pout of 15 dBm.Table 20: 88-Pin QFN Thermal CharacteristicsAirflow0 fpm, 0 mps100 fpm, 0.508 mps200 fpm, 1.016 mps400 fpm, 2.032 mps600 fpm, 3.048 mpsθJA (°C/W) 20.79 17.55 16.24 15.00 14.34θJB (°C/W) 3.95––––θJC (°C/W) 12.44 – – – –ΨJT (°C/W) 3.51 3.50 3.55 3.59 3.61Note: • In the thermal characterizations that were done on the BCM43236 using a 4-layer board, the temperature at 1 mm above the shield must be no higher than 65°C in order to keep the junction temperature (TJ) from exceeding 125°C.• The BCM43236 is designed and rated for operation at a maximum TJ of 125°C.
12/20/2010 CTJ5MCONFIDENTIAL FOR LG INNOTEK CO LTD Package InformationBROADCOM 2.4 GHz/5 GHz 802.11n MAC/PHY/Radio Chip December 17, 2010 • 43236-DS04-R Page 39®BCM43236 Preliminary Data SheetSection 9: Package Information Figure 11: BCM43236 Mechanical Drawing
12/20/2010 CTJ5MCONFIDENTIAL FOR LG INNOTEK CO LTD Ordering InformationBROADCOM 2.4 GHz/5 GHz 802.11n MAC/PHY/Radio Chip December 17, 2010 • 43236-DS04-R Page 40®BCM43236 Preliminary Data SheetSection 10: Ordering Information Table 21: Ordering InformationPart Number Package Temperature @ 1 mm Above the ShieldBCM43236KMLG 10 × 10, 88-pin QFN (RoHs compliant) 0°C to 65°C (32°F to 149°F)
12/20/2010 CTJ5MCONFIDENTIAL FOR LG INNOTEK CO LTD ®Phone: 949-926-5000Fax: 949-926-5203E-mail: info@broadcom.comWeb: www.broadcom.comBROADCOM CORPORATION5300 California AvenueIrvine, CA 92617© 2010 by BROADCOM CORPORATION. All rights reserved.43236-DS04-R December 17, 2010Broadcom® Corporation reserves the right to make changes without further notice to any products or data herein to improve reliability, function, or design.Information furnished by Broadcom Corporation is believed to be accurate and reliable. However, Broadcom Corporation does not assume any liability arising out of the application or use of this information, nor the application or use of any product or circuit described herein, neither does it convey any license under its patent rights nor the rights of others.BCM43236 Preliminary Data Sheet

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